bin/ksh/history.c

46

static uint32_t line_co;

bin/ksh/history.c

554

if (n > 0 && (uint32_t)n != histsize) {

bin/ksh/lex.c

103

uint32_t histsize; /* history size */

bin/ksh/lex.h

112

extern uint32_t histsize; /* history size */

games/arithmetic/arithmetic.c

269

uint32_t penalty[sizeof(keylist) - 1][2];

games/arithmetic/arithmetic.c

272

uint32_t penalty; /* Its penalty. */

games/arithmetic/arithmetic.c

304

getrandom(uint32_t maxval, int op, int operand)

games/arithmetic/arithmetic.c

306

uint32_t value;

games/arithmetic/arithmetic.c

73

int getrandom(uint32_t, int, int);

games/arithmetic/arithmetic.c

85

uint32_t rangemax = 10;

games/atc/update.c

56

uint32_t

games/atc/update.c

65

uint32_t

games/atc/update.c

66

atcrandom_uniform(uint32_t upper_bound)

include/icdb.h

27

struct icdb *icdb_new(uint32_t version, uint32_t nentries, uint32_t entrysize,

include/icdb.h

28

uint32_t nkeys, const uint32_t *keysizes, const uint32_t *keyoffsets);

include/icdb.h

30

struct icdb *icdb_open(const char *name, int flags, uint32_t version);

include/icdb.h

31

int icdb_get(struct icdb *db, void *entry, uint32_t idx);

include/icdb.h

33

uint32_t *idxp);

include/protocols/dumprestore.h

100

uint32_t __uc_gid;

include/protocols/dumprestore.h

77

uint32_t c_inumber; /* number of inode */

include/protocols/dumprestore.h

97

uint32_t __uc_file_flags;

include/protocols/dumprestore.h

99

uint32_t __uc_uid;

include/siphash.h

60

uint32_t bytes;

include/stdlib.h

315

uint32_t arc4random(void);

include/stdlib.h

316

uint32_t arc4random_uniform(uint32_t);

include/uuid.h

54

int32_t uuid_compare(const uuid_t *, const uuid_t *, uint32_t *);

include/uuid.h

55

void uuid_create(uuid_t *, uint32_t *);

include/uuid.h

56

void uuid_create_nil(uuid_t *, uint32_t *);

include/uuid.h

57

int32_t uuid_equal(const uuid_t *, const uuid_t *, uint32_t *);

include/uuid.h

58

void uuid_from_string(const char *, uuid_t *, uint32_t *);

include/uuid.h

59

uint16_t uuid_hash(const uuid_t *, uint32_t *);

include/uuid.h

60

int32_t uuid_is_nil(const uuid_t *, uint32_t *);

include/uuid.h

61

void uuid_to_string(const uuid_t *, char **, uint32_t *);

lib/libagentx/agentx.c

1105

agentx_region(struct agentx_context *axc, uint32_t oid[],

lib/libagentx/agentx.c

1188

uint32_t packetid;

lib/libagentx/agentx.c

123

uint32_t axr_packetid;

lib/libagentx/agentx.c

1274

uint32_t packetid;

lib/libagentx/agentx.c

1422

agentx_index_integer_new(struct agentx_region *axr, uint32_t oid[],

lib/libagentx/agentx.c

1443

agentx_index_integer_any(struct agentx_region *axr, uint32_t oid[],

lib/libagentx/agentx.c

1464

agentx_index_integer_value(struct agentx_region *axr, uint32_t oid[],

lib/libagentx/agentx.c

1495

agentx_index_integer_dynamic(struct agentx_region *axr, uint32_t oid[],

lib/libagentx/agentx.c

1515

agentx_index_string_dynamic(struct agentx_region *axr, uint32_t oid[],

lib/libagentx/agentx.c

1537

agentx_index_nstring_dynamic(struct agentx_region *axr, uint32_t oid[],

lib/libagentx/agentx.c

1571

agentx_index_oid_dynamic(struct agentx_region *axr, uint32_t oid[],

lib/libagentx/agentx.c

1592

agentx_index_noid_dynamic(struct agentx_region *axr, uint32_t oid[],

lib/libagentx/agentx.c

1625

agentx_index_ipaddress_dynamic(struct agentx_region *axr, uint32_t oid[],

lib/libagentx/agentx.c

1690

uint32_t packetid;

lib/libagentx/agentx.c

1890

uint32_t packetid;

lib/libagentx/agentx.c

190

static int agentx_request(struct agentx *, uint32_t,

lib/libagentx/agentx.c

195

static int agentx_oidfill(struct ax_oid *, const uint32_t[], size_t,

lib/libagentx/agentx.c

1995

agentx_object(struct agentx_region *axr, uint32_t oid[], size_t oidlen,

lib/libagentx/agentx.c

2163

uint32_t packetid;

lib/libagentx/agentx.c

2319

uint32_t packetid;

lib/libagentx/agentx.c

2899

if ((uint32_t)index->axv_idata.avb_int32 >

lib/libagentx/agentx.c

2902

else if ((uint32_t)index->axv_idata.avb_int32 <

lib/libagentx/agentx.c

3126

agentx_varbind_oid(struct agentx_varbind *axv, const uint32_t oid[],

lib/libagentx/agentx.c

3183

agentx_varbind_counter32(struct agentx_varbind *axv, uint32_t value)

lib/libagentx/agentx.c

3192

agentx_varbind_gauge32(struct agentx_varbind *axv, uint32_t value)

lib/libagentx/agentx.c

3201

agentx_varbind_unsigned32(struct agentx_varbind *axv, uint32_t value)

lib/libagentx/agentx.c

3207

agentx_varbind_timeticks(struct agentx_varbind *axv, uint32_t value)

lib/libagentx/agentx.c

3565

const uint32_t *

lib/libagentx/agentx.c

3776

struct agentx_index *axi, const uint32_t *value, size_t oidlen)

lib/libagentx/agentx.c

385

agentx_session(struct agentx *ax, uint32_t oid[],

lib/libagentx/agentx.c

3914

agentx_request(struct agentx *ax, uint32_t packetid,

lib/libagentx/agentx.c

3983

agentx_oidfill(struct ax_oid *oid, const uint32_t oidval[], size_t oidlen,

lib/libagentx/agentx.c

451

uint32_t packetid;

lib/libagentx/agentx.c

514

uint32_t packetid;

lib/libagentx/agentx.c

727

uint32_t

lib/libagentx/agentx.c

741

(uint32_t) ((res.tv_sec * 100) + (res.tv_nsec / 10000000));

lib/libagentx/agentx.c

746

const uint32_t oid[], size_t oidlen, int active, int instance)

lib/libagentx/agentx.c

777

const uint32_t oid[], size_t oidlen, int active, int inclusive)

lib/libagentx/agentx.c

880

agentx_agentcaps(struct agentx_context *axc, uint32_t oid[],

lib/libagentx/agentx.c

925

uint32_t packetid;

lib/libagentx/agentx.c

96

uint32_t axo_lock;

lib/libagentx/agentx.c

988

uint32_t packetid;

lib/libagentx/agentx.h

111

void agentx_varbind_oid(struct agentx_varbind *, const uint32_t[],

lib/libagentx/agentx.h

119

void agentx_varbind_counter32(struct agentx_varbind *, uint32_t);

lib/libagentx/agentx.h

120

void agentx_varbind_gauge32(struct agentx_varbind *, uint32_t);

lib/libagentx/agentx.h

121

void agentx_varbind_unsigned32(struct agentx_varbind *, uint32_t);

lib/libagentx/agentx.h

122

void agentx_varbind_timeticks(struct agentx_varbind *, uint32_t);

lib/libagentx/agentx.h

136

const uint32_t *agentx_varbind_get_index_oid(struct agentx_varbind *,

lib/libagentx/agentx.h

147

struct agentx_index *, const uint32_t *, size_t);

lib/libagentx/agentx.h

44

#define AGENTX_OID(...) (uint32_t []) { __VA_ARGS__ }, \

lib/libagentx/agentx.h

45

(sizeof((uint32_t []) { __VA_ARGS__ }) / sizeof(uint32_t))

lib/libagentx/agentx.h

64

uint32_t[], size_t, const char *, uint8_t);

lib/libagentx/agentx.h

69

struct agentx_context *, const uint32_t[], size_t, int, int);

lib/libagentx/agentx.h

71

struct agentx_context *, const uint32_t[], size_t, int, int);

lib/libagentx/agentx.h

72

uint32_t agentx_context_uptime(struct agentx_context *);

lib/libagentx/agentx.h

75

uint32_t[], size_t, const char *);

lib/libagentx/agentx.h

78

uint32_t[], size_t, uint8_t);

lib/libagentx/agentx.h

81

uint32_t[], size_t);

lib/libagentx/agentx.h

83

uint32_t[], size_t);

lib/libagentx/agentx.h

85

uint32_t[], size_t, int32_t);

lib/libagentx/agentx.h

87

struct agentx_region *, uint32_t[], size_t);

lib/libagentx/agentx.h

89

struct agentx_region *, uint32_t[], size_t);

lib/libagentx/agentx.h

91

struct agentx_region *, uint32_t[], size_t, size_t);

lib/libagentx/agentx.h

93

uint32_t[], size_t);

lib/libagentx/agentx.h

95

uint32_t[], size_t, size_t);

lib/libagentx/agentx.h

97

struct agentx_region *, uint32_t[], size_t);

lib/libagentx/agentx.h

99

struct agentx_object *agentx_object(struct agentx_region *, uint32_t[],

lib/libagentx/agentx_internal.h

50

uint32_t axs_id;

lib/libagentx/agentx_internal.h

51

uint32_t axs_timeout;

lib/libagentx/agentx_internal.h

56

uint32_t axs_packetid;

lib/libagentx/agentx_internal.h

65

uint32_t axc_sysuptime;

lib/libagentx/agentx_internal.h

78

uint32_t axg_sessionid;

lib/libagentx/agentx_internal.h

79

uint32_t axg_transactionid;

lib/libagentx/agentx_internal.h

80

uint32_t axg_packetid;

lib/libagentx/ax.c

1012

static uint32_t

lib/libagentx/ax.c

1015

uint32_t packetid, *packetids;

lib/libagentx/ax.c

1062

ax_pdu_add_uint32(struct ax *ax, uint32_t value)

lib/libagentx/ax.c

1217

static uint32_t

lib/libagentx/ax.c

1220

uint32_t value;

lib/libagentx/ax.c

38

enum ax_pdu_type, uint8_t, uint32_t, uint32_t, uint32_t,

lib/libagentx/ax.c

40

static uint32_t ax_packetid(struct ax *);

lib/libagentx/ax.c

400

uint32_t

lib/libagentx/ax.c

41

static uint32_t ax_pdu_queue(struct ax *);

lib/libagentx/ax.c

419

uint32_t

lib/libagentx/ax.c

420

ax_close(struct ax *ax, uint32_t sessionid,

lib/libagentx/ax.c

43

static int ax_pdu_add_uint32(struct ax *, uint32_t);

lib/libagentx/ax.c

436

uint32_t

lib/libagentx/ax.c

437

ax_indexallocate(struct ax *ax, uint8_t flags, uint32_t sessionid,

lib/libagentx/ax.c

455

uint32_t

lib/libagentx/ax.c

456

ax_indexdeallocate(struct ax *ax, uint32_t sessionid,

lib/libagentx/ax.c

469

uint32_t

lib/libagentx/ax.c

470

ax_addagentcaps(struct ax *ax, uint32_t sessionid,

lib/libagentx/ax.c

485

uint32_t

lib/libagentx/ax.c

486

ax_removeagentcaps(struct ax *ax, uint32_t sessionid,

lib/libagentx/ax.c

499

uint32_t

lib/libagentx/ax.c

50

static uint32_t ax_pdutoh32(struct ax_pdu_header *, uint8_t *);

lib/libagentx/ax.c

500

ax_register(struct ax *ax, uint8_t flags, uint32_t sessionid,

lib/libagentx/ax.c

502

uint8_t range_subid, struct ax_oid *subtree, uint32_t upperbound)

lib/libagentx/ax.c

529

uint32_t

lib/libagentx/ax.c

530

ax_unregister(struct ax *ax, uint32_t sessionid,

lib/libagentx/ax.c

532

struct ax_oid *subtree, uint32_t upperbound)

lib/libagentx/ax.c

555

ax_response(struct ax *ax, uint32_t sessionid, uint32_t transactionid,

lib/libagentx/ax.c

556

uint32_t packetid, uint32_t sysuptime, uint16_t error, uint16_t index,

lib/libagentx/ax.c

758

uint32_t upperbound)

lib/libagentx/ax.c

949

ax_oid_add(struct ax_oid *oid, uint32_t value)

lib/libagentx/ax.c

957

static uint32_t

lib/libagentx/ax.c

961

uint32_t packetid, plength;

lib/libagentx/ax.c

978

uint32_t sessionid, uint32_t transactionid, uint32_t packetid,

lib/libagentx/ax.h

125

uint32_t *ax_packetids;

lib/libagentx/ax.h

136

uint32_t aoi_id[AX_OID_MAX_LEN];

lib/libagentx/ax.h

142

uint32_t aos_slen;

lib/libagentx/ax.h

156

uint32_t aph_sessionid;

lib/libagentx/ax.h

157

uint32_t aph_transactionid;

lib/libagentx/ax.h

158

uint32_t aph_packetid;

lib/libagentx/ax.h

159

uint32_t aph_plength;

lib/libagentx/ax.h

167

uint32_t avb_uint32;

lib/libagentx/ax.h

192

uint32_t ap_uptime;

lib/libagentx/ax.h

206

uint32_t ax_open(struct ax *, uint8_t, struct ax_oid *,

lib/libagentx/ax.h

208

uint32_t ax_close(struct ax *, uint32_t, enum ax_close_reason);

lib/libagentx/ax.h

209

uint32_t ax_indexallocate(struct ax *, uint8_t, uint32_t,

lib/libagentx/ax.h

211

uint32_t ax_indexdeallocate(struct ax *, uint32_t,

lib/libagentx/ax.h

213

uint32_t ax_addagentcaps(struct ax *, uint32_t, struct ax_ostring *,

lib/libagentx/ax.h

215

uint32_t ax_removeagentcaps(struct ax *, uint32_t,

lib/libagentx/ax.h

217

uint32_t ax_register(struct ax *, uint8_t, uint32_t,

lib/libagentx/ax.h

219

uint32_t);

lib/libagentx/ax.h

220

uint32_t ax_unregister(struct ax *, uint32_t, struct ax_ostring *,

lib/libagentx/ax.h

221

uint8_t, uint8_t, struct ax_oid *, uint32_t);

lib/libagentx/ax.h

222

int ax_response(struct ax *, uint32_t, uint32_t, uint32_t,

lib/libagentx/ax.h

223

uint32_t, uint16_t, uint16_t, struct ax_varbind *, size_t);

lib/libagentx/ax.h

229

const char *ax_oidrange2string(struct ax_oid *, uint8_t, uint32_t);

lib/libagentx/ax.h

233

int ax_oid_add(struct ax_oid *, uint32_t);

lib/libc/arch/aarch64/gen/_atomic_lock.c

38

uint32_t scratch = 0;

lib/libc/arch/aarch64/gen/fpgetround.c

35

uint32_t fpscr;

lib/libc/arch/aarch64/gen/fpsetround.c

35

uint32_t old, new;

lib/libc/arch/amd64/gen/usertc.c

24

uint32_t hi, lo;

lib/libc/arch/amd64/gen/usertc.c

32

uint32_t hi, lo;

lib/libc/arch/arm/dlfcn/exidx.c

31

uint32_t data[2];

lib/libc/arch/arm/gen/_atomic_lock.c

38

uint32_t scratch = 0;

lib/libc/arch/arm/gen/fpgetround.c

31

uint32_t fpscr;

lib/libc/arch/arm/gen/fpsetround.c

31

uint32_t old, new;

lib/libc/arch/mips64/gen/usertc.c

24

uint32_t count;

lib/libc/arch/riscv64/gen/flt_rounds.c

25

uint32_t frm;

lib/libc/arch/riscv64/gen/fpgetround.c

24

uint32_t frm;

lib/libc/arch/riscv64/gen/fpgetsticky.c

24

uint32_t fflags;

lib/libc/arch/riscv64/gen/fpsetround.c

24

uint32_t frm;

lib/libc/arch/riscv64/gen/fpsetsticky.c

24

uint32_t fflags;

lib/libc/asr/asr_private.h

68

uint32_t rr_ttl;

lib/libc/asr/asr_private.h

86

uint32_t serial;

lib/libc/asr/asr_private.h

87

uint32_t refresh;

lib/libc/asr/asr_private.h

88

uint32_t retry;

lib/libc/asr/asr_private.h

89

uint32_t expire;

lib/libc/asr/asr_private.h

90

uint32_t minimum;

lib/libc/asr/asr_utils.c

211

unpack_u32(struct asr_unpack *p, uint32_t *u32)

lib/libc/asr/asr_utils.c

43

static int unpack_u32(struct asr_unpack *, uint32_t *);

lib/libc/crypt/arc4random.c

172

_rs_random_u32(uint32_t *val)

lib/libc/crypt/arc4random.c

185

uint32_t

lib/libc/crypt/arc4random.c

188

uint32_t val;

lib/libc/crypt/arc4random.c

91

uint32_t rekey_fuzz = 0;

lib/libc/crypt/arc4random_uniform.c

32

uint32_t

lib/libc/crypt/arc4random_uniform.c

33

arc4random_uniform(uint32_t upper_bound)

lib/libc/crypt/arc4random_uniform.c

35

uint32_t r, min;

lib/libc/gdtoa/ldtoa.c

64

uint32_t bits[(LDBL_MANT_DIG + 31) / 32];

lib/libc/locale/___runetype_mb.c

44

uint32_t x;

lib/libc/locale/_wctrans.c

91

uint32_t x;

lib/libc/locale/rune.c

109

re->re_min = ntohl((uint32_t)fre.fre_min);

lib/libc/locale/rune.c

110

re->re_max = ntohl((uint32_t)fre.fre_max);

lib/libc/locale/rune.c

111

re->re_map = ntohl((uint32_t)fre.fre_map);

lib/libc/locale/rune.c

199

uint32_t i;

lib/libc/locale/rune.c

221

uint32_t runetype_nranges, maplower_nranges, mapupper_nranges, var_len;

lib/libc/locale/rune.c

241

var_len = ntohl((uint32_t)frl.frl_variable_len);

lib/libc/locale/rune.c

266

rl->rl_variable_len = ntohl((uint32_t)frl.frl_variable_len);

lib/libc/locale/rune.c

272

rl->rl_maplower[x] = ntohl((uint32_t)frl.frl_maplower[x]);

lib/libc/locale/rune.c

273

rl->rl_mapupper[x] = ntohl((uint32_t)frl.frl_mapupper[x]);

lib/libc/locale/rune.c

82

static int readrange(_RuneLocale *, _RuneRange *, uint32_t, void *, FILE *);

lib/libc/locale/rune.c

86

readrange(_RuneLocale *rl, _RuneRange *rr, uint32_t nranges, void *lastp,

lib/libc/locale/rune.c

89

uint32_t i;

lib/libc/locale/runetype.h

131

uint32_t rr_nranges; /* Number of ranges stored */

lib/libc/locale/runetype.h

43

typedef uint32_t rune_t;

lib/libc/locale/runetype.h

55

typedef uint32_t _RuneType;

lib/libc/locale/runetype.h

90

uint32_t frr_nranges; /* Number of ranges stored */

lib/libc/net/htonl.c

11

uint32_t

lib/libc/net/htonl.c

12

htonl(uint32_t x)

lib/libc/net/ntohl.c

11

uint32_t

lib/libc/net/ntohl.c

12

ntohl(uint32_t x)

lib/libc/stdlib/hcreate.c

158

uint32_t hashval;

lib/libc/stdlib/icdb.c

101

uint32_t allocated;

lib/libc/stdlib/icdb.c

105

static const uint32_t magic = 0x1ca9d0b7;

lib/libc/stdlib/icdb.c

107

static uint32_t

lib/libc/stdlib/icdb.c

108

roundup(uint32_t num)

lib/libc/stdlib/icdb.c

110

uint32_t r = 2;

lib/libc/stdlib/icdb.c

118

icdb_new(uint32_t version, uint32_t nentries, uint32_t entrysize,

lib/libc/stdlib/icdb.c

119

uint32_t nkeys, const uint32_t *keysizes, const uint32_t *keyoffsets)

lib/libc/stdlib/icdb.c

154

icdb_open(const char *name, int flags, uint32_t version)

lib/libc/stdlib/icdb.c

160

uint32_t baseoff, indexsize, idxmask, idxlen;

lib/libc/stdlib/icdb.c

185

idxlen = indexsize * sizeof(uint32_t);

lib/libc/stdlib/icdb.c

208

icdb_get(struct icdb *db, void *entry, uint32_t idx)

lib/libc/stdlib/icdb.c

210

uint32_t entrysize = db->info->entrysize;

lib/libc/stdlib/icdb.c

219

uint32_t *idxp)

lib/libc/stdlib/icdb.c

222

uint32_t offset;

lib/libc/stdlib/icdb.c

224

uint32_t indexsize, idxmask, idxlen;

lib/libc/stdlib/icdb.c

225

uint32_t *idxdata;

lib/libc/stdlib/icdb.c

229

idxlen = indexsize * sizeof(uint32_t);

lib/libc/stdlib/icdb.c

269

uint32_t entrysize = info->entrysize;

lib/libc/stdlib/icdb.c

270

uint32_t baseoff;

lib/libc/stdlib/icdb.c

271

uint32_t indexsize, idxmask, idxlen;

lib/libc/stdlib/icdb.c

275

idxlen = indexsize * sizeof(uint32_t);

lib/libc/stdlib/icdb.c

312

uint32_t entrysize = info->entrysize;

lib/libc/stdlib/icdb.c

313

uint32_t indexsize, idxmask, idxlen;

lib/libc/stdlib/icdb.c

318

idxlen = sizeof(uint32_t) * indexsize;

lib/libc/stdlib/icdb.c

323

uint32_t *idxdata = reallocarray(db->idxdata[i],

lib/libc/stdlib/icdb.c

324

indexsize, sizeof(uint32_t));

lib/libc/stdlib/icdb.c

332

uint32_t *idxdata = db->idxdata[i];

lib/libc/stdlib/icdb.c

349

uint32_t entrysize = info->entrysize;

lib/libc/stdlib/icdb.c

350

uint32_t indexsize, idxlen;

lib/libc/stdlib/icdb.c

357

idxlen = sizeof(uint32_t) * indexsize;

lib/libc/stdlib/icdb.c

81

uint32_t magic; /* magic */

lib/libc/stdlib/icdb.c

82

uint32_t version; /* user specified version */

lib/libc/stdlib/icdb.c

83

uint32_t nentries; /* number of entries stored */

lib/libc/stdlib/icdb.c

84

uint32_t entrysize; /* size of each entry */

lib/libc/stdlib/icdb.c

85

uint32_t indexsize; /* number of entries in hash index */

lib/libc/stdlib/icdb.c

86

uint32_t nkeys; /* number of keys defined */

lib/libc/stdlib/icdb.c

87

uint32_t keysize[8]; /* size of each key */

lib/libc/stdlib/icdb.c

88

uint32_t keyoffset[8]; /* offset of each key in entry */

lib/libc/stdlib/malloc.c

1247

static inline uint32_t

lib/libc/stdlib/malloc.c

1250

uint32_t chunknum;

lib/libc/stdlib/malloc.c

1277

uint32_t chunknum;

lib/libc/stdlib/malloc.c

1278

uint32_t listnum;

lib/libc/stdlib/malloc.c

1606

uint32_t chunknum =

lib/libc/stdlib/malloc.c

1783

uint32_t chunknum;

lib/libc/stdlib/malloc.c

2039

uint32_t chunknum = find_chunknum(pool, info, p, 0);

lib/libc/stdlib/malloc.c

2392

uint32_t chunknum;

lib/libc/string/memmem.c

41

uint32_t nw = n[0]<<24 | n[1]<<16 | n[2]<<8;

lib/libc/string/memmem.c

42

uint32_t hw = h[0]<<24 | h[1]<<16 | h[2]<<8;

lib/libc/string/memmem.c

51

uint32_t nw = n[0]<<24 | n[1]<<16 | n[2]<<8 | n[3];

lib/libc/string/memmem.c

52

uint32_t hw = h[0]<<24 | h[1]<<16 | h[2]<<8 | h[3];

lib/libc/string/strstr.c

40

uint32_t nw = n[0]<<24 | n[1]<<16 | n[2]<<8;

lib/libc/string/strstr.c

41

uint32_t hw = h[0]<<24 | h[1]<<16 | h[2]<<8;

lib/libc/string/strstr.c

49

uint32_t nw = n[0]<<24 | n[1]<<16 | n[2]<<8 | n[3];

lib/libc/string/strstr.c

50

uint32_t hw = h[0]<<24 | h[1]<<16 | h[2]<<8 | h[3];

lib/libc/thread/synch.h

23

_wake(volatile uint32_t *p, int n)

lib/libc/thread/synch.h

29

_twait(volatile uint32_t *p, int val, clockid_t clockid, const struct timespec *abs)

lib/libc/thread/synch.h

60

_requeue(volatile uint32_t *p, int n, int m, volatile uint32_t *q)

lib/libc/uuid/uuid_compare.c

51

uuid_compare(const uuid_t *a, const uuid_t *b, uint32_t *status)

lib/libc/uuid/uuid_create.c

45

uuid_create(uuid_t *u, uint32_t *status)

lib/libc/uuid/uuid_create_nil.c

42

uuid_create_nil(uuid_t *u, uint32_t *status)

lib/libc/uuid/uuid_equal.c

42

uuid_equal(const uuid_t *a, const uuid_t *b, uint32_t *status)

lib/libc/uuid/uuid_from_string.c

48

uuid_from_string(const char *s, uuid_t *u, uint32_t *status)

lib/libc/uuid/uuid_hash.c

41

uuid_hash(const uuid_t *u, uint32_t *status)

lib/libc/uuid/uuid_is_nil.c

42

uuid_is_nil(const uuid_t *u, uint32_t *status)

lib/libc/uuid/uuid_stream.c

107

static __inline uint32_t

lib/libc/uuid/uuid_stream.c

125

be32enc(void *pp, uint32_t u)

lib/libc/uuid/uuid_stream.c

145

le32enc(void *pp, uint32_t u)

lib/libc/uuid/uuid_stream.c

91

static __inline uint32_t

lib/libc/uuid/uuid_to_string.c

47

uuid_to_string(const uuid_t *u, char **s, uint32_t *status)

lib/libcbor/src/cbor/callbacks.c

17

uint32_t _CBOR_UNUSED(_val)) {}

lib/libcbor/src/cbor/callbacks.c

29

uint32_t _CBOR_UNUSED(_val)) {}

lib/libcbor/src/cbor/callbacks.h

117

CBOR_EXPORT void cbor_null_uint32_callback(void *, uint32_t);

lib/libcbor/src/cbor/callbacks.h

129

CBOR_EXPORT void cbor_null_negint32_callback(void *, uint32_t);

lib/libcbor/src/cbor/callbacks.h

27

typedef void (*cbor_int32_callback)(void *, uint32_t);

lib/libcbor/src/cbor/data.h

149

uint32_t as_uint;

lib/libcbor/src/cbor/encoding.c

130

uint32_t val = ((union _cbor_float_helper){.as_float = value}).as_uint;

lib/libcbor/src/cbor/encoding.c

134

uint32_t mant =

lib/libcbor/src/cbor/encoding.c

21

size_t cbor_encode_uint32(uint32_t value, unsigned char *buffer,

lib/libcbor/src/cbor/encoding.c

46

size_t cbor_encode_negint32(uint32_t value, unsigned char *buffer,

lib/libcbor/src/cbor/encoding.h

36

_CBOR_NODISCARD CBOR_EXPORT size_t cbor_encode_uint32(uint32_t, unsigned char *,

lib/libcbor/src/cbor/encoding.h

52

_CBOR_NODISCARD CBOR_EXPORT size_t cbor_encode_negint32(uint32_t,

lib/libcbor/src/cbor/internal/builder_callbacks.c

160

void cbor_builder_uint32_callback(void *context, uint32_t value) {

lib/libcbor/src/cbor/internal/builder_callbacks.c

196

void cbor_builder_negint32_callback(void *context, uint32_t value) {

lib/libcbor/src/cbor/internal/builder_callbacks.h

37

void cbor_builder_uint32_callback(void *, uint32_t);

lib/libcbor/src/cbor/internal/builder_callbacks.h

45

void cbor_builder_negint32_callback(void *, uint32_t);

lib/libcbor/src/cbor/internal/encoders.c

45

size_t _cbor_encode_uint32(uint32_t value, unsigned char *buffer,

lib/libcbor/src/cbor/internal/encoders.c

95

return _cbor_encode_uint32((uint32_t)value, buffer, buffer_size, offset);

lib/libcbor/src/cbor/internal/encoders.h

26

size_t _cbor_encode_uint32(uint32_t value, unsigned char *buffer,

lib/libcbor/src/cbor/internal/loaders.c

24

uint32_t _cbor_load_uint32(const unsigned char *source) {

lib/libcbor/src/cbor/internal/loaders.c

26

uint32_t result;

lib/libcbor/src/cbor/internal/loaders.c

30

return ((uint32_t) * (source + 0) << 0x18) +

lib/libcbor/src/cbor/internal/loaders.c

31

((uint32_t) * (source + 1) << 0x10) +

lib/libcbor/src/cbor/internal/loaders.c

46

((uint32_t) * (source + 4) << 0x18) +

lib/libcbor/src/cbor/internal/loaders.c

47

((uint32_t) * (source + 5) << 0x10) +

lib/libcbor/src/cbor/internal/loaders.h

25

uint32_t _cbor_load_uint32(const unsigned char *source);

lib/libcbor/src/cbor/internal/unicode.c

59

uint32_t _cbor_unicode_decode(uint32_t* state, uint32_t* codep, uint32_t byte) {

lib/libcbor/src/cbor/internal/unicode.c

60

uint32_t type = utf8d[byte];

lib/libcbor/src/cbor/internal/unicode.c

73

uint32_t codepoint, state = UTF8_ACCEPT, res;

lib/libcbor/src/cbor/ints.c

144

cbor_item_t *cbor_build_uint32(uint32_t value) {

lib/libcbor/src/cbor/ints.c

176

cbor_item_t *cbor_build_negint32(uint32_t value) {

lib/libcbor/src/cbor/ints.c

27

uint32_t cbor_get_uint32(const cbor_item_t *item) {

lib/libcbor/src/cbor/ints.c

30

return *(uint32_t *)item->data;

lib/libcbor/src/cbor/ints.c

66

void cbor_set_uint32(cbor_item_t *item, uint32_t value) {

lib/libcbor/src/cbor/ints.c

69

*(uint32_t *)item->data = value;

lib/libcbor/src/cbor/ints.h

170

_CBOR_NODISCARD CBOR_EXPORT cbor_item_t *cbor_build_uint32(uint32_t value);

lib/libcbor/src/cbor/ints.h

198

_CBOR_NODISCARD CBOR_EXPORT cbor_item_t *cbor_build_negint32(uint32_t value);

lib/libcbor/src/cbor/ints.h

43

_CBOR_NODISCARD CBOR_EXPORT uint32_t cbor_get_uint32(const cbor_item_t *item);

lib/libcbor/src/cbor/ints.h

81

CBOR_EXPORT void cbor_set_uint32(cbor_item_t *item, uint32_t value);

lib/libcrypto/aes/aes.c

277

uint32_t ctr;

lib/libcrypto/aes/aes_core.c

1016

const uint32_t *rk;

lib/libcrypto/aes/aes_core.c

1017

uint32_t s0, s1, s2, s3, t0, t1, t2, t3;

lib/libcrypto/aes/aes_core.c

1170

(((uint32_t)Td4[(t0 >> 24)]) << 24) ^

lib/libcrypto/aes/aes_core.c

1177

(((uint32_t)Td4[(t1 >> 24)]) << 24) ^

lib/libcrypto/aes/aes_core.c

1184

(((uint32_t)Td4[(t2 >> 24)]) << 24) ^

lib/libcrypto/aes/aes_core.c

1191

(((uint32_t)Td4[(t3 >> 24)]) << 24) ^

lib/libcrypto/aes/aes_core.c

124

static const uint32_t Te1[256] = {

lib/libcrypto/aes/aes_core.c

190

static const uint32_t Te2[256] = {

lib/libcrypto/aes/aes_core.c

256

static const uint32_t Te3[256] = {

lib/libcrypto/aes/aes_core.c

323

static const uint32_t Td0[256] = {

lib/libcrypto/aes/aes_core.c

389

static const uint32_t Td1[256] = {

lib/libcrypto/aes/aes_core.c

455

static const uint32_t Td2[256] = {

lib/libcrypto/aes/aes_core.c

521

static const uint32_t Td3[256] = {

lib/libcrypto/aes/aes_core.c

58

static const uint32_t Te0[256] = {

lib/libcrypto/aes/aes_core.c

629

static const uint32_t rcon[] = {

lib/libcrypto/aes/aes_core.c

644

uint32_t *rk;

lib/libcrypto/aes/aes_core.c

646

uint32_t temp;

lib/libcrypto/aes/aes_core.c

745

uint32_t *rk;

lib/libcrypto/aes/aes_core.c

746

uint32_t temp;

lib/libcrypto/aes/aes_core.c

815

const uint32_t *rk;

lib/libcrypto/aes/aes_core.c

816

uint32_t s0, s1, s2, s3, t0, t1, t2, t3;

lib/libcrypto/arch/amd64/crypto_cpu_caps.c

35

cpuid(uint32_t eax, uint32_t *out_eax, uint32_t *out_ebx, uint32_t *out_ecx,

lib/libcrypto/arch/amd64/crypto_cpu_caps.c

36

uint32_t *out_edx)

lib/libcrypto/arch/amd64/crypto_cpu_caps.c

38

uint32_t ebx = 0, ecx = 0, edx = 0;

lib/libcrypto/arch/amd64/crypto_cpu_caps.c

57

xgetbv(uint32_t ecx, uint32_t *out_eax, uint32_t *out_edx)

lib/libcrypto/arch/amd64/crypto_cpu_caps.c

59

uint32_t eax = 0, edx = 0;

lib/libcrypto/arch/amd64/crypto_cpu_caps.c

74

uint32_t eax, ebx, ecx, edx, max_cpuid;

lib/libcrypto/arch/i386/crypto_cpu_caps.c

35

cpuid(uint32_t eax, uint32_t *out_eax, uint32_t *out_ebx, uint32_t *out_ecx,

lib/libcrypto/arch/i386/crypto_cpu_caps.c

36

uint32_t *out_edx)

lib/libcrypto/arch/i386/crypto_cpu_caps.c

38

uint32_t ebx = 0, ecx = 0, edx = 0;

lib/libcrypto/arch/i386/crypto_cpu_caps.c

57

xgetbv(uint32_t ecx, uint32_t *out_eax, uint32_t *out_edx)

lib/libcrypto/arch/i386/crypto_cpu_caps.c

59

uint32_t eax = 0, edx = 0;

lib/libcrypto/arch/i386/crypto_cpu_caps.c

74

uint32_t eax, ebx, ecx, edx;

lib/libcrypto/asn1/a_object.c

654

uint32_t tag_number;

lib/libcrypto/asn1/asn1_lib.c

142

int *out_constructed, uint32_t *out_tag_number, int *out_indefinite,

lib/libcrypto/asn1/asn1_lib.c

146

uint32_t tag_number;

lib/libcrypto/asn1/asn1_lib.c

176

asn1_get_primitive(CBS *cbs, int der_mode, uint32_t *out_tag_number,

lib/libcrypto/asn1/asn1_lib.c

180

uint32_t tag_number;

lib/libcrypto/asn1/asn1_lib.c

25

int *out_constructed, uint32_t *out_tag_number)

lib/libcrypto/asn1/asn1_lib.c

29

uint32_t tag_number;

lib/libcrypto/asn1/asn1_local.h

128

int *out_constructed, uint32_t *out_tag_number);

lib/libcrypto/asn1/asn1_local.h

132

int *out_constructed, uint32_t *out_tag_number, int *out_indefinite,

lib/libcrypto/asn1/asn1_local.h

134

int asn1_get_primitive(CBS *cbs, int der_mode, uint32_t *out_tag_number,

lib/libcrypto/asn1/asn1_old_lib.c

75

uint32_t tag_number;

lib/libcrypto/asn1/asn1_types.c

27

uint32_t bit_value;

lib/libcrypto/asn1/tasn_dec.c

110

uint32_t tag_number;

lib/libcrypto/bio/b_sock.c

47

uint32_t *iap = (in_addr_t *)ip;

lib/libcrypto/bio/b_sock.c

62

*iap = (uint32_t)(((struct sockaddr_in *)(res->ai_addr))->sin_addr.s_addr);

lib/libcrypto/bn/bn.h

151

#define BN_ULONG uint32_t

lib/libcrypto/bn/bn_convert.c

731

uint32_t mpi_len;

lib/libcrypto/bytestring/bs_cbb.c

130

cbb_add_u(CBB *cbb, uint32_t v, size_t len_len)

lib/libcrypto/bytestring/bs_cbb.c

396

return cbb_add_u(cbb, (uint32_t)value, 1);

lib/libcrypto/bytestring/bs_cbb.c

405

return cbb_add_u(cbb, (uint32_t)value, 2);

lib/libcrypto/bytestring/bs_cbb.c

414

return cbb_add_u(cbb, (uint32_t)value, 3);

lib/libcrypto/bytestring/bs_cbb.c

423

return cbb_add_u(cbb, (uint32_t)value, 4);

lib/libcrypto/bytestring/bs_cbb.c

429

uint32_t a, b;

lib/libcrypto/bytestring/bs_cbs.c

148

cbs_get_u(CBS *cbs, uint32_t *out, size_t len)

lib/libcrypto/bytestring/bs_cbs.c

150

uint32_t result = 0;

lib/libcrypto/bytestring/bs_cbs.c

183

uint32_t v;

lib/libcrypto/bytestring/bs_cbs.c

193

CBS_get_u24(CBS *cbs, uint32_t *out)

lib/libcrypto/bytestring/bs_cbs.c

199

CBS_get_u32(CBS *cbs, uint32_t *out)

lib/libcrypto/bytestring/bs_cbs.c

207

uint32_t a, b;

lib/libcrypto/bytestring/bs_cbs.c

247

uint32_t len;

lib/libcrypto/bytestring/bs_cbs.c

274

cbs_peek_u(CBS *cbs, uint32_t *out, size_t len)

lib/libcrypto/bytestring/bs_cbs.c

276

uint32_t result = 0;

lib/libcrypto/bytestring/bs_cbs.c

309

uint32_t v;

lib/libcrypto/bytestring/bs_cbs.c

319

CBS_peek_u24(CBS *cbs, uint32_t *out)

lib/libcrypto/bytestring/bs_cbs.c

325

CBS_peek_u32(CBS *cbs, uint32_t *out)

lib/libcrypto/bytestring/bs_cbs.c

392

uint32_t len32;

lib/libcrypto/bytestring/bytestring.h

126

int CBS_get_u24(CBS *cbs, uint32_t *out);

lib/libcrypto/bytestring/bytestring.h

132

int CBS_get_u32(CBS *cbs, uint32_t *out);

lib/libcrypto/bytestring/bytestring.h

189

int CBS_peek_u24(CBS *cbs, uint32_t *out);

lib/libcrypto/bytestring/bytestring.h

195

int CBS_peek_u32(CBS *cbs, uint32_t *out);

lib/libcrypto/chacha/chacha-merged.c

17

typedef uint32_t u32;

lib/libcrypto/chacha/chacha-merged.c

282

uint32_t x[16];

lib/libcrypto/chacha/chacha.c

25

ChaCha_set_key(ChaCha_ctx *ctx, const unsigned char *key, uint32_t keybits)

lib/libcrypto/chacha/chacha.c

62

chacha_encrypt_bytes((chacha_ctx *)ctx, in, out, (uint32_t)n);

lib/libcrypto/chacha/chacha.c

86

ctx.input[12] = (uint32_t)counter;

lib/libcrypto/chacha/chacha.c

87

ctx.input[13] = (uint32_t)(counter >> 32);

lib/libcrypto/chacha/chacha.c

94

chacha_encrypt_bytes(&ctx, in, out, (uint32_t)n);

lib/libcrypto/crypto_internal.h

172

static inline uint32_t

lib/libcrypto/crypto_internal.h

175

uint32_t v;

lib/libcrypto/crypto_internal.h

190

crypto_store_htobe32(uint8_t *dst, uint32_t v)

lib/libcrypto/crypto_internal.h

234

static inline uint32_t

lib/libcrypto/crypto_internal.h

237

uint32_t v;

lib/libcrypto/crypto_internal.h

252

crypto_store_htole32(uint8_t *dst, uint32_t v)

lib/libcrypto/crypto_internal.h

261

crypto_add_u32dw_u64(uint32_t *h, uint32_t *l, uint64_t v)

lib/libcrypto/crypto_internal.h

270

static inline uint32_t

lib/libcrypto/crypto_internal.h

271

crypto_rol_u32(uint32_t v, size_t shift)

lib/libcrypto/crypto_internal.h

278

static inline uint32_t

lib/libcrypto/crypto_internal.h

279

crypto_ror_u32(uint32_t v, size_t shift)

lib/libcrypto/curve25519/curve25519.c

1187

uint32_t y = x; /* 0: yes; 1..255: no */

lib/libcrypto/curve25519/curve25519.c

176

s[3] = (h0 >> 24) | ((uint32_t)(h1) << 2);

lib/libcrypto/curve25519/curve25519.c

179

s[6] = (h1 >> 22) | ((uint32_t)(h2) << 3);

lib/libcrypto/curve25519/curve25519.c

182

s[9] = (h2 >> 21) | ((uint32_t)(h3) << 5);

lib/libcrypto/curve25519/curve25519.c

185

s[12] = (h3 >> 19) | ((uint32_t)(h4) << 6);

lib/libcrypto/curve25519/curve25519.c

192

s[19] = (h5 >> 24) | ((uint32_t)(h6) << 1);

lib/libcrypto/curve25519/curve25519.c

195

s[22] = (h6 >> 23) | ((uint32_t)(h7) << 3);

lib/libcrypto/curve25519/curve25519.c

198

s[25] = (h7 >> 21) | ((uint32_t)(h8) << 4);

lib/libcrypto/curve25519/curve25519.c

201

s[28] = (h8 >> 20) | ((uint32_t)(h9) << 6);

lib/libcrypto/curve25519/curve25519.c

3467

uint32_t x = b;

lib/libcrypto/des/des_local.h

118

static inline uint32_t

lib/libcrypto/des/des_local.h

119

ROTATE(uint32_t a, uint32_t n)

lib/libcrypto/ec/ecx_methods.c

514

int *security_bits, uint32_t *flags)

lib/libcrypto/evp/e_chacha20poly1305.c

147

ctr = (uint64_t)((uint32_t)(nonce[0]) | (uint32_t)(nonce[1]) << 8 |

lib/libcrypto/evp/e_chacha20poly1305.c

148

(uint32_t)(nonce[2]) << 16 | (uint32_t)(nonce[3]) << 24) << 32;

lib/libcrypto/evp/e_chacha20poly1305.c

206

ctr = (uint64_t)((uint32_t)(nonce[0]) | (uint32_t)(nonce[1]) << 8 |

lib/libcrypto/evp/e_chacha20poly1305.c

207

(uint32_t)(nonce[2]) << 16 | (uint32_t)(nonce[3]) << 24) << 32;

lib/libcrypto/evp/e_chacha20poly1305.c

452

ctr = (uint64_t)((uint32_t)(cpx->nonce[0]) |

lib/libcrypto/evp/e_chacha20poly1305.c

453

(uint32_t)(cpx->nonce[1]) << 8 |

lib/libcrypto/evp/e_chacha20poly1305.c

454

(uint32_t)(cpx->nonce[2]) << 16 |

lib/libcrypto/evp/e_chacha20poly1305.c

455

(uint32_t)(cpx->nonce[3]) << 24) << 32;

lib/libcrypto/evp/e_chacha20poly1305.c

462

cpx->chacha.input[12] = (uint32_t)ctr;

lib/libcrypto/evp/e_chacha20poly1305.c

463

cpx->chacha.input[13] = (uint32_t)(ctr >> 32);

lib/libcrypto/evp/evp_local.h

116

int *out_pkey_nid, int *out_security_bits, uint32_t *out_flags);

lib/libcrypto/md4/md4.c

100

uint32_t s)

lib/libcrypto/md4/md4.c

106

md4_round3(uint32_t *a, uint32_t b, uint32_t c, uint32_t d, uint32_t x,

lib/libcrypto/md4/md4.c

107

uint32_t s)

lib/libcrypto/md4/md4.c

71

CTASSERT(sizeof(MD4_LONG) == sizeof(uint32_t));

lib/libcrypto/md4/md4.c

73

static inline uint32_t

lib/libcrypto/md4/md4.c

74

md4_f(uint32_t x, uint32_t y, uint32_t z)

lib/libcrypto/md4/md4.c

79

static inline uint32_t

lib/libcrypto/md4/md4.c

80

md4_g(uint32_t x, uint32_t y, uint32_t z)

lib/libcrypto/md4/md4.c

85

static inline uint32_t

lib/libcrypto/md4/md4.c

86

md4_h(uint32_t x, uint32_t y, uint32_t z)

lib/libcrypto/md4/md4.c

92

md4_round1(uint32_t *a, uint32_t b, uint32_t c, uint32_t d, uint32_t x,

lib/libcrypto/md4/md4.c

93

uint32_t s)

lib/libcrypto/md4/md4.c

99

md4_round2(uint32_t *a, uint32_t b, uint32_t c, uint32_t d, uint32_t x,

lib/libcrypto/md5/md5.c

103

md5_round1(uint32_t *a, uint32_t b, uint32_t c, uint32_t d, uint32_t x,

lib/libcrypto/md5/md5.c

104

uint32_t t, uint32_t s)

lib/libcrypto/md5/md5.c

110

md5_round2(uint32_t *a, uint32_t b, uint32_t c, uint32_t d, uint32_t x,

lib/libcrypto/md5/md5.c

111

uint32_t t, uint32_t s)

lib/libcrypto/md5/md5.c

117

md5_round3(uint32_t *a, uint32_t b, uint32_t c, uint32_t d, uint32_t x,

lib/libcrypto/md5/md5.c

118

uint32_t t, uint32_t s)

lib/libcrypto/md5/md5.c

124

md5_round4(uint32_t *a, uint32_t b, uint32_t c, uint32_t d, uint32_t x,

lib/libcrypto/md5/md5.c

125

uint32_t t, uint32_t s)

lib/libcrypto/md5/md5.c

71

CTASSERT(sizeof(MD5_LONG) == sizeof(uint32_t));

lib/libcrypto/md5/md5.c

78

static inline uint32_t

lib/libcrypto/md5/md5.c

79

md5_F(uint32_t x, uint32_t y, uint32_t z)

lib/libcrypto/md5/md5.c

84

static inline uint32_t

lib/libcrypto/md5/md5.c

85

md5_G(uint32_t x, uint32_t y, uint32_t z)

lib/libcrypto/md5/md5.c

90

static inline uint32_t

lib/libcrypto/md5/md5.c

91

md5_H(uint32_t x, uint32_t y, uint32_t z)

lib/libcrypto/md5/md5.c

96

static inline uint32_t

lib/libcrypto/md5/md5.c

97

md5_I(uint32_t x, uint32_t y, uint32_t z)

lib/libcrypto/mlkem/mlkem_internal.c

220

reduce(uint32_t x)

lib/libcrypto/mlkem/mlkem_internal.c

223

uint32_t quotient = (uint32_t)(product >> kBarrettShift);

lib/libcrypto/mlkem/mlkem_internal.c

224

uint32_t remainder = x - quotient * kPrime;

lib/libcrypto/mlkem/mlkem_internal.c

264

const uint32_t step_root = kNTTRoots[i + step];

lib/libcrypto/mlkem/mlkem_internal.c

310

uint32_t step_root = kInverseNTTRoots[i + step];

lib/libcrypto/mlkem/mlkem_internal.c

373

uint32_t real_real = (uint32_t)lhs->c[2 * i] * rhs->c[2 * i];

lib/libcrypto/mlkem/mlkem_internal.c

374

uint32_t img_img = (uint32_t)lhs->c[2 * i + 1] *

lib/libcrypto/mlkem/mlkem_internal.c

376

uint32_t real_img = (uint32_t)lhs->c[2 * i] * rhs->c[2 * i + 1];

lib/libcrypto/mlkem/mlkem_internal.c

377

uint32_t img_real = (uint32_t)lhs->c[2 * i + 1] * rhs->c[2 * i];

lib/libcrypto/mlkem/mlkem_internal.c

381

(uint32_t)reduce(img_img) * kModRoots[i]);

lib/libcrypto/mlkem/mlkem_internal.c

738

uint32_t shifted = (uint32_t)x << bits;

lib/libcrypto/mlkem/mlkem_internal.c

740

uint32_t quotient = (uint32_t)(product >> kBarrettShift);

lib/libcrypto/mlkem/mlkem_internal.c

741

uint32_t remainder = shifted - quotient * kPrime;

lib/libcrypto/mlkem/mlkem_internal.c

763

uint32_t product = (uint32_t)x * kPrime;

lib/libcrypto/mlkem/mlkem_internal.c

764

uint32_t power = 1 << bits;

lib/libcrypto/mlkem/mlkem_internal.c

766

uint32_t remainder = product & (power - 1);

lib/libcrypto/mlkem/mlkem_internal.c

768

uint32_t lower = product >> bits;

lib/libcrypto/modes/ctr128.c

178

uint32_t n = 12;

lib/libcrypto/modes/ctr128.c

226

ctr32 += (uint32_t)blocks;

lib/libcrypto/modes/ctr128.c

66

uint32_t n = 16;

lib/libcrypto/modes/modes_local.h

36

uint32_t d[4];

lib/libcrypto/modes/xts128.c

65

uint32_t d[4];

lib/libcrypto/ripemd/ripemd.c

71

CTASSERT(sizeof(RIPEMD160_LONG) == sizeof(uint32_t));

lib/libcrypto/rsa/rsa_ameth.c

857

int *out_pkey_nid, int *out_security_bits, uint32_t *out_flags)

lib/libcrypto/rsa/rsa_ameth.c

865

uint32_t flags = 0;

lib/libcrypto/sha/sha1.c

72

CTASSERT(sizeof(SHA_LONG) == sizeof(uint32_t));

lib/libcrypto/sha/sha256.c

69

CTASSERT(sizeof(SHA_LONG) == sizeof(uint32_t));

lib/libcrypto/sm2/sm2_crypt.c

187

uint32_t ctr = 1;

lib/libcrypto/sm3/sm3.c

27

CTASSERT(sizeof(SM3_WORD) == sizeof(uint32_t));

lib/libcrypto/sm4/sm4.c

103

static inline uint32_t

lib/libcrypto/sm4/sm4.c

104

SM4_T_slow(uint32_t X)

lib/libcrypto/sm4/sm4.c

106

uint32_t t = 0;

lib/libcrypto/sm4/sm4.c

108

t |= ((uint32_t)SM4_S[(uint8_t)(X >> 24)]) << 24;

lib/libcrypto/sm4/sm4.c

109

t |= ((uint32_t)SM4_S[(uint8_t)(X >> 16)]) << 16;

lib/libcrypto/sm4/sm4.c

110

t |= ((uint32_t)SM4_S[(uint8_t)(X >> 8)]) << 8;

lib/libcrypto/sm4/sm4.c

118

static inline uint32_t

lib/libcrypto/sm4/sm4.c

119

SM4_T(uint32_t X)

lib/libcrypto/sm4/sm4.c

130

static const uint32_t SM4_FK[4] = {

lib/libcrypto/sm4/sm4.c

137

static const uint32_t SM4_CK[32] = {

lib/libcrypto/sm4/sm4.c

152

uint32_t K[4];

lib/libcrypto/sm4/sm4.c

161

uint32_t X;

lib/libcrypto/sm4/sm4.c

162

uint32_t t = 0;

lib/libcrypto/sm4/sm4.c

166

t |= ((uint32_t)SM4_S[(uint8_t)(X >> 24)]) << 24;

lib/libcrypto/sm4/sm4.c

167

t |= ((uint32_t)SM4_S[(uint8_t)(X >> 16)]) << 16;

lib/libcrypto/sm4/sm4.c

168

t |= ((uint32_t)SM4_S[(uint8_t)(X >> 8)]) << 8;

lib/libcrypto/sm4/sm4.c

184

uint32_t B0, B1, B2, B3;

lib/libcrypto/sm4/sm4.c

246

uint32_t B0, B1, B2, B3;

lib/libcrypto/sm4/sm4.c

26

uint32_t rk[SM4_KEY_SCHEDULE];

lib/libcrypto/sm4/sm4.c

57

static const uint32_t SM4_SBOX_T[256] = {

lib/libcrypto/x509/x509.h

596

uint32_t *flags);

lib/libcrypto/x509/x509_addr.c

886

make_addressPrefix(IPAddressOrRange **out_aor, uint8_t *addr, uint32_t afi,

lib/libcrypto/x509/x509_addr.c

965

uint32_t afi, int length)

lib/libcrypto/x509/x509_purp.c

892

uint32_t

lib/libcrypto/x509/x509_purp.c

903

uint32_t

lib/libcrypto/x509/x509_purp.c

917

uint32_t

lib/libcrypto/x509/x509_siginfo.c

45

int *out_security_bits, uint32_t *out_flags)

lib/libcrypto/x509/x509_siginfo.c

49

uint32_t flags = 0;

lib/libcrypto/x509/x509v3.h

668

uint32_t X509_get_extension_flags(X509 *x);

lib/libcrypto/x509/x509v3.h

669

uint32_t X509_get_key_usage(X509 *x);

lib/libcrypto/x509/x509v3.h

670

uint32_t X509_get_extended_key_usage(X509 *x);

lib/libcurses/curses.h

227

typedef uint32_t chtype;

lib/libcurses/curses.h

228

typedef uint32_t mmask_t;

lib/libelf/_libelf.h

237

int _libelf_xlate_shtype(uint32_t _sht);

lib/libelf/elf_data.c

219

uint32_t sh_type;

lib/libelf/elf_update.c

115

uint32_t sh_type;

lib/libelf/elf_update.c

322

shdr32->sh_addralign = (uint32_t) sh_align;

lib/libelf/elf_update.c

323

shdr32->sh_entsize = (uint32_t) sh_entsize;

lib/libelf/elf_update.c

324

shdr32->sh_offset = (uint32_t) sh_offset;

lib/libelf/elf_update.c

325

shdr32->sh_size = (uint32_t) sh_size;

lib/libelf/elf_update.c

702

eh32->e_phoff = (uint32_t) phoff;

lib/libelf/elf_update.c

703

eh32->e_shoff = (uint32_t) shoff;

lib/libelf/elf_update.c

725

uint32_t sh_type;

lib/libelf/gelf_cap.c

104

uint32_t sh_type;

lib/libelf/gelf_cap.c

45

uint32_t sh_type;

lib/libelf/gelf_dyn.c

105

uint32_t sh_type;

lib/libelf/gelf_dyn.c

45

uint32_t sh_type;

lib/libelf/gelf_move.c

106

uint32_t sh_type;

lib/libelf/gelf_move.c

43

uint32_t sh_type;

lib/libelf/gelf_rel.c

105

uint32_t sh_type;

lib/libelf/gelf_rel.c

43

uint32_t sh_type;

lib/libelf/gelf_rela.c

106

uint32_t sh_type;

lib/libelf/gelf_rela.c

43

uint32_t sh_type;

lib/libelf/gelf_sym.c

105

uint32_t sh_type;

lib/libelf/gelf_sym.c

43

uint32_t sh_type;

lib/libelf/gelf_syminfo.c

102

uint32_t sh_type;

lib/libelf/gelf_syminfo.c

41

uint32_t sh_type;

lib/libelf/gelf_symshndx.c

42

uint32_t sh_type;

lib/libelf/gelf_symshndx.c

95

uint32_t sh_type;

lib/libelf/libelf.h

150

uint32_t gh_nbuckets; /* Number of hash buckets. */

lib/libelf/libelf.h

151

uint32_t gh_symndx; /* First visible symbol in .dynsym. */

lib/libelf/libelf.h

152

uint32_t gh_maskwords; /* #maskwords used in bloom filter. */

lib/libelf/libelf.h

153

uint32_t gh_shift2; /* Bloom filter shift count. */

lib/libelf/libelf_ar.c

433

uint32_t off;

lib/libelf/libelf_data.c

34

_libelf_xlate_shtype(uint32_t sht)

lib/libelf/libelf_ehdr.c

46

uint32_t shtype;

lib/libevent/event.h

173

#define ev_uint32_t uint32_t

lib/libevent/evutil.h

53

#define ev_uint32_t uint32_t

lib/libexpat/lib/siphash.h

120

SIP_U32TO8_LE((p) + 0, (uint32_t)((v) >> 0)); \

lib/libexpat/lib/siphash.h

121

SIP_U32TO8_LE((p) + 4, (uint32_t)((v) >> 32));

lib/libexpat/lib/xmlparse.c

1118

const uint32_t random32 = arc4random();

lib/libexpat/tests/basic_tests.c

2229

uint32_t errorFlags = 0;

lib/libexpat/tests/basic_tests.c

2299

if ((uint32_t)(uintptr_t)XML_GetUserData(g_parser) != 0)

lib/libfido2/src/assert.c

742

uint32_t

lib/libfido2/src/bio.c

419

fido_bio_enroll_t *e, uint32_t timo_ms, int *ms)

lib/libfido2/src/bio.c

447

fido_bio_enroll_t *e, uint32_t timo_ms, const char *pin)

lib/libfido2/src/bio.c

514

fido_bio_enroll_t *e, uint32_t timo_ms, int *ms)

lib/libfido2/src/bio.c

543

fido_bio_enroll_t *e, uint32_t timo_ms)

lib/libfido2/src/cbor.c

1630

return cbor_build_uint32((uint32_t)value);

lib/libfido2/src/cred.c

989

uint32_t

lib/libfido2/src/extern.h

112

int fido_hid_get_usage(const uint8_t *, size_t, uint32_t *);

lib/libfido2/src/extern.h

240

uint32_t uniform_random(uint32_t);

lib/libfido2/src/fido.h

201

uint32_t fido_assert_sigcount(const fido_assert_t *, size_t);

lib/libfido2/src/fido.h

203

uint32_t fido_cred_sigcount(const fido_cred_t *);

lib/libfido2/src/fido/bio.h

82

fido_bio_enroll_t *, uint32_t, const char *);

lib/libfido2/src/fido/bio.h

85

fido_bio_enroll_t *, uint32_t);

lib/libfido2/src/fido/types.h

252

uint32_t cid; /* channel id */

lib/libfido2/src/fido/types.h

263

uint32_t cid; /* assigned channel id */

lib/libfido2/src/fido/types.h

91

uint32_t sigcount; /* signature counter */

lib/libfido2/src/hid.c

27

get_key_val(const void *body, size_t key_len, uint32_t *val)

lib/libfido2/src/hid.c

39

*val = (uint32_t)((ptr[1] << 8) | ptr[0]);

lib/libfido2/src/hid.c

51

uint32_t *usage_page)

lib/libfido2/src/hid.c

63

uint32_t key_val;

lib/libfido2/src/hid.c

87

uint32_t report_size = 0;

lib/libfido2/src/hid.c

96

uint32_t key_val;

lib/libfido2/src/io.c

12

uint32_t cid; /* channel id */

lib/libfido2/src/largeblob.c

466

uint8_t buf[32 + 2 + sizeof(uint32_t) + SHA256_DIGEST_LENGTH];

lib/libfido2/src/largeblob.c

467

uint32_t u32_offset;

lib/libfido2/src/largeblob.c

482

u32_offset = htole32((uint32_t)offset);

lib/libfido2/src/largeblob.c

483

memcpy(&buf[34], &u32_offset, sizeof(uint32_t));

lib/libfido2/src/tpm.c

111

uint32_t exponent; /* zero (meaning 2^16 + 1) */

lib/libfido2/src/tpm.c

128

uint32_t attr;

lib/libfido2/src/tpm.c

139

uint32_t attr;

lib/libfido2/src/tpm.c

66

uint32_t reset_count; /* obfuscated by tpm */

lib/libfido2/src/tpm.c

67

uint32_t restart_count; /* obfuscated by tpm */

lib/libfido2/src/tpm.c

74

uint32_t magic; /* TPM_MAGIC */

lib/libfido2/src/u2f.c

104

authdata_fake(const char *rp_id, uint8_t flags, uint32_t sigcount,

lib/libfido2/src/u2f.c

268

uint32_t sigcount;

lib/libfuse/fuse_common.h

50

uint32_t fh_old; /* old file handle */

lib/libfuse/fuse_common.h

52

uint32_t direct_io : 1;

lib/libfuse/fuse_common.h

53

uint32_t keep_cache : 1;

lib/libfuse/fuse_common.h

54

uint32_t flush : 1;

lib/libfuse/fuse_common.h

55

uint32_t nonseekable : 1;

lib/libfuse/fuse_common.h

56

uint32_t __padd : 27;

lib/libfuse/fuse_common.h

57

uint32_t flock_release : 1;

lib/libfuse/fuse_common.h

76

uint32_t proto_major;

lib/libfuse/fuse_common.h

77

uint32_t proto_minor;

lib/libfuse/fuse_common.h

78

uint32_t async_read;

lib/libfuse/fuse_common.h

79

uint32_t max_write;

lib/libfuse/fuse_common.h

80

uint32_t max_readahead;

lib/libfuse/fuse_common.h

81

uint32_t capable;

lib/libfuse/fuse_common.h

82

uint32_t want;

lib/libfuse/fuse_common.h

83

uint32_t max_background;

lib/libfuse/fuse_common.h

84

uint32_t congestion_threshold;

lib/libfuse/fuse_common.h

85

uint32_t reserved[23];

lib/libfuse/fuse_ops.c

222

uint32_t len, resid;

lib/libfuse/fuse_private.h

48

uint32_t size; /* buffer size */

lib/libfuse/fuse_private.h

49

uint32_t start; /* start offset */

lib/libfuse/fuse_private.h

50

uint32_t idx; /* current offset */

lib/libfuse/fuse_private.h

51

uint32_t len; /* buffer space used */

lib/libkvm/kvm_udf.c

57

uint32_t perm;

lib/libm/src/e_sqrtl.c

100

uint32_t fracl;

lib/libm/src/e_sqrtl.c

117

uint32_t frach;

lib/libm/src/e_sqrtl.c

54

uint32_t frach;

lib/libm/src/e_sqrtl.c

71

uint32_t fracl;

lib/libm/src/ld128/s_exp2l.c

362

uint32_t es, hx, ix, i0;

lib/libm/src/ld128/s_nanl.c

42

uint32_t bits[4];

lib/libm/src/ld80/e_fmodl.c

61

uint32_t hy;

lib/libm/src/ld80/e_fmodl.c

62

uint32_t lx,ly,lz;

lib/libm/src/ld80/s_cbrtl.c

34

uint32_t hx, lx;

lib/libm/src/ld80/s_exp2l.c

216

uint32_t es, hx, ix, i0;

lib/libm/src/ld80/s_nanl.c

42

uint32_t bits[3];

lib/libm/src/ld80/s_remquol.c

60

uint32_t hy;

lib/libm/src/ld80/s_remquol.c

61

uint32_t lx,ly,lz;

lib/libm/src/ld80/s_remquol.c

62

uint32_t esx, esy;

lib/libm/src/ld80/s_truncl.c

45

uint32_t ix0, ix1;

lib/libm/src/math_private.h

385

void _scan_nan(uint32_t *__words, int __num_words, const char *__s);

lib/libm/src/math_private.h

400

uint32_t _lw;

lib/libm/src/s_exp2.c

342

uint32_t hx, ix, lx, i0;

lib/libm/src/s_exp2f.c

96

uint32_t hx, ix, i0;

lib/libm/src/s_nan.c

100

uint32_t bits[2];

lib/libm/src/s_nan.c

119

uint32_t bits[1];

lib/libm/src/s_nan.c

68

_scan_nan(uint32_t *words, int num_words, const char *s)

lib/libm/src/s_nan.c

73

bzero(words, num_words * sizeof(uint32_t));

lib/libm/src/s_rintl.c

59

uint32_t expsign;

lib/libradius/radius.h

417

int radius_get_vs_raw_attr(const RADIUS_PACKET *, uint32_t,

lib/libradius/radius.h

421

int radius_put_vs_raw_attr(RADIUS_PACKET *, uint32_t, uint8_t,

lib/libradius/radius.h

425

int radius_get_vs_raw_attr_ptr(const RADIUS_PACKET *, uint32_t,

lib/libradius/radius.h

429

int radius_get_vs_raw_attr_cat(const RADIUS_PACKET *, uint32_t,

lib/libradius/radius.h

433

int radius_put_vs_raw_attr_cat(RADIUS_PACKET *, uint32_t, uint8_t,

lib/libradius/radius.h

437

int radius_set_vs_raw_attr(RADIUS_PACKET *, uint32_t, uint8_t,

lib/libradius/radius.h

441

int radius_del_vs_attr_all(RADIUS_PACKET *, uint32_t, uint8_t);

lib/libradius/radius.h

444

bool radius_has_vs_attr(const RADIUS_PACKET *, uint32_t, uint8_t);

lib/libradius/radius.h

449

int radius_get_vs_string_attr(const RADIUS_PACKET *, uint32_t,

lib/libradius/radius.h

452

int radius_put_vs_string_attr(RADIUS_PACKET *, uint32_t, uint8_t,

lib/libradius/radius.h

459

uint32_t, uint8_t, uint16_t *);

lib/libradius/radius.h

463

uint32_t, uint8_t, const uint16_t);

lib/libradius/radius.h

467

uint32_t, uint8_t, const uint16_t);

lib/libradius/radius.h

471

uint8_t, uint32_t *);

lib/libradius/radius.h

473

uint32_t, uint8_t, uint32_t *);

lib/libradius/radius.h

475

uint8_t, const uint32_t);

lib/libradius/radius.h

477

uint32_t, uint8_t, const uint32_t);

lib/libradius/radius.h

479

uint8_t, const uint32_t);

lib/libradius/radius.h

481

uint32_t, uint8_t, const uint32_t);

lib/libradius/radius.h

487

uint32_t, uint8_t, uint64_t *);

lib/libradius/radius.h

491

uint32_t, uint8_t, const uint64_t);

lib/libradius/radius.h

495

uint32_t, uint8_t, const uint64_t);

lib/libradius/radius.h

501

uint32_t, uint8_t, struct in_addr *);

lib/libradius/radius.h

505

uint32_t, uint8_t, const struct in_addr);

lib/libradius/radius.h

509

uint32_t, uint8_t, const struct in_addr);

lib/libradius/radius.h

515

uint32_t, uint8_t, struct in6_addr *);

lib/libradius/radius.h

519

uint32_t, uint8_t, const struct in6_addr *);

lib/libradius/radius.h

523

uint32_t, uint8_t, const struct in6_addr *);

lib/libradius/radius_attr.c

125

radius_get_vs_raw_attr(const RADIUS_PACKET * packet, uint32_t vendor,

lib/libradius/radius_attr.c

160

radius_get_vs_raw_attr_cat(const RADIUS_PACKET * packet, uint32_t vendor,

lib/libradius/radius_attr.c

228

radius_put_vs_raw_attr(RADIUS_PACKET * packet, uint32_t vendor, uint8_t vtype,

lib/libradius/radius_attr.c

274

radius_put_vs_raw_attr_cat(RADIUS_PACKET * packet, uint32_t vendor,

lib/libradius/radius_attr.c

309

uint32_t vendor, uint8_t vtype, const void *buf, size_t length)

lib/libradius/radius_attr.c

337

radius_del_vs_attr_all(RADIUS_PACKET * packet, uint32_t vendor, uint8_t vtype)

lib/libradius/radius_attr.c

362

radius_has_vs_attr(const RADIUS_PACKET * packet, uint32_t vendor, uint8_t vtype)

lib/libradius/radius_attr.c

392

uint32_t vendor, uint8_t vtype, char *str, size_t len)

lib/libradius/radius_attr.c

419

uint32_t vendor, uint8_t vtype, const char *str)

lib/libradius/radius_attr.c

443

uint32_t vendor, uint8_t vtype, tname *val) \

lib/libradius/radius_attr.c

469

uint32_t vendor, uint8_t vtype, tname val) \

lib/libradius/radius_attr.c

488

uint32_t vendor, uint8_t vtype, tname val) \

lib/libradius/radius_attr.c

513

uint32_t vendor, uint8_t vtype, tname *val) \

lib/libradius/radius_attr.c

534

uint32_t vendor, uint8_t vtype, const tname *val) \

lib/libradius/radius_attr.c

547

uint32_t vendor, uint8_t vtype, const tname *val) \

lib/libradius/radius_attr.c

554

DEFINE_TYPED_ATTRIBUTE_ACCESSOR_BYVAL(uint32, uint32_t, htonl, ntohl)

lib/libradius/radius_attr.c

99

radius_get_vs_raw_attr_ptr(const RADIUS_PACKET * packet, uint32_t vendor,

lib/libradius/radius_local.h

48

uint32_t vendor;

lib/librthread/synch.h

23

_wake(volatile uint32_t *p, int n)

lib/librthread/synch.h

29

_twait(volatile uint32_t *p, int val, clockid_t clockid, const struct timespec *abs)

lib/librthread/synch.h

60

_requeue(volatile uint32_t *p, int n, int m, volatile uint32_t *q)

lib/libsndio/amsg.h

106

uint32_t ctl;

lib/libsndio/amsg.h

114

uint32_t id; /* client id */

lib/libsndio/amsg.h

154

uint32_t __pad2[4];

lib/libsndio/amsg.h

72

uint32_t cmd;

lib/libsndio/amsg.h

73

uint32_t __pad;

lib/libsndio/amsg.h

86

uint32_t rate; /* frames per second */

lib/libsndio/amsg.h

87

uint32_t bufsz; /* total buffered frames */

lib/libsndio/amsg.h

88

uint32_t round;

lib/libsndio/amsg.h

89

uint32_t appbufsz; /* client side bufsz */

lib/libsndio/amsg.h

90

uint32_t _reserved[1]; /* for future use */

lib/libsndio/amsg.h

94

uint32_t size;

lib/libssl/bs_cbb.c

130

cbb_add_u(CBB *cbb, uint32_t v, size_t len_len)

lib/libssl/bs_cbb.c

396

return cbb_add_u(cbb, (uint32_t)value, 1);

lib/libssl/bs_cbb.c

405

return cbb_add_u(cbb, (uint32_t)value, 2);

lib/libssl/bs_cbb.c

414

return cbb_add_u(cbb, (uint32_t)value, 3);

lib/libssl/bs_cbb.c

423

return cbb_add_u(cbb, (uint32_t)value, 4);

lib/libssl/bs_cbb.c

429

uint32_t a, b;

lib/libssl/bs_cbs.c

148

cbs_get_u(CBS *cbs, uint32_t *out, size_t len)

lib/libssl/bs_cbs.c

150

uint32_t result = 0;

lib/libssl/bs_cbs.c

183

uint32_t v;

lib/libssl/bs_cbs.c

193

CBS_get_u24(CBS *cbs, uint32_t *out)

lib/libssl/bs_cbs.c

199

CBS_get_u32(CBS *cbs, uint32_t *out)

lib/libssl/bs_cbs.c

207

uint32_t a, b;

lib/libssl/bs_cbs.c

247

uint32_t len;

lib/libssl/bs_cbs.c

274

cbs_peek_u(CBS *cbs, uint32_t *out, size_t len)

lib/libssl/bs_cbs.c

276

uint32_t result = 0;

lib/libssl/bs_cbs.c

309

uint32_t v;

lib/libssl/bs_cbs.c

319

CBS_peek_u24(CBS *cbs, uint32_t *out)

lib/libssl/bs_cbs.c

325

CBS_peek_u32(CBS *cbs, uint32_t *out)

lib/libssl/bs_cbs.c

392

uint32_t len32;

lib/libssl/bytestring.h

126

int CBS_get_u24(CBS *cbs, uint32_t *out);

lib/libssl/bytestring.h

132

int CBS_get_u32(CBS *cbs, uint32_t *out);

lib/libssl/bytestring.h

189

int CBS_peek_u24(CBS *cbs, uint32_t *out);

lib/libssl/bytestring.h

195

int CBS_peek_u32(CBS *cbs, uint32_t *out);

lib/libssl/d1_both.c

1174

uint32_t msg_len, frag_off, frag_len;

lib/libssl/ssl.h

1201

uint32_t SSL_SESSION_get_max_early_data(const SSL_SESSION *sess);

lib/libssl/ssl.h

1202

int SSL_SESSION_set_max_early_data(SSL_SESSION *sess, uint32_t max_early_data);

lib/libssl/ssl.h

1280

uint32_t SSL_CTX_get_max_early_data(const SSL_CTX *ctx);

lib/libssl/ssl.h

1281

int SSL_CTX_set_max_early_data(SSL_CTX *ctx, uint32_t max_early_data);

lib/libssl/ssl.h

1283

uint32_t SSL_get_max_early_data(const SSL *s);

lib/libssl/ssl.h

1284

int SSL_set_max_early_data(SSL *s, uint32_t max_early_data);

lib/libssl/ssl_asn1.c

379

s->tlsext_tick_lifetime_hint = (uint32_t)lifetime;

lib/libssl/ssl_both.c

256

uint32_t l;

lib/libssl/ssl_clnt.c

1595

uint32_t lifetime_hint;

lib/libssl/ssl_lib.c

1228

uint32_t

lib/libssl/ssl_lib.c

1236

SSL_CTX_set_max_early_data(SSL_CTX *ctx, uint32_t max_early_data)

lib/libssl/ssl_lib.c

1242

uint32_t

lib/libssl/ssl_lib.c

1250

SSL_set_max_early_data(SSL *s, uint32_t max_early_data)

lib/libssl/ssl_local.h

438

uint32_t tlsext_tick_lifetime_hint; /* Session lifetime hint in seconds */

lib/libssl/ssl_local.h

439

uint32_t tlsext_tick_age_add; /* TLSv1.3 ticket age obfuscation (in ms) */

lib/libssl/ssl_local.h

563

uint32_t extensions_seen;

lib/libssl/ssl_local.h

566

uint32_t extensions_processed;

lib/libssl/ssl_pkt.c

790

uint32_t hs_msg_length;

lib/libssl/ssl_seclevel.c

332

uint32_t flags;

lib/libssl/ssl_sess.c

199

uint32_t

lib/libssl/ssl_sess.c

207

SSL_SESSION_set_max_early_data(SSL_SESSION *s, uint32_t max_early_data)

lib/libssl/ssl_tlsext.c

2387

CTASSERT(N_TLS_EXTENSIONS <= (sizeof(uint32_t) * 8));

lib/libssl/tls13_handshake_msg.c

126

uint32_t msg_len;

lib/libssl/tls13_handshake_msg.c

27

uint32_t msg_len;

lib/libssl/tls13_lib.c

378

uint32_t ticket_lifetime, ticket_age_add;

lib/libtls/tls.h

151

int tls_config_set_protocols(struct tls_config *_config, uint32_t _protocols);

lib/libtls/tls.h

168

int tls_config_parse_protocols(uint32_t *_protocols, const char *_protostr);

lib/libtls/tls.h

173

int tls_config_add_ticket_key(struct tls_config *_config, uint32_t _keyrev,

lib/libtls/tls_config.c

226

tls_config_parse_protocols(uint32_t *protocols, const char *protostr)

lib/libtls/tls_config.c

228

uint32_t proto, protos = 0;

lib/libtls/tls_config.c

714

tls_config_set_protocols(struct tls_config *config, uint32_t protocols)

lib/libtls/tls_config.c

897

tls_config_add_ticket_key(struct tls_config *config, uint32_t keyrev,

lib/libtls/tls_internal.h

106

uint32_t protocols;

lib/libtls/tls_internal.h

111

uint32_t ticket_keyrev;

lib/libtls/tls_internal.h

189

uint32_t flags;

lib/libtls/tls_internal.h

190

uint32_t state;

lib/libusbhid/data.c

37

uint32_t hpos;

lib/libusbhid/data.c

38

uint32_t hsize;

lib/libusbhid/data.c

39

uint32_t data;

lib/libusbhid/data.c

73

data = (uint32_t)((uint32_t)data << hsize) >> hsize;

lib/libusbhid/data.c

82

uint32_t hpos;

lib/libusbhid/data.c

83

uint32_t hsize;

lib/libusbhid/data.c

84

uint32_t mask;

lib/libusbhid/descr.c

76

hid_get_report_desc_data(report_desc_t d, uint8_t **data, uint32_t *size)

lib/libusbhid/parse.c

46

uint32_t pos[ITEMTYPES];

lib/libusbhid/parse.c

540

uint32_t temp;

lib/libusbhid/parse.c

541

uint32_t hpos;

lib/libusbhid/parse.c

542

uint32_t lpos;

lib/libusbhid/parse.c

55

uint32_t pos[ITEMTYPES];

lib/libusbhid/parse.c

59

uint32_t loc_size; /* last seen size */

lib/libusbhid/parse.c

60

uint32_t loc_count; /* last seen count */

lib/libusbhid/usbhid.h

40

uint32_t _usage_page;

lib/libusbhid/usbhid.h

52

uint32_t usage;

lib/libusbhid/usbhid.h

66

uint32_t flags;

lib/libusbhid/usbhid.h

68

uint32_t pos;

lib/libusbhid/usbhid.h

80

void hid_get_report_desc_data(report_desc_t, uint8_t **, uint32_t *);

lib/libusbhid/usbvar.h

31

uint32_t size;

lib/libutil/bcrypt_pbkdf.c

108

uint32_t count;

lib/libutil/bcrypt_pbkdf.c

62

uint32_t cdata[BCRYPT_WORDS];

lib/libutil/imsg-buffer.c

1039

uint32_t

lib/libutil/imsg-buffer.c

186

uint32_t v;

lib/libutil/imsg-buffer.c

219

uint32_t v;

lib/libutil/imsg-buffer.c

324

uint32_t v;

lib/libutil/imsg-buffer.c

357

uint32_t v;

lib/libutil/imsg-buffer.c

37

uint32_t queued;

lib/libutil/imsg-buffer.c

485

ibuf_get_h32(struct ibuf *buf, uint32_t *value)

lib/libutil/imsg-buffer.c

513

ibuf_get_n32(struct ibuf *buf, uint32_t *value)

lib/libutil/imsg-buffer.c

680

uint32_t

lib/libutil/imsg.c

110

uint32_t

lib/libutil/imsg.c

222

uint32_t

lib/libutil/imsg.c

240

uint32_t

lib/libutil/imsg.c

247

imsg_compose(struct imsgbuf *imsgbuf, uint32_t type, uint32_t id, pid_t pid,

lib/libutil/imsg.c

269

imsg_composev(struct imsgbuf *imsgbuf, uint32_t type, uint32_t id, pid_t pid,

lib/libutil/imsg.c

301

imsg_compose_ibuf(struct imsgbuf *imsgbuf, uint32_t type, uint32_t id,

lib/libutil/imsg.c

363

imsg_create(struct imsgbuf *imsgbuf, uint32_t type, uint32_t id, pid_t pid,

lib/libutil/imsg.c

406

uint32_t len;

lib/libutil/imsg.c

437

uint32_t len;

lib/libutil/imsg.c

60

imsgbuf_set_maxsize(struct imsgbuf *imsgbuf, uint32_t max)

lib/libutil/imsg.h

107

int ibuf_get_n32(struct ibuf *, uint32_t *);

lib/libutil/imsg.h

110

int ibuf_get_h32(struct ibuf *, uint32_t *);

lib/libutil/imsg.h

125

uint32_t msgbuf_queuelen(struct msgbuf *);

lib/libutil/imsg.h

136

uint32_t ibufq_queuelen(struct ibufqueue *);

lib/libutil/imsg.h

143

int imsgbuf_set_maxsize(struct imsgbuf *, uint32_t);

lib/libutil/imsg.h

148

uint32_t imsgbuf_queuelen(struct imsgbuf *);

lib/libutil/imsg.h

158

uint32_t imsg_get_id(struct imsg *);

lib/libutil/imsg.h

161

uint32_t imsg_get_type(struct imsg *);

lib/libutil/imsg.h

163

int imsg_compose(struct imsgbuf *, uint32_t, uint32_t, pid_t, int,

lib/libutil/imsg.h

165

int imsg_composev(struct imsgbuf *, uint32_t, uint32_t, pid_t, int,

lib/libutil/imsg.h

167

int imsg_compose_ibuf(struct imsgbuf *, uint32_t, uint32_t, pid_t,

lib/libutil/imsg.h

169

struct ibuf *imsg_create(struct imsgbuf *, uint32_t, uint32_t, pid_t, size_t);

lib/libutil/imsg.h

50

uint32_t maxsize;

lib/libutil/imsg.h

56

uint32_t type;

lib/libutil/imsg.h

57

uint32_t len;

lib/libutil/imsg.h

58

uint32_t peerid;

lib/libutil/imsg.h

59

uint32_t pid;

lib/libutil/ohash.c

205

uint32_t

lib/libutil/ohash.c

208

uint32_t k;

lib/libutil/ohash.c

223

uint32_t hv)

lib/libutil/ohash.c

26

uint32_t hv;

lib/libutil/ohash.c

270

ohash_lookup_memory(struct ohash *h, const char *k, size_t size, uint32_t hv)

lib/libutil/ohash.c

323

uint32_t hv;

lib/libutil/ohash.h

57

const char *, uint32_t);

lib/libutil/ohash.h

59

size_t, uint32_t)

lib/libutil/ohash.h

69

uint32_t ohash_interval(const char *, const char **);

libexec/ld.so/malloc.c

716

static uint32_t

libexec/ld.so/malloc.c

720

uint32_t chunknum;

libexec/ld.so/malloc.c

751

uint32_t chunknum;

libexec/ld.so/resolve.c

53

uint32_t sl_gnu_hash;

libexec/ld.so/resolve.c

589

uint32_t hash = sl->sl_gnu_hash;

libexec/ld.so/resolve.h

68

typedef uint32_t Elf_Hash_Word;

libexec/login_token/token.c

67

uint32_t ul[2];

libexec/snmpd/snmpd_metrics/mib.c

1048

agentx_varbind_counter32(vb, (uint32_t)kif->if_ibytes);

libexec/snmpd/snmpd_metrics/mib.c

1050

agentx_varbind_counter32(vb, (uint32_t)kif->if_ipackets);

libexec/snmpd/snmpd_metrics/mib.c

1052

agentx_varbind_counter32(vb, (uint32_t)kif->if_imcasts);

libexec/snmpd/snmpd_metrics/mib.c

1054

agentx_varbind_counter32(vb, (uint32_t)kif->if_iqdrops);

libexec/snmpd/snmpd_metrics/mib.c

1056

agentx_varbind_counter32(vb, (uint32_t)kif->if_ierrors);

libexec/snmpd/snmpd_metrics/mib.c

1058

agentx_varbind_counter32(vb, (uint32_t)kif->if_noproto);

libexec/snmpd/snmpd_metrics/mib.c

1060

agentx_varbind_counter32(vb, (uint32_t)kif->if_obytes);

libexec/snmpd/snmpd_metrics/mib.c

1062

agentx_varbind_counter32(vb, (uint32_t)kif->if_opackets);

libexec/snmpd/snmpd_metrics/mib.c

1064

agentx_varbind_counter32(vb, (uint32_t)kif->if_omcasts);

libexec/snmpd/snmpd_metrics/mib.c

1066

agentx_varbind_counter32(vb, (uint32_t)kif->if_oqdrops);

libexec/snmpd/snmpd_metrics/mib.c

1068

agentx_varbind_counter32(vb, (uint32_t)kif->if_oerrors);

libexec/snmpd/snmpd_metrics/mib.c

1111

agentx_varbind_counter32(vb, (uint32_t)kif->if_imcasts);

libexec/snmpd/snmpd_metrics/mib.c

1115

agentx_varbind_counter32(vb, (uint32_t)kif->if_omcasts);

libexec/snmpd/snmpd_metrics/mib.c

2459

uint32_t idx;

libexec/snmpd/snmpd_metrics/mib.c

2930

const uint32_t *policy;

libexec/snmpd/snmpd_metrics/mib.c

400

uint32_t sop[] = { HRSTORAGEOTHER };

libexec/snmpd/snmpd_metrics/mib.c

477

memcpy(sop, (uint32_t[]){ HRSTORAGERAM }, sizeof(sop));

libexec/snmpd/snmpd_metrics/mib.c

484

memcpy(sop, (uint32_t[]){ HRSTORAGERAM }, sizeof(sop));

libexec/snmpd/snmpd_metrics/mib.c

491

memcpy(sop, (uint32_t[]){ HRSTORAGEVIRTUALMEMORY },

libexec/snmpd/snmpd_metrics/mib.c

500

memcpy(sop, (uint32_t[]){ HRSTORAGEFIXEDDISK }, sizeof(sop));

libexec/snmpd/snmpd_metrics/mib.c

536

uint32_t fail = 0;

libexec/snmpd/snmpd_metrics/mib.c

541

uint32_t sop[] = { HRDEVICEPROCESSOR };

libexec/tradcpp/macro.c

302

return ((uint32_t)x2)*65535U + x1;

regress/lib/libagentx/main.c

453

uint32_t idx;

regress/lib/libagentx/main.c

482

uint32_t idx1, idx2;

regress/lib/libagentx/main.c

686

const uint32_t *idx;

regress/lib/libagentx/main.c

754

uint32_t idx;

regress/lib/libagentx/main.c

763

uint32_t idx;

regress/lib/libagentx/main.c

772

uint32_t idx;

regress/lib/libagentx/main.c

781

uint32_t idx;

regress/lib/libagentx/main.c

790

uint32_t idx;

regress/lib/libagentx/main.c

799

uint32_t idx;

regress/lib/libc/arc4random-fork/arc4random-fork.c

45

uint32_t x[N];

regress/lib/libc/asr/bin/common.c

289

uint32_t addr;

regress/lib/libc/asr/bin/common.c

505

unpack_u32(struct packed *p, uint32_t *u32)

regress/lib/libc/asr/bin/common.h

114

uint32_t serial;

regress/lib/libc/asr/bin/common.h

115

uint32_t refresh;

regress/lib/libc/asr/bin/common.h

116

uint32_t retry;

regress/lib/libc/asr/bin/common.h

117

uint32_t expire;

regress/lib/libc/asr/bin/common.h

118

uint32_t minimum;

regress/lib/libc/asr/bin/common.h

96

uint32_t rr_ttl;

regress/lib/libc/printf/fp.c

202

static uint32_t junk = 0xdeadbeef;

regress/lib/libc/printf/fp.c

203

uint32_t buf[512];

regress/lib/libc/sys/t_select.c

81

uint32_t p = (*m);

regress/lib/libc/sys/t_select.c

86

uint32_t p = m->__bits[i - 1];

regress/lib/libc/sys/t_stat.c

333

uint32_t iaddr;

regress/lib/libc/uuid/uuidtest.c

31

uint32_t status;

regress/lib/libc/wprintf/wfp.c

195

static uint32_t junk = 0xdeadbeef;

regress/lib/libc/wprintf/wfp.c

196

uint32_t buf[512];

regress/lib/libcrypto/bio/bio_host.c

30

uint32_t ip;

regress/lib/libcrypto/bio/bio_host.c

85

uint32_t i;

regress/lib/libevent/event_regress.c

1510

int evtag_decode_int(uint32_t *pnumber, struct evbuffer *evbuf);

regress/lib/libevent/event_regress.c

1511

int evtag_encode_tag(struct evbuffer *evbuf, uint32_t number);

regress/lib/libevent/event_regress.c

1512

int evtag_decode_tag(uint32_t *pnumber, struct evbuffer *evbuf);

regress/lib/libevent/event_regress.c

1563

uint32_t integers[TEST_MAX_INT] = {

regress/lib/libevent/event_regress.c

1566

uint32_t integer;

regress/lib/libevent/event_regress.c

1646

uint32_t integers[TEST_MAX_INT] = {

regress/lib/libevent/event_regress.c

1649

uint32_t integer;

regress/lib/libevent/event_regress.c

1706

uint32_t tag;

regress/lib/libradius/test21.c

11

uint32_t v32;

regress/lib/libssl/bytestring/bytestringtest.c

104

uint32_t u32;

regress/lib/libssl/bytestring/bytestringtest.c

153

uint32_t u32;

regress/lib/libssl/bytestring/bytestringtest.c

72

uint32_t u32;

regress/lib/libssl/interop/server.c

211

uint32_t context;

regress/lib/libtls/config/configtest.c

142

uint32_t protocols = 0;

regress/lib/libtls/config/configtest.c

27

uint32_t want_protocols;

regress/lib/libtls/tls/tlstest.c

299

uint32_t protocols;

regress/misc/c++abi/nm1.C

28

D(uint32_t)

regress/sbin/iked/parser/common.c

121

group_getid(uint32_t id)

regress/sbin/iked/parser/common.c

35

group_get(uint32_t);

regress/sbin/iked/parser/test_parser_fuzz.c

395

static uint32_t

regress/sbin/iked/parser/test_parser_fuzz.c

398

return *(uint32_t *)&data[OFFSET_LENGTH];

regress/sbin/iked/parser/test_parser_fuzz.c

402

set_length(uint8_t *data, uint32_t length)

regress/sbin/iked/parser/test_parser_fuzz.c

404

uint32_t *p;

regress/sbin/iked/parser/test_parser_fuzz.c

406

p = (uint32_t *)&data[OFFSET_LENGTH];

regress/sbin/iked/test_helper/test_helper.c

396

uint32_t aa1, uint32_t aa2, enum test_predicate pred)

regress/sbin/iked/test_helper/test_helper.h

78

uint32_t aa1, uint32_t aa2, enum test_predicate pred);

regress/sys/arch/i386/f00f/f00f.c

40

if (*((uint32_t *)sip->si_addr) != 0xc8c70ff0)

regress/sys/arch/i386/f00f/f00f.c

51

uint32_t eax, ebx, ecx, edx;

regress/sys/btcfi/foobar.c

29

uint32_t d;

regress/sys/crypto/chachapoly/chachapoly_test.c

322

uint32_t *p;

regress/sys/crypto/chachapoly/chachapoly_test.c

343

p = (uint32_t *)blk;

regress/sys/crypto/chachapoly/chachapoly_test.c

345

p = (uint32_t *)blk + 2;

regress/sys/crypto/gmac/gmac_test.c

644

uint32_t *p;

regress/sys/crypto/gmac/gmac_test.c

665

p = (uint32_t *)blk + 1;

regress/sys/crypto/gmac/gmac_test.c

667

p = (uint32_t *)blk + 3;

regress/sys/dev/video/videotest.c

100

uint32_t pixelformat;

regress/sys/dev/video/videotest.c

245

test_ioctl_enum_fsizes(int fd, uint32_t pixelformat, int index)

regress/sys/dev/video/videotest.c

288

uint32_t last_pixelformat;

regress/sys/dev/video/videotest.c

646

print_pixelformat(uint32_t pixelformat, int lowercase)

regress/sys/dev/video/videotest.c

76

int test_ioctl_enum_fsizes(int, uint32_t, int);

regress/sys/dev/video/videotest.c

81

char *print_pixelformat(uint32_t, int);

regress/sys/dev/video/videotest.c

92

uint32_t width;

regress/sys/dev/video/videotest.c

93

uint32_t height;

regress/sys/fileops/fileops.c

166

uint32_t seed = curpos;

regress/sys/fileops/fileops.c

185

uint32_t seed = curpos;

regress/sys/fileops/fileops.c

39

gen_data(void *buf, size_t size, uint32_t seed)

regress/sys/fileops/fileops.c

44

uint32_t *ibuf = buf;

regress/sys/fileops/fileops.c

50

check_data(const void *buf, size_t size, uint32_t seed)

regress/sys/fileops/fileops.c

53

const uint32_t *ibuf = buf;

regress/sys/fileops/fileops.c

66

const uint32_t *ibuf = buf;

regress/sys/kern/futex/futex.c

33

uint32_t lock = 0;

regress/sys/kern/futex/futex.c

34

uint32_t *shlock;

regress/sys/kern/futex/futex.h

19

futex_wake(volatile uint32_t *p, int n, int priv)

regress/sys/kern/futex/futex.h

25

futex_wait(volatile uint32_t *p, int val, int priv)

regress/sys/kern/futex/futex.h

27

while (*p != (uint32_t)val)

regress/sys/kern/futex/futex.h

32

futex_twait(volatile uint32_t *p, int val, clockid_t clockid,

regress/sys/kern/futex/futex.h

39

futex_requeue(volatile uint32_t *p, int n, int m, volatile uint32_t *q)

regress/sys/kern/kqueue/kqueue-tun.c

71

uint32_t type = htonl(AF_INET);

regress/sys/kern/kqueue/kqueue-tun.c

93

uint32_t type;

regress/sys/kern/ptrace/xstate/xstate.c

16

uint32_t a, b, c, d;

regress/sys/kern/ptrace/xstate/xstate.c

22

uint32_t size;

regress/sys/kern/ptrace/xstate/xstate.c

26

uint32_t supported;

regress/sys/kern/ptrace/xstate/xstate.c

27

uint32_t offset;

regress/sys/kern/ptrace/xstate/xstate.c

28

uint32_t size;

regress/sys/kern/ptrace/xstate/xstate.c

48

cpuid(uint32_t leaf, uint32_t subleaf, struct cpuid *out)

regress/sys/kern/unalign/unalign.c

17

uint32_t array[5];

regress/sys/kern/unalign/unalign.c

48

uint32_t *addr = array;

regress/sys/kern/unalign/unalign.c

51

if (((uint32_t)addr & 7) != 0)

regress/sys/kern/xonly/xonly.c

196

uint32_t ebx, ecx, edx;

regress/sys/net/rtable/kern_compat.h

97

int rt_hash(struct rtentry *, const struct sockaddr *, uint32_t *);

regress/sys/net/rtable/util.c

506

static uint32_t rt_hashjitter;

regress/sys/net/rtable/util.c

524

rt_hash(struct rtentry *rt, const struct sockaddr *dst, uint32_t *src)

regress/sys/net/rtable/util.c

526

uint32_t a, b, c;

regress/usr.bin/ssh/misc/sk-dummy/sk-dummy.c

216

sk_enroll(uint32_t alg, const uint8_t *challenge, size_t challenge_len,

regress/usr.bin/ssh/misc/sk-dummy/sk-dummy.c

291

const char *application, uint32_t counter, uint8_t flags,

regress/usr.bin/ssh/misc/sk-dummy/sk-dummy.c

383

const char *application, uint32_t counter, uint8_t flags,

regress/usr.bin/ssh/misc/sk-dummy/sk-dummy.c

460

sk_sign(uint32_t alg, const uint8_t *data, size_t datalen,

regress/usr.bin/ssh/misc/sk-dummy/sk-dummy.c

70

uint32_t

regress/usr.bin/ssh/unittests/sshbuf/test_sshbuf_fuzz.c

29

uint32_t r;

regress/usr.bin/ssh/unittests/sshbuf/test_sshbuf_getput_basic.c

29

uint32_t v32;

regress/usr.bin/ssh/unittests/sshbuf/test_sshbuf_getput_crypto.c

75

ASSERT_U32_EQ(PEEK_U32(sshbuf_ptr(p1)), (uint32_t)BN_num_bytes(bn));

regress/usr.bin/ssh/unittests/sshbuf/test_sshbuf_getput_crypto.c

99

ASSERT_U32_EQ(PEEK_U32(sshbuf_ptr(p1)), (uint32_t)BN_num_bytes(bn) + 1);

regress/usr.bin/ssh/unittests/sshbuf/test_sshbuf_getput_fuzz.c

34

uint32_t u32;

regress/usr.bin/ssh/unittests/test_helper/test_helper.c

549

uint32_t aa1, uint32_t aa2, enum test_predicate pred)

regress/usr.bin/ssh/unittests/test_helper/test_helper.h

92

uint32_t aa1, uint32_t aa2, enum test_predicate pred);

regress/usr.sbin/bgpd/unittests/bitmap_test.c

24

static const uint32_t foobar[] = { 1, 2, 61, 62, 63, 64, 65, 66,

regress/usr.sbin/bgpd/unittests/bitmap_test.c

27

static const uint32_t foobaz[] = { 17, 18, 67, 222, 512 };

regress/usr.sbin/bgpd/unittests/bitmap_test.c

35

uint32_t id, i;

regress/usr.sbin/bgpd/unittests/chash_test.c

26

uint32_t id;

regress/usr.sbin/bgpd/unittests/chash_test.c

32

__unused static inline uint32_t

regress/usr.sbin/bgpd/unittests/chash_test.c

33

hash(uint32_t h)

regress/usr.sbin/bgpd/unittests/chash_test.c

77

uint32_t i, sum;

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

100

{ 201, (const uint32_t []){ 202 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

101

{ 202, (const uint32_t []){ 203, 204, 205 }, 3 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

102

{ 203, (const uint32_t []){ 103, 111, 112 }, 3 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

104

{ 205, (const uint32_t []){ 0 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

107

{ 65000, (const uint32_t []){

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

111

{ 196618, (const uint32_t []){ 1, 2, 3, 4 }, 4 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

172

{ (const uint32_t []) { 1 }, 1, { 1, 1, 0, 0, 1, 0, 0 } },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

173

{ (const uint32_t []) { 7 }, 1, { 1, 1, 0, 0, 1, 0, 0 } },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

174

{ (const uint32_t []) { 8 }, 1, { 1, 1, 0, 0, 1, 0, 0 } },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

176

{ (const uint32_t []) { 1, 1 }, 2, { 1, 1, 0, 0, 1, 0, 0 } },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

177

{ (const uint32_t []) { 7, 7 }, 2, { 1, 1, 0, 0, 1, 0, 0 } },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

178

{ (const uint32_t []) { 8, 8 }, 2, { 1, 1, 0, 0, 1, 0, 0 } },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

180

{ (const uint32_t []) { 1, 1, 1 }, 3, { 1, 1, 0, 0, 1, 0, 0 } },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

181

{ (const uint32_t []) { 7, 7, 7 }, 3, { 1, 1, 0, 0, 1, 0, 0 } },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

182

{ (const uint32_t []) { 8, 8, 8 }, 3, { 1, 1, 0, 0, 1, 0, 0 } },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

184

{ (const uint32_t []) { 1, 5 }, 2, { 2, 1, 0, 0, 2, 0, 0 } },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

185

{ (const uint32_t []) { 1, 1, 5, 5 }, 4, { 2, 1, 0, 0, 2, 0, 0 } },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

186

{ (const uint32_t []) { 1, 5, 17 }, 3, { 3, 1, 0, 0, 3, 0, 0 } },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

188

{ (const uint32_t []) { 1, 4 }, 2, { 2, 2, 0, 1, 2, 0, 0 } },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

189

{ (const uint32_t []) { 1, 6 }, 2, { 2, 2, 1, 0, 2, 0, 0 } },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

190

{ (const uint32_t []) { 1, 17 }, 2, { 2, 2, 0, 1, 1, 0, 2 } },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

192

{ (const uint32_t []) { 42, 43, 44 }, 3, { 3, 3, 2, 0, 1, 2, 0 } },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

194

{ (const uint32_t []) { 42, 1, 5, 17, 44 }, 5,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

198

{ (const uint32_t []) { 1, 6, 11, 12, 13, 19, 20 }, 7,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

216

{ (const uint32_t []) { }, 0, ROLE_CUSTOMER, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

217

{ (const uint32_t []) { }, 0, ROLE_PROVIDER, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

218

{ (const uint32_t []) { }, 0, ROLE_RS, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

219

{ (const uint32_t []) { }, 0, ROLE_RS_CLIENT, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

220

{ (const uint32_t []) { }, 0, ROLE_PEER, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

222

{ (const uint32_t []) { 2 }, 1, ROLE_RS_CLIENT, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

223

{ (const uint32_t []) { 2 }, 1, ROLE_PEER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

225

{ (const uint32_t []) { 3 }, 1, ROLE_PROVIDER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

226

{ (const uint32_t []) { 4 }, 1, ROLE_CUSTOMER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

227

{ (const uint32_t []) { 5 }, 1, ROLE_CUSTOMER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

228

{ (const uint32_t []) { 6 }, 1, ROLE_CUSTOMER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

230

{ (const uint32_t []) { 7 }, 1, ROLE_PROVIDER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

231

{ (const uint32_t []) { 7 }, 1, ROLE_PEER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

232

{ (const uint32_t []) { 7 }, 1, ROLE_RS_CLIENT, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

234

{ (const uint32_t []) { 2, 8 }, 2, ROLE_PEER, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

235

{ (const uint32_t []) { 2, 8 }, 2, ROLE_RS_CLIENT, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

237

{ (const uint32_t []) { 2, 9 }, 2, ROLE_PEER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

238

{ (const uint32_t []) { 2, 9 }, 2, ROLE_RS_CLIENT, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

240

{ (const uint32_t []) { 2, 10 }, 2, ROLE_PEER, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

241

{ (const uint32_t []) { 2, 10 }, 2, ROLE_RS_CLIENT, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

243

{ (const uint32_t []) { 2, 11 }, 2, ROLE_PEER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

244

{ (const uint32_t []) { 2, 11 }, 2, ROLE_RS_CLIENT, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

246

{ (const uint32_t []) { 3, 8 }, 2, ROLE_PROVIDER, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

247

{ (const uint32_t []) { 3, 12 }, 2, ROLE_PROVIDER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

248

{ (const uint32_t []) { 3, 13 }, 2, ROLE_PROVIDER, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

249

{ (const uint32_t []) { 3, 14 }, 2, ROLE_PROVIDER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

251

{ (const uint32_t []) { 4, 8 }, 2, ROLE_CUSTOMER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

252

{ (const uint32_t []) { 4, 15 }, 2, ROLE_CUSTOMER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

253

{ (const uint32_t []) { 4, 16 }, 2, ROLE_CUSTOMER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

254

{ (const uint32_t []) { 4, 24 }, 2, ROLE_CUSTOMER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

256

{ (const uint32_t []) { 5, 8 }, 2, ROLE_CUSTOMER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

257

{ (const uint32_t []) { 5, 17 }, 2, ROLE_CUSTOMER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

258

{ (const uint32_t []) { 5, 25 }, 2, ROLE_CUSTOMER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

259

{ (const uint32_t []) { 5, 26 }, 2, ROLE_CUSTOMER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

261

{ (const uint32_t []) { 6, 18 }, 2, ROLE_CUSTOMER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

262

{ (const uint32_t []) { 6, 19 }, 2, ROLE_CUSTOMER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

264

{ (const uint32_t []) { 7, 19 }, 2, ROLE_PROVIDER, ASPA_UNKNOWN },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

265

{ (const uint32_t []) { 7, 19 }, 2, ROLE_PEER, ASPA_UNKNOWN },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

266

{ (const uint32_t []) { 7, 19 }, 2, ROLE_RS_CLIENT, ASPA_UNKNOWN },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

267

{ (const uint32_t []) { 7, 21 }, 2, ROLE_PROVIDER, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

268

{ (const uint32_t []) { 7, 21 }, 2, ROLE_PEER, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

269

{ (const uint32_t []) { 7, 21 }, 2, ROLE_RS_CLIENT, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

27

static struct aspath *build_aspath(const uint32_t *, uint32_t, int);

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

271

{ (const uint32_t []) { 6, 19, 20 }, 3, ROLE_CUSTOMER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

272

{ (const uint32_t []) { 20, 19, 6 }, 3, ROLE_CUSTOMER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

274

{ (const uint32_t []) { 3, 14, 25 }, 3, ROLE_PROVIDER, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

275

{ (const uint32_t []) { 3, 14, 19 }, 3, ROLE_PROVIDER, ASPA_UNKNOWN },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

276

{ (const uint32_t []) { 3, 14, 19 }, 3, ROLE_PEER, ASPA_UNKNOWN },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

277

{ (const uint32_t []) { 3, 14, 19 }, 3, ROLE_RS_CLIENT, ASPA_UNKNOWN },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

278

{ (const uint32_t []) { 3, 14, 21 }, 3, ROLE_PROVIDER, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

279

{ (const uint32_t []) { 3, 14, 21 }, 3, ROLE_PEER, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

28

static const char *print_aspath(const uint32_t *, uint32_t);

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

280

{ (const uint32_t []) { 3, 14, 21 }, 3, ROLE_RS_CLIENT, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

281

{ (const uint32_t []) { 3, 14, 27 }, 3, ROLE_PROVIDER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

282

{ (const uint32_t []) { 3, 14, 27 }, 3, ROLE_PEER, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

283

{ (const uint32_t []) { 3, 14, 27 }, 3, ROLE_RS_CLIENT, ASPA_VALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

285

{ (const uint32_t []) { 7, 19, 22, 21 }, 4, ROLE_PROVIDER,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

287

{ (const uint32_t []) { 7, 19, 22, 21 }, 4, ROLE_PEER, ASPA_INVALID },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

288

{ (const uint32_t []) { 7, 19, 22, 21 }, 4, ROLE_RS_CLIENT,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

291

{ (const uint32_t []) { 6, 19, 22, 23 }, 4, ROLE_CUSTOMER,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

294

{ (const uint32_t []) { 1, 5, 17, 13, 3, 14, 27 }, 7, ROLE_CUSTOMER,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

296

{ (const uint32_t []) { 27, 14, 3, 13, 17, 5, 1 }, 7, ROLE_CUSTOMER,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

299

{ (const uint32_t []) { 27, 14, 3, 6, 7, 19, 17, 5, 1 }, 9,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

301

{ (const uint32_t []) { 27, 14, 3, 7, 19, 6, 1, 5, 17 }, 9,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

305

{ (const uint32_t []) { 201, 202, 203, 103, 102, 101 }, 6,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

307

{ (const uint32_t []) { 101, 102, 103, 203, 202, 201 }, 6,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

311

{ (const uint32_t []) { 201, 202, 203, 111, 103, 102, 101 }, 7,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

313

{ (const uint32_t []) { 101, 102, 103, 111, 203, 202, 201 }, 7,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

316

{ (const uint32_t []) { 201, 202, 203, 112, 103, 102, 101 }, 7,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

318

{ (const uint32_t []) { 101, 102, 103, 112, 203, 202, 201 }, 7,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

322

{ (const uint32_t []) { 201, 202, 204, 104, 102, 101 }, 6,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

325

{ (const uint32_t []) { 201, 202, 204, 105, 102, 101 }, 6,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

328

{ (const uint32_t []) { 201, 202, 205, 104, 102, 101 }, 6,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

331

{ (const uint32_t []) { 201, 202, 205, 105, 102, 101 }, 6,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

335

{ (const uint32_t []) { 201, 202, 205, 111, 105, 102, 101 }, 7,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

338

{ (const uint32_t []) { 201, 202, 205, 112, 105, 102, 101 }, 7,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

34

uint32_t customeras;

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

341

{ (const uint32_t []) { 201, 202, 205, 113, 105, 102, 101 }, 7,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

345

{ (const uint32_t []) { 201, 202, 205, 111, 104, 102, 101 }, 7,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

348

{ (const uint32_t []) { 201, 202, 204, 111, 105, 102, 101 }, 7,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

35

const uint32_t *providers;

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

351

{ (const uint32_t []) { 201, 202, 204, 111, 104, 102, 101 }, 7,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

354

{ (const uint32_t []) { 201, 202, 205, 112, 104, 102, 101 }, 7,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

357

{ (const uint32_t []) { 201, 202, 204, 112, 105, 102, 101 }, 7,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

36

uint32_t pascnt;

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

360

{ (const uint32_t []) { 201, 202, 204, 112, 104, 102, 101 }, 7,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

363

{ (const uint32_t []) { 201, 202, 205, 113, 104, 102, 101 }, 7,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

366

{ (const uint32_t []) { 201, 202, 204, 113, 105, 102, 101 }, 7,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

369

{ (const uint32_t []) { 201, 202, 204, 113, 104, 102, 101 }, 7,

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

374

load_test_set(struct aspa_test_set *testv, uint32_t numentries)

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

378

uint32_t i;

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

381

data_size += testv[i].pascnt * sizeof(uint32_t);

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

40

uint32_t customeras;

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

41

uint32_t provideras;

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

46

const uint32_t *aspath;

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

47

uint32_t aspathcnt;

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

52

const uint32_t *aspath;

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

53

uint32_t aspathcnt;

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

541

uint32_t

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

545

uint32_t as;

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

550

ptr += 2 + sizeof(uint32_t) * pos;

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

551

memcpy(&as, ptr, sizeof(uint32_t));

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

556

build_aspath(const uint32_t *asns, uint32_t asncnt, int rev)

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

559

uint32_t i, idx, as;

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

569

len = 2 + sizeof(uint32_t) * asncnt;

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

595

sizeof(uint32_t));

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

60

{ 1, (const uint32_t []){ 4, 5, 6 }, 3 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

602

print_aspath(const uint32_t *asns, uint32_t asncnt)

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

606

uint32_t i;

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

61

{ 2, (const uint32_t []){ 10, 11 }, 2 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

62

{ 3, (const uint32_t []){ 1, 13, 14 }, 3 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

63

{ 4, (const uint32_t []){ 16, 24 }, 2 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

64

{ 5, (const uint32_t []){ 1, 17, 25 }, 3 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

65

{ 8, (const uint32_t []){ 0 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

66

{ 9, (const uint32_t []){ 2 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

67

{ 10, (const uint32_t []){ 0 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

68

{ 11, (const uint32_t []){ 2 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

69

{ 12, (const uint32_t []){ 3 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

70

{ 13, (const uint32_t []){ 0 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

71

{ 14, (const uint32_t []){ 3, 25 }, 2 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

72

{ 15, (const uint32_t []){ 4 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

73

{ 16, (const uint32_t []){ 4 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

74

{ 17, (const uint32_t []){ 5 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

75

{ 18, (const uint32_t []){ 6 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

76

{ 20, (const uint32_t []){ 19 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

77

{ 21, (const uint32_t []){ 0 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

78

{ 23, (const uint32_t []){ 22 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

79

{ 24, (const uint32_t []){ 0 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

80

{ 25, (const uint32_t []){ 0 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

81

{ 26, (const uint32_t []){ 5 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

82

{ 27, (const uint32_t []){ 14 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

84

{ 101, (const uint32_t []){ 102 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

85

{ 102, (const uint32_t []){ 103, 104, 105 }, 3 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

86

{ 103, (const uint32_t []){ 111, 112, 203 }, 3 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

88

{ 105, (const uint32_t []){ 0 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

91

{ 112, (const uint32_t []){ 0 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

92

{ 113, (const uint32_t []){ 104, 105, 204, 205 }, 4 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

94

{ 121, (const uint32_t []){ 131, 132, 133 }, 3 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

95

{ 123, (const uint32_t []){ 0 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

96

{ 131, (const uint32_t []){ 121, 122, 123 }, 3 },

regress/usr.sbin/bgpd/unittests/rde_aspa_test.c

97

{ 133, (const uint32_t []){ 0 }, 1 },

regress/usr.sbin/bgpd/unittests/rde_decide_test.c

334

uint32_t

regress/usr.sbin/bgpd/unittests/rde_decide_test.c

347

as_set_match(const struct as_set *aset, uint32_t asnum)

regress/usr.sbin/bgpd/unittests/rde_decide_test.c

360

uint32_t old_pathid_tx, enum eval_mode mode)

regress/usr.sbin/bgpd/unittests/rde_decide_test.c

68

uint32_t source_as;

regress/usr.sbin/bgpd/unittests/rde_sets_test.c

29

uint32_t va[] = { 19, 14, 32, 76, 125 };

regress/usr.sbin/bgpd/unittests/rde_sets_test.c

30

uint32_t vaa[] = { 125, 14, 76, 32, 19 };

regress/usr.sbin/bgpd/unittests/rde_sets_test.c

31

uint32_t vb[] = { 256, 1024, 512, 4096, 2048, 512 };

regress/usr.sbin/bgpd/unittests/rde_sets_test.c

32

uint32_t vc[] = { 42 };

regress/usr.sbin/bgpd/unittests/rde_sets_test.c

37

build_set(const char *name, uint32_t *mem, size_t nmemb, size_t initial)

regress/usr.sbin/bgpd/unittests/rde_trie_test.c

182

uint32_t as;

regress/usr.sbin/bgpd/unittests/rde_trie_test.c

262

uint32_t as;

regress/usr.sbin/snmpd/agentx.c

1036

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1037

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/agentx.c

104

uint8_t, uint32_t, enum error, uint16_t, struct varbind *, size_t);

regress/usr.sbin/snmpd/agentx.c

107

static void message_add_uint32(struct message *, uint32_t);

regress/usr.sbin/snmpd/agentx.c

1085

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1086

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

109

static void message_add_nstring(struct message *, const void *, uint32_t);

regress/usr.sbin/snmpd/agentx.c

110

static void message_add_oid(struct message *, const uint32_t[], uint8_t,

regress/usr.sbin/snmpd/agentx.c

1113

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1114

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

114

uint32_t, uint32_t, uint32_t);

regress/usr.sbin/snmpd/agentx.c

1143

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1144

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

1170

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1171

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

1199

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1200

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

1228

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1229

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

1257

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1258

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

1286

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

130

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1314

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1315

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

1346

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1347

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

1378

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1379

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

1411

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1412

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

1442

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1443

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

1474

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1475

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

1506

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1507

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

1538

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1539

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

157

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1581

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1582

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/agentx.c

1630

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1631

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

1674

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1675

uint32_t sessionid, upperbound = 10;

regress/usr.sbin/snmpd/agentx.c

1705

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1706

uint32_t sessionid, upperbound = 1;

regress/usr.sbin/snmpd/agentx.c

1736

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1737

uint32_t sessionid, upperbound = 1;

regress/usr.sbin/snmpd/agentx.c

1767

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1768

uint32_t sessionid, upperbound = 10;

regress/usr.sbin/snmpd/agentx.c

1812

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1813

uint32_t sessionid, upperbound = 10;

regress/usr.sbin/snmpd/agentx.c

1857

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1858

uint32_t sessionid, upperbound = 10;

regress/usr.sbin/snmpd/agentx.c

190

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1903

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1904

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

1946

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1947

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

1989

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

1990

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

2019

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

2047

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

2048

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

2079

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

2080

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

2111

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

2112

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

214

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

2145

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

2146

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/agentx.c

215

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

2183

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

2184

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

2186

uint32_t upperbound = 10;

regress/usr.sbin/snmpd/agentx.c

2219

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

2220

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

2253

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

2254

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

2256

uint32_t upperbound = 5;

regress/usr.sbin/snmpd/agentx.c

2289

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

2290

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

2292

uint32_t upperbound = 10;

regress/usr.sbin/snmpd/agentx.c

2326

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

2327

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

2329

uint32_t upperbound = 10;

regress/usr.sbin/snmpd/agentx.c

2363

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

2364

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/agentx.c

2366

uint32_t upperbound = 10;

regress/usr.sbin/snmpd/agentx.c

2399

uint8_t flags, uint32_t sessionid, struct varbind *varbind,

regress/usr.sbin/snmpd/agentx.c

2405

uint32_t u32;

regress/usr.sbin/snmpd/agentx.c

2467

uint8_t flags, uint32_t sessionid, struct searchrange *searchrange,

regress/usr.sbin/snmpd/agentx.c

2473

uint32_t u32;

regress/usr.sbin/snmpd/agentx.c

2575

uint32_t u32;

regress/usr.sbin/snmpd/agentx.c

264

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

265

uint32_t oid[129];

regress/usr.sbin/snmpd/agentx.c

2667

uint32_t u32;

regress/usr.sbin/snmpd/agentx.c

2695

uint8_t flags, uint32_t packetid, enum error error, uint16_t index,

regress/usr.sbin/snmpd/agentx.c

2701

uint32_t u32;

regress/usr.sbin/snmpd/agentx.c

2811

uint32_t

regress/usr.sbin/snmpd/agentx.c

2812

agentx_open(int s, int nbo, uint8_t timeout, uint32_t oid[], size_t oidlen,

regress/usr.sbin/snmpd/agentx.c

2819

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

2841

agentx_close(int s, uint32_t sessionid, enum close_reason reason)

regress/usr.sbin/snmpd/agentx.c

2847

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

2864

agentx_register(int s, uint32_t sessionid, uint8_t instance, uint8_t timeout,

regress/usr.sbin/snmpd/agentx.c

2865

uint8_t priority, uint8_t range_subid, uint32_t oid[], size_t oidlen,

regress/usr.sbin/snmpd/agentx.c

2866

uint32_t upperbound)

regress/usr.sbin/snmpd/agentx.c

2871

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

2901

uint32_t sysuptime = 0;

regress/usr.sbin/snmpd/agentx.c

291

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

2938

message_add_uint32(struct message *msg, uint32_t n)

regress/usr.sbin/snmpd/agentx.c

2960

message_add_nstring(struct message *msg, const void *src, uint32_t len)

regress/usr.sbin/snmpd/agentx.c

2972

message_add_oid(struct message *msg, const uint32_t oid[], uint8_t n_subid,

regress/usr.sbin/snmpd/agentx.c

2997

uint32_t u32;

regress/usr.sbin/snmpd/agentx.c

3039

uint8_t flags, uint32_t sessionid, uint32_t transactionid,

regress/usr.sbin/snmpd/agentx.c

3040

uint32_t packetid)

regress/usr.sbin/snmpd/agentx.c

3080

uint32_t subid;

regress/usr.sbin/snmpd/agentx.c

320

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

348

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

377

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

405

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

433

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

460

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

482

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

483

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

508

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

509

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

534

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

535

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

561

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

562

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

586

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

587

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

612

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

613

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

638

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

639

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

664

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

665

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

690

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

691

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

720

uint32_t sessionid, packetid;

regress/usr.sbin/snmpd/agentx.c

755

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

780

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

781

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

79

#define p32toh(header, value) (uint32_t)(header->flags & NETWORK_BYTE_ORDER ? \

regress/usr.sbin/snmpd/agentx.c

810

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

811

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

840

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

841

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

870

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

871

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

89

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

90

uint32_t transactionid;

regress/usr.sbin/snmpd/agentx.c

900

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

901

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

91

uint32_t packetid;

regress/usr.sbin/snmpd/agentx.c

92

uint32_t payload_length;

regress/usr.sbin/snmpd/agentx.c

930

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

931

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

960

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

961

uint32_t sessionid;

regress/usr.sbin/snmpd/agentx.c

989

uint32_t packetid = arc4random();

regress/usr.sbin/snmpd/agentx.c

990

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

1027

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

1068

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

108

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

1111

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

1154

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

1197

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

1233

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

1280

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

1315

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

1362

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

1403

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

1444

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

145

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

1485

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

1524

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

1563

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

1603

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

1658

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

1701

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

1750

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

1793

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

183

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

1842

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

1891

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

1936

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

1985

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

2029

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

2074

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

2117

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

2161

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

220

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

2221

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

2279

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

2338

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

2407

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

2472

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

2517

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

2560

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

257

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

2605

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

2650

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

2695

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

2739

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

2785

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

2844

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

2908

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

294

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

2964

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

3025

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

3078

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

3131

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3176

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3226

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3282

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

33

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3343

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3413

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

342

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3450

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3493

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3547

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3615

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3650

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3685

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3720

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3755

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

379

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3790

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3825

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3860

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3895

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3930

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

3965

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4000

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4035

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4070

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4105

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4140

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

415

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4175

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4210

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4245

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4280

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4315

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4350

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4385

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4420

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4455

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4490

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

451

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4525

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4560

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4595

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4630

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4665

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4700

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4736

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4772

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4808

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4844

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

488

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4880

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4916

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4952

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

4988

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5024

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5060

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5096

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5132

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5168

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5204

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5240

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5276

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5312

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5348

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5384

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5420

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

544

uint32_t sessionid1, sessionid2;

regress/usr.sbin/snmpd/backend.c

5456

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5492

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5528

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5564

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5600

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5636

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5672

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5708

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5744

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5780

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5816

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

5852

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

598

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

654

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

70

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

707

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

765

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

801

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

832

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

871

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

910

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

949

uint32_t sessionid;

regress/usr.sbin/snmpd/backend.c

988

uint32_t sessionid;

regress/usr.sbin/snmpd/regress.h

125

.n_subid = (sizeof((uint32_t []) { __VA_ARGS__ }) / sizeof(uint32_t)) \

regress/usr.sbin/snmpd/regress.h

128

#define OID_ARG(...) (uint32_t []) { __VA_ARGS__ }, \

regress/usr.sbin/snmpd/regress.h

129

(sizeof((uint32_t []) { __VA_ARGS__ }) / sizeof(uint32_t))

regress/usr.sbin/snmpd/regress.h

155

uint32_t agentx_open(int, int, uint8_t, uint32_t[], size_t, const char *);

regress/usr.sbin/snmpd/regress.h

156

void agentx_close(int, uint32_t, enum close_reason);

regress/usr.sbin/snmpd/regress.h

157

void agentx_register(int, uint32_t, uint8_t, uint8_t, uint8_t, uint8_t,

regress/usr.sbin/snmpd/regress.h

158

uint32_t[], size_t, uint32_t);

regress/usr.sbin/snmpd/regress.h

161

void agentx_get_handle(const char *, const void *, size_t, uint8_t, uint32_t,

regress/usr.sbin/snmpd/regress.h

164

uint32_t, struct searchrange *, struct varbind *, size_t);

regress/usr.sbin/snmpd/regress.h

7

uint32_t subid[OID_MAX];

regress/usr.sbin/snmpd/regress.h

91

uint32_t uint32;

regress/usr.sbin/snmpd/snmp.c

130

uint32_t sessionid;

regress/usr.sbin/snmpd/snmp.c

39

(sizeof((uint32_t []){__VA_ARGS__}) / sizeof(uint32_t)) }

regress/usr.sbin/snmpd/transport.c

22

uint32_t sessionid;

regress/usr.sbin/snmpd/transport.c

59

uint32_t sessionid;

regress/usr.sbin/snmpd/transport.c

95

uint32_t sessionid;

sbin/dhcp6leased/control.c

277

if (IMSG_DATA_SIZE(imsg) != sizeof(uint32_t))

sbin/dhcp6leased/control.c

284

if (IMSG_DATA_SIZE(imsg) != sizeof(uint32_t))

sbin/dhcp6leased/dhcp6leased.c

1002

uint32_t i;

sbin/dhcp6leased/dhcp6leased.c

1189

uint32_t status;

sbin/dhcp6leased/dhcp6leased.c

428

uint32_t if_index;

sbin/dhcp6leased/dhcp6leased.c

637

imsg_compose_event(struct imsgev *iev, uint16_t type, uint32_t peerid,

sbin/dhcp6leased/dhcp6leased.c

76

void open_udpsock(uint32_t);

sbin/dhcp6leased/dhcp6leased.c

906

open_udpsock(uint32_t if_index)

sbin/dhcp6leased/dhcp6leased.h

114

uint32_t iaid;

sbin/dhcp6leased/dhcp6leased.h

115

uint32_t t1;

sbin/dhcp6leased/dhcp6leased.h

116

uint32_t t2;

sbin/dhcp6leased/dhcp6leased.h

120

uint32_t enterprise_number;

sbin/dhcp6leased/dhcp6leased.h

125

uint32_t pltime;

sbin/dhcp6leased/dhcp6leased.h

126

uint32_t vltime;

sbin/dhcp6leased/dhcp6leased.h

183

uint32_t vltime;

sbin/dhcp6leased/dhcp6leased.h

184

uint32_t pltime;

sbin/dhcp6leased/dhcp6leased.h

188

uint32_t if_index;

sbin/dhcp6leased/dhcp6leased.h

193

uint32_t lease_time;

sbin/dhcp6leased/dhcp6leased.h

194

uint32_t t1;

sbin/dhcp6leased/dhcp6leased.h

195

uint32_t t2;

sbin/dhcp6leased/dhcp6leased.h

217

uint32_t ia_count;

sbin/dhcp6leased/dhcp6leased.h

227

uint32_t if_index;

sbin/dhcp6leased/dhcp6leased.h

235

uint32_t if_index;

sbin/dhcp6leased/dhcp6leased.h

241

uint32_t if_index;

sbin/dhcp6leased/dhcp6leased.h

250

uint32_t if_index;

sbin/dhcp6leased/dhcp6leased.h

256

int imsg_compose_event(struct imsgev *, uint16_t, uint32_t,

sbin/dhcp6leased/engine.c

101

uint32_t if_index;

sbin/dhcp6leased/engine.c

112

uint32_t lease_time;

sbin/dhcp6leased/engine.c

113

uint32_t t1;

sbin/dhcp6leased/engine.c

114

uint32_t t2;

sbin/dhcp6leased/engine.c

124

void engine_showinfo_ctl(struct imsg *, uint32_t);

sbin/dhcp6leased/engine.c

126

struct dhcp6leased_iface *get_dhcp6leased_iface_by_id(uint32_t);

sbin/dhcp6leased/engine.c

127

void remove_dhcp6leased_iface(uint32_t);

sbin/dhcp6leased/engine.c

1318

uint32_t i;

sbin/dhcp6leased/engine.c

1386

uint32_t i;

sbin/dhcp6leased/engine.c

1431

uint32_t i;

sbin/dhcp6leased/engine.c

1496

uint32_t if_index;

sbin/dhcp6leased/engine.c

282

uint32_t if_index;

sbin/dhcp6leased/engine.c

601

engine_showinfo_ctl(struct imsg *imsg, uint32_t if_index)

sbin/dhcp6leased/engine.c

675

uint32_t i;

sbin/dhcp6leased/engine.c

697

get_dhcp6leased_iface_by_id(uint32_t if_index)

sbin/dhcp6leased/engine.c

709

remove_dhcp6leased_iface(uint32_t if_index)

sbin/dhcp6leased/engine.c

733

uint32_t t1, t2, lease_time;

sbin/dhcp6leased/engine.h

20

uint32_t if_index;

sbin/dhcp6leased/engine.h

23

uint32_t vltime;

sbin/dhcp6leased/engine.h

24

uint32_t pltime;

sbin/dhcp6leased/engine.h

28

uint32_t if_index;

sbin/dhcp6leased/frontend.c

227

frontend_imsg_compose_engine(int type, uint32_t peerid, pid_t pid,

sbin/dhcp6leased/frontend.c

554

update_iface(uint32_t if_index)

sbin/dhcp6leased/frontend.c

670

uint32_t if_index;

sbin/dhcp6leased/frontend.c

73

void update_iface(uint32_t);

sbin/dhcp6leased/frontend.c

79

struct iface *get_iface_by_id(uint32_t);

sbin/dhcp6leased/frontend.c

81

void remove_iface(uint32_t);

sbin/dhcp6leased/frontend.c

82

void set_udpsock(int, uint32_t);

sbin/dhcp6leased/frontend.c

941

get_iface_by_id(uint32_t if_index)

sbin/dhcp6leased/frontend.c

956

uint32_t ifidx = if_nametoindex(if_name);

sbin/dhcp6leased/frontend.c

964

remove_iface(uint32_t if_index)

sbin/dhcp6leased/frontend.c

982

set_udpsock(int udpsock, uint32_t if_index)

sbin/dhcp6leased/frontend.h

23

int frontend_imsg_compose_engine(int, uint32_t, pid_t, void *,

sbin/dhcpleased/checksum.c

49

uint32_t

sbin/dhcpleased/checksum.c

50

checksum(uint8_t *buf, uint32_t nbytes, uint32_t sum)

sbin/dhcpleased/checksum.c

75

uint32_t

sbin/dhcpleased/checksum.c

76

wrapsum(uint32_t sum)

sbin/dhcpleased/checksum.h

43

uint32_t checksum(uint8_t *, uint32_t, uint32_t);

sbin/dhcpleased/checksum.h

44

uint32_t wrapsum(uint32_t);

sbin/dhcpleased/control.c

232

uint32_t if_index, type;

sbin/dhcpleased/dhcpleased.c

1082

configure_route(uint8_t rtm_type, uint32_t if_index, int rdomain, struct

sbin/dhcpleased/dhcpleased.c

1207

open_bpfsock(uint32_t if_index)

sbin/dhcpleased/dhcpleased.c

1351

i2s(uint32_t type)

sbin/dhcpleased/dhcpleased.c

443

uint32_t if_index, type;

sbin/dhcpleased/dhcpleased.c

527

uint32_t type;

sbin/dhcpleased/dhcpleased.c

699

imsg_compose_event(struct imsgev *iev, uint16_t type, uint32_t peerid,

sbin/dhcpleased/dhcpleased.c

77

void open_bpfsock(uint32_t);

sbin/dhcpleased/dhcpleased.c

82

void configure_route(uint8_t, uint32_t, int, struct sockaddr_in *, struct

sbin/dhcpleased/dhcpleased.h

169

uint32_t xid; /* Transaction ID */

sbin/dhcpleased/dhcpleased.h

233

uint32_t if_index;

sbin/dhcpleased/dhcpleased.h

245

uint32_t lease_time;

sbin/dhcpleased/dhcpleased.h

246

uint32_t renewal_time;

sbin/dhcpleased/dhcpleased.h

247

uint32_t rebinding_time;

sbin/dhcpleased/dhcpleased.h

271

uint32_t if_index;

sbin/dhcpleased/dhcpleased.h

281

uint32_t if_index;

sbin/dhcpleased/dhcpleased.h

288

uint32_t if_index;

sbin/dhcpleased/dhcpleased.h

295

uint32_t if_index;

sbin/dhcpleased/dhcpleased.h

296

uint32_t xid;

sbin/dhcpleased/dhcpleased.h

305

int imsg_compose_event(struct imsgev *, uint16_t, uint32_t,

sbin/dhcpleased/dhcpleased.h

314

const char *i2s(uint32_t);

sbin/dhcpleased/engine.c

104

uint32_t cur_mtu;

sbin/dhcpleased/engine.c

105

uint32_t xid;

sbin/dhcpleased/engine.c

120

uint32_t lease_time;

sbin/dhcpleased/engine.c

121

uint32_t renewal_time;

sbin/dhcpleased/engine.c

122

uint32_t rebinding_time;

sbin/dhcpleased/engine.c

123

uint32_t ipv6_only_time;

sbin/dhcpleased/engine.c

134

void engine_showinfo_ctl(pid_t, uint32_t);

sbin/dhcpleased/engine.c

137

struct dhcpleased_iface *get_dhcpleased_iface_by_id(uint32_t);

sbin/dhcpleased/engine.c

138

void remove_dhcpleased_iface(uint32_t);

sbin/dhcpleased/engine.c

295

uint32_t if_index, type;

sbin/dhcpleased/engine.c

411

uint32_t type;

sbin/dhcpleased/engine.c

631

engine_showinfo_ctl(pid_t pid, uint32_t if_index)

sbin/dhcpleased/engine.c

706

get_dhcpleased_iface_by_id(uint32_t if_index)

sbin/dhcpleased/engine.c

718

remove_dhcpleased_iface(uint32_t if_index)

sbin/dhcpleased/engine.c

751

uint32_t lease_time = 0, renewal_time = 0;

sbin/dhcpleased/engine.c

752

uint32_t rebinding_time = 0;

sbin/dhcpleased/engine.c

753

uint32_t ipv6_only_time = 0;

sbin/dhcpleased/engine.c

98

uint32_t if_index;

sbin/dhcpleased/engine.h

20

uint32_t if_index;

sbin/dhcpleased/frontend.c

1134

IPPROTO_UDP + (uint32_t)ntohs(udp.uh_ulen)))));

sbin/dhcpleased/frontend.c

1157

get_iface_by_id(uint32_t if_index)

sbin/dhcpleased/frontend.c

1170

remove_iface(uint32_t if_index)

sbin/dhcpleased/frontend.c

1190

set_bpfsock(int bpfsock, uint32_t if_index)

sbin/dhcpleased/frontend.c

226

frontend_imsg_compose_engine(int type, uint32_t peerid, pid_t pid,

sbin/dhcpleased/frontend.c

243

uint32_t type;

sbin/dhcpleased/frontend.c

483

uint32_t type;

sbin/dhcpleased/frontend.c

594

uint32_t if_index;

sbin/dhcpleased/frontend.c

677

uint32_t if_index;

sbin/dhcpleased/frontend.c

72

uint32_t xid;

sbin/dhcpleased/frontend.c

797

uint32_t if_index;

sbin/dhcpleased/frontend.c

91

struct iface *get_iface_by_id(uint32_t);

sbin/dhcpleased/frontend.c

911

build_packet(uint8_t message_type, char *if_name, uint32_t xid,

sbin/dhcpleased/frontend.c

92

void remove_iface(uint32_t);

sbin/dhcpleased/frontend.c

93

void set_bpfsock(int, uint32_t);

sbin/dhcpleased/frontend.c

95

ssize_t build_packet(uint8_t, char *, uint32_t, struct ether_addr *,

sbin/dhcpleased/frontend.h

23

int frontend_imsg_compose_engine(int, uint32_t, pid_t, void *,

sbin/fdisk/cmd.c

307

uint32_t status;

sbin/fdisk/disk.c

120

readsectors(const uint64_t sector, const uint32_t count)

sbin/fdisk/disk.c

162

writesectors(const void *buf, const uint64_t sector, const uint32_t count)

sbin/fdisk/disk.c

200

uint32_t count;

sbin/fdisk/disk.c

218

uint32_t count;

sbin/fdisk/disk.c

41

char *readsectors(const uint64_t, const uint32_t);

sbin/fdisk/disk.c

42

int writesectors(const void *, const uint64_t, const uint32_t);

sbin/fdisk/disk.h

23

uint32_t dk_cylinders;

sbin/fdisk/disk.h

24

uint32_t dk_heads;

sbin/fdisk/disk.h

25

uint32_t dk_sectors;

sbin/fdisk/disk.h

26

uint32_t dk_size;

sbin/fdisk/fdisk.c

246

uint32_t blockcount, blockoffset;

sbin/fdisk/gpt.c

100

uint32_t psize;

sbin/fdisk/gpt.c

1081

uint32_t

sbin/fdisk/gpt.c

1082

crc32(const u_char *buf, const uint32_t size)

sbin/fdisk/gpt.c

1085

uint32_t i, byte, crc, mask;

sbin/fdisk/gpt.c

271

uint32_t gh_part_csum;

sbin/fdisk/gpt.c

489

uint32_t status;

sbin/fdisk/gpt.c

56

uint32_t crc32(const u_char *, const uint32_t);

sbin/fdisk/gpt.c

581

uint32_t status;

sbin/fdisk/gpt.c

649

uint32_t status, pn;

sbin/fdisk/gpt.c

701

uint32_t status;

sbin/fdisk/misc.c

262

uint32_t

sbin/fdisk/misc.c

265

uint32_t status;

sbin/fdisk/misc.h

44

uint32_t string_to_uuid(const char *, struct uuid *);

sbin/fdisk/part.c

1071

uint32_t status;

sbin/fdisk/part.c

755

uint32_t head = chs->chs_head;

sbin/fdisk/part.c

756

uint32_t sect = chs->chs_sect;

sbin/fdisk/part.c

776

uint32_t status;

sbin/fdisk/part.c

947

uint32_t t;

sbin/fdisk/part.c

957

memcpy(&t, &dp->dp_start, sizeof(uint32_t));

sbin/fdisk/part.c

959

memcpy(&t, &dp->dp_size, sizeof(uint32_t));

sbin/fdisk/part.c

990

memcpy(&dp->dp_start, &t, sizeof(uint32_t));

sbin/fdisk/part.c

996

memcpy(&dp->dp_size, &t, sizeof(uint32_t));

sbin/fdisk/part.h

21

uint32_t chs_head;

sbin/fdisk/part.h

22

uint32_t chs_sect;

sbin/fsck_ffs/setup.c

610

uint32_t sblockloc)

sbin/fsck_ffs/setup.c

64

int calcsb(char *, int, struct fs *, struct disklabel *, uint32_t);

sbin/fsck_ffs/setup.c

90

uint32_t cg, inopb;

sbin/growfs/growfs.c

105

(uint32_t)(dp)->dp1.field : (dp)->dp2.field)

sbin/ifconfig/ifconfig.c

2440

print_assoc_failures(uint32_t assoc_fail)

sbin/iked/config.c

1251

config_setradcfgmap(struct iked *env, int cfg_type, uint32_t vendor_id,

sbin/iked/control.c

39

uint32_t ctl_peerid;

sbin/iked/crypto.c

150

uint32_t sc_flags;

sbin/iked/crypto_api.h

19

typedef uint32_t crypto_uint32;

sbin/iked/dh.c

301

group_get(uint32_t id)

sbin/iked/dh.c

355

group_getid(uint32_t id)

sbin/iked/dh.h

61

struct dh_group *group_get(uint32_t);

sbin/iked/dh.h

63

*group_getid(uint32_t);

sbin/iked/iked.h

100

uint32_t peerid;

sbin/iked/iked.h

1044

int config_setradcfgmap(struct iked *, int, uint32_t, uint8_t);

sbin/iked/iked.h

1188

uint32_t, uint8_t, uint8_t, uint8_t);

sbin/iked/iked.h

1215

uint32_t

sbin/iked/iked.h

1282

int pfkey_sa_init(struct iked *, struct iked_childsa *, uint32_t *);

sbin/iked/iked.h

1324

int imsg_compose_event(struct imsgev *, uint16_t, uint32_t,

sbin/iked/iked.h

1326

int imsg_composev_event(struct imsgev *, uint16_t, uint32_t,

sbin/iked/iked.h

1329

uint16_t, uint32_t, int, void *, uint16_t);

sbin/iked/iked.h

1333

uint16_t, uint32_t, int, const struct iovec *, int);

sbin/iked/iked.h

1372

prefixlen2mask6(uint8_t, uint32_t *);

sbin/iked/iked.h

1373

uint32_t

sbin/iked/iked.h

277

uint32_t pol_peerdh;

sbin/iked/iked.h

300

uint32_t pol_rekey; /* ike SA lifetime */

sbin/iked/iked.h

345

uint32_t dsa_flags; /* State flags */

sbin/iked/iked.h

419

uint32_t sa_msgid; /* Last request rcvd */

sbin/iked/iked.h

421

uint32_t sa_msgid_current; /* Current requested rcvd */

sbin/iked/iked.h

422

uint32_t sa_reqid; /* Next request sent */

sbin/iked/iked.h

51

uint32_t ike_msgid; /* Message identifier */

sbin/iked/iked.h

52

uint32_t ike_length; /* Total message length */

sbin/iked/iked.h

618

uint32_t eam_state;

sbin/iked/iked.h

648

uint32_t msg_msgid;

sbin/iked/iked.h

765

uint32_t vendor_id;

sbin/iked/iked.h

874

uint32_t sc_opts;

sbin/iked/ikev2.c

1904

uint32_t msgid, uint8_t nextpayload,

sbin/iked/ikev2.c

1932

uint32_t hdrlength = sizeof(*hdr) + length;

sbin/iked/ikev2.c

1970

uint32_t av[4], bv[4], mv[4];

sbin/iked/ikev2.c

2151

uint32_t spi;

sbin/iked/ikev2.c

2335

uint32_t rnd;

sbin/iked/ikev2.c

2482

uint32_t mask4;

sbin/iked/ikev2.c

2674

uint32_t spi32, spi = 0;

sbin/iked/ikev2.c

3089

uint32_t spi32;

sbin/iked/ikev2.c

3575

uint32_t spi32;

sbin/iked/ikev2.c

4150

uint32_t spi;

sbin/iked/ikev2.c

4286

spi = htobe32((uint32_t)csa->csa_peerspi);

sbin/iked/ikev2.c

4452

uint32_t spi32;

sbin/iked/ikev2.c

5256

diff = (uint32_t)(gettime() - last_used);

sbin/iked/ikev2.c

5271

diff = (uint32_t)(gettime() - sa->sa_last_recvd);

sbin/iked/ikev2.c

6129

uint32_t spi32;

sbin/iked/ikev2.c

6186

uint32_t spi = 0;

sbin/iked/ikev2.c

6915

uint32_t spi32;

sbin/iked/ikev2.c

7166

uint32_t mask, host, lower, upper, start, nhost;

sbin/iked/ikev2.c

7296

memcpy(&lower, &cfg6->sin6_addr.s6_addr[12], sizeof(uint32_t));

sbin/iked/ikev2.c

7325

sizeof(uint32_t));

sbin/iked/ikev2.c

7328

sizeof(uint32_t));

sbin/iked/ikev2_msg.c

276

uint32_t natt = 0x00000000;

sbin/iked/ikev2_msg.c

359

uint32_t

sbin/iked/ikev2_msg.c

362

uint32_t id = sa->sa_reqid;

sbin/iked/ikev2_msg.c

63

uint32_t natt = 0x00000000;

sbin/iked/ikev2_msg.c

826

uint32_t msgid;

sbin/iked/ikev2_pld.c

1054

uint32_t spi32;

sbin/iked/ikev2_pld.c

348

uint32_t spi32;

sbin/iked/parse.y

2717

uint32_t ikelifetime, struct iked_lifetime *lt,

sbin/iked/parse.y

385

uint32_t, struct iked_lifetime *,

sbin/iked/parse.y

437

uint32_t vendorid;

sbin/iked/pfkey.c

1062

uint32_t *spip)

sbin/iked/pfkey.c

107

int pfkey_sa_getspi(struct iked *, uint8_t, struct iked_childsa *, uint32_t *);

sbin/iked/pfkey.c

1438

hdr.sadb_msg_pid == (uint32_t)getpid())

sbin/iked/pfkey.c

1443

hdr.sadb_msg_pid != (uint32_t)getpid()) {

sbin/iked/pfkey.c

1519

pfkey_sa_init(struct iked *env, struct iked_childsa *sa, uint32_t *spi)

sbin/iked/pfkey.c

232

(uint32_t *)((struct sockaddr_in6 *)

sbin/iked/pfkey.c

259

(uint32_t *)((struct sockaddr_in6 *)

sbin/iked/pfkey.c

479

uint32_t ifminor;

sbin/iked/pfkey.c

480

uint32_t jitter;

sbin/iked/pfkey.c

52

static uint32_t sadb_msg_seq = 0;

sbin/iked/proc.c

748

imsg_compose_event(struct imsgev *iev, uint16_t type, uint32_t peerid,

sbin/iked/proc.c

761

imsg_composev_event(struct imsgev *iev, uint16_t type, uint32_t peerid,

sbin/iked/proc.c

788

uint16_t type, uint32_t peerid, int fd, void *data, uint16_t datalen)

sbin/iked/proc.c

811

uint16_t type, uint32_t peerid, int fd, const struct iovec *iov, int iovcnt)

sbin/iked/radius.c

48

int, uint32_t, uint8_t);

sbin/iked/radius.c

536

int cfg_type, uint32_t vendor_id, uint8_t attr_type)

sbin/iked/radius.c

829

uint32_t u32, cause = 0;

sbin/iked/util.c

227

uint32_t av[4], bv[4], mv[4];

sbin/iked/util.c

420

snprintf(ptr, 32, "0x%08x", (uint32_t)spi);

sbin/iked/util.c

611

uint32_t

sbin/iked/util.c

624

prefixlen2mask6(uint8_t prefixlen, uint32_t *mask)

sbin/iked/vroute.c

254

(uint32_t *)&mask6.sin6_addr.s6_addr);

sbin/iked/vroute.c

43

int vroute_setroute(struct iked *, uint32_t, struct sockaddr *, uint8_t,

sbin/iked/vroute.c

519

vroute_setroute(struct iked *env, uint32_t rdomain, struct sockaddr *dst,

sbin/iked/vroute.c

556

(uint32_t *)in6->sin6_addr.s6_addr);

sbin/iked/vroute.c

581

uint32_t rdomain;

sbin/iked/vroute.c

655

uint32_t rdomain;

sbin/ipsecctl/parse.y

233

uint32_t unit;

sbin/ipsecctl/pfkdump.c

268

print_flags(uint32_t flags)

sbin/ipsecctl/pfkdump.c

72

static char *print_flags(uint32_t);

sbin/newfs/mkfs.c

172

uint32_t bpg;

sbin/newfs_ext2fs/mke2fs.c

1033

uint32_t *dindir_block, *reserved_gdb;

sbin/newfs_ext2fs/mke2fs.c

1228

uint32_t

sbin/newfs_ext2fs/mke2fs.c

1229

alloc(uint32_t size, uint16_t mode)

sbin/newfs_ext2fs/mke2fs.c

1231

uint32_t loc, bno;

sbin/newfs_ext2fs/mke2fs.c

128

static uint32_t alloc(uint32_t, uint16_t);

sbin/newfs_ext2fs/mke2fs.c

760

uint32_t oldfs[SBSIZE / sizeof(uint32_t)];

sbin/newfs_ext2fs/mke2fs.c

762

uint32_t offset;

sbin/newfs_ext2fs/mke2fs.c

763

uint32_t magic;

sbin/newfs_ext2fs/mke2fs.c

764

uint32_t mask;

sbin/newfs_ext2fs/mke2fs.c

810

uint32_t v;

sbin/pdisk/dump.c

202

uint32_t t;

sbin/pdisk/file_media.c

179

uint32_t tmp32;

sbin/pdisk/file_media.c

302

uint32_t tmp32;

sbin/pdisk/partition_map.c

148

uint32_t limit, base, next, nextbase;

sbin/pdisk/partition_map.c

261

create_partition_map(int fd, char *name, u_int64_t mediasz, uint32_t sectorsz)

sbin/pdisk/partition_map.c

296

add_partition_to_map(const char *name, const char *dptype, uint32_t base,

sbin/pdisk/partition_map.c

297

uint32_t length, struct partition_map *map)

sbin/pdisk/partition_map.c

301

uint32_t old_base, old_length, old_address;

sbin/pdisk/partition_map.c

302

uint32_t new_base, new_length;

sbin/pdisk/partition_map.c

384

const char *dptype, uint32_t base, uint32_t length)

sbin/pdisk/partition_map.c

451

uint32_t base, length, address;

sbin/pdisk/partition_map.c

489

uint32_t start;

sbin/pdisk/partition_map.c

509

uint32_t end;

sbin/pdisk/partition_map.c

51

const char *, uint32_t, uint32_t);

sbin/pdisk/partition_map.c

60

open_partition_map(int fd, char *name, uint64_t mediasz, uint32_t sectorsz)

sbin/pdisk/partition_map.c

610

find_entry_by_base(uint32_t base, struct partition_map *map)

sbin/pdisk/partition_map.c

690

uint32_t start;

sbin/pdisk/partition_map.c

773

uint32_t start;

sbin/pdisk/partition_map.h

100

uint32_t dpme_checksum; /* of the boot code. */

sbin/pdisk/partition_map.h

113

struct partition_map *create_partition_map(int, char *, uint64_t, uint32_t);

sbin/pdisk/partition_map.h

114

struct partition_map *open_partition_map(int, char *, uint64_t, uint32_t);

sbin/pdisk/partition_map.h

118

struct entry *find_entry_by_base(uint32_t, struct partition_map *);

sbin/pdisk/partition_map.h

120

int add_partition_to_map(const char *, const char *, uint32_t, uint32_t,

sbin/pdisk/partition_map.h

39

uint32_t ddBlock; /* 1st driver's starting sbBlkSize block */

sbin/pdisk/partition_map.h

59

uint32_t sbBlkCount; /* # of physical blocks on device */

sbin/pdisk/partition_map.h

62

uint32_t sbData; /* not used */

sbin/pdisk/partition_map.h

77

uint32_t dpme_map_entries; /* # of partition entries */

sbin/pdisk/partition_map.h

78

uint32_t dpme_pblock_start; /* physical block start of partition */

sbin/pdisk/partition_map.h

79

uint32_t dpme_pblocks; /* physical block count of partition */

sbin/pdisk/partition_map.h

82

uint32_t dpme_lblock_start; /* logical block start of partition */

sbin/pdisk/partition_map.h

83

uint32_t dpme_lblocks; /* logical block count of partition */

sbin/pdisk/partition_map.h

84

uint32_t dpme_flags;

sbin/pdisk/partition_map.h

94

uint32_t dpme_boot_block; /* logical block start of boot code */

sbin/pdisk/partition_map.h

95

uint32_t dpme_boot_bytes; /* byte count of boot code */

sbin/pdisk/partition_map.h

98

uint32_t dpme_goto_addr; /* memory jump address of boot code */

sbin/pfctl/parse.y

360

uint32_t id;

sbin/pfctl/parse.y

381

uint32_t id;

sbin/pfctl/pfctl.c

1103

uint32_t id = PF_SOURCELIM_ID_MIN;

sbin/pfctl/pfctl.c

1928

uint32_t ticket;

sbin/pfctl/pfctl.c

3549

uint32_t ida = a->ioc.id;

sbin/pfctl/pfctl.c

3550

uint32_t idb = b->ioc.id;

sbin/pfctl/pfctl.c

3592

pfctl_get_statelim_id(struct pfctl *pf, uint32_t id)

sbin/pfctl/pfctl.c

3617

uint32_t ida = a->ioc.id;

sbin/pfctl/pfctl.c

3618

uint32_t idb = b->ioc.id;

sbin/pfctl/pfctl.c

3661

pfctl_get_sourcelim_id(struct pfctl *pf, uint32_t id)

sbin/pfctl/pfctl.c

926

uint32_t id = PF_STATELIM_ID_MIN;

sbin/pfctl/pfctl.c

975

uint32_t val, inc;

sbin/pfctl/pfctl_parser.h

251

pfctl_get_statelim_id(struct pfctl *, uint32_t);

sbin/pfctl/pfctl_parser.h

256

pfctl_get_sourcelim_id(struct pfctl *, uint32_t);

sbin/resolvd/resolvd.c

58

uint32_t if_index;

sbin/slaacd/control.c

233

uint32_t if_index, type;

sbin/slaacd/engine.c

1046

uint32_t lifetime;

sbin/slaacd/engine.c

1127

uint32_t lifetime;

sbin/slaacd/engine.c

1204

uint32_t lifetime;

sbin/slaacd/engine.c

128

uint32_t vltime;

sbin/slaacd/engine.c

129

uint32_t pltime;

sbin/slaacd/engine.c

144

uint32_t min_lifetime;

sbin/slaacd/engine.c

150

uint32_t reachable_time; /* in milliseconds */

sbin/slaacd/engine.c

151

uint32_t retrans_time; /* in milliseconds */

sbin/slaacd/engine.c

153

uint32_t rdns_lifetime;

sbin/slaacd/engine.c

155

uint32_t mtu;

sbin/slaacd/engine.c

167

uint32_t if_index;

sbin/slaacd/engine.c

175

uint32_t vltime;

sbin/slaacd/engine.c

176

uint32_t pltime;

sbin/slaacd/engine.c

177

uint32_t desync_factor;

sbin/slaacd/engine.c

179

uint32_t mtu;

sbin/slaacd/engine.c

190

uint32_t if_index;

sbin/slaacd/engine.c

193

uint32_t router_lifetime;

sbin/slaacd/engine.c

1938

uint32_t pltime, vltime;

sbin/slaacd/engine.c

205

uint32_t if_index;

sbin/slaacd/engine.c

210

uint32_t rdns_lifetime;

sbin/slaacd/engine.c

220

uint32_t if_index;

sbin/slaacd/engine.c

221

uint32_t rdomain;

sbin/slaacd/engine.c

230

uint32_t cur_mtu;

sbin/slaacd/engine.c

2370

compose_rdns_proposal(uint32_t if_index, int rdomain)

sbin/slaacd/engine.c

245

void engine_showinfo_ctl(pid_t, uint32_t);

sbin/slaacd/engine.c

249

struct slaacd_iface *get_slaacd_iface_by_id(uint32_t);

sbin/slaacd/engine.c

250

void remove_slaacd_iface(uint32_t);

sbin/slaacd/engine.c

2673

uint32_t

sbin/slaacd/engine.c

2674

real_lifetime(struct timespec *received_uptime, uint32_t ltime)

sbin/slaacd/engine.c

282

void compose_rdns_proposal(uint32_t, int);

sbin/slaacd/engine.c

301

uint32_t real_lifetime(struct timespec *, uint32_t);

sbin/slaacd/engine.c

467

uint32_t if_index, type;

sbin/slaacd/engine.c

634

uint32_t type;

sbin/slaacd/engine.c

872

engine_showinfo_ctl(pid_t pid, uint32_t if_index)

sbin/slaacd/engine.c

889

get_slaacd_iface_by_id(uint32_t if_index)

sbin/slaacd/engine.c

901

remove_slaacd_iface(uint32_t if_index)

sbin/slaacd/engine.h

20

uint32_t if_index;

sbin/slaacd/engine.h

24

uint32_t vltime;

sbin/slaacd/engine.h

25

uint32_t pltime;

sbin/slaacd/engine.h

26

uint32_t mtu;

sbin/slaacd/engine.h

31

uint32_t if_index;

sbin/slaacd/engine.h

34

uint32_t router_lifetime;

sbin/slaacd/frontend.c

1002

send_solicitation(uint32_t if_index)

sbin/slaacd/frontend.c

1038

get_iface_by_id(uint32_t if_index)

sbin/slaacd/frontend.c

1051

remove_iface(uint32_t if_index)

sbin/slaacd/frontend.c

273

frontend_imsg_compose_engine(int type, uint32_t peerid, pid_t pid,

sbin/slaacd/frontend.c

287

uint32_t type;

sbin/slaacd/frontend.c

401

uint32_t if_index, type;

sbin/slaacd/frontend.c

504

update_iface(uint32_t if_index, char* if_name)

sbin/slaacd/frontend.c

74

uint32_t if_index;

sbin/slaacd/frontend.c

82

void update_iface(uint32_t, char*);

sbin/slaacd/frontend.c

91

struct iface *get_iface_by_id(uint32_t);

sbin/slaacd/frontend.c

92

void remove_iface(uint32_t);

sbin/slaacd/frontend.c

96

void send_solicitation(uint32_t);

sbin/slaacd/frontend.h

23

int frontend_imsg_compose_engine(int, uint32_t, pid_t, void *,

sbin/slaacd/slaacd.c

394

uint32_t type;

sbin/slaacd/slaacd.c

478

uint32_t type;

sbin/slaacd/slaacd.c

594

imsg_compose_event(struct imsgev *iev, uint16_t type, uint32_t peerid,

sbin/slaacd/slaacd.c

993

i2s(uint32_t type)

sbin/slaacd/slaacd.h

100

uint32_t reachable_time; /* in milliseconds */

sbin/slaacd/slaacd.h

101

uint32_t retrans_time; /* in milliseconds */

sbin/slaacd/slaacd.h

102

uint32_t mtu;

sbin/slaacd/slaacd.h

110

uint32_t vltime;

sbin/slaacd/slaacd.h

111

uint32_t pltime;

sbin/slaacd/slaacd.h

115

uint32_t lifetime;

sbin/slaacd/slaacd.h

129

uint32_t vltime;

sbin/slaacd/slaacd.h

130

uint32_t pltime;

sbin/slaacd/slaacd.h

140

uint32_t router_lifetime;

sbin/slaacd/slaacd.h

151

uint32_t rdns_lifetime;

sbin/slaacd/slaacd.h

159

uint32_t if_index;

sbin/slaacd/slaacd.h

167

uint32_t if_index;

sbin/slaacd/slaacd.h

180

uint32_t if_index;

sbin/slaacd/slaacd.h

185

uint32_t if_index;

sbin/slaacd/slaacd.h

190

uint32_t if_index;

sbin/slaacd/slaacd.h

197

uint32_t if_index;

sbin/slaacd/slaacd.h

203

int imsg_compose_event(struct imsgev *, uint16_t, uint32_t, pid_t,

sbin/slaacd/slaacd.h

208

const char *i2s(uint32_t);

sbin/slaacd/slaacd.h

82

uint32_t if_index;

sbin/unwind/frontend.h

31

uint32_t if_index;

sbin/unwind/libunbound/config.h

1547

uint32_t arc4random(void);

sbin/unwind/libunbound/config.h

1550

uint32_t arc4random_uniform(uint32_t upper_bound);

sbin/unwind/libunbound/config.h

1555

uint32_t arc4random(void);

sbin/unwind/libunbound/config.h

1562

uint32_t arc4random_uniform(uint32_t upper_bound);

sbin/unwind/libunbound/daemon/remote.h

228

uint32_t service_read_cmd;

sbin/unwind/libunbound/dns64/dns64.c

198

static uint32_t

sbin/unwind/libunbound/dns64/dns64.c

201

uint32_t ipv4 = 0;

sbin/unwind/libunbound/dns64/dns64.c

228

ipv4_to_ptr(uint32_t ipv4, char ptr[], size_t nm_len)

sbin/unwind/libunbound/iterator/iter_scrub.c

136

len = sldns_read_uint16(rr->ttl_data+sizeof(uint32_t));

sbin/unwind/libunbound/iterator/iter_scrub.c

139

*nm = rr->ttl_data+sizeof(uint32_t)+sizeof(uint16_t)+offset;

sbin/unwind/libunbound/iterator/iter_scrub.c

205

*sname = rrset->rr_first->ttl_data + sizeof(uint32_t)

sbin/unwind/libunbound/iterator/iter_scrub.c

283

sizeof(uint32_t)+sizeof(uint16_t)+aliaslen);

sbin/unwind/libunbound/iterator/iter_scrub.c

287

sizeof(uint32_t)); /* RFC6672: synth CNAME TTL == DNAME TTL */

sbin/unwind/libunbound/iterator/iter_scrub.c

303

*sname = cn->rr_first->ttl_data + sizeof(uint32_t)+sizeof(uint16_t);

sbin/unwind/libunbound/libunbound/context.c

240

context_serialize_new_query(struct ctx_query* q, uint32_t* len)

sbin/unwind/libunbound/libunbound/context.c

251

*len = sizeof(uint32_t)*4 + slen;

sbin/unwind/libunbound/libunbound/context.c

255

sldns_write_uint32(p+sizeof(uint32_t), (uint32_t)q->querynum);

sbin/unwind/libunbound/libunbound/context.c

256

sldns_write_uint32(p+2*sizeof(uint32_t), (uint32_t)q->res->qtype);

sbin/unwind/libunbound/libunbound/context.c

257

sldns_write_uint32(p+3*sizeof(uint32_t), (uint32_t)q->res->qclass);

sbin/unwind/libunbound/libunbound/context.c

258

memmove(p+4*sizeof(uint32_t), q->res->qname, slen);

sbin/unwind/libunbound/libunbound/context.c

263

context_deserialize_new_query(struct ub_ctx* ctx, uint8_t* p, uint32_t len)

sbin/unwind/libunbound/libunbound/context.c

267

if(len < 4*sizeof(uint32_t)+1) {

sbin/unwind/libunbound/libunbound/context.c

272

q->querynum = (int)sldns_read_uint32(p+sizeof(uint32_t));

sbin/unwind/libunbound/libunbound/context.c

280

q->res->qtype = (int)sldns_read_uint32(p+2*sizeof(uint32_t));

sbin/unwind/libunbound/libunbound/context.c

281

q->res->qclass = (int)sldns_read_uint32(p+3*sizeof(uint32_t));

sbin/unwind/libunbound/libunbound/context.c

282

q->res->qname = strdup((char*)(p+4*sizeof(uint32_t)));

sbin/unwind/libunbound/libunbound/context.c

296

context_lookup_new_query(struct ub_ctx* ctx, uint8_t* p, uint32_t len)

sbin/unwind/libunbound/libunbound/context.c

300

if(len < 4*sizeof(uint32_t)+1) {

sbin/unwind/libunbound/libunbound/context.c

304

querynum = (int)sldns_read_uint32(p+sizeof(uint32_t));

sbin/unwind/libunbound/libunbound/context.c

315

uint32_t* len)

sbin/unwind/libunbound/libunbound/context.c

328

size_t size_of_uint32s = 6 * sizeof(uint32_t);

sbin/unwind/libunbound/libunbound/context.c

336

sldns_write_uint32(p+sizeof(uint32_t), (uint32_t)q->querynum);

sbin/unwind/libunbound/libunbound/context.c

337

sldns_write_uint32(p+2*sizeof(uint32_t), (uint32_t)err);

sbin/unwind/libunbound/libunbound/context.c

338

sldns_write_uint32(p+3*sizeof(uint32_t), (uint32_t)q->msg_security);

sbin/unwind/libunbound/libunbound/context.c

339

sldns_write_uint32(p+4*sizeof(uint32_t), (uint32_t)q->res->was_ratelimited);

sbin/unwind/libunbound/libunbound/context.c

340

sldns_write_uint32(p+5*sizeof(uint32_t), (uint32_t)wlen);

sbin/unwind/libunbound/libunbound/context.c

351

uint8_t* p, uint32_t len, int* err)

sbin/unwind/libunbound/libunbound/context.c

353

size_t size_of_uint32s = 6 * sizeof(uint32_t);

sbin/unwind/libunbound/libunbound/context.c

359

id = (int)sldns_read_uint32(p+sizeof(uint32_t));

sbin/unwind/libunbound/libunbound/context.c

362

*err = (int)sldns_read_uint32(p+2*sizeof(uint32_t));

sbin/unwind/libunbound/libunbound/context.c

363

q->msg_security = sldns_read_uint32(p+3*sizeof(uint32_t));

sbin/unwind/libunbound/libunbound/context.c

364

q->res->was_ratelimited = (int)sldns_read_uint32(p+4*sizeof(uint32_t));

sbin/unwind/libunbound/libunbound/context.c

365

wlen = (size_t)sldns_read_uint32(p+5*sizeof(uint32_t));

sbin/unwind/libunbound/libunbound/context.c

393

context_serialize_cancel(struct ctx_query* q, uint32_t* len)

sbin/unwind/libunbound/libunbound/context.c

398

uint8_t* p = (uint8_t*)reallocarray(NULL, 2, sizeof(uint32_t));

sbin/unwind/libunbound/libunbound/context.c

400

*len = 2*sizeof(uint32_t);

sbin/unwind/libunbound/libunbound/context.c

402

sldns_write_uint32(p+sizeof(uint32_t), (uint32_t)q->querynum);

sbin/unwind/libunbound/libunbound/context.c

407

uint8_t* p, uint32_t len)

sbin/unwind/libunbound/libunbound/context.c

411

if(len != 2*sizeof(uint32_t)) return NULL;

sbin/unwind/libunbound/libunbound/context.c

413

id = (int)sldns_read_uint32(p+sizeof(uint32_t));

sbin/unwind/libunbound/libunbound/context.c

419

context_serialize_quit(uint32_t* len)

sbin/unwind/libunbound/libunbound/context.c

421

uint32_t* p = (uint32_t*)malloc(sizeof(uint32_t));

sbin/unwind/libunbound/libunbound/context.c

424

*len = sizeof(uint32_t);

sbin/unwind/libunbound/libunbound/context.c

429

enum ub_ctx_cmd context_serial_getcmd(uint8_t* p, uint32_t len)

sbin/unwind/libunbound/libunbound/context.c

431

uint32_t v;

sbin/unwind/libunbound/libunbound/context.h

260

uint8_t* context_serialize_new_query(struct ctx_query* q, uint32_t* len);

sbin/unwind/libunbound/libunbound/context.h

273

struct sldns_buffer* pkt, uint32_t* len);

sbin/unwind/libunbound/libunbound/context.h

282

uint8_t* context_serialize_cancel(struct ctx_query* q, uint32_t* len);

sbin/unwind/libunbound/libunbound/context.h

289

uint8_t* context_serialize_quit(uint32_t* len);

sbin/unwind/libunbound/libunbound/context.h

297

enum ub_ctx_cmd context_serial_getcmd(uint8_t* p, uint32_t len);

sbin/unwind/libunbound/libunbound/context.h

307

uint8_t* p, uint32_t len);

sbin/unwind/libunbound/libunbound/context.h

317

uint8_t* p, uint32_t len);

sbin/unwind/libunbound/libunbound/context.h

328

uint8_t* p, uint32_t len, int* err);

sbin/unwind/libunbound/libunbound/context.h

338

uint8_t* p, uint32_t len);

sbin/unwind/libunbound/libunbound/libunbound.c

269

uint32_t len;

sbin/unwind/libunbound/libunbound/libunbound.c

270

uint32_t cmd = UB_LIBCMD_QUIT;

sbin/unwind/libunbound/libunbound/libunbound.c

274

(uint32_t)sizeof(cmd), 0);

sbin/unwind/libunbound/libunbound/libunbound.c

586

process_answer_detail(struct ub_ctx* ctx, uint8_t* msg, uint32_t len,

sbin/unwind/libunbound/libunbound/libunbound.c

651

process_answer(struct ub_ctx* ctx, uint8_t* msg, uint32_t len)

sbin/unwind/libunbound/libunbound/libunbound.c

674

uint32_t len;

sbin/unwind/libunbound/libunbound/libunbound.c

702

uint32_t len;

sbin/unwind/libunbound/libunbound/libunbound.c

839

uint32_t len = 0;

sbin/unwind/libunbound/libunbound/libunbound.c

901

uint32_t len = 0;

sbin/unwind/libunbound/libunbound/libworker.c

199

hash_set_raninit((uint32_t)ub_random(w->env->rnd));

sbin/unwind/libunbound/libunbound/libworker.c

266

handle_cancel(struct libworker* w, uint8_t* buf, uint32_t len)

sbin/unwind/libunbound/libunbound/libworker.c

287

libworker_do_cmd(struct libworker* w, uint8_t* msg, uint32_t len)

sbin/unwind/libunbound/libunbound/libworker.c

331

uint32_t m;

sbin/unwind/libunbound/libunbound/libworker.c

367

(uint32_t)sizeof(m), 0);

sbin/unwind/libunbound/libunbound/libworker.c

740

uint32_t len = 0;

sbin/unwind/libunbound/libunbound/libworker.c

816

handle_newq(struct libworker* w, uint8_t* buf, uint32_t len)

sbin/unwind/libunbound/libunbound/libworker.c

88

static void handle_newq(struct libworker* w, uint8_t* buf, uint32_t len);

sbin/unwind/libunbound/services/authzone.c

1098

az_domain_add_rr(struct auth_data* node, uint16_t rr_type, uint32_t rr_ttl,

sbin/unwind/libunbound/services/authzone.c

1168

uint32_t rr_ttl = sldns_wirerr_get_ttl(rr, rr_len, dname_len);

sbin/unwind/libunbound/services/authzone.c

1320

uint32_t rr_ttl, uint8_t* rr_data, uint16_t rr_rdlen)

sbin/unwind/libunbound/services/authzone.c

1420

uint16_t rr_class, uint32_t rr_ttl, uint8_t* rr_data,

sbin/unwind/libunbound/services/authzone.c

1442

uint16_t rr_class, uint32_t rr_ttl, uint8_t* rr_data,

sbin/unwind/libunbound/services/authzone.c

1808

uint32_t* serial, int* scheme, int* hashalgo, uint8_t** hash,

sbin/unwind/libunbound/services/authzone.c

1843

uint32_t serial2 = 0;

sbin/unwind/libunbound/services/authzone.c

1885

uint32_t soa_serial = 0;

sbin/unwind/libunbound/services/authzone.c

1909

uint32_t serial = 0;

sbin/unwind/libunbound/services/authzone.c

1996

auth_zone_get_serial(struct auth_zone* z, uint32_t* serial)

sbin/unwind/libunbound/services/authzone.c

3655

auth_zone_parse_notify_serial(sldns_buffer* pkt, uint32_t *serial)

sbin/unwind/libunbound/services/authzone.c

3772

xfr_serial_means_update(struct auth_xfer* xfr, uint32_t serial)

sbin/unwind/libunbound/services/authzone.c

3787

xfr_note_notify_serial(struct auth_xfer* xfr, int has_serial, uint32_t serial)

sbin/unwind/libunbound/services/authzone.c

3812

int has_serial, uint32_t serial, struct auth_master* fromhost)

sbin/unwind/libunbound/services/authzone.c

3832

uint32_t serial, int* refused)

sbin/unwind/libunbound/services/authzone.c

4249

uint32_t serial;

sbin/unwind/libunbound/services/authzone.c

4301

uint32_t* serial)

sbin/unwind/libunbound/services/authzone.c

4755

uint16_t* rr_class, uint32_t* rr_ttl, uint16_t* rr_rdlen,

sbin/unwind/libunbound/services/authzone.c

4820

uint32_t rr_ttl, uint16_t rr_rdlen, uint8_t* rr_rdata,

sbin/unwind/libunbound/services/authzone.c

4821

size_t rr_nextpos, uint32_t transfer_serial, uint32_t xfr_serial)

sbin/unwind/libunbound/services/authzone.c

4823

uint32_t startserial;

sbin/unwind/libunbound/services/authzone.c

4875

uint32_t rr_ttl;

sbin/unwind/libunbound/services/authzone.c

4878

uint32_t transfer_serial = 0;

sbin/unwind/libunbound/services/authzone.c

4904

uint32_t serial;

sbin/unwind/libunbound/services/authzone.c

5012

uint32_t rr_ttl;

sbin/unwind/libunbound/services/authzone.c

5013

uint32_t serial = 0;

sbin/unwind/libunbound/services/authzone.c

5922

uint32_t serial;

sbin/unwind/libunbound/services/authzone.c

6098

uint32_t sr = xfr->notify_serial;

sbin/unwind/libunbound/services/authzone.c

6530

uint32_t serial = 0;

sbin/unwind/libunbound/services/authzone.c

7339

compare_serial(uint32_t a, uint32_t b)

sbin/unwind/libunbound/services/authzone.c

7341

const uint32_t cutoff = ((uint32_t) 1 << (SERIAL_BITS - 1));

sbin/unwind/libunbound/services/authzone.c

795

rrset_add_rr(struct auth_rrset* rrset, uint32_t rr_ttl, uint8_t* rdata,

sbin/unwind/libunbound/services/authzone.c

865

rrset_create(struct auth_data* node, uint16_t rr_type, uint32_t rr_ttl,

sbin/unwind/libunbound/services/authzone.h

253

uint32_t notify_serial;

sbin/unwind/libunbound/services/authzone.h

270

uint32_t serial;

sbin/unwind/libunbound/services/authzone.h

423

uint32_t incoming_xfr_serial;

sbin/unwind/libunbound/services/authzone.h

628

uint32_t serial, int* refused);

sbin/unwind/libunbound/services/authzone.h

632

int auth_zone_parse_notify_serial(struct sldns_buffer* pkt, uint32_t *serial);

sbin/unwind/libunbound/services/authzone.h

647

int auth_zone_get_serial(struct auth_zone* z, uint32_t* serial);

sbin/unwind/libunbound/services/authzone.h

710

int compare_serial(uint32_t a, uint32_t b);

sbin/unwind/libunbound/services/cache/dns.c

1060

struct regional* region, uint32_t flags, time_t qstarttime,

sbin/unwind/libunbound/services/cache/dns.c

157

struct reply_info* qrep, uint32_t flags, struct regional* region,

sbin/unwind/libunbound/services/cache/dns.c

369

struct regional* region, struct delegpt* dp, uint32_t flags)

sbin/unwind/libunbound/services/cache/dns.h

126

struct reply_info* qrep, uint32_t flags, struct regional* region,

sbin/unwind/libunbound/services/cache/dns.h

212

struct regional* region, struct delegpt* dp, uint32_t flags);

sbin/unwind/libunbound/services/cache/dns.h

99

struct regional* region, uint32_t flags, time_t qstarttime,

sbin/unwind/libunbound/services/cache/rrset.c

283

uint16_t qtype, uint16_t qclass, uint32_t flags, time_t timenow,

sbin/unwind/libunbound/services/cache/rrset.c

533

uint16_t type, uint16_t dclass, uint32_t flags)

sbin/unwind/libunbound/services/cache/rrset.h

170

uint32_t flags, time_t timenow, int wr);

sbin/unwind/libunbound/services/cache/rrset.h

275

uint16_t type, uint16_t dclass, uint32_t flags);

sbin/unwind/libunbound/services/listen_dnsport.c

1537

int harden_large_queries, uint32_t http_max_streams,

sbin/unwind/libunbound/services/listen_dnsport.c

2532

int32_t stream_id, uint8_t* buf, size_t length, uint32_t* data_flags,

sbin/unwind/libunbound/services/listen_dnsport.c

2714

int32_t stream_id, uint8_t* buf, size_t length, uint32_t* data_flags,

sbin/unwind/libunbound/services/listen_dnsport.c

3553

const uint8_t* dcid, size_t dcidlen, uint32_t version)

sbin/unwind/libunbound/services/listen_dnsport.c

4366

doq_recv_stream_data_cb(ngtcp2_conn* ATTR_UNUSED(conn), uint32_t flags,

sbin/unwind/libunbound/services/listen_dnsport.c

4413

doq_stream_close_cb(ngtcp2_conn* ATTR_UNUSED(conn), uint32_t flags,

sbin/unwind/libunbound/services/listen_dnsport.c

5356

uint32_t flags = 0;

sbin/unwind/libunbound/services/listen_dnsport.h

215

int harden_large_queries, uint32_t http_max_streams,

sbin/unwind/libunbound/services/listen_dnsport.h

594

uint32_t version;

sbin/unwind/libunbound/services/listen_dnsport.h

625

uint32_t close_ecn;

sbin/unwind/libunbound/services/listen_dnsport.h

711

uint32_t version);

sbin/unwind/libunbound/services/rpz.c

1002

enum rpz_action a, uint16_t rrtype, uint16_t rrclass, uint32_t ttl,

sbin/unwind/libunbound/services/rpz.c

1024

enum rpz_action a, uint16_t rrtype, uint16_t rrclass, uint32_t ttl,

sbin/unwind/libunbound/services/rpz.c

1047

enum rpz_action a, uint16_t rrtype, uint16_t rrclass, uint32_t ttl,

sbin/unwind/libunbound/services/rpz.c

1078

size_t dnamelen, uint16_t rr_type, uint16_t rr_class, uint32_t rr_ttl,

sbin/unwind/libunbound/services/rpz.c

661

uint32_t ttl, uint8_t* rdata, size_t rdata_len, uint8_t* rr, size_t rr_len)

sbin/unwind/libunbound/services/rpz.c

750

enum rpz_action a, uint16_t rrtype, uint16_t rrclass, uint32_t ttl,

sbin/unwind/libunbound/services/rpz.c

801

enum rpz_action a, uint16_t rrtype, uint16_t rrclass, uint32_t ttl,

sbin/unwind/libunbound/services/rpz.c

824

uint16_t rrclass, uint32_t ttl, uint8_t* rdata, size_t rdata_len,

sbin/unwind/libunbound/services/rpz.c

967

uint16_t rrclass, uint32_t ttl, uint8_t* rdata, size_t rdata_len,

sbin/unwind/libunbound/services/rpz.h

146

size_t dnamelen, uint16_t rr_type, uint16_t rr_class, uint32_t rr_ttl,

sbin/unwind/libunbound/sldns/keyraw.c

125

uint32_t ac32 = 0;

sbin/unwind/libunbound/sldns/parseutil.c

170

int32_t offset = (int32_t)((uint32_t) time - (uint32_t) now);

sbin/unwind/libunbound/sldns/parseutil.c

211

uint32_t

sbin/unwind/libunbound/sldns/parseutil.c

215

uint32_t i = 0;

sbin/unwind/libunbound/sldns/parseutil.c

216

uint32_t seconds = 0;

sbin/unwind/libunbound/sldns/parseutil.c

217

const uint32_t maxint = 0xffffffff;

sbin/unwind/libunbound/sldns/parseutil.h

81

uint32_t sldns_str2period(const char *nptr, const char **endptr, int* overflow);

sbin/unwind/libunbound/sldns/sbuffer.h

45

INLINE uint32_t

sbin/unwind/libunbound/sldns/sbuffer.h

49

return ntohl(*(const uint32_t *) src);

sbin/unwind/libunbound/sldns/sbuffer.h

52

return ( ((uint32_t) p[0] << 24)

sbin/unwind/libunbound/sldns/sbuffer.h

53

| ((uint32_t) p[1] << 16)

sbin/unwind/libunbound/sldns/sbuffer.h

54

| ((uint32_t) p[2] << 8)

sbin/unwind/libunbound/sldns/sbuffer.h

548

sldns_buffer_write_u32_at(sldns_buffer *buffer, size_t at, uint32_t data)

sbin/unwind/libunbound/sldns/sbuffer.h

55

| (uint32_t) p[3]);

sbin/unwind/libunbound/sldns/sbuffer.h

573

sldns_buffer_write_u32(sldns_buffer *buffer, uint32_t data)

sbin/unwind/libunbound/sldns/sbuffer.h

676

INLINE uint32_t

sbin/unwind/libunbound/sldns/sbuffer.h

679

assert(sldns_buffer_available_at(buffer, at, sizeof(uint32_t)));

sbin/unwind/libunbound/sldns/sbuffer.h

688

INLINE uint32_t

sbin/unwind/libunbound/sldns/sbuffer.h

691

uint32_t result = sldns_buffer_read_u32_at(buffer, buffer->_position);

sbin/unwind/libunbound/sldns/sbuffer.h

692

buffer->_position += sizeof(uint32_t);

sbin/unwind/libunbound/sldns/sbuffer.h

76

sldns_write_uint32(void *dst, uint32_t data)

sbin/unwind/libunbound/sldns/sbuffer.h

79

* (uint32_t *) dst = htonl(data);

sbin/unwind/libunbound/sldns/str2wire.c

1776

uint32_t r;

sbin/unwind/libunbound/sldns/str2wire.c

1780

r = (uint32_t)strtol((char*)str, &end, 10);

sbin/unwind/libunbound/sldns/str2wire.c

1781

else r = (uint32_t)strtoul((char*)str, &end, 10);

sbin/unwind/libunbound/sldns/str2wire.c

2172

sldns_write_uint32(rd, (uint32_t)sldns_mktime_from_utc(&tm));

sbin/unwind/libunbound/sldns/str2wire.c

2176

uint32_t l = (uint32_t)strtol((char*)str, &end, 10);

sbin/unwind/libunbound/sldns/str2wire.c

2191

uint32_t low;

sbin/unwind/libunbound/sldns/str2wire.c

2197

low = (uint32_t)(t);

sbin/unwind/libunbound/sldns/str2wire.c

2208

uint32_t p = sldns_str2period(str, &end, &overflow);

sbin/unwind/libunbound/sldns/str2wire.c

2225

uint32_t meters = 0, cm = 0, val;

sbin/unwind/libunbound/sldns/str2wire.c

2230

meters = (uint32_t)strtol(my_str, &my_str, 10);

sbin/unwind/libunbound/sldns/str2wire.c

2233

cm = (uint32_t)strtol(my_str, &cm_endstr, 10);

sbin/unwind/libunbound/sldns/str2wire.c

2262

uint32_t latitude = 0;

sbin/unwind/libunbound/sldns/str2wire.c

2263

uint32_t longitude = 0;

sbin/unwind/libunbound/sldns/str2wire.c

2264

uint32_t altitude = 0;

sbin/unwind/libunbound/sldns/str2wire.c

2266

uint32_t equator = (uint32_t)1<<31; /* 2**31 */

sbin/unwind/libunbound/sldns/str2wire.c

2269

uint32_t h = 0;

sbin/unwind/libunbound/sldns/str2wire.c

2270

uint32_t m = 0;

sbin/unwind/libunbound/sldns/str2wire.c

2282

h = (uint32_t) strtol(my_str, &my_str, 10);

sbin/unwind/libunbound/sldns/str2wire.c

2292

m = (uint32_t) strtol(my_str, &my_str, 10);

sbin/unwind/libunbound/sldns/str2wire.c

2327

latitude = (uint32_t) s;

sbin/unwind/libunbound/sldns/str2wire.c

2340

h = (uint32_t) strtol(my_str, &my_str, 10);

sbin/unwind/libunbound/sldns/str2wire.c

2350

m = (uint32_t) strtol(my_str, &my_str, 10);

sbin/unwind/libunbound/sldns/str2wire.c

2385

longitude = (uint32_t) s;

sbin/unwind/libunbound/sldns/str2wire.c

2395

altitude = (uint32_t)(strtod(my_str, &my_str)*100.0 +

sbin/unwind/libunbound/sldns/str2wire.c

249

int* not_there, uint32_t* ttl, uint32_t default_ttl)

sbin/unwind/libunbound/sldns/str2wire.c

257

*ttl = (uint32_t) sldns_str2period(token, &endptr, &overflow);

sbin/unwind/libunbound/sldns/str2wire.c

321

size_t dname_len, uint16_t tp, uint16_t cl, uint32_t ttl, int question)

sbin/unwind/libunbound/sldns/str2wire.c

899

size_t* dname_len, uint32_t default_ttl, uint8_t* origin,

sbin/unwind/libunbound/sldns/str2wire.c

905

uint32_t ttl = 0;

sbin/unwind/libunbound/sldns/str2wire.c

948

size_t* dname_len, uint32_t default_ttl, uint8_t* origin,

sbin/unwind/libunbound/sldns/str2wire.c

977

uint32_t sldns_wirerr_get_ttl(uint8_t* rr, size_t len, size_t dname_len)

sbin/unwind/libunbound/sldns/str2wire.h

105

size_t* dname_len, uint32_t default_ttl, uint8_t* origin,

sbin/unwind/libunbound/sldns/str2wire.h

153

uint32_t sldns_wirerr_get_ttl(uint8_t* rr, size_t len, size_t dname_len);

sbin/unwind/libunbound/sldns/str2wire.h

262

uint32_t default_ttl;

sbin/unwind/libunbound/sldns/wire2str.c

1014

uint32_t ttl;

sbin/unwind/libunbound/sldns/wire2str.c

1687

uint32_t t;

sbin/unwind/libunbound/sldns/wire2str.c

1726

uint32_t longitude;

sbin/unwind/libunbound/sldns/wire2str.c

1727

uint32_t latitude;

sbin/unwind/libunbound/sldns/wire2str.c

1728

uint32_t altitude;

sbin/unwind/libunbound/sldns/wire2str.c

1731

uint32_t h;

sbin/unwind/libunbound/sldns/wire2str.c

1732

uint32_t m;

sbin/unwind/libunbound/sldns/wire2str.c

1734

uint32_t equator = (uint32_t)1 << 31; /* 2**31 */

sbin/unwind/libunbound/sldns/wire2str.c

2130

uint32_t lease_life; /* Requested or granted life of LLQ, in seconds */

sbin/unwind/libunbound/sldns/wire2str.c

2166

uint32_t lease;

sbin/unwind/libunbound/sldns/wire2str.c

491

uint32_t ttl;

sbin/unwind/libunbound/util/config_file.c

570

cfg->val_date_override = (uint32_t)atoi(val);

sbin/unwind/libunbound/util/config_file.h

157

uint32_t http_max_streams;

sbin/unwind/libunbound/util/config_file.h

282

uint32_t max_ecs_tree_size_ipv4;

sbin/unwind/libunbound/util/config_file.h

283

uint32_t max_ecs_tree_size_ipv6;

sbin/unwind/libunbound/util/configlexer.c

54

typedef uint32_t flex_uint32_t;

sbin/unwind/libunbound/util/configparser.y

780

else cfg_parser->cfg->max_ecs_tree_size_ipv4 = (uint32_t)atoi($2);

sbin/unwind/libunbound/util/configparser.y

795

else cfg_parser->cfg->max_ecs_tree_size_ipv6 = (uint32_t)atoi($2);

sbin/unwind/libunbound/util/data/msgparse.c

159

static uint32_t

sbin/unwind/libunbound/util/data/msgparse.c

162

uint32_t f = 0;

sbin/unwind/libunbound/util/data/msgparse.c

173

uint16_t dclass, uint32_t rrset_flags)

sbin/unwind/libunbound/util/data/msgparse.c

181

h = hashlittle(&rrset_flags, sizeof(uint32_t), h);

sbin/unwind/libunbound/util/data/msgparse.c

200

uint32_t rrset_flags)

sbin/unwind/libunbound/util/data/msgparse.c

207

h = hashlittle(&rrset_flags, sizeof(uint32_t), h);

sbin/unwind/libunbound/util/data/msgparse.c

214

uint32_t rrset_flags, uint8_t* dname, size_t dnamelen,

sbin/unwind/libunbound/util/data/msgparse.c

227

hashvalue_type h, uint32_t rrset_flags, uint8_t* dname,

sbin/unwind/libunbound/util/data/msgparse.c

396

sldns_buffer* pkt, uint16_t datatype, uint32_t rrset_flags,

sbin/unwind/libunbound/util/data/msgparse.c

468

uint32_t* rrset_flags,

sbin/unwind/libunbound/util/data/msgparse.c

835

uint32_t rrset_flags = 0;

sbin/unwind/libunbound/util/data/msgparse.c

84

uint32_t rrset_flags, sldns_pkt_section section,

sbin/unwind/libunbound/util/data/msgparse.c

950

struct comm_reply* repinfo, uint32_t now, struct regional* region,

sbin/unwind/libunbound/util/data/msgparse.h

171

uint32_t flags;

sbin/unwind/libunbound/util/data/msgparse.h

347

uint16_t type, uint16_t dclass, uint32_t rrset_flags);

sbin/unwind/libunbound/util/data/msgparse.h

362

struct sldns_buffer* pkt, hashvalue_type h, uint32_t rrset_flags,

sbin/unwind/libunbound/util/data/msgreply.c

284

memmove(to, rr->ttl_data+sizeof(uint32_t), rr->size);

sbin/unwind/libunbound/util/data/msgreply.c

289

(rr->ttl_data - sldns_buffer_begin(pkt) + sizeof(uint32_t)));

sbin/unwind/libunbound/util/data/msgreply.h

146

uint32_t padding;

sbin/unwind/libunbound/util/data/packed_rrset.c

173

h = hashlittle(&key->flags, sizeof(uint32_t), h);

sbin/unwind/libunbound/util/data/packed_rrset.c

294

(uint32_t)(d->rr_ttl[i]-adjust));

sbin/unwind/libunbound/util/data/packed_rrset.h

103

uint32_t flags;

sbin/unwind/libunbound/util/edns.c

167

uint32_t timestamp)

sbin/unwind/libunbound/util/edns.c

182

const uint8_t* hash_input, uint32_t now)

sbin/unwind/libunbound/util/edns.c

185

uint32_t timestamp;

sbin/unwind/libunbound/util/edns.c

186

uint32_t subt_1982 = 0; /* Initialize for the compiler; unused value */

sbin/unwind/libunbound/util/edns.c

301

const uint8_t* hash_input, uint32_t now)

sbin/unwind/libunbound/util/edns.h

191

uint32_t timestamp);

sbin/unwind/libunbound/util/edns.h

208

const uint8_t* hash_input, uint32_t now);

sbin/unwind/libunbound/util/edns.h

246

const uint8_t* hash_input, uint32_t now);

sbin/unwind/libunbound/util/net_help.c

285

sa->sin6_scope_id = (uint32_t)atoi(s+1);

sbin/unwind/libunbound/util/netevent.c

1213

doq_set_ecn(int fd, int family, uint32_t ecn)

sbin/unwind/libunbound/util/netevent.c

1329

uint32_t ecn)

sbin/unwind/libunbound/util/netevent.c

1350

doq_send_pkt(struct comm_point* c, struct doq_pkt_addr* paddr, uint32_t ecn)

sbin/unwind/libunbound/util/netevent.c

1531

static uint32_t

sbin/unwind/libunbound/util/netevent.c

1614

uint32_t versions[2];

sbin/unwind/libunbound/util/netevent.c

1742

uint32_t version;

sbin/unwind/libunbound/util/netevent.c

5143

int32_t stream_id, uint32_t ATTR_UNUSED(error_code), void* cb_arg)

sbin/unwind/libunbound/util/netevent.c

6066

uint32_t http_max_streams, char* http_endpoint,

sbin/unwind/libunbound/util/netevent.c

6188

uint32_t http_max_streams, char* http_endpoint,

sbin/unwind/libunbound/util/netevent.h

1010

uint32_t error_code, void* cb_arg);

sbin/unwind/libunbound/util/netevent.h

1125

uint32_t ecn);

sbin/unwind/libunbound/util/netevent.h

293

uint32_t http2_max_streams;

sbin/unwind/libunbound/util/netevent.h

648

uint32_t http_max_streams, char* http_endpoint,

sbin/unwind/libunbound/util/netevent.h

943

uint32_t reads_count;

sbin/unwind/libunbound/util/proxy_protocol.c

49

void (*write_uint32)(void* buf, uint32_t data);

sbin/unwind/libunbound/util/proxy_protocol.c

75

void (*write_uint32)(void* buf, uint32_t data)) {

sbin/unwind/libunbound/util/proxy_protocol.h

107

uint32_t src_addr;

sbin/unwind/libunbound/util/proxy_protocol.h

108

uint32_t dst_addr;

sbin/unwind/libunbound/util/proxy_protocol.h

142

void (*write_uint32)(void* buf, uint32_t data));

sbin/unwind/libunbound/util/random.c

136

return (long)arc4random_uniform((uint32_t)x);

sbin/unwind/libunbound/util/rfc_1982.c

45

compare_1982(uint32_t a, uint32_t b)

sbin/unwind/libunbound/util/rfc_1982.c

48

const uint32_t cutoff = ((uint32_t) 1 << (32 - 1));

sbin/unwind/libunbound/util/rfc_1982.c

59

uint32_t

sbin/unwind/libunbound/util/rfc_1982.c

60

subtract_1982(uint32_t a, uint32_t b)

sbin/unwind/libunbound/util/rfc_1982.c

63

const uint32_t cutoff = ((uint32_t) 1 << (32 - 1));

sbin/unwind/libunbound/util/rfc_1982.c

71

return ((uint32_t)0xffffffff) - (a-b-1);

sbin/unwind/libunbound/util/rfc_1982.h

51

int compare_1982(uint32_t a, uint32_t b);

sbin/unwind/libunbound/util/rfc_1982.h

61

uint32_t subtract_1982(uint32_t a, uint32_t b);

sbin/unwind/libunbound/util/siphash.c

47

U32TO8_LE((p), (uint32_t)((v))); \

sbin/unwind/libunbound/util/siphash.c

48

U32TO8_LE((p) + 4, (uint32_t)((v) >> 32));

sbin/unwind/libunbound/util/siphash.c

77

printf("(%3d) v0 %08x %08x\n", (int)inlen, (uint32_t)(v0 >> 32), \

sbin/unwind/libunbound/util/siphash.c

78

(uint32_t)v0); \

sbin/unwind/libunbound/util/siphash.c

79

printf("(%3d) v1 %08x %08x\n", (int)inlen, (uint32_t)(v1 >> 32), \

sbin/unwind/libunbound/util/siphash.c

80

(uint32_t)v1); \

sbin/unwind/libunbound/util/siphash.c

81

printf("(%3d) v2 %08x %08x\n", (int)inlen, (uint32_t)(v2 >> 32), \

sbin/unwind/libunbound/util/siphash.c

82

(uint32_t)v2); \

sbin/unwind/libunbound/util/siphash.c

83

printf("(%3d) v3 %08x %08x\n", (int)inlen, (uint32_t)(v3 >> 32), \

sbin/unwind/libunbound/util/siphash.c

84

(uint32_t)v3); \

sbin/unwind/libunbound/util/storage/lookup3.c

1013

uint32_t c[HASHSTATE], d[HASHSTATE], i=0, j=0, k, l, m=0, z;

sbin/unwind/libunbound/util/storage/lookup3.c

1014

uint32_t e[HASHSTATE],f[HASHSTATE],g[HASHSTATE],h[HASHSTATE];

sbin/unwind/libunbound/util/storage/lookup3.c

1015

uint32_t x[HASHSTATE],y[HASHSTATE];

sbin/unwind/libunbound/util/storage/lookup3.c

1016

uint32_t hlen;

sbin/unwind/libunbound/util/storage/lookup3.c

1029

e[l]=f[l]=g[l]=h[l]=x[l]=y[l]=~((uint32_t)0);

sbin/unwind/libunbound/util/storage/lookup3.c

1034

uint32_t finished=1;

sbin/unwind/libunbound/util/storage/lookup3.c

1083

uint32_t len;

sbin/unwind/libunbound/util/storage/lookup3.c

1085

uint32_t h;

sbin/unwind/libunbound/util/storage/lookup3.c

1087

uint32_t i;

sbin/unwind/libunbound/util/storage/lookup3.c

1089

uint32_t j;

sbin/unwind/libunbound/util/storage/lookup3.c

1091

uint32_t ref,x,y;

sbin/unwind/libunbound/util/storage/lookup3.c

1096

hashword((const uint32_t *)q, (sizeof(q)-1)/4, 13),

sbin/unwind/libunbound/util/storage/lookup3.c

1097

hashword((const uint32_t *)q, (sizeof(q)-5)/4, 13),

sbin/unwind/libunbound/util/storage/lookup3.c

1098

hashword((const uint32_t *)q, (sizeof(q)-9)/4, 13));

sbin/unwind/libunbound/util/storage/lookup3.c

1156

ref = hashlittle(b, len, (uint32_t)1);

sbin/unwind/libunbound/util/storage/lookup3.c

1159

x = hashlittle(b, len, (uint32_t)1);

sbin/unwind/libunbound/util/storage/lookup3.c

116

#define hashsize(n) ((uint32_t)1<<(n))

sbin/unwind/libunbound/util/storage/lookup3.c

1160

y = hashlittle(b, len, (uint32_t)1);

sbin/unwind/libunbound/util/storage/lookup3.c

1174

uint32_t h,i,state[HASHSTATE];

sbin/unwind/libunbound/util/storage/lookup3.c

121

static uint32_t raninit = (uint32_t)0xdeadbeef;

sbin/unwind/libunbound/util/storage/lookup3.c

124

hash_set_raninit(uint32_t v)

sbin/unwind/libunbound/util/storage/lookup3.c

232

uint32_t hashword(

sbin/unwind/libunbound/util/storage/lookup3.c

233

const uint32_t *k, /* the key, an array of uint32_t values */

sbin/unwind/libunbound/util/storage/lookup3.c

235

uint32_t initval) /* the previous hash, or an arbitrary value */

sbin/unwind/libunbound/util/storage/lookup3.c

237

uint32_t a,b,c;

sbin/unwind/libunbound/util/storage/lookup3.c

240

a = b = c = raninit + (((uint32_t)length)<<2) + initval;

sbin/unwind/libunbound/util/storage/lookup3.c

285

const uint32_t *k, /* the key, an array of uint32_t values */

sbin/unwind/libunbound/util/storage/lookup3.c

287

uint32_t *pc, /* IN: seed OUT: primary hash value */

sbin/unwind/libunbound/util/storage/lookup3.c

288

uint32_t *pb) /* IN: more seed OUT: secondary hash value */

sbin/unwind/libunbound/util/storage/lookup3.c

290

uint32_t a,b,c;

sbin/unwind/libunbound/util/storage/lookup3.c

293

a = b = c = raninit + ((uint32_t)(length<<2)) + *pc;

sbin/unwind/libunbound/util/storage/lookup3.c

356

uint32_t hashlittle( const void *key, size_t length, uint32_t initval)

sbin/unwind/libunbound/util/storage/lookup3.c

358

uint32_t a,b,c; /* internal state */

sbin/unwind/libunbound/util/storage/lookup3.c

362

a = b = c = raninit + ((uint32_t)length) + initval;

sbin/unwind/libunbound/util/storage/lookup3.c

366

const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */

sbin/unwind/libunbound/util/storage/lookup3.c

417

case 11: c+=((uint32_t)k8[10])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

420

case 10: c+=((uint32_t)k8[9])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

427

case 7 : b+=((uint32_t)k8[6])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

430

case 6 : b+=((uint32_t)k8[5])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

437

case 3 : a+=((uint32_t)k8[2])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

440

case 2 : a+=((uint32_t)k8[1])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

456

a += k[0] + (((uint32_t)k[1])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

457

b += k[2] + (((uint32_t)k[3])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

458

c += k[4] + (((uint32_t)k[5])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

468

case 12: c+=k[4]+(((uint32_t)k[5])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

469

b+=k[2]+(((uint32_t)k[3])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

470

a+=k[0]+(((uint32_t)k[1])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

472

case 11: c+=((uint32_t)k8[10])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

476

b+=k[2]+(((uint32_t)k[3])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

477

a+=k[0]+(((uint32_t)k[1])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

482

case 8 : b+=k[2]+(((uint32_t)k[3])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

483

a+=k[0]+(((uint32_t)k[1])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

485

case 7 : b+=((uint32_t)k8[6])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

489

a+=k[0]+(((uint32_t)k[1])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

494

case 4 : a+=k[0]+(((uint32_t)k[1])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

496

case 3 : a+=((uint32_t)k8[2])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

513

a += ((uint32_t)k[1])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

514

a += ((uint32_t)k[2])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

515

a += ((uint32_t)k[3])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

517

b += ((uint32_t)k[5])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

518

b += ((uint32_t)k[6])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

519

b += ((uint32_t)k[7])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

521

c += ((uint32_t)k[9])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

522

c += ((uint32_t)k[10])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

523

c += ((uint32_t)k[11])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

532

case 12: c+=((uint32_t)k[11])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

535

case 11: c+=((uint32_t)k[10])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

538

case 10: c+=((uint32_t)k[9])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

544

case 8 : b+=((uint32_t)k[7])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

547

case 7 : b+=((uint32_t)k[6])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

550

case 6 : b+=((uint32_t)k[5])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

556

case 4 : a+=((uint32_t)k[3])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

559

case 3 : a+=((uint32_t)k[2])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

562

case 2 : a+=((uint32_t)k[1])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

590

uint32_t *pc, /* IN: primary initval, OUT: primary hash */

sbin/unwind/libunbound/util/storage/lookup3.c

591

uint32_t *pb) /* IN: secondary initval, OUT: secondary hash */

sbin/unwind/libunbound/util/storage/lookup3.c

593

uint32_t a,b,c; /* internal state */

sbin/unwind/libunbound/util/storage/lookup3.c

597

a = b = c = raninit + ((uint32_t)length) + *pc;

sbin/unwind/libunbound/util/storage/lookup3.c

602

const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */

sbin/unwind/libunbound/util/storage/lookup3.c

653

case 11: c+=((uint32_t)k8[10])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

656

case 10: c+=((uint32_t)k8[9])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

663

case 7 : b+=((uint32_t)k8[6])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

666

case 6 : b+=((uint32_t)k8[5])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

673

case 3 : a+=((uint32_t)k8[2])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

676

case 2 : a+=((uint32_t)k8[1])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

692

a += k[0] + (((uint32_t)k[1])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

693

b += k[2] + (((uint32_t)k[3])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

694

c += k[4] + (((uint32_t)k[5])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

704

case 12: c+=k[4]+(((uint32_t)k[5])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

705

b+=k[2]+(((uint32_t)k[3])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

706

a+=k[0]+(((uint32_t)k[1])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

708

case 11: c+=((uint32_t)k8[10])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

712

b+=k[2]+(((uint32_t)k[3])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

713

a+=k[0]+(((uint32_t)k[1])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

718

case 8 : b+=k[2]+(((uint32_t)k[3])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

719

a+=k[0]+(((uint32_t)k[1])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

721

case 7 : b+=((uint32_t)k8[6])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

725

a+=k[0]+(((uint32_t)k[1])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

730

case 4 : a+=k[0]+(((uint32_t)k[1])<<16);

sbin/unwind/libunbound/util/storage/lookup3.c

732

case 3 : a+=((uint32_t)k8[2])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

749

a += ((uint32_t)k[1])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

750

a += ((uint32_t)k[2])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

751

a += ((uint32_t)k[3])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

753

b += ((uint32_t)k[5])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

754

b += ((uint32_t)k[6])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

755

b += ((uint32_t)k[7])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

757

c += ((uint32_t)k[9])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

758

c += ((uint32_t)k[10])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

759

c += ((uint32_t)k[11])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

768

case 12: c+=((uint32_t)k[11])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

771

case 11: c+=((uint32_t)k[10])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

774

case 10: c+=((uint32_t)k[9])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

780

case 8 : b+=((uint32_t)k[7])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

783

case 7 : b+=((uint32_t)k[6])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

786

case 6 : b+=((uint32_t)k[5])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

792

case 4 : a+=((uint32_t)k[3])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

795

case 3 : a+=((uint32_t)k[2])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

798

case 2 : a+=((uint32_t)k[1])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

821

uint32_t hashbig( const void *key, size_t length, uint32_t initval)

sbin/unwind/libunbound/util/storage/lookup3.c

823

uint32_t a,b,c;

sbin/unwind/libunbound/util/storage/lookup3.c

827

a = b = c = raninit + ((uint32_t)length) + initval;

sbin/unwind/libunbound/util/storage/lookup3.c

831

const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */

sbin/unwind/libunbound/util/storage/lookup3.c

882

case 11: c+=((uint32_t)k8[10])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

885

case 10: c+=((uint32_t)k8[9])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

888

case 9 : c+=((uint32_t)k8[8])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

892

case 7 : b+=((uint32_t)k8[6])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

895

case 6 : b+=((uint32_t)k8[5])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

898

case 5 : b+=((uint32_t)k8[4])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

902

case 3 : a+=((uint32_t)k8[2])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

905

case 2 : a+=((uint32_t)k8[1])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

908

case 1 : a+=((uint32_t)k8[0])<<24; break;

sbin/unwind/libunbound/util/storage/lookup3.c

920

a += ((uint32_t)k[0])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

921

a += ((uint32_t)k[1])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

922

a += ((uint32_t)k[2])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

923

a += ((uint32_t)k[3]);

sbin/unwind/libunbound/util/storage/lookup3.c

924

b += ((uint32_t)k[4])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

925

b += ((uint32_t)k[5])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

926

b += ((uint32_t)k[6])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

927

b += ((uint32_t)k[7]);

sbin/unwind/libunbound/util/storage/lookup3.c

928

c += ((uint32_t)k[8])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

929

c += ((uint32_t)k[9])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

930

c += ((uint32_t)k[10])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

931

c += ((uint32_t)k[11]);

sbin/unwind/libunbound/util/storage/lookup3.c

943

case 11: c+=((uint32_t)k[10])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

946

case 10: c+=((uint32_t)k[9])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

949

case 9 : c+=((uint32_t)k[8])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

955

case 7 : b+=((uint32_t)k[6])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

958

case 6 : b+=((uint32_t)k[5])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

961

case 5 : b+=((uint32_t)k[4])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

967

case 3 : a+=((uint32_t)k[2])<<8;

sbin/unwind/libunbound/util/storage/lookup3.c

970

case 2 : a+=((uint32_t)k[1])<<16;

sbin/unwind/libunbound/util/storage/lookup3.c

973

case 1 : a+=((uint32_t)k[0])<<24;

sbin/unwind/libunbound/util/storage/lookup3.c

991

uint32_t i;

sbin/unwind/libunbound/util/storage/lookup3.c

992

uint32_t h=0;

sbin/unwind/libunbound/util/storage/lookup3.h

53

uint32_t hashword(const uint32_t *k, size_t length, uint32_t initval);

sbin/unwind/libunbound/util/storage/lookup3.h

62

uint32_t hashlittle(const void *k, size_t length, uint32_t initval);

sbin/unwind/libunbound/util/storage/lookup3.h

69

void hash_set_raninit(uint32_t v);

sbin/unwind/libunbound/util/storage/lruhash.h

119

typedef uint32_t hashvalue_type;

sbin/unwind/libunbound/util/storage/slabhash.c

64

sl->mask = (uint32_t)(sl->size - 1);

sbin/unwind/libunbound/util/storage/slabhash.h

61

uint32_t mask;

sbin/unwind/libunbound/util/tcp_conn_limit.c

112

uint32_t limit;

sbin/unwind/libunbound/util/tcp_conn_limit.c

117

limit = (uint32_t)atoi(s2);

sbin/unwind/libunbound/util/tcp_conn_limit.c

88

socklen_t addrlen, int net, uint32_t limit,

sbin/unwind/libunbound/util/tcp_conn_limit.h

73

uint32_t limit;

sbin/unwind/libunbound/util/tcp_conn_limit.h

75

uint32_t count;

sbin/unwind/libunbound/util/tube.c

288

int tube_write_msg(struct tube* tube, uint8_t* buf, uint32_t len,

sbin/unwind/libunbound/util/tube.c

334

int tube_read_msg(struct tube* tube, uint8_t** buf, uint32_t* len,

sbin/unwind/libunbound/util/tube.c

609

int tube_write_msg(struct tube* tube, uint8_t* buf, uint32_t len,

sbin/unwind/libunbound/util/tube.c

623

int tube_read_msg(struct tube* tube, uint8_t** buf, uint32_t* len,

sbin/unwind/libunbound/util/tube.c

786

uint32_t len = 0;

sbin/unwind/libunbound/util/tube.h

121

uint32_t len;

sbin/unwind/libunbound/util/tube.h

153

int tube_write_msg(struct tube* tube, uint8_t* buf, uint32_t len,

sbin/unwind/libunbound/util/tube.h

173

int tube_read_msg(struct tube* tube, uint8_t** buf, uint32_t* len,

sbin/unwind/libunbound/util/tube.h

79

uint32_t cmd_len;

sbin/unwind/libunbound/validator/autotrust.c

1444

add_key(struct trust_anchor* tp, uint32_t ttl, uint8_t* rdata, size_t rdata_len)

sbin/unwind/libunbound/validator/autotrust.c

1667

ta = add_key(tp, (uint32_t)dd->rr_ttl[i],

sbin/unwind/libunbound/validator/val_neg.c

1061

uint16_t qtype, uint16_t qclass, uint32_t flags,

sbin/unwind/libunbound/validator/val_neg.c

1114

uint32_t flags;

sbin/unwind/libunbound/validator/val_nsec.c

53

static uint32_t

sbin/unwind/libunbound/validator/val_sigcrypt.c

1417

check_dates(struct val_env* ve, uint32_t unow, uint8_t* expi_p,

sbin/unwind/libunbound/validator/val_sigcrypt.c

1421

uint32_t expi, incep, now;

sbin/unwind/libunbound/validator/val_sigcrypt.c

1454

uint32_t skew = subtract_1982(incep, expi)/10;

sbin/unwind/libunbound/validator/val_sigcrypt.c

1455

if(skew < (uint32_t)ve->skew_min) skew = ve->skew_min;

sbin/unwind/libunbound/validator/val_sigcrypt.c

1456

if(skew > (uint32_t)ve->skew_max) skew = ve->skew_max;

sbin/unwind/libunbound/validator/val_sigcrypt.c

1469

uint32_t skew = subtract_1982(incep, expi)/10;

sbin/unwind/libunbound/validator/val_sigcrypt.c

1470

if(skew < (uint32_t)ve->skew_min) skew = ve->skew_min;

sbin/unwind/libunbound/validator/val_sigcrypt.c

1471

if(skew > (uint32_t)ve->skew_max) skew = ve->skew_max;

sbin/unwind/libunbound/validator/val_sigcrypt.c

1488

adjust_ttl(struct val_env* ve, uint32_t unow,

sbin/unwind/libunbound/validator/val_sigcrypt.c

1507

expittl = (int32_t)((uint32_t)expi - (uint32_t)now);

sbin/unwind/libunbound/validator/val_utils.c

395

static uint32_t

sbin/unwind/libunbound/validator/validator.c

172

val_env->bogus_ttl = (uint32_t)cfg->bogus_ttl;

sbin/unwind/libunbound/validator/validator.h

104

uint32_t bogus_ttl;

sbin/unwind/resolver.h

59

uint32_t if_index;

sbin/unwind/unwind.c

543

imsg_compose_event(struct imsgev *iev, uint16_t type, uint32_t peerid,

sbin/unwind/unwind.c

84

uint32_t cmd_opts;

sbin/unwind/unwind.h

134

uint32_t if_index;

sbin/unwind/unwind.h

179

extern uint32_t cmd_opts;

sbin/unwind/unwind.h

187

int imsg_compose_event(struct imsgev *, uint16_t, uint32_t, pid_t,

sys/arch/alpha/alpha/autoconf.c

73

extern uint32_t kernel_text[], endboot[];

sys/arch/alpha/alpha/autoconf.c

74

uint32_t *word = kernel_text;

sys/arch/alpha/pci/tsciic.c

180

tsciicbb_set_bits(void *cookie, uint32_t bits)

sys/arch/alpha/pci/tsciic.c

192

tsciicbb_set_dir(void *cookie, uint32_t dir)

sys/arch/alpha/pci/tsciic.c

197

uint32_t

sys/arch/alpha/pci/tsciic.c

201

uint32_t bits;

sys/arch/alpha/pci/tsciic.c

78

void tsciicbb_set_bits(void *, uint32_t);

sys/arch/alpha/pci/tsciic.c

79

void tsciicbb_set_dir(void *, uint32_t);

sys/arch/alpha/pci/tsciic.c

80

uint32_t tsciicbb_read(void *);

sys/arch/alpha/tc/ioasic.c

395

*(volatile uint32_t *)TC_3000_300_LED =

sys/arch/alpha/tc/ioasic.c

396

(*(volatile uint32_t *)TC_3000_300_LED & ~(0xff << 16)) |

sys/arch/alpha/tc/ioasic.c

402

*(volatile uint32_t *)rw_csr =

sys/arch/alpha/tc/ioasic.c

403

(*(volatile uint32_t *)rw_csr & ~(1 << 5)) ^

sys/arch/alpha/tc/ioasic.c

410

*(volatile uint32_t *)rw_csr =

sys/arch/alpha/tc/ioasic.c

411

(*(volatile uint32_t *)rw_csr & ~0xff) | pattern;

sys/arch/amd64/amd64/acpi_machdep.c

298

acpi_acquire_glk(uint32_t *lock)

sys/arch/amd64/amd64/acpi_machdep.c

300

uint32_t new, old;

sys/arch/amd64/amd64/acpi_machdep.c

318

acpi_release_glk(uint32_t *lock)

sys/arch/amd64/amd64/acpi_machdep.c

320

uint32_t new, old;

sys/arch/amd64/amd64/aesni.c

111

aesni_get(uint32_t);

sys/arch/amd64/amd64/aesni.c

39

uint32_t aes_ekey[4 * (AES_MAXROUNDS + 1)];

sys/arch/amd64/amd64/aesni.c

40

uint32_t aes_dkey[4 * (AES_MAXROUNDS + 1)];

sys/arch/amd64/amd64/aesni.c

41

uint32_t aes_klen;

sys/arch/amd64/amd64/aesni.c

411

aesni_get(uint32_t sid)

sys/arch/amd64/amd64/aesni.c

42

uint32_t aes_pad[3];

sys/arch/amd64/amd64/aesni.c

446

uint32_t *dw;

sys/arch/amd64/amd64/aesni.c

50

uint32_t ses_ekey[4 * (AES_MAXROUNDS + 1)];

sys/arch/amd64/amd64/aesni.c

51

uint32_t ses_dkey[4 * (AES_MAXROUNDS + 1)];

sys/arch/amd64/amd64/aesni.c

52

uint32_t ses_klen;

sys/arch/amd64/amd64/aesni.c

582

dw = (uint32_t *)tag + 1;

sys/arch/amd64/amd64/aesni.c

584

dw = (uint32_t *)tag + 3;

sys/arch/amd64/amd64/aesni.c

67

uint32_t sc_sid;

sys/arch/amd64/amd64/aesni.c

75

uint32_t aesni_ops;

sys/arch/amd64/amd64/amd64_mem.c

531

uint32_t regs[4];

sys/arch/amd64/amd64/cacheinfo.c

28

uint32_t prev_cache[MAX_CACHE_LEAF][3];

sys/arch/amd64/amd64/codepatch.c

33

uint32_t _padding;

sys/arch/amd64/amd64/cpu.c

1048

uint32_t vendor[4];

sys/arch/amd64/amd64/cpu.c

1317

uint32_t dummy, sefflags_edx;

sys/arch/amd64/amd64/cpu.c

1370

uint32_t u32[2];

sys/arch/amd64/amd64/cpu.c

302

uint32_t cap = 0;

sys/arch/amd64/amd64/efi_machdep.c

125

uint32_t mmap_size = bios_efiinfo->mmap_size;

sys/arch/amd64/amd64/efi_machdep.c

126

uint32_t mmap_desc_size = bios_efiinfo->mmap_desc_size;

sys/arch/amd64/amd64/efi_machdep.c

64

uint32_t mmap_desc_ver = bios_efiinfo->mmap_desc_ver;

sys/arch/amd64/amd64/efifb.c

207

uint32_t defattr = 0;

sys/arch/amd64/amd64/efifb.c

344

void **cookiep, int *curxp, int *curyp, uint32_t *attrp)

sys/arch/amd64/amd64/efifb.c

381

uint32_t defattr = 0;

sys/arch/amd64/amd64/efifb.c

41

uint32_t signature32;

sys/arch/amd64/amd64/efifb.c

43

uint32_t header_bytes;

sys/arch/amd64/amd64/efifb.c

44

uint32_t header_checksum;

sys/arch/amd64/amd64/efifb.c

45

uint32_t table_bytes;

sys/arch/amd64/amd64/efifb.c

46

uint32_t table_checksum;

sys/arch/amd64/amd64/efifb.c

47

uint32_t table_entries;

sys/arch/amd64/amd64/efifb.c

52

uint32_t x_resolution;

sys/arch/amd64/amd64/efifb.c

53

uint32_t y_resolution;

sys/arch/amd64/amd64/efifb.c

531

uint32_t sum = 0;

sys/arch/amd64/amd64/efifb.c

54

uint32_t bytes_per_line;

sys/arch/amd64/amd64/efifb.c

67

uint32_t tag;

sys/arch/amd64/amd64/efifb.c

71

uint32_t size;

sys/arch/amd64/amd64/efifb.c

99

int *, int *, uint32_t *);

sys/arch/amd64/amd64/fpu.c

65

uint32_t fpu_mxcsr_mask;

sys/arch/amd64/amd64/ghcb.c

302

size = sizeof(uint32_t);

sys/arch/amd64/amd64/ghcb.c

373

_ghcb_io_rw(uint16_t port, int valsz, uint32_t *val, bool read)

sys/arch/amd64/amd64/identcpu.c

1016

(uint32_t)(msr & 0x7FFFFFFF);

sys/arch/amd64/amd64/identcpu.c

1021

(uint32_t)(msr & IA32_VMX_MSR_LIST_SIZE_MASK) >> 25;

sys/arch/amd64/amd64/identcpu.c

1025

(uint32_t)(msr & IA32_VMX_CR3_TGT_SIZE_MASK) >> 16;

sys/arch/amd64/amd64/identcpu.c

289

cpu_freq_ctr(struct cpu_info *ci, uint32_t cpu_perf_eax,

sys/arch/amd64/amd64/identcpu.c

290

uint32_t cpu_perf_edx)

sys/arch/amd64/amd64/identcpu.c

340

pcpu0id3(const char *id, char reg1, uint32_t val1, const char *bits1,

sys/arch/amd64/amd64/identcpu.c

341

char reg2, uint32_t val2, const char *bits2,

sys/arch/amd64/amd64/identcpu.c

342

char reg3, uint32_t val3, const char *bits3)

sys/arch/amd64/amd64/identcpu.c

357

pmsr032(uint32_t msr, uint32_t value, const char *bits)

sys/arch/amd64/amd64/identcpu.c

364

pbitdiff(uint32_t value, uint32_t base_value, const char *bits)

sys/arch/amd64/amd64/identcpu.c

366

uint32_t minus;

sys/arch/amd64/amd64/identcpu.c

378

pcpuid(struct cpu_info *ci, const char *id, char reg, uint32_t val,

sys/arch/amd64/amd64/identcpu.c

379

uint32_t prev_val, const char *bits)

sys/arch/amd64/amd64/identcpu.c

391

char reg1, uint32_t val1, uint32_t prev_val1, const char *bits1,

sys/arch/amd64/amd64/identcpu.c

392

char reg2, uint32_t val2, uint32_t prev_val2, const char *bits2)

sys/arch/amd64/amd64/identcpu.c

412

char reg1, uint32_t val1, uint32_t prev_val1, const char *bits1,

sys/arch/amd64/amd64/identcpu.c

413

char reg2, uint32_t val2, uint32_t prev_val2, const char *bits2,

sys/arch/amd64/amd64/identcpu.c

414

char reg3, uint32_t val3, uint32_t prev_val3, const char *bits3)

sys/arch/amd64/amd64/identcpu.c

437

pmsr32(struct cpu_info *ci, uint32_t msr, uint32_t value, uint32_t prev_value,

sys/arch/amd64/amd64/identcpu.c

449

static uint32_t prevcpu_perf_eax;

sys/arch/amd64/amd64/identcpu.c

450

static uint32_t prevcpu_perf_edx;

sys/arch/amd64/amd64/identcpu.c

454

print_perf_cpuid(struct cpu_info *ci, uint32_t cpu_perf_eax,

sys/arch/amd64/amd64/identcpu.c

455

uint32_t cpu_perf_edx)

sys/arch/amd64/amd64/identcpu.c

457

uint32_t version;

sys/arch/amd64/amd64/identcpu.c

491

static uint32_t prevcpu_1_ecx, prevcpu_tpm_ecxflags, prevcpu_d_1_eax;

sys/arch/amd64/amd64/identcpu.c

492

static uint32_t prevcpu_apmi_edx, prevcpu_arch_capa;

sys/arch/amd64/amd64/identcpu.c

495

uint32_t cflushsz, curcpu_1_ecx, curcpu_apmi_edx = 0;

sys/arch/amd64/amd64/identcpu.c

496

uint32_t curcpu_perf_eax = 0, curcpu_perf_edx = 0;

sys/arch/amd64/amd64/identcpu.c

497

uint32_t curcpu_tpm_ecxflags = 0, curcpu_d_1_eax = 0;

sys/arch/amd64/amd64/identcpu.c

631

uint32_t dummy;

sys/arch/amd64/amd64/identcpu.c

687

uint32_t msr = rdmsr(MSR_ARCH_CAPABILITIES);

sys/arch/amd64/amd64/identcpu.c

845

uint32_t nthreads = 1; /* per core */

sys/arch/amd64/amd64/identcpu.c

846

uint32_t thread_id; /* within a package */

sys/arch/amd64/amd64/identcpu.c

962

uint32_t cap, dummy, edx;

sys/arch/amd64/amd64/kexec.c

302

uint32_t *stack;

sys/arch/amd64/amd64/kexec.c

339

stack = (uint32_t *)va_data;

sys/arch/amd64/amd64/kexec.c

340

i = PAGE_SIZE / sizeof(uint32_t) - 1;

sys/arch/amd64/amd64/lapic.c

261

uint32_t lint0;

sys/arch/amd64/amd64/lapic.c

420

void lapic_timer_oneshot(uint32_t, uint32_t);

sys/arch/amd64/amd64/lapic.c

421

void lapic_timer_periodic(uint32_t, uint32_t);

sys/arch/amd64/amd64/lapic.c

426

uint32_t cycles;

sys/arch/amd64/amd64/lapic.c

454

lapic_timer_start(uint32_t mode, uint32_t mask, uint32_t cycles)

sys/arch/amd64/amd64/lapic.c

462

lapic_timer_oneshot(uint32_t mask, uint32_t cycles)

sys/arch/amd64/amd64/lapic.c

468

lapic_timer_periodic(uint32_t mask, uint32_t cycles)

sys/arch/amd64/amd64/machdep.c

2075

copyin32(const uint32_t *uaddr, uint32_t *kaddr)

sys/arch/amd64/amd64/machdep.c

2081

return copyin(uaddr, kaddr, sizeof(uint32_t));

sys/arch/amd64/amd64/pctr.c

128

pctrsel(int fflag, uint32_t cmd, uint32_t fn)

sys/arch/amd64/amd64/pctr.c

200

uint32_t fn;

sys/arch/amd64/amd64/pctr.c

51

uint32_t pctr_intel_cap;

sys/arch/amd64/amd64/pctr.c

54

uint32_t pctr_fn[PCTR_NUM];

sys/arch/amd64/amd64/pctr.c

57

static int pctrsel(int, uint32_t, uint32_t);

sys/arch/amd64/amd64/pctr.c

80

uint32_t dummy;

sys/arch/amd64/amd64/pmap.c

685

uint32_t ecx, dummy;

sys/arch/amd64/amd64/pmap.c

741

uint32_t ebx, dummy;

sys/arch/amd64/amd64/powernow-k8.c

132

uint32_t cpuid;

sys/arch/amd64/amd64/powernow-k8.c

143

int k8pnow_states(struct k8pnow_cpu_state *, uint32_t, unsigned int, unsigned int);

sys/arch/amd64/amd64/powernow-k8.c

317

uint32_t ctrl;

sys/arch/amd64/amd64/powernow-k8.c

349

uint32_t ctrl;

sys/arch/amd64/amd64/powernow-k8.c

394

uint32_t ctrl;

sys/arch/amd64/amd64/powernow-k8.c

418

k8pnow_states(struct k8pnow_cpu_state *cstate, uint32_t cpusig,

sys/arch/amd64/amd64/process_machdep.c

252

uint32_t offset_extended_region = offsetof(struct xsave_area,

sys/arch/amd64/amd64/process_machdep.c

254

uint32_t a, b, c, d;

sys/arch/amd64/amd64/sev_bus_space.c

102

uint32_t, size_t);

sys/arch/amd64/amd64/sev_bus_space.c

154

uint32_t sev_ghcb_mem_read_4(bus_space_handle_t, bus_size_t);

sys/arch/amd64/amd64/sev_bus_space.c

162

uint32_t *, bus_size_t);

sys/arch/amd64/amd64/sev_bus_space.c

171

uint32_t *, bus_size_t);

sys/arch/amd64/amd64/sev_bus_space.c

180

uint32_t);

sys/arch/amd64/amd64/sev_bus_space.c

189

bus_size_t, const uint32_t *, bus_size_t);

sys/arch/amd64/amd64/sev_bus_space.c

198

bus_size_t, const uint32_t *, bus_size_t);

sys/arch/amd64/amd64/sev_bus_space.c

207

uint32_t, size_t);

sys/arch/amd64/amd64/sev_bus_space.c

216

uint32_t, size_t);

sys/arch/amd64/amd64/sev_bus_space.c

282

uint32_t

sys/arch/amd64/amd64/sev_bus_space.c

306

uint32_t *ptr, bus_size_t cnt)

sys/arch/amd64/amd64/sev_bus_space.c

330

bus_size_t o, uint32_t *ptr, bus_size_t cnt)

sys/arch/amd64/amd64/sev_bus_space.c

349

sev_ghcb_io_write_4(bus_space_handle_t h, bus_size_t o, uint32_t v)

sys/arch/amd64/amd64/sev_bus_space.c

372

bus_size_t o, const uint32_t *ptr, bus_size_t cnt)

sys/arch/amd64/amd64/sev_bus_space.c

396

bus_size_t o, const uint32_t *ptr, bus_size_t cnt)

sys/arch/amd64/amd64/sev_bus_space.c

424

uint32_t v, size_t c)

sys/arch/amd64/amd64/sev_bus_space.c

454

uint32_t v, size_t c)

sys/arch/amd64/amd64/sev_bus_space.c

527

uint32_t

sys/arch/amd64/amd64/sev_bus_space.c

53

uint32_t sev_ghcb_io_read_4(bus_space_handle_t, bus_size_t);

sys/arch/amd64/amd64/sev_bus_space.c

557

uint32_t *ptr, bus_size_t cnt)

sys/arch/amd64/amd64/sev_bus_space.c

589

bus_size_t o, uint32_t *ptr, bus_size_t cnt)

sys/arch/amd64/amd64/sev_bus_space.c

60

uint32_t *, bus_size_t);

sys/arch/amd64/amd64/sev_bus_space.c

616

sev_ghcb_mem_write_4(bus_space_handle_t h, bus_size_t o, uint32_t v)

sys/arch/amd64/amd64/sev_bus_space.c

645

bus_size_t o, const uint32_t *ptr, bus_size_t cnt)

sys/arch/amd64/amd64/sev_bus_space.c

67

uint32_t *, bus_size_t);

sys/arch/amd64/amd64/sev_bus_space.c

677

bus_size_t o, const uint32_t *ptr, bus_size_t cnt)

sys/arch/amd64/amd64/sev_bus_space.c

713

uint32_t v, size_t c)

sys/arch/amd64/amd64/sev_bus_space.c

74

uint32_t);

sys/arch/amd64/amd64/sev_bus_space.c

753

uint32_t v, size_t c)

sys/arch/amd64/amd64/sev_bus_space.c

81

bus_size_t, const uint32_t *, bus_size_t);

sys/arch/amd64/amd64/sev_bus_space.c

88

bus_size_t, const uint32_t *, bus_size_t);

sys/arch/amd64/amd64/sev_bus_space.c

95

uint32_t, size_t);

sys/arch/amd64/amd64/tsc.c

64

uint32_t eax, ebx, khz, dummy;

sys/arch/amd64/amd64/ucode.c

122

uint32_t id;

sys/arch/amd64/amd64/ucode.c

123

uint32_t a;

sys/arch/amd64/amd64/ucode.c

124

uint32_t b;

sys/arch/amd64/amd64/ucode.c

130

uint32_t type;

sys/arch/amd64/amd64/ucode.c

131

uint32_t len;

sys/arch/amd64/amd64/ucode.c

132

uint32_t a;

sys/arch/amd64/amd64/ucode.c

133

uint32_t level;

sys/arch/amd64/amd64/ucode.c

142

uint32_t magic, tlen, i;

sys/arch/amd64/amd64/ucode.c

144

uint32_t sig, ebx, ecx, edx;

sys/arch/amd64/amd64/ucode.c

146

uint32_t patch_len = 0;

sys/arch/amd64/amd64/ucode.c

224

uint32_t old_rev, new_rev;

sys/arch/amd64/amd64/ucode.c

274

cpu_ucode_intel_find(char *data, size_t left, uint32_t current)

sys/arch/amd64/amd64/ucode.c

277

uint32_t sig, dummy1, dummy2, dummy3;

sys/arch/amd64/amd64/ucode.c

278

uint32_t mask = 1UL << platform_id;

sys/arch/amd64/amd64/ucode.c

280

uint32_t total_size;

sys/arch/amd64/amd64/ucode.c

323

uint32_t *data = (uint32_t *)hdr;

sys/arch/amd64/amd64/ucode.c

325

uint32_t sum;

sys/arch/amd64/amd64/ucode.c

362

uint32_t processor_sig, uint32_t processor_mask,

sys/arch/amd64/amd64/ucode.c

363

uint32_t ucode_revision)

sys/arch/amd64/amd64/ucode.c

367

uint32_t data_size, total_size;

sys/arch/amd64/amd64/ucode.c

404

uint32_t

sys/arch/amd64/amd64/ucode.c

407

uint32_t eax, ebx, ecx, edx;

sys/arch/amd64/amd64/ucode.c

42

uint32_t header_version;

sys/arch/amd64/amd64/ucode.c

43

uint32_t update_revision;

sys/arch/amd64/amd64/ucode.c

44

uint32_t date;

sys/arch/amd64/amd64/ucode.c

45

uint32_t processor_sig;

sys/arch/amd64/amd64/ucode.c

46

uint32_t checksum;

sys/arch/amd64/amd64/ucode.c

47

uint32_t loader_rev;

sys/arch/amd64/amd64/ucode.c

48

uint32_t processor_flags;

sys/arch/amd64/amd64/ucode.c

49

uint32_t data_size;

sys/arch/amd64/amd64/ucode.c

50

uint32_t total_size;

sys/arch/amd64/amd64/ucode.c

51

uint32_t reserved1;

sys/arch/amd64/amd64/ucode.c

52

uint32_t min_runtime_update_rev;

sys/arch/amd64/amd64/ucode.c

53

uint32_t reserved2;

sys/arch/amd64/amd64/ucode.c

57

uint32_t ext_sig_count;

sys/arch/amd64/amd64/ucode.c

58

uint32_t checksum;

sys/arch/amd64/amd64/ucode.c

59

uint32_t reserved[3];

sys/arch/amd64/amd64/ucode.c

63

uint32_t processor_sig;

sys/arch/amd64/amd64/ucode.c

64

uint32_t processor_flags;

sys/arch/amd64/amd64/ucode.c

65

uint32_t checksum;

sys/arch/amd64/amd64/ucode.c

82

cpu_ucode_intel_find(char *, size_t, uint32_t);

sys/arch/amd64/amd64/ucode.c

84

int cpu_ucode_intel_match(struct intel_ucode_header *, uint32_t, uint32_t,

sys/arch/amd64/amd64/ucode.c

85

uint32_t);

sys/arch/amd64/amd64/ucode.c

86

uint32_t cpu_ucode_intel_rev(void);

sys/arch/amd64/amd64/vmm_machdep.c

1148

uint32_t attr;

sys/arch/amd64/amd64/vmm_machdep.c

140

const char *vmx_exit_reason_decode(uint32_t);

sys/arch/amd64/amd64/vmm_machdep.c

141

const char *svm_exit_reason_decode(uint32_t);

sys/arch/amd64/amd64/vmm_machdep.c

142

const char *vmx_instruction_error_decode(uint32_t);

sys/arch/amd64/amd64/vmm_machdep.c

143

void svm_setmsrbr(struct vcpu *, uint32_t);

sys/arch/amd64/amd64/vmm_machdep.c

144

void svm_setmsrbw(struct vcpu *, uint32_t);

sys/arch/amd64/amd64/vmm_machdep.c

145

void svm_setmsrbrw(struct vcpu *, uint32_t);

sys/arch/amd64/amd64/vmm_machdep.c

146

void vmx_setmsrbr(struct vcpu *, uint32_t);

sys/arch/amd64/amd64/vmm_machdep.c

147

void vmx_setmsrbw(struct vcpu *, uint32_t);

sys/arch/amd64/amd64/vmm_machdep.c

148

void vmx_setmsrbrw(struct vcpu *, uint32_t);

sys/arch/amd64/amd64/vmm_machdep.c

149

void svm_set_clean(struct vcpu *, uint32_t);

sys/arch/amd64/amd64/vmm_machdep.c

150

void svm_set_dirty(struct vcpu *, uint32_t);

sys/arch/amd64/amd64/vmm_machdep.c

151

int svm_get_vmsa_pa(uint32_t, uint32_t, uint64_t *);

sys/arch/amd64/amd64/vmm_machdep.c

166

const char *msr_name_decode(uint32_t);

sys/arch/amd64/amd64/vmm_machdep.c

1759

svm_setmsrbr(struct vcpu *vcpu, uint32_t msr)

sys/arch/amd64/amd64/vmm_machdep.c

1800

svm_setmsrbw(struct vcpu *vcpu, uint32_t msr)

sys/arch/amd64/amd64/vmm_machdep.c

1841

svm_setmsrbrw(struct vcpu *vcpu, uint32_t msr)

sys/arch/amd64/amd64/vmm_machdep.c

1857

vmx_setmsrbr(struct vcpu *vcpu, uint32_t msr)

sys/arch/amd64/amd64/vmm_machdep.c

1889

vmx_setmsrbw(struct vcpu *vcpu, uint32_t msr)

sys/arch/amd64/amd64/vmm_machdep.c

1921

vmx_setmsrbrw(struct vcpu *vcpu, uint32_t msr)

sys/arch/amd64/amd64/vmm_machdep.c

1944

svm_set_clean(struct vcpu *vcpu, uint32_t value)

sys/arch/amd64/amd64/vmm_machdep.c

1971

svm_set_dirty(struct vcpu *vcpu, uint32_t value)

sys/arch/amd64/amd64/vmm_machdep.c

2001

uint32_t cr0, cr4;

sys/arch/amd64/amd64/vmm_machdep.c

2002

uint32_t pinbased, procbased, procbased2, exit, entry;

sys/arch/amd64/amd64/vmm_machdep.c

2003

uint32_t want1, want0;

sys/arch/amd64/amd64/vmm_machdep.c

2561

uint32_t cr0, cr4;

sys/arch/amd64/amd64/vmm_machdep.c

3087

vcpu_vmx_check_cap(struct vcpu *vcpu, uint32_t msr, uint32_t cap, int set)

sys/arch/amd64/amd64/vmm_machdep.c

3167

vcpu_vmx_compute_ctrl(uint64_t ctrlval, uint16_t ctrl, uint32_t want1,

sys/arch/amd64/amd64/vmm_machdep.c

3168

uint32_t want0, uint32_t *out)

sys/arch/amd64/amd64/vmm_machdep.c

3559

pte_size = sizeof(uint32_t);

sys/arch/amd64/amd64/vmm_machdep.c

3591

pte = *(uint32_t *)hva;

sys/arch/amd64/amd64/vmm_machdep.c

4500

uint32_t req, resp;

sys/arch/amd64/amd64/vmm_machdep.c

5196

vee->vee_insn_len = (uint32_t)insn_len;

sys/arch/amd64/amd64/vmm_machdep.c

5406

vcpu->vc_exit.vei.vei_data = (uint32_t)vcpu->vc_gueststate.vg_rax;

sys/arch/amd64/amd64/vmm_machdep.c

6186

vmm_handle_cpuid_0xd(struct vcpu *vcpu, uint32_t subleaf, uint64_t *rax,

sys/arch/amd64/amd64/vmm_machdep.c

6187

uint32_t eax, uint32_t ebx, uint32_t ecx, uint32_t edx)

sys/arch/amd64/amd64/vmm_machdep.c

6209

uint32_t dummy;

sys/arch/amd64/amd64/vmm_machdep.c

6274

uint32_t leaf, subleaf, eax, ebx, ecx, edx;

sys/arch/amd64/amd64/vmm_machdep.c

6355

*rbx = *((uint32_t *)&cpu_vendor);

sys/arch/amd64/amd64/vmm_machdep.c

6356

*rdx = *((uint32_t *)&cpu_vendor + 1);

sys/arch/amd64/amd64/vmm_machdep.c

6357

*rcx = *((uint32_t *)&cpu_vendor + 2);

sys/arch/amd64/amd64/vmm_machdep.c

6506

*rbx = *((uint32_t *)&vmm_hv_signature[0]);

sys/arch/amd64/amd64/vmm_machdep.c

6507

*rcx = *((uint32_t *)&vmm_hv_signature[4]);

sys/arch/amd64/amd64/vmm_machdep.c

6508

*rdx = *((uint32_t *)&vmm_hv_signature[8]);

sys/arch/amd64/amd64/vmm_machdep.c

6522

*rbx = *((uint32_t *)&kvm_hv_signature[0]);

sys/arch/amd64/amd64/vmm_machdep.c

6523

*rcx = *((uint32_t *)&kvm_hv_signature[4]);

sys/arch/amd64/amd64/vmm_machdep.c

6524

*rdx = *((uint32_t *)&kvm_hv_signature[8]);

sys/arch/amd64/amd64/vmm_machdep.c

7127

vmx_exit_reason_decode(uint32_t code)

sys/arch/amd64/amd64/vmm_machdep.c

7201

svm_exit_reason_decode(uint32_t code)

sys/arch/amd64/amd64/vmm_machdep.c

7356

vmx_instruction_error_decode(uint32_t code)

sys/arch/amd64/amd64/vmm_machdep.c

7407

svm_get_vmsa_pa(uint32_t vmid, uint32_t vcpuid, uint64_t *vmsapa)

sys/arch/amd64/amd64/vmm_machdep.c

7585

uint32_t cr3_tgt_ct;

sys/arch/amd64/amd64/vmm_machdep.c

760

uint32_t cr4;

sys/arch/amd64/amd64/vmm_machdep.c

827

uint32_t cr4;

sys/arch/amd64/amd64/vmm_machdep.c

8423

msr_name_decode(uint32_t msr)

sys/arch/amd64/amd64/vmm_machdep.c

8472

uint32_t unusable;

sys/arch/amd64/amd64/vmm_machdep.c

94

int vcpu_vmx_check_cap(struct vcpu *, uint32_t, uint32_t, int);

sys/arch/amd64/amd64/vmm_machdep.c

95

int vcpu_vmx_compute_ctrl(uint64_t, uint16_t, uint32_t, uint32_t, uint32_t *);

sys/arch/amd64/include/biosvar.h

102

uint32_t type; /* Type of block */

sys/arch/amd64/include/biosvar.h

126

uint32_t checksum; /* Checksum for drive */

sys/arch/amd64/include/biosvar.h

129

uint32_t flags;

sys/arch/amd64/include/biosvar.h

157

uint32_t pci_chars; /* Characteristics (%eax) */

sys/arch/amd64/include/biosvar.h

158

uint32_t pci_rev; /* BCD Revision (%ebx) */

sys/arch/amd64/include/biosvar.h

159

uint32_t pci_entry32; /* PM entry point for PCI BIOS */

sys/arch/amd64/include/biosvar.h

160

uint32_t pci_lastbus; /* Number of last PCI bus */

sys/arch/amd64/include/biosvar.h

169

uint32_t flags;

sys/arch/amd64/include/biosvar.h

204

uint32_t fb_height;

sys/arch/amd64/include/biosvar.h

205

uint32_t fb_width;

sys/arch/amd64/include/biosvar.h

206

uint32_t fb_pixpsl; /* pixels per scan line */

sys/arch/amd64/include/biosvar.h

207

uint32_t fb_red_mask;

sys/arch/amd64/include/biosvar.h

208

uint32_t fb_green_mask;

sys/arch/amd64/include/biosvar.h

209

uint32_t fb_blue_mask;

sys/arch/amd64/include/biosvar.h

210

uint32_t fb_reserved_mask;

sys/arch/amd64/include/biosvar.h

211

uint32_t flags;

sys/arch/amd64/include/biosvar.h

214

uint32_t mmap_desc_ver;

sys/arch/amd64/include/biosvar.h

215

uint32_t mmap_desc_size;

sys/arch/amd64/include/biosvar.h

216

uint32_t mmap_size;

sys/arch/amd64/include/biosvar.h

236

uint32_t biosr_ax;

sys/arch/amd64/include/biosvar.h

237

uint32_t biosr_cx;

sys/arch/amd64/include/biosvar.h

238

uint32_t biosr_dx;

sys/arch/amd64/include/biosvar.h

239

uint32_t biosr_bx;

sys/arch/amd64/include/biosvar.h

240

uint32_t biosr_bp;

sys/arch/amd64/include/biosvar.h

241

uint32_t biosr_si;

sys/arch/amd64/include/biosvar.h

242

uint32_t biosr_di;

sys/arch/amd64/include/biosvar.h

243

uint32_t biosr_ds;

sys/arch/amd64/include/biosvar.h

244

uint32_t biosr_es;

sys/arch/amd64/include/biosvar.h

74

uint32_t entry; /* initialization entry point */

sys/arch/amd64/include/cpu.h

63

uint32_t vr_revision;

sys/arch/amd64/include/cpu.h

74

uint32_t vmx_vmxon_revision;

sys/arch/amd64/include/cpu.h

75

uint32_t vmx_msr_table_size;

sys/arch/amd64/include/cpu.h

76

uint32_t vmx_cr3_tgt_count;

sys/arch/amd64/include/cpu.h

85

uint32_t svm_max_asid;

sys/arch/amd64/include/cpufunc.h

247

uint32_t hi, lo;

sys/arch/amd64/include/cpufunc.h

252

static __inline uint32_t

sys/arch/amd64/include/cpufunc.h

255

uint32_t edx, pkru;

sys/arch/amd64/include/cpufunc.h

261

wrpkru(u_int ecx, uint32_t pkru)

sys/arch/amd64/include/cpufunc.h

263

uint32_t edx = 0;

sys/arch/amd64/include/cpufunc.h

285

uint32_t hi, lo;

sys/arch/amd64/include/cpufunc.h

338

uint32_t hi, lo;

sys/arch/amd64/include/cpufunc.h

347

uint32_t hi, lo;

sys/arch/amd64/include/cpufunc.h

356

uint32_t hi, lo;

sys/arch/amd64/include/cpufunc.h

365

uint32_t hi, lo;

sys/arch/amd64/include/cpufunc.h

403

xsetbv(uint32_t reg, uint64_t mask)

sys/arch/amd64/include/cpufunc.h

405

uint32_t lo, hi;

sys/arch/amd64/include/cpufunc.h

413

xgetbv(uint32_t reg)

sys/arch/amd64/include/cpufunc.h

415

uint32_t lo, hi;

sys/arch/amd64/include/fpu.h

102

uint32_t lo, hi;

sys/arch/amd64/include/fpu.h

62

extern uint32_t fpu_mxcsr_mask;

sys/arch/amd64/include/fpu.h

80

int xsetbv_user(uint32_t _reg, uint64_t _mask);

sys/arch/amd64/include/fpu.h

92

uint32_t lo, hi;

sys/arch/amd64/include/ghcb.h

139

void _ghcb_io_rw(uint16_t, int, uint32_t *, bool);

sys/arch/amd64/include/ghcb.h

159

static inline uint32_t

sys/arch/amd64/include/ghcb.h

162

uint32_t val;

sys/arch/amd64/include/ghcb.h

190

ghcb_mem_write_4(vaddr_t addr, uint32_t v)

sys/arch/amd64/include/ghcb.h

204

uint32_t val;

sys/arch/amd64/include/ghcb.h

213

uint32_t val;

sys/arch/amd64/include/ghcb.h

219

static inline uint32_t

sys/arch/amd64/include/ghcb.h

222

uint32_t val;

sys/arch/amd64/include/ghcb.h

231

uint32_t val = v;

sys/arch/amd64/include/ghcb.h

239

uint32_t val = v;

sys/arch/amd64/include/ghcb.h

245

ghcb_io_write_4(uint16_t port, uint32_t v)

sys/arch/amd64/include/ghcb.h

89

uint32_t v_ghcb_usage; /* FFCh-FFFh */

sys/arch/amd64/include/ieee.h

92

(a)[0] = (uint32_t)(p)->ext_fracl; \

sys/arch/amd64/include/ieee.h

93

(a)[1] = (uint32_t)(p)->ext_frach; \

sys/arch/amd64/include/ptrace.h

49

uint32_t xsave_len;

sys/arch/amd64/include/smbiosvar.h

150

uint32_t charext;

sys/arch/amd64/include/smbiosvar.h

229

uint32_t cpu_id_eax;

sys/arch/amd64/include/smbiosvar.h

230

uint32_t cpu_id_edx;

sys/arch/amd64/include/smbiosvar.h

55

uint32_t sig; /* "_SM_" */

sys/arch/amd64/include/smbiosvar.h

66

uint32_t addr; /* Structure table address */

sys/arch/amd64/include/smbiosvar.h

80

uint32_t size; /* Structure table maximum size */

sys/arch/amd64/include/smbiosvar.h

93

uint32_t cookie;

sys/arch/amd64/include/vmmvar.h

1020

uint32_t vc_vmx_vmcs_state; /* [a] */

sys/arch/amd64/include/vmmvar.h

1069

int svm_get_vmsa_pa(uint32_t, uint32_t, uint64_t *);

sys/arch/amd64/include/vmmvar.h

325

uint32_t nr_rvi_cpus; /* [I] */

sys/arch/amd64/include/vmmvar.h

326

uint32_t nr_ept_cpus; /* [I] */

sys/arch/amd64/include/vmmvar.h

341

uint32_t vei_data; /* data */

sys/arch/amd64/include/vmmvar.h

362

uint32_t vie_errorcode; /* Optional error code. */

sys/arch/amd64/include/vmmvar.h

378

uint32_t vsi_limit;

sys/arch/amd64/include/vmmvar.h

379

uint32_t vsi_ar;

sys/arch/amd64/include/vmmvar.h

480

uint32_t vip_vm_id;

sys/arch/amd64/include/vmmvar.h

481

uint32_t vip_vcpu_id;

sys/arch/amd64/include/vmmvar.h

498

uint32_t vrwp_vm_id;

sys/arch/amd64/include/vmmvar.h

499

uint32_t vrwp_vcpu_id;

sys/arch/amd64/include/vmmvar.h

634

uint32_t vs_lim; /* 004h */

sys/arch/amd64/include/vmmvar.h

649

uint32_t v_cr_rw; /* 000h */

sys/arch/amd64/include/vmmvar.h

650

uint32_t v_dr_rw; /* 004h */

sys/arch/amd64/include/vmmvar.h

651

uint32_t v_excp; /* 008h */

sys/arch/amd64/include/vmmvar.h

652

uint32_t v_intercept1; /* 00Ch */

sys/arch/amd64/include/vmmvar.h

653

uint32_t v_intercept2; /* 010h */

sys/arch/amd64/include/vmmvar.h

660

uint32_t v_asid; /* 058h */

sys/arch/amd64/include/vmmvar.h

710

uint32_t v_pad7; /* 0CCh-0CFh */

sys/arch/amd64/include/vmmvar.h

807

uint32_t v_pkru; /* 2E8h */

sys/arch/amd64/include/vmmvar.h

808

uint32_t v_tsc_aux; /* 2ECh */

sys/arch/amd64/include/vmmvar.h

842

uint32_t v_mxcsr; /* 408h */

sys/arch/amd64/include/vmmvar.h

875

uint32_t vmcs_revision;

sys/arch/amd64/include/vmmvar.h

919

uint32_t vg_exit_reason; /* 0x88 */

sys/arch/amd64/include/vmmvar.h

965

uint32_t vc_id; /* [I] */

sys/arch/amd64/include/vmmvar.h

988

uint32_t vc_pvclock_version; /* [v] */

sys/arch/amd64/include/vmmvar.h

990

uint32_t vc_pvclock_system_tsc_mul; /* [v] */

sys/arch/amd64/include/vmmvar.h

996

uint32_t vc_pkru; /* [v] */

sys/arch/amd64/pci/acpipci.c

329

uint32_t buf[3];

sys/arch/amd64/pci/acpipci.c

353

uint32_t *p = (uint32_t *)res.v_buffer;

sys/arch/amd64/pci/acpipci.c

68

uint32_t sc_seg;

sys/arch/amd64/pci/pci_machdep.c

584

uint32_t ctrl;

sys/arch/amd64/pci/pci_machdep.c

610

uint32_t ctrl;

sys/arch/amd64/pci/pci_machdep.c

635

uint32_t ctrl;

sys/arch/amd64/pci/pci_machdep.c

672

uint32_t ctrl;

sys/arch/amd64/pci/vga_post.c

111

vm86_emu_outl(struct x86emu *emu, uint16_t port, uint32_t val)

sys/arch/amd64/pci/vga_post.c

49

uint32_t initial_eax;

sys/arch/amd64/pci/vga_post.c

80

static uint32_t

sys/arch/amd64/stand/efiboot/efidev.c

280

uint32_t orig_csum, new_csum;

sys/arch/amd64/stand/efiboot/efidev.c

281

uint32_t ghsize, ghpartsize, ghpartnum, ghpartspersec;

sys/arch/amd64/stand/efiboot/efidev.c

282

uint32_t gpsectors;

sys/arch/amd64/stand/efiboot/exec_i386.c

171

uint32_t model, family, stepping;

sys/arch/amd64/stand/efiboot/exec_i386.c

172

uint32_t dummy, signature;

sys/arch/amd64/stand/efiboot/exec_i386.c

173

uint32_t vendor[4];

sys/arch/amd64/stand/efiboot/exec_i386.c

245

uint32_t max_ex_leaf, sev_feat;

sys/arch/amd64/stand/efiboot/exec_i386.c

246

uint32_t vendor[4];

sys/arch/amd64/stand/efiboot/exec_i386.c

247

uint32_t sev_status, dummy;

sys/arch/amd64/stand/efiboot/machdep.c

54

uint32_t dummy, ebx, ecx, edx;

sys/arch/amd64/stand/efiboot/machdep.c

76

if (memcmp(&ebx, &vmm_hv_signature[0], sizeof(uint32_t)) == 0 &&

sys/arch/amd64/stand/efiboot/machdep.c

77

memcmp(&ecx, &vmm_hv_signature[4], sizeof(uint32_t)) == 0 &&

sys/arch/amd64/stand/efiboot/machdep.c

78

memcmp(&edx, &vmm_hv_signature[8], sizeof(uint32_t)) == 0)

sys/arch/amd64/stand/libsa/exec_i386.c

193

uint32_t model, family, stepping;

sys/arch/amd64/stand/libsa/exec_i386.c

194

uint32_t dummy, signature;

sys/arch/amd64/stand/libsa/exec_i386.c

195

uint32_t vendor[4];

sys/arch/amd64/stand/libsa/machdep.c

52

uint32_t dummy, ebx, ecx, edx;

sys/arch/amd64/stand/libsa/machdep.c

74

if (memcmp(&ebx, &vmm_hv_signature[0], sizeof(uint32_t)) == 0 &&

sys/arch/amd64/stand/libsa/machdep.c

75

memcmp(&ecx, &vmm_hv_signature[4], sizeof(uint32_t)) == 0 &&

sys/arch/amd64/stand/libsa/machdep.c

76

memcmp(&edx, &vmm_hv_signature[8], sizeof(uint32_t)) == 0)

sys/arch/amd64/stand/libsa/mdrandom.c

31

uint32_t hi, lo, acc;

sys/arch/amd64/stand/libsa/pxe.h

198

uint32_t Reserved[2];

sys/arch/amd64/stand/libsa/pxe.h

258

uint32_t XmitGoodFrames; /* Number of successful

sys/arch/amd64/stand/libsa/pxe.h

260

uint32_t RcvGoodFrames; /* Number of good frames

sys/arch/amd64/stand/libsa/pxe.h

262

uint32_t RcvCRCErrors; /* Number of frames with

sys/arch/amd64/stand/libsa/pxe.h

264

uint32_t RcvResourceErrors; /* Number of frames dropped */

sys/arch/amd64/stand/libsa/pxe.h

310

uint32_t EISA_Dev_ID;

sys/arch/amd64/stand/libsa/pxe.h

323

uint32_t LinkSpeed; /* Defined in NDIS 2.0 spec */

sys/arch/amd64/stand/libsa/pxe.h

324

uint32_t ServiceFlags; /* Defined in NDIS 2.0 spec */

sys/arch/amd64/stand/libsa/pxe.h

325

uint32_t Reserved[4]; /* must be 0 */

sys/arch/amd64/stand/libsa/pxe.h

390

uint32_t BufferSize;

sys/arch/amd64/stand/libsa/pxe.h

407

uint32_t FileSize;

sys/arch/amd64/stand/libsa/pxe.h

477

uint32_t ident; /* random number chosen by client */

sys/arch/amd64/stand/libsa/pxe.h

505

uint32_t flags; /* bootp flags/opcodes */

sys/arch/amd64/stand/libsa/pxe.h

57

uint32_t Phy_Addr;

sys/arch/amd64/stand/libsa/pxe.h

63

typedef uint32_t IP4_t;

sys/arch/amd64/stand/libsa/pxe.h

64

typedef uint32_t ADDR32_t;

sys/arch/amd64/stand/libsa/pxe.h

78

uint32_t PMOffset; /* Protected mode entry */

sys/arch/amd64/stand/libsa/softraid_amd64.c

432

uint32_t orig_csum, new_csum;

sys/arch/amd64/stand/libsa/softraid_amd64.c

433

uint32_t ghsize, ghpartsize, ghpartnum, ghpartspersec;

sys/arch/amd64/stand/libsa/softraid_amd64.c

434

uint32_t gpsectors;

sys/arch/arm/arm/cpu.c

157

void cpu_opp_init(struct cpu_info *, uint32_t);

sys/arch/arm/arm/cpu.c

164

uint32_t midr, impl, part;

sys/arch/arm/arm/cpu.c

165

uint32_t clidr;

sys/arch/arm/arm/cpu.c

166

uint32_t ctr, ccsidr, sets, ways, line;

sys/arch/arm/arm/cpu.c

326

uint32_t mpidr;

sys/arch/arm/arm/cpu.c

346

uint32_t mpidr;

sys/arch/arm/arm/cpu.c

347

uint32_t opp;

sys/arch/arm/arm/cpu.c

478

uint32_t ttbr0;

sys/arch/arm/arm/cpu.c

599

uint32_t opp_microvolt;

sys/arch/arm/arm/cpu.c

604

uint32_t ot_phandle;

sys/arch/arm/arm/cpu.c

621

uint32_t cpu_opp_get_cooling_level(void *, uint32_t *);

sys/arch/arm/arm/cpu.c

622

void cpu_opp_set_cooling_level(void *, uint32_t *, uint32_t);

sys/arch/arm/arm/cpu.c

629

uint32_t opp_hz, opp_microvolt;

sys/arch/arm/arm/cpu.c

630

uint32_t *opps, supply;

sys/arch/arm/arm/cpu.c

644

count = len / (2 * sizeof(uint32_t));

sys/arch/arm/arm/cpu.c

652

while (count < len / (2 * sizeof(uint32_t))) {

sys/arch/arm/arm/cpu.c

692

cpu_opp_init(struct cpu_info *ci, uint32_t phandle)

sys/arch/arm/arm/cpu.c

697

uint32_t opp_hz, opp_microvolt;

sys/arch/arm/arm/cpu.c

698

uint32_t values[3];

sys/arch/arm/arm/cpu.c

738

if (len == sizeof(uint32_t) || len == 3 * sizeof(uint32_t))

sys/arch/arm/arm/cpu.c

793

uint32_t curr_microvolt;

sys/arch/arm/arm/cpu.c

871

uint32_t curr_microvolt, opp_microvolt;

sys/arch/arm/arm/cpu.c

953

uint32_t

sys/arch/arm/arm/cpu.c

954

cpu_opp_get_cooling_level(void *cookie, uint32_t *cells)

sys/arch/arm/arm/cpu.c

963

cpu_opp_set_cooling_level(void *cookie, uint32_t *cells, uint32_t level)

sys/arch/arm/arm/cpufunc.c

169

uint32_t ctype;

sys/arch/arm/arm/cpufunc.c

170

uint32_t cachereg;

sys/arch/arm/arm/cpufunc.c

171

uint32_t cache_level_id;

sys/arch/arm/arm/cpufunc.c

172

uint32_t sets;

sys/arch/arm/arm/cpufunc.c

173

uint32_t sel, level;

sys/arch/arm/arm/cpufunc.c

257

uint32_t arg;

sys/arch/arm/arm/cpufunc.c

269

uint32_t wayincr, setincr;

sys/arch/arm/arm/cpufunc.c

270

uint32_t wayval, setval;

sys/arch/arm/arm/cpufunc.c

271

uint32_t word;

sys/arch/arm/arm/cpufunc.c

321

uint32_t mmfr0;

sys/arch/arm/arm/cpufunc.c

360

uint32_t auxctrl, auxctrlmask;

sys/arch/arm/arm/cpufunc.c

361

uint32_t cpuctrl, cpuctrlmask;

sys/arch/arm/arm/cpufunc.c

362

uint32_t id_pfr1;

sys/arch/arm/arm/db_interface.c

350

uint32_t fpexc)

sys/arch/arm/arm/db_interface.c

61

int db_trapper (u_int, u_int, trapframe_t *, int, uint32_t);

sys/arch/arm/arm/fault.c

609

extern int badaddr_read_4(const uint32_t *, uint32_t *);

sys/arch/arm/arm/fault.c

613

uint32_t v4;

sys/arch/arm/arm/fault.c

633

case sizeof(uint32_t):

sys/arch/arm/arm/fault.c

636

*(uint32_t *) rptr = u.v4;

sys/arch/arm/arm/pmap7.c

2734

uint32_t id_mmfr0, id_mmfr3;

sys/arch/arm/arm/undefined.c

105

gdb_trapper(u_int addr, u_int insn, struct trapframe *frame, int code, uint32_t fpexc)

sys/arch/arm/arm/undefined.c

147

uint32_t fpexc;

sys/arch/arm/arm/undefined.c

67

static int gdb_trapper(u_int, u_int, struct trapframe *, int, uint32_t);

sys/arch/arm/arm/vfp.c

139

uint32_t scratch = 0;

sys/arch/arm/arm/vfp.c

173

uint32_t fpexc)

sys/arch/arm/arm/vfp.c

29

set_vfp_fpexc(uint32_t val)

sys/arch/arm/arm/vfp.c

36

static inline uint32_t

sys/arch/arm/arm/vfp.c

39

uint32_t val;

sys/arch/arm/arm/vfp.c

46

int vfp_fault(unsigned int, unsigned int, trapframe_t *, int, uint32_t);

sys/arch/arm/arm/vfp.c

53

uint32_t val;

sys/arch/arm/arm/vfp.c

67

uint32_t scratch;

sys/arch/arm/arm/vfp.c

83

uint32_t

sys/arch/arm/arm/vfp.c

89

uint32_t fpexc;

sys/arch/arm/cortex/agtimer.c

102

uint32_t val;

sys/arch/arm/cortex/agtimer.c

110

agtimer_set_ctrl(uint32_t val)

sys/arch/arm/cortex/agtimer.c

122

agtimer_set_tval(uint32_t val)

sys/arch/arm/cortex/agtimer.c

183

uint32_t cycles;

sys/arch/arm/cortex/agtimer.c

285

uint32_t reg;

sys/arch/arm/cortex/agtimer.c

301

uint32_t id_pfr1, cntfrq = 0;

sys/arch/arm/cortex/ampintc.c

188

uint32_t ampintc_iack(void);

sys/arch/arm/cortex/ampintc.c

189

void ampintc_eoi(uint32_t);

sys/arch/arm/cortex/ampintc.c

237

uint32_t ictr;

sys/arch/arm/cortex/ampintc.c

389

uint32_t prival;

sys/arch/arm/cortex/ampintc.c

445

uint32_t ctrl;

sys/arch/arm/cortex/ampintc.c

544

uint32_t

sys/arch/arm/cortex/ampintc.c

547

uint32_t intid;

sys/arch/arm/cortex/ampintc.c

556

ampintc_eoi(uint32_t eoi)

sys/arch/arm/cortex/ampintc.c

627

uint32_t iack_val;

sys/arch/arm/cortex/ampintc.c

860

uint32_t typer;

sys/arch/arm/cortex/amptimer.c

130

uint32_t high0, high1, low;

sys/arch/arm/cortex/amptimer.c

219

uint32_t cycles, reg;

sys/arch/arm/cortex/arml2cc.c

109

void arml2cc_cache_way_op(struct arml2cc_softc *, bus_size_t, uint32_t);

sys/arch/arm/cortex/arml2cc.c

110

void arml2cc_cache_op(struct arml2cc_softc *, bus_size_t, uint32_t);

sys/arch/arm/cortex/arml2cc.c

197

arml2cc_cache_op(struct arml2cc_softc *sc, bus_size_t off, uint32_t val)

sys/arch/arm/cortex/arml2cc.c

206

arml2cc_cache_way_op(struct arml2cc_softc *sc, bus_size_t off, uint32_t way_mask)

sys/arch/arm/cortex/arml2cc.c

93

uint32_t sc_enabled;

sys/arch/arm/cortex/arml2cc.c

94

uint32_t sc_waymask;

sys/arch/arm/cortex/arml2cc.c

95

uint32_t sc_dcache_line_size;

sys/arch/arm/cortex/cortex.h

53

uint32_t ca_periphbase;

sys/arch/arm/cortex/smc.h

27

uint32_t, uint32_t);

sys/arch/arm/include/cpu.h

174

uint32_t ci_cpl;

sys/arch/arm/include/cpu.h

175

uint32_t ci_ipending;

sys/arch/arm/include/cpu.h

176

uint32_t ci_idepth;

sys/arch/arm/include/cpu.h

187

uint32_t ci_cpu_supply;

sys/arch/arm/include/cpu.h

192

uint32_t ci_ttbr0;

sys/arch/arm/include/cpu.h

318

uint32_t cpsr;

sys/arch/arm/include/fdt.h

31

uint32_t *fa_intr;

sys/arch/arm/include/pte.h

85

typedef uint32_t pd_entry_t; /* L1 table entry */

sys/arch/arm/include/pte.h

86

typedef uint32_t pt_entry_t; /* L2 table entry */

sys/arch/arm/include/reg.h

50

uint32_t fp_scr;

sys/arch/arm/include/undefined.h

54

typedef int (*undef_handler_t) (unsigned int, unsigned int, trapframe_t *, int, uint32_t);

sys/arch/arm/include/vfp.h

132

uint32_t vfp_save(void);

sys/arch/arm/mainbus/mainbus.c

130

if (sc->sc_rangeslen > 0 && !(sc->sc_rangeslen % sizeof(uint32_t))) {

sys/arch/arm/mainbus/mainbus.c

162

uint32_t *cell, *reg;

sys/arch/arm/mainbus/mainbus.c

173

line = (sc->sc_acells + sc->sc_scells) * sizeof(uint32_t);

sys/arch/arm/mainbus/mainbus.c

203

if (len > 0 && (len % sizeof(uint32_t)) == 0) {

sys/arch/arm/mainbus/mainbus.c

205

fa.fa_nintr = len / sizeof(uint32_t);

sys/arch/arm/mainbus/mainbus.c

215

free(fa.fa_intr, M_DEVBUF, fa.fa_nintr * sizeof(uint32_t));

sys/arch/arm/mainbus/mainbus.c

260

uint32_t mpidr;

sys/arch/arm/mainbus/mainbus.c

275

uint32_t mpidr;

sys/arch/arm/simplebus/simplebus.c

109

(sc->sc_dmarangeslen % sizeof(uint32_t)) == 0) {

sys/arch/arm/simplebus/simplebus.c

171

uint32_t *cell, *reg;

sys/arch/arm/simplebus/simplebus.c

197

line = (sc->sc_acells + sc->sc_scells) * sizeof(uint32_t);

sys/arch/arm/simplebus/simplebus.c

227

if (len > 0 && (len % sizeof(uint32_t)) == 0) {

sys/arch/arm/simplebus/simplebus.c

229

fa.fa_nintr = len / sizeof(uint32_t);

sys/arch/arm/simplebus/simplebus.c

248

free(fa.fa_intr, M_DEVBUF, fa.fa_nintr * sizeof(uint32_t));

sys/arch/arm/simplebus/simplebus.c

260

uint32_t *range;

sys/arch/arm/simplebus/simplebus.c

273

rlen = sc->sc_rangeslen / sizeof(uint32_t);

sys/arch/arm/simplebus/simplebus.c

323

rlen = sc->sc_dmarangeslen / sizeof(uint32_t);

sys/arch/arm/simplebus/simplebus.c

329

uint32_t *range;

sys/arch/arm/simplebus/simplebus.c

381

rlen = sc->sc_dmarangeslen / sizeof(uint32_t);

sys/arch/arm/simplebus/simplebus.c

387

uint32_t *range;

sys/arch/arm/simplebus/simplebus.c

96

(sc->sc_rangeslen % sizeof(uint32_t)) == 0) {

sys/arch/arm64/arm64/acpi_machdep.c

122

acpi_acquire_glk(uint32_t *lock)

sys/arch/arm64/arm64/acpi_machdep.c

129

acpi_release_glk(uint32_t *lock)

sys/arch/arm64/arm64/acpi_machdep.c

149

uint32_t interrupt[3];

sys/arch/arm64/arm64/bus_space.c

104

uint32_t v)

sys/arch/arm64/arm64/bus_space.c

106

*(volatile uint32_t *)(h + o) = v;

sys/arch/arm64/arm64/bus_space.c

144

volatile uint32_t *addr = (volatile uint32_t *)(h + o);

sys/arch/arm64/arm64/bus_space.c

147

*(uint32_t *)buf = *addr;

sys/arch/arm64/arm64/bus_space.c

156

volatile uint32_t *addr = (volatile uint32_t *)(h + o);

sys/arch/arm64/arm64/bus_space.c

159

*addr = *(uint32_t *)buf;

sys/arch/arm64/arm64/bus_space.c

76

uint32_t

sys/arch/arm64/arm64/bus_space.c

79

return *(volatile uint32_t *)(h + o);

sys/arch/arm64/arm64/cpu.c

1527

uint32_t opp;

sys/arch/arm64/arm64/cpu.c

2178

uint32_t cpu_opp_get_cooling_level(void *, uint32_t *);

sys/arch/arm64/arm64/cpu.c

2179

void cpu_opp_set_cooling_level(void *, uint32_t *, uint32_t);

sys/arch/arm64/arm64/cpu.c

2182

cpu_opp_init(struct cpu_info *ci, uint32_t phandle)

sys/arch/arm64/arm64/cpu.c

2187

uint32_t opp_hz, opp_microvolt;

sys/arch/arm64/arm64/cpu.c

2188

uint32_t values[3];

sys/arch/arm64/arm64/cpu.c

2228

if (len == sizeof(uint32_t) || len == 3 * sizeof(uint32_t))

sys/arch/arm64/arm64/cpu.c

2283

uint32_t curr_microvolt;

sys/arch/arm64/arm64/cpu.c

2365

uint32_t curr_microvolt, opp_microvolt;

sys/arch/arm64/arm64/cpu.c

2447

uint32_t

sys/arch/arm64/arm64/cpu.c

2448

cpu_opp_get_cooling_level(void *cookie, uint32_t *cells)

sys/arch/arm64/arm64/cpu.c

2457

cpu_opp_set_cooling_level(void *cookie, uint32_t *cells, uint32_t level)

sys/arch/arm64/arm64/cpu.c

2477

uint32_t *domains;

sys/arch/arm64/arm64/cpu.c

2478

uint32_t *domain;

sys/arch/arm64/arm64/cpu.c

2479

uint32_t *states;

sys/arch/arm64/arm64/cpu.c

2480

uint32_t ncells;

sys/arch/arm64/arm64/cpu.c

2481

uint32_t cluster;

sys/arch/arm64/arm64/cpu.c

2491

if (len < (int)sizeof(uint32_t))

sys/arch/arm64/arm64/cpu.c

2499

uint32_t entry, exit, residency, param;

sys/arch/arm64/arm64/cpu.c

2548

while (domain && domain < domains + (len / sizeof(uint32_t))) {

sys/arch/arm64/arm64/cpu.c

2579

if (len < (int)sizeof(uint32_t))

sys/arch/arm64/arm64/cpu.c

2585

node = OF_getnodebyphandle(states[len / sizeof(uint32_t) - 1]);

sys/arch/arm64/arm64/cpu.c

2617

node = OF_getnodebyphandle(states[len / sizeof(uint32_t) - 1]);

sys/arch/arm64/arm64/cpu.c

282

uint32_t opp_microvolt;

sys/arch/arm64/arm64/cpu.c

287

uint32_t ot_phandle;

sys/arch/arm64/arm64/cpu.c

325

void cpu_opp_init(struct cpu_info *, uint32_t);

sys/arch/arm64/arm64/cpu.c

550

uint32_t ctr, sets, ways, line;

sys/arch/arm64/arm64/cryptox.c

318

cryptox_get(uint32_t sid)

sys/arch/arm64/arm64/cryptox.c

40

uint32_t rd_key[4 *(AES_MAXROUNDS + 1)];

sys/arch/arm64/arm64/cryptox.c

47

uint32_t ses_klen;

sys/arch/arm64/arm64/cryptox.c

59

uint32_t sc_sid;

sys/arch/arm64/arm64/cryptox.c

67

uint32_t cryptox_ops;

sys/arch/arm64/arm64/cryptox.c

89

cryptox_get(uint32_t);

sys/arch/arm64/arm64/db_disasm.c

43

return db_get_value(address, sizeof(uint32_t), false);

sys/arch/arm64/arm64/disasm.c

1003

csetsel_common(const disasm_interface_t *di, uint64_t pc, uint32_t insn,

sys/arch/arm64/arm64/disasm.c

1230

uint32_t code;

sys/arch/arm64/arm64/disasm.c

1297

uint32_t code;

sys/arch/arm64/arm64/disasm.c

1526

crc32_common(const disasm_interface_t *di, uint64_t pc, uint32_t insn,

sys/arch/arm64/arm64/disasm.c

226

uint32_t code;

sys/arch/arm64/arm64/disasm.c

3624

uint32_t mask;

sys/arch/arm64/arm64/disasm.c

3625

uint32_t pattern;

sys/arch/arm64/arm64/disasm.c

3984

disasm_insn(const disasm_interface_t *di, vaddr_t loc, uint32_t insn)

sys/arch/arm64/arm64/disasm.c

4010

uint32_t insn;

sys/arch/arm64/arm64/disasm.c

538

sysregname_bsearch(uint32_t code)

sys/arch/arm64/arm64/disasm.c

54

func(const disasm_interface_t *di, uint64_t pc, uint32_t insn, \

sys/arch/arm64/arm64/disasm.c

562

sysregname(char *buf, size_t buflen, uint32_t rw,

sys/arch/arm64/arm64/disasm.c

566

uint32_t code;

sys/arch/arm64/arm64/disasm.c

744

extendreg_common(const disasm_interface_t *di, uint64_t pc, uint32_t insn,

sys/arch/arm64/arm64/disasm.c

787

shiftreg_common(const disasm_interface_t *di, uint64_t pc, uint32_t insn,

sys/arch/arm64/arm64/disasm.c

835

regoffset_b_common(const disasm_interface_t *di, uint64_t pc, uint32_t insn,

sys/arch/arm64/arm64/disasm.c

867

regoffset_h_common(const disasm_interface_t *di, uint64_t pc, uint32_t insn,

sys/arch/arm64/arm64/disasm.c

905

regoffset_w_common(const disasm_interface_t *di, uint64_t pc, uint32_t insn,

sys/arch/arm64/arm64/disasm.c

943

regoffset_x_common(const disasm_interface_t *di, uint64_t pc, uint32_t insn,

sys/arch/arm64/arm64/disasm.c

977

addsub_imm_common(const disasm_interface_t *di, uint64_t pc, uint32_t insn,

sys/arch/arm64/arm64/disasm.h

40

void disasm_insn(const disasm_interface_t *, vaddr_t, uint32_t);

sys/arch/arm64/arm64/intr.c

109

uint32_t phandle;

sys/arch/arm64/arm64/intr.c

123

uint32_t

sys/arch/arm64/arm64/intr.c

127

uint32_t phandle = 0;

sys/arch/arm64/arm64/intr.c

128

uint32_t *cell;

sys/arch/arm64/arm64/intr.c

129

uint32_t *map;

sys/arch/arm64/arm64/intr.c

130

uint32_t mask, rid_base, rid;

sys/arch/arm64/arm64/intr.c

150

ncells = len / sizeof(uint32_t);

sys/arch/arm64/arm64/intr.c

205

uint32_t ip_phandle;

sys/arch/arm64/arm64/intr.c

206

uint32_t ip_cell[MAX_INTERRUPT_CELLS];

sys/arch/arm64/arm64/intr.c

37

uint32_t arm_intr_map_msi(int, uint64_t *);

sys/arch/arm64/arm64/intr.c

370

uint32_t *cell, *cells, phandle;

sys/arch/arm64/arm64/intr.c

379

if (len <= 0 || (len % sizeof(uint32_t) != 0))

sys/arch/arm64/arm64/intr.c

399

ncells = len / sizeof(uint32_t);

sys/arch/arm64/arm64/intr.c

460

uint32_t *cell;

sys/arch/arm64/arm64/intr.c

461

uint32_t map_mask[4], *map;

sys/arch/arm64/arm64/intr.c

480

ncells = len / sizeof(uint32_t);

sys/arch/arm64/arm64/intr.c

534

uint32_t phandle;

sys/arch/arm64/arm64/intr.c

56

uint32_t arm_smask[NIPL];

sys/arch/arm64/arm64/intr.c

703

uint32_t ipending;

sys/arch/arm64/arm64/machdep.c

767

uint32_t ctr_el0;

sys/arch/arm64/arm64/machdep.c

768

uint32_t dczid_el0;

sys/arch/arm64/arm64/machdep.c

796

uint32_t mmap_size;

sys/arch/arm64/arm64/machdep.c

797

uint32_t mmap_desc_size;

sys/arch/arm64/arm64/machdep.c

798

uint32_t mmap_desc_ver;

sys/arch/arm64/arm64/machdep.c

875

boothowto = bemtoh32((uint32_t *)prop);

sys/arch/arm64/arm64/machdep.c

908

mmap_size = bemtoh32((uint32_t *)prop);

sys/arch/arm64/arm64/machdep.c

911

mmap_desc_size = bemtoh32((uint32_t *)prop);

sys/arch/arm64/arm64/machdep.c

914

mmap_desc_ver = bemtoh32((uint32_t *)prop);

sys/arch/arm64/arm64/machdep.c

944

uint32_t csize, size = round_page(fdt_get_size(config));

sys/arch/arm64/arm64/machdep.c

960

uint32_t csize, size = round_page(mmap_size);

sys/arch/arm64/arm64/pmap.c

222

uint32_t pmap_asid[PMAP_MAX_NASID / 32];

sys/arch/arm64/arm64/pmap.c

229

uint32_t bits;

sys/arch/arm64/arm64/pmap.c

277

memset(pmap_asid, 0, (pmap_nasid / 32) * sizeof(uint32_t));

sys/arch/arm64/arm64/trap.c

315

uint32_t exception;

sys/arch/arm64/arm64/trap.c

376

uint32_t exception;

sys/arch/arm64/arm64/trap.c

64

uint32_t insn = *(uint32_t *)elr;

sys/arch/arm64/dev/acpiiort.c

107

acpiiort_smmu_reserve_region(struct acpi_iort_node *node, uint32_t rid,

sys/arch/arm64/dev/acpiiort.c

130

uint32_t rid, offset;

sys/arch/arm64/dev/acpiiort.c

67

uint32_t offset;

sys/arch/arm64/dev/acpiiort.c

93

acpiiort_smmu_map(struct acpi_iort_node *node, uint32_t rid,

sys/arch/arm64/dev/acpiiort.h

29

bus_dma_tag_t (*as_map)(void *, uint32_t,

sys/arch/arm64/dev/acpiiort.h

31

void (*as_reserve)(void *, uint32_t,

sys/arch/arm64/dev/acpiiort.h

36

bus_dma_tag_t acpiiort_smmu_map(struct acpi_iort_node *, uint32_t, bus_dma_tag_t);

sys/arch/arm64/dev/acpiiort.h

37

void acpiiort_smmu_reserve_region(struct acpi_iort_node *, uint32_t, bus_addr_t, bus_size_t);

sys/arch/arm64/dev/acpipci.c

127

uint32_t acpipci_iort_map_msi(pci_chipset_tag_t, pcitag_t,

sys/arch/arm64/dev/acpipci.c

388

uint32_t rid, offset;

sys/arch/arm64/dev/acpipci.c

651

if (bus_dmamap_create(aih->aih_dmat, sizeof(uint32_t), 1,

sys/arch/arm64/dev/acpipci.c

652

sizeof(uint32_t), 0, BUS_DMA_WAITOK, &aih->aih_map)) {

sys/arch/arm64/dev/acpipci.c

660

seg.ds_len = sizeof(uint32_t);

sys/arch/arm64/dev/acpipci.c

663

&seg, 1, sizeof(uint32_t), BUS_DMA_WAITOK)) {

sys/arch/arm64/dev/acpipci.c

79

uint32_t sc_seg;

sys/arch/arm64/dev/acpipci.c

806

uint32_t acpipci_iort_map(struct acpi_iort *, uint32_t, uint32_t,

sys/arch/arm64/dev/acpipci.c

809

uint32_t

sys/arch/arm64/dev/acpipci.c

811

struct acpi_iort_node *node, uint32_t id, struct interrupt_controller **ic)

sys/arch/arm64/dev/acpipci.c

818

uint32_t offset = map[i].output_reference;

sys/arch/arm64/dev/acpipci.c

836

uint32_t

sys/arch/arm64/dev/acpipci.c

837

acpipci_iort_map(struct acpi_iort *iort, uint32_t offset, uint32_t id,

sys/arch/arm64/dev/acpipci.c

868

uint32_t

sys/arch/arm64/dev/acpipci.c

878

uint32_t rid, offset;

sys/arch/arm64/dev/agintc.c

1033

uint32_t

sys/arch/arm64/dev/agintc.c

1354

agintc_eoi(uint32_t eoi)

sys/arch/arm64/dev/agintc.c

1364

uint32_t v;

sys/arch/arm64/dev/agintc.c

1380

uint32_t v;

sys/arch/arm64/dev/agintc.c

1506

uint32_t deviceid;

sys/arch/arm64/dev/agintc.c

1507

uint32_t eventid;

sys/arch/arm64/dev/agintc.c

1508

uint32_t intid;

sys/arch/arm64/dev/agintc.c

1530

uint32_t md_deviceid;

sys/arch/arm64/dev/agintc.c

1531

uint32_t md_events;

sys/arch/arm64/dev/agintc.c

1555

uint32_t sc_deviceid_max;

sys/arch/arm64/dev/agintc.c

157

uint32_t li_deviceid;

sys/arch/arm64/dev/agintc.c

158

uint32_t li_eventid;

sys/arch/arm64/dev/agintc.c

1612

uint32_t pre_its[2];

sys/arch/arm64/dev/agintc.c

1881

agintc_msi_create_device_table(struct agintc_msi_softc *sc, uint32_t deviceid)

sys/arch/arm64/dev/agintc.c

1884

uint32_t idx = deviceid / (sc->sc_dtt_pgsz / sc->sc_dte_sz);

sys/arch/arm64/dev/agintc.c

1915

agintc_msi_create_device(struct agintc_msi_softc *sc, uint32_t deviceid)

sys/arch/arm64/dev/agintc.c

1944

agintc_msi_find_device(struct agintc_msi_softc *sc, uint32_t deviceid)

sys/arch/arm64/dev/agintc.c

2013

uint32_t deviceid = *data;

sys/arch/arm64/dev/agintc.c

2014

uint32_t eventid;

sys/arch/arm64/dev/agintc.c

252

uint32_t agintc_iack(void);

sys/arch/arm64/dev/agintc.c

253

void agintc_eoi(uint32_t);

sys/arch/arm64/dev/agintc.c

313

uint32_t typer;

sys/arch/arm64/dev/agintc.c

314

uint32_t nsacr, oldnsacr;

sys/arch/arm64/dev/agintc.c

315

uint32_t pmr, oldpmr;

sys/arch/arm64/dev/agintc.c

316

uint32_t ctrl, bits;

sys/arch/arm64/dev/agintc.c

317

uint32_t affinity;

sys/arch/arm64/dev/agintc.c

688

uint32_t *ranges;

sys/arch/arm64/dev/agintc.c

695

if (len <= 0 || len % 2 * sizeof(uint32_t) != 0)

sys/arch/arm64/dev/agintc.c

701

sc->sc_mbi_nranges = len / (2 * sizeof(uint32_t));

sys/arch/arm64/dev/agintc.c

726

uint32_t waker;

sys/arch/arm64/dev/agintc.c

774

uint32_t prival;

sys/arch/arm64/dev/agintc.c

794

uint32_t prival;

sys/arch/arm64/dev/agintc.c

925

uint32_t reg;

sys/arch/arm64/dev/agtimer.c

142

uint32_t val;

sys/arch/arm64/dev/agtimer.c

150

agtimer_set_ctrl(uint32_t val)

sys/arch/arm64/dev/agtimer.c

159

agtimer_set_tval(uint32_t val)

sys/arch/arm64/dev/agtimer.c

246

uint32_t cycles;

sys/arch/arm64/dev/agtimer.c

327

uint32_t reg;

sys/arch/arm64/dev/ampchwm.c

41

uint32_t id;

sys/arch/arm64/dev/ampchwm.c

54

uint32_t pad;

sys/arch/arm64/dev/ampintc.c

192

uint32_t ampintc_iack(void);

sys/arch/arm64/dev/ampintc.c

193

void ampintc_eoi(uint32_t);

sys/arch/arm64/dev/ampintc.c

243

uint32_t ictr;

sys/arch/arm64/dev/ampintc.c

411

uint32_t prival;

sys/arch/arm64/dev/ampintc.c

467

uint32_t ctrl;

sys/arch/arm64/dev/ampintc.c

571

uint32_t

sys/arch/arm64/dev/ampintc.c

574

uint32_t intid;

sys/arch/arm64/dev/ampintc.c

583

ampintc_eoi(uint32_t eoi)

sys/arch/arm64/dev/ampintc.c

712

uint32_t iack_val;

sys/arch/arm64/dev/ampintc.c

913

uint32_t typer;

sys/arch/arm64/dev/aplaudio.c

106

uint32_t fmt, pol, clk;

sys/arch/arm64/dev/aplaudio.c

107

uint32_t node, cpu, codec;

sys/arch/arm64/dev/aplaudio.c

108

uint32_t *dais;

sys/arch/arm64/dev/aplaudio.c

138

ncells = len / sizeof(uint32_t);

sys/arch/arm64/dev/aplaudio.c

168

aplaudio_set_format(struct aplaudio_softc *sc, uint32_t fmt, uint32_t pol,

sys/arch/arm64/dev/aplaudio.c

169

uint32_t clk)

sys/arch/arm64/dev/aplaudio.c

277

uint32_t rate;

sys/arch/arm64/dev/aplaudio.c

43

void aplaudio_set_format(struct aplaudio_softc *, uint32_t,

sys/arch/arm64/dev/aplaudio.c

44

uint32_t, uint32_t);

sys/arch/arm64/dev/aplcpu.c

198

uint32_t freq_domain[2], phandle;

sys/arch/arm64/dev/aplcpu.c

199

uint32_t opp_hz, opp_level;

sys/arch/arm64/dev/aplcpu.c

274

uint32_t

sys/arch/arm64/dev/aplcpu.c

277

uint32_t opp_level;

sys/arch/arm64/dev/aplcpu.c

300

uint32_t opp_hz = 0, opp_level;

sys/arch/arm64/dev/aplcpu.c

343

uint32_t opp_level;

sys/arch/arm64/dev/aplcpu.c

416

uint32_t opp_level;

sys/arch/arm64/dev/aplcpu.c

49

uint32_t opp_level;

sys/arch/arm64/dev/aplcpu.c

54

uint32_t ot_phandle;

sys/arch/arm64/dev/aplcpu.c

74

uint32_t sc_cur_ps_mask;

sys/arch/arm64/dev/aplcpu.c

98

uint32_t aplcpu_opp_level(struct aplcpu_softc *, int);

sys/arch/arm64/dev/apldart.c

168

uint32_t sc_tcr_translate_enable;

sys/arch/arm64/dev/apldart.c

169

uint32_t sc_tcr_bypass;

sys/arch/arm64/dev/apldart.c

171

uint32_t sc_ttbr_valid;

sys/arch/arm64/dev/apldart.c

221

bus_dma_tag_t apldart_map(void *, uint32_t *, bus_dma_tag_t);

sys/arch/arm64/dev/apldart.c

222

void apldart_reserve(void *, uint32_t *, bus_addr_t, bus_size_t);

sys/arch/arm64/dev/apldart.c

260

uint32_t config, maj, min, params2, params3, params4, tcr, ttbr;

sys/arch/arm64/dev/apldart.c

449

uint32_t params2;

sys/arch/arm64/dev/apldart.c

450

uint32_t mask;

sys/arch/arm64/dev/apldart.c

527

uint32_t ttbr;

sys/arch/arm64/dev/apldart.c

618

uint32_t mask;

sys/arch/arm64/dev/apldart.c

698

apldart_map(void *cookie, uint32_t *cells, bus_dma_tag_t dmat)

sys/arch/arm64/dev/apldart.c

701

uint32_t sid = cells[0];

sys/arch/arm64/dev/apldart.c

712

apldart_reserve(void *cookie, uint32_t *cells, bus_addr_t addr, bus_size_t size)

sys/arch/arm64/dev/apldart.c

741

uint32_t mask;

sys/arch/arm64/dev/apldart.c

759

uint32_t cmd;

sys/arch/arm64/dev/apldc.c

167

uint32_t stat, pending;

sys/arch/arm64/dev/apldc.c

266

uint32_t ag_gpio[APLDCHIDEV_GPIO_MAX];

sys/arch/arm64/dev/apldc.c

318

uint32_t sc_retcode;

sys/arch/arm64/dev/apldc.c

358

uint32_t phandle;

sys/arch/arm64/dev/apldc.c

445

uint32_t *checksum)

sys/arch/arm64/dev/apldc.c

448

uint32_t data;

sys/arch/arm64/dev/apldc.c

471

uint32_t *checksum)

sys/arch/arm64/dev/apldc.c

474

uint32_t free;

sys/arch/arm64/dev/apldc.c

522

uint32_t retcode;

sys/arch/arm64/dev/apldc.c

562

uint32_t retcode;

sys/arch/arm64/dev/apldc.c

567

uint32_t width;

sys/arch/arm64/dev/apldc.c

568

uint32_t height;

sys/arch/arm64/dev/apldc.c

586

uint32_t gpio[APLDCHIDEV_GPIO_MAX];

sys/arch/arm64/dev/apldc.c

766

uint32_t checksum = 0;

sys/arch/arm64/dev/apldc.c

830

uint32_t checksum = 0xffffffff;

sys/arch/arm64/dev/apldc.c

926

uint32_t size;

sys/arch/arm64/dev/apldc.c

987

uint32_t magic;

sys/arch/arm64/dev/apldc.c

989

uint32_t version;

sys/arch/arm64/dev/apldc.c

991

uint32_t hdr_len;

sys/arch/arm64/dev/apldc.c

992

uint32_t data_len;

sys/arch/arm64/dev/apldc.c

993

uint32_t iface_off;

sys/arch/arm64/dev/apldma.c

228

uint32_t status;

sys/arch/arm64/dev/apldma.c

249

uint32_t intr, intrstat;

sys/arch/arm64/dev/apldma.c

264

uint32_t status;

sys/arch/arm64/dev/apldog.c

47

uint32_t sc_clock_freq;

sys/arch/arm64/dev/apldog.c

48

uint32_t sc_max_period;

sys/arch/arm64/dev/apldog.c

49

uint32_t sc_period;

sys/arch/arm64/dev/apldog.c

84

uint32_t clock_freq;

sys/arch/arm64/dev/aplefuse.c

91

uint32_t value;

sys/arch/arm64/dev/aplhidev.c

143

uint32_t *sc_gpio;

sys/arch/arm64/dev/aplhidev.c

68

uint32_t width;

sys/arch/arm64/dev/aplhidev.c

69

uint32_t height;

sys/arch/arm64/dev/apliic.c

109

uint32_t clock_speed, bus_speed;

sys/arch/arm64/dev/apliic.c

159

uint32_t reg;

sys/arch/arm64/dev/apliic.c

195

uint32_t reg;

sys/arch/arm64/dev/apliic.c

249

uint32_t reg[1];

sys/arch/arm64/dev/apliic.c

72

uint32_t sc_clkdiv;

sys/arch/arm64/dev/aplintc.c

123

uint32_t sc_cpuremap[AIC_MAXCPUS];

sys/arch/arm64/dev/aplintc.c

210

uint32_t info;

sys/arch/arm64/dev/aplintc.c

302

uint32_t hwid;

sys/arch/arm64/dev/aplintc.c

361

uint32_t event;

sys/arch/arm64/dev/aplintc.c

362

uint32_t die, irq, type;

sys/arch/arm64/dev/aplintc.c

556

uint32_t type = cell[0];

sys/arch/arm64/dev/aplintc.c

557

uint32_t die, irq;

sys/arch/arm64/dev/aplmbox.c

129

uint32_t ctrl;

sys/arch/arm64/dev/aplmbox.c

146

aplmbox_channel(void *cookie, uint32_t *cells, struct mbox_client *mc)

sys/arch/arm64/dev/aplmbox.c

166

uint32_t ctrl;

sys/arch/arm64/dev/aplmbox.c

186

uint32_t ctrl;

sys/arch/arm64/dev/aplmbox.c

75

void *aplmbox_channel(void *, uint32_t *, struct mbox_client *);

sys/arch/arm64/dev/aplmbox.h

20

uint32_t data1;

sys/arch/arm64/dev/aplmca.c

121

uint32_t sc_phandle;

sys/arch/arm64/dev/aplmca.c

127

int aplmca_set_format(void *, uint32_t, uint32_t, uint32_t);

sys/arch/arm64/dev/aplmca.c

128

int aplmca_set_sysclk(void *, uint32_t);

sys/arch/arm64/dev/aplmca.c

259

uint32_t conf;

sys/arch/arm64/dev/aplmca.c

305

uint32_t *

sys/arch/arm64/dev/aplmca.c

306

aplmca_dai_next_dai(uint32_t *cells)

sys/arch/arm64/dev/aplmca.c

308

uint32_t phandle = cells[0];

sys/arch/arm64/dev/aplmca.c

323

uint32_t *dais;

sys/arch/arm64/dev/aplmca.c

324

uint32_t *dai;

sys/arch/arm64/dev/aplmca.c

325

uint32_t ports[2];

sys/arch/arm64/dev/aplmca.c

330

if (len != 2 * sizeof(uint32_t) && len != 4 * sizeof(uint32_t))

sys/arch/arm64/dev/aplmca.c

337

while (dai && dai < dais + (len / sizeof(uint32_t))) {

sys/arch/arm64/dev/aplmca.c

371

aplmca_set_format(void *cookie, uint32_t fmt, uint32_t pol,

sys/arch/arm64/dev/aplmca.c

372

uint32_t clk)

sys/arch/arm64/dev/aplmca.c

376

uint32_t conf;

sys/arch/arm64/dev/aplmca.c

408

aplmca_set_sysclk(void *cookie, uint32_t rate)

sys/arch/arm64/dev/aplmca.c

474

uint32_t conf, period;

sys/arch/arm64/dev/aplnco.c

153

aplnco_enable(void *cookie, uint32_t *cells, int on)

sys/arch/arm64/dev/aplnco.c

156

uint32_t idx = cells[0];

sys/arch/arm64/dev/aplnco.c

167

uint32_t

sys/arch/arm64/dev/aplnco.c

168

aplnco_get_frequency(void *cookie, uint32_t *cells)

sys/arch/arm64/dev/aplnco.c

171

uint32_t idx = cells[0];

sys/arch/arm64/dev/aplnco.c

172

uint32_t div, parent_freq;

sys/arch/arm64/dev/aplnco.c

201

aplnco_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/arch/arm64/dev/aplnco.c

204

uint32_t idx = cells[0];

sys/arch/arm64/dev/aplnco.c

205

uint32_t div, parent_freq;

sys/arch/arm64/dev/aplnco.c

208

uint32_t ctrl;

sys/arch/arm64/dev/aplnco.c

72

void aplnco_enable(void *, uint32_t *, int);

sys/arch/arm64/dev/aplnco.c

73

uint32_t aplnco_get_frequency(void *, uint32_t *);

sys/arch/arm64/dev/aplnco.c

74

int aplnco_set_frequency(void *, uint32_t *, uint32_t);

sys/arch/arm64/dev/aplns.c

123

uint32_t asc_sart;

sys/arch/arm64/dev/aplns.c

147

uint32_t nvme_ans_sq_enter(struct nvme_softc *,

sys/arch/arm64/dev/aplns.c

288

uint32_t ctrl, status;

sys/arch/arm64/dev/aplns.c

319

uint32_t ctrl;

sys/arch/arm64/dev/aplns.c

402

uint32_t

sys/arch/arm64/dev/aplns.c

451

uint32_t stat;

sys/arch/arm64/dev/aplns.c

78

uint32_t tcb_prpl_len;

sys/arch/arm64/dev/aplpcie.c

120

uint32_t flags;

sys/arch/arm64/dev/aplpcie.c

159

uint32_t sc_msi_range[6];

sys/arch/arm64/dev/aplpcie.c

218

uint32_t *ranges;

sys/arch/arm64/dev/aplpcie.c

220

uint32_t bus_range[2];

sys/arch/arm64/dev/aplpcie.c

283

(sc->sc_msi_rangelen % sizeof(uint32_t)) ||

sys/arch/arm64/dev/aplpcie.c

284

(sc->sc_msi_rangelen / sizeof(uint32_t)) < 5 ||

sys/arch/arm64/dev/aplpcie.c

285

(sc->sc_msi_rangelen / sizeof(uint32_t) > 6)) {

sys/arch/arm64/dev/aplpcie.c

313

if (rangeslen <= 0 || (rangeslen % sizeof(uint32_t)) ||

sys/arch/arm64/dev/aplpcie.c

314

(rangeslen / sizeof(uint32_t)) % (sc->sc_acells +

sys/arch/arm64/dev/aplpcie.c

324

nranges = (rangeslen / sizeof(uint32_t)) /

sys/arch/arm64/dev/aplpcie.c

443

uint32_t reg[5];

sys/arch/arm64/dev/aplpcie.c

444

uint32_t *pwren_gpio;

sys/arch/arm64/dev/aplpcie.c

445

uint32_t *reset_gpio;

sys/arch/arm64/dev/aplpcie.c

447

uint32_t stat;

sys/arch/arm64/dev/aplpcie.c

564

uint32_t reg[5];

sys/arch/arm64/dev/aplpcie.c

565

uint32_t *pwren_gpio;

sys/arch/arm64/dev/aplpcie.c

566

uint32_t *reset_gpio;

sys/arch/arm64/dev/aplpcie.c

568

uint32_t stat;

sys/arch/arm64/dev/aplpcie.c

699

uint32_t reg[5];

sys/arch/arm64/dev/aplpcie.c

700

uint32_t phys_hi;

sys/arch/arm64/dev/aplpcie.c

770

uint32_t bus_range[2];

sys/arch/arm64/dev/aplpcie.c

771

uint32_t reg[5];

sys/arch/arm64/dev/aplpcie.c

792

aplpcie_map_rid(struct aplpcie_softc *sc, int port, uint16_t rid, uint32_t sid)

sys/arch/arm64/dev/aplpcie.c

794

uint32_t reg;

sys/arch/arm64/dev/aplpcie.c

824

uint32_t sid)

sys/arch/arm64/dev/aplpcie.c

826

uint32_t reg;

sys/arch/arm64/dev/aplpcie.c

858

uint32_t phandle, sid;

sys/arch/arm64/dev/aplpcie.c

952

uint32_t reg[4];

sys/arch/arm64/dev/aplpcie.c

977

uint32_t cells[4];

sys/arch/arm64/dev/aplpcie.c

980

ncells = sc->sc_msi_rangelen / sizeof(uint32_t);

sys/arch/arm64/dev/aplpinctrl.c

100

void aplpinctrl_config_pin(void *, uint32_t *, int);

sys/arch/arm64/dev/aplpinctrl.c

101

int aplpinctrl_get_pin(void *, uint32_t *);

sys/arch/arm64/dev/aplpinctrl.c

102

void aplpinctrl_set_pin(void *, uint32_t *, int);

sys/arch/arm64/dev/aplpinctrl.c

126

uint32_t gpio_ranges[4] = {};

sys/arch/arm64/dev/aplpinctrl.c

185

aplpinctrl_pinctrl(uint32_t phandle, void *cookie)

sys/arch/arm64/dev/aplpinctrl.c

188

uint32_t *pinmux;

sys/arch/arm64/dev/aplpinctrl.c

191

uint32_t reg;

sys/arch/arm64/dev/aplpinctrl.c

204

for (i = 0; i < len / sizeof(uint32_t); i++) {

sys/arch/arm64/dev/aplpinctrl.c

218

aplpinctrl_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/arm64/dev/aplpinctrl.c

221

uint32_t pin = cells[0];

sys/arch/arm64/dev/aplpinctrl.c

222

uint32_t reg;

sys/arch/arm64/dev/aplpinctrl.c

237

aplpinctrl_get_pin(void *cookie, uint32_t *cells)

sys/arch/arm64/dev/aplpinctrl.c

240

uint32_t pin = cells[0];

sys/arch/arm64/dev/aplpinctrl.c

241

uint32_t flags = cells[1];

sys/arch/arm64/dev/aplpinctrl.c

242

uint32_t reg;

sys/arch/arm64/dev/aplpinctrl.c

255

aplpinctrl_set_pin(void *cookie, uint32_t *cells, int val)

sys/arch/arm64/dev/aplpinctrl.c

258

uint32_t pin = cells[0];

sys/arch/arm64/dev/aplpinctrl.c

259

uint32_t flags = cells[1];

sys/arch/arm64/dev/aplpinctrl.c

276

uint32_t status, pending;

sys/arch/arm64/dev/aplpinctrl.c

308

uint32_t pin = cells[0];

sys/arch/arm64/dev/aplpinctrl.c

309

uint32_t type = IST_NONE;

sys/arch/arm64/dev/aplpinctrl.c

310

uint32_t reg;

sys/arch/arm64/dev/aplpinctrl.c

387

uint32_t reg;

sys/arch/arm64/dev/aplpinctrl.c

413

uint32_t reg;

sys/arch/arm64/dev/aplpinctrl.c

448

uint32_t reg;

sys/arch/arm64/dev/aplpinctrl.c

99

int aplpinctrl_pinctrl(uint32_t, void *);

sys/arch/arm64/dev/aplpmgr.c

157

aplpmgr_enable(void *cookie, uint32_t *cells, int on)

sys/arch/arm64/dev/aplpmgr.c

161

uint32_t pstate = on ? PMGR_PS_ACTIVE : PMGR_PS_PWRGATE;

sys/arch/arm64/dev/aplpmgr.c

162

uint32_t val;

sys/arch/arm64/dev/aplpmgr.c

206

aplpmgr_reset(void *cookie, uint32_t *cells, int on)

sys/arch/arm64/dev/aplpmgr.c

210

uint32_t val;

sys/arch/arm64/dev/aplpmgr.c

78

void aplpmgr_enable(void *, uint32_t *, int);

sys/arch/arm64/dev/aplpmgr.c

79

void aplpmgr_reset(void *, uint32_t *, int);

sys/arch/arm64/dev/aplpmgr.c

99

uint32_t reg[2];

sys/arch/arm64/dev/aplpmu.c

136

uint32_t reg[2] = { 0x0, 0x10000 };

sys/arch/arm64/dev/aplpwm.c

112

aplpwm_get_state(void *cookie, uint32_t *cells, struct pwm_state *ps)

sys/arch/arm64/dev/aplpwm.c

116

uint32_t ctrl;

sys/arch/arm64/dev/aplpwm.c

132

aplpwm_set_state(void *cookie, uint32_t *cells, struct pwm_state *ps)

sys/arch/arm64/dev/aplpwm.c

136

uint32_t ctrl;

sys/arch/arm64/dev/aplpwm.c

65

int aplpwm_get_state(void *, uint32_t *, struct pwm_state *);

sys/arch/arm64/dev/aplpwm.c

66

int aplpwm_set_state(void *, uint32_t *, struct pwm_state *);

sys/arch/arm64/dev/aplrtk.c

100

uint32_t ctrl;

sys/arch/arm64/dev/aplrtk.c

115

aplrtk_start(uint32_t phandle)

sys/arch/arm64/dev/aplrtk.c

47

uint32_t sc_phandle;

sys/arch/arm64/dev/aplsart.c

135

uint32_t conf;

sys/arch/arm64/dev/aplsart.c

155

uint32_t conf;

sys/arch/arm64/dev/aplsart.c

173

aplsart_map(uint32_t phandle, bus_addr_t addr, bus_size_t size)

sys/arch/arm64/dev/aplsart.c

228

aplsart_unmap(uint32_t phandle, bus_addr_t addr, bus_size_t size)

sys/arch/arm64/dev/aplsart.c

58

uint32_t sc_phandle;

sys/arch/arm64/dev/aplsmc.c

144

uint32_t sc_suspend_pstr;

sys/arch/arm64/dev/aplsmc.c

196

int aplsmc_send_cmd(struct aplsmc_softc *, uint16_t, uint32_t, uint16_t);

sys/arch/arm64/dev/aplsmc.c

198

int aplsmc_read_key(struct aplsmc_softc *, uint32_t, void *, size_t);

sys/arch/arm64/dev/aplsmc.c

199

int aplsmc_write_key(struct aplsmc_softc *, uint32_t, void *, size_t);

sys/arch/arm64/dev/aplsmc.c

200

int64_t aplsmc_convert_flt(uint32_t, int);

sys/arch/arm64/dev/aplsmc.c

203

void aplsmc_set_pin(void *, uint32_t *, int);

sys/arch/arm64/dev/aplsmc.c

406

uint32_t flt = 0;

sys/arch/arm64/dev/aplsmc.c

504

aplsmc_send_cmd(struct aplsmc_softc *sc, uint16_t cmd, uint32_t key,

sys/arch/arm64/dev/aplsmc.c

539

aplsmc_read_key(struct aplsmc_softc *sc, uint32_t key, void *data, size_t len)

sys/arch/arm64/dev/aplsmc.c

559

if (len > sizeof(uint32_t)) {

sys/arch/arm64/dev/aplsmc.c

563

uint32_t tmp = (sc->sc_data >> 32);

sys/arch/arm64/dev/aplsmc.c

571

aplsmc_write_key(struct aplsmc_softc *sc, uint32_t key, void *data, size_t len)

sys/arch/arm64/dev/aplsmc.c

583

aplsmc_convert_flt(uint32_t flt, int scale)

sys/arch/arm64/dev/aplsmc.c

609

uint32_t key;

sys/arch/arm64/dev/aplsmc.c

629

uint32_t flt;

sys/arch/arm64/dev/aplsmc.c

712

aplsmc_set_pin(void *cookie, uint32_t *cells, int val)

sys/arch/arm64/dev/aplsmc.c

716

uint32_t pin = cells[0];

sys/arch/arm64/dev/aplsmc.c

717

uint32_t flags = cells[1];

sys/arch/arm64/dev/aplsmc.c

718

uint32_t key = SMC_KEY("gP\0\0");

sys/arch/arm64/dev/aplsmc.c

719

uint32_t data;

sys/arch/arm64/dev/aplsmc.c

795

uint32_t key = SMC_KEY("MBSE");

sys/arch/arm64/dev/aplsmc.c

796

uint32_t rest = SMC_KEY("rest");

sys/arch/arm64/dev/aplsmc.c

797

uint32_t phra = SMC_KEY("phra");

sys/arch/arm64/dev/aplsmc.c

810

uint32_t key = SMC_KEY("MBSE");

sys/arch/arm64/dev/aplsmc.c

811

uint32_t offw = SMC_KEY("offw");

sys/arch/arm64/dev/aplsmc.c

812

uint32_t off1 = SMC_KEY("off1");

sys/arch/arm64/dev/aplspi.c

195

uint32_t

sys/arch/arm64/dev/aplspi.c

196

aplspi_clkdiv(struct aplspi_softc *sc, uint32_t freq)

sys/arch/arm64/dev/aplspi.c

198

uint32_t div = 0;

sys/arch/arm64/dev/aplspi.c

225

uint32_t avail, data, status;

sys/arch/arm64/dev/aplspi.c

290

uint32_t reg[1];

sys/arch/arm64/dev/aplspi.c

71

uint32_t sc_pfreq;

sys/arch/arm64/dev/aplspi.c

77

uint32_t *sc_csgpio;

sys/arch/arm64/dev/aplspi.c

86

uint32_t aplspi_clkdiv(struct aplspi_softc *, uint32_t);

sys/arch/arm64/dev/aplspmi.c

140

aplspmi_read_resp(struct aplspmi_softc *sc, uint32_t *resp)

sys/arch/arm64/dev/aplspmi.c

162

uint32_t resp;

sys/arch/arm64/dev/aplspmi.c

193

uint32_t data, resp;

sys/arch/arm64/dev/aplspmi.c

86

uint32_t reg[2];

sys/arch/arm64/dev/bcm2712_mip.c

139

uint32_t cells[3];

sys/arch/arm64/dev/bcm2712_mip.c

60

uint32_t sc_msi_ranges[5];

sys/arch/arm64/dev/bcm2712_mip.c

61

uint32_t sc_msi_offset;

sys/arch/arm64/dev/bcm2836_intr.c

102

uint32_t sc_imask[INTC_NBANK][NIPL];

sys/arch/arm64/dev/bcm2836_intr.c

157

uint32_t phandle, reg[2];

sys/arch/arm64/dev/bcm2836_intr.c

397

uint32_t pending;

sys/arch/arm64/dev/bcm2836_intr.c

636

uint32_t mbox_val;

sys/arch/arm64/dev/efi_machdep.c

43

extern uint32_t mmap_size;

sys/arch/arm64/dev/efi_machdep.c

44

extern uint32_t mmap_desc_size;

sys/arch/arm64/dev/efi_machdep.c

45

extern uint32_t mmap_desc_ver;

sys/arch/arm64/dev/mainbus.c

144

if (sc->sc_rangeslen > 0 && !(sc->sc_rangeslen % sizeof(uint32_t))) {

sys/arch/arm64/dev/mainbus.c

208

uint32_t *cell, *reg;

sys/arch/arm64/dev/mainbus.c

229

line = (sc->sc_acells + sc->sc_scells) * sizeof(uint32_t);

sys/arch/arm64/dev/mainbus.c

259

if (len > 0 && (len % sizeof(uint32_t)) == 0) {

sys/arch/arm64/dev/mainbus.c

261

fa.fa_nintr = len / sizeof(uint32_t);

sys/arch/arm64/dev/mainbus.c

293

free(fa.fa_intr, M_DEVBUF, fa.fa_nintr * sizeof(uint32_t));

sys/arch/arm64/dev/pci_machdep.c

119

int vec, bus_addr_t addr, uint32_t data)

sys/arch/arm64/dev/pci_machdep.c

123

uint32_t ctrl;

sys/arch/arm64/dev/pci_machdep.c

55

bus_addr_t addr, uint32_t data)

sys/arch/arm64/dev/rpiclock.c

174

uint32_t sc_xosc_freq;

sys/arch/arm64/dev/rpiclock.c

190

uint32_t rpiclock_get_frequency(void *, uint32_t *);

sys/arch/arm64/dev/rpiclock.c

191

int rpiclock_set_frequency(void *, uint32_t *, uint32_t);

sys/arch/arm64/dev/rpiclock.c

192

void rpiclock_enable(void *, uint32_t *, int);

sys/arch/arm64/dev/rpiclock.c

239

rpiclock_lookup(uint32_t idx)

sys/arch/arm64/dev/rpiclock.c

253

uint32_t

sys/arch/arm64/dev/rpiclock.c

268

uint32_t freq)

sys/arch/arm64/dev/rpiclock.c

270

uint32_t parent_freq = sc->sc_xosc_freq;

sys/arch/arm64/dev/rpiclock.c

271

uint32_t fbdiv_int, fbdiv_frac;

sys/arch/arm64/dev/rpiclock.c

310

uint32_t

sys/arch/arm64/dev/rpiclock.c

314

uint32_t prim, div1, div2;

sys/arch/arm64/dev/rpiclock.c

327

uint32_t freq)

sys/arch/arm64/dev/rpiclock.c

330

uint32_t best_div1, best_div2, best_freq;

sys/arch/arm64/dev/rpiclock.c

331

uint32_t f, div1, div2;

sys/arch/arm64/dev/rpiclock.c

332

uint32_t prim;

sys/arch/arm64/dev/rpiclock.c

367

uint32_t

sys/arch/arm64/dev/rpiclock.c

371

uint32_t sec, div;

sys/arch/arm64/dev/rpiclock.c

383

uint32_t freq)

sys/arch/arm64/dev/rpiclock.c

386

uint32_t sec, div;

sys/arch/arm64/dev/rpiclock.c

409

uint32_t

sys/arch/arm64/dev/rpiclock.c

411

uint32_t mux, uint32_t freq)

sys/arch/arm64/dev/rpiclock.c

413

uint32_t parent_freq, div;

sys/arch/arm64/dev/rpiclock.c

414

uint32_t idx = clk->parents[mux];

sys/arch/arm64/dev/rpiclock.c

423

uint32_t

sys/arch/arm64/dev/rpiclock.c

424

rpiclock_get_frequency(void *cookie, uint32_t *cells)

sys/arch/arm64/dev/rpiclock.c

428

uint32_t idx = cells[0];

sys/arch/arm64/dev/rpiclock.c

429

uint32_t ctrl, sel, div;

sys/arch/arm64/dev/rpiclock.c

430

uint32_t parent, freq;

sys/arch/arm64/dev/rpiclock.c

480

rpiclock_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/arch/arm64/dev/rpiclock.c

484

uint32_t idx = cells[0];

sys/arch/arm64/dev/rpiclock.c

485

uint32_t parent, parent_freq;

sys/arch/arm64/dev/rpiclock.c

486

uint32_t best_freq, best_mux, f;

sys/arch/arm64/dev/rpiclock.c

487

uint32_t ctrl, div, sel;

sys/arch/arm64/dev/rpiclock.c

569

rpiclock_enable(void *cookie, uint32_t *cells, int on)

sys/arch/arm64/dev/rpiclock.c

573

uint32_t idx = cells[0];

sys/arch/arm64/dev/rpigpio.c

129

const struct rpigpio_bank *rpigpio_get_bank(struct rpigpio_softc *, uint32_t);

sys/arch/arm64/dev/rpigpio.c

130

int rpigpio_pinctrl(uint32_t, void *);

sys/arch/arm64/dev/rpigpio.c

132

const char *, uint32_t);

sys/arch/arm64/dev/rpigpio.c

133

void rpigpio_config_pin(void *, uint32_t *, int);

sys/arch/arm64/dev/rpigpio.c

134

int rpigpio_get_pin(void *, uint32_t *);

sys/arch/arm64/dev/rpigpio.c

135

void rpigpio_set_pin(void *, uint32_t *, int);

sys/arch/arm64/dev/rpigpio.c

201

uint32_t start;

sys/arch/arm64/dev/rpigpio.c

202

uint32_t num;

sys/arch/arm64/dev/rpigpio.c

203

uint32_t gpio;

sys/arch/arm64/dev/rpigpio.c

204

uint32_t rio;

sys/arch/arm64/dev/rpigpio.c

205

uint32_t pads;

sys/arch/arm64/dev/rpigpio.c

215

rpigpio_get_bank(struct rpigpio_softc *sc, uint32_t pin)

sys/arch/arm64/dev/rpigpio.c

232

rpigpio_pinctrl(uint32_t phandle, void *cookie)

sys/arch/arm64/dev/rpigpio.c

239

uint32_t bias;

sys/arch/arm64/dev/rpigpio.c

281

const char *function, uint32_t bias)

sys/arch/arm64/dev/rpigpio.c

284

uint32_t val;

sys/arch/arm64/dev/rpigpio.c

345

rpigpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/arm64/dev/rpigpio.c

349

uint32_t pin = cells[0];

sys/arch/arm64/dev/rpigpio.c

350

uint32_t val;

sys/arch/arm64/dev/rpigpio.c

385

rpigpio_get_pin(void *cookie, uint32_t *cells)

sys/arch/arm64/dev/rpigpio.c

389

uint32_t pin = cells[0];

sys/arch/arm64/dev/rpigpio.c

390

uint32_t flags = cells[1];

sys/arch/arm64/dev/rpigpio.c

391

uint32_t reg;

sys/arch/arm64/dev/rpigpio.c

408

rpigpio_set_pin(void *cookie, uint32_t *cells, int val)

sys/arch/arm64/dev/rpigpio.c

412

uint32_t pin = cells[0];

sys/arch/arm64/dev/rpigpio.c

413

uint32_t flags = cells[1];

sys/arch/arm64/dev/rpigpio.c

414

uint32_t reg;

sys/arch/arm64/dev/rpipwm.c

117

static inline uint32_t

sys/arch/arm64/dev/rpipwm.c

118

cycles_to_ns(uint64_t clk_freq, uint32_t cycles)

sys/arch/arm64/dev/rpipwm.c

123

static inline uint32_t

sys/arch/arm64/dev/rpipwm.c

124

ns_to_cycles(uint64_t clk_freq, uint32_t ns)

sys/arch/arm64/dev/rpipwm.c

130

rpipwm_get_state(void *cookie, uint32_t *cells, struct pwm_state *ps)

sys/arch/arm64/dev/rpipwm.c

133

uint32_t chan = cells[0];

sys/arch/arm64/dev/rpipwm.c

134

uint32_t ctrl, range, duty;

sys/arch/arm64/dev/rpipwm.c

158

rpipwm_set_state(void *cookie, uint32_t *cells, struct pwm_state *ps)

sys/arch/arm64/dev/rpipwm.c

161

uint32_t chan = cells[0];

sys/arch/arm64/dev/rpipwm.c

162

uint32_t range, duty;

sys/arch/arm64/dev/rpipwm.c

57

uint32_t sc_clkin;

sys/arch/arm64/dev/rpipwm.c

58

uint32_t sc_initialized;

sys/arch/arm64/dev/rpipwm.c

73

int rpipwm_get_state(void *, uint32_t *, struct pwm_state *);

sys/arch/arm64/dev/rpipwm.c

74

int rpipwm_set_state(void *, uint32_t *, struct pwm_state *);

sys/arch/arm64/dev/rpirtc.c

120

uint32_t result;

sys/arch/arm64/dev/rpirtc.c

80

uint32_t result;

sys/arch/arm64/dev/rpone.c

181

uint32_t vec = cells[0];

sys/arch/arm64/dev/rpone.c

182

uint32_t type = cells[1];

sys/arch/arm64/dev/rtkit.c

145

rtkit_send(struct rtkit_state *state, uint32_t endpoint,

sys/arch/arm64/dev/rtkit.c

219

rtkit_start(struct rtkit_state *state, uint32_t endpoint)

sys/arch/arm64/dev/rtkit.c

233

uint32_t endpoint;

sys/arch/arm64/dev/rtkit.c

313

uint32_t fourcc;

sys/arch/arm64/dev/rtkit.c

314

uint32_t version;

sys/arch/arm64/dev/rtkit.c

315

uint32_t size;

sys/arch/arm64/dev/rtkit.c

316

uint32_t flags;

sys/arch/arm64/dev/rtkit.c

323

uint32_t timestamp;

sys/arch/arm64/dev/rtkit.c

350

uint32_t idx;

sys/arch/arm64/dev/rtkit.c

355

idx = lemtoh32((uint32_t *)buf);

sys/arch/arm64/dev/rtkit.c

356

buf += sizeof(uint32_t);

sys/arch/arm64/dev/rtkit.c

444

uint32_t fourcc, size;

sys/arch/arm64/dev/rtkit.c

446

fourcc = lemtoh32((uint32_t *)(buf + off));

sys/arch/arm64/dev/rtkit.c

447

size = lemtoh32((uint32_t *)(buf + off + 12));

sys/arch/arm64/dev/rtkit.c

762

uint32_t endpoint;

sys/arch/arm64/dev/rtkit.c

980

rtkit_start_endpoint(struct rtkit_state *state, uint32_t endpoint,

sys/arch/arm64/dev/rtkit.c

995

rtkit_send_endpoint(struct rtkit_state *state, uint32_t endpoint,

sys/arch/arm64/dev/rtkit.h

28

int rtkit_start_endpoint(struct rtkit_state *, uint32_t,

sys/arch/arm64/dev/rtkit.h

30

int rtkit_send_endpoint(struct rtkit_state *, uint32_t, uint64_t);

sys/arch/arm64/dev/rtkit.h

32

int aplrtk_start(uint32_t);

sys/arch/arm64/dev/rtkit.h

33

int aplsart_map(uint32_t, bus_addr_t, bus_size_t);

sys/arch/arm64/dev/rtkit.h

34

int aplsart_unmap(uint32_t, bus_addr_t, bus_size_t);

sys/arch/arm64/dev/simplebus.c

104

(sc->sc_rangeslen % sizeof(uint32_t)) == 0) {

sys/arch/arm64/dev/simplebus.c

117

(sc->sc_dmarangeslen % sizeof(uint32_t)) == 0) {

sys/arch/arm64/dev/simplebus.c

132

sc->sc_dmarangeslen = 3 * sizeof(uint32_t);

sys/arch/arm64/dev/simplebus.c

188

uint32_t *cell, *reg;

sys/arch/arm64/dev/simplebus.c

214

line = (sc->sc_acells + sc->sc_scells) * sizeof(uint32_t);

sys/arch/arm64/dev/simplebus.c

244

if (len > 0 && (len % sizeof(uint32_t)) == 0) {

sys/arch/arm64/dev/simplebus.c

246

fa.fa_nintr = len / sizeof(uint32_t);

sys/arch/arm64/dev/simplebus.c

274

free(fa.fa_intr, M_DEVBUF, fa.fa_nintr * sizeof(uint32_t));

sys/arch/arm64/dev/simplebus.c

286

uint32_t *range;

sys/arch/arm64/dev/simplebus.c

299

rlen = sc->sc_rangeslen / sizeof(uint32_t);

sys/arch/arm64/dev/simplebus.c

340

uint32_t *range;

sys/arch/arm64/dev/simplebus.c

353

rlen = sc->sc_rangeslen / sizeof(uint32_t);

sys/arch/arm64/dev/simplebus.c

413

rlen = sc->sc_dmarangeslen / sizeof(uint32_t);

sys/arch/arm64/dev/simplebus.c

419

uint32_t *range;

sys/arch/arm64/dev/simplebus.c

474

rlen = sc->sc_dmarangeslen / sizeof(uint32_t);

sys/arch/arm64/dev/simplebus.c

480

uint32_t *range;

sys/arch/arm64/dev/smmu.c

118

uint32_t smmu_v3_read_4(struct smmu_softc *, bus_size_t);

sys/arch/arm64/dev/smmu.c

119

void smmu_v3_write_4(struct smmu_softc *, bus_size_t, uint32_t);

sys/arch/arm64/dev/smmu.c

123

uint32_t);

sys/arch/arm64/dev/smmu.c

156

uint32_t reg;

sys/arch/arm64/dev/smmu.c

1587

uint32_t reg;

sys/arch/arm64/dev/smmu.c

1820

uint32_t cons, prod;

sys/arch/arm64/dev/smmu.c

1874

uint32_t gerror, gerrorn;

sys/arch/arm64/dev/smmu.c

1883

uint32_t cons = smmu_v3_read_4(sc, SMMU_V3_CMDQ_CONS);

sys/arch/arm64/dev/smmu.c

1900

uint32_t cons, prod;

sys/arch/arm64/dev/smmu.c

1951

uint32_t

sys/arch/arm64/dev/smmu.c

1958

smmu_v3_write_4(struct smmu_softc *sc, bus_size_t off, uint32_t val)

sys/arch/arm64/dev/smmu.c

1977

uint32_t val)

sys/arch/arm64/dev/smmu.c

2002

uint32_t iovabits;

sys/arch/arm64/dev/smmu.c

2134

uint32_t prod;

sys/arch/arm64/dev/smmu.c

2192

uint32_t prod;

sys/arch/arm64/dev/smmu.c

2234

uint32_t prod;

sys/arch/arm64/dev/smmu.c

2277

uint32_t prod;

sys/arch/arm64/dev/smmu.c

2319

uint32_t prod;

sys/arch/arm64/dev/smmu.c

2361

uint32_t prod;

sys/arch/arm64/dev/smmu.c

2406

uint32_t prod;

sys/arch/arm64/dev/smmu.c

391

uint32_t reg;

sys/arch/arm64/dev/smmu.c

413

uint32_t reg;

sys/arch/arm64/dev/smmu.c

463

uint32_t

sys/arch/arm64/dev/smmu.c

466

uint32_t base = 0 * sc->sc_pagesize;

sys/arch/arm64/dev/smmu.c

472

smmu_gr0_write_4(struct smmu_softc *sc, bus_size_t off, uint32_t val)

sys/arch/arm64/dev/smmu.c

474

uint32_t base = 0 * sc->sc_pagesize;

sys/arch/arm64/dev/smmu.c

479

uint32_t

sys/arch/arm64/dev/smmu.c

482

uint32_t base = 1 * sc->sc_pagesize;

sys/arch/arm64/dev/smmu.c

488

smmu_gr1_write_4(struct smmu_softc *sc, bus_size_t off, uint32_t val)

sys/arch/arm64/dev/smmu.c

490

uint32_t base = 1 * sc->sc_pagesize;

sys/arch/arm64/dev/smmu.c

495

uint32_t

sys/arch/arm64/dev/smmu.c

498

uint32_t base;

sys/arch/arm64/dev/smmu.c

507

smmu_cb_write_4(struct smmu_softc *sc, int idx, bus_size_t off, uint32_t val)

sys/arch/arm64/dev/smmu.c

509

uint32_t base;

sys/arch/arm64/dev/smmu.c

521

uint32_t base;

sys/arch/arm64/dev/smmu.c

539

uint32_t base;

sys/arch/arm64/dev/smmu.c

556

smmu_device_map(void *cookie, uint32_t sid, bus_dma_tag_t dmat)

sys/arch/arm64/dev/smmu.c

583

smmu_domain_lookup(struct smmu_softc *sc, uint32_t sid)

sys/arch/arm64/dev/smmu.c

596

smmu_domain_create(struct smmu_softc *sc, uint32_t sid)

sys/arch/arm64/dev/smmu.c

628

uint32_t iovabits, reg;

sys/arch/arm64/dev/smmu.c

66

uint32_t smmu_gr0_read_4(struct smmu_softc *, bus_size_t);

sys/arch/arm64/dev/smmu.c

67

void smmu_gr0_write_4(struct smmu_softc *, bus_size_t, uint32_t);

sys/arch/arm64/dev/smmu.c

68

uint32_t smmu_gr1_read_4(struct smmu_softc *, bus_size_t);

sys/arch/arm64/dev/smmu.c

69

void smmu_gr1_write_4(struct smmu_softc *, bus_size_t, uint32_t);

sys/arch/arm64/dev/smmu.c

70

uint32_t smmu_cb_read_4(struct smmu_softc *, int, bus_size_t);

sys/arch/arm64/dev/smmu.c

71

void smmu_cb_write_4(struct smmu_softc *, int, bus_size_t, uint32_t);

sys/arch/arm64/dev/smmu.c

80

struct smmu_domain *smmu_domain_lookup(struct smmu_softc *, uint32_t);

sys/arch/arm64/dev/smmu.c

81

struct smmu_domain *smmu_domain_create(struct smmu_softc *, uint32_t);

sys/arch/arm64/dev/smmu.c

845

smmu_reserve_region(void *cookie, uint32_t sid, bus_addr_t addr,

sys/arch/arm64/dev/smmu_fdt.c

119

uint32_t ngirq;

sys/arch/arm64/dev/smmu_fdt.c

218

smmu_fdt_map(void *cookie, uint32_t *cells, bus_dma_tag_t dmat)

sys/arch/arm64/dev/smmu_fdt.c

227

smmu_fdt_reserve(void *cookie, uint32_t *cells, bus_addr_t addr,

sys/arch/arm64/dev/smmu_fdt.c

60

bus_dma_tag_t smmu_fdt_map(void *, uint32_t *, bus_dma_tag_t);

sys/arch/arm64/dev/smmu_fdt.c

61

void smmu_fdt_reserve(void *, uint32_t *, bus_addr_t, bus_size_t);

sys/arch/arm64/dev/smmuvar.h

139

bus_dma_tag_t smmu_device_map(void *, uint32_t, bus_dma_tag_t);

sys/arch/arm64/dev/smmuvar.h

140

void smmu_reserve_region(void *, uint32_t, bus_addr_t, bus_size_t);

sys/arch/arm64/dev/smmuvar.h

28

uint32_t sd_sid;

sys/arch/arm64/dev/smmuvar.h

72

uint32_t sq_prod;

sys/arch/arm64/dev/smmuvar.h

73

uint32_t sq_cons;

sys/arch/arm64/include/bus.h

513

uint32_t generic_space_read_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);

sys/arch/arm64/include/bus.h

522

uint32_t);

sys/arch/arm64/include/cpu.h

144

uint32_t ci_cpl;

sys/arch/arm64/include/cpu.h

145

uint32_t ci_ipending;

sys/arch/arm64/include/cpu.h

146

uint32_t ci_idepth;

sys/arch/arm64/include/cpu.h

158

uint32_t ci_psci_idle_latency;

sys/arch/arm64/include/cpu.h

159

uint32_t ci_psci_idle_param;

sys/arch/arm64/include/cpu.h

160

uint32_t ci_psci_suspend_param;

sys/arch/arm64/include/cpu.h

165

uint32_t ci_cpu_supply;

sys/arch/arm64/include/cpu.h

303

restore_daif(uint32_t daif)

sys/arch/arm64/include/cpu.h

320

static __inline uint32_t

sys/arch/arm64/include/cpu.h

323

uint32_t daif;

sys/arch/arm64/include/fdt.h

31

uint32_t *fa_intr;

sys/arch/arm64/include/ieee.h

96

(a)[0] = (uint32_t)(p)->ext_fracl; \

sys/arch/arm64/include/ieee.h

97

(a)[1] = (uint32_t)(p)->ext_fraclm; \

sys/arch/arm64/include/ieee.h

98

(a)[2] = (uint32_t)(p)->ext_frachm; \

sys/arch/arm64/include/ieee.h

99

(a)[3] = (uint32_t)(p)->ext_frach; \

sys/arch/arm64/include/intr.h

142

extern uint32_t arm_smask[NIPL];

sys/arch/arm64/include/intr.h

166

uint32_t ic_phandle;

sys/arch/arm64/include/intr.h

167

uint32_t ic_cells;

sys/arch/arm64/include/intr.h

168

uint32_t ic_gic_its_id;

sys/arch/arm64/include/pci_machdep.h

132

void pci_msi_enable(pci_chipset_tag_t, pcitag_t, bus_addr_t, uint32_t);

sys/arch/arm64/include/pci_machdep.h

134

int, bus_addr_t, uint32_t);

sys/arch/arm64/include/reg.h

32

uint32_t fp_sr;

sys/arch/arm64/include/reg.h

33

uint32_t fp_cr;

sys/arch/arm64/include/smbiosvar.h

147

uint32_t charext;

sys/arch/arm64/include/smbiosvar.h

226

uint32_t cpu_id_eax;

sys/arch/arm64/include/smbiosvar.h

227

uint32_t cpu_id_edx;

sys/arch/arm64/include/smbiosvar.h

52

uint32_t sig; /* "_SM_" */

sys/arch/arm64/include/smbiosvar.h

63

uint32_t addr; /* Structure table address */

sys/arch/arm64/include/smbiosvar.h

77

uint32_t size; /* Structure table maximum size */

sys/arch/arm64/include/smbiosvar.h

90

uint32_t cookie;

sys/arch/arm64/include/vmmvar.h

32

uint32_t nr_cpus; /* [I] */

sys/arch/arm64/include/vmmvar.h

40

uint32_t vie_errorcode; /* Optional error code. */

sys/arch/arm64/include/vmmvar.h

66

uint32_t vip_vm_id;

sys/arch/arm64/include/vmmvar.h

67

uint32_t vip_vcpu_id;

sys/arch/arm64/include/vmmvar.h

79

uint32_t vrwp_vm_id;

sys/arch/arm64/include/vmmvar.h

80

uint32_t vrwp_vcpu_id;

sys/arch/arm64/stand/efiboot/efiacpi.c

113

uint32_t firmware_ctl; /* phys addr FACS */

sys/arch/arm64/stand/efiboot/efiacpi.c

114

uint32_t dsdt; /* phys addr DSDT */

sys/arch/arm64/stand/efiboot/efiacpi.c

128

uint32_t smi_cmd; /* SMI command port */

sys/arch/arm64/stand/efiboot/efiacpi.c

133

uint32_t pm1a_evt_blk; /* power management 1a */

sys/arch/arm64/stand/efiboot/efiacpi.c

134

uint32_t pm1b_evt_blk; /* power management 1b */

sys/arch/arm64/stand/efiboot/efiacpi.c

135

uint32_t pm1a_cnt_blk; /* pm control 1a */

sys/arch/arm64/stand/efiboot/efiacpi.c

136

uint32_t pm1b_cnt_blk; /* pm control 1b */

sys/arch/arm64/stand/efiboot/efiacpi.c

137

uint32_t pm2_cnt_blk; /* pm control 2 */

sys/arch/arm64/stand/efiboot/efiacpi.c

138

uint32_t pm_tmr_blk;

sys/arch/arm64/stand/efiboot/efiacpi.c

139

uint32_t gpe0_blk;

sys/arch/arm64/stand/efiboot/efiacpi.c

140

uint32_t gpe1_blk;

sys/arch/arm64/stand/efiboot/efiacpi.c

163

uint32_t flags;

sys/arch/arm64/stand/efiboot/efiacpi.c

216

uint32_t reserved;

sys/arch/arm64/stand/efiboot/efiacpi.c

217

uint32_t sec_el1_interrupt;

sys/arch/arm64/stand/efiboot/efiacpi.c

218

uint32_t sec_el1_flags;

sys/arch/arm64/stand/efiboot/efiacpi.c

222

uint32_t nonsec_el1_interrupt;

sys/arch/arm64/stand/efiboot/efiacpi.c

223

uint32_t nonsec_el1_flags;

sys/arch/arm64/stand/efiboot/efiacpi.c

224

uint32_t virt_interrupt;

sys/arch/arm64/stand/efiboot/efiacpi.c

225

uint32_t virt_flags;

sys/arch/arm64/stand/efiboot/efiacpi.c

226

uint32_t nonsec_el2_interrupt;

sys/arch/arm64/stand/efiboot/efiacpi.c

227

uint32_t nonsec_el2_flags;

sys/arch/arm64/stand/efiboot/efiacpi.c

229

uint32_t platform_timer_count;

sys/arch/arm64/stand/efiboot/efiacpi.c

230

uint32_t platform_timer_offset;

sys/arch/arm64/stand/efiboot/efiacpi.c

236

uint32_t local_apic_address;

sys/arch/arm64/stand/efiboot/efiacpi.c

237

uint32_t flags;

sys/arch/arm64/stand/efiboot/efiacpi.c

246

uint32_t gic_id;

sys/arch/arm64/stand/efiboot/efiacpi.c

247

uint32_t acpi_proc_uid;

sys/arch/arm64/stand/efiboot/efiacpi.c

248

uint32_t flags;

sys/arch/arm64/stand/efiboot/efiacpi.c

250

uint32_t parking_protocol_version;

sys/arch/arm64/stand/efiboot/efiacpi.c

251

uint32_t performance_interrupt;

sys/arch/arm64/stand/efiboot/efiacpi.c

256

uint32_t maintenance_interrupt;

sys/arch/arm64/stand/efiboot/efiacpi.c

268

uint32_t gic_id;

sys/arch/arm64/stand/efiboot/efiacpi.c

270

uint32_t interrupt_base;

sys/arch/arm64/stand/efiboot/efiacpi.c

280

uint32_t msi_frame_id;

sys/arch/arm64/stand/efiboot/efiacpi.c

282

uint32_t flags;

sys/arch/arm64/stand/efiboot/efiacpi.c

294

uint32_t discovery_length;

sys/arch/arm64/stand/efiboot/efiacpi.c

302

uint32_t gic_its_id;

sys/arch/arm64/stand/efiboot/efiacpi.c

304

uint32_t reserved2;

sys/arch/arm64/stand/efiboot/efiacpi.c

327

uint32_t gsiv;

sys/arch/arm64/stand/efiboot/efiacpi.c

339

uint32_t pci_flags;

sys/arch/arm64/stand/efiboot/efiacpi.c

341

uint32_t reserved3;

sys/arch/arm64/stand/efiboot/efiacpi.c

347

uint32_t info_offset;

sys/arch/arm64/stand/efiboot/efiacpi.c

348

uint32_t info_count;

sys/arch/arm64/stand/efiboot/efiacpi.c

402

const uint32_t map[] = { 0x4, 0x1, 0x8, 0x2 };

sys/arch/arm64/stand/efiboot/efiacpi.c

403

const uint32_t mask = ACPI_GTDT_TIMER_TRIGGER_EDGE |

sys/arch/arm64/stand/efiboot/efiacpi.c

405

uint32_t interrupts[12];

sys/arch/arm64/stand/efiboot/efiacpi.c

475

uint32_t size;

sys/arch/arm64/stand/efiboot/efiacpi.c

48

uint32_t rsdt; /* physical */

sys/arch/arm64/stand/efiboot/efiacpi.c

504

static uint32_t phandle = 2;

sys/arch/arm64/stand/efiboot/efiacpi.c

520

uint32_t spi_base = htobe32(msi->spi_base);

sys/arch/arm64/stand/efiboot/efiacpi.c

521

uint32_t spi_count = htobe32(msi->spi_count);

sys/arch/arm64/stand/efiboot/efiacpi.c

543

static uint32_t phandle = 2;

sys/arch/arm64/stand/efiboot/efiacpi.c

546

uint32_t its_id;

sys/arch/arm64/stand/efiboot/efiacpi.c

58

uint32_t rsdp_length; /* length of rsdp */

sys/arch/arm64/stand/efiboot/efiacpi.c

656

uint32_t address_size)

sys/arch/arm64/stand/efiboot/efiacpi.c

67

uint32_t length;

sys/arch/arm64/stand/efiboot/efiacpi.c

736

uint32_t address_size;

sys/arch/arm64/stand/efiboot/efiacpi.c

746

address_size = *(uint32_t *)

sys/arch/arm64/stand/efiboot/efiacpi.c

77

uint32_t oemrevision;

sys/arch/arm64/stand/efiboot/efiacpi.c

81

uint32_t aslcompilerrevision;

sys/arch/arm64/stand/efiboot/efiboot.c

399

uint32_t acells, scells;

sys/arch/arm64/stand/efiboot/efiboot.c

401

uint32_t reg[4];

sys/arch/arm64/stand/efiboot/efiboot.c

402

uint32_t width, height, stride, pxsize;

sys/arch/arm64/stand/efiboot/efiboot.c

557

uint32_t *propint;

sys/arch/arm64/stand/efiboot/efiboot.c

559

uint32_t pacells, pscells;

sys/arch/arm64/stand/efiboot/efiboot.c

560

uint32_t acells, scells;

sys/arch/arm64/stand/efiboot/efiboot.c

581

propint = (uint32_t *)prop;

sys/arch/arm64/stand/efiboot/efiboot.c

582

if (len == (acells + pacells + scells) * sizeof(uint32_t)) {

sys/arch/arm64/stand/efiboot/efiboot.c

631

uint32_t boothowto = htobe32(howto);

sys/arch/arm64/stand/efiboot/efiboot.c

717

uint32_t uefi_mmap_size = htobe32(mmap_ndesc * mmap_descsiz);

sys/arch/arm64/stand/efiboot/efiboot.c

718

uint32_t uefi_mmap_desc_size = htobe32(mmap_descsiz);

sys/arch/arm64/stand/efiboot/efiboot.c

719

uint32_t uefi_mmap_desc_ver = htobe32(mmap_version);

sys/arch/arm64/stand/efiboot/efidev.c

270

uint32_t orig_csum, new_csum;

sys/arch/arm64/stand/efiboot/efidev.c

271

uint32_t ghsize, ghpartsize, ghpartnum, ghpartspersec;

sys/arch/arm64/stand/efiboot/efidev.c

272

uint32_t gpsectors;

sys/arch/arm64/stand/efiboot/fdt.c

132

fdt_get_str(uint32_t num)

sys/arch/arm64/stand/efiboot/fdt.c

142

size_t len = roundup(strlen(name) + 1, sizeof(uint32_t));

sys/arch/arm64/stand/efiboot/fdt.c

160

skip_nops(uint32_t *ptr)

sys/arch/arm64/stand/efiboot/fdt.c

169

skip_property(uint32_t *ptr)

sys/arch/arm64/stand/efiboot/fdt.c

171

uint32_t size;

sys/arch/arm64/stand/efiboot/fdt.c

175

ptr += 3 + roundup(size, sizeof(uint32_t)) / sizeof(uint32_t);

sys/arch/arm64/stand/efiboot/fdt.c

181

skip_props(uint32_t *ptr)

sys/arch/arm64/stand/efiboot/fdt.c

190

skip_node_name(uint32_t *ptr)

sys/arch/arm64/stand/efiboot/fdt.c

194

sizeof(uint32_t)) / sizeof(uint32_t);

sys/arch/arm64/stand/efiboot/fdt.c

206

uint32_t *ptr;

sys/arch/arm64/stand/efiboot/fdt.c

207

uint32_t nameid;

sys/arch/arm64/stand/efiboot/fdt.c

213

ptr = (uint32_t *)node;

sys/arch/arm64/stand/efiboot/fdt.c

236

uint32_t *ptr, *next;

sys/arch/arm64/stand/efiboot/fdt.c

237

uint32_t nameid;

sys/arch/arm64/stand/efiboot/fdt.c

238

uint32_t curlen;

sys/arch/arm64/stand/efiboot/fdt.c

245

ptr = (uint32_t *)node;

sys/arch/arm64/stand/efiboot/fdt.c

258

delta = roundup(len, sizeof(uint32_t)) -

sys/arch/arm64/stand/efiboot/fdt.c

259

roundup(curlen, sizeof(uint32_t));

sys/arch/arm64/stand/efiboot/fdt.c

28

char *fdt_get_str(uint32_t);

sys/arch/arm64/stand/efiboot/fdt.c

286

uint32_t *ptr = (uint32_t *)node;

sys/arch/arm64/stand/efiboot/fdt.c

29

void *skip_property(uint32_t *);

sys/arch/arm64/stand/efiboot/fdt.c

291

if (end + 3 * sizeof(uint32_t) > tree.end)

sys/arch/arm64/stand/efiboot/fdt.c

297

tree.struct_size += 3 * sizeof(uint32_t);

sys/arch/arm64/stand/efiboot/fdt.c

298

tree.strings += 3 * sizeof(uint32_t);

sys/arch/arm64/stand/efiboot/fdt.c

30

void *skip_props(uint32_t *);

sys/arch/arm64/stand/efiboot/fdt.c

31

void *skip_node_name(uint32_t *);

sys/arch/arm64/stand/efiboot/fdt.c

310

size_t len = roundup(strlen(name) + 1, sizeof(uint32_t)) + 8;

sys/arch/arm64/stand/efiboot/fdt.c

312

uint32_t *ptr = (uint32_t *)node;

sys/arch/arm64/stand/efiboot/fdt.c

33

void *skip_nops(uint32_t *);

sys/arch/arm64/stand/efiboot/fdt.c

338

ptr += (len - 8) / sizeof(uint32_t);

sys/arch/arm64/stand/efiboot/fdt.c

351

uint32_t *ptr = node;

sys/arch/arm64/stand/efiboot/fdt.c

373

uint32_t *ptr;

sys/arch/arm64/stand/efiboot/fdt.c

381

ptr = skip_nops((uint32_t *)tree.tree);

sys/arch/arm64/stand/efiboot/fdt.c

43

uint32_t *ptr, *tok;

sys/arch/arm64/stand/efiboot/fdt.c

443

uint32_t *ptr;

sys/arch/arm64/stand/efiboot/fdt.c

46

ptr = (uint32_t *)fdt;

sys/arch/arm64/stand/efiboot/fdt.c

467

uint32_t *ptr;

sys/arch/arm64/stand/efiboot/fdt.c

573

uint32_t *ptr;

sys/arch/arm64/stand/efiboot/fdt.c

576

uint32_t nameid, size;

sys/arch/arm64/stand/efiboot/fdt.c

578

ptr = (uint32_t *)node;

sys/arch/arm64/stand/efiboot/fdt.c

608

if ((cnt % sizeof(uint32_t)) == 0)

sys/arch/arm64/stand/efiboot/fdt.c

613

ptr += roundup(size, sizeof(uint32_t)) / sizeof(uint32_t);

sys/arch/arm64/stand/efiboot/fdt.c

622

uint32_t *ptr;

sys/arch/arm64/stand/efiboot/fdt.c

625

ptr = (uint32_t *)node;

sys/arch/arm64/stand/efiboot/fdt.h

20

uint32_t fh_magic;

sys/arch/arm64/stand/efiboot/fdt.h

21

uint32_t fh_size;

sys/arch/arm64/stand/efiboot/fdt.h

22

uint32_t fh_struct_off;

sys/arch/arm64/stand/efiboot/fdt.h

23

uint32_t fh_strings_off;

sys/arch/arm64/stand/efiboot/fdt.h

24

uint32_t fh_reserve_off;

sys/arch/arm64/stand/efiboot/fdt.h

25

uint32_t fh_version;

sys/arch/arm64/stand/efiboot/fdt.h

26

uint32_t fh_comp_ver; /* last compatible version */

sys/arch/arm64/stand/efiboot/fdt.h

27

uint32_t fh_boot_cpu_id; /* fh_version >=2 */

sys/arch/arm64/stand/efiboot/fdt.h

28

uint32_t fh_strings_size; /* fh_version >=3 */

sys/arch/arm64/stand/efiboot/fdt.h

29

uint32_t fh_struct_size; /* fh_version >=17 */

sys/arch/arm64/stand/efiboot/softraid_arm64.c

424

uint32_t orig_csum, new_csum;

sys/arch/arm64/stand/efiboot/softraid_arm64.c

425

uint32_t ghsize, ghpartsize, ghpartnum, ghpartspersec;

sys/arch/arm64/stand/efiboot/softraid_arm64.c

426

uint32_t gpsectors;

sys/arch/armv7/armv7/armv7_machdep.c

344

uint32_t mmap_size;

sys/arch/armv7/armv7/armv7_machdep.c

345

uint32_t mmap_desc_size;

sys/arch/armv7/armv7/armv7_machdep.c

346

uint32_t mmap_desc_ver;

sys/arch/armv7/armv7/armv7_machdep.c

374

extern uint32_t esym; /* &_end if no symbols are loaded */

sys/arch/armv7/armv7/armv7_machdep.c

382

esym = (uint32_t)arg0;

sys/arch/armv7/armv7/armv7_machdep.c

427

boothowto = bemtoh32((uint32_t *)prop);

sys/arch/armv7/armv7/armv7_machdep.c

444

mmap_size = bemtoh32((uint32_t *)prop);

sys/arch/armv7/armv7/armv7_machdep.c

447

mmap_desc_size = bemtoh32((uint32_t *)prop);

sys/arch/armv7/armv7/armv7_machdep.c

450

mmap_desc_ver = bemtoh32((uint32_t *)prop);

sys/arch/armv7/armv7/armv7_machdep.h

34

uint32_t, uint32_t);

sys/arch/armv7/armv7/intr.c

104

uint32_t phandle;

sys/arch/armv7/armv7/intr.c

118

uint32_t

sys/arch/armv7/armv7/intr.c

122

uint32_t phandle = 0;

sys/arch/armv7/armv7/intr.c

123

uint32_t *cell;

sys/arch/armv7/armv7/intr.c

124

uint32_t *map;

sys/arch/armv7/armv7/intr.c

125

uint32_t mask, rid_base, rid;

sys/arch/armv7/armv7/intr.c

145

ncells = len / sizeof(uint32_t);

sys/arch/armv7/armv7/intr.c

200

uint32_t ip_phandle;

sys/arch/armv7/armv7/intr.c

201

uint32_t ip_cell[MAX_INTERRUPT_CELLS];

sys/arch/armv7/armv7/intr.c

32

uint32_t arm_intr_map_msi(int, uint64_t *);

sys/arch/armv7/armv7/intr.c

346

uint32_t *cell, *cells, phandle;

sys/arch/armv7/armv7/intr.c

355

if (len <= 0 || (len % sizeof(uint32_t) != 0))

sys/arch/armv7/armv7/intr.c

375

ncells = len / sizeof(uint32_t);

sys/arch/armv7/armv7/intr.c

436

uint32_t *cell;

sys/arch/armv7/armv7/intr.c

437

uint32_t map_mask[4], *map;

sys/arch/armv7/armv7/intr.c

456

ncells = len / sizeof(uint32_t);

sys/arch/armv7/armv7/intr.c

51

uint32_t arm_smask[NIPL];

sys/arch/armv7/armv7/intr.c

510

uint32_t phandle;

sys/arch/armv7/armv7/platform.c

76

uint32_t op, uint32_t val)

sys/arch/armv7/broadcom/bcm2836_intr.c

147

uint32_t phandle, reg[2];

sys/arch/armv7/broadcom/bcm2836_intr.c

380

uint32_t pending;

sys/arch/armv7/broadcom/bcm2836_intr.c

97

uint32_t sc_bcm_intc_imask[INTC_NBANK][NIPL];

sys/arch/armv7/exynos/ec_commands.h

1027

uint32_t time_us;

sys/arch/armv7/exynos/ec_commands.h

1078

uint32_t mask;

sys/arch/armv7/exynos/ec_commands.h

1082

uint32_t mask;

sys/arch/armv7/exynos/ec_commands.h

1249

uint32_t usb_dev_type;

sys/arch/armv7/exynos/ec_commands.h

1311

uint32_t limit; /* in mA */

sys/arch/armv7/exynos/ec_commands.h

1320

uint32_t limit; /* in mA */

sys/arch/armv7/exynos/ec_commands.h

292

uint32_t version;

sys/arch/armv7/exynos/ec_commands.h

302

uint32_t in_data; /* Pass anything here */

sys/arch/armv7/exynos/ec_commands.h

306

uint32_t out_data; /* Output will be in_data + 0x01020304 */

sys/arch/armv7/exynos/ec_commands.h

323

uint32_t current_image; /* One of ec_current_image */

sys/arch/armv7/exynos/ec_commands.h

330

uint32_t offset; /* Starting value for read buffer */

sys/arch/armv7/exynos/ec_commands.h

331

uint32_t size; /* Size to read in bytes */

sys/arch/armv7/exynos/ec_commands.h

335

uint32_t data[32];

sys/arch/armv7/exynos/ec_commands.h

389

uint32_t version_mask;

sys/arch/armv7/exynos/ec_commands.h

407

uint32_t flags; /* Mask of enum ec_comms_status */

sys/arch/armv7/exynos/ec_commands.h

419

uint32_t flash_size;

sys/arch/armv7/exynos/ec_commands.h

424

uint32_t write_block_size;

sys/arch/armv7/exynos/ec_commands.h

429

uint32_t erase_block_size;

sys/arch/armv7/exynos/ec_commands.h

434

uint32_t protect_block_size;

sys/arch/armv7/exynos/ec_commands.h

445

uint32_t offset; /* Byte offset to read */

sys/arch/armv7/exynos/ec_commands.h

446

uint32_t size; /* Size to read in bytes */

sys/arch/armv7/exynos/ec_commands.h

453

uint32_t offset; /* Byte offset to write */

sys/arch/armv7/exynos/ec_commands.h

454

uint32_t size; /* Size to write in bytes */

sys/arch/armv7/exynos/ec_commands.h

466

uint32_t offset; /* Byte offset to erase */

sys/arch/armv7/exynos/ec_commands.h

467

uint32_t size; /* Size to erase in bytes */

sys/arch/armv7/exynos/ec_commands.h

507

uint32_t mask; /* Bits in flags to apply */

sys/arch/armv7/exynos/ec_commands.h

508

uint32_t flags; /* New flags to apply */

sys/arch/armv7/exynos/ec_commands.h

513

uint32_t flags;

sys/arch/armv7/exynos/ec_commands.h

519

uint32_t valid_flags;

sys/arch/armv7/exynos/ec_commands.h

521

uint32_t writable_flags;

sys/arch/armv7/exynos/ec_commands.h

546

uint32_t region; /* enum ec_flash_region */

sys/arch/armv7/exynos/ec_commands.h

550

uint32_t offset;

sys/arch/armv7/exynos/ec_commands.h

551

uint32_t size;

sys/arch/armv7/exynos/ec_commands.h

565

uint32_t op;

sys/arch/armv7/exynos/ec_commands.h

580

uint32_t rpm;

sys/arch/armv7/exynos/ec_commands.h

587

uint32_t rpm;

sys/arch/armv7/exynos/ec_commands.h

609

uint32_t percent;

sys/arch/armv7/exynos/ec_commands.h

741

uint32_t offset; /* Offset in flash to hash */

sys/arch/armv7/exynos/ec_commands.h

742

uint32_t size; /* Number of bytes to hash */

sys/arch/armv7/exynos/ec_commands.h

751

uint32_t offset; /* Offset in flash which was hashed */

sys/arch/armv7/exynos/ec_commands.h

752

uint32_t size; /* Number of bytes hashed */

sys/arch/armv7/exynos/ec_commands.h

803

uint32_t pstore_size;

sys/arch/armv7/exynos/ec_commands.h

805

uint32_t access_size;

sys/arch/armv7/exynos/ec_commands.h

816

uint32_t offset; /* Byte offset to read */

sys/arch/armv7/exynos/ec_commands.h

817

uint32_t size; /* Size to read in bytes */

sys/arch/armv7/exynos/ec_commands.h

824

uint32_t offset; /* Byte offset to write */

sys/arch/armv7/exynos/ec_commands.h

825

uint32_t size; /* Size to write in bytes */

sys/arch/armv7/exynos/ec_commands.h

834

uint32_t time;

sys/arch/armv7/exynos/ec_commands.h

838

uint32_t time;

sys/arch/armv7/exynos/ec_commands.h

927

uint32_t rows;

sys/arch/armv7/exynos/ec_commands.h

928

uint32_t cols;

sys/arch/armv7/exynos/ec_commands.h

962

uint32_t valid_mask; /* valid fields */

sys/arch/armv7/exynos/ec_commands.h

967

uint32_t poll_timeout_us;

sys/arch/armv7/exynos/exclock.c

106

uint32_t exynos5250_get_frequency(void *, uint32_t *);

sys/arch/armv7/exynos/exclock.c

107

int exynos5250_set_frequency(void *, uint32_t *, uint32_t);

sys/arch/armv7/exynos/exclock.c

108

void exynos5250_enable(void *, uint32_t *, int);

sys/arch/armv7/exynos/exclock.c

109

uint32_t exynos5420_get_frequency(void *, uint32_t *);

sys/arch/armv7/exynos/exclock.c

110

int exynos5420_set_frequency(void *, uint32_t *, uint32_t);

sys/arch/armv7/exynos/exclock.c

111

void exynos5420_enable(void *, uint32_t *, int);

sys/arch/armv7/exynos/exclock.c

164

uint32_t

sys/arch/armv7/exynos/exclock.c

165

exynos5250_get_frequency(void *cookie, uint32_t *cells)

sys/arch/armv7/exynos/exclock.c

168

uint32_t idx = cells[0];

sys/arch/armv7/exynos/exclock.c

180

exynos5250_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/arch/armv7/exynos/exclock.c

182

uint32_t idx = cells[0];

sys/arch/armv7/exynos/exclock.c

194

exynos5250_enable(void *cookie, uint32_t *cells, int on)

sys/arch/armv7/exynos/exclock.c

196

uint32_t idx = cells[0];

sys/arch/armv7/exynos/exclock.c

231

uint32_t

sys/arch/armv7/exynos/exclock.c

232

exynos5420_get_frequency(void *cookie, uint32_t *cells)

sys/arch/armv7/exynos/exclock.c

235

uint32_t idx = cells[0];

sys/arch/armv7/exynos/exclock.c

236

uint32_t reg, div, mux;

sys/arch/armv7/exynos/exclock.c

237

uint32_t kdiv, mdiv, pdiv, sdiv;

sys/arch/armv7/exynos/exclock.c

302

exynos5420_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/arch/armv7/exynos/exclock.c

304

uint32_t idx = cells[0];

sys/arch/armv7/exynos/exclock.c

317

exynos5420_enable(void *cookie, uint32_t *cells, int on)

sys/arch/armv7/exynos/exclock.c

319

uint32_t idx = cells[0];

sys/arch/armv7/exynos/exclock.c

334

uint32_t

sys/arch/armv7/exynos/exclock.c

338

uint32_t m, p, s = 0, mask, fout;

sys/arch/armv7/exynos/exclock.c

384

uint32_t

sys/arch/armv7/exynos/exclock.c

387

uint32_t freq;

sys/arch/armv7/exynos/exclock.c

425

uint32_t freq_sel;

sys/arch/armv7/exynos/exclock.c

426

uint32_t pll_div2_sel = HREAD4(sc, CLOCK_PLL_DIV2_SEL);

sys/arch/armv7/exynos/exclock.c

449

uint32_t

sys/arch/armv7/exynos/exclock.c

452

uint32_t div, armclk, arm_ratio, arm2_ratio;

sys/arch/armv7/exynos/exclock.c

466

uint32_t

sys/arch/armv7/exynos/exclock.c

469

uint32_t div, kfc_ratio;

sys/arch/armv7/exynos/exclock.c

483

uint32_t aclk_66, aclk_66_pre, div, ratio;

sys/arch/armv7/exynos/exclock.c

92

uint32_t exclock_decode_pll_clk(enum clocks, unsigned int, unsigned int);

sys/arch/armv7/exynos/exclock.c

93

uint32_t exclock_get_pll_clk(struct exclock_softc *, enum clocks);

sys/arch/armv7/exynos/exclock.c

94

uint32_t exclock_get_armclk(struct exclock_softc *);

sys/arch/armv7/exynos/exclock.c

95

uint32_t exclock_get_kfcclk(struct exclock_softc *);

sys/arch/armv7/exynos/exdisplay.c

150

uint32_t defattr;

sys/arch/armv7/exynos/exdisplay.c

179

uint32_t defattr;

sys/arch/armv7/exynos/exdisplay.c

241

void **cookiep, int *curxp, int *curyp, uint32_t *attrp)

sys/arch/armv7/exynos/exdisplay.c

69

void **, int *, int *, uint32_t *);

sys/arch/armv7/exynos/exdog.c

113

uint32_t wtcon;

sys/arch/armv7/exynos/exdog.c

98

uint32_t wtcon;

sys/arch/armv7/exynos/exehci.c

117

uint32_t phys[2];

sys/arch/armv7/exynos/exehci.c

118

uint32_t phy_reg[2];

sys/arch/armv7/exynos/exehci.c

220

uint32_t pmureg, sysreg;

sys/arch/armv7/exynos/exehci.c

222

uint32_t val;

sys/arch/armv7/exynos/exgpio.c

128

int exgpio_pinctrl(uint32_t, void *);

sys/arch/armv7/exynos/exgpio.c

129

void exgpio_config_pin(void *, uint32_t *, int);

sys/arch/armv7/exynos/exgpio.c

130

int exgpio_get_pin(void *, uint32_t *);

sys/arch/armv7/exynos/exgpio.c

131

void exgpio_set_pin(void *, uint32_t *, int);

sys/arch/armv7/exynos/exgpio.c

206

exgpio_pinctrl(uint32_t phandle, void *cookie)

sys/arch/armv7/exynos/exgpio.c

211

uint32_t func, val, pud, drv;

sys/arch/armv7/exynos/exgpio.c

212

uint32_t reg;

sys/arch/armv7/exynos/exgpio.c

281

exgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/armv7/exynos/exgpio.c

284

uint32_t pin = cells[0];

sys/arch/armv7/exynos/exgpio.c

285

uint32_t val;

sys/arch/armv7/exynos/exgpio.c

299

exgpio_get_pin(void *cookie, uint32_t *cells)

sys/arch/armv7/exynos/exgpio.c

302

uint32_t pin = cells[0];

sys/arch/armv7/exynos/exgpio.c

303

uint32_t flags = cells[1];

sys/arch/armv7/exynos/exgpio.c

304

uint32_t reg;

sys/arch/armv7/exynos/exgpio.c

319

exgpio_set_pin(void *cookie, uint32_t *cells, int val)

sys/arch/armv7/exynos/exgpio.c

322

uint32_t pin = cells[0];

sys/arch/armv7/exynos/exgpio.c

323

uint32_t flags = cells[1];

sys/arch/armv7/exynos/exgpio.c

324

uint32_t reg;

sys/arch/armv7/exynos/exiic.c

158

uint32_t reg[1];

sys/arch/armv7/exynos/exiic.c

187

uint32_t freq, div = 0, pres = 16;

sys/arch/armv7/exynos/exiic.c

206

exiic_wait_state(struct exiic_softc *sc, uint32_t reg, uint32_t mask, uint32_t value)

sys/arch/armv7/exynos/exiic.c

208

uint32_t state;

sys/arch/armv7/exynos/exiic.c

252

uint32_t ret = 0;

sys/arch/armv7/exynos/exiic.c

84

int exiic_wait_state(struct exiic_softc *, uint32_t, uint32_t, uint32_t);

sys/arch/armv7/exynos/exmct.c

70

uint32_t i, mask, reg;

sys/arch/armv7/imx/imxahci.c

124

uint32_t timeout = 0x100000;

sys/arch/armv7/imx/imxahci.c

126

uint32_t reg;

sys/arch/armv7/imx/imxtemp.c

113

uint32_t phandle;

sys/arch/armv7/imx/imxtemp.c

130

uint32_t calibration;

sys/arch/armv7/imx/imxtemp.c

131

uint32_t phandle;

sys/arch/armv7/imx/imxtemp.c

160

imxtemp_calc_temp(struct imxtemp_softc *sc, uint32_t temp_cnt)

sys/arch/armv7/imx/imxtemp.c

199

uint32_t value;

sys/arch/armv7/imx/imxtemp.c

200

uint32_t temp_cnt;

sys/arch/armv7/imx/imxtemp.c

75

uint32_t sc_hot_count;

sys/arch/armv7/imx/imxtemp.c

76

uint32_t sc_hot_temp;

sys/arch/armv7/imx/imxtemp.c

77

uint32_t sc_room_count;

sys/arch/armv7/imx/imxtemp.c

96

int32_t imxtemp_calc_temp(struct imxtemp_softc *, uint32_t);

sys/arch/armv7/include/intr.h

137

extern uint32_t arm_smask[NIPL];

sys/arch/armv7/include/intr.h

166

uint32_t ic_phandle;

sys/arch/armv7/include/intr.h

167

uint32_t ic_cells;

sys/arch/armv7/marvell/mvacc.c

126

uint32_t

sys/arch/armv7/marvell/mvacc.c

127

mvacc_get_frequency(void *cookie, uint32_t *cells)

sys/arch/armv7/marvell/mvacc.c

130

uint32_t sar, cpu, tclk;

sys/arch/armv7/marvell/mvacc.c

43

static const uint32_t mvacc_cpu_freqs[] = {

sys/arch/armv7/marvell/mvacc.c

83

uint32_t mvacc_get_frequency(void *, uint32_t *);

sys/arch/armv7/marvell/mvagc.c

103

mvagc_enable(void *cookie, uint32_t *cells, int on)

sys/arch/armv7/marvell/mvagc.c

106

uint32_t id = cells[0];

sys/arch/armv7/marvell/mvagc.c

48

void mvagc_enable(void *, uint32_t *, int);

sys/arch/armv7/marvell/mvagc.c

49

uint32_t mvagc_gen_get_frequency(void *, uint32_t *);

sys/arch/armv7/marvell/mvagc.c

94

uint32_t

sys/arch/armv7/marvell/mvagc.c

95

mvagc_gen_get_frequency(void *cookie, uint32_t *cells)

sys/arch/armv7/marvell/mvmbus.c

180

uint32_t *ranges;

sys/arch/armv7/marvell/mvmbus.c

184

if (rangeslen <= 0 || (rangeslen % sizeof(uint32_t)))

sys/arch/armv7/marvell/mvmbus.c

200

rlen = rangeslen / sizeof(uint32_t);

sys/arch/armv7/marvell/mvmbus.c

206

uint32_t window = range[0];

sys/arch/armv7/marvell/mvmbus.c

210

uint32_t size = range[cac + pac];

sys/arch/armv7/marvell/mvmbus.c

215

uint32_t base = range[cac];

sys/arch/armv7/marvell/mvmbus.c

385

uint32_t base = bus_space_read_4(sc->sc_iot, sc->sc_sdram_ioh,

sys/arch/armv7/marvell/mvmbus.c

387

uint32_t size = bus_space_read_4(sc->sc_iot, sc->sc_sdram_ioh,

sys/arch/armv7/marvell/mvmbus.c

91

uint32_t mvmbus_pcie_mem_aperture[2];

sys/arch/armv7/marvell/mvmbus.c

92

uint32_t mvmbus_pcie_io_aperture[2];

sys/arch/armv7/marvell/mvmbusvar.h

26

uint32_t base;

sys/arch/armv7/marvell/mvmbusvar.h

27

uint32_t size;

sys/arch/armv7/marvell/mvmbusvar.h

32

extern uint32_t mvmbus_pcie_mem_aperture[2];

sys/arch/armv7/marvell/mvmbusvar.h

33

extern uint32_t mvmbus_pcie_io_aperture[2];

sys/arch/armv7/marvell/mvortc.c

123

uint32_t

sys/arch/armv7/marvell/mvortc.c

126

uint32_t sample, mode;

sys/arch/armv7/marvell/mvortc.c

127

uint32_t samples[100];

sys/arch/armv7/marvell/mvortc.c

164

mvortc_write(struct mvortc_softc *sc, int reg, uint32_t val)

sys/arch/armv7/marvell/mvortc.c

186

uint32_t reg;

sys/arch/armv7/marvell/mvortc.c

86

uint32_t reg;

sys/arch/armv7/marvell/mvpcie.c

108

uint32_t *po_gpio;

sys/arch/armv7/marvell/mvpcie.c

114

uint32_t po_bridge_command;

sys/arch/armv7/marvell/mvpcie.c

115

uint32_t po_bridge_bar0;

sys/arch/armv7/marvell/mvpcie.c

116

uint32_t po_bridge_bar1;

sys/arch/armv7/marvell/mvpcie.c

117

uint32_t po_bridge_businfo;

sys/arch/armv7/marvell/mvpcie.c

118

uint32_t po_bridge_iobase;

sys/arch/armv7/marvell/mvpcie.c

119

uint32_t po_bridge_iobaseupper;

sys/arch/armv7/marvell/mvpcie.c

120

uint32_t po_bridge_iolimit;

sys/arch/armv7/marvell/mvpcie.c

121

uint32_t po_bridge_iolimitupper;

sys/arch/armv7/marvell/mvpcie.c

122

uint32_t po_bridge_membase;

sys/arch/armv7/marvell/mvpcie.c

123

uint32_t po_bridge_memlimit;

sys/arch/armv7/marvell/mvpcie.c

125

uint32_t po_win_iotarget;

sys/arch/armv7/marvell/mvpcie.c

126

uint32_t po_win_ioattr;

sys/arch/armv7/marvell/mvpcie.c

127

uint32_t po_win_memtarget;

sys/arch/armv7/marvell/mvpcie.c

128

uint32_t po_win_memattr;

sys/arch/armv7/marvell/mvpcie.c

130

uint32_t po_win_iobase;

sys/arch/armv7/marvell/mvpcie.c

131

uint32_t po_win_iosize;

sys/arch/armv7/marvell/mvpcie.c

132

uint32_t po_win_ioremap;

sys/arch/armv7/marvell/mvpcie.c

133

uint32_t po_win_membase;

sys/arch/armv7/marvell/mvpcie.c

134

uint32_t po_win_memsize;

sys/arch/armv7/marvell/mvpcie.c

212

uint32_t bus_range[2];

sys/arch/armv7/marvell/mvpcie.c

213

uint32_t *ranges;

sys/arch/armv7/marvell/mvpcie.c

229

if (rangeslen <= 0 || (rangeslen % sizeof(uint32_t)) ||

sys/arch/armv7/marvell/mvpcie.c

230

(rangeslen / sizeof(uint32_t)) % (sc->sc_acells +

sys/arch/armv7/marvell/mvpcie.c

240

nranges = (rangeslen / sizeof(uint32_t)) /

sys/arch/armv7/marvell/mvpcie.c

320

uint32_t assigned[5];

sys/arch/armv7/marvell/mvpcie.c

321

uint32_t reg[5];

sys/arch/armv7/marvell/mvpcie.c

686

uint32_t old = po->po_bridge_command;

sys/arch/armv7/marvell/mvpcie.c

831

uint32_t reg[4];

sys/arch/armv7/marvell/mvpcie.c

89

uint32_t flags;

sys/arch/armv7/marvell/mvpcie.c

90

uint32_t slot;

sys/arch/armv7/marvell/mvpcie.c

91

uint32_t pci_base;

sys/arch/armv7/omap/amdisplay.c

127

preg(uint32_t reg, char *rn, struct amdisplay_softc *sc)

sys/arch/armv7/omap/amdisplay.c

129

uint32_t read;

sys/arch/armv7/omap/amdisplay.c

180

uint32_t reg;

sys/arch/armv7/omap/amdisplay.c

396

uint32_t reg;

sys/arch/armv7/omap/amdisplay.c

498

uint32_t timing0, timing1, timing2;

sys/arch/armv7/omap/amdisplay.c

499

uint32_t hbp, hfp, hsw, vbp, vfp, vsw, width, height;

sys/arch/armv7/omap/amdisplay.c

646

void **cookiep, int *curxp, int *curyp, uint32_t *attrp)

sys/arch/armv7/omap/amdisplay.c

99

void **, int *, int *, uint32_t *);

sys/arch/armv7/omap/dmtimer.c

340

uint32_t cycles;

sys/arch/armv7/omap/edma.c

108

uint32_t rev;

sys/arch/armv7/omap/edma.c

167

uint32_t ipr, iprh;

sys/arch/armv7/omap/edma.c

197

edma_intr_dma_en(uint32_t ch, edma_intr_cb_t cb, void *dat)

sys/arch/armv7/omap/edma.c

218

edma_intr_dma_dis(uint32_t ch)

sys/arch/armv7/omap/edma.c

234

edma_trig_xfer_man(uint32_t ch)

sys/arch/armv7/omap/edma.c

261

edma_trig_xfer_by_dev(uint32_t ch)

sys/arch/armv7/omap/edma.c

285

edma_param_write(uint32_t ch, struct edma_param *params)

sys/arch/armv7/omap/edma.c

288

EDMA_TPCC_OPT(ch), (uint32_t *)params, 8);

sys/arch/armv7/omap/edma.c

292

edma_param_read(uint32_t ch, struct edma_param *params)

sys/arch/armv7/omap/edma.c

295

EDMA_TPCC_OPT(ch), (uint32_t *)params, 8);

sys/arch/armv7/omap/edmavar.h

27

uint32_t opt; /* Option */

sys/arch/armv7/omap/edmavar.h

28

uint32_t src; /* Ch source */

sys/arch/armv7/omap/edmavar.h

31

uint32_t dst; /* Chan dst addr */

sys/arch/armv7/omap/edmavar.h

42

int edma_intr_dma_en(uint32_t, edma_intr_cb_t, void *); /* en it for chan */

sys/arch/armv7/omap/edmavar.h

43

int edma_intr_dma_dis(uint32_t); /* disable intr for chan */

sys/arch/armv7/omap/edmavar.h

44

int edma_trig_xfer_man(uint32_t); /* trig a dma xfer */

sys/arch/armv7/omap/edmavar.h

45

int edma_trig_xfer_by_dev(uint32_t); /* dma xfer trig by dev */

sys/arch/armv7/omap/edmavar.h

46

void edma_param_write(uint32_t, struct edma_param *);

sys/arch/armv7/omap/edmavar.h

47

void edma_param_read(uint32_t, struct edma_param *);

sys/arch/armv7/omap/gptimer.c

252

uint32_t cycles;

sys/arch/armv7/omap/if_cpsw.c

1150

uint32_t tx0_cp;

sys/arch/armv7/omap/if_cpsw.c

1241

uint32_t miscstat;

sys/arch/armv7/omap/if_cpsw.c

1242

uint32_t dmastat;

sys/arch/armv7/omap/if_cpsw.c

1243

uint32_t stat;

sys/arch/armv7/omap/if_cpsw.c

1282

uint32_t phy_id[2];

sys/arch/armv7/omap/if_cpsw.c

219

cpsw_set_txdesc_next(struct cpsw_softc * const sc, const u_int i, uint32_t n)

sys/arch/armv7/omap/if_cpsw.c

226

cpsw_set_rxdesc_next(struct cpsw_softc * const sc, const u_int i, uint32_t n)

sys/arch/armv7/omap/if_cpsw.c

238

(uint32_t *)bdp, 4);

sys/arch/armv7/omap/if_cpsw.c

247

(uint32_t *)bdp, 4);

sys/arch/armv7/omap/if_cpsw.c

256

(uint32_t *)bdp, 4);

sys/arch/armv7/omap/if_cpsw.c

265

(uint32_t *)bdp, 4);

sys/arch/armv7/omap/if_cpsw.c

285

uint32_t alive, link;

sys/arch/armv7/omap/if_cpsw.c

341

uint32_t memsize;

sys/arch/armv7/omap/if_cpsw.c

700

uint32_t v;

sys/arch/armv7/omap/if_cpsw.c

722

uint32_t v;

sys/arch/armv7/omap/if_cpswreg.h

132

uint32_t next;

sys/arch/armv7/omap/if_cpswreg.h

133

uint32_t bufptr;

sys/arch/armv7/omap/omap_machdep.c

27

extern void omap4_smc_call(uint32_t, uint32_t);

sys/arch/armv7/omap/omap_machdep.c

34

bus_size_t off, uint32_t op, uint32_t val)

sys/arch/armv7/omap/omapid.c

63

uint32_t rev;

sys/arch/armv7/omap/omapid.c

64

uint32_t newclockrate = 0;

sys/arch/armv7/omap/omclock.c

114

uint32_t

sys/arch/armv7/omap/omclock.c

115

omclock_get_frequency(void *cookie, uint32_t *cells)

sys/arch/armv7/omap/omclock.c

122

omclock_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/arch/armv7/omap/omclock.c

129

omclock_enable(void *cookie, uint32_t *cells, int on)

sys/arch/armv7/omap/omclock.c

132

uint32_t base = cells[0];

sys/arch/armv7/omap/omclock.c

133

uint32_t idx = cells[1];

sys/arch/armv7/omap/omclock.c

134

uint32_t reg;

sys/arch/armv7/omap/omclock.c

67

uint32_t omclock_get_frequency(void *, uint32_t *);

sys/arch/armv7/omap/omclock.c

68

int omclock_set_frequency(void *, uint32_t *, uint32_t);

sys/arch/armv7/omap/omclock.c

69

void omclock_enable(void *, uint32_t *, int);

sys/arch/armv7/omap/omdisplay.c

1149

void **cookiep, int *curxp, int *curyp, uint32_t *attrp)

sys/arch/armv7/omap/omdisplay.c

446

void **cookiep, int *curxp, int *curyp, uint32_t *attrp);

sys/arch/armv7/omap/omehci.c

113

uint32_t i;

sys/arch/armv7/omap/omehci.c

117

uint32_t reg[2];

sys/arch/armv7/omap/omehci.c

230

uint32_t i = 0, reg;

sys/arch/armv7/omap/omehci.c

231

uint32_t reset_performed = 0;

sys/arch/armv7/omap/omehci.c

232

uint32_t timeout = 0;

sys/arch/armv7/omap/omehci.c

233

uint32_t tll_ch_mask = 0;

sys/arch/armv7/omap/omehci.c

394

uint32_t reg;

sys/arch/armv7/omap/omehci.c

80

uint32_t ehci_rev;

sys/arch/armv7/omap/omehci.c

81

uint32_t tll_avail;

sys/arch/armv7/omap/omehci.c

83

uint32_t port_mode[OMAP_HS_USB_PORTS];

sys/arch/armv7/omap/omgpio.c

182

int (*sc_padconf_set_gpioflags)(uint32_t, uint32_t);

sys/arch/armv7/omap/omgpio.c

201

void omgpio_config_pin(void *, uint32_t *, int);

sys/arch/armv7/omap/omgpio.c

202

int omgpio_get_pin(void *, uint32_t *);

sys/arch/armv7/omap/omgpio.c

203

void omgpio_set_pin(void *, uint32_t *, int);

sys/arch/armv7/omap/omgpio.c

403

omgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/armv7/omap/omgpio.c

406

uint32_t pin = cells[0];

sys/arch/armv7/omap/omgpio.c

418

omgpio_get_pin(void *cookie, uint32_t *cells)

sys/arch/armv7/omap/omgpio.c

421

uint32_t pin = cells[0];

sys/arch/armv7/omap/omgpio.c

422

uint32_t flags = cells[1];

sys/arch/armv7/omap/omgpio.c

435

omgpio_set_pin(void *cookie, uint32_t *cells, int val)

sys/arch/armv7/omap/omgpio.c

438

uint32_t pin = cells[0];

sys/arch/armv7/omap/omgpio.c

439

uint32_t flags = cells[1];

sys/arch/armv7/omap/ommmc.c

1074

*(uint32_t *)datap = HREAD4(sc, MMCHS_DATA);

sys/arch/armv7/omap/ommmc.c

1079

uint32_t rv = HREAD4(sc, MMCHS_DATA);

sys/arch/armv7/omap/ommmc.c

1091

DPRINTF(3,("%08x\n", *(uint32_t *)datap));

sys/arch/armv7/omap/ommmc.c

1092

HWRITE4(sc, MMCHS_DATA, *((uint32_t *)datap));

sys/arch/armv7/omap/ommmc.c

1097

uint32_t rv = *datap++;

sys/arch/armv7/omap/ommmc.c

1185

uint32_t status;

sys/arch/armv7/omap/ommmc.c

193

uint32_t sc_flags;

sys/arch/armv7/omap/ommmc.c

195

uint32_t sc_gpio[4];

sys/arch/armv7/omap/ommmc.c

199

uint32_t clkbase; /* base clock frequency in kHz */

sys/arch/armv7/omap/ommmc.c

202

uint32_t ocr; /* OCR value from capabilities */

sys/arch/armv7/omap/ommmc.c

203

uint32_t intr_status; /* soft interrupt status */

sys/arch/armv7/omap/ommmc.c

204

uint32_t intr_error_status; /* */

sys/arch/armv7/omap/ommmc.c

231

uint32_t ommmc_host_ocr(sdmmc_chipset_handle_t);

sys/arch/armv7/omap/ommmc.c

234

int ommmc_bus_power(sdmmc_chipset_handle_t, uint32_t);

sys/arch/armv7/omap/ommmc.c

241

int ommmc_wait_state(struct ommmc_softc *, uint32_t, uint32_t);

sys/arch/armv7/omap/ommmc.c

300

uint32_t caps, width;

sys/arch/armv7/omap/ommmc.c

301

uint32_t addr, size;

sys/arch/armv7/omap/ommmc.c

524

uint32_t imask;

sys/arch/armv7/omap/ommmc.c

576

uint32_t

sys/arch/armv7/omap/ommmc.c

619

ommmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)

sys/arch/armv7/omap/ommmc.c

622

uint32_t vdd;

sys/arch/armv7/omap/ommmc.c

623

uint32_t reg;

sys/arch/armv7/omap/ommmc.c

688

ommmc_clock_divisor(struct ommmc_softc *sc, uint32_t freq)

sys/arch/armv7/omap/ommmc.c

691

uint32_t maxclk = MMCHS_SYSCTL_CLKD_MASK>>MMCHS_SYSCTL_CLKD_SH;

sys/arch/armv7/omap/ommmc.c

712

uint32_t reg;

sys/arch/armv7/omap/ommmc.c

829

ommmc_wait_state(struct ommmc_softc *sc, uint32_t mask, uint32_t value)

sys/arch/armv7/omap/ommmc.c

831

uint32_t state;

sys/arch/armv7/omap/ommmc.c

880

uint32_t v0,v1,v2,v3;

sys/arch/armv7/omap/ommmc.c

921

uint32_t blksize = 0;

sys/arch/armv7/omap/ommmc.c

922

uint32_t blkcount = 0;

sys/arch/armv7/omap/ommmc.c

923

uint32_t command;

sys/arch/armv7/omap/omrng.c

134

uint32_t status, detune;

sys/arch/armv7/omap/omusbtll.c

136

omusbtll_init(uint32_t channel_mask)

sys/arch/armv7/omap/omusbtll.c

139

uint32_t val;

sys/arch/armv7/omap/omusbtll.c

90

void omusbtll_init(uint32_t channel_mask);

sys/arch/armv7/omap/prcm.c

303

uint32_t

sys/arch/armv7/omap/prcm.c

338

uint32_t

sys/arch/armv7/omap/prcm.c

399

uint32_t clkctrl;

sys/arch/armv7/omap/prcm.c

417

uint32_t bit;

sys/arch/armv7/omap/prcm.c

418

uint32_t fclk, iclk, fmask, imask, mbit;

sys/arch/armv7/omap/prcm.c

485

uint32_t i;

sys/arch/armv7/omap/prcm.c

486

uint32_t clksel_reg_off;

sys/arch/armv7/omap/prcm.c

487

uint32_t clksel, oclksel;

sys/arch/armv7/omap/prcm.c

534

uint32_t clksel_reg_off;

sys/arch/armv7/omap/prcm.c

535

uint32_t clksel;

sys/arch/armv7/omap/prcm.c

571

uint32_t val;

sys/arch/armv7/omap/prcm.c

68

uint32_t prcm_imask_mask[PRCM_REG_MAX];

sys/arch/armv7/omap/prcm.c

69

uint32_t prcm_fmask_mask[PRCM_REG_MAX];

sys/arch/armv7/omap/prcm.c

70

uint32_t prcm_imask_addr[PRCM_REG_MAX];

sys/arch/armv7/omap/prcm.c

71

uint32_t prcm_fmask_addr[PRCM_REG_MAX];

sys/arch/armv7/omap/prcm.c

87

uint32_t cm1_avail;

sys/arch/armv7/omap/prcm.c

88

uint32_t cm2_avail;

sys/arch/armv7/omap/prcm.c

93

uint32_t prcm_v3_bit(int mod);

sys/arch/armv7/omap/prcm.c

94

uint32_t prcm_am335x_clkctrl(int mod);

sys/arch/armv7/omap/ti_iic.c

134

void ti_iic_handle_intr(struct ti_iic_softc *, uint32_t);

sys/arch/armv7/omap/ti_iic.c

135

void ti_iic_do_read(struct ti_iic_softc *, uint32_t);

sys/arch/armv7/omap/ti_iic.c

136

void ti_iic_do_write(struct ti_iic_softc *, uint32_t);

sys/arch/armv7/omap/ti_iic.c

139

uint32_t ti_iic_stat(struct ti_iic_softc *, uint32_t);

sys/arch/armv7/omap/ti_iic.c

223

uint32_t stat;

sys/arch/armv7/omap/ti_iic.c

308

uint32_t psc, scll, sclh;

sys/arch/armv7/omap/ti_iic.c

453

ti_iic_handle_intr(struct ti_iic_softc *sc, uint32_t stat)

sys/arch/armv7/omap/ti_iic.c

474

ti_iic_do_read(struct ti_iic_softc *sc, uint32_t stat)

sys/arch/armv7/omap/ti_iic.c

500

ti_iic_do_write(struct ti_iic_softc *sc, uint32_t stat)

sys/arch/armv7/omap/ti_iic.c

551

uint32_t

sys/arch/armv7/omap/ti_iic.c

552

ti_iic_stat(struct ti_iic_softc *sc, uint32_t mask)

sys/arch/armv7/omap/ti_iic.c

554

uint32_t v;

sys/arch/armv7/omap/ti_iic.c

597

uint32_t reg[1];

sys/arch/armv7/stand/efiboot/efiboot.c

381

uint32_t acells, scells;

sys/arch/armv7/stand/efiboot/efiboot.c

383

uint32_t reg[4];

sys/arch/armv7/stand/efiboot/efiboot.c

384

uint32_t width, height, stride;

sys/arch/armv7/stand/efiboot/efiboot.c

546

uint32_t boothowto = htobe32(howto);

sys/arch/armv7/stand/efiboot/efiboot.c

620

uint32_t uefi_mmap_size = htobe32(mmap_ndesc * mmap_descsiz);

sys/arch/armv7/stand/efiboot/efiboot.c

621

uint32_t uefi_mmap_desc_size = htobe32(mmap_descsiz);

sys/arch/armv7/stand/efiboot/efiboot.c

622

uint32_t uefi_mmap_desc_ver = htobe32(mmap_version);

sys/arch/armv7/stand/efiboot/efidev.c

270

uint32_t orig_csum, new_csum;

sys/arch/armv7/stand/efiboot/efidev.c

271

uint32_t ghsize, ghpartsize, ghpartnum, ghpartspersec;

sys/arch/armv7/stand/efiboot/efidev.c

272

uint32_t gpsectors;

sys/arch/armv7/stand/efiboot/exec.c

100

uint32_t sctlr;

sys/arch/armv7/stand/efiboot/exec.c

112

uint32_t sctlr;

sys/arch/armv7/stand/efiboot/exec.c

124

uint32_t sctlr;

sys/arch/armv7/stand/efiboot/exec.c

51

uint32_t clidr;

sys/arch/armv7/stand/efiboot/exec.c

52

uint32_t ccsidr;

sys/arch/armv7/stand/efiboot/exec.c

53

uint32_t val;

sys/arch/armv7/stand/efiboot/fdt.c

132

fdt_get_str(uint32_t num)

sys/arch/armv7/stand/efiboot/fdt.c

142

size_t len = roundup(strlen(name) + 1, sizeof(uint32_t));

sys/arch/armv7/stand/efiboot/fdt.c

160

skip_nops(uint32_t *ptr)

sys/arch/armv7/stand/efiboot/fdt.c

169

skip_property(uint32_t *ptr)

sys/arch/armv7/stand/efiboot/fdt.c

171

uint32_t size;

sys/arch/armv7/stand/efiboot/fdt.c

175

ptr += 3 + roundup(size, sizeof(uint32_t)) / sizeof(uint32_t);

sys/arch/armv7/stand/efiboot/fdt.c

181

skip_props(uint32_t *ptr)

sys/arch/armv7/stand/efiboot/fdt.c

190

skip_node_name(uint32_t *ptr)

sys/arch/armv7/stand/efiboot/fdt.c

194

sizeof(uint32_t)) / sizeof(uint32_t);

sys/arch/armv7/stand/efiboot/fdt.c

206

uint32_t *ptr;

sys/arch/armv7/stand/efiboot/fdt.c

207

uint32_t nameid;

sys/arch/armv7/stand/efiboot/fdt.c

213

ptr = (uint32_t *)node;

sys/arch/armv7/stand/efiboot/fdt.c

236

uint32_t *ptr, *next;

sys/arch/armv7/stand/efiboot/fdt.c

237

uint32_t nameid;

sys/arch/armv7/stand/efiboot/fdt.c

238

uint32_t curlen;

sys/arch/armv7/stand/efiboot/fdt.c

245

ptr = (uint32_t *)node;

sys/arch/armv7/stand/efiboot/fdt.c

258

delta = roundup(len, sizeof(uint32_t)) -

sys/arch/armv7/stand/efiboot/fdt.c

259

roundup(curlen, sizeof(uint32_t));

sys/arch/armv7/stand/efiboot/fdt.c

28

char *fdt_get_str(uint32_t);

sys/arch/armv7/stand/efiboot/fdt.c

286

uint32_t *ptr = (uint32_t *)node;

sys/arch/armv7/stand/efiboot/fdt.c

29

void *skip_property(uint32_t *);

sys/arch/armv7/stand/efiboot/fdt.c

291

if (end + 3 * sizeof(uint32_t) > tree.end)

sys/arch/armv7/stand/efiboot/fdt.c

297

tree.struct_size += 3 * sizeof(uint32_t);

sys/arch/armv7/stand/efiboot/fdt.c

298

tree.strings += 3 * sizeof(uint32_t);

sys/arch/armv7/stand/efiboot/fdt.c

30

void *skip_props(uint32_t *);

sys/arch/armv7/stand/efiboot/fdt.c

31

void *skip_node_name(uint32_t *);

sys/arch/armv7/stand/efiboot/fdt.c

310

size_t len = roundup(strlen(name) + 1, sizeof(uint32_t)) + 8;

sys/arch/armv7/stand/efiboot/fdt.c

312

uint32_t *ptr = (uint32_t *)node;

sys/arch/armv7/stand/efiboot/fdt.c

33

void *skip_nops(uint32_t *);

sys/arch/armv7/stand/efiboot/fdt.c

338

ptr += (len - 8) / sizeof(uint32_t);

sys/arch/armv7/stand/efiboot/fdt.c

351

uint32_t *ptr = node;

sys/arch/armv7/stand/efiboot/fdt.c

373

uint32_t *ptr;

sys/arch/armv7/stand/efiboot/fdt.c

381

ptr = skip_nops((uint32_t *)tree.tree);

sys/arch/armv7/stand/efiboot/fdt.c

43

uint32_t *ptr, *tok;

sys/arch/armv7/stand/efiboot/fdt.c

443

uint32_t *ptr;

sys/arch/armv7/stand/efiboot/fdt.c

46

ptr = (uint32_t *)fdt;

sys/arch/armv7/stand/efiboot/fdt.c

467

uint32_t *ptr;

sys/arch/armv7/stand/efiboot/fdt.c

573

uint32_t *ptr;

sys/arch/armv7/stand/efiboot/fdt.c

576

uint32_t nameid, size;

sys/arch/armv7/stand/efiboot/fdt.c

578

ptr = (uint32_t *)node;

sys/arch/armv7/stand/efiboot/fdt.c

608

if ((cnt % sizeof(uint32_t)) == 0)

sys/arch/armv7/stand/efiboot/fdt.c

613

ptr += roundup(size, sizeof(uint32_t)) / sizeof(uint32_t);

sys/arch/armv7/stand/efiboot/fdt.c

622

uint32_t *ptr;

sys/arch/armv7/stand/efiboot/fdt.c

625

ptr = (uint32_t *)node;

sys/arch/armv7/stand/efiboot/fdt.h

20

uint32_t fh_magic;

sys/arch/armv7/stand/efiboot/fdt.h

21

uint32_t fh_size;

sys/arch/armv7/stand/efiboot/fdt.h

22

uint32_t fh_struct_off;

sys/arch/armv7/stand/efiboot/fdt.h

23

uint32_t fh_strings_off;

sys/arch/armv7/stand/efiboot/fdt.h

24

uint32_t fh_reserve_off;

sys/arch/armv7/stand/efiboot/fdt.h

25

uint32_t fh_version;

sys/arch/armv7/stand/efiboot/fdt.h

26

uint32_t fh_comp_ver; /* last compatible version */

sys/arch/armv7/stand/efiboot/fdt.h

27

uint32_t fh_boot_cpu_id; /* fh_version >=2 */

sys/arch/armv7/stand/efiboot/fdt.h

28

uint32_t fh_strings_size; /* fh_version >=3 */

sys/arch/armv7/stand/efiboot/fdt.h

29

uint32_t fh_struct_size; /* fh_version >=17 */

sys/arch/armv7/sunxi/sxiahci.c

223

uint32_t r;

sys/arch/armv7/sunxi/sxiahci.c

96

uint32_t target_supply;

sys/arch/armv7/sunxi/sxiahci.c

97

uint32_t timo;

sys/arch/armv7/sunxi/sxie.c

162

uint32_t intr_status; /* soft interrupt status */

sys/arch/armv7/sunxi/sxie.c

163

uint32_t pauseframe;

sys/arch/armv7/sunxi/sxie.c

164

uint32_t txf_inuse;

sys/arch/armv7/sunxi/sxie.c

294

uint32_t reg;

sys/arch/armv7/sunxi/sxie.c

340

uint32_t clr_m, set_m;

sys/arch/armv7/sunxi/sxie.c

436

uint32_t pending;

sys/arch/armv7/sunxi/sxie.c

477

uint32_t fifo;

sys/arch/armv7/sunxi/sxie.c

478

uint32_t txbuf[SXIE_MAX_PKT_SIZE / sizeof(uint32_t)]; /* XXX !!! */

sys/arch/armv7/sunxi/sxie.c

525

(uint32_t *)td, SXIE_ROUNDUP(m->m_pkthdr.len, 4) >> 2);

sys/arch/armv7/sunxi/sxie.c

578

uint32_t fbc, reg;

sys/arch/armv7/sunxi/sxie.c

622

SXIE_RXIO, (uint32_t *)&rxbuf[0], rlen >> 2);

sys/arch/armv7/sunxi/sxiintc.c

329

uint32_t pr;

sys/arch/armv7/sunxi/sxiintc.c

377

uint32_t er;

sys/arch/armv7/sunxi/sxiintc.c

429

uint32_t er;

sys/arch/armv7/sunxi/sxitimer.c

112

uint32_t sxitimer_freq[] = {

sys/arch/armv7/sunxi/sxitimer.c

119

uint32_t sxitimer_irq[] = {

sys/arch/armv7/sunxi/sxitimer.c

210

uint32_t isr, ier, ctrl;

sys/arch/armv7/sunxi/sxitimer.c

257

uint32_t low, high;

sys/arch/armv7/sunxi/sxitimer.c

275

uint32_t

sys/arch/armv7/sunxi/sxitimer.c

285

uint32_t now = sxitimer_readcnt32();

sys/arch/armv7/sunxi/sxitimer.c

317

uint32_t ctrl, cycles;

sys/arch/armv7/sunxi/sxitimer.c

345

uint32_t ctrl;

sys/arch/armv7/sunxi/sxitimer.c

82

uint32_t sxitimer_readcnt32(void);

sys/arch/armv7/vexpress/pciecam.c

128

uint32_t *ranges;

sys/arch/armv7/vexpress/pciecam.c

143

if (rangeslen <= 0 || (rangeslen % sizeof(uint32_t)) ||

sys/arch/armv7/vexpress/pciecam.c

144

(rangeslen / sizeof(uint32_t)) % (sc->sc_acells +

sys/arch/armv7/vexpress/pciecam.c

152

nranges = (rangeslen / sizeof(uint32_t)) /

sys/arch/armv7/vexpress/pciecam.c

421

uint32_t reg[4];

sys/arch/armv7/vexpress/pciecam.c

59

uint32_t flags;

sys/arch/armv7/vexpress/sysreg.c

82

uint32_t id;

sys/arch/armv7/xilinx/slcreg.h

48

uint32_t zynq_slcr_read(struct regmap *, uint32_t);

sys/arch/armv7/xilinx/slcreg.h

49

void zynq_slcr_write(struct regmap *, uint32_t, uint32_t);

sys/arch/armv7/xilinx/zqclock.c

139

zqclock_get_clock(uint32_t idx)

sys/arch/armv7/xilinx/zqclock.c

153

uint32_t

sys/arch/armv7/xilinx/zqclock.c

154

zqclock_get_pll_frequency(struct zqclock_softc *sc, uint32_t clk_ctrl)

sys/arch/armv7/xilinx/zqclock.c

156

uint32_t reg, val;

sys/arch/armv7/xilinx/zqclock.c

175

uint32_t

sys/arch/armv7/xilinx/zqclock.c

176

zqclock_get_frequency(void *cookie, uint32_t *cells)

sys/arch/armv7/xilinx/zqclock.c

180

uint32_t idx = cells[0];

sys/arch/armv7/xilinx/zqclock.c

181

uint32_t ctl, div, freq;

sys/arch/armv7/xilinx/zqclock.c

204

zqclock_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/arch/armv7/xilinx/zqclock.c

206

static const uint32_t srcsels[] = {

sys/arch/armv7/xilinx/zqclock.c

213

uint32_t idx = cells[0];

sys/arch/armv7/xilinx/zqclock.c

214

uint32_t best_delta = ~0U;

sys/arch/armv7/xilinx/zqclock.c

215

uint32_t best_div1 = 0;

sys/arch/armv7/xilinx/zqclock.c

216

uint32_t best_si = 0;

sys/arch/armv7/xilinx/zqclock.c

217

uint32_t best_pllf = 0;

sys/arch/armv7/xilinx/zqclock.c

218

uint32_t ctl, div, div1, maxdiv1, si;

sys/arch/armv7/xilinx/zqclock.c

236

uint32_t delta, f, pllf;

sys/arch/armv7/xilinx/zqclock.c

295

zqclock_enable(void *cookie, uint32_t *cells, int on)

sys/arch/armv7/xilinx/zqclock.c

299

uint32_t idx = cells[0];

sys/arch/armv7/xilinx/zqclock.c

300

uint32_t ctl;

sys/arch/armv7/xilinx/zqclock.c

72

uint32_t sc_psclk_freq; /* in Hz */

sys/arch/armv7/xilinx/zqclock.c

78

void zqclock_enable(void *, uint32_t *, int);

sys/arch/armv7/xilinx/zqclock.c

79

uint32_t zqclock_get_frequency(void *, uint32_t *);

sys/arch/armv7/xilinx/zqclock.c

80

int zqclock_set_frequency(void *, uint32_t *, uint32_t);

sys/arch/armv7/xilinx/zqreset.c

105

zynq_slcr_write(struct regmap *rm, uint32_t reg, uint32_t val)

sys/arch/armv7/xilinx/zqreset.c

98

uint32_t

sys/arch/armv7/xilinx/zqreset.c

99

zynq_slcr_read(struct regmap *rm, uint32_t reg)

sys/arch/hppa/dev/clock.c

161

uint32_t cycles, t0, t1;

sys/arch/hppa/hppa/db_disasm.c

2213

uint32_t instruct;

sys/arch/hppa/hppa/db_disasm.c

2219

if (copyinsn(NULL, (uint32_t *)(loc &~ HPPA_PC_PRIV_MASK),

sys/arch/hppa/hppa/machdep.c

1119

copyin32(const uint32_t *src, uint32_t *dst)

sys/arch/hppa/hppa/machdep.c

295

extern uint32_t hpmc_v[], hpmc_tramp[], hpmc_tramp_end[];

sys/arch/hppa/hppa/machdep.c

296

uint32_t *p;

sys/arch/hppa/hppa/machdep.c

297

uint32_t cksum = 0;

sys/arch/hppa/hppa/machdep.c

306

p[6] = (uint32_t)&hpmc_tramp;

sys/arch/hppa/hppa/machdep.c

307

p[7] = (hpmc_tramp_end - hpmc_tramp) * sizeof(uint32_t);

sys/arch/hppa/include/cpu.h

250

int spcopy32(pa_space_t ssp, const uint32_t *src,

sys/arch/hppa/include/cpu.h

251

pa_space_t dsp, uint32_t *dst);

sys/arch/hppa/include/reg.h

178

uint32_t r_regs[HPPA_NREGS]; /* r0 is psw */

sys/arch/hppa/include/reg.h

180

uint32_t r_sar;

sys/arch/hppa/include/reg.h

182

uint32_t r_pcsqh;

sys/arch/hppa/include/reg.h

183

uint32_t r_pcsqt;

sys/arch/hppa/include/reg.h

184

uint32_t r_pcoqh;

sys/arch/hppa/include/reg.h

185

uint32_t r_pcoqt;

sys/arch/hppa/include/reg.h

187

uint32_t r_sr0;

sys/arch/hppa/include/reg.h

188

uint32_t r_sr1;

sys/arch/hppa/include/reg.h

189

uint32_t r_sr2;

sys/arch/hppa/include/reg.h

190

uint32_t r_sr3;

sys/arch/hppa/include/reg.h

191

uint32_t r_sr4;

sys/arch/hppa/include/reg.h

192

uint32_t r_sr5;

sys/arch/hppa/include/reg.h

193

uint32_t r_sr6;

sys/arch/hppa/include/reg.h

194

uint32_t r_sr7;

sys/arch/hppa/include/reg.h

196

uint32_t r_cr26;

sys/arch/hppa/include/reg.h

197

uint32_t r_cr27;

sys/arch/hppa/stand/libsa/cmd_hppa.c

813

uint32_t id, bhlcr, class;

sys/arch/hppa/stand/libsa/cmd_hppa.c

814

uint32_t (*conf_read)(u_int, int, int, u_int);

sys/arch/hppa/stand/libsa/cmd_hppa.c

89

uint32_t dino_conf_read(u_int, int, int, u_int);

sys/arch/hppa/stand/libsa/cmd_hppa.c

894

uint32_t

sys/arch/hppa/stand/libsa/cmd_hppa.c

897

volatile uint32_t *dino = (volatile uint32_t *)hpa;

sys/arch/hppa/stand/libsa/cmd_hppa.c

898

uint32_t pamr;

sys/arch/hppa/stand/libsa/cmd_hppa.c

899

uint32_t addr, id;

sys/arch/hppa/stand/libsa/cmd_hppa.c

90

uint32_t elroy_conf_read(u_int, int, int, u_int);

sys/arch/hppa/stand/libsa/cmd_hppa.c

912

uint32_t

sys/arch/hppa/stand/libsa/cmd_hppa.c

916

uint32_t arb_mask, err_cfg, control;

sys/arch/hppa/stand/libsa/cmd_hppa.c

917

uint32_t addr, id;

sys/arch/hppa/stand/libsa/cmd_hppa.c

921

arb_mask = *(volatile uint32_t *)&elroy->arb_mask;

sys/arch/hppa/stand/libsa/cmd_hppa.c

922

err_cfg = *(volatile uint32_t *)&elroy->err_cfg;

sys/arch/hppa/stand/libsa/cmd_hppa.c

923

control = *(volatile uint32_t *)&elroy->control;

sys/arch/hppa/stand/libsa/cmd_hppa.c

926

*(volatile uint32_t *)&elroy->arb_mask =

sys/arch/hppa/stand/libsa/cmd_hppa.c

928

*(volatile uint32_t *)&elroy->err_cfg = err_cfg |

sys/arch/hppa/stand/libsa/cmd_hppa.c

930

*(volatile uint32_t *)&elroy->control =

sys/arch/hppa/stand/libsa/cmd_hppa.c

933

*(volatile uint32_t *)&elroy->pci_conf_addr = htole32(addr);

sys/arch/hppa/stand/libsa/cmd_hppa.c

934

addr = *(volatile uint32_t *)&elroy->pci_conf_addr;

sys/arch/hppa/stand/libsa/cmd_hppa.c

935

id = *(volatile uint32_t *)&elroy->pci_conf_data;

sys/arch/hppa/stand/libsa/cmd_hppa.c

937

*(volatile uint32_t *)&elroy->control =

sys/arch/hppa/stand/libsa/cmd_hppa.c

939

*(volatile uint32_t *)&elroy->control = control;

sys/arch/hppa/stand/libsa/cmd_hppa.c

940

*(volatile uint32_t *)&elroy->err_cfg = err_cfg;

sys/arch/hppa/stand/libsa/cmd_hppa.c

942

*(volatile uint32_t *)&elroy->arb_mask = arb_mask;

sys/arch/i386/i386/acpi_machdep.c

240

acpi_acquire_glk(uint32_t *lock)

sys/arch/i386/i386/acpi_machdep.c

242

uint32_t new, old;

sys/arch/i386/i386/acpi_machdep.c

260

acpi_release_glk(uint32_t *lock)

sys/arch/i386/i386/acpi_machdep.c

262

uint32_t new, old;

sys/arch/i386/i386/bios.c

102

uint32_t bios_cksumlen;

sys/arch/i386/i386/bios.c

224

bios32_entry.offset = (uint32_t)ISA_HOLE_VADDR(h->entry);

sys/arch/i386/i386/bios.c

455

uint32_t off, len;

sys/arch/i386/i386/bios.c

540

bios_cksumlen = *(uint32_t *)q->ba_arg;

sys/arch/i386/i386/bios.c

645

bios32_service(uint32_t service, bios32_entry_t e, bios32_entry_info_t ei)

sys/arch/i386/i386/bios.c

649

uint32_t base, count, off, ent;

sys/arch/i386/i386/cpu.c

477

uint32_t dummy, sefflags_edx;

sys/arch/i386/i386/cpu.c

530

uint32_t r;

sys/arch/i386/i386/cpu.c

590

(uint32_t)va, (uint32_t)pa);

sys/arch/i386/i386/cpu.c

597

(uint32_t)va, (uint32_t)pa);

sys/arch/i386/i386/cpu.c

603

(uint32_t)cif->cif_tss.tss_esp0);

sys/arch/i386/i386/cpu.c

611

(uint32_t)cif->cif_nmi_tss.tss_esp0);

sys/arch/i386/i386/db_interface.c

189

uint32_t cr;

sys/arch/i386/i386/db_memrw.c

71

uint32_t bits;

sys/arch/i386/i386/hibernate_machdep.c

61

typedef uint32_t pt_entry_t;

sys/arch/i386/i386/i686_mem.c

530

uint32_t regs[4];

sys/arch/i386/i386/lapic.c

255

void lapic_timer_oneshot(uint32_t, uint32_t);

sys/arch/i386/i386/lapic.c

256

void lapic_timer_periodic(uint32_t, uint32_t);

sys/arch/i386/i386/lapic.c

261

uint32_t cycles;

sys/arch/i386/i386/lapic.c

289

lapic_timer_start(uint32_t mode, uint32_t mask, uint32_t cycles)

sys/arch/i386/i386/lapic.c

297

lapic_timer_oneshot(uint32_t mask, uint32_t cycles)

sys/arch/i386/i386/lapic.c

303

lapic_timer_periodic(uint32_t mask, uint32_t cycles)

sys/arch/i386/i386/longrun.c

100

uint32_t mode;

sys/arch/i386/i386/longrun.c

40

uint32_t regs[2];

sys/arch/i386/i386/longrun.c

76

uint32_t regs[4];

sys/arch/i386/i386/machdep.c

1650

extern uint32_t cpu_meltdown;

sys/arch/i386/i386/machdep.c

1873

uint32_t dummy;

sys/arch/i386/i386/machdep.c

1990

uint32_t dummy, val;

sys/arch/i386/i386/machdep.c

3892

copyin32(const uint32_t *uaddr, uint32_t *kaddr)

sys/arch/i386/i386/machdep.c

3898

return copyin(uaddr, kaddr, sizeof(uint32_t));

sys/arch/i386/i386/pctr.c

34

uint32_t pctr_intel_cap;

sys/arch/i386/i386/pctr.c

74

uint32_t dummy;

sys/arch/i386/i386/pmap.c

1269

pde_index, (uint32_t)&PDE(pmap, pde_index),

sys/arch/i386/i386/pmap.c

1270

(uint32_t)&(pva_intel[pde_index]));

sys/arch/i386/i386/pmap.c

1340

(uint32_t)va);

sys/arch/i386/i386/pmap.c

2463

uint32_t l2idx, l1idx;

sys/arch/i386/i386/pmap.c

2478

(uint32_t)pmap->pm_pdir_intel, (uint32_t)pmap->pm_pdirpa_intel);

sys/arch/i386/i386/pmap.c

2514

"setting PDE[%d] = 0x%x\n", __func__, (uint32_t)npa,

sys/arch/i386/i386/pmap.c

398

uint32_t protection_codes[8]; /* maps MI prot to i386 prot code */

sys/arch/i386/i386/pmap.c

455

extern uint32_t cpu_meltdown;

sys/arch/i386/i386/pmap.c

569

uint32_t opte, uint32_t npte)

sys/arch/i386/i386/pmap.c

833

uint32_t bits;

sys/arch/i386/i386/pmap.c

834

uint32_t global = 0;

sys/arch/i386/i386/pmap.c

871

uint32_t bits;

sys/arch/i386/i386/pmapae.c

1894

uint32_t l2idx, l1idx;

sys/arch/i386/i386/pmapae.c

1908

(uint32_t)pmap->pm_pdir_intel, (uint32_t)pmap->pm_pdirpa_intel);

sys/arch/i386/i386/pmapae.c

1945

"setting PDE[%d] = 0x%llx\n", __func__, (uint32_t)npa,

sys/arch/i386/i386/pmapae.c

467

extern uint32_t cpu_meltdown;

sys/arch/i386/i386/pmapae.c

661

(uint32_t)kpm->pm_pdir, (uint32_t)kpm->pm_pdirpa,

sys/arch/i386/i386/pmapae.c

677

pd = (uint32_t *)kpm->pm_pdir_intel;

sys/arch/i386/i386/pmapae.c

722

uint32_t *ptp;

sys/arch/i386/i386/pmapae.c

723

uint32_t l1idx, l2idx;

sys/arch/i386/i386/pmapae.c

740

ptp = (uint32_t *)pmap_tmpmap_pa_86(npa);

sys/arch/i386/i386/pmapae.c

748

__func__, (uint32_t)va, l2idx, (uint32_t)pd[l2idx],

sys/arch/i386/i386/pmapae.c

749

l1idx, (uint32_t)ptp[l1idx]);

sys/arch/i386/i386/pmapae.c

768

(uint32_t)VM_PAGE_TO_PHYS(ptppg));

sys/arch/i386/i386/pmapae.c

772

DPRINTF("%s: freeing PDP 0x%x\n", __func__, (uint32_t)pd);

sys/arch/i386/i386/pmapae.c

786

__func__, (uint32_t)kpm->pm_pdir, (uint32_t)kpm->pm_pdirpa,

sys/arch/i386/i386/pmapae.c

959

(uint32_t)va);

sys/arch/i386/i386/powernow-k7.c

127

uint32_t signature;

sys/arch/i386/i386/powernow-k7.c

138

int k7pnow_states(struct k7pnow_cpu_state *, uint32_t, unsigned int,

sys/arch/i386/i386/powernow-k7.c

245

k7pnow_states(struct k7pnow_cpu_state *cstate, uint32_t cpusig,

sys/arch/i386/i386/powernow-k7.c

304

uint32_t ctrl;

sys/arch/i386/i386/powernow-k7.c

337

uint32_t ctrl;

sys/arch/i386/i386/powernow-k7.c

353

uint32_t ctrl;

sys/arch/i386/i386/powernow-k8.c

132

uint32_t cpuid;

sys/arch/i386/i386/powernow-k8.c

145

int k8pnow_states(struct k8pnow_cpu_state *, uint32_t, unsigned int, unsigned int);

sys/arch/i386/i386/powernow-k8.c

313

k8pnow_states(struct k8pnow_cpu_state *cstate, uint32_t cpusig,

sys/arch/i386/i386/powernow-k8.c

370

uint32_t ctrl;

sys/arch/i386/i386/powernow-k8.c

402

uint32_t ctrl;

sys/arch/i386/i386/powernow-k8.c

424

uint32_t ctrl;

sys/arch/i386/i386/powernow.c

58

uint32_t portval;

sys/arch/i386/i386/powernow.c

88

uint32_t portval;

sys/arch/i386/i386/sys_machdep.c

138

uint32_t base = i386_get_threadbase(p, TSEG_FS);

sys/arch/i386/i386/sys_machdep.c

146

uint32_t base;

sys/arch/i386/i386/sys_machdep.c

156

uint32_t base = i386_get_threadbase(p, TSEG_GS);

sys/arch/i386/i386/sys_machdep.c

164

uint32_t base;

sys/arch/i386/i386/sys_machdep.c

87

uint32_t

sys/arch/i386/i386/sys_machdep.c

96

i386_set_threadbase(struct proc *p, uint32_t base, int which)

sys/arch/i386/i386/trap.c

114

upageflttrap(struct trapframe *frame, uint32_t cr2)

sys/arch/i386/i386/trap.c

163

kpageflttrap(struct trapframe *frame, uint32_t cr2)

sys/arch/i386/i386/trap.c

243

uint32_t cr2 = rcr2();

sys/arch/i386/i386/trap.c

63

int upageflttrap(struct trapframe *, uint32_t);

sys/arch/i386/i386/trap.c

64

int kpageflttrap(struct trapframe *, uint32_t);

sys/arch/i386/i386/ucode.c

145

uint32_t id;

sys/arch/i386/i386/ucode.c

146

uint32_t a;

sys/arch/i386/i386/ucode.c

147

uint32_t b;

sys/arch/i386/i386/ucode.c

153

uint32_t type;

sys/arch/i386/i386/ucode.c

154

uint32_t len;

sys/arch/i386/i386/ucode.c

155

uint32_t a;

sys/arch/i386/i386/ucode.c

156

uint32_t level;

sys/arch/i386/i386/ucode.c

165

uint32_t magic, tlen, i;

sys/arch/i386/i386/ucode.c

167

uint32_t sig, ebx, ecx, edx;

sys/arch/i386/i386/ucode.c

169

uint32_t patch_len = 0;

sys/arch/i386/i386/ucode.c

247

uint32_t old_rev, new_rev;

sys/arch/i386/i386/ucode.c

297

cpu_ucode_intel_find(char *data, size_t left, uint32_t current)

sys/arch/i386/i386/ucode.c

300

uint32_t sig, dummy1, dummy2, dummy3;

sys/arch/i386/i386/ucode.c

301

uint32_t mask = 1UL << platform_id;

sys/arch/i386/i386/ucode.c

303

uint32_t total_size;

sys/arch/i386/i386/ucode.c

346

uint32_t *data = (uint32_t *)hdr;

sys/arch/i386/i386/ucode.c

348

uint32_t sum;

sys/arch/i386/i386/ucode.c

385

uint32_t processor_sig, uint32_t processor_mask,

sys/arch/i386/i386/ucode.c

386

uint32_t ucode_revision)

sys/arch/i386/i386/ucode.c

390

uint32_t data_size, total_size;

sys/arch/i386/i386/ucode.c

42

uint32_t header_version;

sys/arch/i386/i386/ucode.c

427

uint32_t

sys/arch/i386/i386/ucode.c

43

uint32_t update_revision;

sys/arch/i386/i386/ucode.c

430

uint32_t eax, ebx, ecx, edx;

sys/arch/i386/i386/ucode.c

44

uint32_t date;

sys/arch/i386/i386/ucode.c

45

uint32_t processor_sig;

sys/arch/i386/i386/ucode.c

46

uint32_t checksum;

sys/arch/i386/i386/ucode.c

47

uint32_t loader_rev;

sys/arch/i386/i386/ucode.c

48

uint32_t processor_flags;

sys/arch/i386/i386/ucode.c

49

uint32_t data_size;

sys/arch/i386/i386/ucode.c

50

uint32_t total_size;

sys/arch/i386/i386/ucode.c

51

uint32_t reserved1;

sys/arch/i386/i386/ucode.c

52

uint32_t min_runtime_update_rev;

sys/arch/i386/i386/ucode.c

53

uint32_t reserved2;

sys/arch/i386/i386/ucode.c

57

uint32_t ext_sig_count;

sys/arch/i386/i386/ucode.c

58

uint32_t checksum;

sys/arch/i386/i386/ucode.c

59

uint32_t reserved[3];

sys/arch/i386/i386/ucode.c

63

uint32_t processor_sig;

sys/arch/i386/i386/ucode.c

64

uint32_t processor_flags;

sys/arch/i386/i386/ucode.c

65

uint32_t checksum;

sys/arch/i386/i386/ucode.c

82

cpu_ucode_intel_find(char *, size_t, uint32_t);

sys/arch/i386/i386/ucode.c

84

int cpu_ucode_intel_match(struct intel_ucode_header *, uint32_t, uint32_t,

sys/arch/i386/i386/ucode.c

85

uint32_t);

sys/arch/i386/i386/ucode.c

86

uint32_t cpu_ucode_intel_rev(void);

sys/arch/i386/i386/vm_machdep.c

96

i386_set_threadbase(p2, (uint32_t)tcb, TSEG_GS);

sys/arch/i386/include/biosvar.h

132

uint32_t type; /* Type of block */

sys/arch/i386/include/biosvar.h

156

uint32_t checksum; /* Checksum for drive */

sys/arch/i386/include/biosvar.h

159

uint32_t flags;

sys/arch/i386/include/biosvar.h

187

uint32_t pci_chars; /* Characteristics (%eax) */

sys/arch/i386/include/biosvar.h

188

uint32_t pci_rev; /* BCD Revision (%ebx) */

sys/arch/i386/include/biosvar.h

189

uint32_t pci_entry32; /* PM entry point for PCI BIOS */

sys/arch/i386/include/biosvar.h

190

uint32_t pci_lastbus; /* Number of last PCI bus */

sys/arch/i386/include/biosvar.h

232

uint32_t fb_height;

sys/arch/i386/include/biosvar.h

233

uint32_t fb_width;

sys/arch/i386/include/biosvar.h

234

uint32_t fb_pixpsl; /* pixels per scan line */

sys/arch/i386/include/biosvar.h

235

uint32_t fb_red_mask;

sys/arch/i386/include/biosvar.h

236

uint32_t fb_green_mask;

sys/arch/i386/include/biosvar.h

237

uint32_t fb_blue_mask;

sys/arch/i386/include/biosvar.h

238

uint32_t fb_reserved_mask;

sys/arch/i386/include/biosvar.h

255

uint32_t biosr_ax;

sys/arch/i386/include/biosvar.h

256

uint32_t biosr_cx;

sys/arch/i386/include/biosvar.h

257

uint32_t biosr_dx;

sys/arch/i386/include/biosvar.h

258

uint32_t biosr_bx;

sys/arch/i386/include/biosvar.h

259

uint32_t biosr_bp;

sys/arch/i386/include/biosvar.h

260

uint32_t biosr_si;

sys/arch/i386/include/biosvar.h

261

uint32_t biosr_di;

sys/arch/i386/include/biosvar.h

262

uint32_t biosr_ds;

sys/arch/i386/include/biosvar.h

263

uint32_t biosr_es;

sys/arch/i386/include/biosvar.h

292

int bios32_service(uint32_t, bios32_entry_t, bios32_entry_info_t);

sys/arch/i386/include/biosvar.h

72

uint32_t entry; /* initialization entry point */

sys/arch/i386/include/biosvar.h

82

uint32_t signature; /* 00: signature "_32_" */

sys/arch/i386/include/biosvar.h

83

uint32_t entry; /* 04: entry point */

sys/arch/i386/include/biosvar.h

92

uint32_t bei_base;

sys/arch/i386/include/biosvar.h

93

uint32_t bei_size;

sys/arch/i386/include/biosvar.h

94

uint32_t bei_entry;

sys/arch/i386/include/biosvar.h

99

uint32_t offset;

sys/arch/i386/include/cpu_full.h

41

uint32_t cif_tramp_stack[(PAGE_SIZE / 4

sys/arch/i386/include/cpu_full.h

42

- offsetof(struct cpu_info, ci_PAGEALIGN)) / sizeof(uint32_t)];

sys/arch/i386/include/cpu_full.h

43

uint32_t cif_nmi_stack[(3 * PAGE_SIZE / 4) / sizeof(uint32_t)];

sys/arch/i386/include/ieee.h

92

(a)[0] = (uint32_t)(p)->ext_fracl; \

sys/arch/i386/include/ieee.h

93

(a)[1] = (uint32_t)(p)->ext_frach; \

sys/arch/i386/include/npx.h

120

uint32_t sv_ex_sw; /* saved SW from last exception */

sys/arch/i386/include/npx.h

121

uint32_t sv_ex_tw; /* saved TW from last exception */

sys/arch/i386/include/npx.h

151

extern uint32_t fpu_mxcsr_mask;

sys/arch/i386/include/npx.h

92

uint32_t en_fip; /* FPU Instruction Pointer */

sys/arch/i386/include/npx.h

95

/*16*/ uint32_t en_foo; /* FPU Data pointer */

sys/arch/i386/include/npx.h

98

uint32_t en_mxcsr; /* MXCSR Register State */

sys/arch/i386/include/npx.h

99

uint32_t en_mxcsr_mask; /* Mask for valid MXCSR bits (may be 0) */

sys/arch/i386/include/smbiosvar.h

150

uint32_t charext;

sys/arch/i386/include/smbiosvar.h

229

uint32_t cpu_id_eax;

sys/arch/i386/include/smbiosvar.h

230

uint32_t cpu_id_edx;

sys/arch/i386/include/smbiosvar.h

55

uint32_t sig; /* "_SM_" */

sys/arch/i386/include/smbiosvar.h

66

uint32_t addr; /* Structure table address */

sys/arch/i386/include/smbiosvar.h

80

uint32_t size; /* Structure table maximum size */

sys/arch/i386/include/smbiosvar.h

93

uint32_t cookie;

sys/arch/i386/include/sysarch.h

22

uint32_t i386_get_threadbase(struct proc *, int);

sys/arch/i386/include/sysarch.h

23

int i386_set_threadbase(struct proc *, uint32_t, int);

sys/arch/i386/include/tcb.h

29

i386_set_threadbase(p, (uint32_t)(addr), TSEG_GS)

sys/arch/i386/isa/clock.c

123

uint32_t i8254_lastcount;

sys/arch/i386/isa/clock.c

124

uint32_t i8254_offset;

sys/arch/i386/isa/npx.c

876

uint32_t cw;

sys/arch/i386/isa/npx.c

98

uint32_t fpu_mxcsr_mask;

sys/arch/i386/pci/glxsb.c

145

uint32_t dma_paddr;

sys/arch/i386/pci/glxsb.c

148

uint32_t ses_key[4];

sys/arch/i386/pci/glxsb.c

196

int glxsb_crypto_newsession(uint32_t *, struct cryptoini *);

sys/arch/i386/pci/glxsb.c

199

static __inline void glxsb_aes(struct glxsb_softc *, uint32_t, uint32_t,

sys/arch/i386/pci/glxsb.c

200

uint32_t, void *, int, void *);

sys/arch/i386/pci/glxsb.c

231

uint32_t intr;

sys/arch/i386/pci/glxsb.c

310

uint32_t status, value;

sys/arch/i386/pci/glxsb.c

355

glxsb_crypto_newsession(uint32_t *sidp, struct cryptoini *cri)

sys/arch/i386/pci/glxsb.c

514

uint32_t sid = ((uint32_t)tid) & 0xffffffff;

sys/arch/i386/pci/glxsb.c

551

glxsb_aes(struct glxsb_softc *sc, uint32_t control, uint32_t psrc,

sys/arch/i386/pci/glxsb.c

552

uint32_t pdst, void *key, int len, void *iv)

sys/arch/i386/pci/glxsb.c

554

uint32_t status;

sys/arch/i386/pci/glxsb.c

650

uint32_t op_psrc, op_pdst;

sys/arch/i386/pci/glxsb.c

655

uint32_t control;

sys/arch/i386/pci/pciide_gcsc_reg.h

66

static const uint32_t gcsc_pio_timings[] = {

sys/arch/i386/pci/pciide_gcsc_reg.h

74

static const uint32_t gcsc_mdma_timings[] = {

sys/arch/i386/pci/pciide_gcsc_reg.h

80

static const uint32_t gcsc_udma_timings[] = {

sys/arch/i386/pci/vga_post.c

111

vm86_emu_outl(struct x86emu *emu, uint16_t port, uint32_t val)

sys/arch/i386/pci/vga_post.c

49

uint32_t initial_eax;

sys/arch/i386/pci/vga_post.c

80

static uint32_t

sys/arch/i386/stand/libsa/exec_i386.c

159

uint32_t model, family, stepping;

sys/arch/i386/stand/libsa/exec_i386.c

160

uint32_t dummy, signature;

sys/arch/i386/stand/libsa/exec_i386.c

161

uint32_t vendor[4];

sys/arch/i386/stand/libsa/machdep.c

101

if (memcmp(&ebx, &vmm_hv_signature[0], sizeof(uint32_t)) == 0 &&

sys/arch/i386/stand/libsa/machdep.c

102

memcmp(&ecx, &vmm_hv_signature[4], sizeof(uint32_t)) == 0 &&

sys/arch/i386/stand/libsa/machdep.c

103

memcmp(&edx, &vmm_hv_signature[8], sizeof(uint32_t)) == 0)

sys/arch/i386/stand/libsa/machdep.c

57

uint32_t dummy, ebx, ecx, edx;

sys/arch/i386/stand/libsa/mdrandom.c

35

uint32_t hi, lo, acc;

sys/arch/i386/stand/libsa/pxe.h

198

uint32_t Reserved[2];

sys/arch/i386/stand/libsa/pxe.h

258

uint32_t XmitGoodFrames; /* Number of successful

sys/arch/i386/stand/libsa/pxe.h

260

uint32_t RcvGoodFrames; /* Number of good frames

sys/arch/i386/stand/libsa/pxe.h

262

uint32_t RcvCRCErrors; /* Number of frames with

sys/arch/i386/stand/libsa/pxe.h

264

uint32_t RcvResourceErrors; /* Number of frames dropped */

sys/arch/i386/stand/libsa/pxe.h

310

uint32_t EISA_Dev_ID;

sys/arch/i386/stand/libsa/pxe.h

323

uint32_t LinkSpeed; /* Defined in NDIS 2.0 spec */

sys/arch/i386/stand/libsa/pxe.h

324

uint32_t ServiceFlags; /* Defined in NDIS 2.0 spec */

sys/arch/i386/stand/libsa/pxe.h

325

uint32_t Reserved[4]; /* must be 0 */

sys/arch/i386/stand/libsa/pxe.h

390

uint32_t BufferSize;

sys/arch/i386/stand/libsa/pxe.h

407

uint32_t FileSize;

sys/arch/i386/stand/libsa/pxe.h

477

uint32_t ident; /* random number chosen by client */

sys/arch/i386/stand/libsa/pxe.h

505

uint32_t flags; /* bootp flags/opcodes */

sys/arch/i386/stand/libsa/pxe.h

57

uint32_t Phy_Addr;

sys/arch/i386/stand/libsa/pxe.h

63

typedef uint32_t IP4_t;

sys/arch/i386/stand/libsa/pxe.h

64

typedef uint32_t ADDR32_t;

sys/arch/i386/stand/libsa/pxe.h

78

uint32_t PMOffset; /* Protected mode entry */

sys/arch/landisk/dev/obio.c

370

uint32_t obio_iomem_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset);

sys/arch/landisk/dev/obio.c

376

bus_size_t offset, uint32_t *addr, bus_size_t count);

sys/arch/landisk/dev/obio.c

386

bus_size_t offset, uint32_t *addr, bus_size_t count);

sys/arch/landisk/dev/obio.c

396

uint32_t value);

sys/arch/landisk/dev/obio.c

402

bus_size_t offset, const uint32_t *addr, bus_size_t count);

sys/arch/landisk/dev/obio.c

412

bus_size_t offset, const uint32_t *addr, bus_size_t count);

sys/arch/landisk/dev/obio.c

422

uint32_t val, bus_size_t count);

sys/arch/landisk/dev/obio.c

428

bus_size_t offset, uint32_t val, bus_size_t count);

sys/arch/landisk/dev/obio.c

573

uint32_t

sys/arch/landisk/dev/obio.c

576

return *(volatile uint32_t *)(bsh + offset);

sys/arch/landisk/dev/obio.c

603

bus_size_t offset, uint32_t *addr, bus_size_t count)

sys/arch/landisk/dev/obio.c

605

volatile uint32_t *p = (void *)(bsh + offset);

sys/arch/landisk/dev/obio.c

629

volatile uint32_t *p = (void *)(bsh + offset);

sys/arch/landisk/dev/obio.c

633

*(uint32_t *)addr = *p;

sys/arch/landisk/dev/obio.c

662

bus_size_t offset, uint32_t *addr, bus_size_t count)

sys/arch/landisk/dev/obio.c

664

volatile uint32_t *p = (void *)(bsh + offset);

sys/arch/landisk/dev/obio.c

688

volatile uint32_t *p = (void *)(bsh + offset);

sys/arch/landisk/dev/obio.c

692

*(uint32_t *)addr = *p++;

sys/arch/landisk/dev/obio.c

714

uint32_t value)

sys/arch/landisk/dev/obio.c

716

*(volatile uint32_t *)(bsh + offset) = value;

sys/arch/landisk/dev/obio.c

743

bus_size_t offset, const uint32_t *addr, bus_size_t count)

sys/arch/landisk/dev/obio.c

745

volatile uint32_t *p = (void *)(bsh + offset);

sys/arch/landisk/dev/obio.c

769

volatile uint32_t *p = (void *)(bsh + offset);

sys/arch/landisk/dev/obio.c

773

*p = *(uint32_t *)addr;

sys/arch/landisk/dev/obio.c

802

bus_size_t offset, const uint32_t *addr, bus_size_t count)

sys/arch/landisk/dev/obio.c

804

volatile uint32_t *p = (void *)(bsh + offset);

sys/arch/landisk/dev/obio.c

828

volatile uint32_t *p = (void *)(bsh + offset);

sys/arch/landisk/dev/obio.c

832

*p++ = *(uint32_t *)addr;

sys/arch/landisk/dev/obio.c

861

bus_size_t offset, uint32_t val, bus_size_t count)

sys/arch/landisk/dev/obio.c

863

volatile uint32_t *p = (void *)(bsh + offset);

sys/arch/landisk/dev/obio.c

894

bus_size_t offset, uint32_t val, bus_size_t count)

sys/arch/landisk/dev/obio.c

896

volatile uint32_t *addr = (void *)(bsh + offset);

sys/arch/landisk/dev/obio.c

947

volatile uint32_t *addr1 = (void *)(h1 + o1);

sys/arch/landisk/dev/obio.c

948

volatile uint32_t *addr2 = (void *)(h2 + o2);

sys/arch/landisk/include/bus.h

105

uint32_t (*bs_r_4)(void *, bus_space_handle_t,

sys/arch/landisk/include/bus.h

116

bus_size_t, uint32_t *, bus_size_t);

sys/arch/landisk/include/bus.h

133

bus_size_t, uint32_t *, bus_size_t);

sys/arch/landisk/include/bus.h

150

bus_size_t, uint32_t);

sys/arch/landisk/include/bus.h

160

bus_size_t, const uint32_t *, bus_size_t);

sys/arch/landisk/include/bus.h

177

bus_size_t, const uint32_t *, bus_size_t);

sys/arch/landisk/include/bus.h

194

bus_size_t, uint32_t, bus_size_t);

sys/arch/landisk/include/bus.h

204

bus_size_t, uint32_t, bus_size_t);

sys/arch/landisk/include/bus.h

290

#define bus_space_read_4(t, h, o) __bs_rs(4,uint32_t,(t),(h),(o))

sys/arch/landisk/include/bus.h

302

__bs_nonsingle(rm,4,uint32_t,(t),(h),(o),(a),(c))

sys/arch/landisk/include/bus.h

309

__bs_nonsingle(rrm,4,uint32_t,(t),(h),(o),(a),(c))

sys/arch/landisk/include/bus.h

322

__bs_nonsingle(rr,4,uint32_t,(t),(h),(o),(a),(c))

sys/arch/landisk/include/bus.h

329

__bs_nonsingle(rrr,4,uint32_t,(t),(h),(o),(a),(c))

sys/arch/landisk/include/bus.h

339

#define bus_space_write_4(t, h, o, v) __bs_ws(4,uint32_t,(t),(h),(o),(v))

sys/arch/landisk/include/bus.h

351

__bs_nonsingle(wm,4,uint32_t,(t),(h),(o),(a),(c))

sys/arch/landisk/include/bus.h

358

__bs_nonsingle(wrm,4,uint32_t,(t),(h),(o),(a),(c))

sys/arch/landisk/include/bus.h

371

__bs_nonsingle(wr,4,uint32_t,(t),(h),(o),(a),(c))

sys/arch/landisk/include/bus.h

378

__bs_nonsingle(wrr,4,uint32_t,(t),(h),(o),(a),(c))

sys/arch/landisk/include/bus.h

391

__bs_set(sm,4,uint32_t,(t),(h),(o),(v),(c))

sys/arch/landisk/include/bus.h

404

__bs_set(sr,4,uint32_t,(t),(h),(o),(v),(c))

sys/arch/landisk/include/bus.h

417

__bs_copy(4, uint32_t, (t), (h1), (o1), (h2), (o2), (c))

sys/arch/landisk/landisk/machdep.c

258

(void)*(volatile uint32_t *)0x80000001; /* CPU shutdown */

sys/arch/landisk/stand/boot/delay.c

112

uint32_t

sys/arch/landisk/stand/boot/delay.c

122

uint32_t base, now;

sys/arch/landisk/stand/boot/getsecs.c

127

rtc_read(uint32_t addr)

sys/arch/landisk/stand/boot/getsecs.c

165

uint32_t sec, min, hour, day;

sys/arch/landisk/stand/boot/getsecs.c

167

uint32_t mon, year;

sys/arch/landisk/stand/boot/getsecs.c

195

printf("getsecs: secs = %d\n", (uint32_t)secs);

sys/arch/landisk/stand/boot/getsecs.c

48

uint8_t rtc_read(uint32_t addr);

sys/arch/landisk/stand/boot/libsa.h

24

int readsects(int dev, uint32_t lba, void *buf, size_t size);

sys/arch/landisk/stand/xxboot/boot1.c

102

if (*(uint32_t *)(LOADADDRESS + 4) != 0x20041110)

sys/arch/landisk/stand/xxboot/boot1.c

42

static uint32_t bios_sector;

sys/arch/landisk/stand/xxboot/boot1.c

44

const char *boot1(uint32_t *);

sys/arch/landisk/stand/xxboot/boot1.c

49

int readsects(int dev, uint32_t lba, void *buf, size_t size);

sys/arch/landisk/stand/xxboot/boot1.c

65

boot1(uint32_t *sector)

sys/arch/loongson/dev/bonito.c

1048

uint32_t pcimap;

sys/arch/loongson/dev/bonito.c

1150

uint32_t reg;

sys/arch/loongson/dev/bonito.c

224

uint32_t reg;

sys/arch/loongson/dev/bonito.c

502

uint32_t clear, set;

sys/arch/loongson/dev/bonito.c

579

uint32_t

sys/arch/loongson/dev/bonito.c

580

bonito_intr_2e(uint32_t hwpend, struct trapframe *frame)

sys/arch/loongson/dev/bonito.c

636

uint32_t

sys/arch/loongson/dev/bonito.c

637

bonito_intr_2f(uint32_t hwpend, struct trapframe *frame)

sys/arch/loongson/dev/bonito.c

98

uint32_t bonito_intr_2e(uint32_t, struct trapframe *);

sys/arch/loongson/dev/bonito.c

99

uint32_t bonito_intr_2f(uint32_t, struct trapframe *);

sys/arch/loongson/dev/bonitovar.h

43

uint32_t bc_gpioIE;

sys/arch/loongson/dev/bonitovar.h

44

uint32_t bc_intEdge;

sys/arch/loongson/dev/bonitovar.h

45

uint32_t bc_intSteer;

sys/arch/loongson/dev/bonitovar.h

46

uint32_t bc_intPol;

sys/arch/loongson/dev/glx.c

134

lo = (uint32_t)pci_conf_read(glxbase_pc, glxbase_tag, PCI_MSR_LO32);

sys/arch/loongson/dev/glx.c

135

hi = (uint32_t)pci_conf_read(glxbase_pc, glxbase_tag, PCI_MSR_HI32);

sys/arch/loongson/dev/glx.c

152

pci_conf_write(glxbase_pc, glxbase_tag, PCI_MSR_LO32, (uint32_t)value);

sys/arch/loongson/dev/glx.c

514

msr = (uint32_t)data & 0xfffffff0;

sys/arch/loongson/dev/glx.c

526

wrmsr(IDE_CFG, (uint32_t)data);

sys/arch/loongson/dev/glx.c

529

wrmsr(IDE_DTC, (uint32_t)data);

sys/arch/loongson/dev/glx.c

532

wrmsr(IDE_ETC, (uint32_t)data);

sys/arch/loongson/dev/radeonfb.c

126

int *, int *, uint32_t *);

sys/arch/loongson/dev/radeonfb.c

157

int radeonfb_erasecols(void *, int, int, int, uint32_t);

sys/arch/loongson/dev/radeonfb.c

159

int radeonfb_eraserows(void *, int, int, uint32_t);

sys/arch/loongson/dev/radeonfb.c

256

void **cookiep, int *curxp, int *curyp, uint32_t *attrp)

sys/arch/loongson/dev/radeonfb.c

438

radeonfb_erasecols(void *cookie, int row, int col, int num, uint32_t attr)

sys/arch/loongson/dev/radeonfb.c

473

radeonfb_eraserows(void *cookie, int row, int num, uint32_t attr)

sys/arch/loongson/dev/radeonfb.c

539

uint32_t gmc;

sys/arch/loongson/dev/radeonfb.c

540

uint32_t dir;

sys/arch/loongson/dev/radeonfb.c

588

uint32_t gmc;

sys/arch/loongson/dev/radeonfb.c

691

uint32_t defattr;

sys/arch/loongson/dev/sisfb.c

260

int *curxp, int *curyp, uint32_t *attrp)

sys/arch/loongson/dev/sisfb.c

601

uint32_t defattr;

sys/arch/loongson/dev/sisfb.c

87

int *, uint32_t *);

sys/arch/loongson/dev/smfb.c

112

int *, uint32_t *);

sys/arch/loongson/dev/smfb.c

140

int smfb_erasecols(void *, int, int, int, uint32_t);

sys/arch/loongson/dev/smfb.c

141

int smfb_eraserows(void *, int, int, uint32_t);

sys/arch/loongson/dev/smfb.c

244

int *curxp, int *curyp, uint32_t *attrp)

sys/arch/loongson/dev/smfb.c

491

uint32_t dir;

sys/arch/loongson/dev/smfb.c

568

smfb_erasecols(void *cookie, int row, int col, int num, uint32_t attr)

sys/arch/loongson/dev/smfb.c

588

smfb_eraserows(void *cookie, int row, int num, uint32_t attr)

sys/arch/loongson/dev/smfb.c

616

uint32_t reg;

sys/arch/loongson/dev/smfb.c

684

uint32_t defattr;

sys/arch/loongson/dev/voyager.c

211

uint32_t isr, imr, mask, bitno;

sys/arch/loongson/dev/voyager.c

240

uint32_t imr;

sys/arch/loongson/dev/voyager.c

372

uint32_t control, value;

sys/arch/loongson/include/autoconf.h

117

#define REGVAL32(x) *((volatile uint32_t *)PHYS_TO_XKPHYS((x), CCA_NC))

sys/arch/loongson/include/bus.h

299

uint32_t generic_space_read_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);

sys/arch/loongson/include/bus.h

308

uint32_t);

sys/arch/loongson/include/intr.h

158

extern uint32_t idle_mask;

sys/arch/loongson/include/intr.h

161

void set_intr(int, uint32_t, uint32_t(*)(uint32_t, struct trapframe *));

sys/arch/loongson/include/intr.h

163

uint32_t updateimask(uint32_t);

sys/arch/loongson/include/intr.h

167

extern uint32_t ipi_mask;

sys/arch/loongson/include/pmon.h

102

uint32_t node;

sys/arch/loongson/include/pmon.h

103

uint32_t type;

sys/arch/loongson/include/pmon.h

114

uint32_t size;

sys/arch/loongson/include/pmon.h

118

uint32_t nentries;

sys/arch/loongson/include/pmon.h

119

uint32_t mem_freq;

sys/arch/loongson/include/pmon.h

125

uint32_t prid; /* cop0 PrID */

sys/arch/loongson/include/pmon.h

126

uint32_t cputype;

sys/arch/loongson/include/pmon.h

134

uint32_t node; /* total number of NUMA nodes */

sys/arch/loongson/include/pmon.h

137

uint32_t speed;

sys/arch/loongson/include/pmon.h

138

uint32_t ncpus;

sys/arch/loongson/include/pmon.h

143

uint32_t ccnuma_smp;

sys/arch/loongson/include/pmon.h

144

uint32_t double_channel;

sys/arch/loongson/include/pmon.h

152

uint32_t vendor; /* not filled */

sys/arch/loongson/include/pmon.h

153

uint32_t device; /* not filled */

sys/arch/loongson/include/pmon.h

154

uint32_t pic_type;

sys/arch/loongson/include/pmon.h

159

uint32_t node;

sys/arch/loongson/include/pmon.h

180

uint32_t flags;

sys/arch/loongson/include/pmon.h

185

uint32_t type;

sys/arch/loongson/include/pmon.h

191

uint32_t nentries;

sys/arch/loongson/include/pmon.h

29

typedef uint32_t pmon_size_t;

sys/arch/loongson/include/pmon.h

47

void pmon_init(int32_t, int32_t, int32_t, int32_t, uint32_t);

sys/arch/loongson/loongson/bus_space.c

118

volatile uint32_t *addr = (volatile uint32_t *)(h + o);

sys/arch/loongson/loongson/bus_space.c

121

*(uint32_t *)buf = *addr;

sys/arch/loongson/loongson/bus_space.c

130

volatile uint32_t *addr = (volatile uint32_t *)(h + o);

sys/arch/loongson/loongson/bus_space.c

133

*addr = *(uint32_t *)buf;

sys/arch/loongson/loongson/bus_space.c

50

uint32_t

sys/arch/loongson/loongson/bus_space.c

53

return *(volatile uint32_t *)(h + o);

sys/arch/loongson/loongson/bus_space.c

78

uint32_t v)

sys/arch/loongson/loongson/bus_space.c

80

*(volatile uint32_t *)(h + o) = v;

sys/arch/loongson/loongson/generic2e_machdep.c

238

uint32_t

sys/arch/loongson/loongson/generic2e_machdep.c

239

generic2e_isa_intr(uint32_t hwpend, struct trapframe *frame)

sys/arch/loongson/loongson/generic2e_machdep.c

95

uint32_t generic2e_isa_intr(uint32_t, struct trapframe *);

sys/arch/loongson/loongson/generic3a_machdep.c

167

uint32_t rs780e_imask;

sys/arch/loongson/loongson/generic3a_machdep.c

192

uint32_t boot_cpuid = loongson3_get_cpuid();

sys/arch/loongson/loongson/generic3a_machdep.c

268

uint32_t boot_cpu = loongson3_get_cpuid();

sys/arch/loongson/loongson/generic3a_machdep.c

269

uint32_t cpu, unit = 0;

sys/arch/loongson/loongson/generic3a_machdep.c

350

uint32_t

sys/arch/loongson/loongson/generic3a_machdep.c

351

generic3a_ipi_intr(uint32_t hwpend, struct trapframe *frame)

sys/arch/loongson/loongson/generic3a_machdep.c

482

rs780e_set_imask(uint32_t new_imask)

sys/arch/loongson/loongson/generic3a_machdep.c

72

uint32_t generic3a_ipi_intr(uint32_t, struct trapframe *);

sys/arch/loongson/loongson/generic3a_machdep.c

89

void rs780e_set_imask(uint32_t);

sys/arch/loongson/loongson/loongson2_machdep.c

276

uint32_t step, val;

sys/arch/loongson/loongson/loongson2_machdep.c

288

uint32_t step, val;

sys/arch/loongson/loongson/loongson3_intr.c

125

loongson3_prop_imask(uint32_t *imask)

sys/arch/loongson/loongson/loongson3_intr.c

139

uint32_t ipls[LS3_IRQ_NUM];

sys/arch/loongson/loongson/loongson3_intr.c

140

uint32_t ipls_ht[LS3_HT_IRQ_NUM];

sys/arch/loongson/loongson/loongson3_intr.c

34

uint32_t loongson3_ht_intr(uint32_t, struct trapframe *);

sys/arch/loongson/loongson/loongson3_intr.c

35

uint32_t loongson3_intr(uint32_t, struct trapframe *);

sys/arch/loongson/loongson/loongson3_intr.c

366

uint32_t

sys/arch/loongson/loongson/loongson3_intr.c

367

loongson3_intr(uint32_t pending, struct trapframe *frame)

sys/arch/loongson/loongson/loongson3_intr.c

371

uint32_t imr, isr, mask;

sys/arch/loongson/loongson/loongson3_intr.c

439

uint32_t

sys/arch/loongson/loongson/loongson3_intr.c

440

loongson3_ht_intr(uint32_t pending, struct trapframe *frame)

sys/arch/loongson/loongson/loongson3_intr.c

444

uint32_t imr, isr, mask;

sys/arch/loongson/loongson/loongson3_intr.c

48

uint32_t loongson3_ht_imask[NIPLS];

sys/arch/loongson/loongson/loongson3_intr.c

49

uint32_t loongson3_ht_intem;

sys/arch/loongson/loongson/loongson3_intr.c

52

uint32_t loongson3_imask[NIPLS];

sys/arch/loongson/loongson/loongson3_intr.c

53

uint32_t loongson3_intem;

sys/arch/loongson/loongson/loongson3_intr.c

56

next_irq(uint32_t *isr)

sys/arch/loongson/loongson/loongson3_intr.c

59

uint32_t irq;

sys/arch/loongson/loongson/loongson3_intr.c

79

uint32_t boot_core = LS3_COREID(loongson3_get_cpuid());

sys/arch/loongson/loongson/machdep.c

120

uint32_t ipi_mask;

sys/arch/loongson/loongson/machdep.c

359

uint32_t i, ncpus, seg = 0;

sys/arch/loongson/loongson/machdep.c

512

uint32_t prid;

sys/arch/loongson/loongson/pmon.c

34

uint32_t prid)

sys/arch/loongson/loongson/yeeloong_machdep.c

341

uint32_t

sys/arch/loongson/loongson/yeeloong_machdep.c

342

lemote_isa_intr(uint32_t hwpend, struct trapframe *frame)

sys/arch/loongson/loongson/yeeloong_machdep.c

81

uint32_t lemote_isa_intr(uint32_t, struct trapframe *);

sys/arch/luna88k/dev/if_le.c

179

volatile struct { uint32_t ctl; } *ds1220;

sys/arch/luna88k/dev/lunafb.c

114

int om_erasecols(void *, int, int, int, uint32_t);

sys/arch/luna88k/dev/lunafb.c

115

int om_eraserows(void *, int, int, uint32_t);

sys/arch/luna88k/dev/lunafb.c

134

void **, int *, int *, uint32_t *);

sys/arch/luna88k/dev/lunafb.c

221

uint32_t defattr;

sys/arch/luna88k/dev/lunafb.c

418

*(volatile uint32_t *)max = 0x5a5a5a5a;

sys/arch/luna88k/dev/lunafb.c

479

int *curxp, int *curyp, uint32_t *attrp)

sys/arch/luna88k/dev/omrasops.c

161

om4_putchar(void *cookie, int row, int startcol, u_int uc, uint32_t attr)

sys/arch/luna88k/dev/omrasops.c

291

om_erasecols(void *cookie, int row, int col, int num, uint32_t attr)

sys/arch/luna88k/dev/omrasops.c

315

om_eraserows(void *cookie, int row, int num, uint32_t attr)

sys/arch/luna88k/dev/omrasops.c

59

int om_erasecols(void *, int, int, int, uint32_t);

sys/arch/luna88k/dev/omrasops.c

60

int om_eraserows(void *, int, int, uint32_t);

sys/arch/luna88k/dev/omrasops.c

62

int om1_putchar(void *, int, int, u_int, uint32_t);

sys/arch/luna88k/dev/omrasops.c

64

int om4_putchar(void *, int, int, u_int, uint32_t);

sys/arch/luna88k/dev/omrasops.c

77

int rasops_pack_cattr(void *, int, int, int, uint32_t *);

sys/arch/luna88k/dev/omrasops.c

78

int rasops_pack_mattr(void *, int, int, int, uint32_t *);

sys/arch/luna88k/dev/omrasops.c

96

om1_putchar(void *cookie, int row, int startcol, u_int uc, uint32_t attr)

sys/arch/luna88k/dev/xp.c

75

uint32_t xp_debug = 0;

sys/arch/luna88k/luna88k/clock.c

173

*(volatile uint32_t *)(ci->ci_clock_ack) = ~0;

sys/arch/luna88k/luna88k/m8820x.c

106

volatile uint32_t* icmmuregs = (volatile uint32_t *)icmmu;

sys/arch/luna88k/luna88k/m8820x.c

107

volatile uint32_t* dcmmuregs = (volatile uint32_t *)dcmmu;

sys/arch/luna88k/luna88k/m8820x.c

99

m8820x_probe_cmmus(uint32_t icmmu, uint32_t dcmmu)

sys/arch/luna88k/luna88k/machdep.c

1178

*(volatile uint32_t *)ci->ci_intr_mask = set_value;

sys/arch/luna88k/luna88k/machdep.c

1196

uint32_t psr;

sys/arch/luna88k/luna88k/machdep.c

1213

uint32_t psr;

sys/arch/luna88k/luna88k/machdep.c

123

void luna88k_vector_init(uint32_t *, uint32_t *);

sys/arch/luna88k/luna88k/machdep.c

1237

*(volatile uint32_t *)ci->ci_swireg = ~0;

sys/arch/luna88k/luna88k/machdep.c

1255

*(volatile uint32_t *)ci->ci_swireg;

sys/arch/luna88k/luna88k/machdep.c

444

*((volatile uint32_t *)RESET_CPU_ALL) = 0;

sys/arch/luna88k/luna88k/machdep.c

648

static const uint32_t clock_ack[] = {

sys/arch/luna88k/luna88k/machdep.c

667

static const uint32_t intr_mask[] = {

sys/arch/luna88k/luna88k/machdep.c

675

static const uint32_t swi_reg[] = {

sys/arch/luna88k/luna88k/machdep.c

802

uint32_t cur_isr;

sys/arch/luna88k/luna88k/machdep.c

806

cur_isr = *(volatile uint32_t *)ci->ci_intr_mask;

sys/arch/luna88k/luna88k/machdep.c

834

cur_isr = *(volatile uint32_t *)ci->ci_intr_mask;

sys/arch/luna88k/luna88k/machdep.c

880

cur_isr = *(volatile uint32_t *)ci->ci_intr_mask;

sys/arch/luna88k/luna88k/machdep.c

951

luna88k_vector_init(uint32_t *bootvbr, uint32_t *vectors)

sys/arch/luna88k/luna88k/machdep.c

953

extern vaddr_t vector_init(uint32_t *, uint32_t *, int); /* gross */

sys/arch/luna88k/luna88k/machdep.c

967

vector_init((uint32_t *)kernel_vbr, vectors, 0);

sys/arch/luna88k/luna88k/machdep.c

988

*(volatile uint32_t *)INT_ST_MASK0 = 0;

sys/arch/luna88k/luna88k/machdep.c

989

*(volatile uint32_t *)INT_ST_MASK1 = 0;

sys/arch/luna88k/luna88k/machdep.c

990

*(volatile uint32_t *)INT_ST_MASK2 = 0;

sys/arch/luna88k/luna88k/machdep.c

991

*(volatile uint32_t *)INT_ST_MASK3 = 0;

sys/arch/luna88k/luna88k/machdep.c

994

*(volatile uint32_t *)SOFT_INT0;

sys/arch/luna88k/luna88k/machdep.c

995

*(volatile uint32_t *)SOFT_INT1;

sys/arch/luna88k/luna88k/machdep.c

996

*(volatile uint32_t *)SOFT_INT2;

sys/arch/luna88k/luna88k/machdep.c

997

*(volatile uint32_t *)SOFT_INT3;

sys/arch/luna88k/stand/boot/bmd.c

283

volatile uint32_t *bmd_rfcnt = (volatile uint32_t *)BMAP_RFCNT;

sys/arch/luna88k/stand/boot/bmd.c

337

volatile uint32_t *bmd_rfcnt = (volatile uint32_t *)BMAP_RFCNT;

sys/arch/luna88k/stand/boot/bmd.c

94

uint32_t u;

sys/arch/luna88k/stand/boot/exec.c

105

cpu_boot = (void (*)(uint32_t, uint32_t, uint32_t, uint32_t))

sys/arch/luna88k/stand/boot/exec.c

106

(uint32_t)marks[MARK_ENTRY];

sys/arch/luna88k/stand/boot/exec.c

82

void (*cpu_boot)(uint32_t, uint32_t, uint32_t, uint32_t);

sys/arch/luna88k/stand/boot/exec.c

83

uint32_t cpu_bootarg1;

sys/arch/luna88k/stand/boot/exec.c

84

uint32_t cpu_bootarg2;

sys/arch/luna88k/stand/boot/exec.c

85

uint32_t cpu_bootarg3;

sys/arch/luna88k/stand/boot/exec.c

86

uint32_t cpu_bootarg4;

sys/arch/luna88k/stand/boot/exec.c

92

printf("entry = 0x%lx\n", (uint32_t)marks[MARK_ENTRY]);

sys/arch/luna88k/stand/boot/exec.c

93

printf("ssym = 0x%lx\n", (uint32_t)marks[MARK_SYM]);

sys/arch/luna88k/stand/boot/exec.c

94

printf("esym = 0x%lx\n", (uint32_t)marks[MARK_END]);

sys/arch/luna88k/stand/boot/exec.c

98

cpu_bootarg2 = (uint32_t)marks[MARK_END];

sys/arch/luna88k/stand/boot/fault.c

111

set_vbr((uint32_t)&vector_page);

sys/arch/luna88k/stand/boot/fault.c

120

if ((uint32_t)addr & 1)

sys/arch/luna88k/stand/boot/fault.c

128

if ((uint32_t)addr & 3)

sys/arch/luna88k/stand/boot/fault.c

131

(void)*(volatile uint32_t *)addr;

sys/arch/luna88k/stand/boot/fault.c

37

static uint32_t badaddr_psr;

sys/arch/luna88k/stand/boot/fault.c

39

static uint32_t prom_vbr;

sys/arch/luna88k/stand/boot/fault.c

40

static uint32_t vector_page[512 * 2] __attribute__ ((__aligned__(0x1000)));

sys/arch/luna88k/stand/boot/fault.c

42

static __inline__ uint32_t

sys/arch/luna88k/stand/boot/fault.c

45

uint32_t vbr;

sys/arch/luna88k/stand/boot/fault.c

51

set_vbr(uint32_t vbr)

sys/arch/luna88k/stand/boot/fault.c

72

static __inline__ uint32_t

sys/arch/luna88k/stand/boot/fault.c

73

br(uint32_t delta)

sys/arch/luna88k/stand/boot/fault.c

82

uint32_t *insn;

sys/arch/luna88k/stand/boot/fault.c

83

uint32_t br_insn;

sys/arch/luna88k/stand/boot/fault.c

88

br_insn = br(prom_vbr - (uint32_t)&vector_page - 4);

sys/arch/luna88k/stand/boot/fault.c

96

br((uint32_t)&libsa_fault_handler -

sys/arch/luna88k/stand/boot/fault.c

97

(uint32_t)&vector_page[3 * 2 + 1]);

sys/arch/luna88k/stand/boot/getsecs.c

67

volatile uint32_t *mclock =

sys/arch/luna88k/stand/boot/getsecs.c

68

(volatile uint32_t *)(NVRAM_ADDR + MK_NVRAM_SPACE);

sys/arch/luna88k/stand/boot/if_le.c

233

volatile struct { uint32_t ctl; } *ds1220;

sys/arch/luna88k/stand/boot/init_main.c

117

uint32_t bootdev;

sys/arch/luna88k/stand/boot/lance.c

260

uint32_t addr = (uint32_t)sc->sc_mem;

sys/arch/luna88k/stand/boot/lance.c

319

uint32_t addr;

sys/arch/luna88k/stand/boot/lance.c

338

addr = (uint32_t)lemem->lem_rmd;

sys/arch/luna88k/stand/boot/lance.c

343

addr = (uint32_t)lemem->lem_tmd;

sys/arch/luna88k/stand/boot/lance.c

349

addr = (uint32_t)lemem->lem_rbuf[i];

sys/arch/luna88k/stand/boot/lance.c

359

addr = (uint32_t)lemem->lem_tbuf[i];

sys/arch/luna88k/stand/boot/samachdep.h

100

extern volatile uint32_t tick;

sys/arch/luna88k/stand/boot/samachdep.h

63

extern uint32_t bootdev;

sys/arch/m88k/include/cpu.h

112

uint32_t (*ci_mp_atomic_begin)

sys/arch/m88k/include/cpu.h

115

(uint32_t psr, __cpu_simple_lock_t *lock, uint csr);

sys/arch/m88k/include/mmu.h

108

typedef uint32_t pt_entry_t;

sys/arch/m88k/include/mmu.h

163

typedef uint32_t batc_t;

sys/arch/m88k/include/mmu.h

79

typedef uint32_t apr_t;

sys/arch/m88k/include/mmu.h

93

typedef uint32_t sdt_entry_t;

sys/arch/m88k/include/pmap.h

71

int pmap_translation_info(pmap_t, vaddr_t, paddr_t *, uint32_t *);

sys/arch/m88k/m88k/db_trace.c

393

uint32_t instruction;

sys/arch/m88k/m88k/db_trace.c

466

uint32_t r31;

sys/arch/m88k/m88k/db_trace.c

467

uint32_t inst;

sys/arch/m88k/m88k/db_trace.c

597

for (instructions_to_search = (addr - check_addr) / sizeof(uint32_t);

sys/arch/m88k/m88k/db_trace.c

599

uint32_t s1, d;

sys/arch/m88k/m88k/m88100_fp.c

86

static inline uint32_t

sys/arch/m88k/m88k/m88100_fp.c

87

m88100_fpu_parse_single(uint32_t hs, uint32_t ls)

sys/arch/m88k/m88k/m88100_fp.c

89

uint32_t result;

sys/arch/m88k/m88k/m88100_machdep.c

348

uint32_t

sys/arch/m88k/m88k/m88100_machdep.c

351

uint32_t psr;

sys/arch/m88k/m88k/m88100_machdep.c

36

uint32_t m88100_mp_atomic_begin(__cpu_simple_lock_t *, uint *);

sys/arch/m88k/m88k/m88100_machdep.c

361

m88100_mp_atomic_end(uint32_t psr, __cpu_simple_lock_t *lock, uint csr)

sys/arch/m88k/m88k/m88100_machdep.c

37

void m88100_mp_atomic_end(uint32_t, __cpu_simple_lock_t *, uint);

sys/arch/m88k/m88k/m8820x_machdep.c

436

uint32_t linestatus;

sys/arch/m88k/m88k/m8820x_machdep.c

529

uint32_t linestatus;

sys/arch/m88k/m88k/m88k_machdep.c

481

extern uint32_t __atomic_lock[];

sys/arch/m88k/m88k/m88k_machdep.c

482

extern uint32_t __atomic_lock_88100[], __atomic_lock_88100_end[];

sys/arch/m88k/m88k/m88k_machdep.c

483

extern uint32_t __atomic_unlock[];

sys/arch/m88k/m88k/m88k_machdep.c

484

extern uint32_t __atomic_unlock_88100[], __atomic_unlock_88100_end[];

sys/arch/m88k/m88k/m88k_machdep.c

486

uint32_t *s, *e, *d;

sys/arch/m88k/m88k/pmap.c

235

uint32_t ti;

sys/arch/m88k/m88k/pmap.c

257

pmap_translation_info(pmap_t pmap, vaddr_t va, paddr_t *pap, uint32_t *ti)

sys/arch/m88k/m88k/trap.c

1596

uint32_t pc, instr, value;

sys/arch/m88k/m88k/trap.c

1688

if (copyin32((const uint32_t *)addr, &value) != 0)

sys/arch/m88k/m88k/trap.c

1692

if (copyin32((const uint32_t *)(addr + 4), &value) != 0)

sys/arch/macppc/dev/dfs.c

140

uint32_t hid1;

sys/arch/macppc/dev/dfs.c

71

uint32_t hid1, reg;

sys/arch/macppc/dev/i2s.c

883

uint32_t reg;

sys/arch/macppc/dev/kiic.c

90

uint32_t reg;

sys/arch/macppc/dev/kiicvar.h

93

uint32_t sc_busport;

sys/arch/macppc/dev/openpic.c

217

uint32_t reg = 0;

sys/arch/macppc/dev/uni_n.c

101

uint32_t rev, reg[2];

sys/arch/macppc/dev/uni_n.c

203

uint32_t

sys/arch/macppc/dev/uni_n.c

210

memc_write(struct memc_softc *sc, int offset, uint32_t value)

sys/arch/macppc/dev/uni_n.c

216

memc_enable(struct memc_softc *sc, int offset, uint32_t bits)

sys/arch/macppc/dev/uni_n.c

223

memc_disable(struct memc_softc *sc, int offset, uint32_t bits)

sys/arch/macppc/dev/uni_n.c

80

uint32_t memc_read(struct memc_softc *sc, int);

sys/arch/macppc/dev/uni_n.c

81

void memc_write(struct memc_softc *sc, int, uint32_t);

sys/arch/macppc/dev/uni_n.c

82

void memc_enable(struct memc_softc *, int, uint32_t);

sys/arch/macppc/dev/uni_n.c

83

void memc_disable(struct memc_softc *, int, uint32_t);

sys/arch/macppc/dev/xlights.c

233

uint32_t *p;

sys/arch/macppc/dev/xlights.c

236

uint32_t val;

sys/arch/macppc/dev/xlights.c

256

BL_BUFSZ / sizeof(uint32_t)) {

sys/arch/macppc/dev/xlights.c

35

uint32_t sc_freq;

sys/arch/macppc/dev/xlights.c

45

uint32_t *sc_buf;

sys/arch/macppc/dev/xlights.c

46

uint32_t *sc_bufpos;

sys/arch/macppc/include/pci_machdep.h

101

int ofw_intr_map(int, uint32_t *, uint32_t *);

sys/arch/macppc/macppc/clock.c

244

uint32_t cycles;

sys/arch/macppc/macppc/cpu.c

547

uint32_t hid0;

sys/arch/macppc/macppc/ofw_machdep.c

250

ofw_maps[i].om_phys = (uint32_t)ofw_maps64[i].om_phys;

sys/arch/macppc/macppc/ofw_machdep.c

425

uint32_t cons_addr;

sys/arch/macppc/macppc/ofw_machdep.c

495

uint32_t defattr;

sys/arch/macppc/macppc/ofw_machdep.c

71

uint32_t size;

sys/arch/macppc/macppc/ofw_machdep.c

82

uint32_t om_virt;

sys/arch/macppc/macppc/ofw_machdep.c

83

uint32_t om_size;

sys/arch/macppc/macppc/ofw_machdep.c

84

uint32_t om_phys;

sys/arch/macppc/macppc/ofw_machdep.c

85

uint32_t om_mode;

sys/arch/macppc/macppc/ofw_machdep.c

89

uint32_t om_virt;

sys/arch/macppc/macppc/ofw_machdep.c

90

uint32_t om_size;

sys/arch/macppc/macppc/ofw_machdep.c

92

uint32_t om_mode;

sys/arch/macppc/macppc/ofw_machdep.h

56

static inline uint32_t

sys/arch/macppc/macppc/ofw_machdep.h

59

uint32_t s = ppc_mfmsr();

sys/arch/macppc/macppc/opendev.c

131

uint32_t s;

sys/arch/macppc/macppc/opendev.c

168

uint32_t s;

sys/arch/macppc/macppc/opendev.c

197

uint32_t s;

sys/arch/macppc/macppc/opendev.c

224

uint32_t s;

sys/arch/macppc/macppc/opendev.c

271

uint32_t s;

sys/arch/macppc/macppc/opendev.c

310

uint32_t s;

sys/arch/macppc/macppc/opendev.c

59

uint32_t s;

sys/arch/macppc/macppc/opendev.c

88

uint32_t s;

sys/arch/macppc/macppc/openfirm.c

113

uint32_t s;

sys/arch/macppc/macppc/openfirm.c

141

uint32_t s;

sys/arch/macppc/macppc/openfirm.c

172

uint32_t s;

sys/arch/macppc/macppc/openfirm.c

210

uint32_t s;

sys/arch/macppc/macppc/openfirm.c

245

uint32_t s;

sys/arch/macppc/macppc/openfirm.c

278

uint32_t s;

sys/arch/macppc/macppc/openfirm.c

318

uint32_t s;

sys/arch/macppc/macppc/openfirm.c

344

uint32_t s;

sys/arch/macppc/macppc/openfirm.c

396

uint32_t s;

sys/arch/macppc/macppc/openfirm.c

59

uint32_t s;

sys/arch/macppc/macppc/openfirm.c

86

uint32_t s;

sys/arch/macppc/pci/ht.c

155

uint32_t val;

sys/arch/macppc/pci/ht.c

187

uint32_t val;

sys/arch/macppc/pci/pci_machdep.c

174

if (ofw_intr_map(OF_parent(node), (uint32_t *)&reg, intr)) {

sys/arch/macppc/pci/pci_machdep.c

250

uint32_t val = 0;

sys/arch/macppc/pci/pci_machdep.c

332

ofw_intr_map(int node, uint32_t *addr, uint32_t *intr)

sys/arch/macppc/pci/pci_machdep.c

334

uint32_t imap[144], mmask[8], *mp, *mp1;

sys/arch/macppc/pci/pci_machdep.c

335

uint32_t acells, icells, mcells;

sys/arch/macppc/pci/vgafb.c

182

uint32_t defattr;

sys/arch/macppc/pci/vgafb.c

457

int *curxp, int *curyp, uint32_t *attrp)

sys/arch/macppc/pci/vgafb.c

511

uint32_t bar, cf;

sys/arch/macppc/pci/vgafb.c

69

int *, int *, uint32_t *);

sys/arch/mips64/include/cpu.h

117

uint32_t c0prid;

sys/arch/mips64/include/cpu.h

118

uint32_t c1prid;

sys/arch/mips64/include/cpu.h

119

uint32_t clock; /* Hz */

sys/arch/mips64/include/cpu.h

120

uint32_t tlbsize;

sys/arch/mips64/include/cpu.h

122

uint32_t l2size;

sys/arch/mips64/include/cpu.h

142

uint32_t ci_delayconst;

sys/arch/mips64/include/cpu.h

181

uint32_t ci_randseed; /* per cpu random seed */

sys/arch/mips64/include/cpu.h

183

uint32_t ci_softpending; /* pending soft interrupts */

sys/arch/mips64/include/cpu.h

416

void tlb_set_page_mask(uint32_t);

sys/arch/mips64/include/cpu.h

418

void tlb_set_wired(uint32_t);

sys/arch/mips64/include/cpu.h

426

int copyinsn(struct proc *, vaddr_t, uint32_t *);

sys/arch/mips64/include/cpu.h

429

int fpe_branch_emulate(struct proc *, struct trapframe *, uint32_t,

sys/arch/mips64/include/cpu.h

437

register_t MipsEmulateBranch(struct trapframe *, vaddr_t, uint32_t, uint32_t);

sys/arch/mips64/include/cpu.h

439

int classify_insn(uint32_t);

sys/arch/mips64/include/cpu.h

457

uint32_t cp0_get_cause(void);

sys/arch/mips64/include/cpu.h

460

uint32_t cp0_get_config_1(void);

sys/arch/mips64/include/cpu.h

461

uint32_t cp0_get_config_2(void);

sys/arch/mips64/include/cpu.h

462

uint32_t cp0_get_config_3(void);

sys/arch/mips64/include/cpu.h

463

uint32_t cp0_get_config_4(void);

sys/arch/mips64/include/cpu.h

464

uint32_t cp0_get_pagegrain(void);

sys/arch/mips64/include/cpu.h

469

void cp0_set_pagegrain(uint32_t);

sys/arch/mips64/include/cpu.h

473

static inline uint32_t

sys/arch/mips64/include/cpu.h

476

uint32_t value;

sys/arch/mips64/include/cpu.h

482

cp0_set_hwrena(uint32_t value)

sys/arch/mips64/include/db_machdep.h

70

int dbmd_print_insn(uint32_t, vaddr_t, int (*)(const char *, ...));

sys/arch/mips64/include/ieee.h

95

(a)[0] = (uint32_t)(p)->ext_fracl; \

sys/arch/mips64/include/ieee.h

96

(a)[1] = (uint32_t)(p)->ext_fraclm; \

sys/arch/mips64/include/ieee.h

97

(a)[2] = (uint32_t)(p)->ext_frachm; \

sys/arch/mips64/include/ieee.h

98

(a)[3] = (uint32_t)(p)->ext_frach; \

sys/arch/mips64/include/loongson3.h

39

static inline uint32_t

sys/arch/mips64/include/loongson3.h

42

uint32_t tmp;

sys/arch/mips64/include/pmap.h

164

int pmap_copyinsn(pmap_t, vaddr_t, uint32_t *);

sys/arch/mips64/include/proc.h

52

uint32_t md_ss_instr; /* saved single step instruction */

sys/arch/mips64/mips64/cache_mips64r2.c

59

uint32_t cfg, valias_mask;

sys/arch/mips64/mips64/cache_mips64r2.c

60

uint32_t s, l, a;

sys/arch/mips64/mips64/cache_octeon.c

63

uint32_t cfg;

sys/arch/mips64/mips64/cache_octeon.c

64

uint32_t s, l, a;

sys/arch/mips64/mips64/clock.c

120

uint32_t

sys/arch/mips64/mips64/clock.c

121

cp0_int5(uint32_t mask, struct trapframe *tf)

sys/arch/mips64/mips64/clock.c

172

uint32_t cycles, t0;

sys/arch/mips64/mips64/clock.c

220

uint32_t offset = 16, t0;

sys/arch/mips64/mips64/clock.c

74

uint32_t cp0_int5(uint32_t, struct trapframe *);

sys/arch/mips64/mips64/db_disasm.c

1020

extern uint32_t kdbpeek(vaddr_t);

sys/arch/mips64/mips64/db_disasm.c

1039

uint32_t insn = 0;

sys/arch/mips64/mips64/db_disasm.c

557

dbmd_print_insn(uint32_t ins, vaddr_t mdbdot, int (*pr)(const char *, ...))

sys/arch/mips64/mips64/db_machdep.c

288

while (size >= sizeof(uint32_t)) {

sys/arch/mips64/mips64/db_machdep.c

289

*(uint32_t *)data = kdbpeek(addr);

sys/arch/mips64/mips64/db_machdep.c

290

data += sizeof(uint32_t);

sys/arch/mips64/mips64/db_machdep.c

291

addr += sizeof(uint32_t);

sys/arch/mips64/mips64/db_machdep.c

292

size -= sizeof(uint32_t);

sys/arch/mips64/mips64/db_machdep.c

313

while (len >= sizeof(uint32_t)) {

sys/arch/mips64/mips64/db_machdep.c

314

kdbpoke(ptr, *(uint32_t *)data);

sys/arch/mips64/mips64/db_machdep.c

315

data += sizeof(uint32_t);

sys/arch/mips64/mips64/db_machdep.c

316

ptr += sizeof(uint32_t);

sys/arch/mips64/mips64/db_machdep.c

317

len -= sizeof(uint32_t);

sys/arch/mips64/mips64/db_machdep.c

364

uint32_t instr;

sys/arch/mips64/mips64/db_machdep.c

58

uint32_t kdbpeek(vaddr_t);

sys/arch/mips64/mips64/db_machdep.c

62

void kdbpoke(vaddr_t, uint32_t);

sys/arch/mips64/mips64/fp_emulate.c

1020

uint32_t rm;

sys/arch/mips64/mips64/fp_emulate.c

1079

uint32_t rm;

sys/arch/mips64/mips64/fp_emulate.c

126

static inline uint32_t

sys/arch/mips64/mips64/fp_emulate.c

129

uint32_t fsr;

sys/arch/mips64/mips64/fp_emulate.c

142

setfsr(uint32_t fsr)

sys/arch/mips64/mips64/fp_emulate.c

1546

nofpu_emulate_cop1(struct proc *p, struct trapframe *tf, uint32_t insn,

sys/arch/mips64/mips64/fp_emulate.c

1624

uint32_t dinsn;

sys/arch/mips64/mips64/fp_emulate.c

163

uint32_t fsr, excbits;

sys/arch/mips64/mips64/fp_emulate.c

164

uint32_t branch = 0;

sys/arch/mips64/mips64/fp_emulate.c

165

uint32_t insn;

sys/arch/mips64/mips64/fp_emulate.c

1675

nofpu_emulate_cop1x(struct proc *p, struct trapframe *tf, uint32_t insn,

sys/arch/mips64/mips64/fp_emulate.c

1682

uint32_t wdata;

sys/arch/mips64/mips64/fp_emulate.c

1764

nofpu_emulate_loadstore(struct proc *p, struct trapframe *tf, uint32_t insn,

sys/arch/mips64/mips64/fp_emulate.c

1771

uint32_t wdata;

sys/arch/mips64/mips64/fp_emulate.c

1838

nofpu_emulate_movci(struct trapframe *tf, uint32_t insn)

sys/arch/mips64/mips64/fp_emulate.c

443

fpu_emulate(struct proc *p, struct trapframe *tf, uint32_t insn,

sys/arch/mips64/mips64/fp_emulate.c

47

int fpu_emulate(struct proc *, struct trapframe *, uint32_t,

sys/arch/mips64/mips64/fp_emulate.c

49

int fpu_emulate_cop1(struct proc *, struct trapframe *, uint32_t);

sys/arch/mips64/mips64/fp_emulate.c

50

int fpu_emulate_cop1x(struct proc *, struct trapframe *, uint32_t);

sys/arch/mips64/mips64/fp_emulate.c

520

fpu_emulate_cop1(struct proc *p, struct trapframe *tf, uint32_t insn)

sys/arch/mips64/mips64/fp_emulate.c

55

int nofpu_emulate_cop1(struct proc *, struct trapframe *, uint32_t,

sys/arch/mips64/mips64/fp_emulate.c

57

int nofpu_emulate_cop1x(struct proc *, struct trapframe *, uint32_t,

sys/arch/mips64/mips64/fp_emulate.c

59

int nofpu_emulate_loadstore(struct proc *, struct trapframe *, uint32_t,

sys/arch/mips64/mips64/fp_emulate.c

61

int nofpu_emulate_movci(struct trapframe *, uint32_t);

sys/arch/mips64/mips64/fp_emulate.c

652

fpu_emulate_cop1x(struct proc *p, struct trapframe *tf, uint32_t insn)

sys/arch/mips64/mips64/fp_emulate.c

779

uint32_t oldrm;

sys/arch/mips64/mips64/fp_emulate.c

809

uint32_t oldrm;

sys/arch/mips64/mips64/interrupt.c

132

uint32_t active;

sys/arch/mips64/mips64/interrupt.c

157

set_intr(int pri, uint32_t mask,

sys/arch/mips64/mips64/interrupt.c

158

uint32_t (*int_hand)(uint32_t, struct trapframe *))

sys/arch/mips64/mips64/interrupt.c

55

uint32_t idle_mask;

sys/arch/mips64/mips64/interrupt.c

59

uint32_t int_mask;

sys/arch/mips64/mips64/interrupt.c

60

uint32_t (*int_hand)(uint32_t, struct trapframe *);

sys/arch/mips64/mips64/mips64_machdep.c

237

uint32_t delayconst;

sys/arch/mips64/mips64/mips64_machdep.c

350

classify_insn(uint32_t insn)

sys/arch/mips64/mips64/mips64_machdep.c

412

extern uint32_t kernel_text[], endboot[];

sys/arch/mips64/mips64/mips64_machdep.c

413

uint32_t *word = kernel_text;

sys/arch/mips64/mips64/mips64_machdep.c

69

const uint32_t insns[] = {

sys/arch/mips64/mips64/mips64_machdep.c

79

uint32_t *dst = (uint32_t *)addr;

sys/arch/mips64/mips64/mips64_machdep.c

80

const uint32_t *src = insns;

sys/arch/mips64/mips64/mips64_machdep.c

81

uint32_t a, b, c, d;

sys/arch/mips64/mips64/pmap.c

2015

pmap_copyinsn(pmap_t pmap, vaddr_t uva, uint32_t *insn)

sys/arch/mips64/mips64/pmap.c

2037

*insn = *(uint32_t *)PHYS_TO_XKPHYS(pa, CCA_CACHED);

sys/arch/mips64/mips64/trap.c

1005

iov.iov_len = sizeof(uint32_t);

sys/arch/mips64/mips64/trap.c

1009

uio.uio_resid = sizeof(uint32_t);

sys/arch/mips64/mips64/trap.c

1026

uint32_t curinstr;

sys/arch/mips64/mips64/trap.c

1123

uint32_t instr, mask;

sys/arch/mips64/mips64/trap.c

126

uint32_t kdbpeek(vaddr_t);

sys/arch/mips64/mips64/trap.c

139

int ptrace_read_insn(struct proc *, vaddr_t, uint32_t *);

sys/arch/mips64/mips64/trap.c

1398

inst.word = *(uint32_t *)va;

sys/arch/mips64/mips64/trap.c

140

int ptrace_write_insn(struct proc *, vaddr_t, uint32_t);

sys/arch/mips64/mips64/trap.c

1402

inst.word = *(uint32_t *)va;

sys/arch/mips64/mips64/trap.c

1489

fpe_branch_emulate(struct proc *p, struct trapframe *tf, uint32_t insn,

sys/arch/mips64/mips64/trap.c

402

uint32_t branch = 0;

sys/arch/mips64/mips64/trap.c

476

uint32_t branch = 0;

sys/arch/mips64/mips64/trap.c

477

uint32_t instr;

sys/arch/mips64/mips64/trap.c

597

uint32_t branch = 0;

sys/arch/mips64/mips64/trap.c

598

uint32_t instr;

sys/arch/mips64/mips64/trap.c

658

uint32_t branch = 0;

sys/arch/mips64/mips64/trap.c

795

copyinsn(struct proc *p, vaddr_t uva, uint32_t *insn)

sys/arch/mips64/mips64/trap.c

867

MipsEmulateBranch(struct trapframe *tf, vaddr_t instPC, uint32_t fsr,

sys/arch/mips64/mips64/trap.c

868

uint32_t curinst)

sys/arch/mips64/mips64/trap.c

981

ptrace_read_insn(struct proc *p, vaddr_t va, uint32_t *insn)

sys/arch/mips64/mips64/trap.c

987

iov.iov_len = sizeof(uint32_t);

sys/arch/mips64/mips64/trap.c

991

uio.uio_resid = sizeof(uint32_t);

sys/arch/mips64/mips64/trap.c

999

ptrace_write_insn(struct proc *p, vaddr_t va, uint32_t insn)

sys/arch/octeon/dev/cn30xxfauvar.h

95

cn30xxfau_op_iobdma((int)((uint32_t)scraddr >> 3) /* XXX */, args);

sys/arch/octeon/dev/cn30xxgmx.c

1457

(uint32_t)_GMX_PORT_RD8(sc, GMX0_RX0_STATS_PKTS);

sys/arch/octeon/dev/cn30xxgmx.c

1459

(uint32_t)_GMX_PORT_RD8(sc, GMX0_RX0_STATS_OCTS);

sys/arch/octeon/dev/cn30xxgmx.c

1461

(uint32_t)_GMX_PORT_RD8(sc, GMX0_RX0_STATS_PKTS_CTL);

sys/arch/octeon/dev/cn30xxgmx.c

1463

(uint32_t)_GMX_PORT_RD8(sc, GMX0_RX0_STATS_PKTS_DMAC);

sys/arch/octeon/dev/cn30xxgmx.c

1465

(uint32_t)_GMX_PORT_RD8(sc, GMX0_RX0_STATS_PKTS_DRP);

sys/arch/octeon/dev/cn30xxgmx.c

1467

(uint32_t)_GMX_PORT_RD8(sc, GMX0_RX0_STATS_PKTS_BAD);

sys/arch/octeon/dev/cn30xxgmx.c

1470

kstat_kv_u64(&kvs[cnmac_stat_tx_coll]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxgmx.c

1474

kstat_kv_u64(&kvs[cnmac_stat_tx_mcol]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxgmx.c

1478

(uint32_t)_GMX_PORT_RD8(sc, GMX0_TX0_STAT2);

sys/arch/octeon/dev/cn30xxgmx.c

1480

(uint32_t)_GMX_PORT_RD8(sc, GMX0_TX0_STAT3);

sys/arch/octeon/dev/cn30xxgmx.c

1483

kstat_kv_u64(&kvs[cnmac_stat_tx_hmin]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxgmx.c

1487

kstat_kv_u64(&kvs[cnmac_stat_tx_h127]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxgmx.c

1491

kstat_kv_u64(&kvs[cnmac_stat_tx_h511]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxgmx.c

1495

kstat_kv_u64(&kvs[cnmac_stat_tx_h1518]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxgmx.c

1499

kstat_kv_u64(&kvs[cnmac_stat_tx_bcast]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxgmx.c

1503

kstat_kv_u64(&kvs[cnmac_stat_tx_ctl]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxpip.c

178

kstat_kv_u64(&kvs[cnmac_stat_rx_qdpo]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxpip.c

182

kstat_kv_u64(&kvs[cnmac_stat_rx_toto_pip]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxpip.c

185

kstat_kv_u64(&kvs[cnmac_stat_rx_raw]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxpip.c

189

kstat_kv_u64(&kvs[cnmac_stat_rx_mcast]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxpip.c

193

kstat_kv_u64(&kvs[cnmac_stat_rx_h64]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxpip.c

197

kstat_kv_u64(&kvs[cnmac_stat_rx_h255]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxpip.c

201

kstat_kv_u64(&kvs[cnmac_stat_rx_h1023]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxpip.c

205

kstat_kv_u64(&kvs[cnmac_stat_rx_hmax]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxpip.c

209

kstat_kv_u64(&kvs[cnmac_stat_rx_undersz]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxpip.c

213

kstat_kv_u64(&kvs[cnmac_stat_rx_oversz]) += (uint32_t)val;

sys/arch/octeon/dev/cn30xxpowvar.h

165

uint32_t tag) /* 0-0xffff.ffff */

sys/arch/octeon/dev/cn30xxpowvar.h

190

cn30xxpow_ops_swtag(int type, uint32_t tag)

sys/arch/octeon/dev/cn30xxpowvar.h

208

cn30xxpow_ops_swtag_full(paddr_t addr, int grp, int type, uint32_t tag)

sys/arch/octeon/dev/cn30xxpowvar.h

225

cn30xxpow_ops_swtag_desched(int no_sched, int grp, int type, uint32_t tag)

sys/arch/octeon/dev/cn30xxpowvar.h

259

cn30xxpow_ops_addwq(paddr_t addr, int qos, int grp, int type, uint32_t tag)

sys/arch/octeon/dev/cn30xxpowvar.h

365

void cn30xxpow_ops_swtag(int, uint32_t);

sys/arch/octeon/dev/if_cnmac.c

104

(((uint32_t)OCTEON_POOL_SIZE_CMD / sizeof(uint64_t)) - 1)

sys/arch/octeon/dev/if_cnmac.c

1266

uint32_t coreid = octeon_get_coreid();

sys/arch/octeon/dev/if_cnmac.c

1267

uint32_t port;

sys/arch/octeon/dev/if_cnmac.c

204

uint32_t cnmac_mac_addr_offset = 0;

sys/arch/octeon/dev/if_cnmacvar.h

91

uint32_t sc_port;

sys/arch/octeon/dev/if_cnmacvar.h

92

uint32_t sc_port_type;

sys/arch/octeon/dev/if_cnmacvar.h

93

uint32_t sc_init_flag;

sys/arch/octeon/dev/if_ogx.c

1661

uint32_t c_reg;

sys/arch/octeon/dev/if_ogx.c

1914

uint32_t chipid;

sys/arch/octeon/dev/if_ogx.c

2180

uint32_t poolid, uint32_t nentries)

sys/arch/octeon/dev/if_ogx.c

2223

uint32_t auraid, struct fpa3pool *pool)

sys/arch/octeon/dev/if_ogx.c

244

void ogx_fpa3_aura_init(struct ogx_node *, struct fpa3aura *, uint32_t,

sys/arch/octeon/dev/if_ogx.c

250

void ogx_fpa3_pool_init(struct ogx_node *, struct fpa3pool *, uint32_t,

sys/arch/octeon/dev/if_ogx.c

251

uint32_t);

sys/arch/octeon/dev/if_ogx.c

372

uint32_t lmac;

sys/arch/octeon/dev/if_ogx.c

957

ogx_get_work(struct ogx_node *node, uint32_t group)

sys/arch/octeon/dev/octboot.c

41

uint32_t octeon_boot_ready;

sys/arch/octeon/dev/octcf.c

148

int octcf_write_sectors(struct octcf_softc *, uint32_t, uint32_t, void *);

sys/arch/octeon/dev/octcf.c

149

int octcf_read_sectors(struct octcf_softc *, uint32_t, uint32_t, void *);

sys/arch/octeon/dev/octcf.c

151

void octcf_command(struct octcf_softc *, uint32_t, uint8_t);

sys/arch/octeon/dev/octcf.c

668

octcf_read_sectors(struct octcf_softc *wd, uint32_t nr_sectors,

sys/arch/octeon/dev/octcf.c

669

uint32_t start_sector, void *buf)

sys/arch/octeon/dev/octcf.c

671

uint32_t count;

sys/arch/octeon/dev/octcf.c

697

octcf_write_sectors(struct octcf_softc *wd, uint32_t nr_sectors,

sys/arch/octeon/dev/octcf.c

698

uint32_t start_sector, void *buf)

sys/arch/octeon/dev/octcf.c

700

uint32_t count;

sys/arch/octeon/dev/octcf.c

724

octcf_command(struct octcf_softc *wd, uint32_t lba, uint8_t cmd)

sys/arch/octeon/dev/octcib.c

169

uint32_t *cells;

sys/arch/octeon/dev/octcib.c

170

uint32_t bit, type;

sys/arch/octeon/dev/octcib.c

180

if (len / (sizeof(uint32_t) * 2) <= idx ||

sys/arch/octeon/dev/octcib.c

181

len % (sizeof(uint32_t) * 2) != 0)

sys/arch/octeon/dev/octcib.c

228

uint32_t bit = cih->cih_bit;

sys/arch/octeon/dev/octcib.c

279

uint32_t bit;

sys/arch/octeon/dev/octcib.c

55

uint32_t cih_bit;

sys/arch/octeon/dev/octcib.c

56

uint32_t cih_flags;

sys/arch/octeon/dev/octcib.c

72

uint32_t sc_maxbits;

sys/arch/octeon/dev/octcit.c

107

uint32_t octcit_intr(uint32_t, struct trapframe *);

sys/arch/octeon/dev/octcit.c

118

uint32_t octcit_ipi_intr(uint32_t, struct trapframe *);

sys/arch/octeon/dev/octcit.c

306

uint32_t *cells;

sys/arch/octeon/dev/octcit.c

311

if (len / (sizeof(uint32_t) * 2) <= idx ||

sys/arch/octeon/dev/octcit.c

312

len % (sizeof(uint32_t) * 2) != 0)

sys/arch/octeon/dev/octcit.c

389

uint32_t

sys/arch/octeon/dev/octcit.c

390

octcit_intr(uint32_t hwpend, struct trapframe *frame)

sys/arch/octeon/dev/octcit.c

501

uint32_t

sys/arch/octeon/dev/octcit.c

502

octcit_ipi_intr(uint32_t hwpend, struct trapframe *frame)

sys/arch/octeon/dev/octciu.c

112

uint32_t octciu_intr0(uint32_t, struct trapframe *);

sys/arch/octeon/dev/octciu.c

113

uint32_t octciu_intr2(uint32_t, struct trapframe *);

sys/arch/octeon/dev/octciu.c

114

uint32_t octciu_intr_bank(struct octciu_softc *, struct intrbank *,

sys/arch/octeon/dev/octciu.c

124

uint32_t octciu_ipi_intr(uint32_t, struct trapframe *);

sys/arch/octeon/dev/octciu.c

301

uint32_t *cells;

sys/arch/octeon/dev/octciu.c

305

if (len / (sizeof(uint32_t) * 2) <= idx ||

sys/arch/octeon/dev/octciu.c

306

len % (sizeof(uint32_t) * 2) != 0)

sys/arch/octeon/dev/octciu.c

462

uint32_t

sys/arch/octeon/dev/octciu.c

549

uint32_t

sys/arch/octeon/dev/octciu.c

550

octciu_intr0(uint32_t hwpend, struct trapframe *frame)

sys/arch/octeon/dev/octciu.c

561

uint32_t

sys/arch/octeon/dev/octciu.c

562

octciu_intr2(uint32_t hwpend, struct trapframe *frame)

sys/arch/octeon/dev/octciu.c

602

uint32_t

sys/arch/octeon/dev/octciu.c

603

octciu_ipi_intr(uint32_t hwpend, struct trapframe *frame)

sys/arch/octeon/dev/octcrypto.c

100

int octcrypto_newsession(uint32_t *, struct cryptoini *);

sys/arch/octeon/dev/octcrypto.c

105

octcrypto_get(struct octcrypto_softc *, uint32_t);

sys/arch/octeon/dev/octcrypto.c

286

octcrypto_get(struct octcrypto_softc *sc, uint32_t sid)

sys/arch/octeon/dev/octcrypto.c

333

octcrypto_newsession(uint32_t *sidp, struct cryptoini *cri)

sys/arch/octeon/dev/octcrypto.c

345

uint32_t sid;

sys/arch/octeon/dev/octcrypto.c

540

uint32_t sid = (uint32_t)tid;

sys/arch/octeon/dev/octcrypto.c

59

uint32_t ses_sid; /* RB key, keep first */

sys/arch/octeon/dev/octcrypto.c

603

ses = octcrypto_get(sc, (uint32_t)crp->crp_sid);

sys/arch/octeon/dev/octcrypto.c

90

uint32_t sc_sid;

sys/arch/octeon/dev/octeon_pcibus.c

76

#define REG_READ32(addr) (*(volatile uint32_t *)(addr))

sys/arch/octeon/dev/octeon_pcibus.c

77

#define REG_WRITE32(addr, data) (*(volatile uint32_t *)(addr) = (uint32_t)(data))

sys/arch/octeon/dev/octgpio.c

139

octgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/octeon/dev/octgpio.c

143

uint32_t pin = cells[0];

sys/arch/octeon/dev/octgpio.c

177

octgpio_get_pin(void *cookie, uint32_t *cells)

sys/arch/octeon/dev/octgpio.c

180

uint32_t pin = cells[0];

sys/arch/octeon/dev/octgpio.c

181

uint32_t flags = cells[1];

sys/arch/octeon/dev/octgpio.c

194

octgpio_set_pin(void *cookie, uint32_t *cells, int value)

sys/arch/octeon/dev/octgpio.c

197

uint32_t pin = cells[0];

sys/arch/octeon/dev/octgpio.c

198

uint32_t flags = cells[1];

sys/arch/octeon/dev/octgpio.c

57

uint32_t sc_npins;

sys/arch/octeon/dev/octgpio.c

58

uint32_t sc_xbit;

sys/arch/octeon/dev/octgpio.c

64

void octgpio_config_pin(void *, uint32_t *, int);

sys/arch/octeon/dev/octgpio.c

65

int octgpio_get_pin(void *, uint32_t *);

sys/arch/octeon/dev/octgpio.c

66

void octgpio_set_pin(void *, uint32_t *, int);

sys/arch/octeon/dev/octgpio.c

90

uint32_t chipid;

sys/arch/octeon/dev/octiic.c

149

uint32_t freq;

sys/arch/octeon/dev/octiic.c

345

uint32_t reg[1];

sys/arch/octeon/dev/octiic.c

439

octiic_set_clock(struct octiic_softc *sc, uint32_t freq)

sys/arch/octeon/dev/octiic.c

66

int octiic_set_clock(struct octiic_softc *, uint32_t);

sys/arch/octeon/dev/octmmc.c

114

uint32_t octmmc_host_ocr(sdmmc_chipset_handle_t);

sys/arch/octeon/dev/octmmc.c

118

int octmmc_bus_power(sdmmc_chipset_handle_t, uint32_t);

sys/arch/octeon/dev/octmmc.c

181

uint32_t bus_id, bus_width;

sys/arch/octeon/dev/octmmc.c

268

bus_id = OF_getpropint(node, "reg", (uint32_t)-1);

sys/arch/octeon/dev/octmmc.c

493

uint32_t

sys/arch/octeon/dev/octmmc.c

518

octmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)

sys/arch/octeon/dev/octmmc.c

75

uint32_t bus_id;

sys/arch/octeon/dev/octmmc.c

76

uint32_t bus_cmd_skew;

sys/arch/octeon/dev/octmmc.c

77

uint32_t bus_dat_skew;

sys/arch/octeon/dev/octmmc.c

78

uint32_t bus_max_freq; /* in kHz */

sys/arch/octeon/dev/octmmc.c

82

uint32_t bus_cd_gpio[3];

sys/arch/octeon/dev/octpcie.c

179

uint32_t cfg_bar_ctl_reg;

sys/arch/octeon/dev/octpcie.c

180

uint32_t cfg_bar1_index_reg;

sys/arch/octeon/dev/octpcie.c

237

uint32_t octpcie_cfgreg_read(struct octpcie_port *, uint32_t);

sys/arch/octeon/dev/octpcie.c

238

void octpcie_cfgreg_write(struct octpcie_port *, uint32_t, uint32_t);

sys/arch/octeon/dev/octpcie.c

284

uint32_t chipid;

sys/arch/octeon/dev/octpcie.c

436

uint32_t chipid, cr;

sys/arch/octeon/dev/octpcie.c

670

uint32_t chipid;

sys/arch/octeon/dev/octpcie.c

848

uint32_t

sys/arch/octeon/dev/octpcie.c

849

octpcie_cfgreg_read(struct octpcie_port *port, uint32_t off)

sys/arch/octeon/dev/octpcie.c

856

return (uint32_t)(val >> 32);

sys/arch/octeon/dev/octpcie.c

860

octpcie_cfgreg_write(struct octpcie_port *port, uint32_t off, uint32_t val)

sys/arch/octeon/dev/octpip.c

61

uint32_t ifindex;

sys/arch/octeon/dev/octpip.c

70

ifindex = OF_getpropint(node, "reg", (uint32_t)-1);

sys/arch/octeon/dev/octsctl.c

73

uint32_t reg[4];

sys/arch/octeon/dev/octuctl.c

103

octuctl_write_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, uint32_t v)

sys/arch/octeon/dev/octuctl.c

105

*(volatile uint32_t *)(h + o) = v;

sys/arch/octeon/dev/octuctl.c

206

uint32_t reg[4];

sys/arch/octeon/dev/octuctl.c

52

uint32_t octuctl_read_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);

sys/arch/octeon/dev/octuctl.c

55

void octuctl_write_4(bus_space_tag_t, bus_space_handle_t, bus_size_t, uint32_t);

sys/arch/octeon/dev/octuctl.c

84

uint32_t

sys/arch/octeon/dev/octuctl.c

87

return *(volatile uint32_t *)(h + o);

sys/arch/octeon/dev/octxctl.c

111

uint32_t reg[4];

sys/arch/octeon/dev/octxctl.c

189

static const uint32_t clock_divs[] = { 1, 2, 4, 6, 8, 16, 24, 32 };

sys/arch/octeon/dev/octxctl.c

332

uint32_t rev;

sys/arch/octeon/dev/octxctl.c

333

uint32_t val;

sys/arch/octeon/dev/octxctl.c

396

uint32_t

sys/arch/octeon/dev/octxctl.c

399

return *(volatile uint32_t *)(h + o);

sys/arch/octeon/dev/octxctl.c

418

uint32_t v)

sys/arch/octeon/dev/octxctl.c

420

*(volatile uint32_t *)(h + o) = v;

sys/arch/octeon/dev/octxctl.c

58

uint32_t octxctl_read_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);

sys/arch/octeon/dev/octxctl.c

64

uint32_t);

sys/arch/octeon/dev/ogxvar.h

23

uint32_t nodeid;

sys/arch/octeon/dev/ogxvar.h

24

uint32_t poolid;

sys/arch/octeon/dev/ogxvar.h

31

uint32_t nodeid;

sys/arch/octeon/dev/ogxvar.h

32

uint32_t poolid;

sys/arch/octeon/dev/ogxvar.h

33

uint32_t auraid;

sys/arch/octeon/dev/simplebus.c

154

uint32_t *cell, *reg;

sys/arch/octeon/dev/simplebus.c

172

line = (sc->sc_acells + sc->sc_scells) * sizeof(uint32_t);

sys/arch/octeon/dev/simplebus.c

202

if (len > 0 && (len % sizeof(uint32_t)) == 0) {

sys/arch/octeon/dev/simplebus.c

204

fa.fa_nintr = len / sizeof(uint32_t);

sys/arch/octeon/dev/simplebus.c

213

free(fa.fa_intr, M_DEVBUF, fa.fa_nintr * sizeof(uint32_t));

sys/arch/octeon/dev/simplebus.c

225

uint32_t *range;

sys/arch/octeon/dev/simplebus.c

238

rlen = sc->sc_rangeslen / sizeof(uint32_t);

sys/arch/octeon/dev/simplebus.c

97

if (sc->sc_rangeslen > 0 && !(sc->sc_rangeslen % sizeof(uint32_t))) {

sys/arch/octeon/include/bus.h

487

uint32_t generic_space_read_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);

sys/arch/octeon/include/bus.h

496

uint32_t);

sys/arch/octeon/include/fdt.h

31

uint32_t *fa_intr;

sys/arch/octeon/include/intr.h

139

extern uint32_t idle_mask;

sys/arch/octeon/include/intr.h

142

void set_intr(int, uint32_t, uint32_t(*)(uint32_t, struct trapframe *));

sys/arch/octeon/include/intr.h

144

uint32_t updateimask(uint32_t);

sys/arch/octeon/include/octeon_model.h

66

static inline uint32_t

sys/arch/octeon/include/octeon_model.h

69

uint32_t tmp;

sys/arch/octeon/include/octeonvar.h

230

uint32_t desc_ver;

sys/arch/octeon/include/octeonvar.h

231

uint32_t desc_size;

sys/arch/octeon/include/octeonvar.h

237

uint32_t __unused18;

sys/arch/octeon/include/octeonvar.h

238

uint32_t __unused15;

sys/arch/octeon/include/octeonvar.h

239

uint32_t __unused14;

sys/arch/octeon/include/octeonvar.h

240

uint32_t argc;

sys/arch/octeon/include/octeonvar.h

241

uint32_t argv[OCTEON_ARGV_MAX];

sys/arch/octeon/include/octeonvar.h

242

uint32_t flags;

sys/arch/octeon/include/octeonvar.h

243

uint32_t core_mask;

sys/arch/octeon/include/octeonvar.h

244

uint32_t dram_size;

sys/arch/octeon/include/octeonvar.h

245

uint32_t phy_mem_desc_addr;

sys/arch/octeon/include/octeonvar.h

246

uint32_t debugger_flag_addr;

sys/arch/octeon/include/octeonvar.h

247

uint32_t eclock;

sys/arch/octeon/include/octeonvar.h

248

uint32_t __unused10;

sys/arch/octeon/include/octeonvar.h

249

uint32_t __unused9;

sys/arch/octeon/include/octeonvar.h

263

uint32_t ver_major;

sys/arch/octeon/include/octeonvar.h

264

uint32_t ver_minor;

sys/arch/octeon/include/octeonvar.h

269

uint32_t exception_base_addr;

sys/arch/octeon/include/octeonvar.h

270

uint32_t stack_size;

sys/arch/octeon/include/octeonvar.h

271

uint32_t flags;

sys/arch/octeon/include/octeonvar.h

272

uint32_t core_mask;

sys/arch/octeon/include/octeonvar.h

273

uint32_t dram_size;

sys/arch/octeon/include/octeonvar.h

274

uint32_t phys_mem_desc_addr;

sys/arch/octeon/include/octeonvar.h

275

uint32_t debugger_flags_addr;

sys/arch/octeon/include/octeonvar.h

276

uint32_t eclock;

sys/arch/octeon/include/octeonvar.h

277

uint32_t dclock;

sys/arch/octeon/include/octeonvar.h

278

uint32_t __unused0;

sys/arch/octeon/include/octeonvar.h

291

uint32_t dfaclock;

sys/arch/octeon/include/octeonvar.h

292

uint32_t config_flags;

sys/arch/octeon/include/octeonvar.h

298

uint32_t lock;

sys/arch/octeon/include/octeonvar.h

299

uint32_t flags;

sys/arch/octeon/include/octeonvar.h

301

uint32_t major_version;

sys/arch/octeon/include/octeonvar.h

302

uint32_t minor_version;

sys/arch/octeon/include/octeonvar.h

305

uint32_t named_block_num_blocks;

sys/arch/octeon/include/octeonvar.h

306

uint32_t named_block_name_len;

sys/arch/octeon/include/octeonvar.h

400

static inline uint32_t

sys/arch/octeon/include/octeonvar.h

403

uint32_t coreid;

sys/arch/octeon/octeon/bus_space.c

118

volatile uint32_t *addr = (volatile uint32_t *)(h + o);

sys/arch/octeon/octeon/bus_space.c

121

*(uint32_t *)buf = *addr;

sys/arch/octeon/octeon/bus_space.c

130

volatile uint32_t *addr = (volatile uint32_t *)(h + o);

sys/arch/octeon/octeon/bus_space.c

133

*addr = *(uint32_t *)buf;

sys/arch/octeon/octeon/bus_space.c

50

uint32_t

sys/arch/octeon/octeon/bus_space.c

53

return *(volatile uint32_t *)(h + o);

sys/arch/octeon/octeon/bus_space.c

78

uint32_t v)

sys/arch/octeon/octeon/bus_space.c

80

*(volatile uint32_t *)(h + o) = v;

sys/arch/octeon/octeon/machdep.c

1279

uint32_t cpu_spinup_mask = 0;

sys/arch/octeon/octeon/machdep.c

1296

cpu_spinup_mask = (uint32_t)ci->ci_cpuid;

sys/arch/octeon/octeon/machdep.c

285

uint32_t config4;

sys/arch/octeon/octeon/machdep.c

707

uint32_t hwrena = 0;

sys/arch/octeon/octeon/machdep.c

708

uint32_t pgrain = 0;

sys/arch/powerpc/ddb/db_trace.c

204

uint32_t code = tf->fixreg[0];

sys/arch/powerpc/ddb/db_trace.c

205

uint32_t type = tf->exc;

sys/arch/powerpc/include/pmap.h

144

int pmap_copyinsn(pmap_t, vaddr_t, uint32_t *);

sys/arch/powerpc/powerpc/cpu_subr.c

30

uint32_t *s;

sys/arch/powerpc/powerpc/cpu_subr.c

31

uint32_t *e;

sys/arch/powerpc/powerpc/cpu_subr.c

34

extern uint32_t rfid_inst, nop_inst;

sys/arch/powerpc/powerpc/cpu_subr.c

39

uint32_t cpu;

sys/arch/powerpc/powerpc/cpu_subr.c

40

uint32_t *inst;

sys/arch/powerpc/powerpc/pmap.c

1603

uint32_t scratch, sdr1;

sys/arch/powerpc/powerpc/pmap.c

1632

sdr1 = (uint32_t)pmap_ptable64 | HTABSIZE_64;

sys/arch/powerpc/powerpc/pmap.c

1634

sdr1 = (uint32_t)pmap_ptable32 | (pmap_ptab_mask >> 10);

sys/arch/powerpc/powerpc/pmap.c

1707

pmap_copyinsn(pmap_t pm, vaddr_t va, uint32_t *insn)

sys/arch/powerpc/powerpc/pmap.c

1727

*insn = *(uint32_t *)pa;

sys/arch/powerpc/powerpc/pmap.c

1817

copyin32(const uint32_t *udaddr, uint32_t *kaddr)

sys/arch/powerpc/powerpc/pmap.c

1819

volatile uint32_t *p;

sys/arch/powerpc/powerpc/trap.c

627

if (pmap_copyinsn(map->pmap, uva, (uint32_t *)insn) == 0)

sys/arch/powerpc/powerpc/trap.c

639

void vecast_asm(uint32_t, void *);

sys/arch/powerpc/powerpc/trap.c

651

uint32_t insn, op, va, vc, lo;

sys/arch/powerpc64/dev/astfb.c

102

uint32_t addr[5];

sys/arch/powerpc64/dev/astfb.c

104

uint32_t defattr;

sys/arch/powerpc64/dev/astfb.c

247

void **cookiep, int *curxp, int *curyp, uint32_t *attrp)

sys/arch/powerpc64/dev/astfb.c

56

void **, int *, int *, uint32_t *);

sys/arch/powerpc64/dev/kexec.c

211

uint32_t boothowto = htobe32(kargs->boothowto);

sys/arch/powerpc64/dev/mainbus.c

148

if (sc->sc_rangeslen > 0 && !(sc->sc_rangeslen % sizeof(uint32_t))) {

sys/arch/powerpc64/dev/mainbus.c

205

uint32_t *cell, *reg;

sys/arch/powerpc64/dev/mainbus.c

226

line = (sc->sc_acells + sc->sc_scells) * sizeof(uint32_t);

sys/arch/powerpc64/dev/mainbus.c

256

if (len > 0 && (len % sizeof(uint32_t)) == 0) {

sys/arch/powerpc64/dev/mainbus.c

258

fa.fa_nintr = len / sizeof(uint32_t);

sys/arch/powerpc64/dev/mainbus.c

290

free(fa.fa_intr, M_DEVBUF, fa.fa_nintr * sizeof(uint32_t));

sys/arch/powerpc64/dev/opal.c

102

uint32_t *interrupts;

sys/arch/powerpc64/dev/opal.c

117

if (len > 0 && (len % sizeof(uint32_t)) != 0) {

sys/arch/powerpc64/dev/opal.c

132

sc->sc_nintr = len / sizeof(uint32_t);

sys/arch/powerpc64/dev/opal.c

281

uint32_t date;

sys/arch/powerpc64/dev/opal.c

312

uint32_t date = 0;

sys/arch/powerpc64/dev/opal.c

320

date |= (uint32_t)TOBCD(dt.dt_day);

sys/arch/powerpc64/dev/opal.c

321

date |= (uint32_t)TOBCD(dt.dt_mon) << 8;

sys/arch/powerpc64/dev/opal.c

322

date |= (uint32_t)TOBCD(dt.dt_year) << 16;

sys/arch/powerpc64/dev/opal.c

323

date |= (uint32_t)TOBCD(dt.dt_year / 100) << 24;

sys/arch/powerpc64/dev/opal.c

344

uint32_t accept, *flags;

sys/arch/powerpc64/dev/opal.c

38

uint32_t oi_isn;

sys/arch/powerpc64/dev/opal.c

388

uint32_t pirs[8];

sys/arch/powerpc64/dev/opalsens.c

31

uint32_t sc_data;

sys/arch/powerpc64/dev/pci_machdep.c

29

bus_addr_t addr, uint32_t data)

sys/arch/powerpc64/dev/pci_machdep.c

90

int vec, bus_addr_t addr, uint32_t data)

sys/arch/powerpc64/dev/pci_machdep.c

94

uint32_t ctrl;

sys/arch/powerpc64/dev/phb.c

153

uint32_t bus_range[2];

sys/arch/powerpc64/dev/phb.c

154

uint32_t *ranges;

sys/arch/powerpc64/dev/phb.c

155

uint32_t m64window[6];

sys/arch/powerpc64/dev/phb.c

156

uint32_t m64ranges[2];

sys/arch/powerpc64/dev/phb.c

158

uint32_t window;

sys/arch/powerpc64/dev/phb.c

159

uint32_t chip_id;

sys/arch/powerpc64/dev/phb.c

223

if (rangeslen <= 0 || (rangeslen % sizeof(uint32_t)) ||

sys/arch/powerpc64/dev/phb.c

224

(rangeslen / sizeof(uint32_t)) % (sc->sc_acells +

sys/arch/powerpc64/dev/phb.c

237

nranges = (rangeslen / sizeof(uint32_t)) /

sys/arch/powerpc64/dev/phb.c

429

uint32_t *tce_sizes;

sys/arch/powerpc64/dev/phb.c

437

if (len <= 0 || (len % sizeof(uint32_t)))

sys/arch/powerpc64/dev/phb.c

443

for (i = 0; i < len / sizeof(uint32_t); i++)

sys/arch/powerpc64/dev/phb.c

48

uint32_t flags;

sys/arch/powerpc64/dev/phb.c

506

uint32_t reg[5];

sys/arch/powerpc64/dev/phb.c

507

uint32_t phys_hi;

sys/arch/powerpc64/dev/phb.c

561

uint32_t data;

sys/arch/powerpc64/dev/phb.c

636

uint32_t addr32, data;

sys/arch/powerpc64/dev/phb.c

638

uint32_t xive;

sys/arch/powerpc64/dev/phb.c

680

uint32_t reg[4];

sys/arch/powerpc64/dev/phb.c

70

uint32_t sc_msi_ranges[2];

sys/arch/powerpc64/dev/phb.c

71

uint32_t sc_xive;

sys/arch/powerpc64/dev/xicp.c

100

void *xicp_intr_establish(uint32_t, int, int, struct cpu_info *,

sys/arch/powerpc64/dev/xicp.c

121

uint32_t ranges[2];

sys/arch/powerpc64/dev/xicp.c

178

xicp_intr_establish(uint32_t girq, int type, int level, struct cpu_info *ci,

sys/arch/powerpc64/dev/xicp.c

235

uint32_t xirr, xisr;

sys/arch/powerpc64/dev/xicp.c

52

uint32_t ih_girq;

sys/arch/powerpc64/dev/xicp.c

76

static inline uint32_t

sys/arch/powerpc64/dev/xicp.c

83

xicp_write_4(struct xicp_softc *sc, bus_size_t off, uint32_t val)

sys/arch/powerpc64/dev/xics.c

80

uint32_t girq = cell[0];

sys/arch/powerpc64/dev/xive.c

100

uint32_t sc_lirq;

sys/arch/powerpc64/dev/xive.c

153

void *xive_intr_establish(uint32_t, int, int, struct cpu_info *,

sys/arch/powerpc64/dev/xive.c

251

xive_intr_establish(uint32_t girq, int type, int level, struct cpu_info *ci,

sys/arch/powerpc64/dev/xive.c

259

uint32_t esb_shift, lirq;

sys/arch/powerpc64/dev/xive.c

401

uint32_t *event;

sys/arch/powerpc64/dev/xive.c

402

uint32_t lirq;

sys/arch/powerpc64/dev/xive.c

75

uint32_t ih_girq;

sys/arch/powerpc64/dev/xive.c

86

uint32_t eq_idx;

sys/arch/powerpc64/dev/xive.c

87

uint32_t eq_gen;

sys/arch/powerpc64/dev/xive.c

99

uint32_t sc_page_size;

sys/arch/powerpc64/include/bus.h

499

uint32_t generic_space_read_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);

sys/arch/powerpc64/include/bus.h

506

uint32_t);

sys/arch/powerpc64/include/bus.h

523

uint32_t little_space_read_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);

sys/arch/powerpc64/include/bus.h

528

uint32_t);

sys/arch/powerpc64/include/bus.h

53

uint32_t (*_space_read_4)(bus_space_tag_t , bus_space_handle_t,

sys/arch/powerpc64/include/bus.h

56

bus_size_t, uint32_t);

sys/arch/powerpc64/include/cpu.h

60

uint32_t ci_cpuid;

sys/arch/powerpc64/include/cpu.h

61

uint32_t ci_pir;

sys/arch/powerpc64/include/cpu.h

80

uint32_t ci_ipending;

sys/arch/powerpc64/include/cpu.h

81

uint32_t ci_idepth;

sys/arch/powerpc64/include/cpu.h

87

uint32_t ci_randseed;

sys/arch/powerpc64/include/cpufunc.h

112

static inline uint32_t

sys/arch/powerpc64/include/cpufunc.h

115

uint32_t value;

sys/arch/powerpc64/include/cpufunc.h

129

mtdec(uint32_t value)

sys/arch/powerpc64/include/cpufunc.h

158

static inline uint32_t

sys/arch/powerpc64/include/cpufunc.h

161

uint32_t value;

sys/arch/powerpc64/include/cpufunc.h

210

static inline uint32_t

sys/arch/powerpc64/include/cpufunc.h

213

uint32_t value;

sys/arch/powerpc64/include/fdt.h

30

uint32_t *fa_intr;

sys/arch/powerpc64/include/intr.h

108

extern void *(*_intr_establish)(uint32_t, int, int, struct cpu_info *,

sys/arch/powerpc64/include/intr.h

121

uint32_t ic_phandle;

sys/arch/powerpc64/include/intr.h

122

uint32_t ic_cells;

sys/arch/powerpc64/include/intr.h

97

void *intr_establish(uint32_t, int, int, struct cpu_info *,

sys/arch/powerpc64/include/opal.h

180

int64_t opal_rtc_read(uint32_t *, uint64_t *);

sys/arch/powerpc64/include/opal.h

181

int64_t opal_rtc_write(uint32_t, uint64_t);

sys/arch/powerpc64/include/opal.h

184

int64_t opal_handle_interrupt(uint32_t, uint64_t *);

sys/arch/powerpc64/include/opal.h

186

int64_t opal_pci_config_read_word(uint64_t, uint64_t, uint64_t, uint32_t *);

sys/arch/powerpc64/include/opal.h

187

int64_t opal_pci_config_write_word(uint64_t, uint64_t, uint64_t, uint32_t);

sys/arch/powerpc64/include/opal.h

188

int64_t opal_set_xive(uint32_t, uint16_t, uint8_t);

sys/arch/powerpc64/include/opal.h

189

int64_t opal_get_xive(uint32_t, uint16_t *, uint8_t *);

sys/arch/powerpc64/include/opal.h

200

int64_t opal_pci_set_xive_pe(uint64_t, uint64_t, uint32_t);

sys/arch/powerpc64/include/opal.h

201

int64_t opal_get_msi_32(uint64_t, uint32_t, uint32_t, uint8_t,

sys/arch/powerpc64/include/opal.h

202

uint32_t *, uint32_t *);

sys/arch/powerpc64/include/opal.h

203

int64_t opal_get_msi_64(uint64_t, uint32_t, uint32_t, uint8_t,

sys/arch/powerpc64/include/opal.h

204

uint64_t *, uint32_t *);

sys/arch/powerpc64/include/opal.h

213

int64_t opal_sensor_read(uint32_t, int, uint32_t *);

sys/arch/powerpc64/include/opal.h

218

int64_t opal_xive_get_irq_info(uint32_t, uint64_t *, uint64_t *,

sys/arch/powerpc64/include/opal.h

219

uint64_t *, uint32_t *, uint32_t *);

sys/arch/powerpc64/include/opal.h

220

int64_t opal_xive_get_irq_config(uint32_t, uint64_t *, uint8_t *, uint32_t *);

sys/arch/powerpc64/include/opal.h

221

int64_t opal_xive_set_irq_config(uint32_t, uint64_t, uint8_t, uint32_t);

sys/arch/powerpc64/include/opal.h

223

uint64_t *, uint64_t *, uint32_t *, uint64_t *);

sys/arch/powerpc64/include/opal.h

227

uint64_t *, uint32_t *);

sys/arch/powerpc64/include/opal.h

229

int64_t opal_xive_dump(uint32_t, uint32_t);

sys/arch/powerpc64/include/opal.h

230

int64_t opal_sensor_read_u64(uint32_t, int, uint64_t *);

sys/arch/powerpc64/include/pci_machdep.h

123

void pci_msi_enable(pci_chipset_tag_t, pcitag_t, bus_addr_t, uint32_t);

sys/arch/powerpc64/include/pci_machdep.h

125

int, bus_addr_t, uint32_t);

sys/arch/powerpc64/include/smbiosvar.h

147

uint32_t charext;

sys/arch/powerpc64/include/smbiosvar.h

226

uint32_t cpu_id_eax;

sys/arch/powerpc64/include/smbiosvar.h

227

uint32_t cpu_id_edx;

sys/arch/powerpc64/include/smbiosvar.h

52

uint32_t sig; /* "_SM_" */

sys/arch/powerpc64/include/smbiosvar.h

63

uint32_t addr; /* Structure table address */

sys/arch/powerpc64/include/smbiosvar.h

77

uint32_t size; /* Structure table maximum size */

sys/arch/powerpc64/include/smbiosvar.h

90

uint32_t cookie;

sys/arch/powerpc64/powerpc64/bus_space.c

121

volatile uint32_t *addr = (volatile uint32_t *)(h + o);

sys/arch/powerpc64/powerpc64/bus_space.c

125

*(uint32_t *)buf = *addr;

sys/arch/powerpc64/powerpc64/bus_space.c

134

volatile uint32_t *addr = (volatile uint32_t *)(h + o);

sys/arch/powerpc64/powerpc64/bus_space.c

138

*addr = *(uint32_t *)buf;

sys/arch/powerpc64/powerpc64/bus_space.c

234

uint32_t

sys/arch/powerpc64/powerpc64/bus_space.c

237

return lemtoh32((volatile uint32_t *)(h + o));

sys/arch/powerpc64/powerpc64/bus_space.c

255

uint32_t v)

sys/arch/powerpc64/powerpc64/bus_space.c

257

htolem32((volatile uint32_t *)(h + o) , v);

sys/arch/powerpc64/powerpc64/bus_space.c

51

uint32_t

sys/arch/powerpc64/powerpc64/bus_space.c

54

return *(volatile uint32_t *)(h + o);

sys/arch/powerpc64/powerpc64/bus_space.c

79

uint32_t v)

sys/arch/powerpc64/powerpc64/bus_space.c

81

*(volatile uint32_t *)(h + o) = v;

sys/arch/powerpc64/powerpc64/clock.c

59

uint32_t cycles;

sys/arch/powerpc64/powerpc64/cpu.c

106

uint32_t pvr, clock_freq, iline, dline;

sys/arch/powerpc64/powerpc64/cpu.c

148

uint32_t isize, iways;

sys/arch/powerpc64/powerpc64/cpu.c

149

uint32_t dsize, dways;

sys/arch/powerpc64/powerpc64/cpu.c

150

uint32_t cache;

sys/arch/powerpc64/powerpc64/cpu.c

225

uint32_t pvr = mfpvr();

sys/arch/powerpc64/powerpc64/cpu.c

315

uint32_t pir = mfpir();

sys/arch/powerpc64/powerpc64/db_trace.c

136

uint32_t ins;

sys/arch/powerpc64/powerpc64/intr.c

191

dummy_intr_establish(uint32_t girq, int type, int level, struct cpu_info *ci,

sys/arch/powerpc64/powerpc64/intr.c

238

uint32_t

sys/arch/powerpc64/powerpc64/intr.c

241

uint32_t phandle = 0;

sys/arch/powerpc64/powerpc64/intr.c

257

uint32_t *cell, *cells, phandle;

sys/arch/powerpc64/powerpc64/intr.c

266

if (len <= 0 || (len % sizeof(uint32_t) != 0))

sys/arch/powerpc64/powerpc64/intr.c

286

ncells = len / sizeof(uint32_t);

sys/arch/powerpc64/powerpc64/intr.c

32

void *dummy_intr_establish(uint32_t, int, int, struct cpu_info *,

sys/arch/powerpc64/powerpc64/intr.c

347

uint32_t *cell;

sys/arch/powerpc64/powerpc64/intr.c

348

uint32_t map_mask[4], *map;

sys/arch/powerpc64/powerpc64/intr.c

367

ncells = len / sizeof(uint32_t);

sys/arch/powerpc64/powerpc64/intr.c

43

void *(*_intr_establish)(uint32_t, int, int, struct cpu_info *,

sys/arch/powerpc64/powerpc64/intr.c

61

intr_establish(uint32_t girq, int type, int level, struct cpu_info *ci,

sys/arch/powerpc64/powerpc64/intr.c

68

uint32_t intr_smask[NIPL];

sys/arch/powerpc64/powerpc64/machdep.c

594

copyin32(const uint32_t *uaddr, uint32_t *kaddr)

sys/arch/powerpc64/powerpc64/machdep.c

596

return copyin(uaddr, kaddr, sizeof(uint32_t));

sys/arch/powerpc64/powerpc64/machdep.c

775

boothowto = bemtoh32((uint32_t *)prop);

sys/arch/powerpc64/powerpc64/pmap.c

382

uint32_t pmap_vsid[NUM_VSID / 32];

sys/arch/powerpc64/powerpc64/pmap.c

387

uint32_t bits;

sys/arch/powerpc64/powerpc64/pmap.c

388

uint32_t vsid, bit;

sys/arch/powerpc64/powerpc64/pmap.c

406

uint32_t bits;

sys/arch/powerpc64/powerpc64/trap.c

181

uint32_t insn = *(uint32_t *)frame->srr0;

sys/arch/powerpc64/powerpc64/trap.c

185

uint32_t rs = (insn >> 21) & 0x1f;

sys/arch/powerpc64/powerpc64/trap.c

186

uint32_t ra = (insn >> 16) & 0x1f;

sys/arch/powerpc64/powerpc64/trap.c

207

*(volatile uint32_t *)ea = frame->fixreg[rs] >> 32;

sys/arch/powerpc64/powerpc64/trap.c

208

*(volatile uint32_t *)(ea + 4) = frame->fixreg[rs];

sys/arch/riscv64/dev/mainbus.c

131

if (sc->sc_rangeslen > 0 && !(sc->sc_rangeslen % sizeof(uint32_t))) {

sys/arch/riscv64/dev/mainbus.c

190

uint32_t *cell, *reg;

sys/arch/riscv64/dev/mainbus.c

211

line = (sc->sc_acells + sc->sc_scells) * sizeof(uint32_t);

sys/arch/riscv64/dev/mainbus.c

241

if (len > 0 && (len % sizeof(uint32_t)) == 0) {

sys/arch/riscv64/dev/mainbus.c

243

fa.fa_nintr = len / sizeof(uint32_t);

sys/arch/riscv64/dev/mainbus.c

278

free(fa.fa_intr, M_DEVBUF, fa.fa_nintr * sizeof(uint32_t));

sys/arch/riscv64/dev/mpfclock.c

100

int mpfclock_set_frequency(void *, uint32_t *, uint32_t);

sys/arch/riscv64/dev/mpfclock.c

159

uint32_t

sys/arch/riscv64/dev/mpfclock.c

160

mpfclock_get_frequency(void *cookie, uint32_t *cells)

sys/arch/riscv64/dev/mpfclock.c

163

uint32_t div, shift;

sys/arch/riscv64/dev/mpfclock.c

164

uint32_t idx = cells[0];

sys/arch/riscv64/dev/mpfclock.c

192

mpfclock_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/arch/riscv64/dev/mpfclock.c

198

mpfclock_enable(void *cookie, uint32_t *cells, int on)

sys/arch/riscv64/dev/mpfclock.c

201

uint32_t idx = cells[0];

sys/arch/riscv64/dev/mpfclock.c

202

uint32_t bit, val;

sys/arch/riscv64/dev/mpfclock.c

84

uint32_t sc_clkcfg;

sys/arch/riscv64/dev/mpfclock.c

85

uint32_t sc_refclk;

sys/arch/riscv64/dev/mpfclock.c

98

void mpfclock_enable(void *, uint32_t *, int);

sys/arch/riscv64/dev/mpfclock.c

99

uint32_t mpfclock_get_frequency(void *, uint32_t *);

sys/arch/riscv64/dev/mpfgpio.c

149

mpfgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/riscv64/dev/mpfgpio.c

152

uint32_t pin = cells[0];

sys/arch/riscv64/dev/mpfgpio.c

153

uint32_t val;

sys/arch/riscv64/dev/mpfgpio.c

173

mpfgpio_get_pin(void *cookie, uint32_t *cells)

sys/arch/riscv64/dev/mpfgpio.c

176

uint32_t pin = cells[0];

sys/arch/riscv64/dev/mpfgpio.c

177

uint32_t flags = cells[1];

sys/arch/riscv64/dev/mpfgpio.c

190

mpfgpio_set_pin(void *cookie, uint32_t *cells, int val)

sys/arch/riscv64/dev/mpfgpio.c

193

uint32_t pin = cells[0];

sys/arch/riscv64/dev/mpfgpio.c

194

uint32_t flags = cells[1];

sys/arch/riscv64/dev/mpfgpio.c

212

uint32_t cells[2];

sys/arch/riscv64/dev/mpfgpio.c

224

uint32_t cells[2];

sys/arch/riscv64/dev/mpfgpio.c

236

uint32_t cells[2];

sys/arch/riscv64/dev/mpfgpio.c

237

uint32_t config = 0;

sys/arch/riscv64/dev/mpfgpio.c

259

uint32_t cfgreg, pin;

sys/arch/riscv64/dev/mpfgpio.c

56

uint32_t sc_npins;

sys/arch/riscv64/dev/mpfgpio.c

73

void mpfgpio_config_pin(void *, uint32_t *, int);

sys/arch/riscv64/dev/mpfgpio.c

74

int mpfgpio_get_pin(void *, uint32_t *);

sys/arch/riscv64/dev/mpfgpio.c

75

void mpfgpio_set_pin(void *, uint32_t *, int);

sys/arch/riscv64/dev/mpfiic.c

109

uint32_t div;

sys/arch/riscv64/dev/mpfiic.c

110

uint32_t cr;

sys/arch/riscv64/dev/mpfiic.c

142

uint32_t i, bus_freq, clock_freq;

sys/arch/riscv64/dev/mpfiic.c

348

uint32_t reg[1];

sys/arch/riscv64/dev/mpfiic.c

76

uint32_t sc_bus_freq; /* in Hz */

sys/arch/riscv64/dev/pci_machdep.c

29

bus_addr_t addr, uint32_t data)

sys/arch/riscv64/dev/pci_machdep.c

90

int vec, bus_addr_t addr, uint32_t data)

sys/arch/riscv64/dev/pci_machdep.c

94

uint32_t ctrl;

sys/arch/riscv64/dev/plic.c

113

int plic_irq_dispatch(uint32_t, void *);

sys/arch/riscv64/dev/plic.c

130

void plic_set_priority(int, uint32_t);

sys/arch/riscv64/dev/plic.c

131

void plic_set_threshold(int, uint32_t);

sys/arch/riscv64/dev/plic.c

133

void plic_intr_enable_with_pri(int, uint32_t, int);

sys/arch/riscv64/dev/plic.c

165

uint32_t *cells;

sys/arch/riscv64/dev/plic.c

166

uint32_t irq;

sys/arch/riscv64/dev/plic.c

323

uint32_t pending;

sys/arch/riscv64/dev/plic.c

324

uint32_t cpu;

sys/arch/riscv64/dev/plic.c

355

plic_irq_dispatch(uint32_t irq, void *frame)

sys/arch/riscv64/dev/plic.c

480

uint32_t min_pri = sc->sc_isrcs[irq].is_irq_min;

sys/arch/riscv64/dev/plic.c

61

#define PLIC_PRIORITY(n) (PLIC_PRIORITY_BASE + (n) * sizeof(uint32_t))

sys/arch/riscv64/dev/plic.c

625

uint32_t hart;

sys/arch/riscv64/dev/plic.c

63

(sc->sc_contexts[h].enable_offset + ((n) / 32) * sizeof(uint32_t))

sys/arch/riscv64/dev/plic.c

651

plic_set_priority(int irq, uint32_t pri)

sys/arch/riscv64/dev/plic.c

654

uint32_t prival;

sys/arch/riscv64/dev/plic.c

673

plic_set_threshold(int cpu, uint32_t threshold)

sys/arch/riscv64/dev/plic.c

676

uint32_t prival;

sys/arch/riscv64/dev/plic.c

697

uint32_t val, mask;

sys/arch/riscv64/dev/plic.c

723

plic_intr_enable_with_pri(int irq, uint32_t min_pri, int cpu)

sys/arch/riscv64/dev/sfcc.c

39

uint32_t sc_line_size;

sys/arch/riscv64/dev/sfclock.c

120

uint32_t

sys/arch/riscv64/dev/sfclock.c

124

uint32_t pllr, pllf, pllq;

sys/arch/riscv64/dev/sfclock.c

125

uint32_t reg;

sys/arch/riscv64/dev/sfclock.c

134

uint32_t

sys/arch/riscv64/dev/sfclock.c

135

sfclock_get_frequency(void *cookie, uint32_t *cells)

sys/arch/riscv64/dev/sfclock.c

138

uint32_t idx = cells[0];

sys/arch/riscv64/dev/sfclock.c

139

uint32_t reg, div;

sys/arch/riscv64/dev/sfclock.c

162

sfclock_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/arch/riscv64/dev/sfclock.c

164

uint32_t idx = cells[0];

sys/arch/riscv64/dev/sfclock.c

171

sfclock_enable(void *cookie, uint32_t *cells, int on)

sys/arch/riscv64/dev/sfclock.c

173

uint32_t idx = cells[0];

sys/arch/riscv64/dev/sfclock.c

78

uint32_t sfclock_get_frequency(void *, uint32_t *);

sys/arch/riscv64/dev/sfclock.c

79

int sfclock_set_frequency(void *, uint32_t *, uint32_t);

sys/arch/riscv64/dev/sfclock.c

80

void sfclock_enable(void *, uint32_t *, int);

sys/arch/riscv64/dev/sfgpio.c

159

sfgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/riscv64/dev/sfgpio.c

162

uint32_t pin = cells[0];

sys/arch/riscv64/dev/sfgpio.c

177

sfgpio_get_pin(void *cookie, uint32_t *cells)

sys/arch/riscv64/dev/sfgpio.c

180

uint32_t pin = cells[0];

sys/arch/riscv64/dev/sfgpio.c

181

uint32_t flags = cells[1];

sys/arch/riscv64/dev/sfgpio.c

182

uint32_t reg;

sys/arch/riscv64/dev/sfgpio.c

196

sfgpio_set_pin(void *cookie, uint32_t *cells, int val)

sys/arch/riscv64/dev/sfgpio.c

199

uint32_t pin = cells[0];

sys/arch/riscv64/dev/sfgpio.c

200

uint32_t flags = cells[1];

sys/arch/riscv64/dev/sfgpio.c

93

void sfgpio_config_pin(void *, uint32_t *, int);

sys/arch/riscv64/dev/sfgpio.c

94

int sfgpio_get_pin(void *, uint32_t *);

sys/arch/riscv64/dev/sfgpio.c

95

void sfgpio_set_pin(void *, uint32_t *, int);

sys/arch/riscv64/dev/sfuart.c

196

uint32_t val;

sys/arch/riscv64/dev/sfuart.c

286

uint32_t div;

sys/arch/riscv64/dev/sfuart.c

601

uint32_t val;

sys/arch/riscv64/dev/sfuart.c

80

uint32_t sc_frequency;

sys/arch/riscv64/dev/sgmsi.c

137

uint32_t cells[2];

sys/arch/riscv64/dev/sgmsi.c

35

uint32_t sc_msi_mask;

sys/arch/riscv64/dev/sgmsi.c

37

uint32_t sc_msi_range[4];

sys/arch/riscv64/dev/simplebus.c

107

(sc->sc_dmarangeslen % sizeof(uint32_t)) == 0) {

sys/arch/riscv64/dev/simplebus.c

165

uint32_t *cell, *reg;

sys/arch/riscv64/dev/simplebus.c

192

line = (sc->sc_acells + sc->sc_scells) * sizeof(uint32_t);

sys/arch/riscv64/dev/simplebus.c

222

if (len > 0 && (len % sizeof(uint32_t)) == 0) {

sys/arch/riscv64/dev/simplebus.c

224

fa.fa_nintr = len / sizeof(uint32_t);

sys/arch/riscv64/dev/simplebus.c

260

free(fa.fa_intr, M_DEVBUF, fa.fa_nintr * sizeof(uint32_t));

sys/arch/riscv64/dev/simplebus.c

272

uint32_t *range;

sys/arch/riscv64/dev/simplebus.c

285

rlen = sc->sc_rangeslen / sizeof(uint32_t);

sys/arch/riscv64/dev/simplebus.c

335

rlen = sc->sc_dmarangeslen / sizeof(uint32_t);

sys/arch/riscv64/dev/simplebus.c

341

uint32_t *range;

sys/arch/riscv64/dev/simplebus.c

95

(sc->sc_rangeslen % sizeof(uint32_t)) == 0) {

sys/arch/riscv64/dev/smtclock.c

263

uint32_t smtclock_get_frequency(void *, uint32_t *);

sys/arch/riscv64/dev/smtclock.c

264

int smtclock_set_frequency(void *, uint32_t *, uint32_t);

sys/arch/riscv64/dev/smtclock.c

265

void smtclock_enable(void *, uint32_t *, int);

sys/arch/riscv64/dev/smtclock.c

266

void smtclock_reset(void *, uint32_t *, int);

sys/arch/riscv64/dev/smtclock.c

322

uint32_t

sys/arch/riscv64/dev/smtclock.c

323

smtclock_get_frequency(void *cookie, uint32_t *cells)

sys/arch/riscv64/dev/smtclock.c

327

uint32_t idx = cells[0];

sys/arch/riscv64/dev/smtclock.c

328

uint32_t reg;

sys/arch/riscv64/dev/smtclock.c

368

smtclock_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/arch/riscv64/dev/smtclock.c

370

uint32_t idx = cells[0];

sys/arch/riscv64/dev/smtclock.c

377

smtclock_enable(void *cookie, uint32_t *cells, int on)

sys/arch/riscv64/dev/smtclock.c

381

uint32_t idx = cells[0];

sys/arch/riscv64/dev/smtclock.c

419

smtclock_reset(void *cookie, uint32_t *cells, int assert)

sys/arch/riscv64/dev/smtclock.c

423

uint32_t idx = cells[0];

sys/arch/riscv64/dev/smtclock.c

424

uint32_t assert_mask = 0;

sys/arch/riscv64/dev/smtclock.c

425

uint32_t deassert_mask = 0;

sys/arch/riscv64/dev/smtclock.c

426

uint32_t mask, val;

sys/arch/riscv64/dev/smtcomphy.c

113

int smtcomphy_combo_enable(void *, uint32_t *);

sys/arch/riscv64/dev/smtcomphy.c

114

int smtcomphy_pcie_enable(void *, uint32_t *);

sys/arch/riscv64/dev/smtcomphy.c

168

uint32_t apmu, val;

sys/arch/riscv64/dev/smtcomphy.c

200

uint32_t val;

sys/arch/riscv64/dev/smtcomphy.c

227

uint32_t val;

sys/arch/riscv64/dev/smtcomphy.c

245

uint32_t val;

sys/arch/riscv64/dev/smtcomphy.c

272

smtcomphy_combo_enable(void *cookie, uint32_t *cells)

sys/arch/riscv64/dev/smtcomphy.c

275

uint32_t type = cells[0];

sys/arch/riscv64/dev/smtcomphy.c

276

uint32_t val, oval;

sys/arch/riscv64/dev/smtcomphy.c

304

smtcomphy_pcie_enable(void *cookie, uint32_t *cells)

sys/arch/riscv64/dev/smtcomphy.c

307

uint32_t val;

sys/arch/riscv64/dev/smtcomphy.c

86

uint32_t rx_rterm;

sys/arch/riscv64/dev/smtcomphy.c

87

uint32_t tx_rterm;

sys/arch/riscv64/dev/smtgpio.c

106

smtgpio_bank_offset(uint32_t bank)

sys/arch/riscv64/dev/smtgpio.c

123

smtgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/riscv64/dev/smtgpio.c

126

uint32_t bank = cells[0];

sys/arch/riscv64/dev/smtgpio.c

127

uint32_t pin = cells[1];

sys/arch/riscv64/dev/smtgpio.c

140

smtgpio_get_pin(void *cookie, uint32_t *cells)

sys/arch/riscv64/dev/smtgpio.c

143

uint32_t bank = cells[0];

sys/arch/riscv64/dev/smtgpio.c

144

uint32_t pin = cells[1];

sys/arch/riscv64/dev/smtgpio.c

145

uint32_t flags = cells[2];

sys/arch/riscv64/dev/smtgpio.c

147

uint32_t reg;

sys/arch/riscv64/dev/smtgpio.c

161

smtgpio_set_pin(void *cookie, uint32_t *cells, int val)

sys/arch/riscv64/dev/smtgpio.c

164

uint32_t bank = cells[0];

sys/arch/riscv64/dev/smtgpio.c

165

uint32_t pin = cells[1];

sys/arch/riscv64/dev/smtgpio.c

166

uint32_t flags = cells[2];

sys/arch/riscv64/dev/smtgpio.c

64

void smtgpio_config_pin(void *, uint32_t *, int);

sys/arch/riscv64/dev/smtgpio.c

65

int smtgpio_get_pin(void *, uint32_t *);

sys/arch/riscv64/dev/smtgpio.c

66

void smtgpio_set_pin(void *, uint32_t *, int);

sys/arch/riscv64/dev/smtiic.c

171

smtiic_wait_state(struct smtiic_softc *sc, uint32_t mask, uint32_t value)

sys/arch/riscv64/dev/smtiic.c

173

uint32_t state;

sys/arch/riscv64/dev/smtiic.c

299

uint32_t reg[1];

sys/arch/riscv64/dev/smtiic.c

68

uint32_t sc_freq;

sys/arch/riscv64/dev/smtiic.c

95

int smtiic_wait_state(struct smtiic_softc *, uint32_t, uint32_t);

sys/arch/riscv64/dev/smtpinctrl.c

101

k1_config_pin(struct smtpinctrl_softc *sc, uint32_t pinmux, int bias, int ds)

sys/arch/riscv64/dev/smtpinctrl.c

106

uint32_t val;

sys/arch/riscv64/dev/smtpinctrl.c

141

k1_pinctrl(uint32_t phandle, void *cookie)

sys/arch/riscv64/dev/smtpinctrl.c

144

uint32_t *pinmux;

sys/arch/riscv64/dev/smtpinctrl.c

218

for (i = 0; i < len / sizeof(uint32_t); i++)

sys/arch/riscv64/dev/smtpinctrl.c

64

int k1_pinctrl(uint32_t, void *);

sys/arch/riscv64/dev/stfclock.c

1062

stfclock_enable_jh7110_sys(void *cookie, uint32_t *cells, int on)

sys/arch/riscv64/dev/stfclock.c

1065

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

1066

uint32_t parent;

sys/arch/riscv64/dev/stfclock.c

1119

stfclock_reset_jh7110_sys(void *cookie, uint32_t *cells, int assert)

sys/arch/riscv64/dev/stfclock.c

1122

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

1123

uint32_t bits, offset;

sys/arch/riscv64/dev/stfclock.c

210

uint32_t stfclock_get_frequency_jh7100(void *, uint32_t *);

sys/arch/riscv64/dev/stfclock.c

211

int stfclock_set_frequency_jh7100(void *, uint32_t *, uint32_t);

sys/arch/riscv64/dev/stfclock.c

212

void stfclock_enable_jh7100(void *, uint32_t *, int);

sys/arch/riscv64/dev/stfclock.c

214

uint32_t stfclock_get_frequency_jh7110_aon(void *, uint32_t *);

sys/arch/riscv64/dev/stfclock.c

215

int stfclock_set_frequency_jh7110_aon(void *, uint32_t *, uint32_t);

sys/arch/riscv64/dev/stfclock.c

216

void stfclock_enable_jh7110_aon(void *, uint32_t *, int);

sys/arch/riscv64/dev/stfclock.c

217

void stfclock_reset_jh7110_aon(void *, uint32_t *, int);

sys/arch/riscv64/dev/stfclock.c

219

uint32_t stfclock_get_frequency_jh7110_pll(void *, uint32_t *);

sys/arch/riscv64/dev/stfclock.c

220

int stfclock_set_frequency_jh7110_pll(void *, uint32_t *, uint32_t);

sys/arch/riscv64/dev/stfclock.c

221

void stfclock_enable_jh7110_pll(void *, uint32_t *, int);

sys/arch/riscv64/dev/stfclock.c

223

uint32_t stfclock_get_frequency_jh7110_stg(void *, uint32_t *);

sys/arch/riscv64/dev/stfclock.c

224

int stfclock_set_frequency_jh7110_stg(void *, uint32_t *, uint32_t);

sys/arch/riscv64/dev/stfclock.c

225

void stfclock_enable_jh7110_stg(void *, uint32_t *, int);

sys/arch/riscv64/dev/stfclock.c

226

void stfclock_reset_jh7110_stg(void *, uint32_t *, int);

sys/arch/riscv64/dev/stfclock.c

228

uint32_t stfclock_get_frequency_jh7110_sys(void *, uint32_t *);

sys/arch/riscv64/dev/stfclock.c

229

int stfclock_set_frequency_jh7110_sys(void *, uint32_t *, uint32_t);

sys/arch/riscv64/dev/stfclock.c

230

void stfclock_enable_jh7110_sys(void *, uint32_t *, int);

sys/arch/riscv64/dev/stfclock.c

231

void stfclock_reset_jh7110_sys(void *, uint32_t *, int);

sys/arch/riscv64/dev/stfclock.c

325

uint32_t

sys/arch/riscv64/dev/stfclock.c

326

stfclock_get_frequency_jh7100(void *cookie, uint32_t *cells)

sys/arch/riscv64/dev/stfclock.c

329

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

330

uint32_t parent, freq;

sys/arch/riscv64/dev/stfclock.c

331

uint32_t reg, div, mux;

sys/arch/riscv64/dev/stfclock.c

451

stfclock_set_frequency_jh7100(void *cookie, uint32_t *cells, uint32_t freq)

sys/arch/riscv64/dev/stfclock.c

453

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

461

stfclock_enable_jh7100(void *cookie, uint32_t *cells, int on)

sys/arch/riscv64/dev/stfclock.c

464

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

495

uint32_t

sys/arch/riscv64/dev/stfclock.c

496

stfclock_get_frequency_jh7110_aon(void *cookie, uint32_t *cells)

sys/arch/riscv64/dev/stfclock.c

499

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

500

uint32_t parent, freq;

sys/arch/riscv64/dev/stfclock.c

501

uint32_t reg, div, mux;

sys/arch/riscv64/dev/stfclock.c

552

stfclock_set_frequency_jh7110_aon(void *cookie, uint32_t *cells, uint32_t freq)

sys/arch/riscv64/dev/stfclock.c

555

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

556

uint32_t parent, parent_freq;

sys/arch/riscv64/dev/stfclock.c

557

uint32_t reg, div, mux;

sys/arch/riscv64/dev/stfclock.c

602

stfclock_enable_jh7110_aon(void *cookie, uint32_t *cells, int on)

sys/arch/riscv64/dev/stfclock.c

605

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

628

stfclock_reset_jh7110_aon(void *cookie, uint32_t *cells, int assert)

sys/arch/riscv64/dev/stfclock.c

631

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

632

uint32_t bits, offset;

sys/arch/riscv64/dev/stfclock.c

643

uint32_t

sys/arch/riscv64/dev/stfclock.c

644

stfclock_get_frequency_jh7110_pll(void *cookie, uint32_t *cells)

sys/arch/riscv64/dev/stfclock.c

647

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

648

uint32_t dacpd, dsmpd, fbdiv, frac, prediv, postdiv, reg;

sys/arch/riscv64/dev/stfclock.c

723

stfclock_set_frequency_jh7110_pll(void *cookie, uint32_t *cells, uint32_t freq)

sys/arch/riscv64/dev/stfclock.c

726

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

727

uint32_t dacpd, dsmpd, fbdiv, prediv, postdiv1, reg;

sys/arch/riscv64/dev/stfclock.c

791

stfclock_enable_jh7110_pll(void *cookie, uint32_t *cells, int on)

sys/arch/riscv64/dev/stfclock.c

793

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

798

uint32_t

sys/arch/riscv64/dev/stfclock.c

799

stfclock_get_frequency_jh7110_stg(void *cookie, uint32_t *cells)

sys/arch/riscv64/dev/stfclock.c

801

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

808

stfclock_set_frequency_jh7110_stg(void *cookie, uint32_t *cells, uint32_t freq)

sys/arch/riscv64/dev/stfclock.c

810

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

818

stfclock_enable_jh7110_stg(void *cookie, uint32_t *cells, int on)

sys/arch/riscv64/dev/stfclock.c

821

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

843

stfclock_reset_jh7110_stg(void *cookie, uint32_t *cells, int assert)

sys/arch/riscv64/dev/stfclock.c

846

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

847

uint32_t bits, offset;

sys/arch/riscv64/dev/stfclock.c

858

uint32_t

sys/arch/riscv64/dev/stfclock.c

859

stfclock_get_frequency_jh7110_sys(void *cookie, uint32_t *cells)

sys/arch/riscv64/dev/stfclock.c

862

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

863

uint32_t parent, freq;

sys/arch/riscv64/dev/stfclock.c

864

uint32_t reg, div, mux;

sys/arch/riscv64/dev/stfclock.c

980

stfclock_set_frequency_jh7110_sys(void *cookie, uint32_t *cells, uint32_t freq)

sys/arch/riscv64/dev/stfclock.c

983

uint32_t idx = cells[0];

sys/arch/riscv64/dev/stfclock.c

984

uint32_t parent, parent_freq;

sys/arch/riscv64/dev/stfclock.c

985

uint32_t reg, div, mux;

sys/arch/riscv64/dev/stfpcie.c

105

uint32_t flags;

sys/arch/riscv64/dev/stfpcie.c

164

uint32_t sc_msi_addr;

sys/arch/riscv64/dev/stfpcie.c

231

uint32_t *ranges;

sys/arch/riscv64/dev/stfpcie.c

233

uint32_t bus_range[2];

sys/arch/riscv64/dev/stfpcie.c

237

uint32_t *perst_gpio;

sys/arch/riscv64/dev/stfpcie.c

239

uint32_t reg, stg;

sys/arch/riscv64/dev/stfpcie.c

325

if (rangeslen <= 0 || (rangeslen % sizeof(uint32_t)) ||

sys/arch/riscv64/dev/stfpcie.c

326

(rangeslen / sizeof(uint32_t)) % (sc->sc_acells +

sys/arch/riscv64/dev/stfpcie.c

336

nranges = (rangeslen / sizeof(uint32_t)) /

sys/arch/riscv64/dev/stfpcie.c

585

uint32_t mask;

sys/arch/riscv64/dev/stfpcie.c

624

uint32_t mask;

sys/arch/riscv64/dev/stfpcie.c

693

stfpcie_intx_intr(struct stfpcie_softc *sc, uint32_t status)

sys/arch/riscv64/dev/stfpcie.c

719

uint32_t status;

sys/arch/riscv64/dev/stfpcie.c

750

uint32_t status;

sys/arch/riscv64/dev/stfpcie.c

790

uint32_t reg[5];

sys/arch/riscv64/dev/stfpcie.c

791

uint32_t phys_hi;

sys/arch/riscv64/dev/stfpcie.c

934

uint32_t reg[4];

sys/arch/riscv64/dev/stfpciephy.c

102

stfpciephy_enable(void *cookie, uint32_t *cells)

sys/arch/riscv64/dev/stfpciephy.c

62

int stfpciephy_enable(void *, uint32_t *);

sys/arch/riscv64/dev/stfpinctrl.c

106

uint32_t sel;

sys/arch/riscv64/dev/stfpinctrl.c

184

stfpinctrl_jh7100_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/riscv64/dev/stfpinctrl.c

187

uint32_t pin = cells[0];

sys/arch/riscv64/dev/stfpinctrl.c

188

uint32_t reg;

sys/arch/riscv64/dev/stfpinctrl.c

209

stfpinctrl_jh7100_get_pin(void *cookie, uint32_t *cells)

sys/arch/riscv64/dev/stfpinctrl.c

212

uint32_t pin = cells[0];

sys/arch/riscv64/dev/stfpinctrl.c

213

uint32_t flags = cells[1];

sys/arch/riscv64/dev/stfpinctrl.c

214

uint32_t reg;

sys/arch/riscv64/dev/stfpinctrl.c

228

stfpinctrl_jh7100_set_pin(void *cookie, uint32_t *cells, int val)

sys/arch/riscv64/dev/stfpinctrl.c

231

uint32_t pin = cells[0];

sys/arch/riscv64/dev/stfpinctrl.c

232

uint32_t flags = cells[1];

sys/arch/riscv64/dev/stfpinctrl.c

246

stfpinctrl_jh7110_config_pin(void *cookie, uint32_t *cells, int config)

sys/arch/riscv64/dev/stfpinctrl.c

249

uint32_t pin = cells[0];

sys/arch/riscv64/dev/stfpinctrl.c

250

uint32_t doen, padcfg;

sys/arch/riscv64/dev/stfpinctrl.c

280

stfpinctrl_jh7110_get_pin(void *cookie, uint32_t *cells)

sys/arch/riscv64/dev/stfpinctrl.c

283

uint32_t pin = cells[0];

sys/arch/riscv64/dev/stfpinctrl.c

284

uint32_t flags = cells[1];

sys/arch/riscv64/dev/stfpinctrl.c

285

uint32_t reg;

sys/arch/riscv64/dev/stfpinctrl.c

300

stfpinctrl_jh7110_set_pin(void *cookie, uint32_t *cells, int val)

sys/arch/riscv64/dev/stfpinctrl.c

303

uint32_t pin = cells[0];

sys/arch/riscv64/dev/stfpinctrl.c

304

uint32_t flags = cells[1];

sys/arch/riscv64/dev/stfpinctrl.c

305

uint32_t reg;

sys/arch/riscv64/dev/stfpinctrl.c

84

void stfpinctrl_jh7100_config_pin(void *, uint32_t *, int);

sys/arch/riscv64/dev/stfpinctrl.c

85

int stfpinctrl_jh7100_get_pin(void *, uint32_t *);

sys/arch/riscv64/dev/stfpinctrl.c

86

void stfpinctrl_jh7100_set_pin(void *, uint32_t *, int);

sys/arch/riscv64/dev/stfpinctrl.c

88

void stfpinctrl_jh7110_config_pin(void *, uint32_t *, int);

sys/arch/riscv64/dev/stfpinctrl.c

89

int stfpinctrl_jh7110_get_pin(void *, uint32_t *);

sys/arch/riscv64/dev/stfpinctrl.c

90

void stfpinctrl_jh7110_set_pin(void *, uint32_t *, int);

sys/arch/riscv64/dev/stfrng.c

122

uint32_t stat, istat;

sys/arch/riscv64/dev/stftemp.c

155

stftemp_get_temperature(void *cookie, uint32_t *cells)

sys/arch/riscv64/dev/stftemp.c

67

int32_t stftemp_get_temperature(void *, uint32_t *);

sys/arch/riscv64/dev/sxitimer.c

155

uint32_t cycles;

sys/arch/riscv64/dev/sxitimer.c

56

uint32_t sc_ticks_per_second;

sys/arch/riscv64/include/bus.h

521

uint32_t generic_space_read_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);

sys/arch/riscv64/include/bus.h

530

uint32_t);

sys/arch/riscv64/include/cpu.h

108

uint32_t ci_cpu_supply;

sys/arch/riscv64/include/cpu.h

148

extern uint32_t boot_hart; /* The hart we booted on. */

sys/arch/riscv64/include/cpu.h

97

uint32_t ci_cpl;

sys/arch/riscv64/include/cpu.h

98

uint32_t ci_ipending;

sys/arch/riscv64/include/cpu.h

99

uint32_t ci_idepth;

sys/arch/riscv64/include/fdt.h

32

uint32_t *fa_intr;

sys/arch/riscv64/include/ieee.h

96

(a)[0] = (uint32_t)(p)->ext_fracl; \

sys/arch/riscv64/include/ieee.h

97

(a)[1] = (uint32_t)(p)->ext_fraclm; \

sys/arch/riscv64/include/ieee.h

98

(a)[2] = (uint32_t)(p)->ext_frachm; \

sys/arch/riscv64/include/ieee.h

99

(a)[3] = (uint32_t)(p)->ext_frach; \

sys/arch/riscv64/include/intr.h

151

extern uint32_t riscv_smask[NIPL];

sys/arch/riscv64/include/intr.h

175

uint32_t ic_phandle;

sys/arch/riscv64/include/intr.h

176

uint32_t ic_cells;

sys/arch/riscv64/include/pci_machdep.h

127

void pci_msi_enable(pci_chipset_tag_t, pcitag_t, bus_addr_t, uint32_t);

sys/arch/riscv64/include/pci_machdep.h

129

int, bus_addr_t, uint32_t);

sys/arch/riscv64/riscv64/bus_space.c

116

uint32_t v)

sys/arch/riscv64/riscv64/bus_space.c

119

*(volatile uint32_t *)(h + o) = v;

sys/arch/riscv64/riscv64/bus_space.c

163

volatile uint32_t *addr = (volatile uint32_t *)(h + o);

sys/arch/riscv64/riscv64/bus_space.c

166

*(uint32_t *)buf = *addr;

sys/arch/riscv64/riscv64/bus_space.c

176

volatile uint32_t *addr = (volatile uint32_t *)(h + o);

sys/arch/riscv64/riscv64/bus_space.c

180

*addr = *(uint32_t *)buf;

sys/arch/riscv64/riscv64/bus_space.c

80

uint32_t

sys/arch/riscv64/riscv64/bus_space.c

83

uint32_t val = *(volatile uint32_t *)(h + o);

sys/arch/riscv64/riscv64/clock.c

66

uint32_t cycles;

sys/arch/riscv64/riscv64/cpu.c

114

void cpu_opp_init(struct cpu_info *, uint32_t);

sys/arch/riscv64/riscv64/cpu.c

130

uint32_t mvendorid;

sys/arch/riscv64/riscv64/cpu.c

249

uint32_t opp;

sys/arch/riscv64/riscv64/cpu.c

337

uint32_t line, iline, dline;

sys/arch/riscv64/riscv64/cpu.c

338

uint32_t size, isize, dsize;

sys/arch/riscv64/riscv64/cpu.c

339

uint32_t ways, iways, dways;

sys/arch/riscv64/riscv64/cpu.c

340

uint32_t cache;

sys/arch/riscv64/riscv64/cpu.c

619

uint32_t opp_microvolt;

sys/arch/riscv64/riscv64/cpu.c

624

uint32_t ot_phandle;

sys/arch/riscv64/riscv64/cpu.c

641

uint32_t cpu_opp_get_cooling_level(void *, uint32_t *);

sys/arch/riscv64/riscv64/cpu.c

642

void cpu_opp_set_cooling_level(void *, uint32_t *, uint32_t);

sys/arch/riscv64/riscv64/cpu.c

645

cpu_opp_init(struct cpu_info *ci, uint32_t phandle)

sys/arch/riscv64/riscv64/cpu.c

650

uint32_t opp_hz, opp_microvolt;

sys/arch/riscv64/riscv64/cpu.c

651

uint32_t values[3];

sys/arch/riscv64/riscv64/cpu.c

691

if (len == sizeof(uint32_t) || len == 3 * sizeof(uint32_t))

sys/arch/riscv64/riscv64/cpu.c

747

uint32_t curr_microvolt;

sys/arch/riscv64/riscv64/cpu.c

81

uint32_t id;

sys/arch/riscv64/riscv64/cpu.c

825

uint32_t curr_microvolt, opp_microvolt;

sys/arch/riscv64/riscv64/cpu.c

912

uint32_t

sys/arch/riscv64/riscv64/cpu.c

913

cpu_opp_get_cooling_level(void *cookie, uint32_t *cells)

sys/arch/riscv64/riscv64/cpu.c

922

cpu_opp_set_cooling_level(void *cookie, uint32_t *cells, uint32_t level)

sys/arch/riscv64/riscv64/db_disasm.c

358

uint32_t rd, rs1, rs2, rs3;

sys/arch/riscv64/riscv64/db_disasm.c

359

uint32_t val;

sys/arch/riscv64/riscv64/db_disasm.c

585

uint32_t insn;

sys/arch/riscv64/riscv64/db_disasm.c

84

int (*match_func)(struct riscv_op *op, uint32_t insn);

sys/arch/riscv64/riscv64/db_disasm.c

88

m_op(struct riscv_op *op, uint32_t insn)

sys/arch/riscv64/riscv64/intr.c

101

uint32_t phandle = 0;

sys/arch/riscv64/riscv64/intr.c

102

uint32_t *cell;

sys/arch/riscv64/riscv64/intr.c

103

uint32_t *map;

sys/arch/riscv64/riscv64/intr.c

104

uint32_t mask, rid_base, rid;

sys/arch/riscv64/riscv64/intr.c

124

ncells = len / sizeof(uint32_t);

sys/arch/riscv64/riscv64/intr.c

179

uint32_t ip_phandle;

sys/arch/riscv64/riscv64/intr.c

180

uint32_t ip_cell[MAX_INTERRUPT_CELLS];

sys/arch/riscv64/riscv64/intr.c

33

uint32_t riscv_intr_map_msi(int, uint64_t *);

sys/arch/riscv64/riscv64/intr.c

333

uint32_t *cell, *cells, phandle;

sys/arch/riscv64/riscv64/intr.c

342

if (len <= 0 || (len % sizeof(uint32_t) != 0))

sys/arch/riscv64/riscv64/intr.c

362

ncells = len / sizeof(uint32_t);

sys/arch/riscv64/riscv64/intr.c

415

uint32_t *cell;

sys/arch/riscv64/riscv64/intr.c

416

uint32_t map_mask[4], *map;

sys/arch/riscv64/riscv64/intr.c

435

ncells = len / sizeof(uint32_t);

sys/arch/riscv64/riscv64/intr.c

481

uint32_t phandle;

sys/arch/riscv64/riscv64/intr.c

49

uint32_t riscv_smask[NIPL];

sys/arch/riscv64/riscv64/intr.c

83

uint32_t phandle;

sys/arch/riscv64/riscv64/intr.c

97

uint32_t

sys/arch/riscv64/riscv64/machdep.c

534

uint32_t mmap_size;

sys/arch/riscv64/riscv64/machdep.c

535

uint32_t mmap_desc_size;

sys/arch/riscv64/riscv64/machdep.c

536

uint32_t mmap_desc_ver;

sys/arch/riscv64/riscv64/machdep.c

601

if (len == sizeof(uint32_t))

sys/arch/riscv64/riscv64/machdep.c

602

tb_freq = bemtoh32((uint32_t *)prop);

sys/arch/riscv64/riscv64/machdep.c

613

boot_hart = bemtoh32((uint32_t *)prop);

sys/arch/riscv64/riscv64/machdep.c

621

boothowto = bemtoh32((uint32_t *)prop);

sys/arch/riscv64/riscv64/machdep.c

654

mmap_size = bemtoh32((uint32_t *)prop);

sys/arch/riscv64/riscv64/machdep.c

657

mmap_desc_size = bemtoh32((uint32_t *)prop);

sys/arch/riscv64/riscv64/machdep.c

660

mmap_desc_ver = bemtoh32((uint32_t *)prop);

sys/arch/riscv64/riscv64/machdep.c

690

uint32_t csize, size = round_page(fdt_get_size(config));

sys/arch/riscv64/riscv64/machdep.c

706

uint32_t csize, size = round_page(mmap_size);

sys/arch/riscv64/riscv64/machdep.c

96

uint32_t boot_hart; /* The hart we booted on. */

sys/arch/riscv64/riscv64/pmap.c

1238

uint32_t mvendorid;

sys/arch/riscv64/stand/efiboot/efiboot.c

360

uint32_t acells, scells;

sys/arch/riscv64/stand/efiboot/efiboot.c

362

uint32_t reg[4];

sys/arch/riscv64/stand/efiboot/efiboot.c

363

uint32_t width, height, stride;

sys/arch/riscv64/stand/efiboot/efiboot.c

511

uint32_t boothowto = htobe32(howto);

sys/arch/riscv64/stand/efiboot/efiboot.c

604

uint32_t uefi_mmap_size = htobe32(mmap_ndesc * mmap_descsiz);

sys/arch/riscv64/stand/efiboot/efiboot.c

605

uint32_t uefi_mmap_desc_size = htobe32(mmap_descsiz);

sys/arch/riscv64/stand/efiboot/efiboot.c

606

uint32_t uefi_mmap_desc_ver = htobe32(mmap_version);

sys/arch/riscv64/stand/efiboot/efidev.c

270

uint32_t orig_csum, new_csum;

sys/arch/riscv64/stand/efiboot/efidev.c

271

uint32_t ghsize, ghpartsize, ghpartnum, ghpartspersec;

sys/arch/riscv64/stand/efiboot/efidev.c

272

uint32_t gpsectors;

sys/arch/riscv64/stand/efiboot/fdt.c

132

fdt_get_str(uint32_t num)

sys/arch/riscv64/stand/efiboot/fdt.c

142

size_t len = roundup(strlen(name) + 1, sizeof(uint32_t));

sys/arch/riscv64/stand/efiboot/fdt.c

160

skip_nops(uint32_t *ptr)

sys/arch/riscv64/stand/efiboot/fdt.c

169

skip_property(uint32_t *ptr)

sys/arch/riscv64/stand/efiboot/fdt.c

171

uint32_t size;

sys/arch/riscv64/stand/efiboot/fdt.c

175

ptr += 3 + roundup(size, sizeof(uint32_t)) / sizeof(uint32_t);

sys/arch/riscv64/stand/efiboot/fdt.c

181

skip_props(uint32_t *ptr)

sys/arch/riscv64/stand/efiboot/fdt.c

190

skip_node_name(uint32_t *ptr)

sys/arch/riscv64/stand/efiboot/fdt.c

194

sizeof(uint32_t)) / sizeof(uint32_t);

sys/arch/riscv64/stand/efiboot/fdt.c

206

uint32_t *ptr;

sys/arch/riscv64/stand/efiboot/fdt.c

207

uint32_t nameid;

sys/arch/riscv64/stand/efiboot/fdt.c

213

ptr = (uint32_t *)node;

sys/arch/riscv64/stand/efiboot/fdt.c

236

uint32_t *ptr, *next;

sys/arch/riscv64/stand/efiboot/fdt.c

237

uint32_t nameid;

sys/arch/riscv64/stand/efiboot/fdt.c

238

uint32_t curlen;

sys/arch/riscv64/stand/efiboot/fdt.c

245

ptr = (uint32_t *)node;

sys/arch/riscv64/stand/efiboot/fdt.c

258

delta = roundup(len, sizeof(uint32_t)) -

sys/arch/riscv64/stand/efiboot/fdt.c

259

roundup(curlen, sizeof(uint32_t));

sys/arch/riscv64/stand/efiboot/fdt.c

28

char *fdt_get_str(uint32_t);

sys/arch/riscv64/stand/efiboot/fdt.c

286

uint32_t *ptr = (uint32_t *)node;

sys/arch/riscv64/stand/efiboot/fdt.c

29

void *skip_property(uint32_t *);

sys/arch/riscv64/stand/efiboot/fdt.c

291

if (end + 3 * sizeof(uint32_t) > tree.end)

sys/arch/riscv64/stand/efiboot/fdt.c

297

tree.struct_size += 3 * sizeof(uint32_t);

sys/arch/riscv64/stand/efiboot/fdt.c

298

tree.strings += 3 * sizeof(uint32_t);

sys/arch/riscv64/stand/efiboot/fdt.c

30

void *skip_props(uint32_t *);

sys/arch/riscv64/stand/efiboot/fdt.c

31

void *skip_node_name(uint32_t *);

sys/arch/riscv64/stand/efiboot/fdt.c

310

size_t len = roundup(strlen(name) + 1, sizeof(uint32_t)) + 8;

sys/arch/riscv64/stand/efiboot/fdt.c

312

uint32_t *ptr = (uint32_t *)node;

sys/arch/riscv64/stand/efiboot/fdt.c

33

void *skip_nops(uint32_t *);

sys/arch/riscv64/stand/efiboot/fdt.c

338

ptr += (len - 8) / sizeof(uint32_t);

sys/arch/riscv64/stand/efiboot/fdt.c

351

uint32_t *ptr = node;

sys/arch/riscv64/stand/efiboot/fdt.c

373

uint32_t *ptr;

sys/arch/riscv64/stand/efiboot/fdt.c

381

ptr = skip_nops((uint32_t *)tree.tree);

sys/arch/riscv64/stand/efiboot/fdt.c

43

uint32_t *ptr, *tok;

sys/arch/riscv64/stand/efiboot/fdt.c

443

uint32_t *ptr;

sys/arch/riscv64/stand/efiboot/fdt.c

46

ptr = (uint32_t *)fdt;

sys/arch/riscv64/stand/efiboot/fdt.c

467

uint32_t *ptr;

sys/arch/riscv64/stand/efiboot/fdt.c

573

uint32_t *ptr;

sys/arch/riscv64/stand/efiboot/fdt.c

576

uint32_t nameid, size;

sys/arch/riscv64/stand/efiboot/fdt.c

578

ptr = (uint32_t *)node;

sys/arch/riscv64/stand/efiboot/fdt.c

608

if ((cnt % sizeof(uint32_t)) == 0)

sys/arch/riscv64/stand/efiboot/fdt.c

613

ptr += roundup(size, sizeof(uint32_t)) / sizeof(uint32_t);

sys/arch/riscv64/stand/efiboot/fdt.c

622

uint32_t *ptr;

sys/arch/riscv64/stand/efiboot/fdt.c

625

ptr = (uint32_t *)node;

sys/arch/riscv64/stand/efiboot/fdt.h

20

uint32_t fh_magic;

sys/arch/riscv64/stand/efiboot/fdt.h

21

uint32_t fh_size;

sys/arch/riscv64/stand/efiboot/fdt.h

22

uint32_t fh_struct_off;

sys/arch/riscv64/stand/efiboot/fdt.h

23

uint32_t fh_strings_off;

sys/arch/riscv64/stand/efiboot/fdt.h

24

uint32_t fh_reserve_off;

sys/arch/riscv64/stand/efiboot/fdt.h

25

uint32_t fh_version;

sys/arch/riscv64/stand/efiboot/fdt.h

26

uint32_t fh_comp_ver; /* last compatible version */

sys/arch/riscv64/stand/efiboot/fdt.h

27

uint32_t fh_boot_cpu_id; /* fh_version >=2 */

sys/arch/riscv64/stand/efiboot/fdt.h

28

uint32_t fh_strings_size; /* fh_version >=3 */

sys/arch/riscv64/stand/efiboot/fdt.h

29

uint32_t fh_struct_size; /* fh_version >=17 */

sys/arch/riscv64/stand/efiboot/softraid_riscv64.c

424

uint32_t orig_csum, new_csum;

sys/arch/riscv64/stand/efiboot/softraid_riscv64.c

425

uint32_t ghsize, ghpartsize, ghpartnum, ghpartspersec;

sys/arch/riscv64/stand/efiboot/softraid_riscv64.c

426

uint32_t gpsectors;

sys/arch/sh/dev/shpcic.c

1017

bus_size_t offset, const uint32_t *addr, bus_size_t count)

sys/arch/sh/dev/shpcic.c

1047

__shpcic_io_write_4(bsh, offset, *(uint32_t *)addr);

sys/arch/sh/dev/shpcic.c

1071

__shpcic_mem_write_4(bsh, offset, *(uint32_t *)addr);

sys/arch/sh/dev/shpcic.c

1100

bus_size_t offset, uint32_t value, bus_size_t count)

sys/arch/sh/dev/shpcic.c

1127

bus_size_t offset, uint32_t value, bus_size_t count)

sys/arch/sh/dev/shpcic.c

1159

bus_size_t offset, uint32_t value, bus_size_t count)

sys/arch/sh/dev/shpcic.c

1189

bus_size_t offset, uint32_t value, bus_size_t count)

sys/arch/sh/dev/shpcic.c

1260

uint32_t value;

sys/arch/sh/dev/shpcic.c

1341

uint32_t value;

sys/arch/sh/dev/shpcic.c

404

static inline uint32_t __shpcic_io_read_4(bus_space_handle_t bsh,

sys/arch/sh/dev/shpcic.c

410

static inline uint32_t __shpcic_mem_read_4(bus_space_handle_t bsh,

sys/arch/sh/dev/shpcic.c

429

static inline uint32_t

sys/arch/sh/dev/shpcic.c

434

return *(volatile uint32_t *)(SH4_PCIC_IO + adr);

sys/arch/sh/dev/shpcic.c

453

static inline uint32_t

sys/arch/sh/dev/shpcic.c

458

return *(volatile uint32_t *)(SH4_PCIC_MEM + adr);

sys/arch/sh/dev/shpcic.c

484

uint32_t

sys/arch/sh/dev/shpcic.c

487

uint32_t value;

sys/arch/sh/dev/shpcic.c

514

uint32_t

sys/arch/sh/dev/shpcic.c

517

uint32_t value;

sys/arch/sh/dev/shpcic.c

547

bus_size_t offset, uint32_t *addr, bus_size_t count)

sys/arch/sh/dev/shpcic.c

574

bus_size_t offset, uint32_t *addr, bus_size_t count)

sys/arch/sh/dev/shpcic.c

59

uint32_t sp_product;

sys/arch/sh/dev/shpcic.c

602

*(uint32_t *)addr = __shpcic_io_read_4(bsh, offset);

sys/arch/sh/dev/shpcic.c

624

*(uint32_t *)addr = __shpcic_mem_read_4(bsh, offset);

sys/arch/sh/dev/shpcic.c

654

bus_size_t offset, uint32_t *addr, bus_size_t count)

sys/arch/sh/dev/shpcic.c

684

bus_size_t offset, uint32_t *addr, bus_size_t count)

sys/arch/sh/dev/shpcic.c

714

*(uint32_t *)addr = __shpcic_io_read_4(bsh, offset);

sys/arch/sh/dev/shpcic.c

738

*(uint32_t *)addr = __shpcic_mem_read_4(bsh, offset);

sys/arch/sh/dev/shpcic.c

750

bus_size_t offset, uint32_t value);

sys/arch/sh/dev/shpcic.c

756

bus_size_t offset, uint32_t value);

sys/arch/sh/dev/shpcic.c

778

uint32_t value)

sys/arch/sh/dev/shpcic.c

782

*(volatile uint32_t *)(SH4_PCIC_IO + adr) = value;

sys/arch/sh/dev/shpcic.c

805

uint32_t value)

sys/arch/sh/dev/shpcic.c

809

*(volatile uint32_t *)(SH4_PCIC_MEM + adr) = value;

sys/arch/sh/dev/shpcic.c

831

bus_size_t offset, uint32_t value)

sys/arch/sh/dev/shpcic.c

852

bus_size_t offset, uint32_t value)

sys/arch/sh/dev/shpcic.c

880

bus_size_t offset, const uint32_t *addr, bus_size_t count)

sys/arch/sh/dev/shpcic.c

907

bus_size_t offset, const uint32_t *addr, bus_size_t count)

sys/arch/sh/dev/shpcic.c

935

__shpcic_io_write_4(bsh, offset, *(uint32_t *)addr);

sys/arch/sh/dev/shpcic.c

957

__shpcic_mem_write_4(bsh, offset, *(uint32_t *)addr);

sys/arch/sh/dev/shpcic.c

987

bus_size_t offset, const uint32_t *addr, bus_size_t count)

sys/arch/sh/dev/shpcicvar.h

117

bus_size_t offset, uint32_t *addr, bus_size_t count);

sys/arch/sh/dev/shpcicvar.h

123

bus_size_t offset, uint32_t *addr, bus_size_t count);

sys/arch/sh/dev/shpcicvar.h

141

bus_size_t offset, uint32_t data);

sys/arch/sh/dev/shpcicvar.h

147

bus_size_t offset, uint32_t data);

sys/arch/sh/dev/shpcicvar.h

155

bus_size_t offset, const uint32_t *addr, bus_size_t count);

sys/arch/sh/dev/shpcicvar.h

161

bus_size_t offset, const uint32_t *addr, bus_size_t count);

sys/arch/sh/dev/shpcicvar.h

179

bus_size_t offset, const uint32_t *addr, bus_size_t count);

sys/arch/sh/dev/shpcicvar.h

185

bus_size_t offset, const uint32_t *addr, bus_size_t count);

sys/arch/sh/dev/shpcicvar.h

203

bus_size_t offset, uint32_t val, bus_size_t count);

sys/arch/sh/dev/shpcicvar.h

209

bus_size_t offset, uint32_t val, bus_size_t count);

sys/arch/sh/dev/shpcicvar.h

217

bus_size_t offset, uint32_t val, bus_size_t count);

sys/arch/sh/dev/shpcicvar.h

223

bus_size_t offset, uint32_t val, bus_size_t count);

sys/arch/sh/dev/shpcicvar.h

82

uint32_t shpcic_io_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset);

sys/arch/sh/dev/shpcicvar.h

85

uint32_t shpcic_mem_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset);

sys/arch/sh/dev/shpcicvar.h

93

bus_size_t offset, uint32_t *addr, bus_size_t count);

sys/arch/sh/dev/shpcicvar.h

99

bus_size_t offset, uint32_t *addr, bus_size_t count);

sys/arch/sh/include/cache_sh3.h

112

uint32_t __e, __w, __wa, __a; \

sys/arch/sh/include/cache_sh3.h

118

(*(volatile uint32_t *)__a) &= \

sys/arch/sh/include/cache_sh3.h

126

uint32_t __e, __w, __wa, __a; \

sys/arch/sh/include/cache_sh3.h

132

(*(volatile uint32_t *)__a) &= \

sys/arch/sh/include/cpu.h

166

#define SH3_P1SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK)

sys/arch/sh/include/cpu.h

167

#define SH3_P2SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK)

sys/arch/sh/include/cpu.h

168

#define SH3_PHYS_TO_P1SEG(x) ((uint32_t)(x) | SH3_P1SEG_BASE)

sys/arch/sh/include/cpu.h

169

#define SH3_PHYS_TO_P2SEG(x) ((uint32_t)(x) | SH3_P2SEG_BASE)

sys/arch/sh/include/cpu.h

170

#define SH3_P1SEG_TO_P2SEG(x) ((uint32_t)(x) | 0x20000000)

sys/arch/sh/include/cpu.h

171

#define SH3_P2SEG_TO_P1SEG(x) ((uint32_t)(x) & ~0x20000000)

sys/arch/sh/include/cpu.h

183

register uint32_t r0 asm("r0"); \

sys/arch/sh/include/cpu.h

184

uint32_t pc; \

sys/arch/sh/include/cpu.h

205

register uint32_t r0 asm("r0"); \

sys/arch/sh/include/cpu.h

206

uint32_t pc; \

sys/arch/sh/include/cpu.h

241

#define SH4_PVR (*(volatile uint32_t *) SH4_PVR_ADDR)

sys/arch/sh/include/cpu.h

243

#define SH4_PRR (*(volatile uint32_t *) SH4_PRR_ADDR)

sys/arch/sh/include/cpu.h

265

void _cpu_spin(uint32_t); /* for delay loop. */

sys/arch/sh/include/devreg.h

41

#define _reg_read_4(a) (*(volatile uint32_t *)((vaddr_t)(a)))

sys/arch/sh/include/devreg.h

47

(*(volatile uint32_t *)(a) = (uint32_t)(v))

sys/arch/sh/include/devreg.h

53

(*(volatile uint32_t *)(a) |= (uint32_t)(v))

sys/arch/sh/include/devreg.h

59

(*(volatile uint32_t *)(a) &= ~(uint32_t)(v))

sys/arch/sh/include/mmu.h

63

void sh3_tlb_update(int, vaddr_t, uint32_t);

sys/arch/sh/include/mmu.h

71

void sh4_tlb_update(int, vaddr_t, uint32_t);

sys/arch/sh/include/mmu.h

76

extern uint32_t __sh_PTEH;

sys/arch/sh/include/mmu.h

82

extern void (*__sh_tlb_update)(int, vaddr_t, uint32_t);

sys/arch/sh/include/mmu_sh3.h

82

#define SH3_TLB_DISABLE *(volatile uint32_t *)SH3_MMUCR = SH3_MMUCR_TF

sys/arch/sh/include/mmu_sh4.h

146

#define SH4_TLB_DISABLE *(volatile uint32_t *)SH4_MMUCR = SH4_MMUCR_TI

sys/arch/sh/include/proc.h

47

uint32_t addr;

sys/arch/sh/include/proc.h

48

uint32_t data;

sys/arch/sh/include/pte.h

90

typedef uint32_t pt_entry_t;

sys/arch/sh/include/rtcreg.h

100

extern uint32_t __sh_RMONAR;

sys/arch/sh/include/rtcreg.h

101

extern uint32_t __sh_RCR1;

sys/arch/sh/include/rtcreg.h

102

extern uint32_t __sh_RCR2;

sys/arch/sh/include/rtcreg.h

87

extern uint32_t __sh_R64CNT;

sys/arch/sh/include/rtcreg.h

88

extern uint32_t __sh_RSECCNT;

sys/arch/sh/include/rtcreg.h

89

extern uint32_t __sh_RMINCNT;

sys/arch/sh/include/rtcreg.h

90

extern uint32_t __sh_RHRCNT;

sys/arch/sh/include/rtcreg.h

91

extern uint32_t __sh_RWKCNT;

sys/arch/sh/include/rtcreg.h

92

extern uint32_t __sh_RDAYCNT;

sys/arch/sh/include/rtcreg.h

93

extern uint32_t __sh_RMONCNT;

sys/arch/sh/include/rtcreg.h

94

extern uint32_t __sh_RYRCNT;

sys/arch/sh/include/rtcreg.h

95

extern uint32_t __sh_RSECAR;

sys/arch/sh/include/rtcreg.h

96

extern uint32_t __sh_RMINAR;

sys/arch/sh/include/rtcreg.h

97

extern uint32_t __sh_RHRAR;

sys/arch/sh/include/rtcreg.h

98

extern uint32_t __sh_RWKAR;

sys/arch/sh/include/rtcreg.h

99

extern uint32_t __sh_RDAYAR;

sys/arch/sh/include/tmureg.h

100

extern uint32_t __sh_TOCR;

sys/arch/sh/include/tmureg.h

101

extern uint32_t __sh_TSTR;

sys/arch/sh/include/tmureg.h

102

extern uint32_t __sh_TCOR0;

sys/arch/sh/include/tmureg.h

103

extern uint32_t __sh_TCNT0;

sys/arch/sh/include/tmureg.h

104

extern uint32_t __sh_TCR0;

sys/arch/sh/include/tmureg.h

105

extern uint32_t __sh_TCOR1;

sys/arch/sh/include/tmureg.h

106

extern uint32_t __sh_TCNT1;

sys/arch/sh/include/tmureg.h

107

extern uint32_t __sh_TCR1;

sys/arch/sh/include/tmureg.h

108

extern uint32_t __sh_TCOR2;

sys/arch/sh/include/tmureg.h

109

extern uint32_t __sh_TCNT2;

sys/arch/sh/include/tmureg.h

110

extern uint32_t __sh_TCR2;

sys/arch/sh/include/tmureg.h

111

extern uint32_t __sh_TCPR2;

sys/arch/sh/include/trap.h

170

extern uint32_t __sh_TRA;

sys/arch/sh/include/trap.h

171

extern uint32_t __sh_EXPEVT;

sys/arch/sh/include/trap.h

172

extern uint32_t __sh_INTEVT;

sys/arch/sh/include/ubcreg.h

72

extern uint32_t __sh_BARA;

sys/arch/sh/include/ubcreg.h

73

extern uint32_t __sh_BAMRA;

sys/arch/sh/include/ubcreg.h

74

extern uint32_t __sh_BASRA;

sys/arch/sh/include/ubcreg.h

75

extern uint32_t __sh_BBRA;

sys/arch/sh/include/ubcreg.h

76

extern uint32_t __sh_BARB;

sys/arch/sh/include/ubcreg.h

77

extern uint32_t __sh_BAMRB;

sys/arch/sh/include/ubcreg.h

78

extern uint32_t __sh_BASRB;

sys/arch/sh/include/ubcreg.h

79

extern uint32_t __sh_BBRB;

sys/arch/sh/include/ubcreg.h

80

extern uint32_t __sh_BDRB;

sys/arch/sh/include/ubcreg.h

81

extern uint32_t __sh_BDMRB;

sys/arch/sh/include/ubcreg.h

82

extern uint32_t __sh_BRCR;

sys/arch/sh/sh/cache_sh3.c

136

cache_sh3_op_line_16_nway(int n, vaddr_t va, uint32_t bits)

sys/arch/sh/sh/cache_sh3.c

158

cache_sh3_op_8lines_16_nway(int n, vaddr_t va, uint32_t bits)

sys/arch/sh/sh/cache_sh3.c

160

volatile uint32_t *cca;

sys/arch/sh/sh/cache_sh3.c

168

cca = (volatile uint32_t *)

sys/arch/sh/sh/cache_sh3.c

52

static inline void cache_sh3_op_line_16_nway(int, vaddr_t, uint32_t);

sys/arch/sh/sh/cache_sh3.c

53

static inline void cache_sh3_op_8lines_16_nway(int, vaddr_t, uint32_t);

sys/arch/sh/sh/cache_sh3.c

59

uint32_t r;

sys/arch/sh/sh/cache_sh4.c

184

cache_sh4_op_line_32(vaddr_t va, vaddr_t base, uint32_t mask, uint32_t bits)

sys/arch/sh/sh/cache_sh4.c

198

cache_sh4_op_8lines_32(vaddr_t va, vaddr_t base, uint32_t mask, uint32_t bits)

sys/arch/sh/sh/cache_sh4.c

200

volatile uint32_t *cca = (volatile uint32_t *)

sys/arch/sh/sh/cache_sh4.c

350

cache_sh4_emode_op_line_32(vaddr_t va, vaddr_t base, uint32_t mask,

sys/arch/sh/sh/cache_sh4.c

351

uint32_t bits, uint32_t way_shift)

sys/arch/sh/sh/cache_sh4.c

372

cache_sh4_emode_op_8lines_32(vaddr_t va, vaddr_t base, uint32_t mask,

sys/arch/sh/sh/cache_sh4.c

373

uint32_t bits, uint32_t way_shift)

sys/arch/sh/sh/cache_sh4.c

375

volatile uint32_t *cca;

sys/arch/sh/sh/cache_sh4.c

381

cca = (volatile uint32_t *)(base | (0 << way_shift) | va);

sys/arch/sh/sh/cache_sh4.c

391

cca = (volatile uint32_t *)(base | (1 << way_shift) | va);

sys/arch/sh/sh/cache_sh4.c

58

static inline void cache_sh4_op_line_32(vaddr_t, vaddr_t, uint32_t,

sys/arch/sh/sh/cache_sh4.c

59

uint32_t);

sys/arch/sh/sh/cache_sh4.c

60

static inline void cache_sh4_op_8lines_32(vaddr_t, vaddr_t, uint32_t,

sys/arch/sh/sh/cache_sh4.c

61

uint32_t);

sys/arch/sh/sh/cache_sh4.c

63

uint32_t, uint32_t, uint32_t);

sys/arch/sh/sh/cache_sh4.c

65

uint32_t, uint32_t, uint32_t);

sys/arch/sh/sh/cache_sh4.c

73

uint32_t r;

sys/arch/sh/sh/clock.c

114

uint32_t s, t0, cnt_1s;

sys/arch/sh/sh/clock.c

167

uint32_t t1;

sys/arch/sh/sh/clock.c

330

uint32_t i;

sys/arch/sh/sh/clock.c

332

i = (uint32_t)SHREG_WTCNT_R;

sys/arch/sh/sh/clock.c

351

uint32_t i;

sys/arch/sh/sh/clock.c

353

i = (uint32_t)SHREG_WTCNT_R;

sys/arch/sh/sh/clock.c

65

uint32_t hz_cnt; /* clock interrupt interval count */

sys/arch/sh/sh/clock.c

66

uint32_t cpucycle_1us; /* calibrated loop variable (1 us) */

sys/arch/sh/sh/clock.c

67

uint32_t tmuclk; /* source clock of TMU0 (Hz) */

sys/arch/sh/sh/clock.c

73

uint32_t pclock; /* PCLOCK */

sys/arch/sh/sh/clock.c

74

uint32_t cpuclock; /* CPU clock */

sys/arch/sh/sh/clock.c

90

uint32_t maxwdog;

sys/arch/sh/sh/db_interface.c

224

uint32_t r, e;

sys/arch/sh/sh/db_interface.c

241

uint32_t a;

sys/arch/sh/sh/db_interface.c

355

__db_tlbdump_pfn(uint32_t r)

sys/arch/sh/sh/db_interface.c

357

uint32_t pa = (r & SH3_MMUDA_D_PPN_MASK);

sys/arch/sh/sh/db_interface.c

378

__db_tlbdump_page_size_sh4(uint32_t r)

sys/arch/sh/sh/db_interface.c

418

uint32_t r;

sys/arch/sh/sh/db_interface.c

463

uint32_t r, e;

sys/arch/sh/sh/db_interface.c

603

uint32_t *t32;

sys/arch/sh/sh/db_interface.c

621

t32 = (uint32_t *)(pcb->pcb_sf.sf_r7_bank - MAX_STACK);

sys/arch/sh/sh/db_interface.c

64

void __db_tlbdump_page_size_sh4(uint32_t);

sys/arch/sh/sh/db_interface.c

65

void __db_tlbdump_pfn(uint32_t);

sys/arch/sh/sh/db_memrw.c

58

*(uint32_t *)data = *(uint32_t *)src;

sys/arch/sh/sh/db_memrw.c

82

*(uint32_t *)dst = *(const uint32_t *)data;

sys/arch/sh/sh/db_trace.c

84

uint32_t vbr;

sys/arch/sh/sh/devreg.c

43

uint32_t __sh_PTEH;

sys/arch/sh/sh/devreg.c

44

uint32_t __sh_TTB;

sys/arch/sh/sh/devreg.c

45

uint32_t __sh_TEA;

sys/arch/sh/sh/devreg.c

46

uint32_t __sh_TRA;

sys/arch/sh/sh/devreg.c

47

uint32_t __sh_EXPEVT;

sys/arch/sh/sh/devreg.c

48

uint32_t __sh_INTEVT;

sys/arch/sh/sh/devreg.c

51

uint32_t __sh_BARA;

sys/arch/sh/sh/devreg.c

52

uint32_t __sh_BAMRA;

sys/arch/sh/sh/devreg.c

53

uint32_t __sh_BASRA;

sys/arch/sh/sh/devreg.c

54

uint32_t __sh_BBRA;

sys/arch/sh/sh/devreg.c

55

uint32_t __sh_BARB;

sys/arch/sh/sh/devreg.c

56

uint32_t __sh_BAMRB;

sys/arch/sh/sh/devreg.c

57

uint32_t __sh_BASRB;

sys/arch/sh/sh/devreg.c

58

uint32_t __sh_BBRB;

sys/arch/sh/sh/devreg.c

59

uint32_t __sh_BDRB;

sys/arch/sh/sh/devreg.c

60

uint32_t __sh_BDMRB;

sys/arch/sh/sh/devreg.c

61

uint32_t __sh_BRCR;

sys/arch/sh/sh/devreg.c

64

uint32_t __sh_R64CNT;

sys/arch/sh/sh/devreg.c

65

uint32_t __sh_RSECCNT;

sys/arch/sh/sh/devreg.c

66

uint32_t __sh_RMINCNT;

sys/arch/sh/sh/devreg.c

67

uint32_t __sh_RHRCNT;

sys/arch/sh/sh/devreg.c

68

uint32_t __sh_RWKCNT;

sys/arch/sh/sh/devreg.c

69

uint32_t __sh_RDAYCNT;

sys/arch/sh/sh/devreg.c

70

uint32_t __sh_RMONCNT;

sys/arch/sh/sh/devreg.c

71

uint32_t __sh_RYRCNT;

sys/arch/sh/sh/devreg.c

72

uint32_t __sh_RSECAR;

sys/arch/sh/sh/devreg.c

73

uint32_t __sh_RMINAR;

sys/arch/sh/sh/devreg.c

74

uint32_t __sh_RHRAR;

sys/arch/sh/sh/devreg.c

75

uint32_t __sh_RWKAR;

sys/arch/sh/sh/devreg.c

76

uint32_t __sh_RDAYAR;

sys/arch/sh/sh/devreg.c

77

uint32_t __sh_RMONAR;

sys/arch/sh/sh/devreg.c

78

uint32_t __sh_RCR1;

sys/arch/sh/sh/devreg.c

79

uint32_t __sh_RCR2;

sys/arch/sh/sh/devreg.c

82

uint32_t __sh_TOCR;

sys/arch/sh/sh/devreg.c

83

uint32_t __sh_TSTR;

sys/arch/sh/sh/devreg.c

84

uint32_t __sh_TCOR0;

sys/arch/sh/sh/devreg.c

85

uint32_t __sh_TCNT0;

sys/arch/sh/sh/devreg.c

86

uint32_t __sh_TCR0;

sys/arch/sh/sh/devreg.c

87

uint32_t __sh_TCOR1;

sys/arch/sh/sh/devreg.c

88

uint32_t __sh_TCNT1;

sys/arch/sh/sh/devreg.c

89

uint32_t __sh_TCR1;

sys/arch/sh/sh/devreg.c

90

uint32_t __sh_TCOR2;

sys/arch/sh/sh/devreg.c

91

uint32_t __sh_TCNT2;

sys/arch/sh/sh/devreg.c

92

uint32_t __sh_TCR2;

sys/arch/sh/sh/devreg.c

93

uint32_t __sh_TCPR2;

sys/arch/sh/sh/interrupt.c

418

volatile uint32_t *iprreg;

sys/arch/sh/sh/interrupt.c

419

uint32_t r;

sys/arch/sh/sh/interrupt.c

434

iprreg = (volatile uint32_t *)SH4_INTPRI00;

sys/arch/sh/sh/interrupt.c

473

volatile uint32_t *iprreg;

sys/arch/sh/sh/interrupt.c

474

uint32_t bit;

sys/arch/sh/sh/interrupt.c

488

iprreg = (volatile uint32_t *)SH4_INTMSKCLR00;

sys/arch/sh/sh/interrupt.c

522

volatile uint32_t *iprreg;

sys/arch/sh/sh/interrupt.c

523

uint32_t bit;

sys/arch/sh/sh/interrupt.c

537

iprreg = (volatile uint32_t *)SH4_INTMSK00;

sys/arch/sh/sh/locore_c.c

172

uint32_t vpn;

sys/arch/sh/sh/locore_c.c

175

vpn = (uint32_t)p->p_addr;

sys/arch/sh/sh/locore_c.c

197

uint32_t vpn;

sys/arch/sh/sh/locore_c.c

200

vpn = (uint32_t)p->p_addr;

sys/arch/sh/sh/mmu.c

45

void (*__sh_tlb_update)(int, vaddr_t, uint32_t);

sys/arch/sh/sh/mmu.c

77

uint32_t r;

sys/arch/sh/sh/mmu_sh3.c

109

sh3_tlb_update(int asid, vaddr_t va, uint32_t pte)

sys/arch/sh/sh/mmu_sh3.c

111

uint32_t oasid;

sys/arch/sh/sh/mmu_sh3.c

55

uint32_t a, d;

sys/arch/sh/sh/mmu_sh3.c

75

uint32_t aw, a;

sys/arch/sh/sh/mmu_sh3.c

94

uint32_t aw, a;

sys/arch/sh/sh/mmu_sh4.c

100

uint32_t a;

sys/arch/sh/sh/mmu_sh4.c

120

uint32_t a;

sys/arch/sh/sh/mmu_sh4.c

145

sh4_tlb_update(int asid, vaddr_t va, uint32_t pte)

sys/arch/sh/sh/mmu_sh4.c

147

uint32_t oasid;

sys/arch/sh/sh/mmu_sh4.c

148

uint32_t ptel;

sys/arch/sh/sh/mmu_sh4.c

76

uint32_t pteh;

sys/arch/sh/sh/pmap.c

88

uint32_t map[8];

sys/arch/sh/sh/trap.c

142

void general_exception(struct proc *, struct trapframe *, uint32_t);

sys/arch/sh/sh/trap.c

143

void tlb_exception(struct proc *, struct trapframe *, uint32_t);

sys/arch/sh/sh/trap.c

155

general_exception(struct proc *p, struct trapframe *tf, uint32_t va)

sys/arch/sh/sh/trap.c

315

tlb_exception(struct proc *p, struct trapframe *tf, uint32_t va)

sys/arch/sparc64/dev/auxio.c

156

auxio_flip(struct auxio_softc *sc, uint32_t mask, uint32_t set)

sys/arch/sparc64/dev/auxio.c

158

uint32_t led;

sys/arch/sparc64/dev/auxio.c

76

void auxio_flip(struct auxio_softc *, uint32_t, uint32_t);

sys/arch/sparc64/dev/creator.c

236

uint32_t attr;

sys/arch/sparc64/dev/creator.c

58

int creator_ras_erasecols(void *, int, int, int, uint32_t);

sys/arch/sparc64/dev/creator.c

581

creator_ras_eraserows(void *cookie, int row, int n, uint32_t attr)

sys/arch/sparc64/dev/creator.c

59

int creator_ras_eraserows(void *, int, int, uint32_t);

sys/arch/sparc64/dev/creator.c

618

creator_ras_erasecols(void *cookie, int row, int col, int n, uint32_t attr)

sys/arch/sparc64/dev/fb.c

121

int *, int *, uint32_t *);

sys/arch/sparc64/dev/fb.c

314

uint32_t defattr;

sys/arch/sparc64/dev/fb.c

447

void **cookiep, int *curxp, int *curyp, uint32_t *attrp)

sys/arch/sparc64/dev/gfxp.c

122

uint32_t sc_read_mode;

sys/arch/sparc64/dev/gfxp.c

123

uint32_t sc_read_pixel;

sys/arch/sparc64/dev/gfxp.c

151

int gfxp_erasecols(void *, int, int, int, uint32_t);

sys/arch/sparc64/dev/gfxp.c

153

int gfxp_eraserows(void *, int, int, uint32_t);

sys/arch/sparc64/dev/gfxp.c

158

void gfxp_indexed_write(struct gfxp_softc *, bus_size_t, uint32_t);

sys/arch/sparc64/dev/gfxp.c

472

gfxp_erasecols(void *cookie, int row, int col, int num, uint32_t attr)

sys/arch/sparc64/dev/gfxp.c

507

gfxp_eraserows(void *cookie, int row, int num, uint32_t attr)

sys/arch/sparc64/dev/gfxp.c

566

gfxp_indexed_write(struct gfxp_softc *sc, bus_size_t offset, uint32_t value)

sys/arch/sparc64/dev/ifb.c

1020

ifb_erasecols(void *cookie, int row, int col, int num, uint32_t attr)

sys/arch/sparc64/dev/ifb.c

1055

ifb_eraserows(void *cookie, int row, int num, uint32_t attr)

sys/arch/sparc64/dev/ifb.c

1114

uint32_t rop, int32_t planemask)

sys/arch/sparc64/dev/ifb.c

1121

int dx, int dy, int w, int h, uint32_t rop, int32_t planemask)

sys/arch/sparc64/dev/ifb.c

1167

uint32_t rop, int32_t planemask)

sys/arch/sparc64/dev/ifb.c

1182

uint32_t rop, int32_t planemask)

sys/arch/sparc64/dev/ifb.c

1186

uint32_t spr, splr;

sys/arch/sparc64/dev/ifb.c

273

volatile uint32_t *sc_comm;

sys/arch/sparc64/dev/ifb.c

280

void (*sc_rop)(void *, int, int, int, int, int, int, uint32_t, int32_t);

sys/arch/sparc64/dev/ifb.c

326

void ifb_rop(struct ifb_softc *, int, int, int, int, int, int, uint32_t,

sys/arch/sparc64/dev/ifb.c

329

int, int, uint32_t, int32_t);

sys/arch/sparc64/dev/ifb.c

330

void ifb_rop_ifb(void *, int, int, int, int, int, int, uint32_t, int32_t);

sys/arch/sparc64/dev/ifb.c

331

void ifb_rop_jfb(void *, int, int, int, int, int, int, uint32_t, int32_t);

sys/arch/sparc64/dev/ifb.c

334

int ifb_putchar_dumb(void *, int, int, u_int, uint32_t);

sys/arch/sparc64/dev/ifb.c

336

int ifb_erasecols_dumb(void *, int, int, int, uint32_t);

sys/arch/sparc64/dev/ifb.c

338

int ifb_eraserows_dumb(void *, int, int, uint32_t);

sys/arch/sparc64/dev/ifb.c

342

int ifb_erasecols(void *, int, int, int, uint32_t);

sys/arch/sparc64/dev/ifb.c

344

int ifb_eraserows(void *, int, int, uint32_t);

sys/arch/sparc64/dev/ifb.c

359

uint32_t dev_comm;

sys/arch/sparc64/dev/ifb.c

452

sc->sc_comm = (volatile uint32_t *)(vaddr_t)dev_comm;

sys/arch/sparc64/dev/ifb.c

777

uint32_t dpms;

sys/arch/sparc64/dev/ifb.c

847

ifb_putchar_dumb(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/arch/sparc64/dev/ifb.c

875

ifb_erasecols_dumb(void *cookie, int row, int col, int num, uint32_t attr)

sys/arch/sparc64/dev/ifb.c

903

ifb_eraserows_dumb(void *cookie, int row, int num, uint32_t attr)

sys/arch/sparc64/dev/ldcvar.h

49

uint32_t seqid;

sys/arch/sparc64/dev/ldcvar.h

53

uint32_t _reserved[13];

sys/arch/sparc64/dev/ldcvar.h

96

uint32_t lc_tx_seqid;

sys/arch/sparc64/dev/machfb.c

218

int machfb_erasecols(void *, int, int, int, uint32_t);

sys/arch/sparc64/dev/machfb.c

220

int machfb_eraserows(void *, int, int, uint32_t);

sys/arch/sparc64/dev/machfb.c

533

machfb_erasecols(void *cookie, int row, int col, int num, uint32_t attr)

sys/arch/sparc64/dev/machfb.c

568

machfb_eraserows(void *cookie, int row, int num, uint32_t attr)

sys/arch/sparc64/dev/machfb.c

595

uint32_t reg;

sys/arch/sparc64/dev/machfb.c

727

uint32_t dest_ctl = 0;

sys/arch/sparc64/dev/pci_machdep.c

562

int vec, bus_addr_t addr, uint32_t data)

sys/arch/sparc64/dev/pci_machdep.c

567

uint32_t ctrl;

sys/arch/sparc64/dev/pcons.c

473

int *, int *, uint32_t *);

sys/arch/sparc64/dev/pcons.c

478

int pcons_putchar(void *, int, int, u_int, uint32_t);

sys/arch/sparc64/dev/pcons.c

510

int *curxp, int *curyp, uint32_t *attrp)

sys/arch/sparc64/dev/pcons.c

584

pcons_putchar(void *v, int row, int col, u_int uc, uint32_t attr)

sys/arch/sparc64/dev/radeonfb.c

145

int radeonfb_erasecols(void *, int, int, int, uint32_t);

sys/arch/sparc64/dev/radeonfb.c

147

int radeonfb_eraserows(void *, int, int, uint32_t);

sys/arch/sparc64/dev/radeonfb.c

472

radeonfb_erasecols(void *cookie, int row, int col, int num, uint32_t attr)

sys/arch/sparc64/dev/radeonfb.c

507

radeonfb_eraserows(void *cookie, int row, int num, uint32_t attr)

sys/arch/sparc64/dev/radeonfb.c

584

uint32_t gmc;

sys/arch/sparc64/dev/radeonfb.c

585

uint32_t dir;

sys/arch/sparc64/dev/radeonfb.c

637

uint32_t gmc;

sys/arch/sparc64/dev/raptor.c

157

int raptor_erasecols(void *, int, int, int, uint32_t);

sys/arch/sparc64/dev/raptor.c

159

int raptor_eraserows(void *, int, int, uint32_t);

sys/arch/sparc64/dev/raptor.c

444

raptor_erasecols(void *cookie, int row, int col, int num, uint32_t attr)

sys/arch/sparc64/dev/raptor.c

479

raptor_eraserows(void *cookie, int row, int num, uint32_t attr)

sys/arch/sparc64/dev/sbbc.c

101

uint32_t cons_magic;

sys/arch/sparc64/dev/sbbc.c

102

uint32_t cons_version;

sys/arch/sparc64/dev/sbbc.c

103

uint32_t cons_size;

sys/arch/sparc64/dev/sbbc.c

105

uint32_t cons_in_begin;

sys/arch/sparc64/dev/sbbc.c

106

uint32_t cons_in_end;

sys/arch/sparc64/dev/sbbc.c

107

uint32_t cons_in_rdptr;

sys/arch/sparc64/dev/sbbc.c

108

uint32_t cons_in_wrptr;

sys/arch/sparc64/dev/sbbc.c

110

uint32_t cons_out_begin;

sys/arch/sparc64/dev/sbbc.c

111

uint32_t cons_out_end;

sys/arch/sparc64/dev/sbbc.c

112

uint32_t cons_out_rdptr;

sys/arch/sparc64/dev/sbbc.c

113

uint32_t cons_out_wrptr;

sys/arch/sparc64/dev/sbbc.c

126

uint32_t sc_sram_toc;

sys/arch/sparc64/dev/sbbc.c

133

uint32_t *sc_sram_solscie;

sys/arch/sparc64/dev/sbbc.c

134

uint32_t *sc_sram_solscir;

sys/arch/sparc64/dev/sbbc.c

135

uint32_t *sc_sram_scsolie;

sys/arch/sparc64/dev/sbbc.c

136

uint32_t *sc_sram_scsolir;

sys/arch/sparc64/dev/sbbc.c

157

void sbbc_attach_tod(struct sbbc_softc *, uint32_t);

sys/arch/sparc64/dev/sbbc.c

161

void sbbc_attach_cons(struct sbbc_softc *, uint32_t);

sys/arch/sparc64/dev/sbbc.c

162

void sbbc_intr_cons(struct sbbc_softc *, uint32_t);

sys/arch/sparc64/dev/sbbc.c

255

sc->sc_sram_solscie = (uint32_t *)

sys/arch/sparc64/dev/sbbc.c

258

sc->sc_sram_solscir = (uint32_t *)

sys/arch/sparc64/dev/sbbc.c

261

sc->sc_sram_scsolie = (uint32_t *)

sys/arch/sparc64/dev/sbbc.c

264

sc->sc_sram_scsolir = (uint32_t *)

sys/arch/sparc64/dev/sbbc.c

289

uint32_t status, reason;

sys/arch/sparc64/dev/sbbc.c

316

sbbc_attach_tod(struct sbbc_softc *sc, uint32_t offset)

sys/arch/sparc64/dev/sbbc.c

359

sbbc_attach_cons(struct sbbc_softc *sc, uint32_t offset)

sys/arch/sparc64/dev/sbbc.c

422

sbbc_intr_cons(struct sbbc_softc *sc, uint32_t reason)

sys/arch/sparc64/dev/sbbc.c

440

uint32_t rdptr = cons->cons_in_rdptr;

sys/arch/sparc64/dev/sbbc.c

462

uint32_t rdptr = cons->cons_in_rdptr;

sys/arch/sparc64/dev/sbbc.c

491

uint32_t wrptr = cons->cons_out_wrptr;

sys/arch/sparc64/dev/sbbc.c

72

uint32_t tag_size;

sys/arch/sparc64/dev/sbbc.c

73

uint32_t tag_offset;

sys/arch/sparc64/dev/sbbc.c

81

uint32_t toc_ntags;

sys/arch/sparc64/dev/sbbc.c

87

uint32_t tod_magic;

sys/arch/sparc64/dev/sbbc.c

88

uint32_t tod_version;

sys/arch/sparc64/dev/sbbc.c

91

uint32_t tod_reserved;

sys/arch/sparc64/dev/sbbc.c

92

uint32_t tod_heartbeat;

sys/arch/sparc64/dev/sbbc.c

93

uint32_t tod_timeout;

sys/arch/sparc64/dev/vcctty.c

48

uint32_t ctrl_msg;

sys/arch/sparc64/dev/vdsk.c

150

uint32_t sc_local_sid;

sys/arch/sparc64/dev/vdsk.c

164

uint32_t sc_vdisk_block_size;

sys/arch/sparc64/dev/vdsk.c

53

uint32_t vdisk_block_size;

sys/arch/sparc64/dev/vdsk.c

94

uint32_t status;

sys/arch/sparc64/dev/vdsk.c

97

uint32_t ncookies;

sys/arch/sparc64/dev/vdsk.c

98

uint32_t _reserved2;

sys/arch/sparc64/dev/vdsp.c

123

uint32_t reserved;

sys/arch/sparc64/dev/vdsp.c

132

uint32_t reserved;

sys/arch/sparc64/dev/vdsp.c

157

uint32_t status;

sys/arch/sparc64/dev/vdsp.c

160

uint32_t ncookies;

sys/arch/sparc64/dev/vdsp.c

161

uint32_t _reserved2;

sys/arch/sparc64/dev/vdsp.c

175

uint32_t status;

sys/arch/sparc64/dev/vdsp.c

178

uint32_t ncookies;

sys/arch/sparc64/dev/vdsp.c

179

uint32_t _reserved2;

sys/arch/sparc64/dev/vdsp.c

230

uint32_t sc_local_sid;

sys/arch/sparc64/dev/vdsp.c

234

uint32_t sc_num_descriptors;

sys/arch/sparc64/dev/vdsp.c

235

uint32_t sc_descriptor_size;

sys/arch/sparc64/dev/vdsp.c

255

uint32_t sc_vdisk_block_size;

sys/arch/sparc64/dev/vdsp.c

72

uint32_t vdisk_block_size;

sys/arch/sparc64/dev/viovar.h

112

uint32_t start_idx;

sys/arch/sparc64/dev/viovar.h

113

uint32_t end_idx;

sys/arch/sparc64/dev/viovar.h

26

uint32_t sid;

sys/arch/sparc64/dev/viovar.h

34

uint32_t sid;

sys/arch/sparc64/dev/viovar.h

79

uint32_t num_descriptors;

sys/arch/sparc64/dev/viovar.h

80

uint32_t descriptor_size;

sys/arch/sparc64/dev/viovar.h

83

uint32_t ncookies;

sys/arch/sparc64/dev/vnet.c

101

uint32_t nbytes;

sys/arch/sparc64/dev/vnet.c

102

uint32_t ncookies;

sys/arch/sparc64/dev/vnet.c

1056

vnet_send_dring_data(struct vnet_softc *sc, uint32_t start_idx)

sys/arch/sparc64/dev/vnet.c

163

uint32_t sc_local_sid;

sys/arch/sparc64/dev/vnet.c

220

void vnet_send_dring_data(struct vnet_softc *, uint32_t);

sys/arch/sparc64/dev/vnet.c

68

uint32_t _reserved1;

sys/arch/sparc64/dev/vnet.c

87

uint32_t _reserved;

sys/arch/sparc64/dev/vnet.c

92

uint32_t nbytes;

sys/arch/sparc64/dev/vnet.c

93

uint32_t ncookies;

sys/arch/sparc64/dev/vpci.c

43

uint32_t mm_version;

sys/arch/sparc64/include/hypervisor.h

70

uint32_t td_size;

sys/arch/sparc64/include/hypervisor.h

71

uint32_t td_ctxidx;

sys/arch/sparc64/include/hypervisor.h

72

uint32_t td_pgsz;

sys/arch/sparc64/include/ieee.h

96

(a)[0] = (uint32_t)(p)->ext_fracl; \

sys/arch/sparc64/include/ieee.h

97

(a)[1] = (uint32_t)(p)->ext_fraclm; \

sys/arch/sparc64/include/ieee.h

98

(a)[2] = (uint32_t)(p)->ext_frachm; \

sys/arch/sparc64/include/ieee.h

99

(a)[3] = (uint32_t)(p)->ext_frach; \

sys/arch/sparc64/include/mdesc.h

19

uint32_t transport_version;

sys/arch/sparc64/include/mdesc.h

20

uint32_t node_blk_sz;

sys/arch/sparc64/include/mdesc.h

21

uint32_t name_blk_sz;

sys/arch/sparc64/include/mdesc.h

22

uint32_t data_blk_sz;

sys/arch/sparc64/include/mdesc.h

29

uint32_t name_offset;

sys/arch/sparc64/include/mdesc.h

32

uint32_t data_len;

sys/arch/sparc64/include/mdesc.h

33

uint32_t data_offset;

sys/arch/sparc64/include/pci_machdep.h

117

int, bus_addr_t, uint32_t);

sys/arch/sparc64/include/pmap.h

166

int pmap_copyinsn(pmap_t, vaddr_t, uint32_t *);

sys/arch/sparc64/sparc64/clock.c

598

uint32_t cycles;

sys/arch/sparc64/sparc64/clock.c

634

uint32_t cycles;

sys/arch/sparc64/sparc64/clock.c

667

uint32_t cycles;

sys/arch/sparc64/sparc64/pmap.c

2888

pmap_copyinsn(pmap_t pmap, vaddr_t va, uint32_t *insn)

sys/arch/sparc64/sparc64/trap.c

1125

if (pmap_copyinsn(map->pmap, uva, (uint32_t *)insn) == 0)

sys/arch/sparc64/stand/ofwboot/boot.c

74

uint32_t boot_debug = 0

sys/crypto/aes.c

107

uint32_t x0, x1, x2, x3, x4, x5, x6, x7;

sys/crypto/aes.c

108

uint32_t y1, y2, y3, y4, y5, y6, y7, y8, y9;

sys/crypto/aes.c

109

uint32_t y10, y11, y12, y13, y14, y15, y16, y17, y18, y19;

sys/crypto/aes.c

110

uint32_t y20, y21;

sys/crypto/aes.c

111

uint32_t z0, z1, z2, z3, z4, z5, z6, z7, z8, z9;

sys/crypto/aes.c

112

uint32_t z10, z11, z12, z13, z14, z15, z16, z17;

sys/crypto/aes.c

113

uint32_t t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;

sys/crypto/aes.c

114

uint32_t t10, t11, t12, t13, t14, t15, t16, t17, t18, t19;

sys/crypto/aes.c

115

uint32_t t20, t21, t22, t23, t24, t25, t26, t27, t28, t29;

sys/crypto/aes.c

116

uint32_t t30, t31, t32, t33, t34, t35, t36, t37, t38, t39;

sys/crypto/aes.c

117

uint32_t t40, t41, t42, t43, t44, t45, t46, t47, t48, t49;

sys/crypto/aes.c

118

uint32_t t50, t51, t52, t53, t54, t55, t56, t57, t58, t59;

sys/crypto/aes.c

119

uint32_t t60, t61, t62, t63, t64, t65, t66, t67;

sys/crypto/aes.c

120

uint32_t s0, s1, s2, s3, s4, s5, s6, s7;

sys/crypto/aes.c

279

aes_ct_ortho(uint32_t *q)

sys/crypto/aes.c

282

uint32_t a, b; \

sys/crypto/aes.c

285

(x) = (a & (uint32_t)cl) | ((b & (uint32_t)cl) << (s)); \

sys/crypto/aes.c

286

(y) = ((a & (uint32_t)ch) >> (s)) | (b & (uint32_t)ch); \

sys/crypto/aes.c

309

static inline uint32_t

sys/crypto/aes.c

310

sub_word(uint32_t x)

sys/crypto/aes.c

312

uint32_t q[8];

sys/crypto/aes.c

334

aes_keysched_base(uint32_t *skey, const void *key, size_t key_len)

sys/crypto/aes.c

338

uint32_t tmp;

sys/crypto/aes.c

35

enc32le(void *dst, uint32_t x)

sys/crypto/aes.c

384

aes_ct_keysched(uint32_t *comp_skey, const void *key, size_t key_len)

sys/crypto/aes.c

386

uint32_t skey[60];

sys/crypto/aes.c

391

uint32_t q[8];

sys/crypto/aes.c

416

aes_ct_skey_expand(uint32_t *skey,

sys/crypto/aes.c

417

unsigned num_rounds, const uint32_t *comp_skey)

sys/crypto/aes.c

423

uint32_t x, y;

sys/crypto/aes.c

434

add_round_key(uint32_t *q, const uint32_t *sk)

sys/crypto/aes.c

447

shift_rows(uint32_t *q)

sys/crypto/aes.c

45

static inline uint32_t

sys/crypto/aes.c

452

uint32_t x;

sys/crypto/aes.c

462

static inline uint32_t

sys/crypto/aes.c

463

rotr16(uint32_t x)

sys/crypto/aes.c

469

mix_columns(uint32_t *q)

sys/crypto/aes.c

471

uint32_t q0, q1, q2, q3, q4, q5, q6, q7;

sys/crypto/aes.c

472

uint32_t r0, r1, r2, r3, r4, r5, r6, r7;

sys/crypto/aes.c

50

return (uint32_t)buf[0]

sys/crypto/aes.c

508

const uint32_t *skey, uint32_t *q)

sys/crypto/aes.c

51

| ((uint32_t)buf[1] << 8)

sys/crypto/aes.c

52

| ((uint32_t)buf[2] << 16)

sys/crypto/aes.c

528

aes_ct_bitslice_invSbox(uint32_t *q)

sys/crypto/aes.c

53

| ((uint32_t)buf[3] << 24);

sys/crypto/aes.c

548

uint32_t q0, q1, q2, q3, q4, q5, q6, q7;

sys/crypto/aes.c

588

inv_shift_rows(uint32_t *q)

sys/crypto/aes.c

593

uint32_t x;

sys/crypto/aes.c

604

inv_mix_columns(uint32_t *q)

sys/crypto/aes.c

606

uint32_t q0, q1, q2, q3, q4, q5, q6, q7;

sys/crypto/aes.c

607

uint32_t r0, r1, r2, r3, r4, r5, r6, r7;

sys/crypto/aes.c

643

const uint32_t *skey, uint32_t *q)

sys/crypto/aes.c

675

uint32_t q[8];

sys/crypto/aes.c

718

uint32_t q[8];

sys/crypto/aes.c

769

AES_KeySetup_Encrypt(uint32_t *skey, const uint8_t *key, int len)

sys/crypto/aes.c

772

uint32_t tkey[60];

sys/crypto/aes.c

779

uint32_t w;

sys/crypto/aes.c

794

static inline uint32_t

sys/crypto/aes.c

795

redgf256(uint32_t x)

sys/crypto/aes.c

797

uint32_t h;

sys/crypto/aes.c

806

static inline uint32_t

sys/crypto/aes.c

807

mul9(uint32_t x)

sys/crypto/aes.c

815

static inline uint32_t

sys/crypto/aes.c

816

mulb(uint32_t x)

sys/crypto/aes.c

824

static inline uint32_t

sys/crypto/aes.c

825

muld(uint32_t x)

sys/crypto/aes.c

833

static inline uint32_t

sys/crypto/aes.c

834

mule(uint32_t x)

sys/crypto/aes.c

840

AES_KeySetup_Decrypt(uint32_t *skey, const uint8_t *key, int len)

sys/crypto/aes.c

843

uint32_t tkey[60];

sys/crypto/aes.c

858

memcpy(skey + (r << 2), tkey, 4 * sizeof(uint32_t));

sys/crypto/aes.c

859

memcpy(skey, tkey + (r << 2), 4 * sizeof(uint32_t));

sys/crypto/aes.c

861

uint32_t sk, sk0, sk1, sk2, sk3;

sys/crypto/aes.c

862

uint32_t tk, tk0, tk1, tk2, tk3;

sys/crypto/aes.c

95

aes_ct_bitslice_Sbox(uint32_t *q)

sys/crypto/aes.h

35

uint32_t sk[60];

sys/crypto/aes.h

36

uint32_t sk_exp[120];

sys/crypto/aes.h

47

int AES_KeySetup_Encrypt(uint32_t *, const uint8_t *, int);

sys/crypto/aes.h

48

int AES_KeySetup_Decrypt(uint32_t *, const uint8_t *, int);

sys/crypto/blake2s.c

100

uint32_t m[16];

sys/crypto/blake2s.c

101

uint32_t v[16];

sys/crypto/blake2s.c

206

uint8_t x_key[BLAKE2S_BLOCK_SIZE] __aligned(__alignof__(uint32_t)) = { 0 };

sys/crypto/blake2s.c

207

uint8_t i_hash[BLAKE2S_HASH_SIZE] __aligned(__alignof__(uint32_t));

sys/crypto/blake2s.c

27

static inline uint32_t

sys/crypto/blake2s.c

28

ror32(uint32_t word, unsigned int shift)

sys/crypto/blake2s.c

33

static const uint32_t blake2s_iv[8] = {

sys/crypto/blake2s.c

57

const uint32_t inc)

sys/crypto/blake2s.c

64

const uint32_t param)

sys/crypto/blake2s.c

98

const uint32_t inc)

sys/crypto/blake2s.h

31

uint32_t h[8];

sys/crypto/blake2s.h

32

uint32_t t[2];

sys/crypto/blake2s.h

33

uint32_t f[2];

sys/crypto/chacha_private.h

59

uint32_t x[] = {

sys/crypto/chachapoly.c

222

uint32_t derived_key[CHACHA20POLY1305_KEY_SIZE / sizeof(uint32_t)];

sys/crypto/chachapoly.c

248

uint32_t derived_key[CHACHA20POLY1305_KEY_SIZE / sizeof(uint32_t)];

sys/crypto/cryptosoft.c

482

uint32_t blkbuf[howmany(EALG_MAX_BLOCK_LEN, sizeof(uint32_t))];

sys/crypto/cryptosoft.c

493

uint32_t *blkp;

sys/crypto/cryptosoft.c

622

blkp = (uint32_t *)blk + 1;

sys/crypto/cryptosoft.c

624

blkp = (uint32_t *)blk + 3;

sys/crypto/cryptosoft.c

631

blkp = (uint32_t *)blk;

sys/crypto/cryptosoft.c

633

blkp = (uint32_t *)blk + 2;

sys/crypto/curve25519.c

102

addcarryx_u26(uint8_t /*bool*/ c, uint32_t a, uint32_t b, uint32_t *low)

sys/crypto/curve25519.c

107

uint32_t x = a + b + c;

sys/crypto/curve25519.c

113

subborrow_u25(uint8_t /*bool*/ c, uint32_t a, uint32_t b, uint32_t *low)

sys/crypto/curve25519.c

118

uint32_t x = a - b - c;

sys/crypto/curve25519.c

124

subborrow_u26(uint8_t /*bool*/ c, uint32_t a, uint32_t b, uint32_t *low)

sys/crypto/curve25519.c

129

uint32_t x = a - b - c;

sys/crypto/curve25519.c

134

static __always_inline uint32_t cmovznz32(uint32_t t, uint32_t z, uint32_t nz)

sys/crypto/curve25519.c

140

static __always_inline void fe_freeze(uint32_t out[10], const uint32_t in1[10])

sys/crypto/curve25519.c

142

const uint32_t x17 = in1[9];

sys/crypto/curve25519.c

143

const uint32_t x18 = in1[8];

sys/crypto/curve25519.c

144

const uint32_t x16 = in1[7];

sys/crypto/curve25519.c

145

const uint32_t x14 = in1[6];

sys/crypto/curve25519.c

146

const uint32_t x12 = in1[5];

sys/crypto/curve25519.c

147

const uint32_t x10 = in1[4];

sys/crypto/curve25519.c

148

const uint32_t x8 = in1[3];

sys/crypto/curve25519.c

149

const uint32_t x6 = in1[2];

sys/crypto/curve25519.c

150

const uint32_t x4 = in1[1];

sys/crypto/curve25519.c

151

const uint32_t x2 = in1[0];

sys/crypto/curve25519.c

152

uint32_t x20; uint8_t/*bool*/ x21 = subborrow_u26(0x0, x2, 0x3ffffed, &x20);

sys/crypto/curve25519.c

153

uint32_t x23; uint8_t/*bool*/ x24 = subborrow_u25(x21, x4, 0x1ffffff, &x23);

sys/crypto/curve25519.c

154

uint32_t x26; uint8_t/*bool*/ x27 = subborrow_u26(x24, x6, 0x3ffffff, &x26);

sys/crypto/curve25519.c

155

uint32_t x29; uint8_t/*bool*/ x30 = subborrow_u25(x27, x8, 0x1ffffff, &x29);

sys/crypto/curve25519.c

156

uint32_t x32; uint8_t/*bool*/ x33 = subborrow_u26(x30, x10, 0x3ffffff, &x32);

sys/crypto/curve25519.c

157

uint32_t x35; uint8_t/*bool*/ x36 = subborrow_u25(x33, x12, 0x1ffffff, &x35);

sys/crypto/curve25519.c

158

uint32_t x38; uint8_t/*bool*/ x39 = subborrow_u26(x36, x14, 0x3ffffff, &x38);

sys/crypto/curve25519.c

159

uint32_t x41; uint8_t/*bool*/ x42 = subborrow_u25(x39, x16, 0x1ffffff, &x41);

sys/crypto/curve25519.c

160

uint32_t x44; uint8_t/*bool*/ x45 = subborrow_u26(x42, x18, 0x3ffffff, &x44);

sys/crypto/curve25519.c

161

uint32_t x47; uint8_t/*bool*/ x48 = subborrow_u25(x45, x17, 0x1ffffff, &x47);

sys/crypto/curve25519.c

162

uint32_t x49 = cmovznz32(x48, 0x0, 0xffffffff);

sys/crypto/curve25519.c

163

uint32_t x50 = (x49 & 0x3ffffed);

sys/crypto/curve25519.c

164

uint32_t x52; uint8_t/*bool*/ x53 = addcarryx_u26(0x0, x20, x50, &x52);

sys/crypto/curve25519.c

165

uint32_t x54 = (x49 & 0x1ffffff);

sys/crypto/curve25519.c

166

uint32_t x56; uint8_t/*bool*/ x57 = addcarryx_u25(x53, x23, x54, &x56);

sys/crypto/curve25519.c

167

uint32_t x58 = (x49 & 0x3ffffff);

sys/crypto/curve25519.c

168

uint32_t x60; uint8_t/*bool*/ x61 = addcarryx_u26(x57, x26, x58, &x60);

sys/crypto/curve25519.c

169

uint32_t x62 = (x49 & 0x1ffffff);

sys/crypto/curve25519.c

170

uint32_t x64; uint8_t/*bool*/ x65 = addcarryx_u25(x61, x29, x62, &x64);

sys/crypto/curve25519.c

171

uint32_t x66 = (x49 & 0x3ffffff);

sys/crypto/curve25519.c

172

uint32_t x68; uint8_t/*bool*/ x69 = addcarryx_u26(x65, x32, x66, &x68);

sys/crypto/curve25519.c

173

uint32_t x70 = (x49 & 0x1ffffff);

sys/crypto/curve25519.c

174

uint32_t x72; uint8_t/*bool*/ x73 = addcarryx_u25(x69, x35, x70, &x72);

sys/crypto/curve25519.c

175

uint32_t x74 = (x49 & 0x3ffffff);

sys/crypto/curve25519.c

176

uint32_t x76; uint8_t/*bool*/ x77 = addcarryx_u26(x73, x38, x74, &x76);

sys/crypto/curve25519.c

177

uint32_t x78 = (x49 & 0x1ffffff);

sys/crypto/curve25519.c

178

uint32_t x80; uint8_t/*bool*/ x81 = addcarryx_u25(x77, x41, x78, &x80);

sys/crypto/curve25519.c

179

uint32_t x82 = (x49 & 0x3ffffff);

sys/crypto/curve25519.c

180

uint32_t x84; uint8_t/*bool*/ x85 = addcarryx_u26(x81, x44, x82, &x84);

sys/crypto/curve25519.c

181

uint32_t x86 = (x49 & 0x1ffffff);

sys/crypto/curve25519.c

182

uint32_t x88; addcarryx_u25(x85, x47, x86, &x88);

sys/crypto/curve25519.c

197

uint32_t h[10];

sys/crypto/curve25519.c

236

memmove(h, f, sizeof(uint32_t) * 10);

sys/crypto/curve25519.c

241

memmove(h, f, sizeof(uint32_t) * 10);

sys/crypto/curve25519.c

247

memset(h, 0, sizeof(uint32_t) * 10);

sys/crypto/curve25519.c

253

memset(h, 0, sizeof(uint32_t) * 10);

sys/crypto/curve25519.c

257

static void fe_add_impl(uint32_t out[10], const uint32_t in1[10], const uint32_t in2[10])

sys/crypto/curve25519.c

259

const uint32_t x20 = in1[9];

sys/crypto/curve25519.c

260

const uint32_t x21 = in1[8];

sys/crypto/curve25519.c

261

const uint32_t x19 = in1[7];

sys/crypto/curve25519.c

262

const uint32_t x17 = in1[6];

sys/crypto/curve25519.c

263

const uint32_t x15 = in1[5];

sys/crypto/curve25519.c

264

const uint32_t x13 = in1[4];

sys/crypto/curve25519.c

265

const uint32_t x11 = in1[3];

sys/crypto/curve25519.c

266

const uint32_t x9 = in1[2];

sys/crypto/curve25519.c

267

const uint32_t x7 = in1[1];

sys/crypto/curve25519.c

268

const uint32_t x5 = in1[0];

sys/crypto/curve25519.c

269

const uint32_t x38 = in2[9];

sys/crypto/curve25519.c

270

const uint32_t x39 = in2[8];

sys/crypto/curve25519.c

271

const uint32_t x37 = in2[7];

sys/crypto/curve25519.c

272

const uint32_t x35 = in2[6];

sys/crypto/curve25519.c

273

const uint32_t x33 = in2[5];

sys/crypto/curve25519.c

274

const uint32_t x31 = in2[4];

sys/crypto/curve25519.c

275

const uint32_t x29 = in2[3];

sys/crypto/curve25519.c

276

const uint32_t x27 = in2[2];

sys/crypto/curve25519.c

277

const uint32_t x25 = in2[1];

sys/crypto/curve25519.c

278

const uint32_t x23 = in2[0];

sys/crypto/curve25519.c

299

static void fe_sub_impl(uint32_t out[10], const uint32_t in1[10], const uint32_t in2[10])

sys/crypto/curve25519.c

301

const uint32_t x20 = in1[9];

sys/crypto/curve25519.c

302

const uint32_t x21 = in1[8];

sys/crypto/curve25519.c

303

const uint32_t x19 = in1[7];

sys/crypto/curve25519.c

304

const uint32_t x17 = in1[6];

sys/crypto/curve25519.c

305

const uint32_t x15 = in1[5];

sys/crypto/curve25519.c

306

const uint32_t x13 = in1[4];

sys/crypto/curve25519.c

307

const uint32_t x11 = in1[3];

sys/crypto/curve25519.c

308

const uint32_t x9 = in1[2];

sys/crypto/curve25519.c

309

const uint32_t x7 = in1[1];

sys/crypto/curve25519.c

310

const uint32_t x5 = in1[0];

sys/crypto/curve25519.c

311

const uint32_t x38 = in2[9];

sys/crypto/curve25519.c

312

const uint32_t x39 = in2[8];

sys/crypto/curve25519.c

313

const uint32_t x37 = in2[7];

sys/crypto/curve25519.c

314

const uint32_t x35 = in2[6];

sys/crypto/curve25519.c

315

const uint32_t x33 = in2[5];

sys/crypto/curve25519.c

316

const uint32_t x31 = in2[4];

sys/crypto/curve25519.c

317

const uint32_t x29 = in2[3];

sys/crypto/curve25519.c

318

const uint32_t x27 = in2[2];

sys/crypto/curve25519.c

319

const uint32_t x25 = in2[1];

sys/crypto/curve25519.c

320

const uint32_t x23 = in2[0];

sys/crypto/curve25519.c

341

static void fe_mul_impl(uint32_t out[10], const uint32_t in1[10], const uint32_t in2[10])

sys/crypto/curve25519.c

343

const uint32_t x20 = in1[9];

sys/crypto/curve25519.c

344

const uint32_t x21 = in1[8];

sys/crypto/curve25519.c

345

const uint32_t x19 = in1[7];

sys/crypto/curve25519.c

346

const uint32_t x17 = in1[6];

sys/crypto/curve25519.c

347

const uint32_t x15 = in1[5];

sys/crypto/curve25519.c

348

const uint32_t x13 = in1[4];

sys/crypto/curve25519.c

349

const uint32_t x11 = in1[3];

sys/crypto/curve25519.c

350

const uint32_t x9 = in1[2];

sys/crypto/curve25519.c

351

const uint32_t x7 = in1[1];

sys/crypto/curve25519.c

352

const uint32_t x5 = in1[0];

sys/crypto/curve25519.c

353

const uint32_t x38 = in2[9];

sys/crypto/curve25519.c

354

const uint32_t x39 = in2[8];

sys/crypto/curve25519.c

355

const uint32_t x37 = in2[7];

sys/crypto/curve25519.c

356

const uint32_t x35 = in2[6];

sys/crypto/curve25519.c

357

const uint32_t x33 = in2[5];

sys/crypto/curve25519.c

358

const uint32_t x31 = in2[4];

sys/crypto/curve25519.c

359

const uint32_t x29 = in2[3];

sys/crypto/curve25519.c

360

const uint32_t x27 = in2[2];

sys/crypto/curve25519.c

361

const uint32_t x25 = in2[1];

sys/crypto/curve25519.c

362

const uint32_t x23 = in2[0];

sys/crypto/curve25519.c

410

uint32_t x87 = ((uint32_t)x85 & 0x3ffffff);

sys/crypto/curve25519.c

413

uint32_t x90 = ((uint32_t)x88 & 0x1ffffff);

sys/crypto/curve25519.c

416

uint32_t x93 = ((uint32_t)x91 & 0x3ffffff);

sys/crypto/curve25519.c

419

uint32_t x96 = ((uint32_t)x94 & 0x1ffffff);

sys/crypto/curve25519.c

42

static __always_inline uint32_t get_unaligned_le32(const uint8_t *a)

sys/crypto/curve25519.c

422

uint32_t x99 = ((uint32_t)x97 & 0x3ffffff);

sys/crypto/curve25519.c

425

uint32_t x102 = ((uint32_t)x100 & 0x1ffffff);

sys/crypto/curve25519.c

428

uint32_t x105 = ((uint32_t)x103 & 0x3ffffff);

sys/crypto/curve25519.c

431

uint32_t x108 = ((uint32_t)x106 & 0x1ffffff);

sys/crypto/curve25519.c

434

uint32_t x111 = ((uint32_t)x109 & 0x3ffffff);

sys/crypto/curve25519.c

437

uint32_t x114 = ((uint32_t)x112 & 0x1ffffff);

sys/crypto/curve25519.c

439

uint32_t x116 = (uint32_t) (x115 >> 0x1a);

sys/crypto/curve25519.c

44

uint32_t l;

sys/crypto/curve25519.c

440

uint32_t x117 = ((uint32_t)x115 & 0x3ffffff);

sys/crypto/curve25519.c

441

uint32_t x118 = (x116 + x90);

sys/crypto/curve25519.c

442

uint32_t x119 = (x118 >> 0x19);

sys/crypto/curve25519.c

443

uint32_t x120 = (x118 & 0x1ffffff);

sys/crypto/curve25519.c

472

static void fe_sqr_impl(uint32_t out[10], const uint32_t in1[10])

sys/crypto/curve25519.c

474

const uint32_t x17 = in1[9];

sys/crypto/curve25519.c

475

const uint32_t x18 = in1[8];

sys/crypto/curve25519.c

476

const uint32_t x16 = in1[7];

sys/crypto/curve25519.c

477

const uint32_t x14 = in1[6];

sys/crypto/curve25519.c

478

const uint32_t x12 = in1[5];

sys/crypto/curve25519.c

479

const uint32_t x10 = in1[4];

sys/crypto/curve25519.c

480

const uint32_t x8 = in1[3];

sys/crypto/curve25519.c

481

const uint32_t x6 = in1[2];

sys/crypto/curve25519.c

482

const uint32_t x4 = in1[1];

sys/crypto/curve25519.c

483

const uint32_t x2 = in1[0];

sys/crypto/curve25519.c

531

uint32_t x66 = ((uint32_t)x64 & 0x3ffffff);

sys/crypto/curve25519.c

534

uint32_t x69 = ((uint32_t)x67 & 0x1ffffff);

sys/crypto/curve25519.c

537

uint32_t x72 = ((uint32_t)x70 & 0x3ffffff);

sys/crypto/curve25519.c

540

uint32_t x75 = ((uint32_t)x73 & 0x1ffffff);

sys/crypto/curve25519.c

543

uint32_t x78 = ((uint32_t)x76 & 0x3ffffff);

sys/crypto/curve25519.c

546

uint32_t x81 = ((uint32_t)x79 & 0x1ffffff);

sys/crypto/curve25519.c

549

uint32_t x84 = ((uint32_t)x82 & 0x3ffffff);

sys/crypto/curve25519.c

55

typedef struct fe { uint32_t v[10]; } fe;

sys/crypto/curve25519.c

552

uint32_t x87 = ((uint32_t)x85 & 0x1ffffff);

sys/crypto/curve25519.c

555

uint32_t x90 = ((uint32_t)x88 & 0x3ffffff);

sys/crypto/curve25519.c

558

uint32_t x93 = ((uint32_t)x91 & 0x1ffffff);

sys/crypto/curve25519.c

560

uint32_t x95 = (uint32_t) (x94 >> 0x1a);

sys/crypto/curve25519.c

561

uint32_t x96 = ((uint32_t)x94 & 0x3ffffff);

sys/crypto/curve25519.c

562

uint32_t x97 = (x95 + x69);

sys/crypto/curve25519.c

563

uint32_t x98 = (x97 >> 0x19);

sys/crypto/curve25519.c

564

uint32_t x99 = (x97 & 0x1ffffff);

sys/crypto/curve25519.c

60

typedef struct fe_loose { uint32_t v[10]; } fe_loose;

sys/crypto/curve25519.c

62

static __always_inline void fe_frombytes_impl(uint32_t h[10], const uint8_t *s)

sys/crypto/curve25519.c

65

uint32_t a0 = get_unaligned_le32(s);

sys/crypto/curve25519.c

654

uint32_t x = f->v[i] ^ g->v[i];

sys/crypto/curve25519.c

66

uint32_t a1 = get_unaligned_le32(s+4);

sys/crypto/curve25519.c

662

static __always_inline void fe_mul_121666_impl(uint32_t out[10], const uint32_t in1[10])

sys/crypto/curve25519.c

664

const uint32_t x20 = in1[9];

sys/crypto/curve25519.c

665

const uint32_t x21 = in1[8];

sys/crypto/curve25519.c

666

const uint32_t x19 = in1[7];

sys/crypto/curve25519.c

667

const uint32_t x17 = in1[6];

sys/crypto/curve25519.c

668

const uint32_t x15 = in1[5];

sys/crypto/curve25519.c

669

const uint32_t x13 = in1[4];

sys/crypto/curve25519.c

67

uint32_t a2 = get_unaligned_le32(s+8);

sys/crypto/curve25519.c

670

const uint32_t x11 = in1[3];

sys/crypto/curve25519.c

671

const uint32_t x9 = in1[2];

sys/crypto/curve25519.c

672

const uint32_t x7 = in1[1];

sys/crypto/curve25519.c

673

const uint32_t x5 = in1[0];

sys/crypto/curve25519.c

674

const uint32_t x38 = 0;

sys/crypto/curve25519.c

675

const uint32_t x39 = 0;

sys/crypto/curve25519.c

676

const uint32_t x37 = 0;

sys/crypto/curve25519.c

677

const uint32_t x35 = 0;

sys/crypto/curve25519.c

678

const uint32_t x33 = 0;

sys/crypto/curve25519.c

679

const uint32_t x31 = 0;

sys/crypto/curve25519.c

68

uint32_t a3 = get_unaligned_le32(s+12);

sys/crypto/curve25519.c

680

const uint32_t x29 = 0;

sys/crypto/curve25519.c

681

const uint32_t x27 = 0;

sys/crypto/curve25519.c

682

const uint32_t x25 = 0;

sys/crypto/curve25519.c

683

const uint32_t x23 = 121666;

sys/crypto/curve25519.c

69

uint32_t a4 = get_unaligned_le32(s+16);

sys/crypto/curve25519.c

70

uint32_t a5 = get_unaligned_le32(s+20);

sys/crypto/curve25519.c

71

uint32_t a6 = get_unaligned_le32(s+24);

sys/crypto/curve25519.c

72

uint32_t a7 = get_unaligned_le32(s+28);

sys/crypto/curve25519.c

731

uint32_t x87 = ((uint32_t)x85 & 0x3ffffff);

sys/crypto/curve25519.c

734

uint32_t x90 = ((uint32_t)x88 & 0x1ffffff);

sys/crypto/curve25519.c

737

uint32_t x93 = ((uint32_t)x91 & 0x3ffffff);

sys/crypto/curve25519.c

740

uint32_t x96 = ((uint32_t)x94 & 0x1ffffff);

sys/crypto/curve25519.c

743

uint32_t x99 = ((uint32_t)x97 & 0x3ffffff);

sys/crypto/curve25519.c

746

uint32_t x102 = ((uint32_t)x100 & 0x1ffffff);

sys/crypto/curve25519.c

749

uint32_t x105 = ((uint32_t)x103 & 0x3ffffff);

sys/crypto/curve25519.c

752

uint32_t x108 = ((uint32_t)x106 & 0x1ffffff);

sys/crypto/curve25519.c

755

uint32_t x111 = ((uint32_t)x109 & 0x3ffffff);

sys/crypto/curve25519.c

758

uint32_t x114 = ((uint32_t)x112 & 0x1ffffff);

sys/crypto/curve25519.c

760

uint32_t x116 = (uint32_t) (x115 >> 0x1a);

sys/crypto/curve25519.c

761

uint32_t x117 = ((uint32_t)x115 & 0x3ffffff);

sys/crypto/curve25519.c

762

uint32_t x118 = (x116 + x90);

sys/crypto/curve25519.c

763

uint32_t x119 = (x118 >> 0x19);

sys/crypto/curve25519.c

764

uint32_t x120 = (x118 & 0x1ffffff);

sys/crypto/curve25519.c

91

addcarryx_u25(uint8_t /*bool*/ c, uint32_t a, uint32_t b, uint32_t *low)

sys/crypto/curve25519.c

96

uint32_t x = a + b + c;

sys/crypto/gmac.c

137

uint32_t blk[4] = { 0, 0, 0, 0 };

sys/crypto/gmac.c

31

void ghash_gfmul(uint32_t *, uint32_t *, uint32_t *);

sys/crypto/gmac.c

39

ghash_gfmul(uint32_t *X, uint32_t *Y, uint32_t *product)

sys/crypto/gmac.c

41

uint32_t v[4];

sys/crypto/gmac.c

42

uint32_t z[4] = { 0, 0, 0, 0};

sys/crypto/gmac.c

44

uint32_t mask;

sys/crypto/gmac.c

78

uint32_t *x = (uint32_t *)X;

sys/crypto/gmac.c

79

uint32_t *s = (uint32_t *)ctx->S;

sys/crypto/gmac.c

80

uint32_t *y = (uint32_t *)ctx->Z;

sys/crypto/gmac.c

89

ghash_gfmul((uint32_t *)ctx->S, (uint32_t *)ctx->H,

sys/crypto/gmac.c

90

(uint32_t *)ctx->S);

sys/crypto/siphash.h

58

uint32_t bytes;

sys/ddb/db_ctf.c

183

uint32_t

sys/ddb/db_ctf.c

187

uint32_t tlen;

sys/ddb/db_ctf.c

206

tlen += sizeof(uint32_t);

sys/ddb/db_ctf.c

209

tlen += sizeof(uint32_t);

sys/ddb/db_ctf.c

258

uint32_t toff;

sys/ddb/db_ctf.c

316

uint32_t objtoff;

sys/ddb/db_ctf.c

346

uint32_t off, toff;

sys/ddb/db_ctf.c

381

uint32_t offset = db_ctf.cth->cth_typeoff;

sys/ddb/db_ctf.c

389

uint32_t toff;

sys/ddb/db_ctf.c

417

uint32_t eob, toff, i;

sys/ddb/db_ctf.c

49

uint32_t ctf_found;

sys/ddb/db_ctf.c

512

uint32_t toff;

sys/ddb/db_ctf.c

54

static const char *db_ctf_off2name(uint32_t);

sys/ddb/db_ctf.c

567

uint32_t toff;

sys/ddb/db_ctf.c

58

uint32_t db_ctf_type_len(const struct ctf_type *);

sys/ddb/db_ctf.c

631

db_ctf_off2name(uint32_t offset)

sys/ddb/db_dwarf.c

228

uint32_t unitsize;

sys/ddb/db_dwarf.c

237

uint32_t header_size;

sys/ddb/db_dwarf.c

298

uint32_t address32;

sys/ddb/db_dwarf.c

91

read_u32(struct dwbuf *d, uint32_t *v)

sys/dev/acpi/acpi.c

192

uint32_t val = pci_conf_read(pc, tag, reg & ~0x3);

sys/dev/acpi/acpi.c

199

uint32_t val = pci_conf_read(pc, tag, reg & ~0x2);

sys/dev/acpi/acpi.c

203

uint32_t

sys/dev/acpi/acpi.c

2069

uint32_t reset_as, reset_len;

sys/dev/acpi/acpi.c

2070

uint32_t value;

sys/dev/acpi/acpi.c

212

uint32_t tmp = pci_conf_read(pc, tag, reg & ~0x3);

sys/dev/acpi/acpi.c

2174

uint32_t processed = 0, idx, jdx;

sys/dev/acpi/acpi.c

221

uint32_t tmp = pci_conf_read(pc, tag, reg & ~0x2);

sys/dev/acpi/acpi.c

228

acpi_pci_conf_write_4(pci_chipset_tag_t pc, pcitag_t tag, int reg, uint32_t val)

sys/dev/acpi/acpi.c

2630

uint32_t acpi_force_bm;

sys/dev/acpi/acpi.c

278

*(uint32_t *)(pb + reg) =

sys/dev/acpi/acpi.c

302

*(uint32_t *)(pb + reg));

sys/dev/acpi/acpi.c

348

*(uint32_t *)(pb + idx) =

sys/dev/acpi/acpi.c

368

*(uint32_t *)(pb + idx));

sys/dev/acpi/acpi.c

610

uint32_t reg;

sys/dev/acpi/acpicpu_x86.c

1080

uint32_t status = 0;

sys/dev/acpi/acpicpu_x86.c

123

uint32_t sc_pblk_addr;

sys/dev/acpi/acpicpu_x86.c

146

uint32_t sc_pct_stat_as;

sys/dev/acpi/acpicpu_x86.c

147

uint32_t sc_pct_ctrl_as;

sys/dev/acpi/acpicpu_x86.c

148

uint32_t sc_pct_stat_len;

sys/dev/acpi/acpicpu_x86.c

149

uint32_t sc_pct_ctrl_len;

sys/dev/acpi/acpicpu_x86.c

200

uint32_t pbval;

sys/dev/acpi/acpicpu_x86.c

234

uint32_t cap;

sys/dev/acpi/acpicpu_x86.c

235

uint32_t buf[3];

sys/dev/acpi/acpicpu_x86.c

290

buf[1] = (*(uint32_t *)&res.v_buffer[4]) & cap;

sys/dev/acpi/acpicpu_x86.c

696

uint32_t status = 0;

sys/dev/acpi/acpicpu_x86.c

758

extern uint32_t acpi_force_bm;

sys/dev/acpi/acpidev.h

100

uint32_t bix_min_avg;

sys/dev/acpi/acpidev.h

101

uint32_t bix_cap_granu1;

sys/dev/acpi/acpidev.h

102

uint32_t bix_cap_granu2;

sys/dev/acpi/acpidev.h

137

uint32_t bst_state;

sys/dev/acpi/acpidev.h

141

uint32_t bst_rate;

sys/dev/acpi/acpidev.h

143

uint32_t bst_capacity;

sys/dev/acpi/acpidev.h

144

uint32_t bst_voltage;

sys/dev/acpi/acpidev.h

178

uint32_t bmd_status;

sys/dev/acpi/acpidev.h

184

uint32_t bmd_capability;

sys/dev/acpi/acpidev.h

190

uint32_t bmd_recalibrate_count;

sys/dev/acpi/acpidev.h

192

uint32_t bmd_quick_recalibrate_time;

sys/dev/acpi/acpidev.h

194

uint32_t bmd_slow_recalibrate_time;

sys/dev/acpi/acpidev.h

261

uint32_t pss_core_freq;

sys/dev/acpi/acpidev.h

262

uint32_t pss_power;

sys/dev/acpi/acpidev.h

263

uint32_t pss_trans_latency;

sys/dev/acpi/acpidev.h

264

uint32_t pss_bus_latency;

sys/dev/acpi/acpidev.h

265

uint32_t pss_ctrl;

sys/dev/acpi/acpidev.h

266

uint32_t pss_status;

sys/dev/acpi/acpidev.h

374

uint32_t sc_gpe;

sys/dev/acpi/acpidev.h

83

uint32_t bix_power_unit;

sys/dev/acpi/acpidev.h

86

uint32_t bix_capacity;

sys/dev/acpi/acpidev.h

88

uint32_t bix_last_capacity;

sys/dev/acpi/acpidev.h

89

uint32_t bix_technology;

sys/dev/acpi/acpidev.h

92

uint32_t bix_voltage;

sys/dev/acpi/acpidev.h

93

uint32_t bix_warning;

sys/dev/acpi/acpidev.h

94

uint32_t bix_low;

sys/dev/acpi/acpidev.h

95

uint32_t bix_cycle_count;

sys/dev/acpi/acpidev.h

96

uint32_t bix_accuracy;

sys/dev/acpi/acpidev.h

97

uint32_t bix_max_sample;

sys/dev/acpi/acpidev.h

98

uint32_t bix_min_sample;

sys/dev/acpi/acpidev.h

99

uint32_t bix_max_avg;

sys/dev/acpi/acpidmar.c

123

static uint32_t sid_flag[MAX_DEVFN];

sys/dev/acpi/acpidmar.c

1815

uint32_t sts;

sys/dev/acpi/acpidmar.c

1880

uint32_t sts;

sys/dev/acpi/acpidmar.c

2004

uint32_t

sys/dev/acpi/acpidmar.c

2007

uint32_t v;

sys/dev/acpi/acpidmar.c

2014

iommu_write_4(struct iommu_softc *iommu, int reg, uint32_t v)

sys/dev/acpi/acpidmar.c

2016

bus_space_write_4(iommu->iot, iommu->ioh, reg, (uint32_t)v);

sys/dev/acpi/acpidmar.c

217

uint32_t gcmd;

sys/dev/acpi/acpidmar.c

252

uint32_t wait_seq;

sys/dev/acpi/acpidmar.c

2847

uint32_t head, tail;

sys/dev/acpi/acpidmar.c

2870

uint32_t head, tail, next;

sys/dev/acpi/acpidmar.c

2994

wq.dw2 = (uint32_t)token;

sys/dev/acpi/acpidmar.c

2995

wq.dw3 = (uint32_t)(token >> 32);

sys/dev/acpi/acpidmar.c

3027

cmd.dw2 = (uint32_t)(iova & ~0xfffULL);

sys/dev/acpi/acpidmar.c

3028

cmd.dw3 = (uint32_t)(iova >> 32);

sys/dev/acpi/acpidmar.c

3054

cmd.dw2 = (uint32_t)(addr & ~0xfffULL);

sys/dev/acpi/acpidmar.c

3055

cmd.dw3 = (uint32_t)(addr >> 32);

sys/dev/acpi/acpidmar.c

336

void iommu_write_4(struct iommu_softc *, int, uint32_t);

sys/dev/acpi/acpidmar.c

337

uint32_t iommu_read_4(struct iommu_softc *, int);

sys/dev/acpi/acpidmar.c

3682

uint32_t sts;

sys/dev/acpi/acpidmar.c

697

(uint32_t)segs[i].ds_len);

sys/dev/acpi/acpidmar.c

729

(uint64_t)base, (uint32_t)alen);

sys/dev/acpi/acpidmar.c

758

dom->exname, (uint64_t)base, (uint32_t)alen);

sys/dev/acpi/acpidmar.c

844

(uint64_t)seg->ds_addr, (uint32_t)seg->ds_len,

sys/dev/acpi/acpidmar.h

234

iommu_rmw32(void *ov, uint32_t mask, uint32_t shift, uint32_t nv)

sys/dev/acpi/acpidmar.h

236

*(uint32_t *)ov &= ~(mask << shift);

sys/dev/acpi/acpidmar.h

237

*(uint32_t *)ov |= (nv & mask) << shift;

sys/dev/acpi/acpidmar.h

241

iommu_rmw64(void *ov, uint32_t mask, uint32_t shift, uint64_t nv)

sys/dev/acpi/acpidmar.h

36

#define _xfld(x,y) (uint32_t)(((x)>> y##_SHIFT) & y##_MASK)

sys/dev/acpi/acpige.c

33

uint32_t ai_irq;

sys/dev/acpi/acpihpet.c

211

uint32_t v1, v2;

sys/dev/acpi/acpihpet.c

258

HPET_CAPABILITIES + sizeof(uint32_t));

sys/dev/acpi/acpihpet.c

289

uint32_t val1, val2;

sys/dev/acpi/acpihpet.c

72

uint32_t sc_conf;

sys/dev/acpi/acpihve.c

31

uint32_t entropy[16];

sys/dev/acpi/acpimadt.c

152

acpimadt_cfg_intr(int flags, uint32_t *redir)

sys/dev/acpi/acpimadt.c

55

int acpimadt_cfg_intr(int, uint32_t *);

sys/dev/acpi/acpireg.h

104

uint32_t firmware_ctl; /* phys addr FACS */

sys/dev/acpi/acpireg.h

105

uint32_t dsdt; /* phys addr DSDT */

sys/dev/acpi/acpireg.h

119

uint32_t smi_cmd; /* SMI command port */

sys/dev/acpi/acpireg.h

124

uint32_t pm1a_evt_blk; /* power management 1a */

sys/dev/acpi/acpireg.h

125

uint32_t pm1b_evt_blk; /* power management 1b */

sys/dev/acpi/acpireg.h

126

uint32_t pm1a_cnt_blk; /* pm control 1a */

sys/dev/acpi/acpireg.h

127

uint32_t pm1b_cnt_blk; /* pm control 1b */

sys/dev/acpi/acpireg.h

128

uint32_t pm2_cnt_blk; /* pm control 2 */

sys/dev/acpi/acpireg.h

129

uint32_t pm_tmr_blk;

sys/dev/acpi/acpireg.h

130

uint32_t gpe0_blk;

sys/dev/acpi/acpireg.h

131

uint32_t gpe1_blk;

sys/dev/acpi/acpireg.h

155

uint32_t flags;

sys/dev/acpi/acpireg.h

226

uint32_t local_apic_address;

sys/dev/acpi/acpireg.h

227

uint32_t flags;

sys/dev/acpi/acpireg.h

237

uint32_t flags;

sys/dev/acpi/acpireg.h

247

uint32_t address;

sys/dev/acpi/acpireg.h

248

uint32_t global_int_base;

sys/dev/acpi/acpireg.h

258

uint32_t global_int;

sys/dev/acpi/acpireg.h

275

uint32_t global_int;

sys/dev/acpi/acpireg.h

301

uint32_t global_int_base;

sys/dev/acpi/acpireg.h

313

uint32_t flags; /* Same flags as acpi_madt_lapic */

sys/dev/acpi/acpireg.h

314

uint32_t acpi_proc_uid;

sys/dev/acpi/acpireg.h

33

uint32_t rsdt; /* physical */

sys/dev/acpi/acpireg.h

330

uint32_t global_int;

sys/dev/acpi/acpireg.h

331

uint32_t platform_int_flags;

sys/dev/acpi/acpireg.h

340

uint32_t apic_id;

sys/dev/acpi/acpireg.h

341

uint32_t flags; /* Same flags as acpi_madt_lapic */

sys/dev/acpi/acpireg.h

342

uint32_t acpi_proc_uid;

sys/dev/acpi/acpireg.h

350

uint32_t apic_proc_uid;

sys/dev/acpi/acpireg.h

360

uint32_t gic_id;

sys/dev/acpi/acpireg.h

361

uint32_t acpi_proc_uid;

sys/dev/acpi/acpireg.h

362

uint32_t flags;

sys/dev/acpi/acpireg.h

363

uint32_t parking_protocol_version;

sys/dev/acpi/acpireg.h

364

uint32_t performance_interrupt;

sys/dev/acpi/acpireg.h

369

uint32_t maintenance_interrupt;

sys/dev/acpi/acpireg.h

395

uint32_t warning_energy_level;

sys/dev/acpi/acpireg.h

396

uint32_t low_energy_level;

sys/dev/acpi/acpireg.h

397

uint32_t critical_energy_level;

sys/dev/acpi/acpireg.h

405

uint32_t uid;

sys/dev/acpi/acpireg.h

413

uint32_t reserved1;

sys/dev/acpi/acpireg.h

426

uint32_t event_timer_block_id;

sys/dev/acpi/acpireg.h

43

uint32_t rsdp_length; /* length of rsdp */

sys/dev/acpi/acpireg.h

444

uint32_t reserved1;

sys/dev/acpi/acpireg.h

459

uint32_t gsiv;

sys/dev/acpi/acpireg.h

471

uint32_t pci_flags;

sys/dev/acpi/acpireg.h

473

uint32_t reserved3;

sys/dev/acpi/acpireg.h

479

uint32_t length;

sys/dev/acpi/acpireg.h

480

uint32_t hardware_signature;

sys/dev/acpi/acpireg.h

481

uint32_t wakeup_vector;

sys/dev/acpi/acpireg.h

482

uint32_t global_lock;

sys/dev/acpi/acpireg.h

485

uint32_t flags;

sys/dev/acpi/acpireg.h

495

uint32_t reserved;

sys/dev/acpi/acpireg.h

497

uint32_t start_method;

sys/dev/acpi/acpireg.h

510

uint32_t type;

sys/dev/acpi/acpireg.h

511

uint32_t length;

sys/dev/acpi/acpireg.h

514

uint32_t flags;

sys/dev/acpi/acpireg.h

518

uint32_t residency;

sys/dev/acpi/acpireg.h

519

uint32_t latency;

sys/dev/acpi/acpireg.h

52

uint32_t length;

sys/dev/acpi/acpireg.h

62

uint32_t oemrevision;

sys/dev/acpi/acpireg.h

653

uint32_t extdata;

sys/dev/acpi/acpireg.h

66

uint32_t aslcompilerrevision;

sys/dev/acpi/acpireg.h

704

uint32_t feature;

sys/dev/acpi/acpireg.h

716

uint32_t attrib;

sys/dev/acpi/acpireg.h

73

uint32_t table_offsets[1];

sys/dev/acpi/acpireg.h

740

uint32_t ivinfo;

sys/dev/acpi/acpireg.h

752

uint32_t number_of_nodes;

sys/dev/acpi/acpireg.h

753

uint32_t offset;

sys/dev/acpi/acpireg.h

754

uint32_t reserved;

sys/dev/acpi/acpireg.h

766

uint32_t reserved1;

sys/dev/acpi/acpireg.h

767

uint32_t number_of_mappings;

sys/dev/acpi/acpireg.h

768

uint32_t mapping_offset;

sys/dev/acpi/acpireg.h

772

uint32_t number_of_itss;

sys/dev/acpi/acpireg.h

773

uint32_t its_ids[];

sys/dev/acpi/acpireg.h

777

uint32_t node_flags;

sys/dev/acpi/acpireg.h

785

uint32_t ats_attributes;

sys/dev/acpi/acpireg.h

786

uint32_t segment;

sys/dev/acpi/acpireg.h

794

uint32_t model;

sys/dev/acpi/acpireg.h

801

uint32_t flags;

sys/dev/acpi/acpireg.h

804

uint32_t global_interrupt_offset;

sys/dev/acpi/acpireg.h

805

uint32_t number_of_context_interrupts;

sys/dev/acpi/acpireg.h

806

uint32_t context_interrupt_offset;

sys/dev/acpi/acpireg.h

807

uint32_t number_of_pmu_interrupts;

sys/dev/acpi/acpireg.h

808

uint32_t pmu_interrupt_offset;

sys/dev/acpi/acpireg.h

812

uint32_t nsgirpt_gsiv;

sys/dev/acpi/acpireg.h

813

uint32_t nsgirpt_flags;

sys/dev/acpi/acpireg.h

815

uint32_t nscfgirpt_gsiv;

sys/dev/acpi/acpireg.h

816

uint32_t nscfgirpt_flags;

sys/dev/acpi/acpireg.h

820

uint32_t gsiv;

sys/dev/acpi/acpireg.h

821

uint32_t flags;

sys/dev/acpi/acpireg.h

825

uint32_t gsiv;

sys/dev/acpi/acpireg.h

826

uint32_t flags;

sys/dev/acpi/acpireg.h

831

uint32_t flags;

sys/dev/acpi/acpireg.h

836

uint32_t reserved;

sys/dev/acpi/acpireg.h

838

uint32_t model;

sys/dev/acpi/acpireg.h

842

uint32_t event;

sys/dev/acpi/acpireg.h

843

uint32_t pri;

sys/dev/acpi/acpireg.h

844

uint32_t gerr;

sys/dev/acpi/acpireg.h

845

uint32_t sync;

sys/dev/acpi/acpireg.h

846

uint32_t proximity_domain;

sys/dev/acpi/acpireg.h

847

uint32_t deviceid_mapping_index;

sys/dev/acpi/acpireg.h

851

uint32_t input_base;

sys/dev/acpi/acpireg.h

852

uint32_t number_of_ids;

sys/dev/acpi/acpireg.h

853

uint32_t output_base;

sys/dev/acpi/acpireg.h

854

uint32_t output_reference;

sys/dev/acpi/acpireg.h

855

uint32_t flags;

sys/dev/acpi/acpitimer.c

117

uint32_t mask = acpi_timecounter.tc_counter_mask;

sys/dev/acpi/acpitimer.c

118

uint32_t val1, val2;

sys/dev/acpi/acpitimer.c

136

uint32_t

sys/dev/acpi/acpitimer.c

139

uint32_t u1, u2, u3;

sys/dev/acpi/acpitimer.c

41

uint32_t acpitimer_read(struct acpitimer_softc *);

sys/dev/acpi/acpitoshiba.c

101

int toshiba_get_brightness(struct acpitoshiba_softc *, uint32_t *);

sys/dev/acpi/acpitoshiba.c

102

int toshiba_set_brightness(struct acpitoshiba_softc *, uint32_t *);

sys/dev/acpi/acpitoshiba.c

103

int toshiba_get_video_output(struct acpitoshiba_softc *, uint32_t *);

sys/dev/acpi/acpitoshiba.c

104

int toshiba_set_video_output(struct acpitoshiba_softc *, uint32_t *);

sys/dev/acpi/acpitoshiba.c

294

uint32_t brightness_level;

sys/dev/acpi/acpitoshiba.c

312

uint32_t brightness_level;

sys/dev/acpi/acpitoshiba.c

329

uint32_t video_output;

sys/dev/acpi/acpitoshiba.c

394

toshiba_set_brightness(struct acpitoshiba_softc *sc, uint32_t *brightness)

sys/dev/acpi/acpitoshiba.c

425

toshiba_get_brightness(struct acpitoshiba_softc *sc, uint32_t *brightness)

sys/dev/acpi/acpitoshiba.c

460

toshiba_get_video_output(struct acpitoshiba_softc *sc, uint32_t *video_output)

sys/dev/acpi/acpitoshiba.c

494

toshiba_set_video_output(struct acpitoshiba_softc *sc, uint32_t *video_output)

sys/dev/acpi/acpitoshiba.c

93

uint32_t sc_brightness;

sys/dev/acpi/acpivar.h

262

uint32_t sc_gpe_sts;

sys/dev/acpi/acpivar.h

263

uint32_t sc_gpe_en;

sys/dev/acpi/acpivar.h

399

int acpi_acquire_glk(uint32_t *);

sys/dev/acpi/acpivar.h

400

int acpi_release_glk(uint32_t *);

sys/dev/acpi/acpivar.h

82

uint32_t aaa_irq[8];

sys/dev/acpi/acpivar.h

83

uint32_t aaa_irq_flags[8];

sys/dev/acpi/acpiwmi.c

223

wmi_eval_method(struct wmihandler *wh, int32_t instance, uint32_t methodid,

sys/dev/acpi/acpiwmi.c

284

asus_dev_get(struct wmiasus *wh, uint32_t devid)

sys/dev/acpi/acpiwmi.c

289

asus_dev_set(struct wmiasus *wh, uint32_t devid, uint32_t val)

sys/dev/acpi/amd_iommu.h

150

uint32_t dw0;

sys/dev/acpi/amd_iommu.h

151

uint32_t dw1;

sys/dev/acpi/amd_iommu.h

152

uint32_t dw2;

sys/dev/acpi/amd_iommu.h

153

uint32_t dw3;

sys/dev/acpi/amd_iommu.h

154

uint32_t dw4;

sys/dev/acpi/amd_iommu.h

155

uint32_t dw5;

sys/dev/acpi/amd_iommu.h

156

uint32_t dw6;

sys/dev/acpi/amd_iommu.h

157

uint32_t dw7;

sys/dev/acpi/amd_iommu.h

290

uint32_t dw0;

sys/dev/acpi/amd_iommu.h

291

uint32_t dw1;

sys/dev/acpi/amd_iommu.h

292

uint32_t dw2;

sys/dev/acpi/amd_iommu.h

293

uint32_t dw3;

sys/dev/acpi/amd_iommu.h

313

uint32_t dw0;

sys/dev/acpi/amd_iommu.h

314

uint32_t dw1;

sys/dev/acpi/amd_iommu.h

315

uint32_t dw2;

sys/dev/acpi/amd_iommu.h

316

uint32_t dw3;

sys/dev/acpi/amdgpio.c

240

uint32_t reg;

sys/dev/acpi/amdgpio.c

251

uint32_t reg;

sys/dev/acpi/amdgpio.c

267

uint32_t reg;

sys/dev/acpi/amdgpio.c

296

uint32_t reg;

sys/dev/acpi/amdgpio.c

309

uint32_t reg;

sys/dev/acpi/amdgpio.c

321

uint32_t reg;

sys/dev/acpi/amdgpio.c

353

uint32_t reg;

sys/dev/acpi/amdgpio.c

55

uint32_t pin_cfg;

sys/dev/acpi/amdpmc.c

148

uint32_t sc_active_blocks;

sys/dev/acpi/amdpmc.c

179

int amdpmc_send_msg(struct amdpmc_softc *, uint8_t, uint32_t, uint32_t *);

sys/dev/acpi/amdpmc.c

199

uint32_t addr_lo, addr_hi;

sys/dev/acpi/amdpmc.c

201

uint32_t version;

sys/dev/acpi/amdpmc.c

449

amdpmc_send_msg(struct amdpmc_softc *sc, uint8_t msg, uint32_t arg,

sys/dev/acpi/amdpmc.c

450

uint32_t *data)

sys/dev/acpi/amdpmc.c

452

uint32_t val;

sys/dev/acpi/amdpmc.c

59

uint32_t table_version;

sys/dev/acpi/amdpmc.c

60

uint32_t hint_count;

sys/dev/acpi/amdpmc.c

61

uint32_t s0i3_last_entry_status;

sys/dev/acpi/amdpmc.c

62

uint32_t timein_s0i2;

sys/dev/acpi/amltypes.h

273

uint32_t iolen;

sys/dev/acpi/amltypes.h

286

uint32_t bitpos;

sys/dev/acpi/amltypes.h

287

uint32_t bitlen;

sys/dev/acpi/amltypes.h

294

uint32_t proc_addr;

sys/dev/acpi/aplgpio.c

184

uint32_t reg;

sys/dev/acpi/aplgpio.c

196

uint32_t reg;

sys/dev/acpi/aplgpio.c

213

uint32_t reg;

sys/dev/acpi/aplgpio.c

244

uint32_t reg;

sys/dev/acpi/aplgpio.c

259

uint32_t reg;

sys/dev/acpi/aplgpio.c

275

uint32_t status, enable;

sys/dev/acpi/asmc.c

309

printf(", %u key%s\n", ntohl(*(uint32_t *)buf),

sys/dev/acpi/asmc.c

310

(ntohl(*(uint32_t *)buf) == 1) ? "" : "s");

sys/dev/acpi/asmc.c

520

static uint32_t

sys/dev/acpi/asmc.c

534

static uint32_t

sys/dev/acpi/asmc.c

540

(ntohl(*(uint32_t *)(buf + 6)) >> 14) * 1000000 :

sys/dev/acpi/asmc.c

554

uint32_t uk;

sys/dev/acpi/atk0110.c

88

uint32_t id;

sys/dev/acpi/atk0110.c

89

uint32_t param1;

sys/dev/acpi/atk0110.c

90

uint32_t param2;

sys/dev/acpi/atk0110.c

95

uint32_t flags;

sys/dev/acpi/atk0110.c

96

uint32_t value;

sys/dev/acpi/bytgpio.c

128

uint32_t reg;

sys/dev/acpi/bytgpio.c

217

uint32_t reg;

sys/dev/acpi/bytgpio.c

227

uint32_t reg;

sys/dev/acpi/bytgpio.c

257

uint32_t reg;

sys/dev/acpi/bytgpio.c

281

uint32_t reg;

sys/dev/acpi/bytgpio.c

295

uint32_t reg;

sys/dev/acpi/chvgpio.c

102

chvgpio_write_pad_cfg1(struct chvgpio_softc *sc, int pin, uint32_t val)

sys/dev/acpi/chvgpio.c

270

uint32_t reg;

sys/dev/acpi/chvgpio.c

282

uint32_t reg;

sys/dev/acpi/chvgpio.c

299

uint32_t reg;

sys/dev/acpi/chvgpio.c

348

uint32_t reg;

sys/dev/acpi/chvgpio.c

367

uint32_t reg;

sys/dev/acpi/chvgpio.c

386

uint32_t reg;

sys/dev/acpi/chvgpio.c

88

chvgpio_write_pad_cfg0(struct chvgpio_softc *sc, int pin, uint32_t val)

sys/dev/acpi/dsdt.c

1444

aml_eisaid(uint32_t pid)

sys/dev/acpi/dsdt.c

2447

*(uint32_t *)(pb + reg) = value;

sys/dev/acpi/dsdt.c

2463

value = *(uint32_t *)(pb + reg);

sys/dev/acpi/dsdt.c

4634

uint8_t *start, uint32_t length)

sys/dev/acpi/dsdt.h

167

uint32_t _min;

sys/dev/acpi/dsdt.h

168

uint32_t _max;

sys/dev/acpi/dsdt.h

169

uint32_t _aln;

sys/dev/acpi/dsdt.h

170

uint32_t _len;

sys/dev/acpi/dsdt.h

176

uint32_t _bas;

sys/dev/acpi/dsdt.h

177

uint32_t _len;

sys/dev/acpi/dsdt.h

187

uint32_t irq[1];

sys/dev/acpi/dsdt.h

214

uint32_t _gra;

sys/dev/acpi/dsdt.h

215

uint32_t _min;

sys/dev/acpi/dsdt.h

216

uint32_t _max;

sys/dev/acpi/dsdt.h

217

uint32_t _tra;

sys/dev/acpi/dsdt.h

218

uint32_t _len;

sys/dev/acpi/dsdt.h

285

uint32_t _spe;

sys/dev/acpi/dsdt.h

332

#define aml_get32(p) *(uint32_t *)(p)

sys/dev/acpi/dsdt.h

37

uint32_t opcode;

sys/dev/acpi/dsdt.h

42

const char *aml_eisaid(uint32_t);

sys/dev/acpi/dsdt.h

58

u_int8_t *, uint32_t);

sys/dev/acpi/dwgpio.c

206

uint32_t reg;

sys/dev/acpi/dwgpio.c

262

uint32_t status;

sys/dev/acpi/dwgpio.c

69

uint32_t sc_npins;

sys/dev/acpi/dwiic_acpi.c

335

uint16_t *lcnt, uint32_t *sda_hold_time)

sys/dev/acpi/dwiic_acpi.c

56

uint16_t *, uint32_t *);

sys/dev/acpi/glkgpio.c

184

uint32_t reg;

sys/dev/acpi/glkgpio.c

196

uint32_t reg;

sys/dev/acpi/glkgpio.c

213

uint32_t reg;

sys/dev/acpi/glkgpio.c

244

uint32_t reg;

sys/dev/acpi/glkgpio.c

259

uint32_t reg;

sys/dev/acpi/glkgpio.c

275

uint32_t status, enable;

sys/dev/acpi/intelpmc.c

164

uint32_t length = entry->length;

sys/dev/acpi/inthid.c

87

uint32_t sc_dsm_fn_mask;

sys/dev/acpi/iosf_acpi.c

122

static uint32_t

sys/dev/acpi/iosf_acpi.c

123

iosf_acpi_mbi_mdr_rd(struct iosf_mbi *mbi, uint32_t mcr, uint32_t mcrx)

sys/dev/acpi/iosf_acpi.c

137

iosf_acpi_mbi_mdr_wr(struct iosf_mbi *mbi, uint32_t mcr, uint32_t mcrx,

sys/dev/acpi/iosf_acpi.c

138

uint32_t mdr)

sys/dev/acpi/iosf_acpi.c

48

static uint32_t iosf_acpi_mbi_mdr_rd(struct iosf_mbi *, uint32_t, uint32_t);

sys/dev/acpi/iosf_acpi.c

49

static void iosf_acpi_mbi_mdr_wr(struct iosf_mbi *, uint32_t, uint32_t,

sys/dev/acpi/iosf_acpi.c

50

uint32_t);

sys/dev/acpi/pchgpio.c

608

uint32_t reg;

sys/dev/acpi/pchgpio.c

627

uint32_t reg;

sys/dev/acpi/pchgpio.c

64

uint32_t pad_cfg_dw0;

sys/dev/acpi/pchgpio.c

65

uint32_t pad_cfg_dw1;

sys/dev/acpi/pchgpio.c

651

uint32_t reg;

sys/dev/acpi/pchgpio.c

693

uint32_t reg;

sys/dev/acpi/pchgpio.c

719

uint32_t reg;

sys/dev/acpi/pchgpio.c

743

uint32_t enable;

sys/dev/acpi/pchgpio.c

773

uint32_t status, enable;

sys/dev/acpi/pchgpio.c

807

uint32_t gpi_ie;

sys/dev/acpi/pchgpio.c

845

uint32_t pad_cfg_dw0, gpi_ie;

sys/dev/acpi/qcgpio.c

194

uint32_t irq;

sys/dev/acpi/qcgpio.c

278

return (uint32_t)npins;

sys/dev/acpi/qcgpio.c

442

uint32_t reg;

sys/dev/acpi/qcgpio.c

477

uint32_t reg;

sys/dev/acpi/qcgpio.c

555

uint32_t stat;

sys/dev/acpi/qcgpio.c

76

uint32_t pm_irq;

sys/dev/acpi/qcgpio.c

89

uint32_t sc_npins;

sys/dev/acpi/qcgpio.c

97

uint32_t sc_npdcmap;

sys/dev/acpi/qcgpio.c

98

uint32_t sc_ipdcmap;

sys/dev/acpi/qciic.c

188

qciic_wait(struct qciic_softc *sc, uint32_t bits)

sys/dev/acpi/qciic.c

190

uint32_t stat;

sys/dev/acpi/qciic.c

208

uint32_t stat, word;

sys/dev/acpi/qciic.c

233

uint32_t stat, word;

sys/dev/acpi/qciic.c

261

uint32_t m_cmd, m_param, stat;

sys/dev/acpi/tpm.c

171

uint32_t sc_devid;

sys/dev/acpi/tpm.c

172

uint32_t sc_rev;

sys/dev/acpi/tpm.c

187

uint32_t devid;

sys/dev/acpi/tpm.c

215

int tpm_waitfor(struct tpm_softc *, bus_space_handle_t, uint32_t, uint32_t, int);

sys/dev/acpi/tpm.c

223

uint32_t tpm2_start_method(struct acpi_softc *);

sys/dev/acpi/tpm.c

266

uint32_t start_method;

sys/dev/acpi/tpm.c

422

uint32_t

sys/dev/acpi/tpm.c

447

uint32_t r;

sys/dev/acpi/tpm.c

472

uint32_t r, intmask;

sys/dev/acpi/tpm.c

512

uint32_t intmask;

sys/dev/acpi/tpm.c

571

uint32_t r;

sys/dev/acpi/tpm.c

606

uint32_t r, mask;

sys/dev/acpi/tpm.c

648

uint32_t r;

sys/dev/acpi/tpm.c

693

tpm_waitfor(struct tpm_softc *sc, bus_size_t offset, uint32_t mask,

sys/dev/acpi/tpm.c

694

uint32_t val, int msecs)

sys/dev/acpi/tpm.c

697

uint32_t r;

sys/dev/acpi/tpm.c

783

uint32_t sz = 0, mask, rc;

sys/dev/acpi/tpm.c

806

sz = be32toh(*(uint32_t *) (p + 2));

sys/dev/acpi/tpm.c

817

rc = be32toh(*(uint32_t *) (p + 6));

sys/dev/acpi/tpm.c

917

uint32_t r, mask;

sys/dev/cardbus/if_athn_cardbus.c

265

uint32_t

sys/dev/cardbus/if_athn_cardbus.c

266

athn_cardbus_read(struct athn_softc *sc, uint32_t addr)

sys/dev/cardbus/if_athn_cardbus.c

274

athn_cardbus_write(struct athn_softc *sc, uint32_t addr, uint32_t val)

sys/dev/cardbus/if_athn_cardbus.c

75

uint32_t athn_cardbus_read(struct athn_softc *, uint32_t);

sys/dev/cardbus/if_athn_cardbus.c

76

void athn_cardbus_write(struct athn_softc *, uint32_t, uint32_t);

sys/dev/cardbus/if_bwi_cardbus.c

245

bwi_cardbus_conf_write(void *self, uint32_t reg, uint32_t val)

sys/dev/cardbus/if_bwi_cardbus.c

253

uint32_t

sys/dev/cardbus/if_bwi_cardbus.c

254

bwi_cardbus_conf_read(void *self, uint32_t reg)

sys/dev/cardbus/if_bwi_cardbus.c

68

void bwi_cardbus_conf_write(void *, uint32_t, uint32_t);

sys/dev/cardbus/if_bwi_cardbus.c

69

uint32_t bwi_cardbus_conf_read(void *, uint32_t);

sys/dev/dt/dt_dev.c

151

volatile uint32_t dt_tracing = 0; /* [D] # of processes tracing */

sys/dev/dt/dt_dev.c

449

uint32_t pbn;

sys/dev/dt/dt_prov_kprobe.c

70

uint32_t

sys/dev/dt/dt_prov_kprobe.c

71

ptr_hash(uint32_t a) {

sys/dev/dt/dtvar.h

100

uint32_t dtai_pbn; /* probe number */

sys/dev/dt/dtvar.h

106

uint32_t dtar_pbn; /* probe number */

sys/dev/dt/dtvar.h

112

uint32_t dtrq_pbn; /* probe number */

sys/dev/dt/dtvar.h

113

uint32_t __unused1;

sys/dev/dt/dtvar.h

213

uint32_t dtp_pbn; /* [I] unique ID */

sys/dev/dt/dtvar.h

214

volatile uint32_t dtp_recording; /* [d] is it recording? */

sys/dev/dt/dtvar.h

235

volatile uint32_t dtpv_recording;/* [D] # of recording PCBs */

sys/dev/dt/dtvar.h

258

extern volatile uint32_t dt_tracing; /* currently tracing? */

sys/dev/dt/dtvar.h

87

uint32_t dtpi_pbn; /* probe number */

sys/dev/efi/efi.h

23

typedef uint32_t UINT32;

sys/dev/efi/efiio.h

41

uint32_t fw_resource_count;

sys/dev/efi/efiio.h

42

uint32_t fw_resource_count_max;

sys/dev/efi/efiio.h

50

uint32_t fw_type;

sys/dev/efi/efiio.h

51

uint32_t fw_version;

sys/dev/efi/efiio.h

52

uint32_t lowest_supported_fw_version;

sys/dev/efi/efiio.h

53

uint32_t capsule_flags;

sys/dev/efi/efiio.h

54

uint32_t last_attempt_version;

sys/dev/efi/efiio.h

55

uint32_t last_attempt_status;

sys/dev/efi/efiio.h

70

uint32_t attrib; /* Attributes */

sys/dev/fdt/acrtc.c

218

acrtc_ck32k_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/acrtc.c

221

uint32_t idx = cells[0];

sys/dev/fdt/acrtc.c

86

void acrtc_ck32k_enable(void *, uint32_t *, int);

sys/dev/fdt/ahci_fdt.c

68

uint32_t pi;

sys/dev/fdt/amlclock.c

140

uint32_t sc_g12b;

sys/dev/fdt/amlclock.c

146

uint32_t sc_xtal;

sys/dev/fdt/amlclock.c

160

uint32_t amlclock_get_frequency(void *, uint32_t *);

sys/dev/fdt/amlclock.c

161

int amlclock_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/amlclock.c

162

void amlclock_enable(void *, uint32_t *, int);

sys/dev/fdt/amlclock.c

205

uint32_t

sys/dev/fdt/amlclock.c

208

uint32_t reg, mux, div;

sys/dev/fdt/amlclock.c

209

uint32_t idx;

sys/dev/fdt/amlclock.c

245

uint32_t freq)

sys/dev/fdt/amlclock.c

247

uint32_t reg, div;

sys/dev/fdt/amlclock.c

248

uint32_t parent_freq;

sys/dev/fdt/amlclock.c

249

uint32_t idx;

sys/dev/fdt/amlclock.c

373

uint32_t freq)

sys/dev/fdt/amlclock.c

375

uint32_t reg, div;

sys/dev/fdt/amlclock.c

376

uint32_t m, n = 1;

sys/dev/fdt/amlclock.c

415

uint32_t

sys/dev/fdt/amlclock.c

416

amlclock_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/amlclock.c

419

uint32_t idx = cells[0];

sys/dev/fdt/amlclock.c

420

uint32_t reg, mux, div;

sys/dev/fdt/amlclock.c

421

uint32_t m, n;

sys/dev/fdt/amlclock.c

559

amlclock_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/amlclock.c

562

uint32_t idx = cells[0];

sys/dev/fdt/amlclock.c

600

amlclock_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/amlclock.c

603

uint32_t idx = cells[0];

sys/dev/fdt/amldwusb.c

147

uint32_t vbus_supply;

sys/dev/fdt/amldwusb.c

148

uint32_t reg;

sys/dev/fdt/amldwusb.c

218

uint32_t reg;

sys/dev/fdt/amliic.c

108

uint32_t clock_speed, bus_speed;

sys/dev/fdt/amliic.c

109

uint32_t div, divl, divh;

sys/dev/fdt/amliic.c

173

uint32_t rdata;

sys/dev/fdt/amliic.c

174

uint32_t ctrl;

sys/dev/fdt/amliic.c

271

uint32_t reg[1];

sys/dev/fdt/amlmmc.c

118

uint32_t cmd_cfg;

sys/dev/fdt/amlmmc.c

119

uint32_t cmd_arg;

sys/dev/fdt/amlmmc.c

120

uint32_t data_addr;

sys/dev/fdt/amlmmc.c

121

uint32_t resp_addr;

sys/dev/fdt/amlmmc.c

135

uint32_t sc_status;

sys/dev/fdt/amlmmc.c

143

uint32_t sc_clkin0;

sys/dev/fdt/amlmmc.c

144

uint32_t sc_clkin1;

sys/dev/fdt/amlmmc.c

145

uint32_t sc_gpio[4];

sys/dev/fdt/amlmmc.c

146

uint32_t sc_vmmc;

sys/dev/fdt/amlmmc.c

147

uint32_t sc_vqmmc;

sys/dev/fdt/amlmmc.c

148

uint32_t sc_pwrseq;

sys/dev/fdt/amlmmc.c

149

uint32_t sc_vdd;

sys/dev/fdt/amlmmc.c

150

uint32_t sc_ocr;

sys/dev/fdt/amlmmc.c

171

void amlmmc_pwrseq_reset(uint32_t);

sys/dev/fdt/amlmmc.c

174

uint32_t amlmmc_host_ocr(sdmmc_chipset_handle_t);

sys/dev/fdt/amlmmc.c

177

int amlmmc_bus_power(sdmmc_chipset_handle_t, uint32_t);

sys/dev/fdt/amlmmc.c

212

uint32_t cfg, width;

sys/dev/fdt/amlmmc.c

379

uint32_t status;

sys/dev/fdt/amlmmc.c

394

uint32_t cfg;

sys/dev/fdt/amlmmc.c

407

amlmmc_pwrseq_reset(uint32_t phandle)

sys/dev/fdt/amlmmc.c

409

uint32_t *gpios, *gpio;

sys/dev/fdt/amlmmc.c

428

while (gpio && gpio < gpios + (len / sizeof(uint32_t))) {

sys/dev/fdt/amlmmc.c

447

uint32_t

sys/dev/fdt/amlmmc.c

481

amlmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)

sys/dev/fdt/amlmmc.c

484

uint32_t vdd = 0;

sys/dev/fdt/amlmmc.c

506

uint32_t div, clock;

sys/dev/fdt/amlmmc.c

558

uint32_t cfg;

sys/dev/fdt/amlmmc.c

584

uint32_t cmd_cfg, status;

sys/dev/fdt/amlmmc.c

585

uint32_t data_addr = 0;

sys/dev/fdt/amlmmc.c

746

uint32_t vccq;

sys/dev/fdt/amlmmc.c

773

uint32_t adjust, cfg, div;

sys/dev/fdt/amlpciephy.c

112

amlpciephy_enable(void *cookie, uint32_t *cells)

sys/dev/fdt/amlpciephy.c

116

uint32_t type = cells[0];

sys/dev/fdt/amlpciephy.c

117

uint32_t reg;

sys/dev/fdt/amlpciephy.c

222

uint32_t reg;

sys/dev/fdt/amlpciephy.c

73

int amlpciephy_enable(void *, uint32_t *);

sys/dev/fdt/amlpinctrl.c

367

int amlpinctrl_pinctrl(uint32_t, void *);

sys/dev/fdt/amlpinctrl.c

368

void amlpinctrl_config_pin(void *, uint32_t *, int);

sys/dev/fdt/amlpinctrl.c

369

int amlpinctrl_get_pin(void *, uint32_t *);

sys/dev/fdt/amlpinctrl.c

370

void amlpinctrl_set_pin(void *, uint32_t *, int);

sys/dev/fdt/amlpinctrl.c

388

uint32_t *cell;

sys/dev/fdt/amlpinctrl.c

389

uint32_t acells, scells;

sys/dev/fdt/amlpinctrl.c

390

uint32_t reg[20];

sys/dev/fdt/amlpinctrl.c

407

line = (acells + scells) * sizeof(uint32_t);

sys/dev/fdt/amlpinctrl.c

485

amlpinctrl_lookup_bank(struct amlpinctrl_softc *sc, uint32_t pin)

sys/dev/fdt/amlpinctrl.c

518

uint32_t pin;

sys/dev/fdt/amlpinctrl.c

519

uint32_t reg;

sys/dev/fdt/amlpinctrl.c

587

amlpinctrl_pinctrl(uint32_t phandle, void *cookie)

sys/dev/fdt/amlpinctrl.c

640

amlpinctrl_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/amlpinctrl.c

645

uint32_t pin = cells[0];

sys/dev/fdt/amlpinctrl.c

646

uint32_t flags = cells[1];

sys/dev/fdt/amlpinctrl.c

647

uint32_t reg;

sys/dev/fdt/amlpinctrl.c

678

amlpinctrl_get_pin(void *cookie, uint32_t *cells)

sys/dev/fdt/amlpinctrl.c

683

uint32_t pin = cells[0];

sys/dev/fdt/amlpinctrl.c

684

uint32_t flags = cells[1];

sys/dev/fdt/amlpinctrl.c

685

uint32_t reg;

sys/dev/fdt/amlpinctrl.c

707

amlpinctrl_set_pin(void *cookie, uint32_t *cells, int val)

sys/dev/fdt/amlpinctrl.c

712

uint32_t pin = cells[0];

sys/dev/fdt/amlpinctrl.c

713

uint32_t flags = cells[1];

sys/dev/fdt/amlpwm.c

125

static inline uint32_t

sys/dev/fdt/amlpwm.c

126

cycles_to_ns(uint64_t clk_freq, uint32_t clk_div, uint32_t cycles)

sys/dev/fdt/amlpwm.c

131

static inline uint32_t

sys/dev/fdt/amlpwm.c

132

ns_to_cycles(uint64_t clk_freq, uint32_t clk_div, uint32_t ns)

sys/dev/fdt/amlpwm.c

138

amlpwm_get_state(void *cookie, uint32_t *cells, struct pwm_state *ps)

sys/dev/fdt/amlpwm.c

141

uint32_t idx = cells[0];

sys/dev/fdt/amlpwm.c

142

uint32_t pwm, misc;

sys/dev/fdt/amlpwm.c

143

uint32_t total, high;

sys/dev/fdt/amlpwm.c

144

uint32_t clk_div;

sys/dev/fdt/amlpwm.c

175

amlpwm_set_state(void *cookie, uint32_t *cells, struct pwm_state *ps)

sys/dev/fdt/amlpwm.c

178

uint32_t idx = cells[0];

sys/dev/fdt/amlpwm.c

179

uint32_t pwm, misc;

sys/dev/fdt/amlpwm.c

180

uint32_t total, high, low;

sys/dev/fdt/amlpwm.c

181

uint32_t clk_div = 1;

sys/dev/fdt/amlpwm.c

64

uint32_t sc_clkin[2];

sys/dev/fdt/amlpwm.c

80

int amlpwm_get_state(void *, uint32_t *, struct pwm_state *);

sys/dev/fdt/amlpwm.c

81

int amlpwm_set_state(void *, uint32_t *, struct pwm_state *);

sys/dev/fdt/amlpwrc.c

119

amlpwrc_toggle(struct regmap *rm, bus_size_t reg, uint32_t mask, int on)

sys/dev/fdt/amlpwrc.c

121

uint32_t val;

sys/dev/fdt/amlpwrc.c

132

amlpwrc_g12a_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/amlpwrc.c

135

uint32_t idx = cells[0];

sys/dev/fdt/amlpwrc.c

152

amlpwrc_sm1_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/amlpwrc.c

155

uint32_t idx = cells[0];

sys/dev/fdt/amlpwrc.c

60

uint32_t sc_ao;

sys/dev/fdt/amlpwrc.c

77

void amlpwrc_g12a_enable(void *, uint32_t *, int);

sys/dev/fdt/amlpwrc.c

78

void amlpwrc_sm1_enable(void *, uint32_t *, int);

sys/dev/fdt/amlreset.c

100

amlreset_reset(void *cookie, uint32_t *cells, int assert)

sys/dev/fdt/amlreset.c

103

uint32_t bank = cells[0] / 32;

sys/dev/fdt/amlreset.c

104

uint32_t bit = cells[0] % 32;

sys/dev/fdt/amlreset.c

63

void amlreset_reset(void *, uint32_t *, int);

sys/dev/fdt/amlsm.c

42

uint32_t version;

sys/dev/fdt/amlsm.c

43

uint32_t chip_id[4];

sys/dev/fdt/amltemp.c

126

uint32_t ao_secure;

sys/dev/fdt/amltemp.c

181

const uint32_t A = 9411;

sys/dev/fdt/amltemp.c

182

const uint32_t B = 3159;

sys/dev/fdt/amltemp.c

183

const uint32_t m = 424;

sys/dev/fdt/amltemp.c

184

const uint32_t n = 324;

sys/dev/fdt/amltemp.c

208

amltemp_get_temperature(void *cookie, uint32_t *cells)

sys/dev/fdt/amltemp.c

85

int32_t amltemp_get_temperature(void *, uint32_t *);

sys/dev/fdt/amluart.c

143

uint32_t reg;

sys/dev/fdt/amlusbphy.c

111

int amlusbphy_enable(void *, uint32_t *);

sys/dev/fdt/amlusbphy.c

148

amlusbphy_enable(void *cookie, uint32_t *cells)

sys/dev/fdt/amlusbphy.c

152

uint32_t phy_supply;

sys/dev/fdt/axppmic.c

68

uint32_t base, delta, nsteps;

sys/dev/fdt/axppmic.c

69

uint32_t base2, delta2, nsteps2;

sys/dev/fdt/axppmic.c

694

uint32_t ar_base, ar_delta, ar_nsteps;

sys/dev/fdt/axppmic.c

695

uint32_t ar_base2, ar_delta2, ar_nsteps2;

sys/dev/fdt/axppmic.c

701

uint32_t axppmic_get_voltage(void *);

sys/dev/fdt/axppmic.c

702

int axppmic_set_voltage(void *, uint32_t);

sys/dev/fdt/axppmic.c

757

uint32_t

sys/dev/fdt/axppmic.c

761

uint32_t voltage;

sys/dev/fdt/axppmic.c

776

axppmic_set_voltage(void *cookie, uint32_t voltage)

sys/dev/fdt/axppmic.c

779

uint32_t value, reg;

sys/dev/fdt/bcm2711_pcie.c

1049

uint32_t reg[4];

sys/dev/fdt/bcm2711_pcie.c

166

uint32_t flags;

sys/dev/fdt/bcm2711_pcie.c

232

uint32_t *);

sys/dev/fdt/bcm2711_pcie.c

234

uint32_t);

sys/dev/fdt/bcm2711_pcie.c

267

uint32_t bus_range[2];

sys/dev/fdt/bcm2711_pcie.c

268

uint32_t *ranges;

sys/dev/fdt/bcm2711_pcie.c

270

uint32_t msi_parent, phandle;

sys/dev/fdt/bcm2711_pcie.c

271

uint32_t reg;

sys/dev/fdt/bcm2711_pcie.c

303

if (rangeslen <= 0 || (rangeslen % sizeof(uint32_t)) ||

sys/dev/fdt/bcm2711_pcie.c

304

(rangeslen / sizeof(uint32_t)) % (sc->sc_acells +

sys/dev/fdt/bcm2711_pcie.c

314

nranges = (rangeslen / sizeof(uint32_t)) /

sys/dev/fdt/bcm2711_pcie.c

344

if ((rangeslen % sizeof(uint32_t)) ||

sys/dev/fdt/bcm2711_pcie.c

345

(rangeslen / sizeof(uint32_t)) % (sc->sc_acells +

sys/dev/fdt/bcm2711_pcie.c

357

nranges = (rangeslen / sizeof(uint32_t)) /

sys/dev/fdt/bcm2711_pcie.c

518

uint32_t reg;

sys/dev/fdt/bcm2711_pcie.c

571

uint32_t reg;

sys/dev/fdt/bcm2711_pcie.c

602

uint32_t reg;

sys/dev/fdt/bcm2711_pcie.c

629

uint32_t reg;

sys/dev/fdt/bcm2711_pcie.c

768

uint32_t reg;

sys/dev/fdt/bcm2711_pcie.c

787

uint32_t reg;

sys/dev/fdt/bcm2711_pcie.c

798

uint32_t *data)

sys/dev/fdt/bcm2711_pcie.c

800

uint32_t reg;

sys/dev/fdt/bcm2711_pcie.c

805

reg |= ((uint32_t)port << PCIE_RC_DL_MDIO_PORT_SHIFT);

sys/dev/fdt/bcm2711_pcie.c

806

reg |= ((uint32_t)addr << PCIE_RC_DL_MDIO_REGAD_SHIFT);

sys/dev/fdt/bcm2711_pcie.c

827

uint32_t data)

sys/dev/fdt/bcm2711_pcie.c

829

uint32_t reg;

sys/dev/fdt/bcm2711_pcie.c

834

reg |= ((uint32_t)port << PCIE_RC_DL_MDIO_PORT_SHIFT);

sys/dev/fdt/bcm2711_pcie.c

835

reg |= ((uint32_t)addr << PCIE_RC_DL_MDIO_REGAD_SHIFT);

sys/dev/fdt/bcm2711_pcie.c

936

uint32_t result;

sys/dev/fdt/bcm2711_rng.c

102

uint32_t data;

sys/dev/fdt/bcm2711_tmon.c

146

bcmtmon_get_temperature(void *cookie, uint32_t *cells)

sys/dev/fdt/bcm2711_tmon.c

64

int32_t bcmtmon_get_temperature(void *, uint32_t *);

sys/dev/fdt/bcm2835_aux.c

104

uint32_t

sys/dev/fdt/bcm2835_aux.c

105

bcm_aux_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/bcm2835_aux.c

107

uint32_t idx = cells[0];

sys/dev/fdt/bcm2835_aux.c

122

uint32_t idx = cells[0];

sys/dev/fdt/bcm2835_aux.c

59

uint32_t bcm_aux_get_frequency(void *, uint32_t *);

sys/dev/fdt/bcm2835_bsc.c

111

uint32_t clock_speed, bus_speed;

sys/dev/fdt/bcm2835_bsc.c

112

uint32_t div, fedl, redl;

sys/dev/fdt/bcm2835_bsc.c

184

bcmbsc_wait(struct bcmbsc_softc *sc, uint32_t mask, uint32_t value)

sys/dev/fdt/bcm2835_bsc.c

186

uint32_t stat;

sys/dev/fdt/bcm2835_bsc.c

238

uint32_t ctrl = BSC_C_I2CEN | BSC_C_ST;

sys/dev/fdt/bcm2835_bsc.c

283

uint32_t reg[1];

sys/dev/fdt/bcm2835_clock.c

121

uint32_t

sys/dev/fdt/bcm2835_clock.c

122

bcmclock_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/bcm2835_clock.c

130

uint32_t result;

sys/dev/fdt/bcm2835_clock.c

93

uint32_t bcmclock_get_frequency(void *, uint32_t *);

sys/dev/fdt/bcm2835_dmac.c

115

bcmdmac_write(struct bcmdmac_softc *sc, bus_size_t offset, uint32_t value)

sys/dev/fdt/bcm2835_dmac.c

120

uint32_t

sys/dev/fdt/bcm2835_dmac.c

141

uint32_t val;

sys/dev/fdt/bcm2835_dmac.c

204

uint32_t cs, ce;

sys/dev/fdt/bcm2835_dmac.c

223

void (*cb)(uint32_t, uint32_t, void *), void *cbarg)

sys/dev/fdt/bcm2835_dmac.c

271

uint32_t val;

sys/dev/fdt/bcm2835_dmac.c

301

uint32_t val;

sys/dev/fdt/bcm2835_dmac.c

317

uint32_t val;

sys/dev/fdt/bcm2835_dmac.c

73

uint32_t sc_channelmask;

sys/dev/fdt/bcm2835_dmac.c

82

void (*ch_callback)(uint32_t, uint32_t, void *);

sys/dev/fdt/bcm2835_dmac.c

84

uint32_t ch_debug;

sys/dev/fdt/bcm2835_dog.c

121

bcmdog_wdog_set(struct bcmdog_softc *sc, uint32_t period)

sys/dev/fdt/bcm2835_dog.c

123

uint32_t rstc, wdog;

sys/dev/fdt/bcm2835_gpio.c

153

uint32_t val;

sys/dev/fdt/bcm2835_gpio.c

167

uint32_t val;

sys/dev/fdt/bcm2835_gpio.c

190

bcmgpio_pinctrl(uint32_t phandle, void *cookie)

sys/dev/fdt/bcm2835_gpio.c

193

uint32_t *pins, *pull = NULL;

sys/dev/fdt/bcm2835_gpio.c

218

for (i = 0; i < len / sizeof(uint32_t); i++) {

sys/dev/fdt/bcm2835_gpio.c

220

if (plen > 0 && i < plen / sizeof(uint32_t))

sys/dev/fdt/bcm2835_gpio.c

236

bcmgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/bcm2835_gpio.c

239

uint32_t pin = cells[0];

sys/dev/fdt/bcm2835_gpio.c

257

bcmgpio_get_pin(void *cookie, uint32_t *cells)

sys/dev/fdt/bcm2835_gpio.c

260

uint32_t pin = cells[0];

sys/dev/fdt/bcm2835_gpio.c

261

uint32_t flags = cells[1];

sys/dev/fdt/bcm2835_gpio.c

262

uint32_t reg;

sys/dev/fdt/bcm2835_gpio.c

276

bcmgpio_set_pin(void *cookie, uint32_t *cells, int val)

sys/dev/fdt/bcm2835_gpio.c

279

uint32_t pin = cells[0];

sys/dev/fdt/bcm2835_gpio.c

280

uint32_t flags = cells[1];

sys/dev/fdt/bcm2835_gpio.c

311

uint32_t cells[2];

sys/dev/fdt/bcm2835_gpio.c

323

uint32_t cells[2];

sys/dev/fdt/bcm2835_gpio.c

335

uint32_t cells[2];

sys/dev/fdt/bcm2835_gpio.c

336

uint32_t config;

sys/dev/fdt/bcm2835_gpio.c

357

uint32_t reg;

sys/dev/fdt/bcm2835_gpio.c

93

int bcmgpio_pinctrl(uint32_t, void *);

sys/dev/fdt/bcm2835_gpio.c

94

void bcmgpio_config_pin(void *, uint32_t *, int);

sys/dev/fdt/bcm2835_gpio.c

95

int bcmgpio_get_pin(void *, uint32_t *);

sys/dev/fdt/bcm2835_gpio.c

96

void bcmgpio_set_pin(void *, uint32_t *, int);

sys/dev/fdt/bcm2835_mbox.c

191

uint32_t

sys/dev/fdt/bcm2835_mbox.c

198

bcmmbox_reg_write(struct bcmmbox_softc *sc, int addr, uint32_t val)

sys/dev/fdt/bcm2835_mbox.c

225

uint32_t mbox, chan, data;

sys/dev/fdt/bcm2835_mbox.c

252

bcmmbox_read(uint8_t chan, uint32_t *data)

sys/dev/fdt/bcm2835_mbox.c

290

bcmmbox_write(uint8_t chan, uint32_t data)

sys/dev/fdt/bcm2835_mbox.c

293

uint32_t rdata;

sys/dev/fdt/bcm2835_mbox.c

311

bcmmbox_post(uint8_t chan, void *buf, size_t len, uint32_t *res)

sys/dev/fdt/bcm2835_mbox.c

81

uint32_t sc_mbox[BCMMBOX_NUM_CHANNELS];

sys/dev/fdt/bcm2835_mbox.c

95

uint32_t bcmmbox_reg_read(struct bcmmbox_softc *, int);

sys/dev/fdt/bcm2835_mbox.c

96

void bcmmbox_reg_write(struct bcmmbox_softc *, int, uint32_t);

sys/dev/fdt/bcm2835_rng.c

102

uint32_t status, data;

sys/dev/fdt/bcm2835_sdhost.c

134

uint32_t sc_intr_hsts;

sys/dev/fdt/bcm2835_sdhost.c

135

uint32_t sc_intr_cv;

sys/dev/fdt/bcm2835_sdhost.c

136

uint32_t sc_dma_cv;

sys/dev/fdt/bcm2835_sdhost.c

140

uint32_t sc_dma_status;

sys/dev/fdt/bcm2835_sdhost.c

141

uint32_t sc_dma_error;

sys/dev/fdt/bcm2835_sdhost.c

156

uint32_t bcmsdhost_host_ocr(sdmmc_chipset_handle_t);

sys/dev/fdt/bcm2835_sdhost.c

159

int bcmsdhost_bus_power(sdmmc_chipset_handle_t, uint32_t);

sys/dev/fdt/bcm2835_sdhost.c

178

void bcmsdhost_dma_done(uint32_t, uint32_t, void *);

sys/dev/fdt/bcm2835_sdhost.c

185

bcmsdhost_write(struct bcmsdhost_softc *sc, bus_size_t offset, uint32_t value)

sys/dev/fdt/bcm2835_sdhost.c

190

static inline uint32_t

sys/dev/fdt/bcm2835_sdhost.c

312

uint32_t edm;

sys/dev/fdt/bcm2835_sdhost.c

340

uint32_t

sys/dev/fdt/bcm2835_sdhost.c

359

bcmsdhost_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)

sys/dev/fdt/bcm2835_sdhost.c

393

uint32_t hcfg;

sys/dev/fdt/bcm2835_sdhost.c

410

uint32_t cmdval, hcfg;

sys/dev/fdt/bcm2835_sdhost.c

509

const uint32_t cmd = bcmsdhost_read(sc, SDCMD);

sys/dev/fdt/bcm2835_sdhost.c

618

bcmsdhost_dma_done(uint32_t status, uint32_t error, void *arg)

sys/dev/fdt/bcm2835_sdhost.c

634

uint32_t *datap = cmd->c_data;

sys/dev/fdt/bcm2835_sdhost.c

635

uint32_t edm, status;

sys/dev/fdt/bcm2835_sdhost.c

678

uint32_t hsts;

sys/dev/fdt/bcmstbgpio.c

159

bcmstbgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/bcmstbgpio.c

175

bcmstbgpio_get_pin(void *cookie, uint32_t *cells)

sys/dev/fdt/bcmstbgpio.c

178

uint32_t bank = cells[0] / 32;

sys/dev/fdt/bcmstbgpio.c

179

uint32_t pin = cells[0] % 32;

sys/dev/fdt/bcmstbgpio.c

180

uint32_t flags = cells[1];

sys/dev/fdt/bcmstbgpio.c

181

uint32_t reg;

sys/dev/fdt/bcmstbgpio.c

195

bcmstbgpio_set_pin(void *cookie, uint32_t *cells, int val)

sys/dev/fdt/bcmstbgpio.c

198

uint32_t bank = cells[0] / 32;;

sys/dev/fdt/bcmstbgpio.c

199

uint32_t pin = cells[0] % 32;

sys/dev/fdt/bcmstbgpio.c

200

uint32_t flags = cells[1];

sys/dev/fdt/bcmstbgpio.c

214

bcmstbgpio_intr_establish_pin(void *cookie, uint32_t *cells, int ipl,

sys/dev/fdt/bcmstbgpio.c

218

uint32_t icells[2];

sys/dev/fdt/bcmstbgpio.c

235

uint32_t mask, stat;

sys/dev/fdt/bcmstbgpio.c

312

uint32_t ec, ei, level;

sys/dev/fdt/bcmstbgpio.c

384

uint32_t bank = ih->ih_irq / 32;

sys/dev/fdt/bcmstbgpio.c

385

uint32_t pin = ih->ih_irq % 32;

sys/dev/fdt/bcmstbgpio.c

395

uint32_t bank = ih->ih_irq / 32;

sys/dev/fdt/bcmstbgpio.c

396

uint32_t pin = ih->ih_irq % 32;

sys/dev/fdt/bcmstbgpio.c

87

void bcmstbgpio_config_pin(void *, uint32_t *, int);

sys/dev/fdt/bcmstbgpio.c

88

int bcmstbgpio_get_pin(void *, uint32_t *);

sys/dev/fdt/bcmstbgpio.c

89

void bcmstbgpio_set_pin(void *, uint32_t *, int);

sys/dev/fdt/bcmstbgpio.c

90

void *bcmstbgpio_intr_establish_pin(void *, uint32_t *, int,

sys/dev/fdt/bcmstbintc.c

137

uint32_t status;

sys/dev/fdt/bcmstbpinctrl.c

122

int bcmstbpinctrl_pinctrl(uint32_t, void *);

sys/dev/fdt/bcmstbpinctrl.c

175

uint32_t val;

sys/dev/fdt/bcmstbpinctrl.c

248

bcmstbpinctrl_pinctrl(uint32_t phandle, void *cookie)

sys/dev/fdt/bcmstbrescal.c

103

bcmstbrescal_reset(void *cookie, uint32_t *cells, int assert)

sys/dev/fdt/bcmstbrescal.c

106

uint32_t status;

sys/dev/fdt/bcmstbrescal.c

66

void bcmstbrescal_reset(void *, uint32_t *, int);

sys/dev/fdt/bcmstbreset.c

101

uint32_t bank = cells[0] / 32;;

sys/dev/fdt/bcmstbreset.c

102

uint32_t bit = cells[0] % 32;

sys/dev/fdt/bcmstbreset.c

60

void bcmstbreset_reset(void *, uint32_t *, int);

sys/dev/fdt/bcmstbreset.c

98

bcmstbreset_reset(void *cookie, uint32_t *cells, int assert)

sys/dev/fdt/bd718x7.c

113

uint32_t bd_base, bd_delta;

sys/dev/fdt/bd718x7.c

118

uint32_t bdpmic_get_voltage(void *);

sys/dev/fdt/bd718x7.c

119

int bdpmic_set_voltage(void *, uint32_t);

sys/dev/fdt/bd718x7.c

153

uint32_t

sys/dev/fdt/bd718x7.c

164

bdpmic_set_voltage(void *cookie, uint32_t voltage)

sys/dev/fdt/bd718x7.c

167

uint32_t vmin = bd->bd_base;

sys/dev/fdt/bd718x7.c

168

uint32_t vmax = vmin + bd->bd_mask * bd->bd_delta;

sys/dev/fdt/bd718x7.c

37

uint32_t base, delta;

sys/dev/fdt/cdpcie.c

143

uint32_t bus_range[2];

sys/dev/fdt/cdpcie.c

144

uint32_t vendor_id, device_id;

sys/dev/fdt/cdpcie.c

323

uint32_t type;

sys/dev/fdt/cdpcie.c

67

uint32_t flags;

sys/dev/fdt/cdsdhc.c

101

uint32_t ver;

sys/dev/fdt/cdsdhc.c

147

uint32_t mode, val;

sys/dev/fdt/cduart.c

160

static inline uint32_t

sys/dev/fdt/cduart.c

161

cduart_read(struct cduart_softc *sc, uint32_t reg)

sys/dev/fdt/cduart.c

167

cduart_write(struct cduart_softc *sc, uint32_t reg, uint32_t val)

sys/dev/fdt/cduart.c

201

uint32_t cr, isr;

sys/dev/fdt/cduart.c

273

uint32_t isr, sr;

sys/dev/fdt/cduart.c

379

uint32_t sr;

sys/dev/fdt/cduart.c

560

uint32_t sr;

sys/dev/fdt/com_fdt.c

115

uint32_t freq, width, shift;

sys/dev/fdt/com_fdt.c

53

uint32_t width, shift;

sys/dev/fdt/cwfg.c

147

uint32_t *batinfo;

sys/dev/fdt/cwfg.c

316

uint32_t vcell, rtt, tmp;

sys/dev/fdt/dwiic_fdt.c

123

uint32_t sda_hold, sda_fall, scl_fall;

sys/dev/fdt/dwiic_fdt.c

152

uint32_t reg[1];

sys/dev/fdt/dwiic_fdt.c

33

static inline uint32_t

sys/dev/fdt/dwmmc.c

1078

uint32_t status;

sys/dev/fdt/dwmmc.c

1137

*(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE);

sys/dev/fdt/dwmmc.c

1142

uint32_t rv = HREAD4(sc, SDMMC_FIFO_BASE);

sys/dev/fdt/dwmmc.c

1155

HWRITE4(sc, SDMMC_FIFO_BASE, *((uint32_t *)datap));

sys/dev/fdt/dwmmc.c

1160

uint32_t rv = *datap++;

sys/dev/fdt/dwmmc.c

1174

*(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE);

sys/dev/fdt/dwmmc.c

1177

*(uint32_t *)datap = HREAD4(sc, SDMMC_FIFO_BASE + 4);

sys/dev/fdt/dwmmc.c

1196

HWRITE4(sc, SDMMC_FIFO_BASE, *((uint32_t *)datap));

sys/dev/fdt/dwmmc.c

1199

HWRITE4(sc, SDMMC_FIFO_BASE + 4, *((uint32_t *)datap));

sys/dev/fdt/dwmmc.c

1204

uint32_t rv = *datap++;

sys/dev/fdt/dwmmc.c

1224

dwmmc_pwrseq_pre(uint32_t phandle)

sys/dev/fdt/dwmmc.c

1226

uint32_t *gpios, *gpio;

sys/dev/fdt/dwmmc.c

1249

while (gpio && gpio < gpios + (len / sizeof(uint32_t))) {

sys/dev/fdt/dwmmc.c

1259

dwmmc_pwrseq_post(uint32_t phandle)

sys/dev/fdt/dwmmc.c

1261

uint32_t *gpios, *gpio;

sys/dev/fdt/dwmmc.c

1281

while (gpio && gpio < gpios + (len / sizeof(uint32_t))) {

sys/dev/fdt/dwmmc.c

1297

uint32_t vccq;

sys/dev/fdt/dwmmc.c

166

uint32_t des[4];

sys/dev/fdt/dwmmc.c

170

uint32_t des[8];

sys/dev/fdt/dwmmc.c

200

uint32_t sc_clkbase;

sys/dev/fdt/dwmmc.c

201

uint32_t sc_fifo_depth;

sys/dev/fdt/dwmmc.c

202

uint32_t sc_fifo_width;

sys/dev/fdt/dwmmc.c

212

uint32_t sc_idsts;

sys/dev/fdt/dwmmc.c

214

uint32_t sc_gpio[4];

sys/dev/fdt/dwmmc.c

216

uint32_t sc_vqmmc;

sys/dev/fdt/dwmmc.c

217

uint32_t sc_pwrseq;

sys/dev/fdt/dwmmc.c

218

uint32_t sc_vdd;

sys/dev/fdt/dwmmc.c

237

uint32_t dwmmc_host_ocr(sdmmc_chipset_handle_t);

sys/dev/fdt/dwmmc.c

240

int dwmmc_bus_power(sdmmc_chipset_handle_t, uint32_t);

sys/dev/fdt/dwmmc.c

270

void dwmmc_pwrseq_pre(uint32_t);

sys/dev/fdt/dwmmc.c

271

void dwmmc_pwrseq_post(uint32_t);

sys/dev/fdt/dwmmc.c

293

uint32_t freq = 0, div = 0;

sys/dev/fdt/dwmmc.c

294

uint32_t hcon, width;

sys/dev/fdt/dwmmc.c

295

uint32_t fifoth;

sys/dev/fdt/dwmmc.c

551

uint32_t stat;

sys/dev/fdt/dwmmc.c

599

uint32_t

sys/dev/fdt/dwmmc.c

615

uint32_t cdetect;

sys/dev/fdt/dwmmc.c

636

dwmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)

sys/dev/fdt/dwmmc.c

639

uint32_t vdd = 0;

sys/dev/fdt/dwmmc.c

664

uint32_t clkena;

sys/dev/fdt/dwmmc.c

782

uint32_t flags;

sys/dev/fdt/dwmmc.c

807

uint32_t flags;

sys/dev/fdt/dwmmc.c

899

uint32_t cmdval = SDMMC_CMD_START_CMD | SDMMC_CMD_USE_HOLD_REG;

sys/dev/fdt/dwmmc.c

900

uint32_t status;

sys/dev/fdt/dwmshc.c

163

uint32_t txclk_tapnum;

sys/dev/fdt/dwmshc.c

164

uint32_t rxclk;

sys/dev/fdt/dwmshc.c

190

bus_size_t, uint32_t);

sys/dev/fdt/dwmshc.c

191

static inline uint32_t dwmshc_rd4(struct dwmshc_softc *, bus_size_t);

sys/dev/fdt/dwmshc.c

251

uint32_t freq;

sys/dev/fdt/dwmshc.c

344

uint32_t status0;

sys/dev/fdt/dwmshc.c

369

uint32_t txclk_tapnum = sc->sc_params->txclk_tapnum;

sys/dev/fdt/dwmshc.c

370

uint32_t dll_val;

sys/dev/fdt/dwmshc.c

451

dwmshc_wr4(struct dwmshc_softc *sc, bus_size_t off, uint32_t v)

sys/dev/fdt/dwmshc.c

456

static inline uint32_t

sys/dev/fdt/dwpcie.c

1045

uint32_t reg, mask;

sys/dev/fdt/dwpcie.c

1057

uint32_t cause;

sys/dev/fdt/dwpcie.c

1070

uint32_t *reset_gpio;

sys/dev/fdt/dwpcie.c

1072

uint32_t reg;

sys/dev/fdt/dwpcie.c

1131

uint32_t reg;

sys/dev/fdt/dwpcie.c

1144

uint32_t *clkreq_gpio, *disable_gpio, *reset_gpio;

sys/dev/fdt/dwpcie.c

1147

uint32_t off, reg;

sys/dev/fdt/dwpcie.c

1361

uint32_t cause;

sys/dev/fdt/dwpcie.c

1398

uint32_t apmu[2], val;

sys/dev/fdt/dwpcie.c

1499

uint32_t reg;

sys/dev/fdt/dwpcie.c

1513

uint32_t *reset_gpio;

sys/dev/fdt/dwpcie.c

1614

uint32_t status;

sys/dev/fdt/dwpcie.c

1645

uint32_t mask = (1U << pin);

sys/dev/fdt/dwpcie.c

1682

uint32_t mask = (1U << di->di_pin);

sys/dev/fdt/dwpcie.c

1725

uint32_t val)

sys/dev/fdt/dwpcie.c

1741

uint32_t

sys/dev/fdt/dwpcie.c

1767

uint32_t reg;

sys/dev/fdt/dwpcie.c

1792

uint32_t reg;

sys/dev/fdt/dwpcie.c

1820

uint32_t reg[5];

sys/dev/fdt/dwpcie.c

1821

uint32_t phys_hi;

sys/dev/fdt/dwpcie.c

1875

uint32_t ret;

sys/dev/fdt/dwpcie.c

200

uint32_t flags;

sys/dev/fdt/dwpcie.c

2135

if (bus_dmamap_create(dmat, sizeof(uint32_t), 1,

sys/dev/fdt/dwpcie.c

2136

sizeof(uint32_t), 0, BUS_DMA_WAITOK, &map)) {

sys/dev/fdt/dwpcie.c

2144

seg.ds_len = sizeof(uint32_t);

sys/dev/fdt/dwpcie.c

2147

sizeof(uint32_t), BUS_DMA_WAITOK)) {

sys/dev/fdt/dwpcie.c

2166

uint32_t reg[4];

sys/dev/fdt/dwpcie.c

390

uint32_t *ranges;

sys/dev/fdt/dwpcie.c

472

if (rangeslen <= 0 || (rangeslen % sizeof(uint32_t)) ||

sys/dev/fdt/dwpcie.c

473

(rangeslen / sizeof(uint32_t)) % (sc->sc_acells +

sys/dev/fdt/dwpcie.c

483

nranges = (rangeslen / sizeof(uint32_t)) /

sys/dev/fdt/dwpcie.c

545

uint32_t bus_range[2];

sys/dev/fdt/dwpcie.c

799

uint32_t mode, width, reg;

sys/dev/fdt/dwpcie.c

845

uint32_t status;

sys/dev/fdt/dwpcie.c

899

error = bus_dmamem_alloc(sc->sc_dmat, sizeof(uint32_t),

sys/dev/fdt/dwpcie.c

900

sizeof(uint32_t), 0, &seg, 1, &rseg, BUS_DMA_WAITOK);

sys/dev/fdt/dwpcie.c

908

error = bus_dmamap_create(sc->sc_dmat, sizeof(uint32_t), 1,

sys/dev/fdt/dwpcie.c

909

sizeof(uint32_t), 0, BUS_DMA_WAITOK, &map);

sys/dev/fdt/dwpcie.c

915

sizeof(uint32_t), BUS_DMA_WAITOK);

sys/dev/fdt/dwpcie.c

981

uint32_t reg;

sys/dev/fdt/ehci_fdt.c

131

uint32_t usbmode;

sys/dev/fdt/ehci_fdt.c

192

void (*init)(struct ehci_fdt_softc *, uint32_t *);

sys/dev/fdt/ehci_fdt.c

195

void sun4i_phy_init(struct ehci_fdt_softc *, uint32_t *);

sys/dev/fdt/ehci_fdt.c

196

void sun9i_phy_init(struct ehci_fdt_softc *, uint32_t *);

sys/dev/fdt/ehci_fdt.c

215

uint32_t *

sys/dev/fdt/ehci_fdt.c

216

ehci_next_phy(uint32_t *cells)

sys/dev/fdt/ehci_fdt.c

218

uint32_t phandle = cells[0];

sys/dev/fdt/ehci_fdt.c

230

ehci_init_phy(struct ehci_fdt_softc *sc, uint32_t *cells)

sys/dev/fdt/ehci_fdt.c

232

uint32_t phy_supply;

sys/dev/fdt/ehci_fdt.c

255

uint32_t *phys;

sys/dev/fdt/ehci_fdt.c

256

uint32_t *phy;

sys/dev/fdt/ehci_fdt.c

270

while (phy && phy < phys + (len / sizeof(uint32_t))) {

sys/dev/fdt/ehci_fdt.c

294

uint32_t *reg, val;

sys/dev/fdt/ehci_fdt.c

310

if (idx < 0 || (idx + 1) > (len / (sizeof(uint32_t) * 2))) {

sys/dev/fdt/ehci_fdt.c

347

sun4i_phy_init(struct ehci_fdt_softc *sc, uint32_t *cells)

sys/dev/fdt/ehci_fdt.c

349

uint32_t vbus_supply;

sys/dev/fdt/ehci_fdt.c

351

uint32_t val;

sys/dev/fdt/ehci_fdt.c

419

sun9i_phy_init(struct ehci_fdt_softc *sc, uint32_t *cells)

sys/dev/fdt/ehci_fdt.c

421

uint32_t phy_supply;

sys/dev/fdt/ehci_fdt.c

422

uint32_t val;

sys/dev/fdt/es8316ac.c

122

int escodec_set_format(void *, uint32_t, uint32_t, uint32_t);

sys/dev/fdt/es8316ac.c

123

int escodec_set_sysclk(void *, uint32_t);

sys/dev/fdt/es8316ac.c

260

escodec_set_format(void *cookie, uint32_t fmt, uint32_t pol,

sys/dev/fdt/es8316ac.c

261

uint32_t clk)

sys/dev/fdt/es8316ac.c

326

escodec_set_sysclk(void *cookie, uint32_t rate)

sys/dev/fdt/exrtc.c

133

uint32_t val;

sys/dev/fdt/exuart.c

136

uint32_t exuart_rx_fifo_cnt_mask;

sys/dev/fdt/exuart.c

137

uint32_t exuart_rx_fifo_full;

sys/dev/fdt/exuart.c

138

uint32_t exuart_tx_fifo_full;

sys/dev/fdt/exuart.c

59

uint32_t sc_rx_fifo_cnt_mask;

sys/dev/fdt/exuart.c

60

uint32_t sc_rx_fifo_full;

sys/dev/fdt/exuart.c

61

uint32_t sc_tx_fifo_full;

sys/dev/fdt/fanpwr.c

109

uint32_t voltage, ramp_delay;

sys/dev/fdt/fanpwr.c

290

uint32_t

sys/dev/fdt/fanpwr.c

301

fanpwr_set_voltage(void *cookie, uint32_t voltage)

sys/dev/fdt/fanpwr.c

304

uint32_t vmin = sc->sc_vbase;

sys/dev/fdt/fanpwr.c

305

uint32_t vmax = vmin + sc->sc_vsel_nsel_mask * sc->sc_vstep;

sys/dev/fdt/fanpwr.c

70

uint32_t sc_vbase;

sys/dev/fdt/fanpwr.c

71

uint32_t sc_vstep;

sys/dev/fdt/fanpwr.c

87

uint32_t fanpwr_get_voltage(void *);

sys/dev/fdt/fanpwr.c

88

int fanpwr_set_voltage(void *, uint32_t);

sys/dev/fdt/fusbtc.c

206

uint32_t *sc_ss_sel;

sys/dev/fdt/gpiobl.c

39

uint32_t sc_gpio[3];

sys/dev/fdt/gpiocharger.c

38

uint32_t *sc_charger_pin;

sys/dev/fdt/gpiokeys.c

112

uint32_t code;

sys/dev/fdt/gpiokeys.c

64

uint32_t *key_pin;

sys/dev/fdt/gpiokeys.c

65

uint32_t key_input_type;

sys/dev/fdt/gpiokeys.c

66

uint32_t key_code;

sys/dev/fdt/gpioleds.c

61

uint32_t *led_pin;

sys/dev/fdt/gpiorestart.c

34

uint32_t *sc_gpio;

sys/dev/fdt/gpiorestart.c

35

uint32_t sc_active_delay;

sys/dev/fdt/gpiorestart.c

36

uint32_t sc_inactive_delay;

sys/dev/fdt/gpiorestart.c

37

uint32_t sc_wait_delay;

sys/dev/fdt/graphaudio.c

117

uint32_t fmt, pol, clk;

sys/dev/fdt/graphaudio.c

118

uint32_t dais;

sys/dev/fdt/graphaudio.c

191

graphaudio_set_format(struct graphaudio_softc *sc, uint32_t fmt, uint32_t pol,

sys/dev/fdt/graphaudio.c

192

uint32_t clk)

sys/dev/fdt/graphaudio.c

258

uint32_t rate;

sys/dev/fdt/graphaudio.c

37

uint32_t sc_mclk_fs;

sys/dev/fdt/graphaudio.c

46

void graphaudio_set_format(struct graphaudio_softc *, uint32_t,

sys/dev/fdt/graphaudio.c

47

uint32_t, uint32_t);

sys/dev/fdt/hiclock.c

184

uint32_t

sys/dev/fdt/hiclock.c

185

hiclock_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/hiclock.c

187

uint32_t idx = cells[0];

sys/dev/fdt/hiclock.c

194

hiclock_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/hiclock.c

196

uint32_t idx = cells[0];

sys/dev/fdt/hiclock.c

225

uint32_t

sys/dev/fdt/hiclock.c

226

hi3670_crgctrl_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/hiclock.c

229

uint32_t idx = cells[0];

sys/dev/fdt/hiclock.c

230

uint32_t reg, freq, div;

sys/dev/fdt/hiclock.c

287

hi3670_crgctrl_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/hiclock.c

289

uint32_t idx = cells[0];

sys/dev/fdt/hiclock.c

308

uint32_t

sys/dev/fdt/hiclock.c

309

hi3670_stub_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/hiclock.c

312

uint32_t idx = cells[0];

sys/dev/fdt/hiclock.c

313

uint32_t reg;

sys/dev/fdt/hiclock.c

331

hi3670_stub_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/hiclock.c

334

uint32_t idx = cells[0];

sys/dev/fdt/hiclock.c

335

uint32_t reg;

sys/dev/fdt/hiclock.c

65

uint32_t (*get_frequency)(void *, uint32_t *);

sys/dev/fdt/hiclock.c

66

int (*set_frequency)(void *, uint32_t *, uint32_t);

sys/dev/fdt/hiclock.c

67

void (*enable)(void *, uint32_t *, int);

sys/dev/fdt/hiclock.c

70

uint32_t hiclock_get_frequency(void *, uint32_t *);

sys/dev/fdt/hiclock.c

71

void hiclock_enable(void *, uint32_t *, int);

sys/dev/fdt/hiclock.c

73

uint32_t hi3670_crgctrl_get_frequency(void *, uint32_t *);

sys/dev/fdt/hiclock.c

74

void hi3670_crgctrl_enable(void *, uint32_t *, int);

sys/dev/fdt/hiclock.c

75

uint32_t hi3670_stub_get_frequency(void *, uint32_t *);

sys/dev/fdt/hiclock.c

76

int hi3670_stub_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/hidwusb.c

66

uint32_t gpio[3];

sys/dev/fdt/hireset.c

33

uint32_t sc_rst_syscon;

sys/dev/fdt/hireset.c

49

void hireset_reset(void *, uint32_t *, int);

sys/dev/fdt/hireset.c

76

hireset_reset(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/hireset.c

80

uint32_t offset = cells[0];

sys/dev/fdt/hireset.c

81

uint32_t bit = cells[1];

sys/dev/fdt/hitemp.c

161

uint32_t value;

sys/dev/fdt/if_bse_fdt.c

58

uint32_t phy;

sys/dev/fdt/if_cad.c

1092

uint32_t netcfg;

sys/dev/fdt/if_cad.c

1198

uint32_t status;

sys/dev/fdt/if_cad.c

1276

uint32_t isr;

sys/dev/fdt/if_cad.c

1322

uint32_t addr, status;

sys/dev/fdt/if_cad.c

1459

uint32_t status;

sys/dev/fdt/if_cad.c

1603

cad_mii_oper(struct cad_softc *sc, int phy_no, int reg, uint32_t oper)

sys/dev/fdt/if_cad.c

1652

uint32_t netcfg;

sys/dev/fdt/if_cad.c

1816

uint32_t c_reg;

sys/dev/fdt/if_cad.c

210

uint32_t d_addr;

sys/dev/fdt/if_cad.c

211

uint32_t d_status;

sys/dev/fdt/if_cad.c

215

uint32_t d_addrlo;

sys/dev/fdt/if_cad.c

216

uint32_t d_status;

sys/dev/fdt/if_cad.c

217

uint32_t d_addrhi;

sys/dev/fdt/if_cad.c

218

uint32_t d_unused;

sys/dev/fdt/if_cad.c

281

uint32_t sc_qmask;

sys/dev/fdt/if_cad.c

301

uint32_t sc_netctl;

sys/dev/fdt/if_cad.c

305

uint32_t sc_tx_freq;

sys/dev/fdt/if_cad.c

393

uint32_t phy_reset_gpio[3];

sys/dev/fdt/if_cad.c

394

uint32_t phy_reset_duration;

sys/dev/fdt/if_cad.c

395

uint32_t hi, lo;

sys/dev/fdt/if_cad.c

396

uint32_t rev, ver;

sys/dev/fdt/if_cad.c

397

uint32_t val;

sys/dev/fdt/if_cad.c

662

uint32_t div, netcfg;

sys/dev/fdt/if_cad.c

721

uint32_t val;

sys/dev/fdt/if_cad.c

890

((uint32_t)sc->sc_ac.ac_enaddr[1] << 8) |

sys/dev/fdt/if_cad.c

891

((uint32_t)sc->sc_ac.ac_enaddr[2] << 16) |

sys/dev/fdt/if_cad.c

892

((uint32_t)sc->sc_ac.ac_enaddr[3] << 24));

sys/dev/fdt/if_cad.c

894

((uint32_t)sc->sc_ac.ac_enaddr[5] << 8));

sys/dev/fdt/if_dwge.c

1142

uint32_t mode;

sys/dev/fdt/if_dwge.c

1245

uint32_t dmactrl;

sys/dev/fdt/if_dwge.c

1300

static uint32_t

sys/dev/fdt/if_dwge.c

1301

bitrev32(uint32_t x)

sys/dev/fdt/if_dwge.c

1318

uint32_t crc, hash[2], hashbit, hashreg;

sys/dev/fdt/if_dwge.c

1319

uint32_t reg;

sys/dev/fdt/if_dwge.c

1453

uint32_t dmactrl;

sys/dev/fdt/if_dwge.c

1574

uint32_t freq;

sys/dev/fdt/if_dwge.c

1648

uint32_t grf;

sys/dev/fdt/if_dwge.c

1737

uint32_t grf;

sys/dev/fdt/if_dwge.c

1738

uint32_t gmac_clk_sel = 0;

sys/dev/fdt/if_dwge.c

1772

uint32_t c_reg;

sys/dev/fdt/if_dwge.c

179

uint32_t sd_status;

sys/dev/fdt/if_dwge.c

180

uint32_t sd_len;

sys/dev/fdt/if_dwge.c

181

uint32_t sd_addr;

sys/dev/fdt/if_dwge.c

182

uint32_t sd_next;

sys/dev/fdt/if_dwge.c

300

uint32_t sc_clk;

sys/dev/fdt/if_dwge.c

303

uint32_t sc_clk_sel_125;

sys/dev/fdt/if_dwge.c

304

uint32_t sc_clk_sel_25;

sys/dev/fdt/if_dwge.c

305

uint32_t sc_clk_sel_2_5;

sys/dev/fdt/if_dwge.c

330

uint32_t dwge_read(struct dwge_softc *, bus_addr_t);

sys/dev/fdt/if_dwge.c

331

void dwge_write(struct dwge_softc *, bus_addr_t, uint32_t);

sys/dev/fdt/if_dwge.c

394

uint32_t phy, phy_supply;

sys/dev/fdt/if_dwge.c

395

uint32_t axi_config;

sys/dev/fdt/if_dwge.c

396

uint32_t mode, pbl;

sys/dev/fdt/if_dwge.c

397

uint32_t version;

sys/dev/fdt/if_dwge.c

398

uint32_t feature;

sys/dev/fdt/if_dwge.c

565

uint32_t blen[7] = { 0 };

sys/dev/fdt/if_dwge.c

566

uint32_t osr_lmt;

sys/dev/fdt/if_dwge.c

651

uint32_t *gpio;

sys/dev/fdt/if_dwge.c

652

uint32_t delays[3];

sys/dev/fdt/if_dwge.c

682

uint32_t

sys/dev/fdt/if_dwge.c

689

dwge_write(struct dwge_softc *sc, bus_addr_t addr, uint32_t data)

sys/dev/fdt/if_dwge.c

697

uint32_t machi, maclo;

sys/dev/fdt/if_dwge.c

905

uint32_t conf;

sys/dev/fdt/if_dwge.c

964

uint32_t mode;

sys/dev/fdt/if_dwge.c

995

uint32_t reg;

sys/dev/fdt/if_dwqe_fdt.c

105

uint32_t phy, phy_supply;

sys/dev/fdt/if_dwqe_fdt.c

106

uint32_t axi_config;

sys/dev/fdt/if_dwqe_fdt.c

303

dwqe_reset_phy(struct dwqe_softc *sc, uint32_t phy)

sys/dev/fdt/if_dwqe_fdt.c

305

uint32_t *gpio;

sys/dev/fdt/if_dwqe_fdt.c

306

uint32_t delays[3];

sys/dev/fdt/if_dwqe_fdt.c

425

uint32_t cells[3];

sys/dev/fdt/if_dwqe_fdt.c

426

uint32_t phandle, offset, reg, shift;

sys/dev/fdt/if_dwqe_fdt.c

428

uint32_t iface;

sys/dev/fdt/if_dwqe_fdt.c

500

uint32_t grf;

sys/dev/fdt/if_dwqe_fdt.c

502

uint32_t iface;

sys/dev/fdt/if_dwqe_fdt.c

564

uint32_t grf;

sys/dev/fdt/if_dwqe_fdt.c

565

uint32_t reg, clk_sel = 0;

sys/dev/fdt/if_dwqe_fdt.c

616

uint32_t grf;

sys/dev/fdt/if_dwqe_fdt.c

618

uint32_t iface;

sys/dev/fdt/if_dwqe_fdt.c

704

uint32_t grf, php_grf;

sys/dev/fdt/if_dwqe_fdt.c

706

uint32_t mode;

sys/dev/fdt/if_dwqe_fdt.c

784

uint32_t grf;

sys/dev/fdt/if_dwqe_fdt.c

785

uint32_t gmac_clk_sel = 0;

sys/dev/fdt/if_dwqe_fdt.c

816

uint32_t grf, php_grf;

sys/dev/fdt/if_dwqe_fdt.c

818

uint32_t iface, clk;

sys/dev/fdt/if_dwqe_fdt.c

87

void dwqe_reset_phy(struct dwqe_softc *, uint32_t);

sys/dev/fdt/if_dwqe_fdt.c

894

uint32_t php_grf;

sys/dev/fdt/if_dwqe_fdt.c

895

uint32_t gmac_clk_sel = 0;

sys/dev/fdt/if_dwxe.c

1131

uint32_t dmactrl;

sys/dev/fdt/if_dwxe.c

1192

static uint32_t

sys/dev/fdt/if_dwxe.c

1193

bitrev32(uint32_t x)

sys/dev/fdt/if_dwxe.c

1210

uint32_t crc, hash[2], hashbit, hashreg;

sys/dev/fdt/if_dwxe.c

1211

uint32_t reg;

sys/dev/fdt/if_dwxe.c

1329

uint32_t dmactrl;

sys/dev/fdt/if_dwxe.c

169

uint32_t sd_status;

sys/dev/fdt/if_dwxe.c

170

uint32_t sd_len;

sys/dev/fdt/if_dwxe.c

171

uint32_t sd_addr;

sys/dev/fdt/if_dwxe.c

172

uint32_t sd_next;

sys/dev/fdt/if_dwxe.c

303

uint32_t sc_clk;

sys/dev/fdt/if_dwxe.c

324

uint32_t dwxe_read(struct dwxe_softc *, bus_addr_t);

sys/dev/fdt/if_dwxe.c

325

void dwxe_write(struct dwxe_softc *, bus_addr_t, uint32_t);

sys/dev/fdt/if_dwxe.c

379

uint32_t phy;

sys/dev/fdt/if_dwxe.c

492

uint32_t phy_supply;

sys/dev/fdt/if_dwxe.c

519

uint32_t syscon;

sys/dev/fdt/if_dwxe.c

520

uint32_t tx_delay, rx_delay;

sys/dev/fdt/if_dwxe.c

566

uint32_t syscon;

sys/dev/fdt/if_dwxe.c

567

uint32_t rx_delay;

sys/dev/fdt/if_dwxe.c

594

uint32_t

sys/dev/fdt/if_dwxe.c

601

dwxe_write(struct dwxe_softc *sc, bus_addr_t addr, uint32_t data)

sys/dev/fdt/if_dwxe.c

609

uint32_t machi, maclo;

sys/dev/fdt/if_dwxe.c

818

uint32_t basicctrl;

sys/dev/fdt/if_dwxe.c

873

uint32_t ctl;

sys/dev/fdt/if_dwxe.c

904

uint32_t reg;

sys/dev/fdt/if_fec.c

1207

uint32_t ecr, rcr;

sys/dev/fdt/if_fec.c

206

uint32_t fd_addr; /* payload's buffer address */

sys/dev/fdt/if_fec.c

208

uint32_t fd_enhanced_status; /* enhanced status with IEEE 1588 */

sys/dev/fdt/if_fec.c

209

uint32_t fd_reserved0; /* reserved */

sys/dev/fdt/if_fec.c

210

uint32_t fd_update_done; /* buffer descriptor update done */

sys/dev/fdt/if_fec.c

211

uint32_t fd_timestamp; /* IEEE 1588 timestamp */

sys/dev/fdt/if_fec.c

212

uint32_t fd_reserved1[2]; /* reserved */

sys/dev/fdt/if_fec.c

242

uint32_t sc_phy_speed;

sys/dev/fdt/if_fec.c

299

uint32_t phy_reset_gpio[3];

sys/dev/fdt/if_fec.c

300

uint32_t phy_reset_duration;

sys/dev/fdt/if_fec.c

481

uint32_t reg;

sys/dev/fdt/if_fec.c

510

uint32_t rxc, rxdv, txc, txen;

sys/dev/fdt/if_fec.c

511

uint32_t rxd0, rxd1, rxd2, rxd3;

sys/dev/fdt/if_fec.c

512

uint32_t txd0, txd1, txd2, txd3;

sys/dev/fdt/if_fec.c

513

uint32_t val, phy;

sys/dev/fdt/if_fec.c

551

uint32_t rxc, rxdv, txc, txen;

sys/dev/fdt/if_fec.c

552

uint32_t rxd0, rxd1, rxd2, rxd3;

sys/dev/fdt/if_fec.c

553

uint32_t txd0, txd1, txd2, txd3;

sys/dev/fdt/if_fec.c

554

uint32_t val, phy;

sys/dev/fdt/if_fec.c

784

uint32_t h;

sys/dev/fdt/if_fec.c

805

HWRITE4(sc, ENET_GAUR, (uint32_t)(ghash >> 32));

sys/dev/fdt/if_fec.c

806

HWRITE4(sc, ENET_GALR, (uint32_t)ghash);

sys/dev/fdt/if_fec.c

808

HWRITE4(sc, ENET_IAUR, (uint32_t)(ihash >> 32));

sys/dev/fdt/if_fec.c

809

HWRITE4(sc, ENET_IALR, (uint32_t)ihash);

sys/dev/fdt/if_mvneta.c

1095

uint32_t panc = MVNETA_READ(sc, MVNETA_PANC);

sys/dev/fdt/if_mvneta.c

1103

uint32_t panc = MVNETA_READ(sc, MVNETA_PANC);

sys/dev/fdt/if_mvneta.c

1244

uint32_t reg, txinprog, txfifoemp;

sys/dev/fdt/if_mvneta.c

1425

uint32_t rxstat;

sys/dev/fdt/if_mvneta.c

1631

uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT];

sys/dev/fdt/if_mvneta.c

1632

uint32_t pxc;

sys/dev/fdt/if_mvneta.c

1924

uint32_t hi, lo;

sys/dev/fdt/if_mvneta.c

256

uint32_t panc = MVNETA_READ(sc, MVNETA_PANC);

sys/dev/fdt/if_mvneta.c

289

uint32_t reg;

sys/dev/fdt/if_mvneta.c

316

uint32_t maddrh, maddrl;

sys/dev/fdt/if_mvneta.c

330

uint32_t en;

sys/dev/fdt/if_mvneta.c

396

uint32_t mode;

sys/dev/fdt/if_mvneta.c

441

uint32_t ctl0, ctl2, ctl4, panc;

sys/dev/fdt/if_mvneta.c

528

uint32_t maddrh, maddrl;

sys/dev/fdt/if_mvneta.c

603

uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT];

sys/dev/fdt/if_mvneta.c

841

uint32_t ic, misc;

sys/dev/fdt/if_mvneta.c

904

uint32_t cmdsts;

sys/dev/fdt/if_mvneta.c

920

const int iphdr_unitlen = sizeof(struct ip) / sizeof(uint32_t);

sys/dev/fdt/if_mvnetareg.h

775

uint32_t cmdsts; /* Descriptor command status */

sys/dev/fdt/if_mvnetareg.h

776

uint32_t nextdescptr; /* Next descriptor pointer */

sys/dev/fdt/if_mvnetareg.h

777

uint32_t bufptr; /* Descriptor buffer pointer */

sys/dev/fdt/if_mvnetareg.h

779

uint32_t cmdsts; /* Descriptor command status */

sys/dev/fdt/if_mvnetareg.h

782

uint32_t bufptr; /* Descriptor buffer pointer */

sys/dev/fdt/if_mvnetareg.h

783

uint32_t nextdescptr; /* Next descriptor pointer */

sys/dev/fdt/if_mvnetareg.h

785

uint32_t _padding[4];

sys/dev/fdt/if_mvnetareg.h

792

uint32_t cmdsts; /* Descriptor command status */

sys/dev/fdt/if_mvnetareg.h

793

uint32_t nextdescptr; /* Next descriptor pointer */

sys/dev/fdt/if_mvnetareg.h

794

uint32_t bufptr; /* Descriptor buffer pointer */

sys/dev/fdt/if_mvnetareg.h

796

uint32_t cmdsts; /* Descriptor command status */

sys/dev/fdt/if_mvnetareg.h

799

uint32_t bufptr; /* Descriptor buffer pointer */

sys/dev/fdt/if_mvnetareg.h

800

uint32_t nextdescptr; /* Next descriptor pointer */

sys/dev/fdt/if_mvnetareg.h

802

uint32_t _padding[4];

sys/dev/fdt/if_mvpp.c

111

uint32_t *freelist;

sys/dev/fdt/if_mvpp.c

130

uint32_t done_pkts_coal;

sys/dev/fdt/if_mvpp.c

1326

uint32_t phy, reg;

sys/dev/fdt/if_mvpp.c

141

uint32_t pkts_coal;

sys/dev/fdt/if_mvpp.c

142

uint32_t time_coal;

sys/dev/fdt/if_mvpp.c

1576

uint32_t reg;

sys/dev/fdt/if_mvpp.c

1615

uint32_t

sys/dev/fdt/if_mvpp.c

1622

mvpp2_write(struct mvpp2_softc *sc, bus_addr_t addr, uint32_t data)

sys/dev/fdt/if_mvpp.c

1627

uint32_t

sys/dev/fdt/if_mvpp.c

1635

mvpp2_gmac_write(struct mvpp2_port *sc, bus_addr_t addr, uint32_t data)

sys/dev/fdt/if_mvpp.c

1642

uint32_t

sys/dev/fdt/if_mvpp.c

1650

mvpp2_xlg_write(struct mvpp2_port *sc, bus_addr_t addr, uint32_t data)

sys/dev/fdt/if_mvpp.c

1657

uint32_t

sys/dev/fdt/if_mvpp.c

1665

mvpp2_mpcs_write(struct mvpp2_port *sc, bus_addr_t addr, uint32_t data)

sys/dev/fdt/if_mvpp.c

1672

uint32_t

sys/dev/fdt/if_mvpp.c

1680

mvpp2_xpcs_write(struct mvpp2_port *sc, bus_addr_t addr, uint32_t data)

sys/dev/fdt/if_mvpp.c

169

uint32_t sc_tclk;

sys/dev/fdt/if_mvpp.c

1711

uint32_t command;

sys/dev/fdt/if_mvpp.c

1942

uint32_t reg;

sys/dev/fdt/if_mvpp.c

1978

uint32_t reg;

sys/dev/fdt/if_mvpp.c

2046

uint32_t reg;

sys/dev/fdt/if_mvpp.c

2076

uint32_t reg;

sys/dev/fdt/if_mvpp.c

2170

uint32_t i, nrecv, pool;

sys/dev/fdt/if_mvpp.c

222

uint32_t sc_tx_time_coal;

sys/dev/fdt/if_mvpp.c

2351

uint32_t reg;

sys/dev/fdt/if_mvpp.c

2454

uint32_t reg;

sys/dev/fdt/if_mvpp.c

2473

uint32_t reg;

sys/dev/fdt/if_mvpp.c

2495

uint32_t reg;

sys/dev/fdt/if_mvpp.c

2585

uint32_t ctl0, ctl4;

sys/dev/fdt/if_mvpp.c

2607

uint32_t ctl0, ctl2, ctl4, panc;

sys/dev/fdt/if_mvpp.c

261

uint32_t mvpp2_read(struct mvpp2_softc *, bus_addr_t);

sys/dev/fdt/if_mvpp.c

262

void mvpp2_write(struct mvpp2_softc *, bus_addr_t, uint32_t);

sys/dev/fdt/if_mvpp.c

263

uint32_t mvpp2_gmac_read(struct mvpp2_port *, bus_addr_t);

sys/dev/fdt/if_mvpp.c

264

void mvpp2_gmac_write(struct mvpp2_port *, bus_addr_t, uint32_t);

sys/dev/fdt/if_mvpp.c

265

uint32_t mvpp2_xlg_read(struct mvpp2_port *, bus_addr_t);

sys/dev/fdt/if_mvpp.c

266

void mvpp2_xlg_write(struct mvpp2_port *, bus_addr_t, uint32_t);

sys/dev/fdt/if_mvpp.c

267

uint32_t mvpp2_xpcs_read(struct mvpp2_port *, bus_addr_t);

sys/dev/fdt/if_mvpp.c

268

void mvpp2_xpcs_write(struct mvpp2_port *, bus_addr_t, uint32_t);

sys/dev/fdt/if_mvpp.c

269

uint32_t mvpp2_mpcs_read(struct mvpp2_port *, bus_addr_t);

sys/dev/fdt/if_mvpp.c

270

void mvpp2_mpcs_write(struct mvpp2_port *, bus_addr_t, uint32_t);

sys/dev/fdt/if_mvpp.c

2708

uint32_t mode;

sys/dev/fdt/if_mvpp.c

2756

uint32_t reg;

sys/dev/fdt/if_mvpp.c

2827

uint32_t reg;

sys/dev/fdt/if_mvpp.c

2844

uint32_t reg;

sys/dev/fdt/if_mvpp.c

2865

uint32_t reg;

sys/dev/fdt/if_mvpp.c

2908

uint32_t reg;

sys/dev/fdt/if_mvpp.c

2964

uint32_t i, nrecv, pool;

sys/dev/fdt/if_mvpp.c

3020

uint32_t val;

sys/dev/fdt/if_mvpp.c

3036

uint32_t val;

sys/dev/fdt/if_mvpp.c

3221

uint32_t val;

sys/dev/fdt/if_mvpp.c

3235

uint32_t val;

sys/dev/fdt/if_mvpp.c

3250

uint32_t qmap;

sys/dev/fdt/if_mvpp.c

3270

uint32_t reg_data;

sys/dev/fdt/if_mvpp.c

3297

uint32_t val;

sys/dev/fdt/if_mvpp.c

3316

uint32_t val;

sys/dev/fdt/if_mvpp.c

3333

uint32_t val = mvpp2_read(port->sc, MVPP2_RXQ_STATUS_REG(rxq_id));

sys/dev/fdt/if_mvpp.c

3342

uint32_t val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);

sys/dev/fdt/if_mvpp.c

3349

uint32_t val;

sys/dev/fdt/if_mvpp.c

3362

uint32_t val, size, mtu;

sys/dev/fdt/if_mvpp.c

3407

uint32_t pkts)

sys/dev/fdt/if_mvpp.c

341

uint32_t);

sys/dev/fdt/if_mvpp.c

3420

uint32_t pkts)

sys/dev/fdt/if_mvpp.c

343

uint32_t);

sys/dev/fdt/if_mvpp.c

3433

uint32_t usec)

sys/dev/fdt/if_mvpp.c

3435

uint32_t val;

sys/dev/fdt/if_mvpp.c

3444

mvpp2_tx_time_coal_set(struct mvpp2_port *port, uint32_t usec)

sys/dev/fdt/if_mvpp.c

3446

uint32_t val;

sys/dev/fdt/if_mvpp.c

345

uint32_t);

sys/dev/fdt/if_mvpp.c

3456

uint32_t ri, uint32_t ri_mask)

sys/dev/fdt/if_mvpp.c

346

void mvpp2_tx_time_coal_set(struct mvpp2_port *, uint32_t);

sys/dev/fdt/if_mvpp.c

3463

mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, uint32_t lu)

sys/dev/fdt/if_mvpp.c

3472

mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe, uint32_t port, int add)

sys/dev/fdt/if_mvpp.c

3483

mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe, uint32_t port_mask)

sys/dev/fdt/if_mvpp.c

3493

uint32_t

sys/dev/fdt/if_mvpp.c

3502

mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe, uint32_t offs,

sys/dev/fdt/if_mvpp.c

3510

mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, uint32_t offs,

sys/dev/fdt/if_mvpp.c

3529

mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe, uint32_t bits, uint32_t enable)

sys/dev/fdt/if_mvpp.c

3553

mvpp2_prs_tcam_data_word_get(struct mvpp2_prs_entry *pe, uint32_t data_offset,

sys/dev/fdt/if_mvpp.c

3554

uint32_t *word, uint32_t *enable)

sys/dev/fdt/if_mvpp.c

3568

mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, uint32_t offs,

sys/dev/fdt/if_mvpp.c

3576

mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, uint32_t bit, uint32_t val)

sys/dev/fdt/if_mvpp.c

3582

mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, uint32_t bit, uint32_t val)

sys/dev/fdt/if_mvpp.c

3588

mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, uint32_t bits, uint32_t mask)

sys/dev/fdt/if_mvpp.c

3614

mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, uint32_t bits, uint32_t mask)

sys/dev/fdt/if_mvpp.c

3648

mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift, uint32_t op)

sys/dev/fdt/if_mvpp.c

365

uint32_t, uint32_t);

sys/dev/fdt/if_mvpp.c

366

void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *, uint32_t);

sys/dev/fdt/if_mvpp.c

3666

mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe, uint32_t type, int offset,

sys/dev/fdt/if_mvpp.c

3667

uint32_t op)

sys/dev/fdt/if_mvpp.c

367

void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *, uint32_t, int);

sys/dev/fdt/if_mvpp.c

368

void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *, uint32_t);

sys/dev/fdt/if_mvpp.c

369

uint32_t mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *);

sys/dev/fdt/if_mvpp.c

370

void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *, uint32_t,

sys/dev/fdt/if_mvpp.c

3704

mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe, uint32_t lu)

sys/dev/fdt/if_mvpp.c

3713

mvpp2_prs_shadow_set(struct mvpp2_softc *sc, int index, uint32_t lu)

sys/dev/fdt/if_mvpp.c

372

void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *, uint32_t,

sys/dev/fdt/if_mvpp.c

375

void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *, uint32_t, uint32_t);

sys/dev/fdt/if_mvpp.c

378

void mvpp2_prs_tcam_data_word_get(struct mvpp2_prs_entry *, uint32_t,

sys/dev/fdt/if_mvpp.c

379

uint32_t *, uint32_t *);

sys/dev/fdt/if_mvpp.c

380

void mvpp2_prs_match_etype(struct mvpp2_prs_entry *, uint32_t, uint16_t);

sys/dev/fdt/if_mvpp.c

3809

mvpp2_prs_mac_drop_all_set(struct mvpp2_softc *sc, uint32_t port, int add)

sys/dev/fdt/if_mvpp.c

382

void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *, uint32_t, uint32_t);

sys/dev/fdt/if_mvpp.c

383

void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *, uint32_t, uint32_t);

sys/dev/fdt/if_mvpp.c

3832

mvpp2_prs_mac_promisc_set(struct mvpp2_softc *sc, uint32_t port, int l2_cast,

sys/dev/fdt/if_mvpp.c

3837

uint32_t ri;

sys/dev/fdt/if_mvpp.c

384

void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *, uint32_t, uint32_t);

sys/dev/fdt/if_mvpp.c

385

void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *, uint32_t, uint32_t);

sys/dev/fdt/if_mvpp.c

386

void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *, int, uint32_t);

sys/dev/fdt/if_mvpp.c

387

void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *, uint32_t, int,

sys/dev/fdt/if_mvpp.c

3871

mvpp2_prs_dsa_tag_set(struct mvpp2_softc *sc, uint32_t port, int add,

sys/dev/fdt/if_mvpp.c

388

uint32_t);

sys/dev/fdt/if_mvpp.c

389

void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *, uint32_t);

sys/dev/fdt/if_mvpp.c

390

void mvpp2_prs_shadow_set(struct mvpp2_softc *, int, uint32_t);

sys/dev/fdt/if_mvpp.c

3913

mvpp2_prs_dsa_tag_ethertype_set(struct mvpp2_softc *sc, uint32_t port,

sys/dev/fdt/if_mvpp.c

395

void mvpp2_prs_mac_drop_all_set(struct mvpp2_softc *, uint32_t, int);

sys/dev/fdt/if_mvpp.c

396

void mvpp2_prs_mac_promisc_set(struct mvpp2_softc *, uint32_t, int, int);

sys/dev/fdt/if_mvpp.c

3965

uint32_t ri_bits, ai_bits;

sys/dev/fdt/if_mvpp.c

397

void mvpp2_prs_dsa_tag_set(struct mvpp2_softc *, uint32_t, int, int, int);

sys/dev/fdt/if_mvpp.c

398

void mvpp2_prs_dsa_tag_ethertype_set(struct mvpp2_softc *, uint32_t,

sys/dev/fdt/if_mvpp.c

3998

mvpp2_prs_vlan_add(struct mvpp2_softc *sc, uint16_t tpid, int ai, uint32_t port_map)

sys/dev/fdt/if_mvpp.c

4001

uint32_t ri_bits;

sys/dev/fdt/if_mvpp.c

402

int mvpp2_prs_vlan_add(struct mvpp2_softc *, uint16_t, int, uint32_t);

sys/dev/fdt/if_mvpp.c

407

uint32_t);

sys/dev/fdt/if_mvpp.c

4078

uint32_t ri_mask;

sys/dev/fdt/if_mvpp.c

408

int mvpp2_prs_ip4_proto(struct mvpp2_softc *, uint16_t, uint32_t, uint32_t);

sys/dev/fdt/if_mvpp.c

410

int mvpp2_prs_ip6_proto(struct mvpp2_softc *, uint16_t, uint32_t, uint32_t);

sys/dev/fdt/if_mvpp.c

4108

uint32_t port_map)

sys/dev/fdt/if_mvpp.c

4112

uint32_t ri_bits;

sys/dev/fdt/if_mvpp.c

4174

mvpp2_prs_ip4_proto(struct mvpp2_softc *sc, uint16_t proto, uint32_t ri,

sys/dev/fdt/if_mvpp.c

4175

uint32_t ri_mask)

sys/dev/fdt/if_mvpp.c

4273

mvpp2_prs_ip6_proto(struct mvpp2_softc *sc, uint16_t proto, uint32_t ri,

sys/dev/fdt/if_mvpp.c

4274

uint32_t ri_mask)

sys/dev/fdt/if_mvpp.c

4367

uint32_t entry_pmap;

sys/dev/fdt/if_mvpp.c

4389

uint32_t pmap, len, ri;

sys/dev/fdt/if_mvpp.c

4457

uint32_t pmap;

sys/dev/fdt/if_mvpp.c

4572

uint32_t val;

sys/dev/fdt/if_mvpp.c

4606

uint32_t val;

sys/dev/fdt/if_mvpp.c

4635

uint32_t val;

sys/dev/fdt/if_mvpp.c

529

uint32_t reg;

sys/dev/fdt/if_mvpp.c

769

uint32_t reg;

sys/dev/fdt/if_mvppreg.h

1205

uint32_t command; /* Options used by HW for packet transmitting.*/

sys/dev/fdt/if_mvppreg.h

1215

uint32_t status; /* info about received packet */

sys/dev/fdt/if_mvppreg.h

1220

uint32_t rsrvd_timestamp;

sys/dev/fdt/if_mvppreg.h

1226

uint32_t word[MVPP2_PRS_TCAM_WORDS];

sys/dev/fdt/if_mvppreg.h

1231

uint32_t word[MVPP2_PRS_SRAM_WORDS];

sys/dev/fdt/if_mvppreg.h

1236

uint32_t index;

sys/dev/fdt/if_mvppreg.h

1252

uint32_t ri;

sys/dev/fdt/if_mvppreg.h

1253

uint32_t ri_mask;

sys/dev/fdt/if_mvppreg.h

1257

uint32_t index;

sys/dev/fdt/if_mvppreg.h

1258

uint32_t data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];

sys/dev/fdt/if_mvppreg.h

1262

uint32_t lkpid;

sys/dev/fdt/if_mvppreg.h

1263

uint32_t way;

sys/dev/fdt/if_mvppreg.h

1264

uint32_t data;

sys/dev/fdt/if_mvppreg.h

1268

uint32_t NextBuffPhysAddr;

sys/dev/fdt/if_mvppreg.h

1269

uint32_t NextBuffVirtAddr;

sys/dev/fdt/iicmux.c

136

uint32_t channel;

sys/dev/fdt/iicmux.c

249

uint32_t reg[1];

sys/dev/fdt/iicmux.c

89

uint32_t phandle;

sys/dev/fdt/imxanatop.c

111

uint32_t ir_reg_offset;

sys/dev/fdt/imxanatop.c

112

uint32_t ir_vol_bit_shift;

sys/dev/fdt/imxanatop.c

113

uint32_t ir_vol_bit_width;

sys/dev/fdt/imxanatop.c

114

uint32_t ir_min_bit_val;

sys/dev/fdt/imxanatop.c

115

uint32_t ir_min_voltage;

sys/dev/fdt/imxanatop.c

116

uint32_t ir_max_voltage;

sys/dev/fdt/imxanatop.c

118

uint32_t ir_delay_reg_offset;

sys/dev/fdt/imxanatop.c

119

uint32_t ir_delay_bit_shift;

sys/dev/fdt/imxanatop.c

120

uint32_t ir_delay_bit_width;

sys/dev/fdt/imxanatop.c

137

uint32_t imxanatop_get_voltage(void *);

sys/dev/fdt/imxanatop.c

138

int imxanatop_set_voltage(void *, uint32_t);

sys/dev/fdt/imxanatop.c

218

uint32_t

sys/dev/fdt/imxanatop.c

222

uint32_t bit_val;

sys/dev/fdt/imxanatop.c

230

imxanatop_set_voltage(void *cookie, uint32_t voltage)

sys/dev/fdt/imxanatop.c

233

uint32_t bit_val, old_bit_val, reg;

sys/dev/fdt/imxanatop.c

259

uint32_t

sys/dev/fdt/imxanatop.c

260

imxanatop_decode_pll(enum imxanatop_clocks pll, uint32_t freq)

sys/dev/fdt/imxanatop.c

263

uint32_t div;

sys/dev/fdt/imxanatop.c

288

uint32_t

sys/dev/fdt/imxanatop.c

298

uint32_t

sys/dev/fdt/imxanatopvar.h

44

uint32_t imxanatop_decode_pll(enum imxanatop_clocks, uint32_t);

sys/dev/fdt/imxanatopvar.h

45

uint32_t imxanatop_get_pll2_pfd(unsigned int);

sys/dev/fdt/imxanatopvar.h

46

uint32_t imxanatop_get_pll3_pfd(unsigned int);

sys/dev/fdt/imxccm.c

1003

uint32_t

sys/dev/fdt/imxccm.c

1004

imxccm_imx8mq_ahb(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

1006

uint32_t mux;

sys/dev/fdt/imxccm.c

1032

uint32_t

sys/dev/fdt/imxccm.c

1033

imxccm_imx8mq_i2c(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

1035

uint32_t mux;

sys/dev/fdt/imxccm.c

1053

uint32_t

sys/dev/fdt/imxccm.c

1054

imxccm_imx8mq_pwm(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

1056

uint32_t mux;

sys/dev/fdt/imxccm.c

1080

uint32_t

sys/dev/fdt/imxccm.c

1081

imxccm_imx8mq_uart(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

1083

uint32_t mux;

sys/dev/fdt/imxccm.c

1101

uint32_t

sys/dev/fdt/imxccm.c

1102

imxccm_imx8mq_usdhc(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

1104

uint32_t mux;

sys/dev/fdt/imxccm.c

1124

uint32_t

sys/dev/fdt/imxccm.c

1125

imxccm_imx8mq_usb(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

1127

uint32_t mux;

sys/dev/fdt/imxccm.c

1153

uint32_t

sys/dev/fdt/imxccm.c

1154

imxccm_imx8mq_get_pll(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

1156

uint32_t divr_val, divq_val, divf_val;

sys/dev/fdt/imxccm.c

1157

uint32_t divff, divfi;

sys/dev/fdt/imxccm.c

1158

uint32_t pllout_div;

sys/dev/fdt/imxccm.c

1159

uint32_t pll0, pll1;

sys/dev/fdt/imxccm.c

1160

uint32_t freq;

sys/dev/fdt/imxccm.c

1161

uint32_t mux;

sys/dev/fdt/imxccm.c

1214

imxccm_imx8mq_set_pll(struct imxccm_softc *sc, uint32_t idx, uint64_t freq)

sys/dev/fdt/imxccm.c

1217

uint32_t pllout_div;

sys/dev/fdt/imxccm.c

1218

uint32_t pll0, pll1;

sys/dev/fdt/imxccm.c

1219

uint32_t mux, reg;

sys/dev/fdt/imxccm.c

1304

imxccm_imx8m_set_div(struct imxccm_softc *sc, uint32_t idx, uint64_t freq,

sys/dev/fdt/imxccm.c

1308

uint32_t reg;

sys/dev/fdt/imxccm.c

1332

imxccm_enable_parent(struct imxccm_softc *sc, uint32_t parent, int on)

sys/dev/fdt/imxccm.c

1339

imxccm_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/imxccm.c

1342

uint32_t idx = cells[0], parent;

sys/dev/fdt/imxccm.c

1343

uint32_t pcells[2];

sys/dev/fdt/imxccm.c

1492

uint32_t

sys/dev/fdt/imxccm.c

1493

imxccm_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/imxccm.c

1496

uint32_t idx = cells[0];

sys/dev/fdt/imxccm.c

1497

uint32_t div, pre, reg, parent;

sys/dev/fdt/imxccm.c

1498

uint32_t freq;

sys/dev/fdt/imxccm.c

1746

imxccm_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/imxccm.c

1749

uint32_t idx = cells[0];

sys/dev/fdt/imxccm.c

1750

uint32_t reg, div, parent, parent_freq;

sys/dev/fdt/imxccm.c

1751

uint32_t pcells[2];

sys/dev/fdt/imxccm.c

1848

imxccm_set_parent(void *cookie, uint32_t *cells, uint32_t *pcells)

sys/dev/fdt/imxccm.c

1851

uint32_t idx = cells[0];

sys/dev/fdt/imxccm.c

1852

uint32_t pidx;

sys/dev/fdt/imxccm.c

1853

uint32_t mux;

sys/dev/fdt/imxccm.c

212

uint32_t sc_phandle;

sys/dev/fdt/imxccm.c

238

uint32_t imxccm_get_armclk(struct imxccm_softc *);

sys/dev/fdt/imxccm.c

240

uint32_t imxccm_get_usdhx(struct imxccm_softc *, int x);

sys/dev/fdt/imxccm.c

241

uint32_t imxccm_get_periphclk(struct imxccm_softc *);

sys/dev/fdt/imxccm.c

242

uint32_t imxccm_get_ahbclk(struct imxccm_softc *);

sys/dev/fdt/imxccm.c

243

uint32_t imxccm_get_ipgclk(struct imxccm_softc *);

sys/dev/fdt/imxccm.c

244

uint32_t imxccm_get_ipg_perclk(struct imxccm_softc *);

sys/dev/fdt/imxccm.c

245

uint32_t imxccm_get_uartclk(struct imxccm_softc *);

sys/dev/fdt/imxccm.c

246

uint32_t imxccm_imx8mm_enet(struct imxccm_softc *sc, uint32_t);

sys/dev/fdt/imxccm.c

247

uint32_t imxccm_imx8mm_ahb(struct imxccm_softc *sc, uint32_t);

sys/dev/fdt/imxccm.c

248

uint32_t imxccm_imx8mm_i2c(struct imxccm_softc *sc, uint32_t);

sys/dev/fdt/imxccm.c

249

uint32_t imxccm_imx8mm_uart(struct imxccm_softc *sc, uint32_t);

sys/dev/fdt/imxccm.c

250

uint32_t imxccm_imx8mm_usdhc(struct imxccm_softc *sc, uint32_t);

sys/dev/fdt/imxccm.c

251

uint32_t imxccm_imx8mp_enet_qos_timer(struct imxccm_softc *sc, uint32_t);

sys/dev/fdt/imxccm.c

252

uint32_t imxccm_imx8mp_enet_qos(struct imxccm_softc *sc, uint32_t);

sys/dev/fdt/imxccm.c

253

uint32_t imxccm_imx8mp_hsio_axi(struct imxccm_softc *sc, uint32_t);

sys/dev/fdt/imxccm.c

254

uint32_t imxccm_imx8mq_ecspi(struct imxccm_softc *sc, uint32_t);

sys/dev/fdt/imxccm.c

255

uint32_t imxccm_imx8mq_enet(struct imxccm_softc *sc, uint32_t);

sys/dev/fdt/imxccm.c

256

uint32_t imxccm_imx8mq_ahb(struct imxccm_softc *sc, uint32_t);

sys/dev/fdt/imxccm.c

257

uint32_t imxccm_imx8mq_i2c(struct imxccm_softc *sc, uint32_t);

sys/dev/fdt/imxccm.c

258

uint32_t imxccm_imx8mq_pwm(struct imxccm_softc *sc, uint32_t);

sys/dev/fdt/imxccm.c

259

uint32_t imxccm_imx8mq_uart(struct imxccm_softc *sc, uint32_t);

sys/dev/fdt/imxccm.c

260

uint32_t imxccm_imx8mq_usdhc(struct imxccm_softc *sc, uint32_t);

sys/dev/fdt/imxccm.c

261

uint32_t imxccm_imx8mq_usb(struct imxccm_softc *sc, uint32_t);

sys/dev/fdt/imxccm.c

262

int imxccm_imx8m_set_div(struct imxccm_softc *, uint32_t, uint64_t, uint64_t);

sys/dev/fdt/imxccm.c

263

void imxccm_enable(void *, uint32_t *, int);

sys/dev/fdt/imxccm.c

264

uint32_t imxccm_get_frequency(void *, uint32_t *);

sys/dev/fdt/imxccm.c

265

int imxccm_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/imxccm.c

266

int imxccm_set_parent(void *, uint32_t *, uint32_t *);

sys/dev/fdt/imxccm.c

358

uint32_t

sys/dev/fdt/imxccm.c

361

uint32_t ccsr = HREAD4(sc, CCM_CCSR);

sys/dev/fdt/imxccm.c

399

uint32_t

sys/dev/fdt/imxccm.c

402

uint32_t clkroot = PLL3_60M;

sys/dev/fdt/imxccm.c

403

uint32_t podf = HREAD4(sc, CCM_CSCDR2);

sys/dev/fdt/imxccm.c

414

uint32_t cscmr1 = HREAD4(sc, CCM_CSCMR1);

sys/dev/fdt/imxccm.c

415

uint32_t cscdr1 = HREAD4(sc, CCM_CSCDR1);

sys/dev/fdt/imxccm.c

416

uint32_t podf, clkroot;

sys/dev/fdt/imxccm.c

432

uint32_t

sys/dev/fdt/imxccm.c

435

uint32_t clkroot = PLL3_80M;

sys/dev/fdt/imxccm.c

436

uint32_t podf = HREAD4(sc, CCM_CSCDR1) & CCM_CSCDR1_UART_PODF_MASK;

sys/dev/fdt/imxccm.c

441

uint32_t

sys/dev/fdt/imxccm.c

473

uint32_t

sys/dev/fdt/imxccm.c

476

uint32_t ahb_podf;

sys/dev/fdt/imxccm.c

483

uint32_t

sys/dev/fdt/imxccm.c

486

uint32_t ipg_podf;

sys/dev/fdt/imxccm.c

493

uint32_t

sys/dev/fdt/imxccm.c

496

uint32_t cscmr1 = HREAD4(sc, CCM_CSCMR1);

sys/dev/fdt/imxccm.c

497

uint32_t freq, ipg_podf;

sys/dev/fdt/imxccm.c

561

uint32_t

sys/dev/fdt/imxccm.c

562

imxccm_imx7d_enet(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

564

uint32_t mux;

sys/dev/fdt/imxccm.c

584

uint32_t

sys/dev/fdt/imxccm.c

585

imxccm_imx7d_i2c(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

587

uint32_t mux;

sys/dev/fdt/imxccm.c

607

uint32_t

sys/dev/fdt/imxccm.c

608

imxccm_imx7d_uart(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

610

uint32_t mux;

sys/dev/fdt/imxccm.c

628

uint32_t

sys/dev/fdt/imxccm.c

629

imxccm_imx7d_usdhc(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

631

uint32_t mux;

sys/dev/fdt/imxccm.c

651

uint32_t

sys/dev/fdt/imxccm.c

652

imxccm_imx8mm_get_pll(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

655

uint32_t pll0, pll1;

sys/dev/fdt/imxccm.c

688

imxccm_imx8mm_set_pll(struct imxccm_softc *sc, uint32_t idx, uint64_t freq)

sys/dev/fdt/imxccm.c

691

uint32_t pll0, pll1, reg;

sys/dev/fdt/imxccm.c

771

uint32_t

sys/dev/fdt/imxccm.c

772

imxccm_imx8mm_enet(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

774

uint32_t mux;

sys/dev/fdt/imxccm.c

794

uint32_t

sys/dev/fdt/imxccm.c

795

imxccm_imx8mm_ahb(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

797

uint32_t mux;

sys/dev/fdt/imxccm.c

823

uint32_t

sys/dev/fdt/imxccm.c

824

imxccm_imx8mm_i2c(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

826

uint32_t mux;

sys/dev/fdt/imxccm.c

844

uint32_t

sys/dev/fdt/imxccm.c

845

imxccm_imx8mm_uart(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

847

uint32_t mux;

sys/dev/fdt/imxccm.c

865

uint32_t

sys/dev/fdt/imxccm.c

866

imxccm_imx8mm_usdhc(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

868

uint32_t mux;

sys/dev/fdt/imxccm.c

888

uint32_t

sys/dev/fdt/imxccm.c

889

imxccm_imx8mp_enet_qos(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

891

uint32_t mux;

sys/dev/fdt/imxccm.c

911

uint32_t

sys/dev/fdt/imxccm.c

912

imxccm_imx8mp_enet_qos_timer(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

914

uint32_t mux;

sys/dev/fdt/imxccm.c

934

uint32_t

sys/dev/fdt/imxccm.c

935

imxccm_imx8mp_hsio_axi(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

937

uint32_t mux;

sys/dev/fdt/imxccm.c

957

uint32_t

sys/dev/fdt/imxccm.c

958

imxccm_imx8mq_ecspi(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

960

uint32_t mux;

sys/dev/fdt/imxccm.c

980

uint32_t

sys/dev/fdt/imxccm.c

981

imxccm_imx8mq_enet(struct imxccm_softc *sc, uint32_t idx)

sys/dev/fdt/imxccm.c

983

uint32_t mux;

sys/dev/fdt/imxehci.c

106

void imxehci_init_phy(struct imxehci_softc *, uint32_t *);

sys/dev/fdt/imxehci.c

124

uint32_t phy[1], misc[2];

sys/dev/fdt/imxehci.c

125

uint32_t misc_reg[2];

sys/dev/fdt/imxehci.c

126

uint32_t off, reg;

sys/dev/fdt/imxehci.c

127

uint32_t vbus;

sys/dev/fdt/imxehci.c

220

uint32_t val = EOREAD4(&sc->sc, EHCI_USBCMD);

sys/dev/fdt/imxehci.c

305

void (*init)(struct imxehci_softc *, uint32_t *);

sys/dev/fdt/imxehci.c

308

void imx23_usb_init(struct imxehci_softc *, uint32_t *);

sys/dev/fdt/imxehci.c

309

static void nop_xceiv_init(struct imxehci_softc *, uint32_t *);

sys/dev/fdt/imxehci.c

317

imxehci_init_phy(struct imxehci_softc *sc, uint32_t *cells)

sys/dev/fdt/imxehci.c

339

imx23_usb_init(struct imxehci_softc *sc, uint32_t *cells)

sys/dev/fdt/imxehci.c

342

uint32_t phy_reg[2];

sys/dev/fdt/imxehci.c

343

uint32_t anatop[1];

sys/dev/fdt/imxehci.c

407

nop_xceiv_init(struct imxehci_softc *sc, uint32_t *cells)

sys/dev/fdt/imxehci.c

94

uint32_t sc_unit;

sys/dev/fdt/imxesdhc.c

1077

*(uint32_t *)datap = HREAD4(sc, SDHC_DATA_BUFF_ACC_PORT);

sys/dev/fdt/imxesdhc.c

1082

uint32_t rv = HREAD4(sc, SDHC_DATA_BUFF_ACC_PORT);

sys/dev/fdt/imxesdhc.c

1094

DPRINTF(3,("%08x\n", *(uint32_t *)datap));

sys/dev/fdt/imxesdhc.c

1095

HWRITE4(sc, SDHC_DATA_BUFF_ACC_PORT, *((uint32_t *)datap));

sys/dev/fdt/imxesdhc.c

1100

uint32_t rv = *datap++;

sys/dev/fdt/imxesdhc.c

167

uint32_t address;

sys/dev/fdt/imxesdhc.c

181

uint32_t sc_gpio[3];

sys/dev/fdt/imxesdhc.c

182

uint32_t sc_vmmc;

sys/dev/fdt/imxesdhc.c

183

uint32_t sc_pwrseq;

sys/dev/fdt/imxesdhc.c

184

uint32_t sc_vdd;

sys/dev/fdt/imxesdhc.c

193

uint32_t ocr; /* OCR value from caps */

sys/dev/fdt/imxesdhc.c

194

uint32_t intr_status; /* soft interrupt status */

sys/dev/fdt/imxesdhc.c

195

uint32_t intr_error_status;

sys/dev/fdt/imxesdhc.c

205

void imxesdhc_clock_enable(uint32_t);

sys/dev/fdt/imxesdhc.c

206

void imxesdhc_pwrseq_pre(uint32_t);

sys/dev/fdt/imxesdhc.c

207

void imxesdhc_pwrseq_post(uint32_t);

sys/dev/fdt/imxesdhc.c

230

uint32_t imxesdhc_host_ocr(sdmmc_chipset_handle_t);

sys/dev/fdt/imxesdhc.c

233

int imxesdhc_bus_power(sdmmc_chipset_handle_t, uint32_t);

sys/dev/fdt/imxesdhc.c

240

int imxesdhc_wait_state(struct imxesdhc_softc *, uint32_t, uint32_t);

sys/dev/fdt/imxesdhc.c

300

uint32_t caps;

sys/dev/fdt/imxesdhc.c

301

uint32_t width;

sys/dev/fdt/imxesdhc.c

469

imxesdhc_clock_enable(uint32_t phandle)

sys/dev/fdt/imxesdhc.c

471

uint32_t gpios[3];

sys/dev/fdt/imxesdhc.c

489

imxesdhc_pwrseq_pre(uint32_t phandle)

sys/dev/fdt/imxesdhc.c

491

uint32_t *gpios, *gpio;

sys/dev/fdt/imxesdhc.c

492

uint32_t clocks;

sys/dev/fdt/imxesdhc.c

517

while (gpio && gpio < gpios + (len / sizeof(uint32_t))) {

sys/dev/fdt/imxesdhc.c

527

imxesdhc_pwrseq_post(uint32_t phandle)

sys/dev/fdt/imxesdhc.c

529

uint32_t *gpios, *gpio;

sys/dev/fdt/imxesdhc.c

548

while (gpio && gpio < gpios + (len / sizeof(uint32_t))) {

sys/dev/fdt/imxesdhc.c

616

uint32_t

sys/dev/fdt/imxesdhc.c

651

imxesdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)

sys/dev/fdt/imxesdhc.c

654

uint32_t vdd = 0;

sys/dev/fdt/imxesdhc.c

737

uint32_t reg;

sys/dev/fdt/imxesdhc.c

780

imxesdhc_wait_state(struct imxesdhc_softc *sc, uint32_t mask, uint32_t value)

sys/dev/fdt/imxesdhc.c

782

uint32_t state;

sys/dev/fdt/imxgpc.c

105

imxgpc_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/imxgpc.c

44

void imxgpc_enable(void *, uint32_t *, int);

sys/dev/fdt/imxgpio.c

150

imxgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/imxgpio.c

153

uint32_t pin = cells[0];

sys/dev/fdt/imxgpio.c

154

uint32_t val;

sys/dev/fdt/imxgpio.c

168

imxgpio_get_pin(void *cookie, uint32_t *cells)

sys/dev/fdt/imxgpio.c

171

uint32_t pin = cells[0];

sys/dev/fdt/imxgpio.c

172

uint32_t flags = cells[1];

sys/dev/fdt/imxgpio.c

173

uint32_t reg;

sys/dev/fdt/imxgpio.c

185

imxgpio_set_pin(void *cookie, uint32_t *cells, int val)

sys/dev/fdt/imxgpio.c

188

uint32_t pin = cells[0];

sys/dev/fdt/imxgpio.c

189

uint32_t flags = cells[1];

sys/dev/fdt/imxgpio.c

190

uint32_t reg;

sys/dev/fdt/imxgpio.c

207

uint32_t status, pending, mask;

sys/dev/fdt/imxgpio.c

320

uint32_t mask;

sys/dev/fdt/imxgpio.c

390

uint32_t mask;

sys/dev/fdt/imxgpio.c

405

uint32_t mask;

sys/dev/fdt/imxgpio.c

76

void imxgpio_config_pin(void *, uint32_t *, int);

sys/dev/fdt/imxgpio.c

77

int imxgpio_get_pin(void *, uint32_t *);

sys/dev/fdt/imxgpio.c

78

void imxgpio_set_pin(void *, uint32_t *, int);

sys/dev/fdt/imxiic_fdt.c

124

uint32_t reg[1];

sys/dev/fdt/imxiomuxc.c

102

uint32_t *pins;

sys/dev/fdt/imxiomuxc.c

121

npins = len / (6 * sizeof(uint32_t));

sys/dev/fdt/imxiomuxc.c

124

uint32_t mux_reg = pins[6 * i + 0];

sys/dev/fdt/imxiomuxc.c

125

uint32_t conf_reg = pins[6 * i + 1];

sys/dev/fdt/imxiomuxc.c

126

uint32_t input_reg = pins[6 * i + 2];

sys/dev/fdt/imxiomuxc.c

127

uint32_t mux_val = pins[6 * i + 3];

sys/dev/fdt/imxiomuxc.c

128

uint32_t conf_val = pins[6 * i + 5];

sys/dev/fdt/imxiomuxc.c

129

uint32_t input_val = pins[6 * i + 4];

sys/dev/fdt/imxiomuxc.c

130

uint32_t val;

sys/dev/fdt/imxiomuxc.c

150

uint32_t clr = ((1 << width) - 1) << shift;

sys/dev/fdt/imxiomuxc.c

151

uint32_t set = (input_val & 0xff) << shift;

sys/dev/fdt/imxiomuxc.c

60

int imxiomuxc_pinctrl(uint32_t, void *);

sys/dev/fdt/imxiomuxc.c

98

imxiomuxc_pinctrl(uint32_t phandle, void *cookie)

sys/dev/fdt/imxpwm.c

132

imxpwm_get_state(void *cookie, uint32_t *cells, struct pwm_state *ps)

sys/dev/fdt/imxpwm.c

167

imxpwm_set_state(void *cookie, uint32_t *cells, struct pwm_state *ps)

sys/dev/fdt/imxpwm.c

67

uint32_t sc_dcycles;

sys/dev/fdt/imxpwm.c

68

uint32_t sc_clkin;

sys/dev/fdt/imxpwm.c

83

int imxpwm_get_state(void *, uint32_t *, struct pwm_state *);

sys/dev/fdt/imxpwm.c

84

int imxpwm_set_state(void *, uint32_t *, struct pwm_state *);

sys/dev/fdt/imxrtc.c

101

uint32_t cr;

sys/dev/fdt/imxrtc.c

140

uint32_t cr;

sys/dev/fdt/imxrtc.c

78

uint32_t regmap;

sys/dev/fdt/imxspi.c

111

uint32_t imxspi_clkdiv(struct imxspi_softc *, uint32_t);

sys/dev/fdt/imxspi.c

117

int imxspi_wait_state(struct imxspi_softc *, uint32_t, uint32_t);

sys/dev/fdt/imxspi.c

174

uint32_t *gpio;

sys/dev/fdt/imxspi.c

229

uint32_t conreg, configreg;

sys/dev/fdt/imxspi.c

268

uint32_t

sys/dev/fdt/imxspi.c

269

imxspi_clkdiv(struct imxspi_softc *sc, uint32_t freq)

sys/dev/fdt/imxspi.c

271

uint32_t pre, post;

sys/dev/fdt/imxspi.c

272

uint32_t pfreq;

sys/dev/fdt/imxspi.c

292

imxspi_wait_state(struct imxspi_softc *sc, uint32_t mask, uint32_t value)

sys/dev/fdt/imxspi.c

294

uint32_t state;

sys/dev/fdt/imxspi.c

309

uint32_t *gpio;

sys/dev/fdt/imxspi.c

329

uint32_t *gpio;

sys/dev/fdt/imxspi.c

411

uint32_t reg[1];

sys/dev/fdt/imxspi.c

93

uint32_t *sc_gpio;

sys/dev/fdt/imxsrc.c

112

void imxsrc_reset(void *, uint32_t *, int);

sys/dev/fdt/imxsrc.c

164

imxsrc_reset(void *cookie, uint32_t *cells, int assert)

sys/dev/fdt/imxsrc.c

168

uint32_t reg;

sys/dev/fdt/imxsrc.c

61

uint32_t reg;

sys/dev/fdt/imxsrc.c

62

uint32_t bit;

sys/dev/fdt/imxtmu.c

102

uint32_t range[4], *calibration;

sys/dev/fdt/imxtmu.c

177

uint32_t value;

sys/dev/fdt/imxtmu.c

192

uint32_t value;

sys/dev/fdt/mtintc.c

103

sc->sc_irq_cfg, sc->sc_ios / sizeof(uint32_t));

sys/dev/fdt/mtintc.c

107

sc->sc_irq_cfg, sc->sc_ios / sizeof(uint32_t));

sys/dev/fdt/mtintc.c

37

uint32_t *sc_irq_cfg;

sys/dev/fdt/mtrng.c

97

uint32_t sta;

sys/dev/fdt/mtxhci.c

185

uint32_t mask, val;

sys/dev/fdt/mvclock.c

131

uint32_t

sys/dev/fdt/mvclock.c

132

ap806_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/mvclock.c

134

uint32_t idx = cells[0];

sys/dev/fdt/mvclock.c

168

uint32_t

sys/dev/fdt/mvclock.c

169

cp110_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/mvclock.c

172

uint32_t mod = cells[0];

sys/dev/fdt/mvclock.c

173

uint32_t idx = cells[1];

sys/dev/fdt/mvclock.c

174

uint32_t parent[2] = { 0, 0 };

sys/dev/fdt/mvclock.c

224

cp110_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/mvclock.c

227

uint32_t mod = cells[0];

sys/dev/fdt/mvclock.c

228

uint32_t idx = cells[1];

sys/dev/fdt/mvclock.c

233

uint32_t reg;

sys/dev/fdt/mvclock.c

298

void a3700_periph_enable(struct mvclock_softc *, uint32_t, int);

sys/dev/fdt/mvclock.c

299

uint32_t a3700_periph_tbg_get_frequency(struct mvclock_softc *, uint32_t);

sys/dev/fdt/mvclock.c

300

uint32_t a3700_periph_get_div(struct mvclock_softc *, uint32_t, uint32_t);

sys/dev/fdt/mvclock.c

301

uint32_t a3700_periph_get_double_div(struct mvclock_softc *, uint32_t,

sys/dev/fdt/mvclock.c

302

uint32_t, uint32_t);

sys/dev/fdt/mvclock.c

305

a3700_periph_nb_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/mvclock.c

308

uint32_t idx = cells[0];

sys/dev/fdt/mvclock.c

326

uint32_t

sys/dev/fdt/mvclock.c

327

a3700_periph_nb_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/mvclock.c

330

uint32_t idx = cells[0];

sys/dev/fdt/mvclock.c

331

uint32_t freq;

sys/dev/fdt/mvclock.c

357

a3700_periph_sb_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/mvclock.c

360

uint32_t idx = cells[0];

sys/dev/fdt/mvclock.c

378

uint32_t

sys/dev/fdt/mvclock.c

379

a3700_periph_sb_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/mvclock.c

382

uint32_t idx = cells[0];

sys/dev/fdt/mvclock.c

383

uint32_t freq;

sys/dev/fdt/mvclock.c

410

a3700_periph_enable(struct mvclock_softc *sc, uint32_t idx, int on)

sys/dev/fdt/mvclock.c

412

uint32_t reg;

sys/dev/fdt/mvclock.c

421

uint32_t

sys/dev/fdt/mvclock.c

422

a3700_periph_tbg_get_frequency(struct mvclock_softc *sc, uint32_t idx)

sys/dev/fdt/mvclock.c

424

uint32_t reg;

sys/dev/fdt/mvclock.c

433

uint32_t

sys/dev/fdt/mvclock.c

434

a3700_periph_get_div(struct mvclock_softc *sc, uint32_t off, uint32_t idx)

sys/dev/fdt/mvclock.c

436

uint32_t reg = HREAD4(sc, off);

sys/dev/fdt/mvclock.c

440

uint32_t

sys/dev/fdt/mvclock.c

441

a3700_periph_get_double_div(struct mvclock_softc *sc, uint32_t off,

sys/dev/fdt/mvclock.c

442

uint32_t idx0, uint32_t idx1)

sys/dev/fdt/mvclock.c

444

uint32_t reg = HREAD4(sc, off);

sys/dev/fdt/mvclock.c

470

uint32_t

sys/dev/fdt/mvclock.c

471

a3700_tbg_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/mvclock.c

474

uint32_t idx = cells[0];

sys/dev/fdt/mvclock.c

476

uint32_t reg, vcodiv;

sys/dev/fdt/mvclock.c

59

uint32_t ap806_get_frequency(void *, uint32_t *);

sys/dev/fdt/mvclock.c

60

uint32_t cp110_get_frequency(void *, uint32_t *);

sys/dev/fdt/mvclock.c

61

void cp110_enable(void *, uint32_t *, int);

sys/dev/fdt/mvclock.c

63

void a3700_periph_nb_enable(void *, uint32_t *, int);

sys/dev/fdt/mvclock.c

64

uint32_t a3700_periph_nb_get_frequency(void *, uint32_t *);

sys/dev/fdt/mvclock.c

65

void a3700_periph_sb_enable(void *, uint32_t *, int);

sys/dev/fdt/mvclock.c

66

uint32_t a3700_periph_sb_get_frequency(void *, uint32_t *);

sys/dev/fdt/mvclock.c

67

uint32_t a3700_tbg_get_frequency(void *, uint32_t *);

sys/dev/fdt/mvgicp.c

129

uint32_t interrupt[3];

sys/dev/fdt/mvgicp.c

130

uint32_t flags;

sys/dev/fdt/mvgicp.c

39

uint32_t sc_spi_ranges[4];

sys/dev/fdt/mvgicp.c

41

uint32_t sc_nspi;

sys/dev/fdt/mvgpio.c

101

mvgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/mvgpio.c

104

uint32_t pin = cells[0];

sys/dev/fdt/mvgpio.c

116

mvgpio_get_pin(void *cookie, uint32_t *cells)

sys/dev/fdt/mvgpio.c

119

uint32_t pin = cells[0];

sys/dev/fdt/mvgpio.c

120

uint32_t flags = cells[1];

sys/dev/fdt/mvgpio.c

121

uint32_t reg;

sys/dev/fdt/mvgpio.c

137

mvgpio_set_pin(void *cookie, uint32_t *cells, int val)

sys/dev/fdt/mvgpio.c

140

uint32_t pin = cells[0];

sys/dev/fdt/mvgpio.c

141

uint32_t flags = cells[1];

sys/dev/fdt/mvgpio.c

65

void mvgpio_config_pin(void *, uint32_t *, int);

sys/dev/fdt/mvgpio.c

66

int mvgpio_get_pin(void *, uint32_t *);

sys/dev/fdt/mvgpio.c

67

void mvgpio_set_pin(void *, uint32_t *, int);

sys/dev/fdt/mvicu.c

152

uint32_t phandle = 0;

sys/dev/fdt/mvicu.c

153

uint32_t group;

sys/dev/fdt/mvicu.c

204

uint32_t idx, flags;

sys/dev/fdt/mviic.c

177

mviic_wait_state(struct mviic_softc *sc, uint32_t mask, uint32_t value)

sys/dev/fdt/mviic.c

179

uint32_t state;

sys/dev/fdt/mviic.c

318

uint32_t reg[1];

sys/dev/fdt/mviic.c

72

int mviic_wait_state(struct mviic_softc *, uint32_t, uint32_t);

sys/dev/fdt/mvkpcie.c

159

uint32_t flags;

sys/dev/fdt/mvkpcie.c

192

uint32_t sc_bridge_command;

sys/dev/fdt/mvkpcie.c

193

uint32_t sc_bridge_businfo;

sys/dev/fdt/mvkpcie.c

194

uint32_t sc_bridge_iostatus;

sys/dev/fdt/mvkpcie.c

195

uint32_t sc_bridge_io_hi;

sys/dev/fdt/mvkpcie.c

196

uint32_t sc_bridge_mem;

sys/dev/fdt/mvkpcie.c

269

uint32_t *reset_gpio;

sys/dev/fdt/mvkpcie.c

273

uint32_t bus_range[2];

sys/dev/fdt/mvkpcie.c

274

uint32_t *ranges;

sys/dev/fdt/mvkpcie.c

277

uint32_t reg;

sys/dev/fdt/mvkpcie.c

298

if (rangeslen <= 0 || (rangeslen % sizeof(uint32_t)) ||

sys/dev/fdt/mvkpcie.c

299

(rangeslen / sizeof(uint32_t)) % (sc->sc_acells +

sys/dev/fdt/mvkpcie.c

316

nranges = (rangeslen / sizeof(uint32_t)) /

sys/dev/fdt/mvkpcie.c

569

uint32_t reg;

sys/dev/fdt/mvkpcie.c

660

uint32_t reg;

sys/dev/fdt/mvkpcie.c

702

uint32_t reg;

sys/dev/fdt/mvkpcie.c

805

uint32_t reg[4];

sys/dev/fdt/mvkpcie.c

875

uint32_t pending;

sys/dev/fdt/mvmdio.c

123

uint32_t smi, val;

sys/dev/fdt/mvmdio.c

161

uint32_t smi;

sys/dev/fdt/mvpinctrl.c

225

mvpinctrl_pinctrl(uint32_t phandle, void *cookie)

sys/dev/fdt/mvpinctrl.c

251

uint32_t off, shift;

sys/dev/fdt/mvpinctrl.c

258

off = (sc->sc_pins[i].pid / 8) * sizeof(uint32_t);

sys/dev/fdt/mvpinctrl.c

280

mvpinctrl_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/mvpinctrl.c

283

uint32_t pin = cells[0];

sys/dev/fdt/mvpinctrl.c

295

mvpinctrl_get_pin(void *cookie, uint32_t *cells)

sys/dev/fdt/mvpinctrl.c

298

uint32_t pin = cells[0];

sys/dev/fdt/mvpinctrl.c

299

uint32_t flags = cells[1];

sys/dev/fdt/mvpinctrl.c

300

uint32_t reg;

sys/dev/fdt/mvpinctrl.c

315

mvpinctrl_set_pin(void *cookie, uint32_t *cells, int val)

sys/dev/fdt/mvpinctrl.c

318

uint32_t pin = cells[0];

sys/dev/fdt/mvpinctrl.c

319

uint32_t flags = cells[1];

sys/dev/fdt/mvpinctrl.c

337

uint32_t

sys/dev/fdt/mvpinctrl.c

338

a3700_xtal_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/mvpinctrl.c

69

int mvpinctrl_pinctrl(uint32_t, void *);

sys/dev/fdt/mvpinctrl.c

71

void mvpinctrl_config_pin(void *, uint32_t *, int);

sys/dev/fdt/mvpinctrl.c

72

int mvpinctrl_get_pin(void *, uint32_t *);

sys/dev/fdt/mvpinctrl.c

73

void mvpinctrl_set_pin(void *, uint32_t *, int);

sys/dev/fdt/mvpinctrl.c

75

uint32_t a3700_xtal_get_frequency(void *, uint32_t *);

sys/dev/fdt/mvrng.c

121

uint32_t status, detune;

sys/dev/fdt/mvrtc.c

85

uint32_t reg;

sys/dev/fdt/mvspi.c

192

uint32_t

sys/dev/fdt/mvspi.c

193

mvspi_clkdiv(struct mvspi_softc *sc, uint32_t freq)

sys/dev/fdt/mvspi.c

195

uint32_t pre;

sys/dev/fdt/mvspi.c

209

mvspi_wait_state(struct mvspi_softc *sc, uint32_t mask, uint32_t value)

sys/dev/fdt/mvspi.c

211

uint32_t state;

sys/dev/fdt/mvspi.c

291

uint32_t reg[1];

sys/dev/fdt/mvspi.c

57

uint32_t sc_pfreq;

sys/dev/fdt/mvspi.c

71

uint32_t mvspi_clkdiv(struct mvspi_softc *, uint32_t);

sys/dev/fdt/mvspi.c

77

int mvspi_wait_state(struct mvspi_softc *, uint32_t, uint32_t);

sys/dev/fdt/mvsw.c

116

uint32_t phy;

sys/dev/fdt/mvtemp.c

189

uint32_t

sys/dev/fdt/mvtemp.c

201

mvtemp_write(struct mvtemp_softc *sc, int reg, uint32_t val)

sys/dev/fdt/mvtemp.c

216

uint32_t ctrl;

sys/dev/fdt/mvtemp.c

234

uint32_t ctrl;

sys/dev/fdt/mvtemp.c

245

mvtemp_ap806_calc_temp(uint32_t stat)

sys/dev/fdt/mvtemp.c

256

uint32_t ctrl;

sys/dev/fdt/mvtemp.c

271

mvtemp_cp110_calc_temp(uint32_t stat)

sys/dev/fdt/mvtemp.c

58

uint32_t sc_stat_valid;

sys/dev/fdt/mvtemp.c

59

int32_t (*sc_calc_temp)(uint32_t);

sys/dev/fdt/mvtemp.c

79

uint32_t stat_valid;

sys/dev/fdt/mvtemp.c

81

int32_t (*calc_temp)(uint32_t);

sys/dev/fdt/mvtemp.c

87

int32_t mvtemp_ap806_calc_temp(uint32_t);

sys/dev/fdt/mvtemp.c

89

int32_t mvtemp_cp110_calc_temp(uint32_t);

sys/dev/fdt/mvuart.c

202

uint32_t stat;

sys/dev/fdt/mvuart.c

222

uint32_t stat;

sys/dev/fdt/ociic.c

128

uint32_t clock_speed, bus_speed;

sys/dev/fdt/ociic.c

129

uint32_t div;

sys/dev/fdt/ociic.c

314

uint32_t reg[1];

sys/dev/fdt/pciecam.c

146

uint32_t *ranges;

sys/dev/fdt/pciecam.c

164

if (rangeslen <= 0 || (rangeslen % sizeof(uint32_t)) ||

sys/dev/fdt/pciecam.c

165

(rangeslen / sizeof(uint32_t)) % (sc->sc_acells +

sys/dev/fdt/pciecam.c

173

nranges = (rangeslen / sizeof(uint32_t)) /

sys/dev/fdt/pciecam.c

409

if (bus_dmamap_create(pih->pih_dmat, sizeof(uint32_t), 1,

sys/dev/fdt/pciecam.c

410

sizeof(uint32_t), 0, BUS_DMA_WAITOK, &pih->pih_map)) {

sys/dev/fdt/pciecam.c

418

seg.ds_len = sizeof(uint32_t);

sys/dev/fdt/pciecam.c

421

&seg, 1, sizeof(uint32_t), BUS_DMA_WAITOK)) {

sys/dev/fdt/pciecam.c

436

uint32_t reg[4];

sys/dev/fdt/pciecam.c

65

uint32_t flags;

sys/dev/fdt/pinctrl.c

108

uint32_t

sys/dev/fdt/pinctrl.c

109

pinctrl_set2(int node, char *setting, uint32_t val)

sys/dev/fdt/pinctrl.c

111

uint32_t values[2];

sys/dev/fdt/pinctrl.c

122

uint32_t

sys/dev/fdt/pinctrl.c

123

pinctrl_set4(int node, char *setting, uint32_t val)

sys/dev/fdt/pinctrl.c

125

uint32_t values[4];

sys/dev/fdt/pinctrl.c

137

pinctrl_pinctrl(uint32_t phandle, void *cookie)

sys/dev/fdt/pinctrl.c

140

uint32_t *pins;

sys/dev/fdt/pinctrl.c

154

for (i = 0; i < len / sizeof(uint32_t); i += (1 + sc->sc_ncells)) {

sys/dev/fdt/pinctrl.c

155

uint32_t reg = pins[i];

sys/dev/fdt/pinctrl.c

156

uint32_t func = pins[i + 1];

sys/dev/fdt/pinctrl.c

157

uint32_t val = 0;

sys/dev/fdt/pinctrl.c

46

uint32_t sc_reg_width;

sys/dev/fdt/pinctrl.c

47

uint32_t sc_func_mask;

sys/dev/fdt/pinctrl.c

48

uint32_t sc_ncells;

sys/dev/fdt/pinctrl.c

62

int pinctrl_pinctrl(uint32_t, void *);

sys/dev/fdt/plgpio.c

104

plgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/plgpio.c

107

uint32_t pin = cells[0];

sys/dev/fdt/plgpio.c

119

plgpio_get_pin(void *cookie, uint32_t *cells)

sys/dev/fdt/plgpio.c

122

uint32_t pin = cells[0];

sys/dev/fdt/plgpio.c

123

uint32_t flags = cells[1];

sys/dev/fdt/plgpio.c

124

uint32_t reg;

sys/dev/fdt/plgpio.c

138

plgpio_set_pin(void *cookie, uint32_t *cells, int val)

sys/dev/fdt/plgpio.c

141

uint32_t pin = cells[0];

sys/dev/fdt/plgpio.c

142

uint32_t flags = cells[1];

sys/dev/fdt/plgpio.c

62

void plgpio_config_pin(void *, uint32_t *, int);

sys/dev/fdt/plgpio.c

63

int plgpio_get_pin(void *, uint32_t *);

sys/dev/fdt/plgpio.c

64

void plgpio_set_pin(void *, uint32_t *, int);

sys/dev/fdt/plrtc.c

66

uint32_t tod;

sys/dev/fdt/pluart_fdt.c

67

uint32_t periphid;

sys/dev/fdt/psci.c

265

smccc(uint32_t func_id, register_t arg0, register_t arg1, register_t arg2)

sys/dev/fdt/psci.c

276

smccc_arch_features(uint32_t arch_func_id)

sys/dev/fdt/psci.c

284

uint32_t

sys/dev/fdt/psci.c

346

psci_features(uint32_t psci_func_id)

sys/dev/fdt/psci.c

44

uint32_t sc_psci_version;

sys/dev/fdt/psci.c

45

uint32_t sc_system_off;

sys/dev/fdt/psci.c

46

uint32_t sc_system_reset;

sys/dev/fdt/psci.c

47

uint32_t sc_system_suspend;

sys/dev/fdt/psci.c

48

uint32_t sc_cpu_on;

sys/dev/fdt/psci.c

49

uint32_t sc_cpu_off;

sys/dev/fdt/psci.c

50

uint32_t sc_cpu_suspend;

sys/dev/fdt/psci.c

52

uint32_t sc_smccc_version;

sys/dev/fdt/psci.c

53

uint32_t sc_method;

sys/dev/fdt/psci.c

67

int32_t smccc_arch_features(uint32_t);

sys/dev/fdt/psci.c

69

uint32_t psci_version(void);

sys/dev/fdt/psci.c

70

int32_t psci_features(uint32_t);

sys/dev/fdt/psci.c

96

uint32_t version;

sys/dev/fdt/pscivar.h

44

int32_t psci_features(uint32_t);

sys/dev/fdt/pscivar.h

48

int32_t smccc(uint32_t, register_t, register_t, register_t);

sys/dev/fdt/pwmbl.c

103

if (len >= (int)sizeof(uint32_t)) {

sys/dev/fdt/pwmbl.c

107

sc->sc_nlevels = len / sizeof(uint32_t);

sys/dev/fdt/pwmbl.c

157

pwmbl_interpolate(struct pwmbl_softc *sc, uint32_t nsteps)

sys/dev/fdt/pwmbl.c

159

uint32_t *levels;

sys/dev/fdt/pwmbl.c

161

uint32_t base;

sys/dev/fdt/pwmbl.c

166

levels = mallocarray(nlevels, sizeof(uint32_t), M_DEVBUF, M_WAITOK);

sys/dev/fdt/pwmbl.c

174

free(sc->sc_levels, M_DEVBUF, sc->sc_nlevels * sizeof(uint32_t));

sys/dev/fdt/pwmbl.c

179

uint32_t

sys/dev/fdt/pwmbl.c

180

pwmbl_find_idx(struct pwmbl_softc *sc, uint32_t level)

sys/dev/fdt/pwmbl.c

182

uint32_t mid;

sys/dev/fdt/pwmbl.c

202

pwmbl_get_brightness(void *cookie, uint32_t *idx)

sys/dev/fdt/pwmbl.c

217

pwmbl_set_brightness(void *cookie, uint32_t idx)

sys/dev/fdt/pwmbl.c

240

uint32_t level;

sys/dev/fdt/pwmbl.c

36

uint32_t *sc_pwm;

sys/dev/fdt/pwmbl.c

38

uint32_t *sc_levels; /* NULL if simple ramp */

sys/dev/fdt/pwmbl.c

41

uint32_t sc_def_idx;

sys/dev/fdt/pwmbl.c

60

void pwmbl_interpolate(struct pwmbl_softc *, uint32_t);

sys/dev/fdt/pwmbl.c

61

int pwmbl_get_brightness(void *, uint32_t *);

sys/dev/fdt/pwmbl.c

62

int pwmbl_set_brightness(void *, uint32_t);

sys/dev/fdt/pwmbl.c

79

uint32_t *gpios;

sys/dev/fdt/pwmbl.c

80

uint32_t nsteps;

sys/dev/fdt/pwmfan.c

107

uint32_t

sys/dev/fdt/pwmfan.c

108

pwmfan_get_cooling_level(void *cookie, uint32_t *cells)

sys/dev/fdt/pwmfan.c

116

pwmfan_set_cooling_level(void *cookie, uint32_t *cells, uint32_t level)

sys/dev/fdt/pwmfan.c

35

uint32_t *sc_pwm;

sys/dev/fdt/pwmfan.c

37

uint32_t *sc_levels;

sys/dev/fdt/pwmfan.c

55

uint32_t pwmfan_get_cooling_level(void *, uint32_t *);

sys/dev/fdt/pwmfan.c

56

void pwmfan_set_cooling_level(void *, uint32_t *, uint32_t);

sys/dev/fdt/pwmfan.c

93

sc->sc_nlevels = len / sizeof(uint32_t);

sys/dev/fdt/pwmleds.c

39

uint32_t *sc_pwm;

sys/dev/fdt/pwmleds.c

41

uint32_t sc_max_brightness;

sys/dev/fdt/pwmreg.c

103

uint32_t

sys/dev/fdt/pwmreg.c

124

pwmreg_set_voltage(void *cookie, uint32_t voltage)

sys/dev/fdt/pwmreg.c

34

uint32_t *sc_pwm;

sys/dev/fdt/pwmreg.c

35

uint32_t sc_dutycycle_unit;

sys/dev/fdt/pwmreg.c

36

uint32_t sc_dutycycle_range[2];

sys/dev/fdt/pwmreg.c

53

uint32_t pwmreg_get_voltage(void *);

sys/dev/fdt/pwmreg.c

54

int pwmreg_set_voltage(void *, uint32_t);

sys/dev/fdt/qcaoss.c

180

uint32_t reg;

sys/dev/fdt/qcaoss.c

186

if (data == NULL || sizeof(uint32_t) + len > sc->sc_size ||

sys/dev/fdt/qcaoss.c

187

(len % sizeof(uint32_t)) != 0)

sys/dev/fdt/qcaoss.c

193

HWRITE4(sc, sc->sc_offset + sizeof(uint32_t) + i, reg);

sys/dev/fdt/qccpu.c

151

uint32_t freq;

sys/dev/fdt/qccpu.c

180

uint32_t

sys/dev/fdt/qccpu.c

181

qccpu_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/qccpu.c

186

uint32_t lval;

sys/dev/fdt/qccpu.c

187

uint32_t group;

sys/dev/fdt/qccpu.c

203

qccpu_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/qccpu.c

210

uint32_t group;

sys/dev/fdt/qccpu.c

249

uint32_t

sys/dev/fdt/qccpu.c

250

qccpu_lut_to_freq(struct qccpu_softc *sc, int index, uint32_t group)

sys/dev/fdt/qccpu.c

257

uint32_t

sys/dev/fdt/qccpu.c

258

qccpu_lut_to_cores(struct qccpu_softc *sc, int index, uint32_t group)

sys/dev/fdt/qccpu.c

271

uint32_t lval;

sys/dev/fdt/qccpu.c

66

uint32_t sc_freq[MAX_GROUP][MAX_LUT];

sys/dev/fdt/qccpu.c

77

int qccpu_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/qccpu.c

78

uint32_t qccpu_get_frequency(void *, uint32_t *);

sys/dev/fdt/qccpu.c

79

uint32_t qccpu_lut_to_freq(struct qccpu_softc *, int, uint32_t);

sys/dev/fdt/qccpu.c

80

uint32_t qccpu_lut_to_cores(struct qccpu_softc *, int, uint32_t);

sys/dev/fdt/qccpucp.c

130

qccpucp_channel(void *cookie, uint32_t *cells, struct mbox_client *mc)

sys/dev/fdt/qccpucp.c

78

void *qccpucp_channel(void *, uint32_t *, struct mbox_client *);

sys/dev/fdt/qcdpc.c

246

uint32_t current_level;

sys/dev/fdt/qcdpc.c

266

uint32_t status;

sys/dev/fdt/qcdpc.c

289

uint32_t status;

sys/dev/fdt/qcdpc.c

319

uint32_t val, stat;

sys/dev/fdt/qcdpc.c

385

uint32_t val;

sys/dev/fdt/qcdpc.c

70

uint32_t sc_intr_status;

sys/dev/fdt/qcdpc.c

73

uint32_t sc_bl_level;

sys/dev/fdt/qcdrm.c

150

uint32_t stat;

sys/dev/fdt/qcgpio_fdt.c

201

qcgpio_fdt_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/qcgpio_fdt.c

204

uint32_t pin = cells[0];

sys/dev/fdt/qcgpio_fdt.c

216

qcgpio_fdt_get_pin(void *cookie, uint32_t *cells)

sys/dev/fdt/qcgpio_fdt.c

219

uint32_t pin = cells[0];

sys/dev/fdt/qcgpio_fdt.c

220

uint32_t flags = cells[1];

sys/dev/fdt/qcgpio_fdt.c

221

uint32_t reg;

sys/dev/fdt/qcgpio_fdt.c

235

qcgpio_fdt_set_pin(void *cookie, uint32_t *cells, int val)

sys/dev/fdt/qcgpio_fdt.c

238

uint32_t pin = cells[0];

sys/dev/fdt/qcgpio_fdt.c

239

uint32_t flags = cells[1];

sys/dev/fdt/qcgpio_fdt.c

257

qcgpio_fdt_intr_establish_pin(void *cookie, uint32_t *cells, int ipl,

sys/dev/fdt/qcgpio_fdt.c

261

uint32_t icells[2];

sys/dev/fdt/qcgpio_fdt.c

274

uint32_t reg;

sys/dev/fdt/qcgpio_fdt.c

378

uint32_t stat;

sys/dev/fdt/qcgpio_fdt.c

77

uint32_t sc_npins;

sys/dev/fdt/qcgpio_fdt.c

93

void qcgpio_fdt_config_pin(void *, uint32_t *, int);

sys/dev/fdt/qcgpio_fdt.c

94

int qcgpio_fdt_get_pin(void *, uint32_t *);

sys/dev/fdt/qcgpio_fdt.c

95

void qcgpio_fdt_set_pin(void *, uint32_t *, int);

sys/dev/fdt/qcgpio_fdt.c

96

void *qcgpio_fdt_intr_establish_pin(void *, uint32_t *, int,

sys/dev/fdt/qciic_fdt.c

143

qciic_fdt_wait(struct qciic_fdt_softc *sc, uint32_t bits)

sys/dev/fdt/qciic_fdt.c

145

uint32_t stat;

sys/dev/fdt/qciic_fdt.c

163

uint32_t stat, word;

sys/dev/fdt/qciic_fdt.c

188

uint32_t stat, word;

sys/dev/fdt/qciic_fdt.c

216

uint32_t m_cmd, m_param, stat;

sys/dev/fdt/qciic_fdt.c

312

uint32_t reg[1];

sys/dev/fdt/qcipcc.c

155

uint32_t reg;

sys/dev/fdt/qcipcc.c

245

qcipcc_channel(void *cookie, uint32_t *cells, struct mbox_client *mc)

sys/dev/fdt/qcipcc.c

70

uint32_t ch_client_id;

sys/dev/fdt/qcipcc.c

71

uint32_t ch_signal_id;

sys/dev/fdt/qcipcc.c

93

void *qcipcc_channel(void *, uint32_t *, struct mbox_client *);

sys/dev/fdt/qcmtx.c

51

int qcmtx_lock(void *, uint32_t *, int);

sys/dev/fdt/qcmtx.c

97

qcmtx_lock(void *cookie, uint32_t *cells, int lock)

sys/dev/fdt/qcpas.c

1014

qcpas_glink_recv_intent(struct qcpas_softc *sc, uint32_t rcid, uint32_t count)

sys/dev/fdt/qcpas.c

1047

qcpas_glink_recv_tx_data(struct qcpas_softc *sc, uint32_t rcid, uint32_t liid)

sys/dev/fdt/qcpas.c

105

uint32_t sc_glink_max_channel;

sys/dev/fdt/qcpas.c

1052

uint32_t chunk_size, left_size;

sys/dev/fdt/qcpas.c

109

uint32_t sc_last_full_capacity;

sys/dev/fdt/qcpas.c

110

uint32_t sc_warning_capacity;

sys/dev/fdt/qcpas.c

1102

qcpas_glink_recv_rx_done(struct qcpas_softc *sc, uint32_t rcid, uint32_t riid,

sys/dev/fdt/qcpas.c

111

uint32_t sc_low_capacity;

sys/dev/fdt/qcpas.c

1190

uint32_t owner;

sys/dev/fdt/qcpas.c

1194

uint32_t type;

sys/dev/fdt/qcpas.c

1197

uint32_t opcode;

sys/dev/fdt/qcpas.c

1221

uint32_t power_unit;

sys/dev/fdt/qcpas.c

1222

uint32_t design_capacity;

sys/dev/fdt/qcpas.c

1223

uint32_t last_full_capacity;

sys/dev/fdt/qcpas.c

1224

uint32_t battery_tech;

sys/dev/fdt/qcpas.c

1225

uint32_t design_voltage;

sys/dev/fdt/qcpas.c

1226

uint32_t capacity_low;

sys/dev/fdt/qcpas.c

1227

uint32_t capacity_warning;

sys/dev/fdt/qcpas.c

1228

uint32_t cycle_count;

sys/dev/fdt/qcpas.c

1229

uint32_t accuracy;

sys/dev/fdt/qcpas.c

1230

uint32_t max_sample_time_ms;

sys/dev/fdt/qcpas.c

1231

uint32_t min_sample_time_ms;

sys/dev/fdt/qcpas.c

1232

uint32_t max_average_interval_ms;

sys/dev/fdt/qcpas.c

1233

uint32_t min_average_interval_ms;

sys/dev/fdt/qcpas.c

1234

uint32_t capacity_granularity1;

sys/dev/fdt/qcpas.c

1235

uint32_t capacity_granularity2;

sys/dev/fdt/qcpas.c

1236

uint32_t swappable;

sys/dev/fdt/qcpas.c

1237

uint32_t capabilities;

sys/dev/fdt/qcpas.c

1244

uint32_t critical_bias;

sys/dev/fdt/qcpas.c

1248

uint32_t battery_id;

sys/dev/fdt/qcpas.c

1252

uint32_t battery_state;

sys/dev/fdt/qcpas.c

1256

uint32_t capacity;

sys/dev/fdt/qcpas.c

1258

uint32_t battery_voltage;

sys/dev/fdt/qcpas.c

1259

uint32_t power_state;

sys/dev/fdt/qcpas.c

1261

uint32_t charging_source;

sys/dev/fdt/qcpas.c

1265

uint32_t temperature;

sys/dev/fdt/qcpas.c

1287

uint32_t battery_id;

sys/dev/fdt/qcpas.c

1302

uint32_t battery_id;

sys/dev/fdt/qcpas.c

1318

uint32_t enable;

sys/dev/fdt/qcpas.c

1319

uint32_t target_soc;

sys/dev/fdt/qcpas.c

1320

uint32_t delta_soc;

sys/dev/fdt/qcpas.c

1373

uint32_t notification;

sys/dev/fdt/qcpas.c

1387

if (len - sizeof(hdr) != sizeof(uint32_t)) {

sys/dev/fdt/qcpas.c

1393

sizeof(uint32_t));

sys/dev/fdt/qcpas.c

1513

uint32_t delta;

sys/dev/fdt/qcpas.c

362

uint32_t memreg[2] = {};

sys/dev/fdt/qcpas.c

363

uint32_t reg[4];

sys/dev/fdt/qcpas.c

40

extern int qcscm_pas_init_image(uint32_t, paddr_t);

sys/dev/fdt/qcpas.c

41

extern int qcscm_pas_mem_setup(uint32_t, paddr_t, size_t);

sys/dev/fdt/qcpas.c

42

extern int qcscm_pas_auth_and_reset(uint32_t);

sys/dev/fdt/qcpas.c

43

extern int qcscm_pas_shutdown(uint32_t);

sys/dev/fdt/qcpas.c

640

uint32_t param2;

sys/dev/fdt/qcpas.c

645

uint32_t size;

sys/dev/fdt/qcpas.c

646

uint32_t iid;

sys/dev/fdt/qcpas.c

651

uint32_t it_id;

sys/dev/fdt/qcpas.c

652

uint32_t it_size;

sys/dev/fdt/qcpas.c

660

uint32_t ch_rcid;

sys/dev/fdt/qcpas.c

661

uint32_t ch_lcid;

sys/dev/fdt/qcpas.c

662

uint32_t ch_max_intent;

sys/dev/fdt/qcpas.c

712

uint32_t remote;

sys/dev/fdt/qcpas.c

713

uint32_t *descs;

sys/dev/fdt/qcpas.c

760

uint32_t head, tail;

sys/dev/fdt/qcpas.c

79

uint32_t sc_pas_id;

sys/dev/fdt/qcpas.c

793

uint32_t tail;

sys/dev/fdt/qcpas.c

80

uint32_t sc_dtb_pas_id;

sys/dev/fdt/qcpas.c

807

uint32_t head, tail;

sys/dev/fdt/qcpas.c

81

uint32_t sc_lite_pas_id;

sys/dev/fdt/qcpas.c

837

uint32_t head;

sys/dev/fdt/qcpas.c

856

uint32_t chunk_size, left_size;

sys/dev/fdt/qcpas.c

88

volatile uint32_t *sc_tx_tail;

sys/dev/fdt/qcpas.c

886

qcpas_glink_recv_version(struct qcpas_softc *sc, uint32_t version,

sys/dev/fdt/qcpas.c

887

uint32_t features)

sys/dev/fdt/qcpas.c

89

volatile uint32_t *sc_tx_head;

sys/dev/fdt/qcpas.c

90

volatile uint32_t *sc_rx_tail;

sys/dev/fdt/qcpas.c

906

qcpas_glink_recv_open(struct qcpas_softc *sc, uint32_t rcid, uint32_t namelen)

sys/dev/fdt/qcpas.c

91

volatile uint32_t *sc_rx_head;

sys/dev/fdt/qcpas.c

93

uint32_t sc_tx_off;

sys/dev/fdt/qcpas.c

94

uint32_t sc_rx_off;

sys/dev/fdt/qcpas.c

975

qcpas_glink_recv_open_ack(struct qcpas_softc *sc, uint32_t lcid)

sys/dev/fdt/qcpdc.c

110

if (len <= 0 || len % (3 * sizeof(uint32_t)) != 0) {

sys/dev/fdt/qcpdc.c

115

sc->sc_npr = len / (3 * sizeof(uint32_t));

sys/dev/fdt/qcpdc.c

119

(uint32_t *)sc->sc_pr, len);

sys/dev/fdt/qcpdc.c

157

uint32_t pcells[3];

sys/dev/fdt/qcpdc.c

28

#define PDC_INTR_ENABLE(x) (0x10 + (sizeof(uint32_t) * ((x) / 32)))

sys/dev/fdt/qcpdc.c

30

#define PDC_INTR_CONFIG(x) (0x110 + (sizeof(uint32_t) * (x)))

sys/dev/fdt/qcpdc.c

53

uint32_t pin_base;

sys/dev/fdt/qcpdc.c

54

uint32_t gic_base;

sys/dev/fdt/qcpdc.c

55

uint32_t count;

sys/dev/fdt/qcpmicgpio.c

170

qcpmicgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/qcpmicgpio.c

173

uint32_t pin = cells[0] - 1;

sys/dev/fdt/qcpmicgpio.c

196

qcpmicgpio_get_pin(void *cookie, uint32_t *cells)

sys/dev/fdt/qcpmicgpio.c

199

uint32_t pin = cells[0] - 1;

sys/dev/fdt/qcpmicgpio.c

200

uint32_t flags = cells[1];

sys/dev/fdt/qcpmicgpio.c

240

qcpmicgpio_set_pin(void *cookie, uint32_t *cells, int val)

sys/dev/fdt/qcpmicgpio.c

243

uint32_t pin = cells[0] - 1;

sys/dev/fdt/qcpmicgpio.c

244

uint32_t flags = cells[1];

sys/dev/fdt/qcpmicgpio.c

87

void qcpmicgpio_config_pin(void *, uint32_t *, int);

sys/dev/fdt/qcpmicgpio.c

88

int qcpmicgpio_get_pin(void *, uint32_t *);

sys/dev/fdt/qcpmicgpio.c

89

void qcpmicgpio_set_pin(void *, uint32_t *, int);

sys/dev/fdt/qcpon.c

116

uint32_t sts;

sys/dev/fdt/qcpon.c

46

uint32_t sc_last_sts;

sys/dev/fdt/qcpon.c

76

uint32_t reg[2];

sys/dev/fdt/qcpwm.c

102

int qcpwm_get_state(void *, uint32_t *, struct pwm_state *);

sys/dev/fdt/qcpwm.c

103

int qcpwm_set_state(void *, uint32_t *, struct pwm_state *);

sys/dev/fdt/qcpwm.c

146

qcpwm_get_state(void *cookie, uint32_t *cells, struct pwm_state *ps)

sys/dev/fdt/qcpwm.c

208

qcpwm_set_state(void *cookie, uint32_t *cells, struct pwm_state *ps)

sys/dev/fdt/qcrtc.c

105

uint32_t reg, off;

sys/dev/fdt/qcrtc.c

132

uint32_t reg, off;

sys/dev/fdt/qcrtc.c

63

extern int qcscm_uefi_rtc_get(uint32_t *);

sys/dev/fdt/qcrtc.c

64

extern int qcscm_uefi_rtc_set(uint32_t);

sys/dev/fdt/qcrtc.c

79

uint32_t reg[2];

sys/dev/fdt/qcscm.c

120

uint32_t sc_uefi_id;

sys/dev/fdt/qcscm.c

136

uint32_t, uint64_t *, int, uint64_t *);

sys/dev/fdt/qcscm.c

137

int qcscm_tee_app_get_id(struct qcscm_softc *, const char *, uint32_t *);

sys/dev/fdt/qcscm.c

138

int qcscm_tee_app_send(struct qcscm_softc *, uint32_t, uint64_t, uint64_t,

sys/dev/fdt/qcscm.c

142

int, EFI_GUID *, uint32_t *, uint8_t *, int *);

sys/dev/fdt/qcscm.c

144

int, EFI_GUID *, uint32_t, uint8_t *, int);

sys/dev/fdt/qcscm.c

160

int qcscm_uefi_rtc_get(uint32_t *);

sys/dev/fdt/qcscm.c

161

int qcscm_uefi_rtc_set(uint32_t);

sys/dev/fdt/qcscm.c

246

uint32_t arginfo, uint64_t *args, int arglen, uint64_t *res)

sys/dev/fdt/qcscm.c

291

qcscm_tee_app_get_id(struct qcscm_softc *sc, const char *name, uint32_t *id)

sys/dev/fdt/qcscm.c

296

uint32_t arginfo;

sys/dev/fdt/qcscm.c

336

qcscm_tee_app_send(struct qcscm_softc *sc, uint32_t id, uint64_t req_phys,

sys/dev/fdt/qcscm.c

341

uint32_t arginfo;

sys/dev/fdt/qcscm.c

374

uint32_t command_id;

sys/dev/fdt/qcscm.c

375

uint32_t length;

sys/dev/fdt/qcscm.c

376

uint32_t name_offset;

sys/dev/fdt/qcscm.c

377

uint32_t name_size;

sys/dev/fdt/qcscm.c

378

uint32_t guid_offset;

sys/dev/fdt/qcscm.c

379

uint32_t guid_size;

sys/dev/fdt/qcscm.c

380

uint32_t data_size;

sys/dev/fdt/qcscm.c

384

uint32_t command_id;

sys/dev/fdt/qcscm.c

385

uint32_t length;

sys/dev/fdt/qcscm.c

386

uint32_t status;

sys/dev/fdt/qcscm.c

387

uint32_t attributes;

sys/dev/fdt/qcscm.c

388

uint32_t data_offset;

sys/dev/fdt/qcscm.c

389

uint32_t data_size;

sys/dev/fdt/qcscm.c

395

uint32_t *attributes, uint8_t *data, int *data_size)

sys/dev/fdt/qcscm.c

480

uint32_t command_id;

sys/dev/fdt/qcscm.c

481

uint32_t length;

sys/dev/fdt/qcscm.c

482

uint32_t name_offset;

sys/dev/fdt/qcscm.c

483

uint32_t name_size;

sys/dev/fdt/qcscm.c

484

uint32_t guid_offset;

sys/dev/fdt/qcscm.c

485

uint32_t guid_size;

sys/dev/fdt/qcscm.c

486

uint32_t attributes;

sys/dev/fdt/qcscm.c

487

uint32_t data_offset;

sys/dev/fdt/qcscm.c

488

uint32_t data_size;

sys/dev/fdt/qcscm.c

492

uint32_t command_id;

sys/dev/fdt/qcscm.c

493

uint32_t length;

sys/dev/fdt/qcscm.c

494

uint32_t status;

sys/dev/fdt/qcscm.c

495

uint32_t unknown[2];

sys/dev/fdt/qcscm.c

501

uint32_t attributes, uint8_t *data, int data_size)

sys/dev/fdt/qcscm.c

562

uint32_t command_id;

sys/dev/fdt/qcscm.c

563

uint32_t length;

sys/dev/fdt/qcscm.c

564

uint32_t guid_offset;

sys/dev/fdt/qcscm.c

565

uint32_t guid_size;

sys/dev/fdt/qcscm.c

566

uint32_t name_offset;

sys/dev/fdt/qcscm.c

567

uint32_t name_size;

sys/dev/fdt/qcscm.c

571

uint32_t command_id;

sys/dev/fdt/qcscm.c

572

uint32_t length;

sys/dev/fdt/qcscm.c

573

uint32_t status;

sys/dev/fdt/qcscm.c

574

uint32_t guid_offset;

sys/dev/fdt/qcscm.c

575

uint32_t guid_size;

sys/dev/fdt/qcscm.c

576

uint32_t name_offset;

sys/dev/fdt/qcscm.c

577

uint32_t name_size;

sys/dev/fdt/qcscm.c

786

qcscm_uefi_rtc_get(uint32_t *off)

sys/dev/fdt/qcscm.c

789

uint32_t rtcinfo[3];

sys/dev/fdt/qcscm.c

806

qcscm_uefi_rtc_set(uint32_t off)

sys/dev/fdt/qcscm.c

809

uint32_t rtcinfo[3];

sys/dev/fdt/qcscm.c

839

qcscm_pas_init_image(uint32_t peripheral, paddr_t metadata)

sys/dev/fdt/qcscm.c

844

uint32_t arginfo;

sys/dev/fdt/qcscm.c

868

qcscm_pas_mem_setup(uint32_t peripheral, paddr_t addr, size_t size)

sys/dev/fdt/qcscm.c

873

uint32_t arginfo;

sys/dev/fdt/qcscm.c

899

qcscm_pas_auth_and_reset(uint32_t peripheral)

sys/dev/fdt/qcscm.c

904

uint32_t arginfo;

sys/dev/fdt/qcscm.c

926

qcscm_pas_shutdown(uint32_t peripheral)

sys/dev/fdt/qcscm.c

931

uint32_t arginfo;

sys/dev/fdt/qcsdam.c

67

uint32_t reg;

sys/dev/fdt/qcsmem.c

103

uint32_t size;

sys/dev/fdt/qcsmem.c

106

uint32_t reserved;

sys/dev/fdt/qcsmem.c

110

uint32_t magic;

sys/dev/fdt/qcsmem.c

112

uint32_t size;

sys/dev/fdt/qcsmem.c

113

uint32_t base_addr;

sys/dev/fdt/qcsmem.c

114

uint32_t reserved;

sys/dev/fdt/qcsmem.c

115

uint32_t num_items;

sys/dev/fdt/qcsmem.c

164

uint32_t version;

sys/dev/fdt/qcsmem.c

165

uint32_t memreg;

sys/dev/fdt/qcsmem.c

166

uint32_t reg[4];

sys/dev/fdt/qcsmem.c

36

uint32_t command;

sys/dev/fdt/qcsmem.c

37

uint32_t status;

sys/dev/fdt/qcsmem.c

38

uint32_t params[2];

sys/dev/fdt/qcsmem.c

42

uint32_t allocated;

sys/dev/fdt/qcsmem.c

43

uint32_t offset;

sys/dev/fdt/qcsmem.c

44

uint32_t size;

sys/dev/fdt/qcsmem.c

45

uint32_t aux_base;

sys/dev/fdt/qcsmem.c

457

uint32_t aux_base;

sys/dev/fdt/qcsmem.c

51

uint32_t version[32];

sys/dev/fdt/qcsmem.c

55

uint32_t initialized;

sys/dev/fdt/qcsmem.c

56

uint32_t free_offset;

sys/dev/fdt/qcsmem.c

57

uint32_t available;

sys/dev/fdt/qcsmem.c

58

uint32_t reserved;

sys/dev/fdt/qcsmem.c

63

uint32_t offset;

sys/dev/fdt/qcsmem.c

64

uint32_t size;

sys/dev/fdt/qcsmem.c

65

uint32_t flags;

sys/dev/fdt/qcsmem.c

69

uint32_t cacheline;

sys/dev/fdt/qcsmem.c

70

uint32_t reserved[7];

sys/dev/fdt/qcsmem.c

74

uint32_t magic;

sys/dev/fdt/qcsmem.c

76

uint32_t version;

sys/dev/fdt/qcsmem.c

78

uint32_t num_entries;

sys/dev/fdt/qcsmem.c

79

uint32_t reserved[5];

sys/dev/fdt/qcsmem.c

84

uint32_t magic;

sys/dev/fdt/qcsmem.c

87

uint32_t size;

sys/dev/fdt/qcsmem.c

88

uint32_t offset_free_uncached;

sys/dev/fdt/qcsmem.c

89

uint32_t offset_free_cached;

sys/dev/fdt/qcsmem.c

90

uint32_t reserved[3];

sys/dev/fdt/qcsmptp.c

266

uint32_t changed, val;

sys/dev/fdt/qcsmptp.c

35

uint32_t magic;

sys/dev/fdt/qcsmptp.c

45

uint32_t flags;

sys/dev/fdt/qcsmptp.c

51

uint32_t value;

sys/dev/fdt/qcsmptp.c

74

uint32_t *e_value;

sys/dev/fdt/qcsmptp.c

75

uint32_t e_last_value;

sys/dev/fdt/qcsmptp.c

86

uint32_t sc_smem_id[2];

sys/dev/fdt/qcspmi.c

133

uint32_t ih_apid;

sys/dev/fdt/qcspmi.c

200

uint32_t val, ppid, irq_own;

sys/dev/fdt/qcspmi.c

225

uint32_t reg[8];

sys/dev/fdt/qcspmi.c

342

uint32_t reg[2];

sys/dev/fdt/qcspmi.c

382

uint32_t reg;

sys/dev/fdt/qcspmi.c

451

uint32_t reg;

sys/dev/fdt/qcspmi.c

648

uint32_t status;

sys/dev/fdt/qctsens.c

127

uint32_t propdata[4];

sys/dev/fdt/qctsens.c

128

uint32_t phandle, reg;

sys/dev/fdt/qctsens.c

193

qctsens_get_temperature(void *cookie, uint32_t *cells)

sys/dev/fdt/qctsens.c

196

uint32_t id = cells[0];

sys/dev/fdt/qctsens.c

73

int32_t qctsens_get_temperature(void *, uint32_t *);

sys/dev/fdt/qctsens.c

89

uint32_t reg;

sys/dev/fdt/rkanxdp.c

102

uint32_t grf;

sys/dev/fdt/rkanxdp.c

151

uint32_t write_mask = EDP_LCDC_SEL << 16;

sys/dev/fdt/rkanxdp.c

152

uint32_t write_val = crtc_index == 0 ? EDP_LCDC_SEL : 0;

sys/dev/fdt/rkclock.c

1003

rk3288_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

1005

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

1040

rk3288_reset(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

1043

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

1044

uint32_t mask = (1 << (idx % 16));

sys/dev/fdt/rkclock.c

1194

uint32_t

sys/dev/fdt/rkclock.c

1195

rk3308_armclk_parent(uint32_t mux)

sys/dev/fdt/rkclock.c

1209

uint32_t

sys/dev/fdt/rkclock.c

1212

uint32_t reg, mux, div_con;

sys/dev/fdt/rkclock.c

1213

uint32_t idx;

sys/dev/fdt/rkclock.c

1226

rk3308_set_armclk(struct rkclock_softc *sc, uint32_t freq)

sys/dev/fdt/rkclock.c

1228

uint32_t reg, mux;

sys/dev/fdt/rkclock.c

1229

uint32_t old_freq, div;

sys/dev/fdt/rkclock.c

1230

uint32_t idx;

sys/dev/fdt/rkclock.c

1279

uint32_t

sys/dev/fdt/rkclock.c

1282

uint32_t fbdiv, postdiv1, postdiv2, refdiv;

sys/dev/fdt/rkclock.c

1283

uint32_t dsmpd, fracdiv;

sys/dev/fdt/rkclock.c

1285

uint32_t reg;

sys/dev/fdt/rkclock.c

1308

rk3308_set_pll(struct rkclock_softc *sc, bus_size_t base, uint32_t freq)

sys/dev/fdt/rkclock.c

1310

uint32_t fbdiv, postdiv1, postdiv2, refdiv;

sys/dev/fdt/rkclock.c

1445

uint32_t

sys/dev/fdt/rkclock.c

1448

uint32_t reg, mux, pll, div_con;

sys/dev/fdt/rkclock.c

1467

rk3308_set_rtc32k(struct rkclock_softc *sc, uint32_t freq)

sys/dev/fdt/rkclock.c

1470

uint32_t vpll0_freq, vpll1_freq, mux, div_con;

sys/dev/fdt/rkclock.c

1490

uint32_t

sys/dev/fdt/rkclock.c

1491

rk3308_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/rkclock.c

1494

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

1526

rk3308_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/rkclock.c

1529

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

1553

rk3308_set_parent(void *cookie, uint32_t *cells, uint32_t *pcells)

sys/dev/fdt/rkclock.c

1564

rk3308_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

1566

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

1577

rk3308_reset(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

1580

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

1581

uint32_t mask = (1 << (idx % 16));

sys/dev/fdt/rkclock.c

1808

uint32_t

sys/dev/fdt/rkclock.c

1809

rk3328_armclk_parent(uint32_t mux)

sys/dev/fdt/rkclock.c

1825

uint32_t

sys/dev/fdt/rkclock.c

1828

uint32_t reg, mux, div_con;

sys/dev/fdt/rkclock.c

1829

uint32_t idx;

sys/dev/fdt/rkclock.c

1842

rk3328_set_armclk(struct rkclock_softc *sc, uint32_t freq)

sys/dev/fdt/rkclock.c

1844

uint32_t reg, mux;

sys/dev/fdt/rkclock.c

1845

uint32_t old_freq, div;

sys/dev/fdt/rkclock.c

1846

uint32_t idx;

sys/dev/fdt/rkclock.c

1897

uint32_t

sys/dev/fdt/rkclock.c

1900

uint32_t fbdiv, postdiv1, postdiv2, refdiv;

sys/dev/fdt/rkclock.c

1901

uint32_t dsmpd, fracdiv;

sys/dev/fdt/rkclock.c

1903

uint32_t reg;

sys/dev/fdt/rkclock.c

1926

rk3328_set_pll(struct rkclock_softc *sc, bus_size_t base, uint32_t freq)

sys/dev/fdt/rkclock.c

1928

uint32_t fbdiv, postdiv1, postdiv2, refdiv;

sys/dev/fdt/rkclock.c

2031

rk3328_set_frac_pll(struct rkclock_softc *sc, bus_size_t base, uint32_t freq)

sys/dev/fdt/rkclock.c

2033

uint32_t fbdiv, postdiv1, postdiv2, refdiv, fracdiv;

sys/dev/fdt/rkclock.c

2035

uint32_t reg;

sys/dev/fdt/rkclock.c

2127

uint32_t

sys/dev/fdt/rkclock.c

2128

rk3328_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/rkclock.c

2131

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

2132

uint32_t reg;

sys/dev/fdt/rkclock.c

2175

rk3328_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/rkclock.c

2178

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

2179

uint32_t reg, mux;

sys/dev/fdt/rkclock.c

2217

rk3328_set_parent(void *cookie, uint32_t *cells, uint32_t *pcells)

sys/dev/fdt/rkclock.c

2220

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

2221

uint32_t parent;

sys/dev/fdt/rkclock.c

2270

rk3328_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

2272

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

2283

rk3328_reset(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

2286

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

2287

uint32_t mask = (1 << (idx % 16));

sys/dev/fdt/rkclock.c

244

uint32_t reg;

sys/dev/fdt/rkclock.c

248

uint32_t flags;

sys/dev/fdt/rkclock.c

2629

uint32_t

sys/dev/fdt/rkclock.c

2632

uint32_t fbdiv, postdiv1, postdiv2, refdiv;

sys/dev/fdt/rkclock.c

2633

uint32_t pll_work_mode;

sys/dev/fdt/rkclock.c

2634

uint32_t reg;

sys/dev/fdt/rkclock.c

2657

rk3399_set_pll(struct rkclock_softc *sc, bus_size_t base, uint32_t freq)

sys/dev/fdt/rkclock.c

2659

uint32_t fbdiv, postdiv1, postdiv2, refdiv;

sys/dev/fdt/rkclock.c

272

uint32_t sc_phandle;

sys/dev/fdt/rkclock.c

2760

uint32_t

sys/dev/fdt/rkclock.c

2761

rk3399_armclk_parent(uint32_t mux)

sys/dev/fdt/rkclock.c

2777

uint32_t

sys/dev/fdt/rkclock.c

2780

uint32_t reg, mux, div_con;

sys/dev/fdt/rkclock.c

2781

uint32_t idx;

sys/dev/fdt/rkclock.c

2794

rk3399_set_armclk(struct rkclock_softc *sc, bus_size_t clksel, uint32_t freq)

sys/dev/fdt/rkclock.c

2796

uint32_t reg, mux;

sys/dev/fdt/rkclock.c

2797

uint32_t old_freq, div;

sys/dev/fdt/rkclock.c

2798

uint32_t idx;

sys/dev/fdt/rkclock.c

2847

uint32_t

sys/dev/fdt/rkclock.c

2848

rk3399_get_frac(struct rkclock_softc *sc, uint32_t parent, bus_size_t base)

sys/dev/fdt/rkclock.c

2850

uint32_t parent_freq, frac;

sys/dev/fdt/rkclock.c

2863

rk3399_set_frac(struct rkclock_softc *sc, uint32_t parent, bus_size_t base,

sys/dev/fdt/rkclock.c

2864

uint32_t freq)

sys/dev/fdt/rkclock.c

2866

uint32_t n, d;

sys/dev/fdt/rkclock.c

2867

uint32_t p0, p1, p2;

sys/dev/fdt/rkclock.c

2868

uint32_t q0, q1, q2;

sys/dev/fdt/rkclock.c

2869

uint32_t a, tmp;

sys/dev/fdt/rkclock.c

291

uint32_t rk3288_get_frequency(void *, uint32_t *);

sys/dev/fdt/rkclock.c

292

int rk3288_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/rkclock.c

2922

uint32_t

sys/dev/fdt/rkclock.c

2923

rk3399_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/rkclock.c

2926

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

293

void rk3288_enable(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

294

void rk3288_reset(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

297

uint32_t rk3308_get_frequency(void *, uint32_t *);

sys/dev/fdt/rkclock.c

2970

rk3399_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/rkclock.c

2973

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

298

int rk3308_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/rkclock.c

299

int rk3308_set_parent(void *, uint32_t *, uint32_t *);

sys/dev/fdt/rkclock.c

300

void rk3308_enable(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

301

void rk3308_reset(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

3023

rk3399_set_parent(void *cookie, uint32_t *cells, uint32_t *pcells)

sys/dev/fdt/rkclock.c

3034

rk3399_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

3037

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

304

uint32_t rk3328_get_frequency(void *, uint32_t *);

sys/dev/fdt/rkclock.c

305

int rk3328_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/rkclock.c

306

int rk3328_set_parent(void *, uint32_t *, uint32_t *);

sys/dev/fdt/rkclock.c

307

void rk3328_enable(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

308

void rk3328_reset(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

3086

rk3399_reset(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

3089

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

3090

uint32_t mask = (1 << (idx % 16));

sys/dev/fdt/rkclock.c

311

uint32_t rk3399_get_frequency(void *, uint32_t *);

sys/dev/fdt/rkclock.c

312

int rk3399_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/rkclock.c

313

int rk3399_set_parent(void *, uint32_t *, uint32_t *);

sys/dev/fdt/rkclock.c

3131

uint32_t

sys/dev/fdt/rkclock.c

3132

rk3399_pmu_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/rkclock.c

3135

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

314

void rk3399_enable(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

3148

rk3399_pmu_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/rkclock.c

315

void rk3399_reset(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

3151

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

3164

rk3399_pmu_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

3166

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

318

uint32_t rk3399_pmu_get_frequency(void *, uint32_t *);

sys/dev/fdt/rkclock.c

3185

rk3399_pmu_reset(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

3187

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

319

int rk3399_pmu_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/rkclock.c

320

void rk3399_pmu_enable(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

321

void rk3399_pmu_reset(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

324

uint32_t rk3528_get_frequency(void *, uint32_t *);

sys/dev/fdt/rkclock.c

325

int rk3528_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/rkclock.c

326

int rk3528_set_parent(void *, uint32_t *, uint32_t *);

sys/dev/fdt/rkclock.c

327

void rk3528_enable(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

328

void rk3528_reset(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

3290

uint32_t

sys/dev/fdt/rkclock.c

3291

rk3528_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/rkclock.c

3294

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

331

uint32_t rk3568_get_frequency(void *, uint32_t *);

sys/dev/fdt/rkclock.c

3313

rk3528_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/rkclock.c

3316

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

332

int rk3568_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/rkclock.c

3322

rk3528_set_parent(void *cookie, uint32_t *cells, uint32_t *pcells)

sys/dev/fdt/rkclock.c

333

int rk3568_set_parent(void *, uint32_t *, uint32_t *);

sys/dev/fdt/rkclock.c

3330

rk3528_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

3332

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

334

void rk3568_enable(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

3342

rk3528_reset(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

3345

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

3346

uint32_t bit, mask, reg;

sys/dev/fdt/rkclock.c

335

void rk3568_reset(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

338

uint32_t rk3568_pmu_get_frequency(void *, uint32_t *);

sys/dev/fdt/rkclock.c

339

int rk3568_pmu_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/rkclock.c

340

void rk3568_pmu_enable(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

341

void rk3568_pmu_reset(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

344

uint32_t rk3576_get_frequency(void *, uint32_t *);

sys/dev/fdt/rkclock.c

345

int rk3576_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/rkclock.c

346

int rk3576_set_parent(void *, uint32_t *, uint32_t *);

sys/dev/fdt/rkclock.c

347

void rk3576_enable(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

348

void rk3576_reset(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

351

int rk3588_set_pll(struct rkclock_softc *, bus_size_t, uint32_t);

sys/dev/fdt/rkclock.c

352

uint32_t rk3588_get_pll(struct rkclock_softc *, bus_size_t);

sys/dev/fdt/rkclock.c

353

uint32_t rk3588_get_frequency(void *, uint32_t *);

sys/dev/fdt/rkclock.c

354

int rk3588_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/rkclock.c

355

void rk3588_enable(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

356

void rk3588_reset(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

363

void (*enable)(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

364

uint32_t (*get_frequency)(void *, uint32_t *);

sys/dev/fdt/rkclock.c

365

int (*set_frequency)(void *, uint32_t *, uint32_t);

sys/dev/fdt/rkclock.c

366

int (*set_parent)(void *, uint32_t *, uint32_t *);

sys/dev/fdt/rkclock.c

367

void (*reset)(void *, uint32_t *, int);

sys/dev/fdt/rkclock.c

3730

rk3568_set_pll(struct rkclock_softc *sc, bus_size_t base, uint32_t freq)

sys/dev/fdt/rkclock.c

3732

uint32_t fbdiv, postdiv1, postdiv2, refdiv;

sys/dev/fdt/rkclock.c

3807

uint32_t

sys/dev/fdt/rkclock.c

3808

rk3568_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/rkclock.c

3811

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

3867

rk3568_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/rkclock.c

3870

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

3883

rk3568_set_parent(void *cookie, uint32_t *cells, uint32_t *pcells)

sys/dev/fdt/rkclock.c

3915

rk3568_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

3917

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

3927

rk3568_reset(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

3930

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

3931

uint32_t mask = (1 << (idx % 16));

sys/dev/fdt/rkclock.c

4028

rk3568_pmu_set_pll(struct rkclock_softc *sc, bus_size_t base, uint32_t freq)

sys/dev/fdt/rkclock.c

4030

uint32_t fbdiv, postdiv1, postdiv2, refdiv;

sys/dev/fdt/rkclock.c

4093

uint32_t

sys/dev/fdt/rkclock.c

4094

rk3568_pmu_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/rkclock.c

4097

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

4122

rk3568_pmu_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/rkclock.c

4125

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

4143

rk3568_pmu_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

4145

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

4167

rk3568_pmu_reset(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

4169

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

4309

const uint32_t rk3576_gates[79] = {

sys/dev/fdt/rkclock.c

4329

uint32_t

sys/dev/fdt/rkclock.c

4330

rk3576_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/rkclock.c

4333

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

4354

rk3576_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/rkclock.c

4357

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

4391

rk3576_set_parent(void *cookie, uint32_t *cells, uint32_t *pcells)

sys/dev/fdt/rkclock.c

4399

rk3576_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

4401

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

4411

rk3576_reset(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

4414

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

4415

uint32_t bit, mask, reg;

sys/dev/fdt/rkclock.c

452

uint32_t grf;

sys/dev/fdt/rkclock.c

4931

const uint32_t rk3588_gates[78] = {

sys/dev/fdt/rkclock.c

4956

rk3588_set_pll(struct rkclock_softc *sc, bus_size_t base, uint32_t freq)

sys/dev/fdt/rkclock.c

4958

uint32_t p, m, s, k;

sys/dev/fdt/rkclock.c

5040

uint32_t

sys/dev/fdt/rkclock.c

5044

uint32_t k, m, p, s;

sys/dev/fdt/rkclock.c

5045

uint32_t reg;

sys/dev/fdt/rkclock.c

505

rkclock_lookup(struct rkclock_softc *sc, uint32_t idx)

sys/dev/fdt/rkclock.c

5064

uint32_t

sys/dev/fdt/rkclock.c

5065

rk3588_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/rkclock.c

5068

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

5069

uint32_t freq;

sys/dev/fdt/rkclock.c

5095

rk3588_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/rkclock.c

5098

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

5117

rk3588_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

5119

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

5129

rk3588_reset(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/rkclock.c

5132

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

5133

uint32_t bit, mask, reg;

sys/dev/fdt/rkclock.c

517

uint32_t

sys/dev/fdt/rkclock.c

543

uint32_t

sys/dev/fdt/rkclock.c

545

uint32_t mux, uint32_t freq)

sys/dev/fdt/rkclock.c

547

uint32_t parent_freq, div, div_con, max_div_con;

sys/dev/fdt/rkclock.c

548

uint32_t idx = clk->parents[mux];

sys/dev/fdt/rkclock.c

559

uint32_t

sys/dev/fdt/rkclock.c

561

uint32_t mux, uint32_t freq)

sys/dev/fdt/rkclock.c

563

uint32_t parent_freq, div_con;

sys/dev/fdt/rkclock.c

564

uint32_t idx = clk->parents[mux];

sys/dev/fdt/rkclock.c

571

uint32_t

sys/dev/fdt/rkclock.c

572

rkclock_get_frequency(struct rkclock_softc *sc, uint32_t idx)

sys/dev/fdt/rkclock.c

575

uint32_t reg, mux, div_con;

sys/dev/fdt/rkclock.c

605

rkclock_set_frequency(struct rkclock_softc *sc, uint32_t idx, uint32_t freq)

sys/dev/fdt/rkclock.c

608

uint32_t reg, mux, div_con;

sys/dev/fdt/rkclock.c

609

uint32_t best_freq, best_mux, f;

sys/dev/fdt/rkclock.c

610

uint32_t parent;

sys/dev/fdt/rkclock.c

703

rkclock_set_parent(struct rkclock_softc *sc, uint32_t idx, uint32_t parent)

sys/dev/fdt/rkclock.c

706

uint32_t mux;

sys/dev/fdt/rkclock.c

757

uint32_t idx;

sys/dev/fdt/rkclock.c

767

uint32_t

sys/dev/fdt/rkclock.c

770

uint32_t clkod, clkr, clkf;

sys/dev/fdt/rkclock.c

771

uint32_t reg;

sys/dev/fdt/rkclock.c

785

rk3288_set_pll(struct rkclock_softc *sc, bus_size_t base, uint32_t freq)

sys/dev/fdt/rkclock.c

788

uint32_t no, nr, nf;

sys/dev/fdt/rkclock.c

864

uint32_t

sys/dev/fdt/rkclock.c

865

rk3288_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/rkclock.c

868

uint32_t idx = cells[0];

sys/dev/fdt/rkclock.c

869

uint32_t reg, mux, div_con, aclk_div_con;

sys/dev/fdt/rkclock.c

978

rk3288_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/rkclock.c

981

uint32_t idx = cells[0];

sys/dev/fdt/rkcomphy.c

131

int rkcomphy_rk3528_enable(void *, uint32_t *);

sys/dev/fdt/rkcomphy.c

132

int rkcomphy_rk3568_enable(void *, uint32_t *);

sys/dev/fdt/rkcomphy.c

133

int rkcomphy_rk3588_enable(void *, uint32_t *);

sys/dev/fdt/rkcomphy.c

183

uint32_t reg;

sys/dev/fdt/rkcomphy.c

199

rkcomphy_rk3528_enable(void *cookie, uint32_t *cells)

sys/dev/fdt/rkcomphy.c

204

uint32_t type = cells[0];

sys/dev/fdt/rkcomphy.c

205

uint32_t grf, phy_grf, reg;

sys/dev/fdt/rkcomphy.c

256

uint32_t reg;

sys/dev/fdt/rkcomphy.c

275

rkcomphy_rk3568_enable(void *cookie, uint32_t *cells)

sys/dev/fdt/rkcomphy.c

280

uint32_t type = cells[0];

sys/dev/fdt/rkcomphy.c

281

uint32_t freq, grf, phy_grf, reg;

sys/dev/fdt/rkcomphy.c

414

uint32_t reg;

sys/dev/fdt/rkcomphy.c

428

rkcomphy_rk3588_enable(void *cookie, uint32_t *cells)

sys/dev/fdt/rkcomphy.c

433

uint32_t type = cells[0];

sys/dev/fdt/rkcomphy.c

434

uint32_t freq, grf, phy_grf;

sys/dev/fdt/rkdrm.c

203

void **, int *, int *, uint32_t *);

sys/dev/fdt/rkdrm.c

300

void **cookiep, int *curxp, int *curyp, uint32_t *attrp)

sys/dev/fdt/rkdrm.c

369

uint32_t *ports;

sys/dev/fdt/rkdrm.c

372

uint32_t defattr;

sys/dev/fdt/rkdrm.c

397

for (i = 0; i < portslen / sizeof(uint32_t); i++) {

sys/dev/fdt/rkdrm.h

57

uint32_t (*get_vblank_counter)(void *);

sys/dev/fdt/rkdwhdmi.c

125

uint32_t grf;

sys/dev/fdt/rkdwhdmi.c

126

uint32_t phandle;

sys/dev/fdt/rkdwhdmi.c

199

const uint32_t write_mask = HDMI_LCDC_SEL << 16;

sys/dev/fdt/rkdwhdmi.c

200

const uint32_t write_val = crtc_index == 0 ? HDMI_LCDC_SEL : 0;

sys/dev/fdt/rkemmcphy.c

123

rkemmcphy_enable(void *cookie, uint32_t *cells)

sys/dev/fdt/rkemmcphy.c

126

uint32_t impedance, freqsel, freq, reg;

sys/dev/fdt/rkemmcphy.c

86

int rkemmcphy_enable(void *, uint32_t *);

sys/dev/fdt/rkgpio.c

118

void rkgpio_config_pin(void *, uint32_t *, int);

sys/dev/fdt/rkgpio.c

119

int rkgpio_get_pin(void *, uint32_t *);

sys/dev/fdt/rkgpio.c

120

void rkgpio_set_pin(void *, uint32_t *, int);

sys/dev/fdt/rkgpio.c

144

uint32_t ver_id;

sys/dev/fdt/rkgpio.c

206

rkgpio_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/rkgpio.c

209

uint32_t pin = cells[0];

sys/dev/fdt/rkgpio.c

210

uint32_t reg;

sys/dev/fdt/rkgpio.c

229

rkgpio_get_pin(void *cookie, uint32_t *cells)

sys/dev/fdt/rkgpio.c

232

uint32_t pin = cells[0];

sys/dev/fdt/rkgpio.c

233

uint32_t flags = cells[1];

sys/dev/fdt/rkgpio.c

234

uint32_t reg;

sys/dev/fdt/rkgpio.c

251

rkgpio_set_pin(void *cookie, uint32_t *cells, int val)

sys/dev/fdt/rkgpio.c

254

uint32_t pin = cells[0];

sys/dev/fdt/rkgpio.c

255

uint32_t flags = cells[1];

sys/dev/fdt/rkgpio.c

256

uint32_t reg;

sys/dev/fdt/rkgpio.c

281

uint32_t status, pending;

sys/dev/fdt/rkgpio.c

359

uint32_t bit = (1 << (irqno % 16));

sys/dev/fdt/rkgpio.c

360

uint32_t mask = bit << 16;

sys/dev/fdt/rkgpio.c

421

uint32_t bit = (1 << (ih->ih_irq % 16));

sys/dev/fdt/rkgpio.c

422

uint32_t mask = bit << 16;

sys/dev/fdt/rkgpio.c

488

uint32_t bit = (1 << (ih->ih_irq % 16));

sys/dev/fdt/rkgpio.c

489

uint32_t mask = bit << 16;

sys/dev/fdt/rkgpio.c

506

uint32_t bit = (1 << (ih->ih_irq % 16));

sys/dev/fdt/rkgpio.c

507

uint32_t mask = bit << 16;

sys/dev/fdt/rkiic.c

124

uint32_t clock_speed, bus_speed;

sys/dev/fdt/rkiic.c

125

uint32_t div, divl, divh;

sys/dev/fdt/rkiic.c

126

uint32_t clkdivl, clkdivh;

sys/dev/fdt/rkiic.c

256

*((uint32_t *)&txbuf[i]));

sys/dev/fdt/rkiic.c

278

uint32_t mrxraddr, rxdata;

sys/dev/fdt/rkiic.c

280

uint32_t con;

sys/dev/fdt/rkiic.c

339

uint32_t con;

sys/dev/fdt/rkiic.c

380

uint32_t reg[1];

sys/dev/fdt/rkiis.c

144

int rkiis_set_format(void *, uint32_t, uint32_t, uint32_t);

sys/dev/fdt/rkiis.c

145

int rkiis_set_sysclk(void *, uint32_t);

sys/dev/fdt/rkiis.c

161

uint32_t oe_mask;

sys/dev/fdt/rkiis.c

162

uint32_t oe_shift;

sys/dev/fdt/rkiis.c

163

uint32_t oe_val;

sys/dev/fdt/rkiis.c

174

uint32_t *ch_start;

sys/dev/fdt/rkiis.c

175

uint32_t *ch_end;

sys/dev/fdt/rkiis.c

176

uint32_t *ch_cur;

sys/dev/fdt/rkiis.c

197

uint32_t sc_active;

sys/dev/fdt/rkiis.c

235

uint32_t grf, val;

sys/dev/fdt/rkiis.c

292

uint32_t sr, val;

sys/dev/fdt/rkiis.c

340

rkiis_set_format(void *cookie, uint32_t fmt, uint32_t pol,

sys/dev/fdt/rkiis.c

341

uint32_t clk)

sys/dev/fdt/rkiis.c

344

uint32_t txcr, rxcr, ckr;

sys/dev/fdt/rkiis.c

412

rkiis_set_sysclk(void *cookie, uint32_t rate)

sys/dev/fdt/rkiis.c

441

uint32_t mclk_rate, bclk_rate;

sys/dev/fdt/rkiis.c

442

uint32_t bclk_div, lrck_div;

sys/dev/fdt/rkiis.c

443

uint32_t ckr, txcr, rxcr;

sys/dev/fdt/rkiis.c

532

uint32_t val;

sys/dev/fdt/rkiis.c

570

uint32_t val;

sys/dev/fdt/rkiis.c

601

uint32_t val;

sys/dev/fdt/rkiovd.c

100

uint32_t phandle;

sys/dev/fdt/rkiovd.c

116

rkiovd_rk3568_notify(void *cookie, uint32_t voltage)

sys/dev/fdt/rkiovd.c

120

uint32_t current_voltage;

sys/dev/fdt/rkiovd.c

121

uint32_t vsel0, vsel1;

sys/dev/fdt/rkiovd.c

73

void rkiovd_rk3568_notify(void *, uint32_t);

sys/dev/fdt/rkpcie.c

178

uint32_t status;

sys/dev/fdt/rkpcie.c

196

uint32_t *ep_gpio = NULL;

sys/dev/fdt/rkpcie.c

197

uint32_t bus_range[2];

sys/dev/fdt/rkpcie.c

198

uint32_t status;

sys/dev/fdt/rkpcie.c

199

uint32_t max_link_speed;

sys/dev/fdt/rkpcie.c

400

uint32_t *ranges = NULL;

sys/dev/fdt/rkpcie.c

404

uint32_t type;

sys/dev/fdt/rkpcie.c

416

if (len <= 0 || (len % (7 * sizeof(uint32_t))) != 0)

sys/dev/fdt/rkpcie.c

421

for (i = 0; i < len / sizeof(uint32_t); i += 7) {

sys/dev/fdt/rkpcie.c

670

uint32_t phys[8];

sys/dev/fdt/rkpcie.c

707

uint32_t status;

sys/dev/fdt/rkpciephy.c

110

rk3568_pciephy_enable(void *cookie, uint32_t *cells)

sys/dev/fdt/rkpciephy.c

115

uint32_t data_lanes[2] = { 0, 0 };

sys/dev/fdt/rkpciephy.c

116

uint32_t grf, stat;

sys/dev/fdt/rkpciephy.c

161

rk3588_pciephy_enable(void *cookie, uint32_t *cells)

sys/dev/fdt/rkpciephy.c

166

uint32_t data_lanes[4] = { 1, 1, 1, 1 };

sys/dev/fdt/rkpciephy.c

167

uint32_t grf, reg, stat;

sys/dev/fdt/rkpciephy.c

187

num_lanes /= sizeof(uint32_t);

sys/dev/fdt/rkpciephy.c

80

int rk3568_pciephy_enable(void *, uint32_t *);

sys/dev/fdt/rkpciephy.c

81

int rk3588_pciephy_enable(void *, uint32_t *);

sys/dev/fdt/rkpinctrl.c

1004

rk3568_pull(uint32_t bank, uint32_t idx, uint32_t phandle)

sys/dev/fdt/rkpinctrl.c

1023

rk3568_strength(uint32_t bank, uint32_t idx, uint32_t phandle)

sys/dev/fdt/rkpinctrl.c

1035

rk3568_schmitt(uint32_t bank, uint32_t idx, uint32_t phandle)

sys/dev/fdt/rkpinctrl.c

1131

rk3568_route(struct rkpinctrl_softc *sc, uint32_t *pins)

sys/dev/fdt/rkpinctrl.c

1161

rk3568_pinctrl(uint32_t phandle, void *cookie)

sys/dev/fdt/rkpinctrl.c

1164

uint32_t *pins;

sys/dev/fdt/rkpinctrl.c

1179

for (i = 0; i < len / sizeof(uint32_t); i += 4) {

sys/dev/fdt/rkpinctrl.c

1182

uint32_t bank, idx, mux;

sys/dev/fdt/rkpinctrl.c

1184

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

122

uint32_t val;

sys/dev/fdt/rkpinctrl.c

1269

rk3576_pinctrl(uint32_t phandle, void *cookie)

sys/dev/fdt/rkpinctrl.c

1273

uint32_t *pins;

sys/dev/fdt/rkpinctrl.c

129

uint32_t sc_grf;

sys/dev/fdt/rkpinctrl.c

1290

for (i = 0; i < len / sizeof(uint32_t); i += 4) {

sys/dev/fdt/rkpinctrl.c

1292

uint32_t bank, idx, mux;

sys/dev/fdt/rkpinctrl.c

1294

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

130

uint32_t sc_pmu;

sys/dev/fdt/rkpinctrl.c

1398

rk3588_pull(uint32_t bank, uint32_t idx, uint32_t phandle)

sys/dev/fdt/rkpinctrl.c

1417

rk3588_strength(uint32_t bank, uint32_t idx, uint32_t phandle)

sys/dev/fdt/rkpinctrl.c

1429

rk3588_schmitt(uint32_t bank, uint32_t idx, uint32_t phandle)

sys/dev/fdt/rkpinctrl.c

144

int rk3288_pinctrl(uint32_t, void *);

sys/dev/fdt/rkpinctrl.c

145

int rk3308_pinctrl(uint32_t, void *);

sys/dev/fdt/rkpinctrl.c

1455

rk3588_base(uint32_t bank, uint32_t idx)

sys/dev/fdt/rkpinctrl.c

146

int rk3328_pinctrl(uint32_t, void *);

sys/dev/fdt/rkpinctrl.c

147

int rk3399_pinctrl(uint32_t, void *);

sys/dev/fdt/rkpinctrl.c

1478

rk3588_pinctrl(uint32_t phandle, void *cookie)

sys/dev/fdt/rkpinctrl.c

148

int rk3528_pinctrl(uint32_t, void *);

sys/dev/fdt/rkpinctrl.c

1482

uint32_t *pins;

sys/dev/fdt/rkpinctrl.c

149

int rk3568_pinctrl(uint32_t, void *);

sys/dev/fdt/rkpinctrl.c

1499

for (i = 0; i < len / sizeof(uint32_t); i += 4) {

sys/dev/fdt/rkpinctrl.c

150

int rk3576_pinctrl(uint32_t, void *);

sys/dev/fdt/rkpinctrl.c

1501

uint32_t bank, idx, mux;

sys/dev/fdt/rkpinctrl.c

1503

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

151

int rk3588_pinctrl(uint32_t, void *);

sys/dev/fdt/rkpinctrl.c

153

int rk3588_pull(uint32_t, uint32_t, uint32_t);

sys/dev/fdt/rkpinctrl.c

154

int rk3588_strength(uint32_t, uint32_t, uint32_t);

sys/dev/fdt/rkpinctrl.c

155

int rk3588_schmitt(uint32_t, uint32_t, uint32_t);

sys/dev/fdt/rkpinctrl.c

212

rk3288_pull(uint32_t bank, uint32_t idx, uint32_t phandle)

sys/dev/fdt/rkpinctrl.c

235

rk3288_strength(uint32_t bank, uint32_t idx, uint32_t phandle)

sys/dev/fdt/rkpinctrl.c

262

rk3288_pinctrl(uint32_t phandle, void *cookie)

sys/dev/fdt/rkpinctrl.c

265

uint32_t *pins;

sys/dev/fdt/rkpinctrl.c

280

for (i = 0; i < len / sizeof(uint32_t); i += 4) {

sys/dev/fdt/rkpinctrl.c

283

uint32_t bank, idx, mux;

sys/dev/fdt/rkpinctrl.c

285

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

361

rk3308_pull(uint32_t bank, uint32_t idx, uint32_t phandle)

sys/dev/fdt/rkpinctrl.c

380

rk3308_strength(uint32_t bank, uint32_t idx, uint32_t phandle)

sys/dev/fdt/rkpinctrl.c

403

rk3308_pinctrl(uint32_t phandle, void *cookie)

sys/dev/fdt/rkpinctrl.c

407

uint32_t *pins;

sys/dev/fdt/rkpinctrl.c

424

for (i = 0; i < len / sizeof(uint32_t); i += 4) {

sys/dev/fdt/rkpinctrl.c

426

uint32_t bank, idx, mux;

sys/dev/fdt/rkpinctrl.c

428

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

507

rk3328_pull(uint32_t bank, uint32_t idx, uint32_t phandle)

sys/dev/fdt/rkpinctrl.c

526

rk3328_strength(uint32_t bank, uint32_t idx, uint32_t phandle)

sys/dev/fdt/rkpinctrl.c

549

rk3328_pinctrl(uint32_t phandle, void *cookie)

sys/dev/fdt/rkpinctrl.c

553

uint32_t *pins;

sys/dev/fdt/rkpinctrl.c

570

for (i = 0; i < len / sizeof(uint32_t); i += 4) {

sys/dev/fdt/rkpinctrl.c

572

uint32_t bank, idx, mux;

sys/dev/fdt/rkpinctrl.c

574

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

662

rk3399_pull(uint32_t bank, uint32_t idx, uint32_t phandle)

sys/dev/fdt/rkpinctrl.c

716

rk3399_strength(uint32_t bank, uint32_t idx, uint32_t phandle)

sys/dev/fdt/rkpinctrl.c

741

rk3399_pinctrl(uint32_t phandle, void *cookie)

sys/dev/fdt/rkpinctrl.c

744

uint32_t *pins;

sys/dev/fdt/rkpinctrl.c

759

for (i = 0; i < len / sizeof(uint32_t); i += 4) {

sys/dev/fdt/rkpinctrl.c

762

uint32_t bank, idx, mux;

sys/dev/fdt/rkpinctrl.c

764

uint32_t mask, bits;

sys/dev/fdt/rkpinctrl.c

836

rk3528_pull(uint32_t bank, uint32_t idx, uint32_t phandle)

sys/dev/fdt/rkpinctrl.c

855

rk3528_strength(uint32_t bank, uint32_t idx, uint32_t phandle)

sys/dev/fdt/rkpinctrl.c

867

rk3528_schmitt(uint32_t bank, uint32_t idx, uint32_t phandle)

sys/dev/fdt/rkpinctrl.c

884

rk3528_pinctrl(uint32_t phandle, void *cookie)

sys/dev/fdt/rkpinctrl.c

888

uint32_t *pins;

sys/dev/fdt/rkpinctrl.c

905

for (i = 0; i < len / sizeof(uint32_t); i += 4) {

sys/dev/fdt/rkpinctrl.c

907

uint32_t bank, idx, mux;

sys/dev/fdt/rkpinctrl.c

909

uint32_t mask, bits;

sys/dev/fdt/rkpmic.c

640

uint32_t rkpmic_get_voltage(void *);

sys/dev/fdt/rkpmic.c

641

int rkpmic_set_voltage(void *, uint32_t);

sys/dev/fdt/rkpmic.c

642

int rkpmic_do_set_voltage(struct rkpmic_regulator *, uint32_t, int);

sys/dev/fdt/rkpmic.c

649

uint32_t voltage;

sys/dev/fdt/rkpmic.c

696

uint32_t

sys/dev/fdt/rkpmic.c

702

uint32_t ret = 0;

sys/dev/fdt/rkpmic.c

727

rkpmic_set_voltage(void *cookie, uint32_t voltage)

sys/dev/fdt/rkpmic.c

733

rkpmic_do_set_voltage(struct rkpmic_regulator *rr, uint32_t voltage, int sleep)

sys/dev/fdt/rkpmic.c

736

uint32_t vmin, vmax, volt;

sys/dev/fdt/rkpmic.c

85

uint32_t base, delta;

sys/dev/fdt/rkpwm.c

125

rkpwm_get_state(void *cookie, uint32_t *cells, struct pwm_state *ps)

sys/dev/fdt/rkpwm.c

128

uint32_t idx = cells[0];

sys/dev/fdt/rkpwm.c

148

rkpwm_set_state(void *cookie, uint32_t *cells, struct pwm_state *ps)

sys/dev/fdt/rkpwm.c

151

uint32_t idx = cells[0];

sys/dev/fdt/rkpwm.c

58

uint32_t sc_clkin;

sys/dev/fdt/rkpwm.c

73

int rkpwm_get_state(void *, uint32_t *, struct pwm_state *);

sys/dev/fdt/rkpwm.c

74

int rkpwm_set_state(void *, uint32_t *, struct pwm_state *);

sys/dev/fdt/rkrng.c

236

uint32_t ctl_m = TRNG_CTL_RNG_START | TRNG_CTL_RNG_ENABLE |

sys/dev/fdt/rkrng.c

238

uint32_t ctl_v = TRNG_CTL_RNG_START | TRNG_CTL_RNG_ENABLE |

sys/dev/fdt/rkrng.c

254

uint32_t ctl_m = TRNG_CTL_RNG_START | TRNG_CTL_RNG_ENABLE;

sys/dev/fdt/rkrng.c

262

uint32_t stat;

sys/dev/fdt/rkrng.c

263

uint32_t mask;

sys/dev/fdt/rkspi.c

114

int rkspi_wait_state(struct rkspi_softc *, uint32_t, uint32_t);

sys/dev/fdt/rkspi.c

205

uint32_t ctrlr0;

sys/dev/fdt/rkspi.c

252

rkspi_wait_state(struct rkspi_softc *sc, uint32_t mask, uint32_t value)

sys/dev/fdt/rkspi.c

345

uint32_t reg[1];

sys/dev/fdt/rktcphy.c

129

int rktcphy_enable(void *, uint32_t *);

sys/dev/fdt/rktcphy.c

152

uint32_t grf;

sys/dev/fdt/rktcphy.c

212

uint32_t reg;

sys/dev/fdt/rktcphy.c

236

rktcphy_enable(void *cookie, uint32_t *cells)

sys/dev/fdt/rktcphy.c

239

uint32_t reg;

sys/dev/fdt/rktemp.c

303

int32_t rktemp_get_temperature(void *, uint32_t *);

sys/dev/fdt/rktemp.c

304

int rktemp_set_limit(void *, uint32_t *, uint32_t);

sys/dev/fdt/rktemp.c

325

uint32_t mode, polarity, temp;

sys/dev/fdt/rktemp.c

326

uint32_t auto_con, inter_pd_soc;

sys/dev/fdt/rktemp.c

421

uint32_t gpio_en, cru_en;

sys/dev/fdt/rktemp.c

463

uint32_t int_en;

sys/dev/fdt/rktemp.c

542

uint32_t stat, ch;

sys/dev/fdt/rktemp.c

565

uint32_t grf;

sys/dev/fdt/rktemp.c

687

rktemp_get_temperature(void *cookie, uint32_t *cells)

sys/dev/fdt/rktemp.c

690

uint32_t ch = cells[0];

sys/dev/fdt/rktemp.c

704

rktemp_set_limit(void *cookie, uint32_t *cells, uint32_t temp)

sys/dev/fdt/rktemp.c

707

uint32_t ch = cells[0];

sys/dev/fdt/rkusbdpphy.c

101

uint32_t reg;

sys/dev/fdt/rkusbdpphy.c

144

4 * sizeof(uint32_t))

sys/dev/fdt/rkusbdpphy.c

167

rkusbdpphy_rk3588_enable(void *cookie, uint32_t *cells)

sys/dev/fdt/rkusbdpphy.c

172

uint32_t type = cells[0];

sys/dev/fdt/rkusbdpphy.c

173

uint32_t usb_grf;

sys/dev/fdt/rkusbdpphy.c

275

uint32_t freq, udphy_grf;

sys/dev/fdt/rkusbdpphy.c

84

int rkusbdpphy_rk3588_enable(void *, uint32_t *);

sys/dev/fdt/rkusbphy.c

238

static uint32_t rkusbphy_rd(struct regmap *,

sys/dev/fdt/rkusbphy.c

243

const struct rkusbphy_reg *, uint32_t);

sys/dev/fdt/rkusbphy.c

247

static int rkusbphy_otg_phy_enable(void *, uint32_t *);

sys/dev/fdt/rkusbphy.c

248

static int rkusbphy_host_phy_enable(void *, uint32_t *);

sys/dev/fdt/rkusbphy.c

252

int (*pc_enable)(void *, uint32_t *);

sys/dev/fdt/rkusbphy.c

321

uint32_t grfph;

sys/dev/fdt/rkusbphy.c

372

static uint32_t

sys/dev/fdt/rkusbphy.c

375

uint32_t v;

sys/dev/fdt/rkusbphy.c

392

rkusbphy_wr(struct regmap *rm, const struct rkusbphy_reg *r, uint32_t v)

sys/dev/fdt/rkusbphy.c

44

uint32_t r_mask;

sys/dev/fdt/rkusbphy.c

449

rkusbphy_otg_phy_enable(void *cookie, uint32_t *cells)

sys/dev/fdt/rkusbphy.c

45

uint32_t r_set;

sys/dev/fdt/rkusbphy.c

462

rkusbphy_host_phy_enable(void *cookie, uint32_t *cells)

sys/dev/fdt/rkvop.c

158

enum vop_ep_type, uint32_t);

sys/dev/fdt/rkvop.c

169

void rk3399_vop_set_polarity(struct rkvop_softc *, enum vop_ep_type, uint32_t);

sys/dev/fdt/rkvop.c

251

uint32_t stride, height;

sys/dev/fdt/rkvop.c

297

uint32_t val;

sys/dev/fdt/rkvop.c

335

HWRITE4(sc, VOP_WIN0_YRGB_MST, (uint32_t)paddr);

sys/dev/fdt/rkvop.c

357

uint32_t val;

sys/dev/fdt/rkvop.c

404

uint32_t val;

sys/dev/fdt/rkvop.c

525

uint32_t formats[] = { DRM_FORMAT_ARGB8888 };

sys/dev/fdt/rkvop.c

571

uint32_t val;

sys/dev/fdt/rkvop.c

579

rk3399_vop_set_polarity(struct rkvop_softc *sc, enum vop_ep_type ep_type, uint32_t pol)

sys/dev/fdt/rkvop.c

581

uint32_t mask, val;

sys/dev/fdt/scmi.c

100

uint32_t pl_perf;

sys/dev/fdt/scmi.c

101

uint32_t pl_cost;

sys/dev/fdt/scmi.c

102

uint32_t pl_ifreq;

sys/dev/fdt/scmi.c

107

uint32_t pd_perf_max;

sys/dev/fdt/scmi.c

108

uint32_t pd_perf_min;

sys/dev/fdt/scmi.c

123

uint32_t sc_smc_id;

sys/dev/fdt/scmi.c

203

uint32_t version;

sys/dev/fdt/scmi.c

204

uint32_t phandle;

sys/dev/fdt/scmi.c

238

shmem->length = sizeof(uint32_t);

sys/dev/fdt/scmi.c

260

uint32_t *shmems;

sys/dev/fdt/scmi.c

262

uint32_t version;

sys/dev/fdt/scmi.c

270

if (len != 4 * sizeof(uint32_t)) {

sys/dev/fdt/scmi.c

276

if (len != 2 * sizeof(uint32_t)) {

sys/dev/fdt/scmi.c

322

sc->sc_shmem_tx->length = sizeof(uint32_t);

sys/dev/fdt/scmi.c

38

uint32_t reserved1;

sys/dev/fdt/scmi.c

39

uint32_t channel_status;

sys/dev/fdt/scmi.c

400

void scmi_clock_enable(void *, uint32_t *, int);

sys/dev/fdt/scmi.c

401

uint32_t scmi_clock_get_frequency(void *, uint32_t *);

sys/dev/fdt/scmi.c

402

int scmi_clock_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/scmi.c

412

shmem->length = sizeof(uint32_t);

sys/dev/fdt/scmi.c

42

uint32_t reserved2;

sys/dev/fdt/scmi.c

43

uint32_t reserved3;

sys/dev/fdt/scmi.c

430

scmi_clock_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/scmi.c

434

uint32_t idx = cells[0];

sys/dev/fdt/scmi.c

437

shmem->length = 3 * sizeof(uint32_t);

sys/dev/fdt/scmi.c

44

uint32_t channel_flags;

sys/dev/fdt/scmi.c

443

uint32_t

sys/dev/fdt/scmi.c

444

scmi_clock_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/scmi.c

448

uint32_t idx = cells[0];

sys/dev/fdt/scmi.c

45

uint32_t length;

sys/dev/fdt/scmi.c

452

shmem->length = 2 * sizeof(uint32_t);

sys/dev/fdt/scmi.c

46

uint32_t message_header;

sys/dev/fdt/scmi.c

464

scmi_clock_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/scmi.c

468

uint32_t idx = cells[0];

sys/dev/fdt/scmi.c

47

uint32_t message_payload[];

sys/dev/fdt/scmi.c

472

shmem->length = 5 * sizeof(uint32_t);

sys/dev/fdt/scmi.c

499

uint32_t version;

sys/dev/fdt/scmi.c

503

sc->sc_shmem_tx->length = sizeof(uint32_t);

sys/dev/fdt/scmi.c

519

shmem->length = sizeof(uint32_t);

sys/dev/fdt/scmi.c

546

shmem->length = 2 * sizeof(uint32_t);

sys/dev/fdt/scmi.c

591

shmem->length = sizeof(uint32_t) * 3;

sys/dev/fdt/scmi.c

639

shmem->length = sizeof(uint32_t) * 2;

sys/dev/fdt/scmi.c

658

shmem->length = sizeof(uint32_t) * 3;

sys/dev/fdt/scmi.c

83

uint32_t pe_perf;

sys/dev/fdt/scmi.c

84

uint32_t pe_cost;

sys/dev/fdt/scmi.c

87

uint32_t pe_ifreq;

sys/dev/fdt/scmi.c

88

uint32_t pe_lindex;

sys/dev/fdt/scmi.c

94

uint32_t protocol_id, uint32_t message_id)

sys/dev/fdt/sdhc_fdt.c

104

uint32_t sc_znr;

sys/dev/fdt/sdhc_fdt.c

105

uint32_t sc_zpr;

sys/dev/fdt/sdhc_fdt.c

121

uint32_t sdhc_fdt_get_frequency(void *, uint32_t *);

sys/dev/fdt/sdhc_fdt.c

147

uint32_t reg, phandle, freq;

sys/dev/fdt/sdhc_fdt.c

361

uint32_t

sys/dev/fdt/sdhc_fdt.c

362

sdhc_fdt_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/sdhc_fdt.c

373

uint32_t reg;

sys/dev/fdt/sdhc_fdt.c

97

uint32_t sc_gpio[3];

sys/dev/fdt/sdhc_fdt.c

98

uint32_t sc_vmmc;

sys/dev/fdt/sdhc_fdt.c

99

uint32_t sc_vqmmc;

sys/dev/fdt/sfp.c

121

sfp_get_gpio(struct sfp_softc *sc, const char *name, uint32_t **gpio)

sys/dev/fdt/sfp.c

39

uint32_t *sc_mod_def0_gpio;

sys/dev/fdt/sfp.c

41

uint32_t *sc_tx_disable_gpio;

sys/dev/fdt/sfp.c

51

int sfp_get_gpio(struct sfp_softc *, const char *, uint32_t **);

sys/dev/fdt/simpleamp.c

44

uint32_t *sc_gpio;

sys/dev/fdt/simpleamp.c

46

uint32_t sc_vcc;

sys/dev/fdt/simpleaudio.c

121

uint32_t fmt, pol, clk;

sys/dev/fdt/simpleaudio.c

122

uint32_t *auxdevs;

sys/dev/fdt/simpleaudio.c

188

if (len % sizeof(uint32_t) != 0)

sys/dev/fdt/simpleaudio.c

195

sc->sc_dai_naux = len / sizeof(uint32_t);

sys/dev/fdt/simpleaudio.c

211

simpleaudio_set_format(struct simpleaudio_softc *sc, uint32_t fmt, uint32_t pol,

sys/dev/fdt/simpleaudio.c

212

uint32_t clk)

sys/dev/fdt/simpleaudio.c

298

uint32_t rate;

sys/dev/fdt/simpleaudio.c

37

uint32_t sc_mclk_fs;

sys/dev/fdt/simpleaudio.c

48

void simpleaudio_set_format(struct simpleaudio_softc *, uint32_t,

sys/dev/fdt/simpleaudio.c

49

uint32_t, uint32_t);

sys/dev/fdt/simplefb.c

140

uint32_t defattr;

sys/dev/fdt/simplefb.c

316

void **cookiep, int *curxp, int *curyp, uint32_t *attrp)

sys/dev/fdt/simplefb.c

341

uint32_t defattr = 0;

sys/dev/fdt/simplefb.c

99

void **, int *, int *, uint32_t *);

sys/dev/fdt/simplepanel.c

86

uint32_t power_supply;

sys/dev/fdt/simplepanel.c

87

uint32_t *gpios;

sys/dev/fdt/sncodec.c

130

uint32_t *sdz_gpio;

sys/dev/fdt/sncodec.c

192

sncodec_set_format(void *cookie, uint32_t fmt, uint32_t pol,

sys/dev/fdt/sncodec.c

193

uint32_t clk)

sys/dev/fdt/sncodec.c

95

int sncodec_set_format(void *, uint32_t, uint32_t, uint32_t);

sys/dev/fdt/ssdfb.c

123

void ssdfb_partial(struct ssdfb_softc *, uint32_t, uint32_t,

sys/dev/fdt/ssdfb.c

124

uint32_t, uint32_t);

sys/dev/fdt/ssdfb.c

131

int *, int *, uint32_t *);

sys/dev/fdt/ssdfb.c

138

int ssdfb_putchar(void *, int, int, u_int, uint32_t);

sys/dev/fdt/ssdfb.c

140

int ssdfb_erasecols(void *, int, int, int, uint32_t);

sys/dev/fdt/ssdfb.c

142

int ssdfb_eraserows(void *, int, int, uint32_t);

sys/dev/fdt/ssdfb.c

280

uint32_t *gpio;

sys/dev/fdt/ssdfb.c

476

ssdfb_partial(struct ssdfb_softc *sc, uint32_t x1, uint32_t x2,

sys/dev/fdt/ssdfb.c

477

uint32_t y1, uint32_t y2)

sys/dev/fdt/ssdfb.c

480

uint32_t off, width, height;

sys/dev/fdt/ssdfb.c

700

void **cookiep, int *curxp, int *curyp, uint32_t *attrp)

sys/dev/fdt/ssdfb.c

746

ssdfb_putchar(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/fdt/ssdfb.c

776

ssdfb_erasecols(void *cookie, int row, int col, int num, uint32_t attr)

sys/dev/fdt/ssdfb.c

804

ssdfb_eraserows(void *cookie, int row, int num, uint32_t attr)

sys/dev/fdt/ssdfb.c

93

uint32_t *sc_gpio;

sys/dev/fdt/sxiccmu.c

100

int sxiccmu_a64_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);

sys/dev/fdt/sxiccmu.c

1004

uint32_t

sys/dev/fdt/sxiccmu.c

1005

sxiccmu_a10s_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)

sys/dev/fdt/sxiccmu.c

1007

uint32_t parent;

sys/dev/fdt/sxiccmu.c

1008

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

1009

uint32_t k, m, n, p;

sys/dev/fdt/sxiccmu.c

101

uint32_t sxiccmu_a80_get_frequency(struct sxiccmu_softc *, uint32_t);

sys/dev/fdt/sxiccmu.c

102

int sxiccmu_a80_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);

sys/dev/fdt/sxiccmu.c

103

uint32_t sxiccmu_d1_get_frequency(struct sxiccmu_softc *, uint32_t);

sys/dev/fdt/sxiccmu.c

104

int sxiccmu_d1_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);

sys/dev/fdt/sxiccmu.c

105

uint32_t sxiccmu_h3_get_frequency(struct sxiccmu_softc *, uint32_t);

sys/dev/fdt/sxiccmu.c

106

int sxiccmu_h3_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);

sys/dev/fdt/sxiccmu.c

107

uint32_t sxiccmu_h3_r_get_frequency(struct sxiccmu_softc *, uint32_t);

sys/dev/fdt/sxiccmu.c

1072

uint32_t

sys/dev/fdt/sxiccmu.c

1073

sxiccmu_a23_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)

sys/dev/fdt/sxiccmu.c

1075

uint32_t parent;

sys/dev/fdt/sxiccmu.c

1076

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

108

uint32_t sxiccmu_h6_get_frequency(struct sxiccmu_softc *, uint32_t);

sys/dev/fdt/sxiccmu.c

109

int sxiccmu_h6_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);

sys/dev/fdt/sxiccmu.c

110

uint32_t sxiccmu_h6_r_get_frequency(struct sxiccmu_softc *, uint32_t);

sys/dev/fdt/sxiccmu.c

111

uint32_t sxiccmu_h616_get_frequency(struct sxiccmu_softc *, uint32_t);

sys/dev/fdt/sxiccmu.c

112

int sxiccmu_h616_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);

sys/dev/fdt/sxiccmu.c

113

uint32_t sxiccmu_h616_r_get_frequency(struct sxiccmu_softc *, uint32_t);

sys/dev/fdt/sxiccmu.c

1134

uint32_t

sys/dev/fdt/sxiccmu.c

1135

sxiccmu_a64_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)

sys/dev/fdt/sxiccmu.c

1137

uint32_t parent;

sys/dev/fdt/sxiccmu.c

1138

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

1139

uint32_t k, m, n, p;

sys/dev/fdt/sxiccmu.c

114

uint32_t sxiccmu_r40_get_frequency(struct sxiccmu_softc *, uint32_t);

sys/dev/fdt/sxiccmu.c

115

int sxiccmu_r40_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);

sys/dev/fdt/sxiccmu.c

116

uint32_t sxiccmu_v3s_get_frequency(struct sxiccmu_softc *, uint32_t);

sys/dev/fdt/sxiccmu.c

117

int sxiccmu_v3s_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);

sys/dev/fdt/sxiccmu.c

118

uint32_t sxiccmu_nop_get_frequency(struct sxiccmu_softc *, uint32_t);

sys/dev/fdt/sxiccmu.c

119

int sxiccmu_nop_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);

sys/dev/fdt/sxiccmu.c

1225

uint32_t

sys/dev/fdt/sxiccmu.c

1226

sxiccmu_a80_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)

sys/dev/fdt/sxiccmu.c

1228

uint32_t parent;

sys/dev/fdt/sxiccmu.c

1229

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

1272

uint32_t

sys/dev/fdt/sxiccmu.c

1273

sxiccmu_d1_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)

sys/dev/fdt/sxiccmu.c

1275

uint32_t parent;

sys/dev/fdt/sxiccmu.c

1276

uint32_t reg, freq;

sys/dev/fdt/sxiccmu.c

1277

uint32_t m, n;

sys/dev/fdt/sxiccmu.c

1344

uint32_t

sys/dev/fdt/sxiccmu.c

1345

sxiccmu_h3_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)

sys/dev/fdt/sxiccmu.c

1347

uint32_t parent;

sys/dev/fdt/sxiccmu.c

1348

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

1349

uint32_t k, m, n, p;

sys/dev/fdt/sxiccmu.c

1438

uint32_t

sys/dev/fdt/sxiccmu.c

1439

sxiccmu_h3_r_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)

sys/dev/fdt/sxiccmu.c

1441

uint32_t parent;

sys/dev/fdt/sxiccmu.c

1442

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

1443

uint32_t freq;

sys/dev/fdt/sxiccmu.c

1480

uint32_t

sys/dev/fdt/sxiccmu.c

1481

sxiccmu_h6_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)

sys/dev/fdt/sxiccmu.c

1483

uint32_t reg, m, n;

sys/dev/fdt/sxiccmu.c

1484

uint32_t freq;

sys/dev/fdt/sxiccmu.c

1508

uint32_t

sys/dev/fdt/sxiccmu.c

1509

sxiccmu_h6_r_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)

sys/dev/fdt/sxiccmu.c

1526

uint32_t

sys/dev/fdt/sxiccmu.c

1527

sxiccmu_h616_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)

sys/dev/fdt/sxiccmu.c

1529

uint32_t reg, m, n;

sys/dev/fdt/sxiccmu.c

1530

uint32_t freq;

sys/dev/fdt/sxiccmu.c

1554

uint32_t

sys/dev/fdt/sxiccmu.c

1555

sxiccmu_h616_r_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)

sys/dev/fdt/sxiccmu.c

1567

uint32_t

sys/dev/fdt/sxiccmu.c

1568

sxiccmu_r40_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)

sys/dev/fdt/sxiccmu.c

1570

uint32_t parent;

sys/dev/fdt/sxiccmu.c

1571

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

1611

uint32_t

sys/dev/fdt/sxiccmu.c

1612

sxiccmu_v3s_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)

sys/dev/fdt/sxiccmu.c

1614

uint32_t parent;

sys/dev/fdt/sxiccmu.c

1615

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

1670

uint32_t

sys/dev/fdt/sxiccmu.c

1671

sxiccmu_nop_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)

sys/dev/fdt/sxiccmu.c

1678

sxiccmu_ccu_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/sxiccmu.c

1681

uint32_t idx = cells[0];

sys/dev/fdt/sxiccmu.c

1687

sxiccmu_a10_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)

sys/dev/fdt/sxiccmu.c

1690

uint32_t parent, parent_freq;

sys/dev/fdt/sxiccmu.c

1691

uint32_t reg;

sys/dev/fdt/sxiccmu.c

1747

sxiccmu_a10s_set_frequency(struct sxiccmu_softc *sc, uint32_t idx,

sys/dev/fdt/sxiccmu.c

1748

uint32_t freq)

sys/dev/fdt/sxiccmu.c

1751

uint32_t parent, parent_freq;

sys/dev/fdt/sxiccmu.c

1752

uint32_t reg;

sys/dev/fdt/sxiccmu.c

1807

sxiccmu_a23_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)

sys/dev/fdt/sxiccmu.c

1810

uint32_t parent, parent_freq;

sys/dev/fdt/sxiccmu.c

1829

sxiccmu_a64_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)

sys/dev/fdt/sxiccmu.c

1832

uint32_t parent, parent_freq;

sys/dev/fdt/sxiccmu.c

1833

uint32_t reg;

sys/dev/fdt/sxiccmu.c

1892

sxiccmu_a80_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)

sys/dev/fdt/sxiccmu.c

1895

uint32_t parent, parent_freq;

sys/dev/fdt/sxiccmu.c

1926

uint32_t freq)

sys/dev/fdt/sxiccmu.c

1928

uint32_t parent_freq;

sys/dev/fdt/sxiccmu.c

1929

uint32_t reg, m, n;

sys/dev/fdt/sxiccmu.c

1930

uint32_t clk_src;

sys/dev/fdt/sxiccmu.c

1968

sxiccmu_d1_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)

sys/dev/fdt/sxiccmu.c

1984

sxiccmu_h3_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)

sys/dev/fdt/sxiccmu.c

1987

uint32_t parent, parent_freq;

sys/dev/fdt/sxiccmu.c

1988

uint32_t reg, lock_time;

sys/dev/fdt/sxiccmu.c

2070

uint32_t freq, uint32_t parent_freq)

sys/dev/fdt/sxiccmu.c

2072

uint32_t reg, m, n;

sys/dev/fdt/sxiccmu.c

2073

uint32_t clk_src;

sys/dev/fdt/sxiccmu.c

2109

sxiccmu_h6_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)

sys/dev/fdt/sxiccmu.c

2111

uint32_t parent_freq;

sys/dev/fdt/sxiccmu.c

2136

sxiccmu_h616_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)

sys/dev/fdt/sxiccmu.c

2138

uint32_t parent_freq;

sys/dev/fdt/sxiccmu.c

2159

sxiccmu_r40_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)

sys/dev/fdt/sxiccmu.c

2162

uint32_t parent, parent_freq;

sys/dev/fdt/sxiccmu.c

2182

sxiccmu_v3s_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)

sys/dev/fdt/sxiccmu.c

2185

uint32_t parent, parent_freq;

sys/dev/fdt/sxiccmu.c

2204

sxiccmu_nop_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)

sys/dev/fdt/sxiccmu.c

2211

sxiccmu_ccu_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/sxiccmu.c

2214

uint32_t idx = cells[0];

sys/dev/fdt/sxiccmu.c

2239

sxiccmu_ccu_reset(void *cookie, uint32_t *cells, int assert)

sys/dev/fdt/sxiccmu.c

2242

uint32_t idx = cells[0];

sys/dev/fdt/sxiccmu.c

362

uint32_t (*get_frequency)(void *, uint32_t *);

sys/dev/fdt/sxiccmu.c

363

int (*set_frequency)(void *, uint32_t *, uint32_t);

sys/dev/fdt/sxiccmu.c

364

void (*enable)(void *, uint32_t *, int);

sys/dev/fdt/sxiccmu.c

365

void (*reset)(void *, uint32_t *, int);

sys/dev/fdt/sxiccmu.c

369

uint32_t sxiccmu_gen_get_frequency(void *, uint32_t *);

sys/dev/fdt/sxiccmu.c

370

uint32_t sxiccmu_osc_get_frequency(void *, uint32_t *);

sys/dev/fdt/sxiccmu.c

371

uint32_t sxiccmu_pll6_get_frequency(void *, uint32_t *);

sys/dev/fdt/sxiccmu.c

372

void sxiccmu_pll6_enable(void *, uint32_t *, int);

sys/dev/fdt/sxiccmu.c

373

uint32_t sxiccmu_apb1_get_frequency(void *, uint32_t *);

sys/dev/fdt/sxiccmu.c

374

uint32_t sxiccmu_cpus_get_frequency(void *, uint32_t *);

sys/dev/fdt/sxiccmu.c

375

uint32_t sxiccmu_apbs_get_frequency(void *, uint32_t *);

sys/dev/fdt/sxiccmu.c

376

int sxiccmu_gmac_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/sxiccmu.c

377

int sxiccmu_mmc_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/sxiccmu.c

378

void sxiccmu_mmc_enable(void *, uint32_t *, int);

sys/dev/fdt/sxiccmu.c

379

void sxiccmu_gate_enable(void *, uint32_t *, int);

sys/dev/fdt/sxiccmu.c

380

void sxiccmu_reset(void *, uint32_t *, int);

sys/dev/fdt/sxiccmu.c

584

uint32_t reg[2];

sys/dev/fdt/sxiccmu.c

630

uint32_t

sys/dev/fdt/sxiccmu.c

631

sxiccmu_gen_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/sxiccmu.c

638

uint32_t

sys/dev/fdt/sxiccmu.c

639

sxiccmu_osc_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/sxiccmu.c

659

uint32_t

sys/dev/fdt/sxiccmu.c

660

sxiccmu_pll6_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/sxiccmu.c

663

uint32_t reg, k, m, n, freq;

sys/dev/fdt/sxiccmu.c

664

uint32_t idx = cells[0];

sys/dev/fdt/sxiccmu.c

688

sxiccmu_pll6_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/sxiccmu.c

69

uint32_t (*sc_get_frequency)(struct sxiccmu_softc *,

sys/dev/fdt/sxiccmu.c

691

uint32_t idx = cells[0];

sys/dev/fdt/sxiccmu.c

692

uint32_t reg;

sys/dev/fdt/sxiccmu.c

70

uint32_t);

sys/dev/fdt/sxiccmu.c

719

uint32_t

sys/dev/fdt/sxiccmu.c

72

uint32_t, uint32_t);

sys/dev/fdt/sxiccmu.c

720

sxiccmu_apb1_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/sxiccmu.c

723

uint32_t reg, m, n, freq;

sys/dev/fdt/sxiccmu.c

739

uint32_t

sys/dev/fdt/sxiccmu.c

740

sxiccmu_cpus_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/sxiccmu.c

743

uint32_t reg, post_div, clk_ratio, freq;

sys/dev/fdt/sxiccmu.c

757

uint32_t

sys/dev/fdt/sxiccmu.c

758

sxiccmu_apbs_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/sxiccmu.c

761

uint32_t reg, freq;

sys/dev/fdt/sxiccmu.c

775

sxiccmu_gmac_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/sxiccmu.c

806

sxiccmu_mmc_do_set_frequency(struct sxiccmu_clock *sc, uint32_t freq,

sys/dev/fdt/sxiccmu.c

807

uint32_t parent_freq)

sys/dev/fdt/sxiccmu.c

809

uint32_t reg, m, n;

sys/dev/fdt/sxiccmu.c

810

uint32_t clk_src;

sys/dev/fdt/sxiccmu.c

846

sxiccmu_mmc_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)

sys/dev/fdt/sxiccmu.c

849

uint32_t parent_freq;

sys/dev/fdt/sxiccmu.c

859

sxiccmu_mmc_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/sxiccmu.c

873

sxiccmu_gate_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/sxiccmu.c

88

uint32_t sxiccmu_ccu_get_frequency(void *, uint32_t *);

sys/dev/fdt/sxiccmu.c

889

sxiccmu_reset(void *cookie, uint32_t *cells, int assert)

sys/dev/fdt/sxiccmu.c

89

int sxiccmu_ccu_set_frequency(void *, uint32_t *, uint32_t);

sys/dev/fdt/sxiccmu.c

90

void sxiccmu_ccu_enable(void *, uint32_t *, int);

sys/dev/fdt/sxiccmu.c

907

uint32_t

sys/dev/fdt/sxiccmu.c

908

sxiccmu_ccu_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/sxiccmu.c

91

void sxiccmu_ccu_reset(void *, uint32_t *, int);

sys/dev/fdt/sxiccmu.c

911

uint32_t idx = cells[0];

sys/dev/fdt/sxiccmu.c

912

uint32_t parent;

sys/dev/fdt/sxiccmu.c

93

uint32_t sxiccmu_a10_get_frequency(struct sxiccmu_softc *, uint32_t);

sys/dev/fdt/sxiccmu.c

94

int sxiccmu_a10_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);

sys/dev/fdt/sxiccmu.c

945

uint32_t

sys/dev/fdt/sxiccmu.c

946

sxiccmu_a10_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)

sys/dev/fdt/sxiccmu.c

948

uint32_t parent;

sys/dev/fdt/sxiccmu.c

949

uint32_t reg, div;

sys/dev/fdt/sxiccmu.c

95

uint32_t sxiccmu_a10s_get_frequency(struct sxiccmu_softc *, uint32_t);

sys/dev/fdt/sxiccmu.c

950

uint32_t k, m, n, p;

sys/dev/fdt/sxiccmu.c

96

int sxiccmu_a10s_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);

sys/dev/fdt/sxiccmu.c

97

uint32_t sxiccmu_a23_get_frequency(struct sxiccmu_softc *, uint32_t);

sys/dev/fdt/sxiccmu.c

98

int sxiccmu_a23_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);

sys/dev/fdt/sxiccmu.c

99

uint32_t sxiccmu_a64_get_frequency(struct sxiccmu_softc *, uint32_t);

sys/dev/fdt/sxidog.c

58

uint32_t sc_key;

sys/dev/fdt/sximmc.c

1103

sximmc_pwrseq_pre(uint32_t phandle)

sys/dev/fdt/sximmc.c

1105

uint32_t *gpios, *gpio;

sys/dev/fdt/sximmc.c

1128

while (gpio && gpio < gpios + (len / sizeof(uint32_t))) {

sys/dev/fdt/sximmc.c

1138

sximmc_pwrseq_post(uint32_t phandle)

sys/dev/fdt/sximmc.c

1140

uint32_t *gpios, *gpio;

sys/dev/fdt/sximmc.c

1159

while (gpio && gpio < gpios + (len / sizeof(uint32_t))) {

sys/dev/fdt/sximmc.c

190

uint32_t dma_config;

sys/dev/fdt/sximmc.c

198

uint32_t dma_buf_size;

sys/dev/fdt/sximmc.c

199

uint32_t dma_buf_addr;

sys/dev/fdt/sximmc.c

200

uint32_t dma_next;

sys/dev/fdt/sximmc.c

214

uint32_t sximmc_host_ocr(sdmmc_chipset_handle_t);

sys/dev/fdt/sximmc.c

217

int sximmc_bus_power(sdmmc_chipset_handle_t, uint32_t);

sys/dev/fdt/sximmc.c

224

void sximmc_pwrseq_pre(uint32_t);

sys/dev/fdt/sximmc.c

225

void sximmc_pwrseq_post(uint32_t);

sys/dev/fdt/sximmc.c

254

uint32_t sc_fifo_reg;

sys/dev/fdt/sximmc.c

255

uint32_t sc_dma_ftrglevel;

sys/dev/fdt/sximmc.c

265

uint32_t sc_intr_rint;

sys/dev/fdt/sximmc.c

266

uint32_t sc_intr_mint;

sys/dev/fdt/sximmc.c

267

uint32_t sc_idma_idst;

sys/dev/fdt/sximmc.c

269

uint32_t sc_gpio[4];

sys/dev/fdt/sximmc.c

270

uint32_t sc_vmmc;

sys/dev/fdt/sximmc.c

271

uint32_t sc_vqmmc;

sys/dev/fdt/sximmc.c

272

uint32_t sc_pwrseq;

sys/dev/fdt/sximmc.c

273

uint32_t sc_vdd;

sys/dev/fdt/sximmc.c

484

uint32_t idst, rint, mint;

sys/dev/fdt/sximmc.c

511

uint32_t imask;

sys/dev/fdt/sximmc.c

527

uint32_t imask;

sys/dev/fdt/sximmc.c

541

uint32_t imask;

sys/dev/fdt/sximmc.c

550

sximmc_wait_rint(struct sximmc_softc *sc, uint32_t mask, int timeout)

sys/dev/fdt/sximmc.c

634

uint32_t

sys/dev/fdt/sximmc.c

672

sximmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)

sys/dev/fdt/sximmc.c

675

uint32_t vdd = 0;

sys/dev/fdt/sximmc.c

702

uint32_t cmd;

sys/dev/fdt/sximmc.c

742

uint32_t clkcr;

sys/dev/fdt/sximmc.c

800

uint32_t bit = (cmd->c_flags & SCF_CMD_READ) ?

sys/dev/fdt/sximmc.c

804

uint32_t status = MMC_READ(sc, SXIMMC_STATUS);

sys/dev/fdt/sximmc.c

823

*(uint32_t *)datap = MMC_READ(sc, sc->sc_fifo_reg);

sys/dev/fdt/sximmc.c

825

MMC_WRITE(sc, sc->sc_fifo_reg, *(uint32_t *)datap);

sys/dev/fdt/sximmc.c

832

uint32_t rv = MMC_READ(sc, sc->sc_fifo_reg);

sys/dev/fdt/sximmc.c

838

uint32_t rv = *datap++;

sys/dev/fdt/sximmc.c

854

uint32_t val;

sys/dev/fdt/sximmc.c

929

uint32_t cmdval = SXIMMC_CMD_START;

sys/dev/fdt/sxipio.c

118

int sxipio_pinctrl(uint32_t, void *);

sys/dev/fdt/sxipio.c

119

void sxipio_config_pin(void *, uint32_t *, int);

sys/dev/fdt/sxipio.c

120

int sxipio_get_pin(void *, uint32_t *);

sys/dev/fdt/sxipio.c

121

void sxipio_set_pin(void *, uint32_t *, int);

sys/dev/fdt/sxipio.c

122

void sxipio_a80_bias_cfg(struct sxipio_softc *, int, uint32_t);

sys/dev/fdt/sxipio.c

309

sxipio_pinctrl(uint32_t phandle, void *cookie)

sys/dev/fdt/sxipio.c

315

uint32_t supply;

sys/dev/fdt/sxipio.c

404

sxipio_config_pin(void *cookie, uint32_t *cells, int config)

sys/dev/fdt/sxipio.c

407

uint32_t port = cells[0];

sys/dev/fdt/sxipio.c

408

uint32_t pin = cells[1];

sys/dev/fdt/sxipio.c

420

sxipio_get_pin(void *cookie, uint32_t *cells)

sys/dev/fdt/sxipio.c

423

uint32_t port = cells[0];

sys/dev/fdt/sxipio.c

424

uint32_t pin = cells[1];

sys/dev/fdt/sxipio.c

425

uint32_t flags = cells[2];

sys/dev/fdt/sxipio.c

426

uint32_t reg;

sys/dev/fdt/sxipio.c

441

sxipio_set_pin(void *cookie, uint32_t *cells, int val)

sys/dev/fdt/sxipio.c

444

uint32_t port = cells[0];

sys/dev/fdt/sxipio.c

445

uint32_t pin = cells[1];

sys/dev/fdt/sxipio.c

446

uint32_t flags = cells[2];

sys/dev/fdt/sxipio.c

447

uint32_t reg;

sys/dev/fdt/sxipio.c

463

sxipio_a80_bias_cfg(struct sxipio_softc *sc, int port, uint32_t supply)

sys/dev/fdt/sxipio.c

465

uint32_t voltage;

sys/dev/fdt/sxipio.c

466

uint32_t bias;

sys/dev/fdt/sxipio.c

501

uint32_t cells[3];

sys/dev/fdt/sxipio.c

514

uint32_t cells[3];

sys/dev/fdt/sxipio.c

527

uint32_t cells[3];

sys/dev/fdt/sxipio.c

544

uint32_t reg;

sys/dev/fdt/sxipio.c

83

int, uint32_t);

sys/dev/fdt/sxipwm.c

141

sxipwm_get_state(void *cookie, uint32_t *cells, struct pwm_state *ps)

sys/dev/fdt/sxipwm.c

144

uint32_t idx = cells[0];

sys/dev/fdt/sxipwm.c

145

uint32_t ctrl, ch_period;

sys/dev/fdt/sxipwm.c

181

sxipwm_set_state(void *cookie, uint32_t *cells, struct pwm_state *ps)

sys/dev/fdt/sxipwm.c

184

uint32_t idx = cells[0];

sys/dev/fdt/sxipwm.c

186

uint32_t reg;

sys/dev/fdt/sxipwm.c

51

uint32_t divider;

sys/dev/fdt/sxipwm.c

75

uint32_t sc_clkin;

sys/dev/fdt/sxipwm.c

90

int sxipwm_get_state(void *, uint32_t *, struct pwm_state *);

sys/dev/fdt/sxipwm.c

91

int sxipwm_set_state(void *, uint32_t *, struct pwm_state *);

sys/dev/fdt/sxirsb.c

109

uint32_t reg;

sys/dev/fdt/sxirsb.c

175

uint32_t freq, parent_freq, div, odly;

sys/dev/fdt/sxirsb.c

176

uint32_t reg;

sys/dev/fdt/sxirtc.c

170

uint32_t

sys/dev/fdt/sxirtc.c

171

sxirtc_get_frequency(void *cookie, uint32_t *cells)

sys/dev/fdt/sxirtc.c

174

uint32_t idx = cells[0];

sys/dev/fdt/sxirtc.c

189

sxirtc_enable(void *cookie, uint32_t *cells, int on)

sys/dev/fdt/sxirtc.c

192

uint32_t idx = cells[0];

sys/dev/fdt/sxirtc.c

216

uint32_t reg;

sys/dev/fdt/sxirtc.c

58

uint32_t base_year;

sys/dev/fdt/sxirtc.c

59

uint32_t year_mask;

sys/dev/fdt/sxirtc.c

60

uint32_t leap_shift;

sys/dev/fdt/sxirtc.c

75

uint32_t sxirtc_get_frequency(void *, uint32_t *);

sys/dev/fdt/sxirtc.c

76

void sxirtc_enable(void *, uint32_t *, int);

sys/dev/fdt/sxisid.c

129

uint32_t val;

sys/dev/fdt/sxisid.c

85

uint32_t sid[4];

sys/dev/fdt/sxitemp.c

101

int32_t sxitemp_get_temperature(void *, uint32_t *);

sys/dev/fdt/sxitemp.c

120

uint32_t enable, irq;

sys/dev/fdt/sxitemp.c

220

uint32_t calib[2];

sys/dev/fdt/sxitemp.c

244

uint32_t cell, stat;

sys/dev/fdt/sxitemp.c

312

uint32_t data;

sys/dev/fdt/sxitemp.c

334

sxitemp_get_temperature(void *cookie, uint32_t *cells)

sys/dev/fdt/sxitemp.c

337

uint32_t idx = cells[0];

sys/dev/fdt/sxitemp.c

338

uint32_t data;

sys/dev/fdt/sxits.c

142

uint32_t data, temp;

sys/dev/fdt/sxits.c

156

sxits_get_temperature(void *cookie, uint32_t *cells)

sys/dev/fdt/sxits.c

159

uint32_t data;

sys/dev/fdt/sxits.c

77

int32_t sxits_get_temperature(void *, uint32_t *);

sys/dev/fdt/sxitwi.c

186

uint32_t freq, parent_freq;

sys/dev/fdt/sxitwi.c

187

uint32_t m, n, nbase;

sys/dev/fdt/sxitwi.c

308

uint32_t reg[1];

sys/dev/fdt/sypwr.c

170

uint32_t

sys/dev/fdt/sypwr.c

184

sypwr_set_voltage(void *cookie, uint32_t voltage)

sys/dev/fdt/sypwr.c

38

uint32_t sc_fixed_microvolt;

sys/dev/fdt/sypwr.c

58

uint32_t sypwr_get_voltage(void *);

sys/dev/fdt/sypwr.c

59

int sypwr_set_voltage(void *, uint32_t);

sys/dev/fdt/sypwr.c

92

uint32_t voltage;

sys/dev/fdt/syscon.c

110

if (OF_getproplen(faa->fa_node, "offset") != sizeof(uint32_t))

sys/dev/fdt/syscon.c

114

if (OF_getproplen(faa->fa_node, "mask") != sizeof(uint32_t) &&

sys/dev/fdt/syscon.c

115

OF_getproplen(faa->fa_node, "value") != sizeof(uint32_t))

sys/dev/fdt/syscon.c

126

if (OF_getproplen(faa->fa_node, "value") != sizeof(uint32_t)) {

sys/dev/fdt/syscon.c

146

uint32_t value;

sys/dev/fdt/syscon.c

164

uint32_t value;

sys/dev/fdt/syscon.c

38

uint32_t sc_regmap;

sys/dev/fdt/syscon.c

40

uint32_t sc_mask;

sys/dev/fdt/syscon.c

41

uint32_t sc_value;

sys/dev/fdt/tascodec.c

122

uint32_t *sdz_gpio;

sys/dev/fdt/tascodec.c

179

tascodec_set_format(void *cookie, uint32_t fmt, uint32_t pol,

sys/dev/fdt/tascodec.c

180

uint32_t clk)

sys/dev/fdt/tascodec.c

87

int tascodec_set_format(void *, uint32_t, uint32_t, uint32_t);

sys/dev/fdt/tcpci.c

172

uint32_t *sc_ss_sel;

sys/dev/fdt/tipd.c

196

uint32_t status;

sys/dev/fdt/tipd.c

231

tipd_read_4(struct tipd_softc *sc, uint8_t reg, uint32_t *val)

sys/dev/fdt/tipd.c

265

tipd_write_4(struct tipd_softc *sc, uint8_t reg, uint32_t val)

sys/dev/fdt/tipd.c

303

uint32_t val;

sys/dev/fdt/tipd.c

63

uint32_t sc_status;

sys/dev/fdt/tipd.c

81

int tipd_read_4(struct tipd_softc *, uint8_t, uint32_t *);

sys/dev/fdt/tipd.c

83

int tipd_write_4(struct tipd_softc *, uint8_t, uint32_t);

sys/dev/fdt/virtio_mmio.c

122

uint32_t sc_version;

sys/dev/fdt/virtio_mmio.c

262

uint32_t id, magic;

sys/dev/fdt/virtio_mmio.c

452

uint32_t

sys/dev/fdt/virtio_mmio.c

467

sc->sc_config_offset + index + sizeof(uint32_t));

sys/dev/fdt/virtio_mmio.c

494

int index, uint32_t value)

sys/dev/fdt/virtio_mmio.c

510

sc->sc_config_offset + index + sizeof(uint32_t),

sys/dev/fdt/virtio_mmio.c

92

uint32_t virtio_mmio_read_device_config_4(struct virtio_softc *, int);

sys/dev/fdt/virtio_mmio.c

96

void virtio_mmio_write_device_config_4(struct virtio_softc *, int, uint32_t);

sys/dev/fdt/xhci_fdt.c

231

uint32_t did, sts;

sys/dev/fdt/xhci_fdt.c

324

uint32_t reg;

sys/dev/fdt/xhci_fdt.c

366

void (*init)(struct xhci_fdt_softc *, uint32_t *);

sys/dev/fdt/xhci_fdt.c

369

void exynos5_usbdrd_init(struct xhci_fdt_softc *, uint32_t *);

sys/dev/fdt/xhci_fdt.c

370

void imx8mp_usb_init(struct xhci_fdt_softc *, uint32_t *);

sys/dev/fdt/xhci_fdt.c

371

void imx8mq_usb_init(struct xhci_fdt_softc *, uint32_t *);

sys/dev/fdt/xhci_fdt.c

372

void nop_xceiv_init(struct xhci_fdt_softc *, uint32_t *);

sys/dev/fdt/xhci_fdt.c

382

uint32_t *

sys/dev/fdt/xhci_fdt.c

383

xhci_next_phy(uint32_t *cells)

sys/dev/fdt/xhci_fdt.c

385

uint32_t phandle = cells[0];

sys/dev/fdt/xhci_fdt.c

397

xhci_init_phy(struct xhci_fdt_softc *sc, uint32_t *cells)

sys/dev/fdt/xhci_fdt.c

417

uint32_t *phys;

sys/dev/fdt/xhci_fdt.c

418

uint32_t *phy;

sys/dev/fdt/xhci_fdt.c

433

while (phy && phy < phys + (len / sizeof(uint32_t))) {

sys/dev/fdt/xhci_fdt.c

469

uint32_t *reset_gpio;

sys/dev/fdt/xhci_fdt.c

518

exynos5_usbdrd_init(struct xhci_fdt_softc *sc, uint32_t *cells)

sys/dev/fdt/xhci_fdt.c

520

uint32_t phy_reg[2];

sys/dev/fdt/xhci_fdt.c

522

uint32_t pmureg;

sys/dev/fdt/xhci_fdt.c

523

uint32_t val;

sys/dev/fdt/xhci_fdt.c

598

imx8mp_usb_init(struct xhci_fdt_softc *sc, uint32_t *cells)

sys/dev/fdt/xhci_fdt.c

600

uint32_t phy_reg[2], reg;

sys/dev/fdt/xhci_fdt.c

601

uint32_t vbus_supply;

sys/dev/fdt/xhci_fdt.c

655

imx8mq_usb_init(struct xhci_fdt_softc *sc, uint32_t *cells)

sys/dev/fdt/xhci_fdt.c

657

uint32_t phy_reg[2], reg;

sys/dev/fdt/xhci_fdt.c

658

uint32_t vbus_supply;

sys/dev/fdt/xhci_fdt.c

701

nop_xceiv_init(struct xhci_fdt_softc *sc, uint32_t *cells)

sys/dev/fdt/xhci_fdt.c

703

uint32_t vcc_supply;

sys/dev/fdt/xhci_fdt.c

92

uint32_t vbus_supply;

sys/dev/hid/hid.c

196

uint32_t oldpos, uval;

sys/dev/hid/hid.c

54

uint32_t pos;

sys/dev/hid/hid.c

544

hid_locate(const void *desc, int size, uint32_t u, uint8_t id, enum hid_kind k,

sys/dev/hid/hid.c

545

struct hid_location *loc, uint32_t *flags)

sys/dev/hid/hid.c

573

uint32_t

sys/dev/hid/hid.c

577

uint32_t hpos = loc->pos;

sys/dev/hid/hid.c

578

uint32_t hsize = loc->size;

sys/dev/hid/hid.c

579

uint32_t data;

sys/dev/hid/hid.c

580

uint32_t rpos;

sys/dev/hid/hid.c

610

data = (uint32_t)((uint32_t)data << n) >> n;

sys/dev/hid/hid.c

623

uint32_t

sys/dev/hid/hid.c

63

uint32_t usages_min[MAXUSAGE];

sys/dev/hid/hid.c

634

uint32_t coll_usage = ~0;

sys/dev/hid/hid.c

64

uint32_t usages_max[MAXUSAGE];

sys/dev/hid/hid.c

65

uint32_t usage_last; /* last seen usage */

sys/dev/hid/hid.c

659

uint32_t collection)

sys/dev/hid/hid.c

66

uint32_t loc_size; /* last seen size */

sys/dev/hid/hid.c

67

uint32_t loc_count; /* last seen count */

sys/dev/hid/hid.c

68

uint32_t ncount; /* end usage item count */

sys/dev/hid/hid.c

682

hid_get_id_of_collection(const void *desc, int size, uint32_t usage,

sys/dev/hid/hid.c

683

uint32_t collection)

sys/dev/hid/hid.c

69

uint32_t icount; /* current usage item count */

sys/dev/hid/hid.c

730

uint32_t matches;

sys/dev/hid/hid.h

57

uint32_t _usage_page;

sys/dev/hid/hid.h

62

uint32_t unit_exponent;

sys/dev/hid/hid.h

63

uint32_t unit;

sys/dev/hid/hid.h

64

uint32_t report_ID;

sys/dev/hid/hid.h

66

uint32_t usage;

sys/dev/hid/hid.h

67

uint32_t usage_minimum;

sys/dev/hid/hid.h

68

uint32_t usage_maximum;

sys/dev/hid/hid.h

69

uint32_t designator_index;

sys/dev/hid/hid.h

70

uint32_t designator_minimum;

sys/dev/hid/hid.h

71

uint32_t designator_maximum;

sys/dev/hid/hid.h

72

uint32_t string_index;

sys/dev/hid/hid.h

73

uint32_t string_minimum;

sys/dev/hid/hid.h

74

uint32_t string_maximum;

sys/dev/hid/hid.h

75

uint32_t set_delimiter;

sys/dev/hid/hid.h

77

uint32_t collection;

sys/dev/hid/hid.h

91

int hid_locate(const void *, int, uint32_t, uint8_t, enum hid_kind,

sys/dev/hid/hid.h

92

struct hid_location *, uint32_t *);

sys/dev/hid/hid.h

94

uint32_t hid_get_udata(const uint8_t *buf, int, struct hid_location *);

sys/dev/hid/hid.h

96

struct hid_data *hid_get_collection_data(const void *, int, int32_t, uint32_t);

sys/dev/hid/hid.h

97

int hid_get_id_of_collection(const void *, int, uint32_t, uint32_t);

sys/dev/hid/hidcc.c

1066

uint32_t vlen = sc->sc_volume.v_len;

sys/dev/hid/hidcc.c

1067

uint32_t voff = sc->sc_volume.v_off;

sys/dev/hid/hidcc.c

605

int hidcc_add_key_volume(struct hidcc *, const struct hid_item *, uint32_t,

sys/dev/hid/hidcc.c

68

uint32_t i_bufsiz;

sys/dev/hid/hidcc.c

69

uint32_t i_off; /* offset in bits */

sys/dev/hid/hidcc.c

70

uint32_t i_len; /* length in bits */

sys/dev/hid/hidcc.c

74

uint32_t v_inc; /* volume increment bit offset */

sys/dev/hid/hidcc.c

75

uint32_t v_dec; /* volume decrement bit offset */

sys/dev/hid/hidcc.c

76

uint32_t v_off; /* offset in bits */

sys/dev/hid/hidcc.c

77

uint32_t v_len; /* length in bits */

sys/dev/hid/hidcc.c

870

uint32_t off;

sys/dev/hid/hidcc.c

877

uint32_t len = hi.loc.size * hi.loc.count;

sys/dev/hid/hidcc.c

989

uint32_t off, u_int bit)

sys/dev/hid/hidcc.c

991

uint32_t len;

sys/dev/hid/hidkbd.c

253

uint32_t qflags, int id, void *desc, int dlen)

sys/dev/hid/hidkbdsc.h

103

int hidkbd_attach(struct device *, struct hidkbd *, int, uint32_t,

sys/dev/hid/hidms.c

247

hidms_setup(struct device *self, struct hidms *ms, uint32_t quirks,

sys/dev/hid/hidms.c

252

uint32_t flags;

sys/dev/hid/hidmsvar.h

91

int hidms_setup(struct device *, struct hidms *, uint32_t, int, void *,

sys/dev/hid/hidmtvar.h

19

uint32_t usage;

sys/dev/hid/hidmtvar.h

38

uint32_t sc_flags;

sys/dev/i2c/i2c_bitbang.c

131

uint32_t bit;

sys/dev/i2c/i2c_bitbang.c

174

uint32_t bit;

sys/dev/i2c/i2c_bitbang.h

49

void (*ibo_set_bits)(void *, uint32_t);

sys/dev/i2c/i2c_bitbang.h

50

void (*ibo_set_dir)(void *, uint32_t);

sys/dev/i2c/i2c_bitbang.h

51

uint32_t (*ibo_read_bits)(void *);

sys/dev/i2c/i2c_bitbang.h

52

uint32_t ibo_bits[I2C_NBITS];

sys/dev/i2c/iatp.c

173

uint32_t max_x;

sys/dev/i2c/iatp.c

174

uint32_t max_y;

sys/dev/i2c/iatp.c

79

uint32_t crc;

sys/dev/i2c/ihidev.h

64

uint32_t reserved;

sys/dev/i2c/pca9548.c

160

uint32_t channel;

sys/dev/i2c/pca9548.c

415

uint32_t reg[1];

sys/dev/i2c/pca9554.c

163

pcagpio_config_pin(void *arg, uint32_t *cells, int config)

sys/dev/i2c/pca9554.c

166

uint32_t pin = cells[0];

sys/dev/i2c/pca9554.c

193

pcagpio_get_pin(void *arg, uint32_t *cells)

sys/dev/i2c/pca9554.c

196

uint32_t pin = cells[0];

sys/dev/i2c/pca9554.c

197

uint32_t flags = cells[1];

sys/dev/i2c/pca9554.c

220

pcagpio_set_pin(void *arg, uint32_t *cells, int value)

sys/dev/i2c/pca9554.c

223

uint32_t pin = cells[0];

sys/dev/i2c/pca9554.c

224

uint32_t flags = cells[1];

sys/dev/i2c/pca9554.c

76

void pcagpio_config_pin(void *, uint32_t *, int);

sys/dev/i2c/pca9554.c

77

int pcagpio_get_pin(void *, uint32_t *);

sys/dev/i2c/pca9554.c

78

void pcagpio_set_pin(void *, uint32_t *, int);

sys/dev/ic/acx.c

1322

uint32_t desc_status;

sys/dev/ic/acx.c

1453

acx_read_eeprom(struct acx_softc *sc, uint32_t offset, uint8_t *val)

sys/dev/ic/acx.c

1480

acx_read_phyreg(struct acx_softc *sc, uint32_t reg, uint8_t *val)

sys/dev/ic/acx.c

1507

acx_write_phyreg(struct acx_softc *sc, uint32_t reg, uint8_t val)

sys/dev/ic/acx.c

1566

uint32_t radio_fw_ofs;

sys/dev/ic/acx.c

1630

acx_load_firmware(struct acx_softc *sc, uint32_t offset, const uint8_t *data,

sys/dev/ic/acx.c

1634

const uint32_t *fw;

sys/dev/ic/acx.c

1641

fw = (const uint32_t *)data;

sys/dev/ic/acx.c

1653

fw = (const uint32_t *)data;

sys/dev/ic/acx.c

1654

fw_len = data_len / sizeof(uint32_t);

sys/dev/ic/acx.c

1688

uint32_t val;

sys/dev/ic/acx.c

170

int acx_read_eeprom(struct acx_softc *, uint32_t, uint8_t *);

sys/dev/ic/acx.c

171

int acx_read_phyreg(struct acx_softc *, uint32_t, uint8_t *);

sys/dev/ic/acx.c

175

int acx_load_firmware(struct acx_softc *, uint32_t,

sys/dev/ic/acx.c

187

int acx_init_radio(struct acx_softc *, uint32_t, uint32_t);

sys/dev/ic/acx.c

2060

uint32_t paddr;

sys/dev/ic/acx.c

2091

uint32_t paddr;

sys/dev/ic/acx.c

2128

uint32_t paddr;

sys/dev/ic/acx.c

2181

uint32_t paddr;

sys/dev/ic/acx.c

2578

acx_init_radio(struct acx_softc *sc, uint32_t radio_ofs, uint32_t radio_len)

sys/dev/ic/acx.c

663

uint32_t fw_rev_no;

sys/dev/ic/acx100.c

105

void acx100_init_fw_txring(struct acx_softc *, uint32_t);

sys/dev/ic/acx100.c

106

void acx100_init_fw_rxring(struct acx_softc *, uint32_t);

sys/dev/ic/acx100.c

128

uint32_t fw_ring_size; /* total size of fw (tx + rx) ring */

sys/dev/ic/acx100.c

129

uint32_t fw_rxring_addr; /* start phyaddr of fw rx desc */

sys/dev/ic/acx100.c

134

uint32_t fw_ring_end[2]; /* see ACX100_SET_RING_END() */

sys/dev/ic/acx100.c

135

uint32_t fw_txring_addr; /* start phyaddr of fw tx desc */

sys/dev/ic/acx100.c

156

uint32_t opt; /* see ACX100_MEMOPT_ */

sys/dev/ic/acx100.c

157

uint32_t h_rxring_paddr; /* host rx desc start phyaddr */

sys/dev/ic/acx100.c

163

uint32_t rx_memblk_addr; /* start addr of rx mem blocks */

sys/dev/ic/acx100.c

164

uint32_t tx_memblk_addr; /* start addr of tx mem blocks */

sys/dev/ic/acx100.c

395

uint32_t txring_start, rxring_start, ring_end;

sys/dev/ic/acx100.c

450

uint32_t memblk_start, memblk_end;

sys/dev/ic/acx100.c

521

acx100_init_fw_txring(struct acx_softc *sc, uint32_t fw_txdesc_start)

sys/dev/ic/acx100.c

525

uint32_t desc_paddr, fw_desc_offset;

sys/dev/ic/acx100.c

556

acx100_init_fw_rxring(struct acx_softc *sc, uint32_t fw_rxdesc_start)

sys/dev/ic/acx100.c

559

uint32_t fw_desc_offset;

sys/dev/ic/acx111.c

122

void acx111_init_fw_txring(struct acx_softc *, uint32_t);

sys/dev/ic/acx111.c

155

uint32_t h_rxring_paddr; /* host rx desc start phyaddr */

sys/dev/ic/acx111.c

173

uint32_t tx_memblk_addr; /* start addr of tx mem blocks */

sys/dev/ic/acx111.c

174

uint32_t rx_memblk_addr; /* start addr of rx mem blocks */

sys/dev/ic/acx111.c

175

uint32_t fw_rxring_start; /* start phyaddr of fw rx ring */

sys/dev/ic/acx111.c

176

uint32_t reserved0;

sys/dev/ic/acx111.c

177

uint32_t fw_txring_start; /* start phyaddr of fw tx ring */

sys/dev/ic/acx111.c

190

uint32_t feature;

sys/dev/ic/acx111.c

191

uint32_t dataflow; /* see ACX111_DF_ */

sys/dev/ic/acx111.c

377

acx111_init_fw_txring(struct acx_softc *sc, uint32_t fw_txdesc_start)

sys/dev/ic/acx111.c

380

uint32_t desc_paddr;

sys/dev/ic/acx111.c

409

uint32_t dataflow;

sys/dev/ic/acxreg.h

234

uint32_t code_start;

sys/dev/ic/acxreg.h

235

uint32_t code_end;

sys/dev/ic/acxreg.h

236

uint32_t wep_cache_start;

sys/dev/ic/acxreg.h

237

uint32_t wep_cache_end;

sys/dev/ic/acxreg.h

238

uint32_t pkt_tmplt_start;

sys/dev/ic/acxreg.h

239

uint32_t pkt_tmplt_end;

sys/dev/ic/acxreg.h

240

uint32_t fw_desc_start;

sys/dev/ic/acxreg.h

241

uint32_t fw_desc_end;

sys/dev/ic/acxreg.h

242

uint32_t memblk_start;

sys/dev/ic/acxreg.h

243

uint32_t memblk_end;

sys/dev/ic/acxreg.h

278

uint32_t hw_id;

sys/dev/ic/acxreg.h

293

uint32_t lifetime;

sys/dev/ic/acxreg.h

458

uint32_t radio_ofs; /* radio firmware offset */

sys/dev/ic/acxreg.h

459

uint32_t radio_len; /* radio firmware length */

sys/dev/ic/acxvar.h

121

uint32_t f_tx_next_desc; /* next acx_fw_txdesc phyaddr */

sys/dev/ic/acxvar.h

122

uint32_t f_tx_host_desc; /* acx_host_desc phyaddr */

sys/dev/ic/acxvar.h

123

uint32_t f_tx_acx_ptr;

sys/dev/ic/acxvar.h

124

uint32_t f_tx_time;

sys/dev/ic/acxvar.h

128

uint32_t f_tx_dev_spec[4];

sys/dev/ic/acxvar.h

150

uint32_t f_tx_queue_info;

sys/dev/ic/acxvar.h

158

uint32_t f_rx_next_desc; /* next acx_fw_rxdesc phyaddr */

sys/dev/ic/acxvar.h

159

uint32_t f_rx_host_desc; /* acx_host_desc phyaddr */

sys/dev/ic/acxvar.h

160

uint32_t f_rx_acx_ptr;

sys/dev/ic/acxvar.h

161

uint32_t f_rx_time;

sys/dev/ic/acxvar.h

164

uint32_t f_rx_wep_ofs;

sys/dev/ic/acxvar.h

175

uint32_t f_rx_unknown1;

sys/dev/ic/acxvar.h

183

uint32_t h_data_paddr; /* data phyaddr */

sys/dev/ic/acxvar.h

188

uint32_t h_next_desc; /* next acx_host_desc phyaddr */

sys/dev/ic/acxvar.h

189

uint32_t h_pnext;

sys/dev/ic/acxvar.h

190

uint32_t h_status; /* see DESC_STATUS_ */

sys/dev/ic/acxvar.h

224

uint32_t rbh_time; /* recv timestamp */

sys/dev/ic/acxvar.h

239

uint32_t rx_ring_paddr;

sys/dev/ic/acxvar.h

244

uint32_t tx_ring_paddr;

sys/dev/ic/acxvar.h

254

uint32_t tb_fwdesc_ofs;

sys/dev/ic/acxvar.h

342

uint32_t sc_flags; /* see ACX_FLAG_ */

sys/dev/ic/acxvar.h

344

uint32_t sc_firmware_ver;

sys/dev/ic/acxvar.h

345

uint32_t sc_hardware_id;

sys/dev/ic/acxvar.h

370

uint32_t sc_cmd; /* cmd reg (MMIO 2) */

sys/dev/ic/acxvar.h

371

uint32_t sc_cmd_param; /* cmd param reg (MMIO 2) */

sys/dev/ic/acxvar.h

372

uint32_t sc_info; /* unused */

sys/dev/ic/acxvar.h

373

uint32_t sc_info_param; /* unused */

sys/dev/ic/acxvar.h

390

uint32_t chip_ee_eaddr_ofs;

sys/dev/ic/acxvar.h

478

void acx_write_phyreg(struct acx_softc *, uint32_t, uint8_t);

sys/dev/ic/aic6915.c

112

uint32_t

sys/dev/ic/aic6915.c

1195

uint32_t reg;

sys/dev/ic/aic6915.c

1249

uint32_t reg0, reg1, reg2;

sys/dev/ic/aic6915.c

1263

uint32_t hash, slot, reg;

sys/dev/ic/aic6915.c

127

sf_reg_write(struct sf_softc *sc, bus_addr_t reg, uint32_t val)

sys/dev/ic/aic6915.c

1288

for (i = 0; i < SF_PERFECT_SIZE; i += sizeof(uint32_t))

sys/dev/ic/aic6915.c

1291

for (i = 0; i < SF_HASH_SIZE; i += sizeof(uint32_t))

sys/dev/ic/aic6915.c

1364

uint32_t v;

sys/dev/ic/aic6915.c

1415

uint32_t ipg;

sys/dev/ic/aic6915.c

573

uint32_t isr;

sys/dev/ic/aic6915.c

648

uint32_t cqci, tcd;

sys/dev/ic/aic6915.c

719

uint32_t cqci, word0;

sys/dev/ic/aic6915.c

858

uint32_t *p;

sys/dev/ic/aic6915.c

862

for (i = 0; i < (sizeof(stats) / sizeof(uint32_t)); i++) {

sys/dev/ic/aic6915.c

864

SF_STATS_BASE + (i * sizeof(uint32_t)));

sys/dev/ic/aic6915.c

865

sf_genreg_write(sc, SF_STATS_BASE + (i * sizeof(uint32_t)), 0);

sys/dev/ic/aic6915.c

949

for (i = 0; i < sizeof(struct sf_stats); i += sizeof(uint32_t))

sys/dev/ic/aic6915.c

97

uint32_t sf_reg_read(struct sf_softc *, bus_addr_t);

sys/dev/ic/aic6915.c

98

void sf_reg_write(struct sf_softc *, bus_addr_t , uint32_t);

sys/dev/ic/aic6915.h

154

uint32_t td_word0; /* ID, flags */

sys/dev/ic/aic6915.h

155

uint32_t td_word1; /* Tx buffer count */

sys/dev/ic/aic6915.h

157

uint32_t fr_addr; /* address */

sys/dev/ic/aic6915.h

158

uint32_t fr_len; /* length */

sys/dev/ic/aic6915.h

169

uint32_t td_word0; /* ID, flags */

sys/dev/ic/aic6915.h

170

uint32_t td_addr; /* buffer address */

sys/dev/ic/aic6915.h

187

uint32_t td_word0; /* ID, flags */

sys/dev/ic/aic6915.h

188

uint32_t td_reserved;

sys/dev/ic/aic6915.h

189

uint32_t td_addr_lo; /* buffer address (LSD) */

sys/dev/ic/aic6915.h

190

uint32_t td_addr_hi; /* buffer address (MSD) */

sys/dev/ic/aic6915.h

197

uint32_t tcd_word0; /* index, priority, flags */

sys/dev/ic/aic6915.h

47

uint32_t rbd32_addr; /* address, flags */

sys/dev/ic/aic6915.h

54

uint32_t rbd64_addr_lo; /* address (LSD), flags */

sys/dev/ic/aic6915.h

55

uint32_t rbd64_addr_hi; /* address (MDS) */

sys/dev/ic/aic6915.h

563

((p) * 32 * sizeof(uint32_t)) + \

sys/dev/ic/aic6915.h

564

((r) * sizeof(uint32_t)))

sys/dev/ic/aic6915.h

643

uint32_t TransmitOKFrames;

sys/dev/ic/aic6915.h

644

uint32_t SingleCollisionFrames;

sys/dev/ic/aic6915.h

645

uint32_t MultipleCollisionFrames;

sys/dev/ic/aic6915.h

646

uint32_t TransmitCRCErrors;

sys/dev/ic/aic6915.h

647

uint32_t TransmitOKOctets;

sys/dev/ic/aic6915.h

648

uint32_t TransmitDeferredFrames;

sys/dev/ic/aic6915.h

649

uint32_t TransmitLateCollisionCount;

sys/dev/ic/aic6915.h

65

uint32_t rcd_word0; /* length, end index, status1 */

sys/dev/ic/aic6915.h

650

uint32_t TransmitPauseControlFrames;

sys/dev/ic/aic6915.h

651

uint32_t TransmitControlFrames;

sys/dev/ic/aic6915.h

652

uint32_t TransmitAbortDueToExcessiveCollisions;

sys/dev/ic/aic6915.h

653

uint32_t TransmitAbortDueToExcessingDeferral;

sys/dev/ic/aic6915.h

654

uint32_t MulticastFramesTransmittedOK;

sys/dev/ic/aic6915.h

655

uint32_t BroadcastFramesTransmittedOK;

sys/dev/ic/aic6915.h

656

uint32_t FramesLostDueToInternalTransmitErrors;

sys/dev/ic/aic6915.h

657

uint32_t ReceiveOKFrames;

sys/dev/ic/aic6915.h

658

uint32_t ReceiveCRCErrors;

sys/dev/ic/aic6915.h

659

uint32_t AlignmentErrors;

sys/dev/ic/aic6915.h

660

uint32_t ReceiveOKOctets;

sys/dev/ic/aic6915.h

661

uint32_t PauseFramesReceivedOK;

sys/dev/ic/aic6915.h

662

uint32_t ControlFramesReceivedOK;

sys/dev/ic/aic6915.h

663

uint32_t ControlFramesReceivedWithUnsupportedOpcode;

sys/dev/ic/aic6915.h

664

uint32_t ReceiveFramesTooLong;

sys/dev/ic/aic6915.h

665

uint32_t ReceiveFramesTooShort;

sys/dev/ic/aic6915.h

666

uint32_t ReceiveFramesJabbersError;

sys/dev/ic/aic6915.h

667

uint32_t ReceiveFramesFragments;

sys/dev/ic/aic6915.h

668

uint32_t ReceivePackets64Bytes;

sys/dev/ic/aic6915.h

669

uint32_t ReceivePackets127Bytes;

sys/dev/ic/aic6915.h

670

uint32_t ReceivePackets255Bytes;

sys/dev/ic/aic6915.h

671

uint32_t ReceivePackets511Bytes;

sys/dev/ic/aic6915.h

672

uint32_t ReceivePackets1023Bytes;

sys/dev/ic/aic6915.h

673

uint32_t ReceivePackets1518Bytes;

sys/dev/ic/aic6915.h

674

uint32_t FramesLostDueToInternalReceiveErrors;

sys/dev/ic/aic6915.h

675

uint32_t TransmitFifoUnderflowCounts;

sys/dev/ic/aic6915.h

72

uint32_t rcd_word0; /* length, end index, status1 */

sys/dev/ic/aic6915.h

73

uint32_t rcd_word1; /* VLAN ID, status2 */

sys/dev/ic/aic6915.h

792

uint32_t sc_InterruptEn; /* prototype InterruptEn register */

sys/dev/ic/aic6915.h

794

uint32_t sc_TransmitFrameCSR; /* prototype TransmitFrameCSR reg */

sys/dev/ic/aic6915.h

795

uint32_t sc_TxDescQueueCtrl; /* prototype TxDescQueueCtrl reg */

sys/dev/ic/aic6915.h

798

uint32_t sc_MacConfig1; /* prototype MacConfig1 register */

sys/dev/ic/aic6915.h

80

uint32_t rcd_word0; /* length, end index, status1 */

sys/dev/ic/aic6915.h

800

uint32_t sc_RxAddressFilteringCtl;

sys/dev/ic/aic6915.h

81

uint32_t rcd_word1; /* partial TCP/UDP checksum, status2 */

sys/dev/ic/aic6915.h

88

uint32_t rcd_word0; /* length, end index, status1 */

sys/dev/ic/aic6915.h

89

uint32_t rcd_word1; /* start index, status3, status2 */

sys/dev/ic/aic6915.h

90

uint32_t rcd_word2; /* VLAN ID + priority, TCP/UDP csum */

sys/dev/ic/aic6915.h

91

uint32_t rcd_timestamp; /* timestamp */

sys/dev/ic/aic79xx.c

10084

uint32_t *dataptr_words;

sys/dev/ic/aic79xx.c

10087

dataptr_words = (uint32_t*)&scb->hscb->dataptr;

sys/dev/ic/aic79xx.c

10124

ahd_sg_bus_to_virt(struct ahd_softc *ahd, struct scb *scb, uint32_t sg_busaddr)

sys/dev/ic/aic79xx.c

10133

uint32_t

sys/dev/ic/aic79xx.c

10174

uint32_t

sys/dev/ic/aic79xx.c

10184

uint32_t sgptr;

sys/dev/ic/aic79xx.c

10200

uint32_t sgptr;

sys/dev/ic/aic79xx.c

10255

uint32_t

sys/dev/ic/aic79xx.c

10265

ahd_outl(struct ahd_softc *ahd, u_int port, uint32_t value)

sys/dev/ic/aic79xx.c

10419

uint32_t

sys/dev/ic/aic79xx.c

10452

uint32_t saved_hscb_busaddr;

sys/dev/ic/aic79xx.c

10537

uint32_t

sys/dev/ic/aic79xx.c

222

role_t role, uint32_t status,

sys/dev/ic/aic79xx.c

2717

uint32_t ahd_debug = AHD_DEBUG_OPTS;

sys/dev/ic/aic79xx.c

2736

(uint32_t)((aic_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF),

sys/dev/ic/aic79xx.c

2737

(uint32_t)(aic_le64toh(hscb->dataptr) & 0xFFFFFFFF),

sys/dev/ic/aic79xx.c

2756

uint32_t len;

sys/dev/ic/aic79xx.c

2762

(uint32_t)((addr >> 32) & 0xFFFFFFFF),

sys/dev/ic/aic79xx.c

2763

(uint32_t)(addr & 0xFFFFFFFF),

sys/dev/ic/aic79xx.c

2773

uint32_t len;

sys/dev/ic/aic79xx.c

4883

uint32_t sgptr;

sys/dev/ic/aic79xx.c

4896

uint32_t data_cnt;

sys/dev/ic/aic79xx.c

4898

uint32_t sglen;

sys/dev/ic/aic79xx.c

5014

uint32_t sgptr;

sys/dev/ic/aic79xx.c

5015

uint32_t resid;

sys/dev/ic/aic79xx.c

6206

uint32_t busaddr;

sys/dev/ic/aic79xx.c

643

uint32_t datacnt;

sys/dev/ic/aic79xx.c

644

uint32_t sgptr;

sys/dev/ic/aic79xx.c

689

uint32_t sgptr;

sys/dev/ic/aic79xx.c

690

uint32_t resid;

sys/dev/ic/aic79xx.c

7022

uint32_t busaddr;

sys/dev/ic/aic79xx.c

7081

ahd_done_with_status(struct ahd_softc *ahd, struct scb *scb, uint32_t status)

sys/dev/ic/aic79xx.c

7097

int lun, u_int tag, role_t role, uint32_t status,

sys/dev/ic/aic79xx.c

7112

uint32_t busaddr;

sys/dev/ic/aic79xx.c

7327

int lun, u_int tag, role_t role, uint32_t status,

sys/dev/ic/aic79xx.c

7483

int lun, u_int tag, role_t role, uint32_t status)

sys/dev/ic/aic79xx.c

758

uint32_t sgptr;

sys/dev/ic/aic79xx.c

760

uint32_t data_len;

sys/dev/ic/aic79xx.c

8078

uint32_t sgptr;

sys/dev/ic/aic79xx.c

8079

uint32_t resid_sgptr;

sys/dev/ic/aic79xx.c

8080

uint32_t resid;

sys/dev/ic/aic79xx.c

82

uint32_t ahd_attach_to_HostRAID_controllers = 1;

sys/dev/ic/aic79xx.c

8522

instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);

sys/dev/ic/aic79xx.c

8560

uint32_t mask;

sys/dev/ic/aic79xx.c

9124

uint32_t checksum;

sys/dev/ic/aic79xx.c

9152

uint32_t checksum;

sys/dev/ic/aic79xx.h

1128

uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS];

sys/dev/ic/aic79xx.h

1129

uint32_t cmdcmplt_total;

sys/dev/ic/aic79xx.h

1400

struct scb *scb, uint32_t status);

sys/dev/ic/aic79xx.h

1403

role_t role, uint32_t status,

sys/dev/ic/aic79xx.h

1410

role_t role, uint32_t status);

sys/dev/ic/aic79xx.h

1490

extern uint32_t ahd_debug;

sys/dev/ic/aic79xx.h

213

extern uint32_t ahd_attach_to_HostRAID_controllers;

sys/dev/ic/aic79xx.h

418

uint32_t residual_datacnt; /* Residual in the current S/G seg */

sys/dev/ic/aic79xx.h

419

uint32_t residual_sgptr; /* The next S/G for this transfer */

sys/dev/ic/aic79xx.h

424

uint32_t residual_datacnt; /* Residual in the current S/G seg */

sys/dev/ic/aic79xx.h

425

uint32_t residual_sgptr; /* The next S/G for this transfer */

sys/dev/ic/aic79xx.h

439

typedef uint32_t sense_addr_t;

sys/dev/ic/aic79xx.h

458

uint32_t spare[2];

sys/dev/ic/aic79xx.h

523

/*32*/ uint32_t datacnt; /* Byte 3 is spare. */

sys/dev/ic/aic79xx.h

524

/*36*/ uint32_t sgptr;

sys/dev/ic/aic79xx.h

525

/*40*/ uint32_t hscb_busaddr;

sys/dev/ic/aic79xx.h

526

/*44*/ uint32_t next_hscb_busaddr;

sys/dev/ic/aic79xx.h

549

uint32_t addr;

sys/dev/ic/aic79xx.h

550

uint32_t len;

sys/dev/ic/aic79xx.h

558

uint32_t len;

sys/dev/ic/aic79xx.h

559

uint32_t pad;

sys/dev/ic/aic79xx_inline.h

111

uint32_t);

sys/dev/ic/aic79xx_inline.h

112

uint32_t

sys/dev/ic/aic79xx_inline.h

118

uint32_t

sys/dev/ic/aic79xx_inline.h

130

uint32_t

sys/dev/ic/aic79xx_inline.h

132

void ahd_outl(struct ahd_softc *, u_int, uint32_t);

sys/dev/ic/aic79xx_inline.h

149

uint32_t ahd_inl_scbram(struct ahd_softc *ahd, u_int offset);

sys/dev/ic/aic79xx_inline.h

155

uint32_t ahd_get_sense_bufaddr(struct ahd_softc *ahd, struct scb *scb);

sys/dev/ic/aic7xxx.c

1558

uint32_t ahc_debug = 0; /* AHC_SHOW_MISC|AHC_SHOW_SENSE|AHC_DEBUG_OPTS;*/

sys/dev/ic/aic7xxx.c

348

*((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;

sys/dev/ic/aic7xxx.c

3629

uint32_t sgptr;

sys/dev/ic/aic7xxx.c

3642

uint32_t data_cnt;

sys/dev/ic/aic7xxx.c

3643

uint32_t data_addr;

sys/dev/ic/aic7xxx.c

3644

uint32_t sglen;

sys/dev/ic/aic7xxx.c

3718

uint32_t sgptr;

sys/dev/ic/aic7xxx.c

3719

uint32_t resid;

sys/dev/ic/aic7xxx.c

3720

uint32_t dataptr;

sys/dev/ic/aic7xxx.c

4455

uint32_t physaddr;

sys/dev/ic/aic7xxx.c

5118

int lun, u_int tag, role_t role, uint32_t status,

sys/dev/ic/aic7xxx.c

5326

int target, char channel, int lun, uint32_t status,

sys/dev/ic/aic7xxx.c

5585

int lun, u_int tag, role_t role, uint32_t status)

sys/dev/ic/aic7xxx.c

5907

uint32_t sgptr;

sys/dev/ic/aic7xxx.c

5908

uint32_t resid_sgptr;

sys/dev/ic/aic7xxx.c

5909

uint32_t resid;

sys/dev/ic/aic7xxx.c

6255

instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);

sys/dev/ic/aic7xxx.c

6334

uint32_t mask;

sys/dev/ic/aic7xxx_inline.h

170

uint32_t sg_busaddr);

sys/dev/ic/aic7xxx_inline.h

171

IO_INLINE uint32_t

sys/dev/ic/aic7xxx_inline.h

174

IO_INLINE uint32_t

sys/dev/ic/aic7xxx_inline.h

179

IO_INLINE uint32_t

sys/dev/ic/aic7xxx_inline.h

187

ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr)

sys/dev/ic/aic7xxx_inline.h

198

IO_INLINE uint32_t

sys/dev/ic/aic7xxx_inline.h

209

IO_INLINE uint32_t

sys/dev/ic/aic7xxx_inline.h

226

IO_INLINE uint32_t

sys/dev/ic/aic7xxx_inline.h

257

IO_INLINE uint32_t

sys/dev/ic/aic7xxx_inline.h

260

uint32_t value);

sys/dev/ic/aic7xxx_inline.h

268

IO_INLINE uint32_t

sys/dev/ic/aic7xxx_inline.h

281

uint32_t sgptr;

sys/dev/ic/aic7xxx_inline.h

321

IO_INLINE uint32_t

sys/dev/ic/aic7xxx_inline.h

331

ahc_outl(struct ahc_softc *ahc, u_int port, uint32_t value)

sys/dev/ic/aic7xxx_inline.h

446

IO_INLINE uint32_t

sys/dev/ic/aic7xxx_openbsd.c

325

uint32_t len;

sys/dev/ic/aic7xxx_openbsd.h

197

static __inline void ahc_set_transaction_status(struct scb *, uint32_t);

sys/dev/ic/aic7xxx_openbsd.h

198

static __inline void ahc_set_scsi_status(struct scb *, uint32_t);

sys/dev/ic/aic7xxx_openbsd.h

199

static __inline uint32_t ahc_get_transaction_status(struct scb *);

sys/dev/ic/aic7xxx_openbsd.h

200

static __inline uint32_t ahc_get_scsi_status(struct scb *);

sys/dev/ic/aic7xxx_openbsd.h

208

static __inline uint32_t ahc_get_sense_bufsize(struct ahc_softc *,

sys/dev/ic/aic7xxx_openbsd.h

213

ahc_set_transaction_status(struct scb *scb, uint32_t status)

sys/dev/ic/aic7xxx_openbsd.h

219

ahc_set_scsi_status(struct scb *scb, uint32_t status)

sys/dev/ic/aic7xxx_openbsd.h

224

static __inline uint32_t

sys/dev/ic/aic7xxx_openbsd.h

233

static __inline uint32_t

sys/dev/ic/aic7xxx_openbsd.h

281

static __inline uint32_t

sys/dev/ic/aic7xxx_openbsd.h

310

static __inline uint32_t ahc_pci_read_config(ahc_dev_softc_t, int, int);

sys/dev/ic/aic7xxx_openbsd.h

311

static __inline void ahc_pci_write_config(ahc_dev_softc_t, int, uint32_t,

sys/dev/ic/aic7xxx_openbsd.h

320

static __inline uint32_t

sys/dev/ic/aic7xxx_openbsd.h

327

ahc_pci_write_config(ahc_dev_softc_t pci, int reg, uint32_t value, int width)

sys/dev/ic/aic7xxx_seeprom.c

337

uint32_t devconfig;

sys/dev/ic/aic7xxx_seeprom.c

757

uint32_t checksum;

sys/dev/ic/aic7xxxvar.h

1227

int, u_int, role_t, uint32_t, ahc_search_action);

sys/dev/ic/aic7xxxvar.h

1229

struct scsi_xfer *, int, char, int, uint32_t,

sys/dev/ic/aic7xxxvar.h

1236

u_int, role_t, uint32_t);

sys/dev/ic/aic7xxxvar.h

1305

extern uint32_t ahc_debug;

sys/dev/ic/aic7xxxvar.h

402

uint32_t residual_datacnt; /* Residual in the current S/G seg */

sys/dev/ic/aic7xxxvar.h

403

uint32_t residual_sg_ptr; /* The next S/G for this transfer */

sys/dev/ic/aic7xxxvar.h

411

uint32_t residual_datacnt; /* Residual in the current S/G seg */

sys/dev/ic/aic7xxxvar.h

412

uint32_t residual_sg_ptr; /* The next S/G for this transfer */

sys/dev/ic/aic7xxxvar.h

428

uint32_t cdb_ptr;

sys/dev/ic/aic7xxxvar.h

469

/*12*/ uint32_t dataptr;

sys/dev/ic/aic7xxxvar.h

470

/*16*/ uint32_t datacnt; /*

sys/dev/ic/aic7xxxvar.h

475

/*20*/ uint32_t sgptr;

sys/dev/ic/aic7xxxvar.h

520

uint32_t addr;

sys/dev/ic/aic7xxxvar.h

521

uint32_t len;

sys/dev/ic/aic7xxxvar.h

912

uint32_t devconfig;

sys/dev/ic/anxdp.c

260

uint32_t sc3;

sys/dev/ic/anxdp.c

277

uint32_t fe2, pd, hrc;

sys/dev/ic/anxdp.c

279

const uint32_t pd_mask = isrockchip(sc) ? RK_AUX_PD : AUX_PD;

sys/dev/ic/anxdp.c

370

uint32_t val;

sys/dev/ic/anxdp.c

428

uint32_t val;

sys/dev/ic/anxdp.c

578

uint32_t val;

sys/dev/ic/anxdp.c

661

uint32_t val;

sys/dev/ic/anxdp.c

746

uint32_t val;

sys/dev/ic/ar5008.c

1215

uint32_t reg;

sys/dev/ic/ar5008.c

1362

uint32_t intr, intr2, intr5, sync;

sys/dev/ic/ar5008.c

139

void athn_get_delta_slope(uint32_t, uint32_t *, uint32_t *);

sys/dev/ic/ar5008.c

1830

uint32_t reg;

sys/dev/ic/ar5008.c

1845

static __inline uint32_t

sys/dev/ic/ar5008.c

1848

uint32_t delay;

sys/dev/ic/ar5008.c

1889

uint32_t phy;

sys/dev/ic/ar5008.c

1918

uint32_t coeff, exp, man, reg;

sys/dev/ic/ar5008.c

1953

uint32_t synth_delay;

sys/dev/ic/ar5008.c

2003

uint32_t reg;

sys/dev/ic/ar5008.c

2027

uint32_t reg;

sys/dev/ic/ar5008.c

2105

uint32_t agc_nfcal;

sys/dev/ic/ar5008.c

2145

uint32_t mode, reg;

sys/dev/ic/ar5008.c

2188

uint32_t reg, i_coff_denom, q_coff_denom;

sys/dev/ic/ar5008.c

2256

uint32_t reg, gain_mismatch_i, gain_mismatch_q;

sys/dev/ic/ar5008.c

2308

uint32_t reg;

sys/dev/ic/ar5008.c

2412

uint32_t mask[4], reg;

sys/dev/ic/ar5008.c

2518

const uint32_t *pvals;

sys/dev/ic/ar5008.c

2519

uint32_t reg;

sys/dev/ic/ar5008.c

2544

uint32_t val = pvals[i];

sys/dev/ic/ar5008.c

279

ar5008_read_eep_word(struct athn_softc *sc, uint32_t addr, uint16_t *val)

sys/dev/ic/ar5008.c

281

uint32_t reg;

sys/dev/ic/ar5008.c

2847

uint32_t reg;

sys/dev/ic/ar5008.c

2868

uint32_t reg;

sys/dev/ic/ar5008.c

2897

uint32_t reg;

sys/dev/ic/ar5008.c

2926

uint32_t reg;

sys/dev/ic/ar5008.c

2937

uint32_t reg;

sys/dev/ic/ar5008.c

2948

uint32_t reg;

sys/dev/ic/ar5008.c

301

uint32_t addr, end;

sys/dev/ic/ar5008.c

382

uint32_t reg;

sys/dev/ic/ar5008.c

411

uint32_t reg;

sys/dev/ic/ar5008.c

428

uint32_t reg;

sys/dev/ic/ar5008.c

457

uint32_t reg;

sys/dev/ic/ar5008.c

63

int ar5008_read_eep_word(struct athn_softc *, uint32_t, uint16_t *);

sys/dev/ic/ar5008.c

735

uint32_t tstamp;

sys/dev/ic/ar5008reg.h

666

uint32_t ds_link;

sys/dev/ic/ar5008reg.h

667

uint32_t ds_data;

sys/dev/ic/ar5008reg.h

668

uint32_t ds_ctl0;

sys/dev/ic/ar5008reg.h

669

uint32_t ds_ctl1;

sys/dev/ic/ar5008reg.h

670

uint32_t ds_ctl2;

sys/dev/ic/ar5008reg.h

671

uint32_t ds_ctl3;

sys/dev/ic/ar5008reg.h

672

uint32_t ds_ctl4;

sys/dev/ic/ar5008reg.h

673

uint32_t ds_ctl5;

sys/dev/ic/ar5008reg.h

674

uint32_t ds_ctl6;

sys/dev/ic/ar5008reg.h

675

uint32_t ds_ctl7;

sys/dev/ic/ar5008reg.h

676

uint32_t ds_ctl8;

sys/dev/ic/ar5008reg.h

677

uint32_t ds_ctl9;

sys/dev/ic/ar5008reg.h

678

uint32_t ds_ctl10;

sys/dev/ic/ar5008reg.h

679

uint32_t ds_ctl11;

sys/dev/ic/ar5008reg.h

680

uint32_t ds_status0;

sys/dev/ic/ar5008reg.h

681

uint32_t ds_status1;

sys/dev/ic/ar5008reg.h

682

uint32_t ds_tstamp;

sys/dev/ic/ar5008reg.h

683

uint32_t ds_ba_bitmap_lo;

sys/dev/ic/ar5008reg.h

684

uint32_t ds_ba_bitmap_hi;

sys/dev/ic/ar5008reg.h

685

uint32_t ds_evm0;

sys/dev/ic/ar5008reg.h

686

uint32_t ds_evm1;

sys/dev/ic/ar5008reg.h

687

uint32_t ds_evm2;

sys/dev/ic/ar5008reg.h

688

uint32_t ds_status8;

sys/dev/ic/ar5008reg.h

689

uint32_t ds_status9;

sys/dev/ic/ar5008reg.h

694

uint32_t pad[8];

sys/dev/ic/ar5008reg.h

862

uint32_t ds_link;

sys/dev/ic/ar5008reg.h

863

uint32_t ds_data;

sys/dev/ic/ar5008reg.h

864

uint32_t ds_ctl0;

sys/dev/ic/ar5008reg.h

865

uint32_t ds_ctl1;

sys/dev/ic/ar5008reg.h

866

uint32_t ds_status0;

sys/dev/ic/ar5008reg.h

867

uint32_t ds_status1;

sys/dev/ic/ar5008reg.h

868

uint32_t ds_status2;

sys/dev/ic/ar5008reg.h

869

uint32_t ds_status3;

sys/dev/ic/ar5008reg.h

870

uint32_t ds_status4;

sys/dev/ic/ar5008reg.h

871

uint32_t ds_status5;

sys/dev/ic/ar5008reg.h

872

uint32_t ds_status6;

sys/dev/ic/ar5008reg.h

873

uint32_t ds_status7;

sys/dev/ic/ar5008reg.h

874

uint32_t ds_status8;

sys/dev/ic/ar5008reg.h

879

uint32_t pad[3];

sys/dev/ic/ar5008reg.h

998

uint32_t binBuildNumber;

sys/dev/ic/ar5416.c

186

uint32_t phy, reg;

sys/dev/ic/ar5416.c

187

uint32_t freq = c->ic_freq;

sys/dev/ic/ar5416.c

240

static const uint32_t chainoffset[] = { 0x0000, 0x2000, 0x1000 };

sys/dev/ic/ar5416.c

243

uint32_t reg, offset;

sys/dev/ic/ar5416.c

429

static const uint32_t chainoffset[] = { 0x0000, 0x2000, 0x1000 };

sys/dev/ic/ar5416.c

436

uint32_t reg, offset;

sys/dev/ic/ar5416.c

762

ar5416_rw_rfbits(uint32_t *buf, int col, int off, uint32_t val, int nbits)

sys/dev/ic/ar5416.c

783

uint32_t *rwbank6tpc)

sys/dev/ic/ar5416.c

809

const uint32_t *bank6tpc;

sys/dev/ic/ar5416.c

82

void ar5416_rw_rfbits(uint32_t *, int, int, uint32_t, int);

sys/dev/ic/ar5416.c

836

uint32_t *rwbank6tpc = sc->rwbuf;

sys/dev/ic/ar5416.c

839

memcpy(rwbank6tpc, bank6tpc, 32 * sizeof(uint32_t));

sys/dev/ic/ar5416.c

84

uint32_t *);

sys/dev/ic/ar5416.c

860

const uint32_t *pvals;

sys/dev/ic/ar5416.c

878

uint32_t *rwbank6 = sc->rwbuf;

sys/dev/ic/ar5416.c

89

uint32_t *);

sys/dev/ic/ar5416.c

909

uint32_t *addac)

sys/dev/ic/ar5416.c

945

const uint32_t *pvals;

sys/dev/ic/ar5416.c

949

uint32_t *rwaddac = sc->rwbuf;

sys/dev/ic/ar5416.c

952

memcpy(rwaddac, addac->vals, addac->nvals * sizeof(uint32_t));

sys/dev/ic/ar5416reg.h

196

static const uint32_t ar5416_vals_5g20[] = {

sys/dev/ic/ar5416reg.h

212

static const uint32_t ar5416_vals_5g40[] = {

sys/dev/ic/ar5416reg.h

228

static const uint32_t ar5416_vals_2g40[] = {

sys/dev/ic/ar5416reg.h

244

static const uint32_t ar5416_vals_2g20[] = {

sys/dev/ic/ar5416reg.h

338

static const uint32_t ar5416_cm_vals[] = {

sys/dev/ic/ar5416reg.h

447

static const uint32_t ar9160_vals_5g20[] = {

sys/dev/ic/ar5416reg.h

463

static const uint32_t ar9160_vals_5g40[] = {

sys/dev/ic/ar5416reg.h

479

static const uint32_t ar9160_vals_2g40[] = {

sys/dev/ic/ar5416reg.h

495

static const uint32_t ar9160_vals_2g20[] = {

sys/dev/ic/ar5416reg.h

57

uint32_t binBuildNumber;

sys/dev/ic/ar5416reg.h

589

static const uint32_t ar9160_cm_vals[] = {

sys/dev/ic/ar5416reg.h

682

static const uint32_t ar5416_bb_rfgain_vals_5g[] = {

sys/dev/ic/ar5416reg.h

698

static const uint32_t ar5416_bb_rfgain_vals_2g[] = {

sys/dev/ic/ar5416reg.h

714

static const uint32_t ar5416_2_1_addac_vals[] = {

sys/dev/ic/ar5416reg.h

730

static const uint32_t ar5416_2_2_addac_vals[] = {

sys/dev/ic/ar5416reg.h

746

static const uint32_t ar9160_1_0_addac_vals[] = {

sys/dev/ic/ar5416reg.h

761

static const uint32_t ar9160_1_1_addac_vals[] = {

sys/dev/ic/ar5416reg.h

776

static const uint32_t ar5416_bank6tpc_vals[] = {

sys/dev/ic/ar5416reg.h

786

static const uint32_t ar9160_bank6tpc_vals[] = {

sys/dev/ic/ar5416reg.h

796

static const uint32_t ar5416_bank6_vals[] = {

sys/dev/ic/ar5416reg.h

80

uint32_t antCtrlChain[AR5416_MAX_CHAINS];

sys/dev/ic/ar5416reg.h

81

uint32_t antCtrlCommon;

sys/dev/ic/ar5416reg.h

810

static const uint32_t ar5416_serdes_regs[] = {

sys/dev/ic/ar5416reg.h

823

static const uint32_t ar5416_serdes_vals[] = {

sys/dev/ic/ar5xxx.h

1377

(((uint32_t)(_val) << _flags##_S) & (_flags))

sys/dev/ic/ar5xxx.h

1379

(((uint32_t)(_val) & (_flags)) >> _flags##_S)

sys/dev/ic/ar9003.c

1188

uint32_t sum;

sys/dev/ic/ar9003.c

121

void ar9003_force_txgain(struct athn_softc *, uint32_t);

sys/dev/ic/ar9003.c

124

int ar9003_compute_predistortion(struct athn_softc *, const uint32_t *,

sys/dev/ic/ar9003.c

125

const uint32_t *);

sys/dev/ic/ar9003.c

1312

uint32_t intr, intr2, intr5, sync;

sys/dev/ic/ar9003.c

1405

uint32_t sum;

sys/dev/ic/ar9003.c

154

void athn_get_delta_slope(uint32_t, uint32_t *, uint32_t *);

sys/dev/ic/ar9003.c

1772

uint32_t reg;

sys/dev/ic/ar9003.c

1784

static __inline uint32_t

sys/dev/ic/ar9003.c

1787

uint32_t delay;

sys/dev/ic/ar9003.c

1828

uint32_t phy;

sys/dev/ic/ar9003.c

1856

uint32_t coeff, exp, man, reg;

sys/dev/ic/ar9003.c

1891

uint32_t synth_delay;

sys/dev/ic/ar9003.c

1943

uint32_t reg;

sys/dev/ic/ar9003.c

1961

uint32_t reg;

sys/dev/ic/ar9003.c

2036

uint32_t agc_nfcal;

sys/dev/ic/ar9003.c

2077

uint32_t reg;

sys/dev/ic/ar9003.c

2121

uint32_t reg;

sys/dev/ic/ar9003.c

2155

uint32_t reg, i_coff_denom, q_coff_denom;

sys/dev/ic/ar9003.c

2340

uint32_t reg;

sys/dev/ic/ar9003.c

235

ar9003_read_eep_word(struct athn_softc *sc, uint32_t addr, uint16_t *val)

sys/dev/ic/ar9003.c

237

uint32_t reg;

sys/dev/ic/ar9003.c

2430

uint32_t reg, ht20mask, ht40mask;

sys/dev/ic/ar9003.c

2544

uint32_t reg;

sys/dev/ic/ar9003.c

2574

ar9003_force_txgain(struct athn_softc *sc, uint32_t txgain)

sys/dev/ic/ar9003.c

2576

uint32_t reg;

sys/dev/ic/ar9003.c

259

ar9003_read_eep_data(struct athn_softc *sc, uint32_t addr, void *buf, int len)

sys/dev/ic/ar9003.c

2673

ar9003_compute_predistortion(struct athn_softc *sc, const uint32_t *lo,

sys/dev/ic/ar9003.c

2674

const uint32_t *hi)

sys/dev/ic/ar9003.c

2924

uint32_t reg;

sys/dev/ic/ar9003.c

296

ar9003_read_otp_word(struct athn_softc *sc, uint32_t addr, uint32_t *val)

sys/dev/ic/ar9003.c

2966

uint32_t lo[48], hi[48];

sys/dev/ic/ar9003.c

298

uint32_t reg;

sys/dev/ic/ar9003.c

3071

#define X(x) ((uint32_t)(x) << 2)

sys/dev/ic/ar9003.c

3073

const uint32_t *pvals;

sys/dev/ic/ar9003.c

3089

#define X(x) ((uint32_t)(x) << 2)

sys/dev/ic/ar9003.c

3091

const uint32_t *pvals;

sys/dev/ic/ar9003.c

3108

#define X(x) ((uint32_t)(x) << 2)

sys/dev/ic/ar9003.c

3111

const uint32_t *pvals;

sys/dev/ic/ar9003.c

3112

uint32_t reg;

sys/dev/ic/ar9003.c

318

ar9003_read_otp_data(struct athn_softc *sc, uint32_t addr, void *buf, int len)

sys/dev/ic/ar9003.c

321

uint32_t val;

sys/dev/ic/ar9003.c

3265

uint32_t reg;

sys/dev/ic/ar9003.c

3285

uint32_t reg;

sys/dev/ic/ar9003.c

3314

uint32_t reg;

sys/dev/ic/ar9003.c

3343

uint32_t reg;

sys/dev/ic/ar9003.c

3354

uint32_t reg;

sys/dev/ic/ar9003.c

3365

uint32_t reg;

sys/dev/ic/ar9003.c

341

uint32_t hdr;

sys/dev/ic/ar9003.c

431

uint32_t hdr;

sys/dev/ic/ar9003.c

511

uint32_t reg;

sys/dev/ic/ar9003.c

526

uint32_t reg;

sys/dev/ic/ar9003.c

538

uint32_t reg;

sys/dev/ic/ar9003.c

559

uint32_t reg;

sys/dev/ic/ar9003.c

63

int ar9003_read_eep_word(struct athn_softc *, uint32_t, uint16_t *);

sys/dev/ic/ar9003.c

64

int ar9003_read_eep_data(struct athn_softc *, uint32_t, void *, int);

sys/dev/ic/ar9003.c

65

int ar9003_read_otp_word(struct athn_softc *, uint32_t, uint32_t *);

sys/dev/ic/ar9003.c

66

int ar9003_read_otp_data(struct athn_softc *, uint32_t, void *, int);

sys/dev/ic/ar9003.c

816

uint32_t reg;

sys/dev/ic/ar9003.c

860

uint32_t tstamp;

sys/dev/ic/ar9003reg.h

1104

uint32_t ds_info;

sys/dev/ic/ar9003reg.h

1105

uint32_t ds_status1;

sys/dev/ic/ar9003reg.h

1106

uint32_t ds_status2;

sys/dev/ic/ar9003reg.h

1107

uint32_t ds_status3;

sys/dev/ic/ar9003reg.h

1108

uint32_t ds_status4;

sys/dev/ic/ar9003reg.h

1109

uint32_t ds_status5;

sys/dev/ic/ar9003reg.h

1110

uint32_t ds_status6;

sys/dev/ic/ar9003reg.h

1111

uint32_t ds_status7;

sys/dev/ic/ar9003reg.h

1112

uint32_t ds_status8;

sys/dev/ic/ar9003reg.h

1139

uint32_t ds_info;

sys/dev/ic/ar9003reg.h

1140

uint32_t ds_status1;

sys/dev/ic/ar9003reg.h

1141

uint32_t ds_status2;

sys/dev/ic/ar9003reg.h

1142

uint32_t ds_status3;

sys/dev/ic/ar9003reg.h

1143

uint32_t ds_status4;

sys/dev/ic/ar9003reg.h

1144

uint32_t ds_status5;

sys/dev/ic/ar9003reg.h

1145

uint32_t ds_status6;

sys/dev/ic/ar9003reg.h

1146

uint32_t ds_status7;

sys/dev/ic/ar9003reg.h

1147

uint32_t ds_status8;

sys/dev/ic/ar9003reg.h

1148

uint32_t ds_status9;

sys/dev/ic/ar9003reg.h

1149

uint32_t ds_status10;

sys/dev/ic/ar9003reg.h

1150

uint32_t ds_status11;

sys/dev/ic/ar9003reg.h

949

uint32_t ds_info;

sys/dev/ic/ar9003reg.h

950

uint32_t ds_link;

sys/dev/ic/ar9003reg.h

952

uint32_t ds_data;

sys/dev/ic/ar9003reg.h

953

uint32_t ds_ctl;

sys/dev/ic/ar9003reg.h

955

uint32_t ds_ctl10;

sys/dev/ic/ar9003reg.h

956

uint32_t ds_ctl11;

sys/dev/ic/ar9003reg.h

957

uint32_t ds_ctl12;

sys/dev/ic/ar9003reg.h

958

uint32_t ds_ctl13;

sys/dev/ic/ar9003reg.h

959

uint32_t ds_ctl14;

sys/dev/ic/ar9003reg.h

960

uint32_t ds_ctl15;

sys/dev/ic/ar9003reg.h

961

uint32_t ds_ctl16;

sys/dev/ic/ar9003reg.h

962

uint32_t ds_ctl17;

sys/dev/ic/ar9003reg.h

963

uint32_t ds_ctl18;

sys/dev/ic/ar9003reg.h

964

uint32_t ds_ctl19;

sys/dev/ic/ar9003reg.h

965

uint32_t ds_ctl20;

sys/dev/ic/ar9003reg.h

966

uint32_t ds_ctl21;

sys/dev/ic/ar9003reg.h

967

uint32_t ds_ctl22;

sys/dev/ic/ar9003reg.h

972

uint32_t pad[9];

sys/dev/ic/ar9280.c

179

uint32_t phy, reg, ndiv = 0;

sys/dev/ic/ar9280.c

180

uint32_t freq = c->ic_freq;

sys/dev/ic/ar9280.c

243

static const uint32_t chainoffset[] = { 0x0000, 0x2000, 0x1000 };

sys/dev/ic/ar9280.c

246

uint32_t reg, offset;

sys/dev/ic/ar9280.c

545

const uint32_t *pvals;

sys/dev/ic/ar9280.c

560

const uint32_t *pvals;

sys/dev/ic/ar9280.c

574

uint32_t reg;

sys/dev/ic/ar9280.c

591

uint32_t reg;

sys/dev/ic/ar9280reg.h

183

static const uint32_t ar9280_2_0_cm_vals[] = {

sys/dev/ic/ar9280reg.h

260

static const uint32_t ar9280_2_0_fast_clock_vals_5g20[] = {

sys/dev/ic/ar9280reg.h

266

static const uint32_t ar9280_2_0_fast_clock_vals_5g40[] = {

sys/dev/ic/ar9280reg.h

301

static const uint32_t ar9280_2_0_tx_gain_vals_5g[] = {

sys/dev/ic/ar9280reg.h

311

static const uint32_t ar9280_2_0_tx_gain_vals_2g[] = {

sys/dev/ic/ar9280reg.h

328

static const uint32_t ar9280_2_0_tx_gain_high_power_vals_5g[] = {

sys/dev/ic/ar9280reg.h

338

static const uint32_t ar9280_2_0_tx_gain_high_power_vals_2g[] = {

sys/dev/ic/ar9280reg.h

387

static const uint32_t ar9280_2_0_rx_gain_vals_5g[] = {

sys/dev/ic/ar9280reg.h

416

static const uint32_t ar9280_2_0_rx_gain_vals_2g[] = {

sys/dev/ic/ar9280reg.h

452

static const uint32_t ar9280_2_0_rx_gain_13db_backoff_vals_5g[] = {

sys/dev/ic/ar9280reg.h

481

static const uint32_t ar9280_2_0_rx_gain_13db_backoff_vals_2g[] = {

sys/dev/ic/ar9280reg.h

517

static const uint32_t ar9280_2_0_rx_gain_23db_backoff_vals_5g[] = {

sys/dev/ic/ar9280reg.h

546

static const uint32_t ar9280_2_0_rx_gain_23db_backoff_vals_2g[] = {

sys/dev/ic/ar9280reg.h

586

static const uint32_t ar9280_2_0_serdes_regs[] = {

sys/dev/ic/ar9280reg.h

599

static const uint32_t ar9280_2_0_serdes_vals[] = {

sys/dev/ic/ar9280reg.h

60

static const uint32_t ar9280_2_0_vals_5g20[] = {

sys/dev/ic/ar9280reg.h

73

static const uint32_t ar9280_2_0_vals_5g40[] = {

sys/dev/ic/ar9280reg.h

86

static const uint32_t ar9280_2_0_vals_2g40[] = {

sys/dev/ic/ar9280reg.h

99

static const uint32_t ar9280_2_0_vals_2g20[] = {

sys/dev/ic/ar9285.c

200

uint32_t reg, offset = 0x1000;

sys/dev/ic/ar9285.c

420

uint32_t svg[7], reg, ccomp_svg;

sys/dev/ic/ar9285.c

523

uint32_t svg[7], reg, rf2g3_svg;

sys/dev/ic/ar9285.c

660

uint32_t reg, mask, clcgain, rf2g5_svg;

sys/dev/ic/ar9285.c

749

uint32_t reg;

sys/dev/ic/ar9285reg.h

1017

static const uint32_t ar9285_2_0_tx_gain_high_power_vals_2g[] = {

sys/dev/ic/ar9285reg.h

1049

static const uint32_t ar9271_tx_gain_vals_2g[] = {

sys/dev/ic/ar9285reg.h

1066

static const uint32_t ar9271_tx_gain_high_power_vals_2g[] = {

sys/dev/ic/ar9285reg.h

182

uint32_t binBuildNumber;

sys/dev/ic/ar9285reg.h

189

uint32_t antCtrlChain;

sys/dev/ic/ar9285reg.h

190

uint32_t antCtrlCommon;

sys/dev/ic/ar9285reg.h

327

static const uint32_t ar9285_1_2_vals_2g40[] = {

sys/dev/ic/ar9285reg.h

391

static const uint32_t ar9285_1_2_vals_2g20[] = {

sys/dev/ic/ar9285reg.h

522

static const uint32_t ar9285_1_2_cm_vals[] = {

sys/dev/ic/ar9285reg.h

669

static const uint32_t ar9271_vals_2g40[] = {

sys/dev/ic/ar9285reg.h

733

static const uint32_t ar9271_vals_2g20[] = {

sys/dev/ic/ar9285reg.h

865

static const uint32_t ar9271_cm_vals[] = {

sys/dev/ic/ar9285reg.h

960

static const uint32_t ar9285_1_2_tx_gain_vals_2g[] = {

sys/dev/ic/ar9285reg.h

978

static const uint32_t ar9285_1_2_tx_gain_high_power_vals_2g[] = {

sys/dev/ic/ar9285reg.h

999

static const uint32_t ar9285_2_0_tx_gain_vals_2g[] = {

sys/dev/ic/ar9287.c

173

uint32_t reg, offset;

sys/dev/ic/ar9287.c

350

uint32_t reg, offset;

sys/dev/ic/ar9287.c

541

uint32_t reg;

sys/dev/ic/ar9287.c

558

uint32_t reg;

sys/dev/ic/ar9287.c

606

uint32_t reg;

sys/dev/ic/ar9287reg.h

103

uint32_t antCtrlChain[AR9287_MAX_CHAINS];

sys/dev/ic/ar9287reg.h

104

uint32_t antCtrlCommon;

sys/dev/ic/ar9287reg.h

191

static const uint32_t ar9287_1_1_vals_2g40[] = {

sys/dev/ic/ar9287reg.h

203

static const uint32_t ar9287_1_1_vals_2g20[] = {

sys/dev/ic/ar9287reg.h

291

static const uint32_t ar9287_1_1_cm_vals[] = {

sys/dev/ic/ar9287reg.h

394

static const uint32_t ar9287_1_1_tx_gain_vals_2g[] = {

sys/dev/ic/ar9287reg.h

471

static const uint32_t ar9287_1_1_rx_gain_vals_2g[] = {

sys/dev/ic/ar9287reg.h

92

uint32_t binBuildNumber;

sys/dev/ic/ar9380.c

246

uint32_t *ht20mask, uint32_t *ht40mask)

sys/dev/ic/ar9380.c

263

uint32_t freq = c->ic_freq;

sys/dev/ic/ar9380.c

264

uint32_t chansel, phy;

sys/dev/ic/ar9380.c

301

uint32_t reg;

sys/dev/ic/ar9380.c

462

ar9485_pmu_write(struct athn_softc *sc, uint32_t addr, uint32_t val)

sys/dev/ic/ar9380.c

484

uint32_t reg;

sys/dev/ic/ar9380.c

511

uint32_t reg;

sys/dev/ic/ar9380.c

551

uint32_t reg;

sys/dev/ic/ar9380.c

68

uint32_t *, uint32_t *);

sys/dev/ic/ar9380.c

72

int ar9485_pmu_write(struct athn_softc *, uint32_t, uint32_t);

sys/dev/ic/ar9380.c

841

uint32_t reg;

sys/dev/ic/ar9380reg.h

1077

static const uint32_t ar9380_2_2_fast_clock_vals_5g20[] = {

sys/dev/ic/ar9380reg.h

1082

static const uint32_t ar9380_2_2_fast_clock_vals_5g40[] = {

sys/dev/ic/ar9380reg.h

1121

static const uint32_t ar9485_1_1_vals_2g40[] = {

sys/dev/ic/ar9380reg.h

1135

static const uint32_t ar9485_1_1_vals_2g20[] = {

sys/dev/ic/ar9380reg.h

114

uint32_t swreg;

sys/dev/ic/ar9380reg.h

118

uint32_t antCtrlCommon;

sys/dev/ic/ar9380reg.h

119

uint32_t antCtrlCommon2;

sys/dev/ic/ar9380reg.h

1228

static const uint32_t ar9485_1_1_cm_vals[] = {

sys/dev/ic/ar9380reg.h

1346

static const uint32_t ar9380_2_2_tx_gain_vals_5g[] = {

sys/dev/ic/ar9380reg.h

1370

static const uint32_t ar9380_2_2_tx_gain_vals_2g[] = {

sys/dev/ic/ar9380reg.h

1404

static const uint32_t ar9380_2_2_tx_gain_high_ob_db_vals_5g[] = {

sys/dev/ic/ar9380reg.h

142

uint32_t papdRateMaskHt20;

sys/dev/ic/ar9380reg.h

1428

static const uint32_t ar9380_2_2_tx_gain_high_ob_db_vals_2g[] = {

sys/dev/ic/ar9380reg.h

143

uint32_t papdRateMaskHt40;

sys/dev/ic/ar9380reg.h

1462

static const uint32_t ar9380_2_2_tx_gain_low_ob_db_vals_5g[] = {

sys/dev/ic/ar9380reg.h

1486

static const uint32_t ar9380_2_2_tx_gain_low_ob_db_vals_2g[] = {

sys/dev/ic/ar9380reg.h

1520

static const uint32_t ar9380_2_2_tx_gain_high_power_vals_5g[] = {

sys/dev/ic/ar9380reg.h

1544

static const uint32_t ar9380_2_2_tx_gain_high_power_vals_2g[] = {

sys/dev/ic/ar9380reg.h

1595

static const uint32_t ar9485_1_1_tx_gain_vals_2g[] = {

sys/dev/ic/ar9380reg.h

1677

static const uint32_t ar9380_2_2_rx_gain_vals[] = {

sys/dev/ic/ar9380reg.h

1742

static const uint32_t ar9380_2_2_rx_gain_wo_xlna_vals[] = {

sys/dev/ic/ar9380reg.h

1836

static const uint32_t ar9485_1_1_rx_gain_vals[] = {

sys/dev/ic/ar9380reg.h

1876

static const uint32_t ar9380_2_2_serdes_regs[] = {

sys/dev/ic/ar9380reg.h

1882

static const uint32_t ar9380_2_2_serdes_vals[] = {

sys/dev/ic/ar9380reg.h

1894

static const uint32_t ar9485_1_1_serdes_regs[] = {

sys/dev/ic/ar9380reg.h

1900

static const uint32_t ar9485_1_1_serdes_vals[] = {

sys/dev/ic/ar9380reg.h

814

static const uint32_t ar9380_2_2_vals_5g20[] = {

sys/dev/ic/ar9380reg.h

831

static const uint32_t ar9380_2_2_vals_5g40[] = {

sys/dev/ic/ar9380reg.h

848

static const uint32_t ar9380_2_2_vals_2g40[] = {

sys/dev/ic/ar9380reg.h

865

static const uint32_t ar9380_2_2_vals_2g20[] = {

sys/dev/ic/ar9380reg.h

977

static const uint32_t ar9380_2_2_cm_vals[] = {

sys/dev/ic/athn.c

1023

uint32_t lo, hi, unicast;

sys/dev/ic/athn.c

1138

uint32_t reg;

sys/dev/ic/athn.c

1177

uint32_t reg;

sys/dev/ic/athn.c

1665

uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2;

sys/dev/ic/athn.c

1773

uint32_t reg;

sys/dev/ic/athn.c

1816

uint32_t reg, ftrig;

sys/dev/ic/athn.c

1897

uint32_t tsflo;

sys/dev/ic/athn.c

2031

uint32_t tsfhi, tsflo, tsftu, reg;

sys/dev/ic/athn.c

2032

uint32_t intval, next_tbtt, next_dtim;

sys/dev/ic/athn.c

2100

uint32_t intval, next_tbtt;

sys/dev/ic/athn.c

2127

uint32_t reg;

sys/dev/ic/athn.c

2173

uint32_t mask2;

sys/dev/ic/athn.c

2244

uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi;

sys/dev/ic/athn.c

2593

uint32_t reg;

sys/dev/ic/athn.c

2762

uint32_t reg = AR_READ(sc, AR_TIME_OUT);

sys/dev/ic/athn.c

2773

uint32_t reg = AR_READ(sc, AR_TIME_OUT);

sys/dev/ic/athn.c

2788

uint32_t reg = AR_READ(sc, AR_USEC);

sys/dev/ic/athn.c

2897

uint32_t val, lo, hi;

sys/dev/ic/athn.c

478

uint32_t rfilt;

sys/dev/ic/athn.c

529

athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt)

sys/dev/ic/athn.c

565

uint32_t reg;

sys/dev/ic/athn.c

75

void athn_set_rxfilter(struct athn_softc *, uint32_t);

sys/dev/ic/athn.c

755

uint32_t pll;

sys/dev/ic/athn.c

832

static const uint32_t ar_nonpcie_serdes_regs[] = {

sys/dev/ic/athn.c

845

static const uint32_t ar_nonpcie_serdes_vals[] = {

sys/dev/ic/athn.c

91

void athn_get_delta_slope(uint32_t, uint32_t *, uint32_t *);

sys/dev/ic/athn.c

968

athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa)

sys/dev/ic/athn.c

971

uint32_t exp, man;

sys/dev/ic/athnreg.h

1491

(((uint32_t)(val) & field##_M) >> field##_S)

sys/dev/ic/athnreg.h

1495

(((uint32_t)(val) << field##_S) & field##_M)

sys/dev/ic/athnvar.h

183

const uint32_t *vals_5g20;

sys/dev/ic/athnvar.h

184

const uint32_t *vals_5g40;

sys/dev/ic/athnvar.h

185

const uint32_t *vals_2g40;

sys/dev/ic/athnvar.h

186

const uint32_t *vals_2g20;

sys/dev/ic/athnvar.h

189

const uint32_t *cmvals;

sys/dev/ic/athnvar.h

192

const uint32_t *fastvals_5g20;

sys/dev/ic/athnvar.h

193

const uint32_t *fastvals_5g40;

sys/dev/ic/athnvar.h

199

const uint32_t *vals_5g;

sys/dev/ic/athnvar.h

200

const uint32_t *vals_2g;

sys/dev/ic/athnvar.h

205

const uint32_t *vals;

sys/dev/ic/athnvar.h

210

const uint32_t *regs;

sys/dev/ic/athnvar.h

211

const uint32_t *vals;

sys/dev/ic/athnvar.h

318

uint32_t listen_time;

sys/dev/ic/athnvar.h

320

uint32_t ofdm_trig_high;

sys/dev/ic/athnvar.h

321

uint32_t ofdm_trig_low;

sys/dev/ic/athnvar.h

326

uint32_t ofdm_phy_err_base;

sys/dev/ic/athnvar.h

327

uint32_t cck_phy_err_base;

sys/dev/ic/athnvar.h

328

uint32_t ofdm_phy_err_count;

sys/dev/ic/athnvar.h

329

uint32_t cck_phy_err_count;

sys/dev/ic/athnvar.h

331

uint32_t cyccnt;

sys/dev/ic/athnvar.h

332

uint32_t txfcnt;

sys/dev/ic/athnvar.h

333

uint32_t rxfcnt;

sys/dev/ic/athnvar.h

337

uint32_t pwr_meas_i;

sys/dev/ic/athnvar.h

338

uint32_t pwr_meas_q;

sys/dev/ic/athnvar.h

343

uint32_t pwr_meas_odd_i;

sys/dev/ic/athnvar.h

344

uint32_t pwr_meas_even_i;

sys/dev/ic/athnvar.h

345

uint32_t pwr_meas_odd_q;

sys/dev/ic/athnvar.h

346

uint32_t pwr_meas_even_q;

sys/dev/ic/athnvar.h

362

uint32_t (*read)(struct athn_softc *, uint32_t);

sys/dev/ic/athnvar.h

363

void (*write)(struct athn_softc *, uint32_t, uint32_t);

sys/dev/ic/athnvar.h

377

int (*read_rom_data)(struct athn_softc *, uint32_t, void *, int);

sys/dev/ic/athnvar.h

418

struct ieee80211_channel *, uint32_t *, uint32_t *);

sys/dev/ic/athnvar.h

471

uint32_t isync;

sys/dev/ic/athnvar.h

472

uint32_t imask;

sys/dev/ic/athnvar.h

503

uint32_t txgain[AR9003_TX_GAIN_TABLE_SIZE];

sys/dev/ic/athnvar.h

511

uint32_t rwbuf[64];

sys/dev/ic/athnvar.h

517

uint32_t eep_base;

sys/dev/ic/athnvar.h

518

uint32_t eep_size;

sys/dev/ic/athnvar.h

543

uint32_t workaround;

sys/dev/ic/athnvar.h

544

uint32_t obs_off;

sys/dev/ic/athnvar.h

545

uint32_t gpio_input_en_off;

sys/dev/ic/atw.c

1001

uint32_t wcsr;

sys/dev/ic/atw.c

1016

uint32_t cmdr;

sys/dev/ic/atw.c

1029

uint32_t tofs2;

sys/dev/ic/atw.c

1070

uint32_t test1;

sys/dev/ic/atw.c

1094

uint32_t cfpp;

sys/dev/ic/atw.c

1122

uint32_t ifst;

sys/dev/ic/atw.c

1155

uint32_t mmiraddr2;

sys/dev/ic/atw.c

1916

uint32_t bits, mask, reg;

sys/dev/ic/atw.c

2309

uint32_t bpli;

sys/dev/ic/atw.c

2311

uint32_t bcnt, cap0, cap1, capinfo;

sys/dev/ic/atw.c

234

static __inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, uint32_t);

sys/dev/ic/atw.c

237

int atw_compute_duration1(int, int, uint32_t, int, struct atw_duration *);

sys/dev/ic/atw.c

2379

static __inline uint32_t

sys/dev/ic/atw.c

238

int atw_compute_duration(struct ieee80211_frame *, int, uint32_t, int,

sys/dev/ic/atw.c

2380

atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival)

sys/dev/ic/atw.c

2402

uint32_t tsfth, tsftl;

sys/dev/ic/atw.c

2425

uint32_t ival, past_even, tbtt, tsfth, tsftl;

sys/dev/ic/atw.c

3313

uint32_t test1, rra, rwa;

sys/dev/ic/atw.c

3374

atw_compute_duration1(int len, int use_ack, uint32_t flags, int rate,

sys/dev/ic/atw.c

3460

atw_compute_duration(struct ieee80211_frame *wh, int len, uint32_t flags,

sys/dev/ic/atw.c

917

uint32_t lpc;

sys/dev/ic/bcm2835_dmac.h

100

uint32_t cb_source_ad;

sys/dev/ic/bcm2835_dmac.h

101

uint32_t cb_dest_ad;

sys/dev/ic/bcm2835_dmac.h

102

uint32_t cb_txfr_len;

sys/dev/ic/bcm2835_dmac.h

105

uint32_t cb_stride;

sys/dev/ic/bcm2835_dmac.h

108

uint32_t cb_nextconbk;

sys/dev/ic/bcm2835_dmac.h

109

uint32_t cb_padding[2];

sys/dev/ic/bcm2835_dmac.h

120

void (*)(uint32_t, uint32_t, void *), void *);

sys/dev/ic/bcm2835_dmac.h

83

uint32_t cb_ti;

sys/dev/ic/bcm2835_mbox.h

95

void bcmmbox_read(uint8_t chan, uint32_t *data);

sys/dev/ic/bcm2835_mbox.h

96

void bcmmbox_write(uint8_t chan, uint32_t data);

sys/dev/ic/bcm2835_mbox.h

98

int bcmmbox_post(uint8_t, void *, size_t, uint32_t *);

sys/dev/ic/bcm2835_vcprop.h

125

uint32_t vpt_len;

sys/dev/ic/bcm2835_vcprop.h

126

uint32_t vpt_rcode;

sys/dev/ic/bcm2835_vcprop.h

135

uint32_t base;

sys/dev/ic/bcm2835_vcprop.h

136

uint32_t size;

sys/dev/ic/bcm2835_vcprop.h

147

uint32_t rev;

sys/dev/ic/bcm2835_vcprop.h

152

uint32_t model;

sys/dev/ic/bcm2835_vcprop.h

157

uint32_t rev;

sys/dev/ic/bcm2835_vcprop.h

204

uint32_t pclk;

sys/dev/ic/bcm2835_vcprop.h

205

uint32_t cclk;

sys/dev/ic/bcm2835_vcprop.h

224

uint32_t mask;

sys/dev/ic/bcm2835_vcprop.h

229

uint32_t id;

sys/dev/ic/bcm2835_vcprop.h

230

uint32_t state;

sys/dev/ic/bcm2835_vcprop.h

235

uint32_t id;

sys/dev/ic/bcm2835_vcprop.h

236

uint32_t rate;

sys/dev/ic/bcm2835_vcprop.h

237

uint32_t noturbo;

sys/dev/ic/bcm2835_vcprop.h

247

uint32_t id;

sys/dev/ic/bcm2835_vcprop.h

248

uint32_t value;

sys/dev/ic/bcm2835_vcprop.h

255

uint32_t id;

sys/dev/ic/bcm2835_vcprop.h

256

uint32_t value;

sys/dev/ic/bcm2835_vcprop.h

270

uint32_t id;

sys/dev/ic/bcm2835_vcprop.h

271

uint32_t data;

sys/dev/ic/bcm2835_vcprop.h

286

uint32_t id;

sys/dev/ic/bcm2835_vcprop.h

287

uint32_t waitusec;

sys/dev/ic/bcm2835_vcprop.h

292

uint32_t id;

sys/dev/ic/bcm2835_vcprop.h

293

uint32_t state;

sys/dev/ic/bcm2835_vcprop.h

298

uint32_t address; /* alignment for request */

sys/dev/ic/bcm2835_vcprop.h

299

uint32_t size;

sys/dev/ic/bcm2835_vcprop.h

307

uint32_t state;

sys/dev/ic/bcm2835_vcprop.h

312

uint32_t width;

sys/dev/ic/bcm2835_vcprop.h

313

uint32_t height;

sys/dev/ic/bcm2835_vcprop.h

318

uint32_t bpp;

sys/dev/ic/bcm2835_vcprop.h

326

uint32_t state;

sys/dev/ic/bcm2835_vcprop.h

331

uint32_t linebytes;

sys/dev/ic/bcm2835_vcprop.h

340

uint32_t state;

sys/dev/ic/bcm2835_vcprop.h

345

uint32_t blockno;

sys/dev/ic/bcm2835_vcprop.h

346

uint32_t status;

sys/dev/ic/bcm2835_vcprop.h

352

uint32_t width;

sys/dev/ic/bcm2835_vcprop.h

353

uint32_t height;

sys/dev/ic/bcm2835_vcprop.h

354

uint32_t format;

sys/dev/ic/bcm2835_vcprop.h

355

uint32_t pixels; /* bus address in VC memory */

sys/dev/ic/bcm2835_vcprop.h

356

uint32_t hotspot_x;

sys/dev/ic/bcm2835_vcprop.h

357

uint32_t hotspot_y;

sys/dev/ic/bcm2835_vcprop.h

362

uint32_t enable; /* 1 - visible */

sys/dev/ic/bcm2835_vcprop.h

363

uint32_t x;

sys/dev/ic/bcm2835_vcprop.h

364

uint32_t y;

sys/dev/ic/bcm2835_vcprop.h

365

uint32_t flags; /* 0 - display coord. 1 - fb coord. */

sys/dev/ic/bcm2835_vcprop.h

370

uint32_t size; /* handle returned here */

sys/dev/ic/bcm2835_vcprop.h

371

uint32_t align;

sys/dev/ic/bcm2835_vcprop.h

372

uint32_t flags;

sys/dev/ic/bcm2835_vcprop.h

390

uint32_t handle; /* bus address returned here */

sys/dev/ic/bcm2835_vcprop.h

395

uint32_t deviceaddress;

sys/dev/ic/bcm2835_vcprop.h

399

uint32_t vpb_len;

sys/dev/ic/bcm2835_vcprop.h

400

uint32_t vpb_rcode;

sys/dev/ic/bcm2835_vcprop.h

57

uint32_t vpt_tag;

sys/dev/ic/bcmgenet.c

156

uint32_t val;

sys/dev/ic/bcmgenet.c

195

uint32_t status;

sys/dev/ic/bcmgenet.c

199

WR4(sc, GENET_TX_DESC_ADDRESS_LO(index), (uint32_t)paddr);

sys/dev/ic/bcmgenet.c

200

WR4(sc, GENET_TX_DESC_ADDRESS_HI(index), (uint32_t)(paddr >> 32));

sys/dev/ic/bcmgenet.c

209

uint32_t flags;

sys/dev/ic/bcmgenet.c

265

WR4(sc, GENET_RX_DESC_ADDRESS_LO(index), (uint32_t)paddr);

sys/dev/ic/bcmgenet.c

266

WR4(sc, GENET_RX_DESC_ADDRESS_HI(index), (uint32_t)(paddr >> 32));

sys/dev/ic/bcmgenet.c

307

uint32_t cidx, index, total;

sys/dev/ic/bcmgenet.c

382

uint32_t addr0 = (ea[0] << 8) | ea[1];

sys/dev/ic/bcmgenet.c

383

uint32_t addr1 = (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5];

sys/dev/ic/bcmgenet.c

396

uint32_t cmd, mdf_ctrl;

sys/dev/ic/bcmgenet.c

438

uint32_t val;

sys/dev/ic/bcmgenet.c

471

uint32_t val;

sys/dev/ic/bcmgenet.c

511

uint32_t val;

sys/dev/ic/bcmgenet.c

588

uint32_t val;

sys/dev/ic/bcmgenet.c

687

uint32_t status, pidx, total;

sys/dev/ic/bcmgenet.c

745

uint32_t queued;

sys/dev/ic/bcmgenet.c

819

uint32_t val;

sys/dev/ic/bcmgenet.c

998

uint32_t maclo, machi;

sys/dev/ic/bcmgenetvar.h

55

uint32_t cidx, pidx;

sys/dev/ic/bwfm.c

1046

uint32_t ioctl, reset;

sys/dev/ic/bwfm.c

1063

uint32_t prereset, uint32_t reset)

sys/dev/ic/bwfm.c

1065

uint32_t val;

sys/dev/ic/bwfm.c

1102

uint32_t prereset, uint32_t reset, uint32_t postreset)

sys/dev/ic/bwfm.c

111

int bwfm_fwvar_cmd_get_int(struct bwfm_softc *, int, uint32_t *);

sys/dev/ic/bwfm.c

112

int bwfm_fwvar_cmd_set_int(struct bwfm_softc *, int, uint32_t);

sys/dev/ic/bwfm.c

1130

uint32_t erom, val, base, wrap;

sys/dev/ic/bwfm.c

115

int bwfm_fwvar_var_get_int(struct bwfm_softc *, char *, uint32_t *);

sys/dev/ic/bwfm.c

116

int bwfm_fwvar_var_set_int(struct bwfm_softc *, char *, uint32_t);

sys/dev/ic/bwfm.c

118

uint32_t bwfm_chan2spec(struct bwfm_softc *, struct ieee80211_channel *);

sys/dev/ic/bwfm.c

1182

bwfm_chip_dmp_get_regaddr(struct bwfm_softc *sc, uint32_t *erom,

sys/dev/ic/bwfm.c

1183

uint32_t *base, uint32_t *wrap)

sys/dev/ic/bwfm.c

1187

uint32_t val;

sys/dev/ic/bwfm.c

119

uint32_t bwfm_chan2spec_d11n(struct bwfm_softc *, struct ieee80211_channel *);

sys/dev/ic/bwfm.c

120

uint32_t bwfm_chan2spec_d11ac(struct bwfm_softc *, struct ieee80211_channel *);

sys/dev/ic/bwfm.c

121

uint32_t bwfm_spec2chan(struct bwfm_softc *, uint32_t);

sys/dev/ic/bwfm.c

122

uint32_t bwfm_spec2chan_d11n(struct bwfm_softc *, uint32_t);

sys/dev/ic/bwfm.c

123

uint32_t bwfm_spec2chan_d11ac(struct bwfm_softc *, uint32_t);

sys/dev/ic/bwfm.c

1246

bwfm_chip_set_active(struct bwfm_softc *sc, uint32_t rstvec)

sys/dev/ic/bwfm.c

1275

bwfm_chip_cr4_set_active(struct bwfm_softc *sc, uint32_t rstvec)

sys/dev/ic/bwfm.c

1291

uint32_t val;

sys/dev/ic/bwfm.c

1310

bwfm_chip_ca7_set_active(struct bwfm_softc *sc, uint32_t rstvec)

sys/dev/ic/bwfm.c

1326

uint32_t val;

sys/dev/ic/bwfm.c

1387

uint32_t reg;

sys/dev/ic/bwfm.c

1449

uint32_t coreinfo, nb, lss, banksize, bankinfo;

sys/dev/ic/bwfm.c

1450

uint32_t ramsize = 0, srsize = 0;

sys/dev/ic/bwfm.c

1505

uint32_t coreinfo, nb, banksize, bankinfo;

sys/dev/ic/bwfm.c

1506

uint32_t ramsize = 0;

sys/dev/ic/bwfm.c

1535

uint32_t cap, nab, nbb, totb, bxinfo, blksize, ramsize = 0;

sys/dev/ic/bwfm.c

1798

bwfm_fwvar_cmd_get_int(struct bwfm_softc *sc, int cmd, uint32_t *data)

sys/dev/ic/bwfm.c

1807

bwfm_fwvar_cmd_set_int(struct bwfm_softc *sc, int cmd, uint32_t data)

sys/dev/ic/bwfm.c

1845

bwfm_fwvar_var_get_int(struct bwfm_softc *sc, char *name, uint32_t *data)

sys/dev/ic/bwfm.c

1854

bwfm_fwvar_var_set_int(struct bwfm_softc *sc, char *name, uint32_t data)

sys/dev/ic/bwfm.c

1861

uint32_t

sys/dev/ic/bwfm.c

1870

uint32_t

sys/dev/ic/bwfm.c

1873

uint32_t chanspec;

sys/dev/ic/bwfm.c

1886

uint32_t

sys/dev/ic/bwfm.c

1889

uint32_t chanspec;

sys/dev/ic/bwfm.c

1902

uint32_t

sys/dev/ic/bwfm.c

1903

bwfm_spec2chan(struct bwfm_softc *sc, uint32_t chanspec)

sys/dev/ic/bwfm.c

1911

uint32_t

sys/dev/ic/bwfm.c

1912

bwfm_spec2chan_d11n(struct bwfm_softc *sc, uint32_t chanspec)

sys/dev/ic/bwfm.c

1914

uint32_t chanidx;

sys/dev/ic/bwfm.c

1938

uint32_t

sys/dev/ic/bwfm.c

1939

bwfm_spec2chan_d11ac(struct bwfm_softc *sc, uint32_t chanspec)

sys/dev/ic/bwfm.c

1941

uint32_t chanidx;

sys/dev/ic/bwfm.c

1997

uint32_t wsec = 0;

sys/dev/ic/bwfm.c

1998

uint32_t wpa = 0;

sys/dev/ic/bwfm.c

2081

uint32_t wsec = 0;

sys/dev/ic/bwfm.c

2082

uint32_t wpa = 0;

sys/dev/ic/bwfm.c

2142

uint32_t nssid = 0, nchan = 0;

sys/dev/ic/bwfm.c

2150

chan_size = roundup(nchan * sizeof(uint16_t), sizeof(uint32_t));

sys/dev/ic/bwfm.c

2200

uint32_t nssid = 0, nchan = 0;

sys/dev/ic/bwfm.c

2208

chan_size = roundup(nchan * sizeof(uint16_t), sizeof(uint32_t));

sys/dev/ic/bwfm.c

2415

uint32_t pktlen, ieslen;

sys/dev/ic/bwfm.c

2454

uint32_t pktlen, ieslen;

sys/dev/ic/bwfm.c

251

uint32_t bandlist[3], tmp;

sys/dev/ic/bwfm.c

2520

uint32_t pktlen;

sys/dev/ic/bwfm.c

2725

uint32_t pktlen, ieslen;

sys/dev/ic/bwfm.c

2855

uint32_t wsec, wsec_enable;

sys/dev/ic/bwfm.c

3013

uint32_t token;

sys/dev/ic/bwfm.c

617

mcastlen = sizeof(uint32_t) + ac->ac_multicnt * ETHER_ADDR_LEN;

sys/dev/ic/bwfm.c

619

htolem32((uint32_t *)mcast, ac->ac_multicnt);

sys/dev/ic/bwfm.c

627

memcpy(mcast + sizeof(uint32_t) + i * ETHER_ADDR_LEN,

sys/dev/ic/bwfm.c

667

bwfm_rate2vhtmcs(int *mcs, int *ss, uint32_t txrate)

sys/dev/ic/bwfm.c

688

bwfm_rate2htmcs(uint32_t txrate)

sys/dev/ic/bwfm.c

711

uint32_t flags;

sys/dev/ic/bwfm.c

713

uint32_t txrate;

sys/dev/ic/bwfm.c

83

uint32_t, uint32_t);

sys/dev/ic/bwfm.c

85

uint32_t, uint32_t, uint32_t);

sys/dev/ic/bwfm.c

87

int bwfm_chip_dmp_get_regaddr(struct bwfm_softc *, uint32_t *,

sys/dev/ic/bwfm.c

88

uint32_t *, uint32_t *);

sys/dev/ic/bwfm.c

888

uint32_t val;

sys/dev/ic/bwfm.c

89

int bwfm_chip_cr4_set_active(struct bwfm_softc *, uint32_t);

sys/dev/ic/bwfm.c

91

int bwfm_chip_ca7_set_active(struct bwfm_softc *, uint32_t);

sys/dev/ic/bwfmreg.h

316

uint32_t cmd;

sys/dev/ic/bwfmreg.h

317

uint32_t len;

sys/dev/ic/bwfmreg.h

318

uint32_t flags;

sys/dev/ic/bwfmreg.h

326

uint32_t status;

sys/dev/ic/bwfmreg.h

347

uint32_t version;

sys/dev/ic/bwfmreg.h

348

uint32_t length;

sys/dev/ic/bwfmreg.h

355

uint32_t nrates;

sys/dev/ic/bwfmreg.h

365

uint32_t nbss_cap;

sys/dev/ic/bwfmreg.h

368

uint32_t reserved32[1];

sys/dev/ic/bwfmreg.h

374

uint32_t ie_length;

sys/dev/ic/bwfmreg.h

384

uint32_t count;

sys/dev/ic/bwfmreg.h

394

uint32_t count;

sys/dev/ic/bwfmreg.h

407

uint32_t flags;

sys/dev/ic/bwfmreg.h

433

uint32_t idle; /* time since data pkt rx'd from sta */

sys/dev/ic/bwfmreg.h

435

uint32_t count; /* # rates in this set */

sys/dev/ic/bwfmreg.h

438

uint32_t in; /* seconds elapsed since associated */

sys/dev/ic/bwfmreg.h

439

uint32_t listen_interval_inms; /* Min Listen interval in ms for STA */

sys/dev/ic/bwfmreg.h

442

uint32_t tx_pkts; /* # of packets transmitted */

sys/dev/ic/bwfmreg.h

443

uint32_t tx_failures; /* # of packets failed */

sys/dev/ic/bwfmreg.h

444

uint32_t rx_ucast_pkts; /* # of unicast packets received */

sys/dev/ic/bwfmreg.h

445

uint32_t rx_mcast_pkts; /* # of multicast packets received */

sys/dev/ic/bwfmreg.h

446

uint32_t tx_rate; /* Rate of last successful tx frame, in bps */

sys/dev/ic/bwfmreg.h

447

uint32_t rx_rate; /* Rate of last successful rx frame, in bps */

sys/dev/ic/bwfmreg.h

448

uint32_t rx_decrypt_succeeds; /* # of packet decrypted successfully */

sys/dev/ic/bwfmreg.h

449

uint32_t rx_decrypt_failures; /* # of packet decrypted failed */

sys/dev/ic/bwfmreg.h

452

uint32_t tx_tot_pkts; /* # of tx pkts (ucast + mcast) */

sys/dev/ic/bwfmreg.h

453

uint32_t rx_tot_pkts; /* # of data packets recvd (uni + mcast) */

sys/dev/ic/bwfmreg.h

454

uint32_t tx_mcast_pkts; /* # of mcast pkts txed */

sys/dev/ic/bwfmreg.h

466

uint32_t tx_pkts_retry_cnt; /* # of frames where a retry was

sys/dev/ic/bwfmreg.h

469

uint32_t tx_pkts_retry_exhausted; /* # of user frames where a retry

sys/dev/ic/bwfmreg.h

479

uint32_t tx_pkts_total; /* # user frames sent successfully */

sys/dev/ic/bwfmreg.h

480

uint32_t tx_pkts_retries; /* # user frames retries */

sys/dev/ic/bwfmreg.h

481

uint32_t tx_pkts_fw_total; /* # FW generated sent successfully */

sys/dev/ic/bwfmreg.h

482

uint32_t tx_pkts_fw_retries; /* # retries for FW generated frames */

sys/dev/ic/bwfmreg.h

483

uint32_t tx_pkts_fw_retry_exhausted; /* # FW generated where a retry

sys/dev/ic/bwfmreg.h

486

uint32_t rx_pkts_retried; /* # rx with retry bit set */

sys/dev/ic/bwfmreg.h

487

uint32_t tx_rate_fallback; /* lowest fallback TX rate */

sys/dev/ic/bwfmreg.h

495

uint32_t rx_dur_total; /* user RX duration (estimate) */

sys/dev/ic/bwfmreg.h

502

uint32_t tx_rspec;/* Rate of last successful tx frame */

sys/dev/ic/bwfmreg.h

503

uint32_t rx_rspec;/* Rate of last successful rx frame */

sys/dev/ic/bwfmreg.h

504

uint32_t wnm_cap;

sys/dev/ic/bwfmreg.h

510

uint32_t len;

sys/dev/ic/bwfmreg.h

523

uint32_t nprobes;

sys/dev/ic/bwfmreg.h

524

uint32_t active_time;

sys/dev/ic/bwfmreg.h

525

uint32_t passive_time;

sys/dev/ic/bwfmreg.h

526

uint32_t home_time;

sys/dev/ic/bwfmreg.h

527

uint32_t channel_num;

sys/dev/ic/bwfmreg.h

542

uint32_t scan_type;

sys/dev/ic/bwfmreg.h

543

uint32_t nprobes;

sys/dev/ic/bwfmreg.h

544

uint32_t active_time;

sys/dev/ic/bwfmreg.h

545

uint32_t passive_time;

sys/dev/ic/bwfmreg.h

546

uint32_t home_time;

sys/dev/ic/bwfmreg.h

547

uint32_t channel_num;

sys/dev/ic/bwfmreg.h

552

uint32_t buflen;

sys/dev/ic/bwfmreg.h

553

uint32_t version;

sys/dev/ic/bwfmreg.h

554

uint32_t count;

sys/dev/ic/bwfmreg.h

559

uint32_t version;

sys/dev/ic/bwfmreg.h

570

uint32_t version;

sys/dev/ic/bwfmreg.h

578

uint32_t buflen;

sys/dev/ic/bwfmreg.h

579

uint32_t version;

sys/dev/ic/bwfmreg.h

588

uint32_t chanspec_num;

sys/dev/ic/bwfmreg.h

616

uint32_t nprobes;

sys/dev/ic/bwfmreg.h

617

uint32_t active_time;

sys/dev/ic/bwfmreg.h

618

uint32_t passive_time;

sys/dev/ic/bwfmreg.h

619

uint32_t home_time;

sys/dev/ic/bwfmreg.h

629

uint32_t index;

sys/dev/ic/bwfmreg.h

630

uint32_t len;

sys/dev/ic/bwfmreg.h

632

uint32_t pad_1[18];

sys/dev/ic/bwfmreg.h

633

uint32_t algo;

sys/dev/ic/bwfmreg.h

634

uint32_t flags;

sys/dev/ic/bwfmreg.h

636

uint32_t pad_2[3];

sys/dev/ic/bwfmreg.h

637

uint32_t iv_initialized;

sys/dev/ic/bwfmreg.h

638

uint32_t pad_3;

sys/dev/ic/bwfmreg.h

641

uint32_t hi;

sys/dev/ic/bwfmreg.h

645

uint32_t pad_5[2];

sys/dev/ic/bwfmreg.h

767

uint32_t event_type;

sys/dev/ic/bwfmreg.h

768

uint32_t status;

sys/dev/ic/bwfmreg.h

769

uint32_t reason;

sys/dev/ic/bwfmreg.h

770

uint32_t auth_type;

sys/dev/ic/bwfmreg.h

771

uint32_t datalen;

sys/dev/ic/bwfmreg.h

793

uint32_t len;

sys/dev/ic/bwfmreg.h

795

uint32_t crc;

sys/dev/ic/bwfmvar.h

106

uint32_t (*bc_read)(struct bwfm_softc *, uint32_t);

sys/dev/ic/bwfmvar.h

107

void (*bc_write)(struct bwfm_softc *, uint32_t, uint32_t);

sys/dev/ic/bwfmvar.h

111

void (*bc_activate)(struct bwfm_softc *, uint32_t);

sys/dev/ic/bwfmvar.h

211

int bwfm_chip_set_active(struct bwfm_softc *, uint32_t);

sys/dev/ic/bwfmvar.h

73

uint32_t co_base;

sys/dev/ic/bwfmvar.h

74

uint32_t co_wrapbase;

sys/dev/ic/bwfmvar.h

79

uint32_t ch_chip;

sys/dev/ic/bwfmvar.h

80

uint32_t ch_chiprev;

sys/dev/ic/bwfmvar.h

81

uint32_t ch_cc_caps;

sys/dev/ic/bwfmvar.h

82

uint32_t ch_cc_caps_ext;

sys/dev/ic/bwfmvar.h

83

uint32_t ch_pmucaps;

sys/dev/ic/bwfmvar.h

84

uint32_t ch_pmurev;

sys/dev/ic/bwfmvar.h

85

uint32_t ch_rambase;

sys/dev/ic/bwfmvar.h

86

uint32_t ch_ramsize;

sys/dev/ic/bwfmvar.h

87

uint32_t ch_srsize;

sys/dev/ic/bwfmvar.h

92

uint32_t prereset, uint32_t reset);

sys/dev/ic/bwfmvar.h

94

uint32_t prereset, uint32_t reset, uint32_t postreset);

sys/dev/ic/bwi.c

1007

uint32_t data_reg;

sys/dev/ic/bwi.c

1022

uint32_t v)

sys/dev/ic/bwi.c

1183

uint32_t intrs;

sys/dev/ic/bwi.c

1258

uint32_t flags, state_lo, status;

sys/dev/ic/bwi.c

132

void bwi_tmplt_write_4(struct bwi_mac *, uint32_t, uint32_t);

sys/dev/ic/bwi.c

1341

uint32_t orig_val, val;

sys/dev/ic/bwi.c

136

uint32_t bwi_memobj_read_4(struct bwi_mac *, uint16_t, uint16_t);

sys/dev/ic/bwi.c

140

uint32_t);

sys/dev/ic/bwi.c

1492

const uint32_t *packet;

sys/dev/ic/bwi.c

1496

static const uint32_t packet_11a[PACKET_LEN] =

sys/dev/ic/bwi.c

1498

static const uint32_t packet_11bg[PACKET_LEN] =

sys/dev/ic/bwi.c

1843

const uint32_t *fw;

sys/dev/ic/bwi.c

1849

fw = (const uint32_t *)(mac->mac_ucode + BWI_FWHDR_SZ);

sys/dev/ic/bwi.c

1850

fw_len = (mac->mac_ucode_size - BWI_FWHDR_SZ) / sizeof(uint32_t);

sys/dev/ic/bwi.c

1862

fw = (const uint32_t *)(mac->mac_pcm + BWI_FWHDR_SZ);

sys/dev/ic/bwi.c

1863

fw_len = (mac->mac_pcm_size - BWI_FWHDR_SZ) / sizeof(uint32_t);

sys/dev/ic/bwi.c

1884

uint32_t intr_status;

sys/dev/ic/bwi.c

192

void bwi_tbl_write_4(struct bwi_mac *mac, uint16_t, uint32_t);

sys/dev/ic/bwi.c

1922

uint32_t filt, bits;

sys/dev/ic/bwi.c

2010

uint32_t val32;

sys/dev/ic/bwi.c

2076

uint32_t mac_status;

sys/dev/ic/bwi.c

2326

uint32_t status;

sys/dev/ic/bwi.c

234

uint32_t bwi_rf_lo_devi_measure(struct bwi_mac *, uint16_t);

sys/dev/ic/bwi.c

2395

uint32_t val;

sys/dev/ic/bwi.c

2419

uint32_t txrx_reg = BWI_TXRX_CTRL_BASE + BWI_TX32_CTRL;

sys/dev/ic/bwi.c

2951

bwi_tbl_write_4(struct bwi_mac *mac, uint16_t ofs, uint32_t data)

sys/dev/ic/bwi.c

304

struct bwi_ring_data *, bus_size_t, uint32_t);

sys/dev/ic/bwi.c

305

int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t,

sys/dev/ic/bwi.c

311

void bwi_enable_intrs(struct bwi_softc *, uint32_t);

sys/dev/ic/bwi.c

312

void bwi_disable_intrs(struct bwi_softc *, uint32_t);

sys/dev/ic/bwi.c

314

void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,

sys/dev/ic/bwi.c

329

void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);

sys/dev/ic/bwi.c

333

uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phymode);

sys/dev/ic/bwi.c

334

void bwi_ofdm_plcp_header(uint32_t *, int, uint8_t);

sys/dev/ic/bwi.c

340

void bwi_start_tx32(struct bwi_softc *, uint32_t, int);

sys/dev/ic/bwi.c

351

uint32_t bwi_regwin_disable_bits(struct bwi_softc *);

sys/dev/ic/bwi.c

353

uint32_t);

sys/dev/ic/bwi.c

355

uint32_t);

sys/dev/ic/bwi.c

363

uint, uint8_t, uint32_t);

sys/dev/ic/bwi.c

3784

uint32_t val;

sys/dev/ic/bwi.c

400

static const uint32_t bwi_phy_rotor_11g_rev1[] =

sys/dev/ic/bwi.c

412

static const uint32_t bwi_phy_delay_11g_rev1[] =

sys/dev/ic/bwi.c

4293

uint32_t test_lim, test;

sys/dev/ic/bwi.c

4911

uint32_t

sys/dev/ic/bwi.c

4915

uint32_t devi = 0;

sys/dev/ic/bwi.c

4948

uint32_t devi_min;

sys/dev/ic/bwi.c

4957

uint32_t devi;

sys/dev/ic/bwi.c

5089

uint32_t devi_min;

sys/dev/ic/bwi.c

5132

uint32_t devi;

sys/dev/ic/bwi.c

5730

thr = __SHIFTIN((uint32_t)thr1, NRSSI_THR1_MASK) |

sys/dev/ic/bwi.c

5731

__SHIFTIN((uint32_t)thr2, NRSSI_THR2_MASK);

sys/dev/ic/bwi.c

576

uint32_t intr_status;

sys/dev/ic/bwi.c

577

uint32_t txrx_intr_status[BWI_TXRX_NRING];

sys/dev/ic/bwi.c

603

uint32_t mask;

sys/dev/ic/bwi.c

6214

uint32_t ctrl, addr, addr_hi, addr_lo;

sys/dev/ic/bwi.c

6243

uint32_t gpio_in, gpio_out, gpio_en, status;

sys/dev/ic/bwi.c

6283

uint32_t gpio_out, gpio_en;

sys/dev/ic/bwi.c

6335

uint32_t win = BWI_PCIM_REGWIN(id);

sys/dev/ic/bwi.c

6353

uint32_t val;

sys/dev/ic/bwi.c

6580

uint32_t info;

sys/dev/ic/bwi.c

6721

uint32_t val;

sys/dev/ic/bwi.c

6742

uint32_t mac_mask;

sys/dev/ic/bwi.c

6848

uint32_t val;

sys/dev/ic/bwi.c

6912

uint32_t clk_ctrl, clk_src;

sys/dev/ic/bwi.c

7504

uint32_t txrx_ctrl_step = 0;

sys/dev/ic/bwi.c

7660

struct bwi_ring_data *rd, bus_size_t size, uint32_t txrx_ctrl)

sys/dev/ic/bwi.c

7699

bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,

sys/dev/ic/bwi.c

8037

bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)

sys/dev/ic/bwi.c

8043

bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)

sys/dev/ic/bwi.c

8053

uint32_t val, addr_hi, addr_lo;

sys/dev/ic/bwi.c

8082

bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,

sys/dev/ic/bwi.c

8085

uint32_t val, addr_hi, addr_lo;

sys/dev/ic/bwi.c

8373

uint32_t plcp;

sys/dev/ic/bwi.c

8483

uint32_t val, rx_ctrl;

sys/dev/ic/bwi.c

8501

bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)

sys/dev/ic/bwi.c

8509

uint32_t status;

sys/dev/ic/bwi.c

8557

uint32_t state, val;

sys/dev/ic/bwi.c

8614

bwi_plcp2rate(uint32_t plcp0, enum ieee80211_phymode phymode)

sys/dev/ic/bwi.c

8616

uint32_t plcp = letoh32(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK;

sys/dev/ic/bwi.c

8621

bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)

sys/dev/ic/bwi.c

8623

uint32_t plcp;

sys/dev/ic/bwi.c

8788

uint8_t rs_rate, uint32_t flags)

sys/dev/ic/bwi.c

8844

uint32_t mac_ctrl;

sys/dev/ic/bwi.c

9033

bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)

sys/dev/ic/bwi.c

9044

uint32_t val, ctrl_base;

sys/dev/ic/bwi.c

9128

uint32_t tx_status0, tx_status1;

sys/dev/ic/bwi.c

9169

uint32_t val;

sys/dev/ic/bwi.c

918

bwi_tmplt_write_4(struct bwi_mac *mac, uint32_t ofs, uint32_t val)

sys/dev/ic/bwi.c

9231

uint32_t

sys/dev/ic/bwi.c

9234

uint32_t busrev;

sys/dev/ic/bwi.c

9251

uint32_t val, disable_bits;

sys/dev/ic/bwi.c

9270

bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)

sys/dev/ic/bwi.c

9272

uint32_t state_lo, disable_bits;

sys/dev/ic/bwi.c

9310

uint32_t state_hi;

sys/dev/ic/bwi.c

9346

bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)

sys/dev/ic/bwi.c

9348

uint32_t state_lo, state_hi, imstate;

sys/dev/ic/bwi.c

9400

uint32_t val;

sys/dev/ic/bwi.c

9418

val |= ((uint32_t)(*p++)) << (j * 8);

sys/dev/ic/bwi.c

964

uint32_t data_reg;

sys/dev/ic/bwi.c

977

uint32_t

sys/dev/ic/bwi.c

985

uint32_t ret;

sys/dev/ic/bwivar.h

101

uint32_t ctrl;

sys/dev/ic/bwivar.h

102

uint32_t addr; /* BWI_DESC32_A_ */

sys/dev/ic/bwivar.h

118

uint32_t ctrl0;

sys/dev/ic/bwivar.h

119

uint32_t ctrl1;

sys/dev/ic/bwivar.h

120

uint32_t addr_lo;

sys/dev/ic/bwivar.h

121

uint32_t addr_hi;

sys/dev/ic/bwivar.h

149

uint32_t txh_mac_ctrl; /* BWI_TXH_MAC_C_ */

sys/dev/ic/bwivar.h

197

uint32_t rdata_txrx_ctrl;

sys/dev/ic/bwivar.h

241

uint32_t stats_ctrl_base;

sys/dev/ic/bwivar.h

250

uint32_t fw_size;

sys/dev/ic/bwivar.h

275

uint32_t val32;

sys/dev/ic/bwivar.h

298

uint32_t rw_flags; /* BWI_REGWIN_F_ */

sys/dev/ic/bwivar.h

326

uint32_t phy_flags; /* BWI_PHY_F_ */

sys/dev/ic/bwivar.h

362

uint32_t rf_flags; /* BWI_RF_F_ */

sys/dev/ic/bwivar.h

432

uint32_t mac_flags; /* BWI_MAC_F_ */

sys/dev/ic/bwivar.h

512

uint32_t sc_flags; /* BWI_F_ */

sys/dev/ic/bwivar.h

514

uint32_t sc_cap; /* BWI_CAP_ */

sys/dev/ic/bwivar.h

595

(struct bwi_softc *, uint32_t, int);

sys/dev/ic/bwivar.h

602

void (*sc_conf_write)(void *, uint32_t, uint32_t);

sys/dev/ic/bwivar.h

603

uint32_t (*sc_conf_read)(void *, uint32_t);

sys/dev/ic/ccp.c

51

uint32_t trng;

sys/dev/ic/dwhdmi.h

54

uint32_t sym;

sys/dev/ic/dwhdmi.h

55

uint32_t term;

sys/dev/ic/dwhdmi.h

56

uint32_t vlev;

sys/dev/ic/dwhdmi.h

61

uint32_t cpce;

sys/dev/ic/dwhdmi.h

62

uint32_t gmp;

sys/dev/ic/dwhdmi.h

63

uint32_t curr;

sys/dev/ic/dwiic.c

106

dwiic_write(struct dwiic_softc *sc, int offset, uint32_t val)

sys/dev/ic/dwiic.c

139

uint32_t reg;

sys/dev/ic/dwiic.c

497

uint32_t

sys/dev/ic/dwiic.c

500

uint32_t stat;

sys/dev/ic/dwiic.c

532

uint32_t en, stat;

sys/dev/ic/dwiic.c

95

uint32_t

sys/dev/ic/dwiicvar.h

100

uint32_t dwiic_read(struct dwiic_softc *, int);

sys/dev/ic/dwiicvar.h

101

void dwiic_write(struct dwiic_softc *, int, uint32_t);

sys/dev/ic/dwiicvar.h

108

uint16_t *, uint32_t *);

sys/dev/ic/dwiicvar.h

70

uint32_t master_cfg;

sys/dev/ic/dwiicvar.h

72

uint32_t sda_hold_time;

sys/dev/ic/dwqe.c

1025

uint32_t reg;

sys/dev/ic/dwqe.c

1107

static uint32_t

sys/dev/ic/dwqe.c

1108

bitrev32(uint32_t x)

sys/dev/ic/dwqe.c

1125

uint32_t crc, hash[2], hashbit, hashreg;

sys/dev/ic/dwqe.c

1126

uint32_t reg;

sys/dev/ic/dwqe.c

117

uint32_t reg;

sys/dev/ic/dwqe.c

1240

txd->sd_tdes0 = (uint32_t)map->dm_segs[i].ds_addr;

sys/dev/ic/dwqe.c

1241

txd->sd_tdes1 = (uint32_t)(map->dm_segs[i].ds_addr >> 32);

sys/dev/ic/dwqe.c

130

uint32_t reg;

sys/dev/ic/dwqe.c

1395

rxd->sd_tdes0 = (uint32_t)rxb->tb_map->dm_segs[0].ds_addr;

sys/dev/ic/dwqe.c

1396

rxd->sd_tdes1 = (uint32_t)(rxb->tb_map->dm_segs[0].ds_addr >> 32);

sys/dev/ic/dwqe.c

154

uint32_t version, mode;

sys/dev/ic/dwqe.c

323

uint32_t

sys/dev/ic/dwqe.c

330

dwqe_write(struct dwqe_softc *sc, bus_addr_t addr, uint32_t data)

sys/dev/ic/dwqe.c

338

uint32_t machi, maclo;

sys/dev/ic/dwqe.c

557

uint32_t conf;

sys/dev/ic/dwqe.c

59

uint32_t dwqe_read(struct dwqe_softc *, bus_addr_t);

sys/dev/ic/dwqe.c

60

void dwqe_write(struct dwqe_softc *, bus_addr_t, uint32_t);

sys/dev/ic/dwqe.c

639

uint32_t reg;

sys/dev/ic/dwqe.c

863

uint32_t mode, reg, fifosz, tqs, rqs;

sys/dev/ic/dwqereg.h

241

uint32_t sd_tdes0;

sys/dev/ic/dwqereg.h

242

uint32_t sd_tdes1;

sys/dev/ic/dwqereg.h

243

uint32_t sd_tdes2;

sys/dev/ic/dwqereg.h

244

uint32_t sd_tdes3;

sys/dev/ic/dwqevar.h

110

uint32_t sc_blen[7];

sys/dev/ic/dwqevar.h

118

uint32_t dwqe_read(struct dwqe_softc *, bus_addr_t);

sys/dev/ic/dwqevar.h

119

void dwqe_write(struct dwqe_softc *, bus_addr_t, uint32_t);

sys/dev/ic/dwqevar.h

84

uint32_t sc_clk;

sys/dev/ic/dwqevar.h

85

uint32_t sc_clkrate;

sys/dev/ic/dwqevar.h

88

uint32_t sc_clk_sel_125;

sys/dev/ic/dwqevar.h

89

uint32_t sc_clk_sel_25;

sys/dev/ic/dwqevar.h

90

uint32_t sc_clk_sel_2_5;

sys/dev/ic/elink3.c

1015

if (m->m_len > 3 && ALIGNED_POINTER(data, uint32_t)) {

sys/dev/ic/elink3.c

1390

ALIGNED_POINTER(data, uint32_t)) {

sys/dev/ic/gem.c

1718

uint32_t prod;

sys/dev/ic/gem.c

1719

uint32_t free, used = 0;

sys/dev/ic/gem.c

1720

uint32_t first, last;

sys/dev/ic/imxiic.c

113

uint32_t div;

sys/dev/ic/imxiic.c

132

imxiic_wait_state(struct imxiic_softc *sc, uint32_t mask, uint32_t value)

sys/dev/ic/imxiic.c

134

uint32_t state;

sys/dev/ic/imxiic.c

48

int imxiic_wait_state(struct imxiic_softc *, uint32_t, uint32_t);

sys/dev/ic/imxiicvar.h

39

uint32_t sc_clkrate;

sys/dev/ic/iosf.c

100

uint32_t rv = IOSF_MBI_ENABLE;

sys/dev/ic/iosf.c

107

static inline uint32_t

sys/dev/ic/iosf.c

108

iosf_mbi_mcrx(uint32_t offset)

sys/dev/ic/iosf.c

117

static uint32_t

sys/dev/ic/iosf.c

119

uint32_t offset)

sys/dev/ic/iosf.c

121

uint32_t mcr, mcrx, mdr;

sys/dev/ic/iosf.c

135

uint32_t offset, uint32_t mdr)

sys/dev/ic/iosf.c

137

uint32_t mcr, mcrx;

sys/dev/ic/iosf.c

149

uint32_t offset, uint32_t bits, uint32_t mask)

sys/dev/ic/iosf.c

151

uint32_t mcr, mcrx, mdr;

sys/dev/ic/iosf.c

172

iosf_mbi_read(uint8_t port, uint8_t opcode, uint32_t offset, uint32_t *mdrp)

sys/dev/ic/iosf.c

188

iosf_mbi_write(uint8_t port, uint8_t opcode, uint32_t offset, uint32_t mdr)

sys/dev/ic/iosf.c

204

iosf_mbi_modify(uint8_t port, uint8_t opcode, uint32_t offset,

sys/dev/ic/iosf.c

205

uint32_t bits, uint32_t mask)

sys/dev/ic/iosf.c

227

static uint32_t

sys/dev/ic/iosf.c

230

uint32_t sem;

sys/dev/ic/iosf.c

97

static inline uint32_t

sys/dev/ic/iosf.c

98

iosf_mbi_mcr(uint8_t op, uint8_t port, uint32_t offset)

sys/dev/ic/iosfvar.h

31

uint32_t (*mbi_mdr_rd)(struct iosf_mbi *sc, uint32_t, uint32_t);

sys/dev/ic/iosfvar.h

32

void (*mbi_mdr_wr)(struct iosf_mbi *sc, uint32_t, uint32_t,

sys/dev/ic/iosfvar.h

33

uint32_t);

sys/dev/ic/iosfvar.h

54

int iosf_mbi_read(uint8_t, uint8_t, uint32_t, uint32_t *);

sys/dev/ic/iosfvar.h

55

int iosf_mbi_write(uint8_t, uint8_t, uint32_t, uint32_t);

sys/dev/ic/iosfvar.h

56

int iosf_mbi_modify(uint8_t, uint8_t, uint32_t, uint32_t, uint32_t);

sys/dev/ic/ispi.c

140

uint32_t csctrl;

sys/dev/ic/ispi.c

161

uint32_t

sys/dev/ic/ispi.c

164

uint32_t val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);

sys/dev/ic/ispi.c

171

ispi_write(struct ispi_softc *sc, int reg, uint32_t val)

sys/dev/ic/ispi.c

178

uint32_t

sys/dev/ic/ispi.c

185

ispi_lpss_write(struct ispi_softc *sc, int reg, uint32_t val)

sys/dev/ic/ispi.c

194

uint32_t sscr0, sscr1;

sys/dev/ic/ispi.c

263

uint32_t t;

sys/dev/ic/ispi.c

87

uint32_t ispi_lpss_read(struct ispi_softc *, int);

sys/dev/ic/ispi.c

88

void ispi_lpss_write(struct ispi_softc *, int, uint32_t);

sys/dev/ic/ispivar.h

81

void ispi_write(struct ispi_softc *sc, int reg, uint32_t val);

sys/dev/ic/ispivar.h

82

uint32_t ispi_read(struct ispi_softc *sc, int reg);

sys/dev/ic/lance.c

568

uint32_t crc;

sys/dev/ic/malo.c

100

uint32_t reserved1; /* SAP packet info ??? */

sys/dev/ic/malo.c

101

uint32_t reserved2;

sys/dev/ic/malo.c

147

uint32_t FWReleaseNumber;

sys/dev/ic/malo.c

148

uint32_t WcbBase0;

sys/dev/ic/malo.c

149

uint32_t RxPdWrPtr;

sys/dev/ic/malo.c

150

uint32_t RxPdRdPtr;

sys/dev/ic/malo.c

151

uint32_t CookiePtr;

sys/dev/ic/malo.c

152

uint32_t WcbBase1;

sys/dev/ic/malo.c

153

uint32_t WcbBase2;

sys/dev/ic/malo.c

154

uint32_t WcbBase3;

sys/dev/ic/malo.c

1605

uint32_t rxRdPtr, rxWrPtr;

sys/dev/ic/malo.c

166

uint32_t gprotection;

sys/dev/ic/malo.c

184

uint32_t isibss;

sys/dev/ic/malo.c

201

uint32_t threshold;

sys/dev/ic/malo.c

2204

malo_cmd_set_rts(struct malo_softc *sc, uint32_t threshold)

sys/dev/ic/malo.c

292

int malo_cmd_set_rts(struct malo_softc *sc, uint32_t threshold);

sys/dev/ic/malo.c

301

uint32_t status;

sys/dev/ic/malo.c

469

sc->sc_cmd_mem = (caddr_t)sc->sc_cmd_mem + sizeof(uint32_t);

sys/dev/ic/malo.c

472

sizeof(uint32_t);

sys/dev/ic/malo.c

490

malo_ctl_write4(sc, 0x0c10, (uint32_t)addr);

sys/dev/ic/malo.c

502

malo_ctl_write4(sc, 0x0c10, (uint32_t)addr);

sys/dev/ic/malo.c

71

uint32_t softstat;

sys/dev/ic/malo.c

84

uint32_t physdata; /* DMA address of data */

sys/dev/ic/malo.c

85

uint32_t physnext; /* DMA address of next control block */

sys/dev/ic/malo.c

92

uint32_t status;

sys/dev/ic/malo.c

96

uint32_t physdata; /* DMA address of data */

sys/dev/ic/malo.c

99

uint32_t physnext; /* DMA address of next control block */

sys/dev/ic/malo.h

93

uint32_t *sc_cookie;

sys/dev/ic/malo.h

96

uint32_t sc_RxPdWrPtr;

sys/dev/ic/malo.h

97

uint32_t sc_RxPdRdPtr;

sys/dev/ic/mfi.c

101

int mfi_do_mgmt(struct mfi_softc *, struct mfi_ccb * , uint32_t,

sys/dev/ic/mfi.c

1014

struct scsi_xfer *xs, uint64_t blockno, uint32_t blockcnt)

sys/dev/ic/mfi.c

102

uint32_t, uint32_t, void *, const union mfi_mbox *);

sys/dev/ic/mfi.c

1160

uint32_t blockcnt;

sys/dev/ic/mfi.c

1322

mfi_mgmt(struct mfi_softc *sc, uint32_t opc, uint32_t dir, uint32_t len,

sys/dev/ic/mfi.c

1337

mfi_do_mgmt(struct mfi_softc *sc, struct mfi_ccb *ccb, uint32_t opc,

sys/dev/ic/mfi.c

1338

uint32_t dir, uint32_t len, void *buf, const union mfi_mbox *mbox)

sys/dev/ic/mfi.c

1898

uint32_t opc, dir = MFI_DATA_NONE;

sys/dev/ic/mfi.c

1946

uint32_t cmd;

sys/dev/ic/mfi.c

2071

uint32_t opc, dir = MFI_DATA_NONE;

sys/dev/ic/mfi.c

2075

uint32_t time, exec_freq;

sys/dev/ic/mfi.c

2215

uint32_t size;

sys/dev/ic/mfi.c

251

uint32_t i;

sys/dev/ic/mfi.c

308

uint32_t

sys/dev/ic/mfi.c

311

uint32_t rv;

sys/dev/ic/mfi.c

322

mfi_write(struct mfi_softc *sc, bus_size_t r, uint32_t v)

sys/dev/ic/mfi.c

42

uint32_t mfi_debug = 0

sys/dev/ic/mfi.c

665

uint32_t status, frames, max_sgl;

sys/dev/ic/mfi.c

714

sc->sc_pcq = mfi_allocmem(sc, (sizeof(uint32_t) * sc->sc_max_cmds) +

sys/dev/ic/mfi.c

84

uint32_t mfi_read(struct mfi_softc *, bus_size_t);

sys/dev/ic/mfi.c

85

void mfi_write(struct mfi_softc *, bus_size_t, uint32_t);

sys/dev/ic/mfi.c

965

uint32_t producer, consumer, ctx;

sys/dev/ic/mfi.c

97

struct scsi_xfer *, uint64_t, uint32_t);

sys/dev/ic/mfi.c

99

int mfi_mgmt(struct mfi_softc *, uint32_t, uint32_t, uint32_t,

sys/dev/ic/mfireg.h

1004

uint32_t mpd_allowed_ops;

sys/dev/ic/mfireg.h

1036

uint32_t mpo_no_entries;

sys/dev/ic/mfireg.h

1037

uint32_t mpo_res;

sys/dev/ic/mfireg.h

1038

uint32_t mpo_allowedops_list[MFI_MAX_PD];

sys/dev/ic/mfireg.h

1077

uint32_t mfc_size;

sys/dev/ic/mfireg.h

1114

uint32_t mfg_date;

sys/dev/ic/mfireg.h

1149

uint32_t auto_learn_period;

sys/dev/ic/mfireg.h

1150

uint32_t next_learn_time;

sys/dev/ic/mfireg.h

1171

uint32_t fw_status;

sys/dev/ic/mfireg.h

1217

uint32_t num_iteration;

sys/dev/ic/mfireg.h

1231

uint32_t next_exec;

sys/dev/ic/mfireg.h

1232

uint32_t exec_freq;

sys/dev/ic/mfireg.h

1233

uint32_t clear_freq;

sys/dev/ic/mfireg.h

1242

uint32_t count; /* Number of foreign configs found */

sys/dev/ic/mfireg.h

179

uint32_t w[3];

sys/dev/ic/mfireg.h

338

uint32_t addr;

sys/dev/ic/mfireg.h

339

uint32_t len;

sys/dev/ic/mfireg.h

344

uint32_t len;

sys/dev/ic/mfireg.h

349

uint32_t len;

sys/dev/ic/mfireg.h

350

uint32_t flag;

sys/dev/ic/mfireg.h

369

uint32_t mfh_context;

sys/dev/ic/mfireg.h

370

uint32_t mfh_pad0;

sys/dev/ic/mfireg.h

373

uint32_t mfh_data_len;

sys/dev/ic/mfireg.h

386

uint32_t mif_reserved[6];

sys/dev/ic/mfireg.h

391

uint32_t miq_flags;

sys/dev/ic/mfireg.h

392

uint32_t miq_rq_entries;

sys/dev/ic/mfireg.h

417

uint32_t mdf_opcode;

sys/dev/ic/mfireg.h

424

uint32_t maf_abort_context;

sys/dev/ic/mfireg.h

425

uint32_t maf_pad;

sys/dev/ic/mfireg.h

427

uint32_t maf_reserved[6];

sys/dev/ic/mfireg.h

442

uint32_t msf_stp_flags;

sys/dev/ic/mfireg.h

468

uint32_t mec_word;

sys/dev/ic/mfireg.h

472

uint32_t mel_newest_seq_num;

sys/dev/ic/mfireg.h

473

uint32_t mel_oldest_seq_num;

sys/dev/ic/mfireg.h

474

uint32_t mel_clear_seq_num;

sys/dev/ic/mfireg.h

475

uint32_t mel_shutdown_seq_num;

sys/dev/ic/mfireg.h

476

uint32_t mel_boot_seq_num;

sys/dev/ic/mfireg.h

498

uint32_t prev_state;

sys/dev/ic/mfireg.h

499

uint32_t new_state;

sys/dev/ic/mfireg.h

528

uint32_t med_seq_num;

sys/dev/ic/mfireg.h

529

uint32_t med_time_stamp;

sys/dev/ic/mfireg.h

530

uint32_t med_code;

sys/dev/ic/mfireg.h

559

uint32_t prev_owner;

sys/dev/ic/mfireg.h

560

uint32_t new_owner;

sys/dev/ic/mfireg.h

577

uint32_t prev_state;

sys/dev/ic/mfireg.h

578

uint32_t new_state;

sys/dev/ic/mfireg.h

590

uint32_t err;

sys/dev/ic/mfireg.h

618

uint32_t rate;

sys/dev/ic/mfireg.h

622

uint32_t rtc;

sys/dev/ic/mfireg.h

623

uint32_t elapsed_seconds;

sys/dev/ic/mfireg.h

627

uint32_t ecar;

sys/dev/ic/mfireg.h

628

uint32_t elog;

sys/dev/ic/mfireg.h

636

uint32_t w[24];

sys/dev/ic/mfireg.h

717

uint32_t mci_image_check_word;

sys/dev/ic/mfireg.h

718

uint32_t mci_image_component_count;

sys/dev/ic/mfireg.h

722

uint32_t mci_pending_image_component_count;

sys/dev/ic/mfireg.h

731

uint32_t mci_hw_present;

sys/dev/ic/mfireg.h

739

uint32_t mci_current_fw_time;

sys/dev/ic/mfireg.h

742

uint32_t mci_max_request_size;

sys/dev/ic/mfireg.h

759

uint32_t mci_raid_levels;

sys/dev/ic/mfireg.h

766

uint32_t mci_adapter_ops;

sys/dev/ic/mfireg.h

792

uint32_t mci_ld_ops;

sys/dev/ic/mfireg.h

805

uint32_t mci_pd_ops;

sys/dev/ic/mfireg.h

810

uint32_t mci_pd_mix_support;

sys/dev/ic/mfireg.h

832

uint32_t mll_no_ld;

sys/dev/ic/mfireg.h

833

uint32_t mll_res;

sys/dev/ic/mfireg.h

901

uint32_t mlp_in_prog;

sys/dev/ic/mfireg.h

936

uint32_t mpl_size;

sys/dev/ic/mfireg.h

937

uint32_t mpl_no_pd;

sys/dev/ic/mfireg.h

947

uint32_t mfp_in_prog;

sys/dev/ic/mfireg.h

965

uint32_t mpd_mediaerr_cnt;

sys/dev/ic/mfireg.h

966

uint32_t mpd_othererr_cnt;

sys/dev/ic/mfireg.h

967

uint32_t mpd_predfail_cnt;

sys/dev/ic/mfireg.h

968

uint32_t mpd_last_pred_event;

sys/dev/ic/mfireg.h

972

uint32_t mpd_ddf_state;

sys/dev/ic/mfivar.h

141

uint32_t ld_present;

sys/dev/ic/mfivar.h

149

uint32_t sc_max_cmds;

sys/dev/ic/mfivar.h

150

uint32_t sc_max_sgl;

sys/dev/ic/mfivar.h

151

uint32_t sc_sgl_size;

sys/dev/ic/mfivar.h

152

uint32_t sc_ld_cnt;

sys/dev/ic/mfivar.h

173

uint32_t sc_frames_size;

sys/dev/ic/mfivar.h

23

extern uint32_t mfi_debug;

sys/dev/ic/mfivar.h

52

uint32_t mpc_producer;

sys/dev/ic/mfivar.h

53

uint32_t mpc_consumer;

sys/dev/ic/mfivar.h

54

uint32_t mpc_reply_q[1]; /* compensate for 1 extra reply per spec */

sys/dev/ic/mfivar.h

61

uint32_t ccb_frame_size;

sys/dev/ic/mfivar.h

62

uint32_t ccb_extra_frames;

sys/dev/ic/mfivar.h

73

uint32_t ccb_len;

sys/dev/ic/mfivar.h

75

uint32_t ccb_direction;

sys/dev/ic/mfivar.h

89

uint32_t ccb_flags;

sys/dev/ic/mpi.c

44

uint32_t mpi_debug = 0

sys/dev/ic/mpivar.h

24

extern uint32_t mpi_debug;

sys/dev/ic/mtwreg.h

740

uint32_t sdp0; /* Segment Data Pointer 0 */

sys/dev/ic/mtwreg.h

749

uint32_t sdp1; /* Segment Data Pointer 1 */

sys/dev/ic/mtwreg.h

815

uint32_t iv;

sys/dev/ic/mtwreg.h

816

uint32_t eiv;

sys/dev/ic/mtwreg.h

817

uint32_t reserved1;

sys/dev/ic/mtwreg.h

822

uint32_t sdp0;

sys/dev/ic/mtwreg.h

828

uint32_t sdp1; /* unused */

sys/dev/ic/mtwreg.h

829

uint32_t flags;

sys/dev/ic/mtwreg.h

860

uint32_t flags;

sys/dev/ic/mtwreg.h

872

uint32_t reserved1;

sys/dev/ic/mtwreg.h

873

uint32_t reserved2;

sys/dev/ic/mtwreg.h

874

uint32_t reserved3;

sys/dev/ic/mtwreg.h

879

uint32_t func;

sys/dev/ic/mtwreg.h

880

uint32_t val;

sys/dev/ic/mtwreg.h

884

uint32_t r1;

sys/dev/ic/mtwreg.h

885

uint32_t r2;

sys/dev/ic/mtwreg.h

886

uint32_t r3;

sys/dev/ic/mtwreg.h

887

uint32_t r4;

sys/dev/ic/nvme.c

1053

uint32_t

sys/dev/ic/nvme.c

1061

uint32_t

sys/dev/ic/nvme.c

1072

uint32_t tail;

sys/dev/ic/nvme.c

137

uint32_t nvme_op_sq_enter(struct nvme_softc *,

sys/dev/ic/nvme.c

141

uint32_t nvme_op_sq_enter_locked(struct nvme_softc *,

sys/dev/ic/nvme.c

1949

uint32_t cc, csts, vs;

sys/dev/ic/nvme.c

2163

uint32_t dwlen;

sys/dev/ic/nvmeio.h

24

uint32_t ps_csts;

sys/dev/ic/nvmeio.h

25

uint32_t ps_cc;

sys/dev/ic/nvmeio.h

34

uint32_t pt_nsid;

sys/dev/ic/nvmeio.h

35

uint32_t pt_cdw10;

sys/dev/ic/nvmeio.h

36

uint32_t pt_cdw11;

sys/dev/ic/nvmeio.h

37

uint32_t pt_cdw12;

sys/dev/ic/nvmeio.h

38

uint32_t pt_cdw13;

sys/dev/ic/nvmeio.h

39

uint32_t pt_cdw14;

sys/dev/ic/nvmeio.h

40

uint32_t pt_cdw15;

sys/dev/ic/nvmeio.h

43

uint32_t pt_statuslen;

sys/dev/ic/nvmeio.h

46

uint32_t pt_databuflen; /* Length of buffer. */

sys/dev/ic/nvmevar.h

83

uint32_t (*op_sq_enter)(struct nvme_softc *,

sys/dev/ic/nvmevar.h

87

uint32_t (*op_sq_enter_locked)(struct nvme_softc *,

sys/dev/ic/pcdisplay_subr.c

148

pcdisplay_putchar(void *id, int row, int col, u_int c, uint32_t attr)

sys/dev/ic/pcdisplay_subr.c

223

pcdisplay_erasecols(void *id, int row, int startcol, int ncols, uint32_t fillattr)

sys/dev/ic/pcdisplay_subr.c

276

pcdisplay_eraserows(void *id, int startrow, int nrows, uint32_t fillattr)

sys/dev/ic/pcdisplayvar.h

80

int pcdisplay_putchar(void *, int, int, u_int, uint32_t);

sys/dev/ic/pcdisplayvar.h

84

int pcdisplay_erasecols(void *, int, int, int, uint32_t);

sys/dev/ic/pcdisplayvar.h

86

int pcdisplay_eraserows(void *, int, int, uint32_t);

sys/dev/ic/pgt.c

111

uint32_t pgt_read_4(struct pgt_softc *, uint16_t);

sys/dev/ic/pgt.c

112

void pgt_write_4(struct pgt_softc *, uint16_t, uint32_t);

sys/dev/ic/pgt.c

113

void pgt_write_4_flush(struct pgt_softc *, uint16_t, uint32_t);

sys/dev/ic/pgt.c

115

uint32_t pgt_queue_frags_pending(struct pgt_softc *, enum pgt_queue);

sys/dev/ic/pgt.c

1307

pgt_trap_received(struct pgt_softc *sc, uint32_t oid, void *trapdata,

sys/dev/ic/pgt.c

1338

*(uint32_t *)p = oid;

sys/dev/ic/pgt.c

1339

p += sizeof(uint32_t);

sys/dev/ic/pgt.c

1356

uint32_t oid, size;

sys/dev/ic/pgt.c

140

void pgt_trap_received(struct pgt_softc *, uint32_t, void *, size_t);

sys/dev/ic/pgt.c

167

struct pgt_obj_bss *, struct wi_scan_res *, uint32_t);

sys/dev/ic/pgt.c

173

void pgt_hostap_handle_mlme(struct pgt_softc *, uint32_t,

sys/dev/ic/pgt.c

1762

uint32_t reg;

sys/dev/ic/pgt.c

1853

uint32_t phymode, country;

sys/dev/ic/pgt.c

199

pgt_write_4(struct pgt_softc *sc, uint16_t offset, uint32_t value)

sys/dev/ic/pgt.c

2031

uint32_t rate;

sys/dev/ic/pgt.c

209

pgt_write_4_flush(struct pgt_softc *sc, uint16_t offset, uint32_t value)

sys/dev/ic/pgt.c

2242

uint32_t noise;

sys/dev/ic/pgt.c

231

uint32_t

sys/dev/ic/pgt.c

2381

struct wi_scan_res *scanres, uint32_t noise)

sys/dev/ic/pgt.c

241

pd->pd_fragp->pf_addr = htole32((uint32_t)pd->pd_dmaaddr);

sys/dev/ic/pgt.c

2533

uint32_t mode, bsstype, config, profile, channel, slot, preamble;

sys/dev/ic/pgt.c

2534

uint32_t wep, exunencrypted, wepkey, dot1x, auth, mlme;

sys/dev/ic/pgt.c

264

pd->pd_fragp->pf_addr = htole32((uint32_t)pd->pd_dmaaddr);

sys/dev/ic/pgt.c

2783

pgt_hostap_handle_mlme(struct pgt_softc *sc, uint32_t oid,

sys/dev/ic/pgt.c

2826

uint32_t channel, noise, ls;

sys/dev/ic/pgt.c

2831

uint32_t oid;

sys/dev/ic/pgt.c

2833

oid = *mtod(args, uint32_t *);

sys/dev/ic/pgt.c

2834

m_adj(args, sizeof(uint32_t));

sys/dev/ic/pgt.c

2840

if (args->m_len < sizeof(uint32_t))

sys/dev/ic/pgt.c

2842

ls = letoh32(*mtod(args, uint32_t *));

sys/dev/ic/pgt.c

286

uint32_t *uc;

sys/dev/ic/pgt.c

314

uc = (uint32_t *)ucode;

sys/dev/ic/pgt.c

444

htole32((uint32_t)sc->sc_cbdmam->dm_segs[0].ds_addr));

sys/dev/ic/pgt.c

640

uint32_t reg;

sys/dev/ic/pgt.c

686

uint32_t npend;

sys/dev/ic/pgt.c

911

uint32_t rstamp;

sys/dev/ic/pgtreg.h

110

uint32_t pf_addr; /* physical host address */

sys/dev/ic/pgtreg.h

117

uint32_t pcb_driver_curfrag[PGT_QUEUE_COUNT];

sys/dev/ic/pgtreg.h

118

uint32_t pcb_device_curfrag[PGT_QUEUE_COUNT];

sys/dev/ic/pgtreg.h

125

uint32_t pcb_padding;

sys/dev/ic/pgtreg.h

145

uint32_t pmf_oid;

sys/dev/ic/pgtreg.h

152

uint32_t pmf_size;

sys/dev/ic/pgtreg.h

159

uint32_t pra_clock; /* 1MHz timestamp */

sys/dev/ic/pgtreg.h

377

uint32_t pob_size;

sys/dev/ic/pgtreg.h

378

uint32_t pob_addr;

sys/dev/ic/pgtreg.h

400

uint32_t pob_count;

sys/dev/ic/pgtvar.h

101

uint32_t pmd_oid;

sys/dev/ic/pgtvar.h

149

uint32_t sc_noise;

sys/dev/ic/psp.c

207

ccp_wait(struct psp_softc *sc, uint32_t *status, int poll)

sys/dev/ic/psp.c

209

uint32_t cmdword;

sys/dev/ic/psp.c

242

uint32_t plo, phi, cmdword, status;

sys/dev/ic/psp.c

64

uint32_t sc_flags;

sys/dev/ic/psp.c

95

uint32_t status;

sys/dev/ic/pspvar.h

108

uint32_t cfges_build;

sys/dev/ic/pspvar.h

109

uint32_t guest_count;

sys/dev/ic/pspvar.h

114

uint32_t handle;

sys/dev/ic/pspvar.h

117

uint32_t policy;

sys/dev/ic/pspvar.h

118

uint32_t asid;

sys/dev/ic/pspvar.h

124

uint32_t handle;

sys/dev/ic/pspvar.h

127

uint32_t policy;

sys/dev/ic/pspvar.h

131

uint32_t dh_cert_len;

sys/dev/ic/pspvar.h

132

uint32_t reserved;

sys/dev/ic/pspvar.h

134

uint32_t session_len;

sys/dev/ic/pspvar.h

139

uint32_t handle;

sys/dev/ic/pspvar.h

140

uint32_t reserved;

sys/dev/ic/pspvar.h

142

uint32_t length;

sys/dev/ic/pspvar.h

147

uint32_t handle;

sys/dev/ic/pspvar.h

148

uint32_t reserved;

sys/dev/ic/pspvar.h

150

uint32_t length;

sys/dev/ic/pspvar.h

155

uint32_t handle;

sys/dev/ic/pspvar.h

156

uint32_t asid;

sys/dev/ic/pspvar.h

157

uint32_t vmid;

sys/dev/ic/pspvar.h

158

uint32_t vcpuid;

sys/dev/ic/pspvar.h

169

uint32_t handle;

sys/dev/ic/pspvar.h

170

uint32_t reserved;

sys/dev/ic/pspvar.h

174

uint32_t measure_len;

sys/dev/ic/pspvar.h

175

uint32_t padding;

sys/dev/ic/pspvar.h

185

uint32_t handle;

sys/dev/ic/pspvar.h

192

uint32_t report_policy;

sys/dev/ic/pspvar.h

193

uint32_t report_sig_usage;

sys/dev/ic/pspvar.h

194

uint32_t report_sig_algo;

sys/dev/ic/pspvar.h

195

uint32_t reserved2;

sys/dev/ic/pspvar.h

201

uint32_t handle;

sys/dev/ic/pspvar.h

202

uint32_t reserved;

sys/dev/ic/pspvar.h

207

uint32_t attest_len;

sys/dev/ic/pspvar.h

208

uint32_t padding;

sys/dev/ic/pspvar.h

222

uint32_t handle;

sys/dev/ic/pspvar.h

223

uint32_t asid;

sys/dev/ic/pspvar.h

228

uint32_t handle;

sys/dev/ic/pspvar.h

233

uint32_t handle;

sys/dev/ic/pspvar.h

238

uint32_t enable_es;

sys/dev/ic/pspvar.h

239

uint32_t reserved;

sys/dev/ic/pspvar.h

241

uint32_t tmr_length;

sys/dev/ic/pspvar.h

247

uint32_t fw_len;

sys/dev/ic/pspvar.h

252

uint32_t handle;

sys/dev/ic/pspvar.h

264

uint32_t build;

sys/dev/ic/pspvar.h

265

uint32_t features;

sys/dev/ic/pspvar.h

266

uint32_t guest_count;

sys/dev/ic/pspvar.h

296

uint32_t capabilities;

sys/dev/ic/qcuart.c

139

uint32_t stat;

sys/dev/ic/qcuart.c

166

uint32_t m_stat, s_stat;

sys/dev/ic/qcuart.c

548

uint32_t stat;

sys/dev/ic/qcuart.c

575

uint32_t stat;

sys/dev/ic/qwx.c

10011

uint32_t n_link_desc_bank, uint32_t n_link_desc, uint32_t last_bank_sz)

sys/dev/ic/qwx.c

10016

uint32_t n_entries_per_buf;

sys/dev/ic/qwx.c

10024

uint32_t end_offset;

sys/dev/ic/qwx.c

10081

uint32_t *

sys/dev/ic/qwx.c

10084

uint32_t *desc;

sys/dev/ic/qwx.c

10085

uint32_t next_hp;

sys/dev/ic/qwx.c

10115

uint32_t *

sys/dev/ic/qwx.c

10118

uint32_t *desc;

sys/dev/ic/qwx.c

10119

uint32_t next_reap_hp;

sys/dev/ic/qwx.c

10137

struct dp_link_desc_bank *link_desc_banks, uint32_t ring_type,

sys/dev/ic/qwx.c

10138

struct hal_srng *srng, uint32_t n_link_desc)

sys/dev/ic/qwx.c

10140

uint32_t tot_mem_sz;

sys/dev/ic/qwx.c

10141

uint32_t n_link_desc_bank, last_bank_sz;

sys/dev/ic/qwx.c

10142

uint32_t entry_sz, n_entries;

sys/dev/ic/qwx.c

10144

uint32_t *desc;

sys/dev/ic/qwx.c

10396

uint32_t ctrl_reg_val;

sys/dev/ic/qwx.c

10397

uint32_t addr;

sys/dev/ic/qwx.c

10400

uint32_t value;

sys/dev/ic/qwx.c

10439

sc->ops.write32(sc, addr, *(uint32_t *)&hw_map_val[i]);

sys/dev/ic/qwx.c

10454

uint32_t interval, uint32_t ring_id)

sys/dev/ic/qwx.c

10858

struct dp_link_desc_bank *desc_bank, uint32_t ring_type,

sys/dev/ic/qwx.c

10921

uint32_t n_link_desc = 0;

sys/dev/ic/qwx.c

11150

sizeof(uint32_t) * req->shadow_reg_v2_len);

sys/dev/ic/qwx.c

11326

uint32_t i;

sys/dev/ic/qwx.c

11356

uint32_t *wmi_ext2_service_bitmap;

sys/dev/ic/qwx.c

11382

wmi_ext2_service_bitmap = (uint32_t *)ptr;

sys/dev/ic/qwx.c

11561

const uint32_t *wmi_svc_bm)

sys/dev/ic/qwx.c

11589

expect_len = WMI_SERVICE_BM_SIZE * sizeof(uint32_t);

sys/dev/ic/qwx.c

11656

uint32_t phy_map;

sys/dev/ic/qwx.c

11657

uint32_t hw_idx, phy_idx = 0;

sys/dev/ic/qwx.c

11736

sizeof(uint32_t) * PSOC_HOST_MAX_PHY_SIZE);

sys/dev/ic/qwx.c

11750

sizeof(uint32_t) * PSOC_HOST_MAX_PHY_SIZE);

sys/dev/ic/qwx.c

11777

uint32_t phy_id_map;

sys/dev/ic/qwx.c

11831

uint32_t phy_map = 0;

sys/dev/ic/qwx.c

11873

uint32_t i;

sys/dev/ic/qwx.c

11990

uint32_t i;

sys/dev/ic/qwx.c

12033

qwx_wmi_alloc_dbring_caps(struct qwx_softc *sc, uint32_t num_cap)

sys/dev/ic/qwx.c

12065

uint32_t i;

sys/dev/ic/qwx.c

123

uint32_t qwx_debug = 0

sys/dev/ic/qwx.c

12334

uint32_t num_mac_addr;

sys/dev/ic/qwx.c

12444

qwx_wmi_vdev_resp_print(uint32_t vdev_resp_status)

sys/dev/ic/qwx.c

12504

uint32_t status;

sys/dev/ic/qwx.c

12528

uint32_t *vdev_id)

sys/dev/ic/qwx.c

12559

uint32_t vdev_id = 0;

sys/dev/ic/qwx.c

12615

uint32_t num_reg_rules, struct cur_reg_rule *reg_rule_ptr)

sys/dev/ic/qwx.c

12618

uint32_t count;

sys/dev/ic/qwx.c

12634

qwx_create_reg_rules_from_wmi(uint32_t num_reg_rules,

sys/dev/ic/qwx.c

12638

uint32_t count;

sys/dev/ic/qwx.c

12670

uint32_t num_2ghz_reg_rules, num_5ghz_reg_rules;

sys/dev/ic/qwx.c

1276

uint32_t reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;

sys/dev/ic/qwx.c

1277

uint32_t val;

sys/dev/ic/qwx.c

1279

uint32_t ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |

sys/dev/ic/qwx.c

13184

qwx_wmi_event_scan_foreign_chan(struct qwx_softc *sc, uint32_t freq)

sys/dev/ic/qwx.c

13301

qwx_pull_chan_info_ev(struct qwx_softc *sc, uint8_t *evt_buf, uint32_t len,

sys/dev/ic/qwx.c

13346

uint32_t cc_freq_hz = sc->cc_freq_hz;

sys/dev/ic/qwx.c

13603

uint32_t freq;

sys/dev/ic/qwx.c

13762

qwx_mac_handle_beacon_miss(struct qwx_softc *sc, uint32_t vdev_id)

sys/dev/ic/qwx.c

1379

uint32_t reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;

sys/dev/ic/qwx.c

1380

uint32_t val;

sys/dev/ic/qwx.c

1382

uint32_t ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |

sys/dev/ic/qwx.c

14067

qwx_connect_pdev_htc_service(struct qwx_softc *sc, uint32_t pdev_idx)

sys/dev/ic/qwx.c

14070

uint32_t svc_id[] = { ATH11K_HTC_SVC_ID_WMI_CONTROL,

sys/dev/ic/qwx.c

14105

uint32_t i;

sys/dev/ic/qwx.c

1420

uint32_t reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;

sys/dev/ic/qwx.c

1421

uint32_t val;

sys/dev/ic/qwx.c

1424

uint32_t ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |

sys/dev/ic/qwx.c

145

int qwx_wmi_set_peer_param(struct qwx_softc *, uint8_t *, uint32_t,

sys/dev/ic/qwx.c

146

uint32_t, uint32_t, uint32_t);

sys/dev/ic/qwx.c

14621

uint32_t svc_id[] = {

sys/dev/ic/qwx.c

14729

qwx_dp_get_mac_addr(uint32_t addr_l32, uint16_t addr_h16, uint8_t *addr)

sys/dev/ic/qwx.c

14737

uint32_t val32;

sys/dev/ic/qwx.c

148

uint8_t *, uint64_t, uint8_t, uint8_t, uint32_t);

sys/dev/ic/qwx.c

14831

*(uint32_t *)resp);

sys/dev/ic/qwx.c

1512

uint32_t

sys/dev/ic/qwx.c

15123

qwx_hal_rx_buf_addr_info_set(void *desc, uint64_t paddr, uint32_t cookie,

sys/dev/ic/qwx.c

15127

uint32_t paddr_lo, paddr_hi;

sys/dev/ic/qwx.c

15138

qwx_hal_rx_buf_addr_info_get(void *desc, uint64_t *paddr, uint32_t *cookie,

sys/dev/ic/qwx.c

15170

uint32_t *desc;

sys/dev/ic/qwx.c

15175

uint32_t cookie;

sys/dev/ic/qwx.c

15267

struct dp_rxdma_ring *rx_ring, uint32_t ringtype)

sys/dev/ic/qwx.c

15364

qwx_dp_tx_get_ring_id_type(struct qwx_softc *sc, int mac_id, uint32_t ring_id,

sys/dev/ic/qwx.c

15425

qwx_dp_tx_htt_srng_setup(struct qwx_softc *sc, uint32_t ring_id, int mac_id,

sys/dev/ic/qwx.c

15432

uint32_t ring_entry_sz;

sys/dev/ic/qwx.c

15533

qwx_dp_tx_htt_h2t_ppdu_stats_req(struct qwx_softc *sc, uint32_t mask,

sys/dev/ic/qwx.c

15570

qwx_dp_tx_htt_rx_filter_setup(struct qwx_softc *sc, uint32_t ring_id,

sys/dev/ic/qwx.c

15640

uint32_t ring_id;

sys/dev/ic/qwx.c

1589

uint32_t

sys/dev/ic/qwx.c

15937

uint8_t mac_id, uint32_t msdu_id, struct dp_tx_ring *tx_ring)

sys/dev/ic/qwx.c

16053

uint32_t msdu_id, struct hal_tx_status *ts)

sys/dev/ic/qwx.c

16118

uint32_t *desc;

sys/dev/ic/qwx.c

16119

uint32_t msdu_id;

sys/dev/ic/qwx.c

16149

uint32_t desc_id;

sys/dev/ic/qwx.c

16202

uint32_t *desc_bank)

sys/dev/ic/qwx.c

16214

qwx_hal_desc_reo_parse_err(struct qwx_softc *sc, uint32_t *rx_desc,

sys/dev/ic/qwx.c

16215

uint64_t *paddr, uint32_t *desc_bank)

sys/dev/ic/qwx.c

16248

qwx_hal_rx_msdu_link_info_get(void *link_desc, uint32_t *num_msdus,

sys/dev/ic/qwx.c

16249

uint32_t *msdu_cookies, enum hal_rx_buf_return_buf_manager *rbm)

sys/dev/ic/qwx.c

16291

qwx_dp_rx_link_desc_return(struct qwx_softc *sc, uint32_t *link_desc,

sys/dev/ic/qwx.c

16296

uint32_t *desc;

sys/dev/ic/qwx.c

16324

uint32_t *ring_desc)

sys/dev/ic/qwx.c

1634

uint32_t

sys/dev/ic/qwx.c

16355

qwx_dp_process_rx_err_buf(struct qwx_softc *sc, uint32_t *ring_desc,

sys/dev/ic/qwx.c

16364

uint32_t hal_rx_desc_sz = sc->hw_params.hal_desc_sz;

sys/dev/ic/qwx.c

16408

uint32_t msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];

sys/dev/ic/qwx.c

1641

uint32_t

sys/dev/ic/qwx.c

16415

uint32_t desc_bank, num_msdus;

sys/dev/ic/qwx.c

16421

uint32_t *desc;

sys/dev/ic/qwx.c

1650

uint32_t info = le32toh(desc->u.ipq8074.msdu_start.info1);

sys/dev/ic/qwx.c

16675

uint32_t *rx_desc;

sys/dev/ic/qwx.c

16835

static inline uint32_t

sys/dev/ic/qwx.c

16853

uint32_t

sys/dev/ic/qwx.c

16856

uint32_t info = le32toh(attn->info1);

sys/dev/ic/qwx.c

16857

uint32_t errmap = 0;

sys/dev/ic/qwx.c

16887

uint32_t errmap;

sys/dev/ic/qwx.c

16923

uint32_t meta_data;

sys/dev/ic/qwx.c

17207

uint32_t err_bitmap;

sys/dev/ic/qwx.c

1723

uint32_t

sys/dev/ic/qwx.c

17300

uint32_t hal_rx_desc_sz = sc->hw_params.hal_desc_sz;

sys/dev/ic/qwx.c

17381

uint32_t freq;

sys/dev/ic/qwx.c

174

int qwx_wmi_vdev_set_param_cmd(struct qwx_softc *, uint32_t, uint8_t,

sys/dev/ic/qwx.c

17466

uint32_t cookie;

sys/dev/ic/qwx.c

175

uint32_t, uint32_t);

sys/dev/ic/qwx.c

17649

uint32_t cookie;

sys/dev/ic/qwx.c

17774

uint32_t rx_buf_sz;

sys/dev/ic/qwx.c

17892

uint32_t msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];

sys/dev/ic/qwx.c

17900

uint32_t desc_bank;

sys/dev/ic/qwx.c

17966

qwx_hal_reo_status_queue_stats(struct qwx_softc *sc, uint32_t *reo_desc,

sys/dev/ic/qwx.c

1800

uint32_t

sys/dev/ic/qwx.c

18032

qwx_hal_reo_flush_queue_status(struct qwx_softc *sc, uint32_t *reo_desc,

sys/dev/ic/qwx.c

18048

qwx_hal_reo_flush_cache_status(struct qwx_softc *sc, uint32_t *reo_desc,

sys/dev/ic/qwx.c

18086

qwx_hal_reo_unblk_cache_status(struct qwx_softc *sc, uint32_t *reo_desc,

sys/dev/ic/qwx.c

18111

qwx_hal_reo_flush_timeout_list_status(struct qwx_softc *ab, uint32_t *reo_desc,

sys/dev/ic/qwx.c

18135

qwx_hal_reo_desc_thresh_reached_status(struct qwx_softc *sc, uint32_t *reo_desc,

sys/dev/ic/qwx.c

18165

qwx_hal_reo_update_rx_reo_queue_status(struct qwx_softc *ab, uint32_t *reo_desc,

sys/dev/ic/qwx.c

18185

uint32_t *reo_desc;

sys/dev/ic/qwx.c

18385

uint32_t round_len = roundup(len, 4);

sys/dev/ic/qwx.c

18396

uint32_t cmd_id)

sys/dev/ic/qwx.c

18400

uint32_t cmd = 0;

sys/dev/ic/qwx.c

18413

qwx_wmi_cmd_send(struct qwx_pdev_wmi *wmi, struct mbuf *m, uint32_t cmd_id)

sys/dev/ic/qwx.c

1845

uint32_t

sys/dev/ic/qwx.c

18468

qwx_wmi_pdev_set_param(struct qwx_softc *sc, uint32_t param_id,

sys/dev/ic/qwx.c

18469

uint32_t param_value, uint8_t pdev_id)

sys/dev/ic/qwx.c

1852

uint32_t

sys/dev/ic/qwx.c

18521

arc4random_buf(cmd->th_4, sizeof(uint32_t) * ATH11K_IPV4_TH_SEED_SIZE);

sys/dev/ic/qwx.c

18522

arc4random_buf(cmd->th_6, sizeof(uint32_t) * ATH11K_IPV6_TH_SEED_SIZE);

sys/dev/ic/qwx.c

18586

uint32_t prob_req_oui;

sys/dev/ic/qwx.c

18589

prob_req_oui = (((uint32_t)mac_addr[0]) << 16) |

sys/dev/ic/qwx.c

18590

(((uint32_t)mac_addr[1]) << 8) | mac_addr[2];

sys/dev/ic/qwx.c

1861

uint32_t info = le32toh(desc->u.qcn9074.msdu_start.info1);

sys/dev/ic/qwx.c

18621

qwx_wmi_send_dfs_phyerr_offload_enable_cmd(struct qwx_softc *sc, uint32_t pdev_id)

sys/dev/ic/qwx.c

18672

uint32_t *reg1, *reg2;

sys/dev/ic/qwx.c

18918

uint32_t *tmp_ptr;

sys/dev/ic/qwx.c

18927

len += params->num_chan * sizeof(uint32_t);

sys/dev/ic/qwx.c

18940

sizeof(uint32_t));

sys/dev/ic/qwx.c

18996

len = params->num_chan * sizeof(uint32_t);

sys/dev/ic/qwx.c

19002

tmp_ptr = (uint32_t *)ptr;

sys/dev/ic/qwx.c

19243

int key_len_aligned = roundup(arg->key_len, sizeof(uint32_t));

sys/dev/ic/qwx.c

1928

uint32_t

sys/dev/ic/qwx.c

19387

uint32_t peer_legacy_rates_align;

sys/dev/ic/qwx.c

19388

uint32_t peer_ht_rates_align;

sys/dev/ic/qwx.c

19392

sizeof(uint32_t));

sys/dev/ic/qwx.c

19394

sizeof(uint32_t));

sys/dev/ic/qwx.c

19627

uint32_t hw_mode_len = 0;

sys/dev/ic/qwx.c

19820

qwx_wmi_set_sta_ps_param(struct qwx_softc *sc, uint32_t vdev_id,

sys/dev/ic/qwx.c

19821

uint8_t pdev_id, uint32_t param, uint32_t param_value)

sys/dev/ic/qwx.c

19861

uint32_t buf_id, struct mbuf *frame, struct qwx_tx_data *tx_data)

sys/dev/ic/qwx.c

19867

uint32_t buf_len;

sys/dev/ic/qwx.c

1998

uint32_t

sys/dev/ic/qwx.c

20005

qwx_wmi_vdev_set_param_cmd(struct qwx_softc *sc, uint32_t vdev_id,

sys/dev/ic/qwx.c

20006

uint8_t pdev_id, uint32_t param_id, uint32_t param_value)

sys/dev/ic/qwx.c

20043

qwx_wmi_vdev_up(struct qwx_softc *sc, uint32_t vdev_id, uint32_t pdev_id,

sys/dev/ic/qwx.c

20044

uint32_t aid, const uint8_t *bssid, uint8_t *tx_bssid,

sys/dev/ic/qwx.c

20045

uint32_t nontx_profile_idx, uint32_t nontx_profile_cnt)

sys/dev/ic/qwx.c

20099

qwx_wmi_vdev_down(struct qwx_softc *sc, uint32_t vdev_id, uint8_t pdev_id)

sys/dev/ic/qwx.c

20136

uint32_t center_freq1 = arg->channel.band_center_freq1;

sys/dev/ic/qwx.c

2043

uint32_t

sys/dev/ic/qwx.c

2050

uint32_t

sys/dev/ic/qwx.c

2059

uint32_t info = le32toh(desc->u.wcn6855.msdu_start.info1);

sys/dev/ic/qwx.c

21104

srng->u.dst_ring.tp_addr = (uint32_t *)(

sys/dev/ic/qwx.c

21108

srng->u.src_ring.hp_addr = (uint32_t *)(

sys/dev/ic/qwx.c

21132

uint32_t target_reg;

sys/dev/ic/qwx.c

21187

qwx_hal_srng_get_shadow_config(struct qwx_softc *sc, uint32_t **cfg,

sys/dev/ic/qwx.c

21188

uint32_t *len)

sys/dev/ic/qwx.c

21200

size_t size = sizeof(uint32_t) * HAL_SRNG_RING_ID_MAX;

sys/dev/ic/qwx.c

21236

size_t size = sizeof(uint32_t) * HAL_SRNG_NUM_LMAC_RINGS;

sys/dev/ic/qwx.c

21304

uint32_t val;

sys/dev/ic/qwx.c

21306

uint32_t reg_base;

sys/dev/ic/qwx.c

21379

uint32_t val;

sys/dev/ic/qwx.c

21381

uint32_t reg_base;

sys/dev/ic/qwx.c

21414

sc->ops.write32(sc, reg_base, (uint32_t)srng->ring_base_paddr);

sys/dev/ic/qwx.c

21493

uint32_t addr;

sys/dev/ic/qwx.c

21494

uint32_t val;

sys/dev/ic/qwx.c

21508

qwx_hal_ce_src_set_desc(void *buf, uint64_t paddr, uint32_t len, uint32_t id,

sys/dev/ic/qwx.c

21535

uint32_t

sys/dev/ic/qwx.c

21540

uint32_t len;

sys/dev/ic/qwx.c

21557

uint32_t lmac_idx;

sys/dev/ic/qwx.c

21559

uint32_t reg_base;

sys/dev/ic/qwx.c

21617

(uint32_t *)((unsigned long)sc->mem +

sys/dev/ic/qwx.c

21650

(uint32_t *)((unsigned long)sc->mem +

sys/dev/ic/qwx.c

21707

uint32_t *desc;

sys/dev/ic/qwx.c

21899

uint32_t message_id, trailer_len = 0;

sys/dev/ic/qwx.c

22319

qwx_ce_get_shadow_config(struct qwx_softc *sc, uint32_t **shadow_cfg,

sys/dev/ic/qwx.c

22320

uint32_t *shadow_cfg_len)

sys/dev/ic/qwx.c

22386

qwx_get_ce_msi_idx(struct qwx_softc *sc, uint32_t ce_id,

sys/dev/ic/qwx.c

22387

uint32_t *msi_data_idx)

sys/dev/ic/qwx.c

22393

qwx_ce_srng_msi_ring_params_setup(struct qwx_softc *sc, uint32_t ce_id,

sys/dev/ic/qwx.c

22396

uint32_t msi_data_start = 0;

sys/dev/ic/qwx.c

22397

uint32_t msi_data_count = 1, msi_data_idx;

sys/dev/ic/qwx.c

22398

uint32_t msi_irq_start = 0;

sys/dev/ic/qwx.c

22399

uint32_t addr_lo;

sys/dev/ic/qwx.c

22400

uint32_t addr_hi;

sys/dev/ic/qwx.c

22425

params.ring_base_vaddr = (uint32_t *)ce_ring->base_addr;

sys/dev/ic/qwx.c

22542

uint32_t tp, hp;

sys/dev/ic/qwx.c

22569

uint32_t *desc;

sys/dev/ic/qwx.c

22583

srng->entry_size * sizeof(uint32_t), BUS_DMASYNC_POSTREAD);

sys/dev/ic/qwx.c

22608

srng->entry_size * sizeof(uint32_t), BUS_DMASYNC_PREREAD);

sys/dev/ic/qwx.c

22713

uint32_t *desc;

sys/dev/ic/qwx.c

22832

uint32_t *desc;

sys/dev/ic/qwx.c

22921

qwx_get_num_chains(uint32_t mask)

sys/dev/ic/qwx.c

22935

qwx_set_antenna(struct qwx_pdev *pdev, uint32_t tx_ant, uint32_t rx_ant)

sys/dev/ic/qwx.c

23158

uint32_t param;

sys/dev/ic/qwx.c

23159

uint32_t min_tx_power = sc->target_caps.hw_min_tx_power;

sys/dev/ic/qwx.c

23160

uint32_t max_tx_power = sc->target_caps.hw_max_tx_power;

sys/dev/ic/qwx.c

23337

uint32_t *flags, uint32_t *tx_vdev_id)

sys/dev/ic/qwx.c

23388

uint32_t param_id, param_value;

sys/dev/ic/qwx.c

23707

uint32_t param_id, param_value;

sys/dev/ic/qwx.c

24102

uint32_t preamble;

sys/dev/ic/qwx.c

24169

qwx_peer_delete(struct qwx_softc *sc, uint32_t vdev_id, uint8_t pdev_id,

sys/dev/ic/qwx.c

24398

uint32_t

sys/dev/ic/qwx.c

24399

qwx_hal_reo_qdesc_size(uint32_t ba_window_size, uint8_t tid)

sys/dev/ic/qwx.c

24401

uint32_t num_ext_desc;

sys/dev/ic/qwx.c

24421

qwx_hal_reo_set_desc_hdr(struct hal_desc_header *hdr, uint8_t owner, uint8_t buffer_type, uint32_t magic)

sys/dev/ic/qwx.c

24431

qwx_hal_reo_qdesc_setup(void *vaddr, int tid, uint32_t ba_window_size,

sys/dev/ic/qwx.c

24432

uint32_t start_seq, enum hal_pn_type type)

sys/dev/ic/qwx.c

24740

struct dp_rx_tid *rx_tid, uint32_t ba_win_sz, uint16_t ssn,

sys/dev/ic/qwx.c

24801

int vdev_id, int pdev_id, uint8_t tid, uint32_t ba_win_sz, uint16_t ssn,

sys/dev/ic/qwx.c

24807

uint32_t hw_desc_sz;

sys/dev/ic/qwx.c

24934

uint32_t reo_dest;

sys/dev/ic/qwx.c

25159

uint32_t ring_selector = 0;

sys/dev/ic/qwx.c

25557

uint32_t vdev_id, uint32_t pdev_id, uint32_t param_id, uint32_t param_val)

sys/dev/ic/qwx.c

25597

uint8_t ba_window_size_valid, uint32_t ba_window_size)

sys/dev/ic/qwx.c

25772

uint32_t scan_timeout;

sys/dev/ic/qwx.c

26053

uint32_t vdev_id, uint32_t pdev_id)

sys/dev/ic/qwx.c

26057

uint32_t vdev_param;

sys/dev/ic/qwx.c

26096

uint32_t param_id;

sys/dev/ic/qwx.c

26318

uint32_t stbc, aggsize, mpdu_density;

sys/dev/ic/qwx.c

26548

uint32_t val;

sys/dev/ic/qwx.c

4926

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5097

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5115

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5142

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5304

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5364

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5388

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5465

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5550

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5559

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5576

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5593

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5609

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5765

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5783

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5801

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5819

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5872

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5890

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

5997

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

6074

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

6092

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

6101

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

6110

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

6127

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

6145

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

6186

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

6203

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwx.c

6677

if (ei->elem_size != sizeof(uint32_t)) {

sys/dev/ic/qwx.c

6703

qwx_qmi_decode_datalen(struct qwx_softc *sc, size_t *used, uint32_t *datalen,

sys/dev/ic/qwx.c

6824

uint32_t min_size;

sys/dev/ic/qwx.c

6846

uint32_t datalen;

sys/dev/ic/qwx.c

6988

uint32_t nelem = 1, i;

sys/dev/ic/qwx.c

751

uint8_t *macaddr, struct ieee80211_key *k, uint32_t flags,

sys/dev/ic/qwx.c

7672

uint32_t pad = 0;

sys/dev/ic/qwx.c

7738

uint32_t pad = 0;

sys/dev/ic/qwx.c

7757

uint32_t type, size, hdrsize;

sys/dev/ic/qwx.c

7831

qwx_qmi_encode_datalen(uint8_t *p, uint32_t *datalen,

sys/dev/ic/qwx.c

7834

memcpy(datalen, input + ei->offset, sizeof(uint32_t));

sys/dev/ic/qwx.c

7889

uint32_t val;

sys/dev/ic/qwx.c

8061

uint32_t datalen = 0;

sys/dev/ic/qwx.c

8121

uint32_t datalen = 0;

sys/dev/ic/qwx.c

8302

uint32_t pad = 0;

sys/dev/ic/qwx.c

8452

uint32_t mem_seg_len;

sys/dev/ic/qwx.c

865

uint32_t flags = 0;

sys/dev/ic/qwx.c

8796

uint32_t id;

sys/dev/ic/qwx.c

8797

uint32_t len;

sys/dev/ic/qwx.c

9113

uint32_t remaining = len;

sys/dev/ic/qwx.c

9230

uint32_t fw_size;

sys/dev/ic/qwx.c

9386

uint32_t size;

sys/dev/ic/qwx.c

9437

qwx_hal_srng_get_entrysize(struct qwx_softc *sc, uint32_t ring_type)

sys/dev/ic/qwx.c

9447

uint32_t

sys/dev/ic/qwx.c

9448

qwx_hal_srng_get_max_entries(struct qwx_softc *sc, uint32_t ring_type)

sys/dev/ic/qwx.c

9458

uint32_t *

sys/dev/ic/qwx.c

9461

uint32_t *desc;

sys/dev/ic/qwx.c

9487

uint32_t tp, hp;

sys/dev/ic/qwx.c

9506

uint32_t *

sys/dev/ic/qwx.c

9509

uint32_t *desc;

sys/dev/ic/qwx.c

9523

uint32_t *

sys/dev/ic/qwx.c

9537

qwx_get_msi_address(struct qwx_softc *sc, uint32_t *addr_lo,

sys/dev/ic/qwx.c

9538

uint32_t *addr_hi)

sys/dev/ic/qwx.c

9616

uint32_t msi_data_start = 0;

sys/dev/ic/qwx.c

9617

uint32_t msi_data_count = 1;

sys/dev/ic/qwx.c

9618

uint32_t msi_irq_start = 0;

sys/dev/ic/qwx.c

9619

uint32_t addr_lo;

sys/dev/ic/qwx.c

9620

uint32_t addr_hi;

sys/dev/ic/qwx.c

9653

uint32_t max_entries = qwx_hal_srng_get_max_entries(sc, type);

sys/dev/ic/qwx.c

9773

*(volatile uint32_t *)srng->u.src_ring.tp_addr;

sys/dev/ic/qwx.c

9792

*(volatile uint32_t *)srng->u.src_ring.tp_addr;

sys/dev/ic/qwx.c

9801

*(volatile uint32_t *)srng->u.src_ring.tp_addr;

sys/dev/ic/qwx.c

9818

qwx_wbm_idle_ring_setup(struct qwx_softc *sc, uint32_t *n_link_desc)

sys/dev/ic/qwx.c

9821

uint32_t n_mpdu_link_desc, n_mpdu_queue_desc;

sys/dev/ic/qwx.c

9822

uint32_t n_tx_msdu_link_desc, n_rx_msdu_link_desc;

sys/dev/ic/qwx.c

9906

uint32_t nsbufs, uint32_t tot_link_desc, uint32_t end_offset)

sys/dev/ic/qwx.c

9910

uint32_t reg_scatter_buf_sz = HAL_WBM_IDLE_SCATTER_BUF_SIZE / 64;

sys/dev/ic/qwx.c

9980

qwx_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, uint32_t cookie,

sys/dev/ic/qwxreg.h

10030

uint32_t service_id;

sys/dev/ic/qwxreg.h

10031

uint32_t pipedir;

sys/dev/ic/qwxreg.h

10032

uint32_t pipenum;

sys/dev/ic/qwxreg.h

10042

uint32_t pipenum;

sys/dev/ic/qwxreg.h

10043

uint32_t pipedir;

sys/dev/ic/qwxreg.h

10044

uint32_t nentries;

sys/dev/ic/qwxreg.h

10045

uint32_t nbytes_max;

sys/dev/ic/qwxreg.h

10046

uint32_t flags;

sys/dev/ic/qwxreg.h

10047

uint32_t reserved;

sys/dev/ic/qwxreg.h

10096

uint32_t htc_info;

sys/dev/ic/qwxreg.h

10097

uint32_t ctrl_info;

sys/dev/ic/qwxreg.h

10137

uint32_t id_credit_count;

sys/dev/ic/qwxreg.h

10138

uint32_t size_ep;

sys/dev/ic/qwxreg.h

10143

uint32_t ver_bundle;

sys/dev/ic/qwxreg.h

10147

uint32_t msg_svc_id;

sys/dev/ic/qwxreg.h

10148

uint32_t flags_len;

sys/dev/ic/qwxreg.h

10152

uint32_t msg_svc_id;

sys/dev/ic/qwxreg.h

10153

uint32_t flags_len;

sys/dev/ic/qwxreg.h

10154

uint32_t svc_meta_pad;

sys/dev/ic/qwxreg.h

10160

uint32_t msg_id;

sys/dev/ic/qwxreg.h

10161

uint32_t flags;

sys/dev/ic/qwxreg.h

10162

uint32_t max_msgs_per_bundled_recv;

sys/dev/ic/qwxreg.h

10166

uint32_t msg_svc_id;

sys/dev/ic/qwxreg.h

10167

uint32_t flags_len;

sys/dev/ic/qwxreg.h

10509

uint32_t info1;

sys/dev/ic/qwxreg.h

10510

uint32_t info2;

sys/dev/ic/qwxreg.h

10794

uint32_t info1;

sys/dev/ic/qwxreg.h

10795

uint32_t info2;

sys/dev/ic/qwxreg.h

10796

uint32_t pn[4];

sys/dev/ic/qwxreg.h

10797

uint32_t peer_meta_data;

sys/dev/ic/qwxreg.h

10798

uint32_t info3;

sys/dev/ic/qwxreg.h

10799

uint32_t reo_queue_desc_lo;

sys/dev/ic/qwxreg.h

10800

uint32_t info4;

sys/dev/ic/qwxreg.h

10801

uint32_t info5;

sys/dev/ic/qwxreg.h

10802

uint32_t info6;

sys/dev/ic/qwxreg.h

10811

uint32_t ht_ctrl;

sys/dev/ic/qwxreg.h

10812

uint32_t raw;

sys/dev/ic/qwxreg.h

10897

uint32_t info7;

sys/dev/ic/qwxreg.h

10898

uint32_t reo_queue_desc_lo;

sys/dev/ic/qwxreg.h

10899

uint32_t info8;

sys/dev/ic/qwxreg.h

10900

uint32_t pn[4];

sys/dev/ic/qwxreg.h

10901

uint32_t info9;

sys/dev/ic/qwxreg.h

10902

uint32_t peer_meta_data;

sys/dev/ic/qwxreg.h

10907

uint32_t info11;

sys/dev/ic/qwxreg.h

10908

uint32_t info12;

sys/dev/ic/qwxreg.h

10909

uint32_t info13;

sys/dev/ic/qwxreg.h

10918

uint32_t ht_ctrl;

sys/dev/ic/qwxreg.h

10922

uint32_t info3;

sys/dev/ic/qwxreg.h

10923

uint32_t reo_queue_desc_lo;

sys/dev/ic/qwxreg.h

10924

uint32_t info4;

sys/dev/ic/qwxreg.h

10925

uint32_t pn[4];

sys/dev/ic/qwxreg.h

10926

uint32_t info2;

sys/dev/ic/qwxreg.h

10927

uint32_t peer_meta_data;

sys/dev/ic/qwxreg.h

10932

uint32_t info1;

sys/dev/ic/qwxreg.h

10933

uint32_t info5;

sys/dev/ic/qwxreg.h

10934

uint32_t info6;

sys/dev/ic/qwxreg.h

10943

uint32_t ht_ctrl;

sys/dev/ic/qwxreg.h

11181

uint32_t info1;

sys/dev/ic/qwxreg.h

11182

uint32_t info2;

sys/dev/ic/qwxreg.h

11183

uint32_t toeplitz_hash;

sys/dev/ic/qwxreg.h

11184

uint32_t flow_id_toeplitz;

sys/dev/ic/qwxreg.h

11185

uint32_t info3;

sys/dev/ic/qwxreg.h

11186

uint32_t ppdu_start_timestamp;

sys/dev/ic/qwxreg.h

11187

uint32_t phy_meta_data;

sys/dev/ic/qwxreg.h

11193

uint32_t info1;

sys/dev/ic/qwxreg.h

11194

uint32_t info2;

sys/dev/ic/qwxreg.h

11195

uint32_t toeplitz_hash;

sys/dev/ic/qwxreg.h

11196

uint32_t flow_id_toeplitz;

sys/dev/ic/qwxreg.h

11197

uint32_t info3;

sys/dev/ic/qwxreg.h

11198

uint32_t ppdu_start_timestamp;

sys/dev/ic/qwxreg.h

11199

uint32_t phy_meta_data;

sys/dev/ic/qwxreg.h

11207

uint32_t info1;

sys/dev/ic/qwxreg.h

11208

uint32_t info2;

sys/dev/ic/qwxreg.h

11209

uint32_t toeplitz_hash;

sys/dev/ic/qwxreg.h

11210

uint32_t flow_id_toeplitz;

sys/dev/ic/qwxreg.h

11211

uint32_t info3;

sys/dev/ic/qwxreg.h

11212

uint32_t ppdu_start_timestamp;

sys/dev/ic/qwxreg.h

11213

uint32_t phy_meta_data;

sys/dev/ic/qwxreg.h

11435

uint32_t info1;

sys/dev/ic/qwxreg.h

11436

uint32_t ext_wapi_pn[2];

sys/dev/ic/qwxreg.h

11437

uint32_t info2;

sys/dev/ic/qwxreg.h

11438

uint32_t ipv6_options_crc;

sys/dev/ic/qwxreg.h

11439

uint32_t tcp_seq_num;

sys/dev/ic/qwxreg.h

11440

uint32_t tcp_ack_num;

sys/dev/ic/qwxreg.h

11443

uint32_t info4;

sys/dev/ic/qwxreg.h

11444

uint32_t rule_indication[2];

sys/dev/ic/qwxreg.h

11447

uint32_t info5;

sys/dev/ic/qwxreg.h

11448

uint32_t fse_metadata;

sys/dev/ic/qwxreg.h

11458

uint32_t info1;

sys/dev/ic/qwxreg.h

11459

uint32_t ext_wapi_pn[2];

sys/dev/ic/qwxreg.h

11460

uint32_t info4;

sys/dev/ic/qwxreg.h

11461

uint32_t ipv6_options_crc;

sys/dev/ic/qwxreg.h

11462

uint32_t tcp_seq_num;

sys/dev/ic/qwxreg.h

11463

uint32_t tcp_ack_num;

sys/dev/ic/qwxreg.h

11466

uint32_t info2;

sys/dev/ic/qwxreg.h

11469

uint32_t info5;

sys/dev/ic/qwxreg.h

11470

uint32_t fse_metadata;

sys/dev/ic/qwxreg.h

11473

uint32_t rule_indication[2];

sys/dev/ic/qwxreg.h

11474

uint32_t info6;

sys/dev/ic/qwxreg.h

11475

uint32_t info7;

sys/dev/ic/qwxreg.h

11509

uint32_t info1;

sys/dev/ic/qwxreg.h

11510

uint32_t rule_indication[2];

sys/dev/ic/qwxreg.h

11511

uint32_t info2;

sys/dev/ic/qwxreg.h

11512

uint32_t ipv6_options_crc;

sys/dev/ic/qwxreg.h

11513

uint32_t tcp_seq_num;

sys/dev/ic/qwxreg.h

11514

uint32_t tcp_ack_num;

sys/dev/ic/qwxreg.h

11521

uint32_t info5;

sys/dev/ic/qwxreg.h

11522

uint32_t fse_metadata;

sys/dev/ic/qwxreg.h

11525

uint32_t info6;

sys/dev/ic/qwxreg.h

11717

uint32_t info1;

sys/dev/ic/qwxreg.h

11804

uint32_t msdu_end_tag;

sys/dev/ic/qwxreg.h

11806

uint32_t rx_attn_tag;

sys/dev/ic/qwxreg.h

11808

uint32_t msdu_start_tag;

sys/dev/ic/qwxreg.h

11811

uint32_t mpdu_start_tag;

sys/dev/ic/qwxreg.h

11813

uint32_t mpdu_end_tag;

sys/dev/ic/qwxreg.h

11816

uint32_t hdr_status_tag;

sys/dev/ic/qwxreg.h

11817

uint32_t phy_ppdu_id;

sys/dev/ic/qwxreg.h

11823

uint32_t msdu_end_tag;

sys/dev/ic/qwxreg.h

11825

uint32_t rx_attn_tag;

sys/dev/ic/qwxreg.h

11827

uint32_t msdu_start_tag;

sys/dev/ic/qwxreg.h

11830

uint32_t mpdu_start_tag;

sys/dev/ic/qwxreg.h

11832

uint32_t mpdu_end_tag;

sys/dev/ic/qwxreg.h

11835

uint32_t hdr_status_tag;

sys/dev/ic/qwxreg.h

11836

uint32_t phy_ppdu_id;

sys/dev/ic/qwxreg.h

11842

uint32_t msdu_end_tag;

sys/dev/ic/qwxreg.h

11844

uint32_t rx_attn_tag;

sys/dev/ic/qwxreg.h

11846

uint32_t msdu_start_tag;

sys/dev/ic/qwxreg.h

11849

uint32_t mpdu_start_tag;

sys/dev/ic/qwxreg.h

11851

uint32_t mpdu_end_tag;

sys/dev/ic/qwxreg.h

11854

uint32_t hdr_status_tag;

sys/dev/ic/qwxreg.h

11855

uint32_t phy_ppdu_id;

sys/dev/ic/qwxreg.h

11907

uint32_t info0;

sys/dev/ic/qwxreg.h

11908

uint32_t info1;

sys/dev/ic/qwxreg.h

11909

uint32_t info2;

sys/dev/ic/qwxreg.h

11910

uint32_t info3;

sys/dev/ic/qwxreg.h

11925

uint32_t ver_reg_info;

sys/dev/ic/qwxreg.h

120

uint32_t cmd_id;

sys/dev/ic/qwxreg.h

12093

uint32_t info0;

sys/dev/ic/qwxreg.h

12094

uint32_t ring_base_addr_lo;

sys/dev/ic/qwxreg.h

12095

uint32_t ring_base_addr_hi;

sys/dev/ic/qwxreg.h

12096

uint32_t info1;

sys/dev/ic/qwxreg.h

12097

uint32_t ring_head_off32_remote_addr_lo;

sys/dev/ic/qwxreg.h

12098

uint32_t ring_head_off32_remote_addr_hi;

sys/dev/ic/qwxreg.h

12099

uint32_t ring_tail_off32_remote_addr_lo;

sys/dev/ic/qwxreg.h

12100

uint32_t ring_tail_off32_remote_addr_hi;

sys/dev/ic/qwxreg.h

12101

uint32_t ring_msi_addr_lo;

sys/dev/ic/qwxreg.h

12102

uint32_t ring_msi_addr_hi;

sys/dev/ic/qwxreg.h

12103

uint32_t msi_data;

sys/dev/ic/qwxreg.h

12104

uint32_t intr_info;

sys/dev/ic/qwxreg.h

12105

uint32_t info2;

sys/dev/ic/qwxreg.h

12142

uint32_t msg;

sys/dev/ic/qwxreg.h

124

uint32_t header;

sys/dev/ic/qwxreg.h

12568

uint32_t info0;

sys/dev/ic/qwxreg.h

12569

uint32_t info1;

sys/dev/ic/qwxreg.h

12570

uint32_t pkt_type_en_flags0;

sys/dev/ic/qwxreg.h

12571

uint32_t pkt_type_en_flags1;

sys/dev/ic/qwxreg.h

12572

uint32_t pkt_type_en_flags2;

sys/dev/ic/qwxreg.h

12573

uint32_t pkt_type_en_flags3;

sys/dev/ic/qwxreg.h

12574

uint32_t rx_filter_tlv;

sys/dev/ic/qwxreg.h

12578

uint32_t rx_filter; /* see htt_rx_filter_tlv_flags */

sys/dev/ic/qwxreg.h

12579

uint32_t pkt_filter_flags0; /* MGMT */

sys/dev/ic/qwxreg.h

12580

uint32_t pkt_filter_flags1; /* MGMT */

sys/dev/ic/qwxreg.h

12581

uint32_t pkt_filter_flags2; /* CTRL */

sys/dev/ic/qwxreg.h

12582

uint32_t pkt_filter_flags3; /* DATA */

sys/dev/ic/qwxreg.h

12607

uint32_t info0;

sys/dev/ic/qwxreg.h

12608

uint32_t cfg;

sys/dev/ic/qwxreg.h

12634

uint32_t version;

sys/dev/ic/qwxreg.h

12646

uint32_t info;

sys/dev/ic/qwxreg.h

12647

uint32_t mac_addr_l32;

sys/dev/ic/qwxreg.h

12648

uint32_t info1;

sys/dev/ic/qwxreg.h

12649

uint32_t info2;

sys/dev/ic/qwxreg.h

12660

uint32_t info;

sys/dev/ic/qwxreg.h

12661

uint32_t mac_addr_l32;

sys/dev/ic/qwxreg.h

12662

uint32_t info1;

sys/dev/ic/qwxreg.h

12768

uint32_t info;

sys/dev/ic/qwxreg.h

12769

uint32_t ppdu_id;

sys/dev/ic/qwxreg.h

12770

uint32_t timestamp;

sys/dev/ic/qwxreg.h

12771

uint32_t rsvd;

sys/dev/ic/qwxreg.h

12776

uint32_t header;

sys/dev/ic/qwxreg.h

12799

uint32_t ppdu_id;

sys/dev/ic/qwxreg.h

12803

uint32_t flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/

sys/dev/ic/qwxreg.h

12804

uint32_t chain_mask;

sys/dev/ic/qwxreg.h

12805

uint32_t fes_duration_us; /* frame exchange sequence */

sys/dev/ic/qwxreg.h

12806

uint32_t ppdu_sch_eval_start_tstmp_us;

sys/dev/ic/qwxreg.h

12807

uint32_t ppdu_sch_end_tstmp_us;

sys/dev/ic/qwxreg.h

12808

uint32_t ppdu_start_tstmp_us;

sys/dev/ic/qwxreg.h

12870

uint32_t info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/

sys/dev/ic/qwxreg.h

12875

uint32_t info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */

sys/dev/ic/qwxreg.h

12876

uint32_t rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */

sys/dev/ic/qwxreg.h

12878

uint32_t resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */

sys/dev/ic/qwxreg.h

12899

uint32_t tx_success_bytes;

sys/dev/ic/qwxreg.h

12900

uint32_t tx_retry_bytes;

sys/dev/ic/qwxreg.h

12901

uint32_t tx_failed_bytes;

sys/dev/ic/qwxreg.h

12902

uint32_t flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */

sys/dev/ic/qwxreg.h

12934

uint32_t ack_rssi;

sys/dev/ic/qwxreg.h

12937

uint32_t flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/

sys/dev/ic/qwxreg.h

12947

uint32_t ppdu_id;

sys/dev/ic/qwxreg.h

12950

uint32_t info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */

sys/dev/ic/qwxreg.h

12953

uint32_t success_bytes;

sys/dev/ic/qwxreg.h

12958

uint32_t num_ppdu_stats;

sys/dev/ic/qwxreg.h

12969

uint32_t tlv_flags;

sys/dev/ic/qwxreg.h

12985

uint32_t ppdu_id;

sys/dev/ic/qwxreg.h

130

#define TLV_HDR_SIZE sizeof(uint32_t) /* wmi_tlv.header */

sys/dev/ic/qwxreg.h

13026

uint32_t hdr;

sys/dev/ic/qwxreg.h

13116

uint32_t cfg_param0;

sys/dev/ic/qwxreg.h

13117

uint32_t cfg_param1;

sys/dev/ic/qwxreg.h

13118

uint32_t cfg_param2;

sys/dev/ic/qwxreg.h

13119

uint32_t cfg_param3;

sys/dev/ic/qwxreg.h

13120

uint32_t reserved;

sys/dev/ic/qwxreg.h

13121

uint32_t cookie_lsb;

sys/dev/ic/qwxreg.h

13122

uint32_t cookie_msb;

sys/dev/ic/qwxreg.h

13159

uint32_t cfg0;

sys/dev/ic/qwxreg.h

13160

uint32_t cfg1;

sys/dev/ic/qwxreg.h

13161

uint32_t cfg2;

sys/dev/ic/qwxreg.h

13162

uint32_t cfg3;

sys/dev/ic/qwxreg.h

13243

uint32_t info0;

sys/dev/ic/qwxreg.h

13245

uint32_t info1;

sys/dev/ic/qwxreg.h

2295

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

2296

uint32_t start_freq;

sys/dev/ic/qwxreg.h

2297

uint32_t end_freq;

sys/dev/ic/qwxreg.h

2301

uint32_t numss_m1;

sys/dev/ic/qwxreg.h

2302

uint32_t ru_bit_mask;

sys/dev/ic/qwxreg.h

2303

uint32_t ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS];

sys/dev/ic/qwxreg.h

2307

uint32_t default_conc_scan_config_bits;

sys/dev/ic/qwxreg.h

2308

uint32_t default_fw_config_bits;

sys/dev/ic/qwxreg.h

2310

uint32_t he_cap_info;

sys/dev/ic/qwxreg.h

2311

uint32_t mpdu_density;

sys/dev/ic/qwxreg.h

2312

uint32_t max_bssid_rx_filters;

sys/dev/ic/qwxreg.h

2313

uint32_t num_hw_modes;

sys/dev/ic/qwxreg.h

2314

uint32_t num_phy;

sys/dev/ic/qwxreg.h

2318

uint32_t hw_mode_id;

sys/dev/ic/qwxreg.h

2319

uint32_t phy_id_map;

sys/dev/ic/qwxreg.h

2320

uint32_t hw_mode_config_type;

sys/dev/ic/qwxreg.h

2332

uint32_t phy_id;

sys/dev/ic/qwxreg.h

2333

uint32_t eeprom_reg_domain;

sys/dev/ic/qwxreg.h

2334

uint32_t eeprom_reg_domain_ext;

sys/dev/ic/qwxreg.h

2335

uint32_t regcap1;

sys/dev/ic/qwxreg.h

2336

uint32_t regcap2;

sys/dev/ic/qwxreg.h

2337

uint32_t wireless_modes;

sys/dev/ic/qwxreg.h

2338

uint32_t low_2ghz_chan;

sys/dev/ic/qwxreg.h

2339

uint32_t high_2ghz_chan;

sys/dev/ic/qwxreg.h

2340

uint32_t low_5ghz_chan;

sys/dev/ic/qwxreg.h

2341

uint32_t high_5ghz_chan;

sys/dev/ic/qwxreg.h

2347

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

2348

uint32_t req_id;

sys/dev/ic/qwxreg.h

2349

uint32_t ptr;

sys/dev/ic/qwxreg.h

2350

uint32_t size;

sys/dev/ic/qwxreg.h

2356

uint32_t len;

sys/dev/ic/qwxreg.h

2357

uint32_t req_id;

sys/dev/ic/qwxreg.h

2361

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

2365

uint32_t hw_mode_id;

sys/dev/ic/qwxreg.h

2366

uint32_t num_band_to_mac;

sys/dev/ic/qwxreg.h

2371

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

2372

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

2373

uint32_t start_freq;

sys/dev/ic/qwxreg.h

2374

uint32_t end_freq;

sys/dev/ic/qwxreg.h

2378

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

2379

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

2380

uint32_t hw_mode_index;

sys/dev/ic/qwxreg.h

2381

uint32_t num_band_to_mac;

sys/dev/ic/qwxreg.h

2385

uint32_t numss_m1; /** NSS - 1*/

sys/dev/ic/qwxreg.h

2387

uint32_t ru_count;

sys/dev/ic/qwxreg.h

2388

uint32_t ru_mask;

sys/dev/ic/qwxreg.h

2390

uint32_t ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS];

sys/dev/ic/qwxreg.h

2396

uint32_t abi_version_0;

sys/dev/ic/qwxreg.h

2397

uint32_t abi_version_1;

sys/dev/ic/qwxreg.h

2398

uint32_t abi_version_ns_0;

sys/dev/ic/qwxreg.h

2399

uint32_t abi_version_ns_1;

sys/dev/ic/qwxreg.h

2400

uint32_t abi_version_ns_2;

sys/dev/ic/qwxreg.h

2401

uint32_t abi_version_ns_3;

sys/dev/ic/qwxreg.h

2405

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

2407

uint32_t num_host_mem_chunks;

sys/dev/ic/qwxreg.h

2417

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

2418

uint32_t num_vdevs;

sys/dev/ic/qwxreg.h

2419

uint32_t num_peers;

sys/dev/ic/qwxreg.h

2420

uint32_t num_offload_peers;

sys/dev/ic/qwxreg.h

2421

uint32_t num_offload_reorder_buffs;

sys/dev/ic/qwxreg.h

2422

uint32_t num_peer_keys;

sys/dev/ic/qwxreg.h

2423

uint32_t num_tids;

sys/dev/ic/qwxreg.h

2424

uint32_t ast_skid_limit;

sys/dev/ic/qwxreg.h

2425

uint32_t tx_chain_mask;

sys/dev/ic/qwxreg.h

2426

uint32_t rx_chain_mask;

sys/dev/ic/qwxreg.h

2427

uint32_t rx_timeout_pri[4];

sys/dev/ic/qwxreg.h

2428

uint32_t rx_decap_mode;

sys/dev/ic/qwxreg.h

2429

uint32_t scan_max_pending_req;

sys/dev/ic/qwxreg.h

2430

uint32_t bmiss_offload_max_vdev;

sys/dev/ic/qwxreg.h

2431

uint32_t roam_offload_max_vdev;

sys/dev/ic/qwxreg.h

2432

uint32_t roam_offload_max_ap_profiles;

sys/dev/ic/qwxreg.h

2433

uint32_t num_mcast_groups;

sys/dev/ic/qwxreg.h

2434

uint32_t num_mcast_table_elems;

sys/dev/ic/qwxreg.h

2435

uint32_t mcast2ucast_mode;

sys/dev/ic/qwxreg.h

2436

uint32_t tx_dbg_log_size;

sys/dev/ic/qwxreg.h

2437

uint32_t num_wds_entries;

sys/dev/ic/qwxreg.h

2438

uint32_t dma_burst_size;

sys/dev/ic/qwxreg.h

2439

uint32_t mac_aggr_delim;

sys/dev/ic/qwxreg.h

2440

uint32_t rx_skip_defrag_timeout_dup_detection_check;

sys/dev/ic/qwxreg.h

2441

uint32_t vow_config;

sys/dev/ic/qwxreg.h

2442

uint32_t gtk_offload_max_vdev;

sys/dev/ic/qwxreg.h

2443

uint32_t num_msdu_desc;

sys/dev/ic/qwxreg.h

2444

uint32_t max_frag_entries;

sys/dev/ic/qwxreg.h

2445

uint32_t num_tdls_vdevs;

sys/dev/ic/qwxreg.h

2446

uint32_t num_tdls_conn_table_entries;

sys/dev/ic/qwxreg.h

2447

uint32_t beacon_tx_offload_max_vdev;

sys/dev/ic/qwxreg.h

2448

uint32_t num_multicast_filter_entries;

sys/dev/ic/qwxreg.h

2449

uint32_t num_wow_filters;

sys/dev/ic/qwxreg.h

2450

uint32_t num_keep_alive_pattern;

sys/dev/ic/qwxreg.h

2451

uint32_t keep_alive_pattern_size;

sys/dev/ic/qwxreg.h

2452

uint32_t max_tdls_concurrent_sleep_sta;

sys/dev/ic/qwxreg.h

2453

uint32_t max_tdls_concurrent_buffer_sta;

sys/dev/ic/qwxreg.h

2454

uint32_t wmi_send_separate;

sys/dev/ic/qwxreg.h

2455

uint32_t num_ocb_vdevs;

sys/dev/ic/qwxreg.h

2456

uint32_t num_ocb_channels;

sys/dev/ic/qwxreg.h

2457

uint32_t num_ocb_schedules;

sys/dev/ic/qwxreg.h

2458

uint32_t flag1;

sys/dev/ic/qwxreg.h

2459

uint32_t smart_ant_cap;

sys/dev/ic/qwxreg.h

2460

uint32_t bk_minfree;

sys/dev/ic/qwxreg.h

2461

uint32_t be_minfree;

sys/dev/ic/qwxreg.h

2462

uint32_t vi_minfree;

sys/dev/ic/qwxreg.h

2463

uint32_t vo_minfree;

sys/dev/ic/qwxreg.h

2464

uint32_t alloc_frag_desc_for_data_pkt;

sys/dev/ic/qwxreg.h

2465

uint32_t num_ns_ext_tuples_cfg;

sys/dev/ic/qwxreg.h

2466

uint32_t bpf_instruction_size;

sys/dev/ic/qwxreg.h

2467

uint32_t max_bssid_rx_filters;

sys/dev/ic/qwxreg.h

2468

uint32_t use_pdev_id;

sys/dev/ic/qwxreg.h

2469

uint32_t max_num_dbs_scan_duty_cycle;

sys/dev/ic/qwxreg.h

2470

uint32_t max_num_group_keys;

sys/dev/ic/qwxreg.h

2471

uint32_t peer_map_unmap_v2_support;

sys/dev/ic/qwxreg.h

2472

uint32_t sched_params;

sys/dev/ic/qwxreg.h

2473

uint32_t twt_ap_pdev_count;

sys/dev/ic/qwxreg.h

2474

uint32_t twt_ap_sta_count;

sys/dev/ic/qwxreg.h

2476

uint32_t max_nlo_ssids;

sys/dev/ic/qwxreg.h

2477

uint32_t num_pkt_filters;

sys/dev/ic/qwxreg.h

2478

uint32_t num_max_sta_vdevs;

sys/dev/ic/qwxreg.h

2479

uint32_t max_bssid_indicator;

sys/dev/ic/qwxreg.h

2480

uint32_t ul_resp_config;

sys/dev/ic/qwxreg.h

2481

uint32_t msdu_flow_override_config0;

sys/dev/ic/qwxreg.h

2482

uint32_t msdu_flow_override_config1;

sys/dev/ic/qwxreg.h

2483

uint32_t flags2;

sys/dev/ic/qwxreg.h

2484

uint32_t host_service_flags;

sys/dev/ic/qwxreg.h

2485

uint32_t max_rnr_neighbours;

sys/dev/ic/qwxreg.h

2486

uint32_t ema_max_vap_cnt;

sys/dev/ic/qwxreg.h

2487

uint32_t ema_max_profile_period;

sys/dev/ic/qwxreg.h

2492

uint32_t fw_build_vers;

sys/dev/ic/qwxreg.h

2494

uint32_t phy_capability;

sys/dev/ic/qwxreg.h

2495

uint32_t max_frag_entry;

sys/dev/ic/qwxreg.h

2496

uint32_t num_rf_chains;

sys/dev/ic/qwxreg.h

2497

uint32_t ht_cap_info;

sys/dev/ic/qwxreg.h

2498

uint32_t vht_cap_info;

sys/dev/ic/qwxreg.h

2499

uint32_t vht_supp_mcs;

sys/dev/ic/qwxreg.h

2500

uint32_t hw_min_tx_power;

sys/dev/ic/qwxreg.h

2501

uint32_t hw_max_tx_power;

sys/dev/ic/qwxreg.h

2502

uint32_t sys_cap_info;

sys/dev/ic/qwxreg.h

2503

uint32_t min_pkt_size_enable;

sys/dev/ic/qwxreg.h

2504

uint32_t max_bcn_ie_size;

sys/dev/ic/qwxreg.h

2505

uint32_t num_mem_reqs;

sys/dev/ic/qwxreg.h

2506

uint32_t max_num_scan_channels;

sys/dev/ic/qwxreg.h

2507

uint32_t hw_bd_id;

sys/dev/ic/qwxreg.h

2508

uint32_t hw_bd_info[HW_BD_INFO_SIZE];

sys/dev/ic/qwxreg.h

2509

uint32_t max_supported_macs;

sys/dev/ic/qwxreg.h

2510

uint32_t wmi_fw_sub_feat_caps;

sys/dev/ic/qwxreg.h

2511

uint32_t num_dbs_hw_modes;

sys/dev/ic/qwxreg.h

2518

uint32_t txrx_chainmask;

sys/dev/ic/qwxreg.h

2519

uint32_t default_dbs_hw_mode_index;

sys/dev/ic/qwxreg.h

2520

uint32_t num_msdu_desc;

sys/dev/ic/qwxreg.h

2523

#define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(uint32_t) - 1) / sizeof(uint32_t))

sys/dev/ic/qwxreg.h

2526

#define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(uint32_t))

sys/dev/ic/qwxreg.h

2531

uint32_t default_conc_scan_config_bits;

sys/dev/ic/qwxreg.h

2532

uint32_t default_fw_config_bits;

sys/dev/ic/qwxreg.h

2534

uint32_t he_cap_info;

sys/dev/ic/qwxreg.h

2535

uint32_t mpdu_density;

sys/dev/ic/qwxreg.h

2536

uint32_t max_bssid_rx_filters;

sys/dev/ic/qwxreg.h

2537

uint32_t fw_build_vers_ext;

sys/dev/ic/qwxreg.h

2538

uint32_t max_nlo_ssids;

sys/dev/ic/qwxreg.h

2539

uint32_t max_bssid_indicator;

sys/dev/ic/qwxreg.h

2540

uint32_t he_cap_info_ext;

sys/dev/ic/qwxreg.h

2544

uint32_t num_hw_modes;

sys/dev/ic/qwxreg.h

2545

uint32_t num_chainmask_tables;

sys/dev/ic/qwxreg.h

2549

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

2550

uint32_t hw_mode_id;

sys/dev/ic/qwxreg.h

2551

uint32_t phy_id_map;

sys/dev/ic/qwxreg.h

2552

uint32_t hw_mode_config_type;

sys/dev/ic/qwxreg.h

2564

uint32_t hw_mode_id;

sys/dev/ic/qwxreg.h

2565

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

2566

uint32_t phy_id;

sys/dev/ic/qwxreg.h

2567

uint32_t supported_flags;

sys/dev/ic/qwxreg.h

2568

uint32_t supported_bands;

sys/dev/ic/qwxreg.h

2569

uint32_t ampdu_density;

sys/dev/ic/qwxreg.h

2570

uint32_t max_bw_supported_2g;

sys/dev/ic/qwxreg.h

2571

uint32_t ht_cap_info_2g;

sys/dev/ic/qwxreg.h

2572

uint32_t vht_cap_info_2g;

sys/dev/ic/qwxreg.h

2573

uint32_t vht_supp_mcs_2g;

sys/dev/ic/qwxreg.h

2574

uint32_t he_cap_info_2g;

sys/dev/ic/qwxreg.h

2575

uint32_t he_supp_mcs_2g;

sys/dev/ic/qwxreg.h

2576

uint32_t tx_chain_mask_2g;

sys/dev/ic/qwxreg.h

2577

uint32_t rx_chain_mask_2g;

sys/dev/ic/qwxreg.h

2578

uint32_t max_bw_supported_5g;

sys/dev/ic/qwxreg.h

2579

uint32_t ht_cap_info_5g;

sys/dev/ic/qwxreg.h

2580

uint32_t vht_cap_info_5g;

sys/dev/ic/qwxreg.h

2581

uint32_t vht_supp_mcs_5g;

sys/dev/ic/qwxreg.h

2582

uint32_t he_cap_info_5g;

sys/dev/ic/qwxreg.h

2583

uint32_t he_supp_mcs_5g;

sys/dev/ic/qwxreg.h

2584

uint32_t tx_chain_mask_5g;

sys/dev/ic/qwxreg.h

2585

uint32_t rx_chain_mask_5g;

sys/dev/ic/qwxreg.h

2586

uint32_t he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE];

sys/dev/ic/qwxreg.h

2587

uint32_t he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE];

sys/dev/ic/qwxreg.h

2590

uint32_t chainmask_table_id;

sys/dev/ic/qwxreg.h

2591

uint32_t lmac_id;

sys/dev/ic/qwxreg.h

2592

uint32_t he_cap_info_2g_ext;

sys/dev/ic/qwxreg.h

2593

uint32_t he_cap_info_5g_ext;

sys/dev/ic/qwxreg.h

2594

uint32_t he_cap_info_internal;

sys/dev/ic/qwxreg.h

2595

uint32_t wireless_modes;

sys/dev/ic/qwxreg.h

2596

uint32_t low_2ghz_chan_freq;

sys/dev/ic/qwxreg.h

2597

uint32_t high_2ghz_chan_freq;

sys/dev/ic/qwxreg.h

2598

uint32_t low_5ghz_chan_freq;

sys/dev/ic/qwxreg.h

2599

uint32_t high_5ghz_chan_freq;

sys/dev/ic/qwxreg.h

2600

uint32_t nss_ratio;

sys/dev/ic/qwxreg.h

2604

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

2605

uint32_t phy_id;

sys/dev/ic/qwxreg.h

2606

uint32_t eeprom_reg_domain;

sys/dev/ic/qwxreg.h

2607

uint32_t eeprom_reg_domain_ext;

sys/dev/ic/qwxreg.h

2608

uint32_t regcap1;

sys/dev/ic/qwxreg.h

2609

uint32_t regcap2;

sys/dev/ic/qwxreg.h

2610

uint32_t wireless_modes;

sys/dev/ic/qwxreg.h

2611

uint32_t low_2ghz_chan;

sys/dev/ic/qwxreg.h

2612

uint32_t high_2ghz_chan;

sys/dev/ic/qwxreg.h

2613

uint32_t low_5ghz_chan;

sys/dev/ic/qwxreg.h

2614

uint32_t high_5ghz_chan;

sys/dev/ic/qwxreg.h

2618

uint32_t num_phy;

sys/dev/ic/qwxreg.h

2626

uint32_t word0;

sys/dev/ic/qwxreg.h

2627

uint32_t word1;

sys/dev/ic/qwxreg.h

2633

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

2634

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

2635

uint32_t module_id;

sys/dev/ic/qwxreg.h

2636

uint32_t min_elem;

sys/dev/ic/qwxreg.h

2637

uint32_t min_buf_sz;

sys/dev/ic/qwxreg.h

2638

uint32_t min_buf_align;

sys/dev/ic/qwxreg.h

2644

uint32_t status;

sys/dev/ic/qwxreg.h

2645

uint32_t num_dscp_table;

sys/dev/ic/qwxreg.h

2646

uint32_t num_extra_mac_addr;

sys/dev/ic/qwxreg.h

2647

uint32_t num_total_peers;

sys/dev/ic/qwxreg.h

2648

uint32_t num_extra_peers;

sys/dev/ic/qwxreg.h

2653

uint32_t max_ast_index;

sys/dev/ic/qwxreg.h

2654

uint32_t pktlog_defs_checksum;

sys/dev/ic/qwxreg.h

2658

uint32_t wmi_service_segment_offset;

sys/dev/ic/qwxreg.h

2659

uint32_t wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32];

sys/dev/ic/qwxreg.h

2664

uint32_t type;

sys/dev/ic/qwxreg.h

2665

uint32_t subtype;

sys/dev/ic/qwxreg.h

2670

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

2671

uint32_t mbssid_flags;

sys/dev/ic/qwxreg.h

2672

uint32_t mbssid_tx_vdev_id;

sys/dev/ic/qwxreg.h

2676

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

2677

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

2678

uint32_t vdev_type;

sys/dev/ic/qwxreg.h

2679

uint32_t vdev_subtype;

sys/dev/ic/qwxreg.h

2681

uint32_t num_cfg_txrx_streams;

sys/dev/ic/qwxreg.h

2682

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

2683

uint32_t mbssid_flags;

sys/dev/ic/qwxreg.h

2684

uint32_t mbssid_tx_vdev_id;

sys/dev/ic/qwxreg.h

2688

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

2689

uint32_t band;

sys/dev/ic/qwxreg.h

2690

uint32_t supported_tx_streams;

sys/dev/ic/qwxreg.h

2691

uint32_t supported_rx_streams;

sys/dev/ic/qwxreg.h

2695

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

2696

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

2700

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

2701

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

2702

uint32_t vdev_assoc_id;

sys/dev/ic/qwxreg.h

2705

uint32_t nontx_profile_idx;

sys/dev/ic/qwxreg.h

2706

uint32_t nontx_profile_cnt;

sys/dev/ic/qwxreg.h

2710

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

2711

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

2715

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

2716

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

2725

uint32_t ssid_len;

sys/dev/ic/qwxreg.h

2726

uint32_t ssid[8];

sys/dev/ic/qwxreg.h

2732

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

2733

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

2734

uint32_t requestor_id;

sys/dev/ic/qwxreg.h

2735

uint32_t beacon_interval;

sys/dev/ic/qwxreg.h

2736

uint32_t dtim_period;

sys/dev/ic/qwxreg.h

2737

uint32_t flags;

sys/dev/ic/qwxreg.h

2739

uint32_t bcn_tx_rate;

sys/dev/ic/qwxreg.h

2740

uint32_t bcn_txpower;

sys/dev/ic/qwxreg.h

2741

uint32_t num_noa_descriptors;

sys/dev/ic/qwxreg.h

2742

uint32_t disable_hw_ack;

sys/dev/ic/qwxreg.h

2743

uint32_t preferred_tx_streams;

sys/dev/ic/qwxreg.h

2744

uint32_t preferred_rx_streams;

sys/dev/ic/qwxreg.h

2745

uint32_t he_ops;

sys/dev/ic/qwxreg.h

2746

uint32_t cac_duration_ms;

sys/dev/ic/qwxreg.h

2747

uint32_t regdomain;

sys/dev/ic/qwxreg.h

2748

uint32_t min_data_rate;

sys/dev/ic/qwxreg.h

2749

uint32_t mbssid_flags;

sys/dev/ic/qwxreg.h

2750

uint32_t mbssid_tx_vdev_id;

sys/dev/ic/qwxreg.h

2761

uint32_t type_count;

sys/dev/ic/qwxreg.h

2762

uint32_t duration;

sys/dev/ic/qwxreg.h

2763

uint32_t interval;

sys/dev/ic/qwxreg.h

2764

uint32_t start_time;

sys/dev/ic/qwxreg.h

2770

uint32_t mhz;

sys/dev/ic/qwxreg.h

2771

uint32_t half_rate:1,

sys/dev/ic/qwxreg.h

2781

uint32_t phy_mode;

sys/dev/ic/qwxreg.h

2782

uint32_t cfreq1;

sys/dev/ic/qwxreg.h

2783

uint32_t cfreq2;

sys/dev/ic/qwxreg.h

2884

uint32_t freq;

sys/dev/ic/qwxreg.h

2885

uint32_t band_center_freq1;

sys/dev/ic/qwxreg.h

2886

uint32_t band_center_freq2;

sys/dev/ic/qwxreg.h

2895

uint32_t min_power;

sys/dev/ic/qwxreg.h

2896

uint32_t max_power;

sys/dev/ic/qwxreg.h

2897

uint32_t max_reg_power;

sys/dev/ic/qwxreg.h

2898

uint32_t max_antenna_gain;

sys/dev/ic/qwxreg.h

2903

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

2905

uint32_t bcn_intval;

sys/dev/ic/qwxreg.h

2906

uint32_t dtim_period;

sys/dev/ic/qwxreg.h

2908

uint32_t ssid_len;

sys/dev/ic/qwxreg.h

2909

uint32_t bcn_tx_rate;

sys/dev/ic/qwxreg.h

2910

uint32_t bcn_tx_power;

sys/dev/ic/qwxreg.h

2914

uint32_t he_ops;

sys/dev/ic/qwxreg.h

2915

uint32_t cac_duration_ms;

sys/dev/ic/qwxreg.h

2916

uint32_t regdomain;

sys/dev/ic/qwxreg.h

2917

uint32_t pref_rx_streams;

sys/dev/ic/qwxreg.h

2918

uint32_t pref_tx_streams;

sys/dev/ic/qwxreg.h

2919

uint32_t num_noa_descriptors;

sys/dev/ic/qwxreg.h

2920

uint32_t min_data_rate;

sys/dev/ic/qwxreg.h

2921

uint32_t mbssid_flags;

sys/dev/ic/qwxreg.h

2922

uint32_t mbssid_tx_vdev_id;

sys/dev/ic/qwxreg.h

2927

uint32_t peer_type;

sys/dev/ic/qwxreg.h

2928

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

2936

uint32_t peer_tid_bitmap;

sys/dev/ic/qwxreg.h

2944

uint32_t ctl_2g;

sys/dev/ic/qwxreg.h

2945

uint32_t ctl_5g;

sys/dev/ic/qwxreg.h

2947

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

2953

uint32_t peer_tid_bitmap;

sys/dev/ic/qwxreg.h

3042

uint32_t param_id;

sys/dev/ic/qwxreg.h

3043

uint32_t param_value;

sys/dev/ic/qwxreg.h

3053

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3054

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3056

uint32_t peer_type;

sys/dev/ic/qwxreg.h

3060

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3061

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3066

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3067

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3069

uint32_t tid;

sys/dev/ic/qwxreg.h

3070

uint32_t queue_ptr_lo;

sys/dev/ic/qwxreg.h

3071

uint32_t queue_ptr_hi;

sys/dev/ic/qwxreg.h

3072

uint32_t queue_no;

sys/dev/ic/qwxreg.h

3073

uint32_t ba_window_size_valid;

sys/dev/ic/qwxreg.h

3074

uint32_t ba_window_size;

sys/dev/ic/qwxreg.h

3078

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3079

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3081

uint32_t tid_mask;

sys/dev/ic/qwxreg.h

3085

uint32_t gpio_num;

sys/dev/ic/qwxreg.h

3086

uint32_t input;

sys/dev/ic/qwxreg.h

3087

uint32_t pull_type;

sys/dev/ic/qwxreg.h

3088

uint32_t intr_mode;

sys/dev/ic/qwxreg.h

3112

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3113

uint32_t gpio_num;

sys/dev/ic/qwxreg.h

3114

uint32_t input;

sys/dev/ic/qwxreg.h

3115

uint32_t pull_type;

sys/dev/ic/qwxreg.h

3116

uint32_t intr_mode;

sys/dev/ic/qwxreg.h

3120

uint32_t gpio_num;

sys/dev/ic/qwxreg.h

3121

uint32_t set;

sys/dev/ic/qwxreg.h

3125

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3126

uint32_t gpio_num;

sys/dev/ic/qwxreg.h

3127

uint32_t set;

sys/dev/ic/qwxreg.h

3131

uint32_t arg;

sys/dev/ic/qwxreg.h

3132

uint32_t value;

sys/dev/ic/qwxreg.h

3136

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3137

uint32_t param_id;

sys/dev/ic/qwxreg.h

3138

uint32_t param_value;

sys/dev/ic/qwxreg.h

3142

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3143

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3144

uint32_t param_id;

sys/dev/ic/qwxreg.h

3145

uint32_t param_value;

sys/dev/ic/qwxreg.h

3149

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3150

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3151

uint32_t sta_ps_mode;

sys/dev/ic/qwxreg.h

3155

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3156

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3157

uint32_t suspend_opt;

sys/dev/ic/qwxreg.h

3161

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3162

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3166

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3168

uint32_t req_type;

sys/dev/ic/qwxreg.h

3169

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3173

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3174

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3176

uint32_t param;

sys/dev/ic/qwxreg.h

3177

uint32_t value;

sys/dev/ic/qwxreg.h

3181

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3182

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3183

uint32_t param;

sys/dev/ic/qwxreg.h

3184

uint32_t value;

sys/dev/ic/qwxreg.h

3188

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3189

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3190

uint32_t reg_domain;

sys/dev/ic/qwxreg.h

3191

uint32_t reg_domain_2g;

sys/dev/ic/qwxreg.h

3192

uint32_t reg_domain_5g;

sys/dev/ic/qwxreg.h

3193

uint32_t conformance_test_limit_2g;

sys/dev/ic/qwxreg.h

3194

uint32_t conformance_test_limit_5g;

sys/dev/ic/qwxreg.h

3195

uint32_t dfs_domain;

sys/dev/ic/qwxreg.h

3199

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3200

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3202

uint32_t param_id;

sys/dev/ic/qwxreg.h

3203

uint32_t param_value;

sys/dev/ic/qwxreg.h

3207

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3208

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3210

uint32_t peer_tid_bitmap;

sys/dev/ic/qwxreg.h

3214

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3215

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3219

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3220

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3221

uint32_t bcn_ctrl_op;

sys/dev/ic/qwxreg.h

3235

uint32_t len;

sys/dev/ic/qwxreg.h

3294

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3295

uint32_t scan_id;

sys/dev/ic/qwxreg.h

3296

uint32_t scan_req_id;

sys/dev/ic/qwxreg.h

3297

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3298

uint32_t scan_priority;

sys/dev/ic/qwxreg.h

3299

uint32_t notify_scan_events;

sys/dev/ic/qwxreg.h

3300

uint32_t dwell_time_active;

sys/dev/ic/qwxreg.h

3301

uint32_t dwell_time_passive;

sys/dev/ic/qwxreg.h

3302

uint32_t min_rest_time;

sys/dev/ic/qwxreg.h

3303

uint32_t max_rest_time;

sys/dev/ic/qwxreg.h

3304

uint32_t repeat_probe_time;

sys/dev/ic/qwxreg.h

3305

uint32_t probe_spacing_time;

sys/dev/ic/qwxreg.h

3306

uint32_t idle_time;

sys/dev/ic/qwxreg.h

3307

uint32_t max_scan_time;

sys/dev/ic/qwxreg.h

3308

uint32_t probe_delay;

sys/dev/ic/qwxreg.h

3309

uint32_t scan_ctrl_flags;

sys/dev/ic/qwxreg.h

3310

uint32_t burst_duration;

sys/dev/ic/qwxreg.h

3311

uint32_t num_chan;

sys/dev/ic/qwxreg.h

3312

uint32_t num_bssid;

sys/dev/ic/qwxreg.h

3313

uint32_t num_ssids;

sys/dev/ic/qwxreg.h

3314

uint32_t ie_len;

sys/dev/ic/qwxreg.h

3315

uint32_t n_probes;

sys/dev/ic/qwxreg.h

3318

uint32_t ie_bitmap[WMI_IE_BITMAP_SIZE];

sys/dev/ic/qwxreg.h

3319

uint32_t num_vendor_oui;

sys/dev/ic/qwxreg.h

3320

uint32_t scan_ctrl_flags_ext;

sys/dev/ic/qwxreg.h

3321

uint32_t dwell_time_active_2g;

sys/dev/ic/qwxreg.h

3322

uint32_t dwell_time_active_6g;

sys/dev/ic/qwxreg.h

3323

uint32_t dwell_time_passive_6g;

sys/dev/ic/qwxreg.h

3324

uint32_t scan_start_offset;

sys/dev/ic/qwxreg.h

3369

uint32_t freq_flags;

sys/dev/ic/qwxreg.h

3370

uint32_t short_ssid;

sys/dev/ic/qwxreg.h

3374

uint32_t freq_flags;

sys/dev/ic/qwxreg.h

3379

uint32_t scan_id;

sys/dev/ic/qwxreg.h

3380

uint32_t scan_req_id;

sys/dev/ic/qwxreg.h

3381

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3382

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3386

uint32_t scan_ev_started:1,

sys/dev/ic/qwxreg.h

3400

uint32_t scan_events;

sys/dev/ic/qwxreg.h

3402

uint32_t scan_ctrl_flags_ext;

sys/dev/ic/qwxreg.h

3403

uint32_t dwell_time_active;

sys/dev/ic/qwxreg.h

3404

uint32_t dwell_time_active_2g;

sys/dev/ic/qwxreg.h

3405

uint32_t dwell_time_passive;

sys/dev/ic/qwxreg.h

3406

uint32_t dwell_time_active_6g;

sys/dev/ic/qwxreg.h

3407

uint32_t dwell_time_passive_6g;

sys/dev/ic/qwxreg.h

3408

uint32_t min_rest_time;

sys/dev/ic/qwxreg.h

3409

uint32_t max_rest_time;

sys/dev/ic/qwxreg.h

3410

uint32_t repeat_probe_time;

sys/dev/ic/qwxreg.h

3411

uint32_t probe_spacing_time;

sys/dev/ic/qwxreg.h

3412

uint32_t idle_time;

sys/dev/ic/qwxreg.h

3413

uint32_t max_scan_time;

sys/dev/ic/qwxreg.h

3414

uint32_t probe_delay;

sys/dev/ic/qwxreg.h

3417

uint32_t scan_f_passive:1,

sys/dev/ic/qwxreg.h

3443

uint32_t scan_flags;

sys/dev/ic/qwxreg.h

3446

uint32_t burst_duration;

sys/dev/ic/qwxreg.h

3447

uint32_t num_chan;

sys/dev/ic/qwxreg.h

3448

uint32_t num_bssid;

sys/dev/ic/qwxreg.h

3449

uint32_t num_ssids;

sys/dev/ic/qwxreg.h

3450

uint32_t n_probes;

sys/dev/ic/qwxreg.h

3451

uint32_t *chan_list;

sys/dev/ic/qwxreg.h

3452

uint32_t notify_scan_events;

sys/dev/ic/qwxreg.h

3458

uint32_t num_hint_s_ssid;

sys/dev/ic/qwxreg.h

3459

uint32_t num_hint_bssid;

sys/dev/ic/qwxreg.h

3476

uint32_t scan_id;

sys/dev/ic/qwxreg.h

3477

uint32_t scan_req_id;

sys/dev/ic/qwxreg.h

3478

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3479

uint32_t scan_priority;

sys/dev/ic/qwxreg.h

3480

uint32_t notify_scan_events;

sys/dev/ic/qwxreg.h

3481

uint32_t dwell_time_active;

sys/dev/ic/qwxreg.h

3482

uint32_t dwell_time_passive;

sys/dev/ic/qwxreg.h

3483

uint32_t min_rest_time;

sys/dev/ic/qwxreg.h

3484

uint32_t max_rest_time;

sys/dev/ic/qwxreg.h

3485

uint32_t repeat_probe_time;

sys/dev/ic/qwxreg.h

3486

uint32_t probe_spacing_time;

sys/dev/ic/qwxreg.h

3487

uint32_t idle_time;

sys/dev/ic/qwxreg.h

3488

uint32_t max_scan_time;

sys/dev/ic/qwxreg.h

3489

uint32_t probe_delay;

sys/dev/ic/qwxreg.h

3490

uint32_t scan_ctrl_flags;

sys/dev/ic/qwxreg.h

3492

uint32_t ie_len;

sys/dev/ic/qwxreg.h

3493

uint32_t n_channels;

sys/dev/ic/qwxreg.h

3494

uint32_t n_ssids;

sys/dev/ic/qwxreg.h

3495

uint32_t n_bssids;

sys/dev/ic/qwxreg.h

3498

uint32_t channels[64];

sys/dev/ic/qwxreg.h

3519

uint32_t requester;

sys/dev/ic/qwxreg.h

3520

uint32_t scan_id;

sys/dev/ic/qwxreg.h

3522

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3523

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3527

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3528

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3529

uint32_t data_len;

sys/dev/ic/qwxreg.h

3531

uint32_t frag_ptr;

sys/dev/ic/qwxreg.h

3532

uint32_t frag_ptr_lo;

sys/dev/ic/qwxreg.h

3534

uint32_t frame_ctrl;

sys/dev/ic/qwxreg.h

3535

uint32_t dtim_flag;

sys/dev/ic/qwxreg.h

3536

uint32_t bcn_antenna;

sys/dev/ic/qwxreg.h

3537

uint32_t frag_ptr_hi;

sys/dev/ic/qwxreg.h

3564

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3565

uint32_t mhz;

sys/dev/ic/qwxreg.h

3566

uint32_t band_center_freq1;

sys/dev/ic/qwxreg.h

3567

uint32_t band_center_freq2;

sys/dev/ic/qwxreg.h

3568

uint32_t info;

sys/dev/ic/qwxreg.h

3569

uint32_t reg_info_1;

sys/dev/ic/qwxreg.h

3570

uint32_t reg_info_2;

sys/dev/ic/qwxreg.h

3600

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3601

uint32_t type;

sys/dev/ic/qwxreg.h

3602

uint32_t delay_time_ms;

sys/dev/ic/qwxreg.h

3606

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3607

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3608

uint32_t param_id;

sys/dev/ic/qwxreg.h

3609

uint32_t param_value;

sys/dev/ic/qwxreg.h

3630

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3632

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3634

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3638

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3639

uint32_t param;

sys/dev/ic/qwxreg.h

3640

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3644

uint32_t len;

sys/dev/ic/qwxreg.h

3645

uint32_t msgref;

sys/dev/ic/qwxreg.h

3646

uint32_t segmentinfo;

sys/dev/ic/qwxreg.h

3647

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3651

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3668

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3669

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3670

uint32_t tim_ie_offset;

sys/dev/ic/qwxreg.h

3671

uint32_t buf_len;

sys/dev/ic/qwxreg.h

3672

uint32_t csa_switch_count_offset;

sys/dev/ic/qwxreg.h

3673

uint32_t ext_csa_switch_count_offset;

sys/dev/ic/qwxreg.h

3674

uint32_t csa_event_bitmap;

sys/dev/ic/qwxreg.h

3675

uint32_t mbssid_ie_offset;

sys/dev/ic/qwxreg.h

3676

uint32_t esp_ie_offset;

sys/dev/ic/qwxreg.h

3677

uint32_t csc_switch_count_offset;

sys/dev/ic/qwxreg.h

3678

uint32_t csc_event_bitmap;

sys/dev/ic/qwxreg.h

3679

uint32_t mu_edca_ie_offset;

sys/dev/ic/qwxreg.h

3680

uint32_t feature_enable_bitmap;

sys/dev/ic/qwxreg.h

3681

uint32_t ema_params;

sys/dev/ic/qwxreg.h

3685

uint32_t key_seq_counter_l;

sys/dev/ic/qwxreg.h

3686

uint32_t key_seq_counter_h;

sys/dev/ic/qwxreg.h

3690

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3691

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3693

uint32_t key_idx;

sys/dev/ic/qwxreg.h

3694

uint32_t key_flags;

sys/dev/ic/qwxreg.h

3695

uint32_t key_cipher;

sys/dev/ic/qwxreg.h

3701

uint32_t key_len;

sys/dev/ic/qwxreg.h

3702

uint32_t key_txmic_len;

sys/dev/ic/qwxreg.h

3703

uint32_t key_rxmic_len;

sys/dev/ic/qwxreg.h

3704

uint32_t is_group_key_id_valid;

sys/dev/ic/qwxreg.h

3705

uint32_t group_key_id;

sys/dev/ic/qwxreg.h

3713

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3715

uint32_t key_idx;

sys/dev/ic/qwxreg.h

3716

uint32_t key_flags;

sys/dev/ic/qwxreg.h

3717

uint32_t key_cipher;

sys/dev/ic/qwxreg.h

3718

uint32_t key_len;

sys/dev/ic/qwxreg.h

3719

uint32_t key_txmic_len;

sys/dev/ic/qwxreg.h

3720

uint32_t key_rxmic_len;

sys/dev/ic/qwxreg.h

3733

uint32_t num_rates;

sys/dev/ic/qwxreg.h

3739

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3740

uint32_t peer_new_assoc;

sys/dev/ic/qwxreg.h

3741

uint32_t peer_associd;

sys/dev/ic/qwxreg.h

3742

uint32_t peer_flags;

sys/dev/ic/qwxreg.h

3743

uint32_t peer_caps;

sys/dev/ic/qwxreg.h

3744

uint32_t peer_listen_intval;

sys/dev/ic/qwxreg.h

3745

uint32_t peer_ht_caps;

sys/dev/ic/qwxreg.h

3746

uint32_t peer_max_mpdu;

sys/dev/ic/qwxreg.h

3747

uint32_t peer_mpdu_density;

sys/dev/ic/qwxreg.h

3748

uint32_t peer_rate_caps;

sys/dev/ic/qwxreg.h

3749

uint32_t peer_nss;

sys/dev/ic/qwxreg.h

3750

uint32_t peer_vht_caps;

sys/dev/ic/qwxreg.h

3751

uint32_t peer_phymode;

sys/dev/ic/qwxreg.h

3752

uint32_t peer_ht_info[2];

sys/dev/ic/qwxreg.h

3755

uint32_t rx_max_rate;

sys/dev/ic/qwxreg.h

3756

uint32_t rx_mcs_set;

sys/dev/ic/qwxreg.h

3757

uint32_t tx_max_rate;

sys/dev/ic/qwxreg.h

3758

uint32_t tx_mcs_set;

sys/dev/ic/qwxreg.h

3761

uint32_t tx_max_mcs_nss;

sys/dev/ic/qwxreg.h

3762

uint32_t peer_bw_rxnss_override;

sys/dev/ic/qwxreg.h

3787

uint32_t peer_he_cap_macinfo[2];

sys/dev/ic/qwxreg.h

3788

uint32_t peer_he_cap_macinfo_internal;

sys/dev/ic/qwxreg.h

3789

uint32_t peer_he_caps_6ghz;

sys/dev/ic/qwxreg.h

3790

uint32_t peer_he_ops;

sys/dev/ic/qwxreg.h

3791

uint32_t peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE];

sys/dev/ic/qwxreg.h

3792

uint32_t peer_he_mcs_count;

sys/dev/ic/qwxreg.h

3793

uint32_t peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];

sys/dev/ic/qwxreg.h

3794

uint32_t peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];

sys/dev/ic/qwxreg.h

3802

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3804

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3805

uint32_t peer_new_assoc;

sys/dev/ic/qwxreg.h

3806

uint32_t peer_associd;

sys/dev/ic/qwxreg.h

3807

uint32_t peer_flags;

sys/dev/ic/qwxreg.h

3808

uint32_t peer_caps;

sys/dev/ic/qwxreg.h

3809

uint32_t peer_listen_intval;

sys/dev/ic/qwxreg.h

3810

uint32_t peer_ht_caps;

sys/dev/ic/qwxreg.h

3811

uint32_t peer_max_mpdu;

sys/dev/ic/qwxreg.h

3812

uint32_t peer_mpdu_density;

sys/dev/ic/qwxreg.h

3813

uint32_t peer_rate_caps;

sys/dev/ic/qwxreg.h

3814

uint32_t peer_nss;

sys/dev/ic/qwxreg.h

3815

uint32_t peer_vht_caps;

sys/dev/ic/qwxreg.h

3816

uint32_t peer_phymode;

sys/dev/ic/qwxreg.h

3817

uint32_t peer_ht_info[2];

sys/dev/ic/qwxreg.h

3818

uint32_t num_peer_legacy_rates;

sys/dev/ic/qwxreg.h

3819

uint32_t num_peer_ht_rates;

sys/dev/ic/qwxreg.h

3820

uint32_t peer_bw_rxnss_override;

sys/dev/ic/qwxreg.h

3822

uint32_t peer_he_cap_info;

sys/dev/ic/qwxreg.h

3823

uint32_t peer_he_ops;

sys/dev/ic/qwxreg.h

3824

uint32_t peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE];

sys/dev/ic/qwxreg.h

3825

uint32_t peer_he_mcs;

sys/dev/ic/qwxreg.h

3826

uint32_t peer_he_cap_info_ext;

sys/dev/ic/qwxreg.h

3827

uint32_t peer_he_cap_info_internal;

sys/dev/ic/qwxreg.h

3828

uint32_t min_data_rate;

sys/dev/ic/qwxreg.h

3829

uint32_t peer_he_caps_6ghz;

sys/dev/ic/qwxreg.h

3833

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3834

uint32_t requestor;

sys/dev/ic/qwxreg.h

3835

uint32_t scan_id;

sys/dev/ic/qwxreg.h

3836

uint32_t req_type;

sys/dev/ic/qwxreg.h

3837

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3838

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3842

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3848

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3849

uint32_t num_scan_chans;

sys/dev/ic/qwxreg.h

3850

uint32_t flags;

sys/dev/ic/qwxreg.h

3851

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3855

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3856

uint32_t prob_req_oui;

sys/dev/ic/qwxreg.h

3873

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3874

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3875

uint32_t desc_id;

sys/dev/ic/qwxreg.h

3876

uint32_t chanfreq;

sys/dev/ic/qwxreg.h

3877

uint32_t paddr_lo;

sys/dev/ic/qwxreg.h

3878

uint32_t paddr_hi;

sys/dev/ic/qwxreg.h

3879

uint32_t frame_len;

sys/dev/ic/qwxreg.h

3880

uint32_t buf_len;

sys/dev/ic/qwxreg.h

3881

uint32_t tx_params_valid;

sys/dev/ic/qwxreg.h

3893

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3894

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3895

uint32_t sta_ps_mode;

sys/dev/ic/qwxreg.h

3899

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3900

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3901

uint32_t forced_mode;

sys/dev/ic/qwxreg.h

3905

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3906

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3907

uint32_t param;

sys/dev/ic/qwxreg.h

3908

uint32_t value;

sys/dev/ic/qwxreg.h

3912

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3913

uint32_t caps;

sys/dev/ic/qwxreg.h

3914

uint32_t erp;

sys/dev/ic/qwxreg.h

3923

uint32_t value;

sys/dev/ic/qwxreg.h

3927

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3928

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3929

uint32_t enable;

sys/dev/ic/qwxreg.h

3933

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3934

uint32_t param;

sys/dev/ic/qwxreg.h

3935

uint32_t value;

sys/dev/ic/qwxreg.h

3939

uint32_t if_id;

sys/dev/ic/qwxreg.h

3940

uint32_t param_id;

sys/dev/ic/qwxreg.h

3941

uint32_t param_value;

sys/dev/ic/qwxreg.h

3945

uint32_t stats_id;

sys/dev/ic/qwxreg.h

3946

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3947

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3955

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3956

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3957

uint32_t new_alpha2;

sys/dev/ic/qwxreg.h

3983

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

3984

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

3985

uint32_t init_cc_type;

sys/dev/ic/qwxreg.h

3987

uint32_t country_code;

sys/dev/ic/qwxreg.h

3988

uint32_t regdom_id;

sys/dev/ic/qwxreg.h

3989

uint32_t alpha2;

sys/dev/ic/qwxreg.h

3994

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

3995

uint32_t scan_period_msec;

sys/dev/ic/qwxreg.h

3996

uint32_t start_interval_msec;

sys/dev/ic/qwxreg.h

4000

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4001

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4002

uint32_t scan_period_msec;

sys/dev/ic/qwxreg.h

4003

uint32_t start_interval_msec;

sys/dev/ic/qwxreg.h

4007

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4008

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4012

uint32_t new_alpha2;

sys/dev/ic/qwxreg.h

4017

uint32_t tmplwm;

sys/dev/ic/qwxreg.h

4018

uint32_t tmphwm;

sys/dev/ic/qwxreg.h

4019

uint32_t dcoffpercent;

sys/dev/ic/qwxreg.h

4020

uint32_t priority;

sys/dev/ic/qwxreg.h

4024

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

4025

uint32_t enable;

sys/dev/ic/qwxreg.h

4026

uint32_t dc;

sys/dev/ic/qwxreg.h

4027

uint32_t dc_per_event;

sys/dev/ic/qwxreg.h

4032

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4033

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

4034

uint32_t enable;

sys/dev/ic/qwxreg.h

4035

uint32_t dc;

sys/dev/ic/qwxreg.h

4036

uint32_t dc_per_event;

sys/dev/ic/qwxreg.h

4037

uint32_t therm_throt_levels;

sys/dev/ic/qwxreg.h

4041

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4042

uint32_t temp_lwm;

sys/dev/ic/qwxreg.h

4043

uint32_t temp_hwm;

sys/dev/ic/qwxreg.h

4044

uint32_t dc_off_percent;

sys/dev/ic/qwxreg.h

4045

uint32_t prio;

sys/dev/ic/qwxreg.h

4049

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4050

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4052

uint32_t tid;

sys/dev/ic/qwxreg.h

4053

uint32_t initiator;

sys/dev/ic/qwxreg.h

4054

uint32_t reasoncode;

sys/dev/ic/qwxreg.h

4058

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4059

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4061

uint32_t tid;

sys/dev/ic/qwxreg.h

4062

uint32_t statuscode;

sys/dev/ic/qwxreg.h

4066

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4067

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4069

uint32_t tid;

sys/dev/ic/qwxreg.h

4070

uint32_t buffersize;

sys/dev/ic/qwxreg.h

4074

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4075

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4080

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4085

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4086

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

4087

uint32_t enable;

sys/dev/ic/qwxreg.h

4088

uint32_t filter_type;

sys/dev/ic/qwxreg.h

4089

uint32_t num_mac;

sys/dev/ic/qwxreg.h

4098

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4099

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

4100

uint32_t evlist; /* WMI_PKTLOG_EVENT */

sys/dev/ic/qwxreg.h

4101

uint32_t enable;

sys/dev/ic/qwxreg.h

4105

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4106

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

4121

uint32_t cmd_id;

sys/dev/ic/qwxreg.h

4122

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

4123

uint32_t radar_param;

sys/dev/ic/qwxreg.h

4127

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4128

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4129

uint32_t module_id;

sys/dev/ic/qwxreg.h

4130

uint32_t num_args;

sys/dev/ic/qwxreg.h

4131

uint32_t diag_token;

sys/dev/ic/qwxreg.h

4164

uint32_t tim_ie_offset;

sys/dev/ic/qwxreg.h

4165

uint32_t tmpl_len;

sys/dev/ic/qwxreg.h

4166

uint32_t tmpl_len_aligned;

sys/dev/ic/qwxreg.h

4167

uint32_t csa_switch_count_offset;

sys/dev/ic/qwxreg.h

4168

uint32_t ext_csa_switch_count_offset;

sys/dev/ic/qwxreg.h

4173

uint32_t num_rates;

sys/dev/ic/qwxreg.h

4174

uint32_t rates[(MAX_SUPPORTED_RATES / 4) + 1];

sys/dev/ic/qwxreg.h

4178

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4179

uint32_t rx_max_rate;

sys/dev/ic/qwxreg.h

4180

uint32_t rx_mcs_set;

sys/dev/ic/qwxreg.h

4181

uint32_t tx_max_rate;

sys/dev/ic/qwxreg.h

4182

uint32_t tx_mcs_set;

sys/dev/ic/qwxreg.h

4183

uint32_t tx_max_mcs_nss;

sys/dev/ic/qwxreg.h

4187

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4190

uint32_t rx_mcs_set;

sys/dev/ic/qwxreg.h

4193

uint32_t tx_mcs_set;

sys/dev/ic/qwxreg.h

4206

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4207

uint32_t requestor_id;

sys/dev/ic/qwxreg.h

4209

uint32_t status;

sys/dev/ic/qwxreg.h

4210

uint32_t chain_mask;

sys/dev/ic/qwxreg.h

4211

uint32_t smps_mode;

sys/dev/ic/qwxreg.h

4213

uint32_t mac_id;

sys/dev/ic/qwxreg.h

4214

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

4216

uint32_t cfgd_tx_streams;

sys/dev/ic/qwxreg.h

4217

uint32_t cfgd_rx_streams;

sys/dev/ic/qwxreg.h

4471

uint32_t dfs_region;

sys/dev/ic/qwxreg.h

4472

uint32_t phybitmap;

sys/dev/ic/qwxreg.h

4473

uint32_t min_bw_2ghz;

sys/dev/ic/qwxreg.h

4474

uint32_t max_bw_2ghz;

sys/dev/ic/qwxreg.h

4475

uint32_t min_bw_5ghz;

sys/dev/ic/qwxreg.h

4476

uint32_t max_bw_5ghz;

sys/dev/ic/qwxreg.h

4477

uint32_t num_2ghz_reg_rules;

sys/dev/ic/qwxreg.h

4478

uint32_t num_5ghz_reg_rules;

sys/dev/ic/qwxreg.h

4487

uint32_t domain_code_6ghz_super_id;

sys/dev/ic/qwxreg.h

4488

uint32_t min_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];

sys/dev/ic/qwxreg.h

4489

uint32_t max_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];

sys/dev/ic/qwxreg.h

4490

uint32_t min_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];

sys/dev/ic/qwxreg.h

4491

uint32_t max_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];

sys/dev/ic/qwxreg.h

4492

uint32_t num_6ghz_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE];

sys/dev/ic/qwxreg.h

4493

uint32_t num_6ghz_rules_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];

sys/dev/ic/qwxreg.h

4500

uint32_t status_code;

sys/dev/ic/qwxreg.h

4501

uint32_t phy_id;

sys/dev/ic/qwxreg.h

4502

uint32_t alpha2;

sys/dev/ic/qwxreg.h

4503

uint32_t num_phy;

sys/dev/ic/qwxreg.h

4504

uint32_t country_id;

sys/dev/ic/qwxreg.h

4505

uint32_t domain_code;

sys/dev/ic/qwxreg.h

4506

uint32_t dfs_region;

sys/dev/ic/qwxreg.h

4507

uint32_t phybitmap;

sys/dev/ic/qwxreg.h

4508

uint32_t min_bw_2ghz;

sys/dev/ic/qwxreg.h

4509

uint32_t max_bw_2ghz;

sys/dev/ic/qwxreg.h

4510

uint32_t min_bw_5ghz;

sys/dev/ic/qwxreg.h

4511

uint32_t max_bw_5ghz;

sys/dev/ic/qwxreg.h

4512

uint32_t num_2ghz_reg_rules;

sys/dev/ic/qwxreg.h

4513

uint32_t num_5ghz_reg_rules;

sys/dev/ic/qwxreg.h

4517

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4518

uint32_t freq_info;

sys/dev/ic/qwxreg.h

4519

uint32_t bw_pwr_info;

sys/dev/ic/qwxreg.h

4520

uint32_t flag_info;

sys/dev/ic/qwxreg.h

4526

uint32_t status_code;

sys/dev/ic/qwxreg.h

4527

uint32_t phy_id;

sys/dev/ic/qwxreg.h

4528

uint32_t alpha2;

sys/dev/ic/qwxreg.h

4529

uint32_t num_phy;

sys/dev/ic/qwxreg.h

4530

uint32_t country_id;

sys/dev/ic/qwxreg.h

4531

uint32_t domain_code;

sys/dev/ic/qwxreg.h

4532

uint32_t dfs_region;

sys/dev/ic/qwxreg.h

4533

uint32_t phybitmap;

sys/dev/ic/qwxreg.h

4534

uint32_t min_bw_2ghz;

sys/dev/ic/qwxreg.h

4535

uint32_t max_bw_2ghz;

sys/dev/ic/qwxreg.h

4536

uint32_t min_bw_5ghz;

sys/dev/ic/qwxreg.h

4537

uint32_t max_bw_5ghz;

sys/dev/ic/qwxreg.h

4538

uint32_t num_2ghz_reg_rules;

sys/dev/ic/qwxreg.h

4539

uint32_t num_5ghz_reg_rules;

sys/dev/ic/qwxreg.h

4540

uint32_t client_type;

sys/dev/ic/qwxreg.h

4541

uint32_t rnr_tpe_usable;

sys/dev/ic/qwxreg.h

4542

uint32_t unspecified_ap_usable;

sys/dev/ic/qwxreg.h

4543

uint32_t domain_code_6ghz_ap_lpi;

sys/dev/ic/qwxreg.h

4544

uint32_t domain_code_6ghz_ap_sp;

sys/dev/ic/qwxreg.h

4545

uint32_t domain_code_6ghz_ap_vlp;

sys/dev/ic/qwxreg.h

4546

uint32_t domain_code_6ghz_client_lpi[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwxreg.h

4547

uint32_t domain_code_6ghz_client_sp[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwxreg.h

4548

uint32_t domain_code_6ghz_client_vlp[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwxreg.h

4549

uint32_t domain_code_6ghz_super_id;

sys/dev/ic/qwxreg.h

4550

uint32_t min_bw_6ghz_ap_sp;

sys/dev/ic/qwxreg.h

4551

uint32_t max_bw_6ghz_ap_sp;

sys/dev/ic/qwxreg.h

4552

uint32_t min_bw_6ghz_ap_lpi;

sys/dev/ic/qwxreg.h

4553

uint32_t max_bw_6ghz_ap_lpi;

sys/dev/ic/qwxreg.h

4554

uint32_t min_bw_6ghz_ap_vlp;

sys/dev/ic/qwxreg.h

4555

uint32_t max_bw_6ghz_ap_vlp;

sys/dev/ic/qwxreg.h

4556

uint32_t min_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwxreg.h

4557

uint32_t max_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwxreg.h

4558

uint32_t min_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwxreg.h

4559

uint32_t max_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwxreg.h

4560

uint32_t min_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwxreg.h

4561

uint32_t max_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwxreg.h

4562

uint32_t num_6ghz_reg_rules_ap_sp;

sys/dev/ic/qwxreg.h

4563

uint32_t num_6ghz_reg_rules_ap_lpi;

sys/dev/ic/qwxreg.h

4564

uint32_t num_6ghz_reg_rules_ap_vlp;

sys/dev/ic/qwxreg.h

4565

uint32_t num_6ghz_reg_rules_client_sp[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwxreg.h

4566

uint32_t num_6ghz_reg_rules_client_lpi[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwxreg.h

4567

uint32_t num_6ghz_reg_rules_client_vlp[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwxreg.h

4571

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4572

uint32_t freq_info;

sys/dev/ic/qwxreg.h

4573

uint32_t bw_pwr_info;

sys/dev/ic/qwxreg.h

4574

uint32_t flag_info;

sys/dev/ic/qwxreg.h

4575

uint32_t psd_power_info;

sys/dev/ic/qwxreg.h

4579

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4583

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4588

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4589

uint32_t tx_status;

sys/dev/ic/qwxreg.h

4593

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4597

uint32_t freq; /* Units in MHz */

sys/dev/ic/qwxreg.h

4598

uint32_t noise_floor; /* units are dBm */

sys/dev/ic/qwxreg.h

4600

uint32_t rx_clear_count_low;

sys/dev/ic/qwxreg.h

4601

uint32_t rx_clear_count_high;

sys/dev/ic/qwxreg.h

4603

uint32_t cycle_count_low;

sys/dev/ic/qwxreg.h

4604

uint32_t cycle_count_high;

sys/dev/ic/qwxreg.h

4606

uint32_t tx_cycle_count_low;

sys/dev/ic/qwxreg.h

4607

uint32_t tx_cycle_count_high;

sys/dev/ic/qwxreg.h

4609

uint32_t rx_cycle_count_low;

sys/dev/ic/qwxreg.h

4610

uint32_t rx_cycle_count_high;

sys/dev/ic/qwxreg.h

4612

uint32_t rx_bss_cycle_count_low;

sys/dev/ic/qwxreg.h

4613

uint32_t rx_bss_cycle_count_high;

sys/dev/ic/qwxreg.h

4614

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

4620

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4622

uint32_t key_idx;

sys/dev/ic/qwxreg.h

4623

uint32_t key_flags;

sys/dev/ic/qwxreg.h

4624

uint32_t status;

sys/dev/ic/qwxreg.h

4628

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4630

uint32_t key_idx;

sys/dev/ic/qwxreg.h

4631

uint32_t key_flags;

sys/dev/ic/qwxreg.h

4632

uint32_t status;

sys/dev/ic/qwxreg.h

4636

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4641

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4646

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4647

uint32_t fils_tt;

sys/dev/ic/qwxreg.h

4648

uint32_t tbtt;

sys/dev/ic/qwxreg.h

4652

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4653

uint32_t tx_status;

sys/dev/ic/qwxreg.h

4661

uint32_t tx_frame_count; /* Cycles spent transmitting frames */

sys/dev/ic/qwxreg.h

4662

uint32_t rx_frame_count; /* Cycles spent receiving frames */

sys/dev/ic/qwxreg.h

4663

uint32_t rx_clear_count; /* Total channel busy time, evidently */

sys/dev/ic/qwxreg.h

4664

uint32_t cycle_count; /* Total on-channel time */

sys/dev/ic/qwxreg.h

4665

uint32_t phy_err_count;

sys/dev/ic/qwxreg.h

4666

uint32_t chan_tx_pwr;

sys/dev/ic/qwxreg.h

4670

uint32_t ack_rx_bad;

sys/dev/ic/qwxreg.h

4671

uint32_t rts_bad;

sys/dev/ic/qwxreg.h

4672

uint32_t rts_good;

sys/dev/ic/qwxreg.h

4673

uint32_t fcs_bad;

sys/dev/ic/qwxreg.h

4674

uint32_t no_beacons;

sys/dev/ic/qwxreg.h

4675

uint32_t mib_int_count;

sys/dev/ic/qwxreg.h

4710

uint32_t hw_paused;

sys/dev/ic/qwxreg.h

4719

uint32_t tx_ko;

sys/dev/ic/qwxreg.h

4721

uint32_t tx_xretry;

sys/dev/ic/qwxreg.h

4724

uint32_t data_rc;

sys/dev/ic/qwxreg.h

4727

uint32_t self_triggers;

sys/dev/ic/qwxreg.h

4730

uint32_t sw_retry_failure;

sys/dev/ic/qwxreg.h

4733

uint32_t illgl_rate_phy_err;

sys/dev/ic/qwxreg.h

4736

uint32_t pdev_cont_xretry;

sys/dev/ic/qwxreg.h

4739

uint32_t pdev_tx_timeout;

sys/dev/ic/qwxreg.h

4742

uint32_t pdev_resets;

sys/dev/ic/qwxreg.h

4745

uint32_t stateless_tid_alloc_failure;

sys/dev/ic/qwxreg.h

4748

uint32_t phy_underrun;

sys/dev/ic/qwxreg.h

4751

uint32_t txop_ovf;

sys/dev/ic/qwxreg.h

4754

uint32_t seq_posted;

sys/dev/ic/qwxreg.h

4757

uint32_t seq_failed_queueing;

sys/dev/ic/qwxreg.h

4760

uint32_t seq_completed;

sys/dev/ic/qwxreg.h

4763

uint32_t seq_restarted;

sys/dev/ic/qwxreg.h

4766

uint32_t mu_seq_posted;

sys/dev/ic/qwxreg.h

4836

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4837

uint32_t beacon_snr;

sys/dev/ic/qwxreg.h

4838

uint32_t data_snr;

sys/dev/ic/qwxreg.h

4839

uint32_t num_tx_frames[WLAN_MAX_AC];

sys/dev/ic/qwxreg.h

4840

uint32_t num_rx_frames;

sys/dev/ic/qwxreg.h

4841

uint32_t num_tx_frames_retries[WLAN_MAX_AC];

sys/dev/ic/qwxreg.h

4842

uint32_t num_tx_frames_failures[WLAN_MAX_AC];

sys/dev/ic/qwxreg.h

4843

uint32_t num_rts_fail;

sys/dev/ic/qwxreg.h

4844

uint32_t num_rts_success;

sys/dev/ic/qwxreg.h

4845

uint32_t num_rx_err;

sys/dev/ic/qwxreg.h

4846

uint32_t num_rx_discard;

sys/dev/ic/qwxreg.h

4847

uint32_t num_tx_not_acked;

sys/dev/ic/qwxreg.h

4848

uint32_t tx_rate_history[MAX_TX_RATE_VALUES];

sys/dev/ic/qwxreg.h

4849

uint32_t beacon_rssi_history[MAX_TX_RATE_VALUES];

sys/dev/ic/qwxreg.h

4853

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4854

uint32_t tx_bcn_succ_cnt;

sys/dev/ic/qwxreg.h

4855

uint32_t tx_bcn_outage_cnt;

sys/dev/ic/qwxreg.h

4859

uint32_t stats_id;

sys/dev/ic/qwxreg.h

4860

uint32_t num_pdev_stats;

sys/dev/ic/qwxreg.h

4861

uint32_t num_vdev_stats;

sys/dev/ic/qwxreg.h

4862

uint32_t num_peer_stats;

sys/dev/ic/qwxreg.h

4863

uint32_t num_bcnflt_stats;

sys/dev/ic/qwxreg.h

4864

uint32_t num_chan_stats;

sys/dev/ic/qwxreg.h

4865

uint32_t num_mib_stats;

sys/dev/ic/qwxreg.h

4866

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

4867

uint32_t num_bcn_stats;

sys/dev/ic/qwxreg.h

4868

uint32_t num_peer_extd_stats;

sys/dev/ic/qwxreg.h

4869

uint32_t num_peer_extd2_stats;

sys/dev/ic/qwxreg.h

4873

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4874

uint32_t rssi_avg_beacon[WMI_MAX_CHAINS];

sys/dev/ic/qwxreg.h

4875

uint32_t rssi_avg_data[WMI_MAX_CHAINS];

sys/dev/ic/qwxreg.h

4880

uint32_t num_per_chain_rssi_stats;

sys/dev/ic/qwxreg.h

4884

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

4885

uint32_t ctl_failsafe_status;

sys/dev/ic/qwxreg.h

4889

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

4890

uint32_t current_switch_count;

sys/dev/ic/qwxreg.h

4891

uint32_t num_vdevs;

sys/dev/ic/qwxreg.h

4895

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

4896

uint32_t detection_mode;

sys/dev/ic/qwxreg.h

4897

uint32_t chan_freq;

sys/dev/ic/qwxreg.h

4898

uint32_t chan_width;

sys/dev/ic/qwxreg.h

4899

uint32_t detector_id;

sys/dev/ic/qwxreg.h

4900

uint32_t segment_id;

sys/dev/ic/qwxreg.h

4901

uint32_t timestamp;

sys/dev/ic/qwxreg.h

4902

uint32_t is_chirp;

sys/dev/ic/qwxreg.h

4910

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

4922

uint32_t chan_freq;

sys/dev/ic/qwxreg.h

4923

uint32_t channel;

sys/dev/ic/qwxreg.h

4924

uint32_t snr;

sys/dev/ic/qwxreg.h

4926

uint32_t rate;

sys/dev/ic/qwxreg.h

4928

uint32_t buf_len;

sys/dev/ic/qwxreg.h

4930

uint32_t flags;

sys/dev/ic/qwxreg.h

4932

uint32_t tsf_delta;

sys/dev/ic/qwxreg.h

4939

uint32_t channel;

sys/dev/ic/qwxreg.h

4940

uint32_t snr;

sys/dev/ic/qwxreg.h

4941

uint32_t rate;

sys/dev/ic/qwxreg.h

4942

uint32_t phy_mode;

sys/dev/ic/qwxreg.h

4943

uint32_t buf_len;

sys/dev/ic/qwxreg.h

4944

uint32_t status;

sys/dev/ic/qwxreg.h

4945

uint32_t rssi_ctl[ATH_MAX_ANTENNA];

sys/dev/ic/qwxreg.h

4946

uint32_t flags;

sys/dev/ic/qwxreg.h

4948

uint32_t tsf_delta;

sys/dev/ic/qwxreg.h

4949

uint32_t rx_tsf_l32;

sys/dev/ic/qwxreg.h

4950

uint32_t rx_tsf_u32;

sys/dev/ic/qwxreg.h

4951

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

4952

uint32_t chan_freq;

sys/dev/ic/qwxreg.h

4958

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

4959

uint32_t rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA];

sys/dev/ic/qwxreg.h

4963

uint32_t desc_id;

sys/dev/ic/qwxreg.h

4964

uint32_t status;

sys/dev/ic/qwxreg.h

4965

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

4966

uint32_t ppdu_id;

sys/dev/ic/qwxreg.h

4967

uint32_t ack_rssi;

sys/dev/ic/qwxreg.h

4971

uint32_t event_type; /* %WMI_SCAN_EVENT_ */

sys/dev/ic/qwxreg.h

4972

uint32_t reason; /* %WMI_SCAN_REASON_ */

sys/dev/ic/qwxreg.h

4973

uint32_t channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */

sys/dev/ic/qwxreg.h

4974

uint32_t scan_req_id;

sys/dev/ic/qwxreg.h

4975

uint32_t scan_id;

sys/dev/ic/qwxreg.h

4976

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

4982

uint32_t tsf_timestamp;

sys/dev/ic/qwxreg.h

5005

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5006

uint32_t reason;

sys/dev/ic/qwxreg.h

5007

uint32_t rssi;

sys/dev/ic/qwxreg.h

5014

uint32_t err_code;

sys/dev/ic/qwxreg.h

5015

uint32_t freq;

sys/dev/ic/qwxreg.h

5016

uint32_t cmd_flags;

sys/dev/ic/qwxreg.h

5017

uint32_t noise_floor;

sys/dev/ic/qwxreg.h

5018

uint32_t rx_clear_count;

sys/dev/ic/qwxreg.h

5019

uint32_t cycle_count;

sys/dev/ic/qwxreg.h

5020

uint32_t chan_tx_pwr_range;

sys/dev/ic/qwxreg.h

5021

uint32_t chan_tx_pwr_tp;

sys/dev/ic/qwxreg.h

5022

uint32_t rx_frame_count;

sys/dev/ic/qwxreg.h

5023

uint32_t my_bss_rx_cycle_count;

sys/dev/ic/qwxreg.h

5024

uint32_t rx_11b_mode_data_duration;

sys/dev/ic/qwxreg.h

5025

uint32_t tx_frame_cnt;

sys/dev/ic/qwxreg.h

5026

uint32_t mac_clk_mhz;

sys/dev/ic/qwxreg.h

5027

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5031

uint32_t phy_capability;

sys/dev/ic/qwxreg.h

5032

uint32_t max_frag_entry;

sys/dev/ic/qwxreg.h

5033

uint32_t num_rf_chains;

sys/dev/ic/qwxreg.h

5034

uint32_t ht_cap_info;

sys/dev/ic/qwxreg.h

5035

uint32_t vht_cap_info;

sys/dev/ic/qwxreg.h

5036

uint32_t vht_supp_mcs;

sys/dev/ic/qwxreg.h

5037

uint32_t hw_min_tx_power;

sys/dev/ic/qwxreg.h

5038

uint32_t hw_max_tx_power;

sys/dev/ic/qwxreg.h

5039

uint32_t sys_cap_info;

sys/dev/ic/qwxreg.h

5040

uint32_t min_pkt_size_enable;

sys/dev/ic/qwxreg.h

5041

uint32_t max_bcn_ie_size;

sys/dev/ic/qwxreg.h

5042

uint32_t max_num_scan_channels;

sys/dev/ic/qwxreg.h

5043

uint32_t max_supported_macs;

sys/dev/ic/qwxreg.h

5044

uint32_t wmi_fw_sub_feat_caps;

sys/dev/ic/qwxreg.h

5045

uint32_t txrx_chainmask;

sys/dev/ic/qwxreg.h

5046

uint32_t default_dbs_hw_mode_index;

sys/dev/ic/qwxreg.h

5047

uint32_t num_msdu_desc;

sys/dev/ic/qwxreg.h

5096

uint32_t wmm_ac;

sys/dev/ic/qwxreg.h

5097

uint32_t user_priority;

sys/dev/ic/qwxreg.h

5098

uint32_t service_interval;

sys/dev/ic/qwxreg.h

5099

uint32_t suspend_interval;

sys/dev/ic/qwxreg.h

5100

uint32_t delay_interval;

sys/dev/ic/qwxreg.h

5104

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5106

uint32_t num_ac;

sys/dev/ic/qwxreg.h

5110

uint32_t wmm_ac;

sys/dev/ic/qwxreg.h

5111

uint32_t user_priority;

sys/dev/ic/qwxreg.h

5112

uint32_t service_interval;

sys/dev/ic/qwxreg.h

5113

uint32_t suspend_interval;

sys/dev/ic/qwxreg.h

5114

uint32_t delay_interval;

sys/dev/ic/qwxreg.h

5279

uint32_t eeprom_rd;

sys/dev/ic/qwxreg.h

5280

uint32_t eeprom_rd_ext;

sys/dev/ic/qwxreg.h

5281

uint32_t regcap1;

sys/dev/ic/qwxreg.h

5282

uint32_t regcap2;

sys/dev/ic/qwxreg.h

5283

uint32_t wireless_modes;

sys/dev/ic/qwxreg.h

5284

uint32_t low_2ghz_chan;

sys/dev/ic/qwxreg.h

5285

uint32_t high_2ghz_chan;

sys/dev/ic/qwxreg.h

5286

uint32_t low_5ghz_chan;

sys/dev/ic/qwxreg.h

5287

uint32_t high_5ghz_chan;

sys/dev/ic/qwxreg.h

5293

uint32_t len;

sys/dev/ic/qwxreg.h

5294

uint32_t req_id;

sys/dev/ic/qwxreg.h

5312

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5313

uint32_t cwmin;

sys/dev/ic/qwxreg.h

5314

uint32_t cwmax;

sys/dev/ic/qwxreg.h

5315

uint32_t aifs;

sys/dev/ic/qwxreg.h

5316

uint32_t txoplimit;

sys/dev/ic/qwxreg.h

5317

uint32_t acm;

sys/dev/ic/qwxreg.h

5318

uint32_t no_ack;

sys/dev/ic/qwxreg.h

5331

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5332

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5334

uint32_t wmm_param_type;

sys/dev/ic/qwxreg.h

5361

uint32_t sta_cong_timer_ms;

sys/dev/ic/qwxreg.h

5362

uint32_t mbss_support;

sys/dev/ic/qwxreg.h

5363

uint32_t default_slot_size;

sys/dev/ic/qwxreg.h

5364

uint32_t congestion_thresh_setup;

sys/dev/ic/qwxreg.h

5365

uint32_t congestion_thresh_teardown;

sys/dev/ic/qwxreg.h

5366

uint32_t congestion_thresh_critical;

sys/dev/ic/qwxreg.h

5367

uint32_t interference_thresh_teardown;

sys/dev/ic/qwxreg.h

5368

uint32_t interference_thresh_setup;

sys/dev/ic/qwxreg.h

5369

uint32_t min_no_sta_setup;

sys/dev/ic/qwxreg.h

5370

uint32_t min_no_sta_teardown;

sys/dev/ic/qwxreg.h

5371

uint32_t no_of_bcast_mcast_slots;

sys/dev/ic/qwxreg.h

5372

uint32_t min_no_twt_slots;

sys/dev/ic/qwxreg.h

5373

uint32_t max_no_sta_twt;

sys/dev/ic/qwxreg.h

5374

uint32_t mode_check_interval;

sys/dev/ic/qwxreg.h

5375

uint32_t add_sta_slot_interval;

sys/dev/ic/qwxreg.h

5376

uint32_t remove_sta_slot_interval;

sys/dev/ic/qwxreg.h

5380

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5381

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

5382

uint32_t sta_cong_timer_ms;

sys/dev/ic/qwxreg.h

5383

uint32_t mbss_support;

sys/dev/ic/qwxreg.h

5384

uint32_t default_slot_size;

sys/dev/ic/qwxreg.h

5385

uint32_t congestion_thresh_setup;

sys/dev/ic/qwxreg.h

5386

uint32_t congestion_thresh_teardown;

sys/dev/ic/qwxreg.h

5387

uint32_t congestion_thresh_critical;

sys/dev/ic/qwxreg.h

5388

uint32_t interference_thresh_teardown;

sys/dev/ic/qwxreg.h

5389

uint32_t interference_thresh_setup;

sys/dev/ic/qwxreg.h

5390

uint32_t min_no_sta_setup;

sys/dev/ic/qwxreg.h

5391

uint32_t min_no_sta_teardown;

sys/dev/ic/qwxreg.h

5392

uint32_t no_of_bcast_mcast_slots;

sys/dev/ic/qwxreg.h

5393

uint32_t min_no_twt_slots;

sys/dev/ic/qwxreg.h

5394

uint32_t max_no_sta_twt;

sys/dev/ic/qwxreg.h

5395

uint32_t mode_check_interval;

sys/dev/ic/qwxreg.h

5396

uint32_t add_sta_slot_interval;

sys/dev/ic/qwxreg.h

5397

uint32_t remove_sta_slot_interval;

sys/dev/ic/qwxreg.h

5401

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5402

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

5422

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5423

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5425

uint32_t dialog_id;

sys/dev/ic/qwxreg.h

5426

uint32_t wake_intvl_us;

sys/dev/ic/qwxreg.h

5427

uint32_t wake_intvl_mantis;

sys/dev/ic/qwxreg.h

5428

uint32_t wake_dura_us;

sys/dev/ic/qwxreg.h

5429

uint32_t sp_offset_us;

sys/dev/ic/qwxreg.h

5430

uint32_t flags;

sys/dev/ic/qwxreg.h

5434

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5436

uint32_t dialog_id;

sys/dev/ic/qwxreg.h

5437

uint32_t wake_intvl_us;

sys/dev/ic/qwxreg.h

5438

uint32_t wake_intvl_mantis;

sys/dev/ic/qwxreg.h

5439

uint32_t wake_dura_us;

sys/dev/ic/qwxreg.h

5440

uint32_t sp_offset_us;

sys/dev/ic/qwxreg.h

5462

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5464

uint32_t dialog_id;

sys/dev/ic/qwxreg.h

5465

uint32_t status;

sys/dev/ic/qwxreg.h

5469

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5471

uint32_t dialog_id;

sys/dev/ic/qwxreg.h

5475

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5476

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5478

uint32_t dialog_id;

sys/dev/ic/qwxreg.h

5482

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5484

uint32_t dialog_id;

sys/dev/ic/qwxreg.h

5488

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5489

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5491

uint32_t dialog_id;

sys/dev/ic/qwxreg.h

5495

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5497

uint32_t dialog_id;

sys/dev/ic/qwxreg.h

5498

uint32_t sp_offset_us;

sys/dev/ic/qwxreg.h

5499

uint32_t next_twt_size;

sys/dev/ic/qwxreg.h

5503

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5504

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5506

uint32_t dialog_id;

sys/dev/ic/qwxreg.h

5507

uint32_t sp_offset_us;

sys/dev/ic/qwxreg.h

5508

uint32_t next_twt_size;

sys/dev/ic/qwxreg.h

5512

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5513

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

5514

uint32_t enable;

sys/dev/ic/qwxreg.h

5517

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5521

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5522

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

5523

uint32_t bitmap[2];

sys/dev/ic/qwxreg.h

5541

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5542

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5543

uint32_t flags;

sys/dev/ic/qwxreg.h

5544

uint32_t evt_type;

sys/dev/ic/qwxreg.h

5545

uint32_t current_bss_color;

sys/dev/ic/qwxreg.h

5546

uint32_t detection_period_ms;

sys/dev/ic/qwxreg.h

5547

uint32_t scan_period_ms;

sys/dev/ic/qwxreg.h

5548

uint32_t free_slot_expiry_time_ms;

sys/dev/ic/qwxreg.h

5552

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5553

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5554

uint32_t enable;

sys/dev/ic/qwxreg.h

5558

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5559

uint32_t evt_type;

sys/dev/ic/qwxreg.h

5567

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5568

uint32_t lro_enable;

sys/dev/ic/qwxreg.h

5569

uint32_t res;

sys/dev/ic/qwxreg.h

5570

uint32_t th_4[ATH11K_IPV4_TH_SEED_SIZE];

sys/dev/ic/qwxreg.h

5571

uint32_t th_6[ATH11K_IPV6_TH_SEED_SIZE];

sys/dev/ic/qwxreg.h

5572

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

5595

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5596

uint32_t scan_count;

sys/dev/ic/qwxreg.h

5597

uint32_t scan_period;

sys/dev/ic/qwxreg.h

5598

uint32_t scan_priority;

sys/dev/ic/qwxreg.h

5599

uint32_t scan_fft_size;

sys/dev/ic/qwxreg.h

5600

uint32_t scan_gc_ena;

sys/dev/ic/qwxreg.h

5601

uint32_t scan_restart_ena;

sys/dev/ic/qwxreg.h

5602

uint32_t scan_noise_floor_ref;

sys/dev/ic/qwxreg.h

5603

uint32_t scan_init_delay;

sys/dev/ic/qwxreg.h

5604

uint32_t scan_nb_tone_thr;

sys/dev/ic/qwxreg.h

5605

uint32_t scan_str_bin_thr;

sys/dev/ic/qwxreg.h

5606

uint32_t scan_wb_rpt_mode;

sys/dev/ic/qwxreg.h

5607

uint32_t scan_rssi_rpt_mode;

sys/dev/ic/qwxreg.h

5608

uint32_t scan_rssi_thr;

sys/dev/ic/qwxreg.h

5609

uint32_t scan_pwr_format;

sys/dev/ic/qwxreg.h

5610

uint32_t scan_rpt_mode;

sys/dev/ic/qwxreg.h

5611

uint32_t scan_bin_scale;

sys/dev/ic/qwxreg.h

5612

uint32_t scan_dbm_adj;

sys/dev/ic/qwxreg.h

5613

uint32_t scan_chn_mask;

sys/dev/ic/qwxreg.h

5617

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5627

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5628

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5629

uint32_t trigger_cmd;

sys/dev/ic/qwxreg.h

5630

uint32_t enable_cmd;

sys/dev/ic/qwxreg.h

5634

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5635

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

5636

uint32_t module_id; /* see enum wmi_direct_buffer_module */

sys/dev/ic/qwxreg.h

5637

uint32_t base_paddr_lo;

sys/dev/ic/qwxreg.h

5638

uint32_t base_paddr_hi;

sys/dev/ic/qwxreg.h

5639

uint32_t head_idx_paddr_lo;

sys/dev/ic/qwxreg.h

5640

uint32_t head_idx_paddr_hi;

sys/dev/ic/qwxreg.h

5641

uint32_t tail_idx_paddr_lo;

sys/dev/ic/qwxreg.h

5642

uint32_t tail_idx_paddr_hi;

sys/dev/ic/qwxreg.h

5643

uint32_t num_elems; /* Number of elems in the ring */

sys/dev/ic/qwxreg.h

5644

uint32_t buf_size; /* size of allocated buffer in bytes */

sys/dev/ic/qwxreg.h

5647

uint32_t num_resp_per_event;

sys/dev/ic/qwxreg.h

5652

uint32_t event_timeout_ms;

sys/dev/ic/qwxreg.h

5656

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

5657

uint32_t module_id;

sys/dev/ic/qwxreg.h

5658

uint32_t num_buf_release_entry;

sys/dev/ic/qwxreg.h

5659

uint32_t num_meta_data_entry;

sys/dev/ic/qwxreg.h

5663

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5664

uint32_t paddr_lo;

sys/dev/ic/qwxreg.h

5669

uint32_t paddr_hi;

sys/dev/ic/qwxreg.h

5678

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5680

uint32_t reset_delay;

sys/dev/ic/qwxreg.h

5681

uint32_t freq1;

sys/dev/ic/qwxreg.h

5682

uint32_t freq2;

sys/dev/ic/qwxreg.h

5683

uint32_t ch_width;

sys/dev/ic/qwxreg.h

5692

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5693

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5694

uint32_t interval;

sys/dev/ic/qwxreg.h

5695

uint32_t config; /* enum wmi_fils_discovery_cmd_type */

sys/dev/ic/qwxreg.h

5699

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5700

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5701

uint32_t buf_len;

sys/dev/ic/qwxreg.h

5705

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5706

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5707

uint32_t buf_len;

sys/dev/ic/qwxreg.h

5711

uint32_t num_vdevs;

sys/dev/ic/qwxreg.h

5712

uint32_t num_peers;

sys/dev/ic/qwxreg.h

5713

uint32_t num_active_peers;

sys/dev/ic/qwxreg.h

5714

uint32_t num_offload_peers;

sys/dev/ic/qwxreg.h

5715

uint32_t num_offload_reorder_buffs;

sys/dev/ic/qwxreg.h

5716

uint32_t num_peer_keys;

sys/dev/ic/qwxreg.h

5717

uint32_t num_tids;

sys/dev/ic/qwxreg.h

5718

uint32_t ast_skid_limit;

sys/dev/ic/qwxreg.h

5719

uint32_t tx_chain_mask;

sys/dev/ic/qwxreg.h

5720

uint32_t rx_chain_mask;

sys/dev/ic/qwxreg.h

5721

uint32_t rx_timeout_pri[4];

sys/dev/ic/qwxreg.h

5722

uint32_t rx_decap_mode;

sys/dev/ic/qwxreg.h

5723

uint32_t scan_max_pending_req;

sys/dev/ic/qwxreg.h

5724

uint32_t bmiss_offload_max_vdev;

sys/dev/ic/qwxreg.h

5725

uint32_t roam_offload_max_vdev;

sys/dev/ic/qwxreg.h

5726

uint32_t roam_offload_max_ap_profiles;

sys/dev/ic/qwxreg.h

5727

uint32_t num_mcast_groups;

sys/dev/ic/qwxreg.h

5728

uint32_t num_mcast_table_elems;

sys/dev/ic/qwxreg.h

5729

uint32_t mcast2ucast_mode;

sys/dev/ic/qwxreg.h

5730

uint32_t tx_dbg_log_size;

sys/dev/ic/qwxreg.h

5731

uint32_t num_wds_entries;

sys/dev/ic/qwxreg.h

5732

uint32_t dma_burst_size;

sys/dev/ic/qwxreg.h

5733

uint32_t mac_aggr_delim;

sys/dev/ic/qwxreg.h

5734

uint32_t rx_skip_defrag_timeout_dup_detection_check;

sys/dev/ic/qwxreg.h

5735

uint32_t vow_config;

sys/dev/ic/qwxreg.h

5736

uint32_t gtk_offload_max_vdev;

sys/dev/ic/qwxreg.h

5737

uint32_t num_msdu_desc;

sys/dev/ic/qwxreg.h

5738

uint32_t max_frag_entries;

sys/dev/ic/qwxreg.h

5739

uint32_t max_peer_ext_stats;

sys/dev/ic/qwxreg.h

5740

uint32_t smart_ant_cap;

sys/dev/ic/qwxreg.h

5741

uint32_t bk_minfree;

sys/dev/ic/qwxreg.h

5742

uint32_t be_minfree;

sys/dev/ic/qwxreg.h

5743

uint32_t vi_minfree;

sys/dev/ic/qwxreg.h

5744

uint32_t vo_minfree;

sys/dev/ic/qwxreg.h

5745

uint32_t rx_batchmode;

sys/dev/ic/qwxreg.h

5746

uint32_t tt_support;

sys/dev/ic/qwxreg.h

5747

uint32_t flag1;

sys/dev/ic/qwxreg.h

5748

uint32_t iphdr_pad_config;

sys/dev/ic/qwxreg.h

5749

uint32_t qwrap_config:16,

sys/dev/ic/qwxreg.h

5751

uint32_t num_tdls_vdevs;

sys/dev/ic/qwxreg.h

5752

uint32_t num_tdls_conn_table_entries;

sys/dev/ic/qwxreg.h

5753

uint32_t beacon_tx_offload_max_vdev;

sys/dev/ic/qwxreg.h

5754

uint32_t num_multicast_filter_entries;

sys/dev/ic/qwxreg.h

5755

uint32_t num_wow_filters;

sys/dev/ic/qwxreg.h

5756

uint32_t num_keep_alive_pattern;

sys/dev/ic/qwxreg.h

5757

uint32_t keep_alive_pattern_size;

sys/dev/ic/qwxreg.h

5758

uint32_t max_tdls_concurrent_sleep_sta;

sys/dev/ic/qwxreg.h

5759

uint32_t max_tdls_concurrent_buffer_sta;

sys/dev/ic/qwxreg.h

5760

uint32_t wmi_send_separate;

sys/dev/ic/qwxreg.h

5761

uint32_t num_ocb_vdevs;

sys/dev/ic/qwxreg.h

5762

uint32_t num_ocb_channels;

sys/dev/ic/qwxreg.h

5763

uint32_t num_ocb_schedules;

sys/dev/ic/qwxreg.h

5764

uint32_t num_ns_ext_tuples_cfg;

sys/dev/ic/qwxreg.h

5765

uint32_t bpf_instruction_size;

sys/dev/ic/qwxreg.h

5766

uint32_t max_bssid_rx_filters;

sys/dev/ic/qwxreg.h

5767

uint32_t use_pdev_id;

sys/dev/ic/qwxreg.h

5768

uint32_t peer_map_unmap_v2_support;

sys/dev/ic/qwxreg.h

5769

uint32_t sched_params;

sys/dev/ic/qwxreg.h

5770

uint32_t twt_ap_pdev_count;

sys/dev/ic/qwxreg.h

5771

uint32_t twt_ap_sta_count;

sys/dev/ic/qwxreg.h

5773

uint32_t ema_max_vap_cnt;

sys/dev/ic/qwxreg.h

5774

uint32_t ema_max_profile_period;

sys/dev/ic/qwxreg.h

5787

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5788

uint32_t dbg_log_param;

sys/dev/ic/qwxreg.h

5789

uint32_t value;

sys/dev/ic/qwxreg.h

5813

uint32_t peer_ps_state;

sys/dev/ic/qwxreg.h

5814

uint32_t ps_supported_bitmap;

sys/dev/ic/qwxreg.h

5815

uint32_t peer_ps_valid;

sys/dev/ic/qwxreg.h

5816

uint32_t peer_ps_timestamp;

sys/dev/ic/qwxreg.h

5826

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

5827

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5828

uint32_t enable;

sys/dev/ic/qwxreg.h

5829

uint32_t hw_filter_bitmap;

sys/dev/ic/qwxreg.h

5977

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

5978

uint32_t flag;

sys/dev/ic/qwxreg.h

5980

uint32_t data_len;

sys/dev/ic/qwxreg.h

6009

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

6010

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

6011

uint32_t is_add;

sys/dev/ic/qwxreg.h

6012

uint32_t event_bitmap;

sys/dev/ic/qwxreg.h

6016

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

6017

uint32_t enable;

sys/dev/ic/qwxreg.h

6018

uint32_t pause_iface_config;

sys/dev/ic/qwxreg.h

6019

uint32_t flags;

sys/dev/ic/qwxreg.h

6023

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

6024

uint32_t reserved;

sys/dev/ic/qwxreg.h

6028

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

6029

uint32_t flag;

sys/dev/ic/qwxreg.h

6030

uint32_t wake_reason;

sys/dev/ic/qwxreg.h

6031

uint32_t data_len;

sys/dev/ic/qwxreg.h

6035

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

6038

uint32_t pattern_offset;

sys/dev/ic/qwxreg.h

6039

uint32_t pattern_len;

sys/dev/ic/qwxreg.h

6040

uint32_t bitmask_len;

sys/dev/ic/qwxreg.h

6041

uint32_t pattern_id;

sys/dev/ic/qwxreg.h

6045

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

6046

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

6047

uint32_t pattern_id;

sys/dev/ic/qwxreg.h

6048

uint32_t pattern_type;

sys/dev/ic/qwxreg.h

6052

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

6053

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

6054

uint32_t pattern_id;

sys/dev/ic/qwxreg.h

6055

uint32_t pattern_type;

sys/dev/ic/qwxreg.h

6104

uint32_t valid;

sys/dev/ic/qwxreg.h

6109

uint32_t valid;

sys/dev/ic/qwxreg.h

6110

uint32_t enc_type;

sys/dev/ic/qwxreg.h

6114

uint32_t valid;

sys/dev/ic/qwxreg.h

6115

uint32_t auth_type;

sys/dev/ic/qwxreg.h

6119

uint32_t valid;

sys/dev/ic/qwxreg.h

6120

uint32_t bcast_nw_type;

sys/dev/ic/qwxreg.h

6124

uint32_t valid;

sys/dev/ic/qwxreg.h

6130

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

6142

uint32_t authentication;

sys/dev/ic/qwxreg.h

6143

uint32_t encryption;

sys/dev/ic/qwxreg.h

6144

uint32_t bcast_nw_type;

sys/dev/ic/qwxreg.h

6155

uint32_t fast_scan_period;

sys/dev/ic/qwxreg.h

6156

uint32_t slow_scan_period;

sys/dev/ic/qwxreg.h

6161

uint32_t delay_start_time;

sys/dev/ic/qwxreg.h

6162

uint32_t active_min_time;

sys/dev/ic/qwxreg.h

6163

uint32_t active_max_time;

sys/dev/ic/qwxreg.h

6164

uint32_t passive_min_time;

sys/dev/ic/qwxreg.h

6165

uint32_t passive_max_time;

sys/dev/ic/qwxreg.h

6168

uint32_t enable_pno_scan_randomization;

sys/dev/ic/qwxreg.h

6174

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

6175

uint32_t flags;

sys/dev/ic/qwxreg.h

6176

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

6177

uint32_t fast_scan_max_cycles;

sys/dev/ic/qwxreg.h

6178

uint32_t active_dwell_time;

sys/dev/ic/qwxreg.h

6179

uint32_t passive_dwell_time;

sys/dev/ic/qwxreg.h

6180

uint32_t probe_bundle_size;

sys/dev/ic/qwxreg.h

6183

uint32_t rest_time;

sys/dev/ic/qwxreg.h

6186

uint32_t max_rest_time;

sys/dev/ic/qwxreg.h

6189

uint32_t scan_backoff_multiplier;

sys/dev/ic/qwxreg.h

6192

uint32_t fast_scan_period;

sys/dev/ic/qwxreg.h

6195

uint32_t slow_scan_period;

sys/dev/ic/qwxreg.h

6197

uint32_t no_of_ssids;

sys/dev/ic/qwxreg.h

6199

uint32_t num_of_channels;

sys/dev/ic/qwxreg.h

6202

uint32_t delay_start_time;

sys/dev/ic/qwxreg.h

6211

uint32_t ie_bitmap[8];

sys/dev/ic/qwxreg.h

6214

uint32_t num_vendor_oui;

sys/dev/ic/qwxreg.h

6217

uint32_t num_cnlo_band_pref;

sys/dev/ic/qwxreg.h

6233

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

6234

uint32_t flags;

sys/dev/ic/qwxreg.h

6248

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

6249

uint32_t flags;

sys/dev/ic/qwxreg.h

6257

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

6258

uint32_t flags;

sys/dev/ic/qwxreg.h

6259

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

6260

uint32_t num_ns_ext_tuples;

sys/dev/ic/qwxreg.h

6283

uint32_t word0;

sys/dev/ic/qwxreg.h

6284

uint32_t word1;

sys/dev/ic/qwxreg.h

6290

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

6291

uint32_t flags;

sys/dev/ic/qwxreg.h

6292

uint32_t refresh_cnt;

sys/dev/ic/qwxreg.h

6305

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

6306

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

6307

uint32_t flags;

sys/dev/ic/qwxreg.h

6318

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

6319

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

6320

uint32_t sar_len;

sys/dev/ic/qwxreg.h

6321

uint32_t rsvd_len;

sys/dev/ic/qwxreg.h

6325

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

6326

uint32_t pdev_id;

sys/dev/ic/qwxreg.h

6327

uint32_t rsvd_len;

sys/dev/ic/qwxreg.h

6331

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

6332

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

6333

uint32_t enabled;

sys/dev/ic/qwxreg.h

6336

uint32_t method;

sys/dev/ic/qwxreg.h

6339

uint32_t interval;

sys/dev/ic/qwxreg.h

6347

uint32_t tlv_header;

sys/dev/ic/qwxreg.h

6348

uint32_t src_ip4_addr;

sys/dev/ic/qwxreg.h

6349

uint32_t dest_ip4_addr;

sys/dev/ic/qwxreg.h

6354

uint32_t vdev_id;

sys/dev/ic/qwxreg.h

6355

uint32_t enabled;

sys/dev/ic/qwxreg.h

6356

uint32_t method;

sys/dev/ic/qwxreg.h

6357

uint32_t interval;

sys/dev/ic/qwxreg.h

6358

uint32_t src_ip4_addr;

sys/dev/ic/qwxreg.h

6359

uint32_t dest_ip4_addr;

sys/dev/ic/qwxreg.h

6383

uint32_t version;

sys/dev/ic/qwxreg.h

6384

uint32_t type;

sys/dev/ic/qwxreg.h

6385

uint32_t src_node_id;

sys/dev/ic/qwxreg.h

6386

uint32_t src_port_id;

sys/dev/ic/qwxreg.h

6387

uint32_t confirm_rx;

sys/dev/ic/qwxreg.h

6388

uint32_t size;

sys/dev/ic/qwxreg.h

6389

uint32_t dst_node_id;

sys/dev/ic/qwxreg.h

6390

uint32_t dst_port_id;

sys/dev/ic/qwxreg.h

6398

uint32_t size;

sys/dev/ic/qwxreg.h

6406

uint32_t cmd;

sys/dev/ic/qwxreg.h

6410

uint32_t service;

sys/dev/ic/qwxreg.h

6411

uint32_t instance;

sys/dev/ic/qwxreg.h

6412

uint32_t node;

sys/dev/ic/qwxreg.h

6413

uint32_t port;

sys/dev/ic/qwxreg.h

6416

uint32_t node;

sys/dev/ic/qwxreg.h

6417

uint32_t port;

sys/dev/ic/qwxreg.h

6479

uint32_t elem_len;

sys/dev/ic/qwxreg.h

6480

uint32_t elem_size;

sys/dev/ic/qwxreg.h

6483

uint32_t offset;

sys/dev/ic/qwxreg.h

6524

uint32_t client_id;

sys/dev/ic/qwxreg.h

6532

uint32_t rejuvenate_enable;

sys/dev/ic/qwxreg.h

6558

uint32_t num_clients;

sys/dev/ic/qwxreg.h

6560

uint32_t wake_msi;

sys/dev/ic/qwxreg.h

6562

uint32_t gpios_len;

sys/dev/ic/qwxreg.h

6563

uint32_t gpios[QMI_WLFW_MAX_NUM_GPIO_V01];

sys/dev/ic/qwxreg.h

6581

uint32_t mem_bucket;

sys/dev/ic/qwxreg.h

6631

uint32_t size;

sys/dev/ic/qwxreg.h

6647

uint32_t size;

sys/dev/ic/qwxreg.h

6649

uint32_t mem_cfg_len;

sys/dev/ic/qwxreg.h

6654

uint32_t mem_seg_len;

sys/dev/ic/qwxreg.h

6660

uint32_t size;

sys/dev/ic/qwxreg.h

6666

uint32_t mem_seg_len;

sys/dev/ic/qwxreg.h

6705

uint32_t pipe_num;

sys/dev/ic/qwxreg.h

6706

uint32_t pipe_dir;

sys/dev/ic/qwxreg.h

6707

uint32_t nentries;

sys/dev/ic/qwxreg.h

6708

uint32_t nbytes_max;

sys/dev/ic/qwxreg.h

6709

uint32_t flags;

sys/dev/ic/qwxreg.h

6713

uint32_t service_id;

sys/dev/ic/qwxreg.h

6714

uint32_t pipe_dir;

sys/dev/ic/qwxreg.h

6715

uint32_t pipe_num;

sys/dev/ic/qwxreg.h

6724

uint32_t addr;

sys/dev/ic/qwxreg.h

6729

uint32_t size;

sys/dev/ic/qwxreg.h

6734

uint32_t chip_id;

sys/dev/ic/qwxreg.h

6735

uint32_t chip_family;

sys/dev/ic/qwxreg.h

6739

uint32_t board_id;

sys/dev/ic/qwxreg.h

6743

uint32_t soc_id;

sys/dev/ic/qwxreg.h

6747

uint32_t fw_version;

sys/dev/ic/qwxreg.h

6775

uint32_t voltage_mv;

sys/dev/ic/qwxreg.h

6777

uint32_t time_freq_hz;

sys/dev/ic/qwxreg.h

6779

uint32_t otp_version;

sys/dev/ic/qwxreg.h

6781

uint32_t eeprom_read_timeout;

sys/dev/ic/qwxreg.h

6800

uint32_t total_size;

sys/dev/ic/qwxreg.h

6802

uint32_t seg_id;

sys/dev/ic/qwxreg.h

6804

uint32_t data_len;

sys/dev/ic/qwxreg.h

6823

uint32_t size;

sys/dev/ic/qwxreg.h

6848

uint32_t mode;

sys/dev/ic/qwxreg.h

6861

uint32_t tgt_cfg_len;

sys/dev/ic/qwxreg.h

6865

uint32_t svc_cfg_len;

sys/dev/ic/qwxreg.h

6869

uint32_t shadow_reg_len;

sys/dev/ic/qwxreg.h

6873

uint32_t shadow_reg_v2_len;

sys/dev/ic/qwxreg.h

7395

uint32_t info0;

sys/dev/ic/qwxreg.h

7396

uint32_t info1;

sys/dev/ic/qwxreg.h

7860

uint32_t tl;

sys/dev/ic/qwxreg.h

7881

uint32_t info0; /* %RX_MPDU_DESC_INFO */

sys/dev/ic/qwxreg.h

7882

uint32_t meta_data;

sys/dev/ic/qwxreg.h

7967

uint32_t info0;

sys/dev/ic/qwxreg.h

7968

uint32_t rsvd0;

sys/dev/ic/qwxreg.h

8073

uint32_t queue_addr_lo;

sys/dev/ic/qwxreg.h

8074

uint32_t info0; /* %HAL_REO_DEST_RING_INFO0_ */

sys/dev/ic/qwxreg.h

8075

uint32_t info1; /* %HAL_REO_DEST_RING_INFO1_ */

sys/dev/ic/qwxreg.h

8076

uint32_t rsvd0;

sys/dev/ic/qwxreg.h

8077

uint32_t rsvd1;

sys/dev/ic/qwxreg.h

8078

uint32_t rsvd2;

sys/dev/ic/qwxreg.h

8079

uint32_t rsvd3;

sys/dev/ic/qwxreg.h

8080

uint32_t rsvd4;

sys/dev/ic/qwxreg.h

8081

uint32_t rsvd5;

sys/dev/ic/qwxreg.h

8082

uint32_t info2; /* %HAL_REO_DEST_RING_INFO2_ */

sys/dev/ic/qwxreg.h

8175

uint32_t queue_addr_lo;

sys/dev/ic/qwxreg.h

8176

uint32_t info0; /* %HAL_REO_ENTR_RING_INFO0_ */

sys/dev/ic/qwxreg.h

8177

uint32_t info1; /* %HAL_REO_ENTR_RING_INFO1_ */

sys/dev/ic/qwxreg.h

8178

uint32_t info2; /* %HAL_REO_DEST_RING_INFO2_ */

sys/dev/ic/qwxreg.h

8255

uint32_t info0;

sys/dev/ic/qwxreg.h

8256

uint32_t info1;

sys/dev/ic/qwxreg.h

8263

uint32_t info0;

sys/dev/ic/qwxreg.h

8329

uint32_t addr_lo;

sys/dev/ic/qwxreg.h

8330

uint32_t flag;

sys/dev/ic/qwxreg.h

8331

uint32_t upd0;

sys/dev/ic/qwxreg.h

8332

uint32_t upd1;

sys/dev/ic/qwxreg.h

8333

uint32_t upd2;

sys/dev/ic/qwxreg.h

8334

uint32_t pn[4];

sys/dev/ic/qwxreg.h

8350

uint32_t queue_addr_lo;

sys/dev/ic/qwxreg.h

8351

uint32_t info0;

sys/dev/ic/qwxreg.h

8352

uint32_t rsvd0[6];

sys/dev/ic/qwxreg.h

8392

uint32_t desc_addr_lo;

sys/dev/ic/qwxreg.h

8393

uint32_t info0;

sys/dev/ic/qwxreg.h

8394

uint32_t rsvd0[6];

sys/dev/ic/qwxreg.h

8407

uint32_t cache_addr_lo;

sys/dev/ic/qwxreg.h

8408

uint32_t info0;

sys/dev/ic/qwxreg.h

8409

uint32_t rsvd0[6];

sys/dev/ic/qwxreg.h

8484

uint32_t info0;

sys/dev/ic/qwxreg.h

8485

uint32_t info1;

sys/dev/ic/qwxreg.h

8486

uint32_t info2;

sys/dev/ic/qwxreg.h

8487

uint32_t info3;

sys/dev/ic/qwxreg.h

8488

uint32_t info4;

sys/dev/ic/qwxreg.h

8675

uint32_t ctrl_buf_addr_lo;

sys/dev/ic/qwxreg.h

8676

uint32_t info0;

sys/dev/ic/qwxreg.h

8677

uint32_t meta_data[2];

sys/dev/ic/qwxreg.h

8678

uint32_t rsvd0[2];

sys/dev/ic/qwxreg.h

8679

uint32_t info1;

sys/dev/ic/qwxreg.h

8724

uint32_t info0;

sys/dev/ic/qwxreg.h

8725

uint32_t msdu_byte_count;

sys/dev/ic/qwxreg.h

8726

uint32_t msdu_timestamp;

sys/dev/ic/qwxreg.h

8727

uint32_t meta_data[2];

sys/dev/ic/qwxreg.h

8728

uint32_t info1;

sys/dev/ic/qwxreg.h

8729

uint32_t rsvd0;

sys/dev/ic/qwxreg.h

8730

uint32_t info2;

sys/dev/ic/qwxreg.h

8769

uint32_t buffer_addr_low;

sys/dev/ic/qwxreg.h

8770

uint32_t buffer_addr_info; /* %HAL_CE_SRC_DESC_ADDR_INFO_ */

sys/dev/ic/qwxreg.h

8771

uint32_t meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */

sys/dev/ic/qwxreg.h

8772

uint32_t flags; /* %HAL_CE_SRC_DESC_FLAGS_ */

sys/dev/ic/qwxreg.h

8858

uint32_t buffer_addr_low;

sys/dev/ic/qwxreg.h

8859

uint32_t buffer_addr_info; /* %HAL_CE_DEST_DESC_ADDR_INFO_ */

sys/dev/ic/qwxreg.h

8913

uint32_t flags; /* %HAL_CE_DST_STATUS_DESC_FLAGS_ */

sys/dev/ic/qwxreg.h

8914

uint32_t toeplitz_hash0;

sys/dev/ic/qwxreg.h

8915

uint32_t toeplitz_hash1;

sys/dev/ic/qwxreg.h

8916

uint32_t meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */

sys/dev/ic/qwxreg.h

9017

uint32_t info0;

sys/dev/ic/qwxreg.h

9018

uint32_t tsf;

sys/dev/ic/qwxreg.h

9126

uint32_t info0;

sys/dev/ic/qwxreg.h

9127

uint32_t info1;

sys/dev/ic/qwxreg.h

9128

uint32_t info2;

sys/dev/ic/qwxreg.h

9130

uint32_t info3;

sys/dev/ic/qwxreg.h

9352

uint32_t info0;

sys/dev/ic/qwxreg.h

9370

uint32_t info0;

sys/dev/ic/qwxreg.h

9371

uint32_t pn[4];

sys/dev/ic/qwxreg.h

9377

uint32_t rsvd;

sys/dev/ic/qwxreg.h

9440

uint32_t rx_queue_num;

sys/dev/ic/qwxreg.h

9441

uint32_t info0;

sys/dev/ic/qwxreg.h

9442

uint32_t info1;

sys/dev/ic/qwxreg.h

9443

uint32_t pn[4];

sys/dev/ic/qwxreg.h

9444

uint32_t last_rx_enqueue_timestamp;

sys/dev/ic/qwxreg.h

9445

uint32_t last_rx_dequeue_timestamp;

sys/dev/ic/qwxreg.h

9446

uint32_t next_aging_queue[2];

sys/dev/ic/qwxreg.h

9447

uint32_t prev_aging_queue[2];

sys/dev/ic/qwxreg.h

9448

uint32_t rx_bitmap[8];

sys/dev/ic/qwxreg.h

9449

uint32_t info2;

sys/dev/ic/qwxreg.h

9450

uint32_t info3;

sys/dev/ic/qwxreg.h

9451

uint32_t info4;

sys/dev/ic/qwxreg.h

9452

uint32_t processed_mpdus;

sys/dev/ic/qwxreg.h

9453

uint32_t processed_msdus;

sys/dev/ic/qwxreg.h

9454

uint32_t processed_total_bytes;

sys/dev/ic/qwxreg.h

9455

uint32_t info5;

sys/dev/ic/qwxreg.h

9456

uint32_t rsvd[3];

sys/dev/ic/qwxreg.h

9577

uint32_t queue_addr_lo;

sys/dev/ic/qwxreg.h

9578

uint32_t info0;

sys/dev/ic/qwxreg.h

9579

uint32_t info1;

sys/dev/ic/qwxreg.h

9580

uint32_t info2;

sys/dev/ic/qwxreg.h

9581

uint32_t pn[4];

sys/dev/ic/qwxreg.h

9589

uint32_t info0;

sys/dev/ic/qwxreg.h

9590

uint32_t rsvd[7];

sys/dev/ic/qwxreg.h

9613

uint32_t info0;

sys/dev/ic/qwxreg.h

9614

uint32_t timestamp;

sys/dev/ic/qwxreg.h

9656

uint32_t info0;

sys/dev/ic/qwxreg.h

9657

uint32_t pn[4];

sys/dev/ic/qwxreg.h

9658

uint32_t last_rx_enqueue_timestamp;

sys/dev/ic/qwxreg.h

9659

uint32_t last_rx_dequeue_timestamp;

sys/dev/ic/qwxreg.h

9660

uint32_t rx_bitmap[8];

sys/dev/ic/qwxreg.h

9661

uint32_t info1;

sys/dev/ic/qwxreg.h

9662

uint32_t info2;

sys/dev/ic/qwxreg.h

9663

uint32_t info3;

sys/dev/ic/qwxreg.h

9664

uint32_t num_mpdu_frames;

sys/dev/ic/qwxreg.h

9665

uint32_t num_msdu_frames;

sys/dev/ic/qwxreg.h

9666

uint32_t total_bytes;

sys/dev/ic/qwxreg.h

9667

uint32_t info4;

sys/dev/ic/qwxreg.h

9668

uint32_t info5;

sys/dev/ic/qwxreg.h

9751

uint32_t info0;

sys/dev/ic/qwxreg.h

9752

uint32_t rsvd0[21];

sys/dev/ic/qwxreg.h

9753

uint32_t info1;

sys/dev/ic/qwxreg.h

9786

uint32_t info0;

sys/dev/ic/qwxreg.h

9787

uint32_t rsvd0[21];

sys/dev/ic/qwxreg.h

9788

uint32_t info1;

sys/dev/ic/qwxreg.h

9848

uint32_t info0;

sys/dev/ic/qwxreg.h

9849

uint32_t rsvd0[21];

sys/dev/ic/qwxreg.h

9850

uint32_t info1;

sys/dev/ic/qwxreg.h

9884

uint32_t info0;

sys/dev/ic/qwxreg.h

9885

uint32_t info1;

sys/dev/ic/qwxreg.h

9886

uint32_t rsvd0[20];

sys/dev/ic/qwxreg.h

9887

uint32_t info2;

sys/dev/ic/qwxreg.h

9927

uint32_t info0;

sys/dev/ic/qwxreg.h

9928

uint32_t info1;

sys/dev/ic/qwxreg.h

9929

uint32_t info2;

sys/dev/ic/qwxreg.h

9930

uint32_t info3;

sys/dev/ic/qwxreg.h

9931

uint32_t info4;

sys/dev/ic/qwxreg.h

9932

uint32_t rsvd0[17];

sys/dev/ic/qwxreg.h

9933

uint32_t info5;

sys/dev/ic/qwxvar.h

1006

uint32_t tx_num;

sys/dev/ic/qwxvar.h

1007

uint32_t timer_tx_num;

sys/dev/ic/qwxvar.h

1008

uint32_t ring_id;

sys/dev/ic/qwxvar.h

1009

uint32_t interval;

sys/dev/ic/qwxvar.h

1016

uint32_t *vaddr;

sys/dev/ic/qwxvar.h

1018

uint32_t size;

sys/dev/ic/qwxvar.h

1019

uint32_t ba_win_sz;

sys/dev/ic/qwxvar.h

1023

uint32_t cur_sn;

sys/dev/ic/qwxvar.h

1061

uint32_t *vaddr;

sys/dev/ic/qwxvar.h

1064

uint32_t ring_id;

sys/dev/ic/qwxvar.h

1085

uint32_t size;

sys/dev/ic/qwxvar.h

1122

uint32_t reo_cmd_cache_flush_count;

sys/dev/ic/qwxvar.h

1174

uint32_t *shadow_reg_v2;

sys/dev/ic/qwxvar.h

1175

uint32_t shadow_reg_v2_len;

sys/dev/ic/qwxvar.h

1179

uint32_t chip_id;

sys/dev/ic/qwxvar.h

1180

uint32_t chip_family;

sys/dev/ic/qwxvar.h

1181

uint32_t board_id;

sys/dev/ic/qwxvar.h

1182

uint32_t soc_id;

sys/dev/ic/qwxvar.h

1183

uint32_t fw_version;

sys/dev/ic/qwxvar.h

1184

uint32_t eeprom_caldata;

sys/dev/ic/qwxvar.h

119

uint32_t desc_id;

sys/dev/ic/qwxvar.h

1197

uint32_t vendor;

sys/dev/ic/qwxvar.h

1198

uint32_t device;

sys/dev/ic/qwxvar.h

1199

uint32_t subsystem_vendor;

sys/dev/ic/qwxvar.h

1200

uint32_t subsystem_device;

sys/dev/ic/qwxvar.h

1209

uint32_t rx_decap_mode;

sys/dev/ic/qwxvar.h

1219

uint32_t max_msg_len[QWX_MAX_RADIOS];

sys/dev/ic/qwxvar.h

1225

uint32_t num_mem_chunks;

sys/dev/ic/qwxvar.h

1226

uint32_t rx_decap_mode;

sys/dev/ic/qwxvar.h

123

uint32_t data_len;

sys/dev/ic/qwxvar.h

124

uint32_t pkt_offset;

sys/dev/ic/qwxvar.h

1243

uint32_t n_dma_ring_caps;

sys/dev/ic/qwxvar.h

1250

uint32_t n_hw_mode_caps;

sys/dev/ic/qwxvar.h

1251

uint32_t tot_phy_id;

sys/dev/ic/qwxvar.h

1255

uint32_t n_mac_phy_caps;

sys/dev/ic/qwxvar.h

1258

uint32_t n_ext_hal_reg_caps;

sys/dev/ic/qwxvar.h

126

uint32_t flags0; /* %HAL_TCL_DATA_CMD_INFO1_ */

sys/dev/ic/qwxvar.h

127

uint32_t flags1; /* %HAL_TCL_DATA_CMD_INFO2_ */

sys/dev/ic/qwxvar.h

1275

uint32_t num_extra_mac_addr;

sys/dev/ic/qwxvar.h

1282

uint32_t num_buf_entry;

sys/dev/ic/qwxvar.h

1283

uint32_t num_meta;

sys/dev/ic/qwxvar.h

1378

uint32_t base_vector;

sys/dev/ic/qwxvar.h

1389

uint32_t phy_id;

sys/dev/ic/qwxvar.h

1390

uint32_t max_bw_supported;

sys/dev/ic/qwxvar.h

1391

uint32_t ht_cap_info;

sys/dev/ic/qwxvar.h

1392

uint32_t he_cap_info[2];

sys/dev/ic/qwxvar.h

1393

uint32_t he_mcs;

sys/dev/ic/qwxvar.h

1394

uint32_t he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];

sys/dev/ic/qwxvar.h

1400

uint32_t supported_bands;

sys/dev/ic/qwxvar.h

1401

uint32_t ampdu_density;

sys/dev/ic/qwxvar.h

1402

uint32_t vht_cap;

sys/dev/ic/qwxvar.h

1403

uint32_t vht_mcs;

sys/dev/ic/qwxvar.h

1404

uint32_t he_mcs;

sys/dev/ic/qwxvar.h

1405

uint32_t tx_chain_mask;

sys/dev/ic/qwxvar.h

1406

uint32_t rx_chain_mask;

sys/dev/ic/qwxvar.h

1407

uint32_t tx_chain_mask_shift;

sys/dev/ic/qwxvar.h

1408

uint32_t rx_chain_mask_shift;

sys/dev/ic/qwxvar.h

1416

uint32_t pdev_id;

sys/dev/ic/qwxvar.h

1422

uint32_t pdev_id;

sys/dev/ic/qwxvar.h

1424

uint32_t min_elem;

sys/dev/ic/qwxvar.h

1425

uint32_t min_buf_sz;

sys/dev/ic/qwxvar.h

1426

uint32_t min_buf_align;

sys/dev/ic/qwxvar.h

1449

uint32_t mcs:4,

sys/dev/ic/qwxvar.h

1455

uint32_t ul_ofdma_user_v0_word0;

sys/dev/ic/qwxvar.h

1456

uint32_t ul_ofdma_user_v0_word1;

sys/dev/ic/qwxvar.h

1457

uint32_t ast_index;

sys/dev/ic/qwxvar.h

1458

uint32_t tid;

sys/dev/ic/qwxvar.h

1466

uint32_t preamble_type;

sys/dev/ic/qwxvar.h

1471

uint32_t mpdu_cnt_fcs_ok;

sys/dev/ic/qwxvar.h

1472

uint32_t mpdu_cnt_fcs_err;

sys/dev/ic/qwxvar.h

1473

uint32_t mpdu_fcs_ok_bitmap[8];

sys/dev/ic/qwxvar.h

1474

uint32_t mpdu_ok_byte_count;

sys/dev/ic/qwxvar.h

1475

uint32_t mpdu_err_byte_count;

sys/dev/ic/qwxvar.h

1479

uint32_t cookie;

sys/dev/ic/qwxvar.h

1482

uint32_t err_code;

sys/dev/ic/qwxvar.h

1498

uint32_t ppdu_id;

sys/dev/ic/qwxvar.h

1499

uint32_t ppdu_ts;

sys/dev/ic/qwxvar.h

1500

uint32_t num_mpdu_fcs_ok;

sys/dev/ic/qwxvar.h

1501

uint32_t num_mpdu_fcs_err;

sys/dev/ic/qwxvar.h

1502

uint32_t preamble_type;

sys/dev/ic/qwxvar.h

1536

uint32_t ast_index;

sys/dev/ic/qwxvar.h

155

uint32_t flags; /* %HAL_TX_STATUS_FLAGS_ */

sys/dev/ic/qwxvar.h

1556

uint32_t ppdu_len;

sys/dev/ic/qwxvar.h

1557

uint32_t prev_ppdu_id;

sys/dev/ic/qwxvar.h

1558

uint32_t device_id;

sys/dev/ic/qwxvar.h

156

uint32_t ppdu_id;

sys/dev/ic/qwxvar.h

1582

uint32_t status_ppdu_state;

sys/dev/ic/qwxvar.h

1583

uint32_t status_ppdu_start;

sys/dev/ic/qwxvar.h

1584

uint32_t status_ppdu_end;

sys/dev/ic/qwxvar.h

1585

uint32_t status_ppdu_compl;

sys/dev/ic/qwxvar.h

1586

uint32_t status_ppdu_start_mis;

sys/dev/ic/qwxvar.h

1587

uint32_t status_ppdu_end_mis;

sys/dev/ic/qwxvar.h

1588

uint32_t status_ppdu_done;

sys/dev/ic/qwxvar.h

1589

uint32_t dest_ppdu_done;

sys/dev/ic/qwxvar.h

1590

uint32_t dest_mpdu_done;

sys/dev/ic/qwxvar.h

1591

uint32_t dest_mpdu_drop;

sys/dev/ic/qwxvar.h

1592

uint32_t dup_mon_linkdesc_cnt;

sys/dev/ic/qwxvar.h

1593

uint32_t dup_mon_buf_cnt;

sys/dev/ic/qwxvar.h

1594

uint32_t dest_mon_stuck;

sys/dev/ic/qwxvar.h

1595

uint32_t dest_mon_not_reaped;

sys/dev/ic/qwxvar.h

160

uint32_t rate_stats;

sys/dev/ic/qwxvar.h

1602

uint32_t mon_ppdu_status;

sys/dev/ic/qwxvar.h

1603

uint32_t mon_last_buf_cookie;

sys/dev/ic/qwxvar.h

1625

uint32_t mac_id;

sys/dev/ic/qwxvar.h

1626

uint32_t mon_dest_ring_stuck_cnt;

sys/dev/ic/qwxvar.h

1651

uint32_t vdev_id;

sys/dev/ic/qwxvar.h

1654

uint32_t beacon_interval;

sys/dev/ic/qwxvar.h

1655

uint32_t dtim_period;

sys/dev/ic/qwxvar.h

1669

uint32_t uapsd;

sys/dev/ic/qwxvar.h

167

uint32_t bdf_addr;

sys/dev/ic/qwxvar.h

1675

uint32_t ssid_len;

sys/dev/ic/qwxvar.h

1679

uint32_t noa_len;

sys/dev/ic/qwxvar.h

1689

uint32_t aid;

sys/dev/ic/qwxvar.h

1727

uint32_t irqs[ATH11K_EXT_IRQ_NUM_MAX];

sys/dev/ic/qwxvar.h

1728

uint32_t num_irq;

sys/dev/ic/qwxvar.h

1729

uint32_t grp_id;

sys/dev/ic/qwxvar.h

181

uint32_t qmi_service_ins_id;

sys/dev/ic/qwxvar.h

1817

uint32_t start_tidmask;

sys/dev/ic/qwxvar.h

1818

uint32_t stop_tidmask;

sys/dev/ic/qwxvar.h

1824

uint32_t sc_flags;

sys/dev/ic/qwxvar.h

183

uint32_t ce_count;

sys/dev/ic/qwxvar.h

185

uint32_t target_ce_count;

sys/dev/ic/qwxvar.h

1863

uint32_t vdev_id_11d_scan;

sys/dev/ic/qwxvar.h

187

uint32_t svc_to_ce_map_len;

sys/dev/ic/qwxvar.h

1890

uint32_t qfullmsk;

sys/dev/ic/qwxvar.h

1914

uint32_t cc_freq_hz;

sys/dev/ic/qwxvar.h

1915

uint32_t cfg_tx_chainmask;

sys/dev/ic/qwxvar.h

1916

uint32_t cfg_rx_chainmask;

sys/dev/ic/qwxvar.h

1921

uint32_t allocated_vdev_map;

sys/dev/ic/qwxvar.h

1922

uint32_t free_vdev_map;

sys/dev/ic/qwxvar.h

1932

uint32_t num_db_cap;

sys/dev/ic/qwxvar.h

1936

uint32_t wlan_init_status;

sys/dev/ic/qwxvar.h

1938

uint32_t pktlog_defs_checksum;

sys/dev/ic/qwxvar.h

1944

uint32_t pdev_id;

sys/dev/ic/qwxvar.h

1947

uint32_t pdevs_active;

sys/dev/ic/qwxvar.h

1952

uint32_t service;

sys/dev/ic/qwxvar.h

1953

uint32_t instance;

sys/dev/ic/qwxvar.h

1954

uint32_t node;

sys/dev/ic/qwxvar.h

1955

uint32_t port;

sys/dev/ic/qwxvar.h

1979

uint32_t msi_addr_lo;

sys/dev/ic/qwxvar.h

1980

uint32_t msi_addr_hi;

sys/dev/ic/qwxvar.h

1981

uint32_t msi_data_start;

sys/dev/ic/qwxvar.h

1983

uint32_t msi_ce_irqmask;

sys/dev/ic/qwxvar.h

2052

void qwx_ce_get_shadow_config(struct qwx_softc *, uint32_t **, uint32_t *);

sys/dev/ic/qwxvar.h

2067

static inline enum ieee80211_edca_ac qwx_tid_to_ac(uint32_t tid)

sys/dev/ic/qwxvar.h

216

uint32_t num_vdevs;

sys/dev/ic/qwxvar.h

217

uint32_t num_peers;

sys/dev/ic/qwxvar.h

219

uint32_t hal_desc_sz;

sys/dev/ic/qwxvar.h

248

uint32_t start;

sys/dev/ic/qwxvar.h

249

uint32_t end;

sys/dev/ic/qwxvar.h

254

uint32_t tx_ring_size;

sys/dev/ic/qwxvar.h

275

uint32_t (*rx_desc_get_encrypt_type)(struct hal_rx_desc *desc);

sys/dev/ic/qwxvar.h

288

uint32_t (*rx_desc_get_msdu_freq)(struct hal_rx_desc *desc);

sys/dev/ic/qwxvar.h

298

uint32_t (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc);

sys/dev/ic/qwxvar.h

299

uint32_t (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc);

sys/dev/ic/qwxvar.h

311

uint32_t (*get_ring_selector)(struct sk_buff *skb);

sys/dev/ic/qwxvar.h

328

uint32_t hal_tcl1_ring_base_lsb;

sys/dev/ic/qwxvar.h

329

uint32_t hal_tcl1_ring_base_msb;

sys/dev/ic/qwxvar.h

330

uint32_t hal_tcl1_ring_id;

sys/dev/ic/qwxvar.h

331

uint32_t hal_tcl1_ring_misc;

sys/dev/ic/qwxvar.h

332

uint32_t hal_tcl1_ring_tp_addr_lsb;

sys/dev/ic/qwxvar.h

333

uint32_t hal_tcl1_ring_tp_addr_msb;

sys/dev/ic/qwxvar.h

334

uint32_t hal_tcl1_ring_consumer_int_setup_ix0;

sys/dev/ic/qwxvar.h

335

uint32_t hal_tcl1_ring_consumer_int_setup_ix1;

sys/dev/ic/qwxvar.h

336

uint32_t hal_tcl1_ring_msi1_base_lsb;

sys/dev/ic/qwxvar.h

337

uint32_t hal_tcl1_ring_msi1_base_msb;

sys/dev/ic/qwxvar.h

338

uint32_t hal_tcl1_ring_msi1_data;

sys/dev/ic/qwxvar.h

339

uint32_t hal_tcl2_ring_base_lsb;

sys/dev/ic/qwxvar.h

340

uint32_t hal_tcl_ring_base_lsb;

sys/dev/ic/qwxvar.h

342

uint32_t hal_tcl_status_ring_base_lsb;

sys/dev/ic/qwxvar.h

344

uint32_t hal_reo1_ring_base_lsb;

sys/dev/ic/qwxvar.h

345

uint32_t hal_reo1_ring_base_msb;

sys/dev/ic/qwxvar.h

346

uint32_t hal_reo1_ring_id;

sys/dev/ic/qwxvar.h

347

uint32_t hal_reo1_ring_misc;

sys/dev/ic/qwxvar.h

348

uint32_t hal_reo1_ring_hp_addr_lsb;

sys/dev/ic/qwxvar.h

349

uint32_t hal_reo1_ring_hp_addr_msb;

sys/dev/ic/qwxvar.h

350

uint32_t hal_reo1_ring_producer_int_setup;

sys/dev/ic/qwxvar.h

351

uint32_t hal_reo1_ring_msi1_base_lsb;

sys/dev/ic/qwxvar.h

352

uint32_t hal_reo1_ring_msi1_base_msb;

sys/dev/ic/qwxvar.h

353

uint32_t hal_reo1_ring_msi1_data;

sys/dev/ic/qwxvar.h

354

uint32_t hal_reo2_ring_base_lsb;

sys/dev/ic/qwxvar.h

355

uint32_t hal_reo1_aging_thresh_ix_0;

sys/dev/ic/qwxvar.h

356

uint32_t hal_reo1_aging_thresh_ix_1;

sys/dev/ic/qwxvar.h

357

uint32_t hal_reo1_aging_thresh_ix_2;

sys/dev/ic/qwxvar.h

358

uint32_t hal_reo1_aging_thresh_ix_3;

sys/dev/ic/qwxvar.h

360

uint32_t hal_reo1_ring_hp;

sys/dev/ic/qwxvar.h

361

uint32_t hal_reo1_ring_tp;

sys/dev/ic/qwxvar.h

362

uint32_t hal_reo2_ring_hp;

sys/dev/ic/qwxvar.h

364

uint32_t hal_reo_tcl_ring_base_lsb;

sys/dev/ic/qwxvar.h

365

uint32_t hal_reo_tcl_ring_hp;

sys/dev/ic/qwxvar.h

367

uint32_t hal_reo_status_ring_base_lsb;

sys/dev/ic/qwxvar.h

368

uint32_t hal_reo_status_hp;

sys/dev/ic/qwxvar.h

370

uint32_t hal_reo_cmd_ring_base_lsb;

sys/dev/ic/qwxvar.h

371

uint32_t hal_reo_cmd_ring_hp;

sys/dev/ic/qwxvar.h

373

uint32_t hal_sw2reo_ring_base_lsb;

sys/dev/ic/qwxvar.h

374

uint32_t hal_sw2reo_ring_hp;

sys/dev/ic/qwxvar.h

376

uint32_t hal_seq_wcss_umac_ce0_src_reg;

sys/dev/ic/qwxvar.h

377

uint32_t hal_seq_wcss_umac_ce0_dst_reg;

sys/dev/ic/qwxvar.h

378

uint32_t hal_seq_wcss_umac_ce1_src_reg;

sys/dev/ic/qwxvar.h

379

uint32_t hal_seq_wcss_umac_ce1_dst_reg;

sys/dev/ic/qwxvar.h

381

uint32_t hal_wbm_idle_link_ring_base_lsb;

sys/dev/ic/qwxvar.h

382

uint32_t hal_wbm_idle_link_ring_misc;

sys/dev/ic/qwxvar.h

384

uint32_t hal_wbm_release_ring_base_lsb;

sys/dev/ic/qwxvar.h

386

uint32_t hal_wbm0_release_ring_base_lsb;

sys/dev/ic/qwxvar.h

387

uint32_t hal_wbm1_release_ring_base_lsb;

sys/dev/ic/qwxvar.h

389

uint32_t pcie_qserdes_sysclk_en_sel;

sys/dev/ic/qwxvar.h

390

uint32_t pcie_pcs_osc_dtct_config_base;

sys/dev/ic/qwxvar.h

392

uint32_t hal_shadow_base_addr;

sys/dev/ic/qwxvar.h

393

uint32_t hal_reo1_misc_ctl;

sys/dev/ic/qwxvar.h

452

uint32_t (*read32)(struct qwx_softc *, uint32_t);

sys/dev/ic/qwxvar.h

453

void (*write32)(struct qwx_softc *, uint32_t, uint32_t);

sys/dev/ic/qwxvar.h

464

int *, uint32_t *, uint32_t *);

sys/dev/ic/qwxvar.h

48

extern uint32_t qwx_debug;

sys/dev/ic/qwxvar.h

484

uint32_t *ring_base_vaddr;

sys/dev/ic/qwxvar.h

486

uint32_t intr_batch_cntr_thres_entries;

sys/dev/ic/qwxvar.h

487

uint32_t intr_timer_thres_us;

sys/dev/ic/qwxvar.h

488

uint32_t flags;

sys/dev/ic/qwxvar.h

489

uint32_t max_buffer_len;

sys/dev/ic/qwxvar.h

490

uint32_t low_threshold;

sys/dev/ic/qwxvar.h

492

uint32_t msi_data;

sys/dev/ic/qwxvar.h

530

uint32_t *ring_base_vaddr;

sys/dev/ic/qwxvar.h

533

uint32_t num_entries;

sys/dev/ic/qwxvar.h

536

uint32_t ring_size;

sys/dev/ic/qwxvar.h

539

uint32_t ring_size_mask;

sys/dev/ic/qwxvar.h

542

uint32_t entry_size;

sys/dev/ic/qwxvar.h

545

uint32_t intr_timer_thres_us;

sys/dev/ic/qwxvar.h

548

uint32_t intr_batch_cntr_thres_entries;

sys/dev/ic/qwxvar.h

554

uint32_t msi_data;

sys/dev/ic/qwxvar.h

557

uint32_t flags;

sys/dev/ic/qwxvar.h

566

uint32_t hwreg_base[HAL_SRNG_NUM_REG_GRP];

sys/dev/ic/qwxvar.h

576

uint32_t tp;

sys/dev/ic/qwxvar.h

579

volatile uint32_t *hp_addr;

sys/dev/ic/qwxvar.h

582

uint32_t cached_hp;

sys/dev/ic/qwxvar.h

588

uint32_t *tp_addr;

sys/dev/ic/qwxvar.h

591

uint32_t loop_cnt;

sys/dev/ic/qwxvar.h

597

uint32_t last_hp;

sys/dev/ic/qwxvar.h

602

uint32_t hp;

sys/dev/ic/qwxvar.h

605

uint32_t reap_hp;

sys/dev/ic/qwxvar.h

608

uint32_t *tp_addr;

sys/dev/ic/qwxvar.h

611

uint32_t cached_tp;

sys/dev/ic/qwxvar.h

617

uint32_t *hp_addr;

sys/dev/ic/qwxvar.h

620

uint32_t low_threshold;

sys/dev/ic/qwxvar.h

623

uint32_t last_tp;

sys/dev/ic/qwxvar.h

658

uint32_t reg_start[HAL_SRNG_NUM_REG_GRP];

sys/dev/ic/qwxvar.h

662

uint32_t max_size;

sys/dev/ic/qwxvar.h

671

uint32_t timestamp;

sys/dev/ic/qwxvar.h

677

uint32_t pn[4];

sys/dev/ic/qwxvar.h

678

uint32_t last_rx_queue_ts;

sys/dev/ic/qwxvar.h

679

uint32_t last_rx_dequeue_ts;

sys/dev/ic/qwxvar.h

680

uint32_t rx_bitmap[8]; /* Bitmap from 0-255 */

sys/dev/ic/qwxvar.h

681

uint32_t curr_mpdu_cnt;

sys/dev/ic/qwxvar.h

682

uint32_t curr_msdu_cnt;

sys/dev/ic/qwxvar.h

685

uint32_t frames_in_order_cnt;

sys/dev/ic/qwxvar.h

686

uint32_t num_mpdu_processed_cnt;

sys/dev/ic/qwxvar.h

687

uint32_t num_msdu_processed_cnt;

sys/dev/ic/qwxvar.h

688

uint32_t total_num_processed_byte_cnt;

sys/dev/ic/qwxvar.h

689

uint32_t late_rx_mpdu_cnt;

sys/dev/ic/qwxvar.h

690

uint32_t reorder_hole_cnt;

sys/dev/ic/qwxvar.h

742

uint32_t link_desc_counter0;

sys/dev/ic/qwxvar.h

743

uint32_t link_desc_counter1;

sys/dev/ic/qwxvar.h

744

uint32_t link_desc_counter2;

sys/dev/ic/qwxvar.h

745

uint32_t link_desc_counter_sum;

sys/dev/ic/qwxvar.h

775

uint32_t *vaddr;

sys/dev/ic/qwxvar.h

782

uint32_t *vaddr;

sys/dev/ic/qwxvar.h

792

uint32_t shadow_reg_addr[HAL_SHADOW_NUM_REGS];

sys/dev/ic/qwxvar.h

813

uint32_t ie1_reg_addr;

sys/dev/ic/qwxvar.h

814

uint32_t ie2_reg_addr;

sys/dev/ic/qwxvar.h

815

uint32_t ie3_reg_addr;

sys/dev/ic/qwxvar.h

819

uint32_t base;

sys/dev/ic/qwxvar.h

820

uint32_t size;

sys/dev/ic/qwxvar.h

879

uint32_t cipher;

sys/dev/ic/qwxvar.h

912

uint32_t hal_ring_id;

sys/dev/ic/qwxvar.h

941

uint32_t msdu_id;

sys/dev/ic/qwz.c

10029

uint32_t num_mac_addr;

sys/dev/ic/qwz.c

1012

qwz_hal_reo_hw_setup(struct qwz_softc *sc, uint32_t ring_hash_map)

sys/dev/ic/qwz.c

10139

qwz_wmi_vdev_resp_print(uint32_t vdev_resp_status)

sys/dev/ic/qwz.c

1014

uint32_t reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;

sys/dev/ic/qwz.c

1015

uint32_t val;

sys/dev/ic/qwz.c

10199

uint32_t status;

sys/dev/ic/qwz.c

10223

uint32_t *vdev_id)

sys/dev/ic/qwz.c

10254

uint32_t vdev_id = 0;

sys/dev/ic/qwz.c

10310

uint32_t num_reg_rules, struct cur_reg_rule *reg_rule_ptr)

sys/dev/ic/qwz.c

10313

uint32_t count;

sys/dev/ic/qwz.c

10329

qwz_create_reg_rules_from_wmi(uint32_t num_reg_rules,

sys/dev/ic/qwz.c

10333

uint32_t count;

sys/dev/ic/qwz.c

10365

uint32_t num_2ghz_reg_rules, num_5ghz_reg_rules;

sys/dev/ic/qwz.c

1086

uint32_t

sys/dev/ic/qwz.c

10877

qwz_wmi_event_scan_foreign_chan(struct qwz_softc *sc, uint32_t freq)

sys/dev/ic/qwz.c

10995

qwz_pull_chan_info_ev(struct qwz_softc *sc, uint8_t *evt_buf, uint32_t len,

sys/dev/ic/qwz.c

11040

uint32_t cc_freq_hz = sc->cc_freq_hz;

sys/dev/ic/qwz.c

114

uint32_t qwz_debug = 0

sys/dev/ic/qwz.c

11438

qwz_mac_handle_beacon_miss(struct qwz_softc *sc, uint32_t vdev_id)

sys/dev/ic/qwz.c

1156

uint32_t

sys/dev/ic/qwz.c

11740

qwz_connect_pdev_htc_service(struct qwz_softc *sc, uint32_t pdev_idx)

sys/dev/ic/qwz.c

11743

uint32_t svc_id[] = { ATH12K_HTC_SVC_ID_WMI_CONTROL,

sys/dev/ic/qwz.c

11777

uint32_t i;

sys/dev/ic/qwz.c

1197

uint32_t

sys/dev/ic/qwz.c

1204

uint32_t

sys/dev/ic/qwz.c

1213

uint32_t info = le32toh(desc->u.wcn7850.msdu_end.info10);

sys/dev/ic/qwz.c

12284

uint32_t svc_id[] = {

sys/dev/ic/qwz.c

1236

uint32_t

sys/dev/ic/qwz.c

12386

qwz_dp_get_mac_addr(uint32_t addr_l32, uint16_t addr_h16, uint8_t *addr)

sys/dev/ic/qwz.c

1239

uint32_t info = le32toh(desc->u.wcn7850.msdu_end.info13);

sys/dev/ic/qwz.c

12394

uint32_t val32;

sys/dev/ic/qwz.c

1240

uint32_t errmap = 0;

sys/dev/ic/qwz.c

12491

*(uint32_t *)resp);

sys/dev/ic/qwz.c

1266

uint32_t qwz_hw_wcn7850_get_rx_desc_size(void)

sys/dev/ic/qwz.c

12744

qwz_hal_rx_buf_addr_info_set(void *desc, uint64_t paddr, uint32_t cookie,

sys/dev/ic/qwz.c

12748

uint32_t paddr_lo, paddr_hi;

sys/dev/ic/qwz.c

12759

qwz_hal_rx_buf_addr_info_get(void *desc, uint64_t *paddr, uint32_t *cookie,

sys/dev/ic/qwz.c

12880

uint32_t *desc;

sys/dev/ic/qwz.c

12886

uint32_t cookie;

sys/dev/ic/qwz.c

12995

struct dp_rxdma_mon_ring *rx_ring, uint32_t ringtype)

sys/dev/ic/qwz.c

13072

qwz_dp_tx_get_ring_id_type(struct qwz_softc *sc, int mac_id, uint32_t ring_id,

sys/dev/ic/qwz.c

13127

qwz_dp_tx_htt_srng_setup(struct qwz_softc *sc, uint32_t ring_id, int mac_id,

sys/dev/ic/qwz.c

13134

uint32_t ring_entry_sz;

sys/dev/ic/qwz.c

13235

qwz_dp_tx_htt_h2t_ppdu_stats_req(struct qwz_softc *sc, uint32_t mask,

sys/dev/ic/qwz.c

13272

qwz_dp_tx_htt_rx_filter_setup(struct qwz_softc *sc, uint32_t ring_id,

sys/dev/ic/qwz.c

13342

uint32_t ring_id;

sys/dev/ic/qwz.c

13551

uint8_t mac_id, uint32_t msdu_id, struct dp_tx_ring *tx_ring)

sys/dev/ic/qwz.c

13667

uint32_t msdu_id, struct hal_tx_status *ts)

sys/dev/ic/qwz.c

137

int qwz_wmi_set_peer_param(struct qwz_softc *, uint8_t *, uint32_t,

sys/dev/ic/qwz.c

13708

uint32_t *desc;

sys/dev/ic/qwz.c

13709

uint32_t msdu_id;

sys/dev/ic/qwz.c

13739

uint32_t desc_id;

sys/dev/ic/qwz.c

13792

uint32_t *desc_bank)

sys/dev/ic/qwz.c

138

uint32_t, uint32_t, uint32_t);

sys/dev/ic/qwz.c

13804

qwz_hal_desc_reo_parse_err(struct qwz_softc *sc, uint32_t *rx_desc,

sys/dev/ic/qwz.c

13805

uint64_t *paddr, uint32_t *desc_bank)

sys/dev/ic/qwz.c

13838

qwz_hal_rx_msdu_link_info_get(void *link_desc, uint32_t *num_msdus,

sys/dev/ic/qwz.c

13839

uint32_t *msdu_cookies, enum hal_rx_buf_return_buf_manager *rbm)

sys/dev/ic/qwz.c

13881

qwz_dp_rx_link_desc_return(struct qwz_softc *sc, uint32_t *link_desc,

sys/dev/ic/qwz.c

13886

uint32_t *desc;

sys/dev/ic/qwz.c

13914

uint32_t *ring_desc)

sys/dev/ic/qwz.c

13927

qwz_dp_process_rx_err_buf(struct qwz_softc *sc, uint32_t *ring_desc,

sys/dev/ic/qwz.c

13937

uint32_t hal_rx_desc_sz = sc->hw_params.hal_desc_sz;

sys/dev/ic/qwz.c

13984

uint32_t msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];

sys/dev/ic/qwz.c

13991

uint32_t desc_bank, num_msdus;

sys/dev/ic/qwz.c

13997

uint32_t *desc;

sys/dev/ic/qwz.c

140

uint8_t *, uint64_t, uint8_t, uint8_t, uint32_t);

sys/dev/ic/qwz.c

14244

uint32_t *rx_desc;

sys/dev/ic/qwz.c

14380

static inline uint32_t

sys/dev/ic/qwz.c

14392

uint32_t

sys/dev/ic/qwz.c

14419

uint32_t meta_data;

sys/dev/ic/qwz.c

14580

uint32_t err_bitmap;

sys/dev/ic/qwz.c

14669

uint32_t hal_rx_desc_sz = sc->hw_params.hal_desc_sz;

sys/dev/ic/qwz.c

14792

uint32_t cookie;

sys/dev/ic/qwz.c

14971

uint32_t cookie;

sys/dev/ic/qwz.c

15090

uint32_t rx_buf_sz;

sys/dev/ic/qwz.c

15234

uint32_t msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];

sys/dev/ic/qwz.c

15242

uint32_t cookie;

sys/dev/ic/qwz.c

15243

uint32_t desc_bank;

sys/dev/ic/qwz.c

15314

qwz_hal_reo_status_queue_stats(struct qwz_softc *sc, uint32_t *reo_desc,

sys/dev/ic/qwz.c

15380

qwz_hal_reo_flush_queue_status(struct qwz_softc *sc, uint32_t *reo_desc,

sys/dev/ic/qwz.c

15396

qwz_hal_reo_flush_cache_status(struct qwz_softc *sc, uint32_t *reo_desc,

sys/dev/ic/qwz.c

15434

qwz_hal_reo_unblk_cache_status(struct qwz_softc *sc, uint32_t *reo_desc,

sys/dev/ic/qwz.c

15459

qwz_hal_reo_flush_timeout_list_status(struct qwz_softc *ab, uint32_t *reo_desc,

sys/dev/ic/qwz.c

15483

qwz_hal_reo_desc_thresh_reached_status(struct qwz_softc *sc, uint32_t *reo_desc,

sys/dev/ic/qwz.c

15513

qwz_hal_reo_update_rx_reo_queue_status(struct qwz_softc *ab, uint32_t *reo_desc,

sys/dev/ic/qwz.c

15533

uint32_t *reo_desc;

sys/dev/ic/qwz.c

15713

uint32_t round_len = roundup(len, 4);

sys/dev/ic/qwz.c

15724

uint32_t cmd_id)

sys/dev/ic/qwz.c

15728

uint32_t cmd = 0;

sys/dev/ic/qwz.c

15741

qwz_wmi_cmd_send(struct qwz_pdev_wmi *wmi, struct mbuf *m, uint32_t cmd_id)

sys/dev/ic/qwz.c

15780

qwz_wmi_pdev_set_param(struct qwz_softc *sc, uint32_t param_id,

sys/dev/ic/qwz.c

15781

uint32_t param_value, uint8_t pdev_id)

sys/dev/ic/qwz.c

15833

arc4random_buf(cmd->th_4, sizeof(uint32_t) * ATH12K_IPV4_TH_SEED_SIZE);

sys/dev/ic/qwz.c

15834

arc4random_buf(cmd->th_6, sizeof(uint32_t) * ATH12K_IPV6_TH_SEED_SIZE);

sys/dev/ic/qwz.c

15892

qwz_wmi_send_dfs_phyerr_offload_enable_cmd(struct qwz_softc *sc, uint32_t pdev_id)

sys/dev/ic/qwz.c

15943

uint32_t *reg1, *reg2;

sys/dev/ic/qwz.c

16186

uint32_t *tmp_ptr;

sys/dev/ic/qwz.c

16195

len += params->num_chan * sizeof(uint32_t);

sys/dev/ic/qwz.c

16218

sizeof(uint32_t));

sys/dev/ic/qwz.c

16268

len = params->num_chan * sizeof(uint32_t);

sys/dev/ic/qwz.c

16274

tmp_ptr = (uint32_t *)ptr;

sys/dev/ic/qwz.c

16515

int key_len_aligned = roundup(arg->key_len, sizeof(uint32_t));

sys/dev/ic/qwz.c

16659

uint32_t peer_legacy_rates_align;

sys/dev/ic/qwz.c

16660

uint32_t peer_ht_rates_align;

sys/dev/ic/qwz.c

16664

sizeof(uint32_t));

sys/dev/ic/qwz.c

16666

sizeof(uint32_t));

sys/dev/ic/qwz.c

16899

uint32_t hw_mode_len = 0;

sys/dev/ic/qwz.c

17090

qwz_wmi_set_sta_ps_param(struct qwz_softc *sc, uint32_t vdev_id,

sys/dev/ic/qwz.c

17091

uint8_t pdev_id, uint32_t param, uint32_t param_value)

sys/dev/ic/qwz.c

17131

uint32_t buf_id, struct mbuf *frame, struct qwz_tx_data *tx_data)

sys/dev/ic/qwz.c

17137

uint32_t buf_len;

sys/dev/ic/qwz.c

17275

qwz_wmi_vdev_set_param_cmd(struct qwz_softc *sc, uint32_t vdev_id,

sys/dev/ic/qwz.c

17276

uint8_t pdev_id, uint32_t param_id, uint32_t param_value)

sys/dev/ic/qwz.c

17313

qwz_wmi_vdev_up(struct qwz_softc *sc, uint32_t vdev_id, uint32_t pdev_id,

sys/dev/ic/qwz.c

17314

uint32_t aid, const uint8_t *bssid, uint8_t *tx_bssid,

sys/dev/ic/qwz.c

17315

uint32_t nontx_profile_idx, uint32_t nontx_profile_cnt)

sys/dev/ic/qwz.c

17369

qwz_wmi_vdev_down(struct qwz_softc *sc, uint32_t vdev_id, uint8_t pdev_id)

sys/dev/ic/qwz.c

17406

uint32_t center_freq1 = arg->channel.band_center_freq1;

sys/dev/ic/qwz.c

17581

uint32_t

sys/dev/ic/qwz.c

18404

srng->u.dst_ring.tp_addr = (uint32_t *)(

sys/dev/ic/qwz.c

18408

srng->u.src_ring.hp_addr = (uint32_t *)(

sys/dev/ic/qwz.c

18432

uint32_t target_reg;

sys/dev/ic/qwz.c

18488

qwz_hal_srng_get_shadow_config(struct qwz_softc *sc, uint32_t **cfg,

sys/dev/ic/qwz.c

18489

uint32_t *len)

sys/dev/ic/qwz.c

18501

size_t size = sizeof(uint32_t) * HAL_SRNG_RING_ID_MAX;

sys/dev/ic/qwz.c

18536

size_t size = sizeof(uint32_t) *

sys/dev/ic/qwz.c

18606

uint32_t val;

sys/dev/ic/qwz.c

18608

uint32_t reg_base;

sys/dev/ic/qwz.c

18681

uint32_t val;

sys/dev/ic/qwz.c

18683

uint32_t reg_base;

sys/dev/ic/qwz.c

18787

uint32_t addr;

sys/dev/ic/qwz.c

18788

uint32_t val;

sys/dev/ic/qwz.c

18802

qwz_hal_ce_src_set_desc(void *buf, uint64_t paddr, uint32_t len, uint32_t id,

sys/dev/ic/qwz.c

18829

uint32_t

sys/dev/ic/qwz.c

18834

uint32_t len;

sys/dev/ic/qwz.c

18851

uint32_t lmac_idx;

sys/dev/ic/qwz.c

18853

uint32_t reg_base;

sys/dev/ic/qwz.c

18906

(uint32_t *)((unsigned long)sc->mem +

sys/dev/ic/qwz.c

18936

(uint32_t *)((unsigned long)sc->mem +

sys/dev/ic/qwz.c

18995

uint32_t *desc;

sys/dev/ic/qwz.c

19168

uint32_t message_id, trailer_len = 0;

sys/dev/ic/qwz.c

1954

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

19566

qwz_ce_get_shadow_config(struct qwz_softc *sc, uint32_t **shadow_cfg,

sys/dev/ic/qwz.c

19567

uint32_t *shadow_cfg_len)

sys/dev/ic/qwz.c

19631

qwz_get_ce_msi_idx(struct qwz_softc *sc, uint32_t ce_id,

sys/dev/ic/qwz.c

19632

uint32_t *msi_data_idx)

sys/dev/ic/qwz.c

19638

qwz_ce_srng_msi_ring_params_setup(struct qwz_softc *sc, uint32_t ce_id,

sys/dev/ic/qwz.c

19641

uint32_t msi_data_start = 0;

sys/dev/ic/qwz.c

19642

uint32_t msi_data_count = 1, msi_data_idx;

sys/dev/ic/qwz.c

19643

uint32_t msi_irq_start = 0;

sys/dev/ic/qwz.c

19644

uint32_t addr_lo;

sys/dev/ic/qwz.c

19645

uint32_t addr_hi;

sys/dev/ic/qwz.c

19670

params.ring_base_vaddr = (uint32_t *)ce_ring->base_addr;

sys/dev/ic/qwz.c

19785

uint32_t tp, hp;

sys/dev/ic/qwz.c

19812

uint32_t *desc;

sys/dev/ic/qwz.c

19826

srng->entry_size * sizeof(uint32_t), BUS_DMASYNC_POSTREAD);

sys/dev/ic/qwz.c

19851

srng->entry_size * sizeof(uint32_t), BUS_DMASYNC_PREREAD);

sys/dev/ic/qwz.c

19956

uint32_t *desc;

sys/dev/ic/qwz.c

20074

uint32_t *desc;

sys/dev/ic/qwz.c

20160

qwz_get_num_chains(uint32_t mask)

sys/dev/ic/qwz.c

20174

qwz_set_antenna(struct qwz_pdev *pdev, uint32_t tx_ant, uint32_t rx_ant)

sys/dev/ic/qwz.c

20366

uint32_t param;

sys/dev/ic/qwz.c

20367

uint32_t min_tx_power = sc->target_caps.hw_min_tx_power;

sys/dev/ic/qwz.c

20368

uint32_t max_tx_power = sc->target_caps.hw_max_tx_power;

sys/dev/ic/qwz.c

20523

uint32_t *flags, uint32_t *tx_vdev_id)

sys/dev/ic/qwz.c

20574

uint32_t param_id, param_value;

sys/dev/ic/qwz.c

20889

uint32_t param_id, param_value;

sys/dev/ic/qwz.c

21285

uint32_t preamble;

sys/dev/ic/qwz.c

21352

qwz_peer_delete(struct qwz_softc *sc, uint32_t vdev_id, uint8_t pdev_id,

sys/dev/ic/qwz.c

21562

uint32_t

sys/dev/ic/qwz.c

21563

qwz_hal_reo_qdesc_size(uint32_t ba_window_size, uint8_t tid)

sys/dev/ic/qwz.c

21565

uint32_t num_ext_desc;

sys/dev/ic/qwz.c

21585

qwz_hal_reo_set_desc_hdr(struct hal_desc_header *hdr, uint8_t owner, uint8_t buffer_type, uint32_t magic)

sys/dev/ic/qwz.c

21595

qwz_hal_reo_qdesc_setup(void *vaddr, int tid, uint32_t ba_window_size,

sys/dev/ic/qwz.c

21596

uint32_t start_seq, enum hal_pn_type type)

sys/dev/ic/qwz.c

2169

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

2187

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

21904

struct dp_rx_tid *rx_tid, uint32_t ba_win_sz, uint16_t ssn,

sys/dev/ic/qwz.c

21962

int vdev_id, int pdev_id, uint8_t tid, uint32_t ba_win_sz, uint16_t ssn,

sys/dev/ic/qwz.c

21968

uint32_t hw_desc_sz;

sys/dev/ic/qwz.c

22079

uint32_t reo_dest;

sys/dev/ic/qwz.c

2214

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

22278

uint32_t ring_selector = 0;

sys/dev/ic/qwz.c

22640

uint32_t vdev_id, uint32_t pdev_id, uint32_t param_id, uint32_t param_val)

sys/dev/ic/qwz.c

22680

uint8_t ba_window_size_valid, uint32_t ba_window_size)

sys/dev/ic/qwz.c

22855

uint32_t scan_timeout;

sys/dev/ic/qwz.c

23071

uint32_t vdev_id, uint32_t pdev_id)

sys/dev/ic/qwz.c

23075

uint32_t vdev_param;

sys/dev/ic/qwz.c

23114

uint32_t param_id;

sys/dev/ic/qwz.c

2376

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

2671

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

2714

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

2738

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

2815

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

2900

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

2909

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

2926

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

2943

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

2985

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

3141

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

3159

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

3177

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

3195

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

3230

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

3301

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

3319

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

3426

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

3503

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

3521

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

3530

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

3539

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

3556

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

3574

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

3615

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

3632

.elem_size = sizeof(uint32_t),

sys/dev/ic/qwz.c

4106

if (ei->elem_size != sizeof(uint32_t)) {

sys/dev/ic/qwz.c

4132

qwz_qmi_decode_datalen(struct qwz_softc *sc, size_t *used, uint32_t *datalen,

sys/dev/ic/qwz.c

4253

uint32_t min_size;

sys/dev/ic/qwz.c

4275

uint32_t datalen;

sys/dev/ic/qwz.c

4417

uint32_t nelem = 1, i;

sys/dev/ic/qwz.c

5155

uint32_t pad = 0;

sys/dev/ic/qwz.c

5221

uint32_t pad = 0;

sys/dev/ic/qwz.c

5240

uint32_t type, size, hdrsize;

sys/dev/ic/qwz.c

5314

qwz_qmi_encode_datalen(uint8_t *p, uint32_t *datalen,

sys/dev/ic/qwz.c

5317

memcpy(datalen, input + ei->offset, sizeof(uint32_t));

sys/dev/ic/qwz.c

5372

uint32_t val;

sys/dev/ic/qwz.c

5544

uint32_t datalen = 0;

sys/dev/ic/qwz.c

5604

uint32_t datalen = 0;

sys/dev/ic/qwz.c

5785

uint32_t pad = 0;

sys/dev/ic/qwz.c

5955

uint32_t mem_seg_len;

sys/dev/ic/qwz.c

612

uint8_t *macaddr, struct ieee80211_key *k, uint32_t flags,

sys/dev/ic/qwz.c

6256

uint32_t id;

sys/dev/ic/qwz.c

6257

uint32_t len;

sys/dev/ic/qwz.c

6555

uint32_t remaining = len;

sys/dev/ic/qwz.c

6641

uint32_t fw_size;

sys/dev/ic/qwz.c

6744

uint32_t size;

sys/dev/ic/qwz.c

6790

qwz_hal_srng_get_entrysize(struct qwz_softc *sc, uint32_t ring_type)

sys/dev/ic/qwz.c

6800

uint32_t

sys/dev/ic/qwz.c

6801

qwz_hal_srng_get_max_entries(struct qwz_softc *sc, uint32_t ring_type)

sys/dev/ic/qwz.c

6811

uint32_t *

sys/dev/ic/qwz.c

6814

uint32_t *desc;

sys/dev/ic/qwz.c

6835

uint32_t tp, hp;

sys/dev/ic/qwz.c

6854

uint32_t *

sys/dev/ic/qwz.c

6857

uint32_t *desc;

sys/dev/ic/qwz.c

6871

uint32_t *

sys/dev/ic/qwz.c

6885

qwz_get_msi_address(struct qwz_softc *sc, uint32_t *addr_lo,

sys/dev/ic/qwz.c

6886

uint32_t *addr_hi)

sys/dev/ic/qwz.c

6974

uint32_t msi_data_start = 0;

sys/dev/ic/qwz.c

6975

uint32_t msi_data_count = 1;

sys/dev/ic/qwz.c

6976

uint32_t msi_irq_start = 0;

sys/dev/ic/qwz.c

6977

uint32_t addr_lo;

sys/dev/ic/qwz.c

6978

uint32_t addr_hi;

sys/dev/ic/qwz.c

698

uint32_t flags = 0;

sys/dev/ic/qwz.c

7011

uint32_t max_entries = qwz_hal_srng_get_max_entries(sc, type);

sys/dev/ic/qwz.c

7106

*(volatile uint32_t *)srng->u.src_ring.tp_addr;

sys/dev/ic/qwz.c

7125

*(volatile uint32_t *)srng->u.src_ring.tp_addr;

sys/dev/ic/qwz.c

7134

*(volatile uint32_t *)srng->u.src_ring.tp_addr;

sys/dev/ic/qwz.c

7151

qwz_wbm_idle_ring_setup(struct qwz_softc *sc, uint32_t *n_link_desc)

sys/dev/ic/qwz.c

7154

uint32_t n_mpdu_link_desc, n_mpdu_queue_desc;

sys/dev/ic/qwz.c

7155

uint32_t n_tx_msdu_link_desc, n_rx_msdu_link_desc;

sys/dev/ic/qwz.c

7239

uint32_t nsbufs, uint32_t tot_link_desc, uint32_t end_offset)

sys/dev/ic/qwz.c

7243

uint32_t reg_scatter_buf_sz = HAL_WBM_IDLE_SCATTER_BUF_SIZE / 64;

sys/dev/ic/qwz.c

7244

uint32_t val;

sys/dev/ic/qwz.c

7316

qwz_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, uint32_t cookie,

sys/dev/ic/qwz.c

7347

uint32_t n_link_desc_bank, uint32_t n_link_desc, uint32_t last_bank_sz)

sys/dev/ic/qwz.c

7352

uint32_t n_entries_per_buf;

sys/dev/ic/qwz.c

7360

uint32_t end_offset;

sys/dev/ic/qwz.c

7361

uint32_t cookie;

sys/dev/ic/qwz.c

7425

uint32_t next_hp;

sys/dev/ic/qwz.c

7455

uint32_t *

sys/dev/ic/qwz.c

7458

uint32_t *desc;

sys/dev/ic/qwz.c

7459

uint32_t next_reap_hp;

sys/dev/ic/qwz.c

7477

struct dp_link_desc_bank *link_desc_banks, uint32_t ring_type,

sys/dev/ic/qwz.c

7478

struct hal_srng *srng, uint32_t n_link_desc)

sys/dev/ic/qwz.c

7480

uint32_t tot_mem_sz;

sys/dev/ic/qwz.c

7481

uint32_t n_link_desc_bank, last_bank_sz;

sys/dev/ic/qwz.c

7482

uint32_t entry_sz, n_entries;

sys/dev/ic/qwz.c

7484

uint32_t *desc;

sys/dev/ic/qwz.c

7486

uint32_t cookie;

sys/dev/ic/qwz.c

7661

uint32_t ctrl_reg_val;

sys/dev/ic/qwz.c

7662

uint32_t addr;

sys/dev/ic/qwz.c

7665

uint32_t value;

sys/dev/ic/qwz.c

7704

sc->ops.write32(sc, addr, *(uint32_t *)&hw_map_val[i]);

sys/dev/ic/qwz.c

8069

uint32_t ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |

sys/dev/ic/qwz.c

8089

struct dp_link_desc_bank *desc_bank, uint32_t ring_type,

sys/dev/ic/qwz.c

8155

uint32_t cmem_base;

sys/dev/ic/qwz.c

8186

uint32_t cmem_base = sc->qmi_dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start;

sys/dev/ic/qwz.c

8187

uint32_t reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;

sys/dev/ic/qwz.c

8188

uint32_t wbm_base = HAL_SEQ_WCSS_UMAC_WBM_REG;

sys/dev/ic/qwz.c

8189

uint32_t val = 0;

sys/dev/ic/qwz.c

8228

uint32_t qwz_dp_cc_cookie_gen(uint16_t ppt_idx, uint16_t spt_idx)

sys/dev/ic/qwz.c

8230

return (uint32_t)ppt_idx << ATH12K_CC_PPT_SHIFT | spt_idx;

sys/dev/ic/qwz.c

8247

uint32_t i, j, pool_id, tx_spt_page;

sys/dev/ic/qwz.c

8248

uint32_t ppt_idx;

sys/dev/ic/qwz.c

8331

uint32_t i, j, pool_id, tx_spt_page;

sys/dev/ic/qwz.c

8486

int qwz_dp_rxdma_mon_ring_buf_setup(struct qwz_softc *, struct dp_rxdma_mon_ring *, uint32_t);

sys/dev/ic/qwz.c

8624

uint32_t n_link_desc = 0;

sys/dev/ic/qwz.c

8874

sizeof(uint32_t) * req->shadow_reg_v3_len);

sys/dev/ic/qwz.c

9053

uint32_t *wmi_ext2_service_bitmap;

sys/dev/ic/qwz.c

9079

wmi_ext2_service_bitmap = (uint32_t *)ptr;

sys/dev/ic/qwz.c

9258

const uint32_t *wmi_svc_bm)

sys/dev/ic/qwz.c

9286

expect_len = WMI_SERVICE_BM_SIZE * sizeof(uint32_t);

sys/dev/ic/qwz.c

9353

uint32_t phy_map;

sys/dev/ic/qwz.c

9354

uint32_t hw_idx, phy_idx = 0;

sys/dev/ic/qwz.c

9433

sizeof(uint32_t) * PSOC_HOST_MAX_PHY_SIZE);

sys/dev/ic/qwz.c

9447

sizeof(uint32_t) * PSOC_HOST_MAX_PHY_SIZE);

sys/dev/ic/qwz.c

9474

uint32_t phy_id_map;

sys/dev/ic/qwz.c

9526

uint32_t phy_map = 0;

sys/dev/ic/qwz.c

9568

uint32_t i;

sys/dev/ic/qwz.c

9685

uint32_t i;

sys/dev/ic/qwz.c

9728

qwz_wmi_alloc_dbring_caps(struct qwz_softc *sc, uint32_t num_cap)

sys/dev/ic/qwz.c

9760

uint32_t i;

sys/dev/ic/qwzreg.h

10009

uint32_t queue_addr_lo;

sys/dev/ic/qwzreg.h

10010

uint32_t info0;

sys/dev/ic/qwzreg.h

10011

uint32_t info1;

sys/dev/ic/qwzreg.h

10012

uint32_t info2;

sys/dev/ic/qwzreg.h

10013

uint32_t pn[4];

sys/dev/ic/qwzreg.h

10021

uint32_t info0;

sys/dev/ic/qwzreg.h

10022

uint32_t rsvd[7];

sys/dev/ic/qwzreg.h

10045

uint32_t info0;

sys/dev/ic/qwzreg.h

10046

uint32_t timestamp;

sys/dev/ic/qwzreg.h

10088

uint32_t info0;

sys/dev/ic/qwzreg.h

10089

uint32_t pn[4];

sys/dev/ic/qwzreg.h

10090

uint32_t last_rx_enqueue_timestamp;

sys/dev/ic/qwzreg.h

10091

uint32_t last_rx_dequeue_timestamp;

sys/dev/ic/qwzreg.h

10092

uint32_t rx_bitmap[8];

sys/dev/ic/qwzreg.h

10093

uint32_t info1;

sys/dev/ic/qwzreg.h

10094

uint32_t info2;

sys/dev/ic/qwzreg.h

10095

uint32_t info3;

sys/dev/ic/qwzreg.h

10096

uint32_t num_mpdu_frames;

sys/dev/ic/qwzreg.h

10097

uint32_t num_msdu_frames;

sys/dev/ic/qwzreg.h

10098

uint32_t total_bytes;

sys/dev/ic/qwzreg.h

10099

uint32_t info4;

sys/dev/ic/qwzreg.h

10100

uint32_t info5;

sys/dev/ic/qwzreg.h

10183

uint32_t info0;

sys/dev/ic/qwzreg.h

10184

uint32_t rsvd0[21];

sys/dev/ic/qwzreg.h

10185

uint32_t info1;

sys/dev/ic/qwzreg.h

10218

uint32_t info0;

sys/dev/ic/qwzreg.h

10219

uint32_t rsvd0[21];

sys/dev/ic/qwzreg.h

10220

uint32_t info1;

sys/dev/ic/qwzreg.h

10280

uint32_t info0;

sys/dev/ic/qwzreg.h

10281

uint32_t rsvd0[21];

sys/dev/ic/qwzreg.h

10282

uint32_t info1;

sys/dev/ic/qwzreg.h

10316

uint32_t info0;

sys/dev/ic/qwzreg.h

10317

uint32_t info1;

sys/dev/ic/qwzreg.h

10318

uint32_t rsvd0[20];

sys/dev/ic/qwzreg.h

10319

uint32_t info2;

sys/dev/ic/qwzreg.h

10359

uint32_t info0;

sys/dev/ic/qwzreg.h

10360

uint32_t info1;

sys/dev/ic/qwzreg.h

10361

uint32_t info2;

sys/dev/ic/qwzreg.h

10362

uint32_t info3;

sys/dev/ic/qwzreg.h

10363

uint32_t info4;

sys/dev/ic/qwzreg.h

10364

uint32_t rsvd0[17];

sys/dev/ic/qwzreg.h

10365

uint32_t info5;

sys/dev/ic/qwzreg.h

10391

uint32_t buffer_addr;

sys/dev/ic/qwzreg.h

10392

uint32_t info0;

sys/dev/ic/qwzreg.h

10396

uint32_t paddr_lo;

sys/dev/ic/qwzreg.h

10397

uint32_t paddr_hi;

sys/dev/ic/qwzreg.h

10415

uint32_t cookie;

sys/dev/ic/qwzreg.h

10416

uint32_t reserved;

sys/dev/ic/qwzreg.h

10417

uint32_t ppdu_id;

sys/dev/ic/qwzreg.h

10418

uint32_t info0;

sys/dev/ic/qwzreg.h

10518

uint32_t service_id;

sys/dev/ic/qwzreg.h

10519

uint32_t pipedir;

sys/dev/ic/qwzreg.h

10520

uint32_t pipenum;

sys/dev/ic/qwzreg.h

10530

uint32_t pipenum;

sys/dev/ic/qwzreg.h

10531

uint32_t pipedir;

sys/dev/ic/qwzreg.h

10532

uint32_t nentries;

sys/dev/ic/qwzreg.h

10533

uint32_t nbytes_max;

sys/dev/ic/qwzreg.h

10534

uint32_t flags;

sys/dev/ic/qwzreg.h

10535

uint32_t reserved;

sys/dev/ic/qwzreg.h

10584

uint32_t htc_info;

sys/dev/ic/qwzreg.h

10585

uint32_t ctrl_info;

sys/dev/ic/qwzreg.h

10625

uint32_t id_credit_count;

sys/dev/ic/qwzreg.h

10626

uint32_t size_ep;

sys/dev/ic/qwzreg.h

10631

uint32_t ver_bundle;

sys/dev/ic/qwzreg.h

10635

uint32_t msg_svc_id;

sys/dev/ic/qwzreg.h

10636

uint32_t flags_len;

sys/dev/ic/qwzreg.h

10640

uint32_t msg_svc_id;

sys/dev/ic/qwzreg.h

10641

uint32_t flags_len;

sys/dev/ic/qwzreg.h

10642

uint32_t svc_meta_pad;

sys/dev/ic/qwzreg.h

10648

uint32_t msg_id;

sys/dev/ic/qwzreg.h

10649

uint32_t flags;

sys/dev/ic/qwzreg.h

10650

uint32_t max_msgs_per_bundled_recv;

sys/dev/ic/qwzreg.h

10654

uint32_t msg_svc_id;

sys/dev/ic/qwzreg.h

10655

uint32_t flags_len;

sys/dev/ic/qwzreg.h

10981

uint32_t info0;

sys/dev/ic/qwzreg.h

10982

uint32_t reo_queue_desc_lo;

sys/dev/ic/qwzreg.h

10983

uint32_t info1;

sys/dev/ic/qwzreg.h

10984

uint32_t pn[4];

sys/dev/ic/qwzreg.h

10985

uint32_t info2;

sys/dev/ic/qwzreg.h

10986

uint32_t peer_meta_data;

sys/dev/ic/qwzreg.h

10991

uint32_t info4;

sys/dev/ic/qwzreg.h

10992

uint32_t info5;

sys/dev/ic/qwzreg.h

10993

uint32_t info6;

sys/dev/ic/qwzreg.h

11002

uint32_t ht_ctrl;

sys/dev/ic/qwzreg.h

11003

uint32_t info7;

sys/dev/ic/qwzreg.h

11006

uint32_t info8;

sys/dev/ic/qwzreg.h

11007

uint32_t res0;

sys/dev/ic/qwzreg.h

11008

uint32_t res1;

sys/dev/ic/qwzreg.h

11045

uint32_t info1;

sys/dev/ic/qwzreg.h

11046

uint32_t pn[4];

sys/dev/ic/qwzreg.h

11047

uint32_t info2;

sys/dev/ic/qwzreg.h

11048

uint32_t peer_meta_data;

sys/dev/ic/qwzreg.h

11053

uint32_t info4;

sys/dev/ic/qwzreg.h

11054

uint32_t info5;

sys/dev/ic/qwzreg.h

11055

uint32_t info6;

sys/dev/ic/qwzreg.h

114

uint32_t cmd_id;

sys/dev/ic/qwzreg.h

11667

uint32_t rule_indication0;

sys/dev/ic/qwzreg.h

11668

uint32_t ipv6_options_crc;

sys/dev/ic/qwzreg.h

11671

uint32_t rule_indication1;

sys/dev/ic/qwzreg.h

11672

uint32_t tcp_seq_num;

sys/dev/ic/qwzreg.h

11673

uint32_t tcp_ack_num;

sys/dev/ic/qwzreg.h

11680

uint32_t info6;

sys/dev/ic/qwzreg.h

11681

uint32_t fse_metadata;

sys/dev/ic/qwzreg.h

11686

uint32_t info8;

sys/dev/ic/qwzreg.h

11687

uint32_t info9;

sys/dev/ic/qwzreg.h

11688

uint32_t info10;

sys/dev/ic/qwzreg.h

11689

uint32_t info11;

sys/dev/ic/qwzreg.h

11692

uint32_t peer_meta_data;

sys/dev/ic/qwzreg.h

11693

uint32_t info12;

sys/dev/ic/qwzreg.h

11694

uint32_t flow_id_toeplitz;

sys/dev/ic/qwzreg.h

11695

uint32_t ppdu_start_timestamp_63_32;

sys/dev/ic/qwzreg.h

11696

uint32_t phy_meta_data;

sys/dev/ic/qwzreg.h

11697

uint32_t ppdu_start_timestamp_31_0;

sys/dev/ic/qwzreg.h

11698

uint32_t toeplitz_hash_2_or_4;

sys/dev/ic/qwzreg.h

11701

uint32_t sa_47_16;

sys/dev/ic/qwzreg.h

11702

uint32_t info13;

sys/dev/ic/qwzreg.h

11703

uint32_t info14;

sys/dev/ic/qwzreg.h

11742

uint32_t info10;

sys/dev/ic/qwzreg.h

11743

uint32_t info11;

sys/dev/ic/qwzreg.h

11744

uint32_t info12;

sys/dev/ic/qwzreg.h

11745

uint32_t flow_id_toeplitz;

sys/dev/ic/qwzreg.h

11746

uint32_t ppdu_start_timestamp_63_32;

sys/dev/ic/qwzreg.h

11747

uint32_t phy_meta_data;

sys/dev/ic/qwzreg.h

11748

uint32_t info13;

sys/dev/ic/qwzreg.h

11749

uint32_t info14;

sys/dev/ic/qwzreg.h

118

uint32_t header;

sys/dev/ic/qwzreg.h

124

#define TLV_HDR_SIZE sizeof(uint32_t) /* wmi_tlv.header */

sys/dev/ic/qwzreg.h

12437

uint32_t info0;

sys/dev/ic/qwzreg.h

12438

uint32_t info1;

sys/dev/ic/qwzreg.h

12439

uint32_t info2;

sys/dev/ic/qwzreg.h

12440

uint32_t info3;

sys/dev/ic/qwzreg.h

12455

uint32_t ver_reg_info;

sys/dev/ic/qwzreg.h

12623

uint32_t info0;

sys/dev/ic/qwzreg.h

12624

uint32_t ring_base_addr_lo;

sys/dev/ic/qwzreg.h

12625

uint32_t ring_base_addr_hi;

sys/dev/ic/qwzreg.h

12626

uint32_t info1;

sys/dev/ic/qwzreg.h

12627

uint32_t ring_head_off32_remote_addr_lo;

sys/dev/ic/qwzreg.h

12628

uint32_t ring_head_off32_remote_addr_hi;

sys/dev/ic/qwzreg.h

12629

uint32_t ring_tail_off32_remote_addr_lo;

sys/dev/ic/qwzreg.h

12630

uint32_t ring_tail_off32_remote_addr_hi;

sys/dev/ic/qwzreg.h

12631

uint32_t ring_msi_addr_lo;

sys/dev/ic/qwzreg.h

12632

uint32_t ring_msi_addr_hi;

sys/dev/ic/qwzreg.h

12633

uint32_t msi_data;

sys/dev/ic/qwzreg.h

12634

uint32_t intr_info;

sys/dev/ic/qwzreg.h

12635

uint32_t info2;

sys/dev/ic/qwzreg.h

12672

uint32_t msg;

sys/dev/ic/qwzreg.h

13098

uint32_t info0;

sys/dev/ic/qwzreg.h

13099

uint32_t info1;

sys/dev/ic/qwzreg.h

13100

uint32_t pkt_type_en_flags0;

sys/dev/ic/qwzreg.h

13101

uint32_t pkt_type_en_flags1;

sys/dev/ic/qwzreg.h

13102

uint32_t pkt_type_en_flags2;

sys/dev/ic/qwzreg.h

13103

uint32_t pkt_type_en_flags3;

sys/dev/ic/qwzreg.h

13104

uint32_t rx_filter_tlv;

sys/dev/ic/qwzreg.h

13108

uint32_t rx_filter; /* see htt_rx_filter_tlv_flags */

sys/dev/ic/qwzreg.h

13109

uint32_t pkt_filter_flags0; /* MGMT */

sys/dev/ic/qwzreg.h

13110

uint32_t pkt_filter_flags1; /* MGMT */

sys/dev/ic/qwzreg.h

13111

uint32_t pkt_filter_flags2; /* CTRL */

sys/dev/ic/qwzreg.h

13112

uint32_t pkt_filter_flags3; /* DATA */

sys/dev/ic/qwzreg.h

13137

uint32_t info0;

sys/dev/ic/qwzreg.h

13138

uint32_t cfg;

sys/dev/ic/qwzreg.h

13164

uint32_t version;

sys/dev/ic/qwzreg.h

13176

uint32_t info;

sys/dev/ic/qwzreg.h

13177

uint32_t mac_addr_l32;

sys/dev/ic/qwzreg.h

13178

uint32_t info1;

sys/dev/ic/qwzreg.h

13179

uint32_t info2;

sys/dev/ic/qwzreg.h

13190

uint32_t info;

sys/dev/ic/qwzreg.h

13191

uint32_t mac_addr_l32;

sys/dev/ic/qwzreg.h

13192

uint32_t info1;

sys/dev/ic/qwzreg.h

13298

uint32_t info;

sys/dev/ic/qwzreg.h

13299

uint32_t ppdu_id;

sys/dev/ic/qwzreg.h

13300

uint32_t timestamp;

sys/dev/ic/qwzreg.h

13301

uint32_t rsvd;

sys/dev/ic/qwzreg.h

13306

uint32_t header;

sys/dev/ic/qwzreg.h

13329

uint32_t ppdu_id;

sys/dev/ic/qwzreg.h

13333

uint32_t flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/

sys/dev/ic/qwzreg.h

13334

uint32_t chain_mask;

sys/dev/ic/qwzreg.h

13335

uint32_t fes_duration_us; /* frame exchange sequence */

sys/dev/ic/qwzreg.h

13336

uint32_t ppdu_sch_eval_start_tstmp_us;

sys/dev/ic/qwzreg.h

13337

uint32_t ppdu_sch_end_tstmp_us;

sys/dev/ic/qwzreg.h

13338

uint32_t ppdu_start_tstmp_us;

sys/dev/ic/qwzreg.h

13400

uint32_t info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/

sys/dev/ic/qwzreg.h

13405

uint32_t info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */

sys/dev/ic/qwzreg.h

13406

uint32_t rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */

sys/dev/ic/qwzreg.h

13408

uint32_t resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */

sys/dev/ic/qwzreg.h

13429

uint32_t tx_success_bytes;

sys/dev/ic/qwzreg.h

13430

uint32_t tx_retry_bytes;

sys/dev/ic/qwzreg.h

13431

uint32_t tx_failed_bytes;

sys/dev/ic/qwzreg.h

13432

uint32_t flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */

sys/dev/ic/qwzreg.h

13464

uint32_t ack_rssi;

sys/dev/ic/qwzreg.h

13467

uint32_t flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/

sys/dev/ic/qwzreg.h

13477

uint32_t ppdu_id;

sys/dev/ic/qwzreg.h

13480

uint32_t info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */

sys/dev/ic/qwzreg.h

13483

uint32_t success_bytes;

sys/dev/ic/qwzreg.h

13488

uint32_t num_ppdu_stats;

sys/dev/ic/qwzreg.h

13499

uint32_t tlv_flags;

sys/dev/ic/qwzreg.h

13515

uint32_t ppdu_id;

sys/dev/ic/qwzreg.h

13556

uint32_t hdr;

sys/dev/ic/qwzreg.h

13646

uint32_t cfg_param0;

sys/dev/ic/qwzreg.h

13647

uint32_t cfg_param1;

sys/dev/ic/qwzreg.h

13648

uint32_t cfg_param2;

sys/dev/ic/qwzreg.h

13649

uint32_t cfg_param3;

sys/dev/ic/qwzreg.h

13650

uint32_t reserved;

sys/dev/ic/qwzreg.h

13651

uint32_t cookie_lsb;

sys/dev/ic/qwzreg.h

13652

uint32_t cookie_msb;

sys/dev/ic/qwzreg.h

13689

uint32_t cfg0;

sys/dev/ic/qwzreg.h

13690

uint32_t cfg1;

sys/dev/ic/qwzreg.h

13691

uint32_t cfg2;

sys/dev/ic/qwzreg.h

13692

uint32_t cfg3;

sys/dev/ic/qwzreg.h

13773

uint32_t info0;

sys/dev/ic/qwzreg.h

13775

uint32_t info1;

sys/dev/ic/qwzreg.h

2290

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

2291

uint32_t start_freq;

sys/dev/ic/qwzreg.h

2292

uint32_t end_freq;

sys/dev/ic/qwzreg.h

2296

uint32_t numss_m1;

sys/dev/ic/qwzreg.h

2297

uint32_t ru_bit_mask;

sys/dev/ic/qwzreg.h

2298

uint32_t ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS];

sys/dev/ic/qwzreg.h

2302

uint32_t default_conc_scan_config_bits;

sys/dev/ic/qwzreg.h

2303

uint32_t default_fw_config_bits;

sys/dev/ic/qwzreg.h

2305

uint32_t he_cap_info;

sys/dev/ic/qwzreg.h

2306

uint32_t mpdu_density;

sys/dev/ic/qwzreg.h

2307

uint32_t max_bssid_rx_filters;

sys/dev/ic/qwzreg.h

2308

uint32_t num_hw_modes;

sys/dev/ic/qwzreg.h

2309

uint32_t num_phy;

sys/dev/ic/qwzreg.h

2313

uint32_t hw_mode_id;

sys/dev/ic/qwzreg.h

2314

uint32_t phy_id_map;

sys/dev/ic/qwzreg.h

2315

uint32_t hw_mode_config_type;

sys/dev/ic/qwzreg.h

2327

uint32_t phy_id;

sys/dev/ic/qwzreg.h

2328

uint32_t eeprom_reg_domain;

sys/dev/ic/qwzreg.h

2329

uint32_t eeprom_reg_domain_ext;

sys/dev/ic/qwzreg.h

2330

uint32_t regcap1;

sys/dev/ic/qwzreg.h

2331

uint32_t regcap2;

sys/dev/ic/qwzreg.h

2332

uint32_t wireless_modes;

sys/dev/ic/qwzreg.h

2333

uint32_t low_2ghz_chan;

sys/dev/ic/qwzreg.h

2334

uint32_t high_2ghz_chan;

sys/dev/ic/qwzreg.h

2335

uint32_t low_5ghz_chan;

sys/dev/ic/qwzreg.h

2336

uint32_t high_5ghz_chan;

sys/dev/ic/qwzreg.h

2342

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

2343

uint32_t req_id;

sys/dev/ic/qwzreg.h

2344

uint32_t ptr;

sys/dev/ic/qwzreg.h

2345

uint32_t size;

sys/dev/ic/qwzreg.h

2351

uint32_t len;

sys/dev/ic/qwzreg.h

2352

uint32_t req_id;

sys/dev/ic/qwzreg.h

2363

uint32_t num_vdevs;

sys/dev/ic/qwzreg.h

2364

uint32_t num_peers;

sys/dev/ic/qwzreg.h

2365

uint32_t num_active_peers;

sys/dev/ic/qwzreg.h

2366

uint32_t num_offload_peers;

sys/dev/ic/qwzreg.h

2367

uint32_t num_offload_reorder_buffs;

sys/dev/ic/qwzreg.h

2368

uint32_t num_peer_keys;

sys/dev/ic/qwzreg.h

2369

uint32_t num_tids;

sys/dev/ic/qwzreg.h

2370

uint32_t ast_skid_limit;

sys/dev/ic/qwzreg.h

2371

uint32_t tx_chain_mask;

sys/dev/ic/qwzreg.h

2372

uint32_t rx_chain_mask;

sys/dev/ic/qwzreg.h

2373

uint32_t rx_timeout_pri[4];

sys/dev/ic/qwzreg.h

2374

uint32_t rx_decap_mode;

sys/dev/ic/qwzreg.h

2375

uint32_t scan_max_pending_req;

sys/dev/ic/qwzreg.h

2376

uint32_t bmiss_offload_max_vdev;

sys/dev/ic/qwzreg.h

2377

uint32_t roam_offload_max_vdev;

sys/dev/ic/qwzreg.h

2378

uint32_t roam_offload_max_ap_profiles;

sys/dev/ic/qwzreg.h

2379

uint32_t num_mcast_groups;

sys/dev/ic/qwzreg.h

2380

uint32_t num_mcast_table_elems;

sys/dev/ic/qwzreg.h

2381

uint32_t mcast2ucast_mode;

sys/dev/ic/qwzreg.h

2382

uint32_t tx_dbg_log_size;

sys/dev/ic/qwzreg.h

2383

uint32_t num_wds_entries;

sys/dev/ic/qwzreg.h

2384

uint32_t dma_burst_size;

sys/dev/ic/qwzreg.h

2385

uint32_t mac_aggr_delim;

sys/dev/ic/qwzreg.h

2386

uint32_t rx_skip_defrag_timeout_dup_detection_check;

sys/dev/ic/qwzreg.h

2387

uint32_t vow_config;

sys/dev/ic/qwzreg.h

2388

uint32_t gtk_offload_max_vdev;

sys/dev/ic/qwzreg.h

2389

uint32_t num_msdu_desc;

sys/dev/ic/qwzreg.h

2390

uint32_t max_frag_entries;

sys/dev/ic/qwzreg.h

2391

uint32_t max_peer_ext_stats;

sys/dev/ic/qwzreg.h

2392

uint32_t smart_ant_cap;

sys/dev/ic/qwzreg.h

2393

uint32_t bk_minfree;

sys/dev/ic/qwzreg.h

2394

uint32_t be_minfree;

sys/dev/ic/qwzreg.h

2395

uint32_t vi_minfree;

sys/dev/ic/qwzreg.h

2396

uint32_t vo_minfree;

sys/dev/ic/qwzreg.h

2397

uint32_t rx_batchmode;

sys/dev/ic/qwzreg.h

2398

uint32_t tt_support;

sys/dev/ic/qwzreg.h

2399

uint32_t atf_config;

sys/dev/ic/qwzreg.h

2400

uint32_t iphdr_pad_config;

sys/dev/ic/qwzreg.h

2401

uint32_t qwrap_config:16,

sys/dev/ic/qwzreg.h

2403

uint32_t num_tdls_vdevs;

sys/dev/ic/qwzreg.h

2404

uint32_t num_tdls_conn_table_entries;

sys/dev/ic/qwzreg.h

2405

uint32_t beacon_tx_offload_max_vdev;

sys/dev/ic/qwzreg.h

2406

uint32_t num_multicast_filter_entries;

sys/dev/ic/qwzreg.h

2407

uint32_t num_wow_filters;

sys/dev/ic/qwzreg.h

2408

uint32_t num_keep_alive_pattern;

sys/dev/ic/qwzreg.h

2409

uint32_t keep_alive_pattern_size;

sys/dev/ic/qwzreg.h

2410

uint32_t max_tdls_concurrent_sleep_sta;

sys/dev/ic/qwzreg.h

2411

uint32_t max_tdls_concurrent_buffer_sta;

sys/dev/ic/qwzreg.h

2412

uint32_t wmi_send_separate;

sys/dev/ic/qwzreg.h

2413

uint32_t num_ocb_vdevs;

sys/dev/ic/qwzreg.h

2414

uint32_t num_ocb_channels;

sys/dev/ic/qwzreg.h

2415

uint32_t num_ocb_schedules;

sys/dev/ic/qwzreg.h

2416

uint32_t num_ns_ext_tuples_cfg;

sys/dev/ic/qwzreg.h

2417

uint32_t bpf_instruction_size;

sys/dev/ic/qwzreg.h

2418

uint32_t max_bssid_rx_filters;

sys/dev/ic/qwzreg.h

2419

uint32_t use_pdev_id;

sys/dev/ic/qwzreg.h

2420

uint32_t peer_map_unmap_version;

sys/dev/ic/qwzreg.h

2421

uint32_t sched_params;

sys/dev/ic/qwzreg.h

2422

uint32_t twt_ap_pdev_count;

sys/dev/ic/qwzreg.h

2423

uint32_t twt_ap_sta_count;

sys/dev/ic/qwzreg.h

2425

uint32_t ema_max_vap_cnt;

sys/dev/ic/qwzreg.h

2426

uint32_t ema_max_profile_period;

sys/dev/ic/qwzreg.h

2434

uint32_t hw_mode_id;

sys/dev/ic/qwzreg.h

2435

uint32_t num_band_to_mac;

sys/dev/ic/qwzreg.h

2440

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

2441

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

2442

uint32_t start_freq;

sys/dev/ic/qwzreg.h

2443

uint32_t end_freq;

sys/dev/ic/qwzreg.h

2447

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

2448

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

2449

uint32_t hw_mode_index;

sys/dev/ic/qwzreg.h

2450

uint32_t num_band_to_mac;

sys/dev/ic/qwzreg.h

2454

uint32_t numss_m1; /** NSS - 1*/

sys/dev/ic/qwzreg.h

2456

uint32_t ru_count;

sys/dev/ic/qwzreg.h

2457

uint32_t ru_mask;

sys/dev/ic/qwzreg.h

2459

uint32_t ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS];

sys/dev/ic/qwzreg.h

2465

uint32_t abi_version_0;

sys/dev/ic/qwzreg.h

2466

uint32_t abi_version_1;

sys/dev/ic/qwzreg.h

2467

uint32_t abi_version_ns_0;

sys/dev/ic/qwzreg.h

2468

uint32_t abi_version_ns_1;

sys/dev/ic/qwzreg.h

2469

uint32_t abi_version_ns_2;

sys/dev/ic/qwzreg.h

2470

uint32_t abi_version_ns_3;

sys/dev/ic/qwzreg.h

2474

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

2476

uint32_t num_host_mem_chunks;

sys/dev/ic/qwzreg.h

2486

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

2487

uint32_t num_vdevs;

sys/dev/ic/qwzreg.h

2488

uint32_t num_peers;

sys/dev/ic/qwzreg.h

2489

uint32_t num_offload_peers;

sys/dev/ic/qwzreg.h

2490

uint32_t num_offload_reorder_buffs;

sys/dev/ic/qwzreg.h

2491

uint32_t num_peer_keys;

sys/dev/ic/qwzreg.h

2492

uint32_t num_tids;

sys/dev/ic/qwzreg.h

2493

uint32_t ast_skid_limit;

sys/dev/ic/qwzreg.h

2494

uint32_t tx_chain_mask;

sys/dev/ic/qwzreg.h

2495

uint32_t rx_chain_mask;

sys/dev/ic/qwzreg.h

2496

uint32_t rx_timeout_pri[4];

sys/dev/ic/qwzreg.h

2497

uint32_t rx_decap_mode;

sys/dev/ic/qwzreg.h

2498

uint32_t scan_max_pending_req;

sys/dev/ic/qwzreg.h

2499

uint32_t bmiss_offload_max_vdev;

sys/dev/ic/qwzreg.h

2500

uint32_t roam_offload_max_vdev;

sys/dev/ic/qwzreg.h

2501

uint32_t roam_offload_max_ap_profiles;

sys/dev/ic/qwzreg.h

2502

uint32_t num_mcast_groups;

sys/dev/ic/qwzreg.h

2503

uint32_t num_mcast_table_elems;

sys/dev/ic/qwzreg.h

2504

uint32_t mcast2ucast_mode;

sys/dev/ic/qwzreg.h

2505

uint32_t tx_dbg_log_size;

sys/dev/ic/qwzreg.h

2506

uint32_t num_wds_entries;

sys/dev/ic/qwzreg.h

2507

uint32_t dma_burst_size;

sys/dev/ic/qwzreg.h

2508

uint32_t mac_aggr_delim;

sys/dev/ic/qwzreg.h

2509

uint32_t rx_skip_defrag_timeout_dup_detection_check;

sys/dev/ic/qwzreg.h

2510

uint32_t vow_config;

sys/dev/ic/qwzreg.h

2511

uint32_t gtk_offload_max_vdev;

sys/dev/ic/qwzreg.h

2512

uint32_t num_msdu_desc;

sys/dev/ic/qwzreg.h

2513

uint32_t max_frag_entries;

sys/dev/ic/qwzreg.h

2514

uint32_t num_tdls_vdevs;

sys/dev/ic/qwzreg.h

2515

uint32_t num_tdls_conn_table_entries;

sys/dev/ic/qwzreg.h

2516

uint32_t beacon_tx_offload_max_vdev;

sys/dev/ic/qwzreg.h

2517

uint32_t num_multicast_filter_entries;

sys/dev/ic/qwzreg.h

2518

uint32_t num_wow_filters;

sys/dev/ic/qwzreg.h

2519

uint32_t num_keep_alive_pattern;

sys/dev/ic/qwzreg.h

2520

uint32_t keep_alive_pattern_size;

sys/dev/ic/qwzreg.h

2521

uint32_t max_tdls_concurrent_sleep_sta;

sys/dev/ic/qwzreg.h

2522

uint32_t max_tdls_concurrent_buffer_sta;

sys/dev/ic/qwzreg.h

2523

uint32_t wmi_send_separate;

sys/dev/ic/qwzreg.h

2524

uint32_t num_ocb_vdevs;

sys/dev/ic/qwzreg.h

2525

uint32_t num_ocb_channels;

sys/dev/ic/qwzreg.h

2526

uint32_t num_ocb_schedules;

sys/dev/ic/qwzreg.h

2527

uint32_t flag1;

sys/dev/ic/qwzreg.h

2528

uint32_t smart_ant_cap;

sys/dev/ic/qwzreg.h

2529

uint32_t bk_minfree;

sys/dev/ic/qwzreg.h

2530

uint32_t be_minfree;

sys/dev/ic/qwzreg.h

2531

uint32_t vi_minfree;

sys/dev/ic/qwzreg.h

2532

uint32_t vo_minfree;

sys/dev/ic/qwzreg.h

2533

uint32_t alloc_frag_desc_for_data_pkt;

sys/dev/ic/qwzreg.h

2534

uint32_t num_ns_ext_tuples_cfg;

sys/dev/ic/qwzreg.h

2535

uint32_t bpf_instruction_size;

sys/dev/ic/qwzreg.h

2536

uint32_t max_bssid_rx_filters;

sys/dev/ic/qwzreg.h

2537

uint32_t use_pdev_id;

sys/dev/ic/qwzreg.h

2538

uint32_t max_num_dbs_scan_duty_cycle;

sys/dev/ic/qwzreg.h

2539

uint32_t max_num_group_keys;

sys/dev/ic/qwzreg.h

2540

uint32_t peer_map_unmap_version;

sys/dev/ic/qwzreg.h

2541

uint32_t sched_params;

sys/dev/ic/qwzreg.h

2542

uint32_t twt_ap_pdev_count;

sys/dev/ic/qwzreg.h

2543

uint32_t twt_ap_sta_count;

sys/dev/ic/qwzreg.h

2545

uint32_t max_nlo_ssids;

sys/dev/ic/qwzreg.h

2546

uint32_t num_pkt_filters;

sys/dev/ic/qwzreg.h

2547

uint32_t num_max_sta_vdevs;

sys/dev/ic/qwzreg.h

2548

uint32_t max_bssid_indicator;

sys/dev/ic/qwzreg.h

2549

uint32_t ul_resp_config;

sys/dev/ic/qwzreg.h

2550

uint32_t msdu_flow_override_config0;

sys/dev/ic/qwzreg.h

2551

uint32_t msdu_flow_override_config1;

sys/dev/ic/qwzreg.h

2552

uint32_t flags2;

sys/dev/ic/qwzreg.h

2553

uint32_t host_service_flags;

sys/dev/ic/qwzreg.h

2554

uint32_t max_rnr_neighbours;

sys/dev/ic/qwzreg.h

2555

uint32_t ema_max_vap_cnt;

sys/dev/ic/qwzreg.h

2556

uint32_t ema_max_profile_period;

sys/dev/ic/qwzreg.h

2561

uint32_t fw_build_vers;

sys/dev/ic/qwzreg.h

2563

uint32_t phy_capability;

sys/dev/ic/qwzreg.h

2564

uint32_t max_frag_entry;

sys/dev/ic/qwzreg.h

2565

uint32_t num_rf_chains;

sys/dev/ic/qwzreg.h

2566

uint32_t ht_cap_info;

sys/dev/ic/qwzreg.h

2567

uint32_t vht_cap_info;

sys/dev/ic/qwzreg.h

2568

uint32_t vht_supp_mcs;

sys/dev/ic/qwzreg.h

2569

uint32_t hw_min_tx_power;

sys/dev/ic/qwzreg.h

2570

uint32_t hw_max_tx_power;

sys/dev/ic/qwzreg.h

2571

uint32_t sys_cap_info;

sys/dev/ic/qwzreg.h

2572

uint32_t min_pkt_size_enable;

sys/dev/ic/qwzreg.h

2573

uint32_t max_bcn_ie_size;

sys/dev/ic/qwzreg.h

2574

uint32_t num_mem_reqs;

sys/dev/ic/qwzreg.h

2575

uint32_t max_num_scan_channels;

sys/dev/ic/qwzreg.h

2576

uint32_t hw_bd_id;

sys/dev/ic/qwzreg.h

2577

uint32_t hw_bd_info[HW_BD_INFO_SIZE];

sys/dev/ic/qwzreg.h

2578

uint32_t max_supported_macs;

sys/dev/ic/qwzreg.h

2579

uint32_t wmi_fw_sub_feat_caps;

sys/dev/ic/qwzreg.h

2580

uint32_t num_dbs_hw_modes;

sys/dev/ic/qwzreg.h

2587

uint32_t txrx_chainmask;

sys/dev/ic/qwzreg.h

2588

uint32_t default_dbs_hw_mode_index;

sys/dev/ic/qwzreg.h

2589

uint32_t num_msdu_desc;

sys/dev/ic/qwzreg.h

2592

#define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(uint32_t) - 1) / sizeof(uint32_t))

sys/dev/ic/qwzreg.h

2595

#define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(uint32_t))

sys/dev/ic/qwzreg.h

2600

uint32_t default_conc_scan_config_bits;

sys/dev/ic/qwzreg.h

2601

uint32_t default_fw_config_bits;

sys/dev/ic/qwzreg.h

2603

uint32_t he_cap_info;

sys/dev/ic/qwzreg.h

2604

uint32_t mpdu_density;

sys/dev/ic/qwzreg.h

2605

uint32_t max_bssid_rx_filters;

sys/dev/ic/qwzreg.h

2606

uint32_t fw_build_vers_ext;

sys/dev/ic/qwzreg.h

2607

uint32_t max_nlo_ssids;

sys/dev/ic/qwzreg.h

2608

uint32_t max_bssid_indicator;

sys/dev/ic/qwzreg.h

2609

uint32_t he_cap_info_ext;

sys/dev/ic/qwzreg.h

2613

uint32_t num_hw_modes;

sys/dev/ic/qwzreg.h

2614

uint32_t num_chainmask_tables;

sys/dev/ic/qwzreg.h

2618

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

2619

uint32_t hw_mode_id;

sys/dev/ic/qwzreg.h

2620

uint32_t phy_id_map;

sys/dev/ic/qwzreg.h

2621

uint32_t hw_mode_config_type;

sys/dev/ic/qwzreg.h

2633

uint32_t hw_mode_id;

sys/dev/ic/qwzreg.h

2634

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

2635

uint32_t phy_id;

sys/dev/ic/qwzreg.h

2636

uint32_t supported_flags;

sys/dev/ic/qwzreg.h

2637

uint32_t supported_bands;

sys/dev/ic/qwzreg.h

2638

uint32_t ampdu_density;

sys/dev/ic/qwzreg.h

2639

uint32_t max_bw_supported_2g;

sys/dev/ic/qwzreg.h

2640

uint32_t ht_cap_info_2g;

sys/dev/ic/qwzreg.h

2641

uint32_t vht_cap_info_2g;

sys/dev/ic/qwzreg.h

2642

uint32_t vht_supp_mcs_2g;

sys/dev/ic/qwzreg.h

2643

uint32_t he_cap_info_2g;

sys/dev/ic/qwzreg.h

2644

uint32_t he_supp_mcs_2g;

sys/dev/ic/qwzreg.h

2645

uint32_t tx_chain_mask_2g;

sys/dev/ic/qwzreg.h

2646

uint32_t rx_chain_mask_2g;

sys/dev/ic/qwzreg.h

2647

uint32_t max_bw_supported_5g;

sys/dev/ic/qwzreg.h

2648

uint32_t ht_cap_info_5g;

sys/dev/ic/qwzreg.h

2649

uint32_t vht_cap_info_5g;

sys/dev/ic/qwzreg.h

2650

uint32_t vht_supp_mcs_5g;

sys/dev/ic/qwzreg.h

2651

uint32_t he_cap_info_5g;

sys/dev/ic/qwzreg.h

2652

uint32_t he_supp_mcs_5g;

sys/dev/ic/qwzreg.h

2653

uint32_t tx_chain_mask_5g;

sys/dev/ic/qwzreg.h

2654

uint32_t rx_chain_mask_5g;

sys/dev/ic/qwzreg.h

2655

uint32_t he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE];

sys/dev/ic/qwzreg.h

2656

uint32_t he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE];

sys/dev/ic/qwzreg.h

2659

uint32_t chainmask_table_id;

sys/dev/ic/qwzreg.h

2660

uint32_t lmac_id;

sys/dev/ic/qwzreg.h

2661

uint32_t he_cap_info_2g_ext;

sys/dev/ic/qwzreg.h

2662

uint32_t he_cap_info_5g_ext;

sys/dev/ic/qwzreg.h

2663

uint32_t he_cap_info_internal;

sys/dev/ic/qwzreg.h

2664

uint32_t wireless_modes;

sys/dev/ic/qwzreg.h

2665

uint32_t low_2ghz_chan_freq;

sys/dev/ic/qwzreg.h

2666

uint32_t high_2ghz_chan_freq;

sys/dev/ic/qwzreg.h

2667

uint32_t low_5ghz_chan_freq;

sys/dev/ic/qwzreg.h

2668

uint32_t high_5ghz_chan_freq;

sys/dev/ic/qwzreg.h

2669

uint32_t nss_ratio;

sys/dev/ic/qwzreg.h

2673

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

2674

uint32_t phy_id;

sys/dev/ic/qwzreg.h

2675

uint32_t eeprom_reg_domain;

sys/dev/ic/qwzreg.h

2676

uint32_t eeprom_reg_domain_ext;

sys/dev/ic/qwzreg.h

2677

uint32_t regcap1;

sys/dev/ic/qwzreg.h

2678

uint32_t regcap2;

sys/dev/ic/qwzreg.h

2679

uint32_t wireless_modes;

sys/dev/ic/qwzreg.h

2680

uint32_t low_2ghz_chan;

sys/dev/ic/qwzreg.h

2681

uint32_t high_2ghz_chan;

sys/dev/ic/qwzreg.h

2682

uint32_t low_5ghz_chan;

sys/dev/ic/qwzreg.h

2683

uint32_t high_5ghz_chan;

sys/dev/ic/qwzreg.h

2687

uint32_t num_phy;

sys/dev/ic/qwzreg.h

2695

uint32_t word0;

sys/dev/ic/qwzreg.h

2696

uint32_t word1;

sys/dev/ic/qwzreg.h

2702

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

2703

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

2704

uint32_t module_id;

sys/dev/ic/qwzreg.h

2705

uint32_t min_elem;

sys/dev/ic/qwzreg.h

2706

uint32_t min_buf_sz;

sys/dev/ic/qwzreg.h

2707

uint32_t min_buf_align;

sys/dev/ic/qwzreg.h

2713

uint32_t status;

sys/dev/ic/qwzreg.h

2714

uint32_t num_dscp_table;

sys/dev/ic/qwzreg.h

2715

uint32_t num_extra_mac_addr;

sys/dev/ic/qwzreg.h

2716

uint32_t num_total_peers;

sys/dev/ic/qwzreg.h

2717

uint32_t num_extra_peers;

sys/dev/ic/qwzreg.h

2722

uint32_t max_ast_index;

sys/dev/ic/qwzreg.h

2723

uint32_t pktlog_defs_checksum;

sys/dev/ic/qwzreg.h

2727

uint32_t wmi_service_segment_offset;

sys/dev/ic/qwzreg.h

2728

uint32_t wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32];

sys/dev/ic/qwzreg.h

2733

uint32_t type;

sys/dev/ic/qwzreg.h

2734

uint32_t subtype;

sys/dev/ic/qwzreg.h

2739

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

2740

uint32_t mbssid_flags;

sys/dev/ic/qwzreg.h

2741

uint32_t mbssid_tx_vdev_id;

sys/dev/ic/qwzreg.h

2745

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

2746

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

2747

uint32_t vdev_type;

sys/dev/ic/qwzreg.h

2748

uint32_t vdev_subtype;

sys/dev/ic/qwzreg.h

2750

uint32_t num_cfg_txrx_streams;

sys/dev/ic/qwzreg.h

2751

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

2752

uint32_t mbssid_flags;

sys/dev/ic/qwzreg.h

2753

uint32_t mbssid_tx_vdev_id;

sys/dev/ic/qwzreg.h

2757

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

2758

uint32_t band;

sys/dev/ic/qwzreg.h

2759

uint32_t supported_tx_streams;

sys/dev/ic/qwzreg.h

2760

uint32_t supported_rx_streams;

sys/dev/ic/qwzreg.h

2764

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

2765

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

2769

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

2770

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

2771

uint32_t vdev_assoc_id;

sys/dev/ic/qwzreg.h

2774

uint32_t nontx_profile_idx;

sys/dev/ic/qwzreg.h

2775

uint32_t nontx_profile_cnt;

sys/dev/ic/qwzreg.h

2779

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

2780

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

2784

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

2785

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

2794

uint32_t ssid_len;

sys/dev/ic/qwzreg.h

2795

uint32_t ssid[8];

sys/dev/ic/qwzreg.h

2801

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

2802

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

2803

uint32_t requestor_id;

sys/dev/ic/qwzreg.h

2804

uint32_t beacon_interval;

sys/dev/ic/qwzreg.h

2805

uint32_t dtim_period;

sys/dev/ic/qwzreg.h

2806

uint32_t flags;

sys/dev/ic/qwzreg.h

2808

uint32_t bcn_tx_rate;

sys/dev/ic/qwzreg.h

2809

uint32_t bcn_txpower;

sys/dev/ic/qwzreg.h

2810

uint32_t num_noa_descriptors;

sys/dev/ic/qwzreg.h

2811

uint32_t disable_hw_ack;

sys/dev/ic/qwzreg.h

2812

uint32_t preferred_tx_streams;

sys/dev/ic/qwzreg.h

2813

uint32_t preferred_rx_streams;

sys/dev/ic/qwzreg.h

2814

uint32_t he_ops;

sys/dev/ic/qwzreg.h

2815

uint32_t cac_duration_ms;

sys/dev/ic/qwzreg.h

2816

uint32_t regdomain;

sys/dev/ic/qwzreg.h

2817

uint32_t min_data_rate;

sys/dev/ic/qwzreg.h

2818

uint32_t mbssid_flags;

sys/dev/ic/qwzreg.h

2819

uint32_t mbssid_tx_vdev_id;

sys/dev/ic/qwzreg.h

2830

uint32_t type_count;

sys/dev/ic/qwzreg.h

2831

uint32_t duration;

sys/dev/ic/qwzreg.h

2832

uint32_t interval;

sys/dev/ic/qwzreg.h

2833

uint32_t start_time;

sys/dev/ic/qwzreg.h

2839

uint32_t mhz;

sys/dev/ic/qwzreg.h

2840

uint32_t half_rate:1,

sys/dev/ic/qwzreg.h

2850

uint32_t phy_mode;

sys/dev/ic/qwzreg.h

2851

uint32_t cfreq1;

sys/dev/ic/qwzreg.h

2852

uint32_t cfreq2;

sys/dev/ic/qwzreg.h

2953

uint32_t freq;

sys/dev/ic/qwzreg.h

2954

uint32_t band_center_freq1;

sys/dev/ic/qwzreg.h

2955

uint32_t band_center_freq2;

sys/dev/ic/qwzreg.h

2964

uint32_t min_power;

sys/dev/ic/qwzreg.h

2965

uint32_t max_power;

sys/dev/ic/qwzreg.h

2966

uint32_t max_reg_power;

sys/dev/ic/qwzreg.h

2967

uint32_t max_antenna_gain;

sys/dev/ic/qwzreg.h

2972

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

2974

uint32_t bcn_intval;

sys/dev/ic/qwzreg.h

2975

uint32_t dtim_period;

sys/dev/ic/qwzreg.h

2977

uint32_t ssid_len;

sys/dev/ic/qwzreg.h

2978

uint32_t bcn_tx_rate;

sys/dev/ic/qwzreg.h

2979

uint32_t bcn_tx_power;

sys/dev/ic/qwzreg.h

2983

uint32_t he_ops;

sys/dev/ic/qwzreg.h

2984

uint32_t cac_duration_ms;

sys/dev/ic/qwzreg.h

2985

uint32_t regdomain;

sys/dev/ic/qwzreg.h

2986

uint32_t pref_rx_streams;

sys/dev/ic/qwzreg.h

2987

uint32_t pref_tx_streams;

sys/dev/ic/qwzreg.h

2988

uint32_t num_noa_descriptors;

sys/dev/ic/qwzreg.h

2989

uint32_t min_data_rate;

sys/dev/ic/qwzreg.h

2990

uint32_t mbssid_flags;

sys/dev/ic/qwzreg.h

2991

uint32_t mbssid_tx_vdev_id;

sys/dev/ic/qwzreg.h

2996

uint32_t peer_type;

sys/dev/ic/qwzreg.h

2997

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3005

uint32_t peer_tid_bitmap;

sys/dev/ic/qwzreg.h

3013

uint32_t ctl_2g;

sys/dev/ic/qwzreg.h

3014

uint32_t ctl_5g;

sys/dev/ic/qwzreg.h

3016

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

3022

uint32_t peer_tid_bitmap;

sys/dev/ic/qwzreg.h

3111

uint32_t param_id;

sys/dev/ic/qwzreg.h

3112

uint32_t param_value;

sys/dev/ic/qwzreg.h

3122

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3123

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3125

uint32_t peer_type;

sys/dev/ic/qwzreg.h

3129

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3130

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3135

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3136

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3138

uint32_t tid;

sys/dev/ic/qwzreg.h

3139

uint32_t queue_ptr_lo;

sys/dev/ic/qwzreg.h

3140

uint32_t queue_ptr_hi;

sys/dev/ic/qwzreg.h

3141

uint32_t queue_no;

sys/dev/ic/qwzreg.h

3142

uint32_t ba_window_size_valid;

sys/dev/ic/qwzreg.h

3143

uint32_t ba_window_size;

sys/dev/ic/qwzreg.h

3147

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3148

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3150

uint32_t tid_mask;

sys/dev/ic/qwzreg.h

3154

uint32_t gpio_num;

sys/dev/ic/qwzreg.h

3155

uint32_t input;

sys/dev/ic/qwzreg.h

3156

uint32_t pull_type;

sys/dev/ic/qwzreg.h

3157

uint32_t intr_mode;

sys/dev/ic/qwzreg.h

3181

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3182

uint32_t gpio_num;

sys/dev/ic/qwzreg.h

3183

uint32_t input;

sys/dev/ic/qwzreg.h

3184

uint32_t pull_type;

sys/dev/ic/qwzreg.h

3185

uint32_t intr_mode;

sys/dev/ic/qwzreg.h

3189

uint32_t gpio_num;

sys/dev/ic/qwzreg.h

3190

uint32_t set;

sys/dev/ic/qwzreg.h

3194

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3195

uint32_t gpio_num;

sys/dev/ic/qwzreg.h

3196

uint32_t set;

sys/dev/ic/qwzreg.h

3200

uint32_t arg;

sys/dev/ic/qwzreg.h

3201

uint32_t value;

sys/dev/ic/qwzreg.h

3205

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3206

uint32_t param_id;

sys/dev/ic/qwzreg.h

3207

uint32_t param_value;

sys/dev/ic/qwzreg.h

3211

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3212

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

3213

uint32_t param_id;

sys/dev/ic/qwzreg.h

3214

uint32_t param_value;

sys/dev/ic/qwzreg.h

3218

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3219

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3220

uint32_t sta_ps_mode;

sys/dev/ic/qwzreg.h

3224

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3225

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

3226

uint32_t suspend_opt;

sys/dev/ic/qwzreg.h

3230

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3231

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

3235

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3237

uint32_t req_type;

sys/dev/ic/qwzreg.h

3238

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

3242

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3243

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3245

uint32_t param;

sys/dev/ic/qwzreg.h

3246

uint32_t value;

sys/dev/ic/qwzreg.h

3250

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3251

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3252

uint32_t param;

sys/dev/ic/qwzreg.h

3253

uint32_t value;

sys/dev/ic/qwzreg.h

3257

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3258

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

3259

uint32_t reg_domain;

sys/dev/ic/qwzreg.h

3260

uint32_t reg_domain_2g;

sys/dev/ic/qwzreg.h

3261

uint32_t reg_domain_5g;

sys/dev/ic/qwzreg.h

3262

uint32_t conformance_test_limit_2g;

sys/dev/ic/qwzreg.h

3263

uint32_t conformance_test_limit_5g;

sys/dev/ic/qwzreg.h

3264

uint32_t dfs_domain;

sys/dev/ic/qwzreg.h

3268

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3269

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3271

uint32_t param_id;

sys/dev/ic/qwzreg.h

3272

uint32_t param_value;

sys/dev/ic/qwzreg.h

3276

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3277

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3279

uint32_t peer_tid_bitmap;

sys/dev/ic/qwzreg.h

3283

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3284

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

3288

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3289

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3290

uint32_t bcn_ctrl_op;

sys/dev/ic/qwzreg.h

3304

uint32_t len;

sys/dev/ic/qwzreg.h

3363

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3364

uint32_t scan_id;

sys/dev/ic/qwzreg.h

3365

uint32_t scan_req_id;

sys/dev/ic/qwzreg.h

3366

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3367

uint32_t scan_priority;

sys/dev/ic/qwzreg.h

3368

uint32_t notify_scan_events;

sys/dev/ic/qwzreg.h

3369

uint32_t dwell_time_active;

sys/dev/ic/qwzreg.h

3370

uint32_t dwell_time_passive;

sys/dev/ic/qwzreg.h

3371

uint32_t min_rest_time;

sys/dev/ic/qwzreg.h

3372

uint32_t max_rest_time;

sys/dev/ic/qwzreg.h

3373

uint32_t repeat_probe_time;

sys/dev/ic/qwzreg.h

3374

uint32_t probe_spacing_time;

sys/dev/ic/qwzreg.h

3375

uint32_t idle_time;

sys/dev/ic/qwzreg.h

3376

uint32_t max_scan_time;

sys/dev/ic/qwzreg.h

3377

uint32_t probe_delay;

sys/dev/ic/qwzreg.h

3378

uint32_t scan_ctrl_flags;

sys/dev/ic/qwzreg.h

3379

uint32_t burst_duration;

sys/dev/ic/qwzreg.h

3380

uint32_t num_chan;

sys/dev/ic/qwzreg.h

3381

uint32_t num_bssid;

sys/dev/ic/qwzreg.h

3382

uint32_t num_ssids;

sys/dev/ic/qwzreg.h

3383

uint32_t ie_len;

sys/dev/ic/qwzreg.h

3384

uint32_t n_probes;

sys/dev/ic/qwzreg.h

3387

uint32_t ie_bitmap[WMI_IE_BITMAP_SIZE];

sys/dev/ic/qwzreg.h

3388

uint32_t num_vendor_oui;

sys/dev/ic/qwzreg.h

3389

uint32_t scan_ctrl_flags_ext;

sys/dev/ic/qwzreg.h

3390

uint32_t dwell_time_active_2g;

sys/dev/ic/qwzreg.h

3391

uint32_t dwell_time_active_6g;

sys/dev/ic/qwzreg.h

3392

uint32_t dwell_time_passive_6g;

sys/dev/ic/qwzreg.h

3393

uint32_t scan_start_offset;

sys/dev/ic/qwzreg.h

3429

uint32_t freq_flags;

sys/dev/ic/qwzreg.h

3430

uint32_t short_ssid;

sys/dev/ic/qwzreg.h

3434

uint32_t freq_flags;

sys/dev/ic/qwzreg.h

3439

uint32_t scan_id;

sys/dev/ic/qwzreg.h

3440

uint32_t scan_req_id;

sys/dev/ic/qwzreg.h

3441

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3442

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

3446

uint32_t scan_ev_started:1,

sys/dev/ic/qwzreg.h

3460

uint32_t scan_events;

sys/dev/ic/qwzreg.h

3462

uint32_t scan_ctrl_flags_ext;

sys/dev/ic/qwzreg.h

3463

uint32_t dwell_time_active;

sys/dev/ic/qwzreg.h

3464

uint32_t dwell_time_active_2g;

sys/dev/ic/qwzreg.h

3465

uint32_t dwell_time_passive;

sys/dev/ic/qwzreg.h

3466

uint32_t dwell_time_active_6g;

sys/dev/ic/qwzreg.h

3467

uint32_t dwell_time_passive_6g;

sys/dev/ic/qwzreg.h

3468

uint32_t min_rest_time;

sys/dev/ic/qwzreg.h

3469

uint32_t max_rest_time;

sys/dev/ic/qwzreg.h

3470

uint32_t repeat_probe_time;

sys/dev/ic/qwzreg.h

3471

uint32_t probe_spacing_time;

sys/dev/ic/qwzreg.h

3472

uint32_t idle_time;

sys/dev/ic/qwzreg.h

3473

uint32_t max_scan_time;

sys/dev/ic/qwzreg.h

3474

uint32_t probe_delay;

sys/dev/ic/qwzreg.h

3477

uint32_t scan_f_passive:1,

sys/dev/ic/qwzreg.h

3503

uint32_t scan_flags;

sys/dev/ic/qwzreg.h

3506

uint32_t burst_duration;

sys/dev/ic/qwzreg.h

3507

uint32_t num_chan;

sys/dev/ic/qwzreg.h

3508

uint32_t num_bssid;

sys/dev/ic/qwzreg.h

3509

uint32_t num_ssids;

sys/dev/ic/qwzreg.h

3510

uint32_t n_probes;

sys/dev/ic/qwzreg.h

3511

uint32_t *chan_list;

sys/dev/ic/qwzreg.h

3512

uint32_t notify_scan_events;

sys/dev/ic/qwzreg.h

3518

uint32_t num_hint_s_ssid;

sys/dev/ic/qwzreg.h

3519

uint32_t num_hint_bssid;

sys/dev/ic/qwzreg.h

3536

uint32_t scan_id;

sys/dev/ic/qwzreg.h

3537

uint32_t scan_req_id;

sys/dev/ic/qwzreg.h

3538

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3539

uint32_t scan_priority;

sys/dev/ic/qwzreg.h

3540

uint32_t notify_scan_events;

sys/dev/ic/qwzreg.h

3541

uint32_t dwell_time_active;

sys/dev/ic/qwzreg.h

3542

uint32_t dwell_time_passive;

sys/dev/ic/qwzreg.h

3543

uint32_t min_rest_time;

sys/dev/ic/qwzreg.h

3544

uint32_t max_rest_time;

sys/dev/ic/qwzreg.h

3545

uint32_t repeat_probe_time;

sys/dev/ic/qwzreg.h

3546

uint32_t probe_spacing_time;

sys/dev/ic/qwzreg.h

3547

uint32_t idle_time;

sys/dev/ic/qwzreg.h

3548

uint32_t max_scan_time;

sys/dev/ic/qwzreg.h

3549

uint32_t probe_delay;

sys/dev/ic/qwzreg.h

3550

uint32_t scan_ctrl_flags;

sys/dev/ic/qwzreg.h

3552

uint32_t ie_len;

sys/dev/ic/qwzreg.h

3553

uint32_t n_channels;

sys/dev/ic/qwzreg.h

3554

uint32_t n_ssids;

sys/dev/ic/qwzreg.h

3555

uint32_t n_bssids;

sys/dev/ic/qwzreg.h

3558

uint32_t channels[64];

sys/dev/ic/qwzreg.h

3579

uint32_t requester;

sys/dev/ic/qwzreg.h

3580

uint32_t scan_id;

sys/dev/ic/qwzreg.h

3582

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3583

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

3587

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3588

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3589

uint32_t data_len;

sys/dev/ic/qwzreg.h

3591

uint32_t frag_ptr;

sys/dev/ic/qwzreg.h

3592

uint32_t frag_ptr_lo;

sys/dev/ic/qwzreg.h

3594

uint32_t frame_ctrl;

sys/dev/ic/qwzreg.h

3595

uint32_t dtim_flag;

sys/dev/ic/qwzreg.h

3596

uint32_t bcn_antenna;

sys/dev/ic/qwzreg.h

3597

uint32_t frag_ptr_hi;

sys/dev/ic/qwzreg.h

3624

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3625

uint32_t mhz;

sys/dev/ic/qwzreg.h

3626

uint32_t band_center_freq1;

sys/dev/ic/qwzreg.h

3627

uint32_t band_center_freq2;

sys/dev/ic/qwzreg.h

3628

uint32_t info;

sys/dev/ic/qwzreg.h

3629

uint32_t reg_info_1;

sys/dev/ic/qwzreg.h

3630

uint32_t reg_info_2;

sys/dev/ic/qwzreg.h

3660

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3661

uint32_t type;

sys/dev/ic/qwzreg.h

3662

uint32_t delay_time_ms;

sys/dev/ic/qwzreg.h

3666

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3667

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3668

uint32_t param_id;

sys/dev/ic/qwzreg.h

3669

uint32_t param_value;

sys/dev/ic/qwzreg.h

3690

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3692

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3694

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

3698

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3699

uint32_t param;

sys/dev/ic/qwzreg.h

3700

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

3704

uint32_t len;

sys/dev/ic/qwzreg.h

3705

uint32_t msgref;

sys/dev/ic/qwzreg.h

3706

uint32_t segmentinfo;

sys/dev/ic/qwzreg.h

3707

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

3711

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3728

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3729

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3730

uint32_t tim_ie_offset;

sys/dev/ic/qwzreg.h

3731

uint32_t buf_len;

sys/dev/ic/qwzreg.h

3732

uint32_t csa_switch_count_offset;

sys/dev/ic/qwzreg.h

3733

uint32_t ext_csa_switch_count_offset;

sys/dev/ic/qwzreg.h

3734

uint32_t csa_event_bitmap;

sys/dev/ic/qwzreg.h

3735

uint32_t mbssid_ie_offset;

sys/dev/ic/qwzreg.h

3736

uint32_t esp_ie_offset;

sys/dev/ic/qwzreg.h

3737

uint32_t csc_switch_count_offset;

sys/dev/ic/qwzreg.h

3738

uint32_t csc_event_bitmap;

sys/dev/ic/qwzreg.h

3739

uint32_t mu_edca_ie_offset;

sys/dev/ic/qwzreg.h

3740

uint32_t feature_enable_bitmap;

sys/dev/ic/qwzreg.h

3741

uint32_t ema_params;

sys/dev/ic/qwzreg.h

3745

uint32_t key_seq_counter_l;

sys/dev/ic/qwzreg.h

3746

uint32_t key_seq_counter_h;

sys/dev/ic/qwzreg.h

3750

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3751

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3753

uint32_t key_idx;

sys/dev/ic/qwzreg.h

3754

uint32_t key_flags;

sys/dev/ic/qwzreg.h

3755

uint32_t key_cipher;

sys/dev/ic/qwzreg.h

3761

uint32_t key_len;

sys/dev/ic/qwzreg.h

3762

uint32_t key_txmic_len;

sys/dev/ic/qwzreg.h

3763

uint32_t key_rxmic_len;

sys/dev/ic/qwzreg.h

3764

uint32_t is_group_key_id_valid;

sys/dev/ic/qwzreg.h

3765

uint32_t group_key_id;

sys/dev/ic/qwzreg.h

3773

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3775

uint32_t key_idx;

sys/dev/ic/qwzreg.h

3776

uint32_t key_flags;

sys/dev/ic/qwzreg.h

3777

uint32_t key_cipher;

sys/dev/ic/qwzreg.h

3778

uint32_t key_len;

sys/dev/ic/qwzreg.h

3779

uint32_t key_txmic_len;

sys/dev/ic/qwzreg.h

3780

uint32_t key_rxmic_len;

sys/dev/ic/qwzreg.h

3793

uint32_t num_rates;

sys/dev/ic/qwzreg.h

3799

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3800

uint32_t peer_new_assoc;

sys/dev/ic/qwzreg.h

3801

uint32_t peer_associd;

sys/dev/ic/qwzreg.h

3802

uint32_t peer_flags;

sys/dev/ic/qwzreg.h

3803

uint32_t peer_caps;

sys/dev/ic/qwzreg.h

3804

uint32_t peer_listen_intval;

sys/dev/ic/qwzreg.h

3805

uint32_t peer_ht_caps;

sys/dev/ic/qwzreg.h

3806

uint32_t peer_max_mpdu;

sys/dev/ic/qwzreg.h

3807

uint32_t peer_mpdu_density;

sys/dev/ic/qwzreg.h

3808

uint32_t peer_rate_caps;

sys/dev/ic/qwzreg.h

3809

uint32_t peer_nss;

sys/dev/ic/qwzreg.h

3810

uint32_t peer_vht_caps;

sys/dev/ic/qwzreg.h

3811

uint32_t peer_phymode;

sys/dev/ic/qwzreg.h

3812

uint32_t peer_ht_info[2];

sys/dev/ic/qwzreg.h

3815

uint32_t rx_max_rate;

sys/dev/ic/qwzreg.h

3816

uint32_t rx_mcs_set;

sys/dev/ic/qwzreg.h

3817

uint32_t tx_max_rate;

sys/dev/ic/qwzreg.h

3818

uint32_t tx_mcs_set;

sys/dev/ic/qwzreg.h

3821

uint32_t tx_max_mcs_nss;

sys/dev/ic/qwzreg.h

3822

uint32_t peer_bw_rxnss_override;

sys/dev/ic/qwzreg.h

3847

uint32_t peer_he_cap_macinfo[2];

sys/dev/ic/qwzreg.h

3848

uint32_t peer_he_cap_macinfo_internal;

sys/dev/ic/qwzreg.h

3849

uint32_t peer_he_caps_6ghz;

sys/dev/ic/qwzreg.h

3850

uint32_t peer_he_ops;

sys/dev/ic/qwzreg.h

3851

uint32_t peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE];

sys/dev/ic/qwzreg.h

3852

uint32_t peer_he_mcs_count;

sys/dev/ic/qwzreg.h

3853

uint32_t peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];

sys/dev/ic/qwzreg.h

3854

uint32_t peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];

sys/dev/ic/qwzreg.h

3862

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3864

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3865

uint32_t peer_new_assoc;

sys/dev/ic/qwzreg.h

3866

uint32_t peer_associd;

sys/dev/ic/qwzreg.h

3867

uint32_t peer_flags;

sys/dev/ic/qwzreg.h

3868

uint32_t peer_caps;

sys/dev/ic/qwzreg.h

3869

uint32_t peer_listen_intval;

sys/dev/ic/qwzreg.h

3870

uint32_t peer_ht_caps;

sys/dev/ic/qwzreg.h

3871

uint32_t peer_max_mpdu;

sys/dev/ic/qwzreg.h

3872

uint32_t peer_mpdu_density;

sys/dev/ic/qwzreg.h

3873

uint32_t peer_rate_caps;

sys/dev/ic/qwzreg.h

3874

uint32_t peer_nss;

sys/dev/ic/qwzreg.h

3875

uint32_t peer_vht_caps;

sys/dev/ic/qwzreg.h

3876

uint32_t peer_phymode;

sys/dev/ic/qwzreg.h

3877

uint32_t peer_ht_info[2];

sys/dev/ic/qwzreg.h

3878

uint32_t num_peer_legacy_rates;

sys/dev/ic/qwzreg.h

3879

uint32_t num_peer_ht_rates;

sys/dev/ic/qwzreg.h

3880

uint32_t peer_bw_rxnss_override;

sys/dev/ic/qwzreg.h

3882

uint32_t peer_he_cap_info;

sys/dev/ic/qwzreg.h

3883

uint32_t peer_he_ops;

sys/dev/ic/qwzreg.h

3884

uint32_t peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE];

sys/dev/ic/qwzreg.h

3885

uint32_t peer_he_mcs;

sys/dev/ic/qwzreg.h

3886

uint32_t peer_he_cap_info_ext;

sys/dev/ic/qwzreg.h

3887

uint32_t peer_he_cap_info_internal;

sys/dev/ic/qwzreg.h

3888

uint32_t min_data_rate;

sys/dev/ic/qwzreg.h

3889

uint32_t peer_he_caps_6ghz;

sys/dev/ic/qwzreg.h

3893

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3894

uint32_t requestor;

sys/dev/ic/qwzreg.h

3895

uint32_t scan_id;

sys/dev/ic/qwzreg.h

3896

uint32_t req_type;

sys/dev/ic/qwzreg.h

3897

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3898

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

3902

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

3908

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3909

uint32_t num_scan_chans;

sys/dev/ic/qwzreg.h

3910

uint32_t flags;

sys/dev/ic/qwzreg.h

3911

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

3928

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3929

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3930

uint32_t desc_id;

sys/dev/ic/qwzreg.h

3931

uint32_t chanfreq;

sys/dev/ic/qwzreg.h

3932

uint32_t paddr_lo;

sys/dev/ic/qwzreg.h

3933

uint32_t paddr_hi;

sys/dev/ic/qwzreg.h

3934

uint32_t frame_len;

sys/dev/ic/qwzreg.h

3935

uint32_t buf_len;

sys/dev/ic/qwzreg.h

3936

uint32_t tx_params_valid;

sys/dev/ic/qwzreg.h

3948

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3949

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3950

uint32_t sta_ps_mode;

sys/dev/ic/qwzreg.h

3954

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3955

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3956

uint32_t forced_mode;

sys/dev/ic/qwzreg.h

3960

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3961

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3962

uint32_t param;

sys/dev/ic/qwzreg.h

3963

uint32_t value;

sys/dev/ic/qwzreg.h

3967

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3968

uint32_t caps;

sys/dev/ic/qwzreg.h

3969

uint32_t erp;

sys/dev/ic/qwzreg.h

3978

uint32_t value;

sys/dev/ic/qwzreg.h

3982

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

3983

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

3984

uint32_t enable;

sys/dev/ic/qwzreg.h

3988

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

3989

uint32_t param;

sys/dev/ic/qwzreg.h

3990

uint32_t value;

sys/dev/ic/qwzreg.h

3994

uint32_t if_id;

sys/dev/ic/qwzreg.h

3995

uint32_t param_id;

sys/dev/ic/qwzreg.h

3996

uint32_t param_value;

sys/dev/ic/qwzreg.h

4000

uint32_t stats_id;

sys/dev/ic/qwzreg.h

4001

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4002

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

4010

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4011

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

4012

uint32_t new_alpha2;

sys/dev/ic/qwzreg.h

4038

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4039

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

4040

uint32_t init_cc_type;

sys/dev/ic/qwzreg.h

4042

uint32_t country_code;

sys/dev/ic/qwzreg.h

4043

uint32_t regdom_id;

sys/dev/ic/qwzreg.h

4044

uint32_t alpha2;

sys/dev/ic/qwzreg.h

4049

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4050

uint32_t scan_period_msec;

sys/dev/ic/qwzreg.h

4051

uint32_t start_interval_msec;

sys/dev/ic/qwzreg.h

4055

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4056

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4057

uint32_t scan_period_msec;

sys/dev/ic/qwzreg.h

4058

uint32_t start_interval_msec;

sys/dev/ic/qwzreg.h

4062

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4063

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4067

uint32_t new_alpha2;

sys/dev/ic/qwzreg.h

4072

uint32_t tmplwm;

sys/dev/ic/qwzreg.h

4073

uint32_t tmphwm;

sys/dev/ic/qwzreg.h

4074

uint32_t dcoffpercent;

sys/dev/ic/qwzreg.h

4075

uint32_t priority;

sys/dev/ic/qwzreg.h

4079

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

4080

uint32_t enable;

sys/dev/ic/qwzreg.h

4081

uint32_t dc;

sys/dev/ic/qwzreg.h

4082

uint32_t dc_per_event;

sys/dev/ic/qwzreg.h

4087

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4088

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

4089

uint32_t enable;

sys/dev/ic/qwzreg.h

4090

uint32_t dc;

sys/dev/ic/qwzreg.h

4091

uint32_t dc_per_event;

sys/dev/ic/qwzreg.h

4092

uint32_t therm_throt_levels;

sys/dev/ic/qwzreg.h

4096

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4097

uint32_t temp_lwm;

sys/dev/ic/qwzreg.h

4098

uint32_t temp_hwm;

sys/dev/ic/qwzreg.h

4099

uint32_t dc_off_percent;

sys/dev/ic/qwzreg.h

4100

uint32_t prio;

sys/dev/ic/qwzreg.h

4104

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4105

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4107

uint32_t tid;

sys/dev/ic/qwzreg.h

4108

uint32_t initiator;

sys/dev/ic/qwzreg.h

4109

uint32_t reasoncode;

sys/dev/ic/qwzreg.h

4113

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4114

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4116

uint32_t tid;

sys/dev/ic/qwzreg.h

4117

uint32_t statuscode;

sys/dev/ic/qwzreg.h

4121

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4122

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4124

uint32_t tid;

sys/dev/ic/qwzreg.h

4125

uint32_t buffersize;

sys/dev/ic/qwzreg.h

4129

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4130

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4135

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4140

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4141

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

4142

uint32_t enable;

sys/dev/ic/qwzreg.h

4143

uint32_t filter_type;

sys/dev/ic/qwzreg.h

4144

uint32_t num_mac;

sys/dev/ic/qwzreg.h

4153

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4154

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

4155

uint32_t evlist; /* WMI_PKTLOG_EVENT */

sys/dev/ic/qwzreg.h

4156

uint32_t enable;

sys/dev/ic/qwzreg.h

4160

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4161

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

4176

uint32_t cmd_id;

sys/dev/ic/qwzreg.h

4177

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

4178

uint32_t radar_param;

sys/dev/ic/qwzreg.h

4182

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4183

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4184

uint32_t module_id;

sys/dev/ic/qwzreg.h

4185

uint32_t num_args;

sys/dev/ic/qwzreg.h

4186

uint32_t diag_token;

sys/dev/ic/qwzreg.h

4219

uint32_t tim_ie_offset;

sys/dev/ic/qwzreg.h

4220

uint32_t tmpl_len;

sys/dev/ic/qwzreg.h

4221

uint32_t tmpl_len_aligned;

sys/dev/ic/qwzreg.h

4222

uint32_t csa_switch_count_offset;

sys/dev/ic/qwzreg.h

4223

uint32_t ext_csa_switch_count_offset;

sys/dev/ic/qwzreg.h

4228

uint32_t num_rates;

sys/dev/ic/qwzreg.h

4229

uint32_t rates[(MAX_SUPPORTED_RATES / 4) + 1];

sys/dev/ic/qwzreg.h

4233

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4234

uint32_t rx_max_rate;

sys/dev/ic/qwzreg.h

4235

uint32_t rx_mcs_set;

sys/dev/ic/qwzreg.h

4236

uint32_t tx_max_rate;

sys/dev/ic/qwzreg.h

4237

uint32_t tx_mcs_set;

sys/dev/ic/qwzreg.h

4238

uint32_t tx_max_mcs_nss;

sys/dev/ic/qwzreg.h

4242

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4245

uint32_t rx_mcs_set;

sys/dev/ic/qwzreg.h

4248

uint32_t tx_mcs_set;

sys/dev/ic/qwzreg.h

4261

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4262

uint32_t requestor_id;

sys/dev/ic/qwzreg.h

4264

uint32_t status;

sys/dev/ic/qwzreg.h

4265

uint32_t chain_mask;

sys/dev/ic/qwzreg.h

4266

uint32_t smps_mode;

sys/dev/ic/qwzreg.h

4268

uint32_t mac_id;

sys/dev/ic/qwzreg.h

4269

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

4271

uint32_t cfgd_tx_streams;

sys/dev/ic/qwzreg.h

4272

uint32_t cfgd_rx_streams;

sys/dev/ic/qwzreg.h

4526

uint32_t dfs_region;

sys/dev/ic/qwzreg.h

4527

uint32_t phybitmap;

sys/dev/ic/qwzreg.h

4528

uint32_t min_bw_2ghz;

sys/dev/ic/qwzreg.h

4529

uint32_t max_bw_2ghz;

sys/dev/ic/qwzreg.h

4530

uint32_t min_bw_5ghz;

sys/dev/ic/qwzreg.h

4531

uint32_t max_bw_5ghz;

sys/dev/ic/qwzreg.h

4532

uint32_t num_2ghz_reg_rules;

sys/dev/ic/qwzreg.h

4533

uint32_t num_5ghz_reg_rules;

sys/dev/ic/qwzreg.h

4542

uint32_t domain_code_6ghz_super_id;

sys/dev/ic/qwzreg.h

4543

uint32_t min_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];

sys/dev/ic/qwzreg.h

4544

uint32_t max_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];

sys/dev/ic/qwzreg.h

4545

uint32_t min_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];

sys/dev/ic/qwzreg.h

4546

uint32_t max_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];

sys/dev/ic/qwzreg.h

4547

uint32_t num_6ghz_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE];

sys/dev/ic/qwzreg.h

4548

uint32_t num_6ghz_rules_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];

sys/dev/ic/qwzreg.h

4555

uint32_t status_code;

sys/dev/ic/qwzreg.h

4556

uint32_t phy_id;

sys/dev/ic/qwzreg.h

4557

uint32_t alpha2;

sys/dev/ic/qwzreg.h

4558

uint32_t num_phy;

sys/dev/ic/qwzreg.h

4559

uint32_t country_id;

sys/dev/ic/qwzreg.h

4560

uint32_t domain_code;

sys/dev/ic/qwzreg.h

4561

uint32_t dfs_region;

sys/dev/ic/qwzreg.h

4562

uint32_t phybitmap;

sys/dev/ic/qwzreg.h

4563

uint32_t min_bw_2ghz;

sys/dev/ic/qwzreg.h

4564

uint32_t max_bw_2ghz;

sys/dev/ic/qwzreg.h

4565

uint32_t min_bw_5ghz;

sys/dev/ic/qwzreg.h

4566

uint32_t max_bw_5ghz;

sys/dev/ic/qwzreg.h

4567

uint32_t num_2ghz_reg_rules;

sys/dev/ic/qwzreg.h

4568

uint32_t num_5ghz_reg_rules;

sys/dev/ic/qwzreg.h

4572

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4573

uint32_t freq_info;

sys/dev/ic/qwzreg.h

4574

uint32_t bw_pwr_info;

sys/dev/ic/qwzreg.h

4575

uint32_t flag_info;

sys/dev/ic/qwzreg.h

4581

uint32_t status_code;

sys/dev/ic/qwzreg.h

4582

uint32_t phy_id;

sys/dev/ic/qwzreg.h

4583

uint32_t alpha2;

sys/dev/ic/qwzreg.h

4584

uint32_t num_phy;

sys/dev/ic/qwzreg.h

4585

uint32_t country_id;

sys/dev/ic/qwzreg.h

4586

uint32_t domain_code;

sys/dev/ic/qwzreg.h

4587

uint32_t dfs_region;

sys/dev/ic/qwzreg.h

4588

uint32_t phybitmap;

sys/dev/ic/qwzreg.h

4589

uint32_t min_bw_2ghz;

sys/dev/ic/qwzreg.h

4590

uint32_t max_bw_2ghz;

sys/dev/ic/qwzreg.h

4591

uint32_t min_bw_5ghz;

sys/dev/ic/qwzreg.h

4592

uint32_t max_bw_5ghz;

sys/dev/ic/qwzreg.h

4593

uint32_t num_2ghz_reg_rules;

sys/dev/ic/qwzreg.h

4594

uint32_t num_5ghz_reg_rules;

sys/dev/ic/qwzreg.h

4595

uint32_t client_type;

sys/dev/ic/qwzreg.h

4596

uint32_t rnr_tpe_usable;

sys/dev/ic/qwzreg.h

4597

uint32_t unspecified_ap_usable;

sys/dev/ic/qwzreg.h

4598

uint32_t domain_code_6ghz_ap_lpi;

sys/dev/ic/qwzreg.h

4599

uint32_t domain_code_6ghz_ap_sp;

sys/dev/ic/qwzreg.h

4600

uint32_t domain_code_6ghz_ap_vlp;

sys/dev/ic/qwzreg.h

4601

uint32_t domain_code_6ghz_client_lpi[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwzreg.h

4602

uint32_t domain_code_6ghz_client_sp[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwzreg.h

4603

uint32_t domain_code_6ghz_client_vlp[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwzreg.h

4604

uint32_t domain_code_6ghz_super_id;

sys/dev/ic/qwzreg.h

4605

uint32_t min_bw_6ghz_ap_sp;

sys/dev/ic/qwzreg.h

4606

uint32_t max_bw_6ghz_ap_sp;

sys/dev/ic/qwzreg.h

4607

uint32_t min_bw_6ghz_ap_lpi;

sys/dev/ic/qwzreg.h

4608

uint32_t max_bw_6ghz_ap_lpi;

sys/dev/ic/qwzreg.h

4609

uint32_t min_bw_6ghz_ap_vlp;

sys/dev/ic/qwzreg.h

4610

uint32_t max_bw_6ghz_ap_vlp;

sys/dev/ic/qwzreg.h

4611

uint32_t min_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwzreg.h

4612

uint32_t max_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwzreg.h

4613

uint32_t min_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwzreg.h

4614

uint32_t max_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwzreg.h

4615

uint32_t min_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwzreg.h

4616

uint32_t max_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwzreg.h

4617

uint32_t num_6ghz_reg_rules_ap_sp;

sys/dev/ic/qwzreg.h

4618

uint32_t num_6ghz_reg_rules_ap_lpi;

sys/dev/ic/qwzreg.h

4619

uint32_t num_6ghz_reg_rules_ap_vlp;

sys/dev/ic/qwzreg.h

4620

uint32_t num_6ghz_reg_rules_client_sp[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwzreg.h

4621

uint32_t num_6ghz_reg_rules_client_lpi[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwzreg.h

4622

uint32_t num_6ghz_reg_rules_client_vlp[WMI_REG_CLIENT_MAX];

sys/dev/ic/qwzreg.h

4626

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

4627

uint32_t freq_info;

sys/dev/ic/qwzreg.h

4628

uint32_t bw_pwr_info;

sys/dev/ic/qwzreg.h

4629

uint32_t flag_info;

sys/dev/ic/qwzreg.h

4630

uint32_t psd_power_info;

sys/dev/ic/qwzreg.h

4634

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4638

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4643

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4644

uint32_t tx_status;

sys/dev/ic/qwzreg.h

4648

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4652

uint32_t freq; /* Units in MHz */

sys/dev/ic/qwzreg.h

4653

uint32_t noise_floor; /* units are dBm */

sys/dev/ic/qwzreg.h

4655

uint32_t rx_clear_count_low;

sys/dev/ic/qwzreg.h

4656

uint32_t rx_clear_count_high;

sys/dev/ic/qwzreg.h

4658

uint32_t cycle_count_low;

sys/dev/ic/qwzreg.h

4659

uint32_t cycle_count_high;

sys/dev/ic/qwzreg.h

4661

uint32_t tx_cycle_count_low;

sys/dev/ic/qwzreg.h

4662

uint32_t tx_cycle_count_high;

sys/dev/ic/qwzreg.h

4664

uint32_t rx_cycle_count_low;

sys/dev/ic/qwzreg.h

4665

uint32_t rx_cycle_count_high;

sys/dev/ic/qwzreg.h

4667

uint32_t rx_bss_cycle_count_low;

sys/dev/ic/qwzreg.h

4668

uint32_t rx_bss_cycle_count_high;

sys/dev/ic/qwzreg.h

4669

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

4675

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4677

uint32_t key_idx;

sys/dev/ic/qwzreg.h

4678

uint32_t key_flags;

sys/dev/ic/qwzreg.h

4679

uint32_t status;

sys/dev/ic/qwzreg.h

4683

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4685

uint32_t key_idx;

sys/dev/ic/qwzreg.h

4686

uint32_t key_flags;

sys/dev/ic/qwzreg.h

4687

uint32_t status;

sys/dev/ic/qwzreg.h

4691

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4696

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4701

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4702

uint32_t fils_tt;

sys/dev/ic/qwzreg.h

4703

uint32_t tbtt;

sys/dev/ic/qwzreg.h

4707

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4708

uint32_t tx_status;

sys/dev/ic/qwzreg.h

4716

uint32_t tx_frame_count; /* Cycles spent transmitting frames */

sys/dev/ic/qwzreg.h

4717

uint32_t rx_frame_count; /* Cycles spent receiving frames */

sys/dev/ic/qwzreg.h

4718

uint32_t rx_clear_count; /* Total channel busy time, evidently */

sys/dev/ic/qwzreg.h

4719

uint32_t cycle_count; /* Total on-channel time */

sys/dev/ic/qwzreg.h

4720

uint32_t phy_err_count;

sys/dev/ic/qwzreg.h

4721

uint32_t chan_tx_pwr;

sys/dev/ic/qwzreg.h

4725

uint32_t ack_rx_bad;

sys/dev/ic/qwzreg.h

4726

uint32_t rts_bad;

sys/dev/ic/qwzreg.h

4727

uint32_t rts_good;

sys/dev/ic/qwzreg.h

4728

uint32_t fcs_bad;

sys/dev/ic/qwzreg.h

4729

uint32_t no_beacons;

sys/dev/ic/qwzreg.h

4730

uint32_t mib_int_count;

sys/dev/ic/qwzreg.h

4765

uint32_t hw_paused;

sys/dev/ic/qwzreg.h

4774

uint32_t tx_ko;

sys/dev/ic/qwzreg.h

4776

uint32_t tx_xretry;

sys/dev/ic/qwzreg.h

4779

uint32_t data_rc;

sys/dev/ic/qwzreg.h

4782

uint32_t self_triggers;

sys/dev/ic/qwzreg.h

4785

uint32_t sw_retry_failure;

sys/dev/ic/qwzreg.h

4788

uint32_t illgl_rate_phy_err;

sys/dev/ic/qwzreg.h

4791

uint32_t pdev_cont_xretry;

sys/dev/ic/qwzreg.h

4794

uint32_t pdev_tx_timeout;

sys/dev/ic/qwzreg.h

4797

uint32_t pdev_resets;

sys/dev/ic/qwzreg.h

4800

uint32_t stateless_tid_alloc_failure;

sys/dev/ic/qwzreg.h

4803

uint32_t phy_underrun;

sys/dev/ic/qwzreg.h

4806

uint32_t txop_ovf;

sys/dev/ic/qwzreg.h

4809

uint32_t seq_posted;

sys/dev/ic/qwzreg.h

4812

uint32_t seq_failed_queueing;

sys/dev/ic/qwzreg.h

4815

uint32_t seq_completed;

sys/dev/ic/qwzreg.h

4818

uint32_t seq_restarted;

sys/dev/ic/qwzreg.h

4821

uint32_t mu_seq_posted;

sys/dev/ic/qwzreg.h

4891

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4892

uint32_t beacon_snr;

sys/dev/ic/qwzreg.h

4893

uint32_t data_snr;

sys/dev/ic/qwzreg.h

4894

uint32_t num_tx_frames[WLAN_MAX_AC];

sys/dev/ic/qwzreg.h

4895

uint32_t num_rx_frames;

sys/dev/ic/qwzreg.h

4896

uint32_t num_tx_frames_retries[WLAN_MAX_AC];

sys/dev/ic/qwzreg.h

4897

uint32_t num_tx_frames_failures[WLAN_MAX_AC];

sys/dev/ic/qwzreg.h

4898

uint32_t num_rts_fail;

sys/dev/ic/qwzreg.h

4899

uint32_t num_rts_success;

sys/dev/ic/qwzreg.h

4900

uint32_t num_rx_err;

sys/dev/ic/qwzreg.h

4901

uint32_t num_rx_discard;

sys/dev/ic/qwzreg.h

4902

uint32_t num_tx_not_acked;

sys/dev/ic/qwzreg.h

4903

uint32_t tx_rate_history[MAX_TX_RATE_VALUES];

sys/dev/ic/qwzreg.h

4904

uint32_t beacon_rssi_history[MAX_TX_RATE_VALUES];

sys/dev/ic/qwzreg.h

4908

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4909

uint32_t tx_bcn_succ_cnt;

sys/dev/ic/qwzreg.h

4910

uint32_t tx_bcn_outage_cnt;

sys/dev/ic/qwzreg.h

4914

uint32_t stats_id;

sys/dev/ic/qwzreg.h

4915

uint32_t num_pdev_stats;

sys/dev/ic/qwzreg.h

4916

uint32_t num_vdev_stats;

sys/dev/ic/qwzreg.h

4917

uint32_t num_peer_stats;

sys/dev/ic/qwzreg.h

4918

uint32_t num_bcnflt_stats;

sys/dev/ic/qwzreg.h

4919

uint32_t num_chan_stats;

sys/dev/ic/qwzreg.h

4920

uint32_t num_mib_stats;

sys/dev/ic/qwzreg.h

4921

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

4922

uint32_t num_bcn_stats;

sys/dev/ic/qwzreg.h

4923

uint32_t num_peer_extd_stats;

sys/dev/ic/qwzreg.h

4924

uint32_t num_peer_extd2_stats;

sys/dev/ic/qwzreg.h

4928

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

4929

uint32_t rssi_avg_beacon[WMI_MAX_CHAINS];

sys/dev/ic/qwzreg.h

4930

uint32_t rssi_avg_data[WMI_MAX_CHAINS];

sys/dev/ic/qwzreg.h

4935

uint32_t num_per_chain_rssi_stats;

sys/dev/ic/qwzreg.h

4939

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

4940

uint32_t ctl_failsafe_status;

sys/dev/ic/qwzreg.h

4944

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

4945

uint32_t current_switch_count;

sys/dev/ic/qwzreg.h

4946

uint32_t num_vdevs;

sys/dev/ic/qwzreg.h

4950

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

4951

uint32_t detection_mode;

sys/dev/ic/qwzreg.h

4952

uint32_t chan_freq;

sys/dev/ic/qwzreg.h

4953

uint32_t chan_width;

sys/dev/ic/qwzreg.h

4954

uint32_t detector_id;

sys/dev/ic/qwzreg.h

4955

uint32_t segment_id;

sys/dev/ic/qwzreg.h

4956

uint32_t timestamp;

sys/dev/ic/qwzreg.h

4957

uint32_t is_chirp;

sys/dev/ic/qwzreg.h

4965

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

4977

uint32_t chan_freq;

sys/dev/ic/qwzreg.h

4978

uint32_t channel;

sys/dev/ic/qwzreg.h

4979

uint32_t snr;

sys/dev/ic/qwzreg.h

4981

uint32_t rate;

sys/dev/ic/qwzreg.h

4983

uint32_t buf_len;

sys/dev/ic/qwzreg.h

4985

uint32_t flags;

sys/dev/ic/qwzreg.h

4987

uint32_t tsf_delta;

sys/dev/ic/qwzreg.h

4994

uint32_t channel;

sys/dev/ic/qwzreg.h

4995

uint32_t snr;

sys/dev/ic/qwzreg.h

4996

uint32_t rate;

sys/dev/ic/qwzreg.h

4997

uint32_t phy_mode;

sys/dev/ic/qwzreg.h

4998

uint32_t buf_len;

sys/dev/ic/qwzreg.h

4999

uint32_t status;

sys/dev/ic/qwzreg.h

5000

uint32_t rssi_ctl[ATH_MAX_ANTENNA];

sys/dev/ic/qwzreg.h

5001

uint32_t flags;

sys/dev/ic/qwzreg.h

5003

uint32_t tsf_delta;

sys/dev/ic/qwzreg.h

5004

uint32_t rx_tsf_l32;

sys/dev/ic/qwzreg.h

5005

uint32_t rx_tsf_u32;

sys/dev/ic/qwzreg.h

5006

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

5007

uint32_t chan_freq;

sys/dev/ic/qwzreg.h

5013

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5014

uint32_t rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA];

sys/dev/ic/qwzreg.h

5018

uint32_t desc_id;

sys/dev/ic/qwzreg.h

5019

uint32_t status;

sys/dev/ic/qwzreg.h

5020

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

5021

uint32_t ppdu_id;

sys/dev/ic/qwzreg.h

5022

uint32_t ack_rssi;

sys/dev/ic/qwzreg.h

5026

uint32_t event_type; /* %WMI_SCAN_EVENT_ */

sys/dev/ic/qwzreg.h

5027

uint32_t reason; /* %WMI_SCAN_REASON_ */

sys/dev/ic/qwzreg.h

5028

uint32_t channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */

sys/dev/ic/qwzreg.h

5029

uint32_t scan_req_id;

sys/dev/ic/qwzreg.h

5030

uint32_t scan_id;

sys/dev/ic/qwzreg.h

5031

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5037

uint32_t tsf_timestamp;

sys/dev/ic/qwzreg.h

5060

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5061

uint32_t reason;

sys/dev/ic/qwzreg.h

5062

uint32_t rssi;

sys/dev/ic/qwzreg.h

5069

uint32_t err_code;

sys/dev/ic/qwzreg.h

5070

uint32_t freq;

sys/dev/ic/qwzreg.h

5071

uint32_t cmd_flags;

sys/dev/ic/qwzreg.h

5072

uint32_t noise_floor;

sys/dev/ic/qwzreg.h

5073

uint32_t rx_clear_count;

sys/dev/ic/qwzreg.h

5074

uint32_t cycle_count;

sys/dev/ic/qwzreg.h

5075

uint32_t chan_tx_pwr_range;

sys/dev/ic/qwzreg.h

5076

uint32_t chan_tx_pwr_tp;

sys/dev/ic/qwzreg.h

5077

uint32_t rx_frame_count;

sys/dev/ic/qwzreg.h

5078

uint32_t my_bss_rx_cycle_count;

sys/dev/ic/qwzreg.h

5079

uint32_t rx_11b_mode_data_duration;

sys/dev/ic/qwzreg.h

5080

uint32_t tx_frame_cnt;

sys/dev/ic/qwzreg.h

5081

uint32_t mac_clk_mhz;

sys/dev/ic/qwzreg.h

5082

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5086

uint32_t phy_capability;

sys/dev/ic/qwzreg.h

5087

uint32_t max_frag_entry;

sys/dev/ic/qwzreg.h

5088

uint32_t num_rf_chains;

sys/dev/ic/qwzreg.h

5089

uint32_t ht_cap_info;

sys/dev/ic/qwzreg.h

5090

uint32_t vht_cap_info;

sys/dev/ic/qwzreg.h

5091

uint32_t vht_supp_mcs;

sys/dev/ic/qwzreg.h

5092

uint32_t hw_min_tx_power;

sys/dev/ic/qwzreg.h

5093

uint32_t hw_max_tx_power;

sys/dev/ic/qwzreg.h

5094

uint32_t sys_cap_info;

sys/dev/ic/qwzreg.h

5095

uint32_t min_pkt_size_enable;

sys/dev/ic/qwzreg.h

5096

uint32_t max_bcn_ie_size;

sys/dev/ic/qwzreg.h

5097

uint32_t max_num_scan_channels;

sys/dev/ic/qwzreg.h

5098

uint32_t max_supported_macs;

sys/dev/ic/qwzreg.h

5099

uint32_t wmi_fw_sub_feat_caps;

sys/dev/ic/qwzreg.h

5100

uint32_t txrx_chainmask;

sys/dev/ic/qwzreg.h

5101

uint32_t default_dbs_hw_mode_index;

sys/dev/ic/qwzreg.h

5102

uint32_t num_msdu_desc;

sys/dev/ic/qwzreg.h

5151

uint32_t wmm_ac;

sys/dev/ic/qwzreg.h

5152

uint32_t user_priority;

sys/dev/ic/qwzreg.h

5153

uint32_t service_interval;

sys/dev/ic/qwzreg.h

5154

uint32_t suspend_interval;

sys/dev/ic/qwzreg.h

5155

uint32_t delay_interval;

sys/dev/ic/qwzreg.h

5159

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5161

uint32_t num_ac;

sys/dev/ic/qwzreg.h

5165

uint32_t wmm_ac;

sys/dev/ic/qwzreg.h

5166

uint32_t user_priority;

sys/dev/ic/qwzreg.h

5167

uint32_t service_interval;

sys/dev/ic/qwzreg.h

5168

uint32_t suspend_interval;

sys/dev/ic/qwzreg.h

5169

uint32_t delay_interval;

sys/dev/ic/qwzreg.h

5333

uint32_t eeprom_rd;

sys/dev/ic/qwzreg.h

5334

uint32_t eeprom_rd_ext;

sys/dev/ic/qwzreg.h

5335

uint32_t regcap1;

sys/dev/ic/qwzreg.h

5336

uint32_t regcap2;

sys/dev/ic/qwzreg.h

5337

uint32_t wireless_modes;

sys/dev/ic/qwzreg.h

5338

uint32_t low_2ghz_chan;

sys/dev/ic/qwzreg.h

5339

uint32_t high_2ghz_chan;

sys/dev/ic/qwzreg.h

5340

uint32_t low_5ghz_chan;

sys/dev/ic/qwzreg.h

5341

uint32_t high_5ghz_chan;

sys/dev/ic/qwzreg.h

5347

uint32_t len;

sys/dev/ic/qwzreg.h

5348

uint32_t req_id;

sys/dev/ic/qwzreg.h

5366

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5367

uint32_t cwmin;

sys/dev/ic/qwzreg.h

5368

uint32_t cwmax;

sys/dev/ic/qwzreg.h

5369

uint32_t aifs;

sys/dev/ic/qwzreg.h

5370

uint32_t txoplimit;

sys/dev/ic/qwzreg.h

5371

uint32_t acm;

sys/dev/ic/qwzreg.h

5372

uint32_t no_ack;

sys/dev/ic/qwzreg.h

5385

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5386

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5388

uint32_t wmm_param_type;

sys/dev/ic/qwzreg.h

5415

uint32_t sta_cong_timer_ms;

sys/dev/ic/qwzreg.h

5416

uint32_t mbss_support;

sys/dev/ic/qwzreg.h

5417

uint32_t default_slot_size;

sys/dev/ic/qwzreg.h

5418

uint32_t congestion_thresh_setup;

sys/dev/ic/qwzreg.h

5419

uint32_t congestion_thresh_teardown;

sys/dev/ic/qwzreg.h

5420

uint32_t congestion_thresh_critical;

sys/dev/ic/qwzreg.h

5421

uint32_t interference_thresh_teardown;

sys/dev/ic/qwzreg.h

5422

uint32_t interference_thresh_setup;

sys/dev/ic/qwzreg.h

5423

uint32_t min_no_sta_setup;

sys/dev/ic/qwzreg.h

5424

uint32_t min_no_sta_teardown;

sys/dev/ic/qwzreg.h

5425

uint32_t no_of_bcast_mcast_slots;

sys/dev/ic/qwzreg.h

5426

uint32_t min_no_twt_slots;

sys/dev/ic/qwzreg.h

5427

uint32_t max_no_sta_twt;

sys/dev/ic/qwzreg.h

5428

uint32_t mode_check_interval;

sys/dev/ic/qwzreg.h

5429

uint32_t add_sta_slot_interval;

sys/dev/ic/qwzreg.h

5430

uint32_t remove_sta_slot_interval;

sys/dev/ic/qwzreg.h

5434

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5435

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

5436

uint32_t sta_cong_timer_ms;

sys/dev/ic/qwzreg.h

5437

uint32_t mbss_support;

sys/dev/ic/qwzreg.h

5438

uint32_t default_slot_size;

sys/dev/ic/qwzreg.h

5439

uint32_t congestion_thresh_setup;

sys/dev/ic/qwzreg.h

5440

uint32_t congestion_thresh_teardown;

sys/dev/ic/qwzreg.h

5441

uint32_t congestion_thresh_critical;

sys/dev/ic/qwzreg.h

5442

uint32_t interference_thresh_teardown;

sys/dev/ic/qwzreg.h

5443

uint32_t interference_thresh_setup;

sys/dev/ic/qwzreg.h

5444

uint32_t min_no_sta_setup;

sys/dev/ic/qwzreg.h

5445

uint32_t min_no_sta_teardown;

sys/dev/ic/qwzreg.h

5446

uint32_t no_of_bcast_mcast_slots;

sys/dev/ic/qwzreg.h

5447

uint32_t min_no_twt_slots;

sys/dev/ic/qwzreg.h

5448

uint32_t max_no_sta_twt;

sys/dev/ic/qwzreg.h

5449

uint32_t mode_check_interval;

sys/dev/ic/qwzreg.h

5450

uint32_t add_sta_slot_interval;

sys/dev/ic/qwzreg.h

5451

uint32_t remove_sta_slot_interval;

sys/dev/ic/qwzreg.h

5455

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5456

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

5476

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5477

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5479

uint32_t dialog_id;

sys/dev/ic/qwzreg.h

5480

uint32_t wake_intvl_us;

sys/dev/ic/qwzreg.h

5481

uint32_t wake_intvl_mantis;

sys/dev/ic/qwzreg.h

5482

uint32_t wake_dura_us;

sys/dev/ic/qwzreg.h

5483

uint32_t sp_offset_us;

sys/dev/ic/qwzreg.h

5484

uint32_t flags;

sys/dev/ic/qwzreg.h

5488

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5490

uint32_t dialog_id;

sys/dev/ic/qwzreg.h

5491

uint32_t wake_intvl_us;

sys/dev/ic/qwzreg.h

5492

uint32_t wake_intvl_mantis;

sys/dev/ic/qwzreg.h

5493

uint32_t wake_dura_us;

sys/dev/ic/qwzreg.h

5494

uint32_t sp_offset_us;

sys/dev/ic/qwzreg.h

5516

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5518

uint32_t dialog_id;

sys/dev/ic/qwzreg.h

5519

uint32_t status;

sys/dev/ic/qwzreg.h

5523

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5525

uint32_t dialog_id;

sys/dev/ic/qwzreg.h

5529

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5530

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5532

uint32_t dialog_id;

sys/dev/ic/qwzreg.h

5536

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5538

uint32_t dialog_id;

sys/dev/ic/qwzreg.h

5542

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5543

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5545

uint32_t dialog_id;

sys/dev/ic/qwzreg.h

5549

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5551

uint32_t dialog_id;

sys/dev/ic/qwzreg.h

5552

uint32_t sp_offset_us;

sys/dev/ic/qwzreg.h

5553

uint32_t next_twt_size;

sys/dev/ic/qwzreg.h

5557

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5558

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5560

uint32_t dialog_id;

sys/dev/ic/qwzreg.h

5561

uint32_t sp_offset_us;

sys/dev/ic/qwzreg.h

5562

uint32_t next_twt_size;

sys/dev/ic/qwzreg.h

5566

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5567

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

5568

uint32_t enable;

sys/dev/ic/qwzreg.h

5571

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5575

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5576

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

5577

uint32_t bitmap[2];

sys/dev/ic/qwzreg.h

5595

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5596

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5597

uint32_t flags;

sys/dev/ic/qwzreg.h

5598

uint32_t evt_type;

sys/dev/ic/qwzreg.h

5599

uint32_t current_bss_color;

sys/dev/ic/qwzreg.h

5600

uint32_t detection_period_ms;

sys/dev/ic/qwzreg.h

5601

uint32_t scan_period_ms;

sys/dev/ic/qwzreg.h

5602

uint32_t free_slot_expiry_time_ms;

sys/dev/ic/qwzreg.h

5606

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5607

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5608

uint32_t enable;

sys/dev/ic/qwzreg.h

5612

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5613

uint32_t evt_type;

sys/dev/ic/qwzreg.h

5621

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5622

uint32_t lro_enable;

sys/dev/ic/qwzreg.h

5623

uint32_t res;

sys/dev/ic/qwzreg.h

5624

uint32_t th_4[ATH12K_IPV4_TH_SEED_SIZE];

sys/dev/ic/qwzreg.h

5625

uint32_t th_6[ATH12K_IPV6_TH_SEED_SIZE];

sys/dev/ic/qwzreg.h

5626

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

5649

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5650

uint32_t scan_count;

sys/dev/ic/qwzreg.h

5651

uint32_t scan_period;

sys/dev/ic/qwzreg.h

5652

uint32_t scan_priority;

sys/dev/ic/qwzreg.h

5653

uint32_t scan_fft_size;

sys/dev/ic/qwzreg.h

5654

uint32_t scan_gc_ena;

sys/dev/ic/qwzreg.h

5655

uint32_t scan_restart_ena;

sys/dev/ic/qwzreg.h

5656

uint32_t scan_noise_floor_ref;

sys/dev/ic/qwzreg.h

5657

uint32_t scan_init_delay;

sys/dev/ic/qwzreg.h

5658

uint32_t scan_nb_tone_thr;

sys/dev/ic/qwzreg.h

5659

uint32_t scan_str_bin_thr;

sys/dev/ic/qwzreg.h

5660

uint32_t scan_wb_rpt_mode;

sys/dev/ic/qwzreg.h

5661

uint32_t scan_rssi_rpt_mode;

sys/dev/ic/qwzreg.h

5662

uint32_t scan_rssi_thr;

sys/dev/ic/qwzreg.h

5663

uint32_t scan_pwr_format;

sys/dev/ic/qwzreg.h

5664

uint32_t scan_rpt_mode;

sys/dev/ic/qwzreg.h

5665

uint32_t scan_bin_scale;

sys/dev/ic/qwzreg.h

5666

uint32_t scan_dbm_adj;

sys/dev/ic/qwzreg.h

5667

uint32_t scan_chn_mask;

sys/dev/ic/qwzreg.h

5671

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5681

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5682

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5683

uint32_t trigger_cmd;

sys/dev/ic/qwzreg.h

5684

uint32_t enable_cmd;

sys/dev/ic/qwzreg.h

5688

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5689

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

5690

uint32_t module_id; /* see enum wmi_direct_buffer_module */

sys/dev/ic/qwzreg.h

5691

uint32_t base_paddr_lo;

sys/dev/ic/qwzreg.h

5692

uint32_t base_paddr_hi;

sys/dev/ic/qwzreg.h

5693

uint32_t head_idx_paddr_lo;

sys/dev/ic/qwzreg.h

5694

uint32_t head_idx_paddr_hi;

sys/dev/ic/qwzreg.h

5695

uint32_t tail_idx_paddr_lo;

sys/dev/ic/qwzreg.h

5696

uint32_t tail_idx_paddr_hi;

sys/dev/ic/qwzreg.h

5697

uint32_t num_elems; /* Number of elems in the ring */

sys/dev/ic/qwzreg.h

5698

uint32_t buf_size; /* size of allocated buffer in bytes */

sys/dev/ic/qwzreg.h

5701

uint32_t num_resp_per_event;

sys/dev/ic/qwzreg.h

5706

uint32_t event_timeout_ms;

sys/dev/ic/qwzreg.h

5710

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

5711

uint32_t module_id;

sys/dev/ic/qwzreg.h

5712

uint32_t num_buf_release_entry;

sys/dev/ic/qwzreg.h

5713

uint32_t num_meta_data_entry;

sys/dev/ic/qwzreg.h

5717

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5718

uint32_t paddr_lo;

sys/dev/ic/qwzreg.h

5723

uint32_t paddr_hi;

sys/dev/ic/qwzreg.h

5732

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5734

uint32_t reset_delay;

sys/dev/ic/qwzreg.h

5735

uint32_t freq1;

sys/dev/ic/qwzreg.h

5736

uint32_t freq2;

sys/dev/ic/qwzreg.h

5737

uint32_t ch_width;

sys/dev/ic/qwzreg.h

5746

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5747

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5748

uint32_t interval;

sys/dev/ic/qwzreg.h

5749

uint32_t config; /* enum wmi_fils_discovery_cmd_type */

sys/dev/ic/qwzreg.h

5753

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5754

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5755

uint32_t buf_len;

sys/dev/ic/qwzreg.h

5759

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5760

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5761

uint32_t buf_len;

sys/dev/ic/qwzreg.h

5765

uint32_t num_vdevs;

sys/dev/ic/qwzreg.h

5766

uint32_t num_peers;

sys/dev/ic/qwzreg.h

5767

uint32_t num_active_peers;

sys/dev/ic/qwzreg.h

5768

uint32_t num_offload_peers;

sys/dev/ic/qwzreg.h

5769

uint32_t num_offload_reorder_buffs;

sys/dev/ic/qwzreg.h

5770

uint32_t num_peer_keys;

sys/dev/ic/qwzreg.h

5771

uint32_t num_tids;

sys/dev/ic/qwzreg.h

5772

uint32_t ast_skid_limit;

sys/dev/ic/qwzreg.h

5773

uint32_t tx_chain_mask;

sys/dev/ic/qwzreg.h

5774

uint32_t rx_chain_mask;

sys/dev/ic/qwzreg.h

5775

uint32_t rx_timeout_pri[4];

sys/dev/ic/qwzreg.h

5776

uint32_t rx_decap_mode;

sys/dev/ic/qwzreg.h

5777

uint32_t scan_max_pending_req;

sys/dev/ic/qwzreg.h

5778

uint32_t bmiss_offload_max_vdev;

sys/dev/ic/qwzreg.h

5779

uint32_t roam_offload_max_vdev;

sys/dev/ic/qwzreg.h

5780

uint32_t roam_offload_max_ap_profiles;

sys/dev/ic/qwzreg.h

5781

uint32_t num_mcast_groups;

sys/dev/ic/qwzreg.h

5782

uint32_t num_mcast_table_elems;

sys/dev/ic/qwzreg.h

5783

uint32_t mcast2ucast_mode;

sys/dev/ic/qwzreg.h

5784

uint32_t tx_dbg_log_size;

sys/dev/ic/qwzreg.h

5785

uint32_t num_wds_entries;

sys/dev/ic/qwzreg.h

5786

uint32_t dma_burst_size;

sys/dev/ic/qwzreg.h

5787

uint32_t mac_aggr_delim;

sys/dev/ic/qwzreg.h

5788

uint32_t rx_skip_defrag_timeout_dup_detection_check;

sys/dev/ic/qwzreg.h

5789

uint32_t vow_config;

sys/dev/ic/qwzreg.h

5790

uint32_t gtk_offload_max_vdev;

sys/dev/ic/qwzreg.h

5791

uint32_t num_msdu_desc;

sys/dev/ic/qwzreg.h

5792

uint32_t max_frag_entries;

sys/dev/ic/qwzreg.h

5793

uint32_t max_peer_ext_stats;

sys/dev/ic/qwzreg.h

5794

uint32_t smart_ant_cap;

sys/dev/ic/qwzreg.h

5795

uint32_t bk_minfree;

sys/dev/ic/qwzreg.h

5796

uint32_t be_minfree;

sys/dev/ic/qwzreg.h

5797

uint32_t vi_minfree;

sys/dev/ic/qwzreg.h

5798

uint32_t vo_minfree;

sys/dev/ic/qwzreg.h

5799

uint32_t rx_batchmode;

sys/dev/ic/qwzreg.h

5800

uint32_t tt_support;

sys/dev/ic/qwzreg.h

5801

uint32_t flag1;

sys/dev/ic/qwzreg.h

5802

uint32_t iphdr_pad_config;

sys/dev/ic/qwzreg.h

5803

uint32_t qwrap_config:16,

sys/dev/ic/qwzreg.h

5805

uint32_t num_tdls_vdevs;

sys/dev/ic/qwzreg.h

5806

uint32_t num_tdls_conn_table_entries;

sys/dev/ic/qwzreg.h

5807

uint32_t beacon_tx_offload_max_vdev;

sys/dev/ic/qwzreg.h

5808

uint32_t num_multicast_filter_entries;

sys/dev/ic/qwzreg.h

5809

uint32_t num_wow_filters;

sys/dev/ic/qwzreg.h

5810

uint32_t num_keep_alive_pattern;

sys/dev/ic/qwzreg.h

5811

uint32_t keep_alive_pattern_size;

sys/dev/ic/qwzreg.h

5812

uint32_t max_tdls_concurrent_sleep_sta;

sys/dev/ic/qwzreg.h

5813

uint32_t max_tdls_concurrent_buffer_sta;

sys/dev/ic/qwzreg.h

5814

uint32_t wmi_send_separate;

sys/dev/ic/qwzreg.h

5815

uint32_t num_ocb_vdevs;

sys/dev/ic/qwzreg.h

5816

uint32_t num_ocb_channels;

sys/dev/ic/qwzreg.h

5817

uint32_t num_ocb_schedules;

sys/dev/ic/qwzreg.h

5818

uint32_t num_ns_ext_tuples_cfg;

sys/dev/ic/qwzreg.h

5819

uint32_t bpf_instruction_size;

sys/dev/ic/qwzreg.h

5820

uint32_t max_bssid_rx_filters;

sys/dev/ic/qwzreg.h

5821

uint32_t use_pdev_id;

sys/dev/ic/qwzreg.h

5822

uint32_t peer_map_unmap_support;

sys/dev/ic/qwzreg.h

5823

uint32_t sched_params;

sys/dev/ic/qwzreg.h

5824

uint32_t twt_ap_pdev_count;

sys/dev/ic/qwzreg.h

5825

uint32_t twt_ap_sta_count;

sys/dev/ic/qwzreg.h

5827

uint32_t ema_max_vap_cnt;

sys/dev/ic/qwzreg.h

5828

uint32_t ema_max_profile_period;

sys/dev/ic/qwzreg.h

5841

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5842

uint32_t dbg_log_param;

sys/dev/ic/qwzreg.h

5843

uint32_t value;

sys/dev/ic/qwzreg.h

5867

uint32_t peer_ps_state;

sys/dev/ic/qwzreg.h

5868

uint32_t ps_supported_bitmap;

sys/dev/ic/qwzreg.h

5869

uint32_t peer_ps_valid;

sys/dev/ic/qwzreg.h

5870

uint32_t peer_ps_timestamp;

sys/dev/ic/qwzreg.h

5880

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

5881

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

5882

uint32_t enable;

sys/dev/ic/qwzreg.h

5883

uint32_t hw_filter_bitmap;

sys/dev/ic/qwzreg.h

6031

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

6032

uint32_t flag;

sys/dev/ic/qwzreg.h

6034

uint32_t data_len;

sys/dev/ic/qwzreg.h

6063

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

6064

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

6065

uint32_t is_add;

sys/dev/ic/qwzreg.h

6066

uint32_t event_bitmap;

sys/dev/ic/qwzreg.h

6070

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

6071

uint32_t enable;

sys/dev/ic/qwzreg.h

6072

uint32_t pause_iface_config;

sys/dev/ic/qwzreg.h

6073

uint32_t flags;

sys/dev/ic/qwzreg.h

6077

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

6078

uint32_t reserved;

sys/dev/ic/qwzreg.h

6082

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

6083

uint32_t flag;

sys/dev/ic/qwzreg.h

6084

uint32_t wake_reason;

sys/dev/ic/qwzreg.h

6085

uint32_t data_len;

sys/dev/ic/qwzreg.h

6089

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

6092

uint32_t pattern_offset;

sys/dev/ic/qwzreg.h

6093

uint32_t pattern_len;

sys/dev/ic/qwzreg.h

6094

uint32_t bitmask_len;

sys/dev/ic/qwzreg.h

6095

uint32_t pattern_id;

sys/dev/ic/qwzreg.h

6099

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

6100

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

6101

uint32_t pattern_id;

sys/dev/ic/qwzreg.h

6102

uint32_t pattern_type;

sys/dev/ic/qwzreg.h

6106

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

6107

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

6108

uint32_t pattern_id;

sys/dev/ic/qwzreg.h

6109

uint32_t pattern_type;

sys/dev/ic/qwzreg.h

6158

uint32_t valid;

sys/dev/ic/qwzreg.h

6163

uint32_t valid;

sys/dev/ic/qwzreg.h

6164

uint32_t enc_type;

sys/dev/ic/qwzreg.h

6168

uint32_t valid;

sys/dev/ic/qwzreg.h

6169

uint32_t auth_type;

sys/dev/ic/qwzreg.h

6173

uint32_t valid;

sys/dev/ic/qwzreg.h

6174

uint32_t bcast_nw_type;

sys/dev/ic/qwzreg.h

6178

uint32_t valid;

sys/dev/ic/qwzreg.h

6184

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

6196

uint32_t authentication;

sys/dev/ic/qwzreg.h

6197

uint32_t encryption;

sys/dev/ic/qwzreg.h

6198

uint32_t bcast_nw_type;

sys/dev/ic/qwzreg.h

6209

uint32_t fast_scan_period;

sys/dev/ic/qwzreg.h

6210

uint32_t slow_scan_period;

sys/dev/ic/qwzreg.h

6215

uint32_t delay_start_time;

sys/dev/ic/qwzreg.h

6216

uint32_t active_min_time;

sys/dev/ic/qwzreg.h

6217

uint32_t active_max_time;

sys/dev/ic/qwzreg.h

6218

uint32_t passive_min_time;

sys/dev/ic/qwzreg.h

6219

uint32_t passive_max_time;

sys/dev/ic/qwzreg.h

6222

uint32_t enable_pno_scan_randomization;

sys/dev/ic/qwzreg.h

6228

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

6229

uint32_t flags;

sys/dev/ic/qwzreg.h

6230

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

6231

uint32_t fast_scan_max_cycles;

sys/dev/ic/qwzreg.h

6232

uint32_t active_dwell_time;

sys/dev/ic/qwzreg.h

6233

uint32_t passive_dwell_time;

sys/dev/ic/qwzreg.h

6234

uint32_t probe_bundle_size;

sys/dev/ic/qwzreg.h

6237

uint32_t rest_time;

sys/dev/ic/qwzreg.h

6240

uint32_t max_rest_time;

sys/dev/ic/qwzreg.h

6243

uint32_t scan_backoff_multiplier;

sys/dev/ic/qwzreg.h

6246

uint32_t fast_scan_period;

sys/dev/ic/qwzreg.h

6249

uint32_t slow_scan_period;

sys/dev/ic/qwzreg.h

6251

uint32_t no_of_ssids;

sys/dev/ic/qwzreg.h

6253

uint32_t num_of_channels;

sys/dev/ic/qwzreg.h

6256

uint32_t delay_start_time;

sys/dev/ic/qwzreg.h

6265

uint32_t ie_bitmap[8];

sys/dev/ic/qwzreg.h

6268

uint32_t num_vendor_oui;

sys/dev/ic/qwzreg.h

6271

uint32_t num_cnlo_band_pref;

sys/dev/ic/qwzreg.h

6287

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

6288

uint32_t flags;

sys/dev/ic/qwzreg.h

6302

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

6303

uint32_t flags;

sys/dev/ic/qwzreg.h

6311

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

6312

uint32_t flags;

sys/dev/ic/qwzreg.h

6313

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

6314

uint32_t num_ns_ext_tuples;

sys/dev/ic/qwzreg.h

6337

uint32_t word0;

sys/dev/ic/qwzreg.h

6338

uint32_t word1;

sys/dev/ic/qwzreg.h

6344

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

6345

uint32_t flags;

sys/dev/ic/qwzreg.h

6346

uint32_t refresh_cnt;

sys/dev/ic/qwzreg.h

6359

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

6360

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

6361

uint32_t flags;

sys/dev/ic/qwzreg.h

6372

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

6373

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

6374

uint32_t sar_len;

sys/dev/ic/qwzreg.h

6375

uint32_t rsvd_len;

sys/dev/ic/qwzreg.h

6379

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

6380

uint32_t pdev_id;

sys/dev/ic/qwzreg.h

6381

uint32_t rsvd_len;

sys/dev/ic/qwzreg.h

6385

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

6386

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

6387

uint32_t enabled;

sys/dev/ic/qwzreg.h

6390

uint32_t method;

sys/dev/ic/qwzreg.h

6393

uint32_t interval;

sys/dev/ic/qwzreg.h

6401

uint32_t tlv_header;

sys/dev/ic/qwzreg.h

6402

uint32_t src_ip4_addr;

sys/dev/ic/qwzreg.h

6403

uint32_t dest_ip4_addr;

sys/dev/ic/qwzreg.h

6408

uint32_t vdev_id;

sys/dev/ic/qwzreg.h

6409

uint32_t enabled;

sys/dev/ic/qwzreg.h

6410

uint32_t method;

sys/dev/ic/qwzreg.h

6411

uint32_t interval;

sys/dev/ic/qwzreg.h

6412

uint32_t src_ip4_addr;

sys/dev/ic/qwzreg.h

6413

uint32_t dest_ip4_addr;

sys/dev/ic/qwzreg.h

6437

uint32_t version;

sys/dev/ic/qwzreg.h

6438

uint32_t type;

sys/dev/ic/qwzreg.h

6439

uint32_t src_node_id;

sys/dev/ic/qwzreg.h

6440

uint32_t src_port_id;

sys/dev/ic/qwzreg.h

6441

uint32_t confirm_rx;

sys/dev/ic/qwzreg.h

6442

uint32_t size;

sys/dev/ic/qwzreg.h

6443

uint32_t dst_node_id;

sys/dev/ic/qwzreg.h

6444

uint32_t dst_port_id;

sys/dev/ic/qwzreg.h

6452

uint32_t size;

sys/dev/ic/qwzreg.h

6460

uint32_t cmd;

sys/dev/ic/qwzreg.h

6464

uint32_t service;

sys/dev/ic/qwzreg.h

6465

uint32_t instance;

sys/dev/ic/qwzreg.h

6466

uint32_t node;

sys/dev/ic/qwzreg.h

6467

uint32_t port;

sys/dev/ic/qwzreg.h

6470

uint32_t node;

sys/dev/ic/qwzreg.h

6471

uint32_t port;

sys/dev/ic/qwzreg.h

6533

uint32_t elem_len;

sys/dev/ic/qwzreg.h

6534

uint32_t elem_size;

sys/dev/ic/qwzreg.h

6537

uint32_t offset;

sys/dev/ic/qwzreg.h

6573

uint32_t board_id;

sys/dev/ic/qwzreg.h

6596

uint32_t client_id;

sys/dev/ic/qwzreg.h

6604

uint32_t rejuvenate_enable;

sys/dev/ic/qwzreg.h

6663

uint32_t num_clients;

sys/dev/ic/qwzreg.h

6665

uint32_t wake_msi;

sys/dev/ic/qwzreg.h

6667

uint32_t gpios_len;

sys/dev/ic/qwzreg.h

6668

uint32_t gpios[QMI_WLFW_MAX_NUM_GPIO_V01];

sys/dev/ic/qwzreg.h

6686

uint32_t mem_bucket;

sys/dev/ic/qwzreg.h

6756

uint32_t size;

sys/dev/ic/qwzreg.h

6772

uint32_t size;

sys/dev/ic/qwzreg.h

6774

uint32_t mem_cfg_len;

sys/dev/ic/qwzreg.h

6779

uint32_t mem_seg_len;

sys/dev/ic/qwzreg.h

6785

uint32_t size;

sys/dev/ic/qwzreg.h

6791

uint32_t mem_seg_len;

sys/dev/ic/qwzreg.h

6830

uint32_t pipe_num;

sys/dev/ic/qwzreg.h

6831

uint32_t pipe_dir;

sys/dev/ic/qwzreg.h

6832

uint32_t nentries;

sys/dev/ic/qwzreg.h

6833

uint32_t nbytes_max;

sys/dev/ic/qwzreg.h

6834

uint32_t flags;

sys/dev/ic/qwzreg.h

6838

uint32_t service_id;

sys/dev/ic/qwzreg.h

6839

uint32_t pipe_dir;

sys/dev/ic/qwzreg.h

6840

uint32_t pipe_num;

sys/dev/ic/qwzreg.h

6849

uint32_t addr;

sys/dev/ic/qwzreg.h

6854

uint32_t size;

sys/dev/ic/qwzreg.h

6859

uint32_t chip_id;

sys/dev/ic/qwzreg.h

6860

uint32_t chip_family;

sys/dev/ic/qwzreg.h

6864

uint32_t board_id;

sys/dev/ic/qwzreg.h

6868

uint32_t soc_id;

sys/dev/ic/qwzreg.h

6872

uint32_t fw_version;

sys/dev/ic/qwzreg.h

6913

uint32_t voltage_mv;

sys/dev/ic/qwzreg.h

6915

uint32_t time_freq_hz;

sys/dev/ic/qwzreg.h

6917

uint32_t otp_version;

sys/dev/ic/qwzreg.h

6919

uint32_t eeprom_read_timeout;

sys/dev/ic/qwzreg.h

6944

uint32_t total_size;

sys/dev/ic/qwzreg.h

6946

uint32_t seg_id;

sys/dev/ic/qwzreg.h

6948

uint32_t data_len;

sys/dev/ic/qwzreg.h

6967

uint32_t size;

sys/dev/ic/qwzreg.h

6992

uint32_t mode;

sys/dev/ic/qwzreg.h

7005

uint32_t tgt_cfg_len;

sys/dev/ic/qwzreg.h

7009

uint32_t svc_cfg_len;

sys/dev/ic/qwzreg.h

7013

uint32_t shadow_reg_len;

sys/dev/ic/qwzreg.h

7017

uint32_t shadow_reg_v3_len;

sys/dev/ic/qwzreg.h

7643

uint32_t info0;

sys/dev/ic/qwzreg.h

7644

uint32_t info1;

sys/dev/ic/qwzreg.h

8108

uint32_t tl;

sys/dev/ic/qwzreg.h

8137

uint32_t info0; /* %RX_MPDU_DESC_INFO */

sys/dev/ic/qwzreg.h

8138

uint32_t meta_data;

sys/dev/ic/qwzreg.h

8223

uint32_t info0;

sys/dev/ic/qwzreg.h

8224

uint32_t rsvd0;

sys/dev/ic/qwzreg.h

8284

uint32_t info0;

sys/dev/ic/qwzreg.h

8411

uint32_t queue_addr_lo;

sys/dev/ic/qwzreg.h

8412

uint32_t info0; /* %HAL_REO_DEST_RING_INFO0_ */

sys/dev/ic/qwzreg.h

8413

uint32_t info1; /* %HAL_REO_DEST_RING_INFO1_ */

sys/dev/ic/qwzreg.h

8414

uint32_t rsvd0;

sys/dev/ic/qwzreg.h

8415

uint32_t rsvd1;

sys/dev/ic/qwzreg.h

8416

uint32_t rsvd2;

sys/dev/ic/qwzreg.h

8417

uint32_t rsvd3;

sys/dev/ic/qwzreg.h

8418

uint32_t rsvd4;

sys/dev/ic/qwzreg.h

8419

uint32_t rsvd5;

sys/dev/ic/qwzreg.h

8420

uint32_t info2; /* %HAL_REO_DEST_RING_INFO2_ */

sys/dev/ic/qwzreg.h

8488

uint32_t buf_va_lo;

sys/dev/ic/qwzreg.h

8489

uint32_t buf_va_hi;

sys/dev/ic/qwzreg.h

8490

uint32_t info0; /* %HAL_REO_DEST_RING_INFO0_ */

sys/dev/ic/qwzreg.h

8594

uint32_t queue_addr_lo;

sys/dev/ic/qwzreg.h

8595

uint32_t info0; /* %HAL_REO_ENTR_RING_INFO0_ */

sys/dev/ic/qwzreg.h

8596

uint32_t info1; /* %HAL_REO_ENTR_RING_INFO1_ */

sys/dev/ic/qwzreg.h

8597

uint32_t info2; /* %HAL_REO_DEST_RING_INFO2_ */

sys/dev/ic/qwzreg.h

8673

uint32_t info0;

sys/dev/ic/qwzreg.h

8674

uint32_t info1;

sys/dev/ic/qwzreg.h

8681

uint32_t info0;

sys/dev/ic/qwzreg.h

8747

uint32_t addr_lo;

sys/dev/ic/qwzreg.h

8748

uint32_t flag;

sys/dev/ic/qwzreg.h

8749

uint32_t upd0;

sys/dev/ic/qwzreg.h

8750

uint32_t upd1;

sys/dev/ic/qwzreg.h

8751

uint32_t upd2;

sys/dev/ic/qwzreg.h

8752

uint32_t pn[4];

sys/dev/ic/qwzreg.h

8768

uint32_t queue_addr_lo;

sys/dev/ic/qwzreg.h

8769

uint32_t info0;

sys/dev/ic/qwzreg.h

8770

uint32_t rsvd0[6];

sys/dev/ic/qwzreg.h

8771

uint32_t tlv64_pad;

sys/dev/ic/qwzreg.h

8811

uint32_t desc_addr_lo;

sys/dev/ic/qwzreg.h

8812

uint32_t info0;

sys/dev/ic/qwzreg.h

8813

uint32_t rsvd0[6];

sys/dev/ic/qwzreg.h

8826

uint32_t cache_addr_lo;

sys/dev/ic/qwzreg.h

8827

uint32_t info0;

sys/dev/ic/qwzreg.h

8828

uint32_t rsvd0[6];

sys/dev/ic/qwzreg.h

8903

uint32_t info0;

sys/dev/ic/qwzreg.h

8904

uint32_t info1;

sys/dev/ic/qwzreg.h

8905

uint32_t info2;

sys/dev/ic/qwzreg.h

8906

uint32_t info3;

sys/dev/ic/qwzreg.h

8907

uint32_t info4;

sys/dev/ic/qwzreg.h

8908

uint32_t info5;

sys/dev/ic/qwzreg.h

9107

uint32_t ctrl_buf_addr_lo;

sys/dev/ic/qwzreg.h

9108

uint32_t info0;

sys/dev/ic/qwzreg.h

9109

uint32_t meta_data[2];

sys/dev/ic/qwzreg.h

9110

uint32_t rsvd0[2];

sys/dev/ic/qwzreg.h

9111

uint32_t info1;

sys/dev/ic/qwzreg.h

9156

uint32_t info0;

sys/dev/ic/qwzreg.h

9157

uint32_t msdu_byte_count;

sys/dev/ic/qwzreg.h

9158

uint32_t msdu_timestamp;

sys/dev/ic/qwzreg.h

9159

uint32_t meta_data[2];

sys/dev/ic/qwzreg.h

9160

uint32_t info1;

sys/dev/ic/qwzreg.h

9161

uint32_t rsvd0;

sys/dev/ic/qwzreg.h

9162

uint32_t info2;

sys/dev/ic/qwzreg.h

9201

uint32_t buffer_addr_low;

sys/dev/ic/qwzreg.h

9202

uint32_t buffer_addr_info; /* %HAL_CE_SRC_DESC_ADDR_INFO_ */

sys/dev/ic/qwzreg.h

9203

uint32_t meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */

sys/dev/ic/qwzreg.h

9204

uint32_t flags; /* %HAL_CE_SRC_DESC_FLAGS_ */

sys/dev/ic/qwzreg.h

9290

uint32_t buffer_addr_low;

sys/dev/ic/qwzreg.h

9291

uint32_t buffer_addr_info; /* %HAL_CE_DEST_DESC_ADDR_INFO_ */

sys/dev/ic/qwzreg.h

9345

uint32_t flags; /* %HAL_CE_DST_STATUS_DESC_FLAGS_ */

sys/dev/ic/qwzreg.h

9346

uint32_t toeplitz_hash0;

sys/dev/ic/qwzreg.h

9347

uint32_t toeplitz_hash1;

sys/dev/ic/qwzreg.h

9348

uint32_t meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */

sys/dev/ic/qwzreg.h

9449

uint32_t info0;

sys/dev/ic/qwzreg.h

9450

uint32_t tsf;

sys/dev/ic/qwzreg.h

9558

uint32_t info0;

sys/dev/ic/qwzreg.h

9559

uint32_t info1;

sys/dev/ic/qwzreg.h

9560

uint32_t info2;

sys/dev/ic/qwzreg.h

9562

uint32_t info3;

sys/dev/ic/qwzreg.h

9784

uint32_t info0;

sys/dev/ic/qwzreg.h

9802

uint32_t info0;

sys/dev/ic/qwzreg.h

9803

uint32_t pn[4];

sys/dev/ic/qwzreg.h

9809

uint32_t rsvd;

sys/dev/ic/qwzreg.h

9872

uint32_t rx_queue_num;

sys/dev/ic/qwzreg.h

9873

uint32_t info0;

sys/dev/ic/qwzreg.h

9874

uint32_t info1;

sys/dev/ic/qwzreg.h

9875

uint32_t pn[4];

sys/dev/ic/qwzreg.h

9876

uint32_t last_rx_enqueue_timestamp;

sys/dev/ic/qwzreg.h

9877

uint32_t last_rx_dequeue_timestamp;

sys/dev/ic/qwzreg.h

9878

uint32_t next_aging_queue[2];

sys/dev/ic/qwzreg.h

9879

uint32_t prev_aging_queue[2];

sys/dev/ic/qwzreg.h

9880

uint32_t rx_bitmap[8];

sys/dev/ic/qwzreg.h

9881

uint32_t info2;

sys/dev/ic/qwzreg.h

9882

uint32_t info3;

sys/dev/ic/qwzreg.h

9883

uint32_t info4;

sys/dev/ic/qwzreg.h

9884

uint32_t processed_mpdus;

sys/dev/ic/qwzreg.h

9885

uint32_t processed_msdus;

sys/dev/ic/qwzreg.h

9886

uint32_t processed_total_bytes;

sys/dev/ic/qwzreg.h

9887

uint32_t info5;

sys/dev/ic/qwzreg.h

9888

uint32_t rsvd[3];

sys/dev/ic/qwzvar.h

1082

uint32_t num_users;

sys/dev/ic/qwzvar.h

1083

uint32_t bank_config;

sys/dev/ic/qwzvar.h

1090

uint32_t tx_num;

sys/dev/ic/qwzvar.h

1091

uint32_t timer_tx_num;

sys/dev/ic/qwzvar.h

1092

uint32_t ring_id;

sys/dev/ic/qwzvar.h

1093

uint32_t interval;

sys/dev/ic/qwzvar.h

1101

uint32_t cookie;

sys/dev/ic/qwzvar.h

1102

uint32_t magic;

sys/dev/ic/qwzvar.h

1111

uint32_t desc_id; /* Cookie */

sys/dev/ic/qwzvar.h

1125

uint32_t *vaddr;

sys/dev/ic/qwzvar.h

1127

uint32_t size;

sys/dev/ic/qwzvar.h

1128

uint32_t ba_win_sz;

sys/dev/ic/qwzvar.h

1132

uint32_t cur_sn;

sys/dev/ic/qwzvar.h

1170

uint32_t *vaddr;

sys/dev/ic/qwzvar.h

1173

uint32_t ring_id;

sys/dev/ic/qwzvar.h

1193

uint32_t size;

sys/dev/ic/qwzvar.h

120

uint32_t wbm2sw_cc_enable;

sys/dev/ic/qwzvar.h

126

uint32_t desc_id;

sys/dev/ic/qwzvar.h

1260

uint32_t reo_cmd_cache_flush_count;

sys/dev/ic/qwzvar.h

1274

uint32_t num_spt_pages;

sys/dev/ic/qwzvar.h

130

uint32_t data_len;

sys/dev/ic/qwzvar.h

131

uint32_t pkt_offset;

sys/dev/ic/qwzvar.h

1329

uint32_t *shadow_reg_v3;

sys/dev/ic/qwzvar.h

133

uint32_t flags0; /* %HAL_TCL_DATA_CMD_INFO1_ */

sys/dev/ic/qwzvar.h

1330

uint32_t shadow_reg_v3_len;

sys/dev/ic/qwzvar.h

1334

uint32_t chip_id;

sys/dev/ic/qwzvar.h

1335

uint32_t chip_family;

sys/dev/ic/qwzvar.h

1336

uint32_t board_id;

sys/dev/ic/qwzvar.h

1337

uint32_t soc_id;

sys/dev/ic/qwzvar.h

1338

uint32_t fw_version;

sys/dev/ic/qwzvar.h

1339

uint32_t eeprom_caldata;

sys/dev/ic/qwzvar.h

134

uint32_t flags1; /* %HAL_TCL_DATA_CMD_INFO2_ */

sys/dev/ic/qwzvar.h

1357

uint32_t vendor;

sys/dev/ic/qwzvar.h

1358

uint32_t device;

sys/dev/ic/qwzvar.h

1359

uint32_t subsystem_vendor;

sys/dev/ic/qwzvar.h

1360

uint32_t subsystem_device;

sys/dev/ic/qwzvar.h

1369

uint32_t rx_decap_mode;

sys/dev/ic/qwzvar.h

1378

uint32_t max_msg_len[QWZ_MAX_RADIOS];

sys/dev/ic/qwzvar.h

1384

uint32_t num_mem_chunks;

sys/dev/ic/qwzvar.h

1385

uint32_t rx_decap_mode;

sys/dev/ic/qwzvar.h

1402

uint32_t n_dma_ring_caps;

sys/dev/ic/qwzvar.h

1409

uint32_t n_hw_mode_caps;

sys/dev/ic/qwzvar.h

1410

uint32_t tot_phy_id;

sys/dev/ic/qwzvar.h

1414

uint32_t n_mac_phy_caps;

sys/dev/ic/qwzvar.h

1417

uint32_t n_ext_hal_reg_caps;

sys/dev/ic/qwzvar.h

1434

uint32_t num_extra_mac_addr;

sys/dev/ic/qwzvar.h

1441

uint32_t num_buf_entry;

sys/dev/ic/qwzvar.h

1442

uint32_t num_meta;

sys/dev/ic/qwzvar.h

1537

uint32_t base_vector;

sys/dev/ic/qwzvar.h

1548

uint32_t phy_id;

sys/dev/ic/qwzvar.h

1549

uint32_t max_bw_supported;

sys/dev/ic/qwzvar.h

1550

uint32_t ht_cap_info;

sys/dev/ic/qwzvar.h

1551

uint32_t he_cap_info[2];

sys/dev/ic/qwzvar.h

1552

uint32_t he_mcs;

sys/dev/ic/qwzvar.h

1553

uint32_t he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];

sys/dev/ic/qwzvar.h

1559

uint32_t supported_bands;

sys/dev/ic/qwzvar.h

1560

uint32_t ampdu_density;

sys/dev/ic/qwzvar.h

1561

uint32_t vht_cap;

sys/dev/ic/qwzvar.h

1562

uint32_t vht_mcs;

sys/dev/ic/qwzvar.h

1563

uint32_t he_mcs;

sys/dev/ic/qwzvar.h

1564

uint32_t tx_chain_mask;

sys/dev/ic/qwzvar.h

1565

uint32_t rx_chain_mask;

sys/dev/ic/qwzvar.h

1566

uint32_t tx_chain_mask_shift;

sys/dev/ic/qwzvar.h

1567

uint32_t rx_chain_mask_shift;

sys/dev/ic/qwzvar.h

1575

uint32_t pdev_id;

sys/dev/ic/qwzvar.h

1581

uint32_t pdev_id;

sys/dev/ic/qwzvar.h

1583

uint32_t min_elem;

sys/dev/ic/qwzvar.h

1584

uint32_t min_buf_sz;

sys/dev/ic/qwzvar.h

1585

uint32_t min_buf_align;

sys/dev/ic/qwzvar.h

1595

uint32_t mcs:4,

sys/dev/ic/qwzvar.h

1601

uint32_t ul_ofdma_user_v0_word0;

sys/dev/ic/qwzvar.h

1602

uint32_t ul_ofdma_user_v0_word1;

sys/dev/ic/qwzvar.h

1603

uint32_t ast_index;

sys/dev/ic/qwzvar.h

1604

uint32_t tid;

sys/dev/ic/qwzvar.h

1612

uint32_t preamble_type;

sys/dev/ic/qwzvar.h

1617

uint32_t mpdu_cnt_fcs_ok;

sys/dev/ic/qwzvar.h

1618

uint32_t mpdu_cnt_fcs_err;

sys/dev/ic/qwzvar.h

1619

uint32_t mpdu_fcs_ok_bitmap[8];

sys/dev/ic/qwzvar.h

162

uint32_t flags; /* %HAL_TX_STATUS_FLAGS_ */

sys/dev/ic/qwzvar.h

1620

uint32_t mpdu_ok_byte_count;

sys/dev/ic/qwzvar.h

1621

uint32_t mpdu_err_byte_count;

sys/dev/ic/qwzvar.h

1625

uint32_t cookie;

sys/dev/ic/qwzvar.h

1628

uint32_t err_code;

sys/dev/ic/qwzvar.h

163

uint32_t ppdu_id;

sys/dev/ic/qwzvar.h

1644

uint32_t ppdu_id;

sys/dev/ic/qwzvar.h

1645

uint32_t ppdu_ts;

sys/dev/ic/qwzvar.h

1646

uint32_t num_mpdu_fcs_ok;

sys/dev/ic/qwzvar.h

1647

uint32_t num_mpdu_fcs_err;

sys/dev/ic/qwzvar.h

1648

uint32_t preamble_type;

sys/dev/ic/qwzvar.h

167

uint32_t rate_stats;

sys/dev/ic/qwzvar.h

1682

uint32_t ast_index;

sys/dev/ic/qwzvar.h

1702

uint32_t ppdu_len;

sys/dev/ic/qwzvar.h

1703

uint32_t prev_ppdu_id;

sys/dev/ic/qwzvar.h

1704

uint32_t device_id;

sys/dev/ic/qwzvar.h

1728

uint32_t status_ppdu_state;

sys/dev/ic/qwzvar.h

1729

uint32_t status_ppdu_start;

sys/dev/ic/qwzvar.h

173

uint32_t (*rxdma_ring_wmask_rx_msdu_end)(void);

sys/dev/ic/qwzvar.h

1730

uint32_t status_ppdu_end;

sys/dev/ic/qwzvar.h

1731

uint32_t status_ppdu_compl;

sys/dev/ic/qwzvar.h

1732

uint32_t status_ppdu_start_mis;

sys/dev/ic/qwzvar.h

1733

uint32_t status_ppdu_end_mis;

sys/dev/ic/qwzvar.h

1734

uint32_t status_ppdu_done;

sys/dev/ic/qwzvar.h

1735

uint32_t dest_ppdu_done;

sys/dev/ic/qwzvar.h

1736

uint32_t dest_mpdu_done;

sys/dev/ic/qwzvar.h

1737

uint32_t dest_mpdu_drop;

sys/dev/ic/qwzvar.h

1738

uint32_t dup_mon_linkdesc_cnt;

sys/dev/ic/qwzvar.h

1739

uint32_t dup_mon_buf_cnt;

sys/dev/ic/qwzvar.h

1740

uint32_t dest_mon_stuck;

sys/dev/ic/qwzvar.h

1741

uint32_t dest_mon_not_reaped;

sys/dev/ic/qwzvar.h

1748

uint32_t mon_ppdu_status;

sys/dev/ic/qwzvar.h

1749

uint32_t mon_last_buf_cookie;

sys/dev/ic/qwzvar.h

1769

uint32_t mac_id;

sys/dev/ic/qwzvar.h

1789

uint32_t vdev_id;

sys/dev/ic/qwzvar.h

1792

uint32_t beacon_interval;

sys/dev/ic/qwzvar.h

1793

uint32_t dtim_period;

sys/dev/ic/qwzvar.h

1807

uint32_t uapsd;

sys/dev/ic/qwzvar.h

1813

uint32_t ssid_len;

sys/dev/ic/qwzvar.h

1817

uint32_t noa_len;

sys/dev/ic/qwzvar.h

182

uint32_t bdf_addr;

sys/dev/ic/qwzvar.h

1827

uint32_t aid;

sys/dev/ic/qwzvar.h

1865

uint32_t irqs[ATH12K_EXT_IRQ_NUM_MAX];

sys/dev/ic/qwzvar.h

1866

uint32_t num_irq;

sys/dev/ic/qwzvar.h

1867

uint32_t grp_id;

sys/dev/ic/qwzvar.h

1899

uint32_t sc_flags;

sys/dev/ic/qwzvar.h

1932

uint32_t vdev_id_11d_scan;

sys/dev/ic/qwzvar.h

1957

uint32_t qfullmsk;

sys/dev/ic/qwzvar.h

196

uint32_t qmi_service_ins_id;

sys/dev/ic/qwzvar.h

1969

uint32_t wmi_conf_rx_decap_mode;

sys/dev/ic/qwzvar.h

198

uint32_t ce_count;

sys/dev/ic/qwzvar.h

1985

uint32_t cc_freq_hz;

sys/dev/ic/qwzvar.h

1986

uint32_t cfg_tx_chainmask;

sys/dev/ic/qwzvar.h

1987

uint32_t cfg_rx_chainmask;

sys/dev/ic/qwzvar.h

1992

uint32_t allocated_vdev_map;

sys/dev/ic/qwzvar.h

1993

uint32_t free_vdev_map;

sys/dev/ic/qwzvar.h

200

uint32_t target_ce_count;

sys/dev/ic/qwzvar.h

2001

uint32_t num_db_cap;

sys/dev/ic/qwzvar.h

2005

uint32_t wlan_init_status;

sys/dev/ic/qwzvar.h

2007

uint32_t pktlog_defs_checksum;

sys/dev/ic/qwzvar.h

2013

uint32_t pdev_id;

sys/dev/ic/qwzvar.h

2016

uint32_t pdevs_active;

sys/dev/ic/qwzvar.h

202

uint32_t svc_to_ce_map_len;

sys/dev/ic/qwzvar.h

2021

uint32_t service;

sys/dev/ic/qwzvar.h

2022

uint32_t instance;

sys/dev/ic/qwzvar.h

2023

uint32_t node;

sys/dev/ic/qwzvar.h

2024

uint32_t port;

sys/dev/ic/qwzvar.h

2049

uint32_t msi_addr_lo;

sys/dev/ic/qwzvar.h

2050

uint32_t msi_addr_hi;

sys/dev/ic/qwzvar.h

2051

uint32_t msi_data_start;

sys/dev/ic/qwzvar.h

2053

uint32_t msi_ce_irqmask;

sys/dev/ic/qwzvar.h

2152

void qwz_ce_get_shadow_config(struct qwz_softc *, uint32_t **, uint32_t *);

sys/dev/ic/qwzvar.h

2167

static inline enum ieee80211_edca_ac qwz_tid_to_ac(uint32_t tid)

sys/dev/ic/qwzvar.h

231

uint32_t hal_desc_sz;

sys/dev/ic/qwzvar.h

233

uint32_t num_tcl_banks;

sys/dev/ic/qwzvar.h

234

uint32_t max_tx_ring;

sys/dev/ic/qwzvar.h

253

uint32_t start;

sys/dev/ic/qwzvar.h

254

uint32_t end;

sys/dev/ic/qwzvar.h

259

uint32_t tx_ring_size;

sys/dev/ic/qwzvar.h

278

uint32_t (*rx_desc_get_encrypt_type)(struct hal_rx_desc *desc);

sys/dev/ic/qwzvar.h

292

uint32_t (*rx_desc_get_msdu_freq)(struct hal_rx_desc *desc);

sys/dev/ic/qwzvar.h

299

uint32_t (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc);

sys/dev/ic/qwzvar.h

300

uint32_t (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc);

sys/dev/ic/qwzvar.h

304

uint32_t (*rx_desc_get_mpdu_start_offset)(void);

sys/dev/ic/qwzvar.h

305

uint32_t (*rx_desc_get_msdu_end_offset)(void);

sys/dev/ic/qwzvar.h

324

uint32_t (*dp_rx_h_mpdu_err)(struct hal_rx_desc *desc);

sys/dev/ic/qwzvar.h

325

uint32_t (*rx_desc_get_desc_size)(void);

sys/dev/ic/qwzvar.h

336

uint32_t hal_tcl1_ring_id;

sys/dev/ic/qwzvar.h

337

uint32_t hal_tcl1_ring_misc;

sys/dev/ic/qwzvar.h

338

uint32_t hal_tcl1_ring_tp_addr_lsb;

sys/dev/ic/qwzvar.h

339

uint32_t hal_tcl1_ring_tp_addr_msb;

sys/dev/ic/qwzvar.h

340

uint32_t hal_tcl1_ring_consumer_int_setup_ix0;

sys/dev/ic/qwzvar.h

341

uint32_t hal_tcl1_ring_consumer_int_setup_ix1;

sys/dev/ic/qwzvar.h

342

uint32_t hal_tcl1_ring_msi1_base_lsb;

sys/dev/ic/qwzvar.h

343

uint32_t hal_tcl1_ring_msi1_base_msb;

sys/dev/ic/qwzvar.h

344

uint32_t hal_tcl1_ring_msi1_data;

sys/dev/ic/qwzvar.h

345

uint32_t hal_tcl_ring_base_lsb;

sys/dev/ic/qwzvar.h

347

uint32_t hal_tcl_status_ring_base_lsb;

sys/dev/ic/qwzvar.h

349

uint32_t hal_wbm_idle_ring_base_lsb;

sys/dev/ic/qwzvar.h

350

uint32_t hal_wbm_idle_ring_misc_addr;

sys/dev/ic/qwzvar.h

351

uint32_t hal_wbm_r0_idle_list_cntl_addr;

sys/dev/ic/qwzvar.h

352

uint32_t hal_wbm_r0_idle_list_size_addr;

sys/dev/ic/qwzvar.h

353

uint32_t hal_wbm_scattered_ring_base_lsb;

sys/dev/ic/qwzvar.h

354

uint32_t hal_wbm_scattered_ring_base_msb;

sys/dev/ic/qwzvar.h

355

uint32_t hal_wbm_scattered_desc_head_info_ix0;

sys/dev/ic/qwzvar.h

356

uint32_t hal_wbm_scattered_desc_head_info_ix1;

sys/dev/ic/qwzvar.h

357

uint32_t hal_wbm_scattered_desc_tail_info_ix0;

sys/dev/ic/qwzvar.h

358

uint32_t hal_wbm_scattered_desc_tail_info_ix1;

sys/dev/ic/qwzvar.h

359

uint32_t hal_wbm_scattered_desc_ptr_hp_addr;

sys/dev/ic/qwzvar.h

361

uint32_t hal_wbm_sw_release_ring_base_lsb;

sys/dev/ic/qwzvar.h

362

uint32_t hal_wbm_sw1_release_ring_base_lsb;

sys/dev/ic/qwzvar.h

363

uint32_t hal_wbm0_release_ring_base_lsb;

sys/dev/ic/qwzvar.h

364

uint32_t hal_wbm1_release_ring_base_lsb;

sys/dev/ic/qwzvar.h

366

uint32_t pcie_qserdes_sysclk_en_sel;

sys/dev/ic/qwzvar.h

367

uint32_t pcie_pcs_osc_dtct_config_base;

sys/dev/ic/qwzvar.h

369

uint32_t hal_ppe_rel_ring_base;

sys/dev/ic/qwzvar.h

371

uint32_t hal_reo2_ring_base;

sys/dev/ic/qwzvar.h

372

uint32_t hal_reo1_misc_ctrl_addr;

sys/dev/ic/qwzvar.h

373

uint32_t hal_reo1_sw_cookie_cfg0;

sys/dev/ic/qwzvar.h

374

uint32_t hal_reo1_sw_cookie_cfg1;

sys/dev/ic/qwzvar.h

375

uint32_t hal_reo1_qdesc_lut_base0;

sys/dev/ic/qwzvar.h

376

uint32_t hal_reo1_qdesc_lut_base1;

sys/dev/ic/qwzvar.h

377

uint32_t hal_reo1_ring_base_lsb;

sys/dev/ic/qwzvar.h

378

uint32_t hal_reo1_ring_base_msb;

sys/dev/ic/qwzvar.h

379

uint32_t hal_reo1_ring_id;

sys/dev/ic/qwzvar.h

380

uint32_t hal_reo1_ring_misc;

sys/dev/ic/qwzvar.h

381

uint32_t hal_reo1_ring_hp_addr_lsb;

sys/dev/ic/qwzvar.h

382

uint32_t hal_reo1_ring_hp_addr_msb;

sys/dev/ic/qwzvar.h

383

uint32_t hal_reo1_ring_producer_int_setup;

sys/dev/ic/qwzvar.h

384

uint32_t hal_reo1_ring_msi1_base_lsb;

sys/dev/ic/qwzvar.h

385

uint32_t hal_reo1_ring_msi1_base_msb;

sys/dev/ic/qwzvar.h

386

uint32_t hal_reo1_ring_msi1_data;

sys/dev/ic/qwzvar.h

387

uint32_t hal_reo1_aging_thres_ix0;

sys/dev/ic/qwzvar.h

388

uint32_t hal_reo1_aging_thres_ix1;

sys/dev/ic/qwzvar.h

389

uint32_t hal_reo1_aging_thres_ix2;

sys/dev/ic/qwzvar.h

390

uint32_t hal_reo1_aging_thres_ix3;

sys/dev/ic/qwzvar.h

392

uint32_t hal_reo2_sw0_ring_base;

sys/dev/ic/qwzvar.h

394

uint32_t hal_sw2reo_ring_base;

sys/dev/ic/qwzvar.h

395

uint32_t hal_sw2reo1_ring_base;

sys/dev/ic/qwzvar.h

397

uint32_t hal_reo_cmd_ring_base;

sys/dev/ic/qwzvar.h

399

uint32_t hal_reo_status_ring_base;

sys/dev/ic/qwzvar.h

454

uint32_t (*read32)(struct qwz_softc *, uint32_t);

sys/dev/ic/qwzvar.h

455

void (*write32)(struct qwz_softc *, uint32_t, uint32_t);

sys/dev/ic/qwzvar.h

466

int *, uint32_t *, uint32_t *);

sys/dev/ic/qwzvar.h

48

extern uint32_t qwz_debug;

sys/dev/ic/qwzvar.h

486

uint32_t *ring_base_vaddr;

sys/dev/ic/qwzvar.h

488

uint32_t intr_batch_cntr_thres_entries;

sys/dev/ic/qwzvar.h

489

uint32_t intr_timer_thres_us;

sys/dev/ic/qwzvar.h

490

uint32_t flags;

sys/dev/ic/qwzvar.h

491

uint32_t max_buffer_len;

sys/dev/ic/qwzvar.h

492

uint32_t low_threshold;

sys/dev/ic/qwzvar.h

494

uint32_t msi_data;

sys/dev/ic/qwzvar.h

531

uint32_t *ring_base_vaddr;

sys/dev/ic/qwzvar.h

534

uint32_t num_entries;

sys/dev/ic/qwzvar.h

537

uint32_t ring_size;

sys/dev/ic/qwzvar.h

540

uint32_t ring_size_mask;

sys/dev/ic/qwzvar.h

543

uint32_t entry_size;

sys/dev/ic/qwzvar.h

546

uint32_t intr_timer_thres_us;

sys/dev/ic/qwzvar.h

549

uint32_t intr_batch_cntr_thres_entries;

sys/dev/ic/qwzvar.h

555

uint32_t msi_data;

sys/dev/ic/qwzvar.h

558

uint32_t flags;

sys/dev/ic/qwzvar.h

567

uint32_t hwreg_base[HAL_SRNG_NUM_REG_GRP];

sys/dev/ic/qwzvar.h

577

uint32_t tp;

sys/dev/ic/qwzvar.h

580

volatile uint32_t *hp_addr;

sys/dev/ic/qwzvar.h

583

uint32_t cached_hp;

sys/dev/ic/qwzvar.h

589

uint32_t *tp_addr;

sys/dev/ic/qwzvar.h

592

uint32_t loop_cnt;

sys/dev/ic/qwzvar.h

598

uint32_t last_hp;

sys/dev/ic/qwzvar.h

603

uint32_t hp;

sys/dev/ic/qwzvar.h

606

uint32_t reap_hp;

sys/dev/ic/qwzvar.h

609

uint32_t *tp_addr;

sys/dev/ic/qwzvar.h

612

uint32_t cached_tp;

sys/dev/ic/qwzvar.h

618

uint32_t *hp_addr;

sys/dev/ic/qwzvar.h

621

uint32_t low_threshold;

sys/dev/ic/qwzvar.h

624

uint32_t last_tp;

sys/dev/ic/qwzvar.h

669

uint32_t reg_start[HAL_SRNG_NUM_REG_GRP];

sys/dev/ic/qwzvar.h

673

uint32_t max_size;

sys/dev/ic/qwzvar.h

682

uint32_t timestamp;

sys/dev/ic/qwzvar.h

688

uint32_t pn[4];

sys/dev/ic/qwzvar.h

689

uint32_t last_rx_queue_ts;

sys/dev/ic/qwzvar.h

690

uint32_t last_rx_dequeue_ts;

sys/dev/ic/qwzvar.h

691

uint32_t rx_bitmap[8]; /* Bitmap from 0-255 */

sys/dev/ic/qwzvar.h

692

uint32_t curr_mpdu_cnt;

sys/dev/ic/qwzvar.h

693

uint32_t curr_msdu_cnt;

sys/dev/ic/qwzvar.h

696

uint32_t frames_in_order_cnt;

sys/dev/ic/qwzvar.h

697

uint32_t num_mpdu_processed_cnt;

sys/dev/ic/qwzvar.h

698

uint32_t num_msdu_processed_cnt;

sys/dev/ic/qwzvar.h

699

uint32_t total_num_processed_byte_cnt;

sys/dev/ic/qwzvar.h

700

uint32_t late_rx_mpdu_cnt;

sys/dev/ic/qwzvar.h

701

uint32_t reorder_hole_cnt;

sys/dev/ic/qwzvar.h

753

uint32_t link_desc_counter0;

sys/dev/ic/qwzvar.h

754

uint32_t link_desc_counter1;

sys/dev/ic/qwzvar.h

755

uint32_t link_desc_counter2;

sys/dev/ic/qwzvar.h

756

uint32_t link_desc_counter_sum;

sys/dev/ic/qwzvar.h

786

uint32_t *vaddr;

sys/dev/ic/qwzvar.h

793

uint32_t *vaddr;

sys/dev/ic/qwzvar.h

803

uint32_t shadow_reg_addr[HAL_SHADOW_NUM_REGS];

sys/dev/ic/qwzvar.h

809

uint32_t hal_desc_sz;

sys/dev/ic/qwzvar.h

826

uint32_t ie1_reg_addr;

sys/dev/ic/qwzvar.h

827

uint32_t ie2_reg_addr;

sys/dev/ic/qwzvar.h

828

uint32_t ie3_reg_addr;

sys/dev/ic/qwzvar.h

832

uint32_t base;

sys/dev/ic/qwzvar.h

833

uint32_t size;

sys/dev/ic/qwzvar.h

891

uint32_t cipher;

sys/dev/ic/qwzvar.h

924

uint32_t hal_ring_id;

sys/dev/ic/qwzvar.h

952

uint32_t msdu_id;

sys/dev/ic/r92creg.h

1131

uint32_t svnidx;

sys/dev/ic/r92creg.h

1132

uint32_t reserved3;

sys/dev/ic/r92creg.h

1134

uint32_t reserved4;

sys/dev/ic/r92creg.h

1135

uint32_t reserved5;

sys/dev/ic/r92creg.h

1167

uint32_t mask;

sys/dev/ic/r92creg.h

1465

uint32_t phydw0;

sys/dev/ic/r92creg.h

1466

uint32_t phydw1;

sys/dev/ic/r92creg.h

1467

uint32_t phydw2;

sys/dev/ic/r92creg.h

1468

uint32_t phydw3;

sys/dev/ic/r92creg.h

1469

uint32_t phydw4;

sys/dev/ic/r92creg.h

1470

uint32_t phydw5;

sys/dev/ic/r92creg.h

1471

uint32_t phydw6;

sys/dev/ic/r92creg.h

1472

uint32_t phydw7;

sys/dev/ic/r92creg.h

1535

uint32_t rxdw0;

sys/dev/ic/r92creg.h

1536

uint32_t rxdw1;

sys/dev/ic/r92creg.h

1537

uint32_t rxdw2;

sys/dev/ic/r92creg.h

1538

uint32_t rxdw3;

sys/dev/ic/r92creg.h

1539

uint32_t rxdw4;

sys/dev/ic/r92creg.h

1540

uint32_t rxdw5;

sys/dev/ic/r92creg.h

1541

uint32_t rxbufaddr;

sys/dev/ic/r92creg.h

1542

uint32_t rxbufaddr64;

sys/dev/ic/r92creg.h

1546

uint32_t rxdw0;

sys/dev/ic/r92creg.h

1547

uint32_t rxdw1;

sys/dev/ic/r92creg.h

1548

uint32_t rxdw2;

sys/dev/ic/r92creg.h

1549

uint32_t rxdw3;

sys/dev/ic/r92creg.h

1550

uint32_t rxdw4;

sys/dev/ic/r92creg.h

1551

uint32_t rxdw5;

sys/dev/ic/r92creg.h

1590

uint32_t txdw0;

sys/dev/ic/r92creg.h

1591

uint32_t txdw1;

sys/dev/ic/r92creg.h

1592

uint32_t txdw2;

sys/dev/ic/r92creg.h

1595

uint32_t txdw4;

sys/dev/ic/r92creg.h

1596

uint32_t txdw5;

sys/dev/ic/r92creg.h

1597

uint32_t txdw6;

sys/dev/ic/r92creg.h

1600

uint32_t txbufaddr;

sys/dev/ic/r92creg.h

1601

uint32_t txbufaddr64;

sys/dev/ic/r92creg.h

1602

uint32_t nextdescaddr;

sys/dev/ic/r92creg.h

1603

uint32_t nextdescaddr64;

sys/dev/ic/r92creg.h

1604

uint32_t reserved[4];

sys/dev/ic/r92creg.h

1608

uint32_t txdw0;

sys/dev/ic/r92creg.h

1609

uint32_t txdw1;

sys/dev/ic/r92creg.h

1610

uint32_t txdw2;

sys/dev/ic/r92creg.h

1613

uint32_t txdw4;

sys/dev/ic/r92creg.h

1614

uint32_t txdw5;

sys/dev/ic/r92creg.h

1615

uint32_t txdw6;

sys/dev/ic/r92creg.h

1621

uint32_t txdw0;

sys/dev/ic/r92creg.h

1622

uint32_t txdw1;

sys/dev/ic/r92creg.h

1623

uint32_t txdw2;

sys/dev/ic/r92creg.h

1624

uint32_t txdw3;

sys/dev/ic/r92creg.h

1625

uint32_t txdw4;

sys/dev/ic/r92creg.h

1626

uint32_t txdw5;

sys/dev/ic/r92creg.h

1627

uint32_t txdw6;

sys/dev/ic/r92creg.h

1630

uint32_t txdw7;

sys/dev/ic/r92creg.h

1945

const uint32_t *vals;

sys/dev/ic/r92creg.h

1947

const uint32_t *agcvals;

sys/dev/ic/r92creg.h

1953

static const uint32_t rtl8192ce_bb_vals_1t[] = {

sys/dev/ic/r92creg.h

2018

static const uint32_t rtl8192ce_bb_vals[] = {

sys/dev/ic/r92creg.h

2059

static const uint32_t rtl8192ce_bb_vals_2t[] = {

sys/dev/ic/r92creg.h

2099

static const uint32_t rtl8192ce_agc_vals[] = {

sys/dev/ic/r92creg.h

2161

static const uint32_t rtl8192cu_bb_vals[] = {

sys/dev/ic/r92creg.h

2213

static const uint32_t rtl8188ce_bb_vals[] = {

sys/dev/ic/r92creg.h

2254

static const uint32_t rtl8188ce_agc_vals[] = {

sys/dev/ic/r92creg.h

2297

static const uint32_t rtl8188cu_bb_vals[] = {

sys/dev/ic/r92creg.h

2374

static const uint32_t rtl8188eu_bb_vals[] = {

sys/dev/ic/r92creg.h

2416

static const uint32_t rtl8188eu_agc_vals[] = {

sys/dev/ic/r92creg.h

2482

static const uint32_t rtl8188ftv_bb_vals[] = {

sys/dev/ic/r92creg.h

2527

static const uint32_t rtl8188ftv_agc_vals[] = {

sys/dev/ic/r92creg.h

2578

static const uint32_t rtl8188ru_bb_vals[] = {

sys/dev/ic/r92creg.h

2619

static const uint32_t rtl8188ru_agc_vals[] = {

sys/dev/ic/r92creg.h

2690

static const uint32_t rtl8723a_bb_vals[] = {

sys/dev/ic/r92creg.h

2745

const uint32_t *vals;

sys/dev/ic/r92creg.h

2767

static const uint32_t rtl8192ce_rf1_vals[] = {

sys/dev/ic/r92creg.h

2798

static const uint32_t rtl8192ce_rf2_vals[] = {

sys/dev/ic/r92creg.h

2823

static const uint32_t rtl8188ce_rf_vals[] = {

sys/dev/ic/r92creg.h

2859

static const uint32_t rtl8188cu_rf_vals[] = {

sys/dev/ic/r92creg.h

2907

static const uint32_t rtl8192e_rf_vals[] = {

sys/dev/ic/r92creg.h

2936

static const uint32_t rtl8192e_rf2_vals[] = {

sys/dev/ic/r92creg.h

2979

static const uint32_t rtl8188eu_rf_vals[] = {

sys/dev/ic/r92creg.h

3021

static const uint32_t rtl8188ftv_rf_vals[] = {

sys/dev/ic/r92creg.h

3077

static const uint32_t rtl8192e_bb_vals[] = {

sys/dev/ic/r92creg.h

3122

static const uint32_t rtl8192eu_agc_vals[] = {

sys/dev/ic/r92creg.h

3163

static const uint32_t rtl8188ru_rf_vals[] = {

sys/dev/ic/r92creg.h

3215

static const uint32_t rtl8723a_rf_vals[] = {

sys/dev/ic/re.c

1455

uint32_t txstat;

sys/dev/ic/re.c

1882

uint32_t rxcfg;

sys/dev/ic/re.c

2486

uint32_t reg;

sys/dev/ic/re.c

275

d->rl_bufaddr_lo = htole32((uint32_t)addr);

sys/dev/ic/rt2560.c

103

uint16_t rt2560_txtime(int, int, uint32_t);

sys/dev/ic/rt2560.c

106

struct rt2560_tx_desc *, uint32_t, int, int, int,

sys/dev/ic/rt2560.c

1175

uint32_t tsf_lo, tsf_hi;

sys/dev/ic/rt2560.c

121

void rt2560_rf_write(struct rt2560_softc *, uint8_t, uint32_t);

sys/dev/ic/rt2560.c

1326

uint32_t r;

sys/dev/ic/rt2560.c

144

uint32_t reg;

sys/dev/ic/rt2560.c

145

uint32_t val;

sys/dev/ic/rt2560.c

1456

rt2560_txtime(int len, int rate, uint32_t flags)

sys/dev/ic/rt2560.c

1502

uint32_t flags, int len, int rate, int encrypt, bus_addr_t physaddr)

sys/dev/ic/rt2560.c

157

static const uint32_t rt2560_rf2522_r2[] = RT2560_RF2522_R2;

sys/dev/ic/rt2560.c

158

static const uint32_t rt2560_rf2523_r2[] = RT2560_RF2523_R2;

sys/dev/ic/rt2560.c

159

static const uint32_t rt2560_rf2524_r2[] = RT2560_RF2524_R2;

sys/dev/ic/rt2560.c

160

static const uint32_t rt2560_rf2525_r2[] = RT2560_RF2525_R2;

sys/dev/ic/rt2560.c

161

static const uint32_t rt2560_rf2525_hi_r2[] = RT2560_RF2525_HI_R2;

sys/dev/ic/rt2560.c

1612

uint32_t flags = 0;

sys/dev/ic/rt2560.c

162

static const uint32_t rt2560_rf2525e_r2[] = RT2560_RF2525E_R2;

sys/dev/ic/rt2560.c

163

static const uint32_t rt2560_rf2526_r2[] = RT2560_RF2526_R2;

sys/dev/ic/rt2560.c

164

static const uint32_t rt2560_rf2526_hi_r2[] = RT2560_RF2526_HI_R2;

sys/dev/ic/rt2560.c

1695

uint32_t flags = 0;

sys/dev/ic/rt2560.c

2053

uint32_t tmp;

sys/dev/ic/rt2560.c

2075

uint32_t val;

sys/dev/ic/rt2560.c

2103

rt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val)

sys/dev/ic/rt2560.c

2105

uint32_t tmp;

sys/dev/ic/rt2560.c

2226

uint32_t tmp;

sys/dev/ic/rt2560.c

2248

uint32_t tmp;

sys/dev/ic/rt2560.c

2329

uint32_t tmp;

sys/dev/ic/rt2560.c

2371

uint32_t tmp;

sys/dev/ic/rt2560.c

2381

uint32_t tmp;

sys/dev/ic/rt2560.c

2395

uint32_t tmp;

sys/dev/ic/rt2560.c

2409

uint32_t tmp;

sys/dev/ic/rt2560.c

2426

uint32_t tmp;

sys/dev/ic/rt2560.c

2443

uint32_t tmp;

sys/dev/ic/rt2560.c

2569

uint32_t tmp;

sys/dev/ic/rt2560.c

818

uint32_t tmp;

sys/dev/ic/rt2560reg.h

176

uint32_t flags;

sys/dev/ic/rt2560reg.h

208

uint32_t physaddr;

sys/dev/ic/rt2560reg.h

222

uint32_t iv;

sys/dev/ic/rt2560reg.h

223

uint32_t eiv;

sys/dev/ic/rt2560reg.h

225

uint32_t reserved2[2];

sys/dev/ic/rt2560reg.h

230

uint32_t flags;

sys/dev/ic/rt2560reg.h

245

uint32_t physaddr;

sys/dev/ic/rt2560reg.h

249

uint32_t iv;

sys/dev/ic/rt2560reg.h

250

uint32_t eiv;

sys/dev/ic/rt2560reg.h

252

uint32_t reserved[2];

sys/dev/ic/rt2560var.h

124

uint32_t asic_rev;

sys/dev/ic/rt2560var.h

133

uint32_t rf_regs[4];

sys/dev/ic/rt2661.c

1054

const uint32_t val = RAL_READ(sc, RT2661_STA_CSR4);

sys/dev/ic/rt2661.c

111

uint16_t rt2661_txtime(int, int, uint32_t);

sys/dev/ic/rt2661.c

114

struct rt2661_tx_desc *, uint32_t, uint16_t, int, int,

sys/dev/ic/rt2661.c

125

void rt2661_rf_write(struct rt2661_softc *, uint8_t, uint32_t);

sys/dev/ic/rt2661.c

1251

uint32_t tsf_lo, tsf_hi;

sys/dev/ic/rt2661.c

1355

uint32_t r1, r2;

sys/dev/ic/rt2661.c

1494

rt2661_txtime(int len, int rate, uint32_t flags)

sys/dev/ic/rt2661.c

1540

uint32_t flags, uint16_t xflags, int len, int rate,

sys/dev/ic/rt2661.c

1608

uint32_t flags = 0;

sys/dev/ic/rt2661.c

166

uint32_t reg;

sys/dev/ic/rt2661.c

167

uint32_t val;

sys/dev/ic/rt2661.c

1695

uint32_t flags = 0;

sys/dev/ic/rt2661.c

181

uint32_t r1, r2, r3, r4;

sys/dev/ic/rt2661.c

193

uint32_t val;

sys/dev/ic/rt2661.c

2047

uint32_t tmp;

sys/dev/ic/rt2661.c

2069

uint32_t val;

sys/dev/ic/rt2661.c

2097

rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)

sys/dev/ic/rt2661.c

2099

uint32_t tmp;

sys/dev/ic/rt2661.c

2140

uint32_t tmp;

sys/dev/ic/rt2661.c

2166

uint32_t tmp;

sys/dev/ic/rt2661.c

2181

uint32_t tmp;

sys/dev/ic/rt2661.c

2218

uint32_t tmp;

sys/dev/ic/rt2661.c

2338

uint32_t tmp;

sys/dev/ic/rt2661.c

2350

uint32_t tmp;

sys/dev/ic/rt2661.c

2363

uint32_t tmp;

sys/dev/ic/rt2661.c

2400

uint32_t tmp;

sys/dev/ic/rt2661.c

2547

uint32_t tmp, sta[3];

sys/dev/ic/rt2661.c

2694

uint32_t tmp;

sys/dev/ic/rt2661.c

2844

uint32_t tmp;

sys/dev/ic/rt2661.c

2958

uint32_t tmp;

sys/dev/ic/rt2661.c

923

uint32_t tmp;

sys/dev/ic/rt2661.c

991

uint32_t tmp;

sys/dev/ic/rt2661reg.h

219

uint32_t flags;

sys/dev/ic/rt2661reg.h

246

uint32_t iv;

sys/dev/ic/rt2661reg.h

247

uint32_t eiv;

sys/dev/ic/rt2661reg.h

258

uint32_t addr[RT2661_MAX_SCATTER];

sys/dev/ic/rt2661reg.h

266

uint32_t flags;

sys/dev/ic/rt2661reg.h

278

uint32_t iv;

sys/dev/ic/rt2661reg.h

279

uint32_t eiv;

sys/dev/ic/rt2661reg.h

280

uint32_t reserved2;

sys/dev/ic/rt2661reg.h

281

uint32_t physaddr;

sys/dev/ic/rt2661reg.h

282

uint32_t reserved3[10];

sys/dev/ic/rt2661reg.h

328

static __inline uint32_t

sys/dev/ic/rt2661reg.h

337

uint32_t *datap, bus_size_t count)

sys/dev/ic/rt2661reg.h

345

RAL_WRITE(struct rt2661_softc *sc, bus_size_t reg, uint32_t val)

sys/dev/ic/rt2661var.h

143

uint32_t rf_regs[4];

sys/dev/ic/rt2661var.h

164

uint32_t erp_csr;

sys/dev/ic/rt2860.c

1010

uint32_t tmp;

sys/dev/ic/rt2860.c

1049

uint32_t tmp;

sys/dev/ic/rt2860.c

1091

uint32_t tmp;

sys/dev/ic/rt2860.c

1152

uint32_t tmp;

sys/dev/ic/rt2860.c

116

void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t);

sys/dev/ic/rt2860.c

1171

uint32_t stat;

sys/dev/ic/rt2860.c

1211

uint32_t hw;

sys/dev/ic/rt2860.c

1270

uint32_t hw;

sys/dev/ic/rt2860.c

1481

uint32_t r;

sys/dev/ic/rt2860.c

167

uint32_t reg;

sys/dev/ic/rt2860.c

168

uint32_t val;

sys/dev/ic/rt2860.c

186

uint32_t r1, r2, r3, r4;

sys/dev/ic/rt2860.c

1908

uint32_t val;

sys/dev/ic/rt2860.c

1945

rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val)

sys/dev/ic/rt2860.c

1947

uint32_t tmp;

sys/dev/ic/rt2860.c

1969

uint32_t tmp;

sys/dev/ic/rt2860.c

2002

uint32_t tmp;

sys/dev/ic/rt2860.c

2026

uint32_t tmp;

sys/dev/ic/rt2860.c

2099

uint32_t tmp;

sys/dev/ic/rt2860.c

2125

uint32_t tmp;

sys/dev/ic/rt2860.c

218

uint32_t tmp, reg;

sys/dev/ic/rt2860.c

2223

uint32_t r2, r3, r4;

sys/dev/ic/rt2860.c

2458

uint32_t tmp;

sys/dev/ic/rt2860.c

2653

uint32_t tmp;

sys/dev/ic/rt2860.c

2719

uint32_t tmp;

sys/dev/ic/rt2860.c

2863

uint32_t tmp;

sys/dev/ic/rt2860.c

2904

uint32_t tmp;

sys/dev/ic/rt2860.c

2917

uint32_t tmp;

sys/dev/ic/rt2860.c

2982

uint32_t attr;

sys/dev/ic/rt2860.c

3036

uint32_t val = arc4random();

sys/dev/ic/rt2860.c

3084

uint32_t attr;

sys/dev/ic/rt2860.c

3132

static __inline uint32_t

sys/dev/ic/rt2860.c

3133

b4inc(uint32_t b32, int8_t delta)

sys/dev/ic/rt2860.c

3177

uint32_t tmp;

sys/dev/ic/rt2860.c

3358

uint32_t reg;

sys/dev/ic/rt2860.c

3363

reg |= (uint32_t)val << 16;

sys/dev/ic/rt2860.c

3572

uint32_t tmp;

sys/dev/ic/rt2860.c

3610

uint32_t tmp;

sys/dev/ic/rt2860.c

3657

uint32_t tmp;

sys/dev/ic/rt2860.c

3959

uint32_t tmp;

sys/dev/ic/rt2860.c

4086

uint32_t tmp;

sys/dev/ic/rt2860.c

4189

uint32_t tmp;

sys/dev/ic/rt2860.c

820

uint32_t tmp = RAL_READ(sc, RT2860_DEBUG);

sys/dev/ic/rt2860.c

907

uint32_t tmp;

sys/dev/ic/rt2860.c

922

uint32_t tmp;

sys/dev/ic/rt2860.c

935

uint32_t tmp;

sys/dev/ic/rt2860reg.h

832

uint32_t sdp0; /* Segment Data Pointer 0 */

sys/dev/ic/rt2860reg.h

841

uint32_t sdp1; /* Segment Data Pointer 1 */

sys/dev/ic/rt2860reg.h

894

uint32_t iv;

sys/dev/ic/rt2860reg.h

895

uint32_t eiv;

sys/dev/ic/rt2860reg.h

900

uint32_t sdp0;

sys/dev/ic/rt2860reg.h

906

uint32_t sdp1; /* unused */

sys/dev/ic/rt2860reg.h

907

uint32_t flags;

sys/dev/ic/rt2860reg.h

930

uint32_t flags;

sys/dev/ic/rt2860var.h

129

uint32_t sc_ic_flags;

sys/dev/ic/rt2860var.h

180

uint32_t txpow20mhz[5];

sys/dev/ic/rt2860var.h

181

uint32_t txpow40mhz_2ghz[5];

sys/dev/ic/rt2860var.h

182

uint32_t txpow40mhz_5ghz[5];

sys/dev/ic/rtl81x9reg.h

698

uint32_t re_rx_er;

sys/dev/ic/rtl81x9reg.h

701

uint32_t re_tx_1col;

sys/dev/ic/rtl81x9reg.h

702

uint32_t re_tx_mcol;

sys/dev/ic/rtl81x9reg.h

705

uint32_t re_rx_ok_mul;

sys/dev/ic/rtw.c

1005

uint32_t ctl, octl, obuf;

sys/dev/ic/rtw.c

1346

uint32_t hstat;

sys/dev/ic/rtw.c

145

int rtw_compute_duration1(int, int, uint32_t, int, struct rtw_duration *);

sys/dev/ic/rtw.c

146

int rtw_compute_duration(struct ieee80211_frame *, int, uint32_t, int,

sys/dev/ic/rtw.c

1462

uint32_t tsfth, tsftl;

sys/dev/ic/rtw.c

1658

uint32_t rdsar;

sys/dev/ic/rtw.c

242

u_int32_t rtw_maxim_swizzle(u_int, uint32_t);

sys/dev/ic/rtw.c

2898

rtw_compute_duration1(int len, int use_ack, uint32_t flags, int rate,

sys/dev/ic/rtw.c

2984

rtw_compute_duration(struct ieee80211_frame *wh, int len, uint32_t flags,

sys/dev/ic/rtw.c

3063

uint32_t proto_ctl0, ctl0, ctl1;

sys/dev/ic/rtw.c

445

uint32_t tcr;

sys/dev/ic/rtw.c

4480

uint32_t enable;

sys/dev/ic/rtwn.c

100

uint32_t ofdm0_trxpathena;

sys/dev/ic/rtwn.c

101

uint32_t ofdm0_trmuxpar;

sys/dev/ic/rtwn.c

102

uint32_t fpga0_rfifacesw0;

sys/dev/ic/rtwn.c

103

uint32_t fpga0_rfifacesw1;

sys/dev/ic/rtwn.c

104

uint32_t fpga0_rfifaceoe0;

sys/dev/ic/rtwn.c

105

uint32_t fpga0_rfifaceoe1;

sys/dev/ic/rtwn.c

106

uint32_t config_ant_a;

sys/dev/ic/rtwn.c

1064

uint32_t reg;

sys/dev/ic/rtwn.c

107

uint32_t config_ant_b;

sys/dev/ic/rtwn.c

108

uint32_t cck0_afesetting;

sys/dev/ic/rtwn.c

113

void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t);

sys/dev/ic/rtwn.c

116

uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t);

sys/dev/ic/rtwn.c

118

void rtwn_rf_write(struct rtwn_softc *, int, uint16_t, uint32_t);

sys/dev/ic/rtwn.c

119

uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t);

sys/dev/ic/rtwn.c

120

void rtwn_cam_write(struct rtwn_softc *, uint32_t, uint32_t);

sys/dev/ic/rtwn.c

1246

uint32_t reg;

sys/dev/ic/rtwn.c

1259

uint32_t reg;

sys/dev/ic/rtwn.c

134

int, uint32_t, int);

sys/dev/ic/rtwn.c

136

int, uint32_t, int);

sys/dev/ic/rtwn.c

1756

uint32_t reg;

sys/dev/ic/rtwn.c

1875

uint32_t reg, type;

sys/dev/ic/rtwn.c

2087

uint32_t reg;

sys/dev/ic/rtwn.c

2413

uint32_t reg;

sys/dev/ic/rtwn.c

2571

uint32_t status;

sys/dev/ic/rtwn.c

2573

uint32_t iqk_tone_92c[] = {

sys/dev/ic/rtwn.c

2576

uint32_t iqk_tone_92e[] = {

sys/dev/ic/rtwn.c

2579

uint32_t *iqk_tone;

sys/dev/ic/rtwn.c

2656

static const uint32_t adda_92c[] = {

sys/dev/ic/rtwn.c

2659

static const uint32_t adda_92e[] = {

sys/dev/ic/rtwn.c

2662

const uint32_t *adda_vals;

sys/dev/ic/rtwn.c

2665

uint32_t hssi_param1, reg;

sys/dev/ic/rtwn.c

2906

uint32_t reg, val, x;

sys/dev/ic/rtwn.c

3008

uint32_t rf_ac[2];

sys/dev/ic/rtwn.c

3125

uint32_t imask = 0;

sys/dev/ic/rtwn.c

3165

uint32_t reg;

sys/dev/ic/rtwn.c

371

rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val)

sys/dev/ic/rtwn.c

388

uint32_t

sys/dev/ic/rtwn.c

438

rtwn_rf_write(struct rtwn_softc *sc, int chain, uint16_t addr, uint32_t val)

sys/dev/ic/rtwn.c

440

uint32_t param_addr;

sys/dev/ic/rtwn.c

463

uint32_t

sys/dev/ic/rtwn.c

466

uint32_t reg[R92C_MAX_CHAINS], val;

sys/dev/ic/rtwn.c

495

rtwn_cam_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data)

sys/dev/ic/rtwn.c

506

uint32_t reg;

sys/dev/ic/rtwn.c

530

uint32_t reg;

sys/dev/ic/rtwn.c

616

uint32_t reg;

sys/dev/ic/rtwn.c

792

uint32_t rates, basicrates;

sys/dev/ic/rtwn.c

862

int maxrate, uint32_t basicrates, int maxbasicrate)

sys/dev/ic/rtwn.c

900

int maxrate, uint32_t basicrates, int maxbasicrate)

sys/dev/ic/rtwn.c

95

uint32_t adda[16];

sys/dev/ic/rtwn.c

99

uint32_t gpio_muxcfg;

sys/dev/ic/rtwnvar.h

118

uint32_t rf_chnlbw[R92C_MAX_CHAINS];

sys/dev/ic/rtwnvar.h

26

uint32_t (*read_4)(void *, uint16_t);

sys/dev/ic/rtwnvar.h

29

void (*write_4)(void *, uint16_t, uint32_t);

sys/dev/ic/rtwnvar.h

71

uint32_t sc_flags;

sys/dev/ic/rtwnvar.h

77

uint32_t chip;

sys/dev/ic/rtwvar.h

219

uint32_t tdb_base;

sys/dev/ic/sti.c

113

int32_t sti_gvid(void *, uint32_t, uint32_t *);

sys/dev/ic/sti.c

1272

int *cxp, int *cyp, uint32_t *defattr)

sys/dev/ic/sti.c

1381

sti_putchar(void *v, int row, int col, u_int uc, uint32_t attr)

sys/dev/ic/sti.c

1458

sti_erasecols(void *v, int row, int startcol, int ncols, uint32_t attr)

sys/dev/ic/sti.c

1484

sti_eraserows(void *v, int srcrow, int nrows, uint32_t attr)

sys/dev/ic/sti.c

1496

sti_pack_attr(void *v, int fg, int bg, int flags, uint32_t *pattr)

sys/dev/ic/sti.c

1507

sti_unpack_attr(void *v, uint32_t attr, int *fg, int *bg, int *ul)

sys/dev/ic/sti.c

1540

void ngle_setup_fb(bus_space_tag_t, bus_space_handle_t, uint32_t);

sys/dev/ic/sti.c

1648

uint32_t cmap_finish;

sys/dev/ic/sti.c

1695

ngle_setup_fb(bus_space_tag_t memt, bus_space_handle_t memh, uint32_t reg10)

sys/dev/ic/sti.c

521

sti_gvid(void *v, uint32_t cmd, uint32_t *params)

sys/dev/ic/sti.c

56

int sti_pack_attr(void *, int, int, int, uint32_t *);

sys/dev/ic/sti.c

60

int sti_erasecols(void *, int, int, int, uint32_t);

sys/dev/ic/sti.c

61

int sti_eraserows(void *, int, int, uint32_t);

sys/dev/ic/sti.c

63

int sti_putchar(void *, int, int, u_int, uint32_t);

sys/dev/ic/sti.c

64

void sti_unpack_attr(void *, uint32_t, int *, int *, int *);

sys/dev/ic/sti.c

79

int *, uint32_t *);

sys/dev/ic/sti.c

834

uint32_t defattr;

sys/dev/ic/stivar.h

105

uint32_t reg10_value;

sys/dev/ic/stivar.h

106

uint32_t reg12_value;

sys/dev/ic/ufshci.c

1038

utrd->dw4 = (uint32_t)dva;

sys/dev/ic/ufshci.c

1039

utrd->dw5 = (uint32_t)(dva >> 32);

sys/dev/ic/ufshci.c

1059

ucd->prdt[i].dw0 = (uint32_t)dva;

sys/dev/ic/ufshci.c

1060

ucd->prdt[i].dw1 = (uint32_t)(dva >> 32);

sys/dev/ic/ufshci.c

1093

uint32_t blocks;

sys/dev/ic/ufshci.c

1159

utrd->dw4 = (uint32_t)dva;

sys/dev/ic/ufshci.c

1160

utrd->dw5 = (uint32_t)(dva >> 32);

sys/dev/ic/ufshci.c

1180

ucd->prdt[i].dw0 = (uint32_t)dva;

sys/dev/ic/ufshci.c

1181

ucd->prdt[i].dw1 = (uint32_t)(dva >> 32);

sys/dev/ic/ufshci.c

1210

struct scsi_xfer *xs, uint32_t lba, uint16_t blocks)

sys/dev/ic/ufshci.c

1271

utrd->dw4 = (uint32_t)dva;

sys/dev/ic/ufshci.c

1272

utrd->dw5 = (uint32_t)(dva >> 32);

sys/dev/ic/ufshci.c

129

uint32_t status, hcs;

sys/dev/ic/ufshci.c

1312

uint32_t reg;

sys/dev/ic/ufshci.c

1696

uint32_t blocks;

sys/dev/ic/ufshci.c

1709

error = ufshci_utr_cmd_sync(sc, ccb, xs, (uint32_t)lba,

sys/dev/ic/ufshci.c

1876

uint32_t secsize; /* Our sector size */

sys/dev/ic/ufshci.c

1882

uint32_t blocks, reg;

sys/dev/ic/ufshci.c

1904

(uint32_t)page_bus_phys);

sys/dev/ic/ufshci.c

1906

(uint32_t)(page_bus_phys >> 32));

sys/dev/ic/ufshci.c

1969

my->utrd.dw4 = (uint32_t)page_bus_phys;

sys/dev/ic/ufshci.c

1970

my->utrd.dw5 = (uint32_t)(page_bus_phys >> 32);

sys/dev/ic/ufshci.c

1985

my->ucd.prdt[0].dw0 = (uint32_t)data_bus_phys;

sys/dev/ic/ufshci.c

1986

my->ucd.prdt[0].dw1 = (uint32_t)(data_bus_phys >> 32);

sys/dev/ic/ufshci.c

284

uint32_t hce;

sys/dev/ic/ufshci.c

311

ufshci_is_poll(struct ufshci_softc *sc, uint32_t type)

sys/dev/ic/ufshci.c

313

uint32_t status;

sys/dev/ic/ufshci.c

427

uint32_t reg;

sys/dev/ic/ufshci.c

486

UFSHCI_WRITE_4(sc, UFSHCI_REG_UTMRLBA, (uint32_t)dva);

sys/dev/ic/ufshci.c

487

UFSHCI_WRITE_4(sc, UFSHCI_REG_UTMRLBAU, (uint32_t)(dva >> 32));

sys/dev/ic/ufshci.c

492

UFSHCI_WRITE_4(sc, UFSHCI_REG_UTRLBA, (uint32_t)dva);

sys/dev/ic/ufshci.c

493

UFSHCI_WRITE_4(sc, UFSHCI_REG_UTRLBAU, (uint32_t)(dva >> 32));

sys/dev/ic/ufshci.c

523

uint32_t reg;

sys/dev/ic/ufshci.c

533

uint32_t reg;

sys/dev/ic/ufshci.c

541

ufshci_doorbell_poll(struct ufshci_softc *sc, int slot, uint32_t timeout_ms)

sys/dev/ic/ufshci.c

543

uint32_t reg;

sys/dev/ic/ufshci.c

614

utrd->dw4 = (uint32_t)dva;

sys/dev/ic/ufshci.c

615

utrd->dw5 = (uint32_t)(dva >> 32);

sys/dev/ic/ufshci.c

64

int ufshci_is_poll(struct ufshci_softc *, uint32_t);

sys/dev/ic/ufshci.c

713

utrd->dw4 = (uint32_t)dva;

sys/dev/ic/ufshci.c

714

utrd->dw5 = (uint32_t)(dva >> 32);

sys/dev/ic/ufshci.c

734

ucd->prdt[i].dw0 = (uint32_t)dva;

sys/dev/ic/ufshci.c

735

ucd->prdt[i].dw1 = (uint32_t)(dva >> 32);

sys/dev/ic/ufshci.c

74

uint32_t);

sys/dev/ic/ufshci.c

819

utrd->dw4 = (uint32_t)dva;

sys/dev/ic/ufshci.c

820

utrd->dw5 = (uint32_t)(dva >> 32);

sys/dev/ic/ufshci.c

840

ucd->prdt[i].dw0 = (uint32_t)dva;

sys/dev/ic/ufshci.c

841

ucd->prdt[i].dw1 = (uint32_t)(dva >> 32);

sys/dev/ic/ufshci.c

89

uint32_t, uint16_t);

sys/dev/ic/ufshci.c

929

utrd->dw4 = (uint32_t)dva;

sys/dev/ic/ufshci.c

930

utrd->dw5 = (uint32_t)(dva >> 32);

sys/dev/ic/ufshci.c

950

ucd->prdt[i].dw0 = (uint32_t)dva;

sys/dev/ic/ufshci.c

951

ucd->prdt[i].dw1 = (uint32_t)(dva >> 32);

sys/dev/ic/ufshcireg.h

270

uint32_t dw0; /* CT, DD, I, CE, CCI */

sys/dev/ic/ufshcireg.h

271

uint32_t dw1; /* Data Unit Number Lower 32-bits (DUNL) */

sys/dev/ic/ufshcireg.h

272

uint32_t dw2; /* OCS */

sys/dev/ic/ufshcireg.h

273

uint32_t dw3; /* Data Unit Number Upper 32-bits (DUNU) */

sys/dev/ic/ufshcireg.h

274

uint32_t dw4; /* UTP Cmd. Desc. Base Addr. Lower 32-bits (UCDBA) */

sys/dev/ic/ufshcireg.h

275

uint32_t dw5; /* UTP Cmd. Desc. Base Addr. Upper 32-bits (UCDBAU) */

sys/dev/ic/ufshcireg.h

276

uint32_t dw6; /* RUO, RUL */

sys/dev/ic/ufshcireg.h

277

uint32_t dw7; /* PRDTO, PRDTL */

sys/dev/ic/ufshcireg.h

291

uint32_t dw0; /* Data base Address Lower 32-bits (DBA) */

sys/dev/ic/ufshcireg.h

292

uint32_t dw1; /* Data base Address Upper 32-bits (DBAU) */

sys/dev/ic/ufshcireg.h

293

uint32_t dw2; /* Reserved */

sys/dev/ic/ufshcireg.h

294

uint32_t dw3; /* Data Byte Count (DBC) */

sys/dev/ic/ufshcireg.h

321

uint32_t dw0; /* I */

sys/dev/ic/ufshcireg.h

322

uint32_t dw1; /* Reserved */

sys/dev/ic/ufshcireg.h

323

uint32_t dw2; /* OCS */

sys/dev/ic/ufshcireg.h

324

uint32_t dw3; /* Reserved */

sys/dev/ic/ufshcireg.h

369

uint32_t expected_xfer_len;

sys/dev/ic/ufshcireg.h

375

uint32_t residual_xfer_len;

sys/dev/ic/ufshcivar.h

77

uint32_t sc_ver;

sys/dev/ic/ufshcivar.h

78

uint32_t sc_cap;

sys/dev/ic/ufshcivar.h

79

uint32_t sc_hcpid;

sys/dev/ic/ufshcivar.h

80

uint32_t sc_hcmid;

sys/dev/ic/vga.c

1020

vga_unpack_attr(void *id, uint32_t attr, int *fg, int *bg, int *ul)

sys/dev/ic/vga.c

109

const struct wsscreen_descr *, int, uint32_t *);

sys/dev/ic/vga.c

115

int vga_putchar(void *, int, int, u_int, uint32_t);

sys/dev/ic/vga.c

1153

vga_putchar(void *c, int row, int col, u_int uc, uint32_t attr)

sys/dev/ic/vga.c

116

int vga_pack_attr(void *, int, int, int, uint32_t *);

sys/dev/ic/vga.c

118

void vga_unpack_attr(void *, uint32_t, int *, int *, int *);

sys/dev/ic/vga.c

247

void **, int *, int *, uint32_t *);

sys/dev/ic/vga.c

399

const struct wsscreen_descr *type, int existing, uint32_t *attrp)

sys/dev/ic/vga.c

576

uint32_t defattr;

sys/dev/ic/vga.c

671

int *curxp, int *curyp, uint32_t *defattrp)

sys/dev/ic/vga.c

988

vga_pack_attr(void *id, int fg, int bg, int flags, uint32_t *attrp)

sys/dev/ic/w83l518d_sdmmc.c

224

uint32_t

sys/dev/ic/w83l518d_sdmmc.c

273

wb_sdmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)

sys/dev/ic/w83l518d_sdmmc.c

61

uint32_t wb_sdmmc_host_ocr(sdmmc_chipset_handle_t);

sys/dev/ic/w83l518d_sdmmc.c

67

int wb_sdmmc_bus_power(sdmmc_chipset_handle_t, uint32_t);

sys/dev/isa/pcdisplay.c

111

void **, int *, int *, uint32_t *);

sys/dev/isa/pcdisplay.c

338

void **cookiep, int *curxp, int *curyp, uint32_t *defattrp)

sys/dev/isa/pcdisplay.c

378

pcdisplay_pack_attr(void *id, int fg, int bg, int flags, uint32_t *attrp)

sys/dev/isa/pcdisplay.c

388

pcdisplay_unpack_attr(void *id, uint32_t attr, int *fg, int *bg, int *ul)

sys/dev/isa/pcdisplay.c

73

static int pcdisplay_pack_attr(void *, int, int, int, uint32_t *);

sys/dev/isa/pcdisplay.c

74

static void pcdisplay_unpack_attr(void *, uint32_t, int *, int *, int *);

sys/dev/kcov.c

204

__sanitizer_cov_trace_cmp4(uint32_t arg1, uint32_t arg2)

sys/dev/kcov.c

228

__sanitizer_cov_trace_const_cmp4(uint32_t arg1, uint32_t arg2)

sys/dev/microcode/aic7xxx/aic79xx_seq.h

1033

uint32_t begin :10,

sys/dev/microcode/aic7xxx/aic7xxx_seq.h

1087

uint32_t begin :10,

sys/dev/microcode/aic7xxx/aicasm_insformat.h

103

uint32_t integer;

sys/dev/microcode/aic7xxx/aicasm_insformat.h

48

uint32_t immediate : 8,

sys/dev/microcode/aic7xxx/aicasm_insformat.h

55

uint32_t parity : 1,

sys/dev/microcode/aic7xxx/aicasm_insformat.h

66

uint32_t shift_control : 8,

sys/dev/microcode/aic7xxx/aicasm_insformat.h

73

uint32_t parity : 1,

sys/dev/microcode/aic7xxx/aicasm_insformat.h

84

uint32_t immediate : 8,

sys/dev/microcode/aic7xxx/aicasm_insformat.h

90

uint32_t parity : 1,

sys/dev/microcode/isp/asm_2400.h

37

static const uint32_t isp_2400_risc_code[] = {

sys/dev/microcode/isp/asm_2500.h

12828

static const uint32_t isp_2500_multi_risc_code[] = {

sys/dev/microcode/isp/asm_2500.h

35

static const uint32_t isp_2500_risc_code[] = {

sys/dev/microcode/udl/build.c

35

uint32_t bit_count;

sys/dev/microcode/udl/build.c

36

uint32_t bit_pattern;

sys/dev/microcode/udl/udl_huffman.h

17

uint32_t bit_count;

sys/dev/microcode/udl/udl_huffman.h

18

uint32_t bit_pattern;

sys/dev/mii/atphy.c

285

uint32_t bmsr, bmcr, gsr, ssr;

sys/dev/mii/atphy.c

348

uint32_t reg;

sys/dev/mii/brgphy.c

1167

uint32_t val;

sys/dev/mii/brswphy.c

171

uint32_t *val);

sys/dev/mii/brswphy.c

296

uint32_t speed;

sys/dev/mii/brswphy.c

380

brswphy_read32(struct mii_softc *sc, uint8_t page, uint8_t reg, uint32_t *val)

sys/dev/mii/eephy.c

205

uint32_t mode;

sys/dev/mii/eephy.c

449

uint32_t *prop, opage;

sys/dev/mii/eephy.c

456

if (len <= 0 || len % (4 * sizeof(uint32_t)) != 0)

sys/dev/mii/eephy.c

464

uint32_t page = prop[i + 0];

sys/dev/mii/eephy.c

465

uint32_t reg = prop[i + 1];

sys/dev/mii/eephy.c

466

uint32_t keep = prop[i + 2];

sys/dev/mii/eephy.c

467

uint32_t set = prop[i + 3];

sys/dev/mii/eephy.c

468

uint32_t val = 0;

sys/dev/mii/ipgphy.c

134

uint32_t gig, reg, speed;

sys/dev/mii/ipgphy.c

271

uint32_t bmsr, bmcr, stat;

sys/dev/mii/ipgphy.c

352

uint32_t reg = 0;

sys/dev/mii/ipgphy.c

396

uint32_t reg;

sys/dev/mii/ytphy.c

290

uint32_t rx_delay = 1950;

sys/dev/mii/ytphy.c

291

uint32_t tx_delay = 1950;

sys/dev/mii/ytphy.c

388

uint32_t volt; /* mV */

sys/dev/mii/ytphy.c

412

uint32_t

sys/dev/mii/ytphy.c

413

ytphy_yt8531_ds(struct mii_softc *sc, uint32_t volt, uint32_t amp)

sys/dev/mii/ytphy.c

435

uint32_t rx_clk_drv = 0;

sys/dev/mii/ytphy.c

436

uint32_t rx_data_drv = 0;

sys/dev/mii/ytphy.c

437

uint32_t clk_out_freq = 0;

sys/dev/ofw/fdt.c

1007

uint32_t

sys/dev/ofw/fdt.c

1008

OF_getpropint(int handle, char *prop, uint32_t defval)

sys/dev/ofw/fdt.c

1010

uint32_t val;

sys/dev/ofw/fdt.c

1021

OF_getpropintarray(int handle, char *prop, uint32_t *buf, int buflen)

sys/dev/ofw/fdt.c

1027

if (len < 0 || (len % sizeof(uint32_t)))

sys/dev/ofw/fdt.c

1030

for (i = 0; i < min(len, buflen) / sizeof(uint32_t); i++)

sys/dev/ofw/fdt.c

149

size_t len = roundup(strlen(name) + 1, sizeof(uint32_t));

sys/dev/ofw/fdt.c

245

uint32_t *ptr, *next;

sys/dev/ofw/fdt.c

246

uint32_t nameid;

sys/dev/ofw/fdt.c

247

uint32_t curlen;

sys/dev/ofw/fdt.c

254

ptr = (uint32_t *)node;

sys/dev/ofw/fdt.c

267

delta = roundup(len, sizeof(uint32_t)) -

sys/dev/ofw/fdt.c

268

roundup(curlen, sizeof(uint32_t));

sys/dev/ofw/fdt.c

295

uint32_t *ptr = (uint32_t *)node;

sys/dev/ofw/fdt.c

303

tree.struct_size += 3 * sizeof(uint32_t);

sys/dev/ofw/fdt.c

305

tree.strings += 3 * sizeof(uint32_t);

sys/dev/ofw/fdt.c

307

tree.memory += 3 * sizeof(uint32_t);

sys/dev/ofw/fdt.c

308

tree.end += 3 * sizeof(uint32_t);

sys/dev/ofw/fdt.c

35

void *fdt_find_phandle_recurse(void *, uint32_t);

sys/dev/ofw/fdt.c

354

ptr = skip_nops((uint32_t *)tree.tree);

sys/dev/ofw/fdt.c

575

fdt_find_phandle_recurse(void *node, uint32_t phandle)

sys/dev/ofw/fdt.c

586

if (len == sizeof(uint32_t) && bemtoh32(data) == phandle)

sys/dev/ofw/fdt.c

597

fdt_find_phandle(uint32_t phandle)

sys/dev/ofw/fdt.c

931

OF_getnodebyphandle(uint32_t phandle)

sys/dev/ofw/fdt.h

68

void *fdt_find_phandle(uint32_t);

sys/dev/ofw/ofw_clock.c

112

clock_enable_cells(uint32_t *cells, int on)

sys/dev/ofw/ofw_clock.c

115

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_clock.c

126

uint32_t *

sys/dev/ofw/ofw_clock.c

127

clock_next_clock(uint32_t *cells)

sys/dev/ofw/ofw_clock.c

129

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_clock.c

140

uint32_t

sys/dev/ofw/ofw_clock.c

143

uint32_t *clocks;

sys/dev/ofw/ofw_clock.c

144

uint32_t *clock;

sys/dev/ofw/ofw_clock.c

145

uint32_t freq = 0;

sys/dev/ofw/ofw_clock.c

156

while (clock && clock < clocks + (len / sizeof(uint32_t))) {

sys/dev/ofw/ofw_clock.c

169

uint32_t

sys/dev/ofw/ofw_clock.c

182

clock_set_frequency_idx(int node, int idx, uint32_t freq)

sys/dev/ofw/ofw_clock.c

184

uint32_t *clocks;

sys/dev/ofw/ofw_clock.c

185

uint32_t *clock;

sys/dev/ofw/ofw_clock.c

197

while (clock && clock < clocks + (len / sizeof(uint32_t))) {

sys/dev/ofw/ofw_clock.c

211

clock_set_frequency(int node, const char *name, uint32_t freq)

sys/dev/ofw/ofw_clock.c

225

uint32_t *clocks;

sys/dev/ofw/ofw_clock.c

226

uint32_t *clock;

sys/dev/ofw/ofw_clock.c

237

while (clock && clock < clocks + (len / sizeof(uint32_t))) {

sys/dev/ofw/ofw_clock.c

288

uint32_t *clocks, *parents, *rates;

sys/dev/ofw/ofw_clock.c

289

uint32_t *clock, *parent, *rate;

sys/dev/ofw/ofw_clock.c

313

while (clock && clock < clocks + (clen / sizeof(uint32_t))) {

sys/dev/ofw/ofw_clock.c

314

if (parent && parent < parents + (plen / sizeof(uint32_t)))

sys/dev/ofw/ofw_clock.c

318

if (rate && rate < rates + (rlen / sizeof(uint32_t)))

sys/dev/ofw/ofw_clock.c

353

reset_assert_cells(uint32_t *cells, int assert)

sys/dev/ofw/ofw_clock.c

356

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_clock.c

367

uint32_t *

sys/dev/ofw/ofw_clock.c

368

reset_next_reset(uint32_t *cells)

sys/dev/ofw/ofw_clock.c

370

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_clock.c

384

uint32_t *resets;

sys/dev/ofw/ofw_clock.c

385

uint32_t *reset;

sys/dev/ofw/ofw_clock.c

396

while (reset && reset < resets + (len / sizeof(uint32_t))) {

sys/dev/ofw/ofw_clock.c

43

uint32_t

sys/dev/ofw/ofw_clock.c

44

clock_get_frequency_cells(uint32_t *cells)

sys/dev/ofw/ofw_clock.c

47

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_clock.c

66

uint32_t mult, div, freq;

sys/dev/ofw/ofw_clock.c

78

clock_set_frequency_cells(uint32_t *cells, uint32_t freq)

sys/dev/ofw/ofw_clock.c

81

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_clock.c

95

clock_set_parent_cells(uint32_t *cells, uint32_t *pcells)

sys/dev/ofw/ofw_clock.c

98

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_clock.h

24

uint32_t (*cd_get_frequency)(void *, uint32_t *);

sys/dev/ofw/ofw_clock.h

25

int (*cd_set_frequency)(void *, uint32_t *, uint32_t);

sys/dev/ofw/ofw_clock.h

26

int (*cd_set_parent)(void *, uint32_t *, uint32_t *);

sys/dev/ofw/ofw_clock.h

27

void (*cd_enable)(void *, uint32_t *, int);

sys/dev/ofw/ofw_clock.h

30

uint32_t cd_phandle;

sys/dev/ofw/ofw_clock.h

31

uint32_t cd_cells;

sys/dev/ofw/ofw_clock.h

36

uint32_t clock_get_frequency(int, const char *);

sys/dev/ofw/ofw_clock.h

37

uint32_t clock_get_frequency_idx(int, int);

sys/dev/ofw/ofw_clock.h

38

int clock_set_frequency(int, const char *, uint32_t);

sys/dev/ofw/ofw_clock.h

39

int clock_set_frequency_idx(int, int idx, uint32_t);

sys/dev/ofw/ofw_clock.h

61

void (*rd_reset)(void *, uint32_t *, int);

sys/dev/ofw/ofw_clock.h

64

uint32_t rd_phandle;

sys/dev/ofw/ofw_clock.h

65

uint32_t rd_cells;

sys/dev/ofw/ofw_gpio.c

102

gpio_controller_get_pin(uint32_t *cells)

sys/dev/ofw/ofw_gpio.c

105

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_gpio.c

120

gpio_controller_set_pin(uint32_t *cells, int val)

sys/dev/ofw/ofw_gpio.c

123

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_gpio.c

134

uint32_t *

sys/dev/ofw/ofw_gpio.c

135

gpio_controller_next_pin(uint32_t *cells)

sys/dev/ofw/ofw_gpio.c

138

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_gpio.c

148

gpio_controller_intr_establish(uint32_t *cells, int ipl, struct cpu_info *ci,

sys/dev/ofw/ofw_gpio.c

152

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_gpio.c

44

uint32_t *gpios;

sys/dev/ofw/ofw_gpio.c

45

uint32_t *gpio;

sys/dev/ofw/ofw_gpio.c

75

while (gpio && gpio < gpios + (len / sizeof(uint32_t))) {

sys/dev/ofw/ofw_gpio.c

87

gpio_controller_config_pin(uint32_t *cells, int config)

sys/dev/ofw/ofw_gpio.c

90

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_gpio.h

34

void (*gc_config_pin)(void *, uint32_t *, int);

sys/dev/ofw/ofw_gpio.h

35

int (*gc_get_pin)(void *, uint32_t *);

sys/dev/ofw/ofw_gpio.h

36

void (*gc_set_pin)(void *, uint32_t *, int);

sys/dev/ofw/ofw_gpio.h

37

void *(*gc_intr_establish)(void *, uint32_t *, int,

sys/dev/ofw/ofw_gpio.h

41

uint32_t gc_phandle;

sys/dev/ofw/ofw_gpio.h

42

uint32_t gc_cells;

sys/dev/ofw/ofw_gpio.h

55

void gpio_controller_config_pin(uint32_t *, int);

sys/dev/ofw/ofw_gpio.h

57

int gpio_controller_get_pin(uint32_t *);

sys/dev/ofw/ofw_gpio.h

58

void gpio_controller_set_pin(uint32_t *, int);

sys/dev/ofw/ofw_gpio.h

59

uint32_t *gpio_controller_next_pin(uint32_t *);

sys/dev/ofw/ofw_gpio.h

61

void *gpio_controller_intr_establish(uint32_t *, int, struct cpu_info *,

sys/dev/ofw/ofw_misc.c

1023

mii_byphandle(uint32_t phandle)

sys/dev/ofw/ofw_misc.c

1057

iommu_device_do_map(uint32_t phandle, uint32_t *cells, bus_dma_tag_t dmat)

sys/dev/ofw/ofw_misc.c

1073

iommu_device_lookup(int node, uint32_t *phandle, uint32_t *cells)

sys/dev/ofw/ofw_misc.c

1075

uint32_t *cell;

sys/dev/ofw/ofw_misc.c

1076

uint32_t *map;

sys/dev/ofw/ofw_misc.c

1089

ncells = len / sizeof(uint32_t);

sys/dev/ofw/ofw_misc.c

109

regmap_write_4(struct regmap *rm, bus_size_t offset, uint32_t value)

sys/dev/ofw/ofw_misc.c

111

KASSERT(offset <= rm->rm_size - sizeof(uint32_t));

sys/dev/ofw/ofw_misc.c

1118

iommu_device_lookup_pci(int node, uint32_t rid, uint32_t *phandle,

sys/dev/ofw/ofw_misc.c

1119

uint32_t *cells)

sys/dev/ofw/ofw_misc.c

1121

uint32_t sid_base;

sys/dev/ofw/ofw_misc.c

1122

uint32_t *cell;

sys/dev/ofw/ofw_misc.c

1123

uint32_t *map;

sys/dev/ofw/ofw_misc.c

1124

uint32_t mask, rid_base;

sys/dev/ofw/ofw_misc.c

1139

ncells = len / sizeof(uint32_t);

sys/dev/ofw/ofw_misc.c

115

uint32_t

sys/dev/ofw/ofw_misc.c

1171

uint32_t phandle, cells[2] = {0};

sys/dev/ofw/ofw_misc.c

118

KASSERT(offset <= rm->rm_size - sizeof(uint32_t));

sys/dev/ofw/ofw_misc.c

1180

iommu_device_map_pci(int node, uint32_t rid, bus_dma_tag_t dmat)

sys/dev/ofw/ofw_misc.c

1182

uint32_t phandle, cells[2] = {0};

sys/dev/ofw/ofw_misc.c

1191

iommu_device_do_reserve(uint32_t phandle, uint32_t *cells, bus_addr_t addr,

sys/dev/ofw/ofw_misc.c

1208

iommu_reserve_region_pci(int node, uint32_t rid, bus_addr_t addr,

sys/dev/ofw/ofw_misc.c

1211

uint32_t phandle, cells[2] = {0};

sys/dev/ofw/ofw_misc.c

1243

mbox_channel_cells(uint32_t *cells, struct mbox_client *client)

sys/dev/ofw/ofw_misc.c

1247

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_misc.c

1268

uint32_t *

sys/dev/ofw/ofw_misc.c

1269

mbox_next_mbox(uint32_t *cells)

sys/dev/ofw/ofw_misc.c

1271

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_misc.c

1286

uint32_t *mboxes;

sys/dev/ofw/ofw_misc.c

1287

uint32_t *mbox;

sys/dev/ofw/ofw_misc.c

1298

while (mbox && mbox < mboxes + (len / sizeof(uint32_t))) {

sys/dev/ofw/ofw_misc.c

1362

hwlock_lock_cells(uint32_t *cells, int lock)

sys/dev/ofw/ofw_misc.c

1365

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_misc.c

1378

uint32_t *

sys/dev/ofw/ofw_misc.c

1379

hwlock_next_hwlock(uint32_t *cells)

sys/dev/ofw/ofw_misc.c

1381

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_misc.c

1395

uint32_t *hwlocks;

sys/dev/ofw/ofw_misc.c

1396

uint32_t *hwlock;

sys/dev/ofw/ofw_misc.c

1408

while (hwlock && hwlock < hwlocks + (len / sizeof(uint32_t))) {

sys/dev/ofw/ofw_misc.c

151

if_byphandle(uint32_t phandle)

sys/dev/ofw/ofw_misc.c

187

uint32_t vcc_supply;

sys/dev/ofw/ofw_misc.c

188

uint32_t *gpio;

sys/dev/ofw/ofw_misc.c

214

phy_enable_cells(uint32_t *cells)

sys/dev/ofw/ofw_misc.c

217

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_misc.c

238

uint32_t *

sys/dev/ofw/ofw_misc.c

239

phy_next_phy(uint32_t *cells)

sys/dev/ofw/ofw_misc.c

241

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_misc.c

255

uint32_t *phys;

sys/dev/ofw/ofw_misc.c

256

uint32_t *phy;

sys/dev/ofw/ofw_misc.c

268

while (phy && phy < phys + (len / sizeof(uint32_t))) {

sys/dev/ofw/ofw_misc.c

330

i2c_byphandle(uint32_t phandle)

sys/dev/ofw/ofw_misc.c

363

sfp_do_enable(uint32_t phandle, int enable)

sys/dev/ofw/ofw_misc.c

379

sfp_enable(uint32_t phandle)

sys/dev/ofw/ofw_misc.c

385

sfp_disable(uint32_t phandle)

sys/dev/ofw/ofw_misc.c

391

sfp_get_sffpage(uint32_t phandle, struct if_sffpage *sff)

sys/dev/ofw/ofw_misc.c

41

uint32_t rm_phandle;

sys/dev/ofw/ofw_misc.c

421

sfp_add_media(uint32_t phandle, struct mii_data *mii)

sys/dev/ofw/ofw_misc.c

501

pwm_init_state(uint32_t *cells, struct pwm_state *ps)

sys/dev/ofw/ofw_misc.c

522

pwm_get_state(uint32_t *cells, struct pwm_state *ps)

sys/dev/ofw/ofw_misc.c

535

pwm_set_state(uint32_t *cells, struct pwm_state *ps)

sys/dev/ofw/ofw_misc.c

555

uint32_t nc_phandle;

sys/dev/ofw/ofw_misc.c

559

uint32_t nc_offset;

sys/dev/ofw/ofw_misc.c

560

uint32_t nc_bitlen;

sys/dev/ofw/ofw_misc.c

572

uint32_t phandle;

sys/dev/ofw/ofw_misc.c

573

uint32_t reg[2], bits[2] = {};

sys/dev/ofw/ofw_misc.c

608

nvmem_read(uint32_t phandle, bus_addr_t addr, void *data, bus_size_t size)

sys/dev/ofw/ofw_misc.c

630

uint32_t phandle, *phandles;

sys/dev/ofw/ofw_misc.c

631

uint32_t offset, bitlen;

sys/dev/ofw/ofw_misc.c

705

uint32_t phandle, *phandles;

sys/dev/ofw/ofw_misc.c

706

uint32_t offset, bitlen;

sys/dev/ofw/ofw_misc.c

838

device_ports_byphandle(uint32_t phandle)

sys/dev/ofw/ofw_misc.c

854

endpoint_byphandle(uint32_t phandle)

sys/dev/ofw/ofw_misc.c

870

endpoint_byreg(struct device_ports *ports, uint32_t dp_reg, uint32_t ep_reg)

sys/dev/ofw/ofw_misc.c

921

device_port_activate(uint32_t phandle, void *arg)

sys/dev/ofw/ofw_misc.c

93

regmap_byphandle(uint32_t phandle)

sys/dev/ofw/ofw_misc.c

983

dai_byphandle(uint32_t phandle)

sys/dev/ofw/ofw_misc.h

101

uint32_t sd_phandle;

sys/dev/ofw/ofw_misc.h

107

int sfp_enable(uint32_t);

sys/dev/ofw/ofw_misc.h

108

int sfp_disable(uint32_t);

sys/dev/ofw/ofw_misc.h

109

int sfp_add_media(uint32_t, struct mii_data *);

sys/dev/ofw/ofw_misc.h

110

int sfp_get_sffpage(uint32_t, struct if_sffpage *);

sys/dev/ofw/ofw_misc.h

117

uint32_t ps_period;

sys/dev/ofw/ofw_misc.h

118

uint32_t ps_pulse_width;

sys/dev/ofw/ofw_misc.h

119

uint32_t ps_flags;

sys/dev/ofw/ofw_misc.h

126

int (*pd_get_state)(void *, uint32_t *, struct pwm_state *);

sys/dev/ofw/ofw_misc.h

127

int (*pd_set_state)(void *, uint32_t *, struct pwm_state *);

sys/dev/ofw/ofw_misc.h

130

uint32_t pd_phandle;

sys/dev/ofw/ofw_misc.h

131

uint32_t pd_cells;

sys/dev/ofw/ofw_misc.h

136

int pwm_init_state(uint32_t *cells, struct pwm_state *ps);

sys/dev/ofw/ofw_misc.h

137

int pwm_get_state(uint32_t *cells, struct pwm_state *ps);

sys/dev/ofw/ofw_misc.h

138

int pwm_set_state(uint32_t *cells, struct pwm_state *ps);

sys/dev/ofw/ofw_misc.h

149

uint32_t nd_phandle;

sys/dev/ofw/ofw_misc.h

153

int nvmem_read(uint32_t, bus_addr_t, void *, bus_size_t);

sys/dev/ofw/ofw_misc.h

173

uint32_t dp_phandle;

sys/dev/ofw/ofw_misc.h

174

uint32_t dp_reg;

sys/dev/ofw/ofw_misc.h

198

uint32_t ep_phandle;

sys/dev/ofw/ofw_misc.h

199

uint32_t ep_reg;

sys/dev/ofw/ofw_misc.h

207

struct device_ports *device_ports_byphandle(uint32_t);

sys/dev/ofw/ofw_misc.h

208

int device_port_activate(uint32_t, void *);

sys/dev/ofw/ofw_misc.h

209

struct endpoint *endpoint_byreg(struct device_ports *, uint32_t, uint32_t);

sys/dev/ofw/ofw_misc.h

220

int (*dd_set_format)(void *, uint32_t, uint32_t, uint32_t);

sys/dev/ofw/ofw_misc.h

221

int (*dd_set_sysclk)(void *, uint32_t);

sys/dev/ofw/ofw_misc.h

225

uint32_t dd_phandle;

sys/dev/ofw/ofw_misc.h

231

struct dai_device *dai_byphandle(uint32_t);

sys/dev/ofw/ofw_misc.h

266

struct mii_bus *mii_byphandle(uint32_t);

sys/dev/ofw/ofw_misc.h

273

bus_dma_tag_t (*id_map)(void *, uint32_t *, bus_dma_tag_t);

sys/dev/ofw/ofw_misc.h

274

void (*id_reserve)(void *, uint32_t *, bus_addr_t, bus_size_t);

sys/dev/ofw/ofw_misc.h

277

uint32_t id_phandle;

sys/dev/ofw/ofw_misc.h

28

struct regmap *regmap_byphandle(uint32_t);

sys/dev/ofw/ofw_misc.h

281

int iommu_device_lookup(int, uint32_t *, uint32_t *);

sys/dev/ofw/ofw_misc.h

282

int iommu_device_lookup_pci(int, uint32_t, uint32_t *, uint32_t *);

sys/dev/ofw/ofw_misc.h

284

bus_dma_tag_t iommu_device_map_pci(int, uint32_t, bus_dma_tag_t);

sys/dev/ofw/ofw_misc.h

285

void iommu_reserve_region_pci(int, uint32_t, bus_addr_t, bus_size_t);

sys/dev/ofw/ofw_misc.h

30

uint32_t regmap_read_4(struct regmap *, bus_size_t);

sys/dev/ofw/ofw_misc.h

301

void *(*md_channel)(void *, uint32_t *, struct mbox_client *);

sys/dev/ofw/ofw_misc.h

306

uint32_t md_phandle;

sys/dev/ofw/ofw_misc.h

307

uint32_t md_cells;

sys/dev/ofw/ofw_misc.h

31

void regmap_write_4(struct regmap *, bus_size_t, uint32_t);

sys/dev/ofw/ofw_misc.h

323

int (*hd_lock)(void *, uint32_t *, int);

sys/dev/ofw/ofw_misc.h

326

uint32_t hd_phandle;

sys/dev/ofw/ofw_misc.h

327

uint32_t hd_cells;

sys/dev/ofw/ofw_misc.h

42

uint32_t if_phandle;

sys/dev/ofw/ofw_misc.h

48

struct ifnet *if_byphandle(uint32_t);

sys/dev/ofw/ofw_misc.h

62

int (*pd_enable)(void *, uint32_t *);

sys/dev/ofw/ofw_misc.h

65

uint32_t pd_phandle;

sys/dev/ofw/ofw_misc.h

66

uint32_t pd_cells;

sys/dev/ofw/ofw_misc.h

83

uint32_t ib_phandle;

sys/dev/ofw/ofw_misc.h

89

struct i2c_controller *i2c_byphandle(uint32_t);

sys/dev/ofw/ofw_pinctrl.c

27

int (*pc_pinctrl)(uint32_t, void *);

sys/dev/ofw/ofw_pinctrl.c

33

void pinctrl_register_child(int, int (*)(uint32_t, void *), void *);

sys/dev/ofw/ofw_pinctrl.c

38

pinctrl_register(int node, int (*pinctrl)(uint32_t, void *), void *cookie)

sys/dev/ofw/ofw_pinctrl.c

45

pinctrl_register_child(int node, int (*pinctrl)(uint32_t, void *), void *cookie)

sys/dev/ofw/ofw_pinctrl.c

48

uint32_t phandle;

sys/dev/ofw/ofw_pinctrl.c

64

pinctrl_byphandle(uint32_t phandle)

sys/dev/ofw/ofw_pinctrl.c

83

uint32_t *phandles;

sys/dev/ofw/ofw_pinctrl.c

93

for (i = 0; i < len / sizeof(uint32_t); i++)

sys/dev/ofw/ofw_pinctrl.h

21

void pinctrl_register(int, int (*)(uint32_t, void *), void *);

sys/dev/ofw/ofw_pinctrl.h

23

int pinctrl_byphandle(uint32_t);

sys/dev/ofw/ofw_power.c

41

power_domain_enable_cells(uint32_t *cells, int on)

sys/dev/ofw/ofw_power.c

44

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_power.c

55

uint32_t *

sys/dev/ofw/ofw_power.c

56

power_domain_next_domain(uint32_t *cells)

sys/dev/ofw/ofw_power.c

58

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_power.c

72

uint32_t *domains;

sys/dev/ofw/ofw_power.c

73

uint32_t *domain;

sys/dev/ofw/ofw_power.c

84

while (domain && domain < domains + (len / sizeof(uint32_t))) {

sys/dev/ofw/ofw_power.h

25

void (*pd_enable)(void *, uint32_t *, int);

sys/dev/ofw/ofw_power.h

28

uint32_t pd_phandle;

sys/dev/ofw/ofw_power.h

29

uint32_t pd_cells;

sys/dev/ofw/ofw_regulator.c

111

uint32_t *gpio;

sys/dev/ofw/ofw_regulator.c

112

uint32_t startup_delay;

sys/dev/ofw/ofw_regulator.c

165

regulator_set(uint32_t phandle, int enable)

sys/dev/ofw/ofw_regulator.c

196

regulator_enable(uint32_t phandle)

sys/dev/ofw/ofw_regulator.c

202

regulator_disable(uint32_t phandle)

sys/dev/ofw/ofw_regulator.c

207

uint32_t

sys/dev/ofw/ofw_regulator.c

208

regulator_get_voltage(uint32_t phandle)

sys/dev/ofw/ofw_regulator.c

239

regulator_set_voltage(uint32_t phandle, uint32_t voltage)

sys/dev/ofw/ofw_regulator.c

242

uint32_t old, delta;

sys/dev/ofw/ofw_regulator.c

290

uint32_t

sys/dev/ofw/ofw_regulator.c

291

regulator_get_current(uint32_t phandle)

sys/dev/ofw/ofw_regulator.c

322

regulator_set_current(uint32_t phandle, uint32_t current)

sys/dev/ofw/ofw_regulator.c

325

uint32_t old, delta;

sys/dev/ofw/ofw_regulator.c

369

uint32_t

sys/dev/ofw/ofw_regulator.c

37

uint32_t regulator_gpio_get(int);

sys/dev/ofw/ofw_regulator.c

372

uint32_t *gpio, *gpios, *states;

sys/dev/ofw/ofw_regulator.c

373

uint32_t idx, value;

sys/dev/ofw/ofw_regulator.c

38

int regulator_gpio_set(int, uint32_t);

sys/dev/ofw/ofw_regulator.c

383

if (slen % (2 * sizeof(uint32_t)) != 0)

sys/dev/ofw/ofw_regulator.c

39

void regulator_do_notify(uint32_t, uint32_t);

sys/dev/ofw/ofw_regulator.c

395

while (gpio && gpio < gpios + (glen / sizeof(uint32_t))) {

sys/dev/ofw/ofw_regulator.c

403

for (i = 0; i < slen / (2 * sizeof(uint32_t)); i++) {

sys/dev/ofw/ofw_regulator.c

409

if (i >= slen / (2 * sizeof(uint32_t)))

sys/dev/ofw/ofw_regulator.c

419

regulator_gpio_set(int node, uint32_t value)

sys/dev/ofw/ofw_regulator.c

421

uint32_t phandle = OF_getpropint(node, "phandle", 0);

sys/dev/ofw/ofw_regulator.c

422

uint32_t *gpio, *gpios, *states;

sys/dev/ofw/ofw_regulator.c

423

uint32_t min, max;

sys/dev/ofw/ofw_regulator.c

424

uint32_t idx;

sys/dev/ofw/ofw_regulator.c

448

if (slen % (2 * sizeof(uint32_t)) != 0)

sys/dev/ofw/ofw_regulator.c

458

for (i = 0; i < slen / (2 * sizeof(uint32_t)); i++) {

sys/dev/ofw/ofw_regulator.c

466

if (i >= slen / (2 * sizeof(uint32_t)))

sys/dev/ofw/ofw_regulator.c

473

while (gpio && gpio < gpios + (glen / sizeof(uint32_t))) {

sys/dev/ofw/ofw_regulator.c

494

regulator_do_notify(uint32_t phandle, uint32_t value)

sys/dev/ofw/ofw_regulator.c

65

uint32_t voltage = rd->rd_get_voltage(rd->rd_cookie);

sys/dev/ofw/ofw_regulator.c

73

uint32_t current = rd->rd_get_current(rd->rd_cookie);

sys/dev/ofw/ofw_regulator.h

24

uint32_t (*rd_get_voltage)(void *);

sys/dev/ofw/ofw_regulator.h

25

int (*rd_set_voltage)(void *, uint32_t);

sys/dev/ofw/ofw_regulator.h

26

uint32_t (*rd_get_current)(void *);

sys/dev/ofw/ofw_regulator.h

27

int (*rd_set_current)(void *, uint32_t);

sys/dev/ofw/ofw_regulator.h

30

uint32_t rd_volt_min, rd_volt_max;

sys/dev/ofw/ofw_regulator.h

31

uint32_t rd_amp_min, rd_amp_max;

sys/dev/ofw/ofw_regulator.h

32

uint32_t rd_ramp_delay;

sys/dev/ofw/ofw_regulator.h

34

uint32_t rd_coupled;

sys/dev/ofw/ofw_regulator.h

35

uint32_t rd_max_spread;

sys/dev/ofw/ofw_regulator.h

38

uint32_t rd_phandle;

sys/dev/ofw/ofw_regulator.h

43

int regulator_enable(uint32_t);

sys/dev/ofw/ofw_regulator.h

44

int regulator_disable(uint32_t);

sys/dev/ofw/ofw_regulator.h

45

uint32_t regulator_get_voltage(uint32_t);

sys/dev/ofw/ofw_regulator.h

46

int regulator_set_voltage(uint32_t, uint32_t);

sys/dev/ofw/ofw_regulator.h

47

uint32_t regulator_get_current(uint32_t);

sys/dev/ofw/ofw_regulator.h

48

int regulator_set_current(uint32_t, uint32_t);

sys/dev/ofw/ofw_regulator.h

51

uint32_t rn_phandle;

sys/dev/ofw/ofw_regulator.h

53

void (*rn_notify)(void *, uint32_t);

sys/dev/ofw/ofw_thermal.c

123

thermal_sensor_update(struct thermal_sensor *ts, uint32_t *cells)

sys/dev/ofw/ofw_thermal.c

130

ts->ts_cells * sizeof(uint32_t)) == 0)

sys/dev/ofw/ofw_thermal.c

147

thermal_get_temperature_cells(uint32_t *cells)

sys/dev/ofw/ofw_thermal.c

150

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_thermal.c

164

thermal_set_limit_cells(uint32_t *cells, uint32_t temp)

sys/dev/ofw/ofw_thermal.c

167

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_thermal.c

188

uint32_t *

sys/dev/ofw/ofw_thermal.c

189

cdev_next_cdev(uint32_t *cells)

sys/dev/ofw/ofw_thermal.c

191

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_thermal.c

202

uint32_t

sys/dev/ofw/ofw_thermal.c

203

cdev_get_level(uint32_t *cells)

sys/dev/ofw/ofw_thermal.c

206

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_thermal.c

220

cdev_set_level(uint32_t *cells, uint32_t level)

sys/dev/ofw/ofw_thermal.c

223

uint32_t phandle = cells[0];

sys/dev/ofw/ofw_thermal.c

239

uint32_t *cdev;

sys/dev/ofw/ofw_thermal.c

260

uint32_t *cdev;

sys/dev/ofw/ofw_thermal.c

305

uint32_t polling_delay;

sys/dev/ofw/ofw_thermal.c

45

uint32_t tp_hysteresis;

sys/dev/ofw/ofw_thermal.c

47

uint32_t tp_phandle;

sys/dev/ofw/ofw_thermal.c

487

cm->cm_cdevend = cm->cm_cdev + len / sizeof(uint32_t);

sys/dev/ofw/ofw_thermal.c

500

uint32_t *cdev;

sys/dev/ofw/ofw_thermal.c

65

uint32_t *cm_cdev;

sys/dev/ofw/ofw_thermal.c

66

uint32_t *cm_cdevend;

sys/dev/ofw/ofw_thermal.c

67

uint32_t cm_trip;

sys/dev/ofw/ofw_thermal.c

71

uint32_t cd_phandle;

sys/dev/ofw/ofw_thermal.c

82

uint32_t *tz_sensors;

sys/dev/ofw/ofw_thermal.c

83

uint32_t tz_polling_delay;

sys/dev/ofw/ofw_thermal.c

84

uint32_t tz_polling_delay_passive;

sys/dev/ofw/ofw_thermal.h

25

int32_t (*ts_get_temperature)(void *, uint32_t *);

sys/dev/ofw/ofw_thermal.h

26

int (*ts_set_limit)(void *, uint32_t *, uint32_t);

sys/dev/ofw/ofw_thermal.h

29

uint32_t ts_phandle;

sys/dev/ofw/ofw_thermal.h

30

uint32_t ts_cells;

sys/dev/ofw/ofw_thermal.h

39

uint32_t (*cd_get_level)(void *, uint32_t *);

sys/dev/ofw/ofw_thermal.h

40

void (*cd_set_level)(void *, uint32_t *, uint32_t);

sys/dev/ofw/ofw_thermal.h

43

uint32_t cd_phandle;

sys/dev/ofw/ofw_thermal.h

44

uint32_t cd_cells;

sys/dev/ofw/ofw_thermal.h

50

void thermal_sensor_update(struct thermal_sensor *, uint32_t *);

sys/dev/ofw/openfirm.h

54

uint32_t OF_getpropint(int handle, char *, uint32_t);

sys/dev/ofw/openfirm.h

55

int OF_getpropintarray(int, char *, uint32_t *, int);

sys/dev/ofw/openfirm.h

78

int OF_getnodebyphandle(uint32_t);

sys/dev/pci/agp_apple.c

178

uint32_t entry;

sys/dev/pci/agp_apple.c

229

agp_apple_enable(void *v, uint32_t mode)

sys/dev/pci/agp_apple.c

52

int agp_apple_enable(void *, uint32_t);

sys/dev/pci/ahc_pci.c

1107

uint32_t devconfig;

sys/dev/pci/ahc_pci.c

1140

uint32_t devconfig;

sys/dev/pci/ahc_pci.c

1301

uint32_t cmd;

sys/dev/pci/ahc_pci.c

1641

uint32_t devconfig;

sys/dev/pci/ahc_pci.c

703

uint32_t devconfig;

sys/dev/pci/ahc_pci.c

953

uint32_t devconfig;

sys/dev/pci/auacer.c

457

uint32_t control;

sys/dev/pci/auacer.c

509

uint32_t val;

sys/dev/pci/auacer.c

511

uint32_t slot;

sys/dev/pci/auacer.c

655

uint32_t sts;

sys/dev/pci/auacer.c

656

uint32_t civ;

sys/dev/pci/auacer.c

713

uint32_t start, uint32_t size, uint32_t blksize, void (*intr)(void *),

sys/dev/pci/auacer.c

716

uint32_t port, slot;

sys/dev/pci/auacer.c

717

uint32_t offs, val;

sys/dev/pci/auacer.c

752

uint32_t size;

sys/dev/pci/auacer.c

79

uint32_t ptr;

sys/dev/pci/auacer.c

80

uint32_t start, p, end;

sys/dev/pci/auacer.c

81

uint32_t blksize, fifoe;

sys/dev/pci/auacer.c

82

uint32_t ack;

sys/dev/pci/auacer.c

83

uint32_t port;

sys/dev/pci/auich.c

195

uint32_t start, p, end;

sys/dev/pci/auich.c

202

uint32_t ap;

sys/dev/pci/auich.c

773

uint32_t sts;

sys/dev/pci/autri.c

190

autri_reg_set_4(struct autri_softc *sc, int no, uint32_t mask)

sys/dev/pci/autri.c

197

autri_reg_clear_4(struct autri_softc *sc, int no, uint32_t mask)

sys/dev/pci/autri.c

89

static __inline void autri_reg_set_4(struct autri_softc *, int, uint32_t);

sys/dev/pci/autri.c

90

static __inline void autri_reg_clear_4(struct autri_softc *, int, uint32_t);

sys/dev/pci/azalia.c

1094

AZ_WRITE_4(az, CORBLBASE, (uint32_t)AZALIA_DMA_DMAADDR(&az->corb_dma));

sys/dev/pci/azalia.c

1179

AZ_WRITE_4(az, RIRBLBASE, (uint32_t)AZALIA_DMA_DMAADDR(&az->rirb_dma));

sys/dev/pci/azalia.c

119

uint32_t intr_bit;

sys/dev/pci/azalia.c

1217

azalia_comresp(const codec_t *codec, nid_t nid, uint32_t control,

sys/dev/pci/azalia.c

1218

uint32_t param, uint32_t* result)

sys/dev/pci/azalia.c

1234

azalia_set_command(azalia_t *az, int caddr, nid_t nid, uint32_t control,

sys/dev/pci/azalia.c

1235

uint32_t param)

sys/dev/pci/azalia.c

1239

uint32_t verb;

sys/dev/pci/azalia.c

1260

azalia_get_response(azalia_t *az, uint32_t *result)

sys/dev/pci/azalia.c

1457

uint32_t result;

sys/dev/pci/azalia.c

153

uint32_t subid;

sys/dev/pci/azalia.c

1532

uint32_t rev, id, result;

sys/dev/pci/azalia.c

179

uint32_t intctl;

sys/dev/pci/azalia.c

210

int azalia_set_command(azalia_t *, nid_t, int, uint32_t, uint32_t);

sys/dev/pci/azalia.c

211

int azalia_get_response(azalia_t *, uint32_t *);

sys/dev/pci/azalia.c

219

void azalia_codec_add_bits(codec_t *, int, uint32_t, int);

sys/dev/pci/azalia.c

220

void azalia_codec_add_format(codec_t *, int, int, uint32_t, int32_t);

sys/dev/pci/azalia.c

2433

uint32_t cap, result;

sys/dev/pci/azalia.c

2660

uint32_t bits_rates;

sys/dev/pci/azalia.c

2775

azalia_codec_add_bits(codec_t *this, int chan, uint32_t bits_rates, int mode)

sys/dev/pci/azalia.c

2790

azalia_codec_add_format(codec_t *this, int chan, int prec, uint32_t rates,

sys/dev/pci/azalia.c

2835

uint32_t digital, stream_chan;

sys/dev/pci/azalia.c

2910

uint32_t v;

sys/dev/pci/azalia.c

2941

uint32_t result;

sys/dev/pci/azalia.c

3249

uint32_t result;

sys/dev/pci/azalia.c

3289

uint32_t result, dir;

sys/dev/pci/azalia.c

3361

uint32_t result;

sys/dev/pci/azalia.c

3515

uint32_t result;

sys/dev/pci/azalia.c

646

uint32_t gctl;

sys/dev/pci/azalia.c

723

uint32_t intsts;

sys/dev/pci/azalia.c

757

uint32_t gctl;

sys/dev/pci/azalia.c

796

uint32_t gctl;

sys/dev/pci/azalia.h

522

uint32_t low;

sys/dev/pci/azalia.h

523

uint32_t high;

sys/dev/pci/azalia.h

524

uint32_t length;

sys/dev/pci/azalia.h

525

uint32_t flags;

sys/dev/pci/azalia.h

531

uint32_t position;

sys/dev/pci/azalia.h

532

uint32_t reserved;

sys/dev/pci/azalia.h

535

typedef uint32_t corb_entry_t;

sys/dev/pci/azalia.h

537

uint32_t resp;

sys/dev/pci/azalia.h

538

uint32_t resp_ex;

sys/dev/pci/azalia.h

558

uint32_t widgetcap;

sys/dev/pci/azalia.h

565

uint32_t inamp_cap;

sys/dev/pci/azalia.h

566

uint32_t outamp_cap;

sys/dev/pci/azalia.h

570

uint32_t encodings;

sys/dev/pci/azalia.h

571

uint32_t bits_rates;

sys/dev/pci/azalia.h

574

uint32_t cap;

sys/dev/pci/azalia.h

575

uint32_t config;

sys/dev/pci/azalia.h

582

uint32_t cap;

sys/dev/pci/azalia.h

652

uint32_t vid; /* codec vendor/device ID */

sys/dev/pci/azalia.h

653

uint32_t subid; /* PCI subvendor/device ID */

sys/dev/pci/azalia.h

731

int azalia_comresp(const codec_t *, nid_t, uint32_t, uint32_t, uint32_t *);

sys/dev/pci/azalia_codec.c

1618

uint32_t result;

sys/dev/pci/azalia_codec.c

1692

uint32_t result, cap, value;

sys/dev/pci/azalia_codec.c

1967

uint32_t result, value;

sys/dev/pci/azalia_codec.c

2416

uint32_t cap;

sys/dev/pci/azalia_codec.c

2497

uint32_t dv)

sys/dev/pci/azalia_codec.c

2499

uint32_t steps;

sys/dev/pci/azalia_codec.c

2522

uint32_t

sys/dev/pci/azalia_codec.c

2526

uint32_t steps;

sys/dev/pci/azalia_codec.c

2551

uint32_t data, mask, dir;

sys/dev/pci/azalia_codec.c

2573

uint32_t cap;

sys/dev/pci/azalia_codec.c

45

struct io_pin *, int, nid_t *, int, uint32_t, uint32_t);

sys/dev/pci/azalia_codec.c

50

u_char azalia_mixer_from_device_value(const codec_t *, nid_t, int, uint32_t );

sys/dev/pci/azalia_codec.c

51

uint32_t azalia_mixer_to_device_value(const codec_t *, nid_t, int, u_char);

sys/dev/pci/azalia_codec.c

617

uint32_t type, uint32_t digital)

sys/dev/pci/azalia_codec.c

736

uint32_t result;

sys/dev/pci/cmpci.c

1761

uint32_t reg_dma_base, reg_dma_bytes, reg_dma_samples, reg_dir,

sys/dev/pci/cmpci.c

1763

uint32_t length;

sys/dev/pci/cmpci.c

205

uint32_t mask, uint32_t val)

sys/dev/pci/cmpci.c

231

cmpci_reg_set_4(struct cmpci_softc *sc, int no, uint32_t mask)

sys/dev/pci/cmpci.c

242

cmpci_reg_clear_4(struct cmpci_softc *sc, int no, uint32_t mask)

sys/dev/pci/cmpci.c

257

cmpci_reg_set_reg_misc(struct cmpci_softc *sc, uint32_t mask)

sys/dev/pci/cmpci.c

266

cmpci_reg_clear_reg_misc(struct cmpci_softc *sc, uint32_t mask)

sys/dev/pci/cmpci.c

525

uint32_t intrstat;

sys/dev/pci/cmpci.c

77

uint32_t, uint32_t);

sys/dev/pci/cmpci.c

80

void cmpci_reg_set_4(struct cmpci_softc *, int, uint32_t);

sys/dev/pci/cmpci.c

81

void cmpci_reg_clear_4(struct cmpci_softc *, int, uint32_t);

sys/dev/pci/cmpci.c

813

uint32_t reg_intr, reg_enable, reg_reset;

sys/dev/pci/cmpci.c

82

void cmpci_reg_set_reg_misc(struct cmpci_softc *, uint32_t);

sys/dev/pci/cmpci.c

83

void cmpci_reg_clear_reg_misc(struct cmpci_softc *, uint32_t);

sys/dev/pci/cmpcivar.h

192

uint32_t sc_id;

sys/dev/pci/cmpcivar.h

193

uint32_t sc_class;

sys/dev/pci/cmpcivar.h

194

uint32_t sc_capable;

sys/dev/pci/cmpcivar.h

246

uint32_t sc_play_channel;

sys/dev/pci/cmpcivar.h

249

uint32_t sc_reg_misc;

sys/dev/pci/cmpcivar.h

252

uint32_t sc_version;

sys/dev/pci/com_pci.c

185

HWRITE4(sc, i * sizeof(uint32_t), sc->sc_priv[i]);

sys/dev/pci/com_pci.c

191

sc->sc_priv[i] = HREAD4(sc, i * sizeof(uint32_t));

sys/dev/pci/com_pci.c

55

uint32_t sc_priv[LPSS_REG_NUM];

sys/dev/pci/com_pci.c

84

uint32_t caps;

sys/dev/pci/drm/amd/amdgpu/aldebaran.c

214

uint32_t ip_block_mask = aldebaran_get_ip_block_mask(adev);

sys/dev/pci/drm/amd/amdgpu/aldebaran.c

74

static inline uint32_t aldebaran_get_ip_block_mask(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/aldebaran.c

76

uint32_t ip_block_mask = BIT(AMD_IP_BLOCK_TYPE_GFX) |

sys/dev/pci/drm/amd/amdgpu/aldebaran.c

87

uint32_t ip_block_mask = aldebaran_get_ip_block_mask(adev);

sys/dev/pci/drm/amd/amdgpu/aldebaran.c

88

uint32_t ip_block;

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

32

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

34

adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

35

adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

36

adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

37

adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

38

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

39

adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

40

adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

41

adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

42

adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

43

adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

44

adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

45

adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(SDMA2_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

46

adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(SDMA3_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

47

adev->reg_offset[SDMA4_HWIP][i] = (uint32_t *)(&(SDMA4_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

48

adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

49

adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

50

adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/aldebaran_reg_init.c

51

adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1020

uint32_t bios_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1021

uint32_t bios_scratch_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1022

uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1226

uint32_t harvest_ip_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1237

uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1283

uint32_t ras_hw_enabled;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1284

uint32_t ras_enabled;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1297

uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1310

uint32_t scpm_status;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1316

uint32_t aid_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1358

static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1367

static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

139

uint32_t num_gpu;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1395

uint32_t flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

140

uint32_t num_dgpu;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1408

uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1409

uint32_t inst, uint32_t reg_addr, char reg_name[],

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

141

uint32_t num_apu;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1410

uint32_t expected_value, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1411

uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1412

uint32_t reg, uint32_t acc_flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1415

uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1416

uint32_t reg, uint32_t acc_flags,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1417

uint32_t xcc_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1419

uint32_t reg, uint32_t v,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1420

uint32_t acc_flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1424

uint32_t reg, uint32_t v,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1425

uint32_t acc_flags,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1426

uint32_t xcc_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1428

uint32_t reg, uint32_t v, uint32_t xcc_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1429

void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1430

uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1507

uint32_t tmp_ = RREG32(reg); \

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1516

uint32_t tmp_ = RREG32_PLL(reg); \

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

161

uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1646

ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

1704

struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

441

uint32_t default_mclk;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

442

uint32_t default_sclk;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

443

uint32_t default_dispclk;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

444

uint32_t dp_extclk;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

445

uint32_t max_pixel_clock;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

516

uint32_t xcp_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

554

uint32_t *wb;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

597

uint32_t reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

730

uint32_t *ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

743

typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

744

typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

746

typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

747

typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

749

typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

750

typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

755

typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

756

typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

820

uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE];

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

824

uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

826

uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

894

uint32_t queue_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

896

uint32_t doorbell_index;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

898

uint32_t hqd_pipe_priority;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

899

uint32_t hqd_queue_priority;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

941

uint32_t hwini_ip_block_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

993

uint32_t family;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

994

uint32_t rev_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu.h

995

uint32_t external_rev_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

73

uint32_t sbdf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_acpi.c

879

static struct amdgpu_numa_info *amdgpu_acpi_get_numa_info(uint32_t pxm)

sys/dev/pci/drm/amd/amdgpu/amdgpu_afmt.c

51

static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq)

sys/dev/pci/drm/amd/amdgpu/amdgpu_afmt.c

88

struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

446

uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

525

uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

537

size_t buffer_size, uint32_t *metadata_size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

538

uint32_t *flags, int8_t *xcp_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

598

uint32_t num_lanes_mask = 1 << num_lanes_shift;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

599

uint32_t gen_speed_mask = 1 << gen_speed_shift;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

649

uint32_t vmid, uint64_t gpu_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

650

uint32_t *ib_cmd, uint32_t ib_len)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

752

pasid_notify pasid_fn, void *data, uint32_t reset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

758

enum amdgpu_ras_block block, uint32_t reset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

764

uint32_t *payload)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

878

int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

887

int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

896

bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c

905

int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

150

uint32_t evicted_bos;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

172

uint32_t vmid, uint64_t gpu_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

173

uint32_t *ib_cmd, uint32_t ib_len);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

204

uint32_t domain,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

232

uint32_t domain,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

248

uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

255

uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

259

size_t buffer_size, uint32_t *metadata_size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

260

uint32_t *flags, int8_t *xcp_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

263

uint32_t *payload);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

266

int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

267

int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

268

int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

270

bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

311

uint64_t *offset, uint32_t flags, bool criu_resume);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

342

enum amdgpu_ras_block block, uint32_t reset);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

346

pasid_notify pasid_fn, void *data, uint32_t reset);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

407

int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

430

int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

432

int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

434

bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

518

static inline int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

528

static inline int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

538

static inline bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

78

uint32_t domain;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

82

uint32_t alloc_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

84

uint32_t invalid;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h

89

uint32_t gem_handle;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

111

uint32_t kgd_aldebaran_set_wave_launch_mode(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

113

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

115

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

123

static uint32_t kgd_gfx_aldebaran_set_address_watch(

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

126

uint32_t watch_address_mask,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

127

uint32_t watch_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

128

uint32_t watch_mode,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

129

uint32_t debug_vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

130

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

132

uint32_t watch_address_high;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

133

uint32_t watch_address_low;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

134

uint32_t watch_address_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

40

uint32_t kgd_aldebaran_enable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

42

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

44

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

54

static uint32_t kgd_aldebaran_disable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

56

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

58

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

68

uint32_t trap_override,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

69

uint32_t *trap_mask_supported)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

89

static uint32_t kgd_aldebaran_set_wave_launch_trap_override(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

90

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

91

uint32_t trap_override,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

92

uint32_t trap_mask_bits,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

93

uint32_t trap_mask_request,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

94

uint32_t *trap_mask_prev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

95

uint32_t kfd_dbg_trap_cntl_prev)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

98

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.h

22

uint32_t kgd_aldebaran_enable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.h

24

uint32_t vmid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.h

25

uint32_t kgd_aldebaran_set_wave_launch_mode(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.h

27

uint32_t vmid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

124

uint32_t __user *wptr, struct mm_struct *mm)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

127

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

129

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

193

uint32_t engine_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

194

uint32_t (**dump)[2], uint32_t *n_regs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

196

uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

198

uint32_t i = 0, reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

227

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

228

uint32_t sdma_rlc_rb_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

246

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

247

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

316

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

348

static uint32_t kgd_arcturus_enable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

350

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

373

static uint32_t kgd_arcturus_disable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

375

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

67

static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

71

uint32_t sdma_engine_reg_base = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

72

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.h

24

uint32_t __user *wptr, struct mm_struct *mm);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.h

26

uint32_t engine_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.h

27

uint32_t (**dump)[2], uint32_t *n_regs);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

129

uint32_t engine_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

130

uint32_t (**dump)[2], uint32_t *n_regs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

132

uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

134

uint32_t i = 0, reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

168

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

169

uint32_t sdma_rlc_rb_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

187

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

188

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

224

u32 pasid, unsigned int vmid, uint32_t xcc_inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

239

uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

285

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

286

uint32_t __user *wptr, uint32_t wptr_shift,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

287

uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

290

uint32_t *mqd_hqd;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

291

uint32_t reg, hqd_base, hqd_end, data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

328

uint32_t queue_size =

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

347

(uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id, queue_id));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

363

static uint32_t kgd_gfx_v9_4_3_disable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

365

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

367

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

378

uint32_t trap_override,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

379

uint32_t *trap_mask_supported)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

400

static uint32_t trap_mask_map_sw_to_hw(uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

402

uint32_t trap_on_start = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START) ? 1 : 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

403

uint32_t trap_on_end = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END) ? 1 : 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

404

uint32_t excp_en = mask & (KFD_DBG_TRAP_MASK_FP_INVALID |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

413

uint32_t ret;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

422

static uint32_t trap_mask_map_hw_to_sw(uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

424

uint32_t ret = REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, EXCP_EN);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

43

static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

436

static uint32_t kgd_gfx_v9_4_3_set_wave_launch_trap_override(

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

438

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

439

uint32_t trap_override,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

440

uint32_t trap_mask_bits,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

441

uint32_t trap_mask_request,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

442

uint32_t *trap_mask_prev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

443

uint32_t kfd_dbg_trap_cntl_prev)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

446

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

461

static uint32_t kgd_gfx_v9_4_3_set_address_watch(

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

464

uint32_t watch_address_mask,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

465

uint32_t watch_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

466

uint32_t watch_mode,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

467

uint32_t debug_vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

468

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

47

uint32_t sdma_engine_reg_base =

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

470

uint32_t watch_address_high;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

471

uint32_t watch_address_low;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

472

uint32_t watch_address_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

506

static uint32_t kgd_gfx_v9_4_3_clear_address_watch(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

507

uint32_t watch_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

51

uint32_t retval = sdma_engine_reg_base +

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

512

static uint32_t kgd_gfx_v9_4_3_hqd_sdma_get_doorbell(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

515

uint32_t reg_offset = get_sdma_rlc_reg_offset(adev, engine, queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

516

uint32_t status = RREG32(regSDMA_RLC0_CONTEXT_STATUS + reg_offset);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

517

uint32_t doorbell_off = RREG32(regSDMA_RLC0_DOORBELL_OFFSET + reg_offset);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

60

uint32_t __user *wptr, struct mm_struct *mm)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

63

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

65

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1017

uint32_t *wait_times,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1018

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1025

uint32_t wait_times,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1026

uint32_t sch_wave,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1027

uint32_t que_sleep,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1028

uint32_t *reg_offset,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1029

uint32_t *reg_data)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1048

uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1049

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

105

uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1074

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1075

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1081

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1082

uint32_t inst, unsigned int utimeout)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1087

uint32_t kgd_gfx_v10_hqd_sdma_get_doorbell(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

140

static int kgd_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

141

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

143

uint32_t mec;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

144

uint32_t pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

160

static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

164

uint32_t sdma_engine_reg_base[2] = {

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

177

uint32_t retval = sdma_engine_reg_base[engine_id]

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

187

static uint32_t get_watch_base_addr(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

189

uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) -

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

209

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

210

uint32_t __user *wptr, uint32_t wptr_shift,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

211

uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

214

uint32_t *mqd_hqd;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

215

uint32_t reg, hqd_base, data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

253

uint32_t queue_size =

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

272

(uint32_t)get_queue_mask(adev, pipe_id, queue_id));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

274

(uint32_t)get_queue_mask(adev, pipe_id, queue_id));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

291

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

292

uint32_t doorbell_off, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

296

uint32_t mec, pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

343

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

344

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

346

uint32_t i = 0, reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

374

uint32_t __user *wptr, struct mm_struct *mm)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

377

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

379

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

44

static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

443

uint32_t engine_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

444

uint32_t (**dump)[2], uint32_t *n_regs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

446

uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

448

uint32_t i = 0, reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

45

uint32_t queue, uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

474

uint64_t queue_address, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

475

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

477

uint32_t act;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

479

uint32_t low, high;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

498

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

499

uint32_t sdma_rlc_rb_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

515

unsigned int utimeout, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

516

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

520

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

57

static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

58

uint32_t queue_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

60

uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

61

uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

630

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

631

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

668

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

67

uint32_t pipe_id, uint32_t queue_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

678

uint32_t gfx_index_val,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

679

uint32_t sq_cmd, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

681

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

702

uint32_t vmid, uint64_t page_table_base)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

736

static void kgd_gfx_v10_set_wave_launch_stall(struct amdgpu_device *adev, uint32_t vmid, bool stall)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

738

uint32_t data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

753

uint32_t kgd_gfx_v10_enable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

755

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

764

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

790

uint32_t kgd_gfx_v10_disable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

792

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

80

static void kgd_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

808

uint32_t trap_override,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

809

uint32_t *trap_mask_supported)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

81

uint32_t sh_mem_config,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

82

uint32_t sh_mem_ape1_base,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

825

uint32_t kgd_gfx_v10_set_wave_launch_trap_override(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

826

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

827

uint32_t trap_override,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

828

uint32_t trap_mask_bits,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

829

uint32_t trap_mask_request,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

83

uint32_t sh_mem_ape1_limit,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

830

uint32_t *trap_mask_prev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

831

uint32_t kfd_dbg_trap_cntl_prev)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

833

uint32_t data, wave_cntl_prev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

84

uint32_t sh_mem_bases, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

859

uint32_t kgd_gfx_v10_set_wave_launch_mode(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

861

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

863

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

885

uint32_t kgd_gfx_v10_set_address_watch(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

887

uint32_t watch_address_mask,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

888

uint32_t watch_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

889

uint32_t watch_mode,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

890

uint32_t debug_vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

891

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

896

uint32_t watch_address_high;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

897

uint32_t watch_address_low;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

898

uint32_t tcp_watch_address_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

899

uint32_t sq_watch_address_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

96

unsigned int vmid, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

984

uint32_t kgd_gfx_v10_clear_address_watch(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

985

uint32_t watch_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

987

uint32_t watch_address_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

23

uint32_t kgd_gfx_v10_enable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

25

uint32_t vmid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

26

uint32_t kgd_gfx_v10_disable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

28

uint32_t vmid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

30

uint32_t trap_override,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

31

uint32_t *trap_mask_supported);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

32

uint32_t kgd_gfx_v10_set_wave_launch_trap_override(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

33

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

34

uint32_t trap_override,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

35

uint32_t trap_mask_bits,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

36

uint32_t trap_mask_request,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

37

uint32_t *trap_mask_prev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

38

uint32_t kfd_dbg_trap_cntl_prev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

39

uint32_t kgd_gfx_v10_set_wave_launch_mode(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

41

uint32_t vmid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

42

uint32_t kgd_gfx_v10_set_address_watch(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

44

uint32_t watch_address_mask,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

45

uint32_t watch_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

46

uint32_t watch_mode,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

47

uint32_t debug_vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

48

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

49

uint32_t kgd_gfx_v10_clear_address_watch(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

50

uint32_t watch_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

52

uint32_t *wait_times,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

53

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

55

uint32_t wait_times,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

56

uint32_t sch_wave,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

57

uint32_t que_sleep,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

58

uint32_t *reg_offset,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

59

uint32_t *reg_data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

61

uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

62

uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

63

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

65

uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

66

uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

67

uint32_t inst,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h

69

uint32_t kgd_gfx_v10_hqd_sdma_get_doorbell(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

109

static int init_interrupts_v10_3(struct amdgpu_device *adev, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

110

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

112

uint32_t mec;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

113

uint32_t pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

129

static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

133

uint32_t sdma_engine_reg_base = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

134

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

180

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

181

uint32_t __user *wptr, uint32_t wptr_shift,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

182

uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

185

uint32_t *mqd_hqd;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

186

uint32_t reg, hqd_base, data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

195

uint32_t value, mec, pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

239

uint32_t queue_size =

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

258

(uint32_t)get_queue_mask(adev, pipe_id, queue_id));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

260

(uint32_t)get_queue_mask(adev, pipe_id, queue_id));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

277

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

278

uint32_t doorbell_off, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

282

uint32_t mec, pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

329

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

330

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

332

uint32_t i = 0, reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

360

uint32_t __user *wptr, struct mm_struct *mm)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

363

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

365

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

429

uint32_t engine_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

430

uint32_t (**dump)[2], uint32_t *n_regs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

432

uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

434

uint32_t i = 0, reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

44

static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

45

uint32_t queue, uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

460

uint64_t queue_address, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

461

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

463

uint32_t act;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

465

uint32_t low, high;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

485

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

486

uint32_t sdma_rlc_rb_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

502

unsigned int utimeout, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

503

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

507

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

554

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

555

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

57

static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

58

uint32_t queue_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

590

uint32_t gfx_index_val,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

591

uint32_t sq_cmd, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

593

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

60

uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

61

uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

616

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

626

uint32_t vmid, uint64_t page_table_base)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

633

uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

634

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

67

uint32_t pipe_id, uint32_t queue_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

80

static void program_sh_mem_settings_v10_3(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

81

uint32_t sh_mem_config,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

82

uint32_t sh_mem_ape1_base,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

83

uint32_t sh_mem_ape1_limit,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

84

uint32_t sh_mem_bases, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

97

unsigned int vmid, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

99

uint32_t value = pasid << IH_VMID_0_LUT__PASID__SHIFT;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

105

static int init_interrupts_v11(struct amdgpu_device *adev, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

106

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

108

uint32_t mec;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

109

uint32_t pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

125

static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

129

uint32_t sdma_engine_reg_base = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

130

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

164

static int hqd_load_v11(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

165

uint32_t queue_id, uint32_t __user *wptr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

166

uint32_t wptr_shift, uint32_t wptr_mask,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

167

struct mm_struct *mm, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

170

uint32_t *mqd_hqd;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

171

uint32_t reg, hqd_base, data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

180

uint32_t value, mec, pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

224

uint32_t queue_size =

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

243

(uint32_t)get_queue_mask(adev, pipe_id, queue_id));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

245

(uint32_t)get_queue_mask(adev, pipe_id, queue_id));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

262

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

263

uint32_t doorbell_off, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

267

uint32_t mec, pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

314

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

315

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

317

uint32_t i = 0, reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

345

uint32_t __user *wptr, struct mm_struct *mm)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

348

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

350

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

414

uint32_t engine_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

415

uint32_t (**dump)[2], uint32_t *n_regs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

417

uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

419

uint32_t i = 0, reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

42

static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

43

uint32_t queue, uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

450

uint32_t pipe_id, uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

452

uint32_t act;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

454

uint32_t low, high;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

473

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

474

uint32_t sdma_rlc_rb_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

490

unsigned int utimeout, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

491

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

495

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

539

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

540

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

55

static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

56

uint32_t queue_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

575

uint32_t gfx_index_val,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

576

uint32_t sq_cmd, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

578

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

58

uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

59

uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

599

uint32_t vmid, uint64_t page_table_base)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

620

static uint32_t kgd_gfx_v11_enable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

622

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

624

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

634

static uint32_t kgd_gfx_v11_disable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

636

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

638

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

648

uint32_t trap_override,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

649

uint32_t *trap_mask_supported)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

65

uint32_t pipe_id, uint32_t queue_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

672

static uint32_t trap_mask_map_sw_to_hw(uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

674

uint32_t trap_on_start = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START) ? 1 : 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

675

uint32_t trap_on_end = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END) ? 1 : 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

676

uint32_t excp_en = mask & (KFD_DBG_TRAP_MASK_FP_INVALID |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

685

uint32_t ret;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

694

static uint32_t trap_mask_map_hw_to_sw(uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

696

uint32_t ret = REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, EXCP_EN);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

708

static uint32_t kgd_gfx_v11_set_wave_launch_trap_override(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

709

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

710

uint32_t trap_override,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

711

uint32_t trap_mask_bits,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

712

uint32_t trap_mask_request,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

713

uint32_t *trap_mask_prev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

714

uint32_t kfd_dbg_trap_cntl_prev)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

716

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

729

static uint32_t kgd_gfx_v11_set_wave_launch_mode(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

731

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

733

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

741

static uint32_t kgd_gfx_v11_set_address_watch(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

743

uint32_t watch_address_mask,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

744

uint32_t watch_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

745

uint32_t watch_mode,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

746

uint32_t debug_vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

747

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

749

uint32_t watch_address_high;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

750

uint32_t watch_address_low;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

751

uint32_t watch_address_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

78

static void program_sh_mem_settings_v11(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

783

static uint32_t kgd_gfx_v11_clear_address_watch(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

784

uint32_t watch_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

79

uint32_t sh_mem_config,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

790

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

791

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

797

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

798

uint32_t inst, unsigned int utimeout)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

80

uint32_t sh_mem_ape1_base,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

803

static uint32_t kgd_gfx_v11_hqd_sdma_get_doorbell(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

81

uint32_t sh_mem_ape1_limit,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

82

uint32_t sh_mem_bases, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

93

unsigned int vmid, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

95

uint32_t value = pasid << IH_VMID_0_LUT__PASID__SHIFT;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

106

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

107

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

109

uint32_t i = 0, reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

137

uint32_t engine_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

138

uint32_t (**dump)[2], uint32_t *n_regs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

140

uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

142

uint32_t i = 0, reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

144

const uint32_t first_reg = regSDMA0_QUEUE0_RB_CNTL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

145

const uint32_t last_reg = regSDMA0_QUEUE0_CONTEXT_STATUS;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

164

uint32_t gfx_index_val,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

165

uint32_t sq_cmd, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

167

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

188

static uint32_t kgd_gfx_v12_enable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

190

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

192

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

202

static uint32_t kgd_gfx_v12_disable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

204

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

206

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

216

uint32_t trap_override,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

217

uint32_t *trap_mask_supported)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

239

static uint32_t trap_mask_map_sw_to_hw(uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

241

uint32_t trap_on_start = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START) ? 1 : 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

242

uint32_t trap_on_end = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END) ? 1 : 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

243

uint32_t excp_en = mask & (KFD_DBG_TRAP_MASK_FP_INVALID |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

252

uint32_t ret;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

261

static uint32_t trap_mask_map_hw_to_sw(uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

263

uint32_t ret = REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, EXCP_EN);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

275

static uint32_t kgd_gfx_v12_set_wave_launch_trap_override(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

276

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

277

uint32_t trap_override,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

278

uint32_t trap_mask_bits,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

279

uint32_t trap_mask_request,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

280

uint32_t *trap_mask_prev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

281

uint32_t kfd_dbg_trap_cntl_prev)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

284

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

298

static uint32_t kgd_gfx_v12_set_wave_launch_mode(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

30

static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

300

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

302

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

31

uint32_t queue, uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

316

static uint32_t kgd_gfx_v12_set_address_watch(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

318

uint32_t watch_address_mask,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

319

uint32_t watch_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

320

uint32_t watch_mode,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

321

uint32_t debug_vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

322

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

324

uint32_t watch_address_high;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

325

uint32_t watch_address_low;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

326

uint32_t watch_address_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

358

static uint32_t kgd_gfx_v12_clear_address_watch(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

359

uint32_t watch_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

364

static uint32_t kgd_gfx_v12_hqd_sdma_get_doorbell(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

43

static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

44

uint32_t queue_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

46

uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

47

uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

57

static int init_interrupts_v12(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

59

uint32_t mec;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

60

uint32_t pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

76

static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

80

uint32_t sdma_engine_reg_base = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

81

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

102

uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

117

static int kgd_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

118

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

120

uint32_t mec;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

121

uint32_t pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

136

static inline uint32_t get_sdma_rlc_reg_offset(struct cik_sdma_rlc_registers *m)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

138

uint32_t retval;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

160

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

161

uint32_t __user *wptr, uint32_t wptr_shift,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

162

uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

165

uint32_t *mqd_hqd;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

166

uint32_t reg, wptr_val, data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

205

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

206

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

208

uint32_t i = 0, reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

240

uint32_t __user *wptr, struct mm_struct *mm)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

244

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

245

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

295

uint32_t engine_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

296

uint32_t (**dump)[2], uint32_t *n_regs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

298

uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

300

uint32_t i = 0, reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

321

uint64_t queue_address, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

322

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

324

uint32_t act;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

326

uint32_t low, high;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

345

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

346

uint32_t sdma_rlc_rb_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

361

unsigned int utimeout, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

362

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

364

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

464

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

465

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

48

static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

49

uint32_t queue, uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

497

uint32_t gfx_index_val,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

498

uint32_t sq_cmd, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

500

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

51

uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

523

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

532

uint64_t va, uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

540

uint32_t vmid, uint64_t page_table_base)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

557

static uint32_t read_vmid_from_vmfault_reg(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

559

uint32_t status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

564

static uint32_t kgd_hqd_sdma_get_doorbell(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

63

static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

64

uint32_t queue_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

66

uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

67

uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

77

static void kgd_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

78

uint32_t sh_mem_config,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

79

uint32_t sh_mem_ape1_base,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

80

uint32_t sh_mem_ape1_limit,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

81

uint32_t sh_mem_bases, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

94

unsigned int vmid, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

112

static int kgd_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

113

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

115

uint32_t mec;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

116

uint32_t pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

131

static inline uint32_t get_sdma_rlc_reg_offset(struct vi_sdma_mqd *m)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

133

uint32_t retval;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

155

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

156

uint32_t __user *wptr, uint32_t wptr_shift,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

157

uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

160

uint32_t *mqd_hqd;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

161

uint32_t reg, wptr_val, data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

170

uint32_t value, mec, pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

229

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

230

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

232

uint32_t i = 0, reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

264

uint32_t __user *wptr, struct mm_struct *mm)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

268

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

269

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

318

uint32_t engine_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

319

uint32_t (**dump)[2], uint32_t *n_regs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

321

uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

323

uint32_t i = 0, reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

353

uint64_t queue_address, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

354

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

356

uint32_t act;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

358

uint32_t low, high;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

377

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

378

uint32_t sdma_rlc_rb_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

393

unsigned int utimeout, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

394

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

396

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

42

static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

43

uint32_t queue, uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

45

uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

499

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

500

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

534

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

543

uint32_t gfx_index_val,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

544

uint32_t sq_cmd, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

546

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

567

uint64_t va, uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

57

static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

575

uint32_t vmid, uint64_t page_table_base)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

58

uint32_t queue_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

585

static uint32_t kgd_hqd_sdma_get_doorbell(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

60

uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

61

uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

71

static void kgd_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

72

uint32_t sh_mem_config,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

73

uint32_t sh_mem_ape1_base,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

74

uint32_t sh_mem_ape1_limit,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

75

uint32_t sh_mem_bases, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

88

unsigned int vmid, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

97

uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

102

unsigned int vmid, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1024

int *max_waves_per_cu, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1081

uint32_t wait_times,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1082

uint32_t sch_wave,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1083

uint32_t que_sleep,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1084

uint32_t *reg_offset,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1085

uint32_t *reg_data)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1104

uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

111

uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1128

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1129

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1131

uint32_t low, high;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1157

static int kgd_gfx_v9_hqd_dequeue_wait(struct amdgpu_device *adev, uint32_t inst,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1163

uint32_t temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1176

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1177

uint32_t inst, unsigned int utimeout)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1179

uint32_t low, high, pipe_reset_data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1226

uint32_t kgd_gfx_v9_hqd_sdma_get_doorbell(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

160

int kgd_gfx_v9_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

161

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

163

uint32_t mec;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

164

uint32_t pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

180

static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

184

uint32_t sdma_engine_reg_base = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

185

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

223

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

224

uint32_t __user *wptr, uint32_t wptr_shift,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

225

uint32_t wptr_mask, struct mm_struct *mm,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

226

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

229

uint32_t *mqd_hqd;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

230

uint32_t reg, hqd_base, data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

267

uint32_t queue_size =

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

286

(uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id, queue_id));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

302

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

303

uint32_t doorbell_off, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

307

uint32_t mec, pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

354

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

355

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

357

uint32_t i = 0, reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

385

uint32_t __user *wptr, struct mm_struct *mm)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

388

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

390

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

454

uint32_t engine_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

455

uint32_t (**dump)[2], uint32_t *n_regs)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

457

uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

459

uint32_t i = 0, reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

485

uint64_t queue_address, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

486

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

488

uint32_t act;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

490

uint32_t low, high;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

50

static void kgd_gfx_v9_lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

509

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

51

uint32_t queue, uint32_t vmid, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

510

uint32_t sdma_rlc_rb_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

526

unsigned int utimeout, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

527

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

531

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

57

static void kgd_gfx_v9_unlock_srbm(struct amdgpu_device *adev, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

580

uint32_t sdma_rlc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

581

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

618

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

628

uint32_t gfx_index_val,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

629

uint32_t sq_cmd, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

63

void kgd_gfx_v9_acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

631

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

64

uint32_t queue_id, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

66

uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

67

uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

672

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

676

uint32_t data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

701

uint32_t kgd_gfx_v9_enable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

703

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

724

uint32_t kgd_gfx_v9_disable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

726

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

73

uint32_t pipe_id, uint32_t queue_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

742

uint32_t trap_override,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

743

uint32_t *trap_mask_supported)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

759

uint32_t kgd_gfx_v9_set_wave_launch_trap_override(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

760

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

761

uint32_t trap_override,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

762

uint32_t trap_mask_bits,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

763

uint32_t trap_mask_request,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

764

uint32_t *trap_mask_prev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

765

uint32_t kfd_dbg_cntl_prev)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

767

uint32_t data, wave_cntl_prev;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

793

uint32_t kgd_gfx_v9_set_wave_launch_mode(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

795

uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

797

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

81

void kgd_gfx_v9_release_queue(struct amdgpu_device *adev, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

818

uint32_t kgd_gfx_v9_set_address_watch(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

820

uint32_t watch_address_mask,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

821

uint32_t watch_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

822

uint32_t watch_mode,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

823

uint32_t debug_vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

824

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

826

uint32_t watch_address_high;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

827

uint32_t watch_address_low;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

828

uint32_t watch_address_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

86

void kgd_gfx_v9_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

87

uint32_t sh_mem_config,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

879

uint32_t kgd_gfx_v9_clear_address_watch(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

88

uint32_t sh_mem_ape1_base,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

880

uint32_t watch_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

882

uint32_t watch_address_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

89

uint32_t sh_mem_ape1_limit,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

90

uint32_t sh_mem_bases, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

905

uint32_t *wait_times,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

906

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

914

uint32_t vmid, uint64_t page_table_base)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

951

struct kfd_cu_occupancy *queue_cnt, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

101

uint32_t wait_times,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

102

uint32_t sch_wave,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

103

uint32_t que_sleep,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

104

uint32_t *reg_offset,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

105

uint32_t *reg_data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

107

uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

108

uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

109

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

111

uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

112

uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

113

uint32_t inst,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

115

uint32_t kgd_gfx_v9_hqd_sdma_get_doorbell(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

23

void kgd_gfx_v9_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

24

uint32_t sh_mem_config,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

25

uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

26

uint32_t sh_mem_bases, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

28

unsigned int vmid, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

29

int kgd_gfx_v9_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

30

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

31

int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

32

uint32_t queue_id, uint32_t __user *wptr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

33

uint32_t wptr_shift, uint32_t wptr_mask,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

34

struct mm_struct *mm, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

36

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

37

uint32_t doorbell_off, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

39

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

40

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

42

uint64_t queue_address, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

43

uint32_t queue_id, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

46

unsigned int utimeout, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

47

uint32_t queue_id, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

49

uint32_t gfx_index_val,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

50

uint32_t sq_cmd, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

54

uint32_t vmid, uint64_t page_table_base);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

57

int *max_waves_per_cu, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

59

uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

60

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

61

void kgd_gfx_v9_acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

62

uint32_t queue_id, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

64

uint32_t pipe_id, uint32_t queue_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

65

void kgd_gfx_v9_release_queue(struct amdgpu_device *adev, uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

67

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

69

uint32_t kgd_gfx_v9_enable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

71

uint32_t vmid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

72

uint32_t kgd_gfx_v9_disable_debug_trap(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

74

uint32_t vmid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

76

uint32_t trap_override,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

77

uint32_t *trap_mask_supported);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

78

uint32_t kgd_gfx_v9_set_wave_launch_mode(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

80

uint32_t vmid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

81

uint32_t kgd_gfx_v9_set_wave_launch_trap_override(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

82

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

83

uint32_t trap_override,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

84

uint32_t trap_mask_bits,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

85

uint32_t trap_mask_request,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

86

uint32_t *trap_mask_prev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

87

uint32_t kfd_dbg_trap_cntl_prev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

88

uint32_t kgd_gfx_v9_set_address_watch(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

90

uint32_t watch_address_mask,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

91

uint32_t watch_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

92

uint32_t watch_mode,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

93

uint32_t debug_vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

94

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

95

uint32_t kgd_gfx_v9_clear_address_watch(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

96

uint32_t watch_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

98

uint32_t *wait_times,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

99

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

1694

uint64_t *offset, uint32_t flags, bool criu_resume)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

2005

uint32_t domain;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

2426

uint32_t handle;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

2528

uint32_t invalid;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

2789

uint32_t evicted_bos;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

2946

uint32_t domain = mem->domain;

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

417

static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

444

uint32_t domain,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

516

uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE |

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

541

static struct sg_table *create_sg_table(uint64_t addr, uint32_t size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1041

index, (uint32_t *)&args, sizeof(args)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1063

index, (uint32_t *)&args, sizeof(args)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1083

index, (uint32_t *)&args, sizeof(args)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1096

index, (uint32_t *)&args, sizeof(args)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1140

index, (uint32_t *)&args, sizeof(args)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1184

(uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1239

index, (uint32_t *)&args, sizeof(args)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1250

index, (uint32_t *)&args, sizeof(args)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1560

uint32_t bios_6_scratch;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1577

uint32_t bios_2_scratch, bios_6_scratch;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1684

if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1685

(uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1726

static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1740

static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1754

static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1768

static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1782

static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1798

static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1801

uint32_t r;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1940

uint32_t table,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.h

210

uint32_t table,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

1006

return amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, (uint32_t *)&asic_init_ps_v2_1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

47

uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.c

959

uint32_t bootup_sclk_in10khz, bootup_mclk_in10khz;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atomfirmware.h

29

uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_bo_list.c

192

const uint32_t info_size = sizeof(struct drm_amdgpu_bo_list_entry);

sys/dev/pci/drm/amd/amdgpu/amdgpu_bo_list.c

194

const uint32_t bo_info_size = in->bo_info_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bo_list.c

195

const uint32_t bo_number = in->bo_number;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bo_list.c

207

const uint32_t bytes = min(bo_info_size, info_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_bo_list.c

233

uint32_t handle = args->in.list_handle;

sys/dev/pci/drm/amd/amdgpu/amdgpu_bo_list.h

40

uint32_t priority;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c

112

static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c

210

uint32_t data_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c

246

uint32_t ucode_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c

247

uint32_t ucode_start_address;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c

44

static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned int offset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c

51

uint32_t value)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c

57

static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,

sys/dev/pci/drm/amd/amdgpu/amdgpu_cgs.c

87

unsigned int index, uint32_t value)

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1600

uint32_t connector_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1601

uint32_t supported_device,

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.c

1616

uint32_t subpixel_order = SubPixelNone;

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.h

33

uint32_t connector_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_connectors.h

34

uint32_t supported_device,

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

124

uint32_t section_length,

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

125

uint32_t section_offset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

151

uint32_t idx,

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

180

uint32_t idx,

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

182

uint32_t *reg_dump,

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

183

uint32_t reg_count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

211

memcpy(section->ctx.reg_dump, reg_dump, reg_count * sizeof(uint32_t));

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

221

uint32_t idx)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

228

uint32_t socket_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

279

uint32_t size = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

38

static void __inc_entry_length(struct cper_hdr *hdr, uint32_t size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

392

uint32_t reg_data[CPER_ACA_REG_COUNT] = { 0 };

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c

395

uint32_t i = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.h

60

uint32_t count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.h

61

uint32_t max_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.h

63

uint32_t wptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.h

76

uint32_t idx,

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.h

80

uint32_t idx,

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.h

82

uint32_t *reg_dump,

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.h

83

uint32_t reg_count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.h

86

uint32_t section_idx);

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

1068

ib->ptr = (uint32_t *)kptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

128

uint32_t *offset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

1637

uint32_t fence_count = wait->in.fence_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

1683

uint32_t fence_count = wait->in.fence_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

1684

uint32_t first = ~0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

183

uint32_t uf_offset = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

220

sizeof(uint32_t));

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

226

size *= sizeof(uint32_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

457

uint32_t handle, u64 point,

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.c

809

uint32_t domain;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.h

38

uint32_t chunk_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_cs.h

39

uint32_t length_dw;

sys/dev/pci/drm/amd/amdgpu/amdgpu_csa.c

39

u32 domain, uint32_t size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_csa.c

67

uint64_t csa_addr, uint32_t size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_csa.h

30

uint32_t amdgpu_get_total_csa_size(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_csa.h

33

u32 domain, uint32_t size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_csa.h

36

uint64_t csa_addr, uint32_t size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

194

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

477

uint32_t *id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

495

*id = (uint32_t)r;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

524

static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

538

struct amdgpu_fpriv *fpriv, uint32_t id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

576

struct amdgpu_fpriv *fpriv, uint32_t id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

638

struct amdgpu_fpriv *fpriv, uint32_t id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

669

uint32_t id, stable_pstate;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

730

struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

900

uint32_t id, i, j;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

926

uint32_t id, i, j;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.c

963

uint32_t id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.h

39

uint32_t hw_ip;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.h

59

uint32_t stable_pstate;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ctx.h

73

struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1061

uint32_t offset, se, sh, cu, wave, simd, data[32];

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1106

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1109

r = put_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1153

uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1199

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1202

r = put_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1251

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1257

r = put_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1304

r = get_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1401

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1403

r = get_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

149

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

153

r = put_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

155

r = get_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1818

uint32_t sync_seq, last_seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1876

uint32_t preempt_seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

1990

uint32_t max_freq, min_freq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

2012

ret = amdgpu_dpm_set_soft_freq_range(adev, PP_SCLK, (uint32_t)val, (uint32_t)val);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

236

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

282

r = put_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

284

r = get_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

403

uint32_t *data, x;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

458

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

461

r = put_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

541

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

548

r = put_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

601

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

603

r = get_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

664

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

667

r = put_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

723

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

725

r = get_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

783

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

786

r = put_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

842

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

844

r = get_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

884

uint32_t *config, no_regs = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

942

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

945

r = put_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c

979

uint32_t values[16];

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

76

uint32_t version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_dev_coredump.c

77

uint32_t feature;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1292

static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1299

static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1316

static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1324

static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1342

static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1367

static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1394

static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1395

uint32_t block, uint32_t reg)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1416

uint32_t block,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1417

uint32_t reg, uint32_t v)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1425

static uint32_t amdgpu_device_get_vbios_flags(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1445

uint32_t flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1610

r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1623

memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1788

uint32_t reg, flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1807

uint32_t fw_ver;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

1814

fw_ver = *((uint32_t *)adev->pm.fw->data + 69);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

2807

uint32_t bios_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

3052

uint32_t smu_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4475

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4654

(uint32_t)adev->rmmio_base);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

4865

uint32_t version = adev->ip_versions[GC_HWIP][0];

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

581

uint32_t hi = ~0, tmp = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

582

uint32_t *data = buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

595

WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

727

uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

728

uint32_t reg, uint32_t acc_flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

730

uint32_t ret;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

766

uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7795

uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7796

uint32_t inst, uint32_t reg_addr, char reg_name[],

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7797

uint32_t expected_value, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7799

uint32_t ret = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7800

uint32_t old_ = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7801

uint32_t tmp_ = RREG32(reg_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7802

uint32_t loop = adev->usec_timeout;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7816

inst, reg_name, (uint32_t)expected_value,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7817

(uint32_t)(tmp_ & (mask)));

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

7842

ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

787

uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

788

uint32_t reg, uint32_t acc_flags,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

789

uint32_t xcc_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

791

uint32_t ret, rlcg_flag;

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

834

void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

856

uint32_t reg, uint32_t v,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

857

uint32_t acc_flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

889

uint32_t reg, uint32_t v,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

890

uint32_t xcc_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

919

uint32_t reg, uint32_t v,

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

920

uint32_t acc_flags, uint32_t xcc_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

922

uint32_t rlcg_flag;

sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h

53

uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);

sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h

54

void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,

sys/dev/pci/drm/amd/amdgpu/amdgpu_df.h

55

uint32_t ficadl_val, uint32_t ficadh_val);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1349

uint32_t wafl_ver;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1841

uint32_t *nps_type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

307

amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

343

static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

354

static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

651

uint32_t *vcn_harvest_count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

715

uint32_t *vcn_harvest_count,

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

716

uint32_t *umc_harvest_count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

722

uint32_t umc_harvest_config = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.h

34

uint32_t *nps_type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1307

uint32_t domains;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1811

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

1817

WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t) cursor.start) | 0x80000000);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

194

uint32_t page_flip_flags, uint32_t target,

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

265

work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

416

uint32_t devices;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

559

uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

562

uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

688

uint32_t metadata[10]; /* Something that fits a descriptor + header. */

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

689

uint32_t size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

773

uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

906

uint32_t dcc_block_bits; /* of base surface data */

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.h

42

uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

362

uint32_t amdgpu_doorbell_index_on_bar(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

364

uint32_t doorbell_index,

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

365

uint32_t db_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

42

uint32_t *cpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

52

uint32_t kiq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

53

uint32_t mec_ring0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

54

uint32_t mec_ring1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

55

uint32_t mec_ring2;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

56

uint32_t mec_ring3;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

57

uint32_t mec_ring4;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

58

uint32_t mec_ring5;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

59

uint32_t mec_ring6;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

60

uint32_t mec_ring7;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

61

uint32_t userqueue_start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

62

uint32_t userqueue_end;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

63

uint32_t gfx_ring0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

64

uint32_t gfx_ring1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

65

uint32_t gfx_userqueue_start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

66

uint32_t gfx_userqueue_end;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

67

uint32_t sdma_engine[16];

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

68

uint32_t mes_ring0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

69

uint32_t mes_ring1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

70

uint32_t ih;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

73

uint32_t vcn_ring0_1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

74

uint32_t vcn_ring2_3;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

75

uint32_t vcn_ring4_5;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

76

uint32_t vcn_ring6_7;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

79

uint32_t uvd_ring0_1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

80

uint32_t uvd_ring2_3;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

81

uint32_t uvd_ring4_5;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

82

uint32_t uvd_ring6_7;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

83

uint32_t vce_ring0_1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

84

uint32_t vce_ring2_3;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

85

uint32_t vce_ring4_5;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

86

uint32_t vce_ring6_7;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

89

uint32_t vpe_ring;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

90

uint32_t first_non_cp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

91

uint32_t last_non_cp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

92

uint32_t max_assignment;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

94

uint32_t sdma_doorbell_range;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell.h

96

uint32_t xcc_doorbell_range;

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell_mgr.c

125

uint32_t amdgpu_doorbell_index_on_bar(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell_mgr.c

127

uint32_t doorbell_index,

sys/dev/pci/drm/amd/amdgpu/amdgpu_doorbell_mgr.c

128

uint32_t db_size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

3589

void **, int *, int *, uint32_t *);

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

3689

void **cookiep, int *curxp, int *curyp, uint32_t *attrp)

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

3909

uint32_t defattr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fdinfo.h

39

uint32_t amdgpu_get_ip_count(struct amdgpu_device *adev, int id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

115

uint32_t seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

186

int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

187

uint32_t timeout)

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

189

uint32_t seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

238

uint32_t seq, last_seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

345

uint32_t wait_seq,

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

388

uint32_t last_seq, sync_seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c

415

void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq, ktime_t timestamp)

sys/dev/pci/drm/amd/amdgpu/amdgpu_fw_attestation.c

101

(uint32_t *)&fw_att_record,

sys/dev/pci/drm/amd/amdgpu/amdgpu_fw_attestation.c

39

uint32_t AttDbVersion; /* version of the fwar feature */

sys/dev/pci/drm/amd/amdgpu/amdgpu_fw_attestation.c

40

uint32_t AttDbCookie; /* cookie as an extra check for corrupt data */

sys/dev/pci/drm/amd/amdgpu/amdgpu_fw_attestation.c

46

uint32_t AttFWVersion; /* FW Version */

sys/dev/pci/drm/amd/amdgpu/amdgpu_fw_attestation.c

50

uint32_t AttFwTaId; /* Ta ID (only in TA Attestation Table) */

sys/dev/pci/drm/amd/amdgpu/amdgpu_fw_attestation.c

87

(uint32_t *)&fw_att_hdr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gds.h

31

uint32_t gds_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gds.h

32

uint32_t gws_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gds.h

33

uint32_t oa_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gds.h

34

uint32_t gds_compute_max_wave_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gds.h

38

uint32_t mem_base;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gds.h

39

uint32_t mem_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gds.h

40

uint32_t gws;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gds.h

41

uint32_t oa;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

1358

uint32_t handle;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

51

uint32_t num_syncobj_handles)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

518

uint32_t handle, initial_domain;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

54

uint32_t *syncobj_handles;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

61

size_mul(sizeof(uint32_t), num_syncobj_handles));

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

614

uint32_t handle;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

689

uint32_t handle, uint64_t *offset_p)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

713

uint32_t handle = args->in.handle;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

753

uint32_t handle = args->in.handle;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

841

uint32_t operation)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

89

uint32_t syncobj_handle,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

922

const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.c

926

const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |

sys/dev/pci/drm/amd/amdgpu/amdgpu_gem.h

54

uint32_t handle, uint64_t *offset_p);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1048

uint32_t xcc_mask = GENMASK(num_xcc - 1, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1060

uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1064

uint32_t seq, reg_val_offs = 0, value = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1134

void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1138

uint32_t seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

1212

uint32_t ucode_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c

910

int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

143

uint16_t pasid, uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

146

uint32_t queue_type, uint32_t me_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

147

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

148

uint32_t xcc_id, uint32_t vmid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

189

uint32_t rb_backend_disable;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

197

uint32_t user_rb_backend_disable;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

205

uint32_t raster_config;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

213

uint32_t raster_config_1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

256

uint32_t tile_mode_array[32];

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

257

uint32_t macrotile_mode_array[16];

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

270

uint32_t double_offchip_lds_buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

272

uint32_t db_debug2;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

274

uint32_t num_sc_per_sh;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

275

uint32_t num_packer_per_sc;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

276

uint32_t pa_sc_tile_steering_override;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

280

uint32_t gc_num_tcp_per_sa;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

281

uint32_t gc_num_sdp_interface;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

282

uint32_t gc_num_tcps;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

283

uint32_t gc_num_tcp_per_wpg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

284

uint32_t gc_tcp_l1_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

285

uint32_t gc_num_sqc_per_wgp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

286

uint32_t gc_l1_instruction_cache_size_per_sqc;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

287

uint32_t gc_l1_data_cache_size_per_sqc;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

288

uint32_t gc_gl1c_per_sa;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

289

uint32_t gc_gl1c_size_per_instance;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

290

uint32_t gc_gl2c_per_gpu;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

291

uint32_t gc_tcp_size_per_cu;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

292

uint32_t gc_num_cu_per_sqc;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

293

uint32_t gc_tcc_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

294

uint32_t gc_tcp_cache_line_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

295

uint32_t gc_instruction_cache_size_per_sqc;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

296

uint32_t gc_instruction_cache_line_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

297

uint32_t gc_scalar_data_cache_size_per_sqc;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

298

uint32_t gc_scalar_data_cache_line_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

299

uint32_t gc_tcc_cache_line_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

303

uint32_t simd_per_cu;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

304

uint32_t max_waves_per_simd;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

305

uint32_t wave_front_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

306

uint32_t max_scratch_slots_per_cu;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

307

uint32_t lds_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

310

uint32_t number;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

311

uint32_t ao_cu_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

312

uint32_t ao_cu_bitmap[4][4];

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

313

uint32_t bitmap[AMDGPU_MAX_GC_INSTANCES][4][4];

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

338

void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

339

uint32_t wave, uint32_t *dst, int *no_fields);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

340

void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

341

uint32_t wave, uint32_t thread, uint32_t start,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

342

uint32_t size, uint32_t *dst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

343

void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

344

uint32_t wave, uint32_t start, uint32_t size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

345

uint32_t *dst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

369

uint32_t *pfp_fw_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

373

uint32_t *pfp_fw_data_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

379

uint32_t *ce_fw_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

385

uint32_t *me_fw_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

389

uint32_t *me_fw_data_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

391

uint32_t num_me;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

392

uint32_t num_pipe_per_me;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

393

uint32_t num_queue_per_pipe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

419

uint32_t me_fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

421

uint32_t pfp_fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

423

uint32_t ce_fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

425

uint32_t rlc_fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

427

uint32_t mec_fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

429

uint32_t mec2_fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

431

uint32_t imu_fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

432

uint32_t me_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

433

uint32_t ce_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

434

uint32_t pfp_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

435

uint32_t rlc_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

436

uint32_t rlc_srlc_fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

437

uint32_t rlc_srlc_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

438

uint32_t rlc_srlg_fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

439

uint32_t rlc_srlg_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

440

uint32_t rlc_srls_fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

441

uint32_t rlc_srls_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

442

uint32_t rlcp_ucode_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

443

uint32_t rlcp_ucode_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

444

uint32_t rlcv_ucode_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

445

uint32_t rlcv_ucode_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

446

uint32_t mec_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

447

uint32_t mec2_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

465

uint32_t gfx_current_status;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

472

uint32_t grbm_soft_reset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

473

uint32_t srbm_soft_reset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

474

uint32_t gfx_supported_reset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

475

uint32_t compute_supported_reset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

480

uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

482

uint32_t gfx_off_residency; /* last logged residency */

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

501

uint32_t num_xcc_per_xcp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

506

uint32_t *ip_dump_core;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

507

uint32_t *ip_dump_compute_queues;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

508

uint32_t *ip_dump_gfx_queues;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

539

uint32_t se_num;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

544

uint32_t size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

604

int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

616

uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

617

void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h

619

void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gfxhub.h

29

void (*setup_vm_pt_regs)(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1333

uint32_t nps_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

1577

uint32_t xcc_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

163

uint32_t gpu_page_idx, uint64_t addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

424

uint32_t hash;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

494

uint32_t last_wptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

496

uint32_t hash;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

61

uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

62

uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) - 1) >> pde0_page_shift;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

659

void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

660

uint32_t vmhub, uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

723

uint32_t flush_type, bool all_hub,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

724

uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

730

uint32_t seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

809

uint32_t reg0, uint32_t reg1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

810

uint32_t ref, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

811

uint32_t xcc_inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

817

uint32_t seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c

939

uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

104

uint32_t status);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

105

uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

109

uint32_t ctx0_ptb_addr_lo32;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

110

uint32_t ctx0_ptb_addr_hi32;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

111

uint32_t vm_inv_eng0_sem;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

112

uint32_t vm_inv_eng0_req;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

113

uint32_t vm_inv_eng0_ack;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

114

uint32_t vm_context0_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

115

uint32_t vm_l2_pro_fault_status;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

116

uint32_t vm_l2_pro_fault_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

122

uint32_t ctx_distance;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

123

uint32_t ctx_addr_distance; /* include LO32/HI32 */

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

124

uint32_t eng_distance;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

125

uint32_t eng_addr_distance; /* include LO32/HI32 */

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

127

uint32_t vm_cntx_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

128

uint32_t vm_cntx_cntl_vm_fault;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

129

uint32_t vm_l2_bank_select_reserved_cid2;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

131

uint32_t vm_contexts_disable;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

143

void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

144

uint32_t vmhub, uint32_t flush_type);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

147

uint32_t flush_type, bool all_hub,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

148

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

164

uint32_t vm_flags,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

186

uint32_t fpfn;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

187

uint32_t lpfn;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

201

uint32_t flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

272

uint32_t fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

274

uint32_t vram_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

276

uint32_t srbm_soft_reset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

278

uint32_t sdpif_register;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

303

uint32_t supported_nps_modes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

304

uint32_t reset_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

309

uint32_t xnack_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

311

uint32_t vmid0_page_table_block_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

312

uint32_t vmid0_page_table_depth;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

319

uint32_t m_half_use;

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

405

uint32_t gpu_page_idx, uint64_t addr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

428

void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

429

uint32_t vmhub, uint32_t flush_type);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

431

uint32_t flush_type, bool all_hub,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

432

uint32_t inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

434

uint32_t reg0, uint32_t reg1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

435

uint32_t ref, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.h

436

uint32_t xcc_inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_gtt_mgr.c

119

uint32_t num_pages = PFN_UP(tbo->base.size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

108

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

123

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

137

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

150

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

158

void amdgpu_bb_set_bits(void *, uint32_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

159

void amdgpu_bb_set_dir(void *, uint32_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

160

uint32_t amdgpu_bb_read_bits(void *);

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

181

amdgpu_bb_set_bits(void *cookie, uint32_t bits)

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

188

amdgpu_bb_set_dir(void *cookie, uint32_t bits)

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

192

uint32_t

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

195

uint32_t bits = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

47

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_i2c.c

89

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ib.c

135

uint32_t status = 0, alloc_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.h

52

uint32_t current_gpu_reset_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.h

54

uint32_t gds_base;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.h

55

uint32_t gds_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.h

56

uint32_t gws_base;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.h

57

uint32_t gws_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.h

58

uint32_t oa_base;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ids.h

59

uint32_t oa_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.c

171

const uint32_t *iv, unsigned int num_dw)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.c

173

uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.c

203

uint32_t checkpoint_wptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.c

289

uint32_t dw[8];

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.c

321

uint32_t iv_size = 32;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.c

322

uint32_t ring_index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.c

323

uint32_t dw1, dw2;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.c

83

ih->ring = (uint32_t *)dmah->kva;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

109

const uint32_t *iv, unsigned int num_dw);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

37

uint32_t ih_rb_base;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

38

uint32_t ih_rb_base_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

39

uint32_t ih_rb_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

40

uint32_t ih_rb_wptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

41

uint32_t ih_rb_rptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

42

uint32_t ih_doorbell_rptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

43

uint32_t ih_rb_wptr_addr_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

44

uint32_t ih_rb_wptr_addr_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

45

uint32_t psp_reg_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

53

uint32_t ptr_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

59

uint32_t *ring;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

64

uint32_t *wptr_cpu;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ih.h

67

uint32_t *rptr_cpu;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ip.c

50

static uint32_t amdgpu_logical_to_dev_mask(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ip.c

52

uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ip.c

54

uint32_t dev_mask = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ip.c

69

uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c

456

entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.h

100

uint32_t srbm_soft_reset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.h

58

const uint32_t *iv_entry;

sys/dev/pci/drm/amd/amdgpu/amdgpu_job.h

69

uint32_t preamble_status;

sys/dev/pci/drm/amd/amdgpu/amdgpu_job.h

70

uint32_t preemption_status;

sys/dev/pci/drm/amd/amdgpu/amdgpu_job.h

77

uint32_t gds_base, gds_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_job.h

78

uint32_t gws_base, gws_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_job.h

79

uint32_t oa_base, oa_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_job.h

93

uint32_t job_run_counter;

sys/dev/pci/drm/amd/amdgpu/amdgpu_job.h

99

uint32_t num_ibs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

155

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

188

static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

232

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c

470

sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

123

uint32_t *dpg_sram_curr_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

147

uint32_t supported_reset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h

148

uint32_t caps;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1069

uint32_t bios_size = adev->bios_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1078

uint32_t bios_offset = info->vbios_info.offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

1332

uint32_t max_ibs[AMDGPU_HW_IP_NUM];

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

175

amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip)

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

401

uint32_t ib_start_alignment = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

402

uint32_t ib_size_alignment = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

405

uint32_t num_slots = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

627

uint32_t size = info->return_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

629

uint32_t ui32 = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

842

uint32_t *regs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c

907

uint32_t pcie_gen_mask, pcie_width_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.c

30

uint32_t reg_index, uint32_t reg_val,

sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.c

31

uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.c

33

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.c

72

uint32_t data,

sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.h

35

uint32_t data, uint64_t size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.h

42

uint32_t data, uint64_t mem_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.h

43

int amdgpu_lsdma_wait_for(struct amdgpu_device *adev, uint32_t reg_index,

sys/dev/pci/drm/amd/amdgpu/amdgpu_lsdma.h

44

uint32_t reg_val, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c

295

static int amdgpu_mca_smu_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c

376

uint32_t count = 0, i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c

405

enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.c

424

uint32_t count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.h

133

struct mca_bank_entry *entry, uint32_t *count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.h

135

uint32_t *count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mca.h

164

enum amdgpu_mca_error_type type, uint32_t *total);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

439

uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg)

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

443

uint32_t addr_offset = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

445

uint32_t *read_val_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

452

read_val_ptr = (uint32_t *)&adev->wb.wb[addr_offset];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

477

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

503

uint32_t reg0, uint32_t reg1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

504

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

533

uint32_t spi_gdbg_per_vmid_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

534

const uint32_t *tcp_watch_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

535

uint32_t flags,

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

601

uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

693

uint32_t mes_rev = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

703

uint32_t node_id, bool enable)

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c

749

uint32_t *mem = (uint32_t *)(adev->mes.event_log_cpu_addr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

103

uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

113

uint32_t vmid_mask_gfxhub;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

114

uint32_t vmid_mask_mmhub;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

115

uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

116

uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

117

uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

118

uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

119

uint32_t sch_ctx_offs[AMDGPU_MAX_MES_PIPES];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

122

uint32_t query_status_fence_offs[AMDGPU_MAX_MES_PIPES];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

127

uint32_t saved_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

135

uint32_t db_start_dw_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

136

uint32_t num_mes_dbs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

140

uint32_t event_log_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

194

uint32_t queue_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

196

uint32_t hqd_pipe_priority;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

197

uint32_t hqd_queue_priority;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

205

uint32_t priority;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

206

uint32_t gang_quantum;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

207

uint32_t inprocess_gang_priority;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

208

uint32_t priority_level;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

213

uint32_t process_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

221

uint32_t inprocess_gang_priority;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

222

uint32_t gang_global_priority_level;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

223

uint32_t doorbell_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

227

uint32_t queue_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

228

uint32_t paging;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

229

uint32_t gws_base;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

230

uint32_t gws_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

233

uint32_t trap_en;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

234

uint32_t skip_process_ctx_clear;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

235

uint32_t is_kfd_process;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

236

uint32_t is_aql_queue;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

237

uint32_t queue_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

238

uint32_t exclusively_scheduled;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

242

uint32_t doorbell_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

247

uint32_t queue_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

248

uint32_t doorbell_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

249

uint32_t pipe_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

250

uint32_t queue_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

257

uint32_t queue_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

258

uint32_t doorbell_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

259

uint32_t pipe_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

260

uint32_t queue_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

269

uint32_t suspend_fence_value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

278

uint32_t queue_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

279

uint32_t doorbell_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

281

uint32_t me_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

282

uint32_t pipe_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

283

uint32_t queue_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

286

uint32_t vmid;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

292

uint32_t queue_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

297

uint32_t xcc_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

317

uint32_t reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

322

uint32_t reg_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

323

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

327

uint32_t ref;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

328

uint32_t mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

329

uint32_t reg0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

330

uint32_t reg1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

337

uint32_t single_memop : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

338

uint32_t single_alu_op : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

339

uint32_t reserved: 29;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

340

uint32_t process_ctx_flush: 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

342

uint32_t u32all;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

344

uint32_t spi_gdbg_per_vmid_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

345

uint32_t tcp_watch_cntl[4];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

346

uint32_t trap_en;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

352

uint32_t limit_single_process : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

353

uint32_t enable_hws_logging_buffer : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

354

uint32_t reserved : 30;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

356

uint32_t all;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

359

uint32_t tdr_level;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

360

uint32_t tdr_delay;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

427

uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

429

uint32_t reg, uint32_t val);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

431

uint32_t reg0, uint32_t reg1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

432

uint32_t ref, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

435

uint32_t spi_gdbg_per_vmid_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

436

const uint32_t *tcp_watch_cntl,

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

437

uint32_t flags,

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

442

uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

78

uint32_t sched_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

79

uint32_t kiq_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

80

uint32_t fw_version[AMDGPU_MAX_MES_PIPES];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

83

uint32_t total_max_queue;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

84

uint32_t max_doorbell_slices;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h

97

uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes_ctx.h

100

uint32_t ib[256] __aligned(256);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes_ctx.h

102

uint32_t padding[64];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes_ctx.h

113

uint32_t gang_ids[AMDGPU_HW_IP_DMA+1];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes_ctx.h

56

uint32_t data[8];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes_ctx.h

71

uint32_t ib[256] __aligned(256);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes_ctx.h

73

uint32_t padding[64];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes_ctx.h

85

uint32_t ib[256] __aligned(256);

sys/dev/pci/drm/amd/amdgpu/amdgpu_mes_ctx.h

87

uint32_t padding[64];

sys/dev/pci/drm/amd/amdgpu/amdgpu_mmhub.h

62

void (*setup_vm_pt_regs)(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

153

uint32_t mask_clk_reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

154

uint32_t mask_data_reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

155

uint32_t a_clk_reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

156

uint32_t a_data_reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

157

uint32_t en_clk_reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

158

uint32_t en_data_reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

159

uint32_t y_clk_reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

160

uint32_t y_data_reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

161

uint32_t mask_clk_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

162

uint32_t mask_data_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

163

uint32_t a_clk_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

164

uint32_t a_data_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

165

uint32_t en_clk_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

166

uint32_t en_data_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

167

uint32_t y_clk_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

168

uint32_t y_data_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

192

uint32_t reference_freq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

195

uint32_t reference_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

196

uint32_t post_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

199

uint32_t pll_in_min;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

200

uint32_t pll_in_max;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

201

uint32_t pll_out_min;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

202

uint32_t pll_out_max;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

203

uint32_t lcd_pll_out_min;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

204

uint32_t lcd_pll_out_max;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

205

uint32_t best_vco;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

208

uint32_t min_ref_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

209

uint32_t max_ref_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

210

uint32_t min_post_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

211

uint32_t max_post_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

212

uint32_t min_feedback_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

213

uint32_t max_feedback_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

214

uint32_t min_frac_feedback_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

215

uint32_t max_frac_feedback_div;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

218

uint32_t flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

221

uint32_t id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

284

uint32_t encoder_enum,

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

285

uint32_t supported_device,

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

288

uint32_t connector_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

289

uint32_t supported_device,

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

463

uint32_t crtc_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

523

uint32_t lcd_misc;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

525

uint32_t lcd_ss_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

537

uint32_t encoder_enum;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

538

uint32_t encoder_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

539

uint32_t devices;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

540

uint32_t active_device;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

541

uint32_t flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

542

uint32_t pixel_clock;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

545

uint32_t underscan_hborder;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

546

uint32_t underscan_vborder;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

621

uint32_t connector_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

622

uint32_t devices;

sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h

711

uint32_t page_flip_flags, uint32_t target,

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

1237

size_t buffer_size, uint32_t *metadata_size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

1555

uint32_t amdgpu_bo_mem_stats_placement(struct amdgpu_bo *bo)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

1557

uint32_t domain = bo->preferred_domains & AMDGPU_GEM_DOMAIN_MASK;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

1592

uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

1593

uint32_t domain)

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

955

uint32_t mem_type = bo->tbo.resource->mem_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

956

uint32_t mem_flags = bo->tbo.resource->placement;

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

294

uint32_t metadata_size, uint64_t flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

296

size_t buffer_size, uint32_t *metadata_size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

312

uint32_t amdgpu_bo_mem_stats_placement(struct amdgpu_bo *bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

313

uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

314

uint32_t domain);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.h

72

uint32_t flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1004

uint32_t cmd_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1006

uint32_t *size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1009

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1044

uint32_t reserv_size, reserv_size_ext, mp0_ip_ver;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1103

static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1128

static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1252

uint32_t session_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1292

uint32_t id, uint32_t value)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1300

uint32_t value)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1352

uint32_t ta_cmd_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1353

uint32_t session_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1361

uint32_t ta_cmd_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1409

int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1760

uint32_t cmd = cmd_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1816

int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

1897

uint32_t boot_cfg = 0xFF;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2007

struct ta_ras_trigger_error_input *info, uint32_t instance_mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2011

uint32_t dev_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2012

uint32_t ras_status = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2113

int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2187

int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2285

int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2421

int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

2951

uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D :

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3443

uint32_t ring_size_dw = ring->ring_size / 4;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3444

uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

3783

uint32_t fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

384

amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

394

amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

4034

uint32_t xcp_id, bool core_override_enable,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

4088

uint32_t fw_ver;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

415

(uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

4166

void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

426

(uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

4311

uint32_t vbflash_status;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

578

int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

579

uint32_t mask, uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

583

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

610

int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

611

uint32_t reg_val, uint32_t mask, uint32_t msec_timeout)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

613

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

798

uint32_t size = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

819

uint64_t pri_buf_mc, uint32_t size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c

829

uint32_t *tmr_size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

124

uint32_t ring_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

125

uint32_t ring_wptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

161

int (*mem_training)(struct psp_context *psp, uint32_t ops);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

162

uint32_t (*ring_get_wptr)(struct psp_context *psp);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

163

void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

165

int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

173

int (*reg_program_no_ring)(struct psp_context *psp, uint32_t val,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

179

int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

194

uint32_t num_nodes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

199

uint32_t fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

200

uint32_t feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

201

uint32_t size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

214

uint32_t session_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

215

uint32_t resp_status;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

313

uint32_t entry_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

343

uint32_t boot_cfg_bitmask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

344

uint32_t reserved;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

422

uint32_t ta_fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

424

uint32_t cap_fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

425

uint32_t cap_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

426

uint32_t cap_ucode_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

438

uint32_t boot_cfg_bitmask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

538

int psp_wait_for(struct psp_context *psp, uint32_t reg_index,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

539

uint32_t field_val, uint32_t mask, uint32_t flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

540

extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

541

uint32_t field_val, uint32_t mask, uint32_t msec_timeout);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

554

uint32_t ta_cmd_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

559

int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

570

int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

574

struct ta_ras_trigger_error_input *info, uint32_t instance_mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

580

int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

581

int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

582

int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

583

int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

588

uint32_t value);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

608

void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

618

int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcp_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h

621

int amdgpu_psp_reg_program_no_ring(struct psp_context *psp, uint32_t val,

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

146

uint32_t ta_type = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

147

uint32_t ta_bin_len = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

149

uint32_t copy_pos = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

159

ret = copy_from_user((void *)&ta_type, &buf[copy_pos], sizeof(uint32_t));

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

163

copy_pos += sizeof(uint32_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

165

ret = copy_from_user((void *)&ta_bin_len, &buf[copy_pos], sizeof(uint32_t));

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

172

copy_pos += sizeof(uint32_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

230

if (copy_to_user((char *)buf, (void *)&context->session_id, sizeof(uint32_t)))

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

245

uint32_t ta_type = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

246

uint32_t ta_id = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

247

uint32_t copy_pos = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

257

ret = copy_from_user((void *)&ta_type, &buf[copy_pos], sizeof(uint32_t));

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

261

copy_pos += sizeof(uint32_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

263

ret = copy_from_user((void *)&ta_id, &buf[copy_pos], sizeof(uint32_t));

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

291

uint32_t ta_type = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

292

uint32_t ta_id = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

293

uint32_t cmd_id = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

294

uint32_t shared_buf_len = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

296

uint32_t copy_pos = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

306

ret = copy_from_user((void *)&ta_type, &buf[copy_pos], sizeof(uint32_t));

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

309

copy_pos += sizeof(uint32_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

311

ret = copy_from_user((void *)&ta_id, &buf[copy_pos], sizeof(uint32_t));

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

314

copy_pos += sizeof(uint32_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

316

ret = copy_from_user((void *)&cmd_id, &buf[copy_pos], sizeof(uint32_t));

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

319

copy_pos += sizeof(uint32_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

321

ret = copy_from_user((void *)&shared_buf_len, &buf[copy_pos], sizeof(uint32_t));

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

324

copy_pos += sizeof(uint32_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

36

static uint32_t get_bin_version(const uint8_t *bin)

sys/dev/pci/drm/amd/amdgpu/amdgpu_psp_ta.c

46

uint32_t shared_buf_len)

sys/dev/pci/drm/amd/amdgpu/amdgpu_rap.c

52

uint32_t op;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

1065

enum amdgpu_ras_block block, uint32_t sub_block_index)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

2854

uint32_t socket = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

2883

uint32_t die_id, socket = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3057

uint32_t i = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3287

uint32_t max_count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3323

pasid_notify pasid_fn, void *data, uint32_t reset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3394

uint32_t delayed_ms)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

340

uint32_t sub_block;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3439

uint32_t poison_creation_count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3495

uint32_t msg_count, uint32_t *gpu_reset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3498

uint32_t reset_flags = 0, reset = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3549

uint32_t poison_creation_count, msg_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

3550

uint32_t gpu_reset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

436

uint32_t mask, inst_mask = data->inject.instance_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4741

static struct amdgpu_device *find_adev(uint32_t node_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4768

uint32_t gpu_id = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

4769

uint32_t umc_inst = 0, ch_inst = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5014

void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5034

uint32_t instance,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5035

uint32_t *memory_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5037

uint32_t err_status_lo_data, err_status_lo_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5058

uint32_t instance,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5061

uint32_t err_status_hi_data, err_status_hi_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5084

uint32_t reg_list_size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5086

uint32_t mem_list_size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5087

uint32_t instance,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5088

uint32_t err_type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5091

uint32_t memory_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5094

uint32_t i, j;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5136

uint32_t reg_list_size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5137

uint32_t instance)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5139

uint32_t err_status_lo_offset, err_status_hi_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c

5140

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

1008

pasid_notify pasid_fn, void *data, uint32_t reset);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

397

uint32_t hwip;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

398

uint32_t ip_inst;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

399

uint32_t seg_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

400

uint32_t reg_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

401

uint32_t seg_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

402

uint32_t reg_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

403

uint32_t reg_inst;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

404

uint32_t flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

409

uint32_t memory_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

416

uint32_t sub_block_index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

472

uint32_t reset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

478

uint32_t count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

488

uint32_t channel_idx;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

509

uint32_t features;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

510

uint32_t schema;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

531

uint32_t flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

538

uint32_t bad_page_cnt_threshold;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

561

uint32_t gpu_reset_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

708

uint32_t instance_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

738

enum amdgpu_ras_block block, uint32_t sub_block_index);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

747

void *inject_if, uint32_t instance_mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

949

void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

952

uint32_t instance,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

953

uint32_t *memory_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

956

uint32_t instance,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

960

uint32_t reg_list_size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

962

uint32_t mem_list_size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

963

uint32_t instance,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

964

uint32_t err_type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

968

uint32_t reg_list_size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h

969

uint32_t instance);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

1052

uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

240

u32 *pp = (uint32_t *)buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

253

u32 *pp = (uint32_t *)buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

297

u32 *pp = (uint32_t *)buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

300

tmp = ((uint32_t)(rai->rma_status) & 0xFF) |

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

301

(((uint32_t)(rai->health_percent) << 8) & 0xFF00) |

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

302

(((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

310

u32 *pp = (uint32_t *)buf;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.c

391

uint32_t header)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

158

uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

48

uint32_t header;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

49

uint32_t version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

50

uint32_t first_rec_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

51

uint32_t tbl_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ras_eeprom.h

52

uint32_t checksum;

sys/dev/pci/drm/amd/amdgpu/amdgpu_res_cursor.h

41

uint32_t mem_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

132

void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

134

uint32_t occupied, chunk1, chunk2;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

177

uint32_t count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

440

uint32_t reg0, uint32_t reg1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

441

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

501

uint32_t value, result, early[3];

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

519

r = put_user(early[i], (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

537

r = put_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.c

557

r = put_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

101

uint32_t length_dw;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

103

uint32_t *ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

104

uint32_t flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

117

uint32_t *cpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

119

uint32_t sync_seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

150

uint32_t seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

171

int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

172

uint32_t timeout);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

176

uint32_t wait_seq,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

183

void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

200

uint32_t align_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

245

uint32_t flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

252

void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

253

uint32_t gds_base, uint32_t gds_size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

254

uint32_t gws_base, uint32_t gws_size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

255

uint32_t oa_base, uint32_t oa_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

260

void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

270

void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

273

void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

274

uint32_t reg_val_offs);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

275

void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

276

void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

277

uint32_t val, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

279

uint32_t reg0, uint32_t reg1,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

280

uint32_t ref, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

306

uint32_t *ring;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

308

uint32_t *ring_backup;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

368

uint32_t buf_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

461

void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

471

uint32_t reg0, uint32_t val0,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

472

uint32_t reg1, uint32_t val1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

487

static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h

556

uint32_t value)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

360

void amdgpu_sw_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

484

uint32_t last_seq = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.c

80

uint32_t seq, last_seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

120

void amdgpu_sw_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

77

uint32_t seqno_to_resubmit;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ring_mux.h

96

uint32_t sync_seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

209

uint32_t offset : 25;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

210

uint32_t id : 7;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

217

uint32_t reserved0 : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

218

uint32_t reserved1 : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

219

uint32_t reserved2 : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

220

uint32_t memory_destination : 2;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

221

uint32_t vfflr_image_code : 4;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

222

uint32_t reserved9 : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

223

uint32_t reserved10 : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

224

uint32_t reserved11 : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

225

uint32_t size_x16 : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

226

uint32_t reserved13 : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

227

uint32_t size : 18;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

261

bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

265

uint32_t scratch_reg0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

266

uint32_t scratch_reg1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

267

uint32_t scratch_reg2;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

268

uint32_t scratch_reg3;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

269

uint32_t grbm_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

270

uint32_t grbm_idx;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

271

uint32_t spare_int;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

278

uint32_t *sr_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

284

uint32_t *cs_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h

290

uint32_t *cp_table_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sched.c

45

uint32_t id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

53

int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index)

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

556

int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.c

74

uint32_t index = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

125

uint32_t sdma_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

127

uint32_t srbm_soft_reset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

131

uint32_t *ip_dump;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

132

uint32_t supported_reset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

144

uint32_t copy_max_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

156

uint32_t byte_count,

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

157

uint32_t copy_flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

160

uint32_t fill_max_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

168

uint32_t src_data,

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

172

uint32_t byte_count);

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

175

int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

183

int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

62

uint32_t fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

63

uint32_t feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

68

uint32_t aid_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_sdma.h

72

uint32_t *sdma_fw_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_securedisplay.c

98

uint32_t phy_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_securedisplay.c

99

uint32_t op;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

27

uint32_t state;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

28

uint32_t dscclk_mhz;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

29

uint32_t dcfclk_mhz;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

30

uint32_t socclk_mhz;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

31

uint32_t dram_speed_mts;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

32

uint32_t fabricclk_mhz;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

33

uint32_t dispclk_mhz;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

34

uint32_t phyclk_mhz;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

35

uint32_t dppclk_mhz;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

39

uint32_t sr_exit_time_us;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

40

uint32_t sr_enter_plus_exit_time_us;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

41

uint32_t urgent_latency_us;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

42

uint32_t urgent_latency_pixel_data_only_us;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

43

uint32_t urgent_latency_pixel_mixed_with_vm_data_us;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

44

uint32_t urgent_latency_vm_data_only_us;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

45

uint32_t writeback_latency_us;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

46

uint32_t ideal_dram_bw_after_urgent_percent;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

47

uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

48

uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

49

uint32_t pct_ideal_dram_sdp_bw_after_urgent_vm_only;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

50

uint32_t max_avg_sdp_bw_use_normal_percent;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

51

uint32_t max_avg_dram_bw_use_normal_percent;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

52

uint32_t max_request_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

53

uint32_t downspread_percent;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

54

uint32_t dram_page_open_time_ns;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

55

uint32_t dram_rw_turnaround_time_ns;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

56

uint32_t dram_return_buffer_per_channel_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

57

uint32_t dram_channel_width_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

58

uint32_t fabric_datapath_to_dcn_data_return_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

59

uint32_t dcn_downspread_percent;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

60

uint32_t dispclk_dppclk_vco_speed_mhz;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

61

uint32_t dfs_vco_period_ps;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

62

uint32_t urgent_out_of_order_return_per_channel_pixel_only_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

63

uint32_t urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

64

uint32_t urgent_out_of_order_return_per_channel_vm_only_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

65

uint32_t round_trip_ping_latency_dcfclk_cycles;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

66

uint32_t urgent_out_of_order_return_per_channel_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

67

uint32_t channel_interleave_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

68

uint32_t num_banks;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

69

uint32_t num_chans;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

70

uint32_t vmm_page_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

71

uint32_t dram_clock_change_latency_us;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

72

uint32_t writeback_dram_clock_change_latency_us;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

73

uint32_t return_bus_width_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

74

uint32_t voltage_override;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

75

uint32_t xfc_bus_transport_time_us;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

76

uint32_t xfc_xbuf_latency_tolerance_us;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

77

uint32_t use_urgent_burst_bw;

sys/dev/pci/drm/amd/amdgpu/amdgpu_socbb.h

78

uint32_t num_states;

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

367

uint32_t incr, uint64_t flags, bool immediate),

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

39

TP_PROTO(unsigned did, uint32_t reg, uint32_t value),

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

43

__field(uint32_t, reg)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

44

__field(uint32_t, value)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

525

TP_PROTO(struct amdgpu_bo *bo, uint32_t new_placement, uint32_t old_placement),

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

566

TP_PROTO(uint32_t address, uint32_t value),

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

569

__field(uint32_t, address)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

570

__field(uint32_t, value)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

58

TP_PROTO(unsigned did, uint32_t reg, uint32_t value),

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

62

__field(uint32_t, reg)

sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h

63

__field(uint32_t, value)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1135

uint32_t page_flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1285

uint64_t addr, uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1503

uint32_t shift = (pos & 0x3) * 8;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1504

uint32_t mask = 0xffffffff << shift;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1505

uint32_t value = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1516

value |= (*(uint32_t *)buf << shift) & mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1771

uint32_t reserve_size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1798

uint32_t reserve_size = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

1823

reserve_size = max(reserve_size, (uint32_t)280 << 20);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

215

num_pages = min_t(uint32_t, num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2347

uint64_t dst_offset, uint32_t byte_count,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2350

bool vm_needs_flush, uint32_t copy_flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2355

uint32_t max_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2375

uint32_t cur_size_in_bytes = min(byte_count, max_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2401

static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2402

uint64_t dst_addr, uint32_t byte_count,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2411

uint32_t max_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2424

uint32_t cur_size = min(byte_count, max_bytes);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2506

uint32_t src_data,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2618

uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2652

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

2657

r = get_user(value, (uint32_t *)buf);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

300

uint32_t copy_flags = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

315

uint32_t num_type, data_format, max_com, write_compress_disable;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

675

uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

696

uint32_t userflags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h

170

uint64_t dst_offset, uint32_t byte_count,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h

173

bool vm_needs_flush, uint32_t copy_flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h

184

uint32_t src_data,

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h

192

uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h

222

uint64_t addr, uint32_t flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.h

88

uint32_t discovery_tmr_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

1420

uint32_t version = amdgpu_ip_version(adev, block_type, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

349

uint32_t fw_index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.c

729

static inline int amdgpu_ucode_is_valid(uint32_t fw_version)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

112

uint32_t fw_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

113

uint32_t fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

114

uint32_t offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

115

uint32_t size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

138

uint32_t psp_fw_bin_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

145

uint32_t psp_fw_bin_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

146

uint32_t psp_aux_fw_bin_index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

176

uint32_t ta_fw_bin_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

183

uint32_t ucode_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

184

uint32_t jt_offset; /* jt location */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

185

uint32_t jt_size; /* size of jt */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

191

uint32_t ucode_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

192

uint32_t ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

193

uint32_t ucode_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

194

uint32_t data_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

195

uint32_t data_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

196

uint32_t ucode_start_addr_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

197

uint32_t ucode_start_addr_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

203

uint32_t mes_ucode_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

204

uint32_t mes_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

205

uint32_t mes_ucode_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

206

uint32_t mes_ucode_data_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

207

uint32_t mes_ucode_data_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

208

uint32_t mes_ucode_data_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

209

uint32_t mes_uc_start_addr_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

210

uint32_t mes_uc_start_addr_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

211

uint32_t mes_data_start_addr_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

212

uint32_t mes_data_start_addr_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

218

uint32_t ucode_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

219

uint32_t save_and_restore_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

220

uint32_t clear_state_descriptor_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

221

uint32_t avail_scratch_ram_locations;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

222

uint32_t master_pkt_description_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

228

uint32_t ucode_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

229

uint32_t jt_offset; /* jt location */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

230

uint32_t jt_size; /* size of jt */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

231

uint32_t save_and_restore_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

232

uint32_t clear_state_descriptor_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

233

uint32_t avail_scratch_ram_locations;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

234

uint32_t reg_restore_list_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

235

uint32_t reg_list_format_start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

236

uint32_t reg_list_format_separate_start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

237

uint32_t starting_offsets_start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

238

uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

239

uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

240

uint32_t reg_list_size_bytes; /* size of reg list array in bytes */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

241

uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

242

uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

243

uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

244

uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

245

uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

251

uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

252

uint32_t save_restore_list_cntl_ucode_ver;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

253

uint32_t save_restore_list_cntl_feature_ver;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

254

uint32_t save_restore_list_cntl_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

255

uint32_t save_restore_list_cntl_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

256

uint32_t save_restore_list_gpm_ucode_ver;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

257

uint32_t save_restore_list_gpm_feature_ver;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

258

uint32_t save_restore_list_gpm_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

259

uint32_t save_restore_list_gpm_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

260

uint32_t save_restore_list_srm_ucode_ver;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

261

uint32_t save_restore_list_srm_feature_ver;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

262

uint32_t save_restore_list_srm_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

263

uint32_t save_restore_list_srm_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

269

uint32_t rlc_iram_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

270

uint32_t rlc_iram_ucode_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

271

uint32_t rlc_dram_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

272

uint32_t rlc_dram_ucode_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

278

uint32_t rlcp_ucode_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

279

uint32_t rlcp_ucode_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

280

uint32_t rlcp_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

281

uint32_t rlcp_ucode_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

282

uint32_t rlcv_ucode_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

283

uint32_t rlcv_ucode_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

284

uint32_t rlcv_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

285

uint32_t rlcv_ucode_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

291

uint32_t global_tap_delays_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

292

uint32_t global_tap_delays_ucode_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

293

uint32_t se0_tap_delays_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

294

uint32_t se0_tap_delays_ucode_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

295

uint32_t se1_tap_delays_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

296

uint32_t se1_tap_delays_ucode_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

297

uint32_t se2_tap_delays_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

298

uint32_t se2_tap_delays_ucode_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

299

uint32_t se3_tap_delays_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

300

uint32_t se3_tap_delays_ucode_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

306

uint32_t ucode_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

307

uint32_t ucode_change_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

308

uint32_t jt_offset; /* jt location */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

309

uint32_t jt_size; /* size of jt */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

31

uint32_t size_bytes; /* size of the entire header+image(s) in bytes */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

315

uint32_t digest_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

32

uint32_t header_size_bytes; /* size of just the header in bytes */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

321

uint32_t ucode_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

322

uint32_t ctx_ucode_size_bytes; /* context thread ucode size */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

323

uint32_t ctx_jt_offset; /* context thread jt location */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

324

uint32_t ctx_jt_size; /* context thread size of jt */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

325

uint32_t ctl_ucode_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

326

uint32_t ctl_ucode_size_bytes; /* control thread ucode size */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

327

uint32_t ctl_jt_offset; /* control thread jt location */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

328

uint32_t ctl_jt_size; /* control thread size of jt */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

334

uint32_t ucode_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

335

uint32_t ctx_ucode_size_bytes; /* context thread ucode size */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

336

uint32_t ctx_jt_offset; /* context thread jt location */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

337

uint32_t ctx_jt_size; /* context thread size of jt */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

338

uint32_t ctl_ucode_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

339

uint32_t ctl_ucode_size_bytes; /* control thread ucode size */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

340

uint32_t ctl_jt_offset; /* control thread jt location */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

341

uint32_t ctl_jt_size; /* control thread size of jt */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

347

uint32_t umsch_mm_ucode_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

348

uint32_t umsch_mm_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

349

uint32_t umsch_mm_ucode_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

350

uint32_t umsch_mm_ucode_data_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

351

uint32_t umsch_mm_ucode_data_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

352

uint32_t umsch_mm_ucode_data_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

353

uint32_t umsch_mm_irq_start_addr_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

354

uint32_t umsch_mm_irq_start_addr_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

355

uint32_t umsch_mm_uc_start_addr_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

356

uint32_t umsch_mm_uc_start_addr_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

357

uint32_t umsch_mm_data_start_addr_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

358

uint32_t umsch_mm_data_start_addr_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

364

uint32_t ucode_feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

365

uint32_t ucode_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

366

uint32_t ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

37

uint32_t ucode_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

371

uint32_t gc_num_se;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

372

uint32_t gc_num_cu_per_sh;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

373

uint32_t gc_num_sh_per_se;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

374

uint32_t gc_num_rb_per_se;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

375

uint32_t gc_num_tccs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

376

uint32_t gc_num_gprs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

377

uint32_t gc_num_max_gs_thds;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

378

uint32_t gc_gs_table_depth;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

379

uint32_t gc_gsprim_buff_depth;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

38

uint32_t ucode_size_bytes; /* size of ucode in bytes */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

380

uint32_t gc_parameter_cache_depth;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

381

uint32_t gc_double_offchip_lds_buffer;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

382

uint32_t gc_wave_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

383

uint32_t gc_max_waves_per_simd;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

384

uint32_t gc_max_scratch_slots_per_cu;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

385

uint32_t gc_lds_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

39

uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

390

uint32_t num_sc_per_sh;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

391

uint32_t num_packer_per_sc;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

40

uint32_t crc32; /* crc32 checksum of the payload */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

411

uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

412

uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

418

uint32_t inst_const_bytes; /* size of instruction region, in bytes */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

419

uint32_t bss_data_bytes; /* size of bss/data region, in bytes */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

425

uint32_t imu_iram_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

426

uint32_t imu_iram_ucode_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

427

uint32_t imu_dram_ucode_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

428

uint32_t imu_dram_ucode_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

46

uint32_t io_debug_size_bytes; /* size of debug array in dwords */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

47

uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

53

uint32_t ucode_start_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

583

uint32_t ucode_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

585

uint32_t tmr_mc_addr_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

586

uint32_t tmr_mc_addr_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

59

uint32_t ppt_offset_bytes; /* soft pptable offset */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

60

uint32_t ppt_size_bytes; /* soft pptable size */

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

605

uint32_t pldm_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

64

uint32_t id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

65

uint32_t ppt_offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

66

uint32_t ppt_size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

72

uint32_t pptable_count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

73

uint32_t pptable_entry_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

77

uint32_t fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

78

uint32_t offset_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_ucode.h

79

uint32_t size_bytes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

191

uint32_t reset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

210

pasid_notify pasid_fn, void *data, uint32_t reset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

271

enum amdgpu_ras_block block, uint32_t reset)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

33

uint32_t ch_inst, uint32_t umc_inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

366

uint32_t channel_index,

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

367

uint32_t umc_inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

395

uint32_t umc_node_inst;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

396

uint32_t node_inst;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

397

uint32_t umc_inst;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

398

uint32_t ch_inst;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

434

uint32_t node_inst = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

435

uint32_t umc_inst = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

436

uint32_t ch_inst = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

50

uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst)

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

546

uint64_t err_addr, uint32_t ch, uint32_t umc,

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.c

547

uint32_t node, uint32_t socket,

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

113

uint32_t (*get_die_id_from_pa)(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

124

uint32_t max_ras_err_cnt_per_query;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

126

uint32_t channel_inst_num;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

128

uint32_t umc_inst_num;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

131

uint32_t node_inst_num;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

134

uint32_t channel_offs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

136

uint32_t retire_unit;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

138

const uint32_t *channel_idx_tbl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

155

enum amdgpu_ras_block block, uint32_t reset);

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

158

pasid_notify pasid_fn, void *data, uint32_t reset);

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

165

uint32_t channel_index,

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

166

uint32_t umc_inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

172

uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst);

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

189

uint64_t err_addr, uint32_t ch, uint32_t umc,

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

190

uint32_t node, uint32_t socket,

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

87

uint32_t flip_bits_in_pa[RETIRE_FLIP_BITS_NUM];

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

88

uint32_t flip_row_bit;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

89

uint32_t r13_in_pa;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

90

uint32_t bit_num;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

93

typedef int (*umc_func)(struct amdgpu_device *adev, uint32_t node_inst,

sys/dev/pci/drm/amd/amdgpu/amdgpu_umc.h

94

uint32_t umc_inst, uint32_t ch_inst, void *data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.c

182

uint32_t fw_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.c

214

uint32_t fw_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.c

256

uint32_t umsch_mm_agdb_start;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

100

uint32_t doorbell_offset_0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

101

uint32_t doorbell_offset_1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

103

uint32_t context_csa_array_index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

107

uint32_t rb_base_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

108

uint32_t rb_base_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

109

uint32_t rb_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

110

uint32_t wptr_val;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

111

uint32_t rptr_val;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

112

uint32_t unmapped;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

113

uint32_t vmid;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

136

uint32_t rb_wptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

137

uint32_t rb_rptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

142

uint32_t fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

143

uint32_t feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

147

uint32_t *ucode_fw_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

150

uint32_t ucode_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

154

uint32_t *data_fw_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

156

uint32_t data_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

160

uint32_t *cmd_buf_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

161

uint32_t *cmd_buf_curr_ptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

163

uint32_t wb_index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

165

uint32_t *sch_ctx_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

167

uint32_t vmid_mask_mm_vcn;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

168

uint32_t vmid_mask_mm_vpe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

169

uint32_t engine_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

170

uint32_t vcn0_hqd_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

171

uint32_t vcn1_hqd_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

172

uint32_t vcn_hqd_mask[2];

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

173

uint32_t vpe_hqd_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

174

uint32_t agdb_index[CONTEXT_PRIORITY_NUM_LEVELS];

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

180

uint32_t mem_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

181

uint32_t log_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

202

uint32_t reg_offset = adev->reg_offset[VCN_HWIP][0][reg##_BASE_IDX] + reg; \

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

45

uint32_t vmid_mask_mm_vcn;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

46

uint32_t vmid_mask_mm_vpe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

47

uint32_t collaboration_mask_vpe;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

48

uint32_t logging_vmid;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

49

uint32_t engine_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

52

uint32_t disable_reset : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

53

uint32_t disable_umsch_mm_log : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

54

uint32_t use_rs64mem_for_proc_ctx_csa : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

55

uint32_t reserved : 29;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

57

uint32_t uint32_all;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

62

uint32_t rptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

63

uint32_t wptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

64

uint32_t buffer_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

65

uint32_t header_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

66

uint32_t wrapped;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

70

uint32_t process_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

78

uint32_t inprocess_context_priority;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

80

uint32_t doorbell_offset_0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

81

uint32_t doorbell_offset_1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

83

uint32_t affinity;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

87

uint32_t vm_context_cntl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

89

uint32_t process_csa_array_index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

90

uint32_t context_csa_array_index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

93

uint32_t is_context_suspended : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

94

uint32_t collaboration_mode : 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h

95

uint32_t reserved : 30;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.c

991

uint32_t queue_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.h

108

uint32_t queue_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_userq.h

109

uint32_t doorbell_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

1047

uint32_t cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

1130

uint32_t offset, data[4];

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

1201

int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

1206

uint32_t *msg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

1229

int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

1234

uint32_t *msg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

1367

uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

1370

uint32_t used_handles = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

141

uint32_t size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

526

uint32_t handle = atomic_read(&adev->uvd.handles[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

561

uint32_t lo, hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

584

uint32_t cmd;

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

599

uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

620

static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c

916

uint32_t cmd;

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.h

48

uint32_t srbm_soft_reset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.h

70

uint32_t keyselect;

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.h

80

int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.h

82

int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.h

92

uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

1071

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

1110

uint32_t rptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

415

uint32_t handle = atomic_read(&adev->vce.handles[i]);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

438

static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

530

static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

652

int lo, int hi, unsigned int size, uint32_t index)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

701

uint32_t handle, uint32_t *allocated)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

743

uint32_t destroyed = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

744

uint32_t created = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

745

uint32_t allocated = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

746

uint32_t tmp, handle = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

747

uint32_t dummy = 0xffffffff;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

748

uint32_t *size = &dummy;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

755

uint32_t len = amdgpu_ib_get_value(ib, idx);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

756

uint32_t cmd = amdgpu_ib_get_value(ib, idx + 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

821

uint32_t len = amdgpu_ib_get_value(ib, idx);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

822

uint32_t cmd = amdgpu_ib_get_value(ib, idx + 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

85

static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

87

static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

980

uint32_t destroyed = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

981

uint32_t created = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

982

uint32_t allocated = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

983

uint32_t tmp, handle = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

987

uint32_t len = amdgpu_ib_get_value(ib, idx);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c

988

uint32_t cmd = amdgpu_ib_get_value(ib, idx + 1);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.h

44

uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.h

52

uint32_t srbm_soft_reset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.h

68

struct amdgpu_ib *ib, uint32_t flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1240

uint32_t *flag = vcn->fw_shared.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1492

uint32_t instance_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

1563

sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

297

bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

557

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

588

uint32_t rptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

665

static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

669

uint32_t *msg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

679

msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

700

static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

704

uint32_t *msg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

714

msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

759

static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

760

uint32_t ib_pack_in_dw, bool enc)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

762

uint32_t *ib_checksum;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

772

ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

777

static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

778

uint32_t ib_pack_in_dw)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

780

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

781

uint32_t checksum = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

800

uint32_t *ib_checksum;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

801

uint32_t ib_pack_in_dw;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

818

ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

893

uint32_t rptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

921

static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

930

uint32_t *ib_checksum = NULL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

988

static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c

997

uint32_t *ib_checksum = NULL;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

103

uint32_t internal_reg_offset, addr; \

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

164

uint32_t internal_reg_offset, addr; \

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

294

uint32_t mem_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

295

uint32_t log_offset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

315

uint32_t *dpg_sram_curr_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

321

uint32_t vcn_codec_disable_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

357

uint32_t *ip_dump;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

359

uint32_t supported_reset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

360

uint32_t caps;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

373

uint32_t rptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

374

uint32_t wptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

399

uint32_t addr_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

400

uint32_t addr_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

401

uint32_t size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

410

uint32_t present_flag_0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

421

uint32_t rb_addr_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

422

uint32_t rb_addr_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

423

uint32_t rb_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

427

uint32_t is_rb_enabled_flags;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

431

uint32_t rb_addr_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

432

uint32_t rb_addr_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

433

uint32_t rb_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

434

uint32_t rb4_addr_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

435

uint32_t rb4_addr_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

436

uint32_t rb4_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

437

uint32_t reserved[6];

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

457

uint32_t present_flag_0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

471

uint32_t rptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

472

uint32_t wptr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

473

uint32_t buffer_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

474

uint32_t header_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

479

uint32_t valid_buf_flag;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

480

uint32_t msg_buffer_address_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

481

uint32_t msg_buffer_address_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

482

uint32_t pad[30];

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

486

uint32_t size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

487

uint32_t present_flag_0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

495

uint32_t present_flag_0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h

526

enum vcn_ring_type type, uint32_t vcn_instance);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1056

uint32_t timeout = 50000;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1057

uint32_t i, tmp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1058

uint32_t ret = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1304

uint32_t checksum, used_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1382

uint32_t checksum, used_size, i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1436

uint32_t more = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

1515

uint32_t checksum, used_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

419

uint64_t bp_block_offset, uint32_t bp_block_size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

423

uint32_t bp_idx, bp_cnt;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

453

uint32_t checksum;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

454

uint32_t checkval;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

456

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

457

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

700

uint32_t bp_block_size = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

746

uint32_t reg;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

849

uint32_t reg = amdgpu_virt_init_detect_asic(adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

922

bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

989

struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

990

struct amdgpu_video_codec_info *decode, uint32_t decode_array_size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c

992

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

214

uint32_t checksum;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

218

uint32_t driver_cert;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

220

uint32_t os_info;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

222

uint32_t fb_usage;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

224

uint32_t gfx_usage;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

226

uint32_t gfx_health;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

228

uint32_t compute_usage;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

230

uint32_t compute_health;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

232

uint32_t vce_enc_usage;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

234

uint32_t vce_enc_health;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

236

uint32_t uvd_enc_usage;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

238

uint32_t uvd_enc_health;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

239

uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

281

uint32_t caps;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

285

uint32_t reg_val_offs;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

298

uint32_t gim_feature;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

299

uint32_t reg_access_mode;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

304

uint32_t reg_access;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

308

uint32_t vf2pf_update_interval_ms;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

313

uint32_t decode_max_dimension_pixels;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

314

uint32_t decode_max_frame_pixels;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

315

uint32_t encode_max_dimension_pixels;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

316

uint32_t encode_max_frame_pixels;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

319

uint32_t autoload_ucode_id;

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

448

struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

449

struct amdgpu_video_codec_info *decode, uint32_t decode_array_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

456

uint32_t ucode_id);

sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.h

65

uint32_t *cpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

1748

uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

1749

uint32_t xcc_mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

1904

uint64_t size, uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

1963

uint64_t size, uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2384

static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2407

void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2408

uint32_t fragment_size_default, unsigned max_level,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

2646

int32_t xcp_id, uint32_t pasid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

3227

uint32_t status,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

366

uint32_t bo_memtype = amdgpu_bo_mem_stats_placement(bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

416

uint32_t bo_memtype = amdgpu_bo_mem_stats_placement(bo);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c

427

uint32_t res_memtype = res->mem_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

230

uint32_t incr);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

235

uint32_t incr, uint64_t flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

314

unsigned count, uint32_t incr, uint64_t flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

323

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

471

uint32_t num_level;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

472

uint32_t block_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

473

uint32_t fragment_size;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

514

int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id, uint32_t pasid);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

538

uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

539

uint32_t xcc_mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

568

uint64_t size, uint32_t flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

572

uint64_t size, uint32_t flags);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

584

void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

585

uint32_t fragment_size_default, unsigned max_level,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.h

697

uint32_t status,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_cpu.c

73

uint64_t addr, unsigned count, uint32_t incr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c

102

static uint32_t amdgpu_vm_pt_entries_mask(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_pt.c

682

unsigned int count, uint32_t incr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_sdma.c

190

uint32_t incr, uint64_t flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vm_sdma.c

221

uint64_t addr, unsigned count, uint32_t incr,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

124

uint32_t dpm_ctl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

130

uint32_t idx;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

131

uint32_t vpeclk_enalbled_num = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

132

uint32_t pratio_vmax_vnorm = 0, pratio_vnorm_vmid = 0, pratio_vmid_vmin = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

158

uint32_t soc_dpm_level;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

159

uint32_t min_freq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

192

uint32_t pratio_ctl;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

194

pratio_vmax_vnorm = (uint32_t)vpe_internal_get_pratio(pratio_vmax_freq, pratio_vnorm_freq);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

195

pratio_vnorm_vmid = (uint32_t)vpe_internal_get_pratio(pratio_vnorm_freq, pratio_vmid_freq);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

196

pratio_vmid_vmin = (uint32_t)vpe_internal_get_pratio(pratio_vmid_freq, pratio_vmin_freq);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

485

static void vpe_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

497

static uint64_t vpe_get_csa_mc_addr(struct amdgpu_ring *ring, uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

500

uint32_t index = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

513

uint32_t device_select,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

514

uint32_t exec_count)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

527

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

529

uint32_t vmid = AMDGPU_JOB_GET_VMID(job);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

569

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

587

static void vpe_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

596

static void vpe_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

597

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

638

uint32_t preempt_reg = vpe->regs.queue0_preempt;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

777

const uint32_t test_pattern = 0xdeadbeef;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

778

uint32_t index, i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

819

const uint32_t test_pattern = 0xdeadbeef;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

822

uint32_t index;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c

879

uint32_t context_notify;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

35

uint32_t (*get_reg_offset)(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset);

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

47

uint32_t queue0_rb_rptr_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

48

uint32_t queue0_rb_rptr_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

49

uint32_t queue0_rb_wptr_lo;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

50

uint32_t queue0_rb_wptr_hi;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

51

uint32_t queue0_preempt;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

53

uint32_t dpm_enable;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

54

uint32_t dpm_pratio;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

55

uint32_t dpm_request_interval;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

56

uint32_t dpm_decision_threshold;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

57

uint32_t dpm_busy_clamp_threshold;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

58

uint32_t dpm_idle_clamp_threshold;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

59

uint32_t dpm_request_lv;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

60

uint32_t context_indicator;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

71

uint32_t fw_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

72

uint32_t feature_version;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

76

uint32_t *cmdbuf_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

80

uint32_t num_instances;

sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.h

82

uint32_t supported_reset;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

128

uint32_t inst_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

36

int (*run_func)(void *handle, uint32_t inst_mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

381

uint32_t *inst_mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

523

uint32_t inst_idx,

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.c

528

uint32_t inst_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h

130

uint32_t supp_xcp_modes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h

131

uint32_t avail_xcp_modes;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h

168

uint32_t *inst_mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h

86

int (*prepare_suspend)(void *handle, uint32_t inst_mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h

87

int (*suspend)(void *handle, uint32_t inst_mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h

88

int (*prepare_resume)(void *handle, uint32_t inst_mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h

89

int (*resume)(void *handle, uint32_t inst_mask);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xcp.h

94

uint32_t inst_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1289

static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1297

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1369

uint32_t value,

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1370

uint32_t mask_value,

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1371

uint32_t *ue_count,

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1372

uint32_t *ce_count,

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1379

uint32_t field_array_size = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1426

uint32_t data, mask_data = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1427

uint32_t ue_cnt = 0, ce_cnt = 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

1603

void *inject_if, uint32_t instance_mask)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

543

uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.c

896

uint32_t *min_bw, uint32_t *max_bw)

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.h

107

uint32_t *min_bw, uint32_t *max_bw);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.h

125

uint32_t amdgpu_xgmi_get_max_bandwidth(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.h

53

uint32_t pcs_err_mask;

sys/dev/pci/drm/amd/amdgpu/amdgpu_xgmi.h

54

uint32_t pcs_err_shift;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

100

uint32_t vcn_rb_decouple : 1;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

101

uint32_t mes_info_dump_enable : 1;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

102

uint32_t ras_caps : 1;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

103

uint32_t ras_telemetry : 1;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

104

uint32_t ras_cper : 1;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

105

uint32_t reserved : 20;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

107

uint32_t all;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

112

uint32_t vf_reg_access_ih : 1;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

113

uint32_t vf_reg_access_mmhub : 1;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

114

uint32_t vf_reg_access_gc : 1;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

115

uint32_t vf_reg_access_l1_tlb_cntl : 1;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

116

uint32_t vf_reg_access_sq_config : 1;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

117

uint32_t reserved : 27;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

119

uint32_t all;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

151

uint32_t windows : 1;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

152

uint32_t reserved : 31;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

154

uint32_t all;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

160

uint32_t did : 16;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

161

uint32_t fcn : 8;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

162

uint32_t asic_7 : 8;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

164

uint32_t time_low;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

168

uint32_t time_mid : 16;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

169

uint32_t time_high : 12;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

170

uint32_t version : 4;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

185

uint32_t asic_0;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

190

uint32_t size;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

192

uint32_t version;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

194

uint32_t reserved[2];

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

202

uint32_t checksum;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

206

uint32_t hevc_enc_max_mb_per_second;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

208

uint32_t hevc_enc_max_mb_per_frame;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

210

uint32_t avc_enc_max_mb_per_second;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

212

uint32_t avc_enc_max_mb_per_frame;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

216

uint32_t mecfw_size;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

220

uint32_t uvdfw_size;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

224

uint32_t vcefw_size;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

226

uint32_t bp_block_offset_low;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

227

uint32_t bp_block_offset_high;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

229

uint32_t bp_block_size;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

231

uint32_t vf2pf_update_interval_ms;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

234

uint32_t fcn_idx;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

239

uint32_t decode_max_dimension_pixels;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

240

uint32_t decode_max_frame_pixels;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

241

uint32_t encode_max_dimension_pixels;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

242

uint32_t encode_max_frame_pixels;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

247

uint32_t pcie_atomic_ops_support_flags;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

249

uint32_t gpu_capacity;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

251

uint32_t bdf_on_host;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

252

uint32_t more_bp; //Reserved for future use.

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

257

uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE];

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

262

uint32_t size;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

264

uint32_t version;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

266

uint32_t reserved[2];

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

273

uint32_t checksum;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

277

uint32_t driver_cert;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

281

uint32_t fb_usage;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

283

uint32_t gfx_usage;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

285

uint32_t gfx_health;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

287

uint32_t compute_usage;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

289

uint32_t compute_health;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

291

uint32_t avc_enc_usage;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

293

uint32_t avc_enc_health;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

295

uint32_t hevc_enc_usage;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

297

uint32_t hevc_enc_health;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

299

uint32_t encode_usage;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

300

uint32_t decode_usage;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

302

uint32_t pf2vf_version_required;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

304

uint32_t fb_vis_usage;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

305

uint32_t fb_vis_size;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

306

uint32_t fb_size;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

310

uint32_t version;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

315

uint32_t mes_info_size;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

317

uint32_t reserved[256 - AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE];

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

383

uint32_t checksum;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

384

uint32_t used_size;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

385

uint32_t reserved[2];

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

390

uint32_t ce_count;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

391

uint32_t ue_count;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

392

uint32_t de_count;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

393

uint32_t ce_overflow_count;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

394

uint32_t ue_overflow_count;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

395

uint32_t de_overflow_count;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

396

uint32_t reserved[6];

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

401

uint32_t more;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

405

uint32_t buf[];

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

409

uint32_t hit;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

93

uint32_t error_log_collect : 1;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

94

uint32_t host_load_ucodes : 1;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

95

uint32_t host_flr_vramlost : 1;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

96

uint32_t mm_bw_management : 1;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

97

uint32_t pp_one_vf_mode : 1;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

98

uint32_t reg_indirect_acc : 1;

sys/dev/pci/drm/amd/amdgpu/amdgv_sriovmsg.h

99

uint32_t av1_support : 1;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

230

uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

458

uint32_t xcc_mask;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

585

uint32_t num_regs;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

586

uint32_t incrx;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

618

uint32_t start_addr, incrx, num_regs, szbuf;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

709

uint32_t start_addr, incrx, num_regs, szbuf;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

783

uint32_t start_addr, incrx, num_regs, szbuf;

sys/dev/pci/drm/amd/amdgpu/aqua_vanjaram.c

894

uint32_t start_addr, incrx, num_regs, szbuf, num_smn;

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

32

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

34

adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

35

adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

36

adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

37

adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

38

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

39

adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

40

adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

41

adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

42

adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

43

adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

44

adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

45

adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

46

adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(SDMA2_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

47

adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(SDMA3_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

48

adev->reg_offset[SDMA4_HWIP][i] = (uint32_t *)(&(SDMA4_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

49

adev->reg_offset[SDMA5_HWIP][i] = (uint32_t *)(&(SDMA5_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

50

adev->reg_offset[SDMA6_HWIP][i] = (uint32_t *)(&(SDMA6_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

51

adev->reg_offset[SDMA7_HWIP][i] = (uint32_t *)(&(SDMA7_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

52

adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

53

adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

54

adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/arct_reg_init.c

55

adev->reg_offset[RSMU_HWIP][i] = (uint32_t *)(&(RSMU_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/athub_v1_0.c

35

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/athub_v1_0.c

51

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/athub_v2_0.c

37

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/athub_v2_0.c

57

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/athub_v2_1.c

36

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/athub_v2_1.c

53

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/athub_v3_0.c

37

static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/athub_v3_0.c

39

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/athub_v3_0.c

55

static void athub_v3_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data)

sys/dev/pci/drm/amd/amdgpu/athub_v3_0.c

74

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/athub_v3_0.c

91

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/athub_v4_1_0.c

30

static uint32_t athub_v4_1_0_get_cg_cntl(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/athub_v4_1_0.c

32

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/athub_v4_1_0.c

45

static void athub_v4_1_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data)

sys/dev/pci/drm/amd/amdgpu/athub_v4_1_0.c

60

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/athub_v4_1_0.c

77

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/atom.c

1010

uint32_t dst, src, saved;

sys/dev/pci/drm/amd/amdgpu/atom.c

1024

uint32_t src, val, target;

sys/dev/pci/drm/amd/amdgpu/atom.c

1051

uint32_t dst, src;

sys/dev/pci/drm/amd/amdgpu/atom.c

1063

uint32_t dst, src, saved;

sys/dev/pci/drm/amd/amdgpu/atom.c

110

static uint32_t atom_iio_execute(struct atom_context *ctx, int base,

sys/dev/pci/drm/amd/amdgpu/atom.c

111

uint32_t index, uint32_t data)

sys/dev/pci/drm/amd/amdgpu/atom.c

113

uint32_t temp = 0xCDCDCDCD;

sys/dev/pci/drm/amd/amdgpu/atom.c

1221

static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params, int params_size)

sys/dev/pci/drm/amd/amdgpu/atom.c

1291

int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params, int params_size)

sys/dev/pci/drm/amd/amdgpu/atom.c

1591

uint32_t ps[16];

sys/dev/pci/drm/amd/amdgpu/atom.c

182

static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,

sys/dev/pci/drm/amd/amdgpu/atom.c

183

int *ptr, uint32_t *saved, int print)

sys/dev/pci/drm/amd/amdgpu/atom.c

185

uint32_t idx, val = 0xCDCDCDCD, align, arg;

sys/dev/pci/drm/amd/amdgpu/atom.c

375

uint32_t align = (attr >> 3) & 7, arg = attr & 7;

sys/dev/pci/drm/amd/amdgpu/atom.c

408

static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)

sys/dev/pci/drm/amd/amdgpu/atom.c

413

static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)

sys/dev/pci/drm/amd/amdgpu/atom.c

415

uint32_t val = 0xCDCDCDCD;

sys/dev/pci/drm/amd/amdgpu/atom.c

439

static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,

sys/dev/pci/drm/amd/amdgpu/atom.c

440

int *ptr, uint32_t *saved, int print)

sys/dev/pci/drm/amd/amdgpu/atom.c

456

int *ptr, uint32_t val, uint32_t saved)

sys/dev/pci/drm/amd/amdgpu/atom.c

458

uint32_t align =

sys/dev/pci/drm/amd/amdgpu/atom.c

602

uint32_t dst, src, saved;

sys/dev/pci/drm/amd/amdgpu/atom.c

616

uint32_t dst, src, saved;

sys/dev/pci/drm/amd/amdgpu/atom.c

64

uint32_t *ps, *ws;

sys/dev/pci/drm/amd/amdgpu/atom.c

651

uint32_t saved;

sys/dev/pci/drm/amd/amdgpu/atom.c

663

uint32_t dst, src;

sys/dev/pci/drm/amd/amdgpu/atom.c

689

uint32_t dst, src;

sys/dev/pci/drm/amd/amdgpu/atom.c

707

uint32_t dst, src;

sys/dev/pci/drm/amd/amdgpu/atom.c

74

static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params, int params_size);

sys/dev/pci/drm/amd/amdgpu/atom.c

75

int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params, int params_size);

sys/dev/pci/drm/amd/amdgpu/atom.c

77

static uint32_t atom_arg_mask[8] =

sys/dev/pci/drm/amd/amdgpu/atom.c

786

uint32_t dst, mask, src, saved;

sys/dev/pci/drm/amd/amdgpu/atom.c

803

uint32_t src, saved;

sys/dev/pci/drm/amd/amdgpu/atom.c

820

uint32_t dst, src;

sys/dev/pci/drm/amd/amdgpu/atom.c

832

uint32_t dst, src;

sys/dev/pci/drm/amd/amdgpu/atom.c

850

uint32_t dst, src, saved;

sys/dev/pci/drm/amd/amdgpu/atom.c

940

uint32_t saved, dst;

sys/dev/pci/drm/amd/amdgpu/atom.c

956

uint32_t saved, dst;

sys/dev/pci/drm/amd/amdgpu/atom.c

972

uint32_t saved, dst;

sys/dev/pci/drm/amd/amdgpu/atom.c

974

uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];

sys/dev/pci/drm/amd/amdgpu/atom.c

991

uint32_t saved, dst;

sys/dev/pci/drm/amd/amdgpu/atom.c

993

uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];

sys/dev/pci/drm/amd/amdgpu/atom.h

122

u32 reg, uint32_t val); /* filled by driver */

sys/dev/pci/drm/amd/amdgpu/atom.h

123

uint32_t (*reg_read)(struct card_info *info, uint32_t reg); /* filled by driver */

sys/dev/pci/drm/amd/amdgpu/atom.h

125

u32 reg, uint32_t val); /* filled by driver */

sys/dev/pci/drm/amd/amdgpu/atom.h

126

uint32_t (*mc_read)(struct card_info *info, uint32_t reg); /* filled by driver */

sys/dev/pci/drm/amd/amdgpu/atom.h

128

u32 reg, uint32_t val); /* filled by driver */

sys/dev/pci/drm/amd/amdgpu/atom.h

129

uint32_t (*pll_read)(struct card_info *info, uint32_t reg); /* filled by driver */

sys/dev/pci/drm/amd/amdgpu/atom.h

136

uint32_t cmd_table, data_table;

sys/dev/pci/drm/amd/amdgpu/atom.h

140

uint32_t fb_base;

sys/dev/pci/drm/amd/amdgpu/atom.h

141

uint32_t divmul[2];

sys/dev/pci/drm/amd/amdgpu/atom.h

147

uint32_t *scratch;

sys/dev/pci/drm/amd/amdgpu/atom.h

152

uint32_t version;

sys/dev/pci/drm/amd/amdgpu/atom.h

161

int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params, int params_size);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

109

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

126

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

142

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

158

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

174

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

186

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

231

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

296

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

398

index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

431

index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

517

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

547

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

743

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

80

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

304

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

86

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1139

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1167

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1291

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1636

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1709

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1724

uint32_t bios_0_scratch;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1822

uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

338

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

435

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

735

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_i2c.c

175

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/atombios_i2c.c

89

amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/amd/amdgpu/cik.c

1122

static uint32_t cik_get_register_value(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/cik.c

1127

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/cik.c

1221

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/cik.c

1456

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/cik.c

1852

static uint32_t cik_get_rev_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/cik.c

1888

uint32_t perfctr = 0;

sys/dev/pci/drm/amd/amdgpu/cik.c

957

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/cik_ih.c

254

uint32_t dw[4];

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1290

uint32_t byte_count,

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1291

uint32_t copy_flags)

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1313

uint32_t src_data,

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

1315

uint32_t byte_count)

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

199

static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

225

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

746

uint32_t incr)

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

776

uint32_t incr, uint64_t flags)

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

824

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/cik_sdma.c

866

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

34

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

38

adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

39

adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

40

adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

41

adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

42

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

43

adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

44

adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

45

adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

46

adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

47

adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

48

adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

49

adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

50

adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

51

adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

52

adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/cyan_skillfish_reg_init.c

53

adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/cz_ih.c

245

uint32_t dw[4];

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1476

static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1850

uint32_t fb_format, fb_pitch_pixels;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2278

uint32_t cur_lock;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2362

uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2363

uint32_t width,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2364

uint32_t height,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2463

u16 *blue, uint32_t size,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2689

uint32_t fb_format;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3268

uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3305

uint32_t disp_int, mask;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3513

uint32_t encoder_enum,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3514

uint32_t supported_device,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

76

static const uint32_t dig_offsets[] = {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

87

uint32_t reg;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

88

uint32_t vblank;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

89

uint32_t vline;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

90

uint32_t hpd;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

100

uint32_t vline;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

101

uint32_t hpd;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1478

uint32_t clock, int bpc)

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

1888

uint32_t fb_format, fb_pitch_pixels, pipe_config;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2251

uint32_t cur_lock;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2335

uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2336

uint32_t width,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2337

uint32_t height,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2435

u16 *blue, uint32_t size,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2656

uint32_t fb_format;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3085

uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3197

uint32_t disp_int, mask;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3411

uint32_t encoder_enum,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3412

uint32_t supported_device,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

87

static const uint32_t dig_offsets[] = {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

98

uint32_t reg;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

99

uint32_t vblank;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1457

static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1464

uint32_t offset = dig->afmt->offset;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1486

uint32_t offset = dig->afmt->offset;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1536

uint32_t offset, val;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1797

uint32_t fb_format, fb_pitch_pixels;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2199

uint32_t cur_lock;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2281

uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2282

uint32_t width,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2283

uint32_t height,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2382

u16 *blue, uint32_t size,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

2615

uint32_t fb_format;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3101

uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3213

uint32_t disp_int, mask;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3421

uint32_t encoder_enum,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3422

uint32_t supported_device,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

75

static const uint32_t dig_offsets[] = {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

86

uint32_t reg;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

87

uint32_t vblank;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

88

uint32_t vline;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

89

uint32_t hpd;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

119

static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

120

uint32_t lo_val, uint32_t hi_addr, uint32_t hi_val)

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

137

uint32_t lo_addr, uint32_t lo_val,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

138

uint32_t hi_addr, uint32_t hi_val)

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

141

uint32_t lo_val_rb, hi_val_rb;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

172

uint32_t lo_addr, uint32_t lo_val,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

173

uint32_t hi_addr, uint32_t hi_val)

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

363

uint32_t *lo_base_addr,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

364

uint32_t *hi_base_addr)

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

396

uint32_t *lo_base_addr,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

397

uint32_t *hi_base_addr)

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

407

uint32_t *lo_base_addr,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

408

uint32_t *hi_base_addr,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

409

uint32_t *lo_val,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

410

uint32_t *hi_val,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

414

uint32_t eventsel, instance, unitmask;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

415

uint32_t instance_10, instance_5432, instance_76;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

46

uint32_t ficaa_val)

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

49

uint32_t ficadl_val, ficadh_val;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

504

uint32_t lo_base_addr = 0, hi_base_addr = 0;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

519

uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

561

uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

600

uint32_t lo_base_addr = 0, hi_base_addr = 0, lo_val = 0, hi_val = 0;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

644

uint32_t hw_assert_msklo, hw_assert_mskhi;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

645

uint32_t v0, v1, v28, v31;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

69

static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

70

uint32_t ficadl_val, uint32_t ficadh_val)

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

97

uint32_t lo_addr, uint32_t *lo_val,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

98

uint32_t hi_addr, uint32_t *hi_val)

sys/dev/pci/drm/amd/amdgpu/df_v4_15.c

32

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/df_v4_15.c

33

uint32_t dis_lcl_proc = (1 << 1 |

sys/dev/pci/drm/amd/amdgpu/df_v4_3.c

31

uint32_t hw_assert_msklo, hw_assert_mskhi;

sys/dev/pci/drm/amd/amdgpu/df_v4_3.c

32

uint32_t v0, v1, v28, v31;

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

33

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

35

adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

36

adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

37

adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

38

adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

39

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

40

adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

41

adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

42

adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN0_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

43

adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

44

adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

45

adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

46

adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

47

adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

48

adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

49

adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

50

adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c

51

adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10178

uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10198

uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

10199

uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3700

uint16_t pasid, uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3731

uint32_t eng_sel = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3771

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3798

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3815

uint16_t pasid, uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3821

static void gfx_v10_0_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3822

uint32_t me_id, uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3823

uint32_t xcc_id, uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3827

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

3847

(uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4001

bool wc, uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4012

int mem_space, int opt, uint32_t addr0,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4013

uint32_t addr1, uint32_t ref, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4014

uint32_t inv)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4036

uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4037

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4078

uint32_t *cpu_ptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4477

static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4485

static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4486

uint32_t thread, uint32_t regno,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4487

uint32_t num, uint32_t *out)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4498

static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4526

static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4527

uint32_t wave, uint32_t start,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4528

uint32_t size, uint32_t *dst)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4537

static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4538

uint32_t wave, uint32_t thread,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4539

uint32_t start, uint32_t size,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4540

uint32_t *dst)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4556

uint32_t data, def;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4713

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4714

uint32_t *ptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4715

uint32_t inst;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4717

ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4730

ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

4743

ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5135

uint32_t num_sc;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5136

uint32_t enabled_rb_per_sh;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5137

uint32_t active_rb_bitmap;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5138

uint32_t num_rb_per_sc;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5139

uint32_t num_packer_per_sc;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5140

uint32_t pa_sc_tile_steering_override;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5175

uint32_t first_vmid,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5176

uint32_t last_vmid)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5178

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5179

uint32_t trap_config_vmid_mask = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5200

uint32_t sh_mem_bases;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5324

uint32_t tcc_disable;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5487

uint32_t rlc_pg_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5521

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5660

static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5662

uint32_t total_size = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5686

uint32_t total_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5716

uint32_t fw_size)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5718

uint32_t toc_offset;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5719

uint32_t toc_fw_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5743

uint32_t size;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5756

uint32_t fw_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5817

uint32_t fw_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5833

(uint32_t *)fw_data +

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5841

(uint32_t *)fw_data +

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5850

uint32_t rlc_g_offset, rlc_g_size, tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5883

uint32_t usec_timeout = 50000; /* wait for 50ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5884

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5920

uint32_t usec_timeout = 50000; /* wait for 50ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5921

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5957

uint32_t usec_timeout = 50000; /* wait for 50ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5958

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5994

uint32_t usec_timeout = 50000; /* wait for 50ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

5995

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6031

uint32_t cp_status;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6032

uint32_t bootload_status;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6107

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6108

uint32_t usec_timeout = 50000; /* wait for 50ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6185

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6186

uint32_t usec_timeout = 50000; /* wait for 50ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6262

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6263

uint32_t usec_timeout = 50000; /* wait for 50ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6717

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6767

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6768

uint32_t rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6911

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7283

uint32_t data, pattern = 0xDEADBEEF;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7327

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7464

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7762

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7763

uint32_t gds_base, uint32_t gds_size,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7764

uint32_t gws_base, uint32_t gws_size,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7765

uint32_t oa_base, uint32_t oa_size)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7856

uint32_t rlc_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7865

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7906

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7929

uint32_t data, def;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8003

uint32_t data, def;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8062

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8121

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8159

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8160

uint32_t reg_idx = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8161

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8163

const uint32_t tcp_ctrl_regs[] = {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8190

const uint32_t tcp_ctrl_regs_nv12[] = {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8213

const uint32_t sm_ctlr_regs[] = {

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8331

uint32_t offset,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8335

uint32_t reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8545

return *(uint32_t *)ring->rptr_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8584

return *(uint32_t *)ring->rptr_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8644

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8681

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8749

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8757

uint16_t pasid, uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8815

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8817

uint32_t dw2 = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8981

uint32_t v = secure ? FRAME_TMZ : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8987

static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

8988

uint32_t reg_val_offs)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9004

static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9005

uint32_t val)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9007

uint32_t cmd = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9027

static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9028

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9034

uint32_t reg0, uint32_t reg1,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9035

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9053

uint32_t me, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9056

uint32_t cp_int_cntl, cp_int_cntl_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9417

uint32_t tmp, target;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9497

static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9652

uint32_t i, j, k, reg, index = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9653

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9721

uint32_t i, j, k, reg, index = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

9722

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1019

static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1020

uint32_t wave, uint32_t start,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1021

uint32_t size, uint32_t *dst)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1030

static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1031

uint32_t wave, uint32_t thread,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1032

uint32_t start, uint32_t size,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1033

uint32_t *dst)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1215

static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1217

uint32_t total_size = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1236

uint32_t total_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1258

uint32_t fw_size,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1259

uint32_t *fw_autoload_mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1261

uint32_t toc_offset;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1262

uint32_t toc_fw_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1287

uint32_t *fw_autoload_mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1290

uint32_t size;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1308

uint32_t *fw_autoload_mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1311

uint32_t fw_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1435

uint32_t *fw_autoload_mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1438

uint32_t fw_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1459

uint32_t *fw_autoload_mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1496

uint32_t rlc_g_offset, rlc_g_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1498

uint32_t autoload_fw_id[2];

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1500

memset(autoload_fw_id, 0, sizeof(uint32_t) * 2);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1534

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1535

uint32_t *ptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1536

uint32_t inst;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1538

ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1551

ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

1564

ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2050

uint32_t sh_mem_bases;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2051

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2115

uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) |

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2266

uint32_t rlc_pg_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2298

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2489

uint32_t usec_timeout = 50000; /* wait for 50ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2490

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2533

uint32_t usec_timeout = 50000; /* wait for 50ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2534

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2577

uint32_t usec_timeout = 50000; /* wait for 50ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2578

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2621

uint32_t usec_timeout = 50000; /* wait for 50ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2622

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2743

uint32_t usec_timeout = 50000; /* wait for 50ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2744

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2866

uint32_t usec_timeout = 50000; /* wait for 50ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2867

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

2952

uint32_t pipe_id, tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3034

uint32_t cp_status;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3035

uint32_t bootload_status;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3185

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3186

uint32_t usec_timeout = 50000; /* wait for 50ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

336

static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

337

uint32_t val);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

340

uint16_t pasid, uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3403

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

3404

uint32_t usec_timeout = 50000; /* wait for 50ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

372

uint32_t me = 0, eng_sel = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4043

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4091

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4092

uint32_t rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

416

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4233

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

448

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

465

uint16_t pasid, uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

4729

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

511

bool wc, uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5190

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5191

uint32_t gds_base, uint32_t gds_size,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5192

uint32_t gws_base, uint32_t gws_size,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5193

uint32_t oa_base, uint32_t oa_size)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

522

int mem_space, int opt, uint32_t addr0,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

523

uint32_t addr1, uint32_t ref, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

524

uint32_t inv)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5292

uint32_t rlc_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5301

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5326

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5345

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5364

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5383

uint32_t data, def;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5418

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

543

static void gfx_v11_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

561

uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

562

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5762

return *(uint32_t *)ring->rptr_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5801

return *(uint32_t *)ring->rptr_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5862

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5896

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5964

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

5972

uint16_t pasid, uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6030

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6032

uint32_t dw2 = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

606

uint32_t *cpu_ptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6246

uint32_t v = secure ? FRAME_TMZ : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6252

static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6253

uint32_t reg_val_offs)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6269

static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6270

uint32_t val)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6272

uint32_t cmd = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6292

static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6293

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6299

uint32_t reg0, uint32_t reg1,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6300

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6310

uint32_t me, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6313

uint32_t cp_int_cntl, cp_int_cntl_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6697

uint32_t tmp, target;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6769

uint32_t reset_pipe = 0, clean_pipe = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

6861

uint32_t reset_pipe = 0, clean_pipe = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7021

uint32_t i, j, k, reg, index = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7022

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7090

uint32_t i, j, k, reg, index = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

7091

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0);

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

972

static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

980

static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

981

uint32_t thread, uint32_t regno,

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

982

uint32_t num, uint32_t *out)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c

993

static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0_3.c

38

uint32_t rlc_status0 = 0, rlc_status1 = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v11_0_3.c

89

uint32_t rlc_status0 = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1056

static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1058

uint32_t total_size = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1079

uint32_t total_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1100

uint32_t fw_size)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1102

uint32_t toc_offset;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1103

uint32_t toc_fw_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1128

uint32_t size;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1129

uint32_t *toc_ptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1134

toc_ptr = (uint32_t *)data + size / 4 - 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1145

uint32_t fw_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1257

uint32_t fw_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1306

uint32_t rlc_g_offset, rlc_g_size;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1308

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1351

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1352

uint32_t *ptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1353

uint32_t inst;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1355

ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1368

ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1381

ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1763

uint32_t sh_mem_bases;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1764

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1931

uint32_t rlc_pg_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

1963

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2108

uint32_t pipe_id, tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2294

uint32_t cp_status;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2295

uint32_t bootload_status;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2353

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2354

uint32_t usec_timeout = 50000; /* wait for 50ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2497

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2498

uint32_t usec_timeout = 50000; /* wait for 50ms */

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

281

static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

282

uint32_t val);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

285

uint16_t pasid, uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2938

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2968

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

2969

uint32_t rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

311

uint32_t me = 0, eng_sel = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3111

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

355

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3574

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3743

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

386

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3905

uint32_t rlc_cntl;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3915

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3941

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

3981

uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4036

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

404

uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4153

uint32_t data, def;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4187

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4208

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

429

int mem_space, int opt, uint32_t addr0,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

430

uint32_t addr1, uint32_t ref,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

431

uint32_t mask, uint32_t inv)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4317

return *(uint32_t *)ring->rptr_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4356

return *(uint32_t *)ring->rptr_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4417

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4440

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4490

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4498

uint16_t pasid, uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

453

uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

454

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4550

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4552

uint32_t dw2 = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4636

static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4637

uint32_t reg_val_offs)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4654

uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4655

uint32_t val)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4657

uint32_t cmd = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4677

static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4678

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4684

uint32_t reg0, uint32_t reg1,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4685

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4695

uint32_t me, uint32_t pipe,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

4698

uint32_t cp_int_cntl, cp_int_cntl_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

499

uint32_t *cpu_ptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5080

static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5105

uint32_t i, j, k, reg, index = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5106

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5169

uint32_t i, j, k, reg, index = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5170

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5242

uint32_t reset_pipe = 0, clean_pipe = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

5333

uint32_t reset_pipe = 0, clean_pipe = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

815

static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

823

static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

824

uint32_t thread, uint32_t regno,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

825

uint32_t num, uint32_t *out)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

837

uint32_t xcc_id,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

838

uint32_t simd, uint32_t wave,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

839

uint32_t *dst, int *no_fields)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

874

uint32_t xcc_id, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

875

uint32_t wave, uint32_t start,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

876

uint32_t size, uint32_t *dst)

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

886

uint32_t xcc_id, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

887

uint32_t wave, uint32_t thread,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

888

uint32_t start, uint32_t size,

sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c

889

uint32_t *dst)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1791

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1856

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

1899

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2289

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2342

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2933

static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2943

static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2953

static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2954

uint32_t wave, uint32_t thread,

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2955

uint32_t regno, uint32_t num, uint32_t *out)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2968

static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2993

static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2994

uint32_t wave, uint32_t start,

sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c

2995

uint32_t size, uint32_t *dst)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1000

uint32_t *tile, *macrotile;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1825

uint32_t sh_mem_config;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

1826

uint32_t sh_mem_bases;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2036

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2207

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2238

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2269

static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2271

uint32_t dw2 = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2304

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2945

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2946

uint32_t mqd_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2947

uint32_t *mqd_data;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3109

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3180

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3962

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3963

uint32_t gds_base, uint32_t gds_size,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3964

uint32_t gws_base, uint32_t gws_size,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

3965

uint32_t oa_base, uint32_t oa_size)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4003

uint32_t value = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4012

static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4022

static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4023

uint32_t wave, uint32_t thread,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4024

uint32_t regno, uint32_t num, uint32_t *out)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4037

static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4062

static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4063

uint32_t wave, uint32_t start,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4064

uint32_t size, uint32_t *dst)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

2066

uint32_t *modearray, *mod2array;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3651

uint32_t sh_mem_config;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3652

uint32_t sh_mem_bases;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

3988

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4294

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4404

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4549

uint32_t mqd_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4550

uint32_t *mqd_data;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5117

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5118

uint32_t gds_base, uint32_t gds_size,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5119

uint32_t gws_base, uint32_t gws_size,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5120

uint32_t oa_base, uint32_t oa_size)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5155

static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5165

static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5166

uint32_t wave, uint32_t thread,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5167

uint32_t regno, uint32_t num, uint32_t *out)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5180

static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5205

static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5206

uint32_t wave, uint32_t start,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5207

uint32_t size, uint32_t *dst)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5442

uint32_t reg_addr, uint32_t cmd)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5444

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5491

uint32_t rlc_setting;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5502

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5529

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5584

uint32_t temp, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5684

uint32_t temp, temp1, data, data1;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5795

uint32_t msg_id, pp_state = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5796

uint32_t pp_support_state = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5845

uint32_t msg_id, pp_state = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

5846

uint32_t pp_support_state = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6046

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6078

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6151

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6257

static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6259

uint32_t dw2 = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6306

static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6307

uint32_t reg_val_offs)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6323

static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6324

uint32_t val)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6326

uint32_t cmd;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6350

uint32_t value = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6767

uint32_t pipe, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6769

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6770

uint32_t wcl_cs_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

6800

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

738

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

841

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

876

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1014

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1032

uint16_t pasid, uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1044

static void gfx_v9_0_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1045

uint32_t me_id, uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1046

uint32_t xcc_id, uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1161

bool wc, uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1173

int mem_space, int opt, uint32_t addr0,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1174

uint32_t addr1, uint32_t ref, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1175

uint32_t inv)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1197

uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1198

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1232

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1496

uint32_t smu_version;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1668

uint32_t pg_always_on_cu_num = 2;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1669

uint32_t always_on_cu_num;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1670

uint32_t i, j, k;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1671

uint32_t mask, cu_bitmap, counter;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1711

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1760

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1929

static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1939

static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1940

uint32_t wave, uint32_t thread,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1941

uint32_t regno, uint32_t num, uint32_t *out)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1954

static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1975

static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1976

uint32_t wave, uint32_t start,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1977

uint32_t size, uint32_t *dst)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1984

static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1985

uint32_t wave, uint32_t thread,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1986

uint32_t start, uint32_t size,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

1987

uint32_t *dst)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2186

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2187

uint32_t *ptr;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2188

uint32_t inst;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2190

ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2203

ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2562

uint32_t first_vmid,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2563

uint32_t last_vmid)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2565

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2566

uint32_t trap_config_vmid_mask = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2588

uint32_t sh_mem_config;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2589

uint32_t sh_mem_bases;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2643

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2928

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2929

uint32_t default_data = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2953

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2996

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

2997

uint32_t default_data = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3010

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3011

uint32_t default_data = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3024

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3025

uint32_t default_data = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3038

uint32_t data, default_data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3051

uint32_t data, default_data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3068

uint32_t data, default_data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3081

uint32_t data, default_data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3522

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3550

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4199

uint32_t seq, reg_val_offs = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4309

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4310

uint32_t gds_base, uint32_t gds_size,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4311

uint32_t gws_base, uint32_t gws_size,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4312

uint32_t oa_base, uint32_t oa_size)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4885

uint32_t rlc_setting;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4897

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4914

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

4960

uint32_t data, def;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5031

uint32_t data, def;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5082

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5184

uint32_t offset,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5188

uint32_t reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5410

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5511

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5550

uint32_t dw2 = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5587

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5803

uint32_t v = secure ? FRAME_TMZ : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5809

static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5811

uint32_t dw2 = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5857

static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5858

uint32_t reg_val_offs)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5874

static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5875

uint32_t val)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5877

uint32_t cmd = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5897

static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5898

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5904

uint32_t reg0, uint32_t reg1,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5905

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5923

uint32_t value = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6733

void *inject_if, uint32_t instance_mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6852

uint32_t i, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6853

uint32_t sec_count, ded_count;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6948

uint32_t se_id, uint32_t inst_id, uint32_t value,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6949

uint32_t *sec_count, uint32_t *ded_count)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6951

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

6952

uint32_t sec_cnt, ded_cnt;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7047

uint32_t sec_count = 0, ded_count = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7048

uint32_t i, j, k;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7049

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7103

uint32_t pipe, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7106

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7107

uint32_t wcl_cs_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7136

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7161

static void gfx_v9_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7252

uint32_t i, j, k, reg, index = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7253

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7297

uint32_t i, j, k, reg, index = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

7298

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

920

void *inject_if, uint32_t instance_mask);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

956

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

986

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

691

uint32_t i, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

692

uint32_t sec_count, ded_count;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

828

uint32_t se_id, uint32_t inst_id,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

829

uint32_t value, uint32_t *sec_count,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

830

uint32_t *ded_count)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

832

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

833

uint32_t sec_cnt, ded_cnt;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

869

uint32_t sec_count = 0, ded_count = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

870

uint32_t i, j, k;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

871

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

978

uint32_t i, j;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c

979

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1464

uint32_t se_id, uint32_t inst_id,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1465

uint32_t value, uint32_t *sec_count,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1466

uint32_t *ded_count)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1468

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1469

uint32_t sec_cnt, ded_cnt;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1502

uint32_t *sec_count, uint32_t *ded_count)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1504

uint32_t i, j, k, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1505

uint32_t sec_cnt = 0, ded_cnt = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1557

uint32_t instance, uint32_t sec_cnt,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1558

uint32_t ded_cnt)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1560

uint32_t bank, way, mem;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1607

uint32_t *sec_count,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1608

uint32_t *ded_count)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1610

uint32_t i, j, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1611

uint32_t sec_cnt, ded_cnt;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1612

uint32_t num_instances;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1661

uint32_t sec_count = 0, ded_count = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1688

uint32_t i, j;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1689

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1717

uint32_t i, j;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1718

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1748

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1791

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1792

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1816

static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1827

uint32_t status)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1830

uint32_t i, simd, wave;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1831

uint32_t wave_status;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1832

uint32_t wave_pc_lo, wave_pc_hi;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1833

uint32_t wave_exec_lo, wave_exec_hi;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1834

uint32_t wave_inst_dw0, wave_inst_dw1;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1835

uint32_t wave_ib_sts;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1870

uint32_t se_idx, sh_idx, cu_idx;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1871

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

1904

uint32_t se_idx, sh_idx, cu_idx;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

355

uint32_t total_size, shader_offset;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

420

static void gfx_v9_4_2_log_wave_assignment(struct amdgpu_device *adev, uint32_t *wb_ptr)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

422

uint32_t se, cu, simd, wave;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

423

uint32_t offset = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

453

uint32_t *wb_ptr, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

454

uint32_t pattern, uint32_t num_wave, bool wait)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

456

uint32_t se, cu, simd, wave;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

457

uint32_t loop = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

458

uint32_t wave_cnt;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

459

uint32_t offset;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

507

r = amdgpu_ib_get(adev, NULL, (1 + wb_size) * sizeof(uint32_t),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

51

uint32_t num_banks;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

513

memset(wb_ib.ptr, 0, (1 + wb_size) * sizeof(uint32_t));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

52

uint32_t num_ways;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

53

uint32_t num_mem_blocks;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

56

uint32_t sec_count_mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

57

uint32_t sec_count_shift;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

579

memset(wb_ib.ptr, 0, (1 + wb_size) * sizeof(uint32_t));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

58

uint32_t ded_count_mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

59

uint32_t ded_count_shift;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

60

uint32_t clear;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

650

r = amdgpu_ib_get(adev, NULL, (1 + wb_size) * sizeof(uint32_t),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

656

memset(wb_ib.ptr, 0, (1 + wb_size) * sizeof(uint32_t));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

725

uint32_t die_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

753

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

764

uint32_t first_vmid,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

765

uint32_t last_vmid)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c

767

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.h

28

uint32_t first_vmid, uint32_t last_vmid);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.h

30

uint32_t die_id);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1011

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1012

uint32_t *ptr, num_xcc, inst;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1016

ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1029

ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1219

uint32_t sh_mem_config;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1220

uint32_t sh_mem_bases;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1221

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1286

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1390

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1399

uint32_t rlc_setting;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1411

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1429

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1697

uint32_t offset,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1701

uint32_t reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1802

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

1830

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

205

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

235

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2487

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2488

uint32_t gds_base, uint32_t gds_size,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2489

uint32_t gws_base, uint32_t gws_size,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2490

uint32_t oa_base, uint32_t oa_size)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2560

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2582

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2604

uint32_t data, def;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

262

uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2669

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

280

uint16_t pasid, uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2852

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

291

static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

292

uint32_t me_id, uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2921

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

293

uint32_t xcc_id, uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2992

static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2993

uint32_t reg_val_offs)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3011

static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3012

uint32_t val)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3014

uint32_t cmd = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3036

static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3037

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3043

uint32_t reg0, uint32_t reg1,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3044

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3054

uint32_t value = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3413

uint32_t pipe, bool enable)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3416

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3417

uint32_t wcl_cs_reg;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3446

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3470

static int gfx_v9_4_3_unmap_done(struct amdgpu_device *adev, uint32_t me,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3471

uint32_t pipe, uint32_t queue,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3472

uint32_t xcc_id)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

3509

uint32_t reset_pipe, clean_pipe;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

361

static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

363

uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

376

bool wc, uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

389

int mem_space, int opt, uint32_t addr0,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

390

uint32_t addr1, uint32_t ref, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

391

uint32_t inv)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

418

uint32_t scratch_reg0_offset, xcc_offset;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

420

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4390

uint32_t i, j, k;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4464

uint32_t i, j, k;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4514

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4515

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4560

static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4578

uint32_t i, j, k;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4579

uint32_t xcc_id, xcc_offset, inst_offset;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4580

uint32_t num_xcc, reg, num_inst;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4581

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

459

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4647

uint32_t i, j, k;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4648

uint32_t num_xcc, reg, num_inst;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4649

uint32_t xcc_id, xcc_offset, inst_offset;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4650

uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4986

static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

4989

uint32_t tmp_mask;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

5018

static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

716

static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

726

static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

727

uint32_t wave, uint32_t thread,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

728

uint32_t regno, uint32_t num, uint32_t *out)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

742

uint32_t xcc_id, uint32_t simd, uint32_t wave,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

743

uint32_t *dst, int *no_fields)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

764

static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

765

uint32_t wave, uint32_t start,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

766

uint32_t size, uint32_t *dst)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

772

static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

773

uint32_t wave, uint32_t thread,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

774

uint32_t start, uint32_t size,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

775

uint32_t *dst)

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

976

uint32_t xcc_doorbell_start;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

124

static void gfxhub_v11_5_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

189

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

209

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

260

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

297

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

59

static uint32_t gfxhub_v11_5_0_get_invalidate_req(unsigned int vmid,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

60

uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c

81

uint32_t status)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

127

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

194

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

214

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

265

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

302

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

61

static uint32_t gfxhub_v12_0_get_invalidate_req(unsigned int vmid,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

62

uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c

83

uint32_t status)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

156

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

176

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

220

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

254

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c

40

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

127

uint32_t xcc_mask)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

130

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

197

uint32_t xcc_mask)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

199

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

223

uint32_t xcc_mask)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

225

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

272

uint32_t xcc_mask)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

274

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

292

uint32_t xcc_mask)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

329

uint32_t xcc_mask)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

333

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

401

uint32_t xcc_mask)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

419

uint32_t xcc_mask)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

43

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

439

uint32_t xcc_mask;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

446

uint32_t xcc_mask)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

45

uint32_t xcc_mask)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

480

uint32_t xcc_mask;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

488

uint32_t xcc_mask)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

538

uint32_t xcc_mask;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

544

static void gfxhub_v1_2_xcc_init(struct amdgpu_device *adev, uint32_t xcc_mask)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

587

uint32_t xcc_mask;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

643

static int gfxhub_v1_2_xcp_resume(void *handle, uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

65

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

661

static int gfxhub_v1_2_xcp_suspend(void *handle, uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

68

uint32_t xcc_mask;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c

75

uint32_t xcc_mask)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

120

static void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

188

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

207

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

256

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

287

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

55

static uint32_t gfxhub_v2_0_get_invalidate_req(unsigned int vmid,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

56

uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c

77

uint32_t status)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

123

static void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

192

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

211

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

262

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

299

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

58

static uint32_t gfxhub_v2_1_get_invalidate_req(unsigned int vmid,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

59

uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

625

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c

80

uint32_t status)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

119

static void gfxhub_v3_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

186

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

206

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

257

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

294

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

54

static uint32_t gfxhub_v3_0_get_invalidate_req(unsigned int vmid,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

55

uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c

76

uint32_t status)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

122

static void gfxhub_v3_0_3_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

191

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

211

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

262

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

299

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

57

static uint32_t gfxhub_v3_0_3_get_invalidate_req(unsigned int vmid,

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

58

uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c

79

uint32_t status)

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

103

uint32_t vmhub_index = entry->client_id == SOC15_IH_CLIENTID_VMC ?

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

109

uint32_t status = 0;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

214

uint32_t vmhub)

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

224

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

250

static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

251

uint32_t vmhub, uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

348

uint16_t pasid, uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

349

bool all_hub, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

379

uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

426

uint32_t reg;

sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c

495

uint32_t vm_flags,

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

103

uint32_t vmhub_index = entry->client_id == SOC21_IH_CLIENTID_VMC ?

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

108

uint32_t status = 0;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

210

uint32_t vmhub)

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

235

static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

236

uint32_t vmhub, uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

340

uint16_t pasid, uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

341

bool all_hub, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

371

uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

418

uint32_t reg;

sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c

486

uint32_t vm_flags,

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

203

uint32_t vmhub)

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

225

static void gmc_v12_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

226

unsigned int vmhub, uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

317

static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

318

uint32_t vmhub, uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

360

uint16_t pasid, uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

361

bool all_hub, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

407

uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

454

uint32_t reg;

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

524

uint32_t vm_flags,

sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c

96

uint32_t status = 0;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

354

static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

355

uint32_t vmhub, uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

363

uint32_t reg;

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

387

uint32_t vm_flags,

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

446

uint32_t low = AMDGPU_VA_RESERVED_BOTTOM >>

sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c

448

uint32_t high = adev->vm_manager.max_pfn -

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

435

uint16_t pasid, uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

436

bool all_hub, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

470

static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

471

uint32_t vmhub, uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

480

uint32_t reg;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

509

uint32_t vm_flags,

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

551

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

576

uint32_t low = AMDGPU_VA_RESERVED_BOTTOM >>

sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c

578

uint32_t high = adev->vm_manager.max_pfn -

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1506

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

1586

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

626

uint16_t pasid, uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

627

bool all_hub, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

661

static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

662

uint32_t vmhub, uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

671

uint32_t reg;

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

721

uint32_t vm_flags,

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

793

uint32_t low = AMDGPU_VA_RESERVED_BOTTOM >>

sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c

795

uint32_t high = adev->vm_manager.max_pfn -

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1037

uint32_t reg;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1112

uint32_t vm_flags,

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1123

uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0);

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1228

uint32_t vm_flags,

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

1550

uint32_t supp_modes;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

342

static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

377

static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

549

uint32_t status = 0, cid = 0, rw = 0, fed = 0;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

556

uint32_t cam_index = 0;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

558

uint32_t node_id;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

771

static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

772

uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

798

uint32_t vmhub)

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

814

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

840

static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

841

uint32_t vmhub, uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

866

uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

867

uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

957

uint16_t pasid, uint32_t flush_type,

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

958

bool all_hub, uint32_t inst)

sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c

990

uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);

sys/dev/pci/drm/amd/amdgpu/hdp_v4_0.c

86

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

139

uint32_t hdp_clk_cntl;

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

148

~(uint32_t)

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

177

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

45

uint32_t hdp_clk_cntl, hdp_clk_cntl1;

sys/dev/pci/drm/amd/amdgpu/hdp_v5_0.c

46

uint32_t hdp_mem_pwr_cntl;

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

142

uint32_t hdp_clk_cntl;

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

151

~(uint32_t)

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

173

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

57

uint32_t hdp_clk_cntl;

sys/dev/pci/drm/amd/amdgpu/hdp_v5_2.c

58

uint32_t hdp_mem_pwr_cntl;

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

128

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

36

uint32_t hdp_clk_cntl;

sys/dev/pci/drm/amd/amdgpu/hdp_v6_0.c

37

uint32_t hdp_mem_pwr_cntl;

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

116

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

33

uint32_t hdp_clk_cntl, hdp_clk_cntl1;

sys/dev/pci/drm/amd/amdgpu/hdp_v7_0.c

34

uint32_t hdp_mem_pwr_cntl;

sys/dev/pci/drm/amd/amdgpu/iceland_ih.c

244

uint32_t dw[4];

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

132

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

215

static uint32_t ih_v6_0_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

238

static uint32_t ih_v6_0_doorbell_rptr(struct amdgpu_ih_ring *ih)

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

269

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

488

uint32_t v = 0;

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

489

uint32_t i = 0;

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

543

uint32_t wptr = cpu_to_le32(entry->src_data[0]);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

679

uint32_t data, def, field_val;

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

712

uint32_t ih_mem_pwr_cntl;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

132

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

187

static uint32_t ih_v6_1_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

210

static uint32_t ih_v6_1_doorbell_rptr(struct amdgpu_ih_ring *ih)

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

241

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

457

uint32_t v = 0;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

458

uint32_t i = 0;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

512

uint32_t wptr = cpu_to_le32(entry->src_data[0]);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

654

uint32_t data, def, field_val;

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

689

uint32_t ih_mem_pwr_cntl;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

132

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

187

static uint32_t ih_v7_0_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

210

static uint32_t ih_v7_0_doorbell_rptr(struct amdgpu_ih_ring *ih)

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

241

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

456

uint32_t v = 0;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

457

uint32_t i = 0;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

509

uint32_t wptr = cpu_to_le32(entry->src_data[0]);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

644

uint32_t data, def, field_val;

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

679

uint32_t ih_mem_pwr_cntl;

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

300

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

354

uint32_t reg, uint32_t val,

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

355

uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

358

uint32_t reg_offset = (reg << 2);

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

387

uint32_t data0, data1, mask;

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

399

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

402

uint32_t reg_offset = (reg << 2);

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

419

static void jpeg_v1_0_decode_ring_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

42

static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

57

static void jpeg_v1_0_decode_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr)

sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c

61

uint32_t reg, reg_offset, val, mask, i;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

231

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

258

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

284

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

307

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

557

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

613

void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

614

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

616

uint32_t reg_offset = (reg << 2);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

644

uint32_t data0, data1, mask;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

655

void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

657

uint32_t reg_offset = (reg << 2);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c

673

void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.h

53

struct amdgpu_ib *ib, uint32_t flags);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.h

54

void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.h

55

uint32_t val, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.h

58

void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.h

59

void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count);

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

301

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

330

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

620

uint32_t ip_instance;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

812

static uint32_t jpeg_v2_6_query_poison_by_instance(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

813

uint32_t instance, uint32_t sub_block)

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

815

uint32_t poison_stat = 0, reg_value = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c

839

uint32_t inst = 0, sub = 0, poison_stat = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

246

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

276

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

290

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c

325

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

278

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

302

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

327

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

362

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

437

uint32_t param, resp, expected;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

438

uint32_t tmp, timeout;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

441

uint32_t *table_loc;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

442

uint32_t table_size;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

443

uint32_t size, size_dw;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

444

uint32_t init_status;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

457

table_loc = (uint32_t *)table->cpu_addr;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

467

table_loc = (uint32_t *)table->cpu_addr;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

494

table_loc = (uint32_t *)table->cpu_addr;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

821

static uint32_t jpeg_v4_0_query_poison_by_instance(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

822

uint32_t instance, uint32_t sub_block)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

824

uint32_t poison_stat = 0, reg_value = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c

848

uint32_t inst = 0, sub = 0, poison_stat = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1069

uint32_t i, inst;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1289

uint32_t jpeg_inst,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1306

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1318

uint32_t jpeg_inst)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1328

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1339

static uint32_t jpeg_v4_0_3_query_poison_by_instance(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1340

uint32_t instance, uint32_t sub_block)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1342

uint32_t poison_stat = 0, reg_value = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

1366

uint32_t inst = 0, sub = 0, poison_stat = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

255

uint32_t param, resp, expected;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

256

uint32_t tmp, timeout;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

259

uint32_t *table_loc;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

260

uint32_t table_size;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

261

uint32_t size, size_dw, item_offset;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

262

uint32_t init_status;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

282

table_loc = (uint32_t *)table->cpu_addr;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

315

table_loc = (uint32_t *)table->cpu_addr;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

496

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

521

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

834

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

886

void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

887

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

889

uint32_t reg_offset;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

923

uint32_t data0, data1, mask;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

934

void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

936

uint32_t reg_offset;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c

958

void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.h

61

uint32_t flags);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.h

67

void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.h

70

void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.h

71

void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.h

72

uint32_t val, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

309

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

333

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

358

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

424

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

446

(uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

486

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c

738

uint32_t ip_instance;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

242

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

254

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

271

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

306

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

344

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

355

(uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c

411

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

453

uint32_t param, resp, expected;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

454

uint32_t tmp, timeout;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

457

uint32_t *table_loc;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

458

uint32_t table_size;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

459

uint32_t size, size_dw, item_offset;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

460

uint32_t init_status;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

480

table_loc = (uint32_t *)table->cpu_addr;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

513

table_loc = (uint32_t *)table->cpu_addr;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

955

static uint32_t jpeg_v5_0_1_query_poison_by_instance(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

956

uint32_t instance, uint32_t sub_block)

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

958

uint32_t poison_stat = 0, reg_value = 0;

sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c

982

uint32_t inst = 0, sub = 0, poison_stat = 0;

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

107

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

45

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

74

uint32_t data,

sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c

78

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

107

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

45

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

74

uint32_t data,

sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c

78

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mca_v3_0.c

41

enum amdgpu_ras_block block, uint32_t sub_block_index)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1011

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1108

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1212

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1509

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1544

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

1556

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

316

uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

387

static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

388

uint32_t me_id, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

389

uint32_t queue_id, uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

392

uint32_t value, reg;

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

405

(uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));

sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c

946

uint32_t pipe, data = 0;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1086

uint32_t pipe, data = 0;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1181

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1270

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1379

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1690

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

1726

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

309

uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

412

static int mes_v12_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

413

uint32_t me_id, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

414

uint32_t queue_id, uint32_t vmid)

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

417

uint32_t value, reg;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

430

(uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

730

uint32_t mes_rev = (pipe == AMDGPU_MES_SCHED_PIPE) ?

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

807

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c

863

uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL);

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

139

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

159

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

201

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

235

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

282

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

501

uint32_t def, data, def1, data1, def2 = 0, data2 = 0;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

54

static void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

564

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

759

uint32_t value, uint32_t *sec_count, uint32_t *ded_count)

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

761

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

762

uint32_t sec_cnt, ded_cnt;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

798

uint32_t sec_count = 0, ded_count = 0;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

799

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

800

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

820

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c

88

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

107

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

1233

uint32_t value,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

1234

uint32_t *sec_count,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

1235

uint32_t *ded_count)

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

1237

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

1238

uint32_t sec_cnt, ded_cnt;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

1272

uint32_t sec_count = 0, ded_count = 0;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

1273

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

1274

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

1293

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

1314

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

1334

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

157

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

178

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

180

uint32_t distance = regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE -

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

201

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

252

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

290

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

484

uint32_t def, data, def1, data1, def2 = 0, data2 = 0;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

538

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c

54

static void mmhub_v1_7_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

132

uint32_t tmp, inst_mask;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

195

uint32_t tmp, inst_mask;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

239

uint32_t tmp, inst_mask;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

241

uint32_t distance = regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE -

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

267

uint32_t tmp, inst_mask;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

328

uint32_t tmp, inst_mask;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

381

uint32_t tmp, inst_mask;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

55

static void mmhub_v1_8_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

692

uint32_t mmhub_inst,

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

729

uint32_t inst_mask;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

730

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

743

uint32_t mmhub_inst)

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

757

uint32_t inst_mask;

sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c

758

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

119

static uint32_t mmhub_v2_0_get_invalidate_req(unsigned int vmid,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

120

uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

141

uint32_t status)

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

143

uint32_t cid, rw;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

190

static void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

224

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

260

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

279

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

330

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

370

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

569

uint32_t def, data, def1, data1;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c

626

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

122

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

154

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

188

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

207

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

252

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

286

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

496

uint32_t def, data, def1, data1;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

530

uint32_t def, data, def1, data1, def2, data2;

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

58

static uint32_t mmhub_v2_3_get_invalidate_req(unsigned int vmid,

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

59

uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

80

uint32_t status)

sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c

82

uint32_t cid, rw;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

137

static void mmhub_v3_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

171

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

213

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

233

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

284

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

324

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

546

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

548

uint32_t def1, data1, def2 = 0, data2 = 0;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

607

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

75

static uint32_t mmhub_v3_0_get_invalidate_req(unsigned int vmid,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

76

uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

97

uint32_t status)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c

99

uint32_t cid, rw;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

104

uint32_t status)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

106

uint32_t cid, rw;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

146

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

180

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

219

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

239

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

284

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

318

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

528

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

544

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

82

static uint32_t mmhub_v3_0_1_get_invalidate_req(unsigned int vmid,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c

83

uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

130

static void mmhub_v3_0_2_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

164

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

205

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

225

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

276

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

316

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

75

static uint32_t mmhub_v3_0_2_get_invalidate_req(unsigned int vmid,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

76

uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

97

uint32_t status)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c

99

uint32_t cid, rw;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

166

static uint32_t mmhub_v3_3_get_invalidate_req(unsigned int vmid,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

167

uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

188

uint32_t status)

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

190

uint32_t cid, rw;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

237

uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

272

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

311

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

331

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

376

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

411

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

473

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

676

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c

692

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

130

uint32_t vmid, uint64_t page_table_base)

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

163

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

206

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

226

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

277

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

317

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

542

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

544

uint32_t def1, data1, def2 = 0, data2 = 0;

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

587

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

67

static uint32_t mmhub_v4_1_0_get_invalidate_req(unsigned int vmid,

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

68

uint32_t flush_type)

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

90

uint32_t status)

sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c

92

uint32_t cid, rw;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

100

static void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

114

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

1594

uint32_t value,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

1595

uint32_t *sec_count,

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

1596

uint32_t *ded_count)

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

1598

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

1599

uint32_t sec_cnt, ded_cnt;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

1633

uint32_t sec_count = 0, ded_count = 0;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

1634

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

1635

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

1654

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

1677

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

177

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

204

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

206

uint32_t distance = mmDAGB1_WRCLI_GPU_SNOOP_OVERRIDE -

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

208

uint32_t huboffset = hubid * MMHUB_INSTANCE_REGISTER_OFFSET;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

233

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

288

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

329

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

58

uint32_t vmid, uint64_t value)

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

593

uint32_t def, data, def1, data1;

sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c

650

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

100

uint32_t value)

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

108

uint32_t *init_table,

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

109

uint32_t reg_offset,

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

110

uint32_t mask, uint32_t data)

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

120

uint32_t *init_table,

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

121

uint32_t reg_offset,

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

122

uint32_t mask, uint32_t wait)

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

38

uint32_t version;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

39

uint32_t header_size;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

40

uint32_t vce_init_status;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

41

uint32_t uvd_init_status;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

42

uint32_t vce_table_offset;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

43

uint32_t vce_table_size;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

44

uint32_t uvd_table_offset;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

45

uint32_t uvd_table_size;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

49

uint32_t init_status;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

50

uint32_t table_offset;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

51

uint32_t table_size;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

55

uint32_t version;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

56

uint32_t total_size;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

61

uint32_t reg_offset : 28;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

62

uint32_t command_type : 4;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

66

uint32_t reg_offset : 20;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

67

uint32_t reg_idx_space : 8;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

68

uint32_t command_type : 4;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

73

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

78

uint32_t write_data;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

79

uint32_t mask_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

84

uint32_t mask_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

85

uint32_t wait_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

94

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

98

uint32_t *init_table,

sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h

99

uint32_t reg_offset,

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

237

uint32_t version;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

238

uint32_t header_size;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

239

uint32_t vcn_init_status;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

240

uint32_t vcn_table_offset;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

241

uint32_t vcn_table_size;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

245

uint32_t reg_offset : 28;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

246

uint32_t command_type : 4;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

250

uint32_t reg_offset : 20;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

251

uint32_t reg_idx_space : 8;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

252

uint32_t command_type : 4;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

257

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

262

uint32_t write_data;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

263

uint32_t mask_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

268

uint32_t mask_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

269

uint32_t wait_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

278

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

282

uint32_t *init_table,

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

283

uint32_t reg_offset,

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

284

uint32_t value)

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

292

uint32_t *init_table,

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

293

uint32_t reg_offset,

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

294

uint32_t mask, uint32_t data)

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

304

uint32_t *init_table,

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

305

uint32_t reg_offset,

sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h

306

uint32_t mask, uint32_t wait)

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

44

uint32_t init_status;

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

45

uint32_t table_offset;

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

46

uint32_t table_size;

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

50

uint32_t version;

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

51

uint32_t total_size;

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

56

uint32_t reg_offset : 28;

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

57

uint32_t command_type : 4;

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

61

uint32_t reg_offset : 20;

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

62

uint32_t reg_idx_space : 8;

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

63

uint32_t command_type : 4;

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

68

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

73

uint32_t write_data;

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

74

uint32_t mask_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

79

uint32_t mask_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

80

uint32_t wait_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h

89

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

101

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

55

uint32_t init_status;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

56

uint32_t table_offset;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

57

uint32_t table_size;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

61

uint32_t version;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

62

uint32_t total_size;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

68

uint32_t reg_offset : 28;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

69

uint32_t command_type : 4;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

73

uint32_t reg_offset : 20;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

74

uint32_t reg_idx_space : 8;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

75

uint32_t command_type : 4;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

80

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

85

uint32_t write_data;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

86

uint32_t mask_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

91

uint32_t mask_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h

92

uint32_t wait_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0_3.h

31

uint32_t version;

sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0_3.h

32

uint32_t total_size;

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

100

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

53

uint32_t init_status;

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

54

uint32_t table_offset;

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

55

uint32_t table_size;

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

59

uint32_t version;

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

60

uint32_t total_size;

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

67

uint32_t reg_offset : 28;

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

68

uint32_t command_type : 4;

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

72

uint32_t reg_offset : 20;

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

73

uint32_t reg_idx_space : 8;

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

74

uint32_t command_type : 4;

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

79

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

84

uint32_t write_data;

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

85

uint32_t mask_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

90

uint32_t mask_value;

sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h

91

uint32_t wait_value;

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

549

uint32_t vf_rptr_hi, vf_rptr_lo;

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

551

vf_rptr_hi = (uint32_t)(vf_rptr >> 32);

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

552

vf_rptr_lo = (uint32_t)(vf_rptr & 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

564

uint32_t addr_hi, addr_lo;

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

566

addr_hi = (uint32_t)(addr >> 32);

sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c

567

addr_lo = (uint32_t)(addr & 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

157

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

213

static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

236

static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

267

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

464

uint32_t v = 0;

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

465

uint32_t i = 0;

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

649

uint32_t data, def, field_val;

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

297

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

317

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

347

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

487

uint32_t bif_doorbell_int_cntl;

sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c

517

uint32_t bif_doorbell_int_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

231

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

260

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

333

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

350

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

382

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

406

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

496

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

497

uint32_t link_width = 0;

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

521

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c

533

uint32_t reg, reg_data;

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

241

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

270

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

341

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

362

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

389

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

567

uint32_t bif_doorbell_int_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c

597

uint32_t bif_doorbell_int_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

166

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

194

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

264

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

283

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c

307

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

130

static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

132

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

140

static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset,

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

141

uint32_t data)

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

150

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

189

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c

278

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

266

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

291

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

320

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c

350

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

236

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

262

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c

370

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

257

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

343

uint32_t baco_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

361

uint32_t bif_doorbell_intr_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

424

uint32_t bif_doorbell_intr_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

457

uint32_t bif_intr_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

502

uint32_t bif_intr_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

589

uint32_t global_sts, central_sts, int_eoi, parity_sts;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

590

uint32_t corr, fatal, non_fatal;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

678

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c

702

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

238

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

260

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

289

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c

319

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

518

uint32_t bif_doorbell_intr_cntl;

sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c

570

uint32_t bif_doorbell_intr_cntl;

sys/dev/pci/drm/amd/amdgpu/nv.c

357

static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/nv.c

360

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/nv.c

374

static uint32_t nv_get_register_value(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/nv.c

390

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

131

uint32_t app_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

132

uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binary */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

133

uint32_t app_len; /* length of the TA binary in bytes */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

134

uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

135

uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

136

uint32_t cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

148

uint32_t session_id; /* Session ID of the loaded TA to be unloaded */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

157

uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

158

uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

159

uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

171

uint32_t num_desc; /* number of buffer descriptors in the list */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

172

uint32_t total_size; /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

181

uint32_t session_id; /* Session ID of the TA to be executed */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

182

uint32_t ta_cmd_id; /* Command ID to be sent to TA */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

191

uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

192

uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

193

uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

196

uint32_t sriov_enabled:1; /* whether the device runs under SR-IOV*/

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

197

uint32_t virt_phy_addr:1; /* driver passes both virtual and physical address to PSP*/

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

198

uint32_t reserved:30;

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

200

uint32_t tmr_flags;

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

202

uint32_t system_phy_addr_lo; /* bits [31:0] of system physical address of TMR buffer (must be 4 KB aligned) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

203

uint32_t system_phy_addr_hi; /* bits [63:32] of system physical address of TMR buffer */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

313

uint32_t fw_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

314

uint32_t fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

315

uint32_t fw_size; /* FW buffer size in bytes */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

323

uint32_t save_fw; /* if set, command is used for saving fw otherwise for resetoring*/

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

324

uint32_t save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

325

uint32_t save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as save/restore buffer */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

326

uint32_t buf_size; /* Size of the save/restore buffer in bytes */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

332

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

333

uint32_t reg_id;

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

339

uint32_t toc_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

340

uint32_t toc_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

341

uint32_t toc_size; /* FW buffer size in bytes */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

347

uint32_t timestamp; /* calendar time as number of seconds */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

349

uint32_t boot_config; /* dynamic boot configuration bitmask */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

350

uint32_t boot_config_valid; /* dynamic boot configuration valid bits bitmask */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

354

uint32_t mode;

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

355

uint32_t override_ips;

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

356

uint32_t override_xcds_avail;

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

357

uint32_t override_this_aid;

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

362

uint32_t gfx_xcp_mask;

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

370

uint32_t mode; /* requested NPS mode */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

371

uint32_t resvd;

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

394

uint32_t reserved[8];

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

400

uint32_t fwar_db_addr_lo;

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

401

uint32_t fwar_db_addr_hi;

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

406

uint32_t boot_cfg; /* boot config data */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

411

uint32_t reserve_base_address_hi;

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

412

uint32_t reserve_base_address_lo;

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

413

uint32_t reserve_size;

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

430

uint32_t status; /* +0 status of command execution */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

431

uint32_t session_id; /* +4 session ID in response to LoadTa command */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

432

uint32_t fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

433

uint32_t fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

434

uint32_t tmr_size; /* +16 size of the TMR to be reserved including MM fw and Gfx fw in response to cmd_load_toc command */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

436

uint32_t reserved[11];

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

448

uint32_t buf_size; /* +0 total size of the buffer in bytes */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

449

uint32_t buf_version; /* +4 version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

450

uint32_t cmd_id; /* +8 command ID */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

454

uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

455

uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

456

uint32_t resp_offset; /* +20 offset within response buffer */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

457

uint32_t resp_buf_size; /* +24 total size of the response buffer in bytes */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

479

uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

480

uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

481

uint32_t cmd_buf_size; /* +8 command buffer size in bytes */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

482

uint32_t fence_addr_lo; /* +12 bits [31:0] of GPU Virtual address of Fence for this frame */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

483

uint32_t fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

484

uint32_t fence_value; /* +20 Fence value */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

485

uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

486

uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

490

uint32_t reserved2[7]; /* +36 reserved, must be 0 */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

68

volatile uint32_t cmd_resp; /* +0 Command/Response register for Gfx commands */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

69

volatile uint32_t rbi_wptr; /* +4 Write pointer (index) of RBI ring */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

70

volatile uint32_t rbi_rptr; /* +8 Read pointer (index) of RBI ring */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

71

volatile uint32_t gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

72

volatile uint32_t gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

73

volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

74

volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) */

sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h

75

volatile uint32_t ring_buf_size; /* +28 Ring buffer size (in bytes) */

sys/dev/pci/drm/amd/amdgpu/psp_v10_0.c

147

static uint32_t psp_v10_0_ring_get_wptr(struct psp_context *psp)

sys/dev/pci/drm/amd/amdgpu/psp_v10_0.c

154

static void psp_v10_0_ring_set_wptr(struct psp_context *psp, uint32_t value)

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

148

uint32_t sol_reg1, sol_reg2;

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

193

uint32_t sol_reg;

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

205

uint32_t psp_gfxdrv_command_reg = 0;

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

223

(uint32_t)(psp->fw_pri_mc_addr >> 20));

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

269

(uint32_t)(psp->fw_pri_mc_addr >> 20));

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

406

uint32_t offset;

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

431

uint32_t data_32;

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

462

static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

465

uint32_t *pcache = (uint32_t *)ctx->sys_cache;

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

467

uint32_t p2c_header[4];

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

468

uint32_t sz;

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

583

static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

585

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

596

static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

611

uint32_t reg_status;

sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c

651

static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)

sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c

150

static uint32_t psp_v11_0_8_ring_get_wptr(struct psp_context *psp)

sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c

152

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c

163

static void psp_v11_0_8_ring_set_wptr(struct psp_context *psp, uint32_t value)

sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

110

uint32_t sol_reg;

sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

130

(uint32_t)(psp->fw_pri_mc_addr >> 20));

sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

219

uint32_t offset;

sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

252

static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)

sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

254

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

265

static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)

sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

72

uint32_t psp_gfxdrv_command_reg = 0;

sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

74

uint32_t sol_reg;

sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c

94

(uint32_t)(psp->fw_pri_mc_addr >> 20));

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

142

uint32_t sol_reg;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

255

uint32_t psp_gfxdrv_command_reg = 0;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

275

(uint32_t)(psp->fw_pri_mc_addr >> 20));

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

357

(uint32_t)(psp->fw_pri_mc_addr >> 20));

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

493

static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

495

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

506

static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

522

uint32_t data_32;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

551

static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

554

uint32_t *pcache = (uint32_t *)ctx->sys_cache;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

556

uint32_t p2c_header[4];

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

557

uint32_t sz;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

675

uint32_t reg_status;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

715

static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

732

uint32_t reg_status = 0, reg_val = 0;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

844

uint32_t reg_data;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

902

uint32_t ucode_ver;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c

924

static int psp_v13_0_reg_program_no_ring(struct psp_context *psp, uint32_t val,

sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c

115

(uint32_t)(psp->fw_pri_mc_addr >> 20));

sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c

178

(uint32_t)(psp->fw_pri_mc_addr >> 20));

sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c

311

static uint32_t psp_v13_0_4_ring_get_wptr(struct psp_context *psp)

sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c

313

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c

324

static void psp_v13_0_4_ring_set_wptr(struct psp_context *psp, uint32_t value)

sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c

62

uint32_t sol_reg;

sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c

95

uint32_t psp_gfxdrv_command_reg = 0;

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

130

uint32_t psp_gfxdrv_command_reg = 0;

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

150

(uint32_t)(psp->fw_pri_mc_addr >> 20));

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

224

(uint32_t)(psp->fw_pri_mc_addr >> 20));

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

358

static uint32_t psp_v14_0_ring_get_wptr(struct psp_context *psp)

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

360

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

371

static void psp_v14_0_ring_set_wptr(struct psp_context *psp, uint32_t value)

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

387

uint32_t data_32;

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

416

static int psp_v14_0_memory_training(struct psp_context *psp, uint32_t ops)

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

419

uint32_t *pcache = (uint32_t *)ctx->sys_cache;

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

421

uint32_t p2c_header[4];

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

422

uint32_t sz;

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

540

uint32_t reg_status;

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

581

static int psp_v14_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

599

uint32_t reg_status = 0, reg_val = 0;

sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c

97

uint32_t sol_reg;

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

103

(uint32_t)(psp->fw_pri_mc_addr >> 20));

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

122

uint32_t sol_reg;

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

142

(uint32_t)(psp->fw_pri_mc_addr >> 20));

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

158

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

301

uint32_t reg;

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

310

uint32_t offset;

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

341

static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

343

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

353

static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value)

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

81

uint32_t psp_gfxdrv_command_reg = 0;

sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c

83

uint32_t sol_reg;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1184

uint32_t byte_count,

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1185

uint32_t copy_flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1208

uint32_t src_data,

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

1210

uint32_t byte_count)

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

224

static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

250

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

682

uint32_t incr)

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

712

uint32_t incr, uint64_t flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

760

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c

804

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1033

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1077

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1427

uint32_t temp, data;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1466

uint32_t temp, data;

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1626

uint32_t byte_count,

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1627

uint32_t copy_flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1650

uint32_t src_data,

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

1652

uint32_t byte_count)

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

400

static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

426

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

955

uint32_t incr)

sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c

985

uint32_t incr, uint64_t flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1066

static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1069

uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1254

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1274

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1406

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1616

uint32_t incr)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1647

uint32_t incr, uint64_t flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1695

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1723

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1731

static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1732

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1800

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1801

uint32_t *ptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

1923

ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2239

uint32_t data, def;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2278

uint32_t data, def;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2357

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2358

uint32_t instance_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2378

uint32_t instance_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2379

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2563

uint32_t byte_count,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2564

uint32_t copy_flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2588

uint32_t src_data,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2590

uint32_t byte_count)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2642

static void sdma_v4_0_get_ras_error_count(uint32_t value,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2643

uint32_t instance,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2644

uint32_t *sec_count)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2646

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2647

uint32_t sec_cnt;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2667

uint32_t instance, void *ras_error_status)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2670

uint32_t sec_count = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

2671

uint32_t reg_value = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

603

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

784

static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

810

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

830

uint32_t addr0, uint32_t addr1,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

831

uint32_t ref, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c

832

uint32_t inv)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c

167

uint32_t reg_offset,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c

168

uint32_t value,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c

169

uint32_t instance,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c

170

uint32_t *sec_count)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c

172

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c

173

uint32_t sec_cnt;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c

196

uint32_t instance,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c

200

uint32_t sec_count = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c

201

uint32_t reg_value = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c

202

uint32_t reg_offset = 0;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c

239

uint32_t reg_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c

36

static uint32_t sdma_v4_4_get_reg_offset(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c

37

uint32_t instance,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c

38

uint32_t offset)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4.c

40

uint32_t sdma_base = adev->reg_offset[SDMA0_HWIP][0][0];

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1212

uint32_t incr)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1243

uint32_t incr, uint64_t flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1291

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1319

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1327

static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1328

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1403

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1404

uint32_t *ptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1516

ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1557

uint32_t inst_mask;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1571

uint32_t inst_mask;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

163

uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1650

static bool sdma_v4_4_2_is_queue_selected(struct amdgpu_device *adev, uint32_t instance_id, bool is_page_queue)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1652

uint32_t reg_offset = is_page_queue ? regSDMA_PAGE_CONTEXT_STATUS : regSDMA_GFX_CONTEXT_STATUS;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1653

uint32_t context_status = RREG32(sdma_v4_4_2_get_reg_offset(adev, instance_id, reg_offset));

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1765

uint32_t instance, i;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1942

struct amdgpu_device *adev, bool enable, uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1944

uint32_t data, def;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1971

struct amdgpu_device *adev, bool enable, uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

1973

uint32_t data, def;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2011

uint32_t inst_mask;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2054

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2055

uint32_t instance_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2075

uint32_t instance_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2076

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2264

uint32_t byte_count,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2265

uint32_t copy_flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2289

uint32_t src_data,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2291

uint32_t byte_count)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2389

static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2402

static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2405

uint32_t tmp_mask = inst_mask;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2459

uint32_t sdma_inst,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2463

uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2486

uint32_t inst_mask;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2499

uint32_t sdma_inst)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2501

uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

2511

uint32_t inst_mask;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

351

static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

377

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

397

uint32_t addr0, uint32_t addr1,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

398

uint32_t ref, uint32_t mask,

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

399

uint32_t inv)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

492

uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

535

uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

549

uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

576

bool enable, uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

631

uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

661

static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

664

uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

904

uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

921

uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

967

uint32_t inst_mask, bool restore)

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

970

uint32_t tmp_mask;

sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c

994

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1184

uint32_t incr)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1215

uint32_t incr, uint64_t flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1264

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1298

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1306

static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1307

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1321

uint32_t reg0, uint32_t reg1,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1322

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1384

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1385

uint32_t *ptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1432

ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1698

uint32_t mes_queue_id = entry->src_data[0];

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1764

uint32_t data, def;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1801

uint32_t data, def;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1876

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1877

uint32_t instance_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1897

uint32_t instance_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1898

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

2013

uint32_t byte_count,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

2014

uint32_t copy_flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

2038

uint32_t src_data,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

2040

uint32_t byte_count)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

407

static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

433

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

467

uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

563

static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev, uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

660

uint32_t inst_mask;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1083

uint32_t incr)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1114

uint32_t incr, uint64_t flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1164

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1195

uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1219

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1227

static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1228

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1242

uint32_t reg0, uint32_t reg1,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1243

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1308

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1309

uint32_t *ptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1350

ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1604

uint32_t mes_queue_id = entry->src_data[0];

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1726

uint32_t data, def;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1763

uint32_t data, def;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1878

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1879

uint32_t instance_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1899

uint32_t instance_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1900

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

2017

uint32_t byte_count,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

2018

uint32_t copy_flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

2042

uint32_t src_data,

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

2044

uint32_t byte_count)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

255

static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

281

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

315

uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB |

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

413

static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev, uint32_t inst_mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

509

uint32_t inst_mask;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1089

uint32_t incr)

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1120

uint32_t incr, uint64_t flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1168

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1198

uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1222

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1230

static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1231

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1245

uint32_t reg0, uint32_t reg1,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1246

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1312

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1313

uint32_t *ptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1364

ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1689

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1690

uint32_t instance_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1710

uint32_t instance_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1711

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1831

uint32_t byte_count,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1832

uint32_t copy_flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1856

uint32_t src_data,

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

1858

uint32_t byte_count)

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

241

static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

267

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c

301

uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1109

uint32_t incr)

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1140

uint32_t incr, uint64_t flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1189

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1222

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1232

static void sdma_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1233

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1247

uint32_t reg0, uint32_t reg1,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1248

uint32_t ref, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1298

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1299

uint32_t *ptr;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1348

ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1622

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1623

uint32_t instance_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1643

uint32_t instance_offset;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1644

uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0);

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1765

uint32_t byte_count,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1766

uint32_t copy_flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1768

uint32_t num_type, data_format, max_com, write_cm;

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1807

uint32_t src_data,

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

1809

uint32_t byte_count)

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

245

static void sdma_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

271

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

305

uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |

sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c

684

uint32_t tmp, sdma_status, ic_op_cntl;

sys/dev/pci/drm/amd/amdgpu/si.c

1178

static uint32_t si_get_register_value(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/si.c

1183

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/si.c

1256

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/si.c

1470

uint32_t temp;

sys/dev/pci/drm/amd/amdgpu/si.c

1598

uint32_t perfctr = 0;

sys/dev/pci/drm/amd/amdgpu/si.c

1668

uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;

sys/dev/pci/drm/amd/amdgpu/si.c

1895

uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;

sys/dev/pci/drm/amd/amdgpu/si.c

2034

static uint32_t si_get_rev_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/si_dma.c

349

uint32_t incr)

sys/dev/pci/drm/amd/amdgpu/si_dma.c

378

uint32_t incr, uint64_t flags)

sys/dev/pci/drm/amd/amdgpu/si_dma.c

431

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/si_dma.c

469

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/si_dma.c

783

uint32_t byte_count,

sys/dev/pci/drm/amd/amdgpu/si_dma.c

784

uint32_t copy_flags)

sys/dev/pci/drm/amd/amdgpu/si_dma.c

805

uint32_t src_data,

sys/dev/pci/drm/amd/amdgpu/si_dma.c

807

uint32_t byte_count)

sys/dev/pci/drm/amd/amdgpu/si_dma.c

81

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/si_ih.c

138

uint32_t dw[4];

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

117

uint32_t reg = 0;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

171

static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control)

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

175

uint32_t ret = I2C_OK;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

176

uint32_t reg, reg_c_tx_abrt_source;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

223

static uint32_t smu_v11_0_i2c_poll_rx_status(struct i2c_adapter *control)

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

227

uint32_t ret = I2C_OK;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

228

uint32_t reg_ic_status, reg_c_tx_abrt_source;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

268

static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter *control,

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

367

static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter *control,

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

373

uint32_t bytes_received, ret = I2C_OK;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

384

uint32_t reg = 0;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

445

uint32_t reg = 0;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

463

const uint32_t IDLE_TIMEOUT = 1024;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

464

uint32_t timeout_count = 0;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

465

uint32_t reg_ic_enable, reg_ic_enable_status, reg_ic_clr_activity;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

51

uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT);

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

582

static uint32_t smu_v11_0_i2c_read_data(struct i2c_adapter *control,

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

583

struct i2c_msg *msg, uint32_t i2c_flag)

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

585

uint32_t ret;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

595

static uint32_t smu_v11_0_i2c_write_data(struct i2c_adapter *control,

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

596

struct i2c_msg *msg, uint32_t i2c_flag)

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

598

uint32_t ret;

sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c

770

uint32_t ret = I2C_OK;

sys/dev/pci/drm/amd/amdgpu/soc15.c

1375

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/soc15.c

1404

uint32_t def, data;

sys/dev/pci/drm/amd/amdgpu/soc15.c

404

static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/soc15.c

407

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/soc15.c

421

static uint32_t soc15_get_register_value(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/soc15.c

439

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/soc15.c

759

uint32_t perfctr = 0;

sys/dev/pci/drm/amd/amdgpu/soc15.c

806

uint32_t perfctr = 0;

sys/dev/pci/drm/amd/amdgpu/soc15.h

54

uint32_t hwip;

sys/dev/pci/drm/amd/amdgpu/soc15.h

55

uint32_t inst;

sys/dev/pci/drm/amd/amdgpu/soc15.h

56

uint32_t seg;

sys/dev/pci/drm/amd/amdgpu/soc15.h

57

uint32_t reg_offset;

sys/dev/pci/drm/amd/amdgpu/soc15.h

61

uint32_t hwip;

sys/dev/pci/drm/amd/amdgpu/soc15.h

62

uint32_t inst;

sys/dev/pci/drm/amd/amdgpu/soc15.h

63

uint32_t seg;

sys/dev/pci/drm/amd/amdgpu/soc15.h

64

uint32_t reg_offset;

sys/dev/pci/drm/amd/amdgpu/soc15.h

65

uint32_t reg_value;

sys/dev/pci/drm/amd/amdgpu/soc15.h

66

uint32_t se_num;

sys/dev/pci/drm/amd/amdgpu/soc15.h

67

uint32_t instance;

sys/dev/pci/drm/amd/amdgpu/soc15.h

71

uint32_t hwip;

sys/dev/pci/drm/amd/amdgpu/soc15.h

72

uint32_t inst;

sys/dev/pci/drm/amd/amdgpu/soc15.h

73

uint32_t seg;

sys/dev/pci/drm/amd/amdgpu/soc15.h

74

uint32_t reg_offset;

sys/dev/pci/drm/amd/amdgpu/soc15.h

80

uint32_t hwip;

sys/dev/pci/drm/amd/amdgpu/soc15.h

81

uint32_t inst;

sys/dev/pci/drm/amd/amdgpu/soc15.h

82

uint32_t seg;

sys/dev/pci/drm/amd/amdgpu/soc15.h

83

uint32_t reg_offset;

sys/dev/pci/drm/amd/amdgpu/soc15.h

84

uint32_t sec_count_mask;

sys/dev/pci/drm/amd/amdgpu/soc15.h

85

uint32_t sec_count_shift;

sys/dev/pci/drm/amd/amdgpu/soc15.h

86

uint32_t ded_count_mask;

sys/dev/pci/drm/amd/amdgpu/soc15.h

87

uint32_t ded_count_shift;

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

116

uint32_t i = 0; \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

117

uint32_t retries = 50000; \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

118

uint32_t r0 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0; \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

119

uint32_t r1 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1; \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

120

uint32_t spare_int = adev->reg_offset[GC_HWIP][inst][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SPARE_INT; \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

153

uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

155

uint32_t r2 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2; \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

156

uint32_t r3 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3; \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

157

uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_GFX_CNTL; \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

158

uint32_t grbm_idx = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX; \

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

174

uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\

sys/dev/pci/drm/amd/amdgpu/soc15_common.h

180

uint32_t target_reg = adev->reg_offset[GC_HWIP][inst][reg##_BASE_IDX] + reg;\

sys/dev/pci/drm/amd/amdgpu/soc21.c

278

static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num,

sys/dev/pci/drm/amd/amdgpu/soc21.c

281

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/soc21.c

295

static uint32_t soc21_get_register_value(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/soc21.c

311

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/soc24.c

135

static uint32_t soc24_read_indexed_register(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/soc24.c

140

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/soc24.c

154

static uint32_t soc24_get_register_value(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/soc24.c

171

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/ta_rap_if.h

29

#define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)

sys/dev/pci/drm/amd/amdgpu/ta_rap_if.h

58

uint32_t last_subsection;

sys/dev/pci/drm/amd/amdgpu/ta_rap_if.h

59

uint32_t num_total_validate;

sys/dev/pci/drm/amd/amdgpu/ta_rap_if.h

60

uint32_t num_valid;

sys/dev/pci/drm/amd/amdgpu/ta_rap_if.h

61

uint32_t last_validate_addr;

sys/dev/pci/drm/amd/amdgpu/ta_rap_if.h

62

uint32_t last_validate_val;

sys/dev/pci/drm/amd/amdgpu/ta_rap_if.h

63

uint32_t last_validate_val_exptd;

sys/dev/pci/drm/amd/amdgpu/ta_rap_if.h

75

uint32_t cmd_id;

sys/dev/pci/drm/amd/amdgpu/ta_rap_if.h

76

uint32_t validation_method_id;

sys/dev/pci/drm/amd/amdgpu/ta_rap_if.h

77

uint32_t resp_id;

sys/dev/pci/drm/amd/amdgpu/ta_ras_if.h

146

uint32_t sub_block_index; // mem block. i.e. hbm, sram etc.

sys/dev/pci/drm/amd/amdgpu/ta_ras_if.h

157

uint32_t active_umc_mask;

sys/dev/pci/drm/amd/amdgpu/ta_ras_if.h

162

uint32_t ch_inst;

sys/dev/pci/drm/amd/amdgpu/ta_ras_if.h

163

uint32_t umc_inst;

sys/dev/pci/drm/amd/amdgpu/ta_ras_if.h

164

uint32_t node_inst;

sys/dev/pci/drm/amd/amdgpu/ta_ras_if.h

165

uint32_t socket_id;

sys/dev/pci/drm/amd/amdgpu/ta_ras_if.h

170

uint32_t bank;

sys/dev/pci/drm/amd/amdgpu/ta_ras_if.h

171

uint32_t channel_idx;

sys/dev/pci/drm/amd/amdgpu/ta_ras_if.h

202

uint32_t reserve_pad[256];

sys/dev/pci/drm/amd/amdgpu/ta_ras_if.h

209

uint32_t reserve_pad[256];

sys/dev/pci/drm/amd/amdgpu/ta_ras_if.h

215

uint32_t cmd_id;

sys/dev/pci/drm/amd/amdgpu/ta_ras_if.h

216

uint32_t resp_id;

sys/dev/pci/drm/amd/amdgpu/ta_ras_if.h

217

uint32_t ras_status;

sys/dev/pci/drm/amd/amdgpu/ta_ras_if.h

218

uint32_t if_version;

sys/dev/pci/drm/amd/amdgpu/ta_ras_if.h

31

#define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)

sys/dev/pci/drm/amd/amdgpu/ta_secureDisplay_if.h

103

uint32_t phy_id;

sys/dev/pci/drm/amd/amdgpu/ta_secureDisplay_if.h

108

uint32_t phy_id;

sys/dev/pci/drm/amd/amdgpu/ta_secureDisplay_if.h

121

uint32_t reserved[4];

sys/dev/pci/drm/amd/amdgpu/ta_secureDisplay_if.h

133

uint32_t query_cmd_ret;

sys/dev/pci/drm/amd/amdgpu/ta_secureDisplay_if.h

159

uint32_t reserved[4];

sys/dev/pci/drm/amd/amdgpu/ta_secureDisplay_if.h

166

uint32_t cmd_id; /**< +0 Bytes Command ID */

sys/dev/pci/drm/amd/amdgpu/ta_secureDisplay_if.h

168

uint32_t reserved[2]; /**< +8 Bytes Reserved */

sys/dev/pci/drm/amd/amdgpu/ta_xgmi_if.h

107

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/ta_xgmi_if.h

119

uint32_t num_nodes;

sys/dev/pci/drm/amd/amdgpu/ta_xgmi_if.h

124

uint32_t num_nodes;

sys/dev/pci/drm/amd/amdgpu/ta_xgmi_if.h

129

uint32_t num_nodes;

sys/dev/pci/drm/amd/amdgpu/ta_xgmi_if.h

135

uint32_t num_nodes;

sys/dev/pci/drm/amd/amdgpu/ta_xgmi_if.h

140

uint32_t num_nodes;

sys/dev/pci/drm/amd/amdgpu/ta_xgmi_if.h

161

uint32_t cmd_id;

sys/dev/pci/drm/amd/amdgpu/ta_xgmi_if.h

162

uint32_t resp_id;

sys/dev/pci/drm/amd/amdgpu/ta_xgmi_if.h

28

#define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)

sys/dev/pci/drm/amd/amdgpu/tonga_ih.c

248

uint32_t dw[4];

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

138

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

139

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

180

uint32_t vram_type = adev->gmc.vram_type;

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

241

uint32_t col, col_lower, row, row_lower, row_high, bank;

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

242

uint32_t channel_index = 0, umc_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

243

uint32_t i, bit_num, retire_unit, *flip_bits;

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

327

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

328

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

35

uint32_t node_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

36

uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

37

uint32_t ch_inst)

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

39

uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst;

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

392

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

393

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

395

uint32_t odecc_cnt_sel;

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

50

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

51

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

533

uint32_t shift_bit = adev->umc.flip_bits.flip_bits_in_pa[2];

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

692

static uint32_t umc_v12_0_get_die_id(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/umc_v12_0.c

695

uint32_t die = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

147

uint32_t umc_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

148

uint32_t ch_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

149

uint32_t umc_reg_offset = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

150

uint32_t rsmu_umc_index_state =

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

170

uint32_t umc_reg_offset,

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

173

uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

174

uint32_t ecc_err_cnt, ecc_err_cnt_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

176

uint32_t mc_umc_status_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

227

uint32_t umc_reg_offset,

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

231

uint32_t mc_umc_status_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

259

uint32_t umc_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

260

uint32_t ch_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

261

uint32_t umc_reg_offset = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

263

uint32_t rsmu_umc_index_state = umc_v6_1_get_umc_index_mode_state(adev);

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

297

uint32_t umc_reg_offset,

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

298

uint32_t ch_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

299

uint32_t umc_inst)

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

301

uint32_t lsb, mc_umc_status_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

303

uint32_t channel_index = adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

358

uint32_t umc_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

359

uint32_t ch_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

36

const uint32_t

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

360

uint32_t umc_reg_offset = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

362

uint32_t rsmu_umc_index_state = umc_v6_1_get_umc_index_mode_state(adev);

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

392

uint32_t umc_reg_offset)

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

394

uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

395

uint32_t ecc_err_cnt_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

431

uint32_t umc_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

432

uint32_t ch_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

433

uint32_t umc_reg_offset = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

435

uint32_t rsmu_umc_index_state = umc_v6_1_get_umc_index_mode_state(adev);

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

46

uint32_t rsmu_umc_addr, rsmu_umc_val;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

61

uint32_t rsmu_umc_addr, rsmu_umc_val;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

74

static uint32_t umc_v6_1_get_umc_index_mode_state(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

76

uint32_t rsmu_umc_addr, rsmu_umc_val;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

87

static inline uint32_t get_umc_6_reg_offset(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

88

uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

89

uint32_t ch_inst)

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

95

uint32_t umc_reg_offset)

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

97

uint32_t ecc_err_cnt_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.c

98

uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v6_1.h

49

extern const uint32_t

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

100

uint32_t umc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

118

uint32_t channel_index =

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

137

uint32_t umc_inst, uint32_t ch_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

141

uint32_t eccinfo_table_idx;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

142

uint32_t umc_reg_offset;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

164

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

165

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

189

uint32_t ch_inst, uint32_t umc_inst)

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

191

uint32_t channel_index;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

223

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

224

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

227

uint32_t eccinfo_table_idx;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

262

uint32_t umc_reg_offset,

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

264

uint32_t ch_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

265

uint32_t umc_inst)

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

267

uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

268

uint32_t ecc_err_cnt, ecc_err_cnt_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

270

uint32_t mc_umc_status_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

31

const uint32_t

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

312

uint32_t mc_umc_addrt0;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

313

uint32_t channel_index;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

338

uint32_t umc_reg_offset,

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

342

uint32_t mc_umc_status_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

362

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

363

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

365

uint32_t ecc_err_cnt_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

366

uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

367

uint32_t umc_reg_offset =

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

38

const uint32_t

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

413

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

414

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

417

uint32_t umc_reg_offset =

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

442

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

443

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

445

uint32_t mc_umc_status_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

448

uint32_t umc_reg_offset =

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

46

static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

47

uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

48

uint32_t ch_inst)

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

491

static uint32_t umc_v6_7_query_ras_poison_mode_per_channel(

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

493

uint32_t umc_reg_offset)

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

495

uint32_t ecc_ctrl_addr, ecc_ctrl;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

50

uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

507

uint32_t umc_reg_offset = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

61

uint64_t mc_umc_status, uint32_t umc_reg_offset)

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

63

uint32_t mc_umc_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

95

uint32_t umc_inst, uint32_t ch_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.c

99

uint32_t eccinfo_table_idx;

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.h

70

extern const uint32_t

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.h

72

extern const uint32_t

sys/dev/pci/drm/amd/amdgpu/umc_v6_7.h

76

uint32_t ch_inst, uint32_t umc_inst);

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

104

uint32_t umc_reg_offset,

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

108

uint32_t mc_umc_status_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

124

uint32_t umc_reg_offset,

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

128

uint32_t mc_umc_status_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

144

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

145

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

148

uint32_t umc_reg_offset =

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

170

static uint32_t umc_v8_10_get_col_bit(uint32_t channel_num)

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

172

uint32_t t = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

186

uint32_t channel_idx,

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

189

uint32_t channel_num = UMC_V8_10_TOTAL_CHANNEL_NUM(adev);

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

190

uint32_t col_bit = umc_v8_10_get_col_bit(channel_num);

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

207

uint32_t ch_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

208

uint32_t node_inst, uint64_t mc_umc_status)

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

212

uint32_t channel_index, addr_lsb, col = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

245

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

246

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

252

uint32_t umc_reg_offset =

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

295

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

296

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

298

uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

299

uint32_t ecc_err_cnt_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

300

uint32_t umc_reg_offset =

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

336

uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

34

uint32_t channel_num;

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

340

uint32_t eccinfo_table_idx;

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

35

uint32_t col_bit;

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

355

uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

359

uint32_t eccinfo_table_idx;

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

380

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

381

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

402

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

403

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

405

uint32_t eccinfo_table_idx;

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

48

const uint32_t

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

58

const uint32_t

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

70

static inline uint32_t get_umc_v8_10_reg_offset(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

71

uint32_t node_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

72

uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

73

uint32_t ch_inst)

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

80

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

81

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

83

uint32_t ecc_err_cnt_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.c

84

uint32_t umc_reg_offset =

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.h

65

extern const uint32_t

sys/dev/pci/drm/amd/amdgpu/umc_v8_10.h

70

extern const uint32_t

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

120

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

121

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

123

uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

124

uint32_t ecc_err_cnt_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

125

uint32_t umc_reg_offset =

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

30

static inline uint32_t get_umc_v8_14_reg_offset(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

31

uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

32

uint32_t ch_inst)

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

38

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

39

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

41

uint32_t ecc_err_cnt_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

42

uint32_t umc_reg_offset =

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

62

uint32_t umc_reg_offset,

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

65

uint32_t ecc_err_cnt, ecc_err_cnt_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

78

uint32_t umc_reg_offset,

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

81

uint32_t ecc_err_cnt, ecc_err_cnt_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

93

uint32_t node_inst, uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

94

uint32_t ch_inst, void *data)

sys/dev/pci/drm/amd/amdgpu/umc_v8_14.c

97

uint32_t umc_reg_offset =

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

113

uint32_t ch_inst, uint32_t umc_inst)

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

116

uint32_t channel_index;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

132

uint32_t ch_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

133

uint32_t umc_inst)

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

136

uint32_t eccinfo_table_idx;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

165

uint32_t umc_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

166

uint32_t ch_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

181

uint32_t umc_reg_offset)

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

183

uint32_t ecc_err_cnt_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

184

uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

220

uint32_t umc_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

221

uint32_t ch_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

222

uint32_t umc_reg_offset = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

235

uint32_t umc_reg_offset,

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

238

uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

239

uint32_t ecc_err_cnt, ecc_err_cnt_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

241

uint32_t mc_umc_status_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

282

uint32_t umc_reg_offset,

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

286

uint32_t mc_umc_status_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

306

uint32_t umc_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

307

uint32_t ch_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

308

uint32_t umc_reg_offset = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

328

uint32_t umc_reg_offset,

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

329

uint32_t ch_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

330

uint32_t umc_inst)

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

332

uint32_t lsb, mc_umc_status_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

35

const uint32_t

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

373

uint32_t umc_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

374

uint32_t ch_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

375

uint32_t umc_reg_offset = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

391

uint32_t umc_reg_offset)

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

393

uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

394

uint32_t ecc_err_cnt_addr;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

421

uint32_t umc_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

422

uint32_t ch_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

423

uint32_t umc_reg_offset = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

43

static inline uint32_t get_umc_v8_7_reg_offset(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

44

uint32_t umc_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

45

uint32_t ch_inst)

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

51

uint32_t umc_inst, uint32_t ch_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

55

uint32_t eccinfo_table_idx;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

70

uint32_t umc_inst, uint32_t ch_inst,

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

74

uint32_t eccinfo_table_idx;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

95

uint32_t umc_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.c

96

uint32_t ch_inst = 0;

sys/dev/pci/drm/amd/amdgpu/umc_v8_7.h

48

extern const uint32_t

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

187

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

218

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

248

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

296

sizeof(uint32_t) * 5);

sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c

301

sizeof(uint32_t) * 5);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

142

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

167

static void uvd_v3_1_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

243

uint32_t size;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

285

uint32_t keysel = adev->uvd.keyselect;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

323

uint32_t rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

383

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

449

uint32_t i, j;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

450

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

551

uint32_t ucode_len;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

647

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

92

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

158

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

285

uint32_t rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

346

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

412

uint32_t i, j;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

413

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

509

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

547

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

555

static void uvd_v4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

577

uint32_t size;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

154

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

283

uint32_t size;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

322

uint32_t rb_bufsz, tmp;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

323

uint32_t lmi_swap_cntl;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

324

uint32_t mp_swap_cntl;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

389

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

524

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

561

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

571

static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

635

uint32_t data1, data3, suvd_flags;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

681

uint32_t data, data2;

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

729

uint32_t data, data1, cgc_flags, suvd_flags;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1027

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1055

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1067

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1094

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1109

static void uvd_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1123

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1285

uint32_t data1, data3;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1340

uint32_t data, data2;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1389

uint32_t data, data1, cgc_flags, suvd_flags;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

173

uint32_t rptr;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

208

static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

273

uint32_t handle,

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

468

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

609

uint32_t size;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

729

uint32_t rb_bufsz, tmp;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

730

uint32_t lmi_swap_cntl;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

731

uint32_t mp_swap_cntl;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

805

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

989

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1048

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1255

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1301

uint32_t reg = amdgpu_ib_get_value(ib, i);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1324

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1357

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1369

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1384

static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1385

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1407

uint32_t data0, data1, mask;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1418

static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1437

uint32_t reg, uint32_t val,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1438

uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1460

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1480

uint32_t ip_instance;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

178

uint32_t rptr;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

523

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

676

uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

677

uint32_t offset;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

735

uint32_t data = 0, loop;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

738

uint32_t size;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

791

uint32_t offset, size, tmp;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

792

uint32_t table_size = 0;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

797

uint32_t *init_table = adev->virt.mm_table.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

882

(uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

893

(uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

957

uint32_t rb_bufsz, tmp;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

958

uint32_t lmi_swap_cntl;

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

959

uint32_t mp_swap_cntl;

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

105

uint32_t status = RREG32(mmVCE_LMI_STATUS);

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

122

uint32_t status = RREG32(mmVCE_STATUS);

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

170

uint32_t size, offset;

sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c

553

uint32_t val = 0;

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

241

uint32_t status = RREG32(mmVCE_STATUS);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

551

uint32_t offset, size;

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

731

uint32_t val = 0;

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

783

uint32_t data = RREG32(mmVCE_CLOCK_GATING_A);

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

862

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c

887

uint32_t seq = ring->fence_drv.sync_seq;

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

131

uint32_t status =

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

156

uint32_t data = 0, loop;

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

159

uint32_t size;

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

208

uint32_t offset, size;

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

209

uint32_t table_size = 0;

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

214

uint32_t *init_table = adev->virt.mm_table.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

250

uint32_t low = adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_lo;

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

251

uint32_t hi = adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_hi;

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

632

uint32_t offset, size;

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

713

struct amdgpu_ib *ib, uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

741

static void vce_v4_0_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

742

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

764

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c

776

uint32_t val = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

28

u64 seq, uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

45

struct amdgpu_ib *ib, uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

47

uint32_t vmid = AMDGPU_JOB_GET_VMID(job);

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

56

void vcn_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

57

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

66

uint32_t vmid, uint64_t pd_addr)

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

69

uint32_t data0, data1, mask;

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

80

void vcn_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c

81

uint32_t val)

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.h

33

u64 seq, uint32_t flags);

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.h

36

struct amdgpu_ib *ib, uint32_t flags);

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.h

37

void vcn_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.h

38

uint32_t val, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.h

40

uint32_t vmid, uint64_t pd_addr);

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.h

41

void vcn_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.h

42

uint32_t val);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1030

uint32_t rb_bufsz, tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1031

uint32_t lmi_swap_cntl;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1247

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1302

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1303

uint32_t reg_data2 = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

131

uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

132

uint32_t *ptr;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1596

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1617

uint32_t reg, uint32_t val,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1618

uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1640

uint32_t data0, data1, mask;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1652

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1760

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1772

uint32_t reg, uint32_t val,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1773

uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1795

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1835

static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1978

uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1979

uint32_t inst_off, is_powered;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2011

uint32_t inst_off;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2012

uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2095

uint32_t msg_lo = 0, msg_hi = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2102

uint32_t reg = amdgpu_ib_get_value(ib, i);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2103

uint32_t val = amdgpu_ib_get_value(ib, i + 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

211

ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

357

uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

358

uint32_t offset;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

425

uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

426

uint32_t offset;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

505

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

632

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

699

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

754

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

800

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

850

uint32_t rb_bufsz, tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

851

uint32_t lmi_swap_cntl;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

928

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1006

uint32_t rb_bufsz, tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1007

uint32_t lmi_swap_cntl;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1091

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1184

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1219

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1296

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1512

void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1577

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1593

void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1594

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1616

uint32_t data0, data1, mask;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1628

uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1752

uint32_t flags)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1763

void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1764

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1785

void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1828

uint32_t tmp = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1893

uint32_t data = 0, loop;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1896

uint32_t size;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1958

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1960

uint32_t offset, size;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1961

uint32_t table_size = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1966

uint32_t *init_table = adev->virt.mm_table.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

384

uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

385

uint32_t offset;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

442

uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

443

uint32_t offset;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

546

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

653

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

708

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

763

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

813

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

858

uint32_t rb_bufsz, tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

870

adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h

29

extern void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h

33

struct amdgpu_ib *ib, uint32_t flags);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h

34

extern void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h

35

uint32_t val, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h

39

uint32_t reg, uint32_t val);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h

46

struct amdgpu_ib *ib, uint32_t flags);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h

47

extern void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h

48

uint32_t val, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h

51

extern void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1011

uint32_t rb_bufsz, tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1024

adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1169

uint32_t rb_bufsz, tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1258

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1355

uint32_t data = 0, loop = 0, size = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1411

uint32_t offset, size, tmp, i, rb_bufsz;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1412

uint32_t table_size = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1416

uint32_t *init_table = adev->virt.mm_table.cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1552

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1587

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1663

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2050

uint32_t ip_instance;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2162

static uint32_t vcn_v2_6_query_poison_by_instance(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2163

uint32_t instance, uint32_t sub_block)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2165

uint32_t poison_stat = 0, reg_value = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2185

uint32_t inst, sub;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

2186

uint32_t poison_stat = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

598

uint32_t size;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

599

uint32_t offset;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

655

uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

656

uint32_t offset;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

760

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

870

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

926

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

981

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1034

uint32_t rb_bufsz, tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1047

adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1199

uint32_t rb_bufsz, tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1287

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1392

uint32_t param, resp, expected;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1393

uint32_t offset, cache_size;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1394

uint32_t tmp, timeout;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1397

uint32_t *table_loc;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1398

uint32_t table_size;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1399

uint32_t size, size_dw;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1423

table_loc = (uint32_t *)table->cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1541

table_loc = (uint32_t *)table->cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1599

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1636

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1720

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1911

uint32_t *msg, num_buffers;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1959

uint32_t offset, size, *create;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1993

uint32_t msg_lo = 0, msg_hi = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2002

uint32_t reg = amdgpu_ib_get_value(ib, i);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2003

uint32_t val = amdgpu_ib_get_value(ib, i + 1);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2292

uint32_t ip_instance;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

524

uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

525

uint32_t offset;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

577

uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

578

uint32_t offset;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

675

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

728

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

782

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

914

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

970

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1002

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1015

adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1142

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1232

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1314

static int vcn_v4_0_init_ring_metadata(struct amdgpu_device *adev, uint32_t vcn_inst, struct amdgpu_ring *ring_enc)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1339

uint32_t param, resp, expected;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1340

uint32_t offset, cache_size;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1341

uint32_t tmp, timeout;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1344

uint32_t *table_loc;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1345

uint32_t table_size;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1346

uint32_t size, size_dw;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1347

uint32_t init_status;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1348

uint32_t enabled_vcn;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1375

table_loc = (uint32_t *)table->cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1503

table_loc = (uint32_t *)table->cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1574

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1610

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1703

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1828

uint32_t *msg, num_buffers;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1876

uint32_t offset, size, *create;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1912

static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int start)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

1930

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2171

uint32_t ip_instance;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2261

static uint32_t vcn_v4_0_query_poison_by_instance(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2262

uint32_t instance, uint32_t sub_block)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2264

uint32_t poison_stat = 0, reg_value = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2284

uint32_t inst, sub;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

2285

uint32_t poison_stat = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

451

uint32_t offset, size;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

514

uint32_t offset, size;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

622

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

644

uint32_t value;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

688

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

744

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

860

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

915

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c

969

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1002

uint32_t *table_loc;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1003

uint32_t table_size;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1004

uint32_t size, size_dw;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1005

uint32_t init_status;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1006

uint32_t enabled_vcn;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1033

table_loc = (uint32_t *)table->cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1128

table_loc = (uint32_t *)table->cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1193

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1276

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1328

ring->ring_size / sizeof(uint32_t));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1361

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1402

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1531

void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1532

uint32_t val, uint32_t mask)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1544

void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1545

uint32_t val)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1809

uint32_t i, inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1911

uint32_t vcn_inst,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1928

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1940

uint32_t vcn_inst)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1950

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1961

static uint32_t vcn_v4_0_3_query_poison_by_instance(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1962

uint32_t instance, uint32_t sub_block)

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1964

uint32_t poison_stat = 0, reg_value = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1984

uint32_t inst, sub;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

1985

uint32_t poison_stat = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

2109

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

456

uint32_t offset, size, vcn_inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

533

uint32_t offset, size;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

647

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

745

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

794

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

852

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

868

(uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

961

ring->ring_size / sizeof(uint32_t));

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

997

uint32_t param, resp, expected;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

998

uint32_t offset, cache_size;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c

999

uint32_t tmp, timeout;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.h

35

void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.h

36

uint32_t val, uint32_t mask);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.h

38

void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.h

39

uint32_t val);

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1054

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1144

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1237

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1272

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1366

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

1646

uint32_t ip_instance;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

402

uint32_t offset, size;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

465

uint32_t offset, size;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

579

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

639

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

682

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

798

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

853

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

917

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c

931

(uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1003

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1094

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

1367

uint32_t ip_instance;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

366

uint32_t offset, size;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

429

uint32_t offset, size;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

540

uint32_t data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

608

uint32_t data;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

701

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

715

adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

811

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

872

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c

967

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1038

uint32_t status;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1136

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1175

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1490

uint32_t i, inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1588

static uint32_t vcn_v5_0_1_query_poison_by_instance(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1589

uint32_t instance, uint32_t sub_block)

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1591

uint32_t poison_stat = 0, reg_value = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1611

uint32_t inst, sub;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

1612

uint32_t poison_stat = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

424

uint32_t offset, size, vcn_inst;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

489

uint32_t offset, size;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

624

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

676

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

691

(uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

754

WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / sizeof(uint32_t));

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

789

uint32_t param, resp, expected;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

790

uint32_t offset, cache_size;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

791

uint32_t tmp, timeout;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

794

uint32_t *table_loc;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

795

uint32_t table_size;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

796

uint32_t size, size_dw;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

797

uint32_t init_status;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

798

uint32_t enabled_vcn;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

825

table_loc = (uint32_t *)table->cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

920

table_loc = (uint32_t *)table->cpu_addr;

sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c

984

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

101

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

158

static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

181

static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

212

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

395

uint32_t v = 0;

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

396

uint32_t i = 0;

sys/dev/pci/drm/amd/amdgpu/vega10_ih.c

580

uint32_t data, def, field_val;

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

32

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

34

adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

35

adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

36

adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

37

adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

38

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

39

adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

40

adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

41

adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

42

adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

43

adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

44

adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

45

adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

46

adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

47

adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

48

adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

49

adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

50

adev->reg_offset[PWR_HWIP][i] = (uint32_t *)(&(PWR_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

51

adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIF_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

52

adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega10_reg_init.c

53

adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

109

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

194

static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

217

static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

248

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

286

static uint32_t vega20_setup_retry_doorbell(u32 doorbell_index)

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

479

uint32_t v = 0;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

480

uint32_t i = 0;

sys/dev/pci/drm/amd/amdgpu/vega20_ih.c

680

uint32_t data, def, field_val;

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

32

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

34

adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

35

adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

36

adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

37

adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

38

adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

39

adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

40

adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

41

adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

42

adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

43

adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

44

adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

45

adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

46

adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

47

adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

48

adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

49

adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

50

adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

51

adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

52

adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vega20_reg_init.c

53

adev->reg_offset[RSMU_HWIP][i] = (uint32_t *)(&(RSMU_BASE.instance[i]));

sys/dev/pci/drm/amd/amdgpu/vi.c

1300

static uint32_t vi_get_rev_id(struct amdgpu_device *adev)

sys/dev/pci/drm/amd/amdgpu/vi.c

1355

uint32_t perfctr = 0;

sys/dev/pci/drm/amd/amdgpu/vi.c

1746

uint32_t temp, data;

sys/dev/pci/drm/amd/amdgpu/vi.c

1766

uint32_t temp, data;

sys/dev/pci/drm/amd/amdgpu/vi.c

1782

uint32_t temp, data;

sys/dev/pci/drm/amd/amdgpu/vi.c

1798

uint32_t temp, data;

sys/dev/pci/drm/amd/amdgpu/vi.c

1815

uint32_t temp, data;

sys/dev/pci/drm/amd/amdgpu/vi.c

1833

uint32_t msg_id, pp_state = 0;

sys/dev/pci/drm/amd/amdgpu/vi.c

1834

uint32_t pp_support_state = 0;

sys/dev/pci/drm/amd/amdgpu/vi.c

744

static uint32_t vi_get_register_value(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/amdgpu/vi.c

749

uint32_t val;

sys/dev/pci/drm/amd/amdgpu/vi.c

843

uint32_t i;

sys/dev/pci/drm/amd/amdgpu/vi.c

985

uint32_t tmp;

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

103

uint32_t vpe_colla_cntl, vpe_colla_cfg, i;

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

128

uint32_t ucode_offset[2], ucode_size[2];

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

129

uint32_t i, j, size_dw;

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

130

uint32_t ret;

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

159

uint32_t f32_offset, f32_cntl;

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

210

uint32_t doorbell, doorbell_offset;

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

211

uint32_t rb_bufsz, rb_cntl;

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

212

uint32_t ib_cntl, i;

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

279

uint32_t queue_reset, i;

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

315

uint32_t vpe_cntl;

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

64

static uint32_t vpe_v6_1_get_reg_offset(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset)

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

66

uint32_t base;

sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c

76

uint32_t i, f32_cntl;

sys/dev/pci/drm/amd/amdkfd/cik_event_interrupt.c

30

const uint32_t *ih_ring_entry,

sys/dev/pci/drm/amd/amdkfd/cik_event_interrupt.c

31

uint32_t *patched_ihre,

sys/dev/pci/drm/amd/amdkfd/cik_event_interrupt.c

89

const uint32_t *ih_ring_entry)

sys/dev/pci/drm/amd/amdkfd/cik_event_interrupt.c

93

uint32_t context_id = ihre->data & 0xfffffff;

sys/dev/pci/drm/amd/amdkfd/cik_int.h

29

uint32_t source_id;

sys/dev/pci/drm/amd/amdkfd/cik_int.h

30

uint32_t data;

sys/dev/pci/drm/amd/amdkfd/cik_int.h

31

uint32_t ring_id;

sys/dev/pci/drm/amd/amdkfd/cik_int.h

32

uint32_t reserved;

sys/dev/pci/drm/amd/amdkfd/cwsr_trap_handler.h

1305

static const uint32_t cwsr_trap_arcturus_hex[] = {

sys/dev/pci/drm/amd/amdkfd/cwsr_trap_handler.h

1786

static const uint32_t cwsr_trap_aldebaran_hex[] = {

sys/dev/pci/drm/amd/amdkfd/cwsr_trap_handler.h

2278

static const uint32_t cwsr_trap_gfx10_hex[] = {

sys/dev/pci/drm/amd/amdkfd/cwsr_trap_handler.h

23

static const uint32_t cwsr_trap_gfx8_hex[] = {

sys/dev/pci/drm/amd/amdkfd/cwsr_trap_handler.h

2712

static const uint32_t cwsr_trap_gfx11_hex[] = {

sys/dev/pci/drm/amd/amdkfd/cwsr_trap_handler.h

276

static const uint32_t cwsr_trap_gfx9_hex[] = {

sys/dev/pci/drm/amd/amdkfd/cwsr_trap_handler.h

3156

static const uint32_t cwsr_trap_gfx9_4_3_hex[] = {

sys/dev/pci/drm/amd/amdkfd/cwsr_trap_handler.h

3646

static const uint32_t cwsr_trap_gfx12_hex[] = {

sys/dev/pci/drm/amd/amdkfd/cwsr_trap_handler.h

4184

static const uint32_t cwsr_trap_gfx9_5_0_hex[] = {

sys/dev/pci/drm/amd/amdkfd/cwsr_trap_handler.h

681

static const uint32_t cwsr_trap_nv1x_hex[] = {

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

1055

uint32_t flags = args->flags;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

1249

uint32_t *devices_arr = NULL;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

1365

uint32_t *devices_arr = NULL, i;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

1511

uint32_t flags;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

1770

uint32_t num_devices,

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

1825

static uint32_t get_process_num_bos(struct kfd_process *p)

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

1827

uint32_t num_of_bos = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

1894

uint32_t num_bos,

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

1947

bo_bucket->alloc_flags = (uint32_t)kgd_mem->alloc_flags;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

2022

uint32_t *num_devices,

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

2023

uint32_t *num_bos,

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

2024

uint32_t *num_objects,

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

2028

uint32_t num_queues, num_events, num_svm_ranges;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

2061

uint32_t num_devices, num_bos, num_objects;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

2194

uint32_t i;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

220

sizeof(uint32_t))) {

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

226

sizeof(uint32_t))) {

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

233

sizeof(uint32_t))) {

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

240

sizeof(uint32_t))) {

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

2437

uint32_t i = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

2509

uint32_t i;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

2516

uint32_t object_type;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

2523

ret = get_user(object_type, (uint32_t __user *)(args->priv_data + *priv_offset));

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

3046

(uint32_t *)args->suspend_queues.queue_array_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

3051

(uint32_t *)args->resume_queues.queue_array_ptr);

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

314

uint32_t doorbell_offset_in_process = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

499

uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr;

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

500

size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32);

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

521

cu_mask_size = sizeof(uint32_t) * (max_num_cus/32);

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

950

args->num_tile_configs * sizeof(uint32_t));

sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c

961

args->num_macro_tile_configs * sizeof(uint32_t));

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1075

find_subtype_mem(uint32_t heap_type, uint32_t flags, uint32_t width,

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1097

uint32_t heap_type;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1099

uint32_t flags = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1100

uint32_t width;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1166

uint32_t id;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1167

uint32_t total_num_of_cu;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1235

uint32_t id_from;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1236

uint32_t id_to;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1364

uint32_t proximity_domain)

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1372

uint32_t image_len;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1824

uint32_t *num_entries,

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1882

uint32_t entries = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

1984

uint32_t proximity_domain,

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

2111

uint32_t proximity_domain)

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

2184

uint32_t proximity_domain_from,

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

2185

uint32_t proximity_domain_to)

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

2234

uint32_t proximity_domain)

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

2244

uint32_t total_num_of_cu;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

2245

uint32_t nid = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

2404

uint32_t proximity_domain)

sys/dev/pci/drm/amd/amdkfd/kfd_crat.c

38

static uint32_t gpu_processor_id_low = 0x80001000;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

102

uint32_t flags;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

103

uint32_t proximity_domain;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

104

uint32_t processor_id_low;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

135

uint32_t flags;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

136

uint32_t proximity_domain;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

137

uint32_t base_addr_low;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

138

uint32_t base_addr_high;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

139

uint32_t length_low;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

140

uint32_t length_high;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

141

uint32_t width;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

162

uint32_t flags;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

163

uint32_t processor_id_low;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

165

uint32_t cache_size;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

191

uint32_t flags;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

192

uint32_t processor_id_low;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

194

uint32_t tlb_level;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

222

uint32_t flags;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

223

uint32_t processor_id_low;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

225

uint32_t apu_size;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

268

uint32_t flags;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

269

uint32_t proximity_domain_from;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

270

uint32_t proximity_domain_to;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

274

uint32_t minimum_latency;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

275

uint32_t maximum_latency;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

276

uint32_t minimum_bandwidth_mbs;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

277

uint32_t maximum_bandwidth_mbs;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

278

uint32_t recommended_transfer_size;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

293

uint32_t flags;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

302

uint32_t cache_size;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

303

uint32_t cache_level;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

304

uint32_t cache_line_size;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

305

uint32_t flags;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

309

uint32_t num_cu_shared;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

315

uint32_t proximity_domain);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

318

uint32_t proximity_domain);

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

50

uint32_t signature;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

51

uint32_t length;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

56

uint32_t oem_revision;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

57

uint32_t creator_id;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

58

uint32_t creator_revision;

sys/dev/pci/drm/amd/amdkfd/kfd_crat.h

59

uint32_t total_entries;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

1051

uint32_t *number_of_device_infos,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

1052

uint32_t *entry_size)

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

1055

uint32_t tmp_entry_size, tmp_num_devices;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

201

uint32_t doorbell_id,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

351

uint32_t spi_dbg_cntl = pdd->spi_dbg_override | pdd->spi_dbg_launch_mode;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

352

uint32_t flags = pdd->process->dbg_flags;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

429

uint32_t watch_id)

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

463

uint32_t watch_address_mask,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

464

uint32_t *watch_id,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

465

uint32_t watch_mode)

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

468

uint32_t xcc_mask = pdd->dev->xcc_mask;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

517

int kfd_dbg_trap_set_flags(struct kfd_process *target, uint32_t *flags)

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

519

uint32_t prev_flags = target->dbg_flags;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

525

uint32_t caps = topo_dev->node_props.capability;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

594

uint32_t flags = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

772

int kfd_dbg_trap_enable(struct kfd_process *target, uint32_t fd,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

773

void __user *runtime_info, uint32_t *runtime_size)

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

776

uint32_t copy_size;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

828

uint32_t trap_override,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

829

uint32_t trap_mask_request,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

830

uint32_t *trap_mask_supported)

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

854

uint32_t trap_override,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

855

uint32_t trap_mask_bits,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

856

uint32_t trap_mask_request,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

857

uint32_t *trap_mask_prev,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

858

uint32_t *trap_mask_supported)

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

929

uint32_t source_id,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

930

uint32_t exception_code,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

933

uint32_t *info_size)

sys/dev/pci/drm/amd/amdkfd/kfd_debug.c

937

uint32_t copy_size, actual_info_size = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

37

uint32_t doorbell_id,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

47

int kfd_dbg_trap_enable(struct kfd_process *target, uint32_t fd,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

49

uint32_t *runtime_info_size);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

51

uint32_t trap_override,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

52

uint32_t trap_mask_bits,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

53

uint32_t trap_mask_request,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

54

uint32_t *trap_mask_prev,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

55

uint32_t *trap_mask_supported);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

59

uint32_t watch_id);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

62

uint32_t watch_address_mask,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

63

uint32_t *watch_id,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

64

uint32_t watch_mode);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

65

int kfd_dbg_trap_set_flags(struct kfd_process *target, uint32_t *flags);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

67

uint32_t source_id,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

68

uint32_t exception_code,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

71

uint32_t *info_size);

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

90

uint32_t *number_of_device_infos,

sys/dev/pci/drm/amd/amdkfd/kfd_debug.h

91

uint32_t *entry_size);

sys/dev/pci/drm/amd/amdkfd/kfd_debugfs.c

58

uint32_t gpu_id;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

1123

uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

1162

int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger)

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

1290

static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

1294

return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

143

uint32_t gc_version = KFD_GC_VERSION(kfd);

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

1549

int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id)

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

1590

int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id)

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

1624

bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id)

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

201

bool vf, uint32_t gfx_target_version)

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

203

uint32_t gc_version = KFD_GC_VERSION(kfd);

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

204

uint32_t asic_type = kfd->adev->asic_type;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

214

kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t);

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

251

kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t);

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

269

uint32_t gfx_target_version = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

567

uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

683

uint32_t xcc_mask = node->xcc_mask;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

684

uint32_t xcc, mapped_xcc;

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

69

uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0);

sys/dev/pci/drm/amd/amdkfd/kfd_device.c

719

uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1471

uint32_t xcc_mask = dqm->dev->xcc_mask;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

148

uint32_t xcc_mask = dqm->dev->xcc_mask;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1486

uint32_t xcc_mask = dqm->dev->xcc_mask;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

1576

struct queue *q, const uint32_t *restore_sdma_id)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2154

uint32_t mec, pipe, queue;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2276

uint32_t doorbell_off)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2311

uint32_t doorbell_off =

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2373

uint32_t filter_param,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2374

uint32_t grace_period,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2466

uint32_t filter_param,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2467

uint32_t grace_period)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

254

queue_input.queue_type = (uint32_t)queue_type;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

2895

uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size *

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3174

uint32_t trap_debug_vmid;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3216

static void q_array_invalidate(uint32_t num_queues, uint32_t *queue_ids)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3226

uint32_t num_queues,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3227

uint32_t *queue_ids)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3250

uint32_t tmp_ctl_stack_used_size, tmp_save_area_used_size;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3293

static uint32_t *get_queue_ids(uint32_t num_queues, uint32_t *usr_queue_id_array)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3295

size_t array_size = num_queues * sizeof(uint32_t);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3304

uint32_t num_queues,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3305

uint32_t *usr_queue_id_array)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3307

uint32_t *queue_ids = NULL;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3399

num_queues * sizeof(uint32_t)))

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3409

uint32_t num_queues,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3410

uint32_t grace_period,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3412

uint32_t *usr_queue_id_array)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3414

uint32_t *queue_ids = get_queue_ids(num_queues, usr_queue_id_array);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3517

num_queues * sizeof(uint32_t)))

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3525

static uint32_t set_queue_type_for_user(struct queue_properties *q_props)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3556

qss_entry->ring_size = (uint32_t)q->properties.queue_size;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3640

uint32_t (*dump)[2], uint32_t n_regs)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3642

uint32_t i, count;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3646

dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) {

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3663

uint32_t xcc_mask = dqm->dev->xcc_mask;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3664

uint32_t (*dump)[2], n_regs;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

3667

uint32_t sdma_engine_start;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

433

uint32_t const *restore_id)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

454

uint32_t *idx_offset = dev->kfd->shared_resources.sdma_doorbell_idx;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

462

uint32_t valid_id = idx_offset[qpd->dqm->dev->node_id *

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

520

uint32_t xcc_mask = dqm->dev->xcc_mask;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

54

uint32_t filter_param,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

55

uint32_t grace_period);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

58

uint32_t filter_param,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

59

uint32_t grace_period,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

590

ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

595

qpd->ib_base, (uint32_t *)qpd->ib_kaddr,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

596

pmf->release_mem_size / sizeof(uint32_t));

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

71

struct queue *q, const uint32_t *restore_sdma_id);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.c

794

uint32_t xcc_mask = dev->xcc_mask;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

268

uint32_t trap_debug_vmid;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

278

uint32_t current_logical_xcc_start;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

280

uint32_t wait_times;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

314

uint32_t num_queues,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

315

uint32_t grace_period,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

317

uint32_t *usr_queue_id_array);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

319

uint32_t num_queues,

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

320

uint32_t *usr_queue_id_array);

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

48

uint32_t cmd:3;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

49

uint32_t:1;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

50

uint32_t mode:3;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

51

uint32_t check_vmid:1;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

52

uint32_t trap_id:3;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

53

uint32_t:5;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

54

uint32_t wave_id:4;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

55

uint32_t simd_id:2;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

56

uint32_t:2;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

57

uint32_t queue_id:3;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

58

uint32_t:1;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

59

uint32_t vm_id:4;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

61

uint32_t u32All;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

68

uint32_t instance_index:8;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

69

uint32_t sh_index:8;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

70

uint32_t se_index:8;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

71

uint32_t:5;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

72

uint32_t sh_broadcast_writes:1;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

73

uint32_t instance_broadcast_writes:1;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

74

uint32_t se_broadcast_writes:1;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager.h

76

uint32_t u32All;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_cik.c

60

static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_cik.c

95

uint32_t default_mtype;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_cik.c

96

uint32_t ape1_mtype;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v10.c

51

static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v10.c

53

uint32_t shared_base = pdd->lds_base >> 48;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v10.c

54

uint32_t private_base = pdd->scratch_base >> 48;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v11.c

50

static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v11.c

52

uint32_t shared_base = pdd->lds_base >> 48;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v11.c

53

uint32_t private_base = pdd->scratch_base >> 48;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v12.c

50

static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v12.c

52

uint32_t shared_base = pdd->lds_base >> 48;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v12.c

53

uint32_t private_base = pdd->scratch_base >> 48;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v9.c

50

static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v9.c

52

uint32_t shared_base = pdd->lds_base >> 48;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_v9.c

53

uint32_t private_base = pdd->scratch_base >> 48;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_vi.c

60

static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_vi.c

96

uint32_t default_mtype;

sys/dev/pci/drm/amd/amdkfd/kfd_device_queue_manager_vi.c

97

uint32_t ape1_mtype;

sys/dev/pci/drm/amd/amdkfd/kfd_doorbell.c

238

uint32_t first_db_index;

sys/dev/pci/drm/amd/amdkfd/kfd_doorbell.c

250

return adev->doorbell.base + first_db_index * sizeof(uint32_t);

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

1125

uint32_t id;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

1210

uint32_t id;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

1264

uint32_t id, idx;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

1348

uint32_t id = KFD_FIRST_NONSIGNAL_EVENT_ID;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

135

static struct kfd_event *lookup_event_by_id(struct kfd_process *p, uint32_t id)

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

158

struct kfd_process *p, uint32_t id, uint32_t bits)

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

232

(uint32_t)KFD_LAST_NONSIGNAL_EVENT_ID + 1,

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

284

uint32_t id;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

403

uint32_t event_type, bool auto_reset, uint32_t node_id,

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

404

uint32_t *event_id, uint32_t *event_trigger_data,

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

405

uint64_t *event_page_offset, uint32_t *event_slot_index)

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

536

uint32_t ev_id;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

538

uint32_t num_events = kfd_get_num_events(p);

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

602

uint32_t id;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

612

int kfd_event_destroy(struct kfd_process *p, uint32_t event_id)

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

653

int kfd_set_event(struct kfd_process *p, uint32_t event_id)

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

684

int kfd_reset_event(struct kfd_process *p, uint32_t event_id)

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

726

void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id,

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

727

uint32_t valid_id_bits)

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

755

uint32_t id;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

800

static struct kfd_event_waiter *alloc_event_waiters(uint32_t num_events)

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

803

uint32_t i;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

855

static uint32_t test_event_condition(bool all, uint32_t num_events,

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

858

uint32_t i;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

859

uint32_t activated_count = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

881

static int copy_signaled_event_data(uint32_t num_events,

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

889

uint32_t i, size = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

919

static long user_timeout_to_jiffies(uint32_t user_timeout_ms)

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

932

user_timeout_ms = min_t(uint32_t, user_timeout_ms, 0x7FFFFFFF);

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

937

static void free_waiters(uint32_t num_events, struct kfd_event_waiter *waiters,

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

940

uint32_t i;

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

957

uint32_t num_events, void __user *data,

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

958

bool all, uint32_t *user_timeout_ms,

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

959

uint32_t *wait_result)

sys/dev/pci/drm/amd/amdkfd/kfd_events.c

963

uint32_t i;

sys/dev/pci/drm/amd/amdkfd/kfd_events.h

87

extern void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id,

sys/dev/pci/drm/amd/amdkfd/kfd_events.h

88

uint32_t valid_id_bits);

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c

133

const uint32_t *ih_ring_entry,

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c

134

uint32_t *patched_ihre,

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c

138

const uint32_t *data = ih_ring_entry;

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c

195

const uint32_t *ih_ring_entry)

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c

198

uint32_t context_id0, context_id1;

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v10.c

199

uint32_t encoding, sq_intr_err_type;

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c

151

static void print_sq_intr_info_auto(struct kfd_node *dev, uint32_t context_id0,

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c

152

uint32_t context_id1)

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c

176

static void print_sq_intr_info_inst(struct kfd_node *dev, uint32_t context_id0,

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c

177

uint32_t context_id1)

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c

194

static void print_sq_intr_info_error(struct kfd_node *dev, uint32_t context_id0,

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c

195

uint32_t context_id1)

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c

221

uint32_t reset = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c

259

const uint32_t *ih_ring_entry,

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c

260

uint32_t *patched_ihre,

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c

264

const uint32_t *data = ih_ring_entry;

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c

265

uint32_t context_id0;

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c

308

const uint32_t *ih_ring_entry)

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v11.c

311

uint32_t context_id0, context_id1;

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c

148

uint32_t reset = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c

260

const uint32_t *ih_ring_entry,

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c

261

uint32_t *patched_ihre,

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c

265

const uint32_t *data = ih_ring_entry;

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c

304

const uint32_t pasid_mask = 0xffff;

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c

335

uint32_t context_id =

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c

358

const uint32_t *ih_ring_entry)

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c

361

uint32_t context_id0, context_id1;

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c

362

uint32_t sq_intr_err, sq_int_data, encoding;

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c

574

const uint32_t *ih_ring_entry,

sys/dev/pci/drm/amd/amdkfd/kfd_int_process_v9.c

575

uint32_t *patched_ihre,

sys/dev/pci/drm/amd/amdkfd/kfd_interrupt.c

139

uint32_t *ih_ring_entry;

sys/dev/pci/drm/amd/amdkfd/kfd_interrupt.c

158

const uint32_t *ih_ring_entry,

sys/dev/pci/drm/amd/amdkfd/kfd_interrupt.c

159

uint32_t *patched_ihre, bool *flag)

sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.c

135

prop.read_ptr = (uint32_t *) kq->rptr_gpu_addr;

sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.c

136

prop.write_ptr = (uint32_t *) kq->wptr_gpu_addr;

sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.c

165

retval = kfd_gtt_sa_allocate(dev, sizeof(uint32_t),

sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.c

234

uint32_t wptr, rptr;

sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.c

363

uint32_t *buffer, i;

sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.h

60

uint32_t pending_wptr;

sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.h

64

uint32_t *rptr_kernel;

sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.h

69

uint32_t *wptr_kernel;

sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.h

74

uint32_t *pq_kernel_addr;

sys/dev/pci/drm/amd/amdkfd/kfd_kernel_queue.h

77

uint32_t *eop_kernel_addr;

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

390

u64 end, uint32_t trigger, u64 ttm_res_offset)

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

488

svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc,

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

490

struct mm_struct *mm, uint32_t trigger)

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

688

uint32_t trigger, struct page *fault_page)

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

791

uint32_t trigger, struct page *fault_page)

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

884

svm_migrate_vram_to_vram(struct svm_range *prange, uint32_t best_loc,

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

886

struct mm_struct *mm, uint32_t trigger)

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

911

svm_migrate_to_vram(struct svm_range *prange, uint32_t best_loc,

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.c

913

struct mm_struct *mm, uint32_t trigger)

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.h

43

int svm_migrate_to_vram(struct svm_range *prange, uint32_t best_loc,

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.h

45

struct mm_struct *mm, uint32_t trigger);

sys/dev/pci/drm/amd/amdkfd/kfd_migrate.h

49

uint32_t trigger, struct page *fault_page);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

100

uint32_t *se_mask, uint32_t inst)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

104

uint32_t cu_per_sh[KFD_MAX_NUM_SE][KFD_MAX_NUM_SH_PER_SE] = {0};

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

106

uint32_t en_mask = wgp_mode_req ? 0x3 : 0x1;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

108

uint32_t cu_active_per_node;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

209

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

218

uint32_t pipe_id, uint32_t queue_id)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

236

uint64_t queue_address, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

237

uint32_t queue_id)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

244

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

248

(uint32_t __user *)p->write_ptr,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

258

unsigned int timeout, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

259

uint32_t queue_id)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

265

uint64_t queue_address, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

266

uint32_t queue_id)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

277

uint32_t virtual_xcc_id)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

286

mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

296

bool kfd_check_hiq_mqd_doorbell_id(struct kfd_node *node, uint32_t doorbell_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

297

uint32_t inst)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

85

mqd_mem_obj->cpu_ptr = (uint32_t *)((uint64_t)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.c

99

const uint32_t *cu_mask, uint32_t cu_mask_count,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

105

void (*get_checkpoint_info)(struct mqd_manager *mm, void *mqd, uint32_t *ctl_stack_size);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

128

uint32_t mqd_size;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

137

uint32_t control_stack_offset;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

142

uint32_t control_stack_size;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

148

uint32_t wave_state_offset;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

153

uint32_t wave_state_size;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

165

const uint32_t *cu_mask, uint32_t cu_mask_count,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

166

uint32_t *se_mask, uint32_t inst);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

169

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

174

uint32_t pipe_id, uint32_t queue_id);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

180

uint64_t queue_address, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

181

uint32_t queue_id);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

184

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

189

uint32_t pipe_id, uint32_t queue_id);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

192

uint64_t queue_address, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

193

uint32_t queue_id);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

196

struct kfd_mem_obj *mqd_mem_obj, uint32_t virtual_xcc_id);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

201

bool kfd_check_hiq_mqd_doorbell_id(struct kfd_node *node, uint32_t doorbell_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

202

uint32_t inst);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

79

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

89

unsigned int timeout, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

90

uint32_t queue_id);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

96

uint64_t queue_address, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager.h

97

uint32_t queue_id);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c

159

static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c

160

uint32_t queue_id, struct queue_properties *p,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c

164

uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c

165

uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c

168

(uint32_t __user *)p->write_ptr,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c

49

uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

151

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

156

uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

159

(uint32_t __user *)p->write_ptr,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

326

uint32_t pipe_id, uint32_t queue_id)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c

49

uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

130

uint32_t wa_mask = q->is_dbg_wa ? 0xffff : 0xffffffff;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

205

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

210

uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

213

(uint32_t __user *)p->write_ptr,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

379

uint32_t pipe_id, uint32_t queue_id)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

48

uint32_t se_mask[KFD_MAX_NUM_SE] = {0};

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c

58

uint32_t wa_mask =

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c

168

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c

173

uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c

176

(uint32_t __user *)p->write_ptr,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c

48

uint32_t se_mask[KFD_MAX_NUM_SE] = {0};

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

232

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

236

uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

239

(uint32_t __user *)p->write_ptr,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

329

uint32_t doorbell_id = m->queue_doorbell_id0;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

457

uint32_t pipe_id, uint32_t queue_id)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

595

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

598

uint32_t xcc_mask = mm->dev->xcc_mask;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

620

uint32_t pipe_id, uint32_t queue_id)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

622

uint32_t xcc_mask = mm->dev->xcc_mask;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

63

struct mqd_update_info *minfo, uint32_t inst)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

648

uint32_t xcc_mask = mm->dev->xcc_mask;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

66

uint32_t se_mask[KFD_MAX_NUM_SE] = {0};

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

671

xcc_mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t)mqd_mem_obj->cpu_ptr

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

685

uint32_t local_xcc_start = mm->dev->dqm->current_logical_xcc_start++;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

818

uint32_t pipe_id, uint32_t queue_id)

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

820

uint32_t xcc_mask = mm->dev->xcc_mask;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

845

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

849

uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

850

uint32_t xcc_mask = mm->dev->xcc_mask;

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c

859

(uint32_t __user *)p->write_ptr, wptr_shift, 0, mms,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

158

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

162

uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

163

uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1);

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

166

(uint32_t __user *)p->write_ptr,

sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c

52

uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

267

alloc_size_bytes / sizeof(uint32_t),

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

272

for (i = 0; i < alloc_size_bytes / sizeof(uint32_t); i++)

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

333

uint32_t *buffer, size;

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

339

size / sizeof(uint32_t),

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

362

uint32_t *rl_buffer;

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

373

packet_size_dwords = pm->pmf->runlist_size / sizeof(uint32_t);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

382

rl_ib_size / sizeof(uint32_t), false);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

39

unsigned int temp = *wptr + increment_bytes / sizeof(uint32_t);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

406

uint32_t *buffer, size;

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

41

WARN((temp * sizeof(uint32_t)) > buffer_size_bytes,

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

415

size / sizeof(uint32_t), (unsigned int **)&buffer);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

444

uint32_t value)

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

449

uint32_t *buffer, size;

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

465

size / sizeof(uint32_t),

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

494

uint32_t filter_param, bool reset)

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

498

uint32_t *buffer, size;

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

504

size / sizeof(uint32_t), (unsigned int **)&buffer);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

557

uint32_t *buffer, size;

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager.c

566

size / sizeof(uint32_t), (unsigned int **)&buffer);

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

148

static int pm_runlist_v9(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

191

static int pm_set_resources_v9(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

227

static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

304

uint32_t sch_value, uint32_t que_sleep, uint32_t *reg_offset,

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

305

uint32_t *reg_data)

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

324

uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

326

uint32_t value)

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

329

uint32_t reg_offset = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

33

uint32_t *buffer, struct qcm_process_device *qpd)

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

330

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

334

uint32_t sch_wave = 0, que_sleep = 1;

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

394

static int pm_unmap_queues_v9(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

396

uint32_t filter_param, bool reset)

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

445

static int pm_query_status_v9(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c

90

uint32_t *buffer, struct qcm_process_device *qpd)

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c

115

static int pm_set_resources_vi(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c

143

static int pm_map_queues_vi(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c

201

static int pm_unmap_queues_vi(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c

203

uint32_t filter_param, bool reset)

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c

247

static int pm_query_status_vi(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c

272

static int pm_release_mem_vi(uint64_t gpu_addr, uint32_t *buffer)

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c

42

static int pm_map_process_vi(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c

76

static int pm_runlist_vi(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

103

uint32_t ordinal1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

108

uint32_t pasid:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

109

uint32_t reserved1:8;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

110

uint32_t diq_enable:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

111

uint32_t process_quantum:7;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

113

uint32_t ordinal2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

118

uint32_t page_table_base:28;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

119

uint32_t reserved2:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

121

uint32_t ordinal3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

124

uint32_t reserved3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

125

uint32_t sh_mem_bases;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

126

uint32_t sh_mem_config;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

127

uint32_t sh_mem_ape1_base;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

128

uint32_t sh_mem_ape1_limit;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

129

uint32_t sh_hidden_private_base_vmid;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

130

uint32_t reserved4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

131

uint32_t reserved5;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

132

uint32_t gds_addr_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

133

uint32_t gds_addr_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

137

uint32_t num_gws:6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

138

uint32_t reserved6:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

139

uint32_t num_oac:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

140

uint32_t reserved7:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

141

uint32_t gds_size:6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

142

uint32_t num_queues:10;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

144

uint32_t ordinal14;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

147

uint32_t completion_signal_lo32;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

148

uint32_t completion_signal_hi32;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

33

uint32_t reserved1:8;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

35

uint32_t opcode:8;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

37

uint32_t count:14;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

39

uint32_t type:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

41

uint32_t u32all;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

54

uint32_t ordinal1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

59

uint32_t pasid:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

60

uint32_t reserved1:8;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

61

uint32_t diq_enable:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

62

uint32_t process_quantum:7;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

64

uint32_t ordinal2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

69

uint32_t page_table_base:28;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

70

uint32_t reserved3:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

72

uint32_t ordinal3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

75

uint32_t sh_mem_bases;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

76

uint32_t sh_mem_ape1_base;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

77

uint32_t sh_mem_ape1_limit;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

78

uint32_t sh_mem_config;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

79

uint32_t gds_addr_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

80

uint32_t gds_addr_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

84

uint32_t num_gws:6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

85

uint32_t reserved4:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

86

uint32_t num_oac:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

87

uint32_t reserved5:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

88

uint32_t gds_size:6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

89

uint32_t num_queues:10;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers.h

91

uint32_t ordinal10;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

107

uint32_t ordinal1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

112

uint32_t reserved1:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

113

uint32_t ib_base_lo:30;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

115

uint32_t ordinal2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

118

uint32_t ib_base_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

122

uint32_t ib_size:20;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

123

uint32_t chain:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

124

uint32_t offload_polling:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

125

uint32_t chained_runlist_idle_disable:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

126

uint32_t valid:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

127

uint32_t process_cnt:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

128

uint32_t reserved3:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

130

uint32_t ordinal4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

144

uint32_t ordinal1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

149

uint32_t pasid:16; /* 0 - 15 */

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

150

uint32_t reserved1:1; /* 16 */

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

151

uint32_t exec_cleaner_shader:1; /* 17 */

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

152

uint32_t debug_vmid:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

153

uint32_t new_debug:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

154

uint32_t reserved2:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

155

uint32_t diq_enable:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

156

uint32_t process_quantum:7;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

158

uint32_t ordinal2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

161

uint32_t vm_context_page_table_base_addr_lo32;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

163

uint32_t vm_context_page_table_base_addr_hi32;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

165

uint32_t sh_mem_bases;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

167

uint32_t sh_mem_config;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

169

uint32_t sq_shader_tba_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

171

uint32_t sq_shader_tba_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

173

uint32_t sq_shader_tma_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

175

uint32_t sq_shader_tma_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

177

uint32_t reserved6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

179

uint32_t gds_addr_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

181

uint32_t gds_addr_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

185

uint32_t num_gws:7;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

186

uint32_t sdma_enable:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

187

uint32_t num_oac:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

188

uint32_t gds_size_hi:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

189

uint32_t gds_size:6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

190

uint32_t num_queues:10;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

192

uint32_t ordinal14;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

195

uint32_t completion_signal_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

197

uint32_t completion_signal_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

211

uint32_t ordinal1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

214

uint32_t reserved1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

216

uint32_t vm_context_cntl;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

218

uint32_t reserved2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

220

uint32_t vm_context_page_table_end_addr_lo32;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

222

uint32_t vm_context_page_table_end_addr_hi32;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

224

uint32_t vm_context_page_table_start_addr_lo32;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

226

uint32_t vm_context_page_table_start_addr_hi32;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

228

uint32_t reserved3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

230

uint32_t reserved4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

232

uint32_t reserved5;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

234

uint32_t reserved6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

236

uint32_t reserved7;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

238

uint32_t reserved8;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

240

uint32_t completion_signal_lo32;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

242

uint32_t completion_signal_hi32;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

278

uint32_t ordinal1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

283

uint32_t reserved1:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

286

uint32_t reserved5:6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

287

uint32_t gws_control_queue:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

288

uint32_t reserved2:8;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

290

uint32_t reserved3:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

292

uint32_t num_queues:3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

294

uint32_t ordinal2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

299

uint32_t reserved3:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

300

uint32_t check_disable:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

301

uint32_t doorbell_offset:26;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

302

uint32_t reserved4:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

304

uint32_t ordinal3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

307

uint32_t mqd_addr_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

308

uint32_t mqd_addr_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

309

uint32_t wptr_addr_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

310

uint32_t wptr_addr_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

32

uint32_t reserved1 : 8; /* < reserved */

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

33

uint32_t opcode : 8; /* < IT opcode */

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

34

uint32_t count : 14;/* < number of DWORDs - 1 in the

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

340

uint32_t ordinal1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

345

uint32_t context_id:28;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

349

uint32_t ordinal2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

354

uint32_t pasid:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

355

uint32_t reserved1:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

358

uint32_t reserved2:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

359

uint32_t doorbell_offset:26;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

361

uint32_t reserved3:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

363

uint32_t ordinal3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

366

uint32_t addr_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

367

uint32_t addr_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

368

uint32_t data_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

369

uint32_t data_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

37

uint32_t type : 2; /* < packet identifier.

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

405

uint32_t ordinal1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

41

uint32_t u32All;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

413

uint32_t reserved2:20;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

415

uint32_t num_queues:3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

417

uint32_t ordinal2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

422

uint32_t pasid:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

423

uint32_t reserved3:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

426

uint32_t reserved4:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

427

uint32_t doorbell_offset0:26;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

430

uint32_t ordinal3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

435

uint32_t reserved6:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

436

uint32_t doorbell_offset1:26;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

437

uint32_t reserved7:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

439

uint32_t ordinal4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

444

uint32_t reserved8:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

445

uint32_t doorbell_offset2:26;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

446

uint32_t reserved9:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

448

uint32_t ordinal5;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

453

uint32_t reserved10:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

454

uint32_t doorbell_offset3:26;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

455

uint32_t reserved11:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

457

uint32_t ordinal6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

523

uint32_t reserved3:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

524

uint32_t tc_nc_action_ena:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

525

uint32_t tc_wc_action_ena:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

526

uint32_t tc_md_action_ena:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

527

uint32_t reserved4:3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

529

uint32_t reserved5:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

531

uint32_t reserved6:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

538

uint32_t reserved7:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

540

uint32_t reserved8:6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

542

uint32_t reserved9:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

550

uint32_t reserved10:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

554

uint32_t reserved11:3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

555

uint32_t address_lo_64b:29;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

557

uint32_t reserved12;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

562

uint32_t address_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

563

uint32_t reserved13;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

564

uint32_t ordinal5;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

568

uint32_t data_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

569

uint32_t cmp_data_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

571

uint32_t dw_offset:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

572

uint32_t num_dwords:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

574

uint32_t reserved14;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

575

uint32_t ordinal6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

579

uint32_t data_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

580

uint32_t cmp_data_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

581

uint32_t reserved15;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

582

uint32_t reserved16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

583

uint32_t ordinal7;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

586

uint32_t int_ctxid;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

59

uint32_t ordinal1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

64

uint32_t vmid_mask:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

649

uint32_t reserved7;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

65

uint32_t unmap_latency:8;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

651

uint32_t data;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

66

uint32_t reserved1:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

67

uint32_t enb_xnack_retry_disable_check:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

70

uint32_t ordinal2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

73

uint32_t queue_mask_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

74

uint32_t queue_mask_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

75

uint32_t gws_mask_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

76

uint32_t gws_mask_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

80

uint32_t oac_mask:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

81

uint32_t reserved2:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

83

uint32_t ordinal7;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

88

uint32_t gds_heap_base:10;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

89

uint32_t reserved3:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

90

uint32_t gds_heap_size:10;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

91

uint32_t reserved4:11;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_ai.h

93

uint32_t ordinal8;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

33

uint32_t ordinal1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

38

uint32_t pasid:16; /* 0 - 15 */

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

39

uint32_t single_memops:1; /* 16 */

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

40

uint32_t exec_cleaner_shader:1; /* 17 */

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

41

uint32_t debug_vmid:4; /* 18 - 21 */

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

42

uint32_t new_debug:1; /* 22 */

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

43

uint32_t tmz:1; /* 23 */

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

44

uint32_t diq_enable:1; /* 24 */

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

45

uint32_t process_quantum:7; /* 25 - 31 */

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

47

uint32_t ordinal2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

50

uint32_t vm_context_page_table_base_addr_lo32;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

52

uint32_t vm_context_page_table_base_addr_hi32;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

54

uint32_t sh_mem_bases;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

56

uint32_t sh_mem_config;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

58

uint32_t sq_shader_tba_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

60

uint32_t sq_shader_tba_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

62

uint32_t sq_shader_tma_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

64

uint32_t sq_shader_tma_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

66

uint32_t reserved6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

68

uint32_t gds_addr_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

70

uint32_t gds_addr_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

74

uint32_t num_gws:7;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

75

uint32_t sdma_enable:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

76

uint32_t num_oac:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

77

uint32_t gds_size_hi:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

78

uint32_t gds_size:6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

79

uint32_t num_queues:10;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

81

uint32_t ordinal14;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

84

uint32_t spi_gdbg_per_vmid_cntl;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

86

uint32_t tcp_watch_cntl[4];

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

88

uint32_t completion_signal_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h

90

uint32_t completion_signal_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

106

uint32_t ordinal1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

111

uint32_t reserved1:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

112

uint32_t ib_base_lo:30;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

114

uint32_t ordinal2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

119

uint32_t ib_base_hi:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

120

uint32_t reserved2:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

122

uint32_t ordinal3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

127

uint32_t ib_size:20;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

128

uint32_t chain:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

129

uint32_t offload_polling:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

130

uint32_t reserved2:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

131

uint32_t valid:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

132

uint32_t process_cnt:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

133

uint32_t reserved3:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

135

uint32_t ordinal4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

149

uint32_t ordinal1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

154

uint32_t pasid:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

155

uint32_t reserved1:8;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

156

uint32_t diq_enable:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

157

uint32_t process_quantum:7;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

159

uint32_t ordinal2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

164

uint32_t page_table_base:28;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

165

uint32_t reserved3:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

167

uint32_t ordinal3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

170

uint32_t reserved;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

172

uint32_t sh_mem_bases;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

173

uint32_t sh_mem_config;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

174

uint32_t sh_mem_ape1_base;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

175

uint32_t sh_mem_ape1_limit;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

177

uint32_t sh_hidden_private_base_vmid;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

179

uint32_t reserved2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

180

uint32_t reserved3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

182

uint32_t gds_addr_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

183

uint32_t gds_addr_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

187

uint32_t num_gws:6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

188

uint32_t reserved4:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

189

uint32_t num_oac:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

190

uint32_t reserved5:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

191

uint32_t gds_size:6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

192

uint32_t num_queues:10;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

194

uint32_t ordinal10;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

197

uint32_t completion_signal_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

198

uint32_t completion_signal_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

230

uint32_t ordinal1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

235

uint32_t reserved1:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

237

uint32_t reserved2:15;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

239

uint32_t reserved3:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

241

uint32_t num_queues:3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

243

uint32_t ordinal2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

248

uint32_t reserved3:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

249

uint32_t check_disable:1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

250

uint32_t doorbell_offset:21;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

251

uint32_t reserved4:3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

252

uint32_t queue:6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

254

uint32_t ordinal3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

257

uint32_t mqd_addr_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

258

uint32_t mqd_addr_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

259

uint32_t wptr_addr_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

260

uint32_t wptr_addr_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

290

uint32_t ordinal1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

295

uint32_t context_id:28;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

300

uint32_t ordinal2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

305

uint32_t pasid:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

306

uint32_t reserved1:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

309

uint32_t reserved2:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

310

uint32_t doorbell_offset:21;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

311

uint32_t reserved3:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

313

uint32_t reserved4:4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

315

uint32_t ordinal3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

318

uint32_t addr_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

319

uint32_t addr_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

32

uint32_t reserved1 : 8; /* < reserved */

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

320

uint32_t data_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

321

uint32_t data_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

33

uint32_t opcode : 8; /* < IT opcode */

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

34

uint32_t count : 14;/* < Number of DWORDS - 1 in the

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

352

uint32_t ordinal1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

358

uint32_t reserved1:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

360

uint32_t reserved2:20;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

362

uint32_t num_queues:3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

364

uint32_t ordinal2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

369

uint32_t pasid:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

37

uint32_t type : 2; /* < packet identifier

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

370

uint32_t reserved3:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

373

uint32_t reserved4:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

374

uint32_t doorbell_offset0:21;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

375

uint32_t reserved5:9;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

377

uint32_t ordinal3;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

382

uint32_t reserved6:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

383

uint32_t doorbell_offset1:21;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

384

uint32_t reserved7:9;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

386

uint32_t ordinal4;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

391

uint32_t reserved8:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

392

uint32_t doorbell_offset2:21;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

393

uint32_t reserved9:9;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

395

uint32_t ordinal5;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

400

uint32_t reserved10:2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

401

uint32_t doorbell_offset3:21;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

402

uint32_t reserved11:9;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

404

uint32_t ordinal6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

41

uint32_t u32All;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

59

uint32_t ordinal1;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

64

uint32_t vmid_mask:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

65

uint32_t unmap_latency:8;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

66

uint32_t reserved1:5;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

69

uint32_t ordinal2;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

72

uint32_t queue_mask_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

73

uint32_t queue_mask_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

74

uint32_t gws_mask_lo;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

75

uint32_t gws_mask_hi;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

79

uint32_t oac_mask:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

80

uint32_t reserved2:16;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

82

uint32_t ordinal7;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

87

uint32_t gds_heap_base:6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

88

uint32_t reserved3:5;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

89

uint32_t gds_heap_size:6;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

90

uint32_t reserved4:15;

sys/dev/pci/drm/amd/amdkfd/kfd_pm4_headers_vi.h

92

uint32_t ordinal8;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1057

int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1059

uint32_t *gpuid, uint32_t *gpuidx);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1061

uint32_t gpuidx, uint32_t *gpuid) {

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1065

struct kfd_process *p, uint32_t gpuidx) {

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1070

int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1076

uint32_t gpu_id);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1078

int kfd_process_get_user_gpu_id(struct kfd_process *p, uint32_t actual_gpu_id);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1150

uint32_t proximity_domain);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1152

uint32_t proximity_domain);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1153

struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1154

struct kfd_node *kfd_device_by_id(uint32_t gpu_id);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1155

static inline bool kfd_irq_is_from_node(struct kfd_node *node, uint32_t node_id,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1156

uint32_t vmid)

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1162

uint32_t node_id, uint32_t vmid) {

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1164

uint32_t i;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1190

const uint32_t *ih_ring_entry,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1191

uint32_t *patched_ihre, bool *flag);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1222

uint32_t version;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1223

uint32_t xnack_mode;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1233

uint32_t idr_handle;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1234

uint32_t mapped_gpuids[MAX_GPU_INSTANCE];

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1248

uint32_t object_type;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1256

uint32_t object_type;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1264

uint32_t gpu_id;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1265

uint32_t type;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1266

uint32_t format;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1267

uint32_t q_id;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1268

uint32_t priority;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1269

uint32_t q_percent;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1270

uint32_t doorbell_id;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1271

uint32_t gws;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1272

uint32_t sdma_id;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1273

uint32_t eop_ring_buffer_size;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1274

uint32_t ctx_save_restore_area_size;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1275

uint32_t ctl_stack_size;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1276

uint32_t mqd_size;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1280

uint32_t object_type;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1282

uint32_t event_id;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1283

uint32_t auto_reset;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1284

uint32_t type;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1285

uint32_t signaled;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1294

uint32_t *num_queues,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1370

uint32_t *p_doorbell_offset_in_process);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1389

uint32_t *entry_size);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1436

int (*map_process)(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1438

int (*runlist)(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1440

int (*set_resources)(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1442

int (*map_queues)(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1444

int (*unmap_queues)(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1446

uint32_t filter_param, bool reset);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1447

int (*config_dequeue_wait_counts)(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1448

enum kfd_config_dequeue_wait_counts_cmd cmd, uint32_t value);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1449

int (*query_status)(struct packet_manager *pm, uint32_t *buffer,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1451

int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1478

uint32_t filter_param, bool reset);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1484

uint32_t wait_counts_config);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1504

uint32_t num_events, void __user *data,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1505

bool all, uint32_t *user_timeout_ms,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1506

uint32_t *wait_result);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1507

void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1508

uint32_t valid_id_bits);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1510

int kfd_set_event(struct kfd_process *p, uint32_t event_id);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1511

int kfd_reset_event(struct kfd_process *p, uint32_t event_id);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1515

uint32_t event_type, bool auto_reset, uint32_t node_id,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1516

uint32_t *event_id, uint32_t *event_trigger_data,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1517

uint64_t *event_page_offset, uint32_t *event_slot_index);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

1520

int kfd_event_destroy(struct kfd_process *p, uint32_t event_id);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

224

const uint32_t *ih_ring_entry, uint32_t *patched_ihre,

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

227

const uint32_t *ih_ring_entry);

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

231

uint32_t gfx_target_version;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

241

uint32_t no_atomic_fw_version;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

251

uint32_t range_start;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

252

uint32_t range_end;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

254

uint32_t *cpu_ptr;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

259

uint32_t first_vmid_kfd;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

260

uint32_t last_vmid_kfd;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

261

uint32_t vmid_num_kfd;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

279

uint32_t xcc_mask; /* Instance mask of XCCs present */

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

292

uint32_t interrupt_bitmap; /* Only used for GFX 9.4.3 */

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

303

uint32_t reset_seq_num;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

321

uint32_t alloc_watch_ids;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

511

uint32_t priority;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

512

uint32_t queue_percent;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

516

uint32_t doorbell_off;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

523

uint32_t pm4_target_xcc;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

529

uint32_t sdma_engine_id;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

530

uint32_t sdma_queue_id;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

531

uint32_t sdma_vm_addr;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

534

uint32_t eop_ring_buffer_size;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

536

uint32_t ctx_save_restore_area_size;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

537

uint32_t ctl_stack_size;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

564

uint32_t count; /* Must be a multiple of 32 */

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

565

uint32_t *ptr;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

611

uint32_t mec;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

612

uint32_t pipe;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

613

uint32_t queue;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

651

uint32_t oac_mask;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

652

uint32_t gds_heap_base;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

653

uint32_t gds_heap_size;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

693

uint32_t sh_mem_config;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

694

uint32_t sh_mem_bases;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

695

uint32_t sh_mem_ape1_base;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

696

uint32_t sh_mem_ape1_limit;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

697

uint32_t gds_size;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

698

uint32_t num_gws;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

699

uint32_t num_oac;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

700

uint32_t sh_hidden_private_base;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

847

uint32_t spi_dbg_override;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

848

uint32_t spi_dbg_launch_mode;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

849

uint32_t watch_points[4];

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

850

uint32_t alloc_watch_ids;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

857

uint32_t user_gpu_id;

sys/dev/pci/drm/amd/amdkfd/kfd_priv.h

931

uint32_t n_pdds;

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

1385

uint32_t flags = KFD_IOC_ALLOC_MEM_FLAGS_GTT

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

1884

int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger)

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

1961

int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id)

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

1973

uint32_t *gpuid, uint32_t *gpuidx)

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

2159

uint32_t irq_drain_fence[8];

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

2228

uint32_t ev_id;

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

2281

struct kfd_process_device *kfd_process_device_data_by_id(struct kfd_process *p, uint32_t gpu_id)

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

2296

int kfd_process_get_user_gpu_id(struct kfd_process *p, uint32_t actual_gpu_id)

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

740

uint64_t gpu_va, uint32_t size,

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

741

uint32_t flags, struct kgd_mem **mem, void **kptr)

sys/dev/pci/drm/amd/amdkfd/kfd_process.c

795

uint32_t flags = KFD_IOC_ALLOC_MEM_FLAGS_GTT |

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

1082

uint32_t *mqd_size,

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

1083

uint32_t *ctl_stack_size)

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

314

uint32_t *p_doorbell_offset_in_process)

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

470

uint32_t first_db_index = amdgpu_doorbell_index_on_bar(pdd->dev->adev,

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

476

- first_db_index) * sizeof(uint32_t);

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

656

uint32_t cu_pair = (minfo->cu_mask.ptr[i / 32] >> (i % 32)) & 0x3;

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

711

uint32_t *entry_size)

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

715

uint32_t tmp_entry_size = *entry_size, tmp_qss_entries = *num_qss_entries;

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

749

uint32_t *mqd_size,

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

750

uint32_t *ctl_stack_size)

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

765

uint32_t *num_queues,

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

768

uint32_t extra_data_sizes = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

783

uint32_t mqd_size, ctl_stack_size;

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

886

uint32_t mqd_size;

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

887

uint32_t ctl_stack_size;

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

970

struct kfd_criu_queue_priv_data *q_data, uint32_t num_xcc)

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

977

qp->read_ptr = (uint32_t *) q_data->read_ptr_addr;

sys/dev/pci/drm/amd/amdkfd/kfd_process_queue_manager.c

978

qp->write_ptr = (uint32_t *) q_data->write_ptr_addr;

sys/dev/pci/drm/amd/amdkfd/kfd_queue.c

107

uint32_t gpuid, gpuidx;

sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.c

282

uint32_t from, uint32_t to,

sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.c

283

uint32_t prefetch_loc, uint32_t preferred_loc,

sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.c

284

uint32_t trigger)

sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.c

294

uint32_t from, uint32_t to, uint32_t trigger,

sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.c

304

uint32_t trigger)

sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.c

340

uint32_t trigger)

sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.c

368

int kfd_smi_event_open(struct kfd_node *dev, uint32_t *fd)

sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.h

29

int kfd_smi_event_open(struct kfd_node *dev, uint32_t *fd);

sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.h

42

uint32_t from, uint32_t to,

sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.h

43

uint32_t prefetch_loc, uint32_t preferred_loc,

sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.h

44

uint32_t trigger);

sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.h

47

uint32_t from, uint32_t to, uint32_t trigger,

sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.h

50

uint32_t trigger);

sys/dev/pci/drm/amd/amdkfd/kfd_smi_events.h

55

uint32_t trigger);

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

1215

uint32_t flags = prange->flags;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

1216

uint32_t mapping_flags = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

1217

uint32_t gc_ip_version = KFD_GC_VERSION(node);

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

1346

unsigned long last, uint32_t trigger)

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

1352

uint32_t gpuidx;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

1486

uint32_t gpuidx;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

1546

uint32_t gpuidx;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

162

unsigned long *hmm_pfns, uint32_t gpuidx)

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2013

uint32_t trigger;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

212

uint32_t gpuidx;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2153

uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs,

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2336

uint32_t i;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2501

uint32_t trigger = KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2507

uint32_t i;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2534

uint32_t checkpoint_wptr;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

260

uint32_t gpuidx;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2719

uint32_t gpuid;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2822

uint32_t i;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

284

uint32_t gpuidx;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2873

uint32_t gpuid, gpuidx;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2965

uint32_t gpuid;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

2996

uint32_t vmid, uint32_t node_id,

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

315

uint32_t *flags)

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3369

uint32_t i;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3462

static uint32_t

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3466

uint32_t best_loc = prange->prefetch_loc;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3470

uint32_t gpuidx;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3547

uint32_t best_loc;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3659

uint64_t start, uint64_t size, uint32_t nattr,

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3793

uint64_t start, uint64_t size, uint32_t nattr,

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3808

uint32_t prefetch_loc = KFD_IOCTL_SVM_LOCATION_UNDEFINED;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3809

uint32_t location = KFD_IOCTL_SVM_LOCATION_UNDEFINED;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3810

uint32_t flags_and = 0xffffffff;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3811

uint32_t flags_or = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3813

uint32_t i;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3960

attrs[i].value = (uint32_t)granularity;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

3975

uint32_t set_flags = 0xffffffff;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

4080

uint32_t num_devices;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

4124

void svm_range_get_info(struct kfd_process *p, uint32_t *num_svm_ranges,

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

4132

uint32_t count = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

4275

uint64_t size, uint32_t nattrs, struct kfd_ioctl_svm_attribute *attrs)

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

680

svm_range_get_node_by_id(struct svm_range *prange, uint32_t gpu_id)

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

716

uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs)

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

718

uint32_t i;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

721

uint32_t val = attrs[i].value;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

765

uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs,

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

768

uint32_t i;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

807

prange->granularity = min_t(uint32_t, attrs[i].value, 0x3F);

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

817

uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs)

sys/dev/pci/drm/amd/amdkfd/kfd_svm.c

819

uint32_t i;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.h

126

uint32_t flags;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.h

127

uint32_t preferred_loc;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.h

128

uint32_t prefetch_loc;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.h

129

uint32_t actual_loc;

sys/dev/pci/drm/amd/amdkfd/kfd_svm.h

166

uint64_t size, uint32_t nattrs,

sys/dev/pci/drm/amd/amdkfd/kfd_svm.h

172

uint32_t gpu_id);

sys/dev/pci/drm/amd/amdkfd/kfd_svm.h

177

uint32_t vmid, uint32_t node_id, uint64_t addr, uint64_t ts,

sys/dev/pci/drm/amd/amdkfd/kfd_svm.h

187

void svm_range_get_info(struct kfd_process *p, uint32_t *num_svm_ranges,

sys/dev/pci/drm/amd/amdkfd/kfd_svm.h

227

uint32_t client_id, uint32_t node_id,

sys/dev/pci/drm/amd/amdkfd/kfd_svm.h

241

uint32_t *num_svm_ranges,

sys/dev/pci/drm/amd/amdkfd/kfd_svm.h

49

uint32_t evicting;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

100

struct kfd_node *kfd_device_by_id(uint32_t gpu_id)

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

1090

static uint32_t kfd_generate_gpu_id(struct kfd_node *gpu)

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

1092

uint32_t gpu_id;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

1093

uint32_t buf[8];

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

1183

static void kfd_notify_gpu_change(uint32_t gpu_id, int arrival)

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

1225

uint32_t cap;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

1285

uint32_t sdma_eng_id_mask = (1 << num_sdma_engines) - 1;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

1286

uint32_t xgmi_sdma_eng_id_mask =

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

1311

uint32_t engine_mask = (outbound_link->iolink_type == CRAT_IOLINK_TYPE_XGMI &&

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

1568

uint32_t i;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

1570

uint32_t k;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

1937

uint32_t mes_api_rev = (dev->gpu->adev->mes.sched_version &

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

1940

uint32_t mes_rev = dev->gpu->adev->mes.sched_version &

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

2038

uint32_t gpu_id;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

2267

uint32_t gpu_id;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

329

uint32_t i, j;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

374

uint32_t data;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

409

uint32_t log_max_watch_addr;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

51

static uint32_t topology_crat_proximity_domain;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

54

uint32_t proximity_domain)

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

642

uint32_t id)

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

650

uint32_t i, num_attrs;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

69

uint32_t proximity_domain)

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

82

struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id)

sys/dev/pci/drm/amd/amdkfd/kfd_topology.c

830

uint32_t i = 0;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

102

uint32_t processor_id_low;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

103

uint32_t cache_level;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

104

uint32_t cache_size;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

105

uint32_t cacheline_size;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

106

uint32_t cachelines_per_tag;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

107

uint32_t cache_assoc;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

108

uint32_t cache_latency;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

109

uint32_t cache_type;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

114

uint32_t sibling_map_size;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

119

uint32_t iolink_type;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

120

uint32_t ver_maj;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

121

uint32_t ver_min;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

122

uint32_t node_from;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

123

uint32_t node_to;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

124

uint32_t weight;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

125

uint32_t min_latency;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

126

uint32_t max_latency;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

127

uint32_t min_bandwidth;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

128

uint32_t max_bandwidth;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

129

uint32_t rec_transfer_size;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

130

uint32_t rec_sdma_eng_id_mask;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

131

uint32_t flags;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

140

uint32_t max_concurrent;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

146

uint32_t gpu_id;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

147

uint32_t proximity_domain;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

169

uint32_t oem_revision;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

173

uint32_t num_devices; /* Number of H-NUMA nodes */

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

174

uint32_t generation_count;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

45

uint32_t cpu_cores_count;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

46

uint32_t simd_count;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

47

uint32_t mem_banks_count;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

48

uint32_t caches_count;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

49

uint32_t io_links_count;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

50

uint32_t p2p_links_count;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

51

uint32_t cpu_core_id_base;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

52

uint32_t simd_id_base;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

53

uint32_t capability;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

54

uint32_t capability2;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

56

uint32_t max_waves_per_simd;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

57

uint32_t lds_size_in_kb;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

58

uint32_t gds_size_in_kb;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

59

uint32_t num_gws;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

60

uint32_t wave_front_size;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

61

uint32_t array_count;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

62

uint32_t simd_arrays_per_engine;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

63

uint32_t cu_per_simd_array;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

64

uint32_t simd_per_cu;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

65

uint32_t max_slots_scratch_cu;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

66

uint32_t engine_id;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

67

uint32_t gfx_target_version;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

68

uint32_t vendor_id;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

69

uint32_t device_id;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

70

uint32_t location_id;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

71

uint32_t domain;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

72

uint32_t max_engine_clk_fcompute;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

73

uint32_t max_engine_clk_ccompute;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

75

uint32_t num_sdma_engines;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

76

uint32_t num_sdma_xgmi_engines;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

77

uint32_t num_sdma_queues_per_engine;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

78

uint32_t num_cp_queues;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

79

uint32_t cwsr_size;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

80

uint32_t ctl_stack_size;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

81

uint32_t eop_buffer_size;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

82

uint32_t debug_memory_size;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

88

uint32_t heap_type;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

90

uint32_t flags;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

91

uint32_t width;

sys/dev/pci/drm/amd/amdkfd/kfd_topology.h

92

uint32_t mem_clk_max;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11970

uint32_t highest_id = 0, prev_id = UINT_MAX;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13161

void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13177

uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13280

uint32_t timeout_us

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13321

uint32_t timeout_us)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1781

uint32_t timeout_us)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1784

uint32_t i;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

232

uint32_t link_index);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2430

static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2437

static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2438

uint32_t value)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4982

uint32_t *user_brightness)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5045

uint32_t brightness)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5059

uint32_t brightness)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7029

uint32_t max_dsc_target_bpp_limit_override)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9065

uint32_t link_index)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9564

static inline uint32_t get_mem_type(struct drm_framebuffer *fb)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

1079

uint32_t timeout_us

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

417

uint32_t dmcub_fw_version;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

575

uint32_t dmcu_fw_version;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

589

uint32_t active_vblank_irq_count;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

693

uint32_t dsc_num_slices_v;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

694

uint32_t dsc_num_slices_h;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

695

uint32_t dsc_bits_per_pixel;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

745

uint32_t connector_id;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

776

uint32_t mst_local_bw;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

781

uint32_t branch_ieee_oui;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1058

uint32_t degamma_size;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1139

uint32_t degamma_size;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1188

uint32_t shaper_size, lut3d_size, blend_size;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

338

__extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

357

static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

360

uint32_t expected;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

389

uint32_t r, g, b;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

484

const struct drm_color_lut *lut, uint32_t lut_size,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

522

const struct drm_color_lut *lut, uint32_t lut_size,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

571

uint32_t regamma_size, bool has_rom,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

617

const struct drm_color_lut *lut, uint32_t lut_size)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

680

uint32_t lut3d_size,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

732

uint32_t drm_lut3d_size,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

753

uint32_t shaper_size,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

779

uint32_t blend_size,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

822

uint32_t exp_size, size, dim_size = MAX_COLOR_3DLUT_SIZE;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

863

uint32_t size = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

915

uint32_t degamma_size, regamma_size;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

730

uint32_t crcs[3];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

779

uint32_t crc_r[MAX_CRC_WINDOW_NUM] = {0};

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

780

uint32_t crc_g[MAX_CRC_WINDOW_NUM] = {0};

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

781

uint32_t crc_b[MAX_CRC_WINDOW_NUM] = {0};

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h

64

uint32_t crc_R;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h

65

uint32_t crc_G;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h

66

uint32_t crc_B;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h

67

uint32_t frame_count;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

724

uint32_t crtc_index)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h

48

uint32_t link_index);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1202

uint32_t wr_buf_size = 42;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1334

uint32_t write_size = 36;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1443

uint32_t wr_buf_size = 42;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1561

const uint32_t rd_buf_size = 10;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1644

uint32_t wr_buf_size = 42;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1747

const uint32_t rd_buf_size = 100;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1828

uint32_t wr_buf_size = 42;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1931

const uint32_t rd_buf_size = 100;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

195

const uint32_t rd_buf_size = 100;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

196

uint32_t result = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2012

uint32_t wr_buf_size = 42;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2111

const uint32_t rd_buf_size = 100;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2189

uint32_t wr_buf_size = 42;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2286

const uint32_t rd_buf_size = 100;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2340

const uint32_t rd_buf_size = 100;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2409

const uint32_t rd_buf_size = 100;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2478

const uint32_t rd_buf_size = 100;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2544

const uint32_t rd_buf_size = 10;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2617

uint32_t wr_buf_size = 42;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

265

const uint32_t wr_buf_size = 40;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2689

uint32_t rcg_count, ips1_count, ips2_count;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3192

adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3301

uint32_t response;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3395

uint32_t link_rate_in_khz;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3396

uint32_t entry = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3438

const uint32_t wr_buf_size = 40;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

396

const uint32_t wr_buf_size = 40;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4166

const uint32_t rd_buf_size = 32;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

4167

uint32_t result = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

50

uint32_t entry_count;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

51

uint32_t reserved[3];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

537

const uint32_t rd_buf_size = 20;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

538

uint32_t result = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

55

uint32_t trace_code;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

56

uint32_t tick_count;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

57

uint32_t param0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

58

uint32_t param1;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

615

uint32_t wr_buf_size = 40;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

757

uint32_t wr_buf_size = 100;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

76

static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

82

uint32_t wr_buf_count = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

910

uint32_t tbuf_size, max_entries, num_entries, first_entry, i;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

975

uint32_t state_size;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

100

uint32_t poll_timeout_us,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

109

static uint8_t *psp_get_srm(struct psp_context *psp, uint32_t *srm_version, uint32_t *srm_size)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

134

u8 *srm, uint32_t srm_size, uint32_t *srm_version)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

42

lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t size)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

53

lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t *data, uint32_t size)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

66

lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data, uint32_t size)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

74

lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

86

uint32_t poll_timeout_us,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h

73

uint32_t srm_version;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h

74

uint32_t srm_size;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1372

static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

570

uint32_t address,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

572

uint32_t size)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

587

uint32_t address,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

589

uint32_t size)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

61

uint32_t panel_id = edid_extract_panel_id(edid);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

640

uint32_t timeout_us

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1768

static uint32_t kbps_from_pbn(unsigned int pbn)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1777

return (uint32_t)kbps;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1799

static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_link_bw)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1801

uint32_t total_data_bw_efficiency_x10000 = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1802

uint32_t link_rate_per_lane_kbps = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1863

uint32_t end_to_end_bw_in_kbps = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1864

uint32_t root_link_bw_in_kbps = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1865

uint32_t virtual_channel_bw_in_kbps = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1868

uint32_t stream_kbps;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

1904

uint32_t end_link_bw = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

857

uint32_t dm_mst_get_pbn_divider(struct dc_link *link)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

859

uint32_t pbn_div_x100;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

880

uint32_t num_slices_h;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

881

uint32_t num_slices_v;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

882

uint32_t bpp_overwrite;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h

63

uint32_t dm_mst_get_pbn_divider(struct dc_link *link);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

112

static const uint32_t alpha_formats[] = {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

122

uint32_t format = plane_state->fb->format->format;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1526

uint32_t format,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1811

uint32_t formats[32];

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1906

bool amdgpu_dm_plane_is_video_format(uint32_t format)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

49

static const uint32_t rgb_formats[] = {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

66

static const uint32_t overlay_formats[] = {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

78

static const uint32_t video_formats[] = {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

781

uint32_t *formats, int max_formats)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

932

uint32_t domain;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h

67

bool amdgpu_dm_plane_is_video_format(uint32_t format);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

116

uint32_t disp_clks_in_khz[6] = {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

118

uint32_t sclks_in_khz[6] = {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

120

uint32_t mclks_in_khz[2] = { 333000, 800000 };

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

218

uint32_t i;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

244

uint32_t i;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

271

uint32_t i;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

302

uint32_t i;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c

56

void dm_trace_smu_enter(uint32_t msg_id, uint32_t param_in, unsigned int delay, struct dc_context *ctx)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c

60

void dm_trace_smu_exit(bool success, uint32_t response, struct dc_context *ctx)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

109

__field(uint32_t, conn_id)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

113

__field(uint32_t, crtc_id)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

114

__field(uint32_t, best_encoder_id)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

169

__field(uint32_t, crtc_id)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

229

__field(uint32_t, plane_id)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

233

__field(uint32_t, crtc_id)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

234

__field(uint32_t, fb_id)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

235

__field(uint32_t, fb_format)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

241

__field(uint32_t, crtc_w)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

242

__field(uint32_t, crtc_h)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

243

__field(uint32_t, src_x)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

244

__field(uint32_t, src_y)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

245

__field(uint32_t, src_w)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

246

__field(uint32_t, src_h)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

248

__field(uint32_t, pixel_blend_mode)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

46

TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

50

__field(uint32_t, reg)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

51

__field(uint32_t, value)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

604

TP_PROTO(uint32_t trace_code, uint32_t tick_count, uint32_t param0,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

605

uint32_t param1),

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

608

__field(uint32_t, trace_code)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

609

__field(uint32_t, tick_count)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

610

__field(uint32_t, param0)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

611

__field(uint32_t, param1)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

625

TP_PROTO(int crtc_index, ktime_t refresh_rate_ns, uint32_t refresh_rate_hz),

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

630

__field(uint32_t, refresh_rate_hz)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

66

TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

70

TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

79

__field(uint32_t, reads)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

80

__field(uint32_t, writes)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

81

__field(uint32_t, read_delta)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

82

__field(uint32_t, write_delta)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

84

__field(uint32_t, line)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c

188

uint32_t link_index)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c

90

uint32_t domain;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.h

34

uint32_t link_index);

sys/dev/pci/drm/amd/display/dc/basics/bw_fixed.c

80

uint32_t i = BW_FIXED_BITS_PER_FRACTIONAL_PART;

sys/dev/pci/drm/amd/display/dc/basics/conversion.c

132

uint32_t buffer_size)

sys/dev/pci/drm/amd/display/dc/basics/conversion.c

138

static uint32_t find_gcd(uint32_t a, uint32_t b)

sys/dev/pci/drm/amd/display/dc/basics/conversion.c

140

uint32_t remainder;

sys/dev/pci/drm/amd/display/dc/basics/conversion.c

150

void reduce_fraction(uint32_t num, uint32_t den,

sys/dev/pci/drm/amd/display/dc/basics/conversion.c

151

uint32_t *out_num, uint32_t *out_den)

sys/dev/pci/drm/amd/display/dc/basics/conversion.c

153

uint32_t gcd = 0;

sys/dev/pci/drm/amd/display/dc/basics/conversion.c

82

uint32_t buffer_size)

sys/dev/pci/drm/amd/display/dc/basics/conversion.c

88

uint32_t i;

sys/dev/pci/drm/amd/display/dc/basics/conversion.c

91

uint32_t reg_value =

sys/dev/pci/drm/amd/display/dc/basics/conversion.h

39

uint32_t buffer_size);

sys/dev/pci/drm/amd/display/dc/basics/conversion.h

41

void reduce_fraction(uint32_t num, uint32_t den,

sys/dev/pci/drm/amd/display/dc/basics/conversion.h

42

uint32_t *out_num, uint32_t *out_den);

sys/dev/pci/drm/amd/display/dc/basics/conversion.h

46

uint32_t buffer_size);

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

102

uint32_t mantissa,

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

103

uint32_t exponenta,

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

104

uint32_t *result)

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

106

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

107

uint32_t j = 0;

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

108

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

114

const uint32_t mantissa_mask =

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

117

const uint32_t exponenta_mask =

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

133

uint32_t mask = 1 << i;

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

142

uint32_t mask = 1 << j;

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

160

uint32_t *result)

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

162

uint32_t mantissa;

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

163

uint32_t exponenta;

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

32

uint32_t *mantissa,

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

33

uint32_t *exponenta)

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

35

uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1;

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

58

uint32_t i = 1;

sys/dev/pci/drm/amd/display/dc/basics/custom_float.c

75

uint32_t i = 1;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

2770

uint32_t int_max_clk;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

85

const uint32_t s_low = 0;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

86

const uint32_t s_mid1 = 1;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

87

const uint32_t s_mid2 = 2;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

88

const uint32_t s_mid3 = 3;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

89

const uint32_t s_mid4 = 4;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

90

const uint32_t s_mid5 = 5;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

91

const uint32_t s_mid6 = 6;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

92

const uint32_t s_high = 7;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

93

const uint32_t dmif_chunk_buff_margin = 1;

sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c

95

uint32_t max_chunks_fbc_mode = 0;

sys/dev/pci/drm/amd/display/dc/basics/vector.c

113

uint32_t capacity,

sys/dev/pci/drm/amd/display/dc/basics/vector.c

114

uint32_t struct_size)

sys/dev/pci/drm/amd/display/dc/basics/vector.c

147

uint32_t dal_vector_get_count(

sys/dev/pci/drm/amd/display/dc/basics/vector.c

155

uint32_t index)

sys/dev/pci/drm/amd/display/dc/basics/vector.c

164

uint32_t index)

sys/dev/pci/drm/amd/display/dc/basics/vector.c

182

uint32_t index)

sys/dev/pci/drm/amd/display/dc/basics/vector.c

196

static inline uint32_t calc_increased_capacity(

sys/dev/pci/drm/amd/display/dc/basics/vector.c

197

uint32_t old_capacity)

sys/dev/pci/drm/amd/display/dc/basics/vector.c

205

uint32_t position)

sys/dev/pci/drm/amd/display/dc/basics/vector.c

245

uint32_t count;

sys/dev/pci/drm/amd/display/dc/basics/vector.c

279

uint32_t dal_vector_capacity(const struct vector *vector)

sys/dev/pci/drm/amd/display/dc/basics/vector.c

284

bool dal_vector_reserve(struct vector *vector, uint32_t capacity)

sys/dev/pci/drm/amd/display/dc/basics/vector.c

32

uint32_t capacity,

sys/dev/pci/drm/amd/display/dc/basics/vector.c

33

uint32_t struct_size)

sys/dev/pci/drm/amd/display/dc/basics/vector.c

55

uint32_t count,

sys/dev/pci/drm/amd/display/dc/basics/vector.c

57

uint32_t struct_size)

sys/dev/pci/drm/amd/display/dc/basics/vector.c

59

uint32_t i;

sys/dev/pci/drm/amd/display/dc/basics/vector.c

93

uint32_t size,

sys/dev/pci/drm/amd/display/dc/basics/vector.c

95

uint32_t struct_size)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1022

uint32_t id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1028

uint32_t tbl_size, i;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1067

(uint32_t)le16_to_cpu(tbl[i].usSpreadSpectrumPercentage);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1069

(uint32_t)(le16_to_cpu(tbl[i].usSpreadRateIn10Hz) * 10);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1092

uint32_t id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1098

uint32_t table_size;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1099

uint32_t i;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1100

uint32_t id_local = SS_ID_UNKNOWN;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1144

if (id_local != (uint32_t)tbl->asSS_Info[i].ucSS_Id)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1159

(uint32_t)le16_to_cpu(tbl->asSS_Info[i].usSpreadSpectrumPercentage);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1166

(uint32_t)tbl->asSS_Info[i].ucSS_Range * 10000;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1276

~(uint32_t)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1279

~(uint32_t)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

132

static uint8_t get_number_of_objects(struct bios_parser *bp, uint32_t offset)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1322

(uint32_t) (ATOM_PANEL_MISC_GREY_LEVEL &

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

136

uint32_t object_table_offset = bp->object_info_tbl_offset + offset;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1394

~(uint32_t)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1397

~(uint32_t)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1456

(uint32_t) (ATOM_PANEL_MISC_V13_GREY_LEVEL &

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1512

uint32_t offset;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1544

static uint32_t get_ss_entry_number(

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1546

uint32_t id);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1547

static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1(

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1549

uint32_t id);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1550

static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_V3_1(

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1552

uint32_t id);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1553

static uint32_t get_ss_entry_number_from_ss_info_tbl(

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1555

uint32_t id);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1566

static uint32_t bios_parser_get_ss_entry_number(

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1571

uint32_t ss_id = 0;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1619

static uint32_t get_ss_entry_number_from_ss_info_tbl(

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1621

uint32_t id)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1625

uint32_t table_size;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1626

uint32_t i;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1627

uint32_t number = 0;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1628

uint32_t id_local = SS_ID_UNKNOWN;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

165

uint32_t connector_table_offset = bp->object_info_tbl_offset

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1672

if (id_local == (uint32_t)tbl->asSS_Info[i].ucSS_Id) {

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1691

static uint32_t get_ss_entry_number(struct bios_parser *bp, uint32_t id)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1709

static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1(

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1711

uint32_t id)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1715

uint32_t size;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1716

uint32_t i;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1750

static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_V3_1(

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1752

uint32_t id)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1754

uint32_t number = 0;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1757

uint32_t size;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1758

uint32_t i;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1799

uint32_t gpio_id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1804

uint32_t count = 0;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1805

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1831

(uint32_t) le16_to_cpu(header->asGPIO_Pin[i].usGpioPin_AIndex);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1836

info->mask = (uint32_t) (1 <<

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1853

uint32_t count = 0;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

186

struct graphics_object_id object_id, uint32_t index,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

189

uint32_t number;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1972

uint32_t offset;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

1974

uint32_t i;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

2015

static uint32_t get_src_obj_list(struct bios_parser *bp, ATOM_OBJECT *object,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

2018

uint32_t offset;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

2121

(uint32_t) GET_DATA_TABLE_MAJOR_REVISION(atom_data_tbl);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

2123

(uint32_t) GET_DATA_TABLE_MINOR_REVISION(atom_data_tbl);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

2126

static uint32_t signal_to_ss_id(enum as_signal_type signal)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

2128

uint32_t clk_id_ss = 0;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

2152

static uint32_t get_support_mask_for_device_id(struct device_id device_id)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

2155

uint32_t enum_id = device_id.enum_id;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

218

uint32_t offset;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

2252

uint32_t i;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

2402

uint32_t i;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

293

uint32_t offset;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

327

uint32_t device_tag_index,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

462

uint32_t id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

463

uint32_t index,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

473

uint32_t index;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

556

uint32_t index;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

59

static uint32_t get_src_obj_list(struct bios_parser *bp, ATOM_OBJECT *object,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

639

(uint32_t) (le32_to_cpu(firmware_info->ulGPUPLL_OutputFreq) * 10);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

646

uint32_t id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

647

uint32_t index,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

652

uint32_t table_size;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

653

uint32_t i;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

654

uint32_t table_index = 0;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

69

static uint32_t signal_to_ss_id(enum as_signal_type signal);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

70

static uint32_t get_support_mask_for_device_id(struct device_id device_id);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

718

(uint32_t)le16_to_cpu(tbl[i].usSpreadSpectrumPercentage);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

720

(uint32_t)(le16_to_cpu(tbl[i].usSpreadRateIn10Hz) * 10);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

861

uint32_t mask = get_support_mask_for_device_id(id);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

870

uint32_t offset;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

902

uint32_t id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

906

uint32_t id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

924

uint32_t index,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

929

uint32_t clk_id_ss = 0;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

979

uint32_t id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser.c

996

uint32_t id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1069

uint32_t index,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

130

(uint32_t) atom_data_tbl->format_revision & 0x3f;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

132

(uint32_t) atom_data_tbl->content_revision & 0x3f;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1544

static uint32_t get_support_mask_for_device_id(struct device_id device_id)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1547

uint32_t enum_id = device_id.enum_id;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1590

uint32_t mask = get_support_mask_for_device_id(id);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

1603

static uint32_t bios_parser_get_ss_entry_number(

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

205

struct graphics_object_id object_id, uint32_t index,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

2179

uint32_t offset;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

2216

uint32_t offset;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

2252

uint32_t offset;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

2338

uint32_t offset;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

2514

uint32_t i;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

2731

uint32_t i;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

2893

uint32_t i;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

3545

uint32_t rev_major,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

3546

uint32_t rev_minor,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

3550

uint32_t dc_golden_offset = 0;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

389

uint32_t offset;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

464

uint32_t count = 0;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

531

uint32_t offset;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

608

uint32_t offset;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

655

uint32_t gpio_id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

660

uint32_t count = 0;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

661

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

688

(uint32_t) le16_to_cpu(

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

694

info->mask = (uint32_t) (1 <<

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

765

uint32_t device_tag_index,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

808

uint32_t id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

809

uint32_t index,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

896

uint32_t id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

897

uint32_t index,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

976

uint32_t id,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser2.c

977

uint32_t index,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.c

100

static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.c

102

uint32_t bios_encoder_id = gpu_id_from_bios_object_id(bios_object_id);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.c

173

uint32_t bios_object_id)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.c

175

uint32_t bios_connector_id = gpu_id_from_bios_object_id(bios_object_id);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.c

227

static enum generic_id generic_id_from_bios_object_id(uint32_t bios_object_id)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.c

229

uint32_t bios_generic_id = gpu_id_from_bios_object_id(bios_object_id);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.c

251

static uint32_t id_from_bios_object_id(enum object_type type,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.c

252

uint32_t bios_object_id)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.c

258

return (uint32_t)encoder_id_from_bios_object_id(bios_object_id);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.c

260

return (uint32_t)connector_id_from_bios_object_id(

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.c

269

struct graphics_object_id object_id_from_bios_object_id(uint32_t bios_object_id)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.c

29

static enum object_type object_type_from_bios_object_id(uint32_t bios_object_id)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.c

31

uint32_t bios_object_type = (bios_object_id & OBJECT_TYPE_MASK)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.c

59

static enum object_enum_id enum_id_from_bios_object_id(uint32_t bios_object_id)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.c

61

uint32_t bios_enum_id =

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.c

95

static uint32_t gpu_id_from_bios_object_id(uint32_t bios_object_id)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_common.h

32

struct graphics_object_id object_id_from_bios_object_id(uint32_t bios_object_id);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_helper.c

37

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_helper.c

38

uint32_t size)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_helper.c

60

uint32_t acc_mode;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_helper.c

68

uint32_t state)

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_helper.c

78

uint32_t critial_state = state ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_helper.h

31

uint8_t *bios_get_image(struct dc_bios *bp, uint32_t offset,

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_helper.h

32

uint32_t size);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_helper.h

35

void bios_set_scratch_acc_mode_change(struct dc_bios *bios, uint32_t state);

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_types_internal.h

33

uint32_t major;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_types_internal.h

34

uint32_t minor;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_types_internal.h

57

uint32_t object_info_tbl_offset;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_types_internal2.h

35

uint32_t major;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_types_internal2.h

36

uint32_t minor;

sys/dev/pci/drm/amd/display/dc/bios/bios_parser_types_internal2.h

59

uint32_t object_info_tbl_offset;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1053

uint32_t pll_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1123

uint32_t pll_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

120

uint32_t version =

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1215

uint32_t pll_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1525

uint32_t pixel_clock_10KHz_in = bp_params->pixel_clock / 10;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1565

uint32_t pixel_clk_10_kHz_in = bp_params->pixel_clock / 10;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1623

uint32_t pixel_clock,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1628

uint32_t pixel_clock,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1654

uint32_t pixel_clock,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1672

uint32_t pixel_clock,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1693

uint32_t pixel_clock,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1796

uint32_t dtd_version =

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2119

uint32_t atom_pll_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2150

uint32_t atom_pll_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2175

(uint32_t)(le32_to_cpu(params.sPCLKInput.ulDispEngClkFreq) * 10);

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2394

uint32_t atom_pll_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

2395

uint32_t atom_clock_type;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

40

(uint32_t *)&params, sizeof(params)) == 0)

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

557

uint32_t pll_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

691

uint32_t ref_clk_src_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

83

static uint32_t bios_cmd_table_para_revision(void *dev,

sys/dev/pci/drm/amd/display/dc/bios/command_table.c

84

uint32_t index)

sys/dev/pci/drm/amd/display/dc/bios/command_table.h

58

uint32_t pixel_clock,

sys/dev/pci/drm/amd/display/dc/bios/command_table.h

63

uint32_t pixel_clock,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

327

static struct dc_link *get_link_by_phy_id(struct dc *p_dc, uint32_t phy_id)

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

486

uint32_t pll_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

52

(uint32_t *)&params, sizeof(params)) == 0)

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

591

uint32_t dtd_version =

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

64

static uint32_t bios_cmd_table_para_revision(void *dev,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

65

uint32_t index)

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

919

uint32_t atom_pll_id;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

920

uint32_t atom_clock_type;

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

96

uint32_t version =

sys/dev/pci/drm/amd/display/dc/bios/command_table2.h

58

uint32_t pixel_clock,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.h

63

uint32_t pixel_clock,

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

146

uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom(

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

214

uint32_t *ref_clk_src_id)

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

356

bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.h

44

uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom(

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.h

55

uint32_t *ref_clk_src_id);

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.h

68

bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id);

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

170

uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2(

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.c

199

uint32_t *ref_clk_src_id)

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.h

44

uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2(

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper2.h

50

uint32_t *ref_clk_src_id);

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper_struct.h

38

uint32_t (*encoder_mode_bp_to_atom)(enum amd_signal_type s,

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper_struct.h

41

uint32_t *atom_engine_id);

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper_struct.h

47

uint32_t *atom_pll_id);

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper_struct.h

50

uint32_t *ref_clk_src_id);

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper_struct.h

62

uint32_t *atom_clock_type);

sys/dev/pci/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c

107

uint32_t *atom_pll_id)

sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c

106

uint32_t *atom_pll_id)

sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c

205

uint32_t *atom_clock_type)

sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c

104

uint32_t *atom_pll_id)

sys/dev/pci/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c

203

uint32_t *atom_clock_type)

sys/dev/pci/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c

63

uint32_t *atom_pll_id)

sys/dev/pci/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c

63

uint32_t *atom_pll_id)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

165

uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

167

uint32_t max_pix_clk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h

39

uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

100

uint32_t vertical_blank_time = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

101

uint32_t vertical_total_min = stream->timing.v_total;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

224

(uint32_t) div64_s64(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

92

uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

95

uint32_t min_vertical_blank_time = -1;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

99

uint32_t vertical_blank_in_pixels = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.h

42

uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

106

uint32_t result;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

85

static uint32_t rv1_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

87

uint32_t res_val = VBIOSSMC_Status_BUSY;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

131

uint32_t dppclk_wdivider = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

132

uint32_t dispclk_wdivider = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

133

uint32_t current_dispclk_wdivider;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

134

uint32_t i;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

154

uint32_t fifo_level;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

187

uint32_t fifo_level;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

428

uint32_t dispclk_wdivider;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

429

uint32_t dppclk_wdivider;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

536

uint32_t pll_req_reg;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

73

uint32_t dentist_get_did_from_divider(int divider)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

75

uint32_t divider_id;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

46

uint32_t dentist_get_did_from_divider(int divider);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h

41

uint32_t CLK1_CLK0_CURRENT_CNT; /* DPREFCLK */

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

103

uint32_t result;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

80

static uint32_t rn_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

82

uint32_t res_val = VBIOSSMC_Status_BUSY;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

178

uint32_t pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

81

static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

85

uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

112

bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

114

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

144

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

163

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

179

void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

187

void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

212

unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

214

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

217

uint32_t param = (clk << 16) | freq_mhz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

230

unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

232

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

235

uint32_t param = (clk << 16) | freq_mhz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

261

unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

263

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

266

uint32_t param = (clk << 16) | dpm_level;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

279

unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

281

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

284

uint32_t param = clk << 16;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

296

void dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

304

void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

315

uint32_t param = (cache_timer_scale << 7) | (cache_timer_delay << 1) | (enable ? 1 : 0);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

54

static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

56

const uint32_t initial_max_retries = max_retries;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

57

uint32_t reg = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

77

static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

79

uint32_t result;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

33

bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

37

void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

38

void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

41

unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

42

unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

43

unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

44

unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

45

void dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

46

void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_smu11_driver_if.h

59

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.c

31

uint32_t dcn30m_set_smartmux_switch(struct clk_mgr *clk_mgr_base, uint32_t pins_to_set)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.h

29

uint32_t dcn30m_set_smartmux_switch(struct clk_mgr *clk_mgr_base, uint32_t pins_to_set);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

108

uint32_t dcn30m_smu_set_smart_mux_switch(struct clk_mgr_internal *clk_mgr, uint32_t pins_to_set)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

110

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

53

static uint32_t dcn30m_smu_wait_for_response(struct clk_mgr_internal *clk_mgr,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

56

uint32_t reg = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

77

uint32_t msg_id, uint32_t param_in, uint32_t *param_out)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

79

uint32_t result;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.h

33

uint32_t dcn30m_smu_set_smart_mux_switch(struct clk_mgr_internal *clk_mgr, uint32_t pins_to_set);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

102

uint32_t result;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

218

void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

255

void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

263

void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

80

static uint32_t dcn301_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

82

uint32_t res_val = VBIOSSMC_Status_BUSY;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

100

uint32_t DispClocks[VG_NUM_DISPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

101

uint32_t DppClocks[VG_NUM_DPPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

102

uint32_t SocClocks[VG_NUM_SOCCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

103

uint32_t IspiClocks[VG_NUM_ISPICLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

104

uint32_t IspxClocks[VG_NUM_ISPXCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

107

uint32_t SocVoltage[VG_NUM_SOC_VOLTAGE_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

111

uint32_t MinGfxClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

112

uint32_t MaxGfxClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

133

uint32_t MmHubPadding[7]; // SMU internal use

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

146

uint32_t data;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

156

void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

159

void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

160

void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

32

uint32_t fclk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

33

uint32_t memclk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

34

uint32_t voltage;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

38

uint32_t vclk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

39

uint32_t dclk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

79

uint32_t MmHubPadding[7]; // SMU internal use

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

99

uint32_t DcfClocks[VG_NUM_DCFCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

530

static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

532

uint32_t max = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

566

uint32_t max_dispclk = 0, max_dppclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

299

uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

520

static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

522

uint32_t max = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

535

const uint32_t clocks[],

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

562

uint32_t max_dispclk = 0, max_dppclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

107

uint32_t result;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

240

void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

284

void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

293

void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

85

static uint32_t dcn31_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

87

uint32_t res_val = VBIOSSMC_Status_BUSY;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

121

uint32_t FClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

122

uint32_t MemClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

123

uint32_t Voltage;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

131

uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

132

uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

133

uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

134

uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

135

uint32_t VClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

136

uint32_t DClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

137

uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

147

uint32_t MinGfxClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

148

uint32_t MaxGfxClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

233

uint32_t MmHubPadding[7]; // SMU internal use

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

251

uint32_t data;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

260

void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

263

void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

264

void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

35

uint32_t numFractionalBits;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

76

uint32_t MmHubPadding[7]; // SMU internal use

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

240

uint32_t ssc_enable;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

250

uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

716

static inline bool is_valid_clock_value(uint32_t clock_value)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

736

static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

738

uint32_t max = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

755

uint32_t max_pstate = 0, max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

782

uint32_t min_fclk = clock_table->DfPstateTable[0].FClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

899

uint32_t clock_source;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h

46

uint32_t ss_divider;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h

47

uint32_t ss_percentage[DCN314_NUM_CLOCK_SOURCES];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

101

static uint32_t dcn314_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

103

uint32_t res_val = VBIOSSMC_Status_BUSY;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

123

uint32_t result;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

259

void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

303

void dcn314_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

312

void dcn314_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

102

void dcn314_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

103

void dcn314_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

40

uint32_t FClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

41

uint32_t MemClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

42

uint32_t Voltage;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

50

uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

51

uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

52

uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

53

uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

54

uint32_t VClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

55

uint32_t DClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

56

uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

66

uint32_t MinGfxClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

67

uint32_t MaxGfxClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

73

uint32_t MmHubPadding[7]; // SMU internal use

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

90

uint32_t data;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

99

void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

487

uint32_t max_pstate = clock_table->NumDfPstatesEnabled - 1;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

114

static uint32_t dcn315_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

116

uint32_t res_val = VBIOSSMC_Status_BUSY;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

136

uint32_t result;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

137

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

138

uint32_t read_back_data;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

253

void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

296

void dcn315_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

305

void dcn315_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

111

uint32_t data;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

119

void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

121

void dcn315_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

122

void dcn315_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

62

uint32_t FClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

63

uint32_t MemClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

64

uint32_t Voltage;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

70

uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

71

uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

72

uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

73

uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

74

uint32_t VClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

75

uint32_t DClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

76

uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

84

uint32_t MinGfxClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

85

uint32_t MaxGfxClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

91

uint32_t MmHubPadding[7]; // SMU internal use

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

446

static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

448

uint32_t max = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

461

const uint32_t clocks[],

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

489

uint32_t max_dispclk = 0, max_dppclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

100

static uint32_t dcn316_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

102

uint32_t res_val = VBIOSSMC_Status_BUSY;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

122

uint32_t result;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

228

void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

261

void dcn316_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

270

void dcn316_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

119

uint32_t data;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

127

void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

129

void dcn316_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

130

void dcn316_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

68

uint32_t FClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

69

uint32_t MemClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

70

uint32_t Voltage;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

78

uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

79

uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

80

uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

81

uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

82

uint32_t VClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

83

uint32_t DClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

84

uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

92

uint32_t MinGfxClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

93

uint32_t MaxGfxClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

99

uint32_t MmHubPadding[7]; // SMU internal use

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

138

uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

271

uint32_t tg_mask = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

352

uint32_t new_disp_divider = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

353

uint32_t new_dispclk_wdivider = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

354

uint32_t old_dispclk_wdivider = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

355

uint32_t i;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

356

uint32_t dentist_dispclk_wdivider_readback = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

373

uint32_t fifo_level;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

400

uint32_t temp_disp_divider = dentist_get_divider_from_did(126);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

401

uint32_t temp_dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / temp_disp_divider;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

429

uint32_t fifo_level;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

477

uint32_t dispclk_wdivider;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

564

uint32_t pix_clk_list[MAX_PIPES] = {0};

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

848

static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

851

uint32_t pll_req_reg = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

876

uint32_t dprefclk_did = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

877

uint32_t dcfclk_did = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

878

uint32_t dtbclk_did = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

879

uint32_t dispclk_did = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

880

uint32_t dppclk_did = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

881

uint32_t target_div = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

107

static uint32_t dcn32_smu_wait_for_response_delay(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries, unsigned int *total_delay_us)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

109

uint32_t reg = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

129

static bool dcn32_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out, unsigned int *total_delay_us)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

171

uint32_t param = (num_ways << 1) | (num_ways > 0);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

212

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

215

uint32_t param = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

227

uint32_t clk)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

281

unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

283

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

287

uint32_t param = (clk << 16) | freq_mhz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

50

static uint32_t dcn32_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

52

const uint32_t initial_max_retries = max_retries;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

53

uint32_t reg = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

72

static bool dcn32_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h

43

unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h

47

uint32_t Spare[16];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h

49

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1015

static inline uint32_t calc_dram_speed_mts(const MemPstateTable_t *entry)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1026

uint32_t max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1027

uint32_t max_pstate = 0, max_dram_speed_mts = 0, min_dram_speed_mts = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1028

uint32_t num_memps, num_fclk, num_dcfclk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1035

uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1047

uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

259

uint32_t tg_mask = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

346

uint32_t host_router_bw_kbps[MAX_HOST_ROUTERS_NUM] = { 0 };

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

710

uint32_t ssc_enable;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

723

uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

851

uint32_t clock_source = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

980

static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

982

uint32_t max = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

993

static inline bool is_valid_clock_value(uint32_t clock_value)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

40

uint32_t ss_divider;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

41

uint32_t ss_percentage[NUM_CLOCK_SOURCES];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

104

uint32_t hr_id : 16;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

105

uint32_t bw_mbps : 16;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

107

uint32_t all;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

115

static uint32_t dcn35_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

117

uint32_t res_val = VBIOSSMC_Status_BUSY;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

140

uint32_t result;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

278

void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

325

void dcn35_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

334

void dcn35_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

500

void dcn35_smu_notify_host_router_bw(struct clk_mgr_internal *clk_mgr, uint32_t hr_id, uint32_t bw_kbps)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

104

uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

105

uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

106

uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

107

uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

108

uint32_t VClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

109

uint32_t DClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

110

uint32_t VPEClocks[NUM_VPE_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

111

uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

112

uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

113

uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

125

uint32_t MinGfxClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

126

uint32_t MaxGfxClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

130

uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

131

uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

132

uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

133

uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

134

uint32_t VClocks0[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

135

uint32_t VClocks1[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

136

uint32_t DClocks0[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

137

uint32_t DClocks1[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

138

uint32_t VPEClocks[NUM_VPE_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

139

uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

140

uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

141

uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

151

uint32_t MinGfxClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

152

uint32_t MaxGfxClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

171

uint32_t MmHubPadding[7]; // SMU internal use

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

193

uint32_t data;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

202

void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

205

void dcn35_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

206

void dcn35_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

218

void dcn35_smu_notify_host_router_bw(struct clk_mgr_internal *clk_mgr, uint32_t hr_id, uint32_t bw_kbps);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

73

uint32_t MmHubPadding[7]; // SMU internal use

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

94

uint32_t UClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

95

uint32_t MemClk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

96

uint32_t Voltage;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1250

static uint32_t dcn401_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1253

uint32_t pll_req_reg = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1486

uint32_t dispclk_wdivider;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

165

uint32_t ret = dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

337

uint32_t dprefclk_did = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

338

uint32_t dcfclk_did = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

339

uint32_t dtbclk_did = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

340

uint32_t dispclk_did = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

341

uint32_t dppclk_did = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

342

uint32_t fclk_did = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

343

uint32_t target_div = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

466

uint32_t pix_clk_list[MAX_PIPES] = {0};

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

617

uint32_t new_disp_divider = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

618

uint32_t new_dispclk_wdivider = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

619

uint32_t dentist_dispclk_wdivider_readback = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

13

uint32_t num_displays;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

17

uint32_t ppclk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

20

uint32_t *response;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

24

uint32_t ppclk;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

27

uint32_t *response;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

112

static bool dcn401_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out, unsigned int *total_delay_us)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

164

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

183

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

217

uint32_t param = (num_ways << 1) | (num_ways > 0);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

223

void dcn401_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

231

void dcn401_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

257

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

260

uint32_t param = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

271

static bool dcn401_smu_wait_hard_min_status(struct clk_mgr_internal *clk_mgr, uint32_t ppclk)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

301

unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

303

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

307

uint32_t param = (clk << 16) | freq_mhz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

340

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

344

uint32_t param = (fclk_freq_mhz << 16) | uclk_freq_mhz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

362

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

366

uint32_t param = (fclk_freq_mhz << 16) | uclk_freq_mhz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

37

static uint32_t dcn401_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

384

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

388

uint32_t param = (fclk_freq_mhz << 16) | uclk_freq_mhz;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

39

uint32_t reg = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

398

void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

406

void dcn401_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

439

unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

441

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

444

uint32_t param = (clk << 16) | dpm_level;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

457

unsigned int dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

459

uint32_t response = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

462

uint32_t param = clk << 16;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

55

static bool dcn401_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

92

static uint32_t dcn401_smu_wait_for_response_delay(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries, unsigned int *total_delay_us)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

94

uint32_t reg = 0;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

19

void dcn401_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

20

void dcn401_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

23

unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

35

void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

36

void dcn401_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

38

unsigned int dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

39

unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level);

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_smu14_driver_if.h

48

uint32_t Spare[16];

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_smu14_driver_if.h

50

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/display/dc/core/dc.c

1468

uint32_t requested_pix_clk_100hz =

sys/dev/pci/drm/amd/display/dc/core/dc.c

159

uint32_t i;

sys/dev/pci/drm/amd/display/dc/core/dc.c

167

static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links)

sys/dev/pci/drm/amd/display/dc/core/dc.c

170

uint32_t count = 0;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1910

uint32_t numOdmPipes = 1;

sys/dev/pci/drm/amd/display/dc/core/dc.c

1911

uint32_t id_src[4] = {0};

sys/dev/pci/drm/amd/display/dc/core/dc.c

1926

uint32_t pixels_per_cycle = se->funcs->get_pixels_per_cycle(se);

sys/dev/pci/drm/amd/display/dc/core/dc.c

195

uint32_t num_virtual_links)

sys/dev/pci/drm/amd/display/dc/core/dc.c

2203

uint32_t prev_dsc_changed = context->streams[i]->update_flags.bits.dsc_changed;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3041

uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3333

uint32_t old_dsc_enabled = stream->timing.flags.DSC;

sys/dev/pci/drm/amd/display/dc/core/dc.c

3334

uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

4533

uint32_t i;

sys/dev/pci/drm/amd/display/dc/core/dc.c

517

uint32_t *refresh_rate)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5407

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5408

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5483

uint32_t i;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5498

enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5881

uint32_t link_index,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5972

uint32_t link_index,

sys/dev/pci/drm/amd/display/dc/core/dc.c

6017

uint32_t link_index,

sys/dev/pci/drm/amd/display/dc/core/dc.c

6061

void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6082

uint32_t hpd_int_enable)

sys/dev/pci/drm/amd/display/dc/core/dc.c

6342

uint32_t i;

sys/dev/pci/drm/amd/display/dc/core/dc.c

6354

uint32_t i;

sys/dev/pci/drm/amd/display/dc/core/dc.c

772

uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1121

uint32_t color_value = MAX_TG_COLOR_VALUE;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

221

uint32_t *array_size)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

336

uint32_t color_value = MAX_TG_COLOR_VALUE;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

386

uint32_t color_value = MAX_TG_COLOR_VALUE;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

435

uint32_t color_value = MAX_TG_COLOR_VALUE;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

461

uint32_t color_value = MAX_TG_COLOR_VALUE;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

498

uint32_t color_value = MAX_TG_COLOR_VALUE;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

526

uint32_t color_value = MAX_TG_COLOR_VALUE;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

570

uint32_t color_value = MAX_TG_COLOR_VALUE;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

588

const uint32_t MCACHE_ID_UNASSIGNED = 0xF;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

604

uint32_t first_id = pipe_ctx->mcache_regs.main.p0.mcache_id_first;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

605

uint32_t second_id = pipe_ctx->mcache_regs.main.p0.mcache_id_second;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

625

uint32_t assigned_id = (first_id != MCACHE_ID_UNASSIGNED) ? first_id : second_id;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

709

uint32_t color_value = MAX_TG_COLOR_VALUE;

sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c

46

if (link_enc && ((uint32_t)stream->link->connector_signal & link_enc->output_signals)) {

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

122

uint32_t dc_link_bandwidth_kbps(

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

129

uint32_t dc_link_required_hblank_size_bytes(

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

137

void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

142

void dc_restore_link_res_map(const struct dc *dc, uint32_t *map)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

175

uint32_t link_index,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

306

uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

312

struct dc_link_settings *link_setting, uint32_t req_bw)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

39

struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

434

uint32_t *backlight_millinits_avg,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

435

uint32_t *backlight_millinits_peak)

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

451

uint32_t backlight_millinits,

sys/dev/pci/drm/amd/display/dc/core/dc_link_exports.c

452

uint32_t transition_time_in_ms)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2197

uint32_t left_edge_extra_pixel_count;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3589

uint32_t pix_clk = timing->pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3590

uint32_t normalized_pix_clk = pix_clk;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3641

uint32_t numPipes = 1;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3642

uint32_t id_src[4] = {0};

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4402

uint32_t pixel_encoding = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4721

uint32_t asic_blank_start = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4722

uint32_t asic_blank_end = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4723

uint32_t v_update = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

562

uint32_t base60_refresh_rates[] = {10, 20, 5};

sys/dev/pci/drm/amd/display/dc/core/dc_stat.c

83

void dc_stat_get_dmub_dataout(const struct dc *dc, uint32_t *dataout)

sys/dev/pci/drm/amd/display/dc/core/dc_state.c

1069

uint32_t i;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

551

uint32_t dwb_pipe_inst)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

588

uint32_t dwb_pipe_inst)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

642

uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

68

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

701

uint32_t *v_blank_start,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

702

uint32_t *v_blank_end,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

703

uint32_t *h_position,

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

704

uint32_t *v_position)

sys/dev/pci/drm/amd/display/dc/dc.h

1017

uint32_t edid_read_retry_times;

sys/dev/pci/drm/amd/display/dc/dc.h

1075

uint32_t ips_skip_crtc_disable_mask;

sys/dev/pci/drm/amd/display/dc/dc.h

1078

uint32_t fixed_vs_aux_delay_config_wa;

sys/dev/pci/drm/amd/display/dc/dc.h

108

uint32_t per_pixel_alpha : 1;

sys/dev/pci/drm/amd/display/dc/dc.h

1085

uint32_t subvp_extra_lines;

sys/dev/pci/drm/amd/display/dc/dc.h

1092

uint32_t mst_start_top_delay;

sys/dev/pci/drm/amd/display/dc/dc.h

110

uint32_t argb8888 : 1;

sys/dev/pci/drm/amd/display/dc/dc.h

111

uint32_t nv12 : 1;

sys/dev/pci/drm/amd/display/dc/dc.h

1113

uint32_t fpo_vactive_margin_us;

sys/dev/pci/drm/amd/display/dc/dc.h

112

uint32_t fp16 : 1;

sys/dev/pci/drm/amd/display/dc/dc.h

1120

uint32_t fpo_vactive_min_active_margin_us;

sys/dev/pci/drm/amd/display/dc/dc.h

1121

uint32_t fpo_vactive_max_blank_us;

sys/dev/pci/drm/amd/display/dc/dc.h

113

uint32_t p010 : 1;

sys/dev/pci/drm/amd/display/dc/dc.h

1136

uint32_t pwm_freq;

sys/dev/pci/drm/amd/display/dc/dc.h

114

uint32_t ayuv : 1;

sys/dev/pci/drm/amd/display/dc/dc.h

1141

uint32_t dml21_force_pstate_method_values[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/dc.h

1142

uint32_t dml21_disable_pstate_method_mask;

sys/dev/pci/drm/amd/display/dc/dc.h

1159

uint32_t acpi_transition_bitmasks[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/dc.h

120

uint32_t argb8888;

sys/dev/pci/drm/amd/display/dc/dc.h

121

uint32_t nv12;

sys/dev/pci/drm/amd/display/dc/dc.h

122

uint32_t fp16;

sys/dev/pci/drm/amd/display/dc/dc.h

1223

uint32_t *dcn_reg_offsets;

sys/dev/pci/drm/amd/display/dc/dc.h

1224

uint32_t *nbio_reg_offsets;

sys/dev/pci/drm/amd/display/dc/dc.h

1225

uint32_t *clk_reg_offsets;

sys/dev/pci/drm/amd/display/dc/dc.h

1262

uint32_t min_luminance;

sys/dev/pci/drm/amd/display/dc/dc.h

1263

uint32_t max_luminance;

sys/dev/pci/drm/amd/display/dc/dc.h

1264

uint32_t maximum_content_light_level;

sys/dev/pci/drm/amd/display/dc/dc.h

1265

uint32_t maximum_frame_average_light_level;

sys/dev/pci/drm/amd/display/dc/dc.h

128

uint32_t argb8888;

sys/dev/pci/drm/amd/display/dc/dc.h

129

uint32_t nv12;

sys/dev/pci/drm/amd/display/dc/dc.h

130

uint32_t fp16;

sys/dev/pci/drm/amd/display/dc/dc.h

1305

uint32_t sdr_ref_white_level;

sys/dev/pci/drm/amd/display/dc/dc.h

1315

uint32_t initialized:1; /*if 3dlut is went through color module for initialization */

sys/dev/pci/drm/amd/display/dc/dc.h

1316

uint32_t rmu_idx_valid:1; /*if mux settings are valid*/

sys/dev/pci/drm/amd/display/dc/dc.h

1317

uint32_t rmu_mux_num:3; /*index of mux to use*/

sys/dev/pci/drm/amd/display/dc/dc.h

1318

uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/

sys/dev/pci/drm/amd/display/dc/dc.h

1319

uint32_t mpc_rmu1_mux:4;

sys/dev/pci/drm/amd/display/dc/dc.h

1320

uint32_t mpc_rmu2_mux:4;

sys/dev/pci/drm/amd/display/dc/dc.h

1321

uint32_t reserved:15;

sys/dev/pci/drm/amd/display/dc/dc.h

1323

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/dc.h

133

uint32_t min_width;

sys/dev/pci/drm/amd/display/dc/dc.h

134

uint32_t min_height;

sys/dev/pci/drm/amd/display/dc/dc.h

1380

uint32_t addr_update:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1382

uint32_t dcc_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1383

uint32_t color_space_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1384

uint32_t horizontal_mirror_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1385

uint32_t per_pixel_alpha_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1386

uint32_t global_alpha_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1387

uint32_t hdr_mult:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1388

uint32_t rotation_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1389

uint32_t swizzle_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1390

uint32_t scaling_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1391

uint32_t position_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1392

uint32_t in_transfer_func_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1393

uint32_t input_csc_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1394

uint32_t coeff_reduction_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1395

uint32_t pixel_format_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1396

uint32_t plane_size_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1397

uint32_t gamut_remap_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1400

uint32_t new_plane:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1401

uint32_t bpp_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1402

uint32_t gamma_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1403

uint32_t bandwidth_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1404

uint32_t clock_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1405

uint32_t stereo_format_change:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1406

uint32_t lut_3d:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1407

uint32_t tmz_changed:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1408

uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */

sys/dev/pci/drm/amd/display/dc/dc.h

1409

uint32_t full_update:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1410

uint32_t sdr_white_level_nits:1;

sys/dev/pci/drm/amd/display/dc/dc.h

1413

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/dc.h

1646

uint32_t dongle_max_pix_clk;

sys/dev/pci/drm/amd/display/dc/dc.h

1694

uint32_t phy_transition_bitmask;

sys/dev/pci/drm/amd/display/dc/dc.h

1756

uint32_t *dcn_reg_offsets;

sys/dev/pci/drm/amd/display/dc/dc.h

1757

uint32_t *nbio_reg_offsets;

sys/dev/pci/drm/amd/display/dc/dc.h

1758

uint32_t *clk_reg_offsets;

sys/dev/pci/drm/amd/display/dc/dc.h

1833

uint32_t otg_inst;

sys/dev/pci/drm/amd/display/dc/dc.h

1834

uint32_t otg_underflow;

sys/dev/pci/drm/amd/display/dc/dc.h

1835

uint32_t h_position;

sys/dev/pci/drm/amd/display/dc/dc.h

1836

uint32_t v_position;

sys/dev/pci/drm/amd/display/dc/dc.h

1837

uint32_t otg_frame_count;

sys/dev/pci/drm/amd/display/dc/dc.h

1839

uint32_t hubp_underflow;

sys/dev/pci/drm/amd/display/dc/dc.h

1840

uint32_t hubp_in_blank;

sys/dev/pci/drm/amd/display/dc/dc.h

1841

uint32_t hubp_readline;

sys/dev/pci/drm/amd/display/dc/dc.h

1842

uint32_t det_config_error;

sys/dev/pci/drm/amd/display/dc/dc.h

1844

uint32_t curr_det_sizes[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/dc.h

1845

uint32_t target_det_sizes[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/dc.h

1846

uint32_t compbuf_config_error;

sys/dev/pci/drm/amd/display/dc/dc.h

1938

uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);

sys/dev/pci/drm/amd/display/dc/dc.h

1945

uint32_t dc_bandwidth_in_kbps_from_timing(

sys/dev/pci/drm/amd/display/dc/dc.h

1955

struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);

sys/dev/pci/drm/amd/display/dc/dc.h

204

uint32_t dma_3d_lut : 1; /*< DMA mode support for 3D LUT */

sys/dev/pci/drm/amd/display/dc/dc.h

206

uint32_t swizzle_3d_rgb : 1;

sys/dev/pci/drm/amd/display/dc/dc.h

2069

uint32_t link_index,

sys/dev/pci/drm/amd/display/dc/dc.h

207

uint32_t swizzle_3d_bgr : 1;

sys/dev/pci/drm/amd/display/dc/dc.h

208

uint32_t linear_1d : 1;

sys/dev/pci/drm/amd/display/dc/dc.h

211

uint32_t unorm_12msb : 1;

sys/dev/pci/drm/amd/display/dc/dc.h

212

uint32_t unorm_12lsb : 1;

sys/dev/pci/drm/amd/display/dc/dc.h

213

uint32_t float_fp1_5_10 : 1;

sys/dev/pci/drm/amd/display/dc/dc.h

216

uint32_t order_rgba : 1;

sys/dev/pci/drm/amd/display/dc/dc.h

217

uint32_t order_bgra : 1;

sys/dev/pci/drm/amd/display/dc/dc.h

2170

uint32_t dc_link_bandwidth_kbps(

sys/dev/pci/drm/amd/display/dc/dc.h

2177

uint32_t channel_count;

sys/dev/pci/drm/amd/display/dc/dc.h

2178

uint32_t sample_rate_hz;

sys/dev/pci/drm/amd/display/dc/dc.h

2188

uint32_t dc_link_required_hblank_size_bytes(

sys/dev/pci/drm/amd/display/dc/dc.h

2206

void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);

sys/dev/pci/drm/amd/display/dc/dc.h

221

uint32_t dim_9 : 1; /* 3D LUT support for 9x9x9 */

sys/dev/pci/drm/amd/display/dc/dc.h

222

uint32_t dim_17 : 1; /* 3D LUT support for 17x17x17 */

sys/dev/pci/drm/amd/display/dc/dc.h

2223

void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);

sys/dev/pci/drm/amd/display/dc/dc.h

223

uint32_t dim_33 : 1; /* 3D LUT support for 33x33x33 */

sys/dev/pci/drm/amd/display/dc/dc.h

2231

uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw);

sys/dev/pci/drm/amd/display/dc/dc.h

224

uint32_t dim_45 : 1; /* 3D LUT support for 45x45x45 */

sys/dev/pci/drm/amd/display/dc/dc.h

2243

uint32_t req_bw);

sys/dev/pci/drm/amd/display/dc/dc.h

225

uint32_t dim_65 : 1; /* 3D LUT support for 65x65x65 */

sys/dev/pci/drm/amd/display/dc/dc.h

2391

uint32_t backlight_millinits,

sys/dev/pci/drm/amd/display/dc/dc.h

2392

uint32_t transition_time_in_ms);

sys/dev/pci/drm/amd/display/dc/dc.h

2395

uint32_t *backlight_millinits,

sys/dev/pci/drm/amd/display/dc/dc.h

2396

uint32_t *backlight_millinits_peak);

sys/dev/pci/drm/amd/display/dc/dc.h

2563

uint32_t dongle_max_pix_clk;

sys/dev/pci/drm/amd/display/dc/dc.h

2579

uint32_t sink_id;

sys/dev/pci/drm/amd/display/dc/dc.h

2594

uint32_t dongle_max_pix_clk;

sys/dev/pci/drm/amd/display/dc/dc.h

2610

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/dc.h

2611

uint32_t ext_id);

sys/dev/pci/drm/amd/display/dc/dc.h

2615

struct dc *dc, uint32_t link_index);

sys/dev/pci/drm/amd/display/dc/dc.h

2637

enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);

sys/dev/pci/drm/amd/display/dc/dc.h

2688

uint32_t link_index,

sys/dev/pci/drm/amd/display/dc/dc.h

2696

uint32_t link_index,

sys/dev/pci/drm/amd/display/dc/dc.h

2701

uint32_t link_index,

sys/dev/pci/drm/amd/display/dc/dc.h

2705

void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps);

sys/dev/pci/drm/amd/display/dc/dc.h

2708

uint32_t hpd_int_enable);

sys/dev/pci/drm/amd/display/dc/dc.h

282

uint32_t max_streams;

sys/dev/pci/drm/amd/display/dc/dc.h

283

uint32_t max_links;

sys/dev/pci/drm/amd/display/dc/dc.h

284

uint32_t max_audios;

sys/dev/pci/drm/amd/display/dc/dc.h

285

uint32_t max_slave_planes;

sys/dev/pci/drm/amd/display/dc/dc.h

286

uint32_t max_slave_yuv_planes;

sys/dev/pci/drm/amd/display/dc/dc.h

287

uint32_t max_slave_rgb_planes;

sys/dev/pci/drm/amd/display/dc/dc.h

288

uint32_t max_planes;

sys/dev/pci/drm/amd/display/dc/dc.h

289

uint32_t max_downscale_ratio;

sys/dev/pci/drm/amd/display/dc/dc.h

290

uint32_t i2c_speed_in_khz;

sys/dev/pci/drm/amd/display/dc/dc.h

291

uint32_t i2c_speed_in_khz_hdcp;

sys/dev/pci/drm/amd/display/dc/dc.h

292

uint32_t dmdata_alloc_size;

sys/dev/pci/drm/amd/display/dc/dc.h

316

uint32_t num_of_internal_disp;

sys/dev/pci/drm/amd/display/dc/dc.h

330

uint32_t max_otg_num;

sys/dev/pci/drm/amd/display/dc/dc.h

331

uint32_t max_cab_allocation_bytes;

sys/dev/pci/drm/amd/display/dc/dc.h

332

uint32_t cache_line_size;

sys/dev/pci/drm/amd/display/dc/dc.h

333

uint32_t cache_num_ways;

sys/dev/pci/drm/amd/display/dc/dc.h

341

uint32_t max_v_total;

sys/dev/pci/drm/amd/display/dc/dc.h

343

uint32_t max_disp_clock_khz_at_vmin;

sys/dev/pci/drm/amd/display/dc/dc.h

349

uint32_t dcc_plane_width_limit;

sys/dev/pci/drm/amd/display/dc/dc.h

389

uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case)

sys/dev/pci/drm/amd/display/dc/dc.h

390

uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0

sys/dev/pci/drm/amd/display/dc/dc.h

391

uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0

sys/dev/pci/drm/amd/display/dc/dc.h

392

uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case)

sys/dev/pci/drm/amd/display/dc/dc.h

393

uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case)

sys/dev/pci/drm/amd/display/dc/dc.h

394

uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x

sys/dev/pci/drm/amd/display/dc/dc.h

395

uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case)

sys/dev/pci/drm/amd/display/dc/dc.h

498

uint32_t allow_edp_hotplug_detection;

sys/dev/pci/drm/amd/display/dc/dc.h

772

uint32_t u32All;

sys/dev/pci/drm/amd/display/dc/dc.h

787

uint32_t reserved: 22;

sys/dev/pci/drm/amd/display/dc/dc.h

789

uint32_t u32All;

sys/dev/pci/drm/amd/display/dc/dc.h

808

uint32_t reserved : 19;

sys/dev/pci/drm/amd/display/dc/dc.h

810

uint32_t u32All;

sys/dev/pci/drm/amd/display/dc/dc.h

845

uint32_t disable_dpia:1; /* bit 0 */

sys/dev/pci/drm/amd/display/dc/dc.h

846

uint32_t force_non_lttpr:1; /* bit 1 */

sys/dev/pci/drm/amd/display/dc/dc.h

847

uint32_t extend_aux_rd_interval:1; /* bit 2 */

sys/dev/pci/drm/amd/display/dc/dc.h

848

uint32_t disable_mst_dsc_work_around:1; /* bit 3 */

sys/dev/pci/drm/amd/display/dc/dc.h

849

uint32_t enable_force_tbt3_work_around:1; /* bit 4 */

sys/dev/pci/drm/amd/display/dc/dc.h

850

uint32_t disable_usb4_pm_support:1; /* bit 5 */

sys/dev/pci/drm/amd/display/dc/dc.h

851

uint32_t enable_usb4_bw_zero_alloc_patch:1; /* bit 6 */

sys/dev/pci/drm/amd/display/dc/dc.h

852

uint32_t enable_bw_allocation_mode:1; /* bit 7 */

sys/dev/pci/drm/amd/display/dc/dc.h

853

uint32_t reserved:24;

sys/dev/pci/drm/amd/display/dc/dc.h

855

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/dc.h

866

uint32_t enable_wa : 1;

sys/dev/pci/drm/amd/display/dc/dc.h

867

uint32_t use_default_timeout : 1;

sys/dev/pci/drm/amd/display/dc/dc.h

868

uint32_t rsvd: 14;

sys/dev/pci/drm/amd/display/dc/dc.h

869

uint32_t timeout_ms : 16;

sys/dev/pci/drm/amd/display/dc/dc.h

871

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/dc.h

875

uint32_t ltFailCount;

sys/dev/pci/drm/amd/display/dc/dc.h

876

uint32_t i2cErrorCount;

sys/dev/pci/drm/amd/display/dc/dc.h

877

uint32_t auxErrorCount;

sys/dev/pci/drm/amd/display/dc/dc.h

908

uint32_t page_table_block_size_in_bytes;

sys/dev/pci/drm/amd/display/dc/dc.h

996

uint32_t underflow_assert_delay_us;

sys/dev/pci/drm/amd/display/dc/dc_bios_types.h

168

uint32_t BIOS_SCRATCH_3;

sys/dev/pci/drm/amd/display/dc/dc_bios_types.h

169

uint32_t BIOS_SCRATCH_6;

sys/dev/pci/drm/amd/display/dc/dc_bios_types.h

176

uint32_t bios_size;

sys/dev/pci/drm/amd/display/dc/dc_bios_types.h

49

struct graphics_object_id object_id, uint32_t index,

sys/dev/pci/drm/amd/display/dc/dc_bios_types.h

62

uint32_t device_tag_index,

sys/dev/pci/drm/amd/display/dc/dc_bios_types.h

67

uint32_t index,

sys/dev/pci/drm/amd/display/dc/dc_bios_types.h

69

uint32_t (*get_ss_entry_number)(

sys/dev/pci/drm/amd/display/dc/dc_bios_types.h

77

uint32_t gpio_id,

sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h

101

uint32_t defer_delay;

sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h

109

uint32_t length;

sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h

129

uint32_t speed;

sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h

134

uint32_t ddc_channel;

sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h

146

uint32_t DP_SKIP_POWER_OFF:1;

sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h

147

uint32_t DP_AUX_POWER_UP_WA_DELAY:1;

sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h

149

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h

193

uint32_t address;

sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h

194

uint32_t edid_buf_len;

sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h

51

uint32_t address;

sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h

54

uint32_t length;

sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h

76

uint32_t length;

sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h

90

uint32_t address;

sys/dev/pci/drm/amd/display/dc/dc_ddc_types.h

91

uint32_t length;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1347

uint32_t rcg_exit_count = 0, ips1_exit_count = 0, ips2_exit_count = 0, ips1z8_exit_count = 0;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1642

uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1645

const uint32_t wait_us = wait_type == DM_DMUB_WAIT_TYPE_NO_WAIT ? 0 : 30;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1669

uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1696

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1763

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1815

uint32_t tg_inst,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1816

uint32_t vtotal_min,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1817

uint32_t vtotal_max,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1818

uint32_t vtotal_mid,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1819

uint32_t vtotal_mid_frame_num,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1964

uint32_t bytes = sizeof(struct dmub_ips_residency_info);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1976

cmd.ips_query_residency_info.info_data.ips_mode = (uint32_t)ips_mode;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2017

uint32_t count

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2145

uint32_t byte_count,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2146

uint32_t overlap_disable

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2179

uint32_t byte_count,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2180

uint32_t data

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2209

bool dmub_lsdma_send_poll_reg_write_command(struct dc_dmub_srv *dc_dmub_srv, uint32_t reg_addr, uint32_t reg_data)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

376

void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

392

void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

660

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

715

uint32_t subvp0_prefetch_us = 0;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

716

uint32_t subvp1_prefetch_us = 0;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

717

uint32_t prefetch_delta_us = 0;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

781

uint32_t j;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

787

uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

875

uint32_t i, pipe_idx;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

879

uint32_t wm_val_refclk = 0;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

953

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

194

uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

200

uint32_t tg_inst,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

201

uint32_t vtotal_min,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

202

uint32_t vtotal_max,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

203

uint32_t vtotal_mid,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

204

uint32_t vtotal_mid_frame_num,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

218

uint32_t count);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

221

uint32_t src_lo;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

222

uint32_t src_hi;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

224

uint32_t dst_lo;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

225

uint32_t dst_hi;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

227

uint32_t src_x : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

228

uint32_t src_y : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

230

uint32_t dst_x : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

231

uint32_t dst_y : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

233

uint32_t rect_x : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

234

uint32_t rect_y : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

236

uint32_t src_pitch : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

237

uint32_t dst_pitch : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

239

uint32_t src_slice_pitch;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

240

uint32_t dst_slice_pitch;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

242

uint32_t tmz : 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

243

uint32_t element_size : 3;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

244

uint32_t src_cache_policy : 3;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

245

uint32_t dst_cache_policy : 3;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

246

uint32_t padding : 22;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

257

uint32_t byte_count,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

258

uint32_t overlap_disable);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

262

uint32_t byte_count,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

263

uint32_t data);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

269

uint32_t src_x : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

270

uint32_t src_y : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

272

uint32_t dst_x : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

273

uint32_t dst_y : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

275

uint32_t src_width : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

276

uint32_t dst_width : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

278

uint32_t rect_x : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

279

uint32_t rect_y : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

281

uint32_t src_height : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

282

uint32_t dst_height : 16;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

284

uint32_t data_format : 6;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

285

uint32_t swizzle_mode : 5;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

286

uint32_t element_size : 3;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

287

uint32_t dcc : 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

288

uint32_t tmz : 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

289

uint32_t read_compress : 2;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

290

uint32_t write_compress : 2;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

291

uint32_t max_com : 2;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

292

uint32_t max_uncom : 1;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

293

uint32_t padding : 9;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

299

bool dmub_lsdma_send_poll_reg_write_command(struct dc_dmub_srv *dc_dmub_srv, uint32_t reg_addr, uint32_t reg_data);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

42

uint32_t same_addr_count;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

86

void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

88

void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst);

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1219

uint32_t dp_hdmi_max_bpc;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1220

uint32_t dp_hdmi_max_pixel_clk_in_khz;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1221

uint32_t dp_hdmi_frl_max_link_bw_in_kbps;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1222

uint32_t dp_hdmi_regulated_autonomous_mode_support;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1248

uint32_t sink_dev_id;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1253

uint32_t branch_dev_id;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

167

uint32_t bw_granularity;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

168

uint32_t estimated_bw;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

169

uint32_t allocated_bw;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

636

uint32_t backlight_millinits_peak; /* 326h */

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

637

uint32_t backlight_millinits_avg; /* 32Ah */

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

108

uint32_t max_target_bpp_limit_override_x16,

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

112

void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

35

uint32_t min_kbps; /* Bandwidth if min_target_bpp_x16 is used */

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

36

uint32_t min_target_bpp_x16;

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

37

uint32_t max_kbps; /* Bandwidth if max_target_bpp_x16 is used */

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

38

uint32_t max_target_bpp_x16;

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

39

uint32_t stream_kbps; /* Uncompressed stream bandwidth */

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

52

uint32_t max_target_bpp;

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

53

uint32_t min_target_bpp;

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

58

uint32_t dsc_min_slice_height_override;

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

59

uint32_t max_target_bpp_limit_override_x16;

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

60

uint32_t slice_height_granularity;

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

61

uint32_t dsc_force_odm_hslice_override;

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

72

uint32_t dsc_min_slice_height_override,

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

73

uint32_t min_bpp_x16,

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

74

uint32_t max_bpp_x16,

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

84

uint32_t target_bandwidth_kbps,

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

89

uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

90

uint32_t bpp_x16, uint32_t num_slices_h, bool is_dp);

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

92

uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps(

sys/dev/pci/drm/amd/display/dc/dc_fused_io.c

106

const uint32_t ddc_line = link->ddc->ddc_pin->pin_data->en;

sys/dev/pci/drm/amd/display/dc/dc_fused_io.c

127

uint32_t poll_timeout_us,

sys/dev/pci/drm/amd/display/dc/dc_fused_io.c

134

const uint32_t ddc_line = link->ddc->ddc_pin->pin_data->en;

sys/dev/pci/drm/amd/display/dc/dc_fused_io.c

14

uint32_t ddc_line,

sys/dev/pci/drm/amd/display/dc/dc_fused_io.c

40

uint32_t ddc_line

sys/dev/pci/drm/amd/display/dc/dc_fused_io.c

62

uint32_t poll_timeout_us,

sys/dev/pci/drm/amd/display/dc/dc_fused_io.c

67

const uint32_t timeout_per_request_us = 10000;

sys/dev/pci/drm/amd/display/dc/dc_fused_io.c

68

const uint32_t timeout_per_aux_transaction_us = 10000;

sys/dev/pci/drm/amd/display/dc/dc_fused_io.c

98

uint32_t poll_timeout_us,

sys/dev/pci/drm/amd/display/dc/dc_fused_io.h

17

uint32_t poll_timeout_us,

sys/dev/pci/drm/amd/display/dc/dc_fused_io.h

26

uint32_t poll_timeout_us,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

107

uint32_t addr, int n,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

108

uint8_t shift1, uint32_t mask1, uint32_t field_value1,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

111

uint32_t shift, mask, field_value;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

119

shift = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

120

mask = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

121

field_value = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

143

static bool dmub_reg_value_burst_set_pack(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

144

uint32_t reg_val)

sys/dev/pci/drm/amd/display/dc/dc_helper.c

168

static uint32_t dmub_reg_value_pack(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

207

static void dmub_reg_wait_done_pack(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

208

uint32_t mask, uint32_t shift, uint32_t condition_value, uint32_t time_out_us)

sys/dev/pci/drm/amd/display/dc/dc_helper.c

221

uint32_t generic_reg_update_ex(const struct dc_context *ctx,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

222

uint32_t addr, int n,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

223

uint8_t shift1, uint32_t mask1, uint32_t field_value1,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

227

uint32_t reg_val;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

249

uint32_t generic_reg_set_ex(const struct dc_context *ctx,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

250

uint32_t addr, uint32_t reg_val, int n,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

251

uint8_t shift1, uint32_t mask1, uint32_t field_value1,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

277

uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

278

uint8_t shift, uint32_t mask, uint32_t *field_value)

sys/dev/pci/drm/amd/display/dc/dc_helper.c

280

uint32_t reg_val = dm_read_reg(ctx, addr);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

285

uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

286

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

287

uint8_t shift2, uint32_t mask2, uint32_t *field_value2)

sys/dev/pci/drm/amd/display/dc/dc_helper.c

289

uint32_t reg_val = dm_read_reg(ctx, addr);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

295

uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

296

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

297

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

298

uint8_t shift3, uint32_t mask3, uint32_t *field_value3)

sys/dev/pci/drm/amd/display/dc/dc_helper.c

300

uint32_t reg_val = dm_read_reg(ctx, addr);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

307

uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

308

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

309

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

310

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

311

uint8_t shift4, uint32_t mask4, uint32_t *field_value4)

sys/dev/pci/drm/amd/display/dc/dc_helper.c

313

uint32_t reg_val = dm_read_reg(ctx, addr);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

321

uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

322

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

323

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

324

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

325

uint8_t shift4, uint32_t mask4, uint32_t *field_value4,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

326

uint8_t shift5, uint32_t mask5, uint32_t *field_value5)

sys/dev/pci/drm/amd/display/dc/dc_helper.c

328

uint32_t reg_val = dm_read_reg(ctx, addr);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

337

uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

338

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

339

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

340

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

341

uint8_t shift4, uint32_t mask4, uint32_t *field_value4,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

342

uint8_t shift5, uint32_t mask5, uint32_t *field_value5,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

343

uint8_t shift6, uint32_t mask6, uint32_t *field_value6)

sys/dev/pci/drm/amd/display/dc/dc_helper.c

345

uint32_t reg_val = dm_read_reg(ctx, addr);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

355

uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

356

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

357

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

358

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

359

uint8_t shift4, uint32_t mask4, uint32_t *field_value4,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

360

uint8_t shift5, uint32_t mask5, uint32_t *field_value5,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

361

uint8_t shift6, uint32_t mask6, uint32_t *field_value6,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

362

uint8_t shift7, uint32_t mask7, uint32_t *field_value7)

sys/dev/pci/drm/amd/display/dc/dc_helper.c

364

uint32_t reg_val = dm_read_reg(ctx, addr);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

375

uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

376

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

377

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

378

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

379

uint8_t shift4, uint32_t mask4, uint32_t *field_value4,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

380

uint8_t shift5, uint32_t mask5, uint32_t *field_value5,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

381

uint8_t shift6, uint32_t mask6, uint32_t *field_value6,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

382

uint8_t shift7, uint32_t mask7, uint32_t *field_value7,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

383

uint8_t shift8, uint32_t mask8, uint32_t *field_value8)

sys/dev/pci/drm/amd/display/dc/dc_helper.c

385

uint32_t reg_val = dm_read_reg(ctx, addr);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

428

uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

432

uint32_t field_value;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

433

uint32_t reg_val;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

480

uint32_t addr_index, uint32_t addr_data,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

481

uint32_t index, uint32_t data)

sys/dev/pci/drm/amd/display/dc/dc_helper.c

487

uint32_t generic_read_indirect_reg(const struct dc_context *ctx,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

488

uint32_t addr_index, uint32_t addr_data,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

489

uint32_t index)

sys/dev/pci/drm/amd/display/dc/dc_helper.c

491

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

505

uint32_t generic_indirect_reg_get(const struct dc_context *ctx,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

506

uint32_t addr_index, uint32_t addr_data,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

507

uint32_t index, int n,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

508

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

511

uint32_t shift, mask, *field_value;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

512

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

523

shift = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

524

mask = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

525

field_value = va_arg(ap, uint32_t *);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

536

uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

537

uint32_t addr_index, uint32_t addr_data,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

538

uint32_t index, uint32_t reg_val, int n,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

539

uint8_t shift1, uint32_t mask1, uint32_t field_value1,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

542

uint32_t shift, mask, field_value;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

552

shift = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

553

mask = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

554

field_value = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

567

uint32_t generic_indirect_reg_update_ex_sync(const struct dc_context *ctx,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

568

uint32_t index, uint32_t reg_val, int n,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

569

uint8_t shift1, uint32_t mask1, uint32_t field_value1,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

572

uint32_t shift, mask, field_value;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

582

shift = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

583

mask = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

584

field_value = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

596

uint32_t generic_indirect_reg_get_sync(const struct dc_context *ctx,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

597

uint32_t index, int n,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

598

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

601

uint32_t shift, mask, *field_value;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

602

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

613

shift = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

614

mask = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

615

field_value = va_arg(ap, uint32_t *);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

68

sizeof(uint32_t) * offload->reg_seq_count;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

90

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

91

uint32_t mask;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

96

uint32_t value,

sys/dev/pci/drm/amd/display/dc/dc_helper.c

97

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

1016

uint32_t v_total_min;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

1017

uint32_t v_total_max;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

1018

uint32_t v_total_mid;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

1019

uint32_t v_total_mid_frame_num;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

1020

uint32_t allow_otg_v_count_halt;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

466

uint32_t x;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

47

uint32_t low_part;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

471

uint32_t y;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

476

uint32_t x_hotspot;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

481

uint32_t y_hotspot;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

52

uint32_t low_part;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

583

uint32_t ENABLE_MAGNIFICATION:1;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

584

uint32_t INVERSE_TRANSPARENT_CLAMPING:1;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

585

uint32_t HORIZONTAL_MIRROR:1;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

586

uint32_t VERTICAL_MIRROR:1;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

587

uint32_t INVERT_PIXEL_DATA:1;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

588

uint32_t ZERO_EXPANSION:1;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

589

uint32_t MIN_MAX_INVERT:1;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

590

uint32_t ENABLE_CURSOR_DEGAMMA:1;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

591

uint32_t RESERVED:24;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

593

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

607

uint32_t pitch;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

612

uint32_t width;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

616

uint32_t height;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

625

uint32_t sdr_white_level;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

712

uint32_t v_taps;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

713

uint32_t h_taps;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

714

uint32_t v_taps_c;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

715

uint32_t h_taps_c;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

781

uint32_t INTERLACE :1;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

782

uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

784

uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

787

uint32_t HORZ_COUNT_BY_TWO:1;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

789

uint32_t EXCLUSIVE_3D :1; /* if this bit set,

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

792

uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

794

uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right images subsampled

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

796

uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

798

uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

800

uint32_t Y_ONLY :1;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

802

uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

803

uint32_t DTD_COUNTER :5; /* values 1 to 16 */

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

805

uint32_t FORCE_HDR :1;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

809

uint32_t LTE_340MCSC_SCRAMBLE:1;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

811

uint32_t DSC : 1; /* Use DSC with this timing */

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

812

uint32_t VBLANK_SYNCHRONIZABLE: 1;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

861

uint32_t num_slices_h; /* Number of DSC slices - horizontal */

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

862

uint32_t num_slices_v; /* Number of DSC slices - vertical */

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

863

uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

865

uint32_t linebuf_depth; /* DSC line buffer depth */

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

866

uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

871

uint32_t mst_pbn; /* pbn of display on dsc mst hub */

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

890

uint32_t h_total;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

895

uint32_t h_border_left;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

902

uint32_t h_addressable;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

907

uint32_t h_border_right;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

913

uint32_t h_front_porch;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

918

uint32_t h_sync_width;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

929

uint32_t v_total;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

934

uint32_t v_border_top;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

942

uint32_t v_addressable;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

947

uint32_t v_border_bottom;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

961

uint32_t v_front_porch;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

966

uint32_t v_sync_width;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

974

uint32_t pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

976

uint32_t min_refresh_in_uhz;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

977

uint32_t max_refresh_in_uhz;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

979

uint32_t vic;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

980

uint32_t hdmi_vic;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

981

uint32_t rid;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

982

uint32_t fr_index;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

983

uint32_t frl_uncompressed_video_bandwidth_in_kbps;

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

991

uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */

sys/dev/pci/drm/amd/display/dc/dc_hw_types.h

995

uint32_t expanded_hblank;

sys/dev/pci/drm/amd/display/dc/dc_plane.h

33

uint32_t address : 1;

sys/dev/pci/drm/amd/display/dc/dc_plane.h

35

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/dc_stat.h

41

void dc_stat_get_dmub_dataout(const struct dc *dc, uint32_t *dataout);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

131

uint32_t mst_stream_bw; // new mst bandwidth in kbps

sys/dev/pci/drm/amd/display/dc/dc_stream.h

136

uint32_t scaling:1;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

137

uint32_t out_tf:1;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

138

uint32_t out_csc:1;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

139

uint32_t abm_level:1;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

140

uint32_t dpms_off:1;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

141

uint32_t gamut_remap:1;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

142

uint32_t wb_update:1;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

143

uint32_t dsc_changed : 1;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

144

uint32_t mst_bw : 1;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

145

uint32_t crtc_timing_adjust : 1;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

146

uint32_t fams_changed : 1;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

147

uint32_t scaler_sharpener : 1;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

148

uint32_t sharpening_required : 1;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

151

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

276

uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode

sys/dev/pci/drm/amd/display/dc/dc_stream.h

304

uint32_t apply_boot_odm_mode;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

306

uint32_t stream_id;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

420

uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

434

uint32_t *v_blank_start,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

435

uint32_t *v_blank_end,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

436

uint32_t *h_position,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

437

uint32_t *v_position);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

445

uint32_t dwb_pipe_inst);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

449

uint32_t dwb_pipe_inst);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

539

uint32_t *refresh_rate);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

564

uint32_t *r_cr,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

565

uint32_t *g_y,

sys/dev/pci/drm/amd/display/dc/dc_stream.h

566

uint32_t *b_cb);

sys/dev/pci/drm/amd/display/dc/dc_stream.h

80

uint32_t dmdata_size;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

88

uint32_t dmdata_qos_level;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

92

uint32_t dmdata_dl_delta;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

94

uint32_t *dmdata_sw_data;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1135

uint32_t debug_flags;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1175

uint32_t coasting_vtotal;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1177

uint32_t coasting_vtotal_table[PR_COASTING_TYPE_NUM];

sys/dev/pci/drm/amd/display/dc/dc_types.h

1179

uint32_t defer_update_coasting_vtotal_table[PR_COASTING_TYPE_NUM];

sys/dev/pci/drm/amd/display/dc/dc_types.h

1181

uint32_t link_off_frame_count;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1187

uint32_t replay_desync_error_fail_count;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1370

uint32_t backlight_pwm_u16_16;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1372

uint32_t frame_ramp;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1380

uint32_t backlight_millinits;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1382

uint32_t transition_time_in_ms;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1384

uint32_t min_luminance;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1386

uint32_t max_luminance;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1388

uint32_t min_backlight_pwm;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1390

uint32_t max_backlight_pwm;

sys/dev/pci/drm/amd/display/dc/dc_types.h

1407

uint32_t required_bw;

sys/dev/pci/drm/amd/display/dc/dc_types.h

152

uint32_t length;

sys/dev/pci/drm/amd/display/dc/dc_types.h

192

uint32_t serial_number;

sys/dev/pci/drm/amd/display/dc/dc_types.h

199

uint32_t audio_mode_count;

sys/dev/pci/drm/amd/display/dc/dc_types.h

201

uint32_t audio_latency;

sys/dev/pci/drm/amd/display/dc/dc_types.h

202

uint32_t video_latency;

sys/dev/pci/drm/amd/display/dc/dc_types.h

207

uint32_t max_tmds_clk_mhz;

sys/dev/pci/drm/amd/display/dc/dc_types.h

221

uint32_t INTERLACE :1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

223

uint32_t NATIVE :1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

225

uint32_t PREFERRED :1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

228

uint32_t REDUCED_BLANKING :1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

230

uint32_t VIDEO_OPTIMIZED_RATE :1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

232

uint32_t PACKED_PIXEL_FORMAT :1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

234

uint32_t PREFERRED_VIEW :1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

236

uint32_t TILED_MODE :1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

237

uint32_t DSE_MODE :1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

242

uint32_t MIRACAST_REFRESH_DIVIDER;

sys/dev/pci/drm/amd/display/dc/dc_types.h

307

uint32_t pixel_width;

sys/dev/pci/drm/amd/display/dc/dc_types.h

308

uint32_t pixel_height;

sys/dev/pci/drm/amd/display/dc/dc_types.h

309

uint32_t field_rate;

sys/dev/pci/drm/amd/display/dc/dc_types.h

452

uint32_t FL_FR:1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

453

uint32_t LFE:1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

454

uint32_t FC:1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

455

uint32_t RL_RR:1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

456

uint32_t RC:1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

457

uint32_t FLC_FRC:1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

458

uint32_t RLC_RRC:1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

459

uint32_t SUPPORT_AI:1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

463

uint32_t ALLSPEAKERS:7;

sys/dev/pci/drm/amd/display/dc/dc_types.h

464

uint32_t SUPPORT_AI:1;

sys/dev/pci/drm/amd/display/dc/dc_types.h

523

uint32_t video_latency;

sys/dev/pci/drm/amd/display/dc/dc_types.h

524

uint32_t audio_latency;

sys/dev/pci/drm/amd/display/dc/dc_types.h

525

uint32_t display_index;

sys/dev/pci/drm/amd/display/dc/dc_types.h

527

uint32_t manufacture_id;

sys/dev/pci/drm/amd/display/dc/dc_types.h

528

uint32_t product_id;

sys/dev/pci/drm/amd/display/dc/dc_types.h

530

uint32_t port_id[2];

sys/dev/pci/drm/amd/display/dc/dc_types.h

531

uint32_t mode_count;

sys/dev/pci/drm/amd/display/dc/dc_types.h

567

uint32_t max_retry_count;

sys/dev/pci/drm/amd/display/dc/dc_types.h

568

uint32_t delay_time_ms;

sys/dev/pci/drm/amd/display/dc/dc_types.h

569

uint32_t ignore_checksum;

sys/dev/pci/drm/amd/display/dc/dc_types.h

777

uint32_t max_clock_khz;

sys/dev/pci/drm/amd/display/dc/dc_types.h

778

uint32_t min_clock_khz;

sys/dev/pci/drm/amd/display/dc/dc_types.h

779

uint32_t bw_requirequired_clock_khz;

sys/dev/pci/drm/amd/display/dc/dc_types.h

780

uint32_t current_clock_khz;/*current clock in use*/

sys/dev/pci/drm/amd/display/dc/dc_types.h

784

uint32_t chip_id;

sys/dev/pci/drm/amd/display/dc/dc_types.h

785

uint32_t chip_family;

sys/dev/pci/drm/amd/display/dc/dc_types.h

786

uint32_t pci_revision_id;

sys/dev/pci/drm/amd/display/dc/dc_types.h

787

uint32_t hw_internal_rev;

sys/dev/pci/drm/amd/display/dc/dc_types.h

788

uint32_t vram_type;

sys/dev/pci/drm/amd/display/dc/dc_types.h

789

uint32_t vram_width;

sys/dev/pci/drm/amd/display/dc/dc_types.h

790

uint32_t feature_flags;

sys/dev/pci/drm/amd/display/dc/dc_types.h

791

uint32_t fake_paths_num;

sys/dev/pci/drm/amd/display/dc/dc_types.h

813

uint32_t dc_sink_id_count;

sys/dev/pci/drm/amd/display/dc/dc_types.h

814

uint32_t dc_stream_id_count;

sys/dev/pci/drm/amd/display/dc/dc_types.h

815

uint32_t dc_edp_id_count;

sys/dev/pci/drm/amd/display/dc/dc_types.h

819

uint32_t *dcn_reg_offsets;

sys/dev/pci/drm/amd/display/dc/dc_types.h

820

uint32_t *nbio_reg_offsets;

sys/dev/pci/drm/amd/display/dc/dc_types.h

821

uint32_t *clk_reg_offsets;

sys/dev/pci/drm/amd/display/dc/dc_types.h

886

uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */

sys/dev/pci/drm/amd/display/dc/dc_types.h

889

uint32_t branch_overall_throughput_0_mps; /* In MPs */

sys/dev/pci/drm/amd/display/dc/dc_types.h

890

uint32_t branch_overall_throughput_1_mps; /* In MPs */

sys/dev/pci/drm/amd/display/dc/dc_types.h

891

uint32_t branch_max_line_width;

sys/dev/pci/drm/amd/display/dc/dc_types.h

900

uint32_t buffer_size; /* Add 1 to value and multiply by 32 */

sys/dev/pci/drm/amd/display/dc/dc_types.h

905

uint32_t aux_dphy_rx_control0_val;

sys/dev/pci/drm/amd/display/dc/dc_types.h

906

uint32_t aux_dphy_tx_control_val;

sys/dev/pci/drm/amd/display/dc/dc_types.h

907

uint32_t aux_dphy_rx_control1_val;

sys/dev/pci/drm/amd/display/dc/dc_types.h

908

uint32_t dc_gpio_aux_ctrl_0_val;

sys/dev/pci/drm/amd/display/dc/dc_types.h

909

uint32_t dc_gpio_aux_ctrl_1_val;

sys/dev/pci/drm/amd/display/dc/dc_types.h

910

uint32_t dc_gpio_aux_ctrl_2_val;

sys/dev/pci/drm/amd/display/dc/dc_types.h

911

uint32_t dc_gpio_aux_ctrl_3_val;

sys/dev/pci/drm/amd/display/dc/dc_types.h

912

uint32_t dc_gpio_aux_ctrl_4_val;

sys/dev/pci/drm/amd/display/dc/dc_types.h

913

uint32_t dc_gpio_aux_ctrl_5_val;

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

109

uint32_t otg_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

121

uint32_t otg_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

82

uint32_t clk_en = 0;

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

83

uint32_t clk_sel = 0;

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

373

DCCG_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

374

DCCG3_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

375

DCCG31_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

376

DCCG314_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

377

DCCG32_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

378

DCCG35_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

379

DCCG401_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

383

uint32_t DPPCLK_DTO_CTRL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

384

uint32_t DPPCLK_DTO_PARAM[6]; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

385

uint32_t REFCLK_CNTL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

386

uint32_t DISPCLK_FREQ_CHANGE_CNTL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

387

uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

388

uint32_t HDMICHARCLK_CLOCK_CNTL[6]; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

389

uint32_t PHYASYMCLK_CLOCK_CNTL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

390

uint32_t PHYBSYMCLK_CLOCK_CNTL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

391

uint32_t PHYCSYMCLK_CLOCK_CNTL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

392

uint32_t PHYDSYMCLK_CLOCK_CNTL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

393

uint32_t PHYESYMCLK_CLOCK_CNTL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

394

uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

395

uint32_t DTBCLK_DTO_PHASE[MAX_PIPES]; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

396

uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

397

uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

398

uint32_t DCCG_AUDIO_DTO_SOURCE; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

399

uint32_t DPSTREAMCLK_CNTL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

400

uint32_t HDMISTREAMCLK_CNTL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

401

uint32_t SYMCLK32_SE_CNTL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

402

uint32_t SYMCLK32_LE_CNTL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

403

uint32_t DENTIST_DISPCLK_CNTL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

404

uint32_t DSCCLK_DTO_CTRL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

405

uint32_t DSCCLK0_DTO_PARAM; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

406

uint32_t DSCCLK1_DTO_PARAM; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

407

uint32_t DSCCLK2_DTO_PARAM; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

408

uint32_t DSCCLK3_DTO_PARAM; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

409

uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

410

uint32_t DPSTREAMCLK_GATE_DISABLE; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

411

uint32_t DCCG_GATE_DISABLE_CNTL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

412

uint32_t DCCG_GATE_DISABLE_CNTL2; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

413

uint32_t DCCG_GATE_DISABLE_CNTL3; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

414

uint32_t HDMISTREAMCLK0_DTO_PARAM; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

415

uint32_t DCCG_GATE_DISABLE_CNTL4; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

416

uint32_t OTG_PIXEL_RATE_DIV; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

417

uint32_t DTBCLK_P_CNTL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

418

uint32_t DPPCLK_CTRL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

419

uint32_t DCCG_GATE_DISABLE_CNTL5; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

420

uint32_t DCCG_GATE_DISABLE_CNTL6; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

421

uint32_t DCCG_GLOBAL_FGCG_REP_CNTL; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

422

uint32_t SYMCLKA_CLOCK_ENABLE; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

423

uint32_t SYMCLKB_CLOCK_ENABLE; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

424

uint32_t SYMCLKC_CLOCK_ENABLE; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

425

uint32_t SYMCLKD_CLOCK_ENABLE; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

426

uint32_t SYMCLKE_CLOCK_ENABLE; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

427

uint32_t DP_DTO_MODULO[MAX_PIPES]; \

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

428

uint32_t DP_DTO_PHASE[MAX_PIPES]

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

449

uint32_t otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

451

uint32_t otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

550

uint32_t dtbdto_div;

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

573

uint32_t modulo, phase;

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

617

uint32_t modulo, phase;

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

695

uint32_t otg_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

704

uint32_t otg_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

225

uint32_t otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

229

uint32_t otg_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

102

uint32_t otg_inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

107

uint32_t cur_k1 = PIXEL_RATE_DIV_NA;

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

108

uint32_t cur_k2 = PIXEL_RATE_DIV_NA;

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

151

uint32_t otg_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

155

uint32_t p_src_sel = 0; /* selects dprefclk */

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

214

uint32_t modulo, phase;

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

52

uint32_t dispclk_rdivider_value = 0;

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

60

uint32_t otg_inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

61

uint32_t *k1,

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

62

uint32_t *k2)

sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

65

uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA;

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

102

uint32_t otg_inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

107

uint32_t cur_k1 = PIXEL_RATE_DIV_NA;

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

108

uint32_t cur_k2 = PIXEL_RATE_DIV_NA;

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

151

uint32_t otg_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

155

uint32_t p_src_sel = 0; /* selects dprefclk */

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

213

uint32_t modulo, phase;

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

313

uint32_t otg_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

322

uint32_t otg_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

49

uint32_t dispclk_rdivider_value = 0;

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

60

uint32_t otg_inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

61

uint32_t *k1,

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

62

uint32_t *k2)

sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

65

uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1111

uint32_t dispclk_rdivider_value = 0;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1119

uint32_t dpp_inst, uint32_t enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1184

uint32_t dpp_inst, uint32_t disallow_rcg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1216

uint32_t otg_inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1217

uint32_t *k1,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1218

uint32_t *k2)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1221

uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1258

uint32_t otg_inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1263

uint32_t cur_k1 = PIXEL_RATE_DIV_NA;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1264

uint32_t cur_k2 = PIXEL_RATE_DIV_NA;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1308

uint32_t otg_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1312

uint32_t p_src_sel = 0; /* selects dprefclk */

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1370

uint32_t modulo, phase;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1894

static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1971

static uint8_t dccg35_get_number_enabled_symclk_fe_connected_to_be(struct dccg *dccg, uint32_t link_enc_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1974

uint32_t fe_clk_en[5] = {0}, be_clk_sel[5] = {0};

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2001

static void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2286

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2306

uint32_t modulo, phase;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2356

static void dccg35_enable_symclk_se_cb(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2367

uint32_t stream_enc_inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2368

uint32_t link_enc_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2375

void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

560

uint32_t en;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

561

uint32_t src_sel;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

785

uint32_t en = 0;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

786

uint32_t src_sel = 0;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

847

static uint32_t dccg35_is_fe_rcg(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

849

uint32_t enable = 0;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

880

static uint32_t dccg35_is_symclk32_se_rcg(struct dccg *dccg, int inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

882

uint32_t disable_l1 = 0;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

883

uint32_t disable_l2 = 0;

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

244

void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

113

uint32_t dentist_dispclk_value = REG_READ(DENTIST_DISPCLK_CNTL);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

121

uint32_t otg_inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

122

uint32_t *tmds_div,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

123

uint32_t *dp_dto_int)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

126

uint32_t val_tmds_div = PIXEL_RATE_DIV_NA;

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

159

uint32_t otg_inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

164

uint32_t cur_tmds_div = PIXEL_RATE_DIV_NA;

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

165

uint32_t dp_dto_int;

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

166

uint32_t reg_val;

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

215

uint32_t otg_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

219

uint32_t p_src_sel = 0; /* selects dprefclk */

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

364

uint32_t otg_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

373

uint32_t otg_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

56

uint32_t dpp_inst, uint32_t enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

730

void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

767

uint32_t dsc_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

801

void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

837

void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

212

void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

214

uint32_t dsc_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

220

uint32_t otg_inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

225

uint32_t otg_inst,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

226

uint32_t *tmds_div,

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

227

uint32_t *dp_dto_int);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

231

void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

232

void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);

sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

236

uint32_t otg_inst);

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

138

static void dce_abm_init(struct abm *abm, uint32_t backlight, uint32_t user_level)

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

199

static bool dce_abm_set_level(struct abm *abm, uint32_t level)

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

220

static bool dce_abm_immediate_disable(struct abm *abm, uint32_t panel_inst)

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

58

static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id, uint32_t panel_inst)

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

61

uint32_t rampingBoundary = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

88

uint32_t backlight_pwm_u16_16,

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

89

uint32_t frame_ramp,

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

90

uint32_t controller_id,

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

91

uint32_t panel_id)

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c

94

uint32_t s2;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

345

ABM_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

349

uint32_t DC_ABM1_HG_SAMPLE_RATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

350

uint32_t DC_ABM1_LS_SAMPLE_RATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

351

uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

352

uint32_t DC_ABM1_HG_MISC_CTRL;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

353

uint32_t DC_ABM1_IPCSC_COEFF_SEL;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

354

uint32_t BL1_PWM_CURRENT_ABM_LEVEL;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

355

uint32_t BL1_PWM_TARGET_ABM_LEVEL;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

356

uint32_t BL1_PWM_USER_LEVEL;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

357

uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

358

uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

359

uint32_t DC_ABM1_ACE_OFFSET_SLOPE_0;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

360

uint32_t DC_ABM1_ACE_OFFSET_SLOPE_DATA;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

361

uint32_t DC_ABM1_ACE_PWL_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

362

uint32_t DC_ABM1_HG_BIN_33_40_SHIFT_INDEX;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

363

uint32_t DC_ABM1_HG_BIN_33_64_SHIFT_FLAG;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

364

uint32_t DC_ABM1_HG_BIN_41_48_SHIFT_INDEX;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

365

uint32_t DC_ABM1_HG_BIN_49_56_SHIFT_INDEX;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

366

uint32_t DC_ABM1_HG_BIN_57_64_SHIFT_INDEX;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

367

uint32_t DC_ABM1_HG_RESULT_DATA;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

368

uint32_t DC_ABM1_HG_RESULT_INDEX;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

369

uint32_t DC_ABM1_ACE_THRES_DATA;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

370

uint32_t DC_ABM1_ACE_THRES_12;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

371

uint32_t MASTER_COMM_CNTL_REG;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

372

uint32_t MASTER_COMM_CMD_REG;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

373

uint32_t MASTER_COMM_DATA_REG1;

sys/dev/pci/drm/amd/display/dc/dce/dce_abm.h

374

uint32_t BIOS_SCRATCH_2;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1026

uint32_t crtc_pixel_clock_100hz,

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1027

uint32_t actual_pixel_clock_100Hz,

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1042

uint32_t requested_pixel_clock_100Hz,

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1072

uint32_t src_sel;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1164

uint32_t src_sel;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1246

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1247

uint32_t port_connectivity;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

126

uint32_t channel_count,

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

1263

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

129

uint32_t samples;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

130

uint32_t h_blank;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

273

uint32_t channel_count,

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

303

static uint32_t get_av_stream_map_lane_count(

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

308

uint32_t av_stream_map_lane_count = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

324

static uint32_t get_audio_sdp_overhead(

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

329

uint32_t audio_sdp_overhead = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

345

static uint32_t calculate_required_audio_bw_in_symbols(

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

348

uint32_t channel_count,

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

349

uint32_t sample_rate_hz,

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

350

uint32_t av_stream_map_lane_count,

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

351

uint32_t audio_sdp_overhead)

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

361

uint32_t num_sdp_with_max_layouts;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

362

uint32_t required_symbols_per_hblank;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

394

static uint32_t calculate_available_hblank_bw_in_symbols(

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

408

uint32_t available_hblank_bw = 0; /* in stream symbols */

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

472

uint32_t channel_count,

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

476

uint32_t available_hblank_bw;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

477

uint32_t av_stream_map_lane_count;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

478

uint32_t audio_sdp_overhead;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

531

uint32_t channel_count,

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

556

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

56

uint32_t reg_index,

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

57

uint32_t reg_data)

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

573

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

593

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

613

uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

640

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

672

uint32_t speakers = audio_info->flags.info.ALLSPEAKERS;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

673

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

674

uint32_t field = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

676

uint32_t format_index;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

677

uint32_t index;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

680

uint32_t strlen = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

70

static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index)

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

74

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

89

uint32_t *format_index)

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

91

uint32_t index;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c

92

uint32_t max_channe_index = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

114

uint32_t DCCG_AUDIO_DTO0_USE_512FBR_DTO;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

115

uint32_t DCCG_AUDIO_DTO1_USE_512FBR_DTO;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

116

uint32_t CLOCK_GATING_DISABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

120

uint32_t AZALIA_ENDPOINT_REG_INDEX;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

121

uint32_t AZALIA_ENDPOINT_REG_DATA;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

123

uint32_t AUDIO_RATE_CAPABILITIES;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

124

uint32_t CLKSTOP;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

125

uint32_t EPSS;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

127

uint32_t DCCG_AUDIO_DTO0_SOURCE_SEL;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

128

uint32_t DCCG_AUDIO_DTO_SEL;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

129

uint32_t DCCG_AUDIO_DTO0_MODULE;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

130

uint32_t DCCG_AUDIO_DTO0_PHASE;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

131

uint32_t DCCG_AUDIO_DTO1_MODULE;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

132

uint32_t DCCG_AUDIO_DTO1_PHASE;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

133

uint32_t DCCG_AUDIO_DTO2_USE_512FBR_DTO;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

134

uint32_t DCCG_AUDIO_DTO0_USE_512FBR_DTO;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

135

uint32_t DCCG_AUDIO_DTO1_USE_512FBR_DTO;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

136

uint32_t CLOCK_GATING_DISABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

83

uint32_t AZALIA_F0_CODEC_ENDPOINT_INDEX;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

84

uint32_t AZALIA_F0_CODEC_ENDPOINT_DATA;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

86

uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

87

uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

88

uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

90

uint32_t DCCG_AUDIO_DTO_SOURCE;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

91

uint32_t DCCG_AUDIO_DTO0_MODULE;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

92

uint32_t DCCG_AUDIO_DTO0_PHASE;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

93

uint32_t DCCG_AUDIO_DTO1_MODULE;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

94

uint32_t DCCG_AUDIO_DTO1_PHASE;

sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h

96

uint32_t AUDIO_RATE_CAPABILITIES;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

100

uint32_t field = get_reg_field_value(

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

112

uint32_t value = REG_READ(AUX_ARB_CONTROL);

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

113

uint32_t field = get_reg_field_value(

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

188

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

189

uint32_t length;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

266

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

281

static int read_channel_reply(struct dce_aux *engine, uint32_t size,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

283

uint32_t *sw_status)

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

286

uint32_t bytes_replied;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

287

uint32_t reply_result_32;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

311

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

321

uint32_t aux_sw_data_val;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

340

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

434

static uint32_t dce_aux_configure_timeout(struct ddc_service *ddc,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

435

uint32_t timeout_in_us)

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

437

uint32_t multiplier = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

438

uint32_t length = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

439

uint32_t prev_length = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

440

uint32_t prev_mult = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

441

uint32_t prev_timeout_val = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

509

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

510

uint32_t timeout_period,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

568

uint32_t status;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

644

unsigned char *payload, uint32_t length, uint32_t max_length_to_log)

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

652

uint32_t hex_str_remaining = sizeof(hex_str);

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

706

uint32_t defer_time_in_ms = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c

99

uint32_t value = REG_READ(AUX_ARB_CONTROL);

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

242

uint32_t inst;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

246

uint32_t delay;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

247

uint32_t max_defer_write_retry;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

254

DCE_AUX_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

268

uint32_t aux_control;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

269

uint32_t aux_arb_control;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

270

uint32_t aux_sw_data;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

271

uint32_t aux_sw_control;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

272

uint32_t aux_interrupt_control;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

273

uint32_t aux_dphy_rx_control1;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

274

uint32_t aux_dphy_rx_control0;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

275

uint32_t aux_sw_status;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

277

uint32_t polling_timeout_period;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

281

uint32_t engine_id;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

282

uint32_t timeout_period;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

289

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

290

uint32_t timeout_period,

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

314

uint32_t (*configure_timeout)

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

316

uint32_t timeout);

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

54

uint32_t AUX_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

55

uint32_t AUX_ARB_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

56

uint32_t AUX_SW_DATA;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

57

uint32_t AUX_SW_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

58

uint32_t AUX_INTERRUPT_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

59

uint32_t AUX_DPHY_RX_CONTROL1;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

60

uint32_t AUX_SW_STATUS;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

61

uint32_t AUXN_IMPCAL;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

62

uint32_t AUXP_IMPCAL;

sys/dev/pci/drm/amd/display/dc/dce/dce_aux.h

64

uint32_t AUX_RESET_MASK;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

184

static uint32_t get_max_pixel_clock_for_all_paths(struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

186

uint32_t max_pix_clk = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

548

static uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

551

uint32_t min_vertical_blank_time = -1;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

555

uint32_t vertical_blank_in_pixels = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c

556

uint32_t vertical_blank_time = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1365

static uint32_t dcn3_get_pix_clk_dividers(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

138

uint32_t target_pix_clk_100hz,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

139

uint32_t ref_divider,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

140

uint32_t post_divider,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

141

uint32_t *feedback_divider_param,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

142

uint32_t *fract_feedback_divider_param)

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1449

uint32_t *ss_entries_num)

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1456

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

1595

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

198

uint32_t ref_divider,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

199

uint32_t post_divider,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

200

uint32_t tolerance)

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

202

uint32_t feedback_divider;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

203

uint32_t fract_feedback_divider;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

204

uint32_t actual_calculated_clock_100hz;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

205

uint32_t abs_err;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

226

actual_calculated_clock_100hz = (uint32_t)(actual_calc_clk_100hz);

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

254

uint32_t min_ref_divider,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

255

uint32_t max_ref_divider,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

256

uint32_t min_post_divider,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

257

uint32_t max_post_divider,

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

258

uint32_t err_tolerance)

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

260

uint32_t ref_divider;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

261

uint32_t post_divider;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

262

uint32_t tolerance;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

293

static uint32_t calculate_pixel_clock_pll_dividers(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

297

uint32_t err_tolerance;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

298

uint32_t min_post_divider;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

299

uint32_t max_post_divider;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

300

uint32_t min_ref_divider;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

301

uint32_t max_ref_divider;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

401

uint32_t actual_pix_clk_100hz = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

402

uint32_t requested_clk_100hz = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

475

static uint32_t dce110_get_pix_clk_dividers_helper (

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

480

uint32_t field = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

481

uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

542

uint32_t actual_pixel_clock_100hz;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

568

static uint32_t dce110_get_pix_clk_dividers(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

574

uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

601

static uint32_t dce112_get_pix_clk_dividers(

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

65

uint32_t pix_clk_khz)

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

68

uint32_t entrys_num;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

69

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

804

uint32_t deep_color_cntl = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c

805

uint32_t double_rate_enable = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

216

CS_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

217

CS_REG_FIELD_LIST_DCN32(uint32_t)

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

221

uint32_t RESYNC_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

222

uint32_t PIXCLK_RESYNC_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

223

uint32_t PLL_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

228

uint32_t PHASE[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

229

uint32_t MODULO[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

230

uint32_t PIXEL_RATE_CNTL[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

241

uint32_t dp_ss_params_cnt;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

243

uint32_t hdmi_ss_params_cnt;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

245

uint32_t dvi_ss_params_cnt;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

247

uint32_t lvds_ss_params_cnt;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

249

uint32_t ext_clk_khz;

sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h

250

uint32_t ref_freq_khz;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

1093

uint32_t psp_version = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

110

uint32_t psr_state_offset = 0xf0;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

334

uint32_t dmcu_version_offset = 0xf1;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

358

uint32_t fractional_pwm)

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

465

uint32_t dmcub_psp_version = REG_READ(DMCUB_SCRATCH15);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

523

uint32_t psr_state_offset = 0xf0;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

70

static const uint32_t abm_gain_stepsize = 0x0060;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

821

uint32_t header, data1, data2;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

830

header = ((uint32_t)offset & 0xFFFF) << 16 | (total_length & 0xFFFF);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

831

data1 = (((uint32_t)data[0]) << 24) | (((uint32_t)data[1]) << 16) |

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

832

(((uint32_t)data[2]) << 8) | ((uint32_t)data[3]);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

833

data2 = (((uint32_t)data[4]) << 24) | (((uint32_t)data[5]) << 16) |

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

834

(((uint32_t)data[6]) << 8) | ((uint32_t)data[7]);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

856

uint32_t *cmd,

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

857

uint32_t *data1,

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

858

uint32_t *data2,

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

859

uint32_t *data3)

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

883

uint32_t data[4];

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c

908

uint32_t data[4];

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

203

DMCU_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

207

uint32_t DMCU_CTRL;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

208

uint32_t DMCU_STATUS;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

209

uint32_t DMCU_RAM_ACCESS_CTRL;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

210

uint32_t DCI_MEM_PWR_STATUS;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

211

uint32_t DMU_MEM_PWR_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

212

uint32_t DMCU_IRAM_WR_CTRL;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

213

uint32_t DMCU_IRAM_WR_DATA;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

215

uint32_t MASTER_COMM_DATA_REG1;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

216

uint32_t MASTER_COMM_DATA_REG2;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

217

uint32_t MASTER_COMM_DATA_REG3;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

218

uint32_t MASTER_COMM_CMD_REG;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

219

uint32_t MASTER_COMM_CNTL_REG;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

220

uint32_t SLAVE_COMM_DATA_REG1;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

221

uint32_t SLAVE_COMM_DATA_REG2;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

222

uint32_t SLAVE_COMM_DATA_REG3;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

223

uint32_t SLAVE_COMM_CMD_REG;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

224

uint32_t SLAVE_COMM_CNTL_REG;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

225

uint32_t DMCU_IRAM_RD_CTRL;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

226

uint32_t DMCU_IRAM_RD_DATA;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

227

uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

228

uint32_t SMU_INTERRUPT_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

229

uint32_t DC_DMCU_SCRATCH;

sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.h

230

uint32_t DMCUB_SCRATCH15;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

104

uint32_t length = reply->length;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

119

uint32_t i2c_data;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

146

uint32_t i2c_sw_status = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

162

uint32_t length = request->length;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

166

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

262

uint32_t speed)

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

264

uint32_t xtal_ref_div = 0, ref_base_div = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

265

uint32_t prescale = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

266

uint32_t i2c_ref_clock = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

297

uint32_t arbitrate = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

324

uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

325

uint32_t reset_length = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

393

uint32_t arbitrate = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

413

uint32_t i2c_sw_status = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

446

uint32_t counter = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

495

uint32_t timeout,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

499

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

539

static uint32_t get_transaction_timeout_hw(

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

541

uint32_t length,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

542

uint32_t speed)

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

544

uint32_t period_timeout;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

545

uint32_t num_of_clock_stretches;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

563

uint32_t speed)

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

568

uint32_t transaction_timeout;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

668

uint32_t engine_id,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

691

uint32_t engine_id,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

708

uint32_t engine_id,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

72

uint32_t i2c_sw_status = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

725

uint32_t engine_id,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

73

uint32_t value =

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

742

uint32_t engine_id,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c

93

static uint32_t get_hw_buffer_available_size(

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

195

uint32_t DC_I2C_DDC1_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

196

uint32_t DC_I2C_DDC1_TIME_LIMIT;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

197

uint32_t DC_I2C_DDC1_DATA_DRIVE_EN;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

198

uint32_t DC_I2C_DDC1_CLK_DRIVE_EN;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

199

uint32_t DC_I2C_DDC1_DATA_DRIVE_SEL;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

200

uint32_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

201

uint32_t DC_I2C_DDC1_INTRA_BYTE_DELAY;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

202

uint32_t DC_I2C_DDC1_HW_STATUS;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

203

uint32_t DC_I2C_SW_DONE_USING_I2C_REG;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

204

uint32_t DC_I2C_SW_USE_I2C_REG_REQ;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

205

uint32_t DC_I2C_NO_QUEUED_SW_GO;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

206

uint32_t DC_I2C_SW_PRIORITY;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

207

uint32_t DC_I2C_SOFT_RESET;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

208

uint32_t DC_I2C_SW_STATUS_RESET;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

209

uint32_t DC_I2C_GO;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

210

uint32_t DC_I2C_SEND_RESET;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

211

uint32_t DC_I2C_TRANSACTION_COUNT;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

212

uint32_t DC_I2C_DDC_SELECT;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

213

uint32_t DC_I2C_DDC1_PRESCALE;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

214

uint32_t DC_I2C_DDC1_THRESHOLD;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

215

uint32_t DC_I2C_DDC1_START_STOP_TIMING_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

216

uint32_t DC_I2C_SW_STOPPED_ON_NACK;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

217

uint32_t DC_I2C_SW_TIMEOUT;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

218

uint32_t DC_I2C_SW_ABORTED;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

219

uint32_t DC_I2C_SW_DONE;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

220

uint32_t DC_I2C_SW_STATUS;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

221

uint32_t DC_I2C_STOP_ON_NACK0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

222

uint32_t DC_I2C_START0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

223

uint32_t DC_I2C_RW0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

224

uint32_t DC_I2C_STOP0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

225

uint32_t DC_I2C_COUNT0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

226

uint32_t DC_I2C_DATA_RW;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

227

uint32_t DC_I2C_DATA;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

228

uint32_t DC_I2C_INDEX;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

229

uint32_t DC_I2C_INDEX_WRITE;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

230

uint32_t XTAL_REF_DIV;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

231

uint32_t MICROSECOND_TIME_BASE_DIV;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

232

uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

233

uint32_t DC_I2C_REG_RW_CNTL_STATUS;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

234

uint32_t I2C_LIGHT_SLEEP_FORCE;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

235

uint32_t I2C_MEM_PWR_STATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

236

uint32_t DC_I2C_DDC1_CLK_EN;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

257

uint32_t SETUP;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

258

uint32_t SPEED;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

259

uint32_t HW_STATUS;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

260

uint32_t DC_I2C_ARBITRATION;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

261

uint32_t DC_I2C_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

262

uint32_t DC_I2C_SW_STATUS;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

263

uint32_t DC_I2C_TRANSACTION0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

264

uint32_t DC_I2C_TRANSACTION1;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

265

uint32_t DC_I2C_TRANSACTION2;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

266

uint32_t DC_I2C_TRANSACTION3;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

267

uint32_t DC_I2C_DATA;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

268

uint32_t MICROSECOND_TIME_BASE_DIV;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

269

uint32_t DIO_MEM_PWR_CTRL;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

270

uint32_t DIO_MEM_PWR_STATUS;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

282

uint32_t length;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

288

uint32_t engine_keep_power_up_count;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

289

uint32_t transaction_count;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

290

uint32_t buffer_used_bytes;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

291

uint32_t buffer_used_write;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

292

uint32_t reference_frequency;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

293

uint32_t default_speed;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

294

uint32_t engine_id;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

295

uint32_t setup_limit;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

296

uint32_t send_reset_length;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

297

uint32_t buffer_size;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

308

uint32_t engine_id,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

316

uint32_t engine_id,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

324

uint32_t engine_id,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

332

uint32_t engine_id,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.h

340

uint32_t engine_id,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

217

uint32_t retry = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

254

uint32_t length,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

257

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

276

uint32_t length,

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

279

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

301

uint32_t retry = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

342

uint32_t speed)

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

375

uint32_t counter = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

43

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

58

uint32_t value = bit ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

79

uint32_t scl_retry = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.c

80

uint32_t scl_retry_max = I2C_SW_TIMEOUT_DELAY / clock_delay_div_4;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.h

38

uint32_t clock_delay;

sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_sw.h

39

uint32_t speed;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c

222

uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c

238

uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

235

IPP_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

239

uint32_t CUR_UPDATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

240

uint32_t CUR_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

241

uint32_t CUR_POSITION;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

242

uint32_t CUR_HOT_SPOT;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

243

uint32_t CUR_COLOR1;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

244

uint32_t CUR_COLOR2;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

245

uint32_t CUR_SIZE;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

246

uint32_t CUR_SURFACE_ADDRESS_HIGH;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

247

uint32_t CUR_SURFACE_ADDRESS;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

248

uint32_t PRESCALE_GRPH_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

249

uint32_t PRESCALE_VALUES_GRPH_R;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

250

uint32_t PRESCALE_VALUES_GRPH_G;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

251

uint32_t PRESCALE_VALUES_GRPH_B;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

252

uint32_t INPUT_GAMMA_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

253

uint32_t DCFE_MEM_PWR_CTRL;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

254

uint32_t DC_LUT_WRITE_EN_MASK;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

255

uint32_t DC_LUT_RW_MODE;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

256

uint32_t DC_LUT_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

257

uint32_t DC_LUT_RW_INDEX;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

258

uint32_t DC_LUT_SEQ_COLOR;

sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.h

259

uint32_t DEGAMMA_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1051

uint32_t pixel_clock)

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1087

uint32_t pixel_clock)

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1485

uint32_t *src,

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1486

uint32_t *slots)

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1505

uint32_t value1 = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1506

uint32_t value2 = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1507

uint32_t slots = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1508

uint32_t src = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1509

uint32_t retries = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1626

uint32_t field;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1645

uint32_t addr = HPD_REG(DC_HPD_CONTROL);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1646

uint32_t hpd_enable = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1647

uint32_t value = dm_read_reg(ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1659

uint32_t addr = HPD_REG(DC_HPD_CONTROL);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

1660

uint32_t value = dm_read_reg(ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

275

uint32_t index)

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

298

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

629

uint32_t addr = AUX_REG(AUX_CONTROL);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

630

uint32_t value = dm_read_reg(ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

683

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c

717

uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

137

uint32_t AUX_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

138

uint32_t AUX_DPHY_RX_CONTROL0;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

139

uint32_t AUX_DPHY_RX_CONTROL1;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

143

uint32_t DC_HPD_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

148

uint32_t MASTER_COMM_DATA_REG1;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

149

uint32_t MASTER_COMM_DATA_REG2;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

150

uint32_t MASTER_COMM_DATA_REG3;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

151

uint32_t MASTER_COMM_CMD_REG;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

152

uint32_t MASTER_COMM_CNTL_REG;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

153

uint32_t DMCU_RAM_ACCESS_CTRL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

154

uint32_t DCI_MEM_PWR_STATUS;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

155

uint32_t DMU_MEM_PWR_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

156

uint32_t DMCU_IRAM_RD_CTRL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

157

uint32_t DMCU_IRAM_RD_DATA;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

158

uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

161

uint32_t DIG_BE_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

162

uint32_t DIG_BE_EN_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

163

uint32_t DP_CONFIG;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

164

uint32_t DP_DPHY_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

165

uint32_t DP_DPHY_INTERNAL_CTRL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

166

uint32_t DP_DPHY_PRBS_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

167

uint32_t DP_DPHY_SCRAM_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

168

uint32_t DP_DPHY_SYM0;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

169

uint32_t DP_DPHY_SYM1;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

170

uint32_t DP_DPHY_SYM2;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

171

uint32_t DP_DPHY_TRAINING_PATTERN_SEL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

172

uint32_t DP_LINK_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

173

uint32_t DP_LINK_FRAMING_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

174

uint32_t DP_MSE_SAT0;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

175

uint32_t DP_MSE_SAT1;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

176

uint32_t DP_MSE_SAT2;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

177

uint32_t DP_MSE_SAT_UPDATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

178

uint32_t DP_SEC_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

179

uint32_t DP_VID_STREAM_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

180

uint32_t DP_DPHY_FAST_TRAINING;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

181

uint32_t DP_DPHY_BS_SR_SWAP_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

182

uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

183

uint32_t DP_SEC_CNTL1;

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

254

uint32_t pixel_clock);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

272

uint32_t pixel_clock);

sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.h

303

uint32_t index);

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

165

uint32_t wm_select,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

166

uint32_t urgency_low_wm,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

167

uint32_t urgency_high_wm)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

180

uint32_t wm_select,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

181

uint32_t urgency_low_wm,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

182

uint32_t urgency_high_wm)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

195

uint32_t wm_select,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

196

uint32_t urgency_low_wm,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

197

uint32_t urgency_high_wm)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

215

uint32_t wm_select,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

216

uint32_t nbp_wm)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

233

uint32_t wm_select,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

234

uint32_t nbp_wm)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

266

uint32_t wm_select,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

267

uint32_t stutter_mark)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

279

uint32_t wm_select,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

280

uint32_t stutter_mark,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

281

uint32_t stutter_entry)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

298

uint32_t wm_select,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

299

uint32_t stutter_mark)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

318

uint32_t total_dest_line_time_ns)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

321

uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

345

uint32_t total_dest_line_time_ns)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

348

uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

371

uint32_t total_dest_line_time_ns)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

374

uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

404

uint32_t total_dest_line_time_ns)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

407

uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

491

const uint32_t rotation_angles[ROTATION_ANGLE_COUNT] = {

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

559

uint32_t red_xbar = 0, blue_xbar = 0; /* no swap */

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

560

uint32_t grph_depth = 0, grph_format = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

561

uint32_t sign = 0, floating = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

690

static uint32_t get_dmif_switch_time_us(

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

691

uint32_t h_total,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

692

uint32_t v_total,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

693

uint32_t pix_clk_khz)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

695

uint32_t frame_time;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

696

uint32_t pixels_per_second;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

697

uint32_t pixels_per_frame;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

698

uint32_t refresh_rate;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

699

const uint32_t us_in_sec = 1000000;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

700

const uint32_t min_single_frame_time_us = 30000;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

702

const uint32_t single_frame_time_multiplier = 2;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

738

uint32_t h_total,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

739

uint32_t v_total,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

740

uint32_t pix_clk_khz,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

741

uint32_t total_stream_num)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

744

const uint32_t retry_delay = 10;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

745

uint32_t retry_count = get_dmif_switch_time_us(

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

750

uint32_t pix_dur;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

751

uint32_t buffers_allocated;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

752

uint32_t dmif_buffer_control;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

775

uint32_t enable = (total_stream_num > 1) ? 0 :

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

785

uint32_t total_stream_num)

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

788

uint32_t buffers_allocated;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

789

uint32_t dmif_buffer_control;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

805

uint32_t enable = (total_stream_num > 1) ? 0 :

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

846

uint32_t update_pending;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

111

uint32_t GRPH_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

112

uint32_t GRPH_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

113

uint32_t GRPH_X_START;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

114

uint32_t GRPH_Y_START;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

115

uint32_t GRPH_X_END;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

116

uint32_t GRPH_Y_END;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

117

uint32_t GRPH_PITCH;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

118

uint32_t HW_ROTATION;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

119

uint32_t GRPH_SWAP_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

120

uint32_t PRESCALE_GRPH_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

121

uint32_t GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

122

uint32_t DVMM_PTE_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

123

uint32_t DVMM_PTE_ARB_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

124

uint32_t GRPH_UPDATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

125

uint32_t GRPH_FLIP_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

126

uint32_t GRPH_PRIMARY_SURFACE_ADDRESS;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

127

uint32_t GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

128

uint32_t GRPH_SECONDARY_SURFACE_ADDRESS;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

129

uint32_t GRPH_SECONDARY_SURFACE_ADDRESS_HIGH;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

131

uint32_t DPG_PIPE_ARBITRATION_CONTROL1;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

133

uint32_t DPG_PIPE_ARBITRATION_CONTROL3;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

135

uint32_t DPG_WATERMARK_MASK_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

136

uint32_t DPG_PIPE_URGENCY_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

137

uint32_t DPG_PIPE_URGENT_LEVEL_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

138

uint32_t DPG_PIPE_NB_PSTATE_CHANGE_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

139

uint32_t DPG_PIPE_LOW_POWER_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

140

uint32_t DPG_PIPE_STUTTER_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

141

uint32_t DPG_PIPE_STUTTER_CONTROL2;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

143

uint32_t DMIF_BUFFER_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

145

uint32_t MC_HUB_RDREQ_DMIF_LIMIT;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

147

uint32_t DCHUB_FB_LOCATION;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

148

uint32_t DCHUB_AGP_BASE;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

149

uint32_t DCHUB_AGP_BOT;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

150

uint32_t DCHUB_AGP_TOP;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

416

MI_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

581

uint32_t fmt_mem_cntl_value;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

726

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

745

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

283

OPP_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

287

uint32_t FMT_DYNAMIC_EXP_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

288

uint32_t FMT_BIT_DEPTH_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

289

uint32_t FMT_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

290

uint32_t FMT_DITHER_RAND_R_SEED;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

291

uint32_t FMT_DITHER_RAND_G_SEED;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

292

uint32_t FMT_DITHER_RAND_B_SEED;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

293

uint32_t FMT_TEMPORAL_DITHER_PATTERN_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

294

uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

295

uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

296

uint32_t CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

297

uint32_t FMT_CLAMP_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

298

uint32_t FMT_CLAMP_COMPONENT_R;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

299

uint32_t FMT_CLAMP_COMPONENT_G;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

300

uint32_t FMT_CLAMP_COMPONENT_B;

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

316

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

324

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

150

uint32_t blon, blon_ovrd, pwrseq_target_state;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

164

uint32_t pwr_seq_state, dig_on, dig_on_ovrd;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

189

uint32_t backlight_pwm_u16_16)

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

191

uint32_t backlight_16bit;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

192

uint32_t masked_pwm_period;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

195

uint32_t pwm_period_bitcnt;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

52

uint32_t bl_period, bl_int_count;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

53

uint32_t bl_pwm, fractional_duty_cycle_en;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

54

uint32_t bl_period_mask, bl_pwm_mask;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

62

REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm));

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

86

return (uint32_t)(current_backlight);

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

89

static uint32_t dce_panel_cntl_hw_init(struct panel_cntl *panel_cntl)

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

92

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c

93

uint32_t current_backlight;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h

101

DCE_PANEL_CNTL_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h

105

uint32_t PWRSEQ_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h

106

uint32_t PWRSEQ_STATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h

107

uint32_t BL_PWM_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h

108

uint32_t BL_PWM_CNTL2;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h

109

uint32_t BL_PWM_PERIOD_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h

110

uint32_t BL_PWM_GRP1_REG_LOCK;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h

111

uint32_t PWRSEQ_REF_DIV;

sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.h

112

uint32_t BIOS_SCRATCH_2;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1150

static uint32_t calc_max_audio_packets_per_line(

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1153

uint32_t max_packets_per_line;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

117

const uint32_t *content =

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1173

uint32_t crtc_pixel_clock_100Hz,

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1174

uint32_t actual_pixel_clock_100Hz,

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1178

uint32_t index;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1179

uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

118

(const uint32_t *) &info_packet->sb[0];

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1180

uint32_t audio_array_size;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1239

uint32_t channels = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1262

uint32_t max_packets_per_line;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1418

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

1507

uint32_t tg_inst = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

179

uint32_t packet_index,

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

182

uint32_t cont, send, line;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

272

uint32_t enable_sdp_splitting)

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

274

uint32_t h_active_start;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

275

uint32_t v_active_start;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

276

uint32_t misc0 = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

277

uint32_t misc1 = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

278

uint32_t h_blank;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

279

uint32_t h_back_porch;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

64

uint32_t packet_index,

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

70

uint32_t max_retries = 50;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

701

uint32_t x = dc_fixpt_floor(

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

703

uint32_t y = dc_fixpt_ceil(

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

734

const uint32_t *content =

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

735

(const uint32_t *) &info_frame->avi.sb[0];

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

834

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

878

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

905

uint32_t reg1 = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

906

uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

957

uint32_t n_vid = 0x8000;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

958

uint32_t m_vid;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

971

m_vid = (uint32_t) m_vid_l;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

500

uint32_t AFMT_GENERIC_INDEX;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

501

uint32_t AFMT_GENERIC0_UPDATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

502

uint32_t AFMT_GENERIC2_UPDATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

503

uint32_t AFMT_GENERIC_HB0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

504

uint32_t AFMT_GENERIC_HB1;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

505

uint32_t AFMT_GENERIC_HB2;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

506

uint32_t AFMT_GENERIC_HB3;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

507

uint32_t AFMT_GENERIC_LOCK_STATUS;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

508

uint32_t AFMT_GENERIC_CONFLICT;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

509

uint32_t AFMT_GENERIC_CONFLICT_CLR;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

510

uint32_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

511

uint32_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

512

uint32_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

513

uint32_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

514

uint32_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

515

uint32_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

516

uint32_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

517

uint32_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

518

uint32_t AFMT_GENERIC0_FRAME_UPDATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

519

uint32_t AFMT_GENERIC1_FRAME_UPDATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

520

uint32_t AFMT_GENERIC2_FRAME_UPDATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

521

uint32_t AFMT_GENERIC3_FRAME_UPDATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

522

uint32_t AFMT_GENERIC4_FRAME_UPDATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

523

uint32_t AFMT_GENERIC5_FRAME_UPDATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

524

uint32_t AFMT_GENERIC6_FRAME_UPDATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

525

uint32_t AFMT_GENERIC7_FRAME_UPDATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

526

uint32_t HDMI_GENERIC0_CONT;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

527

uint32_t HDMI_GENERIC0_SEND;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

528

uint32_t HDMI_GENERIC0_LINE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

529

uint32_t HDMI_GENERIC1_CONT;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

530

uint32_t HDMI_GENERIC1_SEND;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

531

uint32_t HDMI_GENERIC1_LINE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

532

uint32_t DP_PIXEL_ENCODING;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

533

uint32_t DP_COMPONENT_DEPTH;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

534

uint32_t DP_DYN_RANGE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

535

uint32_t DP_YCBCR_RANGE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

536

uint32_t HDMI_PACKET_GEN_VERSION;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

537

uint32_t HDMI_KEEPOUT_MODE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

538

uint32_t HDMI_DEEP_COLOR_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

539

uint32_t HDMI_CLOCK_CHANNEL_RATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

540

uint32_t HDMI_DEEP_COLOR_DEPTH;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

541

uint32_t HDMI_GC_CONT;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

542

uint32_t HDMI_GC_SEND;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

543

uint32_t HDMI_NULL_SEND;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

544

uint32_t HDMI_DATA_SCRAMBLE_EN;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

545

uint32_t HDMI_ACP_SEND;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

546

uint32_t HDMI_AUDIO_INFO_SEND;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

547

uint32_t AFMT_AUDIO_INFO_UPDATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

548

uint32_t HDMI_AUDIO_INFO_LINE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

549

uint32_t HDMI_GC_AVMUTE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

550

uint32_t DP_MSE_RATE_X;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

551

uint32_t DP_MSE_RATE_Y;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

552

uint32_t DP_MSE_RATE_UPDATE_PENDING;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

553

uint32_t AFMT_AVI_INFO_VERSION;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

554

uint32_t HDMI_AVI_INFO_SEND;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

555

uint32_t HDMI_AVI_INFO_CONT;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

556

uint32_t HDMI_AVI_INFO_LINE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

557

uint32_t DP_SEC_GSP0_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

558

uint32_t DP_SEC_STREAM_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

559

uint32_t DP_SEC_GSP1_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

560

uint32_t DP_SEC_GSP2_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

561

uint32_t DP_SEC_GSP3_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

562

uint32_t DP_SEC_GSP4_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

563

uint32_t DP_SEC_GSP5_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

564

uint32_t DP_SEC_GSP6_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

565

uint32_t DP_SEC_GSP7_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

566

uint32_t DP_SEC_AVI_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

567

uint32_t DP_SEC_MPG_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

568

uint32_t DP_VID_STREAM_DIS_DEFER;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

569

uint32_t DP_VID_STREAM_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

570

uint32_t DP_VID_STREAM_STATUS;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

571

uint32_t DP_STEER_FIFO_RESET;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

572

uint32_t DP_VID_M_N_GEN_EN;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

573

uint32_t DP_VID_N;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

574

uint32_t DP_VID_M;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

575

uint32_t DIG_START;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

576

uint32_t AFMT_AUDIO_SRC_SELECT;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

577

uint32_t AFMT_AUDIO_CHANNEL_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

578

uint32_t HDMI_AUDIO_PACKETS_PER_LINE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

579

uint32_t HDMI_AUDIO_DELAY_EN;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

580

uint32_t AFMT_60958_CS_UPDATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

581

uint32_t AFMT_AUDIO_LAYOUT_OVRD;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

582

uint32_t AFMT_60958_OSF_OVRD;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

583

uint32_t HDMI_ACR_AUTO_SEND;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

584

uint32_t HDMI_ACR_SOURCE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

585

uint32_t HDMI_ACR_AUDIO_PRIORITY;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

586

uint32_t HDMI_ACR_CTS_32;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

587

uint32_t HDMI_ACR_N_32;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

588

uint32_t HDMI_ACR_CTS_44;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

589

uint32_t HDMI_ACR_N_44;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

590

uint32_t HDMI_ACR_CTS_48;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

591

uint32_t HDMI_ACR_N_48;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

592

uint32_t AFMT_60958_CS_CHANNEL_NUMBER_L;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

593

uint32_t AFMT_60958_CS_CLOCK_ACCURACY;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

594

uint32_t AFMT_60958_CS_CHANNEL_NUMBER_R;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

595

uint32_t AFMT_60958_CS_CHANNEL_NUMBER_2;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

596

uint32_t AFMT_60958_CS_CHANNEL_NUMBER_3;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

597

uint32_t AFMT_60958_CS_CHANNEL_NUMBER_4;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

598

uint32_t AFMT_60958_CS_CHANNEL_NUMBER_5;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

599

uint32_t AFMT_60958_CS_CHANNEL_NUMBER_6;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

600

uint32_t AFMT_60958_CS_CHANNEL_NUMBER_7;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

601

uint32_t DP_SEC_AUD_N;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

602

uint32_t DP_SEC_TIMESTAMP_MODE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

603

uint32_t DP_SEC_ASP_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

604

uint32_t DP_SEC_ATP_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

605

uint32_t DP_SEC_AIP_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

606

uint32_t DP_SEC_ACM_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

607

uint32_t AFMT_AUDIO_SAMPLE_SEND;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

608

uint32_t AFMT_AUDIO_CLOCK_EN;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

609

uint32_t TMDS_PIXEL_ENCODING;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

610

uint32_t DIG_STEREOSYNC_SELECT;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

611

uint32_t DIG_STEREOSYNC_GATE_EN;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

612

uint32_t TMDS_COLOR_FORMAT;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

613

uint32_t DP_DB_DISABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

614

uint32_t DP_MSA_MISC0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

615

uint32_t DP_MSA_HTOTAL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

616

uint32_t DP_MSA_VTOTAL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

617

uint32_t DP_MSA_HSTART;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

618

uint32_t DP_MSA_VSTART;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

619

uint32_t DP_MSA_HSYNCWIDTH;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

620

uint32_t DP_MSA_HSYNCPOLARITY;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

621

uint32_t DP_MSA_VSYNCWIDTH;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

622

uint32_t DP_MSA_VSYNCPOLARITY;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

623

uint32_t DP_MSA_HWIDTH;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

624

uint32_t DP_MSA_VHEIGHT;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

625

uint32_t HDMI_DB_DISABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

626

uint32_t DP_VID_N_MUL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

627

uint32_t DP_VID_M_DOUBLE_VALUE_EN;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

628

uint32_t DIG_SOURCE_SELECT;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

632

uint32_t AFMT_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

633

uint32_t AFMT_AVI_INFO0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

634

uint32_t AFMT_AVI_INFO1;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

635

uint32_t AFMT_AVI_INFO2;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

636

uint32_t AFMT_AVI_INFO3;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

637

uint32_t AFMT_GENERIC_0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

638

uint32_t AFMT_GENERIC_1;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

639

uint32_t AFMT_GENERIC_2;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

640

uint32_t AFMT_GENERIC_3;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

641

uint32_t AFMT_GENERIC_4;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

642

uint32_t AFMT_GENERIC_5;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

643

uint32_t AFMT_GENERIC_6;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

644

uint32_t AFMT_GENERIC_7;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

645

uint32_t AFMT_GENERIC_HDR;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

646

uint32_t AFMT_INFOFRAME_CONTROL0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

647

uint32_t AFMT_VBI_PACKET_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

648

uint32_t AFMT_VBI_PACKET_CONTROL1;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

649

uint32_t AFMT_AUDIO_PACKET_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

650

uint32_t AFMT_AUDIO_PACKET_CONTROL2;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

651

uint32_t AFMT_AUDIO_SRC_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

652

uint32_t AFMT_60958_0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

653

uint32_t AFMT_60958_1;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

654

uint32_t AFMT_60958_2;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

655

uint32_t DIG_FE_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

656

uint32_t DP_MSE_RATE_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

657

uint32_t DP_MSE_RATE_UPDATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

658

uint32_t DP_PIXEL_FORMAT;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

659

uint32_t DP_SEC_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

660

uint32_t DP_STEER_FIFO;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

661

uint32_t DP_VID_M;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

662

uint32_t DP_VID_N;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

663

uint32_t DP_VID_STREAM_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

664

uint32_t DP_VID_TIMING;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

665

uint32_t DP_SEC_AUD_N;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

666

uint32_t DP_SEC_TIMESTAMP;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

667

uint32_t HDMI_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

668

uint32_t HDMI_GC;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

669

uint32_t HDMI_GENERIC_PACKET_CONTROL0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

670

uint32_t HDMI_GENERIC_PACKET_CONTROL1;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

671

uint32_t HDMI_GENERIC_PACKET_CONTROL2;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

672

uint32_t HDMI_GENERIC_PACKET_CONTROL3;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

673

uint32_t HDMI_INFOFRAME_CONTROL0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

674

uint32_t HDMI_INFOFRAME_CONTROL1;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

675

uint32_t HDMI_VBI_PACKET_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

676

uint32_t HDMI_AUDIO_PACKET_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

677

uint32_t HDMI_ACR_PACKET_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

678

uint32_t HDMI_ACR_32_0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

679

uint32_t HDMI_ACR_32_1;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

680

uint32_t HDMI_ACR_44_0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

681

uint32_t HDMI_ACR_44_1;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

682

uint32_t HDMI_ACR_48_0;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

683

uint32_t HDMI_ACR_48_1;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

684

uint32_t TMDS_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

685

uint32_t DP_DB_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

686

uint32_t DP_MSA_MISC;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

687

uint32_t DP_MSA_COLORIMETRY;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

688

uint32_t DP_MSA_TIMING_PARAM1;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

689

uint32_t DP_MSA_TIMING_PARAM2;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

690

uint32_t DP_MSA_TIMING_PARAM3;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

691

uint32_t DP_MSA_TIMING_PARAM4;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

692

uint32_t HDMI_DB_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1146

static uint32_t decide_taps(struct fixed31_32 ratio, uint32_t in_taps, bool chroma)

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1148

uint32_t taps;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1382

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1416

uint32_t retval;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1419

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1636

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

1665

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

221

uint32_t power_ctl = 0;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

533

XFM_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

538

uint32_t DATA_FORMAT;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

540

uint32_t LB_DATA_FORMAT;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

541

uint32_t GAMUT_REMAP_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

542

uint32_t GAMUT_REMAP_C11_C12;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

543

uint32_t GAMUT_REMAP_C13_C14;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

544

uint32_t GAMUT_REMAP_C21_C22;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

545

uint32_t GAMUT_REMAP_C23_C24;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

546

uint32_t GAMUT_REMAP_C31_C32;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

547

uint32_t GAMUT_REMAP_C33_C34;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

548

uint32_t OUTPUT_CSC_C11_C12;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

549

uint32_t OUTPUT_CSC_C13_C14;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

550

uint32_t OUTPUT_CSC_C21_C22;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

551

uint32_t OUTPUT_CSC_C23_C24;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

552

uint32_t OUTPUT_CSC_C31_C32;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

553

uint32_t OUTPUT_CSC_C33_C34;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

554

uint32_t OUTPUT_CSC_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

555

uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

556

uint32_t REGAMMA_CNTLA_START_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

557

uint32_t REGAMMA_CNTLA_SLOPE_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

558

uint32_t REGAMMA_CNTLA_END_CNTL1;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

559

uint32_t REGAMMA_CNTLA_END_CNTL2;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

560

uint32_t REGAMMA_CNTLA_REGION_0_1;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

561

uint32_t REGAMMA_CNTLA_REGION_2_3;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

562

uint32_t REGAMMA_CNTLA_REGION_4_5;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

563

uint32_t REGAMMA_CNTLA_REGION_6_7;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

564

uint32_t REGAMMA_CNTLA_REGION_8_9;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

565

uint32_t REGAMMA_CNTLA_REGION_10_11;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

566

uint32_t REGAMMA_CNTLA_REGION_12_13;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

567

uint32_t REGAMMA_CNTLA_REGION_14_15;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

568

uint32_t REGAMMA_LUT_WRITE_EN_MASK;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

569

uint32_t REGAMMA_LUT_INDEX;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

570

uint32_t REGAMMA_LUT_DATA;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

571

uint32_t REGAMMA_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

572

uint32_t DENORM_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

573

uint32_t DCP_SPATIAL_DITHER_CNTL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

574

uint32_t OUT_ROUND_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

575

uint32_t OUT_CLAMP_CONTROL_R_CR;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

576

uint32_t OUT_CLAMP_CONTROL_G_Y;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

577

uint32_t OUT_CLAMP_CONTROL_B_CB;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

578

uint32_t SCL_MODE;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

579

uint32_t SCL_TAP_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

580

uint32_t SCL_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

581

uint32_t SCL_BYPASS_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

582

uint32_t EXT_OVERSCAN_LEFT_RIGHT;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

583

uint32_t EXT_OVERSCAN_TOP_BOTTOM;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

584

uint32_t SCL_VERT_FILTER_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

585

uint32_t SCL_HORZ_FILTER_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

586

uint32_t DCFE_MEM_PWR_CTRL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

587

uint32_t DCFE_MEM_PWR_STATUS;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

588

uint32_t SCL_COEF_RAM_SELECT;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

589

uint32_t SCL_COEF_RAM_TAP_DATA;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

590

uint32_t VIEWPORT_START;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

591

uint32_t VIEWPORT_SIZE;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

592

uint32_t SCL_HORZ_FILTER_SCALE_RATIO;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

593

uint32_t SCL_VERT_FILTER_SCALE_RATIO;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

594

uint32_t SCL_HORZ_FILTER_INIT;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

596

uint32_t SCL_SCALER_ENABLE;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

597

uint32_t SCL_HORZ_FILTER_INIT_RGB_LUMA;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

598

uint32_t SCL_HORZ_FILTER_INIT_CHROMA;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

600

uint32_t SCL_VERT_FILTER_INIT;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

601

uint32_t SCL_AUTOMATIC_MODE_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

603

uint32_t DC_LB_MEMORY_SPLIT;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

604

uint32_t DC_LB_MEM_SIZE;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

606

uint32_t LB_MEMORY_CTRL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

607

uint32_t SCL_UPDATE;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

608

uint32_t SCL_F_SHARP_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

612

uint32_t integer;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

613

uint32_t fraction;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

617

uint32_t h_int_scale_ratio;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

618

uint32_t v_int_scale_ratio;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

625

uint32_t h_int_scale_ratio;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

626

uint32_t v_int_scale_ratio;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

660

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

668

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

155

uint32_t otg_inst,

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

156

uint32_t option,

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

157

uint32_t panel_inst,

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

158

uint32_t pwrseq_inst)

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

62

static void dmub_abm_init_ex(struct abm *abm, uint32_t backlight, uint32_t user_level)

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm.c

81

static bool dmub_abm_set_level_ex(struct abm *abm, uint32_t level)

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

141

bool dmub_abm_set_level(struct abm *abm, uint32_t level, uint8_t panel_mask)

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

255

uint32_t otg_inst,

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

256

uint32_t option,

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

257

uint32_t panel_inst,

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

258

uint32_t pwrseq_inst)

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

59

uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == false) ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

60

uint32_t edp_id_count = dc->dc_edp_id_count;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

78

void dmub_abm_init(struct abm *abm, uint32_t backlight, uint32_t user_level)

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.h

33

void dmub_abm_init(struct abm *abm, uint32_t backlight, uint32_t user_level);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.h

34

bool dmub_abm_set_level(struct abm *abm, uint32_t level, uint8_t panel_mask);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.h

47

bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, uint32_t option, uint32_t panel_inst, uint32_t pwrseq_inst);

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

110

uint32_t raw_state = 0;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

111

uint32_t retry_count = 0;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

183

uint32_t retry_count;

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

43

static enum dc_psr_state convert_psr_state(uint32_t raw_state)

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

454

static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency,

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.h

49

void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency,

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

215

uint32_t coasting_vtotal,

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

238

uint32_t *residency, const bool is_start, enum pr_residency_mode mode)

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

241

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

26

uint32_t retry_count = 0;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

286

unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal)

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

31

(uint32_t *)state, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) {

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

51

uint32_t retry_count;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.h

29

void (*replay_set_coasting_vtotal)(struct dmub_replay *dmub, uint32_t coasting_vtotal,

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.h

32

uint8_t panel_inst, uint32_t *residency, const bool is_start, const enum pr_residency_mode mode);

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.h

34

unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

114

uint32_t counter = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

115

uint32_t addr = mmFBC_STATUS;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

116

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

141

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

142

uint32_t addr;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

194

uint32_t addr;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

195

uint32_t value, misc_value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

241

uint32_t crtc_inst = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

245

uint32_t reg_data;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

267

uint32_t *inst)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

270

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

299

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

300

uint32_t fbc_pitch = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

301

uint32_t compressed_surf_address_low_part =

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

345

uint32_t fbc_trigger)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

350

uint32_t addr = mmFBC_CLIENT_REGION_MASK;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

351

uint32_t value = dm_read_reg(compressor->ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

65

static uint32_t align_to_chunks_number_per_line(uint32_t pixels)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

70

static void reset_lb_on_vblank(struct compressor *compressor, uint32_t crtc_inst)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

72

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

73

uint32_t frame_count;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

74

uint32_t status_pos;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c

75

uint32_t retry = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.h

34

uint32_t dcp_offset;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.h

35

uint32_t dmif_offset;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.h

59

uint32_t fbc_trigger);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.h

66

uint32_t *fbc_mapped_crtc_id);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

1010

uint32_t total_stream_num)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

154

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

168

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

233

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

365

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

43

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

439

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

474

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

581

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

64

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

65

uint32_t temp = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

655

const uint32_t urgency_addr,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

656

const uint32_t wm_addr,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

658

uint32_t total_dest_line_time_ns)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

661

uint32_t urgency_cntl = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

662

uint32_t wm_mask_cntl = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

713

uint32_t total_dest_line_time_ns)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

726

uint32_t total_dest_line_time_ns)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

738

const uint32_t stutter_addr,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

739

const uint32_t wm_addr,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

743

uint32_t stutter_cntl = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

744

uint32_t wm_mask_cntl = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

820

const uint32_t wm_mask_ctrl_addr,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

821

const uint32_t nbp_pstate_ctrl_addr,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

824

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

928

uint32_t total_dest_line_time_ns)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

950

uint32_t total_dest_line_time_ns)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

968

uint32_t h_total,/* for current stream */

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

969

uint32_t v_total,/* for current stream */

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

970

uint32_t pix_clk_khz,/* for current stream */

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

971

uint32_t total_stream_num)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

973

uint32_t addr;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

974

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

975

uint32_t pix_dur;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

98

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c

99

uint32_t temp = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

114

uint32_t cntl_value = dm_read_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

127

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

128

uint32_t addr = mmOUTPUT_CSC_C11_C12_A;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

145

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

146

uint32_t addr = mmOUTPUT_CSC_C13_C14_A;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

163

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

164

uint32_t addr = mmOUTPUT_CSC_C21_C22_A;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

181

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

182

uint32_t addr = mmOUTPUT_CSC_C23_C24_A;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

199

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

200

uint32_t addr = mmOUTPUT_CSC_C31_C32_A;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

217

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

218

uint32_t addr = mmOUTPUT_CSC_C33_C34_A;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

241

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

242

uint32_t addr = mmOUTPUT_CSC_C11_C12_B;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

259

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

260

uint32_t addr = mmOUTPUT_CSC_C13_C14_B;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

277

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

278

uint32_t addr = mmOUTPUT_CSC_C21_C22_B;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

295

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

296

uint32_t addr = mmOUTPUT_CSC_C23_C24_B;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

313

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

314

uint32_t addr = mmOUTPUT_CSC_C31_C32_B;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

331

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

332

uint32_t addr = mmOUTPUT_CSC_C33_C34_B;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

365

uint32_t addr = mmCOL_MAN_OUTPUT_CSC_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

366

uint32_t value = dm_read_reg(ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

465

uint32_t value = dm_read_reg(xfm->ctx, mmDENORM_CLAMP_CONTROL);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

508

uint32_t regval[12];

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

536

const uint32_t *regval = NULL;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

538

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

683

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

101

static void configure_regamma_mode(struct dce_transform *xfm_dce, uint32_t mode)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

103

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

134

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

37

uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

454

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

470

const uint32_t addr = mmGAMMA_CORR_LUT_DATA;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

471

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

521

uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

86

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

107

uint32_t early_cntl)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

109

uint32_t regval;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

111

uint32_t address = CRTC_REG(mmCRTC_CONTROL);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1118

uint32_t h_blank;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1119

uint32_t h_back_porch, hsync_offset, h_sync_start;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1221

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1223

uint32_t address = DCP_REG(mmDCP_GSL_CONTROL);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1224

uint32_t check_point = FLIP_READY_BACK_LOOKUP;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1273

uint32_t value_crtc_vtotal;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

128

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1322

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1324

uint32_t address = DCP_REG(mmDCP_GSL_CONTROL);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1415

uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1416

uint32_t value = dm_read_reg(tg->ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1477

uint32_t addr = CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1478

uint32_t value = dm_read_reg(ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1493

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1494

uint32_t rising_edge = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1495

uint32_t falling_edge = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1501

uint32_t pol_value = dm_read_reg(tg->ctx,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

156

uint32_t addr = CRTC_REG(mmCRTC_BLACK_COLOR);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

157

uint32_t value = dm_read_reg(tg->ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1583

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1584

uint32_t rising_edge = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1585

uint32_t falling_edge = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1713

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1778

uint32_t value = dm_read_reg(tg->ctx,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1780

uint32_t value1 = dm_read_reg(tg->ctx,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1800

uint32_t addr = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1801

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1850

uint32_t addr;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1851

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1897

uint32_t addr = CRTC_REG(mmCRTC_BLACK_COLOR);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1898

uint32_t value = dm_read_reg(tg->ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

192

uint32_t addr = CRTC_REG(mmCRTC_3D_STRUCTURE_CONTROL);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1926

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1927

uint32_t addr;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

193

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

194

uint32_t test = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

195

uint32_t field = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

196

uint32_t struc_en = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

197

uint32_t struc_stereo_sel_ovr = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1971

uint32_t value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_BLANK_CONTROL));

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

1989

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2069

uint32_t v_blank_start = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2070

uint32_t v_blank_end = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2071

uint32_t val = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2072

uint32_t h_position, v_position;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2104

uint32_t addr = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2105

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2106

uint32_t field = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2119

uint32_t cntl_addr = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2120

uint32_t addr = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2121

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2255

uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2257

uint32_t addr = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2258

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2259

uint32_t field = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

2343

uint32_t instance,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

258

uint32_t regval;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

289

uint32_t vsync_offset = dc_crtc_timing->v_border_bottom +

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

291

uint32_t v_sync_start = dc_crtc_timing->v_addressable + vsync_offset;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

293

uint32_t hsync_offset = dc_crtc_timing->h_border_right +

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

295

uint32_t h_sync_start = dc_crtc_timing->h_addressable + hsync_offset;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

370

uint32_t v_total_min = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

371

uint32_t v_total_max = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

372

uint32_t v_total_cntl = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

375

uint32_t addr = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

471

uint32_t event_triggers,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

472

uint32_t num_frames)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

475

uint32_t static_screen_cntl = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

476

uint32_t addr = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

512

uint32_t dce110_timing_generator_get_vblank_counter(struct timing_generator *tg)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

515

uint32_t addr = CRTC_REG(mmCRTC_STATUS_FRAME_COUNT);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

516

uint32_t value = dm_read_reg(tg->ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

517

uint32_t field = get_reg_field_value(

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

536

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

571

uint32_t *v_blank_start,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

572

uint32_t *v_blank_end,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

573

uint32_t *h_position,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

574

uint32_t *v_position)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

579

uint32_t value = dm_read_reg(tg->ctx,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

604

uint32_t vsync_offset = timing->v_border_bottom +

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

606

uint32_t v_sync_start = timing->v_addressable + vsync_offset;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

608

uint32_t hsync_offset = timing->h_border_right +

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

610

uint32_t h_sync_start = timing->h_addressable + hsync_offset;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

614

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

615

uint32_t addr = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

616

uint32_t tmp = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

712

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

713

uint32_t addr;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

719

uint32_t src_bpc = 16;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

721

uint32_t dst_bpc;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

722

uint32_t index;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

732

uint32_t inc_base;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

94

uint32_t addr = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

95

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c

96

uint32_t field = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

103

uint32_t max_h_total;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

104

uint32_t max_v_total;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

106

uint32_t min_h_blank;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

107

uint32_t min_h_front_porch;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

108

uint32_t min_h_back_porch;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

111

uint32_t min_h_sync_width;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

112

uint32_t min_v_sync_width;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

113

uint32_t min_v_blank;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

123

uint32_t instance,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

145

uint32_t early_cntl);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

150

uint32_t dce110_timing_generator_get_vblank_counter(

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

234

uint32_t event_triggers,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

235

uint32_t num_frames);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

239

uint32_t *v_blank_start,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

240

uint32_t *v_blank_end,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

241

uint32_t *h_position,

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

242

uint32_t *v_position);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.h

290

uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

101

uint32_t addr = mmCRTCV_BLANK_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

102

uint32_t value = dm_read_reg(tg->ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

121

uint32_t addr = mmCRTCV_BLANK_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

122

uint32_t value = dm_read_reg(tg->ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

142

uint32_t addr = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

143

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

144

uint32_t field = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

154

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

155

uint32_t h1 = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

156

uint32_t h2 = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

157

uint32_t v1 = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

158

uint32_t v2 = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

245

uint32_t vsync_offset = timing->v_border_bottom +

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

247

uint32_t v_sync_start = timing->v_addressable + vsync_offset;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

249

uint32_t hsync_offset = timing->h_border_right +

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

251

uint32_t h_sync_start = timing->h_addressable + hsync_offset;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

254

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

255

uint32_t addr = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

256

uint32_t tmp = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

388

uint32_t addr = mmCRTCV_START_LINE_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

389

uint32_t value = dm_read_reg(tg->ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

455

uint32_t addr = mmCRTCV_BLACK_COLOR;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

456

uint32_t value = dm_read_reg(tg->ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

482

uint32_t addr;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

483

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

526

uint32_t addr = mmCRTCV_BLACK_COLOR;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

527

uint32_t value = dm_read_reg(tg->ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

555

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

556

uint32_t addr;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

59

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

592

uint32_t early_cntl)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

594

uint32_t regval;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

595

uint32_t address = mmCRTC_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

603

static uint32_t dce110_timing_generator_v_get_vblank_counter(struct timing_generator *tg)

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

605

uint32_t addr = mmCRTCV_STATUS_FRAME_COUNT;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

606

uint32_t value = dm_read_reg(tg->ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

607

uint32_t field = get_reg_field_value(

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

82

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

163

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

231

uint32_t overscan_left_right = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

232

uint32_t overscan_top_bottom = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

275

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

294

uint32_t select = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

295

uint32_t power_ctl, power_ctl_off;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

324

uint32_t data = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

37

uint32_t h_int_scale_ratio_luma;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

38

uint32_t h_int_scale_ratio_chroma;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

39

uint32_t v_int_scale_ratio_luma;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

394

uint32_t addr = mmSCLV_HORZ_FILTER_SCALE_RATIO;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

395

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

40

uint32_t v_int_scale_ratio_chroma;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

506

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

633

uint32_t reg_data = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

83

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_transform_v.c

84

uint32_t addr = 0;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

105

static uint32_t lpt_memory_control_config(struct dce112_compressor *cp110,

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

106

uint32_t lpt_control)

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

270

uint32_t source_view_width,

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

271

uint32_t source_view_height)

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

283

static uint32_t align_to_chunks_number_per_line(

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

285

uint32_t pixels)

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

295

uint32_t addr = mmFBC_STATUS;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

296

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

318

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

319

uint32_t addr;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

364

uint32_t paths_num,

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

377

uint32_t addr;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

378

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

420

uint32_t reg_data;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

441

uint32_t *inst)

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

444

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

470

uint32_t value = dm_read_reg(compressor->ctx,

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

484

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

485

uint32_t fbc_pitch = 0;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

486

uint32_t compressed_surf_address_low_part =

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

498

uint32_t lpt_alignment = lpt_size_alignment(cp110);

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

543

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

544

uint32_t addr;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

545

uint32_t inx;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

597

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

598

uint32_t addr;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

599

uint32_t value_control;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

600

uint32_t channels;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

64

static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

658

uint32_t rows_per_channel;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

659

uint32_t lpt_alignment;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

660

uint32_t source_view_width;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

661

uint32_t source_view_height;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

662

uint32_t lpt_control = 0;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

732

uint32_t fbc_trigger)

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

737

uint32_t addr = mmFBC_CLIENT_REGION_MASK;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

738

uint32_t value = dm_read_reg(compressor->ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c

98

static uint32_t lpt_size_alignment(struct dce112_compressor *cp110)

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.h

34

uint32_t dcp_offset;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.h

35

uint32_t dmif_offset;

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.h

53

void dce112_compressor_enable_fbc(struct compressor *cp, uint32_t paths_num,

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.h

59

uint32_t fbc_trigger);

sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.h

66

uint32_t *fbc_mapped_crtc_id);

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

106

uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

1060

uint32_t v_blank_start, v_blank_end, h_position, v_position;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

107

uint32_t v_blank =

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

1084

uint32_t value, field;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

1175

uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

1178

uint32_t value, field;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

1258

uint32_t instance,

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

158

uint32_t early_cntl)

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

169

static uint32_t dce120_timing_generator_get_vblank_counter(

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

173

uint32_t value = dm_read_reg_soc15(

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

177

uint32_t field = get_reg_field_value(

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

189

uint32_t value = dm_read_reg_soc15(

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

250

uint32_t value_crtc_vtotal =

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

255

uint32_t check_point =

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

309

uint32_t rising_edge = 0;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

310

uint32_t falling_edge = 0;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

312

uint32_t pol_value = dm_read_reg_soc15(

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

374

uint32_t value = dm_read_reg_soc15(

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

389

uint32_t offset = 0;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

390

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

432

uint32_t tmp1 = 0;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

433

uint32_t tmp2 = 0;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

434

uint32_t vsync_offset = timing->v_border_bottom +

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

436

uint32_t v_sync_start = timing->v_addressable + vsync_offset;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

438

uint32_t hsync_offset = timing->h_border_right +

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

440

uint32_t h_sync_start = timing->h_addressable + hsync_offset;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

506

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

594

uint32_t *v_blank_start,

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

595

uint32_t *v_blank_end,

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

596

uint32_t *h_position,

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

597

uint32_t *v_position)

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

602

uint32_t v_blank_start_end = dm_read_reg_soc15(

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

627

uint32_t v_sync_width_and_b_porch =

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

630

uint32_t value = dm_read_reg_soc15(

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

663

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

713

uint32_t value = dm_read_reg_soc15(

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

780

uint32_t event_triggers,

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

781

uint32_t num_frames)

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

803

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

809

uint32_t src_bpc = 16;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

811

uint32_t dst_bpc;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

812

uint32_t index;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

822

uint32_t inc_base;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

88

uint32_t field = 0;

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c

90

uint32_t value = dm_read_reg_soc15(

sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.h

37

uint32_t instance,

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

130

uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

131

uint32_t value = dm_read_reg(tg->ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

133

uint32_t addr2 = CRTC_REG(mmCRTC_CONTROL);

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

134

uint32_t value2 = dm_read_reg(tg->ctx, addr2);

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

181

uint32_t addr = 0;

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

182

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

183

uint32_t field = 0;

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

248

uint32_t instance,

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

87

static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz)

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

90

uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c

92

uint32_t value = dm_read_reg(tg->ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.h

36

uint32_t instance,

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

130

uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

131

uint32_t value = dm_read_reg(tg->ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

230

uint32_t instance,

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

87

static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz)

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

90

uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c

92

uint32_t value = dm_read_reg(tg->ctx, addr);

sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.h

36

uint32_t instance,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

151

uint32_t hw_points_num,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

158

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

346

uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

46

uint32_t cur_csc_reg;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

510

uint32_t red_clamp = dc_fixpt_clamp_u0d14(rgb->delta_red);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

511

uint32_t green_clamp = dc_fixpt_clamp_u0d14(rgb->delta_green);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

512

uint32_t blue_clamp = dc_fixpt_clamp_u0d14(rgb->delta_blue);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

551

uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

69

uint32_t cur_csc_reg, regval0, regval1;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c

90

uint32_t reg_region_cur;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

105

uint32_t hw_points_num,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

42

uint32_t start_cntl_b; \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

43

uint32_t start_cntl_g; \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

44

uint32_t start_cntl_r; \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

45

uint32_t start_slope_cntl_b; \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

46

uint32_t start_slope_cntl_g; \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

47

uint32_t start_slope_cntl_r; \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

48

uint32_t start_end_cntl1_b; \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

49

uint32_t start_end_cntl2_b; \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

50

uint32_t start_end_cntl1_g; \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

51

uint32_t start_end_cntl2_g; \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

52

uint32_t start_end_cntl1_r; \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

53

uint32_t start_end_cntl2_r; \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

54

uint32_t region_start; \

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

55

uint32_t region_end

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

66

TF_HELPER_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

81

TF_CM_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

88

uint32_t csc_c11_c12;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h

89

uint32_t csc_c33_c34;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

215

uint32_t WB_ENABLE;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

216

uint32_t WB_EC_CONFIG;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

217

uint32_t CNV_MODE;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

218

uint32_t WB_SOFT_RESET;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

219

uint32_t MCIF_WB_BUFMGR_SW_CONTROL;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

220

uint32_t MCIF_WB_BUF_PITCH;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

221

uint32_t MCIF_WB_ARBITRATION_CONTROL;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

222

uint32_t MCIF_WB_SCLK_CHANGE;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

223

uint32_t MCIF_WB_BUF_1_ADDR_Y;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

224

uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

225

uint32_t MCIF_WB_BUF_1_ADDR_C;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

226

uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

227

uint32_t MCIF_WB_BUF_2_ADDR_Y;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

228

uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

229

uint32_t MCIF_WB_BUF_2_ADDR_C;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

230

uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

231

uint32_t MCIF_WB_BUF_3_ADDR_Y;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

232

uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

233

uint32_t MCIF_WB_BUF_3_ADDR_C;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

234

uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

235

uint32_t MCIF_WB_BUF_4_ADDR_Y;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

236

uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

237

uint32_t MCIF_WB_BUF_4_ADDR_C;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

238

uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

239

uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

240

uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

241

uint32_t MCIF_WB_NB_PSTATE_CONTROL;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

242

uint32_t MCIF_WB_WATERMARK;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

243

uint32_t MCIF_WB_WARM_UP_CNTL;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

244

uint32_t MCIF_WB_BUF_LUMA_SIZE;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

245

uint32_t MCIF_WB_BUF_CHROMA_SIZE;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h

248

DWBC_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

119

const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

81

const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

179

IPP_DCN10_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

183

uint32_t CURSOR_SETTINS;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

184

uint32_t CURSOR_SETTINGS;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

185

uint32_t CNVC_SURFACE_PIXEL_FORMAT;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

186

uint32_t CURSOR0_CONTROL;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

187

uint32_t CURSOR0_COLOR0;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

188

uint32_t CURSOR0_COLOR1;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

189

uint32_t FORMAT_CONTROL;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

190

uint32_t CURSOR_SURFACE_ADDRESS_HIGH;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

191

uint32_t CURSOR_SURFACE_ADDRESS;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

192

uint32_t CURSOR_SIZE;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

193

uint32_t CURSOR_CONTROL;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

194

uint32_t CURSOR_POSITION;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

195

uint32_t CURSOR_HOT_SPOT;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.h

196

uint32_t CURSOR_DST_OFFSET;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c

305

uint32_t wbscl_mode = REG_READ(WBSCL_MODE);

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

331

uint32_t WB_ENABLE;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

332

uint32_t WB_EC_CONFIG;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

333

uint32_t CNV_MODE;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

334

uint32_t CNV_WINDOW_START;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

335

uint32_t CNV_WINDOW_SIZE;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

336

uint32_t CNV_UPDATE;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

337

uint32_t CNV_SOURCE_SIZE;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

338

uint32_t CNV_TEST_CNTL;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

339

uint32_t CNV_TEST_CRC_RED;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

340

uint32_t CNV_TEST_CRC_GREEN;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

341

uint32_t CNV_TEST_CRC_BLUE;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

342

uint32_t WB_DEBUG_CTRL;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

343

uint32_t WB_DBG_MODE;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

344

uint32_t WB_HW_DEBUG;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

345

uint32_t CNV_TEST_DEBUG_INDEX;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

346

uint32_t CNV_TEST_DEBUG_DATA;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

347

uint32_t WB_SOFT_RESET;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

348

uint32_t WBSCL_COEF_RAM_SELECT;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

349

uint32_t WBSCL_COEF_RAM_TAP_DATA;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

350

uint32_t WBSCL_MODE;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

351

uint32_t WBSCL_TAP_CONTROL;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

352

uint32_t WBSCL_DEST_SIZE;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

353

uint32_t WBSCL_HORZ_FILTER_SCALE_RATIO;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

354

uint32_t WBSCL_HORZ_FILTER_INIT_Y_RGB;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

355

uint32_t WBSCL_HORZ_FILTER_INIT_CBCR;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

356

uint32_t WBSCL_VERT_FILTER_SCALE_RATIO;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

357

uint32_t WBSCL_VERT_FILTER_INIT_Y_RGB;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

358

uint32_t WBSCL_VERT_FILTER_INIT_CBCR;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

359

uint32_t WBSCL_ROUND_OFFSET;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

360

uint32_t WBSCL_OVERFLOW_STATUS;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

361

uint32_t WBSCL_COEF_RAM_CONFLICT_STATUS;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

362

uint32_t WBSCL_TEST_CNTL;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

363

uint32_t WBSCL_TEST_CRC_RED;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

364

uint32_t WBSCL_TEST_CRC_GREEN;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

365

uint32_t WBSCL_TEST_CRC_BLUE;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

366

uint32_t WBSCL_BACKPRESSURE_CNT_EN;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

367

uint32_t WB_MCIF_BACKPRESSURE_CNT;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

368

uint32_t WBSCL_CLAMP_Y_RGB;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

369

uint32_t WBSCL_CLAMP_CBCR;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

370

uint32_t WBSCL_OUTSIDE_PIX_STRATEGY;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

371

uint32_t WBSCL_OUTSIDE_PIX_STRATEGY_CBCR;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

372

uint32_t WBSCL_DEBUG;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

373

uint32_t WBSCL_TEST_DEBUG_INDEX;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

374

uint32_t WBSCL_TEST_DEBUG_DATA;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

375

uint32_t WB_WARM_UP_MODE_CTL1;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

376

uint32_t WB_WARM_UP_MODE_CTL2;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

381

DWBC_REG_FIELD_LIST_DCN2_0(uint32_t)

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

418

uint32_t src_height,

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

419

uint32_t dest_height,

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

424

uint32_t src_width,

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h

425

uint32_t dest_width,

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

684

uint32_t taps,

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

723

uint32_t src_width,

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

724

uint32_t dest_width,

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

727

uint32_t h_ratio_luma = 1;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

728

uint32_t h_taps_luma = num_taps.h_taps;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

729

uint32_t h_taps_chroma = num_taps.h_taps_c;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

732

uint32_t h_init_phase_luma_int = 0;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

733

uint32_t h_init_phase_luma_frac = 0;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

734

uint32_t h_init_phase_chroma_int = 0;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

735

uint32_t h_init_phase_chroma_frac = 0;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

801

uint32_t src_height,

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

802

uint32_t dest_height,

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

806

uint32_t v_ratio_luma = 1;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

807

uint32_t v_taps_luma = num_taps.v_taps;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

808

uint32_t v_taps_chroma = num_taps.v_taps_c;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

811

uint32_t v_init_phase_luma_int = 0;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

812

uint32_t v_init_phase_luma_frac = 0;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

813

uint32_t v_init_phase_chroma_int = 0;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

814

uint32_t v_init_phase_chroma_frac = 0;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.c

59

uint32_t entry_lo32;

sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.h

65

DCN20_VMID_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.c

55

uint32_t value1, value2;

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.c

70

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.h

67

MPC_REG_FIELD_LIST_DCN201(uint32_t)

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_opp.c

62

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_opp.h

51

OPP_DCN201_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_opp.h

68

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c

126

uint32_t channels = 0;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c

202

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

165

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

45

uint32_t AFMT_INFOFRAME_CONTROL0;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

46

uint32_t AFMT_VBI_PACKET_CONTROL;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

47

uint32_t AFMT_AUDIO_PACKET_CONTROL;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

48

uint32_t AFMT_AUDIO_PACKET_CONTROL2;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

49

uint32_t AFMT_AUDIO_SRC_CONTROL;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

50

uint32_t AFMT_60958_0;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

51

uint32_t AFMT_60958_1;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

52

uint32_t AFMT_60958_2;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

53

uint32_t AFMT_MEM_PWR;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.h

99

AFMT_DCN3_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

123

uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

257

uint32_t red_clamp;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

258

uint32_t green_clamp;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

259

uint32_t blue_clamp;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

307

uint32_t hw_points_num,

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

314

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

462

bool is_rgb_equal(const struct pwl_result_data *rgb, uint32_t num)

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

464

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c

48

uint32_t reg_region_cur;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

413

uint32_t MMHUBBUB_MEM_PWR_CNTL;\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

414

uint32_t MMHUBBUB_WARMUP_ADDR_REGION;\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

415

uint32_t MMHUBBUB_WARMUP_BASE_ADDR_HIGH;\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

416

uint32_t MMHUBBUB_WARMUP_BASE_ADDR_LOW;\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

417

uint32_t MMHUBBUB_WARMUP_CONTROL_STATUS;\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

418

uint32_t MMHUBBUB_WARMUP_P_VMID;\

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

419

uint32_t MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h

427

MCIF_WB_REG_FIELD_LIST_DCN3_0(uint32_t);

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.c

100

(const uint32_t *) &info_packet->sb[0];

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.c

251

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.c

48

uint32_t packet_index,

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.c

53

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.c

58

uint32_t max_retries = 50;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.c

99

const uint32_t *content =

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.h

133

VPG_DCN3_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.h

145

uint32_t packet_index,

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.h

151

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.h

42

uint32_t VPG_GENERIC_STATUS;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.h

43

uint32_t VPG_GENERIC_PACKET_ACCESS_CTRL;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.h

44

uint32_t VPG_GENERIC_PACKET_DATA;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.h

45

uint32_t VPG_GSP_FRAME_UPDATE_CTRL;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.h

46

uint32_t VPG_GSP_IMMEDIATE_UPDATE_CTRL;

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

100

uint32_t current_backlight;

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

161

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

171

uint32_t pwr_seq_state, dig_on, dig_on_ovrd;

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

51

uint32_t round_result;

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

52

uint32_t bl_period, bl_int_count;

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

53

uint32_t bl_pwm, fractional_duty_cycle_en;

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

54

uint32_t bl_period_mask, bl_pwm_mask;

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

86

round_result = (uint32_t)(current_backlight & 0xFFFFFFFF);

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

93

return (uint32_t)(current_backlight);

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

96

static uint32_t dcn301_panel_cntl_hw_init(struct panel_cntl *panel_cntl)

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

99

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h

80

DCN301_PANEL_CNTL_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.c

79

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

103

AFMT_DCN31_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

121

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

45

uint32_t AFMT_INFOFRAME_CONTROL0;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

46

uint32_t AFMT_VBI_PACKET_CONTROL;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

47

uint32_t AFMT_AUDIO_PACKET_CONTROL;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

48

uint32_t AFMT_AUDIO_PACKET_CONTROL2;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

49

uint32_t AFMT_AUDIO_SRC_CONTROL;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

50

uint32_t AFMT_60958_0;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

51

uint32_t AFMT_60958_1;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

52

uint32_t AFMT_60958_2;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.h

53

uint32_t AFMT_MEM_PWR;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.c

106

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.h

105

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.h

40

uint32_t APG_CONTROL;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.h

41

uint32_t APG_CONTROL2;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.h

42

uint32_t APG_MEM_PWR;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.h

43

uint32_t APG_DBG_GEN_CONTROL;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.h

68

APG_DCN31_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

101

uint32_t xtal = panel_cntl->ctx->dc->res_pool->ref_clocks.dccg_ref_clock_inKhz;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

58

static uint32_t dcn31_get_16_bit_backlight_from_pwm(struct panel_cntl *panel_cntl)

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

68

static uint32_t dcn31_panel_cntl_hw_init(struct panel_cntl *panel_cntl)

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

73

uint32_t freq_to_set = panel_cntl->ctx->dc->debug.pwm_freq;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.c

66

uint32_t vpg_gsp_mem_pwr_state;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.c

79

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.h

140

VPG_DCN31_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.h

158

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.h

43

uint32_t VPG_GENERIC_STATUS;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.h

44

uint32_t VPG_GENERIC_PACKET_ACCESS_CTRL;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.h

45

uint32_t VPG_GENERIC_PACKET_DATA;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.h

46

uint32_t VPG_GSP_FRAME_UPDATE_CTRL;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.h

47

uint32_t VPG_GSP_IMMEDIATE_UPDATE_CTRL;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.h

48

uint32_t VPG_MEM_PWR;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1208

uint32_t *src,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1209

uint32_t *slots)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1228

uint32_t value1 = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1229

uint32_t value2 = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1230

uint32_t slots = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1231

uint32_t src = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1232

uint32_t retries = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1350

uint32_t field;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1434

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

208

uint32_t index)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

231

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

535

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

569

uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

923

uint32_t pixel_clock)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

960

uint32_t pixel_clock)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

100

uint32_t DP_MSE_SAT1;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

101

uint32_t DP_MSE_SAT2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

102

uint32_t DP_MSE_SAT_UPDATE;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

103

uint32_t DP_SEC_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

104

uint32_t DP_VID_STREAM_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

105

uint32_t DP_DPHY_FAST_TRAINING;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

106

uint32_t DP_DPHY_BS_SR_SWAP_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

107

uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

108

uint32_t DP_SEC_CNTL1;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

109

uint32_t TMDS_CTL_BITS;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

111

uint32_t CLOCK_ENABLE;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

113

uint32_t DIG_LANE_ENABLE;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

115

uint32_t CHANNEL_XBAR_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

117

uint32_t RDPCSTX_PHY_CNTL3;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

118

uint32_t RDPCSTX_PHY_CNTL4;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

119

uint32_t RDPCSTX_PHY_CNTL5;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

120

uint32_t RDPCSTX_PHY_CNTL6;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

121

uint32_t RDPCSPIPE_PHY_CNTL6;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

122

uint32_t RDPCSTX_PHY_CNTL7;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

123

uint32_t RDPCSTX_PHY_CNTL8;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

124

uint32_t RDPCSTX_PHY_CNTL9;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

125

uint32_t RDPCSTX_PHY_CNTL10;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

126

uint32_t RDPCSTX_PHY_CNTL11;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

127

uint32_t RDPCSTX_PHY_CNTL12;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

128

uint32_t RDPCSTX_PHY_CNTL13;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

129

uint32_t RDPCSTX_PHY_CNTL14;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

130

uint32_t RDPCSTX_PHY_CNTL15;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

131

uint32_t RDPCSTX_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

132

uint32_t RDPCSTX_CLOCK_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

133

uint32_t RDPCSTX_PHY_CNTL0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

134

uint32_t RDPCSTX_PHY_CNTL2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

135

uint32_t RDPCSTX_PLL_UPDATE_DATA;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

136

uint32_t RDPCS_TX_CR_ADDR;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

137

uint32_t RDPCS_TX_CR_DATA;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

138

uint32_t DPCSTX_TX_CLOCK_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

139

uint32_t DPCSTX_TX_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

140

uint32_t RDPCSTX_INTERRUPT_CONTROL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

141

uint32_t RDPCSTX_PHY_FUSE0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

142

uint32_t RDPCSTX_PHY_FUSE1;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

143

uint32_t RDPCSTX_PHY_FUSE2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

144

uint32_t RDPCSTX_PHY_FUSE3;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

145

uint32_t RDPCSTX_PHY_RX_LD_VAL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

146

uint32_t DPCSTX_DEBUG_CONFIG;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

147

uint32_t RDPCSTX_DEBUG_CONFIG;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

148

uint32_t RDPCSTX0_RDPCSTX_SCRATCH;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

149

uint32_t RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

150

uint32_t DCIO_SOFT_RESET;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

152

uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

153

uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

154

uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

155

uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

156

uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

157

uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

158

uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

159

uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

160

uint32_t TMDS_DCBALANCER_CONTROL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

161

uint32_t PHYA_LINK_CNTL2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

162

uint32_t PHYB_LINK_CNTL2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

163

uint32_t PHYC_LINK_CNTL2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

164

uint32_t DIO_LINKA_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

165

uint32_t DIO_LINKB_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

166

uint32_t DIO_LINKC_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

167

uint32_t DIO_LINKD_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

168

uint32_t DIO_LINKE_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

169

uint32_t DIO_LINKF_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

170

uint32_t DIO_CLK_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

171

uint32_t DIG_BE_CLK_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

515

DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

516

DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

517

DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

518

DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

519

DCN35_LINK_ENCODER_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

588

uint32_t pixel_clock);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

595

uint32_t pixel_clock);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

636

uint32_t index);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

74

uint32_t AUX_CONTROL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

75

uint32_t AUX_DPHY_RX_CONTROL0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

76

uint32_t AUX_DPHY_TX_CONTROL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

77

uint32_t AUX_DPHY_RX_CONTROL1;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

81

uint32_t DC_HPD_CONTROL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

85

uint32_t DIG_BE_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

86

uint32_t DIG_BE_EN_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

87

uint32_t DIG_CLOCK_PATTERN;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

88

uint32_t DP_CONFIG;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

89

uint32_t DP_DPHY_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

90

uint32_t DP_DPHY_INTERNAL_CTRL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

91

uint32_t DP_DPHY_PRBS_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

92

uint32_t DP_DPHY_SCRAM_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

93

uint32_t DP_DPHY_SYM0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

94

uint32_t DP_DPHY_SYM1;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

95

uint32_t DP_DPHY_SYM2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

96

uint32_t DP_DPHY_TRAINING_PATTERN_SEL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

97

uint32_t DP_LINK_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

98

uint32_t DP_LINK_FRAMING_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

99

uint32_t DP_MSE_SAT0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

107

const uint32_t *content =

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

108

(const uint32_t *) &info_packet->sb[0];

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1165

uint32_t crtc_pixel_clock_100Hz,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1166

uint32_t actual_pixel_clock_100Hz,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1170

uint32_t index;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1171

uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1172

uint32_t audio_array_size;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1231

uint32_t channels = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1408

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1501

uint32_t tg_inst = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1514

uint32_t hw_encoding = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1515

uint32_t hw_depth = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

160

uint32_t packet_index,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

163

uint32_t cont, send, line;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

250

uint32_t enable_sdp_splitting)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

252

uint32_t h_active_start;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

253

uint32_t v_active_start;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

254

uint32_t misc0 = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

255

uint32_t misc1 = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

256

uint32_t h_blank;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

257

uint32_t h_back_porch;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

59

uint32_t packet_index,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

630

uint32_t x = dc_fixpt_floor(

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

632

uint32_t y = dc_fixpt_ceil(

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

65

uint32_t max_retries = 50;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

721

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

787

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

792

uint32_t max_retries = 50;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

835

const uint32_t *content =

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

836

(const uint32_t *) &custom_sdp_message[4];

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

880

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

908

uint32_t reg1 = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

909

uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

966

uint32_t n_vid = 0x8000;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

967

uint32_t m_vid;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

968

uint32_t n_multiply = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

985

m_vid = (uint32_t) m_vid_l;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

106

uint32_t AFMT_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

107

uint32_t AFMT_AVI_INFO0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

108

uint32_t AFMT_AVI_INFO1;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

109

uint32_t AFMT_AVI_INFO2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

110

uint32_t AFMT_AVI_INFO3;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

111

uint32_t AFMT_GENERIC_0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

112

uint32_t AFMT_GENERIC_1;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

113

uint32_t AFMT_GENERIC_2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

114

uint32_t AFMT_GENERIC_3;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

115

uint32_t AFMT_GENERIC_4;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

116

uint32_t AFMT_GENERIC_5;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

117

uint32_t AFMT_GENERIC_6;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

118

uint32_t AFMT_GENERIC_7;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

119

uint32_t AFMT_GENERIC_HDR;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

120

uint32_t AFMT_INFOFRAME_CONTROL0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

121

uint32_t AFMT_VBI_PACKET_CONTROL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

122

uint32_t AFMT_VBI_PACKET_CONTROL1;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

123

uint32_t AFMT_AUDIO_PACKET_CONTROL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

124

uint32_t AFMT_AUDIO_PACKET_CONTROL2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

125

uint32_t AFMT_AUDIO_SRC_CONTROL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

126

uint32_t AFMT_60958_0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

127

uint32_t AFMT_60958_1;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

128

uint32_t AFMT_60958_2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

129

uint32_t DIG_FE_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

130

uint32_t DIG_FIFO_STATUS;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

131

uint32_t DP_MSE_RATE_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

132

uint32_t DP_MSE_RATE_UPDATE;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

133

uint32_t DP_PIXEL_FORMAT;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

134

uint32_t DP_SEC_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

135

uint32_t DP_SEC_CNTL1;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

136

uint32_t DP_SEC_CNTL2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

137

uint32_t DP_SEC_CNTL5;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

138

uint32_t DP_SEC_CNTL6;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

139

uint32_t DP_STEER_FIFO;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

140

uint32_t DP_VID_M;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

141

uint32_t DP_VID_N;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

142

uint32_t DP_VID_STREAM_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

143

uint32_t DP_VID_TIMING;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

144

uint32_t DP_SEC_AUD_N;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

145

uint32_t DP_SEC_AUD_N_READBACK;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

146

uint32_t DP_SEC_AUD_M_READBACK;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

147

uint32_t DP_SEC_TIMESTAMP;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

148

uint32_t HDMI_CONTROL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

149

uint32_t HDMI_GC;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

150

uint32_t HDMI_GENERIC_PACKET_CONTROL0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

151

uint32_t HDMI_GENERIC_PACKET_CONTROL1;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

152

uint32_t HDMI_GENERIC_PACKET_CONTROL2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

153

uint32_t HDMI_GENERIC_PACKET_CONTROL3;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

154

uint32_t HDMI_GENERIC_PACKET_CONTROL4;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

155

uint32_t HDMI_GENERIC_PACKET_CONTROL5;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

156

uint32_t HDMI_INFOFRAME_CONTROL0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

157

uint32_t HDMI_INFOFRAME_CONTROL1;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

158

uint32_t HDMI_VBI_PACKET_CONTROL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

159

uint32_t HDMI_AUDIO_PACKET_CONTROL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

160

uint32_t HDMI_ACR_PACKET_CONTROL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

161

uint32_t HDMI_ACR_32_0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

162

uint32_t HDMI_ACR_32_1;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

163

uint32_t HDMI_ACR_44_0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

164

uint32_t HDMI_ACR_44_1;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

165

uint32_t HDMI_ACR_48_0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

166

uint32_t HDMI_ACR_48_1;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

167

uint32_t DP_DB_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

168

uint32_t DP_MSA_MISC;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

169

uint32_t DP_MSA_VBID_MISC;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

170

uint32_t DP_MSA_COLORIMETRY;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

171

uint32_t DP_MSA_TIMING_PARAM1;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

172

uint32_t DP_MSA_TIMING_PARAM2;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

173

uint32_t DP_MSA_TIMING_PARAM3;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

174

uint32_t DP_MSA_TIMING_PARAM4;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

175

uint32_t HDMI_DB_CONTROL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

176

uint32_t DP_DSC_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

177

uint32_t DP_DSC_BYTES_PER_PIXEL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

178

uint32_t DME_CONTROL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

179

uint32_t DP_SEC_METADATA_TRANSMISSION;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

180

uint32_t HDMI_METADATA_PACKET_CONTROL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

181

uint32_t DP_SEC_FRAMING4;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

182

uint32_t DP_GSP11_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

183

uint32_t HDMI_GENERIC_PACKET_CONTROL6;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

184

uint32_t HDMI_GENERIC_PACKET_CONTROL7;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

185

uint32_t HDMI_GENERIC_PACKET_CONTROL8;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

186

uint32_t HDMI_GENERIC_PACKET_CONTROL9;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

187

uint32_t HDMI_GENERIC_PACKET_CONTROL10;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

188

uint32_t DIG_CLOCK_PATTERN;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

189

uint32_t DIG_FIFO_CTRL0;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

190

uint32_t DIG_FE_CLK_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

191

uint32_t DIG_FE_EN_CNTL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

192

uint32_t STREAM_MAPPER_CONTROL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

608

SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

612

SE_REG_FIELD_LIST_DCN1_0(uint32_t);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

613

uint32_t HDMI_ACP_SEND;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

614

SE_REG_FIELD_LIST_DCN2_0(uint32_t);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

615

SE_REG_FIELD_LIST_DCN3_0(uint32_t);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

616

SE_REG_FIELD_LIST_DCN3_1_COMMON(uint32_t);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

617

SE_REG_FIELD_LIST_DCN3_5_COMMON(uint32_t);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

618

SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

639

uint32_t packet_index,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

647

uint32_t enable_sdp_splitting);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

737

uint32_t crtc_pixel_clock_100Hz,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

738

uint32_t actual_pixel_clock_100Hz,

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

190

uint32_t active = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

272

uint32_t is_in_usb_c_dp4_mode = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

288

uint32_t dp_alt_mode_disable = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

250

uint32_t mpllb_ana_v2i;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

251

uint32_t mpllb_ana_freq_vco;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

252

uint32_t mpllb_ana_cp_int;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

253

uint32_t mpllb_ana_cp_prop;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

254

uint32_t mpllb_multiplier;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

255

uint32_t ref_clk_mpllb_div;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

262

uint32_t mpllb_div_multiplier;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

263

uint32_t mpllb_tx_clk_div;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

264

uint32_t mpllb_fracn_quot;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

265

uint32_t mpllb_fracn_den;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

266

uint32_t mpllb_ssc_peak;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

267

uint32_t mpllb_ssc_stepsize;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

268

uint32_t mpllb_ssc_up_spread;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

269

uint32_t mpllb_fracn_rem;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

270

uint32_t mpllb_hdmi_div;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

272

uint32_t tx_vboost_lvl;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

273

uint32_t hdmi_pixel_clk_div;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

274

uint32_t ref_range;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

275

uint32_t ref_clk;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

282

uint32_t tx_peaking_lvl;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

283

uint32_t ctr_reqs_pll;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

299

uint32_t dp_tx0_term_ctrl;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

300

uint32_t dp_tx1_term_ctrl;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

301

uint32_t dp_tx2_term_ctrl;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

302

uint32_t dp_tx3_term_ctrl;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

303

uint32_t fw_data[0x1000];

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

304

uint32_t dp_tx0_width;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

305

uint32_t dp_tx1_width;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

306

uint32_t dp_tx2_width;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

307

uint32_t dp_tx3_width;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

308

uint32_t dp_tx0_rate;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

309

uint32_t dp_tx1_rate;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

310

uint32_t dp_tx2_rate;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

311

uint32_t dp_tx3_rate;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

312

uint32_t dp_tx0_eq_main;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

313

uint32_t dp_tx0_eq_pre;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

314

uint32_t dp_tx0_eq_post;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

315

uint32_t dp_tx1_eq_main;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

316

uint32_t dp_tx1_eq_pre;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

317

uint32_t dp_tx1_eq_post;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

318

uint32_t dp_tx2_eq_main;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

319

uint32_t dp_tx2_eq_pre;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

320

uint32_t dp_tx2_eq_post;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

321

uint32_t dp_tx3_eq_main;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

322

uint32_t dp_tx3_eq_pre;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

323

uint32_t dp_tx3_eq_post;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

326

uint32_t ldpcs_fifo_start_delay;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

327

uint32_t rdpcs_fifo_start_delay;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

217

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

222

uint32_t max_retries = 50;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

223

const uint32_t *content = (const uint32_t *) &info_packet->sb[0];

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

257

uint32_t packet_index = 7 + i;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

282

uint32_t dsc_bytes_per_pixel,

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

283

uint32_t dsc_slice_width)

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

379

uint32_t hubp_requestor_id,

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

447

uint32_t dmdata_packet_enabled = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

476

uint32_t n_vid = 0x8000;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

477

uint32_t m_vid;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

478

uint32_t n_multiply = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

495

m_vid = (uint32_t) m_vid_l;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

52

uint32_t packet_index,

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

55

uint32_t cont, send, line;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

567

uint32_t enable_sdp_splitting)

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

581

uint32_t enc2_get_fifo_cal_average_level(

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

585

uint32_t fifo_level;

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h

104

uint32_t enable_sdp_splitting);

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h

113

uint32_t hubp_requestor_id,

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h

116

uint32_t enc2_get_fifo_cal_average_level(

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

305

uint32_t dsc_bytes_per_pixel,

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

306

uint32_t dsc_slice_width)

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

426

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

427

uint32_t dmdata_packet_enabled = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

52

uint32_t packet_index,

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

55

uint32_t cont, send, line;

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

328

uint32_t packet_index,

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

137

uint32_t hpo_inst)

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

596

uint32_t dp_alt_mode_disable;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

640

uint32_t is_in_usb_c_dp4_mode = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h

254

uint32_t hpo_inst);

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

305

uint32_t n_vid = 0x8000;

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

306

uint32_t m_vid;

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

307

uint32_t n_multiply = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

308

uint32_t pix_per_cycle = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

326

m_vid = (uint32_t) m_vid_l;

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

394

uint32_t dsc_bytes_per_pixel,

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

395

uint32_t dsc_slice_width)

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

55

uint32_t reset_val = reset ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

56

uint32_t is_symclk_on;

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

89

uint32_t reset_val;

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

352

uint32_t dsc_bytes_per_pixel,

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

353

uint32_t dsc_slice_width);

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

252

uint32_t n_vid = 0x8000;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

253

uint32_t m_vid;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

254

uint32_t n_multiply = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

255

uint32_t pix_per_cycle = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

274

m_vid = (uint32_t) m_vid_l;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

356

uint32_t dsc_bytes_per_pixel,

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

357

uint32_t dsc_slice_width)

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

397

uint32_t reset_val = reset ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

398

uint32_t is_symclk_on;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

58

uint32_t enabled;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

68

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

284

uint32_t n_vid = 0x8000;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

285

uint32_t m_vid;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

286

uint32_t n_multiply = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

287

uint32_t pix_per_cycle = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

306

m_vid = (uint32_t) m_vid_l;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

369

uint32_t stream_enc_inst,

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

370

uint32_t link_enc_inst)

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

382

uint32_t reset_val = reset ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

383

uint32_t is_symclk_on;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

397

uint32_t reset_val;

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

425

static uint32_t enc35_get_pixels_per_cycle(struct stream_encoder *enc)

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

428

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

159

uint32_t clk_enabled;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

160

uint32_t dig_enabled;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

172

uint32_t value;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

271

uint32_t n_vid = 0x8000;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

272

uint32_t m_vid;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

273

uint32_t pix_per_container = 1;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

289

m_vid = (uint32_t) m_vid_l;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

442

uint32_t enable_sdp_splitting)

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

444

uint32_t h_active_start;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

445

uint32_t v_active_start;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

446

uint32_t misc0 = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

447

uint32_t misc1 = 0;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

448

uint32_t h_blank;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

449

uint32_t h_back_porch;

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

710

uint32_t stream_enc_inst,

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

711

uint32_t link_enc_inst)

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

797

uint32_t hubp_requestor_id,

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h

206

uint32_t hubp_requestor_id,

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h

216

uint32_t enable_sdp_splitting);

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h

232

uint32_t stream_enc_inst,

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h

233

uint32_t link_enc_inst);

sys/dev/pci/drm/amd/display/dc/dm_helpers.h

137

uint32_t address,

sys/dev/pci/drm/amd/display/dc/dm_helpers.h

139

uint32_t size);

sys/dev/pci/drm/amd/display/dc/dm_helpers.h

147

uint32_t address,

sys/dev/pci/drm/amd/display/dc/dm_helpers.h

149

uint32_t size);

sys/dev/pci/drm/amd/display/dc/dm_helpers.h

161

uint32_t timeout_us

sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h

254

uint32_t Freq; // In MHz

sys/dev/pci/drm/amd/display/dc/dm_pp_smu.h

255

uint32_t Vol; // Millivolts with 2 fractional bits

sys/dev/pci/drm/amd/display/dc/dm_services.h

102

static inline uint32_t set_reg_field_value_ex(

sys/dev/pci/drm/amd/display/dc/dm_services.h

103

uint32_t reg_value,

sys/dev/pci/drm/amd/display/dc/dm_services.h

104

uint32_t value,

sys/dev/pci/drm/amd/display/dc/dm_services.h

105

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/dm_services.h

119

uint32_t generic_reg_set_ex(const struct dc_context *ctx,

sys/dev/pci/drm/amd/display/dc/dm_services.h

120

uint32_t addr, uint32_t reg_val, int n,

sys/dev/pci/drm/amd/display/dc/dm_services.h

121

uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);

sys/dev/pci/drm/amd/display/dc/dm_services.h

123

uint32_t generic_reg_update_ex(const struct dc_context *ctx,

sys/dev/pci/drm/amd/display/dc/dm_services.h

124

uint32_t addr, int n,

sys/dev/pci/drm/amd/display/dc/dm_services.h

125

uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);

sys/dev/pci/drm/amd/display/dc/dm_services.h

142

uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value,

sys/dev/pci/drm/amd/display/dc/dm_services.h

280

void dm_trace_smu_enter(uint32_t msg_id, uint32_t param_in, unsigned int delay, struct dc_context *ctx);

sys/dev/pci/drm/amd/display/dc/dm_services.h

281

void dm_trace_smu_exit(bool success, uint32_t response, struct dc_context *ctx);

sys/dev/pci/drm/amd/display/dc/dm_services.h

56

uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,

sys/dev/pci/drm/amd/display/dc/dm_services.h

62

void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,

sys/dev/pci/drm/amd/display/dc/dm_services.h

63

uint32_t value, const char *func_name);

sys/dev/pci/drm/amd/display/dc/dm_services.h

71

static inline uint32_t dm_read_index_reg(

sys/dev/pci/drm/amd/display/dc/dm_services.h

74

uint32_t index)

sys/dev/pci/drm/amd/display/dc/dm_services.h

82

uint32_t index,

sys/dev/pci/drm/amd/display/dc/dm_services.h

83

uint32_t value)

sys/dev/pci/drm/amd/display/dc/dm_services.h

88

static inline uint32_t get_reg_field_value_ex(

sys/dev/pci/drm/amd/display/dc/dm_services.h

89

uint32_t reg_value,

sys/dev/pci/drm/amd/display/dc/dm_services.h

90

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

103

uint32_t clocks_in_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

104

uint32_t latency_in_us;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

108

uint32_t num_levels;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

113

uint32_t clocks_in_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

114

uint32_t voltage_in_mv;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

118

uint32_t num_levels;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

127

uint32_t src_height;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

128

uint32_t src_width;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

129

uint32_t v_refresh;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

130

uint32_t pixel_clock; /* Pixel clock in KHz (for HDMI only: normalized) */

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

146

uint32_t wm_min_eng_clk_in_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

147

uint32_t wm_max_eng_clk_in_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

148

uint32_t wm_min_mem_clk_in_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

149

uint32_t wm_max_mem_clk_in_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

153

uint32_t num_wm_sets;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

159

uint32_t wm_min_dcfclk_clk_in_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

160

uint32_t wm_max_dcfclk_clk_in_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

161

uint32_t wm_min_mem_clk_in_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

162

uint32_t wm_max_mem_clk_in_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

167

uint32_t wm_min_socclk_clk_in_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

168

uint32_t wm_max_socclk_clk_in_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

169

uint32_t wm_min_mem_clk_in_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

170

uint32_t wm_max_mem_clk_in_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

174

uint32_t num_wm_dmif_sets;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

175

uint32_t num_wm_mcif_sets;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

188

uint32_t cpu_pstate_separation_time;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

190

uint32_t min_memory_clock_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

191

uint32_t min_engine_clock_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

192

uint32_t min_engine_clock_deep_sleep_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

194

uint32_t avail_mclk_switch_time_us;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

195

uint32_t avail_mclk_switch_time_in_disp_active_us;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

196

uint32_t min_dcfclock_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

197

uint32_t min_dcfc_deep_sleep_clock_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

199

uint32_t disp_clk_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

210

uint32_t line_time_in_us;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

255

uint32_t clocks_in_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

259

uint32_t max_sclk_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

260

uint32_t max_mclk_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

267

uint32_t disp_clk_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

268

uint32_t min_engine_clock_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

269

uint32_t min_memory_clock_khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

287

uint32_t phy_id;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

289

uint32_t sym_clock_10khz;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

293

uint32_t transition_bitmask;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

298

uint32_t phy_id;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

299

uint32_t transition_id;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

300

uint32_t phy_configuration;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

301

uint32_t data_rate;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

98

uint32_t num_levels;

sys/dev/pci/drm/amd/display/dc/dm_services_types.h

99

uint32_t clocks_in_khz[DM_PP_MAX_CLOCK_LEVELS];

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1110

uint32_t asic_blank_end = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1111

uint32_t asic_blank_start = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1112

uint32_t newVstartup = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2159

uint32_t pipe_cnt;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

490

uint32_t cstate_enter_plus_exit_z8_ns;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1007

if ((uint32_t)refresh_rate < min_refresh)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1008

min_refresh = (uint32_t)refresh_rate;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1009

if ((uint32_t)refresh_rate > max_refresh)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1010

max_refresh = (uint32_t)refresh_rate;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1043

uint32_t i, pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1616

uint32_t asic_blank_end = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1617

uint32_t asic_blank_start = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1618

uint32_t newVstartup = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

338

uint32_t i, pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3394

uint32_t refresh_rate = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3395

uint32_t min_refresh = subvp_active_margin_list.min_refresh;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3396

uint32_t max_refresh = subvp_active_margin_list.max_refresh;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3397

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3400

uint32_t width = subvp_active_margin_list.res[i].width;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3401

uint32_t height = subvp_active_margin_list.res[i].height;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3436

uint32_t refresh_rate = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3437

uint32_t subvp_min_refresh = subvp_high_refresh_list.min_refresh;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3438

uint32_t subvp_max_refresh = subvp_high_refresh_list.max_refresh;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3439

uint32_t min_refresh = subvp_max_refresh;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3440

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3466

uint32_t width = subvp_high_refresh_list.res[i].width;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3467

uint32_t height = subvp_high_refresh_list.res[i].height;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3560

bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, struct dc_stream_state *fpo_candidate_stream, uint32_t vactive_margin_req_us)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

476

uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

730

uint32_t microschedule_lines = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

731

uint32_t index = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

732

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

733

uint32_t max_microschedule_us = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

738

uint32_t time_us = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

800

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

904

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

989

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

991

uint32_t min_refresh = subvp_high_refresh_list.min_refresh, max_refresh = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

74

bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, struct dc_stream_state *fpo_candidate_stream, uint32_t vactive_margin_req);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

54

uint32_t pixel_chunk_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

55

uint32_t min_pixel_chunk_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

56

uint32_t meta_chunk_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

57

uint32_t min_meta_chunk_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

58

uint32_t dpte_group_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

59

uint32_t mpte_group_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

61

uint32_t p1_pixel_chunk_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

62

uint32_t p1_min_pixel_chunk_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

63

uint32_t p1_meta_chunk_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

64

uint32_t p1_min_meta_chunk_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

65

uint32_t p1_dpte_group_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

66

uint32_t p1_mpte_group_bytes = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

91

uint32_t pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

100

uint32_t qos_level_fixed;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

101

uint32_t qos_ramp_disable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

105

uint32_t chunk_size;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

106

uint32_t min_chunk_size;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

107

uint32_t dpte_group_size;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

108

uint32_t mpte_group_size;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

109

uint32_t swath_height;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

110

uint32_t pte_row_height_linear;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

113

uint32_t meta_chunk_size;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

114

uint32_t min_meta_chunk_size;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

12

uint32_t refcyc_h_blank_end;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

120

uint32_t drq_expansion_mode;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

121

uint32_t prq_expansion_mode;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

122

uint32_t crq_expansion_mode;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

123

uint32_t plane1_base_address;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

124

uint32_t unbounded_request_enabled;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

127

uint32_t mrq_expansion_mode;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

13

uint32_t dlg_vblank_end;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

131

uint32_t mcache_id_first;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

132

uint32_t mcache_id_second;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

133

uint32_t split_location;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

14

uint32_t min_dst_y_next_start;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

15

uint32_t refcyc_per_htotal;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

152

uint32_t det_size;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

157

uint32_t urgent;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

158

uint32_t sr_enter;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

159

uint32_t sr_exit;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

16

uint32_t refcyc_x_after_scaler;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

160

uint32_t sr_enter_z8;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

161

uint32_t sr_exit_z8;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

162

uint32_t sr_enter_low_power;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

163

uint32_t sr_exit_low_power;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

164

uint32_t uclk_pstate;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

165

uint32_t fclk_pstate;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

166

uint32_t temp_read_or_ppt;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

167

uint32_t usr;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

169

uint32_t refcyc_per_trip_to_mem;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

17

uint32_t dst_y_after_scaler;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

170

uint32_t refcyc_per_meta_trip_to_mem;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

171

uint32_t frac_urg_bw_flip;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

172

uint32_t frac_urg_bw_nom;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

173

uint32_t frac_urg_bw_mall;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

18

uint32_t dst_y_prefetch;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

19

uint32_t dst_y_per_vm_vblank;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

20

uint32_t dst_y_per_row_vblank;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

21

uint32_t dst_y_per_vm_flip;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

22

uint32_t dst_y_per_row_flip;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

23

uint32_t ref_freq_to_pix_freq;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

24

uint32_t vratio_prefetch;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

25

uint32_t vratio_prefetch_c;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

26

uint32_t refcyc_per_tdlut_group;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

27

uint32_t refcyc_per_pte_group_vblank_l;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

28

uint32_t refcyc_per_pte_group_vblank_c;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

29

uint32_t refcyc_per_pte_group_flip_l;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

30

uint32_t refcyc_per_pte_group_flip_c;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

31

uint32_t dst_y_per_pte_row_nom_l;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

32

uint32_t dst_y_per_pte_row_nom_c;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

33

uint32_t refcyc_per_pte_group_nom_l;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

34

uint32_t refcyc_per_pte_group_nom_c;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

35

uint32_t refcyc_per_line_delivery_pre_l;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

36

uint32_t refcyc_per_line_delivery_pre_c;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

37

uint32_t refcyc_per_line_delivery_l;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

38

uint32_t refcyc_per_line_delivery_c;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

39

uint32_t refcyc_per_vm_group_vblank;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

40

uint32_t refcyc_per_vm_group_flip;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

41

uint32_t refcyc_per_vm_req_vblank;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

42

uint32_t refcyc_per_vm_req_flip;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

43

uint32_t dst_y_offset_cur0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

44

uint32_t chunk_hdl_adjust_cur0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

45

uint32_t vready_after_vcount0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

46

uint32_t dst_y_delta_drq_limit;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

47

uint32_t refcyc_per_vm_dmdata;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

48

uint32_t dmdata_dl_delta;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

49

uint32_t dst_y_svp_drq_limit;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

52

uint32_t refcyc_per_meta_chunk_vblank_l;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

53

uint32_t refcyc_per_meta_chunk_vblank_c;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

54

uint32_t refcyc_per_meta_chunk_flip_l;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

55

uint32_t refcyc_per_meta_chunk_flip_c;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

56

uint32_t dst_y_per_meta_row_nom_l;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

57

uint32_t dst_y_per_meta_row_nom_c;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

58

uint32_t refcyc_per_meta_chunk_nom_l;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

59

uint32_t refcyc_per_meta_chunk_nom_c;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

63

uint32_t qos_level_low_wm;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

64

uint32_t qos_level_high_wm;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

65

uint32_t min_ttu_vblank;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

66

uint32_t qos_level_flip;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

67

uint32_t refcyc_per_req_delivery_l;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

68

uint32_t refcyc_per_req_delivery_c;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

69

uint32_t refcyc_per_req_delivery_cur0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

70

uint32_t refcyc_per_req_delivery_pre_l;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

71

uint32_t refcyc_per_req_delivery_pre_c;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

72

uint32_t refcyc_per_req_delivery_pre_cur0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

73

uint32_t qos_level_fixed_l;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

74

uint32_t qos_level_fixed_c;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

75

uint32_t qos_level_fixed_cur0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

76

uint32_t qos_ramp_disable_l;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

77

uint32_t qos_ramp_disable_c;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

78

uint32_t qos_ramp_disable_cur0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

82

uint32_t max_req_outstanding;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

83

uint32_t min_req_outstanding;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

84

uint32_t sat_level_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

85

uint32_t hvm_max_qos_commit_threshold;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

86

uint32_t hvm_min_req_outstand_commit_threshold;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

87

uint32_t compbuf_reserved_space_kbytes;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

88

uint32_t compbuf_size;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

89

uint32_t sdpif_request_rate_limit;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

90

uint32_t allow_sdpif_rate_limit_when_cstate_req;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

91

uint32_t dcfclk_deep_sleep_hysteresis;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

92

uint32_t pstate_stall_threshold;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

96

uint32_t dst_x_offset; // CURSOR0_DST_X_OFFSET

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

97

uint32_t dst_y_offset; // CURSOR0_DST_Y_OFFSET

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

98

uint32_t chunk_hdl_adjust; // CURSOR0_CHUNK_HDL_ADJUST

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

404

uint32_t dispclk_did;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

405

uint32_t dpprefclk_did;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

406

uint32_t dtbrefclk_did;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

186

static bool add_margin_and_round_to_dfs_grainularity(double clock_khz, double margin, unsigned long vco_freq_khz, unsigned long *rounded_khz, uint32_t *divider_id)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

328

static const uint32_t MCACHE_ID_UNASSIGNED = 0xF;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

329

static const uint32_t SPLIT_LOCATION_UNDEFINED = 0xFFFF;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

34

uint32_t num_ways = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

35

uint32_t bytes_per_pixel = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

36

uint32_t cache_lines_used = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

361

uint32_t microschedule_lines = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

362

uint32_t index = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

363

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

364

uint32_t max_microschedule_us = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

369

uint32_t time_us = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

37

uint32_t lines_per_way = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

38

uint32_t total_cache_lines = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

39

uint32_t bytes_in_mall = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

40

uint32_t num_mblks = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

41

uint32_t cache_lines_per_plane = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

42

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

43

uint32_t mblk_width = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

434

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

44

uint32_t mblk_height = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

45

uint32_t full_vp_width_blk_aligned = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

46

uint32_t mall_alloc_width_blk_aligned = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

47

uint32_t mall_alloc_height_blk_aligned = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

513

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

605

uint32_t i, pipe_idx;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

660

uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.c

406

uint32_t cstate_enter_plus_exit_z8_ns;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

210

uint32_t re_mode = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

285

uint32_t pixel_format;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

286

uint32_t alpha_en;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

438

uint32_t width,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

439

uint32_t height)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

450

uint32_t cur_en = pos->enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

575

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1101

TF_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1105

uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1106

uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1107

uint32_t OTG_H_BLANK; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1108

uint32_t OTG_V_BLANK; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1109

uint32_t DSCL_MEM_PWR_CTRL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1110

uint32_t DSCL_MEM_PWR_STATUS; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1111

uint32_t SCL_MODE; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1112

uint32_t LB_DATA_FORMAT; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1113

uint32_t LB_MEMORY_CTRL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1114

uint32_t DSCL_AUTOCAL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1115

uint32_t DSCL_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1116

uint32_t SCL_BLACK_OFFSET; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1117

uint32_t SCL_TAP_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1118

uint32_t SCL_COEF_RAM_TAP_SELECT; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1119

uint32_t SCL_COEF_RAM_TAP_DATA; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1120

uint32_t DSCL_2TAP_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1121

uint32_t MPC_SIZE; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1122

uint32_t SCL_HORZ_FILTER_SCALE_RATIO; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1123

uint32_t SCL_VERT_FILTER_SCALE_RATIO; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1124

uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1125

uint32_t SCL_VERT_FILTER_SCALE_RATIO_C; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1126

uint32_t SCL_HORZ_FILTER_INIT; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1127

uint32_t SCL_HORZ_FILTER_INIT_C; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1128

uint32_t SCL_VERT_FILTER_INIT; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1129

uint32_t SCL_VERT_FILTER_INIT_BOT; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1130

uint32_t SCL_VERT_FILTER_INIT_C; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1131

uint32_t SCL_VERT_FILTER_INIT_BOT_C; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1132

uint32_t RECOUT_START; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1133

uint32_t RECOUT_SIZE; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1134

uint32_t CM_GAMUT_REMAP_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1135

uint32_t CM_GAMUT_REMAP_C11_C12; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1136

uint32_t CM_GAMUT_REMAP_C13_C14; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1137

uint32_t CM_GAMUT_REMAP_C21_C22; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1138

uint32_t CM_GAMUT_REMAP_C23_C24; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1139

uint32_t CM_GAMUT_REMAP_C31_C32; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1140

uint32_t CM_GAMUT_REMAP_C33_C34; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1141

uint32_t CM_COMA_C11_C12; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1142

uint32_t CM_COMA_C33_C34; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1143

uint32_t CM_COMB_C11_C12; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1144

uint32_t CM_COMB_C33_C34; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1145

uint32_t CM_OCSC_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1146

uint32_t CM_OCSC_C11_C12; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1147

uint32_t CM_OCSC_C33_C34; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1148

uint32_t CM_MEM_PWR_CTRL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1149

uint32_t CM_RGAM_LUT_DATA; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1150

uint32_t CM_RGAM_LUT_WRITE_EN_MASK; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1151

uint32_t CM_RGAM_LUT_INDEX; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1152

uint32_t CM_RGAM_RAMB_START_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1153

uint32_t CM_RGAM_RAMB_START_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1154

uint32_t CM_RGAM_RAMB_START_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1155

uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1156

uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1157

uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1158

uint32_t CM_RGAM_RAMB_END_CNTL1_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1159

uint32_t CM_RGAM_RAMB_END_CNTL2_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1160

uint32_t CM_RGAM_RAMB_END_CNTL1_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1161

uint32_t CM_RGAM_RAMB_END_CNTL2_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1162

uint32_t CM_RGAM_RAMB_END_CNTL1_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1163

uint32_t CM_RGAM_RAMB_END_CNTL2_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1164

uint32_t CM_RGAM_RAMB_REGION_0_1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1165

uint32_t CM_RGAM_RAMB_REGION_32_33; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1166

uint32_t CM_RGAM_RAMA_START_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1167

uint32_t CM_RGAM_RAMA_START_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1168

uint32_t CM_RGAM_RAMA_START_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1169

uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1170

uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1171

uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1172

uint32_t CM_RGAM_RAMA_END_CNTL1_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1173

uint32_t CM_RGAM_RAMA_END_CNTL2_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1174

uint32_t CM_RGAM_RAMA_END_CNTL1_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1175

uint32_t CM_RGAM_RAMA_END_CNTL2_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1176

uint32_t CM_RGAM_RAMA_END_CNTL1_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1177

uint32_t CM_RGAM_RAMA_END_CNTL2_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1178

uint32_t CM_RGAM_RAMA_REGION_0_1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1179

uint32_t CM_RGAM_RAMA_REGION_32_33; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1180

uint32_t CM_RGAM_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1181

uint32_t CM_CMOUT_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1182

uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1183

uint32_t CM_BLNDGAM_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1184

uint32_t CM_BLNDGAM_RAMB_START_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1185

uint32_t CM_BLNDGAM_RAMB_START_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1186

uint32_t CM_BLNDGAM_RAMB_START_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1187

uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1188

uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1189

uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1190

uint32_t CM_BLNDGAM_RAMB_END_CNTL1_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1191

uint32_t CM_BLNDGAM_RAMB_END_CNTL2_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1192

uint32_t CM_BLNDGAM_RAMB_END_CNTL1_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1193

uint32_t CM_BLNDGAM_RAMB_END_CNTL2_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1194

uint32_t CM_BLNDGAM_RAMB_END_CNTL1_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1195

uint32_t CM_BLNDGAM_RAMB_END_CNTL2_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1196

uint32_t CM_BLNDGAM_RAMB_REGION_0_1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1197

uint32_t CM_BLNDGAM_RAMB_REGION_2_3; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1198

uint32_t CM_BLNDGAM_RAMB_REGION_4_5; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1199

uint32_t CM_BLNDGAM_RAMB_REGION_6_7; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1200

uint32_t CM_BLNDGAM_RAMB_REGION_8_9; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1201

uint32_t CM_BLNDGAM_RAMB_REGION_10_11; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1202

uint32_t CM_BLNDGAM_RAMB_REGION_12_13; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1203

uint32_t CM_BLNDGAM_RAMB_REGION_14_15; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1204

uint32_t CM_BLNDGAM_RAMB_REGION_16_17; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1205

uint32_t CM_BLNDGAM_RAMB_REGION_18_19; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1206

uint32_t CM_BLNDGAM_RAMB_REGION_20_21; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1207

uint32_t CM_BLNDGAM_RAMB_REGION_22_23; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1208

uint32_t CM_BLNDGAM_RAMB_REGION_24_25; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1209

uint32_t CM_BLNDGAM_RAMB_REGION_26_27; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1210

uint32_t CM_BLNDGAM_RAMB_REGION_28_29; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1211

uint32_t CM_BLNDGAM_RAMB_REGION_30_31; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1212

uint32_t CM_BLNDGAM_RAMB_REGION_32_33; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1213

uint32_t CM_BLNDGAM_RAMA_START_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1214

uint32_t CM_BLNDGAM_RAMA_START_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1215

uint32_t CM_BLNDGAM_RAMA_START_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1216

uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1217

uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1218

uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1219

uint32_t CM_BLNDGAM_RAMA_END_CNTL1_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1220

uint32_t CM_BLNDGAM_RAMA_END_CNTL2_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1221

uint32_t CM_BLNDGAM_RAMA_END_CNTL1_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1222

uint32_t CM_BLNDGAM_RAMA_END_CNTL2_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1223

uint32_t CM_BLNDGAM_RAMA_END_CNTL1_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1224

uint32_t CM_BLNDGAM_RAMA_END_CNTL2_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1225

uint32_t CM_BLNDGAM_RAMA_REGION_0_1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1226

uint32_t CM_BLNDGAM_RAMA_REGION_2_3; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1227

uint32_t CM_BLNDGAM_RAMA_REGION_4_5; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1228

uint32_t CM_BLNDGAM_RAMA_REGION_6_7; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1229

uint32_t CM_BLNDGAM_RAMA_REGION_8_9; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1230

uint32_t CM_BLNDGAM_RAMA_REGION_10_11; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1231

uint32_t CM_BLNDGAM_RAMA_REGION_12_13; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1232

uint32_t CM_BLNDGAM_RAMA_REGION_14_15; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1233

uint32_t CM_BLNDGAM_RAMA_REGION_16_17; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1234

uint32_t CM_BLNDGAM_RAMA_REGION_18_19; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1235

uint32_t CM_BLNDGAM_RAMA_REGION_20_21; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1236

uint32_t CM_BLNDGAM_RAMA_REGION_22_23; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1237

uint32_t CM_BLNDGAM_RAMA_REGION_24_25; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1238

uint32_t CM_BLNDGAM_RAMA_REGION_26_27; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1239

uint32_t CM_BLNDGAM_RAMA_REGION_28_29; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1240

uint32_t CM_BLNDGAM_RAMA_REGION_30_31; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1241

uint32_t CM_BLNDGAM_RAMA_REGION_32_33; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1242

uint32_t CM_BLNDGAM_LUT_INDEX; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1243

uint32_t CM_3DLUT_MODE; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1244

uint32_t CM_3DLUT_INDEX; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1245

uint32_t CM_3DLUT_DATA; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1246

uint32_t CM_3DLUT_DATA_30BIT; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1247

uint32_t CM_3DLUT_READ_WRITE_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1248

uint32_t CM_SHAPER_LUT_WRITE_EN_MASK; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1249

uint32_t CM_SHAPER_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1250

uint32_t CM_SHAPER_RAMB_START_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1251

uint32_t CM_SHAPER_RAMB_START_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1252

uint32_t CM_SHAPER_RAMB_START_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1253

uint32_t CM_SHAPER_RAMB_END_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1254

uint32_t CM_SHAPER_RAMB_END_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1255

uint32_t CM_SHAPER_RAMB_END_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1256

uint32_t CM_SHAPER_RAMB_REGION_0_1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1257

uint32_t CM_SHAPER_RAMB_REGION_2_3; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1258

uint32_t CM_SHAPER_RAMB_REGION_4_5; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1259

uint32_t CM_SHAPER_RAMB_REGION_6_7; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1260

uint32_t CM_SHAPER_RAMB_REGION_8_9; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1261

uint32_t CM_SHAPER_RAMB_REGION_10_11; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1262

uint32_t CM_SHAPER_RAMB_REGION_12_13; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1263

uint32_t CM_SHAPER_RAMB_REGION_14_15; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1264

uint32_t CM_SHAPER_RAMB_REGION_16_17; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1265

uint32_t CM_SHAPER_RAMB_REGION_18_19; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1266

uint32_t CM_SHAPER_RAMB_REGION_20_21; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1267

uint32_t CM_SHAPER_RAMB_REGION_22_23; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1268

uint32_t CM_SHAPER_RAMB_REGION_24_25; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1269

uint32_t CM_SHAPER_RAMB_REGION_26_27; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1270

uint32_t CM_SHAPER_RAMB_REGION_28_29; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1271

uint32_t CM_SHAPER_RAMB_REGION_30_31; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1272

uint32_t CM_SHAPER_RAMB_REGION_32_33; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1273

uint32_t CM_SHAPER_RAMA_START_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1274

uint32_t CM_SHAPER_RAMA_START_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1275

uint32_t CM_SHAPER_RAMA_START_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1276

uint32_t CM_SHAPER_RAMA_END_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1277

uint32_t CM_SHAPER_RAMA_END_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1278

uint32_t CM_SHAPER_RAMA_END_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1279

uint32_t CM_SHAPER_RAMA_REGION_0_1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1280

uint32_t CM_SHAPER_RAMA_REGION_2_3; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1281

uint32_t CM_SHAPER_RAMA_REGION_4_5; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1282

uint32_t CM_SHAPER_RAMA_REGION_6_7; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1283

uint32_t CM_SHAPER_RAMA_REGION_8_9; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1284

uint32_t CM_SHAPER_RAMA_REGION_10_11; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1285

uint32_t CM_SHAPER_RAMA_REGION_12_13; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1286

uint32_t CM_SHAPER_RAMA_REGION_14_15; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1287

uint32_t CM_SHAPER_RAMA_REGION_16_17; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1288

uint32_t CM_SHAPER_RAMA_REGION_18_19; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1289

uint32_t CM_SHAPER_RAMA_REGION_20_21; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1290

uint32_t CM_SHAPER_RAMA_REGION_22_23; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1291

uint32_t CM_SHAPER_RAMA_REGION_24_25; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1292

uint32_t CM_SHAPER_RAMA_REGION_26_27; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1293

uint32_t CM_SHAPER_RAMA_REGION_28_29; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1294

uint32_t CM_SHAPER_RAMA_REGION_30_31; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1295

uint32_t CM_SHAPER_RAMA_REGION_32_33; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1296

uint32_t CM_SHAPER_LUT_INDEX; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1297

uint32_t CM_SHAPER_LUT_DATA; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1298

uint32_t CM_ICSC_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1299

uint32_t CM_ICSC_C11_C12; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1300

uint32_t CM_ICSC_C33_C34; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1301

uint32_t CM_BNS_VALUES_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1302

uint32_t CM_BNS_VALUES_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1303

uint32_t CM_BNS_VALUES_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1304

uint32_t CM_DGAM_RAMB_START_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1305

uint32_t CM_DGAM_RAMB_START_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1306

uint32_t CM_DGAM_RAMB_START_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1307

uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1308

uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1309

uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1310

uint32_t CM_DGAM_RAMB_END_CNTL1_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1311

uint32_t CM_DGAM_RAMB_END_CNTL2_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1312

uint32_t CM_DGAM_RAMB_END_CNTL1_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1313

uint32_t CM_DGAM_RAMB_END_CNTL2_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1314

uint32_t CM_DGAM_RAMB_END_CNTL1_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1315

uint32_t CM_DGAM_RAMB_END_CNTL2_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1316

uint32_t CM_DGAM_RAMB_REGION_0_1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1317

uint32_t CM_DGAM_RAMB_REGION_14_15; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1318

uint32_t CM_DGAM_RAMA_START_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1319

uint32_t CM_DGAM_RAMA_START_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1320

uint32_t CM_DGAM_RAMA_START_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1321

uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1322

uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1323

uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1324

uint32_t CM_DGAM_RAMA_END_CNTL1_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1325

uint32_t CM_DGAM_RAMA_END_CNTL2_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1326

uint32_t CM_DGAM_RAMA_END_CNTL1_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1327

uint32_t CM_DGAM_RAMA_END_CNTL2_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1328

uint32_t CM_DGAM_RAMA_END_CNTL1_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1329

uint32_t CM_DGAM_RAMA_END_CNTL2_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1330

uint32_t CM_DGAM_RAMA_REGION_0_1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1331

uint32_t CM_DGAM_RAMA_REGION_14_15; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1332

uint32_t CM_DGAM_LUT_WRITE_EN_MASK; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1333

uint32_t CM_DGAM_LUT_INDEX; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1334

uint32_t CM_DGAM_LUT_DATA; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1335

uint32_t CM_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1336

uint32_t CM_DGAM_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1337

uint32_t CM_IGAM_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1338

uint32_t CM_IGAM_LUT_RW_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1339

uint32_t CM_IGAM_LUT_RW_INDEX; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1340

uint32_t CM_IGAM_LUT_SEQ_COLOR; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1341

uint32_t CM_TEST_DEBUG_INDEX; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1342

uint32_t CM_TEST_DEBUG_DATA; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1343

uint32_t FORMAT_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1344

uint32_t CNVC_SURFACE_PIXEL_FORMAT; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1345

uint32_t CURSOR_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1346

uint32_t CURSOR0_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1347

uint32_t CURSOR0_COLOR0; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1348

uint32_t CURSOR0_COLOR1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1349

uint32_t DPP_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1350

uint32_t CM_HDR_MULT_COEF; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1351

uint32_t CURSOR0_FP_SCALE_BIAS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1390

uint32_t width,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1391

uint32_t height);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1423

uint32_t num,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1462

uint32_t num);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1512

uint32_t multiplier);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1521

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

189

uint32_t selection;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

256

uint32_t ocsc_mode;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

257

uint32_t cur_mode;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

398

uint32_t num)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

400

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

499

uint32_t cur_select = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

707

uint32_t status_reg = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

726

uint32_t num,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

729

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

799

uint32_t status_reg = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

833

uint32_t ram_num;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

877

uint32_t multiplier)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

184

uint32_t max_partitions = 63; /* Currently hardcoded on all ASICs before DCN 3.2 */

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

189

uint32_t pixel_depth = dpp1_dscl_get_pixel_depth_val(lb_params->depth);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

190

uint32_t dyn_pix_depth = lb_params->dynamic_pixel_depth;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

242

uint32_t taps,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

287

uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

288

uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

334

uint32_t scl_mode = REG_READ(SCL_MODE);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

513

uint32_t init_frac = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

514

uint32_t init_int = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

106

uint32_t pixel_format = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

107

uint32_t alpha_en = 1;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

112

uint32_t is_2bit = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

409

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

642

TF_REG_FIELD_LIST_DCN2_0(uint32_t);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

647

uint32_t CM_BLNDGAM_LUT_DATA; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

648

uint32_t ALPHA_2BIT_LUT; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

649

uint32_t FCNV_FP_BIAS_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

650

uint32_t FCNV_FP_BIAS_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

651

uint32_t FCNV_FP_BIAS_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

652

uint32_t FCNV_FP_SCALE_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

653

uint32_t FCNV_FP_SCALE_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

654

uint32_t FCNV_FP_SCALE_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

655

uint32_t COLOR_KEYER_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

656

uint32_t COLOR_KEYER_ALPHA; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

657

uint32_t COLOR_KEYER_RED; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

658

uint32_t COLOR_KEYER_GREEN; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

659

uint32_t COLOR_KEYER_BLUE; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

660

uint32_t OBUF_MEM_PWR_CTRL

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

663

uint32_t CM_GAMUT_REMAP_B_C11_C12; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

664

uint32_t CM_GAMUT_REMAP_B_C13_C14; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

665

uint32_t CM_GAMUT_REMAP_B_C21_C22; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

666

uint32_t CM_GAMUT_REMAP_B_C23_C24; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

667

uint32_t CM_GAMUT_REMAP_B_C31_C32; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

668

uint32_t CM_GAMUT_REMAP_B_C33_C34; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

669

uint32_t CM_ICSC_B_C11_C12; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

670

uint32_t CM_ICSC_B_C33_C34

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

773

uint32_t multiplier);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

777

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1019

uint32_t lut_mode;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1052

uint32_t entries)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1054

uint32_t i, red, green, blue, red1, green1, blue1;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1086

uint32_t entries)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1088

uint32_t i, red, green, blue, value;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1106

uint32_t ram_selection_mask)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1197

uint32_t multiplier)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

166

uint32_t cur_select = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

242

uint32_t selection;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

302

uint32_t cur_select = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

392

uint32_t num)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

394

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

499

uint32_t state_mode;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

560

uint32_t num)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

562

uint32_t i, red, green, blue;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

563

uint32_t red_delta, green_delta, blue_delta;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

564

uint32_t red_value, green_value, blue_value;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

592

uint32_t state_mode;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

69

uint32_t status_reg = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

88

uint32_t num,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

91

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

972

uint32_t i_mode, i_enable_10bits, lut_size;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

300

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

53

uint32_t pixel_format = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

54

uint32_t alpha_en = 1;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

58

uint32_t is_2bit = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h

47

TF_REG_FIELD_LIST_DCN201(uint32_t);

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h

78

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1238

uint32_t i_mode, i_enable_10bits, lut_size;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1286

uint32_t lut_mode;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1319

uint32_t entries)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1321

uint32_t i, red, green, blue, red1, green1, blue1;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1353

uint32_t entries)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1355

uint32_t i, red, green, blue, value;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1373

uint32_t ram_selection_mask)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1506

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

213

uint32_t pixel_format = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

214

uint32_t alpha_en = 1;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

218

uint32_t is_2bit = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

219

uint32_t alpha_plane_enable = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

220

uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

221

uint32_t realpha_en = 0, realpha_ablnd_en = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

47

uint32_t gamcor_lut_mode, rgam_lut_mode;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

634

uint32_t num)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

636

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

638

uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

639

uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

640

uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

753

uint32_t mode_current = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

754

uint32_t in_use = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

822

uint32_t num)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

824

uint32_t i, red, green, blue;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

825

uint32_t red_delta, green_delta, blue_delta;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

826

uint32_t red_value, green_value, blue_value;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

854

uint32_t state_mode;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

98

uint32_t cur_select = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

472

DPP_REG_FIELD_LIST_DCN3(uint32_t);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

477

uint32_t CM_MEM_PWR_STATUS;\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

478

uint32_t CM_MEM_PWR_STATUS2;\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

479

uint32_t CM_MEM_PWR_CTRL2;\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

480

uint32_t CM_DEALPHA;\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

481

uint32_t CM_BIAS_CR_R;\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

482

uint32_t CM_BIAS_Y_G_CB_B;\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

483

uint32_t PRE_DEGAM;\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

484

uint32_t PRE_DEALPHA; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

485

uint32_t PRE_REALPHA; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

486

uint32_t PRE_CSC_MODE; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

487

uint32_t PRE_CSC_C11_C12; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

488

uint32_t PRE_CSC_C33_C34; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

489

uint32_t PRE_CSC_B_C11_C12; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

490

uint32_t PRE_CSC_B_C33_C34; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

491

uint32_t CM_POST_CSC_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

492

uint32_t CM_POST_CSC_C11_C12; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

493

uint32_t CM_POST_CSC_C33_C34; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

494

uint32_t CM_POST_CSC_B_C11_C12; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

495

uint32_t CM_POST_CSC_B_C33_C34; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

496

uint32_t CM_GAMUT_REMAP_B_C11_C12; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

497

uint32_t CM_GAMUT_REMAP_B_C13_C14; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

498

uint32_t CM_GAMUT_REMAP_B_C21_C22; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

499

uint32_t CM_GAMUT_REMAP_B_C23_C24; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

500

uint32_t CM_GAMUT_REMAP_B_C31_C32; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

501

uint32_t CM_GAMUT_REMAP_B_C33_C34; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

502

uint32_t CM_GAMCOR_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

503

uint32_t CM_GAMCOR_LUT_CONTROL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

504

uint32_t CM_GAMCOR_LUT_INDEX; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

505

uint32_t CM_GAMCOR_LUT_DATA; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

506

uint32_t CM_GAMCOR_RAMB_START_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

507

uint32_t CM_GAMCOR_RAMB_START_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

508

uint32_t CM_GAMCOR_RAMB_START_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

509

uint32_t CM_GAMCOR_RAMB_START_SLOPE_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

510

uint32_t CM_GAMCOR_RAMB_START_SLOPE_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

511

uint32_t CM_GAMCOR_RAMB_START_SLOPE_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

512

uint32_t CM_GAMCOR_RAMB_END_CNTL1_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

513

uint32_t CM_GAMCOR_RAMB_END_CNTL2_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

514

uint32_t CM_GAMCOR_RAMB_END_CNTL1_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

515

uint32_t CM_GAMCOR_RAMB_END_CNTL2_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

516

uint32_t CM_GAMCOR_RAMB_END_CNTL1_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

517

uint32_t CM_GAMCOR_RAMB_END_CNTL2_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

518

uint32_t CM_GAMCOR_RAMB_REGION_0_1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

519

uint32_t CM_GAMCOR_RAMB_REGION_32_33; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

520

uint32_t CM_GAMCOR_RAMB_OFFSET_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

521

uint32_t CM_GAMCOR_RAMB_OFFSET_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

522

uint32_t CM_GAMCOR_RAMB_OFFSET_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

523

uint32_t CM_GAMCOR_RAMB_START_BASE_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

524

uint32_t CM_GAMCOR_RAMB_START_BASE_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

525

uint32_t CM_GAMCOR_RAMB_START_BASE_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

526

uint32_t CM_GAMCOR_RAMA_START_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

527

uint32_t CM_GAMCOR_RAMA_START_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

528

uint32_t CM_GAMCOR_RAMA_START_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

529

uint32_t CM_GAMCOR_RAMA_START_SLOPE_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

530

uint32_t CM_GAMCOR_RAMA_START_SLOPE_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

531

uint32_t CM_GAMCOR_RAMA_START_SLOPE_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

532

uint32_t CM_GAMCOR_RAMA_END_CNTL1_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

533

uint32_t CM_GAMCOR_RAMA_END_CNTL2_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

534

uint32_t CM_GAMCOR_RAMA_END_CNTL1_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

535

uint32_t CM_GAMCOR_RAMA_END_CNTL2_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

536

uint32_t CM_GAMCOR_RAMA_END_CNTL1_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

537

uint32_t CM_GAMCOR_RAMA_END_CNTL2_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

538

uint32_t CM_GAMCOR_RAMA_REGION_0_1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

539

uint32_t CM_GAMCOR_RAMA_REGION_32_33; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

540

uint32_t CM_GAMCOR_RAMA_OFFSET_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

541

uint32_t CM_GAMCOR_RAMA_OFFSET_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

542

uint32_t CM_GAMCOR_RAMA_OFFSET_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

543

uint32_t CM_GAMCOR_RAMA_START_BASE_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

544

uint32_t CM_GAMCOR_RAMA_START_BASE_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

545

uint32_t CM_GAMCOR_RAMA_START_BASE_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

546

uint32_t CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

547

uint32_t CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

548

uint32_t CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

549

uint32_t CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

550

uint32_t CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

551

uint32_t CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

552

uint32_t CM_BLNDGAM_LUT_CONTROL

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

582

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

592

uint32_t enable, uint32_t additive_blending);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

616

uint32_t multiplier);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

641

uint32_t enable, uint32_t additive_blending);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

147

uint32_t enable, uint32_t additive_blending)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

306

uint32_t multiplier)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

414

uint32_t selection;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

60

uint32_t state_mode;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

61

uint32_t lut_mode;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

80

uint32_t num,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

83

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

85

uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

86

uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

87

uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;

sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

149

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.h

33

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

130

uint32_t inst, const struct dcn3_dpp_registers *tf_regs,

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h

49

DPP_REG_FIELD_LIST_DCN35(uint32_t);

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h

58

uint32_t inst, const struct dcn3_dpp_registers *tf_regs,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

264

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

64

uint32_t pixel_format = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

65

uint32_t alpha_en = 1;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

68

uint32_t is_2bit = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

69

uint32_t alpha_plane_enable = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

70

uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

71

uint32_t realpha_en = 0, realpha_ablnd_en = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

572

uint32_t CURSOR0_FP_SCALE_BIAS_G_Y; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

573

uint32_t CURSOR0_FP_SCALE_BIAS_RB_CRCB; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

574

uint32_t CUR0_MATRIX_MODE; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

575

uint32_t CUR0_MATRIX_C11_C12_A; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

576

uint32_t CUR0_MATRIX_C13_C14_A; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

577

uint32_t CUR0_MATRIX_C21_C22_A; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

578

uint32_t CUR0_MATRIX_C23_C24_A; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

579

uint32_t CUR0_MATRIX_C31_C32_A; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

580

uint32_t CUR0_MATRIX_C33_C34_A; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

581

uint32_t CUR0_MATRIX_C11_C12_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

582

uint32_t CUR0_MATRIX_C13_C14_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

583

uint32_t CUR0_MATRIX_C21_C22_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

584

uint32_t CUR0_MATRIX_C23_C24_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

585

uint32_t CUR0_MATRIX_C31_C32_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

586

uint32_t CUR0_MATRIX_C33_C34_B; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

587

uint32_t DSCL_SC_MODE; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

588

uint32_t DSCL_EASF_H_MODE; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

589

uint32_t DSCL_EASF_H_BF_CNTL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

590

uint32_t DSCL_EASF_H_RINGEST_EVENTAP_REDUCE; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

591

uint32_t DSCL_EASF_H_RINGEST_EVENTAP_GAIN; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

592

uint32_t DSCL_EASF_H_BF_FINAL_MAX_MIN; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

593

uint32_t DSCL_EASF_H_BF1_PWL_SEG0; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

594

uint32_t DSCL_EASF_H_BF1_PWL_SEG1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

595

uint32_t DSCL_EASF_H_BF1_PWL_SEG2; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

596

uint32_t DSCL_EASF_H_BF1_PWL_SEG3; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

597

uint32_t DSCL_EASF_H_BF1_PWL_SEG4; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

598

uint32_t DSCL_EASF_H_BF1_PWL_SEG5; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

599

uint32_t DSCL_EASF_H_BF1_PWL_SEG6; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

600

uint32_t DSCL_EASF_H_BF1_PWL_SEG7; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

601

uint32_t DSCL_EASF_H_BF3_PWL_SEG0; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

602

uint32_t DSCL_EASF_H_BF3_PWL_SEG1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

603

uint32_t DSCL_EASF_H_BF3_PWL_SEG2; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

604

uint32_t DSCL_EASF_H_BF3_PWL_SEG3; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

605

uint32_t DSCL_EASF_H_BF3_PWL_SEG4; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

606

uint32_t DSCL_EASF_H_BF3_PWL_SEG5; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

607

uint32_t DSCL_EASF_V_MODE; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

608

uint32_t DSCL_EASF_V_BF_CNTL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

609

uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

610

uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL2; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

611

uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL3; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

612

uint32_t DSCL_EASF_V_RINGEST_EVENTAP_REDUCE; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

613

uint32_t DSCL_EASF_V_RINGEST_EVENTAP_GAIN; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

614

uint32_t DSCL_EASF_V_BF_FINAL_MAX_MIN; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

615

uint32_t DSCL_EASF_V_BF1_PWL_SEG0; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

616

uint32_t DSCL_EASF_V_BF1_PWL_SEG1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

617

uint32_t DSCL_EASF_V_BF1_PWL_SEG2; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

618

uint32_t DSCL_EASF_V_BF1_PWL_SEG3; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

619

uint32_t DSCL_EASF_V_BF1_PWL_SEG4; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

620

uint32_t DSCL_EASF_V_BF1_PWL_SEG5; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

621

uint32_t DSCL_EASF_V_BF1_PWL_SEG6; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

622

uint32_t DSCL_EASF_V_BF1_PWL_SEG7; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

623

uint32_t DSCL_EASF_V_BF3_PWL_SEG0; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

624

uint32_t DSCL_EASF_V_BF3_PWL_SEG1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

625

uint32_t DSCL_EASF_V_BF3_PWL_SEG2; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

626

uint32_t DSCL_EASF_V_BF3_PWL_SEG3; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

627

uint32_t DSCL_EASF_V_BF3_PWL_SEG4; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

628

uint32_t DSCL_EASF_V_BF3_PWL_SEG5; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

629

uint32_t DSCL_SC_MATRIX_C0C1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

630

uint32_t DSCL_SC_MATRIX_C2C3; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

631

uint32_t ISHARP_MODE; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

632

uint32_t ISHARP_NOISEDET_THRESHOLD; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

633

uint32_t ISHARP_NOISE_GAIN_PWL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

634

uint32_t ISHARP_LBA_PWL_SEG0; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

635

uint32_t ISHARP_LBA_PWL_SEG1; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

636

uint32_t ISHARP_LBA_PWL_SEG2; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

637

uint32_t ISHARP_LBA_PWL_SEG3; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

638

uint32_t ISHARP_LBA_PWL_SEG4; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

639

uint32_t ISHARP_LBA_PWL_SEG5; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

640

uint32_t ISHARP_DELTA_CTRL; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

641

uint32_t ISHARP_DELTA_DATA; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

642

uint32_t ISHARP_DELTA_INDEX; \

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

643

uint32_t ISHARP_NLDELTA_SOFT_CLIP

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

654

DPP_REG_FIELD_LIST_DCN401(uint32_t);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

688

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

713

uint32_t width,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

714

uint32_t height);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

128

uint32_t width,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

129

uint32_t height)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

132

uint32_t cur_en = pos->enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

162

uint32_t mode_select = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1058

uint32_t mpc_width = scl_data->h_active;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1059

uint32_t mpc_height = scl_data->v_active;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1060

uint32_t v_num_taps = scl_data->taps.v_taps - 1;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1061

uint32_t v_num_taps_c = scl_data->taps.v_taps_c - 1;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1062

uint32_t h_num_taps = scl_data->taps.h_taps - 1;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1063

uint32_t h_num_taps_c = scl_data->taps.h_taps_c - 1;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1085

sizeof(uint32_t) * ISHARP_LUT_TABLE_SIZE);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

176

uint32_t max_partitions = 63; /* Currently hardcoded on all ASICs before DCN 3.2 */

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

181

uint32_t pixel_depth = dpp401_dscl_get_pixel_depth_val(lb_params->depth);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

182

uint32_t dyn_pix_depth = lb_params->dynamic_pixel_depth;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

234

uint32_t taps,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

280

uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

281

uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

338

uint32_t scl_mode = REG_READ(SCL_MODE);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

519

uint32_t init_frac = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

520

uint32_t init_int = 0;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

921

struct dcn401_dpp *dpp, const uint32_t *filter)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

924

uint32_t filter_data;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1297

uint32_t target_bandwidth_kbps,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1320

uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1321

uint32_t bpp_x16, uint32_t num_slices_h, bool is_dp)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1323

uint32_t overhead_in_kbps;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1336

uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps(

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1363

uint32_t max_target_bpp_limit_override_x16,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1367

uint32_t bpc = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1432

void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

161

const uint32_t min_bpp_x16,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

162

const uint32_t max_bpp_x16,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

163

const uint32_t num_slices_h,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

169

static uint32_t compute_bpp_x16_from_target_bandwidth(

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

170

const uint32_t bandwidth_in_kbps,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

172

const uint32_t num_slices_h,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

173

const uint32_t bpp_increment_div,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

299

static bool dsc_bpp_increment_div_from_dpcd(uint8_t bpp_increment_dpcd, uint32_t *bpp_increment_div)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

42

static uint32_t dsc_policy_max_target_bpp_limit = 16;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

460

uint32_t dsc_min_slice_height_override,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

461

uint32_t min_bpp_x16,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

462

uint32_t max_bpp_x16,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

61

static uint32_t apply_128b_132b_stream_overhead(

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

62

const struct dc_crtc_timing *timing, const uint32_t kbps)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

630

static inline uint32_t dsc_div_by_10_round_up(uint32_t value)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

64

uint32_t total_kbps = kbps;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

761

dsc_common_caps->bpp_increment_div = min(dsc_common_caps->bpp_increment_div, (uint32_t)8);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

768

static uint32_t compute_bpp_x16_from_target_bandwidth(

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

769

const uint32_t bandwidth_in_kbps,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

771

const uint32_t num_slices_h,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

772

const uint32_t bpp_increment_div,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

775

uint32_t overhead_in_kbps;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

798

const uint32_t min_bpp_x16,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

799

const uint32_t max_bpp_x16,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

800

const uint32_t num_slices_h,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

806

uint32_t preferred_bpp_x16 = timing->dsc_fixed_bits_per_pixel_x16;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

93

uint32_t dc_bandwidth_in_kbps_from_timing(

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

97

uint32_t bits_per_channel = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

98

uint32_t kbps;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

580

uint32_t temp_int;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

468

uint32_t DSC_TOP_CONTROL;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

469

uint32_t DSC_DEBUG_CONTROL;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

470

uint32_t DSCC_CONFIG0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

471

uint32_t DSCC_CONFIG1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

472

uint32_t DSCC_STATUS;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

473

uint32_t DSCC_INTERRUPT_CONTROL_STATUS;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

474

uint32_t DSCC_PPS_CONFIG0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

475

uint32_t DSCC_PPS_CONFIG1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

476

uint32_t DSCC_PPS_CONFIG2;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

477

uint32_t DSCC_PPS_CONFIG3;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

478

uint32_t DSCC_PPS_CONFIG4;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

479

uint32_t DSCC_PPS_CONFIG5;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

480

uint32_t DSCC_PPS_CONFIG6;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

481

uint32_t DSCC_PPS_CONFIG7;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

482

uint32_t DSCC_PPS_CONFIG8;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

483

uint32_t DSCC_PPS_CONFIG9;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

484

uint32_t DSCC_PPS_CONFIG10;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

485

uint32_t DSCC_PPS_CONFIG11;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

486

uint32_t DSCC_PPS_CONFIG12;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

487

uint32_t DSCC_PPS_CONFIG13;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

488

uint32_t DSCC_PPS_CONFIG14;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

489

uint32_t DSCC_PPS_CONFIG15;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

490

uint32_t DSCC_PPS_CONFIG16;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

491

uint32_t DSCC_PPS_CONFIG17;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

492

uint32_t DSCC_PPS_CONFIG18;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

493

uint32_t DSCC_PPS_CONFIG19;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

494

uint32_t DSCC_PPS_CONFIG20;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

495

uint32_t DSCC_PPS_CONFIG21;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

496

uint32_t DSCC_PPS_CONFIG22;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

497

uint32_t DSCC_MEM_POWER_CONTROL;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

498

uint32_t DSCC_R_Y_SQUARED_ERROR_LOWER;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

499

uint32_t DSCC_R_Y_SQUARED_ERROR_UPPER;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

500

uint32_t DSCC_G_CB_SQUARED_ERROR_LOWER;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

501

uint32_t DSCC_G_CB_SQUARED_ERROR_UPPER;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

502

uint32_t DSCC_B_CR_SQUARED_ERROR_LOWER;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

503

uint32_t DSCC_B_CR_SQUARED_ERROR_UPPER;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

504

uint32_t DSCC_MAX_ABS_ERROR0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

505

uint32_t DSCC_MAX_ABS_ERROR1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

506

uint32_t DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

507

uint32_t DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

508

uint32_t DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

509

uint32_t DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

510

uint32_t DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

511

uint32_t DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

512

uint32_t DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

513

uint32_t DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

514

uint32_t DSCC_TEST_DEBUG_BUS_ROTATE;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

515

uint32_t DSCCIF_CONFIG0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

516

uint32_t DSCCIF_CONFIG1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

517

uint32_t DSCRM_DSC_FORWARD_CONFIG;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

526

DSC_FIELD_LIST_DCN20(uint32_t);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

544

uint32_t dsc_clock_enable;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

545

uint32_t dsc_clock_gating_disable;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

546

uint32_t underflow_recovery_en;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

547

uint32_t underflow_occurred_int_en;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

548

uint32_t underflow_occurred_status;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

550

uint32_t ich_reset_at_eol;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

551

uint32_t alternate_ich_encoding_en;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

552

uint32_t num_slices_h;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

553

uint32_t num_slices_v;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

554

uint32_t rc_buffer_model_size;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

555

uint32_t disable_ich;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

556

uint32_t bpp_x32;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

557

uint32_t dsc_dbg_en;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

558

uint32_t rc_buffer_model_overflow_int_en[4];

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.h

47

DSC_FIELD_LIST_DCN35(uint32_t);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

201

uint32_t temp_int;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

203

uint32_t DSC_TOP_CONTROL;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

204

uint32_t DSC_DEBUG_CONTROL;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

205

uint32_t DSCC_CONFIG0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

206

uint32_t DSCC_CONFIG1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

207

uint32_t DSCC_STATUS;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

208

uint32_t DSCC_INTERRUPT_CONTROL0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

209

uint32_t DSCC_INTERRUPT_CONTROL1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

210

uint32_t DSCC_INTERRUPT_STATUS0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

211

uint32_t DSCC_INTERRUPT_STATUS1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

212

uint32_t DSCC_PPS_CONFIG0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

213

uint32_t DSCC_PPS_CONFIG1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

214

uint32_t DSCC_PPS_CONFIG2;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

215

uint32_t DSCC_PPS_CONFIG3;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

216

uint32_t DSCC_PPS_CONFIG4;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

217

uint32_t DSCC_PPS_CONFIG5;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

218

uint32_t DSCC_PPS_CONFIG6;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

219

uint32_t DSCC_PPS_CONFIG7;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

220

uint32_t DSCC_PPS_CONFIG8;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

221

uint32_t DSCC_PPS_CONFIG9;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

222

uint32_t DSCC_PPS_CONFIG10;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

223

uint32_t DSCC_PPS_CONFIG11;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

224

uint32_t DSCC_PPS_CONFIG12;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

225

uint32_t DSCC_PPS_CONFIG13;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

226

uint32_t DSCC_PPS_CONFIG14;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

227

uint32_t DSCC_PPS_CONFIG15;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

228

uint32_t DSCC_PPS_CONFIG16;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

229

uint32_t DSCC_PPS_CONFIG17;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

230

uint32_t DSCC_PPS_CONFIG18;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

231

uint32_t DSCC_PPS_CONFIG19;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

232

uint32_t DSCC_PPS_CONFIG20;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

233

uint32_t DSCC_PPS_CONFIG21;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

234

uint32_t DSCC_PPS_CONFIG22;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

235

uint32_t DSCC_MEM_POWER_CONTROL0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

236

uint32_t DSCC_MEM_POWER_CONTROL1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

237

uint32_t DSCC_R_Y_SQUARED_ERROR_LOWER;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

238

uint32_t DSCC_R_Y_SQUARED_ERROR_UPPER;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

239

uint32_t DSCC_G_CB_SQUARED_ERROR_LOWER;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

240

uint32_t DSCC_G_CB_SQUARED_ERROR_UPPER;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

241

uint32_t DSCC_B_CR_SQUARED_ERROR_LOWER;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

242

uint32_t DSCC_B_CR_SQUARED_ERROR_UPPER;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

243

uint32_t DSCC_MAX_ABS_ERROR0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

244

uint32_t DSCC_MAX_ABS_ERROR1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

245

uint32_t DSCC_TEST_DEBUG_BUS_ROTATE;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

246

uint32_t DSCCIF_CONFIG0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

247

uint32_t DSCRM_DSC_FORWARD_CONFIG;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

248

uint32_t DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

249

uint32_t DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

250

uint32_t DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

251

uint32_t DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

252

uint32_t DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

253

uint32_t DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

254

uint32_t DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

255

uint32_t DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

314

DSC_FIELD_LIST_DCN401(uint32_t);

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

38

uint32_t pic_width;

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

39

uint32_t pic_height;

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

49

uint32_t slice_width; /* Slice width in pixels */

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

50

uint32_t bytes_per_pixel; /* Bytes per pixel in u3.28 format */

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

56

uint32_t dsc_clock_en;

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

57

uint32_t dsc_slice_width;

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

58

uint32_t dsc_bits_per_pixel;

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

59

uint32_t dsc_slice_height;

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

60

uint32_t dsc_pic_width;

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

61

uint32_t dsc_pic_height;

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

62

uint32_t dsc_slice_bpg_offset;

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

63

uint32_t dsc_chunk_size;

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

64

uint32_t dsc_fw_en;

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

65

uint32_t dsc_opp_source;

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

94

uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

95

uint32_t edp_sink_max_bits_per_pixel;

sys/dev/pci/drm/amd/display/dc/dsc/dscc_types.h

45

uint32_t bytes_per_pixel; /* In u3.28 format */

sys/dev/pci/drm/amd/display/dc/dsc/dscc_types.h

46

uint32_t rc_buffer_model_size;

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc_dpi.c

115

(uint32_t)(div_u64(((uint64_t)dsc_cfg.slice_chunk_size * 0x10000000 + (dsc_cfg.slice_width - 1)),

sys/dev/pci/drm/amd/display/dc/dsc/rc_calc_dpi.c

116

(uint32_t)dsc_cfg.slice_width)); /* Round-up */

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h

41

TF_HELPER_REG_FIELD_LIST_DCN3(uint32_t);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h

49

uint32_t offset_b;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h

50

uint32_t offset_g;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h

51

uint32_t offset_r;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h

52

uint32_t start_base_cntl_b;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h

53

uint32_t start_base_cntl_g;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h

54

uint32_t start_base_cntl_r;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h

69

uint32_t hw_points_num,

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h

72

bool is_rgb_equal(const struct pwl_result_data *rgb, uint32_t num);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

720

uint32_t DWB_ENABLE_CLK_CTRL;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

721

uint32_t DWB_MEM_PWR_CTRL;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

722

uint32_t FC_MODE_CTRL;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

723

uint32_t FC_FLOW_CTRL;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

724

uint32_t FC_WINDOW_START;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

725

uint32_t FC_WINDOW_SIZE;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

726

uint32_t FC_SOURCE_SIZE;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

727

uint32_t DWB_UPDATE_CTRL;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

728

uint32_t DWB_CRC_CTRL;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

729

uint32_t DWB_CRC_MASK_R_G;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

730

uint32_t DWB_CRC_MASK_B_A;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

731

uint32_t DWB_CRC_VAL_R_G;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

732

uint32_t DWB_CRC_VAL_B_A;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

733

uint32_t DWB_OUT_CTRL;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

734

uint32_t DWB_MMHUBBUB_BACKPRESSURE_CNT_EN;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

735

uint32_t DWB_MMHUBBUB_BACKPRESSURE_CNT;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

736

uint32_t DWB_HOST_READ_CONTROL;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

737

uint32_t DWB_SOFT_RESET;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

738

uint32_t DWB_DEBUG_CTRL;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

739

uint32_t DWB_DEBUG;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

740

uint32_t DWB_TEST_DEBUG_INDEX;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

741

uint32_t DWB_TEST_DEBUG_DATA;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

744

uint32_t DWBSCL_COEF_RAM_TAP_SELECT;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

745

uint32_t DWBSCL_COEF_RAM_TAP_DATA;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

746

uint32_t DWBSCL_MODE;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

747

uint32_t DWBSCL_TAP_CONTROL;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

748

uint32_t DWBSCL_HORZ_FILTER_SCALE_RATIO;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

749

uint32_t DWBSCL_HORZ_FILTER_INIT;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

750

uint32_t DWBSCL_VERT_FILTER_SCALE_RATIO;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

751

uint32_t DWBSCL_VERT_FILTER_INIT;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

752

uint32_t DWBSCL_BOUNDARY_CTRL;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

753

uint32_t DWBSCL_DEST_SIZE;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

754

uint32_t DWBSCL_OVERFLOW_STATUS;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

755

uint32_t DWBSCL_OVERFLOW_COUNTER;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

756

uint32_t DWBSCL_DEBUG;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

757

uint32_t DWBSCL_TEST_DEBUG_INDEX;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

758

uint32_t DWBSCL_TEST_DEBUG_DATA;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

761

uint32_t DWB_HDR_MULT_COEF;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

762

uint32_t DWB_GAMUT_REMAP_MODE;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

763

uint32_t DWB_GAMUT_REMAP_COEF_FORMAT;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

764

uint32_t DWB_GAMUT_REMAPA_C11_C12;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

765

uint32_t DWB_GAMUT_REMAPA_C13_C14;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

766

uint32_t DWB_GAMUT_REMAPA_C21_C22;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

767

uint32_t DWB_GAMUT_REMAPA_C23_C24;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

768

uint32_t DWB_GAMUT_REMAPA_C31_C32;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

769

uint32_t DWB_GAMUT_REMAPA_C33_C34;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

770

uint32_t DWB_GAMUT_REMAPB_C11_C12;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

771

uint32_t DWB_GAMUT_REMAPB_C13_C14;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

772

uint32_t DWB_GAMUT_REMAPB_C21_C22;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

773

uint32_t DWB_GAMUT_REMAPB_C23_C24;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

774

uint32_t DWB_GAMUT_REMAPB_C31_C32;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

775

uint32_t DWB_GAMUT_REMAPB_C33_C34;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

776

uint32_t DWB_OGAM_CONTROL;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

777

uint32_t DWB_OGAM_LUT_INDEX;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

778

uint32_t DWB_OGAM_LUT_DATA;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

779

uint32_t DWB_OGAM_LUT_CONTROL;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

780

uint32_t DWB_OGAM_RAMA_START_CNTL_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

781

uint32_t DWB_OGAM_RAMA_START_CNTL_G;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

782

uint32_t DWB_OGAM_RAMA_START_CNTL_R;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

783

uint32_t DWB_OGAM_RAMA_START_BASE_CNTL_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

784

uint32_t DWB_OGAM_RAMA_START_SLOPE_CNTL_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

785

uint32_t DWB_OGAM_RAMA_START_BASE_CNTL_G;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

786

uint32_t DWB_OGAM_RAMA_START_SLOPE_CNTL_G;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

787

uint32_t DWB_OGAM_RAMA_START_BASE_CNTL_R;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

788

uint32_t DWB_OGAM_RAMA_START_SLOPE_CNTL_R;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

789

uint32_t DWB_OGAM_RAMA_END_CNTL1_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

790

uint32_t DWB_OGAM_RAMA_END_CNTL2_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

791

uint32_t DWB_OGAM_RAMA_END_CNTL1_G;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

792

uint32_t DWB_OGAM_RAMA_END_CNTL2_G;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

793

uint32_t DWB_OGAM_RAMA_END_CNTL1_R;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

794

uint32_t DWB_OGAM_RAMA_END_CNTL2_R;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

795

uint32_t DWB_OGAM_RAMA_OFFSET_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

796

uint32_t DWB_OGAM_RAMA_OFFSET_G;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

797

uint32_t DWB_OGAM_RAMA_OFFSET_R;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

798

uint32_t DWB_OGAM_RAMA_REGION_0_1;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

799

uint32_t DWB_OGAM_RAMA_REGION_2_3;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

800

uint32_t DWB_OGAM_RAMA_REGION_4_5;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

801

uint32_t DWB_OGAM_RAMA_REGION_6_7;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

802

uint32_t DWB_OGAM_RAMA_REGION_8_9;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

803

uint32_t DWB_OGAM_RAMA_REGION_10_11;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

804

uint32_t DWB_OGAM_RAMA_REGION_12_13;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

805

uint32_t DWB_OGAM_RAMA_REGION_14_15;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

806

uint32_t DWB_OGAM_RAMA_REGION_16_17;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

807

uint32_t DWB_OGAM_RAMA_REGION_18_19;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

808

uint32_t DWB_OGAM_RAMA_REGION_20_21;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

809

uint32_t DWB_OGAM_RAMA_REGION_22_23;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

810

uint32_t DWB_OGAM_RAMA_REGION_24_25;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

811

uint32_t DWB_OGAM_RAMA_REGION_26_27;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

812

uint32_t DWB_OGAM_RAMA_REGION_28_29;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

813

uint32_t DWB_OGAM_RAMA_REGION_30_31;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

814

uint32_t DWB_OGAM_RAMA_REGION_32_33;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

815

uint32_t DWB_OGAM_RAMB_START_CNTL_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

816

uint32_t DWB_OGAM_RAMB_START_CNTL_G;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

817

uint32_t DWB_OGAM_RAMB_START_CNTL_R;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

818

uint32_t DWB_OGAM_RAMB_START_BASE_CNTL_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

819

uint32_t DWB_OGAM_RAMB_START_SLOPE_CNTL_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

820

uint32_t DWB_OGAM_RAMB_START_BASE_CNTL_G;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

821

uint32_t DWB_OGAM_RAMB_START_SLOPE_CNTL_G;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

822

uint32_t DWB_OGAM_RAMB_START_BASE_CNTL_R;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

823

uint32_t DWB_OGAM_RAMB_START_SLOPE_CNTL_R;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

824

uint32_t DWB_OGAM_RAMB_END_CNTL1_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

825

uint32_t DWB_OGAM_RAMB_END_CNTL2_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

826

uint32_t DWB_OGAM_RAMB_END_CNTL1_G;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

827

uint32_t DWB_OGAM_RAMB_END_CNTL2_G;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

828

uint32_t DWB_OGAM_RAMB_END_CNTL1_R;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

829

uint32_t DWB_OGAM_RAMB_END_CNTL2_R;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

830

uint32_t DWB_OGAM_RAMB_OFFSET_B;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

831

uint32_t DWB_OGAM_RAMB_OFFSET_G;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

832

uint32_t DWB_OGAM_RAMB_OFFSET_R;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

833

uint32_t DWB_OGAM_RAMB_REGION_0_1;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

834

uint32_t DWB_OGAM_RAMB_REGION_2_3;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

835

uint32_t DWB_OGAM_RAMB_REGION_4_5;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

836

uint32_t DWB_OGAM_RAMB_REGION_6_7;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

837

uint32_t DWB_OGAM_RAMB_REGION_8_9;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

838

uint32_t DWB_OGAM_RAMB_REGION_10_11;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

839

uint32_t DWB_OGAM_RAMB_REGION_12_13;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

840

uint32_t DWB_OGAM_RAMB_REGION_14_15;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

841

uint32_t DWB_OGAM_RAMB_REGION_16_17;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

842

uint32_t DWB_OGAM_RAMB_REGION_18_19;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

843

uint32_t DWB_OGAM_RAMB_REGION_20_21;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

844

uint32_t DWB_OGAM_RAMB_REGION_22_23;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

845

uint32_t DWB_OGAM_RAMB_REGION_24_25;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

846

uint32_t DWB_OGAM_RAMB_REGION_26_27;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

847

uint32_t DWB_OGAM_RAMB_REGION_28_29;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

848

uint32_t DWB_OGAM_RAMB_REGION_30_31;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

849

uint32_t DWB_OGAM_RAMB_REGION_32_33;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

850

uint32_t DWBCP_DEBUG;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

851

uint32_t DWBCP_TEST_DEBUG_INDEX;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

852

uint32_t DWBCP_TEST_DEBUG_DATA;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

863

DWBC_REG_FIELD_LIST_DCN3_0(uint32_t);

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

150

uint32_t state_mode;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

151

uint32_t ram_select;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

188

uint32_t num)

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

190

uint32_t i;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

192

uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

193

uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;

sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

194

uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;

sys/dev/pci/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.h

45

DWBC_REG_FIELD_LIST_DCN3_5(uint32_t);

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

114

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

137

static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

183

uint32_t en,

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

40

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

41

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c

43

uint32_t *en)

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

131

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

154

static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

205

uint32_t en,

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

62

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

63

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

65

uint32_t *en)

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

118

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

141

static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

212

uint32_t en,

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

44

static uint32_t index_from_vector(

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

45

uint32_t vector)

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

47

uint32_t result = 0;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

48

uint32_t mask = 1;

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

64

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

65

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c

67

uint32_t *en)

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

118

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

141

static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

212

uint32_t en,

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

44

static uint32_t index_from_vector(

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

45

uint32_t vector)

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

47

uint32_t result = 0;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

48

uint32_t mask = 1;

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

64

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

65

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c

67

uint32_t *en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

151

static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

163

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

186

static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

205

uint32_t en,

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

62

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

63

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

65

uint32_t *en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

183

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

206

static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

216

static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

194

uint32_t en,

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

66

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

67

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

69

uint32_t *en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

159

static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

171

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

194

static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

190

uint32_t en,

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

65

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

66

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

68

uint32_t *en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

190

static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

202

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

225

static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

201

uint32_t en,

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

73

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

74

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

76

uint32_t *en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

180

static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

192

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

215

static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

191

uint32_t en,

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

66

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

67

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

69

uint32_t *en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

192

static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

204

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

227

static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

172

uint32_t en,

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

64

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

65

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

67

uint32_t *en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

184

static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

196

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

219

static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

156

uint32_t en,

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

39

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

40

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

42

uint32_t *en)

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

125

uint32_t ddc_setup;

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

126

uint32_t phy_aux_cntl;

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

127

uint32_t dc_gpio_aux_ctrl_5;

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

132

uint32_t DC_I2C_DDC1_ENABLE;

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

133

uint32_t DC_I2C_DDC1_EDID_DETECT_ENABLE;

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

134

uint32_t DC_I2C_DDC1_EDID_DETECT_MODE;

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

136

uint32_t DC_GPIO_DDC1DATA_PD_EN;

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

137

uint32_t DC_GPIO_DDC1CLK_PD_EN;

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

138

uint32_t AUX_PAD1_MODE;

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

140

uint32_t DC_GPIO_SDA_PD_DIS;

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

141

uint32_t DC_GPIO_SCL_PD_DIS;

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

143

uint32_t AUX_PAD_RXSEL;

sys/dev/pci/drm/amd/display/dc/gpio/ddc_regs.h

144

uint32_t DDC_PAD_I2CMODE;

sys/dev/pci/drm/amd/display/dc/gpio/generic_regs.h

54

uint32_t mux;

sys/dev/pci/drm/amd/display/dc/gpio/generic_regs.h

59

uint32_t GENERIC_EN;

sys/dev/pci/drm/amd/display/dc/gpio/generic_regs.h

61

uint32_t GENERIC_SEL;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_base.c

138

uint32_t dal_gpio_get_enum(

sys/dev/pci/drm/amd/display/dc/gpio/gpio_base.c

270

uint32_t en,

sys/dev/pci/drm/amd/display/dc/gpio/gpio_base.c

80

uint32_t *value)

sys/dev/pci/drm/amd/display/dc/gpio/gpio_base.c

92

uint32_t value)

sys/dev/pci/drm/amd/display/dc/gpio/gpio_regs.h

30

uint32_t MASK_reg;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_regs.h

31

uint32_t MASK_mask;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_regs.h

32

uint32_t MASK_shift;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_regs.h

33

uint32_t A_reg;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_regs.h

34

uint32_t A_mask;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_regs.h

35

uint32_t A_shift;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_regs.h

36

uint32_t EN_reg;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_regs.h

37

uint32_t EN_mask;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_regs.h

38

uint32_t EN_shift;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_regs.h

39

uint32_t Y_reg;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_regs.h

40

uint32_t Y_mask;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_regs.h

41

uint32_t Y_shift;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

128

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

129

uint32_t mask)

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

132

uint32_t en;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

144

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

145

uint32_t mask)

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

148

uint32_t en;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

179

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

203

uint32_t index_of_id = 0;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

240

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

251

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

262

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

273

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

287

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

303

uint32_t en = gpio->en;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

451

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

490

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

491

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

495

uint32_t en;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

86

uint32_t number_of_bits =

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.c

88

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.h

54

uint32_t en);

sys/dev/pci/drm/amd/display/dc/gpio/gpio_service.h

59

uint32_t en);

sys/dev/pci/drm/amd/display/dc/gpio/hpd_regs.h

65

uint32_t int_status;

sys/dev/pci/drm/amd/display/dc/gpio/hpd_regs.h

66

uint32_t toggle_filt_cntl;

sys/dev/pci/drm/amd/display/dc/gpio/hpd_regs.h

71

uint32_t DC_HPD_SENSE_DELAYED;

sys/dev/pci/drm/amd/display/dc/gpio/hpd_regs.h

72

uint32_t DC_HPD_SENSE;

sys/dev/pci/drm/amd/display/dc/gpio/hpd_regs.h

74

uint32_t DC_HPD_CONNECT_INT_DELAY;

sys/dev/pci/drm/amd/display/dc/gpio/hpd_regs.h

75

uint32_t DC_HPD_DISCONNECT_INT_DELAY;

sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c

110

uint32_t sda_pd_dis = 0;

sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c

111

uint32_t scl_pd_dis = 0;

sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c

218

uint32_t en,

sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c

229

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c

72

uint32_t regval;

sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c

73

uint32_t ddc_data_pd_en = 0;

sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c

74

uint32_t ddc_clk_pd_en = 0;

sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c

75

uint32_t aux_pad_mode = 0;

sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.h

45

uint32_t en);

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.h

36

uint32_t number_of_pins[GPIO_ID_COUNT];

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.h

43

uint32_t en);

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.h

48

uint32_t en);

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.h

53

uint32_t en);

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.h

62

uint32_t en);

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.h

65

uint32_t en);

sys/dev/pci/drm/amd/display/dc/gpio/hw_factory.h

68

uint32_t en);

sys/dev/pci/drm/amd/display/dc/gpio/hw_generic.c

107

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/hw_generic.c

96

uint32_t en,

sys/dev/pci/drm/amd/display/dc/gpio/hw_generic.h

46

uint32_t en);

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.c

182

uint32_t en,

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.c

75

uint32_t *value)

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.c

97

uint32_t value)

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h

100

uint32_t en;

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h

101

uint32_t mux;

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h

115

uint32_t en,

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h

124

uint32_t *value);

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h

135

uint32_t value);

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h

35

uint32_t addr;

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h

36

uint32_t mask;

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h

42

uint32_t en;

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h

56

uint32_t *value);

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h

59

uint32_t value);

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h

98

uint32_t mask;

sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.h

99

uint32_t a;

sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.c

117

uint32_t en,

sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.c

128

uint32_t en)

sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.c

67

uint32_t *value)

sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.c

70

uint32_t hpd_delayed = 0;

sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.h

45

uint32_t en);

sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.h

31

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.h

32

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.h

34

uint32_t *en);

sys/dev/pci/drm/amd/display/dc/gpio/hw_translate.h

37

uint32_t en,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

194

static const uint32_t hdcp_dpcd_addrs[HDCP_MESSAGE_ID_MAX] = {

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

231

uint32_t length,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

233

uint32_t dpcd_addr,

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

237

uint32_t cur_length = 0;

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

238

uint32_t offset = 0;

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

239

uint32_t ksv_read_size = 0x6803b - 0x6802c;

sys/dev/pci/drm/amd/display/dc/hdcp/hdcp_msg.c

388

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

267

uint32_t *src,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

268

uint32_t *slots)

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

287

uint32_t slots = 0;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

288

uint32_t src = 0;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

385

uint32_t stream_encoder_inst,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

389

uint32_t x = dc_fixpt_floor(

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

391

uint32_t y = dc_fixpt_ceil(

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

443

uint32_t dp_alt_mode_disable = 0;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

465

MODE, (uint32_t *)&state->link_mode);

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

54

uint32_t dp_link_enabled;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

613

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

94

uint32_t tp_custom;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

100

uint32_t DP_DPHY_SYM32_SAT_UPDATE

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

104

uint32_t RDPCSTX_PHY_CNTL6[5];

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

173

DCN3_1_HPO_DP_LINK_ENC_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

185

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

217

uint32_t stream_encoder_inst,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

232

uint32_t *src,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

233

uint32_t *slots);

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

72

uint32_t DP_LINK_ENC_CLOCK_CONTROL;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

73

uint32_t DP_DPHY_SYM32_CONTROL;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

74

uint32_t DP_DPHY_SYM32_STATUS;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

75

uint32_t DP_DPHY_SYM32_TP_CONFIG;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

76

uint32_t DP_DPHY_SYM32_TP_PRBS_SEED0;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

77

uint32_t DP_DPHY_SYM32_TP_PRBS_SEED1;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

78

uint32_t DP_DPHY_SYM32_TP_PRBS_SEED2;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

79

uint32_t DP_DPHY_SYM32_TP_PRBS_SEED3;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

80

uint32_t DP_DPHY_SYM32_TP_SQ_PULSE;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

81

uint32_t DP_DPHY_SYM32_TP_CUSTOM0;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

82

uint32_t DP_DPHY_SYM32_TP_CUSTOM1;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

83

uint32_t DP_DPHY_SYM32_TP_CUSTOM2;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

84

uint32_t DP_DPHY_SYM32_TP_CUSTOM3;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

85

uint32_t DP_DPHY_SYM32_TP_CUSTOM4;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

86

uint32_t DP_DPHY_SYM32_TP_CUSTOM5;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

87

uint32_t DP_DPHY_SYM32_TP_CUSTOM6;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

88

uint32_t DP_DPHY_SYM32_TP_CUSTOM7;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

89

uint32_t DP_DPHY_SYM32_TP_CUSTOM8;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

90

uint32_t DP_DPHY_SYM32_TP_CUSTOM9;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

91

uint32_t DP_DPHY_SYM32_TP_CUSTOM10;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

92

uint32_t DP_DPHY_SYM32_SAT_VC0;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

93

uint32_t DP_DPHY_SYM32_SAT_VC1;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

94

uint32_t DP_DPHY_SYM32_SAT_VC2;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

95

uint32_t DP_DPHY_SYM32_SAT_VC3;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

96

uint32_t DP_DPHY_SYM32_VC_RATE_CNTL0;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

97

uint32_t DP_DPHY_SYM32_VC_RATE_CNTL1;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

98

uint32_t DP_DPHY_SYM32_VC_RATE_CNTL2;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h

99

uint32_t DP_DPHY_SYM32_VC_RATE_CNTL3;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

194

uint32_t h_active_start;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

195

uint32_t v_active_start;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

196

uint32_t h_blank;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

197

uint32_t h_back_porch;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

198

uint32_t h_width;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

199

uint32_t v_height;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

455

uint32_t dmdata_packet_enabled = 0;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

511

uint32_t asp_enable = 0;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

512

uint32_t atp_enable = 0;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

513

uint32_t aip_enable = 0;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

514

uint32_t acm_enable = 0;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

531

static uint32_t hpo_dp_is_gsp_enabled(

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

535

uint32_t gsp0_enabled = 0;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

536

uint32_t gsp2_enabled = 0;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

537

uint32_t gsp3_enabled = 0;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

538

uint32_t gsp11_enabled = 0;

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

605

uint32_t stream_enc_inst,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

606

uint32_t link_enc_inst)

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

762

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

92

uint32_t stream_source)

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

100

uint32_t DP_SYM32_ENC_VID_MSA2;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

101

uint32_t DP_SYM32_ENC_VID_MSA3;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

102

uint32_t DP_SYM32_ENC_VID_MSA4;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

103

uint32_t DP_SYM32_ENC_VID_MSA5;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

104

uint32_t DP_SYM32_ENC_VID_MSA6;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

105

uint32_t DP_SYM32_ENC_VID_MSA7;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

106

uint32_t DP_SYM32_ENC_VID_MSA8;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

107

uint32_t DP_SYM32_ENC_VID_MSA_CONTROL;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

108

uint32_t DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

109

uint32_t DP_SYM32_ENC_VID_FIFO_CONTROL;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

110

uint32_t DP_SYM32_ENC_VID_STREAM_CONTROL;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

111

uint32_t DP_SYM32_ENC_VID_VBID_CONTROL;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

112

uint32_t DP_SYM32_ENC_SDP_CONTROL;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

113

uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL0;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

114

uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL2;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

115

uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL3;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

116

uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL5;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

117

uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL11;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

118

uint32_t DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

119

uint32_t DP_SYM32_ENC_SDP_AUDIO_CONTROL0;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

120

uint32_t DP_SYM32_ENC_VID_CRC_CONTROL;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

121

uint32_t DP_SYM32_ENC_HBLANK_CONTROL

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

221

DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

236

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

87

uint32_t DP_STREAM_MAPPER_CONTROL0;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

88

uint32_t DP_STREAM_MAPPER_CONTROL1;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

89

uint32_t DP_STREAM_MAPPER_CONTROL2;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

90

uint32_t DP_STREAM_MAPPER_CONTROL3;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

91

uint32_t DP_STREAM_ENC_CLOCK_CONTROL;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

92

uint32_t DP_STREAM_ENC_INPUT_MUX_CONTROL;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

93

uint32_t DP_STREAM_ENC_AUDIO_CONTROL;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

94

uint32_t DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

95

uint32_t DP_SYM32_ENC_CONTROL;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

96

uint32_t DP_SYM32_ENC_VID_PIXEL_FORMAT;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

97

uint32_t DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

98

uint32_t DP_SYM32_ENC_VID_MSA0;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h

99

uint32_t DP_SYM32_ENC_VID_MSA1;\

sys/dev/pci/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c

48

uint32_t dp_alt_mode_disable = 0;

sys/dev/pci/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c

74

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.h

60

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

107

uint32_t enable = 0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

218

static uint32_t convert_and_clamp(

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

219

uint32_t wm_ns,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

220

uint32_t refclk_mhz,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

221

uint32_t clamp_value)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

223

uint32_t ret_val = 0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

250

uint32_t prog_wm_value;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

364

uint32_t prog_wm_value;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

509

uint32_t prog_wm_value;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

686

uint32_t reset_en = reset ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

100

uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

101

uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

102

uint32_t DCHUBBUB_ARB_SAT_LEVEL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

103

uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

104

uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

105

uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

106

uint32_t DCHUBBUB_TEST_DEBUG_INDEX;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

107

uint32_t DCHUBBUB_TEST_DEBUG_DATA;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

108

uint32_t DCHUBBUB_SDPIF_FB_TOP;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

109

uint32_t DCHUBBUB_SDPIF_FB_BASE;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

110

uint32_t DCHUBBUB_SDPIF_FB_OFFSET;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

111

uint32_t DCHUBBUB_SDPIF_AGP_BASE;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

112

uint32_t DCHUBBUB_SDPIF_AGP_BOT;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

113

uint32_t DCHUBBUB_SDPIF_AGP_TOP;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

114

uint32_t DCHUBBUB_CRC_CTRL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

115

uint32_t DCHUBBUB_SOFT_RESET;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

116

uint32_t DCN_VM_FB_LOCATION_BASE;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

117

uint32_t DCN_VM_FB_LOCATION_TOP;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

118

uint32_t DCN_VM_FB_OFFSET;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

119

uint32_t DCN_VM_AGP_BOT;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

120

uint32_t DCN_VM_AGP_TOP;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

121

uint32_t DCN_VM_AGP_BASE;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

122

uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

123

uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

124

uint32_t DCN_VM_FAULT_ADDR_MSB;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

125

uint32_t DCN_VM_FAULT_ADDR_LSB;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

126

uint32_t DCN_VM_FAULT_CNTL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

127

uint32_t DCN_VM_FAULT_STATUS;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

128

uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

129

uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

130

uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

131

uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

132

uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

133

uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

134

uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

135

uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

136

uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

137

uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

138

uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

139

uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

140

uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

141

uint32_t DCHVM_CTRL0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

142

uint32_t DCHVM_MEM_CTRL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

143

uint32_t DCHVM_CLK_CTRL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

144

uint32_t DCHVM_RIOMMU_CTRL0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

145

uint32_t DCHVM_RIOMMU_STAT0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

146

uint32_t DCHUBBUB_DET0_CTRL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

147

uint32_t DCHUBBUB_DET1_CTRL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

148

uint32_t DCHUBBUB_DET2_CTRL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

149

uint32_t DCHUBBUB_DET3_CTRL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

150

uint32_t DCHUBBUB_COMPBUF_CTRL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

151

uint32_t COMPBUF_RESERVED_SPACE;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

152

uint32_t DCHUBBUB_DEBUG_CTRL_0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

153

uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

154

uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

155

uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

156

uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

157

uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

158

uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

159

uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

160

uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

161

uint32_t DCHUBBUB_ARB_USR_RETRAINING_CNTL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

162

uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

163

uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

164

uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

165

uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

166

uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

167

uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

168

uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

169

uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

170

uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

171

uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

172

uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

173

uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

174

uint32_t DCHUBBUB_ARB_MALL_CNTL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

175

uint32_t SDPIF_REQUEST_RATE_LIMIT;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

176

uint32_t DCHUBBUB_SDPIF_CFG0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

177

uint32_t DCHUBBUB_SDPIF_CFG1;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

178

uint32_t DCHUBBUB_CLOCK_CNTL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

179

uint32_t DCHUBBUB_MEM_PWR_MODE_CTRL;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

180

uint32_t DCHUBBUB_ARB_QOS_FORCE;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

181

uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

182

uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

183

uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

184

uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

185

uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

186

uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

187

uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

188

uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

189

uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

190

uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

191

uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

192

uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

193

uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

194

uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

195

uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

196

uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

197

uint32_t DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

198

uint32_t DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

199

uint32_t DCHUBBUB_ARB_FRAC_URG_BW_MALL_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

200

uint32_t DCHUBBUB_ARB_FRAC_URG_BW_MALL_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

201

uint32_t DCHUBBUB_TIMEOUT_DETECTION_CTRL1;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

202

uint32_t DCHUBBUB_TIMEOUT_DETECTION_CTRL2;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

203

uint32_t DCHUBBUB_CTRL_STATUS;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

453

DCN_HUBBUB_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

454

HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

455

HUBBUB_HVM_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

456

HUBBUB_RET_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

457

HUBBUB_REG_FIELD_LIST_DCN32(uint32_t);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

458

HUBBUB_REG_FIELD_LIST_DCN35(uint32_t);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

459

HUBBUB_REG_FIELD_LIST_DCN4_01(uint32_t);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

81

uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

82

uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

83

uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

84

uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

85

uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

86

uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

87

uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

88

uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

89

uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

90

uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

91

uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

92

uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

93

uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

94

uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

95

uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

96

uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

97

uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

98

uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

99

uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

565

uint32_t ref_div = 0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

566

uint32_t ref_en = 0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

148

uint32_t prog_wm_value;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

342

uint32_t prog_wm_value;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

495

uint32_t prog_wm_value;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

52

static uint32_t convert_and_clamp(

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

53

uint32_t wm_ns,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

54

uint32_t refclk_mhz,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

55

uint32_t clamp_value)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

57

uint32_t ret_val = 0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

686

uint32_t prog_wm_value;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

70

uint32_t riommu_active;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

382

uint32_t refclk_mhz = hubbub->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

383

uint32_t prog_wm_value = convert_and_clamp(hubbub1->watermarks.a.urgent_ns,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

405

uint32_t reg;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

443

void hubbub3_get_det_sizes(struct hubbub *hubbub, uint32_t *curr_det_sizes, uint32_t *target_det_sizes)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

461

uint32_t hubbub3_compbuf_config_error(struct hubbub *hubbub)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

464

uint32_t compbuf_config_error = 0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

49

static uint32_t convert_and_clamp(

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

50

uint32_t wm_ns,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

51

uint32_t refclk_mhz,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

52

uint32_t clamp_value)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

54

uint32_t ret_val = 0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h

137

uint32_t *curr_det_sizes,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h

138

uint32_t *target_det_sizes);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h

140

uint32_t hubbub3_compbuf_config_error(struct hubbub *hubbub);

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

155

static uint32_t convert_and_clamp(

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

156

uint32_t wm_ns,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

157

uint32_t refclk_mhz,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

158

uint32_t clamp_value)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

160

uint32_t ret_val = 0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

180

uint32_t prog_wm_value;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

370

uint32_t prog_wm_value;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

643

uint32_t prog_wm_value;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

947

uint32_t ref_div = 0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

948

uint32_t ref_en = 0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

161

static uint32_t convert_and_clamp(

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

162

uint32_t wm_ns,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

163

uint32_t refclk_mhz,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

164

uint32_t clamp_value)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

166

uint32_t ret_val = 0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

184

uint32_t prog_wm_value;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

374

uint32_t prog_wm_value;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

520

uint32_t prog_wm_value;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

673

uint32_t prog_wm_value;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

830

uint32_t reg;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

88

uint32_t request_limit = 3 * memory_channel_count * words_per_channel / 4;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

970

uint32_t refclk_mhz = hubbub->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

971

uint32_t prog_wm_value = convert_and_clamp(hubbub2->watermarks.a.urgent_ns,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

981

uint32_t prefetch_complete, mall_en;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

100

uint32_t ret_val = 0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

119

uint32_t prog_wm_value;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

263

uint32_t ref_div = 0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

264

uint32_t ref_en = 0;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

341

uint32_t reg;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

95

static uint32_t convert_and_clamp(

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

96

uint32_t wm_ns,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

97

uint32_t refclk_mhz,

sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

98

uint32_t clamp_value)

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1200

uint32_t temp;

sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

500

uint32_t reg;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

113

uint32_t blank_en = blank ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

121

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1211

uint32_t dst_x_offset;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1212

uint32_t cur_en = pos->enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1301

uint32_t clk_enable = enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1306

void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1315

uint32_t in_blank;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1405

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

170

uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

209

uint32_t mirror;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

241

uint32_t red_bar = 3;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

242

uint32_t blue_bar = 2;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

44

uint32_t blank_en = blank ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

51

uint32_t reg_val = REG_READ(DCHUBP_CNTL);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

538

uint32_t dcc_en = enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

539

uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

753

uint32_t flip_pending = 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

779

static uint32_t aperture_default_system = 1;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

780

static uint32_t context0_default_system; /* = 0;*/

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

84

uint32_t disable = disable_hubp ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

895

uint32_t aperture_low_msb, aperture_low_lsb;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

896

uint32_t aperture_high_msb, aperture_high_lsb;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

92

uint32_t hubp_underflow = 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

147

uint32_t DCHUBP_CNTL; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

148

uint32_t HUBPREQ_DEBUG_DB; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

149

uint32_t HUBPREQ_DEBUG; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

150

uint32_t DCSURF_ADDR_CONFIG; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

151

uint32_t DCSURF_TILING_CONFIG; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

152

uint32_t DCSURF_SURFACE_PITCH; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

153

uint32_t DCSURF_SURFACE_PITCH_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

154

uint32_t DCSURF_SURFACE_CONFIG; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

155

uint32_t DCSURF_FLIP_CONTROL; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

156

uint32_t DCSURF_PRI_VIEWPORT_DIMENSION; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

157

uint32_t DCSURF_PRI_VIEWPORT_START; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

158

uint32_t DCSURF_SEC_VIEWPORT_DIMENSION; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

159

uint32_t DCSURF_SEC_VIEWPORT_START; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

160

uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

161

uint32_t DCSURF_PRI_VIEWPORT_START_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

162

uint32_t DCSURF_SEC_VIEWPORT_DIMENSION_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

163

uint32_t DCSURF_SEC_VIEWPORT_START_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

164

uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

165

uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

166

uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

167

uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

168

uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

169

uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

170

uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

171

uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

172

uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

173

uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

174

uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

175

uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

176

uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

177

uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

178

uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

179

uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

180

uint32_t DCSURF_SURFACE_INUSE; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

181

uint32_t DCSURF_SURFACE_INUSE_HIGH; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

182

uint32_t DCSURF_SURFACE_INUSE_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

183

uint32_t DCSURF_SURFACE_INUSE_HIGH_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

184

uint32_t DCSURF_SURFACE_EARLIEST_INUSE; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

185

uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

186

uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

187

uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

188

uint32_t DCSURF_SURFACE_CONTROL; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

189

uint32_t DCSURF_SURFACE_FLIP_INTERRUPT; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

190

uint32_t HUBPRET_CONTROL; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

191

uint32_t HUBPRET_READ_LINE_STATUS; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

192

uint32_t DCN_EXPANSION_MODE; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

193

uint32_t DCHUBP_REQ_SIZE_CONFIG; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

194

uint32_t DCHUBP_REQ_SIZE_CONFIG_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

195

uint32_t BLANK_OFFSET_0; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

196

uint32_t BLANK_OFFSET_1; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

197

uint32_t DST_DIMENSIONS; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

198

uint32_t DST_AFTER_SCALER; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

199

uint32_t PREFETCH_SETTINS; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

200

uint32_t PREFETCH_SETTINGS; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

201

uint32_t VBLANK_PARAMETERS_0; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

202

uint32_t REF_FREQ_TO_PIX_FREQ; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

203

uint32_t VBLANK_PARAMETERS_1; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

204

uint32_t VBLANK_PARAMETERS_3; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

205

uint32_t NOM_PARAMETERS_0; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

206

uint32_t NOM_PARAMETERS_1; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

207

uint32_t NOM_PARAMETERS_4; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

208

uint32_t NOM_PARAMETERS_5; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

209

uint32_t PER_LINE_DELIVERY_PRE; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

210

uint32_t PER_LINE_DELIVERY; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

211

uint32_t PREFETCH_SETTINS_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

212

uint32_t PREFETCH_SETTINGS_C; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

213

uint32_t VBLANK_PARAMETERS_2; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

214

uint32_t VBLANK_PARAMETERS_4; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

215

uint32_t NOM_PARAMETERS_2; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

216

uint32_t NOM_PARAMETERS_3; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

217

uint32_t NOM_PARAMETERS_6; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

218

uint32_t NOM_PARAMETERS_7; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

219

uint32_t DCN_TTU_QOS_WM; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

220

uint32_t DCN_GLOBAL_TTU_CNTL; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

221

uint32_t DCN_SURF0_TTU_CNTL0; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

222

uint32_t DCN_SURF0_TTU_CNTL1; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

223

uint32_t DCN_SURF1_TTU_CNTL0; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

224

uint32_t DCN_SURF1_TTU_CNTL1; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

225

uint32_t DCN_CUR0_TTU_CNTL0; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

226

uint32_t DCN_CUR0_TTU_CNTL1; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

227

uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

228

uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

229

uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

230

uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

231

uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

232

uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

233

uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

234

uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

235

uint32_t DCN_VM_MX_L1_TLB_CNTL; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

236

uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

237

uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

238

uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

239

uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

240

uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

241

uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

242

uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

243

uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

244

uint32_t CURSOR_SETTINS; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

245

uint32_t CURSOR_SETTINGS; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

246

uint32_t CURSOR_SURFACE_ADDRESS_HIGH; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

247

uint32_t CURSOR_SURFACE_ADDRESS; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

248

uint32_t CURSOR_SIZE; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

249

uint32_t CURSOR_CONTROL; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

250

uint32_t CURSOR_POSITION; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

251

uint32_t CURSOR_HOT_SPOT; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

252

uint32_t CURSOR_DST_OFFSET; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

253

uint32_t HUBP_CLK_CNTL; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

254

uint32_t HUBPRET_READ_LINE_VALUE

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

670

DCN_HUBP_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

674

uint32_t lut_enable;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

675

uint32_t lut_done;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

676

uint32_t lut_addr_mode;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

677

uint32_t lut_width;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

678

uint32_t lut_mpc_width;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

679

uint32_t lut_tmz;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

680

uint32_t lut_crossbar_sel_r;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

681

uint32_t lut_crossbar_sel_g;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

682

uint32_t lut_crossbar_sel_b;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

683

uint32_t lut_addr_hi;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

684

uint32_t lut_addr_lo;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

685

uint32_t refcyc_3dlut_group;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

686

uint32_t lut_fl_bias;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

687

uint32_t lut_fl_scale;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

688

uint32_t lut_fl_mode;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

689

uint32_t lut_fl_format;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

697

uint32_t pixel_format;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

698

uint32_t inuse_addr_hi;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

699

uint32_t inuse_addr_lo;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

700

uint32_t viewport_width;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

701

uint32_t viewport_height;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

702

uint32_t rotation_angle;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

703

uint32_t h_mirror_en;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

704

uint32_t sw_mode;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

705

uint32_t dcc_en;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

706

uint32_t blank_en;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

707

uint32_t clock_en;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

708

uint32_t underflow_status;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

709

uint32_t ttu_disable;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

710

uint32_t min_ttu_vblank;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

711

uint32_t qos_level_low_wm;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

712

uint32_t qos_level_high_wm;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

713

uint32_t primary_surface_addr_lo;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

714

uint32_t primary_surface_addr_hi;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

715

uint32_t primary_meta_addr_lo;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

716

uint32_t primary_meta_addr_hi;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

717

uint32_t uclk_pstate_force;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

718

uint32_t hubp_cntl;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

719

uint32_t flip_control;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

798

void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

803

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1001

uint32_t dst_x_offset;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1002

uint32_t cur_en = pos->enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1112

uint32_t clk_enable = enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1117

void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1703

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

175

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

335

uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

382

uint32_t mirror;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

426

uint32_t dcc_en = enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

427

uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

442

uint32_t red_bar = 3;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

443

uint32_t blue_bar = 2;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

706

uint32_t dmdata_sw_size,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

707

const uint32_t *dmdata_sw_data)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

719

uint32_t status;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

894

uint32_t triple_buffer_en = 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

909

uint32_t triple_buffer_en = 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

925

uint32_t flip_pending = 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

964

uint32_t blank_en = blank ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

967

uint32_t reg_val = REG_READ(DCHUBP_CNTL);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

135

uint32_t DMDATA_ADDRESS_HIGH; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

136

uint32_t DMDATA_ADDRESS_LOW; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

137

uint32_t DMDATA_CNTL; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

138

uint32_t DMDATA_SW_CNTL; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

139

uint32_t DMDATA_QOS_CNTL; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

140

uint32_t DMDATA_SW_DATA; \

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

141

uint32_t DMDATA_STATUS;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

142

uint32_t DCSURF_FLIP_CONTROL2;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

143

uint32_t FLIP_PARAMETERS_0;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

144

uint32_t FLIP_PARAMETERS_1;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

145

uint32_t FLIP_PARAMETERS_2;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

146

uint32_t DCN_CUR1_TTU_CNTL0;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

147

uint32_t DCN_CUR1_TTU_CNTL1;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

148

uint32_t VMID_SETTINGS_0

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

153

uint32_t FLIP_PARAMETERS_3;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

154

uint32_t FLIP_PARAMETERS_4;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

155

uint32_t FLIP_PARAMETERS_5;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

156

uint32_t FLIP_PARAMETERS_6;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

157

uint32_t VBLANK_PARAMETERS_5;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

158

uint32_t VBLANK_PARAMETERS_6

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

162

uint32_t DCN_DMDATA_VM_CNTL

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

166

uint32_t DCHUBP_MALL_CONFIG;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

167

uint32_t DCHUBP_VMPG_CONFIG;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

168

uint32_t UCLK_PSTATE_FORCE

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

172

uint32_t _3DLUT_FL_BIAS_SCALE;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

173

uint32_t _3DLUT_FL_CONFIG;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

174

uint32_t HUBP_3DLUT_ADDRESS_HIGH;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

175

uint32_t HUBP_3DLUT_ADDRESS_LOW;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

176

uint32_t HUBP_3DLUT_CONTROL;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

177

uint32_t HUBP_3DLUT_DLG_PARAM;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

178

uint32_t DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

179

uint32_t DCHUBP_MCACHEID_CONFIG

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

296

DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

310

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

340

uint32_t dmdata_sw_size,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

341

const uint32_t *dmdata_sw_data);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

404

void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst);

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

141

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

113

DCN201_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

127

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

84

uint32_t refcyc_per_vm_group_vblank;

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

849

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

85

uint32_t refcyc_per_vm_req_vblank;

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

86

uint32_t refcyc_per_vm_group_flip;

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

87

uint32_t refcyc_per_vm_req_flip;

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

88

const uint32_t uninitialized_hw_default = 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

117

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

356

uint32_t dcc_en = enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

508

uint32_t hubp3_get_current_read_line(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

510

uint32_t read_line = 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

522

uint32_t hubp_underflow = 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

568

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

252

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

303

uint32_t hubp3_get_current_read_line(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

305

uint32_t hubp3_get_underflow_status(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

121

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

71

uint32_t hubp31_get_det_config_error(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

73

uint32_t config_error = 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

239

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

251

uint32_t hubp31_get_det_config_error(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

118

uint32_t cursor_width = ((attr->width + 63) / 64) * 64;

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

119

uint32_t cursor_height = attr->height;

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

120

uint32_t cursor_size = cursor_width * cursor_height;

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

217

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

59

void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor)

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

88

uint32_t reg_val;

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

51

void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

65

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

229

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

62

uint32_t green_bar = 1;

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

63

uint32_t red_bar = 3;

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

64

uint32_t blue_bar = 2;

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

47

DCN35_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

54

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1082

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

136

uint32_t mpc_width = {(cfg->width == 17) ? 0 : 1};

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

137

uint32_t width = {cfg->width};

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

167

void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

196

uint32_t reg_value = 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

602

uint32_t pitch, pitch_c;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

723

uint32_t in_blank;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

743

uint32_t cur_en = pos->enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

259

void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

320

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

101

uint32_t feedthrough = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

102

uint32_t blnd_mode = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

103

uint32_t multiplied_mode = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

104

uint32_t alpha_mode = 2;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

184

uint32_t rate_source = clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

194

uint32_t rate_source = clk_src->id - CLOCK_SOURCE_ID_PLL0;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

51

uint32_t lock_val = lock ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

52

uint32_t dcp_grph, scl, blnd, update_lock_mode, val;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

82

uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]);

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1259

HWSEQ_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1260

HWSEQ_DCN_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1261

HWSEQ_DCN3_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1262

HWSEQ_DCN301_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1263

HWSEQ_DCN31_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1264

HWSEQ_DCN35_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1265

HWSEQ_DCN401_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

574

uint32_t DCFE_CLOCK_CONTROL[6];

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

575

uint32_t DCFEV_CLOCK_CONTROL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

576

uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

577

uint32_t BLND_V_UPDATE_LOCK[6];

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

578

uint32_t BLND_CONTROL[6];

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

579

uint32_t BLNDV_CONTROL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

580

uint32_t CRTC_H_BLANK_START_END[6];

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

581

uint32_t PIXEL_RATE_CNTL[6];

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

582

uint32_t PHYPLL_PIXEL_RATE_CNTL[6];

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

584

uint32_t DCHUB_FB_LOCATION;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

585

uint32_t DCHUB_AGP_BASE;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

586

uint32_t DCHUB_AGP_BOT;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

587

uint32_t DCHUB_AGP_TOP;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

589

uint32_t REFCLK_CNTL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

591

uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

592

uint32_t DCHUBBUB_SDPIF_FB_BASE;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

593

uint32_t DCHUBBUB_SDPIF_FB_OFFSET;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

594

uint32_t DCHUBBUB_SDPIF_AGP_BASE;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

595

uint32_t DCHUBBUB_SDPIF_AGP_BOT;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

596

uint32_t DCHUBBUB_SDPIF_AGP_TOP;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

597

uint32_t DC_IP_REQUEST_CNTL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

598

uint32_t DOMAIN0_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

599

uint32_t DOMAIN1_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

600

uint32_t DOMAIN2_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

601

uint32_t DOMAIN3_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

602

uint32_t DOMAIN4_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

603

uint32_t DOMAIN5_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

604

uint32_t DOMAIN6_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

605

uint32_t DOMAIN7_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

606

uint32_t DOMAIN8_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

607

uint32_t DOMAIN9_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

608

uint32_t DOMAIN10_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

609

uint32_t DOMAIN11_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

610

uint32_t DOMAIN16_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

611

uint32_t DOMAIN17_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

612

uint32_t DOMAIN18_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

613

uint32_t DOMAIN19_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

614

uint32_t DOMAIN20_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

615

uint32_t DOMAIN21_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

616

uint32_t DOMAIN0_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

617

uint32_t DOMAIN1_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

618

uint32_t DOMAIN2_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

619

uint32_t DOMAIN3_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

620

uint32_t DOMAIN4_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

621

uint32_t DOMAIN5_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

622

uint32_t DOMAIN6_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

623

uint32_t DOMAIN7_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

624

uint32_t DOMAIN8_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

625

uint32_t DOMAIN9_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

626

uint32_t DOMAIN10_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

627

uint32_t DOMAIN11_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

628

uint32_t DOMAIN16_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

629

uint32_t DOMAIN17_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

630

uint32_t DOMAIN18_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

631

uint32_t DOMAIN19_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

632

uint32_t DOMAIN20_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

633

uint32_t DOMAIN21_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

634

uint32_t DIO_MEM_PWR_CTRL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

635

uint32_t DCCG_GATE_DISABLE_CNTL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

636

uint32_t DCCG_GATE_DISABLE_CNTL2;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

637

uint32_t DCFCLK_CNTL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

638

uint32_t MICROSECOND_TIME_BASE_DIV;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

639

uint32_t MILLISECOND_TIME_BASE_DIV;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

640

uint32_t DISPCLK_FREQ_CHANGE_CNTL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

641

uint32_t RBBMIF_TIMEOUT_DIS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

642

uint32_t RBBMIF_TIMEOUT_DIS_2;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

643

uint32_t DCHUBBUB_CRC_CTRL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

644

uint32_t DPP_TOP0_DPP_CRC_CTRL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

645

uint32_t DPP_TOP0_DPP_CRC_VAL_R_G;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

646

uint32_t DPP_TOP0_DPP_CRC_VAL_B_A;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

647

uint32_t DPP_TOP0_DPP_CRC_VAL_R;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

648

uint32_t DPP_TOP0_DPP_CRC_VAL_G;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

649

uint32_t DPP_TOP0_DPP_CRC_VAL_B;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

650

uint32_t DPP_TOP0_DPP_CRC_VAL_A;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

651

uint32_t MPC_CRC_CTRL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

652

uint32_t MPC_CRC_RESULT_GB;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

653

uint32_t MPC_CRC_RESULT_C;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

654

uint32_t MPC_CRC_RESULT_AR;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

655

uint32_t MPC_CRC_RESULT_R;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

656

uint32_t MPC_CRC_RESULT_G;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

657

uint32_t MPC_CRC_RESULT_B;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

658

uint32_t MPC_CRC_RESULT_A;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

659

uint32_t D1VGA_CONTROL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

660

uint32_t D2VGA_CONTROL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

661

uint32_t D3VGA_CONTROL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

662

uint32_t D4VGA_CONTROL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

663

uint32_t D5VGA_CONTROL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

664

uint32_t D6VGA_CONTROL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

665

uint32_t VGA_TEST_CONTROL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

667

uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

668

uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

669

uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

670

uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

671

uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

672

uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

673

uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

674

uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

675

uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

676

uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

677

uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

678

uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

679

uint32_t MC_VM_XGMI_LFB_CNTL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

680

uint32_t AZALIA_AUDIO_DTO;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

681

uint32_t AZALIA_CONTROLLER_CLOCK_GATING;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

683

uint32_t MC_VM_FB_LOCATION_BASE;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

684

uint32_t MC_VM_FB_LOCATION_TOP;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

685

uint32_t MC_VM_FB_OFFSET;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

686

uint32_t MMHUBBUB_MEM_PWR_CNTL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

687

uint32_t HPO_TOP_CLOCK_CONTROL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

688

uint32_t ODM_MEM_PWR_CTRL3;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

689

uint32_t DMU_MEM_PWR_CNTL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

690

uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

691

uint32_t HPO_TOP_HW_CONTROL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

692

uint32_t DMU_CLK_CNTL;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

693

uint32_t DCCG_GATE_DISABLE_CNTL4;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

694

uint32_t DCCG_GATE_DISABLE_CNTL5;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

695

uint32_t DOMAIN22_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

696

uint32_t DOMAIN23_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

697

uint32_t DOMAIN24_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

698

uint32_t DOMAIN25_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

699

uint32_t DOMAIN22_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

700

uint32_t DOMAIN23_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

701

uint32_t DOMAIN24_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.h

702

uint32_t DOMAIN25_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

39

uint32_t blnd;

sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

40

uint32_t crtc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

101

uint32_t crtc;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1331

uint32_t h_active = crtc_timing->h_addressable + crtc_timing->h_border_left

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1333

uint32_t h_blank = crtc_timing->h_total - h_active;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1335

uint32_t bpp;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

134

uint32_t addr;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

135

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

136

uint32_t chunk_int = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

137

uint32_t chunk_mul = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2030

static uint32_t compute_pstate_blackout_duration(

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2034

uint32_t total_dest_line_time_ns;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2035

uint32_t pstate_blackout_duration_ns;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2056

uint32_t total_dest_line_time_ns;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2201

uint32_t *pipe_idx)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2203

uint32_t i;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2268

uint32_t pipe_idx = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2691

const uint32_t frames_to_wait_on_triggered_reset = 10;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2692

uint32_t i;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2816

uint32_t backlight = MAX_BACKLIGHT_LEVEL;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2817

uint32_t user_level = MAX_BACKLIGHT_LEVEL;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3187

uint32_t backlight_pwm_u16_16 = backlight_level_params->backlight_pwm_u16_16;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3188

uint32_t frame_ramp = backlight_level_params->frame_ramp;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3198

uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3236

uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3245

uint32_t pixel_clock)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3259

uint32_t pixel_clock)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

332

uint32_t hw_points_num)

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

338

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

449

uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

671

uint32_t active_total_with_borders;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

672

uint32_t early_control = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

717

uint32_t time_elapsed = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

718

uint32_t timeout = power_up ?

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

759

uint32_t detected = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

100

uint32_t pixel_clock);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

106

uint32_t pixel_clock);

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

38

uint32_t crtc;

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

71

uint32_t addr;

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

72

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

73

uint32_t chunk_int = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

74

uint32_t chunk_mul = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

253

uint32_t pf_max_region;

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

51

uint32_t crtc;

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

86

uint32_t addr;

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

87

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

88

uint32_t chunk_int = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

89

uint32_t chunk_mul = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

118

uint32_t pipe_idx = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

200

uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

52

uint32_t *pipe_idx)

sys/dev/pci/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

54

uint32_t i;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

106

uint32_t vupdate_start, vupdate_end, vblank_start;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1718

uint32_t num_opps = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1719

uint32_t opp_id_src0 = OPP_ID_INVALID;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1720

uint32_t opp_id_src1 = OPP_ID_INVALID;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1729

uint32_t optc_dsc_state = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1767

uint32_t backlight = MAX_BACKLIGHT_LEVEL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1768

uint32_t user_level = MAX_BACKLIGHT_LEVEL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

179

uint32_t vupdate_start, vupdate_end;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2085

const struct dc_transfer_func *tf, uint32_t hw_points_num)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2194

uint32_t vupdate_start, vupdate_end;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2274

const uint32_t frames_to_wait_on_triggered_reset = 10;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2332

uint32_t num_remainder, denom_remainder;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2355

uint32_t master_pipe_refresh_rate =

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2365

uint32_t clock_divider = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2366

uint32_t numpipes = 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2393

uint32_t embedded_pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2396

uint32_t dp_ref_clk_100hz =

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2652

uint32_t logical_addr_low;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2653

uint32_t logical_addr_high;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2678

uint32_t fb_base_value;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2679

uint32_t fb_offset_value;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3186

uint32_t hw_mult = 0x1f000; // 1.0 default multiplier

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

343

uint32_t values[] = {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3741

pos_cpy.x = (uint32_t)x_pos;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3742

pos_cpy.y = (uint32_t)y_pos;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3769

uint32_t temp_x = pos_cpy.x;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3777

uint32_t temp_y = pos_cpy.y;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3875

uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3878

uint32_t hw_scale = 0x3c00; // 1.0 default multiplier

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3947

uint32_t *start_line,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3948

uint32_t *end_line)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3963

uint32_t *start_line,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3964

uint32_t *end_line)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3994

uint32_t start_line = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3995

uint32_t end_line = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4053

uint32_t clk_khz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4054

uint32_t stepping)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

566

uint32_t values[] = {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

86

uint32_t ref_cycle)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

88

const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

899

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

90

uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

900

uint32_t pwr_status = power_on ? PGFSM_POWER_ON : PGFSM_POWER_OFF;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

960

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

961

uint32_t pwr_status = power_on ? PGFSM_POWER_ON : PGFSM_POWER_OFF;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

191

uint32_t clk_khz,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

192

uint32_t stepping);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

40

uint32_t *start_line,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

41

uint32_t *end_line);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1284

uint32_t org_ip_request_cntl = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3025

uint32_t active_total_with_borders;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3026

uint32_t early_control = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

312

uint32_t org_ip_request_cntl = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

414

uint32_t num_opps, opp_id_src0, opp_id_src1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

415

uint32_t otg_active_width = 0, otg_active_height = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

479

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

480

uint32_t pwr_status = power_on ? 0 : 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

481

uint32_t org_ip_request_cntl = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

556

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

557

uint32_t pwr_status = power_on ? 0 : 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

638

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

639

uint32_t pwr_status = power_on ? 0 : 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

172

uint32_t num_opps, opp_id_src0, opp_id_src1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

173

uint32_t otg_active_width = 0, otg_active_height = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

204

uint32_t fb_base = REG_READ(MC_VM_FB_LOCATION_BASE);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

205

uint32_t fb_top = REG_READ(MC_VM_FB_LOCATION_TOP);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

206

uint32_t fb_offset = REG_READ(MC_VM_FB_OFFSET);

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

140

bool dcn21_dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

141

uint32_t option, uint32_t panel_inst, uint32_t pwrseq_inst)

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

162

static void dmub_abm_set_backlight(struct dc_context *dc, uint32_t backlight_pwm_u16_16,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

163

uint32_t frame_ramp, uint32_t panel_inst)

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

182

uint32_t otg_inst = pipe_ctx->stream_res.tg->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

218

uint32_t otg_inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

251

uint32_t otg_inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

252

uint32_t backlight_pwm_u16_16 = backlight_level_params->backlight_pwm_u16_16;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

253

uint32_t frame_ramp = backlight_level_params->frame_ramp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

55

uint32_t page_table_base_hi;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

56

uint32_t page_table_base_lo;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

91

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

50

bool dcn21_dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

51

uint32_t option, uint32_t panel_inst, uint32_t pwrseq_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1144

uint32_t i;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1240

uint32_t v_blank_start = 0, v_blank_end = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

646

uint32_t backlight = MAX_BACKLIGHT_LEVEL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

647

uint32_t user_level = MAX_BACKLIGHT_LEVEL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

912

uint32_t tmr_delay = 0, tmr_scale = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

104

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

105

uint32_t pwr_status = power_on ? 0 : 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

161

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

162

uint32_t pwr_status = power_on ? 0 : 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

163

uint32_t org_ip_request_cntl = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

47

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

48

uint32_t pwr_status = power_on ? 0 : 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

115

uint32_t backlight = MAX_BACKLIGHT_LEVEL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

116

uint32_t user_level = MAX_BACKLIGHT_LEVEL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

196

uint32_t num_opps, opp_id_src0, opp_id_src1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

286

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

287

uint32_t pwr_status = power_on ? 0 : 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

288

uint32_t org_ip_request_cntl = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

350

uint32_t org_ip_request_cntl = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

450

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

451

uint32_t pwr_status = power_on ? 0 : 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

452

uint32_t org_ip_request_cntl;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

685

struct set_backlight_level_params *backlight_level_params, uint32_t panel_inst)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

714

uint32_t otg_inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

229

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

230

uint32_t pwr_status = power_on ? 0 : 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

231

uint32_t org_ip_request_cntl = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

298

uint32_t org_ip_request_cntl = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

547

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

548

uint32_t pwr_status = power_on ? 0 : 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

138

uint32_t org_ip_request_cntl = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1432

uint32_t i;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1485

uint32_t pwr_status = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1640

uint32_t num_opps, opp_id_src0, opp_id_src1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1641

uint32_t otg_active_width = 0, otg_active_height = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1642

uint32_t i;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

165

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

166

uint32_t pwr_status = power_on ? 0 : 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

220

static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

223

uint32_t num_ways = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

224

uint32_t mall_ss_size_bytes = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

256

uint32_t ways;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

74

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

75

uint32_t pwr_status = power_on ? 0 : 2;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

76

uint32_t org_ip_request_cntl = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

786

uint32_t backlight = MAX_BACKLIGHT_LEVEL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

787

uint32_t user_level = MAX_BACKLIGHT_LEVEL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

144

uint32_t backlight = MAX_BACKLIGHT_LEVEL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

145

uint32_t user_level = MAX_BACKLIGHT_LEVEL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1463

int num_pipes, uint32_t v_total_min, uint32_t v_total_max)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

228

uint32_t num_opps, opp_id_src0, opp_id_src1;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

569

uint32_t num_active_edp = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

770

uint32_t num_opps = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

771

uint32_t opp_id_src0 = OPP_ID_INVALID;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

772

uint32_t opp_id_src1 = OPP_ID_INVALID;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

773

uint32_t optc_dsc_state = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

98

int num_pipes, uint32_t v_total_min, uint32_t v_total_max);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1010

void adjust_hotspot_between_slices_for_2x_magnify(uint32_t cursor_width, struct dc_cursor_position *pos_cpy)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1197

pos_cpy.x = (uint32_t)x_pos;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1198

pos_cpy.y = (uint32_t)y_pos;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1240

static uint32_t dcn401_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1244

uint32_t mall_ss_size_bytes = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

144

uint32_t backlight = MAX_BACKLIGHT_LEVEL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

145

uint32_t user_level = MAX_BACKLIGHT_LEVEL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2654

uint32_t org_ip_request_cntl = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

914

uint32_t *early_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

921

uint32_t active_total_with_borders;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

949

uint32_t early_control = 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

27

uint32_t desire_pwr_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

31

uint32_t current_pwr_state;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

85

void adjust_hotspot_between_slices_for_2x_magnify(uint32_t cursor_width, struct dc_cursor_position *pos_cpy);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

267

uint32_t *start_line,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

268

uint32_t *end_line);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

343

uint32_t clk_khz, uint32_t stepping);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

386

uint32_t pixel_clock);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

390

uint32_t pixel_clock);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

462

void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

494

uint32_t *array_size);

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

108

uint32_t actual_pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

109

uint32_t adjusted_pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

110

uint32_t calculated_pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

111

uint32_t vco_freq;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

112

uint32_t reference_freq;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

113

uint32_t reference_divider;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

114

uint32_t feedback_divider;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

115

uint32_t fract_feedback_divider;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

116

uint32_t pix_clk_post_divider;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

117

uint32_t ss_percentage;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

123

uint32_t min_pix_clk_pll_post_divider;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

124

uint32_t max_pix_clk_pll_post_divider;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

125

uint32_t min_pll_ref_divider;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

126

uint32_t max_pll_ref_divider;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

127

uint32_t min_override_input_pxl_clk_pll_freq_khz;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

130

uint32_t max_override_input_pxl_clk_pll_freq_khz;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

133

uint32_t num_fract_fb_divider_decimal_point;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

136

uint32_t num_fract_fb_divider_decimal_point_precision;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

143

uint32_t ref_freq_khz;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

144

uint32_t min_pix_clock_pll_post_divider;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

145

uint32_t max_pix_clock_pll_post_divider;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

146

uint32_t min_pll_ref_divider;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

147

uint32_t max_pll_ref_divider;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

149

uint32_t max_vco_khz;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

150

uint32_t min_vco_khz;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

151

uint32_t min_pll_input_freq_khz;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

152

uint32_t max_pll_input_freq_khz;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

154

uint32_t fract_fb_divider_decimal_points_num;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

155

uint32_t fract_fb_divider_factor;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

156

uint32_t fract_fb_divider_precision;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

157

uint32_t fract_fb_divider_precision_factor;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

169

uint32_t (*get_pix_clk_dividers)(

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

36

uint32_t percentage; /*> In unit of 0.01% or 0.001%*/

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

37

uint32_t percentage_divider; /*> 100 or 1000 */

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

38

uint32_t freq_range_khz;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

39

uint32_t modulation_freq_hz;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

45

uint32_t feedback_amount;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

46

uint32_t nfrac_amount;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

47

uint32_t ds_frac_size;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

48

uint32_t ds_frac_amount;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

57

uint32_t ENABLE_SS:1;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

58

uint32_t DISPLAY_BLANKED:1;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

59

uint32_t PROGRAM_PIXEL_CLOCK:1;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

60

uint32_t PROGRAM_ID_CLOCK:1;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

61

uint32_t SUPPORT_YCBCR420:1;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

71

uint32_t avg_dp_ref_clk_khz;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

73

uint32_t ss_percentage_on_dp_ref_clk;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

76

uint32_t ss_percentage_divider;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

81

uint32_t requested_pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

84

uint32_t requested_sym_clk; /* in KHz */

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

86

uint32_t dp_ref_clk; /* in KHz */

sys/dev/pci/drm/amd/display/dc/inc/clock_source.h

99

uint32_t dio_se_pix_per_cycle;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

100

uint32_t embedded_panel_h_size;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

101

uint32_t embedded_panel_v_size;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

102

uint32_t memory_bus_width;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

103

uint32_t banks_num;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

104

uint32_t raw_size;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

105

uint32_t channel_interleave_size;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

106

uint32_t dram_channels_num;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

108

uint32_t allocated_size;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

109

uint32_t preferred_requested_size;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

110

uint32_t lpt_channels_num;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

42

uint32_t low_part;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

50

uint32_t inst;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

51

uint32_t source_view_width;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

52

uint32_t source_view_height;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

71

uint32_t fbc_trigger);

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

76

uint32_t *fbc_mapped_crtc_id);

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

81

uint32_t attached_inst;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

85

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

87

uint32_t FBC_SUPPORT:1;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

88

uint32_t FB_POOL:1;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

89

uint32_t DYNAMIC_ALLOC:1;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

90

uint32_t LPT_SUPPORT:1;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

91

uint32_t LPT_MC_CONFIG:1;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

92

uint32_t DUMMY_BACKEND:1;

sys/dev/pci/drm/amd/display/dc/inc/compressor.h

93

uint32_t CLK_GATING_DISABLED:1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

403

uint32_t enable : 1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

404

uint32_t disable : 1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

405

uint32_t odm : 1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

406

uint32_t global_sync : 1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

407

uint32_t opp_changed : 1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

408

uint32_t tg_changed : 1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

409

uint32_t mpcc : 1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

410

uint32_t dppclk : 1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

411

uint32_t hubp_interdependent : 1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

412

uint32_t hubp_rq_dlg_ttu : 1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

413

uint32_t gamut_remap : 1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

414

uint32_t scaler : 1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

415

uint32_t viewport : 1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

416

uint32_t plane_changed : 1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

417

uint32_t det_size : 1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

418

uint32_t unbounded_req : 1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

419

uint32_t test_pattern_changed : 1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

421

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

425

uint32_t div_factor1;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

426

uint32_t div_factor2;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

442

uint32_t dsc_htotal_padding;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

443

uint32_t dsc_pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

505

uint32_t next_vupdate;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

506

uint32_t wait_frame_count;

sys/dev/pci/drm/amd/display/dc/inc/custom_float.h

37

uint32_t *result);

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

135

uint32_t percent_of_ideal_port_bw_received_after_urgent_latency;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

136

uint32_t max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

137

uint32_t max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

139

uint32_t cursor_max_outstanding_group_num;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

142

uint32_t lines_interleaved_into_lb;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

143

uint32_t low_power_tiling_mode;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

144

uint32_t chunk_width;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

145

uint32_t number_of_graphics_pipes;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

146

uint32_t number_of_underlay_pipes;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

158

uint32_t max_dmif_buffer_allocated;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

159

uint32_t graphics_dmif_size;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

160

uint32_t underlay_luma_dmif_size;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

161

uint32_t underlay_chroma_dmif_size;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

181

uint32_t scatter_gather_lines_of_pte_prefetching_in_linear_mode;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

182

uint32_t display_write_back420_luma_mcifwr_buffer_size;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

183

uint32_t display_write_back420_chroma_mcifwr_buffer_size;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

188

uint32_t scatter_gather_pte_request_rows_in_tiling_mode;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

194

uint32_t dram_channel_width_in_bits;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

195

uint32_t number_of_dram_channels;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

196

uint32_t number_of_dram_banks;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

223

uint32_t cursor_width;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

224

uint32_t average_compression_rate;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

225

uint32_t number_of_request_slots_gmc_reserves_for_dmif_per_channel;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

239

uint32_t number_of_displays;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

243

uint32_t graphics_lb_bpc;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

244

uint32_t underlay_lb_bpc;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

255

uint32_t y_clk_level;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

256

uint32_t sclk_level;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

257

uint32_t number_of_underlay_surfaces;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

258

uint32_t number_of_dram_wrchannels;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

259

uint32_t chunk_request_delay;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

260

uint32_t number_of_dram_channels;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

357

uint32_t total_stutter_dmif_buffer_size;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

358

uint32_t total_bytes_requested;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

359

uint32_t min_stutter_dmif_buffer_size;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

360

uint32_t num_stutter_bursts;

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

374

uint32_t bytes_per_pixel[maximum_number_of_surfaces];

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

375

uint32_t max_chunks_non_fbc_mode[maximum_number_of_surfaces];

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

376

uint32_t lb_bpc[maximum_number_of_surfaces];

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

377

uint32_t output_bpphdmi[maximum_number_of_surfaces];

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

378

uint32_t output_bppdp4_lane_hbr[maximum_number_of_surfaces];

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

379

uint32_t output_bppdp4_lane_hbr2[maximum_number_of_surfaces];

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

380

uint32_t output_bppdp4_lane_hbr3[maximum_number_of_surfaces];

sys/dev/pci/drm/amd/display/dc/inc/dce_calcs.h

452

uint32_t num_displays_with_margin[3][8];

sys/dev/pci/drm/amd/display/dc/inc/hw/abm.h

39

void (*abm_init)(struct abm *abm, uint32_t back_light, uint32_t user_level);

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

103

uint32_t current_read_length;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

104

uint32_t offset;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

112

uint32_t timed_out_retry_aux;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

113

uint32_t invalid_reply_retry_aux;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

114

uint32_t defer_retry_aux;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

115

uint32_t defer_retry_i2c;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

116

uint32_t invalid_reply_retry_aux_on_ack;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

126

uint32_t current_write_length;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

134

uint32_t timed_out_retry_aux;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

135

uint32_t invalid_reply_retry_aux;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

136

uint32_t defer_retry_aux;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

137

uint32_t defer_retry_i2c;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

138

uint32_t max_defer_retry;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

139

uint32_t ack_m_retry;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

151

uint32_t timeout);

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

167

uint32_t size,

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

170

uint32_t *sw_status);

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

45

uint32_t address;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

46

uint32_t length;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

85

uint32_t ALLOW_AUX_WHEN_HPD_LOW:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

87

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

91

uint32_t inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

96

uint32_t delay;

sys/dev/pci/drm/amd/display/dc/inc/hw/aux_engine.h

97

uint32_t max_defer_write_retry;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

184

uint32_t dcfclk;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

185

uint32_t dcf_deep_sleep_divider;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

186

uint32_t dcf_deep_sleep_allow;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

187

uint32_t dprefclk;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

188

uint32_t dispclk;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

189

uint32_t dppclk;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

190

uint32_t dtbclk;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

191

uint32_t fclk;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

193

uint32_t dppclk_bypass;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

194

uint32_t dcfclk_bypass;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

195

uint32_t dprefclk_bypass;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

196

uint32_t dispclk_bypass;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

200

uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

201

uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

202

uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

203

uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

204

uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

206

uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

207

uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

208

uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

212

uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

213

uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

214

uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

215

uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

216

uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

217

uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

219

uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

220

uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

221

uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

222

uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

228

uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

229

uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

230

uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

231

uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

232

uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

237

uint32_t dcfclk_bypass;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

238

uint32_t dispclk_pypass;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

239

uint32_t dprefclk_bypass;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

274

uint32_t dprefclk_khz;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

340

uint32_t (*set_smartmux_switch)(struct clk_mgr *clk_mgr, uint32_t pins_to_set);

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

48

uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

49

uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

50

uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

51

uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

52

uint32_t CLK1_CLK4_CURRENT_CNT;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

53

uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

54

uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

56

uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

57

uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

58

uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

59

uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

61

uint32_t CLK4_CLK0_CURRENT_CNT; //fclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

66

uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

67

uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

68

uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

69

uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

70

uint32_t CLK1_CLK4_CURRENT_CNT; //dtbclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

73

uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

74

uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

76

uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

77

uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

78

uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

79

uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

80

uint32_t CLK1_CLK4_BYPASS_CNTL; //dtbclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

85

uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

86

uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

87

uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

88

uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

89

uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

90

uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

92

uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

93

uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

94

uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr.h

95

uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

256

uint32_t DPREFCLK_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

257

uint32_t DENTIST_DISPCLK_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

259

uint32_t CLK4_CLK2_CURRENT_CNT;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

260

uint32_t CLK4_CLK_PLL_REQ;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

262

uint32_t CLK4_CLK0_CURRENT_CNT;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

264

uint32_t CLK3_CLK2_DFS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

265

uint32_t CLK3_CLK_PLL_REQ;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

267

uint32_t CLK0_CLK2_DFS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

268

uint32_t CLK0_CLK_PLL_REQ;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

270

uint32_t CLK1_CLK_PLL_REQ;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

271

uint32_t CLK1_CLK0_DFS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

272

uint32_t CLK1_CLK1_DFS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

273

uint32_t CLK1_CLK2_DFS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

274

uint32_t CLK1_CLK3_DFS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

275

uint32_t CLK1_CLK4_DFS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

276

uint32_t CLK1_CLK5_DFS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

277

uint32_t CLK2_CLK2_DFS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

279

uint32_t CLK1_CLK0_CURRENT_CNT;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

280

uint32_t CLK1_CLK1_CURRENT_CNT;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

281

uint32_t CLK1_CLK2_CURRENT_CNT;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

282

uint32_t CLK1_CLK3_CURRENT_CNT;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

283

uint32_t CLK1_CLK4_CURRENT_CNT;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

284

uint32_t CLK1_CLK5_CURRENT_CNT;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

286

uint32_t CLK0_CLK0_DFS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

287

uint32_t CLK0_CLK1_DFS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

288

uint32_t CLK0_CLK3_DFS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

289

uint32_t CLK0_CLK4_DFS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

290

uint32_t CLK1_CLK0_BYPASS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

291

uint32_t CLK1_CLK1_BYPASS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

292

uint32_t CLK1_CLK2_BYPASS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

293

uint32_t CLK1_CLK3_BYPASS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

294

uint32_t CLK1_CLK4_BYPASS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

295

uint32_t CLK1_CLK5_BYPASS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

297

uint32_t CLK1_CLK0_DS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

298

uint32_t CLK1_CLK1_DS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

299

uint32_t CLK1_CLK2_DS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

300

uint32_t CLK1_CLK3_DS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

301

uint32_t CLK1_CLK4_DS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

302

uint32_t CLK1_CLK5_DS_CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

304

uint32_t CLK1_CLK0_ALLOW_DS;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

305

uint32_t CLK1_CLK1_ALLOW_DS;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

306

uint32_t CLK1_CLK2_ALLOW_DS;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

307

uint32_t CLK1_CLK3_ALLOW_DS;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

308

uint32_t CLK1_CLK4_ALLOW_DS;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

309

uint32_t CLK1_CLK5_ALLOW_DS;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

310

uint32_t CLK5_spll_field_8;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

311

uint32_t CLK6_spll_field_8;

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

320

CLK_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

321

CLK20_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

370

uint32_t dfs_ref_freq_khz;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

10

uint32_t reser0: 3;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

11

uint32_t cur_2x_magnify: 1;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

12

uint32_t reser1: 3;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

13

uint32_t mode: 3;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

14

uint32_t reser2: 5;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

15

uint32_t pitch: 2;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

16

uint32_t reser3: 6;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

17

uint32_t line_per_chunk: 5;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

18

uint32_t reser4: 3;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

20

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

26

uint32_t x_pos: 16;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

27

uint32_t y_pos: 16;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

29

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

33

uint32_t x_hot: 16;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

34

uint32_t y_hot: 16;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

36

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

40

uint32_t dst_x_offset: 13;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

41

uint32_t reserved: 19;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

43

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

48

uint32_t SURFACE_ADDR_HIGH;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

49

uint32_t SURFACE_ADDR;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

53

uint32_t width: 16;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

54

uint32_t height: 16;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

56

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

60

uint32_t dst_y_offset: 8;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

61

uint32_t chunk_hdl_adjust: 2;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

62

uint32_t reserved: 22;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

64

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

69

uint32_t x;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

70

uint32_t y;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

71

uint32_t w;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

72

uint32_t h;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

77

uint32_t cur0_enable: 1;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

78

uint32_t expansion_mode: 1;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

79

uint32_t reser0: 1;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

80

uint32_t cur0_rom_en: 1;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

81

uint32_t mode: 3;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

82

uint32_t reserved: 25;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

84

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/inc/hw/cursor_reg_cache.h

9

uint32_t cur_enable: 1;

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

105

uint32_t otg_inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

107

uint32_t otg_inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

175

uint32_t otg_inst,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

180

uint32_t otg_inst,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

181

uint32_t *div_factor1,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

182

uint32_t *div_factor2);

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

200

uint32_t stream_enc_inst,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

201

uint32_t link_enc_inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

205

uint32_t stream_enc_inst,

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

206

uint32_t link_enc_inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

213

uint32_t otg_inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

214

void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst, uint32_t num_slices_h);

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

215

void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h

216

void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

129

uint32_t vm_fault_addr_msb;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

130

uint32_t vm_fault_addr_lsb;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

131

uint32_t vm_error_status;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

132

uint32_t vm_error_vmid;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

133

uint32_t vm_error_pipe;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

134

uint32_t vm_error_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

135

uint32_t test_debug_data;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

136

uint32_t watermark_change_cntl;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

137

uint32_t dram_state_cntl;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

141

uint32_t max_latency_ns;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

142

uint32_t avg_latency_ns;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

143

uint32_t min_latency_ns;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

147

uint32_t refclk_mhz;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

148

uint32_t t_win_ns;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

149

uint32_t bandwidth_mbps;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

150

uint32_t bw_factor_x1000;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

245

void (*get_det_sizes)(struct hubbub *hubbub, uint32_t *curr_det_sizes, uint32_t *target_det_sizes);

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

246

uint32_t (*compbuf_config_error)(struct hubbub *hubbub);

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

249

void (*get_system_latency_result)(struct hubbub *hubbub, uint32_t refclk_mhz, struct hubbub_system_latencies *latencies);

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

251

void (*get_in_order_bandwidth_result)(struct hubbub *hubbub, uint32_t refclk_mhz, uint32_t *bandwidth_mbps);

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

253

void (*get_urgent_ramp_latency_result)(struct hubbub *hubbub, uint32_t refclk_mhz, uint32_t *latency_ns);

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

56

uint32_t wm_set;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

57

uint32_t data_urgent;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

58

uint32_t pte_meta_urgent;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

59

uint32_t sr_enter;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

60

uint32_t sr_exit;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

61

uint32_t dram_clk_change;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

62

uint32_t usr_retrain;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

63

uint32_t fclk_pstate_change;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

64

uint32_t sr_enter_exit_Z8;

sys/dev/pci/drm/amd/display/dc/inc/hw/dchubbub.h

65

uint32_t sr_enter_Z8;

sys/dev/pci/drm/amd/display/dc/inc/hw/dmcu.h

55

uint32_t psp_version;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

180

uint32_t is_enabled;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

181

uint32_t igam_lut_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

182

uint32_t igam_input_format;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

183

uint32_t dgam_lut_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

184

uint32_t rgam_lut_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

186

uint32_t gamut_remap_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

187

uint32_t gamut_remap_c11_c12;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

188

uint32_t gamut_remap_c13_c14;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

189

uint32_t gamut_remap_c21_c22;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

190

uint32_t gamut_remap_c23_c24;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

191

uint32_t gamut_remap_c31_c32;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

192

uint32_t gamut_remap_c33_c34;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

195

uint32_t shaper_lut_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

196

uint32_t lut3d_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

197

uint32_t lut3d_bit_depth;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

198

uint32_t lut3d_size;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

199

uint32_t blnd_lut_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

200

uint32_t pre_dgam_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

201

uint32_t pre_dgam_select;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

202

uint32_t gamcor_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

206

uint32_t cm_bias_cr_r;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

207

uint32_t cm_bias_y_g;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

208

uint32_t cm_bias_cb_b;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

209

uint32_t cm_bias_format;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

220

uint32_t enable, uint32_t additive_blending);

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

262

uint32_t num);

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

314

uint32_t width,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

315

uint32_t height

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

320

uint32_t multiplier);

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

66

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h

169

uint32_t mask_id;

sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h

234

struct dwbc *dwbc, uint32_t *time_stamp);

sys/dev/pci/drm/amd/display/dc/inc/hw/gpio.h

42

uint32_t en;

sys/dev/pci/drm/amd/display/dc/inc/hw/gpio.h

57

uint32_t en);

sys/dev/pci/drm/amd/display/dc/inc/hw/gpio.h

61

uint32_t en);

sys/dev/pci/drm/amd/display/dc/inc/hw/gpio.h

65

uint32_t en);

sys/dev/pci/drm/amd/display/dc/inc/hw/gpio.h

69

uint32_t en);

sys/dev/pci/drm/amd/display/dc/inc/hw/gpio.h

73

uint32_t en);

sys/dev/pci/drm/amd/display/dc/inc/hw/gpio.h

77

uint32_t en);

sys/dev/pci/drm/amd/display/dc/inc/hw/gpio.h

81

uint32_t en);

sys/dev/pci/drm/amd/display/dc/inc/hw/gpio.h

85

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/inc/hw/gpio.h

86

uint32_t mask,

sys/dev/pci/drm/amd/display/dc/inc/hw/gpio.h

88

uint32_t *en);

sys/dev/pci/drm/amd/display/dc/inc/hw/gpio.h

91

uint32_t en,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

137

uint32_t DCSURF_SURFACE_CONTROL;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

138

uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

139

uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

140

uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

141

uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

142

uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

143

uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

144

uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

145

uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

146

uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

147

uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

148

uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

149

uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

237

void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

250

uint32_t dmdata_sw_size,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

251

const uint32_t *dmdata_sw_data);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

280

void (*hubp_update_mall_sel)(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

309

uint32_t (*hubp_get_current_read_line)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

310

uint32_t (*hubp_get_det_config_error)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

101

uint32_t red;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

102

uint32_t green;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

103

uint32_t blue;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

141

uint32_t hw_points_num;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

226

uint32_t scale_red;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

227

uint32_t bias_red;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

228

uint32_t scale_green;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

229

uint32_t bias_green;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

230

uint32_t scale_blue;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

231

uint32_t bias_blue;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

359

uint32_t FL:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

360

uint32_t FR:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

361

uint32_t LFE:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

362

uint32_t FC:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

363

uint32_t RL_RC:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

364

uint32_t RR:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

365

uint32_t RC_RLC_FLC:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

366

uint32_t RRC_FRC:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

60

uint32_t offset;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

61

uint32_t segments_num;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

70

uint32_t custom_float_x;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

71

uint32_t custom_float_y;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

72

uint32_t custom_float_offset;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

73

uint32_t custom_float_slope;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

91

uint32_t red_reg;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

92

uint32_t green_reg;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

93

uint32_t blue_reg;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

95

uint32_t delta_red_reg;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

96

uint32_t delta_green_reg;

sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h

97

uint32_t delta_blue_reg;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

119

uint32_t pixel_clock);

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

128

uint32_t pixel_clock);

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

170

uint32_t hpo_inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

225

uint32_t link_enc_enabled;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

226

uint32_t link_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

227

uint32_t lane_count;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

228

uint32_t slot_count[4];

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

229

uint32_t stream_src[4];

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

230

uint32_t vc_rate_x[4];

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

231

uint32_t vc_rate_y[4];

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

270

uint32_t stream_encoder_inst,

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

57

uint32_t IS_HBR2_CAPABLE:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

58

uint32_t IS_HBR3_CAPABLE:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

59

uint32_t IS_TPS3_CAPABLE:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

60

uint32_t IS_TPS4_CAPABLE:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

61

uint32_t HDMI_6GB_EN:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

62

uint32_t IS_DP2_CAPABLE:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

63

uint32_t IS_UHBR10_CAPABLE:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

64

uint32_t IS_UHBR13_5_CAPABLE:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

65

uint32_t IS_UHBR20_CAPABLE:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

66

uint32_t DP_IS_USB_C:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

68

uint32_t raw;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

84

uint32_t output_signals;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

94

uint32_t dphy_fec_en;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

95

uint32_t dphy_fec_ready_shadow;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

96

uint32_t dphy_fec_active_status;

sys/dev/pci/drm/amd/display/dc/inc/hw/link_encoder.h

97

uint32_t dp_link_training_complete;

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

125

uint32_t total_dest_line_time_ns);

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

132

uint32_t total_dest_line_time_ns);

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

136

uint32_t h_total,/* for current target */

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

137

uint32_t v_total,/* for current target */

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

138

uint32_t pix_clk_khz,/* for current target */

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

139

uint32_t total_streams_num);

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

143

uint32_t paths_num);

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

36

uint32_t cstate_exit_ns;

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

37

uint32_t cstate_exit_z8_ns;

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

38

uint32_t cstate_enter_plus_exit_z8_ns;

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

39

uint32_t cstate_enter_plus_exit_ns;

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

40

uint32_t pstate_change_ns;

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

41

uint32_t fclk_pstate_change_ns;

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

45

uint32_t pte_meta_urgent_ns;

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

46

uint32_t urgent_ns;

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

47

uint32_t frac_urg_bw_nom;

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

48

uint32_t frac_urg_bw_flip;

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

49

uint32_t urgent_latency_ns;

sys/dev/pci/drm/amd/display/dc/inc/hw/mem_input.h

51

uint32_t usr_retraining_ns;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1079

void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1082

bool (*is_config_supported)(uint32_t width);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1103

void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1106

bool (*is_config_supported)(uint32_t width);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

1108

void (*power_on_shaper_3dlut)(struct mpc *mpc, uint32_t mpcc_id, bool power_on);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

204

uint32_t rmcm_3dlut_mem_pwr_state;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

205

uint32_t rmcm_3dlut_mem_pwr_force;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

206

uint32_t rmcm_3dlut_mem_pwr_dis;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

207

uint32_t rmcm_3dlut_mem_pwr_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

208

uint32_t rmcm_3dlut_size;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

209

uint32_t rmcm_3dlut_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

210

uint32_t rmcm_3dlut_mode_cur;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

211

uint32_t rmcm_3dlut_read_sel;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

212

uint32_t rmcm_3dlut_30bit_en;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

213

uint32_t rmcm_3dlut_wr_en_mask;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

214

uint32_t rmcm_3dlut_ram_sel;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

215

uint32_t rmcm_3dlut_out_norm_factor;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

216

uint32_t rmcm_3dlut_fl_sel;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

217

uint32_t rmcm_3dlut_out_offset_r;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

218

uint32_t rmcm_3dlut_out_scale_r;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

219

uint32_t rmcm_3dlut_fl_done;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

220

uint32_t rmcm_3dlut_fl_soft_underflow;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

221

uint32_t rmcm_3dlut_fl_hard_underflow;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

222

uint32_t rmcm_cntl;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

223

uint32_t rmcm_shaper_mem_pwr_state;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

224

uint32_t rmcm_shaper_mem_pwr_force;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

225

uint32_t rmcm_shaper_mem_pwr_dis;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

226

uint32_t rmcm_shaper_mem_pwr_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

227

uint32_t rmcm_shaper_lut_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

228

uint32_t rmcm_shaper_mode_cur;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

229

uint32_t rmcm_shaper_lut_write_en_mask;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

230

uint32_t rmcm_shaper_lut_write_sel;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

231

uint32_t rmcm_shaper_offset_b;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

232

uint32_t rmcm_shaper_scale_b;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

233

uint32_t rmcm_shaper_rama_exp_region_start_b;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

234

uint32_t rmcm_shaper_rama_exp_region_start_seg_b;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

235

uint32_t rmcm_shaper_rama_exp_region_end_b;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

236

uint32_t rmcm_shaper_rama_exp_region_end_base_b;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

334

uint32_t opp_id;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

335

uint32_t dpp_id;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

336

uint32_t bot_mpcc_id;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

337

uint32_t mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

338

uint32_t alpha_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

339

uint32_t pre_multiplied_alpha;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

340

uint32_t overlap_only;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

341

uint32_t idle;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

342

uint32_t busy;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

343

uint32_t shaper_lut_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

344

uint32_t lut3d_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

345

uint32_t lut3d_bit_depth;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

346

uint32_t lut3d_size;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

347

uint32_t rgam_mode;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

348

uint32_t rgam_lut;

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

866

uint32_t rmu_idx);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

885

uint32_t rmu_idx);

sys/dev/pci/drm/amd/display/dc/inc/hw/mpc.h

901

uint32_t (*acquire_rmu)(struct mpc *mpc, int mpcc_id, int rmu_idx);

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

100

uint32_t FRC50:2;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

101

uint32_t FRC75:2;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

104

uint32_t r_seed_value;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

105

uint32_t b_seed_value;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

106

uint32_t g_seed_value;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

146

uint32_t mantissa_bits;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

147

uint32_t exponenta_bits;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

152

uint32_t mantissa;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

153

uint32_t exponenta;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

154

uint32_t value;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

159

uint32_t custom_float_x;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

237

uint32_t inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

242

uint32_t dyn_expansion;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

270

uint32_t divider; /* (actually HW range is min/divider; divider !=0) */

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

293

uint32_t active_width;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

295

uint32_t mso_overlap_pixel_num;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

296

uint32_t pixel_repetition;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

297

uint32_t num_segment_padded_pixels;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

367

uint32_t (*opp_get_left_edge_extra_pixel_count)(

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

72

uint32_t TRUNCATE_ENABLED:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

74

uint32_t TRUNCATE_DEPTH:2;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

76

uint32_t TRUNCATE_MODE:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

80

uint32_t SPATIAL_DITHER_ENABLED:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

82

uint32_t SPATIAL_DITHER_DEPTH:2;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

84

uint32_t SPATIAL_DITHER_MODE:2;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

86

uint32_t RGB_RANDOM:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

88

uint32_t FRAME_RANDOM:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

90

uint32_t HIGHPASS_RANDOM:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

94

uint32_t FRAME_MODULATION_ENABLED:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

96

uint32_t FRAME_MODULATION_DEPTH:2;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

98

uint32_t TEMPORAL_LEVEL:1;

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

99

uint32_t FRC25:2;

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

115

uint32_t optc1_get_vblank_counter(struct timing_generator *optc);

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

118

uint32_t *v_blank_start,

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

119

uint32_t *v_blank_end,

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

120

uint32_t *h_position,

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

121

uint32_t *v_position);

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

124

uint32_t early_cntl);

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

155

uint32_t event_triggers,

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

156

uint32_t num_frames);

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

177

uint32_t *otg_active_width,

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

178

uint32_t *otg_active_height);

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

187

uint32_t *r_cr,

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

188

uint32_t *g_y,

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

189

uint32_t *b_cb);

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

54

uint32_t max_h_total;

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

55

uint32_t max_v_total;

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

57

uint32_t min_h_blank;

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

59

uint32_t min_h_sync_width;

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

60

uint32_t min_v_sync_width;

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

61

uint32_t min_v_blank;

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

62

uint32_t min_v_blank_interlace;

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

71

uint32_t max_frame_count;

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

92

uint32_t start_line,

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

93

uint32_t end_line);

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

96

uint32_t start_line);

sys/dev/pci/drm/amd/display/dc/inc/hw/optc.h

99

uint32_t start_line);

sys/dev/pci/drm/amd/display/dc/inc/hw/panel_cntl.h

48

uint32_t (*hw_init)(struct panel_cntl *panel_cntl);

sys/dev/pci/drm/amd/display/dc/inc/hw/panel_cntl.h

53

uint32_t backlight_pwm_u16_16);

sys/dev/pci/drm/amd/display/dc/inc/hw/panel_cntl.h

54

uint32_t (*get_current_backlight)(struct panel_cntl *panel_cntl);

sys/dev/pci/drm/amd/display/dc/inc/hw/panel_cntl.h

59

uint32_t inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/panel_cntl.h

60

uint32_t eng_id;

sys/dev/pci/drm/amd/display/dc/inc/hw/panel_cntl.h

66

uint32_t inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/panel_cntl.h

67

uint32_t pwrseq_inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

102

uint32_t pix_per_cycle;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

108

uint32_t custom_pattern_size;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

117

uint32_t stream_enc_inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

124

uint32_t dsc_mode; // DISABLED 0; 1 or 2 indicate enabled state.

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

125

uint32_t dsc_slice_width;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

126

uint32_t sec_gsp_pps_line_num;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

127

uint32_t vbid6_line_reference;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

128

uint32_t vbid6_line_num;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

129

uint32_t sec_gsp_pps_enable;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

130

uint32_t sec_stream_enable;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

139

uint32_t enable_sdp_splitting);

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

248

uint32_t dsc_bytes_per_pixel,

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

249

uint32_t dsc_slice_width);

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

258

uint32_t hubp_requestor_id,

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

268

uint32_t (*get_fifo_cal_average_level)(

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

276

void (*map_stream_to_link)(struct stream_encoder *enc, uint32_t stream_enc_inst, uint32_t link_enc_inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

277

uint32_t (*get_pixels_per_cycle)(struct stream_encoder *enc);

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

281

uint32_t stream_enc_enabled;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

282

uint32_t vid_stream_enabled;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

283

uint32_t otg_inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

284

uint32_t pixel_encoding;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

285

uint32_t component_depth;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

286

uint32_t compressed_format;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

287

uint32_t sdp_enabled;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

288

uint32_t mapped_to_link_enc;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

295

uint32_t inst;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

307

uint32_t stream_source);

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

342

uint32_t stream_enc_inst,

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

343

uint32_t link_enc_inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

57

uint32_t pixel_clock_in_10khz;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

59

uint32_t n_32khz;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

61

uint32_t cts_32khz;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

62

uint32_t n_44khz;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

63

uint32_t cts_44khz;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

64

uint32_t n_48khz;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

65

uint32_t cts_48khz;

sys/dev/pci/drm/amd/display/dc/inc/hw/stream_encoder.h

77

uint32_t adaptive_sync_line_num;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

150

uint32_t v_blank_start;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

151

uint32_t v_blank_end;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

152

uint32_t v_sync_a_pol;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

153

uint32_t v_total;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

154

uint32_t v_total_max;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

155

uint32_t v_total_min;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

156

uint32_t v_total_min_sel;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

157

uint32_t v_total_max_sel;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

158

uint32_t v_sync_a_start;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

159

uint32_t v_sync_a_end;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

160

uint32_t h_blank_start;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

161

uint32_t h_blank_end;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

162

uint32_t h_sync_a_start;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

163

uint32_t h_sync_a_end;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

164

uint32_t h_sync_a_pol;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

165

uint32_t h_total;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

166

uint32_t underflow_occurred_status;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

167

uint32_t otg_enabled;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

168

uint32_t blank_enabled;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

169

uint32_t vertical_interrupt1_en;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

170

uint32_t vertical_interrupt1_line;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

171

uint32_t vertical_interrupt2_en;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

172

uint32_t vertical_interrupt2_line;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

173

uint32_t vertical_interrupt2_dest;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

174

uint32_t otg_master_update_lock;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

175

uint32_t otg_double_buffer_control;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

213

uint32_t start_line,

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

214

uint32_t end_line);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

217

uint32_t start_line);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

220

uint32_t start_line);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

231

uint32_t (*get_frame_count)(struct timing_generator *tg);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

234

uint32_t *v_blank_start,

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

235

uint32_t *v_blank_end,

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

236

uint32_t *h_position,

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

237

uint32_t *v_position);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

239

uint32_t *otg_active_width,

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

240

uint32_t *otg_active_height);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

244

uint32_t early_cntl);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

277

void (*get_last_used_drr_vtotal)(struct timing_generator *optc, uint32_t *refresh_rate);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

279

uint32_t event_triggers,

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

280

uint32_t num_frames);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

307

uint32_t dwb_pipe_inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

310

uint32_t *num_of_input_segments,

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

311

uint32_t *seg0_src_sel,

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

312

uint32_t *seg1_src_sel);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

327

uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

339

uint32_t dsc_bytes_per_pixel,

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

340

uint32_t dsc_slice_width);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

342

uint32_t *dsc_mode);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

356

uint32_t gsl_ready_signal);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

359

uint32_t window_start, uint32_t window_end);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

361

uint32_t limit);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

364

uint32_t master_pixel_clock_100Hz,

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

365

uint32_t slave_pixel_clock_100Hz,

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

371

uint32_t vtotal_change_limit);

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

60

uint32_t vertical_total_min;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

61

uint32_t vertical_total_max;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

62

uint32_t vertical_total_mid;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

63

uint32_t vertical_total_mid_frame_num;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

68

uint32_t vertical_total_min;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

69

uint32_t vertical_total_max;

sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h

70

uint32_t vertical_blank_start;

sys/dev/pci/drm/amd/display/dc/inc/hw/transform.h

204

uint32_t num);

sys/dev/pci/drm/amd/display/dc/inc/hw/vmid.h

33

uint32_t CNTL;

sys/dev/pci/drm/amd/display/dc/inc/hw/vmid.h

34

uint32_t PAGE_TABLE_BASE_ADDR_HI32;

sys/dev/pci/drm/amd/display/dc/inc/hw/vmid.h

35

uint32_t PAGE_TABLE_BASE_ADDR_LO32;

sys/dev/pci/drm/amd/display/dc/inc/hw/vmid.h

36

uint32_t PAGE_TABLE_START_ADDR_HI32;

sys/dev/pci/drm/amd/display/dc/inc/hw/vmid.h

37

uint32_t PAGE_TABLE_START_ADDR_LO32;

sys/dev/pci/drm/amd/display/dc/inc/hw/vmid.h

38

uint32_t PAGE_TABLE_END_ADDR_HI32;

sys/dev/pci/drm/amd/display/dc/inc/hw/vmid.h

39

uint32_t PAGE_TABLE_END_ADDR_LO32;

sys/dev/pci/drm/amd/display/dc/inc/hw/vpg.h

36

uint32_t packet_index,

sys/dev/pci/drm/amd/display/dc/inc/link_hwss.h

84

struct audio_output *audio_output, uint32_t audio_inst);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

133

void (*get_cur_res_map)(const struct dc *dc, uint32_t *map);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

134

void (*restore_res_map)(const struct dc *dc, uint32_t *map);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

144

uint32_t (*dp_link_bandwidth_kbps)(

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

151

uint32_t (*dp_required_hblank_size_bytes)(

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

164

struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

166

struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

178

uint32_t address,

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

180

uint32_t write_size,

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

182

uint32_t read_size);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

189

uint32_t len);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

193

uint32_t (*get_aux_defer_delay)(struct ddc_service *ddc);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

216

struct dc_link_settings *link_setting, uint32_t req_bw);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

217

uint32_t (*bw_kbps_from_raw_frl_link_rate_data)(uint8_t bw);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

256

uint32_t *backlight_millinits_avg,

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

257

uint32_t *backlight_millinits_peak);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

262

uint32_t backlight_millinits,

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

263

uint32_t transition_time_in_ms);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

282

const struct dc_link *link, uint32_t *residency, enum psr_residency_mode mode);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

295

struct dc_link *link, uint32_t coasting_vtotal);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

300

const unsigned int *power_opts, uint32_t coasting_vtotal);

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

86

uint32_t connector_index; /* this will be mapped to the HPD pins */

sys/dev/pci/drm/amd/display/dc/inc/link_service.h

87

uint32_t link_index; /* this is mapped to DAL display_index

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

383

{ uint32_t val = REG_UPDATE(reg, f1, v1); \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

387

{ uint32_t val = REG_UPDATE(reg, f1, v1); \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

391

uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

392

uint8_t shift, uint32_t mask, uint32_t *field_value);

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

394

uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

395

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

396

uint8_t shift2, uint32_t mask2, uint32_t *field_value2);

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

398

uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

399

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

400

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

401

uint8_t shift3, uint32_t mask3, uint32_t *field_value3);

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

403

uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

404

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

405

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

406

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

407

uint8_t shift4, uint32_t mask4, uint32_t *field_value4);

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

409

uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

410

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

411

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

412

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

413

uint8_t shift4, uint32_t mask4, uint32_t *field_value4,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

414

uint8_t shift5, uint32_t mask5, uint32_t *field_value5);

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

416

uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

417

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

418

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

419

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

420

uint8_t shift4, uint32_t mask4, uint32_t *field_value4,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

421

uint8_t shift5, uint32_t mask5, uint32_t *field_value5,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

422

uint8_t shift6, uint32_t mask6, uint32_t *field_value6);

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

424

uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

425

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

426

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

427

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

428

uint8_t shift4, uint32_t mask4, uint32_t *field_value4,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

429

uint8_t shift5, uint32_t mask5, uint32_t *field_value5,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

430

uint8_t shift6, uint32_t mask6, uint32_t *field_value6,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

431

uint8_t shift7, uint32_t mask7, uint32_t *field_value7);

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

433

uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

434

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

435

uint8_t shift2, uint32_t mask2, uint32_t *field_value2,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

436

uint8_t shift3, uint32_t mask3, uint32_t *field_value3,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

437

uint8_t shift4, uint32_t mask4, uint32_t *field_value4,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

438

uint8_t shift5, uint32_t mask5, uint32_t *field_value5,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

439

uint8_t shift6, uint32_t mask6, uint32_t *field_value6,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

440

uint8_t shift7, uint32_t mask7, uint32_t *field_value7,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

441

uint8_t shift8, uint32_t mask8, uint32_t *field_value8);

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

482

uint32_t addr_index, uint32_t addr_data,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

483

uint32_t index, uint32_t data);

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

485

uint32_t generic_read_indirect_reg(const struct dc_context *ctx,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

486

uint32_t addr_index, uint32_t addr_data,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

487

uint32_t index);

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

489

uint32_t generic_indirect_reg_get(const struct dc_context *ctx,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

490

uint32_t addr_index, uint32_t addr_data,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

491

uint32_t index, int n,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

492

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

495

uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

496

uint32_t addr_index, uint32_t addr_data,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

497

uint32_t index, uint32_t reg_val, int n,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

498

uint8_t shift1, uint32_t mask1, uint32_t field_value1,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

529

uint32_t generic_indirect_reg_get_sync(const struct dc_context *ctx,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

530

uint32_t index, int n,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

531

uint8_t shift1, uint32_t mask1, uint32_t *field_value1,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

534

uint32_t generic_indirect_reg_update_ex_sync(const struct dc_context *ctx,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

535

uint32_t index, uint32_t reg_val, int n,

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

536

uint8_t shift1, uint32_t mask1, uint32_t field_value1,

sys/dev/pci/drm/amd/display/dc/inc/resource.h

65

uint32_t hdmi_disable;

sys/dev/pci/drm/amd/display/dc/inc/resource.h

66

uint32_t dc_pinstraps_audio;

sys/dev/pci/drm/amd/display/dc/inc/resource.h

67

uint32_t audio_stream_number;

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

328

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

329

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

45

uint32_t addr = info->status_reg;

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

46

uint32_t value = dm_read_reg(irq_service->ctx, addr);

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

47

uint32_t current_status = get_reg_field_value(value,

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.h

36

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.h

37

uint32_t ext_id);

sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

263

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

264

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.h

33

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dce60/irq_service_dce60.h

34

uint32_t ext_id);

sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

42

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

43

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

43

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

44

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

42

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

43

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

42

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

43

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

52

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

53

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

38

static enum dc_irq_source to_dal_irq_source_dcn302(struct irq_service *irq_service, uint32_t src_id, uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

38

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

39

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

40

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

41

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

42

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

43

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

47

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

48

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

41

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

42

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

39

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

40

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

18

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

19

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

17

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

18

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

20

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

21

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

100

uint32_t addr = info->enable_reg;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

101

uint32_t value = dm_read_reg(irq_service->ctx, addr);

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

144

uint32_t addr = info->ack_reg;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

145

uint32_t value = dm_read_reg(irq_service->ctx, addr);

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

182

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

183

uint32_t ext_id)

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

195

uint32_t addr = info->status_reg;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

196

uint32_t value = dm_read_reg(irq_service->ctx, addr);

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

197

uint32_t current_status =

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

222

uint32_t addr = info->status_reg;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

223

uint32_t value = dm_read_reg(irq_service->ctx, addr);

sys/dev/pci/drm/amd/display/dc/irq/irq_service.c

224

uint32_t current_status =

sys/dev/pci/drm/amd/display/dc/irq/irq_service.h

47

uint32_t src_id;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.h

48

uint32_t ext_id;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.h

49

uint32_t enable_reg;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.h

50

uint32_t enable_mask;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.h

51

uint32_t enable_value[2];

sys/dev/pci/drm/amd/display/dc/irq/irq_service.h

52

uint32_t ack_reg;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.h

53

uint32_t ack_mask;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.h

54

uint32_t ack_value;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.h

55

uint32_t status_reg;

sys/dev/pci/drm/amd/display/dc/irq/irq_service.h

62

uint32_t src_id,

sys/dev/pci/drm/amd/display/dc/irq/irq_service.h

63

uint32_t ext_id);

sys/dev/pci/drm/amd/display/dc/irq_types.h

219

uint32_t micro_sec_interval;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

688

(uint32_t)cust_pattern_size);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

734

(uint32_t)cust_pattern_size);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.c

250

struct audio_output *audio_output, uint32_t audio_inst)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio.h

56

struct audio_output *audio_output, uint32_t audio_inst);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h

30

uint32_t dp_dio_fixed_vs_pe_retimer_get_lttpr_write_address(struct dc_link *link);

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

179

struct audio_output *audio_output, uint32_t audio_inst)

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

54

uint32_t link_bw_in_kbps =

sys/dev/pci/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

54

struct audio_output *audio_output, uint32_t audio_inst);

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

1247

uint32_t is_hpd_high = 0;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

286

uint32_t address,

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

288

uint32_t len)

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

395

uint32_t max_tmds_clk =

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

526

uint32_t read_dpcd_retry_cnt = 10;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

875

uint32_t i;

sys/dev/pci/drm/amd/display/dc/link/link_detection.c

886

const uint32_t post_oui_delay = 30; // 30ms

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1079

const uint32_t VCP_Y_PRECISION = 1000;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1120

uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1132

uint32_t numerator = 0;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1133

uint32_t denominator = 1;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1175

uint32_t lane_count,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1560

const uint32_t max_retries = 30;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1561

uint32_t retries = 0;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1739

enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1827

enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2048

uint32_t bl_oled_enable_delay = 50; // in ms

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2049

uint32_t post_oui_delay = 30; // 30ms

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2549

uint32_t post_oui_delay = 30; // 30ms

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

323

uint8_t address, uint8_t *buffer, uint32_t length)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

753

uint32_t precision = 1 << 28;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

754

uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

755

uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

767

config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.h

43

enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.h

44

enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

52

void link_get_cur_res_map(const struct dc *dc, uint32_t *map)

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

55

uint32_t i;

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

56

uint32_t hpo_dp_recycle_map = 0;

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

75

void link_restore_res_map(const struct dc *dc, uint32_t *map)

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

78

uint32_t i;

sys/dev/pci/drm/amd/display/dc/link/link_resource.c

80

uint32_t hpo_dp_recycle_map = (*map & LINK_RES_HPO_DP_REC_MAP__MASK)

sys/dev/pci/drm/amd/display/dc/link/link_resource.h

28

void link_get_cur_res_map(const struct dc *dc, uint32_t *map);

sys/dev/pci/drm/amd/display/dc/link/link_resource.h

29

void link_restore_res_map(const struct dc *dc, uint32_t *map);

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

230

uint32_t dp_link_bandwidth_kbps(

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

234

uint32_t total_data_bw_efficiency_x10000 = 0;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

235

uint32_t link_rate_per_lane_kbps = 0;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

266

static uint32_t dp_get_timing_bandwidth_kbps(

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

278

uint32_t req_bw;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

279

uint32_t max_bw;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

290

if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

291

timing->h_addressable == (uint32_t) 640 &&

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

292

timing->v_addressable == (uint32_t) 480)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

337

uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

38

static uint32_t get_tmds_output_pixel_clock_100hz(const struct dc_crtc_timing *timing)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

403

uint32_t timing_bw;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

41

uint32_t pxl_clk = timing->pix_clk_100hz;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

456

uint32_t channel_count,

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

488

static uint32_t get_av_stream_map_lane_count(

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

493

uint32_t av_stream_map_lane_count = 0;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

509

static uint32_t get_audio_sdp_overhead(

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

514

uint32_t audio_sdp_overhead = 0;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

532

static uint32_t calculate_overhead_hblank_bw_in_symbols(

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

533

uint32_t max_slice_h)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

535

uint32_t overhead_hblank_bw = 0; /* in stream symbols */

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

543

uint32_t dp_required_hblank_size_bytes(

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

556

const uint32_t channel_count = audio_params->channel_count;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

557

const uint32_t sample_rate_hz = audio_params->sample_rate_hz;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

561

const uint32_t lane_count = 4;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

564

const uint32_t max_slices_h = 16;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

566

const uint32_t av_stream_map_lane_count = get_av_stream_map_lane_count(

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

568

const uint32_t audio_sdp_overhead = get_audio_sdp_overhead(

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

586

uint32_t num_sdp_with_max_layouts;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

587

uint32_t required_symbols_per_hblank;

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

588

uint32_t required_bytes_per_hblank = 0;

sys/dev/pci/drm/amd/display/dc/link/link_validation.h

36

uint32_t dp_link_bandwidth_kbps(

sys/dev/pci/drm/amd/display/dc/link/link_validation.h

41

uint32_t dp_required_hblank_size_bytes(

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

211

static uint32_t defer_delay_converter_wa(

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

213

uint32_t defer_delay)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

247

uint32_t link_get_aux_defer_delay(struct ddc_service *ddc)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

249

uint32_t defer_delay = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

278

uint32_t retrieved = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

291

uint32_t payload_length = is_end_of_payload ?

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

315

uint32_t address,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

317

uint32_t write_size,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

319

uint32_t read_size)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

322

uint32_t payload_size =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

326

uint32_t write_payloads =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

329

uint32_t read_payloads =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

332

uint32_t payloads_num = write_payloads + read_payloads;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

413

uint32_t link_get_fixed_vs_pe_retimer_write_address(struct dc_link *link)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

415

uint32_t vendor_lttpr_write_address = 0xF004F;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

454

uint32_t link_get_fixed_vs_pe_retimer_read_address(struct dc_link *link)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

459

bool link_configure_fixed_vs_pe_retimer(struct ddc_service *ddc, const uint8_t *data, uint32_t length)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

477

bool link_query_fixed_vs_pe_retimer(struct ddc_service *ddc, uint8_t *data, uint32_t length)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

503

uint32_t timeout)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

512

const uint32_t fixed_vs_address = 0xF004F;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

541

uint32_t pix_clk,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

57

uint32_t count)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

71

static uint32_t i2c_payloads_get_count(struct i2c_payloads *p)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

88

uint32_t address,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

89

uint32_t len,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

93

uint32_t payload_size = EDID_SEGMENT_SIZE;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.c

94

uint32_t pos;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.h

49

uint32_t link_get_aux_defer_delay(struct ddc_service *ddc);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.h

54

uint32_t timeout);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.h

58

uint32_t address,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.h

60

uint32_t write_size,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.h

62

uint32_t read_size);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.h

78

uint32_t length);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.h

83

uint32_t length);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.h

85

uint32_t link_get_fixed_vs_pe_retimer_read_address(struct dc_link *link);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.h

86

uint32_t link_get_fixed_vs_pe_retimer_write_address(struct dc_link *link);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_ddc.h

91

uint32_t pix_clk,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1055

uint32_t aux_channel_retry_cnt = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1325

uint32_t read_dpcd_retry_cnt = 3;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1579

uint32_t lttpr_count;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1580

uint32_t closest_lttpr_offset;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

161

uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

169

uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1694

uint32_t read_dpcd_retry_cnt = 20;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1697

const uint32_t post_oui_delay = 30; // 30ms

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

189

static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2089

uint32_t entry;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2090

uint32_t link_rate_in_khz;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2461

uint32_t clock_pin = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

255

static uint32_t intersect_frl_link_bw_support(

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

256

const uint32_t max_supported_frl_bw_in_kbps,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

259

uint32_t supported_bw_in_kbps = max_supported_frl_bw_in_kbps;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

388

uint32_t lttpr_count = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

594

uint32_t cur_idx = 0, next_idx;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

720

static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

726

uint32_t link_bw;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

763

struct dc_link_settings *link_setting, uint32_t req_bw)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

767

uint32_t link_bw;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

814

uint32_t req_bw,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

819

uint32_t link_bw;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

951

uint32_t req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, dc_link_get_highest_encoding_format(link));

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

979

uint32_t orig_req_bw;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h

107

uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h

52

uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h

82

struct dc_link_settings *link_setting, uint32_t req_bw);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.h

86

uint32_t req_bw,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

184

uint32_t temp, request_bw;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

330

uint32_t link_dpia_get_dp_overhead(const struct dc_link *link)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

332

uint32_t link_dp_overhead = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

342

uint32_t link_bw_in_kbps = (uint32_t)link_cap->link_rate *

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

343

(uint32_t)link_cap->lane_count *

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

364

uint32_t granularity_Gbps;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

366

uint32_t link_bw_granularity;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

367

uint32_t link_required_bw;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

402

uint32_t remaining_bw =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

423

uint32_t total_bw = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h

45

uint32_t required_bw;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h

46

uint32_t allocated_bw;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h

47

uint32_t estimated_bw;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h

48

uint32_t remaining_bw;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h

89

uint32_t link_dpia_get_dp_overhead(const struct dc_link *link);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

53

uint32_t lane;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

101

uint32_t offset)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

91

static inline bool is_immediate_downstream(struct dc_link *link, uint32_t offset)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.h

45

uint32_t offset);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1021

uint32_t i;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1023

uint32_t intra_hop_disable_time_ms = (lttpr_count > 0 ? lttpr_count * 300 : 10);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1186

uint32_t offset)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1229

uint32_t offset)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1231

uint32_t dpcd_base_lt_offset;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1234

uint32_t size_in_bytes;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1356

uint32_t offset)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1370

uint32_t custom_pattern_size)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1388

uint32_t offset)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1428

uint32_t adj_req_count;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1429

uint32_t adj_req_timer;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1431

uint32_t lane;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1466

for (lane = 0; lane < (uint32_t)(lane_count); lane++) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1784

uint32_t req_bw;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1785

uint32_t link_bw;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

258

uint32_t index)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

273

uint32_t wait_in_micro_secs)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

305

uint32_t lane;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

411

uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

457

bool is_repeater(const struct link_training_settings *lt_settings, uint32_t offset)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

465

uint32_t lane;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

467

(uint32_t)(lt_settings->link_settings.lane_count);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

481

uint32_t lane;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

483

for (lane = 0; lane < (uint32_t)(ln_count); lane++) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

495

uint32_t lane;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

496

for (lane = 0; lane < (uint32_t)(ln_count); lane++)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

506

uint32_t lane;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

507

for (lane = 0; lane < (uint32_t)(ln_count); lane++)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

529

uint32_t dp_get_eq_aux_rd_interval(

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

532

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

537

return max(lt_settings->eq_pattern_time, (uint32_t) DPIA_CLK_SYNC_DELAY);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

561

uint32_t lane;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

600

uint32_t offset)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

606

uint32_t lane;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

631

(uint32_t)(link_training_setting->link_settings.lane_count);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

683

uint32_t lane;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

724

uint32_t lane;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

859

uint32_t lane;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

921

uint32_t aux_interval_address;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

994

void repeater_training_done(struct dc_link *link, uint32_t offset)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

998

const uint32_t dpcd_base_lt_offset =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h

103

uint32_t offset);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h

149

bool is_repeater(const struct link_training_settings *lt_settings, uint32_t offset);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h

166

uint32_t wait_in_micro_secs);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h

182

uint32_t dp_translate_training_aux_read_interval(

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h

183

uint32_t dpcd_aux_read_interval);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h

186

uint32_t index);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h

192

uint32_t dp_get_eq_aux_rd_interval(

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h

195

uint32_t offset,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h

49

uint32_t offset);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h

56

uint32_t custom_pattern_size);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h

66

uint32_t offset);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h

77

uint32_t offset);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h

86

uint32_t offset);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.h

98

void repeater_training_done(struct dc_link *link, uint32_t offset);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

167

uint32_t wait_time = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

56

uint32_t *interval_in_us)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

59

uint32_t interval_unit = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

77

uint32_t aux_rd_interval = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

78

uint32_t wait_time = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

187

uint32_t lttpr_count)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

198

uint32_t closest_lttpr_address_offset = dp_get_closest_lttpr_offset(lttpr_count);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

224

uint32_t offset)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

227

uint32_t retries_cr;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

228

uint32_t retry_count;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

229

uint32_t wait_time_microsec;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

344

uint32_t offset)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

348

uint32_t retries_ch_eq;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

349

uint32_t wait_time_microsec;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

54

uint32_t wait_in_micro_secs = 100;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

77

static uint32_t get_eq_training_aux_rd_interval(

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.h

46

uint32_t offset);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.h

52

uint32_t offset);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

237

uint32_t hop)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

240

uint32_t dpcd_tps_offset = DP_TRAINING_PATTERN_SET;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

291

uint32_t hop)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

296

uint32_t retries_cr = 0; /* Number of consecutive attempts with same VS or PE. */

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

297

uint32_t retry_count = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

298

uint32_t wait_time_microsec = TRAINING_AUX_RD_INTERVAL; /* From DP spec, CR read interval is always 100us. */

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

462

uint32_t retries_cr = 0; /* Number of consecutive attempts with same VS or PE. */

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

463

uint32_t retry_count = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

464

uint32_t wait_time_microsec = lt_settings->cr_pattern_time;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

558

uint32_t hop)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

586

uint32_t hop)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

590

uint32_t retries_eq = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

593

uint32_t wait_time_microsec = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

668

wait_time_microsec = max(wait_time_microsec, (uint32_t) DPIA_CLK_SYNC_DELAY);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

734

uint32_t retries_eq = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

737

uint32_t wait_time_microsec;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

813

uint32_t hop)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

828

uint32_t hop)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

831

uint32_t dpcd_tps_offset = DP_TRAINING_PATTERN_SET;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

862

uint32_t hop)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

919

uint32_t dpia_get_eq_aux_rd_interval(

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

922

uint32_t hop)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

944

uint32_t hop)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

947

uint32_t dpcd_tps_offset = DP_TRAINING_PATTERN_SET;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

975

uint32_t hop)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h

47

uint32_t hop);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h

49

uint32_t dpia_get_eq_aux_rd_interval(

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h

52

uint32_t hop);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h

58

uint32_t offset);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

202

uint32_t pre_disable_intercept_delay_ms = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

323

uint32_t retries_cr;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

324

uint32_t retry_count;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

325

uint32_t wait_time_microsec;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

453

uint32_t retries_ch_eq;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

454

uint32_t wait_time_microsec;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

105

const uint32_t start_address,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

106

const uint32_t end_address)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

111

static uint32_t dpcd_get_next_partition_size(const uint32_t address, const uint32_t size)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

113

const uint32_t end_address = END_ADDRESS(address, size);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

114

uint32_t partition_iterator = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

139

const uint32_t in_address,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

141

const uint32_t in_size,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

142

uint32_t *out_address,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

144

uint32_t *out_size)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

146

const uint32_t end_address = END_ADDRESS(in_address, in_size);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

149

uint32_t i;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

176

const uint32_t extended_address,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

178

const uint32_t extended_size,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

179

const uint32_t reduced_address,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

181

const uint32_t reduced_size)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

183

const uint32_t offset = reduced_address - extended_address;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

199

uint32_t address,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

201

uint32_t size)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

203

uint32_t extended_address;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

204

uint32_t partitioned_address;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

206

uint32_t extended_size;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

208

uint32_t size_left_to_read;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

211

uint32_t partition_size;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

212

uint32_t data_index = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

232

uint32_t address,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

234

uint32_t size)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

236

uint32_t partition_size;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

237

uint32_t data_index = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

40

uint32_t start;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

41

uint32_t end;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

46

uint32_t address,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

48

uint32_t size)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

61

uint32_t address,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

63

uint32_t size)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.h

33

uint32_t address,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.h

35

uint32_t size);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.h

39

uint32_t address,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.h

41

uint32_t size);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1113

bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1155

const unsigned int *power_opts, uint32_t coasting_vtotal)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

157

uint32_t backlight_millinits,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

158

uint32_t transition_time_in_ms)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

204

*(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

238

uint32_t *backlight_millinits_avg,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

239

uint32_t *backlight_millinits_peak)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

288

static bool read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

297

sizeof(uint32_t)))

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

301

memset(backlight_millinits, 0, sizeof(uint32_t));

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

314

uint32_t default_backlight;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

355

uint32_t req_bw;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

553

uint32_t backlight_pwm_u16_16 = backlight_level_params->backlight_pwm_u16_16;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

554

uint32_t frame_ramp = backlight_level_params->frame_ramp;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

908

void edp_get_psr_residency(const struct dc_link *link, uint32_t *residency, enum psr_residency_mode mode)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

37

uint32_t *backlight_millinits_avg,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

38

uint32_t *backlight_millinits_peak);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

43

uint32_t backlight_millinits,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

44

uint32_t transition_time_in_ms);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

54

void edp_get_psr_residency(const struct dc_link *link, uint32_t *residency, enum psr_residency_mode mode);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

62

bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

67

const unsigned int *power_opts, uint32_t coasting_vtotal);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

120

bool query_hpd_status(struct dc_link *link, uint32_t *is_hpd_high)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.c

38

uint32_t state = 0;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_hpd.h

46

bool query_hpd_status(struct dc_link *link, uint32_t *is_hpd_high);

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

415

uint32_t MCIF_WB_BUFMGR_SW_CONTROL;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

416

uint32_t MCIF_WB_BUFMGR_CUR_LINE_R;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

417

uint32_t MCIF_WB_BUFMGR_STATUS;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

418

uint32_t MCIF_WB_BUF_PITCH;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

419

uint32_t MCIF_WB_BUF_1_STATUS;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

420

uint32_t MCIF_WB_BUF_1_STATUS2;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

421

uint32_t MCIF_WB_BUF_2_STATUS;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

422

uint32_t MCIF_WB_BUF_2_STATUS2;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

423

uint32_t MCIF_WB_BUF_3_STATUS;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

424

uint32_t MCIF_WB_BUF_3_STATUS2;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

425

uint32_t MCIF_WB_BUF_4_STATUS;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

426

uint32_t MCIF_WB_BUF_4_STATUS2;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

427

uint32_t MCIF_WB_ARBITRATION_CONTROL;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

428

uint32_t MCIF_WB_SCLK_CHANGE;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

429

uint32_t MCIF_WB_TEST_DEBUG_INDEX;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

430

uint32_t MCIF_WB_TEST_DEBUG_DATA;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

431

uint32_t MCIF_WB_BUF_1_ADDR_Y;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

432

uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

433

uint32_t MCIF_WB_BUF_1_ADDR_C;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

434

uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

435

uint32_t MCIF_WB_BUF_2_ADDR_Y;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

436

uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

437

uint32_t MCIF_WB_BUF_2_ADDR_C;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

438

uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

439

uint32_t MCIF_WB_BUF_3_ADDR_Y;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

440

uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

441

uint32_t MCIF_WB_BUF_3_ADDR_C;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

442

uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

443

uint32_t MCIF_WB_BUF_4_ADDR_Y;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

444

uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

445

uint32_t MCIF_WB_BUF_4_ADDR_C;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

446

uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

447

uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

448

uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

449

uint32_t MCIF_WB_NB_PSTATE_CONTROL;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

450

uint32_t MCIF_WB_WATERMARK;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

451

uint32_t MCIF_WB_CLOCK_GATER_CONTROL;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

452

uint32_t MCIF_WB_WARM_UP_CNTL;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

453

uint32_t MCIF_WB_SELF_REFRESH_CONTROL;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

454

uint32_t MULTI_LEVEL_QOS_CTRL;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

455

uint32_t MCIF_WB_SECURITY_LEVEL;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

456

uint32_t MCIF_WB_BUF_LUMA_SIZE;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

457

uint32_t MCIF_WB_BUF_CHROMA_SIZE;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

458

uint32_t MCIF_WB_BUF_1_ADDR_Y_HIGH;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

459

uint32_t MCIF_WB_BUF_1_ADDR_C_HIGH;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

460

uint32_t MCIF_WB_BUF_2_ADDR_Y_HIGH;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

461

uint32_t MCIF_WB_BUF_2_ADDR_C_HIGH;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

462

uint32_t MCIF_WB_BUF_3_ADDR_Y_HIGH;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

463

uint32_t MCIF_WB_BUF_3_ADDR_C_HIGH;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

464

uint32_t MCIF_WB_BUF_4_ADDR_Y_HIGH;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

465

uint32_t MCIF_WB_BUF_4_ADDR_C_HIGH;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

466

uint32_t MCIF_WB_BUF_1_RESOLUTION;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

467

uint32_t MCIF_WB_BUF_2_RESOLUTION;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

468

uint32_t MCIF_WB_BUF_3_RESOLUTION;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

469

uint32_t MCIF_WB_BUF_4_RESOLUTION;\

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

470

uint32_t SMU_WM_CONTROL

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h

478

MCIF_WB_REG_FIELD_LIST_DCN2_0(uint32_t);

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.h

35

uint32_t MMHUBBUB_CLOCK_CNTL

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.h

60

MCIF_WB_REG_FIELD_LIST_DCN3_5(uint32_t);

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

46

uint32_t bg_r_cr, bg_g_y, bg_b_cb;

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

470

uint32_t val = 0xf;

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

121

MPC_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

50

uint32_t MPCC_TOP_SEL[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

51

uint32_t MPCC_BOT_SEL[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

52

uint32_t MPCC_CONTROL[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

53

uint32_t MPCC_STATUS[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

54

uint32_t MPCC_OPP_ID[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

55

uint32_t MPCC_BG_G_Y[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

56

uint32_t MPCC_BG_R_CR[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

57

uint32_t MPCC_BG_B_CB[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

58

uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

59

uint32_t MUX[MAX_OPP]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

60

uint32_t MPCC_UPDATE_LOCK_SEL[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

61

uint32_t CUR[MAX_OPP];

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

137

uint32_t cur_mode;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

191

uint32_t cur_mode;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

193

uint32_t arr_size;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

299

uint32_t state_mode;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

379

uint32_t num)

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

381

uint32_t i;

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

100

uint32_t MPCC_OGAM_RAMA_END_CNTL1_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

101

uint32_t MPCC_OGAM_RAMA_END_CNTL2_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

102

uint32_t MPCC_OGAM_RAMA_END_CNTL1_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

103

uint32_t MPCC_OGAM_RAMA_END_CNTL2_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

104

uint32_t MPCC_OGAM_RAMA_REGION_0_1[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

105

uint32_t MPCC_OGAM_RAMA_REGION_32_33[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

106

uint32_t MPCC_OGAM_RAMB_START_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

107

uint32_t MPCC_OGAM_RAMB_START_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

108

uint32_t MPCC_OGAM_RAMB_START_CNTL_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

109

uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

110

uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

111

uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

112

uint32_t MPCC_OGAM_RAMB_END_CNTL1_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

113

uint32_t MPCC_OGAM_RAMB_END_CNTL2_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

114

uint32_t MPCC_OGAM_RAMB_END_CNTL1_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

115

uint32_t MPCC_OGAM_RAMB_END_CNTL2_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

116

uint32_t MPCC_OGAM_RAMB_END_CNTL1_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

117

uint32_t MPCC_OGAM_RAMB_END_CNTL2_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

118

uint32_t MPCC_OGAM_RAMB_REGION_0_1[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

119

uint32_t MPCC_OGAM_RAMB_REGION_32_33[MAX_MPCC];\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

120

uint32_t MPCC_MEM_PWR_CTRL[MAX_MPCC];\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

121

uint32_t MPCC_OGAM_LUT_INDEX[MAX_MPCC];\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

122

uint32_t MPCC_OGAM_LUT_RAM_CONTROL[MAX_MPCC];\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

123

uint32_t MPCC_OGAM_LUT_DATA[MAX_MPCC];\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

124

uint32_t MPCC_OGAM_MODE[MAX_MPCC];\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

125

uint32_t MPC_OCSC_TEST_DEBUG_DATA;\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

126

uint32_t MPC_OCSC_TEST_DEBUG_INDEX;\

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

127

uint32_t CSC_MODE[MAX_OPP]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

128

uint32_t CSC_C11_C12_A[MAX_OPP]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

129

uint32_t CSC_C33_C34_A[MAX_OPP]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

130

uint32_t CSC_C11_C12_B[MAX_OPP]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

131

uint32_t CSC_C33_C34_B[MAX_OPP]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

132

uint32_t DENORM_CONTROL[MAX_OPP]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

133

uint32_t DENORM_CLAMP_G_Y[MAX_OPP]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

134

uint32_t DENORM_CLAMP_B_CB[MAX_OPP];

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

257

MPC_REG_FIELD_LIST_DCN2_0(uint32_t)

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

89

uint32_t MPCC_TOP_GAIN[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

90

uint32_t MPCC_BOT_GAIN_INSIDE[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

91

uint32_t MPCC_BOT_GAIN_OUTSIDE[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

92

uint32_t MPCC_OGAM_RAMA_START_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

93

uint32_t MPCC_OGAM_RAMA_START_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

94

uint32_t MPCC_OGAM_RAMA_START_CNTL_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

95

uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

96

uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

97

uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

98

uint32_t MPCC_OGAM_RAMA_END_CNTL1_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

99

uint32_t MPCC_OGAM_RAMA_END_CNTL2_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1000

uint32_t rmu_idx)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1002

uint32_t i, red, green, blue, red1, green1, blue1;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1030

uint32_t entries,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1031

uint32_t rmu_idx)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1033

uint32_t i, red, green, blue, value;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1163

uint32_t *select)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1349

uint32_t arr_size;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

136

uint32_t state_mode;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

137

uint32_t state_ram_lut_in_use;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1400

uint32_t mpc3_get_rmu_mux_status(

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1404

uint32_t status = 0xf;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1415

uint32_t mpcc3_acquire_rmu(struct mpc *mpc, int mpcc_id, int rmu_idx)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1417

uint32_t rmu_status;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1438

uint32_t rmu_status;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1477

uint32_t rmu_status = 0xf;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

305

uint32_t num)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

307

uint32_t i;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

447

static enum dc_lut_mode mpc3_get_shaper_current(struct mpc *mpc, uint32_t rmu_idx)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

450

uint32_t state_mode;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

476

uint32_t rmu_idx)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

490

uint32_t rmu_idx)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

639

uint32_t rmu_idx)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

790

uint32_t num,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

791

uint32_t rmu_idx)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

793

uint32_t i, red, green, blue;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

794

uint32_t red_delta, green_delta, blue_delta;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

795

uint32_t red_value, green_value, blue_value;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

822

uint32_t rmu_idx,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

825

uint32_t power_status_shaper = 2;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

826

uint32_t power_status_3dlut = 2;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

866

uint32_t rmu_idx)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

909

uint32_t rmu_idx)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

911

uint32_t lut_mode;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

932

uint32_t i_mode, i_enable_10bits, lut_size;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

975

uint32_t rmu_idx)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

986

uint32_t ram_selection_mask,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

987

uint32_t rmu_idx)

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

999

uint32_t entries,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1020

uint32_t rmu_idx);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1027

uint32_t mpcc3_acquire_rmu(struct mpc *mpc,

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1057

uint32_t mpc3_get_rmu_mux_status(

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

190

uint32_t DWB_MUX[MAX_DWB]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

191

uint32_t MPCC_GAMUT_REMAP_COEF_FORMAT[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

192

uint32_t MPCC_GAMUT_REMAP_MODE[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

193

uint32_t MPC_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

194

uint32_t MPC_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

195

uint32_t MPC_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

196

uint32_t MPC_GAMUT_REMAP_C33_C34_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

197

uint32_t MPC_RMU_CONTROL; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

198

uint32_t MPC_RMU_MEM_PWR_CTRL; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

199

uint32_t SHAPER_CONTROL[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

200

uint32_t SHAPER_OFFSET_R[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

201

uint32_t SHAPER_OFFSET_G[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

202

uint32_t SHAPER_OFFSET_B[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

203

uint32_t SHAPER_SCALE_R[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

204

uint32_t SHAPER_SCALE_G_B[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

205

uint32_t SHAPER_LUT_INDEX[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

206

uint32_t SHAPER_LUT_DATA[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

207

uint32_t SHAPER_LUT_WRITE_EN_MASK[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

208

uint32_t SHAPER_RAMA_START_CNTL_B[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

209

uint32_t SHAPER_RAMA_START_CNTL_G[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

210

uint32_t SHAPER_RAMA_START_CNTL_R[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

211

uint32_t SHAPER_RAMA_END_CNTL_B[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

212

uint32_t SHAPER_RAMA_END_CNTL_G[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

213

uint32_t SHAPER_RAMA_END_CNTL_R[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

214

uint32_t SHAPER_RAMA_REGION_0_1[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

215

uint32_t SHAPER_RAMA_REGION_2_3[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

216

uint32_t SHAPER_RAMA_REGION_4_5[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

217

uint32_t SHAPER_RAMA_REGION_6_7[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

218

uint32_t SHAPER_RAMA_REGION_8_9[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

219

uint32_t SHAPER_RAMA_REGION_10_11[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

220

uint32_t SHAPER_RAMA_REGION_12_13[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

221

uint32_t SHAPER_RAMA_REGION_14_15[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

222

uint32_t SHAPER_RAMA_REGION_16_17[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

223

uint32_t SHAPER_RAMA_REGION_18_19[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

224

uint32_t SHAPER_RAMA_REGION_20_21[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

225

uint32_t SHAPER_RAMA_REGION_22_23[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

226

uint32_t SHAPER_RAMA_REGION_24_25[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

227

uint32_t SHAPER_RAMA_REGION_26_27[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

228

uint32_t SHAPER_RAMA_REGION_28_29[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

229

uint32_t SHAPER_RAMA_REGION_30_31[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

230

uint32_t SHAPER_RAMA_REGION_32_33[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

231

uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

232

uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

233

uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

234

uint32_t MPCC_OGAM_RAMA_OFFSET_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

235

uint32_t MPCC_OGAM_RAMA_OFFSET_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

236

uint32_t MPCC_OGAM_RAMA_OFFSET_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

237

uint32_t MPCC_OGAM_RAMA_START_BASE_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

238

uint32_t MPCC_OGAM_RAMA_START_BASE_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

239

uint32_t MPCC_OGAM_RAMA_START_BASE_CNTL_R[MAX_MPCC];\

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

240

uint32_t SHAPER_RAMB_START_CNTL_B[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

241

uint32_t SHAPER_RAMB_START_CNTL_G[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

242

uint32_t SHAPER_RAMB_START_CNTL_R[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

243

uint32_t SHAPER_RAMB_END_CNTL_B[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

244

uint32_t SHAPER_RAMB_END_CNTL_G[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

245

uint32_t SHAPER_RAMB_END_CNTL_R[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

246

uint32_t SHAPER_RAMB_REGION_0_1[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

247

uint32_t SHAPER_RAMB_REGION_2_3[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

248

uint32_t SHAPER_RAMB_REGION_4_5[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

249

uint32_t SHAPER_RAMB_REGION_6_7[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

250

uint32_t SHAPER_RAMB_REGION_8_9[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

251

uint32_t SHAPER_RAMB_REGION_10_11[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

252

uint32_t SHAPER_RAMB_REGION_12_13[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

253

uint32_t SHAPER_RAMB_REGION_14_15[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

254

uint32_t SHAPER_RAMB_REGION_16_17[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

255

uint32_t SHAPER_RAMB_REGION_18_19[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

256

uint32_t SHAPER_RAMB_REGION_20_21[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

257

uint32_t SHAPER_RAMB_REGION_22_23[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

258

uint32_t SHAPER_RAMB_REGION_24_25[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

259

uint32_t SHAPER_RAMB_REGION_26_27[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

260

uint32_t SHAPER_RAMB_REGION_28_29[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

261

uint32_t SHAPER_RAMB_REGION_30_31[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

262

uint32_t SHAPER_RAMB_REGION_32_33[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

263

uint32_t RMU_3DLUT_MODE[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

264

uint32_t RMU_3DLUT_INDEX[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

265

uint32_t RMU_3DLUT_DATA[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

266

uint32_t RMU_3DLUT_DATA_30BIT[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

267

uint32_t RMU_3DLUT_READ_WRITE_CONTROL[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

268

uint32_t RMU_3DLUT_OUT_NORM_FACTOR[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

269

uint32_t RMU_3DLUT_OUT_OFFSET_R[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

270

uint32_t RMU_3DLUT_OUT_OFFSET_G[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

271

uint32_t RMU_3DLUT_OUT_OFFSET_B[MAX_RMU]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

272

uint32_t MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

273

uint32_t MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

274

uint32_t MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

275

uint32_t MPCC_OGAM_CONTROL[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

276

uint32_t MPCC_OGAM_LUT_CONTROL[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

277

uint32_t MPCC_OGAM_RAMB_OFFSET_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

278

uint32_t MPCC_OGAM_RAMB_OFFSET_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

279

uint32_t MPCC_OGAM_RAMB_OFFSET_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

280

uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

281

uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

282

uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

283

uint32_t MPC_OUT_CSC_COEF_FORMAT

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

286

uint32_t MPCC_MOVABLE_CM_LOCATION_CONTROL[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

287

uint32_t MPCC_MCM_SHAPER_CONTROL[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

288

uint32_t MPCC_MCM_SHAPER_OFFSET_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

289

uint32_t MPCC_MCM_SHAPER_OFFSET_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

290

uint32_t MPCC_MCM_SHAPER_OFFSET_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

291

uint32_t MPCC_MCM_SHAPER_SCALE_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

292

uint32_t MPCC_MCM_SHAPER_SCALE_G_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

293

uint32_t MPCC_MCM_SHAPER_LUT_INDEX[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

294

uint32_t MPCC_MCM_SHAPER_LUT_DATA[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

295

uint32_t MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

296

uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

297

uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

298

uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

299

uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

300

uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

301

uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

302

uint32_t MPCC_MCM_SHAPER_RAMA_REGION_0_1[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

303

uint32_t MPCC_MCM_SHAPER_RAMA_REGION_2_3[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

304

uint32_t MPCC_MCM_SHAPER_RAMA_REGION_4_5[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

305

uint32_t MPCC_MCM_SHAPER_RAMA_REGION_6_7[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

306

uint32_t MPCC_MCM_SHAPER_RAMA_REGION_8_9[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

307

uint32_t MPCC_MCM_SHAPER_RAMA_REGION_10_11[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

308

uint32_t MPCC_MCM_SHAPER_RAMA_REGION_12_13[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

309

uint32_t MPCC_MCM_SHAPER_RAMA_REGION_14_15[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

310

uint32_t MPCC_MCM_SHAPER_RAMA_REGION_16_17[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

311

uint32_t MPCC_MCM_SHAPER_RAMA_REGION_18_19[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

312

uint32_t MPCC_MCM_SHAPER_RAMA_REGION_20_21[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

313

uint32_t MPCC_MCM_SHAPER_RAMA_REGION_22_23[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

314

uint32_t MPCC_MCM_SHAPER_RAMA_REGION_24_25[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

315

uint32_t MPCC_MCM_SHAPER_RAMA_REGION_26_27[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

316

uint32_t MPCC_MCM_SHAPER_RAMA_REGION_28_29[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

317

uint32_t MPCC_MCM_SHAPER_RAMA_REGION_30_31[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

318

uint32_t MPCC_MCM_SHAPER_RAMA_REGION_32_33[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

319

uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

320

uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

321

uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

322

uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

323

uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

324

uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

325

uint32_t MPCC_MCM_SHAPER_RAMB_REGION_0_1[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

326

uint32_t MPCC_MCM_SHAPER_RAMB_REGION_2_3[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

327

uint32_t MPCC_MCM_SHAPER_RAMB_REGION_4_5[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

328

uint32_t MPCC_MCM_SHAPER_RAMB_REGION_6_7[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

329

uint32_t MPCC_MCM_SHAPER_RAMB_REGION_8_9[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

330

uint32_t MPCC_MCM_SHAPER_RAMB_REGION_10_11[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

331

uint32_t MPCC_MCM_SHAPER_RAMB_REGION_12_13[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

332

uint32_t MPCC_MCM_SHAPER_RAMB_REGION_14_15[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

333

uint32_t MPCC_MCM_SHAPER_RAMB_REGION_16_17[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

334

uint32_t MPCC_MCM_SHAPER_RAMB_REGION_18_19[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

335

uint32_t MPCC_MCM_SHAPER_RAMB_REGION_20_21[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

336

uint32_t MPCC_MCM_SHAPER_RAMB_REGION_22_23[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

337

uint32_t MPCC_MCM_SHAPER_RAMB_REGION_24_25[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

338

uint32_t MPCC_MCM_SHAPER_RAMB_REGION_26_27[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

339

uint32_t MPCC_MCM_SHAPER_RAMB_REGION_28_29[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

340

uint32_t MPCC_MCM_SHAPER_RAMB_REGION_30_31[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

341

uint32_t MPCC_MCM_SHAPER_RAMB_REGION_32_33[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

342

uint32_t MPCC_MCM_3DLUT_MODE[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

343

uint32_t MPCC_MCM_3DLUT_INDEX[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

344

uint32_t MPCC_MCM_3DLUT_DATA[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

345

uint32_t MPCC_MCM_3DLUT_DATA_30BIT[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

346

uint32_t MPCC_MCM_3DLUT_READ_WRITE_CONTROL[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

347

uint32_t MPCC_MCM_3DLUT_OUT_NORM_FACTOR[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

348

uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

349

uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

350

uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

351

uint32_t MPCC_MCM_1DLUT_CONTROL[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

352

uint32_t MPCC_MCM_1DLUT_LUT_INDEX[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

353

uint32_t MPCC_MCM_1DLUT_LUT_DATA[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

354

uint32_t MPCC_MCM_1DLUT_LUT_CONTROL[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

355

uint32_t MPCC_MCM_1DLUT_RAMA_START_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

356

uint32_t MPCC_MCM_1DLUT_RAMA_START_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

357

uint32_t MPCC_MCM_1DLUT_RAMA_START_CNTL_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

358

uint32_t MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

359

uint32_t MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

360

uint32_t MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

361

uint32_t MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

362

uint32_t MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

363

uint32_t MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

364

uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL1_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

365

uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL2_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

366

uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL1_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

367

uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL2_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

368

uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL1_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

369

uint32_t MPCC_MCM_1DLUT_RAMA_END_CNTL2_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

370

uint32_t MPCC_MCM_1DLUT_RAMA_OFFSET_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

371

uint32_t MPCC_MCM_1DLUT_RAMA_OFFSET_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

372

uint32_t MPCC_MCM_1DLUT_RAMA_OFFSET_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

373

uint32_t MPCC_MCM_1DLUT_RAMA_REGION_0_1[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

374

uint32_t MPCC_MCM_1DLUT_RAMA_REGION_2_3[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

375

uint32_t MPCC_MCM_1DLUT_RAMA_REGION_4_5[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

376

uint32_t MPCC_MCM_1DLUT_RAMA_REGION_6_7[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

377

uint32_t MPCC_MCM_1DLUT_RAMA_REGION_8_9[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

378

uint32_t MPCC_MCM_1DLUT_RAMA_REGION_10_11[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

379

uint32_t MPCC_MCM_1DLUT_RAMA_REGION_12_13[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

380

uint32_t MPCC_MCM_1DLUT_RAMA_REGION_14_15[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

381

uint32_t MPCC_MCM_1DLUT_RAMA_REGION_16_17[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

382

uint32_t MPCC_MCM_1DLUT_RAMA_REGION_18_19[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

383

uint32_t MPCC_MCM_1DLUT_RAMA_REGION_20_21[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

384

uint32_t MPCC_MCM_1DLUT_RAMA_REGION_22_23[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

385

uint32_t MPCC_MCM_1DLUT_RAMA_REGION_24_25[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

386

uint32_t MPCC_MCM_1DLUT_RAMA_REGION_26_27[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

387

uint32_t MPCC_MCM_1DLUT_RAMA_REGION_28_29[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

388

uint32_t MPCC_MCM_1DLUT_RAMA_REGION_30_31[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

389

uint32_t MPCC_MCM_1DLUT_RAMA_REGION_32_33[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

390

uint32_t MPCC_MCM_1DLUT_RAMB_START_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

391

uint32_t MPCC_MCM_1DLUT_RAMB_START_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

392

uint32_t MPCC_MCM_1DLUT_RAMB_START_CNTL_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

393

uint32_t MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

394

uint32_t MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

395

uint32_t MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

396

uint32_t MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

397

uint32_t MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

398

uint32_t MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

399

uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL1_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

400

uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL2_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

401

uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL1_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

402

uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL2_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

403

uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL1_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

404

uint32_t MPCC_MCM_1DLUT_RAMB_END_CNTL2_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

405

uint32_t MPCC_MCM_1DLUT_RAMB_OFFSET_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

406

uint32_t MPCC_MCM_1DLUT_RAMB_OFFSET_G[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

407

uint32_t MPCC_MCM_1DLUT_RAMB_OFFSET_R[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

408

uint32_t MPCC_MCM_1DLUT_RAMB_REGION_0_1[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

409

uint32_t MPCC_MCM_1DLUT_RAMB_REGION_2_3[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

410

uint32_t MPCC_MCM_1DLUT_RAMB_REGION_4_5[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

411

uint32_t MPCC_MCM_1DLUT_RAMB_REGION_6_7[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

412

uint32_t MPCC_MCM_1DLUT_RAMB_REGION_8_9[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

413

uint32_t MPCC_MCM_1DLUT_RAMB_REGION_10_11[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

414

uint32_t MPCC_MCM_1DLUT_RAMB_REGION_12_13[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

415

uint32_t MPCC_MCM_1DLUT_RAMB_REGION_14_15[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

416

uint32_t MPCC_MCM_1DLUT_RAMB_REGION_16_17[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

417

uint32_t MPCC_MCM_1DLUT_RAMB_REGION_18_19[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

418

uint32_t MPCC_MCM_1DLUT_RAMB_REGION_20_21[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

419

uint32_t MPCC_MCM_1DLUT_RAMB_REGION_22_23[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

420

uint32_t MPCC_MCM_1DLUT_RAMB_REGION_24_25[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

421

uint32_t MPCC_MCM_1DLUT_RAMB_REGION_26_27[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

422

uint32_t MPCC_MCM_1DLUT_RAMB_REGION_28_29[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

423

uint32_t MPCC_MCM_1DLUT_RAMB_REGION_30_31[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

424

uint32_t MPCC_MCM_1DLUT_RAMB_REGION_32_33[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

425

uint32_t MPCC_MCM_MEM_PWR_CTRL[MAX_MPCC]

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

987

MPC_REG_FIELD_LIST_DCN3_0(uint32_t);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

988

MPC_REG_FIELD_LIST_DCN32(uint32_t);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

126

uint32_t mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

169

uint32_t mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

198

uint32_t mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

226

uint32_t mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

228

uint32_t num)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

230

uint32_t i;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

232

uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

233

uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

234

uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

264

uint32_t mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

301

static enum dc_lut_mode mpc32_get_shaper_current(struct mpc *mpc, uint32_t mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

304

uint32_t state_mode;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

331

uint32_t mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

346

uint32_t mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

498

uint32_t mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

651

uint32_t num,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

652

uint32_t mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

654

uint32_t i, red, green, blue;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

655

uint32_t red_delta, green_delta, blue_delta;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

656

uint32_t red_value, green_value, blue_value;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

684

uint32_t mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

687

uint32_t power_status_shaper = 2;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

688

uint32_t power_status_3dlut = 2;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

69

uint32_t mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

715

uint32_t mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

759

uint32_t i_mode, i_enable_10bits, lut_size;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

803

uint32_t mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

815

uint32_t ram_selection_mask,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

816

uint32_t mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

829

uint32_t entries,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

830

uint32_t mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

832

uint32_t i, red, green, blue, red1, green1, blue1;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

861

uint32_t entries,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

862

uint32_t mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

864

uint32_t i, red, green, blue, value;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

885

uint32_t mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

887

uint32_t lut_mode;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

92

static enum dc_lut_mode mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t mpcc_id)

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

95

uint32_t mode_current = 0;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

96

uint32_t in_use = 0;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

319

uint32_t mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

323

uint32_t mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

335

uint32_t mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

339

uint32_t mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

341

uint32_t num);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

344

uint32_t mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

348

uint32_t mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

352

uint32_t mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

357

uint32_t num,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

358

uint32_t mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

362

uint32_t mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

366

uint32_t mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

370

uint32_t mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

373

uint32_t mpcc_id,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

378

uint32_t entries,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

379

uint32_t mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

383

uint32_t entries,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

384

uint32_t mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

387

uint32_t ram_selection_mask,

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

388

uint32_t mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

393

uint32_t mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h

400

uint32_t mpcc_id);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

418

uint32_t mode_select = 0;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

465

uint32_t *mode_select)

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

557

uint32_t mode_select = MPCC_GAMUT_REMAP_MODE_SELECT_0;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

72

uint32_t i_mode, i_enable_10bits, lut_size;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

182

MPC_REG_FIELD_LIST_DCN4_01(uint32_t);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

250

uint32_t *mode_select);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

37

uint32_t MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

38

uint32_t MPCC_MCM_FIRST_GAMUT_REMAP_MODE[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

39

uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

40

uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

41

uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

42

uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

43

uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

44

uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

45

uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

46

uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

47

uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

48

uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

49

uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

50

uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

51

uint32_t MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

52

uint32_t MPCC_MCM_SECOND_GAMUT_REMAP_MODE[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

53

uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

54

uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

55

uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

56

uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

57

uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

58

uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

59

uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

60

uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

61

uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

62

uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

63

uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

64

uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

65

uint32_t MPCC_MCM_3DLUT_FAST_LOAD_SELECT[MAX_MPCC]; \

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h

66

uint32_t MPCC_MCM_3DLUT_FAST_LOAD_STATUS[MAX_MPCC];

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

330

uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right;

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

331

uint32_t space1_size = timing->v_total - timing->v_addressable;

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

333

uint32_t space2_size = timing->v_total - timing->v_addressable;

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

370

uint32_t regval = enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

400

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

147

OPP_DCN10_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

162

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

54

uint32_t FMT_BIT_DEPTH_CONTROL; \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

55

uint32_t FMT_CONTROL; \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

56

uint32_t FMT_DITHER_RAND_R_SEED; \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

57

uint32_t FMT_DITHER_RAND_G_SEED; \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

58

uint32_t FMT_DITHER_RAND_B_SEED; \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

59

uint32_t FMT_CLAMP_CNTL; \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

60

uint32_t FMT_DYNAMIC_EXP_CNTL; \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

61

uint32_t FMT_MAP420_MEMORY_CONTROL; \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

62

uint32_t OPPBUF_CONTROL; \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

63

uint32_t OPPBUF_CONTROL1; \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

64

uint32_t OPPBUF_3D_PARAMETERS_0; \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

65

uint32_t OPPBUF_3D_PARAMETERS_1; \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

66

uint32_t OPP_PIPE_CONTROL

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

327

uint32_t dpg_en, dpg_mode;

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

328

uint32_t double_buffer_pending;

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

344

uint32_t double_buffer_pending;

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

345

uint32_t dpg_en;

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

360

uint32_t count = opp2_get_left_edge_extra_pixel_count(opp, pixel_encoding, is_primary);

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

369

uint32_t opp2_get_left_edge_extra_pixel_count(struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

402

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

58

uint32_t src_bpc = 16;

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

60

uint32_t dst_bpc;

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

61

uint32_t index;

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

71

uint32_t inc_base;

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

126

OPP_DCN20_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

141

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

172

uint32_t opp2_get_left_edge_extra_pixel_count(struct output_pixel_processor *opp,

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

54

uint32_t FMT_422_CONTROL; \

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

55

uint32_t DPG_CONTROL; \

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

56

uint32_t DPG_DIMENSIONS; \

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

57

uint32_t DPG_OFFSET_SEGMENT; \

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

58

uint32_t DPG_COLOUR_B_CB; \

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

59

uint32_t DPG_COLOUR_G_Y; \

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

60

uint32_t DPG_COLOUR_R_CR; \

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

61

uint32_t DPG_RAMP_CONTROL; \

sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.h

62

uint32_t DPG_STATUS

sys/dev/pci/drm/amd/display/dc/opp/dcn35/dcn35_opp.c

40

uint32_t inst, const struct dcn35_opp_registers *regs,

sys/dev/pci/drm/amd/display/dc/opp/dcn35/dcn35_opp.h

34

uint32_t OPP_TOP_CLK_CONTROL

sys/dev/pci/drm/amd/display/dc/opp/dcn35/dcn35_opp.h

55

OPP_DCN35_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/opp/dcn35/dcn35_opp.h

60

uint32_t inst,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

109

uint32_t start_line,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

110

uint32_t end_line)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

121

uint32_t start_line)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1231

uint32_t *v_blank_start,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1232

uint32_t *v_blank_end,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1233

uint32_t *h_position,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1234

uint32_t *v_position)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1255

uint32_t stereo_en;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1294

uint32_t left_eye = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

131

uint32_t start_line)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1399

uint32_t *otg_active_width,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1400

uint32_t *otg_active_height)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1402

uint32_t otg_enabled;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1403

uint32_t v_blank_start;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1404

uint32_t v_blank_end;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1405

uint32_t h_blank_start;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1406

uint32_t h_blank_end;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1446

uint32_t otg_enabled = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1457

uint32_t underflow_occurred = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1561

uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1563

uint32_t field = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

168

uint32_t asic_blank_end;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

169

uint32_t asic_blank_start;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

170

uint32_t v_total;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

171

uint32_t v_sync_end;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

172

uint32_t h_sync_polarity, v_sync_polarity;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

173

uint32_t start_point = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

174

uint32_t field_num = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

309

uint32_t data_fmt = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

349

uint32_t asic_blank_end;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

350

uint32_t v_init;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

351

uint32_t v_fp2 = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

394

uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

414

uint32_t mode = enable ? 2 : 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

472

uint32_t blank_en;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

473

uint32_t blank_state;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

594

uint32_t v_blank;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

595

uint32_t h_blank;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

596

uint32_t min_v_blank;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

660

uint32_t optc1_get_vblank_counter(struct timing_generator *optc)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

663

uint32_t frame_count;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

728

uint32_t occurred_force, occurred_vsync;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

755

uint32_t falling_edge;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

792

uint32_t falling_edge = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

793

uint32_t rising_edge = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

856

uint32_t early_cntl)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

866

uint32_t event_triggers,

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

867

uint32_t num_frames)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

982

uint32_t pattern_mask;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

983

uint32_t pattern_data;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

985

uint32_t src_bpc = 16;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

987

uint32_t dst_bpc;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

988

uint32_t index;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

998

uint32_t inc_base;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

108

uint32_t OTG_GLOBAL_CONTROL1; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

109

uint32_t OTG_GLOBAL_CONTROL2; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

110

uint32_t OTG_VERT_SYNC_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

111

uint32_t OTG_MASTER_UPDATE_MODE; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

112

uint32_t OTG_GSL_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

113

uint32_t OTG_VSTARTUP_PARAM; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

114

uint32_t OTG_VUPDATE_PARAM; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

115

uint32_t OTG_VREADY_PARAM; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

116

uint32_t OTG_BLANK_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

117

uint32_t OTG_MASTER_UPDATE_LOCK; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

118

uint32_t OTG_GLOBAL_CONTROL0; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

119

uint32_t OTG_DOUBLE_BUFFER_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

120

uint32_t OTG_H_TOTAL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

121

uint32_t OTG_H_BLANK_START_END; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

122

uint32_t OTG_H_SYNC_A; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

123

uint32_t OTG_H_SYNC_A_CNTL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

124

uint32_t OTG_H_TIMING_CNTL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

125

uint32_t OTG_V_TOTAL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

126

uint32_t OTG_V_BLANK_START_END; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

127

uint32_t OTG_V_SYNC_A; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

128

uint32_t OTG_V_SYNC_A_CNTL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

129

uint32_t OTG_INTERLACE_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

130

uint32_t OTG_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

131

uint32_t OTG_STEREO_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

132

uint32_t OTG_3D_STRUCTURE_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

133

uint32_t OTG_STEREO_STATUS; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

134

uint32_t OTG_V_TOTAL_MAX; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

135

uint32_t OTG_V_TOTAL_MID; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

136

uint32_t OTG_V_TOTAL_MIN; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

137

uint32_t OTG_V_TOTAL_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

138

uint32_t OTG_V_COUNT_STOP_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

139

uint32_t OTG_V_COUNT_STOP_CONTROL2; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

140

uint32_t OTG_TRIGA_CNTL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

141

uint32_t OTG_TRIGA_MANUAL_TRIG; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

142

uint32_t OTG_MANUAL_FLOW_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

143

uint32_t OTG_FORCE_COUNT_NOW_CNTL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

144

uint32_t OTG_STATIC_SCREEN_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

145

uint32_t OTG_STATUS_FRAME_COUNT; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

146

uint32_t OTG_STATUS; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

147

uint32_t OTG_STATUS_POSITION; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

148

uint32_t OTG_NOM_VERT_POSITION; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

149

uint32_t OTG_BLACK_COLOR; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

150

uint32_t OTG_TEST_PATTERN_PARAMETERS; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

151

uint32_t OTG_TEST_PATTERN_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

152

uint32_t OTG_TEST_PATTERN_COLOR; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

153

uint32_t OTG_CLOCK_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

154

uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

155

uint32_t OTG_VERTICAL_INTERRUPT0_POSITION; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

156

uint32_t OTG_VERTICAL_INTERRUPT1_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

157

uint32_t OTG_VERTICAL_INTERRUPT1_POSITION; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

158

uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

159

uint32_t OTG_VERTICAL_INTERRUPT2_POSITION; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

160

uint32_t OPTC_INPUT_CLOCK_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

161

uint32_t OPTC_DATA_SOURCE_SELECT; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

162

uint32_t OPTC_MEMORY_CONFIG; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

163

uint32_t OPTC_INPUT_GLOBAL_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

164

uint32_t CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

165

uint32_t OTG_GSL_WINDOW_X; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

166

uint32_t OTG_GSL_WINDOW_Y; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

167

uint32_t OTG_VUPDATE_KEEPOUT; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

168

uint32_t OTG_CRC_CNTL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

169

uint32_t OTG_CRC_CNTL2; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

170

uint32_t OTG_CRC0_DATA_RG; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

171

uint32_t OTG_CRC0_DATA_B; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

172

uint32_t OTG_CRC1_DATA_B; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

173

uint32_t OTG_CRC2_DATA_B; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

174

uint32_t OTG_CRC3_DATA_B; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

175

uint32_t OTG_CRC1_DATA_RG; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

176

uint32_t OTG_CRC2_DATA_RG; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

177

uint32_t OTG_CRC3_DATA_RG; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

178

uint32_t OTG_CRC0_WINDOWA_X_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

179

uint32_t OTG_CRC0_WINDOWA_Y_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

180

uint32_t OTG_CRC0_WINDOWB_X_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

181

uint32_t OTG_CRC0_WINDOWB_Y_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

182

uint32_t OTG_CRC1_WINDOWA_X_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

183

uint32_t OTG_CRC1_WINDOWA_Y_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

184

uint32_t OTG_CRC1_WINDOWB_X_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

185

uint32_t OTG_CRC1_WINDOWB_Y_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

186

uint32_t GSL_SOURCE_SELECT; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

187

uint32_t DWB_SOURCE_SELECT; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

188

uint32_t OTG_DSC_START_POSITION; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

189

uint32_t OPTC_DATA_FORMAT_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

190

uint32_t OPTC_BYTES_PER_PIXEL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

191

uint32_t OPTC_WIDTH_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

192

uint32_t OTG_DRR_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

193

uint32_t OTG_BLANK_DATA_COLOR; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

194

uint32_t OTG_BLANK_DATA_COLOR_EXT; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

195

uint32_t OTG_DRR_TRIGGER_WINDOW; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

196

uint32_t OTG_M_CONST_DTO0; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

197

uint32_t OTG_M_CONST_DTO1; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

198

uint32_t OTG_DRR_V_TOTAL_CHANGE; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

199

uint32_t OTG_GLOBAL_CONTROL4; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

200

uint32_t OTG_CRC0_WINDOWA_X_CONTROL_READBACK; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

201

uint32_t OTG_CRC0_WINDOWA_Y_CONTROL_READBACK; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

202

uint32_t OTG_CRC0_WINDOWB_X_CONTROL_READBACK; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

203

uint32_t OTG_CRC0_WINDOWB_Y_CONTROL_READBACK; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

204

uint32_t OTG_CRC1_WINDOWA_X_CONTROL_READBACK; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

205

uint32_t OTG_CRC1_WINDOWA_Y_CONTROL_READBACK; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

206

uint32_t OTG_CRC1_WINDOWB_X_CONTROL_READBACK; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

207

uint32_t OTG_CRC1_WINDOWB_Y_CONTROL_READBACK; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

208

uint32_t OPTC_CLOCK_CONTROL; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

209

uint32_t OPTC_WIDTH_CONTROL2; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

210

uint32_t OTG_PSTATE_REGISTER; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

211

uint32_t OTG_PIPE_UPDATE_STATUS; \

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

212

uint32_t INTERRUPT_DEST

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

641

TG_REG_FIELD_LIST(uint32_t)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

642

TG_REG_FIELD_LIST_DCN2_0(uint32_t)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

643

TG_REG_FIELD_LIST_DCN3_2(uint32_t)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

644

TG_REG_FIELD_LIST_DCN3_5(uint32_t)

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

645

TG_REG_FIELD_LIST_DCN401(uint32_t)

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

108

uint32_t gsl_ready_signal)

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

134

uint32_t dsc_bytes_per_pixel,

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

135

uint32_t dsc_slice_width)

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

153

uint32_t *dsc_mode)

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

165

uint32_t h_div_2 = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

185

uint32_t memory_mask;

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

221

uint32_t *num_of_src_opp,

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

222

uint32_t *src_opp_id_0,

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

223

uint32_t *src_opp_id_1)

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

225

uint32_t num_of_input_segments;

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

244

uint32_t dwb_pipe_inst)

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

259

uint32_t master_pixel_clock_100Hz,

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

260

uint32_t slave_pixel_clock_100Hz,

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

267

uint32_t master_v_active = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

268

uint32_t master_h_total = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

269

uint32_t slave_h_total = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

271

uint32_t X, Y, p = 10000;

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

272

uint32_t master_update_lock;

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

412

uint32_t v_blank_start = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

413

uint32_t h_blank_start = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

498

void optc2_get_last_used_drr_vtotal(struct timing_generator *optc, uint32_t *refresh_rate)

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

103

uint32_t dsc_bytes_per_pixel,

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

104

uint32_t dsc_slice_width);

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

107

uint32_t *dsc_mode);

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

116

uint32_t *num_of_src_opp,

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

117

uint32_t *src_opp_id_0,

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

118

uint32_t *src_opp_id_1);

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

90

uint32_t *refresh_rate);

sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

99

uint32_t gsl_ready_signal);

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

120

uint32_t *num_of_src_opp,

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

121

uint32_t *src_opp_id_0,

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

122

uint32_t *src_opp_id_1)

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

72

uint32_t v_blank;

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

73

uint32_t h_blank;

sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

74

uint32_t min_v_blank;

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

159

uint32_t window_start, uint32_t window_end)

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

169

uint32_t limit)

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

186

uint32_t dsc_bytes_per_pixel,

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

187

uint32_t dsc_slice_width)

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

222

uint32_t memory_mask = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

278

uint32_t update_pending = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

291

uint32_t update_pending = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

304

uint32_t flip_pending = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

305

uint32_t dc_update_pending = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

330

uint32_t mode = enable ? 2 : 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

68

uint32_t v_blank_start = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

69

uint32_t v_blank_end = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

70

uint32_t h_blank_start = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

71

uint32_t h_blank_end = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

341

uint32_t window_start, uint32_t window_end);

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

349

uint32_t limit);

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

353

uint32_t dsc_bytes_per_pixel,

sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.h

354

uint32_t dsc_slice_width);

sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

47

uint32_t memory_mask = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

54

uint32_t memory_mask = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

49

uint32_t memory_mask = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

309

uint32_t max_otg_v_total = optc1->max_v_total - 1;

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

354

uint32_t vcount_stop_timer = 0, vcount_stop = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

355

uint32_t max_otg_v_total = optc1->max_v_total - 1;

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

436

uint32_t is_master_en;

sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

62

uint32_t memory_mask = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

108

uint32_t h_active = segment_width * (opp_cnt - 1) + last_segment_width;

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

109

uint32_t odm_mem_bit_map = decide_odm_mem_bit_map(

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

453

uint32_t lock_status = 0;

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

57

static uint32_t decide_odm_mem_bit_map(int *opp_id, int opp_cnt, int h_active)

sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

61

uint32_t memory_bit_map = 0;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

148

uint32_t pwr_status = 0;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

178

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

179

uint32_t pwr_status = power_on ? 0 : 2;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

180

uint32_t org_ip_request_cntl;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

241

uint32_t pwr_status = 0;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

252

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

253

uint32_t pwr_status = power_on ? 0 : 2;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

254

uint32_t org_ip_request_cntl;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

255

uint32_t power_forceon;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

289

uint32_t pwr_status = 0;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

300

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

301

uint32_t pwr_status = power_on ? 0 : 2;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

302

uint32_t org_ip_request_cntl;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

303

uint32_t power_forceon;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

339

uint32_t pwr_status = 0;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

380

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

381

uint32_t pwr_status = power_on ? 0 : 2;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

382

uint32_t org_ip_request_cntl;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

453

uint32_t pwr_status = 0;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

50

uint32_t pwr_status = 0;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

79

uint32_t power_gate = power_on ? 0 : 1;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

80

uint32_t pwr_status = power_on ? 0 : 2;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

81

uint32_t org_ip_request_cntl = 0;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

132

PG_CNTL_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

133

PG_CNTL_DCN35_REG_FIELD_LIST(uint32_t);

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

137

uint32_t LONO_STATE;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

138

uint32_t DC_IP_REQUEST_CNTL;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

139

uint32_t DOMAIN0_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

140

uint32_t DOMAIN1_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

141

uint32_t DOMAIN2_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

142

uint32_t DOMAIN3_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

143

uint32_t DOMAIN16_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

144

uint32_t DOMAIN17_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

145

uint32_t DOMAIN18_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

146

uint32_t DOMAIN19_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

147

uint32_t DOMAIN22_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

148

uint32_t DOMAIN23_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

149

uint32_t DOMAIN24_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

150

uint32_t DOMAIN25_PG_CONFIG;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

151

uint32_t DOMAIN0_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

152

uint32_t DOMAIN1_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

153

uint32_t DOMAIN2_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

154

uint32_t DOMAIN3_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

155

uint32_t DOMAIN16_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

156

uint32_t DOMAIN17_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

157

uint32_t DOMAIN18_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

158

uint32_t DOMAIN19_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

159

uint32_t DOMAIN22_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

160

uint32_t DOMAIN23_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

161

uint32_t DOMAIN24_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h

162

uint32_t DOMAIN25_PG_STATUS;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

464

uint32_t instance,

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

561

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

584

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

598

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

661

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

676

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

714

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

848

const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

511

uint32_t instance,

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

605

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

628

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

642

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

705

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

720

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

758

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

492

uint32_t instance,

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

577

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

599

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

665

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

681

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

696

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c

734

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1051

static uint32_t read_pipe_fuses(struct dc_context *ctx)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1053

uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

1071

uint32_t pipe_fuses = 0;

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

428

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

442

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

480

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

578

uint32_t instance,

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

675

uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0);

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

750

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

872

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce120/dce120_resource.c

888

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

497

uint32_t instance,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

512

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

527

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

565

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

669

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

692

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

784

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

503

uint32_t instance,

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

518

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

533

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

571

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

675

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

698

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

790

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1289

static uint32_t read_pipe_fuses(struct dc_context *ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1291

uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1320

uint32_t pipe_fuses = read_pipe_fuses(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

571

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

585

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

602

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

618

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

655

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

703

uint32_t instance)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

981

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1061

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1198

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2240

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2263

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2311

uint32_t hw_internal_rev)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2323

uint32_t hw_internal_rev)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2332

static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

733

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

751

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

768

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

785

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

823

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

882

uint32_t instance)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

102

struct dc_context *ctx, uint32_t inst);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

107

uint32_t inst);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

110

uint32_t instance);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

84

uint32_t inst);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

87

struct dc_context *ctx, uint32_t inst);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

90

struct dc_context *ctx, uint32_t inst);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

93

struct dc_context *ctx, uint32_t inst);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

97

uint32_t inst);

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

629

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

646

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

662

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

677

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

710

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

724

static struct mpc *dcn201_mpc_create(struct dc_context *ctx, uint32_t num_mpcc)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

759

uint32_t instance)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

983

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1026

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1042

uint32_t instance)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1090

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1345

static uint32_t read_pipe_fuses(struct dc_context *ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1347

uint32_t value = REG_READ(CC_DC_PIPE_DIS);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1392

uint32_t pipe_fuses = read_pipe_fuses(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1393

uint32_t num_pipes = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

484

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

501

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

520

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

557

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

979

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1198

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1218

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1243

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1266

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1488

uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1915

uint32_t sec_per_100_lines;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1916

uint32_t max_v_blank;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1917

uint32_t curr_v_blank;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1918

uint32_t v_stretch_max;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1919

uint32_t stretched_frame_pix_cnt;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1920

uint32_t scaled_stretched_frame_pix_cnt;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1921

uint32_t scaled_refresh_rate;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2260

static uint32_t read_pipe_fuses(struct dc_context *ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2262

uint32_t value = REG_READ(CC_DC_PIPE_DIS);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2277

uint32_t pipe_fuses = read_pipe_fuses(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2278

uint32_t num_pipes = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

750

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

768

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

785

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

824

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

890

uint32_t instance)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

979

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

996

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1158

static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1178

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1203

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1226

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1281

uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1415

uint32_t pipe_fuses = read_pipe_fuses(ctx);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1416

uint32_t num_pipes = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

714

static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

731

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

746

static struct dce_aux *dcn301_aux_engine_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

780

static struct dce_i2c_hw *dcn301_i2c_hw_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

846

struct dc_context *ctx, uint32_t instance)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

923

static uint32_t read_pipe_fuses(struct dc_context *ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

925

uint32_t value = REG_READ(CC_DC_PIPE_DIS);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

950

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

967

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

297

static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

329

static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

504

static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

538

static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

572

static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

604

static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

680

static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

711

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

746

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

787

static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

818

static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

946

uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

290

static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

319

static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

485

static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

516

static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

547

static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

576

static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

641

static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

672

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

707

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

745

static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

773

static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

891

uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1056

uint32_t instance)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1167

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1184

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1203

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1261

uint32_t hpo_dp_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1262

uint32_t vpg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1263

uint32_t apg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1496

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1516

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1541

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1564

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1621

uint32_t pipe_cnt;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

916

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

934

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

951

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

988

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1046

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1114

uint32_t instance)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1225

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1242

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1261

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1319

uint32_t hpo_dp_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1320

uint32_t vpg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1321

uint32_t apg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1554

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1574

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1599

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1622

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

952

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

970

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

987

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1054

uint32_t instance)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1165

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1182

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1201

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1261

uint32_t hpo_dp_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1262

uint32_t vpg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1263

uint32_t apg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1496

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1516

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1541

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1564

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

914

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

932

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

949

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

986

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1048

uint32_t instance)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1159

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1176

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1196

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1256

uint32_t hpo_dp_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1257

uint32_t vpg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1258

uint32_t apg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1489

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1509

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1534

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1557

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

908

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

926

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

943

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

980

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1122

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1152

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1178

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1251

uint32_t hpo_dp_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1252

uint32_t vpg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1253

uint32_t apg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1507

uint32_t dwb_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1536

uint32_t dwb_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1563

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2029

uint32_t cache_lines_used, lines_per_way, total_cache_lines, num_ways;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2122

static uint32_t read_pipe_fuses(struct dc_context *ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2124

uint32_t value = REG_READ(CC_DC_PIPE_DIS);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2140

uint32_t pipe_fuses = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2141

uint32_t num_pipes = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

747

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

787

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

890

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

922

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

972

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

997

uint32_t instance)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

116

uint32_t dcn32_helper_calculate_mall_bytes_for_cursor(

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

121

uint32_t dcn32_helper_calculate_num_ways_for_subvp(

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

110

uint32_t i;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

156

uint32_t i;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

173

uint32_t i;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

186

uint32_t i;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

198

uint32_t i;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

245

uint32_t i;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

315

uint32_t i, j, k;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

39

uint32_t dcn32_helper_calculate_mall_bytes_for_cursor(

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

428

uint32_t fpo_vactive_margin_us)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

431

uint32_t sec_per_100_lines;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

432

uint32_t max_v_blank;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

433

uint32_t curr_v_blank;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

434

uint32_t v_stretch_max;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

435

uint32_t stretched_frame_pix_cnt;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

436

uint32_t scaled_stretched_frame_pix_cnt;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

437

uint32_t scaled_refresh_rate;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

438

uint32_t v_scale;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

45

uint32_t cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

46

uint32_t cursor_mall_size_bytes = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

463

struct dc_stream_state *fpo_candidate_stream, uint32_t fpo_vactive_margin_us, int current_refresh_rate)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

521

uint32_t fpo_vactive_margin_us = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

647

uint32_t i;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

682

((uint32_t)refresh_rate < 120))

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

707

uint32_t i;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

743

((uint32_t)refresh_rate < 120) && !subvp_disallow &&

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

90

uint32_t dcn32_helper_calculate_num_ways_for_subvp(

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1103

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1133

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1159

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1232

uint32_t hpo_dp_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1233

uint32_t vpg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1234

uint32_t apg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1487

uint32_t dwb_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1516

uint32_t dwb_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1543

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1625

static uint32_t read_pipe_fuses(struct dc_context *ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1627

uint32_t value = REG_READ(CC_DC_PIPE_DIS);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1643

uint32_t pipe_fuses = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1644

uint32_t num_pipes = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

741

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

781

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

884

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

916

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

966

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

991

uint32_t instance)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1030

uint32_t instance)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1183

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1213

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1241

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1314

uint32_t hpo_dp_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1315

uint32_t vpg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1316

uint32_t apg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1568

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1601

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1640

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1669

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

808

static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

838

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

865

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

928

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1010

uint32_t instance)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1163

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1193

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1221

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1294

uint32_t hpo_dp_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1295

uint32_t vpg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1296

uint32_t apg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1548

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1581

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1620

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1649

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

788

static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

818

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

845

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

908

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1011

uint32_t instance)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1164

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1194

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1222

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1295

uint32_t hpo_dp_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1296

uint32_t vpg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1297

uint32_t apg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1549

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1582

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1621

uint32_t pipe_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1650

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

789

static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

819

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

846

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

909

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1096

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1126

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1151

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1222

uint32_t hpo_dp_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1223

uint32_t vpg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1224

uint32_t apg_inst;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1510

uint32_t dwb_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1541

uint32_t dwb_count = pool->res_cap->num_dwb;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1568

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1808

static uint32_t read_pipe_fuses(struct dc_context *ctx)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1810

uint32_t value = REG_READ(CC_DC_PIPE_DIS);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1826

uint32_t pipe_fuses = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1827

uint32_t num_pipes = 4;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

742

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

781

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

883

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

915

uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

965

struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

990

uint32_t instance)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1262

static void spl_calculate_c0_c3_hdr(struct dscl_prog_data *dscl_prog_data, uint32_t sdr_white_level_nits)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1267

uint32_t hdr_multx100_int;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1303

uint32_t sdr_white_level_nits)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl.c

1680

sizeof(uint32_t) * ISHARP_LUT_TABLE_SIZE);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c

20

static const uint32_t filter_isharp_1D_lut_3p0x[ISHARP_LUT_TABLE_SIZE] = {

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c

458

uint32_t filter_pregen_store[ISHARP_LUT_TABLE_SIZE];

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c

509

uint32_t *spl_get_pregen_filter_isharp_1D_lut(enum system_setup setup)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_isharp_filters.h

20

uint32_t value[ISHARP_LUT_TABLE_SIZE];

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_isharp_filters.h

36

uint32_t *spl_get_pregen_filter_isharp_1D_lut(enum system_setup setup);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2381

static uint32_t spl_easf_get_scale_ratio_to_reg_value(struct spl_fixed31_32 ratio,

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2386

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2409

uint32_t spl_get_v_bf3_mode(struct spl_fixed31_32 ratio)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2411

uint32_t value;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2418

uint32_t spl_get_h_bf3_mode(struct spl_fixed31_32 ratio)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2420

uint32_t value;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2427

uint32_t spl_get_reducer_gain6(int taps, struct spl_fixed31_32 ratio)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2429

uint32_t value;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2446

uint32_t spl_get_reducer_gain4(int taps, struct spl_fixed31_32 ratio)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2448

uint32_t value;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2465

uint32_t spl_get_gainRing6(int taps, struct spl_fixed31_32 ratio)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2467

uint32_t value;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2484

uint32_t spl_get_gainRing4(int taps, struct spl_fixed31_32 ratio)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2486

uint32_t value;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2503

uint32_t spl_get_3tap_dntilt_uptilt_offset(int taps, struct spl_fixed31_32 ratio)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2505

uint32_t value;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2517

uint32_t spl_get_3tap_uptilt_maxval(int taps, struct spl_fixed31_32 ratio)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2519

uint32_t value;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2531

uint32_t spl_get_3tap_dntilt_slope(int taps, struct spl_fixed31_32 ratio)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2533

uint32_t value;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2545

uint32_t spl_get_3tap_uptilt1_slope(int taps, struct spl_fixed31_32 ratio)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2547

uint32_t value;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2559

uint32_t spl_get_3tap_uptilt2_slope(int taps, struct spl_fixed31_32 ratio)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2561

uint32_t value;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2573

uint32_t spl_get_3tap_uptilt2_offset(int taps, struct spl_fixed31_32 ratio)

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2575

uint32_t value;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h

13

const uint32_t reg_value;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h

20

uint32_t spl_get_v_bf3_mode(struct spl_fixed31_32 ratio);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h

21

uint32_t spl_get_h_bf3_mode(struct spl_fixed31_32 ratio);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h

22

uint32_t spl_get_reducer_gain6(int taps, struct spl_fixed31_32 ratio);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h

23

uint32_t spl_get_reducer_gain4(int taps, struct spl_fixed31_32 ratio);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h

24

uint32_t spl_get_gainRing6(int taps, struct spl_fixed31_32 ratio);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h

25

uint32_t spl_get_gainRing4(int taps, struct spl_fixed31_32 ratio);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h

26

uint32_t spl_get_3tap_dntilt_uptilt_offset(int taps, struct spl_fixed31_32 ratio);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h

27

uint32_t spl_get_3tap_uptilt_maxval(int taps, struct spl_fixed31_32 ratio);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h

28

uint32_t spl_get_3tap_dntilt_slope(int taps, struct spl_fixed31_32 ratio);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h

29

uint32_t spl_get_3tap_uptilt1_slope(int taps, struct spl_fixed31_32 ratio);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h

30

uint32_t spl_get_3tap_uptilt2_slope(int taps, struct spl_fixed31_32 ratio);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h

31

uint32_t spl_get_3tap_uptilt2_offset(int taps, struct spl_fixed31_32 ratio);

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

14

uint32_t width;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

15

uint32_t height;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

171

uint32_t width;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

172

uint32_t height;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

186

uint32_t offset_rgb_y;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

187

uint32_t offset_rgb_cbcr;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

191

uint32_t h_scale_ratio;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

192

uint32_t v_scale_ratio;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

193

uint32_t h_scale_ratio_c;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

194

uint32_t v_scale_ratio_c;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

200

uint32_t h_filter_init_frac; // SCL_H_INIT_FRAC

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

201

uint32_t h_filter_init_int; // SCL_H_INIT_INT

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

203

uint32_t h_filter_init_frac_c; // SCL_H_INIT_FRAC_C

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

204

uint32_t h_filter_init_int_c; // SCL_H_INIT_INT_C

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

206

uint32_t v_filter_init_frac; // SCL_V_INIT_FRAC

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

207

uint32_t v_filter_init_int; // SCL_V_INIT_INT

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

209

uint32_t v_filter_init_frac_c; // SCL_V_INIT_FRAC_C

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

210

uint32_t v_filter_init_int_c; // SCL_V_INIT_INT_C

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

212

uint32_t v_filter_init_bot_frac; // SCL_V_INIT_FRAC_BOT

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

213

uint32_t v_filter_init_bot_int; // SCL_V_INIT_INT_BOT

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

215

uint32_t v_filter_init_bot_frac_c; // SCL_V_INIT_FRAC_BOT_C

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

216

uint32_t v_filter_init_bot_int_c; // SCL_V_INIT_INT_BOT_C

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

223

uint32_t enable; // ISHARP_NOISEDET_EN

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

224

uint32_t mode; // ISHARP_NOISEDET_MODE

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

225

uint32_t uthreshold; // ISHARP_NOISEDET_UTHRE

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

226

uint32_t dthreshold; // ISHARP_NOISEDET_DTHRE

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

227

uint32_t pwl_start_in; // ISHARP_NOISEDET_PWL_START_IN

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

228

uint32_t pwl_end_in; // ISHARP_NOISEDET_PWL_END_IN

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

229

uint32_t pwl_slope; // ISHARP_NOISEDET_PWL_SLOPE

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

232

uint32_t mode; // ISHARP_LBA_MODE

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

233

uint32_t in_seg[6];

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

234

uint32_t base_seg[6];

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

235

uint32_t slope_seg[6];

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

238

uint32_t mode; // ISHARP_FMT_MODE

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

239

uint32_t norm; // ISHARP_FMT_NORM

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

242

uint32_t enable_p; // ISHARP_NLDELTA_SCLIP_EN_P

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

243

uint32_t pivot_p; // ISHARP_NLDELTA_SCLIP_PIVOT_P

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

244

uint32_t slope_p; // ISHARP_NLDELTA_SCLIP_SLOPE_P

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

245

uint32_t enable_n; // ISHARP_NLDELTA_SCLIP_EN_N

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

246

uint32_t pivot_n; // ISHARP_NLDELTA_SCLIP_PIVOT_N

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

247

uint32_t slope_n; // ISHARP_NLDELTA_SCLIP_SLOPE_N

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

259

uint32_t dscl_mode;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

272

uint32_t easf_matrix_mode;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

273

uint32_t easf_ltonl_en;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

274

uint32_t easf_v_en;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

275

uint32_t easf_v_sharp_factor;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

276

uint32_t easf_v_ring;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

277

uint32_t easf_v_bf1_en;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

278

uint32_t easf_v_bf2_mode;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

279

uint32_t easf_v_bf3_mode;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

280

uint32_t easf_v_bf2_flat1_gain;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

281

uint32_t easf_v_bf2_flat2_gain;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

282

uint32_t easf_v_bf2_roc_gain;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

283

uint32_t easf_v_ringest_3tap_dntilt_uptilt;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

284

uint32_t easf_v_ringest_3tap_uptilt_max;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

285

uint32_t easf_v_ringest_3tap_dntilt_slope;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

286

uint32_t easf_v_ringest_3tap_uptilt1_slope;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

287

uint32_t easf_v_ringest_3tap_uptilt2_slope;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

288

uint32_t easf_v_ringest_3tap_uptilt2_offset;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

289

uint32_t easf_v_ringest_eventap_reduceg1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

290

uint32_t easf_v_ringest_eventap_reduceg2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

291

uint32_t easf_v_ringest_eventap_gain1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

292

uint32_t easf_v_ringest_eventap_gain2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

293

uint32_t easf_v_bf_maxa;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

294

uint32_t easf_v_bf_maxb;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

295

uint32_t easf_v_bf_mina;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

296

uint32_t easf_v_bf_minb;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

297

uint32_t easf_v_bf1_pwl_in_seg0;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

298

uint32_t easf_v_bf1_pwl_base_seg0;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

299

uint32_t easf_v_bf1_pwl_slope_seg0;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

300

uint32_t easf_v_bf1_pwl_in_seg1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

301

uint32_t easf_v_bf1_pwl_base_seg1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

302

uint32_t easf_v_bf1_pwl_slope_seg1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

303

uint32_t easf_v_bf1_pwl_in_seg2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

304

uint32_t easf_v_bf1_pwl_base_seg2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

305

uint32_t easf_v_bf1_pwl_slope_seg2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

306

uint32_t easf_v_bf1_pwl_in_seg3;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

307

uint32_t easf_v_bf1_pwl_base_seg3;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

308

uint32_t easf_v_bf1_pwl_slope_seg3;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

309

uint32_t easf_v_bf1_pwl_in_seg4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

310

uint32_t easf_v_bf1_pwl_base_seg4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

311

uint32_t easf_v_bf1_pwl_slope_seg4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

312

uint32_t easf_v_bf1_pwl_in_seg5;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

313

uint32_t easf_v_bf1_pwl_base_seg5;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

314

uint32_t easf_v_bf1_pwl_slope_seg5;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

315

uint32_t easf_v_bf1_pwl_in_seg6;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

316

uint32_t easf_v_bf1_pwl_base_seg6;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

317

uint32_t easf_v_bf1_pwl_slope_seg6;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

318

uint32_t easf_v_bf1_pwl_in_seg7;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

319

uint32_t easf_v_bf1_pwl_base_seg7;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

320

uint32_t easf_v_bf3_pwl_in_set0;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

321

uint32_t easf_v_bf3_pwl_base_set0;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

322

uint32_t easf_v_bf3_pwl_slope_set0;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

323

uint32_t easf_v_bf3_pwl_in_set1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

324

uint32_t easf_v_bf3_pwl_base_set1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

325

uint32_t easf_v_bf3_pwl_slope_set1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

326

uint32_t easf_v_bf3_pwl_in_set2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

327

uint32_t easf_v_bf3_pwl_base_set2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

328

uint32_t easf_v_bf3_pwl_slope_set2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

329

uint32_t easf_v_bf3_pwl_in_set3;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

330

uint32_t easf_v_bf3_pwl_base_set3;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

331

uint32_t easf_v_bf3_pwl_slope_set3;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

332

uint32_t easf_v_bf3_pwl_in_set4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

333

uint32_t easf_v_bf3_pwl_base_set4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

334

uint32_t easf_v_bf3_pwl_slope_set4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

335

uint32_t easf_v_bf3_pwl_in_set5;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

336

uint32_t easf_v_bf3_pwl_base_set5;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

337

uint32_t easf_h_en;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

338

uint32_t easf_h_sharp_factor;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

339

uint32_t easf_h_ring;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

340

uint32_t easf_h_bf1_en;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

341

uint32_t easf_h_bf2_mode;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

342

uint32_t easf_h_bf3_mode;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

343

uint32_t easf_h_bf2_flat1_gain;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

344

uint32_t easf_h_bf2_flat2_gain;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

345

uint32_t easf_h_bf2_roc_gain;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

346

uint32_t easf_h_ringest_eventap_reduceg1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

347

uint32_t easf_h_ringest_eventap_reduceg2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

348

uint32_t easf_h_ringest_eventap_gain1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

349

uint32_t easf_h_ringest_eventap_gain2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

350

uint32_t easf_h_bf_maxa;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

351

uint32_t easf_h_bf_maxb;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

352

uint32_t easf_h_bf_mina;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

353

uint32_t easf_h_bf_minb;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

354

uint32_t easf_h_bf1_pwl_in_seg0;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

355

uint32_t easf_h_bf1_pwl_base_seg0;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

356

uint32_t easf_h_bf1_pwl_slope_seg0;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

357

uint32_t easf_h_bf1_pwl_in_seg1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

358

uint32_t easf_h_bf1_pwl_base_seg1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

359

uint32_t easf_h_bf1_pwl_slope_seg1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

360

uint32_t easf_h_bf1_pwl_in_seg2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

361

uint32_t easf_h_bf1_pwl_base_seg2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

362

uint32_t easf_h_bf1_pwl_slope_seg2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

363

uint32_t easf_h_bf1_pwl_in_seg3;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

364

uint32_t easf_h_bf1_pwl_base_seg3;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

365

uint32_t easf_h_bf1_pwl_slope_seg3;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

366

uint32_t easf_h_bf1_pwl_in_seg4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

367

uint32_t easf_h_bf1_pwl_base_seg4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

368

uint32_t easf_h_bf1_pwl_slope_seg4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

369

uint32_t easf_h_bf1_pwl_in_seg5;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

370

uint32_t easf_h_bf1_pwl_base_seg5;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

371

uint32_t easf_h_bf1_pwl_slope_seg5;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

372

uint32_t easf_h_bf1_pwl_in_seg6;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

373

uint32_t easf_h_bf1_pwl_base_seg6;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

374

uint32_t easf_h_bf1_pwl_slope_seg6;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

375

uint32_t easf_h_bf1_pwl_in_seg7;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

376

uint32_t easf_h_bf1_pwl_base_seg7;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

377

uint32_t easf_h_bf3_pwl_in_set0;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

378

uint32_t easf_h_bf3_pwl_base_set0;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

379

uint32_t easf_h_bf3_pwl_slope_set0;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

38

uint32_t v_taps;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

380

uint32_t easf_h_bf3_pwl_in_set1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

381

uint32_t easf_h_bf3_pwl_base_set1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

382

uint32_t easf_h_bf3_pwl_slope_set1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

383

uint32_t easf_h_bf3_pwl_in_set2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

384

uint32_t easf_h_bf3_pwl_base_set2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

385

uint32_t easf_h_bf3_pwl_slope_set2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

386

uint32_t easf_h_bf3_pwl_in_set3;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

387

uint32_t easf_h_bf3_pwl_base_set3;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

388

uint32_t easf_h_bf3_pwl_slope_set3;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

389

uint32_t easf_h_bf3_pwl_in_set4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

39

uint32_t h_taps;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

390

uint32_t easf_h_bf3_pwl_base_set4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

391

uint32_t easf_h_bf3_pwl_slope_set4;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

392

uint32_t easf_h_bf3_pwl_in_set5;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

393

uint32_t easf_h_bf3_pwl_base_set5;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

394

uint32_t easf_matrix_c0;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

395

uint32_t easf_matrix_c1;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

396

uint32_t easf_matrix_c2;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

397

uint32_t easf_matrix_c3;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

399

uint32_t isharp_en; // ISHARP_EN

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

40

uint32_t v_taps_c;

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

401

uint32_t isharp_nl_en; // ISHARP_NL_EN ? TODO:check this

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

404

uint32_t isharp_delta[ISHARP_LUT_TABLE_SIZE];

sys/dev/pci/drm/amd/display/dc/sspl/dc_spl_types.h

41

uint32_t h_taps_c;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

11

uint32_t *mantissa,

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

112

uint32_t mask = 1 << i;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

12

uint32_t *exponenta)

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

121

uint32_t mask = 1 << j;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

139

uint32_t *result)

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

14

uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

141

uint32_t mantissa;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

142

uint32_t exponenta;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

37

uint32_t i = 1;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

54

uint32_t i = 1;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

81

uint32_t mantissa,

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

82

uint32_t exponenta,

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

83

uint32_t *result)

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

85

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

86

uint32_t j = 0;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

87

uint32_t value = 0;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

93

const uint32_t mantissa_mask =

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.c

96

const uint32_t exponenta_mask =

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.h

12

uint32_t mantissa_bits;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.h

13

uint32_t exponenta_bits;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.h

18

uint32_t mantissa;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.h

19

uint32_t exponenta;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.h

20

uint32_t value;

sys/dev/pci/drm/amd/display/dc/sspl/spl_custom_float.h

27

uint32_t *result);

sys/dev/pci/drm/amd/display/dc/sspl/spl_os_types.h

24

static inline uint64_t spl_div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder)

sys/dev/pci/drm/amd/display/dc/sspl/spl_os_types.h

29

static inline uint64_t spl_div_u64(uint64_t dividend, uint32_t divisor)

sys/dev/pci/drm/amd/display/dc/virtual/virtual_link_encoder.c

46

uint32_t pixel_clock) {}

sys/dev/pci/drm/amd/display/dc/virtual/virtual_stream_encoder.c

34

uint32_t enable_sdp_splitting) {}

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

1056

uint32_t timeout_us,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

1057

uint32_t num_free_required);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

189

uint32_t base;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

190

uint32_t top;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

212

uint32_t size;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

223

uint32_t inst_const_size;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

224

uint32_t bss_data_size;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

225

uint32_t vbios_size;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

247

uint32_t fb_size;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

248

uint32_t gart_size;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

300

uint32_t psp_version;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

338

uint32_t dmcub_version;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

339

uint32_t scratch[17];

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

340

uint32_t pc[DMUB_PC_SNAPSHOT_COUNT];

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

341

uint32_t undefined_address_fault_addr;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

342

uint32_t inst_fetch_fault_addr;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

343

uint32_t data_write_fault_addr;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

344

uint32_t inbox1_rptr;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

345

uint32_t inbox1_wptr;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

346

uint32_t inbox1_size;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

347

uint32_t inbox0_rptr;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

348

uint32_t inbox0_wptr;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

349

uint32_t inbox0_size;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

350

uint32_t outbox1_rptr;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

351

uint32_t outbox1_wptr;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

352

uint32_t outbox1_size;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

353

uint32_t gpint_datain0;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

390

uint32_t (*reg_read)(void *ctx, uint32_t address);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

397

void (*reg_write)(void *ctx, uint32_t address, uint32_t value);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

430

uint32_t (*get_inbox1_wptr)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

432

uint32_t (*get_inbox1_rptr)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

434

void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

439

uint32_t (*get_outbox1_wptr)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

441

void (*set_outbox1_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

446

uint32_t (*get_outbox0_wptr)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

448

void (*set_outbox0_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

450

uint32_t (*emul_get_inbox1_rptr)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

452

uint32_t (*emul_get_inbox1_wptr)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

454

void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

478

uint32_t (*get_gpint_response)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

480

uint32_t (*get_gpint_dataout)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

484

uint32_t (*read_inbox0_ack_register)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

486

uint32_t (*get_current_time)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

497

uint32_t (*read_reg_inbox0_rsp_int_status)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

504

uint32_t (*read_reg_outbox0_rdy_int_status)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

506

void (*read_reg_outbox0_msg)(struct dmub_srv *dmub, uint32_t *msg);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

507

void (*write_reg_outbox0_rsp)(struct dmub_srv *dmub, uint32_t *rsp);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

508

uint32_t (*read_reg_outbox0_rsp_int_status)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

526

uint32_t fw_version;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

543

uint32_t fw_version;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

559

uint32_t inbox1_last_wptr;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

575

uint32_t psp_version;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

772

uint32_t timeout_us);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

793

uint32_t timeout_us);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

812

uint32_t timeout_us);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

829

uint32_t timeout_us);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

846

uint32_t timeout_us);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

869

uint16_t param, uint32_t timeout_us);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

885

uint32_t *response);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

901

uint32_t *dataout);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

963

enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us);

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1078

uint32_t param : 16; /**< 16-bit parameter */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1079

uint32_t command_code : 12; /**< GPINT command */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1080

uint32_t status : 4; /**< Command status bit */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1082

uint32_t all; /**< GPINT 32-bit access */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1345

uint32_t command_code: 8; /**< INBOX0 command code */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1346

uint32_t param: 24; /**< 24-bit parameter */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1348

uint32_t all;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1356

uint32_t command_code: 8;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1359

uint32_t hw_lock_client: 2;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1362

uint32_t otg_inst: 3;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1363

uint32_t opp_inst: 3;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1364

uint32_t dig_inst: 3;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1367

uint32_t lock_pipe: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1368

uint32_t lock_cursor: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1369

uint32_t lock_dig: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1370

uint32_t triple_buffer_lock: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1372

uint32_t lock: 1; /**< Lock */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1373

uint32_t should_release: 1; /**< Release */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1374

uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1376

uint32_t all;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1656

uint32_t addr; /**< register address */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1657

uint32_t modify_mask; /**< modify mask */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1658

uint32_t modify_value; /**< modify value */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1691

uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1692

uint32_t modify_value; /**< value to update with */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1705

uint32_t addr; /**< register address */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1729

uint32_t addr; /**< register start address */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1733

uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1751

uint32_t addr; /**< Register address */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1752

uint32_t mask; /**< Mask for register bits */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1753

uint32_t condition_field_value; /**< Value to wait for */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1754

uint32_t time_out_us; /**< Time out for reg wait in microseconds */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1771

uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1772

uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1773

uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1774

uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1775

uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1777

uint32_t hubp_inst : 4; /**< HUBP instance */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1778

uint32_t tmz_surface : 1; /**< TMZ enable or disable */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1779

uint32_t immediate :1; /**< Immediate flip */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1780

uint32_t vmid : 4; /**< VMID */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1781

uint32_t grph_stereo : 1; /**< 1 if stereo */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1782

uint32_t reserved : 21; /**< Reserved */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1784

uint32_t reserved[9]; /**< Reserved bits */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1824

uint32_t tmr_delay; /**< Timer delay */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1825

uint32_t tmr_scale; /**< Timer scale */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1885

uint32_t pix_clk_100hz;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1910

uint32_t pix_clk_100hz;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1959

uint32_t surf_addr_lo;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1960

uint32_t surf_addr_c_lo;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1961

uint32_t meta_addr_lo;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1962

uint32_t meta_addr_c_lo;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1991

uint32_t ring_size;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1994

uint32_t src_addr_lo;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1995

uint32_t src_addr_hi;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1997

uint32_t dst_addr_lo;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

1998

uint32_t dst_addr_hi;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2000

uint32_t src_x : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2001

uint32_t src_y : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2003

uint32_t dst_x : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2004

uint32_t dst_y : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2006

uint32_t src_width : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2007

uint32_t src_height : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2009

uint32_t dst_width : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2010

uint32_t dst_height : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2012

uint32_t rect_x : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2013

uint32_t rect_y : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2015

uint32_t src_swizzle_mode : 5;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2016

uint32_t src_mip_max : 5;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2017

uint32_t src_mip_id : 5;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2018

uint32_t dst_mip_max : 5;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2019

uint32_t dst_swizzle_mode : 5;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2020

uint32_t dst_mip_id : 5;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2021

uint32_t tmz : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2022

uint32_t dcc : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2024

uint32_t data_format : 6;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2025

uint32_t padding1 : 4;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2026

uint32_t dst_element_size : 3;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2027

uint32_t num_type : 3;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2028

uint32_t src_element_size : 3;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2029

uint32_t write_compress : 2;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2030

uint32_t cache_policy_dst : 2;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2031

uint32_t cache_policy_src : 2;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2032

uint32_t read_compress : 2;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2033

uint32_t src_dim : 2;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2034

uint32_t dst_dim : 2;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2035

uint32_t max_uncom : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2037

uint32_t max_com : 2;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2038

uint32_t padding : 30;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2041

uint32_t src_lo;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2042

uint32_t src_hi;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2044

uint32_t dst_lo;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2045

uint32_t dst_hi;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2047

uint32_t count : 30;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2048

uint32_t cache_policy_dst : 2;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2050

uint32_t tmz : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2051

uint32_t cache_policy_src : 2;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2052

uint32_t padding : 29;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2055

uint32_t src_lo;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2056

uint32_t src_hi;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2058

uint32_t dst_lo;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2059

uint32_t dst_hi;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2061

uint32_t src_x : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2062

uint32_t src_y : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2064

uint32_t dst_x : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2065

uint32_t dst_y : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2067

uint32_t rect_x : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2068

uint32_t rect_y : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2070

uint32_t src_pitch : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2071

uint32_t dst_pitch : 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2073

uint32_t src_slice_pitch;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2074

uint32_t dst_slice_pitch;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2076

uint32_t tmz : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2077

uint32_t element_size : 3;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2078

uint32_t src_cache_policy : 3;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2079

uint32_t dst_cache_policy : 3;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2080

uint32_t reserved0 : 22;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2083

uint32_t reg_addr;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2084

uint32_t reg_data;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2087

uint32_t src_lo;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2088

uint32_t src_hi;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2090

uint32_t dst_lo;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2091

uint32_t dst_hi;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2095

uint32_t byte_count : 26;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2096

uint32_t src_loc : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2097

uint32_t dst_loc : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2098

uint32_t src_addr_inc : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2099

uint32_t dst_addr_inc : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2100

uint32_t overlap_disable : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2101

uint32_t constant_fill : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2103

uint32_t raw;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2107

uint32_t dst_lo;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2108

uint32_t dst_hi;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2112

uint32_t byte_count : 26;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2113

uint32_t src_loc : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2114

uint32_t dst_loc : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2115

uint32_t src_addr_inc : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2116

uint32_t dst_addr_inc : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2117

uint32_t overlap_disable : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2118

uint32_t constant_fill : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2120

uint32_t raw;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2123

uint32_t data;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2126

uint32_t all[14];

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2136

uint32_t v_total_min;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2137

uint32_t v_total_max;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2138

uint32_t v_total_mid;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2139

uint32_t v_total_mid_frame_num;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2146

uint32_t vpos;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2147

uint32_t hpos;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2148

uint32_t frame;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2269

uint32_t otg_vline_time_ns;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2270

uint32_t otg_vline_time_ticks;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2301

uint32_t otg_vline_time_ns;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2302

uint32_t otg_vline_time_ticks;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2350

uint32_t enable: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2351

uint32_t enable_ppt_check: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2352

uint32_t enable_stall_recovery: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2353

uint32_t enable_debug: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2354

uint32_t enable_offload_flip: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2355

uint32_t enable_visual_confirm: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2356

uint32_t allow_delay_check_mode: 2;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2357

uint32_t reserved: 24;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2359

uint32_t all;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2363

uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2364

uint32_t lock_wait_time_us; // time to forecast acquisition of lock

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2365

uint32_t num_streams;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2367

uint32_t recovery_timeout_us;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2368

uint32_t hwfq_flip_programming_delay_us;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2369

uint32_t max_allow_to_target_delta_us; // how early DCN could assert P-State allow compared to the P-State target

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2495

uint32_t dispclk_khz; /**< dispclk kHz */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2496

uint32_t dppclk_khz; /**< dppclk kHz */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2497

uint32_t dcfclk_khz; /**< dcfclk kHz */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2498

uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

256

uint32_t pause;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2576

uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2585

uint32_t reserved3[11]; /**< For future use */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

261

uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS];

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2632

uint32_t symclk_10khz; /** Symbol Clock in 10Khz */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2638

uint32_t reserved1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

266

uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS];

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2674

uint32_t msg_data; /* set config message data */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

271

uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS];

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2734

uint32_t enable; /* dpia hpd interrupt enable */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

277

uint32_t knee_threshold;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2809

uint32_t address; /**< DP AUX address */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

281

uint32_t current_gain;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2853

uint32_t enable;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

2886

uint32_t handle;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

299

uint32_t low_part; /**< Lower 32 bits */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

300

uint32_t high_part; /**< Upper 32 bits */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3117

uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3118

uint32_t new_hpd_sense_mask; /**< New HPD sense mask */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

313

uint32_t dram_clk_change_blackout_ns;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

314

uint32_t dram_clk_change_read_only_ns;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

315

uint32_t dram_clk_change_write_only_ns;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

316

uint32_t fclk_change_blackout_ns;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

317

uint32_t g7_ppt_blackout_ns;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

318

uint32_t stutter_enter_plus_exit_latency_ns;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

319

uint32_t stutter_exit_latency_ns;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

320

uint32_t z8_stutter_enter_plus_exit_latency_ns;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

321

uint32_t z8_stutter_exit_latency_ns;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

322

uint32_t z8_min_idle_time_ns;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

323

uint32_t type_b_dram_clk_change_blackout_ns;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

324

uint32_t type_b_ppt_blackout_ns;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

325

uint32_t vmin_limit_dispclk_khz;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

326

uint32_t vmin_limit_dcfclk_khz;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

327

uint32_t g7_temperature_read_blackout_ns;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

338

uint32_t x;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3401

uint32_t line_time_in_us;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

343

uint32_t y;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

348

uint32_t width;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

353

uint32_t height;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3628

uint32_t u32All;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

367

uint32_t visual_confirm : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3683

uint32_t cur_enable: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3684

uint32_t reser0: 3;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3685

uint32_t cur_2x_magnify: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3686

uint32_t reser1: 3;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3687

uint32_t mode: 3;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3688

uint32_t reser2: 5;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3689

uint32_t pitch: 2;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3690

uint32_t reser3: 6;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3691

uint32_t line_per_chunk: 5;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3692

uint32_t reser4: 3;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3694

uint32_t raw;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3700

uint32_t cur_x_pos: 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3701

uint32_t cur_y_pos: 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3703

uint32_t raw;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3707

uint32_t hot_x: 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3708

uint32_t hot_y: 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3710

uint32_t raw;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3714

uint32_t dst_x_offset: 13;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3715

uint32_t reserved: 19;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3717

uint32_t raw;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

372

uint32_t force_full_frame_update : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3723

uint32_t cur0_enable: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3724

uint32_t expansion_mode: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3725

uint32_t reser0: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3726

uint32_t cur0_rom_en: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3727

uint32_t mode: 3;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3728

uint32_t reserved: 25;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3730

uint32_t raw;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3746

uint32_t SURFACE_ADDR_HIGH;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3747

uint32_t SURFACE_ADDR;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3751

uint32_t width: 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3752

uint32_t height: 16;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3754

uint32_t raw;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3758

uint32_t dst_y_offset: 8;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3759

uint32_t chunk_hdl_adjust: 2;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3760

uint32_t reserved: 22;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3762

uint32_t raw;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

377

uint32_t use_hw_lock_mgr : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

382

uint32_t force_wakeup_by_tps3 : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

387

uint32_t back_to_back_flip : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

3892

uint32_t power_opt;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

392

uint32_t enable_ips_visual_confirm : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

398

uint32_t u32All;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

410

uint32_t visual_confirm : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

4118

uint32_t line_time_in_ns;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

416

uint32_t skip_crc : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

422

uint32_t force_link_power_on : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

428

uint32_t force_phy_power_on : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

4299

uint32_t power_opt;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

434

uint32_t timing_resync_disabled : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

4371

uint32_t param1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

4373

uint32_t param2;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

440

uint32_t skip_crtc_disabled : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

446

uint32_t force_defer_one_frame_update : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

452

uint32_t disable_delay_alpm_on : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

458

uint32_t disable_desync_error_check : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

464

uint32_t force_self_update_when_abm_non_steady : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

471

uint32_t enable_ips_visual_confirm : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

477

uint32_t enable_ips_residency_profiling : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

4810

uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS];

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

4815

uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS];

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

4820

uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS];

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

483

uint32_t enable_coasting_vtotal_check : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

488

uint32_t enable_visual_confirm_debug : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

490

uint32_t reserved : 18;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

493

uint32_t u32All;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

504

uint32_t desync_error : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5043

uint32_t frame_ramp;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5048

uint32_t backlight_user_level;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5083

uint32_t min_luminance;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5088

uint32_t max_luminance;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

509

uint32_t state_transition_error : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5093

uint32_t min_backlight_pwm;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5098

uint32_t max_backlight_pwm;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5123

uint32_t level;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

514

uint32_t crc_error : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5165

uint32_t ambient_lux;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

519

uint32_t reserved_3 : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5208

uint32_t fractional_pwm;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

525

uint32_t incorrect_vtotal_in_static_screen : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

530

uint32_t no_double_rr : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

535

uint32_t reserved_6_7 : 2;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

540

uint32_t reserved_9_31 : 24;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

543

uint32_t u32All;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

552

uint32_t allow_alpm_fw_standby_mode : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5524

uint32_t vb_scaling_strength_mapping;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

557

uint32_t dsc_enable_status : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

562

uint32_t fec_enable_status : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5628

uint32_t pwrseq_inst; /**< pwrseq instance */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5629

uint32_t current_backlight; /* in/out */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5630

uint32_t bl_pwm_cntl; /* in/out */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5631

uint32_t bl_pwm_period_cntl; /* in/out */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5632

uint32_t bl_pwm_ref_div1; /* in/out */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5636

uint32_t bl_pwm_ref_div2; /* in/out */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5649

uint32_t v_total_max;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5650

uint32_t v_total_min;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5651

uint32_t tg_inst;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5660

uint32_t pix_clk_100hz;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

569

uint32_t smu_optimizations_en : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5736

uint32_t symclk_100Hz; /**< PLL symclock in 100hz */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5739

uint32_t status;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

574

uint32_t phy_power_state : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

579

uint32_t link_power_state : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

583

uint32_t force_wakeup_by_tps3 : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

587

uint32_t is_alpm_initialized : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5877

uint32_t timeout_us;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5889

uint32_t is_aux : 1; // True

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5890

uint32_t ddc_line : 3;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5891

uint32_t address : 20;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5892

uint32_t length : 8; // Automatically split into 16B transactions

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

592

uint32_t alpm_mode : 2;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

595

uint32_t u32All;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6007

uint32_t reserved[3];

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6029

uint32_t residency_millipercent;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6030

uint32_t entry_counter;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6031

uint32_t histogram[NUM_IPS_HISTOGRAM_BUCKETS];

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6034

uint32_t ono_pg_state_at_collection;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6035

uint32_t ono_pg_state_last_seen_in_ips;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6057

uint32_t size;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6058

uint32_t ips_mode;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6444

uint32_t capacity; /**< Ringbuffer capacity in bytes */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6445

uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6446

uint32_t write_ptr; /**< Initial write pointer for producer in bytes */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6454

uint32_t rptr; /**< Read pointer for consumer in bytes */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6455

uint32_t wrpt; /**< Write pointer for producer in bytes */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6456

uint32_t capacity; /**< Ringbuffer capacity in bytes */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6480

static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb)

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6482

uint32_t data_count;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6498

static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb)

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6500

uint32_t data_count;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

652

uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6522

uint32_t data_count;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

653

uint32_t reserved : 31;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

655

uint32_t all; /**< 32-bit access to status bits */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6625

uint32_t num_cmds,

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6626

uint32_t *next_rptr)

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6648

uint32_t rptr)

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6718

uint32_t rptr = rb->rptr;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

6719

uint32_t wptr = rb->wrpt;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

674

uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

675

uint32_t fw_region_size; /**< size of the firmware state region */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

676

uint32_t trace_buffer_size; /**< size of the tracebuffer region */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

677

uint32_t fw_version; /**< the firmware version information */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

680

uint32_t shared_state_size; /**< size of the shared state region in bytes */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

703

typedef uint32_t dmub_trace_code_t;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

710

uint32_t tick_count; /**< the tick count at time of trace */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

711

uint32_t param0; /**< trace defined parameter 0 */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

712

uint32_t param1; /**< trace defined parameter 1 */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

734

uint32_t dal_fw : 1; /**< 1 if DAL FW */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

735

uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

736

uint32_t optimized_init_done : 1; /**< 1 if optimized init done */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

737

uint32_t restore_required : 1; /**< 1 if driver should call restore */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

738

uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

739

uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

740

uint32_t detection_required: 1; /**< if detection need to be triggered by driver */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

741

uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

742

uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

744

uint32_t all; /**< 32-bit access to status bits */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

765

uint32_t psp_ok : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

766

uint32_t edp_on : 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

767

uint32_t reserved : 30;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

769

uint32_t all;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

823

uint32_t pemu_env : 1; /**< 1 if PEMU */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

824

uint32_t fpga_env : 1; /**< 1 if FPGA */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

825

uint32_t optimized_init : 1; /**< 1 if optimized init */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

826

uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

827

uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

828

uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

829

uint32_t z10_disable: 1; /**< 1 to disable z10 */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

830

uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

831

uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

832

uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

833

uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

835

uint32_t power_optimization: 1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

836

uint32_t diag_env: 1; /* 1 if diagnostic environment */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

837

uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

838

uint32_t usb4_cm_version: 1; /**< 1 CM support */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

839

uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

840

uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

841

uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

842

uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

843

uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

844

uint32_t ips_disable: 3; /* options to disable ips support*/

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

845

uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

846

uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

847

uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

848

uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

849

uint32_t reserved : 5; /**< reserved */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

851

uint32_t all; /**< 32-bit access to bits */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

890

uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

891

uint32_t ips2_commit : 1; /**< 1 if in IPS2 */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

892

uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

893

uint32_t detection_required : 1; /**< 1 if detection is required */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

894

uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

895

uint32_t reserved_bits : 27; /**< Reversed */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

897

uint32_t all;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

905

uint32_t allow_pg : 1; /**< 1 if PG is allowed */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

906

uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

907

uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

908

uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

909

uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

910

uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

911

uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

912

uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

913

uint32_t allow_dynamic_ips1 : 1; /**< 1 if IPS1 is allowed in dynamic use cases such as VPB */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

914

uint32_t allow_dynamic_ips1_z8: 1; /**< 1 if IPS1 z8 ret is allowed in dynamic use cases such as VPB */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

915

uint32_t reserved_bits : 22; /**< Reversed bits */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

917

uint32_t all;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

928

uint32_t exclude_points[62];

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

938

uint32_t rcg_entry_count; /**< Entry counter for RCG */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

939

uint32_t rcg_exit_count; /**< Exit counter for RCG */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

940

uint32_t ips1_entry_count; /**< Entry counter for IPS1 */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

941

uint32_t ips1_exit_count; /**< Exit counter for IPS1 */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

942

uint32_t ips2_entry_count; /**< Entry counter for IPS2 */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

943

uint32_t ips2_exit_count; /**< Exit counter for IPS2 */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

944

uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

945

uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

946

uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

959

uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

966

uint32_t padding[62];

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

975

uint32_t reserved; /**< Reserved bytes. */

sys/dev/pci/drm/amd/display/dmub/inc/dmub_trace_buffer.h

53

uint32_t tick_count;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_trace_buffer.h

54

uint32_t param0;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_trace_buffer.h

55

uint32_t param1;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_trace_buffer.h

63

uint32_t entry_count;

sys/dev/pci/drm/amd/display/dmub/inc/dmub_trace_buffer.h

64

uint32_t clk_freq;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

286

uint32_t dmub_dcn20_get_inbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

291

uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

296

void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

313

uint32_t dmub_dcn20_get_outbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

322

void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

339

uint32_t dmub_dcn20_get_outbox0_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

344

void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

351

uint32_t is_hw_init;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

360

uint32_t supported = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

384

uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

412

uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

419

uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

420

uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

64

uint32_t tmp;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

97

const uint32_t timeout = 30;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

98

uint32_t in_reset, scratch, i;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

157

#define DMUB_SR(reg) uint32_t reg;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

170

#define DMUB_SF(reg, field) uint32_t reg##__##field;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

206

uint32_t dmub_dcn20_get_inbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

208

uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

210

void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

215

uint32_t dmub_dcn20_get_outbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

217

void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

222

uint32_t dmub_dcn20_get_outbox0_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

224

void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

236

uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

248

uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c

64

uint32_t tmp;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

251

uint32_t dmub_dcn31_get_inbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

256

uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

261

void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

273

uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

282

void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

294

uint32_t is_enable;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

304

uint32_t supported = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

333

uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

338

uint32_t dmub_dcn31_get_gpint_dataout(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

340

uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

403

uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

408

void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

413

uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

420

uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset, is_pwait;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

421

uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

491

uint32_t fw_boot_status = REG_READ(DMCUB_SCRATCH0);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

60

uint32_t tmp;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

86

const uint32_t timeout = 100000;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

87

uint32_t in_reset, is_enabled, scratch, i, pwait_mode;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

158

#define DMUB_SR(reg) uint32_t reg;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

171

#define DMUB_SF(reg, field) uint32_t reg##__##field;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

208

uint32_t dmub_dcn31_get_inbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

210

uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

212

void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

217

uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

219

void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

233

uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

235

uint32_t dmub_dcn31_get_gpint_dataout(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

248

uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

250

void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

252

uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

281

uint32_t dmub_dcn32_get_inbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

286

uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

291

void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

303

uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

312

void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

324

uint32_t is_hw_init;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

334

uint32_t supported = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

358

uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

363

uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

365

uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

411

uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

416

void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

421

uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

428

uint32_t is_dmub_enabled, is_soft_reset, is_pwait;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

429

uint32_t is_traceport_enabled, is_cw6_enabled;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

516

uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

523

uint32_t index = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

66

uint32_t tmp;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

92

const uint32_t timeout = 100000;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

93

uint32_t in_reset, is_enabled, scratch, i, pwait_mode;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

174

#define DMUB_SR(reg) uint32_t reg;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

187

#define DMUB_SF(reg, field) uint32_t reg##__##field;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

221

uint32_t dmub_dcn32_get_inbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

223

uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

225

void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

230

uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

232

void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

244

uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

246

uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

257

uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

259

void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

261

uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

268

uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

287

uint32_t dmub_dcn35_get_inbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

292

uint32_t dmub_dcn35_get_inbox1_rptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

297

void dmub_dcn35_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

309

uint32_t dmub_dcn35_get_outbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

318

void dmub_dcn35_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

330

uint32_t is_enable;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

340

uint32_t supported = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

364

uint32_t dmub_dcn35_get_gpint_response(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

369

uint32_t dmub_dcn35_get_gpint_dataout(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

371

uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

441

uint32_t dmub_dcn35_get_outbox0_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

446

void dmub_dcn35_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

451

uint32_t dmub_dcn35_get_current_time(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

458

uint32_t is_dmub_enabled, is_soft_reset, is_pwait;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

459

uint32_t is_traceport_enabled, is_cw6_enabled;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

538

uint32_t fw_boot_status = REG_READ(DMCUB_SCRATCH0);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

553

uint32_t dmub_dcn35_read_inbox0_ack_register(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

561

uint32_t is_enable;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

63

uint32_t tmp;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

91

const uint32_t timeout = 100000;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

92

uint32_t in_reset, is_enabled, scratch, i, pwait_mode;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

176

#define DMUB_SR(reg) uint32_t reg;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

189

#define DMUB_SF(reg, field) uint32_t reg##__##field;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

228

uint32_t dmub_dcn35_get_inbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

230

uint32_t dmub_dcn35_get_inbox1_rptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

232

void dmub_dcn35_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

237

uint32_t dmub_dcn35_get_outbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

239

void dmub_dcn35_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

251

uint32_t dmub_dcn35_get_gpint_response(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

253

uint32_t dmub_dcn35_get_gpint_dataout(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

266

uint32_t dmub_dcn35_get_outbox0_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

268

void dmub_dcn35_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

270

uint32_t dmub_dcn35_get_current_time(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

280

uint32_t dmub_dcn35_read_inbox0_ack_register(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

267

uint32_t dmub_dcn401_get_inbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

272

uint32_t dmub_dcn401_get_inbox1_rptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

277

void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

289

uint32_t dmub_dcn401_get_outbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

298

void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

310

uint32_t is_hw_init;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

320

uint32_t supported = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

344

uint32_t dmub_dcn401_get_gpint_response(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

349

uint32_t dmub_dcn401_get_gpint_dataout(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

351

uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

399

uint32_t dmub_dcn401_get_outbox0_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

40

uint32_t tmp;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

404

void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

409

uint32_t dmub_dcn401_get_current_time(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

416

uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset, is_pwait;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

417

uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

510

uint32_t dmub_dcn401_read_inbox0_ack_register(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

518

uint32_t *dwords = (uint32_t *)cmd;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

520

uint32_t msg_index;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

584

uint32_t dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

586

uint32_t status;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

595

uint32_t *dwords = (uint32_t *)cmd;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

638

void dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

643

void dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

648

uint32_t dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

650

uint32_t status;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

66

const uint32_t timeout_us = 1 * 1000 * 1000; //1s

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

661

uint32_t dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

663

uint32_t status;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

67

const uint32_t poll_delay_us = 1; //1us

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

68

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

69

uint32_t enabled, in_reset, scratch, pwait_mode;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

176

#define DMUB_SR(reg) uint32_t reg;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

189

#define DMUB_SF(reg, field) uint32_t reg##__##field;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

225

uint32_t dmub_dcn401_get_inbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

227

uint32_t dmub_dcn401_get_inbox1_rptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

229

void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

234

uint32_t dmub_dcn401_get_outbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

236

void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

248

uint32_t dmub_dcn401_get_gpint_response(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

250

uint32_t dmub_dcn401_get_gpint_dataout(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

261

uint32_t dmub_dcn401_get_outbox0_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

263

void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

265

uint32_t dmub_dcn401_get_current_time(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

272

uint32_t dmub_dcn401_read_inbox0_ack_register(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

276

uint32_t dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

284

void dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

285

void dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *msg);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

286

uint32_t dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

288

uint32_t dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

104

void dmub_reg_get(struct dmub_srv *srv, uint32_t addr, uint8_t shift,

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

105

uint32_t mask, uint32_t *field_value)

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

107

uint32_t reg_val = srv->funcs.reg_read(srv->user_ctx, addr);

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

30

uint32_t value;

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

31

uint32_t mask;

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

36

uint32_t value, uint32_t mask, uint8_t shift)

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

44

uint32_t addr, int n, uint8_t shift1,

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

45

uint32_t mask1, uint32_t field_value1,

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

48

uint32_t shift, mask, field_value;

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

56

shift = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

57

mask = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

58

field_value = va_arg(ap, uint32_t);

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

66

static inline uint32_t get_reg_field_value_ex(uint32_t reg_value, uint32_t mask,

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

72

void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1,

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

73

uint32_t mask1, uint32_t field_value1, ...)

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

76

uint32_t reg_val;

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

89

void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n,

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

90

uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...)

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

114

void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n,

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

115

uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

117

void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1,

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

118

uint32_t mask1, uint32_t field_value1, ...);

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

120

void dmub_reg_get(struct dmub_srv *srv, uint32_t addr, uint8_t shift,

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

121

uint32_t mask, uint32_t *field_value);

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

100

uint32_t pos, end;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1019

uint16_t param, uint32_t timeout_us)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1022

uint32_t i;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1050

uint32_t *response)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1066

uint32_t *dataout)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

117

dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1176

enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1178

uint32_t i = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1179

uint32_t ack = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1222

uint32_t num_pending = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1285

uint32_t rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1286

uint32_t wptr = dmub->hw_funcs.get_inbox1_wptr(dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1316

uint32_t timeout_us,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1317

uint32_t num_free_required)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1320

uint32_t i;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1321

const uint32_t polling_interval_us = 1;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1344

uint32_t rptr;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

148

uint32_t i;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

501

static uint32_t dmub_srv_calc_regions_for_memory_type(const struct dmub_srv_region_params *params,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

503

const uint32_t *window_sizes,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

506

uint32_t i, top = 0;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

527

uint32_t fw_state_size = DMUB_FW_STATE_SIZE;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

528

uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

529

uint32_t shared_state_size = DMUB_FW_HEADER_SHARED_STATE_SIZE;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

530

uint32_t window_sizes[DMUB_WINDOW_TOTAL] = { 0 };

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

585

uint32_t i;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

892

uint32_t timeout_us)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

894

uint32_t i;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

91

static inline uint32_t dmub_align(uint32_t val, uint32_t factor)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

910

uint32_t timeout_us)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

912

uint32_t i;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

953

uint32_t timeout_us)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

955

uint32_t i;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

956

const uint32_t polling_interval_us = 1;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

991

uint32_t timeout_us)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

994

uint32_t i;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

995

const uint32_t polling_interval_us = 1;

sys/dev/pci/drm/amd/display/include/audio_types.h

38

uint32_t link_bandwidth_kbps;

sys/dev/pci/drm/amd/display/include/audio_types.h

39

uint32_t hblank_min_symbol_width;

sys/dev/pci/drm/amd/display/include/audio_types.h

47

uint32_t h_total;

sys/dev/pci/drm/amd/display/include/audio_types.h

48

uint32_t h_active;

sys/dev/pci/drm/amd/display/include/audio_types.h

49

uint32_t v_active;

sys/dev/pci/drm/amd/display/include/audio_types.h

50

uint32_t requested_pixel_clock_100Hz; /* in 100Hz */

sys/dev/pci/drm/amd/display/include/audio_types.h

51

uint32_t calculated_pixel_clock_100Hz; /* in 100Hz */

sys/dev/pci/drm/amd/display/include/audio_types.h

52

uint32_t dsc_bits_per_pixel;

sys/dev/pci/drm/amd/display/include/audio_types.h

53

uint32_t dsc_num_slices;

sys/dev/pci/drm/amd/display/include/audio_types.h

61

uint32_t pixel_clock_in_10khz;

sys/dev/pci/drm/amd/display/include/audio_types.h

62

uint32_t audio_dto_phase;

sys/dev/pci/drm/amd/display/include/audio_types.h

63

uint32_t audio_dto_module;

sys/dev/pci/drm/amd/display/include/audio_types.h

64

uint32_t audio_dto_wall_clock_ratio;

sys/dev/pci/drm/amd/display/include/audio_types.h

80

uint32_t audio_dto_source_clock_in_khz;

sys/dev/pci/drm/amd/display/include/audio_types.h

81

uint32_t ss_percentage;

sys/dev/pci/drm/amd/display/include/audio_types.h

89

uint32_t ALL_CHANNEL_FL:4;

sys/dev/pci/drm/amd/display/include/audio_types.h

90

uint32_t ALL_CHANNEL_FR:4;

sys/dev/pci/drm/amd/display/include/audio_types.h

91

uint32_t ALL_CHANNEL_FC:4;

sys/dev/pci/drm/amd/display/include/audio_types.h

92

uint32_t ALL_CHANNEL_Sub:4;

sys/dev/pci/drm/amd/display/include/audio_types.h

93

uint32_t ALL_CHANNEL_SL:4;

sys/dev/pci/drm/amd/display/include/audio_types.h

94

uint32_t ALL_CHANNEL_SR:4;

sys/dev/pci/drm/amd/display/include/audio_types.h

95

uint32_t ALL_CHANNEL_BL:4;

sys/dev/pci/drm/amd/display/include/audio_types.h

96

uint32_t ALL_CHANNEL_BR:4;

sys/dev/pci/drm/amd/display/include/audio_types.h

98

uint32_t u32all;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

119

uint32_t pixel_clock; /* khz */

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

132

uint32_t pixel_clock; /* in KHz */

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

161

uint32_t pixel_clock;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

162

uint32_t lane_select;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

163

uint32_t lane_settings;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

172

uint32_t h_total;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

173

uint32_t h_addressable;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

174

uint32_t h_overscan_left;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

175

uint32_t h_overscan_right;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

176

uint32_t h_sync_start;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

177

uint32_t h_sync_width;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

180

uint32_t v_total;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

181

uint32_t v_addressable;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

182

uint32_t v_overscan_top;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

183

uint32_t v_overscan_bottom;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

184

uint32_t v_sync_start;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

185

uint32_t v_sync_width;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

188

uint32_t INTERLACE:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

189

uint32_t PIXEL_REPETITION:4;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

190

uint32_t HSYNC_POSITIVE_POLARITY:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

191

uint32_t VSYNC_POSITIVE_POLARITY:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

192

uint32_t HORZ_COUNT_BY_TWO:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

204

uint32_t pixel_clock;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

206

uint32_t adjusted_pixel_clock;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

209

uint32_t reference_divider;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

212

uint32_t pixel_clock_post_divider;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

224

uint32_t target_pixel_clock_100hz;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

226

uint32_t reference_divider;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

228

uint32_t feedback_divider;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

230

uint32_t fractional_feedback_divider;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

232

uint32_t pixel_clock_post_divider;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

236

uint32_t dfs_bypass_display_clock;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

241

uint32_t FORCE_PROGRAMMING_OF_PLL:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

244

uint32_t USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

246

uint32_t SET_EXTERNAL_REF_DIV_SRC:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

248

uint32_t SET_DISPCLK_DFS_BYPASS:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

250

uint32_t PROGRAM_PHY_PLL_ONLY:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

252

uint32_t SUPPORT_YUV_420:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

254

uint32_t SET_XTALIN_REF_SRC:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

256

uint32_t SET_GENLOCK_REF_DIV_SRC:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

269

uint32_t target_clock_frequency;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

274

uint32_t USE_GENERICA_AS_SOURCE_FOR_DPREFCLK:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

276

uint32_t USE_XTALIN_AS_SOURCE_FOR_DPREFCLK:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

278

uint32_t USE_PCIE_AS_SOURCE_FOR_DPREFCLK:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

280

uint32_t USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

286

uint32_t CENTER_SPREAD:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

288

uint32_t EXTERNAL_SS:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

290

uint32_t DS_TYPE:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

295

uint32_t percentage;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

296

uint32_t ds_frac_amount;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

300

uint32_t step;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

301

uint32_t delay;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

302

uint32_t range; /* In Hz unit */

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

305

uint32_t feedback_amount;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

306

uint32_t nfrac_amount;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

307

uint32_t ds_frac_size;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

315

uint32_t INTERNAL_DISPLAY : 1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

316

uint32_t INTERNAL_DISPLAY_BL : 1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

320

uint32_t DP_HBR2_CAP:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

321

uint32_t DP_HBR2_EN:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

322

uint32_t DP_HBR3_EN:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

323

uint32_t HDMI_6GB_EN:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

324

uint32_t IS_DP2_CAPABLE:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

325

uint32_t DP_UHBR10_EN:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

326

uint32_t DP_UHBR13_5_EN:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

327

uint32_t DP_UHBR20_EN:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

328

uint32_t DP_IS_USB_C:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

329

uint32_t RESERVED:27;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

333

uint32_t dram_clock_change_latency_100ns;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

334

uint32_t dram_sr_exit_latency_100ns;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

335

uint32_t dram_sr_enter_exit_latency_100ns;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

339

uint32_t DP_HBR2_EN:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

340

uint32_t DP_HBR3_EN:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

341

uint32_t HDMI_6GB_EN:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

342

uint32_t DP_UHBR10_EN:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

343

uint32_t DP_UHBR13_5_EN:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

344

uint32_t DP_UHBR20_EN:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

345

uint32_t DP_IS_USB_C:1;

sys/dev/pci/drm/amd/display/include/bios_parser_types.h

346

uint32_t RESERVED:28;

sys/dev/pci/drm/amd/display/include/ddc_service_types.h

106

uint32_t dp_link_lane_count;

sys/dev/pci/drm/amd/display/include/ddc_service_types.h

107

uint32_t dp_link_rate;

sys/dev/pci/drm/amd/display/include/ddc_service_types.h

108

uint32_t dp_link_spead;

sys/dev/pci/drm/amd/display/include/ddc_service_types.h

82

uint32_t downstrm_sink_count;

sys/dev/pci/drm/amd/display/include/ddc_service_types.h

88

uint32_t additional_audio_delay;

sys/dev/pci/drm/amd/display/include/ddc_service_types.h

90

uint32_t audio_latency;

sys/dev/pci/drm/amd/display/include/ddc_service_types.h

92

uint32_t video_latency_interlace;

sys/dev/pci/drm/amd/display/include/ddc_service_types.h

94

uint32_t video_latency_progressive;

sys/dev/pci/drm/amd/display/include/ddc_service_types.h

96

uint32_t max_hdmi_pixel_clock;

sys/dev/pci/drm/amd/display/include/gpio_interface.h

46

uint32_t *value);

sys/dev/pci/drm/amd/display/include/gpio_interface.h

51

uint32_t value);

sys/dev/pci/drm/amd/display/include/gpio_interface.h

75

uint32_t dal_gpio_get_enum(

sys/dev/pci/drm/amd/display/include/gpio_service_interface.h

38

uint32_t en,

sys/dev/pci/drm/amd/display/include/gpio_service_interface.h

51

uint32_t offset,

sys/dev/pci/drm/amd/display/include/gpio_service_interface.h

52

uint32_t mask);

sys/dev/pci/drm/amd/display/include/gpio_service_interface.h

56

uint32_t offset,

sys/dev/pci/drm/amd/display/include/gpio_service_interface.h

57

uint32_t mask);

sys/dev/pci/drm/amd/display/include/gpio_service_interface.h

69

uint32_t en);

sys/dev/pci/drm/amd/display/include/gpio_service_interface.h

73

uint32_t offset,

sys/dev/pci/drm/amd/display/include/gpio_service_interface.h

74

uint32_t mask,

sys/dev/pci/drm/amd/display/include/gpio_service_interface.h

99

uint32_t en);

sys/dev/pci/drm/amd/display/include/gpio_types.h

299

uint32_t delay_on_connect; /* milliseconds */

sys/dev/pci/drm/amd/display/include/gpio_types.h

300

uint32_t delay_on_disconnect; /* milliseconds */

sys/dev/pci/drm/amd/display/include/gpio_types.h

319

uint32_t gsl_group;

sys/dev/pci/drm/amd/display/include/gpio_types.h

77

uint32_t offset;

sys/dev/pci/drm/amd/display/include/gpio_types.h

78

uint32_t offset_y;

sys/dev/pci/drm/amd/display/include/gpio_types.h

79

uint32_t offset_en;

sys/dev/pci/drm/amd/display/include/gpio_types.h

80

uint32_t offset_mask;

sys/dev/pci/drm/amd/display/include/gpio_types.h

82

uint32_t mask;

sys/dev/pci/drm/amd/display/include/gpio_types.h

83

uint32_t mask_y;

sys/dev/pci/drm/amd/display/include/gpio_types.h

84

uint32_t mask_en;

sys/dev/pci/drm/amd/display/include/gpio_types.h

85

uint32_t mask_mask;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

104

uint32_t acpi_device;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

110

uint32_t HORIZONTAL_CUT_OFF:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

112

uint32_t H_SYNC_POLARITY:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

114

uint32_t V_SYNC_POLARITY:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

115

uint32_t VERTICAL_CUT_OFF:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

116

uint32_t H_REPLICATION_BY2:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

117

uint32_t V_REPLICATION_BY2:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

118

uint32_t COMPOSITE_SYNC:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

119

uint32_t INTERLACE:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

120

uint32_t DOUBLE_CLOCK:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

121

uint32_t RGB888:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

122

uint32_t GREY_LEVEL:2;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

123

uint32_t SPATIAL:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

124

uint32_t TEMPORAL:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

125

uint32_t API_ENABLED:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

128

uint32_t pixel_clk; /* in KHz */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

129

uint32_t horizontal_addressable;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

130

uint32_t horizontal_blanking_time;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

131

uint32_t vertical_addressable;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

132

uint32_t vertical_blanking_time;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

133

uint32_t horizontal_sync_offset;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

134

uint32_t horizontal_sync_width;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

135

uint32_t vertical_sync_offset;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

136

uint32_t vertical_sync_width;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

137

uint32_t horizontal_border;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

138

uint32_t vertical_border;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

142

uint32_t REFRESH_RATE_30HZ:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

143

uint32_t REFRESH_RATE_40HZ:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

144

uint32_t REFRESH_RATE_48HZ:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

145

uint32_t REFRESH_RATE_50HZ:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

146

uint32_t REFRESH_RATE_60HZ:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

151

uint32_t ss_id;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

153

uint32_t drr_enabled;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

154

uint32_t min_drr_refresh_rate;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

160

uint32_t crystal_frequency; /* in KHz */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

161

uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

162

uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

163

uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

164

uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

168

uint32_t memory_clk_ss_percentage;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

169

uint32_t engine_clk_ss_percentage;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

172

uint32_t default_display_engine_pll_frequency; /* in KHz */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

173

uint32_t external_clock_source_frequency_for_dp; /* in KHz */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

174

uint32_t smu_gpu_pll_output_freq; /* in KHz */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

177

uint32_t default_memory_clk; /* in KHz */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

178

uint32_t default_engine_clk; /* in KHz */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

179

uint32_t dp_phy_ref_clk; /* in KHz - DCE12 only */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

180

uint32_t i2c_engine_ref_clk; /* in KHz - DCE12 only */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

192

uint32_t step;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

193

uint32_t delay;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

194

uint32_t recommended_ref_div;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

206

uint32_t spread_spectrum_percentage;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

207

uint32_t spread_percentage_divider; /* 100 or 1000 */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

208

uint32_t spread_spectrum_range; /* modulation freq (HZ)*/

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

215

uint32_t target_clock_range; /* in KHz */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

221

uint32_t dp_hbr2_cap:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

222

uint32_t dp_hbr2_validated:1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

226

uint32_t reserved:15;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

230

uint32_t gpio_id;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

303

uint32_t voltage_index;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

305

uint32_t max_supported_clk; /* in KHz */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

311

uint32_t device_tag;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

313

uint32_t device_acpi_enum;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

336

uint32_t supported_s_clk; /* in KHz */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

338

uint32_t voltage_index;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

340

uint32_t voltage_id;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

345

uint32_t boot_up_engine_clock; /* in KHz */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

346

uint32_t dentist_vco_freq; /* in KHz */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

347

uint32_t boot_up_uma_clock; /* in KHz */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

348

uint32_t boot_up_req_display_vector;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

349

uint32_t other_display_misc;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

350

uint32_t gpu_cap_info;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

351

uint32_t sb_mmio_base_addr;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

352

uint32_t system_config;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

353

uint32_t cpu_cap_info;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

354

uint32_t max_nb_voltage;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

355

uint32_t min_nb_voltage;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

356

uint32_t boot_up_nb_voltage;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

357

uint32_t ext_disp_conn_info_offset;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

358

uint32_t csr_m3_arb_cntl_default[NUMBER_OF_CSR_M3_ARB];

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

359

uint32_t csr_m3_arb_cntl_uvd[NUMBER_OF_CSR_M3_ARB];

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

360

uint32_t csr_m3_arb_cntl_fs3d[NUMBER_OF_CSR_M3_ARB];

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

361

uint32_t gmc_restore_reset_time;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

362

uint32_t minimum_n_clk;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

363

uint32_t idle_n_clk;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

364

uint32_t ddr_dll_power_up_time;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

365

uint32_t ddr_pll_power_up_time;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

367

uint32_t pcie_clk_ss_type;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

368

uint32_t lvds_ss_percentage;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

369

uint32_t lvds_sspread_rate_in_10hz;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

370

uint32_t hdmi_ss_percentage;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

371

uint32_t hdmi_sspread_rate_in_10hz;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

372

uint32_t dvi_ss_percentage;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

373

uint32_t dvi_sspread_rate_in_10_hz;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

374

uint32_t sclk_dpm_boost_margin;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

375

uint32_t sclk_dpm_throttle_margin;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

376

uint32_t sclk_dpm_tdp_limit_pg;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

377

uint32_t sclk_dpm_tdp_limit_boost;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

378

uint32_t boost_engine_clock;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

379

uint32_t boost_vid_2bit;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

380

uint32_t enable_boost;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

381

uint32_t gnb_tdp_limit;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

383

uint32_t max_lvds_pclk_freq_in_single_link;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

384

uint32_t lvds_misc;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

385

uint32_t lvds_pwr_on_seq_dig_on_to_de_in_4ms;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

386

uint32_t lvds_pwr_on_seq_de_to_vary_bl_in_4ms;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

387

uint32_t lvds_pwr_off_seq_vary_bl_to_de_in4ms;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

388

uint32_t lvds_pwr_off_seq_de_to_dig_on_in4ms;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

389

uint32_t lvds_off_to_on_delay_in_4ms;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

390

uint32_t lvds_pwr_on_seq_vary_bl_to_blon_in_4ms;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

391

uint32_t lvds_pwr_off_seq_blon_to_vary_bl_in_4ms;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

392

uint32_t lvds_reserved1;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

393

uint32_t lvds_bit_depth_control_val;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

416

uint32_t dp_ss_control;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

420

uint32_t gpuclk_ss_percentage;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

421

uint32_t gpuclk_ss_type;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

437

uint32_t min_signal_level;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

438

uint32_t max_signal_level;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

67

uint32_t enum_id:16; /* 1 based enum */

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

73

uint32_t clk_mask_register_index;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

74

uint32_t clk_en_register_index;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

75

uint32_t clk_y_register_index;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

76

uint32_t clk_a_register_index;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

77

uint32_t data_mask_register_index;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

78

uint32_t data_en_register_index;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

79

uint32_t data_y_register_index;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

80

uint32_t data_a_register_index;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

82

uint32_t clk_mask_shift;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

83

uint32_t clk_en_shift;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

84

uint32_t clk_y_shift;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

85

uint32_t clk_a_shift;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

86

uint32_t data_mask_shift;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

87

uint32_t data_en_shift;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

88

uint32_t data_y_shift;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

89

uint32_t data_a_shift;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

93

uint32_t i2c_line;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

94

uint32_t i2c_engine_id;

sys/dev/pci/drm/amd/display/include/grph_object_ctrl_defs.h

95

uint32_t i2c_slave_address;

sys/dev/pci/drm/amd/display/include/grph_object_id.h

228

uint32_t id:8;

sys/dev/pci/drm/amd/display/include/grph_object_id.h

231

uint32_t reserved:16; /* for padding. total size should be u32 */

sys/dev/pci/drm/amd/display/include/grph_object_id.h

237

uint32_t id,

sys/dev/pci/drm/amd/display/include/grph_object_id.h

249

static inline uint32_t dal_graphics_object_id_to_uint(

sys/dev/pci/drm/amd/display/include/hdcp_msg_types.h

102

uint32_t length;

sys/dev/pci/drm/amd/display/include/irq_service_interface.h

48

uint32_t src_id,

sys/dev/pci/drm/amd/display/include/irq_service_interface.h

49

uint32_t ext_id);

sys/dev/pci/drm/amd/display/include/link_service_types.h

85

uint32_t eq_wait_time_limit;

sys/dev/pci/drm/amd/display/include/link_service_types.h

87

uint32_t cds_wait_time_limit;

sys/dev/pci/drm/amd/display/include/vector.h

100

uint32_t index);

sys/dev/pci/drm/amd/display/include/vector.h

102

uint32_t dal_vector_capacity(const struct vector *vector);

sys/dev/pci/drm/amd/display/include/vector.h

104

bool dal_vector_reserve(struct vector *vector, uint32_t capacity);

sys/dev/pci/drm/amd/display/include/vector.h

116

uint32_t position) \

sys/dev/pci/drm/amd/display/include/vector.h

136

uint32_t index) \

sys/dev/pci/drm/amd/display/include/vector.h

145

uint32_t index) \

sys/dev/pci/drm/amd/display/include/vector.h

31

uint32_t struct_size;

sys/dev/pci/drm/amd/display/include/vector.h

32

uint32_t count;

sys/dev/pci/drm/amd/display/include/vector.h

33

uint32_t capacity;

sys/dev/pci/drm/amd/display/include/vector.h

40

uint32_t capacity,

sys/dev/pci/drm/amd/display/include/vector.h

41

uint32_t struct_size);

sys/dev/pci/drm/amd/display/include/vector.h

45

uint32_t capacity,

sys/dev/pci/drm/amd/display/include/vector.h

46

uint32_t struct_size);

sys/dev/pci/drm/amd/display/include/vector.h

52

uint32_t size,

sys/dev/pci/drm/amd/display/include/vector.h

54

uint32_t struct_size);

sys/dev/pci/drm/amd/display/include/vector.h

62

uint32_t dal_vector_get_count(

sys/dev/pci/drm/amd/display/include/vector.h

75

uint32_t position);

sys/dev/pci/drm/amd/display/include/vector.h

84

uint32_t index);

sys/dev/pci/drm/amd/display/include/vector.h

89

uint32_t index);

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1047

uint32_t hw_points_num,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1052

uint32_t i;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1181

uint32_t hw_points_num,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1184

uint32_t i;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1186

uint32_t begin_index, end_index;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1230

uint32_t hw_points_num,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1232

uint32_t sdr_white_level, uint32_t max_luminance_nits)

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1234

uint32_t i;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1253

uint32_t hw_points_num,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1255

uint32_t sdr_white_level, uint32_t max_luminance_nits)

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1257

uint32_t i;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1282

uint32_t i;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1342

uint32_t i;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1423

uint32_t num_hw_points,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1498

uint32_t numberof_points,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1504

uint32_t i = 0;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1541

uint32_t hw_points_num,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1545

uint32_t i = 0;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1565

uint32_t number_of_points,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1570

uint32_t max_entries = 3 - 1;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1572

uint32_t i = 0;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1602

uint32_t hw_points_num,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1605

uint32_t i = 0;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1629

uint32_t hw_points_num,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1681

uint32_t i;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

169

uint32_t seg_offset;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

170

uint32_t index;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1832

uint32_t sdr_ref_white_level,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1835

uint32_t i;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

275

uint32_t sdr_white_level, uint32_t max_luminance_nits)

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

306

uint32_t sdr_white_level, uint32_t max_luminance_nits)

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

369

uint32_t begin_index, end_index;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

401

uint32_t i = 0;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

402

uint32_t index = 0;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

579

uint32_t color_index,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

599

uint32_t color_index)

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

616

uint32_t *index_to_start,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

617

uint32_t *index_left,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

618

uint32_t *index_right,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

621

const uint32_t max_number = ramp->num_entries + 3;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

625

uint32_t i = *index_to_start;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

696

uint32_t number_of_points)

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

698

uint32_t i = 0;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

703

uint32_t index_to_start = 0;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

704

uint32_t index_left = 0;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

705

uint32_t index_right = 0;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

786

uint32_t max_index)

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

845

uint32_t hw_points_num,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

847

uint32_t sdr_white_level)

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

849

uint32_t i, start_index;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

896

uint32_t hw_points_num,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

899

uint32_t i;

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

924

uint32_t hw_points_num,

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

929

uint32_t i;

sys/dev/pci/drm/amd/display/modules/color/luts_1d.h

31

uint32_t custom_float_x;

sys/dev/pci/drm/amd/display/modules/color/luts_1d.h

32

uint32_t custom_float_y;

sys/dev/pci/drm/amd/display/modules/color/luts_1d.h

33

uint32_t custom_float_slope;

sys/dev/pci/drm/amd/display/modules/color/luts_1d.h

37

uint32_t red;

sys/dev/pci/drm/amd/display/modules/color/luts_1d.h

38

uint32_t green;

sys/dev/pci/drm/amd/display/modules/color/luts_1d.h

39

uint32_t blue;

sys/dev/pci/drm/amd/display/modules/color/luts_1d.h

40

uint32_t delta_red;

sys/dev/pci/drm/amd/display/modules/color/luts_1d.h

41

uint32_t delta_green;

sys/dev/pci/drm/amd/display/modules/color/luts_1d.h

42

uint32_t delta_blue;

sys/dev/pci/drm/amd/display/modules/color/luts_1d.h

49

uint32_t hw_points_num;

sys/dev/pci/drm/amd/display/modules/freesync/freesync.c

195

uint32_t h_total_up_scaled;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

179

uint32_t id;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

188

uint32_t stay_count;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

325

void mod_hdcp_dump_binary_message(uint8_t *msg, uint32_t msg_size,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp.h

326

uint8_t *buf, uint32_t buf_size);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

117

static const uint32_t hdcp_dpcd_addrs[] = {

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

155

uint32_t buf_len)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

158

uint32_t cur_size = 0;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

159

uint32_t data_offset = 0;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

193

(uint32_t)buf_len);

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

202

uint32_t buf_len,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

206

uint32_t cur_size = 0;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

207

uint32_t data_offset = 0;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

226

uint32_t buf_len)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

229

uint32_t cur_size = 0;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

230

uint32_t data_offset = 0;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

266

(uint32_t)(buf_len+1));

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

511

uint32_t device_count = 0;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

512

uint32_t rx_id_list_size = 0;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

513

uint32_t bytes_read = 0;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

680

uint32_t size = 1;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_ddc.c

683

uint32_t cp_irq_addrs = (hdcp->connection.link.dp.rev >= 0x14)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.c

29

void mod_hdcp_dump_binary_message(uint8_t *msg, uint32_t msg_size,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.c

30

uint8_t *buf, uint32_t buf_size)

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.c

36

uint32_t line_count = msg_size / bytes_per_line,

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.c

38

uint32_t target_size = (byte_size * bytes_per_line + newline_size) * line_count +

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.c

40

uint32_t buf_pos = 0;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_log.c

41

uint32_t i = 0;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

110

uint32_t display_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

111

uint32_t is_active;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

112

uint32_t is_miracast;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

113

uint32_t controller;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

114

uint32_t ddc_line;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

115

uint32_t link_enc;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

116

uint32_t stream_enc;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

117

uint32_t dp_mst_vcid;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

118

uint32_t is_assr;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

119

uint32_t max_hdcp_supported_version;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

121

uint32_t phy_id;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

122

uint32_t link_hdcp_cap;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

124

uint32_t dio_output_id;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

128

uint32_t display_topology_dig_be_index;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

144

uint32_t reserved;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

148

uint32_t cmd_id;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

149

uint32_t resp_id;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

151

uint32_t reserved;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

331

uint32_t session_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

341

uint32_t session_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

345

uint32_t session_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

358

uint32_t session_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

361

uint32_t ksv_list_size;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

371

uint32_t session_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

375

uint32_t session_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

376

uint32_t display_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

380

uint32_t session_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

384

uint32_t protection_level;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

388

uint32_t display_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

393

uint32_t session_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

397

uint32_t session_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

402

uint32_t msg_size;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

413

uint32_t hdcp_version;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

414

uint32_t is_km_stored;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

415

uint32_t is_locality_precompute_support;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

416

uint32_t is_repeater;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

436

uint32_t session_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

442

uint32_t authentication_status;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

448

uint32_t session_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

452

uint32_t session_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

457

uint32_t protection_level;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

461

uint32_t session_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

462

uint32_t display_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

466

uint32_t srm_buf_size;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

472

uint32_t srm_version;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

476

uint32_t srm_version;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

477

uint32_t srm_buf_size;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

517

uint32_t cmd_id;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

519

uint32_t reserved;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

78

uint32_t display_handle;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

79

uint32_t is_active;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

80

uint32_t is_miracast;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

81

uint32_t controller;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

82

uint32_t ddc_line;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

83

uint32_t dig_be;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

84

uint32_t dig_fe;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

85

uint32_t dp_mst_vcid;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

86

uint32_t is_assr;

sys/dev/pci/drm/amd/display/modules/hdcp/hdcp_psp.h

87

uint32_t max_hdcp_supported_version;

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

65

uint32_t mid_point_in_us;

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

66

uint32_t inserted_duration_in_us;

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

67

uint32_t frames_to_insert;

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

68

uint32_t frame_counter;

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

69

uint32_t margin_in_us;

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

76

uint32_t target_refresh_in_uhz;

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

77

uint32_t frame_counter;

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

84

uint32_t flip_interval_detect_counter;

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

85

uint32_t vsyncs_between_flip;

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

86

uint32_t vsync_to_flip_in_us;

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

87

uint32_t v_update_timestamp_in_us;

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

95

uint32_t min_refresh_in_uhz;

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

96

uint32_t max_duration_in_us;

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

97

uint32_t max_refresh_in_uhz;

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

98

uint32_t min_duration_in_us;

sys/dev/pci/drm/amd/display/modules/inc/mod_freesync.h

99

uint32_t fixed_refresh_in_uhz;

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

140

uint32_t size;

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

144

uint32_t address;

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

146

uint32_t size;

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

153

uint32_t address,

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

156

uint32_t size);

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

158

uint32_t address,

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

160

uint32_t size);

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

162

uint32_t address,

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

164

uint32_t size);

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

166

uint32_t address,

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

168

uint32_t size);

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

174

uint32_t poll_timeout_us,

sys/dev/pci/drm/amd/display/modules/inc/mod_hdcp.h

182

uint32_t poll_timeout_us,

sys/dev/pci/drm/amd/display/modules/info_packet/info_packet.c

457

uint32_t i = 0;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

700

uint32_t i, j = 0;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

980

uint32_t vtotal)

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

994

uint32_t vtotal)

sys/dev/pci/drm/amd/display/modules/power/power_helpers.h

59

uint32_t vtotal);

sys/dev/pci/drm/amd/display/modules/power/power_helpers.h

62

uint32_t vtotal);

sys/dev/pci/drm/amd/include/amd_cper.h

103

uint32_t signature_end; /* 0xFFFFFFFF */

sys/dev/pci/drm/amd/include/amd_cper.h

108

uint32_t platform_id : 1;

sys/dev/pci/drm/amd/include/amd_cper.h

109

uint32_t timestamp : 1;

sys/dev/pci/drm/amd/include/amd_cper.h

110

uint32_t partition_id : 1;

sys/dev/pci/drm/amd/include/amd_cper.h

111

uint32_t reserved : 29;

sys/dev/pci/drm/amd/include/amd_cper.h

113

uint32_t valid_mask;

sys/dev/pci/drm/amd/include/amd_cper.h

115

uint32_t record_length; /* Total size of CPER Entry */

sys/dev/pci/drm/amd/include/amd_cper.h

122

uint32_t flags; /* Reserved */

sys/dev/pci/drm/amd/include/amd_cper.h

128

uint32_t sec_offset; /* Offset from the start of CPER entry */

sys/dev/pci/drm/amd/include/amd_cper.h

129

uint32_t sec_length;

sys/dev/pci/drm/amd/include/amd_cper.h

143

uint32_t primary : 1;

sys/dev/pci/drm/amd/include/amd_cper.h

144

uint32_t reserved1 : 2;

sys/dev/pci/drm/amd/include/amd_cper.h

145

uint32_t exceed_err_threshold : 1;

sys/dev/pci/drm/amd/include/amd_cper.h

146

uint32_t latent_err : 1;

sys/dev/pci/drm/amd/include/amd_cper.h

147

uint32_t reserved2 : 27;

sys/dev/pci/drm/amd/include/amd_cper.h

149

uint32_t flag_mask;

sys/dev/pci/drm/amd/include/amd_cper.h

212

uint32_t msr_addr;

sys/dev/pci/drm/amd/include/amd_cper.h

214

uint32_t reg_dump[CPER_ACA_REG_COUNT];

sys/dev/pci/drm/amd/include/amd_cper.h

231

uint32_t status_lo;

sys/dev/pci/drm/amd/include/amd_cper.h

232

uint32_t status_hi;

sys/dev/pci/drm/amd/include/amd_cper.h

233

uint32_t addr_lo;

sys/dev/pci/drm/amd/include/amd_cper.h

234

uint32_t addr_hi;

sys/dev/pci/drm/amd/include/amd_cper.h

235

uint32_t ipid_lo;

sys/dev/pci/drm/amd/include/amd_cper.h

236

uint32_t ipid_hi;

sys/dev/pci/drm/amd/include/amd_cper.h

237

uint32_t synd_lo;

sys/dev/pci/drm/amd/include/amd_cper.h

238

uint32_t synd_hi;

sys/dev/pci/drm/amd/include/amd_cper.h

244

uint32_t reserved1;

sys/dev/pci/drm/amd/include/amd_cper.h

252

uint32_t reserved1;

sys/dev/pci/drm/amd/include/amd_pcie_helpers.h

28

static inline bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap)

sys/dev/pci/drm/amd/include/amd_pcie_helpers.h

36

static inline bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap)

sys/dev/pci/drm/amd/include/amd_pcie_helpers.h

45

static inline uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap,

sys/dev/pci/drm/amd/include/amd_pcie_helpers.h

48

uint32_t asic_pcie_link_speed_cap = (pcie_link_speed_cap &

sys/dev/pci/drm/amd/include/amd_pcie_helpers.h

50

uint32_t sys_pcie_link_speed_cap = (pcie_link_speed_cap &

sys/dev/pci/drm/amd/include/amd_pcie_helpers.h

76

static inline uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap,

sys/dev/pci/drm/amd/include/amdgpu_reg_state.h

106

uint32_t sub_bus_number_latency;

sys/dev/pci/drm/amd/include/amdgpu_reg_state.h

107

uint32_t pcie_corr_err_status;

sys/dev/pci/drm/amd/include/amdgpu_reg_state.h

108

uint32_t pcie_uncorr_err_status;

sys/dev/pci/drm/amd/include/amdgpu_reg_state.h

63

uint32_t value;

sys/dev/pci/drm/amd/include/amdgpu_reg_state.h

64

uint32_t pad;

sys/dev/pci/drm/amd/include/atom-bits.h

40

static inline uint32_t get_u32(void *bios, int ptr)

sys/dev/pci/drm/amd/include/atom-bits.h

42

return get_u16(bios, ptr)|(((uint32_t)get_u16(bios, ptr+2))<<16);

sys/dev/pci/drm/amd/include/atom-types.h

31

typedef uint32_t ULONG;

sys/dev/pci/drm/amd/include/atomfirmware.h

1063

uint32_t display_caps;

sys/dev/pci/drm/amd/include/atomfirmware.h

1064

uint32_t bootup_dispclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

1095

uint32_t display_caps;

sys/dev/pci/drm/amd/include/atomfirmware.h

1096

uint32_t bootup_dispclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

1129

uint32_t display_caps;

sys/dev/pci/drm/amd/include/atomfirmware.h

1130

uint32_t bootup_dispclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

1162

uint32_t display_caps;

sys/dev/pci/drm/amd/include/atomfirmware.h

1163

uint32_t bootup_dispclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

1190

uint32_t dispclk_pll_vco_freq;

sys/dev/pci/drm/amd/include/atomfirmware.h

1191

uint32_t dp_ref_clk_freq;

sys/dev/pci/drm/amd/include/atomfirmware.h

1192

uint32_t max_mclk_chg_lat; // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us)

sys/dev/pci/drm/amd/include/atomfirmware.h

1193

uint32_t max_sr_exit_lat; // Worst case memory self refresh exit time, units of 100ns of ns (0.1us)

sys/dev/pci/drm/amd/include/atomfirmware.h

1194

uint32_t max_sr_enter_exit_lat; // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us)

sys/dev/pci/drm/amd/include/atomfirmware.h

1197

uint32_t reserved3[3];

sys/dev/pci/drm/amd/include/atomfirmware.h

1202

uint32_t aux_dphy_rx_control0_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1203

uint32_t aux_dphy_tx_control_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1204

uint32_t aux_dphy_rx_control1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1205

uint32_t dc_gpio_aux_ctrl_0_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1206

uint32_t dc_gpio_aux_ctrl_1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1207

uint32_t dc_gpio_aux_ctrl_2_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1208

uint32_t dc_gpio_aux_ctrl_3_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1209

uint32_t dc_gpio_aux_ctrl_4_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1210

uint32_t dc_gpio_aux_ctrl_5_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1211

uint32_t reserved[23];

sys/dev/pci/drm/amd/include/atomfirmware.h

1229

uint32_t display_caps;

sys/dev/pci/drm/amd/include/atomfirmware.h

1230

uint32_t bootup_dispclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

1261

uint32_t dispclk_pll_vco_freq;

sys/dev/pci/drm/amd/include/atomfirmware.h

1262

uint32_t dp_ref_clk_freq;

sys/dev/pci/drm/amd/include/atomfirmware.h

1264

uint32_t max_mclk_chg_lat;

sys/dev/pci/drm/amd/include/atomfirmware.h

1266

uint32_t max_sr_exit_lat;

sys/dev/pci/drm/amd/include/atomfirmware.h

1268

uint32_t max_sr_enter_exit_lat;

sys/dev/pci/drm/amd/include/atomfirmware.h

1271

uint32_t aux_dphy_rx_control0_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1272

uint32_t aux_dphy_tx_control_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1273

uint32_t aux_dphy_rx_control1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1274

uint32_t dc_gpio_aux_ctrl_0_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1275

uint32_t dc_gpio_aux_ctrl_1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1276

uint32_t dc_gpio_aux_ctrl_2_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1277

uint32_t dc_gpio_aux_ctrl_3_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1278

uint32_t dc_gpio_aux_ctrl_4_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1279

uint32_t dc_gpio_aux_ctrl_5_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1280

uint32_t reserved[26];

sys/dev/pci/drm/amd/include/atomfirmware.h

1339

uint32_t param;

sys/dev/pci/drm/amd/include/atomfirmware.h

1362

uint32_t versionCode;

sys/dev/pci/drm/amd/include/atomfirmware.h

1366

uint32_t crc_val; // CRC

sys/dev/pci/drm/amd/include/atomfirmware.h

1372

uint32_t max_symclk_in10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

1418

uint32_t max_symclk_in10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

1461

uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def

sys/dev/pci/drm/amd/include/atomfirmware.h

1462

uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def

sys/dev/pci/drm/amd/include/atomfirmware.h

1463

uint32_t system_config;

sys/dev/pci/drm/amd/include/atomfirmware.h

1464

uint32_t cpucapinfo;

sys/dev/pci/drm/amd/include/atomfirmware.h

1504

uint32_t reserved[66];

sys/dev/pci/drm/amd/include/atomfirmware.h

1510

uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def

sys/dev/pci/drm/amd/include/atomfirmware.h

1511

uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def

sys/dev/pci/drm/amd/include/atomfirmware.h

1512

uint32_t system_config;

sys/dev/pci/drm/amd/include/atomfirmware.h

1513

uint32_t cpucapinfo;

sys/dev/pci/drm/amd/include/atomfirmware.h

1554

uint32_t reserved[63];

sys/dev/pci/drm/amd/include/atomfirmware.h

1563

uint32_t reserved2;

sys/dev/pci/drm/amd/include/atomfirmware.h

1570

uint32_t reserved4[3];

sys/dev/pci/drm/amd/include/atomfirmware.h

1576

uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def

sys/dev/pci/drm/amd/include/atomfirmware.h

1577

uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def

sys/dev/pci/drm/amd/include/atomfirmware.h

1578

uint32_t system_config;

sys/dev/pci/drm/amd/include/atomfirmware.h

1579

uint32_t cpucapinfo;

sys/dev/pci/drm/amd/include/atomfirmware.h

1591

uint32_t reserved3[8];

sys/dev/pci/drm/amd/include/atomfirmware.h

1597

uint32_t reserved4[6];//reserve 2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset)

sys/dev/pci/drm/amd/include/atomfirmware.h

1603

uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset)

sys/dev/pci/drm/amd/include/atomfirmware.h

1608

uint32_t reserved6[30];// reserve size of(atom_camera_data) for camera_info

sys/dev/pci/drm/amd/include/atomfirmware.h

1609

uint32_t reserved7[32];

sys/dev/pci/drm/amd/include/atomfirmware.h

1618

uint32_t reserved2;

sys/dev/pci/drm/amd/include/atomfirmware.h

1619

uint32_t speed_upto;

sys/dev/pci/drm/amd/include/atomfirmware.h

1632

uint32_t reserved4;

sys/dev/pci/drm/amd/include/atomfirmware.h

1633

uint32_t reserved5;

sys/dev/pci/drm/amd/include/atomfirmware.h

1634

uint32_t reserved6;

sys/dev/pci/drm/amd/include/atomfirmware.h

1645

uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def

sys/dev/pci/drm/amd/include/atomfirmware.h

1646

uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def

sys/dev/pci/drm/amd/include/atomfirmware.h

1647

uint32_t system_config;

sys/dev/pci/drm/amd/include/atomfirmware.h

1648

uint32_t cpucapinfo;

sys/dev/pci/drm/amd/include/atomfirmware.h

1660

uint32_t reserved3[8];

sys/dev/pci/drm/amd/include/atomfirmware.h

1663

uint32_t reserved4[189];

sys/dev/pci/drm/amd/include/atomfirmware.h

1682

uint32_t vbios_misc; // enum of atom_system_vbiosmisc_def

sys/dev/pci/drm/amd/include/atomfirmware.h

1683

uint32_t gpucapinfo; // enum of atom_system_gpucapinf_def

sys/dev/pci/drm/amd/include/atomfirmware.h

1684

uint32_t system_config;

sys/dev/pci/drm/amd/include/atomfirmware.h

1685

uint32_t cpucapinfo;

sys/dev/pci/drm/amd/include/atomfirmware.h

1697

uint32_t reserved2[8];

sys/dev/pci/drm/amd/include/atomfirmware.h

1779

uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable

sys/dev/pci/drm/amd/include/atomfirmware.h

1800

uint32_t regaddr_cp_dma_src_addr;

sys/dev/pci/drm/amd/include/atomfirmware.h

1801

uint32_t regaddr_cp_dma_src_addr_hi;

sys/dev/pci/drm/amd/include/atomfirmware.h

1802

uint32_t regaddr_cp_dma_dst_addr;

sys/dev/pci/drm/amd/include/atomfirmware.h

1803

uint32_t regaddr_cp_dma_dst_addr_hi;

sys/dev/pci/drm/amd/include/atomfirmware.h

1804

uint32_t regaddr_cp_dma_command;

sys/dev/pci/drm/amd/include/atomfirmware.h

1805

uint32_t regaddr_cp_status;

sys/dev/pci/drm/amd/include/atomfirmware.h

1806

uint32_t regaddr_rlc_gpu_clock_32;

sys/dev/pci/drm/amd/include/atomfirmware.h

1807

uint32_t rlc_gpu_timer_refclk;

sys/dev/pci/drm/amd/include/atomfirmware.h

1820

uint32_t regaddr_cp_dma_src_addr;

sys/dev/pci/drm/amd/include/atomfirmware.h

1821

uint32_t regaddr_cp_dma_src_addr_hi;

sys/dev/pci/drm/amd/include/atomfirmware.h

1822

uint32_t regaddr_cp_dma_dst_addr;

sys/dev/pci/drm/amd/include/atomfirmware.h

1823

uint32_t regaddr_cp_dma_dst_addr_hi;

sys/dev/pci/drm/amd/include/atomfirmware.h

1824

uint32_t regaddr_cp_dma_command;

sys/dev/pci/drm/amd/include/atomfirmware.h

1825

uint32_t regaddr_cp_status;

sys/dev/pci/drm/amd/include/atomfirmware.h

1826

uint32_t regaddr_rlc_gpu_clock_32;

sys/dev/pci/drm/amd/include/atomfirmware.h

1827

uint32_t rlc_gpu_timer_refclk;

sys/dev/pci/drm/amd/include/atomfirmware.h

1831

uint32_t rm21_sram_vmin_value;

sys/dev/pci/drm/amd/include/atomfirmware.h

1845

uint32_t regaddr_cp_dma_src_addr;

sys/dev/pci/drm/amd/include/atomfirmware.h

1846

uint32_t regaddr_cp_dma_src_addr_hi;

sys/dev/pci/drm/amd/include/atomfirmware.h

1847

uint32_t regaddr_cp_dma_dst_addr;

sys/dev/pci/drm/amd/include/atomfirmware.h

1848

uint32_t regaddr_cp_dma_dst_addr_hi;

sys/dev/pci/drm/amd/include/atomfirmware.h

1849

uint32_t regaddr_cp_dma_command;

sys/dev/pci/drm/amd/include/atomfirmware.h

1850

uint32_t regaddr_cp_status;

sys/dev/pci/drm/amd/include/atomfirmware.h

1851

uint32_t regaddr_rlc_gpu_clock_32;

sys/dev/pci/drm/amd/include/atomfirmware.h

1852

uint32_t rlc_gpu_timer_refclk;

sys/dev/pci/drm/amd/include/atomfirmware.h

1866

uint32_t sram_rm_fuses_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1867

uint32_t sram_custom_rm_fuses_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1880

uint32_t regaddr_cp_dma_src_addr;

sys/dev/pci/drm/amd/include/atomfirmware.h

1881

uint32_t regaddr_cp_dma_src_addr_hi;

sys/dev/pci/drm/amd/include/atomfirmware.h

1882

uint32_t regaddr_cp_dma_dst_addr;

sys/dev/pci/drm/amd/include/atomfirmware.h

1883

uint32_t regaddr_cp_dma_dst_addr_hi;

sys/dev/pci/drm/amd/include/atomfirmware.h

1884

uint32_t regaddr_cp_dma_command;

sys/dev/pci/drm/amd/include/atomfirmware.h

1885

uint32_t regaddr_cp_status;

sys/dev/pci/drm/amd/include/atomfirmware.h

1886

uint32_t regaddr_rlc_gpu_clock_32;

sys/dev/pci/drm/amd/include/atomfirmware.h

1887

uint32_t rlc_gpu_timer_refclk;

sys/dev/pci/drm/amd/include/atomfirmware.h

1901

uint32_t sram_rm_fuses_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1902

uint32_t sram_custom_rm_fuses_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1906

uint32_t gc_config;

sys/dev/pci/drm/amd/include/atomfirmware.h

1908

uint32_t reserved2[6];

sys/dev/pci/drm/amd/include/atomfirmware.h

1921

uint32_t regaddr_lsdma_queue0_rb_rptr;

sys/dev/pci/drm/amd/include/atomfirmware.h

1922

uint32_t regaddr_lsdma_queue0_rb_rptr_hi;

sys/dev/pci/drm/amd/include/atomfirmware.h

1923

uint32_t regaddr_lsdma_queue0_rb_wptr;

sys/dev/pci/drm/amd/include/atomfirmware.h

1924

uint32_t regaddr_lsdma_queue0_rb_wptr_hi;

sys/dev/pci/drm/amd/include/atomfirmware.h

1925

uint32_t regaddr_lsdma_command;

sys/dev/pci/drm/amd/include/atomfirmware.h

1926

uint32_t regaddr_lsdma_status;

sys/dev/pci/drm/amd/include/atomfirmware.h

1927

uint32_t regaddr_golden_tsc_count_lower;

sys/dev/pci/drm/amd/include/atomfirmware.h

1928

uint32_t golden_tsc_count_lower_refclk;

sys/dev/pci/drm/amd/include/atomfirmware.h

1933

uint32_t sram_rm_fuses_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1934

uint32_t sram_custom_rm_fuses_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1935

uint32_t inactive_sa_mask;

sys/dev/pci/drm/amd/include/atomfirmware.h

1936

uint32_t gc_config;

sys/dev/pci/drm/amd/include/atomfirmware.h

1939

uint32_t gdfll_as_wait_ctrl_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1940

uint32_t gdfll_as_step_ctrl_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

1941

uint32_t reserved[8];

sys/dev/pci/drm/amd/include/atomfirmware.h

1960

uint32_t core_refclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

1981

uint32_t core_refclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

1993

uint32_t gpupll_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

1994

uint32_t bootup_smnclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

1995

uint32_t bootup_socclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

1996

uint32_t bootup_mp0clk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

1997

uint32_t bootup_mp1clk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

1998

uint32_t bootup_lclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

1999

uint32_t bootup_dcefclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2000

uint32_t ctf_threshold_override_value;

sys/dev/pci/drm/amd/include/atomfirmware.h

2001

uint32_t reserved[5];

sys/dev/pci/drm/amd/include/atomfirmware.h

2014

uint32_t core_refclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2026

uint32_t gpupll_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2027

uint32_t bootup_smnclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2028

uint32_t bootup_socclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2029

uint32_t bootup_mp0clk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2030

uint32_t bootup_mp1clk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2031

uint32_t bootup_lclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2032

uint32_t bootup_dcefclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2033

uint32_t ctf_threshold_override_value;

sys/dev/pci/drm/amd/include/atomfirmware.h

2034

uint32_t syspll3_0_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2035

uint32_t syspll3_1_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2036

uint32_t bootup_fclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2037

uint32_t bootup_waflclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2038

uint32_t smu_info_caps;

sys/dev/pci/drm/amd/include/atomfirmware.h

2041

uint32_t reserved;

sys/dev/pci/drm/amd/include/atomfirmware.h

2055

uint32_t core_refclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2056

uint32_t syspll0_1_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2057

uint32_t syspll0_2_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2061

uint32_t syspll0_0_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2062

uint32_t bootup_smnclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2063

uint32_t bootup_socclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2064

uint32_t bootup_mp0clk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2065

uint32_t bootup_mp1clk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2066

uint32_t bootup_lclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2067

uint32_t bootup_dcefclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2068

uint32_t ctf_threshold_override_value;

sys/dev/pci/drm/amd/include/atomfirmware.h

2069

uint32_t syspll3_0_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2070

uint32_t syspll3_1_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2071

uint32_t bootup_fclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2072

uint32_t bootup_waflclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2073

uint32_t smu_info_caps;

sys/dev/pci/drm/amd/include/atomfirmware.h

2076

uint32_t bootup_dprefclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2077

uint32_t bootup_usbclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2078

uint32_t smb_slave_address;

sys/dev/pci/drm/amd/include/atomfirmware.h

2079

uint32_t cg_fdo_ctrl0_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2080

uint32_t cg_fdo_ctrl1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2081

uint32_t cg_fdo_ctrl2_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2082

uint32_t gdfll_as_wait_ctrl_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2083

uint32_t gdfll_as_step_ctrl_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2084

uint32_t bootup_dtbclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2085

uint32_t fclk_syspll_refclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2086

uint32_t smusvi_svc0_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2087

uint32_t smusvi_svc1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2088

uint32_t smusvi_svd0_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2089

uint32_t smusvi_svd1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2090

uint32_t smusvi_svt0_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2091

uint32_t smusvi_svt1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2092

uint32_t cg_tach_ctrl_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2093

uint32_t cg_pump_ctrl1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2094

uint32_t cg_pump_tach_ctrl_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2095

uint32_t thm_ctf_delay_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2096

uint32_t thm_thermal_int_ctrl_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2097

uint32_t thm_tmon_config_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2098

uint32_t reserved[16];

sys/dev/pci/drm/amd/include/atomfirmware.h

2112

uint32_t core_refclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2113

uint32_t syspll0_1_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2114

uint32_t syspll0_2_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2118

uint32_t syspll0_0_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2119

uint32_t bootup_smnclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2120

uint32_t bootup_socclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2121

uint32_t bootup_mp0clk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2122

uint32_t bootup_mp1clk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2123

uint32_t bootup_lclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2124

uint32_t bootup_dxioclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2125

uint32_t ctf_threshold_override_value;

sys/dev/pci/drm/amd/include/atomfirmware.h

2126

uint32_t syspll3_0_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2127

uint32_t syspll3_1_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2128

uint32_t bootup_fclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2129

uint32_t bootup_waflclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2130

uint32_t smu_info_caps;

sys/dev/pci/drm/amd/include/atomfirmware.h

2133

uint32_t bootup_gfxavsclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2134

uint32_t bootup_mpioclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2135

uint32_t smb_slave_address;

sys/dev/pci/drm/amd/include/atomfirmware.h

2136

uint32_t cg_fdo_ctrl0_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2137

uint32_t cg_fdo_ctrl1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2138

uint32_t cg_fdo_ctrl2_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2139

uint32_t gdfll_as_wait_ctrl_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2140

uint32_t gdfll_as_step_ctrl_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2141

uint32_t reserved_clk;

sys/dev/pci/drm/amd/include/atomfirmware.h

2142

uint32_t fclk_syspll_refclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2143

uint32_t smusvi_svc0_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2144

uint32_t smusvi_svc1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2145

uint32_t smusvi_svd0_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2146

uint32_t smusvi_svd1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2147

uint32_t smusvi_svt0_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2148

uint32_t smusvi_svt1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2149

uint32_t cg_tach_ctrl_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2150

uint32_t cg_pump_ctrl1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2151

uint32_t cg_pump_tach_ctrl_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2152

uint32_t thm_ctf_delay_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2153

uint32_t thm_thermal_int_ctrl_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2154

uint32_t thm_tmon_config_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2155

uint32_t bootup_vclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2156

uint32_t bootup_dclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2157

uint32_t smu_gpiopad_pu_en_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2158

uint32_t smu_gpiopad_pd_en_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2159

uint32_t reserved[12];

sys/dev/pci/drm/amd/include/atomfirmware.h

2164

uint32_t bootup_gfxclk_bypass_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2165

uint32_t bootup_usrclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2166

uint32_t bootup_csrclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2167

uint32_t core_refclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2168

uint32_t syspll1_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2169

uint32_t syspll2_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2173

uint32_t syspll0_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2174

uint32_t bootup_smnclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2175

uint32_t bootup_socclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2176

uint32_t bootup_mp0clk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2177

uint32_t bootup_mp1clk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2178

uint32_t bootup_lclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2179

uint32_t bootup_dcefclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2180

uint32_t ctf_threshold_override_value;

sys/dev/pci/drm/amd/include/atomfirmware.h

2181

uint32_t syspll3_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2182

uint32_t mm_syspll_vco_freq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2183

uint32_t bootup_fclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2184

uint32_t bootup_waflclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2185

uint32_t smu_info_caps;

sys/dev/pci/drm/amd/include/atomfirmware.h

2188

uint32_t bootup_dprefclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2189

uint32_t bootup_usbclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2190

uint32_t smb_slave_address;

sys/dev/pci/drm/amd/include/atomfirmware.h

2191

uint32_t cg_fdo_ctrl0_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2192

uint32_t cg_fdo_ctrl1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2193

uint32_t cg_fdo_ctrl2_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2194

uint32_t gdfll_as_wait_ctrl_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2195

uint32_t gdfll_as_step_ctrl_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2196

uint32_t bootup_dtbclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2197

uint32_t fclk_syspll_refclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2198

uint32_t smusvi_svc0_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2199

uint32_t smusvi_svc1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2200

uint32_t smusvi_svd0_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2201

uint32_t smusvi_svd1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2202

uint32_t smusvi_svt0_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2203

uint32_t smusvi_svt1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2204

uint32_t cg_tach_ctrl_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2205

uint32_t cg_pump_ctrl1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2206

uint32_t cg_pump_tach_ctrl_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2207

uint32_t thm_ctf_delay_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2208

uint32_t thm_thermal_int_ctrl_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2209

uint32_t thm_tmon_config_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2210

uint32_t smbus_timing_cntrl0_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2211

uint32_t smbus_timing_cntrl1_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2212

uint32_t smbus_timing_cntrl2_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2213

uint32_t pwr_disp_timer_global_control_val;

sys/dev/pci/drm/amd/include/atomfirmware.h

2214

uint32_t bootup_mpioclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2215

uint32_t bootup_dclk0_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2216

uint32_t bootup_vclk0_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2217

uint32_t bootup_dclk1_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2218

uint32_t bootup_vclk1_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2219

uint32_t bootup_baco400clk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2220

uint32_t bootup_baco1200clk_bypass_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2221

uint32_t bootup_baco700clk_bypass_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

2222

uint32_t reserved[16];

sys/dev/pci/drm/amd/include/atomfirmware.h

2310

uint32_t boardreserved[9];

sys/dev/pci/drm/amd/include/atomfirmware.h

2396

uint32_t boardreserved[10];

sys/dev/pci/drm/amd/include/atomfirmware.h

2400

uint32_t enabled;

sys/dev/pci/drm/amd/include/atomfirmware.h

2401

uint32_t slaveaddress;

sys/dev/pci/drm/amd/include/atomfirmware.h

2402

uint32_t controllerport;

sys/dev/pci/drm/amd/include/atomfirmware.h

2403

uint32_t controllername;

sys/dev/pci/drm/amd/include/atomfirmware.h

2404

uint32_t thermalthrottler;

sys/dev/pci/drm/amd/include/atomfirmware.h

2405

uint32_t i2cprotocol;

sys/dev/pci/drm/amd/include/atomfirmware.h

2406

uint32_t i2cspeed;

sys/dev/pci/drm/amd/include/atomfirmware.h

2412

uint32_t i2c_padding[3];

sys/dev/pci/drm/amd/include/atomfirmware.h

2484

uint32_t boardreserved[10];

sys/dev/pci/drm/amd/include/atomfirmware.h

2526

uint32_t SlaveAddress;

sys/dev/pci/drm/amd/include/atomfirmware.h

261

uint32_t pspdirtableoffset;

sys/dev/pci/drm/amd/include/atomfirmware.h

2612

uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)

sys/dev/pci/drm/amd/include/atomfirmware.h

2614

uint32_t BoardReserved[9];

sys/dev/pci/drm/amd/include/atomfirmware.h

2622

uint32_t i2c_padding[3]; // old i2c control are moved to new area

sys/dev/pci/drm/amd/include/atomfirmware.h

2684

uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask.

sys/dev/pci/drm/amd/include/atomfirmware.h

2701

uint32_t boardreserved[10];

sys/dev/pci/drm/amd/include/atomfirmware.h

2783

uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)

sys/dev/pci/drm/amd/include/atomfirmware.h

2803

uint32_t BoardReserved[5];

sys/dev/pci/drm/amd/include/atomfirmware.h

2861

uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)

sys/dev/pci/drm/amd/include/atomfirmware.h

2907

uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.

sys/dev/pci/drm/amd/include/atomfirmware.h

2925

uint32_t BoardReserved[16];

sys/dev/pci/drm/amd/include/atomfirmware.h

2952

uint32_t BoardVoltageCoeffA; // decode by /1000

sys/dev/pci/drm/amd/include/atomfirmware.h

2953

uint32_t BoardVoltageCoeffB; // decode by /1000

sys/dev/pci/drm/amd/include/atomfirmware.h

2979

uint32_t reserved[16];

sys/dev/pci/drm/amd/include/atomfirmware.h

2990

uint32_t maxvddc;

sys/dev/pci/drm/amd/include/atomfirmware.h

2991

uint32_t minvddc;

sys/dev/pci/drm/amd/include/atomfirmware.h

2992

uint32_t avfs_meannsigma_acontant0;

sys/dev/pci/drm/amd/include/atomfirmware.h

2993

uint32_t avfs_meannsigma_acontant1;

sys/dev/pci/drm/amd/include/atomfirmware.h

2994

uint32_t avfs_meannsigma_acontant2;

sys/dev/pci/drm/amd/include/atomfirmware.h

2998

uint32_t gb_vdroop_table_cksoff_a0;

sys/dev/pci/drm/amd/include/atomfirmware.h

2999

uint32_t gb_vdroop_table_cksoff_a1;

sys/dev/pci/drm/amd/include/atomfirmware.h

3000

uint32_t gb_vdroop_table_cksoff_a2;

sys/dev/pci/drm/amd/include/atomfirmware.h

3001

uint32_t gb_vdroop_table_ckson_a0;

sys/dev/pci/drm/amd/include/atomfirmware.h

3002

uint32_t gb_vdroop_table_ckson_a1;

sys/dev/pci/drm/amd/include/atomfirmware.h

3003

uint32_t gb_vdroop_table_ckson_a2;

sys/dev/pci/drm/amd/include/atomfirmware.h

3004

uint32_t avfsgb_fuse_table_cksoff_m1;

sys/dev/pci/drm/amd/include/atomfirmware.h

3005

uint32_t avfsgb_fuse_table_cksoff_m2;

sys/dev/pci/drm/amd/include/atomfirmware.h

3006

uint32_t avfsgb_fuse_table_cksoff_b;

sys/dev/pci/drm/amd/include/atomfirmware.h

3007

uint32_t avfsgb_fuse_table_ckson_m1;

sys/dev/pci/drm/amd/include/atomfirmware.h

3008

uint32_t avfsgb_fuse_table_ckson_m2;

sys/dev/pci/drm/amd/include/atomfirmware.h

3009

uint32_t avfsgb_fuse_table_ckson_b;

sys/dev/pci/drm/amd/include/atomfirmware.h

3018

uint32_t dispclk2gfxclk_a;

sys/dev/pci/drm/amd/include/atomfirmware.h

3019

uint32_t dispclk2gfxclk_b;

sys/dev/pci/drm/amd/include/atomfirmware.h

3020

uint32_t dispclk2gfxclk_c;

sys/dev/pci/drm/amd/include/atomfirmware.h

3021

uint32_t pixclk2gfxclk_a;

sys/dev/pci/drm/amd/include/atomfirmware.h

3022

uint32_t pixclk2gfxclk_b;

sys/dev/pci/drm/amd/include/atomfirmware.h

3023

uint32_t pixclk2gfxclk_c;

sys/dev/pci/drm/amd/include/atomfirmware.h

3024

uint32_t dcefclk2gfxclk_a;

sys/dev/pci/drm/amd/include/atomfirmware.h

3025

uint32_t dcefclk2gfxclk_b;

sys/dev/pci/drm/amd/include/atomfirmware.h

3026

uint32_t dcefclk2gfxclk_c;

sys/dev/pci/drm/amd/include/atomfirmware.h

3027

uint32_t phyclk2gfxclk_a;

sys/dev/pci/drm/amd/include/atomfirmware.h

3028

uint32_t phyclk2gfxclk_b;

sys/dev/pci/drm/amd/include/atomfirmware.h

3029

uint32_t phyclk2gfxclk_c;

sys/dev/pci/drm/amd/include/atomfirmware.h

3034

uint32_t maxvddc;

sys/dev/pci/drm/amd/include/atomfirmware.h

3035

uint32_t minvddc;

sys/dev/pci/drm/amd/include/atomfirmware.h

3036

uint32_t avfs_meannsigma_acontant0;

sys/dev/pci/drm/amd/include/atomfirmware.h

3037

uint32_t avfs_meannsigma_acontant1;

sys/dev/pci/drm/amd/include/atomfirmware.h

3038

uint32_t avfs_meannsigma_acontant2;

sys/dev/pci/drm/amd/include/atomfirmware.h

3042

uint32_t gb_vdroop_table_cksoff_a0;

sys/dev/pci/drm/amd/include/atomfirmware.h

3043

uint32_t gb_vdroop_table_cksoff_a1;

sys/dev/pci/drm/amd/include/atomfirmware.h

3044

uint32_t gb_vdroop_table_cksoff_a2;

sys/dev/pci/drm/amd/include/atomfirmware.h

3045

uint32_t gb_vdroop_table_ckson_a0;

sys/dev/pci/drm/amd/include/atomfirmware.h

3046

uint32_t gb_vdroop_table_ckson_a1;

sys/dev/pci/drm/amd/include/atomfirmware.h

3047

uint32_t gb_vdroop_table_ckson_a2;

sys/dev/pci/drm/amd/include/atomfirmware.h

3048

uint32_t avfsgb_fuse_table_cksoff_m1;

sys/dev/pci/drm/amd/include/atomfirmware.h

3049

uint32_t avfsgb_fuse_table_cksoff_m2;

sys/dev/pci/drm/amd/include/atomfirmware.h

3050

uint32_t avfsgb_fuse_table_cksoff_b;

sys/dev/pci/drm/amd/include/atomfirmware.h

3051

uint32_t avfsgb_fuse_table_ckson_m1;

sys/dev/pci/drm/amd/include/atomfirmware.h

3052

uint32_t avfsgb_fuse_table_ckson_m2;

sys/dev/pci/drm/amd/include/atomfirmware.h

3053

uint32_t avfsgb_fuse_table_ckson_b;

sys/dev/pci/drm/amd/include/atomfirmware.h

3062

uint32_t dispclk2gfxclk_a;

sys/dev/pci/drm/amd/include/atomfirmware.h

3063

uint32_t dispclk2gfxclk_b;

sys/dev/pci/drm/amd/include/atomfirmware.h

3064

uint32_t dispclk2gfxclk_c;

sys/dev/pci/drm/amd/include/atomfirmware.h

3065

uint32_t pixclk2gfxclk_a;

sys/dev/pci/drm/amd/include/atomfirmware.h

3066

uint32_t pixclk2gfxclk_b;

sys/dev/pci/drm/amd/include/atomfirmware.h

3067

uint32_t pixclk2gfxclk_c;

sys/dev/pci/drm/amd/include/atomfirmware.h

3068

uint32_t dcefclk2gfxclk_a;

sys/dev/pci/drm/amd/include/atomfirmware.h

3069

uint32_t dcefclk2gfxclk_b;

sys/dev/pci/drm/amd/include/atomfirmware.h

3070

uint32_t dcefclk2gfxclk_c;

sys/dev/pci/drm/amd/include/atomfirmware.h

3071

uint32_t phyclk2gfxclk_a;

sys/dev/pci/drm/amd/include/atomfirmware.h

3072

uint32_t phyclk2gfxclk_b;

sys/dev/pci/drm/amd/include/atomfirmware.h

3073

uint32_t phyclk2gfxclk_c;

sys/dev/pci/drm/amd/include/atomfirmware.h

3074

uint32_t acg_gb_vdroop_table_a0;

sys/dev/pci/drm/amd/include/atomfirmware.h

3075

uint32_t acg_gb_vdroop_table_a1;

sys/dev/pci/drm/amd/include/atomfirmware.h

3076

uint32_t acg_gb_vdroop_table_a2;

sys/dev/pci/drm/amd/include/atomfirmware.h

3077

uint32_t acg_avfsgb_fuse_table_m1;

sys/dev/pci/drm/amd/include/atomfirmware.h

3078

uint32_t acg_avfsgb_fuse_table_m2;

sys/dev/pci/drm/amd/include/atomfirmware.h

3079

uint32_t acg_avfsgb_fuse_table_b;

sys/dev/pci/drm/amd/include/atomfirmware.h

3082

uint32_t acg_dispclk2gfxclk_a;

sys/dev/pci/drm/amd/include/atomfirmware.h

3083

uint32_t acg_dispclk2gfxclk_b;

sys/dev/pci/drm/amd/include/atomfirmware.h

3084

uint32_t acg_dispclk2gfxclk_c;

sys/dev/pci/drm/amd/include/atomfirmware.h

3085

uint32_t acg_pixclk2gfxclk_a;

sys/dev/pci/drm/amd/include/atomfirmware.h

3086

uint32_t acg_pixclk2gfxclk_b;

sys/dev/pci/drm/amd/include/atomfirmware.h

3087

uint32_t acg_pixclk2gfxclk_c;

sys/dev/pci/drm/amd/include/atomfirmware.h

3088

uint32_t acg_dcefclk2gfxclk_a;

sys/dev/pci/drm/amd/include/atomfirmware.h

3089

uint32_t acg_dcefclk2gfxclk_b;

sys/dev/pci/drm/amd/include/atomfirmware.h

3090

uint32_t acg_dcefclk2gfxclk_c;

sys/dev/pci/drm/amd/include/atomfirmware.h

3091

uint32_t acg_phyclk2gfxclk_a;

sys/dev/pci/drm/amd/include/atomfirmware.h

3092

uint32_t acg_phyclk2gfxclk_b;

sys/dev/pci/drm/amd/include/atomfirmware.h

3093

uint32_t acg_phyclk2gfxclk_c;

sys/dev/pci/drm/amd/include/atomfirmware.h

3112

uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent

sys/dev/pci/drm/amd/include/atomfirmware.h

3113

uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent

sys/dev/pci/drm/amd/include/atomfirmware.h

3125

uint32_t ucode_version;

sys/dev/pci/drm/amd/include/atomfirmware.h

3126

uint32_t ucode_rom_startaddr;

sys/dev/pci/drm/amd/include/atomfirmware.h

3127

uint32_t ucode_length;

sys/dev/pci/drm/amd/include/atomfirmware.h

3136

uint32_t mem_refclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

3152

uint32_t ucode_version;

sys/dev/pci/drm/amd/include/atomfirmware.h

3153

uint32_t ucode_rom_startaddr;

sys/dev/pci/drm/amd/include/atomfirmware.h

3154

uint32_t ucode_length;

sys/dev/pci/drm/amd/include/atomfirmware.h

3163

uint32_t mem_refclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

3164

uint32_t pstate_uclk_10khz[4];

sys/dev/pci/drm/amd/include/atomfirmware.h

3172

uint32_t ucode_reserved;

sys/dev/pci/drm/amd/include/atomfirmware.h

3173

uint32_t ucode_rom_startaddr;

sys/dev/pci/drm/amd/include/atomfirmware.h

3174

uint32_t ucode_length;

sys/dev/pci/drm/amd/include/atomfirmware.h

3183

uint32_t mem_refclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

3184

uint32_t pstate_uclk_10khz[4];

sys/dev/pci/drm/amd/include/atomfirmware.h

3187

uint32_t umc_config1;

sys/dev/pci/drm/amd/include/atomfirmware.h

3188

uint32_t bist_data_startaddr;

sys/dev/pci/drm/amd/include/atomfirmware.h

3189

uint32_t reserved[2];

sys/dev/pci/drm/amd/include/atomfirmware.h

3203

uint32_t ucode_reserved[5];

sys/dev/pci/drm/amd/include/atomfirmware.h

3208

uint32_t mem_refclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

3209

uint32_t clk_reserved[4];

sys/dev/pci/drm/amd/include/atomfirmware.h

3210

uint32_t golden_reserved;

sys/dev/pci/drm/amd/include/atomfirmware.h

3211

uint32_t umc_config1;

sys/dev/pci/drm/amd/include/atomfirmware.h

3212

uint32_t reserved[2];

sys/dev/pci/drm/amd/include/atomfirmware.h

3226

uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros

sys/dev/pci/drm/amd/include/atomfirmware.h

3227

uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not

sys/dev/pci/drm/amd/include/atomfirmware.h

3228

uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined

sys/dev/pci/drm/amd/include/atomfirmware.h

3276

uint32_t dram_size_per_ch;

sys/dev/pci/drm/amd/include/atomfirmware.h

3277

uint32_t reserved[3];

sys/dev/pci/drm/amd/include/atomfirmware.h

3298

uint32_t channel_enable;

sys/dev/pci/drm/amd/include/atomfirmware.h

3299

uint32_t channel1_enable;

sys/dev/pci/drm/amd/include/atomfirmware.h

3300

uint32_t feature_enable;

sys/dev/pci/drm/amd/include/atomfirmware.h

3301

uint32_t feature1_enable;

sys/dev/pci/drm/amd/include/atomfirmware.h

3302

uint32_t hardcode_mem_size;

sys/dev/pci/drm/amd/include/atomfirmware.h

3303

uint32_t reserved4[4];

sys/dev/pci/drm/amd/include/atomfirmware.h

3308

uint32_t umc_register_addr:24;

sys/dev/pci/drm/amd/include/atomfirmware.h

3309

uint32_t umc_reg_type_ind:1;

sys/dev/pci/drm/amd/include/atomfirmware.h

3310

uint32_t umc_reg_rsvd:7;

sys/dev/pci/drm/amd/include/atomfirmware.h

3321

uint32_t u32umc_reg_addr;

sys/dev/pci/drm/amd/include/atomfirmware.h

3325

uint32_t memclockrange:24;

sys/dev/pci/drm/amd/include/atomfirmware.h

3326

uint32_t mem_blk_id:8;

sys/dev/pci/drm/amd/include/atomfirmware.h

3332

uint32_t u32umc_id_access;

sys/dev/pci/drm/amd/include/atomfirmware.h

3337

uint32_t u32umc_reg_data[1];

sys/dev/pci/drm/amd/include/atomfirmware.h

3349

uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros

sys/dev/pci/drm/amd/include/atomfirmware.h

3350

uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not

sys/dev/pci/drm/amd/include/atomfirmware.h

3351

uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined

sys/dev/pci/drm/amd/include/atomfirmware.h

3391

uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros

sys/dev/pci/drm/amd/include/atomfirmware.h

3392

uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not

sys/dev/pci/drm/amd/include/atomfirmware.h

3417

uint32_t u32umc_id_access;

sys/dev/pci/drm/amd/include/atomfirmware.h

3457

uint32_t tXSH;

sys/dev/pci/drm/amd/include/atomfirmware.h

3481

uint32_t dphy_byteremap; //mmUMC_DPHY_ByteRemap

sys/dev/pci/drm/amd/include/atomfirmware.h

3482

uint32_t dphy_bitremap0; //mmUMC_DPHY_BitRemap0

sys/dev/pci/drm/amd/include/atomfirmware.h

3483

uint32_t dphy_bitremap1; //mmUMC_DPHY_BitRemap1

sys/dev/pci/drm/amd/include/atomfirmware.h

3484

uint32_t dphy_bitremap2; //mmUMC_DPHY_BitRemap2

sys/dev/pci/drm/amd/include/atomfirmware.h

3485

uint32_t aphy_bitremap0; //mmUMC_APHY_BitRemap0

sys/dev/pci/drm/amd/include/atomfirmware.h

3486

uint32_t aphy_bitremap1; //mmUMC_APHY_BitRemap1

sys/dev/pci/drm/amd/include/atomfirmware.h

3487

uint32_t phy_dram; //mmUMC_PHY_DRAM

sys/dev/pci/drm/amd/include/atomfirmware.h

3491

uint32_t table_size;

sys/dev/pci/drm/amd/include/atomfirmware.h

3580

uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register

sys/dev/pci/drm/amd/include/atomfirmware.h

3591

uint32_t gpio_mask_val; // GPIO Mask value

sys/dev/pci/drm/amd/include/atomfirmware.h

3642

uint32_t sclkfreqin10khz:24;

sys/dev/pci/drm/amd/include/atomfirmware.h

3643

uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */

sys/dev/pci/drm/amd/include/atomfirmware.h

3648

uint32_t mclkfreqin10khz:24;

sys/dev/pci/drm/amd/include/atomfirmware.h

3649

uint32_t memflag:8; /* enum atom_asic_init_mem_flag */

sys/dev/pci/drm/amd/include/atomfirmware.h

3661

uint32_t reserved[16];

sys/dev/pci/drm/amd/include/atomfirmware.h

3686

uint32_t sclkfreqin10khz:24;

sys/dev/pci/drm/amd/include/atomfirmware.h

3687

uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */

sys/dev/pci/drm/amd/include/atomfirmware.h

3688

uint32_t reserved[10];

sys/dev/pci/drm/amd/include/atomfirmware.h

3694

uint32_t reserved[10];

sys/dev/pci/drm/amd/include/atomfirmware.h

3712

uint32_t sclk_10khz; // current engine speed in 10KHz unit

sys/dev/pci/drm/amd/include/atomfirmware.h

3713

uint32_t reserved;

sys/dev/pci/drm/amd/include/atomfirmware.h

3723

uint32_t mclkfreqin10khz:24;

sys/dev/pci/drm/amd/include/atomfirmware.h

3724

uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */

sys/dev/pci/drm/amd/include/atomfirmware.h

3725

uint32_t reserved[10];

sys/dev/pci/drm/amd/include/atomfirmware.h

3731

uint32_t reserved[10];

sys/dev/pci/drm/amd/include/atomfirmware.h

3742

uint32_t mclk_10khz; // current engine speed in 10KHz unit

sys/dev/pci/drm/amd/include/atomfirmware.h

3743

uint32_t reserved;

sys/dev/pci/drm/amd/include/atomfirmware.h

3772

uint32_t reserved[10];

sys/dev/pci/drm/amd/include/atomfirmware.h

3792

uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock

sys/dev/pci/drm/amd/include/atomfirmware.h

3793

uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type

sys/dev/pci/drm/amd/include/atomfirmware.h

3794

uint32_t reserved[5];

sys/dev/pci/drm/amd/include/atomfirmware.h

3800

uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock

sys/dev/pci/drm/amd/include/atomfirmware.h

3801

uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly

sys/dev/pci/drm/amd/include/atomfirmware.h

3802

uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac

sys/dev/pci/drm/amd/include/atomfirmware.h

3803

uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac

sys/dev/pci/drm/amd/include/atomfirmware.h

3807

uint32_t reserved1[2];

sys/dev/pci/drm/amd/include/atomfirmware.h

3829

uint32_t efusevalue;

sys/dev/pci/drm/amd/include/atomfirmware.h

3959

uint32_t smu_clock_freq_hz;

sys/dev/pci/drm/amd/include/atomfirmware.h

3960

uint32_t syspllvcofreq_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

3961

uint32_t sysspllrefclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

3983

uint32_t mclk_10khz:24; //Input= target mclk

sys/dev/pci/drm/amd/include/atomfirmware.h

3984

uint32_t command:8; //command enum of atom_dynamic_memory_setting_command

sys/dev/pci/drm/amd/include/atomfirmware.h

3985

uint32_t reserved;

sys/dev/pci/drm/amd/include/atomfirmware.h

3991

uint32_t sclk_10khz:24; //Input= target mclk

sys/dev/pci/drm/amd/include/atomfirmware.h

3992

uint32_t command:8; //command enum of atom_dynamic_memory_setting_command

sys/dev/pci/drm/amd/include/atomfirmware.h

3993

uint32_t mclk_10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

3994

uint32_t reserved;

sys/dev/pci/drm/amd/include/atomfirmware.h

4023

uint32_t reserved[5];

sys/dev/pci/drm/amd/include/atomfirmware.h

4035

uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz.

sys/dev/pci/drm/amd/include/atomfirmware.h

4045

uint32_t reserved2;

sys/dev/pci/drm/amd/include/atomfirmware.h

4082

uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.

sys/dev/pci/drm/amd/include/atomfirmware.h

4121

uint32_t ulReserved[2];

sys/dev/pci/drm/amd/include/atomfirmware.h

4133

uint32_t reserved1;

sys/dev/pci/drm/amd/include/atomfirmware.h

4166

uint32_t ulReserved[4];

sys/dev/pci/drm/amd/include/atomfirmware.h

4306

uint32_t pclk_10khz; // Pixel Clock in 10Khz

sys/dev/pci/drm/amd/include/atomfirmware.h

4330

uint32_t reserved2[2];

sys/dev/pci/drm/amd/include/atomfirmware.h

4338

uint32_t reserved2[2];

sys/dev/pci/drm/amd/include/atomfirmware.h

4363

uint32_t symclk_10khz; // Symbol Clock in 10Khz

sys/dev/pci/drm/amd/include/atomfirmware.h

4368

uint32_t reserved1;

sys/dev/pci/drm/amd/include/atomfirmware.h

4374

uint32_t reserved[4];

sys/dev/pci/drm/amd/include/atomfirmware.h

44

#ifndef uint32_t

sys/dev/pci/drm/amd/include/atomfirmware.h

4484

uint32_t reserved[2];

sys/dev/pci/drm/amd/include/atomfirmware.h

4496

uint32_t signature;

sys/dev/pci/drm/amd/include/atomfirmware.h

4497

uint32_t tableLength; //Length

sys/dev/pci/drm/amd/include/atomfirmware.h

4502

uint32_t oemRevision;

sys/dev/pci/drm/amd/include/atomfirmware.h

4503

uint32_t creatorId;

sys/dev/pci/drm/amd/include/atomfirmware.h

4504

uint32_t creatorRevision;

sys/dev/pci/drm/amd/include/atomfirmware.h

4510

uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the structure.

sys/dev/pci/drm/amd/include/atomfirmware.h

4511

uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the structure.

sys/dev/pci/drm/amd/include/atomfirmware.h

4512

uint32_t reserved[4]; //0x3C

sys/dev/pci/drm/amd/include/atomfirmware.h

4516

uint32_t pcibus; //0x4C

sys/dev/pci/drm/amd/include/atomfirmware.h

4517

uint32_t pcidevice; //0x50

sys/dev/pci/drm/amd/include/atomfirmware.h

4518

uint32_t pcifunction; //0x54

sys/dev/pci/drm/amd/include/atomfirmware.h

4523

uint32_t revision; //0x60

sys/dev/pci/drm/amd/include/atomfirmware.h

4524

uint32_t imagelength; //0x64

sys/dev/pci/drm/amd/include/atomfirmware.h

482

uint32_t firmware_revision;

sys/dev/pci/drm/amd/include/atomfirmware.h

483

uint32_t bootup_sclk_in10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

484

uint32_t bootup_mclk_in10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

485

uint32_t firmware_capability; // enum atombios_firmware_capability

sys/dev/pci/drm/amd/include/atomfirmware.h

486

uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */

sys/dev/pci/drm/amd/include/atomfirmware.h

487

uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address

sys/dev/pci/drm/amd/include/atomfirmware.h

495

uint32_t mc_baseaddr_high;

sys/dev/pci/drm/amd/include/atomfirmware.h

496

uint32_t mc_baseaddr_low;

sys/dev/pci/drm/amd/include/atomfirmware.h

497

uint32_t reserved2[6];

sys/dev/pci/drm/amd/include/atomfirmware.h

521

uint32_t firmware_revision;

sys/dev/pci/drm/amd/include/atomfirmware.h

522

uint32_t bootup_sclk_in10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

523

uint32_t bootup_mclk_in10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

524

uint32_t firmware_capability; // enum atombios_firmware_capability

sys/dev/pci/drm/amd/include/atomfirmware.h

525

uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */

sys/dev/pci/drm/amd/include/atomfirmware.h

526

uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address

sys/dev/pci/drm/amd/include/atomfirmware.h

534

uint32_t mc_baseaddr_high;

sys/dev/pci/drm/amd/include/atomfirmware.h

535

uint32_t mc_baseaddr_low;

sys/dev/pci/drm/amd/include/atomfirmware.h

542

uint32_t zfbstartaddrin16mb;

sys/dev/pci/drm/amd/include/atomfirmware.h

543

uint32_t reserved2[3];

sys/dev/pci/drm/amd/include/atomfirmware.h

549

uint32_t firmware_revision;

sys/dev/pci/drm/amd/include/atomfirmware.h

550

uint32_t bootup_sclk_in10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

551

uint32_t bootup_mclk_in10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

552

uint32_t firmware_capability; // enum atombios_firmware_capability

sys/dev/pci/drm/amd/include/atomfirmware.h

553

uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */

sys/dev/pci/drm/amd/include/atomfirmware.h

554

uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address

sys/dev/pci/drm/amd/include/atomfirmware.h

562

uint32_t mc_baseaddr_high;

sys/dev/pci/drm/amd/include/atomfirmware.h

563

uint32_t mc_baseaddr_low;

sys/dev/pci/drm/amd/include/atomfirmware.h

570

uint32_t zfbstartaddrin16mb;

sys/dev/pci/drm/amd/include/atomfirmware.h

571

uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS

sys/dev/pci/drm/amd/include/atomfirmware.h

572

uint32_t reserved2[2];

sys/dev/pci/drm/amd/include/atomfirmware.h

577

uint32_t firmware_revision;

sys/dev/pci/drm/amd/include/atomfirmware.h

578

uint32_t bootup_sclk_in10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

579

uint32_t bootup_mclk_in10khz;

sys/dev/pci/drm/amd/include/atomfirmware.h

580

uint32_t firmware_capability; // enum atombios_firmware_capability

sys/dev/pci/drm/amd/include/atomfirmware.h

581

uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */

sys/dev/pci/drm/amd/include/atomfirmware.h

582

uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address

sys/dev/pci/drm/amd/include/atomfirmware.h

590

uint32_t mc_baseaddr_high;

sys/dev/pci/drm/amd/include/atomfirmware.h

591

uint32_t mc_baseaddr_low;

sys/dev/pci/drm/amd/include/atomfirmware.h

598

uint32_t zfbstartaddrin16mb;

sys/dev/pci/drm/amd/include/atomfirmware.h

599

uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS

sys/dev/pci/drm/amd/include/atomfirmware.h

600

uint32_t mvdd_ratio; // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2)

sys/dev/pci/drm/amd/include/atomfirmware.h

605

uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt

sys/dev/pci/drm/amd/include/atomfirmware.h

606

uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt

sys/dev/pci/drm/amd/include/atomfirmware.h

607

uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb.

sys/dev/pci/drm/amd/include/atomfirmware.h

608

uint32_t pspbl_init_done_reg_addr;

sys/dev/pci/drm/amd/include/atomfirmware.h

609

uint32_t pspbl_init_done_value;

sys/dev/pci/drm/amd/include/atomfirmware.h

610

uint32_t pspbl_init_done_check_timeout; // time out in unit of us when polling pspbl init done

sys/dev/pci/drm/amd/include/atomfirmware.h

611

uint32_t reserved[2];

sys/dev/pci/drm/amd/include/atomfirmware.h

616

uint32_t firmware_revision;

sys/dev/pci/drm/amd/include/atomfirmware.h

617

uint32_t bootup_clk_reserved[2];

sys/dev/pci/drm/amd/include/atomfirmware.h

618

uint32_t firmware_capability; // enum atombios_firmware_capability

sys/dev/pci/drm/amd/include/atomfirmware.h

619

uint32_t fw_protect_region_size_in_kb; /* FW allocate a write protect region at top of FB. */

sys/dev/pci/drm/amd/include/atomfirmware.h

620

uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address

sys/dev/pci/drm/amd/include/atomfirmware.h

621

uint32_t bootup_voltage_reserved[2];

sys/dev/pci/drm/amd/include/atomfirmware.h

626

uint32_t mc_baseaddr_high;

sys/dev/pci/drm/amd/include/atomfirmware.h

627

uint32_t mc_baseaddr_low;

sys/dev/pci/drm/amd/include/atomfirmware.h

632

uint32_t bootup_voltage_reserved1;

sys/dev/pci/drm/amd/include/atomfirmware.h

633

uint32_t zfb_reserved;

sys/dev/pci/drm/amd/include/atomfirmware.h

635

uint32_t pplib_pptable_id;

sys/dev/pci/drm/amd/include/atomfirmware.h

636

uint32_t hw_voltage_reserved[3];

sys/dev/pci/drm/amd/include/atomfirmware.h

637

uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt

sys/dev/pci/drm/amd/include/atomfirmware.h

638

uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt

sys/dev/pci/drm/amd/include/atomfirmware.h

639

uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb.

sys/dev/pci/drm/amd/include/atomfirmware.h

640

uint32_t pspbl_init_reserved[3];

sys/dev/pci/drm/amd/include/atomfirmware.h

641

uint32_t spi_rom_size; // GPU spi rom size

sys/dev/pci/drm/amd/include/atomfirmware.h

644

uint32_t reserved[16];

sys/dev/pci/drm/amd/include/atomfirmware.h

678

uint32_t reserved1[8];

sys/dev/pci/drm/amd/include/atomfirmware.h

703

uint32_t data_a_reg_index;

sys/dev/pci/drm/amd/include/atomfirmware.h

787

uint32_t start_address_in_kb;

sys/dev/pci/drm/amd/include/atomfirmware.h

794

uint32_t fw_region_start_address_in_kb;

sys/dev/pci/drm/amd/include/atomfirmware.h

797

uint32_t driver_region0_start_address_in_kb;

sys/dev/pci/drm/amd/include/atomfirmware.h

798

uint32_t used_by_driver_region0_in_kb;

sys/dev/pci/drm/amd/include/atomfirmware.h

799

uint32_t reserved32[7];

sys/dev/pci/drm/amd/include/atomfirmware.h

853

uint32_t connector_max_speed; // connector Max speed attribute, it sets 8100 in Mhz when DP connector @8.1Ghz.

sys/dev/pci/drm/amd/include/atomfirmware.h

875

uint32_t encodercaps;

sys/dev/pci/drm/amd/include/atomfirmware.h

887

uint32_t connectcaps;

sys/dev/pci/drm/amd/include/cgs_common.h

108

typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,

sys/dev/pci/drm/amd/include/cgs_common.h

118

unsigned index, uint32_t value);

sys/dev/pci/drm/amd/include/cgs_common.h

71

uint32_t image_size;

sys/dev/pci/drm/amd/include/cgs_common.h

75

uint32_t ucode_start_address;

sys/dev/pci/drm/amd/include/cgs_common.h

90

typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);

sys/dev/pci/drm/amd/include/cgs_common.h

99

uint32_t value);

sys/dev/pci/drm/amd/include/cik_structs.h

100

uint32_t cp_hqd_ib_control;

sys/dev/pci/drm/amd/include/cik_structs.h

101

uint32_t cp_hqd_iq_timer;

sys/dev/pci/drm/amd/include/cik_structs.h

102

uint32_t cp_hqd_iq_rptr;

sys/dev/pci/drm/amd/include/cik_structs.h

103

uint32_t cp_hqd_dequeue_request;

sys/dev/pci/drm/amd/include/cik_structs.h

104

uint32_t cp_hqd_dma_offload;

sys/dev/pci/drm/amd/include/cik_structs.h

105

uint32_t cp_hqd_sema_cmd;

sys/dev/pci/drm/amd/include/cik_structs.h

106

uint32_t cp_hqd_msg_type;

sys/dev/pci/drm/amd/include/cik_structs.h

107

uint32_t cp_hqd_atomic0_preop_lo;

sys/dev/pci/drm/amd/include/cik_structs.h

108

uint32_t cp_hqd_atomic0_preop_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

109

uint32_t cp_hqd_atomic1_preop_lo;

sys/dev/pci/drm/amd/include/cik_structs.h

110

uint32_t cp_hqd_atomic1_preop_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

111

uint32_t cp_hqd_hq_status0;

sys/dev/pci/drm/amd/include/cik_structs.h

112

uint32_t cp_hqd_hq_control0;

sys/dev/pci/drm/amd/include/cik_structs.h

113

uint32_t cp_mqd_control;

sys/dev/pci/drm/amd/include/cik_structs.h

114

uint32_t cp_mqd_query_time_lo;

sys/dev/pci/drm/amd/include/cik_structs.h

115

uint32_t cp_mqd_query_time_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

116

uint32_t cp_mqd_connect_start_time_lo;

sys/dev/pci/drm/amd/include/cik_structs.h

117

uint32_t cp_mqd_connect_start_time_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

118

uint32_t cp_mqd_connect_end_time_lo;

sys/dev/pci/drm/amd/include/cik_structs.h

119

uint32_t cp_mqd_connect_end_time_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

120

uint32_t cp_mqd_connect_end_wf_count;

sys/dev/pci/drm/amd/include/cik_structs.h

121

uint32_t cp_mqd_connect_end_pq_rptr;

sys/dev/pci/drm/amd/include/cik_structs.h

122

uint32_t cp_mqd_connect_end_pq_wptr;

sys/dev/pci/drm/amd/include/cik_structs.h

123

uint32_t cp_mqd_connect_end_ib_rptr;

sys/dev/pci/drm/amd/include/cik_structs.h

124

uint32_t reserved_96;

sys/dev/pci/drm/amd/include/cik_structs.h

125

uint32_t reserved_97;

sys/dev/pci/drm/amd/include/cik_structs.h

126

uint32_t reserved_98;

sys/dev/pci/drm/amd/include/cik_structs.h

127

uint32_t reserved_99;

sys/dev/pci/drm/amd/include/cik_structs.h

128

uint32_t iqtimer_pkt_header;

sys/dev/pci/drm/amd/include/cik_structs.h

129

uint32_t iqtimer_pkt_dw0;

sys/dev/pci/drm/amd/include/cik_structs.h

130

uint32_t iqtimer_pkt_dw1;

sys/dev/pci/drm/amd/include/cik_structs.h

131

uint32_t iqtimer_pkt_dw2;

sys/dev/pci/drm/amd/include/cik_structs.h

132

uint32_t iqtimer_pkt_dw3;

sys/dev/pci/drm/amd/include/cik_structs.h

133

uint32_t iqtimer_pkt_dw4;

sys/dev/pci/drm/amd/include/cik_structs.h

134

uint32_t iqtimer_pkt_dw5;

sys/dev/pci/drm/amd/include/cik_structs.h

135

uint32_t iqtimer_pkt_dw6;

sys/dev/pci/drm/amd/include/cik_structs.h

136

uint32_t reserved_108;

sys/dev/pci/drm/amd/include/cik_structs.h

137

uint32_t reserved_109;

sys/dev/pci/drm/amd/include/cik_structs.h

138

uint32_t reserved_110;

sys/dev/pci/drm/amd/include/cik_structs.h

139

uint32_t reserved_111;

sys/dev/pci/drm/amd/include/cik_structs.h

140

uint32_t queue_doorbell_id0;

sys/dev/pci/drm/amd/include/cik_structs.h

141

uint32_t queue_doorbell_id1;

sys/dev/pci/drm/amd/include/cik_structs.h

142

uint32_t queue_doorbell_id2;

sys/dev/pci/drm/amd/include/cik_structs.h

143

uint32_t queue_doorbell_id3;

sys/dev/pci/drm/amd/include/cik_structs.h

144

uint32_t queue_doorbell_id4;

sys/dev/pci/drm/amd/include/cik_structs.h

145

uint32_t queue_doorbell_id5;

sys/dev/pci/drm/amd/include/cik_structs.h

146

uint32_t queue_doorbell_id6;

sys/dev/pci/drm/amd/include/cik_structs.h

147

uint32_t queue_doorbell_id7;

sys/dev/pci/drm/amd/include/cik_structs.h

148

uint32_t queue_doorbell_id8;

sys/dev/pci/drm/amd/include/cik_structs.h

149

uint32_t queue_doorbell_id9;

sys/dev/pci/drm/amd/include/cik_structs.h

150

uint32_t queue_doorbell_id10;

sys/dev/pci/drm/amd/include/cik_structs.h

151

uint32_t queue_doorbell_id11;

sys/dev/pci/drm/amd/include/cik_structs.h

152

uint32_t queue_doorbell_id12;

sys/dev/pci/drm/amd/include/cik_structs.h

153

uint32_t queue_doorbell_id13;

sys/dev/pci/drm/amd/include/cik_structs.h

154

uint32_t queue_doorbell_id14;

sys/dev/pci/drm/amd/include/cik_structs.h

155

uint32_t queue_doorbell_id15;

sys/dev/pci/drm/amd/include/cik_structs.h

159

uint32_t sdma_rlc_rb_cntl;

sys/dev/pci/drm/amd/include/cik_structs.h

160

uint32_t sdma_rlc_rb_base;

sys/dev/pci/drm/amd/include/cik_structs.h

161

uint32_t sdma_rlc_rb_base_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

162

uint32_t sdma_rlc_rb_rptr;

sys/dev/pci/drm/amd/include/cik_structs.h

163

uint32_t sdma_rlc_rb_wptr;

sys/dev/pci/drm/amd/include/cik_structs.h

164

uint32_t sdma_rlc_rb_wptr_poll_cntl;

sys/dev/pci/drm/amd/include/cik_structs.h

165

uint32_t sdma_rlc_rb_wptr_poll_addr_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

166

uint32_t sdma_rlc_rb_wptr_poll_addr_lo;

sys/dev/pci/drm/amd/include/cik_structs.h

167

uint32_t sdma_rlc_rb_rptr_addr_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

168

uint32_t sdma_rlc_rb_rptr_addr_lo;

sys/dev/pci/drm/amd/include/cik_structs.h

169

uint32_t sdma_rlc_ib_cntl;

sys/dev/pci/drm/amd/include/cik_structs.h

170

uint32_t sdma_rlc_ib_rptr;

sys/dev/pci/drm/amd/include/cik_structs.h

171

uint32_t sdma_rlc_ib_offset;

sys/dev/pci/drm/amd/include/cik_structs.h

172

uint32_t sdma_rlc_ib_base_lo;

sys/dev/pci/drm/amd/include/cik_structs.h

173

uint32_t sdma_rlc_ib_base_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

174

uint32_t sdma_rlc_ib_size;

sys/dev/pci/drm/amd/include/cik_structs.h

175

uint32_t sdma_rlc_skip_cntl;

sys/dev/pci/drm/amd/include/cik_structs.h

176

uint32_t sdma_rlc_context_status;

sys/dev/pci/drm/amd/include/cik_structs.h

177

uint32_t sdma_rlc_doorbell;

sys/dev/pci/drm/amd/include/cik_structs.h

178

uint32_t sdma_rlc_virtual_addr;

sys/dev/pci/drm/amd/include/cik_structs.h

179

uint32_t sdma_rlc_ape1_cntl;

sys/dev/pci/drm/amd/include/cik_structs.h

180

uint32_t sdma_rlc_doorbell_log;

sys/dev/pci/drm/amd/include/cik_structs.h

181

uint32_t reserved_22;

sys/dev/pci/drm/amd/include/cik_structs.h

182

uint32_t reserved_23;

sys/dev/pci/drm/amd/include/cik_structs.h

183

uint32_t reserved_24;

sys/dev/pci/drm/amd/include/cik_structs.h

184

uint32_t reserved_25;

sys/dev/pci/drm/amd/include/cik_structs.h

185

uint32_t reserved_26;

sys/dev/pci/drm/amd/include/cik_structs.h

186

uint32_t reserved_27;

sys/dev/pci/drm/amd/include/cik_structs.h

187

uint32_t reserved_28;

sys/dev/pci/drm/amd/include/cik_structs.h

188

uint32_t reserved_29;

sys/dev/pci/drm/amd/include/cik_structs.h

189

uint32_t reserved_30;

sys/dev/pci/drm/amd/include/cik_structs.h

190

uint32_t reserved_31;

sys/dev/pci/drm/amd/include/cik_structs.h

191

uint32_t reserved_32;

sys/dev/pci/drm/amd/include/cik_structs.h

192

uint32_t reserved_33;

sys/dev/pci/drm/amd/include/cik_structs.h

193

uint32_t reserved_34;

sys/dev/pci/drm/amd/include/cik_structs.h

194

uint32_t reserved_35;

sys/dev/pci/drm/amd/include/cik_structs.h

195

uint32_t reserved_36;

sys/dev/pci/drm/amd/include/cik_structs.h

196

uint32_t reserved_37;

sys/dev/pci/drm/amd/include/cik_structs.h

197

uint32_t reserved_38;

sys/dev/pci/drm/amd/include/cik_structs.h

198

uint32_t reserved_39;

sys/dev/pci/drm/amd/include/cik_structs.h

199

uint32_t reserved_40;

sys/dev/pci/drm/amd/include/cik_structs.h

200

uint32_t reserved_41;

sys/dev/pci/drm/amd/include/cik_structs.h

201

uint32_t reserved_42;

sys/dev/pci/drm/amd/include/cik_structs.h

202

uint32_t reserved_43;

sys/dev/pci/drm/amd/include/cik_structs.h

203

uint32_t reserved_44;

sys/dev/pci/drm/amd/include/cik_structs.h

204

uint32_t reserved_45;

sys/dev/pci/drm/amd/include/cik_structs.h

205

uint32_t reserved_46;

sys/dev/pci/drm/amd/include/cik_structs.h

206

uint32_t reserved_47;

sys/dev/pci/drm/amd/include/cik_structs.h

207

uint32_t reserved_48;

sys/dev/pci/drm/amd/include/cik_structs.h

208

uint32_t reserved_49;

sys/dev/pci/drm/amd/include/cik_structs.h

209

uint32_t reserved_50;

sys/dev/pci/drm/amd/include/cik_structs.h

210

uint32_t reserved_51;

sys/dev/pci/drm/amd/include/cik_structs.h

211

uint32_t reserved_52;

sys/dev/pci/drm/amd/include/cik_structs.h

212

uint32_t reserved_53;

sys/dev/pci/drm/amd/include/cik_structs.h

213

uint32_t reserved_54;

sys/dev/pci/drm/amd/include/cik_structs.h

214

uint32_t reserved_55;

sys/dev/pci/drm/amd/include/cik_structs.h

215

uint32_t reserved_56;

sys/dev/pci/drm/amd/include/cik_structs.h

216

uint32_t reserved_57;

sys/dev/pci/drm/amd/include/cik_structs.h

217

uint32_t reserved_58;

sys/dev/pci/drm/amd/include/cik_structs.h

218

uint32_t reserved_59;

sys/dev/pci/drm/amd/include/cik_structs.h

219

uint32_t reserved_60;

sys/dev/pci/drm/amd/include/cik_structs.h

220

uint32_t reserved_61;

sys/dev/pci/drm/amd/include/cik_structs.h

221

uint32_t reserved_62;

sys/dev/pci/drm/amd/include/cik_structs.h

222

uint32_t reserved_63;

sys/dev/pci/drm/amd/include/cik_structs.h

223

uint32_t reserved_64;

sys/dev/pci/drm/amd/include/cik_structs.h

224

uint32_t reserved_65;

sys/dev/pci/drm/amd/include/cik_structs.h

225

uint32_t reserved_66;

sys/dev/pci/drm/amd/include/cik_structs.h

226

uint32_t reserved_67;

sys/dev/pci/drm/amd/include/cik_structs.h

227

uint32_t reserved_68;

sys/dev/pci/drm/amd/include/cik_structs.h

228

uint32_t reserved_69;

sys/dev/pci/drm/amd/include/cik_structs.h

229

uint32_t reserved_70;

sys/dev/pci/drm/amd/include/cik_structs.h

230

uint32_t reserved_71;

sys/dev/pci/drm/amd/include/cik_structs.h

231

uint32_t reserved_72;

sys/dev/pci/drm/amd/include/cik_structs.h

232

uint32_t reserved_73;

sys/dev/pci/drm/amd/include/cik_structs.h

233

uint32_t reserved_74;

sys/dev/pci/drm/amd/include/cik_structs.h

234

uint32_t reserved_75;

sys/dev/pci/drm/amd/include/cik_structs.h

235

uint32_t reserved_76;

sys/dev/pci/drm/amd/include/cik_structs.h

236

uint32_t reserved_77;

sys/dev/pci/drm/amd/include/cik_structs.h

237

uint32_t reserved_78;

sys/dev/pci/drm/amd/include/cik_structs.h

238

uint32_t reserved_79;

sys/dev/pci/drm/amd/include/cik_structs.h

239

uint32_t reserved_80;

sys/dev/pci/drm/amd/include/cik_structs.h

240

uint32_t reserved_81;

sys/dev/pci/drm/amd/include/cik_structs.h

241

uint32_t reserved_82;

sys/dev/pci/drm/amd/include/cik_structs.h

242

uint32_t reserved_83;

sys/dev/pci/drm/amd/include/cik_structs.h

243

uint32_t reserved_84;

sys/dev/pci/drm/amd/include/cik_structs.h

244

uint32_t reserved_85;

sys/dev/pci/drm/amd/include/cik_structs.h

245

uint32_t reserved_86;

sys/dev/pci/drm/amd/include/cik_structs.h

246

uint32_t reserved_87;

sys/dev/pci/drm/amd/include/cik_structs.h

247

uint32_t reserved_88;

sys/dev/pci/drm/amd/include/cik_structs.h

248

uint32_t reserved_89;

sys/dev/pci/drm/amd/include/cik_structs.h

249

uint32_t reserved_90;

sys/dev/pci/drm/amd/include/cik_structs.h

250

uint32_t reserved_91;

sys/dev/pci/drm/amd/include/cik_structs.h

251

uint32_t reserved_92;

sys/dev/pci/drm/amd/include/cik_structs.h

252

uint32_t reserved_93;

sys/dev/pci/drm/amd/include/cik_structs.h

253

uint32_t reserved_94;

sys/dev/pci/drm/amd/include/cik_structs.h

254

uint32_t reserved_95;

sys/dev/pci/drm/amd/include/cik_structs.h

255

uint32_t reserved_96;

sys/dev/pci/drm/amd/include/cik_structs.h

256

uint32_t reserved_97;

sys/dev/pci/drm/amd/include/cik_structs.h

257

uint32_t reserved_98;

sys/dev/pci/drm/amd/include/cik_structs.h

258

uint32_t reserved_99;

sys/dev/pci/drm/amd/include/cik_structs.h

259

uint32_t reserved_100;

sys/dev/pci/drm/amd/include/cik_structs.h

260

uint32_t reserved_101;

sys/dev/pci/drm/amd/include/cik_structs.h

261

uint32_t reserved_102;

sys/dev/pci/drm/amd/include/cik_structs.h

262

uint32_t reserved_103;

sys/dev/pci/drm/amd/include/cik_structs.h

263

uint32_t reserved_104;

sys/dev/pci/drm/amd/include/cik_structs.h

264

uint32_t reserved_105;

sys/dev/pci/drm/amd/include/cik_structs.h

265

uint32_t reserved_106;

sys/dev/pci/drm/amd/include/cik_structs.h

266

uint32_t reserved_107;

sys/dev/pci/drm/amd/include/cik_structs.h

267

uint32_t reserved_108;

sys/dev/pci/drm/amd/include/cik_structs.h

268

uint32_t reserved_109;

sys/dev/pci/drm/amd/include/cik_structs.h

269

uint32_t reserved_110;

sys/dev/pci/drm/amd/include/cik_structs.h

270

uint32_t reserved_111;

sys/dev/pci/drm/amd/include/cik_structs.h

271

uint32_t reserved_112;

sys/dev/pci/drm/amd/include/cik_structs.h

272

uint32_t reserved_113;

sys/dev/pci/drm/amd/include/cik_structs.h

273

uint32_t reserved_114;

sys/dev/pci/drm/amd/include/cik_structs.h

274

uint32_t reserved_115;

sys/dev/pci/drm/amd/include/cik_structs.h

275

uint32_t reserved_116;

sys/dev/pci/drm/amd/include/cik_structs.h

276

uint32_t reserved_117;

sys/dev/pci/drm/amd/include/cik_structs.h

277

uint32_t reserved_118;

sys/dev/pci/drm/amd/include/cik_structs.h

278

uint32_t reserved_119;

sys/dev/pci/drm/amd/include/cik_structs.h

279

uint32_t reserved_120;

sys/dev/pci/drm/amd/include/cik_structs.h

28

uint32_t header;

sys/dev/pci/drm/amd/include/cik_structs.h

280

uint32_t reserved_121;

sys/dev/pci/drm/amd/include/cik_structs.h

281

uint32_t reserved_122;

sys/dev/pci/drm/amd/include/cik_structs.h

282

uint32_t reserved_123;

sys/dev/pci/drm/amd/include/cik_structs.h

283

uint32_t reserved_124;

sys/dev/pci/drm/amd/include/cik_structs.h

284

uint32_t reserved_125;

sys/dev/pci/drm/amd/include/cik_structs.h

286

uint32_t sdma_engine_id;

sys/dev/pci/drm/amd/include/cik_structs.h

287

uint32_t sdma_queue_id;

sys/dev/pci/drm/amd/include/cik_structs.h

29

uint32_t compute_dispatch_initiator;

sys/dev/pci/drm/amd/include/cik_structs.h

30

uint32_t compute_dim_x;

sys/dev/pci/drm/amd/include/cik_structs.h

31

uint32_t compute_dim_y;

sys/dev/pci/drm/amd/include/cik_structs.h

32

uint32_t compute_dim_z;

sys/dev/pci/drm/amd/include/cik_structs.h

33

uint32_t compute_start_x;

sys/dev/pci/drm/amd/include/cik_structs.h

34

uint32_t compute_start_y;

sys/dev/pci/drm/amd/include/cik_structs.h

35

uint32_t compute_start_z;

sys/dev/pci/drm/amd/include/cik_structs.h

36

uint32_t compute_num_thread_x;

sys/dev/pci/drm/amd/include/cik_structs.h

37

uint32_t compute_num_thread_y;

sys/dev/pci/drm/amd/include/cik_structs.h

38

uint32_t compute_num_thread_z;

sys/dev/pci/drm/amd/include/cik_structs.h

39

uint32_t compute_pipelinestat_enable;

sys/dev/pci/drm/amd/include/cik_structs.h

40

uint32_t compute_perfcount_enable;

sys/dev/pci/drm/amd/include/cik_structs.h

41

uint32_t compute_pgm_lo;

sys/dev/pci/drm/amd/include/cik_structs.h

42

uint32_t compute_pgm_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

43

uint32_t compute_tba_lo;

sys/dev/pci/drm/amd/include/cik_structs.h

44

uint32_t compute_tba_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

45

uint32_t compute_tma_lo;

sys/dev/pci/drm/amd/include/cik_structs.h

46

uint32_t compute_tma_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

47

uint32_t compute_pgm_rsrc1;

sys/dev/pci/drm/amd/include/cik_structs.h

48

uint32_t compute_pgm_rsrc2;

sys/dev/pci/drm/amd/include/cik_structs.h

49

uint32_t compute_vmid;

sys/dev/pci/drm/amd/include/cik_structs.h

50

uint32_t compute_resource_limits;

sys/dev/pci/drm/amd/include/cik_structs.h

51

uint32_t compute_static_thread_mgmt_se0;

sys/dev/pci/drm/amd/include/cik_structs.h

52

uint32_t compute_static_thread_mgmt_se1;

sys/dev/pci/drm/amd/include/cik_structs.h

53

uint32_t compute_tmpring_size;

sys/dev/pci/drm/amd/include/cik_structs.h

54

uint32_t compute_static_thread_mgmt_se2;

sys/dev/pci/drm/amd/include/cik_structs.h

55

uint32_t compute_static_thread_mgmt_se3;

sys/dev/pci/drm/amd/include/cik_structs.h

56

uint32_t compute_restart_x;

sys/dev/pci/drm/amd/include/cik_structs.h

57

uint32_t compute_restart_y;

sys/dev/pci/drm/amd/include/cik_structs.h

58

uint32_t compute_restart_z;

sys/dev/pci/drm/amd/include/cik_structs.h

59

uint32_t compute_thread_trace_enable;

sys/dev/pci/drm/amd/include/cik_structs.h

60

uint32_t compute_misc_reserved;

sys/dev/pci/drm/amd/include/cik_structs.h

61

uint32_t compute_user_data_0;

sys/dev/pci/drm/amd/include/cik_structs.h

62

uint32_t compute_user_data_1;

sys/dev/pci/drm/amd/include/cik_structs.h

63

uint32_t compute_user_data_2;

sys/dev/pci/drm/amd/include/cik_structs.h

64

uint32_t compute_user_data_3;

sys/dev/pci/drm/amd/include/cik_structs.h

65

uint32_t compute_user_data_4;

sys/dev/pci/drm/amd/include/cik_structs.h

66

uint32_t compute_user_data_5;

sys/dev/pci/drm/amd/include/cik_structs.h

67

uint32_t compute_user_data_6;

sys/dev/pci/drm/amd/include/cik_structs.h

68

uint32_t compute_user_data_7;

sys/dev/pci/drm/amd/include/cik_structs.h

69

uint32_t compute_user_data_8;

sys/dev/pci/drm/amd/include/cik_structs.h

70

uint32_t compute_user_data_9;

sys/dev/pci/drm/amd/include/cik_structs.h

71

uint32_t compute_user_data_10;

sys/dev/pci/drm/amd/include/cik_structs.h

72

uint32_t compute_user_data_11;

sys/dev/pci/drm/amd/include/cik_structs.h

73

uint32_t compute_user_data_12;

sys/dev/pci/drm/amd/include/cik_structs.h

74

uint32_t compute_user_data_13;

sys/dev/pci/drm/amd/include/cik_structs.h

75

uint32_t compute_user_data_14;

sys/dev/pci/drm/amd/include/cik_structs.h

76

uint32_t compute_user_data_15;

sys/dev/pci/drm/amd/include/cik_structs.h

77

uint32_t cp_compute_csinvoc_count_lo;

sys/dev/pci/drm/amd/include/cik_structs.h

78

uint32_t cp_compute_csinvoc_count_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

79

uint32_t cp_mqd_base_addr_lo;

sys/dev/pci/drm/amd/include/cik_structs.h

80

uint32_t cp_mqd_base_addr_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

81

uint32_t cp_hqd_active;

sys/dev/pci/drm/amd/include/cik_structs.h

82

uint32_t cp_hqd_vmid;

sys/dev/pci/drm/amd/include/cik_structs.h

83

uint32_t cp_hqd_persistent_state;

sys/dev/pci/drm/amd/include/cik_structs.h

84

uint32_t cp_hqd_pipe_priority;

sys/dev/pci/drm/amd/include/cik_structs.h

85

uint32_t cp_hqd_queue_priority;

sys/dev/pci/drm/amd/include/cik_structs.h

86

uint32_t cp_hqd_quantum;

sys/dev/pci/drm/amd/include/cik_structs.h

87

uint32_t cp_hqd_pq_base_lo;

sys/dev/pci/drm/amd/include/cik_structs.h

88

uint32_t cp_hqd_pq_base_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

89

uint32_t cp_hqd_pq_rptr;

sys/dev/pci/drm/amd/include/cik_structs.h

90

uint32_t cp_hqd_pq_rptr_report_addr_lo;

sys/dev/pci/drm/amd/include/cik_structs.h

91

uint32_t cp_hqd_pq_rptr_report_addr_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

92

uint32_t cp_hqd_pq_wptr_poll_addr_lo;

sys/dev/pci/drm/amd/include/cik_structs.h

93

uint32_t cp_hqd_pq_wptr_poll_addr_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

94

uint32_t cp_hqd_pq_doorbell_control;

sys/dev/pci/drm/amd/include/cik_structs.h

95

uint32_t cp_hqd_pq_wptr;

sys/dev/pci/drm/amd/include/cik_structs.h

96

uint32_t cp_hqd_pq_control;

sys/dev/pci/drm/amd/include/cik_structs.h

97

uint32_t cp_hqd_ib_base_addr_lo;

sys/dev/pci/drm/amd/include/cik_structs.h

98

uint32_t cp_hqd_ib_base_addr_hi;

sys/dev/pci/drm/amd/include/cik_structs.h

99

uint32_t cp_hqd_ib_rptr;

sys/dev/pci/drm/amd/include/discovery.h

107

uint32_t base_address[]; /* variable number of Addresses */

sys/dev/pci/drm/amd/include/discovery.h

125

uint32_t base_address[]; /* Base Address list. Corresponds to the num_base_address field*/

sys/dev/pci/drm/amd/include/discovery.h

143

DECLARE_FLEX_ARRAY(uint32_t, base_address); /* 32-bit Base Address list. Corresponds to the num_base_address field*/

sys/dev/pci/drm/amd/include/discovery.h

170

uint32_t table_id; /* table ID */

sys/dev/pci/drm/amd/include/discovery.h

173

uint32_t size; /* size of the entire header+data in bytes */

sys/dev/pci/drm/amd/include/discovery.h

179

uint32_t gc_num_se;

sys/dev/pci/drm/amd/include/discovery.h

180

uint32_t gc_num_wgp0_per_sa;

sys/dev/pci/drm/amd/include/discovery.h

181

uint32_t gc_num_wgp1_per_sa;

sys/dev/pci/drm/amd/include/discovery.h

182

uint32_t gc_num_rb_per_se;

sys/dev/pci/drm/amd/include/discovery.h

183

uint32_t gc_num_gl2c;

sys/dev/pci/drm/amd/include/discovery.h

184

uint32_t gc_num_gprs;

sys/dev/pci/drm/amd/include/discovery.h

185

uint32_t gc_num_max_gs_thds;

sys/dev/pci/drm/amd/include/discovery.h

186

uint32_t gc_gs_table_depth;

sys/dev/pci/drm/amd/include/discovery.h

187

uint32_t gc_gsprim_buff_depth;

sys/dev/pci/drm/amd/include/discovery.h

188

uint32_t gc_parameter_cache_depth;

sys/dev/pci/drm/amd/include/discovery.h

189

uint32_t gc_double_offchip_lds_buffer;

sys/dev/pci/drm/amd/include/discovery.h

190

uint32_t gc_wave_size;

sys/dev/pci/drm/amd/include/discovery.h

191

uint32_t gc_max_waves_per_simd;

sys/dev/pci/drm/amd/include/discovery.h

192

uint32_t gc_max_scratch_slots_per_cu;

sys/dev/pci/drm/amd/include/discovery.h

193

uint32_t gc_lds_size;

sys/dev/pci/drm/amd/include/discovery.h

194

uint32_t gc_num_sc_per_se;

sys/dev/pci/drm/amd/include/discovery.h

195

uint32_t gc_num_sa_per_se;

sys/dev/pci/drm/amd/include/discovery.h

196

uint32_t gc_num_packer_per_sc;

sys/dev/pci/drm/amd/include/discovery.h

197

uint32_t gc_num_gl2a;

sys/dev/pci/drm/amd/include/discovery.h

203

uint32_t gc_num_se;

sys/dev/pci/drm/amd/include/discovery.h

204

uint32_t gc_num_wgp0_per_sa;

sys/dev/pci/drm/amd/include/discovery.h

205

uint32_t gc_num_wgp1_per_sa;

sys/dev/pci/drm/amd/include/discovery.h

206

uint32_t gc_num_rb_per_se;

sys/dev/pci/drm/amd/include/discovery.h

207

uint32_t gc_num_gl2c;

sys/dev/pci/drm/amd/include/discovery.h

208

uint32_t gc_num_gprs;

sys/dev/pci/drm/amd/include/discovery.h

209

uint32_t gc_num_max_gs_thds;

sys/dev/pci/drm/amd/include/discovery.h

210

uint32_t gc_gs_table_depth;

sys/dev/pci/drm/amd/include/discovery.h

211

uint32_t gc_gsprim_buff_depth;

sys/dev/pci/drm/amd/include/discovery.h

212

uint32_t gc_parameter_cache_depth;

sys/dev/pci/drm/amd/include/discovery.h

213

uint32_t gc_double_offchip_lds_buffer;

sys/dev/pci/drm/amd/include/discovery.h

214

uint32_t gc_wave_size;

sys/dev/pci/drm/amd/include/discovery.h

215

uint32_t gc_max_waves_per_simd;

sys/dev/pci/drm/amd/include/discovery.h

216

uint32_t gc_max_scratch_slots_per_cu;

sys/dev/pci/drm/amd/include/discovery.h

217

uint32_t gc_lds_size;

sys/dev/pci/drm/amd/include/discovery.h

218

uint32_t gc_num_sc_per_se;

sys/dev/pci/drm/amd/include/discovery.h

219

uint32_t gc_num_sa_per_se;

sys/dev/pci/drm/amd/include/discovery.h

220

uint32_t gc_num_packer_per_sc;

sys/dev/pci/drm/amd/include/discovery.h

221

uint32_t gc_num_gl2a;

sys/dev/pci/drm/amd/include/discovery.h

222

uint32_t gc_num_tcp_per_sa;

sys/dev/pci/drm/amd/include/discovery.h

223

uint32_t gc_num_sdp_interface;

sys/dev/pci/drm/amd/include/discovery.h

224

uint32_t gc_num_tcps;

sys/dev/pci/drm/amd/include/discovery.h

229

uint32_t gc_num_se;

sys/dev/pci/drm/amd/include/discovery.h

230

uint32_t gc_num_wgp0_per_sa;

sys/dev/pci/drm/amd/include/discovery.h

231

uint32_t gc_num_wgp1_per_sa;

sys/dev/pci/drm/amd/include/discovery.h

232

uint32_t gc_num_rb_per_se;

sys/dev/pci/drm/amd/include/discovery.h

233

uint32_t gc_num_gl2c;

sys/dev/pci/drm/amd/include/discovery.h

234

uint32_t gc_num_gprs;

sys/dev/pci/drm/amd/include/discovery.h

235

uint32_t gc_num_max_gs_thds;

sys/dev/pci/drm/amd/include/discovery.h

236

uint32_t gc_gs_table_depth;

sys/dev/pci/drm/amd/include/discovery.h

237

uint32_t gc_gsprim_buff_depth;

sys/dev/pci/drm/amd/include/discovery.h

238

uint32_t gc_parameter_cache_depth;

sys/dev/pci/drm/amd/include/discovery.h

239

uint32_t gc_double_offchip_lds_buffer;

sys/dev/pci/drm/amd/include/discovery.h

240

uint32_t gc_wave_size;

sys/dev/pci/drm/amd/include/discovery.h

241

uint32_t gc_max_waves_per_simd;

sys/dev/pci/drm/amd/include/discovery.h

242

uint32_t gc_max_scratch_slots_per_cu;

sys/dev/pci/drm/amd/include/discovery.h

243

uint32_t gc_lds_size;

sys/dev/pci/drm/amd/include/discovery.h

244

uint32_t gc_num_sc_per_se;

sys/dev/pci/drm/amd/include/discovery.h

245

uint32_t gc_num_sa_per_se;

sys/dev/pci/drm/amd/include/discovery.h

246

uint32_t gc_num_packer_per_sc;

sys/dev/pci/drm/amd/include/discovery.h

247

uint32_t gc_num_gl2a;

sys/dev/pci/drm/amd/include/discovery.h

248

uint32_t gc_num_tcp_per_sa;

sys/dev/pci/drm/amd/include/discovery.h

249

uint32_t gc_num_sdp_interface;

sys/dev/pci/drm/amd/include/discovery.h

250

uint32_t gc_num_tcps;

sys/dev/pci/drm/amd/include/discovery.h

251

uint32_t gc_num_tcp_per_wpg;

sys/dev/pci/drm/amd/include/discovery.h

252

uint32_t gc_tcp_l1_size;

sys/dev/pci/drm/amd/include/discovery.h

253

uint32_t gc_num_sqc_per_wgp;

sys/dev/pci/drm/amd/include/discovery.h

254

uint32_t gc_l1_instruction_cache_size_per_sqc;

sys/dev/pci/drm/amd/include/discovery.h

255

uint32_t gc_l1_data_cache_size_per_sqc;

sys/dev/pci/drm/amd/include/discovery.h

256

uint32_t gc_gl1c_per_sa;

sys/dev/pci/drm/amd/include/discovery.h

257

uint32_t gc_gl1c_size_per_instance;

sys/dev/pci/drm/amd/include/discovery.h

258

uint32_t gc_gl2c_per_gpu;

sys/dev/pci/drm/amd/include/discovery.h

263

uint32_t gc_num_se;

sys/dev/pci/drm/amd/include/discovery.h

264

uint32_t gc_num_wgp0_per_sa;

sys/dev/pci/drm/amd/include/discovery.h

265

uint32_t gc_num_wgp1_per_sa;

sys/dev/pci/drm/amd/include/discovery.h

266

uint32_t gc_num_rb_per_se;

sys/dev/pci/drm/amd/include/discovery.h

267

uint32_t gc_num_gl2c;

sys/dev/pci/drm/amd/include/discovery.h

268

uint32_t gc_num_gprs;

sys/dev/pci/drm/amd/include/discovery.h

269

uint32_t gc_num_max_gs_thds;

sys/dev/pci/drm/amd/include/discovery.h

270

uint32_t gc_gs_table_depth;

sys/dev/pci/drm/amd/include/discovery.h

271

uint32_t gc_gsprim_buff_depth;

sys/dev/pci/drm/amd/include/discovery.h

272

uint32_t gc_parameter_cache_depth;

sys/dev/pci/drm/amd/include/discovery.h

273

uint32_t gc_double_offchip_lds_buffer;

sys/dev/pci/drm/amd/include/discovery.h

274

uint32_t gc_wave_size;

sys/dev/pci/drm/amd/include/discovery.h

275

uint32_t gc_max_waves_per_simd;

sys/dev/pci/drm/amd/include/discovery.h

276

uint32_t gc_max_scratch_slots_per_cu;

sys/dev/pci/drm/amd/include/discovery.h

277

uint32_t gc_lds_size;

sys/dev/pci/drm/amd/include/discovery.h

278

uint32_t gc_num_sc_per_se;

sys/dev/pci/drm/amd/include/discovery.h

279

uint32_t gc_num_sa_per_se;

sys/dev/pci/drm/amd/include/discovery.h

280

uint32_t gc_num_packer_per_sc;

sys/dev/pci/drm/amd/include/discovery.h

281

uint32_t gc_num_gl2a;

sys/dev/pci/drm/amd/include/discovery.h

282

uint32_t gc_num_tcp_per_sa;

sys/dev/pci/drm/amd/include/discovery.h

283

uint32_t gc_num_sdp_interface;

sys/dev/pci/drm/amd/include/discovery.h

284

uint32_t gc_num_tcps;

sys/dev/pci/drm/amd/include/discovery.h

285

uint32_t gc_num_tcp_per_wpg;

sys/dev/pci/drm/amd/include/discovery.h

286

uint32_t gc_tcp_l1_size;

sys/dev/pci/drm/amd/include/discovery.h

287

uint32_t gc_num_sqc_per_wgp;

sys/dev/pci/drm/amd/include/discovery.h

288

uint32_t gc_l1_instruction_cache_size_per_sqc;

sys/dev/pci/drm/amd/include/discovery.h

289

uint32_t gc_l1_data_cache_size_per_sqc;

sys/dev/pci/drm/amd/include/discovery.h

290

uint32_t gc_gl1c_per_sa;

sys/dev/pci/drm/amd/include/discovery.h

291

uint32_t gc_gl1c_size_per_instance;

sys/dev/pci/drm/amd/include/discovery.h

292

uint32_t gc_gl2c_per_gpu;

sys/dev/pci/drm/amd/include/discovery.h

293

uint32_t gc_tcp_size_per_cu;

sys/dev/pci/drm/amd/include/discovery.h

294

uint32_t gc_tcp_cache_line_size;

sys/dev/pci/drm/amd/include/discovery.h

295

uint32_t gc_instruction_cache_size_per_sqc;

sys/dev/pci/drm/amd/include/discovery.h

296

uint32_t gc_instruction_cache_line_size;

sys/dev/pci/drm/amd/include/discovery.h

297

uint32_t gc_scalar_data_cache_size_per_sqc;

sys/dev/pci/drm/amd/include/discovery.h

298

uint32_t gc_scalar_data_cache_line_size;

sys/dev/pci/drm/amd/include/discovery.h

299

uint32_t gc_tcc_size;

sys/dev/pci/drm/amd/include/discovery.h

300

uint32_t gc_tcc_cache_line_size;

sys/dev/pci/drm/amd/include/discovery.h

306

uint32_t gc_num_se;

sys/dev/pci/drm/amd/include/discovery.h

307

uint32_t gc_num_cu_per_sh;

sys/dev/pci/drm/amd/include/discovery.h

308

uint32_t gc_num_sh_per_se;

sys/dev/pci/drm/amd/include/discovery.h

309

uint32_t gc_num_rb_per_se;

sys/dev/pci/drm/amd/include/discovery.h

310

uint32_t gc_num_tccs;

sys/dev/pci/drm/amd/include/discovery.h

311

uint32_t gc_num_gprs;

sys/dev/pci/drm/amd/include/discovery.h

312

uint32_t gc_num_max_gs_thds;

sys/dev/pci/drm/amd/include/discovery.h

313

uint32_t gc_gs_table_depth;

sys/dev/pci/drm/amd/include/discovery.h

314

uint32_t gc_gsprim_buff_depth;

sys/dev/pci/drm/amd/include/discovery.h

315

uint32_t gc_parameter_cache_depth;

sys/dev/pci/drm/amd/include/discovery.h

316

uint32_t gc_double_offchip_lds_buffer;

sys/dev/pci/drm/amd/include/discovery.h

317

uint32_t gc_wave_size;

sys/dev/pci/drm/amd/include/discovery.h

318

uint32_t gc_max_waves_per_simd;

sys/dev/pci/drm/amd/include/discovery.h

319

uint32_t gc_max_scratch_slots_per_cu;

sys/dev/pci/drm/amd/include/discovery.h

320

uint32_t gc_lds_size;

sys/dev/pci/drm/amd/include/discovery.h

321

uint32_t gc_num_sc_per_se;

sys/dev/pci/drm/amd/include/discovery.h

322

uint32_t gc_num_packer_per_sc;

sys/dev/pci/drm/amd/include/discovery.h

328

uint32_t gc_num_se;

sys/dev/pci/drm/amd/include/discovery.h

329

uint32_t gc_num_cu_per_sh;

sys/dev/pci/drm/amd/include/discovery.h

330

uint32_t gc_num_sh_per_se;

sys/dev/pci/drm/amd/include/discovery.h

331

uint32_t gc_num_rb_per_se;

sys/dev/pci/drm/amd/include/discovery.h

332

uint32_t gc_num_tccs;

sys/dev/pci/drm/amd/include/discovery.h

333

uint32_t gc_num_gprs;

sys/dev/pci/drm/amd/include/discovery.h

334

uint32_t gc_num_max_gs_thds;

sys/dev/pci/drm/amd/include/discovery.h

335

uint32_t gc_gs_table_depth;

sys/dev/pci/drm/amd/include/discovery.h

336

uint32_t gc_gsprim_buff_depth;

sys/dev/pci/drm/amd/include/discovery.h

337

uint32_t gc_parameter_cache_depth;

sys/dev/pci/drm/amd/include/discovery.h

338

uint32_t gc_double_offchip_lds_buffer;

sys/dev/pci/drm/amd/include/discovery.h

339

uint32_t gc_wave_size;

sys/dev/pci/drm/amd/include/discovery.h

340

uint32_t gc_max_waves_per_simd;

sys/dev/pci/drm/amd/include/discovery.h

341

uint32_t gc_max_scratch_slots_per_cu;

sys/dev/pci/drm/amd/include/discovery.h

342

uint32_t gc_lds_size;

sys/dev/pci/drm/amd/include/discovery.h

343

uint32_t gc_num_sc_per_se;

sys/dev/pci/drm/amd/include/discovery.h

344

uint32_t gc_num_packer_per_sc;

sys/dev/pci/drm/amd/include/discovery.h

346

uint32_t gc_num_tcp_per_sh;

sys/dev/pci/drm/amd/include/discovery.h

347

uint32_t gc_tcp_size_per_cu;

sys/dev/pci/drm/amd/include/discovery.h

348

uint32_t gc_num_sdp_interface;

sys/dev/pci/drm/amd/include/discovery.h

349

uint32_t gc_num_cu_per_sqc;

sys/dev/pci/drm/amd/include/discovery.h

350

uint32_t gc_instruction_cache_size_per_sqc;

sys/dev/pci/drm/amd/include/discovery.h

351

uint32_t gc_scalar_data_cache_size_per_sqc;

sys/dev/pci/drm/amd/include/discovery.h

352

uint32_t gc_tcc_size;

sys/dev/pci/drm/amd/include/discovery.h

356

uint32_t signature; /* Table Signature */

sys/dev/pci/drm/amd/include/discovery.h

357

uint32_t version; /* Table Version */

sys/dev/pci/drm/amd/include/discovery.h

372

uint32_t table_id; /* table ID */

sys/dev/pci/drm/amd/include/discovery.h

375

uint32_t size_bytes; /* size of the entire header+data in bytes */

sys/dev/pci/drm/amd/include/discovery.h

380

uint32_t mall_size_per_m;

sys/dev/pci/drm/amd/include/discovery.h

381

uint32_t m_s_present;

sys/dev/pci/drm/amd/include/discovery.h

382

uint32_t m_half_use;

sys/dev/pci/drm/amd/include/discovery.h

383

uint32_t m_mall_config;

sys/dev/pci/drm/amd/include/discovery.h

384

uint32_t reserved[5];

sys/dev/pci/drm/amd/include/discovery.h

389

uint32_t mall_size_per_umc;

sys/dev/pci/drm/amd/include/discovery.h

390

uint32_t reserved[8];

sys/dev/pci/drm/amd/include/discovery.h

396

uint32_t table_id; /* table ID */

sys/dev/pci/drm/amd/include/discovery.h

399

uint32_t size_bytes; /* size of the entire header+data in bytes */

sys/dev/pci/drm/amd/include/discovery.h

404

uint32_t instance_num; /* VCN IP instance number. 0 - VCN0; 1 - VCN1 etc*/

sys/dev/pci/drm/amd/include/discovery.h

407

uint32_t av1_disabled : 1;

sys/dev/pci/drm/amd/include/discovery.h

408

uint32_t vp9_disabled : 1;

sys/dev/pci/drm/amd/include/discovery.h

409

uint32_t hevc_disabled : 1;

sys/dev/pci/drm/amd/include/discovery.h

410

uint32_t h264_disabled : 1;

sys/dev/pci/drm/amd/include/discovery.h

411

uint32_t reserved : 28;

sys/dev/pci/drm/amd/include/discovery.h

413

uint32_t all_bits;

sys/dev/pci/drm/amd/include/discovery.h

415

uint32_t reserved[2];

sys/dev/pci/drm/amd/include/discovery.h

420

uint32_t num_of_instances; /* number of entries used in instance_info below*/

sys/dev/pci/drm/amd/include/discovery.h

422

uint32_t reserved[4];

sys/dev/pci/drm/amd/include/discovery.h

428

uint32_t table_id; /* table ID */

sys/dev/pci/drm/amd/include/discovery.h

431

uint32_t size_bytes; /* size of the entire header+data in bytes = 0x000000D4 (212) */

sys/dev/pci/drm/amd/include/discovery.h

441

uint32_t nps_type;

sys/dev/pci/drm/amd/include/discovery.h

442

uint32_t count;

sys/dev/pci/drm/amd/include/discovery.h

59

uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */

sys/dev/pci/drm/amd/include/discovery.h

76

uint32_t signature; /* Table Signature */

sys/dev/pci/drm/amd/include/discovery.h

79

uint32_t id; /* Table ID */

sys/dev/pci/drm/amd/include/dm_pp_interface.h

102

uint32_t display_clk;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

108

uint32_t dce_tolerable_mclk_in_active_latency;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

109

uint32_t min_dcef_set_clk;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

110

uint32_t min_dcef_deep_sleep_set_clk;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

114

uint32_t engine_max_clock;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

115

uint32_t memory_max_clock;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

116

uint32_t level;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

137

uint32_t min_engine_clock;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

138

uint32_t max_engine_clock;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

139

uint32_t min_memory_clock;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

140

uint32_t max_memory_clock;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

141

uint32_t min_bus_bandwidth;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

142

uint32_t max_bus_bandwidth;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

143

uint32_t max_engine_clock_in_sr;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

144

uint32_t min_engine_clock_in_sr;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

164

uint32_t count;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

165

uint32_t clock[MAX_NUM_CLOCKS];

sys/dev/pci/drm/amd/include/dm_pp_interface.h

166

uint32_t latency[MAX_NUM_CLOCKS];

sys/dev/pci/drm/amd/include/dm_pp_interface.h

170

uint32_t clocks_in_khz;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

171

uint32_t latency_in_us;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

175

uint32_t num_levels;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

180

uint32_t clocks_in_khz;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

181

uint32_t voltage_in_mv;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

185

uint32_t num_levels;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

191

uint32_t clock_freq_in_khz;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

49

uint32_t controller_index;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

50

uint32_t controller_id;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

51

uint32_t signal_type;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

52

uint32_t display_state;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

62

uint32_t config_flags;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

63

uint32_t display_type;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

64

uint32_t view_resolution_cx;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

65

uint32_t view_resolution_cy;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

67

uint32_t vertical_refresh; /* for active display */

sys/dev/pci/drm/amd/include/dm_pp_interface.h

68

uint32_t pixel_clock; /* Pixel clock in KHz (for HDMI only: normalized) */

sys/dev/pci/drm/amd/include/dm_pp_interface.h

77

uint32_t cpu_pstate_separation_time;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

79

uint32_t num_display; /* total number of display*/

sys/dev/pci/drm/amd/include/dm_pp_interface.h

80

uint32_t num_path_including_non_display;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

81

uint32_t crossfire_display_index;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

82

uint32_t min_mem_set_clock;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

83

uint32_t min_core_set_clock;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

85

uint32_t min_bus_bandwidth;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

87

uint32_t min_core_set_clock_in_sr;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

91

uint32_t vrefresh; /* for active display*/

sys/dev/pci/drm/amd/include/dm_pp_interface.h

93

uint32_t min_vblank_time; /* for active display*/

sys/dev/pci/drm/amd/include/dm_pp_interface.h

97

uint32_t crtc_index;

sys/dev/pci/drm/amd/include/dm_pp_interface.h

99

uint32_t line_time_in_us;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

111

uint32_t num_pipe_per_mec;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

114

uint32_t num_queue_per_pipe;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

123

uint32_t *sdma_doorbell_idx;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

128

uint32_t non_cp_doorbells_start;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

129

uint32_t non_cp_doorbells_end;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

150

uint32_t *tile_config_ptr;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

151

uint32_t *macro_tile_config_ptr;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

152

uint32_t num_tile_configs;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

153

uint32_t num_macro_tile_configs;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

155

uint32_t gb_addr_config;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

156

uint32_t num_banks;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

157

uint32_t num_ranks;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

222

void (*program_sh_mem_settings)(struct amdgpu_device *adev, uint32_t vmid,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

223

uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

224

uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

225

uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

228

unsigned int vmid, uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

230

int (*init_interrupts)(struct amdgpu_device *adev, uint32_t pipe_id,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

231

uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

234

int (*hqd_load)(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

235

uint32_t queue_id, uint32_t __user *wptr,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

236

uint32_t wptr_shift, uint32_t wptr_mask,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

237

struct mm_struct *mm, uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

241

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

242

uint32_t doorbell_off, uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

246

uint32_t __user *wptr, struct mm_struct *mm);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

250

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

251

uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

254

uint32_t engine_id, uint32_t queue_id,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

255

uint32_t (**dump)[2], uint32_t *n_regs);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

258

uint64_t queue_address, uint32_t pipe_id,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

259

uint32_t queue_id, uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

263

unsigned int timeout, uint32_t pipe_id,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

264

uint32_t queue_id, uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

272

uint32_t gfx_index_val,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

273

uint32_t sq_cmd, uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

283

uint64_t va, uint32_t vmid);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

286

uint32_t vmid, uint64_t page_table_base);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

287

uint32_t (*read_vmid_from_vmfault_reg)(struct amdgpu_device *adev);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

289

uint32_t (*enable_debug_trap)(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

291

uint32_t vmid);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

292

uint32_t (*disable_debug_trap)(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

294

uint32_t vmid);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

296

uint32_t trap_override,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

297

uint32_t *trap_mask_supported);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

298

uint32_t (*set_wave_launch_trap_override)(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

299

uint32_t vmid,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

300

uint32_t trap_override,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

301

uint32_t trap_mask_bits,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

302

uint32_t trap_mask_request,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

303

uint32_t *trap_mask_prev,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

304

uint32_t kfd_dbg_trap_cntl_prev);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

305

uint32_t (*set_wave_launch_mode)(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

307

uint32_t vmid);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

308

uint32_t (*set_address_watch)(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

310

uint32_t watch_address_mask,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

311

uint32_t watch_id,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

312

uint32_t watch_mode,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

313

uint32_t debug_vmid,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

314

uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

315

uint32_t (*clear_address_watch)(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

316

uint32_t watch_id);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

318

uint32_t *wait_times,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

319

uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

321

uint32_t wait_times,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

322

uint32_t sch_wave,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

323

uint32_t que_sleep,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

324

uint32_t *reg_offset,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

325

uint32_t *reg_data);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

328

int *max_waves_per_cu, uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

330

uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

331

uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

333

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

334

uint32_t inst);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

336

uint32_t pipe_id, uint32_t queue_id,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

337

uint32_t inst, unsigned int utimeout);

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

338

uint32_t (*hqd_sdma_get_doorbell)(struct amdgpu_device *adev,

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

51

uint32_t vmid;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

52

uint32_t mc_id;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

53

uint32_t status;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

64

uint32_t vram_width;

sys/dev/pci/drm/amd/include/kgd_kfd_interface.h

65

uint32_t mem_clk_max;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1000

uint32_t pcie_nak_rcvd_count_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1023

uint32_t pcie_lc_perf_other_end_recovery;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1051

uint32_t accumulation_counter;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1054

uint32_t prochot_residency_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1055

uint32_t ppt_residency_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1056

uint32_t socket_thm_residency_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1057

uint32_t vr_thm_residency_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1058

uint32_t hbm_thm_residency_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1061

uint32_t gfxclk_lock_status;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1072

uint32_t gfx_activity_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1073

uint32_t mem_activity_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1091

uint32_t pcie_nak_sent_count_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1094

uint32_t pcie_nak_rcvd_count_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1122

uint32_t pcie_lc_perf_other_end_recovery;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1150

uint32_t accumulation_counter;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1153

uint32_t prochot_residency_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1154

uint32_t ppt_residency_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1155

uint32_t socket_thm_residency_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1156

uint32_t vr_thm_residency_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1157

uint32_t hbm_thm_residency_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1160

uint32_t gfxclk_lock_status;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1171

uint32_t gfx_activity_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1172

uint32_t mem_activity_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1190

uint32_t pcie_nak_sent_count_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1193

uint32_t pcie_nak_rcvd_count_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1221

uint32_t pcie_lc_perf_other_end_recovery;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1270

uint32_t throttle_status;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1320

uint32_t throttle_status;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1370

uint32_t throttle_status;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1423

uint32_t throttle_status;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1482

uint32_t throttle_status;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1545

uint32_t average_socket_power;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1549

uint32_t average_apu_power;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1551

uint32_t average_gfx_power;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1553

uint32_t average_dgpu_power;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1555

uint32_t average_all_core_power;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1584

uint32_t throttle_residency_prochot;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1585

uint32_t throttle_residency_spl;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1586

uint32_t throttle_residency_fppt;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1587

uint32_t throttle_residency_sppt;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1588

uint32_t throttle_residency_thm_core;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1589

uint32_t throttle_residency_thm_gfx;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1590

uint32_t throttle_residency_thm_soc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1593

uint32_t time_filter_alphavalue;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1599

uint32_t mp1_ip_discovery_version;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1600

uint32_t pmfw_version;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1601

uint32_t pmmetrics_version;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1670

uint32_t node_temp[AMDGPU_NODE_MAX_TEMP_ENTRIES];

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1671

uint32_t vr_temp[AMDGPU_VR_MAX_TEMP_ENTRIES];

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1680

uint32_t system_temp[AMDGPU_SYSTEM_MAX_TEMP_ENTRIES];

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

1694

uint32_t gfx_busy_inst[MAX_XCC];

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

223

uint32_t nums;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

224

uint32_t states[16];

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

375

uint32_t gfx_busy_inst[MAX_XCC];

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

384

uint32_t gfx_busy_inst[MAX_XCC];

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

395

uint32_t gfx_busy_inst[MAX_XCC];

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

425

int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

430

int (*set_sclk_od)(void *handle, uint32_t value);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

432

int (*set_mclk_od)(void *handle, uint32_t value);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

434

int (*get_apu_thermal_limit)(void *handle, uint32_t *limit);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

435

int (*set_apu_thermal_limit)(void *handle, uint32_t limit);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

438

int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

439

int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

453

uint32_t block_type,

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

456

int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

457

int (*set_power_limit)(void *handle, uint32_t n);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

458

int (*get_power_limit)(void *handle, uint32_t *limit,

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

462

int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

463

int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

465

long *input, uint32_t size);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

468

int (*gfx_state_change_set)(void *handle, uint32_t state);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

495

int (*set_active_display_count)(void *handle, uint32_t count);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

496

int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

497

int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

498

int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

507

int (*set_xgmi_pstate)(void *handle, uint32_t pstate);

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

560

uint32_t energy_accumulator;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

581

uint32_t throttle_status;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

633

uint32_t throttle_status;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

644

uint32_t gfx_activity_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

645

uint32_t mem_activity_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

692

uint32_t throttle_status;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

703

uint32_t gfx_activity_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

704

uint32_t mem_activity_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

754

uint32_t throttle_status;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

765

uint32_t gfx_activity_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

766

uint32_t mem_activity_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

807

uint32_t throttle_status;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

810

uint32_t gfxclk_lock_status;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

821

uint32_t gfx_activity_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

822

uint32_t mem_activity_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

880

uint32_t throttle_status;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

883

uint32_t gfxclk_lock_status;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

894

uint32_t gfx_activity_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

895

uint32_t mem_activity_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

913

uint32_t pcie_nak_sent_count_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

916

uint32_t pcie_nak_rcvd_count_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

957

uint32_t accumulation_counter;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

960

uint32_t prochot_residency_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

961

uint32_t ppt_residency_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

962

uint32_t socket_thm_residency_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

963

uint32_t vr_thm_residency_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

964

uint32_t hbm_thm_residency_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

967

uint32_t gfxclk_lock_status;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

978

uint32_t gfx_activity_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

979

uint32_t mem_activity_acc;

sys/dev/pci/drm/amd/include/kgd_pp_interface.h

997

uint32_t pcie_nak_sent_count_acc;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

174

uint32_t first_free_entry_index;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

175

uint32_t wraparound_count;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

182

uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

183

uint32_t reserved_operation_type_bits;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

206

uint32_t vmid_mask_mmhub;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

207

uint32_t vmid_mask_gfxhub;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

208

uint32_t gds_size;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

209

uint32_t paging_vmid;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

210

uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

211

uint32_t gfx_hqd_mask[MAX_GFX_PIPES];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

212

uint32_t sdma_hqd_mask[MAX_SDMA_PIPES];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

213

uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

216

uint32_t gc_base[MES_MAX_HWIP_SEGMENT];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

217

uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

218

uint32_t osssys_base[MES_MAX_HWIP_SEGMENT];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

222

uint32_t disable_reset : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

223

uint32_t use_different_vmid_compute : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

224

uint32_t disable_mes_log : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

225

uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

226

uint32_t apply_grbm_remote_register_dummy_read_wa : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

227

uint32_t second_gfx_pipe_enabled : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

228

uint32_t enable_level_process_quantum_check : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

229

uint32_t legacy_sch_mode : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

230

uint32_t disable_add_queue_wptr_mc_addr : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

231

uint32_t enable_mes_event_int_logging : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

232

uint32_t enable_reg_active_poll : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

233

uint32_t use_disable_queue_in_legacy_uq_preemption : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

234

uint32_t send_write_data : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

235

uint32_t os_tdr_timeout_override : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

236

uint32_t use_rs64mem_for_proc_gang_ctx : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

237

uint32_t use_add_queue_unmap_flag_addr : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

238

uint32_t enable_mes_sch_stb_log : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

239

uint32_t limit_single_process : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

240

uint32_t is_strix_tmz_wa_enabled :1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

241

uint32_t enable_lr_compute_wa : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

242

uint32_t reserved : 12;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

244

uint32_t uint32_t_all;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

246

uint32_t oversubscription_timer;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

250

uint32_t os_tdr_timeout_in_sec;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

253

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

263

uint32_t enable_mes_info_ctx : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

264

uint32_t reserved : 31;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

266

uint32_t uint32_all;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

269

uint32_t mes_info_ctx_size;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

274

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

280

uint32_t process_id;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

288

uint32_t inprocess_gang_priority;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

290

uint32_t doorbell_offset;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

296

uint32_t gds_base;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

297

uint32_t gds_size;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

298

uint32_t gws_base;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

299

uint32_t gws_size;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

300

uint32_t oa_mask;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

302

uint32_t vm_context_cntl;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

305

uint32_t paging : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

306

uint32_t debug_vmid : 4;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

307

uint32_t program_gds : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

308

uint32_t is_gang_suspended : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

309

uint32_t is_tmz_queue : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

310

uint32_t map_kiq_utility_queue : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

311

uint32_t is_kfd_process : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

312

uint32_t trap_en : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

313

uint32_t is_aql_queue : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

314

uint32_t skip_process_ctx_clear : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

315

uint32_t map_legacy_kq : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

316

uint32_t exclusively_scheduled : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

317

uint32_t is_long_running : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

318

uint32_t is_dwm_queue : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

319

uint32_t is_video_blit_queue : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

320

uint32_t reserved : 14;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

324

uint32_t sch_id;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

326

uint32_t process_context_array_index;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

327

uint32_t gang_context_array_index;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

328

uint32_t pipe_id;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

329

uint32_t queue_id;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

330

uint32_t alignment_mode_setting;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

334

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

340

uint32_t doorbell_offset;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

344

uint32_t unmap_legacy_gfx_queue : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

345

uint32_t unmap_kiq_utility_queue : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

346

uint32_t preempt_legacy_gfx_queue : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

347

uint32_t unmap_legacy_queue : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

348

uint32_t reserved : 28;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

352

uint32_t pipe_id;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

353

uint32_t queue_id;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

356

uint32_t tf_data;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

361

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

384

uint32_t normal_yield_percent;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

388

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

394

uint32_t dummy;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

398

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

404

uint32_t inprocess_gang_priority;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

411

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

419

uint32_t suspend_all_gangs : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

420

uint32_t reserved : 31;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

426

uint32_t suspend_fence_value;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

431

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

439

uint32_t resume_all_gangs : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

440

uint32_t reserved : 31;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

448

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

457

uint32_t reset_queue_only : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

459

uint32_t hang_detect_then_reset : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

461

uint32_t hang_detect_only : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

463

uint32_t reset_legacy_gfx : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

464

uint32_t reserved : 28;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

470

uint32_t doorbell_offset;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

477

uint32_t pipe_id_lp;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

478

uint32_t queue_id_lp;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

479

uint32_t vmid_id_lp;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

481

uint32_t doorbell_offset_lp;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

484

uint32_t pipe_id_hp;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

485

uint32_t queue_id_hp;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

486

uint32_t vmid_id_hp;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

488

uint32_t doorbell_offset_hp;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

494

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

505

uint32_t number_of_entries;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

507

uint32_t interrupt_entry;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

512

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

522

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

529

uint32_t gds_base;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

530

uint32_t gds_size;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

531

uint32_t gws_base;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

532

uint32_t gws_size;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

533

uint32_t oa_mask;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

537

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

546

uint32_t use_gds : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

547

uint32_t operation : 2;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

548

uint32_t reserved : 29;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

550

uint32_t u32All;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

552

uint32_t reserved;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

553

uint32_t debug_vmid;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

558

uint32_t gds_base;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

559

uint32_t gds_size;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

560

uint32_t gws_base;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

561

uint32_t gws_size;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

562

uint32_t oa_mask;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

568

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

589

uint32_t reg_offset;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

590

uint32_t reg_value;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

594

uint32_t reg_offset;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

606

uint32_t reference;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

607

uint32_t mask;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

608

uint32_t reg_offset1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

609

uint32_t reg_offset2;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

618

uint32_t context_id;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

625

uint32_t single_memop : 1; /* SQ_DEBUG.single_memop */

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

626

uint32_t single_alu_op : 1; /* SQ_DEBUG.single_alu_op */

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

627

uint32_t reserved : 29;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

628

uint32_t process_ctx_flush : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

630

uint32_t u32all;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

632

uint32_t spi_gdbg_per_vmid_cntl;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

633

uint32_t tcp_watch_cntl[4]; /* TCP_WATCHx_CNTL */

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

634

uint32_t trap_en;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

649

uint32_t limit_single_process : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

650

uint32_t enable_hws_logging_buffer : 1;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

651

uint32_t reserved : 31;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

653

uint32_t all;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

657

uint32_t tdr_level;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

658

uint32_t tdr_delay;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

678

uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

682

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

693

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

704

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

73

uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

74

uint32_t opcode : 8;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

75

uint32_t dwsize : 8; /* including header */

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

76

uint32_t reserved : 12;

sys/dev/pci/drm/amd/include/mes_v11_api_def.h

79

uint32_t u32All;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

221

uint32_t first_free_entry_index;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

222

uint32_t wraparound_count;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

229

uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

230

uint32_t reserved_operation_type_bits;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

253

uint32_t vmid_mask_mmhub;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

254

uint32_t vmid_mask_gfxhub;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

255

uint32_t gds_size;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

256

uint32_t paging_vmid;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

257

uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

258

uint32_t gfx_hqd_mask[MAX_GFX_PIPES];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

259

uint32_t sdma_hqd_mask[MAX_SDMA_PIPES];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

260

uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

263

uint32_t gc_base[MES_MAX_HWIP_SEGMENT];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

264

uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

265

uint32_t osssys_base[MES_MAX_HWIP_SEGMENT];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

269

uint32_t disable_reset : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

270

uint32_t use_different_vmid_compute : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

271

uint32_t disable_mes_log : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

272

uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

273

uint32_t apply_grbm_remote_register_dummy_read_wa : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

274

uint32_t second_gfx_pipe_enabled : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

275

uint32_t enable_level_process_quantum_check : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

276

uint32_t legacy_sch_mode : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

277

uint32_t disable_add_queue_wptr_mc_addr : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

278

uint32_t enable_mes_event_int_logging : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

279

uint32_t enable_reg_active_poll : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

280

uint32_t use_disable_queue_in_legacy_uq_preemption : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

281

uint32_t send_write_data : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

282

uint32_t os_tdr_timeout_override : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

283

uint32_t use_rs64mem_for_proc_gang_ctx : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

284

uint32_t halt_on_misaligned_access : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

285

uint32_t use_add_queue_unmap_flag_addr : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

286

uint32_t enable_mes_sch_stb_log : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

287

uint32_t limit_single_process : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

288

uint32_t unmapped_doorbell_handling: 2;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

289

uint32_t enable_mes_fence_int: 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

290

uint32_t enable_lr_compute_wa : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

291

uint32_t reserved : 9;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

293

uint32_t uint32_all;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

295

uint32_t oversubscription_timer;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

299

uint32_t os_tdr_timeout_in_sec;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

302

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

312

uint32_t enable_mes_debug_ctx : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

313

uint32_t reserved : 31;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

315

uint32_t uint32_all;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

318

uint32_t mes_debug_ctx_size;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

320

uint32_t mes_kiq_unmap_timeout;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

325

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

331

uint32_t process_id;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

339

uint32_t inprocess_gang_priority;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

341

uint32_t doorbell_offset;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

348

uint32_t gds_base;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

351

uint32_t gds_size;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

352

uint32_t kfd_queue_size;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

354

uint32_t gws_base;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

355

uint32_t gws_size;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

356

uint32_t oa_mask;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

358

uint32_t vm_context_cntl;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

361

uint32_t paging : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

362

uint32_t debug_vmid : 4;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

363

uint32_t program_gds : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

364

uint32_t is_gang_suspended : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

365

uint32_t is_tmz_queue : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

366

uint32_t map_kiq_utility_queue : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

367

uint32_t is_kfd_process : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

368

uint32_t trap_en : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

369

uint32_t is_aql_queue : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

370

uint32_t skip_process_ctx_clear : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

371

uint32_t map_legacy_kq : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

372

uint32_t exclusively_scheduled : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

373

uint32_t is_long_running : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

374

uint32_t is_dwm_queue : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

375

uint32_t reserved : 15;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

379

uint32_t sch_id;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

381

uint32_t process_context_array_index;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

382

uint32_t gang_context_array_index;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

383

uint32_t pipe_id; //used for mapping legacy kernel queue

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

384

uint32_t queue_id;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

385

uint32_t alignment_mode_setting;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

388

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

394

uint32_t doorbell_offset;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

398

uint32_t reserved01 : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

399

uint32_t unmap_kiq_utility_queue : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

400

uint32_t preempt_legacy_gfx_queue : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

401

uint32_t unmap_legacy_queue : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

402

uint32_t reserved : 28;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

406

uint32_t pipe_id;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

407

uint32_t queue_id;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

410

uint32_t tf_data;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

414

uint32_t gang_context_array_index;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

417

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

437

uint32_t normal_yield_percent;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

443

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

449

uint32_t dummy;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

454

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

460

uint32_t inprocess_gang_priority;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

465

uint32_t doorbell_offset;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

467

uint32_t gang_context_array_index;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

469

uint32_t queue_quantum_scale : 2;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

470

uint32_t queue_quantum_duration : 8;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

471

uint32_t apply_quantum_all_processes : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

472

uint32_t reserved : 21;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

476

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

484

uint32_t suspend_all_gangs : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

485

uint32_t reserved : 31;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

492

uint32_t suspend_fence_value;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

497

uint32_t return_value; // to be removed

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

498

uint32_t sch_id; //keep the old return_value temporarily for compatibility

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

500

uint32_t doorbell_offset;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

504

uint32_t gang_context_array_index;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

507

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

515

uint32_t resume_all_gangs : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

516

uint32_t reserved : 31;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

522

uint32_t doorbell_offset;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

524

uint32_t gang_context_array_index;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

527

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

536

uint32_t reset_queue_only : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

538

uint32_t hang_detect_then_reset : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

540

uint32_t hang_detect_only : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

542

uint32_t reset_legacy_gfx : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

544

uint32_t use_connected_queue_index : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

546

uint32_t use_connected_queue_index_p1 : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

547

uint32_t reserved : 26;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

553

uint32_t doorbell_offset;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

560

uint32_t pipe_id_lp;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

561

uint32_t queue_id_lp;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

562

uint32_t vmid_id_lp;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

564

uint32_t doorbell_offset_lp;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

567

uint32_t pipe_id_hp;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

568

uint32_t queue_id_hp;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

569

uint32_t vmid_id_hp;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

571

uint32_t doorbell_offset_hp;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

575

uint32_t active_vmids;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

578

uint32_t gang_context_array_index;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

580

uint32_t connected_queue_index;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

581

uint32_t connected_queue_index_p1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

584

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

595

uint32_t number_of_entries;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

597

uint32_t interrupt_entry;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

601

uint32_t vmid;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

604

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

633

uint32_t data[QUERY_MES_MAX_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

637

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

646

uint32_t use_gds : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

647

uint32_t operation : 2;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

648

uint32_t reserved : 29;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

650

uint32_t u32All;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

652

uint32_t reserved;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

653

uint32_t debug_vmid;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

658

uint32_t gds_base;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

659

uint32_t gds_size;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

660

uint32_t gws_base;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

661

uint32_t gws_size;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

662

uint32_t oa_mask;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

668

uint32_t process_vm_cntl;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

671

uint32_t process_context_array_index;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

673

uint32_t alignment_mode_setting;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

676

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

699

uint32_t reg_offset;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

700

uint32_t reg_value;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

704

uint32_t reg_offset;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

708

uint32_t read64Bits : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

709

uint32_t reserved : 31;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

711

uint32_t all;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

721

uint32_t context_id;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

734

uint32_t reference;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

735

uint32_t mask;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

736

uint32_t reg_offset1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

737

uint32_t reg_offset2;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

744

uint32_t single_memop : 1; // SQ_DEBUG.single_memop

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

745

uint32_t single_alu_op : 1; // SQ_DEBUG.single_alu_op

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

746

uint32_t reserved : 30;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

748

uint32_t u32all;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

750

uint32_t spi_gdbg_per_vmid_cntl;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

751

uint32_t tcp_watch_cntl[4]; // TCP_WATCHx_CNTL

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

752

uint32_t trap_en;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

758

uint32_t gang_context_array_index;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

759

uint32_t slave_gang_context_array_index;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

76

uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

77

uint32_t opcode : 8;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

774

uint32_t limit_single_process : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

775

uint32_t enable_hws_logging_buffer : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

776

uint32_t reserved : 30;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

778

uint32_t all;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

78

uint32_t dwsize : 8; /* including header */

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

782

uint32_t tdr_level;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

783

uint32_t tdr_delay;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

79

uint32_t reserved : 12;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

801

uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

804

uint32_t doorbell_offset;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

805

uint32_t os_fence;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

808

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

818

uint32_t process_context_array_index;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

82

uint32_t u32All;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

821

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

833

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

850

uint32_t cpg_ctxt_sync_fence_value;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

854

uint32_t log_seq_time : 1;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

855

uint32_t reserved : 31;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

857

uint32_t uint32_all;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

862

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

872

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

885

uint32_t hub_id;

sys/dev/pci/drm/amd/include/mes_v12_api_def.h

901

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

101

uint32_t first_free_entry_index;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

102

uint32_t wraparound_count;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

109

uint32_t operation_type; /* operation_type is of UMSCH_LOG_OPERATION type */

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

110

uint32_t reserved_operation_type_bits;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

144

uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

145

uint32_t opcode : 8;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

146

uint32_t dwsize : 8;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

147

uint32_t reserved : 12;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

150

uint32_t u32All;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

184

uint32_t api_completion_fence_value;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

213

uint32_t vmid_mask_mm_vcn;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

214

uint32_t vmid_mask_mm_vpe;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

215

uint32_t collaboration_mask_vpe;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

216

uint32_t engine_mask;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

217

uint32_t logging_vmid;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

218

uint32_t vcn0_hqd_mask[MAX_VCN0_INSTANCES];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

219

uint32_t vcn1_hqd_mask[MAX_VCN1_INSTANCES];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

220

uint32_t vcn_hqd_mask[MAX_VCN_INSTANCES];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

221

uint32_t vpe_hqd_mask[MAX_VPE_INSTANCES];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

223

uint32_t mmhub_base[UMSCH_MAX_HWIP_SEGMENT];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

224

uint32_t mmhub_version;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

225

uint32_t osssys_base[UMSCH_MAX_HWIP_SEGMENT];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

226

uint32_t osssys_version;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

227

uint32_t vcn_version;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

228

uint32_t vpe_version;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

232

uint32_t disable_reset : 1;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

233

uint32_t disable_umsch_log : 1;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

234

uint32_t enable_level_process_quantum_check : 1;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

235

uint32_t is_vcn0_enabled : 1;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

236

uint32_t is_vcn1_enabled : 1;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

237

uint32_t use_rs64mem_for_proc_ctx_csa : 1;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

238

uint32_t reserved : 26;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

240

uint32_t uint32_all;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

244

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

246

static_assert(sizeof(union UMSCHAPI__SET_HW_RESOURCES) <= API_FRAME_SIZE_IN_DWORDS * sizeof(uint32_t),

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

269

uint32_t normal_yield_percent;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

274

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

280

uint32_t process_id;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

288

uint32_t inprocess_context_priority;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

290

uint32_t doorbell_offset_0;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

291

uint32_t doorbell_offset_1;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

297

uint32_t vm_context_cntl;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

300

uint32_t is_context_suspended : 1;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

301

uint32_t collaboration_mode : 1;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

302

uint32_t reserved : 30;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

305

uint32_t process_csa_array_index;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

306

uint32_t context_csa_array_index;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

309

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

316

uint32_t doorbell_offset_0;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

317

uint32_t doorbell_offset_1;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

321

uint32_t context_csa_array_index;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

324

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

330

uint32_t dummy;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

334

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

342

uint32_t suspend_fence_value;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

345

uint32_t context_csa_array_index;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

348

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

365

uint32_t context_csa_array_index;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

368

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

387

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

398

uint32_t number_of_entries;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

400

uint32_t interrupt_entry;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

405

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

414

uint32_t context_csa_array_index;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

417

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

423

uint32_t inprocess_context_priority;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

428

uint32_t context_csa_array_index;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

431

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

441

uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

71

uint32_t instance_index;

sys/dev/pci/drm/amd/include/umsch_mm_4_0_api_def.h

72

uint32_t doorbell_offset;

sys/dev/pci/drm/amd/include/v10_structs.h

100

uint32_t reserved_72; // offset: 72 (0x48)

sys/dev/pci/drm/amd/include/v10_structs.h

1000

uint32_t reserved_324;

sys/dev/pci/drm/amd/include/v10_structs.h

1001

uint32_t reserved_325;

sys/dev/pci/drm/amd/include/v10_structs.h

1002

uint32_t reserved_326;

sys/dev/pci/drm/amd/include/v10_structs.h

1003

uint32_t reserved_327;

sys/dev/pci/drm/amd/include/v10_structs.h

1004

uint32_t reserved_328;

sys/dev/pci/drm/amd/include/v10_structs.h

1005

uint32_t reserved_329;

sys/dev/pci/drm/amd/include/v10_structs.h

1006

uint32_t reserved_330;

sys/dev/pci/drm/amd/include/v10_structs.h

1007

uint32_t reserved_331;

sys/dev/pci/drm/amd/include/v10_structs.h

1008

uint32_t reserved_332;

sys/dev/pci/drm/amd/include/v10_structs.h

1009

uint32_t reserved_333;

sys/dev/pci/drm/amd/include/v10_structs.h

101

uint32_t reserved_73; // offset: 73 (0x49)

sys/dev/pci/drm/amd/include/v10_structs.h

1010

uint32_t reserved_334;

sys/dev/pci/drm/amd/include/v10_structs.h

1011

uint32_t reserved_335;

sys/dev/pci/drm/amd/include/v10_structs.h

1012

uint32_t reserved_336;

sys/dev/pci/drm/amd/include/v10_structs.h

1013

uint32_t reserved_337;

sys/dev/pci/drm/amd/include/v10_structs.h

1014

uint32_t reserved_338;

sys/dev/pci/drm/amd/include/v10_structs.h

1015

uint32_t reserved_339;

sys/dev/pci/drm/amd/include/v10_structs.h

1016

uint32_t reserved_340;

sys/dev/pci/drm/amd/include/v10_structs.h

1017

uint32_t reserved_341;

sys/dev/pci/drm/amd/include/v10_structs.h

1018

uint32_t reserved_342;

sys/dev/pci/drm/amd/include/v10_structs.h

1019

uint32_t reserved_343;

sys/dev/pci/drm/amd/include/v10_structs.h

102

uint32_t reserved_74; // offset: 74 (0x4A)

sys/dev/pci/drm/amd/include/v10_structs.h

1020

uint32_t reserved_344;

sys/dev/pci/drm/amd/include/v10_structs.h

1021

uint32_t reserved_345;

sys/dev/pci/drm/amd/include/v10_structs.h

1022

uint32_t reserved_346;

sys/dev/pci/drm/amd/include/v10_structs.h

1023

uint32_t reserved_347;

sys/dev/pci/drm/amd/include/v10_structs.h

1024

uint32_t reserved_348;

sys/dev/pci/drm/amd/include/v10_structs.h

1025

uint32_t reserved_349;

sys/dev/pci/drm/amd/include/v10_structs.h

1026

uint32_t reserved_350;

sys/dev/pci/drm/amd/include/v10_structs.h

1027

uint32_t reserved_351;

sys/dev/pci/drm/amd/include/v10_structs.h

1028

uint32_t reserved_352;

sys/dev/pci/drm/amd/include/v10_structs.h

1029

uint32_t reserved_353;

sys/dev/pci/drm/amd/include/v10_structs.h

103

uint32_t reserved_75; // offset: 75 (0x4B)

sys/dev/pci/drm/amd/include/v10_structs.h

1030

uint32_t reserved_354;

sys/dev/pci/drm/amd/include/v10_structs.h

1031

uint32_t reserved_355;

sys/dev/pci/drm/amd/include/v10_structs.h

1032

uint32_t reserved_356;

sys/dev/pci/drm/amd/include/v10_structs.h

1033

uint32_t reserved_357;

sys/dev/pci/drm/amd/include/v10_structs.h

1034

uint32_t reserved_358;

sys/dev/pci/drm/amd/include/v10_structs.h

1035

uint32_t reserved_359;

sys/dev/pci/drm/amd/include/v10_structs.h

1036

uint32_t reserved_360;

sys/dev/pci/drm/amd/include/v10_structs.h

1037

uint32_t reserved_361;

sys/dev/pci/drm/amd/include/v10_structs.h

1038

uint32_t reserved_362;

sys/dev/pci/drm/amd/include/v10_structs.h

1039

uint32_t reserved_363;

sys/dev/pci/drm/amd/include/v10_structs.h

104

uint32_t reserved_76; // offset: 76 (0x4C)

sys/dev/pci/drm/amd/include/v10_structs.h

1040

uint32_t reserved_364;

sys/dev/pci/drm/amd/include/v10_structs.h

1041

uint32_t reserved_365;

sys/dev/pci/drm/amd/include/v10_structs.h

1042

uint32_t reserved_366;

sys/dev/pci/drm/amd/include/v10_structs.h

1043

uint32_t reserved_367;

sys/dev/pci/drm/amd/include/v10_structs.h

1044

uint32_t reserved_368;

sys/dev/pci/drm/amd/include/v10_structs.h

1045

uint32_t reserved_369;

sys/dev/pci/drm/amd/include/v10_structs.h

1046

uint32_t reserved_370;

sys/dev/pci/drm/amd/include/v10_structs.h

1047

uint32_t reserved_371;

sys/dev/pci/drm/amd/include/v10_structs.h

1048

uint32_t reserved_372;

sys/dev/pci/drm/amd/include/v10_structs.h

1049

uint32_t reserved_373;

sys/dev/pci/drm/amd/include/v10_structs.h

105

uint32_t reserved_77; // offset: 77 (0x4D)

sys/dev/pci/drm/amd/include/v10_structs.h

1050

uint32_t reserved_374;

sys/dev/pci/drm/amd/include/v10_structs.h

1051

uint32_t reserved_375;

sys/dev/pci/drm/amd/include/v10_structs.h

1052

uint32_t reserved_376;

sys/dev/pci/drm/amd/include/v10_structs.h

1053

uint32_t reserved_377;

sys/dev/pci/drm/amd/include/v10_structs.h

1054

uint32_t reserved_378;

sys/dev/pci/drm/amd/include/v10_structs.h

1055

uint32_t reserved_379;

sys/dev/pci/drm/amd/include/v10_structs.h

1056

uint32_t reserved_380;

sys/dev/pci/drm/amd/include/v10_structs.h

1057

uint32_t reserved_381;

sys/dev/pci/drm/amd/include/v10_structs.h

1058

uint32_t reserved_382;

sys/dev/pci/drm/amd/include/v10_structs.h

1059

uint32_t reserved_383;

sys/dev/pci/drm/amd/include/v10_structs.h

106

uint32_t reserved_78; // offset: 78 (0x4E)

sys/dev/pci/drm/amd/include/v10_structs.h

1060

uint32_t reserved_384;

sys/dev/pci/drm/amd/include/v10_structs.h

1061

uint32_t reserved_385;

sys/dev/pci/drm/amd/include/v10_structs.h

1062

uint32_t reserved_386;

sys/dev/pci/drm/amd/include/v10_structs.h

1063

uint32_t reserved_387;

sys/dev/pci/drm/amd/include/v10_structs.h

1064

uint32_t reserved_388;

sys/dev/pci/drm/amd/include/v10_structs.h

1065

uint32_t reserved_389;

sys/dev/pci/drm/amd/include/v10_structs.h

1066

uint32_t reserved_390;

sys/dev/pci/drm/amd/include/v10_structs.h

1067

uint32_t reserved_391;

sys/dev/pci/drm/amd/include/v10_structs.h

1068

uint32_t reserved_392;

sys/dev/pci/drm/amd/include/v10_structs.h

1069

uint32_t reserved_393;

sys/dev/pci/drm/amd/include/v10_structs.h

107

uint32_t reserved_79; // offset: 79 (0x4F)

sys/dev/pci/drm/amd/include/v10_structs.h

1070

uint32_t reserved_394;

sys/dev/pci/drm/amd/include/v10_structs.h

1071

uint32_t reserved_395;

sys/dev/pci/drm/amd/include/v10_structs.h

1072

uint32_t reserved_396;

sys/dev/pci/drm/amd/include/v10_structs.h

1073

uint32_t reserved_397;

sys/dev/pci/drm/amd/include/v10_structs.h

1074

uint32_t reserved_398;

sys/dev/pci/drm/amd/include/v10_structs.h

1075

uint32_t reserved_399;

sys/dev/pci/drm/amd/include/v10_structs.h

1076

uint32_t reserved_400;

sys/dev/pci/drm/amd/include/v10_structs.h

1077

uint32_t reserved_401;

sys/dev/pci/drm/amd/include/v10_structs.h

1078

uint32_t reserved_402;

sys/dev/pci/drm/amd/include/v10_structs.h

1079

uint32_t reserved_403;

sys/dev/pci/drm/amd/include/v10_structs.h

108

uint32_t reserved_80; // offset: 80 (0x50)

sys/dev/pci/drm/amd/include/v10_structs.h

1080

uint32_t reserved_404;

sys/dev/pci/drm/amd/include/v10_structs.h

1081

uint32_t reserved_405;

sys/dev/pci/drm/amd/include/v10_structs.h

1082

uint32_t reserved_406;

sys/dev/pci/drm/amd/include/v10_structs.h

1083

uint32_t reserved_407;

sys/dev/pci/drm/amd/include/v10_structs.h

1084

uint32_t reserved_408;

sys/dev/pci/drm/amd/include/v10_structs.h

1085

uint32_t reserved_409;

sys/dev/pci/drm/amd/include/v10_structs.h

1086

uint32_t reserved_410;

sys/dev/pci/drm/amd/include/v10_structs.h

1087

uint32_t reserved_411;

sys/dev/pci/drm/amd/include/v10_structs.h

1088

uint32_t reserved_412;

sys/dev/pci/drm/amd/include/v10_structs.h

1089

uint32_t reserved_413;

sys/dev/pci/drm/amd/include/v10_structs.h

109

uint32_t reserved_81; // offset: 81 (0x51)

sys/dev/pci/drm/amd/include/v10_structs.h

1090

uint32_t reserved_414;

sys/dev/pci/drm/amd/include/v10_structs.h

1091

uint32_t reserved_415;

sys/dev/pci/drm/amd/include/v10_structs.h

1092

uint32_t reserved_416;

sys/dev/pci/drm/amd/include/v10_structs.h

1093

uint32_t reserved_417;

sys/dev/pci/drm/amd/include/v10_structs.h

1094

uint32_t reserved_418;

sys/dev/pci/drm/amd/include/v10_structs.h

1095

uint32_t reserved_419;

sys/dev/pci/drm/amd/include/v10_structs.h

1096

uint32_t reserved_420;

sys/dev/pci/drm/amd/include/v10_structs.h

1097

uint32_t reserved_421;

sys/dev/pci/drm/amd/include/v10_structs.h

1098

uint32_t reserved_422;

sys/dev/pci/drm/amd/include/v10_structs.h

1099

uint32_t reserved_423;

sys/dev/pci/drm/amd/include/v10_structs.h

110

uint32_t reserved_82; // offset: 82 (0x52)

sys/dev/pci/drm/amd/include/v10_structs.h

1100

uint32_t reserved_424;

sys/dev/pci/drm/amd/include/v10_structs.h

1101

uint32_t reserved_425;

sys/dev/pci/drm/amd/include/v10_structs.h

1102

uint32_t reserved_426;

sys/dev/pci/drm/amd/include/v10_structs.h

1103

uint32_t reserved_427;

sys/dev/pci/drm/amd/include/v10_structs.h

1104

uint32_t reserved_428;

sys/dev/pci/drm/amd/include/v10_structs.h

1105

uint32_t reserved_429;

sys/dev/pci/drm/amd/include/v10_structs.h

1106

uint32_t reserved_430;

sys/dev/pci/drm/amd/include/v10_structs.h

1107

uint32_t reserved_431;

sys/dev/pci/drm/amd/include/v10_structs.h

1108

uint32_t reserved_432;

sys/dev/pci/drm/amd/include/v10_structs.h

1109

uint32_t reserved_433;

sys/dev/pci/drm/amd/include/v10_structs.h

111

uint32_t reserved_83; // offset: 83 (0x53)

sys/dev/pci/drm/amd/include/v10_structs.h

1110

uint32_t reserved_434;

sys/dev/pci/drm/amd/include/v10_structs.h

1111

uint32_t reserved_435;

sys/dev/pci/drm/amd/include/v10_structs.h

1112

uint32_t reserved_436;

sys/dev/pci/drm/amd/include/v10_structs.h

1113

uint32_t reserved_437;

sys/dev/pci/drm/amd/include/v10_structs.h

1114

uint32_t reserved_438;

sys/dev/pci/drm/amd/include/v10_structs.h

1115

uint32_t reserved_439;

sys/dev/pci/drm/amd/include/v10_structs.h

1116

uint32_t reserved_440;

sys/dev/pci/drm/amd/include/v10_structs.h

1117

uint32_t reserved_441;

sys/dev/pci/drm/amd/include/v10_structs.h

1118

uint32_t reserved_442;

sys/dev/pci/drm/amd/include/v10_structs.h

1119

uint32_t reserved_443;

sys/dev/pci/drm/amd/include/v10_structs.h

112

uint32_t reserved_84; // offset: 84 (0x54)

sys/dev/pci/drm/amd/include/v10_structs.h

1120

uint32_t reserved_444;

sys/dev/pci/drm/amd/include/v10_structs.h

1121

uint32_t reserved_445;

sys/dev/pci/drm/amd/include/v10_structs.h

1122

uint32_t reserved_446;

sys/dev/pci/drm/amd/include/v10_structs.h

1123

uint32_t reserved_447;

sys/dev/pci/drm/amd/include/v10_structs.h

1124

uint32_t reserved_448;

sys/dev/pci/drm/amd/include/v10_structs.h

1125

uint32_t reserved_449;

sys/dev/pci/drm/amd/include/v10_structs.h

1126

uint32_t reserved_450;

sys/dev/pci/drm/amd/include/v10_structs.h

1127

uint32_t reserved_451;

sys/dev/pci/drm/amd/include/v10_structs.h

1128

uint32_t reserved_452;

sys/dev/pci/drm/amd/include/v10_structs.h

1129

uint32_t reserved_453;

sys/dev/pci/drm/amd/include/v10_structs.h

113

uint32_t reserved_85; // offset: 85 (0x55)

sys/dev/pci/drm/amd/include/v10_structs.h

1130

uint32_t reserved_454;

sys/dev/pci/drm/amd/include/v10_structs.h

1131

uint32_t reserved_455;

sys/dev/pci/drm/amd/include/v10_structs.h

1132

uint32_t reserved_456;

sys/dev/pci/drm/amd/include/v10_structs.h

1133

uint32_t reserved_457;

sys/dev/pci/drm/amd/include/v10_structs.h

1134

uint32_t reserved_458;

sys/dev/pci/drm/amd/include/v10_structs.h

1135

uint32_t reserved_459;

sys/dev/pci/drm/amd/include/v10_structs.h

1136

uint32_t reserved_460;

sys/dev/pci/drm/amd/include/v10_structs.h

1137

uint32_t reserved_461;

sys/dev/pci/drm/amd/include/v10_structs.h

1138

uint32_t reserved_462;

sys/dev/pci/drm/amd/include/v10_structs.h

1139

uint32_t reserved_463;

sys/dev/pci/drm/amd/include/v10_structs.h

114

uint32_t reserved_86; // offset: 86 (0x56)

sys/dev/pci/drm/amd/include/v10_structs.h

1140

uint32_t reserved_464;

sys/dev/pci/drm/amd/include/v10_structs.h

1141

uint32_t reserved_465;

sys/dev/pci/drm/amd/include/v10_structs.h

1142

uint32_t reserved_466;

sys/dev/pci/drm/amd/include/v10_structs.h

1143

uint32_t reserved_467;

sys/dev/pci/drm/amd/include/v10_structs.h

1144

uint32_t reserved_468;

sys/dev/pci/drm/amd/include/v10_structs.h

1145

uint32_t reserved_469;

sys/dev/pci/drm/amd/include/v10_structs.h

1146

uint32_t reserved_470;

sys/dev/pci/drm/amd/include/v10_structs.h

1147

uint32_t reserved_471;

sys/dev/pci/drm/amd/include/v10_structs.h

1148

uint32_t reserved_472;

sys/dev/pci/drm/amd/include/v10_structs.h

1149

uint32_t reserved_473;

sys/dev/pci/drm/amd/include/v10_structs.h

115

uint32_t reserved_87; // offset: 87 (0x57)

sys/dev/pci/drm/amd/include/v10_structs.h

1150

uint32_t reserved_474;

sys/dev/pci/drm/amd/include/v10_structs.h

1151

uint32_t reserved_475;

sys/dev/pci/drm/amd/include/v10_structs.h

1152

uint32_t reserved_476;

sys/dev/pci/drm/amd/include/v10_structs.h

1153

uint32_t reserved_477;

sys/dev/pci/drm/amd/include/v10_structs.h

1154

uint32_t reserved_478;

sys/dev/pci/drm/amd/include/v10_structs.h

1155

uint32_t reserved_479;

sys/dev/pci/drm/amd/include/v10_structs.h

1156

uint32_t reserved_480;

sys/dev/pci/drm/amd/include/v10_structs.h

1157

uint32_t reserved_481;

sys/dev/pci/drm/amd/include/v10_structs.h

1158

uint32_t reserved_482;

sys/dev/pci/drm/amd/include/v10_structs.h

1159

uint32_t reserved_483;

sys/dev/pci/drm/amd/include/v10_structs.h

116

uint32_t reserved_88; // offset: 88 (0x58)

sys/dev/pci/drm/amd/include/v10_structs.h

1160

uint32_t reserved_484;

sys/dev/pci/drm/amd/include/v10_structs.h

1161

uint32_t reserved_485;

sys/dev/pci/drm/amd/include/v10_structs.h

1162

uint32_t reserved_486;

sys/dev/pci/drm/amd/include/v10_structs.h

1163

uint32_t reserved_487;

sys/dev/pci/drm/amd/include/v10_structs.h

1164

uint32_t reserved_488;

sys/dev/pci/drm/amd/include/v10_structs.h

1165

uint32_t reserved_489;

sys/dev/pci/drm/amd/include/v10_structs.h

1166

uint32_t reserved_490;

sys/dev/pci/drm/amd/include/v10_structs.h

1167

uint32_t reserved_491;

sys/dev/pci/drm/amd/include/v10_structs.h

1168

uint32_t reserved_492;

sys/dev/pci/drm/amd/include/v10_structs.h

1169

uint32_t reserved_493;

sys/dev/pci/drm/amd/include/v10_structs.h

117

uint32_t reserved_89; // offset: 89 (0x59)

sys/dev/pci/drm/amd/include/v10_structs.h

1170

uint32_t reserved_494;

sys/dev/pci/drm/amd/include/v10_structs.h

1171

uint32_t reserved_495;

sys/dev/pci/drm/amd/include/v10_structs.h

1172

uint32_t reserved_496;

sys/dev/pci/drm/amd/include/v10_structs.h

1173

uint32_t reserved_497;

sys/dev/pci/drm/amd/include/v10_structs.h

1174

uint32_t reserved_498;

sys/dev/pci/drm/amd/include/v10_structs.h

1175

uint32_t reserved_499;

sys/dev/pci/drm/amd/include/v10_structs.h

1176

uint32_t reserved_500;

sys/dev/pci/drm/amd/include/v10_structs.h

1177

uint32_t reserved_501;

sys/dev/pci/drm/amd/include/v10_structs.h

1178

uint32_t reserved_502;

sys/dev/pci/drm/amd/include/v10_structs.h

1179

uint32_t reserved_503;

sys/dev/pci/drm/amd/include/v10_structs.h

118

uint32_t reserved_90; // offset: 90 (0x5A)

sys/dev/pci/drm/amd/include/v10_structs.h

1180

uint32_t reserved_504;

sys/dev/pci/drm/amd/include/v10_structs.h

1181

uint32_t reserved_505;

sys/dev/pci/drm/amd/include/v10_structs.h

1182

uint32_t reserved_506;

sys/dev/pci/drm/amd/include/v10_structs.h

1183

uint32_t reserved_507;

sys/dev/pci/drm/amd/include/v10_structs.h

1184

uint32_t reserved_508;

sys/dev/pci/drm/amd/include/v10_structs.h

1185

uint32_t reserved_509;

sys/dev/pci/drm/amd/include/v10_structs.h

1186

uint32_t reserved_510;

sys/dev/pci/drm/amd/include/v10_structs.h

1187

uint32_t reserved_511;

sys/dev/pci/drm/amd/include/v10_structs.h

119

uint32_t reserved_91; // offset: 91 (0x5B)

sys/dev/pci/drm/amd/include/v10_structs.h

1192

uint32_t ce_ib_completion_status;

sys/dev/pci/drm/amd/include/v10_structs.h

1193

uint32_t ce_constegnine_count;

sys/dev/pci/drm/amd/include/v10_structs.h

1194

uint32_t ce_ibOffset_ib1;

sys/dev/pci/drm/amd/include/v10_structs.h

1195

uint32_t ce_ibOffset_ib2;

sys/dev/pci/drm/amd/include/v10_structs.h

1198

uint32_t ce_chainib_addrlo_ib1;

sys/dev/pci/drm/amd/include/v10_structs.h

1199

uint32_t ce_chainib_addrlo_ib2;

sys/dev/pci/drm/amd/include/v10_structs.h

120

uint32_t reserved_92; // offset: 92 (0x5C)

sys/dev/pci/drm/amd/include/v10_structs.h

1200

uint32_t ce_chainib_addrhi_ib1;

sys/dev/pci/drm/amd/include/v10_structs.h

1201

uint32_t ce_chainib_addrhi_ib2;

sys/dev/pci/drm/amd/include/v10_structs.h

1202

uint32_t ce_chainib_size_ib1;

sys/dev/pci/drm/amd/include/v10_structs.h

1203

uint32_t ce_chainib_size_ib2;

sys/dev/pci/drm/amd/include/v10_structs.h

1208

uint32_t ib_completion_status;

sys/dev/pci/drm/amd/include/v10_structs.h

1209

uint32_t de_constEngine_count;

sys/dev/pci/drm/amd/include/v10_structs.h

121

uint32_t reserved_93; // offset: 93 (0x5D)

sys/dev/pci/drm/amd/include/v10_structs.h

1210

uint32_t ib_offset_ib1;

sys/dev/pci/drm/amd/include/v10_structs.h

1211

uint32_t ib_offset_ib2;

sys/dev/pci/drm/amd/include/v10_structs.h

1214

uint32_t chain_ib_addrlo_ib1;

sys/dev/pci/drm/amd/include/v10_structs.h

1215

uint32_t chain_ib_addrlo_ib2;

sys/dev/pci/drm/amd/include/v10_structs.h

1216

uint32_t chain_ib_addrhi_ib1;

sys/dev/pci/drm/amd/include/v10_structs.h

1217

uint32_t chain_ib_addrhi_ib2;

sys/dev/pci/drm/amd/include/v10_structs.h

1218

uint32_t chain_ib_size_ib1;

sys/dev/pci/drm/amd/include/v10_structs.h

1219

uint32_t chain_ib_size_ib2;

sys/dev/pci/drm/amd/include/v10_structs.h

122

uint32_t reserved_94; // offset: 94 (0x5E)

sys/dev/pci/drm/amd/include/v10_structs.h

1222

uint32_t preamble_begin_ib1;

sys/dev/pci/drm/amd/include/v10_structs.h

1223

uint32_t preamble_begin_ib2;

sys/dev/pci/drm/amd/include/v10_structs.h

1224

uint32_t preamble_end_ib1;

sys/dev/pci/drm/amd/include/v10_structs.h

1225

uint32_t preamble_end_ib2;

sys/dev/pci/drm/amd/include/v10_structs.h

1228

uint32_t chain_ib_pream_addrlo_ib1;

sys/dev/pci/drm/amd/include/v10_structs.h

1229

uint32_t chain_ib_pream_addrlo_ib2;

sys/dev/pci/drm/amd/include/v10_structs.h

123

uint32_t reserved_95; // offset: 95 (0x5F)

sys/dev/pci/drm/amd/include/v10_structs.h

1230

uint32_t chain_ib_pream_addrhi_ib1;

sys/dev/pci/drm/amd/include/v10_structs.h

1231

uint32_t chain_ib_pream_addrhi_ib2;

sys/dev/pci/drm/amd/include/v10_structs.h

1234

uint32_t draw_indirect_baseLo;

sys/dev/pci/drm/amd/include/v10_structs.h

1235

uint32_t draw_indirect_baseHi;

sys/dev/pci/drm/amd/include/v10_structs.h

1236

uint32_t disp_indirect_baseLo;

sys/dev/pci/drm/amd/include/v10_structs.h

1237

uint32_t disp_indirect_baseHi;

sys/dev/pci/drm/amd/include/v10_structs.h

1238

uint32_t gds_backup_addrlo;

sys/dev/pci/drm/amd/include/v10_structs.h

1239

uint32_t gds_backup_addrhi;

sys/dev/pci/drm/amd/include/v10_structs.h

124

uint32_t reserved_96; // offset: 96 (0x60)

sys/dev/pci/drm/amd/include/v10_structs.h

1240

uint32_t index_base_addrlo;

sys/dev/pci/drm/amd/include/v10_structs.h

1241

uint32_t index_base_addrhi;

sys/dev/pci/drm/amd/include/v10_structs.h

1242

uint32_t sample_cntl;

sys/dev/pci/drm/amd/include/v10_structs.h

1248

uint32_t reserved1[54];

sys/dev/pci/drm/amd/include/v10_structs.h

125

uint32_t reserved_97; // offset: 97 (0x61)

sys/dev/pci/drm/amd/include/v10_structs.h

1252

uint32_t DeIbBaseAddrLo;

sys/dev/pci/drm/amd/include/v10_structs.h

1253

uint32_t DeIbBaseAddrHi;

sys/dev/pci/drm/amd/include/v10_structs.h

1254

uint32_t reserved2[931];

sys/dev/pci/drm/amd/include/v10_structs.h

126

uint32_t reserved_98; // offset: 98 (0x62)

sys/dev/pci/drm/amd/include/v10_structs.h

127

uint32_t reserved_99; // offset: 99 (0x63)

sys/dev/pci/drm/amd/include/v10_structs.h

128

uint32_t reserved_100; // offset: 100 (0x64)

sys/dev/pci/drm/amd/include/v10_structs.h

129

uint32_t reserved_101; // offset: 101 (0x65)

sys/dev/pci/drm/amd/include/v10_structs.h

130

uint32_t reserved_102; // offset: 102 (0x66)

sys/dev/pci/drm/amd/include/v10_structs.h

131

uint32_t reserved_103; // offset: 103 (0x67)

sys/dev/pci/drm/amd/include/v10_structs.h

132

uint32_t reserved_104; // offset: 104 (0x68)

sys/dev/pci/drm/amd/include/v10_structs.h

133

uint32_t reserved_105; // offset: 105 (0x69)

sys/dev/pci/drm/amd/include/v10_structs.h

134

uint32_t disable_queue; // offset: 106 (0x6A)

sys/dev/pci/drm/amd/include/v10_structs.h

135

uint32_t reserved_107; // offset: 107 (0x6B)

sys/dev/pci/drm/amd/include/v10_structs.h

136

uint32_t reserved_108; // offset: 108 (0x6C)

sys/dev/pci/drm/amd/include/v10_structs.h

137

uint32_t reserved_109; // offset: 109 (0x6D)

sys/dev/pci/drm/amd/include/v10_structs.h

138

uint32_t reserved_110; // offset: 110 (0x6E)

sys/dev/pci/drm/amd/include/v10_structs.h

139

uint32_t reserved_111; // offset: 111 (0x6F)

sys/dev/pci/drm/amd/include/v10_structs.h

140

uint32_t reserved_112; // offset: 112 (0x70)

sys/dev/pci/drm/amd/include/v10_structs.h

141

uint32_t reserved_113; // offset: 113 (0x71)

sys/dev/pci/drm/amd/include/v10_structs.h

142

uint32_t reserved_114; // offset: 114 (0x72)

sys/dev/pci/drm/amd/include/v10_structs.h

143

uint32_t reserved_115; // offset: 115 (0x73)

sys/dev/pci/drm/amd/include/v10_structs.h

144

uint32_t reserved_116; // offset: 116 (0x74)

sys/dev/pci/drm/amd/include/v10_structs.h

145

uint32_t reserved_117; // offset: 117 (0x75)

sys/dev/pci/drm/amd/include/v10_structs.h

146

uint32_t reserved_118; // offset: 118 (0x76)

sys/dev/pci/drm/amd/include/v10_structs.h

147

uint32_t reserved_119; // offset: 119 (0x77)

sys/dev/pci/drm/amd/include/v10_structs.h

148

uint32_t reserved_120; // offset: 120 (0x78)

sys/dev/pci/drm/amd/include/v10_structs.h

149

uint32_t reserved_121; // offset: 121 (0x79)

sys/dev/pci/drm/amd/include/v10_structs.h

150

uint32_t reserved_122; // offset: 122 (0x7A)

sys/dev/pci/drm/amd/include/v10_structs.h

151

uint32_t reserved_123; // offset: 123 (0x7B)

sys/dev/pci/drm/amd/include/v10_structs.h

152

uint32_t reserved_124; // offset: 124 (0x7C)

sys/dev/pci/drm/amd/include/v10_structs.h

153

uint32_t reserved_125; // offset: 125 (0x7D)

sys/dev/pci/drm/amd/include/v10_structs.h

154

uint32_t reserved_126; // offset: 126 (0x7E)

sys/dev/pci/drm/amd/include/v10_structs.h

155

uint32_t reserved_127; // offset: 127 (0x7F)

sys/dev/pci/drm/amd/include/v10_structs.h

156

uint32_t cp_mqd_base_addr; // offset: 128 (0x80)

sys/dev/pci/drm/amd/include/v10_structs.h

157

uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81)

sys/dev/pci/drm/amd/include/v10_structs.h

158

uint32_t cp_gfx_hqd_active; // offset: 130 (0x82)

sys/dev/pci/drm/amd/include/v10_structs.h

159

uint32_t cp_gfx_hqd_vmid; // offset: 131 (0x83)

sys/dev/pci/drm/amd/include/v10_structs.h

160

uint32_t reserved_131; // offset: 132 (0x84)

sys/dev/pci/drm/amd/include/v10_structs.h

161

uint32_t reserved_132; // offset: 133 (0x85)

sys/dev/pci/drm/amd/include/v10_structs.h

162

uint32_t cp_gfx_hqd_queue_priority; // offset: 134 (0x86)

sys/dev/pci/drm/amd/include/v10_structs.h

163

uint32_t cp_gfx_hqd_quantum; // offset: 135 (0x87)

sys/dev/pci/drm/amd/include/v10_structs.h

164

uint32_t cp_gfx_hqd_base; // offset: 136 (0x88)

sys/dev/pci/drm/amd/include/v10_structs.h

165

uint32_t cp_gfx_hqd_base_hi; // offset: 137 (0x89)

sys/dev/pci/drm/amd/include/v10_structs.h

166

uint32_t cp_gfx_hqd_rptr; // offset: 138 (0x8A)

sys/dev/pci/drm/amd/include/v10_structs.h

167

uint32_t cp_gfx_hqd_rptr_addr; // offset: 139 (0x8B)

sys/dev/pci/drm/amd/include/v10_structs.h

168

uint32_t cp_gfx_hqd_rptr_addr_hi; // offset: 140 (0x8C)

sys/dev/pci/drm/amd/include/v10_structs.h

169

uint32_t cp_rb_wptr_poll_addr_lo; // offset: 141 (0x8D)

sys/dev/pci/drm/amd/include/v10_structs.h

170

uint32_t cp_rb_wptr_poll_addr_hi; // offset: 142 (0x8E)

sys/dev/pci/drm/amd/include/v10_structs.h

171

uint32_t cp_rb_doorbell_control; // offset: 143 (0x8F)

sys/dev/pci/drm/amd/include/v10_structs.h

172

uint32_t cp_gfx_hqd_offset; // offset: 144 (0x90)

sys/dev/pci/drm/amd/include/v10_structs.h

173

uint32_t cp_gfx_hqd_cntl; // offset: 145 (0x91)

sys/dev/pci/drm/amd/include/v10_structs.h

174

uint32_t reserved_146; // offset: 146 (0x92)

sys/dev/pci/drm/amd/include/v10_structs.h

175

uint32_t reserved_147; // offset: 147 (0x93)

sys/dev/pci/drm/amd/include/v10_structs.h

176

uint32_t cp_gfx_hqd_csmd_rptr; // offset: 148 (0x94)

sys/dev/pci/drm/amd/include/v10_structs.h

177

uint32_t cp_gfx_hqd_wptr; // offset: 149 (0x95)

sys/dev/pci/drm/amd/include/v10_structs.h

178

uint32_t cp_gfx_hqd_wptr_hi; // offset: 150 (0x96)

sys/dev/pci/drm/amd/include/v10_structs.h

179

uint32_t reserved_151; // offset: 151 (0x97)

sys/dev/pci/drm/amd/include/v10_structs.h

180

uint32_t reserved_152; // offset: 152 (0x98)

sys/dev/pci/drm/amd/include/v10_structs.h

181

uint32_t reserved_153; // offset: 153 (0x99)

sys/dev/pci/drm/amd/include/v10_structs.h

182

uint32_t reserved_154; // offset: 154 (0x9A)

sys/dev/pci/drm/amd/include/v10_structs.h

183

uint32_t reserved_155; // offset: 155 (0x9B)

sys/dev/pci/drm/amd/include/v10_structs.h

184

uint32_t cp_gfx_hqd_mapped; // offset: 156 (0x9C)

sys/dev/pci/drm/amd/include/v10_structs.h

185

uint32_t cp_gfx_hqd_que_mgr_control; // offset: 157 (0x9D)

sys/dev/pci/drm/amd/include/v10_structs.h

186

uint32_t reserved_158; // offset: 158 (0x9E)

sys/dev/pci/drm/amd/include/v10_structs.h

187

uint32_t reserved_159; // offset: 159 (0x9F)

sys/dev/pci/drm/amd/include/v10_structs.h

188

uint32_t cp_gfx_hqd_hq_status0; // offset: 160 (0xA0)

sys/dev/pci/drm/amd/include/v10_structs.h

189

uint32_t cp_gfx_hqd_hq_control0; // offset: 161 (0xA1)

sys/dev/pci/drm/amd/include/v10_structs.h

190

uint32_t cp_gfx_mqd_control; // offset: 162 (0xA2)

sys/dev/pci/drm/amd/include/v10_structs.h

191

uint32_t reserved_163; // offset: 163 (0xA3)

sys/dev/pci/drm/amd/include/v10_structs.h

192

uint32_t reserved_164; // offset: 164 (0xA4)

sys/dev/pci/drm/amd/include/v10_structs.h

193

uint32_t reserved_165; // offset: 165 (0xA5)

sys/dev/pci/drm/amd/include/v10_structs.h

194

uint32_t reserved_166; // offset: 166 (0xA6)

sys/dev/pci/drm/amd/include/v10_structs.h

195

uint32_t reserved_167; // offset: 167 (0xA7)

sys/dev/pci/drm/amd/include/v10_structs.h

196

uint32_t reserved_168; // offset: 168 (0xA8)

sys/dev/pci/drm/amd/include/v10_structs.h

197

uint32_t reserved_169; // offset: 169 (0xA9)

sys/dev/pci/drm/amd/include/v10_structs.h

198

uint32_t cp_num_prim_needed_count0_lo; // offset: 170 (0xAA)

sys/dev/pci/drm/amd/include/v10_structs.h

199

uint32_t cp_num_prim_needed_count0_hi; // offset: 171 (0xAB)

sys/dev/pci/drm/amd/include/v10_structs.h

200

uint32_t cp_num_prim_needed_count1_lo; // offset: 172 (0xAC)

sys/dev/pci/drm/amd/include/v10_structs.h

201

uint32_t cp_num_prim_needed_count1_hi; // offset: 173 (0xAD)

sys/dev/pci/drm/amd/include/v10_structs.h

202

uint32_t cp_num_prim_needed_count2_lo; // offset: 174 (0xAE)

sys/dev/pci/drm/amd/include/v10_structs.h

203

uint32_t cp_num_prim_needed_count2_hi; // offset: 175 (0xAF)

sys/dev/pci/drm/amd/include/v10_structs.h

204

uint32_t cp_num_prim_needed_count3_lo; // offset: 176 (0xB0)

sys/dev/pci/drm/amd/include/v10_structs.h

205

uint32_t cp_num_prim_needed_count3_hi; // offset: 177 (0xB1)

sys/dev/pci/drm/amd/include/v10_structs.h

206

uint32_t cp_num_prim_written_count0_lo; // offset: 178 (0xB2)

sys/dev/pci/drm/amd/include/v10_structs.h

207

uint32_t cp_num_prim_written_count0_hi; // offset: 179 (0xB3)

sys/dev/pci/drm/amd/include/v10_structs.h

208

uint32_t cp_num_prim_written_count1_lo; // offset: 180 (0xB4)

sys/dev/pci/drm/amd/include/v10_structs.h

209

uint32_t cp_num_prim_written_count1_hi; // offset: 181 (0xB5)

sys/dev/pci/drm/amd/include/v10_structs.h

210

uint32_t cp_num_prim_written_count2_lo; // offset: 182 (0xB6)

sys/dev/pci/drm/amd/include/v10_structs.h

211

uint32_t cp_num_prim_written_count2_hi; // offset: 183 (0xB7)

sys/dev/pci/drm/amd/include/v10_structs.h

212

uint32_t cp_num_prim_written_count3_lo; // offset: 184 (0xB8)

sys/dev/pci/drm/amd/include/v10_structs.h

213

uint32_t cp_num_prim_written_count3_hi; // offset: 185 (0xB9)

sys/dev/pci/drm/amd/include/v10_structs.h

214

uint32_t reserved_186; // offset: 186 (0xBA)

sys/dev/pci/drm/amd/include/v10_structs.h

215

uint32_t reserved_187; // offset: 187 (0xBB)

sys/dev/pci/drm/amd/include/v10_structs.h

216

uint32_t reserved_188; // offset: 188 (0xBC)

sys/dev/pci/drm/amd/include/v10_structs.h

217

uint32_t reserved_189; // offset: 189 (0xBD)

sys/dev/pci/drm/amd/include/v10_structs.h

218

uint32_t mp1_smn_fps_cnt; // offset: 190 (0xBE)

sys/dev/pci/drm/amd/include/v10_structs.h

219

uint32_t sq_thread_trace_buf0_base; // offset: 191 (0xBF)

sys/dev/pci/drm/amd/include/v10_structs.h

220

uint32_t sq_thread_trace_buf0_size; // offset: 192 (0xC0)

sys/dev/pci/drm/amd/include/v10_structs.h

221

uint32_t sq_thread_trace_buf1_base; // offset: 193 (0xC1)

sys/dev/pci/drm/amd/include/v10_structs.h

222

uint32_t sq_thread_trace_buf1_size; // offset: 194 (0xC2)

sys/dev/pci/drm/amd/include/v10_structs.h

223

uint32_t sq_thread_trace_wptr; // offset: 195 (0xC3)

sys/dev/pci/drm/amd/include/v10_structs.h

224

uint32_t sq_thread_trace_mask; // offset: 196 (0xC4)

sys/dev/pci/drm/amd/include/v10_structs.h

225

uint32_t sq_thread_trace_token_mask; // offset: 197 (0xC5)

sys/dev/pci/drm/amd/include/v10_structs.h

226

uint32_t sq_thread_trace_ctrl; // offset: 198 (0xC6)

sys/dev/pci/drm/amd/include/v10_structs.h

227

uint32_t sq_thread_trace_status; // offset: 199 (0xC7)

sys/dev/pci/drm/amd/include/v10_structs.h

228

uint32_t sq_thread_trace_dropped_cntr; // offset: 200 (0xC8)

sys/dev/pci/drm/amd/include/v10_structs.h

229

uint32_t sq_thread_trace_finish_done_debug; // offset: 201 (0xC9)

sys/dev/pci/drm/amd/include/v10_structs.h

230

uint32_t sq_thread_trace_gfx_draw_cntr; // offset: 202 (0xCA)

sys/dev/pci/drm/amd/include/v10_structs.h

231

uint32_t sq_thread_trace_gfx_marker_cntr; // offset: 203 (0xCB)

sys/dev/pci/drm/amd/include/v10_structs.h

232

uint32_t sq_thread_trace_hp3d_draw_cntr; // offset: 204 (0xCC)

sys/dev/pci/drm/amd/include/v10_structs.h

233

uint32_t sq_thread_trace_hp3d_marker_cntr; // offset: 205 (0xCD)

sys/dev/pci/drm/amd/include/v10_structs.h

234

uint32_t reserved_206; // offset: 206 (0xCE)

sys/dev/pci/drm/amd/include/v10_structs.h

235

uint32_t reserved_207; // offset: 207 (0xCF)

sys/dev/pci/drm/amd/include/v10_structs.h

236

uint32_t cp_sc_psinvoc_count0_lo; // offset: 208 (0xD0)

sys/dev/pci/drm/amd/include/v10_structs.h

237

uint32_t cp_sc_psinvoc_count0_hi; // offset: 209 (0xD1)

sys/dev/pci/drm/amd/include/v10_structs.h

238

uint32_t cp_pa_cprim_count_lo; // offset: 210 (0xD2)

sys/dev/pci/drm/amd/include/v10_structs.h

239

uint32_t cp_pa_cprim_count_hi; // offset: 211 (0xD3)

sys/dev/pci/drm/amd/include/v10_structs.h

240

uint32_t cp_pa_cinvoc_count_lo; // offset: 212 (0xD4)

sys/dev/pci/drm/amd/include/v10_structs.h

241

uint32_t cp_pa_cinvoc_count_hi; // offset: 213 (0xD5)

sys/dev/pci/drm/amd/include/v10_structs.h

242

uint32_t cp_vgt_vsinvoc_count_lo; // offset: 214 (0xD6)

sys/dev/pci/drm/amd/include/v10_structs.h

243

uint32_t cp_vgt_vsinvoc_count_hi; // offset: 215 (0xD7)

sys/dev/pci/drm/amd/include/v10_structs.h

244

uint32_t cp_vgt_gsinvoc_count_lo; // offset: 216 (0xD8)

sys/dev/pci/drm/amd/include/v10_structs.h

245

uint32_t cp_vgt_gsinvoc_count_hi; // offset: 217 (0xD9)

sys/dev/pci/drm/amd/include/v10_structs.h

246

uint32_t cp_vgt_gsprim_count_lo; // offset: 218 (0xDA)

sys/dev/pci/drm/amd/include/v10_structs.h

247

uint32_t cp_vgt_gsprim_count_hi; // offset: 219 (0xDB)

sys/dev/pci/drm/amd/include/v10_structs.h

248

uint32_t cp_vgt_iaprim_count_lo; // offset: 220 (0xDC)

sys/dev/pci/drm/amd/include/v10_structs.h

249

uint32_t cp_vgt_iaprim_count_hi; // offset: 221 (0xDD)

sys/dev/pci/drm/amd/include/v10_structs.h

250

uint32_t cp_vgt_iavert_count_lo; // offset: 222 (0xDE)

sys/dev/pci/drm/amd/include/v10_structs.h

251

uint32_t cp_vgt_iavert_count_hi; // offset: 223 (0xDF)

sys/dev/pci/drm/amd/include/v10_structs.h

252

uint32_t cp_vgt_hsinvoc_count_lo; // offset: 224 (0xE0)

sys/dev/pci/drm/amd/include/v10_structs.h

253

uint32_t cp_vgt_hsinvoc_count_hi; // offset: 225 (0xE1)

sys/dev/pci/drm/amd/include/v10_structs.h

254

uint32_t cp_vgt_dsinvoc_count_lo; // offset: 226 (0xE2)

sys/dev/pci/drm/amd/include/v10_structs.h

255

uint32_t cp_vgt_dsinvoc_count_hi; // offset: 227 (0xE3)

sys/dev/pci/drm/amd/include/v10_structs.h

256

uint32_t cp_vgt_csinvoc_count_lo; // offset: 228 (0xE4)

sys/dev/pci/drm/amd/include/v10_structs.h

257

uint32_t cp_vgt_csinvoc_count_hi; // offset: 229 (0xE5)

sys/dev/pci/drm/amd/include/v10_structs.h

258

uint32_t reserved_230; // offset: 230 (0xE6)

sys/dev/pci/drm/amd/include/v10_structs.h

259

uint32_t reserved_231; // offset: 231 (0xE7)

sys/dev/pci/drm/amd/include/v10_structs.h

260

uint32_t reserved_232; // offset: 232 (0xE8)

sys/dev/pci/drm/amd/include/v10_structs.h

261

uint32_t reserved_233; // offset: 233 (0xE9)

sys/dev/pci/drm/amd/include/v10_structs.h

262

uint32_t reserved_234; // offset: 234 (0xEA)

sys/dev/pci/drm/amd/include/v10_structs.h

263

uint32_t reserved_235; // offset: 235 (0xEB)

sys/dev/pci/drm/amd/include/v10_structs.h

264

uint32_t reserved_236; // offset: 236 (0xEC)

sys/dev/pci/drm/amd/include/v10_structs.h

265

uint32_t reserved_237; // offset: 237 (0xED)

sys/dev/pci/drm/amd/include/v10_structs.h

266

uint32_t reserved_238; // offset: 238 (0xEE)

sys/dev/pci/drm/amd/include/v10_structs.h

267

uint32_t reserved_239; // offset: 239 (0xEF)

sys/dev/pci/drm/amd/include/v10_structs.h

268

uint32_t reserved_240; // offset: 240 (0xF0)

sys/dev/pci/drm/amd/include/v10_structs.h

269

uint32_t reserved_241; // offset: 241 (0xF1)

sys/dev/pci/drm/amd/include/v10_structs.h

270

uint32_t reserved_242; // offset: 242 (0xF2)

sys/dev/pci/drm/amd/include/v10_structs.h

271

uint32_t reserved_243; // offset: 243 (0xF3)

sys/dev/pci/drm/amd/include/v10_structs.h

272

uint32_t reserved_244; // offset: 244 (0xF4)

sys/dev/pci/drm/amd/include/v10_structs.h

273

uint32_t reserved_245; // offset: 245 (0xF5)

sys/dev/pci/drm/amd/include/v10_structs.h

274

uint32_t reserved_246; // offset: 246 (0xF6)

sys/dev/pci/drm/amd/include/v10_structs.h

275

uint32_t reserved_247; // offset: 247 (0xF7)

sys/dev/pci/drm/amd/include/v10_structs.h

276

uint32_t reserved_248; // offset: 248 (0xF8)

sys/dev/pci/drm/amd/include/v10_structs.h

277

uint32_t reserved_249; // offset: 249 (0xF9)

sys/dev/pci/drm/amd/include/v10_structs.h

278

uint32_t reserved_250; // offset: 250 (0xFA)

sys/dev/pci/drm/amd/include/v10_structs.h

279

uint32_t reserved_251; // offset: 251 (0xFB)

sys/dev/pci/drm/amd/include/v10_structs.h

28

uint32_t reserved_0; // offset: 0 (0x0)

sys/dev/pci/drm/amd/include/v10_structs.h

280

uint32_t reserved_252; // offset: 252 (0xFC)

sys/dev/pci/drm/amd/include/v10_structs.h

281

uint32_t reserved_253; // offset: 253 (0xFD)

sys/dev/pci/drm/amd/include/v10_structs.h

282

uint32_t reserved_254; // offset: 254 (0xFE)

sys/dev/pci/drm/amd/include/v10_structs.h

283

uint32_t reserved_255; // offset: 255 (0xFF)

sys/dev/pci/drm/amd/include/v10_structs.h

284

uint32_t reserved_256; // offset: 256 (0x100)

sys/dev/pci/drm/amd/include/v10_structs.h

285

uint32_t reserved_257; // offset: 257 (0x101)

sys/dev/pci/drm/amd/include/v10_structs.h

286

uint32_t reserved_258; // offset: 258 (0x102)

sys/dev/pci/drm/amd/include/v10_structs.h

287

uint32_t reserved_259; // offset: 259 (0x103)

sys/dev/pci/drm/amd/include/v10_structs.h

288

uint32_t reserved_260; // offset: 260 (0x104)

sys/dev/pci/drm/amd/include/v10_structs.h

289

uint32_t reserved_261; // offset: 261 (0x105)

sys/dev/pci/drm/amd/include/v10_structs.h

29

uint32_t reserved_1; // offset: 1 (0x1)

sys/dev/pci/drm/amd/include/v10_structs.h

290

uint32_t reserved_262; // offset: 262 (0x106)

sys/dev/pci/drm/amd/include/v10_structs.h

291

uint32_t reserved_263; // offset: 263 (0x107)

sys/dev/pci/drm/amd/include/v10_structs.h

292

uint32_t reserved_264; // offset: 264 (0x108)

sys/dev/pci/drm/amd/include/v10_structs.h

293

uint32_t reserved_265; // offset: 265 (0x109)

sys/dev/pci/drm/amd/include/v10_structs.h

294

uint32_t reserved_266; // offset: 266 (0x10A)

sys/dev/pci/drm/amd/include/v10_structs.h

295

uint32_t reserved_267; // offset: 267 (0x10B)

sys/dev/pci/drm/amd/include/v10_structs.h

296

uint32_t vgt_strmout_buffer_filled_size_0; // offset: 268 (0x10C)

sys/dev/pci/drm/amd/include/v10_structs.h

297

uint32_t vgt_strmout_buffer_filled_size_1; // offset: 269 (0x10D)

sys/dev/pci/drm/amd/include/v10_structs.h

298

uint32_t vgt_strmout_buffer_filled_size_2; // offset: 270 (0x10E)

sys/dev/pci/drm/amd/include/v10_structs.h

299

uint32_t vgt_strmout_buffer_filled_size_3; // offset: 271 (0x10F)

sys/dev/pci/drm/amd/include/v10_structs.h

30

uint32_t reserved_2; // offset: 2 (0x2)

sys/dev/pci/drm/amd/include/v10_structs.h

300

uint32_t reserved_272; // offset: 272 (0x110)

sys/dev/pci/drm/amd/include/v10_structs.h

301

uint32_t reserved_273; // offset: 273 (0x111)

sys/dev/pci/drm/amd/include/v10_structs.h

302

uint32_t reserved_274; // offset: 274 (0x112)

sys/dev/pci/drm/amd/include/v10_structs.h

303

uint32_t reserved_275; // offset: 275 (0x113)

sys/dev/pci/drm/amd/include/v10_structs.h

304

uint32_t vgt_dma_max_size; // offset: 276 (0x114)

sys/dev/pci/drm/amd/include/v10_structs.h

305

uint32_t vgt_dma_num_instances; // offset: 277 (0x115)

sys/dev/pci/drm/amd/include/v10_structs.h

306

uint32_t reserved_278; // offset: 278 (0x116)

sys/dev/pci/drm/amd/include/v10_structs.h

307

uint32_t reserved_279; // offset: 279 (0x117)

sys/dev/pci/drm/amd/include/v10_structs.h

308

uint32_t reserved_280; // offset: 280 (0x118)

sys/dev/pci/drm/amd/include/v10_structs.h

309

uint32_t reserved_281; // offset: 281 (0x119)

sys/dev/pci/drm/amd/include/v10_structs.h

31

uint32_t reserved_3; // offset: 3 (0x3)

sys/dev/pci/drm/amd/include/v10_structs.h

310

uint32_t reserved_282; // offset: 282 (0x11A)

sys/dev/pci/drm/amd/include/v10_structs.h

311

uint32_t reserved_283; // offset: 283 (0x11B)

sys/dev/pci/drm/amd/include/v10_structs.h

312

uint32_t reserved_284; // offset: 284 (0x11C)

sys/dev/pci/drm/amd/include/v10_structs.h

313

uint32_t reserved_285; // offset: 285 (0x11D)

sys/dev/pci/drm/amd/include/v10_structs.h

314

uint32_t reserved_286; // offset: 286 (0x11E)

sys/dev/pci/drm/amd/include/v10_structs.h

315

uint32_t reserved_287; // offset: 287 (0x11F)

sys/dev/pci/drm/amd/include/v10_structs.h

316

uint32_t it_set_base_ib_addr_lo; // offset: 288 (0x120)

sys/dev/pci/drm/amd/include/v10_structs.h

317

uint32_t it_set_base_ib_addr_hi; // offset: 289 (0x121)

sys/dev/pci/drm/amd/include/v10_structs.h

318

uint32_t reserved_290; // offset: 290 (0x122)

sys/dev/pci/drm/amd/include/v10_structs.h

319

uint32_t reserved_291; // offset: 291 (0x123)

sys/dev/pci/drm/amd/include/v10_structs.h

32

uint32_t reserved_4; // offset: 4 (0x4)

sys/dev/pci/drm/amd/include/v10_structs.h

320

uint32_t reserved_292; // offset: 292 (0x124)

sys/dev/pci/drm/amd/include/v10_structs.h

321

uint32_t reserved_293; // offset: 293 (0x125)

sys/dev/pci/drm/amd/include/v10_structs.h

322

uint32_t reserved_294; // offset: 294 (0x126)

sys/dev/pci/drm/amd/include/v10_structs.h

323

uint32_t reserved_295; // offset: 295 (0x127)

sys/dev/pci/drm/amd/include/v10_structs.h

324

uint32_t reserved_296; // offset: 296 (0x128)

sys/dev/pci/drm/amd/include/v10_structs.h

325

uint32_t reserved_297; // offset: 297 (0x129)

sys/dev/pci/drm/amd/include/v10_structs.h

326

uint32_t reserved_298; // offset: 298 (0x12A)

sys/dev/pci/drm/amd/include/v10_structs.h

327

uint32_t reserved_299; // offset: 299 (0x12B)

sys/dev/pci/drm/amd/include/v10_structs.h

328

uint32_t reserved_300; // offset: 300 (0x12C)

sys/dev/pci/drm/amd/include/v10_structs.h

329

uint32_t reserved_301; // offset: 301 (0x12D)

sys/dev/pci/drm/amd/include/v10_structs.h

33

uint32_t reserved_5; // offset: 5 (0x5)

sys/dev/pci/drm/amd/include/v10_structs.h

330

uint32_t reserved_302; // offset: 302 (0x12E)

sys/dev/pci/drm/amd/include/v10_structs.h

331

uint32_t reserved_303; // offset: 303 (0x12F)

sys/dev/pci/drm/amd/include/v10_structs.h

332

uint32_t reserved_304; // offset: 304 (0x130)

sys/dev/pci/drm/amd/include/v10_structs.h

333

uint32_t reserved_305; // offset: 305 (0x131)

sys/dev/pci/drm/amd/include/v10_structs.h

334

uint32_t reserved_306; // offset: 306 (0x132)

sys/dev/pci/drm/amd/include/v10_structs.h

335

uint32_t reserved_307; // offset: 307 (0x133)

sys/dev/pci/drm/amd/include/v10_structs.h

336

uint32_t reserved_308; // offset: 308 (0x134)

sys/dev/pci/drm/amd/include/v10_structs.h

337

uint32_t reserved_309; // offset: 309 (0x135)

sys/dev/pci/drm/amd/include/v10_structs.h

338

uint32_t reserved_310; // offset: 310 (0x136)

sys/dev/pci/drm/amd/include/v10_structs.h

339

uint32_t reserved_311; // offset: 311 (0x137)

sys/dev/pci/drm/amd/include/v10_structs.h

34

uint32_t reserved_6; // offset: 6 (0x6)

sys/dev/pci/drm/amd/include/v10_structs.h

340

uint32_t reserved_312; // offset: 312 (0x138)

sys/dev/pci/drm/amd/include/v10_structs.h

341

uint32_t reserved_313; // offset: 313 (0x139)

sys/dev/pci/drm/amd/include/v10_structs.h

342

uint32_t reserved_314; // offset: 314 (0x13A)

sys/dev/pci/drm/amd/include/v10_structs.h

343

uint32_t reserved_315; // offset: 315 (0x13B)

sys/dev/pci/drm/amd/include/v10_structs.h

344

uint32_t reserved_316; // offset: 316 (0x13C)

sys/dev/pci/drm/amd/include/v10_structs.h

345

uint32_t reserved_317; // offset: 317 (0x13D)

sys/dev/pci/drm/amd/include/v10_structs.h

346

uint32_t reserved_318; // offset: 318 (0x13E)

sys/dev/pci/drm/amd/include/v10_structs.h

347

uint32_t reserved_319; // offset: 319 (0x13F)

sys/dev/pci/drm/amd/include/v10_structs.h

348

uint32_t reserved_320; // offset: 320 (0x140)

sys/dev/pci/drm/amd/include/v10_structs.h

349

uint32_t reserved_321; // offset: 321 (0x141)

sys/dev/pci/drm/amd/include/v10_structs.h

35

uint32_t reserved_7; // offset: 7 (0x7)

sys/dev/pci/drm/amd/include/v10_structs.h

350

uint32_t reserved_322; // offset: 322 (0x142)

sys/dev/pci/drm/amd/include/v10_structs.h

351

uint32_t reserved_323; // offset: 323 (0x143)

sys/dev/pci/drm/amd/include/v10_structs.h

352

uint32_t reserved_324; // offset: 324 (0x144)

sys/dev/pci/drm/amd/include/v10_structs.h

353

uint32_t reserved_325; // offset: 325 (0x145)

sys/dev/pci/drm/amd/include/v10_structs.h

354

uint32_t reserved_326; // offset: 326 (0x146)

sys/dev/pci/drm/amd/include/v10_structs.h

355

uint32_t reserved_327; // offset: 327 (0x147)

sys/dev/pci/drm/amd/include/v10_structs.h

356

uint32_t reserved_328; // offset: 328 (0x148)

sys/dev/pci/drm/amd/include/v10_structs.h

357

uint32_t reserved_329; // offset: 329 (0x149)

sys/dev/pci/drm/amd/include/v10_structs.h

358

uint32_t reserved_330; // offset: 330 (0x14A)

sys/dev/pci/drm/amd/include/v10_structs.h

359

uint32_t reserved_331; // offset: 331 (0x14B)

sys/dev/pci/drm/amd/include/v10_structs.h

36

uint32_t reserved_8; // offset: 8 (0x8)

sys/dev/pci/drm/amd/include/v10_structs.h

360

uint32_t reserved_332; // offset: 332 (0x14C)

sys/dev/pci/drm/amd/include/v10_structs.h

361

uint32_t reserved_333; // offset: 333 (0x14D)

sys/dev/pci/drm/amd/include/v10_structs.h

362

uint32_t reserved_334; // offset: 334 (0x14E)

sys/dev/pci/drm/amd/include/v10_structs.h

363

uint32_t reserved_335; // offset: 335 (0x14F)

sys/dev/pci/drm/amd/include/v10_structs.h

364

uint32_t reserved_336; // offset: 336 (0x150)

sys/dev/pci/drm/amd/include/v10_structs.h

365

uint32_t reserved_337; // offset: 337 (0x151)

sys/dev/pci/drm/amd/include/v10_structs.h

366

uint32_t reserved_338; // offset: 338 (0x152)

sys/dev/pci/drm/amd/include/v10_structs.h

367

uint32_t reserved_339; // offset: 339 (0x153)

sys/dev/pci/drm/amd/include/v10_structs.h

368

uint32_t reserved_340; // offset: 340 (0x154)

sys/dev/pci/drm/amd/include/v10_structs.h

369

uint32_t reserved_341; // offset: 341 (0x155)

sys/dev/pci/drm/amd/include/v10_structs.h

37

uint32_t reserved_9; // offset: 9 (0x9)

sys/dev/pci/drm/amd/include/v10_structs.h

370

uint32_t reserved_342; // offset: 342 (0x156)

sys/dev/pci/drm/amd/include/v10_structs.h

371

uint32_t reserved_343; // offset: 343 (0x157)

sys/dev/pci/drm/amd/include/v10_structs.h

372

uint32_t reserved_344; // offset: 344 (0x158)

sys/dev/pci/drm/amd/include/v10_structs.h

373

uint32_t reserved_345; // offset: 345 (0x159)

sys/dev/pci/drm/amd/include/v10_structs.h

374

uint32_t reserved_346; // offset: 346 (0x15A)

sys/dev/pci/drm/amd/include/v10_structs.h

375

uint32_t reserved_347; // offset: 347 (0x15B)

sys/dev/pci/drm/amd/include/v10_structs.h

376

uint32_t reserved_348; // offset: 348 (0x15C)

sys/dev/pci/drm/amd/include/v10_structs.h

377

uint32_t reserved_349; // offset: 349 (0x15D)

sys/dev/pci/drm/amd/include/v10_structs.h

378

uint32_t reserved_350; // offset: 350 (0x15E)

sys/dev/pci/drm/amd/include/v10_structs.h

379

uint32_t reserved_351; // offset: 351 (0x15F)

sys/dev/pci/drm/amd/include/v10_structs.h

38

uint32_t reserved_10; // offset: 10 (0xA)

sys/dev/pci/drm/amd/include/v10_structs.h

380

uint32_t reserved_352; // offset: 352 (0x160)

sys/dev/pci/drm/amd/include/v10_structs.h

381

uint32_t reserved_353; // offset: 353 (0x161)

sys/dev/pci/drm/amd/include/v10_structs.h

382

uint32_t reserved_354; // offset: 354 (0x162)

sys/dev/pci/drm/amd/include/v10_structs.h

383

uint32_t reserved_355; // offset: 355 (0x163)

sys/dev/pci/drm/amd/include/v10_structs.h

384

uint32_t spi_shader_pgm_rsrc3_ps; // offset: 356 (0x164)

sys/dev/pci/drm/amd/include/v10_structs.h

385

uint32_t spi_shader_pgm_rsrc3_vs; // offset: 357 (0x165)

sys/dev/pci/drm/amd/include/v10_structs.h

386

uint32_t spi_shader_pgm_rsrc3_gs; // offset: 358 (0x166)

sys/dev/pci/drm/amd/include/v10_structs.h

387

uint32_t spi_shader_pgm_rsrc3_hs; // offset: 359 (0x167)

sys/dev/pci/drm/amd/include/v10_structs.h

388

uint32_t spi_shader_pgm_rsrc4_ps; // offset: 360 (0x168)

sys/dev/pci/drm/amd/include/v10_structs.h

389

uint32_t spi_shader_pgm_rsrc4_vs; // offset: 361 (0x169)

sys/dev/pci/drm/amd/include/v10_structs.h

39

uint32_t reserved_11; // offset: 11 (0xB)

sys/dev/pci/drm/amd/include/v10_structs.h

390

uint32_t spi_shader_pgm_rsrc4_gs; // offset: 362 (0x16A)

sys/dev/pci/drm/amd/include/v10_structs.h

391

uint32_t spi_shader_pgm_rsrc4_hs; // offset: 363 (0x16B)

sys/dev/pci/drm/amd/include/v10_structs.h

392

uint32_t db_occlusion_count0_low_00; // offset: 364 (0x16C)

sys/dev/pci/drm/amd/include/v10_structs.h

393

uint32_t db_occlusion_count0_hi_00; // offset: 365 (0x16D)

sys/dev/pci/drm/amd/include/v10_structs.h

394

uint32_t db_occlusion_count1_low_00; // offset: 366 (0x16E)

sys/dev/pci/drm/amd/include/v10_structs.h

395

uint32_t db_occlusion_count1_hi_00; // offset: 367 (0x16F)

sys/dev/pci/drm/amd/include/v10_structs.h

396

uint32_t db_occlusion_count2_low_00; // offset: 368 (0x170)

sys/dev/pci/drm/amd/include/v10_structs.h

397

uint32_t db_occlusion_count2_hi_00; // offset: 369 (0x171)

sys/dev/pci/drm/amd/include/v10_structs.h

398

uint32_t db_occlusion_count3_low_00; // offset: 370 (0x172)

sys/dev/pci/drm/amd/include/v10_structs.h

399

uint32_t db_occlusion_count3_hi_00; // offset: 371 (0x173)

sys/dev/pci/drm/amd/include/v10_structs.h

40

uint32_t reserved_12; // offset: 12 (0xC)

sys/dev/pci/drm/amd/include/v10_structs.h

400

uint32_t db_occlusion_count0_low_01; // offset: 372 (0x174)

sys/dev/pci/drm/amd/include/v10_structs.h

401

uint32_t db_occlusion_count0_hi_01; // offset: 373 (0x175)

sys/dev/pci/drm/amd/include/v10_structs.h

402

uint32_t db_occlusion_count1_low_01; // offset: 374 (0x176)

sys/dev/pci/drm/amd/include/v10_structs.h

403

uint32_t db_occlusion_count1_hi_01; // offset: 375 (0x177)

sys/dev/pci/drm/amd/include/v10_structs.h

404

uint32_t db_occlusion_count2_low_01; // offset: 376 (0x178)

sys/dev/pci/drm/amd/include/v10_structs.h

405

uint32_t db_occlusion_count2_hi_01; // offset: 377 (0x179)

sys/dev/pci/drm/amd/include/v10_structs.h

406

uint32_t db_occlusion_count3_low_01; // offset: 378 (0x17A)

sys/dev/pci/drm/amd/include/v10_structs.h

407

uint32_t db_occlusion_count3_hi_01; // offset: 379 (0x17B)

sys/dev/pci/drm/amd/include/v10_structs.h

408

uint32_t db_occlusion_count0_low_02; // offset: 380 (0x17C)

sys/dev/pci/drm/amd/include/v10_structs.h

409

uint32_t db_occlusion_count0_hi_02; // offset: 381 (0x17D)

sys/dev/pci/drm/amd/include/v10_structs.h

41

uint32_t reserved_13; // offset: 13 (0xD)

sys/dev/pci/drm/amd/include/v10_structs.h

410

uint32_t db_occlusion_count1_low_02; // offset: 382 (0x17E)

sys/dev/pci/drm/amd/include/v10_structs.h

411

uint32_t db_occlusion_count1_hi_02; // offset: 383 (0x17F)

sys/dev/pci/drm/amd/include/v10_structs.h

412

uint32_t db_occlusion_count2_low_02; // offset: 384 (0x180)

sys/dev/pci/drm/amd/include/v10_structs.h

413

uint32_t db_occlusion_count2_hi_02; // offset: 385 (0x181)

sys/dev/pci/drm/amd/include/v10_structs.h

414

uint32_t db_occlusion_count3_low_02; // offset: 386 (0x182)

sys/dev/pci/drm/amd/include/v10_structs.h

415

uint32_t db_occlusion_count3_hi_02; // offset: 387 (0x183)

sys/dev/pci/drm/amd/include/v10_structs.h

416

uint32_t db_occlusion_count0_low_03; // offset: 388 (0x184)

sys/dev/pci/drm/amd/include/v10_structs.h

417

uint32_t db_occlusion_count0_hi_03; // offset: 389 (0x185)

sys/dev/pci/drm/amd/include/v10_structs.h

418

uint32_t db_occlusion_count1_low_03; // offset: 390 (0x186)

sys/dev/pci/drm/amd/include/v10_structs.h

419

uint32_t db_occlusion_count1_hi_03; // offset: 391 (0x187)

sys/dev/pci/drm/amd/include/v10_structs.h

42

uint32_t reserved_14; // offset: 14 (0xE)

sys/dev/pci/drm/amd/include/v10_structs.h

420

uint32_t db_occlusion_count2_low_03; // offset: 392 (0x188)

sys/dev/pci/drm/amd/include/v10_structs.h

421

uint32_t db_occlusion_count2_hi_03; // offset: 393 (0x189)

sys/dev/pci/drm/amd/include/v10_structs.h

422

uint32_t db_occlusion_count3_low_03; // offset: 394 (0x18A)

sys/dev/pci/drm/amd/include/v10_structs.h

423

uint32_t db_occlusion_count3_hi_03; // offset: 395 (0x18B)

sys/dev/pci/drm/amd/include/v10_structs.h

424

uint32_t db_occlusion_count0_low_04; // offset: 396 (0x18C)

sys/dev/pci/drm/amd/include/v10_structs.h

425

uint32_t db_occlusion_count0_hi_04; // offset: 397 (0x18D)

sys/dev/pci/drm/amd/include/v10_structs.h

426

uint32_t db_occlusion_count1_low_04; // offset: 398 (0x18E)

sys/dev/pci/drm/amd/include/v10_structs.h

427

uint32_t db_occlusion_count1_hi_04; // offset: 399 (0x18F)

sys/dev/pci/drm/amd/include/v10_structs.h

428

uint32_t db_occlusion_count2_low_04; // offset: 400 (0x190)

sys/dev/pci/drm/amd/include/v10_structs.h

429

uint32_t db_occlusion_count2_hi_04; // offset: 401 (0x191)

sys/dev/pci/drm/amd/include/v10_structs.h

43

uint32_t reserved_15; // offset: 15 (0xF)

sys/dev/pci/drm/amd/include/v10_structs.h

430

uint32_t db_occlusion_count3_low_04; // offset: 402 (0x192)

sys/dev/pci/drm/amd/include/v10_structs.h

431

uint32_t db_occlusion_count3_hi_04; // offset: 403 (0x193)

sys/dev/pci/drm/amd/include/v10_structs.h

432

uint32_t db_occlusion_count0_low_05; // offset: 404 (0x194)

sys/dev/pci/drm/amd/include/v10_structs.h

433

uint32_t db_occlusion_count0_hi_05; // offset: 405 (0x195)

sys/dev/pci/drm/amd/include/v10_structs.h

434

uint32_t db_occlusion_count1_low_05; // offset: 406 (0x196)

sys/dev/pci/drm/amd/include/v10_structs.h

435

uint32_t db_occlusion_count1_hi_05; // offset: 407 (0x197)

sys/dev/pci/drm/amd/include/v10_structs.h

436

uint32_t db_occlusion_count2_low_05; // offset: 408 (0x198)

sys/dev/pci/drm/amd/include/v10_structs.h

437

uint32_t db_occlusion_count2_hi_05; // offset: 409 (0x199)

sys/dev/pci/drm/amd/include/v10_structs.h

438

uint32_t db_occlusion_count3_low_05; // offset: 410 (0x19A)

sys/dev/pci/drm/amd/include/v10_structs.h

439

uint32_t db_occlusion_count3_hi_05; // offset: 411 (0x19B)

sys/dev/pci/drm/amd/include/v10_structs.h

44

uint32_t reserved_16; // offset: 16 (0x10)

sys/dev/pci/drm/amd/include/v10_structs.h

440

uint32_t db_occlusion_count0_low_06; // offset: 412 (0x19C)

sys/dev/pci/drm/amd/include/v10_structs.h

441

uint32_t db_occlusion_count0_hi_06; // offset: 413 (0x19D)

sys/dev/pci/drm/amd/include/v10_structs.h

442

uint32_t db_occlusion_count1_low_06; // offset: 414 (0x19E)

sys/dev/pci/drm/amd/include/v10_structs.h

443

uint32_t db_occlusion_count1_hi_06; // offset: 415 (0x19F)

sys/dev/pci/drm/amd/include/v10_structs.h

444

uint32_t db_occlusion_count2_low_06; // offset: 416 (0x1A0)

sys/dev/pci/drm/amd/include/v10_structs.h

445

uint32_t db_occlusion_count2_hi_06; // offset: 417 (0x1A1)

sys/dev/pci/drm/amd/include/v10_structs.h

446

uint32_t db_occlusion_count3_low_06; // offset: 418 (0x1A2)

sys/dev/pci/drm/amd/include/v10_structs.h

447

uint32_t db_occlusion_count3_hi_06; // offset: 419 (0x1A3)

sys/dev/pci/drm/amd/include/v10_structs.h

448

uint32_t db_occlusion_count0_low_07; // offset: 420 (0x1A4)

sys/dev/pci/drm/amd/include/v10_structs.h

449

uint32_t db_occlusion_count0_hi_07; // offset: 421 (0x1A5)

sys/dev/pci/drm/amd/include/v10_structs.h

45

uint32_t reserved_17; // offset: 17 (0x11)

sys/dev/pci/drm/amd/include/v10_structs.h

450

uint32_t db_occlusion_count1_low_07; // offset: 422 (0x1A6)

sys/dev/pci/drm/amd/include/v10_structs.h

451

uint32_t db_occlusion_count1_hi_07; // offset: 423 (0x1A7)

sys/dev/pci/drm/amd/include/v10_structs.h

452

uint32_t db_occlusion_count2_low_07; // offset: 424 (0x1A8)

sys/dev/pci/drm/amd/include/v10_structs.h

453

uint32_t db_occlusion_count2_hi_07; // offset: 425 (0x1A9)

sys/dev/pci/drm/amd/include/v10_structs.h

454

uint32_t db_occlusion_count3_low_07; // offset: 426 (0x1AA)

sys/dev/pci/drm/amd/include/v10_structs.h

455

uint32_t db_occlusion_count3_hi_07; // offset: 427 (0x1AB)

sys/dev/pci/drm/amd/include/v10_structs.h

456

uint32_t db_occlusion_count0_low_10; // offset: 428 (0x1AC)

sys/dev/pci/drm/amd/include/v10_structs.h

457

uint32_t db_occlusion_count0_hi_10; // offset: 429 (0x1AD)

sys/dev/pci/drm/amd/include/v10_structs.h

458

uint32_t db_occlusion_count1_low_10; // offset: 430 (0x1AE)

sys/dev/pci/drm/amd/include/v10_structs.h

459

uint32_t db_occlusion_count1_hi_10; // offset: 431 (0x1AF)

sys/dev/pci/drm/amd/include/v10_structs.h

46

uint32_t reserved_18; // offset: 18 (0x12)

sys/dev/pci/drm/amd/include/v10_structs.h

460

uint32_t db_occlusion_count2_low_10; // offset: 432 (0x1B0)

sys/dev/pci/drm/amd/include/v10_structs.h

461

uint32_t db_occlusion_count2_hi_10; // offset: 433 (0x1B1)

sys/dev/pci/drm/amd/include/v10_structs.h

462

uint32_t db_occlusion_count3_low_10; // offset: 434 (0x1B2)

sys/dev/pci/drm/amd/include/v10_structs.h

463

uint32_t db_occlusion_count3_hi_10; // offset: 435 (0x1B3)

sys/dev/pci/drm/amd/include/v10_structs.h

464

uint32_t db_occlusion_count0_low_11; // offset: 436 (0x1B4)

sys/dev/pci/drm/amd/include/v10_structs.h

465

uint32_t db_occlusion_count0_hi_11; // offset: 437 (0x1B5)

sys/dev/pci/drm/amd/include/v10_structs.h

466

uint32_t db_occlusion_count1_low_11; // offset: 438 (0x1B6)

sys/dev/pci/drm/amd/include/v10_structs.h

467

uint32_t db_occlusion_count1_hi_11; // offset: 439 (0x1B7)

sys/dev/pci/drm/amd/include/v10_structs.h

468

uint32_t db_occlusion_count2_low_11; // offset: 440 (0x1B8)

sys/dev/pci/drm/amd/include/v10_structs.h

469

uint32_t db_occlusion_count2_hi_11; // offset: 441 (0x1B9)

sys/dev/pci/drm/amd/include/v10_structs.h

47

uint32_t reserved_19; // offset: 19 (0x13)

sys/dev/pci/drm/amd/include/v10_structs.h

470

uint32_t db_occlusion_count3_low_11; // offset: 442 (0x1BA)

sys/dev/pci/drm/amd/include/v10_structs.h

471

uint32_t db_occlusion_count3_hi_11; // offset: 443 (0x1BB)

sys/dev/pci/drm/amd/include/v10_structs.h

472

uint32_t db_occlusion_count0_low_12; // offset: 444 (0x1BC)

sys/dev/pci/drm/amd/include/v10_structs.h

473

uint32_t db_occlusion_count0_hi_12; // offset: 445 (0x1BD)

sys/dev/pci/drm/amd/include/v10_structs.h

474

uint32_t db_occlusion_count1_low_12; // offset: 446 (0x1BE)

sys/dev/pci/drm/amd/include/v10_structs.h

475

uint32_t db_occlusion_count1_hi_12; // offset: 447 (0x1BF)

sys/dev/pci/drm/amd/include/v10_structs.h

476

uint32_t db_occlusion_count2_low_12; // offset: 448 (0x1C0)

sys/dev/pci/drm/amd/include/v10_structs.h

477

uint32_t db_occlusion_count2_hi_12; // offset: 449 (0x1C1)

sys/dev/pci/drm/amd/include/v10_structs.h

478

uint32_t db_occlusion_count3_low_12; // offset: 450 (0x1C2)

sys/dev/pci/drm/amd/include/v10_structs.h

479

uint32_t db_occlusion_count3_hi_12; // offset: 451 (0x1C3)

sys/dev/pci/drm/amd/include/v10_structs.h

48

uint32_t reserved_20; // offset: 20 (0x14)

sys/dev/pci/drm/amd/include/v10_structs.h

480

uint32_t db_occlusion_count0_low_13; // offset: 452 (0x1C4)

sys/dev/pci/drm/amd/include/v10_structs.h

481

uint32_t db_occlusion_count0_hi_13; // offset: 453 (0x1C5)

sys/dev/pci/drm/amd/include/v10_structs.h

482

uint32_t db_occlusion_count1_low_13; // offset: 454 (0x1C6)

sys/dev/pci/drm/amd/include/v10_structs.h

483

uint32_t db_occlusion_count1_hi_13; // offset: 455 (0x1C7)

sys/dev/pci/drm/amd/include/v10_structs.h

484

uint32_t db_occlusion_count2_low_13; // offset: 456 (0x1C8)

sys/dev/pci/drm/amd/include/v10_structs.h

485

uint32_t db_occlusion_count2_hi_13; // offset: 457 (0x1C9)

sys/dev/pci/drm/amd/include/v10_structs.h

486

uint32_t db_occlusion_count3_low_13; // offset: 458 (0x1CA)

sys/dev/pci/drm/amd/include/v10_structs.h

487

uint32_t db_occlusion_count3_hi_13; // offset: 459 (0x1CB)

sys/dev/pci/drm/amd/include/v10_structs.h

488

uint32_t db_occlusion_count0_low_14; // offset: 460 (0x1CC)

sys/dev/pci/drm/amd/include/v10_structs.h

489

uint32_t db_occlusion_count0_hi_14; // offset: 461 (0x1CD)

sys/dev/pci/drm/amd/include/v10_structs.h

49

uint32_t reserved_21; // offset: 21 (0x15)

sys/dev/pci/drm/amd/include/v10_structs.h

490

uint32_t db_occlusion_count1_low_14; // offset: 462 (0x1CE)

sys/dev/pci/drm/amd/include/v10_structs.h

491

uint32_t db_occlusion_count1_hi_14; // offset: 463 (0x1CF)

sys/dev/pci/drm/amd/include/v10_structs.h

492

uint32_t db_occlusion_count2_low_14; // offset: 464 (0x1D0)

sys/dev/pci/drm/amd/include/v10_structs.h

493

uint32_t db_occlusion_count2_hi_14; // offset: 465 (0x1D1)

sys/dev/pci/drm/amd/include/v10_structs.h

494

uint32_t db_occlusion_count3_low_14; // offset: 466 (0x1D2)

sys/dev/pci/drm/amd/include/v10_structs.h

495

uint32_t db_occlusion_count3_hi_14; // offset: 467 (0x1D3)

sys/dev/pci/drm/amd/include/v10_structs.h

496

uint32_t db_occlusion_count0_low_15; // offset: 468 (0x1D4)

sys/dev/pci/drm/amd/include/v10_structs.h

497

uint32_t db_occlusion_count0_hi_15; // offset: 469 (0x1D5)

sys/dev/pci/drm/amd/include/v10_structs.h

498

uint32_t db_occlusion_count1_low_15; // offset: 470 (0x1D6)

sys/dev/pci/drm/amd/include/v10_structs.h

499

uint32_t db_occlusion_count1_hi_15; // offset: 471 (0x1D7)

sys/dev/pci/drm/amd/include/v10_structs.h

50

uint32_t reserved_22; // offset: 22 (0x16)

sys/dev/pci/drm/amd/include/v10_structs.h

500

uint32_t db_occlusion_count2_low_15; // offset: 472 (0x1D8)

sys/dev/pci/drm/amd/include/v10_structs.h

501

uint32_t db_occlusion_count2_hi_15; // offset: 473 (0x1D9)

sys/dev/pci/drm/amd/include/v10_structs.h

502

uint32_t db_occlusion_count3_low_15; // offset: 474 (0x1DA)

sys/dev/pci/drm/amd/include/v10_structs.h

503

uint32_t db_occlusion_count3_hi_15; // offset: 475 (0x1DB)

sys/dev/pci/drm/amd/include/v10_structs.h

504

uint32_t db_occlusion_count0_low_16; // offset: 476 (0x1DC)

sys/dev/pci/drm/amd/include/v10_structs.h

505

uint32_t db_occlusion_count0_hi_16; // offset: 477 (0x1DD)

sys/dev/pci/drm/amd/include/v10_structs.h

506

uint32_t db_occlusion_count1_low_16; // offset: 478 (0x1DE)

sys/dev/pci/drm/amd/include/v10_structs.h

507

uint32_t db_occlusion_count1_hi_16; // offset: 479 (0x1DF)

sys/dev/pci/drm/amd/include/v10_structs.h

508

uint32_t db_occlusion_count2_low_16; // offset: 480 (0x1E0)

sys/dev/pci/drm/amd/include/v10_structs.h

509

uint32_t db_occlusion_count2_hi_16; // offset: 481 (0x1E1)

sys/dev/pci/drm/amd/include/v10_structs.h

51

uint32_t reserved_23; // offset: 23 (0x17)

sys/dev/pci/drm/amd/include/v10_structs.h

510

uint32_t db_occlusion_count3_low_16; // offset: 482 (0x1E2)

sys/dev/pci/drm/amd/include/v10_structs.h

511

uint32_t db_occlusion_count3_hi_16; // offset: 483 (0x1E3)

sys/dev/pci/drm/amd/include/v10_structs.h

512

uint32_t db_occlusion_count0_low_17; // offset: 484 (0x1E4)

sys/dev/pci/drm/amd/include/v10_structs.h

513

uint32_t db_occlusion_count0_hi_17; // offset: 485 (0x1E5)

sys/dev/pci/drm/amd/include/v10_structs.h

514

uint32_t db_occlusion_count1_low_17; // offset: 486 (0x1E6)

sys/dev/pci/drm/amd/include/v10_structs.h

515

uint32_t db_occlusion_count1_hi_17; // offset: 487 (0x1E7)

sys/dev/pci/drm/amd/include/v10_structs.h

516

uint32_t db_occlusion_count2_low_17; // offset: 488 (0x1E8)

sys/dev/pci/drm/amd/include/v10_structs.h

517

uint32_t db_occlusion_count2_hi_17; // offset: 489 (0x1E9)

sys/dev/pci/drm/amd/include/v10_structs.h

518

uint32_t db_occlusion_count3_low_17; // offset: 490 (0x1EA)

sys/dev/pci/drm/amd/include/v10_structs.h

519

uint32_t db_occlusion_count3_hi_17; // offset: 491 (0x1EB)

sys/dev/pci/drm/amd/include/v10_structs.h

52

uint32_t reserved_24; // offset: 24 (0x18)

sys/dev/pci/drm/amd/include/v10_structs.h

520

uint32_t reserved_492; // offset: 492 (0x1EC)

sys/dev/pci/drm/amd/include/v10_structs.h

521

uint32_t reserved_493; // offset: 493 (0x1ED)

sys/dev/pci/drm/amd/include/v10_structs.h

522

uint32_t reserved_494; // offset: 494 (0x1EE)

sys/dev/pci/drm/amd/include/v10_structs.h

523

uint32_t reserved_495; // offset: 495 (0x1EF)

sys/dev/pci/drm/amd/include/v10_structs.h

524

uint32_t reserved_496; // offset: 496 (0x1F0)

sys/dev/pci/drm/amd/include/v10_structs.h

525

uint32_t reserved_497; // offset: 497 (0x1F1)

sys/dev/pci/drm/amd/include/v10_structs.h

526

uint32_t reserved_498; // offset: 498 (0x1F2)

sys/dev/pci/drm/amd/include/v10_structs.h

527

uint32_t reserved_499; // offset: 499 (0x1F3)

sys/dev/pci/drm/amd/include/v10_structs.h

528

uint32_t reserved_500; // offset: 500 (0x1F4)

sys/dev/pci/drm/amd/include/v10_structs.h

529

uint32_t reserved_501; // offset: 501 (0x1F5)

sys/dev/pci/drm/amd/include/v10_structs.h

53

uint32_t reserved_25; // offset: 25 (0x19)

sys/dev/pci/drm/amd/include/v10_structs.h

530

uint32_t reserved_502; // offset: 502 (0x1F6)

sys/dev/pci/drm/amd/include/v10_structs.h

531

uint32_t reserved_503; // offset: 503 (0x1F7)

sys/dev/pci/drm/amd/include/v10_structs.h

532

uint32_t reserved_504; // offset: 504 (0x1F8)

sys/dev/pci/drm/amd/include/v10_structs.h

533

uint32_t reserved_505; // offset: 505 (0x1F9)

sys/dev/pci/drm/amd/include/v10_structs.h

534

uint32_t reserved_506; // offset: 506 (0x1FA)

sys/dev/pci/drm/amd/include/v10_structs.h

535

uint32_t reserved_507; // offset: 507 (0x1FB)

sys/dev/pci/drm/amd/include/v10_structs.h

536

uint32_t reserved_508; // offset: 508 (0x1FC)

sys/dev/pci/drm/amd/include/v10_structs.h

537

uint32_t reserved_509; // offset: 509 (0x1FD)

sys/dev/pci/drm/amd/include/v10_structs.h

538

uint32_t reserved_510; // offset: 510 (0x1FE)

sys/dev/pci/drm/amd/include/v10_structs.h

539

uint32_t reserved_511; // offset: 511 (0x1FF)

sys/dev/pci/drm/amd/include/v10_structs.h

54

uint32_t reserved_26; // offset: 26 (0x1A)

sys/dev/pci/drm/amd/include/v10_structs.h

543

uint32_t sdmax_rlcx_rb_cntl;

sys/dev/pci/drm/amd/include/v10_structs.h

544

uint32_t sdmax_rlcx_rb_base;

sys/dev/pci/drm/amd/include/v10_structs.h

545

uint32_t sdmax_rlcx_rb_base_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

546

uint32_t sdmax_rlcx_rb_rptr;

sys/dev/pci/drm/amd/include/v10_structs.h

547

uint32_t sdmax_rlcx_rb_rptr_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

548

uint32_t sdmax_rlcx_rb_wptr;

sys/dev/pci/drm/amd/include/v10_structs.h

549

uint32_t sdmax_rlcx_rb_wptr_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

55

uint32_t reserved_27; // offset: 27 (0x1B)

sys/dev/pci/drm/amd/include/v10_structs.h

550

uint32_t sdmax_rlcx_rb_wptr_poll_cntl;

sys/dev/pci/drm/amd/include/v10_structs.h

551

uint32_t sdmax_rlcx_rb_rptr_addr_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

552

uint32_t sdmax_rlcx_rb_rptr_addr_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

553

uint32_t sdmax_rlcx_ib_cntl;

sys/dev/pci/drm/amd/include/v10_structs.h

554

uint32_t sdmax_rlcx_ib_rptr;

sys/dev/pci/drm/amd/include/v10_structs.h

555

uint32_t sdmax_rlcx_ib_offset;

sys/dev/pci/drm/amd/include/v10_structs.h

556

uint32_t sdmax_rlcx_ib_base_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

557

uint32_t sdmax_rlcx_ib_base_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

558

uint32_t sdmax_rlcx_ib_size;

sys/dev/pci/drm/amd/include/v10_structs.h

559

uint32_t sdmax_rlcx_skip_cntl;

sys/dev/pci/drm/amd/include/v10_structs.h

56

uint32_t reserved_28; // offset: 28 (0x1C)

sys/dev/pci/drm/amd/include/v10_structs.h

560

uint32_t sdmax_rlcx_context_status;

sys/dev/pci/drm/amd/include/v10_structs.h

561

uint32_t sdmax_rlcx_doorbell;

sys/dev/pci/drm/amd/include/v10_structs.h

562

uint32_t sdmax_rlcx_status;

sys/dev/pci/drm/amd/include/v10_structs.h

563

uint32_t sdmax_rlcx_doorbell_log;

sys/dev/pci/drm/amd/include/v10_structs.h

564

uint32_t sdmax_rlcx_watermark;

sys/dev/pci/drm/amd/include/v10_structs.h

565

uint32_t sdmax_rlcx_doorbell_offset;

sys/dev/pci/drm/amd/include/v10_structs.h

566

uint32_t sdmax_rlcx_csa_addr_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

567

uint32_t sdmax_rlcx_csa_addr_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

568

uint32_t sdmax_rlcx_ib_sub_remain;

sys/dev/pci/drm/amd/include/v10_structs.h

569

uint32_t sdmax_rlcx_preempt;

sys/dev/pci/drm/amd/include/v10_structs.h

57

uint32_t reserved_29; // offset: 29 (0x1D)

sys/dev/pci/drm/amd/include/v10_structs.h

570

uint32_t sdmax_rlcx_dummy_reg;

sys/dev/pci/drm/amd/include/v10_structs.h

571

uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

572

uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

573

uint32_t sdmax_rlcx_rb_aql_cntl;

sys/dev/pci/drm/amd/include/v10_structs.h

574

uint32_t sdmax_rlcx_minor_ptr_update;

sys/dev/pci/drm/amd/include/v10_structs.h

575

uint32_t sdmax_rlcx_midcmd_data0;

sys/dev/pci/drm/amd/include/v10_structs.h

576

uint32_t sdmax_rlcx_midcmd_data1;

sys/dev/pci/drm/amd/include/v10_structs.h

577

uint32_t sdmax_rlcx_midcmd_data2;

sys/dev/pci/drm/amd/include/v10_structs.h

578

uint32_t sdmax_rlcx_midcmd_data3;

sys/dev/pci/drm/amd/include/v10_structs.h

579

uint32_t sdmax_rlcx_midcmd_data4;

sys/dev/pci/drm/amd/include/v10_structs.h

58

uint32_t reserved_30; // offset: 30 (0x1E)

sys/dev/pci/drm/amd/include/v10_structs.h

580

uint32_t sdmax_rlcx_midcmd_data5;

sys/dev/pci/drm/amd/include/v10_structs.h

581

uint32_t sdmax_rlcx_midcmd_data6;

sys/dev/pci/drm/amd/include/v10_structs.h

582

uint32_t sdmax_rlcx_midcmd_data7;

sys/dev/pci/drm/amd/include/v10_structs.h

583

uint32_t sdmax_rlcx_midcmd_data8;

sys/dev/pci/drm/amd/include/v10_structs.h

584

uint32_t sdmax_rlcx_midcmd_cntl;

sys/dev/pci/drm/amd/include/v10_structs.h

585

uint32_t reserved_42;

sys/dev/pci/drm/amd/include/v10_structs.h

586

uint32_t reserved_43;

sys/dev/pci/drm/amd/include/v10_structs.h

587

uint32_t reserved_44;

sys/dev/pci/drm/amd/include/v10_structs.h

588

uint32_t reserved_45;

sys/dev/pci/drm/amd/include/v10_structs.h

589

uint32_t reserved_46;

sys/dev/pci/drm/amd/include/v10_structs.h

59

uint32_t reserved_31; // offset: 31 (0x1F)

sys/dev/pci/drm/amd/include/v10_structs.h

590

uint32_t reserved_47;

sys/dev/pci/drm/amd/include/v10_structs.h

591

uint32_t reserved_48;

sys/dev/pci/drm/amd/include/v10_structs.h

592

uint32_t reserved_49;

sys/dev/pci/drm/amd/include/v10_structs.h

593

uint32_t reserved_50;

sys/dev/pci/drm/amd/include/v10_structs.h

594

uint32_t reserved_51;

sys/dev/pci/drm/amd/include/v10_structs.h

595

uint32_t reserved_52;

sys/dev/pci/drm/amd/include/v10_structs.h

596

uint32_t reserved_53;

sys/dev/pci/drm/amd/include/v10_structs.h

597

uint32_t reserved_54;

sys/dev/pci/drm/amd/include/v10_structs.h

598

uint32_t reserved_55;

sys/dev/pci/drm/amd/include/v10_structs.h

599

uint32_t reserved_56;

sys/dev/pci/drm/amd/include/v10_structs.h

60

uint32_t reserved_32; // offset: 32 (0x20)

sys/dev/pci/drm/amd/include/v10_structs.h

600

uint32_t reserved_57;

sys/dev/pci/drm/amd/include/v10_structs.h

601

uint32_t reserved_58;

sys/dev/pci/drm/amd/include/v10_structs.h

602

uint32_t reserved_59;

sys/dev/pci/drm/amd/include/v10_structs.h

603

uint32_t reserved_60;

sys/dev/pci/drm/amd/include/v10_structs.h

604

uint32_t reserved_61;

sys/dev/pci/drm/amd/include/v10_structs.h

605

uint32_t reserved_62;

sys/dev/pci/drm/amd/include/v10_structs.h

606

uint32_t reserved_63;

sys/dev/pci/drm/amd/include/v10_structs.h

607

uint32_t reserved_64;

sys/dev/pci/drm/amd/include/v10_structs.h

608

uint32_t reserved_65;

sys/dev/pci/drm/amd/include/v10_structs.h

609

uint32_t reserved_66;

sys/dev/pci/drm/amd/include/v10_structs.h

61

uint32_t reserved_33; // offset: 33 (0x21)

sys/dev/pci/drm/amd/include/v10_structs.h

610

uint32_t reserved_67;

sys/dev/pci/drm/amd/include/v10_structs.h

611

uint32_t reserved_68;

sys/dev/pci/drm/amd/include/v10_structs.h

612

uint32_t reserved_69;

sys/dev/pci/drm/amd/include/v10_structs.h

613

uint32_t reserved_70;

sys/dev/pci/drm/amd/include/v10_structs.h

614

uint32_t reserved_71;

sys/dev/pci/drm/amd/include/v10_structs.h

615

uint32_t reserved_72;

sys/dev/pci/drm/amd/include/v10_structs.h

616

uint32_t reserved_73;

sys/dev/pci/drm/amd/include/v10_structs.h

617

uint32_t reserved_74;

sys/dev/pci/drm/amd/include/v10_structs.h

618

uint32_t reserved_75;

sys/dev/pci/drm/amd/include/v10_structs.h

619

uint32_t reserved_76;

sys/dev/pci/drm/amd/include/v10_structs.h

62

uint32_t reserved_34; // offset: 34 (0x22)

sys/dev/pci/drm/amd/include/v10_structs.h

620

uint32_t reserved_77;

sys/dev/pci/drm/amd/include/v10_structs.h

621

uint32_t reserved_78;

sys/dev/pci/drm/amd/include/v10_structs.h

622

uint32_t reserved_79;

sys/dev/pci/drm/amd/include/v10_structs.h

623

uint32_t reserved_80;

sys/dev/pci/drm/amd/include/v10_structs.h

624

uint32_t reserved_81;

sys/dev/pci/drm/amd/include/v10_structs.h

625

uint32_t reserved_82;

sys/dev/pci/drm/amd/include/v10_structs.h

626

uint32_t reserved_83;

sys/dev/pci/drm/amd/include/v10_structs.h

627

uint32_t reserved_84;

sys/dev/pci/drm/amd/include/v10_structs.h

628

uint32_t reserved_85;

sys/dev/pci/drm/amd/include/v10_structs.h

629

uint32_t reserved_86;

sys/dev/pci/drm/amd/include/v10_structs.h

63

uint32_t reserved_35; // offset: 35 (0x23)

sys/dev/pci/drm/amd/include/v10_structs.h

630

uint32_t reserved_87;

sys/dev/pci/drm/amd/include/v10_structs.h

631

uint32_t reserved_88;

sys/dev/pci/drm/amd/include/v10_structs.h

632

uint32_t reserved_89;

sys/dev/pci/drm/amd/include/v10_structs.h

633

uint32_t reserved_90;

sys/dev/pci/drm/amd/include/v10_structs.h

634

uint32_t reserved_91;

sys/dev/pci/drm/amd/include/v10_structs.h

635

uint32_t reserved_92;

sys/dev/pci/drm/amd/include/v10_structs.h

636

uint32_t reserved_93;

sys/dev/pci/drm/amd/include/v10_structs.h

637

uint32_t reserved_94;

sys/dev/pci/drm/amd/include/v10_structs.h

638

uint32_t reserved_95;

sys/dev/pci/drm/amd/include/v10_structs.h

639

uint32_t reserved_96;

sys/dev/pci/drm/amd/include/v10_structs.h

64

uint32_t reserved_36; // offset: 36 (0x24)

sys/dev/pci/drm/amd/include/v10_structs.h

640

uint32_t reserved_97;

sys/dev/pci/drm/amd/include/v10_structs.h

641

uint32_t reserved_98;

sys/dev/pci/drm/amd/include/v10_structs.h

642

uint32_t reserved_99;

sys/dev/pci/drm/amd/include/v10_structs.h

643

uint32_t reserved_100;

sys/dev/pci/drm/amd/include/v10_structs.h

644

uint32_t reserved_101;

sys/dev/pci/drm/amd/include/v10_structs.h

645

uint32_t reserved_102;

sys/dev/pci/drm/amd/include/v10_structs.h

646

uint32_t reserved_103;

sys/dev/pci/drm/amd/include/v10_structs.h

647

uint32_t reserved_104;

sys/dev/pci/drm/amd/include/v10_structs.h

648

uint32_t reserved_105;

sys/dev/pci/drm/amd/include/v10_structs.h

649

uint32_t reserved_106;

sys/dev/pci/drm/amd/include/v10_structs.h

65

uint32_t reserved_37; // offset: 37 (0x25)

sys/dev/pci/drm/amd/include/v10_structs.h

650

uint32_t reserved_107;

sys/dev/pci/drm/amd/include/v10_structs.h

651

uint32_t reserved_108;

sys/dev/pci/drm/amd/include/v10_structs.h

652

uint32_t reserved_109;

sys/dev/pci/drm/amd/include/v10_structs.h

653

uint32_t reserved_110;

sys/dev/pci/drm/amd/include/v10_structs.h

654

uint32_t reserved_111;

sys/dev/pci/drm/amd/include/v10_structs.h

655

uint32_t reserved_112;

sys/dev/pci/drm/amd/include/v10_structs.h

656

uint32_t reserved_113;

sys/dev/pci/drm/amd/include/v10_structs.h

657

uint32_t reserved_114;

sys/dev/pci/drm/amd/include/v10_structs.h

658

uint32_t reserved_115;

sys/dev/pci/drm/amd/include/v10_structs.h

659

uint32_t reserved_116;

sys/dev/pci/drm/amd/include/v10_structs.h

66

uint32_t reserved_38; // offset: 38 (0x26)

sys/dev/pci/drm/amd/include/v10_structs.h

660

uint32_t reserved_117;

sys/dev/pci/drm/amd/include/v10_structs.h

661

uint32_t reserved_118;

sys/dev/pci/drm/amd/include/v10_structs.h

662

uint32_t reserved_119;

sys/dev/pci/drm/amd/include/v10_structs.h

663

uint32_t reserved_120;

sys/dev/pci/drm/amd/include/v10_structs.h

664

uint32_t reserved_121;

sys/dev/pci/drm/amd/include/v10_structs.h

665

uint32_t reserved_122;

sys/dev/pci/drm/amd/include/v10_structs.h

666

uint32_t reserved_123;

sys/dev/pci/drm/amd/include/v10_structs.h

667

uint32_t reserved_124;

sys/dev/pci/drm/amd/include/v10_structs.h

668

uint32_t reserved_125;

sys/dev/pci/drm/amd/include/v10_structs.h

669

uint32_t reserved_126;

sys/dev/pci/drm/amd/include/v10_structs.h

67

uint32_t reserved_39; // offset: 39 (0x27)

sys/dev/pci/drm/amd/include/v10_structs.h

670

uint32_t reserved_127;

sys/dev/pci/drm/amd/include/v10_structs.h

671

uint32_t sdma_engine_id;

sys/dev/pci/drm/amd/include/v10_structs.h

672

uint32_t sdma_queue_id;

sys/dev/pci/drm/amd/include/v10_structs.h

676

uint32_t header;

sys/dev/pci/drm/amd/include/v10_structs.h

677

uint32_t compute_dispatch_initiator;

sys/dev/pci/drm/amd/include/v10_structs.h

678

uint32_t compute_dim_x;

sys/dev/pci/drm/amd/include/v10_structs.h

679

uint32_t compute_dim_y;

sys/dev/pci/drm/amd/include/v10_structs.h

68

uint32_t reserved_40; // offset: 40 (0x28)

sys/dev/pci/drm/amd/include/v10_structs.h

680

uint32_t compute_dim_z;

sys/dev/pci/drm/amd/include/v10_structs.h

681

uint32_t compute_start_x;

sys/dev/pci/drm/amd/include/v10_structs.h

682

uint32_t compute_start_y;

sys/dev/pci/drm/amd/include/v10_structs.h

683

uint32_t compute_start_z;

sys/dev/pci/drm/amd/include/v10_structs.h

684

uint32_t compute_num_thread_x;

sys/dev/pci/drm/amd/include/v10_structs.h

685

uint32_t compute_num_thread_y;

sys/dev/pci/drm/amd/include/v10_structs.h

686

uint32_t compute_num_thread_z;

sys/dev/pci/drm/amd/include/v10_structs.h

687

uint32_t compute_pipelinestat_enable;

sys/dev/pci/drm/amd/include/v10_structs.h

688

uint32_t compute_perfcount_enable;

sys/dev/pci/drm/amd/include/v10_structs.h

689

uint32_t compute_pgm_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

69

uint32_t reserved_41; // offset: 41 (0x29)

sys/dev/pci/drm/amd/include/v10_structs.h

690

uint32_t compute_pgm_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

691

uint32_t compute_tba_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

692

uint32_t compute_tba_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

693

uint32_t compute_tma_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

694

uint32_t compute_tma_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

695

uint32_t compute_pgm_rsrc1;

sys/dev/pci/drm/amd/include/v10_structs.h

696

uint32_t compute_pgm_rsrc2;

sys/dev/pci/drm/amd/include/v10_structs.h

697

uint32_t compute_vmid;

sys/dev/pci/drm/amd/include/v10_structs.h

698

uint32_t compute_resource_limits;

sys/dev/pci/drm/amd/include/v10_structs.h

699

uint32_t compute_static_thread_mgmt_se0;

sys/dev/pci/drm/amd/include/v10_structs.h

70

uint32_t reserved_42; // offset: 42 (0x2A)

sys/dev/pci/drm/amd/include/v10_structs.h

700

uint32_t compute_static_thread_mgmt_se1;

sys/dev/pci/drm/amd/include/v10_structs.h

701

uint32_t compute_tmpring_size;

sys/dev/pci/drm/amd/include/v10_structs.h

702

uint32_t compute_static_thread_mgmt_se2;

sys/dev/pci/drm/amd/include/v10_structs.h

703

uint32_t compute_static_thread_mgmt_se3;

sys/dev/pci/drm/amd/include/v10_structs.h

704

uint32_t compute_restart_x;

sys/dev/pci/drm/amd/include/v10_structs.h

705

uint32_t compute_restart_y;

sys/dev/pci/drm/amd/include/v10_structs.h

706

uint32_t compute_restart_z;

sys/dev/pci/drm/amd/include/v10_structs.h

707

uint32_t compute_thread_trace_enable;

sys/dev/pci/drm/amd/include/v10_structs.h

708

uint32_t compute_misc_reserved;

sys/dev/pci/drm/amd/include/v10_structs.h

709

uint32_t compute_dispatch_id;

sys/dev/pci/drm/amd/include/v10_structs.h

71

uint32_t reserved_43; // offset: 43 (0x2B)

sys/dev/pci/drm/amd/include/v10_structs.h

710

uint32_t compute_threadgroup_id;

sys/dev/pci/drm/amd/include/v10_structs.h

711

uint32_t compute_relaunch;

sys/dev/pci/drm/amd/include/v10_structs.h

712

uint32_t compute_wave_restore_addr_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

713

uint32_t compute_wave_restore_addr_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

714

uint32_t compute_wave_restore_control;

sys/dev/pci/drm/amd/include/v10_structs.h

715

uint32_t reserved_39;

sys/dev/pci/drm/amd/include/v10_structs.h

716

uint32_t reserved_40;

sys/dev/pci/drm/amd/include/v10_structs.h

717

uint32_t reserved_41;

sys/dev/pci/drm/amd/include/v10_structs.h

718

uint32_t reserved_42;

sys/dev/pci/drm/amd/include/v10_structs.h

719

uint32_t reserved_43;

sys/dev/pci/drm/amd/include/v10_structs.h

72

uint32_t reserved_44; // offset: 44 (0x2C)

sys/dev/pci/drm/amd/include/v10_structs.h

720

uint32_t reserved_44;

sys/dev/pci/drm/amd/include/v10_structs.h

721

uint32_t reserved_45;

sys/dev/pci/drm/amd/include/v10_structs.h

722

uint32_t reserved_46;

sys/dev/pci/drm/amd/include/v10_structs.h

723

uint32_t reserved_47;

sys/dev/pci/drm/amd/include/v10_structs.h

724

uint32_t reserved_48;

sys/dev/pci/drm/amd/include/v10_structs.h

725

uint32_t reserved_49;

sys/dev/pci/drm/amd/include/v10_structs.h

726

uint32_t reserved_50;

sys/dev/pci/drm/amd/include/v10_structs.h

727

uint32_t reserved_51;

sys/dev/pci/drm/amd/include/v10_structs.h

728

uint32_t reserved_52;

sys/dev/pci/drm/amd/include/v10_structs.h

729

uint32_t reserved_53;

sys/dev/pci/drm/amd/include/v10_structs.h

73

uint32_t reserved_45; // offset: 45 (0x2D)

sys/dev/pci/drm/amd/include/v10_structs.h

730

uint32_t reserved_54;

sys/dev/pci/drm/amd/include/v10_structs.h

731

uint32_t reserved_55;

sys/dev/pci/drm/amd/include/v10_structs.h

732

uint32_t reserved_56;

sys/dev/pci/drm/amd/include/v10_structs.h

733

uint32_t reserved_57;

sys/dev/pci/drm/amd/include/v10_structs.h

734

uint32_t reserved_58;

sys/dev/pci/drm/amd/include/v10_structs.h

735

uint32_t reserved_59;

sys/dev/pci/drm/amd/include/v10_structs.h

736

uint32_t reserved_60;

sys/dev/pci/drm/amd/include/v10_structs.h

737

uint32_t reserved_61;

sys/dev/pci/drm/amd/include/v10_structs.h

738

uint32_t reserved_62;

sys/dev/pci/drm/amd/include/v10_structs.h

739

uint32_t reserved_63;

sys/dev/pci/drm/amd/include/v10_structs.h

74

uint32_t reserved_46; // offset: 46 (0x2E)

sys/dev/pci/drm/amd/include/v10_structs.h

740

uint32_t reserved_64;

sys/dev/pci/drm/amd/include/v10_structs.h

741

uint32_t compute_user_data_0;

sys/dev/pci/drm/amd/include/v10_structs.h

742

uint32_t compute_user_data_1;

sys/dev/pci/drm/amd/include/v10_structs.h

743

uint32_t compute_user_data_2;

sys/dev/pci/drm/amd/include/v10_structs.h

744

uint32_t compute_user_data_3;

sys/dev/pci/drm/amd/include/v10_structs.h

745

uint32_t compute_user_data_4;

sys/dev/pci/drm/amd/include/v10_structs.h

746

uint32_t compute_user_data_5;

sys/dev/pci/drm/amd/include/v10_structs.h

747

uint32_t compute_user_data_6;

sys/dev/pci/drm/amd/include/v10_structs.h

748

uint32_t compute_user_data_7;

sys/dev/pci/drm/amd/include/v10_structs.h

749

uint32_t compute_user_data_8;

sys/dev/pci/drm/amd/include/v10_structs.h

75

uint32_t reserved_47; // offset: 47 (0x2F)

sys/dev/pci/drm/amd/include/v10_structs.h

750

uint32_t compute_user_data_9;

sys/dev/pci/drm/amd/include/v10_structs.h

751

uint32_t compute_user_data_10;

sys/dev/pci/drm/amd/include/v10_structs.h

752

uint32_t compute_user_data_11;

sys/dev/pci/drm/amd/include/v10_structs.h

753

uint32_t compute_user_data_12;

sys/dev/pci/drm/amd/include/v10_structs.h

754

uint32_t compute_user_data_13;

sys/dev/pci/drm/amd/include/v10_structs.h

755

uint32_t compute_user_data_14;

sys/dev/pci/drm/amd/include/v10_structs.h

756

uint32_t compute_user_data_15;

sys/dev/pci/drm/amd/include/v10_structs.h

757

uint32_t cp_compute_csinvoc_count_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

758

uint32_t cp_compute_csinvoc_count_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

759

uint32_t reserved_83;

sys/dev/pci/drm/amd/include/v10_structs.h

76

uint32_t reserved_48; // offset: 48 (0x30)

sys/dev/pci/drm/amd/include/v10_structs.h

760

uint32_t reserved_84;

sys/dev/pci/drm/amd/include/v10_structs.h

761

uint32_t reserved_85;

sys/dev/pci/drm/amd/include/v10_structs.h

762

uint32_t cp_mqd_query_time_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

763

uint32_t cp_mqd_query_time_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

764

uint32_t cp_mqd_connect_start_time_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

765

uint32_t cp_mqd_connect_start_time_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

766

uint32_t cp_mqd_connect_end_time_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

767

uint32_t cp_mqd_connect_end_time_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

768

uint32_t cp_mqd_connect_end_wf_count;

sys/dev/pci/drm/amd/include/v10_structs.h

769

uint32_t cp_mqd_connect_end_pq_rptr;

sys/dev/pci/drm/amd/include/v10_structs.h

77

uint32_t reserved_49; // offset: 49 (0x31)

sys/dev/pci/drm/amd/include/v10_structs.h

770

uint32_t cp_mqd_connect_end_pq_wptr;

sys/dev/pci/drm/amd/include/v10_structs.h

771

uint32_t cp_mqd_connect_end_ib_rptr;

sys/dev/pci/drm/amd/include/v10_structs.h

772

uint32_t cp_mqd_readindex_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

773

uint32_t cp_mqd_readindex_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

774

uint32_t cp_mqd_save_start_time_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

775

uint32_t cp_mqd_save_start_time_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

776

uint32_t cp_mqd_save_end_time_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

777

uint32_t cp_mqd_save_end_time_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

778

uint32_t cp_mqd_restore_start_time_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

779

uint32_t cp_mqd_restore_start_time_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

78

uint32_t reserved_50; // offset: 50 (0x32)

sys/dev/pci/drm/amd/include/v10_structs.h

780

uint32_t cp_mqd_restore_end_time_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

781

uint32_t cp_mqd_restore_end_time_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

782

uint32_t disable_queue;

sys/dev/pci/drm/amd/include/v10_structs.h

783

uint32_t reserved_107;

sys/dev/pci/drm/amd/include/v10_structs.h

784

uint32_t gds_cs_ctxsw_cnt0;

sys/dev/pci/drm/amd/include/v10_structs.h

785

uint32_t gds_cs_ctxsw_cnt1;

sys/dev/pci/drm/amd/include/v10_structs.h

786

uint32_t gds_cs_ctxsw_cnt2;

sys/dev/pci/drm/amd/include/v10_structs.h

787

uint32_t gds_cs_ctxsw_cnt3;

sys/dev/pci/drm/amd/include/v10_structs.h

788

uint32_t reserved_112;

sys/dev/pci/drm/amd/include/v10_structs.h

789

uint32_t reserved_113;

sys/dev/pci/drm/amd/include/v10_structs.h

79

uint32_t reserved_51; // offset: 51 (0x33)

sys/dev/pci/drm/amd/include/v10_structs.h

790

uint32_t cp_pq_exe_status_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

791

uint32_t cp_pq_exe_status_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

792

uint32_t cp_packet_id_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

793

uint32_t cp_packet_id_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

794

uint32_t cp_packet_exe_status_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

795

uint32_t cp_packet_exe_status_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

796

uint32_t gds_save_base_addr_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

797

uint32_t gds_save_base_addr_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

798

uint32_t gds_save_mask_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

799

uint32_t gds_save_mask_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

80

uint32_t reserved_52; // offset: 52 (0x34)

sys/dev/pci/drm/amd/include/v10_structs.h

800

uint32_t ctx_save_base_addr_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

801

uint32_t ctx_save_base_addr_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

802

uint32_t reserved_126;

sys/dev/pci/drm/amd/include/v10_structs.h

803

uint32_t reserved_127;

sys/dev/pci/drm/amd/include/v10_structs.h

804

uint32_t cp_mqd_base_addr_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

805

uint32_t cp_mqd_base_addr_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

806

uint32_t cp_hqd_active;

sys/dev/pci/drm/amd/include/v10_structs.h

807

uint32_t cp_hqd_vmid;

sys/dev/pci/drm/amd/include/v10_structs.h

808

uint32_t cp_hqd_persistent_state;

sys/dev/pci/drm/amd/include/v10_structs.h

809

uint32_t cp_hqd_pipe_priority;

sys/dev/pci/drm/amd/include/v10_structs.h

81

uint32_t reserved_53; // offset: 53 (0x35)

sys/dev/pci/drm/amd/include/v10_structs.h

810

uint32_t cp_hqd_queue_priority;

sys/dev/pci/drm/amd/include/v10_structs.h

811

uint32_t cp_hqd_quantum;

sys/dev/pci/drm/amd/include/v10_structs.h

812

uint32_t cp_hqd_pq_base_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

813

uint32_t cp_hqd_pq_base_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

814

uint32_t cp_hqd_pq_rptr;

sys/dev/pci/drm/amd/include/v10_structs.h

815

uint32_t cp_hqd_pq_rptr_report_addr_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

816

uint32_t cp_hqd_pq_rptr_report_addr_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

817

uint32_t cp_hqd_pq_wptr_poll_addr_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

818

uint32_t cp_hqd_pq_wptr_poll_addr_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

819

uint32_t cp_hqd_pq_doorbell_control;

sys/dev/pci/drm/amd/include/v10_structs.h

82

uint32_t reserved_54; // offset: 54 (0x36)

sys/dev/pci/drm/amd/include/v10_structs.h

820

uint32_t reserved_144;

sys/dev/pci/drm/amd/include/v10_structs.h

821

uint32_t cp_hqd_pq_control;

sys/dev/pci/drm/amd/include/v10_structs.h

822

uint32_t cp_hqd_ib_base_addr_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

823

uint32_t cp_hqd_ib_base_addr_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

824

uint32_t cp_hqd_ib_rptr;

sys/dev/pci/drm/amd/include/v10_structs.h

825

uint32_t cp_hqd_ib_control;

sys/dev/pci/drm/amd/include/v10_structs.h

826

uint32_t cp_hqd_iq_timer;

sys/dev/pci/drm/amd/include/v10_structs.h

827

uint32_t cp_hqd_iq_rptr;

sys/dev/pci/drm/amd/include/v10_structs.h

828

uint32_t cp_hqd_dequeue_request;

sys/dev/pci/drm/amd/include/v10_structs.h

829

uint32_t cp_hqd_dma_offload;

sys/dev/pci/drm/amd/include/v10_structs.h

83

uint32_t reserved_55; // offset: 55 (0x37)

sys/dev/pci/drm/amd/include/v10_structs.h

830

uint32_t cp_hqd_sema_cmd;

sys/dev/pci/drm/amd/include/v10_structs.h

831

uint32_t cp_hqd_msg_type;

sys/dev/pci/drm/amd/include/v10_structs.h

832

uint32_t cp_hqd_atomic0_preop_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

833

uint32_t cp_hqd_atomic0_preop_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

834

uint32_t cp_hqd_atomic1_preop_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

835

uint32_t cp_hqd_atomic1_preop_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

836

uint32_t cp_hqd_hq_scheduler0;

sys/dev/pci/drm/amd/include/v10_structs.h

837

uint32_t cp_hqd_hq_scheduler1;

sys/dev/pci/drm/amd/include/v10_structs.h

838

uint32_t cp_mqd_control;

sys/dev/pci/drm/amd/include/v10_structs.h

839

uint32_t cp_hqd_hq_status1;

sys/dev/pci/drm/amd/include/v10_structs.h

84

uint32_t reserved_56; // offset: 56 (0x38)

sys/dev/pci/drm/amd/include/v10_structs.h

840

uint32_t cp_hqd_hq_control1;

sys/dev/pci/drm/amd/include/v10_structs.h

841

uint32_t cp_hqd_eop_base_addr_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

842

uint32_t cp_hqd_eop_base_addr_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

843

uint32_t cp_hqd_eop_control;

sys/dev/pci/drm/amd/include/v10_structs.h

844

uint32_t cp_hqd_eop_rptr;

sys/dev/pci/drm/amd/include/v10_structs.h

845

uint32_t cp_hqd_eop_wptr;

sys/dev/pci/drm/amd/include/v10_structs.h

846

uint32_t cp_hqd_eop_done_events;

sys/dev/pci/drm/amd/include/v10_structs.h

847

uint32_t cp_hqd_ctx_save_base_addr_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

848

uint32_t cp_hqd_ctx_save_base_addr_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

849

uint32_t cp_hqd_ctx_save_control;

sys/dev/pci/drm/amd/include/v10_structs.h

85

uint32_t reserved_57; // offset: 57 (0x39)

sys/dev/pci/drm/amd/include/v10_structs.h

850

uint32_t cp_hqd_cntl_stack_offset;

sys/dev/pci/drm/amd/include/v10_structs.h

851

uint32_t cp_hqd_cntl_stack_size;

sys/dev/pci/drm/amd/include/v10_structs.h

852

uint32_t cp_hqd_wg_state_offset;

sys/dev/pci/drm/amd/include/v10_structs.h

853

uint32_t cp_hqd_ctx_save_size;

sys/dev/pci/drm/amd/include/v10_structs.h

854

uint32_t cp_hqd_gds_resource_state;

sys/dev/pci/drm/amd/include/v10_structs.h

855

uint32_t cp_hqd_error;

sys/dev/pci/drm/amd/include/v10_structs.h

856

uint32_t cp_hqd_eop_wptr_mem;

sys/dev/pci/drm/amd/include/v10_structs.h

857

uint32_t cp_hqd_aql_control;

sys/dev/pci/drm/amd/include/v10_structs.h

858

uint32_t cp_hqd_pq_wptr_lo;

sys/dev/pci/drm/amd/include/v10_structs.h

859

uint32_t cp_hqd_pq_wptr_hi;

sys/dev/pci/drm/amd/include/v10_structs.h

86

uint32_t reserved_58; // offset: 58 (0x3A)

sys/dev/pci/drm/amd/include/v10_structs.h

860

uint32_t cp_hqd_suspend_cntl_stack_offset;

sys/dev/pci/drm/amd/include/v10_structs.h

861

uint32_t cp_hqd_suspend_cntl_stack_dw_cnt;

sys/dev/pci/drm/amd/include/v10_structs.h

862

uint32_t cp_hqd_suspend_wg_state_offset;

sys/dev/pci/drm/amd/include/v10_structs.h

863

uint32_t reserved_187;

sys/dev/pci/drm/amd/include/v10_structs.h

864

uint32_t reserved_188;

sys/dev/pci/drm/amd/include/v10_structs.h

865

uint32_t reserved_189;

sys/dev/pci/drm/amd/include/v10_structs.h

866

uint32_t reserved_190;

sys/dev/pci/drm/amd/include/v10_structs.h

867

uint32_t reserved_191;

sys/dev/pci/drm/amd/include/v10_structs.h

868

uint32_t iqtimer_pkt_header;

sys/dev/pci/drm/amd/include/v10_structs.h

869

uint32_t iqtimer_pkt_dw0;

sys/dev/pci/drm/amd/include/v10_structs.h

87

uint32_t reserved_59; // offset: 59 (0x3B)

sys/dev/pci/drm/amd/include/v10_structs.h

870

uint32_t iqtimer_pkt_dw1;

sys/dev/pci/drm/amd/include/v10_structs.h

871

uint32_t iqtimer_pkt_dw2;

sys/dev/pci/drm/amd/include/v10_structs.h

872

uint32_t iqtimer_pkt_dw3;

sys/dev/pci/drm/amd/include/v10_structs.h

873

uint32_t iqtimer_pkt_dw4;

sys/dev/pci/drm/amd/include/v10_structs.h

874

uint32_t iqtimer_pkt_dw5;

sys/dev/pci/drm/amd/include/v10_structs.h

875

uint32_t iqtimer_pkt_dw6;

sys/dev/pci/drm/amd/include/v10_structs.h

876

uint32_t iqtimer_pkt_dw7;

sys/dev/pci/drm/amd/include/v10_structs.h

877

uint32_t iqtimer_pkt_dw8;

sys/dev/pci/drm/amd/include/v10_structs.h

878

uint32_t iqtimer_pkt_dw9;

sys/dev/pci/drm/amd/include/v10_structs.h

879

uint32_t iqtimer_pkt_dw10;

sys/dev/pci/drm/amd/include/v10_structs.h

88

uint32_t reserved_60; // offset: 60 (0x3C)

sys/dev/pci/drm/amd/include/v10_structs.h

880

uint32_t iqtimer_pkt_dw11;

sys/dev/pci/drm/amd/include/v10_structs.h

881

uint32_t iqtimer_pkt_dw12;

sys/dev/pci/drm/amd/include/v10_structs.h

882

uint32_t iqtimer_pkt_dw13;

sys/dev/pci/drm/amd/include/v10_structs.h

883

uint32_t iqtimer_pkt_dw14;

sys/dev/pci/drm/amd/include/v10_structs.h

884

uint32_t iqtimer_pkt_dw15;

sys/dev/pci/drm/amd/include/v10_structs.h

885

uint32_t iqtimer_pkt_dw16;

sys/dev/pci/drm/amd/include/v10_structs.h

886

uint32_t iqtimer_pkt_dw17;

sys/dev/pci/drm/amd/include/v10_structs.h

887

uint32_t iqtimer_pkt_dw18;

sys/dev/pci/drm/amd/include/v10_structs.h

888

uint32_t iqtimer_pkt_dw19;

sys/dev/pci/drm/amd/include/v10_structs.h

889

uint32_t iqtimer_pkt_dw20;

sys/dev/pci/drm/amd/include/v10_structs.h

89

uint32_t reserved_61; // offset: 61 (0x3D)

sys/dev/pci/drm/amd/include/v10_structs.h

890

uint32_t iqtimer_pkt_dw21;

sys/dev/pci/drm/amd/include/v10_structs.h

891

uint32_t iqtimer_pkt_dw22;

sys/dev/pci/drm/amd/include/v10_structs.h

892

uint32_t iqtimer_pkt_dw23;

sys/dev/pci/drm/amd/include/v10_structs.h

893

uint32_t iqtimer_pkt_dw24;

sys/dev/pci/drm/amd/include/v10_structs.h

894

uint32_t iqtimer_pkt_dw25;

sys/dev/pci/drm/amd/include/v10_structs.h

895

uint32_t iqtimer_pkt_dw26;

sys/dev/pci/drm/amd/include/v10_structs.h

896

uint32_t iqtimer_pkt_dw27;

sys/dev/pci/drm/amd/include/v10_structs.h

897

uint32_t iqtimer_pkt_dw28;

sys/dev/pci/drm/amd/include/v10_structs.h

898

uint32_t iqtimer_pkt_dw29;

sys/dev/pci/drm/amd/include/v10_structs.h

899

uint32_t iqtimer_pkt_dw30;

sys/dev/pci/drm/amd/include/v10_structs.h

90

uint32_t reserved_62; // offset: 62 (0x3E)

sys/dev/pci/drm/amd/include/v10_structs.h

900

uint32_t iqtimer_pkt_dw31;

sys/dev/pci/drm/amd/include/v10_structs.h

901

uint32_t reserved_225;

sys/dev/pci/drm/amd/include/v10_structs.h

902

uint32_t reserved_226;

sys/dev/pci/drm/amd/include/v10_structs.h

903

uint32_t reserved_227;

sys/dev/pci/drm/amd/include/v10_structs.h

904

uint32_t set_resources_header;

sys/dev/pci/drm/amd/include/v10_structs.h

905

uint32_t set_resources_dw1;

sys/dev/pci/drm/amd/include/v10_structs.h

906

uint32_t set_resources_dw2;

sys/dev/pci/drm/amd/include/v10_structs.h

907

uint32_t set_resources_dw3;

sys/dev/pci/drm/amd/include/v10_structs.h

908

uint32_t set_resources_dw4;

sys/dev/pci/drm/amd/include/v10_structs.h

909

uint32_t set_resources_dw5;

sys/dev/pci/drm/amd/include/v10_structs.h

91

uint32_t reserved_63; // offset: 63 (0x3F)

sys/dev/pci/drm/amd/include/v10_structs.h

910

uint32_t set_resources_dw6;

sys/dev/pci/drm/amd/include/v10_structs.h

911

uint32_t set_resources_dw7;

sys/dev/pci/drm/amd/include/v10_structs.h

912

uint32_t reserved_236;

sys/dev/pci/drm/amd/include/v10_structs.h

913

uint32_t reserved_237;

sys/dev/pci/drm/amd/include/v10_structs.h

914

uint32_t reserved_238;

sys/dev/pci/drm/amd/include/v10_structs.h

915

uint32_t reserved_239;

sys/dev/pci/drm/amd/include/v10_structs.h

916

uint32_t queue_doorbell_id0;

sys/dev/pci/drm/amd/include/v10_structs.h

917

uint32_t queue_doorbell_id1;

sys/dev/pci/drm/amd/include/v10_structs.h

918

uint32_t queue_doorbell_id2;

sys/dev/pci/drm/amd/include/v10_structs.h

919

uint32_t queue_doorbell_id3;

sys/dev/pci/drm/amd/include/v10_structs.h

92

uint32_t reserved_64; // offset: 64 (0x40)

sys/dev/pci/drm/amd/include/v10_structs.h

920

uint32_t queue_doorbell_id4;

sys/dev/pci/drm/amd/include/v10_structs.h

921

uint32_t queue_doorbell_id5;

sys/dev/pci/drm/amd/include/v10_structs.h

922

uint32_t queue_doorbell_id6;

sys/dev/pci/drm/amd/include/v10_structs.h

923

uint32_t queue_doorbell_id7;

sys/dev/pci/drm/amd/include/v10_structs.h

924

uint32_t queue_doorbell_id8;

sys/dev/pci/drm/amd/include/v10_structs.h

925

uint32_t queue_doorbell_id9;

sys/dev/pci/drm/amd/include/v10_structs.h

926

uint32_t queue_doorbell_id10;

sys/dev/pci/drm/amd/include/v10_structs.h

927

uint32_t queue_doorbell_id11;

sys/dev/pci/drm/amd/include/v10_structs.h

928

uint32_t queue_doorbell_id12;

sys/dev/pci/drm/amd/include/v10_structs.h

929

uint32_t queue_doorbell_id13;

sys/dev/pci/drm/amd/include/v10_structs.h

93

uint32_t reserved_65; // offset: 65 (0x41)

sys/dev/pci/drm/amd/include/v10_structs.h

930

uint32_t queue_doorbell_id14;

sys/dev/pci/drm/amd/include/v10_structs.h

931

uint32_t queue_doorbell_id15;

sys/dev/pci/drm/amd/include/v10_structs.h

932

uint32_t reserved_256;

sys/dev/pci/drm/amd/include/v10_structs.h

933

uint32_t reserved_257;

sys/dev/pci/drm/amd/include/v10_structs.h

934

uint32_t reserved_258;

sys/dev/pci/drm/amd/include/v10_structs.h

935

uint32_t reserved_259;

sys/dev/pci/drm/amd/include/v10_structs.h

936

uint32_t reserved_260;

sys/dev/pci/drm/amd/include/v10_structs.h

937

uint32_t reserved_261;

sys/dev/pci/drm/amd/include/v10_structs.h

938

uint32_t reserved_262;

sys/dev/pci/drm/amd/include/v10_structs.h

939

uint32_t reserved_263;

sys/dev/pci/drm/amd/include/v10_structs.h

94

uint32_t reserved_66; // offset: 66 (0x42)

sys/dev/pci/drm/amd/include/v10_structs.h

940

uint32_t reserved_264;

sys/dev/pci/drm/amd/include/v10_structs.h

941

uint32_t reserved_265;

sys/dev/pci/drm/amd/include/v10_structs.h

942

uint32_t reserved_266;

sys/dev/pci/drm/amd/include/v10_structs.h

943

uint32_t reserved_267;

sys/dev/pci/drm/amd/include/v10_structs.h

944

uint32_t reserved_268;

sys/dev/pci/drm/amd/include/v10_structs.h

945

uint32_t reserved_269;

sys/dev/pci/drm/amd/include/v10_structs.h

946

uint32_t reserved_270;

sys/dev/pci/drm/amd/include/v10_structs.h

947

uint32_t reserved_271;

sys/dev/pci/drm/amd/include/v10_structs.h

948

uint32_t reserved_272;

sys/dev/pci/drm/amd/include/v10_structs.h

949

uint32_t reserved_273;

sys/dev/pci/drm/amd/include/v10_structs.h

95

uint32_t reserved_67; // offset: 67 (0x43)

sys/dev/pci/drm/amd/include/v10_structs.h

950

uint32_t reserved_274;

sys/dev/pci/drm/amd/include/v10_structs.h

951

uint32_t reserved_275;

sys/dev/pci/drm/amd/include/v10_structs.h

952

uint32_t reserved_276;

sys/dev/pci/drm/amd/include/v10_structs.h

953

uint32_t reserved_277;

sys/dev/pci/drm/amd/include/v10_structs.h

954

uint32_t reserved_278;

sys/dev/pci/drm/amd/include/v10_structs.h

955

uint32_t reserved_279;

sys/dev/pci/drm/amd/include/v10_structs.h

956

uint32_t reserved_280;

sys/dev/pci/drm/amd/include/v10_structs.h

957

uint32_t reserved_281;

sys/dev/pci/drm/amd/include/v10_structs.h

958

uint32_t reserved_282;

sys/dev/pci/drm/amd/include/v10_structs.h

959

uint32_t reserved_283;

sys/dev/pci/drm/amd/include/v10_structs.h

96

uint32_t reserved_68; // offset: 68 (0x44)

sys/dev/pci/drm/amd/include/v10_structs.h

960

uint32_t reserved_284;

sys/dev/pci/drm/amd/include/v10_structs.h

961

uint32_t reserved_285;

sys/dev/pci/drm/amd/include/v10_structs.h

962

uint32_t reserved_286;

sys/dev/pci/drm/amd/include/v10_structs.h

963

uint32_t reserved_287;

sys/dev/pci/drm/amd/include/v10_structs.h

964

uint32_t reserved_288;

sys/dev/pci/drm/amd/include/v10_structs.h

965

uint32_t reserved_289;

sys/dev/pci/drm/amd/include/v10_structs.h

966

uint32_t reserved_290;

sys/dev/pci/drm/amd/include/v10_structs.h

967

uint32_t reserved_291;

sys/dev/pci/drm/amd/include/v10_structs.h

968

uint32_t reserved_292;

sys/dev/pci/drm/amd/include/v10_structs.h

969

uint32_t reserved_293;

sys/dev/pci/drm/amd/include/v10_structs.h

97

uint32_t reserved_69; // offset: 69 (0x45)

sys/dev/pci/drm/amd/include/v10_structs.h

970

uint32_t reserved_294;

sys/dev/pci/drm/amd/include/v10_structs.h

971

uint32_t reserved_295;

sys/dev/pci/drm/amd/include/v10_structs.h

972

uint32_t reserved_296;

sys/dev/pci/drm/amd/include/v10_structs.h

973

uint32_t reserved_297;

sys/dev/pci/drm/amd/include/v10_structs.h

974

uint32_t reserved_298;

sys/dev/pci/drm/amd/include/v10_structs.h

975

uint32_t reserved_299;

sys/dev/pci/drm/amd/include/v10_structs.h

976

uint32_t reserved_300;

sys/dev/pci/drm/amd/include/v10_structs.h

977

uint32_t reserved_301;

sys/dev/pci/drm/amd/include/v10_structs.h

978

uint32_t reserved_302;

sys/dev/pci/drm/amd/include/v10_structs.h

979

uint32_t reserved_303;

sys/dev/pci/drm/amd/include/v10_structs.h

98

uint32_t reserved_70; // offset: 70 (0x46)

sys/dev/pci/drm/amd/include/v10_structs.h

980

uint32_t reserved_304;

sys/dev/pci/drm/amd/include/v10_structs.h

981

uint32_t reserved_305;

sys/dev/pci/drm/amd/include/v10_structs.h

982

uint32_t reserved_306;

sys/dev/pci/drm/amd/include/v10_structs.h

983

uint32_t reserved_307;

sys/dev/pci/drm/amd/include/v10_structs.h

984

uint32_t reserved_308;

sys/dev/pci/drm/amd/include/v10_structs.h

985

uint32_t reserved_309;

sys/dev/pci/drm/amd/include/v10_structs.h

986

uint32_t reserved_310;

sys/dev/pci/drm/amd/include/v10_structs.h

987

uint32_t reserved_311;

sys/dev/pci/drm/amd/include/v10_structs.h

988

uint32_t reserved_312;

sys/dev/pci/drm/amd/include/v10_structs.h

989

uint32_t reserved_313;

sys/dev/pci/drm/amd/include/v10_structs.h

99

uint32_t reserved_71; // offset: 71 (0x47)

sys/dev/pci/drm/amd/include/v10_structs.h

990

uint32_t reserved_314;

sys/dev/pci/drm/amd/include/v10_structs.h

991

uint32_t reserved_315;

sys/dev/pci/drm/amd/include/v10_structs.h

992

uint32_t reserved_316;

sys/dev/pci/drm/amd/include/v10_structs.h

993

uint32_t reserved_317;

sys/dev/pci/drm/amd/include/v10_structs.h

994

uint32_t reserved_318;

sys/dev/pci/drm/amd/include/v10_structs.h

995

uint32_t reserved_319;

sys/dev/pci/drm/amd/include/v10_structs.h

996

uint32_t reserved_320;

sys/dev/pci/drm/amd/include/v10_structs.h

997

uint32_t reserved_321;

sys/dev/pci/drm/amd/include/v10_structs.h

998

uint32_t reserved_322;

sys/dev/pci/drm/amd/include/v10_structs.h

999

uint32_t reserved_323;

sys/dev/pci/drm/amd/include/v11_structs.h

100

uint32_t reserved_72; // offset: 72 (0x48)

sys/dev/pci/drm/amd/include/v11_structs.h

1000

uint32_t reserved_325; // offset: 325 (0x145)

sys/dev/pci/drm/amd/include/v11_structs.h

1001

uint32_t reserved_326; // offset: 326 (0x146)

sys/dev/pci/drm/amd/include/v11_structs.h

1002

uint32_t reserved_327; // offset: 327 (0x147)

sys/dev/pci/drm/amd/include/v11_structs.h

1003

uint32_t reserved_328; // offset: 328 (0x148)

sys/dev/pci/drm/amd/include/v11_structs.h

1004

uint32_t reserved_329; // offset: 329 (0x149)

sys/dev/pci/drm/amd/include/v11_structs.h

1005

uint32_t reserved_330; // offset: 330 (0x14A)

sys/dev/pci/drm/amd/include/v11_structs.h

1006

uint32_t reserved_331; // offset: 331 (0x14B)

sys/dev/pci/drm/amd/include/v11_structs.h

1007

uint32_t reserved_332; // offset: 332 (0x14C)

sys/dev/pci/drm/amd/include/v11_structs.h

1008

uint32_t reserved_333; // offset: 333 (0x14D)

sys/dev/pci/drm/amd/include/v11_structs.h

1009

uint32_t reserved_334; // offset: 334 (0x14E)

sys/dev/pci/drm/amd/include/v11_structs.h

101

uint32_t reserved_73; // offset: 73 (0x49)

sys/dev/pci/drm/amd/include/v11_structs.h

1010

uint32_t reserved_335; // offset: 335 (0x14F)

sys/dev/pci/drm/amd/include/v11_structs.h

1011

uint32_t reserved_336; // offset: 336 (0x150)

sys/dev/pci/drm/amd/include/v11_structs.h

1012

uint32_t reserved_337; // offset: 337 (0x151)

sys/dev/pci/drm/amd/include/v11_structs.h

1013

uint32_t reserved_338; // offset: 338 (0x152)

sys/dev/pci/drm/amd/include/v11_structs.h

1014

uint32_t reserved_339; // offset: 339 (0x153)

sys/dev/pci/drm/amd/include/v11_structs.h

1015

uint32_t reserved_340; // offset: 340 (0x154)

sys/dev/pci/drm/amd/include/v11_structs.h

1016

uint32_t reserved_341; // offset: 341 (0x155)

sys/dev/pci/drm/amd/include/v11_structs.h

1017

uint32_t reserved_342; // offset: 342 (0x156)

sys/dev/pci/drm/amd/include/v11_structs.h

1018

uint32_t reserved_343; // offset: 343 (0x157)

sys/dev/pci/drm/amd/include/v11_structs.h

1019

uint32_t reserved_344; // offset: 344 (0x158)

sys/dev/pci/drm/amd/include/v11_structs.h

102

uint32_t reserved_74; // offset: 74 (0x4A)

sys/dev/pci/drm/amd/include/v11_structs.h

1020

uint32_t reserved_345; // offset: 345 (0x159)

sys/dev/pci/drm/amd/include/v11_structs.h

1021

uint32_t reserved_346; // offset: 346 (0x15A)

sys/dev/pci/drm/amd/include/v11_structs.h

1022

uint32_t reserved_347; // offset: 347 (0x15B)

sys/dev/pci/drm/amd/include/v11_structs.h

1023

uint32_t reserved_348; // offset: 348 (0x15C)

sys/dev/pci/drm/amd/include/v11_structs.h

1024

uint32_t reserved_349; // offset: 349 (0x15D)

sys/dev/pci/drm/amd/include/v11_structs.h

1025

uint32_t reserved_350; // offset: 350 (0x15E)

sys/dev/pci/drm/amd/include/v11_structs.h

1026

uint32_t reserved_351; // offset: 351 (0x15F)

sys/dev/pci/drm/amd/include/v11_structs.h

1027

uint32_t reserved_352; // offset: 352 (0x160)

sys/dev/pci/drm/amd/include/v11_structs.h

1028

uint32_t reserved_353; // offset: 353 (0x161)

sys/dev/pci/drm/amd/include/v11_structs.h

1029

uint32_t reserved_354; // offset: 354 (0x162)

sys/dev/pci/drm/amd/include/v11_structs.h

103

uint32_t reserved_75; // offset: 75 (0x4B)

sys/dev/pci/drm/amd/include/v11_structs.h

1030

uint32_t reserved_355; // offset: 355 (0x163)

sys/dev/pci/drm/amd/include/v11_structs.h

1031

uint32_t reserved_356; // offset: 356 (0x164)

sys/dev/pci/drm/amd/include/v11_structs.h

1032

uint32_t reserved_357; // offset: 357 (0x165)

sys/dev/pci/drm/amd/include/v11_structs.h

1033

uint32_t reserved_358; // offset: 358 (0x166)

sys/dev/pci/drm/amd/include/v11_structs.h

1034

uint32_t reserved_359; // offset: 359 (0x167)

sys/dev/pci/drm/amd/include/v11_structs.h

1035

uint32_t reserved_360; // offset: 360 (0x168)

sys/dev/pci/drm/amd/include/v11_structs.h

1036

uint32_t reserved_361; // offset: 361 (0x169)

sys/dev/pci/drm/amd/include/v11_structs.h

1037

uint32_t reserved_362; // offset: 362 (0x16A)

sys/dev/pci/drm/amd/include/v11_structs.h

1038

uint32_t reserved_363; // offset: 363 (0x16B)

sys/dev/pci/drm/amd/include/v11_structs.h

1039

uint32_t reserved_364; // offset: 364 (0x16C)

sys/dev/pci/drm/amd/include/v11_structs.h

104

uint32_t reserved_76; // offset: 76 (0x4C)

sys/dev/pci/drm/amd/include/v11_structs.h

1040

uint32_t reserved_365; // offset: 365 (0x16D)

sys/dev/pci/drm/amd/include/v11_structs.h

1041

uint32_t reserved_366; // offset: 366 (0x16E)

sys/dev/pci/drm/amd/include/v11_structs.h

1042

uint32_t reserved_367; // offset: 367 (0x16F)

sys/dev/pci/drm/amd/include/v11_structs.h

1043

uint32_t reserved_368; // offset: 368 (0x170)

sys/dev/pci/drm/amd/include/v11_structs.h

1044

uint32_t reserved_369; // offset: 369 (0x171)

sys/dev/pci/drm/amd/include/v11_structs.h

1045

uint32_t reserved_370; // offset: 370 (0x172)

sys/dev/pci/drm/amd/include/v11_structs.h

1046

uint32_t reserved_371; // offset: 371 (0x173)

sys/dev/pci/drm/amd/include/v11_structs.h

1047

uint32_t reserved_372; // offset: 372 (0x174)

sys/dev/pci/drm/amd/include/v11_structs.h

1048

uint32_t reserved_373; // offset: 373 (0x175)

sys/dev/pci/drm/amd/include/v11_structs.h

1049

uint32_t reserved_374; // offset: 374 (0x176)

sys/dev/pci/drm/amd/include/v11_structs.h

105

uint32_t reserved_77; // offset: 77 (0x4D)

sys/dev/pci/drm/amd/include/v11_structs.h

1050

uint32_t reserved_375; // offset: 375 (0x177)

sys/dev/pci/drm/amd/include/v11_structs.h

1051

uint32_t reserved_376; // offset: 376 (0x178)

sys/dev/pci/drm/amd/include/v11_structs.h

1052

uint32_t reserved_377; // offset: 377 (0x179)

sys/dev/pci/drm/amd/include/v11_structs.h

1053

uint32_t reserved_378; // offset: 378 (0x17A)

sys/dev/pci/drm/amd/include/v11_structs.h

1054

uint32_t reserved_379; // offset: 379 (0x17B)

sys/dev/pci/drm/amd/include/v11_structs.h

1055

uint32_t reserved_380; // offset: 380 (0x17C)

sys/dev/pci/drm/amd/include/v11_structs.h

1056

uint32_t reserved_381; // offset: 381 (0x17D)

sys/dev/pci/drm/amd/include/v11_structs.h

1057

uint32_t reserved_382; // offset: 382 (0x17E)

sys/dev/pci/drm/amd/include/v11_structs.h

1058

uint32_t reserved_383; // offset: 383 (0x17F)

sys/dev/pci/drm/amd/include/v11_structs.h

1059

uint32_t reserved_384; // offset: 384 (0x180)

sys/dev/pci/drm/amd/include/v11_structs.h

106

uint32_t reserved_78; // offset: 78 (0x4E)

sys/dev/pci/drm/amd/include/v11_structs.h

1060

uint32_t reserved_385; // offset: 385 (0x181)

sys/dev/pci/drm/amd/include/v11_structs.h

1061

uint32_t reserved_386; // offset: 386 (0x182)

sys/dev/pci/drm/amd/include/v11_structs.h

1062

uint32_t reserved_387; // offset: 387 (0x183)

sys/dev/pci/drm/amd/include/v11_structs.h

1063

uint32_t reserved_388; // offset: 388 (0x184)

sys/dev/pci/drm/amd/include/v11_structs.h

1064

uint32_t reserved_389; // offset: 389 (0x185)

sys/dev/pci/drm/amd/include/v11_structs.h

1065

uint32_t reserved_390; // offset: 390 (0x186)

sys/dev/pci/drm/amd/include/v11_structs.h

1066

uint32_t reserved_391; // offset: 391 (0x187)

sys/dev/pci/drm/amd/include/v11_structs.h

1067

uint32_t reserved_392; // offset: 392 (0x188)

sys/dev/pci/drm/amd/include/v11_structs.h

1068

uint32_t reserved_393; // offset: 393 (0x189)

sys/dev/pci/drm/amd/include/v11_structs.h

1069

uint32_t reserved_394; // offset: 394 (0x18A)

sys/dev/pci/drm/amd/include/v11_structs.h

107

uint32_t reserved_79; // offset: 79 (0x4F)

sys/dev/pci/drm/amd/include/v11_structs.h

1070

uint32_t reserved_395; // offset: 395 (0x18B)

sys/dev/pci/drm/amd/include/v11_structs.h

1071

uint32_t reserved_396; // offset: 396 (0x18C)

sys/dev/pci/drm/amd/include/v11_structs.h

1072

uint32_t reserved_397; // offset: 397 (0x18D)

sys/dev/pci/drm/amd/include/v11_structs.h

1073

uint32_t reserved_398; // offset: 398 (0x18E)

sys/dev/pci/drm/amd/include/v11_structs.h

1074

uint32_t reserved_399; // offset: 399 (0x18F)

sys/dev/pci/drm/amd/include/v11_structs.h

1075

uint32_t reserved_400; // offset: 400 (0x190)

sys/dev/pci/drm/amd/include/v11_structs.h

1076

uint32_t reserved_401; // offset: 401 (0x191)

sys/dev/pci/drm/amd/include/v11_structs.h

1077

uint32_t reserved_402; // offset: 402 (0x192)

sys/dev/pci/drm/amd/include/v11_structs.h

1078

uint32_t reserved_403; // offset: 403 (0x193)

sys/dev/pci/drm/amd/include/v11_structs.h

1079

uint32_t reserved_404; // offset: 404 (0x194)

sys/dev/pci/drm/amd/include/v11_structs.h

108

uint32_t reserved_80; // offset: 80 (0x50)

sys/dev/pci/drm/amd/include/v11_structs.h

1080

uint32_t reserved_405; // offset: 405 (0x195)

sys/dev/pci/drm/amd/include/v11_structs.h

1081

uint32_t reserved_406; // offset: 406 (0x196)

sys/dev/pci/drm/amd/include/v11_structs.h

1082

uint32_t reserved_407; // offset: 407 (0x197)

sys/dev/pci/drm/amd/include/v11_structs.h

1083

uint32_t reserved_408; // offset: 408 (0x198)

sys/dev/pci/drm/amd/include/v11_structs.h

1084

uint32_t reserved_409; // offset: 409 (0x199)

sys/dev/pci/drm/amd/include/v11_structs.h

1085

uint32_t reserved_410; // offset: 410 (0x19A)

sys/dev/pci/drm/amd/include/v11_structs.h

1086

uint32_t reserved_411; // offset: 411 (0x19B)

sys/dev/pci/drm/amd/include/v11_structs.h

1087

uint32_t reserved_412; // offset: 412 (0x19C)

sys/dev/pci/drm/amd/include/v11_structs.h

1088

uint32_t reserved_413; // offset: 413 (0x19D)

sys/dev/pci/drm/amd/include/v11_structs.h

1089

uint32_t reserved_414; // offset: 414 (0x19E)

sys/dev/pci/drm/amd/include/v11_structs.h

109

uint32_t reserved_81; // offset: 81 (0x51)

sys/dev/pci/drm/amd/include/v11_structs.h

1090

uint32_t reserved_415; // offset: 415 (0x19F)

sys/dev/pci/drm/amd/include/v11_structs.h

1091

uint32_t reserved_416; // offset: 416 (0x1A0)

sys/dev/pci/drm/amd/include/v11_structs.h

1092

uint32_t reserved_417; // offset: 417 (0x1A1)

sys/dev/pci/drm/amd/include/v11_structs.h

1093

uint32_t reserved_418; // offset: 418 (0x1A2)

sys/dev/pci/drm/amd/include/v11_structs.h

1094

uint32_t reserved_419; // offset: 419 (0x1A3)

sys/dev/pci/drm/amd/include/v11_structs.h

1095

uint32_t reserved_420; // offset: 420 (0x1A4)

sys/dev/pci/drm/amd/include/v11_structs.h

1096

uint32_t reserved_421; // offset: 421 (0x1A5)

sys/dev/pci/drm/amd/include/v11_structs.h

1097

uint32_t reserved_422; // offset: 422 (0x1A6)

sys/dev/pci/drm/amd/include/v11_structs.h

1098

uint32_t reserved_423; // offset: 423 (0x1A7)

sys/dev/pci/drm/amd/include/v11_structs.h

1099

uint32_t reserved_424; // offset: 424 (0x1A8)

sys/dev/pci/drm/amd/include/v11_structs.h

110

uint32_t reserved_82; // offset: 82 (0x52)

sys/dev/pci/drm/amd/include/v11_structs.h

1100

uint32_t reserved_425; // offset: 425 (0x1A9)

sys/dev/pci/drm/amd/include/v11_structs.h

1101

uint32_t reserved_426; // offset: 426 (0x1AA)

sys/dev/pci/drm/amd/include/v11_structs.h

1102

uint32_t reserved_427; // offset: 427 (0x1AB)

sys/dev/pci/drm/amd/include/v11_structs.h

1103

uint32_t reserved_428; // offset: 428 (0x1AC)

sys/dev/pci/drm/amd/include/v11_structs.h

1104

uint32_t reserved_429; // offset: 429 (0x1AD)

sys/dev/pci/drm/amd/include/v11_structs.h

1105

uint32_t reserved_430; // offset: 430 (0x1AE)

sys/dev/pci/drm/amd/include/v11_structs.h

1106

uint32_t reserved_431; // offset: 431 (0x1AF)

sys/dev/pci/drm/amd/include/v11_structs.h

1107

uint32_t reserved_432; // offset: 432 (0x1B0)

sys/dev/pci/drm/amd/include/v11_structs.h

1108

uint32_t reserved_433; // offset: 433 (0x1B1)

sys/dev/pci/drm/amd/include/v11_structs.h

1109

uint32_t reserved_434; // offset: 434 (0x1B2)

sys/dev/pci/drm/amd/include/v11_structs.h

111

uint32_t reserved_83; // offset: 83 (0x53)

sys/dev/pci/drm/amd/include/v11_structs.h

1110

uint32_t reserved_435; // offset: 435 (0x1B3)

sys/dev/pci/drm/amd/include/v11_structs.h

1111

uint32_t reserved_436; // offset: 436 (0x1B4)

sys/dev/pci/drm/amd/include/v11_structs.h

1112

uint32_t reserved_437; // offset: 437 (0x1B5)

sys/dev/pci/drm/amd/include/v11_structs.h

1113

uint32_t reserved_438; // offset: 438 (0x1B6)

sys/dev/pci/drm/amd/include/v11_structs.h

1114

uint32_t reserved_439; // offset: 439 (0x1B7)

sys/dev/pci/drm/amd/include/v11_structs.h

1115

uint32_t reserved_440; // offset: 440 (0x1B8)

sys/dev/pci/drm/amd/include/v11_structs.h

1116

uint32_t reserved_441; // offset: 441 (0x1B9)

sys/dev/pci/drm/amd/include/v11_structs.h

1117

uint32_t reserved_442; // offset: 442 (0x1BA)

sys/dev/pci/drm/amd/include/v11_structs.h

1118

uint32_t reserved_443; // offset: 443 (0x1BB)

sys/dev/pci/drm/amd/include/v11_structs.h

1119

uint32_t reserved_444; // offset: 444 (0x1BC)

sys/dev/pci/drm/amd/include/v11_structs.h

112

uint32_t checksum_lo; // offset: 84 (0x54)

sys/dev/pci/drm/amd/include/v11_structs.h

1120

uint32_t reserved_445; // offset: 445 (0x1BD)

sys/dev/pci/drm/amd/include/v11_structs.h

1121

uint32_t fence_address_lo; // offset: 446 (0x1BE)

sys/dev/pci/drm/amd/include/v11_structs.h

1122

uint32_t fence_address_hi; // offset: 447 (0x1BF)

sys/dev/pci/drm/amd/include/v11_structs.h

1123

uint32_t gws_0_val; // offset: 448 (0x1C0)

sys/dev/pci/drm/amd/include/v11_structs.h

1124

uint32_t gws_1_val; // offset: 449 (0x1C1)

sys/dev/pci/drm/amd/include/v11_structs.h

1125

uint32_t gws_2_val; // offset: 450 (0x1C2)

sys/dev/pci/drm/amd/include/v11_structs.h

1126

uint32_t gws_3_val; // offset: 451 (0x1C3)

sys/dev/pci/drm/amd/include/v11_structs.h

1127

uint32_t gws_4_val; // offset: 452 (0x1C4)

sys/dev/pci/drm/amd/include/v11_structs.h

1128

uint32_t gws_5_val; // offset: 453 (0x1C5)

sys/dev/pci/drm/amd/include/v11_structs.h

1129

uint32_t gws_6_val; // offset: 454 (0x1C6)

sys/dev/pci/drm/amd/include/v11_structs.h

113

uint32_t checksum_hi; // offset: 85 (0x55)

sys/dev/pci/drm/amd/include/v11_structs.h

1130

uint32_t gws_7_val; // offset: 455 (0x1C7)

sys/dev/pci/drm/amd/include/v11_structs.h

1131

uint32_t gws_8_val; // offset: 456 (0x1C8)

sys/dev/pci/drm/amd/include/v11_structs.h

1132

uint32_t gws_9_val; // offset: 457 (0x1C9)

sys/dev/pci/drm/amd/include/v11_structs.h

1133

uint32_t gws_10_val; // offset: 458 (0x1CA)

sys/dev/pci/drm/amd/include/v11_structs.h

1134

uint32_t gws_11_val; // offset: 459 (0x1CB)

sys/dev/pci/drm/amd/include/v11_structs.h

1135

uint32_t gws_12_val; // offset: 460 (0x1CC)

sys/dev/pci/drm/amd/include/v11_structs.h

1136

uint32_t gws_13_val; // offset: 461 (0x1CD)

sys/dev/pci/drm/amd/include/v11_structs.h

1137

uint32_t gws_14_val; // offset: 462 (0x1CE)

sys/dev/pci/drm/amd/include/v11_structs.h

1138

uint32_t gws_15_val; // offset: 463 (0x1CF)

sys/dev/pci/drm/amd/include/v11_structs.h

1139

uint32_t gws_16_val; // offset: 464 (0x1D0)

sys/dev/pci/drm/amd/include/v11_structs.h

114

uint32_t cp_mqd_query_time_lo; // offset: 86 (0x56)

sys/dev/pci/drm/amd/include/v11_structs.h

1140

uint32_t gws_17_val; // offset: 465 (0x1D1)

sys/dev/pci/drm/amd/include/v11_structs.h

1141

uint32_t gws_18_val; // offset: 466 (0x1D2)

sys/dev/pci/drm/amd/include/v11_structs.h

1142

uint32_t gws_19_val; // offset: 467 (0x1D3)

sys/dev/pci/drm/amd/include/v11_structs.h

1143

uint32_t gws_20_val; // offset: 468 (0x1D4)

sys/dev/pci/drm/amd/include/v11_structs.h

1144

uint32_t gws_21_val; // offset: 469 (0x1D5)

sys/dev/pci/drm/amd/include/v11_structs.h

1145

uint32_t gws_22_val; // offset: 470 (0x1D6)

sys/dev/pci/drm/amd/include/v11_structs.h

1146

uint32_t gws_23_val; // offset: 471 (0x1D7)

sys/dev/pci/drm/amd/include/v11_structs.h

1147

uint32_t gws_24_val; // offset: 472 (0x1D8)

sys/dev/pci/drm/amd/include/v11_structs.h

1148

uint32_t gws_25_val; // offset: 473 (0x1D9)

sys/dev/pci/drm/amd/include/v11_structs.h

1149

uint32_t gws_26_val; // offset: 474 (0x1DA)

sys/dev/pci/drm/amd/include/v11_structs.h

115

uint32_t cp_mqd_query_time_hi; // offset: 87 (0x57)

sys/dev/pci/drm/amd/include/v11_structs.h

1150

uint32_t gws_27_val; // offset: 475 (0x1DB)

sys/dev/pci/drm/amd/include/v11_structs.h

1151

uint32_t gws_28_val; // offset: 476 (0x1DC)

sys/dev/pci/drm/amd/include/v11_structs.h

1152

uint32_t gws_29_val; // offset: 477 (0x1DD)

sys/dev/pci/drm/amd/include/v11_structs.h

1153

uint32_t gws_30_val; // offset: 478 (0x1DE)

sys/dev/pci/drm/amd/include/v11_structs.h

1154

uint32_t gws_31_val; // offset: 479 (0x1DF)

sys/dev/pci/drm/amd/include/v11_structs.h

1155

uint32_t gws_32_val; // offset: 480 (0x1E0)

sys/dev/pci/drm/amd/include/v11_structs.h

1156

uint32_t gws_33_val; // offset: 481 (0x1E1)

sys/dev/pci/drm/amd/include/v11_structs.h

1157

uint32_t gws_34_val; // offset: 482 (0x1E2)

sys/dev/pci/drm/amd/include/v11_structs.h

1158

uint32_t gws_35_val; // offset: 483 (0x1E3)

sys/dev/pci/drm/amd/include/v11_structs.h

1159

uint32_t gws_36_val; // offset: 484 (0x1E4)

sys/dev/pci/drm/amd/include/v11_structs.h

116

uint32_t reserved_88; // offset: 88 (0x58)

sys/dev/pci/drm/amd/include/v11_structs.h

1160

uint32_t gws_37_val; // offset: 485 (0x1E5)

sys/dev/pci/drm/amd/include/v11_structs.h

1161

uint32_t gws_38_val; // offset: 486 (0x1E6)

sys/dev/pci/drm/amd/include/v11_structs.h

1162

uint32_t gws_39_val; // offset: 487 (0x1E7)

sys/dev/pci/drm/amd/include/v11_structs.h

1163

uint32_t gws_40_val; // offset: 488 (0x1E8)

sys/dev/pci/drm/amd/include/v11_structs.h

1164

uint32_t gws_41_val; // offset: 489 (0x1E9)

sys/dev/pci/drm/amd/include/v11_structs.h

1165

uint32_t gws_42_val; // offset: 490 (0x1EA)

sys/dev/pci/drm/amd/include/v11_structs.h

1166

uint32_t gws_43_val; // offset: 491 (0x1EB)

sys/dev/pci/drm/amd/include/v11_structs.h

1167

uint32_t gws_44_val; // offset: 492 (0x1EC)

sys/dev/pci/drm/amd/include/v11_structs.h

1168

uint32_t gws_45_val; // offset: 493 (0x1ED)

sys/dev/pci/drm/amd/include/v11_structs.h

1169

uint32_t gws_46_val; // offset: 494 (0x1EE)

sys/dev/pci/drm/amd/include/v11_structs.h

117

uint32_t reserved_89; // offset: 89 (0x59)

sys/dev/pci/drm/amd/include/v11_structs.h

1170

uint32_t gws_47_val; // offset: 495 (0x1EF)

sys/dev/pci/drm/amd/include/v11_structs.h

1171

uint32_t gws_48_val; // offset: 496 (0x1F0)

sys/dev/pci/drm/amd/include/v11_structs.h

1172

uint32_t gws_49_val; // offset: 497 (0x1F1)

sys/dev/pci/drm/amd/include/v11_structs.h

1173

uint32_t gws_50_val; // offset: 498 (0x1F2)

sys/dev/pci/drm/amd/include/v11_structs.h

1174

uint32_t gws_51_val; // offset: 499 (0x1F3)

sys/dev/pci/drm/amd/include/v11_structs.h

1175

uint32_t gws_52_val; // offset: 500 (0x1F4)

sys/dev/pci/drm/amd/include/v11_structs.h

1176

uint32_t gws_53_val; // offset: 501 (0x1F5)

sys/dev/pci/drm/amd/include/v11_structs.h

1177

uint32_t gws_54_val; // offset: 502 (0x1F6)

sys/dev/pci/drm/amd/include/v11_structs.h

1178

uint32_t gws_55_val; // offset: 503 (0x1F7)

sys/dev/pci/drm/amd/include/v11_structs.h

1179

uint32_t gws_56_val; // offset: 504 (0x1F8)

sys/dev/pci/drm/amd/include/v11_structs.h

118

uint32_t reserved_90; // offset: 90 (0x5A)

sys/dev/pci/drm/amd/include/v11_structs.h

1180

uint32_t gws_57_val; // offset: 505 (0x1F9)

sys/dev/pci/drm/amd/include/v11_structs.h

1181

uint32_t gws_58_val; // offset: 506 (0x1FA)

sys/dev/pci/drm/amd/include/v11_structs.h

1182

uint32_t gws_59_val; // offset: 507 (0x1FB)

sys/dev/pci/drm/amd/include/v11_structs.h

1183

uint32_t gws_60_val; // offset: 508 (0x1FC)

sys/dev/pci/drm/amd/include/v11_structs.h

1184

uint32_t gws_61_val; // offset: 509 (0x1FD)

sys/dev/pci/drm/amd/include/v11_structs.h

1185

uint32_t gws_62_val; // offset: 510 (0x1FE)

sys/dev/pci/drm/amd/include/v11_structs.h

1186

uint32_t gws_63_val; // offset: 511 (0x1FF)

sys/dev/pci/drm/amd/include/v11_structs.h

119

uint32_t reserved_91; // offset: 91 (0x5B)

sys/dev/pci/drm/amd/include/v11_structs.h

120

uint32_t cp_mqd_query_wave_count; // offset: 92 (0x5C)

sys/dev/pci/drm/amd/include/v11_structs.h

121

uint32_t cp_mqd_query_gfx_hqd_rptr; // offset: 93 (0x5D)

sys/dev/pci/drm/amd/include/v11_structs.h

122

uint32_t cp_mqd_query_gfx_hqd_wptr; // offset: 94 (0x5E)

sys/dev/pci/drm/amd/include/v11_structs.h

123

uint32_t cp_mqd_query_gfx_hqd_offset; // offset: 95 (0x5F)

sys/dev/pci/drm/amd/include/v11_structs.h

124

uint32_t reserved_96; // offset: 96 (0x60)

sys/dev/pci/drm/amd/include/v11_structs.h

125

uint32_t reserved_97; // offset: 97 (0x61)

sys/dev/pci/drm/amd/include/v11_structs.h

126

uint32_t reserved_98; // offset: 98 (0x62)

sys/dev/pci/drm/amd/include/v11_structs.h

127

uint32_t reserved_99; // offset: 99 (0x63)

sys/dev/pci/drm/amd/include/v11_structs.h

128

uint32_t reserved_100; // offset: 100 (0x64)

sys/dev/pci/drm/amd/include/v11_structs.h

129

uint32_t reserved_101; // offset: 101 (0x65)

sys/dev/pci/drm/amd/include/v11_structs.h

130

uint32_t reserved_102; // offset: 102 (0x66)

sys/dev/pci/drm/amd/include/v11_structs.h

131

uint32_t reserved_103; // offset: 103 (0x67)

sys/dev/pci/drm/amd/include/v11_structs.h

132

uint32_t control_buf_addr_lo; // offset: 104 (0x68)

sys/dev/pci/drm/amd/include/v11_structs.h

133

uint32_t control_buf_addr_hi; // offset: 105 (0x69)

sys/dev/pci/drm/amd/include/v11_structs.h

134

uint32_t disable_queue; // offset: 106 (0x6A)

sys/dev/pci/drm/amd/include/v11_structs.h

135

uint32_t reserved_107; // offset: 107 (0x6B)

sys/dev/pci/drm/amd/include/v11_structs.h

136

uint32_t reserved_108; // offset: 108 (0x6C)

sys/dev/pci/drm/amd/include/v11_structs.h

137

uint32_t reserved_109; // offset: 109 (0x6D)

sys/dev/pci/drm/amd/include/v11_structs.h

138

uint32_t reserved_110; // offset: 110 (0x6E)

sys/dev/pci/drm/amd/include/v11_structs.h

139

uint32_t reserved_111; // offset: 111 (0x6F)

sys/dev/pci/drm/amd/include/v11_structs.h

140

uint32_t reserved_112; // offset: 112 (0x70)

sys/dev/pci/drm/amd/include/v11_structs.h

141

uint32_t reserved_113; // offset: 113 (0x71)

sys/dev/pci/drm/amd/include/v11_structs.h

142

uint32_t reserved_114; // offset: 114 (0x72)

sys/dev/pci/drm/amd/include/v11_structs.h

143

uint32_t reserved_115; // offset: 115 (0x73)

sys/dev/pci/drm/amd/include/v11_structs.h

144

uint32_t reserved_116; // offset: 116 (0x74)

sys/dev/pci/drm/amd/include/v11_structs.h

145

uint32_t reserved_117; // offset: 117 (0x75)

sys/dev/pci/drm/amd/include/v11_structs.h

146

uint32_t reserved_118; // offset: 118 (0x76)

sys/dev/pci/drm/amd/include/v11_structs.h

147

uint32_t reserved_119; // offset: 119 (0x77)

sys/dev/pci/drm/amd/include/v11_structs.h

148

uint32_t reserved_120; // offset: 120 (0x78)

sys/dev/pci/drm/amd/include/v11_structs.h

149

uint32_t reserved_121; // offset: 121 (0x79)

sys/dev/pci/drm/amd/include/v11_structs.h

150

uint32_t reserved_122; // offset: 122 (0x7A)

sys/dev/pci/drm/amd/include/v11_structs.h

151

uint32_t reserved_123; // offset: 123 (0x7B)

sys/dev/pci/drm/amd/include/v11_structs.h

152

uint32_t reserved_124; // offset: 124 (0x7C)

sys/dev/pci/drm/amd/include/v11_structs.h

153

uint32_t reserved_125; // offset: 125 (0x7D)

sys/dev/pci/drm/amd/include/v11_structs.h

154

uint32_t reserved_126; // offset: 126 (0x7E)

sys/dev/pci/drm/amd/include/v11_structs.h

155

uint32_t reserved_127; // offset: 127 (0x7F)

sys/dev/pci/drm/amd/include/v11_structs.h

156

uint32_t cp_mqd_base_addr; // offset: 128 (0x80)

sys/dev/pci/drm/amd/include/v11_structs.h

157

uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81)

sys/dev/pci/drm/amd/include/v11_structs.h

158

uint32_t cp_gfx_hqd_active; // offset: 130 (0x82)

sys/dev/pci/drm/amd/include/v11_structs.h

159

uint32_t cp_gfx_hqd_vmid; // offset: 131 (0x83)

sys/dev/pci/drm/amd/include/v11_structs.h

160

uint32_t reserved_131; // offset: 132 (0x84)

sys/dev/pci/drm/amd/include/v11_structs.h

161

uint32_t reserved_132; // offset: 133 (0x85)

sys/dev/pci/drm/amd/include/v11_structs.h

162

uint32_t cp_gfx_hqd_queue_priority; // offset: 134 (0x86)

sys/dev/pci/drm/amd/include/v11_structs.h

163

uint32_t cp_gfx_hqd_quantum; // offset: 135 (0x87)

sys/dev/pci/drm/amd/include/v11_structs.h

164

uint32_t cp_gfx_hqd_base; // offset: 136 (0x88)

sys/dev/pci/drm/amd/include/v11_structs.h

165

uint32_t cp_gfx_hqd_base_hi; // offset: 137 (0x89)

sys/dev/pci/drm/amd/include/v11_structs.h

166

uint32_t cp_gfx_hqd_rptr; // offset: 138 (0x8A)

sys/dev/pci/drm/amd/include/v11_structs.h

167

uint32_t cp_gfx_hqd_rptr_addr; // offset: 139 (0x8B)

sys/dev/pci/drm/amd/include/v11_structs.h

168

uint32_t cp_gfx_hqd_rptr_addr_hi; // offset: 140 (0x8C)

sys/dev/pci/drm/amd/include/v11_structs.h

169

uint32_t cp_rb_wptr_poll_addr_lo; // offset: 141 (0x8D)

sys/dev/pci/drm/amd/include/v11_structs.h

170

uint32_t cp_rb_wptr_poll_addr_hi; // offset: 142 (0x8E)

sys/dev/pci/drm/amd/include/v11_structs.h

171

uint32_t cp_rb_doorbell_control; // offset: 143 (0x8F)

sys/dev/pci/drm/amd/include/v11_structs.h

172

uint32_t cp_gfx_hqd_offset; // offset: 144 (0x90)

sys/dev/pci/drm/amd/include/v11_structs.h

173

uint32_t cp_gfx_hqd_cntl; // offset: 145 (0x91)

sys/dev/pci/drm/amd/include/v11_structs.h

174

uint32_t reserved_146; // offset: 146 (0x92)

sys/dev/pci/drm/amd/include/v11_structs.h

175

uint32_t reserved_147; // offset: 147 (0x93)

sys/dev/pci/drm/amd/include/v11_structs.h

176

uint32_t cp_gfx_hqd_csmd_rptr; // offset: 148 (0x94)

sys/dev/pci/drm/amd/include/v11_structs.h

177

uint32_t cp_gfx_hqd_wptr; // offset: 149 (0x95)

sys/dev/pci/drm/amd/include/v11_structs.h

178

uint32_t cp_gfx_hqd_wptr_hi; // offset: 150 (0x96)

sys/dev/pci/drm/amd/include/v11_structs.h

179

uint32_t reserved_151; // offset: 151 (0x97)

sys/dev/pci/drm/amd/include/v11_structs.h

180

uint32_t reserved_152; // offset: 152 (0x98)

sys/dev/pci/drm/amd/include/v11_structs.h

181

uint32_t reserved_153; // offset: 153 (0x99)

sys/dev/pci/drm/amd/include/v11_structs.h

182

uint32_t reserved_154; // offset: 154 (0x9A)

sys/dev/pci/drm/amd/include/v11_structs.h

183

uint32_t reserved_155; // offset: 155 (0x9B)

sys/dev/pci/drm/amd/include/v11_structs.h

184

uint32_t cp_gfx_hqd_mapped; // offset: 156 (0x9C)

sys/dev/pci/drm/amd/include/v11_structs.h

185

uint32_t cp_gfx_hqd_que_mgr_control; // offset: 157 (0x9D)

sys/dev/pci/drm/amd/include/v11_structs.h

186

uint32_t reserved_158; // offset: 158 (0x9E)

sys/dev/pci/drm/amd/include/v11_structs.h

187

uint32_t reserved_159; // offset: 159 (0x9F)

sys/dev/pci/drm/amd/include/v11_structs.h

188

uint32_t cp_gfx_hqd_hq_status0; // offset: 160 (0xA0)

sys/dev/pci/drm/amd/include/v11_structs.h

189

uint32_t cp_gfx_hqd_hq_control0; // offset: 161 (0xA1)

sys/dev/pci/drm/amd/include/v11_structs.h

190

uint32_t cp_gfx_mqd_control; // offset: 162 (0xA2)

sys/dev/pci/drm/amd/include/v11_structs.h

191

uint32_t reserved_163; // offset: 163 (0xA3)

sys/dev/pci/drm/amd/include/v11_structs.h

192

uint32_t reserved_164; // offset: 164 (0xA4)

sys/dev/pci/drm/amd/include/v11_structs.h

193

uint32_t reserved_165; // offset: 165 (0xA5)

sys/dev/pci/drm/amd/include/v11_structs.h

194

uint32_t reserved_166; // offset: 166 (0xA6)

sys/dev/pci/drm/amd/include/v11_structs.h

195

uint32_t reserved_167; // offset: 167 (0xA7)

sys/dev/pci/drm/amd/include/v11_structs.h

196

uint32_t reserved_168; // offset: 168 (0xA8)

sys/dev/pci/drm/amd/include/v11_structs.h

197

uint32_t reserved_169; // offset: 169 (0xA9)

sys/dev/pci/drm/amd/include/v11_structs.h

198

uint32_t cp_num_prim_needed_count0_lo; // offset: 170 (0xAA)

sys/dev/pci/drm/amd/include/v11_structs.h

199

uint32_t cp_num_prim_needed_count0_hi; // offset: 171 (0xAB)

sys/dev/pci/drm/amd/include/v11_structs.h

200

uint32_t cp_num_prim_needed_count1_lo; // offset: 172 (0xAC)

sys/dev/pci/drm/amd/include/v11_structs.h

201

uint32_t cp_num_prim_needed_count1_hi; // offset: 173 (0xAD)

sys/dev/pci/drm/amd/include/v11_structs.h

202

uint32_t cp_num_prim_needed_count2_lo; // offset: 174 (0xAE)

sys/dev/pci/drm/amd/include/v11_structs.h

203

uint32_t cp_num_prim_needed_count2_hi; // offset: 175 (0xAF)

sys/dev/pci/drm/amd/include/v11_structs.h

204

uint32_t cp_num_prim_needed_count3_lo; // offset: 176 (0xB0)

sys/dev/pci/drm/amd/include/v11_structs.h

205

uint32_t cp_num_prim_needed_count3_hi; // offset: 177 (0xB1)

sys/dev/pci/drm/amd/include/v11_structs.h

206

uint32_t cp_num_prim_written_count0_lo; // offset: 178 (0xB2)

sys/dev/pci/drm/amd/include/v11_structs.h

207

uint32_t cp_num_prim_written_count0_hi; // offset: 179 (0xB3)

sys/dev/pci/drm/amd/include/v11_structs.h

208

uint32_t cp_num_prim_written_count1_lo; // offset: 180 (0xB4)

sys/dev/pci/drm/amd/include/v11_structs.h

209

uint32_t cp_num_prim_written_count1_hi; // offset: 181 (0xB5)

sys/dev/pci/drm/amd/include/v11_structs.h

210

uint32_t cp_num_prim_written_count2_lo; // offset: 182 (0xB6)

sys/dev/pci/drm/amd/include/v11_structs.h

211

uint32_t cp_num_prim_written_count2_hi; // offset: 183 (0xB7)

sys/dev/pci/drm/amd/include/v11_structs.h

212

uint32_t cp_num_prim_written_count3_lo; // offset: 184 (0xB8)

sys/dev/pci/drm/amd/include/v11_structs.h

213

uint32_t cp_num_prim_written_count3_hi; // offset: 185 (0xB9)

sys/dev/pci/drm/amd/include/v11_structs.h

214

uint32_t reserved_186; // offset: 186 (0xBA)

sys/dev/pci/drm/amd/include/v11_structs.h

215

uint32_t reserved_187; // offset: 187 (0xBB)

sys/dev/pci/drm/amd/include/v11_structs.h

216

uint32_t reserved_188; // offset: 188 (0xBC)

sys/dev/pci/drm/amd/include/v11_structs.h

217

uint32_t reserved_189; // offset: 189 (0xBD)

sys/dev/pci/drm/amd/include/v11_structs.h

218

uint32_t mp1_smn_fps_cnt; // offset: 190 (0xBE)

sys/dev/pci/drm/amd/include/v11_structs.h

219

uint32_t sq_thread_trace_buf0_base; // offset: 191 (0xBF)

sys/dev/pci/drm/amd/include/v11_structs.h

220

uint32_t sq_thread_trace_buf0_size; // offset: 192 (0xC0)

sys/dev/pci/drm/amd/include/v11_structs.h

221

uint32_t sq_thread_trace_buf1_base; // offset: 193 (0xC1)

sys/dev/pci/drm/amd/include/v11_structs.h

222

uint32_t sq_thread_trace_buf1_size; // offset: 194 (0xC2)

sys/dev/pci/drm/amd/include/v11_structs.h

223

uint32_t sq_thread_trace_wptr; // offset: 195 (0xC3)

sys/dev/pci/drm/amd/include/v11_structs.h

224

uint32_t sq_thread_trace_mask; // offset: 196 (0xC4)

sys/dev/pci/drm/amd/include/v11_structs.h

225

uint32_t sq_thread_trace_token_mask; // offset: 197 (0xC5)

sys/dev/pci/drm/amd/include/v11_structs.h

226

uint32_t sq_thread_trace_ctrl; // offset: 198 (0xC6)

sys/dev/pci/drm/amd/include/v11_structs.h

227

uint32_t sq_thread_trace_status; // offset: 199 (0xC7)

sys/dev/pci/drm/amd/include/v11_structs.h

228

uint32_t sq_thread_trace_dropped_cntr; // offset: 200 (0xC8)

sys/dev/pci/drm/amd/include/v11_structs.h

229

uint32_t sq_thread_trace_finish_done_debug; // offset: 201 (0xC9)

sys/dev/pci/drm/amd/include/v11_structs.h

230

uint32_t sq_thread_trace_gfx_draw_cntr; // offset: 202 (0xCA)

sys/dev/pci/drm/amd/include/v11_structs.h

231

uint32_t sq_thread_trace_gfx_marker_cntr; // offset: 203 (0xCB)

sys/dev/pci/drm/amd/include/v11_structs.h

232

uint32_t sq_thread_trace_hp3d_draw_cntr; // offset: 204 (0xCC)

sys/dev/pci/drm/amd/include/v11_structs.h

233

uint32_t sq_thread_trace_hp3d_marker_cntr; // offset: 205 (0xCD)

sys/dev/pci/drm/amd/include/v11_structs.h

234

uint32_t reserved_206; // offset: 206 (0xCE)

sys/dev/pci/drm/amd/include/v11_structs.h

235

uint32_t reserved_207; // offset: 207 (0xCF)

sys/dev/pci/drm/amd/include/v11_structs.h

236

uint32_t cp_sc_psinvoc_count0_lo; // offset: 208 (0xD0)

sys/dev/pci/drm/amd/include/v11_structs.h

237

uint32_t cp_sc_psinvoc_count0_hi; // offset: 209 (0xD1)

sys/dev/pci/drm/amd/include/v11_structs.h

238

uint32_t cp_pa_cprim_count_lo; // offset: 210 (0xD2)

sys/dev/pci/drm/amd/include/v11_structs.h

239

uint32_t cp_pa_cprim_count_hi; // offset: 211 (0xD3)

sys/dev/pci/drm/amd/include/v11_structs.h

240

uint32_t cp_pa_cinvoc_count_lo; // offset: 212 (0xD4)

sys/dev/pci/drm/amd/include/v11_structs.h

241

uint32_t cp_pa_cinvoc_count_hi; // offset: 213 (0xD5)

sys/dev/pci/drm/amd/include/v11_structs.h

242

uint32_t cp_vgt_vsinvoc_count_lo; // offset: 214 (0xD6)

sys/dev/pci/drm/amd/include/v11_structs.h

243

uint32_t cp_vgt_vsinvoc_count_hi; // offset: 215 (0xD7)

sys/dev/pci/drm/amd/include/v11_structs.h

244

uint32_t cp_vgt_gsinvoc_count_lo; // offset: 216 (0xD8)

sys/dev/pci/drm/amd/include/v11_structs.h

245

uint32_t cp_vgt_gsinvoc_count_hi; // offset: 217 (0xD9)

sys/dev/pci/drm/amd/include/v11_structs.h

246

uint32_t cp_vgt_gsprim_count_lo; // offset: 218 (0xDA)

sys/dev/pci/drm/amd/include/v11_structs.h

247

uint32_t cp_vgt_gsprim_count_hi; // offset: 219 (0xDB)

sys/dev/pci/drm/amd/include/v11_structs.h

248

uint32_t cp_vgt_iaprim_count_lo; // offset: 220 (0xDC)

sys/dev/pci/drm/amd/include/v11_structs.h

249

uint32_t cp_vgt_iaprim_count_hi; // offset: 221 (0xDD)

sys/dev/pci/drm/amd/include/v11_structs.h

250

uint32_t cp_vgt_iavert_count_lo; // offset: 222 (0xDE)

sys/dev/pci/drm/amd/include/v11_structs.h

251

uint32_t cp_vgt_iavert_count_hi; // offset: 223 (0xDF)

sys/dev/pci/drm/amd/include/v11_structs.h

252

uint32_t cp_vgt_hsinvoc_count_lo; // offset: 224 (0xE0)

sys/dev/pci/drm/amd/include/v11_structs.h

253

uint32_t cp_vgt_hsinvoc_count_hi; // offset: 225 (0xE1)

sys/dev/pci/drm/amd/include/v11_structs.h

254

uint32_t cp_vgt_dsinvoc_count_lo; // offset: 226 (0xE2)

sys/dev/pci/drm/amd/include/v11_structs.h

255

uint32_t cp_vgt_dsinvoc_count_hi; // offset: 227 (0xE3)

sys/dev/pci/drm/amd/include/v11_structs.h

256

uint32_t cp_vgt_csinvoc_count_lo; // offset: 228 (0xE4)

sys/dev/pci/drm/amd/include/v11_structs.h

257

uint32_t cp_vgt_csinvoc_count_hi; // offset: 229 (0xE5)

sys/dev/pci/drm/amd/include/v11_structs.h

258

uint32_t reserved_230; // offset: 230 (0xE6)

sys/dev/pci/drm/amd/include/v11_structs.h

259

uint32_t reserved_231; // offset: 231 (0xE7)

sys/dev/pci/drm/amd/include/v11_structs.h

260

uint32_t reserved_232; // offset: 232 (0xE8)

sys/dev/pci/drm/amd/include/v11_structs.h

261

uint32_t reserved_233; // offset: 233 (0xE9)

sys/dev/pci/drm/amd/include/v11_structs.h

262

uint32_t reserved_234; // offset: 234 (0xEA)

sys/dev/pci/drm/amd/include/v11_structs.h

263

uint32_t reserved_235; // offset: 235 (0xEB)

sys/dev/pci/drm/amd/include/v11_structs.h

264

uint32_t reserved_236; // offset: 236 (0xEC)

sys/dev/pci/drm/amd/include/v11_structs.h

265

uint32_t reserved_237; // offset: 237 (0xED)

sys/dev/pci/drm/amd/include/v11_structs.h

266

uint32_t reserved_238; // offset: 238 (0xEE)

sys/dev/pci/drm/amd/include/v11_structs.h

267

uint32_t reserved_239; // offset: 239 (0xEF)

sys/dev/pci/drm/amd/include/v11_structs.h

268

uint32_t reserved_240; // offset: 240 (0xF0)

sys/dev/pci/drm/amd/include/v11_structs.h

269

uint32_t reserved_241; // offset: 241 (0xF1)

sys/dev/pci/drm/amd/include/v11_structs.h

270

uint32_t reserved_242; // offset: 242 (0xF2)

sys/dev/pci/drm/amd/include/v11_structs.h

271

uint32_t reserved_243; // offset: 243 (0xF3)

sys/dev/pci/drm/amd/include/v11_structs.h

272

uint32_t reserved_244; // offset: 244 (0xF4)

sys/dev/pci/drm/amd/include/v11_structs.h

273

uint32_t reserved_245; // offset: 245 (0xF5)

sys/dev/pci/drm/amd/include/v11_structs.h

274

uint32_t reserved_246; // offset: 246 (0xF6)

sys/dev/pci/drm/amd/include/v11_structs.h

275

uint32_t reserved_247; // offset: 247 (0xF7)

sys/dev/pci/drm/amd/include/v11_structs.h

276

uint32_t reserved_248; // offset: 248 (0xF8)

sys/dev/pci/drm/amd/include/v11_structs.h

277

uint32_t reserved_249; // offset: 249 (0xF9)

sys/dev/pci/drm/amd/include/v11_structs.h

278

uint32_t reserved_250; // offset: 250 (0xFA)

sys/dev/pci/drm/amd/include/v11_structs.h

279

uint32_t reserved_251; // offset: 251 (0xFB)

sys/dev/pci/drm/amd/include/v11_structs.h

28

uint32_t shadow_base_lo; // offset: 0 (0x0)

sys/dev/pci/drm/amd/include/v11_structs.h

280

uint32_t reserved_252; // offset: 252 (0xFC)

sys/dev/pci/drm/amd/include/v11_structs.h

281

uint32_t reserved_253; // offset: 253 (0xFD)

sys/dev/pci/drm/amd/include/v11_structs.h

282

uint32_t reserved_254; // offset: 254 (0xFE)

sys/dev/pci/drm/amd/include/v11_structs.h

283

uint32_t reserved_255; // offset: 255 (0xFF)

sys/dev/pci/drm/amd/include/v11_structs.h

284

uint32_t reserved_256; // offset: 256 (0x100)

sys/dev/pci/drm/amd/include/v11_structs.h

285

uint32_t reserved_257; // offset: 257 (0x101)

sys/dev/pci/drm/amd/include/v11_structs.h

286

uint32_t reserved_258; // offset: 258 (0x102)

sys/dev/pci/drm/amd/include/v11_structs.h

287

uint32_t reserved_259; // offset: 259 (0x103)

sys/dev/pci/drm/amd/include/v11_structs.h

288

uint32_t reserved_260; // offset: 260 (0x104)

sys/dev/pci/drm/amd/include/v11_structs.h

289

uint32_t reserved_261; // offset: 261 (0x105)

sys/dev/pci/drm/amd/include/v11_structs.h

29

uint32_t shadow_base_hi; // offset: 1 (0x1)

sys/dev/pci/drm/amd/include/v11_structs.h

290

uint32_t reserved_262; // offset: 262 (0x106)

sys/dev/pci/drm/amd/include/v11_structs.h

291

uint32_t reserved_263; // offset: 263 (0x107)

sys/dev/pci/drm/amd/include/v11_structs.h

292

uint32_t reserved_264; // offset: 264 (0x108)

sys/dev/pci/drm/amd/include/v11_structs.h

293

uint32_t reserved_265; // offset: 265 (0x109)

sys/dev/pci/drm/amd/include/v11_structs.h

294

uint32_t reserved_266; // offset: 266 (0x10A)

sys/dev/pci/drm/amd/include/v11_structs.h

295

uint32_t reserved_267; // offset: 267 (0x10B)

sys/dev/pci/drm/amd/include/v11_structs.h

296

uint32_t vgt_strmout_buffer_filled_size_0; // offset: 268 (0x10C)

sys/dev/pci/drm/amd/include/v11_structs.h

297

uint32_t vgt_strmout_buffer_filled_size_1; // offset: 269 (0x10D)

sys/dev/pci/drm/amd/include/v11_structs.h

298

uint32_t vgt_strmout_buffer_filled_size_2; // offset: 270 (0x10E)

sys/dev/pci/drm/amd/include/v11_structs.h

299

uint32_t vgt_strmout_buffer_filled_size_3; // offset: 271 (0x10F)

sys/dev/pci/drm/amd/include/v11_structs.h

30

uint32_t gds_bkup_base_lo; // offset: 2 (0x2)

sys/dev/pci/drm/amd/include/v11_structs.h

300

uint32_t reserved_272; // offset: 272 (0x110)

sys/dev/pci/drm/amd/include/v11_structs.h

301

uint32_t reserved_273; // offset: 273 (0x111)

sys/dev/pci/drm/amd/include/v11_structs.h

302

uint32_t reserved_274; // offset: 274 (0x112)

sys/dev/pci/drm/amd/include/v11_structs.h

303

uint32_t reserved_275; // offset: 275 (0x113)

sys/dev/pci/drm/amd/include/v11_structs.h

304

uint32_t vgt_dma_max_size; // offset: 276 (0x114)

sys/dev/pci/drm/amd/include/v11_structs.h

305

uint32_t vgt_dma_num_instances; // offset: 277 (0x115)

sys/dev/pci/drm/amd/include/v11_structs.h

306

uint32_t reserved_278; // offset: 278 (0x116)

sys/dev/pci/drm/amd/include/v11_structs.h

307

uint32_t reserved_279; // offset: 279 (0x117)

sys/dev/pci/drm/amd/include/v11_structs.h

308

uint32_t reserved_280; // offset: 280 (0x118)

sys/dev/pci/drm/amd/include/v11_structs.h

309

uint32_t reserved_281; // offset: 281 (0x119)

sys/dev/pci/drm/amd/include/v11_structs.h

31

uint32_t gds_bkup_base_hi; // offset: 3 (0x3)

sys/dev/pci/drm/amd/include/v11_structs.h

310

uint32_t reserved_282; // offset: 282 (0x11A)

sys/dev/pci/drm/amd/include/v11_structs.h

311

uint32_t reserved_283; // offset: 283 (0x11B)

sys/dev/pci/drm/amd/include/v11_structs.h

312

uint32_t reserved_284; // offset: 284 (0x11C)

sys/dev/pci/drm/amd/include/v11_structs.h

313

uint32_t reserved_285; // offset: 285 (0x11D)

sys/dev/pci/drm/amd/include/v11_structs.h

314

uint32_t reserved_286; // offset: 286 (0x11E)

sys/dev/pci/drm/amd/include/v11_structs.h

315

uint32_t reserved_287; // offset: 287 (0x11F)

sys/dev/pci/drm/amd/include/v11_structs.h

316

uint32_t it_set_base_ib_addr_lo; // offset: 288 (0x120)

sys/dev/pci/drm/amd/include/v11_structs.h

317

uint32_t it_set_base_ib_addr_hi; // offset: 289 (0x121)

sys/dev/pci/drm/amd/include/v11_structs.h

318

uint32_t reserved_290; // offset: 290 (0x122)

sys/dev/pci/drm/amd/include/v11_structs.h

319

uint32_t reserved_291; // offset: 291 (0x123)

sys/dev/pci/drm/amd/include/v11_structs.h

32

uint32_t fw_work_area_base_lo; // offset: 4 (0x4)

sys/dev/pci/drm/amd/include/v11_structs.h

320

uint32_t reserved_292; // offset: 292 (0x124)

sys/dev/pci/drm/amd/include/v11_structs.h

321

uint32_t reserved_293; // offset: 293 (0x125)

sys/dev/pci/drm/amd/include/v11_structs.h

322

uint32_t reserved_294; // offset: 294 (0x126)

sys/dev/pci/drm/amd/include/v11_structs.h

323

uint32_t reserved_295; // offset: 295 (0x127)

sys/dev/pci/drm/amd/include/v11_structs.h

324

uint32_t reserved_296; // offset: 296 (0x128)

sys/dev/pci/drm/amd/include/v11_structs.h

325

uint32_t reserved_297; // offset: 297 (0x129)

sys/dev/pci/drm/amd/include/v11_structs.h

326

uint32_t reserved_298; // offset: 298 (0x12A)

sys/dev/pci/drm/amd/include/v11_structs.h

327

uint32_t reserved_299; // offset: 299 (0x12B)

sys/dev/pci/drm/amd/include/v11_structs.h

328

uint32_t reserved_300; // offset: 300 (0x12C)

sys/dev/pci/drm/amd/include/v11_structs.h

329

uint32_t reserved_301; // offset: 301 (0x12D)

sys/dev/pci/drm/amd/include/v11_structs.h

33

uint32_t fw_work_area_base_hi; // offset: 5 (0x5)

sys/dev/pci/drm/amd/include/v11_structs.h

330

uint32_t reserved_302; // offset: 302 (0x12E)

sys/dev/pci/drm/amd/include/v11_structs.h

331

uint32_t reserved_303; // offset: 303 (0x12F)

sys/dev/pci/drm/amd/include/v11_structs.h

332

uint32_t reserved_304; // offset: 304 (0x130)

sys/dev/pci/drm/amd/include/v11_structs.h

333

uint32_t reserved_305; // offset: 305 (0x131)

sys/dev/pci/drm/amd/include/v11_structs.h

334

uint32_t reserved_306; // offset: 306 (0x132)

sys/dev/pci/drm/amd/include/v11_structs.h

335

uint32_t reserved_307; // offset: 307 (0x133)

sys/dev/pci/drm/amd/include/v11_structs.h

336

uint32_t reserved_308; // offset: 308 (0x134)

sys/dev/pci/drm/amd/include/v11_structs.h

337

uint32_t reserved_309; // offset: 309 (0x135)

sys/dev/pci/drm/amd/include/v11_structs.h

338

uint32_t reserved_310; // offset: 310 (0x136)

sys/dev/pci/drm/amd/include/v11_structs.h

339

uint32_t reserved_311; // offset: 311 (0x137)

sys/dev/pci/drm/amd/include/v11_structs.h

34

uint32_t shadow_initialized; // offset: 6 (0x6)

sys/dev/pci/drm/amd/include/v11_structs.h

340

uint32_t reserved_312; // offset: 312 (0x138)

sys/dev/pci/drm/amd/include/v11_structs.h

341

uint32_t reserved_313; // offset: 313 (0x139)

sys/dev/pci/drm/amd/include/v11_structs.h

342

uint32_t reserved_314; // offset: 314 (0x13A)

sys/dev/pci/drm/amd/include/v11_structs.h

343

uint32_t reserved_315; // offset: 315 (0x13B)

sys/dev/pci/drm/amd/include/v11_structs.h

344

uint32_t reserved_316; // offset: 316 (0x13C)

sys/dev/pci/drm/amd/include/v11_structs.h

345

uint32_t reserved_317; // offset: 317 (0x13D)

sys/dev/pci/drm/amd/include/v11_structs.h

346

uint32_t reserved_318; // offset: 318 (0x13E)

sys/dev/pci/drm/amd/include/v11_structs.h

347

uint32_t reserved_319; // offset: 319 (0x13F)

sys/dev/pci/drm/amd/include/v11_structs.h

348

uint32_t reserved_320; // offset: 320 (0x140)

sys/dev/pci/drm/amd/include/v11_structs.h

349

uint32_t reserved_321; // offset: 321 (0x141)

sys/dev/pci/drm/amd/include/v11_structs.h

35

uint32_t ib_vmid; // offset: 7 (0x7)

sys/dev/pci/drm/amd/include/v11_structs.h

350

uint32_t reserved_322; // offset: 322 (0x142)

sys/dev/pci/drm/amd/include/v11_structs.h

351

uint32_t reserved_323; // offset: 323 (0x143)

sys/dev/pci/drm/amd/include/v11_structs.h

352

uint32_t reserved_324; // offset: 324 (0x144)

sys/dev/pci/drm/amd/include/v11_structs.h

353

uint32_t reserved_325; // offset: 325 (0x145)

sys/dev/pci/drm/amd/include/v11_structs.h

354

uint32_t reserved_326; // offset: 326 (0x146)

sys/dev/pci/drm/amd/include/v11_structs.h

355

uint32_t reserved_327; // offset: 327 (0x147)

sys/dev/pci/drm/amd/include/v11_structs.h

356

uint32_t reserved_328; // offset: 328 (0x148)

sys/dev/pci/drm/amd/include/v11_structs.h

357

uint32_t reserved_329; // offset: 329 (0x149)

sys/dev/pci/drm/amd/include/v11_structs.h

358

uint32_t reserved_330; // offset: 330 (0x14A)

sys/dev/pci/drm/amd/include/v11_structs.h

359

uint32_t reserved_331; // offset: 331 (0x14B)

sys/dev/pci/drm/amd/include/v11_structs.h

36

uint32_t reserved_8; // offset: 8 (0x8)

sys/dev/pci/drm/amd/include/v11_structs.h

360

uint32_t reserved_332; // offset: 332 (0x14C)

sys/dev/pci/drm/amd/include/v11_structs.h

361

uint32_t reserved_333; // offset: 333 (0x14D)

sys/dev/pci/drm/amd/include/v11_structs.h

362

uint32_t reserved_334; // offset: 334 (0x14E)

sys/dev/pci/drm/amd/include/v11_structs.h

363

uint32_t reserved_335; // offset: 335 (0x14F)

sys/dev/pci/drm/amd/include/v11_structs.h

364

uint32_t reserved_336; // offset: 336 (0x150)

sys/dev/pci/drm/amd/include/v11_structs.h

365

uint32_t reserved_337; // offset: 337 (0x151)

sys/dev/pci/drm/amd/include/v11_structs.h

366

uint32_t reserved_338; // offset: 338 (0x152)

sys/dev/pci/drm/amd/include/v11_structs.h

367

uint32_t reserved_339; // offset: 339 (0x153)

sys/dev/pci/drm/amd/include/v11_structs.h

368

uint32_t reserved_340; // offset: 340 (0x154)

sys/dev/pci/drm/amd/include/v11_structs.h

369

uint32_t reserved_341; // offset: 341 (0x155)

sys/dev/pci/drm/amd/include/v11_structs.h

37

uint32_t reserved_9; // offset: 9 (0x9)

sys/dev/pci/drm/amd/include/v11_structs.h

370

uint32_t reserved_342; // offset: 342 (0x156)

sys/dev/pci/drm/amd/include/v11_structs.h

371

uint32_t reserved_343; // offset: 343 (0x157)

sys/dev/pci/drm/amd/include/v11_structs.h

372

uint32_t reserved_344; // offset: 344 (0x158)

sys/dev/pci/drm/amd/include/v11_structs.h

373

uint32_t reserved_345; // offset: 345 (0x159)

sys/dev/pci/drm/amd/include/v11_structs.h

374

uint32_t reserved_346; // offset: 346 (0x15A)

sys/dev/pci/drm/amd/include/v11_structs.h

375

uint32_t reserved_347; // offset: 347 (0x15B)

sys/dev/pci/drm/amd/include/v11_structs.h

376

uint32_t reserved_348; // offset: 348 (0x15C)

sys/dev/pci/drm/amd/include/v11_structs.h

377

uint32_t reserved_349; // offset: 349 (0x15D)

sys/dev/pci/drm/amd/include/v11_structs.h

378

uint32_t reserved_350; // offset: 350 (0x15E)

sys/dev/pci/drm/amd/include/v11_structs.h

379

uint32_t reserved_351; // offset: 351 (0x15F)

sys/dev/pci/drm/amd/include/v11_structs.h

38

uint32_t reserved_10; // offset: 10 (0xA)

sys/dev/pci/drm/amd/include/v11_structs.h

380

uint32_t reserved_352; // offset: 352 (0x160)

sys/dev/pci/drm/amd/include/v11_structs.h

381

uint32_t reserved_353; // offset: 353 (0x161)

sys/dev/pci/drm/amd/include/v11_structs.h

382

uint32_t reserved_354; // offset: 354 (0x162)

sys/dev/pci/drm/amd/include/v11_structs.h

383

uint32_t reserved_355; // offset: 355 (0x163)

sys/dev/pci/drm/amd/include/v11_structs.h

384

uint32_t spi_shader_pgm_rsrc3_ps; // offset: 356 (0x164)

sys/dev/pci/drm/amd/include/v11_structs.h

385

uint32_t spi_shader_pgm_rsrc3_vs; // offset: 357 (0x165)

sys/dev/pci/drm/amd/include/v11_structs.h

386

uint32_t spi_shader_pgm_rsrc3_gs; // offset: 358 (0x166)

sys/dev/pci/drm/amd/include/v11_structs.h

387

uint32_t spi_shader_pgm_rsrc3_hs; // offset: 359 (0x167)

sys/dev/pci/drm/amd/include/v11_structs.h

388

uint32_t spi_shader_pgm_rsrc4_ps; // offset: 360 (0x168)

sys/dev/pci/drm/amd/include/v11_structs.h

389

uint32_t spi_shader_pgm_rsrc4_vs; // offset: 361 (0x169)

sys/dev/pci/drm/amd/include/v11_structs.h

39

uint32_t reserved_11; // offset: 11 (0xB)

sys/dev/pci/drm/amd/include/v11_structs.h

390

uint32_t spi_shader_pgm_rsrc4_gs; // offset: 362 (0x16A)

sys/dev/pci/drm/amd/include/v11_structs.h

391

uint32_t spi_shader_pgm_rsrc4_hs; // offset: 363 (0x16B)

sys/dev/pci/drm/amd/include/v11_structs.h

392

uint32_t db_occlusion_count0_low_00; // offset: 364 (0x16C)

sys/dev/pci/drm/amd/include/v11_structs.h

393

uint32_t db_occlusion_count0_hi_00; // offset: 365 (0x16D)

sys/dev/pci/drm/amd/include/v11_structs.h

394

uint32_t db_occlusion_count1_low_00; // offset: 366 (0x16E)

sys/dev/pci/drm/amd/include/v11_structs.h

395

uint32_t db_occlusion_count1_hi_00; // offset: 367 (0x16F)

sys/dev/pci/drm/amd/include/v11_structs.h

396

uint32_t db_occlusion_count2_low_00; // offset: 368 (0x170)

sys/dev/pci/drm/amd/include/v11_structs.h

397

uint32_t db_occlusion_count2_hi_00; // offset: 369 (0x171)

sys/dev/pci/drm/amd/include/v11_structs.h

398

uint32_t db_occlusion_count3_low_00; // offset: 370 (0x172)

sys/dev/pci/drm/amd/include/v11_structs.h

399

uint32_t db_occlusion_count3_hi_00; // offset: 371 (0x173)

sys/dev/pci/drm/amd/include/v11_structs.h

40

uint32_t reserved_12; // offset: 12 (0xC)

sys/dev/pci/drm/amd/include/v11_structs.h

400

uint32_t db_occlusion_count0_low_01; // offset: 372 (0x174)

sys/dev/pci/drm/amd/include/v11_structs.h

401

uint32_t db_occlusion_count0_hi_01; // offset: 373 (0x175)

sys/dev/pci/drm/amd/include/v11_structs.h

402

uint32_t db_occlusion_count1_low_01; // offset: 374 (0x176)

sys/dev/pci/drm/amd/include/v11_structs.h

403

uint32_t db_occlusion_count1_hi_01; // offset: 375 (0x177)

sys/dev/pci/drm/amd/include/v11_structs.h

404

uint32_t db_occlusion_count2_low_01; // offset: 376 (0x178)

sys/dev/pci/drm/amd/include/v11_structs.h

405

uint32_t db_occlusion_count2_hi_01; // offset: 377 (0x179)

sys/dev/pci/drm/amd/include/v11_structs.h

406

uint32_t db_occlusion_count3_low_01; // offset: 378 (0x17A)

sys/dev/pci/drm/amd/include/v11_structs.h

407

uint32_t db_occlusion_count3_hi_01; // offset: 379 (0x17B)

sys/dev/pci/drm/amd/include/v11_structs.h

408

uint32_t db_occlusion_count0_low_02; // offset: 380 (0x17C)

sys/dev/pci/drm/amd/include/v11_structs.h

409

uint32_t db_occlusion_count0_hi_02; // offset: 381 (0x17D)

sys/dev/pci/drm/amd/include/v11_structs.h

41

uint32_t reserved_13; // offset: 13 (0xD)

sys/dev/pci/drm/amd/include/v11_structs.h

410

uint32_t db_occlusion_count1_low_02; // offset: 382 (0x17E)

sys/dev/pci/drm/amd/include/v11_structs.h

411

uint32_t db_occlusion_count1_hi_02; // offset: 383 (0x17F)

sys/dev/pci/drm/amd/include/v11_structs.h

412

uint32_t db_occlusion_count2_low_02; // offset: 384 (0x180)

sys/dev/pci/drm/amd/include/v11_structs.h

413

uint32_t db_occlusion_count2_hi_02; // offset: 385 (0x181)

sys/dev/pci/drm/amd/include/v11_structs.h

414

uint32_t db_occlusion_count3_low_02; // offset: 386 (0x182)

sys/dev/pci/drm/amd/include/v11_structs.h

415

uint32_t db_occlusion_count3_hi_02; // offset: 387 (0x183)

sys/dev/pci/drm/amd/include/v11_structs.h

416

uint32_t db_occlusion_count0_low_03; // offset: 388 (0x184)

sys/dev/pci/drm/amd/include/v11_structs.h

417

uint32_t db_occlusion_count0_hi_03; // offset: 389 (0x185)

sys/dev/pci/drm/amd/include/v11_structs.h

418

uint32_t db_occlusion_count1_low_03; // offset: 390 (0x186)

sys/dev/pci/drm/amd/include/v11_structs.h

419

uint32_t db_occlusion_count1_hi_03; // offset: 391 (0x187)

sys/dev/pci/drm/amd/include/v11_structs.h

42

uint32_t reserved_14; // offset: 14 (0xE)

sys/dev/pci/drm/amd/include/v11_structs.h

420

uint32_t db_occlusion_count2_low_03; // offset: 392 (0x188)

sys/dev/pci/drm/amd/include/v11_structs.h

421

uint32_t db_occlusion_count2_hi_03; // offset: 393 (0x189)

sys/dev/pci/drm/amd/include/v11_structs.h

422

uint32_t db_occlusion_count3_low_03; // offset: 394 (0x18A)

sys/dev/pci/drm/amd/include/v11_structs.h

423

uint32_t db_occlusion_count3_hi_03; // offset: 395 (0x18B)

sys/dev/pci/drm/amd/include/v11_structs.h

424

uint32_t db_occlusion_count0_low_04; // offset: 396 (0x18C)

sys/dev/pci/drm/amd/include/v11_structs.h

425

uint32_t db_occlusion_count0_hi_04; // offset: 397 (0x18D)

sys/dev/pci/drm/amd/include/v11_structs.h

426

uint32_t db_occlusion_count1_low_04; // offset: 398 (0x18E)

sys/dev/pci/drm/amd/include/v11_structs.h

427

uint32_t db_occlusion_count1_hi_04; // offset: 399 (0x18F)

sys/dev/pci/drm/amd/include/v11_structs.h

428

uint32_t db_occlusion_count2_low_04; // offset: 400 (0x190)

sys/dev/pci/drm/amd/include/v11_structs.h

429

uint32_t db_occlusion_count2_hi_04; // offset: 401 (0x191)

sys/dev/pci/drm/amd/include/v11_structs.h

43

uint32_t reserved_15; // offset: 15 (0xF)

sys/dev/pci/drm/amd/include/v11_structs.h

430

uint32_t db_occlusion_count3_low_04; // offset: 402 (0x192)

sys/dev/pci/drm/amd/include/v11_structs.h

431

uint32_t db_occlusion_count3_hi_04; // offset: 403 (0x193)

sys/dev/pci/drm/amd/include/v11_structs.h

432

uint32_t db_occlusion_count0_low_05; // offset: 404 (0x194)

sys/dev/pci/drm/amd/include/v11_structs.h

433

uint32_t db_occlusion_count0_hi_05; // offset: 405 (0x195)

sys/dev/pci/drm/amd/include/v11_structs.h

434

uint32_t db_occlusion_count1_low_05; // offset: 406 (0x196)

sys/dev/pci/drm/amd/include/v11_structs.h

435

uint32_t db_occlusion_count1_hi_05; // offset: 407 (0x197)

sys/dev/pci/drm/amd/include/v11_structs.h

436

uint32_t db_occlusion_count2_low_05; // offset: 408 (0x198)

sys/dev/pci/drm/amd/include/v11_structs.h

437

uint32_t db_occlusion_count2_hi_05; // offset: 409 (0x199)

sys/dev/pci/drm/amd/include/v11_structs.h

438

uint32_t db_occlusion_count3_low_05; // offset: 410 (0x19A)

sys/dev/pci/drm/amd/include/v11_structs.h

439

uint32_t db_occlusion_count3_hi_05; // offset: 411 (0x19B)

sys/dev/pci/drm/amd/include/v11_structs.h

44

uint32_t reserved_16; // offset: 16 (0x10)

sys/dev/pci/drm/amd/include/v11_structs.h

440

uint32_t db_occlusion_count0_low_06; // offset: 412 (0x19C)

sys/dev/pci/drm/amd/include/v11_structs.h

441

uint32_t db_occlusion_count0_hi_06; // offset: 413 (0x19D)

sys/dev/pci/drm/amd/include/v11_structs.h

442

uint32_t db_occlusion_count1_low_06; // offset: 414 (0x19E)

sys/dev/pci/drm/amd/include/v11_structs.h

443

uint32_t db_occlusion_count1_hi_06; // offset: 415 (0x19F)

sys/dev/pci/drm/amd/include/v11_structs.h

444

uint32_t db_occlusion_count2_low_06; // offset: 416 (0x1A0)

sys/dev/pci/drm/amd/include/v11_structs.h

445

uint32_t db_occlusion_count2_hi_06; // offset: 417 (0x1A1)

sys/dev/pci/drm/amd/include/v11_structs.h

446

uint32_t db_occlusion_count3_low_06; // offset: 418 (0x1A2)

sys/dev/pci/drm/amd/include/v11_structs.h

447

uint32_t db_occlusion_count3_hi_06; // offset: 419 (0x1A3)

sys/dev/pci/drm/amd/include/v11_structs.h

448

uint32_t db_occlusion_count0_low_07; // offset: 420 (0x1A4)

sys/dev/pci/drm/amd/include/v11_structs.h

449

uint32_t db_occlusion_count0_hi_07; // offset: 421 (0x1A5)

sys/dev/pci/drm/amd/include/v11_structs.h

45

uint32_t reserved_17; // offset: 17 (0x11)

sys/dev/pci/drm/amd/include/v11_structs.h

450

uint32_t db_occlusion_count1_low_07; // offset: 422 (0x1A6)

sys/dev/pci/drm/amd/include/v11_structs.h

451

uint32_t db_occlusion_count1_hi_07; // offset: 423 (0x1A7)

sys/dev/pci/drm/amd/include/v11_structs.h

452

uint32_t db_occlusion_count2_low_07; // offset: 424 (0x1A8)

sys/dev/pci/drm/amd/include/v11_structs.h

453

uint32_t db_occlusion_count2_hi_07; // offset: 425 (0x1A9)

sys/dev/pci/drm/amd/include/v11_structs.h

454

uint32_t db_occlusion_count3_low_07; // offset: 426 (0x1AA)

sys/dev/pci/drm/amd/include/v11_structs.h

455

uint32_t db_occlusion_count3_hi_07; // offset: 427 (0x1AB)

sys/dev/pci/drm/amd/include/v11_structs.h

456

uint32_t db_occlusion_count0_low_10; // offset: 428 (0x1AC)

sys/dev/pci/drm/amd/include/v11_structs.h

457

uint32_t db_occlusion_count0_hi_10; // offset: 429 (0x1AD)

sys/dev/pci/drm/amd/include/v11_structs.h

458

uint32_t db_occlusion_count1_low_10; // offset: 430 (0x1AE)

sys/dev/pci/drm/amd/include/v11_structs.h

459

uint32_t db_occlusion_count1_hi_10; // offset: 431 (0x1AF)

sys/dev/pci/drm/amd/include/v11_structs.h

46

uint32_t reserved_18; // offset: 18 (0x12)

sys/dev/pci/drm/amd/include/v11_structs.h

460

uint32_t db_occlusion_count2_low_10; // offset: 432 (0x1B0)

sys/dev/pci/drm/amd/include/v11_structs.h

461

uint32_t db_occlusion_count2_hi_10; // offset: 433 (0x1B1)

sys/dev/pci/drm/amd/include/v11_structs.h

462

uint32_t db_occlusion_count3_low_10; // offset: 434 (0x1B2)

sys/dev/pci/drm/amd/include/v11_structs.h

463

uint32_t db_occlusion_count3_hi_10; // offset: 435 (0x1B3)

sys/dev/pci/drm/amd/include/v11_structs.h

464

uint32_t db_occlusion_count0_low_11; // offset: 436 (0x1B4)

sys/dev/pci/drm/amd/include/v11_structs.h

465

uint32_t db_occlusion_count0_hi_11; // offset: 437 (0x1B5)

sys/dev/pci/drm/amd/include/v11_structs.h

466

uint32_t db_occlusion_count1_low_11; // offset: 438 (0x1B6)

sys/dev/pci/drm/amd/include/v11_structs.h

467

uint32_t db_occlusion_count1_hi_11; // offset: 439 (0x1B7)

sys/dev/pci/drm/amd/include/v11_structs.h

468

uint32_t db_occlusion_count2_low_11; // offset: 440 (0x1B8)

sys/dev/pci/drm/amd/include/v11_structs.h

469

uint32_t db_occlusion_count2_hi_11; // offset: 441 (0x1B9)

sys/dev/pci/drm/amd/include/v11_structs.h

47

uint32_t reserved_19; // offset: 19 (0x13)

sys/dev/pci/drm/amd/include/v11_structs.h

470

uint32_t db_occlusion_count3_low_11; // offset: 442 (0x1BA)

sys/dev/pci/drm/amd/include/v11_structs.h

471

uint32_t db_occlusion_count3_hi_11; // offset: 443 (0x1BB)

sys/dev/pci/drm/amd/include/v11_structs.h

472

uint32_t db_occlusion_count0_low_12; // offset: 444 (0x1BC)

sys/dev/pci/drm/amd/include/v11_structs.h

473

uint32_t db_occlusion_count0_hi_12; // offset: 445 (0x1BD)

sys/dev/pci/drm/amd/include/v11_structs.h

474

uint32_t db_occlusion_count1_low_12; // offset: 446 (0x1BE)

sys/dev/pci/drm/amd/include/v11_structs.h

475

uint32_t db_occlusion_count1_hi_12; // offset: 447 (0x1BF)

sys/dev/pci/drm/amd/include/v11_structs.h

476

uint32_t db_occlusion_count2_low_12; // offset: 448 (0x1C0)

sys/dev/pci/drm/amd/include/v11_structs.h

477

uint32_t db_occlusion_count2_hi_12; // offset: 449 (0x1C1)

sys/dev/pci/drm/amd/include/v11_structs.h

478

uint32_t db_occlusion_count3_low_12; // offset: 450 (0x1C2)

sys/dev/pci/drm/amd/include/v11_structs.h

479

uint32_t db_occlusion_count3_hi_12; // offset: 451 (0x1C3)

sys/dev/pci/drm/amd/include/v11_structs.h

48

uint32_t reserved_20; // offset: 20 (0x14)

sys/dev/pci/drm/amd/include/v11_structs.h

480

uint32_t db_occlusion_count0_low_13; // offset: 452 (0x1C4)

sys/dev/pci/drm/amd/include/v11_structs.h

481

uint32_t db_occlusion_count0_hi_13; // offset: 453 (0x1C5)

sys/dev/pci/drm/amd/include/v11_structs.h

482

uint32_t db_occlusion_count1_low_13; // offset: 454 (0x1C6)

sys/dev/pci/drm/amd/include/v11_structs.h

483

uint32_t db_occlusion_count1_hi_13; // offset: 455 (0x1C7)

sys/dev/pci/drm/amd/include/v11_structs.h

484

uint32_t db_occlusion_count2_low_13; // offset: 456 (0x1C8)

sys/dev/pci/drm/amd/include/v11_structs.h

485

uint32_t db_occlusion_count2_hi_13; // offset: 457 (0x1C9)

sys/dev/pci/drm/amd/include/v11_structs.h

486

uint32_t db_occlusion_count3_low_13; // offset: 458 (0x1CA)

sys/dev/pci/drm/amd/include/v11_structs.h

487

uint32_t db_occlusion_count3_hi_13; // offset: 459 (0x1CB)

sys/dev/pci/drm/amd/include/v11_structs.h

488

uint32_t db_occlusion_count0_low_14; // offset: 460 (0x1CC)

sys/dev/pci/drm/amd/include/v11_structs.h

489

uint32_t db_occlusion_count0_hi_14; // offset: 461 (0x1CD)

sys/dev/pci/drm/amd/include/v11_structs.h

49

uint32_t reserved_21; // offset: 21 (0x15)

sys/dev/pci/drm/amd/include/v11_structs.h

490

uint32_t db_occlusion_count1_low_14; // offset: 462 (0x1CE)

sys/dev/pci/drm/amd/include/v11_structs.h

491

uint32_t db_occlusion_count1_hi_14; // offset: 463 (0x1CF)

sys/dev/pci/drm/amd/include/v11_structs.h

492

uint32_t db_occlusion_count2_low_14; // offset: 464 (0x1D0)

sys/dev/pci/drm/amd/include/v11_structs.h

493

uint32_t db_occlusion_count2_hi_14; // offset: 465 (0x1D1)

sys/dev/pci/drm/amd/include/v11_structs.h

494

uint32_t db_occlusion_count3_low_14; // offset: 466 (0x1D2)

sys/dev/pci/drm/amd/include/v11_structs.h

495

uint32_t db_occlusion_count3_hi_14; // offset: 467 (0x1D3)

sys/dev/pci/drm/amd/include/v11_structs.h

496

uint32_t db_occlusion_count0_low_15; // offset: 468 (0x1D4)

sys/dev/pci/drm/amd/include/v11_structs.h

497

uint32_t db_occlusion_count0_hi_15; // offset: 469 (0x1D5)

sys/dev/pci/drm/amd/include/v11_structs.h

498

uint32_t db_occlusion_count1_low_15; // offset: 470 (0x1D6)

sys/dev/pci/drm/amd/include/v11_structs.h

499

uint32_t db_occlusion_count1_hi_15; // offset: 471 (0x1D7)

sys/dev/pci/drm/amd/include/v11_structs.h

50

uint32_t reserved_22; // offset: 22 (0x16)

sys/dev/pci/drm/amd/include/v11_structs.h

500

uint32_t db_occlusion_count2_low_15; // offset: 472 (0x1D8)

sys/dev/pci/drm/amd/include/v11_structs.h

501

uint32_t db_occlusion_count2_hi_15; // offset: 473 (0x1D9)

sys/dev/pci/drm/amd/include/v11_structs.h

502

uint32_t db_occlusion_count3_low_15; // offset: 474 (0x1DA)

sys/dev/pci/drm/amd/include/v11_structs.h

503

uint32_t db_occlusion_count3_hi_15; // offset: 475 (0x1DB)

sys/dev/pci/drm/amd/include/v11_structs.h

504

uint32_t db_occlusion_count0_low_16; // offset: 476 (0x1DC)

sys/dev/pci/drm/amd/include/v11_structs.h

505

uint32_t db_occlusion_count0_hi_16; // offset: 477 (0x1DD)

sys/dev/pci/drm/amd/include/v11_structs.h

506

uint32_t db_occlusion_count1_low_16; // offset: 478 (0x1DE)

sys/dev/pci/drm/amd/include/v11_structs.h

507

uint32_t db_occlusion_count1_hi_16; // offset: 479 (0x1DF)

sys/dev/pci/drm/amd/include/v11_structs.h

508

uint32_t db_occlusion_count2_low_16; // offset: 480 (0x1E0)

sys/dev/pci/drm/amd/include/v11_structs.h

509

uint32_t db_occlusion_count2_hi_16; // offset: 481 (0x1E1)

sys/dev/pci/drm/amd/include/v11_structs.h

51

uint32_t reserved_23; // offset: 23 (0x17)

sys/dev/pci/drm/amd/include/v11_structs.h

510

uint32_t db_occlusion_count3_low_16; // offset: 482 (0x1E2)

sys/dev/pci/drm/amd/include/v11_structs.h

511

uint32_t db_occlusion_count3_hi_16; // offset: 483 (0x1E3)

sys/dev/pci/drm/amd/include/v11_structs.h

512

uint32_t db_occlusion_count0_low_17; // offset: 484 (0x1E4)

sys/dev/pci/drm/amd/include/v11_structs.h

513

uint32_t db_occlusion_count0_hi_17; // offset: 485 (0x1E5)

sys/dev/pci/drm/amd/include/v11_structs.h

514

uint32_t db_occlusion_count1_low_17; // offset: 486 (0x1E6)

sys/dev/pci/drm/amd/include/v11_structs.h

515

uint32_t db_occlusion_count1_hi_17; // offset: 487 (0x1E7)

sys/dev/pci/drm/amd/include/v11_structs.h

516

uint32_t db_occlusion_count2_low_17; // offset: 488 (0x1E8)

sys/dev/pci/drm/amd/include/v11_structs.h

517

uint32_t db_occlusion_count2_hi_17; // offset: 489 (0x1E9)

sys/dev/pci/drm/amd/include/v11_structs.h

518

uint32_t db_occlusion_count3_low_17; // offset: 490 (0x1EA)

sys/dev/pci/drm/amd/include/v11_structs.h

519

uint32_t db_occlusion_count3_hi_17; // offset: 491 (0x1EB)

sys/dev/pci/drm/amd/include/v11_structs.h

52

uint32_t reserved_24; // offset: 24 (0x18)

sys/dev/pci/drm/amd/include/v11_structs.h

520

uint32_t reserved_492; // offset: 492 (0x1EC)

sys/dev/pci/drm/amd/include/v11_structs.h

521

uint32_t reserved_493; // offset: 493 (0x1ED)

sys/dev/pci/drm/amd/include/v11_structs.h

522

uint32_t reserved_494; // offset: 494 (0x1EE)

sys/dev/pci/drm/amd/include/v11_structs.h

523

uint32_t reserved_495; // offset: 495 (0x1EF)

sys/dev/pci/drm/amd/include/v11_structs.h

524

uint32_t reserved_496; // offset: 496 (0x1F0)

sys/dev/pci/drm/amd/include/v11_structs.h

525

uint32_t reserved_497; // offset: 497 (0x1F1)

sys/dev/pci/drm/amd/include/v11_structs.h

526

uint32_t reserved_498; // offset: 498 (0x1F2)

sys/dev/pci/drm/amd/include/v11_structs.h

527

uint32_t reserved_499; // offset: 499 (0x1F3)

sys/dev/pci/drm/amd/include/v11_structs.h

528

uint32_t reserved_500; // offset: 500 (0x1F4)

sys/dev/pci/drm/amd/include/v11_structs.h

529

uint32_t reserved_501; // offset: 501 (0x1F5)

sys/dev/pci/drm/amd/include/v11_structs.h

53

uint32_t reserved_25; // offset: 25 (0x19)

sys/dev/pci/drm/amd/include/v11_structs.h

530

uint32_t reserved_502; // offset: 502 (0x1F6)

sys/dev/pci/drm/amd/include/v11_structs.h

531

uint32_t reserved_503; // offset: 503 (0x1F7)

sys/dev/pci/drm/amd/include/v11_structs.h

532

uint32_t reserved_504; // offset: 504 (0x1F8)

sys/dev/pci/drm/amd/include/v11_structs.h

533

uint32_t reserved_505; // offset: 505 (0x1F9)

sys/dev/pci/drm/amd/include/v11_structs.h

534

uint32_t reserved_506; // offset: 506 (0x1FA)

sys/dev/pci/drm/amd/include/v11_structs.h

535

uint32_t reserved_507; // offset: 507 (0x1FB)

sys/dev/pci/drm/amd/include/v11_structs.h

536

uint32_t reserved_508; // offset: 508 (0x1FC)

sys/dev/pci/drm/amd/include/v11_structs.h

537

uint32_t reserved_509; // offset: 509 (0x1FD)

sys/dev/pci/drm/amd/include/v11_structs.h

538

uint32_t fence_address_lo; // offset: 510 (0x1FE)

sys/dev/pci/drm/amd/include/v11_structs.h

539

uint32_t fence_address_hi; // offset: 511 (0x1FF)

sys/dev/pci/drm/amd/include/v11_structs.h

54

uint32_t reserved_26; // offset: 26 (0x1A)

sys/dev/pci/drm/amd/include/v11_structs.h

543

uint32_t sdmax_rlcx_rb_cntl; // offset: 0 (0x0)

sys/dev/pci/drm/amd/include/v11_structs.h

544

uint32_t sdmax_rlcx_rb_base; // offset: 1 (0x1)

sys/dev/pci/drm/amd/include/v11_structs.h

545

uint32_t sdmax_rlcx_rb_base_hi; // offset: 2 (0x2)

sys/dev/pci/drm/amd/include/v11_structs.h

546

uint32_t sdmax_rlcx_rb_rptr; // offset: 3 (0x3)

sys/dev/pci/drm/amd/include/v11_structs.h

547

uint32_t sdmax_rlcx_rb_rptr_hi; // offset: 4 (0x4)

sys/dev/pci/drm/amd/include/v11_structs.h

548

uint32_t sdmax_rlcx_rb_wptr; // offset: 5 (0x5)

sys/dev/pci/drm/amd/include/v11_structs.h

549

uint32_t sdmax_rlcx_rb_wptr_hi; // offset: 6 (0x6)

sys/dev/pci/drm/amd/include/v11_structs.h

55

uint32_t reserved_27; // offset: 27 (0x1B)

sys/dev/pci/drm/amd/include/v11_structs.h

550

uint32_t sdmax_rlcx_rb_rptr_addr_hi; // offset: 7 (0x7)

sys/dev/pci/drm/amd/include/v11_structs.h

551

uint32_t sdmax_rlcx_rb_rptr_addr_lo; // offset: 8 (0x8)

sys/dev/pci/drm/amd/include/v11_structs.h

552

uint32_t sdmax_rlcx_ib_cntl; // offset: 9 (0x9)

sys/dev/pci/drm/amd/include/v11_structs.h

553

uint32_t sdmax_rlcx_ib_rptr; // offset: 10 (0xA)

sys/dev/pci/drm/amd/include/v11_structs.h

554

uint32_t sdmax_rlcx_ib_offset; // offset: 11 (0xB)

sys/dev/pci/drm/amd/include/v11_structs.h

555

uint32_t sdmax_rlcx_ib_base_lo; // offset: 12 (0xC)

sys/dev/pci/drm/amd/include/v11_structs.h

556

uint32_t sdmax_rlcx_ib_base_hi; // offset: 13 (0xD)

sys/dev/pci/drm/amd/include/v11_structs.h

557

uint32_t sdmax_rlcx_ib_size; // offset: 14 (0xE)

sys/dev/pci/drm/amd/include/v11_structs.h

558

uint32_t sdmax_rlcx_skip_cntl; // offset: 15 (0xF)

sys/dev/pci/drm/amd/include/v11_structs.h

559

uint32_t sdmax_rlcx_context_status; // offset: 16 (0x10)

sys/dev/pci/drm/amd/include/v11_structs.h

56

uint32_t reserved_28; // offset: 28 (0x1C)

sys/dev/pci/drm/amd/include/v11_structs.h

560

uint32_t sdmax_rlcx_doorbell; // offset: 17 (0x11)

sys/dev/pci/drm/amd/include/v11_structs.h

561

uint32_t sdmax_rlcx_doorbell_log; // offset: 18 (0x12)

sys/dev/pci/drm/amd/include/v11_structs.h

562

uint32_t sdmax_rlcx_doorbell_offset; // offset: 19 (0x13)

sys/dev/pci/drm/amd/include/v11_structs.h

563

uint32_t sdmax_rlcx_csa_addr_lo; // offset: 20 (0x14)

sys/dev/pci/drm/amd/include/v11_structs.h

564

uint32_t sdmax_rlcx_csa_addr_hi; // offset: 21 (0x15)

sys/dev/pci/drm/amd/include/v11_structs.h

565

uint32_t sdmax_rlcx_sched_cntl; // offset: 22 (0x16)

sys/dev/pci/drm/amd/include/v11_structs.h

566

uint32_t sdmax_rlcx_ib_sub_remain; // offset: 23 (0x17)

sys/dev/pci/drm/amd/include/v11_structs.h

567

uint32_t sdmax_rlcx_preempt; // offset: 24 (0x18)

sys/dev/pci/drm/amd/include/v11_structs.h

568

uint32_t sdmax_rlcx_dummy_reg; // offset: 25 (0x19)

sys/dev/pci/drm/amd/include/v11_structs.h

569

uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi; // offset: 26 (0x1A)

sys/dev/pci/drm/amd/include/v11_structs.h

57

uint32_t reserved_29; // offset: 29 (0x1D)

sys/dev/pci/drm/amd/include/v11_structs.h

570

uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo; // offset: 27 (0x1B)

sys/dev/pci/drm/amd/include/v11_structs.h

571

uint32_t sdmax_rlcx_rb_aql_cntl; // offset: 28 (0x1C)

sys/dev/pci/drm/amd/include/v11_structs.h

572

uint32_t sdmax_rlcx_minor_ptr_update; // offset: 29 (0x1D)

sys/dev/pci/drm/amd/include/v11_structs.h

573

uint32_t sdmax_rlcx_rb_preempt; // offset: 30 (0x1E)

sys/dev/pci/drm/amd/include/v11_structs.h

574

uint32_t sdmax_rlcx_midcmd_data0; // offset: 31 (0x1F)

sys/dev/pci/drm/amd/include/v11_structs.h

575

uint32_t sdmax_rlcx_midcmd_data1; // offset: 32 (0x20)

sys/dev/pci/drm/amd/include/v11_structs.h

576

uint32_t sdmax_rlcx_midcmd_data2; // offset: 33 (0x21)

sys/dev/pci/drm/amd/include/v11_structs.h

577

uint32_t sdmax_rlcx_midcmd_data3; // offset: 34 (0x22)

sys/dev/pci/drm/amd/include/v11_structs.h

578

uint32_t sdmax_rlcx_midcmd_data4; // offset: 35 (0x23)

sys/dev/pci/drm/amd/include/v11_structs.h

579

uint32_t sdmax_rlcx_midcmd_data5; // offset: 36 (0x24)

sys/dev/pci/drm/amd/include/v11_structs.h

58

uint32_t reserved_30; // offset: 30 (0x1E)

sys/dev/pci/drm/amd/include/v11_structs.h

580

uint32_t sdmax_rlcx_midcmd_data6; // offset: 37 (0x25)

sys/dev/pci/drm/amd/include/v11_structs.h

581

uint32_t sdmax_rlcx_midcmd_data7; // offset: 38 (0x26)

sys/dev/pci/drm/amd/include/v11_structs.h

582

uint32_t sdmax_rlcx_midcmd_data8; // offset: 39 (0x27)

sys/dev/pci/drm/amd/include/v11_structs.h

583

uint32_t sdmax_rlcx_midcmd_data9; // offset: 40 (0x28)

sys/dev/pci/drm/amd/include/v11_structs.h

584

uint32_t sdmax_rlcx_midcmd_data10; // offset: 41 (0x29)

sys/dev/pci/drm/amd/include/v11_structs.h

585

uint32_t sdmax_rlcx_midcmd_cntl; // offset: 42 (0x2A)

sys/dev/pci/drm/amd/include/v11_structs.h

586

uint32_t sdmax_rlcx_f32_dbg0; // offset: 43 (0x2B)

sys/dev/pci/drm/amd/include/v11_structs.h

587

uint32_t sdmax_rlcx_f32_dbg1; // offset: 44 (0x2C)

sys/dev/pci/drm/amd/include/v11_structs.h

588

uint32_t reserved_45; // offset: 45 (0x2D)

sys/dev/pci/drm/amd/include/v11_structs.h

589

uint32_t reserved_46; // offset: 46 (0x2E)

sys/dev/pci/drm/amd/include/v11_structs.h

59

uint32_t reserved_31; // offset: 31 (0x1F)

sys/dev/pci/drm/amd/include/v11_structs.h

590

uint32_t reserved_47; // offset: 47 (0x2F)

sys/dev/pci/drm/amd/include/v11_structs.h

591

uint32_t reserved_48; // offset: 48 (0x30)

sys/dev/pci/drm/amd/include/v11_structs.h

592

uint32_t reserved_49; // offset: 49 (0x31)

sys/dev/pci/drm/amd/include/v11_structs.h

593

uint32_t reserved_50; // offset: 50 (0x32)

sys/dev/pci/drm/amd/include/v11_structs.h

594

uint32_t reserved_51; // offset: 51 (0x33)

sys/dev/pci/drm/amd/include/v11_structs.h

595

uint32_t reserved_52; // offset: 52 (0x34)

sys/dev/pci/drm/amd/include/v11_structs.h

596

uint32_t reserved_53; // offset: 53 (0x35)

sys/dev/pci/drm/amd/include/v11_structs.h

597

uint32_t reserved_54; // offset: 54 (0x36)

sys/dev/pci/drm/amd/include/v11_structs.h

598

uint32_t reserved_55; // offset: 55 (0x37)

sys/dev/pci/drm/amd/include/v11_structs.h

599

uint32_t reserved_56; // offset: 56 (0x38)

sys/dev/pci/drm/amd/include/v11_structs.h

60

uint32_t reserved_32; // offset: 32 (0x20)

sys/dev/pci/drm/amd/include/v11_structs.h

600

uint32_t reserved_57; // offset: 57 (0x39)

sys/dev/pci/drm/amd/include/v11_structs.h

601

uint32_t reserved_58; // offset: 58 (0x3A)

sys/dev/pci/drm/amd/include/v11_structs.h

602

uint32_t reserved_59; // offset: 59 (0x3B)

sys/dev/pci/drm/amd/include/v11_structs.h

603

uint32_t reserved_60; // offset: 60 (0x3C)

sys/dev/pci/drm/amd/include/v11_structs.h

604

uint32_t reserved_61; // offset: 61 (0x3D)

sys/dev/pci/drm/amd/include/v11_structs.h

605

uint32_t reserved_62; // offset: 62 (0x3E)

sys/dev/pci/drm/amd/include/v11_structs.h

606

uint32_t reserved_63; // offset: 63 (0x3F)

sys/dev/pci/drm/amd/include/v11_structs.h

607

uint32_t reserved_64; // offset: 64 (0x40)

sys/dev/pci/drm/amd/include/v11_structs.h

608

uint32_t reserved_65; // offset: 65 (0x41)

sys/dev/pci/drm/amd/include/v11_structs.h

609

uint32_t reserved_66; // offset: 66 (0x42)

sys/dev/pci/drm/amd/include/v11_structs.h

61

uint32_t reserved_33; // offset: 33 (0x21)

sys/dev/pci/drm/amd/include/v11_structs.h

610

uint32_t reserved_67; // offset: 67 (0x43)

sys/dev/pci/drm/amd/include/v11_structs.h

611

uint32_t reserved_68; // offset: 68 (0x44)

sys/dev/pci/drm/amd/include/v11_structs.h

612

uint32_t reserved_69; // offset: 69 (0x45)

sys/dev/pci/drm/amd/include/v11_structs.h

613

uint32_t reserved_70; // offset: 70 (0x46)

sys/dev/pci/drm/amd/include/v11_structs.h

614

uint32_t reserved_71; // offset: 0 (0x47)

sys/dev/pci/drm/amd/include/v11_structs.h

615

uint32_t reserved_72; // offset: 1 (0x48)

sys/dev/pci/drm/amd/include/v11_structs.h

616

uint32_t reserved_73; // offset: 2 (0x49)

sys/dev/pci/drm/amd/include/v11_structs.h

617

uint32_t reserved_74; // offset: 3 (0x4A)

sys/dev/pci/drm/amd/include/v11_structs.h

618

uint32_t reserved_75; // offset: 4 (0x4B)

sys/dev/pci/drm/amd/include/v11_structs.h

619

uint32_t reserved_76; // offset: 5 (0x4C)

sys/dev/pci/drm/amd/include/v11_structs.h

62

uint32_t reserved_34; // offset: 34 (0x22)

sys/dev/pci/drm/amd/include/v11_structs.h

620

uint32_t reserved_77; // offset: 6 (0x4D)

sys/dev/pci/drm/amd/include/v11_structs.h

621

uint32_t reserved_78; // offset: 7 (0x4E)

sys/dev/pci/drm/amd/include/v11_structs.h

622

uint32_t reserved_79; // offset: 79 (0x4F)

sys/dev/pci/drm/amd/include/v11_structs.h

623

uint32_t reserved_80; // offset: 80 (0x50)

sys/dev/pci/drm/amd/include/v11_structs.h

624

uint32_t reserved_81; // offset: 81 (0x51)

sys/dev/pci/drm/amd/include/v11_structs.h

625

uint32_t reserved_82; // offset: 82 (0x52)

sys/dev/pci/drm/amd/include/v11_structs.h

626

uint32_t reserved_83; // offset: 83 (0x53)

sys/dev/pci/drm/amd/include/v11_structs.h

627

uint32_t reserved_84; // offset: 84 (0x54)

sys/dev/pci/drm/amd/include/v11_structs.h

628

uint32_t reserved_85; // offset: 85 (0x55)

sys/dev/pci/drm/amd/include/v11_structs.h

629

uint32_t reserved_86; // offset: 86 (0x56)

sys/dev/pci/drm/amd/include/v11_structs.h

63

uint32_t reserved_35; // offset: 35 (0x23)

sys/dev/pci/drm/amd/include/v11_structs.h

630

uint32_t reserved_87; // offset: 87 (0x57)

sys/dev/pci/drm/amd/include/v11_structs.h

631

uint32_t reserved_88; // offset: 88 (0x58)

sys/dev/pci/drm/amd/include/v11_structs.h

632

uint32_t reserved_89; // offset: 89 (0x59)

sys/dev/pci/drm/amd/include/v11_structs.h

633

uint32_t reserved_90; // offset: 90 (0x5A)

sys/dev/pci/drm/amd/include/v11_structs.h

634

uint32_t reserved_91; // offset: 91 (0x5B)

sys/dev/pci/drm/amd/include/v11_structs.h

635

uint32_t reserved_92; // offset: 92 (0x5C)

sys/dev/pci/drm/amd/include/v11_structs.h

636

uint32_t reserved_93; // offset: 93 (0x5D)

sys/dev/pci/drm/amd/include/v11_structs.h

637

uint32_t reserved_94; // offset: 94 (0x5E)

sys/dev/pci/drm/amd/include/v11_structs.h

638

uint32_t reserved_95; // offset: 95 (0x5F)

sys/dev/pci/drm/amd/include/v11_structs.h

639

uint32_t reserved_96; // offset: 96 (0x60)

sys/dev/pci/drm/amd/include/v11_structs.h

64

uint32_t reserved_36; // offset: 36 (0x24)

sys/dev/pci/drm/amd/include/v11_structs.h

640

uint32_t reserved_97; // offset: 97 (0x61)

sys/dev/pci/drm/amd/include/v11_structs.h

641

uint32_t reserved_98; // offset: 98 (0x62)

sys/dev/pci/drm/amd/include/v11_structs.h

642

uint32_t reserved_99; // offset: 99 (0x63)

sys/dev/pci/drm/amd/include/v11_structs.h

643

uint32_t reserved_100; // offset: 100 (0x64)

sys/dev/pci/drm/amd/include/v11_structs.h

644

uint32_t reserved_101; // offset: 101 (0x65)

sys/dev/pci/drm/amd/include/v11_structs.h

645

uint32_t reserved_102; // offset: 102 (0x66)

sys/dev/pci/drm/amd/include/v11_structs.h

646

uint32_t reserved_103; // offset: 103 (0x67)

sys/dev/pci/drm/amd/include/v11_structs.h

647

uint32_t reserved_104; // offset: 104 (0x68)

sys/dev/pci/drm/amd/include/v11_structs.h

648

uint32_t reserved_105; // offset: 105 (0x69)

sys/dev/pci/drm/amd/include/v11_structs.h

649

uint32_t reserved_106; // offset: 106 (0x6A)

sys/dev/pci/drm/amd/include/v11_structs.h

65

uint32_t reserved_37; // offset: 37 (0x25)

sys/dev/pci/drm/amd/include/v11_structs.h

650

uint32_t reserved_107; // offset: 107 (0x6B)

sys/dev/pci/drm/amd/include/v11_structs.h

651

uint32_t reserved_108; // offset: 108 (0x6C)

sys/dev/pci/drm/amd/include/v11_structs.h

652

uint32_t reserved_109; // offset: 109 (0x6D)

sys/dev/pci/drm/amd/include/v11_structs.h

653

uint32_t reserved_110; // offset: 110 (0x6E)

sys/dev/pci/drm/amd/include/v11_structs.h

654

uint32_t reserved_111; // offset: 111 (0x6F)

sys/dev/pci/drm/amd/include/v11_structs.h

655

uint32_t reserved_112; // offset: 112 (0x70)

sys/dev/pci/drm/amd/include/v11_structs.h

656

uint32_t reserved_113; // offset: 113 (0x71)

sys/dev/pci/drm/amd/include/v11_structs.h

657

uint32_t reserved_114; // offset: 114 (0x72)

sys/dev/pci/drm/amd/include/v11_structs.h

658

uint32_t reserved_115; // offset: 115 (0x73)

sys/dev/pci/drm/amd/include/v11_structs.h

659

uint32_t reserved_116; // offset: 116 (0x74)

sys/dev/pci/drm/amd/include/v11_structs.h

66

uint32_t reserved_38; // offset: 38 (0x26)

sys/dev/pci/drm/amd/include/v11_structs.h

660

uint32_t reserved_117; // offset: 117 (0x75)

sys/dev/pci/drm/amd/include/v11_structs.h

661

uint32_t reserved_118; // offset: 118 (0x76)

sys/dev/pci/drm/amd/include/v11_structs.h

662

uint32_t reserved_119; // offset: 119 (0x77)

sys/dev/pci/drm/amd/include/v11_structs.h

663

uint32_t reserved_120; // offset: 120 (0x78)

sys/dev/pci/drm/amd/include/v11_structs.h

664

uint32_t reserved_121; // offset: 121 (0x79)

sys/dev/pci/drm/amd/include/v11_structs.h

665

uint32_t reserved_122; // offset: 122 (0x7A)

sys/dev/pci/drm/amd/include/v11_structs.h

666

uint32_t reserved_123; // offset: 123 (0x7B)

sys/dev/pci/drm/amd/include/v11_structs.h

667

uint32_t reserved_124; // offset: 124 (0x7C)

sys/dev/pci/drm/amd/include/v11_structs.h

668

uint32_t reserved_125; // offset: 125 (0x7D)

sys/dev/pci/drm/amd/include/v11_structs.h

67

uint32_t reserved_39; // offset: 39 (0x27)

sys/dev/pci/drm/amd/include/v11_structs.h

670

uint32_t sdma_engine_id;

sys/dev/pci/drm/amd/include/v11_structs.h

671

uint32_t sdma_queue_id;

sys/dev/pci/drm/amd/include/v11_structs.h

675

uint32_t header; // offset: 0 (0x0)

sys/dev/pci/drm/amd/include/v11_structs.h

676

uint32_t compute_dispatch_initiator; // offset: 1 (0x1)

sys/dev/pci/drm/amd/include/v11_structs.h

677

uint32_t compute_dim_x; // offset: 2 (0x2)

sys/dev/pci/drm/amd/include/v11_structs.h

678

uint32_t compute_dim_y; // offset: 3 (0x3)

sys/dev/pci/drm/amd/include/v11_structs.h

679

uint32_t compute_dim_z; // offset: 4 (0x4)

sys/dev/pci/drm/amd/include/v11_structs.h

68

uint32_t reserved_40; // offset: 40 (0x28)

sys/dev/pci/drm/amd/include/v11_structs.h

680

uint32_t compute_start_x; // offset: 5 (0x5)

sys/dev/pci/drm/amd/include/v11_structs.h

681

uint32_t compute_start_y; // offset: 6 (0x6)

sys/dev/pci/drm/amd/include/v11_structs.h

682

uint32_t compute_start_z; // offset: 7 (0x7)

sys/dev/pci/drm/amd/include/v11_structs.h

683

uint32_t compute_num_thread_x; // offset: 8 (0x8)

sys/dev/pci/drm/amd/include/v11_structs.h

684

uint32_t compute_num_thread_y; // offset: 9 (0x9)

sys/dev/pci/drm/amd/include/v11_structs.h

685

uint32_t compute_num_thread_z; // offset: 10 (0xA)

sys/dev/pci/drm/amd/include/v11_structs.h

686

uint32_t compute_pipelinestat_enable; // offset: 11 (0xB)

sys/dev/pci/drm/amd/include/v11_structs.h

687

uint32_t compute_perfcount_enable; // offset: 12 (0xC)

sys/dev/pci/drm/amd/include/v11_structs.h

688

uint32_t compute_pgm_lo; // offset: 13 (0xD)

sys/dev/pci/drm/amd/include/v11_structs.h

689

uint32_t compute_pgm_hi; // offset: 14 (0xE)

sys/dev/pci/drm/amd/include/v11_structs.h

69

uint32_t reserved_41; // offset: 41 (0x29)

sys/dev/pci/drm/amd/include/v11_structs.h

690

uint32_t compute_dispatch_pkt_addr_lo; // offset: 15 (0xF)

sys/dev/pci/drm/amd/include/v11_structs.h

691

uint32_t compute_dispatch_pkt_addr_hi; // offset: 16 (0x10)

sys/dev/pci/drm/amd/include/v11_structs.h

692

uint32_t compute_dispatch_scratch_base_lo; // offset: 17 (0x11)

sys/dev/pci/drm/amd/include/v11_structs.h

693

uint32_t compute_dispatch_scratch_base_hi; // offset: 18 (0x12)

sys/dev/pci/drm/amd/include/v11_structs.h

694

uint32_t compute_pgm_rsrc1; // offset: 19 (0x13)

sys/dev/pci/drm/amd/include/v11_structs.h

695

uint32_t compute_pgm_rsrc2; // offset: 20 (0x14)

sys/dev/pci/drm/amd/include/v11_structs.h

696

uint32_t compute_vmid; // offset: 21 (0x15)

sys/dev/pci/drm/amd/include/v11_structs.h

697

uint32_t compute_resource_limits; // offset: 22 (0x16)

sys/dev/pci/drm/amd/include/v11_structs.h

698

uint32_t compute_static_thread_mgmt_se0; // offset: 23 (0x17)

sys/dev/pci/drm/amd/include/v11_structs.h

699

uint32_t compute_static_thread_mgmt_se1; // offset: 24 (0x18)

sys/dev/pci/drm/amd/include/v11_structs.h

70

uint32_t reserved_42; // offset: 42 (0x2A)

sys/dev/pci/drm/amd/include/v11_structs.h

700

uint32_t compute_tmpring_size; // offset: 25 (0x19)

sys/dev/pci/drm/amd/include/v11_structs.h

701

uint32_t compute_static_thread_mgmt_se2; // offset: 26 (0x1A)

sys/dev/pci/drm/amd/include/v11_structs.h

702

uint32_t compute_static_thread_mgmt_se3; // offset: 27 (0x1B)

sys/dev/pci/drm/amd/include/v11_structs.h

703

uint32_t compute_restart_x; // offset: 28 (0x1C)

sys/dev/pci/drm/amd/include/v11_structs.h

704

uint32_t compute_restart_y; // offset: 29 (0x1D)

sys/dev/pci/drm/amd/include/v11_structs.h

705

uint32_t compute_restart_z; // offset: 30 (0x1E)

sys/dev/pci/drm/amd/include/v11_structs.h

706

uint32_t compute_thread_trace_enable; // offset: 31 (0x1F)

sys/dev/pci/drm/amd/include/v11_structs.h

707

uint32_t compute_misc_reserved; // offset: 32 (0x20)

sys/dev/pci/drm/amd/include/v11_structs.h

708

uint32_t compute_dispatch_id; // offset: 33 (0x21)

sys/dev/pci/drm/amd/include/v11_structs.h

709

uint32_t compute_threadgroup_id; // offset: 34 (0x22)

sys/dev/pci/drm/amd/include/v11_structs.h

71

uint32_t reserved_43; // offset: 43 (0x2B)

sys/dev/pci/drm/amd/include/v11_structs.h

710

uint32_t compute_req_ctrl; // offset: 35 (0x23)

sys/dev/pci/drm/amd/include/v11_structs.h

711

uint32_t reserved_36; // offset: 36 (0x24)

sys/dev/pci/drm/amd/include/v11_structs.h

712

uint32_t compute_user_accum_0; // offset: 37 (0x25)

sys/dev/pci/drm/amd/include/v11_structs.h

713

uint32_t compute_user_accum_1; // offset: 38 (0x26)

sys/dev/pci/drm/amd/include/v11_structs.h

714

uint32_t compute_user_accum_2; // offset: 39 (0x27)

sys/dev/pci/drm/amd/include/v11_structs.h

715

uint32_t compute_user_accum_3; // offset: 40 (0x28)

sys/dev/pci/drm/amd/include/v11_structs.h

716

uint32_t compute_pgm_rsrc3; // offset: 41 (0x29)

sys/dev/pci/drm/amd/include/v11_structs.h

717

uint32_t compute_ddid_index; // offset: 42 (0x2A)

sys/dev/pci/drm/amd/include/v11_structs.h

718

uint32_t compute_shader_chksum; // offset: 43 (0x2B)

sys/dev/pci/drm/amd/include/v11_structs.h

719

uint32_t compute_static_thread_mgmt_se4; // offset: 44 (0x2C)

sys/dev/pci/drm/amd/include/v11_structs.h

72

uint32_t reserved_44; // offset: 44 (0x2C)

sys/dev/pci/drm/amd/include/v11_structs.h

720

uint32_t compute_static_thread_mgmt_se5; // offset: 45 (0x2D)

sys/dev/pci/drm/amd/include/v11_structs.h

721

uint32_t compute_static_thread_mgmt_se6; // offset: 46 (0x2E)

sys/dev/pci/drm/amd/include/v11_structs.h

722

uint32_t compute_static_thread_mgmt_se7; // offset: 47 (0x2F)

sys/dev/pci/drm/amd/include/v11_structs.h

723

uint32_t compute_dispatch_interleave; // offset: 48 (0x30)

sys/dev/pci/drm/amd/include/v11_structs.h

724

uint32_t compute_relaunch; // offset: 49 (0x31)

sys/dev/pci/drm/amd/include/v11_structs.h

725

uint32_t compute_wave_restore_addr_lo; // offset: 50 (0x32)

sys/dev/pci/drm/amd/include/v11_structs.h

726

uint32_t compute_wave_restore_addr_hi; // offset: 51 (0x33)

sys/dev/pci/drm/amd/include/v11_structs.h

727

uint32_t compute_wave_restore_control; // offset: 52 (0x34)

sys/dev/pci/drm/amd/include/v11_structs.h

728

uint32_t reserved_53; // offset: 53 (0x35)

sys/dev/pci/drm/amd/include/v11_structs.h

729

uint32_t reserved_54; // offset: 54 (0x36)

sys/dev/pci/drm/amd/include/v11_structs.h

73

uint32_t reserved_45; // offset: 45 (0x2D)

sys/dev/pci/drm/amd/include/v11_structs.h

730

uint32_t reserved_55; // offset: 55 (0x37)

sys/dev/pci/drm/amd/include/v11_structs.h

731

uint32_t reserved_56; // offset: 56 (0x38)

sys/dev/pci/drm/amd/include/v11_structs.h

732

uint32_t reserved_57; // offset: 57 (0x39)

sys/dev/pci/drm/amd/include/v11_structs.h

733

uint32_t reserved_58; // offset: 58 (0x3A)

sys/dev/pci/drm/amd/include/v11_structs.h

734

uint32_t reserved_59; // offset: 59 (0x3B)

sys/dev/pci/drm/amd/include/v11_structs.h

735

uint32_t reserved_60; // offset: 60 (0x3C)

sys/dev/pci/drm/amd/include/v11_structs.h

736

uint32_t reserved_61; // offset: 61 (0x3D)

sys/dev/pci/drm/amd/include/v11_structs.h

737

uint32_t reserved_62; // offset: 62 (0x3E)

sys/dev/pci/drm/amd/include/v11_structs.h

738

uint32_t reserved_63; // offset: 63 (0x3F)

sys/dev/pci/drm/amd/include/v11_structs.h

739

uint32_t reserved_64; // offset: 64 (0x40)

sys/dev/pci/drm/amd/include/v11_structs.h

74

uint32_t reserved_46; // offset: 46 (0x2E)

sys/dev/pci/drm/amd/include/v11_structs.h

740

uint32_t compute_user_data_0; // offset: 65 (0x41)

sys/dev/pci/drm/amd/include/v11_structs.h

741

uint32_t compute_user_data_1; // offset: 66 (0x42)

sys/dev/pci/drm/amd/include/v11_structs.h

742

uint32_t compute_user_data_2; // offset: 67 (0x43)

sys/dev/pci/drm/amd/include/v11_structs.h

743

uint32_t compute_user_data_3; // offset: 68 (0x44)

sys/dev/pci/drm/amd/include/v11_structs.h

744

uint32_t compute_user_data_4; // offset: 69 (0x45)

sys/dev/pci/drm/amd/include/v11_structs.h

745

uint32_t compute_user_data_5; // offset: 70 (0x46)

sys/dev/pci/drm/amd/include/v11_structs.h

746

uint32_t compute_user_data_6; // offset: 71 (0x47)

sys/dev/pci/drm/amd/include/v11_structs.h

747

uint32_t compute_user_data_7; // offset: 72 (0x48)

sys/dev/pci/drm/amd/include/v11_structs.h

748

uint32_t compute_user_data_8; // offset: 73 (0x49)

sys/dev/pci/drm/amd/include/v11_structs.h

749

uint32_t compute_user_data_9; // offset: 74 (0x4A)

sys/dev/pci/drm/amd/include/v11_structs.h

75

uint32_t reserved_47; // offset: 47 (0x2F)

sys/dev/pci/drm/amd/include/v11_structs.h

750

uint32_t compute_user_data_10; // offset: 75 (0x4B)

sys/dev/pci/drm/amd/include/v11_structs.h

751

uint32_t compute_user_data_11; // offset: 76 (0x4C)

sys/dev/pci/drm/amd/include/v11_structs.h

752

uint32_t compute_user_data_12; // offset: 77 (0x4D)

sys/dev/pci/drm/amd/include/v11_structs.h

753

uint32_t compute_user_data_13; // offset: 78 (0x4E)

sys/dev/pci/drm/amd/include/v11_structs.h

754

uint32_t compute_user_data_14; // offset: 79 (0x4F)

sys/dev/pci/drm/amd/include/v11_structs.h

755

uint32_t compute_user_data_15; // offset: 80 (0x50)

sys/dev/pci/drm/amd/include/v11_structs.h

756

uint32_t cp_compute_csinvoc_count_lo; // offset: 81 (0x51)

sys/dev/pci/drm/amd/include/v11_structs.h

757

uint32_t cp_compute_csinvoc_count_hi; // offset: 82 (0x52)

sys/dev/pci/drm/amd/include/v11_structs.h

758

uint32_t reserved_83; // offset: 83 (0x53)

sys/dev/pci/drm/amd/include/v11_structs.h

759

uint32_t reserved_84; // offset: 84 (0x54)

sys/dev/pci/drm/amd/include/v11_structs.h

76

uint32_t reserved_48; // offset: 48 (0x30)

sys/dev/pci/drm/amd/include/v11_structs.h

760

uint32_t reserved_85; // offset: 85 (0x55)

sys/dev/pci/drm/amd/include/v11_structs.h

761

uint32_t cp_mqd_query_time_lo; // offset: 86 (0x56)

sys/dev/pci/drm/amd/include/v11_structs.h

762

uint32_t cp_mqd_query_time_hi; // offset: 87 (0x57)

sys/dev/pci/drm/amd/include/v11_structs.h

763

uint32_t cp_mqd_connect_start_time_lo; // offset: 88 (0x58)

sys/dev/pci/drm/amd/include/v11_structs.h

764

uint32_t cp_mqd_connect_start_time_hi; // offset: 89 (0x59)

sys/dev/pci/drm/amd/include/v11_structs.h

765

uint32_t cp_mqd_connect_end_time_lo; // offset: 90 (0x5A)

sys/dev/pci/drm/amd/include/v11_structs.h

766

uint32_t cp_mqd_connect_end_time_hi; // offset: 91 (0x5B)

sys/dev/pci/drm/amd/include/v11_structs.h

767

uint32_t cp_mqd_connect_end_wf_count; // offset: 92 (0x5C)

sys/dev/pci/drm/amd/include/v11_structs.h

768

uint32_t cp_mqd_connect_end_pq_rptr; // offset: 93 (0x5D)

sys/dev/pci/drm/amd/include/v11_structs.h

769

uint32_t cp_mqd_connect_end_pq_wptr; // offset: 94 (0x5E)

sys/dev/pci/drm/amd/include/v11_structs.h

77

uint32_t reserved_49; // offset: 49 (0x31)

sys/dev/pci/drm/amd/include/v11_structs.h

770

uint32_t cp_mqd_connect_end_ib_rptr; // offset: 95 (0x5F)

sys/dev/pci/drm/amd/include/v11_structs.h

771

uint32_t cp_mqd_readindex_lo; // offset: 96 (0x60)

sys/dev/pci/drm/amd/include/v11_structs.h

772

uint32_t cp_mqd_readindex_hi; // offset: 97 (0x61)

sys/dev/pci/drm/amd/include/v11_structs.h

773

uint32_t cp_mqd_save_start_time_lo; // offset: 98 (0x62)

sys/dev/pci/drm/amd/include/v11_structs.h

774

uint32_t cp_mqd_save_start_time_hi; // offset: 99 (0x63)

sys/dev/pci/drm/amd/include/v11_structs.h

775

uint32_t cp_mqd_save_end_time_lo; // offset: 100 (0x64)

sys/dev/pci/drm/amd/include/v11_structs.h

776

uint32_t cp_mqd_save_end_time_hi; // offset: 101 (0x65)

sys/dev/pci/drm/amd/include/v11_structs.h

777

uint32_t cp_mqd_restore_start_time_lo; // offset: 102 (0x66)

sys/dev/pci/drm/amd/include/v11_structs.h

778

uint32_t cp_mqd_restore_start_time_hi; // offset: 103 (0x67)

sys/dev/pci/drm/amd/include/v11_structs.h

779

uint32_t cp_mqd_restore_end_time_lo; // offset: 104 (0x68)

sys/dev/pci/drm/amd/include/v11_structs.h

78

uint32_t reserved_50; // offset: 50 (0x32)

sys/dev/pci/drm/amd/include/v11_structs.h

780

uint32_t cp_mqd_restore_end_time_hi; // offset: 105 (0x69)

sys/dev/pci/drm/amd/include/v11_structs.h

781

uint32_t disable_queue; // offset: 106 (0x6A)

sys/dev/pci/drm/amd/include/v11_structs.h

782

uint32_t reserved_107; // offset: 107 (0x6B)

sys/dev/pci/drm/amd/include/v11_structs.h

783

uint32_t gds_cs_ctxsw_cnt0; // offset: 108 (0x6C)

sys/dev/pci/drm/amd/include/v11_structs.h

784

uint32_t gds_cs_ctxsw_cnt1; // offset: 109 (0x6D)

sys/dev/pci/drm/amd/include/v11_structs.h

785

uint32_t gds_cs_ctxsw_cnt2; // offset: 110 (0x6E)

sys/dev/pci/drm/amd/include/v11_structs.h

786

uint32_t gds_cs_ctxsw_cnt3; // offset: 111 (0x6F)

sys/dev/pci/drm/amd/include/v11_structs.h

787

uint32_t reserved_112; // offset: 112 (0x70)

sys/dev/pci/drm/amd/include/v11_structs.h

788

uint32_t reserved_113; // offset: 113 (0x71)

sys/dev/pci/drm/amd/include/v11_structs.h

789

uint32_t cp_pq_exe_status_lo; // offset: 114 (0x72)

sys/dev/pci/drm/amd/include/v11_structs.h

79

uint32_t reserved_51; // offset: 51 (0x33)

sys/dev/pci/drm/amd/include/v11_structs.h

790

uint32_t cp_pq_exe_status_hi; // offset: 115 (0x73)

sys/dev/pci/drm/amd/include/v11_structs.h

791

uint32_t cp_packet_id_lo; // offset: 116 (0x74)

sys/dev/pci/drm/amd/include/v11_structs.h

792

uint32_t cp_packet_id_hi; // offset: 117 (0x75)

sys/dev/pci/drm/amd/include/v11_structs.h

793

uint32_t cp_packet_exe_status_lo; // offset: 118 (0x76)

sys/dev/pci/drm/amd/include/v11_structs.h

794

uint32_t cp_packet_exe_status_hi; // offset: 119 (0x77)

sys/dev/pci/drm/amd/include/v11_structs.h

795

uint32_t gds_save_base_addr_lo; // offset: 120 (0x78)

sys/dev/pci/drm/amd/include/v11_structs.h

796

uint32_t gds_save_base_addr_hi; // offset: 121 (0x79)

sys/dev/pci/drm/amd/include/v11_structs.h

797

uint32_t gds_save_mask_lo; // offset: 122 (0x7A)

sys/dev/pci/drm/amd/include/v11_structs.h

798

uint32_t gds_save_mask_hi; // offset: 123 (0x7B)

sys/dev/pci/drm/amd/include/v11_structs.h

799

uint32_t ctx_save_base_addr_lo; // offset: 124 (0x7C)

sys/dev/pci/drm/amd/include/v11_structs.h

80

uint32_t reserved_52; // offset: 52 (0x34)

sys/dev/pci/drm/amd/include/v11_structs.h

800

uint32_t ctx_save_base_addr_hi; // offset: 125 (0x7D)

sys/dev/pci/drm/amd/include/v11_structs.h

801

uint32_t reserved_126; // offset: 126 (0x7E)

sys/dev/pci/drm/amd/include/v11_structs.h

802

uint32_t reserved_127; // offset: 127 (0x7F)

sys/dev/pci/drm/amd/include/v11_structs.h

803

uint32_t cp_mqd_base_addr_lo; // offset: 128 (0x80)

sys/dev/pci/drm/amd/include/v11_structs.h

804

uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81)

sys/dev/pci/drm/amd/include/v11_structs.h

805

uint32_t cp_hqd_active; // offset: 130 (0x82)

sys/dev/pci/drm/amd/include/v11_structs.h

806

uint32_t cp_hqd_vmid; // offset: 131 (0x83)

sys/dev/pci/drm/amd/include/v11_structs.h

807

uint32_t cp_hqd_persistent_state; // offset: 132 (0x84)

sys/dev/pci/drm/amd/include/v11_structs.h

808

uint32_t cp_hqd_pipe_priority; // offset: 133 (0x85)

sys/dev/pci/drm/amd/include/v11_structs.h

809

uint32_t cp_hqd_queue_priority; // offset: 134 (0x86)

sys/dev/pci/drm/amd/include/v11_structs.h

81

uint32_t reserved_53; // offset: 53 (0x35)

sys/dev/pci/drm/amd/include/v11_structs.h

810

uint32_t cp_hqd_quantum; // offset: 135 (0x87)

sys/dev/pci/drm/amd/include/v11_structs.h

811

uint32_t cp_hqd_pq_base_lo; // offset: 136 (0x88)

sys/dev/pci/drm/amd/include/v11_structs.h

812

uint32_t cp_hqd_pq_base_hi; // offset: 137 (0x89)

sys/dev/pci/drm/amd/include/v11_structs.h

813

uint32_t cp_hqd_pq_rptr; // offset: 138 (0x8A)

sys/dev/pci/drm/amd/include/v11_structs.h

814

uint32_t cp_hqd_pq_rptr_report_addr_lo; // offset: 139 (0x8B)

sys/dev/pci/drm/amd/include/v11_structs.h

815

uint32_t cp_hqd_pq_rptr_report_addr_hi; // offset: 140 (0x8C)

sys/dev/pci/drm/amd/include/v11_structs.h

816

uint32_t cp_hqd_pq_wptr_poll_addr_lo; // offset: 141 (0x8D)

sys/dev/pci/drm/amd/include/v11_structs.h

817

uint32_t cp_hqd_pq_wptr_poll_addr_hi; // offset: 142 (0x8E)

sys/dev/pci/drm/amd/include/v11_structs.h

818

uint32_t cp_hqd_pq_doorbell_control; // offset: 143 (0x8F)

sys/dev/pci/drm/amd/include/v11_structs.h

819

uint32_t reserved_144; // offset: 144 (0x90)

sys/dev/pci/drm/amd/include/v11_structs.h

82

uint32_t reserved_54; // offset: 54 (0x36)

sys/dev/pci/drm/amd/include/v11_structs.h

820

uint32_t cp_hqd_pq_control; // offset: 145 (0x91)

sys/dev/pci/drm/amd/include/v11_structs.h

821

uint32_t cp_hqd_ib_base_addr_lo; // offset: 146 (0x92)

sys/dev/pci/drm/amd/include/v11_structs.h

822

uint32_t cp_hqd_ib_base_addr_hi; // offset: 147 (0x93)

sys/dev/pci/drm/amd/include/v11_structs.h

823

uint32_t cp_hqd_ib_rptr; // offset: 148 (0x94)

sys/dev/pci/drm/amd/include/v11_structs.h

824

uint32_t cp_hqd_ib_control; // offset: 149 (0x95)

sys/dev/pci/drm/amd/include/v11_structs.h

825

uint32_t cp_hqd_iq_timer; // offset: 150 (0x96)

sys/dev/pci/drm/amd/include/v11_structs.h

826

uint32_t cp_hqd_iq_rptr; // offset: 151 (0x97)

sys/dev/pci/drm/amd/include/v11_structs.h

827

uint32_t cp_hqd_dequeue_request; // offset: 152 (0x98)

sys/dev/pci/drm/amd/include/v11_structs.h

828

uint32_t cp_hqd_dma_offload; // offset: 153 (0x99)

sys/dev/pci/drm/amd/include/v11_structs.h

829

uint32_t cp_hqd_sema_cmd; // offset: 154 (0x9A)

sys/dev/pci/drm/amd/include/v11_structs.h

83

uint32_t reserved_55; // offset: 55 (0x37)

sys/dev/pci/drm/amd/include/v11_structs.h

830

uint32_t cp_hqd_msg_type; // offset: 155 (0x9B)

sys/dev/pci/drm/amd/include/v11_structs.h

831

uint32_t cp_hqd_atomic0_preop_lo; // offset: 156 (0x9C)

sys/dev/pci/drm/amd/include/v11_structs.h

832

uint32_t cp_hqd_atomic0_preop_hi; // offset: 157 (0x9D)

sys/dev/pci/drm/amd/include/v11_structs.h

833

uint32_t cp_hqd_atomic1_preop_lo; // offset: 158 (0x9E)

sys/dev/pci/drm/amd/include/v11_structs.h

834

uint32_t cp_hqd_atomic1_preop_hi; // offset: 159 (0x9F)

sys/dev/pci/drm/amd/include/v11_structs.h

835

uint32_t cp_hqd_hq_status0; // offset: 160 (0xA0)

sys/dev/pci/drm/amd/include/v11_structs.h

836

uint32_t cp_hqd_hq_control0; // offset: 161 (0xA1)

sys/dev/pci/drm/amd/include/v11_structs.h

837

uint32_t cp_mqd_control; // offset: 162 (0xA2)

sys/dev/pci/drm/amd/include/v11_structs.h

838

uint32_t cp_hqd_hq_status1; // offset: 163 (0xA3)

sys/dev/pci/drm/amd/include/v11_structs.h

839

uint32_t cp_hqd_hq_control1; // offset: 164 (0xA4)

sys/dev/pci/drm/amd/include/v11_structs.h

84

uint32_t reserved_56; // offset: 56 (0x38)

sys/dev/pci/drm/amd/include/v11_structs.h

840

uint32_t cp_hqd_eop_base_addr_lo; // offset: 165 (0xA5)

sys/dev/pci/drm/amd/include/v11_structs.h

841

uint32_t cp_hqd_eop_base_addr_hi; // offset: 166 (0xA6)

sys/dev/pci/drm/amd/include/v11_structs.h

842

uint32_t cp_hqd_eop_control; // offset: 167 (0xA7)

sys/dev/pci/drm/amd/include/v11_structs.h

843

uint32_t cp_hqd_eop_rptr; // offset: 168 (0xA8)

sys/dev/pci/drm/amd/include/v11_structs.h

844

uint32_t cp_hqd_eop_wptr; // offset: 169 (0xA9)

sys/dev/pci/drm/amd/include/v11_structs.h

845

uint32_t cp_hqd_eop_done_events; // offset: 170 (0xAA)

sys/dev/pci/drm/amd/include/v11_structs.h

846

uint32_t cp_hqd_ctx_save_base_addr_lo; // offset: 171 (0xAB)

sys/dev/pci/drm/amd/include/v11_structs.h

847

uint32_t cp_hqd_ctx_save_base_addr_hi; // offset: 172 (0xAC)

sys/dev/pci/drm/amd/include/v11_structs.h

848

uint32_t cp_hqd_ctx_save_control; // offset: 173 (0xAD)

sys/dev/pci/drm/amd/include/v11_structs.h

849

uint32_t cp_hqd_cntl_stack_offset; // offset: 174 (0xAE)

sys/dev/pci/drm/amd/include/v11_structs.h

85

uint32_t reserved_57; // offset: 57 (0x39)

sys/dev/pci/drm/amd/include/v11_structs.h

850

uint32_t cp_hqd_cntl_stack_size; // offset: 175 (0xAF)

sys/dev/pci/drm/amd/include/v11_structs.h

851

uint32_t cp_hqd_wg_state_offset; // offset: 176 (0xB0)

sys/dev/pci/drm/amd/include/v11_structs.h

852

uint32_t cp_hqd_ctx_save_size; // offset: 177 (0xB1)

sys/dev/pci/drm/amd/include/v11_structs.h

853

uint32_t cp_hqd_gds_resource_state; // offset: 178 (0xB2)

sys/dev/pci/drm/amd/include/v11_structs.h

854

uint32_t cp_hqd_error; // offset: 179 (0xB3)

sys/dev/pci/drm/amd/include/v11_structs.h

855

uint32_t cp_hqd_eop_wptr_mem; // offset: 180 (0xB4)

sys/dev/pci/drm/amd/include/v11_structs.h

856

uint32_t cp_hqd_aql_control; // offset: 181 (0xB5)

sys/dev/pci/drm/amd/include/v11_structs.h

857

uint32_t cp_hqd_pq_wptr_lo; // offset: 182 (0xB6)

sys/dev/pci/drm/amd/include/v11_structs.h

858

uint32_t cp_hqd_pq_wptr_hi; // offset: 183 (0xB7)

sys/dev/pci/drm/amd/include/v11_structs.h

859

uint32_t reserved_184; // offset: 184 (0xB8)

sys/dev/pci/drm/amd/include/v11_structs.h

86

uint32_t reserved_58; // offset: 58 (0x3A)

sys/dev/pci/drm/amd/include/v11_structs.h

860

uint32_t reserved_185; // offset: 185 (0xB9)

sys/dev/pci/drm/amd/include/v11_structs.h

861

uint32_t reserved_186; // offset: 186 (0xBA)

sys/dev/pci/drm/amd/include/v11_structs.h

862

uint32_t reserved_187; // offset: 187 (0xBB)

sys/dev/pci/drm/amd/include/v11_structs.h

863

uint32_t reserved_188; // offset: 188 (0xBC)

sys/dev/pci/drm/amd/include/v11_structs.h

864

uint32_t reserved_189; // offset: 189 (0xBD)

sys/dev/pci/drm/amd/include/v11_structs.h

865

uint32_t reserved_190; // offset: 190 (0xBE)

sys/dev/pci/drm/amd/include/v11_structs.h

866

uint32_t reserved_191; // offset: 191 (0xBF)

sys/dev/pci/drm/amd/include/v11_structs.h

867

uint32_t iqtimer_pkt_header; // offset: 192 (0xC0)

sys/dev/pci/drm/amd/include/v11_structs.h

868

uint32_t iqtimer_pkt_dw0; // offset: 193 (0xC1)

sys/dev/pci/drm/amd/include/v11_structs.h

869

uint32_t iqtimer_pkt_dw1; // offset: 194 (0xC2)

sys/dev/pci/drm/amd/include/v11_structs.h

87

uint32_t reserved_59; // offset: 59 (0x3B)

sys/dev/pci/drm/amd/include/v11_structs.h

870

uint32_t iqtimer_pkt_dw2; // offset: 195 (0xC3)

sys/dev/pci/drm/amd/include/v11_structs.h

871

uint32_t iqtimer_pkt_dw3; // offset: 196 (0xC4)

sys/dev/pci/drm/amd/include/v11_structs.h

872

uint32_t iqtimer_pkt_dw4; // offset: 197 (0xC5)

sys/dev/pci/drm/amd/include/v11_structs.h

873

uint32_t iqtimer_pkt_dw5; // offset: 198 (0xC6)

sys/dev/pci/drm/amd/include/v11_structs.h

874

uint32_t iqtimer_pkt_dw6; // offset: 199 (0xC7)

sys/dev/pci/drm/amd/include/v11_structs.h

875

uint32_t iqtimer_pkt_dw7; // offset: 200 (0xC8)

sys/dev/pci/drm/amd/include/v11_structs.h

876

uint32_t iqtimer_pkt_dw8; // offset: 201 (0xC9)

sys/dev/pci/drm/amd/include/v11_structs.h

877

uint32_t iqtimer_pkt_dw9; // offset: 202 (0xCA)

sys/dev/pci/drm/amd/include/v11_structs.h

878

uint32_t iqtimer_pkt_dw10; // offset: 203 (0xCB)

sys/dev/pci/drm/amd/include/v11_structs.h

879

uint32_t iqtimer_pkt_dw11; // offset: 204 (0xCC)

sys/dev/pci/drm/amd/include/v11_structs.h

88

uint32_t reserved_60; // offset: 60 (0x3C)

sys/dev/pci/drm/amd/include/v11_structs.h

880

uint32_t iqtimer_pkt_dw12; // offset: 205 (0xCD)

sys/dev/pci/drm/amd/include/v11_structs.h

881

uint32_t iqtimer_pkt_dw13; // offset: 206 (0xCE)

sys/dev/pci/drm/amd/include/v11_structs.h

882

uint32_t iqtimer_pkt_dw14; // offset: 207 (0xCF)

sys/dev/pci/drm/amd/include/v11_structs.h

883

uint32_t iqtimer_pkt_dw15; // offset: 208 (0xD0)

sys/dev/pci/drm/amd/include/v11_structs.h

884

uint32_t iqtimer_pkt_dw16; // offset: 209 (0xD1)

sys/dev/pci/drm/amd/include/v11_structs.h

885

uint32_t iqtimer_pkt_dw17; // offset: 210 (0xD2)

sys/dev/pci/drm/amd/include/v11_structs.h

886

uint32_t iqtimer_pkt_dw18; // offset: 211 (0xD3)

sys/dev/pci/drm/amd/include/v11_structs.h

887

uint32_t iqtimer_pkt_dw19; // offset: 212 (0xD4)

sys/dev/pci/drm/amd/include/v11_structs.h

888

uint32_t iqtimer_pkt_dw20; // offset: 213 (0xD5)

sys/dev/pci/drm/amd/include/v11_structs.h

889

uint32_t iqtimer_pkt_dw21; // offset: 214 (0xD6)

sys/dev/pci/drm/amd/include/v11_structs.h

89

uint32_t reserved_61; // offset: 61 (0x3D)

sys/dev/pci/drm/amd/include/v11_structs.h

890

uint32_t iqtimer_pkt_dw22; // offset: 215 (0xD7)

sys/dev/pci/drm/amd/include/v11_structs.h

891

uint32_t iqtimer_pkt_dw23; // offset: 216 (0xD8)

sys/dev/pci/drm/amd/include/v11_structs.h

892

uint32_t iqtimer_pkt_dw24; // offset: 217 (0xD9)

sys/dev/pci/drm/amd/include/v11_structs.h

893

uint32_t iqtimer_pkt_dw25; // offset: 218 (0xDA)

sys/dev/pci/drm/amd/include/v11_structs.h

894

uint32_t iqtimer_pkt_dw26; // offset: 219 (0xDB)

sys/dev/pci/drm/amd/include/v11_structs.h

895

uint32_t iqtimer_pkt_dw27; // offset: 220 (0xDC)

sys/dev/pci/drm/amd/include/v11_structs.h

896

uint32_t iqtimer_pkt_dw28; // offset: 221 (0xDD)

sys/dev/pci/drm/amd/include/v11_structs.h

897

uint32_t iqtimer_pkt_dw29; // offset: 222 (0xDE)

sys/dev/pci/drm/amd/include/v11_structs.h

898

uint32_t iqtimer_pkt_dw30; // offset: 223 (0xDF)

sys/dev/pci/drm/amd/include/v11_structs.h

899

uint32_t iqtimer_pkt_dw31; // offset: 224 (0xE0)

sys/dev/pci/drm/amd/include/v11_structs.h

90

uint32_t reserved_62; // offset: 62 (0x3E)

sys/dev/pci/drm/amd/include/v11_structs.h

900

uint32_t reserved_225; // offset: 225 (0xE1)

sys/dev/pci/drm/amd/include/v11_structs.h

901

uint32_t reserved_226; // offset: 226 (0xE2)

sys/dev/pci/drm/amd/include/v11_structs.h

902

uint32_t reserved_227; // offset: 227 (0xE3)

sys/dev/pci/drm/amd/include/v11_structs.h

903

uint32_t set_resources_header; // offset: 228 (0xE4)

sys/dev/pci/drm/amd/include/v11_structs.h

904

uint32_t set_resources_dw1; // offset: 229 (0xE5)

sys/dev/pci/drm/amd/include/v11_structs.h

905

uint32_t set_resources_dw2; // offset: 230 (0xE6)

sys/dev/pci/drm/amd/include/v11_structs.h

906

uint32_t set_resources_dw3; // offset: 231 (0xE7)

sys/dev/pci/drm/amd/include/v11_structs.h

907

uint32_t set_resources_dw4; // offset: 232 (0xE8)

sys/dev/pci/drm/amd/include/v11_structs.h

908

uint32_t set_resources_dw5; // offset: 233 (0xE9)

sys/dev/pci/drm/amd/include/v11_structs.h

909

uint32_t set_resources_dw6; // offset: 234 (0xEA)

sys/dev/pci/drm/amd/include/v11_structs.h

91

uint32_t reserved_63; // offset: 63 (0x3F)

sys/dev/pci/drm/amd/include/v11_structs.h

910

uint32_t set_resources_dw7; // offset: 235 (0xEB)

sys/dev/pci/drm/amd/include/v11_structs.h

911

uint32_t reserved_236; // offset: 236 (0xEC)

sys/dev/pci/drm/amd/include/v11_structs.h

912

uint32_t reserved_237; // offset: 237 (0xED)

sys/dev/pci/drm/amd/include/v11_structs.h

913

uint32_t reserved_238; // offset: 238 (0xEE)

sys/dev/pci/drm/amd/include/v11_structs.h

914

uint32_t reserved_239; // offset: 239 (0xEF)

sys/dev/pci/drm/amd/include/v11_structs.h

915

uint32_t queue_doorbell_id0; // offset: 240 (0xF0)

sys/dev/pci/drm/amd/include/v11_structs.h

916

uint32_t queue_doorbell_id1; // offset: 241 (0xF1)

sys/dev/pci/drm/amd/include/v11_structs.h

917

uint32_t queue_doorbell_id2; // offset: 242 (0xF2)

sys/dev/pci/drm/amd/include/v11_structs.h

918

uint32_t queue_doorbell_id3; // offset: 243 (0xF3)

sys/dev/pci/drm/amd/include/v11_structs.h

919

uint32_t queue_doorbell_id4; // offset: 244 (0xF4)

sys/dev/pci/drm/amd/include/v11_structs.h

92

uint32_t reserved_64; // offset: 64 (0x40)

sys/dev/pci/drm/amd/include/v11_structs.h

920

uint32_t queue_doorbell_id5; // offset: 245 (0xF5)

sys/dev/pci/drm/amd/include/v11_structs.h

921

uint32_t queue_doorbell_id6; // offset: 246 (0xF6)

sys/dev/pci/drm/amd/include/v11_structs.h

922

uint32_t queue_doorbell_id7; // offset: 247 (0xF7)

sys/dev/pci/drm/amd/include/v11_structs.h

923

uint32_t queue_doorbell_id8; // offset: 248 (0xF8)

sys/dev/pci/drm/amd/include/v11_structs.h

924

uint32_t queue_doorbell_id9; // offset: 249 (0xF9)

sys/dev/pci/drm/amd/include/v11_structs.h

925

uint32_t queue_doorbell_id10; // offset: 250 (0xFA)

sys/dev/pci/drm/amd/include/v11_structs.h

926

uint32_t queue_doorbell_id11; // offset: 251 (0xFB)

sys/dev/pci/drm/amd/include/v11_structs.h

927

uint32_t queue_doorbell_id12; // offset: 252 (0xFC)

sys/dev/pci/drm/amd/include/v11_structs.h

928

uint32_t queue_doorbell_id13; // offset: 253 (0xFD)

sys/dev/pci/drm/amd/include/v11_structs.h

929

uint32_t queue_doorbell_id14; // offset: 254 (0xFE)

sys/dev/pci/drm/amd/include/v11_structs.h

93

uint32_t reserved_65; // offset: 65 (0x41)

sys/dev/pci/drm/amd/include/v11_structs.h

930

uint32_t queue_doorbell_id15; // offset: 255 (0xFF)

sys/dev/pci/drm/amd/include/v11_structs.h

931

uint32_t control_buf_addr_lo; // offset: 256 (0x100)

sys/dev/pci/drm/amd/include/v11_structs.h

932

uint32_t control_buf_addr_hi; // offset: 257 (0x101)

sys/dev/pci/drm/amd/include/v11_structs.h

933

uint32_t control_buf_wptr_lo; // offset: 258 (0x102)

sys/dev/pci/drm/amd/include/v11_structs.h

934

uint32_t control_buf_wptr_hi; // offset: 259 (0x103)

sys/dev/pci/drm/amd/include/v11_structs.h

935

uint32_t control_buf_dptr_lo; // offset: 260 (0x104)

sys/dev/pci/drm/amd/include/v11_structs.h

936

uint32_t control_buf_dptr_hi; // offset: 261 (0x105)

sys/dev/pci/drm/amd/include/v11_structs.h

937

uint32_t control_buf_num_entries; // offset: 262 (0x106)

sys/dev/pci/drm/amd/include/v11_structs.h

938

uint32_t draw_ring_addr_lo; // offset: 263 (0x107)

sys/dev/pci/drm/amd/include/v11_structs.h

939

uint32_t draw_ring_addr_hi; // offset: 264 (0x108)

sys/dev/pci/drm/amd/include/v11_structs.h

94

uint32_t reserved_66; // offset: 66 (0x42)

sys/dev/pci/drm/amd/include/v11_structs.h

940

uint32_t reserved_265; // offset: 265 (0x109)

sys/dev/pci/drm/amd/include/v11_structs.h

941

uint32_t reserved_266; // offset: 266 (0x10A)

sys/dev/pci/drm/amd/include/v11_structs.h

942

uint32_t reserved_267; // offset: 267 (0x10B)

sys/dev/pci/drm/amd/include/v11_structs.h

943

uint32_t reserved_268; // offset: 268 (0x10C)

sys/dev/pci/drm/amd/include/v11_structs.h

944

uint32_t reserved_269; // offset: 269 (0x10D)

sys/dev/pci/drm/amd/include/v11_structs.h

945

uint32_t reserved_270; // offset: 270 (0x10E)

sys/dev/pci/drm/amd/include/v11_structs.h

946

uint32_t reserved_271; // offset: 271 (0x10F)

sys/dev/pci/drm/amd/include/v11_structs.h

947

uint32_t reserved_272; // offset: 272 (0x110)

sys/dev/pci/drm/amd/include/v11_structs.h

948

uint32_t reserved_273; // offset: 273 (0x111)

sys/dev/pci/drm/amd/include/v11_structs.h

949

uint32_t reserved_274; // offset: 274 (0x112)

sys/dev/pci/drm/amd/include/v11_structs.h

95

uint32_t reserved_67; // offset: 67 (0x43)

sys/dev/pci/drm/amd/include/v11_structs.h

950

uint32_t reserved_275; // offset: 275 (0x113)

sys/dev/pci/drm/amd/include/v11_structs.h

951

uint32_t reserved_276; // offset: 276 (0x114)

sys/dev/pci/drm/amd/include/v11_structs.h

952

uint32_t reserved_277; // offset: 277 (0x115)

sys/dev/pci/drm/amd/include/v11_structs.h

953

uint32_t reserved_278; // offset: 278 (0x116)

sys/dev/pci/drm/amd/include/v11_structs.h

954

uint32_t reserved_279; // offset: 279 (0x117)

sys/dev/pci/drm/amd/include/v11_structs.h

955

uint32_t reserved_280; // offset: 280 (0x118)

sys/dev/pci/drm/amd/include/v11_structs.h

956

uint32_t reserved_281; // offset: 281 (0x119)

sys/dev/pci/drm/amd/include/v11_structs.h

957

uint32_t reserved_282; // offset: 282 (0x11A)

sys/dev/pci/drm/amd/include/v11_structs.h

958

uint32_t reserved_283; // offset: 283 (0x11B)

sys/dev/pci/drm/amd/include/v11_structs.h

959

uint32_t reserved_284; // offset: 284 (0x11C)

sys/dev/pci/drm/amd/include/v11_structs.h

96

uint32_t reserved_68; // offset: 68 (0x44)

sys/dev/pci/drm/amd/include/v11_structs.h

960

uint32_t reserved_285; // offset: 285 (0x11D)

sys/dev/pci/drm/amd/include/v11_structs.h

961

uint32_t reserved_286; // offset: 286 (0x11E)

sys/dev/pci/drm/amd/include/v11_structs.h

962

uint32_t reserved_287; // offset: 287 (0x11F)

sys/dev/pci/drm/amd/include/v11_structs.h

963

uint32_t reserved_288; // offset: 288 (0x120)

sys/dev/pci/drm/amd/include/v11_structs.h

964

uint32_t reserved_289; // offset: 289 (0x121)

sys/dev/pci/drm/amd/include/v11_structs.h

965

uint32_t reserved_290; // offset: 290 (0x122)

sys/dev/pci/drm/amd/include/v11_structs.h

966

uint32_t reserved_291; // offset: 291 (0x123)

sys/dev/pci/drm/amd/include/v11_structs.h

967

uint32_t reserved_292; // offset: 292 (0x124)

sys/dev/pci/drm/amd/include/v11_structs.h

968

uint32_t reserved_293; // offset: 293 (0x125)

sys/dev/pci/drm/amd/include/v11_structs.h

969

uint32_t reserved_294; // offset: 294 (0x126)

sys/dev/pci/drm/amd/include/v11_structs.h

97

uint32_t reserved_69; // offset: 69 (0x45)

sys/dev/pci/drm/amd/include/v11_structs.h

970

uint32_t reserved_295; // offset: 295 (0x127)

sys/dev/pci/drm/amd/include/v11_structs.h

971

uint32_t reserved_296; // offset: 296 (0x128)

sys/dev/pci/drm/amd/include/v11_structs.h

972

uint32_t reserved_297; // offset: 297 (0x129)

sys/dev/pci/drm/amd/include/v11_structs.h

973

uint32_t reserved_298; // offset: 298 (0x12A)

sys/dev/pci/drm/amd/include/v11_structs.h

974

uint32_t reserved_299; // offset: 299 (0x12B)

sys/dev/pci/drm/amd/include/v11_structs.h

975

uint32_t reserved_300; // offset: 300 (0x12C)

sys/dev/pci/drm/amd/include/v11_structs.h

976

uint32_t reserved_301; // offset: 301 (0x12D)

sys/dev/pci/drm/amd/include/v11_structs.h

977

uint32_t reserved_302; // offset: 302 (0x12E)

sys/dev/pci/drm/amd/include/v11_structs.h

978

uint32_t reserved_303; // offset: 303 (0x12F)

sys/dev/pci/drm/amd/include/v11_structs.h

979

uint32_t reserved_304; // offset: 304 (0x130)

sys/dev/pci/drm/amd/include/v11_structs.h

98

uint32_t reserved_70; // offset: 70 (0x46)

sys/dev/pci/drm/amd/include/v11_structs.h

980

uint32_t reserved_305; // offset: 305 (0x131)

sys/dev/pci/drm/amd/include/v11_structs.h

981

uint32_t reserved_306; // offset: 306 (0x132)

sys/dev/pci/drm/amd/include/v11_structs.h

982

uint32_t reserved_307; // offset: 307 (0x133)

sys/dev/pci/drm/amd/include/v11_structs.h

983

uint32_t reserved_308; // offset: 308 (0x134)

sys/dev/pci/drm/amd/include/v11_structs.h

984

uint32_t reserved_309; // offset: 309 (0x135)

sys/dev/pci/drm/amd/include/v11_structs.h

985

uint32_t reserved_310; // offset: 310 (0x136)

sys/dev/pci/drm/amd/include/v11_structs.h

986

uint32_t reserved_311; // offset: 311 (0x137)

sys/dev/pci/drm/amd/include/v11_structs.h

987

uint32_t reserved_312; // offset: 312 (0x138)

sys/dev/pci/drm/amd/include/v11_structs.h

988

uint32_t reserved_313; // offset: 313 (0x139)

sys/dev/pci/drm/amd/include/v11_structs.h

989

uint32_t reserved_314; // offset: 314 (0x13A)

sys/dev/pci/drm/amd/include/v11_structs.h

99

uint32_t reserved_71; // offset: 71 (0x47)

sys/dev/pci/drm/amd/include/v11_structs.h

990

uint32_t reserved_315; // offset: 315 (0x13B)

sys/dev/pci/drm/amd/include/v11_structs.h

991

uint32_t reserved_316; // offset: 316 (0x13C)

sys/dev/pci/drm/amd/include/v11_structs.h

992

uint32_t reserved_317; // offset: 317 (0x13D)

sys/dev/pci/drm/amd/include/v11_structs.h

993

uint32_t reserved_318; // offset: 318 (0x13E)

sys/dev/pci/drm/amd/include/v11_structs.h

994

uint32_t reserved_319; // offset: 319 (0x13F)

sys/dev/pci/drm/amd/include/v11_structs.h

995

uint32_t reserved_320; // offset: 320 (0x140)

sys/dev/pci/drm/amd/include/v11_structs.h

996

uint32_t reserved_321; // offset: 321 (0x141)

sys/dev/pci/drm/amd/include/v11_structs.h

997

uint32_t reserved_322; // offset: 322 (0x142)

sys/dev/pci/drm/amd/include/v11_structs.h

998

uint32_t reserved_323; // offset: 323 (0x143)

sys/dev/pci/drm/amd/include/v11_structs.h

999

uint32_t reserved_324; // offset: 324 (0x144)

sys/dev/pci/drm/amd/include/v12_structs.h

100

uint32_t reserved_72; // offset: 72 (0x48)

sys/dev/pci/drm/amd/include/v12_structs.h

1000

uint32_t reserved_325; // offset: 325 (0x145)

sys/dev/pci/drm/amd/include/v12_structs.h

1001

uint32_t reserved_326; // offset: 326 (0x146)

sys/dev/pci/drm/amd/include/v12_structs.h

1002

uint32_t reserved_327; // offset: 327 (0x147)

sys/dev/pci/drm/amd/include/v12_structs.h

1003

uint32_t reserved_328; // offset: 328 (0x148)

sys/dev/pci/drm/amd/include/v12_structs.h

1004

uint32_t reserved_329; // offset: 329 (0x149)

sys/dev/pci/drm/amd/include/v12_structs.h

1005

uint32_t reserved_330; // offset: 330 (0x14A)

sys/dev/pci/drm/amd/include/v12_structs.h

1006

uint32_t reserved_331; // offset: 331 (0x14B)

sys/dev/pci/drm/amd/include/v12_structs.h

1007

uint32_t reserved_332; // offset: 332 (0x14C)

sys/dev/pci/drm/amd/include/v12_structs.h

1008

uint32_t reserved_333; // offset: 333 (0x14D)

sys/dev/pci/drm/amd/include/v12_structs.h

1009

uint32_t reserved_334; // offset: 334 (0x14E)

sys/dev/pci/drm/amd/include/v12_structs.h

101

uint32_t reserved_73; // offset: 73 (0x49)

sys/dev/pci/drm/amd/include/v12_structs.h

1010

uint32_t reserved_335; // offset: 335 (0x14F)

sys/dev/pci/drm/amd/include/v12_structs.h

1011

uint32_t reserved_336; // offset: 336 (0x150)

sys/dev/pci/drm/amd/include/v12_structs.h

1012

uint32_t reserved_337; // offset: 337 (0x151)

sys/dev/pci/drm/amd/include/v12_structs.h

1013

uint32_t reserved_338; // offset: 338 (0x152)

sys/dev/pci/drm/amd/include/v12_structs.h

1014

uint32_t reserved_339; // offset: 339 (0x153)

sys/dev/pci/drm/amd/include/v12_structs.h

1015

uint32_t reserved_340; // offset: 340 (0x154)

sys/dev/pci/drm/amd/include/v12_structs.h

1016

uint32_t reserved_341; // offset: 341 (0x155)

sys/dev/pci/drm/amd/include/v12_structs.h

1017

uint32_t reserved_342; // offset: 342 (0x156)

sys/dev/pci/drm/amd/include/v12_structs.h

1018

uint32_t reserved_343; // offset: 343 (0x157)

sys/dev/pci/drm/amd/include/v12_structs.h

1019

uint32_t reserved_344; // offset: 344 (0x158)

sys/dev/pci/drm/amd/include/v12_structs.h

102

uint32_t reserved_74; // offset: 74 (0x4A)

sys/dev/pci/drm/amd/include/v12_structs.h

1020

uint32_t reserved_345; // offset: 345 (0x159)

sys/dev/pci/drm/amd/include/v12_structs.h

1021

uint32_t reserved_346; // offset: 346 (0x15A)

sys/dev/pci/drm/amd/include/v12_structs.h

1022

uint32_t reserved_347; // offset: 347 (0x15B)

sys/dev/pci/drm/amd/include/v12_structs.h

1023

uint32_t reserved_348; // offset: 348 (0x15C)

sys/dev/pci/drm/amd/include/v12_structs.h

1024

uint32_t reserved_349; // offset: 349 (0x15D)

sys/dev/pci/drm/amd/include/v12_structs.h

1025

uint32_t reserved_350; // offset: 350 (0x15E)

sys/dev/pci/drm/amd/include/v12_structs.h

1026

uint32_t reserved_351; // offset: 351 (0x15F)

sys/dev/pci/drm/amd/include/v12_structs.h

1027

uint32_t reserved_352; // offset: 352 (0x160)

sys/dev/pci/drm/amd/include/v12_structs.h

1028

uint32_t reserved_353; // offset: 353 (0x161)

sys/dev/pci/drm/amd/include/v12_structs.h

1029

uint32_t reserved_354; // offset: 354 (0x162)

sys/dev/pci/drm/amd/include/v12_structs.h

103

uint32_t reserved_75; // offset: 75 (0x4B)

sys/dev/pci/drm/amd/include/v12_structs.h

1030

uint32_t reserved_355; // offset: 355 (0x163)

sys/dev/pci/drm/amd/include/v12_structs.h

1031

uint32_t reserved_356; // offset: 356 (0x164)

sys/dev/pci/drm/amd/include/v12_structs.h

1032

uint32_t reserved_357; // offset: 357 (0x165)

sys/dev/pci/drm/amd/include/v12_structs.h

1033

uint32_t reserved_358; // offset: 358 (0x166)

sys/dev/pci/drm/amd/include/v12_structs.h

1034

uint32_t reserved_359; // offset: 359 (0x167)

sys/dev/pci/drm/amd/include/v12_structs.h

1035

uint32_t reserved_360; // offset: 360 (0x168)

sys/dev/pci/drm/amd/include/v12_structs.h

1036

uint32_t reserved_361; // offset: 361 (0x169)

sys/dev/pci/drm/amd/include/v12_structs.h

1037

uint32_t reserved_362; // offset: 362 (0x16A)

sys/dev/pci/drm/amd/include/v12_structs.h

1038

uint32_t reserved_363; // offset: 363 (0x16B)

sys/dev/pci/drm/amd/include/v12_structs.h

1039

uint32_t reserved_364; // offset: 364 (0x16C)

sys/dev/pci/drm/amd/include/v12_structs.h

104

uint32_t reserved_76; // offset: 76 (0x4C)

sys/dev/pci/drm/amd/include/v12_structs.h

1040

uint32_t reserved_365; // offset: 365 (0x16D)

sys/dev/pci/drm/amd/include/v12_structs.h

1041

uint32_t reserved_366; // offset: 366 (0x16E)

sys/dev/pci/drm/amd/include/v12_structs.h

1042

uint32_t reserved_367; // offset: 367 (0x16F)

sys/dev/pci/drm/amd/include/v12_structs.h

1043

uint32_t reserved_368; // offset: 368 (0x170)

sys/dev/pci/drm/amd/include/v12_structs.h

1044

uint32_t reserved_369; // offset: 369 (0x171)

sys/dev/pci/drm/amd/include/v12_structs.h

1045

uint32_t reserved_370; // offset: 370 (0x172)

sys/dev/pci/drm/amd/include/v12_structs.h

1046

uint32_t reserved_371; // offset: 371 (0x173)

sys/dev/pci/drm/amd/include/v12_structs.h

1047

uint32_t reserved_372; // offset: 372 (0x174)

sys/dev/pci/drm/amd/include/v12_structs.h

1048

uint32_t reserved_373; // offset: 373 (0x175)

sys/dev/pci/drm/amd/include/v12_structs.h

1049

uint32_t reserved_374; // offset: 374 (0x176)

sys/dev/pci/drm/amd/include/v12_structs.h

105

uint32_t reserved_77; // offset: 77 (0x4D)

sys/dev/pci/drm/amd/include/v12_structs.h

1050

uint32_t reserved_375; // offset: 375 (0x177)

sys/dev/pci/drm/amd/include/v12_structs.h

1051

uint32_t reserved_376; // offset: 376 (0x178)

sys/dev/pci/drm/amd/include/v12_structs.h

1052

uint32_t reserved_377; // offset: 377 (0x179)

sys/dev/pci/drm/amd/include/v12_structs.h

1053

uint32_t reserved_378; // offset: 378 (0x17A)

sys/dev/pci/drm/amd/include/v12_structs.h

1054

uint32_t reserved_379; // offset: 379 (0x17B)

sys/dev/pci/drm/amd/include/v12_structs.h

1055

uint32_t reserved_380; // offset: 380 (0x17C)

sys/dev/pci/drm/amd/include/v12_structs.h

1056

uint32_t reserved_381; // offset: 381 (0x17D)

sys/dev/pci/drm/amd/include/v12_structs.h

1057

uint32_t reserved_382; // offset: 382 (0x17E)

sys/dev/pci/drm/amd/include/v12_structs.h

1058

uint32_t reserved_383; // offset: 383 (0x17F)

sys/dev/pci/drm/amd/include/v12_structs.h

1059

uint32_t reserved_384; // offset: 384 (0x180)

sys/dev/pci/drm/amd/include/v12_structs.h

106

uint32_t reserved_78; // offset: 78 (0x4E)

sys/dev/pci/drm/amd/include/v12_structs.h

1060

uint32_t reserved_385; // offset: 385 (0x181)

sys/dev/pci/drm/amd/include/v12_structs.h

1061

uint32_t reserved_386; // offset: 386 (0x182)

sys/dev/pci/drm/amd/include/v12_structs.h

1062

uint32_t reserved_387; // offset: 387 (0x183)

sys/dev/pci/drm/amd/include/v12_structs.h

1063

uint32_t reserved_388; // offset: 388 (0x184)

sys/dev/pci/drm/amd/include/v12_structs.h

1064

uint32_t reserved_389; // offset: 389 (0x185)

sys/dev/pci/drm/amd/include/v12_structs.h

1065

uint32_t reserved_390; // offset: 390 (0x186)

sys/dev/pci/drm/amd/include/v12_structs.h

1066

uint32_t reserved_391; // offset: 391 (0x187)

sys/dev/pci/drm/amd/include/v12_structs.h

1067

uint32_t reserved_392; // offset: 392 (0x188)

sys/dev/pci/drm/amd/include/v12_structs.h

1068

uint32_t reserved_393; // offset: 393 (0x189)

sys/dev/pci/drm/amd/include/v12_structs.h

1069

uint32_t reserved_394; // offset: 394 (0x18A)

sys/dev/pci/drm/amd/include/v12_structs.h

107

uint32_t reserved_79; // offset: 79 (0x4F)

sys/dev/pci/drm/amd/include/v12_structs.h

1070

uint32_t reserved_395; // offset: 395 (0x18B)

sys/dev/pci/drm/amd/include/v12_structs.h

1071

uint32_t reserved_396; // offset: 396 (0x18C)

sys/dev/pci/drm/amd/include/v12_structs.h

1072

uint32_t reserved_397; // offset: 397 (0x18D)

sys/dev/pci/drm/amd/include/v12_structs.h

1073

uint32_t reserved_398; // offset: 398 (0x18E)

sys/dev/pci/drm/amd/include/v12_structs.h

1074

uint32_t reserved_399; // offset: 399 (0x18F)

sys/dev/pci/drm/amd/include/v12_structs.h

1075

uint32_t reserved_400; // offset: 400 (0x190)

sys/dev/pci/drm/amd/include/v12_structs.h

1076

uint32_t reserved_401; // offset: 401 (0x191)

sys/dev/pci/drm/amd/include/v12_structs.h

1077

uint32_t reserved_402; // offset: 402 (0x192)

sys/dev/pci/drm/amd/include/v12_structs.h

1078

uint32_t reserved_403; // offset: 403 (0x193)

sys/dev/pci/drm/amd/include/v12_structs.h

1079

uint32_t reserved_404; // offset: 404 (0x194)

sys/dev/pci/drm/amd/include/v12_structs.h

108

uint32_t reserved_80; // offset: 80 (0x50)

sys/dev/pci/drm/amd/include/v12_structs.h

1080

uint32_t reserved_405; // offset: 405 (0x195)

sys/dev/pci/drm/amd/include/v12_structs.h

1081

uint32_t reserved_406; // offset: 406 (0x196)

sys/dev/pci/drm/amd/include/v12_structs.h

1082

uint32_t reserved_407; // offset: 407 (0x197)

sys/dev/pci/drm/amd/include/v12_structs.h

1083

uint32_t reserved_408; // offset: 408 (0x198)

sys/dev/pci/drm/amd/include/v12_structs.h

1084

uint32_t reserved_409; // offset: 409 (0x199)

sys/dev/pci/drm/amd/include/v12_structs.h

1085

uint32_t reserved_410; // offset: 410 (0x19A)

sys/dev/pci/drm/amd/include/v12_structs.h

1086

uint32_t reserved_411; // offset: 411 (0x19B)

sys/dev/pci/drm/amd/include/v12_structs.h

1087

uint32_t reserved_412; // offset: 412 (0x19C)

sys/dev/pci/drm/amd/include/v12_structs.h

1088

uint32_t reserved_413; // offset: 413 (0x19D)

sys/dev/pci/drm/amd/include/v12_structs.h

1089

uint32_t reserved_414; // offset: 414 (0x19E)

sys/dev/pci/drm/amd/include/v12_structs.h

109

uint32_t reserved_81; // offset: 81 (0x51)

sys/dev/pci/drm/amd/include/v12_structs.h

1090

uint32_t reserved_415; // offset: 415 (0x19F)

sys/dev/pci/drm/amd/include/v12_structs.h

1091

uint32_t reserved_416; // offset: 416 (0x1A0)

sys/dev/pci/drm/amd/include/v12_structs.h

1092

uint32_t reserved_417; // offset: 417 (0x1A1)

sys/dev/pci/drm/amd/include/v12_structs.h

1093

uint32_t reserved_418; // offset: 418 (0x1A2)

sys/dev/pci/drm/amd/include/v12_structs.h

1094

uint32_t reserved_419; // offset: 419 (0x1A3)

sys/dev/pci/drm/amd/include/v12_structs.h

1095

uint32_t reserved_420; // offset: 420 (0x1A4)

sys/dev/pci/drm/amd/include/v12_structs.h

1096

uint32_t reserved_421; // offset: 421 (0x1A5)

sys/dev/pci/drm/amd/include/v12_structs.h

1097

uint32_t reserved_422; // offset: 422 (0x1A6)

sys/dev/pci/drm/amd/include/v12_structs.h

1098

uint32_t reserved_423; // offset: 423 (0x1A7)

sys/dev/pci/drm/amd/include/v12_structs.h

1099

uint32_t reserved_424; // offset: 424 (0x1A8)

sys/dev/pci/drm/amd/include/v12_structs.h

110

uint32_t reserved_82; // offset: 82 (0x52)

sys/dev/pci/drm/amd/include/v12_structs.h

1100

uint32_t reserved_425; // offset: 425 (0x1A9)

sys/dev/pci/drm/amd/include/v12_structs.h

1101

uint32_t reserved_426; // offset: 426 (0x1AA)

sys/dev/pci/drm/amd/include/v12_structs.h

1102

uint32_t reserved_427; // offset: 427 (0x1AB)

sys/dev/pci/drm/amd/include/v12_structs.h

1103

uint32_t reserved_428; // offset: 428 (0x1AC)

sys/dev/pci/drm/amd/include/v12_structs.h

1104

uint32_t reserved_429; // offset: 429 (0x1AD)

sys/dev/pci/drm/amd/include/v12_structs.h

1105

uint32_t reserved_430; // offset: 430 (0x1AE)

sys/dev/pci/drm/amd/include/v12_structs.h

1106

uint32_t reserved_431; // offset: 431 (0x1AF)

sys/dev/pci/drm/amd/include/v12_structs.h

1107

uint32_t reserved_432; // offset: 432 (0x1B0)

sys/dev/pci/drm/amd/include/v12_structs.h

1108

uint32_t reserved_433; // offset: 433 (0x1B1)

sys/dev/pci/drm/amd/include/v12_structs.h

1109

uint32_t reserved_434; // offset: 434 (0x1B2)

sys/dev/pci/drm/amd/include/v12_structs.h

111

uint32_t reserved_83; // offset: 83 (0x53)

sys/dev/pci/drm/amd/include/v12_structs.h

1110

uint32_t reserved_435; // offset: 435 (0x1B3)

sys/dev/pci/drm/amd/include/v12_structs.h

1111

uint32_t reserved_436; // offset: 436 (0x1B4)

sys/dev/pci/drm/amd/include/v12_structs.h

1112

uint32_t reserved_437; // offset: 437 (0x1B5)

sys/dev/pci/drm/amd/include/v12_structs.h

1113

uint32_t reserved_438; // offset: 438 (0x1B6)

sys/dev/pci/drm/amd/include/v12_structs.h

1114

uint32_t reserved_439; // offset: 439 (0x1B7)

sys/dev/pci/drm/amd/include/v12_structs.h

1115

uint32_t reserved_440; // offset: 440 (0x1B8)

sys/dev/pci/drm/amd/include/v12_structs.h

1116

uint32_t reserved_441; // offset: 441 (0x1B9)

sys/dev/pci/drm/amd/include/v12_structs.h

1117

uint32_t reserved_442; // offset: 442 (0x1BA)

sys/dev/pci/drm/amd/include/v12_structs.h

1118

uint32_t reserved_443; // offset: 443 (0x1BB)

sys/dev/pci/drm/amd/include/v12_structs.h

1119

uint32_t reserved_444; // offset: 444 (0x1BC)

sys/dev/pci/drm/amd/include/v12_structs.h

112

uint32_t checksum_lo; // offset: 84 (0x54)

sys/dev/pci/drm/amd/include/v12_structs.h

1120

uint32_t reserved_445; // offset: 445 (0x1BD)

sys/dev/pci/drm/amd/include/v12_structs.h

1121

uint32_t fence_address_lo; // offset: 446 (0x1BE)

sys/dev/pci/drm/amd/include/v12_structs.h

1122

uint32_t fence_address_hi; // offset: 447 (0x1BF)

sys/dev/pci/drm/amd/include/v12_structs.h

1123

uint32_t gws_0_val; // offset: 448 (0x1C0)

sys/dev/pci/drm/amd/include/v12_structs.h

1124

uint32_t gws_1_val; // offset: 449 (0x1C1)

sys/dev/pci/drm/amd/include/v12_structs.h

1125

uint32_t gws_2_val; // offset: 450 (0x1C2)

sys/dev/pci/drm/amd/include/v12_structs.h

1126

uint32_t gws_3_val; // offset: 451 (0x1C3)

sys/dev/pci/drm/amd/include/v12_structs.h

1127

uint32_t gws_4_val; // offset: 452 (0x1C4)

sys/dev/pci/drm/amd/include/v12_structs.h

1128

uint32_t gws_5_val; // offset: 453 (0x1C5)

sys/dev/pci/drm/amd/include/v12_structs.h

1129

uint32_t gws_6_val; // offset: 454 (0x1C6)

sys/dev/pci/drm/amd/include/v12_structs.h

113

uint32_t checksum_hi; // offset: 85 (0x55)

sys/dev/pci/drm/amd/include/v12_structs.h

1130

uint32_t gws_7_val; // offset: 455 (0x1C7)

sys/dev/pci/drm/amd/include/v12_structs.h

1131

uint32_t gws_8_val; // offset: 456 (0x1C8)

sys/dev/pci/drm/amd/include/v12_structs.h

1132

uint32_t gws_9_val; // offset: 457 (0x1C9)

sys/dev/pci/drm/amd/include/v12_structs.h

1133

uint32_t gws_10_val; // offset: 458 (0x1CA)

sys/dev/pci/drm/amd/include/v12_structs.h

1134

uint32_t gws_11_val; // offset: 459 (0x1CB)

sys/dev/pci/drm/amd/include/v12_structs.h

1135

uint32_t gws_12_val; // offset: 460 (0x1CC)

sys/dev/pci/drm/amd/include/v12_structs.h

1136

uint32_t gws_13_val; // offset: 461 (0x1CD)

sys/dev/pci/drm/amd/include/v12_structs.h

1137

uint32_t gws_14_val; // offset: 462 (0x1CE)

sys/dev/pci/drm/amd/include/v12_structs.h

1138

uint32_t gws_15_val; // offset: 463 (0x1CF)

sys/dev/pci/drm/amd/include/v12_structs.h

1139

uint32_t gws_16_val; // offset: 464 (0x1D0)

sys/dev/pci/drm/amd/include/v12_structs.h

114

uint32_t cp_mqd_query_time_lo; // offset: 86 (0x56)

sys/dev/pci/drm/amd/include/v12_structs.h

1140

uint32_t gws_17_val; // offset: 465 (0x1D1)

sys/dev/pci/drm/amd/include/v12_structs.h

1141

uint32_t gws_18_val; // offset: 466 (0x1D2)

sys/dev/pci/drm/amd/include/v12_structs.h

1142

uint32_t gws_19_val; // offset: 467 (0x1D3)

sys/dev/pci/drm/amd/include/v12_structs.h

1143

uint32_t gws_20_val; // offset: 468 (0x1D4)

sys/dev/pci/drm/amd/include/v12_structs.h

1144

uint32_t gws_21_val; // offset: 469 (0x1D5)

sys/dev/pci/drm/amd/include/v12_structs.h

1145

uint32_t gws_22_val; // offset: 470 (0x1D6)

sys/dev/pci/drm/amd/include/v12_structs.h

1146

uint32_t gws_23_val; // offset: 471 (0x1D7)

sys/dev/pci/drm/amd/include/v12_structs.h

1147

uint32_t gws_24_val; // offset: 472 (0x1D8)

sys/dev/pci/drm/amd/include/v12_structs.h

1148

uint32_t gws_25_val; // offset: 473 (0x1D9)

sys/dev/pci/drm/amd/include/v12_structs.h

1149

uint32_t gws_26_val; // offset: 474 (0x1DA)

sys/dev/pci/drm/amd/include/v12_structs.h

115

uint32_t cp_mqd_query_time_hi; // offset: 87 (0x57)

sys/dev/pci/drm/amd/include/v12_structs.h

1150

uint32_t gws_27_val; // offset: 475 (0x1DB)

sys/dev/pci/drm/amd/include/v12_structs.h

1151

uint32_t gws_28_val; // offset: 476 (0x1DC)

sys/dev/pci/drm/amd/include/v12_structs.h

1152

uint32_t gws_29_val; // offset: 477 (0x1DD)

sys/dev/pci/drm/amd/include/v12_structs.h

1153

uint32_t gws_30_val; // offset: 478 (0x1DE)

sys/dev/pci/drm/amd/include/v12_structs.h

1154

uint32_t gws_31_val; // offset: 479 (0x1DF)

sys/dev/pci/drm/amd/include/v12_structs.h

1155

uint32_t gws_32_val; // offset: 480 (0x1E0)

sys/dev/pci/drm/amd/include/v12_structs.h

1156

uint32_t gws_33_val; // offset: 481 (0x1E1)

sys/dev/pci/drm/amd/include/v12_structs.h

1157

uint32_t gws_34_val; // offset: 482 (0x1E2)

sys/dev/pci/drm/amd/include/v12_structs.h

1158

uint32_t gws_35_val; // offset: 483 (0x1E3)

sys/dev/pci/drm/amd/include/v12_structs.h

1159

uint32_t gws_36_val; // offset: 484 (0x1E4)

sys/dev/pci/drm/amd/include/v12_structs.h

116

uint32_t reserved_88; // offset: 88 (0x58)

sys/dev/pci/drm/amd/include/v12_structs.h

1160

uint32_t gws_37_val; // offset: 485 (0x1E5)

sys/dev/pci/drm/amd/include/v12_structs.h

1161

uint32_t gws_38_val; // offset: 486 (0x1E6)

sys/dev/pci/drm/amd/include/v12_structs.h

1162

uint32_t gws_39_val; // offset: 487 (0x1E7)

sys/dev/pci/drm/amd/include/v12_structs.h

1163

uint32_t gws_40_val; // offset: 488 (0x1E8)

sys/dev/pci/drm/amd/include/v12_structs.h

1164

uint32_t gws_41_val; // offset: 489 (0x1E9)

sys/dev/pci/drm/amd/include/v12_structs.h

1165

uint32_t gws_42_val; // offset: 490 (0x1EA)

sys/dev/pci/drm/amd/include/v12_structs.h

1166

uint32_t gws_43_val; // offset: 491 (0x1EB)

sys/dev/pci/drm/amd/include/v12_structs.h

1167

uint32_t gws_44_val; // offset: 492 (0x1EC)

sys/dev/pci/drm/amd/include/v12_structs.h

1168

uint32_t gws_45_val; // offset: 493 (0x1ED)

sys/dev/pci/drm/amd/include/v12_structs.h

1169

uint32_t gws_46_val; // offset: 494 (0x1EE)

sys/dev/pci/drm/amd/include/v12_structs.h

117

uint32_t reserved_89; // offset: 89 (0x59)

sys/dev/pci/drm/amd/include/v12_structs.h

1170

uint32_t gws_47_val; // offset: 495 (0x1EF)

sys/dev/pci/drm/amd/include/v12_structs.h

1171

uint32_t gws_48_val; // offset: 496 (0x1F0)

sys/dev/pci/drm/amd/include/v12_structs.h

1172

uint32_t gws_49_val; // offset: 497 (0x1F1)

sys/dev/pci/drm/amd/include/v12_structs.h

1173

uint32_t gws_50_val; // offset: 498 (0x1F2)

sys/dev/pci/drm/amd/include/v12_structs.h

1174

uint32_t gws_51_val; // offset: 499 (0x1F3)

sys/dev/pci/drm/amd/include/v12_structs.h

1175

uint32_t gws_52_val; // offset: 500 (0x1F4)

sys/dev/pci/drm/amd/include/v12_structs.h

1176

uint32_t gws_53_val; // offset: 501 (0x1F5)

sys/dev/pci/drm/amd/include/v12_structs.h

1177

uint32_t gws_54_val; // offset: 502 (0x1F6)

sys/dev/pci/drm/amd/include/v12_structs.h

1178

uint32_t gws_55_val; // offset: 503 (0x1F7)

sys/dev/pci/drm/amd/include/v12_structs.h

1179

uint32_t gws_56_val; // offset: 504 (0x1F8)

sys/dev/pci/drm/amd/include/v12_structs.h

118

uint32_t reserved_90; // offset: 90 (0x5A)

sys/dev/pci/drm/amd/include/v12_structs.h

1180

uint32_t gws_57_val; // offset: 505 (0x1F9)

sys/dev/pci/drm/amd/include/v12_structs.h

1181

uint32_t gws_58_val; // offset: 506 (0x1FA)

sys/dev/pci/drm/amd/include/v12_structs.h

1182

uint32_t gws_59_val; // offset: 507 (0x1FB)

sys/dev/pci/drm/amd/include/v12_structs.h

1183

uint32_t gws_60_val; // offset: 508 (0x1FC)

sys/dev/pci/drm/amd/include/v12_structs.h

1184

uint32_t gws_61_val; // offset: 509 (0x1FD)

sys/dev/pci/drm/amd/include/v12_structs.h

1185

uint32_t gws_62_val; // offset: 510 (0x1FE)

sys/dev/pci/drm/amd/include/v12_structs.h

1186

uint32_t gws_63_val; // offset: 511 (0x1FF)

sys/dev/pci/drm/amd/include/v12_structs.h

119

uint32_t reserved_91; // offset: 91 (0x5B)

sys/dev/pci/drm/amd/include/v12_structs.h

120

uint32_t cp_mqd_query_wave_count; // offset: 92 (0x5C)

sys/dev/pci/drm/amd/include/v12_structs.h

121

uint32_t cp_mqd_query_gfx_hqd_rptr; // offset: 93 (0x5D)

sys/dev/pci/drm/amd/include/v12_structs.h

122

uint32_t cp_mqd_query_gfx_hqd_wptr; // offset: 94 (0x5E)

sys/dev/pci/drm/amd/include/v12_structs.h

123

uint32_t cp_mqd_query_gfx_hqd_offset; // offset: 95 (0x5F)

sys/dev/pci/drm/amd/include/v12_structs.h

124

uint32_t reserved_96; // offset: 96 (0x60)

sys/dev/pci/drm/amd/include/v12_structs.h

125

uint32_t reserved_97; // offset: 97 (0x61)

sys/dev/pci/drm/amd/include/v12_structs.h

126

uint32_t reserved_98; // offset: 98 (0x62)

sys/dev/pci/drm/amd/include/v12_structs.h

127

uint32_t reserved_99; // offset: 99 (0x63)

sys/dev/pci/drm/amd/include/v12_structs.h

128

uint32_t reserved_100; // offset: 100 (0x64)

sys/dev/pci/drm/amd/include/v12_structs.h

129

uint32_t reserved_101; // offset: 101 (0x65)

sys/dev/pci/drm/amd/include/v12_structs.h

130

uint32_t reserved_102; // offset: 102 (0x66)

sys/dev/pci/drm/amd/include/v12_structs.h

131

uint32_t reserved_103; // offset: 103 (0x67)

sys/dev/pci/drm/amd/include/v12_structs.h

132

uint32_t task_shader_control_buf_addr_lo; // offset: 104 (0x68)

sys/dev/pci/drm/amd/include/v12_structs.h

133

uint32_t task_shader_control_buf_addr_hi; // offset: 105 (0x69)

sys/dev/pci/drm/amd/include/v12_structs.h

134

uint32_t task_shader_read_rptr_lo; // offset: 106 (0x6A)

sys/dev/pci/drm/amd/include/v12_structs.h

135

uint32_t task_shader_read_rptr_hi; // offset: 107 (0x6B)

sys/dev/pci/drm/amd/include/v12_structs.h

136

uint32_t task_shader_num_entries; // offset: 108 (0x6C)

sys/dev/pci/drm/amd/include/v12_structs.h

137

uint32_t task_shader_num_entries_bits; // offset: 109 (0x6D)

sys/dev/pci/drm/amd/include/v12_structs.h

138

uint32_t task_shader_ring_buffer_addr_lo; // offset: 110 (0x6E)

sys/dev/pci/drm/amd/include/v12_structs.h

139

uint32_t task_shader_ring_buffer_addr_hi; // offset: 111 (0x6F)

sys/dev/pci/drm/amd/include/v12_structs.h

140

uint32_t reserved_112; // offset: 112 (0x70)

sys/dev/pci/drm/amd/include/v12_structs.h

141

uint32_t reserved_113; // offset: 113 (0x71)

sys/dev/pci/drm/amd/include/v12_structs.h

142

uint32_t reserved_114; // offset: 114 (0x72)

sys/dev/pci/drm/amd/include/v12_structs.h

143

uint32_t reserved_115; // offset: 115 (0x73)

sys/dev/pci/drm/amd/include/v12_structs.h

144

uint32_t reserved_116; // offset: 116 (0x74)

sys/dev/pci/drm/amd/include/v12_structs.h

145

uint32_t reserved_117; // offset: 117 (0x75)

sys/dev/pci/drm/amd/include/v12_structs.h

146

uint32_t reserved_118; // offset: 118 (0x76)

sys/dev/pci/drm/amd/include/v12_structs.h

147

uint32_t reserved_119; // offset: 119 (0x77)

sys/dev/pci/drm/amd/include/v12_structs.h

148

uint32_t reserved_120; // offset: 120 (0x78)

sys/dev/pci/drm/amd/include/v12_structs.h

149

uint32_t reserved_121; // offset: 121 (0x79)

sys/dev/pci/drm/amd/include/v12_structs.h

150

uint32_t reserved_122; // offset: 122 (0x7A)

sys/dev/pci/drm/amd/include/v12_structs.h

151

uint32_t reserved_123; // offset: 123 (0x7B)

sys/dev/pci/drm/amd/include/v12_structs.h

152

uint32_t reserved_124; // offset: 124 (0x7C)

sys/dev/pci/drm/amd/include/v12_structs.h

153

uint32_t reserved_125; // offset: 125 (0x7D)

sys/dev/pci/drm/amd/include/v12_structs.h

154

uint32_t reserved_126; // offset: 126 (0x7E)

sys/dev/pci/drm/amd/include/v12_structs.h

155

uint32_t reserved_127; // offset: 127 (0x7F)

sys/dev/pci/drm/amd/include/v12_structs.h

156

uint32_t cp_mqd_base_addr; // offset: 128 (0x80)

sys/dev/pci/drm/amd/include/v12_structs.h

157

uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81)

sys/dev/pci/drm/amd/include/v12_structs.h

158

uint32_t cp_gfx_hqd_active; // offset: 130 (0x82)

sys/dev/pci/drm/amd/include/v12_structs.h

159

uint32_t cp_gfx_hqd_vmid; // offset: 131 (0x83)

sys/dev/pci/drm/amd/include/v12_structs.h

160

uint32_t reserved_132; // offset: 132 (0x84)

sys/dev/pci/drm/amd/include/v12_structs.h

161

uint32_t reserved_133; // offset: 133 (0x85)

sys/dev/pci/drm/amd/include/v12_structs.h

162

uint32_t cp_gfx_hqd_queue_priority; // offset: 134 (0x86)

sys/dev/pci/drm/amd/include/v12_structs.h

163

uint32_t cp_gfx_hqd_quantum; // offset: 135 (0x87)

sys/dev/pci/drm/amd/include/v12_structs.h

164

uint32_t cp_gfx_hqd_base; // offset: 136 (0x88)

sys/dev/pci/drm/amd/include/v12_structs.h

165

uint32_t cp_gfx_hqd_base_hi; // offset: 137 (0x89)

sys/dev/pci/drm/amd/include/v12_structs.h

166

uint32_t cp_gfx_hqd_rptr; // offset: 138 (0x8A)

sys/dev/pci/drm/amd/include/v12_structs.h

167

uint32_t cp_gfx_hqd_rptr_addr; // offset: 139 (0x8B)

sys/dev/pci/drm/amd/include/v12_structs.h

168

uint32_t cp_gfx_hqd_rptr_addr_hi; // offset: 140 (0x8C)

sys/dev/pci/drm/amd/include/v12_structs.h

169

uint32_t cp_rb_wptr_poll_addr_lo; // offset: 141 (0x8D)

sys/dev/pci/drm/amd/include/v12_structs.h

170

uint32_t cp_rb_wptr_poll_addr_hi; // offset: 142 (0x8E)

sys/dev/pci/drm/amd/include/v12_structs.h

171

uint32_t cp_rb_doorbell_control; // offset: 143 (0x8F)

sys/dev/pci/drm/amd/include/v12_structs.h

172

uint32_t cp_gfx_hqd_offset; // offset: 144 (0x90)

sys/dev/pci/drm/amd/include/v12_structs.h

173

uint32_t cp_gfx_hqd_cntl; // offset: 145 (0x91)

sys/dev/pci/drm/amd/include/v12_structs.h

174

uint32_t reserved_146; // offset: 146 (0x92)

sys/dev/pci/drm/amd/include/v12_structs.h

175

uint32_t reserved_147; // offset: 147 (0x93)

sys/dev/pci/drm/amd/include/v12_structs.h

176

uint32_t cp_gfx_hqd_csmd_rptr; // offset: 148 (0x94)

sys/dev/pci/drm/amd/include/v12_structs.h

177

uint32_t cp_gfx_hqd_wptr; // offset: 149 (0x95)

sys/dev/pci/drm/amd/include/v12_structs.h

178

uint32_t cp_gfx_hqd_wptr_hi; // offset: 150 (0x96)

sys/dev/pci/drm/amd/include/v12_structs.h

179

uint32_t reserved_151; // offset: 151 (0x97)

sys/dev/pci/drm/amd/include/v12_structs.h

180

uint32_t reserved_152; // offset: 152 (0x98)

sys/dev/pci/drm/amd/include/v12_structs.h

181

uint32_t reserved_153; // offset: 153 (0x99)

sys/dev/pci/drm/amd/include/v12_structs.h

182

uint32_t reserved_154; // offset: 154 (0x9A)

sys/dev/pci/drm/amd/include/v12_structs.h

183

uint32_t reserved_155; // offset: 155 (0x9B)

sys/dev/pci/drm/amd/include/v12_structs.h

184

uint32_t cp_gfx_hqd_mapped; // offset: 156 (0x9C)

sys/dev/pci/drm/amd/include/v12_structs.h

185

uint32_t cp_gfx_hqd_que_mgr_control; // offset: 157 (0x9D)

sys/dev/pci/drm/amd/include/v12_structs.h

186

uint32_t reserved_158; // offset: 158 (0x9E)

sys/dev/pci/drm/amd/include/v12_structs.h

187

uint32_t reserved_159; // offset: 159 (0x9F)

sys/dev/pci/drm/amd/include/v12_structs.h

188

uint32_t cp_gfx_hqd_hq_status0; // offset: 160 (0xA0)

sys/dev/pci/drm/amd/include/v12_structs.h

189

uint32_t cp_gfx_hqd_hq_control0; // offset: 161 (0xA1)

sys/dev/pci/drm/amd/include/v12_structs.h

190

uint32_t cp_gfx_mqd_control; // offset: 162 (0xA2)

sys/dev/pci/drm/amd/include/v12_structs.h

191

uint32_t reserved_163; // offset: 163 (0xA3)

sys/dev/pci/drm/amd/include/v12_structs.h

192

uint32_t reserved_164; // offset: 164 (0xA4)

sys/dev/pci/drm/amd/include/v12_structs.h

193

uint32_t reserved_165; // offset: 165 (0xA5)

sys/dev/pci/drm/amd/include/v12_structs.h

194

uint32_t reserved_166; // offset: 166 (0xA6)

sys/dev/pci/drm/amd/include/v12_structs.h

195

uint32_t reserved_167; // offset: 167 (0xA7)

sys/dev/pci/drm/amd/include/v12_structs.h

196

uint32_t reserved_168; // offset: 168 (0xA8)

sys/dev/pci/drm/amd/include/v12_structs.h

197

uint32_t reserved_169; // offset: 169 (0xA9)

sys/dev/pci/drm/amd/include/v12_structs.h

198

uint32_t reserved_170; // offset: 170 (0xAA)

sys/dev/pci/drm/amd/include/v12_structs.h

199

uint32_t reserved_171; // offset: 171 (0xAB)

sys/dev/pci/drm/amd/include/v12_structs.h

200

uint32_t reserved_172; // offset: 172 (0xAC)

sys/dev/pci/drm/amd/include/v12_structs.h

201

uint32_t reserved_173; // offset: 173 (0xAD)

sys/dev/pci/drm/amd/include/v12_structs.h

202

uint32_t reserved_174; // offset: 174 (0xAE)

sys/dev/pci/drm/amd/include/v12_structs.h

203

uint32_t reserved_175; // offset: 175 (0xAF)

sys/dev/pci/drm/amd/include/v12_structs.h

204

uint32_t reserved_176; // offset: 176 (0xB0)

sys/dev/pci/drm/amd/include/v12_structs.h

205

uint32_t reserved_177; // offset: 177 (0xB1)

sys/dev/pci/drm/amd/include/v12_structs.h

206

uint32_t reserved_178; // offset: 178 (0xB2)

sys/dev/pci/drm/amd/include/v12_structs.h

207

uint32_t reserved_179; // offset: 179 (0xB3)

sys/dev/pci/drm/amd/include/v12_structs.h

208

uint32_t reserved_180; // offset: 180 (0xB4)

sys/dev/pci/drm/amd/include/v12_structs.h

209

uint32_t reserved_181; // offset: 181 (0xB5)

sys/dev/pci/drm/amd/include/v12_structs.h

210

uint32_t reserved_182; // offset: 182 (0xB6)

sys/dev/pci/drm/amd/include/v12_structs.h

211

uint32_t reserved_183; // offset: 183 (0xB7)

sys/dev/pci/drm/amd/include/v12_structs.h

212

uint32_t reserved_184; // offset: 184 (0xB8)

sys/dev/pci/drm/amd/include/v12_structs.h

213

uint32_t reserved_185; // offset: 185 (0xB9)

sys/dev/pci/drm/amd/include/v12_structs.h

214

uint32_t reserved_186; // offset: 186 (0xBA)

sys/dev/pci/drm/amd/include/v12_structs.h

215

uint32_t reserved_187; // offset: 187 (0xBB)

sys/dev/pci/drm/amd/include/v12_structs.h

216

uint32_t reserved_188; // offset: 188 (0xBC)

sys/dev/pci/drm/amd/include/v12_structs.h

217

uint32_t reserved_189; // offset: 189 (0xBD)

sys/dev/pci/drm/amd/include/v12_structs.h

218

uint32_t reserved_190; // offset: 190 (0xBE)

sys/dev/pci/drm/amd/include/v12_structs.h

219

uint32_t reserved_191; // offset: 191 (0xBF)

sys/dev/pci/drm/amd/include/v12_structs.h

220

uint32_t reserved_192; // offset: 192 (0xC0)

sys/dev/pci/drm/amd/include/v12_structs.h

221

uint32_t reserved_193; // offset: 193 (0xC1)

sys/dev/pci/drm/amd/include/v12_structs.h

222

uint32_t reserved_194; // offset: 194 (0xC2)

sys/dev/pci/drm/amd/include/v12_structs.h

223

uint32_t reserved_195; // offset: 195 (0xC3)

sys/dev/pci/drm/amd/include/v12_structs.h

224

uint32_t reserved_196; // offset: 196 (0xC4)

sys/dev/pci/drm/amd/include/v12_structs.h

225

uint32_t reserved_197; // offset: 197 (0xC5)

sys/dev/pci/drm/amd/include/v12_structs.h

226

uint32_t reserved_198; // offset: 198 (0xC6)

sys/dev/pci/drm/amd/include/v12_structs.h

227

uint32_t reserved_199; // offset: 199 (0xC7)

sys/dev/pci/drm/amd/include/v12_structs.h

228

uint32_t reserved_200; // offset: 200 (0xC8)

sys/dev/pci/drm/amd/include/v12_structs.h

229

uint32_t reserved_201; // offset: 201 (0xC9)

sys/dev/pci/drm/amd/include/v12_structs.h

230

uint32_t reserved_202; // offset: 202 (0xCA)

sys/dev/pci/drm/amd/include/v12_structs.h

231

uint32_t reserved_203; // offset: 203 (0xCB)

sys/dev/pci/drm/amd/include/v12_structs.h

232

uint32_t reserved_204; // offset: 204 (0xCC)

sys/dev/pci/drm/amd/include/v12_structs.h

233

uint32_t reserved_205; // offset: 205 (0xCD)

sys/dev/pci/drm/amd/include/v12_structs.h

234

uint32_t reserved_206; // offset: 206 (0xCE)

sys/dev/pci/drm/amd/include/v12_structs.h

235

uint32_t reserved_207; // offset: 207 (0xCF)

sys/dev/pci/drm/amd/include/v12_structs.h

236

uint32_t reserved_208; // offset: 208 (0xD0)

sys/dev/pci/drm/amd/include/v12_structs.h

237

uint32_t reserved_209; // offset: 209 (0xD1)

sys/dev/pci/drm/amd/include/v12_structs.h

238

uint32_t reserved_210; // offset: 210 (0xD2)

sys/dev/pci/drm/amd/include/v12_structs.h

239

uint32_t reserved_211; // offset: 211 (0xD3)

sys/dev/pci/drm/amd/include/v12_structs.h

240

uint32_t reserved_212; // offset: 212 (0xD4)

sys/dev/pci/drm/amd/include/v12_structs.h

241

uint32_t reserved_213; // offset: 213 (0xD5)

sys/dev/pci/drm/amd/include/v12_structs.h

242

uint32_t reserved_214; // offset: 214 (0xD6)

sys/dev/pci/drm/amd/include/v12_structs.h

243

uint32_t reserved_215; // offset: 215 (0xD7)

sys/dev/pci/drm/amd/include/v12_structs.h

244

uint32_t reserved_216; // offset: 216 (0xD8)

sys/dev/pci/drm/amd/include/v12_structs.h

245

uint32_t reserved_217; // offset: 217 (0xD9)

sys/dev/pci/drm/amd/include/v12_structs.h

246

uint32_t reserved_218; // offset: 218 (0xDA)

sys/dev/pci/drm/amd/include/v12_structs.h

247

uint32_t reserved_219; // offset: 219 (0xDB)

sys/dev/pci/drm/amd/include/v12_structs.h

248

uint32_t reserved_220; // offset: 220 (0xDC)

sys/dev/pci/drm/amd/include/v12_structs.h

249

uint32_t reserved_221; // offset: 221 (0xDD)

sys/dev/pci/drm/amd/include/v12_structs.h

250

uint32_t reserved_222; // offset: 222 (0xDE)

sys/dev/pci/drm/amd/include/v12_structs.h

251

uint32_t reserved_223; // offset: 223 (0xDF)

sys/dev/pci/drm/amd/include/v12_structs.h

252

uint32_t reserved_224; // offset: 224 (0xE0)

sys/dev/pci/drm/amd/include/v12_structs.h

253

uint32_t reserved_225; // offset: 225 (0xE1)

sys/dev/pci/drm/amd/include/v12_structs.h

254

uint32_t reserved_226; // offset: 226 (0xE2)

sys/dev/pci/drm/amd/include/v12_structs.h

255

uint32_t reserved_227; // offset: 227 (0xE3)

sys/dev/pci/drm/amd/include/v12_structs.h

256

uint32_t reserved_228; // offset: 228 (0xE4)

sys/dev/pci/drm/amd/include/v12_structs.h

257

uint32_t reserved_229; // offset: 229 (0xE5)

sys/dev/pci/drm/amd/include/v12_structs.h

258

uint32_t reserved_230; // offset: 230 (0xE6)

sys/dev/pci/drm/amd/include/v12_structs.h

259

uint32_t reserved_231; // offset: 231 (0xE7)

sys/dev/pci/drm/amd/include/v12_structs.h

260

uint32_t reserved_232; // offset: 232 (0xE8)

sys/dev/pci/drm/amd/include/v12_structs.h

261

uint32_t reserved_233; // offset: 233 (0xE9)

sys/dev/pci/drm/amd/include/v12_structs.h

262

uint32_t reserved_234; // offset: 234 (0xEA)

sys/dev/pci/drm/amd/include/v12_structs.h

263

uint32_t reserved_235; // offset: 235 (0xEB)

sys/dev/pci/drm/amd/include/v12_structs.h

264

uint32_t reserved_236; // offset: 236 (0xEC)

sys/dev/pci/drm/amd/include/v12_structs.h

265

uint32_t reserved_237; // offset: 237 (0xED)

sys/dev/pci/drm/amd/include/v12_structs.h

266

uint32_t reserved_238; // offset: 238 (0xEE)

sys/dev/pci/drm/amd/include/v12_structs.h

267

uint32_t reserved_239; // offset: 239 (0xEF)

sys/dev/pci/drm/amd/include/v12_structs.h

268

uint32_t reserved_240; // offset: 240 (0xF0)

sys/dev/pci/drm/amd/include/v12_structs.h

269

uint32_t reserved_241; // offset: 241 (0xF1)

sys/dev/pci/drm/amd/include/v12_structs.h

270

uint32_t reserved_242; // offset: 242 (0xF2)

sys/dev/pci/drm/amd/include/v12_structs.h

271

uint32_t reserved_243; // offset: 243 (0xF3)

sys/dev/pci/drm/amd/include/v12_structs.h

272

uint32_t reserved_244; // offset: 244 (0xF4)

sys/dev/pci/drm/amd/include/v12_structs.h

273

uint32_t reserved_245; // offset: 245 (0xF5)

sys/dev/pci/drm/amd/include/v12_structs.h

274

uint32_t reserved_246; // offset: 246 (0xF6)

sys/dev/pci/drm/amd/include/v12_structs.h

275

uint32_t reserved_247; // offset: 247 (0xF7)

sys/dev/pci/drm/amd/include/v12_structs.h

276

uint32_t reserved_248; // offset: 248 (0xF8)

sys/dev/pci/drm/amd/include/v12_structs.h

277

uint32_t reserved_249; // offset: 249 (0xF9)

sys/dev/pci/drm/amd/include/v12_structs.h

278

uint32_t reserved_250; // offset: 250 (0xFA)

sys/dev/pci/drm/amd/include/v12_structs.h

279

uint32_t reserved_251; // offset: 251 (0xFB)

sys/dev/pci/drm/amd/include/v12_structs.h

28

uint32_t shadow_base_lo; // offset: 0 (0x0)

sys/dev/pci/drm/amd/include/v12_structs.h

280

uint32_t reserved_252; // offset: 252 (0xFC)

sys/dev/pci/drm/amd/include/v12_structs.h

281

uint32_t reserved_253; // offset: 253 (0xFD)

sys/dev/pci/drm/amd/include/v12_structs.h

282

uint32_t reserved_254; // offset: 254 (0xFE)

sys/dev/pci/drm/amd/include/v12_structs.h

283

uint32_t reserved_255; // offset: 255 (0xFF)

sys/dev/pci/drm/amd/include/v12_structs.h

284

uint32_t reserved_256; // offset: 256 (0x100)

sys/dev/pci/drm/amd/include/v12_structs.h

285

uint32_t reserved_257; // offset: 257 (0x101)

sys/dev/pci/drm/amd/include/v12_structs.h

286

uint32_t reserved_258; // offset: 258 (0x102)

sys/dev/pci/drm/amd/include/v12_structs.h

287

uint32_t reserved_259; // offset: 259 (0x103)

sys/dev/pci/drm/amd/include/v12_structs.h

288

uint32_t reserved_260; // offset: 260 (0x104)

sys/dev/pci/drm/amd/include/v12_structs.h

289

uint32_t reserved_261; // offset: 261 (0x105)

sys/dev/pci/drm/amd/include/v12_structs.h

29

uint32_t shadow_base_hi; // offset: 1 (0x1)

sys/dev/pci/drm/amd/include/v12_structs.h

290

uint32_t reserved_262; // offset: 262 (0x106)

sys/dev/pci/drm/amd/include/v12_structs.h

291

uint32_t reserved_263; // offset: 263 (0x107)

sys/dev/pci/drm/amd/include/v12_structs.h

292

uint32_t reserved_264; // offset: 264 (0x108)

sys/dev/pci/drm/amd/include/v12_structs.h

293

uint32_t reserved_265; // offset: 265 (0x109)

sys/dev/pci/drm/amd/include/v12_structs.h

294

uint32_t reserved_266; // offset: 266 (0x10A)

sys/dev/pci/drm/amd/include/v12_structs.h

295

uint32_t reserved_267; // offset: 267 (0x10B)

sys/dev/pci/drm/amd/include/v12_structs.h

296

uint32_t reserved_268; // offset: 268 (0x10C)

sys/dev/pci/drm/amd/include/v12_structs.h

297

uint32_t reserved_269; // offset: 269 (0x10D)

sys/dev/pci/drm/amd/include/v12_structs.h

298

uint32_t reserved_270; // offset: 270 (0x10E)

sys/dev/pci/drm/amd/include/v12_structs.h

299

uint32_t reserved_271; // offset: 271 (0x10F)

sys/dev/pci/drm/amd/include/v12_structs.h

30

uint32_t reserved_2; // offset: 2 (0x2)

sys/dev/pci/drm/amd/include/v12_structs.h

300

uint32_t dfwx_flags; // offset: 272 (0x110)

sys/dev/pci/drm/amd/include/v12_structs.h

301

uint32_t dfwx_slot; // offset: 273 (0x111)

sys/dev/pci/drm/amd/include/v12_structs.h

302

uint32_t dfwx_client_data_addr_lo; // offset: 274 (0x112)

sys/dev/pci/drm/amd/include/v12_structs.h

303

uint32_t dfwx_client_data_addr_hi; // offset: 275 (0x113)

sys/dev/pci/drm/amd/include/v12_structs.h

304

uint32_t reserved_276; // offset: 276 (0x114)

sys/dev/pci/drm/amd/include/v12_structs.h

305

uint32_t reserved_277; // offset: 277 (0x115)

sys/dev/pci/drm/amd/include/v12_structs.h

306

uint32_t reserved_278; // offset: 278 (0x116)

sys/dev/pci/drm/amd/include/v12_structs.h

307

uint32_t reserved_279; // offset: 279 (0x117)

sys/dev/pci/drm/amd/include/v12_structs.h

308

uint32_t reserved_280; // offset: 280 (0x118)

sys/dev/pci/drm/amd/include/v12_structs.h

309

uint32_t reserved_281; // offset: 281 (0x119)

sys/dev/pci/drm/amd/include/v12_structs.h

31

uint32_t reserved_3; // offset: 3 (0x3)

sys/dev/pci/drm/amd/include/v12_structs.h

310

uint32_t reserved_282; // offset: 282 (0x11A)

sys/dev/pci/drm/amd/include/v12_structs.h

311

uint32_t reserved_283; // offset: 283 (0x11B)

sys/dev/pci/drm/amd/include/v12_structs.h

312

uint32_t reserved_284; // offset: 284 (0x11C)

sys/dev/pci/drm/amd/include/v12_structs.h

313

uint32_t reserved_285; // offset: 285 (0x11D)

sys/dev/pci/drm/amd/include/v12_structs.h

314

uint32_t reserved_286; // offset: 286 (0x11E)

sys/dev/pci/drm/amd/include/v12_structs.h

315

uint32_t reserved_287; // offset: 287 (0x11F)

sys/dev/pci/drm/amd/include/v12_structs.h

316

uint32_t reserved_288; // offset: 288 (0x120)

sys/dev/pci/drm/amd/include/v12_structs.h

317

uint32_t reserved_289; // offset: 289 (0x121)

sys/dev/pci/drm/amd/include/v12_structs.h

318

uint32_t reserved_290; // offset: 290 (0x122)

sys/dev/pci/drm/amd/include/v12_structs.h

319

uint32_t reserved_291; // offset: 291 (0x123)

sys/dev/pci/drm/amd/include/v12_structs.h

32

uint32_t fw_work_area_base_lo; // offset: 4 (0x4)

sys/dev/pci/drm/amd/include/v12_structs.h

320

uint32_t reserved_292; // offset: 292 (0x124)

sys/dev/pci/drm/amd/include/v12_structs.h

321

uint32_t reserved_293; // offset: 293 (0x125)

sys/dev/pci/drm/amd/include/v12_structs.h

322

uint32_t reserved_294; // offset: 294 (0x126)

sys/dev/pci/drm/amd/include/v12_structs.h

323

uint32_t reserved_295; // offset: 295 (0x127)

sys/dev/pci/drm/amd/include/v12_structs.h

324

uint32_t reserved_296; // offset: 296 (0x128)

sys/dev/pci/drm/amd/include/v12_structs.h

325

uint32_t reserved_297; // offset: 297 (0x129)

sys/dev/pci/drm/amd/include/v12_structs.h

326

uint32_t reserved_298; // offset: 298 (0x12A)

sys/dev/pci/drm/amd/include/v12_structs.h

327

uint32_t reserved_299; // offset: 299 (0x12B)

sys/dev/pci/drm/amd/include/v12_structs.h

328

uint32_t reserved_300; // offset: 300 (0x12C)

sys/dev/pci/drm/amd/include/v12_structs.h

329

uint32_t reserved_301; // offset: 301 (0x12D)

sys/dev/pci/drm/amd/include/v12_structs.h

33

uint32_t fw_work_area_base_hi; // offset: 5 (0x5)

sys/dev/pci/drm/amd/include/v12_structs.h

330

uint32_t reserved_302; // offset: 302 (0x12E)

sys/dev/pci/drm/amd/include/v12_structs.h

331

uint32_t reserved_303; // offset: 303 (0x12F)

sys/dev/pci/drm/amd/include/v12_structs.h

332

uint32_t reserved_304; // offset: 304 (0x130)

sys/dev/pci/drm/amd/include/v12_structs.h

333

uint32_t reserved_305; // offset: 305 (0x131)

sys/dev/pci/drm/amd/include/v12_structs.h

334

uint32_t reserved_306; // offset: 306 (0x132)

sys/dev/pci/drm/amd/include/v12_structs.h

335

uint32_t reserved_307; // offset: 307 (0x133)

sys/dev/pci/drm/amd/include/v12_structs.h

336

uint32_t reserved_308; // offset: 308 (0x134)

sys/dev/pci/drm/amd/include/v12_structs.h

337

uint32_t reserved_309; // offset: 309 (0x135)

sys/dev/pci/drm/amd/include/v12_structs.h

338

uint32_t reserved_310; // offset: 310 (0x136)

sys/dev/pci/drm/amd/include/v12_structs.h

339

uint32_t reserved_311; // offset: 311 (0x137)

sys/dev/pci/drm/amd/include/v12_structs.h

34

uint32_t shadow_initialized; // offset: 6 (0x6)

sys/dev/pci/drm/amd/include/v12_structs.h

340

uint32_t reserved_312; // offset: 312 (0x138)

sys/dev/pci/drm/amd/include/v12_structs.h

341

uint32_t reserved_313; // offset: 313 (0x139)

sys/dev/pci/drm/amd/include/v12_structs.h

342

uint32_t reserved_314; // offset: 314 (0x13A)

sys/dev/pci/drm/amd/include/v12_structs.h

343

uint32_t reserved_315; // offset: 315 (0x13B)

sys/dev/pci/drm/amd/include/v12_structs.h

344

uint32_t reserved_316; // offset: 316 (0x13C)

sys/dev/pci/drm/amd/include/v12_structs.h

345

uint32_t reserved_317; // offset: 317 (0x13D)

sys/dev/pci/drm/amd/include/v12_structs.h

346

uint32_t reserved_318; // offset: 318 (0x13E)

sys/dev/pci/drm/amd/include/v12_structs.h

347

uint32_t reserved_319; // offset: 319 (0x13F)

sys/dev/pci/drm/amd/include/v12_structs.h

348

uint32_t reserved_320; // offset: 320 (0x140)

sys/dev/pci/drm/amd/include/v12_structs.h

349

uint32_t reserved_321; // offset: 321 (0x141)

sys/dev/pci/drm/amd/include/v12_structs.h

35

uint32_t ib_vmid; // offset: 7 (0x7)

sys/dev/pci/drm/amd/include/v12_structs.h

350

uint32_t reserved_322; // offset: 322 (0x142)

sys/dev/pci/drm/amd/include/v12_structs.h

351

uint32_t reserved_323; // offset: 323 (0x143)

sys/dev/pci/drm/amd/include/v12_structs.h

352

uint32_t reserved_324; // offset: 324 (0x144)

sys/dev/pci/drm/amd/include/v12_structs.h

353

uint32_t reserved_325; // offset: 325 (0x145)

sys/dev/pci/drm/amd/include/v12_structs.h

354

uint32_t reserved_326; // offset: 326 (0x146)

sys/dev/pci/drm/amd/include/v12_structs.h

355

uint32_t reserved_327; // offset: 327 (0x147)

sys/dev/pci/drm/amd/include/v12_structs.h

356

uint32_t reserved_328; // offset: 328 (0x148)

sys/dev/pci/drm/amd/include/v12_structs.h

357

uint32_t reserved_329; // offset: 329 (0x149)

sys/dev/pci/drm/amd/include/v12_structs.h

358

uint32_t reserved_330; // offset: 330 (0x14A)

sys/dev/pci/drm/amd/include/v12_structs.h

359

uint32_t reserved_331; // offset: 331 (0x14B)

sys/dev/pci/drm/amd/include/v12_structs.h

36

uint32_t reserved_8; // offset: 8 (0x8)

sys/dev/pci/drm/amd/include/v12_structs.h

360

uint32_t reserved_332; // offset: 332 (0x14C)

sys/dev/pci/drm/amd/include/v12_structs.h

361

uint32_t reserved_333; // offset: 333 (0x14D)

sys/dev/pci/drm/amd/include/v12_structs.h

362

uint32_t reserved_334; // offset: 334 (0x14E)

sys/dev/pci/drm/amd/include/v12_structs.h

363

uint32_t reserved_335; // offset: 335 (0x14F)

sys/dev/pci/drm/amd/include/v12_structs.h

364

uint32_t reserved_336; // offset: 336 (0x150)

sys/dev/pci/drm/amd/include/v12_structs.h

365

uint32_t reserved_337; // offset: 337 (0x151)

sys/dev/pci/drm/amd/include/v12_structs.h

366

uint32_t reserved_338; // offset: 338 (0x152)

sys/dev/pci/drm/amd/include/v12_structs.h

367

uint32_t reserved_339; // offset: 339 (0x153)

sys/dev/pci/drm/amd/include/v12_structs.h

368

uint32_t reserved_340; // offset: 340 (0x154)

sys/dev/pci/drm/amd/include/v12_structs.h

369

uint32_t reserved_341; // offset: 341 (0x155)

sys/dev/pci/drm/amd/include/v12_structs.h

37

uint32_t reserved_9; // offset: 9 (0x9)

sys/dev/pci/drm/amd/include/v12_structs.h

370

uint32_t reserved_342; // offset: 342 (0x156)

sys/dev/pci/drm/amd/include/v12_structs.h

371

uint32_t reserved_343; // offset: 343 (0x157)

sys/dev/pci/drm/amd/include/v12_structs.h

372

uint32_t reserved_344; // offset: 344 (0x158)

sys/dev/pci/drm/amd/include/v12_structs.h

373

uint32_t reserved_345; // offset: 345 (0x159)

sys/dev/pci/drm/amd/include/v12_structs.h

374

uint32_t reserved_346; // offset: 346 (0x15A)

sys/dev/pci/drm/amd/include/v12_structs.h

375

uint32_t reserved_347; // offset: 347 (0x15B)

sys/dev/pci/drm/amd/include/v12_structs.h

376

uint32_t reserved_348; // offset: 348 (0x15C)

sys/dev/pci/drm/amd/include/v12_structs.h

377

uint32_t reserved_349; // offset: 349 (0x15D)

sys/dev/pci/drm/amd/include/v12_structs.h

378

uint32_t reserved_350; // offset: 350 (0x15E)

sys/dev/pci/drm/amd/include/v12_structs.h

379

uint32_t reserved_351; // offset: 351 (0x15F)

sys/dev/pci/drm/amd/include/v12_structs.h

38

uint32_t reserved_10; // offset: 10 (0xA)

sys/dev/pci/drm/amd/include/v12_structs.h

380

uint32_t reserved_352; // offset: 352 (0x160)

sys/dev/pci/drm/amd/include/v12_structs.h

381

uint32_t reserved_353; // offset: 353 (0x161)

sys/dev/pci/drm/amd/include/v12_structs.h

382

uint32_t reserved_354; // offset: 354 (0x162)

sys/dev/pci/drm/amd/include/v12_structs.h

383

uint32_t reserved_355; // offset: 355 (0x163)

sys/dev/pci/drm/amd/include/v12_structs.h

384

uint32_t reserved_356; // offset: 356 (0x164)

sys/dev/pci/drm/amd/include/v12_structs.h

385

uint32_t reserved_357; // offset: 357 (0x165)

sys/dev/pci/drm/amd/include/v12_structs.h

386

uint32_t reserved_358; // offset: 358 (0x166)

sys/dev/pci/drm/amd/include/v12_structs.h

387

uint32_t reserved_359; // offset: 359 (0x167)

sys/dev/pci/drm/amd/include/v12_structs.h

388

uint32_t reserved_360; // offset: 360 (0x168)

sys/dev/pci/drm/amd/include/v12_structs.h

389

uint32_t reserved_361; // offset: 361 (0x169)

sys/dev/pci/drm/amd/include/v12_structs.h

39

uint32_t reserved_11; // offset: 11 (0xB)

sys/dev/pci/drm/amd/include/v12_structs.h

390

uint32_t reserved_362; // offset: 362 (0x16A)

sys/dev/pci/drm/amd/include/v12_structs.h

391

uint32_t reserved_363; // offset: 363 (0x16B)

sys/dev/pci/drm/amd/include/v12_structs.h

392

uint32_t reserved_364; // offset: 364 (0x16C)

sys/dev/pci/drm/amd/include/v12_structs.h

393

uint32_t reserved_365; // offset: 365 (0x16D)

sys/dev/pci/drm/amd/include/v12_structs.h

394

uint32_t reserved_366; // offset: 366 (0x16E)

sys/dev/pci/drm/amd/include/v12_structs.h

395

uint32_t reserved_367; // offset: 367 (0x16F)

sys/dev/pci/drm/amd/include/v12_structs.h

396

uint32_t reserved_368; // offset: 368 (0x170)

sys/dev/pci/drm/amd/include/v12_structs.h

397

uint32_t reserved_369; // offset: 369 (0x171)

sys/dev/pci/drm/amd/include/v12_structs.h

398

uint32_t reserved_370; // offset: 370 (0x172)

sys/dev/pci/drm/amd/include/v12_structs.h

399

uint32_t reserved_371; // offset: 371 (0x173)

sys/dev/pci/drm/amd/include/v12_structs.h

40

uint32_t reserved_12; // offset: 12 (0xC)

sys/dev/pci/drm/amd/include/v12_structs.h

400

uint32_t reserved_372; // offset: 372 (0x174)

sys/dev/pci/drm/amd/include/v12_structs.h

401

uint32_t reserved_373; // offset: 373 (0x175)

sys/dev/pci/drm/amd/include/v12_structs.h

402

uint32_t reserved_374; // offset: 374 (0x176)

sys/dev/pci/drm/amd/include/v12_structs.h

403

uint32_t reserved_375; // offset: 375 (0x177)

sys/dev/pci/drm/amd/include/v12_structs.h

404

uint32_t reserved_376; // offset: 376 (0x178)

sys/dev/pci/drm/amd/include/v12_structs.h

405

uint32_t reserved_377; // offset: 377 (0x179)

sys/dev/pci/drm/amd/include/v12_structs.h

406

uint32_t reserved_378; // offset: 378 (0x17A)

sys/dev/pci/drm/amd/include/v12_structs.h

407

uint32_t reserved_379; // offset: 379 (0x17B)

sys/dev/pci/drm/amd/include/v12_structs.h

408

uint32_t reserved_380; // offset: 380 (0x17C)

sys/dev/pci/drm/amd/include/v12_structs.h

409

uint32_t reserved_381; // offset: 381 (0x17D)

sys/dev/pci/drm/amd/include/v12_structs.h

41

uint32_t reserved_13; // offset: 13 (0xD)

sys/dev/pci/drm/amd/include/v12_structs.h

410

uint32_t reserved_382; // offset: 382 (0x17E)

sys/dev/pci/drm/amd/include/v12_structs.h

411

uint32_t reserved_383; // offset: 383 (0x17F)

sys/dev/pci/drm/amd/include/v12_structs.h

412

uint32_t reserved_384; // offset: 384 (0x180)

sys/dev/pci/drm/amd/include/v12_structs.h

413

uint32_t reserved_385; // offset: 385 (0x181)

sys/dev/pci/drm/amd/include/v12_structs.h

414

uint32_t reserved_386; // offset: 386 (0x182)

sys/dev/pci/drm/amd/include/v12_structs.h

415

uint32_t reserved_387; // offset: 387 (0x183)

sys/dev/pci/drm/amd/include/v12_structs.h

416

uint32_t reserved_388; // offset: 388 (0x184)

sys/dev/pci/drm/amd/include/v12_structs.h

417

uint32_t reserved_389; // offset: 389 (0x185)

sys/dev/pci/drm/amd/include/v12_structs.h

418

uint32_t reserved_390; // offset: 390 (0x186)

sys/dev/pci/drm/amd/include/v12_structs.h

419

uint32_t reserved_391; // offset: 391 (0x187)

sys/dev/pci/drm/amd/include/v12_structs.h

42

uint32_t reserved_14; // offset: 14 (0xE)

sys/dev/pci/drm/amd/include/v12_structs.h

420

uint32_t reserved_392; // offset: 392 (0x188)

sys/dev/pci/drm/amd/include/v12_structs.h

421

uint32_t reserved_393; // offset: 393 (0x189)

sys/dev/pci/drm/amd/include/v12_structs.h

422

uint32_t reserved_394; // offset: 394 (0x18A)

sys/dev/pci/drm/amd/include/v12_structs.h

423

uint32_t reserved_395; // offset: 395 (0x18B)

sys/dev/pci/drm/amd/include/v12_structs.h

424

uint32_t reserved_396; // offset: 396 (0x18C)

sys/dev/pci/drm/amd/include/v12_structs.h

425

uint32_t reserved_397; // offset: 397 (0x18D)

sys/dev/pci/drm/amd/include/v12_structs.h

426

uint32_t reserved_398; // offset: 398 (0x18E)

sys/dev/pci/drm/amd/include/v12_structs.h

427

uint32_t reserved_399; // offset: 399 (0x18F)

sys/dev/pci/drm/amd/include/v12_structs.h

428

uint32_t reserved_400; // offset: 400 (0x190)

sys/dev/pci/drm/amd/include/v12_structs.h

429

uint32_t reserved_401; // offset: 401 (0x191)

sys/dev/pci/drm/amd/include/v12_structs.h

43

uint32_t reserved_15; // offset: 15 (0xF)

sys/dev/pci/drm/amd/include/v12_structs.h

430

uint32_t reserved_402; // offset: 402 (0x192)

sys/dev/pci/drm/amd/include/v12_structs.h

431

uint32_t reserved_403; // offset: 403 (0x193)

sys/dev/pci/drm/amd/include/v12_structs.h

432

uint32_t reserved_404; // offset: 404 (0x194)

sys/dev/pci/drm/amd/include/v12_structs.h

433

uint32_t reserved_405; // offset: 405 (0x195)

sys/dev/pci/drm/amd/include/v12_structs.h

434

uint32_t reserved_406; // offset: 406 (0x196)

sys/dev/pci/drm/amd/include/v12_structs.h

435

uint32_t reserved_407; // offset: 407 (0x197)

sys/dev/pci/drm/amd/include/v12_structs.h

436

uint32_t reserved_408; // offset: 408 (0x198)

sys/dev/pci/drm/amd/include/v12_structs.h

437

uint32_t reserved_409; // offset: 409 (0x199)

sys/dev/pci/drm/amd/include/v12_structs.h

438

uint32_t reserved_410; // offset: 410 (0x19A)

sys/dev/pci/drm/amd/include/v12_structs.h

439

uint32_t reserved_411; // offset: 411 (0x19B)

sys/dev/pci/drm/amd/include/v12_structs.h

44

uint32_t reserved_16; // offset: 16 (0x10)

sys/dev/pci/drm/amd/include/v12_structs.h

440

uint32_t reserved_412; // offset: 412 (0x19C)

sys/dev/pci/drm/amd/include/v12_structs.h

441

uint32_t reserved_413; // offset: 413 (0x19D)

sys/dev/pci/drm/amd/include/v12_structs.h

442

uint32_t reserved_414; // offset: 414 (0x19E)

sys/dev/pci/drm/amd/include/v12_structs.h

443

uint32_t reserved_415; // offset: 415 (0x19F)

sys/dev/pci/drm/amd/include/v12_structs.h

444

uint32_t reserved_416; // offset: 416 (0x1A0)

sys/dev/pci/drm/amd/include/v12_structs.h

445

uint32_t reserved_417; // offset: 417 (0x1A1)

sys/dev/pci/drm/amd/include/v12_structs.h

446

uint32_t reserved_418; // offset: 418 (0x1A2)

sys/dev/pci/drm/amd/include/v12_structs.h

447

uint32_t reserved_419; // offset: 419 (0x1A3)

sys/dev/pci/drm/amd/include/v12_structs.h

448

uint32_t reserved_420; // offset: 420 (0x1A4)

sys/dev/pci/drm/amd/include/v12_structs.h

449

uint32_t reserved_421; // offset: 421 (0x1A5)

sys/dev/pci/drm/amd/include/v12_structs.h

45

uint32_t reserved_17; // offset: 17 (0x11)

sys/dev/pci/drm/amd/include/v12_structs.h

450

uint32_t reserved_422; // offset: 422 (0x1A6)

sys/dev/pci/drm/amd/include/v12_structs.h

451

uint32_t reserved_423; // offset: 423 (0x1A7)

sys/dev/pci/drm/amd/include/v12_structs.h

452

uint32_t reserved_424; // offset: 424 (0x1A8)

sys/dev/pci/drm/amd/include/v12_structs.h

453

uint32_t reserved_425; // offset: 425 (0x1A9)

sys/dev/pci/drm/amd/include/v12_structs.h

454

uint32_t reserved_426; // offset: 426 (0x1AA)

sys/dev/pci/drm/amd/include/v12_structs.h

455

uint32_t reserved_427; // offset: 427 (0x1AB)

sys/dev/pci/drm/amd/include/v12_structs.h

456

uint32_t reserved_428; // offset: 428 (0x1AC)

sys/dev/pci/drm/amd/include/v12_structs.h

457

uint32_t reserved_429; // offset: 429 (0x1AD)

sys/dev/pci/drm/amd/include/v12_structs.h

458

uint32_t reserved_430; // offset: 430 (0x1AE)

sys/dev/pci/drm/amd/include/v12_structs.h

459

uint32_t reserved_431; // offset: 431 (0x1AF)

sys/dev/pci/drm/amd/include/v12_structs.h

46

uint32_t reserved_18; // offset: 18 (0x12)

sys/dev/pci/drm/amd/include/v12_structs.h

460

uint32_t reserved_432; // offset: 432 (0x1B0)

sys/dev/pci/drm/amd/include/v12_structs.h

461

uint32_t reserved_433; // offset: 433 (0x1B1)

sys/dev/pci/drm/amd/include/v12_structs.h

462

uint32_t reserved_434; // offset: 434 (0x1B2)

sys/dev/pci/drm/amd/include/v12_structs.h

463

uint32_t reserved_435; // offset: 435 (0x1B3)

sys/dev/pci/drm/amd/include/v12_structs.h

464

uint32_t reserved_436; // offset: 436 (0x1B4)

sys/dev/pci/drm/amd/include/v12_structs.h

465

uint32_t reserved_437; // offset: 437 (0x1B5)

sys/dev/pci/drm/amd/include/v12_structs.h

466

uint32_t reserved_438; // offset: 438 (0x1B6)

sys/dev/pci/drm/amd/include/v12_structs.h

467

uint32_t reserved_439; // offset: 439 (0x1B7)

sys/dev/pci/drm/amd/include/v12_structs.h

468

uint32_t reserved_440; // offset: 440 (0x1B8)

sys/dev/pci/drm/amd/include/v12_structs.h

469

uint32_t reserved_441; // offset: 441 (0x1B9)

sys/dev/pci/drm/amd/include/v12_structs.h

47

uint32_t reserved_19; // offset: 19 (0x13)

sys/dev/pci/drm/amd/include/v12_structs.h

470

uint32_t reserved_442; // offset: 442 (0x1BA)

sys/dev/pci/drm/amd/include/v12_structs.h

471

uint32_t reserved_443; // offset: 443 (0x1BB)

sys/dev/pci/drm/amd/include/v12_structs.h

472

uint32_t reserved_444; // offset: 444 (0x1BC)

sys/dev/pci/drm/amd/include/v12_structs.h

473

uint32_t reserved_445; // offset: 445 (0x1BD)

sys/dev/pci/drm/amd/include/v12_structs.h

474

uint32_t reserved_446; // offset: 446 (0x1BE)

sys/dev/pci/drm/amd/include/v12_structs.h

475

uint32_t reserved_447; // offset: 447 (0x1BF)

sys/dev/pci/drm/amd/include/v12_structs.h

476

uint32_t reserved_448; // offset: 448 (0x1C0)

sys/dev/pci/drm/amd/include/v12_structs.h

477

uint32_t reserved_449; // offset: 449 (0x1C1)

sys/dev/pci/drm/amd/include/v12_structs.h

478

uint32_t reserved_450; // offset: 450 (0x1C2)

sys/dev/pci/drm/amd/include/v12_structs.h

479

uint32_t reserved_451; // offset: 451 (0x1C3)

sys/dev/pci/drm/amd/include/v12_structs.h

48

uint32_t reserved_20; // offset: 20 (0x14)

sys/dev/pci/drm/amd/include/v12_structs.h

480

uint32_t reserved_452; // offset: 452 (0x1C4)

sys/dev/pci/drm/amd/include/v12_structs.h

481

uint32_t reserved_453; // offset: 453 (0x1C5)

sys/dev/pci/drm/amd/include/v12_structs.h

482

uint32_t reserved_454; // offset: 454 (0x1C6)

sys/dev/pci/drm/amd/include/v12_structs.h

483

uint32_t reserved_455; // offset: 455 (0x1C7)

sys/dev/pci/drm/amd/include/v12_structs.h

484

uint32_t reserved_456; // offset: 456 (0x1C8)

sys/dev/pci/drm/amd/include/v12_structs.h

485

uint32_t reserved_457; // offset: 457 (0x1C9)

sys/dev/pci/drm/amd/include/v12_structs.h

486

uint32_t reserved_458; // offset: 458 (0x1CA)

sys/dev/pci/drm/amd/include/v12_structs.h

487

uint32_t reserved_459; // offset: 459 (0x1CB)

sys/dev/pci/drm/amd/include/v12_structs.h

488

uint32_t reserved_460; // offset: 460 (0x1CC)

sys/dev/pci/drm/amd/include/v12_structs.h

489

uint32_t reserved_461; // offset: 461 (0x1CD)

sys/dev/pci/drm/amd/include/v12_structs.h

49

uint32_t reserved_21; // offset: 21 (0x15)

sys/dev/pci/drm/amd/include/v12_structs.h

490

uint32_t reserved_462; // offset: 462 (0x1CE)

sys/dev/pci/drm/amd/include/v12_structs.h

491

uint32_t reserved_463; // offset: 463 (0x1CF)

sys/dev/pci/drm/amd/include/v12_structs.h

492

uint32_t reserved_464; // offset: 464 (0x1D0)

sys/dev/pci/drm/amd/include/v12_structs.h

493

uint32_t reserved_465; // offset: 465 (0x1D1)

sys/dev/pci/drm/amd/include/v12_structs.h

494

uint32_t reserved_466; // offset: 466 (0x1D2)

sys/dev/pci/drm/amd/include/v12_structs.h

495

uint32_t reserved_467; // offset: 467 (0x1D3)

sys/dev/pci/drm/amd/include/v12_structs.h

496

uint32_t reserved_468; // offset: 468 (0x1D4)

sys/dev/pci/drm/amd/include/v12_structs.h

497

uint32_t reserved_469; // offset: 469 (0x1D5)

sys/dev/pci/drm/amd/include/v12_structs.h

498

uint32_t reserved_470; // offset: 470 (0x1D6)

sys/dev/pci/drm/amd/include/v12_structs.h

499

uint32_t reserved_471; // offset: 471 (0x1D7)

sys/dev/pci/drm/amd/include/v12_structs.h

50

uint32_t reserved_22; // offset: 22 (0x16)

sys/dev/pci/drm/amd/include/v12_structs.h

500

uint32_t reserved_472; // offset: 472 (0x1D8)

sys/dev/pci/drm/amd/include/v12_structs.h

501

uint32_t reserved_473; // offset: 473 (0x1D9)

sys/dev/pci/drm/amd/include/v12_structs.h

502

uint32_t reserved_474; // offset: 474 (0x1DA)

sys/dev/pci/drm/amd/include/v12_structs.h

503

uint32_t reserved_475; // offset: 475 (0x1DB)

sys/dev/pci/drm/amd/include/v12_structs.h

504

uint32_t reserved_476; // offset: 476 (0x1DC)

sys/dev/pci/drm/amd/include/v12_structs.h

505

uint32_t reserved_477; // offset: 477 (0x1DD)

sys/dev/pci/drm/amd/include/v12_structs.h

506

uint32_t reserved_478; // offset: 478 (0x1DE)

sys/dev/pci/drm/amd/include/v12_structs.h

507

uint32_t reserved_479; // offset: 479 (0x1DF)

sys/dev/pci/drm/amd/include/v12_structs.h

508

uint32_t reserved_480; // offset: 480 (0x1E0)

sys/dev/pci/drm/amd/include/v12_structs.h

509

uint32_t reserved_481; // offset: 481 (0x1E1)

sys/dev/pci/drm/amd/include/v12_structs.h

51

uint32_t reserved_23; // offset: 23 (0x17)

sys/dev/pci/drm/amd/include/v12_structs.h

510

uint32_t reserved_482; // offset: 482 (0x1E2)

sys/dev/pci/drm/amd/include/v12_structs.h

511

uint32_t reserved_483; // offset: 483 (0x1E3)

sys/dev/pci/drm/amd/include/v12_structs.h

512

uint32_t reserved_484; // offset: 484 (0x1E4)

sys/dev/pci/drm/amd/include/v12_structs.h

513

uint32_t reserved_485; // offset: 485 (0x1E5)

sys/dev/pci/drm/amd/include/v12_structs.h

514

uint32_t reserved_486; // offset: 486 (0x1E6)

sys/dev/pci/drm/amd/include/v12_structs.h

515

uint32_t reserved_487; // offset: 487 (0x1E7)

sys/dev/pci/drm/amd/include/v12_structs.h

516

uint32_t reserved_488; // offset: 488 (0x1E8)

sys/dev/pci/drm/amd/include/v12_structs.h

517

uint32_t reserved_489; // offset: 489 (0x1E9)

sys/dev/pci/drm/amd/include/v12_structs.h

518

uint32_t reserved_490; // offset: 490 (0x1EA)

sys/dev/pci/drm/amd/include/v12_structs.h

519

uint32_t reserved_491; // offset: 491 (0x1EB)

sys/dev/pci/drm/amd/include/v12_structs.h

52

uint32_t reserved_24; // offset: 24 (0x18)

sys/dev/pci/drm/amd/include/v12_structs.h

520

uint32_t reserved_492; // offset: 492 (0x1EC)

sys/dev/pci/drm/amd/include/v12_structs.h

521

uint32_t reserved_493; // offset: 493 (0x1ED)

sys/dev/pci/drm/amd/include/v12_structs.h

522

uint32_t reserved_494; // offset: 494 (0x1EE)

sys/dev/pci/drm/amd/include/v12_structs.h

523

uint32_t reserved_495; // offset: 495 (0x1EF)

sys/dev/pci/drm/amd/include/v12_structs.h

524

uint32_t reserved_496; // offset: 496 (0x1F0)

sys/dev/pci/drm/amd/include/v12_structs.h

525

uint32_t reserved_497; // offset: 497 (0x1F1)

sys/dev/pci/drm/amd/include/v12_structs.h

526

uint32_t reserved_498; // offset: 498 (0x1F2)

sys/dev/pci/drm/amd/include/v12_structs.h

527

uint32_t reserved_499; // offset: 499 (0x1F3)

sys/dev/pci/drm/amd/include/v12_structs.h

528

uint32_t reserved_500; // offset: 500 (0x1F4)

sys/dev/pci/drm/amd/include/v12_structs.h

529

uint32_t reserved_501; // offset: 501 (0x1F5)

sys/dev/pci/drm/amd/include/v12_structs.h

53

uint32_t reserved_25; // offset: 25 (0x19)

sys/dev/pci/drm/amd/include/v12_structs.h

530

uint32_t reserved_502; // offset: 502 (0x1F6)

sys/dev/pci/drm/amd/include/v12_structs.h

531

uint32_t reserved_503; // offset: 503 (0x1F7)

sys/dev/pci/drm/amd/include/v12_structs.h

532

uint32_t reserved_504; // offset: 504 (0x1F8)

sys/dev/pci/drm/amd/include/v12_structs.h

533

uint32_t reserved_505; // offset: 505 (0x1F9)

sys/dev/pci/drm/amd/include/v12_structs.h

534

uint32_t reserved_506; // offset: 506 (0x1FA)

sys/dev/pci/drm/amd/include/v12_structs.h

535

uint32_t reserved_507; // offset: 507 (0x1FB)

sys/dev/pci/drm/amd/include/v12_structs.h

536

uint32_t reserved_508; // offset: 508 (0x1FC)

sys/dev/pci/drm/amd/include/v12_structs.h

537

uint32_t reserved_509; // offset: 509 (0x1FD)

sys/dev/pci/drm/amd/include/v12_structs.h

538

uint32_t fence_address_lo; // offset: 510 (0x1FE)

sys/dev/pci/drm/amd/include/v12_structs.h

539

uint32_t fence_address_hi; // offset: 511 (0x1FF)

sys/dev/pci/drm/amd/include/v12_structs.h

54

uint32_t reserved_26; // offset: 26 (0x1A)

sys/dev/pci/drm/amd/include/v12_structs.h

543

uint32_t sdmax_rlcx_rb_cntl; // offset: 0 (0x0)

sys/dev/pci/drm/amd/include/v12_structs.h

544

uint32_t sdmax_rlcx_rb_base; // offset: 1 (0x1)

sys/dev/pci/drm/amd/include/v12_structs.h

545

uint32_t sdmax_rlcx_rb_base_hi; // offset: 2 (0x2)

sys/dev/pci/drm/amd/include/v12_structs.h

546

uint32_t sdmax_rlcx_rb_rptr; // offset: 3 (0x3)

sys/dev/pci/drm/amd/include/v12_structs.h

547

uint32_t sdmax_rlcx_rb_rptr_hi; // offset: 4 (0x4)

sys/dev/pci/drm/amd/include/v12_structs.h

548

uint32_t sdmax_rlcx_rb_wptr; // offset: 5 (0x5)

sys/dev/pci/drm/amd/include/v12_structs.h

549

uint32_t sdmax_rlcx_rb_wptr_hi; // offset: 6 (0x6)

sys/dev/pci/drm/amd/include/v12_structs.h

55

uint32_t reserved_27; // offset: 27 (0x1B)

sys/dev/pci/drm/amd/include/v12_structs.h

550

uint32_t sdmax_rlcx_rb_rptr_addr_lo; // offset: 7 (0x7)

sys/dev/pci/drm/amd/include/v12_structs.h

551

uint32_t sdmax_rlcx_rb_rptr_addr_hi; // offset: 8 (0x8)

sys/dev/pci/drm/amd/include/v12_structs.h

552

uint32_t sdmax_rlcx_ib_cntl; // offset: 9 (0x9)

sys/dev/pci/drm/amd/include/v12_structs.h

553

uint32_t sdmax_rlcx_ib_rptr; // offset: 10 (0xA)

sys/dev/pci/drm/amd/include/v12_structs.h

554

uint32_t sdmax_rlcx_ib_offset; // offset: 11 (0xB)

sys/dev/pci/drm/amd/include/v12_structs.h

555

uint32_t sdmax_rlcx_ib_base_lo; // offset: 12 (0xC)

sys/dev/pci/drm/amd/include/v12_structs.h

556

uint32_t sdmax_rlcx_ib_base_hi; // offset: 13 (0xD)

sys/dev/pci/drm/amd/include/v12_structs.h

557

uint32_t sdmax_rlcx_ib_size; // offset: 14 (0xE)

sys/dev/pci/drm/amd/include/v12_structs.h

558

uint32_t sdmax_rlcx_doorbell; // offset: 15 (0xF)

sys/dev/pci/drm/amd/include/v12_structs.h

559

uint32_t sdmax_rlcx_doorbell_log; // offset: 16 (0x10)

sys/dev/pci/drm/amd/include/v12_structs.h

56

uint32_t reserved_28; // offset: 28 (0x1C)

sys/dev/pci/drm/amd/include/v12_structs.h

560

uint32_t sdmax_rlcx_doorbell_offset; // offset: 17 (0x11)

sys/dev/pci/drm/amd/include/v12_structs.h

561

uint32_t sdmax_rlcx_csa_addr_lo; // offset: 18 (0x12)

sys/dev/pci/drm/amd/include/v12_structs.h

562

uint32_t sdmax_rlcx_csa_addr_hi; // offset: 19 (0x13)

sys/dev/pci/drm/amd/include/v12_structs.h

563

uint32_t sdmax_rlcx_sched_cntl; // offset: 20 (0x14)

sys/dev/pci/drm/amd/include/v12_structs.h

564

uint32_t sdmax_rlcx_ib_sub_remain; // offset: 21 (0x15)

sys/dev/pci/drm/amd/include/v12_structs.h

565

uint32_t sdmax_rlcx_preempt; // offset: 22 (0x16)

sys/dev/pci/drm/amd/include/v12_structs.h

566

uint32_t sdmax_rlcx_dummy_reg; // offset: 23 (0x17)

sys/dev/pci/drm/amd/include/v12_structs.h

567

uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo; // offset: 24 (0x18)

sys/dev/pci/drm/amd/include/v12_structs.h

568

uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi; // offset: 25 (0x19)

sys/dev/pci/drm/amd/include/v12_structs.h

569

uint32_t sdmax_rlcx_rb_aql_cntl; // offset: 26 (0x1A)

sys/dev/pci/drm/amd/include/v12_structs.h

57

uint32_t reserved_29; // offset: 29 (0x1D)

sys/dev/pci/drm/amd/include/v12_structs.h

570

uint32_t sdmax_rlcx_minor_ptr_update; // offset: 27 (0x1B)

sys/dev/pci/drm/amd/include/v12_structs.h

571

uint32_t sdmax_rlcx_mcu_dbg0; // offset: 28 (0x1C)

sys/dev/pci/drm/amd/include/v12_structs.h

572

uint32_t sdmax_rlcx_mcu_dbg1; // offset: 29 (0x1D)

sys/dev/pci/drm/amd/include/v12_structs.h

573

uint32_t sdmax_rlcx_context_switch_status; // offset: 30 (0x1E)

sys/dev/pci/drm/amd/include/v12_structs.h

574

uint32_t sdmax_rlcx_midcmd_cntl; // offset: 31 (0x1F)

sys/dev/pci/drm/amd/include/v12_structs.h

575

uint32_t sdmax_rlcx_midcmd_data0; // offset: 32 (0x20)

sys/dev/pci/drm/amd/include/v12_structs.h

576

uint32_t sdmax_rlcx_midcmd_data1; // offset: 33 (0x21)

sys/dev/pci/drm/amd/include/v12_structs.h

577

uint32_t sdmax_rlcx_midcmd_data2; // offset: 34 (0x22)

sys/dev/pci/drm/amd/include/v12_structs.h

578

uint32_t sdmax_rlcx_midcmd_data3; // offset: 35 (0x23)

sys/dev/pci/drm/amd/include/v12_structs.h

579

uint32_t sdmax_rlcx_midcmd_data4; // offset: 36 (0x24)

sys/dev/pci/drm/amd/include/v12_structs.h

58

uint32_t reserved_30; // offset: 30 (0x1E)

sys/dev/pci/drm/amd/include/v12_structs.h

580

uint32_t sdmax_rlcx_midcmd_data5; // offset: 37 (0x25)

sys/dev/pci/drm/amd/include/v12_structs.h

581

uint32_t sdmax_rlcx_midcmd_data6; // offset: 38 (0x26)

sys/dev/pci/drm/amd/include/v12_structs.h

582

uint32_t sdmax_rlcx_midcmd_data7; // offset: 39 (0x27)

sys/dev/pci/drm/amd/include/v12_structs.h

583

uint32_t sdmax_rlcx_midcmd_data8; // offset: 40 (0x28)

sys/dev/pci/drm/amd/include/v12_structs.h

584

uint32_t sdmax_rlcx_midcmd_data9; // offset: 41 (0x29)

sys/dev/pci/drm/amd/include/v12_structs.h

585

uint32_t sdmax_rlcx_midcmd_data10; // offset: 42 (0x2A)

sys/dev/pci/drm/amd/include/v12_structs.h

586

uint32_t sdmax_rlcx_wait_unsatisfied_thd; // offset: 43 (0x2B)

sys/dev/pci/drm/amd/include/v12_structs.h

587

uint32_t sdmax_rlcx_mqd_base_addr_lo; // offset: 44 (0x2C)

sys/dev/pci/drm/amd/include/v12_structs.h

588

uint32_t sdmax_rlcx_mqd_base_addr_hi; // offset: 45 (0x2D)

sys/dev/pci/drm/amd/include/v12_structs.h

589

uint32_t sdmax_rlcx_mqd_control; // offset: 46 (0x2E)

sys/dev/pci/drm/amd/include/v12_structs.h

59

uint32_t reserved_31; // offset: 31 (0x1F)

sys/dev/pci/drm/amd/include/v12_structs.h

590

uint32_t reserved_47; // offset: 47 (0x2F)

sys/dev/pci/drm/amd/include/v12_structs.h

591

uint32_t reserved_48; // offset: 48 (0x30)

sys/dev/pci/drm/amd/include/v12_structs.h

592

uint32_t reserved_49; // offset: 49 (0x31)

sys/dev/pci/drm/amd/include/v12_structs.h

593

uint32_t reserved_50; // offset: 50 (0x32)

sys/dev/pci/drm/amd/include/v12_structs.h

594

uint32_t reserved_51; // offset: 51 (0x33)

sys/dev/pci/drm/amd/include/v12_structs.h

595

uint32_t reserved_52; // offset: 52 (0x34)

sys/dev/pci/drm/amd/include/v12_structs.h

596

uint32_t reserved_53; // offset: 53 (0x35)

sys/dev/pci/drm/amd/include/v12_structs.h

597

uint32_t reserved_54; // offset: 54 (0x36)

sys/dev/pci/drm/amd/include/v12_structs.h

598

uint32_t reserved_55; // offset: 55 (0x37)

sys/dev/pci/drm/amd/include/v12_structs.h

599

uint32_t reserved_56; // offset: 56 (0x38)

sys/dev/pci/drm/amd/include/v12_structs.h

60

uint32_t reserved_32; // offset: 32 (0x20)

sys/dev/pci/drm/amd/include/v12_structs.h

600

uint32_t reserved_57; // offset: 57 (0x39)

sys/dev/pci/drm/amd/include/v12_structs.h

601

uint32_t reserved_58; // offset: 58 (0x3A)

sys/dev/pci/drm/amd/include/v12_structs.h

602

uint32_t reserved_59; // offset: 59 (0x3B)

sys/dev/pci/drm/amd/include/v12_structs.h

603

uint32_t reserved_60; // offset: 60 (0x3C)

sys/dev/pci/drm/amd/include/v12_structs.h

604

uint32_t reserved_61; // offset: 61 (0x3D)

sys/dev/pci/drm/amd/include/v12_structs.h

605

uint32_t reserved_62; // offset: 62 (0x3E)

sys/dev/pci/drm/amd/include/v12_structs.h

606

uint32_t reserved_63; // offset: 63 (0x3F)

sys/dev/pci/drm/amd/include/v12_structs.h

607

uint32_t reserved_64; // offset: 64 (0x40)

sys/dev/pci/drm/amd/include/v12_structs.h

608

uint32_t reserved_65; // offset: 65 (0x41)

sys/dev/pci/drm/amd/include/v12_structs.h

609

uint32_t reserved_66; // offset: 66 (0x42)

sys/dev/pci/drm/amd/include/v12_structs.h

61

uint32_t reserved_33; // offset: 33 (0x21)

sys/dev/pci/drm/amd/include/v12_structs.h

610

uint32_t reserved_67; // offset: 67 (0x43)

sys/dev/pci/drm/amd/include/v12_structs.h

611

uint32_t reserved_68; // offset: 68 (0x44)

sys/dev/pci/drm/amd/include/v12_structs.h

612

uint32_t reserved_69; // offset: 69 (0x45)

sys/dev/pci/drm/amd/include/v12_structs.h

613

uint32_t reserved_70; // offset: 70 (0x46)

sys/dev/pci/drm/amd/include/v12_structs.h

614

uint32_t reserved_71; // offset: 0 (0x47)

sys/dev/pci/drm/amd/include/v12_structs.h

615

uint32_t reserved_72; // offset: 1 (0x48)

sys/dev/pci/drm/amd/include/v12_structs.h

616

uint32_t reserved_73; // offset: 2 (0x49)

sys/dev/pci/drm/amd/include/v12_structs.h

617

uint32_t reserved_74; // offset: 3 (0x4A)

sys/dev/pci/drm/amd/include/v12_structs.h

618

uint32_t reserved_75; // offset: 4 (0x4B)

sys/dev/pci/drm/amd/include/v12_structs.h

619

uint32_t reserved_76; // offset: 5 (0x4C)

sys/dev/pci/drm/amd/include/v12_structs.h

62

uint32_t reserved_34; // offset: 34 (0x22)

sys/dev/pci/drm/amd/include/v12_structs.h

620

uint32_t reserved_77; // offset: 6 (0x4D)

sys/dev/pci/drm/amd/include/v12_structs.h

621

uint32_t reserved_78; // offset: 7 (0x4E)

sys/dev/pci/drm/amd/include/v12_structs.h

622

uint32_t reserved_79; // offset: 79 (0x4F)

sys/dev/pci/drm/amd/include/v12_structs.h

623

uint32_t reserved_80; // offset: 80 (0x50)

sys/dev/pci/drm/amd/include/v12_structs.h

624

uint32_t reserved_81; // offset: 81 (0x51)

sys/dev/pci/drm/amd/include/v12_structs.h

625

uint32_t reserved_82; // offset: 82 (0x52)

sys/dev/pci/drm/amd/include/v12_structs.h

626

uint32_t reserved_83; // offset: 83 (0x53)

sys/dev/pci/drm/amd/include/v12_structs.h

627

uint32_t reserved_84; // offset: 84 (0x54)

sys/dev/pci/drm/amd/include/v12_structs.h

628

uint32_t reserved_85; // offset: 85 (0x55)

sys/dev/pci/drm/amd/include/v12_structs.h

629

uint32_t reserved_86; // offset: 86 (0x56)

sys/dev/pci/drm/amd/include/v12_structs.h

63

uint32_t reserved_35; // offset: 35 (0x23)

sys/dev/pci/drm/amd/include/v12_structs.h

630

uint32_t reserved_87; // offset: 87 (0x57)

sys/dev/pci/drm/amd/include/v12_structs.h

631

uint32_t reserved_88; // offset: 88 (0x58)

sys/dev/pci/drm/amd/include/v12_structs.h

632

uint32_t reserved_89; // offset: 89 (0x59)

sys/dev/pci/drm/amd/include/v12_structs.h

633

uint32_t reserved_90; // offset: 90 (0x5A)

sys/dev/pci/drm/amd/include/v12_structs.h

634

uint32_t reserved_91; // offset: 91 (0x5B)

sys/dev/pci/drm/amd/include/v12_structs.h

635

uint32_t reserved_92; // offset: 92 (0x5C)

sys/dev/pci/drm/amd/include/v12_structs.h

636

uint32_t reserved_93; // offset: 93 (0x5D)

sys/dev/pci/drm/amd/include/v12_structs.h

637

uint32_t reserved_94; // offset: 94 (0x5E)

sys/dev/pci/drm/amd/include/v12_structs.h

638

uint32_t reserved_95; // offset: 95 (0x5F)

sys/dev/pci/drm/amd/include/v12_structs.h

639

uint32_t reserved_96; // offset: 96 (0x60)

sys/dev/pci/drm/amd/include/v12_structs.h

64

uint32_t reserved_36; // offset: 36 (0x24)

sys/dev/pci/drm/amd/include/v12_structs.h

640

uint32_t reserved_97; // offset: 97 (0x61)

sys/dev/pci/drm/amd/include/v12_structs.h

641

uint32_t reserved_98; // offset: 98 (0x62)

sys/dev/pci/drm/amd/include/v12_structs.h

642

uint32_t reserved_99; // offset: 99 (0x63)

sys/dev/pci/drm/amd/include/v12_structs.h

643

uint32_t reserved_100; // offset: 100 (0x64)

sys/dev/pci/drm/amd/include/v12_structs.h

644

uint32_t reserved_101; // offset: 101 (0x65)

sys/dev/pci/drm/amd/include/v12_structs.h

645

uint32_t reserved_102; // offset: 102 (0x66)

sys/dev/pci/drm/amd/include/v12_structs.h

646

uint32_t reserved_103; // offset: 103 (0x67)

sys/dev/pci/drm/amd/include/v12_structs.h

647

uint32_t reserved_104; // offset: 104 (0x68)

sys/dev/pci/drm/amd/include/v12_structs.h

648

uint32_t reserved_105; // offset: 105 (0x69)

sys/dev/pci/drm/amd/include/v12_structs.h

649

uint32_t reserved_106; // offset: 106 (0x6A)

sys/dev/pci/drm/amd/include/v12_structs.h

65

uint32_t reserved_37; // offset: 37 (0x25)

sys/dev/pci/drm/amd/include/v12_structs.h

650

uint32_t reserved_107; // offset: 107 (0x6B)

sys/dev/pci/drm/amd/include/v12_structs.h

651

uint32_t reserved_108; // offset: 108 (0x6C)

sys/dev/pci/drm/amd/include/v12_structs.h

652

uint32_t reserved_109; // offset: 109 (0x6D)

sys/dev/pci/drm/amd/include/v12_structs.h

653

uint32_t reserved_110; // offset: 110 (0x6E)

sys/dev/pci/drm/amd/include/v12_structs.h

654

uint32_t reserved_111; // offset: 111 (0x6F)

sys/dev/pci/drm/amd/include/v12_structs.h

655

uint32_t reserved_112; // offset: 112 (0x70)

sys/dev/pci/drm/amd/include/v12_structs.h

656

uint32_t reserved_113; // offset: 113 (0x71)

sys/dev/pci/drm/amd/include/v12_structs.h

657

uint32_t reserved_114; // offset: 114 (0x72)

sys/dev/pci/drm/amd/include/v12_structs.h

658

uint32_t reserved_115; // offset: 115 (0x73)

sys/dev/pci/drm/amd/include/v12_structs.h

659

uint32_t reserved_116; // offset: 116 (0x74)

sys/dev/pci/drm/amd/include/v12_structs.h

66

uint32_t reserved_38; // offset: 38 (0x26)

sys/dev/pci/drm/amd/include/v12_structs.h

660

uint32_t reserved_117; // offset: 117 (0x75)

sys/dev/pci/drm/amd/include/v12_structs.h

661

uint32_t reserved_118; // offset: 118 (0x76)

sys/dev/pci/drm/amd/include/v12_structs.h

662

uint32_t reserved_119; // offset: 119 (0x77)

sys/dev/pci/drm/amd/include/v12_structs.h

663

uint32_t reserved_120; // offset: 120 (0x78)

sys/dev/pci/drm/amd/include/v12_structs.h

664

uint32_t reserved_121; // offset: 121 (0x79)

sys/dev/pci/drm/amd/include/v12_structs.h

665

uint32_t reserved_122; // offset: 122 (0x7A)

sys/dev/pci/drm/amd/include/v12_structs.h

666

uint32_t reserved_123; // offset: 123 (0x7B)

sys/dev/pci/drm/amd/include/v12_structs.h

667

uint32_t reserved_124; // offset: 124 (0x7C)

sys/dev/pci/drm/amd/include/v12_structs.h

668

uint32_t reserved_125; // offset: 125 (0x7D)

sys/dev/pci/drm/amd/include/v12_structs.h

67

uint32_t reserved_39; // offset: 39 (0x27)

sys/dev/pci/drm/amd/include/v12_structs.h

670

uint32_t sdma_engine_id;

sys/dev/pci/drm/amd/include/v12_structs.h

671

uint32_t sdma_queue_id;

sys/dev/pci/drm/amd/include/v12_structs.h

675

uint32_t header; // offset: 0 (0x0)

sys/dev/pci/drm/amd/include/v12_structs.h

676

uint32_t compute_dispatch_initiator; // offset: 1 (0x1)

sys/dev/pci/drm/amd/include/v12_structs.h

677

uint32_t compute_dim_x; // offset: 2 (0x2)

sys/dev/pci/drm/amd/include/v12_structs.h

678

uint32_t compute_dim_y; // offset: 3 (0x3)

sys/dev/pci/drm/amd/include/v12_structs.h

679

uint32_t compute_dim_z; // offset: 4 (0x4)

sys/dev/pci/drm/amd/include/v12_structs.h

68

uint32_t reserved_40; // offset: 40 (0x28)

sys/dev/pci/drm/amd/include/v12_structs.h

680

uint32_t compute_start_x; // offset: 5 (0x5)

sys/dev/pci/drm/amd/include/v12_structs.h

681

uint32_t compute_start_y; // offset: 6 (0x6)

sys/dev/pci/drm/amd/include/v12_structs.h

682

uint32_t compute_start_z; // offset: 7 (0x7)

sys/dev/pci/drm/amd/include/v12_structs.h

683

uint32_t compute_num_thread_x; // offset: 8 (0x8)

sys/dev/pci/drm/amd/include/v12_structs.h

684

uint32_t compute_num_thread_y; // offset: 9 (0x9)

sys/dev/pci/drm/amd/include/v12_structs.h

685

uint32_t compute_num_thread_z; // offset: 10 (0xA)

sys/dev/pci/drm/amd/include/v12_structs.h

686

uint32_t compute_pipelinestat_enable; // offset: 11 (0xB)

sys/dev/pci/drm/amd/include/v12_structs.h

687

uint32_t compute_perfcount_enable; // offset: 12 (0xC)

sys/dev/pci/drm/amd/include/v12_structs.h

688

uint32_t compute_pgm_lo; // offset: 13 (0xD)

sys/dev/pci/drm/amd/include/v12_structs.h

689

uint32_t compute_pgm_hi; // offset: 14 (0xE)

sys/dev/pci/drm/amd/include/v12_structs.h

69

uint32_t reserved_41; // offset: 41 (0x29)

sys/dev/pci/drm/amd/include/v12_structs.h

690

uint32_t compute_dispatch_pkt_addr_lo; // offset: 15 (0xF)

sys/dev/pci/drm/amd/include/v12_structs.h

691

uint32_t compute_dispatch_pkt_addr_hi; // offset: 16 (0x10)

sys/dev/pci/drm/amd/include/v12_structs.h

692

uint32_t compute_dispatch_scratch_base_lo; // offset: 17 (0x11)

sys/dev/pci/drm/amd/include/v12_structs.h

693

uint32_t compute_dispatch_scratch_base_hi; // offset: 18 (0x12)

sys/dev/pci/drm/amd/include/v12_structs.h

694

uint32_t compute_pgm_rsrc1; // offset: 19 (0x13)

sys/dev/pci/drm/amd/include/v12_structs.h

695

uint32_t compute_pgm_rsrc2; // offset: 20 (0x14)

sys/dev/pci/drm/amd/include/v12_structs.h

696

uint32_t compute_vmid; // offset: 21 (0x15)

sys/dev/pci/drm/amd/include/v12_structs.h

697

uint32_t compute_resource_limits; // offset: 22 (0x16)

sys/dev/pci/drm/amd/include/v12_structs.h

698

uint32_t compute_static_thread_mgmt_se0; // offset: 23 (0x17)

sys/dev/pci/drm/amd/include/v12_structs.h

699

uint32_t compute_static_thread_mgmt_se1; // offset: 24 (0x18)

sys/dev/pci/drm/amd/include/v12_structs.h

70

uint32_t reserved_42; // offset: 42 (0x2A)

sys/dev/pci/drm/amd/include/v12_structs.h

700

uint32_t compute_tmpring_size; // offset: 25 (0x19)

sys/dev/pci/drm/amd/include/v12_structs.h

701

uint32_t compute_static_thread_mgmt_se2; // offset: 26 (0x1A)

sys/dev/pci/drm/amd/include/v12_structs.h

702

uint32_t compute_static_thread_mgmt_se3; // offset: 27 (0x1B)

sys/dev/pci/drm/amd/include/v12_structs.h

703

uint32_t compute_restart_x; // offset: 28 (0x1C)

sys/dev/pci/drm/amd/include/v12_structs.h

704

uint32_t compute_restart_y; // offset: 29 (0x1D)

sys/dev/pci/drm/amd/include/v12_structs.h

705

uint32_t compute_restart_z; // offset: 30 (0x1E)

sys/dev/pci/drm/amd/include/v12_structs.h

706

uint32_t compute_thread_trace_enable; // offset: 31 (0x1F)

sys/dev/pci/drm/amd/include/v12_structs.h

707

uint32_t compute_misc_reserved; // offset: 32 (0x20)

sys/dev/pci/drm/amd/include/v12_structs.h

708

uint32_t compute_dispatch_id; // offset: 33 (0x21)

sys/dev/pci/drm/amd/include/v12_structs.h

709

uint32_t compute_threadgroup_id; // offset: 34 (0x22)

sys/dev/pci/drm/amd/include/v12_structs.h

71

uint32_t reserved_43; // offset: 43 (0x2B)

sys/dev/pci/drm/amd/include/v12_structs.h

710

uint32_t compute_req_ctrl; // offset: 35 (0x23)

sys/dev/pci/drm/amd/include/v12_structs.h

711

uint32_t reserved_36; // offset: 36 (0x24)

sys/dev/pci/drm/amd/include/v12_structs.h

712

uint32_t compute_user_accum_0; // offset: 37 (0x25)

sys/dev/pci/drm/amd/include/v12_structs.h

713

uint32_t compute_user_accum_1; // offset: 38 (0x26)

sys/dev/pci/drm/amd/include/v12_structs.h

714

uint32_t compute_user_accum_2; // offset: 39 (0x27)

sys/dev/pci/drm/amd/include/v12_structs.h

715

uint32_t compute_user_accum_3; // offset: 40 (0x28)

sys/dev/pci/drm/amd/include/v12_structs.h

716

uint32_t compute_pgm_rsrc3; // offset: 41 (0x29)

sys/dev/pci/drm/amd/include/v12_structs.h

717

uint32_t compute_ddid_index; // offset: 42 (0x2A)

sys/dev/pci/drm/amd/include/v12_structs.h

718

uint32_t compute_shader_chksum; // offset: 43 (0x2B)

sys/dev/pci/drm/amd/include/v12_structs.h

719

uint32_t compute_static_thread_mgmt_se4; // offset: 44 (0x2C)

sys/dev/pci/drm/amd/include/v12_structs.h

72

uint32_t reserved_44; // offset: 44 (0x2C)

sys/dev/pci/drm/amd/include/v12_structs.h

720

uint32_t compute_static_thread_mgmt_se5; // offset: 45 (0x2D)

sys/dev/pci/drm/amd/include/v12_structs.h

721

uint32_t compute_static_thread_mgmt_se6; // offset: 46 (0x2E)

sys/dev/pci/drm/amd/include/v12_structs.h

722

uint32_t compute_static_thread_mgmt_se7; // offset: 47 (0x2F)

sys/dev/pci/drm/amd/include/v12_structs.h

723

uint32_t compute_dispatch_interleave; // offset: 48 (0x30)

sys/dev/pci/drm/amd/include/v12_structs.h

724

uint32_t compute_relaunch; // offset: 49 (0x31)

sys/dev/pci/drm/amd/include/v12_structs.h

725

uint32_t compute_wave_restore_addr_lo; // offset: 50 (0x32)

sys/dev/pci/drm/amd/include/v12_structs.h

726

uint32_t compute_wave_restore_addr_hi; // offset: 51 (0x33)

sys/dev/pci/drm/amd/include/v12_structs.h

727

uint32_t compute_wave_restore_control; // offset: 52 (0x34)

sys/dev/pci/drm/amd/include/v12_structs.h

728

uint32_t reserved_53; // offset: 53 (0x35)

sys/dev/pci/drm/amd/include/v12_structs.h

729

uint32_t reserved_54; // offset: 54 (0x36)

sys/dev/pci/drm/amd/include/v12_structs.h

73

uint32_t reserved_45; // offset: 45 (0x2D)

sys/dev/pci/drm/amd/include/v12_structs.h

730

uint32_t reserved_55; // offset: 55 (0x37)

sys/dev/pci/drm/amd/include/v12_structs.h

731

uint32_t reserved_56; // offset: 56 (0x38)

sys/dev/pci/drm/amd/include/v12_structs.h

732

uint32_t reserved_57; // offset: 57 (0x39)

sys/dev/pci/drm/amd/include/v12_structs.h

733

uint32_t reserved_58; // offset: 58 (0x3A)

sys/dev/pci/drm/amd/include/v12_structs.h

734

uint32_t compute_static_thread_mgmt_se8; // offset: 59 (0x3B)

sys/dev/pci/drm/amd/include/v12_structs.h

735

uint32_t reserved_60; // offset: 60 (0x3C)

sys/dev/pci/drm/amd/include/v12_structs.h

736

uint32_t reserved_61; // offset: 61 (0x3D)

sys/dev/pci/drm/amd/include/v12_structs.h

737

uint32_t reserved_62; // offset: 62 (0x3E)

sys/dev/pci/drm/amd/include/v12_structs.h

738

uint32_t reserved_63; // offset: 63 (0x3F)

sys/dev/pci/drm/amd/include/v12_structs.h

739

uint32_t reserved_64; // offset: 64 (0x40)

sys/dev/pci/drm/amd/include/v12_structs.h

74

uint32_t reserved_46; // offset: 46 (0x2E)

sys/dev/pci/drm/amd/include/v12_structs.h

740

uint32_t compute_user_data_0; // offset: 65 (0x41)

sys/dev/pci/drm/amd/include/v12_structs.h

741

uint32_t compute_user_data_1; // offset: 66 (0x42)

sys/dev/pci/drm/amd/include/v12_structs.h

742

uint32_t compute_user_data_2; // offset: 67 (0x43)

sys/dev/pci/drm/amd/include/v12_structs.h

743

uint32_t compute_user_data_3; // offset: 68 (0x44)

sys/dev/pci/drm/amd/include/v12_structs.h

744

uint32_t compute_user_data_4; // offset: 69 (0x45)

sys/dev/pci/drm/amd/include/v12_structs.h

745

uint32_t compute_user_data_5; // offset: 70 (0x46)

sys/dev/pci/drm/amd/include/v12_structs.h

746

uint32_t compute_user_data_6; // offset: 71 (0x47)

sys/dev/pci/drm/amd/include/v12_structs.h

747

uint32_t compute_user_data_7; // offset: 72 (0x48)

sys/dev/pci/drm/amd/include/v12_structs.h

748

uint32_t compute_user_data_8; // offset: 73 (0x49)

sys/dev/pci/drm/amd/include/v12_structs.h

749

uint32_t compute_user_data_9; // offset: 74 (0x4A)

sys/dev/pci/drm/amd/include/v12_structs.h

75

uint32_t reserved_47; // offset: 47 (0x2F)

sys/dev/pci/drm/amd/include/v12_structs.h

750

uint32_t compute_user_data_10; // offset: 75 (0x4B)

sys/dev/pci/drm/amd/include/v12_structs.h

751

uint32_t compute_user_data_11; // offset: 76 (0x4C)

sys/dev/pci/drm/amd/include/v12_structs.h

752

uint32_t compute_user_data_12; // offset: 77 (0x4D)

sys/dev/pci/drm/amd/include/v12_structs.h

753

uint32_t compute_user_data_13; // offset: 78 (0x4E)

sys/dev/pci/drm/amd/include/v12_structs.h

754

uint32_t compute_user_data_14; // offset: 79 (0x4F)

sys/dev/pci/drm/amd/include/v12_structs.h

755

uint32_t compute_user_data_15; // offset: 80 (0x50)

sys/dev/pci/drm/amd/include/v12_structs.h

756

uint32_t cp_compute_csinvoc_count_lo; // offset: 81 (0x51)

sys/dev/pci/drm/amd/include/v12_structs.h

757

uint32_t cp_compute_csinvoc_count_hi; // offset: 82 (0x52)

sys/dev/pci/drm/amd/include/v12_structs.h

758

uint32_t reserved_83; // offset: 83 (0x53)

sys/dev/pci/drm/amd/include/v12_structs.h

759

uint32_t reserved_84; // offset: 84 (0x54)

sys/dev/pci/drm/amd/include/v12_structs.h

76

uint32_t reserved_48; // offset: 48 (0x30)

sys/dev/pci/drm/amd/include/v12_structs.h

760

uint32_t reserved_85; // offset: 85 (0x55)

sys/dev/pci/drm/amd/include/v12_structs.h

761

uint32_t cp_mqd_query_time_lo; // offset: 86 (0x56)

sys/dev/pci/drm/amd/include/v12_structs.h

762

uint32_t cp_mqd_query_time_hi; // offset: 87 (0x57)

sys/dev/pci/drm/amd/include/v12_structs.h

763

uint32_t cp_mqd_connect_start_time_lo; // offset: 88 (0x58)

sys/dev/pci/drm/amd/include/v12_structs.h

764

uint32_t cp_mqd_connect_start_time_hi; // offset: 89 (0x59)

sys/dev/pci/drm/amd/include/v12_structs.h

765

uint32_t cp_mqd_connect_end_time_lo; // offset: 90 (0x5A)

sys/dev/pci/drm/amd/include/v12_structs.h

766

uint32_t cp_mqd_connect_end_time_hi; // offset: 91 (0x5B)

sys/dev/pci/drm/amd/include/v12_structs.h

767

uint32_t cp_mqd_connect_end_wf_count; // offset: 92 (0x5C)

sys/dev/pci/drm/amd/include/v12_structs.h

768

uint32_t cp_mqd_connect_end_pq_rptr; // offset: 93 (0x5D)

sys/dev/pci/drm/amd/include/v12_structs.h

769

uint32_t cp_mqd_connect_end_pq_wptr; // offset: 94 (0x5E)

sys/dev/pci/drm/amd/include/v12_structs.h

77

uint32_t reserved_49; // offset: 49 (0x31)

sys/dev/pci/drm/amd/include/v12_structs.h

770

uint32_t cp_mqd_connect_end_ib_rptr; // offset: 95 (0x5F)

sys/dev/pci/drm/amd/include/v12_structs.h

771

uint32_t cp_mqd_readindex_lo; // offset: 96 (0x60)

sys/dev/pci/drm/amd/include/v12_structs.h

772

uint32_t cp_mqd_readindex_hi; // offset: 97 (0x61)

sys/dev/pci/drm/amd/include/v12_structs.h

773

uint32_t cp_mqd_save_start_time_lo; // offset: 98 (0x62)

sys/dev/pci/drm/amd/include/v12_structs.h

774

uint32_t cp_mqd_save_start_time_hi; // offset: 99 (0x63)

sys/dev/pci/drm/amd/include/v12_structs.h

775

uint32_t cp_mqd_save_end_time_lo; // offset: 100 (0x64)

sys/dev/pci/drm/amd/include/v12_structs.h

776

uint32_t cp_mqd_save_end_time_hi; // offset: 101 (0x65)

sys/dev/pci/drm/amd/include/v12_structs.h

777

uint32_t cp_mqd_restore_start_time_lo; // offset: 102 (0x66)

sys/dev/pci/drm/amd/include/v12_structs.h

778

uint32_t cp_mqd_restore_start_time_hi; // offset: 103 (0x67)

sys/dev/pci/drm/amd/include/v12_structs.h

779

uint32_t cp_mqd_restore_end_time_lo; // offset: 104 (0x68)

sys/dev/pci/drm/amd/include/v12_structs.h

78

uint32_t reserved_50; // offset: 50 (0x32)

sys/dev/pci/drm/amd/include/v12_structs.h

780

uint32_t cp_mqd_restore_end_time_hi; // offset: 105 (0x69)

sys/dev/pci/drm/amd/include/v12_structs.h

781

uint32_t disable_queue; // offset: 106 (0x6A)

sys/dev/pci/drm/amd/include/v12_structs.h

782

uint32_t reserved_107; // offset: 107 (0x6B)

sys/dev/pci/drm/amd/include/v12_structs.h

783

uint32_t reserved_108; // offset: 108 (0x6C)

sys/dev/pci/drm/amd/include/v12_structs.h

784

uint32_t reserved_109; // offset: 109 (0x6D)

sys/dev/pci/drm/amd/include/v12_structs.h

785

uint32_t reserved_110; // offset: 110 (0x6E)

sys/dev/pci/drm/amd/include/v12_structs.h

786

uint32_t reserved_111; // offset: 111 (0x6F)

sys/dev/pci/drm/amd/include/v12_structs.h

787

uint32_t reserved_112; // offset: 112 (0x70)

sys/dev/pci/drm/amd/include/v12_structs.h

788

uint32_t reserved_113; // offset: 113 (0x71)

sys/dev/pci/drm/amd/include/v12_structs.h

789

uint32_t cp_pq_exe_status_lo; // offset: 114 (0x72)

sys/dev/pci/drm/amd/include/v12_structs.h

79

uint32_t reserved_51; // offset: 51 (0x33)

sys/dev/pci/drm/amd/include/v12_structs.h

790

uint32_t cp_pq_exe_status_hi; // offset: 115 (0x73)

sys/dev/pci/drm/amd/include/v12_structs.h

791

uint32_t cp_packet_id_lo; // offset: 116 (0x74)

sys/dev/pci/drm/amd/include/v12_structs.h

792

uint32_t cp_packet_id_hi; // offset: 117 (0x75)

sys/dev/pci/drm/amd/include/v12_structs.h

793

uint32_t cp_packet_exe_status_lo; // offset: 118 (0x76)

sys/dev/pci/drm/amd/include/v12_structs.h

794

uint32_t cp_packet_exe_status_hi; // offset: 119 (0x77)

sys/dev/pci/drm/amd/include/v12_structs.h

795

uint32_t reserved_120; // offset: 120 (0x78)

sys/dev/pci/drm/amd/include/v12_structs.h

796

uint32_t reserved_121; // offset: 121 (0x79)

sys/dev/pci/drm/amd/include/v12_structs.h

797

uint32_t reserved_122; // offset: 122 (0x7A)

sys/dev/pci/drm/amd/include/v12_structs.h

798

uint32_t reserved_123; // offset: 123 (0x7B)

sys/dev/pci/drm/amd/include/v12_structs.h

799

uint32_t ctx_save_base_addr_lo; // offset: 124 (0x7C)

sys/dev/pci/drm/amd/include/v12_structs.h

80

uint32_t reserved_52; // offset: 52 (0x34)

sys/dev/pci/drm/amd/include/v12_structs.h

800

uint32_t ctx_save_base_addr_hi; // offset: 125 (0x7D)

sys/dev/pci/drm/amd/include/v12_structs.h

801

uint32_t reserved_126; // offset: 126 (0x7E)

sys/dev/pci/drm/amd/include/v12_structs.h

802

uint32_t reserved_127; // offset: 127 (0x7F)

sys/dev/pci/drm/amd/include/v12_structs.h

803

uint32_t cp_mqd_base_addr_lo; // offset: 128 (0x80)

sys/dev/pci/drm/amd/include/v12_structs.h

804

uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81)

sys/dev/pci/drm/amd/include/v12_structs.h

805

uint32_t cp_hqd_active; // offset: 130 (0x82)

sys/dev/pci/drm/amd/include/v12_structs.h

806

uint32_t cp_hqd_vmid; // offset: 131 (0x83)

sys/dev/pci/drm/amd/include/v12_structs.h

807

uint32_t cp_hqd_persistent_state; // offset: 132 (0x84)

sys/dev/pci/drm/amd/include/v12_structs.h

808

uint32_t cp_hqd_pipe_priority; // offset: 133 (0x85)

sys/dev/pci/drm/amd/include/v12_structs.h

809

uint32_t cp_hqd_queue_priority; // offset: 134 (0x86)

sys/dev/pci/drm/amd/include/v12_structs.h

81

uint32_t reserved_53; // offset: 53 (0x35)

sys/dev/pci/drm/amd/include/v12_structs.h

810

uint32_t cp_hqd_quantum; // offset: 135 (0x87)

sys/dev/pci/drm/amd/include/v12_structs.h

811

uint32_t cp_hqd_pq_base_lo; // offset: 136 (0x88)

sys/dev/pci/drm/amd/include/v12_structs.h

812

uint32_t cp_hqd_pq_base_hi; // offset: 137 (0x89)

sys/dev/pci/drm/amd/include/v12_structs.h

813

uint32_t cp_hqd_pq_rptr; // offset: 138 (0x8A)

sys/dev/pci/drm/amd/include/v12_structs.h

814

uint32_t cp_hqd_pq_rptr_report_addr_lo; // offset: 139 (0x8B)

sys/dev/pci/drm/amd/include/v12_structs.h

815

uint32_t cp_hqd_pq_rptr_report_addr_hi; // offset: 140 (0x8C)

sys/dev/pci/drm/amd/include/v12_structs.h

816

uint32_t cp_hqd_pq_wptr_poll_addr_lo; // offset: 141 (0x8D)

sys/dev/pci/drm/amd/include/v12_structs.h

817

uint32_t cp_hqd_pq_wptr_poll_addr_hi; // offset: 142 (0x8E)

sys/dev/pci/drm/amd/include/v12_structs.h

818

uint32_t cp_hqd_pq_doorbell_control; // offset: 143 (0x8F)

sys/dev/pci/drm/amd/include/v12_structs.h

819

uint32_t reserved_144; // offset: 144 (0x90)

sys/dev/pci/drm/amd/include/v12_structs.h

82

uint32_t reserved_54; // offset: 54 (0x36)

sys/dev/pci/drm/amd/include/v12_structs.h

820

uint32_t cp_hqd_pq_control; // offset: 145 (0x91)

sys/dev/pci/drm/amd/include/v12_structs.h

821

uint32_t cp_hqd_ib_base_addr_lo; // offset: 146 (0x92)

sys/dev/pci/drm/amd/include/v12_structs.h

822

uint32_t cp_hqd_ib_base_addr_hi; // offset: 147 (0x93)

sys/dev/pci/drm/amd/include/v12_structs.h

823

uint32_t cp_hqd_ib_rptr; // offset: 148 (0x94)

sys/dev/pci/drm/amd/include/v12_structs.h

824

uint32_t cp_hqd_ib_control; // offset: 149 (0x95)

sys/dev/pci/drm/amd/include/v12_structs.h

825

uint32_t cp_hqd_iq_timer; // offset: 150 (0x96)

sys/dev/pci/drm/amd/include/v12_structs.h

826

uint32_t cp_hqd_iq_rptr; // offset: 151 (0x97)

sys/dev/pci/drm/amd/include/v12_structs.h

827

uint32_t cp_hqd_dequeue_request; // offset: 152 (0x98)

sys/dev/pci/drm/amd/include/v12_structs.h

828

uint32_t cp_hqd_dma_offload; // offset: 153 (0x99)

sys/dev/pci/drm/amd/include/v12_structs.h

829

uint32_t cp_hqd_sema_cmd; // offset: 154 (0x9A)

sys/dev/pci/drm/amd/include/v12_structs.h

83

uint32_t reserved_55; // offset: 55 (0x37)

sys/dev/pci/drm/amd/include/v12_structs.h

830

uint32_t cp_hqd_msg_type; // offset: 155 (0x9B)

sys/dev/pci/drm/amd/include/v12_structs.h

831

uint32_t cp_hqd_atomic0_preop_lo; // offset: 156 (0x9C)

sys/dev/pci/drm/amd/include/v12_structs.h

832

uint32_t cp_hqd_atomic0_preop_hi; // offset: 157 (0x9D)

sys/dev/pci/drm/amd/include/v12_structs.h

833

uint32_t cp_hqd_atomic1_preop_lo; // offset: 158 (0x9E)

sys/dev/pci/drm/amd/include/v12_structs.h

834

uint32_t cp_hqd_atomic1_preop_hi; // offset: 159 (0x9F)

sys/dev/pci/drm/amd/include/v12_structs.h

835

uint32_t cp_hqd_hq_status0; // offset: 160 (0xA0)

sys/dev/pci/drm/amd/include/v12_structs.h

836

uint32_t cp_hqd_hq_control0; // offset: 161 (0xA1)

sys/dev/pci/drm/amd/include/v12_structs.h

837

uint32_t cp_mqd_control; // offset: 162 (0xA2)

sys/dev/pci/drm/amd/include/v12_structs.h

838

uint32_t cp_hqd_hq_status1; // offset: 163 (0xA3)

sys/dev/pci/drm/amd/include/v12_structs.h

839

uint32_t cp_hqd_hq_control1; // offset: 164 (0xA4)

sys/dev/pci/drm/amd/include/v12_structs.h

84

uint32_t reserved_56; // offset: 56 (0x38)

sys/dev/pci/drm/amd/include/v12_structs.h

840

uint32_t cp_hqd_eop_base_addr_lo; // offset: 165 (0xA5)

sys/dev/pci/drm/amd/include/v12_structs.h

841

uint32_t cp_hqd_eop_base_addr_hi; // offset: 166 (0xA6)

sys/dev/pci/drm/amd/include/v12_structs.h

842

uint32_t cp_hqd_eop_control; // offset: 167 (0xA7)

sys/dev/pci/drm/amd/include/v12_structs.h

843

uint32_t cp_hqd_eop_rptr; // offset: 168 (0xA8)

sys/dev/pci/drm/amd/include/v12_structs.h

844

uint32_t cp_hqd_eop_wptr; // offset: 169 (0xA9)

sys/dev/pci/drm/amd/include/v12_structs.h

845

uint32_t cp_hqd_eop_done_events; // offset: 170 (0xAA)

sys/dev/pci/drm/amd/include/v12_structs.h

846

uint32_t cp_hqd_ctx_save_base_addr_lo; // offset: 171 (0xAB)

sys/dev/pci/drm/amd/include/v12_structs.h

847

uint32_t cp_hqd_ctx_save_base_addr_hi; // offset: 172 (0xAC)

sys/dev/pci/drm/amd/include/v12_structs.h

848

uint32_t cp_hqd_ctx_save_control; // offset: 173 (0xAD)

sys/dev/pci/drm/amd/include/v12_structs.h

849

uint32_t cp_hqd_cntl_stack_offset; // offset: 174 (0xAE)

sys/dev/pci/drm/amd/include/v12_structs.h

85

uint32_t reserved_57; // offset: 57 (0x39)

sys/dev/pci/drm/amd/include/v12_structs.h

850

uint32_t cp_hqd_cntl_stack_size; // offset: 175 (0xAF)

sys/dev/pci/drm/amd/include/v12_structs.h

851

uint32_t cp_hqd_wg_state_offset; // offset: 176 (0xB0)

sys/dev/pci/drm/amd/include/v12_structs.h

852

uint32_t cp_hqd_ctx_save_size; // offset: 177 (0xB1)

sys/dev/pci/drm/amd/include/v12_structs.h

853

uint32_t reserved_178; // offset: 178 (0xB2)

sys/dev/pci/drm/amd/include/v12_structs.h

854

uint32_t cp_hqd_error; // offset: 179 (0xB3)

sys/dev/pci/drm/amd/include/v12_structs.h

855

uint32_t cp_hqd_eop_wptr_mem; // offset: 180 (0xB4)

sys/dev/pci/drm/amd/include/v12_structs.h

856

uint32_t cp_hqd_aql_control; // offset: 181 (0xB5)

sys/dev/pci/drm/amd/include/v12_structs.h

857

uint32_t cp_hqd_pq_wptr_lo; // offset: 182 (0xB6)

sys/dev/pci/drm/amd/include/v12_structs.h

858

uint32_t cp_hqd_pq_wptr_hi; // offset: 183 (0xB7)

sys/dev/pci/drm/amd/include/v12_structs.h

859

uint32_t reserved_184; // offset: 184 (0xB8)

sys/dev/pci/drm/amd/include/v12_structs.h

86

uint32_t reserved_58; // offset: 58 (0x3A)

sys/dev/pci/drm/amd/include/v12_structs.h

860

uint32_t reserved_185; // offset: 185 (0xB9)

sys/dev/pci/drm/amd/include/v12_structs.h

861

uint32_t reserved_186; // offset: 186 (0xBA)

sys/dev/pci/drm/amd/include/v12_structs.h

862

uint32_t reserved_187; // offset: 187 (0xBB)

sys/dev/pci/drm/amd/include/v12_structs.h

863

uint32_t reserved_188; // offset: 188 (0xBC)

sys/dev/pci/drm/amd/include/v12_structs.h

864

uint32_t reserved_189; // offset: 189 (0xBD)

sys/dev/pci/drm/amd/include/v12_structs.h

865

uint32_t reserved_190; // offset: 190 (0xBE)

sys/dev/pci/drm/amd/include/v12_structs.h

866

uint32_t reserved_191; // offset: 191 (0xBF)

sys/dev/pci/drm/amd/include/v12_structs.h

867

uint32_t iqtimer_pkt_header; // offset: 192 (0xC0)

sys/dev/pci/drm/amd/include/v12_structs.h

868

uint32_t iqtimer_pkt_dw0; // offset: 193 (0xC1)

sys/dev/pci/drm/amd/include/v12_structs.h

869

uint32_t iqtimer_pkt_dw1; // offset: 194 (0xC2)

sys/dev/pci/drm/amd/include/v12_structs.h

87

uint32_t reserved_59; // offset: 59 (0x3B)

sys/dev/pci/drm/amd/include/v12_structs.h

870

uint32_t iqtimer_pkt_dw2; // offset: 195 (0xC3)

sys/dev/pci/drm/amd/include/v12_structs.h

871

uint32_t iqtimer_pkt_dw3; // offset: 196 (0xC4)

sys/dev/pci/drm/amd/include/v12_structs.h

872

uint32_t iqtimer_pkt_dw4; // offset: 197 (0xC5)

sys/dev/pci/drm/amd/include/v12_structs.h

873

uint32_t iqtimer_pkt_dw5; // offset: 198 (0xC6)

sys/dev/pci/drm/amd/include/v12_structs.h

874

uint32_t iqtimer_pkt_dw6; // offset: 199 (0xC7)

sys/dev/pci/drm/amd/include/v12_structs.h

875

uint32_t iqtimer_pkt_dw7; // offset: 200 (0xC8)

sys/dev/pci/drm/amd/include/v12_structs.h

876

uint32_t iqtimer_pkt_dw8; // offset: 201 (0xC9)

sys/dev/pci/drm/amd/include/v12_structs.h

877

uint32_t iqtimer_pkt_dw9; // offset: 202 (0xCA)

sys/dev/pci/drm/amd/include/v12_structs.h

878

uint32_t iqtimer_pkt_dw10; // offset: 203 (0xCB)

sys/dev/pci/drm/amd/include/v12_structs.h

879

uint32_t iqtimer_pkt_dw11; // offset: 204 (0xCC)

sys/dev/pci/drm/amd/include/v12_structs.h

88

uint32_t reserved_60; // offset: 60 (0x3C)

sys/dev/pci/drm/amd/include/v12_structs.h

880

uint32_t iqtimer_pkt_dw12; // offset: 205 (0xCD)

sys/dev/pci/drm/amd/include/v12_structs.h

881

uint32_t iqtimer_pkt_dw13; // offset: 206 (0xCE)

sys/dev/pci/drm/amd/include/v12_structs.h

882

uint32_t iqtimer_pkt_dw14; // offset: 207 (0xCF)

sys/dev/pci/drm/amd/include/v12_structs.h

883

uint32_t iqtimer_pkt_dw15; // offset: 208 (0xD0)

sys/dev/pci/drm/amd/include/v12_structs.h

884

uint32_t iqtimer_pkt_dw16; // offset: 209 (0xD1)

sys/dev/pci/drm/amd/include/v12_structs.h

885

uint32_t iqtimer_pkt_dw17; // offset: 210 (0xD2)

sys/dev/pci/drm/amd/include/v12_structs.h

886

uint32_t iqtimer_pkt_dw18; // offset: 211 (0xD3)

sys/dev/pci/drm/amd/include/v12_structs.h

887

uint32_t iqtimer_pkt_dw19; // offset: 212 (0xD4)

sys/dev/pci/drm/amd/include/v12_structs.h

888

uint32_t iqtimer_pkt_dw20; // offset: 213 (0xD5)

sys/dev/pci/drm/amd/include/v12_structs.h

889

uint32_t iqtimer_pkt_dw21; // offset: 214 (0xD6)

sys/dev/pci/drm/amd/include/v12_structs.h

89

uint32_t reserved_61; // offset: 61 (0x3D)

sys/dev/pci/drm/amd/include/v12_structs.h

890

uint32_t iqtimer_pkt_dw22; // offset: 215 (0xD7)

sys/dev/pci/drm/amd/include/v12_structs.h

891

uint32_t iqtimer_pkt_dw23; // offset: 216 (0xD8)

sys/dev/pci/drm/amd/include/v12_structs.h

892

uint32_t iqtimer_pkt_dw24; // offset: 217 (0xD9)

sys/dev/pci/drm/amd/include/v12_structs.h

893

uint32_t iqtimer_pkt_dw25; // offset: 218 (0xDA)

sys/dev/pci/drm/amd/include/v12_structs.h

894

uint32_t iqtimer_pkt_dw26; // offset: 219 (0xDB)

sys/dev/pci/drm/amd/include/v12_structs.h

895

uint32_t iqtimer_pkt_dw27; // offset: 220 (0xDC)

sys/dev/pci/drm/amd/include/v12_structs.h

896

uint32_t iqtimer_pkt_dw28; // offset: 221 (0xDD)

sys/dev/pci/drm/amd/include/v12_structs.h

897

uint32_t iqtimer_pkt_dw29; // offset: 222 (0xDE)

sys/dev/pci/drm/amd/include/v12_structs.h

898

uint32_t iqtimer_pkt_dw30; // offset: 223 (0xDF)

sys/dev/pci/drm/amd/include/v12_structs.h

899

uint32_t iqtimer_pkt_dw31; // offset: 224 (0xE0)

sys/dev/pci/drm/amd/include/v12_structs.h

90

uint32_t reserved_62; // offset: 62 (0x3E)

sys/dev/pci/drm/amd/include/v12_structs.h

900

uint32_t reserved_225; // offset: 225 (0xE1)

sys/dev/pci/drm/amd/include/v12_structs.h

901

uint32_t reserved_226; // offset: 226 (0xE2)

sys/dev/pci/drm/amd/include/v12_structs.h

902

uint32_t reserved_227; // offset: 227 (0xE3)

sys/dev/pci/drm/amd/include/v12_structs.h

903

uint32_t set_resources_header; // offset: 228 (0xE4)

sys/dev/pci/drm/amd/include/v12_structs.h

904

uint32_t set_resources_dw1; // offset: 229 (0xE5)

sys/dev/pci/drm/amd/include/v12_structs.h

905

uint32_t set_resources_dw2; // offset: 230 (0xE6)

sys/dev/pci/drm/amd/include/v12_structs.h

906

uint32_t set_resources_dw3; // offset: 231 (0xE7)

sys/dev/pci/drm/amd/include/v12_structs.h

907

uint32_t set_resources_dw4; // offset: 232 (0xE8)

sys/dev/pci/drm/amd/include/v12_structs.h

908

uint32_t set_resources_dw5; // offset: 233 (0xE9)

sys/dev/pci/drm/amd/include/v12_structs.h

909

uint32_t set_resources_dw6; // offset: 234 (0xEA)

sys/dev/pci/drm/amd/include/v12_structs.h

91

uint32_t reserved_63; // offset: 63 (0x3F)

sys/dev/pci/drm/amd/include/v12_structs.h

910

uint32_t set_resources_dw7; // offset: 235 (0xEB)

sys/dev/pci/drm/amd/include/v12_structs.h

911

uint32_t reserved_236; // offset: 236 (0xEC)

sys/dev/pci/drm/amd/include/v12_structs.h

912

uint32_t reserved_237; // offset: 237 (0xED)

sys/dev/pci/drm/amd/include/v12_structs.h

913

uint32_t reserved_238; // offset: 238 (0xEE)

sys/dev/pci/drm/amd/include/v12_structs.h

914

uint32_t reserved_239; // offset: 239 (0xEF)

sys/dev/pci/drm/amd/include/v12_structs.h

915

uint32_t queue_doorbell_id0; // offset: 240 (0xF0)

sys/dev/pci/drm/amd/include/v12_structs.h

916

uint32_t queue_doorbell_id1; // offset: 241 (0xF1)

sys/dev/pci/drm/amd/include/v12_structs.h

917

uint32_t queue_doorbell_id2; // offset: 242 (0xF2)

sys/dev/pci/drm/amd/include/v12_structs.h

918

uint32_t queue_doorbell_id3; // offset: 243 (0xF3)

sys/dev/pci/drm/amd/include/v12_structs.h

919

uint32_t queue_doorbell_id4; // offset: 244 (0xF4)

sys/dev/pci/drm/amd/include/v12_structs.h

92

uint32_t reserved_64; // offset: 64 (0x40)

sys/dev/pci/drm/amd/include/v12_structs.h

920

uint32_t queue_doorbell_id5; // offset: 245 (0xF5)

sys/dev/pci/drm/amd/include/v12_structs.h

921

uint32_t queue_doorbell_id6; // offset: 246 (0xF6)

sys/dev/pci/drm/amd/include/v12_structs.h

922

uint32_t queue_doorbell_id7; // offset: 247 (0xF7)

sys/dev/pci/drm/amd/include/v12_structs.h

923

uint32_t queue_doorbell_id8; // offset: 248 (0xF8)

sys/dev/pci/drm/amd/include/v12_structs.h

924

uint32_t queue_doorbell_id9; // offset: 249 (0xF9)

sys/dev/pci/drm/amd/include/v12_structs.h

925

uint32_t queue_doorbell_id10; // offset: 250 (0xFA)

sys/dev/pci/drm/amd/include/v12_structs.h

926

uint32_t queue_doorbell_id11; // offset: 251 (0xFB)

sys/dev/pci/drm/amd/include/v12_structs.h

927

uint32_t queue_doorbell_id12; // offset: 252 (0xFC)

sys/dev/pci/drm/amd/include/v12_structs.h

928

uint32_t queue_doorbell_id13; // offset: 253 (0xFD)

sys/dev/pci/drm/amd/include/v12_structs.h

929

uint32_t queue_doorbell_id14; // offset: 254 (0xFE)

sys/dev/pci/drm/amd/include/v12_structs.h

93

uint32_t reserved_65; // offset: 65 (0x41)

sys/dev/pci/drm/amd/include/v12_structs.h

930

uint32_t queue_doorbell_id15; // offset: 255 (0xFF)

sys/dev/pci/drm/amd/include/v12_structs.h

931

uint32_t control_buf_addr_lo; // offset: 256 (0x100)

sys/dev/pci/drm/amd/include/v12_structs.h

932

uint32_t control_buf_addr_hi; // offset: 257 (0x101)

sys/dev/pci/drm/amd/include/v12_structs.h

933

uint32_t control_buf_wptr_lo; // offset: 258 (0x102)

sys/dev/pci/drm/amd/include/v12_structs.h

934

uint32_t control_buf_wptr_hi; // offset: 259 (0x103)

sys/dev/pci/drm/amd/include/v12_structs.h

935

uint32_t control_buf_dptr_lo; // offset: 260 (0x104)

sys/dev/pci/drm/amd/include/v12_structs.h

936

uint32_t control_buf_dptr_hi; // offset: 261 (0x105)

sys/dev/pci/drm/amd/include/v12_structs.h

937

uint32_t control_buf_num_entries; // offset: 262 (0x106)

sys/dev/pci/drm/amd/include/v12_structs.h

938

uint32_t draw_ring_addr_lo; // offset: 263 (0x107)

sys/dev/pci/drm/amd/include/v12_structs.h

939

uint32_t draw_ring_addr_hi; // offset: 264 (0x108)

sys/dev/pci/drm/amd/include/v12_structs.h

94

uint32_t reserved_66; // offset: 66 (0x42)

sys/dev/pci/drm/amd/include/v12_structs.h

940

uint32_t reserved_265; // offset: 265 (0x109)

sys/dev/pci/drm/amd/include/v12_structs.h

941

uint32_t reserved_266; // offset: 266 (0x10A)

sys/dev/pci/drm/amd/include/v12_structs.h

942

uint32_t reserved_267; // offset: 267 (0x10B)

sys/dev/pci/drm/amd/include/v12_structs.h

943

uint32_t reserved_268; // offset: 268 (0x10C)

sys/dev/pci/drm/amd/include/v12_structs.h

944

uint32_t reserved_269; // offset: 269 (0x10D)

sys/dev/pci/drm/amd/include/v12_structs.h

945

uint32_t reserved_270; // offset: 270 (0x10E)

sys/dev/pci/drm/amd/include/v12_structs.h

946

uint32_t reserved_271; // offset: 271 (0x10F)

sys/dev/pci/drm/amd/include/v12_structs.h

947

uint32_t dfwx_flags; // offset: 272 (0x110)

sys/dev/pci/drm/amd/include/v12_structs.h

948

uint32_t dfwx_slot; // offset: 273 (0x111)

sys/dev/pci/drm/amd/include/v12_structs.h

949

uint32_t dfwx_client_data_addr_lo; // offset: 274 (0x112)

sys/dev/pci/drm/amd/include/v12_structs.h

95

uint32_t reserved_67; // offset: 67 (0x43)

sys/dev/pci/drm/amd/include/v12_structs.h

950

uint32_t dfwx_client_data_addr_hi; // offset: 275 (0x113)

sys/dev/pci/drm/amd/include/v12_structs.h

951

uint32_t reserved_276; // offset: 276 (0x114)

sys/dev/pci/drm/amd/include/v12_structs.h

952

uint32_t reserved_277; // offset: 277 (0x115)

sys/dev/pci/drm/amd/include/v12_structs.h

953

uint32_t reserved_278; // offset: 278 (0x116)

sys/dev/pci/drm/amd/include/v12_structs.h

954

uint32_t reserved_279; // offset: 279 (0x117)

sys/dev/pci/drm/amd/include/v12_structs.h

955

uint32_t reserved_280; // offset: 280 (0x118)

sys/dev/pci/drm/amd/include/v12_structs.h

956

uint32_t reserved_281; // offset: 281 (0x119)

sys/dev/pci/drm/amd/include/v12_structs.h

957

uint32_t reserved_282; // offset: 282 (0x11A)

sys/dev/pci/drm/amd/include/v12_structs.h

958

uint32_t reserved_283; // offset: 283 (0x11B)

sys/dev/pci/drm/amd/include/v12_structs.h

959

uint32_t reserved_284; // offset: 284 (0x11C)

sys/dev/pci/drm/amd/include/v12_structs.h

96

uint32_t reserved_68; // offset: 68 (0x44)

sys/dev/pci/drm/amd/include/v12_structs.h

960

uint32_t reserved_285; // offset: 285 (0x11D)

sys/dev/pci/drm/amd/include/v12_structs.h

961

uint32_t reserved_286; // offset: 286 (0x11E)

sys/dev/pci/drm/amd/include/v12_structs.h

962

uint32_t reserved_287; // offset: 287 (0x11F)

sys/dev/pci/drm/amd/include/v12_structs.h

963

uint32_t reserved_288; // offset: 288 (0x120)

sys/dev/pci/drm/amd/include/v12_structs.h

964

uint32_t reserved_289; // offset: 289 (0x121)

sys/dev/pci/drm/amd/include/v12_structs.h

965

uint32_t reserved_290; // offset: 290 (0x122)

sys/dev/pci/drm/amd/include/v12_structs.h

966

uint32_t reserved_291; // offset: 291 (0x123)

sys/dev/pci/drm/amd/include/v12_structs.h

967

uint32_t reserved_292; // offset: 292 (0x124)

sys/dev/pci/drm/amd/include/v12_structs.h

968

uint32_t reserved_293; // offset: 293 (0x125)

sys/dev/pci/drm/amd/include/v12_structs.h

969

uint32_t reserved_294; // offset: 294 (0x126)

sys/dev/pci/drm/amd/include/v12_structs.h

97

uint32_t reserved_69; // offset: 69 (0x45)

sys/dev/pci/drm/amd/include/v12_structs.h

970

uint32_t reserved_295; // offset: 295 (0x127)

sys/dev/pci/drm/amd/include/v12_structs.h

971

uint32_t reserved_296; // offset: 296 (0x128)

sys/dev/pci/drm/amd/include/v12_structs.h

972

uint32_t reserved_297; // offset: 297 (0x129)

sys/dev/pci/drm/amd/include/v12_structs.h

973

uint32_t reserved_298; // offset: 298 (0x12A)

sys/dev/pci/drm/amd/include/v12_structs.h

974

uint32_t reserved_299; // offset: 299 (0x12B)

sys/dev/pci/drm/amd/include/v12_structs.h

975

uint32_t reserved_300; // offset: 300 (0x12C)

sys/dev/pci/drm/amd/include/v12_structs.h

976

uint32_t reserved_301; // offset: 301 (0x12D)

sys/dev/pci/drm/amd/include/v12_structs.h

977

uint32_t reserved_302; // offset: 302 (0x12E)

sys/dev/pci/drm/amd/include/v12_structs.h

978

uint32_t reserved_303; // offset: 303 (0x12F)

sys/dev/pci/drm/amd/include/v12_structs.h

979

uint32_t reserved_304; // offset: 304 (0x130)

sys/dev/pci/drm/amd/include/v12_structs.h

98

uint32_t reserved_70; // offset: 70 (0x46)

sys/dev/pci/drm/amd/include/v12_structs.h

980

uint32_t reserved_305; // offset: 305 (0x131)

sys/dev/pci/drm/amd/include/v12_structs.h

981

uint32_t reserved_306; // offset: 306 (0x132)

sys/dev/pci/drm/amd/include/v12_structs.h

982

uint32_t reserved_307; // offset: 307 (0x133)

sys/dev/pci/drm/amd/include/v12_structs.h

983

uint32_t reserved_308; // offset: 308 (0x134)

sys/dev/pci/drm/amd/include/v12_structs.h

984

uint32_t reserved_309; // offset: 309 (0x135)

sys/dev/pci/drm/amd/include/v12_structs.h

985

uint32_t reserved_310; // offset: 310 (0x136)

sys/dev/pci/drm/amd/include/v12_structs.h

986

uint32_t reserved_311; // offset: 311 (0x137)

sys/dev/pci/drm/amd/include/v12_structs.h

987

uint32_t reserved_312; // offset: 312 (0x138)

sys/dev/pci/drm/amd/include/v12_structs.h

988

uint32_t reserved_313; // offset: 313 (0x139)

sys/dev/pci/drm/amd/include/v12_structs.h

989

uint32_t reserved_314; // offset: 314 (0x13A)

sys/dev/pci/drm/amd/include/v12_structs.h

99

uint32_t reserved_71; // offset: 71 (0x47)

sys/dev/pci/drm/amd/include/v12_structs.h

990

uint32_t reserved_315; // offset: 315 (0x13B)

sys/dev/pci/drm/amd/include/v12_structs.h

991

uint32_t reserved_316; // offset: 316 (0x13C)

sys/dev/pci/drm/amd/include/v12_structs.h

992

uint32_t reserved_317; // offset: 317 (0x13D)

sys/dev/pci/drm/amd/include/v12_structs.h

993

uint32_t reserved_318; // offset: 318 (0x13E)

sys/dev/pci/drm/amd/include/v12_structs.h

994

uint32_t reserved_319; // offset: 319 (0x13F)

sys/dev/pci/drm/amd/include/v12_structs.h

995

uint32_t reserved_320; // offset: 320 (0x140)

sys/dev/pci/drm/amd/include/v12_structs.h

996

uint32_t reserved_321; // offset: 321 (0x141)

sys/dev/pci/drm/amd/include/v12_structs.h

997

uint32_t reserved_322; // offset: 322 (0x142)

sys/dev/pci/drm/amd/include/v12_structs.h

998

uint32_t reserved_323; // offset: 323 (0x143)

sys/dev/pci/drm/amd/include/v12_structs.h

999

uint32_t reserved_324; // offset: 324 (0x144)

sys/dev/pci/drm/amd/include/v9_structs.h

100

uint32_t reserved_72;

sys/dev/pci/drm/amd/include/v9_structs.h

101

uint32_t reserved_73;

sys/dev/pci/drm/amd/include/v9_structs.h

102

uint32_t reserved_74;

sys/dev/pci/drm/amd/include/v9_structs.h

103

uint32_t reserved_75;

sys/dev/pci/drm/amd/include/v9_structs.h

104

uint32_t reserved_76;

sys/dev/pci/drm/amd/include/v9_structs.h

105

uint32_t reserved_77;

sys/dev/pci/drm/amd/include/v9_structs.h

106

uint32_t reserved_78;

sys/dev/pci/drm/amd/include/v9_structs.h

107

uint32_t reserved_79;

sys/dev/pci/drm/amd/include/v9_structs.h

108

uint32_t reserved_80;

sys/dev/pci/drm/amd/include/v9_structs.h

109

uint32_t reserved_81;

sys/dev/pci/drm/amd/include/v9_structs.h

110

uint32_t reserved_82;

sys/dev/pci/drm/amd/include/v9_structs.h

111

uint32_t reserved_83;

sys/dev/pci/drm/amd/include/v9_structs.h

112

uint32_t reserved_84;

sys/dev/pci/drm/amd/include/v9_structs.h

113

uint32_t reserved_85;

sys/dev/pci/drm/amd/include/v9_structs.h

114

uint32_t reserved_86;

sys/dev/pci/drm/amd/include/v9_structs.h

115

uint32_t reserved_87;

sys/dev/pci/drm/amd/include/v9_structs.h

116

uint32_t reserved_88;

sys/dev/pci/drm/amd/include/v9_structs.h

117

uint32_t reserved_89;

sys/dev/pci/drm/amd/include/v9_structs.h

118

uint32_t reserved_90;

sys/dev/pci/drm/amd/include/v9_structs.h

119

uint32_t reserved_91;

sys/dev/pci/drm/amd/include/v9_structs.h

120

uint32_t reserved_92;

sys/dev/pci/drm/amd/include/v9_structs.h

121

uint32_t reserved_93;

sys/dev/pci/drm/amd/include/v9_structs.h

122

uint32_t reserved_94;

sys/dev/pci/drm/amd/include/v9_structs.h

123

uint32_t reserved_95;

sys/dev/pci/drm/amd/include/v9_structs.h

124

uint32_t reserved_96;

sys/dev/pci/drm/amd/include/v9_structs.h

125

uint32_t reserved_97;

sys/dev/pci/drm/amd/include/v9_structs.h

126

uint32_t reserved_98;

sys/dev/pci/drm/amd/include/v9_structs.h

127

uint32_t reserved_99;

sys/dev/pci/drm/amd/include/v9_structs.h

128

uint32_t reserved_100;

sys/dev/pci/drm/amd/include/v9_structs.h

129

uint32_t reserved_101;

sys/dev/pci/drm/amd/include/v9_structs.h

130

uint32_t reserved_102;

sys/dev/pci/drm/amd/include/v9_structs.h

131

uint32_t reserved_103;

sys/dev/pci/drm/amd/include/v9_structs.h

132

uint32_t reserved_104;

sys/dev/pci/drm/amd/include/v9_structs.h

133

uint32_t reserved_105;

sys/dev/pci/drm/amd/include/v9_structs.h

134

uint32_t reserved_106;

sys/dev/pci/drm/amd/include/v9_structs.h

135

uint32_t reserved_107;

sys/dev/pci/drm/amd/include/v9_structs.h

136

uint32_t reserved_108;

sys/dev/pci/drm/amd/include/v9_structs.h

137

uint32_t reserved_109;

sys/dev/pci/drm/amd/include/v9_structs.h

138

uint32_t reserved_110;

sys/dev/pci/drm/amd/include/v9_structs.h

139

uint32_t reserved_111;

sys/dev/pci/drm/amd/include/v9_structs.h

140

uint32_t reserved_112;

sys/dev/pci/drm/amd/include/v9_structs.h

141

uint32_t reserved_113;

sys/dev/pci/drm/amd/include/v9_structs.h

142

uint32_t reserved_114;

sys/dev/pci/drm/amd/include/v9_structs.h

143

uint32_t reserved_115;

sys/dev/pci/drm/amd/include/v9_structs.h

144

uint32_t reserved_116;

sys/dev/pci/drm/amd/include/v9_structs.h

145

uint32_t reserved_117;

sys/dev/pci/drm/amd/include/v9_structs.h

146

uint32_t reserved_118;

sys/dev/pci/drm/amd/include/v9_structs.h

147

uint32_t reserved_119;

sys/dev/pci/drm/amd/include/v9_structs.h

148

uint32_t reserved_120;

sys/dev/pci/drm/amd/include/v9_structs.h

149

uint32_t reserved_121;

sys/dev/pci/drm/amd/include/v9_structs.h

150

uint32_t reserved_122;

sys/dev/pci/drm/amd/include/v9_structs.h

151

uint32_t reserved_123;

sys/dev/pci/drm/amd/include/v9_structs.h

152

uint32_t reserved_124;

sys/dev/pci/drm/amd/include/v9_structs.h

153

uint32_t reserved_125;

sys/dev/pci/drm/amd/include/v9_structs.h

155

uint32_t sdma_engine_id;

sys/dev/pci/drm/amd/include/v9_structs.h

156

uint32_t sdma_queue_id;

sys/dev/pci/drm/amd/include/v9_structs.h

160

uint32_t header;

sys/dev/pci/drm/amd/include/v9_structs.h

161

uint32_t compute_dispatch_initiator;

sys/dev/pci/drm/amd/include/v9_structs.h

162

uint32_t compute_dim_x;

sys/dev/pci/drm/amd/include/v9_structs.h

163

uint32_t compute_dim_y;

sys/dev/pci/drm/amd/include/v9_structs.h

164

uint32_t compute_dim_z;

sys/dev/pci/drm/amd/include/v9_structs.h

165

uint32_t compute_start_x;

sys/dev/pci/drm/amd/include/v9_structs.h

166

uint32_t compute_start_y;

sys/dev/pci/drm/amd/include/v9_structs.h

167

uint32_t compute_start_z;

sys/dev/pci/drm/amd/include/v9_structs.h

168

uint32_t compute_num_thread_x;

sys/dev/pci/drm/amd/include/v9_structs.h

169

uint32_t compute_num_thread_y;

sys/dev/pci/drm/amd/include/v9_structs.h

170

uint32_t compute_num_thread_z;

sys/dev/pci/drm/amd/include/v9_structs.h

171

uint32_t compute_pipelinestat_enable;

sys/dev/pci/drm/amd/include/v9_structs.h

172

uint32_t compute_perfcount_enable;

sys/dev/pci/drm/amd/include/v9_structs.h

173

uint32_t compute_pgm_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

174

uint32_t compute_pgm_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

175

uint32_t compute_tba_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

176

uint32_t compute_tba_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

177

uint32_t compute_tma_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

178

uint32_t compute_tma_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

179

uint32_t compute_pgm_rsrc1;

sys/dev/pci/drm/amd/include/v9_structs.h

180

uint32_t compute_pgm_rsrc2;

sys/dev/pci/drm/amd/include/v9_structs.h

181

uint32_t compute_vmid;

sys/dev/pci/drm/amd/include/v9_structs.h

182

uint32_t compute_resource_limits;

sys/dev/pci/drm/amd/include/v9_structs.h

183

uint32_t compute_static_thread_mgmt_se0;

sys/dev/pci/drm/amd/include/v9_structs.h

184

uint32_t compute_static_thread_mgmt_se1;

sys/dev/pci/drm/amd/include/v9_structs.h

185

uint32_t compute_tmpring_size;

sys/dev/pci/drm/amd/include/v9_structs.h

186

uint32_t compute_static_thread_mgmt_se2;

sys/dev/pci/drm/amd/include/v9_structs.h

187

uint32_t compute_static_thread_mgmt_se3;

sys/dev/pci/drm/amd/include/v9_structs.h

188

uint32_t compute_restart_x;

sys/dev/pci/drm/amd/include/v9_structs.h

189

uint32_t compute_restart_y;

sys/dev/pci/drm/amd/include/v9_structs.h

190

uint32_t compute_restart_z;

sys/dev/pci/drm/amd/include/v9_structs.h

191

uint32_t compute_thread_trace_enable;

sys/dev/pci/drm/amd/include/v9_structs.h

192

uint32_t compute_misc_reserved;

sys/dev/pci/drm/amd/include/v9_structs.h

193

uint32_t compute_dispatch_id;

sys/dev/pci/drm/amd/include/v9_structs.h

194

uint32_t compute_threadgroup_id;

sys/dev/pci/drm/amd/include/v9_structs.h

195

uint32_t compute_relaunch;

sys/dev/pci/drm/amd/include/v9_structs.h

196

uint32_t compute_wave_restore_addr_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

197

uint32_t compute_wave_restore_addr_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

198

uint32_t compute_wave_restore_control;

sys/dev/pci/drm/amd/include/v9_structs.h

201

uint32_t compute_static_thread_mgmt_se4;

sys/dev/pci/drm/amd/include/v9_structs.h

202

uint32_t compute_static_thread_mgmt_se5;

sys/dev/pci/drm/amd/include/v9_structs.h

203

uint32_t compute_static_thread_mgmt_se6;

sys/dev/pci/drm/amd/include/v9_structs.h

204

uint32_t compute_static_thread_mgmt_se7;

sys/dev/pci/drm/amd/include/v9_structs.h

207

uint32_t compute_current_logic_xcc_id; // offset: 39 (0x27)

sys/dev/pci/drm/amd/include/v9_structs.h

208

uint32_t compute_restart_cg_tg_id; // offset: 40 (0x28)

sys/dev/pci/drm/amd/include/v9_structs.h

209

uint32_t compute_tg_chunk_size; // offset: 41 (0x29)

sys/dev/pci/drm/amd/include/v9_structs.h

210

uint32_t compute_restore_tg_chunk_size; // offset: 42 (0x2A)

sys/dev/pci/drm/amd/include/v9_structs.h

213

uint32_t reserved_43;

sys/dev/pci/drm/amd/include/v9_structs.h

214

uint32_t reserved_44;

sys/dev/pci/drm/amd/include/v9_structs.h

215

uint32_t reserved_45;

sys/dev/pci/drm/amd/include/v9_structs.h

216

uint32_t reserved_46;

sys/dev/pci/drm/amd/include/v9_structs.h

217

uint32_t reserved_47;

sys/dev/pci/drm/amd/include/v9_structs.h

218

uint32_t reserved_48;

sys/dev/pci/drm/amd/include/v9_structs.h

219

uint32_t reserved_49;

sys/dev/pci/drm/amd/include/v9_structs.h

220

uint32_t reserved_50;

sys/dev/pci/drm/amd/include/v9_structs.h

221

uint32_t reserved_51;

sys/dev/pci/drm/amd/include/v9_structs.h

222

uint32_t reserved_52;

sys/dev/pci/drm/amd/include/v9_structs.h

223

uint32_t reserved_53;

sys/dev/pci/drm/amd/include/v9_structs.h

224

uint32_t reserved_54;

sys/dev/pci/drm/amd/include/v9_structs.h

225

uint32_t reserved_55;

sys/dev/pci/drm/amd/include/v9_structs.h

226

uint32_t reserved_56;

sys/dev/pci/drm/amd/include/v9_structs.h

227

uint32_t reserved_57;

sys/dev/pci/drm/amd/include/v9_structs.h

228

uint32_t reserved_58;

sys/dev/pci/drm/amd/include/v9_structs.h

229

uint32_t reserved_59;

sys/dev/pci/drm/amd/include/v9_structs.h

230

uint32_t reserved_60;

sys/dev/pci/drm/amd/include/v9_structs.h

231

uint32_t reserved_61;

sys/dev/pci/drm/amd/include/v9_structs.h

232

uint32_t reserved_62;

sys/dev/pci/drm/amd/include/v9_structs.h

233

uint32_t reserved_63;

sys/dev/pci/drm/amd/include/v9_structs.h

234

uint32_t reserved_64;

sys/dev/pci/drm/amd/include/v9_structs.h

235

uint32_t compute_user_data_0;

sys/dev/pci/drm/amd/include/v9_structs.h

236

uint32_t compute_user_data_1;

sys/dev/pci/drm/amd/include/v9_structs.h

237

uint32_t compute_user_data_2;

sys/dev/pci/drm/amd/include/v9_structs.h

238

uint32_t compute_user_data_3;

sys/dev/pci/drm/amd/include/v9_structs.h

239

uint32_t compute_user_data_4;

sys/dev/pci/drm/amd/include/v9_structs.h

240

uint32_t compute_user_data_5;

sys/dev/pci/drm/amd/include/v9_structs.h

241

uint32_t compute_user_data_6;

sys/dev/pci/drm/amd/include/v9_structs.h

242

uint32_t compute_user_data_7;

sys/dev/pci/drm/amd/include/v9_structs.h

243

uint32_t compute_user_data_8;

sys/dev/pci/drm/amd/include/v9_structs.h

244

uint32_t compute_user_data_9;

sys/dev/pci/drm/amd/include/v9_structs.h

245

uint32_t compute_user_data_10;

sys/dev/pci/drm/amd/include/v9_structs.h

246

uint32_t compute_user_data_11;

sys/dev/pci/drm/amd/include/v9_structs.h

247

uint32_t compute_user_data_12;

sys/dev/pci/drm/amd/include/v9_structs.h

248

uint32_t compute_user_data_13;

sys/dev/pci/drm/amd/include/v9_structs.h

249

uint32_t compute_user_data_14;

sys/dev/pci/drm/amd/include/v9_structs.h

250

uint32_t compute_user_data_15;

sys/dev/pci/drm/amd/include/v9_structs.h

251

uint32_t cp_compute_csinvoc_count_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

252

uint32_t cp_compute_csinvoc_count_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

253

uint32_t reserved_83;

sys/dev/pci/drm/amd/include/v9_structs.h

254

uint32_t reserved_84;

sys/dev/pci/drm/amd/include/v9_structs.h

255

uint32_t reserved_85;

sys/dev/pci/drm/amd/include/v9_structs.h

256

uint32_t cp_mqd_query_time_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

257

uint32_t cp_mqd_query_time_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

258

uint32_t cp_mqd_connect_start_time_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

259

uint32_t cp_mqd_connect_start_time_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

260

uint32_t cp_mqd_connect_end_time_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

261

uint32_t cp_mqd_connect_end_time_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

262

uint32_t cp_mqd_connect_end_wf_count;

sys/dev/pci/drm/amd/include/v9_structs.h

263

uint32_t cp_mqd_connect_end_pq_rptr;

sys/dev/pci/drm/amd/include/v9_structs.h

264

uint32_t cp_mqd_connect_end_pq_wptr;

sys/dev/pci/drm/amd/include/v9_structs.h

265

uint32_t cp_mqd_connect_end_ib_rptr;

sys/dev/pci/drm/amd/include/v9_structs.h

266

uint32_t cp_mqd_readindex_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

267

uint32_t cp_mqd_readindex_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

268

uint32_t cp_mqd_save_start_time_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

269

uint32_t cp_mqd_save_start_time_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

270

uint32_t cp_mqd_save_end_time_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

271

uint32_t cp_mqd_save_end_time_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

272

uint32_t cp_mqd_restore_start_time_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

273

uint32_t cp_mqd_restore_start_time_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

274

uint32_t cp_mqd_restore_end_time_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

275

uint32_t cp_mqd_restore_end_time_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

276

uint32_t disable_queue;

sys/dev/pci/drm/amd/include/v9_structs.h

277

uint32_t reserved_107;

sys/dev/pci/drm/amd/include/v9_structs.h

278

uint32_t gds_cs_ctxsw_cnt0;

sys/dev/pci/drm/amd/include/v9_structs.h

279

uint32_t gds_cs_ctxsw_cnt1;

sys/dev/pci/drm/amd/include/v9_structs.h

28

uint32_t sdmax_rlcx_rb_cntl;

sys/dev/pci/drm/amd/include/v9_structs.h

280

uint32_t gds_cs_ctxsw_cnt2;

sys/dev/pci/drm/amd/include/v9_structs.h

281

uint32_t gds_cs_ctxsw_cnt3;

sys/dev/pci/drm/amd/include/v9_structs.h

282

uint32_t reserved_112;

sys/dev/pci/drm/amd/include/v9_structs.h

283

uint32_t reserved_113;

sys/dev/pci/drm/amd/include/v9_structs.h

284

uint32_t cp_pq_exe_status_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

285

uint32_t cp_pq_exe_status_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

286

uint32_t cp_packet_id_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

287

uint32_t cp_packet_id_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

288

uint32_t cp_packet_exe_status_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

289

uint32_t cp_packet_exe_status_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

29

uint32_t sdmax_rlcx_rb_base;

sys/dev/pci/drm/amd/include/v9_structs.h

290

uint32_t gds_save_base_addr_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

291

uint32_t gds_save_base_addr_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

292

uint32_t gds_save_mask_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

293

uint32_t gds_save_mask_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

294

uint32_t ctx_save_base_addr_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

295

uint32_t ctx_save_base_addr_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

296

uint32_t dynamic_cu_mask_addr_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

297

uint32_t dynamic_cu_mask_addr_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

298

uint32_t cp_mqd_base_addr_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

299

uint32_t cp_mqd_base_addr_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

30

uint32_t sdmax_rlcx_rb_base_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

300

uint32_t cp_hqd_active;

sys/dev/pci/drm/amd/include/v9_structs.h

301

uint32_t cp_hqd_vmid;

sys/dev/pci/drm/amd/include/v9_structs.h

302

uint32_t cp_hqd_persistent_state;

sys/dev/pci/drm/amd/include/v9_structs.h

303

uint32_t cp_hqd_pipe_priority;

sys/dev/pci/drm/amd/include/v9_structs.h

304

uint32_t cp_hqd_queue_priority;

sys/dev/pci/drm/amd/include/v9_structs.h

305

uint32_t cp_hqd_quantum;

sys/dev/pci/drm/amd/include/v9_structs.h

306

uint32_t cp_hqd_pq_base_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

307

uint32_t cp_hqd_pq_base_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

308

uint32_t cp_hqd_pq_rptr;

sys/dev/pci/drm/amd/include/v9_structs.h

309

uint32_t cp_hqd_pq_rptr_report_addr_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

31

uint32_t sdmax_rlcx_rb_rptr;

sys/dev/pci/drm/amd/include/v9_structs.h

310

uint32_t cp_hqd_pq_rptr_report_addr_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

311

uint32_t cp_hqd_pq_wptr_poll_addr_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

312

uint32_t cp_hqd_pq_wptr_poll_addr_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

313

uint32_t cp_hqd_pq_doorbell_control;

sys/dev/pci/drm/amd/include/v9_structs.h

314

uint32_t reserved_144;

sys/dev/pci/drm/amd/include/v9_structs.h

315

uint32_t cp_hqd_pq_control;

sys/dev/pci/drm/amd/include/v9_structs.h

316

uint32_t cp_hqd_ib_base_addr_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

317

uint32_t cp_hqd_ib_base_addr_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

318

uint32_t cp_hqd_ib_rptr;

sys/dev/pci/drm/amd/include/v9_structs.h

319

uint32_t cp_hqd_ib_control;

sys/dev/pci/drm/amd/include/v9_structs.h

32

uint32_t sdmax_rlcx_rb_rptr_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

320

uint32_t cp_hqd_iq_timer;

sys/dev/pci/drm/amd/include/v9_structs.h

321

uint32_t cp_hqd_iq_rptr;

sys/dev/pci/drm/amd/include/v9_structs.h

322

uint32_t cp_hqd_dequeue_request;

sys/dev/pci/drm/amd/include/v9_structs.h

323

uint32_t cp_hqd_dma_offload;

sys/dev/pci/drm/amd/include/v9_structs.h

324

uint32_t cp_hqd_sema_cmd;

sys/dev/pci/drm/amd/include/v9_structs.h

325

uint32_t cp_hqd_msg_type;

sys/dev/pci/drm/amd/include/v9_structs.h

326

uint32_t cp_hqd_atomic0_preop_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

327

uint32_t cp_hqd_atomic0_preop_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

328

uint32_t cp_hqd_atomic1_preop_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

329

uint32_t cp_hqd_atomic1_preop_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

33

uint32_t sdmax_rlcx_rb_wptr;

sys/dev/pci/drm/amd/include/v9_structs.h

330

uint32_t cp_hqd_hq_status0;

sys/dev/pci/drm/amd/include/v9_structs.h

331

uint32_t cp_hqd_hq_control0;

sys/dev/pci/drm/amd/include/v9_structs.h

332

uint32_t cp_mqd_control;

sys/dev/pci/drm/amd/include/v9_structs.h

333

uint32_t cp_hqd_hq_status1;

sys/dev/pci/drm/amd/include/v9_structs.h

334

uint32_t cp_hqd_hq_control1;

sys/dev/pci/drm/amd/include/v9_structs.h

335

uint32_t cp_hqd_eop_base_addr_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

336

uint32_t cp_hqd_eop_base_addr_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

337

uint32_t cp_hqd_eop_control;

sys/dev/pci/drm/amd/include/v9_structs.h

338

uint32_t cp_hqd_eop_rptr;

sys/dev/pci/drm/amd/include/v9_structs.h

339

uint32_t cp_hqd_eop_wptr;

sys/dev/pci/drm/amd/include/v9_structs.h

34

uint32_t sdmax_rlcx_rb_wptr_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

340

uint32_t cp_hqd_eop_done_events;

sys/dev/pci/drm/amd/include/v9_structs.h

341

uint32_t cp_hqd_ctx_save_base_addr_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

342

uint32_t cp_hqd_ctx_save_base_addr_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

343

uint32_t cp_hqd_ctx_save_control;

sys/dev/pci/drm/amd/include/v9_structs.h

344

uint32_t cp_hqd_cntl_stack_offset;

sys/dev/pci/drm/amd/include/v9_structs.h

345

uint32_t cp_hqd_cntl_stack_size;

sys/dev/pci/drm/amd/include/v9_structs.h

346

uint32_t cp_hqd_wg_state_offset;

sys/dev/pci/drm/amd/include/v9_structs.h

347

uint32_t cp_hqd_ctx_save_size;

sys/dev/pci/drm/amd/include/v9_structs.h

348

uint32_t cp_hqd_gds_resource_state;

sys/dev/pci/drm/amd/include/v9_structs.h

349

uint32_t cp_hqd_error;

sys/dev/pci/drm/amd/include/v9_structs.h

35

uint32_t sdmax_rlcx_rb_wptr_poll_cntl;

sys/dev/pci/drm/amd/include/v9_structs.h

350

uint32_t cp_hqd_eop_wptr_mem;

sys/dev/pci/drm/amd/include/v9_structs.h

351

uint32_t cp_hqd_aql_control;

sys/dev/pci/drm/amd/include/v9_structs.h

352

uint32_t cp_hqd_pq_wptr_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

353

uint32_t cp_hqd_pq_wptr_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

354

uint32_t reserved_184;

sys/dev/pci/drm/amd/include/v9_structs.h

355

uint32_t reserved_185;

sys/dev/pci/drm/amd/include/v9_structs.h

356

uint32_t reserved_186;

sys/dev/pci/drm/amd/include/v9_structs.h

357

uint32_t reserved_187;

sys/dev/pci/drm/amd/include/v9_structs.h

358

uint32_t reserved_188;

sys/dev/pci/drm/amd/include/v9_structs.h

359

uint32_t reserved_189;

sys/dev/pci/drm/amd/include/v9_structs.h

36

uint32_t sdmax_rlcx_rb_rptr_addr_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

360

uint32_t reserved_190;

sys/dev/pci/drm/amd/include/v9_structs.h

361

uint32_t reserved_191;

sys/dev/pci/drm/amd/include/v9_structs.h

362

uint32_t iqtimer_pkt_header;

sys/dev/pci/drm/amd/include/v9_structs.h

363

uint32_t iqtimer_pkt_dw0;

sys/dev/pci/drm/amd/include/v9_structs.h

364

uint32_t iqtimer_pkt_dw1;

sys/dev/pci/drm/amd/include/v9_structs.h

365

uint32_t iqtimer_pkt_dw2;

sys/dev/pci/drm/amd/include/v9_structs.h

366

uint32_t iqtimer_pkt_dw3;

sys/dev/pci/drm/amd/include/v9_structs.h

367

uint32_t iqtimer_pkt_dw4;

sys/dev/pci/drm/amd/include/v9_structs.h

368

uint32_t iqtimer_pkt_dw5;

sys/dev/pci/drm/amd/include/v9_structs.h

369

uint32_t iqtimer_pkt_dw6;

sys/dev/pci/drm/amd/include/v9_structs.h

37

uint32_t sdmax_rlcx_rb_rptr_addr_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

370

uint32_t iqtimer_pkt_dw7;

sys/dev/pci/drm/amd/include/v9_structs.h

371

uint32_t iqtimer_pkt_dw8;

sys/dev/pci/drm/amd/include/v9_structs.h

372

uint32_t iqtimer_pkt_dw9;

sys/dev/pci/drm/amd/include/v9_structs.h

373

uint32_t iqtimer_pkt_dw10;

sys/dev/pci/drm/amd/include/v9_structs.h

374

uint32_t iqtimer_pkt_dw11;

sys/dev/pci/drm/amd/include/v9_structs.h

375

uint32_t iqtimer_pkt_dw12;

sys/dev/pci/drm/amd/include/v9_structs.h

376

uint32_t iqtimer_pkt_dw13;

sys/dev/pci/drm/amd/include/v9_structs.h

377

uint32_t iqtimer_pkt_dw14;

sys/dev/pci/drm/amd/include/v9_structs.h

378

uint32_t iqtimer_pkt_dw15;

sys/dev/pci/drm/amd/include/v9_structs.h

379

uint32_t iqtimer_pkt_dw16;

sys/dev/pci/drm/amd/include/v9_structs.h

38

uint32_t sdmax_rlcx_ib_cntl;

sys/dev/pci/drm/amd/include/v9_structs.h

380

uint32_t iqtimer_pkt_dw17;

sys/dev/pci/drm/amd/include/v9_structs.h

381

uint32_t iqtimer_pkt_dw18;

sys/dev/pci/drm/amd/include/v9_structs.h

382

uint32_t iqtimer_pkt_dw19;

sys/dev/pci/drm/amd/include/v9_structs.h

383

uint32_t iqtimer_pkt_dw20;

sys/dev/pci/drm/amd/include/v9_structs.h

384

uint32_t iqtimer_pkt_dw21;

sys/dev/pci/drm/amd/include/v9_structs.h

385

uint32_t iqtimer_pkt_dw22;

sys/dev/pci/drm/amd/include/v9_structs.h

386

uint32_t iqtimer_pkt_dw23;

sys/dev/pci/drm/amd/include/v9_structs.h

387

uint32_t iqtimer_pkt_dw24;

sys/dev/pci/drm/amd/include/v9_structs.h

388

uint32_t iqtimer_pkt_dw25;

sys/dev/pci/drm/amd/include/v9_structs.h

389

uint32_t iqtimer_pkt_dw26;

sys/dev/pci/drm/amd/include/v9_structs.h

39

uint32_t sdmax_rlcx_ib_rptr;

sys/dev/pci/drm/amd/include/v9_structs.h

390

uint32_t iqtimer_pkt_dw27;

sys/dev/pci/drm/amd/include/v9_structs.h

391

uint32_t iqtimer_pkt_dw28;

sys/dev/pci/drm/amd/include/v9_structs.h

392

uint32_t iqtimer_pkt_dw29;

sys/dev/pci/drm/amd/include/v9_structs.h

393

uint32_t iqtimer_pkt_dw30;

sys/dev/pci/drm/amd/include/v9_structs.h

394

uint32_t iqtimer_pkt_dw31;

sys/dev/pci/drm/amd/include/v9_structs.h

397

uint32_t reserved_225;

sys/dev/pci/drm/amd/include/v9_structs.h

398

uint32_t reserved_226;

sys/dev/pci/drm/amd/include/v9_structs.h

40

uint32_t sdmax_rlcx_ib_offset;

sys/dev/pci/drm/amd/include/v9_structs.h

401

uint32_t pm4_target_xcc_in_xcp; // offset: 225 (0xE1)

sys/dev/pci/drm/amd/include/v9_structs.h

402

uint32_t cp_mqd_stride_size; // offset: 226 (0xE2)

sys/dev/pci/drm/amd/include/v9_structs.h

405

uint32_t reserved_227;

sys/dev/pci/drm/amd/include/v9_structs.h

406

uint32_t set_resources_header;

sys/dev/pci/drm/amd/include/v9_structs.h

407

uint32_t set_resources_dw1;

sys/dev/pci/drm/amd/include/v9_structs.h

408

uint32_t set_resources_dw2;

sys/dev/pci/drm/amd/include/v9_structs.h

409

uint32_t set_resources_dw3;

sys/dev/pci/drm/amd/include/v9_structs.h

41

uint32_t sdmax_rlcx_ib_base_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

410

uint32_t set_resources_dw4;

sys/dev/pci/drm/amd/include/v9_structs.h

411

uint32_t set_resources_dw5;

sys/dev/pci/drm/amd/include/v9_structs.h

412

uint32_t set_resources_dw6;

sys/dev/pci/drm/amd/include/v9_structs.h

413

uint32_t set_resources_dw7;

sys/dev/pci/drm/amd/include/v9_structs.h

414

uint32_t reserved_236;

sys/dev/pci/drm/amd/include/v9_structs.h

415

uint32_t reserved_237;

sys/dev/pci/drm/amd/include/v9_structs.h

416

uint32_t reserved_238;

sys/dev/pci/drm/amd/include/v9_structs.h

417

uint32_t reserved_239;

sys/dev/pci/drm/amd/include/v9_structs.h

418

uint32_t queue_doorbell_id0;

sys/dev/pci/drm/amd/include/v9_structs.h

419

uint32_t queue_doorbell_id1;

sys/dev/pci/drm/amd/include/v9_structs.h

42

uint32_t sdmax_rlcx_ib_base_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

420

uint32_t queue_doorbell_id2;

sys/dev/pci/drm/amd/include/v9_structs.h

421

uint32_t queue_doorbell_id3;

sys/dev/pci/drm/amd/include/v9_structs.h

422

uint32_t queue_doorbell_id4;

sys/dev/pci/drm/amd/include/v9_structs.h

423

uint32_t queue_doorbell_id5;

sys/dev/pci/drm/amd/include/v9_structs.h

424

uint32_t queue_doorbell_id6;

sys/dev/pci/drm/amd/include/v9_structs.h

425

uint32_t queue_doorbell_id7;

sys/dev/pci/drm/amd/include/v9_structs.h

426

uint32_t queue_doorbell_id8;

sys/dev/pci/drm/amd/include/v9_structs.h

427

uint32_t queue_doorbell_id9;

sys/dev/pci/drm/amd/include/v9_structs.h

428

uint32_t queue_doorbell_id10;

sys/dev/pci/drm/amd/include/v9_structs.h

429

uint32_t queue_doorbell_id11;

sys/dev/pci/drm/amd/include/v9_structs.h

43

uint32_t sdmax_rlcx_ib_size;

sys/dev/pci/drm/amd/include/v9_structs.h

430

uint32_t queue_doorbell_id12;

sys/dev/pci/drm/amd/include/v9_structs.h

431

uint32_t queue_doorbell_id13;

sys/dev/pci/drm/amd/include/v9_structs.h

432

uint32_t queue_doorbell_id14;

sys/dev/pci/drm/amd/include/v9_structs.h

433

uint32_t queue_doorbell_id15;

sys/dev/pci/drm/amd/include/v9_structs.h

434

uint32_t reserved_256;

sys/dev/pci/drm/amd/include/v9_structs.h

435

uint32_t reserved_257;

sys/dev/pci/drm/amd/include/v9_structs.h

436

uint32_t reserved_258;

sys/dev/pci/drm/amd/include/v9_structs.h

437

uint32_t reserved_259;

sys/dev/pci/drm/amd/include/v9_structs.h

438

uint32_t reserved_260;

sys/dev/pci/drm/amd/include/v9_structs.h

439

uint32_t reserved_261;

sys/dev/pci/drm/amd/include/v9_structs.h

44

uint32_t sdmax_rlcx_skip_cntl;

sys/dev/pci/drm/amd/include/v9_structs.h

440

uint32_t reserved_262;

sys/dev/pci/drm/amd/include/v9_structs.h

441

uint32_t reserved_263;

sys/dev/pci/drm/amd/include/v9_structs.h

442

uint32_t reserved_264;

sys/dev/pci/drm/amd/include/v9_structs.h

443

uint32_t reserved_265;

sys/dev/pci/drm/amd/include/v9_structs.h

444

uint32_t reserved_266;

sys/dev/pci/drm/amd/include/v9_structs.h

445

uint32_t reserved_267;

sys/dev/pci/drm/amd/include/v9_structs.h

446

uint32_t reserved_268;

sys/dev/pci/drm/amd/include/v9_structs.h

447

uint32_t reserved_269;

sys/dev/pci/drm/amd/include/v9_structs.h

448

uint32_t reserved_270;

sys/dev/pci/drm/amd/include/v9_structs.h

449

uint32_t reserved_271;

sys/dev/pci/drm/amd/include/v9_structs.h

45

uint32_t sdmax_rlcx_context_status;

sys/dev/pci/drm/amd/include/v9_structs.h

450

uint32_t reserved_272;

sys/dev/pci/drm/amd/include/v9_structs.h

451

uint32_t reserved_273;

sys/dev/pci/drm/amd/include/v9_structs.h

452

uint32_t reserved_274;

sys/dev/pci/drm/amd/include/v9_structs.h

453

uint32_t reserved_275;

sys/dev/pci/drm/amd/include/v9_structs.h

454

uint32_t reserved_276;

sys/dev/pci/drm/amd/include/v9_structs.h

455

uint32_t reserved_277;

sys/dev/pci/drm/amd/include/v9_structs.h

456

uint32_t reserved_278;

sys/dev/pci/drm/amd/include/v9_structs.h

457

uint32_t reserved_279;

sys/dev/pci/drm/amd/include/v9_structs.h

458

uint32_t reserved_280;

sys/dev/pci/drm/amd/include/v9_structs.h

459

uint32_t reserved_281;

sys/dev/pci/drm/amd/include/v9_structs.h

46

uint32_t sdmax_rlcx_doorbell;

sys/dev/pci/drm/amd/include/v9_structs.h

460

uint32_t reserved_282;

sys/dev/pci/drm/amd/include/v9_structs.h

461

uint32_t reserved_283;

sys/dev/pci/drm/amd/include/v9_structs.h

462

uint32_t reserved_284;

sys/dev/pci/drm/amd/include/v9_structs.h

463

uint32_t reserved_285;

sys/dev/pci/drm/amd/include/v9_structs.h

464

uint32_t reserved_286;

sys/dev/pci/drm/amd/include/v9_structs.h

465

uint32_t reserved_287;

sys/dev/pci/drm/amd/include/v9_structs.h

466

uint32_t reserved_288;

sys/dev/pci/drm/amd/include/v9_structs.h

467

uint32_t reserved_289;

sys/dev/pci/drm/amd/include/v9_structs.h

468

uint32_t reserved_290;

sys/dev/pci/drm/amd/include/v9_structs.h

469

uint32_t reserved_291;

sys/dev/pci/drm/amd/include/v9_structs.h

47

uint32_t sdmax_rlcx_status;

sys/dev/pci/drm/amd/include/v9_structs.h

470

uint32_t reserved_292;

sys/dev/pci/drm/amd/include/v9_structs.h

471

uint32_t reserved_293;

sys/dev/pci/drm/amd/include/v9_structs.h

472

uint32_t reserved_294;

sys/dev/pci/drm/amd/include/v9_structs.h

473

uint32_t reserved_295;

sys/dev/pci/drm/amd/include/v9_structs.h

474

uint32_t reserved_296;

sys/dev/pci/drm/amd/include/v9_structs.h

475

uint32_t reserved_297;

sys/dev/pci/drm/amd/include/v9_structs.h

476

uint32_t reserved_298;

sys/dev/pci/drm/amd/include/v9_structs.h

477

uint32_t reserved_299;

sys/dev/pci/drm/amd/include/v9_structs.h

478

uint32_t reserved_300;

sys/dev/pci/drm/amd/include/v9_structs.h

479

uint32_t reserved_301;

sys/dev/pci/drm/amd/include/v9_structs.h

48

uint32_t sdmax_rlcx_doorbell_log;

sys/dev/pci/drm/amd/include/v9_structs.h

480

uint32_t reserved_302;

sys/dev/pci/drm/amd/include/v9_structs.h

481

uint32_t reserved_303;

sys/dev/pci/drm/amd/include/v9_structs.h

482

uint32_t reserved_304;

sys/dev/pci/drm/amd/include/v9_structs.h

483

uint32_t reserved_305;

sys/dev/pci/drm/amd/include/v9_structs.h

484

uint32_t reserved_306;

sys/dev/pci/drm/amd/include/v9_structs.h

485

uint32_t reserved_307;

sys/dev/pci/drm/amd/include/v9_structs.h

486

uint32_t reserved_308;

sys/dev/pci/drm/amd/include/v9_structs.h

487

uint32_t reserved_309;

sys/dev/pci/drm/amd/include/v9_structs.h

488

uint32_t reserved_310;

sys/dev/pci/drm/amd/include/v9_structs.h

489

uint32_t reserved_311;

sys/dev/pci/drm/amd/include/v9_structs.h

49

uint32_t sdmax_rlcx_watermark;

sys/dev/pci/drm/amd/include/v9_structs.h

490

uint32_t reserved_312;

sys/dev/pci/drm/amd/include/v9_structs.h

491

uint32_t reserved_313;

sys/dev/pci/drm/amd/include/v9_structs.h

492

uint32_t reserved_314;

sys/dev/pci/drm/amd/include/v9_structs.h

493

uint32_t reserved_315;

sys/dev/pci/drm/amd/include/v9_structs.h

494

uint32_t reserved_316;

sys/dev/pci/drm/amd/include/v9_structs.h

495

uint32_t reserved_317;

sys/dev/pci/drm/amd/include/v9_structs.h

496

uint32_t reserved_318;

sys/dev/pci/drm/amd/include/v9_structs.h

497

uint32_t reserved_319;

sys/dev/pci/drm/amd/include/v9_structs.h

498

uint32_t reserved_320;

sys/dev/pci/drm/amd/include/v9_structs.h

499

uint32_t reserved_321;

sys/dev/pci/drm/amd/include/v9_structs.h

50

uint32_t sdmax_rlcx_doorbell_offset;

sys/dev/pci/drm/amd/include/v9_structs.h

500

uint32_t reserved_322;

sys/dev/pci/drm/amd/include/v9_structs.h

501

uint32_t reserved_323;

sys/dev/pci/drm/amd/include/v9_structs.h

502

uint32_t reserved_324;

sys/dev/pci/drm/amd/include/v9_structs.h

503

uint32_t reserved_325;

sys/dev/pci/drm/amd/include/v9_structs.h

504

uint32_t reserved_326;

sys/dev/pci/drm/amd/include/v9_structs.h

505

uint32_t reserved_327;

sys/dev/pci/drm/amd/include/v9_structs.h

506

uint32_t reserved_328;

sys/dev/pci/drm/amd/include/v9_structs.h

507

uint32_t reserved_329;

sys/dev/pci/drm/amd/include/v9_structs.h

508

uint32_t reserved_330;

sys/dev/pci/drm/amd/include/v9_structs.h

509

uint32_t reserved_331;

sys/dev/pci/drm/amd/include/v9_structs.h

51

uint32_t sdmax_rlcx_csa_addr_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

510

uint32_t reserved_332;

sys/dev/pci/drm/amd/include/v9_structs.h

511

uint32_t reserved_333;

sys/dev/pci/drm/amd/include/v9_structs.h

512

uint32_t reserved_334;

sys/dev/pci/drm/amd/include/v9_structs.h

513

uint32_t reserved_335;

sys/dev/pci/drm/amd/include/v9_structs.h

514

uint32_t reserved_336;

sys/dev/pci/drm/amd/include/v9_structs.h

515

uint32_t reserved_337;

sys/dev/pci/drm/amd/include/v9_structs.h

516

uint32_t reserved_338;

sys/dev/pci/drm/amd/include/v9_structs.h

517

uint32_t reserved_339;

sys/dev/pci/drm/amd/include/v9_structs.h

518

uint32_t reserved_340;

sys/dev/pci/drm/amd/include/v9_structs.h

519

uint32_t reserved_341;

sys/dev/pci/drm/amd/include/v9_structs.h

52

uint32_t sdmax_rlcx_csa_addr_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

520

uint32_t reserved_342;

sys/dev/pci/drm/amd/include/v9_structs.h

521

uint32_t reserved_343;

sys/dev/pci/drm/amd/include/v9_structs.h

522

uint32_t reserved_344;

sys/dev/pci/drm/amd/include/v9_structs.h

523

uint32_t reserved_345;

sys/dev/pci/drm/amd/include/v9_structs.h

524

uint32_t reserved_346;

sys/dev/pci/drm/amd/include/v9_structs.h

525

uint32_t reserved_347;

sys/dev/pci/drm/amd/include/v9_structs.h

526

uint32_t reserved_348;

sys/dev/pci/drm/amd/include/v9_structs.h

527

uint32_t reserved_349;

sys/dev/pci/drm/amd/include/v9_structs.h

528

uint32_t reserved_350;

sys/dev/pci/drm/amd/include/v9_structs.h

529

uint32_t reserved_351;

sys/dev/pci/drm/amd/include/v9_structs.h

53

uint32_t sdmax_rlcx_ib_sub_remain;

sys/dev/pci/drm/amd/include/v9_structs.h

530

uint32_t reserved_352;

sys/dev/pci/drm/amd/include/v9_structs.h

531

uint32_t reserved_353;

sys/dev/pci/drm/amd/include/v9_structs.h

532

uint32_t reserved_354;

sys/dev/pci/drm/amd/include/v9_structs.h

533

uint32_t reserved_355;

sys/dev/pci/drm/amd/include/v9_structs.h

534

uint32_t reserved_356;

sys/dev/pci/drm/amd/include/v9_structs.h

535

uint32_t reserved_357;

sys/dev/pci/drm/amd/include/v9_structs.h

536

uint32_t reserved_358;

sys/dev/pci/drm/amd/include/v9_structs.h

537

uint32_t reserved_359;

sys/dev/pci/drm/amd/include/v9_structs.h

538

uint32_t reserved_360;

sys/dev/pci/drm/amd/include/v9_structs.h

539

uint32_t reserved_361;

sys/dev/pci/drm/amd/include/v9_structs.h

54

uint32_t sdmax_rlcx_preempt;

sys/dev/pci/drm/amd/include/v9_structs.h

540

uint32_t reserved_362;

sys/dev/pci/drm/amd/include/v9_structs.h

541

uint32_t reserved_363;

sys/dev/pci/drm/amd/include/v9_structs.h

542

uint32_t reserved_364;

sys/dev/pci/drm/amd/include/v9_structs.h

543

uint32_t reserved_365;

sys/dev/pci/drm/amd/include/v9_structs.h

544

uint32_t reserved_366;

sys/dev/pci/drm/amd/include/v9_structs.h

545

uint32_t reserved_367;

sys/dev/pci/drm/amd/include/v9_structs.h

546

uint32_t reserved_368;

sys/dev/pci/drm/amd/include/v9_structs.h

547

uint32_t reserved_369;

sys/dev/pci/drm/amd/include/v9_structs.h

548

uint32_t reserved_370;

sys/dev/pci/drm/amd/include/v9_structs.h

549

uint32_t reserved_371;

sys/dev/pci/drm/amd/include/v9_structs.h

55

uint32_t sdmax_rlcx_dummy_reg;

sys/dev/pci/drm/amd/include/v9_structs.h

550

uint32_t reserved_372;

sys/dev/pci/drm/amd/include/v9_structs.h

551

uint32_t reserved_373;

sys/dev/pci/drm/amd/include/v9_structs.h

552

uint32_t reserved_374;

sys/dev/pci/drm/amd/include/v9_structs.h

553

uint32_t reserved_375;

sys/dev/pci/drm/amd/include/v9_structs.h

554

uint32_t reserved_376;

sys/dev/pci/drm/amd/include/v9_structs.h

555

uint32_t reserved_377;

sys/dev/pci/drm/amd/include/v9_structs.h

556

uint32_t reserved_378;

sys/dev/pci/drm/amd/include/v9_structs.h

557

uint32_t reserved_379;

sys/dev/pci/drm/amd/include/v9_structs.h

558

uint32_t reserved_380;

sys/dev/pci/drm/amd/include/v9_structs.h

559

uint32_t reserved_381;

sys/dev/pci/drm/amd/include/v9_structs.h

56

uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;

sys/dev/pci/drm/amd/include/v9_structs.h

560

uint32_t reserved_382;

sys/dev/pci/drm/amd/include/v9_structs.h

561

uint32_t reserved_383;

sys/dev/pci/drm/amd/include/v9_structs.h

562

uint32_t reserved_384;

sys/dev/pci/drm/amd/include/v9_structs.h

563

uint32_t reserved_385;

sys/dev/pci/drm/amd/include/v9_structs.h

564

uint32_t reserved_386;

sys/dev/pci/drm/amd/include/v9_structs.h

565

uint32_t reserved_387;

sys/dev/pci/drm/amd/include/v9_structs.h

566

uint32_t reserved_388;

sys/dev/pci/drm/amd/include/v9_structs.h

567

uint32_t reserved_389;

sys/dev/pci/drm/amd/include/v9_structs.h

568

uint32_t reserved_390;

sys/dev/pci/drm/amd/include/v9_structs.h

569

uint32_t reserved_391;

sys/dev/pci/drm/amd/include/v9_structs.h

57

uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;

sys/dev/pci/drm/amd/include/v9_structs.h

570

uint32_t reserved_392;

sys/dev/pci/drm/amd/include/v9_structs.h

571

uint32_t reserved_393;

sys/dev/pci/drm/amd/include/v9_structs.h

572

uint32_t reserved_394;

sys/dev/pci/drm/amd/include/v9_structs.h

573

uint32_t reserved_395;

sys/dev/pci/drm/amd/include/v9_structs.h

574

uint32_t reserved_396;

sys/dev/pci/drm/amd/include/v9_structs.h

575

uint32_t reserved_397;

sys/dev/pci/drm/amd/include/v9_structs.h

576

uint32_t reserved_398;

sys/dev/pci/drm/amd/include/v9_structs.h

577

uint32_t reserved_399;

sys/dev/pci/drm/amd/include/v9_structs.h

578

uint32_t reserved_400;

sys/dev/pci/drm/amd/include/v9_structs.h

579

uint32_t reserved_401;

sys/dev/pci/drm/amd/include/v9_structs.h

58

uint32_t sdmax_rlcx_rb_aql_cntl;

sys/dev/pci/drm/amd/include/v9_structs.h

580

uint32_t reserved_402;

sys/dev/pci/drm/amd/include/v9_structs.h

581

uint32_t reserved_403;

sys/dev/pci/drm/amd/include/v9_structs.h

582

uint32_t reserved_404;

sys/dev/pci/drm/amd/include/v9_structs.h

583

uint32_t reserved_405;

sys/dev/pci/drm/amd/include/v9_structs.h

584

uint32_t reserved_406;

sys/dev/pci/drm/amd/include/v9_structs.h

585

uint32_t reserved_407;

sys/dev/pci/drm/amd/include/v9_structs.h

586

uint32_t reserved_408;

sys/dev/pci/drm/amd/include/v9_structs.h

587

uint32_t reserved_409;

sys/dev/pci/drm/amd/include/v9_structs.h

588

uint32_t reserved_410;

sys/dev/pci/drm/amd/include/v9_structs.h

589

uint32_t reserved_411;

sys/dev/pci/drm/amd/include/v9_structs.h

59

uint32_t sdmax_rlcx_minor_ptr_update;

sys/dev/pci/drm/amd/include/v9_structs.h

590

uint32_t reserved_412;

sys/dev/pci/drm/amd/include/v9_structs.h

591

uint32_t reserved_413;

sys/dev/pci/drm/amd/include/v9_structs.h

592

uint32_t reserved_414;

sys/dev/pci/drm/amd/include/v9_structs.h

593

uint32_t reserved_415;

sys/dev/pci/drm/amd/include/v9_structs.h

594

uint32_t reserved_416;

sys/dev/pci/drm/amd/include/v9_structs.h

595

uint32_t reserved_417;

sys/dev/pci/drm/amd/include/v9_structs.h

596

uint32_t reserved_418;

sys/dev/pci/drm/amd/include/v9_structs.h

597

uint32_t reserved_419;

sys/dev/pci/drm/amd/include/v9_structs.h

598

uint32_t reserved_420;

sys/dev/pci/drm/amd/include/v9_structs.h

599

uint32_t reserved_421;

sys/dev/pci/drm/amd/include/v9_structs.h

60

uint32_t sdmax_rlcx_midcmd_data0;

sys/dev/pci/drm/amd/include/v9_structs.h

600

uint32_t reserved_422;

sys/dev/pci/drm/amd/include/v9_structs.h

601

uint32_t reserved_423;

sys/dev/pci/drm/amd/include/v9_structs.h

602

uint32_t reserved_424;

sys/dev/pci/drm/amd/include/v9_structs.h

603

uint32_t reserved_425;

sys/dev/pci/drm/amd/include/v9_structs.h

604

uint32_t reserved_426;

sys/dev/pci/drm/amd/include/v9_structs.h

605

uint32_t reserved_427;

sys/dev/pci/drm/amd/include/v9_structs.h

606

uint32_t reserved_428;

sys/dev/pci/drm/amd/include/v9_structs.h

607

uint32_t reserved_429;

sys/dev/pci/drm/amd/include/v9_structs.h

608

uint32_t reserved_430;

sys/dev/pci/drm/amd/include/v9_structs.h

609

uint32_t reserved_431;

sys/dev/pci/drm/amd/include/v9_structs.h

61

uint32_t sdmax_rlcx_midcmd_data1;

sys/dev/pci/drm/amd/include/v9_structs.h

610

uint32_t reserved_432;

sys/dev/pci/drm/amd/include/v9_structs.h

611

uint32_t reserved_433;

sys/dev/pci/drm/amd/include/v9_structs.h

612

uint32_t reserved_434;

sys/dev/pci/drm/amd/include/v9_structs.h

613

uint32_t reserved_435;

sys/dev/pci/drm/amd/include/v9_structs.h

614

uint32_t reserved_436;

sys/dev/pci/drm/amd/include/v9_structs.h

615

uint32_t reserved_437;

sys/dev/pci/drm/amd/include/v9_structs.h

616

uint32_t reserved_438;

sys/dev/pci/drm/amd/include/v9_structs.h

617

uint32_t reserved_439;

sys/dev/pci/drm/amd/include/v9_structs.h

618

uint32_t reserved_440;

sys/dev/pci/drm/amd/include/v9_structs.h

619

uint32_t reserved_441;

sys/dev/pci/drm/amd/include/v9_structs.h

62

uint32_t sdmax_rlcx_midcmd_data2;

sys/dev/pci/drm/amd/include/v9_structs.h

620

uint32_t reserved_442;

sys/dev/pci/drm/amd/include/v9_structs.h

621

uint32_t reserved_443;

sys/dev/pci/drm/amd/include/v9_structs.h

622

uint32_t reserved_444;

sys/dev/pci/drm/amd/include/v9_structs.h

623

uint32_t reserved_445;

sys/dev/pci/drm/amd/include/v9_structs.h

624

uint32_t reserved_446;

sys/dev/pci/drm/amd/include/v9_structs.h

625

uint32_t reserved_447;

sys/dev/pci/drm/amd/include/v9_structs.h

626

uint32_t reserved_448;

sys/dev/pci/drm/amd/include/v9_structs.h

627

uint32_t reserved_449;

sys/dev/pci/drm/amd/include/v9_structs.h

628

uint32_t reserved_450;

sys/dev/pci/drm/amd/include/v9_structs.h

629

uint32_t reserved_451;

sys/dev/pci/drm/amd/include/v9_structs.h

63

uint32_t sdmax_rlcx_midcmd_data3;

sys/dev/pci/drm/amd/include/v9_structs.h

630

uint32_t reserved_452;

sys/dev/pci/drm/amd/include/v9_structs.h

631

uint32_t reserved_453;

sys/dev/pci/drm/amd/include/v9_structs.h

632

uint32_t reserved_454;

sys/dev/pci/drm/amd/include/v9_structs.h

633

uint32_t reserved_455;

sys/dev/pci/drm/amd/include/v9_structs.h

634

uint32_t reserved_456;

sys/dev/pci/drm/amd/include/v9_structs.h

635

uint32_t reserved_457;

sys/dev/pci/drm/amd/include/v9_structs.h

636

uint32_t reserved_458;

sys/dev/pci/drm/amd/include/v9_structs.h

637

uint32_t reserved_459;

sys/dev/pci/drm/amd/include/v9_structs.h

638

uint32_t reserved_460;

sys/dev/pci/drm/amd/include/v9_structs.h

639

uint32_t reserved_461;

sys/dev/pci/drm/amd/include/v9_structs.h

64

uint32_t sdmax_rlcx_midcmd_data4;

sys/dev/pci/drm/amd/include/v9_structs.h

640

uint32_t reserved_462;

sys/dev/pci/drm/amd/include/v9_structs.h

641

uint32_t reserved_463;

sys/dev/pci/drm/amd/include/v9_structs.h

642

uint32_t reserved_464;

sys/dev/pci/drm/amd/include/v9_structs.h

643

uint32_t reserved_465;

sys/dev/pci/drm/amd/include/v9_structs.h

644

uint32_t reserved_466;

sys/dev/pci/drm/amd/include/v9_structs.h

645

uint32_t reserved_467;

sys/dev/pci/drm/amd/include/v9_structs.h

646

uint32_t reserved_468;

sys/dev/pci/drm/amd/include/v9_structs.h

647

uint32_t reserved_469;

sys/dev/pci/drm/amd/include/v9_structs.h

648

uint32_t reserved_470;

sys/dev/pci/drm/amd/include/v9_structs.h

649

uint32_t reserved_471;

sys/dev/pci/drm/amd/include/v9_structs.h

65

uint32_t sdmax_rlcx_midcmd_data5;

sys/dev/pci/drm/amd/include/v9_structs.h

650

uint32_t reserved_472;

sys/dev/pci/drm/amd/include/v9_structs.h

651

uint32_t reserved_473;

sys/dev/pci/drm/amd/include/v9_structs.h

652

uint32_t reserved_474;

sys/dev/pci/drm/amd/include/v9_structs.h

653

uint32_t reserved_475;

sys/dev/pci/drm/amd/include/v9_structs.h

654

uint32_t reserved_476;

sys/dev/pci/drm/amd/include/v9_structs.h

655

uint32_t reserved_477;

sys/dev/pci/drm/amd/include/v9_structs.h

656

uint32_t reserved_478;

sys/dev/pci/drm/amd/include/v9_structs.h

657

uint32_t reserved_479;

sys/dev/pci/drm/amd/include/v9_structs.h

658

uint32_t reserved_480;

sys/dev/pci/drm/amd/include/v9_structs.h

659

uint32_t reserved_481;

sys/dev/pci/drm/amd/include/v9_structs.h

66

uint32_t sdmax_rlcx_midcmd_data6;

sys/dev/pci/drm/amd/include/v9_structs.h

660

uint32_t reserved_482;

sys/dev/pci/drm/amd/include/v9_structs.h

661

uint32_t reserved_483;

sys/dev/pci/drm/amd/include/v9_structs.h

662

uint32_t reserved_484;

sys/dev/pci/drm/amd/include/v9_structs.h

663

uint32_t reserved_485;

sys/dev/pci/drm/amd/include/v9_structs.h

664

uint32_t reserved_486;

sys/dev/pci/drm/amd/include/v9_structs.h

665

uint32_t reserved_487;

sys/dev/pci/drm/amd/include/v9_structs.h

666

uint32_t reserved_488;

sys/dev/pci/drm/amd/include/v9_structs.h

667

uint32_t reserved_489;

sys/dev/pci/drm/amd/include/v9_structs.h

668

uint32_t reserved_490;

sys/dev/pci/drm/amd/include/v9_structs.h

669

uint32_t reserved_491;

sys/dev/pci/drm/amd/include/v9_structs.h

67

uint32_t sdmax_rlcx_midcmd_data7;

sys/dev/pci/drm/amd/include/v9_structs.h

670

uint32_t reserved_492;

sys/dev/pci/drm/amd/include/v9_structs.h

671

uint32_t reserved_493;

sys/dev/pci/drm/amd/include/v9_structs.h

672

uint32_t reserved_494;

sys/dev/pci/drm/amd/include/v9_structs.h

673

uint32_t reserved_495;

sys/dev/pci/drm/amd/include/v9_structs.h

674

uint32_t reserved_496;

sys/dev/pci/drm/amd/include/v9_structs.h

675

uint32_t reserved_497;

sys/dev/pci/drm/amd/include/v9_structs.h

676

uint32_t reserved_498;

sys/dev/pci/drm/amd/include/v9_structs.h

677

uint32_t reserved_499;

sys/dev/pci/drm/amd/include/v9_structs.h

678

uint32_t reserved_500;

sys/dev/pci/drm/amd/include/v9_structs.h

679

uint32_t reserved_501;

sys/dev/pci/drm/amd/include/v9_structs.h

68

uint32_t sdmax_rlcx_midcmd_data8;

sys/dev/pci/drm/amd/include/v9_structs.h

680

uint32_t reserved_502;

sys/dev/pci/drm/amd/include/v9_structs.h

681

uint32_t reserved_503;

sys/dev/pci/drm/amd/include/v9_structs.h

682

uint32_t reserved_504;

sys/dev/pci/drm/amd/include/v9_structs.h

683

uint32_t reserved_505;

sys/dev/pci/drm/amd/include/v9_structs.h

684

uint32_t reserved_506;

sys/dev/pci/drm/amd/include/v9_structs.h

685

uint32_t reserved_507;

sys/dev/pci/drm/amd/include/v9_structs.h

686

uint32_t reserved_508;

sys/dev/pci/drm/amd/include/v9_structs.h

687

uint32_t reserved_509;

sys/dev/pci/drm/amd/include/v9_structs.h

688

uint32_t reserved_510;

sys/dev/pci/drm/amd/include/v9_structs.h

689

uint32_t reserved_511;

sys/dev/pci/drm/amd/include/v9_structs.h

69

uint32_t sdmax_rlcx_midcmd_cntl;

sys/dev/pci/drm/amd/include/v9_structs.h

694

uint32_t wptr_poll_mem;

sys/dev/pci/drm/amd/include/v9_structs.h

695

uint32_t rptr_report_mem;

sys/dev/pci/drm/amd/include/v9_structs.h

696

uint32_t dynamic_cu_mask;

sys/dev/pci/drm/amd/include/v9_structs.h

697

uint32_t dynamic_rb_mask;

sys/dev/pci/drm/amd/include/v9_structs.h

70

uint32_t reserved_42;

sys/dev/pci/drm/amd/include/v9_structs.h

703

uint32_t ce_ib_completion_status;

sys/dev/pci/drm/amd/include/v9_structs.h

704

uint32_t ce_constegnine_count;

sys/dev/pci/drm/amd/include/v9_structs.h

705

uint32_t ce_ibOffset_ib1;

sys/dev/pci/drm/amd/include/v9_structs.h

706

uint32_t ce_ibOffset_ib2;

sys/dev/pci/drm/amd/include/v9_structs.h

709

uint32_t ce_chainib_addrlo_ib1;

sys/dev/pci/drm/amd/include/v9_structs.h

71

uint32_t reserved_43;

sys/dev/pci/drm/amd/include/v9_structs.h

710

uint32_t ce_chainib_addrlo_ib2;

sys/dev/pci/drm/amd/include/v9_structs.h

711

uint32_t ce_chainib_addrhi_ib1;

sys/dev/pci/drm/amd/include/v9_structs.h

712

uint32_t ce_chainib_addrhi_ib2;

sys/dev/pci/drm/amd/include/v9_structs.h

713

uint32_t ce_chainib_size_ib1;

sys/dev/pci/drm/amd/include/v9_structs.h

714

uint32_t ce_chainib_size_ib2;

sys/dev/pci/drm/amd/include/v9_structs.h

719

uint32_t ib_completion_status;

sys/dev/pci/drm/amd/include/v9_structs.h

72

uint32_t reserved_44;

sys/dev/pci/drm/amd/include/v9_structs.h

720

uint32_t de_constEngine_count;

sys/dev/pci/drm/amd/include/v9_structs.h

721

uint32_t ib_offset_ib1;

sys/dev/pci/drm/amd/include/v9_structs.h

722

uint32_t ib_offset_ib2;

sys/dev/pci/drm/amd/include/v9_structs.h

725

uint32_t chain_ib_addrlo_ib1;

sys/dev/pci/drm/amd/include/v9_structs.h

726

uint32_t chain_ib_addrlo_ib2;

sys/dev/pci/drm/amd/include/v9_structs.h

727

uint32_t chain_ib_addrhi_ib1;

sys/dev/pci/drm/amd/include/v9_structs.h

728

uint32_t chain_ib_addrhi_ib2;

sys/dev/pci/drm/amd/include/v9_structs.h

729

uint32_t chain_ib_size_ib1;

sys/dev/pci/drm/amd/include/v9_structs.h

73

uint32_t reserved_45;

sys/dev/pci/drm/amd/include/v9_structs.h

730

uint32_t chain_ib_size_ib2;

sys/dev/pci/drm/amd/include/v9_structs.h

733

uint32_t preamble_begin_ib1;

sys/dev/pci/drm/amd/include/v9_structs.h

734

uint32_t preamble_begin_ib2;

sys/dev/pci/drm/amd/include/v9_structs.h

735

uint32_t preamble_end_ib1;

sys/dev/pci/drm/amd/include/v9_structs.h

736

uint32_t preamble_end_ib2;

sys/dev/pci/drm/amd/include/v9_structs.h

739

uint32_t chain_ib_pream_addrlo_ib1;

sys/dev/pci/drm/amd/include/v9_structs.h

74

uint32_t reserved_46;

sys/dev/pci/drm/amd/include/v9_structs.h

740

uint32_t chain_ib_pream_addrlo_ib2;

sys/dev/pci/drm/amd/include/v9_structs.h

741

uint32_t chain_ib_pream_addrhi_ib1;

sys/dev/pci/drm/amd/include/v9_structs.h

742

uint32_t chain_ib_pream_addrhi_ib2;

sys/dev/pci/drm/amd/include/v9_structs.h

745

uint32_t draw_indirect_baseLo;

sys/dev/pci/drm/amd/include/v9_structs.h

746

uint32_t draw_indirect_baseHi;

sys/dev/pci/drm/amd/include/v9_structs.h

747

uint32_t disp_indirect_baseLo;

sys/dev/pci/drm/amd/include/v9_structs.h

748

uint32_t disp_indirect_baseHi;

sys/dev/pci/drm/amd/include/v9_structs.h

749

uint32_t gds_backup_addrlo;

sys/dev/pci/drm/amd/include/v9_structs.h

75

uint32_t reserved_47;

sys/dev/pci/drm/amd/include/v9_structs.h

750

uint32_t gds_backup_addrhi;

sys/dev/pci/drm/amd/include/v9_structs.h

751

uint32_t index_base_addrlo;

sys/dev/pci/drm/amd/include/v9_structs.h

752

uint32_t index_base_addrhi;

sys/dev/pci/drm/amd/include/v9_structs.h

753

uint32_t sample_cntl;

sys/dev/pci/drm/amd/include/v9_structs.h

759

uint32_t reserved1[54];

sys/dev/pci/drm/amd/include/v9_structs.h

76

uint32_t reserved_48;

sys/dev/pci/drm/amd/include/v9_structs.h

763

uint32_t DeIbBaseAddrLo;

sys/dev/pci/drm/amd/include/v9_structs.h

764

uint32_t DeIbBaseAddrHi;

sys/dev/pci/drm/amd/include/v9_structs.h

765

uint32_t reserved2[931];

sys/dev/pci/drm/amd/include/v9_structs.h

77

uint32_t reserved_49;

sys/dev/pci/drm/amd/include/v9_structs.h

78

uint32_t reserved_50;

sys/dev/pci/drm/amd/include/v9_structs.h

79

uint32_t reserved_51;

sys/dev/pci/drm/amd/include/v9_structs.h

80

uint32_t reserved_52;

sys/dev/pci/drm/amd/include/v9_structs.h

81

uint32_t reserved_53;

sys/dev/pci/drm/amd/include/v9_structs.h

82

uint32_t reserved_54;

sys/dev/pci/drm/amd/include/v9_structs.h

83

uint32_t reserved_55;

sys/dev/pci/drm/amd/include/v9_structs.h

84

uint32_t reserved_56;

sys/dev/pci/drm/amd/include/v9_structs.h

85

uint32_t reserved_57;

sys/dev/pci/drm/amd/include/v9_structs.h

86

uint32_t reserved_58;

sys/dev/pci/drm/amd/include/v9_structs.h

87

uint32_t reserved_59;

sys/dev/pci/drm/amd/include/v9_structs.h

88

uint32_t reserved_60;

sys/dev/pci/drm/amd/include/v9_structs.h

89

uint32_t reserved_61;

sys/dev/pci/drm/amd/include/v9_structs.h

90

uint32_t reserved_62;

sys/dev/pci/drm/amd/include/v9_structs.h

91

uint32_t reserved_63;

sys/dev/pci/drm/amd/include/v9_structs.h

92

uint32_t reserved_64;

sys/dev/pci/drm/amd/include/v9_structs.h

93

uint32_t reserved_65;

sys/dev/pci/drm/amd/include/v9_structs.h

94

uint32_t reserved_66;

sys/dev/pci/drm/amd/include/v9_structs.h

95

uint32_t reserved_67;

sys/dev/pci/drm/amd/include/v9_structs.h

96

uint32_t reserved_68;

sys/dev/pci/drm/amd/include/v9_structs.h

97

uint32_t reserved_69;

sys/dev/pci/drm/amd/include/v9_structs.h

98

uint32_t reserved_70;

sys/dev/pci/drm/amd/include/v9_structs.h

99

uint32_t reserved_71;

sys/dev/pci/drm/amd/include/vi_structs.h

100

uint32_t reserved_72;

sys/dev/pci/drm/amd/include/vi_structs.h

101

uint32_t reserved_73;

sys/dev/pci/drm/amd/include/vi_structs.h

102

uint32_t reserved_74;

sys/dev/pci/drm/amd/include/vi_structs.h

103

uint32_t reserved_75;

sys/dev/pci/drm/amd/include/vi_structs.h

104

uint32_t reserved_76;

sys/dev/pci/drm/amd/include/vi_structs.h

105

uint32_t reserved_77;

sys/dev/pci/drm/amd/include/vi_structs.h

106

uint32_t reserved_78;

sys/dev/pci/drm/amd/include/vi_structs.h

107

uint32_t reserved_79;

sys/dev/pci/drm/amd/include/vi_structs.h

108

uint32_t reserved_80;

sys/dev/pci/drm/amd/include/vi_structs.h

109

uint32_t reserved_81;

sys/dev/pci/drm/amd/include/vi_structs.h

110

uint32_t reserved_82;

sys/dev/pci/drm/amd/include/vi_structs.h

111

uint32_t reserved_83;

sys/dev/pci/drm/amd/include/vi_structs.h

112

uint32_t reserved_84;

sys/dev/pci/drm/amd/include/vi_structs.h

113

uint32_t reserved_85;

sys/dev/pci/drm/amd/include/vi_structs.h

114

uint32_t reserved_86;

sys/dev/pci/drm/amd/include/vi_structs.h

115

uint32_t reserved_87;

sys/dev/pci/drm/amd/include/vi_structs.h

116

uint32_t reserved_88;

sys/dev/pci/drm/amd/include/vi_structs.h

117

uint32_t reserved_89;

sys/dev/pci/drm/amd/include/vi_structs.h

118

uint32_t reserved_90;

sys/dev/pci/drm/amd/include/vi_structs.h

119

uint32_t reserved_91;

sys/dev/pci/drm/amd/include/vi_structs.h

120

uint32_t reserved_92;

sys/dev/pci/drm/amd/include/vi_structs.h

121

uint32_t reserved_93;

sys/dev/pci/drm/amd/include/vi_structs.h

122

uint32_t reserved_94;

sys/dev/pci/drm/amd/include/vi_structs.h

123

uint32_t reserved_95;

sys/dev/pci/drm/amd/include/vi_structs.h

124

uint32_t reserved_96;

sys/dev/pci/drm/amd/include/vi_structs.h

125

uint32_t reserved_97;

sys/dev/pci/drm/amd/include/vi_structs.h

126

uint32_t reserved_98;

sys/dev/pci/drm/amd/include/vi_structs.h

127

uint32_t reserved_99;

sys/dev/pci/drm/amd/include/vi_structs.h

128

uint32_t reserved_100;

sys/dev/pci/drm/amd/include/vi_structs.h

129

uint32_t reserved_101;

sys/dev/pci/drm/amd/include/vi_structs.h

130

uint32_t reserved_102;

sys/dev/pci/drm/amd/include/vi_structs.h

131

uint32_t reserved_103;

sys/dev/pci/drm/amd/include/vi_structs.h

132

uint32_t reserved_104;

sys/dev/pci/drm/amd/include/vi_structs.h

133

uint32_t reserved_105;

sys/dev/pci/drm/amd/include/vi_structs.h

134

uint32_t reserved_106;

sys/dev/pci/drm/amd/include/vi_structs.h

135

uint32_t reserved_107;

sys/dev/pci/drm/amd/include/vi_structs.h

136

uint32_t reserved_108;

sys/dev/pci/drm/amd/include/vi_structs.h

137

uint32_t reserved_109;

sys/dev/pci/drm/amd/include/vi_structs.h

138

uint32_t reserved_110;

sys/dev/pci/drm/amd/include/vi_structs.h

139

uint32_t reserved_111;

sys/dev/pci/drm/amd/include/vi_structs.h

140

uint32_t reserved_112;

sys/dev/pci/drm/amd/include/vi_structs.h

141

uint32_t reserved_113;

sys/dev/pci/drm/amd/include/vi_structs.h

142

uint32_t reserved_114;

sys/dev/pci/drm/amd/include/vi_structs.h

143

uint32_t reserved_115;

sys/dev/pci/drm/amd/include/vi_structs.h

144

uint32_t reserved_116;

sys/dev/pci/drm/amd/include/vi_structs.h

145

uint32_t reserved_117;

sys/dev/pci/drm/amd/include/vi_structs.h

146

uint32_t reserved_118;

sys/dev/pci/drm/amd/include/vi_structs.h

147

uint32_t reserved_119;

sys/dev/pci/drm/amd/include/vi_structs.h

148

uint32_t reserved_120;

sys/dev/pci/drm/amd/include/vi_structs.h

149

uint32_t reserved_121;

sys/dev/pci/drm/amd/include/vi_structs.h

150

uint32_t reserved_122;

sys/dev/pci/drm/amd/include/vi_structs.h

151

uint32_t reserved_123;

sys/dev/pci/drm/amd/include/vi_structs.h

152

uint32_t reserved_124;

sys/dev/pci/drm/amd/include/vi_structs.h

153

uint32_t reserved_125;

sys/dev/pci/drm/amd/include/vi_structs.h

155

uint32_t sdma_engine_id;

sys/dev/pci/drm/amd/include/vi_structs.h

156

uint32_t sdma_queue_id;

sys/dev/pci/drm/amd/include/vi_structs.h

160

uint32_t header;

sys/dev/pci/drm/amd/include/vi_structs.h

161

uint32_t compute_dispatch_initiator;

sys/dev/pci/drm/amd/include/vi_structs.h

162

uint32_t compute_dim_x;

sys/dev/pci/drm/amd/include/vi_structs.h

163

uint32_t compute_dim_y;

sys/dev/pci/drm/amd/include/vi_structs.h

164

uint32_t compute_dim_z;

sys/dev/pci/drm/amd/include/vi_structs.h

165

uint32_t compute_start_x;

sys/dev/pci/drm/amd/include/vi_structs.h

166

uint32_t compute_start_y;

sys/dev/pci/drm/amd/include/vi_structs.h

167

uint32_t compute_start_z;

sys/dev/pci/drm/amd/include/vi_structs.h

168

uint32_t compute_num_thread_x;

sys/dev/pci/drm/amd/include/vi_structs.h

169

uint32_t compute_num_thread_y;

sys/dev/pci/drm/amd/include/vi_structs.h

170

uint32_t compute_num_thread_z;

sys/dev/pci/drm/amd/include/vi_structs.h

171

uint32_t compute_pipelinestat_enable;

sys/dev/pci/drm/amd/include/vi_structs.h

172

uint32_t compute_perfcount_enable;

sys/dev/pci/drm/amd/include/vi_structs.h

173

uint32_t compute_pgm_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

174

uint32_t compute_pgm_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

175

uint32_t compute_tba_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

176

uint32_t compute_tba_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

177

uint32_t compute_tma_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

178

uint32_t compute_tma_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

179

uint32_t compute_pgm_rsrc1;

sys/dev/pci/drm/amd/include/vi_structs.h

180

uint32_t compute_pgm_rsrc2;

sys/dev/pci/drm/amd/include/vi_structs.h

181

uint32_t compute_vmid;

sys/dev/pci/drm/amd/include/vi_structs.h

182

uint32_t compute_resource_limits;

sys/dev/pci/drm/amd/include/vi_structs.h

183

uint32_t compute_static_thread_mgmt_se0;

sys/dev/pci/drm/amd/include/vi_structs.h

184

uint32_t compute_static_thread_mgmt_se1;

sys/dev/pci/drm/amd/include/vi_structs.h

185

uint32_t compute_tmpring_size;

sys/dev/pci/drm/amd/include/vi_structs.h

186

uint32_t compute_static_thread_mgmt_se2;

sys/dev/pci/drm/amd/include/vi_structs.h

187

uint32_t compute_static_thread_mgmt_se3;

sys/dev/pci/drm/amd/include/vi_structs.h

188

uint32_t compute_restart_x;

sys/dev/pci/drm/amd/include/vi_structs.h

189

uint32_t compute_restart_y;

sys/dev/pci/drm/amd/include/vi_structs.h

190

uint32_t compute_restart_z;

sys/dev/pci/drm/amd/include/vi_structs.h

191

uint32_t compute_thread_trace_enable;

sys/dev/pci/drm/amd/include/vi_structs.h

192

uint32_t compute_misc_reserved;

sys/dev/pci/drm/amd/include/vi_structs.h

193

uint32_t compute_dispatch_id;

sys/dev/pci/drm/amd/include/vi_structs.h

194

uint32_t compute_threadgroup_id;

sys/dev/pci/drm/amd/include/vi_structs.h

195

uint32_t compute_relaunch;

sys/dev/pci/drm/amd/include/vi_structs.h

196

uint32_t compute_wave_restore_addr_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

197

uint32_t compute_wave_restore_addr_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

198

uint32_t compute_wave_restore_control;

sys/dev/pci/drm/amd/include/vi_structs.h

199

uint32_t reserved9;

sys/dev/pci/drm/amd/include/vi_structs.h

200

uint32_t reserved10;

sys/dev/pci/drm/amd/include/vi_structs.h

201

uint32_t reserved11;

sys/dev/pci/drm/amd/include/vi_structs.h

202

uint32_t reserved12;

sys/dev/pci/drm/amd/include/vi_structs.h

203

uint32_t reserved13;

sys/dev/pci/drm/amd/include/vi_structs.h

204

uint32_t reserved14;

sys/dev/pci/drm/amd/include/vi_structs.h

205

uint32_t reserved15;

sys/dev/pci/drm/amd/include/vi_structs.h

206

uint32_t reserved16;

sys/dev/pci/drm/amd/include/vi_structs.h

207

uint32_t reserved17;

sys/dev/pci/drm/amd/include/vi_structs.h

208

uint32_t reserved18;

sys/dev/pci/drm/amd/include/vi_structs.h

209

uint32_t reserved19;

sys/dev/pci/drm/amd/include/vi_structs.h

210

uint32_t reserved20;

sys/dev/pci/drm/amd/include/vi_structs.h

211

uint32_t reserved21;

sys/dev/pci/drm/amd/include/vi_structs.h

212

uint32_t reserved22;

sys/dev/pci/drm/amd/include/vi_structs.h

213

uint32_t reserved23;

sys/dev/pci/drm/amd/include/vi_structs.h

214

uint32_t reserved24;

sys/dev/pci/drm/amd/include/vi_structs.h

215

uint32_t reserved25;

sys/dev/pci/drm/amd/include/vi_structs.h

216

uint32_t reserved26;

sys/dev/pci/drm/amd/include/vi_structs.h

217

uint32_t reserved27;

sys/dev/pci/drm/amd/include/vi_structs.h

218

uint32_t reserved28;

sys/dev/pci/drm/amd/include/vi_structs.h

219

uint32_t reserved29;

sys/dev/pci/drm/amd/include/vi_structs.h

220

uint32_t reserved30;

sys/dev/pci/drm/amd/include/vi_structs.h

221

uint32_t reserved31;

sys/dev/pci/drm/amd/include/vi_structs.h

222

uint32_t reserved32;

sys/dev/pci/drm/amd/include/vi_structs.h

223

uint32_t reserved33;

sys/dev/pci/drm/amd/include/vi_structs.h

224

uint32_t reserved34;

sys/dev/pci/drm/amd/include/vi_structs.h

225

uint32_t compute_user_data_0;

sys/dev/pci/drm/amd/include/vi_structs.h

226

uint32_t compute_user_data_1;

sys/dev/pci/drm/amd/include/vi_structs.h

227

uint32_t compute_user_data_2;

sys/dev/pci/drm/amd/include/vi_structs.h

228

uint32_t compute_user_data_3;

sys/dev/pci/drm/amd/include/vi_structs.h

229

uint32_t compute_user_data_4;

sys/dev/pci/drm/amd/include/vi_structs.h

230

uint32_t compute_user_data_5;

sys/dev/pci/drm/amd/include/vi_structs.h

231

uint32_t compute_user_data_6;

sys/dev/pci/drm/amd/include/vi_structs.h

232

uint32_t compute_user_data_7;

sys/dev/pci/drm/amd/include/vi_structs.h

233

uint32_t compute_user_data_8;

sys/dev/pci/drm/amd/include/vi_structs.h

234

uint32_t compute_user_data_9;

sys/dev/pci/drm/amd/include/vi_structs.h

235

uint32_t compute_user_data_10;

sys/dev/pci/drm/amd/include/vi_structs.h

236

uint32_t compute_user_data_11;

sys/dev/pci/drm/amd/include/vi_structs.h

237

uint32_t compute_user_data_12;

sys/dev/pci/drm/amd/include/vi_structs.h

238

uint32_t compute_user_data_13;

sys/dev/pci/drm/amd/include/vi_structs.h

239

uint32_t compute_user_data_14;

sys/dev/pci/drm/amd/include/vi_structs.h

240

uint32_t compute_user_data_15;

sys/dev/pci/drm/amd/include/vi_structs.h

241

uint32_t cp_compute_csinvoc_count_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

242

uint32_t cp_compute_csinvoc_count_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

243

uint32_t reserved35;

sys/dev/pci/drm/amd/include/vi_structs.h

244

uint32_t reserved36;

sys/dev/pci/drm/amd/include/vi_structs.h

245

uint32_t reserved37;

sys/dev/pci/drm/amd/include/vi_structs.h

246

uint32_t cp_mqd_query_time_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

247

uint32_t cp_mqd_query_time_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

248

uint32_t cp_mqd_connect_start_time_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

249

uint32_t cp_mqd_connect_start_time_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

250

uint32_t cp_mqd_connect_end_time_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

251

uint32_t cp_mqd_connect_end_time_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

252

uint32_t cp_mqd_connect_end_wf_count;

sys/dev/pci/drm/amd/include/vi_structs.h

253

uint32_t cp_mqd_connect_end_pq_rptr;

sys/dev/pci/drm/amd/include/vi_structs.h

254

uint32_t cp_mqd_connect_endvi_sdma_mqd_pq_wptr;

sys/dev/pci/drm/amd/include/vi_structs.h

255

uint32_t cp_mqd_connect_end_ib_rptr;

sys/dev/pci/drm/amd/include/vi_structs.h

256

uint32_t reserved38;

sys/dev/pci/drm/amd/include/vi_structs.h

257

uint32_t reserved39;

sys/dev/pci/drm/amd/include/vi_structs.h

258

uint32_t cp_mqd_save_start_time_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

259

uint32_t cp_mqd_save_start_time_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

260

uint32_t cp_mqd_save_end_time_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

261

uint32_t cp_mqd_save_end_time_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

262

uint32_t cp_mqd_restore_start_time_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

263

uint32_t cp_mqd_restore_start_time_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

264

uint32_t cp_mqd_restore_end_time_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

265

uint32_t cp_mqd_restore_end_time_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

266

uint32_t disable_queue;

sys/dev/pci/drm/amd/include/vi_structs.h

267

uint32_t reserved41;

sys/dev/pci/drm/amd/include/vi_structs.h

268

uint32_t gds_cs_ctxsw_cnt0;

sys/dev/pci/drm/amd/include/vi_structs.h

269

uint32_t gds_cs_ctxsw_cnt1;

sys/dev/pci/drm/amd/include/vi_structs.h

270

uint32_t gds_cs_ctxsw_cnt2;

sys/dev/pci/drm/amd/include/vi_structs.h

271

uint32_t gds_cs_ctxsw_cnt3;

sys/dev/pci/drm/amd/include/vi_structs.h

272

uint32_t reserved42;

sys/dev/pci/drm/amd/include/vi_structs.h

273

uint32_t reserved43;

sys/dev/pci/drm/amd/include/vi_structs.h

274

uint32_t cp_pq_exe_status_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

275

uint32_t cp_pq_exe_status_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

276

uint32_t cp_packet_id_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

277

uint32_t cp_packet_id_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

278

uint32_t cp_packet_exe_status_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

279

uint32_t cp_packet_exe_status_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

28

uint32_t sdmax_rlcx_rb_cntl;

sys/dev/pci/drm/amd/include/vi_structs.h

280

uint32_t gds_save_base_addr_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

281

uint32_t gds_save_base_addr_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

282

uint32_t gds_save_mask_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

283

uint32_t gds_save_mask_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

284

uint32_t ctx_save_base_addr_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

285

uint32_t ctx_save_base_addr_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

286

uint32_t dynamic_cu_mask_addr_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

287

uint32_t dynamic_cu_mask_addr_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

288

uint32_t cp_mqd_base_addr_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

289

uint32_t cp_mqd_base_addr_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

29

uint32_t sdmax_rlcx_rb_base;

sys/dev/pci/drm/amd/include/vi_structs.h

290

uint32_t cp_hqd_active;

sys/dev/pci/drm/amd/include/vi_structs.h

291

uint32_t cp_hqd_vmid;

sys/dev/pci/drm/amd/include/vi_structs.h

292

uint32_t cp_hqd_persistent_state;

sys/dev/pci/drm/amd/include/vi_structs.h

293

uint32_t cp_hqd_pipe_priority;

sys/dev/pci/drm/amd/include/vi_structs.h

294

uint32_t cp_hqd_queue_priority;

sys/dev/pci/drm/amd/include/vi_structs.h

295

uint32_t cp_hqd_quantum;

sys/dev/pci/drm/amd/include/vi_structs.h

296

uint32_t cp_hqd_pq_base_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

297

uint32_t cp_hqd_pq_base_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

298

uint32_t cp_hqd_pq_rptr;

sys/dev/pci/drm/amd/include/vi_structs.h

299

uint32_t cp_hqd_pq_rptr_report_addr_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

30

uint32_t sdmax_rlcx_rb_base_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

300

uint32_t cp_hqd_pq_rptr_report_addr_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

301

uint32_t cp_hqd_pq_wptr_poll_addr_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

302

uint32_t cp_hqd_pq_wptr_poll_addr_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

303

uint32_t cp_hqd_pq_doorbell_control;

sys/dev/pci/drm/amd/include/vi_structs.h

304

uint32_t cp_hqd_pq_wptr;

sys/dev/pci/drm/amd/include/vi_structs.h

305

uint32_t cp_hqd_pq_control;

sys/dev/pci/drm/amd/include/vi_structs.h

306

uint32_t cp_hqd_ib_base_addr_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

307

uint32_t cp_hqd_ib_base_addr_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

308

uint32_t cp_hqd_ib_rptr;

sys/dev/pci/drm/amd/include/vi_structs.h

309

uint32_t cp_hqd_ib_control;

sys/dev/pci/drm/amd/include/vi_structs.h

31

uint32_t sdmax_rlcx_rb_rptr;

sys/dev/pci/drm/amd/include/vi_structs.h

310

uint32_t cp_hqd_iq_timer;

sys/dev/pci/drm/amd/include/vi_structs.h

311

uint32_t cp_hqd_iq_rptr;

sys/dev/pci/drm/amd/include/vi_structs.h

312

uint32_t cp_hqd_dequeue_request;

sys/dev/pci/drm/amd/include/vi_structs.h

313

uint32_t cp_hqd_dma_offload;

sys/dev/pci/drm/amd/include/vi_structs.h

314

uint32_t cp_hqd_sema_cmd;

sys/dev/pci/drm/amd/include/vi_structs.h

315

uint32_t cp_hqd_msg_type;

sys/dev/pci/drm/amd/include/vi_structs.h

316

uint32_t cp_hqd_atomic0_preop_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

317

uint32_t cp_hqd_atomic0_preop_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

318

uint32_t cp_hqd_atomic1_preop_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

319

uint32_t cp_hqd_atomic1_preop_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

32

uint32_t sdmax_rlcx_rb_wptr;

sys/dev/pci/drm/amd/include/vi_structs.h

320

uint32_t cp_hqd_hq_status0;

sys/dev/pci/drm/amd/include/vi_structs.h

321

uint32_t cp_hqd_hq_control0;

sys/dev/pci/drm/amd/include/vi_structs.h

322

uint32_t cp_mqd_control;

sys/dev/pci/drm/amd/include/vi_structs.h

323

uint32_t cp_hqd_hq_status1;

sys/dev/pci/drm/amd/include/vi_structs.h

324

uint32_t cp_hqd_hq_control1;

sys/dev/pci/drm/amd/include/vi_structs.h

325

uint32_t cp_hqd_eop_base_addr_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

326

uint32_t cp_hqd_eop_base_addr_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

327

uint32_t cp_hqd_eop_control;

sys/dev/pci/drm/amd/include/vi_structs.h

328

uint32_t cp_hqd_eop_rptr;

sys/dev/pci/drm/amd/include/vi_structs.h

329

uint32_t cp_hqd_eop_wptr;

sys/dev/pci/drm/amd/include/vi_structs.h

33

uint32_t sdmax_rlcx_rb_wptr_poll_cntl;

sys/dev/pci/drm/amd/include/vi_structs.h

330

uint32_t cp_hqd_eop_done_events;

sys/dev/pci/drm/amd/include/vi_structs.h

331

uint32_t cp_hqd_ctx_save_base_addr_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

332

uint32_t cp_hqd_ctx_save_base_addr_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

333

uint32_t cp_hqd_ctx_save_control;

sys/dev/pci/drm/amd/include/vi_structs.h

334

uint32_t cp_hqd_cntl_stack_offset;

sys/dev/pci/drm/amd/include/vi_structs.h

335

uint32_t cp_hqd_cntl_stack_size;

sys/dev/pci/drm/amd/include/vi_structs.h

336

uint32_t cp_hqd_wg_state_offset;

sys/dev/pci/drm/amd/include/vi_structs.h

337

uint32_t cp_hqd_ctx_save_size;

sys/dev/pci/drm/amd/include/vi_structs.h

338

uint32_t cp_hqd_gds_resource_state;

sys/dev/pci/drm/amd/include/vi_structs.h

339

uint32_t cp_hqd_error;

sys/dev/pci/drm/amd/include/vi_structs.h

34

uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

340

uint32_t cp_hqd_eop_wptr_mem;

sys/dev/pci/drm/amd/include/vi_structs.h

341

uint32_t cp_hqd_eop_dones;

sys/dev/pci/drm/amd/include/vi_structs.h

342

uint32_t reserved46;

sys/dev/pci/drm/amd/include/vi_structs.h

343

uint32_t reserved47;

sys/dev/pci/drm/amd/include/vi_structs.h

344

uint32_t reserved48;

sys/dev/pci/drm/amd/include/vi_structs.h

345

uint32_t reserved49;

sys/dev/pci/drm/amd/include/vi_structs.h

346

uint32_t reserved50;

sys/dev/pci/drm/amd/include/vi_structs.h

347

uint32_t reserved51;

sys/dev/pci/drm/amd/include/vi_structs.h

348

uint32_t reserved52;

sys/dev/pci/drm/amd/include/vi_structs.h

349

uint32_t reserved53;

sys/dev/pci/drm/amd/include/vi_structs.h

35

uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

350

uint32_t reserved54;

sys/dev/pci/drm/amd/include/vi_structs.h

351

uint32_t reserved55;

sys/dev/pci/drm/amd/include/vi_structs.h

352

uint32_t iqtimer_pkt_header;

sys/dev/pci/drm/amd/include/vi_structs.h

353

uint32_t iqtimer_pkt_dw0;

sys/dev/pci/drm/amd/include/vi_structs.h

354

uint32_t iqtimer_pkt_dw1;

sys/dev/pci/drm/amd/include/vi_structs.h

355

uint32_t iqtimer_pkt_dw2;

sys/dev/pci/drm/amd/include/vi_structs.h

356

uint32_t iqtimer_pkt_dw3;

sys/dev/pci/drm/amd/include/vi_structs.h

357

uint32_t iqtimer_pkt_dw4;

sys/dev/pci/drm/amd/include/vi_structs.h

358

uint32_t iqtimer_pkt_dw5;

sys/dev/pci/drm/amd/include/vi_structs.h

359

uint32_t iqtimer_pkt_dw6;

sys/dev/pci/drm/amd/include/vi_structs.h

36

uint32_t sdmax_rlcx_rb_rptr_addr_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

360

uint32_t iqtimer_pkt_dw7;

sys/dev/pci/drm/amd/include/vi_structs.h

361

uint32_t iqtimer_pkt_dw8;

sys/dev/pci/drm/amd/include/vi_structs.h

362

uint32_t iqtimer_pkt_dw9;

sys/dev/pci/drm/amd/include/vi_structs.h

363

uint32_t iqtimer_pkt_dw10;

sys/dev/pci/drm/amd/include/vi_structs.h

364

uint32_t iqtimer_pkt_dw11;

sys/dev/pci/drm/amd/include/vi_structs.h

365

uint32_t iqtimer_pkt_dw12;

sys/dev/pci/drm/amd/include/vi_structs.h

366

uint32_t iqtimer_pkt_dw13;

sys/dev/pci/drm/amd/include/vi_structs.h

367

uint32_t iqtimer_pkt_dw14;

sys/dev/pci/drm/amd/include/vi_structs.h

368

uint32_t iqtimer_pkt_dw15;

sys/dev/pci/drm/amd/include/vi_structs.h

369

uint32_t iqtimer_pkt_dw16;

sys/dev/pci/drm/amd/include/vi_structs.h

37

uint32_t sdmax_rlcx_rb_rptr_addr_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

370

uint32_t iqtimer_pkt_dw17;

sys/dev/pci/drm/amd/include/vi_structs.h

371

uint32_t iqtimer_pkt_dw18;

sys/dev/pci/drm/amd/include/vi_structs.h

372

uint32_t iqtimer_pkt_dw19;

sys/dev/pci/drm/amd/include/vi_structs.h

373

uint32_t iqtimer_pkt_dw20;

sys/dev/pci/drm/amd/include/vi_structs.h

374

uint32_t iqtimer_pkt_dw21;

sys/dev/pci/drm/amd/include/vi_structs.h

375

uint32_t iqtimer_pkt_dw22;

sys/dev/pci/drm/amd/include/vi_structs.h

376

uint32_t iqtimer_pkt_dw23;

sys/dev/pci/drm/amd/include/vi_structs.h

377

uint32_t iqtimer_pkt_dw24;

sys/dev/pci/drm/amd/include/vi_structs.h

378

uint32_t iqtimer_pkt_dw25;

sys/dev/pci/drm/amd/include/vi_structs.h

379

uint32_t iqtimer_pkt_dw26;

sys/dev/pci/drm/amd/include/vi_structs.h

38

uint32_t sdmax_rlcx_ib_cntl;

sys/dev/pci/drm/amd/include/vi_structs.h

380

uint32_t iqtimer_pkt_dw27;

sys/dev/pci/drm/amd/include/vi_structs.h

381

uint32_t iqtimer_pkt_dw28;

sys/dev/pci/drm/amd/include/vi_structs.h

382

uint32_t iqtimer_pkt_dw29;

sys/dev/pci/drm/amd/include/vi_structs.h

383

uint32_t iqtimer_pkt_dw30;

sys/dev/pci/drm/amd/include/vi_structs.h

384

uint32_t iqtimer_pkt_dw31;

sys/dev/pci/drm/amd/include/vi_structs.h

385

uint32_t reserved56;

sys/dev/pci/drm/amd/include/vi_structs.h

386

uint32_t reserved57;

sys/dev/pci/drm/amd/include/vi_structs.h

387

uint32_t reserved58;

sys/dev/pci/drm/amd/include/vi_structs.h

388

uint32_t set_resources_header;

sys/dev/pci/drm/amd/include/vi_structs.h

389

uint32_t set_resources_dw1;

sys/dev/pci/drm/amd/include/vi_structs.h

39

uint32_t sdmax_rlcx_ib_rptr;

sys/dev/pci/drm/amd/include/vi_structs.h

390

uint32_t set_resources_dw2;

sys/dev/pci/drm/amd/include/vi_structs.h

391

uint32_t set_resources_dw3;

sys/dev/pci/drm/amd/include/vi_structs.h

392

uint32_t set_resources_dw4;

sys/dev/pci/drm/amd/include/vi_structs.h

393

uint32_t set_resources_dw5;

sys/dev/pci/drm/amd/include/vi_structs.h

394

uint32_t set_resources_dw6;

sys/dev/pci/drm/amd/include/vi_structs.h

395

uint32_t set_resources_dw7;

sys/dev/pci/drm/amd/include/vi_structs.h

396

uint32_t reserved59;

sys/dev/pci/drm/amd/include/vi_structs.h

397

uint32_t reserved60;

sys/dev/pci/drm/amd/include/vi_structs.h

398

uint32_t reserved61;

sys/dev/pci/drm/amd/include/vi_structs.h

399

uint32_t reserved62;

sys/dev/pci/drm/amd/include/vi_structs.h

40

uint32_t sdmax_rlcx_ib_offset;

sys/dev/pci/drm/amd/include/vi_structs.h

400

uint32_t queue_doorbell_id0;

sys/dev/pci/drm/amd/include/vi_structs.h

401

uint32_t queue_doorbell_id1;

sys/dev/pci/drm/amd/include/vi_structs.h

402

uint32_t queue_doorbell_id2;

sys/dev/pci/drm/amd/include/vi_structs.h

403

uint32_t queue_doorbell_id3;

sys/dev/pci/drm/amd/include/vi_structs.h

404

uint32_t queue_doorbell_id4;

sys/dev/pci/drm/amd/include/vi_structs.h

405

uint32_t queue_doorbell_id5;

sys/dev/pci/drm/amd/include/vi_structs.h

406

uint32_t queue_doorbell_id6;

sys/dev/pci/drm/amd/include/vi_structs.h

407

uint32_t queue_doorbell_id7;

sys/dev/pci/drm/amd/include/vi_structs.h

408

uint32_t queue_doorbell_id8;

sys/dev/pci/drm/amd/include/vi_structs.h

409

uint32_t queue_doorbell_id9;

sys/dev/pci/drm/amd/include/vi_structs.h

41

uint32_t sdmax_rlcx_ib_base_lo;

sys/dev/pci/drm/amd/include/vi_structs.h

410

uint32_t queue_doorbell_id10;

sys/dev/pci/drm/amd/include/vi_structs.h

411

uint32_t queue_doorbell_id11;

sys/dev/pci/drm/amd/include/vi_structs.h

412

uint32_t queue_doorbell_id12;

sys/dev/pci/drm/amd/include/vi_structs.h

413

uint32_t queue_doorbell_id13;

sys/dev/pci/drm/amd/include/vi_structs.h

414

uint32_t queue_doorbell_id14;

sys/dev/pci/drm/amd/include/vi_structs.h

415

uint32_t queue_doorbell_id15;

sys/dev/pci/drm/amd/include/vi_structs.h

416

uint32_t reserved_t[256];

sys/dev/pci/drm/amd/include/vi_structs.h

42

uint32_t sdmax_rlcx_ib_base_hi;

sys/dev/pci/drm/amd/include/vi_structs.h

421

uint32_t wptr_poll_mem;

sys/dev/pci/drm/amd/include/vi_structs.h

422

uint32_t rptr_report_mem;

sys/dev/pci/drm/amd/include/vi_structs.h

423

uint32_t dynamic_cu_mask;

sys/dev/pci/drm/amd/include/vi_structs.h

424

uint32_t dynamic_rb_mask;

sys/dev/pci/drm/amd/include/vi_structs.h

428

uint32_t ce_ib_completion_status;

sys/dev/pci/drm/amd/include/vi_structs.h

429

uint32_t ce_constegnine_count;

sys/dev/pci/drm/amd/include/vi_structs.h

43

uint32_t sdmax_rlcx_ib_size;

sys/dev/pci/drm/amd/include/vi_structs.h

430

uint32_t ce_ibOffset_ib1;

sys/dev/pci/drm/amd/include/vi_structs.h

431

uint32_t ce_ibOffset_ib2;

sys/dev/pci/drm/amd/include/vi_structs.h

435

uint32_t ib_completion_status;

sys/dev/pci/drm/amd/include/vi_structs.h

436

uint32_t de_constEngine_count;

sys/dev/pci/drm/amd/include/vi_structs.h

437

uint32_t ib_offset_ib1;

sys/dev/pci/drm/amd/include/vi_structs.h

438

uint32_t ib_offset_ib2;

sys/dev/pci/drm/amd/include/vi_structs.h

439

uint32_t preamble_begin_ib1;

sys/dev/pci/drm/amd/include/vi_structs.h

44

uint32_t sdmax_rlcx_skip_cntl;

sys/dev/pci/drm/amd/include/vi_structs.h

440

uint32_t preamble_begin_ib2;

sys/dev/pci/drm/amd/include/vi_structs.h

441

uint32_t preamble_end_ib1;

sys/dev/pci/drm/amd/include/vi_structs.h

442

uint32_t preamble_end_ib2;

sys/dev/pci/drm/amd/include/vi_structs.h

443

uint32_t draw_indirect_baseLo;

sys/dev/pci/drm/amd/include/vi_structs.h

444

uint32_t draw_indirect_baseHi;

sys/dev/pci/drm/amd/include/vi_structs.h

445

uint32_t disp_indirect_baseLo;

sys/dev/pci/drm/amd/include/vi_structs.h

446

uint32_t disp_indirect_baseHi;

sys/dev/pci/drm/amd/include/vi_structs.h

447

uint32_t gds_backup_addrlo;

sys/dev/pci/drm/amd/include/vi_structs.h

448

uint32_t gds_backup_addrhi;

sys/dev/pci/drm/amd/include/vi_structs.h

449

uint32_t index_base_addrlo;

sys/dev/pci/drm/amd/include/vi_structs.h

45

uint32_t sdmax_rlcx_context_status;

sys/dev/pci/drm/amd/include/vi_structs.h

450

uint32_t index_base_addrhi;

sys/dev/pci/drm/amd/include/vi_structs.h

451

uint32_t sample_cntl;

sys/dev/pci/drm/amd/include/vi_structs.h

456

uint32_t ce_ib_completion_status;

sys/dev/pci/drm/amd/include/vi_structs.h

457

uint32_t ce_constegnine_count;

sys/dev/pci/drm/amd/include/vi_structs.h

458

uint32_t ce_ibOffset_ib1;

sys/dev/pci/drm/amd/include/vi_structs.h

459

uint32_t ce_ibOffset_ib2;

sys/dev/pci/drm/amd/include/vi_structs.h

46

uint32_t sdmax_rlcx_doorbell;

sys/dev/pci/drm/amd/include/vi_structs.h

462

uint32_t ce_chainib_addrlo_ib1;

sys/dev/pci/drm/amd/include/vi_structs.h

463

uint32_t ce_chainib_addrlo_ib2;

sys/dev/pci/drm/amd/include/vi_structs.h

464

uint32_t ce_chainib_addrhi_ib1;

sys/dev/pci/drm/amd/include/vi_structs.h

465

uint32_t ce_chainib_addrhi_ib2;

sys/dev/pci/drm/amd/include/vi_structs.h

466

uint32_t ce_chainib_size_ib1;

sys/dev/pci/drm/amd/include/vi_structs.h

467

uint32_t ce_chainib_size_ib2;

sys/dev/pci/drm/amd/include/vi_structs.h

47

uint32_t sdmax_rlcx_virtual_addr;

sys/dev/pci/drm/amd/include/vi_structs.h

472

uint32_t ib_completion_status;

sys/dev/pci/drm/amd/include/vi_structs.h

473

uint32_t de_constEngine_count;

sys/dev/pci/drm/amd/include/vi_structs.h

474

uint32_t ib_offset_ib1;

sys/dev/pci/drm/amd/include/vi_structs.h

475

uint32_t ib_offset_ib2;

sys/dev/pci/drm/amd/include/vi_structs.h

478

uint32_t chain_ib_addrlo_ib1;

sys/dev/pci/drm/amd/include/vi_structs.h

479

uint32_t chain_ib_addrlo_ib2;

sys/dev/pci/drm/amd/include/vi_structs.h

48

uint32_t sdmax_rlcx_ape1_cntl;

sys/dev/pci/drm/amd/include/vi_structs.h

480

uint32_t chain_ib_addrhi_ib1;

sys/dev/pci/drm/amd/include/vi_structs.h

481

uint32_t chain_ib_addrhi_ib2;

sys/dev/pci/drm/amd/include/vi_structs.h

482

uint32_t chain_ib_size_ib1;

sys/dev/pci/drm/amd/include/vi_structs.h

483

uint32_t chain_ib_size_ib2;

sys/dev/pci/drm/amd/include/vi_structs.h

486

uint32_t preamble_begin_ib1;

sys/dev/pci/drm/amd/include/vi_structs.h

487

uint32_t preamble_begin_ib2;

sys/dev/pci/drm/amd/include/vi_structs.h

488

uint32_t preamble_end_ib1;

sys/dev/pci/drm/amd/include/vi_structs.h

489

uint32_t preamble_end_ib2;

sys/dev/pci/drm/amd/include/vi_structs.h

49

uint32_t sdmax_rlcx_doorbell_log;

sys/dev/pci/drm/amd/include/vi_structs.h

492

uint32_t chain_ib_pream_addrlo_ib1;

sys/dev/pci/drm/amd/include/vi_structs.h

493

uint32_t chain_ib_pream_addrlo_ib2;

sys/dev/pci/drm/amd/include/vi_structs.h

494

uint32_t chain_ib_pream_addrhi_ib1;

sys/dev/pci/drm/amd/include/vi_structs.h

495

uint32_t chain_ib_pream_addrhi_ib2;

sys/dev/pci/drm/amd/include/vi_structs.h

498

uint32_t draw_indirect_baseLo;

sys/dev/pci/drm/amd/include/vi_structs.h

499

uint32_t draw_indirect_baseHi;

sys/dev/pci/drm/amd/include/vi_structs.h

50

uint32_t reserved_22;

sys/dev/pci/drm/amd/include/vi_structs.h

500

uint32_t disp_indirect_baseLo;

sys/dev/pci/drm/amd/include/vi_structs.h

501

uint32_t disp_indirect_baseHi;

sys/dev/pci/drm/amd/include/vi_structs.h

502

uint32_t gds_backup_addrlo;

sys/dev/pci/drm/amd/include/vi_structs.h

503

uint32_t gds_backup_addrhi;

sys/dev/pci/drm/amd/include/vi_structs.h

504

uint32_t index_base_addrlo;

sys/dev/pci/drm/amd/include/vi_structs.h

505

uint32_t index_base_addrhi;

sys/dev/pci/drm/amd/include/vi_structs.h

506

uint32_t sample_cntl;

sys/dev/pci/drm/amd/include/vi_structs.h

51

uint32_t reserved_23;

sys/dev/pci/drm/amd/include/vi_structs.h

512

uint32_t reserved1[60];

sys/dev/pci/drm/amd/include/vi_structs.h

516

uint32_t DeIbBaseAddrLo;

sys/dev/pci/drm/amd/include/vi_structs.h

517

uint32_t DeIbBaseAddrHi;

sys/dev/pci/drm/amd/include/vi_structs.h

518

uint32_t reserved2[941];

sys/dev/pci/drm/amd/include/vi_structs.h

52

uint32_t reserved_24;

sys/dev/pci/drm/amd/include/vi_structs.h

524

uint32_t reserved1[54];

sys/dev/pci/drm/amd/include/vi_structs.h

528

uint32_t DeIbBaseAddrLo;

sys/dev/pci/drm/amd/include/vi_structs.h

529

uint32_t DeIbBaseAddrHi;

sys/dev/pci/drm/amd/include/vi_structs.h

53

uint32_t reserved_25;

sys/dev/pci/drm/amd/include/vi_structs.h

530

uint32_t reserved2[931];

sys/dev/pci/drm/amd/include/vi_structs.h

54

uint32_t reserved_26;

sys/dev/pci/drm/amd/include/vi_structs.h

55

uint32_t reserved_27;

sys/dev/pci/drm/amd/include/vi_structs.h

56

uint32_t reserved_28;

sys/dev/pci/drm/amd/include/vi_structs.h

57

uint32_t reserved_29;

sys/dev/pci/drm/amd/include/vi_structs.h

58

uint32_t reserved_30;

sys/dev/pci/drm/amd/include/vi_structs.h

59

uint32_t reserved_31;

sys/dev/pci/drm/amd/include/vi_structs.h

60

uint32_t reserved_32;

sys/dev/pci/drm/amd/include/vi_structs.h

61

uint32_t reserved_33;

sys/dev/pci/drm/amd/include/vi_structs.h

62

uint32_t reserved_34;

sys/dev/pci/drm/amd/include/vi_structs.h

63

uint32_t reserved_35;

sys/dev/pci/drm/amd/include/vi_structs.h

64

uint32_t reserved_36;

sys/dev/pci/drm/amd/include/vi_structs.h

65

uint32_t reserved_37;

sys/dev/pci/drm/amd/include/vi_structs.h

66

uint32_t reserved_38;

sys/dev/pci/drm/amd/include/vi_structs.h

67

uint32_t reserved_39;

sys/dev/pci/drm/amd/include/vi_structs.h

68

uint32_t reserved_40;

sys/dev/pci/drm/amd/include/vi_structs.h

69

uint32_t reserved_41;

sys/dev/pci/drm/amd/include/vi_structs.h

70

uint32_t reserved_42;

sys/dev/pci/drm/amd/include/vi_structs.h

71

uint32_t reserved_43;

sys/dev/pci/drm/amd/include/vi_structs.h

72

uint32_t reserved_44;

sys/dev/pci/drm/amd/include/vi_structs.h

73

uint32_t reserved_45;

sys/dev/pci/drm/amd/include/vi_structs.h

74

uint32_t reserved_46;

sys/dev/pci/drm/amd/include/vi_structs.h

75

uint32_t reserved_47;

sys/dev/pci/drm/amd/include/vi_structs.h

76

uint32_t reserved_48;

sys/dev/pci/drm/amd/include/vi_structs.h

77

uint32_t reserved_49;

sys/dev/pci/drm/amd/include/vi_structs.h

78

uint32_t reserved_50;

sys/dev/pci/drm/amd/include/vi_structs.h

79

uint32_t reserved_51;

sys/dev/pci/drm/amd/include/vi_structs.h

80

uint32_t reserved_52;

sys/dev/pci/drm/amd/include/vi_structs.h

81

uint32_t reserved_53;

sys/dev/pci/drm/amd/include/vi_structs.h

82

uint32_t reserved_54;

sys/dev/pci/drm/amd/include/vi_structs.h

83

uint32_t reserved_55;

sys/dev/pci/drm/amd/include/vi_structs.h

84

uint32_t reserved_56;

sys/dev/pci/drm/amd/include/vi_structs.h

85

uint32_t reserved_57;

sys/dev/pci/drm/amd/include/vi_structs.h

86

uint32_t reserved_58;

sys/dev/pci/drm/amd/include/vi_structs.h

87

uint32_t reserved_59;

sys/dev/pci/drm/amd/include/vi_structs.h

88

uint32_t reserved_60;

sys/dev/pci/drm/amd/include/vi_structs.h

89

uint32_t reserved_61;

sys/dev/pci/drm/amd/include/vi_structs.h

90

uint32_t reserved_62;

sys/dev/pci/drm/amd/include/vi_structs.h

91

uint32_t reserved_63;

sys/dev/pci/drm/amd/include/vi_structs.h

92

uint32_t reserved_64;

sys/dev/pci/drm/amd/include/vi_structs.h

93

uint32_t reserved_65;

sys/dev/pci/drm/amd/include/vi_structs.h

94

uint32_t reserved_66;

sys/dev/pci/drm/amd/include/vi_structs.h

95

uint32_t reserved_67;

sys/dev/pci/drm/amd/include/vi_structs.h

96

uint32_t reserved_68;

sys/dev/pci/drm/amd/include/vi_structs.h

97

uint32_t reserved_69;

sys/dev/pci/drm/amd/include/vi_structs.h

98

uint32_t reserved_70;

sys/dev/pci/drm/amd/include/vi_structs.h

99

uint32_t reserved_71;

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1091

uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1203

uint32_t type,

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1205

uint32_t size)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1224

uint32_t type,

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1226

uint32_t size)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1319

uint32_t mask)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1351

int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1388

int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1428

long *input, uint32_t size)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1479

uint32_t *fan_mode)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1496

uint32_t speed)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1513

uint32_t *speed)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1530

uint32_t *speed)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1547

uint32_t speed)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1564

uint32_t mode)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1581

uint32_t *limit,

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1602

uint32_t limit)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1903

uint32_t count)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1920

uint32_t clock)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1937

uint32_t clock)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

1951

uint32_t clock)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

384

uint32_t pstate)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

400

uint32_t cstate)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

462

uint32_t msg_id)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

518

void *data, uint32_t *size)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

538

int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

552

int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

670

int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

708

int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

723

int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

74

uint32_t block_type,

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

776

int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

791

int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

823

uint32_t *min,

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

824

uint32_t *max)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

846

uint32_t min,

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

847

uint32_t max)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

939

int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)

sys/dev/pci/drm/amd/pm/amdgpu_dpm.c

997

uint32_t idx)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1021

static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1058

uint32_t mask = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1234

uint32_t value = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1267

amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1280

uint32_t value = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1313

amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1375

uint32_t parameter_size = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1379

uint32_t i = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1430

int r, size = sizeof(uint32_t);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1711

uint32_t mask,

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1785

uint32_t ss_power;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1896

uint32_t mask, enum amdgpu_device_attr_states *states)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1905

uint32_t mask, enum amdgpu_device_attr_states *states)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1907

uint32_t ss_power;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1922

uint32_t mask, enum amdgpu_device_attr_states *states)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1924

uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1949

uint32_t mask, enum amdgpu_device_attr_states *states)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1952

uint32_t gc_ver;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1981

uint32_t mask, enum amdgpu_device_attr_states *states)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1985

uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

1986

uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2557

uint32_t mask, enum amdgpu_device_attr_states *states)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2561

uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2663

uint32_t mask, struct list_head *attr_list)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2672

uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2722

uint32_t counts,

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2723

uint32_t mask,

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

2727

uint32_t i = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3313

uint32_t limit;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3370

uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3416

uint32_t sclk;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3440

uint32_t mclk;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3651

uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3652

uint32_t tmp;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3877

uint32_t *num_of_params)

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3880

uint32_t parameter_size = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

3935

uint32_t parameter_size = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

418

uint32_t i;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4673

uint32_t mask = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4674

uint32_t tmp;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4793

uint32_t size;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4795

uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4814

uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4815

uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4816

uint32_t value;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4818

uint32_t query = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4839

size = sizeof(uint32_t);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

4846

size = sizeof(uint32_t);

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

757

uint32_t parameter_size = 0;

sys/dev/pci/drm/amd/pm/amdgpu_pm.c

763

uint32_t type;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

354

uint32_t fw_version;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

355

uint32_t pcie_gen_mask;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

356

uint32_t pcie_mlw_mask;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

358

uint32_t smu_prv_buffer_size;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

362

uint32_t pp_feature;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

375

uint32_t smu_debug_mask;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

387

uint32_t od_feature_mask;

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

391

void *data, uint32_t *size);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

393

int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

394

int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

397

uint32_t block_type, bool gate, int inst);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

404

uint32_t pstate);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

434

uint32_t cstate);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

439

uint32_t msg_id);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

452

int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

454

int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

455

int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

459

uint32_t *min,

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

460

uint32_t *max);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

463

uint32_t min,

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

464

uint32_t max);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

471

int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

478

uint32_t idx);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

492

uint32_t type,

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

494

uint32_t size);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

496

uint32_t type,

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

498

uint32_t size);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

511

uint32_t mask);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

513

int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

515

int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

519

long *input, uint32_t size);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

538

uint32_t *fan_mode);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

540

uint32_t speed);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

542

uint32_t *speed);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

544

uint32_t *speed);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

546

uint32_t speed);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

548

uint32_t mode);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

550

uint32_t *limit,

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

554

uint32_t limit);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

589

uint32_t count);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

591

uint32_t clock);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

593

uint32_t clock);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

595

uint32_t clock);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

609

int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask);

sys/dev/pci/drm/amd/pm/inc/amdgpu_dpm.h

611

int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask);

sys/dev/pci/drm/amd/pm/inc/amdgpu_pm.h

89

uint32_t mask, enum amdgpu_device_attr_states *states);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3264

uint32_t sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3279

*((uint32_t *)value) = sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3285

*((uint32_t *)value) = kv_dpm_get_temp(adev);

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

3294

uint32_t block_type,

sys/dev/pci/drm/amd/pm/legacy-dpm/ppsmc.h

176

#define PPSMC_MSG_DPM_Config ((uint32_t) 0x102)

sys/dev/pci/drm/amd/pm/legacy-dpm/ppsmc.h

177

#define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104)

sys/dev/pci/drm/amd/pm/legacy-dpm/ppsmc.h

178

#define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108)

sys/dev/pci/drm/amd/pm/legacy-dpm/ppsmc.h

179

#define PPSMC_MSG_Voltage_Cntl_Enable ((uint32_t) 0x109)

sys/dev/pci/drm/amd/pm/legacy-dpm/ppsmc.h

180

#define PPSMC_MSG_Thermal_Cntl_Enable ((uint32_t) 0x10a)

sys/dev/pci/drm/amd/pm/legacy-dpm/ppsmc.h

181

#define PPSMC_MSG_VCEPowerOFF ((uint32_t) 0x10e)

sys/dev/pci/drm/amd/pm/legacy-dpm/ppsmc.h

182

#define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f)

sys/dev/pci/drm/amd/pm/legacy-dpm/ppsmc.h

183

#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112)

sys/dev/pci/drm/amd/pm/legacy-dpm/ppsmc.h

184

#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d)

sys/dev/pci/drm/amd/pm/legacy-dpm/ppsmc.h

185

#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e)

sys/dev/pci/drm/amd/pm/legacy-dpm/ppsmc.h

186

#define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120)

sys/dev/pci/drm/amd/pm/legacy-dpm/ppsmc.h

187

#define PPSMC_MSG_DisableBAPM ((uint32_t) 0x121)

sys/dev/pci/drm/amd/pm/legacy-dpm/ppsmc.h

188

#define PPSMC_MSG_UVD_DPM_Config ((uint32_t) 0x124)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

8068

uint32_t sclk, mclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

8081

*((uint32_t *)value) = sclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

8089

*((uint32_t *)value) = mclk;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

8095

*((uint32_t *)value) = si_dpm_get_temp(adev);

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

284

uint32_t value[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

301

uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

367

uint32_t vCG_SPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

368

uint32_t vCG_SPLL_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

369

uint32_t vCG_SPLL_FUNC_CNTL_3;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

370

uint32_t vCG_SPLL_SPREAD_SPECTRUM;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

371

uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

372

uint32_t sclk_value;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

379

uint32_t vMPLL_AD_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

380

uint32_t vMPLL_AD_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

381

uint32_t vMPLL_DQ_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

382

uint32_t vMPLL_DQ_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

383

uint32_t vMCLK_PWRMGT_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

384

uint32_t vDLL_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

385

uint32_t vMPLL_SS;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

386

uint32_t vMPLL_SS2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

387

uint32_t mclk_value;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

395

uint32_t vMCLK_PWRMGT_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

396

uint32_t vDLL_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

397

uint32_t vMPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

398

uint32_t vMPLL_FUNC_CNTL2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

399

uint32_t vMPLL_FUNC_CNTL3;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

400

uint32_t vMPLL_SS;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

401

uint32_t vMPLL_SS2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

402

uint32_t mclk_value;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

437

uint32_t aT;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

438

uint32_t bSP;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

466

uint32_t lowMask[RV770_SMC_VOLTAGEMASK_MAX];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

478

uint32_t lowSMIO[MAX_NO_VREG_STEPS];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

707

uint32_t TDPLimit;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

708

uint32_t NearTDPLimit;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

709

uint32_t SafePowerLimit;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

710

uint32_t PowerBoostLimit;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

716

uint32_t vCG_SPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

717

uint32_t vCG_SPLL_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

718

uint32_t vCG_SPLL_FUNC_CNTL_3;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

719

uint32_t vCG_SPLL_FUNC_CNTL_4;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

720

uint32_t vCG_SPLL_SPREAD_SPECTRUM;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

721

uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

722

uint32_t sclk_value;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

729

uint32_t vMPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

730

uint32_t vMPLL_FUNC_CNTL_1;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

731

uint32_t vMPLL_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

732

uint32_t vMPLL_AD_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

733

uint32_t vMPLL_AD_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

734

uint32_t vMPLL_DQ_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

735

uint32_t vMPLL_DQ_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

736

uint32_t vMCLK_PWRMGT_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

737

uint32_t vDLL_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

738

uint32_t vMPLL_SS;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

739

uint32_t vMPLL_SS2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

740

uint32_t mclk_value;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

764

uint32_t aT;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

765

uint32_t bSP;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

772

uint32_t powergate_en;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

777

uint32_t SQPowerThrottle;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

778

uint32_t SQPowerThrottle_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

779

uint32_t reserved[2];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

799

uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX];

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h

813

uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS];

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

100

uint32_t vCG_SPLL_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

101

uint32_t vCG_SPLL_FUNC_CNTL_3;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

102

uint32_t vCG_SPLL_FUNC_CNTL_4;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

103

uint32_t vCG_SPLL_SPREAD_SPECTRUM;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

104

uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

105

uint32_t sclk_value;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

111

uint32_t vMPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

112

uint32_t vMPLL_FUNC_CNTL_1;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

113

uint32_t vMPLL_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

114

uint32_t vMPLL_AD_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

115

uint32_t vMPLL_DQ_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

116

uint32_t vMCLK_PWRMGT_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

117

uint32_t vDLL_CNTL;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

118

uint32_t vMPLL_SS;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

119

uint32_t vMPLL_SS2;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

120

uint32_t mclk_value;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

142

uint32_t aT;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

143

uint32_t bSP;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

154

uint32_t SQPowerThrottle;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

155

uint32_t SQPowerThrottle_2;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

156

uint32_t MaxPoweredUpCU;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

159

uint32_t reserved[2];

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

199

uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX];

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

211

uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS];

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

261

uint32_t refresh_period;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

277

uint32_t lkge_lut_V0;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

278

uint32_t lkge_lut_Vstep;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

279

uint32_t WinTime;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

280

uint32_t R_LL;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

281

uint32_t calculation_repeats;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

282

uint32_t l2numWin_TDP;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

283

uint32_t dc_cac;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

288

uint32_t lkge_lut_T0;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

289

uint32_t lkge_lut_Tstep;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

305

uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

320

uint32_t mc_arb_dram_timing;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

321

uint32_t mc_arb_dram_timing2;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

338

uint32_t freq[256];

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

339

uint32_t ss[256];

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

358

uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

359

uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

360

uint32_t K;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

361

uint32_t T0;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

362

uint32_t MaxT;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

368

uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

369

uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

370

uint32_t Tthreshold;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

50

uint32_t dpm2Flags;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

63

uint32_t SwitchDownCounter;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

64

uint32_t SysScalingFactor;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

70

uint32_t TDPLimit;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

71

uint32_t NearTDPLimit;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

72

uint32_t SafePowerLimit;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

73

uint32_t PowerBoostLimit;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

74

uint32_t MinLimitDelta;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

79

uint32_t EstimatedDGPU_T;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

80

uint32_t EstimatedDGPU_P;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

81

uint32_t EstimatedAPU_T;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

82

uint32_t EstimatedAPU_P;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

89

uint32_t NearTDPLimitTherm;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

90

uint32_t NearTDPLimitPAPM;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

91

uint32_t PlatformPowerLimit;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

92

uint32_t dGPU_T_Limit;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

93

uint32_t dGPU_T_Warning;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

94

uint32_t dGPU_T_Hysteresis;

sys/dev/pci/drm/amd/pm/legacy-dpm/sislands_smc.h

99

uint32_t vCG_SPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

106

uint32_t gpu_temperature, size = sizeof(gpu_temperature);

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1235

uint32_t block_type,

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1305

static int pp_set_min_deep_sleep_dcefclk(void *handle, uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1322

static int pp_set_hard_min_dcefclk_by_freq(void *handle, uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1339

static int pp_set_hard_min_fclk_by_freq(void *handle, uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1356

static int pp_set_active_display_count(void *handle, uint32_t count)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1486

static int pp_set_xgmi_pstate(void *handle, uint32_t pstate)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

1514

static int pp_gfx_state_change_set(void *handle, uint32_t state)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

331

static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

349

uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

399

static uint32_t pp_dpm_get_sclk(void *handle, bool low)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

413

static uint32_t pp_dpm_get_mclk(void *handle, bool low)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

498

static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

516

static int pp_dpm_get_fan_control_mode(void *handle, uint32_t *fan_mode)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

533

static int pp_dpm_set_fan_speed_pwm(void *handle, uint32_t speed)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

549

static int pp_dpm_get_fan_speed_pwm(void *handle, uint32_t *speed)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

565

static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

581

static int pp_dpm_set_fan_speed_rpm(void *handle, uint32_t rpm)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

691

enum pp_clock_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

756

static int pp_dpm_set_sclk_od(void *handle, uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

785

static int pp_dpm_set_mclk_od(void *handle, uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

809

*((uint32_t *)value) = hwmgr->pstate_sclk * 100;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

812

*((uint32_t *)value) = hwmgr->pstate_mclk * 100;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

815

*((uint32_t *)value) = hwmgr->pstate_sclk_peak * 100;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

818

*((uint32_t *)value) = hwmgr->pstate_mclk_peak * 100;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

821

*((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

824

*((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMaxRPM;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

856

static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

871

static int pp_set_fine_grain_clk_vol(void *handle, uint32_t type, long *input, uint32_t size)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

885

long *input, uint32_t size)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

921

uint32_t index;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

958

static int pp_set_power_limit(void *handle, uint32_t limit)

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

961

uint32_t max_power_limit;

sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c

988

static int pp_get_power_limit(void *handle, uint32_t *limit,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

38

uint32_t reg_offset;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

39

uint32_t mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

40

uint32_t shift;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

41

uint32_t timeout;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

42

uint32_t val;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

47

uint32_t hwip;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

48

uint32_t inst;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

49

uint32_t seg;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

50

uint32_t reg_offset;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

51

uint32_t mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

52

uint32_t shift;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

53

uint32_t timeout;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.h

54

uint32_t val;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c

353

PHM_PerformanceLevelDesignation designation, uint32_t index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c

502

int phm_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

100

uint32_t pcie_sclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

105

uint32_t count; /* Number of entries. */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

32

uint32_t clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

44

uint32_t sclk_offset;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

50

uint32_t count; /* Number of entries. */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

59

uint32_t dclk; /* UVD D-clock */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

60

uint32_t vclk; /* UVD V-clock */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

61

uint32_t eclk; /* VCE clock */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

62

uint32_t aclk; /* ACP clock */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

63

uint32_t samclock; /* SAMU clock */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

73

uint32_t count; /* Number of entries. */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h

88

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pp_overdriver.c

1269

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pp_overdriver.h

32

uint32_t VFT2_m1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pp_overdriver.h

33

uint32_t VFT2_m2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pp_overdriver.h

34

uint32_t VFT2_b;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pp_overdriver.h

35

uint32_t VFT1_m1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pp_overdriver.h

36

uint32_t VFT1_m2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pp_overdriver.h

37

uint32_t VFT1_b;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pp_overdriver.h

38

uint32_t VFT0_m1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pp_overdriver.h

39

uint32_t VFT0_m2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pp_overdriver.h

40

uint32_t VFT0_b;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pp_psm.c

274

uint32_t index;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

1112

(uint32_t *)voltage_parameters, sizeof(*voltage_parameters));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

1181

void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

1182

uint32_t *min_vddc)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

1249

uint32_t length, i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

219

uint32_t engine_clock,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

220

uint32_t memory_clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

237

(uint32_t *)&engine_clock_parameters, sizeof(engine_clock_parameters));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

295

uint32_t clock_value,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

308

(uint32_t *)&mpll_parameters, sizeof(mpll_parameters));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

316

(uint32_t)mpll_parameters.ucPostDiv;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

318

(uint32_t)(mpll_parameters.ucPllCntlFlag &

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

321

(uint32_t)((mpll_parameters.ucPllCntlFlag &

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

324

(uint32_t)((mpll_parameters.ucPllCntlFlag &

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

327

(uint32_t)((mpll_parameters.ucPllCntlFlag &

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

330

(uint32_t)(mpll_parameters.ucDllSpeed);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

332

(uint32_t)(mpll_parameters.ucBWCntl);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

346

uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

356

(uint32_t *)&mpll_parameters, sizeof(mpll_parameters));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

360

(uint32_t)mpll_parameters.ulClock.ucPostDiv;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

366

uint32_t clock_value,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

377

(uint32_t *)&mpll_parameters, sizeof(mpll_parameters));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

396

uint32_t clock_value,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

407

(uint32_t *)&pll_parameters, sizeof(pll_parameters));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

419

uint32_t clock_value,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

431

(uint32_t *)&pll_patameters, sizeof(pll_patameters));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

456

uint32_t clock_value,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

468

(uint32_t *)&pll_patameters, sizeof(pll_patameters));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

488

uint32_t clock_value,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

501

(uint32_t *)&pll_patameters, sizeof(pll_patameters));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

51

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

528

uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

533

uint32_t clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

543

clock = (uint32_t)(le16_to_cpu(fw_info->usReferenceClock));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

58

while (*(uint32_t *)reg_data != END_OF_REG_DATA_BLOCK &&

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

60

tmem_id = (uint8_t)((*(uint32_t *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

618

const uint32_t pinId,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

64

(uint32_t)((*(uint32_t *)reg_data & CLOCK_RANGE_MASK) >>

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

671

const uint32_t pinId,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

700

uint32_t sclk, uint16_t virtual_voltage_Id,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

71

(uint32_t)*((uint32_t *)reg_data + j);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

718

(uint32_t *)&get_voltage_info_param_space, sizeof(get_voltage_info_param_space));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

763

(uint32_t *)&get_voltage_info_param_space, sizeof(get_voltage_info_param_space));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

777

uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

780

uint32_t clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

796

clock = (uint32_t)(le16_to_cpu(fwInfo_2_1->usMemoryReferenceClock));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

800

clock = (uint32_t)(le16_to_cpu(fwInfo_0_0->usReferenceClock));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

840

const uint32_t clockSpeed,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

859

((uint32_t)clockSpeed <= le32_to_cpu(ssInfo->ulTargetClockRange))) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

87

PP_ASSERT_WITH_CODE((*(uint32_t *)reg_data == END_OF_REG_DATA_BLOCK),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

903

const uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

915

const uint32_t engine_clock,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

923

uint16_t end_index, uint32_t *efuse)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

926

uint32_t mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

943

(uint32_t *)&efuse_param, sizeof(efuse_param));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

949

int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

964

(uint32_t *)&memory_clock_parameters, sizeof(memory_clock_parameters));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

970

uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

983

(uint32_t *)&get_voltage_info_param_space, sizeof(get_voltage_info_param_space));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

114

uint32_t cl_kf : 12;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

115

uint32_t clk_frac : 12;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

116

uint32_t un_used : 8;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

118

uint32_t ul_fb_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

130

uint32_t mpll_post_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

131

uint32_t bw_ctrl;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

132

uint32_t dll_speed;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

133

uint32_t vco_mode;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

134

uint32_t yclk_sel;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

135

uint32_t qdr;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

136

uint32_t half_rate;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

141

uint32_t ulClock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

142

uint32_t ulPostDiv;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

149

uint32_t speed_spectrum_percentage; /* in 1/100 percentage */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

150

uint32_t speed_spectrum_rate; /* in KHz */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

164

uint32_t ul_bootup_uma_clock; /* in 10kHz unit */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

171

uint32_t ul_csr_m3_srb_cntl[NUMBER_OF_M3ARB_PARAM_SETS][NUMBER_OF_M3ARB_PARAMS];/* arrays with values for CSR M3 arbiter for default */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

187

uint32_t mclk[MAX_AC_TIMING_ENTRIES];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

193

uint32_t smio_low;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

199

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

200

uint32_t mask_low;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

201

uint32_t phase_delay; /* Used for ATOM_GPIO_VOLTAGE_OBJECT_V3 and later */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

211

uint32_t mclk_max;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

212

uint32_t mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

253

uint32_t ulAVFS_meanNsigma_Acontant0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

254

uint32_t ulAVFS_meanNsigma_Acontant1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

255

uint32_t ulAVFS_meanNsigma_Acontant2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

259

uint32_t ulGB_VDROOP_TABLE_CKSOFF_a0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

260

uint32_t ulGB_VDROOP_TABLE_CKSOFF_a1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

261

uint32_t ulGB_VDROOP_TABLE_CKSOFF_a2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

262

uint32_t ulGB_VDROOP_TABLE_CKSON_a0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

263

uint32_t ulGB_VDROOP_TABLE_CKSON_a1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

264

uint32_t ulGB_VDROOP_TABLE_CKSON_a2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

265

uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_m1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

267

uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_b;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

268

uint32_t ulAVFSGB_FUSE_TABLE_CKSON_m1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

270

uint32_t ulAVFSGB_FUSE_TABLE_CKSON_b;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

293

extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

294

extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

296

extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

299

extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

300

extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

303

extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

304

extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

305

extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

306

extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

307

extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

311

uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

313

uint32_t clock_value, pp_atomctrl_memory_clock_param_ai *mpll_param);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

315

uint32_t clock_value,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

318

uint16_t end_index, uint32_t *efuse);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

319

extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

320

extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

323

uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

338

extern void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

339

uint32_t *min_vddc);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

39

uint32_t pll_post_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

40

uint32_t pll_feedback_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

41

uint32_t pll_ref_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

49

uint32_t ul_fb_div_frac : 14;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

50

uint32_t ul_fb_div : 12;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

51

uint32_t un_used : 6;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

53

uint32_t ul_fb_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

59

uint32_t pll_post_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

61

uint32_t pll_ref_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

64

uint32_t vco_mode;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

70

uint32_t pll_post_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

71

uint32_t real_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

76

uint32_t pll_post_divider; /* post divider value */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

77

uint32_t real_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

86

uint32_t pll_post_divider; /* post divider value */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

87

uint32_t real_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

169

uint32_t clock_type, uint32_t clock_value,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

175

uint32_t idx;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

177

pll_parameters.gpuclock_10khz = (uint32_t)clock_value;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

183

adev->mode_info.atom_context, idx, (uint32_t *)&pll_parameters, sizeof(pll_parameters)))

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

415

uint32_t *frequency)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

420

uint32_t ix;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

430

adev->mode_info.atom_context, ix, (uint32_t *)&parameters, sizeof(parameters)))

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

443

uint32_t frequency = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

479

uint32_t frequency = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

100

uint32_t ulDispclk2GfxclkM1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

101

uint32_t ulDispclk2GfxclkM2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

102

uint32_t ulDispclk2GfxclkB;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

103

uint32_t ulDcefclk2GfxclkM1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

104

uint32_t ulDcefclk2GfxclkM2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

105

uint32_t ulDcefclk2GfxclkB;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

106

uint32_t ulPixelclk2GfxclkM1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

107

uint32_t ulPixelclk2GfxclkM2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

108

uint32_t ulPixelclk2GfxclkB;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

109

uint32_t ulPhyclk2GfxclkM1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

110

uint32_t ulPhyclk2GfxclkM2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

111

uint32_t ulPhyclk2GfxclkB;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

112

uint32_t ulAcgGbVdroopTableA0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

113

uint32_t ulAcgGbVdroopTableA1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

114

uint32_t ulAcgGbVdroopTableA2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

115

uint32_t ulAcgGbFuseTableM1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

116

uint32_t ulAcgGbFuseTableM2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

117

uint32_t ulAcgGbFuseTableB;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

118

uint32_t ucAcgEnableGbVdroopTable;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

119

uint32_t ucAcgEnableGbFuseTable;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

134

uint32_t ulRevision;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

135

uint32_t ulGfxClk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

136

uint32_t ulUClk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

137

uint32_t ulSocClk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

138

uint32_t ulDCEFClk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

139

uint32_t ulEClk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

140

uint32_t ulVClk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

141

uint32_t ulDClk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

142

uint32_t ulFClk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

218

uint32_t clock_type, uint32_t clock_value,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

237

uint32_t *frequency);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

40

uint32_t smio_low;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

44

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

45

uint32_t mask_low;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

46

uint32_t phase_delay;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

61

uint32_t ulClock; /* the actual clock */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

62

uint32_t ulDid; /* DFS divider */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

63

uint32_t ulPll_fb_mult; /* Feedback Multiplier: bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

64

uint32_t ulPll_ss_fbsmult; /* Spread FB Multiplier: bit 8:0 int, bit 31:16 frac */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

68

uint32_t ulReserve[2];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

72

uint32_t ulMaxVddc;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

73

uint32_t ulMinVddc;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

75

uint32_t ulMeanNsigmaAcontant0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

76

uint32_t ulMeanNsigmaAcontant1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

77

uint32_t ulMeanNsigmaAcontant2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

81

uint32_t ulGbVdroopTableCksoffA0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

82

uint32_t ulGbVdroopTableCksoffA1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

83

uint32_t ulGbVdroopTableCksoffA2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

84

uint32_t ulGbVdroopTableCksonA0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

85

uint32_t ulGbVdroopTableCksonA1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

86

uint32_t ulGbVdroopTableCksonA2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

88

uint32_t ulGbFuseTableCksoffM1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

89

uint32_t ulGbFuseTableCksoffM2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

90

uint32_t ulGbFuseTableCksoffB;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

92

uint32_t ulGbFuseTableCksonM1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

93

uint32_t ulGbFuseTableCksonM2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

94

uint32_t ulGbFuseTableCksonB;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pppcielanes.c

57

uint8_t encode_pcie_lane_width(uint32_t num_lanes)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pppcielanes.c

62

uint8_t decode_pcie_lane_width(uint32_t num_lanes)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pppcielanes.h

27

extern uint8_t encode_pcie_lane_width(uint32_t num_lanes);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/pppcielanes.h

28

extern uint8_t decode_pcie_lane_width(uint32_t num_lanes);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1254

return (uint32_t)(state_arrays->ucNumEntries);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1260

static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1263

uint32_t result = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1304

static int ppt_get_vce_state_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t i,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1305

struct amd_vce_state *vce_state, void **clock_info, uint32_t *flag)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1367

uint32_t entry_index, struct pp_power_state *power_state,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1369

struct pp_power_state *, void *, uint32_t))

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

1376

uint32_t flags = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

157

uint32_t max_levels

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

160

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

250

uint32_t disable_ppm = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

251

uint32_t disable_power_control = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

317

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

329

table->count = (uint32_t)clk_volt_pp_table->count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

335

table->values[i] = (uint32_t)dep_record->clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

366

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

379

mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

406

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

423

sclk_table->count = (uint32_t)tonga_table->ucNumEntries;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

452

sclk_table->count = (uint32_t)polaris_table->ucNumEntries;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

481

uint32_t i, pcie_count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

505

if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

506

pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

542

if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

543

pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

55

static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

573

uint32_t table_size;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

576

table_size = sizeof(uint32_t) + sizeof(struct phm_cac_tdp_table);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

720

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

759

uint32_t table_size;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.h

30

extern int get_powerplay_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t entry_index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.h

32

struct pp_power_state *, void *, uint32_t));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

1688

vce_state->evclk = ((uint32_t)vce_clock_info->ucEVClkHigh << 16) | le16_to_cpu(vce_clock_info->usEVClkLow);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

1689

vce_state->ecclk = ((uint32_t)vce_clock_info->ucECClkHigh << 16) | le16_to_cpu(vce_clock_info->usECClkLow);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

848

uint32_t *vol_rep_time, uint32_t *bb_rep_time)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

855

*vol_rep_time = (uint32_t)le16_to_cpu(powerplay_tab->usVoltageTime);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

856

*bb_rep_time = (uint32_t)le16_to_cpu(powerplay_tab->usBackbiasTime);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.h

48

uint32_t *vol_rep_time, uint32_t *bb_rep_time);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1033

uint32_t i, now, size = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1034

uint32_t min_freq, max_freq = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1111

PHM_PerformanceLevelDesignation designation, uint32_t index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1154

static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1155

uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1170

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1227

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1284

uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1301

uint32_t sclk, mclk, activity_percent;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1321

*((uint32_t *)value) = sclk * 100;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1329

*((uint32_t *)value) = mclk * 100;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1333

*((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1336

*(uint32_t *)value = smu10_data->vcn_power_gated ? 0 : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1347

*((uint32_t *)value) = min(activity_percent, (u32)100);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1451

uint32_t i, size = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1494

static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1538

long *input, uint32_t size)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1540

uint32_t min_freq, max_freq = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1632

static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t state)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

204

static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

218

static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

232

static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

246

static int smu10_set_hard_min_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

260

static int smu10_set_soft_max_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

274

static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

337

uint32_t reg;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

471

uint32_t num_entry, const DpmClock_t *pclk_dependency_table)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

473

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

496

uint32_t result;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

56

uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

628

uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

629

uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

630

uint32_t index_fclk = data->clock_vol_info.vdd_dep_on_fclk->count - 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

631

uint32_t index_socclk = data->clock_vol_info.vdd_dep_on_socclk->count - 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

632

uint32_t fine_grain_min_freq = 0, fine_grain_max_freq = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

852

static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

868

static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

950

static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

973

enum pp_clock_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

978

uint32_t low, high;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

100

uint32_t vclk_high_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

101

uint32_t dclk_low_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

102

uint32_t dclk_high_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

108

uint32_t entry : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

109

uint32_t display : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

110

uint32_t driver: 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

111

uint32_t vce : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

112

uint32_t uvd : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

113

uint32_t acp : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

114

uint32_t reserved: 26;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

116

uint32_t u32All;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

129

uint32_t level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

131

uint32_t evclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

132

uint32_t ecclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

133

uint32_t samclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

134

uint32_t acpclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

137

uint32_t nbps_flags;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

138

uint32_t bapm_flags;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

178

uint32_t frequency;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

179

uint32_t latency;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

183

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

188

uint32_t clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

189

uint32_t vol;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

194

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

209

uint32_t disable_driver_thermal_policy;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

210

uint32_t thermal_auto_throttling_treshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

214

uint32_t ddi_power_gating_disabled;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

217

uint32_t dce_slow_sclk_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

221

uint32_t bapm_enabled;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

226

uint32_t is_nb_dpm_enabled;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

227

uint32_t is_voltage_island_enabled;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

228

uint32_t disable_smu_acp_s3_handshake;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

229

uint32_t disable_notify_smu_vpu_recovery;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

235

uint32_t power_containment_features;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

243

uint32_t sram_end;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

244

uint32_t dpm_table_start;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

245

uint32_t soft_regs_start;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

254

uint32_t fps_high_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

255

uint32_t fps_low_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

257

uint32_t dpm_flags;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

264

uint32_t max_sclk_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

265

uint32_t num_of_clk_entries;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

268

uint32_t separation_time;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

273

uint32_t ulTotalActiveCUs;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

277

uint32_t isp_actual_hard_min_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

278

uint32_t soc_actual_hard_min_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

279

uint32_t dcf_actual_hard_min_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

281

uint32_t f_actual_hard_min_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

282

uint32_t fabric_actual_soft_min_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

283

uint32_t vclk_soft_min;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

284

uint32_t dclk_soft_min;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

285

uint32_t gfx_actual_soft_min_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

286

uint32_t gfx_actual_soft_max_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

287

uint32_t gfx_min_freq_limit;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

288

uint32_t gfx_max_freq_limit; /* in 10Khz*/

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

299

uint32_t active_process_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

301

uint32_t deep_sleep_dcefclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

302

uint32_t num_active_display;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

69

uint32_t soft_min_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

70

uint32_t hard_min_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

71

uint32_t soft_max_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

72

uint32_t hard_max_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

76

uint32_t engine_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

97

uint32_t vclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

98

uint32_t dclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

99

uint32_t vclk_low_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_baco.c

39

uint32_t reg;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_baco.c

55

uint32_t reg;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c

170

const uint32_t *msg_id)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c

173

uint32_t value;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.h

34

const uint32_t *msg_id);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1011

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1167

uint32_t soft_register_value = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1168

uint32_t handshake_disables_offset = data->soft_regs_start

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1183

uint32_t soft_register_value = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1184

uint32_t handshake_disables_offset = data->soft_regs_start

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1377

static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

144

uint32_t DIDTEDCConfig_P12[] = {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1460

uint32_t *cac_config_regs,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1463

uint32_t data, i = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

174

enum pp_clock_type type, uint32_t mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

1989

uint32_t asicrev1, evv_revision, max = 0, min = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2052

uint32_t sclk = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

214

uint32_t speedCntl = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2149

uint32_t index;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2177

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2248

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

225

uint32_t link_width;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2352

uint32_t table_size, i, j;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2433

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2497

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2498

uint32_t hw_revision, sub_vendor_id, sub_sys_id;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2538

uint32_t temp_reg;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2630

uint32_t *voltage, struct smu7_leakage_voltage *leakage_table)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2632

uint32_t index;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2751

uint32_t vddc, vddci;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2770

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2771

uint32_t vddc;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2776

vddc = (uint32_t)(tab->entries[i].Vddc);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

291

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

2928

uint32_t efuse;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3033

uint32_t level, tmp;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3129

uint32_t level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3168

uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3170

uint32_t percentage;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

322

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3238

uint32_t sclk_mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3239

uint32_t mclk_mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3240

uint32_t pcie_mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3284

uint32_t vblank_time_us)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3287

uint32_t switch_limit_us;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3318

uint32_t sclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3319

uint32_t mclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3325

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3331

uint32_t latency;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3487

static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3509

static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3593

void *pp_table, uint32_t classification_flag)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3733

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3799

uint32_t engine_clock, memory_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

3881

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4000

uint32_t sclk, mclk, activity_percent;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4001

uint32_t offset, val_vid;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4015

*((uint32_t *)value) = sclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4022

*((uint32_t *)value) = mclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4036

*((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4040

*((uint32_t *)value) = smu7_thermal_get_temperature(hwmgr);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4044

*((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4048

*((uint32_t *)value) = data->vce_power_gated ? 0 : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4056

return smu7_get_gpu_power(hwmgr, (uint32_t *)value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4066

return smu7_get_gpu_power(hwmgr, (uint32_t *)value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4076

*((uint32_t *)value) = (uint32_t)convert_to_vddc(val_vid);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4091

uint32_t sclk = smu7_ps->performance_levels

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4094

uint32_t mclk = smu7_ps->performance_levels

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4097

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4140

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4141

uint32_t sclk, max_sclk = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4254

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4298

uint32_t low_limit, uint32_t high_limit)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4300

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4321

uint32_t high_limit_count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

453

uint32_t display_gap =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4582

uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4583

uint32_t display_gap2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4584

uint32_t pre_vbi_time_in_us;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4585

uint32_t frame_time_in_us;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4586

uint32_t ref_clock, refresh_rate;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4759

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4919

enum pp_clock_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4943

uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4975

uint32_t i, now, clock, pcie_speed;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5064

static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5084

static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5105

static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

514

uint32_t arb_src, uint32_t arb_dest)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5147

static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

516

uint32_t mc_arb_dram_timing;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

517

uint32_t mc_arb_dram_timing2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

518

uint32_t burst_time;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

519

uint32_t mc_cg_config;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5199

static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5341

uint32_t i, j, k;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5375

uint32_t virtual_addr_low,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5376

uint32_t virtual_addr_hi,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5377

uint32_t mc_addr_low,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5378

uint32_t mc_addr_hi,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5379

uint32_t size)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5456

uint32_t clk,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5457

uint32_t voltage)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5493

long *input, uint32_t size)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5495

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5500

uint32_t input_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5501

uint32_t input_vol;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5502

uint32_t input_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5561

uint32_t i, size = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5562

uint32_t len;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5622

uint32_t tmp, level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5638

static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5710

PHM_PerformanceLevelDesignation designation, uint32_t index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5714

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

579

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5806

uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5807

uint32_t clock_insr)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5810

uint32_t temp;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

5811

uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

642

uint32_t i, max_entry;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

643

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

790

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

872

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

938

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

983

uint32_t min_vddc = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

984

uint32_t max_vddc = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

113

uint32_t vCG_SPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

114

uint32_t vCG_SPLL_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

115

uint32_t vCG_SPLL_FUNC_CNTL_3;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

116

uint32_t vCG_SPLL_FUNC_CNTL_4;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

117

uint32_t vCG_SPLL_SPREAD_SPECTRUM;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

118

uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

119

uint32_t vDLL_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

120

uint32_t vMCLK_PWRMGT_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

121

uint32_t vMPLL_AD_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

122

uint32_t vMPLL_DQ_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

123

uint32_t vMPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

124

uint32_t vMPLL_FUNC_CNTL_1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

125

uint32_t vMPLL_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

126

uint32_t vMPLL_SS1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

127

uint32_t vMPLL_SS2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

134

uint32_t vS0_VID_LOWER_SMIO_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

150

uint32_t sclk_bootup_value;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

151

uint32_t mclk_bootup_value;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

157

uint32_t min_clock_in_sr;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

158

uint32_t num_existing_displays;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

159

uint32_t vrefresh;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

163

uint32_t uvd_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

164

uint32_t vce_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

165

uint32_t acp_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

166

uint32_t samu_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

167

uint32_t sclk_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

168

uint32_t mclk_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

169

uint32_t pcie_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

178

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

187

uint32_t odn_mclk_min_limit;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

188

uint32_t min_vddc;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

189

uint32_t max_vddc;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

204

uint32_t frequency;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

205

uint32_t latency;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

209

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

219

uint32_t voting_rights_clients[8];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

220

uint32_t static_screen_threshold_unit;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

221

uint32_t static_screen_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

222

uint32_t voltage_control;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

223

uint32_t vdd_gfx_control;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

224

uint32_t vddc_vddgfx_delta;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

225

uint32_t active_auto_throttle_sources;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

234

uint32_t pcie_gen_cap;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

235

uint32_t pcie_lane_cap;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

236

uint32_t pcie_spc_cap;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

241

uint32_t mvdd_control;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

242

uint32_t vddc_mask_low;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

243

uint32_t mvdd_mask_low;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

259

uint32_t soft_regs_start;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

261

uint32_t vddci_control;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

267

uint32_t mgcg_cgtt_local2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

268

uint32_t mgcg_cgtt_local3;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

269

uint32_t gpio_debug;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

270

uint32_t mc_micro_code_feature;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

271

uint32_t highest_mclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

282

uint32_t cac_table_start;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

288

uint32_t power_containment_features;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

295

uint32_t dte_tj_offset;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

296

uint32_t fast_watermark_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

307

uint32_t need_update_smu7_dpm_table;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

308

uint32_t sclk_dpm_key_disabled;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

309

uint32_t mclk_dpm_key_disabled;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

310

uint32_t pcie_dpm_key_disabled;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

311

uint32_t min_engine_clocks;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

318

uint32_t mclk_dpm0_activity_target;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

319

uint32_t low_sclk_interrupt_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

320

uint32_t last_mclk_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

331

uint32_t down_hyst;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

332

uint32_t up_hyst;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

333

uint32_t disable_dpm_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

336

uint32_t avfs_vdroop_override_setting;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

338

uint32_t frame_time_x2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

339

uint32_t last_sent_vbi_timeout;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

342

uint32_t vr_config;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

345

uint32_t ro_range_minimum;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

346

uint32_t ro_range_maximum;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

385

uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

386

uint32_t clock_insr);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

47

uint32_t offset;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

48

uint32_t mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

49

uint32_t shift;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

50

uint32_t value;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

55

uint32_t memory_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

56

uint32_t engine_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

68

uint32_t vclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

69

uint32_t dclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

73

uint32_t evclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

74

uint32_t ecclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

78

uint32_t magic;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

81

uint32_t sam_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

84

uint32_t sclk_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

90

uint32_t value;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

91

uint32_t param1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h

99

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1125

int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1139

uint32_t target_tdp)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

1262

result = smu7_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

32

static uint32_t DIDTBlock_Info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

34

static uint32_t Polaris11_DIDTBlock_Info = SQ_PCC_MASK | TCP_IR_MASK | TD_PCC_MASK;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

853

uint32_t en = enable ? 1 : 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

854

uint32_t block_en = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

856

uint32_t didt_block;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

901

uint32_t cache = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

902

uint32_t data = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

961

uint32_t num_se = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

962

uint32_t count, value, value2;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c

964

uint32_t efuse;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.h

57

int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

108

int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

204

uint32_t speed)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

206

uint32_t duty100;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

207

uint32_t duty;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

213

speed = min_t(uint32_t, speed, 255);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

226

duty = (uint32_t)tmp64;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

262

int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

264

uint32_t tach_period;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

265

uint32_t crystal_clock_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

374

uint32_t alert;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

392

uint32_t alert;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

55

uint32_t *speed)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

57

uint32_t duty100;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

58

uint32_t duty;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

75

*speed = min_t(uint32_t, tmp64, 255);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

80

int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

82

uint32_t tach_period;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c

83

uint32_t crystal_clock_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.h

44

extern int smu7_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr *hwmgr, uint32_t *speed);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.h

46

extern int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.h

47

extern int smu7_fan_ctrl_set_fan_speed_pwm(struct pp_hwmgr *hwmgr, uint32_t speed);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.h

50

extern int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_thermal.h

51

extern int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

100

uint32_t clock, uint32_t msg)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

129

static uint32_t smu8_get_uvd_level(struct pp_hwmgr *hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

130

uint32_t clock, uint32_t msg)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1343

static uint32_t smu8_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1350

static uint32_t smu8_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1467

uint32_t data = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1498

static int smu8_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1528

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1547

enum pp_clock_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1573

uint32_t i, now;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

160

static uint32_t smu8_get_max_sclk_level(struct pp_hwmgr *hwmgr)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1608

PHM_PerformanceLevelDesignation designation, uint32_t index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1613

uint32_t level_index;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1614

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1713

uint32_t val = cgs_read_ind_register(hwmgr->device,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1715

uint32_t temp = PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1739

uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1741

uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1743

uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1746

uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1759

*((uint32_t *)value) = sclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1767

*((uint32_t *)value) = vddnb;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1773

*((uint32_t *)value) = vddgfx;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1781

*((uint32_t *)value) = vclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1785

*((uint32_t *)value) = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1793

*((uint32_t *)value) = dclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1797

*((uint32_t *)value) = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1805

*((uint32_t *)value) = ecclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1809

*((uint32_t *)value) = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1819

*((uint32_t *)value) = activity_percent;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1822

*((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1825

*((uint32_t *)value) = data->vce_power_gated ? 0 : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1828

*((uint32_t *)value) = smu8_thermal_get_temperature(hwmgr);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1836

uint32_t virtual_addr_low,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1837

uint32_t virtual_addr_hi,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1838

uint32_t mc_addr_low,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1839

uint32_t mc_addr_hi,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1840

uint32_t size)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1883

uint32_t dpm_features = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1939

uint32_t dpm_features = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

250

static uint32_t smu8_convert_8Bit_index_to_voltage(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

313

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

439

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

586

uint32_t level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

616

uint32_t level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

646

uint32_t level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

68

static uint32_t smu8_get_eclk_level(struct pp_hwmgr *hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

69

uint32_t clock, uint32_t msg)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

769

uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

99

static uint32_t smu8_get_sclk_level(struct pp_hwmgr *hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

100

uint32_t engineClock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

114

uint32_t vclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

115

uint32_t dclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

116

uint32_t vclk_low_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

117

uint32_t vclk_high_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

118

uint32_t dclk_low_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

119

uint32_t dclk_high_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

131

uint32_t entry : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

132

uint32_t display : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

133

uint32_t driver: 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

134

uint32_t vce : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

135

uint32_t uvd : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

136

uint32_t acp : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

137

uint32_t reserved: 26;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

139

uint32_t u32All;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

145

uint32_t level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

147

uint32_t evclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

148

uint32_t ecclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

149

uint32_t samclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

150

uint32_t acpclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

152

uint32_t nbps_flags;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

153

uint32_t bapm_flags;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

179

uint32_t cpu_pstate_separation_time;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

183

uint32_t dpm_interval;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

185

uint32_t voltage_drop_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

187

uint32_t voting_rights_clients;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

189

uint32_t disable_driver_thermal_policy;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

191

uint32_t static_screen_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

193

uint32_t gfx_power_gating_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

195

uint32_t activity_hysteresis;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

196

uint32_t bootup_sclk_divider;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

197

uint32_t gfx_ramp_step;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

198

uint32_t gfx_ramp_delay; /* in micro-seconds */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

200

uint32_t thermal_auto_throttling_treshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

208

uint32_t mgcg_cgtt_local0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

209

uint32_t mgcg_cgtt_local1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

211

uint32_t tdr_clock; /* in 10khz unit */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

213

uint32_t ddi_power_gating_disabled;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

214

uint32_t disable_gfx_power_gating_in_uvd;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

215

uint32_t disable_nb_ps3_in_battery;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

217

uint32_t lock_nb_ps_in_uvd_play_back;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

220

uint32_t vce_slow_sclk_threshold; /* default 200mhz */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

221

uint32_t dce_slow_sclk_threshold; /* default 300mhz */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

222

uint32_t min_sclk_did; /* minimum sclk divider */

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

226

uint32_t bapm_enabled;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

227

uint32_t clock_slow_down_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

228

uint32_t skip_clock_slow_down;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

229

uint32_t enable_nb_ps_policy;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

230

uint32_t voltage_drop_in_dce_power_gating;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

231

uint32_t uvd_dpm_interval;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

232

uint32_t override_dynamic_mgpg;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

233

uint32_t lclk_deep_enabled;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

235

uint32_t uvd_performance;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

239

uint32_t lowest_valid;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

240

uint32_t highest_valid;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

241

uint32_t high_voltage_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

242

uint32_t is_nb_dpm_enabled;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

244

uint32_t is_voltage_island_enabled;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

251

uint32_t power_containment_features;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

257

uint32_t sram_end;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

258

uint32_t dpm_table_start;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

259

uint32_t soft_regs_start;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

266

uint32_t fps_high_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

267

uint32_t fps_low_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

269

uint32_t dpm_flags;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

291

uint32_t display_cac;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

292

uint32_t low_sclk_interrupt_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

294

uint32_t dram_log_addr_h;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

295

uint32_t dram_log_addr_l;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

296

uint32_t dram_log_phy_addr_h;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

297

uint32_t dram_log_phy_addr_l;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

298

uint32_t dram_log_buff_size;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

305

uint32_t active_process_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

307

uint32_t max_sclk_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

308

uint32_t num_of_clk_entries;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

45

uint32_t soft_min_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

46

uint32_t hard_min_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

47

uint32_t soft_max_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

48

uint32_t hard_max_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

52

uint32_t bootup_uma_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

53

uint32_t bootup_engine_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

54

uint32_t dentist_vco_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

55

uint32_t nb_dpm_enable;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

56

uint32_t nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

57

uint32_t nbp_n_clock[SMU8_NUM_NBPSTATES];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

59

uint32_t display_clock[MAX_DISPLAY_CLOCK_LEVEL];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

63

uint32_t system_config;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

64

uint32_t uma_channel_number;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

79

(((uint32_t)(phyID))<<DISPLAYPHY_PHYID_SHIFT | \

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.h

80

((uint32_t)(lanemask))<<DISPLAYPHY_LANESELECT_SHIFT | \

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu9_baco.c

34

uint32_t reg, data;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu9_baco.c

55

uint32_t reg;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

110

int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

111

uint32_t value, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

113

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

114

uint32_t cur_value;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

141

uint32_t indirect_port,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

142

uint32_t index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

143

uint32_t value,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

144

uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

156

uint32_t index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

157

uint32_t value, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

159

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

160

uint32_t cur_value;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

180

uint32_t indirect_port,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

181

uint32_t index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

182

uint32_t value,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

183

uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

206

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

251

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

279

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

328

void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

347

uint32_t count, int max)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

363

uint32_t index, uint32_t pcie_gen,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

364

uint32_t pcie_lanes)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

410

uint32_t voltage)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

432

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

444

uint32_t value, uint32_t *boot_level)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

447

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

48

uint32_t **pptable_info_array,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

49

const uint32_t *pptable_array,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

50

uint32_t power_saving_clock_count)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

52

uint32_t array_size, i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

53

uint32_t *table;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

535

uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

537

uint32_t level = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

55

array_size = sizeof(uint32_t) * power_saving_clock_count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

553

uint32_t req_vddc = 0, req_volt, i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

570

req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

583

uint32_t sclk, uint16_t id, uint16_t *voltage)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

585

uint32_t vol;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

607

uint32_t client_id = entry->client_id;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

608

uint32_t src_id = entry->src_id;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

674

void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

70

uint32_t **pptable_info_array,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

71

const uint32_t *pptable_array,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

718

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

72

uint32_t od_setting_count)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

74

uint32_t array_size, i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

75

uint32_t *table;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

77

array_size = sizeof(uint32_t) * od_setting_count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.c

90

uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

100

uint32_t value, uint32_t mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

103

uint32_t indirect_port,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

104

uint32_t index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

105

uint32_t value,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

106

uint32_t mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

127

void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

47

uint32_t padding[7];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

52

uint32_t **pptable_info_array,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

53

const uint32_t *pptable_array,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

54

uint32_t power_saving_clock_count);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

58

uint32_t **pptable_info_array,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

59

const uint32_t *pptable_array,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

60

uint32_t od_setting_count);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

63

uint32_t index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

64

uint32_t value, uint32_t mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

67

uint32_t indirect_port, uint32_t index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

68

uint32_t value, uint32_t mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

79

extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

80

extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

81

extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

84

uint32_t voltage);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

87

extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

91

extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

95

uint32_t sclk, uint16_t id, uint16_t *voltage);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

97

extern uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h

99

extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1025

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1097

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1148

uint32_t max_vol_steps,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1266

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1313

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1501

uint32_t lclock, uint8_t *curr_lclk_did)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1522

uint32_t pcie_gen = 0, pcie_width = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1573

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1614

uint32_t gfx_clock, PllSetting_t *current_gfxclk_level,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1615

uint32_t *acg_freq)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1622

uint32_t gfx_max_clock =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1624

uint32_t i = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1681

uint32_t soc_clock, uint8_t *current_soc_did,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1689

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1735

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1792

uint32_t i, max_vddc_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1818

uint32_t mem_clock, uint8_t *current_mem_vid,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1826

uint32_t mem_max_clock =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1828

uint32_t i = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1885

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1929

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1978

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1990

uint32_t eclock, uint8_t *current_eclk_did,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1998

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2022

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2048

uint32_t vclock, uint8_t *current_vclk_did)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2064

uint32_t dclock, uint8_t *current_dclk_did)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2092

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2158

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2179

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2363

uint32_t agc_btc_response;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2494

uint32_t top32, bottom32;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2535

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2696

(uint32_t)(data->vbios_boot_state.dcef_clock / 100),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2910

static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2913

uint32_t i, feature_mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2947

static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2950

uint32_t i, feature_mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3136

void *pp_table, uint32_t classification_flag)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

314

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3282

uint32_t sclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3283

uint32_t mclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3290

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3295

uint32_t stable_pstate_sclk_dpm_percentage;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3296

uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3297

uint32_t latency;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3441

uint32_t sclk, mclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3442

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3528

uint32_t low_limit, uint32_t high_limit)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3530

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3544

uint32_t low_limit, uint32_t high_limit,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3545

uint32_t disable_dpm_mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3547

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3565

uint32_t high_limit_count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3592

static uint32_t vega10_find_lowest_dpm_level(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3595

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

360

uint32_t sub_vendor_id, hw_revision;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3605

static uint32_t vega10_find_highest_dpm_level(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3608

uint32_t i = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

361

uint32_t top32, bottom32;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3643

uint32_t socclk_idx;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3815

uint32_t low_sclk_interrupt_threshold = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3828

(uint32_t)low_sclk_interrupt_threshold,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3884

static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3906

static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3929

uint32_t *query)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3931

uint32_t value;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3951

uint32_t sclk_mhz, mclk_idx, activity_percent = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3955

uint32_t val_vid;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3963

*((uint32_t *)value) = sclk_mhz * 100;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3970

*((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3979

*((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3983

*((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3987

smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHotspot, (uint32_t *)value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3988

*((uint32_t *)value) = *((uint32_t *)value) *

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3993

smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHBM, (uint32_t *)value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3994

*((uint32_t *)value) = *((uint32_t *)value) *

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

3999

*((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4003

*((uint32_t *)value) = data->vce_power_gated ? 0 : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4007

ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4013

*((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4042

uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4044

uint32_t clk_request = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4078

uint32_t frequency)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4105

uint32_t idx;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4107

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4220

uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4252

static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4275

enum pp_clock_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4337

uint32_t sclk_mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4338

uint32_t mclk_mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4339

uint32_t soc_mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4380

static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4411

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4432

uint32_t j = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4433

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4457

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4473

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4513

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4537

clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4691

uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4694

uint32_t i, now, count = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4837

uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5164

static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5217

static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5256

uint32_t virtual_addr_low,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5257

uint32_t virtual_addr_hi,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5258

uint32_t mc_addr_low,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5259

uint32_t mc_addr_hi,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5260

uint32_t size)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5324

uint32_t i, size = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5367

static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5374

uint32_t power_profile_mode = input[size];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5420

uint32_t clk,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5421

uint32_t voltage)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5593

long *input, uint32_t size)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5599

uint32_t input_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5600

uint32_t input_vol;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5601

uint32_t input_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5602

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

564

uint32_t vddc = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

566

uint32_t sclk = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5682

PHM_PerformanceLevelDesignation designation, uint32_t index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5686

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

5707

uint32_t feature_mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

61

static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

620

uint32_t index;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

648

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

723

uint32_t table_size, i, j;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

830

uint32_t config_telemetry = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

969

uint32_t mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

970

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

980

mask |= (uint32_t)(i << (8 * j));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

101

uint32_t evclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

102

uint32_t ecclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

106

uint32_t magic;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

111

uint32_t sclk_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

117

uint32_t value;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

118

uint32_t param1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

127

uint32_t soft_min_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

128

uint32_t soft_max_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

129

uint32_t hard_min_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

130

uint32_t hard_max_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

134

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

143

uint32_t lclk[MAX_PCIE_CONF];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

168

uint32_t min_clock_in_sr;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

169

uint32_t num_existing_displays;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

173

uint32_t uvd_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

174

uint32_t vce_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

175

uint32_t acp_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

176

uint32_t samu_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

177

uint32_t sclk_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

178

uint32_t mclk_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

187

uint32_t gfx_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

188

uint32_t mem_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

189

uint32_t soc_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

190

uint32_t dcef_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

194

uint32_t soc_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

195

uint32_t gfx_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

196

uint32_t dcef_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

197

uint32_t mem_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

198

uint32_t uvd_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

199

uint32_t vce_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

200

uint32_t gfx_max_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

201

uint32_t mem_max_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

202

uint32_t soc_max_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

215

uint32_t frequency;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

216

uint32_t latency;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

220

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

236

uint32_t fast_watermark_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

244

uint32_t pcieClockOverride;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

261

uint32_t stable_pstate_sclk_dpm_percentage;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

274

uint32_t vddc_vddci_delta;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

285

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

290

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

299

uint32_t max_vddc;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

300

uint32_t min_vddc;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

304

uint32_t target_fan_speed;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

305

uint32_t target_temperature;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

306

uint32_t min_performance_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

307

uint32_t min_fan_limit;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

319

uint32_t vddc_control;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

321

uint32_t mvdd_control;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

323

uint32_t vddci_control;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

326

uint32_t active_auto_throttle_sources;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

327

uint32_t water_marks_bitmap;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

340

uint32_t low_sclk_interrupt_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

342

uint32_t total_active_cus;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

348

uint32_t debug_settings;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

349

uint32_t lowest_uclk_reserved_for_ulv;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

350

uint32_t gfxclk_average_alpha;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

351

uint32_t socclk_average_alpha;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

352

uint32_t uclk_average_alpha;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

353

uint32_t gfx_activity_average_alpha;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

354

uint32_t display_voltage_mode;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

355

uint32_t dcef_clk_quad_eqn_a;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

356

uint32_t dcef_clk_quad_eqn_b;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

357

uint32_t dcef_clk_quad_eqn_c;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

358

uint32_t disp_clk_quad_eqn_a;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

359

uint32_t disp_clk_quad_eqn_b;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

360

uint32_t disp_clk_quad_eqn_c;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

361

uint32_t pixel_clk_quad_eqn_a;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

362

uint32_t pixel_clk_quad_eqn_b;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

363

uint32_t pixel_clk_quad_eqn_c;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

364

uint32_t phy_clk_quad_eqn_a;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

365

uint32_t phy_clk_quad_eqn_b;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

366

uint32_t phy_clk_quad_eqn_c;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

377

uint32_t disable_dpm_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

383

uint32_t config_telemetry;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

384

uint32_t acg_loop_state;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

385

uint32_t mem_channels;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

80

uint32_t smu_feature_id;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

81

uint32_t smu_feature_bitmap;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

85

uint32_t soc_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

86

uint32_t gfx_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

87

uint32_t mem_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

91

uint32_t baco_flags;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

96

uint32_t vclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.h

97

uint32_t dclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1046

uint32_t num_se = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1047

uint32_t count, data;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1090

uint32_t data;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1276

int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1297

(uint32_t)(tdp_table->usMaximumPowerDeliveryLimit);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1346

uint32_t adjust_percent)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

1363

(uint32_t)adjust_percent);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

751

uint32_t data;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

787

uint32_t data;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

802

uint32_t data;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

803

uint32_t en = (enable ? 1 : 0);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

804

uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

887

uint32_t num_se = 0, count, data;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

938

uint32_t num_se = 0, count, data;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

976

uint32_t data;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

999

uint32_t num_se = 0, count, data;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

46

uint32_t offset;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

47

uint32_t mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

48

uint32_t shift;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

49

uint32_t value;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

54

uint32_t offset;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

55

uint32_t mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

56

uint32_t shift;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

57

uint32_t value;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.h

74

int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1036

uint32_t max_levels)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1038

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1066

uint32_t disable_power_control = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1262

return (uint32_t)(state_arrays->ucNumEntries);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1265

static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1268

uint32_t result = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1295

uint32_t entry_index, struct pp_power_state *power_state,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

1297

struct pp_power_state *, void *, uint32_t))

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

346

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

422

uint32_t table_size;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

430

table_size = sizeof(uint32_t) + sizeof(struct phm_tdp_table);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

570

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

581

clk_table->count = (uint32_t)clk_dep_table->ucNumEntries;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

600

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

611

mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

635

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

698

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

730

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

734

uint32_t dev_id;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

735

uint32_t rev_id;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

763

clk_table->count = (uint32_t)num_entries;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

786

uint32_t i, pcie_count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

850

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

861

table->count = (uint32_t)clk_volt_pp_table->count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

864

table->values[i] = (uint32_t)clk_volt_pp_table->entries[i].clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

88

static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.h

59

extern int vega10_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, uint32_t entry_index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.h

61

struct pp_power_state *, void *, uint32_t));

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

126

int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

248

uint32_t speed)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

251

uint32_t duty100;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

252

uint32_t duty;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

258

speed = min_t(uint32_t, speed, 255);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

271

duty = (uint32_t)tmp64;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

302

int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

305

uint32_t tach_period;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

306

uint32_t crystal_clock_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

32

static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

368

uint32_t val;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

436

uint32_t val = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

526

(uint32_t)table->FanTargetTemperature,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

68

uint32_t *speed)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

71

uint32_t duty100, duty;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

84

*speed = min_t(uint32_t, tmp64, 255);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

89

int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

93

uint32_t tach_period;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

94

uint32_t crystal_clock_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.h

58

uint32_t *speed);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.h

61

uint32_t mode);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.h

63

uint32_t speed);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.h

68

uint32_t speed);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_thermal.h

70

uint32_t *speed);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1027

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1120

static uint32_t vega12_find_lowest_dpm_level(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1123

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1138

static uint32_t vega12_find_highest_dpm_level(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1156

return (uint32_t)i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1162

uint32_t min_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1253

uint32_t max_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1339

static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1343

uint32_t gfx_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1362

static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1366

uint32_t mem_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1413

static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1427

static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1429

uint32_t gfx_clk = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1444

static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1446

uint32_t mem_clk = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1464

uint32_t *activity_percent)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1497

ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1502

ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1508

ret = vega12_get_current_activity_percent(hwmgr, idx, (uint32_t *)value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1513

*((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1521

*((uint32_t *)value) = metrics_table.TemperatureHotspot *

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1530

*((uint32_t *)value) = metrics_table.TemperatureHBM *

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1535

*((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1539

*((uint32_t *)value) = data->vce_power_gated ? 0 : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1543

ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1579

uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1581

uint32_t clk_request = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1659

uint32_t soft_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1688

uint32_t soft_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1728

uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1760

static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1782

uint32_t sclk_mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1783

uint32_t mclk_mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1784

uint32_t soc_mask = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1815

static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1841

uint32_t *clock,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1859

uint32_t ucount;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1882

static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1883

uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1892

uint32_t ucount;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1919

uint32_t ucount;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

1947

uint32_t ucount;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2026

enum pp_clock_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2029

uint32_t soft_min_level, soft_max_level, hard_min_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2245

uint32_t width_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2265

uint32_t speed_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2364

uint32_t i, latency;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2666

uint32_t *sclk_idx, uint32_t *mclk_idx,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2667

uint32_t min_sclk, uint32_t min_mclk)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2671

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2714

static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2735

static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2742

uint32_t virtual_addr_low,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2743

uint32_t virtual_addr_hi,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2744

uint32_t mc_addr_low,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2745

uint32_t mc_addr_hi,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2746

uint32_t size)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2835

PHM_PerformanceLevelDesignation designation, uint32_t index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2885

uint32_t fan_speed_rpm;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

300

uint32_t top32, bottom32;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

499

uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg, pcie_gen_arg, pcie_width_arg;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

579

PPCLK_e clk_id, uint32_t *num_of_levels)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

58

enum pp_clock_type type, uint32_t mask);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

595

PPCLK_e clkID, uint32_t index, uint32_t *clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

60

uint32_t *clock,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

614

uint32_t i, num_of_levels, clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

789

uint32_t min_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

845

(uint32_t)(data->vbios_boot_state.dcef_clock / 100),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

861

uint32_t result;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

879

uint32_t allowed_features_low = 0, allowed_features_high = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

974

uint32_t adjust_percent)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

991

(uint32_t)adjust_percent);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

100

uint32_t soft_min_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

101

uint32_t soft_max_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

102

uint32_t hard_min_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

103

uint32_t hard_max_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

107

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

113

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

114

uint32_t entries[MAX_REGULAR_DPM_NUMBER];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

121

uint32_t lclk[MAX_PCIE_CONF];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

146

uint32_t min_clock_in_sr;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

147

uint32_t num_existing_displays;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

151

uint32_t uvd_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

152

uint32_t vce_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

153

uint32_t samu_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

154

uint32_t sclk_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

155

uint32_t mclk_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

165

uint32_t gfx_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

166

uint32_t mem_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

167

uint32_t soc_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

168

uint32_t dcef_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

169

uint32_t eclock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

170

uint32_t dclock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

171

uint32_t vclock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

181

uint32_t soc_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

182

uint32_t gfx_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

183

uint32_t dcef_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

184

uint32_t mem_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

185

uint32_t uvd_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

186

uint32_t vce_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

187

uint32_t gfx_max_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

188

uint32_t mem_max_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

205

uint32_t frequency;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

206

uint32_t latency;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

210

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

229

uint32_t pcie_clock_override;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

258

uint32_t force_workload_policy_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

262

uint32_t perf_ui_tuning_profile_turbo;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

263

uint32_t perf_ui_tuning_profile_powerSave;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

264

uint32_t perf_ui_tuning_profile_xl;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

267

uint32_t stable_pstate_sclk_dpm_percentage;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

272

uint32_t auto_wattman_debug;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

273

uint32_t auto_wattman_sample_period;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

282

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

295

uint32_t odn_mclk_min_limit;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

299

uint32_t target_fan_speed;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

300

uint32_t target_temperature;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

301

uint32_t min_performance_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

302

uint32_t min_fan_limit;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

307

uint32_t ACMax;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

308

uint32_t ACMin;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

309

uint32_t DCMax;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

321

uint32_t vddc_control;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

323

uint32_t mvdd_control;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

325

uint32_t vddci_control;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

328

uint32_t active_auto_throttle_sources;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

329

uint32_t water_marks_bitmap;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

342

uint32_t low_sclk_interrupt_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

344

uint32_t total_active_cus;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

350

uint32_t debug_settings;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

351

uint32_t lowest_uclk_reserved_for_ulv;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

352

uint32_t gfxclk_average_alpha;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

353

uint32_t socclk_average_alpha;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

354

uint32_t uclk_average_alpha;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

355

uint32_t gfx_activity_average_alpha;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

356

uint32_t display_voltage_mode;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

357

uint32_t dcef_clk_quad_eqn_a;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

358

uint32_t dcef_clk_quad_eqn_b;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

359

uint32_t dcef_clk_quad_eqn_c;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

360

uint32_t disp_clk_quad_eqn_a;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

361

uint32_t disp_clk_quad_eqn_b;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

362

uint32_t disp_clk_quad_eqn_c;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

363

uint32_t pixel_clk_quad_eqn_a;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

364

uint32_t pixel_clk_quad_eqn_b;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

365

uint32_t pixel_clk_quad_eqn_c;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

366

uint32_t phy_clk_quad_eqn_a;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

367

uint32_t phy_clk_quad_eqn_b;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

368

uint32_t phy_clk_quad_eqn_c;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

381

uint32_t disable_dpm_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

384

uint32_t apply_overdrive_next_settings_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

387

uint32_t workload_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

390

uint32_t smu_version;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

84

uint32_t smu_feature_id;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

90

uint32_t value;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.h

91

uint32_t param1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

196

uint32_t disable_power_control = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

322

static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

325

uint32_t result = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

352

uint32_t entry_index, struct pp_power_state *power_state,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

354

struct pp_power_state *, void *, uint32_t))

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c

76

static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

178

uint32_t val;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

212

uint32_t val = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

260

(uint32_t)table->FanTargetTemperature,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

32

static int vega12_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

55

int vega12_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega12_thermal.h

58

uint32_t *speed);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_baco.c

42

uint32_t reg;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_baco.c

60

uint32_t reg;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_baco.c

77

uint32_t data;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1229

uint32_t *voltage,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1230

uint32_t freq)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1402

uint32_t index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1403

uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1496

struct pp_hwmgr *hwmgr, uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1501

uint32_t od_sclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1542

struct pp_hwmgr *hwmgr, uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1547

uint32_t od_mclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1776

static uint32_t vega20_find_lowest_dpm_level(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1779

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1793

static uint32_t vega20_find_highest_dpm_level(

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1820

static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1824

uint32_t min_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1921

static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

1925

uint32_t max_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2038

uint32_t *clock,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2063

static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2067

uint32_t gfx_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2089

static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2093

uint32_t mem_clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2144

uint32_t *query)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2170

PPCLK_e clk_id, uint32_t *clk_freq)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2189

uint32_t *activity_percent)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2219

uint32_t val_vid;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2228

*((uint32_t *)value) = metrics_table.AverageGfxclkFrequency * 100;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2234

(uint32_t *)value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2240

ret = vega20_get_current_activity_percent(hwmgr, idx, (uint32_t *)value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2245

*((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2253

*((uint32_t *)value) = metrics_table.TemperatureEdge *

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2262

*((uint32_t *)value) = metrics_table.TemperatureHBM *

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2267

*((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2271

*((uint32_t *)value) = data->vce_power_gated ? 0 : 1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2277

ret = vega20_get_gpu_power(hwmgr, idx, (uint32_t *)value);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2283

*((uint32_t *)value) =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2284

(uint32_t)convert_to_vddc((uint8_t)val_vid);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2304

uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2306

uint32_t clk_request = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2341

PHM_PerformanceLevelDesignation designation, uint32_t index,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2395

uint32_t soft_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2437

uint32_t soft_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2480

uint32_t soft_min_level, soft_max_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2534

uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2567

enum pp_clock_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2570

uint32_t soft_min_level, soft_max_level, hard_min_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2734

uint32_t sclk_mask, mclk_mask, soc_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2770

static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2780

static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2837

static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2838

uint32_t clock)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2968

long *input, uint32_t size)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2977

uint32_t input_index;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3336

uint32_t width_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

335

uint32_t top32, bottom32;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3356

uint32_t speed_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3380

uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3746

uint32_t i, latency;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3994

uint32_t i, size = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4091

static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4095

uint32_t power_profile_mode = input[size];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4198

uint32_t virtual_addr_low,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4199

uint32_t virtual_addr_hi,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4200

uint32_t mc_addr_low,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4201

uint32_t mc_addr_hi,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4202

uint32_t size)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4297

uint32_t pstate)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

4331

uint32_t fan_speed_rpm;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

537

PPCLK_e clk_id, uint32_t *num_of_levels)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

553

PPCLK_e clk_id, uint32_t index, uint32_t *clk)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

572

uint32_t i, num_of_levels, clk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

820

(uint32_t)(data->vbios_boot_state.dcef_clock / 100),

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

845

uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg, pcie_gen_arg, pcie_width_arg;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

929

uint32_t allowed_features_low = 0, allowed_features_high = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

102

uint32_t soc_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

103

uint32_t gfx_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

104

uint32_t mem_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

108

uint32_t baco_flags;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

113

uint32_t vclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

114

uint32_t dclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

118

uint32_t evclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

119

uint32_t ecclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

123

uint32_t magic;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

128

uint32_t sclk_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

134

uint32_t value;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

135

uint32_t param1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

153

uint32_t soft_min_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

154

uint32_t soft_max_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

155

uint32_t hard_min_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

156

uint32_t hard_max_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

160

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

166

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

167

uint32_t entries[MAX_REGULAR_DPM_NUMBER];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

174

uint32_t lclk[MAX_PCIE_CONF];

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

200

uint32_t min_clock_in_sr;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

201

uint32_t num_existing_displays;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

205

uint32_t uvd_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

206

uint32_t vce_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

207

uint32_t samu_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

208

uint32_t sclk_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

209

uint32_t mclk_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

218

uint32_t gfx_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

219

uint32_t mem_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

220

uint32_t soc_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

221

uint32_t dcef_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

222

uint32_t eclock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

223

uint32_t dclock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

224

uint32_t vclock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

225

uint32_t fclock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

242

uint32_t soc_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

243

uint32_t gfx_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

244

uint32_t dcef_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

245

uint32_t mem_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

246

uint32_t uvd_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

247

uint32_t vce_boot_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

248

uint32_t gfx_max_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

249

uint32_t mem_max_level;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

266

uint32_t frequency;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

267

uint32_t latency;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

271

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

290

uint32_t pcie_clock_override;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

319

uint32_t force_workload_policy_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

323

uint32_t perf_ui_tuning_profile_turbo;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

324

uint32_t perf_ui_tuning_profile_powerSave;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

325

uint32_t perf_ui_tuning_profile_xl;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

328

uint32_t stable_pstate_sclk_dpm_percentage;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

333

uint32_t auto_wattman_debug;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

334

uint32_t auto_wattman_sample_period;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

335

uint32_t fclk_gfxclk_ratio;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

345

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

358

uint32_t odn_mclk_min_limit;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

362

uint32_t target_fan_speed;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

363

uint32_t target_temperature;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

364

uint32_t min_performance_clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

365

uint32_t min_fan_limit;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

378

uint32_t apply_overdrive_next_settings_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

379

uint32_t overdrive_next_state;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

380

uint32_t overdrive_next_capabilities;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

381

uint32_t odn_sclk_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

382

uint32_t odn_mclk_dpm_enable_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

422

uint32_t feature_id;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

430

uint32_t overdrive8_capabilities;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

445

uint32_t vddc_control;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

447

uint32_t mvdd_control;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

449

uint32_t vddci_control;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

452

uint32_t active_auto_throttle_sources;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

463

uint32_t low_sclk_interrupt_threshold;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

465

uint32_t total_active_cus;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

467

uint32_t water_marks_bitmap;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

47

typedef uint32_t PP_Clock;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

473

uint32_t debug_settings;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

474

uint32_t lowest_uclk_reserved_for_ulv;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

475

uint32_t gfxclk_average_alpha;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

476

uint32_t socclk_average_alpha;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

477

uint32_t uclk_average_alpha;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

478

uint32_t gfx_activity_average_alpha;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

479

uint32_t display_voltage_mode;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

480

uint32_t dcef_clk_quad_eqn_a;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

481

uint32_t dcef_clk_quad_eqn_b;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

482

uint32_t dcef_clk_quad_eqn_c;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

483

uint32_t disp_clk_quad_eqn_a;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

484

uint32_t disp_clk_quad_eqn_b;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

485

uint32_t disp_clk_quad_eqn_c;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

486

uint32_t pixel_clk_quad_eqn_a;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

487

uint32_t pixel_clk_quad_eqn_b;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

488

uint32_t pixel_clk_quad_eqn_c;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

489

uint32_t phy_clk_quad_eqn_a;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

490

uint32_t phy_clk_quad_eqn_b;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

491

uint32_t phy_clk_quad_eqn_c;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

504

uint32_t disable_dpm_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

515

uint32_t workload_mask;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

518

uint32_t smu_version;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

524

uint32_t counter_gfxoff;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

531

uint32_t pcie_gen_level1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

532

uint32_t pcie_width_level1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.h

97

uint32_t smu_feature_id;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_powertune.c

32

int vega20_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_powertune.c

46

uint32_t tdp_percentage_adjustment, uint32_t tdp_absolute_value_adjustment)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_powertune.c

52

uint32_t adjust_percent)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_powertune.c

69

(uint32_t)adjust_percent);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_powertune.h

26

int vega20_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_powertune.h

29

uint32_t tdp_percentage_adjustment,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_powertune.h

30

uint32_t tdp_absolute_value_adjustment);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

117

uint32_t array_size, i;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

246

uint32_t disable_power_control = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

247

uint32_t od_feature_count, od_setting_count, power_saving_clock_count;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c

86

static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

104

static int vega20_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

118

uint32_t *speed)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

121

uint32_t duty100, duty;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

134

*speed = min_t(uint32_t, tmp64, 255);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

140

uint32_t speed)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

143

uint32_t duty100;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

144

uint32_t duty;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

147

speed = min_t(uint32_t, speed, 255);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

160

duty = (uint32_t)tmp64;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

181

int vega20_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

188

int vega20_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

191

uint32_t tach_period, crystal_clock_freq;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

249

uint32_t val;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

283

uint32_t val = 0;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

331

(uint32_t)table->FanTargetTemperature,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

90

static int vega20_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.h

56

uint32_t *speed);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.h

58

uint32_t speed);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.h

60

uint32_t *speed);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_thermal.h

62

uint32_t speed);

sys/dev/pci/drm/amd/pm/powerplay/inc/fiji_ppsmc.h

213

#define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0x126)

sys/dev/pci/drm/amd/pm/powerplay/inc/fiji_ppsmc.h

214

#define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint32_t) 0x127)

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

253

#define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8)

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

260

uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

271

uint32_t coreClock;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

272

uint32_t memory_clock;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

273

uint32_t vddc;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

274

uint32_t vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

275

uint32_t nonLocalMemoryFreq;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

276

uint32_t nonLocalMemoryWidth;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

282

static inline void phm_cap_set(uint32_t *caps,

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

289

static inline void phm_cap_unset(uint32_t *caps,

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

295

static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c)

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

326

uint32_t engineClock;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

327

uint32_t memoryClock;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

328

uint32_t BusBandwidth;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

329

uint32_t engineClockInSR;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

330

uint32_t dcefClock;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

331

uint32_t dcefClockInSR;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

335

uint32_t min_mem_clk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

336

uint32_t max_mem_clk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

337

uint32_t min_eng_clk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

338

uint32_t max_eng_clk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

339

uint32_t min_bus_bandwidth;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

340

uint32_t max_bus_bandwidth;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

344

uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

345

uint32_t vbiosInterruptId;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

348

uint32_t hardwareActivityPerformanceLevels;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

349

uint32_t minimumClocksReductionPercentage;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

350

uint32_t minOverdriveVDDC;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

351

uint32_t maxOverdriveVDDC;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

352

uint32_t overdriveVDDCStep;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

353

uint32_t hardwarePerformanceLevels;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

355

uint32_t TDPLimit;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

356

uint32_t nearTDPLimit;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

357

uint32_t nearTDPLimitAdjusted;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

358

uint32_t SQRampingThreshold;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

359

uint32_t CACLeakage;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

36

uint32_t min_percent;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

361

uint32_t TDPAdjustment;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

364

uint32_t VidMinLimit;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

365

uint32_t VidMaxLimit;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

366

uint32_t VidStep;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

367

uint32_t VidAdjustment;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

37

uint32_t max_percent;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

372

uint32_t num_of_entries;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

373

uint32_t clock[MAX_NUM_CLOCKS];

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

38

uint32_t min_rpm;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

384

uint32_t clock;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

385

uint32_t vddc;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

39

uint32_t max_rpm;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

390

uint32_t size;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

391

uint32_t options;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

392

uint32_t flags;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

393

uint32_t num_of_pl;

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

437

PHM_PerformanceLevelDesignation designation, uint32_t index,

sys/dev/pci/drm/amd/pm/powerplay/inc/hardwaremanager.h

462

extern int phm_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

103

uint32_t ecclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

104

uint32_t evclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

105

uint32_t v;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

109

uint32_t vclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

110

uint32_t dclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

111

uint32_t v;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

115

uint32_t samclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

116

uint32_t v;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

120

uint32_t acpclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

121

uint32_t v;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

125

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

130

uint32_t Voltage;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

131

uint32_t Sclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

132

uint32_t Mclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

136

uint32_t vclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

137

uint32_t dclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

138

uint32_t v;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

147

uint32_t acpclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

148

uint32_t v;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

152

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

157

uint32_t ecclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

158

uint32_t evclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

159

uint32_t v;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

163

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

183

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

205

uint32_t firmware);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

208

uint32_t firmware);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

209

uint32_t (*get_argument)(struct pp_hwmgr *hwmgr);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

212

uint16_t msg, uint32_t parameter);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

216

int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

225

uint32_t (*get_offsetof)(uint32_t type, uint32_t member);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

226

uint32_t (*get_mac_definition)(uint32_t value);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

263

uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

264

uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

272

const uint32_t *msg_id);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

277

void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

278

uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

279

int (*set_fan_speed_pwm)(struct pp_hwmgr *hwmgr, uint32_t speed);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

280

int (*get_fan_speed_pwm)(struct pp_hwmgr *hwmgr, uint32_t *speed);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

281

int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t speed);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

282

int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

292

int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

298

PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

313

int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

319

int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

321

int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

325

int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

326

int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

329

uint32_t virtual_addr_low,

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

330

uint32_t virtual_addr_hi,

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

331

uint32_t mc_addr_low,

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

332

uint32_t mc_addr_hi,

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

333

uint32_t size);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

337

int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

340

long *input, uint32_t size);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

343

long *input, uint32_t size);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

344

int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

349

int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

350

int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

351

int (*set_hard_min_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

352

int (*set_soft_max_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

362

int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

366

int (*gfx_state_change)(struct pp_hwmgr *hwmgr, uint32_t state);

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

384

uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

394

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

399

uint32_t samclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

400

uint32_t v;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

441

uint32_t usBoostPowerLimit;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

483

uint32_t usBoostPowerLimit;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

486

uint32_t ulBoostClock;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

492

uint32_t platform_tdp;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

493

uint32_t small_ac_platform_tdp;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

494

uint32_t platform_tdc;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

495

uint32_t small_ac_platform_tdc;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

496

uint32_t apu_tdp;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

497

uint32_t dgpu_tdp;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

498

uint32_t dgpu_ulv_power;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

499

uint32_t tj_max;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

503

uint32_t ulCUs;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

504

uint32_t ulSustainableSOCPowerLimitLow;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

505

uint32_t ulSustainableSOCPowerLimitHigh;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

506

uint32_t ulMinSclkLow;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

507

uint32_t ulMinSclkHigh;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

509

uint32_t ulDClk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

510

uint32_t ulEClk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

511

uint32_t ulSustainableSclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

512

uint32_t ulSustainableCUs;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

521

uint32_t sclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

522

uint32_t mclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

523

uint32_t gfxclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

57

uint32_t value;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

58

uint32_t param1;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

619

uint32_t *power_saving_clock_max;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

62

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

620

uint32_t *power_saving_clock_min;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

623

uint32_t *od_settings_max;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

624

uint32_t *od_settings_min;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

639

uint32_t mclk_sclk_ratio;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

640

uint32_t sclk_mclk_delta;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

641

uint32_t vddc_vddci_delta;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

642

uint32_t min_vddc_for_pcie_gen2;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

663

uint32_t ulMinRPM;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

664

uint32_t ulMaxRPM;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

675

uint32_t ulCycleDelay; /* The time between two invocations of the fan control routine in microseconds. */

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

694

uint32_t ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

707

uint32_t ulMaxFanSCLKAcousticLimit; /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

708

uint32_t ulTargetGfxClk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

724

uint32_t SMC;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

725

uint32_t DMCU;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

726

uint32_t MC;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

727

uint32_t NB;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

744

uint32_t chip_family;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

745

uint32_t chip_id;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

746

uint32_t smu_version;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

752

uint32_t pp_table_version;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

756

uint32_t soft_pp_table_size;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

761

uint32_t num_vce_state_tables;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

766

uint32_t usec_timeout;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

781

uint32_t num_ps;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

784

uint32_t fan_ctrl_default_mode;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

786

uint32_t tmin;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

788

uint32_t ps_size;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

794

uint32_t feature_mask;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

798

uint32_t power_profile_mode;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

799

uint32_t default_power_profile_mode;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

800

uint32_t pstate_sclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

801

uint32_t pstate_mclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

803

uint32_t power_limit;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

804

uint32_t default_power_limit;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

805

uint32_t workload_mask;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

806

uint32_t workload_prority[Workload_Policy_Max];

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

807

uint32_t workload_setting[Workload_Policy_Max];

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

809

uint32_t pstate_sclk_peak;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

810

uint32_t pstate_mclk_peak;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

93

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

94

uint32_t values[];

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

98

uint32_t clk;

sys/dev/pci/drm/amd/pm/powerplay/inc/hwmgr.h

99

uint32_t v;

sys/dev/pci/drm/amd/pm/powerplay/inc/polaris10_pwrvirus.h

33

uint32_t data;

sys/dev/pci/drm/amd/pm/powerplay/inc/polaris10_pwrvirus.h

34

uint32_t reg;

sys/dev/pci/drm/amd/pm/powerplay/inc/polaris10_pwrvirus.h

40

uint32_t dfy_cntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/polaris10_pwrvirus.h

41

uint32_t dfy_addr_hi, dfy_addr_lo;

sys/dev/pci/drm/amd/pm/powerplay/inc/polaris10_pwrvirus.h

42

uint32_t dfy_size;

sys/dev/pci/drm/amd/pm/powerplay/inc/polaris10_pwrvirus.h

43

uint32_t dfy_data[];

sys/dev/pci/drm/amd/pm/powerplay/inc/power_state.h

144

uint32_t VCLK;

sys/dev/pci/drm/amd/pm/powerplay/inc/power_state.h

145

uint32_t DCLK;

sys/dev/pci/drm/amd/pm/powerplay/inc/power_state.h

152

uint32_t id;

sys/dev/pci/drm/amd/pm/powerplay/inc/ppinterrupt.h

36

unsigned src_id, const uint32_t *iv_entry);

sys/dev/pci/drm/amd/pm/powerplay/inc/ppinterrupt.h

42

uint32_t src_id; /* Registered interrupt id */

sys/dev/pci/drm/amd/pm/powerplay/inc/ppinterrupt.h

43

const uint32_t *iv_entry;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

148

uint32_t CurrLevel_ACP : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

149

uint32_t CurrLevel_ISP : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

150

uint32_t CurrLevel_VCN : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

151

uint32_t CurrLevel_LCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

152

uint32_t CurrLevel_MP0CLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

153

uint32_t CurrLevel_FCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

154

uint32_t CurrLevel_SOCCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

155

uint32_t CurrLevel_DCEFCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

157

uint32_t TargLevel_ACP : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

158

uint32_t TargLevel_ISP : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

159

uint32_t TargLevel_VCN : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

160

uint32_t TargLevel_LCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

161

uint32_t TargLevel_MP0CLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

162

uint32_t TargLevel_FCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

163

uint32_t TargLevel_SOCCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

164

uint32_t TargLevel_DCEFCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

166

uint32_t CurrLevel_SHUBCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

167

uint32_t TargLevel_SHUBCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

168

uint32_t InUlv : 1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

169

uint32_t InS0i2 : 1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

170

uint32_t InWhisperMode : 1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

171

uint32_t Reserved : 21;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

173

uint32_t Reserved2[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10.h

175

uint32_t FeatureStatus[NUM_FEATURES / 32];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10_driver_if.h

106

uint32_t Freq; /* In MHz */

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10_driver_if.h

107

uint32_t Vol; /* Millivolts with 2 fractional bits */

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10_driver_if.h

33

uint32_t numFractionalBits;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu10_driver_if.h

71

uint32_t MmHubPadding[7];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

289

uint32_t Enabled;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

290

uint32_t SlaveAddress;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

291

uint32_t ControllerPort;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

292

uint32_t ControllerName;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

294

uint32_t ThermalThrottler;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

295

uint32_t I2cProtocol;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

296

uint32_t I2cSpeed;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

300

uint32_t a;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

301

uint32_t b;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

302

uint32_t c;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

306

uint32_t m;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

307

uint32_t b;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

311

uint32_t a;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

312

uint32_t b;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

313

uint32_t c;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

363

uint32_t Version;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

366

uint32_t FeaturesToRun[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

392

uint32_t FitLimit;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

519

uint32_t DebugOverrides;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

536

uint32_t Reserved[11];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

538

uint32_t Padding32[3];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

607

uint32_t BoardReserved[10];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

610

uint32_t MmHubPadding[8];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

625

uint32_t MmHubPadding[8];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

670

uint32_t ThrottlerStatus ;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

677

uint32_t MmHubPadding[7];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

702

uint32_t MmHubPadding[7];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

717

uint32_t MmHubPadding[6];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

752

uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

753

uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

754

uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

756

uint32_t VInversion[AVFS_VOLTAGE_COUNT];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

763

uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

765

uint32_t EnabledAvfsModules;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

767

uint32_t MmHubPadding[7];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

781

uint32_t Gfx_PD_Data_limit_a;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

782

uint32_t Gfx_PD_Data_limit_b;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

783

uint32_t Gfx_PD_Data_limit_c;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

784

uint32_t Gfx_PD_Data_error_coeff;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

785

uint32_t Gfx_PD_Data_error_rate_coeff;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

796

uint32_t Soc_PD_Data_limit_a;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

797

uint32_t Soc_PD_Data_limit_b;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

798

uint32_t Soc_PD_Data_limit_c;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

799

uint32_t Soc_PD_Data_error_coeff;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

800

uint32_t Soc_PD_Data_error_rate_coeff;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

811

uint32_t Mem_PD_Data_limit_a;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

812

uint32_t Mem_PD_Data_limit_b;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

813

uint32_t Mem_PD_Data_limit_c;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

814

uint32_t Mem_PD_Data_error_coeff;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

815

uint32_t Mem_PD_Data_error_rate_coeff;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

826

uint32_t Fclk_PD_Data_limit_a;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

827

uint32_t Fclk_PD_Data_limit_b;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

828

uint32_t Fclk_PD_Data_limit_c;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

829

uint32_t Fclk_PD_Data_error_coeff;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h

830

uint32_t Fclk_PD_Data_error_rate_coeff;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

105

uint32_t Ki;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

108

uint32_t StatePrecision;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

109

uint32_t LfPrecision;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

110

uint32_t LfOffset;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

111

uint32_t MaxState;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

112

uint32_t MaxLfFraction;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

113

uint32_t StateShift;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

139

uint32_t Digest[5];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

140

uint32_t Version;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

141

uint32_t HeaderSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

142

uint32_t Flags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

143

uint32_t EntryPoint;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

144

uint32_t CodeSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

145

uint32_t ImageSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

147

uint32_t Rtos;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

148

uint32_t SoftRegisters;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

149

uint32_t DpmTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

150

uint32_t FanTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

151

uint32_t CacConfigTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

152

uint32_t CacStatusTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

154

uint32_t mcRegisterTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

156

uint32_t mcArbDramTimingTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

158

uint32_t PmFuseTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

159

uint32_t Globals;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

160

uint32_t Reserved[42];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7.h

161

uint32_t Signature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

122

uint32_t Ki;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

125

uint32_t StatePrecision;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

126

uint32_t LfPrecision;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

127

uint32_t LfOffset;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

128

uint32_t MaxState;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

129

uint32_t MaxLfFraction;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

130

uint32_t StateShift;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

136

uint32_t PercentageBusy;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

142

uint32_t SigmaDeltaAccum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

143

uint32_t SigmaDeltaOutput;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

144

uint32_t SigmaDeltaLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

146

uint32_t UtilizationSetpoint;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

168

uint32_t MinimumPerfSclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

194

uint32_t MaxAllowedFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

276

uint32_t AvgGpuPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

293

uint32_t RocPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

295

uint32_t last_power;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

296

uint32_t enableWinAvg;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

298

uint32_t lkg_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

302

uint32_t uvd_cac_dclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

303

uint32_t uvd_cac_vclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

304

uint32_t vce_cac_eclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

305

uint32_t samu_cac_samclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

306

uint32_t display_cac_dispclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

307

uint32_t acp_cac_aclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

308

uint32_t unb_cac;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

310

uint32_t WinTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

360

uint32_t RefClockFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

361

uint32_t PmTimerPeriod;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

362

uint32_t FeatureEnables;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

364

uint32_t PreVBlankGap;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

365

uint32_t VBlankTimeout;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

366

uint32_t TrainTimeGap;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

367

uint32_t MvddSwitchTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

368

uint32_t LongestAcpiTrainTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

369

uint32_t AcpiDelay;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

370

uint32_t G5TrainTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

371

uint32_t DelayMpllPwron;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

372

uint32_t VoltageChangeTimeout;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

374

uint32_t HandshakeDisables;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

386

uint32_t AverageGraphicsActivity;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

387

uint32_t AverageMemoryActivity;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

388

uint32_t AverageGioActivity;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

395

uint32_t DRAM_LOG_ADDR_H;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

396

uint32_t DRAM_LOG_ADDR_L;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

397

uint32_t DRAM_LOG_PHY_ADDR_H;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

398

uint32_t DRAM_LOG_PHY_ADDR_L;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

399

uint32_t DRAM_LOG_BUFF_SIZE;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

400

uint32_t UlvEnterCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

401

uint32_t UlvTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

402

uint32_t UcodeLoadStatus;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

406

uint32_t Reserved;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

412

uint32_t Digest[5];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

413

uint32_t Version;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

414

uint32_t HeaderSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

415

uint32_t Flags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

416

uint32_t EntryPoint;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

417

uint32_t CodeSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

418

uint32_t ImageSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

420

uint32_t Rtos;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

421

uint32_t SoftRegisters;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

422

uint32_t DpmTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

423

uint32_t FanTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

424

uint32_t CacConfigTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

425

uint32_t CacStatusTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

427

uint32_t mcRegisterTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

429

uint32_t mcArbDramTimingTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

431

uint32_t PmFuseTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

432

uint32_t Globals;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

433

uint32_t UvdDpmTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

434

uint32_t AcpDpmTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

435

uint32_t VceDpmTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

436

uint32_t SamuDpmTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

437

uint32_t UlvSettings;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

438

uint32_t Reserved[37];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

439

uint32_t Signature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

44

uint32_t high;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71.h

45

uint32_t low;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

100

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

101

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

105

uint32_t Reserved;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

112

uint32_t MinVddc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

113

uint32_t MinVddcPhases;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

114

uint32_t MinVddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

115

uint32_t MinMvdd;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

117

uint32_t MclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

138

uint32_t MpllFuncCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

139

uint32_t MpllFuncCntl_1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

140

uint32_t MpllFuncCntl_2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

141

uint32_t MpllAdFuncCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

142

uint32_t MpllDqFuncCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

143

uint32_t MclkPwrmgtCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

144

uint32_t DllCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

145

uint32_t MpllSs1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

146

uint32_t MpllSs2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

157

uint32_t DownThreshold;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

158

uint32_t UpThreshold;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

159

uint32_t Reserved;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

169

uint32_t McArbDramTiming;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

170

uint32_t McArbDramTiming2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

188

uint32_t VclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

189

uint32_t DclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

202

uint32_t Frequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

216

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

217

uint32_t MclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

218

uint32_t VclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

219

uint32_t DclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

220

uint32_t SamclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

221

uint32_t AclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

222

uint32_t EclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

246

uint32_t SystemFlags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

249

uint32_t SmioMaskVddcVid;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

250

uint32_t SmioMaskVddcPhase;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

251

uint32_t SmioMaskVddciVid;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

252

uint32_t SmioMaskMvddVid;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

254

uint32_t VddcLevelCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

255

uint32_t VddciLevelCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

256

uint32_t MvddLevelCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

267

uint32_t Reserved[5];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

276

uint32_t SclkStepSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

277

uint32_t Smio [SMU71_MAX_ENTRIES_SMIO];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

310

uint32_t DisplayCac;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

332

uint32_t BAPM_TEMP_GRADIENT;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

334

uint32_t LowSclkInterruptThreshold;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

335

uint32_t VddGfxReChkWait;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

360

uint32_t value[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

393

uint32_t RefreshPeriod;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

407

uint32_t PercentageBusy;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

413

uint32_t SigmaDeltaAccum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

414

uint32_t SigmaDeltaOutput;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

415

uint32_t SigmaDeltaLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

417

uint32_t UtilizationSetpoint;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

439

uint32_t MinimumPerfMclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

477

uint32_t UlvAbortedCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

478

uint32_t UlvTimeStamp;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

489

uint32_t VddGfxEnteredCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

49

uint32_t MinVddc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

490

uint32_t VddGfxAbortedCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

496

uint32_t SavedInterruptMask[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

50

uint32_t MinVddcPhases;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

52

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

559

uint32_t version;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

560

uint32_t asic_id;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

563

uint32_t total_size;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

564

uint32_t num_of_entries;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

568

uint32_t filler_1[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

577

uint32_t BufferSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

578

uint32_t SamplesLogged;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

579

uint32_t SampleSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

58

uint32_t CgSpllFuncCntl3;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

580

uint32_t AddrL;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

581

uint32_t AddrH;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

59

uint32_t CgSpllFuncCntl4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

592

uint32_t temperature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

593

uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

594

uint32_t filler[4];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

60

uint32_t SpllSpreadSpectrum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

600

uint32_t VddcTotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

601

uint32_t VddcLeakagePower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

602

uint32_t VddcConstantPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

603

uint32_t VddcGfxDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

604

uint32_t VddcUvdDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

605

uint32_t VddcVceDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

606

uint32_t VddcAcpDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

607

uint32_t VddcPcieDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

608

uint32_t VddcDceDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

609

uint32_t VddcCurrent;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

61

uint32_t SpllSpreadSpectrum2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

610

uint32_t VddcVoltage;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

611

uint32_t VddciTotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

612

uint32_t VddciLeakagePower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

613

uint32_t VddciConstantPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

614

uint32_t VddciDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

615

uint32_t Vddr1TotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

616

uint32_t Vddr1LeakagePower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

617

uint32_t Vddr1ConstantPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

618

uint32_t Vddr1DynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

619

uint32_t spare[8];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

62

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

620

uint32_t temperature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

63

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

78

uint32_t Flags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

79

uint32_t MinVddc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

80

uint32_t MinVddcPhases;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

81

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

86

uint32_t CgSpllFuncCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

87

uint32_t CgSpllFuncCntl2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

88

uint32_t CgSpllFuncCntl3;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

89

uint32_t CgSpllFuncCntl4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

90

uint32_t SpllSpreadSpectrum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

91

uint32_t SpllSpreadSpectrum2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

92

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu71_discrete.h

93

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

208

uint32_t Ki;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

211

uint32_t StatePrecision;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

212

uint32_t LfPrecision;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

213

uint32_t LfOffset;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

214

uint32_t MaxState;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

215

uint32_t MaxLfFraction;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

216

uint32_t StateShift;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

222

uint32_t PercentageBusy;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

228

uint32_t SigmaDeltaAccum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

229

uint32_t SigmaDeltaOutput;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

230

uint32_t SigmaDeltaLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

232

uint32_t UtilizationSetpoint;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

254

uint32_t MinimumPerfSclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

280

uint32_t MaxAllowedFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

282

uint32_t FilteredSclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

283

uint32_t LastSclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

284

uint32_t FilteredSclkFrequencyCnt;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

379

uint32_t TotalGpuPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

380

uint32_t TdcCurrent;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

391

uint32_t WinTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

398

uint32_t VddcCurrentTelemetry;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

399

uint32_t VddGfxCurrentTelemetry;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

400

uint32_t VddcPowerTelemetry;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

401

uint32_t VddGfxPowerTelemetry;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

402

uint32_t VddciPowerTelemetry;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

404

uint32_t VddcPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

405

uint32_t VddGfxPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

406

uint32_t VddciPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

408

uint32_t TelemetryCurrent[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

409

uint32_t TelemetryVoltage[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

410

uint32_t TelemetryPower[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

434

uint32_t Alpha;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

459

uint32_t RefClockFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

460

uint32_t PmTimerPeriod;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

461

uint32_t FeatureEnables;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

463

uint32_t PreVBlankGap;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

464

uint32_t VBlankTimeout;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

465

uint32_t TrainTimeGap;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

467

uint32_t MvddSwitchTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

468

uint32_t LongestAcpiTrainTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

469

uint32_t AcpiDelay;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

470

uint32_t G5TrainTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

471

uint32_t DelayMpllPwron;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

472

uint32_t VoltageChangeTimeout;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

474

uint32_t HandshakeDisables;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

486

uint32_t AverageGraphicsActivity;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

487

uint32_t AverageMemoryActivity;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

488

uint32_t AverageGioActivity;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

500

uint32_t DRAM_LOG_ADDR_H;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

501

uint32_t DRAM_LOG_ADDR_L;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

502

uint32_t DRAM_LOG_PHY_ADDR_H;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

503

uint32_t DRAM_LOG_PHY_ADDR_L;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

504

uint32_t DRAM_LOG_BUFF_SIZE;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

505

uint32_t UlvEnterCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

506

uint32_t UlvTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

507

uint32_t UcodeLoadStatus;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

508

uint32_t Reserved[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

515

uint32_t Digest[5];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

516

uint32_t Version;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

517

uint32_t HeaderSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

518

uint32_t Flags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

519

uint32_t EntryPoint;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

520

uint32_t CodeSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

521

uint32_t ImageSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

523

uint32_t Rtos;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

524

uint32_t SoftRegisters;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

525

uint32_t DpmTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

526

uint32_t FanTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

527

uint32_t CacConfigTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

528

uint32_t CacStatusTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

529

uint32_t mcRegisterTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

530

uint32_t mcArbDramTimingTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

531

uint32_t PmFuseTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

532

uint32_t Globals;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

533

uint32_t ClockStretcherTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

534

uint32_t Reserved[41];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

535

uint32_t Signature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

73

uint32_t Cac;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

74

uint32_t DynPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

75

uint32_t TotalCurrent;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

76

uint32_t TotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

83

uint32_t value;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

90

uint32_t high;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72.h

91

uint32_t low;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

100

uint32_t Reserved;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

107

uint32_t MinMvdd;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

109

uint32_t MclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

130

uint32_t MpllFuncCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

131

uint32_t MpllFuncCntl_1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

132

uint32_t MpllFuncCntl_2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

133

uint32_t MpllAdFuncCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

134

uint32_t MpllDqFuncCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

135

uint32_t MclkPwrmgtCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

136

uint32_t DllCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

137

uint32_t MpllSs1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

138

uint32_t MpllSs2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

148

uint32_t DownThreshold;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

149

uint32_t UpThreshold;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

150

uint32_t Reserved;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

157

uint32_t McArbDramTiming;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

158

uint32_t McArbDramTiming2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

173

uint32_t VclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

174

uint32_t DclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

185

uint32_t Frequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

194

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

195

uint32_t MclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

196

uint32_t VclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

197

uint32_t DclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

198

uint32_t SamclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

199

uint32_t AclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

200

uint32_t EclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

222

uint32_t SystemFlags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

225

uint32_t VRConfig;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

226

uint32_t SmioMask1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

227

uint32_t SmioMask2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

231

uint32_t VddcLevelCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

232

uint32_t VddciLevelCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

233

uint32_t VddGfxLevelCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

234

uint32_t MvddLevelCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

262

uint32_t Reserved[4];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

276

uint32_t SclkStepSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

277

uint32_t Smio[SMU72_MAX_ENTRIES_SMIO];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

333

uint32_t BAPM_TEMP_GRADIENT;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

335

uint32_t LowSclkInterruptThreshold;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

336

uint32_t VddGfxReChkWait;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

364

uint32_t value[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

396

uint32_t RefreshPeriod;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

409

uint32_t PercentageBusy;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

415

uint32_t SigmaDeltaAccum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

416

uint32_t SigmaDeltaOutput;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

417

uint32_t SigmaDeltaLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

419

uint32_t UtilizationSetpoint;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

441

uint32_t MinimumPerfMclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

487

uint32_t UlvAbortedCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

488

uint32_t UlvTimeStamp;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

494

uint32_t GPU_DBG[3];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

495

uint32_t MEC_BaseAddress_Hi;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

496

uint32_t MEC_BaseAddress_Lo;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

497

uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

498

uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

499

uint32_t CP_INT_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

50

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

510

uint32_t VddGfxEnteredCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

511

uint32_t VddGfxAbortedCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

513

uint32_t VddGfxVid;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

524

uint32_t FilteredIddc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

525

uint32_t IddcLimit;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

526

uint32_t IddcHyst;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

536

uint32_t FilteredPkgPwr;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

537

uint32_t Limit;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

538

uint32_t Hyst;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

539

uint32_t LimitFromDriver;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

546

uint32_t source_powers[SMU72_DTE_SOURCES];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

547

uint32_t source_powers_last[SMU72_DTE_SOURCES];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

56

uint32_t CgSpllFuncCntl3;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

566

uint32_t measured_temperature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

57

uint32_t CgSpllFuncCntl4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

573

uint32_t SavedInterruptMask[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

58

uint32_t SpllSpreadSpectrum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

59

uint32_t SpllSpreadSpectrum2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

60

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

61

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

626

uint32_t version;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

627

uint32_t asic_id;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

630

uint32_t total_size;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

631

uint32_t num_of_entries;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

635

uint32_t filler_1[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

644

uint32_t BufferSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

645

uint32_t SamplesLogged;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

646

uint32_t SampleSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

647

uint32_t AddrL;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

648

uint32_t AddrH;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

656

uint32_t temperature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

657

uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

663

uint32_t VddcTotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

664

uint32_t VddcLeakagePower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

665

uint32_t VddcConstantPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

666

uint32_t VddcGfxDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

667

uint32_t VddcUvdDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

668

uint32_t VddcVceDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

669

uint32_t VddcAcpDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

670

uint32_t VddcPcieDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

671

uint32_t VddcDceDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

672

uint32_t VddcCurrent;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

673

uint32_t VddcVoltage;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

674

uint32_t VddciTotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

675

uint32_t VddciLeakagePower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

676

uint32_t VddciConstantPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

677

uint32_t VddciDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

678

uint32_t Vddr1TotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

679

uint32_t Vddr1LeakagePower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

680

uint32_t Vddr1ConstantPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

681

uint32_t Vddr1DynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

682

uint32_t spare[4];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

683

uint32_t temperature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

694

uint32_t P_scalar_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

695

uint32_t P_calc_max;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

696

uint32_t P_calc_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

699

uint32_t I_calc_max;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

700

uint32_t I_calc_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

701

uint32_t I_calc_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

702

uint32_t V_calc_noload_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

703

uint32_t V_calc_load_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

704

uint32_t V_calc_noload_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

705

uint32_t P_meas_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

706

uint32_t V_meas_noload_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

707

uint32_t V_meas_load_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

708

uint32_t I_meas_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

709

uint32_t P_meas_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

710

uint32_t V_meas_noload_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

711

uint32_t V_meas_load_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

712

uint32_t I_meas_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

721

uint32_t P_vddci_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

722

uint32_t P_vddr1_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

723

uint32_t P_nte1_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

724

uint32_t PkgPwr_max;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

725

uint32_t PkgPwr_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

726

uint32_t MclkSwitchingTime_max;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

727

uint32_t MclkSwitchingTime_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

728

uint32_t FanPwm_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

729

uint32_t FanRpm_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

731

uint32_t AccCnt;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

75

uint32_t Flags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

77

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

82

uint32_t CgSpllFuncCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

83

uint32_t CgSpllFuncCntl2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

84

uint32_t CgSpllFuncCntl3;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

85

uint32_t CgSpllFuncCntl4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

86

uint32_t SpllSpreadSpectrum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

87

uint32_t SpllSpreadSpectrum2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

88

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

89

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

95

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu72_discrete.h

96

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

199

uint32_t Ki;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

202

uint32_t StatePrecision;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

204

uint32_t LfPrecision;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

205

uint32_t LfOffset;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

206

uint32_t MaxState;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

207

uint32_t MaxLfFraction;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

208

uint32_t StateShift;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

214

uint32_t PercentageBusy;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

220

uint32_t SigmaDeltaAccum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

221

uint32_t SigmaDeltaOutput;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

222

uint32_t SigmaDeltaLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

224

uint32_t UtilizationSetpoint;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

246

uint32_t MinimumPerfSclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

272

uint32_t MaxAllowedFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

274

uint32_t FilteredSclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

275

uint32_t LastSclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

276

uint32_t FilteredSclkFrequencyCnt;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

282

uint32_t LedAndMask;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

286

uint32_t CurrentFps;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

287

uint32_t FilteredFps;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

288

uint32_t FrameCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

289

uint32_t FrameCountLast;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

310

typedef uint32_t SMU_VoltageLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

392

uint32_t GpuPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

394

uint32_t VddcPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

395

uint32_t VddcVoltage;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

396

uint32_t VddcCurrent;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

398

uint32_t MvddPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

399

uint32_t MvddVoltage;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

400

uint32_t MvddCurrent;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

402

uint32_t RocPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

431

uint32_t RefClockFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

432

uint32_t PmTimerPeriod;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

433

uint32_t FeatureEnables;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

435

uint32_t PreVBlankGap;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

436

uint32_t VBlankTimeout;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

437

uint32_t TrainTimeGap;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

439

uint32_t MvddSwitchTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

440

uint32_t LongestAcpiTrainTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

441

uint32_t AcpiDelay;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

442

uint32_t G5TrainTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

443

uint32_t DelayMpllPwron;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

444

uint32_t VoltageChangeTimeout;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

446

uint32_t HandshakeDisables;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

458

uint32_t AverageGraphicsActivity;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

459

uint32_t AverageMemoryActivity;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

460

uint32_t AverageGioActivity;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

472

uint32_t DRAM_LOG_ADDR_H;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

473

uint32_t DRAM_LOG_ADDR_L;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

474

uint32_t DRAM_LOG_PHY_ADDR_H;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

475

uint32_t DRAM_LOG_PHY_ADDR_L;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

476

uint32_t DRAM_LOG_BUFF_SIZE;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

477

uint32_t UlvEnterCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

478

uint32_t UlvTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

479

uint32_t UcodeLoadStatus;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

480

uint32_t Reserved[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

487

uint32_t Digest[5];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

488

uint32_t Version;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

489

uint32_t HeaderSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

490

uint32_t Flags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

491

uint32_t EntryPoint;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

492

uint32_t CodeSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

493

uint32_t ImageSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

495

uint32_t Rtos;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

496

uint32_t SoftRegisters;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

497

uint32_t DpmTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

498

uint32_t FanTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

499

uint32_t CacConfigTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

500

uint32_t CacStatusTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

503

uint32_t mcRegisterTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

506

uint32_t mcArbDramTimingTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

511

uint32_t PmFuseTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

512

uint32_t Globals;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

513

uint32_t ClockStretcherTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

514

uint32_t Reserved[41];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

515

uint32_t Signature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

64

uint32_t Cac;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

65

uint32_t DynPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

66

uint32_t TotalCurrent;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

67

uint32_t TotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

74

uint32_t value;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

81

uint32_t high;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73.h

82

uint32_t low;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

102

uint32_t MinVoltage;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

103

uint32_t MinMvdd;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

105

uint32_t MclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

129

uint32_t DownThreshold;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

130

uint32_t UpThreshold;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

131

uint32_t Reserved;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

139

uint32_t McArbDramTiming;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

140

uint32_t McArbDramTiming2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

157

uint32_t VclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

158

uint32_t DclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

159

uint32_t MinVoltage;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

169

uint32_t Frequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

170

uint32_t MinVoltage;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

178

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

179

uint32_t MclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

180

uint32_t VclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

181

uint32_t DclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

182

uint32_t SamclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

183

uint32_t AclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

184

uint32_t EclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

206

uint32_t SystemFlags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

209

uint32_t VRConfig;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

210

uint32_t SmioMask1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

211

uint32_t SmioMask2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

215

uint32_t MvddLevelCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

236

uint32_t Reserved[4];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

250

uint32_t SclkStepSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

251

uint32_t Smio[SMU73_MAX_ENTRIES_SMIO];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

320

uint32_t GeminiApertureHigh;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

321

uint32_t GeminiApertureLow;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

331

uint32_t spare123[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

341

uint32_t BAPM_TEMP_GRADIENT;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

343

uint32_t LowSclkInterruptThreshold;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

344

uint32_t VddGfxReChkWait;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

376

uint32_t RefreshPeriod;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

391

uint32_t PercentageBusy;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

397

uint32_t SigmaDeltaAccum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

398

uint32_t SigmaDeltaOutput;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

399

uint32_t SigmaDeltaLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

401

uint32_t UtilizationSetpoint;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

423

uint32_t MinimumPerfMclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

45

uint32_t MinVoltage;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

469

uint32_t UlvAbortedCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

47

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

470

uint32_t UlvTimeStamp;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

476

uint32_t GPU_DBG[3];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

477

uint32_t MEC_BaseAddress_Hi;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

478

uint32_t MEC_BaseAddress_Lo;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

479

uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

480

uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

481

uint32_t CP_INT_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

492

uint32_t VddGfxEnteredCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

493

uint32_t VddGfxAbortedCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

495

uint32_t VddGfxVid;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

506

uint32_t FilteredIddc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

507

uint32_t IddcLimit;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

508

uint32_t IddcHyst;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

518

uint32_t FilteredPkgPwr;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

519

uint32_t Limit;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

52

uint32_t CgSpllFuncCntl3;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

520

uint32_t Hyst;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

521

uint32_t LimitFromDriver;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

528

uint32_t source_powers[SMU73_DTE_SOURCES];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

529

uint32_t source_powers_last[SMU73_DTE_SOURCES];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

53

uint32_t CgSpllFuncCntl4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

54

uint32_t SpllSpreadSpectrum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

548

uint32_t measured_temperature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

55

uint32_t SpllSpreadSpectrum2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

555

uint32_t SavedInterruptMask[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

56

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

567

uint32_t b;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

57

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

635

uint32_t PsmCharzFreq;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

640

uint32_t EnabledAvfsModules;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

646

uint32_t version;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

647

uint32_t asic_id;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

650

uint32_t total_size;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

651

uint32_t num_of_entries;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

655

uint32_t filler_1[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

664

uint32_t BufferSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

665

uint32_t SamplesLogged;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

666

uint32_t SampleSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

667

uint32_t AddrL;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

668

uint32_t AddrH;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

676

uint32_t temperature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

677

uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

683

uint32_t VddcTotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

684

uint32_t VddcLeakagePower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

685

uint32_t VddcConstantPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

686

uint32_t VddcGfxDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

687

uint32_t VddcUvdDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

688

uint32_t VddcVceDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

689

uint32_t VddcAcpDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

690

uint32_t VddcPcieDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

691

uint32_t VddcDceDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

692

uint32_t VddcCurrent;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

693

uint32_t VddcVoltage;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

694

uint32_t VddciTotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

695

uint32_t VddciLeakagePower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

696

uint32_t VddciConstantPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

697

uint32_t VddciDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

698

uint32_t Vddr1TotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

699

uint32_t Vddr1LeakagePower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

700

uint32_t Vddr1ConstantPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

701

uint32_t Vddr1DynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

702

uint32_t spare[4];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

703

uint32_t temperature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

71

uint32_t Flags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

713

uint32_t T_hbm_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

716

uint32_t I_calc_max;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

717

uint32_t I_calc_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

718

uint32_t P_meas_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

719

uint32_t V_meas_load_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

72

uint32_t MinVoltage;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

720

uint32_t I_meas_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

721

uint32_t P_meas_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

722

uint32_t V_meas_load_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

723

uint32_t I_meas_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

73

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

731

uint32_t P_roc_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

732

uint32_t PkgPwr_max;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

733

uint32_t PkgPwr_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

734

uint32_t MclkSwitchingTime_max;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

735

uint32_t MclkSwitchingTime_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

736

uint32_t FanPwm_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

737

uint32_t FanRpm_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

738

uint32_t Gfx_busy_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

739

uint32_t Mc_busy_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

740

uint32_t Fps_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

742

uint32_t AccCnt;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

78

uint32_t CgSpllFuncCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

79

uint32_t CgSpllFuncCntl2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

80

uint32_t CgSpllFuncCntl3;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

81

uint32_t CgSpllFuncCntl4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

82

uint32_t SpllSpreadSpectrum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

83

uint32_t SpllSpreadSpectrum2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

84

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

85

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

91

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

92

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h

96

uint32_t Reserved;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

100

uint32_t TotalCurrent;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

101

uint32_t TotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

108

uint32_t value;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

115

uint32_t high;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

116

uint32_t low;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

235

uint32_t Ki;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

238

uint32_t StatePrecision;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

239

uint32_t LfPrecision;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

240

uint32_t LfOffset;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

241

uint32_t MaxState;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

242

uint32_t MaxLfFraction;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

243

uint32_t StateShift;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

249

uint32_t PercentageBusy;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

255

uint32_t SigmaDeltaAccum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

256

uint32_t SigmaDeltaOutput;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

257

uint32_t SigmaDeltaLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

259

uint32_t UtilizationSetpoint;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

281

uint32_t MinimumPerfSclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

307

uint32_t MaxAllowedFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

309

uint32_t FilteredSclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

310

uint32_t LastSclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

311

uint32_t FilteredSclkFrequencyCnt;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

318

uint32_t CurrentFps;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

319

uint32_t FilteredFps;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

320

uint32_t FrameCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

321

uint32_t FrameCountLast;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

342

typedef uint32_t SMU_VoltageLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

424

uint32_t TotalGpuPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

425

uint32_t TdcCurrent;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

436

uint32_t WinTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

443

uint32_t VddcCurrentTelemetry;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

444

uint32_t VddGfxCurrentTelemetry;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

445

uint32_t VddcPowerTelemetry;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

446

uint32_t VddGfxPowerTelemetry;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

447

uint32_t VddciPowerTelemetry;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

449

uint32_t VddcPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

450

uint32_t VddGfxPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

451

uint32_t VddciPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

453

uint32_t TelemetryCurrent[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

454

uint32_t TelemetryVoltage[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

455

uint32_t TelemetryPower[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

479

uint32_t Alpha;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

503

uint32_t RefClockFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

504

uint32_t PmTimerPeriod;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

505

uint32_t FeatureEnables;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

507

uint32_t PreVBlankGap;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

508

uint32_t VBlankTimeout;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

509

uint32_t TrainTimeGap;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

511

uint32_t MvddSwitchTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

512

uint32_t LongestAcpiTrainTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

513

uint32_t AcpiDelay;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

514

uint32_t G5TrainTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

515

uint32_t DelayMpllPwron;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

516

uint32_t VoltageChangeTimeout;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

518

uint32_t HandshakeDisables;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

530

uint32_t AverageGraphicsActivity;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

531

uint32_t AverageMemoryActivity;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

532

uint32_t AverageGioActivity;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

544

uint32_t DRAM_LOG_ADDR_H;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

545

uint32_t DRAM_LOG_ADDR_L;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

546

uint32_t DRAM_LOG_PHY_ADDR_H;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

547

uint32_t DRAM_LOG_PHY_ADDR_L;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

548

uint32_t DRAM_LOG_BUFF_SIZE;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

549

uint32_t UlvEnterCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

550

uint32_t UlvTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

551

uint32_t UcodeLoadStatus;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

552

uint32_t AllowMvddSwitch;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

560

uint32_t Digest[5];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

561

uint32_t Version;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

562

uint32_t HeaderSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

563

uint32_t Flags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

564

uint32_t EntryPoint;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

565

uint32_t CodeSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

566

uint32_t ImageSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

568

uint32_t Rtos;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

569

uint32_t SoftRegisters;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

570

uint32_t DpmTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

571

uint32_t FanTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

572

uint32_t CacConfigTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

573

uint32_t CacStatusTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

575

uint32_t mcRegisterTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

577

uint32_t mcArbDramTimingTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

579

uint32_t PmFuseTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

580

uint32_t Globals;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

581

uint32_t ClockStretcherTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

582

uint32_t VftTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

583

uint32_t Reserved1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

584

uint32_t AvfsTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

585

uint32_t AvfsCksOffGbvTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

586

uint32_t AvfsMeanNSigma;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

587

uint32_t AvfsSclkOffsetTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

588

uint32_t Reserved[16];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

589

uint32_t Signature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

807

uint32_t spare;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

817

uint32_t Aconstant[3];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

98

uint32_t Cac;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74.h

99

uint32_t DynPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

106

uint32_t Flags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

108

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

113

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

114

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

122

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

123

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

135

uint32_t MinMvdd;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

137

uint32_t MclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

161

uint32_t DownThreshold;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

162

uint32_t UpThreshold;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

170

uint32_t McArbDramTiming;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

171

uint32_t McArbDramTiming2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

185

uint32_t VclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

186

uint32_t DclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

196

uint32_t Frequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

205

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

206

uint32_t MclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

207

uint32_t VclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

208

uint32_t DclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

209

uint32_t SamclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

210

uint32_t AclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

211

uint32_t EclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

228

uint32_t b;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

242

uint32_t SystemFlags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

244

uint32_t VRConfig;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

245

uint32_t SmioMask1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

246

uint32_t SmioMask2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

250

uint32_t MvddLevelCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

280

uint32_t Reserved[1];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

295

uint32_t SclkStepSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

296

uint32_t Smio[SMU74_MAX_ENTRIES_SMIO];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

354

uint32_t LowSclkInterruptThreshold;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

355

uint32_t VddGfxReChkWait;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

367

uint32_t CurrSclkPllRange;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

391

uint32_t RefreshPeriod;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

404

uint32_t PercentageBusy;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

410

uint32_t SigmaDeltaAccum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

411

uint32_t SigmaDeltaOutput;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

412

uint32_t SigmaDeltaLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

414

uint32_t UtilizationSetpoint;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

436

uint32_t MinimumPerfMclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

478

uint32_t UlvAbortedCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

479

uint32_t UlvTimeStamp;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

485

uint32_t GPU_DBG[3];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

486

uint32_t MEC_BaseAddress_Hi;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

487

uint32_t MEC_BaseAddress_Lo;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

488

uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

489

uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

490

uint32_t CP_INT_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

501

uint32_t VddGfxEnteredCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

502

uint32_t VddGfxAbortedCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

504

uint32_t VddGfxVid;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

515

uint32_t FilteredIddc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

516

uint32_t IddcLimit;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

517

uint32_t IddcHyst;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

527

uint32_t FilteredPkgPwr;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

528

uint32_t Limit;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

529

uint32_t Hyst;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

530

uint32_t LimitFromDriver;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

537

uint32_t source_powers[SMU74_DTE_SOURCES];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

538

uint32_t source_powers_last[SMU74_DTE_SOURCES];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

557

uint32_t measured_temperature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

564

uint32_t SavedInterruptMask[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

616

uint32_t PsmCharzFreq;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

621

uint32_t EnabledAvfsModules;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

627

uint32_t version;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

628

uint32_t asic_id;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

631

uint32_t total_size;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

632

uint32_t num_of_entries;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

636

uint32_t filler_1[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

645

uint32_t BufferSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

646

uint32_t SamplesLogged;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

647

uint32_t SampleSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

648

uint32_t AddrL;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

649

uint32_t AddrH;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

660

uint32_t temperature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

661

uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

667

uint32_t VddcTotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

668

uint32_t VddcLeakagePower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

669

uint32_t VddcConstantPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

670

uint32_t VddcGfxDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

671

uint32_t VddcUvdDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

672

uint32_t VddcVceDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

673

uint32_t VddcAcpDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

674

uint32_t VddcPcieDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

675

uint32_t VddcDceDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

676

uint32_t VddcCurrent;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

677

uint32_t VddcVoltage;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

678

uint32_t VddciTotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

679

uint32_t VddciLeakagePower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

68

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

680

uint32_t VddciConstantPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

681

uint32_t VddciDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

682

uint32_t Vddr1TotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

683

uint32_t Vddr1LeakagePower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

684

uint32_t Vddr1ConstantPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

685

uint32_t Vddr1DynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

686

uint32_t spare[4];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

687

uint32_t temperature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

697

uint32_t P_scalar_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

698

uint32_t P_calc_max;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

699

uint32_t P_calc_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

701

uint32_t I_calc_max;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

702

uint32_t I_calc_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

703

uint32_t I_calc_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

704

uint32_t V_calc_noload_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

705

uint32_t V_calc_load_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

706

uint32_t V_calc_noload_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

707

uint32_t P_meas_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

708

uint32_t V_meas_noload_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

709

uint32_t V_meas_load_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

710

uint32_t I_meas_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

711

uint32_t P_meas_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

712

uint32_t V_meas_noload_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

713

uint32_t V_meas_load_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

714

uint32_t I_meas_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

721

uint32_t P_vddci_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

722

uint32_t P_vddr1_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

723

uint32_t P_nte1_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

724

uint32_t PkgPwr_max;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

725

uint32_t PkgPwr_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

726

uint32_t MclkSwitchingTime_max;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

727

uint32_t MclkSwitchingTime_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

728

uint32_t FanPwm_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

729

uint32_t FanRpm_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

731

uint32_t AccCnt;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

88

uint32_t CgSpllFuncCntl3;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

89

uint32_t CgSpllFuncCntl4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

90

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h

91

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

169

uint32_t Ki;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

172

uint32_t StatePrecision;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

173

uint32_t LfPrecision;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

174

uint32_t LfOffset;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

175

uint32_t MaxState;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

176

uint32_t MaxLfFraction;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

177

uint32_t StateShift;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

183

uint32_t PercentageBusy;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

189

uint32_t SigmaDeltaAccum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

190

uint32_t SigmaDeltaOutput;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

191

uint32_t SigmaDeltaLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

193

uint32_t UtilizationSetpoint;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

215

uint32_t MinimumPerfSclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

241

uint32_t MaxAllowedFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

243

uint32_t FilteredSclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

244

uint32_t LastSclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

245

uint32_t FilteredSclkFrequencyCnt;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

257

uint32_t CurrentFps;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

258

uint32_t FilteredFps;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

259

uint32_t FrameCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

260

uint32_t FrameCountLast;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

281

typedef uint32_t SMU_VoltageLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

29

uint32_t high;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

30

uint32_t low;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

356

uint32_t GpuPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

358

uint32_t VddcPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

359

uint32_t VddcVoltage;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

360

uint32_t VddcCurrent;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

362

uint32_t VddciPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

363

uint32_t VddciVoltage;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

364

uint32_t VddciCurrent;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

366

uint32_t RocPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

397

uint32_t RefClockFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

398

uint32_t PmTimerPeriod;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

399

uint32_t FeatureEnables;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

401

uint32_t PreVBlankGap;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

402

uint32_t VBlankTimeout;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

403

uint32_t TrainTimeGap;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

404

uint32_t MvddSwitchTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

405

uint32_t LongestAcpiTrainTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

406

uint32_t AcpiDelay;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

407

uint32_t G5TrainTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

408

uint32_t DelayMpllPwron;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

409

uint32_t VoltageChangeTimeout;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

411

uint32_t HandshakeDisables;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

423

uint32_t AverageGraphicsActivity;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

424

uint32_t AverageMemoryActivity;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

425

uint32_t AverageGioActivity;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

437

uint32_t DRAM_LOG_ADDR_H;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

438

uint32_t DRAM_LOG_ADDR_L;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

439

uint32_t DRAM_LOG_PHY_ADDR_H;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

440

uint32_t DRAM_LOG_PHY_ADDR_L;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

441

uint32_t DRAM_LOG_BUFF_SIZE;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

442

uint32_t UlvEnterCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

443

uint32_t UlvTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

444

uint32_t UcodeLoadStatus;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

445

uint32_t AllowMvddSwitch;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

453

uint32_t Digest[5];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

454

uint32_t Version;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

455

uint32_t HeaderSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

456

uint32_t Flags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

457

uint32_t EntryPoint;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

458

uint32_t CodeSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

459

uint32_t ImageSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

461

uint32_t Rtos;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

462

uint32_t SoftRegisters;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

463

uint32_t DpmTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

464

uint32_t FanTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

465

uint32_t CacConfigTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

466

uint32_t CacStatusTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

467

uint32_t mcRegisterTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

468

uint32_t mcArbDramTimingTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

469

uint32_t PmFuseTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

470

uint32_t Globals;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

471

uint32_t ClockStretcherTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

472

uint32_t VftTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

473

uint32_t Reserved1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

474

uint32_t AvfsCksOff_AvfsGbvTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

475

uint32_t AvfsCksOff_BtcGbvTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

476

uint32_t MM_AvfsTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

477

uint32_t PowerSharingTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

478

uint32_t AvfsTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

479

uint32_t AvfsCksOffGbvTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

480

uint32_t AvfsMeanNSigma;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

481

uint32_t AvfsSclkOffsetTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

482

uint32_t Reserved[12];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

483

uint32_t Signature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

700

uint32_t spare;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

735

uint32_t Aconstant[3];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

750

uint32_t EnergyCounter;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75.h

751

uint32_t EngeryThreshold;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

111

uint32_t Flags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

113

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

118

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

119

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

127

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

128

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

140

uint32_t MinMvdd;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

142

uint32_t MclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

171

uint32_t DownThreshold;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

172

uint32_t UpThreshold;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

182

uint32_t McArbDramTiming;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

183

uint32_t McArbDramTiming2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

184

uint32_t McArbBurstTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

185

uint32_t McArbRfshRate;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

186

uint32_t McArbMisc3;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

199

uint32_t VclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

200

uint32_t DclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

211

uint32_t Frequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

220

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

221

uint32_t MclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

222

uint32_t VclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

223

uint32_t DclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

224

uint32_t SamclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

225

uint32_t AclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

226

uint32_t EclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

246

uint32_t SystemFlags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

248

uint32_t VRConfig;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

249

uint32_t SmioMask1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

250

uint32_t SmioMask2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

254

uint32_t MvddLevelCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

285

uint32_t Reserved;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

300

uint32_t SclkStepSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

301

uint32_t Smio [SMU75_MAX_ENTRIES_SMIO];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

359

uint32_t LowSclkInterruptThreshold;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

360

uint32_t VddGfxReChkWait;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

372

uint32_t CurrSclkPllRange;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

396

uint32_t RefreshPeriod;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

410

uint32_t PercentageBusy;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

416

uint32_t SigmaDeltaAccum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

417

uint32_t SigmaDeltaOutput;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

418

uint32_t SigmaDeltaLevel;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

420

uint32_t UtilizationSetpoint;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

442

uint32_t MinimumPerfMclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

475

uint32_t HbmTempRegBackup;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

489

uint32_t UlvAbortedCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

490

uint32_t UlvTimeStamp;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

496

uint32_t GPU_DBG[3];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

497

uint32_t MEC_BaseAddress_Hi;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

498

uint32_t MEC_BaseAddress_Lo;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

499

uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

500

uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

501

uint32_t CP_INT_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

512

uint32_t VddGfxEnteredCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

513

uint32_t VddGfxAbortedCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

515

uint32_t VddGfxVid;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

526

uint32_t FilteredIddc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

527

uint32_t IddcLimit;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

528

uint32_t IddcHyst;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

538

uint32_t FilteredPkgPwr;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

539

uint32_t Limit;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

540

uint32_t Hyst;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

541

uint32_t LimitFromDriver;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

546

uint32_t EnergyCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

547

uint32_t PSACTCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

557

uint32_t source_powers[SMU75_DTE_SOURCES];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

558

uint32_t source_powers_last[SMU75_DTE_SOURCES];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

577

uint32_t measured_temperature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

584

uint32_t SavedInterruptMask[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

642

uint32_t PsmCharzFreq;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

647

uint32_t EnabledAvfsModules;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

655

uint32_t version;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

656

uint32_t asic_id;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

659

uint32_t total_size;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

66

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

660

uint32_t num_of_entries;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

664

uint32_t filler_1[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

673

uint32_t BufferSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

674

uint32_t SamplesLogged;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

675

uint32_t SampleSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

676

uint32_t AddrL;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

677

uint32_t AddrH;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

688

uint32_t temperature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

689

uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

695

uint32_t VddcTotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

696

uint32_t VddcLeakagePower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

697

uint32_t VddcConstantPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

698

uint32_t VddcGfxDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

699

uint32_t VddcUvdDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

700

uint32_t VddcVceDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

701

uint32_t VddcAcpDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

702

uint32_t VddcPcieDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

703

uint32_t VddcDceDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

704

uint32_t VddcCurrent;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

705

uint32_t VddcVoltage;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

706

uint32_t VddciTotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

707

uint32_t VddciLeakagePower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

708

uint32_t VddciConstantPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

709

uint32_t VddciDynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

710

uint32_t Vddr1TotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

711

uint32_t Vddr1LeakagePower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

712

uint32_t Vddr1ConstantPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

713

uint32_t Vddr1DynamicPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

714

uint32_t spare[4];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

715

uint32_t temperature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

724

uint32_t I_calc_max;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

725

uint32_t I_calc_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

726

uint32_t P_meas_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

727

uint32_t V_meas_load_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

728

uint32_t I_meas_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

729

uint32_t P_meas_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

730

uint32_t V_meas_load_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

731

uint32_t I_meas_acc_vddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

738

uint32_t P_roc_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

739

uint32_t PkgPwr_max;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

740

uint32_t PkgPwr_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

741

uint32_t MclkSwitchingTime_max;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

742

uint32_t MclkSwitchingTime_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

743

uint32_t FanPwm_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

744

uint32_t FanRpm_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

745

uint32_t Gfx_busy_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

746

uint32_t Mc_busy_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

747

uint32_t Fps_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

749

uint32_t AccCnt;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

758

uint32_t TgpPwr_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

759

uint32_t Gfx_busy_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

760

uint32_t Mc_busy_acc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

761

uint32_t AccCnt;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

88

uint32_t CgSpllFuncCntl3;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

89

uint32_t CgSpllFuncCntl4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

90

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu75_discrete.h

91

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

105

uint32_t Flags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

106

uint32_t MinVddc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

107

uint32_t MinVddcPhases;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

109

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

114

uint32_t CgSpllFuncCntl3;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

115

uint32_t CgSpllFuncCntl4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

116

uint32_t SpllSpreadSpectrum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

117

uint32_t SpllSpreadSpectrum2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

118

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

119

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

136

uint32_t Flags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

137

uint32_t MinVddc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

138

uint32_t MinVddcPhases;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

139

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

144

uint32_t CgSpllFuncCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

145

uint32_t CgSpllFuncCntl2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

146

uint32_t CgSpllFuncCntl3;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

147

uint32_t CgSpllFuncCntl4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

148

uint32_t SpllSpreadSpectrum;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

149

uint32_t SpllSpreadSpectrum2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

150

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

151

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

158

uint32_t CcPwrDynRm;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

159

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

163

uint32_t Reserved;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

170

uint32_t MinVddc;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

171

uint32_t MinVddcPhases;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

172

uint32_t MinVddci;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

173

uint32_t MinMvdd;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

175

uint32_t MclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

196

uint32_t MpllFuncCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

197

uint32_t MpllFuncCntl_1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

198

uint32_t MpllFuncCntl_2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

199

uint32_t MpllAdFuncCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

200

uint32_t MpllDqFuncCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

201

uint32_t MclkPwrmgtCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

202

uint32_t DllCntl;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

203

uint32_t MpllSs1;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

204

uint32_t MpllSs2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

215

uint32_t DownT;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

216

uint32_t UpT;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

217

uint32_t Reserved;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

225

uint32_t McArbDramTiming;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

226

uint32_t McArbDramTiming2;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

242

uint32_t VclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

243

uint32_t DclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

255

uint32_t Frequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

265

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

266

uint32_t MclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

267

uint32_t VclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

268

uint32_t DclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

269

uint32_t SamclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

270

uint32_t AclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

271

uint32_t EclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

294

uint32_t SystemFlags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

297

uint32_t SmioMaskVddcVid;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

298

uint32_t SmioMaskVddcPhase;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

299

uint32_t SmioMaskVddciVid;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

300

uint32_t SmioMaskMvddVid;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

302

uint32_t VddcLevelCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

303

uint32_t VddciLevelCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

304

uint32_t MvddLevelCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

319

uint32_t VRConfig;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

320

uint32_t Reserved[4];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

334

uint32_t SclkStepSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

335

uint32_t Smio [SMU7_MAX_ENTRIES_SMIO];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

40

uint32_t RefClockFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

400

uint32_t BAPM_TEMP_GRADIENT;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

402

uint32_t LowSclkInterruptT;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

41

uint32_t PmTimerP;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

42

uint32_t FeatureEnables;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

420

uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

43

uint32_t PreVBlankGap;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

44

uint32_t VBlankTimeout;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

45

uint32_t TrainTimeGap;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

451

uint32_t RefreshPeriod;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

47

uint32_t MvddSwitchTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

48

uint32_t LongestAcpiTrainTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

49

uint32_t AcpiDelay;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

50

uint32_t G5TrainTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

51

uint32_t DelayMpllPwron;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

52

uint32_t VoltageChangeTimeout;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

53

uint32_t HandshakeDisables;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

65

uint32_t AverageGraphicsA;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

66

uint32_t AverageMemoryA;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

67

uint32_t AverageGioA;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

79

uint32_t DRAM_LOG_ADDR_H;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

80

uint32_t DRAM_LOG_ADDR_L;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

81

uint32_t DRAM_LOG_PHY_ADDR_H;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

82

uint32_t DRAM_LOG_PHY_ADDR_L;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

83

uint32_t DRAM_LOG_BUFF_SIZE;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

84

uint32_t UlvEnterC;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

85

uint32_t UlvTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_discrete.h

86

uint32_t Reserved[3];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

107

uint32_t reserved;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

118

uint32_t MinVddNb;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

124

uint32_t LclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

138

uint32_t VclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

139

uint32_t DclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

155

uint32_t Frequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

160

uint32_t Reserved;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

165

uint32_t Flags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

166

uint32_t MinVddNb;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

167

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

194

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

195

uint32_t LclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

196

uint32_t VclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

197

uint32_t DclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

198

uint32_t SamclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

199

uint32_t AclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

200

uint32_t EclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

210

uint32_t SystemFlags;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

249

uint32_t DisplayCac;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

250

uint32_t LowSclkInterruptT;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

252

uint32_t DRAM_LOG_ADDR_H;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

253

uint32_t DRAM_LOG_ADDR_L;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

254

uint32_t DRAM_LOG_PHY_ADDR_H;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

255

uint32_t DRAM_LOG_PHY_ADDR_L;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

256

uint32_t DRAM_LOG_BUFF_SIZE;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

266

uint32_t GIOLevelCount;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

40

uint32_t RefClockFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

41

uint32_t PmTimerP;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

42

uint32_t FeatureEnables;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

43

uint32_t HandshakeDisables;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

55

uint32_t AverageGraphicsA;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

56

uint32_t AverageMemoryA;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

57

uint32_t AverageGioA;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

69

uint32_t DRAM_LOG_ADDR_H;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

70

uint32_t DRAM_LOG_ADDR_L;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

71

uint32_t DRAM_LOG_PHY_ADDR_H;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

72

uint32_t DRAM_LOG_PHY_ADDR_L;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

73

uint32_t DRAM_LOG_BUFF_SIZE;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

74

uint32_t UlvEnterC;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

75

uint32_t UlvTime;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

76

uint32_t Reserved[3];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

83

uint32_t MinVddNb;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_fusion.h

85

uint32_t SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_ppsmc.h

210

#define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0x126)

sys/dev/pci/drm/amd/pm/powerplay/inc/smu7_ppsmc.h

211

#define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint32_t) 0x127)

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

32

uint32_t Version;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

33

uint32_t ImageSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

34

uint32_t CodeSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

35

uint32_t HeaderSize;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

36

uint32_t EntryPoint;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

37

uint32_t Rtos;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

38

uint32_t UcodeLoadStatus;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

39

uint32_t DpmTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

40

uint32_t FanTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

41

uint32_t PmFuseTable;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

42

uint32_t Globals;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

43

uint32_t Reserved[20];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

44

uint32_t Signature;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

48

uint32_t avgTotalPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

49

uint32_t avgGpuPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

50

uint32_t avgUvdPower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

51

uint32_t avgVcePower;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

53

uint32_t avgSclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

54

uint32_t avgDclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

55

uint32_t avgVclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

56

uint32_t avgEclk;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

58

uint32_t startTimeHi;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

59

uint32_t startTimeLo;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

61

uint32_t endTimeHi;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8.h

62

uint32_t endTimeLo;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8_fusion.h

103

uint32_t VclkValidMask;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8_fusion.h

104

uint32_t MaxVclkIndex;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8_fusion.h

111

uint32_t DclkValidMask;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8_fusion.h

112

uint32_t MaxDclkIndex;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8_fusion.h

119

uint32_t AclkValidMask;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8_fusion.h

120

uint32_t MaxAclkIndex;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8_fusion.h

41

uint32_t MmioAddress;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8_fusion.h

42

uint32_t MemoryBaseHi;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8_fusion.h

43

uint32_t MemoryBaseLo;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8_fusion.h

71

uint32_t DfsBypass;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8_fusion.h

72

uint32_t Frequency;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8_fusion.h

79

uint32_t SclkValidMask;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8_fusion.h

80

uint32_t MaxSclkIndex;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8_fusion.h

87

uint32_t LclkValidMask;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8_fusion.h

88

uint32_t MaxLclkIndex;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8_fusion.h

95

uint32_t EclkValidMask;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu8_fusion.h

96

uint32_t MaxEclkIndex;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9.h

124

uint32_t CurrLevel_GFXCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9.h

125

uint32_t CurrLevel_UVD : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9.h

126

uint32_t CurrLevel_VCE : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9.h

127

uint32_t CurrLevel_LCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9.h

128

uint32_t CurrLevel_MP0CLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9.h

129

uint32_t CurrLevel_UCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9.h

130

uint32_t CurrLevel_SOCCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9.h

131

uint32_t CurrLevel_DCEFCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9.h

133

uint32_t TargLevel_GFXCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9.h

134

uint32_t TargLevel_UVD : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9.h

135

uint32_t TargLevel_VCE : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9.h

136

uint32_t TargLevel_LCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9.h

137

uint32_t TargLevel_MP0CLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9.h

138

uint32_t TargLevel_UCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9.h

139

uint32_t TargLevel_SOCCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9.h

140

uint32_t TargLevel_DCEFCLK : 4;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9.h

142

uint32_t Reserved[6];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

140

uint32_t FitLimit; /* Failures in time (failures per million parts over the defined lifetime) */

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

150

uint32_t GeminiApertureHigh;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

151

uint32_t GeminiApertureLow;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

212

uint32_t LowGfxclkInterruptThreshold; /* in units of 10KHz */

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

298

uint32_t AConstant[3];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

304

uint32_t DpmLevelPowerDelta;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

321

uint32_t AcgFreqTable[NUM_GFXCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

324

uint32_t MmHubPadding[3]; /* SMU internal use */

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

351

uint32_t MmHubPadding[7]; /* SMU internal use */

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

362

uint32_t MmHubPadding[7]; /* SMU internal use */

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

366

uint32_t AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

367

uint32_t AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

368

uint32_t AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

369

uint32_t AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

370

uint32_t DcBtcGb;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

372

uint32_t MmHubPadding[7]; /* SMU internal use */

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

382

uint32_t MmHubPadding[7]; /* SMU internal use */

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

410

uint32_t AvfsTempCold;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

411

uint32_t AvfsTempMid;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

412

uint32_t AvfsTempHot;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

414

uint32_t InversionVoltage; /* in mV with 2 fractional bits */

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

420

uint32_t P2VCharzFreq; /* in 10KHz units */

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

422

uint32_t EnabledAvfsModules;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

424

uint32_t MmHubPadding[7]; /* SMU internal use */

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

81

uint32_t FbMult; /* Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */

sys/dev/pci/drm/amd/pm/powerplay/inc/smu9_driver_if.h

82

uint32_t SsFbMult; /* Spread FB Mult: bit 8:0 int, bit 31:16 frac */

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

109

uint32_t high;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

110

uint32_t low;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

118

uint32_t size_bytes;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

141

uint32_t register_address;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

142

uint32_t register_data;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

148

uint32_t register_address;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

149

uint32_t register_mask;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

150

uint32_t register_data;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

155

uint32_t register_address;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

156

uint32_t register_mask;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

157

uint32_t target_value;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

163

uint32_t register_address;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

164

uint32_t register_mask;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

165

uint32_t register_data;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_vi.h

75

uint32_t image_addr_high;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_vi.h

76

uint32_t image_addr_low;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_vi.h

77

uint32_t meta_data_addr_high;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_vi.h

78

uint32_t meta_data_addr_low;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_vi.h

79

uint32_t data_size_byte;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_vi.h

85

uint32_t image_addr_high;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_vi.h

86

uint32_t image_addr_low;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_vi.h

87

uint32_t meta_data_addr_high;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_vi.h

88

uint32_t meta_data_addr_low;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_vi.h

89

uint32_t data_size_byte;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_vi.h

96

uint32_t structure_version;

sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_vi.h

97

uint32_t num_entries;

sys/dev/pci/drm/amd/pm/powerplay/inc/smumgr.h

104

extern uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr,

sys/dev/pci/drm/amd/pm/powerplay/inc/smumgr.h

105

uint32_t type, uint32_t member);

sys/dev/pci/drm/amd/pm/powerplay/inc/smumgr.h

106

extern uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value);

sys/dev/pci/drm/amd/pm/powerplay/inc/smumgr.h

88

extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t *resp);

sys/dev/pci/drm/amd/pm/powerplay/inc/smumgr.h

91

uint16_t msg, uint32_t parameter,

sys/dev/pci/drm/amd/pm/powerplay/inc/smumgr.h

92

uint32_t *resp);

sys/dev/pci/drm/amd/pm/powerplay/inc/smumgr.h

96

extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

202

uint32_t a;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

203

uint32_t b;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

204

uint32_t c;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

208

uint32_t m;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

209

uint32_t b;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

213

uint32_t a;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

214

uint32_t b;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

215

uint32_t c;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

250

uint32_t Version;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

253

uint32_t FeaturesToRun[2];

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

279

uint32_t FitLimit;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

410

uint32_t DebugOverrides;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

419

uint32_t Reserved[14];

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

506

uint32_t BoardReserved[9];

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

509

uint32_t MmHubPadding[7];

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

523

uint32_t MmHubPadding[7];

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

564

uint32_t ThrottlerStatus ;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

570

uint32_t MmHubPadding[7];

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

595

uint32_t MmHubPadding[7];

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

604

uint32_t MmHubPadding[7];

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

638

uint32_t AvfsTempCold;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

639

uint32_t AvfsTempMid;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

640

uint32_t AvfsTempHot;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

642

uint32_t GfxVInversion;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

643

uint32_t SocVInversion;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

649

uint32_t P2VCharzFreq;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

651

uint32_t EnabledAvfsModules;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

653

uint32_t MmHubPadding[7];

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

667

uint32_t Gfx_PD_Data_limit_a;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

668

uint32_t Gfx_PD_Data_limit_b;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

669

uint32_t Gfx_PD_Data_limit_c;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

670

uint32_t Gfx_PD_Data_error_coeff;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

671

uint32_t Gfx_PD_Data_error_rate_coeff;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

682

uint32_t Soc_PD_Data_limit_a;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

683

uint32_t Soc_PD_Data_limit_b;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

684

uint32_t Soc_PD_Data_limit_c;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

685

uint32_t Soc_PD_Data_error_coeff;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

686

uint32_t Soc_PD_Data_error_rate_coeff;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

697

uint32_t Mem_PD_Data_limit_a;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

698

uint32_t Mem_PD_Data_limit_b;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

699

uint32_t Mem_PD_Data_limit_c;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

700

uint32_t Mem_PD_Data_error_coeff;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

701

uint32_t Mem_PD_Data_error_rate_coeff;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega20_ppsmc.h

126

typedef uint32_t PPSMC_Result;

sys/dev/pci/drm/amd/pm/powerplay/inc/vega20_ppsmc.h

127

typedef uint32_t PPSMC_Msg;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1002

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1025

uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1032

uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1033

uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1034

uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1035

uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1036

uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1037

uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1038

uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1039

uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1040

uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1072

uint32_t freq_nom;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1073

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1074

uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

108

static int ci_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1087

uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1088

uint32_t clkv =

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1089

(uint32_t)((((131 * ss_info.speed_spectrum_percentage *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

109

const uint8_t *src, uint32_t byte_count, uint32_t limit)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1119

static uint8_t ci_get_mclk_frequency_ratio(uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

112

uint32_t data = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

113

uint32_t original_data;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

114

uint32_t addr = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1143

static uint8_t ci_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

115

uint32_t extra_shift;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1158

uint32_t memory_clock, uint32_t *p_shed)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1176

uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1183

uint32_t mclk_edc_wr_enable_threshold = 40000;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1184

uint32_t mclk_edc_enable_threshold = 40000;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1185

uint32_t mclk_strobe_mode_threshold = 40000;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1307

uint32_t dev_id;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1309

uint32_t level_array_address = smu_data->dpm_table_start + offsetof(SMU7_Discrete_DpmTable, MemoryLevel);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1310

uint32_t level_array_size = sizeof(SMU7_Discrete_MemoryLevel) * SMU7_MAX_LEVELS_MEMORY;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1312

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1344

level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1350

static int ci_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1355

uint32_t i = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1385

uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1386

uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1387

uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1388

uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1623

uint32_t engine_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1624

uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1628

uint32_t dramTiming;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1629

uint32_t dramTiming2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1630

uint32_t burstTime;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1656

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1698

(uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1708

(uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1728

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1750

uint32_t num_entries, uint32_t valid_flag)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1752

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1764

const uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1769

uint32_t i = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1794

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1814

uint32_t address;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1828

address = smu_data->mc_reg_table_start + (uint32_t)offsetof(SMU7_Discrete_MCRegisters, data[0]);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

194

static int ci_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

195

uint32_t *value, uint32_t limit)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2129

uint32_t duty100;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2130

uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2132

uint32_t reference_clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2195

res = ci_copy_bytes_to_smc(hwmgr, ci_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2217

uint32_t low_sclk_interrupt_threshold = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2233

sizeof(uint32_t),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2249

static uint32_t ci_get_offsetof(uint32_t type, uint32_t member)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

228

uint16_t msg, uint32_t parameter)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2289

static uint32_t ci_get_mac_definition(uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2315

uint32_t byte_count, start_addr;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2317

uint32_t data;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2373

uint32_t tmp = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

238

uint32_t dev_id;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2543

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2587

uint32_t temp_reg;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2769

uint32_t array = smu_data->dpm_table_start +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2772

uint32_t mclk_array = smu_data->dpm_table_start +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2776

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2777

uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

279

uint32_t clock, uint32_t *vol)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

281

uint32_t i = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2863

uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2867

uint32_t max_vddc = adev->pm.ac_power ? hwmgr->dyn_state.max_clock_voltage_on_ac.vddc :

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2900

uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2904

uint32_t max_vddc = adev->pm.ac_power ? hwmgr->dyn_state.max_clock_voltage_on_ac.vddc :

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2926

static int ci_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

298

uint32_t clock, struct SMU7_Discrete_GraphicsLevel *sclk)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

302

uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

303

uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

304

uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

305

uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

306

uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

307

uint32_t ref_clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

308

uint32_t ref_divider;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

309

uint32_t fbdiv;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

343

uint32_t vco_freq = clock * dividers.uc_pll_post_div;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

347

uint32_t clk_s = ref_clock * 5 /

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

349

uint32_t clk_v = 4 * ss_info.speed_spectrum_percentage *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

373

uint32_t sclk, uint32_t *p_shed)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

388

static uint8_t ci_get_sleep_divider_id_from_clock(uint32_t clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

389

uint32_t clock_insr)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

392

uint32_t temp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

393

uint32_t min = min_t(uint32_t, clock_insr, CISLAND_MINIMUM_ENGINE_CLOCK);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

409

uint32_t clock, struct SMU7_Discrete_GraphicsLevel *level)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

420

(uint32_t *)(&level->MinVddc));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

478

uint32_t array = smu_data->dpm_table_start +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

480

uint32_t array_size = sizeof(struct SMU7_Discrete_GraphicsLevel) *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

484

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

542

static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

546

uint32_t temp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

551

(uint32_t *)&temp, SMC_RAM_END))

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

561

static int ci_populate_fuzzy_fan(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

592

for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

676

uint32_t pm_fuse_table_offset;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

782

for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

785

if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

798

for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

801

if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

874

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

902

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

95

uint32_t smc_addr, uint32_t limit)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

950

uint32_t voltage_response_time, ulv_voltage;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

49

uint32_t mclk_max;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

50

uint32_t mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

62

uint32_t soft_regs_start;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

63

uint32_t dpm_table_start;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

64

uint32_t mc_reg_table_start;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

65

uint32_t fan_table_start;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

66

uint32_t arb_table_start;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.h

67

uint32_t ulv_setting_starts;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1010

uint32_t array = smu_data->smu7_data.dpm_table_start +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1012

uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1016

uint32_t i, max_entry;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1087

(uint32_t)array_size, SMC_RAM_END);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1106

static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1143

uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1162

uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1168

uint32_t mclk_stutter_mode_threshold = 60000;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1179

(uint32_t *)(&mem_level->MinVoltage), &mem_level->MinMvdd);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1226

uint32_t array = smu_data->smu7_data.dpm_table_start +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1228

uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1232

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1266

(uint32_t)array_size, SMC_RAM_END);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1272

uint32_t mclk, SMIO_Pattern *smio_pat)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1277

uint32_t i = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1305

uint32_t mvdd;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1307

uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1308

uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1320

(uint32_t *)(&table->ACPILevel.MinVoltage), &mvdd);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1378

(uint32_t *)(&table->MemoryACPILevel.MinVoltage), &mvdd);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1497

uint32_t dram_timing;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1498

uint32_t dram_timing2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1499

uint32_t burstTime;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1529

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1611

(uint32_t *)&(table->GraphicsBootLevel));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1615

(uint32_t *)&(table->MemoryBootLevel));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1662

uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1703

volt_without_cks = (uint32_t)((14041 *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1706

volt_with_cks = (uint32_t)((13946 *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1864

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1882

tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2133

uint32_t duty100;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2134

uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2136

uint32_t reference_clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2213

(uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

225

uint32_t table_start;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

226

uint32_t level_addr, vr_config_addr;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2267

uint32_t low_sclk_interrupt_threshold = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

227

uint32_t level_size = sizeof(avfs_graphics_level);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2283

sizeof(uint32_t),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2293

static uint32_t fiji_get_offsetof(uint32_t type, uint32_t member)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2339

static uint32_t fiji_get_mac_definition(uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2368

uint32_t mm_boot_level_offset, mm_boot_level_value;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2393

(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2401

uint32_t mm_boot_level_offset, mm_boot_level_value;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2426

(uint32_t)1 << smu_data->smc_state_table.VceBootLevel,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2431

static int fiji_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2450

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2556

uint32_t array = smu_data->smu7_data.dpm_table_start +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2559

uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2563

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2564

uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

320

uint32_t efuse = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

354

uint32_t clock, uint32_t *voltage, uint32_t *mvdd)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

356

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

388

*mvdd = (uint32_t) dep_table->entries[i].mvdd *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

412

*mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

420

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

603

static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

607

uint32_t temp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

612

(uint32_t *)&temp, SMC_RAM_END))

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

69

static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] = {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

691

uint32_t pm_fuse_table_offset;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

757

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

856

uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

860

uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

861

uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

862

uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

863

uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

864

uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

865

uint32_t ref_clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

866

uint32_t ref_divider;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

867

uint32_t fbdiv;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

902

uint32_t vco_freq = clock * dividers.uc_pll_post_div;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

911

uint32_t clk_s = ref_clock * 5 /

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

914

uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

937

uint32_t clock, struct SMU73_Discrete_GraphicsLevel *level)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

941

uint32_t mvdd;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

957

(uint32_t *)(&level->MinVoltage), &mvdd);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1038

(uint8_t *)levels, (uint32_t)level_array_size,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1046

uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1054

uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1055

uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1056

uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1057

uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1058

uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1059

uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1060

uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1061

uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1062

uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1113

uint32_t freq_nom;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1114

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1115

uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1132

uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1136

uint32_t clkv =

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1137

(uint32_t)((((131 * ss_info.speed_spectrum_percentage *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1169

static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1195

static uint8_t iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1211

uint32_t memory_clock, uint32_t *p_shed)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1229

uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1236

uint32_t mclk_edc_wr_enable_threshold = 40000;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1237

uint32_t mclk_edc_enable_threshold = 40000;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1238

uint32_t mclk_strobe_mode_threshold = 40000;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1354

uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1355

uint32_t level_array_size = sizeof(SMU71_Discrete_MemoryLevel) * SMU71_MAX_LEVELS_MEMORY;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1357

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1389

level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1395

static int iceland_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1400

uint32_t i = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1428

uint32_t vddc_phase_shed_control = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1431

uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1432

uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1433

uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1434

uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

158

uint32_t length, const uint8_t *src,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1584

uint32_t engine_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1585

uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1589

uint32_t dramTiming;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

159

uint32_t limit, uint32_t start_addr)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1590

uint32_t dramTiming2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1591

uint32_t burstTime;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

161

uint32_t byte_count = length;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1617

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

162

uint32_t data;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1659

(uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1669

(uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1693

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1716

uint32_t num_entries, uint32_t valid_flag)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1718

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1729

const uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1734

uint32_t i = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1759

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1779

uint32_t address;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1794

address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

186

uint32_t val;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2089

uint32_t duty100;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2090

uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2092

uint32_t reference_clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2157

res = smu7_copy_bytes_to_smc(hwmgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2180

uint32_t low_sclk_interrupt_threshold = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2196

sizeof(uint32_t),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2212

static uint32_t iceland_get_offsetof(uint32_t type, uint32_t member)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2254

static uint32_t iceland_get_mac_definition(uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2283

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

229

uint32_t firmwareType)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2470

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

2514

uint32_t temp_reg;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

284

uint32_t dev_id;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

335

static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

339

uint32_t temp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

344

(uint32_t *)&temp, SMC_RAM_END))

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

404

for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

438

uint32_t pm_fuse_table_offset;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

508

uint32_t clock, uint32_t *vol)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

510

uint32_t i = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

554

for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

557

if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

574

for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

577

if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

647

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

672

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

717

uint32_t voltage_response_time, ulv_voltage;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

769

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

796

uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

800

uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

801

uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

802

uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

803

uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

804

uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

805

uint32_t reference_clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

806

uint32_t reference_divider;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

807

uint32_t fbdiv;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

842

uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

849

uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

852

uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

875

uint32_t sclk, uint32_t *p_shed)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

892

uint32_t engine_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

964

uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

967

uint32_t level_array_size = sizeof(SMU71_Discrete_GraphicsLevel) *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

972

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.h

41

uint32_t display_cac;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.h

42

uint32_t bapm_temp_gradient;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.h

48

uint32_t mclk_max;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.h

49

uint32_t mc_data[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1046

uint32_t array = smu_data->smu7_data.dpm_table_start +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1048

uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1052

uint32_t i, max_entry;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1059

uint32_t dpm0_sclkfrequency = levels[0].SclkSetting.SclkFrequency;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1147

(uint32_t)array_size, SMC_RAM_END);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1154

uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1160

uint32_t mclk_stutter_mode_threshold = 40000;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1215

uint32_t array = smu_data->smu7_data.dpm_table_start +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1217

uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

122

uint32_t vr_config;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1221

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

123

uint32_t dpm_table_start;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1247

(uint32_t)array_size, SMC_RAM_END);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1253

uint32_t mclk, SMIO_Pattern *smio_pat)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1258

uint32_t i = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

126

uint32_t graphics_level_address, vr_config_address, graphics_level_size;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1281

uint32_t sclk_frequency;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1286

uint32_t mvdd;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1376

uint32_t vddci;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1388

vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1426

uint32_t vddci;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

143

(uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1437

vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1468

uint32_t dram_timing;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1469

uint32_t dram_timing2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1470

uint32_t burst_time;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1495

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1531

uint32_t vddci;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1544

vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1589

(uint32_t *)&(table->GraphicsBootLevel));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1597

(uint32_t *)&(table->MemoryBootLevel));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1658

uint32_t ro, efuse, volt_without_cks, volt_with_cks, value;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1675

volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 - (ro - 70) * 1000000) / \

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1677

volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1680

volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 - (ro - 50) * 1000000) / \

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1682

volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1780

uint32_t tmp, i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2171

uint32_t duty100;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2172

uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2174

uint32_t reference_clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2255

(uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2284

uint32_t mm_boot_level_offset, mm_boot_level_value;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2309

(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2317

uint32_t mm_boot_level_offset, mm_boot_level_value;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2342

(uint32_t)1 << smu_data->smc_state_table.VceBootLevel,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2364

static int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2388

uint32_t low_sclk_interrupt_threshold = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2404

sizeof(uint32_t),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2418

static uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2464

static uint32_t polaris10_get_mac_definition(uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2496

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2594

uint32_t array = smu_data->smu7_data.dpm_table_start +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2597

uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2601

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2602

uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

325

uint32_t efuse;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

355

uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

357

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

389

*mvdd = (uint32_t) dep_table->entries[i].mvdd *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

415

*mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

422

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

521

static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

525

uint32_t temp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

530

(uint32_t *)&temp, SMC_RAM_END))

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

607

uint32_t pm_fuse_table_offset;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

668

uint32_t count, level;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

685

table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

694

uint32_t count, level;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

719

uint32_t count, level;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

744

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

851

uint32_t i, ref_clk;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

891

uint32_t clock, SMU_SclkSetting *sclk_setting)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

896

uint32_t ref_clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

897

uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

956

uint32_t clock, struct SMU74_Discrete_GraphicsLevel *level)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

960

uint32_t mvdd;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h

43

uint32_t DisplayCac;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h

44

uint32_t BAPM_TEMP_GRADIENT;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h

50

uint32_t trans_lower_frequency; /* in 10khz */

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h

51

uint32_t trans_upper_frequency;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h

62

uint32_t bif_sclk_table[SMU74_MAX_LEVELS_LINK];

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

187

uint32_t smc_driver_if_version;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

49

static uint32_t smu10_wait_for_response(struct pp_hwmgr *hwmgr)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

52

uint32_t reg;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

72

static uint32_t smu10_read_arg_from_smc(struct pp_hwmgr *hwmgr)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

97

uint16_t msg, uint32_t parameter)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.h

33

uint32_t version;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.h

34

uint32_t size;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.h

35

uint32_t table_id;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

161

int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

170

uint32_t smu7_get_argument(struct pp_hwmgr *hwmgr)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

180

enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

229

int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

240

int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t value, uint32_t limit)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

255

uint32_t fw_type,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

292

uint32_t fw_to_load;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

38

static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t limit)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

401

int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

418

static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint32_t *src, uint32_t limit)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

420

uint32_t byte_count = length;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

454

result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

462

uint32_t reg, data;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

49

int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

50

const uint8_t *src, uint32_t byte_count, uint32_t limit)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

53

uint32_t data = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

54

uint32_t original_data;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

55

uint32_t addr = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c

56

uint32_t extra_shift;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

33

uint32_t data_size;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

44

uint32_t soft_regs_start;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

45

uint32_t dpm_table_start;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

46

uint32_t mc_reg_table_start;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

47

uint32_t fan_table_start;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

48

uint32_t arb_table_start;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

49

uint32_t ulv_setting_starts;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

51

uint32_t acpi_optimization;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

52

uint32_t avfs_btc_param;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

56

int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

57

const uint8_t *src, uint32_t byte_count, uint32_t limit);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

62

uint32_t parameter);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

63

uint32_t smu7_get_argument(struct pp_hwmgr *hwmgr);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

66

enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

67

int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

68

uint32_t *value, uint32_t limit);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

69

int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

70

uint32_t value, uint32_t limit);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h

73

int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

110

uint32_t smc_address, uint32_t limit)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

132

uint32_t smc_address, uint32_t value, uint32_t limit)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

147

uint32_t firmware)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

150

uint32_t index = SMN_MP1_SRAM_START_ADDR +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

176

uint32_t reg_data;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

177

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

290

static enum cgs_ucode_id smu8_convert_fw_type_to_cgs(uint32_t fw_type)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

549

uint32_t firmware_type;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

550

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

56

static uint32_t smu8_get_argument(struct pp_hwmgr *hwmgr)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

583

uint32_t ulsize_byte,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

587

uint32_t ulsize_aligned = SIZE_ALIGN_32(ulsize_byte);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

665

uint32_t smc_address;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

666

uint32_t fw_to_check = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

67

uint16_t msg, uint32_t parameter)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

736

uint32_t index = SMN_MP1_SRAM_START_ADDR +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

80

uint32_t val = cgs_read_register(hwmgr->device,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

874

uint32_t features;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.h

62

uint32_t data_size;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.h

70

uint32_t offset;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.h

71

uint32_t value;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.h

75

uint32_t command;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c

116

uint32_t ret;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c

142

uint16_t msg, uint32_t parameter)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c

145

uint32_t ret;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c

166

uint32_t smu9_get_argument(struct pp_hwmgr *hwmgr)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c

42

uint32_t mp1_fw_flags;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c

59

static uint32_t smu9_wait_for_response(struct pp_hwmgr *hwmgr)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c

62

uint32_t reg;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c

63

uint32_t ret;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.h

29

uint16_t msg, uint32_t parameter);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.h

30

uint32_t smu9_get_argument(struct pp_hwmgr *hwmgr);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smumgr.c

106

uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smumgr.c

130

int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t *resp)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smumgr.c

157

uint32_t parameter,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smumgr.c

158

uint32_t *resp)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smumgr.c

82

int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smumgr.c

91

uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr, uint32_t type, uint32_t member)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1095

uint32_t level_array_address =

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1098

uint32_t level_array_size =

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1103

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1137

level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1144

uint32_t mclk, SMIO_Pattern *smio_pattern)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1149

uint32_t i = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1183

uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1184

uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1185

uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1186

uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1459

uint32_t engine_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1460

uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1464

uint32_t dramTiming;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1465

uint32_t dramTiming2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1466

uint32_t burstTime;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1493

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1535

(uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1547

(uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1575

uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1586

uint32_t hw_revision, dev_id;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1624

volt_without_cks = (uint32_t)((7732 + 60 - ro - 20838 *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1627

volt_with_cks = (uint32_t)((5250 + 51 - ro - 2404 *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1631

volt_without_cks = (uint32_t)((14041 *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1634

volt_with_cks = (uint32_t)((13946 *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1800

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1819

tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1909

static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1914

uint32_t temp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1919

(uint32_t *)&temp, SMC_RAM_END))

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1998

uint32_t pm_fuse_table_offset;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2068

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2094

uint32_t num_entries, uint32_t valid_flag)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2096

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2108

const uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2113

uint32_t i = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2138

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2158

uint32_t address;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2174

(uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2465

uint32_t duty100;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2466

uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2468

uint32_t reference_clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

248

uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

250

uint32_t i = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2545

(uint32_t)sizeof(fan_table),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2570

uint32_t low_sclk_interrupt_threshold = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2586

sizeof(uint32_t),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2604

static uint32_t tonga_get_offsetof(uint32_t type, uint32_t member)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2650

static uint32_t tonga_get_mac_definition(uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2679

uint32_t mm_boot_level_offset, mm_boot_level_value;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2705

(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2714

uint32_t mm_boot_level_offset, mm_boot_level_value;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2737

(uint32_t)1 << smu_data->smc_state_table.VceBootLevel,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2742

static int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2762

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

279

*mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2932

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

297

*mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2978

uint32_t temp_reg;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3155

uint32_t array = smu_data->smu7_data.dpm_table_start +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3158

uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3162

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

3163

uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

340

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

370

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

394

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

407

uint32_t vddc_level_count = PP_SMC_TO_HOST_UL(table->VddcLevelCount);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

408

uint32_t vddgfx_level_count = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

512

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

539

uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

543

uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

544

uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

545

uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

546

uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

547

uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

548

uint32_t reference_clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

549

uint32_t reference_divider;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

550

uint32_t fbdiv;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

585

uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

592

uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

595

uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

617

uint32_t engine_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

621

uint32_t mvdd;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

694

uint32_t level_array_address = smu_data->smu7_data.dpm_table_start +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

697

uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

702

uint32_t i, max_entry;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

781

(uint8_t *)levels, (uint32_t)level_array_size,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

789

uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

797

uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

798

uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

799

uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

800

uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

801

uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

802

uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

803

uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

804

uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

805

uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

86

static const uint32_t tonga_clock_stretcher_ddt_table[2][4][4] = {

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

865

uint32_t freq_nom;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

866

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

867

uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

884

uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

888

uint32_t clkv =

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

889

(uint32_t)((((131 * ss_info.speed_spectrum_percentage *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

920

static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

944

static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

961

uint32_t memory_clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

968

uint32_t mclk_edc_wr_enable_threshold = 40000;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

969

uint32_t mclk_stutter_mode_threshold = 30000;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

970

uint32_t mclk_edc_enable_threshold = 40000;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

971

uint32_t mclk_strobe_mode_threshold = 40000;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

975

uint32_t mvdd = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.h

43

uint32_t display_cac;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.h

44

uint32_t bapm_temp_gradient;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.h

50

uint32_t mclk_max;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.h

51

uint32_t mc_data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

112

bool enable, uint32_t feature_mask)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

132

uint32_t enabled_features;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

180

uint32_t smc_driver_if_version;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

182

uint32_t dev_id;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

183

uint32_t rev_id;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.h

29

uint32_t version;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.h

30

uint32_t size;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.h

31

uint32_t table_id;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.h

46

bool enable, uint32_t feature_mask);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

128

uint32_t smu_features_low, smu_features_high;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

130

smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

131

smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

159

uint32_t smc_features_low, smc_features_high;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.h

31

uint32_t version;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.h

32

uint32_t size;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

131

uint16_t msg, uint32_t parameter)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

151

static uint32_t vega20_get_argument(struct pp_hwmgr *hwmgr)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

320

uint32_t smu_features_low, smu_features_high;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

323

smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

324

smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

352

uint32_t smc_features_low, smc_features_high;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

52

uint32_t mp1_fw_flags;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

70

static uint32_t vega20_wait_for_response(struct pp_hwmgr *hwmgr)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

73

uint32_t reg;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.h

30

uint32_t version;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.h

31

uint32_t size;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1041

uint32_t array = smu_data->smu7_data.dpm_table_start +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1043

uint32_t array_size = sizeof(SMU75_Discrete_MemoryLevel) *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1047

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1080

(uint32_t)array_size, SMC_RAM_END);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1086

uint32_t mclk, SMIO_Pattern *smio_pat)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1091

uint32_t i = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1114

uint32_t sclk_frequency;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1119

uint32_t mvdd;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1205

uint32_t vddci;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1217

vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1248

uint32_t dram_timing;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1249

uint32_t dram_timing2;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1250

uint32_t burst_time;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1251

uint32_t rfsh_rate;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1252

uint32_t misc3;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1282

uint32_t i, j;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1318

uint32_t vddci;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1331

vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1376

(uint32_t *)&(table->GraphicsBootLevel));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1382

(uint32_t *)&(table->MemoryBootLevel));

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1433

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1488

uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1512

volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1515

volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1549

uint32_t efuse;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1571

uint32_t tmp, i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1761

static int vegam_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1765

uint32_t temp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1770

(uint32_t *)&temp, SMC_RAM_END))

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1847

uint32_t pm_fuse_table_offset;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2153

static uint32_t vegam_get_offsetof(uint32_t type, uint32_t member)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2218

uint32_t low_sclk_interrupt_threshold = 0;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2234

sizeof(uint32_t),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

229

uint32_t tmp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

302

static uint32_t vegam_get_mac_definition(uint32_t value)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

333

uint32_t mm_boot_level_offset, mm_boot_level_value;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

358

(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

366

uint32_t mm_boot_level_offset, mm_boot_level_value;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

391

(uint32_t)1 << smu_data->smc_state_table.VceBootLevel,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

413

static int vegam_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

452

uint32_t count, level;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

469

table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

478

uint32_t count, level;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

503

uint32_t count;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

602

uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

604

uint32_t i;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

636

*mvdd = (uint32_t) dep_table->entries[i].mvdd *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

664

*mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

673

uint32_t i, ref_clk;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

720

uint32_t clock, SMU_SclkSetting *sclk_setting)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

725

uint32_t ref_clock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

726

uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

790

static uint8_t vegam_get_sleep_divider_id_from_clock(uint32_t clock,

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

791

uint32_t clock_insr)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

794

uint32_t temp;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

795

uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

810

uint32_t clock, struct SMU75_Discrete_GraphicsLevel *level)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

814

uint32_t mvdd;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

874

uint32_t array = smu_data->smu7_data.dpm_table_start +

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

876

uint32_t array_size = sizeof(struct SMU75_Discrete_GraphicsLevel) *

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

880

uint32_t i, max_entry;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

958

(uint32_t)array_size, SMC_RAM_END);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

964

uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

973

mem_level->MclkFrequency = (uint32_t)mpll_param.ulClock;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

982

uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

988

uint32_t mclk_stutter_mode_threshold = 60000;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.h

52

uint32_t DisplayCac;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.h

53

uint32_t BAPM_TEMP_GRADIENT;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.h

59

uint32_t trans_lower_frequency; /* in 10khz */

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.h

60

uint32_t trans_upper_frequency;

sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.h

71

uint32_t bif_sclk_table[SMU75_MAX_LEVELS_LINK];

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

1263

uint32_t hotspot_tmp, size;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

130

int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

142

uint32_t min,

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

143

uint32_t max)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

1476

uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

164

uint32_t *min,

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

165

uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

197

uint32_t clk_freq;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

211

uint32_t clk_freq;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2336

uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2611

static int smu_set_display_count(void *handle, uint32_t count)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2623

uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2649

uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2868

static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2906

uint32_t *limit,

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2913

uint32_t limit_type;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2988

static int smu_set_power_limit(void *handle, uint32_t limit)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

2991

uint32_t limit_type = limit >> 24;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3133

long *input, uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3158

uint32_t *size, size_val;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3175

*((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3179

*((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3183

*((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3187

*((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3195

*(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3199

*(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3203

*(uint32_t *)data = 0;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3206

*(uint32_t *)data = 1;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3213

*(uint32_t *)data = 0;

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3229

static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3240

static int smu_set_apu_thermal_limit(void *handle, uint32_t limit)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3266

uint32_t param_size)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3397

static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3416

static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3494

uint32_t pstate)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

3732

uint32_t state)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

390

uint32_t block_type,

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

4015

int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

4118

int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

4128

int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

4160

int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

4175

int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask)

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

64

uint32_t mask);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

679

uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

71

static int smu_set_power_limit(void *handle, uint32_t limit);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

72

static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

82

long *input, uint32_t size);

sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c

964

uint32_t max_table_size = 0;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1089

enum smu_message_type msg, uint32_t param, uint32_t *read_arg);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1098

uint32_t *read_arg);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1104

int (*init_display_count)(struct smu_context *smu, uint32_t count);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1143

uint32_t limit);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1165

int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1178

uint32_t (*get_fan_control_mode)(struct smu_context *smu);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1183

int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1188

int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1193

int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1199

int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1216

uint32_t (*get_gfx_off_status)(struct smu_context *smu);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1232

u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1315

int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1321

int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max,

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1403

int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1426

int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1436

int (*reset_sdma)(struct smu_context *smu, uint32_t inst_mask);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1441

int (*dpm_reset_vcn)(struct smu_context *smu, uint32_t inst_mask);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1452

int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1468

int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1655

uint32_t WifiBandEntryNum;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1657

uint32_t MmHubPadding[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1701

uint32_t cache_interval)

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1733

uint32_t *limit,

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1749

uint32_t *min, uint32_t *max);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1752

uint32_t min, uint32_t max);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1767

int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1774

int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1776

int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1777

int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1779

int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

1781

int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

184

uint32_t vclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

185

uint32_t dclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

192

uint32_t id;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

233

uint32_t fan_mode;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

234

uint32_t power_limit;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

235

uint32_t fan_speed_pwm;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

236

uint32_t fan_speed_rpm;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

237

uint32_t flags;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

238

uint32_t user_od;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

241

uint32_t clk_mask[SMU_CLK_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

242

uint32_t clk_dependency;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

256

uint32_t interval;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

262

uint32_t align;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

267

uint32_t version;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

277

uint32_t core_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

278

uint32_t memory_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

279

uint32_t vddc;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

280

uint32_t vddci;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

281

uint32_t non_local_mem_freq;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

282

uint32_t non_local_mem_width;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

286

uint32_t min_mem_clk;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

287

uint32_t max_mem_clk;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

288

uint32_t min_eng_clk;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

289

uint32_t max_eng_clk;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

290

uint32_t min_bus_bandwidth;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

291

uint32_t max_bus_bandwidth;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

295

uint32_t revision;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

296

uint32_t gfxclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

297

uint32_t uclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

298

uint32_t socclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

299

uint32_t dcefclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

300

uint32_t eclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

301

uint32_t vclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

302

uint32_t dclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

308

uint32_t pp_table_id;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

309

uint32_t format_revision;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

310

uint32_t content_revision;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

311

uint32_t fclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

312

uint32_t lclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

313

uint32_t firmware_caps;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

342

uint32_t power_play_table_size;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

373

uint32_t gpu_metrics_table_size;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

399

uint32_t dpm_context_size;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

427

uint32_t power_context_size;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

433

uint32_t feature_num;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

439

uint32_t engine_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

440

uint32_t memory_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

441

uint32_t bus_bandwidth;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

442

uint32_t engine_clock_in_sr;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

443

uint32_t dcef_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

444

uint32_t dcef_clock_in_sr;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

449

uint32_t frequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

450

uint32_t latency;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

453

uint32_t count;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

472

uint32_t state;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

478

uint32_t min;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

479

uint32_t max;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

480

uint32_t freq_level;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

484

uint32_t min;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

485

uint32_t standard;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

486

uint32_t peak;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

503

uint32_t flags;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

512

uint32_t stb_buf_size;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

568

uint32_t pstate_sclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

569

uint32_t pstate_mclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

572

uint32_t current_power_limit;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

573

uint32_t default_power_limit;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

574

uint32_t max_power_limit;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

575

uint32_t min_power_limit;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

578

uint32_t ppt_offset_bytes;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

579

uint32_t ppt_size_bytes;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

587

uint32_t watermarks_bitmap;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

588

uint32_t hard_min_uclk_req_from_dal;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

592

uint32_t workload_mask;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

595

uint32_t power_profile_mode;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

596

uint32_t workload_refcount[PP_SMC_POWER_PROFILE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

602

uint32_t smc_driver_if_version;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

603

uint32_t smc_fw_if_version;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

604

uint32_t smc_fw_version;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

605

uint32_t smc_fw_caps;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

618

uint32_t gfx_default_hard_min_freq;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

619

uint32_t gfx_default_soft_max_freq;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

620

uint32_t gfx_actual_hard_min_freq;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

621

uint32_t gfx_actual_soft_max_freq;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

624

uint32_t cpu_default_soft_min_freq;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

625

uint32_t cpu_default_soft_max_freq;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

626

uint32_t cpu_actual_soft_min_freq;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

627

uint32_t cpu_actual_soft_max_freq;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

628

uint32_t cpu_core_id_select;

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

693

int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

744

int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

754

long *input, uint32_t size);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

822

void *data, uint32_t *size);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

828

int (*get_apu_thermal_limit)(struct smu_context *smu, uint32_t *limit);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

834

int (*set_apu_thermal_limit)(struct smu_context *smu, uint32_t limit);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

875

int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

880

int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

899

int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

925

uint32_t *current_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

926

uint32_t *default_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

927

uint32_t *max_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

928

uint32_t *min_power_limit);

sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h

933

int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit,

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/aldebaran_ppsmc.h

127

typedef uint32_t PPSMC_Result;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/aldebaran_ppsmc.h

128

typedef uint32_t PPSMC_Msg;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/arcturus_ppsmc.h

130

typedef uint32_t PPSMC_Result;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/arcturus_ppsmc.h

131

typedef uint32_t PPSMC_Msg;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

266

uint32_t SlaveAddress;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

316

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

342

uint32_t a; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

343

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

344

uint32_t c; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

348

uint32_t m; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

349

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

353

uint32_t a; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

354

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

355

uint32_t c; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

469

uint32_t Version;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

472

uint32_t FeaturesToRun[2];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

488

uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime)

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

494

uint32_t ThrottlerControlMask; // See Throtter masks defines

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

522

uint32_t Paddingclks[16];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

610

uint32_t DebugOverrides;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

627

uint32_t PaddingAPCC[6]; //FIXME pending SPEC

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

642

uint32_t Reserved[7];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

706

uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

728

uint32_t BoardVoltageCoeffA; // decode by /1000

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

729

uint32_t BoardVoltageCoeffB; // decode by /1000

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

731

uint32_t BoardReserved[7];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

734

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

753

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

774

uint32_t ThrottlerStatus ;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

780

uint32_t EnergyAccumulator ;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

782

uint32_t Padding[2];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

785

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

795

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

831

uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

832

uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

833

uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

835

uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

842

uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

844

uint32_t EnabledAvfsModules[3];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

846

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

861

uint32_t Gfx_PD_Data_limit_a; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

862

uint32_t Gfx_PD_Data_limit_b; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

863

uint32_t Gfx_PD_Data_limit_c; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

864

uint32_t Gfx_PD_Data_error_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

865

uint32_t Gfx_PD_Data_error_rate_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

878

uint32_t Mem_PD_Data_limit_a; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

879

uint32_t Mem_PD_Data_limit_b; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

880

uint32_t Mem_PD_Data_limit_c; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

881

uint32_t Mem_PD_Data_error_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

882

uint32_t Mem_PD_Data_error_rate_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

884

uint32_t Mem_UpThreshold_Limit; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

889

uint32_t BusyThreshold; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

890

uint32_t BusyHyst;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

891

uint32_t IdleHyst;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h

893

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_cyan_skillfish.h

42

uint32_t CorePower[6]; //[mW]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_cyan_skillfish.h

59

uint32_t Voltage[2]; //[mV] indices: VDDCR_VDD, VDDCR_GFX

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_cyan_skillfish.h

60

uint32_t Current[2]; //[mA] indices: VDDCR_VDD, VDDCR_GFX

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_cyan_skillfish.h

61

uint32_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_GFX

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_cyan_skillfish.h

62

uint32_t CurrentSocketPower; //[mW]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_cyan_skillfish.h

74

uint32_t SampleStartTime;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_cyan_skillfish.h

75

uint32_t SampleStopTime;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_cyan_skillfish.h

76

uint32_t Accnt;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1008

uint32_t Padding32_1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1012

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1031

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1046

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1055

uint32_t MmHubPadding[32]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1064

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1101

uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1102

uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1103

uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1105

uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1112

uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1114

uint32_t EnabledAvfsModules[2]; //NV10 - 36 AVFS modules

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1116

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1130

uint32_t Gfx_PD_Data_limit_a; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1131

uint32_t Gfx_PD_Data_limit_b; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1132

uint32_t Gfx_PD_Data_limit_c; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1133

uint32_t Gfx_PD_Data_error_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1134

uint32_t Gfx_PD_Data_error_rate_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1145

uint32_t Soc_PD_Data_limit_a; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1146

uint32_t Soc_PD_Data_limit_b; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1147

uint32_t Soc_PD_Data_limit_c; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1148

uint32_t Soc_PD_Data_error_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1149

uint32_t Soc_PD_Data_error_rate_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1160

uint32_t Mem_PD_Data_limit_a; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1161

uint32_t Mem_PD_Data_limit_b; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1162

uint32_t Mem_PD_Data_limit_c; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1163

uint32_t Mem_PD_Data_error_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1164

uint32_t Mem_PD_Data_error_rate_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1166

uint32_t Mem_UpThreshold_Limit; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1171

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

1216

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

270

uint32_t SlaveAddress;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

320

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

346

uint32_t a; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

347

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

348

uint32_t c; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

352

uint32_t m; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

353

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

357

uint32_t a; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

358

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

359

uint32_t c; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

500

uint32_t DieTemperatureRegisterOffset;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

502

uint32_t Reserved2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

504

uint32_t Reserved3;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

506

uint32_t Status;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

515

uint32_t BoardLevelEnergyAccumulator;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

520

uint32_t Version;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

523

uint32_t FeaturesToRun[2];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

546

uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime)

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

552

uint32_t ThrottlerControlMask; // See Throtter masks defines

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

555

uint32_t FwDStateMask; // See FW DState masks defines

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

594

uint32_t Paddingclks[16];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

691

uint32_t DebugOverrides;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

705

uint32_t MGpuFanBoostLimitRpm;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

706

uint32_t PaddingAPCC[5];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

720

uint32_t BtcConfig;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

726

uint32_t Reserved[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

805

uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

812

uint32_t BoardReserved[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

815

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

830

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

856

uint32_t MmHubPadding[6]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

883

uint32_t ThrottlerStatus ;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

890

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

916

uint32_t ThrottlerStatus ;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

929

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

955

uint32_t ThrottlerStatus ;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

961

uint32_t EnergyAccumulator;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

968

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h

994

uint32_t ThrottlerStatus ;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1000

uint32_t ThrottlerControlMask; // See Throtter masks defines

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1003

uint32_t FwDStateMask; // See FW DState masks defines

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1052

uint32_t Paddingclks;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1056

uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1081

uint32_t GfxGpoVotingAllow; //For indicating which feature changes should result in a GPO table recalculation

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1083

uint32_t GfxGpoPadding32[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1094

uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1099

uint32_t DcsParamPadding[5];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1176

uint32_t DebugOverrides;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1190

uint32_t VcBtcPsmA; // A_PSM

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1191

uint32_t VcBtcPsmB; // B_PSM

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1192

uint32_t VcBtcVminA; // A_VMIN

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1193

uint32_t VcBtcVminB; // B_VMIN

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1199

uint32_t SkuReserved[63];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1206

uint32_t GamingClk[6];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1244

uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1289

uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1314

uint32_t BoardReserved[11];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1319

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1339

uint32_t Spare[7];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1341

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1368

uint32_t Spare[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1370

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1374

uint32_t CurrClock[PPCLK_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1402

uint32_t ThrottlerStatus ;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1415

uint32_t EnergyAccumulator;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1429

uint32_t CurrClock[PPCLK_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1457

uint32_t AccCnt ;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1472

uint32_t EnergyAccumulator;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1486

uint32_t CurrClock[PPCLK_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1514

uint32_t AccCnt;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1529

uint32_t EnergyAccumulator;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1540

uint32_t PublicSerialNumLower32;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1541

uint32_t PublicSerialNumUpper32;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1546

uint32_t CurrClock[PPCLK_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1574

uint32_t AccCnt;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1589

uint32_t EnergyAccumulator;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1614

uint32_t Spare[1];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1617

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1655

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1668

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1705

uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1706

uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1707

uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1709

uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1716

uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1718

uint32_t EnabledAvfsModules[3]; //Sienna_Cichlid - 67 AVFS modules

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1724

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1737

uint32_t Gfx_PD_Data_limit_a; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1738

uint32_t Gfx_PD_Data_limit_b; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1739

uint32_t Gfx_PD_Data_limit_c; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1740

uint32_t Gfx_PD_Data_error_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1741

uint32_t Gfx_PD_Data_error_rate_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1752

uint32_t Fclk_PD_Data_limit_a; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1753

uint32_t Fclk_PD_Data_limit_b; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1754

uint32_t Fclk_PD_Data_limit_c; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1755

uint32_t Fclk_PD_Data_error_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1756

uint32_t Fclk_PD_Data_error_rate_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1767

uint32_t Mem_PD_Data_limit_a; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1768

uint32_t Mem_PD_Data_limit_b; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1769

uint32_t Mem_PD_Data_limit_c; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1770

uint32_t Mem_PD_Data_error_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1771

uint32_t Mem_PD_Data_error_rate_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1773

uint32_t Mem_UpThreshold_Limit; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1783

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

1828

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

277

uint32_t eccPadding;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

404

uint32_t Spare[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

405

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

430

uint32_t a; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

431

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

432

uint32_t c; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

436

uint32_t a; // store in fixed point, [31:20] signed integer, [19:0] fractional bits

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

437

uint32_t b; // store in fixed point, [31:20] signed integer, [19:0] fractional bits

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

438

uint32_t c; // store in fixed point, [31:20] signed integer, [19:0] fractional bits

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

442

uint32_t m; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

443

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

447

uint32_t a; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

448

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

449

uint32_t c; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

462

uint32_t Fset[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //in GHz, store in IEEE float format

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

463

uint32_t Vdroop[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //in V , store in IEEE float format

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

606

uint32_t Version;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

609

uint32_t FeaturesToRun[NUM_FEATURES / 32];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

622

uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime)

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

629

uint32_t ApccPlusResidencyLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

635

uint32_t PaddingAPCC;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

640

uint32_t ThrottlerControlMask; // See Throtter masks defines

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

643

uint32_t FwDStateMask; // See FW DState masks defines

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

692

uint32_t Paddingclks;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

696

uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

721

uint32_t GfxGpoVotingAllow; //For indicating which feature changes should result in a GPO table recalculation

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

723

uint32_t GfxGpoPadding32[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

734

uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

739

uint32_t DcsParamPadding[5];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

816

uint32_t DebugOverrides;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

830

uint32_t VcBtcPsmA; // A_PSM

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

831

uint32_t VcBtcPsmB; // B_PSM

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

832

uint32_t VcBtcVminA; // A_VMIN

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

833

uint32_t VcBtcVminB; // B_VMIN

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

839

uint32_t SkuReserved[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

845

uint32_t GamingClk[6];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

883

uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

928

uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

953

uint32_t BoardReserved[11];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

958

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

966

uint32_t Version;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

969

uint32_t FeaturesToRun[NUM_FEATURES / 32];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

982

uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime)

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

989

uint32_t ApccPlusResidencyLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h

995

uint32_t PaddingAPCC;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

114

uint32_t fclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

115

uint32_t memclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

116

uint32_t voltage;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

120

uint32_t vclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

121

uint32_t dclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

128

uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

129

uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

130

uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

131

uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

132

uint32_t IspiClocks[NUM_ISPICLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

133

uint32_t IspxClocks[NUM_ISPXCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

136

uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

140

uint32_t MinGfxClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

141

uint32_t MaxGfxClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

230

uint32_t SampleStartTime;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

231

uint32_t SampleStopTime;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

33

uint32_t numFractionalBits;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h

74

uint32_t MmHubPadding[7]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

112

uint32_t Freq; // In MHz

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

113

uint32_t Vol; // Millivolts with 2 fractional bits

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

34

uint32_t numFractionalBits;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h

75

uint32_t MmHubPadding[7]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

221

uint32_t Spare[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

222

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

226

uint32_t a; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

227

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

228

uint32_t c; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

232

uint32_t m; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

233

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

274

uint32_t Version;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

277

uint32_t FeaturesToRun[2];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

302

uint32_t FidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

304

uint32_t FidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

307

uint32_t StartupFidPll0; //GFXAVFSCLK, SOCCLK, MP0CLK, MPIOCLK, DXIOCLK

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

308

uint32_t StartupFidPll4; //VCLK, DCLK, WAFLCLK

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

309

uint32_t StartupFidPll5; //SMNCLK, MP1CLK, LCLK

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

338

uint32_t StartupGfxclkFid;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

388

uint32_t ApccPlusResidencyLimit; //PCC residency % (0-100)

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

395

uint32_t spare3[14];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

416

uint32_t BoardVoltageCoeffA; // decode by /1000

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

417

uint32_t BoardVoltageCoeffB; // decode by /1000

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

451

uint32_t reserved[14];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

466

uint32_t Spare[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

468

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

490

uint32_t ThrottlerStatus ;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

492

uint32_t PublicSerialNumLower32;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

493

uint32_t PublicSerialNumUpper32;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

495

uint32_t GfxBusyAcc ;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

496

uint32_t DramBusyAcc ;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

497

uint32_t EnergyAcc64bitLow ; //15.259uJ resolution

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

498

uint32_t EnergyAcc64bitHigh ;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

499

uint32_t TimeStampLow ; //10ns resolution

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

500

uint32_t TimeStampHigh ;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

503

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

513

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

522

uint32_t eccPadding;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h

532

uint32_t eccPadding;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1020

uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1022

uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1024

uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1026

uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1035

uint32_t SpareVmin[9];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1053

uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1080

uint32_t GfxOffEntryHysteresis;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1081

uint32_t GfxoffSpare[15];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1084

uint32_t DfllBtcMasterScalerM;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1086

uint32_t DfllBtcSlaveScalerM;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1089

uint32_t DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1090

uint32_t DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1092

uint32_t DfllL2FrequencyBoostM; //Unitless (float)

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1093

uint32_t DfllL2FrequencyBoostB; //In MHz (integer)

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1094

uint32_t GfxGpoSpare[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1104

uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1111

uint32_t DcsFoptM; //Tuning paramters to shift Fopt calculation

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1112

uint32_t DcsFoptB; //Tuning paramters to shift Fopt calculation

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1114

uint32_t DcsSpare[11];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1153

uint32_t TempInputSelectMask;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1179

uint32_t FanSpare[13];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1186

uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1187

uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1189

uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1191

uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1192

uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1194

uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1195

uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1196

uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1197

uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1199

uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1201

uint32_t dGbV_dT_vmin;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1202

uint32_t dGbV_dT_vmax;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1205

uint32_t V2F_vmin_range_low;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1206

uint32_t V2F_vmin_range_high;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1207

uint32_t V2F_vmax_range_low;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1208

uint32_t V2F_vmax_range_high;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1212

uint32_t GfxAvfsSpare[32];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1230

uint32_t SocAvfsSpare[32];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1244

uint32_t reserved[22];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1247

uint32_t DebugOverrides;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1269

uint32_t Spare[41];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1272

uint32_t MmHubPadding[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1278

uint32_t Version; //should be unique to each board type

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1304

uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1356

uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1357

uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1363

uint32_t BoardSpare[63];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1368

uint32_t MmHubPadding[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1393

uint32_t Spare[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1395

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1417

uint32_t Spare[32];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1420

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1425

uint32_t CurrClock[PPCLK_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1442

uint32_t MetricsCounter;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1452

uint32_t EnergyAccumulator;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1472

uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1473

uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1474

uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1482

uint32_t PublicSerialNumberLower;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1483

uint32_t PublicSerialNumberUpper;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1489

uint32_t Spare[29];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1492

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1518

uint32_t Spare[16];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1520

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1533

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1547

uint32_t Gfx_PD_Data_limit_a; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1548

uint32_t Gfx_PD_Data_limit_b; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1549

uint32_t Gfx_PD_Data_limit_c; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1550

uint32_t Gfx_PD_Data_error_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1551

uint32_t Gfx_PD_Data_error_rate_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1562

uint32_t Fclk_PD_Data_limit_a; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1563

uint32_t Fclk_PD_Data_limit_b; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1564

uint32_t Fclk_PD_Data_limit_c; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1565

uint32_t Fclk_PD_Data_error_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1566

uint32_t Fclk_PD_Data_error_rate_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1568

uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

1579

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

376

uint32_t Spare[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

377

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

387

uint32_t eccPadding;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

416

uint32_t a; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

417

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

418

uint32_t c; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

422

uint32_t m; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

423

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

427

uint32_t a; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

428

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

429

uint32_t c; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

507

uint32_t Padding3[3];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

696

uint32_t FeatureCtrlMask;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

701

uint32_t Reserved;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

725

uint32_t Spare[13];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

726

uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

735

uint32_t FeatureCtrlMask;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

762

uint32_t Spare[13];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

854

uint32_t InitVcoFreqPll0;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

855

uint32_t InitVcoFreqPll1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

856

uint32_t InitVcoFreqPll2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

857

uint32_t InitVcoFreqPll3;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

858

uint32_t InitVcoFreqPll4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

859

uint32_t InitVcoFreqPll5;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

860

uint32_t InitVcoFreqPll6;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

869

uint32_t Spare[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

900

uint32_t Spare[11];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

912

uint32_t Reserved[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

941

uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different)

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

944

uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

977

uint32_t FitControllerFailureRateLimit; //in IEEE float

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

979

uint32_t FitControllerGfxDutyCycle; // in IEEE float

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

981

uint32_t FitControllerSocDutyCycle; // in IEEE float

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

984

uint32_t FitControllerSocOffset; //in IEEE float

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

986

uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

989

uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

992

uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

113

uint32_t FClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

114

uint32_t MemClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

115

uint32_t Voltage;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

123

uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

124

uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

125

uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

126

uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

127

uint32_t VClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

128

uint32_t DClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

129

uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

139

uint32_t MinGfxClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

140

uint32_t MaxGfxClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

187

uint32_t ApuPower; //[mW]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

188

uint32_t dGpuPower; //[mW]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

214

uint32_t MetricsCounter; //Counts the # of metrics table parameter reads per update to the metrics table, i.e. if the metrics table update happens every 1 second, this value could be up to 1000 if the smu collected metrics data every cycle, or as low as 0 if the smu was asleep the whole time. Reset to 0 after writing.

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

34

uint32_t numFractionalBits;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

75

uint32_t MmHubPadding[7]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

111

uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

112

uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

113

uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

114

uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

115

uint32_t VClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

116

uint32_t DClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

117

uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

125

uint32_t MinGfxClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

126

uint32_t MaxGfxClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

74

uint32_t MmHubPadding[7]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

78

uint32_t FClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

79

uint32_t MemClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h

80

uint32_t Voltage;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h

171

uint32_t Spare[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h

172

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1001

uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1029

uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1031

uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1033

uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1035

uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1044

uint32_t SpareVmin[9];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1062

uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1088

uint32_t GfxOffEntryHysteresis; //For RLC to count after it enters CGCG, and before triggers GFXOFF entry

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1089

uint32_t GfxoffSpare[15];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1092

uint32_t DfllBtcMasterScalerM;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1094

uint32_t DfllBtcSlaveScalerM;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1096

uint32_t DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1097

uint32_t DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1098

uint32_t GfxGpoSpare[10];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1108

uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1114

uint32_t DcsSpare[14];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1155

uint32_t TempInputSelectMask;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1181

uint32_t FanSpare[13];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1187

uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1188

uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1190

uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1192

uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1193

uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1195

uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1196

uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1197

uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1198

uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1200

uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1202

uint32_t dGbV_dT_vmin;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1203

uint32_t dGbV_dT_vmax;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1205

uint32_t V2F_vmin_range_low;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1206

uint32_t V2F_vmin_range_high;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1207

uint32_t V2F_vmax_range_low;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1208

uint32_t V2F_vmax_range_high;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1212

uint32_t GfxAvfsSpare[32];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1230

uint32_t SocAvfsSpare[32];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1247

uint32_t DebugOverrides;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1263

uint32_t Spare[43];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1266

uint32_t MmHubPadding[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1272

uint32_t Version; //should be unique to each board type

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1298

uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1349

uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1350

uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1356

uint32_t BoardSpare[63];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1361

uint32_t MmHubPadding[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1386

uint32_t Spare[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1388

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1410

uint32_t Spare[32];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1413

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1418

uint32_t CurrClock[PPCLK_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1435

uint32_t MetricsCounter ;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1445

uint32_t EnergyAccumulator;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1463

uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1464

uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1465

uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1473

uint32_t PublicSerialNumberLower;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1474

uint32_t PublicSerialNumberUpper;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1479

uint32_t Spare[30];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1482

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1508

uint32_t Spare[16];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1510

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1523

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1537

uint32_t Gfx_PD_Data_limit_a; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1538

uint32_t Gfx_PD_Data_limit_b; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1539

uint32_t Gfx_PD_Data_limit_c; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1540

uint32_t Gfx_PD_Data_error_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1541

uint32_t Gfx_PD_Data_error_rate_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1552

uint32_t Fclk_PD_Data_limit_a; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1553

uint32_t Fclk_PD_Data_limit_b; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1554

uint32_t Fclk_PD_Data_limit_c; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1555

uint32_t Fclk_PD_Data_error_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1556

uint32_t Fclk_PD_Data_error_rate_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1558

uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

1569

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

377

uint32_t Spare[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

378

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

388

uint32_t eccPadding;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

417

uint32_t a; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

418

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

419

uint32_t c; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

423

uint32_t m; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

424

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

428

uint32_t a; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

429

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

430

uint32_t c; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

508

uint32_t Padding3[3];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

706

uint32_t FeatureCtrlMask;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

711

uint32_t Reserved;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

736

uint32_t Spare[12];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

737

uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

746

uint32_t FeatureCtrlMask;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

774

uint32_t Spare[12];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

863

uint32_t InitVcoFreqPll0;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

864

uint32_t InitVcoFreqPll1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

865

uint32_t InitVcoFreqPll2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

866

uint32_t InitVcoFreqPll3;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

867

uint32_t InitVcoFreqPll4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

868

uint32_t InitVcoFreqPll5;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

869

uint32_t InitVcoFreqPll6;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

878

uint32_t Spare[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

909

uint32_t Spare[11];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

921

uint32_t Reserved[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

950

uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different)

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

953

uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

986

uint32_t FitControllerFailureRateLimit; //in IEEE float

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

988

uint32_t FitControllerGfxDutyCycle; // in IEEE float

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

990

uint32_t FitControllerSocDutyCycle; // in IEEE float

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

993

uint32_t FitControllerSocOffset; //in IEEE float

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

995

uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h

998

uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

112

uint32_t FClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

113

uint32_t MemClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

114

uint32_t Voltage;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

122

uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

123

uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

124

uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

125

uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

126

uint32_t VClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

127

uint32_t DClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

128

uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

138

uint32_t MinGfxClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

139

uint32_t MaxGfxClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

187

uint32_t ApuPower; //[mW]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

188

uint32_t dGpuPower; //[mW]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

33

uint32_t numFractionalBits;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_yellow_carp.h

74

uint32_t MmHubPadding[7]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1000

uint32_t Spare[11];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1012

uint32_t Reserved[3];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1042

uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1044

uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1046

uint32_t DebugOverrides;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1048

uint32_t Spare[2];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1053

uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different)

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1078

uint32_t FitControllerFailureRateLimit; //in IEEE float

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1080

uint32_t FitControllerGfxDutyCycle; // in IEEE float

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1082

uint32_t FitControllerSocDutyCycle; // in IEEE float

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1085

uint32_t FitControllerSocOffset; //in IEEE float

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1087

uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1090

uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1119

uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1121

uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1123

uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1125

uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1135

uint32_t SpareVmin[6];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1153

uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1175

uint32_t GfxOffEntryHysteresis; //For RLC to count after it enters CGCG, and before triggers GFXOFF entry

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1176

uint32_t GfxoffSpare[15];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1181

uint32_t DfllBtcMasterScalerM;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1183

uint32_t DfllBtcSlaveScalerM;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1186

uint32_t DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1187

uint32_t DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1188

uint32_t GfxDfllSpare[9];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1191

uint32_t DvoPsmDownThresholdVoltage; //Voltage float

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1192

uint32_t DvoPsmUpThresholdVoltage; //Voltage float

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1193

uint32_t DvoFmaxLowScaler; //Unitless float

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1196

uint32_t PaddingDcs;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1201

uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1206

uint32_t DcsPfGfxFopt; //Default to GFX FMIN

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1207

uint32_t DcsPfUclkFopt; //Default to UCLK FMIN

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1211

uint32_t DcsFoptM; //Tuning paramters to shift Fopt calculation, IEEE754 float

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1212

uint32_t DcsFoptB; //Tuning paramters to shift Fopt calculation, IEEE754 float

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1213

uint32_t DcsSpare[9];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1228

uint32_t PaddingFclk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1240

uint32_t SocHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //new added for Soc domain

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1241

uint32_t GfxL2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1245

uint32_t PsmDidt_StaticDroop_A[PP_NUM_PSM_DIDT_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1246

uint32_t PsmDidt_StaticDroop_B[PP_NUM_PSM_DIDT_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1247

uint32_t PsmDidt_DynDroop_A[PP_NUM_PSM_DIDT_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1248

uint32_t PsmDidt_DynDroop_B[PP_NUM_PSM_DIDT_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1249

uint32_t spare_HwRtAvfsFuses[19];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1251

uint32_t SocCommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1252

uint32_t GfxCommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1254

uint32_t SocFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1255

uint32_t GfxL2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1257

uint32_t spare_FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1259

uint32_t Soc_Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1260

uint32_t Soc_Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1261

uint32_t Soc_Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1262

uint32_t Soc_Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1264

uint32_t Gfx_Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1265

uint32_t Gfx_Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1266

uint32_t Gfx_Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1267

uint32_t Gfx_Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1269

uint32_t Gfx_Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1270

uint32_t Soc_Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1272

uint32_t dGbV_dT_vmin;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1273

uint32_t dGbV_dT_vmax;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1275

uint32_t PaddingV2F[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1279

uint32_t GfxAvfsSpare[29];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1297

uint32_t SocAvfsSpare[29];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1326

uint32_t AptUclkGfxclkLookupHyst[POWER_SOURCE_COUNT][6];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1327

uint32_t AptPadding;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1331

uint32_t GfxXvminDidtResetDDWait;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1332

uint32_t GfxXvminDidtClkStopWait;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1333

uint32_t GfxXvminDidtFcsStepCtrl;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1334

uint32_t GfxXvminDidtFcsWaitCtrl;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1337

uint32_t PsmModeEnabled; //0: all disabled 1: static mode only 2: dynamic mode only 3:static + dynamic mode

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1338

uint32_t P2v_a; // floating point in U32 format

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1339

uint32_t P2v_b;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1340

uint32_t P2v_c;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1341

uint32_t T2p_a;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1342

uint32_t T2p_b;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1343

uint32_t T2p_c;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1344

uint32_t P2vTemp;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1350

uint32_t PsmDidtStallPattern; //Will be written to both pattern 1 and didt_static_level_prog

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1352

uint32_t CacEdcCacLeakageC0;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1353

uint32_t CacEdcCacLeakageC1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1354

uint32_t CacEdcCacLeakageC2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1355

uint32_t CacEdcCacLeakageC3;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1356

uint32_t CacEdcCacLeakageC4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1357

uint32_t CacEdcCacLeakageC5;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1358

uint32_t CacEdcGfxClkScalar;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1359

uint32_t CacEdcGfxClkIntercept;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1360

uint32_t CacEdcCac_m;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1361

uint32_t CacEdcCac_b;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1362

uint32_t CacEdcCurrLimitGuardband;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1363

uint32_t CacEdcDynToTotalCacRatio;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1365

uint32_t XVmin_Gfx_EdcThreshScalar;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1366

uint32_t XVmin_Gfx_EdcEnableFreq;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1367

uint32_t XVmin_Gfx_EdcPccAsStepCtrl;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1368

uint32_t XVmin_Gfx_EdcPccAsWaitCtrl;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1372

uint32_t XVmin_Soc_EdcThreshScalar;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1373

uint32_t XVmin_Soc_EdcEnableFreq;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1374

uint32_t XVmin_Soc_EdcThreshold; // LPF: number of cycles Xvmin_trig_filt will react.

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1401

uint32_t Spare;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1404

uint32_t MmHubPadding[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1423

uint32_t SettingOverrideMask;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1428

uint32_t Version; //should be unique to each board type

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1437

uint32_t Svi3SvcSpeed;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1492

uint32_t Paddign1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1493

uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1499

uint32_t LoadlineGfx;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1500

uint32_t LoadlineSoc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1501

uint32_t GfxEdcLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1502

uint32_t SocEdcLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1504

uint32_t RestBoardPower; //power consumed by board that is not captured by the SVI3 input telemetry

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1505

uint32_t ConnectorsImpedance; // impedance of the input ATX power connectors

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1512

uint32_t BoardSpare[52];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1517

uint32_t MmHubPadding[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1545

uint32_t TempInputSelectMask;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1572

uint32_t FanSpare2[12];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1574

uint32_t ODFeatureCtrlMask;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1586

uint32_t CustomSkuSpare32b[10];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1591

uint32_t MmHubPadding[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1618

uint32_t Spare[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1620

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1642

uint32_t Spare[32];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1645

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1650

uint32_t CurrClock[PPCLK_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1684

uint32_t MetricsCounter ;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1694

uint32_t EnergyAccumulator;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1714

uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1715

uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1716

uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1724

uint32_t PublicSerialNumberLower;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1725

uint32_t PublicSerialNumberUpper;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1731

uint32_t Spare[30];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1734

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1760

uint32_t Spare[16];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1762

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1777

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1791

uint32_t Gfx_PD_Data_limit_a; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1792

uint32_t Gfx_PD_Data_limit_b; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1793

uint32_t Gfx_PD_Data_limit_c; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1794

uint32_t Gfx_PD_Data_error_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1795

uint32_t Gfx_PD_Data_error_rate_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1806

uint32_t Fclk_PD_Data_limit_a; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1807

uint32_t Fclk_PD_Data_limit_b; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1808

uint32_t Fclk_PD_Data_limit_c; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1809

uint32_t Fclk_PD_Data_error_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1810

uint32_t Fclk_PD_Data_error_rate_coeff; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1812

uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

1822

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

377

uint32_t Spare[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

378

uint32_t MmHubPadding[8]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

388

uint32_t eccPadding;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

432

uint32_t a; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

433

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

434

uint32_t c; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

438

uint32_t m; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

439

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

443

uint32_t a; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

444

uint32_t b; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

445

uint32_t c; // store in IEEE float format in this variable

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

521

uint32_t Padding3[3];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

752

uint32_t FeatureCtrlMask;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

805

uint32_t Spare[9];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

806

uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

815

uint32_t FeatureCtrlMask;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

864

uint32_t Spare[5];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

953

uint32_t InitVcoFreqPll0; //smu_socclk_t

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

954

uint32_t InitVcoFreqPll1; //smu_displayclk_t

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

955

uint32_t InitVcoFreqPll2; //smu_nbioclk_t

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

956

uint32_t InitVcoFreqPll3; //smu_vcnclk_t

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

957

uint32_t InitVcoFreqPll4; //smu_fclk_t

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

958

uint32_t InitVcoFreqPll5; //smu_uclk_01_t

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

959

uint32_t InitVcoFreqPll6; //smu_uclk_23_t

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

960

uint32_t InitVcoFreqPll7; //smu_uclk_45_t

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

961

uint32_t InitVcoFreqPll8; //smu_uclk_67_t

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h

971

uint32_t Spare[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

112

uint32_t UClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

113

uint32_t MemClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

114

uint32_t Voltage;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

122

uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

123

uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

124

uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

125

uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

126

uint32_t VClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

127

uint32_t DClocks[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

128

uint32_t VPEClocks[NUM_VPE_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

129

uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

130

uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

131

uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

144

uint32_t MinGfxClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

145

uint32_t MaxGfxClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

151

uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

152

uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

153

uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

154

uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

155

uint32_t VClocks0[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

156

uint32_t VClocks1[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

157

uint32_t DClocks0[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

158

uint32_t DClocks1[NUM_VCN_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

159

uint32_t VPEClocks[NUM_VPE_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

160

uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

161

uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

162

uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

174

uint32_t MinGfxClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

175

uint32_t MaxGfxClk;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

202

uint32_t ApuPower; //Time filtered APU power [mW]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

203

uint32_t GfxPower; //Time filtered GFX power [mW]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

204

uint32_t dGpuPower; //Time filtered dGPU power [mW]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

205

uint32_t SocketPower; //Time filtered power used for PPT/STAPM [APU+dGPU] [mW]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

206

uint32_t AllCorePower; //Time filtered sum of core power across all cores in the socket [mW]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

207

uint32_t FilterAlphaValue; //Metrics table alpha filter time constant [us]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

208

uint32_t MetricsCounter; //Counter that is incremented on every metrics table update [PM_TIMER cycles]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

213

uint32_t ThrottleResidency_PROCHOT; //Counter that is incremented on every metrics table update when PROCHOT was engaged [PM_TIMER cycles]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

214

uint32_t ThrottleResidency_SPL; //Counter that is incremented on every metrics table update when SPL was engaged [PM_TIMER cycles]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

215

uint32_t ThrottleResidency_FPPT; //Counter that is incremented on every metrics table update when fast PPT was engaged [PM_TIMER cycles]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

216

uint32_t ThrottleResidency_SPPT; //Counter that is incremented on every metrics table update when slow PPT was engaged [PM_TIMER cycles]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

217

uint32_t ThrottleResidency_THM_CORE; //Counter that is incremented on every metrics table update when CORE thermal throttling was engaged [PM_TIMER cycles]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

218

uint32_t ThrottleResidency_THM_GFX; //Counter that is incremented on every metrics table update when GFX thermal throttling was engaged [PM_TIMER cycles]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

219

uint32_t ThrottleResidency_THM_SOC; //Counter that is incremented on every metrics table update when SOC thermal throttling was engaged [PM_TIMER cycles]

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

222

uint32_t spare[6];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

29

uint32_t numFractionalBits;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

70

uint32_t MmHubPadding[7]; // SMU internal use

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_0_ppsmc.h

135

typedef uint32_t PPSMC_Result;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_0_ppsmc.h

136

typedef uint32_t PPSMC_Msg;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_pmfw.h

100

uint32_t DpmTimerID : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_pmfw.h

101

uint32_t DpmHubID : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_pmfw.h

102

uint32_t DpmHubTask : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_pmfw.h

104

uint32_t GfxStatus : 2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_pmfw.h

105

uint32_t GfxoffStatus : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_pmfw.h

106

uint32_t CpuOff : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_pmfw.h

107

uint32_t VddOff : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_pmfw.h

108

uint32_t InUlv : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_pmfw.h

109

uint32_t InS0i2 : 2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_pmfw.h

110

uint32_t InWhisperMode : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_pmfw.h

111

uint32_t spare1 : 16;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_pmfw.h

113

uint32_t P2JobHandler : 32;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_pmfw.h

98

uint32_t DpmHandlerID : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_pmfw.h

99

uint32_t ActivityMonitorID : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

123

uint32_t SPARE1 : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

124

uint32_t SPARE2 : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

125

uint32_t SPARE3 : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

126

uint32_t CurrLevel_LCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

127

uint32_t CurrLevel_MP0CLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

128

uint32_t CurrLevel_FCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

129

uint32_t CurrLevel_SOCCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

130

uint32_t CurrLevel_DCEFCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

132

uint32_t SPARE4 : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

133

uint32_t SPARE5 : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

134

uint32_t SPARE6 : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

135

uint32_t TargLevel_LCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

136

uint32_t TargLevel_MP0CLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

137

uint32_t TargLevel_FCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

138

uint32_t TargLevel_SOCCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

139

uint32_t TargLevel_DCEFCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

141

uint32_t CurrLevel_SHUBCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

142

uint32_t TargLevel_SHUBCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

143

uint32_t Reserved : 24;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

145

uint32_t Reserved2[2];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_8_pmfw.h

147

uint32_t FeatureStatus[NUM_FEATURES / 32];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

200

uint32_t MaxSocketTemperature;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

201

uint32_t MaxVrTemperature;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

202

uint32_t MaxHbmTemperature;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

208

uint32_t SocketPowerLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

209

uint32_t SocketPower;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

219

uint32_t GfxclkFrequencyLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

220

uint32_t FclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

221

uint32_t UclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

222

uint32_t SocclkFrequency[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

223

uint32_t VclkFrequency[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

224

uint32_t DclkFrequency[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

225

uint32_t LclkFrequency[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

229

uint32_t MaxLclkDpmRange;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

230

uint32_t MinLclkDpmRange;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

233

uint32_t XgmiWidth;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

234

uint32_t XgmiBitrate;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

239

uint32_t SocketGfxBusy;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

240

uint32_t DramBandwidthUtilization;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

243

uint32_t MaxDramBandwidth;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

248

uint32_t ProchotResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

249

uint32_t PptResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

250

uint32_t SocketThmResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

251

uint32_t VrThmResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

252

uint32_t HbmThmResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

253

uint32_t GfxLockXCDMak;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

256

uint32_t GfxclkFrequency[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

263

uint32_t PcieBandwidth[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

264

uint32_t PCIeL0ToRecoveryCountAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

265

uint32_t PCIenReplayAAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

266

uint32_t PCIenReplayARolloverCountAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

267

uint32_t PCIeNAKSentCountAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

268

uint32_t PCIeNAKReceivedCountAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

271

uint32_t VcnBusy[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

272

uint32_t JpegBusy[40];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

275

uint32_t PCIeLinkSpeed;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

276

uint32_t PCIeLinkWidth;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

279

uint32_t GfxBusy[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

283

uint32_t PCIeOtherEndRecoveryAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

291

uint32_t AidTemperature[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

292

uint32_t XcdTemperature[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

293

uint32_t HbmTemperature[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

310

uint32_t NodePowerLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

311

uint32_t NodePower;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

312

uint32_t GlobalPPTResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

317

uint32_t AccumulationCounter;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

318

uint32_t InstGfxclk_TargFreq;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

342

uint32_t MaxSocketPowerLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

345

uint32_t MaxGfxclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

346

uint32_t MinGfxclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

347

uint32_t FclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

348

uint32_t UclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

349

uint32_t SocclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

350

uint32_t VclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

351

uint32_t DclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

352

uint32_t LclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

359

uint32_t MaxXgmiWidth;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

360

uint32_t MaxXgmiBitrate;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

363

uint32_t InputTelemetryVoltageInmV;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

366

uint32_t pldmVersion[2];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

369

uint32_t MaxNodePowerLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h

145

typedef uint32_t PPSMC_Result;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h

146

typedef uint32_t PPSMC_MSG;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

100

uint32_t DpmHandlerID : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

101

uint32_t ActivityMonitorID : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

102

uint32_t DpmTimerID : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

103

uint32_t DpmHubID : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

104

uint32_t DpmHubTask : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

106

uint32_t GfxoffStatus : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

107

uint32_t GfxStatus : 2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

108

uint32_t CpuOff : 2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

109

uint32_t VddOff : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

110

uint32_t InUlv : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

111

uint32_t InWhisperMode : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

112

uint32_t spare0 : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

113

uint32_t ZstateStatus : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

114

uint32_t spare1 : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

115

uint32_t DstateFun : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

116

uint32_t DstateDev : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

118

uint32_t P2JobHandler :24;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

119

uint32_t RsmuPmiP2FinishedCnt : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

121

uint32_t PostCode :32;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

123

uint32_t MsgPortBusy :15;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

124

uint32_t RsmuPmiP1Pending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

125

uint32_t DfCstateExitPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

126

uint32_t Pc6EntryPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

127

uint32_t Pc6ExitPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

128

uint32_t WarmResetPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

129

uint32_t Mp0ClkPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

130

uint32_t spare2 : 3;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

131

uint32_t RsmuPmiP2PendingCnt : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h

133

uint32_t IdleMask :32;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

100

uint32_t ActivityMonitorID : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

101

uint32_t DpmTimerID : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

102

uint32_t DpmHubID : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

103

uint32_t DpmHubTask : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

105

uint32_t GfxoffStatus : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

106

uint32_t GfxStatus : 2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

107

uint32_t CpuOff : 2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

108

uint32_t VddOff : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

109

uint32_t InUlv : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

110

uint32_t InWhisperMode : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

111

uint32_t spare0 : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

112

uint32_t ZstateStatus : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

113

uint32_t spare1 : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

114

uint32_t DstateFun : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

115

uint32_t DstateDev : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

117

uint32_t P2JobHandler :32;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

119

uint32_t PostCode :32;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

121

uint32_t MsgPortBusy :15;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

122

uint32_t RsmuPmiP1Pending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

123

uint32_t RsmuPmiP2PendingCnt : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

124

uint32_t DfCstateExitPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

125

uint32_t Pc6EntryPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

126

uint32_t Pc6ExitPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

127

uint32_t WarmResetPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

128

uint32_t Mp0ClkPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

129

uint32_t spare2 : 3;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

131

uint32_t IdleMask :32;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

99

uint32_t DpmHandlerID : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

100

uint32_t TargLevel_VCN : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

101

uint32_t TargLevel_LCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

102

uint32_t TargLevel_MP0CLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

103

uint32_t TargLevel_FCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

104

uint32_t TargLevel_SOCCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

105

uint32_t TargLevel_DCFCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

107

uint32_t CurrLevel_SHUBCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

108

uint32_t TargLevel_SHUBCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

109

uint32_t InUlv : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

110

uint32_t InS0i2 : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

111

uint32_t InWhisperMode : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

112

uint32_t GfxOn : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

113

uint32_t RsmuCalBusyDpmIndex: 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

114

uint32_t DpmHandlerId : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

115

uint32_t DpmTimerId : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

117

uint32_t ReadWriteSmnRegAddr: 32;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

119

uint32_t Reserved1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

121

uint32_t FeatureStatus[NUM_FEATURES / 32];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

89

uint32_t CurrLevel_ACP : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

90

uint32_t CurrLevel_ISP : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

91

uint32_t CurrLevel_VCN : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

92

uint32_t CurrLevel_LCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

93

uint32_t CurrLevel_MP0CLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

94

uint32_t CurrLevel_FCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

95

uint32_t CurrLevel_SOCCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

96

uint32_t CurrLevel_DCFCLK : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

98

uint32_t TargLevel_ACP : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h

99

uint32_t TargLevel_ISP : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

134

uint32_t AccumulationCounter;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

137

uint32_t MaxSocketTemperature;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

138

uint32_t MaxVrTemperature;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

139

uint32_t MaxHbmTemperature;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

145

uint32_t SocketPowerLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

146

uint32_t MaxSocketPowerLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

147

uint32_t SocketPower;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

158

uint32_t CclkFrequencyLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

159

uint32_t GfxclkFrequencyLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

160

uint32_t FclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

161

uint32_t UclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

162

uint32_t SocclkFrequency[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

163

uint32_t VclkFrequency[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

164

uint32_t DclkFrequency[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

165

uint32_t LclkFrequency[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

170

uint32_t MaxCclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

171

uint32_t MinCclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

172

uint32_t MaxGfxclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

173

uint32_t MinGfxclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

174

uint32_t FclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

175

uint32_t UclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

176

uint32_t SocclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

177

uint32_t VclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

178

uint32_t DclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

179

uint32_t LclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

180

uint32_t MaxLclkDpmRange;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

181

uint32_t MinLclkDpmRange;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

184

uint32_t XgmiWidth;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

185

uint32_t XgmiBitrate;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

190

uint32_t SocketC0Residency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

191

uint32_t SocketGfxBusy;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

192

uint32_t DramBandwidthUtilization;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

196

uint32_t MaxDramBandwidth;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

201

uint32_t ProchotResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

202

uint32_t PptResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

203

uint32_t SocketThmResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

204

uint32_t VrThmResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

205

uint32_t HbmThmResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

206

uint32_t GfxLockXCDMak;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

209

uint32_t GfxclkFrequency[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

221

uint32_t PcieBandwidth[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

222

uint32_t PCIeL0ToRecoveryCountAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

223

uint32_t PCIenReplayAAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

224

uint32_t PCIenReplayARolloverCountAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

225

uint32_t PCIeNAKSentCountAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

226

uint32_t PCIeNAKReceivedCountAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

229

uint32_t VcnBusy[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

230

uint32_t JpegBusy[32];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

233

uint32_t PCIeLinkSpeed;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

234

uint32_t PCIeLinkWidth;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

237

uint32_t GfxBusy[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

241

uint32_t PCIeOtherEndRecoveryAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

252

uint32_t AccumulationCounter;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

255

uint32_t MaxSocketTemperature;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

256

uint32_t MaxVrTemperature;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

257

uint32_t MaxHbmTemperature;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

263

uint32_t SocketPowerLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

264

uint32_t MaxSocketPowerLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

265

uint32_t SocketPower;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

276

uint32_t CclkFrequencyLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

277

uint32_t GfxclkFrequencyLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

278

uint32_t FclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

279

uint32_t UclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

280

uint32_t SocclkFrequency[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

281

uint32_t VclkFrequency[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

282

uint32_t DclkFrequency[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

283

uint32_t LclkFrequency[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

288

uint32_t MaxCclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

289

uint32_t MinCclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

290

uint32_t MaxGfxclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

291

uint32_t MinGfxclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

292

uint32_t FclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

293

uint32_t UclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

294

uint32_t SocclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

295

uint32_t VclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

296

uint32_t DclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

297

uint32_t LclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

298

uint32_t MaxLclkDpmRange;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

299

uint32_t MinLclkDpmRange;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

302

uint32_t XgmiWidth;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

303

uint32_t XgmiBitrate;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

308

uint32_t SocketC0Residency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

309

uint32_t SocketGfxBusy;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

310

uint32_t DramBandwidthUtilization;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

314

uint32_t MaxDramBandwidth;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

319

uint32_t ProchotResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

320

uint32_t PptResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

321

uint32_t SocketThmResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

322

uint32_t VrThmResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

323

uint32_t HbmThmResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

324

uint32_t GfxLockXCDMak;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

327

uint32_t GfxclkFrequency[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

339

uint32_t VcnBusy[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

340

uint32_t JpegBusy[32];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

348

uint32_t MaxSocketTemperature;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

349

uint32_t MaxVrTemperature;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

350

uint32_t MaxHbmTemperature;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

356

uint32_t SocketPowerLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

357

uint32_t MaxSocketPowerLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

358

uint32_t SocketPower;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

369

uint32_t GfxclkFrequencyLimit;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

370

uint32_t FclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

371

uint32_t UclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

372

uint32_t SocclkFrequency[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

373

uint32_t VclkFrequency[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

374

uint32_t DclkFrequency[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

375

uint32_t LclkFrequency[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

379

uint32_t MaxGfxclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

380

uint32_t MinGfxclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

381

uint32_t FclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

382

uint32_t UclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

383

uint32_t SocclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

384

uint32_t VclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

385

uint32_t DclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

386

uint32_t LclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

387

uint32_t MaxLclkDpmRange;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

388

uint32_t MinLclkDpmRange;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

391

uint32_t XgmiWidth;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

392

uint32_t XgmiBitrate;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

397

uint32_t SocketGfxBusy;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

398

uint32_t DramBandwidthUtilization;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

402

uint32_t MaxDramBandwidth;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

407

uint32_t ProchotResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

408

uint32_t PptResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

409

uint32_t SocketThmResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

410

uint32_t VrThmResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

411

uint32_t HbmThmResidencyAcc;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

412

uint32_t GfxLockXCDMak;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

415

uint32_t GfxclkFrequency[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

426

uint32_t PcieBandwidth[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

427

uint32_t PCIeL0ToRecoveryCountAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

428

uint32_t PCIenReplayAAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

429

uint32_t PCIenReplayARolloverCountAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

430

uint32_t PCIeNAKSentCountAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

431

uint32_t PCIeNAKReceivedCountAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

434

uint32_t VcnBusy[4];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

435

uint32_t JpegBusy[32];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

438

uint32_t PCIeLinkSpeed;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

439

uint32_t PCIeLinkWidth;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

442

uint32_t GfxBusy[8];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

446

uint32_t PCIeOtherEndRecoveryAcc; // The Pcie counter itself is accumulated

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

455

uint32_t AccumulationCounter;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

456

uint32_t InstGfxclk_TargFreq;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

465

uint32_t InputTelemetryVoltageInmV;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h

467

uint32_t pldmVersion[2];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h

120

typedef uint32_t PPSMC_Result;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h

121

typedef uint32_t PPSMC_MSG;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

102

uint32_t Signature;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

108

uint32_t ImageVersion;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

109

uint32_t ImageVersion2; // This is repeated because DW0 cannot be written in SRAM due to HW bug.

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

110

uint32_t Padding0[3];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

111

uint32_t SizeFWSigned;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

112

uint32_t Padding1[25];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

113

uint32_t FirmwareType;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

114

uint32_t Filler[32];

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

119

uint32_t DpmHandlerID : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

120

uint32_t ActivityMonitorID : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

121

uint32_t DpmTimerID : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

122

uint32_t DpmHubID : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

123

uint32_t DpmHubTask : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

125

uint32_t CclkSyncStatus : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

126

uint32_t Ccx0CpuOff : 2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

127

uint32_t Ccx1CpuOff : 2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

128

uint32_t GfxOffStatus : 2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

129

uint32_t VddOff : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

130

uint32_t InWhisperMode : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

131

uint32_t ZstateStatus : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

132

uint32_t spare0 : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

133

uint32_t DstateFun : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

134

uint32_t DstateDev : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

136

uint32_t P2JobHandler :24;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

137

uint32_t RsmuPmiP2PendingCnt : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

139

uint32_t PostCode :32;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

141

uint32_t MsgPortBusy :24;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

142

uint32_t RsmuPmiP1Pending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

143

uint32_t DfCstateExitPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

144

uint32_t Ccx0Pc6ExitPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

145

uint32_t Ccx1Pc6ExitPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

146

uint32_t WarmResetPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

147

uint32_t spare1 : 3;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

149

uint32_t IdleMask :32;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

156

uint32_t DpmHandlerID : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

157

uint32_t ActivityMonitorID : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

158

uint32_t DpmTimerID : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

159

uint32_t DpmHubID : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

160

uint32_t DpmHubTask : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

162

uint32_t CclkSyncStatus : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

163

uint32_t ZstateStatus : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

164

uint32_t Cpu1VddOff : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

165

uint32_t DstateFun : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

166

uint32_t DstateDev : 4;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

167

uint32_t GfxOffStatus : 2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

168

uint32_t Cpu0Off : 2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

169

uint32_t Cpu1Off : 2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

170

uint32_t Cpu0VddOff : 2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

172

uint32_t P2JobHandler :32;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

174

uint32_t PostCode :32;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

176

uint32_t MsgPortBusy :15;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

177

uint32_t RsmuPmiP1Pending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

178

uint32_t RsmuPmiP2PendingCnt : 8;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

179

uint32_t DfCstateExitPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

180

uint32_t Pc6EntryPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

181

uint32_t Pc6ExitPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

182

uint32_t WarmResetPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

183

uint32_t Mp0ClkPending : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

184

uint32_t InWhisperMode : 1;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

185

uint32_t spare2 : 2;

sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

187

uint32_t IdleMask :32;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

120

uint32_t workload_policy_mask;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

121

uint32_t dcef_min_ds_clk;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

133

uint32_t power_source;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

139

uint32_t power_source;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

143

uint32_t current_fast_ppt_limit;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

144

uint32_t default_fast_ppt_limit;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

145

uint32_t max_fast_ppt_limit;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

181

int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

188

uint32_t *power_limit);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

192

uint32_t limit);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

200

int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

202

int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

209

uint32_t

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

214

uint32_t mode);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

217

uint32_t speed);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

220

uint32_t speed);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

223

uint32_t *speed);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

226

uint32_t *speed);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

229

uint32_t pstate);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

255

uint32_t *min, uint32_t *max);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

258

uint32_t min, uint32_t max, bool automatic);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

262

uint32_t min,

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

263

uint32_t max);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

274

uint32_t *value);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

278

uint32_t *value);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

75

uint32_t display_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

76

uint32_t phy_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

77

uint32_t pixel_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

78

uint32_t uclock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

79

uint32_t dcef_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

80

uint32_t soc_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

85

uint32_t value;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

89

uint32_t min; /* MHz */

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

90

uint32_t max; /* MHz */

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0.h

91

uint32_t count;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

137

uint32_t feature_count; //Total number of supported features

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

138

uint32_t setting_count; //Total number of supported settings

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

140

uint32_t max[SMU_11_0_7_MAX_ODSETTING]; //default maximum settings

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

141

uint32_t min[SMU_11_0_7_MAX_ODSETTING]; //default minimum settings

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

167

uint32_t count; //power_saving_clock_count = SMU_11_0_7_PPCLOCK_COUNT

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

168

uint32_t max[SMU_11_0_7_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

169

uint32_t min[SMU_11_0_7_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

177

uint32_t golden_pp_id; //PPGen use only: PP Table ID on the Golden Data Base

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

178

uint32_t golden_revision; //PPGen use only: PP Table Revision on the Golden Data Base

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h

180

uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

107

uint32_t feature_count; //Total number of supported features

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

108

uint32_t setting_count; //Total number of supported settings

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

110

uint32_t max[SMU_11_0_MAX_ODSETTING]; //default maximum settings

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

111

uint32_t min[SMU_11_0_MAX_ODSETTING]; //default minimum settings

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

132

uint32_t count; //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

133

uint32_t max[SMU_11_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

134

uint32_t min[SMU_11_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

141

uint32_t golden_pp_id;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

142

uint32_t golden_revision;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h

144

uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v12_0.h

48

uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v12_0.h

59

uint32_t min, uint32_t max, bool automatic);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

113

uint32_t workload_policy_mask;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

114

uint32_t dcef_min_ds_clk;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

116

uint32_t board_volt;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

128

uint32_t power_source;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

172

uint32_t *power_limit);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

176

uint32_t limit);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

184

int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

186

uint32_t

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

191

uint32_t mode);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

194

uint32_t speed);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

197

uint32_t speed);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

200

uint32_t pstate);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

217

uint32_t *min, uint32_t *max);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

220

uint32_t min, uint32_t max, bool automatic);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

234

uint32_t *value);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

272

uint32_t size);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

282

uint32_t *size,

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

283

uint32_t pptable_id);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

298

uint32_t *value);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

68

uint32_t display_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

69

uint32_t phy_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

70

uint32_t pixel_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

71

uint32_t uclock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

72

uint32_t dcef_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

73

uint32_t soc_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

78

uint32_t value;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

82

uint32_t min; /* MHz */

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

83

uint32_t max; /* MHz */

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

84

uint32_t count;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h

93

uint32_t num_of_link_levels;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h

146

uint32_t feature_count; //Total number of supported features

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h

147

uint32_t setting_count; //Total number of supported settings

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h

149

uint32_t max[SMU_13_0_0_MAX_ODSETTING]; //default maximum settings

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h

150

uint32_t min[SMU_13_0_0_MAX_ODSETTING]; //default minimum settings

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h

177

uint32_t golden_pp_id; //PPGen use only: PP Table ID on the Golden Data Base

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h

178

uint32_t golden_revision; //PPGen use only: PP Table Revision on the Golden Data Base

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h

180

uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h

189

uint32_t reserve[45];

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h

146

uint32_t feature_count; //Total number of supported features

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h

147

uint32_t setting_count; //Total number of supported settings

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h

149

uint32_t max[SMU_13_0_7_MAX_ODSETTING]; //default maximum settings

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h

150

uint32_t min[SMU_13_0_7_MAX_ODSETTING]; //default minimum settings

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h

177

uint32_t golden_pp_id; //PPGen use only: PP Table ID on the Golden Data Base

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h

178

uint32_t golden_revision; //PPGen use only: PP Table Revision on the Golden Data Base

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h

180

uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h

189

uint32_t reserve[45];

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h

109

uint32_t feature_count; //Total number of supported features

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h

110

uint32_t setting_count; //Total number of supported settings

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h

112

uint32_t max[SMU_13_0_MAX_ODSETTING]; //default maximum settings

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h

113

uint32_t min[SMU_13_0_MAX_ODSETTING]; //default minimum settings

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h

134

uint32_t count; //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h

135

uint32_t max[SMU_13_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h

136

uint32_t min[SMU_13_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h

143

uint32_t golden_pp_id;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h

144

uint32_t golden_revision;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h

146

uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

108

uint32_t workload_policy_mask;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

109

uint32_t dcef_min_ds_clk;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

121

uint32_t power_source;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

164

uint32_t *power_limit);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

168

uint32_t limit);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

187

uint32_t *min, uint32_t *max);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

190

uint32_t min, uint32_t max, bool automatic);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

194

uint32_t min,

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

195

uint32_t max);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

236

uint32_t *size,

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

237

uint32_t pptable_id);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

241

long input[], uint32_t size);

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

63

uint32_t display_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

64

uint32_t phy_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

65

uint32_t pixel_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

66

uint32_t uclock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

67

uint32_t dcef_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

68

uint32_t soc_clock;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

73

uint32_t value;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

77

uint32_t min; /* MHz */

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

78

uint32_t max; /* MHz */

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

79

uint32_t count;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0.h

88

uint32_t num_of_link_levels;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h

153

uint32_t golden_pp_id; // PPGen use only: PP Table ID on the Golden Data Base

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h

154

uint32_t golden_revision; // PPGen use only: PP Table Revision on the Golden Data Base

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h

156

uint32_t platform_caps; // POWERPLAYTABLE::ulPlatformCaps

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h

195

uint32_t custom_platform_caps;

sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h

198

uint32_t reserve[8];

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1003

enum smu_clk_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1007

uint32_t soft_min_level, soft_max_level;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1097

void *data, uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1111

*(uint32_t *)data = pptable->FanMaximumRpm;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1117

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1123

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1129

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1135

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1141

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1147

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1151

ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1153

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1157

ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1158

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1162

ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1175

uint32_t mode)

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1190

uint32_t *speed)

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1193

uint32_t crystal_clock_freq = 2500;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1194

uint32_t tach_status;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1223

*speed = (uint32_t)tmp64;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1235

uint32_t speed)

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1238

uint32_t duty100, duty;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1241

speed = min_t(uint32_t, speed, 255);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1250

duty = (uint32_t)tmp64;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1260

uint32_t speed)

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1267

uint32_t crystal_clock_freq = 2500;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1268

uint32_t tach_period;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1283

uint32_t *speed)

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1286

uint32_t duty100, duty;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1308

*speed = min_t(uint32_t, tmp64, 255);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1326

uint32_t *current_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1327

uint32_t *default_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1328

uint32_t *max_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1329

uint32_t *min_power_limit)

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1332

uint32_t power_limit;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1376

uint32_t i, size = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1774

uint32_t top32 = 0, bottom32 = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1813

uint32_t feature_mask;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1829

uint32_t throttler_status;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1866

uint32_t esm_ctrl;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

350

uint32_t *feature_mask, uint32_t num)

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

356

memset(feature_mask, 0xFF, sizeof(uint32_t) * num);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

458

uint32_t val;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

618

uint32_t i;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

620

clocks->num_levels = min_t(uint32_t,

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

622

(uint32_t)PP_MAX_CLOCK_LEVELS);

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

639

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

737

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

808

uint32_t gen_speed, lane_width;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

809

uint32_t i, cur_value = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

949

uint32_t feature_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

950

uint32_t level)

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

954

uint32_t freq;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.h

35

uint32_t value;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.h

36

uint32_t param1;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.h

40

uint32_t soft_min_level;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.h

41

uint32_t soft_max_level;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.h

42

uint32_t hard_min_level;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.h

43

uint32_t hard_max_level;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.h

47

uint32_t count;

sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.h

56

uint32_t lclk[MAX_PCIE_CONF];

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

131

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

193

uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

204

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

205

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

211

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

212

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

218

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

224

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

230

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

236

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

242

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

248

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

261

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

295

uint32_t cur_value = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

440

long input[], uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

443

uint32_t vid;

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

537

uint32_t *min,

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

538

uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

541

uint32_t low, high;

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

57

uint32_t sclk;

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

58

uint32_t vddc;

sys/dev/pci/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

61

static uint32_t cyan_skillfish_sclk_default;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1185

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1249

uint32_t *min, uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1264

uint32_t cur_value = 0, value = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1265

uint32_t freq_values[3] = {0};

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1266

uint32_t i, levels, mark_index = 0, count = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1268

uint32_t gen_speed, lane_width;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1275

uint32_t min_value, max_value;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1473

uint32_t cur_value = 0, value = 0, count = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1474

uint32_t freq_values[3] = {0};

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1475

uint32_t mark_index = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1477

uint32_t gen_speed, lane_width;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1484

uint32_t min_value, max_value;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1660

enum smu_clk_type clk_type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1664

uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1722

uint32_t sclk_freq;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1805

uint32_t level_count = 0, freq = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1817

level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1839

uint32_t max_freq = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1887

uint32_t *speed)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1921

uint32_t i, size = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2230

void *data, uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2241

*(uint32_t *)data = pptable->FanMaximumRpm;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2247

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2253

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2259

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2265

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2271

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2277

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2281

ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2282

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2286

ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2287

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2291

ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2303

static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2305

uint32_t num_discrete_levels = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2369

uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2370

uint32_t max_memory_clock = max_sustainable_clocks->uclock;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2387

uint32_t *current_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2388

uint32_t *default_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2389

uint32_t *max_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2390

uint32_t *min_power_limit)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2396

uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2446

uint32_t smu_pcie_arg;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2491

uint32_t value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2506

uint32_t freq)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2508

uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2509

uint32_t value = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2625

static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

266

uint32_t mp0_fw_intf;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

279

uint32_t *feature_mask, uint32_t num)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2828

uint32_t uclk_count, uclk_min, uclk_max;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

286

memset(feature_mask, 0, sizeof(uint32_t) * num);

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2879

uint32_t i;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

2908

uint32_t param;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

3428

uint32_t param = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

372

uint32_t val;

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

557

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

643

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

732

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

818

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c

907

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1197

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1250

uint32_t clk_index = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1264

uint32_t *min, uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1285

uint32_t cur_value = 0, value = 0, count = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1286

uint32_t freq_values[3] = {0};

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1287

uint32_t mark_index = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1288

uint32_t gen_speed, lane_width;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1289

uint32_t min_value, max_value;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1441

enum smu_clk_type clk_type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1444

uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1535

uint32_t max_freq = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1589

uint32_t *speed)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1619

uint32_t i, size = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1931

void *data, uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1949

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1955

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1961

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1967

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1973

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1979

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1985

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1986

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1992

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1993

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1997

ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2004

METRICS_SS_APU_SHARE, (uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2014

METRICS_SS_DGPU_SHARE, (uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2032

uint32_t upper32 = 0, lower32 = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2049

static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2051

uint32_t num_discrete_levels = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2121

uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2122

uint32_t max_memory_clock = max_sustainable_clocks->uclock;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2147

uint32_t smu_pcie_arg;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2194

uint32_t *min, uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2259

uint32_t value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2277

long input[], uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2511

uint32_t val;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2512

uint32_t smu_version;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

280

uint32_t *feature_mask, uint32_t num)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

287

memset(feature_mask, 0, sizeof(uint32_t) * num);

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2987

uint32_t reg;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

3062

uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

3064

uint32_t *p = buf;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

369

uint32_t val;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

481

uint32_t *board_reserved;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

483

uint32_t i;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

595

static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu,

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

602

uint32_t throttler_status = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

627

uint32_t *current_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

628

uint32_t *default_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

629

uint32_t *max_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

630

uint32_t *min_power_limit)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

635

uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

677

uint32_t *apu_percent,

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

678

uint32_t *dgpu_percent)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

686

uint32_t apu_boost = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

687

uint32_t dgpu_boost = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

688

uint32_t cur_power_limit;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

732

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

745

uint32_t apu_percent = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

746

uint32_t dgpu_percent = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1038

int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1041

uint32_t vdd = 0, val_vid = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1049

vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1065

uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1136

uint32_t

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1162

smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1177

smu_v11_0_set_fan_speed_pwm(struct smu_context *smu, uint32_t speed)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1180

uint32_t duty100, duty;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1183

speed = min_t(uint32_t, speed, 255);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1192

duty = (uint32_t)tmp64;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1202

uint32_t speed)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1209

uint32_t crystal_clock_freq = 2500;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1210

uint32_t tach_period;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1232

uint32_t *speed)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1235

uint32_t duty100, duty;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1258

*speed = min_t(uint32_t, tmp64, 255);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1264

uint32_t *speed)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1267

uint32_t crystal_clock_freq = 2500;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1268

uint32_t tach_status;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1287

*speed = (uint32_t)tmp64;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1298

uint32_t mode)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1327

uint32_t pstate)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1341

uint32_t low, high;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1342

uint32_t val = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1410

uint32_t client_id = entry->client_id;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1411

uint32_t src_id = entry->src_id;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1416

uint32_t ctxid = entry->src_data[0];

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1417

uint32_t data;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

143

const uint32_t *src;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

145

uint32_t addr_start = MP1_SRAM;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

146

uint32_t i;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

147

uint32_t smc_fw_size;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

148

uint32_t mp1_fw_flags;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

151

src = (const uint32_t *)(adev->pm.fw->data +

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1604

uint32_t data;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1716

uint32_t *min, uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1719

uint32_t param = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1720

uint32_t clock_limit;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1776

uint32_t min,

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1777

uint32_t max,

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1781

uint32_t param;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1794

param = (uint32_t)((clk_id << 16) | 0xffff);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1796

param = (uint32_t)((clk_id << 16) | (max & 0xffff));

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1805

param = (uint32_t)((clk_id << 16) | 0);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1807

param = (uint32_t)((clk_id << 16) | (min & 0xffff));

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1820

uint32_t min,

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1821

uint32_t max)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1824

uint32_t param;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

183

uint32_t mp1_fw_flags;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1839

param = (uint32_t)((clk_id << 16) | (max & 0xffff));

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1847

param = (uint32_t)((clk_id << 16) | (min & 0xffff));

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1871

uint32_t sclk_min = 0, sclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1872

uint32_t mclk_min = 0, mclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1873

uint32_t socclk_min = 0, socclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1971

(uint32_t)power_src);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

198

uint32_t if_version = 0xff, smu_version = 0xff;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1984

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1987

uint32_t param;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

2001

param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

2021

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

2034

uint32_t clk;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

2078

uint32_t width_level;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

2098

uint32_t speed_level;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

271

static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

274

uint32_t ppt_offset_bytes;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

287

uint32_t *size, uint32_t pptable_id)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

292

uint32_t pptable_count = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

318

uint32_t size = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

503

uint32_t *clk_freq)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

516

(uint32_t *)&input, sizeof(input));

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

633

uint32_t address_low, address_high;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

639

address_high = (uint32_t)upper_32_bits(address);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

640

address_low = (uint32_t)lower_32_bits(address);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

656

address_high = (uint32_t)upper_32_bits(address);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

657

address_low = (uint32_t)lower_32_bits(address);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

668

(uint32_t)memory_pool->size, NULL);

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

675

int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

727

int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

752

uint32_t feature_mask[2];

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

794

smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

85

uint32_t data, loop = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

909

uint32_t *power_limit)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

941

uint32_t limit)

sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

945

uint32_t limit_param;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1035

uint32_t i, size = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1085

uint32_t min,

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1086

uint32_t max,

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1167

enum smu_clk_type clk_type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1169

uint32_t soft_min_level = 0, soft_max_level = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1170

uint32_t min_freq = 0, max_freq = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1276

uint32_t min_freq, max_freq, force_freq;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1304

uint32_t min_freq, max_freq;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1309

uint32_t feature;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1341

uint32_t socclk_freq = 0, fclk_freq = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1342

uint32_t vclk_freq = 0, dclk_freq = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1383

uint32_t soc_mask, mclk_mask, fclk_mask;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1384

uint32_t vclk_mask = 0, dclk_mask = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1499

void *data, uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1510

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1516

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1522

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1528

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1534

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1540

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1546

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1547

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1553

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1554

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1560

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1566

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1572

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1583

static int vangogh_get_apu_thermal_limit(struct smu_context *smu, uint32_t *limit)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1590

static int vangogh_set_apu_thermal_limit(struct smu_context *smu, uint32_t limit)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1990

uint32_t smu_program;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1991

uint32_t fw_version;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2020

long input[], uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2220

uint32_t tmp;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2224

uint32_t req_active_wgps = adev->gfx.cu_info.number/2;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2225

uint32_t total_cu = adev->gfx.config.max_cu_per_sh *

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2317

uint32_t *current_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2318

uint32_t *default_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2319

uint32_t *max_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2320

uint32_t *min_power_limit)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2324

uint32_t ppt_limit;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2359

uint32_t *ppt_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2390

uint32_t ppt_limit)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2478

static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t *residency)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

274

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

343

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

416

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

460

uint32_t eax, ebx, ecx, edx;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

528

uint32_t dpm_level, uint32_t *freq)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

577

uint32_t cur_value = 0, value = 0, count = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

678

uint32_t cur_value = 0, value = 0, count = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

680

uint32_t min, max;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

808

uint32_t *vclk_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

809

uint32_t *dclk_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

810

uint32_t *mclk_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

811

uint32_t *fclk_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

812

uint32_t *soc_mask)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

894

uint32_t *min,

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

895

uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

898

uint32_t soc_mask;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

899

uint32_t vclk_mask;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

900

uint32_t dclk_mask;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

901

uint32_t mclk_mask;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

902

uint32_t fclk_mask;

sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

903

uint32_t clock_limit;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1125

uint32_t i, size = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1150

uint32_t *apu_percent, uint32_t *dgpu_percent)

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1152

uint32_t apu_boost = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1153

uint32_t dgpu_boost = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1184

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1190

uint32_t apu_percent = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1191

uint32_t dgpu_percent = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1269

void *data, uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1280

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1286

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1292

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1298

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1304

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1305

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1311

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1312

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1318

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1324

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1330

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1336

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1342

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1434

static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state)

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

203

uint32_t dpm_level, uint32_t *freq)

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

252

uint32_t *sclk_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

253

uint32_t *mclk_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

254

uint32_t *soc_mask)

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

282

uint32_t *min,

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

283

uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

286

uint32_t mclk_mask, soc_mask;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

287

uint32_t clock_limit;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

385

long input[], uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

472

uint32_t min = 0, max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

498

uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

691

uint32_t min_freq, max_freq, force_freq;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

718

uint32_t min_freq, max_freq;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

723

uint32_t feature;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

793

enum smu_clk_type clk_type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

797

uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

888

uint32_t sclk_freq = 0, uclk_freq = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu12/renoir_ppt.c

914

uint32_t sclk = 0, socclk = 0, fclk = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c

145

uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)

sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c

147

uint32_t reg;

sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c

148

uint32_t gfxOff_Status = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c

214

uint32_t min, uint32_t max, bool automatic)

sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c

291

uint32_t *clk_freq)

sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c

304

(uint32_t *)&input, sizeof(input));

sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c

61

uint32_t mp1_fw_flags;

sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c

76

uint32_t if_version = 0xff, smu_version = 0xff;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1040

enum smu_clk_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1044

uint32_t soft_min_level, soft_max_level;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1123

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1151

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1184

void *data, uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1199

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1205

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1212

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1216

ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1218

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1222

ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1223

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1227

ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1240

uint32_t *current_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1241

uint32_t *default_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1242

uint32_t *max_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1243

uint32_t *min_power_limit)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1246

uint32_t power_limit = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1300

uint32_t limit)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1361

uint32_t min,

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1362

uint32_t max,

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1369

uint32_t min_clk;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1370

uint32_t max_clk;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1432

long input[], uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1437

uint32_t min_clk;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1438

uint32_t max_clk;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1669

uint32_t upper32 = 0, lower32 = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1703

uint32_t feature_mask;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1717

uint32_t throttler_status;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1754

uint32_t esm_ctrl;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

2009

uint32_t val;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

2010

uint32_t smu_version;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

2046

uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

2068

uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

334

uint32_t *feature_mask, uint32_t num)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

340

memset(feature_mask, 0xFF, sizeof(uint32_t) * num);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

347

uint32_t *min, uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

351

uint32_t min_clk, max_clk;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

645

uint32_t i;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

647

clocks->num_levels = min_t(uint32_t,

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

649

(uint32_t)PP_MAX_CLOCK_LEVELS);

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

667

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

763

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

835

uint32_t i;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

837

uint32_t freq_values[3] = {0};

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

838

uint32_t min_clk, max_clk, cur_value = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

986

uint32_t feature_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

987

uint32_t level)

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

991

uint32_t freq;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.h

35

uint32_t value;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.h

36

uint32_t param1;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.h

40

uint32_t soft_min_level;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.h

41

uint32_t soft_max_level;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.h

42

uint32_t hard_min_level;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.h

43

uint32_t hard_max_level;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.h

47

uint32_t count;

sys/dev/pci/drm/amd/pm/swsmu/smu13/aldebaran_ppt.h

56

uint32_t lclk[ALDEBARAN_MAX_PCIE_CONF];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1040

int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1043

uint32_t vdd = 0, val_vid = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1051

vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1059

uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1084

smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1099

uint32_t speed)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1102

uint32_t duty100, duty;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1105

speed = min_t(uint32_t, speed, 255);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1117

duty = (uint32_t)tmp64;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1128

uint32_t mode)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1155

uint32_t speed)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1158

uint32_t crystal_clock_freq = 2500;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1159

uint32_t tach_period;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1179

uint32_t pstate)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1195

uint32_t low, high;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1196

uint32_t val = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1270

uint32_t client_id = entry->client_id;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1271

uint32_t src_id = entry->src_id;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1276

uint32_t ctxid = entry->src_data[0];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1277

uint32_t data;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1278

uint32_t high;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

148

const uint32_t *src;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1485

uint32_t *min, uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1488

uint32_t param = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1489

uint32_t clock_limit;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

150

uint32_t addr_start = MP1_SRAM;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

151

uint32_t i;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

152

uint32_t smc_fw_size;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

153

uint32_t mp1_fw_flags;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1541

uint32_t min,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1542

uint32_t max,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1546

uint32_t param;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

156

src = (const uint32_t *)(adev->pm.fw->data +

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1560

param = (uint32_t)((clk_id << 16) | 0xffff);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1562

param = (uint32_t)((clk_id << 16) | (max & 0xffff));

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1571

param = (uint32_t)((clk_id << 16) | 0);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1573

param = (uint32_t)((clk_id << 16) | (min & 0xffff));

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1604

uint32_t sclk_min = 0, sclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1605

uint32_t mclk_min = 0, mclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1606

uint32_t socclk_min = 0, socclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1607

uint32_t vclk_min = 0, vclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1608

uint32_t dclk_min = 0, dclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1609

uint32_t fclk_min = 0, fclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1782

(uint32_t)power_src);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1794

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1828

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1831

uint32_t param;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1845

param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1861

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1878

uint32_t param;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1879

uint32_t value;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1893

param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

190

uint32_t size = 0, pptable_id = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1916

uint32_t clk;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1970

uint32_t width_level;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1990

uint32_t speed_level;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

2274

long input[], uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

2390

uint32_t smu_pcie_arg;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

240

uint32_t mp1_fw_flags;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

264

uint32_t if_version = 0xff, smu_version = 0xff;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

303

static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

306

uint32_t ppt_offset_bytes;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

319

uint32_t *size, uint32_t pptable_id)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

324

uint32_t pptable_count = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

345

static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

369

uint32_t *size,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

370

uint32_t pptable_id)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

409

uint32_t size = 0, pptable_id = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

680

(uint32_t)frev, (uint32_t)crev);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

694

uint32_t address_low, address_high;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

700

address_high = (uint32_t)upper_32_bits(address);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

701

address_low = (uint32_t)lower_32_bits(address);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

712

(uint32_t)memory_pool->size, NULL);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

763

uint32_t feature_mask[2];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

829

smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

944

uint32_t *power_limit)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

972

uint32_t limit)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1010

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1197

uint32_t gen_speed, lane_width;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1607

uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1613

uint32_t offset_of_voltageoffset;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1615

uint32_t feature_ctrlmask;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1674

(uint32_t)od_table->OverDriveTable.GfxclkFmin,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1675

(uint32_t)od_table->OverDriveTable.GfxclkFmax);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1735

(uint32_t)od_table->OverDriveTable.UclkFmin,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1736

(uint32_t)od_table->OverDriveTable.UclkFmax);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1987

uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1992

uint32_t soft_min_level, soft_max_level;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

1993

uint32_t min_freq, max_freq;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2112

uint32_t mp1_ver = amdgpu_ip_version(smu->adev, MP1_HWIP, 0);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2373

uint32_t upper32 = 0, lower32 = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2388

uint32_t *speed)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2404

*speed = min(*speed * 255 / 100, (uint32_t)255);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2410

uint32_t *speed)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2440

uint32_t *current_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2441

uint32_t *default_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2442

uint32_t *max_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2443

uint32_t *min_power_limit)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2450

uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2451

uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2508

uint32_t i, size = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2893

uint32_t supported_version,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2894

uint32_t *param)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2909

uint32_t param;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

2983

uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

300

uint32_t *feature_mask, uint32_t num)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

3000

uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

307

memset(feature_mask, 0xff, sizeof(uint32_t) * num);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

3085

uint32_t limit)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

3089

uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

3140

uint32_t smu_pcie_arg;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

3141

uint32_t link_level;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

429

uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

727

static uint32_t smu_v13_0_get_throttler_status(SmuMetrics_t *metrics)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

729

uint32_t throttler_status = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

742

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

874

uint32_t *min,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

875

uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

926

uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

940

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

946

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

952

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

958

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

964

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

970

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

976

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

982

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

983

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

989

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

990

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

996

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

274

uint32_t table_version;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

370

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

589

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

302

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

390

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

426

uint32_t dpm_level,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

427

uint32_t *freq)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

470

uint32_t *count)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

501

uint32_t cur_value = 0, value = 0, count = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

502

uint32_t min, max;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

573

void *data, uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

584

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

590

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

596

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

602

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

608

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

614

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

620

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

621

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

627

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

628

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

634

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

640

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

646

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

652

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

752

uint32_t *min,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

753

uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

756

uint32_t clock_limit;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

757

uint32_t max_dpm_level, min_dpm_level;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

839

uint32_t min,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

840

uint32_t max)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

843

uint32_t min_clk = min;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

844

uint32_t max_clk = max;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

888

uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

890

uint32_t soft_min_level = 0, soft_max_level = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

891

uint32_t min_freq = 0, max_freq = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

923

uint32_t *min_clk,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

924

uint32_t *max_clk)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

927

uint32_t clk_limit = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

968

uint32_t sclk_min = 0, sclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

969

uint32_t fclk_min = 0, fclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

970

uint32_t socclk_min = 0, socclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

971

uint32_t vclk_min = 0, vclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

972

uint32_t dclk_min = 0, dclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

1005

uint32_t sclk_min = 0, sclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

1006

uint32_t vclk_min = 0, vclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

1007

uint32_t dclk_min = 0, dclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

260

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

323

void *data, uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

334

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

340

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

346

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

352

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

358

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

364

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

365

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

371

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

372

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

378

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

384

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

390

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

396

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

514

long input[], uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

596

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

627

uint32_t *count)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

656

uint32_t dpm_level,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

657

uint32_t *freq)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

729

uint32_t *min,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

730

uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

733

uint32_t clock_limit;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

734

uint32_t max_dpm_level, min_dpm_level;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

817

uint32_t min,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

818

uint32_t max,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

822

uint32_t min_clk = min;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

823

uint32_t max_clk = max;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

865

uint32_t cur_value = 0, value = 0, count = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

866

uint32_t min = 0, max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

936

enum smu_clk_type clk_type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

938

uint32_t soft_min_level = 0, soft_max_level = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

939

uint32_t min_freq = 0, max_freq = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

972

uint32_t *min_clk,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

973

uint32_t *max_clk)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

976

uint32_t clk_limit = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1041

uint32_t *levels)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1068

uint32_t gfxclkmin, gfxclkmax, levels;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

116

enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1165

uint32_t mp1_fw_flags;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1249

static uint32_t smu_v13_0_6_get_throttler_status(struct smu_context *smu)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1253

uint32_t throttler_status = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1263

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1344

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1379

uint32_t curr_clk, const char *clk_name)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1383

uint32_t clk1, clk2;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1437

uint32_t min_clk, max_clk;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1582

uint32_t feature_mask, uint32_t level)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1585

uint32_t freq;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1641

enum smu_clk_type type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1645

uint32_t soft_min_level, soft_max_level;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1699

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1726

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1752

uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1767

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1773

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1779

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1784

smu, SMU_UCLK, (uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1786

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1791

smu, SMU_GFXCLK, (uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1792

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1796

ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1801

*(uint32_t *)data = dpm_context->board_volt;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1812

ret = smu_v13_0_12_get_npm_data(smu, sensor, (uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1827

uint32_t *current_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1828

uint32_t *default_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1829

uint32_t *max_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1830

uint32_t *min_power_limit)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1835

uint32_t power_limit = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1861

uint32_t limit)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1873

uint32_t client_id = entry->client_id;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1874

uint32_t ctxid = entry->src_data[0];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1875

uint32_t src_id = entry->src_id;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1876

uint32_t data;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1926

uint32_t val = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2025

uint32_t min,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2026

uint32_t max)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2098

uint32_t min, uint32_t max,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2105

uint32_t min_clk;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2106

uint32_t max_clk;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2189

long input[], uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2194

uint32_t min_clk;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2195

uint32_t max_clk;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2376

uint32_t table_size;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

253

uint32_t feature_num;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

255

uint32_t *freq_table;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2564

uint32_t throttler_status;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2610

uint32_t speed_level;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

2611

uint32_t esm_ctrl;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

304

uint32_t fw_ver = smu->smc_fw_version;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3148

uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3200

static int smu_v13_0_6_reset_sdma(struct smu_context *smu, uint32_t inst_mask)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3222

static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3256

static int smu_v13_0_6_get_valid_mca_count(struct smu_context *smu, enum amdgpu_mca_error_type type, uint32_t *count)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3258

uint32_t msg;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3285

int idx, int offset, uint32_t *val)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3287

uint32_t msg, param;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3306

int idx, int offset, uint32_t *val, int count)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

334

uint32_t fw_ver = smu->smc_fw_version;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3356

uint32_t data[2] = {0, 0};

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3417

enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3420

uint32_t ext_error_code;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3421

uint32_t odecc_err_cnt;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3447

uint32_t *count)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3465

uint32_t errcode)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3481

enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3505

enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3532

uint32_t instlo;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3552

uint32_t errcode, instlo;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3643

static int mca_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3674

struct mca_bank_entry *entry, uint32_t *count)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3700

enum amdgpu_mca_error_type type, uint32_t *count)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3723

uint32_t msg;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3771

uint32_t msg, param;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

3786

return smu_cmn_send_smc_msg_with_param(smu, msg, param, (uint32_t *)val);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

382

uint32_t fw_ver = smu->smc_fw_version;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

383

uint32_t pgm = (fw_ver >> 24) & 0xFF;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

488

uint32_t p2s_table_id = P2S_TABLE_ID_A;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

738

uint32_t *feature_mask,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

739

uint32_t num)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

745

memset(feature_mask, 0xFF, sizeof(uint32_t) * num);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

754

uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

784

uint32_t table_version = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].version;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

785

uint32_t table_size = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].size;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

787

uint32_t pmfw_version;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

836

uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

864

uint32_t table_version;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

956

uint32_t *min, uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

963

uint32_t min_clk, max_clk, param;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h

40

uint32_t MaxSocketPowerLimit;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h

41

uint32_t MaxGfxclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h

42

uint32_t MinGfxclkFrequency;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h

43

uint32_t FclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h

44

uint32_t UclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h

45

uint32_t SocclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h

46

uint32_t VclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h

47

uint32_t DclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h

48

uint32_t LclkFrequencyTable[4];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h

49

uint32_t MaxLclkDpmRange;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h

50

uint32_t MinLclkDpmRange;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h

52

uint32_t MaxNodePowerLimit;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h

89

MetricsMember_t member, uint32_t *value);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h

98

uint32_t *value);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1186

uint32_t gen_speed, lane_width;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1595

uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1601

uint32_t offset_of_voltageoffset;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1603

uint32_t feature_ctrlmask;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1662

(uint32_t)od_table->OverDriveTable.GfxclkFmin,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1663

(uint32_t)od_table->OverDriveTable.GfxclkFmax);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1723

(uint32_t)od_table->OverDriveTable.UclkFmin,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1724

(uint32_t)od_table->OverDriveTable.UclkFmax);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1976

uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1981

uint32_t soft_min_level, soft_max_level;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

1982

uint32_t min_freq, max_freq;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2349

uint32_t *speed)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2365

*speed = min(*speed * 255 / 100, (uint32_t)255);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2371

uint32_t *speed)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2401

uint32_t *current_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2402

uint32_t *default_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2403

uint32_t *max_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2404

uint32_t *min_power_limit)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2411

uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2412

uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2454

uint32_t i, j, size = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2677

uint32_t limit)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2681

uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

269

uint32_t *feature_mask, uint32_t num)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

2733

uint32_t smu_pcie_arg;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

276

memset(feature_mask, 0, sizeof(uint32_t) * num);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

396

uint32_t mp1_fw_flags;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

442

uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

719

static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

721

uint32_t throttler_status = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

734

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

863

uint32_t *min,

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

864

uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

915

uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

929

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

935

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

941

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

947

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

953

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

959

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

965

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

971

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

972

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

978

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

979

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

985

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

999

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1005

static uint32_t yellow_carp_get_umd_pstate_clk_default(struct smu_context *smu,

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1008

uint32_t clk_limit = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1045

uint32_t cur_value = 0, value = 0, count = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1046

uint32_t min, max;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1047

uint32_t clk_limit = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1118

enum smu_clk_type clk_type, uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1120

uint32_t soft_min_level = 0, soft_max_level = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1121

uint32_t min_freq = 0, max_freq = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1156

uint32_t *min_clk,

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1157

uint32_t *max_clk)

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1160

uint32_t clk_limit = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1200

uint32_t sclk_min = 0, sclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1201

uint32_t fclk_min = 0, fclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1202

uint32_t socclk_min = 0, socclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1203

uint32_t vclk_min = 0, vclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

1204

uint32_t dclk_min = 0, dclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

299

uint32_t *apu_percent, uint32_t *dgpu_percent)

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

301

uint32_t apu_boost = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

302

uint32_t dgpu_boost = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

335

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

341

uint32_t apu_percent = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

342

uint32_t dgpu_percent = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

414

void *data, uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

425

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

431

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

437

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

443

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

449

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

455

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

456

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

462

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

463

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

469

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

475

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

481

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

487

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

624

static uint32_t yellow_carp_get_gfxoff_status(struct smu_context *smu)

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

626

uint32_t reg;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

627

uint32_t gfxoff_status = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

645

long input[], uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

727

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

761

uint32_t *count)

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

790

uint32_t dpm_level,

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

791

uint32_t *freq)

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

863

uint32_t *min,

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

864

uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

867

uint32_t clock_limit;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

868

uint32_t max_dpm_level, min_dpm_level;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

951

uint32_t min,

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

952

uint32_t max,

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

956

uint32_t min_clk = min;

sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

957

uint32_t max_clk = max;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1095

uint32_t *min, uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1098

uint32_t param = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1099

uint32_t clock_limit;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1164

uint32_t min,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1165

uint32_t max,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1169

uint32_t param;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1183

param = (uint32_t)((clk_id << 16) | 0xffff);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1185

param = (uint32_t)((clk_id << 16) | (max & 0xffff));

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1194

param = (uint32_t)((clk_id << 16) | 0);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1196

param = (uint32_t)((clk_id << 16) | (min & 0xffff));

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1209

uint32_t min,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1210

uint32_t max)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1213

uint32_t param;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

122

const uint32_t *src;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1228

param = (uint32_t)((clk_id << 16) | (max & 0xffff));

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1236

param = (uint32_t)((clk_id << 16) | (min & 0xffff));

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

124

uint32_t addr_start = MP1_SRAM;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

125

uint32_t i;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

126

uint32_t smc_fw_size;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1266

uint32_t sclk_min = 0, sclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1267

uint32_t mclk_min = 0, mclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1268

uint32_t socclk_min = 0, socclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1269

uint32_t vclk_min = 0, vclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

127

uint32_t mp1_fw_flags;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1270

uint32_t dclk_min = 0, dclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1271

uint32_t fclk_min = 0, fclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

130

src = (const uint32_t *)(adev->pm.fw->data +

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1431

(uint32_t)power_src);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1444

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1447

uint32_t param;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1461

param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1477

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1491

uint32_t param;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1492

uint32_t value;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1506

param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1529

uint32_t clk;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

167

uint32_t size = 0, pptable_id = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1871

long input[], uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

216

uint32_t mp1_fw_flags;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

235

uint32_t if_version = 0xff, smu_version = 0xff;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

293

static int smu_v14_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

296

uint32_t ppt_offset_bytes;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

309

uint32_t *size, uint32_t pptable_id)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

314

uint32_t pptable_count = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

335

static int smu_v14_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

359

uint32_t *size,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

360

uint32_t pptable_id)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

399

uint32_t size = 0, pptable_id = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

665

(uint32_t)frev, (uint32_t)crev);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

679

uint32_t address_low, address_high;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

685

address_high = (uint32_t)upper_32_bits(address);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

686

address_low = (uint32_t)lower_32_bits(address);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

697

(uint32_t)memory_pool->size, NULL);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

748

uint32_t feature_mask[2];

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

815

uint32_t *power_limit)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

843

uint32_t limit)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

872

uint32_t low, high;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

873

uint32_t val = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

955

uint32_t client_id = entry->client_id;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

956

uint32_t src_id = entry->src_id;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

962

uint32_t ctxid = entry->src_data[0];

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

963

uint32_t data;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c

964

uint32_t high;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1010

uint32_t *min,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1011

uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1023

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1062

uint32_t *count)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1093

uint32_t *count)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1122

uint32_t *count)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1136

uint32_t cur_value = 0, value = 0, count = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1137

uint32_t min, max;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1266

uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1268

uint32_t soft_min_level = 0, soft_max_level = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1269

uint32_t min_freq = 0, max_freq = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1303

uint32_t *min_clk,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1304

uint32_t *max_clk)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1306

uint32_t clk_limit = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1363

uint32_t sclk_min = 0, sclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1364

uint32_t fclk_min = 0, fclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1365

uint32_t socclk_min = 0, socclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1366

uint32_t vclk_min = 0, vclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1367

uint32_t dclk_min = 0, dclk_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1368

uint32_t vclk1_min = 0, vclk1_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

1369

uint32_t dclk1_min = 0, dclk1_max = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

259

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

379

void *data, uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

390

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

396

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

402

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

408

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

414

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

420

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

426

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

427

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

433

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

434

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

440

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

446

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

452

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

458

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

632

uint32_t dpm_level,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

633

uint32_t *freq)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

686

uint32_t dpm_level,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

687

uint32_t *freq)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

730

uint32_t dpm_level,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

731

uint32_t *freq)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

774

uint32_t *min,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

775

uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

778

uint32_t clock_limit;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

779

uint32_t max_dpm_level, min_dpm_level;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

896

uint32_t *min,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

897

uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

900

uint32_t clock_limit;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

901

uint32_t max_dpm_level, min_dpm_level;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1058

uint32_t gen_speed, lane_width;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1382

uint32_t mask)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1387

uint32_t soft_min_level, soft_max_level;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1388

uint32_t min_freq, max_freq;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1468

uint32_t smu_pcie_arg;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1469

uint32_t link_level;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1646

uint32_t upper32 = 0, lower32 = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1661

uint32_t *speed)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1677

*speed = min(*speed * 255 / 100, (uint32_t)255);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1683

uint32_t *speed)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1694

uint32_t *current_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1695

uint32_t *default_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1696

uint32_t *max_power_limit,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1697

uint32_t *min_power_limit)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1705

uint32_t msg_limit = pptable->SkuTable.MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1706

uint32_t power_limit;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

1763

uint32_t i, size = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

2488

uint32_t size)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

2494

uint32_t offset_of_voltageoffset;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

2496

uint32_t feature_ctrlmask;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

2581

(uint32_t)od_table->OverDriveTable.UclkFmin,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

2582

(uint32_t)od_table->OverDriveTable.UclkFmax);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

269

uint32_t *feature_mask, uint32_t num)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

277

memset(feature_mask, 0xff, sizeof(uint32_t) * num);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

2812

uint32_t limit)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

2815

uint32_t msg_limit = pptable->SkuTable.MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

373

uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

651

static uint32_t smu_v14_0_2_get_throttler_status(SmuMetrics_t *metrics)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

653

uint32_t throttler_status = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

666

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

792

uint32_t *min,

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

793

uint32_t *max)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

844

uint32_t *size)

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

858

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

864

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

870

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

876

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

882

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

888

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

894

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

900

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

901

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

907

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

908

*(uint32_t *)data *= 100;

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

914

(uint32_t *)data);

sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

927

uint32_t *value)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

1032

uint32_t table_size =

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

248

static inline uint32_t __smu_cmn_get_msg_flags(struct smu_context *smu,

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

258

uint32_t flags, resp;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

323

uint32_t param)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

423

uint32_t param,

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

424

uint32_t *read_arg)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

494

uint32_t *read_arg)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

503

uint32_t msg)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

509

uint32_t msg, uint32_t param)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

516

uint32_t index)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

66

uint32_t *arg)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

690

uint32_t *feature_mask_high;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

691

uint32_t *feature_mask_low;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

697

feature_mask_low = &((uint32_t *)feature_mask)[0];

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

698

feature_mask_high = &((uint32_t *)feature_mask)[1];

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

813

uint32_t count = 0;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

920

uint32_t *if_version,

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

921

uint32_t *smu_version)

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c

970

uint32_t table_size;

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h

106

uint32_t param);

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h

109

uint32_t param,

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h

110

uint32_t *read_arg);

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h

114

uint32_t *read_arg);

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h

117

uint32_t msg);

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h

120

uint32_t msg, uint32_t param);

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h

126

uint32_t index);

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h

162

uint32_t *if_version,

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h

163

uint32_t *smu_version);

sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.h

99

static inline int pcie_gen_to_speed(uint32_t gen)

sys/dev/pci/drm/apple/apldcp.c

133

uint32_t *phandles;

sys/dev/pci/drm/apple/apldcp.c

134

uint32_t iommu_addrs[5];

sys/dev/pci/drm/apple/apldcp.c

148

for (idx = 0; idx < len / sizeof(uint32_t); idx++) {

sys/dev/pci/drm/apple/apldrm.c

185

void **cookiep, int *curxp, int *curyp, uint32_t *attrp)

sys/dev/pci/drm/apple/apldrm.c

302

uint32_t defattr;

sys/dev/pci/drm/apple/apldrm.c

321

if (idx >= 0 && idx < len / sizeof(uint32_t)) {

sys/dev/pci/drm/apple/apldrm.c

322

uint32_t *phandles;

sys/dev/pci/drm/display/drm_dp_helper.c

2284

uint32_t crcs[3];

sys/dev/pci/drm/drm_atomic.c

607

uint32_t num_clips;

sys/dev/pci/drm/drm_atomic_helper.c

2978

uint32_t flags)

sys/dev/pci/drm/drm_atomic_helper.c

3395

uint32_t src_x, uint32_t src_y,

sys/dev/pci/drm/drm_atomic_helper.c

3396

uint32_t src_w, uint32_t src_h,

sys/dev/pci/drm/drm_atomic_helper.c

3914

uint32_t flags)

sys/dev/pci/drm/drm_atomic_helper.c

3969

uint32_t flags,

sys/dev/pci/drm/drm_atomic_helper.c

4012

uint32_t flags,

sys/dev/pci/drm/drm_atomic_helper.c

4013

uint32_t target,

sys/dev/pci/drm/drm_atomic_uapi.c

1409

uint32_t __user *objs_ptr = (uint32_t __user *)(unsigned long)(arg->objs_ptr);

sys/dev/pci/drm/drm_atomic_uapi.c

1410

uint32_t __user *count_props_ptr = (uint32_t __user *)(unsigned long)(arg->count_props_ptr);

sys/dev/pci/drm/drm_atomic_uapi.c

1411

uint32_t __user *props_ptr = (uint32_t __user *)(unsigned long)(arg->props_ptr);

sys/dev/pci/drm/drm_atomic_uapi.c

1478

uint32_t obj_id, count_props;

sys/dev/pci/drm/drm_atomic_uapi.c

1509

uint32_t prop_id;

sys/dev/pci/drm/drm_connector.c

3342

uint32_t __user *encoder_ptr;

sys/dev/pci/drm/drm_connector.c

3358

encoder_ptr = (uint32_t __user *)(unsigned long)(out_resp->encoders_ptr);

sys/dev/pci/drm/drm_connector.c

3461

(uint32_t __user *)(unsigned long)(out_resp->props_ptr),

sys/dev/pci/drm/drm_crtc.c

703

uint32_t __user *set_connectors_ptr;

sys/dev/pci/drm/drm_crtc.c

839

set_connectors_ptr = (uint32_t __user *)(unsigned long)crtc_req->set_connectors_ptr;

sys/dev/pci/drm/drm_crtc_internal.h

154

uint32_t obj_type, bool register_obj,

sys/dev/pci/drm/drm_crtc_internal.h

157

uint32_t obj_type);

sys/dev/pci/drm/drm_crtc_internal.h

162

uint32_t id, uint32_t type);

sys/dev/pci/drm/drm_crtc_internal.h

166

uint32_t __user *prop_ptr,

sys/dev/pci/drm/drm_crtc_internal.h

168

uint32_t *arg_count_props);

sys/dev/pci/drm/drm_crtc_internal.h

170

uint32_t prop_id);

sys/dev/pci/drm/drm_crtc_internal.h

212

int drm_framebuffer_check_src_coords(uint32_t src_x, uint32_t src_y,

sys/dev/pci/drm/drm_crtc_internal.h

213

uint32_t src_w, uint32_t src_h,

sys/dev/pci/drm/drm_damage_helper.c

136

uint32_t inc = 1;

sys/dev/pci/drm/drm_damage_helper.c

42

uint32_t num_clips, uint32_t src_inc)

sys/dev/pci/drm/drm_debugfs_crc.c

395

uint32_t frame, uint32_t *crcs)

sys/dev/pci/drm/drm_fb_helper.c

1495

static uint32_t drm_fb_helper_find_format(struct drm_fb_helper *fb_helper, const uint32_t *formats,

sys/dev/pci/drm/drm_fb_helper.c

1499

uint32_t format;

sys/dev/pci/drm/drm_fb_helper.c

1530

uint32_t surface_format = DRM_FORMAT_INVALID;

sys/dev/pci/drm/drm_fb_helper.c

1709

static void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch,

sys/dev/pci/drm/drm_fb_helper.c

1730

uint32_t fb_width, uint32_t fb_height)

sys/dev/pci/drm/drm_format_helper.c

1202

int drm_fb_blit(struct iosys_map *dst, const unsigned int *dst_pitch, uint32_t dst_format,

sys/dev/pci/drm/drm_format_helper.c

1206

uint32_t fb_format = fb->format->format;

sys/dev/pci/drm/drm_fourcc.c

118

uint32_t drm_driver_legacy_fb_format(struct drm_device *dev,

sys/dev/pci/drm/drm_fourcc.c

119

uint32_t bpp, uint32_t depth)

sys/dev/pci/drm/drm_fourcc.c

121

uint32_t fmt = drm_mode_legacy_fb_format(bpp, depth);

sys/dev/pci/drm/drm_fourcc.c

158

uint32_t drm_driver_color_mode_format(struct drm_device *dev, unsigned int color_mode)

sys/dev/pci/drm/drm_fourcc.c

40

uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth)

sys/dev/pci/drm/drm_fourcc.c

42

uint32_t fmt = DRM_FORMAT_INVALID;

sys/dev/pci/drm/drm_framebuffer.c

481

uint32_t *fb_id = data;

sys/dev/pci/drm/drm_framebuffer.c

76

int drm_framebuffer_check_src_coords(uint32_t src_x, uint32_t src_y,

sys/dev/pci/drm/drm_framebuffer.c

77

uint32_t src_w, uint32_t src_h,

sys/dev/pci/drm/drm_framebuffer.c

929

uint32_t id)

sys/dev/pci/drm/drm_gem_dma_helper.c

153

uint32_t handle;

sys/dev/pci/drm/drm_internal.h

89

struct dma_buf *dma_buf, uint32_t handle);

sys/dev/pci/drm/drm_internal.h

91

uint32_t handle);

sys/dev/pci/drm/drm_ioctl.c

1048

uint32_t drv_size;

sys/dev/pci/drm/drm_ioctl.c

1055

uint32_t drv_size;

sys/dev/pci/drm/drm_linux.c

1075

uint32_t start = xr.start;

sys/dev/pci/drm/drm_linux.c

1076

uint32_t end = xr.end;

sys/dev/pci/drm/drm_linux.c

1318

uint32_t

sys/dev/pci/drm/drm_linux.c

2110

dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count,

sys/dev/pci/drm/drm_linux.c

2111

uint32_t *idx)

sys/dev/pci/drm/drm_linux.c

2127

dma_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count,

sys/dev/pci/drm/drm_linux.c

2128

bool intr, long timeout, uint32_t *idx)

sys/dev/pci/drm/drm_linux.c

2989

uint32_t offset, capid;

sys/dev/pci/drm/drm_linux.c

3706

uint32_t gpios[4];

sys/dev/pci/drm/drm_linux.c

3795

const char *propname, uint32_t *out_values, size_t sz_min, size_t sz_max)

sys/dev/pci/drm/drm_linux.c

3848

uint32_t phandles[16] = {};

sys/dev/pci/drm/drm_linux.c

3853

if (len < (idx + 1) * sizeof(uint32_t))

sys/dev/pci/drm/drm_linux.c

3867

uint32_t phandles[16] = {};

sys/dev/pci/drm/drm_linux.c

3872

if (len < (idx + 1) * sizeof(uint32_t))

sys/dev/pci/drm/drm_mode_config.c

101

uint32_t __user *fb_id;

sys/dev/pci/drm/drm_mode_config.c

102

uint32_t __user *crtc_id;

sys/dev/pci/drm/drm_mode_config.c

103

uint32_t __user *connector_id;

sys/dev/pci/drm/drm_mode_config.c

104

uint32_t __user *encoder_id;

sys/dev/pci/drm/drm_mode_object.c

126

bool drm_mode_object_lease_required(uint32_t type)

sys/dev/pci/drm/drm_mode_object.c

140

uint32_t id, uint32_t type)

sys/dev/pci/drm/drm_mode_object.c

181

uint32_t id, uint32_t type)

sys/dev/pci/drm/drm_mode_object.c

409

uint32_t __user *prop_ptr,

sys/dev/pci/drm/drm_mode_object.c

41

uint32_t obj_type, bool register_obj,

sys/dev/pci/drm/drm_mode_object.c

411

uint32_t *arg_count_props)

sys/dev/pci/drm/drm_mode_object.c

480

(uint32_t __user *)(unsigned long)(arg->props_ptr),

sys/dev/pci/drm/drm_mode_object.c

492

uint32_t prop_id)

sys/dev/pci/drm/drm_mode_object.c

81

struct drm_mode_object *obj, uint32_t obj_type)

sys/dev/pci/drm/drm_modeset_helper.c

109

static const uint32_t safe_modeset_formats[] = {

sys/dev/pci/drm/drm_modeset_lock.c

253

uint32_t flags)

sys/dev/pci/drm/drm_plane.c

1022

uint32_t crtc_w, uint32_t crtc_h,

sys/dev/pci/drm/drm_plane.c

1024

uint32_t src_x, uint32_t src_y,

sys/dev/pci/drm/drm_plane.c

1025

uint32_t src_w, uint32_t src_h,

sys/dev/pci/drm/drm_plane.c

1075

uint32_t crtc_w, uint32_t crtc_h,

sys/dev/pci/drm/drm_plane.c

1076

uint32_t src_x, uint32_t src_y,

sys/dev/pci/drm/drm_plane.c

1077

uint32_t src_w, uint32_t src_h,

sys/dev/pci/drm/drm_plane.c

1110

uint32_t crtc_w, uint32_t crtc_h,

sys/dev/pci/drm/drm_plane.c

1112

uint32_t src_x, uint32_t src_y,

sys/dev/pci/drm/drm_plane.c

1113

uint32_t src_w, uint32_t src_h)

sys/dev/pci/drm/drm_plane.c

1203

uint32_t crtc_w = 0, crtc_h = 0;

sys/dev/pci/drm/drm_plane.c

1204

uint32_t src_w = 0, src_h = 0;

sys/dev/pci/drm/drm_plane.c

362

uint32_t possible_crtcs,

sys/dev/pci/drm/drm_plane.c

364

const uint32_t *formats,

sys/dev/pci/drm/drm_plane.c

402

plane->format_types = kmalloc_array(format_count, sizeof(uint32_t),

sys/dev/pci/drm/drm_plane.c

451

memcpy(plane->format_types, formats, format_count * sizeof(uint32_t));

sys/dev/pci/drm/drm_plane.c

533

uint32_t possible_crtcs,

sys/dev/pci/drm/drm_plane.c

535

const uint32_t *formats, unsigned int format_count,

sys/dev/pci/drm/drm_plane.c

565

size_t offset, uint32_t possible_crtcs,

sys/dev/pci/drm/drm_plane.c

567

const uint32_t *formats, unsigned int format_count,

sys/dev/pci/drm/drm_plane.c

604

size_t offset, uint32_t possible_crtcs,

sys/dev/pci/drm/drm_plane.c

606

const uint32_t *formats, unsigned int format_count,

sys/dev/pci/drm/drm_plane.c

807

uint32_t __user *plane_ptr;

sys/dev/pci/drm/drm_plane.c

858

uint32_t __user *format_ptr;

sys/dev/pci/drm/drm_plane.c

895

format_ptr = (uint32_t __user *)(unsigned long)plane_resp->format_type_ptr;

sys/dev/pci/drm/drm_plane.c

898

sizeof(uint32_t) * plane->format_count)) {

sys/dev/pci/drm/drm_plane.c

951

uint32_t crtc_w, uint32_t crtc_h,

sys/dev/pci/drm/drm_plane.c

952

uint32_t src_x, uint32_t src_y,

sys/dev/pci/drm/drm_plane.c

953

uint32_t src_w, uint32_t src_h)

sys/dev/pci/drm/drm_plane_helper.c

169

uint32_t src_x, uint32_t src_y,

sys/dev/pci/drm/drm_plane_helper.c

170

uint32_t src_w, uint32_t src_h,

sys/dev/pci/drm/drm_prime.c

144

uint32_t handle)

sys/dev/pci/drm/drm_prime.c

166

uint32_t *handle)

sys/dev/pci/drm/drm_prime.c

189

uint32_t handle)

sys/dev/pci/drm/drm_prime.c

295

uint32_t *handle)

sys/dev/pci/drm/drm_prime.c

378

uint32_t flags)

sys/dev/pci/drm/drm_prime.c

433

struct drm_file *file_priv, uint32_t handle,

sys/dev/pci/drm/drm_prime.c

434

uint32_t flags)

sys/dev/pci/drm/drm_prime.c

514

struct drm_file *file_priv, uint32_t handle,

sys/dev/pci/drm/drm_prime.c

515

uint32_t flags,

sys/dev/pci/drm/drm_prime.c

90

uint32_t handle;

sys/dev/pci/drm/drm_prime.c

97

struct dma_buf *dma_buf, uint32_t handle)

sys/dev/pci/drm/drm_probe_helper.c

446

uint32_t maxX, uint32_t maxY,

sys/dev/pci/drm/drm_probe_helper.c

560

uint32_t maxX, uint32_t maxY)

sys/dev/pci/drm/drm_property.c

334

uint32_t type)

sys/dev/pci/drm/drm_property.c

652

uint32_t id)

sys/dev/pci/drm/drm_syncobj.c

1122

uint32_t count,

sys/dev/pci/drm/drm_syncobj.c

1123

uint32_t flags,

sys/dev/pci/drm/drm_syncobj.c

1125

uint32_t *idx,

sys/dev/pci/drm/drm_syncobj.c

1131

uint32_t signaled_count, i;

sys/dev/pci/drm/drm_syncobj.c

1326

uint32_t first = ~0;

sys/dev/pci/drm/drm_syncobj.c

1356

uint32_t count_handles,

sys/dev/pci/drm/drm_syncobj.c

1359

uint32_t i, *handles;

sys/dev/pci/drm/drm_syncobj.c

1368

sizeof(uint32_t) * count_handles)) {

sys/dev/pci/drm/drm_syncobj.c

1402

uint32_t count)

sys/dev/pci/drm/drm_syncobj.c

1404

uint32_t i;

sys/dev/pci/drm/drm_syncobj.c

1610

uint32_t i;

sys/dev/pci/drm/drm_syncobj.c

1643

uint32_t i;

sys/dev/pci/drm/drm_syncobj.c

1681

uint32_t i, j;

sys/dev/pci/drm/drm_syncobj.c

1752

uint32_t i;

sys/dev/pci/drm/drm_syncobj.c

564

int drm_syncobj_create(struct drm_syncobj **out_syncobj, uint32_t flags,

sys/dev/pci/drm/drm_syncobj.c

632

u32 *handle, uint32_t flags)

sys/dev/pci/drm/i915/display/intel_gmbus.c

374

void intel_bb_set_bits(void *, uint32_t);

sys/dev/pci/drm/i915/display/intel_gmbus.c

375

void intel_bb_set_dir(void *, uint32_t);

sys/dev/pci/drm/i915/display/intel_gmbus.c

376

uint32_t intel_bb_read_bits(void *);

sys/dev/pci/drm/i915/display/intel_gmbus.c

397

intel_bb_set_bits(void *cookie, uint32_t bits)

sys/dev/pci/drm/i915/display/intel_gmbus.c

404

intel_bb_set_dir(void *cookie, uint32_t bits)

sys/dev/pci/drm/i915/display/intel_gmbus.c

408

uint32_t

sys/dev/pci/drm/i915/display/intel_gmbus.c

411

uint32_t bits = 0;

sys/dev/pci/drm/i915/gem/i915_gem_ttm.c

273

uint32_t page_flags)

sys/dev/pci/drm/i915/i915_driver.c

1920

void **, int *, int *, uint32_t *);

sys/dev/pci/drm/i915/i915_driver.c

2033

void **cookiep, int *curxp, int *curyp, uint32_t *attrp)

sys/dev/pci/drm/i915/i915_driver.c

2487

uint32_t defattr;

sys/dev/pci/drm/i915/intel_stolen.c

14

uint32_t bsm = pci_conf_read(dev_priv->pc, dev_priv->tag,

sys/dev/pci/drm/include/asm/div64.h

10

uint32_t __rem = ((uint64_t)(n)) % __base; \

sys/dev/pci/drm/include/asm/div64.h

9

uint32_t __base = (base); \

sys/dev/pci/drm/include/drm/drm_atomic_helper.h

129

uint32_t flags);

sys/dev/pci/drm/include/drm/drm_atomic_helper.h

154

uint32_t src_x, uint32_t src_y,

sys/dev/pci/drm/include/drm/drm_atomic_helper.h

155

uint32_t src_w, uint32_t src_h,

sys/dev/pci/drm/include/drm/drm_atomic_helper.h

179

uint32_t flags,

sys/dev/pci/drm/include/drm/drm_atomic_helper.h

185

uint32_t flags,

sys/dev/pci/drm/include/drm/drm_atomic_helper.h

186

uint32_t target,

sys/dev/pci/drm/include/drm/drm_connector.h

1409

int (*fill_modes)(struct drm_connector *connector, uint32_t max_width, uint32_t max_height);

sys/dev/pci/drm/include/drm/drm_connector.h

2377

uint32_t id)

sys/dev/pci/drm/include/drm/drm_crtc.h

1068

uint32_t gamma_size;

sys/dev/pci/drm/include/drm/drm_crtc.h

1198

uint32_t x;

sys/dev/pci/drm/include/drm/drm_crtc.h

1199

uint32_t y;

sys/dev/pci/drm/include/drm/drm_crtc.h

1277

static inline uint32_t drm_crtc_mask(const struct drm_crtc *crtc)

sys/dev/pci/drm/include/drm/drm_crtc.h

1297

uint32_t id)

sys/dev/pci/drm/include/drm/drm_crtc.h

437

uint32_t handle, uint32_t width, uint32_t height);

sys/dev/pci/drm/include/drm/drm_crtc.h

459

uint32_t handle, uint32_t width, uint32_t height,

sys/dev/pci/drm/include/drm/drm_crtc.h

494

uint32_t size,

sys/dev/pci/drm/include/drm/drm_crtc.h

579

uint32_t flags,

sys/dev/pci/drm/include/drm/drm_crtc.h

598

uint32_t flags, uint32_t target,

sys/dev/pci/drm/include/drm/drm_damage_helper.h

60

uint32_t num_clips;

sys/dev/pci/drm/include/drm/drm_damage_helper.h

62

uint32_t curr_clip;

sys/dev/pci/drm/include/drm/drm_debugfs_crc.h

41

uint32_t frame;

sys/dev/pci/drm/include/drm/drm_debugfs_crc.h

42

uint32_t crcs[DRM_MAX_CRC_NR];

sys/dev/pci/drm/include/drm/drm_debugfs_crc.h

71

uint32_t frame, uint32_t *crcs);

sys/dev/pci/drm/include/drm/drm_debugfs_crc.h

74

uint32_t frame, uint32_t *crcs)

sys/dev/pci/drm/include/drm/drm_drv.h

302

uint32_t handle, uint32_t flags, int *prime_fd);

sys/dev/pci/drm/include/drm/drm_drv.h

309

int prime_fd, uint32_t *handle);

sys/dev/pci/drm/include/drm/drm_drv.h

376

struct drm_device *dev, uint32_t handle,

sys/dev/pci/drm/include/drm/drm_encoder.h

156

uint32_t possible_crtcs;

sys/dev/pci/drm/include/drm/drm_encoder.h

177

uint32_t possible_clones;

sys/dev/pci/drm/include/drm/drm_encoder.h

313

uint32_t id)

sys/dev/pci/drm/include/drm/drm_format_helper.h

131

int drm_fb_blit(struct iosys_map *dst, const unsigned int *dst_pitch, uint32_t dst_format,

sys/dev/pci/drm/include/drm/drm_fourcc.h

312

uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth);

sys/dev/pci/drm/include/drm/drm_fourcc.h

313

uint32_t drm_driver_legacy_fb_format(struct drm_device *dev,

sys/dev/pci/drm/include/drm/drm_fourcc.h

314

uint32_t bpp, uint32_t depth);

sys/dev/pci/drm/include/drm/drm_fourcc.h

315

uint32_t drm_driver_color_mode_format(struct drm_device *dev, unsigned int color_mode);

sys/dev/pci/drm/include/drm/drm_framebuffer.h

218

uint32_t id);

sys/dev/pci/drm/include/drm/drm_framebuffer.h

252

static inline uint32_t drm_framebuffer_read_refcount(const struct drm_framebuffer *fb)

sys/dev/pci/drm/include/drm/drm_gem_dma_helper.h

14

uint32_t, uint64_t *);

sys/dev/pci/drm/include/drm/drm_mipi_dsi.h

27

uint32_t channel;

sys/dev/pci/drm/include/drm/drm_mipi_dsi.h

28

uint32_t mode_flags;

sys/dev/pci/drm/include/drm/drm_mode_config.h

886

uint32_t preferred_depth, prefer_shadow;

sys/dev/pci/drm/include/drm/drm_mode_config.h

952

uint32_t cursor_width, cursor_height;

sys/dev/pci/drm/include/drm/drm_mode_object.h

123

uint32_t id, uint32_t type);

sys/dev/pci/drm/include/drm/drm_mode_object.h

141

bool drm_mode_object_lease_required(uint32_t type);

sys/dev/pci/drm/include/drm/drm_mode_object.h

56

uint32_t id;

sys/dev/pci/drm/include/drm/drm_mode_object.h

57

uint32_t type;

sys/dev/pci/drm/include/drm/drm_modeset_lock.h

101

uint32_t flags);

sys/dev/pci/drm/include/drm/drm_plane.h

105

uint32_t crtc_w, crtc_h;

sys/dev/pci/drm/include/drm/drm_plane.h

111

uint32_t src_x;

sys/dev/pci/drm/include/drm/drm_plane.h

116

uint32_t src_y;

sys/dev/pci/drm/include/drm/drm_plane.h

119

uint32_t src_h, src_w;

sys/dev/pci/drm/include/drm/drm_plane.h

323

uint32_t src_x, uint32_t src_y,

sys/dev/pci/drm/include/drm/drm_plane.h

324

uint32_t src_w, uint32_t src_h,

sys/dev/pci/drm/include/drm/drm_plane.h

550

bool (*format_mod_supported)(struct drm_plane *plane, uint32_t format,

sys/dev/pci/drm/include/drm/drm_plane.h

667

uint32_t possible_crtcs;

sys/dev/pci/drm/include/drm/drm_plane.h

669

uint32_t *format_types;

sys/dev/pci/drm/include/drm/drm_plane.h

813

uint32_t possible_crtcs,

sys/dev/pci/drm/include/drm/drm_plane.h

815

const uint32_t *formats,

sys/dev/pci/drm/include/drm/drm_plane.h

825

uint32_t possible_crtcs,

sys/dev/pci/drm/include/drm/drm_plane.h

827

const uint32_t *formats,

sys/dev/pci/drm/include/drm/drm_plane.h

870

uint32_t possible_crtcs,

sys/dev/pci/drm/include/drm/drm_plane.h

872

const uint32_t *formats,

sys/dev/pci/drm/include/drm/drm_plane.h

950

uint32_t id)

sys/dev/pci/drm/include/drm/drm_plane_helper.h

38

uint32_t src_x, uint32_t src_y,

sys/dev/pci/drm/include/drm/drm_plane_helper.h

39

uint32_t src_w, uint32_t src_h,

sys/dev/pci/drm/include/drm/drm_prime.h

71

struct drm_file *file_priv, int prime_fd, uint32_t *handle);

sys/dev/pci/drm/include/drm/drm_prime.h

73

struct drm_file *file_priv, uint32_t handle,

sys/dev/pci/drm/include/drm/drm_prime.h

74

uint32_t flags);

sys/dev/pci/drm/include/drm/drm_prime.h

76

struct drm_file *file_priv, uint32_t handle, uint32_t flags,

sys/dev/pci/drm/include/drm/drm_probe_helper.h

14

*connector, uint32_t maxX,

sys/dev/pci/drm/include/drm/drm_probe_helper.h

15

uint32_t maxY);

sys/dev/pci/drm/include/drm/drm_property.h

166

uint32_t flags;

sys/dev/pci/drm/include/drm/drm_property.h

176

uint32_t num_values;

sys/dev/pci/drm/include/drm/drm_property.h

242

uint32_t type)

sys/dev/pci/drm/include/drm/drm_property.h

270

uint32_t type);

sys/dev/pci/drm/include/drm/drm_property.h

281

uint32_t id);

sys/dev/pci/drm/include/drm/drm_property.h

309

uint32_t id)

sys/dev/pci/drm/include/drm/drm_syncobj.h

130

int drm_syncobj_create(struct drm_syncobj **out_syncobj, uint32_t flags,

sys/dev/pci/drm/include/drm/intel/i915_hdcp_interface.h

16

uint32_t seq_num_m;

sys/dev/pci/drm/include/drm/ttm/ttm_bo.h

111

uint32_t page_alignment;

sys/dev/pci/drm/include/drm/ttm/ttm_bo.h

403

uint32_t alignment, struct ttm_operation_ctx *ctx,

sys/dev/pci/drm/include/drm/ttm/ttm_bo.h

408

uint32_t alignment, bool interruptible,

sys/dev/pci/drm/include/drm/ttm/ttm_device.h

74

uint32_t page_flags);

sys/dev/pci/drm/include/drm/ttm/ttm_placement.h

86

uint32_t mem_type;

sys/dev/pci/drm/include/drm/ttm/ttm_placement.h

87

uint32_t flags;

sys/dev/pci/drm/include/drm/ttm/ttm_resource.h

257

uint32_t mem_type;

sys/dev/pci/drm/include/drm/ttm/ttm_resource.h

258

uint32_t placement;

sys/dev/pci/drm/include/drm/ttm/ttm_tt.h

108

uint32_t page_flags;

sys/dev/pci/drm/include/drm/ttm/ttm_tt.h

110

uint32_t num_pages;

sys/dev/pci/drm/include/drm/ttm/ttm_tt.h

214

uint32_t page_flags, enum ttm_caching caching,

sys/dev/pci/drm/include/drm/ttm/ttm_tt.h

217

uint32_t page_flags, enum ttm_caching caching);

sys/dev/pci/drm/include/drm/ttm/ttm_tt.h

326

uint32_t page_flags);

sys/dev/pci/drm/include/linux/bitops.h

121

static inline uint32_t

sys/dev/pci/drm/include/linux/bitops.h

122

ror32(uint32_t word, unsigned int shift)

sys/dev/pci/drm/include/linux/clk.h

7

uint32_t freq;

sys/dev/pci/drm/include/linux/dma-fence.h

105

uint32_t al, bl;

sys/dev/pci/drm/include/linux/dma-fence.h

70

long dma_fence_wait_any_timeout(struct dma_fence **, uint32_t, bool, long,

sys/dev/pci/drm/include/linux/dma-fence.h

71

uint32_t *);

sys/dev/pci/drm/include/linux/fb.h

24

uint32_t xres;

sys/dev/pci/drm/include/linux/fb.h

25

uint32_t yres;

sys/dev/pci/drm/include/linux/fb.h

26

uint32_t width;

sys/dev/pci/drm/include/linux/fb.h

27

uint32_t height;

sys/dev/pci/drm/include/linux/hash.h

11

static inline uint32_t

sys/dev/pci/drm/include/linux/hash.h

12

hash_32(uint32_t val, unsigned int bits)

sys/dev/pci/drm/include/linux/hash.h

20

static inline uint32_t

sys/dev/pci/drm/include/linux/i2c.h

90

uint32_t (*functionality)(struct i2c_adapter *);

sys/dev/pci/drm/include/linux/io.h

121

uint32_t val;

sys/dev/pci/drm/include/linux/io.h

65

uint32_t val;

sys/dev/pci/drm/include/linux/io.h

68

val = *(volatile uint32_t *)addr;

sys/dev/pci/drm/include/linux/io.h

95

*(volatile uint32_t *)addr = val;

sys/dev/pci/drm/include/linux/iosys-map.h

107

uint32_t: ioread32(addr), \

sys/dev/pci/drm/include/linux/iosys-map.h

121

uint32_t: iowrite32(v, addr), \

sys/dev/pci/drm/include/linux/jiffies.h

69

#define time_after32(a,b) ((int32_t)((uint32_t)(b) - (uint32_t)(a)) < 0)

sys/dev/pci/drm/include/linux/kref.h

27

uint32_t refcount;

sys/dev/pci/drm/include/linux/math64.h

10

div_u64(uint64_t x, uint32_t y)

sys/dev/pci/drm/include/linux/math64.h

35

div_u64_rem(uint64_t x, uint32_t y, uint32_t *rem)

sys/dev/pci/drm/include/linux/math64.h

48

mul_u32_u32(uint32_t x, uint32_t y)

sys/dev/pci/drm/include/linux/math64.h

54

mul_u64_u32_div(uint64_t x, uint32_t y, uint32_t div)

sys/dev/pci/drm/include/linux/math64.h

60

DIV_U64_ROUND_UP(uint64_t x, uint32_t y)

sys/dev/pci/drm/include/linux/math64.h

78

mul_u64_u32_shr(uint64_t x, uint32_t y, unsigned int shift)

sys/dev/pci/drm/include/linux/math64.h

80

uint32_t hi, lo;

sys/dev/pci/drm/include/linux/mod_devicetable.h

49

uint32_t class;

sys/dev/pci/drm/include/linux/mod_devicetable.h

50

uint32_t class_mask;

sys/dev/pci/drm/include/linux/of.h

41

const char *, uint32_t *, size_t, size_t);

sys/dev/pci/drm/include/linux/of.h

65

uint32_t args[5];

sys/dev/pci/drm/include/linux/pci.h

152

uint32_t v;

sys/dev/pci/drm/include/linux/pci.h

162

uint32_t v;

sys/dev/pci/drm/include/linux/pci.h

179

uint32_t v;

sys/dev/pci/drm/include/linux/pci.h

191

uint32_t v;

sys/dev/pci/drm/include/linux/pci.h

206

uint32_t v;

sys/dev/pci/drm/include/linux/pci.h

219

uint32_t v;

sys/dev/pci/drm/include/linux/pci.h

232

uint32_t v;

sys/dev/pci/drm/include/linux/pci.h

62

uint32_t class; /* class:subclass:interface */

sys/dev/pci/drm/include/linux/random.h

15

static inline uint32_t

sys/dev/pci/drm/include/linux/random.h

16

get_random_u32_below(uint32_t x)

sys/dev/pci/drm/include/linux/random.h

45

static inline uint32_t

sys/dev/pci/drm/include/linux/random.h

46

prandom_u32_max(uint32_t x)

sys/dev/pci/drm/include/linux/random.h

9

static inline uint32_t

sys/dev/pci/drm/include/linux/refcount.h

12

refcount_dec_and_test(uint32_t *p)

sys/dev/pci/drm/include/linux/refcount.h

18

refcount_inc_not_zero(uint32_t *p)

sys/dev/pci/drm/include/linux/refcount.h

24

refcount_set(uint32_t *p, int v)

sys/dev/pci/drm/include/linux/refcount.h

43

static inline uint32_t

sys/dev/pci/drm/include/linux/refcount.h

44

refcount_read(uint32_t *p)

sys/dev/pci/drm/include/linux/stackdepot.h

6

typedef uint32_t depot_stack_handle_t;

sys/dev/pci/drm/include/linux/string.h

24

memset32(uint32_t *b, uint32_t c, size_t len)

sys/dev/pci/drm/include/linux/string.h

26

uint32_t *dst = b;

sys/dev/pci/drm/include/linux/string.h

47

return memset32((uint32_t *)p, (uintptr_t)v, n);

sys/dev/pci/drm/include/linux/types.h

20

typedef uint32_t __u32;

sys/dev/pci/drm/include/linux/types.h

29

typedef uint32_t u32;

sys/dev/pci/drm/include/linux/types.h

35

typedef uint32_t __le32;

sys/dev/pci/drm/include/linux/types.h

36

typedef uint32_t __be32;

sys/dev/pci/drm/include/linux/xarray.h

40

uint32_t start;

sys/dev/pci/drm/include/linux/xarray.h

41

uint32_t end;

sys/dev/pci/drm/include/uapi/drm/drm.h

63

typedef uint32_t __u32;

sys/dev/pci/drm/radeon/atom-bits.h

40

static inline uint32_t get_u32(void *bios, int ptr)

sys/dev/pci/drm/radeon/atom-bits.h

42

return get_u16(bios, ptr)|(((uint32_t)get_u16(bios, ptr+2))<<16);

sys/dev/pci/drm/radeon/atom-types.h

31

typedef uint32_t ULONG;

sys/dev/pci/drm/radeon/atom.c

1018

uint32_t dst, src;

sys/dev/pci/drm/radeon/atom.c

1030

uint32_t dst, src, saved;

sys/dev/pci/drm/radeon/atom.c

113

static uint32_t atom_iio_execute(struct atom_context *ctx, int base,

sys/dev/pci/drm/radeon/atom.c

114

uint32_t index, uint32_t data)

sys/dev/pci/drm/radeon/atom.c

117

uint32_t temp = 0xCDCDCDCD;

sys/dev/pci/drm/radeon/atom.c

1174

static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params, int params_size)

sys/dev/pci/drm/radeon/atom.c

1238

int atom_execute_table_scratch_unlocked(struct atom_context *ctx, int index, uint32_t *params, int params_size)

sys/dev/pci/drm/radeon/atom.c

1259

int atom_execute_table(struct atom_context *ctx, int index, uint32_t *params, int params_size)

sys/dev/pci/drm/radeon/atom.c

1349

uint32_t ps[16];

sys/dev/pci/drm/radeon/atom.c

184

static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,

sys/dev/pci/drm/radeon/atom.c

185

int *ptr, uint32_t *saved, int print)

sys/dev/pci/drm/radeon/atom.c

187

uint32_t idx, val = 0xCDCDCDCD, align, arg;

sys/dev/pci/drm/radeon/atom.c

377

uint32_t align = (attr >> 3) & 7, arg = attr & 7;

sys/dev/pci/drm/radeon/atom.c

411

static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)

sys/dev/pci/drm/radeon/atom.c

416

static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)

sys/dev/pci/drm/radeon/atom.c

418

uint32_t val = 0xCDCDCDCD;

sys/dev/pci/drm/radeon/atom.c

442

static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,

sys/dev/pci/drm/radeon/atom.c

443

int *ptr, uint32_t *saved, int print)

sys/dev/pci/drm/radeon/atom.c

459

int *ptr, uint32_t val, uint32_t saved)

sys/dev/pci/drm/radeon/atom.c

461

uint32_t align =

sys/dev/pci/drm/radeon/atom.c

605

uint32_t dst, src, saved;

sys/dev/pci/drm/radeon/atom.c

619

uint32_t dst, src, saved;

sys/dev/pci/drm/radeon/atom.c

62

uint32_t *ps, *ws;

sys/dev/pci/drm/radeon/atom.c

654

uint32_t saved;

sys/dev/pci/drm/radeon/atom.c

666

uint32_t dst, src;

sys/dev/pci/drm/radeon/atom.c

692

uint32_t dst, src;

sys/dev/pci/drm/radeon/atom.c

72

static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params, int params_size);

sys/dev/pci/drm/radeon/atom.c

73

int atom_execute_table(struct atom_context *ctx, int index, uint32_t *params, int params_size);

sys/dev/pci/drm/radeon/atom.c

75

static uint32_t atom_arg_mask[8] = {

sys/dev/pci/drm/radeon/atom.c

767

uint32_t dst, mask, src, saved;

sys/dev/pci/drm/radeon/atom.c

784

uint32_t src, saved;

sys/dev/pci/drm/radeon/atom.c

801

uint32_t dst, src;

sys/dev/pci/drm/radeon/atom.c

817

uint32_t dst, src, saved;

sys/dev/pci/drm/radeon/atom.c

907

uint32_t saved, dst;

sys/dev/pci/drm/radeon/atom.c

923

uint32_t saved, dst;

sys/dev/pci/drm/radeon/atom.c

939

uint32_t saved, dst;

sys/dev/pci/drm/radeon/atom.c

941

uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];

sys/dev/pci/drm/radeon/atom.c

958

uint32_t saved, dst;

sys/dev/pci/drm/radeon/atom.c

960

uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];

sys/dev/pci/drm/radeon/atom.c

977

uint32_t dst, src, saved;

sys/dev/pci/drm/radeon/atom.c

991

uint32_t src, val, target;

sys/dev/pci/drm/radeon/atom.h

115

void (* reg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */

sys/dev/pci/drm/radeon/atom.h

116

uint32_t (* reg_read)(struct card_info *, uint32_t); /* filled by driver */

sys/dev/pci/drm/radeon/atom.h

117

void (* ioreg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */

sys/dev/pci/drm/radeon/atom.h

118

uint32_t (* ioreg_read)(struct card_info *, uint32_t); /* filled by driver */

sys/dev/pci/drm/radeon/atom.h

119

void (* mc_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */

sys/dev/pci/drm/radeon/atom.h

120

uint32_t (* mc_read)(struct card_info *, uint32_t); /* filled by driver */

sys/dev/pci/drm/radeon/atom.h

121

void (* pll_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */

sys/dev/pci/drm/radeon/atom.h

122

uint32_t (* pll_read)(struct card_info *, uint32_t); /* filled by driver */

sys/dev/pci/drm/radeon/atom.h

130

uint32_t cmd_table, data_table;

sys/dev/pci/drm/radeon/atom.h

134

uint32_t fb_base;

sys/dev/pci/drm/radeon/atom.h

135

uint32_t divmul[2];

sys/dev/pci/drm/radeon/atom.h

141

uint32_t *scratch;

sys/dev/pci/drm/radeon/atom.h

148

int atom_execute_table(struct atom_context *, int, uint32_t *, int);

sys/dev/pci/drm/radeon/atom.h

149

int atom_execute_table_scratch_unlocked(struct atom_context *, int, uint32_t *, int);

sys/dev/pci/drm/radeon/atombios_crtc.c

1145

uint32_t fb_format, fb_pitch_pixels, tiling_flags;

sys/dev/pci/drm/radeon/atombios_crtc.c

1466

uint32_t fb_format, fb_pitch_pixels, tiling_flags;

sys/dev/pci/drm/radeon/atombios_crtc.c

160

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_crtc.c

181

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_crtc.c

197

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_crtc.c

213

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_crtc.c

245

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_crtc.c

264

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_crtc.c

346

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_crtc.c

392

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_crtc.c

549

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_crtc.c

695

index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_crtc.c

728

index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_crtc.c

80

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_crtc.c

812

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_crtc.c

952

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_dp.c

115

atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_dp.c

352

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

122

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

125

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

127

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

1364

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

1400

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

1522

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

1534

uint32_t temp, reg;

sys/dev/pci/drm/radeon/atombios_encoders.c

1557

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

1621

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

1624

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

1632

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

1640

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

1643

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

1986

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

2006

uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);

sys/dev/pci/drm/radeon/atombios_encoders.c

2055

uint32_t dig_enc_in_use = 0;

sys/dev/pci/drm/radeon/atombios_encoders.c

2313

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

2327

uint32_t bios_0_scratch;

sys/dev/pci/drm/radeon/atombios_encoders.c

2659

uint32_t encoder_enum,

sys/dev/pci/drm/radeon/atombios_encoders.c

2660

uint32_t supported_device,

sys/dev/pci/drm/radeon/atombios_encoders.c

392

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

448

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

549

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

667

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_encoders.c

982

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/atombios_i2c.c

81

atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/cik.c

3447

uint32_t scratch;

sys/dev/pci/drm/radeon/cik.c

3448

uint32_t tmp = 0;

sys/dev/pci/drm/radeon/cik.c

3772

uint32_t scratch;

sys/dev/pci/drm/radeon/cik.c

3773

uint32_t tmp = 0;

sys/dev/pci/drm/radeon/cik.c

5541

uint32_t reg;

sys/dev/pci/drm/radeon/cik.c

9432

uint32_t tmp;

sys/dev/pci/drm/radeon/cik_reg.h

230

uint32_t mask:24;

sys/dev/pci/drm/radeon/cik_reg.h

231

uint32_t vmid:4;

sys/dev/pci/drm/radeon/cik_reg.h

232

uint32_t atc:1;

sys/dev/pci/drm/radeon/cik_reg.h

233

uint32_t mode:2;

sys/dev/pci/drm/radeon/cik_reg.h

234

uint32_t valid:1;

sys/dev/pci/drm/radeon/cik_reg.h

236

uint32_t u32All;

sys/dev/pci/drm/radeon/cik_sdma.c

305

uint32_t reg_offset, value;

sys/dev/pci/drm/radeon/cik_sdma.c

62

uint32_t cik_sdma_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/cik_sdma.c

844

uint32_t incr, uint32_t flags)

sys/dev/pci/drm/radeon/cik_sdma.c

89

uint32_t cik_sdma_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/cik_sdma.c

893

uint32_t incr, uint32_t flags)

sys/dev/pci/drm/radeon/evergreen.c

3000

uint32_t cp_me;

sys/dev/pci/drm/radeon/evergreen_cs.c

1029

static uint32_t vline_start_end[6] = {

sys/dev/pci/drm/radeon/evergreen_cs.c

1037

static uint32_t vline_status[6] = {

sys/dev/pci/drm/radeon/evergreen_cs.c

1778

uint32_t *ib;

sys/dev/pci/drm/radeon/evergreen_cs.c

2622

uint32_t areg;

sys/dev/pci/drm/radeon/evergreen_cs.c

2623

uint32_t allowed_reg_base;

sys/dev/pci/drm/radeon/evergreen_cs.c

2624

uint32_t source_sel;

sys/dev/pci/drm/radeon/evergreen_cs.c

2644

uint32_t swap;

sys/dev/pci/drm/radeon/evergreen_cs.c

2893

uint32_t *ib = p->ib.ptr;

sys/dev/pci/drm/radeon/evergreen_cs.c

3591

uint32_t areg;

sys/dev/pci/drm/radeon/evergreen_cs.c

3592

uint32_t allowed_reg_base;

sys/dev/pci/drm/radeon/evergreen_cs.c

452

uint32_t *ib = p->ib.ptr;

sys/dev/pci/drm/radeon/evergreen_hdmi.c

324

uint32_t val;

sys/dev/pci/drm/radeon/evergreen_hdmi.c

457

uint32_t val;

sys/dev/pci/drm/radeon/evergreen_smc.h

41

uint32_t value[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/radeon/ni.c

1411

uint32_t next_rptr = ring->wptr + 3 + 4 + 8;

sys/dev/pci/drm/radeon/ni.c

1663

uint32_t rb_cntl;

sys/dev/pci/drm/radeon/ni_dma.c

356

uint32_t incr, uint32_t flags)

sys/dev/pci/drm/radeon/ni_dma.c

404

uint32_t incr, uint32_t flags)

sys/dev/pci/drm/radeon/ni_dma.c

52

uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/ni_dma.c

79

uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/nislands_smc.h

100

uint32_t aT;

sys/dev/pci/drm/radeon/nislands_smc.h

101

uint32_t bSP;

sys/dev/pci/drm/radeon/nislands_smc.h

108

uint32_t powergate_en;

sys/dev/pci/drm/radeon/nislands_smc.h

113

uint32_t SQPowerThrottle;

sys/dev/pci/drm/radeon/nislands_smc.h

114

uint32_t SQPowerThrottle_2;

sys/dev/pci/drm/radeon/nislands_smc.h

115

uint32_t reserved[2];

sys/dev/pci/drm/radeon/nislands_smc.h

154

uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX];

sys/dev/pci/drm/radeon/nislands_smc.h

167

uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS];

sys/dev/pci/drm/radeon/nislands_smc.h

198

uint32_t tpp[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES];

sys/dev/pci/drm/radeon/nislands_smc.h

199

uint32_t cacValue[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES];

sys/dev/pci/drm/radeon/nislands_smc.h

206

uint32_t cac_bif_lut[SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES];

sys/dev/pci/drm/radeon/nislands_smc.h

207

uint32_t cac_lkge_lut[SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES];

sys/dev/pci/drm/radeon/nislands_smc.h

209

uint32_t pwr_const;

sys/dev/pci/drm/radeon/nislands_smc.h

211

uint32_t dc_cacValue;

sys/dev/pci/drm/radeon/nislands_smc.h

212

uint32_t bif_cacValue;

sys/dev/pci/drm/radeon/nislands_smc.h

213

uint32_t lkge_pwr;

sys/dev/pci/drm/radeon/nislands_smc.h

221

uint32_t last_power;

sys/dev/pci/drm/radeon/nislands_smc.h

233

uint32_t dynPwr_TDP[4];

sys/dev/pci/drm/radeon/nislands_smc.h

234

uint32_t lkgePwr_TDP[4];

sys/dev/pci/drm/radeon/nislands_smc.h

235

uint32_t power_TDP[4];

sys/dev/pci/drm/radeon/nislands_smc.h

236

uint32_t avg_dynPwr_TDP;

sys/dev/pci/drm/radeon/nislands_smc.h

237

uint32_t avg_lkgePwr_TDP;

sys/dev/pci/drm/radeon/nislands_smc.h

238

uint32_t avg_power_TDP;

sys/dev/pci/drm/radeon/nislands_smc.h

239

uint32_t lts_power_TDP;

sys/dev/pci/drm/radeon/nislands_smc.h

258

uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/radeon/nislands_smc.h

273

uint32_t mc_arb_dram_timing;

sys/dev/pci/drm/radeon/nislands_smc.h

274

uint32_t mc_arb_dram_timing2;

sys/dev/pci/drm/radeon/nislands_smc.h

290

uint32_t freq[256];

sys/dev/pci/drm/radeon/nislands_smc.h

291

uint32_t ss[256];

sys/dev/pci/drm/radeon/nislands_smc.h

47

uint32_t TDPLimit;

sys/dev/pci/drm/radeon/nislands_smc.h

48

uint32_t NearTDPLimit;

sys/dev/pci/drm/radeon/nislands_smc.h

49

uint32_t SafePowerLimit;

sys/dev/pci/drm/radeon/nislands_smc.h

50

uint32_t PowerBoostLimit;

sys/dev/pci/drm/radeon/nislands_smc.h

55

uint32_t vCG_SPLL_FUNC_CNTL;

sys/dev/pci/drm/radeon/nislands_smc.h

56

uint32_t vCG_SPLL_FUNC_CNTL_2;

sys/dev/pci/drm/radeon/nislands_smc.h

57

uint32_t vCG_SPLL_FUNC_CNTL_3;

sys/dev/pci/drm/radeon/nislands_smc.h

58

uint32_t vCG_SPLL_FUNC_CNTL_4;

sys/dev/pci/drm/radeon/nislands_smc.h

59

uint32_t vCG_SPLL_SPREAD_SPECTRUM;

sys/dev/pci/drm/radeon/nislands_smc.h

60

uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;

sys/dev/pci/drm/radeon/nislands_smc.h

61

uint32_t sclk_value;

sys/dev/pci/drm/radeon/nislands_smc.h

67

uint32_t vMPLL_FUNC_CNTL;

sys/dev/pci/drm/radeon/nislands_smc.h

68

uint32_t vMPLL_FUNC_CNTL_1;

sys/dev/pci/drm/radeon/nislands_smc.h

69

uint32_t vMPLL_FUNC_CNTL_2;

sys/dev/pci/drm/radeon/nislands_smc.h

70

uint32_t vMPLL_AD_FUNC_CNTL;

sys/dev/pci/drm/radeon/nislands_smc.h

71

uint32_t vMPLL_AD_FUNC_CNTL_2;

sys/dev/pci/drm/radeon/nislands_smc.h

72

uint32_t vMPLL_DQ_FUNC_CNTL;

sys/dev/pci/drm/radeon/nislands_smc.h

73

uint32_t vMPLL_DQ_FUNC_CNTL_2;

sys/dev/pci/drm/radeon/nislands_smc.h

74

uint32_t vMCLK_PWRMGT_CNTL;

sys/dev/pci/drm/radeon/nislands_smc.h

75

uint32_t vDLL_CNTL;

sys/dev/pci/drm/radeon/nislands_smc.h

76

uint32_t vMPLL_SS;

sys/dev/pci/drm/radeon/nislands_smc.h

77

uint32_t vMPLL_SS2;

sys/dev/pci/drm/radeon/nislands_smc.h

78

uint32_t mclk_value;

sys/dev/pci/drm/radeon/ppsmc.h

172

#define PPSMC_MSG_DPM_Config ((uint32_t) 0x102)

sys/dev/pci/drm/radeon/ppsmc.h

173

#define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104)

sys/dev/pci/drm/radeon/ppsmc.h

174

#define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108)

sys/dev/pci/drm/radeon/ppsmc.h

175

#define PPSMC_MSG_Thermal_Cntl_Enable ((uint32_t) 0x10a)

sys/dev/pci/drm/radeon/ppsmc.h

176

#define PPSMC_MSG_Voltage_Cntl_Enable ((uint32_t) 0x109)

sys/dev/pci/drm/radeon/ppsmc.h

177

#define PPSMC_MSG_VCEPowerOFF ((uint32_t) 0x10e)

sys/dev/pci/drm/radeon/ppsmc.h

178

#define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f)

sys/dev/pci/drm/radeon/ppsmc.h

179

#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112)

sys/dev/pci/drm/radeon/ppsmc.h

180

#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d)

sys/dev/pci/drm/radeon/ppsmc.h

181

#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e)

sys/dev/pci/drm/radeon/ppsmc.h

182

#define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120)

sys/dev/pci/drm/radeon/ppsmc.h

183

#define PPSMC_MSG_DisableBAPM ((uint32_t) 0x121)

sys/dev/pci/drm/radeon/ppsmc.h

184

#define PPSMC_MSG_UVD_DPM_Config ((uint32_t) 0x124)

sys/dev/pci/drm/radeon/r100.c

1151

uint32_t tmp;

sys/dev/pci/drm/radeon/r100.c

1338

volatile uint32_t *ib;

sys/dev/pci/drm/radeon/r100.c

1460

uint32_t header, h_idx, reg;

sys/dev/pci/drm/radeon/r100.c

1461

volatile uint32_t *ib;

sys/dev/pci/drm/radeon/r100.c

1527

static int r100_get_vtx_size(uint32_t vtx_fmt)

sys/dev/pci/drm/radeon/r100.c

1586

volatile uint32_t *ib;

sys/dev/pci/drm/radeon/r100.c

1587

uint32_t tmp;

sys/dev/pci/drm/radeon/r100.c

167

uint32_t crtc_pitch, pitch_pixels;

sys/dev/pci/drm/radeon/r100.c

1809

uint32_t temp = idx_value >> 4;

sys/dev/pci/drm/radeon/r100.c

1945

volatile uint32_t *ib;

sys/dev/pci/drm/radeon/r100.c

2502

uint32_t tmp;

sys/dev/pci/drm/radeon/r100.c

2517

uint32_t tmp;

sys/dev/pci/drm/radeon/r100.c

2535

uint32_t tmp;

sys/dev/pci/drm/radeon/r100.c

2563

uint32_t tmp;

sys/dev/pci/drm/radeon/r100.c

2730

uint32_t tmp;

sys/dev/pci/drm/radeon/r100.c

2814

uint32_t tom;

sys/dev/pci/drm/radeon/r100.c

2844

uint32_t temp;

sys/dev/pci/drm/radeon/r100.c

2899

uint32_t save, tmp;

sys/dev/pci/drm/radeon/r100.c

2909

uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)

sys/dev/pci/drm/radeon/r100.c

2912

uint32_t data;

sys/dev/pci/drm/radeon/r100.c

2923

void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/pci/drm/radeon/r100.c

2955

uint32_t reg, value;

sys/dev/pci/drm/radeon/r100.c

2975

uint32_t rdp, wdp;

sys/dev/pci/drm/radeon/r100.c

3000

uint32_t csq_stat, csq2_stat, tmp;

sys/dev/pci/drm/radeon/r100.c

3048

uint32_t tmp;

sys/dev/pci/drm/radeon/r100.c

3113

uint32_t tiling_flags, uint32_t pitch,

sys/dev/pci/drm/radeon/r100.c

3114

uint32_t offset, uint32_t obj_size)

sys/dev/pci/drm/radeon/r100.c

3172

uint32_t temp, data, mem_trcd, mem_trp, mem_tras;

sys/dev/pci/drm/radeon/r100.c

3235

uint32_t pixel_bytes1 = 0;

sys/dev/pci/drm/radeon/r100.c

3236

uint32_t pixel_bytes2 = 0;

sys/dev/pci/drm/radeon/r100.c

3266

uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);

sys/dev/pci/drm/radeon/r100.c

3672

uint32_t scratch;

sys/dev/pci/drm/radeon/r100.c

3673

uint32_t tmp = 0;

sys/dev/pci/drm/radeon/r100.c

3728

uint32_t scratch;

sys/dev/pci/drm/radeon/r100.c

3729

uint32_t tmp = 0;

sys/dev/pci/drm/radeon/r100.c

4122

uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)

sys/dev/pci/drm/radeon/r100.c

4125

uint32_t ret;

sys/dev/pci/drm/radeon/r100.c

4134

void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/pci/drm/radeon/r100.c

673

uint32_t tmp;

sys/dev/pci/drm/radeon/r100.c

695

uint32_t tmp;

sys/dev/pci/drm/radeon/r100.c

704

uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags)

sys/dev/pci/drm/radeon/r100.c

725

uint32_t tmp = 0;

sys/dev/pci/drm/radeon/r100.c

768

static uint32_t r100_irq_ack(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/r100.c

770

uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);

sys/dev/pci/drm/radeon/r100.c

771

uint32_t irq_mask = RADEON_SW_INT_TEST |

sys/dev/pci/drm/radeon/r100.c

783

uint32_t status, msi_rearm;

sys/dev/pci/drm/radeon/r100.c

909

uint32_t cur_pages;

sys/dev/pci/drm/radeon/r100.c

910

uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;

sys/dev/pci/drm/radeon/r100.c

911

uint32_t pitch;

sys/dev/pci/drm/radeon/r100.c

912

uint32_t stride_pixels;

sys/dev/pci/drm/radeon/r200.c

132

static int r200_get_vtx_size_1(uint32_t vtx_fmt_1)

sys/dev/pci/drm/radeon/r200.c

151

volatile uint32_t *ib;

sys/dev/pci/drm/radeon/r200.c

152

uint32_t tmp;

sys/dev/pci/drm/radeon/r200.c

372

uint32_t temp = idx_value >> 4;

sys/dev/pci/drm/radeon/r200.c

39

static int r200_get_vtx_size_0(uint32_t vtx_fmt_0)

sys/dev/pci/drm/radeon/r200.c

91

uint32_t size;

sys/dev/pci/drm/radeon/r200.c

92

uint32_t cur_size;

sys/dev/pci/drm/radeon/r300.c

106

uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags)

sys/dev/pci/drm/radeon/r300.c

1178

volatile uint32_t *ib;

sys/dev/pci/drm/radeon/r300.c

153

uint32_t table_addr;

sys/dev/pci/drm/radeon/r300.c

154

uint32_t tmp;

sys/dev/pci/drm/radeon/r300.c

349

uint32_t tmp;

sys/dev/pci/drm/radeon/r300.c

365

uint32_t gb_tile_config, tmp;

sys/dev/pci/drm/radeon/r300.c

503

uint32_t link_width_cntl, mask;

sys/dev/pci/drm/radeon/r300.c

595

uint32_t tmp;

sys/dev/pci/drm/radeon/r300.c

60

uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)

sys/dev/pci/drm/radeon/r300.c

63

uint32_t r;

sys/dev/pci/drm/radeon/r300.c

633

volatile uint32_t *ib;

sys/dev/pci/drm/radeon/r300.c

634

uint32_t tmp, tile_flags = 0;

sys/dev/pci/drm/radeon/r300.c

72

void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/pci/drm/radeon/r300.c

89

uint32_t tmp;

sys/dev/pci/drm/radeon/r420.c

479

uint32_t tmp;

sys/dev/pci/drm/radeon/r520.c

39

uint32_t tmp;

sys/dev/pci/drm/radeon/r520.c

95

uint32_t tmp;

sys/dev/pci/drm/radeon/r600.c

1277

uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)

sys/dev/pci/drm/radeon/r600.c

1280

uint32_t r;

sys/dev/pci/drm/radeon/r600.c

1290

void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/pci/drm/radeon/r600.c

1437

uint32_t h_addr, l_addr;

sys/dev/pci/drm/radeon/r600.c

1984

int r600_count_pipe_bits(uint32_t val)

sys/dev/pci/drm/radeon/r600.c

2690

uint32_t cp_me;

sys/dev/pci/drm/radeon/r600.c

2825

uint32_t scratch;

sys/dev/pci/drm/radeon/r600.c

2826

uint32_t tmp = 0;

sys/dev/pci/drm/radeon/r600.c

3029

uint32_t tiling_flags, uint32_t pitch,

sys/dev/pci/drm/radeon/r600.c

3030

uint32_t offset, uint32_t obj_size)

sys/dev/pci/drm/radeon/r600.c

3192

uint32_t temp;

sys/dev/pci/drm/radeon/r600.c

3399

uint32_t scratch;

sys/dev/pci/drm/radeon/r600.c

3400

uint32_t tmp = 0;

sys/dev/pci/drm/radeon/r600_cs.c

476

uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);

sys/dev/pci/drm/radeon/r600_cs.c

479

uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);

sys/dev/pci/drm/radeon/r600_cs.c

494

uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);

sys/dev/pci/drm/radeon/r600_cs.c

497

uint32_t bytes = (block_max + 1) * 128;

sys/dev/pci/drm/radeon/r600_cs.c

798

static uint32_t vline_start_end[2] = {AVIVO_D1MODE_VLINE_START_END,

sys/dev/pci/drm/radeon/r600_cs.c

800

static uint32_t vline_status[2] = {AVIVO_D1MODE_VLINE_STATUS,

sys/dev/pci/drm/radeon/r600_cs.c

828

uint32_t *vline_start_end,

sys/dev/pci/drm/radeon/r600_cs.c

829

uint32_t *vline_status)

sys/dev/pci/drm/radeon/r600_cs.c

836

uint32_t header, h_idx, reg, wait_reg_mem_info;

sys/dev/pci/drm/radeon/r600_cs.c

837

volatile uint32_t *ib;

sys/dev/pci/drm/radeon/r600_dma.c

50

uint32_t r600_dma_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/r600_dma.c

71

uint32_t r600_dma_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/r600_hdmi.c

185

uint32_t acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL :

sys/dev/pci/drm/radeon/r600_hdmi.c

251

uint32_t offset = dig->afmt->offset;

sys/dev/pci/drm/radeon/r600_hdmi.c

269

uint32_t offset = dig->afmt->offset;

sys/dev/pci/drm/radeon/r600_hdmi.c

399

uint32_t offset;

sys/dev/pci/drm/radeon/r600_hdmi.c

400

uint32_t value;

sys/dev/pci/drm/radeon/r600_hdmi.c

63

uint32_t value;

sys/dev/pci/drm/radeon/radeon.h

1002

uint32_t **data);

sys/dev/pci/drm/radeon/radeon.h

1004

unsigned size, uint32_t *data);

sys/dev/pci/drm/radeon/radeon.h

1023

uint32_t length_dw;

sys/dev/pci/drm/radeon/radeon.h

1024

uint32_t *kdata;

sys/dev/pci/drm/radeon/radeon.h

1139

volatile uint32_t *wb;

sys/dev/pci/drm/radeon/radeon.h

1694

uint32_t handle, struct radeon_fence **fence);

sys/dev/pci/drm/radeon/radeon.h

1696

uint32_t handle, struct radeon_fence **fence);

sys/dev/pci/drm/radeon/radeon.h

1698

uint32_t allowed_domains);

sys/dev/pci/drm/radeon/radeon.h

1729

uint32_t keyselect;

sys/dev/pci/drm/radeon/radeon.h

1737

uint32_t handle, struct radeon_fence **fence);

sys/dev/pci/drm/radeon/radeon.h

1739

uint32_t handle, struct radeon_fence **fence);

sys/dev/pci/drm/radeon/radeon.h

1868

uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);

sys/dev/pci/drm/radeon/radeon.h

1883

uint32_t incr, uint32_t flags);

sys/dev/pci/drm/radeon/radeon.h

1888

uint32_t incr, uint32_t flags);

sys/dev/pci/drm/radeon/radeon.h

1940

uint32_t tiling_flags, uint32_t pitch,

sys/dev/pci/drm/radeon/radeon.h

1941

uint32_t offset, uint32_t obj_size);

sys/dev/pci/drm/radeon/radeon.h

1958

uint32_t (*get_engine_clock)(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon.h

1959

void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);

sys/dev/pci/drm/radeon/radeon.h

1960

uint32_t (*get_memory_clock)(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon.h

1961

void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);

sys/dev/pci/drm/radeon/radeon.h

2161

uint32_t tile_mode_array[32];

sys/dev/pci/drm/radeon/radeon.h

2162

uint32_t active_cus;

sys/dev/pci/drm/radeon/radeon.h

2192

uint32_t tile_mode_array[32];

sys/dev/pci/drm/radeon/radeon.h

2193

uint32_t macrotile_mode_array[16];

sys/dev/pci/drm/radeon/radeon.h

2194

uint32_t active_cus;

sys/dev/pci/drm/radeon/radeon.h

2250

volatile uint32_t *ptr;

sys/dev/pci/drm/radeon/radeon.h

2308

typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);

sys/dev/pci/drm/radeon/radeon.h

2309

typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);

sys/dev/pci/drm/radeon/radeon.h

2397

uint32_t pcie_reg_mask;

sys/dev/pci/drm/radeon/radeon.h

2423

uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];

sys/dev/pci/drm/radeon/radeon.h

2491

uint32_t flags);

sys/dev/pci/drm/radeon/radeon.h

2497

uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);

sys/dev/pci/drm/radeon/radeon.h

2498

void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/pci/drm/radeon/radeon.h

2499

static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,

sys/dev/pci/drm/radeon/radeon.h

2508

static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,

sys/dev/pci/drm/radeon/radeon.h

2582

uint32_t tmp_ = RREG32(reg); \

sys/dev/pci/drm/radeon/radeon.h

2591

uint32_t tmp_ = RREG32_PLL(reg); \

sys/dev/pci/drm/radeon/radeon.h

2598

uint32_t tmp_ = RREG32_SMC(reg); \

sys/dev/pci/drm/radeon/radeon.h

2618

uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/pci/drm/radeon/radeon.h

2619

void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/pci/drm/radeon/radeon.h

2723

static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)

sys/dev/pci/drm/radeon/radeon.h

284

uint32_t default_mclk;

sys/dev/pci/drm/radeon/radeon.h

285

uint32_t default_sclk;

sys/dev/pci/drm/radeon/radeon.h

2853

uint32_t flags);

sys/dev/pci/drm/radeon/radeon.h

286

uint32_t default_dispclk;

sys/dev/pci/drm/radeon/radeon.h

287

uint32_t current_dispclk;

sys/dev/pci/drm/radeon/radeon.h

288

uint32_t dp_extclk;

sys/dev/pci/drm/radeon/radeon.h

289

uint32_t max_pixel_clock;

sys/dev/pci/drm/radeon/radeon.h

290

uint32_t vco_freq;

sys/dev/pci/drm/radeon/radeon.h

2912

uint32_t flags);

sys/dev/pci/drm/radeon/radeon.h

2996

uint32_t *vline_start_end,

sys/dev/pci/drm/radeon/radeon.h

2997

uint32_t *vline_status);

sys/dev/pci/drm/radeon/radeon.h

375

uint32_t scratch_reg;

sys/dev/pci/drm/radeon/radeon.h

377

volatile uint32_t *cpu_addr;

sys/dev/pci/drm/radeon/radeon.h

473

uint32_t tiling_flags;

sys/dev/pci/drm/radeon/radeon.h

480

uint32_t flags;

sys/dev/pci/drm/radeon/radeon.h

555

uint32_t handle, uint64_t *offset_p);

sys/dev/pci/drm/radeon/radeon.h

639

dma_addr_t *dma_addr, uint32_t flags);

sys/dev/pci/drm/radeon/radeon.h

675

uint32_t reg_base;

sys/dev/pci/drm/radeon/radeon.h

677

uint32_t reg[32];

sys/dev/pci/drm/radeon/radeon.h

680

int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);

sys/dev/pci/drm/radeon/radeon.h

681

void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);

sys/dev/pci/drm/radeon/radeon.h

793

uint32_t length_dw;

sys/dev/pci/drm/radeon/radeon.h

795

uint32_t *ptr;

sys/dev/pci/drm/radeon/radeon.h

806

volatile uint32_t *ring;

sys/dev/pci/drm/radeon/radeon.h

819

uint32_t align_mask;

sys/dev/pci/drm/radeon/radeon.h

820

uint32_t ptr_mask;

sys/dev/pci/drm/radeon/radeon.h

919

uint32_t max_pfn;

sys/dev/pci/drm/radeon/radeon.h

927

uint32_t saved_table_addr[RADEON_NUM_VM];

sys/dev/pci/drm/radeon/radeon.h

942

volatile uint32_t *ring;

sys/dev/pci/drm/radeon/radeon.h

946

uint32_t ptr_mask;

sys/dev/pci/drm/radeon/radeon.h

960

volatile uint32_t *sr_ptr;

sys/dev/pci/drm/radeon/radeon.h

966

volatile uint32_t *cs_ptr;

sys/dev/pci/drm/radeon/radeon.h

972

volatile uint32_t *cp_table_ptr;

sys/dev/pci/drm/radeon/radeon_agp.c

246

uint32_t agp_status;

sys/dev/pci/drm/radeon/radeon_asic.c

53

static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)

sys/dev/pci/drm/radeon/radeon_asic.c

70

static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/pci/drm/radeon/radeon_asic.h

177

extern uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags);

sys/dev/pci/drm/radeon/radeon_asic.h

213

uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags);

sys/dev/pci/drm/radeon/radeon_asic.h

216

uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/pci/drm/radeon/radeon_asic.h

217

void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/pci/drm/radeon/radeon_asic.h

238

uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags);

sys/dev/pci/drm/radeon/radeon_asic.h

241

uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/pci/drm/radeon/radeon_asic.h

242

void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/pci/drm/radeon/radeon_asic.h

266

uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/pci/drm/radeon/radeon_asic.h

267

void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/pci/drm/radeon/radeon_asic.h

285

uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/pci/drm/radeon/radeon_asic.h

286

void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/pci/drm/radeon/radeon_asic.h

318

uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/pci/drm/radeon/radeon_asic.h

319

void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/pci/drm/radeon/radeon_asic.h

339

uint32_t tiling_flags, uint32_t pitch,

sys/dev/pci/drm/radeon/radeon_asic.h

34

uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

340

uint32_t offset, uint32_t obj_size);

sys/dev/pci/drm/radeon/radeon_asic.h

35

void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);

sys/dev/pci/drm/radeon/radeon_asic.h

36

uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

365

extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/pci/drm/radeon/radeon_asic.h

366

extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/pci/drm/radeon/radeon_asic.h

376

int r600_count_pipe_bits(uint32_t val);

sys/dev/pci/drm/radeon/radeon_asic.h

39

uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

40

void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);

sys/dev/pci/drm/radeon/radeon_asic.h

403

void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock);

sys/dev/pci/drm/radeon/radeon_asic.h

41

uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);

sys/dev/pci/drm/radeon/radeon_asic.h

414

uint32_t r600_dma_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

416

uint32_t r600_dma_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

42

void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);

sys/dev/pci/drm/radeon/radeon_asic.h

615

uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);

sys/dev/pci/drm/radeon/radeon_asic.h

631

uint32_t incr, uint32_t flags);

sys/dev/pci/drm/radeon/radeon_asic.h

636

uint32_t incr, uint32_t flags);

sys/dev/pci/drm/radeon/radeon_asic.h

648

uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

650

uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

70

uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags);

sys/dev/pci/drm/radeon/radeon_asic.h

737

uint32_t incr, uint32_t flags);

sys/dev/pci/drm/radeon/radeon_asic.h

742

uint32_t incr, uint32_t flags);

sys/dev/pci/drm/radeon/radeon_asic.h

784

uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/pci/drm/radeon/radeon_asic.h

785

void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/pci/drm/radeon/radeon_asic.h

83

void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

sys/dev/pci/drm/radeon/radeon_asic.h

839

uint32_t incr, uint32_t flags);

sys/dev/pci/drm/radeon/radeon_asic.h

84

uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);

sys/dev/pci/drm/radeon/radeon_asic.h

844

uint32_t incr, uint32_t flags);

sys/dev/pci/drm/radeon/radeon_asic.h

91

uint32_t tiling_flags, uint32_t pitch,

sys/dev/pci/drm/radeon/radeon_asic.h

92

uint32_t offset, uint32_t obj_size);

sys/dev/pci/drm/radeon/radeon_asic.h

927

uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

929

uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

969

uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

971

uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_asic.h

975

int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data);

sys/dev/pci/drm/radeon/radeon_atombios.c

282

uint32_t supported_device,

sys/dev/pci/drm/radeon/radeon_atombios.c

2865

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

2879

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

2894

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

2914

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

2933

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

2944

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

2985

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

3018

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

3021

uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/radeon_atombios.c

3026

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

3030

uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/radeon_atombios.c

3035

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

3040

uint32_t eng_clock)

sys/dev/pci/drm/radeon/radeon_atombios.c

3047

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

3051

uint32_t mem_clock)

sys/dev/pci/drm/radeon/radeon_atombios.c

3061

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

3080

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

3091

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

3103

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

3147

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

3168

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

3177

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

3213

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

3340

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

3366

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

3374

atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));

sys/dev/pci/drm/radeon/radeon_atombios.c

4085

uint32_t bios_2_scratch, bios_6_scratch;

sys/dev/pci/drm/radeon/radeon_atombios.c

4117

uint32_t scratch_reg;

sys/dev/pci/drm/radeon/radeon_atombios.c

4131

uint32_t scratch_reg;

sys/dev/pci/drm/radeon/radeon_atombios.c

4147

uint32_t bios_6_scratch;

sys/dev/pci/drm/radeon/radeon_atombios.c

4179

uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;

sys/dev/pci/drm/radeon/radeon_atombios.c

4361

uint32_t bios_3_scratch;

sys/dev/pci/drm/radeon/radeon_atombios.c

4416

uint32_t bios_2_scratch;

sys/dev/pci/drm/radeon/radeon_atombios.c

606

uint32_t slot_config, ct;

sys/dev/pci/drm/radeon/radeon_atombios.h

39

void radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,

sys/dev/pci/drm/radeon/radeon_atombios.h

40

uint32_t supported_device, u16 caps);

sys/dev/pci/drm/radeon/radeon_bios.c

435

uint32_t viph_control;

sys/dev/pci/drm/radeon/radeon_bios.c

436

uint32_t bus_cntl;

sys/dev/pci/drm/radeon/radeon_bios.c

437

uint32_t d1vga_control;

sys/dev/pci/drm/radeon/radeon_bios.c

438

uint32_t d2vga_control;

sys/dev/pci/drm/radeon/radeon_bios.c

439

uint32_t vga_render_control;

sys/dev/pci/drm/radeon/radeon_bios.c

440

uint32_t rom_cntl;

sys/dev/pci/drm/radeon/radeon_bios.c

441

uint32_t cg_spll_func_cntl = 0;

sys/dev/pci/drm/radeon/radeon_bios.c

442

uint32_t cg_spll_status;

sys/dev/pci/drm/radeon/radeon_bios.c

504

uint32_t viph_control;

sys/dev/pci/drm/radeon/radeon_bios.c

505

uint32_t bus_cntl;

sys/dev/pci/drm/radeon/radeon_bios.c

506

uint32_t d1vga_control;

sys/dev/pci/drm/radeon/radeon_bios.c

507

uint32_t d2vga_control;

sys/dev/pci/drm/radeon/radeon_bios.c

508

uint32_t vga_render_control;

sys/dev/pci/drm/radeon/radeon_bios.c

509

uint32_t rom_cntl;

sys/dev/pci/drm/radeon/radeon_bios.c

510

uint32_t general_pwrmgt;

sys/dev/pci/drm/radeon/radeon_bios.c

511

uint32_t low_vid_lower_gpio_cntl;

sys/dev/pci/drm/radeon/radeon_bios.c

512

uint32_t medium_vid_lower_gpio_cntl;

sys/dev/pci/drm/radeon/radeon_bios.c

513

uint32_t high_vid_lower_gpio_cntl;

sys/dev/pci/drm/radeon/radeon_bios.c

514

uint32_t ctxsw_vid_lower_gpio_cntl;

sys/dev/pci/drm/radeon/radeon_bios.c

515

uint32_t lower_gpio_enable;

sys/dev/pci/drm/radeon/radeon_bios.c

591

uint32_t seprom_cntl1;

sys/dev/pci/drm/radeon/radeon_bios.c

592

uint32_t viph_control;

sys/dev/pci/drm/radeon/radeon_bios.c

593

uint32_t bus_cntl;

sys/dev/pci/drm/radeon/radeon_bios.c

594

uint32_t d1vga_control;

sys/dev/pci/drm/radeon/radeon_bios.c

595

uint32_t d2vga_control;

sys/dev/pci/drm/radeon/radeon_bios.c

596

uint32_t vga_render_control;

sys/dev/pci/drm/radeon/radeon_bios.c

597

uint32_t gpiopad_a;

sys/dev/pci/drm/radeon/radeon_bios.c

598

uint32_t gpiopad_en;

sys/dev/pci/drm/radeon/radeon_bios.c

599

uint32_t gpiopad_mask;

sys/dev/pci/drm/radeon/radeon_bios.c

652

uint32_t seprom_cntl1;

sys/dev/pci/drm/radeon/radeon_bios.c

653

uint32_t viph_control;

sys/dev/pci/drm/radeon/radeon_bios.c

654

uint32_t bus_cntl;

sys/dev/pci/drm/radeon/radeon_bios.c

655

uint32_t crtc_gen_cntl;

sys/dev/pci/drm/radeon/radeon_bios.c

656

uint32_t crtc2_gen_cntl;

sys/dev/pci/drm/radeon/radeon_bios.c

657

uint32_t crtc_ext_cntl;

sys/dev/pci/drm/radeon/radeon_bios.c

658

uint32_t fp2_gen_cntl;

sys/dev/pci/drm/radeon/radeon_clocks.c

197

uint32_t val;

sys/dev/pci/drm/radeon/radeon_clocks.c

435

static uint32_t calc_eng_mem_clock(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/radeon_clocks.c

436

uint32_t req_clock,

sys/dev/pci/drm/radeon/radeon_clocks.c

44

uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/radeon_clocks.c

47

uint32_t fb_div, ref_div, post_div, sclk;

sys/dev/pci/drm/radeon/radeon_clocks.c

475

uint32_t eng_clock)

sys/dev/pci/drm/radeon/radeon_clocks.c

477

uint32_t tmp;

sys/dev/pci/drm/radeon/radeon_clocks.c

562

uint32_t tmp;

sys/dev/pci/drm/radeon/radeon_clocks.c

74

uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)

sys/dev/pci/drm/radeon/radeon_clocks.c

77

uint32_t fb_div, ref_div, post_div, mclk;

sys/dev/pci/drm/radeon/radeon_combios.c

1098

uint32_t fp_vert_stretch, fp_horz_stretch;

sys/dev/pci/drm/radeon/radeon_combios.c

1099

uint32_t ppll_div_sel, ppll_val;

sys/dev/pci/drm/radeon/radeon_combios.c

1100

uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);

sys/dev/pci/drm/radeon/radeon_combios.c

1169

uint32_t panel_setup;

sys/dev/pci/drm/radeon/radeon_combios.c

2268

uint32_t ext_tmds_info;

sys/dev/pci/drm/radeon/radeon_combios.c

2303

uint32_t conn_info, entry, devices;

sys/dev/pci/drm/radeon/radeon_combios.c

2596

uint32_t tv_info =

sys/dev/pci/drm/radeon/radeon_combios.c

2888

uint32_t index, id;

sys/dev/pci/drm/radeon/radeon_combios.c

2889

uint32_t reg, val, and_mask, or_mask;

sys/dev/pci/drm/radeon/radeon_combios.c

3019

uint32_t addr = (RBIOS16(offset) & 0x1fff);

sys/dev/pci/drm/radeon/radeon_combios.c

3020

uint32_t val, and_mask, or_mask;

sys/dev/pci/drm/radeon/radeon_combios.c

3021

uint32_t tmp;

sys/dev/pci/drm/radeon/radeon_combios.c

3099

uint32_t val, shift, tmp;

sys/dev/pci/drm/radeon/radeon_combios.c

3100

uint32_t and_mask, or_mask;

sys/dev/pci/drm/radeon/radeon_combios.c

3154

uint32_t mclk_cntl =

sys/dev/pci/drm/radeon/radeon_combios.c

3185

uint32_t tmp;

sys/dev/pci/drm/radeon/radeon_combios.c

3193

uint32_t channel_complete_mask;

sys/dev/pci/drm/radeon/radeon_combios.c

3209

uint32_t or_mask = RBIOS16(offset);

sys/dev/pci/drm/radeon/radeon_combios.c

3228

static uint32_t combios_detect_ram(struct drm_device *dev, int ram,

sys/dev/pci/drm/radeon/radeon_combios.c

3232

uint32_t mem_cntl;

sys/dev/pci/drm/radeon/radeon_combios.c

3233

uint32_t mem_size;

sys/dev/pci/drm/radeon/radeon_combios.c

3234

uint32_t addr = 0;

sys/dev/pci/drm/radeon/radeon_combios.c

3265

uint32_t mem_size = 0;

sys/dev/pci/drm/radeon/radeon_combios.c

3266

uint32_t mem_cntl = 0;

sys/dev/pci/drm/radeon/radeon_combios.c

3417

uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;

sys/dev/pci/drm/radeon/radeon_combios.c

3442

uint32_t bios_6_scratch;

sys/dev/pci/drm/radeon/radeon_combios.c

3464

uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);

sys/dev/pci/drm/radeon/radeon_combios.c

3465

uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);

sys/dev/pci/drm/radeon/radeon_combios.c

3563

uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);

sys/dev/pci/drm/radeon/radeon_combios.c

3598

uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);

sys/dev/pci/drm/radeon/radeon_combios.c

824

static const uint32_t default_primarydac_adj[CHIP_LAST] = {

sys/dev/pci/drm/radeon/radeon_combios.c

971

static const uint32_t default_tvdac_adj[CHIP_LAST] = {

sys/dev/pci/drm/radeon/radeon_connectors.c

1834

uint32_t connector_id,

sys/dev/pci/drm/radeon/radeon_connectors.c

1835

uint32_t supported_device,

sys/dev/pci/drm/radeon/radeon_connectors.c

1838

uint32_t igp_lane_info,

sys/dev/pci/drm/radeon/radeon_connectors.c

1850

uint32_t subpixel_order = SubPixelNone;

sys/dev/pci/drm/radeon/radeon_connectors.c

2360

uint32_t connector_id,

sys/dev/pci/drm/radeon/radeon_connectors.c

2361

uint32_t supported_device,

sys/dev/pci/drm/radeon/radeon_connectors.c

2371

uint32_t subpixel_order = SubPixelNone;

sys/dev/pci/drm/radeon/radeon_cs.c

147

uint32_t domain = r->write_domain ?

sys/dev/pci/drm/radeon/radeon_cs.c

163

uint32_t domain = p->relocs[i].preferred_domains;

sys/dev/pci/drm/radeon/radeon_cs.c

311

uint32_t __user *cdata;

sys/dev/pci/drm/radeon/radeon_cs.c

352

p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/radeon/radeon_cs.c

353

size *= sizeof(uint32_t);

sys/dev/pci/drm/radeon/radeon_cs.c

752

uint32_t header;

sys/dev/pci/drm/radeon/radeon_cs.c

834

volatile uint32_t *ib;

sys/dev/pci/drm/radeon/radeon_cursor.c

278

uint32_t handle,

sys/dev/pci/drm/radeon/radeon_cursor.c

279

uint32_t width,

sys/dev/pci/drm/radeon/radeon_cursor.c

280

uint32_t height,

sys/dev/pci/drm/radeon/radeon_cursor.c

36

uint32_t cur_lock;

sys/dev/pci/drm/radeon/radeon_device.c

1296

uint32_t flags)

sys/dev/pci/drm/radeon/radeon_device.c

1805

uint32_t *ring_data[RADEON_NUM_RINGS];

sys/dev/pci/drm/radeon/radeon_device.c

293

int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)

sys/dev/pci/drm/radeon/radeon_device.c

315

void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)

sys/dev/pci/drm/radeon/radeon_device.c

356

DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);

sys/dev/pci/drm/radeon/radeon_device.c

669

uint32_t reg;

sys/dev/pci/drm/radeon/radeon_device.c

844

static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)

sys/dev/pci/drm/radeon/radeon_device.c

847

uint32_t r;

sys/dev/pci/drm/radeon/radeon_device.c

862

static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)

sys/dev/pci/drm/radeon/radeon_device.c

878

static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)

sys/dev/pci/drm/radeon/radeon_device.c

881

uint32_t r;

sys/dev/pci/drm/radeon/radeon_device.c

896

static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)

sys/dev/pci/drm/radeon/radeon_device.c

912

static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)

sys/dev/pci/drm/radeon/radeon_device.c

928

static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)

sys/dev/pci/drm/radeon/radeon_device.c

931

uint32_t r;

sys/dev/pci/drm/radeon/radeon_device.c

946

static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)

sys/dev/pci/drm/radeon/radeon_device.c

962

static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)

sys/dev/pci/drm/radeon/radeon_device.c

965

uint32_t r;

sys/dev/pci/drm/radeon/radeon_display.c

1099

static inline uint32_t radeon_div(uint64_t n, uint32_t d)

sys/dev/pci/drm/radeon/radeon_display.c

1109

uint32_t *dot_clock_p,

sys/dev/pci/drm/radeon/radeon_display.c

1110

uint32_t *fb_div_p,

sys/dev/pci/drm/radeon/radeon_display.c

1111

uint32_t *frac_fb_div_p,

sys/dev/pci/drm/radeon/radeon_display.c

1112

uint32_t *ref_div_p,

sys/dev/pci/drm/radeon/radeon_display.c

1113

uint32_t *post_div_p)

sys/dev/pci/drm/radeon/radeon_display.c

1115

uint32_t min_ref_div = pll->min_ref_div;

sys/dev/pci/drm/radeon/radeon_display.c

1116

uint32_t max_ref_div = pll->max_ref_div;

sys/dev/pci/drm/radeon/radeon_display.c

1117

uint32_t min_post_div = pll->min_post_div;

sys/dev/pci/drm/radeon/radeon_display.c

1118

uint32_t max_post_div = pll->max_post_div;

sys/dev/pci/drm/radeon/radeon_display.c

1119

uint32_t min_fractional_feed_div = 0;

sys/dev/pci/drm/radeon/radeon_display.c

1120

uint32_t max_fractional_feed_div = 0;

sys/dev/pci/drm/radeon/radeon_display.c

1121

uint32_t best_vco = pll->best_vco;

sys/dev/pci/drm/radeon/radeon_display.c

1122

uint32_t best_post_div = 1;

sys/dev/pci/drm/radeon/radeon_display.c

1123

uint32_t best_ref_div = 1;

sys/dev/pci/drm/radeon/radeon_display.c

1124

uint32_t best_feedback_div = 1;

sys/dev/pci/drm/radeon/radeon_display.c

1125

uint32_t best_frac_feedback_div = 0;

sys/dev/pci/drm/radeon/radeon_display.c

1126

uint32_t best_freq = -1;

sys/dev/pci/drm/radeon/radeon_display.c

1127

uint32_t best_error = 0xffffffff;

sys/dev/pci/drm/radeon/radeon_display.c

1128

uint32_t best_vco_diff = 1;

sys/dev/pci/drm/radeon/radeon_display.c

1129

uint32_t post_div;

sys/dev/pci/drm/radeon/radeon_display.c

1150

uint32_t mid = (min_ref_div + max_ref_div) / 2;

sys/dev/pci/drm/radeon/radeon_display.c

1151

uint32_t pll_in = pll->reference_freq / mid;

sys/dev/pci/drm/radeon/radeon_display.c

1170

uint32_t ref_div;

sys/dev/pci/drm/radeon/radeon_display.c

1189

uint32_t feedback_div, current_freq = 0, error, vco_diff;

sys/dev/pci/drm/radeon/radeon_display.c

1190

uint32_t pll_in = pll->reference_freq / ref_div;

sys/dev/pci/drm/radeon/radeon_display.c

1191

uint32_t min_feed_div = pll->min_feedback_div;

sys/dev/pci/drm/radeon/radeon_display.c

1192

uint32_t max_feed_div = pll->max_feedback_div + 1;

sys/dev/pci/drm/radeon/radeon_display.c

1198

uint32_t vco;

sys/dev/pci/drm/radeon/radeon_display.c

1199

uint32_t min_frac_feed_div = min_fractional_feed_div;

sys/dev/pci/drm/radeon/radeon_display.c

1200

uint32_t max_frac_feed_div = max_fractional_feed_div + 1;

sys/dev/pci/drm/radeon/radeon_display.c

1201

uint32_t frac_feedback_div;

sys/dev/pci/drm/radeon/radeon_display.c

1504

static uint32_t eg_offsets[] = {

sys/dev/pci/drm/radeon/radeon_display.c

200

uint32_t dac2_cntl;

sys/dev/pci/drm/radeon/radeon_display.c

204

dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;

sys/dev/pci/drm/radeon/radeon_display.c

240

u16 *blue, uint32_t size,

sys/dev/pci/drm/radeon/radeon_display.c

481

uint32_t page_flip_flags,

sys/dev/pci/drm/radeon/radeon_display.c

482

uint32_t target,

sys/dev/pci/drm/radeon/radeon_display.c

491

uint32_t tiling_flags, pitch_pixels;

sys/dev/pci/drm/radeon/radeon_display.c

582

work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +

sys/dev/pci/drm/radeon/radeon_display.c

774

uint32_t devices;

sys/dev/pci/drm/radeon/radeon_dp_auxch.c

62

uint32_t tmp, ack = 0;

sys/dev/pci/drm/radeon/radeon_drv.c

1313

uint32_t defattr;

sys/dev/pci/drm/radeon/radeon_drv.c

739

void **, int *, int *, uint32_t *);

sys/dev/pci/drm/radeon/radeon_drv.c

825

void **cookiep, int *curxp, int *curyp, uint32_t *attrp)

sys/dev/pci/drm/radeon/radeon_encoders.c

40

static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)

sys/dev/pci/drm/radeon/radeon_encoders.c

46

uint32_t index_mask = drm_encoder_mask(encoder);

sys/dev/pci/drm/radeon/radeon_encoders.c

86

uint32_t

sys/dev/pci/drm/radeon/radeon_encoders.c

87

radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)

sys/dev/pci/drm/radeon/radeon_encoders.c

90

uint32_t ret = 0;

sys/dev/pci/drm/radeon/radeon_gart.c

333

uint32_t flags)

sys/dev/pci/drm/radeon/radeon_gem.c

218

uint32_t rdomain, uint32_t wdomain)

sys/dev/pci/drm/radeon/radeon_gem.c

221

uint32_t domain;

sys/dev/pci/drm/radeon/radeon_gem.c

408

uint32_t handle;

sys/dev/pci/drm/radeon/radeon_gem.c

445

uint32_t handle;

sys/dev/pci/drm/radeon/radeon_gem.c

560

uint32_t handle, uint64_t *offset_p)

sys/dev/pci/drm/radeon/radeon_gem.c

594

uint32_t cur_placement = 0;

sys/dev/pci/drm/radeon/radeon_gem.c

622

uint32_t cur_placement = 0;

sys/dev/pci/drm/radeon/radeon_gem.c

933

uint32_t handle;

sys/dev/pci/drm/radeon/radeon_i2c.c

163

uint32_t temp;

sys/dev/pci/drm/radeon/radeon_i2c.c

182

uint32_t val;

sys/dev/pci/drm/radeon/radeon_i2c.c

197

uint32_t val;

sys/dev/pci/drm/radeon/radeon_i2c.c

211

uint32_t val;

sys/dev/pci/drm/radeon/radeon_i2c.c

224

uint32_t val;

sys/dev/pci/drm/radeon/radeon_i2c.c

234

void radeon_bb_set_bits(void *, uint32_t);

sys/dev/pci/drm/radeon/radeon_i2c.c

235

void radeon_bb_set_dir(void *, uint32_t);

sys/dev/pci/drm/radeon/radeon_i2c.c

236

uint32_t radeon_bb_read_bits(void *);

sys/dev/pci/drm/radeon/radeon_i2c.c

257

radeon_bb_set_bits(void *cookie, uint32_t bits)

sys/dev/pci/drm/radeon/radeon_i2c.c

264

radeon_bb_set_dir(void *cookie, uint32_t bits)

sys/dev/pci/drm/radeon/radeon_i2c.c

268

uint32_t

sys/dev/pci/drm/radeon/radeon_i2c.c

271

uint32_t bits = 0;

sys/dev/pci/drm/radeon/radeon_i2c.c

93

uint32_t temp;

sys/dev/pci/drm/radeon/radeon_kms.c

199

uint32_t *value)

sys/dev/pci/drm/radeon/radeon_kms.c

237

uint32_t *value, value_tmp, *value_ptr, value_size;

sys/dev/pci/drm/radeon/radeon_kms.c

243

value_ptr = (uint32_t *)((unsigned long)info->value);

sys/dev/pci/drm/radeon/radeon_kms.c

245

value_size = sizeof(uint32_t);

sys/dev/pci/drm/radeon/radeon_kms.c

269

if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {

sys/dev/pci/drm/radeon/radeon_kms.c

326

if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {

sys/dev/pci/drm/radeon/radeon_kms.c

338

if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {

sys/dev/pci/drm/radeon/radeon_kms.c

446

value = (uint32_t *)&value64;

sys/dev/pci/drm/radeon/radeon_kms.c

474

if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {

sys/dev/pci/drm/radeon/radeon_kms.c

500

value_size = sizeof(uint32_t)*32;

sys/dev/pci/drm/radeon/radeon_kms.c

503

value_size = sizeof(uint32_t)*32;

sys/dev/pci/drm/radeon/radeon_kms.c

512

value_size = sizeof(uint32_t)*16;

sys/dev/pci/drm/radeon/radeon_kms.c

545

value = (uint32_t *)&value64;

sys/dev/pci/drm/radeon/radeon_kms.c

550

value = (uint32_t *)&value64;

sys/dev/pci/drm/radeon/radeon_kms.c

556

value = (uint32_t *)&value64;

sys/dev/pci/drm/radeon/radeon_kms.c

599

if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

302

uint32_t crtc_ext_cntl = 0;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

303

uint32_t mask;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

384

uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

385

uint32_t crtc_pitch, pitch_pixels;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

386

uint32_t tiling_flags;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

388

uint32_t gen_cntl_reg, gen_cntl_val;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

584

uint32_t crtc_h_total_disp;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

585

uint32_t crtc_h_sync_strt_wid;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

586

uint32_t crtc_v_total_disp;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

587

uint32_t crtc_v_sync_strt_wid;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

651

uint32_t crtc2_gen_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

652

uint32_t disp2_merge_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

684

uint32_t crtc_gen_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

685

uint32_t crtc_ext_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

686

uint32_t disp_merge_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

739

uint32_t feedback_div = 0;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

740

uint32_t frac_fb_div = 0;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

741

uint32_t reference_div = 0;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

742

uint32_t post_divider = 0;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

743

uint32_t freq = 0;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

747

uint32_t pll_ref_div = 0;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

748

uint32_t pll_fb_post_div = 0;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

749

uint32_t htotal_cntl = 0;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

854

uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

871

| ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

918

uint32_t pixclks_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_crtc.c

952

| ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1036

uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1037

uint32_t tv_master_cntl = 0;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1154

uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1155

uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1218

uint32_t dac_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1304

uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1305

uint32_t disp_output_cntl, gpiopad_a, tmp;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1375

uint32_t tv_dac_cntl, dac_cntl2;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1376

uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1439

uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1440

uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1441

uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1442

uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1443

uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1529

uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1530

uint32_t gpiopad_a = 0, pixclks_cntl, tmp;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1531

uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

1738

radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

194

uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

516

uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

517

uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

518

uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

585

uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

61

uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

639

uint32_t vclk_ecp_cntl, crtc_ext_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

640

uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

728

uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

782

uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

801

if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

892

uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);

sys/dev/pci/drm/radeon/radeon_legacy_encoders.c

947

uint32_t fp2_gen_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_encoders.h

33

void radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,

sys/dev/pci/drm/radeon/radeon_legacy_encoders.h

34

uint32_t supported_device);

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

281

uint32_t save_pll_test;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

301

uint16_t addr, uint32_t value)

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

305

uint32_t tmp;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

323

static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr)

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

327

uint32_t tmp;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

344

static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr)

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

365

static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr)

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

392

uint32_t tmp;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

400

tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]);

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

406

tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]);

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

535

uint32_t vert_space, flicker_removal, tmp;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

536

uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

537

uint32_t tv_modulator_cntl1, tv_modulator_cntl2;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

538

uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

539

uint32_t tv_pll_cntl, tv_ftotal;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

540

uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

541

uint32_t m, n, p;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

826

uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

827

uint32_t *v_total_disp, uint32_t *v_sync_strt_wid)

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

831

uint32_t tmp;

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

873

uint32_t *htotal_cntl, uint32_t *ppll_ref_div,

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

874

uint32_t *ppll_div_3, uint32_t *pixclks_cntl)

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

893

uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,

sys/dev/pci/drm/radeon/radeon_legacy_tv.c

894

uint32_t *p2pll_div_0, uint32_t *pixclks_cntl)

sys/dev/pci/drm/radeon/radeon_mode.h

127

uint32_t mask_clk_reg;

sys/dev/pci/drm/radeon/radeon_mode.h

128

uint32_t mask_data_reg;

sys/dev/pci/drm/radeon/radeon_mode.h

129

uint32_t a_clk_reg;

sys/dev/pci/drm/radeon/radeon_mode.h

130

uint32_t a_data_reg;

sys/dev/pci/drm/radeon/radeon_mode.h

131

uint32_t en_clk_reg;

sys/dev/pci/drm/radeon/radeon_mode.h

132

uint32_t en_data_reg;

sys/dev/pci/drm/radeon/radeon_mode.h

133

uint32_t y_clk_reg;

sys/dev/pci/drm/radeon/radeon_mode.h

134

uint32_t y_data_reg;

sys/dev/pci/drm/radeon/radeon_mode.h

135

uint32_t mask_clk_mask;

sys/dev/pci/drm/radeon/radeon_mode.h

136

uint32_t mask_data_mask;

sys/dev/pci/drm/radeon/radeon_mode.h

137

uint32_t a_clk_mask;

sys/dev/pci/drm/radeon/radeon_mode.h

138

uint32_t a_data_mask;

sys/dev/pci/drm/radeon/radeon_mode.h

139

uint32_t en_clk_mask;

sys/dev/pci/drm/radeon/radeon_mode.h

140

uint32_t en_data_mask;

sys/dev/pci/drm/radeon/radeon_mode.h

141

uint32_t y_clk_mask;

sys/dev/pci/drm/radeon/radeon_mode.h

142

uint32_t y_data_mask;

sys/dev/pci/drm/radeon/radeon_mode.h

146

uint32_t freq;

sys/dev/pci/drm/radeon/radeon_mode.h

147

uint32_t value;

sys/dev/pci/drm/radeon/radeon_mode.h

171

uint32_t reference_freq;

sys/dev/pci/drm/radeon/radeon_mode.h

174

uint32_t reference_div;

sys/dev/pci/drm/radeon/radeon_mode.h

175

uint32_t post_div;

sys/dev/pci/drm/radeon/radeon_mode.h

178

uint32_t pll_in_min;

sys/dev/pci/drm/radeon/radeon_mode.h

179

uint32_t pll_in_max;

sys/dev/pci/drm/radeon/radeon_mode.h

180

uint32_t pll_out_min;

sys/dev/pci/drm/radeon/radeon_mode.h

181

uint32_t pll_out_max;

sys/dev/pci/drm/radeon/radeon_mode.h

182

uint32_t lcd_pll_out_min;

sys/dev/pci/drm/radeon/radeon_mode.h

183

uint32_t lcd_pll_out_max;

sys/dev/pci/drm/radeon/radeon_mode.h

184

uint32_t best_vco;

sys/dev/pci/drm/radeon/radeon_mode.h

187

uint32_t min_ref_div;

sys/dev/pci/drm/radeon/radeon_mode.h

188

uint32_t max_ref_div;

sys/dev/pci/drm/radeon/radeon_mode.h

189

uint32_t min_post_div;

sys/dev/pci/drm/radeon/radeon_mode.h

190

uint32_t max_post_div;

sys/dev/pci/drm/radeon/radeon_mode.h

191

uint32_t min_feedback_div;

sys/dev/pci/drm/radeon/radeon_mode.h

192

uint32_t max_feedback_div;

sys/dev/pci/drm/radeon/radeon_mode.h

193

uint32_t min_frac_feedback_div;

sys/dev/pci/drm/radeon/radeon_mode.h

194

uint32_t max_frac_feedback_div;

sys/dev/pci/drm/radeon/radeon_mode.h

197

uint32_t flags;

sys/dev/pci/drm/radeon/radeon_mode.h

200

uint32_t id;

sys/dev/pci/drm/radeon/radeon_mode.h

278

uint32_t active_encoders;

sys/dev/pci/drm/radeon/radeon_mode.h

294

uint32_t tv_uv_adr;

sys/dev/pci/drm/radeon/radeon_mode.h

295

uint32_t timing_cntl;

sys/dev/pci/drm/radeon/radeon_mode.h

296

uint32_t hrestart;

sys/dev/pci/drm/radeon/radeon_mode.h

297

uint32_t vrestart;

sys/dev/pci/drm/radeon/radeon_mode.h

298

uint32_t frestart;

sys/dev/pci/drm/radeon/radeon_mode.h

328

uint32_t crtc_offset;

sys/dev/pci/drm/radeon/radeon_mode.h

339

uint32_t legacy_display_base_addr;

sys/dev/pci/drm/radeon/radeon_mode.h

372

uint32_t ps2_pdac_adj;

sys/dev/pci/drm/radeon/radeon_mode.h

385

uint32_t lvds_gen_cntl;

sys/dev/pci/drm/radeon/radeon_mode.h

395

uint32_t ps2_tvdac_adj;

sys/dev/pci/drm/radeon/radeon_mode.h

396

uint32_t ntsc_tvdac_adj;

sys/dev/pci/drm/radeon/radeon_mode.h

397

uint32_t pal_tvdac_adj;

sys/dev/pci/drm/radeon/radeon_mode.h

427

uint32_t lcd_misc;

sys/dev/pci/drm/radeon/radeon_mode.h

429

uint32_t lcd_ss_id;

sys/dev/pci/drm/radeon/radeon_mode.h

446

uint32_t encoder_enum;

sys/dev/pci/drm/radeon/radeon_mode.h

447

uint32_t encoder_id;

sys/dev/pci/drm/radeon/radeon_mode.h

448

uint32_t devices;

sys/dev/pci/drm/radeon/radeon_mode.h

449

uint32_t active_device;

sys/dev/pci/drm/radeon/radeon_mode.h

450

uint32_t flags;

sys/dev/pci/drm/radeon/radeon_mode.h

451

uint32_t pixel_clock;

sys/dev/pci/drm/radeon/radeon_mode.h

454

uint32_t underscan_hborder;

sys/dev/pci/drm/radeon/radeon_mode.h

455

uint32_t underscan_vborder;

sys/dev/pci/drm/radeon/radeon_mode.h

464

uint32_t offset;

sys/dev/pci/drm/radeon/radeon_mode.h

468

uint32_t igp_lane_info;

sys/dev/pci/drm/radeon/radeon_mode.h

520

uint32_t connector_id;

sys/dev/pci/drm/radeon/radeon_mode.h

521

uint32_t devices;

sys/dev/pci/drm/radeon/radeon_mode.h

659

uint32_t connector_id,

sys/dev/pci/drm/radeon/radeon_mode.h

660

uint32_t supported_device,

sys/dev/pci/drm/radeon/radeon_mode.h

663

uint32_t igp_lane_info,

sys/dev/pci/drm/radeon/radeon_mode.h

669

uint32_t connector_id,

sys/dev/pci/drm/radeon/radeon_mode.h

670

uint32_t supported_device,

sys/dev/pci/drm/radeon/radeon_mode.h

675

extern uint32_t

sys/dev/pci/drm/radeon/radeon_mode.h

676

radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,

sys/dev/pci/drm/radeon/radeon_mode.h

776

uint32_t *dot_clock_p,

sys/dev/pci/drm/radeon/radeon_mode.h

777

uint32_t *fb_div_p,

sys/dev/pci/drm/radeon/radeon_mode.h

778

uint32_t *frac_fb_div_p,

sys/dev/pci/drm/radeon/radeon_mode.h

779

uint32_t *ref_div_p,

sys/dev/pci/drm/radeon/radeon_mode.h

780

uint32_t *post_div_p);

sys/dev/pci/drm/radeon/radeon_mode.h

829

uint32_t handle,

sys/dev/pci/drm/radeon/radeon_mode.h

830

uint32_t width,

sys/dev/pci/drm/radeon/radeon_mode.h

831

uint32_t height,

sys/dev/pci/drm/radeon/radeon_mode.h

923

uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,

sys/dev/pci/drm/radeon/radeon_mode.h

924

uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);

sys/dev/pci/drm/radeon/radeon_mode.h

926

uint32_t *htotal_cntl, uint32_t *ppll_ref_div,

sys/dev/pci/drm/radeon/radeon_mode.h

927

uint32_t *ppll_div_3, uint32_t *pixclks_cntl);

sys/dev/pci/drm/radeon/radeon_mode.h

929

uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,

sys/dev/pci/drm/radeon/radeon_mode.h

930

uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);

sys/dev/pci/drm/radeon/radeon_object.c

624

uint32_t tiling_flags, uint32_t pitch)

sys/dev/pci/drm/radeon/radeon_object.c

684

uint32_t *tiling_flags,

sys/dev/pci/drm/radeon/radeon_object.c

685

uint32_t *pitch)

sys/dev/pci/drm/radeon/radeon_ring.c

256

uint32_t rptr = radeon_ring_get_rptr(rdev, ring);

sys/dev/pci/drm/radeon/radeon_ring.c

286

uint32_t **data)

sys/dev/pci/drm/radeon/radeon_ring.c

325

*data = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);

sys/dev/pci/drm/radeon/radeon_ring.c

350

unsigned size, uint32_t *data)

sys/dev/pci/drm/radeon/radeon_ring.c

472

uint32_t rptr, wptr, rptr_next;

sys/dev/pci/drm/radeon/radeon_ring.c

523

static const char *radeon_debugfs_ring_idx_to_name(uint32_t ridx)

sys/dev/pci/drm/radeon/radeon_ring.c

85

uint32_t rptr = radeon_ring_get_rptr(rdev, ring);

sys/dev/pci/drm/radeon/radeon_test.c

266

uint32_t handle = ring->idx ^ 0xdeafbeef;

sys/dev/pci/drm/radeon/radeon_trace.h

85

uint32_t incr, uint32_t flags),

sys/dev/pci/drm/radeon/radeon_ttm.c

326

uint32_t userflags;

sys/dev/pci/drm/radeon/radeon_ttm.c

441

uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |

sys/dev/pci/drm/radeon/radeon_ttm.c

496

uint32_t page_flags)

sys/dev/pci/drm/radeon/radeon_ttm.c

590

uint32_t flags)

sys/dev/pci/drm/radeon/radeon_ttm.c

844

uint32_t value;

sys/dev/pci/drm/radeon/radeon_ttm.c

850

WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);

sys/dev/pci/drm/radeon/radeon_ttm.c

856

r = put_user(value, (uint32_t __user *)buf);

sys/dev/pci/drm/radeon/radeon_ucode.h

157

uint32_t size_bytes; /* size of the entire header+image(s) in bytes */

sys/dev/pci/drm/radeon/radeon_ucode.h

158

uint32_t header_size_bytes; /* size of just the header in bytes */

sys/dev/pci/drm/radeon/radeon_ucode.h

163

uint32_t ucode_version;

sys/dev/pci/drm/radeon/radeon_ucode.h

164

uint32_t ucode_size_bytes; /* size of ucode in bytes */

sys/dev/pci/drm/radeon/radeon_ucode.h

165

uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */

sys/dev/pci/drm/radeon/radeon_ucode.h

166

uint32_t crc32; /* crc32 checksum of the payload */

sys/dev/pci/drm/radeon/radeon_ucode.h

172

uint32_t io_debug_size_bytes; /* size of debug array in dwords */

sys/dev/pci/drm/radeon/radeon_ucode.h

173

uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */

sys/dev/pci/drm/radeon/radeon_ucode.h

179

uint32_t ucode_start_addr;

sys/dev/pci/drm/radeon/radeon_ucode.h

185

uint32_t ucode_feature_version;

sys/dev/pci/drm/radeon/radeon_ucode.h

186

uint32_t jt_offset; /* jt location */

sys/dev/pci/drm/radeon/radeon_ucode.h

187

uint32_t jt_size; /* size of jt */

sys/dev/pci/drm/radeon/radeon_ucode.h

193

uint32_t ucode_feature_version;

sys/dev/pci/drm/radeon/radeon_ucode.h

194

uint32_t save_and_restore_offset;

sys/dev/pci/drm/radeon/radeon_ucode.h

195

uint32_t clear_state_descriptor_offset;

sys/dev/pci/drm/radeon/radeon_ucode.h

196

uint32_t avail_scratch_ram_locations;

sys/dev/pci/drm/radeon/radeon_ucode.h

197

uint32_t master_pkt_description_offset;

sys/dev/pci/drm/radeon/radeon_ucode.h

203

uint32_t ucode_feature_version;

sys/dev/pci/drm/radeon/radeon_ucode.h

204

uint32_t ucode_change_version;

sys/dev/pci/drm/radeon/radeon_ucode.h

205

uint32_t jt_offset; /* jt location */

sys/dev/pci/drm/radeon/radeon_ucode.h

206

uint32_t jt_size; /* size of jt */

sys/dev/pci/drm/radeon/radeon_uvd.c

1026

uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;

sys/dev/pci/drm/radeon/radeon_uvd.c

259

uint32_t handle = atomic_read(&rdev->uvd.handles[i]);

sys/dev/pci/drm/radeon/radeon_uvd.c

305

uint32_t allowed_domains)

sys/dev/pci/drm/radeon/radeon_uvd.c

333

uint32_t handle = atomic_read(&rdev->uvd.handles[i]);

sys/dev/pci/drm/radeon/radeon_uvd.c

355

static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])

sys/dev/pci/drm/radeon/radeon_uvd.c

767

uint32_t handle, struct radeon_fence **fence)

sys/dev/pci/drm/radeon/radeon_uvd.c

773

uint32_t __iomem *msg = (void __iomem *)(rdev->uvd.cpu_addr + offs);

sys/dev/pci/drm/radeon/radeon_uvd.c

803

uint32_t handle, struct radeon_fence **fence)

sys/dev/pci/drm/radeon/radeon_uvd.c

809

uint32_t __iomem *msg = (void __iomem *)(rdev->uvd.cpu_addr + offs);

sys/dev/pci/drm/radeon/radeon_vce.c

349

uint32_t handle = atomic_read(&rdev->vce.handles[i]);

sys/dev/pci/drm/radeon/radeon_vce.c

376

uint32_t handle, struct radeon_fence **fence)

sys/dev/pci/drm/radeon/radeon_vce.c

443

uint32_t handle, struct radeon_fence **fence)

sys/dev/pci/drm/radeon/radeon_vce.c

549

uint32_t handle, bool *allocated)

sys/dev/pci/drm/radeon/radeon_vce.c

590

uint32_t tmp = 0, handle = 0;

sys/dev/pci/drm/radeon/radeon_vce.c

591

uint32_t *size = &tmp;

sys/dev/pci/drm/radeon/radeon_vce.c

595

uint32_t len = radeon_get_ib_value(p, p->idx);

sys/dev/pci/drm/radeon/radeon_vce.c

596

uint32_t cmd = radeon_get_ib_value(p, p->idx + 1);

sys/dev/pci/drm/radeon/radeon_vce.c

787

uint32_t rptr = vce_v1_0_get_rptr(rdev, ring);

sys/dev/pci/drm/radeon/radeon_vm.c

362

uint32_t incr, uint32_t flags)

sys/dev/pci/drm/radeon/radeon_vm.c

448

uint32_t flags)

sys/dev/pci/drm/radeon/radeon_vm.c

612

static uint32_t radeon_vm_page_flags(uint32_t flags)

sys/dev/pci/drm/radeon/radeon_vm.c

614

uint32_t hw_flags = 0;

sys/dev/pci/drm/radeon/radeon_vm.c

643

uint32_t incr = RADEON_VM_PTE_COUNT * 8;

sys/dev/pci/drm/radeon/radeon_vm.c

732

uint64_t addr, uint32_t flags)

sys/dev/pci/drm/radeon/radeon_vm.c

816

uint64_t dst, uint32_t flags)

sys/dev/pci/drm/radeon/radeon_vm.c

917

uint32_t flags;

sys/dev/pci/drm/radeon/rs400.c

113

uint32_t size_reg;

sys/dev/pci/drm/radeon/rs400.c

114

uint32_t tmp;

sys/dev/pci/drm/radeon/rs400.c

200

uint32_t tmp;

sys/dev/pci/drm/radeon/rs400.c

219

uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags)

sys/dev/pci/drm/radeon/rs400.c

221

uint32_t entry;

sys/dev/pci/drm/radeon/rs400.c

244

uint32_t tmp;

sys/dev/pci/drm/radeon/rs400.c

298

uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)

sys/dev/pci/drm/radeon/rs400.c

301

uint32_t r;

sys/dev/pci/drm/radeon/rs400.c

311

void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/pci/drm/radeon/rs400.c

326

uint32_t tmp;

sys/dev/pci/drm/radeon/rs400.c

67

uint32_t tmp;

sys/dev/pci/drm/radeon/rs600.c

529

uint32_t tmp;

sys/dev/pci/drm/radeon/rs600.c

644

uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags)

sys/dev/pci/drm/radeon/rs600.c

668

uint32_t tmp = 0;

sys/dev/pci/drm/radeon/rs600.c

669

uint32_t mode_int = 0;

sys/dev/pci/drm/radeon/rs600.c

721

uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);

sys/dev/pci/drm/radeon/rs600.c

722

uint32_t irq_mask = S_000044_SW_INT(1);

sys/dev/pci/drm/radeon/rs600.c

930

uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)

sys/dev/pci/drm/radeon/rs600.c

943

void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/pci/drm/radeon/rs690.c

153

uint32_t h_addr, l_addr;

sys/dev/pci/drm/radeon/rs690.c

40

uint32_t tmp;

sys/dev/pci/drm/radeon/rs690.c

651

uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)

sys/dev/pci/drm/radeon/rs690.c

654

uint32_t r;

sys/dev/pci/drm/radeon/rs690.c

664

void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/pci/drm/radeon/rv515.c

122

uint32_t tmp;

sys/dev/pci/drm/radeon/rv515.c

1246

uint32_t tmp;

sys/dev/pci/drm/radeon/rv515.c

166

uint32_t tmp;

sys/dev/pci/drm/radeon/rv515.c

196

uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)

sys/dev/pci/drm/radeon/rv515.c

199

uint32_t r;

sys/dev/pci/drm/radeon/rv515.c

210

void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)

sys/dev/pci/drm/radeon/rv515.c

225

uint32_t tmp;

sys/dev/pci/drm/radeon/rv515.c

241

uint32_t tmp;

sys/dev/pci/drm/radeon/rv770_smc.h

100

uint32_t aT;

sys/dev/pci/drm/radeon/rv770_smc.h

101

uint32_t bSP;

sys/dev/pci/drm/radeon/rv770_smc.h

140

uint32_t lowMask[RV770_SMC_VOLTAGEMASK_MAX];

sys/dev/pci/drm/radeon/rv770_smc.h

153

uint32_t lowSMIO[MAX_NO_VREG_STEPS];

sys/dev/pci/drm/radeon/rv770_smc.h

35

uint32_t vCG_SPLL_FUNC_CNTL;

sys/dev/pci/drm/radeon/rv770_smc.h

36

uint32_t vCG_SPLL_FUNC_CNTL_2;

sys/dev/pci/drm/radeon/rv770_smc.h

37

uint32_t vCG_SPLL_FUNC_CNTL_3;

sys/dev/pci/drm/radeon/rv770_smc.h

38

uint32_t vCG_SPLL_SPREAD_SPECTRUM;

sys/dev/pci/drm/radeon/rv770_smc.h

39

uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;

sys/dev/pci/drm/radeon/rv770_smc.h

40

uint32_t sclk_value;

sys/dev/pci/drm/radeon/rv770_smc.h

46

uint32_t vMPLL_AD_FUNC_CNTL;

sys/dev/pci/drm/radeon/rv770_smc.h

47

uint32_t vMPLL_AD_FUNC_CNTL_2;

sys/dev/pci/drm/radeon/rv770_smc.h

48

uint32_t vMPLL_DQ_FUNC_CNTL;

sys/dev/pci/drm/radeon/rv770_smc.h

49

uint32_t vMPLL_DQ_FUNC_CNTL_2;

sys/dev/pci/drm/radeon/rv770_smc.h

50

uint32_t vMCLK_PWRMGT_CNTL;

sys/dev/pci/drm/radeon/rv770_smc.h

51

uint32_t vDLL_CNTL;

sys/dev/pci/drm/radeon/rv770_smc.h

52

uint32_t vMPLL_SS;

sys/dev/pci/drm/radeon/rv770_smc.h

53

uint32_t vMPLL_SS2;

sys/dev/pci/drm/radeon/rv770_smc.h

54

uint32_t mclk_value;

sys/dev/pci/drm/radeon/rv770_smc.h

61

uint32_t vMCLK_PWRMGT_CNTL;

sys/dev/pci/drm/radeon/rv770_smc.h

62

uint32_t vDLL_CNTL;

sys/dev/pci/drm/radeon/rv770_smc.h

63

uint32_t vMPLL_FUNC_CNTL;

sys/dev/pci/drm/radeon/rv770_smc.h

64

uint32_t vMPLL_FUNC_CNTL2;

sys/dev/pci/drm/radeon/rv770_smc.h

65

uint32_t vMPLL_FUNC_CNTL3;

sys/dev/pci/drm/radeon/rv770_smc.h

66

uint32_t vMPLL_SS;

sys/dev/pci/drm/radeon/rv770_smc.h

67

uint32_t vMPLL_SS2;

sys/dev/pci/drm/radeon/rv770_smc.h

68

uint32_t mclk_value;

sys/dev/pci/drm/radeon/si.c

4358

uint32_t reg;

sys/dev/pci/drm/radeon/si.c

7445

uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;

sys/dev/pci/drm/radeon/si_dma.c

108

uint32_t incr, uint32_t flags)

sys/dev/pci/drm/radeon/si_dma.c

155

uint32_t incr, uint32_t flags)

sys/dev/pci/drm/radeon/sislands_smc.h

103

uint32_t vCG_SPLL_FUNC_CNTL;

sys/dev/pci/drm/radeon/sislands_smc.h

104

uint32_t vCG_SPLL_FUNC_CNTL_2;

sys/dev/pci/drm/radeon/sislands_smc.h

105

uint32_t vCG_SPLL_FUNC_CNTL_3;

sys/dev/pci/drm/radeon/sislands_smc.h

106

uint32_t vCG_SPLL_FUNC_CNTL_4;

sys/dev/pci/drm/radeon/sislands_smc.h

107

uint32_t vCG_SPLL_SPREAD_SPECTRUM;

sys/dev/pci/drm/radeon/sislands_smc.h

108

uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;

sys/dev/pci/drm/radeon/sislands_smc.h

109

uint32_t sclk_value;

sys/dev/pci/drm/radeon/sislands_smc.h

115

uint32_t vMPLL_FUNC_CNTL;

sys/dev/pci/drm/radeon/sislands_smc.h

116

uint32_t vMPLL_FUNC_CNTL_1;

sys/dev/pci/drm/radeon/sislands_smc.h

117

uint32_t vMPLL_FUNC_CNTL_2;

sys/dev/pci/drm/radeon/sislands_smc.h

118

uint32_t vMPLL_AD_FUNC_CNTL;

sys/dev/pci/drm/radeon/sislands_smc.h

119

uint32_t vMPLL_DQ_FUNC_CNTL;

sys/dev/pci/drm/radeon/sislands_smc.h

120

uint32_t vMCLK_PWRMGT_CNTL;

sys/dev/pci/drm/radeon/sislands_smc.h

121

uint32_t vDLL_CNTL;

sys/dev/pci/drm/radeon/sislands_smc.h

122

uint32_t vMPLL_SS;

sys/dev/pci/drm/radeon/sislands_smc.h

123

uint32_t vMPLL_SS2;

sys/dev/pci/drm/radeon/sislands_smc.h

124

uint32_t mclk_value;

sys/dev/pci/drm/radeon/sislands_smc.h

146

uint32_t aT;

sys/dev/pci/drm/radeon/sislands_smc.h

147

uint32_t bSP;

sys/dev/pci/drm/radeon/sislands_smc.h

158

uint32_t SQPowerThrottle;

sys/dev/pci/drm/radeon/sislands_smc.h

159

uint32_t SQPowerThrottle_2;

sys/dev/pci/drm/radeon/sislands_smc.h

160

uint32_t MaxPoweredUpCU;

sys/dev/pci/drm/radeon/sislands_smc.h

163

uint32_t reserved[2];

sys/dev/pci/drm/radeon/sislands_smc.h

203

uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX];

sys/dev/pci/drm/radeon/sislands_smc.h

215

uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS];

sys/dev/pci/drm/radeon/sislands_smc.h

265

uint32_t refresh_period;

sys/dev/pci/drm/radeon/sislands_smc.h

281

uint32_t lkge_lut_V0;

sys/dev/pci/drm/radeon/sislands_smc.h

282

uint32_t lkge_lut_Vstep;

sys/dev/pci/drm/radeon/sislands_smc.h

283

uint32_t WinTime;

sys/dev/pci/drm/radeon/sislands_smc.h

284

uint32_t R_LL;

sys/dev/pci/drm/radeon/sislands_smc.h

285

uint32_t calculation_repeats;

sys/dev/pci/drm/radeon/sislands_smc.h

286

uint32_t l2numWin_TDP;

sys/dev/pci/drm/radeon/sislands_smc.h

287

uint32_t dc_cac;

sys/dev/pci/drm/radeon/sislands_smc.h

292

uint32_t lkge_lut_T0;

sys/dev/pci/drm/radeon/sislands_smc.h

293

uint32_t lkge_lut_Tstep;

sys/dev/pci/drm/radeon/sislands_smc.h

309

uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/radeon/sislands_smc.h

324

uint32_t mc_arb_dram_timing;

sys/dev/pci/drm/radeon/sislands_smc.h

325

uint32_t mc_arb_dram_timing2;

sys/dev/pci/drm/radeon/sislands_smc.h

342

uint32_t freq[256];

sys/dev/pci/drm/radeon/sislands_smc.h

343

uint32_t ss[256];

sys/dev/pci/drm/radeon/sislands_smc.h

362

uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];

sys/dev/pci/drm/radeon/sislands_smc.h

363

uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];

sys/dev/pci/drm/radeon/sislands_smc.h

364

uint32_t K;

sys/dev/pci/drm/radeon/sislands_smc.h

365

uint32_t T0;

sys/dev/pci/drm/radeon/sislands_smc.h

366

uint32_t MaxT;

sys/dev/pci/drm/radeon/sislands_smc.h

372

uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

sys/dev/pci/drm/radeon/sislands_smc.h

373

uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

sys/dev/pci/drm/radeon/sislands_smc.h

374

uint32_t Tthreshold;

sys/dev/pci/drm/radeon/sislands_smc.h

52

uint32_t dpm2Flags;

sys/dev/pci/drm/radeon/sislands_smc.h

65

uint32_t SwitchDownCounter;

sys/dev/pci/drm/radeon/sislands_smc.h

66

uint32_t SysScalingFactor;

sys/dev/pci/drm/radeon/sislands_smc.h

73

uint32_t TDPLimit;

sys/dev/pci/drm/radeon/sislands_smc.h

74

uint32_t NearTDPLimit;

sys/dev/pci/drm/radeon/sislands_smc.h

75

uint32_t SafePowerLimit;

sys/dev/pci/drm/radeon/sislands_smc.h

76

uint32_t PowerBoostLimit;

sys/dev/pci/drm/radeon/sislands_smc.h

77

uint32_t MinLimitDelta;

sys/dev/pci/drm/radeon/sislands_smc.h

83

uint32_t EstimatedDGPU_T;

sys/dev/pci/drm/radeon/sislands_smc.h

84

uint32_t EstimatedDGPU_P;

sys/dev/pci/drm/radeon/sislands_smc.h

85

uint32_t EstimatedAPU_T;

sys/dev/pci/drm/radeon/sislands_smc.h

86

uint32_t EstimatedAPU_P;

sys/dev/pci/drm/radeon/sislands_smc.h

93

uint32_t NearTDPLimitTherm;

sys/dev/pci/drm/radeon/sislands_smc.h

94

uint32_t NearTDPLimitPAPM;

sys/dev/pci/drm/radeon/sislands_smc.h

95

uint32_t PlatformPowerLimit;

sys/dev/pci/drm/radeon/sislands_smc.h

96

uint32_t dGPU_T_Limit;

sys/dev/pci/drm/radeon/sislands_smc.h

97

uint32_t dGPU_T_Warning;

sys/dev/pci/drm/radeon/sislands_smc.h

98

uint32_t dGPU_T_Hysteresis;

sys/dev/pci/drm/radeon/smu7.h

120

uint32_t Digest[5];

sys/dev/pci/drm/radeon/smu7.h

121

uint32_t Version;

sys/dev/pci/drm/radeon/smu7.h

122

uint32_t HeaderSize;

sys/dev/pci/drm/radeon/smu7.h

123

uint32_t Flags;

sys/dev/pci/drm/radeon/smu7.h

124

uint32_t EntryPoint;

sys/dev/pci/drm/radeon/smu7.h

125

uint32_t CodeSize;

sys/dev/pci/drm/radeon/smu7.h

126

uint32_t ImageSize;

sys/dev/pci/drm/radeon/smu7.h

128

uint32_t Rtos;

sys/dev/pci/drm/radeon/smu7.h

129

uint32_t SoftRegisters;

sys/dev/pci/drm/radeon/smu7.h

130

uint32_t DpmTable;

sys/dev/pci/drm/radeon/smu7.h

131

uint32_t FanTable;

sys/dev/pci/drm/radeon/smu7.h

132

uint32_t CacConfigTable;

sys/dev/pci/drm/radeon/smu7.h

133

uint32_t CacStatusTable;

sys/dev/pci/drm/radeon/smu7.h

135

uint32_t mcRegisterTable;

sys/dev/pci/drm/radeon/smu7.h

137

uint32_t mcArbDramTimingTable;

sys/dev/pci/drm/radeon/smu7.h

139

uint32_t PmFuseTable;

sys/dev/pci/drm/radeon/smu7.h

140

uint32_t Globals;

sys/dev/pci/drm/radeon/smu7.h

141

uint32_t Reserved[42];

sys/dev/pci/drm/radeon/smu7.h

142

uint32_t Signature;

sys/dev/pci/drm/radeon/smu7.h

86

uint32_t Ki;

sys/dev/pci/drm/radeon/smu7.h

89

uint32_t StatePrecision;

sys/dev/pci/drm/radeon/smu7.h

90

uint32_t LfPrecision;

sys/dev/pci/drm/radeon/smu7.h

91

uint32_t LfOffset;

sys/dev/pci/drm/radeon/smu7.h

92

uint32_t MaxState;

sys/dev/pci/drm/radeon/smu7.h

93

uint32_t MaxLfFraction;

sys/dev/pci/drm/radeon/smu7.h

94

uint32_t StateShift;

sys/dev/pci/drm/radeon/smu7_discrete.h

102

uint32_t Flags;

sys/dev/pci/drm/radeon/smu7_discrete.h

103

uint32_t MinVddc;

sys/dev/pci/drm/radeon/smu7_discrete.h

104

uint32_t MinVddcPhases;

sys/dev/pci/drm/radeon/smu7_discrete.h

106

uint32_t SclkFrequency;

sys/dev/pci/drm/radeon/smu7_discrete.h

111

uint32_t CgSpllFuncCntl3;

sys/dev/pci/drm/radeon/smu7_discrete.h

112

uint32_t CgSpllFuncCntl4;

sys/dev/pci/drm/radeon/smu7_discrete.h

113

uint32_t SpllSpreadSpectrum;

sys/dev/pci/drm/radeon/smu7_discrete.h

114

uint32_t SpllSpreadSpectrum2;

sys/dev/pci/drm/radeon/smu7_discrete.h

115

uint32_t CcPwrDynRm;

sys/dev/pci/drm/radeon/smu7_discrete.h

116

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/radeon/smu7_discrete.h

132

uint32_t Flags;

sys/dev/pci/drm/radeon/smu7_discrete.h

133

uint32_t MinVddc;

sys/dev/pci/drm/radeon/smu7_discrete.h

134

uint32_t MinVddcPhases;

sys/dev/pci/drm/radeon/smu7_discrete.h

135

uint32_t SclkFrequency;

sys/dev/pci/drm/radeon/smu7_discrete.h

140

uint32_t CgSpllFuncCntl;

sys/dev/pci/drm/radeon/smu7_discrete.h

141

uint32_t CgSpllFuncCntl2;

sys/dev/pci/drm/radeon/smu7_discrete.h

142

uint32_t CgSpllFuncCntl3;

sys/dev/pci/drm/radeon/smu7_discrete.h

143

uint32_t CgSpllFuncCntl4;

sys/dev/pci/drm/radeon/smu7_discrete.h

144

uint32_t SpllSpreadSpectrum;

sys/dev/pci/drm/radeon/smu7_discrete.h

145

uint32_t SpllSpreadSpectrum2;

sys/dev/pci/drm/radeon/smu7_discrete.h

146

uint32_t CcPwrDynRm;

sys/dev/pci/drm/radeon/smu7_discrete.h

147

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/radeon/smu7_discrete.h

153

uint32_t CcPwrDynRm;

sys/dev/pci/drm/radeon/smu7_discrete.h

154

uint32_t CcPwrDynRm1;

sys/dev/pci/drm/radeon/smu7_discrete.h

158

uint32_t Reserved;

sys/dev/pci/drm/radeon/smu7_discrete.h

164

uint32_t MinVddc;

sys/dev/pci/drm/radeon/smu7_discrete.h

165

uint32_t MinVddcPhases;

sys/dev/pci/drm/radeon/smu7_discrete.h

166

uint32_t MinVddci;

sys/dev/pci/drm/radeon/smu7_discrete.h

167

uint32_t MinMvdd;

sys/dev/pci/drm/radeon/smu7_discrete.h

169

uint32_t MclkFrequency;

sys/dev/pci/drm/radeon/smu7_discrete.h

190

uint32_t MpllFuncCntl;

sys/dev/pci/drm/radeon/smu7_discrete.h

191

uint32_t MpllFuncCntl_1;

sys/dev/pci/drm/radeon/smu7_discrete.h

192

uint32_t MpllFuncCntl_2;

sys/dev/pci/drm/radeon/smu7_discrete.h

193

uint32_t MpllAdFuncCntl;

sys/dev/pci/drm/radeon/smu7_discrete.h

194

uint32_t MpllDqFuncCntl;

sys/dev/pci/drm/radeon/smu7_discrete.h

195

uint32_t MclkPwrmgtCntl;

sys/dev/pci/drm/radeon/smu7_discrete.h

196

uint32_t DllCntl;

sys/dev/pci/drm/radeon/smu7_discrete.h

197

uint32_t MpllSs1;

sys/dev/pci/drm/radeon/smu7_discrete.h

198

uint32_t MpllSs2;

sys/dev/pci/drm/radeon/smu7_discrete.h

208

uint32_t DownT;

sys/dev/pci/drm/radeon/smu7_discrete.h

209

uint32_t UpT;

sys/dev/pci/drm/radeon/smu7_discrete.h

210

uint32_t Reserved;

sys/dev/pci/drm/radeon/smu7_discrete.h

217

uint32_t McArbDramTiming;

sys/dev/pci/drm/radeon/smu7_discrete.h

218

uint32_t McArbDramTiming2;

sys/dev/pci/drm/radeon/smu7_discrete.h

232

uint32_t VclkFrequency;

sys/dev/pci/drm/radeon/smu7_discrete.h

233

uint32_t DclkFrequency;

sys/dev/pci/drm/radeon/smu7_discrete.h

244

uint32_t Frequency;

sys/dev/pci/drm/radeon/smu7_discrete.h

253

uint32_t SclkFrequency;

sys/dev/pci/drm/radeon/smu7_discrete.h

254

uint32_t MclkFrequency;

sys/dev/pci/drm/radeon/smu7_discrete.h

255

uint32_t VclkFrequency;

sys/dev/pci/drm/radeon/smu7_discrete.h

256

uint32_t DclkFrequency;

sys/dev/pci/drm/radeon/smu7_discrete.h

257

uint32_t SamclkFrequency;

sys/dev/pci/drm/radeon/smu7_discrete.h

258

uint32_t AclkFrequency;

sys/dev/pci/drm/radeon/smu7_discrete.h

259

uint32_t EclkFrequency;

sys/dev/pci/drm/radeon/smu7_discrete.h

281

uint32_t SystemFlags;

sys/dev/pci/drm/radeon/smu7_discrete.h

284

uint32_t SmioMaskVddcVid;

sys/dev/pci/drm/radeon/smu7_discrete.h

285

uint32_t SmioMaskVddcPhase;

sys/dev/pci/drm/radeon/smu7_discrete.h

286

uint32_t SmioMaskVddciVid;

sys/dev/pci/drm/radeon/smu7_discrete.h

287

uint32_t SmioMaskMvddVid;

sys/dev/pci/drm/radeon/smu7_discrete.h

289

uint32_t VddcLevelCount;

sys/dev/pci/drm/radeon/smu7_discrete.h

290

uint32_t VddciLevelCount;

sys/dev/pci/drm/radeon/smu7_discrete.h

291

uint32_t MvddLevelCount;

sys/dev/pci/drm/radeon/smu7_discrete.h

306

uint32_t Reserved[5];

sys/dev/pci/drm/radeon/smu7_discrete.h

320

uint32_t SclkStepSize;

sys/dev/pci/drm/radeon/smu7_discrete.h

321

uint32_t Smio [SMU7_MAX_ENTRIES_SMIO];

sys/dev/pci/drm/radeon/smu7_discrete.h

386

uint32_t BAPM_TEMP_GRADIENT;

sys/dev/pci/drm/radeon/smu7_discrete.h

388

uint32_t LowSclkInterruptT;

sys/dev/pci/drm/radeon/smu7_discrete.h

39

uint32_t RefClockFrequency;

sys/dev/pci/drm/radeon/smu7_discrete.h

40

uint32_t PmTimerP;

sys/dev/pci/drm/radeon/smu7_discrete.h

404

uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/pci/drm/radeon/smu7_discrete.h

41

uint32_t FeatureEnables;

sys/dev/pci/drm/radeon/smu7_discrete.h

42

uint32_t PreVBlankGap;

sys/dev/pci/drm/radeon/smu7_discrete.h

43

uint32_t VBlankTimeout;

sys/dev/pci/drm/radeon/smu7_discrete.h

433

uint32_t RefreshPeriod;

sys/dev/pci/drm/radeon/smu7_discrete.h

44

uint32_t TrainTimeGap;

sys/dev/pci/drm/radeon/smu7_discrete.h

46

uint32_t MvddSwitchTime;

sys/dev/pci/drm/radeon/smu7_discrete.h

47

uint32_t LongestAcpiTrainTime;

sys/dev/pci/drm/radeon/smu7_discrete.h

48

uint32_t AcpiDelay;

sys/dev/pci/drm/radeon/smu7_discrete.h

49

uint32_t G5TrainTime;

sys/dev/pci/drm/radeon/smu7_discrete.h

50

uint32_t DelayMpllPwron;

sys/dev/pci/drm/radeon/smu7_discrete.h

51

uint32_t VoltageChangeTimeout;

sys/dev/pci/drm/radeon/smu7_discrete.h

52

uint32_t HandshakeDisables;

sys/dev/pci/drm/radeon/smu7_discrete.h

64

uint32_t AverageGraphicsA;

sys/dev/pci/drm/radeon/smu7_discrete.h

65

uint32_t AverageMemoryA;

sys/dev/pci/drm/radeon/smu7_discrete.h

66

uint32_t AverageGioA;

sys/dev/pci/drm/radeon/smu7_discrete.h

78

uint32_t DRAM_LOG_ADDR_H;

sys/dev/pci/drm/radeon/smu7_discrete.h

79

uint32_t DRAM_LOG_ADDR_L;

sys/dev/pci/drm/radeon/smu7_discrete.h

80

uint32_t DRAM_LOG_PHY_ADDR_H;

sys/dev/pci/drm/radeon/smu7_discrete.h

81

uint32_t DRAM_LOG_PHY_ADDR_L;

sys/dev/pci/drm/radeon/smu7_discrete.h

82

uint32_t DRAM_LOG_BUFF_SIZE;

sys/dev/pci/drm/radeon/smu7_discrete.h

83

uint32_t UlvEnterC;

sys/dev/pci/drm/radeon/smu7_discrete.h

84

uint32_t UlvTime;

sys/dev/pci/drm/radeon/smu7_discrete.h

85

uint32_t Reserved[3];

sys/dev/pci/drm/radeon/smu7_fusion.h

107

uint32_t reserved;

sys/dev/pci/drm/radeon/smu7_fusion.h

118

uint32_t MinVddNb;

sys/dev/pci/drm/radeon/smu7_fusion.h

124

uint32_t LclkFrequency;

sys/dev/pci/drm/radeon/smu7_fusion.h

138

uint32_t VclkFrequency;

sys/dev/pci/drm/radeon/smu7_fusion.h

139

uint32_t DclkFrequency;

sys/dev/pci/drm/radeon/smu7_fusion.h

155

uint32_t Frequency;

sys/dev/pci/drm/radeon/smu7_fusion.h

160

uint32_t Reserved;

sys/dev/pci/drm/radeon/smu7_fusion.h

165

uint32_t Flags;

sys/dev/pci/drm/radeon/smu7_fusion.h

166

uint32_t MinVddNb;

sys/dev/pci/drm/radeon/smu7_fusion.h

167

uint32_t SclkFrequency;

sys/dev/pci/drm/radeon/smu7_fusion.h

194

uint32_t SclkFrequency;

sys/dev/pci/drm/radeon/smu7_fusion.h

195

uint32_t LclkFrequency;

sys/dev/pci/drm/radeon/smu7_fusion.h

196

uint32_t VclkFrequency;

sys/dev/pci/drm/radeon/smu7_fusion.h

197

uint32_t DclkFrequency;

sys/dev/pci/drm/radeon/smu7_fusion.h

198

uint32_t SamclkFrequency;

sys/dev/pci/drm/radeon/smu7_fusion.h

199

uint32_t AclkFrequency;

sys/dev/pci/drm/radeon/smu7_fusion.h

200

uint32_t EclkFrequency;

sys/dev/pci/drm/radeon/smu7_fusion.h

210

uint32_t SystemFlags;

sys/dev/pci/drm/radeon/smu7_fusion.h

249

uint32_t DisplayCac;

sys/dev/pci/drm/radeon/smu7_fusion.h

250

uint32_t LowSclkInterruptT;

sys/dev/pci/drm/radeon/smu7_fusion.h

252

uint32_t DRAM_LOG_ADDR_H;

sys/dev/pci/drm/radeon/smu7_fusion.h

253

uint32_t DRAM_LOG_ADDR_L;

sys/dev/pci/drm/radeon/smu7_fusion.h

254

uint32_t DRAM_LOG_PHY_ADDR_H;

sys/dev/pci/drm/radeon/smu7_fusion.h

255

uint32_t DRAM_LOG_PHY_ADDR_L;

sys/dev/pci/drm/radeon/smu7_fusion.h

256

uint32_t DRAM_LOG_BUFF_SIZE;

sys/dev/pci/drm/radeon/smu7_fusion.h

266

uint32_t GIOLevelCount;

sys/dev/pci/drm/radeon/smu7_fusion.h

40

uint32_t RefClockFrequency;

sys/dev/pci/drm/radeon/smu7_fusion.h

41

uint32_t PmTimerP;

sys/dev/pci/drm/radeon/smu7_fusion.h

42

uint32_t FeatureEnables;

sys/dev/pci/drm/radeon/smu7_fusion.h

43

uint32_t HandshakeDisables;

sys/dev/pci/drm/radeon/smu7_fusion.h

55

uint32_t AverageGraphicsA;

sys/dev/pci/drm/radeon/smu7_fusion.h

56

uint32_t AverageMemoryA;

sys/dev/pci/drm/radeon/smu7_fusion.h

57

uint32_t AverageGioA;

sys/dev/pci/drm/radeon/smu7_fusion.h

69

uint32_t DRAM_LOG_ADDR_H;

sys/dev/pci/drm/radeon/smu7_fusion.h

70

uint32_t DRAM_LOG_ADDR_L;

sys/dev/pci/drm/radeon/smu7_fusion.h

71

uint32_t DRAM_LOG_PHY_ADDR_H;

sys/dev/pci/drm/radeon/smu7_fusion.h

72

uint32_t DRAM_LOG_PHY_ADDR_L;

sys/dev/pci/drm/radeon/smu7_fusion.h

73

uint32_t DRAM_LOG_BUFF_SIZE;

sys/dev/pci/drm/radeon/smu7_fusion.h

74

uint32_t UlvEnterC;

sys/dev/pci/drm/radeon/smu7_fusion.h

75

uint32_t UlvTime;

sys/dev/pci/drm/radeon/smu7_fusion.h

76

uint32_t Reserved[3];

sys/dev/pci/drm/radeon/smu7_fusion.h

83

uint32_t MinVddNb;

sys/dev/pci/drm/radeon/smu7_fusion.h

85

uint32_t SclkFrequency;

sys/dev/pci/drm/radeon/uvd_v1_0.c

113

uint32_t size;

sys/dev/pci/drm/radeon/uvd_v1_0.c

145

WREG32(UVD_FW_START, *((uint32_t *)rdev->uvd.cpu_addr));

sys/dev/pci/drm/radeon/uvd_v1_0.c

160

uint32_t tmp;

sys/dev/pci/drm/radeon/uvd_v1_0.c

266

uint32_t rb_bufsz;

sys/dev/pci/drm/radeon/uvd_v1_0.c

330

uint32_t status;

sys/dev/pci/drm/radeon/uvd_v1_0.c

39

uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/uvd_v1_0.c

423

uint32_t tmp = 0;

sys/dev/pci/drm/radeon/uvd_v1_0.c

53

uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/uvd_v2_2.c

101

uint32_t chip_id, size;

sys/dev/pci/drm/radeon/uvd_v4_2.c

41

uint32_t size;

sys/dev/pci/drm/radeon/vce_v1_0.c

158

int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data)

sys/dev/pci/drm/radeon/vce_v1_0.c

161

uint32_t chip_id;

sys/dev/pci/drm/radeon/vce_v1_0.c

219

uint32_t size;

sys/dev/pci/drm/radeon/vce_v1_0.c

326

uint32_t status;

sys/dev/pci/drm/radeon/vce_v1_0.c

42

uint32_t len;

sys/dev/pci/drm/radeon/vce_v1_0.c

45

uint32_t chip_id;

sys/dev/pci/drm/radeon/vce_v1_0.c

46

uint32_t keyselect;

sys/dev/pci/drm/radeon/vce_v1_0.c

47

uint32_t nonce[4];

sys/dev/pci/drm/radeon/vce_v1_0.c

48

uint32_t sigval[4];

sys/dev/pci/drm/radeon/vce_v1_0.c

60

uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/vce_v1_0.c

77

uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,

sys/dev/pci/drm/radeon/vce_v2_0.c

161

uint32_t size;

sys/dev/pci/drm/ttm/tests/ttm_mock_manager.c

223

void ttm_bad_manager_fini(struct ttm_device *bdev, uint32_t mem_type)

sys/dev/pci/drm/ttm/ttm_agp_backend.c

141

uint32_t page_flags)

sys/dev/pci/drm/ttm/ttm_bo.c

1023

uint32_t alignment, bool interruptible,

sys/dev/pci/drm/ttm/ttm_bo.c

930

uint32_t alignment, struct ttm_operation_ctx *ctx,

sys/dev/pci/drm/ttm/ttm_tt.c

162

uint32_t page_flags,

sys/dev/pci/drm/ttm/ttm_tt.c

180

uint32_t page_flags, enum ttm_caching caching,

sys/dev/pci/drm/ttm/ttm_tt.c

226

uint32_t page_flags, enum ttm_caching caching)

sys/dev/pci/drm/ttm/ttm_tt.c

70

uint32_t page_flags = 0;

sys/dev/pci/glxpcib.c

180

const uint32_t glxpcib_msrlist[] = {

sys/dev/pci/if_age.c

1084

uint32_t reg;

sys/dev/pci/if_age.c

1118

uint32_t cflags, poff, vtag;

sys/dev/pci/if_age.c

1269

uint32_t status, index;

sys/dev/pci/if_age.c

1485

uint32_t reg;

sys/dev/pci/if_age.c

1513

uint32_t reg, fsize;

sys/dev/pci/if_age.c

1514

uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo;

sys/dev/pci/if_age.c

1790

uint32_t reg;

sys/dev/pci/if_age.c

1957

uint32_t reg;

sys/dev/pci/if_age.c

1984

uint32_t reg;

sys/dev/pci/if_age.c

2149

uint32_t reg;

sys/dev/pci/if_age.c

2165

uint32_t crc;

sys/dev/pci/if_age.c

2166

uint32_t mchash[2];

sys/dev/pci/if_age.c

2167

uint32_t rxcfg;

sys/dev/pci/if_age.c

306

uint32_t v;

sys/dev/pci/if_age.c

337

uint32_t v;

sys/dev/pci/if_age.c

392

uint32_t reg;

sys/dev/pci/if_age.c

445

uint32_t status;

sys/dev/pci/if_age.c

510

uint32_t ea[2], reg;

sys/dev/pci/if_agereg.h

496

uint32_t rx_frames;

sys/dev/pci/if_agereg.h

497

uint32_t rx_bcast_frames;

sys/dev/pci/if_agereg.h

498

uint32_t rx_mcast_frames;

sys/dev/pci/if_agereg.h

499

uint32_t rx_pause_frames;

sys/dev/pci/if_agereg.h

500

uint32_t rx_control_frames;

sys/dev/pci/if_agereg.h

501

uint32_t rx_crcerrs;

sys/dev/pci/if_agereg.h

502

uint32_t rx_lenerrs;

sys/dev/pci/if_agereg.h

503

uint32_t rx_bytes;

sys/dev/pci/if_agereg.h

504

uint32_t rx_runts;

sys/dev/pci/if_agereg.h

505

uint32_t rx_fragments;

sys/dev/pci/if_agereg.h

506

uint32_t rx_pkts_64;

sys/dev/pci/if_agereg.h

507

uint32_t rx_pkts_65_127;

sys/dev/pci/if_agereg.h

508

uint32_t rx_pkts_128_255;

sys/dev/pci/if_agereg.h

509

uint32_t rx_pkts_256_511;

sys/dev/pci/if_agereg.h

510

uint32_t rx_pkts_512_1023;

sys/dev/pci/if_agereg.h

511

uint32_t rx_pkts_1024_1518;

sys/dev/pci/if_agereg.h

512

uint32_t rx_pkts_1519_max;

sys/dev/pci/if_agereg.h

513

uint32_t rx_pkts_truncated;

sys/dev/pci/if_agereg.h

514

uint32_t rx_fifo_oflows;

sys/dev/pci/if_agereg.h

515

uint32_t rx_desc_oflows;

sys/dev/pci/if_agereg.h

516

uint32_t rx_alignerrs;

sys/dev/pci/if_agereg.h

517

uint32_t rx_bcast_bytes;

sys/dev/pci/if_agereg.h

518

uint32_t rx_mcast_bytes;

sys/dev/pci/if_agereg.h

519

uint32_t rx_pkts_filtered;

sys/dev/pci/if_agereg.h

521

uint32_t tx_frames;

sys/dev/pci/if_agereg.h

522

uint32_t tx_bcast_frames;

sys/dev/pci/if_agereg.h

523

uint32_t tx_mcast_frames;

sys/dev/pci/if_agereg.h

524

uint32_t tx_pause_frames;

sys/dev/pci/if_agereg.h

525

uint32_t tx_excess_defer;

sys/dev/pci/if_agereg.h

526

uint32_t tx_control_frames;

sys/dev/pci/if_agereg.h

527

uint32_t tx_deferred;

sys/dev/pci/if_agereg.h

528

uint32_t tx_bytes;

sys/dev/pci/if_agereg.h

529

uint32_t tx_pkts_64;

sys/dev/pci/if_agereg.h

530

uint32_t tx_pkts_65_127;

sys/dev/pci/if_agereg.h

531

uint32_t tx_pkts_128_255;

sys/dev/pci/if_agereg.h

532

uint32_t tx_pkts_256_511;

sys/dev/pci/if_agereg.h

533

uint32_t tx_pkts_512_1023;

sys/dev/pci/if_agereg.h

534

uint32_t tx_pkts_1024_1518;

sys/dev/pci/if_agereg.h

535

uint32_t tx_pkts_1519_max;

sys/dev/pci/if_agereg.h

536

uint32_t tx_single_colls;

sys/dev/pci/if_agereg.h

537

uint32_t tx_multi_colls;

sys/dev/pci/if_agereg.h

538

uint32_t tx_late_colls;

sys/dev/pci/if_agereg.h

539

uint32_t tx_excess_colls;

sys/dev/pci/if_agereg.h

540

uint32_t tx_underrun;

sys/dev/pci/if_agereg.h

541

uint32_t tx_desc_underrun;

sys/dev/pci/if_agereg.h

542

uint32_t tx_lenerrs;

sys/dev/pci/if_agereg.h

543

uint32_t tx_pkts_truncated;

sys/dev/pci/if_agereg.h

544

uint32_t tx_bcast_bytes;

sys/dev/pci/if_agereg.h

545

uint32_t tx_mcast_bytes;

sys/dev/pci/if_agereg.h

546

uint32_t updated;

sys/dev/pci/if_agereg.h

551

uint32_t intr_status;

sys/dev/pci/if_agereg.h

552

uint32_t rprod_cons;

sys/dev/pci/if_agereg.h

557

uint32_t tpd_cons;

sys/dev/pci/if_agereg.h

565

uint32_t index;

sys/dev/pci/if_agereg.h

570

uint32_t len;

sys/dev/pci/if_agereg.h

575

uint32_t flags;

sys/dev/pci/if_agereg.h

595

uint32_t vtags;

sys/dev/pci/if_agereg.h

616

uint32_t len;

sys/dev/pci/if_agereg.h

626

uint32_t len;

sys/dev/pci/if_agereg.h

637

uint32_t flags;

sys/dev/pci/if_agereg.h

765

uint32_t rx_pause_frames;

sys/dev/pci/if_agereg.h

766

uint32_t rx_control_frames;

sys/dev/pci/if_agereg.h

767

uint32_t rx_crcerrs;

sys/dev/pci/if_agereg.h

768

uint32_t rx_lenerrs;

sys/dev/pci/if_agereg.h

770

uint32_t rx_runts;

sys/dev/pci/if_agereg.h

780

uint32_t rx_fifo_oflows;

sys/dev/pci/if_agereg.h

781

uint32_t rx_desc_oflows;

sys/dev/pci/if_agereg.h

782

uint32_t rx_alignerrs;

sys/dev/pci/if_agereg.h

790

uint32_t tx_pause_frames;

sys/dev/pci/if_agereg.h

791

uint32_t tx_excess_defer;

sys/dev/pci/if_agereg.h

792

uint32_t tx_control_frames;

sys/dev/pci/if_agereg.h

793

uint32_t tx_deferred;

sys/dev/pci/if_agereg.h

802

uint32_t tx_single_colls;

sys/dev/pci/if_agereg.h

803

uint32_t tx_multi_colls;

sys/dev/pci/if_agereg.h

804

uint32_t tx_late_colls;

sys/dev/pci/if_agereg.h

805

uint32_t tx_excess_colls;

sys/dev/pci/if_agereg.h

806

uint32_t tx_underrun;

sys/dev/pci/if_agereg.h

807

uint32_t tx_desc_underrun;

sys/dev/pci/if_agereg.h

808

uint32_t tx_lenerrs;

sys/dev/pci/if_agereg.h

809

uint32_t tx_pkts_truncated;

sys/dev/pci/if_agereg.h

836

uint32_t age_dma_rd_burst;

sys/dev/pci/if_agereg.h

837

uint32_t age_dma_wr_burst;

sys/dev/pci/if_agereg.h

839

uint32_t age_flags;

sys/dev/pci/if_alc.c

1062

uint32_t pmcfg;

sys/dev/pci/if_alc.c

1098

uint32_t cap, ctl, val;

sys/dev/pci/if_alc.c

1171

uint32_t ctl, mod;

sys/dev/pci/if_alc.c

132

uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 };

sys/dev/pci/if_alc.c

168

uint32_t v;

sys/dev/pci/if_alc.c

1809

uint32_t cflags, poff, vtag;

sys/dev/pci/if_alc.c

185

uint32_t v;

sys/dev/pci/if_alc.c

2023

uint32_t reg;

sys/dev/pci/if_alc.c

2058

uint32_t *reg;

sys/dev/pci/if_alc.c

2075

i += sizeof(uint32_t);

sys/dev/pci/if_alc.c

2081

i += sizeof(uint32_t);

sys/dev/pci/if_alc.c

2092

uint32_t *reg;

sys/dev/pci/if_alc.c

2109

i += sizeof(uint32_t);

sys/dev/pci/if_alc.c

2115

i += sizeof(uint32_t);

sys/dev/pci/if_alc.c

2198

uint32_t status;

sys/dev/pci/if_alc.c

220

uint32_t clk, v;

sys/dev/pci/if_alc.c

2256

uint32_t cons, prod;

sys/dev/pci/if_alc.c

2361

uint32_t nsegs, status;

sys/dev/pci/if_alc.c

2436

uint32_t rdinfo, status;

sys/dev/pci/if_alc.c

2561

uint32_t reg;

sys/dev/pci/if_alc.c

2596

uint32_t reg, pmcfg = 0;

sys/dev/pci/if_alc.c

263

uint32_t v;

sys/dev/pci/if_alc.c

2684

uint32_t reg, rxf_hi, rxf_lo;

sys/dev/pci/if_alc.c

285

uint32_t clk, v;

sys/dev/pci/if_alc.c

3071

uint32_t reg;

sys/dev/pci/if_alc.c

313

uint32_t reg;

sys/dev/pci/if_alc.c

3141

uint32_t reg;

sys/dev/pci/if_alc.c

3165

uint32_t qcfg[] = {

sys/dev/pci/if_alc.c

3172

uint32_t cfg;

sys/dev/pci/if_alc.c

3192

uint32_t reg;

sys/dev/pci/if_alc.c

3322

uint32_t reg;

sys/dev/pci/if_alc.c

3339

uint32_t crc;

sys/dev/pci/if_alc.c

3340

uint32_t mchash[2];

sys/dev/pci/if_alc.c

3341

uint32_t rxcfg;

sys/dev/pci/if_alc.c

372

uint32_t clk, v;

sys/dev/pci/if_alc.c

402

uint32_t clk, v;

sys/dev/pci/if_alc.c

549

uint32_t opt;

sys/dev/pci/if_alc.c

650

uint32_t reg;

sys/dev/pci/if_alc.c

709

uint32_t ea[2];

sys/dev/pci/if_alc.c

724

uint32_t pmcfg;

sys/dev/pci/if_alc.c

864

uint32_t val;

sys/dev/pci/if_alc.c

921

uint32_t gphy;

sys/dev/pci/if_alc.c

979

uint32_t pmcfg;

sys/dev/pci/if_alcreg.h

1096

uint32_t rx_frames;

sys/dev/pci/if_alcreg.h

1097

uint32_t rx_bcast_frames;

sys/dev/pci/if_alcreg.h

1098

uint32_t rx_mcast_frames;

sys/dev/pci/if_alcreg.h

1099

uint32_t rx_pause_frames;

sys/dev/pci/if_alcreg.h

1100

uint32_t rx_control_frames;

sys/dev/pci/if_alcreg.h

1101

uint32_t rx_crcerrs;

sys/dev/pci/if_alcreg.h

1102

uint32_t rx_lenerrs;

sys/dev/pci/if_alcreg.h

1103

uint32_t rx_bytes;

sys/dev/pci/if_alcreg.h

1104

uint32_t rx_runts;

sys/dev/pci/if_alcreg.h

1105

uint32_t rx_fragments;

sys/dev/pci/if_alcreg.h

1106

uint32_t rx_pkts_64;

sys/dev/pci/if_alcreg.h

1107

uint32_t rx_pkts_65_127;

sys/dev/pci/if_alcreg.h

1108

uint32_t rx_pkts_128_255;

sys/dev/pci/if_alcreg.h

1109

uint32_t rx_pkts_256_511;

sys/dev/pci/if_alcreg.h

1110

uint32_t rx_pkts_512_1023;

sys/dev/pci/if_alcreg.h

1111

uint32_t rx_pkts_1024_1518;

sys/dev/pci/if_alcreg.h

1112

uint32_t rx_pkts_1519_max;

sys/dev/pci/if_alcreg.h

1113

uint32_t rx_pkts_truncated;

sys/dev/pci/if_alcreg.h

1114

uint32_t rx_fifo_oflows;

sys/dev/pci/if_alcreg.h

1115

uint32_t rx_rrs_errs;

sys/dev/pci/if_alcreg.h

1116

uint32_t rx_alignerrs;

sys/dev/pci/if_alcreg.h

1117

uint32_t rx_bcast_bytes;

sys/dev/pci/if_alcreg.h

1118

uint32_t rx_mcast_bytes;

sys/dev/pci/if_alcreg.h

1119

uint32_t rx_pkts_filtered;

sys/dev/pci/if_alcreg.h

1121

uint32_t tx_frames;

sys/dev/pci/if_alcreg.h

1122

uint32_t tx_bcast_frames;

sys/dev/pci/if_alcreg.h

1123

uint32_t tx_mcast_frames;

sys/dev/pci/if_alcreg.h

1124

uint32_t tx_pause_frames;

sys/dev/pci/if_alcreg.h

1125

uint32_t tx_excess_defer;

sys/dev/pci/if_alcreg.h

1126

uint32_t tx_control_frames;

sys/dev/pci/if_alcreg.h

1127

uint32_t tx_deferred;

sys/dev/pci/if_alcreg.h

1128

uint32_t tx_bytes;

sys/dev/pci/if_alcreg.h

1129

uint32_t tx_pkts_64;

sys/dev/pci/if_alcreg.h

1130

uint32_t tx_pkts_65_127;

sys/dev/pci/if_alcreg.h

1131

uint32_t tx_pkts_128_255;

sys/dev/pci/if_alcreg.h

1132

uint32_t tx_pkts_256_511;

sys/dev/pci/if_alcreg.h

1133

uint32_t tx_pkts_512_1023;

sys/dev/pci/if_alcreg.h

1134

uint32_t tx_pkts_1024_1518;

sys/dev/pci/if_alcreg.h

1135

uint32_t tx_pkts_1519_max;

sys/dev/pci/if_alcreg.h

1136

uint32_t tx_single_colls;

sys/dev/pci/if_alcreg.h

1137

uint32_t tx_multi_colls;

sys/dev/pci/if_alcreg.h

1138

uint32_t tx_late_colls;

sys/dev/pci/if_alcreg.h

1139

uint32_t tx_excess_colls;

sys/dev/pci/if_alcreg.h

1140

uint32_t tx_underrun;

sys/dev/pci/if_alcreg.h

1141

uint32_t tx_desc_underrun;

sys/dev/pci/if_alcreg.h

1142

uint32_t tx_lenerrs;

sys/dev/pci/if_alcreg.h

1143

uint32_t tx_pkts_truncated;

sys/dev/pci/if_alcreg.h

1144

uint32_t tx_bcast_bytes;

sys/dev/pci/if_alcreg.h

1145

uint32_t tx_mcast_bytes;

sys/dev/pci/if_alcreg.h

1146

uint32_t updated;

sys/dev/pci/if_alcreg.h

1151

uint32_t cons;

sys/dev/pci/if_alcreg.h

1161

uint32_t rdinfo;

sys/dev/pci/if_alcreg.h

1174

uint32_t rss;

sys/dev/pci/if_alcreg.h

1175

uint32_t vtag;

sys/dev/pci/if_alcreg.h

1195

uint32_t status;

sys/dev/pci/if_alcreg.h

1225

uint32_t len;

sys/dev/pci/if_alcreg.h

1232

uint32_t flags;

sys/dev/pci/if_alcreg.h

1368

uint32_t rx_frames;

sys/dev/pci/if_alcreg.h

1369

uint32_t rx_bcast_frames;

sys/dev/pci/if_alcreg.h

1370

uint32_t rx_mcast_frames;

sys/dev/pci/if_alcreg.h

1371

uint32_t rx_pause_frames;

sys/dev/pci/if_alcreg.h

1372

uint32_t rx_control_frames;

sys/dev/pci/if_alcreg.h

1373

uint32_t rx_crcerrs;

sys/dev/pci/if_alcreg.h

1374

uint32_t rx_lenerrs;

sys/dev/pci/if_alcreg.h

1376

uint32_t rx_runts;

sys/dev/pci/if_alcreg.h

1377

uint32_t rx_fragments;

sys/dev/pci/if_alcreg.h

1378

uint32_t rx_pkts_64;

sys/dev/pci/if_alcreg.h

1379

uint32_t rx_pkts_65_127;

sys/dev/pci/if_alcreg.h

1380

uint32_t rx_pkts_128_255;

sys/dev/pci/if_alcreg.h

1381

uint32_t rx_pkts_256_511;

sys/dev/pci/if_alcreg.h

1382

uint32_t rx_pkts_512_1023;

sys/dev/pci/if_alcreg.h

1383

uint32_t rx_pkts_1024_1518;

sys/dev/pci/if_alcreg.h

1384

uint32_t rx_pkts_1519_max;

sys/dev/pci/if_alcreg.h

1385

uint32_t rx_pkts_truncated;

sys/dev/pci/if_alcreg.h

1386

uint32_t rx_fifo_oflows;

sys/dev/pci/if_alcreg.h

1387

uint32_t rx_rrs_errs;

sys/dev/pci/if_alcreg.h

1388

uint32_t rx_alignerrs;

sys/dev/pci/if_alcreg.h

1391

uint32_t rx_pkts_filtered;

sys/dev/pci/if_alcreg.h

1393

uint32_t tx_frames;

sys/dev/pci/if_alcreg.h

1394

uint32_t tx_bcast_frames;

sys/dev/pci/if_alcreg.h

1395

uint32_t tx_mcast_frames;

sys/dev/pci/if_alcreg.h

1396

uint32_t tx_pause_frames;

sys/dev/pci/if_alcreg.h

1397

uint32_t tx_excess_defer;

sys/dev/pci/if_alcreg.h

1398

uint32_t tx_control_frames;

sys/dev/pci/if_alcreg.h

1399

uint32_t tx_deferred;

sys/dev/pci/if_alcreg.h

1401

uint32_t tx_pkts_64;

sys/dev/pci/if_alcreg.h

1402

uint32_t tx_pkts_65_127;

sys/dev/pci/if_alcreg.h

1403

uint32_t tx_pkts_128_255;

sys/dev/pci/if_alcreg.h

1404

uint32_t tx_pkts_256_511;

sys/dev/pci/if_alcreg.h

1405

uint32_t tx_pkts_512_1023;

sys/dev/pci/if_alcreg.h

1406

uint32_t tx_pkts_1024_1518;

sys/dev/pci/if_alcreg.h

1407

uint32_t tx_pkts_1519_max;

sys/dev/pci/if_alcreg.h

1408

uint32_t tx_single_colls;

sys/dev/pci/if_alcreg.h

1409

uint32_t tx_multi_colls;

sys/dev/pci/if_alcreg.h

1410

uint32_t tx_late_colls;

sys/dev/pci/if_alcreg.h

1411

uint32_t tx_excess_colls;

sys/dev/pci/if_alcreg.h

1412

uint32_t tx_underrun;

sys/dev/pci/if_alcreg.h

1413

uint32_t tx_desc_underrun;

sys/dev/pci/if_alcreg.h

1414

uint32_t tx_lenerrs;

sys/dev/pci/if_alcreg.h

1415

uint32_t tx_pkts_truncated;

sys/dev/pci/if_alcreg.h

1442

uint32_t alc_max_framelen;

sys/dev/pci/if_alcreg.h

1443

uint32_t alc_dma_rd_burst;

sys/dev/pci/if_alcreg.h

1444

uint32_t alc_dma_wr_burst;

sys/dev/pci/if_alcreg.h

1445

uint32_t alc_rcb;

sys/dev/pci/if_ale.c

1102

uint32_t reg;

sys/dev/pci/if_ale.c

1132

uint32_t *reg;

sys/dev/pci/if_ale.c

1137

i += sizeof(uint32_t);

sys/dev/pci/if_ale.c

1142

i += sizeof(uint32_t);

sys/dev/pci/if_ale.c

1152

uint32_t *reg;

sys/dev/pci/if_ale.c

1161

i += sizeof(uint32_t);

sys/dev/pci/if_ale.c

1166

i += sizeof(uint32_t);

sys/dev/pci/if_ale.c

1240

uint32_t status;

sys/dev/pci/if_ale.c

1284

uint32_t cons, prod;

sys/dev/pci/if_ale.c

132

uint32_t v;

sys/dev/pci/if_ale.c

1335

uint32_t length, uint32_t *prod)

sys/dev/pci/if_ale.c

1384

ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status)

sys/dev/pci/if_ale.c

1433

uint32_t length, prod, seqno, status;

sys/dev/pci/if_ale.c

1518

uint32_t vtags = ALE_RX_VLAN(letoh32(rs->vtags));

sys/dev/pci/if_ale.c

1552

uint32_t reg;

sys/dev/pci/if_ale.c

1585

uint32_t reg, rxf_hi, rxf_lo;

sys/dev/pci/if_ale.c

164

uint32_t v;

sys/dev/pci/if_ale.c

1825

uint32_t reg;

sys/dev/pci/if_ale.c

1880

uint32_t reg;

sys/dev/pci/if_ale.c

191

uint32_t reg;

sys/dev/pci/if_ale.c

1953

uint32_t reg;

sys/dev/pci/if_ale.c

1969

uint32_t crc;

sys/dev/pci/if_ale.c

1970

uint32_t mchash[2];

sys/dev/pci/if_ale.c

1971

uint32_t rxcfg;

sys/dev/pci/if_ale.c

270

uint32_t ea[2], reg;

sys/dev/pci/if_ale.c

370

uint32_t rxf_len, txf_len;

sys/dev/pci/if_ale.c

863

uint32_t cflags, poff, vtag;

sys/dev/pci/if_ale.c

88

uint32_t, uint32_t *);

sys/dev/pci/if_ale.c

89

void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t);

sys/dev/pci/if_alereg.h

557

uint32_t rx_frames;

sys/dev/pci/if_alereg.h

558

uint32_t rx_bcast_frames;

sys/dev/pci/if_alereg.h

559

uint32_t rx_mcast_frames;

sys/dev/pci/if_alereg.h

560

uint32_t rx_pause_frames;

sys/dev/pci/if_alereg.h

561

uint32_t rx_control_frames;

sys/dev/pci/if_alereg.h

562

uint32_t rx_crcerrs;

sys/dev/pci/if_alereg.h

563

uint32_t rx_lenerrs;

sys/dev/pci/if_alereg.h

564

uint32_t rx_bytes;

sys/dev/pci/if_alereg.h

565

uint32_t rx_runts;

sys/dev/pci/if_alereg.h

566

uint32_t rx_fragments;

sys/dev/pci/if_alereg.h

567

uint32_t rx_pkts_64;

sys/dev/pci/if_alereg.h

568

uint32_t rx_pkts_65_127;

sys/dev/pci/if_alereg.h

569

uint32_t rx_pkts_128_255;

sys/dev/pci/if_alereg.h

570

uint32_t rx_pkts_256_511;

sys/dev/pci/if_alereg.h

571

uint32_t rx_pkts_512_1023;

sys/dev/pci/if_alereg.h

572

uint32_t rx_pkts_1024_1518;

sys/dev/pci/if_alereg.h

573

uint32_t rx_pkts_1519_max;

sys/dev/pci/if_alereg.h

574

uint32_t rx_pkts_truncated;

sys/dev/pci/if_alereg.h

575

uint32_t rx_fifo_oflows;

sys/dev/pci/if_alereg.h

576

uint32_t rx_rrs_errs;

sys/dev/pci/if_alereg.h

577

uint32_t rx_alignerrs;

sys/dev/pci/if_alereg.h

578

uint32_t rx_bcast_bytes;

sys/dev/pci/if_alereg.h

579

uint32_t rx_mcast_bytes;

sys/dev/pci/if_alereg.h

580

uint32_t rx_pkts_filtered;

sys/dev/pci/if_alereg.h

582

uint32_t tx_frames;

sys/dev/pci/if_alereg.h

583

uint32_t tx_bcast_frames;

sys/dev/pci/if_alereg.h

584

uint32_t tx_mcast_frames;

sys/dev/pci/if_alereg.h

585

uint32_t tx_pause_frames;

sys/dev/pci/if_alereg.h

586

uint32_t tx_excess_defer;

sys/dev/pci/if_alereg.h

587

uint32_t tx_control_frames;

sys/dev/pci/if_alereg.h

588

uint32_t tx_deferred;

sys/dev/pci/if_alereg.h

589

uint32_t tx_bytes;

sys/dev/pci/if_alereg.h

590

uint32_t tx_pkts_64;

sys/dev/pci/if_alereg.h

591

uint32_t tx_pkts_65_127;

sys/dev/pci/if_alereg.h

592

uint32_t tx_pkts_128_255;

sys/dev/pci/if_alereg.h

593

uint32_t tx_pkts_256_511;

sys/dev/pci/if_alereg.h

594

uint32_t tx_pkts_512_1023;

sys/dev/pci/if_alereg.h

595

uint32_t tx_pkts_1024_1518;

sys/dev/pci/if_alereg.h

596

uint32_t tx_pkts_1519_max;

sys/dev/pci/if_alereg.h

597

uint32_t tx_single_colls;

sys/dev/pci/if_alereg.h

598

uint32_t tx_multi_colls;

sys/dev/pci/if_alereg.h

599

uint32_t tx_late_colls;

sys/dev/pci/if_alereg.h

600

uint32_t tx_excess_colls;

sys/dev/pci/if_alereg.h

601

uint32_t tx_underrun;

sys/dev/pci/if_alereg.h

602

uint32_t tx_desc_underrun;

sys/dev/pci/if_alereg.h

603

uint32_t tx_lenerrs;

sys/dev/pci/if_alereg.h

604

uint32_t tx_pkts_truncated;

sys/dev/pci/if_alereg.h

605

uint32_t tx_bcast_bytes;

sys/dev/pci/if_alereg.h

606

uint32_t tx_mcast_bytes;

sys/dev/pci/if_alereg.h

656

uint32_t seqno;

sys/dev/pci/if_alereg.h

663

uint32_t length;

sys/dev/pci/if_alereg.h

676

uint32_t flags;

sys/dev/pci/if_alereg.h

703

uint32_t vtags;

sys/dev/pci/if_alereg.h

717

uint32_t len;

sys/dev/pci/if_alereg.h

728

uint32_t flags;

sys/dev/pci/if_alereg.h

801

uint32_t *cmb_addr;

sys/dev/pci/if_alereg.h

803

uint32_t cons;

sys/dev/pci/if_alereg.h

814

uint32_t *ale_tx_cmb;

sys/dev/pci/if_alereg.h

819

uint32_t ale_tx_prod;

sys/dev/pci/if_alereg.h

820

uint32_t ale_tx_cons;

sys/dev/pci/if_alereg.h

834

#define ALE_TX_CMB_SZ (sizeof(uint32_t))

sys/dev/pci/if_alereg.h

835

#define ALE_RX_CMB_SZ (sizeof(uint32_t))

sys/dev/pci/if_alereg.h

844

uint32_t rx_frames;

sys/dev/pci/if_alereg.h

845

uint32_t rx_bcast_frames;

sys/dev/pci/if_alereg.h

846

uint32_t rx_mcast_frames;

sys/dev/pci/if_alereg.h

847

uint32_t rx_pause_frames;

sys/dev/pci/if_alereg.h

848

uint32_t rx_control_frames;

sys/dev/pci/if_alereg.h

849

uint32_t rx_crcerrs;

sys/dev/pci/if_alereg.h

850

uint32_t rx_lenerrs;

sys/dev/pci/if_alereg.h

852

uint32_t rx_runts;

sys/dev/pci/if_alereg.h

853

uint32_t rx_fragments;

sys/dev/pci/if_alereg.h

854

uint32_t rx_pkts_64;

sys/dev/pci/if_alereg.h

855

uint32_t rx_pkts_65_127;

sys/dev/pci/if_alereg.h

856

uint32_t rx_pkts_128_255;

sys/dev/pci/if_alereg.h

857

uint32_t rx_pkts_256_511;

sys/dev/pci/if_alereg.h

858

uint32_t rx_pkts_512_1023;

sys/dev/pci/if_alereg.h

859

uint32_t rx_pkts_1024_1518;

sys/dev/pci/if_alereg.h

860

uint32_t rx_pkts_1519_max;

sys/dev/pci/if_alereg.h

861

uint32_t rx_pkts_truncated;

sys/dev/pci/if_alereg.h

862

uint32_t rx_fifo_oflows;

sys/dev/pci/if_alereg.h

863

uint32_t rx_rrs_errs;

sys/dev/pci/if_alereg.h

864

uint32_t rx_alignerrs;

sys/dev/pci/if_alereg.h

867

uint32_t rx_pkts_filtered;

sys/dev/pci/if_alereg.h

869

uint32_t tx_frames;

sys/dev/pci/if_alereg.h

870

uint32_t tx_bcast_frames;

sys/dev/pci/if_alereg.h

871

uint32_t tx_mcast_frames;

sys/dev/pci/if_alereg.h

872

uint32_t tx_pause_frames;

sys/dev/pci/if_alereg.h

873

uint32_t tx_excess_defer;

sys/dev/pci/if_alereg.h

874

uint32_t tx_control_frames;

sys/dev/pci/if_alereg.h

875

uint32_t tx_deferred;

sys/dev/pci/if_alereg.h

877

uint32_t tx_pkts_64;

sys/dev/pci/if_alereg.h

878

uint32_t tx_pkts_65_127;

sys/dev/pci/if_alereg.h

879

uint32_t tx_pkts_128_255;

sys/dev/pci/if_alereg.h

880

uint32_t tx_pkts_256_511;

sys/dev/pci/if_alereg.h

881

uint32_t tx_pkts_512_1023;

sys/dev/pci/if_alereg.h

882

uint32_t tx_pkts_1024_1518;

sys/dev/pci/if_alereg.h

883

uint32_t tx_pkts_1519_max;

sys/dev/pci/if_alereg.h

884

uint32_t tx_single_colls;

sys/dev/pci/if_alereg.h

885

uint32_t tx_multi_colls;

sys/dev/pci/if_alereg.h

886

uint32_t tx_late_colls;

sys/dev/pci/if_alereg.h

887

uint32_t tx_excess_colls;

sys/dev/pci/if_alereg.h

888

uint32_t tx_underrun;

sys/dev/pci/if_alereg.h

889

uint32_t tx_desc_underrun;

sys/dev/pci/if_alereg.h

890

uint32_t tx_lenerrs;

sys/dev/pci/if_alereg.h

891

uint32_t tx_pkts_truncated;

sys/dev/pci/if_alereg.h

895

uint32_t reset_brk_seq;

sys/dev/pci/if_alereg.h

920

uint32_t ale_dma_rd_burst;

sys/dev/pci/if_alereg.h

921

uint32_t ale_dma_wr_burst;

sys/dev/pci/if_aq_pci.c

1005

uint32_t sc_mbox_addr;

sys/dev/pci/if_aq_pci.c

1010

uint32_t sc_fw_version;

sys/dev/pci/if_aq_pci.c

1015

uint32_t sc_features;

sys/dev/pci/if_aq_pci.c

1167

int aq1_fw_downld_dwords(struct aq_softc *, uint32_t, uint32_t *, uint32_t);

sys/dev/pci/if_aq_pci.c

1169

int aq2_interface_buffer_read(struct aq_softc *, uint32_t, uint32_t *,

sys/dev/pci/if_aq_pci.c

1170

uint32_t);

sys/dev/pci/if_aq_pci.c

1172

int aq2_filter_art_set(struct aq_softc *, uint32_t, uint32_t, uint32_t,

sys/dev/pci/if_aq_pci.c

1173

uint32_t action);

sys/dev/pci/if_aq_pci.c

1534

uint32_t ver, v, boot_exit_code;

sys/dev/pci/if_aq_pci.c

1663

uint32_t v;

sys/dev/pci/if_aq_pci.c

1704

uint32_t flb_status;

sys/dev/pci/if_aq_pci.c

1762

uint32_t v;

sys/dev/pci/if_aq_pci.c

1811

uint32_t hwrev = AQ_READ_REG(sc, AQ_HW_REVISION_REG);

sys/dev/pci/if_aq_pci.c

1845

uint32_t data;

sys/dev/pci/if_aq_pci.c

1880

aq2_interface_buffer_read(struct aq_softc *sc, uint32_t reg0, uint32_t *data0,

sys/dev/pci/if_aq_pci.c

1881

uint32_t size0)

sys/dev/pci/if_aq_pci.c

1883

uint32_t tid0, tid1, reg, *data, size;

sys/dev/pci/if_aq_pci.c

1915

uint32_t v;

sys/dev/pci/if_aq_pci.c

1918

uint32_t filter_caps[3];

sys/dev/pci/if_aq_pci.c

1968

(uint32_t *)&v, sizeof(v));

sys/dev/pci/if_aq_pci.c

1981

(uint32_t *)&v, sizeof(v));

sys/dev/pci/if_aq_pci.c

2040

uint32_t mac_addr[2];

sys/dev/pci/if_aq_pci.c

2041

uint32_t efuse_shadow_addr;

sys/dev/pci/if_aq_pci.c

2090

aq1_fw_downld_dwords(struct aq_softc *sc, uint32_t addr, uint32_t *p,

sys/dev/pci/if_aq_pci.c

2091

uint32_t cnt)

sys/dev/pci/if_aq_pci.c

2093

uint32_t v;

sys/dev/pci/if_aq_pci.c

2123

addr += sizeof(uint32_t);

sys/dev/pci/if_aq_pci.c

2142

(uint32_t *)&caps, sizeof caps / sizeof(uint32_t));

sys/dev/pci/if_aq_pci.c

2256

uint32_t v;

sys/dev/pci/if_aq_pci.c

2286

uint32_t mac_addr[2];

sys/dev/pci/if_aq_pci.c

2317

uint32_t v, ov;

sys/dev/pci/if_aq_pci.c

2388

uint32_t v;

sys/dev/pci/if_aq_pci.c

2449

uint32_t v;

sys/dev/pci/if_aq_pci.c

2466

uint32_t fpgaver, speed;

sys/dev/pci/if_aq_pci.c

2554

uint32_t bits;

sys/dev/pci/if_aq_pci.c

2652

uint32_t h, l;

sys/dev/pci/if_aq_pci.c

2665

l = ((uint32_t)enaddr[2] << 24) | (enaddr[3] << 16) |

sys/dev/pci/if_aq_pci.c

2762

uint32_t tc = 0;

sys/dev/pci/if_aq_pci.c

2763

uint32_t buff_size;

sys/dev/pci/if_aq_pci.c

2844

uint32_t rss_key[AQ_RSS_KEYSIZE / sizeof(uint32_t)];

sys/dev/pci/if_aq_pci.c

2845

uint32_t redir;

sys/dev/pci/if_aq_pci.c

3095

uint32_t end, idx;

sys/dev/pci/if_aq_pci.c

3097

uint32_t rxd_type;

sys/dev/pci/if_aq_pci.c

3211

uint32_t idx, end, free;

sys/dev/pci/if_aq_pci.c

3262

uint32_t idx, free, used, ctl1, ctl2;

sys/dev/pci/if_aq_pci.c

3375

uint32_t status;

sys/dev/pci/if_aq_pci.c

3376

uint32_t clear;

sys/dev/pci/if_aq_pci.c

3398

uint32_t status;

sys/dev/pci/if_aq_pci.c

3415

uint32_t status;

sys/dev/pci/if_aq_pci.c

3587

uint32_t cache;

sys/dev/pci/if_aq_pci.c

3661

uint32_t imask = 0;

sys/dev/pci/if_aq_pci.c

3875

aq2_filter_art_set(struct aq_softc *sc, uint32_t idx,

sys/dev/pci/if_aq_pci.c

3876

uint32_t tag, uint32_t mask, uint32_t action)

sys/dev/pci/if_aq_pci.c

3907

uint32_t action;

sys/dev/pci/if_aq_pci.c

611

#define __LOWEST_SET_BIT(__mask) (((((uint32_t)__mask) - 1) & ((uint32_t)__mask)) ^ ((uint32_t)__mask))

sys/dev/pci/if_aq_pci.c

624

uint32_t _v; \

sys/dev/pci/if_aq_pci.c

638

AQ_WRITE_REG(sc, reg, (uint32_t)val); \

sys/dev/pci/if_aq_pci.c

639

AQ_WRITE_REG(sc, reg + 4, (uint32_t)(val >> 32)); \

sys/dev/pci/if_aq_pci.c

816

uint32_t version;

sys/dev/pci/if_aq_pci.c

817

uint32_t transaction_id;

sys/dev/pci/if_aq_pci.c

822

uint32_t uprc;

sys/dev/pci/if_aq_pci.c

823

uint32_t mprc;

sys/dev/pci/if_aq_pci.c

824

uint32_t bprc;

sys/dev/pci/if_aq_pci.c

825

uint32_t erpt;

sys/dev/pci/if_aq_pci.c

826

uint32_t uptc;

sys/dev/pci/if_aq_pci.c

827

uint32_t mptc;

sys/dev/pci/if_aq_pci.c

828

uint32_t bptc;

sys/dev/pci/if_aq_pci.c

829

uint32_t erpr;

sys/dev/pci/if_aq_pci.c

830

uint32_t mbtc;

sys/dev/pci/if_aq_pci.c

831

uint32_t bbtc;

sys/dev/pci/if_aq_pci.c

832

uint32_t mbrc;

sys/dev/pci/if_aq_pci.c

833

uint32_t bbrc;

sys/dev/pci/if_aq_pci.c

834

uint32_t ubrc;

sys/dev/pci/if_aq_pci.c

835

uint32_t ubtc;

sys/dev/pci/if_aq_pci.c

836

uint32_t ptc;

sys/dev/pci/if_aq_pci.c

837

uint32_t prc;

sys/dev/pci/if_aq_pci.c

838

uint32_t dpc; /* not exists in fw2x_msm_statistics */

sys/dev/pci/if_aq_pci.c

839

uint32_t cprc; /* not exists in fw2x_msm_statistics */

sys/dev/pci/if_aq_pci.c

843

uint32_t caps_lo;

sys/dev/pci/if_aq_pci.c

844

uint32_t caps_hi;

sys/dev/pci/if_aq_pci.c

848

uint32_t uprc;

sys/dev/pci/if_aq_pci.c

849

uint32_t mprc;

sys/dev/pci/if_aq_pci.c

850

uint32_t bprc;

sys/dev/pci/if_aq_pci.c

851

uint32_t erpt;

sys/dev/pci/if_aq_pci.c

852

uint32_t uptc;

sys/dev/pci/if_aq_pci.c

853

uint32_t mptc;

sys/dev/pci/if_aq_pci.c

854

uint32_t bptc;

sys/dev/pci/if_aq_pci.c

855

uint32_t erpr;

sys/dev/pci/if_aq_pci.c

856

uint32_t mbtc;

sys/dev/pci/if_aq_pci.c

857

uint32_t bbtc;

sys/dev/pci/if_aq_pci.c

858

uint32_t mbrc;

sys/dev/pci/if_aq_pci.c

859

uint32_t bbrc;

sys/dev/pci/if_aq_pci.c

860

uint32_t ubrc;

sys/dev/pci/if_aq_pci.c

861

uint32_t ubtc;

sys/dev/pci/if_aq_pci.c

862

uint32_t ptc;

sys/dev/pci/if_aq_pci.c

863

uint32_t prc;

sys/dev/pci/if_aq_pci.c

867

uint32_t lane_data[4];

sys/dev/pci/if_aq_pci.c

874

uint32_t phy_info1;

sys/dev/pci/if_aq_pci.c

877

uint32_t phy_info2;

sys/dev/pci/if_aq_pci.c

882

uint32_t reserved[8];

sys/dev/pci/if_aq_pci.c

895

uint32_t type;

sys/dev/pci/if_aq_pci.c

904

uint32_t rss_hash;

sys/dev/pci/if_aq_pci.c

919

uint32_t ctl1;

sys/dev/pci/if_aq_pci.c

933

uint32_t ctl2;

sys/dev/pci/if_aq_pci.c

952

uint32_t rx_prod;

sys/dev/pci/if_aq_pci.c

953

uint32_t rx_cons;

sys/dev/pci/if_aq_pci.c

966

uint32_t tx_prod;

sys/dev/pci/if_aq_pci.c

967

uint32_t tx_cons;

sys/dev/pci/if_athn_pci.c

243

uint32_t

sys/dev/pci/if_athn_pci.c

244

athn_pci_read(struct athn_softc *sc, uint32_t addr)

sys/dev/pci/if_athn_pci.c

252

athn_pci_write(struct athn_softc *sc, uint32_t addr, uint32_t val)

sys/dev/pci/if_athn_pci.c

73

uint32_t athn_pci_read(struct athn_softc *, uint32_t);

sys/dev/pci/if_athn_pci.c

74

void athn_pci_write(struct athn_softc *, uint32_t, uint32_t);

sys/dev/pci/if_bge.c

202

void bge_ape_send_event(struct bge_softc *, uint32_t);

sys/dev/pci/if_bge.c

3856

uint32_t collisions, discards, inerrors;

sys/dev/pci/if_bge.c

3857

uint32_t ucast, mcast, bcast;

sys/dev/pci/if_bge.c

3946

ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrors);

sys/dev/pci/if_bge.c

554

uint32_t bit, regbase;

sys/dev/pci/if_bge.c

608

uint32_t apedata, features;

sys/dev/pci/if_bge.c

651

uint32_t bit, gnt, req, status;

sys/dev/pci/if_bge.c

733

uint32_t bit, gnt;

sys/dev/pci/if_bge.c

784

bge_ape_send_event(struct bge_softc *sc, uint32_t event)

sys/dev/pci/if_bge.c

786

uint32_t apedata;

sys/dev/pci/if_bge.c

817

uint32_t apedata, event;

sys/dev/pci/if_bnxt.c

1398

uint32_t rx_mask, mc_count;

sys/dev/pci/if_bnxt.c

154

uint32_t ring_size;

sys/dev/pci/if_bnxt.c

1622

uint32_t outlen;

sys/dev/pci/if_bnxt.c

1623

uint32_t paylen;

sys/dev/pci/if_bnxt.c

163

uint32_t cons;

sys/dev/pci/if_bnxt.c

165

uint32_t commit_cons;

sys/dev/pci/if_bnxt.c

171

uint32_t grp_id;

sys/dev/pci/if_bnxt.c

1723

uint32_t cons;

sys/dev/pci/if_bnxt.c

185

uint32_t flags;

sys/dev/pci/if_bnxt.c

191

uint32_t flow_id;

sys/dev/pci/if_bnxt.c

2400

uint32_t val = CMPL_DOORBELL_KEY_CMPL;

sys/dev/pci/if_bnxt.c

2415

uint32_t index, int enable)

sys/dev/pci/if_bnxt.c

2437

uint32_t val = CMPL_DOORBELL_KEY_CMPL |

sys/dev/pci/if_bnxt.c

2452

uint32_t index)

sys/dev/pci/if_bnxt.c

2471

uint32_t val = CMPL_DOORBELL_KEY_CMPL |

sys/dev/pci/if_bnxt.c

250

uint32_t q_stat_ctx_id;

sys/dev/pci/if_bnxt.c

2501

uint32_t val = RX_DOORBELL_KEY_RX | index;

sys/dev/pci/if_bnxt.c

2533

uint32_t val = TX_DOORBELL_KEY_TX | index;

sys/dev/pci/if_bnxt.c

2659

uint32_t flags;

sys/dev/pci/if_bnxt.c

272

uint32_t sc_cmd_timeo;

sys/dev/pci/if_bnxt.c

273

uint32_t sc_flags;

sys/dev/pci/if_bnxt.c

2817

_hwrm_send_message(struct bnxt_softc *softc, void *msg, uint32_t msg_len)

sys/dev/pci/if_bnxt.c

2821

uint32_t *data = msg;

sys/dev/pci/if_bnxt.c

2850

data = (uint32_t *)&short_input;

sys/dev/pci/if_bnxt.c

2923

hwrm_send_message(struct bnxt_softc *softc, void *msg, uint32_t msg_len)

sys/dev/pci/if_bnxt.c

2974

uint32_t dev_caps_cfg;

sys/dev/pci/if_bnxt.c

3455

uint32_t stat_ctx_id, int irq)

sys/dev/pci/if_bnxt.c

355

struct bnxt_cp_ring *, uint32_t, int);

sys/dev/pci/if_bnxt.c

357

struct bnxt_cp_ring *, uint32_t);

sys/dev/pci/if_bnxt.c

3577

bnxt_hwrm_stat_ctx_alloc(struct bnxt_softc *softc, uint32_t *stat_ctx_id,

sys/dev/pci/if_bnxt.c

3615

bnxt_hwrm_stat_ctx_free(struct bnxt_softc *softc, uint32_t *stat_ctx_id)

sys/dev/pci/if_bnxt.c

3664

uint32_t vnic_id, uint32_t rx_mask, uint64_t mc_addr, uint32_t mc_count)

sys/dev/pci/if_bnxt.c

3682

uint32_t enables = 0;

sys/dev/pci/if_bnxt.c

3744

uint32_t hash_type, daddr_t rss_table, daddr_t rss_key)

sys/dev/pci/if_bnxt.c

377

int _hwrm_send_message(struct bnxt_softc *, void *, uint32_t);

sys/dev/pci/if_bnxt.c

378

int hwrm_send_message(struct bnxt_softc *, void *, uint32_t);

sys/dev/pci/if_bnxt.c

3817

uint32_t *tqm_num_entries;

sys/dev/pci/if_bnxt.c

3818

uint32_t tqm_enable;

sys/dev/pci/if_bnxt.c

384

struct bnxt_ring *, uint16_t, uint16_t, uint32_t, int);

sys/dev/pci/if_bnxt.c

400

uint32_t *, uint64_t);

sys/dev/pci/if_bnxt.c

402

uint32_t *);

sys/dev/pci/if_bnxt.c

4067

uint32_t flags;

sys/dev/pci/if_bnxt.c

412

uint32_t, uint32_t, uint64_t, uint32_t);

sys/dev/pci/if_bnxt.c

4157

uint16_t *device_id, uint32_t *sector_size, uint32_t *nvram_size,

sys/dev/pci/if_bnxt.c

4158

uint32_t *reserved_size, uint32_t *available_size)

sys/dev/pci/if_bnxt.c

4164

uint32_t old_timeo;

sys/dev/pci/if_bnxt.c

418

struct bnxt_vnic_info *, uint32_t, daddr_t, daddr_t);

sys/dev/pci/if_bnxt.c

423

uint16_t *, uint32_t *, uint32_t *, uint32_t *, uint32_t *);

sys/dev/pci/if_bnxtreg.h

10029

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

10045

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

10073

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

10089

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

10146

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

10170

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

10210

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

10226

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

10270

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

10286

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

10314

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

10330

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

10372

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

10412

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

10460

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

10496

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

10566

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

10582

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

10622

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

10651

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

10676

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

10692

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

10720

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

10736

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

10764

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

10780

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

10808

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

10824

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

10855

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

10871

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

10902

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

10918

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

10949

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

10965

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

10993

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

11009

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

11041

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

11072

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

11137

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

11153

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

11201

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

11217

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

11262

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

11278

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

11319

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

11335

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

11363

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

11379

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

11407

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

11423

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

11448

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

11477

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

11527

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

11543

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

11578

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

11635

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

11665

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

11690

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

11715

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

11731

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

11784

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

11800

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

11829

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

11851

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

11913

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

11949

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

11981

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

11997

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

12033

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

12049

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

12078

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

12094

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

12124

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

12140

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

12171

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

12187

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

12244

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

12273

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

12304

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

12328

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

12359

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

12391

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

12427

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

12452

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

12507

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

12523

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

12548

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

12596

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

12633

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

12659

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

12690

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

12706

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

12788

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

12804

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

12842

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

12861

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

12902

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

12921

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

12975

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

12991

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

13036

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

13061

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

13129

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

13145

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

13182

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

13215

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

13246

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

13262

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

13303

uint32_t unused1;

sys/dev/pci/if_bnxtreg.h

13309

uint32_t md_type_link_flags_kid_lo;

sys/dev/pci/if_bnxtreg.h

13443

uint32_t md_type_link_flags_kid_lo;

sys/dev/pci/if_bnxtreg.h

13596

uint32_t md_type_link_flags_kid_lo;

sys/dev/pci/if_bnxtreg.h

13705

uint32_t resync_record_tcp_seq_num;

sys/dev/pci/if_bnxtreg.h

13706

uint32_t unused0;

sys/dev/pci/if_bnxtreg.h

13716

uint32_t key_idx;

sys/dev/pci/if_bnxtreg.h

13740

uint32_t key_idx;

sys/dev/pci/if_bnxtreg.h

13764

uint32_t key_mask_valid_idx;

sys/dev/pci/if_bnxtreg.h

13801

uint32_t key_idx;

sys/dev/pci/if_bnxtreg.h

13828

uint32_t key_sz_idx;

sys/dev/pci/if_bnxtreg.h

13946

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

14063

uint32_t mss;

sys/dev/pci/if_bnxtreg.h

14085

uint32_t cfa_meta;

sys/dev/pci/if_bnxtreg.h

14136

uint32_t data[25];

sys/dev/pci/if_bnxtreg.h

14175

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

14276

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

14355

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

14430

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

14506

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

14630

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

14727

uint32_t num_ktls_tx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

14729

uint32_t num_ktls_rx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

14734

uint32_t num_quic_tx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

14736

uint32_t num_quic_rx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

14832

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

15092

uint32_t max_encap_records;

sys/dev/pci/if_bnxtreg.h

15097

uint32_t max_decap_records;

sys/dev/pci/if_bnxtreg.h

15102

uint32_t max_tx_em_flows;

sys/dev/pci/if_bnxtreg.h

15107

uint32_t max_tx_wm_flows;

sys/dev/pci/if_bnxtreg.h

15112

uint32_t max_rx_em_flows;

sys/dev/pci/if_bnxtreg.h

15117

uint32_t max_rx_wm_flows;

sys/dev/pci/if_bnxtreg.h

15122

uint32_t max_mcast_filters;

sys/dev/pci/if_bnxtreg.h

15127

uint32_t max_flow_id;

sys/dev/pci/if_bnxtreg.h

15132

uint32_t max_hw_ring_grps;

sys/dev/pci/if_bnxtreg.h

15149

uint32_t flags_ext;

sys/dev/pci/if_bnxtreg.h

15354

uint32_t flags_ext2;

sys/dev/pci/if_bnxtreg.h

15646

uint32_t roce_vf_max_av;

sys/dev/pci/if_bnxtreg.h

15653

uint32_t roce_vf_max_cq;

sys/dev/pci/if_bnxtreg.h

15660

uint32_t roce_vf_max_mrw;

sys/dev/pci/if_bnxtreg.h

15667

uint32_t roce_vf_max_qp;

sys/dev/pci/if_bnxtreg.h

15674

uint32_t roce_vf_max_srq;

sys/dev/pci/if_bnxtreg.h

15681

uint32_t roce_vf_max_gid;

sys/dev/pci/if_bnxtreg.h

15682

uint32_t flags_ext3;

sys/dev/pci/if_bnxtreg.h

15997

uint32_t min_bw;

sys/dev/pci/if_bnxtreg.h

16029

uint32_t max_bw;

sys/dev/pci/if_bnxtreg.h

16108

uint32_t alloc_mcast_filters;

sys/dev/pci/if_bnxtreg.h

16113

uint32_t alloc_hw_ring_grps;

sys/dev/pci/if_bnxtreg.h

16168

uint32_t reset_addr_poll;

sys/dev/pci/if_bnxtreg.h

16255

uint32_t partition_min_bw;

sys/dev/pci/if_bnxtreg.h

16284

uint32_t partition_max_bw;

sys/dev/pci/if_bnxtreg.h

16342

uint32_t num_ktls_tx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

16344

uint32_t num_ktls_rx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

16363

uint32_t num_quic_tx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

16365

uint32_t num_quic_rx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

16371

uint32_t roce_max_av_per_vf;

sys/dev/pci/if_bnxtreg.h

16376

uint32_t roce_max_cq_per_vf;

sys/dev/pci/if_bnxtreg.h

16382

uint32_t roce_max_mrw_per_vf;

sys/dev/pci/if_bnxtreg.h

16387

uint32_t roce_max_qp_per_vf;

sys/dev/pci/if_bnxtreg.h

16393

uint32_t roce_max_srq_per_vf;

sys/dev/pci/if_bnxtreg.h

16399

uint32_t roce_max_gid_per_vf;

sys/dev/pci/if_bnxtreg.h

16476

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

16672

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

16911

uint32_t dflt_ip_addr[4];

sys/dev/pci/if_bnxtreg.h

16917

uint32_t min_bw;

sys/dev/pci/if_bnxtreg.h

16949

uint32_t max_bw;

sys/dev/pci/if_bnxtreg.h

17146

uint32_t partition_min_bw;

sys/dev/pci/if_bnxtreg.h

17175

uint32_t partition_max_bw;

sys/dev/pci/if_bnxtreg.h

17220

uint32_t flags2;

sys/dev/pci/if_bnxtreg.h

17237

uint32_t enables2;

sys/dev/pci/if_bnxtreg.h

17340

uint32_t num_ktls_tx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

17342

uint32_t num_ktls_rx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

17344

uint32_t num_quic_tx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

17346

uint32_t num_quic_rx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

17348

uint32_t roce_max_av_per_vf;

sys/dev/pci/if_bnxtreg.h

17350

uint32_t roce_max_cq_per_vf;

sys/dev/pci/if_bnxtreg.h

17352

uint32_t roce_max_mrw_per_vf;

sys/dev/pci/if_bnxtreg.h

17354

uint32_t roce_max_qp_per_vf;

sys/dev/pci/if_bnxtreg.h

17356

uint32_t roce_max_srq_per_vf;

sys/dev/pci/if_bnxtreg.h

17358

uint32_t roce_max_gid_per_vf;

sys/dev/pci/if_bnxtreg.h

17640

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

17892

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

1797

uint32_t opaque_0;

sys/dev/pci/if_bnxtreg.h

18015

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

18081

uint32_t timestamp;

sys/dev/pci/if_bnxtreg.h

18095

uint32_t vf_req_fwd[8];

sys/dev/pci/if_bnxtreg.h

18111

uint32_t async_event_fwd[8];

sys/dev/pci/if_bnxtreg.h

18133

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

18186

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

1819

#define HWRM_NA_SIGNATURE ((uint32_t)(-1))

sys/dev/pci/if_bnxtreg.h

18253

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

18389

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

18462

uint32_t reserved;

sys/dev/pci/if_bnxtreg.h

18676

uint32_t min_ktls_tx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18678

uint32_t max_ktls_tx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18680

uint32_t min_ktls_rx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18682

uint32_t max_ktls_rx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18684

uint32_t min_quic_tx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18686

uint32_t max_quic_tx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18688

uint32_t min_quic_rx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18690

uint32_t max_quic_rx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18784

uint32_t min_ktls_tx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18786

uint32_t max_ktls_tx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18788

uint32_t min_ktls_rx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18790

uint32_t max_ktls_rx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18792

uint32_t min_quic_tx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18794

uint32_t max_quic_tx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18796

uint32_t min_quic_rx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18798

uint32_t max_quic_rx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18829

uint32_t reserved_ktls_tx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18831

uint32_t reserved_ktls_rx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18833

uint32_t reserved_quic_tx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18835

uint32_t reserved_quic_rx_key_ctxs;

sys/dev/pci/if_bnxtreg.h

18897

uint32_t qp_max_entries;

sys/dev/pci/if_bnxtreg.h

18914

uint32_t srq_max_entries;

sys/dev/pci/if_bnxtreg.h

18920

uint32_t cq_max_entries;

sys/dev/pci/if_bnxtreg.h

18936

uint32_t stat_max_entries;

sys/dev/pci/if_bnxtreg.h

18942

uint32_t tqm_min_entries_per_ring;

sys/dev/pci/if_bnxtreg.h

18969

uint32_t tqm_max_entries_per_ring;

sys/dev/pci/if_bnxtreg.h

18974

uint32_t mrav_max_entries;

sys/dev/pci/if_bnxtreg.h

18980

uint32_t tim_max_entries;

sys/dev/pci/if_bnxtreg.h

19117

uint32_t tkc_max_entries;

sys/dev/pci/if_bnxtreg.h

19122

uint32_t rkc_max_entries;

sys/dev/pci/if_bnxtreg.h

19176

uint32_t tqm_ring_num_entries;

sys/dev/pci/if_bnxtreg.h

19217

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

19230

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

19870

uint32_t qp_num_entries;

sys/dev/pci/if_bnxtreg.h

19872

uint32_t srq_num_entries;

sys/dev/pci/if_bnxtreg.h

19874

uint32_t cq_num_entries;

sys/dev/pci/if_bnxtreg.h

19876

uint32_t stat_num_entries;

sys/dev/pci/if_bnxtreg.h

19896

uint32_t tqm_sp_num_entries;

sys/dev/pci/if_bnxtreg.h

19909

uint32_t tqm_ring0_num_entries;

sys/dev/pci/if_bnxtreg.h

19922

uint32_t tqm_ring1_num_entries;

sys/dev/pci/if_bnxtreg.h

19935

uint32_t tqm_ring2_num_entries;

sys/dev/pci/if_bnxtreg.h

19948

uint32_t tqm_ring3_num_entries;

sys/dev/pci/if_bnxtreg.h

19961

uint32_t tqm_ring4_num_entries;

sys/dev/pci/if_bnxtreg.h

19974

uint32_t tqm_ring5_num_entries;

sys/dev/pci/if_bnxtreg.h

19987

uint32_t tqm_ring6_num_entries;

sys/dev/pci/if_bnxtreg.h

20000

uint32_t tqm_ring7_num_entries;

sys/dev/pci/if_bnxtreg.h

20015

uint32_t mrav_num_entries;

sys/dev/pci/if_bnxtreg.h

20017

uint32_t tim_num_entries;

sys/dev/pci/if_bnxtreg.h

20079

uint32_t tqm_ring8_num_entries;

sys/dev/pci/if_bnxtreg.h

20115

uint32_t tqm_ring9_num_entries;

sys/dev/pci/if_bnxtreg.h

20151

uint32_t tqm_ring10_num_entries;

sys/dev/pci/if_bnxtreg.h

20155

uint32_t tkc_num_entries;

sys/dev/pci/if_bnxtreg.h

20157

uint32_t rkc_num_entries;

sys/dev/pci/if_bnxtreg.h

20306

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

20319

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

2041

uint32_t dev_caps_cfg;

sys/dev/pci/if_bnxtreg.h

20963

uint32_t qp_num_entries;

sys/dev/pci/if_bnxtreg.h

20965

uint32_t srq_num_entries;

sys/dev/pci/if_bnxtreg.h

20971

uint32_t cq_num_entries;

sys/dev/pci/if_bnxtreg.h

20977

uint32_t stat_num_entries;

sys/dev/pci/if_bnxtreg.h

20979

uint32_t tqm_sp_num_entries;

sys/dev/pci/if_bnxtreg.h

20981

uint32_t tqm_ring0_num_entries;

sys/dev/pci/if_bnxtreg.h

20983

uint32_t tqm_ring1_num_entries;

sys/dev/pci/if_bnxtreg.h

20985

uint32_t tqm_ring2_num_entries;

sys/dev/pci/if_bnxtreg.h

20987

uint32_t tqm_ring3_num_entries;

sys/dev/pci/if_bnxtreg.h

20989

uint32_t tqm_ring4_num_entries;

sys/dev/pci/if_bnxtreg.h

20991

uint32_t tqm_ring5_num_entries;

sys/dev/pci/if_bnxtreg.h

20993

uint32_t tqm_ring6_num_entries;

sys/dev/pci/if_bnxtreg.h

20995

uint32_t tqm_ring7_num_entries;

sys/dev/pci/if_bnxtreg.h

21010

uint32_t mrav_num_entries;

sys/dev/pci/if_bnxtreg.h

21012

uint32_t tim_num_entries;

sys/dev/pci/if_bnxtreg.h

21046

uint32_t tqm_ring8_num_entries;

sys/dev/pci/if_bnxtreg.h

21082

uint32_t tqm_ring9_num_entries;

sys/dev/pci/if_bnxtreg.h

21118

uint32_t tqm_ring10_num_entries;

sys/dev/pci/if_bnxtreg.h

21122

uint32_t tkc_num_entries;

sys/dev/pci/if_bnxtreg.h

21124

uint32_t rkc_num_entries;

sys/dev/pci/if_bnxtreg.h

21258

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

21275

uint32_t driver_polling_freq;

sys/dev/pci/if_bnxtreg.h

21283

uint32_t master_func_wait_period;

sys/dev/pci/if_bnxtreg.h

21291

uint32_t normal_func_wait_period;

sys/dev/pci/if_bnxtreg.h

21299

uint32_t master_func_wait_period_after_reset;

sys/dev/pci/if_bnxtreg.h

21307

uint32_t max_bailout_time_after_reset;

sys/dev/pci/if_bnxtreg.h

21314

uint32_t fw_health_status_reg;

sys/dev/pci/if_bnxtreg.h

21353

uint32_t fw_heartbeat_reg;

sys/dev/pci/if_bnxtreg.h

21391

uint32_t fw_reset_cnt_reg;

sys/dev/pci/if_bnxtreg.h

21429

uint32_t reset_inprogress_reg;

sys/dev/pci/if_bnxtreg.h

21462

uint32_t reset_inprogress_reg_mask;

sys/dev/pci/if_bnxtreg.h

21479

uint32_t reset_reg[16];

sys/dev/pci/if_bnxtreg.h

21512

uint32_t reset_reg_val[16];

sys/dev/pci/if_bnxtreg.h

21528

uint32_t err_recovery_cnt_reg;

sys/dev/pci/if_bnxtreg.h

21608

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

21609

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

21818

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

22102

uint32_t ptp_freq_adj_ext_period;

sys/dev/pci/if_bnxtreg.h

22108

uint32_t ptp_freq_adj_ext_up;

sys/dev/pci/if_bnxtreg.h

22118

uint32_t ptp_freq_adj_ext_phase_lower;

sys/dev/pci/if_bnxtreg.h

22124

uint32_t ptp_freq_adj_ext_phase_upper;

sys/dev/pci/if_bnxtreg.h

22192

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

22231

uint32_t ptm_link_delay;

sys/dev/pci/if_bnxtreg.h

22361

uint32_t failover_timer;

sys/dev/pci/if_bnxtreg.h

22462

uint32_t last_failover_event;

sys/dev/pci/if_bnxtreg.h

22527

uint32_t rate;

sys/dev/pci/if_bnxtreg.h

22681

uint32_t rates[128];

sys/dev/pci/if_bnxtreg.h

22751

uint32_t dma_bufr_size_bytes;

sys/dev/pci/if_bnxtreg.h

22777

uint32_t partition_start_xid;

sys/dev/pci/if_bnxtreg.h

22810

uint32_t partition_start_xid;

sys/dev/pci/if_bnxtreg.h

22873

uint32_t partition_start_xid;

sys/dev/pci/if_bnxtreg.h

23027

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

23061

uint32_t num_entries;

sys/dev/pci/if_bnxtreg.h

23122

uint32_t split_entry_0;

sys/dev/pci/if_bnxtreg.h

23124

uint32_t split_entry_1;

sys/dev/pci/if_bnxtreg.h

23126

uint32_t split_entry_2;

sys/dev/pci/if_bnxtreg.h

23128

uint32_t split_entry_3;

sys/dev/pci/if_bnxtreg.h

23129

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

23142

uint32_t next_bs_offset;

sys/dev/pci/if_bnxtreg.h

23371

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

23375

uint32_t num_entries;

sys/dev/pci/if_bnxtreg.h

23435

uint32_t split_entry_0;

sys/dev/pci/if_bnxtreg.h

23437

uint32_t split_entry_1;

sys/dev/pci/if_bnxtreg.h

23439

uint32_t split_entry_2;

sys/dev/pci/if_bnxtreg.h

23441

uint32_t split_entry_3;

sys/dev/pci/if_bnxtreg.h

23459

uint32_t qp_num_l2_entries;

sys/dev/pci/if_bnxtreg.h

23461

uint32_t qp_num_qp1_entries;

sys/dev/pci/if_bnxtreg.h

23466

uint32_t qp_num_fast_qpmd_entries;

sys/dev/pci/if_bnxtreg.h

23467

uint32_t rsvd;

sys/dev/pci/if_bnxtreg.h

23475

uint32_t srq_num_l2_entries;

sys/dev/pci/if_bnxtreg.h

23476

uint32_t rsvd;

sys/dev/pci/if_bnxtreg.h

23485

uint32_t cq_num_l2_entries;

sys/dev/pci/if_bnxtreg.h

23486

uint32_t rsvd;

sys/dev/pci/if_bnxtreg.h

23495

uint32_t vnic_num_vnic_entries;

sys/dev/pci/if_bnxtreg.h

23496

uint32_t rsvd;

sys/dev/pci/if_bnxtreg.h

23505

uint32_t mrav_num_av_entries;

sys/dev/pci/if_bnxtreg.h

23506

uint32_t rsvd;

sys/dev/pci/if_bnxtreg.h

23515

uint32_t region_num_entries;

sys/dev/pci/if_bnxtreg.h

23536

uint32_t num_quic_entries;

sys/dev/pci/if_bnxtreg.h

23537

uint32_t rsvd;

sys/dev/pci/if_bnxtreg.h

23724

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

23773

uint32_t instance_bit_map;

sys/dev/pci/if_bnxtreg.h

23794

uint32_t max_num_entries;

sys/dev/pci/if_bnxtreg.h

23800

uint32_t min_num_entries;

sys/dev/pci/if_bnxtreg.h

23863

uint32_t split_entry_0;

sys/dev/pci/if_bnxtreg.h

23865

uint32_t split_entry_1;

sys/dev/pci/if_bnxtreg.h

23867

uint32_t split_entry_2;

sys/dev/pci/if_bnxtreg.h

23869

uint32_t split_entry_3;

sys/dev/pci/if_bnxtreg.h

23928

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

23943

uint32_t primary_nq_id;

sys/dev/pci/if_bnxtreg.h

23948

uint32_t pacing_threshold;

sys/dev/pci/if_bnxtreg.h

24035

uint32_t dbr_stat_db_fifo_reg;

sys/dev/pci/if_bnxtreg.h

24072

uint32_t dbr_stat_db_fifo_reg_watermark_mask;

sys/dev/pci/if_bnxtreg.h

24083

uint32_t dbr_stat_db_fifo_reg_fifo_room_mask;

sys/dev/pci/if_bnxtreg.h

24099

uint32_t dbr_throttling_aeq_arm_reg;

sys/dev/pci/if_bnxtreg.h

24139

uint32_t dbr_stat_db_max_fifo_depth;

sys/dev/pci/if_bnxtreg.h

24144

uint32_t primary_nq_id;

sys/dev/pci/if_bnxtreg.h

24149

uint32_t pacing_threshold;

sys/dev/pci/if_bnxtreg.h

24305

uint32_t num_nqs;

sys/dev/pci/if_bnxtreg.h

24358

uint32_t epoch;

sys/dev/pci/if_bnxtreg.h

2471

uint32_t table_index;

sys/dev/pci/if_bnxtreg.h

2521

uint32_t table_index;

sys/dev/pci/if_bnxtreg.h

2524

uint32_t unused0;

sys/dev/pci/if_bnxtreg.h

2525

uint32_t unused1;

sys/dev/pci/if_bnxtreg.h

2532

uint32_t dta[32];

sys/dev/pci/if_bnxtreg.h

25456

uint32_t rsvd2;

sys/dev/pci/if_bnxtreg.h

25458

uint32_t rsvd3;

sys/dev/pci/if_bnxtreg.h

25514

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

25566

uint32_t rsvd1;

sys/dev/pci/if_bnxtreg.h

25568

uint32_t rsvd2;

sys/dev/pci/if_bnxtreg.h

25637

uint32_t max_vnic_id_cnt;

sys/dev/pci/if_bnxtreg.h

25658

uint32_t vnic_id_cnt;

sys/dev/pci/if_bnxtreg.h

2569

uint32_t table_index;

sys/dev/pci/if_bnxtreg.h

25939

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

25954

uint32_t unused;

sys/dev/pci/if_bnxtreg.h

25968

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

26229

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

2625

uint32_t table_index;

sys/dev/pci/if_bnxtreg.h

26254

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

26325

uint32_t hash_type;

sys/dev/pci/if_bnxtreg.h

2637

uint32_t dta[32];

sys/dev/pci/if_bnxtreg.h

26439

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

26455

uint32_t hash_type;

sys/dev/pci/if_bnxtreg.h

26493

uint32_t hash_key[10];

sys/dev/pci/if_bnxtreg.h

26586

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

2671

uint32_t unused0;

sys/dev/pci/if_bnxtreg.h

26831

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

27143

uint32_t preemphasis;

sys/dev/pci/if_bnxtreg.h

2715

uint32_t table_index;

sys/dev/pci/if_bnxtreg.h

27186

uint32_t tx_lpi_timer;

sys/dev/pci/if_bnxtreg.h

2741

uint32_t unused1;

sys/dev/pci/if_bnxtreg.h

2752

uint32_t version_algorithm_kid_opcode;

sys/dev/pci/if_bnxtreg.h

27720

uint32_t preemphasis;

sys/dev/pci/if_bnxtreg.h

28047

uint32_t xcvr_identifier_type_tx_lpi_timer;

sys/dev/pci/if_bnxtreg.h

2825

uint32_t pkt_tcp_seq_num;

sys/dev/pci/if_bnxtreg.h

2833

uint32_t tls_header_tcp_seq_num;

sys/dev/pci/if_bnxtreg.h

28464

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

28554

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

2860

uint32_t kid_opcode_ctx_kind;

sys/dev/pci/if_bnxtreg.h

2901

uint32_t resync_status_kid_opcode;

sys/dev/pci/if_bnxtreg.h

29253

uint32_t rx_ts_reg_off_lower;

sys/dev/pci/if_bnxtreg.h

29258

uint32_t rx_ts_reg_off_upper;

sys/dev/pci/if_bnxtreg.h

29260

uint32_t rx_ts_reg_off_seq_id;

sys/dev/pci/if_bnxtreg.h

29262

uint32_t rx_ts_reg_off_src_id_0;

sys/dev/pci/if_bnxtreg.h

29264

uint32_t rx_ts_reg_off_src_id_1;

sys/dev/pci/if_bnxtreg.h

29266

uint32_t rx_ts_reg_off_src_id_2;

sys/dev/pci/if_bnxtreg.h

29268

uint32_t rx_ts_reg_off_domain_id;

sys/dev/pci/if_bnxtreg.h

29270

uint32_t rx_ts_reg_off_fifo;

sys/dev/pci/if_bnxtreg.h

29272

uint32_t rx_ts_reg_off_fifo_adv;

sys/dev/pci/if_bnxtreg.h

29274

uint32_t rx_ts_reg_off_granularity;

sys/dev/pci/if_bnxtreg.h

29279

uint32_t tx_ts_reg_off_lower;

sys/dev/pci/if_bnxtreg.h

29284

uint32_t tx_ts_reg_off_upper;

sys/dev/pci/if_bnxtreg.h

29286

uint32_t tx_ts_reg_off_seq_id;

sys/dev/pci/if_bnxtreg.h

29288

uint32_t tx_ts_reg_off_fifo;

sys/dev/pci/if_bnxtreg.h

29290

uint32_t tx_ts_reg_off_granularity;

sys/dev/pci/if_bnxtreg.h

29292

uint32_t ts_ref_clock_reg_lower;

sys/dev/pci/if_bnxtreg.h

29294

uint32_t ts_ref_clock_reg_upper;

sys/dev/pci/if_bnxtreg.h

2938

uint32_t resync_record_tcp_seq_num;

sys/dev/pci/if_bnxtreg.h

2951

uint32_t resync_status_kid_opcode;

sys/dev/pci/if_bnxtreg.h

2988

uint32_t resync_record_tcp_seq_num;

sys/dev/pci/if_bnxtreg.h

3037

uint32_t header_tcp_seq_num;

sys/dev/pci/if_bnxtreg.h

3048

uint32_t start_tcp_seq_num;

sys/dev/pci/if_bnxtreg.h

3060

uint32_t end_tcp_seq_num;

sys/dev/pci/if_bnxtreg.h

3089

uint32_t ver_algo_kid_opcode;

sys/dev/pci/if_bnxtreg.h

31094

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

31146

uint32_t ptp_seq_id;

sys/dev/pci/if_bnxtreg.h

3133

uint32_t ctx_kind_dcid_width_key_phase;

sys/dev/pci/if_bnxtreg.h

31398

uint32_t tx_lpi_timer_low;

sys/dev/pci/if_bnxtreg.h

31412

uint32_t valid_tx_lpi_timer_high;

sys/dev/pci/if_bnxtreg.h

31598

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

31599

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

3160

uint32_t unused_1;

sys/dev/pci/if_bnxtreg.h

31628

uint32_t data[16];

sys/dev/pci/if_bnxtreg.h

31689

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

31690

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

31732

uint32_t data[16];

sys/dev/pci/if_bnxtreg.h

31938

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

32961

uint32_t unused_1;

sys/dev/pci/if_bnxtreg.h

33029

uint32_t tx_lane_map;

sys/dev/pci/if_bnxtreg.h

33035

uint32_t rx_lane_map;

sys/dev/pci/if_bnxtreg.h

33122

uint32_t data_offset;

sys/dev/pci/if_bnxtreg.h

33301

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

33324

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

3340

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

33443

uint32_t supported_mask;

sys/dev/pci/if_bnxtreg.h

33444

uint32_t sideband_signals;

sys/dev/pci/if_bnxtreg.h

33714

uint32_t txfir_val_1;

sys/dev/pci/if_bnxtreg.h

33716

uint32_t txfir_val_2;

sys/dev/pci/if_bnxtreg.h

33718

uint32_t txfir_val_3;

sys/dev/pci/if_bnxtreg.h

33720

uint32_t txfir_val_4;

sys/dev/pci/if_bnxtreg.h

33816

uint32_t txfir_val_1;

sys/dev/pci/if_bnxtreg.h

33818

uint32_t txfir_val_2;

sys/dev/pci/if_bnxtreg.h

33820

uint32_t txfir_val_3;

sys/dev/pci/if_bnxtreg.h

33822

uint32_t txfir_val_4;

sys/dev/pci/if_bnxtreg.h

34176

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

34177

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

34192

uint32_t tx_rate_limit;

sys/dev/pci/if_bnxtreg.h

34269

uint32_t supported;

sys/dev/pci/if_bnxtreg.h

34275

uint32_t enabled;

sys/dev/pci/if_bnxtreg.h

34286

uint32_t tx_rate_limit;

sys/dev/pci/if_bnxtreg.h

3453

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

34543

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

35085

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

35098

uint32_t queue_id;

sys/dev/pci/if_bnxtreg.h

35116

uint32_t queue_len;

sys/dev/pci/if_bnxtreg.h

35182

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

35197

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

35209

uint32_t queue_id;

sys/dev/pci/if_bnxtreg.h

35215

uint32_t dflt_len;

sys/dev/pci/if_bnxtreg.h

35306

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

35386

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

35486

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

35637

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

35659

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

35836

uint32_t queue_id0_min_bw;

sys/dev/pci/if_bnxtreg.h

35868

uint32_t queue_id0_max_bw;

sys/dev/pci/if_bnxtreg.h

35924

uint32_t queue_id1_min_bw;

sys/dev/pci/if_bnxtreg.h

35956

uint32_t queue_id1_max_bw;

sys/dev/pci/if_bnxtreg.h

36012

uint32_t queue_id2_min_bw;

sys/dev/pci/if_bnxtreg.h

36044

uint32_t queue_id2_max_bw;

sys/dev/pci/if_bnxtreg.h

36100

uint32_t queue_id3_min_bw;

sys/dev/pci/if_bnxtreg.h

36132

uint32_t queue_id3_max_bw;

sys/dev/pci/if_bnxtreg.h

36188

uint32_t queue_id4_min_bw;

sys/dev/pci/if_bnxtreg.h

36220

uint32_t queue_id4_max_bw;

sys/dev/pci/if_bnxtreg.h

36276

uint32_t queue_id5_min_bw;

sys/dev/pci/if_bnxtreg.h

36308

uint32_t queue_id5_max_bw;

sys/dev/pci/if_bnxtreg.h

36364

uint32_t queue_id6_min_bw;

sys/dev/pci/if_bnxtreg.h

36396

uint32_t queue_id6_max_bw;

sys/dev/pci/if_bnxtreg.h

36452

uint32_t queue_id7_min_bw;

sys/dev/pci/if_bnxtreg.h

36484

uint32_t queue_id7_max_bw;

sys/dev/pci/if_bnxtreg.h

36580

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

36581

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

3663

uint32_t kid_or_ts_high_mss;

sys/dev/pci/if_bnxtreg.h

36636

uint32_t queue_id0_min_bw;

sys/dev/pci/if_bnxtreg.h

36668

uint32_t queue_id0_max_bw;

sys/dev/pci/if_bnxtreg.h

36724

uint32_t queue_id1_min_bw;

sys/dev/pci/if_bnxtreg.h

36756

uint32_t queue_id1_max_bw;

sys/dev/pci/if_bnxtreg.h

36812

uint32_t queue_id2_min_bw;

sys/dev/pci/if_bnxtreg.h

36844

uint32_t queue_id2_max_bw;

sys/dev/pci/if_bnxtreg.h

36900

uint32_t queue_id3_min_bw;

sys/dev/pci/if_bnxtreg.h

36932

uint32_t queue_id3_max_bw;

sys/dev/pci/if_bnxtreg.h

36988

uint32_t queue_id4_min_bw;

sys/dev/pci/if_bnxtreg.h

37020

uint32_t queue_id4_max_bw;

sys/dev/pci/if_bnxtreg.h

3703

uint32_t cfa_meta;

sys/dev/pci/if_bnxtreg.h

37076

uint32_t queue_id5_min_bw;

sys/dev/pci/if_bnxtreg.h

37108

uint32_t queue_id5_max_bw;

sys/dev/pci/if_bnxtreg.h

37164

uint32_t queue_id6_min_bw;

sys/dev/pci/if_bnxtreg.h

37196

uint32_t queue_id6_max_bw;

sys/dev/pci/if_bnxtreg.h

37252

uint32_t queue_id7_min_bw;

sys/dev/pci/if_bnxtreg.h

37284

uint32_t queue_id7_max_bw;

sys/dev/pci/if_bnxtreg.h

37560

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

37563

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

37854

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

38189

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

3847

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

38491

uint32_t buffer_pool_id0_size;

sys/dev/pci/if_bnxtreg.h

38493

uint32_t buffer_pool_id1_size;

sys/dev/pci/if_bnxtreg.h

38495

uint32_t buffer_pool_id2_size;

sys/dev/pci/if_bnxtreg.h

38497

uint32_t buffer_pool_id3_size;

sys/dev/pci/if_bnxtreg.h

38802

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

39123

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

39266

uint32_t rx_feature_params;

sys/dev/pci/if_bnxtreg.h

39282

uint32_t tx_feature_params;

sys/dev/pci/if_bnxtreg.h

39297

uint32_t rx_tuning_params;

sys/dev/pci/if_bnxtreg.h

39397

uint32_t tx_tuning_params;

sys/dev/pci/if_bnxtreg.h

39529

uint32_t wfq_cost;

sys/dev/pci/if_bnxtreg.h

39534

uint32_t wfq_upper_factor;

sys/dev/pci/if_bnxtreg.h

39540

uint32_t hyst_window_size_factor;

sys/dev/pci/if_bnxtreg.h

39548

uint32_t pcie_bw_eff;

sys/dev/pci/if_bnxtreg.h

39550

uint32_t xoff_headroom_factor;

sys/dev/pci/if_bnxtreg.h

39556

uint32_t l2_min_latency;

sys/dev/pci/if_bnxtreg.h

39562

uint32_t l2_max_latency;

sys/dev/pci/if_bnxtreg.h

39568

uint32_t roce_min_latency;

sys/dev/pci/if_bnxtreg.h

39574

uint32_t roce_max_latency;

sys/dev/pci/if_bnxtreg.h

39581

uint32_t l2_pipe_cos_latency;

sys/dev/pci/if_bnxtreg.h

39588

uint32_t roce_pipe_cos_latency;

sys/dev/pci/if_bnxtreg.h

39590

uint32_t cos_shared_min_ratio;

sys/dev/pci/if_bnxtreg.h

39597

uint32_t rsvd_cells_limit_ratio;

sys/dev/pci/if_bnxtreg.h

39602

uint32_t shaper_refill_timer;

sys/dev/pci/if_bnxtreg.h

39650

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

39680

uint32_t wfq_cost;

sys/dev/pci/if_bnxtreg.h

39685

uint32_t wfq_upper_factor;

sys/dev/pci/if_bnxtreg.h

39691

uint32_t hyst_window_size_factor;

sys/dev/pci/if_bnxtreg.h

39699

uint32_t pcie_bw_eff;

sys/dev/pci/if_bnxtreg.h

39701

uint32_t xoff_headroom_factor;

sys/dev/pci/if_bnxtreg.h

39707

uint32_t l2_min_latency;

sys/dev/pci/if_bnxtreg.h

39713

uint32_t l2_max_latency;

sys/dev/pci/if_bnxtreg.h

39719

uint32_t roce_min_latency;

sys/dev/pci/if_bnxtreg.h

39725

uint32_t roce_max_latency;

sys/dev/pci/if_bnxtreg.h

39732

uint32_t l2_pipe_cos_latency;

sys/dev/pci/if_bnxtreg.h

39739

uint32_t roce_pipe_cos_latency;

sys/dev/pci/if_bnxtreg.h

39741

uint32_t cos_shared_min_ratio;

sys/dev/pci/if_bnxtreg.h

39748

uint32_t rsvd_cells_limit_ratio;

sys/dev/pci/if_bnxtreg.h

39753

uint32_t shaper_refill_timer;

sys/dev/pci/if_bnxtreg.h

3976

uint32_t kid_or_ts_high;

sys/dev/pci/if_bnxtreg.h

39829

uint32_t wfq_cost;

sys/dev/pci/if_bnxtreg.h

39834

uint32_t wfq_upper_factor;

sys/dev/pci/if_bnxtreg.h

39840

uint32_t hyst_window_size_factor;

sys/dev/pci/if_bnxtreg.h

39847

uint32_t rsvd_cells_limit_ratio;

sys/dev/pci/if_bnxtreg.h

39853

uint32_t l2_min_latency;

sys/dev/pci/if_bnxtreg.h

39859

uint32_t l2_max_latency;

sys/dev/pci/if_bnxtreg.h

39865

uint32_t roce_min_latency;

sys/dev/pci/if_bnxtreg.h

39871

uint32_t roce_max_latency;

sys/dev/pci/if_bnxtreg.h

39873

uint32_t max_tbm_cells_prereserved;

sys/dev/pci/if_bnxtreg.h

39878

uint32_t shaper_refill_timer;

sys/dev/pci/if_bnxtreg.h

39926

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

39948

uint32_t wfq_cost;

sys/dev/pci/if_bnxtreg.h

39953

uint32_t wfq_upper_factor;

sys/dev/pci/if_bnxtreg.h

39959

uint32_t hyst_window_size_factor;

sys/dev/pci/if_bnxtreg.h

39966

uint32_t rsvd_cells_limit_ratio;

sys/dev/pci/if_bnxtreg.h

39972

uint32_t l2_min_latency;

sys/dev/pci/if_bnxtreg.h

39978

uint32_t l2_max_latency;

sys/dev/pci/if_bnxtreg.h

39984

uint32_t roce_min_latency;

sys/dev/pci/if_bnxtreg.h

39990

uint32_t roce_max_latency;

sys/dev/pci/if_bnxtreg.h

39992

uint32_t max_tbm_cells_prereserved;

sys/dev/pci/if_bnxtreg.h

39997

uint32_t shaper_refill_timer;

sys/dev/pci/if_bnxtreg.h

4009

uint32_t cfa_meta;

sys/dev/pci/if_bnxtreg.h

40256

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

40289

uint32_t vnic_id;

sys/dev/pci/if_bnxtreg.h

40338

uint32_t vnic_id;

sys/dev/pci/if_bnxtreg.h

40339

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

40451

uint32_t vnic_id;

sys/dev/pci/if_bnxtreg.h

40513

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

40581

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

40807

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

40814

uint32_t vnic_id;

sys/dev/pci/if_bnxtreg.h

40851

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

41040

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

41058

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

4124

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

41310

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

41375

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

41444

uint32_t max_agg_timer;

sys/dev/pci/if_bnxtreg.h

41451

uint32_t min_agg_len;

sys/dev/pci/if_bnxtreg.h

41459

uint32_t tnl_tpa_en_bitmap;

sys/dev/pci/if_bnxtreg.h

41622

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

4168

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

41717

uint32_t max_agg_timer;

sys/dev/pci/if_bnxtreg.h

41722

uint32_t min_agg_len;

sys/dev/pci/if_bnxtreg.h

41730

uint32_t tnl_tpa_en_bitmap;

sys/dev/pci/if_bnxtreg.h

4174

uint32_t kid;

sys/dev/pci/if_bnxtreg.h

4182

uint32_t unused_1;

sys/dev/pci/if_bnxtreg.h

41863

uint32_t hash_type;

sys/dev/pci/if_bnxtreg.h

42164

uint32_t hash_type;

sys/dev/pci/if_bnxtreg.h

42241

uint32_t hash_key[10];

sys/dev/pci/if_bnxtreg.h

42364

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

42423

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

42445

uint32_t vnic_id;

sys/dev/pci/if_bnxtreg.h

42548

uint32_t vnic_id;

sys/dev/pci/if_bnxtreg.h

4256

uint32_t rate;

sys/dev/pci/if_bnxtreg.h

42563

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

42817

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

42965

uint32_t fbo;

sys/dev/pci/if_bnxtreg.h

43002

uint32_t length;

sys/dev/pci/if_bnxtreg.h

43082

uint32_t reserved3;

sys/dev/pci/if_bnxtreg.h

43088

uint32_t stat_ctx_id;

sys/dev/pci/if_bnxtreg.h

43093

uint32_t reserved4;

sys/dev/pci/if_bnxtreg.h

43100

uint32_t max_bw;

sys/dev/pci/if_bnxtreg.h

43295

uint32_t prod_idx;

sys/dev/pci/if_bnxtreg.h

43300

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

43301

uint32_t unused_1;

sys/dev/pci/if_bnxtreg.h

4341

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

43551

uint32_t tx_metadata;

sys/dev/pci/if_bnxtreg.h

43705

uint32_t tx_metadata;

sys/dev/pci/if_bnxtreg.h

43767

uint32_t cmpl_params;

sys/dev/pci/if_bnxtreg.h

4379

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

43813

uint32_t nq_params;

sys/dev/pci/if_bnxtreg.h

44201

uint32_t ring_group_id;

sys/dev/pci/if_bnxtreg.h

44250

uint32_t ring_group_id;

sys/dev/pci/if_bnxtreg.h

4431

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

44312

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

44354

uint32_t reserved;

sys/dev/pci/if_bnxtreg.h

4446

uint32_t mp_client_dma_length_opcode_status_type;

sys/dev/pci/if_bnxtreg.h

44630

uint32_t tqm_ring0_num_entries;

sys/dev/pci/if_bnxtreg.h

44642

uint32_t tqm_ring1_num_entries;

sys/dev/pci/if_bnxtreg.h

44654

uint32_t tqm_ring2_num_entries;

sys/dev/pci/if_bnxtreg.h

44666

uint32_t tqm_ring3_num_entries;

sys/dev/pci/if_bnxtreg.h

44678

uint32_t tqm_ring4_num_entries;

sys/dev/pci/if_bnxtreg.h

44690

uint32_t tqm_ring5_num_entries;

sys/dev/pci/if_bnxtreg.h

44702

uint32_t tqm_ring6_num_entries;

sys/dev/pci/if_bnxtreg.h

44714

uint32_t tqm_ring7_num_entries;

sys/dev/pci/if_bnxtreg.h

44796

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

44802

uint32_t max_bw_tc0;

sys/dev/pci/if_bnxtreg.h

44804

uint32_t max_bw_tc1;

sys/dev/pci/if_bnxtreg.h

44806

uint32_t max_bw_tc2;

sys/dev/pci/if_bnxtreg.h

44808

uint32_t max_bw_tc3;

sys/dev/pci/if_bnxtreg.h

44810

uint32_t max_bw_tc4;

sys/dev/pci/if_bnxtreg.h

44812

uint32_t max_bw_tc5;

sys/dev/pci/if_bnxtreg.h

44814

uint32_t max_bw_tc6;

sys/dev/pci/if_bnxtreg.h

44816

uint32_t max_bw_tc7;

sys/dev/pci/if_bnxtreg.h

44823

uint32_t tc_bw_reservation0;

sys/dev/pci/if_bnxtreg.h

44830

uint32_t tc_bw_reservation1;

sys/dev/pci/if_bnxtreg.h

44837

uint32_t tc_bw_reservation2;

sys/dev/pci/if_bnxtreg.h

44844

uint32_t tc_bw_reservation3;

sys/dev/pci/if_bnxtreg.h

44851

uint32_t tc_bw_reservation4;

sys/dev/pci/if_bnxtreg.h

44858

uint32_t tc_bw_reservation5;

sys/dev/pci/if_bnxtreg.h

44865

uint32_t tc_bw_reservation6;

sys/dev/pci/if_bnxtreg.h

44872

uint32_t tc_bw_reservation7;

sys/dev/pci/if_bnxtreg.h

44877

uint32_t max_bw;

sys/dev/pci/if_bnxtreg.h

45023

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

45079

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

45274

uint32_t src_id;

sys/dev/pci/if_bnxtreg.h

45344

uint32_t unused_6;

sys/dev/pci/if_bnxtreg.h

45379

uint32_t flow_id;

sys/dev/pci/if_bnxtreg.h

45517

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

45565

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

45597

uint32_t dst_id;

sys/dev/pci/if_bnxtreg.h

45602

uint32_t new_mirror_vnic_id;

sys/dev/pci/if_bnxtreg.h

45610

uint32_t prof_func;

sys/dev/pci/if_bnxtreg.h

45618

uint32_t l2_context_id;

sys/dev/pci/if_bnxtreg.h

4565

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

45681

uint32_t vnic_id;

sys/dev/pci/if_bnxtreg.h

45682

uint32_t mask;

sys/dev/pci/if_bnxtreg.h

45781

uint32_t num_mc_entries;

sys/dev/pci/if_bnxtreg.h

45794

uint32_t num_vlan_tags;

sys/dev/pci/if_bnxtreg.h

45880

uint32_t num_vlan_entries;

sys/dev/pci/if_bnxtreg.h

4596

uint32_t table_index;

sys/dev/pci/if_bnxtreg.h

45961

uint32_t max_vlan_entries;

sys/dev/pci/if_bnxtreg.h

45985

uint32_t num_vlan_entries;

sys/dev/pci/if_bnxtreg.h

46034

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

46040

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

4611

uint32_t dta[8];

sys/dev/pci/if_bnxtreg.h

46117

uint32_t l3_addr[4];

sys/dev/pci/if_bnxtreg.h

46122

uint32_t t_l3_addr[4];

sys/dev/pci/if_bnxtreg.h

4619

uint32_t dta[16];

sys/dev/pci/if_bnxtreg.h

46217

uint32_t vni;

sys/dev/pci/if_bnxtreg.h

46219

uint32_t dst_vnic_id;

sys/dev/pci/if_bnxtreg.h

46224

uint32_t mirror_vnic_id;

sys/dev/pci/if_bnxtreg.h

46247

uint32_t flow_id;

sys/dev/pci/if_bnxtreg.h

4627

uint32_t dta[24];

sys/dev/pci/if_bnxtreg.h

4635

uint32_t dta[32];

sys/dev/pci/if_bnxtreg.h

46686

uint32_t src_ip_addr;

sys/dev/pci/if_bnxtreg.h

46688

uint32_t dest_ip_addr;

sys/dev/pci/if_bnxtreg.h

46695

uint32_t ver_tc_flow_label;

sys/dev/pci/if_bnxtreg.h

46716

uint32_t src_ip_addr[4];

sys/dev/pci/if_bnxtreg.h

46718

uint32_t dest_ip_addr[4];

sys/dev/pci/if_bnxtreg.h

46743

uint32_t l3[10];

sys/dev/pci/if_bnxtreg.h

46756

uint32_t vni;

sys/dev/pci/if_bnxtreg.h

46805

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

46854

uint32_t encap_data[20];

sys/dev/pci/if_bnxtreg.h

46869

uint32_t encap_record_id;

sys/dev/pci/if_bnxtreg.h

46919

uint32_t encap_record_id;

sys/dev/pci/if_bnxtreg.h

46982

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

47028

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

4705

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

4706

uint32_t v;

sys/dev/pci/if_bnxtreg.h

4715

uint32_t kid;

sys/dev/pci/if_bnxtreg.h

47255

uint32_t src_ipaddr[4];

sys/dev/pci/if_bnxtreg.h

47261

uint32_t src_ipaddr_mask[4];

sys/dev/pci/if_bnxtreg.h

47266

uint32_t dst_ipaddr[4];

sys/dev/pci/if_bnxtreg.h

47272

uint32_t dst_ipaddr_mask[4];

sys/dev/pci/if_bnxtreg.h

47321

uint32_t flow_id;

sys/dev/pci/if_bnxtreg.h

47472

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

47488

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

47517

uint32_t new_dst_id;

sys/dev/pci/if_bnxtreg.h

47522

uint32_t new_mirror_vnic_id;

sys/dev/pci/if_bnxtreg.h

47597

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

47640

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

47783

uint32_t tunnel_id;

sys/dev/pci/if_bnxtreg.h

47847

uint32_t src_ipaddr[4];

sys/dev/pci/if_bnxtreg.h

47853

uint32_t dst_ipaddr[4];

sys/dev/pci/if_bnxtreg.h

47877

uint32_t encap_record_id;

sys/dev/pci/if_bnxtreg.h

47901

uint32_t flow_id;

sys/dev/pci/if_bnxtreg.h

48036

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

48061

uint32_t new_dst_id;

sys/dev/pci/if_bnxtreg.h

48066

uint32_t new_mirror_vnic_id;

sys/dev/pci/if_bnxtreg.h

48154

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

48286

uint32_t reserved2;

sys/dev/pci/if_bnxtreg.h

48288

uint32_t commit_rate;

sys/dev/pci/if_bnxtreg.h

48316

uint32_t commit_burst;

sys/dev/pci/if_bnxtreg.h

48344

uint32_t excess_peak_rate;

sys/dev/pci/if_bnxtreg.h

48372

uint32_t excess_peak_burst;

sys/dev/pci/if_bnxtreg.h

48584

uint32_t reserved;

sys/dev/pci/if_bnxtreg.h

48586

uint32_t commit_rate;

sys/dev/pci/if_bnxtreg.h

48614

uint32_t commit_burst;

sys/dev/pci/if_bnxtreg.h

48642

uint32_t excess_peak_rate;

sys/dev/pci/if_bnxtreg.h

48670

uint32_t excess_peak_burst;

sys/dev/pci/if_bnxtreg.h

4869

uint32_t info2;

sys/dev/pci/if_bnxtreg.h

4875

uint32_t info3_v;

sys/dev/pci/if_bnxtreg.h

4880

uint32_t info4;

sys/dev/pci/if_bnxtreg.h

49023

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

49026

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

49119

uint32_t tunnel_id;

sys/dev/pci/if_bnxtreg.h

49223

uint32_t unused_4;

sys/dev/pci/if_bnxtreg.h

49228

uint32_t src_ipaddr[4];

sys/dev/pci/if_bnxtreg.h

49233

uint32_t dst_ipaddr[4];

sys/dev/pci/if_bnxtreg.h

4926

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

49269

uint32_t decap_filter_id;

sys/dev/pci/if_bnxtreg.h

49319

uint32_t decap_filter_id;

sys/dev/pci/if_bnxtreg.h

49439

uint32_t tunnel_handle;

sys/dev/pci/if_bnxtreg.h

49519

uint32_t ip_dst[4];

sys/dev/pci/if_bnxtreg.h

49521

uint32_t ip_src[4];

sys/dev/pci/if_bnxtreg.h

49546

uint32_t nat_ip_address[4];

sys/dev/pci/if_bnxtreg.h

49621

uint32_t flow_id;

sys/dev/pci/if_bnxtreg.h

49647

uint32_t flow_counter_id;

sys/dev/pci/if_bnxtreg.h

49728

uint32_t flow_counter_id;

sys/dev/pci/if_bnxtreg.h

49798

uint32_t nat_ip_address[4];

sys/dev/pci/if_bnxtreg.h

49836

uint32_t encap_data[20];

sys/dev/pci/if_bnxtreg.h

49886

uint32_t tunnel_id;

sys/dev/pci/if_bnxtreg.h

49896

uint32_t unused;

sys/dev/pci/if_bnxtreg.h

49906

uint32_t ip_dst[4];

sys/dev/pci/if_bnxtreg.h

49908

uint32_t ip_src[4];

sys/dev/pci/if_bnxtreg.h

49910

uint32_t nat_ip_address[4];

sys/dev/pci/if_bnxtreg.h

49952

uint32_t t_l2_key_data[14];

sys/dev/pci/if_bnxtreg.h

49954

uint32_t t_l2_key_mask[14];

sys/dev/pci/if_bnxtreg.h

49956

uint32_t t_l3_key_data[16];

sys/dev/pci/if_bnxtreg.h

49958

uint32_t t_l3_key_mask[16];

sys/dev/pci/if_bnxtreg.h

49966

uint32_t l2_key_data[14];

sys/dev/pci/if_bnxtreg.h

49968

uint32_t l2_key_mask[14];

sys/dev/pci/if_bnxtreg.h

4997

uint32_t unused_2;

sys/dev/pci/if_bnxtreg.h

49970

uint32_t l3_key_data[16];

sys/dev/pci/if_bnxtreg.h

49972

uint32_t l3_key_mask[16];

sys/dev/pci/if_bnxtreg.h

50078

uint32_t tunnel_handle;

sys/dev/pci/if_bnxtreg.h

50083

uint32_t flow_key_data[130];

sys/dev/pci/if_bnxtreg.h

50085

uint32_t flow_action_info[30];

sys/dev/pci/if_bnxtreg.h

50135

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

50334

uint32_t flow_id_0;

sys/dev/pci/if_bnxtreg.h

50336

uint32_t flow_id_1;

sys/dev/pci/if_bnxtreg.h

50338

uint32_t flow_id_2;

sys/dev/pci/if_bnxtreg.h

50340

uint32_t flow_id_3;

sys/dev/pci/if_bnxtreg.h

50342

uint32_t flow_id_4;

sys/dev/pci/if_bnxtreg.h

50344

uint32_t flow_id_5;

sys/dev/pci/if_bnxtreg.h

50346

uint32_t flow_id_6;

sys/dev/pci/if_bnxtreg.h

50348

uint32_t flow_id_7;

sys/dev/pci/if_bnxtreg.h

50350

uint32_t flow_id_8;

sys/dev/pci/if_bnxtreg.h

50352

uint32_t flow_id_9;

sys/dev/pci/if_bnxtreg.h

50470

uint32_t flow_timer;

sys/dev/pci/if_bnxtreg.h

5052

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

50599

uint32_t tcp_flow_timer;

sys/dev/pci/if_bnxtreg.h

50604

uint32_t tcp_fin_timer;

sys/dev/pci/if_bnxtreg.h

50609

uint32_t udp_flow_timer;

sys/dev/pci/if_bnxtreg.h

50621

uint32_t eem_ctx_max_entries;

sys/dev/pci/if_bnxtreg.h

50723

uint32_t tcp_flow_timer;

sys/dev/pci/if_bnxtreg.h

50728

uint32_t tcp_fin_timer;

sys/dev/pci/if_bnxtreg.h

50733

uint32_t udp_flow_timer;

sys/dev/pci/if_bnxtreg.h

50745

uint32_t eem_ctx_max_entries;

sys/dev/pci/if_bnxtreg.h

50828

uint32_t max_tcp_flow_timer;

sys/dev/pci/if_bnxtreg.h

50833

uint32_t max_tcp_fin_timer;

sys/dev/pci/if_bnxtreg.h

50838

uint32_t max_udp_flow_timer;

sys/dev/pci/if_bnxtreg.h

50840

uint32_t max_aging_flows;

sys/dev/pci/if_bnxtreg.h

51095

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

5122

uint32_t sq_cons_idx;

sys/dev/pci/if_bnxtreg.h

51235

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

51458

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

51752

uint32_t tunnel_mask;

sys/dev/pci/if_bnxtreg.h

51869

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

5202

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

52186

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

52194

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

52199

uint32_t min_rx_fc;

sys/dev/pci/if_bnxtreg.h

52204

uint32_t max_rx_fc;

sys/dev/pci/if_bnxtreg.h

52209

uint32_t min_tx_fc;

sys/dev/pci/if_bnxtreg.h

52214

uint32_t max_tx_fc;

sys/dev/pci/if_bnxtreg.h

52219

uint32_t min_rx_efc;

sys/dev/pci/if_bnxtreg.h

52224

uint32_t max_rx_efc;

sys/dev/pci/if_bnxtreg.h

52229

uint32_t min_tx_efc;

sys/dev/pci/if_bnxtreg.h

52234

uint32_t max_tx_efc;

sys/dev/pci/if_bnxtreg.h

52239

uint32_t min_rx_mdc;

sys/dev/pci/if_bnxtreg.h

52244

uint32_t max_rx_mdc;

sys/dev/pci/if_bnxtreg.h

52249

uint32_t min_tx_mdc;

sys/dev/pci/if_bnxtreg.h

52254

uint32_t max_tx_mdc;

sys/dev/pci/if_bnxtreg.h

52259

uint32_t max_flow_alloc_fc;

sys/dev/pci/if_bnxtreg.h

52346

uint32_t num_entries;

sys/dev/pci/if_bnxtreg.h

52347

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

52428

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

52444

uint32_t num_entries;

sys/dev/pci/if_bnxtreg.h

52570

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

52585

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

52599

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

52626

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

52627

uint32_t supported;

sys/dev/pci/if_bnxtreg.h

52665

uint32_t max_entries_supported;

sys/dev/pci/if_bnxtreg.h

52722

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

52751

uint32_t num_entries;

sys/dev/pci/if_bnxtreg.h

52752

uint32_t unused_1;

sys/dev/pci/if_bnxtreg.h

52764

uint32_t unused_3;

sys/dev/pci/if_bnxtreg.h

52826

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

52831

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

52845

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

52853

uint32_t num_entries;

sys/dev/pci/if_bnxtreg.h

5291

uint32_t ts_ns_lo;

sys/dev/pci/if_bnxtreg.h

52912

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

53011

uint32_t unused_0[4];

sys/dev/pci/if_bnxtreg.h

53025

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

53216

uint32_t tf_req[26];

sys/dev/pci/if_bnxtreg.h

53235

uint32_t tf_resp_code;

sys/dev/pci/if_bnxtreg.h

53237

uint32_t tf_resp[170];

sys/dev/pci/if_bnxtreg.h

53442

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

53443

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

53557

uint32_t src_ipaddr[4];

sys/dev/pci/if_bnxtreg.h

53562

uint32_t dst_ipaddr[4];

sys/dev/pci/if_bnxtreg.h

53577

uint32_t kid;

sys/dev/pci/if_bnxtreg.h

53602

uint32_t flow_id;

sys/dev/pci/if_bnxtreg.h

53755

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

53762

uint32_t unused_1;

sys/dev/pci/if_bnxtreg.h

53831

uint32_t req[26];

sys/dev/pci/if_bnxtreg.h

53850

uint32_t resp_code;

sys/dev/pci/if_bnxtreg.h

53852

uint32_t resp[170];

sys/dev/pci/if_bnxtreg.h

53996

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

54001

uint32_t fw_session_client_id;

sys/dev/pci/if_bnxtreg.h

54003

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

54078

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

54080

uint32_t unused0;

sys/dev/pci/if_bnxtreg.h

54101

uint32_t fw_session_client_id;

sys/dev/pci/if_bnxtreg.h

54155

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

54160

uint32_t fw_session_client_id;

sys/dev/pci/if_bnxtreg.h

5419

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

54224

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

54290

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

54397

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

54435

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

54511

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

54611

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

54696

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

54764

uint32_t type;

sys/dev/pci/if_bnxtreg.h

54776

uint32_t type;

sys/dev/pci/if_bnxtreg.h

54820

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

54861

uint32_t resp_code;

sys/dev/pci/if_bnxtreg.h

54917

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

5493

uint32_t rss_hash;

sys/dev/pci/if_bnxtreg.h

54949

uint32_t type;

sys/dev/pci/if_bnxtreg.h

54951

uint32_t index;

sys/dev/pci/if_bnxtreg.h

54966

uint32_t resp_code;

sys/dev/pci/if_bnxtreg.h

5500

uint32_t flags2;

sys/dev/pci/if_bnxtreg.h

55023

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

55052

uint32_t type;

sys/dev/pci/if_bnxtreg.h

55054

uint32_t index;

sys/dev/pci/if_bnxtreg.h

55124

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

55168

uint32_t resp_code;

sys/dev/pci/if_bnxtreg.h

55219

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

55232

uint32_t action_ptr;

sys/dev/pci/if_bnxtreg.h

55234

uint32_t em_record_idx;

sys/dev/pci/if_bnxtreg.h

55310

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

55325

uint32_t key0_hash;

sys/dev/pci/if_bnxtreg.h

55327

uint32_t key1_hash;

sys/dev/pci/if_bnxtreg.h

55329

uint32_t em_record_idx;

sys/dev/pci/if_bnxtreg.h

55331

uint32_t unused0;

sys/dev/pci/if_bnxtreg.h

55403

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

55488

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

55501

uint32_t new_index;

sys/dev/pci/if_bnxtreg.h

55503

uint32_t unused0;

sys/dev/pci/if_bnxtreg.h

55571

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

55573

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

55590

uint32_t type;

sys/dev/pci/if_bnxtreg.h

55674

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

55676

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

55688

uint32_t type;

sys/dev/pci/if_bnxtreg.h

55771

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

55773

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

55785

uint32_t type;

sys/dev/pci/if_bnxtreg.h

55855

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

55857

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

55869

uint32_t type;

sys/dev/pci/if_bnxtreg.h

55939

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

55941

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

55952

uint32_t type;

sys/dev/pci/if_bnxtreg.h

55954

uint32_t offset;

sys/dev/pci/if_bnxtreg.h

5599

uint32_t metadata;

sys/dev/pci/if_bnxtreg.h

56026

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

56028

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

56037

uint32_t type;

sys/dev/pci/if_bnxtreg.h

56039

uint32_t offset;

sys/dev/pci/if_bnxtreg.h

56113

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

56129

uint32_t type;

sys/dev/pci/if_bnxtreg.h

56131

uint32_t index;

sys/dev/pci/if_bnxtreg.h

56146

uint32_t resp_code;

sys/dev/pci/if_bnxtreg.h

56203

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

56219

uint32_t type;

sys/dev/pci/if_bnxtreg.h

56221

uint32_t index;

sys/dev/pci/if_bnxtreg.h

56291

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

56312

uint32_t type;

sys/dev/pci/if_bnxtreg.h

56314

uint32_t start_index;

sys/dev/pci/if_bnxtreg.h

56316

uint32_t num_entries;

sys/dev/pci/if_bnxtreg.h

56318

uint32_t unused1;

sys/dev/pci/if_bnxtreg.h

56335

uint32_t resp_code;

sys/dev/pci/if_bnxtreg.h

56388

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

56463

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

56542

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

56641

uint32_t fw_session_id;

sys/dev/pci/if_bnxtreg.h

56687

uint32_t resp_code;

sys/dev/pci/if_bnxtreg.h

56764

uint32_t max_lkup_rec_cnt;

sys/dev/pci/if_bnxtreg.h

56769

uint32_t max_act_rec_cnt;

sys/dev/pci/if_bnxtreg.h

56969

uint32_t pbl_page_sz;

sys/dev/pci/if_bnxtreg.h

5790

uint32_t reorder;

sys/dev/pci/if_bnxtreg.h

59313

uint32_t resp_code;

sys/dev/pci/if_bnxtreg.h

5940

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

59997

uint32_t update_period_ms;

sys/dev/pci/if_bnxtreg.h

60045

uint32_t stat_ctx_id;

sys/dev/pci/if_bnxtreg.h

60066

uint32_t stat_ctx_id;

sys/dev/pci/if_bnxtreg.h

60115

uint32_t stat_ctx_id;

sys/dev/pci/if_bnxtreg.h

60131

uint32_t stat_ctx_id;

sys/dev/pci/if_bnxtreg.h

60180

uint32_t stat_ctx_id;

sys/dev/pci/if_bnxtreg.h

60290

uint32_t stat_ctx_id;

sys/dev/pci/if_bnxtreg.h

6038

uint32_t rss_hash;

sys/dev/pci/if_bnxtreg.h

60404

uint32_t stat_ctx_id;

sys/dev/pci/if_bnxtreg.h

6045

uint32_t flags2;

sys/dev/pci/if_bnxtreg.h

60508

uint32_t stat_ctx_id;

sys/dev/pci/if_bnxtreg.h

60637

uint32_t pcie_ltssm_histogram[4];

sys/dev/pci/if_bnxtreg.h

60885

uint32_t tx_db_drop_invalid_qp_state;

sys/dev/pci/if_bnxtreg.h

60890

uint32_t rx_db_drop_invalid_rq_state;

sys/dev/pci/if_bnxtreg.h

60896

uint32_t tx_db_drop_format_error;

sys/dev/pci/if_bnxtreg.h

60902

uint32_t express_db_dropped_misc_error;

sys/dev/pci/if_bnxtreg.h

60907

uint32_t express_db_dropped_sq_overflow;

sys/dev/pci/if_bnxtreg.h

60912

uint32_t express_db_dropped_rq_overflow;

sys/dev/pci/if_bnxtreg.h

6153

uint32_t metadata2;

sys/dev/pci/if_bnxtreg.h

61662

uint32_t tlv_value[64];

sys/dev/pci/if_bnxtreg.h

61676

uint32_t mgmt_addr[8];

sys/dev/pci/if_bnxtreg.h

61678

uint32_t system_caps;

sys/dev/pci/if_bnxtreg.h

61685

uint32_t intf_num;

sys/dev/pci/if_bnxtreg.h

61688

uint32_t mgmt_addr_oid[32];

sys/dev/pci/if_bnxtreg.h

61757

uint32_t bkup_power_info_ver;

sys/dev/pci/if_bnxtreg.h

61759

uint32_t platform_bkup_power_count;

sys/dev/pci/if_bnxtreg.h

61761

uint32_t load_milli_watt;

sys/dev/pci/if_bnxtreg.h

61763

uint32_t bkup_time_milli_seconds;

sys/dev/pci/if_bnxtreg.h

61765

uint32_t bkup_power_status;

sys/dev/pci/if_bnxtreg.h

61767

uint32_t bkup_power_charge_time;

sys/dev/pci/if_bnxtreg.h

61790

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

61848

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

62133

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

62176

uint32_t data_offset;

sys/dev/pci/if_bnxtreg.h

62195

uint32_t msg_data_1;

sys/dev/pci/if_bnxtreg.h

62196

uint32_t msg_data_2;

sys/dev/pci/if_bnxtreg.h

62253

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

62255

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

62483

uint32_t fw_status;

sys/dev/pci/if_bnxtreg.h

62746

uint32_t patch_len;

sys/dev/pci/if_bnxtreg.h

62844

uint32_t sync_action;

sys/dev/pci/if_bnxtreg.h

62933

uint32_t sync_status;

sys/dev/pci/if_bnxtreg.h

63030

uint32_t backup_memory;

sys/dev/pci/if_bnxtreg.h

63049

uint32_t quiesce_timeout;

sys/dev/pci/if_bnxtreg.h

63055

uint32_t fw_status_blackout;

sys/dev/pci/if_bnxtreg.h

63062

uint32_t fw_status_max_wait;

sys/dev/pci/if_bnxtreg.h

63140

uint32_t quiesce_status;

sys/dev/pci/if_bnxtreg.h

63208

uint32_t unquiesce_status;

sys/dev/pci/if_bnxtreg.h

63306

uint32_t backup_status;

sys/dev/pci/if_bnxtreg.h

63427

uint32_t restore_status;

sys/dev/pci/if_bnxtreg.h

63633

uint32_t encap_request[26];

sys/dev/pci/if_bnxtreg.h

63709

uint32_t encap_request[26];

sys/dev/pci/if_bnxtreg.h

63809

uint32_t encap_resp[24];

sys/dev/pci/if_bnxtreg.h

6387

uint32_t timestamp;

sys/dev/pci/if_bnxtreg.h

63881

uint32_t encap_async_event_cmpl[4];

sys/dev/pci/if_bnxtreg.h

64110

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

64119

uint32_t in_power_mw;

sys/dev/pci/if_bnxtreg.h

64124

uint32_t out_power_mw;

sys/dev/pci/if_bnxtreg.h

64186

uint32_t core_frequency_hz;

sys/dev/pci/if_bnxtreg.h

64235

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

64241

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

64285

uint32_t sampling_period;

sys/dev/pci/if_bnxtreg.h

64302

uint32_t power_hist[26];

sys/dev/pci/if_bnxtreg.h

64413

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

64414

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

64562

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

64571

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

64737

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

64906

uint32_t read_addr;

sys/dev/pci/if_bnxtreg.h

64908

uint32_t read_len32;

sys/dev/pci/if_bnxtreg.h

64927

uint32_t crc32;

sys/dev/pci/if_bnxtreg.h

64976

uint32_t write_addr;

sys/dev/pci/if_bnxtreg.h

64978

uint32_t write_len32;

sys/dev/pci/if_bnxtreg.h

64980

uint32_t write_data[8];

sys/dev/pci/if_bnxtreg.h

65047

uint32_t host_dest_addr_len;

sys/dev/pci/if_bnxtreg.h

65110

uint32_t start_index;

sys/dev/pci/if_bnxtreg.h

65112

uint32_t num_of_entries;

sys/dev/pci/if_bnxtreg.h

65117

uint32_t opaque[10];

sys/dev/pci/if_bnxtreg.h

65231

uint32_t start_index;

sys/dev/pci/if_bnxtreg.h

65233

uint32_t num_of_entries;

sys/dev/pci/if_bnxtreg.h

65236

uint32_t write_data[8];

sys/dev/pci/if_bnxtreg.h

65238

uint32_t opaque[10];

sys/dev/pci/if_bnxtreg.h

6530

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

65304

uint32_t handle;

sys/dev/pci/if_bnxtreg.h

65334

uint32_t nexthandle;

sys/dev/pci/if_bnxtreg.h

65339

uint32_t dbg_data_len;

sys/dev/pci/if_bnxtreg.h

65459

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

65584

uint32_t dump_size;

sys/dev/pci/if_bnxtreg.h

65589

uint32_t crash_time;

sys/dev/pci/if_bnxtreg.h

65657

uint32_t power_on_count;

sys/dev/pci/if_bnxtreg.h

65722

uint32_t unused_1;

sys/dev/pci/if_bnxtreg.h

65813

uint32_t coredump_component_disable_caps;

sys/dev/pci/if_bnxtreg.h

65819

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

65919

uint32_t coredump_component_disable_flags;

sys/dev/pci/if_bnxtreg.h

65949

uint32_t coredump_size;

sys/dev/pci/if_bnxtreg.h

65950

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

65994

uint32_t crashdump_size;

sys/dev/pci/if_bnxtreg.h

66079

uint32_t size;

sys/dev/pci/if_bnxtreg.h

66084

uint32_t coredump_component_disable_flags;

sys/dev/pci/if_bnxtreg.h

66090

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

66147

uint32_t segment_len;

sys/dev/pci/if_bnxtreg.h

66192

uint32_t host_buf_len;

sys/dev/pci/if_bnxtreg.h

66327

uint32_t address;

sys/dev/pci/if_bnxtreg.h

66333

uint32_t flags_length;

sys/dev/pci/if_bnxtreg.h

66340

uint32_t instance;

sys/dev/pci/if_bnxtreg.h

66342

uint32_t next_offset;

sys/dev/pci/if_bnxtreg.h

66387

uint32_t host_buf_len;

sys/dev/pci/if_bnxtreg.h

66389

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

66406

uint32_t unused_4;

sys/dev/pci/if_bnxtreg.h

66408

uint32_t seq_no;

sys/dev/pci/if_bnxtreg.h

66409

uint32_t unused_5;

sys/dev/pci/if_bnxtreg.h

66590

uint32_t host_buf_len;

sys/dev/pci/if_bnxtreg.h

66610

uint32_t cli_data_len;

sys/dev/pci/if_bnxtreg.h

66671

uint32_t fw_ring_id;

sys/dev/pci/if_bnxtreg.h

66686

uint32_t producer_index;

sys/dev/pci/if_bnxtreg.h

66688

uint32_t consumer_index;

sys/dev/pci/if_bnxtreg.h

66693

uint32_t cag_vector_ctrl;

sys/dev/pci/if_bnxtreg.h

66832

uint32_t size;

sys/dev/pci/if_bnxtreg.h

66854

uint32_t nz_fw_timestamp;

sys/dev/pci/if_bnxtreg.h

66860

uint32_t useq_resp_flags;

sys/dev/pci/if_bnxtreg.h

66881

uint32_t valid;

sys/dev/pci/if_bnxtreg.h

6690

uint32_t rss_hash;

sys/dev/pci/if_bnxtreg.h

66938

uint32_t nz_fw_timestamp;

sys/dev/pci/if_bnxtreg.h

66944

uint32_t useq_resp_flags;

sys/dev/pci/if_bnxtreg.h

66955

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

66963

uint32_t valid;

sys/dev/pci/if_bnxtreg.h

6697

uint32_t flags2;

sys/dev/pci/if_bnxtreg.h

67025

uint32_t nz_fw_timestamp;

sys/dev/pci/if_bnxtreg.h

67031

uint32_t useq_resp_flags;

sys/dev/pci/if_bnxtreg.h

67042

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

67050

uint32_t valid;

sys/dev/pci/if_bnxtreg.h

67130

uint32_t opaque[24];

sys/dev/pci/if_bnxtreg.h

67145

uint32_t nz_fw_timestamp;

sys/dev/pci/if_bnxtreg.h

67151

uint32_t useq_resp_flags;

sys/dev/pci/if_bnxtreg.h

67213

uint32_t nz_fw_timestamp;

sys/dev/pci/if_bnxtreg.h

67219

uint32_t useq_resp_flags;

sys/dev/pci/if_bnxtreg.h

67230

uint32_t max_num_useq;

sys/dev/pci/if_bnxtreg.h

67232

uint32_t max_useq_size;

sys/dev/pci/if_bnxtreg.h

67234

uint32_t max_useq_32b_output_size;

sys/dev/pci/if_bnxtreg.h

67236

uint32_t num_buf;

sys/dev/pci/if_bnxtreg.h

67238

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

67246

uint32_t valid;

sys/dev/pci/if_bnxtreg.h

67308

uint32_t polling_interval;

sys/dev/pci/if_bnxtreg.h

67323

uint32_t nz_fw_timestamp;

sys/dev/pci/if_bnxtreg.h

67329

uint32_t useq_resp_flags;

sys/dev/pci/if_bnxtreg.h

67340

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

67348

uint32_t valid;

sys/dev/pci/if_bnxtreg.h

67419

uint32_t run_interval;

sys/dev/pci/if_bnxtreg.h

67429

uint32_t host_dest_len;

sys/dev/pci/if_bnxtreg.h

67431

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

67446

uint32_t nz_fw_timestamp;

sys/dev/pci/if_bnxtreg.h

67452

uint32_t useq_resp_flags;

sys/dev/pci/if_bnxtreg.h

67467

uint32_t host_dest_filled_len;

sys/dev/pci/if_bnxtreg.h

67475

uint32_t valid;

sys/dev/pci/if_bnxtreg.h

67525

uint32_t host_dest_len[8];

sys/dev/pci/if_bnxtreg.h

67540

uint32_t nz_fw_timestamp;

sys/dev/pci/if_bnxtreg.h

67546

uint32_t useq_resp_flags;

sys/dev/pci/if_bnxtreg.h

67561

uint32_t host_dest_filled_len[8];

sys/dev/pci/if_bnxtreg.h

67563

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

67571

uint32_t valid;

sys/dev/pci/if_bnxtreg.h

67637

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

67663

uint32_t current_buffer_offset;

sys/dev/pci/if_bnxtreg.h

67718

uint32_t resp_data_offset;

sys/dev/pci/if_bnxtreg.h

68068

uint32_t pdi_req_buf_len;

sys/dev/pci/if_bnxtreg.h

6815

uint32_t metadata2;

sys/dev/pci/if_bnxtreg.h

68169

uint32_t dest_addr;

sys/dev/pci/if_bnxtreg.h

68171

uint32_t len;

sys/dev/pci/if_bnxtreg.h

68251

uint32_t offset;

sys/dev/pci/if_bnxtreg.h

68253

uint32_t len;

sys/dev/pci/if_bnxtreg.h

68321

uint32_t offset;

sys/dev/pci/if_bnxtreg.h

68323

uint32_t len;

sys/dev/pci/if_bnxtreg.h

68473

uint32_t entries;

sys/dev/pci/if_bnxtreg.h

68475

uint32_t entry_length;

sys/dev/pci/if_bnxtreg.h

68555

uint32_t dir_data_length;

sys/dev/pci/if_bnxtreg.h

68593

uint32_t dir_item_length;

sys/dev/pci/if_bnxtreg.h

68598

uint32_t offset;

sys/dev/pci/if_bnxtreg.h

68603

uint32_t len;

sys/dev/pci/if_bnxtreg.h

68604

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

68625

uint32_t dir_item_length;

sys/dev/pci/if_bnxtreg.h

68718

uint32_t offset;

sys/dev/pci/if_bnxtreg.h

68723

uint32_t len;

sys/dev/pci/if_bnxtreg.h

68785

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

68829

uint32_t dir_item_length;

sys/dev/pci/if_bnxtreg.h

68831

uint32_t dir_data_length;

sys/dev/pci/if_bnxtreg.h

68837

uint32_t fw_ver;

sys/dev/pci/if_bnxtreg.h

68981

uint32_t sector_size;

sys/dev/pci/if_bnxtreg.h

68983

uint32_t nvram_size;

sys/dev/pci/if_bnxtreg.h

68984

uint32_t reserved_size;

sys/dev/pci/if_bnxtreg.h

68989

uint32_t available_size;

sys/dev/pci/if_bnxtreg.h

69159

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

69186

uint32_t checksum;

sys/dev/pci/if_bnxtreg.h

69332

uint32_t install_type;

sys/dev/pci/if_bnxtreg.h

6999

uint32_t timestamp;

sys/dev/pci/if_bnxtreg.h

70195

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

70397

#define ROCE_SP_HSI_NA_SIGNATURE ((uint32_t)(-1))

sys/dev/pci/if_bnxtreg.h

70414

uint32_t prod_idx;

sys/dev/pci/if_bnxtreg.h

70423

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

70425

uint32_t prod_idx;

sys/dev/pci/if_bnxtreg.h

70683

uint32_t qp_flags;

sys/dev/pci/if_bnxtreg.h

70818

uint32_t dpi;

sys/dev/pci/if_bnxtreg.h

70824

uint32_t sq_size;

sys/dev/pci/if_bnxtreg.h

70826

uint32_t rq_size;

sys/dev/pci/if_bnxtreg.h

70855

uint32_t scq_cid;

sys/dev/pci/if_bnxtreg.h

70857

uint32_t rcq_cid;

sys/dev/pci/if_bnxtreg.h

70859

uint32_t srq_cid;

sys/dev/pci/if_bnxtreg.h

70861

uint32_t pd_id;

sys/dev/pci/if_bnxtreg.h

70895

uint32_t request_xid;

sys/dev/pci/if_bnxtreg.h

70907

uint32_t ext_stats_ctx_id;

sys/dev/pci/if_bnxtreg.h

7127

uint32_t rss_hash;

sys/dev/pci/if_bnxtreg.h

71382

uint32_t number_of_qp;

sys/dev/pci/if_bnxtreg.h

71387

uint32_t number_of_mrw;

sys/dev/pci/if_bnxtreg.h

71392

uint32_t number_of_srq;

sys/dev/pci/if_bnxtreg.h

71397

uint32_t number_of_cq;

sys/dev/pci/if_bnxtreg.h

71402

uint32_t max_qp_per_vf;

sys/dev/pci/if_bnxtreg.h

71420

uint32_t max_mrw_per_vf;

sys/dev/pci/if_bnxtreg.h

71425

uint32_t max_srq_per_vf;

sys/dev/pci/if_bnxtreg.h

71430

uint32_t max_cq_per_vf;

sys/dev/pci/if_bnxtreg.h

71435

uint32_t max_gid_per_vf;

sys/dev/pci/if_bnxtreg.h

71437

uint32_t stat_ctx_id;

sys/dev/pci/if_bnxtreg.h

71476

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

71538

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

71584

uint32_t qp_flags;

sys/dev/pci/if_bnxtreg.h

71719

uint32_t dpi;

sys/dev/pci/if_bnxtreg.h

71725

uint32_t sq_size;

sys/dev/pci/if_bnxtreg.h

71727

uint32_t rq_size;

sys/dev/pci/if_bnxtreg.h

71756

uint32_t scq_cid;

sys/dev/pci/if_bnxtreg.h

71758

uint32_t rcq_cid;

sys/dev/pci/if_bnxtreg.h

71760

uint32_t srq_cid;

sys/dev/pci/if_bnxtreg.h

71762

uint32_t pd_id;

sys/dev/pci/if_bnxtreg.h

71796

uint32_t request_xid;

sys/dev/pci/if_bnxtreg.h

71808

uint32_t ext_stats_ctx_id;

sys/dev/pci/if_bnxtreg.h

71843

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

71892

uint32_t qp_cid;

sys/dev/pci/if_bnxtreg.h

71893

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

71917

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

71987

uint32_t modify_mask;

sys/dev/pci/if_bnxtreg.h

72053

uint32_t qp_cid;

sys/dev/pci/if_bnxtreg.h

7209

uint32_t errors_agg_bufs_opaque;

sys/dev/pci/if_bnxtreg.h

72105

uint32_t qkey;

sys/dev/pci/if_bnxtreg.h

72107

uint32_t dgid[4];

sys/dev/pci/if_bnxtreg.h

72109

uint32_t flow_label;

sys/dev/pci/if_bnxtreg.h

72160

uint32_t rq_psn;

sys/dev/pci/if_bnxtreg.h

72162

uint32_t sq_psn;

sys/dev/pci/if_bnxtreg.h

72174

uint32_t sq_size;

sys/dev/pci/if_bnxtreg.h

72176

uint32_t rq_size;

sys/dev/pci/if_bnxtreg.h

72182

uint32_t max_inline_data;

sys/dev/pci/if_bnxtreg.h

72184

uint32_t dest_qp_id;

sys/dev/pci/if_bnxtreg.h

72186

uint32_t pingpong_push_dpi;

sys/dev/pci/if_bnxtreg.h

72206

uint32_t ext_modify_mask;

sys/dev/pci/if_bnxtreg.h

72212

uint32_t ext_stats_ctx_id;

sys/dev/pci/if_bnxtreg.h

72224

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

72248

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

72280

uint32_t lag_src_mac;

sys/dev/pci/if_bnxtreg.h

72308

uint32_t qp_cid;

sys/dev/pci/if_bnxtreg.h

72309

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

72333

uint32_t size;

sys/dev/pci/if_bnxtreg.h

72368

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

72408

uint32_t qkey;

sys/dev/pci/if_bnxtreg.h

72416

uint32_t dgid[4];

sys/dev/pci/if_bnxtreg.h

72418

uint32_t flow_label;

sys/dev/pci/if_bnxtreg.h

72456

uint32_t rq_psn;

sys/dev/pci/if_bnxtreg.h

72458

uint32_t sq_psn;

sys/dev/pci/if_bnxtreg.h

72474

uint32_t sq_size;

sys/dev/pci/if_bnxtreg.h

72476

uint32_t rq_size;

sys/dev/pci/if_bnxtreg.h

72482

uint32_t max_inline_data;

sys/dev/pci/if_bnxtreg.h

72484

uint32_t dest_qp_id;

sys/dev/pci/if_bnxtreg.h

72535

uint32_t function_id;

sys/dev/pci/if_bnxtreg.h

72548

uint32_t current_index;

sys/dev/pci/if_bnxtreg.h

72572

uint32_t size;

sys/dev/pci/if_bnxtreg.h

72590

uint32_t current_index;

sys/dev/pci/if_bnxtreg.h

72612

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

72639

uint32_t qkey;

sys/dev/pci/if_bnxtreg.h

72653

uint32_t dgid[4];

sys/dev/pci/if_bnxtreg.h

72655

uint32_t dest_qp_id;

sys/dev/pci/if_bnxtreg.h

72741

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

72768

uint32_t qkey;

sys/dev/pci/if_bnxtreg.h

72782

uint32_t dgid[4];

sys/dev/pci/if_bnxtreg.h

72784

uint32_t dest_qp_id;

sys/dev/pci/if_bnxtreg.h

72872

uint32_t dpi;

sys/dev/pci/if_bnxtreg.h

72874

uint32_t pd_id;

sys/dev/pci/if_bnxtreg.h

72905

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

72946

uint32_t srq_cid;

sys/dev/pci/if_bnxtreg.h

72947

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

72971

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

73020

uint32_t srq_cid;

sys/dev/pci/if_bnxtreg.h

73021

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

73045

uint32_t size;

sys/dev/pci/if_bnxtreg.h

73080

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

73085

uint32_t data[4];

sys/dev/pci/if_bnxtreg.h

73144

uint32_t pg_size_lvl;

sys/dev/pci/if_bnxtreg.h

73177

uint32_t cq_fco_cnq_id;

sys/dev/pci/if_bnxtreg.h

73185

uint32_t dpi;

sys/dev/pci/if_bnxtreg.h

73187

uint32_t cq_size;

sys/dev/pci/if_bnxtreg.h

73193

uint32_t coalescing;

sys/dev/pci/if_bnxtreg.h

73252

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

73293

uint32_t cq_cid;

sys/dev/pci/if_bnxtreg.h

73294

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

73318

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

73374

uint32_t cq_cid;

sys/dev/pci/if_bnxtreg.h

73375

uint32_t new_cq_size_pg_size_lvl;

sys/dev/pci/if_bnxtreg.h

73411

uint32_t new_cq_fco;

sys/dev/pci/if_bnxtreg.h

73412

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

73436

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

73488

uint32_t modify_mask;

sys/dev/pci/if_bnxtreg.h

73502

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

73505

uint32_t cq_fco_cnq_id;

sys/dev/pci/if_bnxtreg.h

73513

uint32_t dpi;

sys/dev/pci/if_bnxtreg.h

73515

uint32_t cq_size;

sys/dev/pci/if_bnxtreg.h

73517

uint32_t reserved32_1;

sys/dev/pci/if_bnxtreg.h

73545

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

73620

uint32_t pd_id;

sys/dev/pci/if_bnxtreg.h

73644

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

73708

uint32_t key;

sys/dev/pci/if_bnxtreg.h

73732

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

73758

uint32_t bound_window_info;

sys/dev/pci/if_bnxtreg.h

73886

uint32_t key;

sys/dev/pci/if_bnxtreg.h

73921

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

73962

uint32_t lkey;

sys/dev/pci/if_bnxtreg.h

73963

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

73987

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

74008

uint32_t bound_windows;

sys/dev/pci/if_bnxtreg.h

74036

uint32_t gid[4];

sys/dev/pci/if_bnxtreg.h

74085

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

74109

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

74175

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

74216

uint32_t gid[4];

sys/dev/pci/if_bnxtreg.h

7428

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

74287

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

74354

uint32_t size;

sys/dev/pci/if_bnxtreg.h

74389

uint32_t gid[4];

sys/dev/pci/if_bnxtreg.h

74428

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

74458

uint32_t qp_flags;

sys/dev/pci/if_bnxtreg.h

74533

uint32_t dpi;

sys/dev/pci/if_bnxtreg.h

74535

uint32_t sq_size;

sys/dev/pci/if_bnxtreg.h

74537

uint32_t rq_size;

sys/dev/pci/if_bnxtreg.h

74553

uint32_t scq_cid;

sys/dev/pci/if_bnxtreg.h

74555

uint32_t rcq_cid;

sys/dev/pci/if_bnxtreg.h

74557

uint32_t srq_cid;

sys/dev/pci/if_bnxtreg.h

74559

uint32_t pd_id;

sys/dev/pci/if_bnxtreg.h

74587

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

74628

uint32_t qp1_cid;

sys/dev/pci/if_bnxtreg.h

74629

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

74653

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

74696

uint32_t dgid[4];

sys/dev/pci/if_bnxtreg.h

74710

uint32_t dest_vlan_id_flow_label;

sys/dev/pci/if_bnxtreg.h

74718

uint32_t pd_id;

sys/dev/pci/if_bnxtreg.h

74719

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

74750

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

74791

uint32_t ah_cid;

sys/dev/pci/if_bnxtreg.h

74792

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

74816

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

74872

uint32_t function_id;

sys/dev/pci/if_bnxtreg.h

74881

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

74905

uint32_t size;

sys/dev/pci/if_bnxtreg.h

7492

uint32_t rss_hash;

sys/dev/pci/if_bnxtreg.h

74939

uint32_t num_counters;

sys/dev/pci/if_bnxtreg.h

74940

uint32_t rsvd1;

sys/dev/pci/if_bnxtreg.h

7504

uint32_t flags2;

sys/dev/pci/if_bnxtreg.h

75073

uint32_t function_id;

sys/dev/pci/if_bnxtreg.h

75082

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

75106

uint32_t size;

sys/dev/pci/if_bnxtreg.h

75335

uint32_t size;

sys/dev/pci/if_bnxtreg.h

75381

uint32_t max_qp;

sys/dev/pci/if_bnxtreg.h

75478

uint32_t max_cq;

sys/dev/pci/if_bnxtreg.h

75480

uint32_t max_cqe;

sys/dev/pci/if_bnxtreg.h

75482

uint32_t max_pd;

sys/dev/pci/if_bnxtreg.h

75499

uint32_t max_mr;

sys/dev/pci/if_bnxtreg.h

75501

uint32_t max_mw;

sys/dev/pci/if_bnxtreg.h

75503

uint32_t max_raw_eth_qp;

sys/dev/pci/if_bnxtreg.h

75505

uint32_t max_ah;

sys/dev/pci/if_bnxtreg.h

75507

uint32_t max_fmr;

sys/dev/pci/if_bnxtreg.h

75509

uint32_t max_srq_wr;

sys/dev/pci/if_bnxtreg.h

75511

uint32_t max_pkeys;

sys/dev/pci/if_bnxtreg.h

75516

uint32_t max_inline_data;

sys/dev/pci/if_bnxtreg.h

7552

uint32_t metadata;

sys/dev/pci/if_bnxtreg.h

75524

uint32_t max_gid;

sys/dev/pci/if_bnxtreg.h

75536

uint32_t tqm_alloc_reqs[12];

sys/dev/pci/if_bnxtreg.h

75538

uint32_t max_dpi;

sys/dev/pci/if_bnxtreg.h

75582

uint32_t start_qid;

sys/dev/pci/if_bnxtreg.h

75677

uint32_t number_of_qp;

sys/dev/pci/if_bnxtreg.h

75683

uint32_t number_of_mrw;

sys/dev/pci/if_bnxtreg.h

75689

uint32_t number_of_srq;

sys/dev/pci/if_bnxtreg.h

75695

uint32_t number_of_cq;

sys/dev/pci/if_bnxtreg.h

75700

uint32_t max_qp_per_vf;

sys/dev/pci/if_bnxtreg.h

75718

uint32_t max_mrw_per_vf;

sys/dev/pci/if_bnxtreg.h

75723

uint32_t max_srq_per_vf;

sys/dev/pci/if_bnxtreg.h

75728

uint32_t max_cq_per_vf;

sys/dev/pci/if_bnxtreg.h

75733

uint32_t max_gid_per_vf;

sys/dev/pci/if_bnxtreg.h

75735

uint32_t stat_ctx_id;

sys/dev/pci/if_bnxtreg.h

75758

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

7581

uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;

sys/dev/pci/if_bnxtreg.h

75820

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

75864

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

75912

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

75929

uint32_t reserved_32;

sys/dev/pci/if_bnxtreg.h

75968

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

75991

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

76054

uint32_t size;

sys/dev/pci/if_bnxtreg.h

76157

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

76308

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

76534

uint32_t link64B_per_rtt;

sys/dev/pci/if_bnxtreg.h

76628

uint32_t dcn_qlevel_tbl_act[8];

sys/dev/pci/if_bnxtreg.h

76666

uint32_t modify_mask;

sys/dev/pci/if_bnxtreg.h

76785

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

76870

uint32_t modify_mask;

sys/dev/pci/if_bnxtreg.h

76989

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

7733

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

77370

uint32_t link64B_per_rtt;

sys/dev/pci/if_bnxtreg.h

77485

uint32_t dcn_qlevel_tbl_act;

sys/dev/pci/if_bnxtreg.h

77518

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

77559

uint32_t modify_mask;

sys/dev/pci/if_bnxtreg.h

77621

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

77699

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

77732

uint32_t vf_misc;

sys/dev/pci/if_bnxtreg.h

77740

uint32_t unused_1;

sys/dev/pci/if_bnxtreg.h

77812

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

77853

uint32_t start_xid;

sys/dev/pci/if_bnxtreg.h

77855

uint32_t count;

sys/dev/pci/if_bnxtreg.h

77857

uint32_t per_qp_param_size;

sys/dev/pci/if_bnxtreg.h

77858

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

77890

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

77905

uint32_t count;

sys/dev/pci/if_bnxtreg.h

77937

uint32_t start_xid;

sys/dev/pci/if_bnxtreg.h

77942

uint32_t count;

sys/dev/pci/if_bnxtreg.h

77967

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

77982

uint32_t count;

sys/dev/pci/if_bnxtreg.h

78029

uint32_t update_period_ms;

sys/dev/pci/if_bnxtreg.h

78056

uint32_t roce_stats_ext_xid;

sys/dev/pci/if_bnxtreg.h

78097

uint32_t roce_stats_ext_xid;

sys/dev/pci/if_bnxtreg.h

78098

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

78124

uint32_t roce_stats_ext_xid;

sys/dev/pci/if_bnxtreg.h

7816

uint32_t rss_hash;

sys/dev/pci/if_bnxtreg.h

78168

uint32_t roce_stats_ext_xid;

sys/dev/pci/if_bnxtreg.h

78169

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

78195

uint32_t size;

sys/dev/pci/if_bnxtreg.h

7828

uint32_t flags2;

sys/dev/pci/if_bnxtreg.h

78441

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

78789

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

79058

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

79258

uint32_t l_key;

sys/dev/pci/if_bnxtreg.h

79263

uint32_t size;

sys/dev/pci/if_bnxtreg.h

79270

uint32_t opcode_start_psn;

sys/dev/pci/if_bnxtreg.h

79277

uint32_t flags_next_psn;

sys/dev/pci/if_bnxtreg.h

79291

uint32_t opcode_start_psn;

sys/dev/pci/if_bnxtreg.h

79298

uint32_t flags_next_psn;

sys/dev/pci/if_bnxtreg.h

79313

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

79423

uint32_t inv_key_or_imm_data;

sys/dev/pci/if_bnxtreg.h

79425

uint32_t length;

sys/dev/pci/if_bnxtreg.h

79435

uint32_t q_key;

sys/dev/pci/if_bnxtreg.h

7944

uint32_t metadata2;

sys/dev/pci/if_bnxtreg.h

79443

uint32_t dst_qp;

sys/dev/pci/if_bnxtreg.h

79446

uint32_t avid;

sys/dev/pci/if_bnxtreg.h

79453

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

79454

uint32_t timestamp;

sys/dev/pci/if_bnxtreg.h

79470

uint32_t data[24];

sys/dev/pci/if_bnxtreg.h

79559

uint32_t inv_key_or_imm_data;

sys/dev/pci/if_bnxtreg.h

79561

uint32_t length;

sys/dev/pci/if_bnxtreg.h

79571

uint32_t q_key;

sys/dev/pci/if_bnxtreg.h

79579

uint32_t dst_qp;

sys/dev/pci/if_bnxtreg.h

79582

uint32_t avid;

sys/dev/pci/if_bnxtreg.h

79589

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

79590

uint32_t timestamp;

sys/dev/pci/if_bnxtreg.h

79725

uint32_t length;

sys/dev/pci/if_bnxtreg.h

79726

uint32_t reserved32_1;

sys/dev/pci/if_bnxtreg.h

79731

uint32_t cfa_meta;

sys/dev/pci/if_bnxtreg.h

79776

uint32_t reserved32_2;

sys/dev/pci/if_bnxtreg.h

79777

uint32_t reserved32_3;

sys/dev/pci/if_bnxtreg.h

79778

uint32_t timestamp;

sys/dev/pci/if_bnxtreg.h

79794

uint32_t data[24];

sys/dev/pci/if_bnxtreg.h

79922

uint32_t length;

sys/dev/pci/if_bnxtreg.h

79923

uint32_t reserved32_1;

sys/dev/pci/if_bnxtreg.h

79928

uint32_t cfa_meta;

sys/dev/pci/if_bnxtreg.h

79973

uint32_t reserved32_2;

sys/dev/pci/if_bnxtreg.h

79974

uint32_t reserved32_3;

sys/dev/pci/if_bnxtreg.h

79975

uint32_t timestamp;

sys/dev/pci/if_bnxtreg.h

80068

uint32_t imm_data;

sys/dev/pci/if_bnxtreg.h

8007

uint32_t hdr_offsets;

sys/dev/pci/if_bnxtreg.h

80070

uint32_t length;

sys/dev/pci/if_bnxtreg.h

80071

uint32_t reserved32_1;

sys/dev/pci/if_bnxtreg.h

80079

uint32_t remote_key;

sys/dev/pci/if_bnxtreg.h

80080

uint32_t timestamp;

sys/dev/pci/if_bnxtreg.h

80096

uint32_t data[24];

sys/dev/pci/if_bnxtreg.h

80182

uint32_t imm_data;

sys/dev/pci/if_bnxtreg.h

80184

uint32_t length;

sys/dev/pci/if_bnxtreg.h

80185

uint32_t reserved32_1;

sys/dev/pci/if_bnxtreg.h

80193

uint32_t remote_key;

sys/dev/pci/if_bnxtreg.h

80194

uint32_t timestamp;

sys/dev/pci/if_bnxtreg.h

80269

uint32_t remote_key;

sys/dev/pci/if_bnxtreg.h

80284

uint32_t data[24];

sys/dev/pci/if_bnxtreg.h

80352

uint32_t remote_key;

sys/dev/pci/if_bnxtreg.h

80423

uint32_t inv_l_key;

sys/dev/pci/if_bnxtreg.h

80427

uint32_t data[24];

sys/dev/pci/if_bnxtreg.h

80489

uint32_t inv_l_key;

sys/dev/pci/if_bnxtreg.h

80632

uint32_t l_key;

sys/dev/pci/if_bnxtreg.h

80734

uint32_t data[24];

sys/dev/pci/if_bnxtreg.h

80875

uint32_t l_key;

sys/dev/pci/if_bnxtreg.h

81116

uint32_t l_key;

sys/dev/pci/if_bnxtreg.h

81118

uint32_t length;

sys/dev/pci/if_bnxtreg.h

81222

uint32_t data[24];

sys/dev/pci/if_bnxtreg.h

8133

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

81363

uint32_t l_key;

sys/dev/pci/if_bnxtreg.h

81365

uint32_t length;

sys/dev/pci/if_bnxtreg.h

81607

uint32_t parent_l_key;

sys/dev/pci/if_bnxtreg.h

81613

uint32_t l_key;

sys/dev/pci/if_bnxtreg.h

81623

uint32_t data[24];

sys/dev/pci/if_bnxtreg.h

81763

uint32_t parent_l_key;

sys/dev/pci/if_bnxtreg.h

81769

uint32_t l_key;

sys/dev/pci/if_bnxtreg.h

81805

uint32_t wqe_opaque;

sys/dev/pci/if_bnxtreg.h

81923

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

81930

uint32_t inv_key_or_imm_data;

sys/dev/pci/if_bnxtreg.h

81931

uint32_t timestamp;

sys/dev/pci/if_bnxtreg.h

81947

uint32_t data[28];

sys/dev/pci/if_bnxtreg.h

82053

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

82060

uint32_t inv_key_or_imm_data;

sys/dev/pci/if_bnxtreg.h

82061

uint32_t timestamp;

sys/dev/pci/if_bnxtreg.h

82162

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

82257

uint32_t cfa_meta;

sys/dev/pci/if_bnxtreg.h

82302

uint32_t timestamp;

sys/dev/pci/if_bnxtreg.h

82319

uint32_t data[24];

sys/dev/pci/if_bnxtreg.h

8236

uint32_t rss_hash;

sys/dev/pci/if_bnxtreg.h

82413

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

8248

uint32_t flags2;

sys/dev/pci/if_bnxtreg.h

82508

uint32_t cfa_meta;

sys/dev/pci/if_bnxtreg.h

82553

uint32_t timestamp;

sys/dev/pci/if_bnxtreg.h

82663

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

82668

uint32_t imm_data;

sys/dev/pci/if_bnxtreg.h

82678

uint32_t q_key;

sys/dev/pci/if_bnxtreg.h

82686

uint32_t dst_qp;

sys/dev/pci/if_bnxtreg.h

82689

uint32_t avid;

sys/dev/pci/if_bnxtreg.h

82696

uint32_t reserved2;

sys/dev/pci/if_bnxtreg.h

82697

uint32_t timestamp;

sys/dev/pci/if_bnxtreg.h

82713

uint32_t data[24];

sys/dev/pci/if_bnxtreg.h

82815

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

82820

uint32_t imm_data;

sys/dev/pci/if_bnxtreg.h

82830

uint32_t q_key;

sys/dev/pci/if_bnxtreg.h

82838

uint32_t dst_qp;

sys/dev/pci/if_bnxtreg.h

82841

uint32_t avid;

sys/dev/pci/if_bnxtreg.h

82848

uint32_t reserved2;

sys/dev/pci/if_bnxtreg.h

82849

uint32_t timestamp;

sys/dev/pci/if_bnxtreg.h

82960

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

82965

uint32_t imm_data;

sys/dev/pci/if_bnxtreg.h

82966

uint32_t reserved2;

sys/dev/pci/if_bnxtreg.h

82974

uint32_t remote_key;

sys/dev/pci/if_bnxtreg.h

82975

uint32_t timestamp;

sys/dev/pci/if_bnxtreg.h

82991

uint32_t data[24];

sys/dev/pci/if_bnxtreg.h

83095

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

83100

uint32_t imm_data;

sys/dev/pci/if_bnxtreg.h

83101

uint32_t reserved2;

sys/dev/pci/if_bnxtreg.h

83109

uint32_t remote_key;

sys/dev/pci/if_bnxtreg.h

83110

uint32_t timestamp;

sys/dev/pci/if_bnxtreg.h

83190

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

83196

uint32_t remote_key;

sys/dev/pci/if_bnxtreg.h

83197

uint32_t reserved2;

sys/dev/pci/if_bnxtreg.h

83230

uint32_t l_key;

sys/dev/pci/if_bnxtreg.h

83237

uint32_t size;

sys/dev/pci/if_bnxtreg.h

83310

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

83316

uint32_t remote_key;

sys/dev/pci/if_bnxtreg.h

83317

uint32_t reserved2;

sys/dev/pci/if_bnxtreg.h

83404

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

83410

uint32_t inv_l_key;

sys/dev/pci/if_bnxtreg.h

83411

uint32_t reserved2;

sys/dev/pci/if_bnxtreg.h

83481

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

83487

uint32_t inv_l_key;

sys/dev/pci/if_bnxtreg.h

83488

uint32_t reserved2;

sys/dev/pci/if_bnxtreg.h

83582

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

83588

uint32_t l_key;

sys/dev/pci/if_bnxtreg.h

8372

uint32_t metadata2;

sys/dev/pci/if_bnxtreg.h

83853

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

83859

uint32_t l_key;

sys/dev/pci/if_bnxtreg.h

84177

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

84183

uint32_t parent_l_key;

sys/dev/pci/if_bnxtreg.h

84189

uint32_t l_key;

sys/dev/pci/if_bnxtreg.h

84338

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

84344

uint32_t parent_l_key;

sys/dev/pci/if_bnxtreg.h

8435

uint32_t hdr_offsets;

sys/dev/pci/if_bnxtreg.h

84350

uint32_t l_key;

sys/dev/pci/if_bnxtreg.h

84431

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

84435

uint32_t reserved_3;

sys/dev/pci/if_bnxtreg.h

84503

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

84507

uint32_t reserved_3;

sys/dev/pci/if_bnxtreg.h

84534

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

84548

uint32_t data[24];

sys/dev/pci/if_bnxtreg.h

84575

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

84610

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

84616

uint32_t data[124];

sys/dev/pci/if_bnxtreg.h

84642

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

84870

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

84890

uint32_t reserved32_2;

sys/dev/pci/if_bnxtreg.h

84947

uint32_t reserved32_1;

sys/dev/pci/if_bnxtreg.h

84958

uint32_t length;

sys/dev/pci/if_bnxtreg.h

84963

uint32_t imm_data_or_inv_r_key;

sys/dev/pci/if_bnxtreg.h

85035

uint32_t srq_or_rq_wr_id;

sys/dev/pci/if_bnxtreg.h

85070

uint32_t imm_data;

sys/dev/pci/if_bnxtreg.h

85205

uint32_t src_qp_high_srq_or_rq_wr_id;

sys/dev/pci/if_bnxtreg.h

85240

uint32_t imm_data;

sys/dev/pci/if_bnxtreg.h

85373

uint32_t src_qp_high_srq_or_rq_wr_id;

sys/dev/pci/if_bnxtreg.h

85423

uint32_t imm_data;

sys/dev/pci/if_bnxtreg.h

85424

uint32_t qid;

sys/dev/pci/if_bnxtreg.h

85436

uint32_t cfa_metadata;

sys/dev/pci/if_bnxtreg.h

8556

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

85586

uint32_t src_qp_high_srq_or_rq_wr_id;

sys/dev/pci/if_bnxtreg.h

85621

uint32_t imm_data;

sys/dev/pci/if_bnxtreg.h

85622

uint32_t qid;

sys/dev/pci/if_bnxtreg.h

85642

uint32_t cfa_metadata2;

sys/dev/pci/if_bnxtreg.h

85772

uint32_t src_qp_high_srq_or_rq_wr_id;

sys/dev/pci/if_bnxtreg.h

86030

uint32_t raweth_qp1_flags2;

sys/dev/pci/if_bnxtreg.h

8611

uint32_t tsdelta;

sys/dev/pci/if_bnxtreg.h

86130

uint32_t raweth_qp1_metadata;

sys/dev/pci/if_bnxtreg.h

86204

uint32_t raweth_qp1_payload_offset_srq_or_rq_wr_id;

sys/dev/pci/if_bnxtreg.h

8623

uint32_t tpa_dup_acks;

sys/dev/pci/if_bnxtreg.h

86452

uint32_t raweth_qp1_flags2;

sys/dev/pci/if_bnxtreg.h

86561

uint32_t cfa_metadata2;

sys/dev/pci/if_bnxtreg.h

86622

uint32_t raweth_qp1_payload_offset_srq_or_rq_wr_id;

sys/dev/pci/if_bnxtreg.h

86683

uint32_t reserved32_1;

sys/dev/pci/if_bnxtreg.h

86707

uint32_t reserved32_2;

sys/dev/pci/if_bnxtreg.h

86752

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

86784

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

86816

uint32_t reserved2;

sys/dev/pci/if_bnxtreg.h

8691

uint32_t start_opaque;

sys/dev/pci/if_bnxtreg.h

86957

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

86984

uint32_t length;

sys/dev/pci/if_bnxtreg.h

86989

uint32_t imm_data_or_inv_r_key;

sys/dev/pci/if_bnxtreg.h

87117

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

87151

uint32_t imm_data;

sys/dev/pci/if_bnxtreg.h

87255

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

87509

uint32_t raweth_qp1_flags2;

sys/dev/pci/if_bnxtreg.h

87635

uint32_t cfa_metadata2;

sys/dev/pci/if_bnxtreg.h

87722

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

87766

uint32_t imm_data;

sys/dev/pci/if_bnxtreg.h

87767

uint32_t qid_cfa_metadata1_src_qp_high;

sys/dev/pci/if_bnxtreg.h

87799

uint32_t cfa_metadata2;

sys/dev/pci/if_bnxtreg.h

8793

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

87966

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

88001

uint32_t info32;

sys/dev/pci/if_bnxtreg.h

88050

uint32_t cq_handle_low;

sys/dev/pci/if_bnxtreg.h

88051

uint32_t v;

sys/dev/pci/if_bnxtreg.h

88062

uint32_t cq_handle_high;

sys/dev/pci/if_bnxtreg.h

88102

uint32_t srq_handle_low;

sys/dev/pci/if_bnxtreg.h

88103

uint32_t v;

sys/dev/pci/if_bnxtreg.h

88115

uint32_t srq_handle_high;

sys/dev/pci/if_bnxtreg.h

88151

uint32_t db_dpi;

sys/dev/pci/if_bnxtreg.h

88158

uint32_t v;

sys/dev/pci/if_bnxtreg.h

88165

uint32_t db_type_db_xid;

sys/dev/pci/if_bnxtreg.h

88206

uint32_t cq_handle_low;

sys/dev/pci/if_bnxtreg.h

88207

uint32_t v;

sys/dev/pci/if_bnxtreg.h

88218

uint32_t cq_handle_high;

sys/dev/pci/if_bnxtreg.h

88241

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

88242

uint32_t psn;

sys/dev/pci/if_bnxtreg.h

88246

uint32_t msn;

sys/dev/pci/if_bnxtreg.h

88266

uint32_t rdma_r_key;

sys/dev/pci/if_bnxtreg.h

88271

uint32_t length;

sys/dev/pci/if_bnxtreg.h

88314

uint32_t length;

sys/dev/pci/if_bnxtreg.h

88315

uint32_t psn;

sys/dev/pci/if_bnxtreg.h

88319

uint32_t end_psn;

sys/dev/pci/if_bnxtreg.h

88338

uint32_t single_sge_l_key;

sys/dev/pci/if_bnxtreg.h

88340

uint32_t single_sge_size;

sys/dev/pci/if_bnxtreg.h

88414

uint32_t index;

sys/dev/pci/if_bnxtreg.h

88457

uint32_t type_path_xid;

sys/dev/pci/if_bnxtreg.h

8847

uint32_t rss_hash;

sys/dev/pci/if_bnxtreg.h

8859

uint32_t flags2;

sys/dev/pci/if_bnxtreg.h

88804

uint32_t type_abs_incr_xid;

sys/dev/pci/if_bnxtreg.h

89033

uint32_t push_size_push_index;

sys/dev/pci/if_bnxtreg.h

89059

uint32_t reserved32;

sys/dev/pci/if_bnxtreg.h

89076

uint32_t index;

sys/dev/pci/if_bnxtreg.h

89272

uint32_t xid;

sys/dev/pci/if_bnxtreg.h

89357

uint32_t db_format_linked_last_valid_stride_size;

sys/dev/pci/if_bnxtreg.h

89426

uint32_t pi;

sys/dev/pci/if_bnxtreg.h

89553

uint32_t index;

sys/dev/pci/if_bnxtreg.h

8958

uint32_t metadata;

sys/dev/pci/if_bnxtreg.h

89602

uint32_t type_path_xid;

sys/dev/pci/if_bnxtreg.h

89812

uint32_t reserved;

sys/dev/pci/if_bnxtreg.h

89813

uint32_t type_xid;

sys/dev/pci/if_bnxtreg.h

89859

uint32_t wqe[14];

sys/dev/pci/if_bnxtreg.h

89871

uint32_t fw_status;

sys/dev/pci/if_bnxtreg.h

89992

uint32_t sig_ver;

sys/dev/pci/if_bnxtreg.h

90009

uint32_t fw_status_loc;

sys/dev/pci/if_bnxtreg.h

9015

uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;

sys/dev/pci/if_bnxtreg.h

90381

uint32_t resp_data_offset;

sys/dev/pci/if_bnxtreg.h

90590

uint32_t fru_lock;

sys/dev/pci/if_bnxtreg.h

90591

uint32_t unused_0;

sys/dev/pci/if_bnxtreg.h

90671

uint32_t us_tick;

sys/dev/pci/if_bnxtreg.h

90677

uint32_t ms_tick;

sys/dev/pci/if_bnxtreg.h

90683

uint32_t ms100_tick;

sys/dev/pci/if_bnxtreg.h

90881

uint32_t enc_device_type;

sys/dev/pci/if_bnxtreg.h

91198

uint32_t image_signature;

sys/dev/pci/if_bnxtreg.h

91203

uint32_t image_type;

sys/dev/pci/if_bnxtreg.h

91211

uint32_t image_offset;

sys/dev/pci/if_bnxtreg.h

91216

uint32_t image_length;

sys/dev/pci/if_bnxtreg.h

91236

uint32_t entrypoint_offset;

sys/dev/pci/if_bnxtreg.h

91237

uint32_t flags;

sys/dev/pci/if_bnxtreg.h

91256

uint32_t seq_number;

sys/dev/pci/if_bnxtreg.h

91258

uint32_t reserved1;

sys/dev/pci/if_bnxtreg.h

91321

uint32_t reserved1;

sys/dev/pci/if_bnxtreg.h

91323

uint32_t reserved2;

sys/dev/pci/if_bnxtreg.h

91341

uint32_t primate_flags;

sys/dev/pci/if_bnxtreg.h

91343

uint32_t reserved1;

sys/dev/pci/if_bnxtreg.h

91345

uint32_t ap_status;

sys/dev/pci/if_bnxtreg.h

91350

uint32_t crmu_status;

sys/dev/pci/if_bnxtreg.h

91356

uint32_t image_signature;

sys/dev/pci/if_bnxtreg.h

91362

uint32_t image_command;

sys/dev/pci/if_bnxtreg.h

91423

uint32_t unused_1;

sys/dev/pci/if_bnxtreg.h

91438

uint32_t total_data_len;

sys/dev/pci/if_bnxtreg.h

91506

uint32_t data_len;

sys/dev/pci/if_bnxtreg.h

91508

uint32_t offset;

sys/dev/pci/if_bnxtreg.h

91523

uint32_t total_data_len;

sys/dev/pci/if_bnxtreg.h

9154

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

91586

uint32_t health_status;

sys/dev/pci/if_bnxtreg.h

9183

uint32_t tsdelta;

sys/dev/pci/if_bnxtreg.h

92161

uint32_t reserved1;

sys/dev/pci/if_bnxtreg.h

92163

uint32_t reserved2;

sys/dev/pci/if_bnxtreg.h

92197

uint32_t silicon_id;

sys/dev/pci/if_bnxtreg.h

92285

uint32_t peripheral_tests;

sys/dev/pci/if_bnxtreg.h

92361

uint32_t peripheral_tests;

sys/dev/pci/if_bnxtreg.h

92412

uint32_t peripheral_requested_tests;

sys/dev/pci/if_bnxtreg.h

92434

uint32_t peripheral_tests_success;

sys/dev/pci/if_bnxtreg.h

92506

uint32_t oem_id;

sys/dev/pci/if_bnxtreg.h

92525

uint32_t oem_data[26];

sys/dev/pci/if_bnxtreg.h

92540

uint32_t oem_id;

sys/dev/pci/if_bnxtreg.h

92547

uint32_t oem_data[18];

sys/dev/pci/if_bnxtreg.h

92595

uint32_t opaque[32];

sys/dev/pci/if_bnxtreg.h

92609

uint32_t opaque[32];

sys/dev/pci/if_bnxtreg.h

92742

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

9286

uint32_t start_opaque;

sys/dev/pci/if_bnxtreg.h

92878

uint32_t enables;

sys/dev/pci/if_bnxtreg.h

92914

uint32_t tx_stats_record;

sys/dev/pci/if_bnxtreg.h

92919

uint32_t rx_stats_record;

sys/dev/pci/if_bnxtreg.h

93016

uint32_t dest_ip[4];

sys/dev/pci/if_bnxtreg.h

93021

uint32_t src_qp_num;

sys/dev/pci/if_bnxtreg.h

93023

uint32_t dest_qp_num;

sys/dev/pci/if_bnxtreg.h

93028

uint32_t tx_stats_record;

sys/dev/pci/if_bnxtreg.h

93033

uint32_t rx_stats_record;

sys/dev/pci/if_bnxtreg.h

93098

uint32_t min_rtt_ns;

sys/dev/pci/if_bnxtreg.h

93100

uint32_t max_rtt_ns;

sys/dev/pci/if_bnxtreg.h

93105

uint32_t cur_rate_mbps;

sys/dev/pci/if_bnxtreg.h

93110

uint32_t tx_event_count;

sys/dev/pci/if_bnxtreg.h

93115

uint32_t cnp_rx_event_count;

sys/dev/pci/if_bnxtreg.h

93120

uint32_t rtt_req_count;

sys/dev/pci/if_bnxtreg.h

93125

uint32_t rtt_resp_count;

sys/dev/pci/if_bnxtreg.h

93127

uint32_t tx_bytes_count;

sys/dev/pci/if_bnxtreg.h

93129

uint32_t tx_packets_count;

sys/dev/pci/if_bnxtreg.h

93131

uint32_t init_probes_sent;

sys/dev/pci/if_bnxtreg.h

93133

uint32_t term_probes_recv;

sys/dev/pci/if_bnxtreg.h

93135

uint32_t cnp_packets_recv;

sys/dev/pci/if_bnxtreg.h

93137

uint32_t rto_event_recv;

sys/dev/pci/if_bnxtreg.h

93139

uint32_t seq_err_nak_recv;

sys/dev/pci/if_bnxtreg.h

93141

uint32_t qp_count;

sys/dev/pci/if_bnxtreg.h

93143

uint32_t tx_event_detect_count;

sys/dev/pci/if_bnxtreg.h

93203

uint32_t arg_len;

sys/dev/pci/if_bnxtreg.h

93211

uint32_t cfg_len;

sys/dev/pci/if_bnxtreg.h

9326

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

93290

uint32_t arg_len;

sys/dev/pci/if_bnxtreg.h

93298

uint32_t cfg_host_buf_size;

sys/dev/pci/if_bnxtreg.h

93323

uint32_t cfg_len;

sys/dev/pci/if_bnxtreg.h

93383

uint32_t arg_len;

sys/dev/pci/if_bnxtreg.h

93391

uint32_t data_host_buf_size;

sys/dev/pci/if_bnxtreg.h

9340

uint32_t unused_1;

sys/dev/pci/if_bnxtreg.h

93416

uint32_t data_len;

sys/dev/pci/if_bnxtreg.h

9376

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

9377

uint32_t v;

sys/dev/pci/if_bnxtreg.h

9385

uint32_t unused_2;

sys/dev/pci/if_bnxtreg.h

9392

uint32_t downstream_path_type;

sys/dev/pci/if_bnxtreg.h

9423

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

9424

uint32_t v;

sys/dev/pci/if_bnxtreg.h

9432

uint32_t unused_3;

sys/dev/pci/if_bnxtreg.h

9472

uint32_t opaque;

sys/dev/pci/if_bnxtreg.h

9510

uint32_t unused_2;

sys/dev/pci/if_bnxtreg.h

9535

uint32_t unused_1;

sys/dev/pci/if_bnxtreg.h

9536

uint32_t v;

sys/dev/pci/if_bnxtreg.h

9544

uint32_t unused_3;

sys/dev/pci/if_bnxtreg.h

9582

uint32_t unused0;

sys/dev/pci/if_bnxtreg.h

9865

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

9881

uint32_t event_data1;

sys/dev/pci/if_bnxtreg.h

9966

uint32_t event_data2;

sys/dev/pci/if_bnxtreg.h

9982

uint32_t event_data1;

sys/dev/pci/if_bwfm_pci.c

1008

uint32_t coreid, base, words;

sys/dev/pci/if_bwfm_pci.c

1009

uint32_t page, offset, sromctl;

sys/dev/pci/if_bwfm_pci.c

1099

if (size < sizeof(uint32_t))

sys/dev/pci/if_bwfm_pci.c

1104

size -= sizeof(uint32_t);

sys/dev/pci/if_bwfm_pci.c

1105

data += sizeof(uint32_t);

sys/dev/pci/if_bwfm_pci.c

112

uint32_t npkt;

sys/dev/pci/if_bwfm_pci.c

1249

struct mbuf *m, uint32_t *pktid, paddr_t *paddr)

sys/dev/pci/if_bwfm_pci.c

1282

uint32_t pktid)

sys/dev/pci/if_bwfm_pci.c

1309

uint32_t msgtype)

sys/dev/pci/if_bwfm_pci.c

1313

uint32_t pktid;

sys/dev/pci/if_bwfm_pci.c

1352

uint32_t pktid;

sys/dev/pci/if_bwfm_pci.c

1389

int nitem, size_t itemsz, uint32_t w_idx, uint32_t r_idx,

sys/dev/pci/if_bwfm_pci.c

139

uint32_t sc_shared_address;

sys/dev/pci/if_bwfm_pci.c

1390

int idx, uint32_t idx_off, uint32_t *ring_mem)

sys/dev/pci/if_bwfm_pci.c

140

uint32_t sc_shared_flags;

sys/dev/pci/if_bwfm_pci.c

148

uint32_t sc_rx_dataoffset;

sys/dev/pci/if_bwfm_pci.c

149

uint32_t sc_htod_mb_data_addr;

sys/dev/pci/if_bwfm_pci.c

150

uint32_t sc_dtoh_mb_data_addr;

sys/dev/pci/if_bwfm_pci.c

151

uint32_t sc_ring_info_addr;

sys/dev/pci/if_bwfm_pci.c

153

uint32_t sc_console_base_addr;

sys/dev/pci/if_bwfm_pci.c

154

uint32_t sc_console_buf_addr;

sys/dev/pci/if_bwfm_pci.c

155

uint32_t sc_console_buf_size;

sys/dev/pci/if_bwfm_pci.c

156

uint32_t sc_console_readidx;

sys/dev/pci/if_bwfm_pci.c

1822

uint32_t

sys/dev/pci/if_bwfm_pci.c

1823

bwfm_pci_buscore_read(struct bwfm_softc *bwfm, uint32_t reg)

sys/dev/pci/if_bwfm_pci.c

1826

uint32_t page, offset;

sys/dev/pci/if_bwfm_pci.c

1835

bwfm_pci_buscore_write(struct bwfm_softc *bwfm, uint32_t reg, uint32_t val)

sys/dev/pci/if_bwfm_pci.c

1838

uint32_t page, offset;

sys/dev/pci/if_bwfm_pci.c

1857

uint32_t reg;

sys/dev/pci/if_bwfm_pci.c

1913

bwfm_pci_buscore_activate(struct bwfm_softc *bwfm, uint32_t rstvec)

sys/dev/pci/if_bwfm_pci.c

216

uint32_t bwfm_pci_intr_status(struct bwfm_pci_softc *);

sys/dev/pci/if_bwfm_pci.c

217

void bwfm_pci_intr_ack(struct bwfm_pci_softc *, uint32_t);

sys/dev/pci/if_bwfm_pci.c

218

uint32_t bwfm_pci_intmask(struct bwfm_pci_softc *);

sys/dev/pci/if_bwfm_pci.c

2200

uint32_t pktid;

sys/dev/pci/if_bwfm_pci.c

2263

bwfm_pci_send_mb_data(struct bwfm_pci_softc *sc, uint32_t htod_mb_data)

sys/dev/pci/if_bwfm_pci.c

2267

uint32_t reg;

sys/dev/pci/if_bwfm_pci.c

2299

uint32_t reg;

sys/dev/pci/if_bwfm_pci.c

232

uint32_t *, paddr_t *);

sys/dev/pci/if_bwfm_pci.c

2323

uint32_t newidx = bus_space_read_4(sc->sc_tcm_iot, sc->sc_tcm_ioh,

sys/dev/pci/if_bwfm_pci.c

234

struct bwfm_pci_pkts *, uint32_t);

sys/dev/pci/if_bwfm_pci.c

2347

uint32_t status, mask;

sys/dev/pci/if_bwfm_pci.c

236

struct if_rxring *, uint32_t);

sys/dev/pci/if_bwfm_pci.c

240

int, size_t, uint32_t, uint32_t, int, uint32_t, uint32_t *);

sys/dev/pci/if_bwfm_pci.c

2414

uint32_t

sys/dev/pci/if_bwfm_pci.c

2426

bwfm_pci_intr_ack(struct bwfm_pci_softc *sc, uint32_t status)

sys/dev/pci/if_bwfm_pci.c

2436

uint32_t

sys/dev/pci/if_bwfm_pci.c

2470

uint32_t pktid;

sys/dev/pci/if_bwfm_pci.c

2574

bwfm_pci_msgbuf_h2d_mb_write(struct bwfm_pci_softc *sc, uint32_t data)

sys/dev/pci/if_bwfm_pci.c

272

uint32_t bwfm_pci_buscore_read(struct bwfm_softc *, uint32_t);

sys/dev/pci/if_bwfm_pci.c

273

void bwfm_pci_buscore_write(struct bwfm_softc *, uint32_t,

sys/dev/pci/if_bwfm_pci.c

274

uint32_t);

sys/dev/pci/if_bwfm_pci.c

277

void bwfm_pci_buscore_activate(struct bwfm_softc *, uint32_t);

sys/dev/pci/if_bwfm_pci.c

292

int bwfm_pci_send_mb_data(struct bwfm_pci_softc *, uint32_t);

sys/dev/pci/if_bwfm_pci.c

306

uint32_t);

sys/dev/pci/if_bwfm_pci.c

439

uint32_t d2h_w_idx_ptr, d2h_r_idx_ptr;

sys/dev/pci/if_bwfm_pci.c

440

uint32_t h2d_w_idx_ptr, h2d_r_idx_ptr;

sys/dev/pci/if_bwfm_pci.c

441

uint32_t idx_offset, reg;

sys/dev/pci/if_bwfm_pci.c

517

uint32_t *ramsize = (uint32_t *)&ucode[BWFM_RAMSIZE];

sys/dev/pci/if_bwfm_pci.c

543

uint32_t host_cap;

sys/dev/pci/if_bwfm_pci.c

566

sc->sc_dma_idx_sz = sizeof(uint32_t);

sys/dev/pci/if_bwfm_pci.c

617

idx_offset = sizeof(uint32_t);

sys/dev/pci/if_bwfm_pci.c

669

uint32_t ring_mem_ptr = letoh32(ringinfo.ringmem);

sys/dev/pci/if_bwfm_pci.c

812

uint32_t addr, shared, written;

sys/dev/pci/if_bwfm_pci.c

83

uint32_t w_idx_addr;

sys/dev/pci/if_bwfm_pci.c

84

uint32_t r_idx_addr;

sys/dev/pci/if_bwfm_pci.c

85

uint32_t w_ptr;

sys/dev/pci/if_bwfm_pci.c

86

uint32_t r_ptr;

sys/dev/pci/if_bwfm_pci.c

867

bwfm_chip_set_active(bwfm, *(uint32_t *)ucode);

sys/dev/pci/if_bwfm_pci.h

164

uint32_t length;

sys/dev/pci/if_bwfm_pci.h

165

uint32_t magic;

sys/dev/pci/if_bwfm_pci.h

169

uint32_t ringmem;

sys/dev/pci/if_bwfm_pci.h

170

uint32_t h2d_w_idx_ptr;

sys/dev/pci/if_bwfm_pci.h

171

uint32_t h2d_r_idx_ptr;

sys/dev/pci/if_bwfm_pci.h

172

uint32_t d2h_w_idx_ptr;

sys/dev/pci/if_bwfm_pci.h

173

uint32_t d2h_r_idx_ptr;

sys/dev/pci/if_bwfm_pci.h

174

uint32_t h2d_w_idx_hostaddr_low;

sys/dev/pci/if_bwfm_pci.h

175

uint32_t h2d_w_idx_hostaddr_high;

sys/dev/pci/if_bwfm_pci.h

176

uint32_t h2d_r_idx_hostaddr_low;

sys/dev/pci/if_bwfm_pci.h

177

uint32_t h2d_r_idx_hostaddr_high;

sys/dev/pci/if_bwfm_pci.h

178

uint32_t d2h_w_idx_hostaddr_low;

sys/dev/pci/if_bwfm_pci.h

179

uint32_t d2h_w_idx_hostaddr_high;

sys/dev/pci/if_bwfm_pci.h

180

uint32_t d2h_r_idx_hostaddr_low;

sys/dev/pci/if_bwfm_pci.h

181

uint32_t d2h_r_idx_hostaddr_high;

sys/dev/pci/if_bwfm_pci.h

221

uint32_t request_id;

sys/dev/pci/if_bwfm_pci.h

225

uint32_t low_addr;

sys/dev/pci/if_bwfm_pci.h

226

uint32_t high_addr;

sys/dev/pci/if_bwfm_pci.h

231

uint32_t cmd;

sys/dev/pci/if_bwfm_pci.h

237

uint32_t rsvd1[2];

sys/dev/pci/if_bwfm_pci.h

251

uint32_t rsvd0;

sys/dev/pci/if_bwfm_pci.h

258

uint32_t rsvd0;

sys/dev/pci/if_bwfm_pci.h

268

uint32_t rsvd1[4];

sys/dev/pci/if_bwfm_pci.h

289

uint32_t cmd;

sys/dev/pci/if_bwfm_pci.h

290

uint32_t rsvd0;

sys/dev/pci/if_bwfm_pci.h

307

uint32_t rx_status_0;

sys/dev/pci/if_bwfm_pci.h

308

uint32_t rx_status_1;

sys/dev/pci/if_bwfm_pci.h

309

uint32_t rsvd0;

sys/dev/pci/if_bwfm_pci.h

331

uint32_t rsvd0[7];

sys/dev/pci/if_bwfm_pci.h

337

uint32_t rsvd0[3];

sys/dev/pci/if_bwfm_pci.h

343

uint32_t rsvd0[3];

sys/dev/pci/if_bwfm_pci.h

349

uint32_t rsvd0[3];

sys/dev/pci/if_bwfm_pci.h

354

uint32_t data;

sys/dev/pci/if_bwfm_pci.h

355

uint32_t rsvd0[7];

sys/dev/pci/if_bwfm_pci.h

361

uint32_t data;

sys/dev/pci/if_bwfm_pci.h

362

uint32_t rsvd0[2];

sys/dev/pci/if_bwi_pci.c

234

bwi_pci_conf_write(void *self, uint32_t reg, uint32_t val)

sys/dev/pci/if_bwi_pci.c

241

uint32_t

sys/dev/pci/if_bwi_pci.c

242

bwi_pci_conf_read(void *self, uint32_t reg)

sys/dev/pci/if_bwi_pci.c

55

void bwi_pci_conf_write(void *, uint32_t, uint32_t);

sys/dev/pci/if_bwi_pci.c

56

uint32_t bwi_pci_conf_read(void *, uint32_t);

sys/dev/pci/if_em.c

1424

uint32_t tctl;

sys/dev/pci/if_em.c

1684

uint32_t reg;

sys/dev/pci/if_em.c

1883

uint32_t ret_val;

sys/dev/pci/if_em.c

2369

uint32_t reg_val;

sys/dev/pci/if_em.c

2437

uint32_t vlan_macip_lens = 0, type_tucmd_mlhl = 0, mss_l4len_idx = 0;

sys/dev/pci/if_em.c

2445

uint32_t vtag = mp->m_pkthdr.ether_vtag;

sys/dev/pci/if_em.c

2504

uint32_t vlan_macip_lens = 0, type_tucmd_mlhl = 0, mss_l4len_idx = 0;

sys/dev/pci/if_em.c

2513

uint32_t vtag = mp->m_pkthdr.ether_vtag;

sys/dev/pci/if_em.c

2939

uint32_t reg;

sys/dev/pci/if_em.c

3273

uint32_t ctrl;

sys/dev/pci/if_em.c

3283

uint32_t mask;

sys/dev/pci/if_em.c

329

void em_tbi_adjust_stats(struct em_softc *, uint32_t, uint8_t *);

sys/dev/pci/if_em.c

3316

em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)

sys/dev/pci/if_em.c

3333

em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)

sys/dev/pci/if_em.c

3368

em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value)

sys/dev/pci/if_em.c

3482

uint32_t tctl, txd_lower = E1000_TXD_CMD_IFCS;

sys/dev/pci/if_em.c

3519

uint32_t rctl, rxdctl;

sys/dev/pci/if_em.c

3559

uint32_t fextnvm11, tdlen;

sys/dev/pci/if_em.c

3677

uint32_t reg;

sys/dev/pci/if_em.c

3798

uint32_t lo, hi;

sys/dev/pci/if_em.c

3892

em_tbi_adjust_stats(struct em_softc *sc, uint32_t frame_len, uint8_t *mac_addr)

sys/dev/pci/if_em.c

4064

uint32_t icr;

sys/dev/pci/if_em.c

4090

uint32_t ivar, newitr, index;

sys/dev/pci/if_em.c

562

uint32_t reg = EM_READ_REG(&sc->hw, E1000_STATUS);

sys/dev/pci/if_em.c

864

uint32_t pba;

sys/dev/pci/if_em.h

366

uint32_t me; /* queue index, also msix vector */

sys/dev/pci/if_em.h

367

uint32_t eims; /* msix only */

sys/dev/pci/if_em.h

452

uint32_t msix_linkvec;

sys/dev/pci/if_em.h

453

uint32_t msix_linkmask;

sys/dev/pci/if_em.h

454

uint32_t msix_queuesmask;

sys/dev/pci/if_em_hw.c

100

static int32_t em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t);

sys/dev/pci/if_em_hw.c

10017

em_valid_nvm_bank_detect_ich8lan(struct em_hw *hw, uint32_t *bank)

sys/dev/pci/if_em_hw.c

10019

uint32_t eecd;

sys/dev/pci/if_em_hw.c

10020

uint32_t bank1_offset = hw->flash_bank_size * sizeof(uint16_t);

sys/dev/pci/if_em_hw.c

10021

uint32_t act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;

sys/dev/pci/if_em_hw.c

10022

uint32_t nvm_dword = 0;

sys/dev/pci/if_em_hw.c

101

static int32_t em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *);

sys/dev/pci/if_em_hw.c

10115

uint32_t flash_bank = 0;

sys/dev/pci/if_em_hw.c

10116

uint32_t act_offset = 0;

sys/dev/pci/if_em_hw.c

10117

uint32_t bank_offset = 0;

sys/dev/pci/if_em_hw.c

10118

uint32_t dword = 0;

sys/dev/pci/if_em_hw.c

102

static int32_t em_read_ich8_dword(struct em_hw *, uint32_t, uint32_t *);

sys/dev/pci/if_em_hw.c

10210

uint32_t flash_bank = 0;

sys/dev/pci/if_em_hw.c

10211

uint32_t act_offset = 0;

sys/dev/pci/if_em_hw.c

10212

uint32_t bank_offset = 0;

sys/dev/pci/if_em_hw.c

10276

uint32_t i = 0;

sys/dev/pci/if_em_hw.c

103

static int32_t em_read_ich8_data(struct em_hw *, uint32_t, uint32_t,

sys/dev/pci/if_em_hw.c

10421

em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout)

sys/dev/pci/if_em_hw.c

10426

uint32_t i = 0;

sys/dev/pci/if_em_hw.c

10439

(uint32_t)hsflctl.regval << 16);

sys/dev/pci/if_em_hw.c

10472

em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size,

sys/dev/pci/if_em_hw.c

10477

uint32_t flash_linear_address;

sys/dev/pci/if_em_hw.c

10478

uint32_t flash_data = 0;

sys/dev/pci/if_em_hw.c

105

static int32_t em_write_ich8_data(struct em_hw *, uint32_t, uint32_t,

sys/dev/pci/if_em_hw.c

10553

em_read_ich8_data32(struct em_hw *hw, uint32_t offset, uint32_t *data)

sys/dev/pci/if_em_hw.c

10557

uint32_t flash_linear_address;

sys/dev/pci/if_em_hw.c

10559

uint32_t count = 0;

sys/dev/pci/if_em_hw.c

10580

hsflctl.hsf_ctrl.fldbcount = sizeof(uint32_t) - 1;

sys/dev/pci/if_em_hw.c

10584

(uint32_t)hsflctl.regval << 16);

sys/dev/pci/if_em_hw.c

10602

(*data) = (uint32_t)E1000_READ_ICH_FLASH_REG32(hw,

sys/dev/pci/if_em_hw.c

10638

em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size,

sys/dev/pci/if_em_hw.c

10643

uint32_t flash_linear_address;

sys/dev/pci/if_em_hw.c

10644

uint32_t flash_data = 0;

sys/dev/pci/if_em_hw.c

10680

flash_data = (uint32_t) data & 0x00FF;

sys/dev/pci/if_em_hw.c

10682

flash_data = (uint32_t) data;

sys/dev/pci/if_em_hw.c

10723

em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data)

sys/dev/pci/if_em_hw.c

10748

em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte)

sys/dev/pci/if_em_hw.c

10781

em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data)

sys/dev/pci/if_em_hw.c

10798

em_read_ich8_dword(struct em_hw *hw, uint32_t index, uint32_t *data)

sys/dev/pci/if_em_hw.c

10813

em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data)

sys/dev/pci/if_em_hw.c

10832

em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank)

sys/dev/pci/if_em_hw.c

10836

uint32_t flash_linear_address;

sys/dev/pci/if_em_hw.c

10867

uint32_t gfpreg, sector_base_addr, sector_end_addr;

sys/dev/pci/if_em_hw.c

11050

uint32_t invm_dword;

sys/dev/pci/if_em_hw.c

11078

em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr,

sys/dev/pci/if_em_hw.c

11079

uint32_t cnf_size)

sys/dev/pci/if_em_hw.c

11081

uint32_t ret_val = E1000_SUCCESS;

sys/dev/pci/if_em_hw.c

11104

em_write_phy_reg_ex(hw, (uint32_t) reg_addr, reg_data);

sys/dev/pci/if_em_hw.c

11123

uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask;

sys/dev/pci/if_em_hw.c

11197

uint32_t gcr = E1000_READ_REG(hw, GCR);

sys/dev/pci/if_em_hw.c

11524

uint32_t mac_reg;

sys/dev/pci/if_em_hw.c

11558

uint32_t fextnvm6 = E1000_READ_REG(hw, FEXTNVM6);

sys/dev/pci/if_em_hw.c

11559

uint32_t status = E1000_READ_REG(hw, STATUS);

sys/dev/pci/if_em_hw.c

11635

uint32_t extcnf_ctrl;

sys/dev/pci/if_em_hw.c

11664

uint32_t ctrl_reg = 0;

sys/dev/pci/if_em_hw.c

11665

uint32_t ctrl_ext = 0;

sys/dev/pci/if_em_hw.c

11666

uint32_t reg = 0;

sys/dev/pci/if_em_hw.c

11751

uint32_t ipcnfg, eeer;

sys/dev/pci/if_em_hw.c

118

static int32_t em_set_pci_ex_no_snoop(struct em_hw *, uint32_t);

sys/dev/pci/if_em_hw.c

11898

uint32_t

sys/dev/pci/if_em_hw.c

11899

em_translate_82542_register(uint32_t reg)

sys/dev/pci/if_em_hw.c

1195

uint32_t kab = E1000_READ_REG(hw, KABGTXD);

sys/dev/pci/if_em_hw.c

1201

uint32_t mdicnfg;

sys/dev/pci/if_em_hw.c

121

static void em_write_reg_io(struct em_hw *, uint32_t, uint32_t);

sys/dev/pci/if_em_hw.c

1242

uint32_t reg_ctrl, reg_ctrl_ext;

sys/dev/pci/if_em_hw.c

1243

uint32_t reg_tarc0, reg_tarc1;

sys/dev/pci/if_em_hw.c

1244

uint32_t reg_tctl;

sys/dev/pci/if_em_hw.c

1245

uint32_t reg_txdctl;

sys/dev/pci/if_em_hw.c

129

static void em_raise_mdi_clk(struct em_hw *, uint32_t *);

sys/dev/pci/if_em_hw.c

130

static void em_lower_mdi_clk(struct em_hw *, uint32_t *);

sys/dev/pci/if_em_hw.c

131

static void em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t);

sys/dev/pci/if_em_hw.c

1372

uint32_t mac_reg;

sys/dev/pci/if_em_hw.c

139

static void em_raise_ee_clk(struct em_hw *, uint32_t *);

sys/dev/pci/if_em_hw.c

140

static void em_lower_ee_clk(struct em_hw *, uint32_t *);

sys/dev/pci/if_em_hw.c

142

static int32_t em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t);

sys/dev/pci/if_em_hw.c

1426

uint32_t mac_reg;

sys/dev/pci/if_em_hw.c

143

static int32_t em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *);

sys/dev/pci/if_em_hw.c

152

static uint8_t em_calculate_mng_checksum(char *, uint32_t);

sys/dev/pci/if_em_hw.c

1564

uint32_t ctrl;

sys/dev/pci/if_em_hw.c

1565

uint32_t i;

sys/dev/pci/if_em_hw.c

1571

uint32_t mta_size;

sys/dev/pci/if_em_hw.c

1572

uint32_t reg_data;

sys/dev/pci/if_em_hw.c

1573

uint32_t ctrl_ext;

sys/dev/pci/if_em_hw.c

1574

uint32_t snoop;

sys/dev/pci/if_em_hw.c

1575

uint32_t fwsm;

sys/dev/pci/if_em_hw.c

165

int32_t em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t,

sys/dev/pci/if_em_hw.c

167

int32_t em_access_phy_debug_regs_hv(struct em_hw *, uint32_t,

sys/dev/pci/if_em_hw.c

169

int32_t em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *,

sys/dev/pci/if_em_hw.c

177

int32_t em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *);

sys/dev/pci/if_em_hw.c

1826

uint32_t gcr = E1000_READ_REG(hw, GCR);

sys/dev/pci/if_em_hw.c

1852

uint32_t fflt_dbg = E1000_READ_REG(hw, FFLT_DBG);

sys/dev/pci/if_em_hw.c

1923

uint32_t ctrl_ext;

sys/dev/pci/if_em_hw.c

2095

uint32_t reg;

sys/dev/pci/if_em_hw.c

2128

uint32_t ctrl, ctrl_ext, reg;

sys/dev/pci/if_em_hw.c

2129

uint32_t status;

sys/dev/pci/if_em_hw.c

2130

uint32_t txcw = 0;

sys/dev/pci/if_em_hw.c

2131

uint32_t i;

sys/dev/pci/if_em_hw.c

2132

uint32_t signal = 0;

sys/dev/pci/if_em_hw.c

2329

uint32_t ctrl;

sys/dev/pci/if_em_hw.c

2397

uint32_t led_ctrl;

sys/dev/pci/if_em_hw.c

2555

uint32_t reg_data;

sys/dev/pci/if_em_hw.c

2865

uint32_t led_ctl;

sys/dev/pci/if_em_hw.c

3320

uint32_t tipg;

sys/dev/pci/if_em_hw.c

3356

uint32_t tipg;

sys/dev/pci/if_em_hw.c

3538

uint32_t ctrl;

sys/dev/pci/if_em_hw.c

3873

uint32_t tctl, coll_dist;

sys/dev/pci/if_em_hw.c

3902

uint32_t ctrl;

sys/dev/pci/if_em_hw.c

3962

uint32_t ctrl;

sys/dev/pci/if_em_hw.c

4251

uint32_t rxcw = 0;

sys/dev/pci/if_em_hw.c

4252

uint32_t ctrl;

sys/dev/pci/if_em_hw.c

4253

uint32_t status;

sys/dev/pci/if_em_hw.c

4254

uint32_t rctl;

sys/dev/pci/if_em_hw.c

4255

uint32_t icr;

sys/dev/pci/if_em_hw.c

4256

uint32_t signal = 0;

sys/dev/pci/if_em_hw.c

4560

uint32_t pcs;

sys/dev/pci/if_em_hw.c

4612

uint32_t status;

sys/dev/pci/if_em_hw.c

4730

em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl)

sys/dev/pci/if_em_hw.c

4748

em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl)

sys/dev/pci/if_em_hw.c

4769

em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count)

sys/dev/pci/if_em_hw.c

4771

uint32_t ctrl;

sys/dev/pci/if_em_hw.c

4772

uint32_t mask;

sys/dev/pci/if_em_hw.c

4823

uint32_t ctrl;

sys/dev/pci/if_em_hw.c

4872

uint32_t swfw_sync = 0;

sys/dev/pci/if_em_hw.c

4873

uint32_t swmask = mask;

sys/dev/pci/if_em_hw.c

4874

uint32_t fwmask = mask << 16;

sys/dev/pci/if_em_hw.c

4916

uint32_t swfw_sync;

sys/dev/pci/if_em_hw.c

4917

uint32_t swmask = mask;

sys/dev/pci/if_em_hw.c

4950

em_access_phy_wakeup_reg_bm(struct em_hw *hw, uint32_t reg_addr,

sys/dev/pci/if_em_hw.c

5021

em_access_phy_debug_regs_hv(struct em_hw *hw, uint32_t reg_addr,

sys/dev/pci/if_em_hw.c

5025

uint32_t addr_reg = 0;

sys/dev/pci/if_em_hw.c

5026

uint32_t data_reg = 0;

sys/dev/pci/if_em_hw.c

5065

em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data,

sys/dev/pci/if_em_hw.c

5068

uint32_t ret_val;

sys/dev/pci/if_em_hw.c

5136

em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data)

sys/dev/pci/if_em_hw.c

5138

uint32_t ret_val;

sys/dev/pci/if_em_hw.c

5214

em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data)

sys/dev/pci/if_em_hw.c

5216

uint32_t i;

sys/dev/pci/if_em_hw.c

5217

uint32_t mdic = 0;

sys/dev/pci/if_em_hw.c

5316

em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data)

sys/dev/pci/if_em_hw.c

5318

uint32_t ret_val;

sys/dev/pci/if_em_hw.c

5386

em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data)

sys/dev/pci/if_em_hw.c

5388

uint32_t i;

sys/dev/pci/if_em_hw.c

5389

uint32_t mdic = 0;

sys/dev/pci/if_em_hw.c

5416

mdic = (((uint32_t) phy_data) |

sys/dev/pci/if_em_hw.c

5459

mdic |= (uint32_t) phy_data;

sys/dev/pci/if_em_hw.c

5468

em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data)

sys/dev/pci/if_em_hw.c

5470

uint32_t reg_val;

sys/dev/pci/if_em_hw.c

5493

em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data)

sys/dev/pci/if_em_hw.c

5495

uint32_t reg_val;

sys/dev/pci/if_em_hw.c

5521

uint32_t reg = 0;

sys/dev/pci/if_em_hw.c

5554

em_read_phy_reg_i2c(struct em_hw *hw, uint32_t offset, uint16_t *data)

sys/dev/pci/if_em_hw.c

5556

uint32_t i, i2ccmd = 0;

sys/dev/pci/if_em_hw.c

5601

em_write_phy_reg_i2c(struct em_hw *hw, uint32_t offset, uint16_t data)

sys/dev/pci/if_em_hw.c

5603

uint32_t i, i2ccmd = 0;

sys/dev/pci/if_em_hw.c

5664

uint32_t i = 0;

sys/dev/pci/if_em_hw.c

5665

uint32_t i2ccmd = 0;

sys/dev/pci/if_em_hw.c

5666

uint32_t data_local = 0;

sys/dev/pci/if_em_hw.c

5712

uint32_t ctrl, ctrl_ext;

sys/dev/pci/if_em_hw.c

5713

uint32_t led_ctrl;

sys/dev/pci/if_em_hw.c

5805

uint32_t mac_reg;

sys/dev/pci/if_em_hw.c

59

static int32_t em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *);

sys/dev/pci/if_em_hw.c

60

static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t);

sys/dev/pci/if_em_hw.c

6023

hw->phy_id = (uint32_t) (phy_id_high << 16);

sys/dev/pci/if_em_hw.c

6029

hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);

sys/dev/pci/if_em_hw.c

6030

hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;

sys/dev/pci/if_em_hw.c

6084

uint32_t mdic;

sys/dev/pci/if_em_hw.c

6227

uint32_t ctrl_ext = EM_READ_REG(hw, E1000_CTRL_EXT);

sys/dev/pci/if_em_hw.c

6288

uint32_t eecd = E1000_READ_REG(hw, EECD);

sys/dev/pci/if_em_hw.c

6429

uint32_t flash_size =

sys/dev/pci/if_em_hw.c

6467

uint32_t flash_size = EM_READ_REG(hw, 0xc /* STRAP */);

sys/dev/pci/if_em_hw.c

6542

em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd)

sys/dev/pci/if_em_hw.c

6561

em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd)

sys/dev/pci/if_em_hw.c

6584

uint32_t eecd;

sys/dev/pci/if_em_hw.c

6585

uint32_t mask;

sys/dev/pci/if_em_hw.c

6636

uint32_t eecd;

sys/dev/pci/if_em_hw.c

6637

uint32_t i;

sys/dev/pci/if_em_hw.c

6679

uint32_t eecd, i = 0;

sys/dev/pci/if_em_hw.c

6735

uint32_t eecd;

sys/dev/pci/if_em_hw.c

6782

uint32_t eecd;

sys/dev/pci/if_em_hw.c

6876

uint32_t i = 0;

sys/dev/pci/if_em_hw.c

6985

uint32_t i, eerd = 0;

sys/dev/pci/if_em_hw.c

7017

uint32_t register_value = 0;

sys/dev/pci/if_em_hw.c

7018

uint32_t i = 0;

sys/dev/pci/if_em_hw.c

7053

uint32_t attempts = 100000;

sys/dev/pci/if_em_hw.c

7054

uint32_t i, reg = 0;

sys/dev/pci/if_em_hw.c

7080

uint32_t eecd = 0;

sys/dev/pci/if_em_hw.c

7108

uint32_t eecd;

sys/dev/pci/if_em_hw.c

72

static int32_t em_erase_ich8_4k_segment(struct em_hw *, uint32_t);

sys/dev/pci/if_em_hw.c

7224

uint32_t ctrl_ext;

sys/dev/pci/if_em_hw.c

7394

uint32_t eecd;

sys/dev/pci/if_em_hw.c

745

uint32_t ctrl_ext = 0;

sys/dev/pci/if_em_hw.c

7477

uint32_t attempts = 100000;

sys/dev/pci/if_em_hw.c

7478

uint32_t eecd = 0;

sys/dev/pci/if_em_hw.c

7479

uint32_t flop = 0;

sys/dev/pci/if_em_hw.c

7480

uint32_t i = 0;

sys/dev/pci/if_em_hw.c

7482

uint32_t old_bank_offset = 0;

sys/dev/pci/if_em_hw.c

7483

uint32_t new_bank_offset = 0;

sys/dev/pci/if_em_hw.c

7663

em_read_part_num(struct em_hw *hw, uint32_t *part_num)

sys/dev/pci/if_em_hw.c

7675

*part_num = (uint32_t)eeprom_data << 16;

sys/dev/pci/if_em_hw.c

7750

uint32_t mac_reg;

sys/dev/pci/if_em_hw.c

7840

uint32_t i;

sys/dev/pci/if_em_hw.c

7841

uint32_t rar_num;

sys/dev/pci/if_em_hw.c

7898

uint32_t mc_addr_count, uint32_t pad)

sys/dev/pci/if_em_hw.c

79

static int32_t em_ich8_flash_cycle(struct em_hw *, uint32_t);

sys/dev/pci/if_em_hw.c

7900

uint32_t hash_value;

sys/dev/pci/if_em_hw.c

7901

uint32_t i;

sys/dev/pci/if_em_hw.c

7902

uint32_t num_mta_entry;

sys/dev/pci/if_em_hw.c

7947

uint32_t

sys/dev/pci/if_em_hw.c

7950

uint32_t hash_value = 0;

sys/dev/pci/if_em_hw.c

8020

em_mta_set(struct em_hw *hw, uint32_t hash_value)

sys/dev/pci/if_em_hw.c

8022

uint32_t hash_bit, hash_reg;

sys/dev/pci/if_em_hw.c

8023

uint32_t mta;

sys/dev/pci/if_em_hw.c

8024

uint32_t temp;

sys/dev/pci/if_em_hw.c

8068

em_rar_set(struct em_hw *hw, uint8_t *addr, uint32_t index)

sys/dev/pci/if_em_hw.c

8070

uint32_t rar_low, rar_high;

sys/dev/pci/if_em_hw.c

8075

rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) |

sys/dev/pci/if_em_hw.c

8076

((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));

sys/dev/pci/if_em_hw.c

8077

rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));

sys/dev/pci/if_em_hw.c

81

static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *, uint32_t,

sys/dev/pci/if_em_hw.c

811

uint32_t status, ctrl_ext, mdic;

sys/dev/pci/if_em_hw.c

8122

uint32_t offset;

sys/dev/pci/if_em_hw.c

8123

uint32_t vfta_value = 0;

sys/dev/pci/if_em_hw.c

8124

uint32_t vfta_offset = 0;

sys/dev/pci/if_em_hw.c

8125

uint32_t vfta_bit_in_reg = 0;

sys/dev/pci/if_em_hw.c

8165

uint32_t offset;

sys/dev/pci/if_em_hw.c

8178

uint32_t ledctl;

sys/dev/pci/if_em_hw.c

8179

const uint32_t ledctl_mask = 0x000000FF;

sys/dev/pci/if_em_hw.c

8180

const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;

sys/dev/pci/if_em_hw.c

8181

const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;

sys/dev/pci/if_em_hw.c

82

uint32_t);

sys/dev/pci/if_em_hw.c

8259

volatile uint32_t temp;

sys/dev/pci/if_em_hw.c

8390

uint32_t status;

sys/dev/pci/if_em_hw.c

8479

em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value)

sys/dev/pci/if_em_hw.c

8802

uint32_t idle_errs = 0;

sys/dev/pci/if_em_hw.c

8991

uint32_t phy_ctrl = 0;

sys/dev/pci/if_em_hw.c

9127

uint32_t phy_ctrl = 0;

sys/dev/pci/if_em_hw.c

928

uint32_t ctrl;

sys/dev/pci/if_em_hw.c

929

uint32_t ctrl_ext;

sys/dev/pci/if_em_hw.c

930

uint32_t icr;

sys/dev/pci/if_em_hw.c

931

uint32_t manc;

sys/dev/pci/if_em_hw.c

9316

uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;

sys/dev/pci/if_em_hw.c

932

uint32_t led_ctrl;

sys/dev/pci/if_em_hw.c

9322

*((uint32_t *) buffer + i) =

sys/dev/pci/if_em_hw.c

933

uint32_t timeout;

sys/dev/pci/if_em_hw.c

934

uint32_t extcnf_ctrl;

sys/dev/pci/if_em_hw.c

9340

uint32_t hicr;

sys/dev/pci/if_em_hw.c

9371

uint32_t fwsm;

sys/dev/pci/if_em_hw.c

9391

em_calculate_mng_checksum(char *buffer, uint32_t length)

sys/dev/pci/if_em_hw.c

9394

uint32_t i;

sys/dev/pci/if_em_hw.c

9540

uint32_t ctrl;

sys/dev/pci/if_em_hw.c

9669

uint32_t cfg_mask = E1000_NVM_CFG_DONE_PORT_0;

sys/dev/pci/if_em_hw.c

9727

uint32_t swsm;

sys/dev/pci/if_em_hw.c

9774

uint32_t swsm;

sys/dev/pci/if_em_hw.c

98

static int32_t em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *);

sys/dev/pci/if_em_hw.c

9803

uint32_t swsm;

sys/dev/pci/if_em_hw.c

9838

uint32_t swsm;

sys/dev/pci/if_em_hw.c

9864

uint32_t manc = 0;

sys/dev/pci/if_em_hw.c

9865

uint32_t fwsm = 0;

sys/dev/pci/if_em_hw.c

9898

em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop)

sys/dev/pci/if_em_hw.c

99

static int32_t em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t);

sys/dev/pci/if_em_hw.c

9900

uint32_t gcr_reg = 0;

sys/dev/pci/if_em_hw.c

9916

uint32_t ctrl_ext;

sys/dev/pci/if_em_hw.c

9937

uint32_t extcnf_ctrl;

sys/dev/pci/if_em_hw.c

9994

uint32_t extcnf_ctrl;

sys/dev/pci/if_em_hw.h

1000

volatile uint32_t value; /* Flexible Filter Value (RW) */

sys/dev/pci/if_em_hw.h

1001

volatile uint32_t reserved;

sys/dev/pci/if_em_hw.h

1406

uint32_t phy_init_script;

sys/dev/pci/if_em_hw.h

1410

uint32_t flash_bank_size;

sys/dev/pci/if_em_hw.h

1411

uint32_t flash_base_addr;

sys/dev/pci/if_em_hw.h

1412

uint32_t fc;

sys/dev/pci/if_em_hw.h

1420

uint32_t asf_firmware_present;

sys/dev/pci/if_em_hw.h

1421

uint32_t eeprom_semaphore_present;

sys/dev/pci/if_em_hw.h

1422

uint32_t swfw_sync_present;

sys/dev/pci/if_em_hw.h

1423

uint32_t swfwhw_semaphore_present;

sys/dev/pci/if_em_hw.h

1425

uint32_t phy_id;

sys/dev/pci/if_em_hw.h

1426

uint32_t phy_revision;

sys/dev/pci/if_em_hw.h

1427

uint32_t phy_addr;

sys/dev/pci/if_em_hw.h

1428

uint32_t original_fc;

sys/dev/pci/if_em_hw.h

1429

uint32_t txcw;

sys/dev/pci/if_em_hw.h

1430

uint32_t autoneg_failed;

sys/dev/pci/if_em_hw.h

1431

uint32_t max_frame_size;

sys/dev/pci/if_em_hw.h

1432

uint32_t min_frame_size;

sys/dev/pci/if_em_hw.h

1433

uint32_t mc_filter_type;

sys/dev/pci/if_em_hw.h

1434

uint32_t num_mc_addrs;

sys/dev/pci/if_em_hw.h

1435

uint32_t collision_delta;

sys/dev/pci/if_em_hw.h

1436

uint32_t tx_packet_delta;

sys/dev/pci/if_em_hw.h

1437

uint32_t ledctl_default;

sys/dev/pci/if_em_hw.h

1438

uint32_t ledctl_mode1;

sys/dev/pci/if_em_hw.h

1439

uint32_t ledctl_mode2;

sys/dev/pci/if_em_hw.h

1486

uint32_t icp_xxxx_port_num;

sys/dev/pci/if_em_hw.h

2117

uint32_t vlan_macip_lens;

sys/dev/pci/if_em_hw.h

2119

uint32_t launch_time;

sys/dev/pci/if_em_hw.h

2120

uint32_t seqnum_seed;

sys/dev/pci/if_em_hw.h

2122

uint32_t type_tucmd_mlhl;

sys/dev/pci/if_em_hw.h

2123

uint32_t mss_l4len_idx;

sys/dev/pci/if_em_hw.h

2705

#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)

sys/dev/pci/if_em_hw.h

297

uint32_t idle_errors;

sys/dev/pci/if_em_hw.h

298

uint32_t receive_errors;

sys/dev/pci/if_em_hw.h

359

int32_t em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data);

sys/dev/pci/if_em_hw.h

360

int32_t em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data);

sys/dev/pci/if_em_hw.h

3609

uint32_t grra :8; /* 0:7 GbE region Read Access */

sys/dev/pci/if_em_hw.h

3610

uint32_t grwa :8; /* 8:15 GbE region Write Access */

sys/dev/pci/if_em_hw.h

3611

uint32_t gmrag :8; /* 23:16 GbE Master Read Access Grant */

sys/dev/pci/if_em_hw.h

3612

uint32_t gmwag :8; /* 31:24 GbE Master Write Access Grant */

sys/dev/pci/if_em_hw.h

364

int32_t em_read_phy_reg_i2c(struct em_hw *, uint32_t, uint16_t *);

sys/dev/pci/if_em_hw.h

365

int32_t em_write_phy_reg_i2c(struct em_hw *, uint32_t, uint16_t);

sys/dev/pci/if_em_hw.h

400

uint32_t signature;

sys/dev/pci/if_em_hw.h

404

uint32_t reserved1;

sys/dev/pci/if_em_hw.h

410

int32_t em_read_part_num(struct em_hw *hw, uint32_t *part_num);

sys/dev/pci/if_em_hw.h

421

void em_mc_addr_list_update(struct em_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count,

sys/dev/pci/if_em_hw.h

422

uint32_t pad);

sys/dev/pci/if_em_hw.h

423

uint32_t em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr);

sys/dev/pci/if_em_hw.h

424

void em_mta_set(struct em_hw *hw, uint32_t hash_value);

sys/dev/pci/if_em_hw.h

425

void em_rar_set(struct em_hw *hw, uint8_t *mc_addr, uint32_t rar_index);

sys/dev/pci/if_em_hw.h

434

void em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value);

sys/dev/pci/if_em_hw.h

435

void em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value);

sys/dev/pci/if_em_hw.h

436

int32_t em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value);

sys/dev/pci/if_em_hw.h

440

uint32_t em_translate_82542_register(uint32_t);

sys/dev/pci/if_em_hw.h

757

uint32_t mrq; /* Multiple Rx Queues */

sys/dev/pci/if_em_hw.h

759

uint32_t rss; /* RSS Hash */

sys/dev/pci/if_em_hw.h

767

uint32_t status_error; /* ext status/error */

sys/dev/pci/if_em_hw.h

783

uint32_t mrq; /* Multiple Rx Queues */

sys/dev/pci/if_em_hw.h

785

uint32_t rss; /* RSS Hash */

sys/dev/pci/if_em_hw.h

793

uint32_t status_error; /* ext status/error */

sys/dev/pci/if_em_hw.h

862

uint32_t data;

sys/dev/pci/if_em_hw.h

870

uint32_t data;

sys/dev/pci/if_em_hw.h

904

uint32_t ip_config;

sys/dev/pci/if_em_hw.h

912

uint32_t tcp_config;

sys/dev/pci/if_em_hw.h

919

uint32_t cmd_and_length; /* */

sys/dev/pci/if_em_hw.h

921

uint32_t data;

sys/dev/pci/if_em_hw.h

934

uint32_t data;

sys/dev/pci/if_em_hw.h

942

uint32_t data;

sys/dev/pci/if_em_hw.h

961

volatile uint32_t low; /* receive address low */

sys/dev/pci/if_em_hw.h

962

volatile uint32_t high; /* receive address high */

sys/dev/pci/if_em_hw.h

971

volatile uint32_t ipv4_addr; /* IP Address (RW) */

sys/dev/pci/if_em_hw.h

972

volatile uint32_t reserved;

sys/dev/pci/if_em_hw.h

988

volatile uint32_t length; /* Flexible Filter Length (RW) */

sys/dev/pci/if_em_hw.h

989

volatile uint32_t reserved;

sys/dev/pci/if_em_hw.h

994

volatile uint32_t mask; /* Flexible Filter Mask (RW) */

sys/dev/pci/if_em_hw.h

995

volatile uint32_t reserved;

sys/dev/pci/if_em_soc.c

102

uint32_t data, done = 0;

sys/dev/pci/if_em_soc.c

54

uint32_t data = 0;

sys/dev/pci/if_em_soc.c

55

uint32_t done = 0;

sys/dev/pci/if_et.c

1183

uint32_t hash[4] = { 0, 0, 0, 0 };

sys/dev/pci/if_et.c

1184

uint32_t rxmac_ctrl, pktfilt;

sys/dev/pci/if_et.c

1201

uint32_t *hp, h;

sys/dev/pci/if_et.c

1238

uint32_t rxq_end;

sys/dev/pci/if_et.c

1304

bzero(txsd->txsd_status, sizeof(uint32_t));

sys/dev/pci/if_et.c

140

static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */

sys/dev/pci/if_et.c

1452

uint32_t val;

sys/dev/pci/if_et.c

1504

uint32_t val;

sys/dev/pci/if_et.c

1597

uint32_t val = 0;

sys/dev/pci/if_et.c

1628

uint32_t val;

sys/dev/pci/if_et.c

1665

uint32_t rxs_stat_ring;

sys/dev/pci/if_et.c

1685

uint32_t rxstat_pos, rxring_pos;

sys/dev/pci/if_et.c

1767

uint32_t tx_ready_pos, last_td_ctrl2;

sys/dev/pci/if_et.c

1877

uint32_t tx_done;

sys/dev/pci/if_et.c

309

uint32_t val;

sys/dev/pci/if_et.c

352

uint32_t val;

sys/dev/pci/if_et.c

390

uint32_t cfg2, ctrl;

sys/dev/pci/if_et.c

474

uint32_t val; //, max_plsz;

sys/dev/pci/if_et.c

550

uint32_t r;

sys/dev/pci/if_et.c

588

et_enable_intrs(struct et_softc *sc, uint32_t intrs)

sys/dev/pci/if_et.c

617

error = et_dma_mem_create(sc, sizeof(uint32_t),

sys/dev/pci/if_et.c

630

static const uint32_t rx_ring_posreg[ET_RX_NRING] =

sys/dev/pci/if_et.c

875

uint32_t val;

sys/dev/pci/if_et.c

917

uint32_t intrs;

sys/dev/pci/if_et.c

95

void et_enable_intrs(struct et_softc *, uint32_t);

sys/dev/pci/if_etreg.h

361

uint32_t td_addr_hi;

sys/dev/pci/if_etreg.h

362

uint32_t td_addr_lo;

sys/dev/pci/if_etreg.h

363

uint32_t td_ctrl1; /* ET_TDCTRL1_ */

sys/dev/pci/if_etreg.h

364

uint32_t td_ctrl2; /* ET_TDCTRL2_ */

sys/dev/pci/if_etreg.h

374

uint32_t rd_addr_lo;

sys/dev/pci/if_etreg.h

375

uint32_t rd_addr_hi;

sys/dev/pci/if_etreg.h

376

uint32_t rd_ctrl; /* ET_RDCTRL_ */

sys/dev/pci/if_etreg.h

382

uint32_t rxst_info1;

sys/dev/pci/if_etreg.h

383

uint32_t rxst_info2; /* ET_RXST_INFO2_ */

sys/dev/pci/if_etreg.h

391

uint32_t rxs_ring;

sys/dev/pci/if_etreg.h

392

uint32_t rxs_stat_ring; /* ET_RXS_STATRING_ */

sys/dev/pci/if_etreg.h

412

uint32_t *txsd_status;

sys/dev/pci/if_etreg.h

456

uint32_t rr_posreg;

sys/dev/pci/if_etreg.h

512

uint32_t sc_tx;

sys/dev/pci/if_etreg.h

513

uint32_t sc_tx_intr;

sys/dev/pci/if_etreg.h

521

uint32_t sc_timer;

sys/dev/pci/if_iavf.c

132

uint32_t iaq_vc_opcode;

sys/dev/pci/if_iavf.c

133

uint32_t iaq_vc_retval;

sys/dev/pci/if_iavf.c

1335

uint32_t key_len = sc->sc_rss_key_size;

sys/dev/pci/if_iavf.c

135

uint32_t iaq_param[4];

sys/dev/pci/if_iavf.c

1366

uint32_t lut_size = sc->sc_rss_lut_size;

sys/dev/pci/if_iavf.c

1638

uint32_t reg;

sys/dev/pci/if_iavf.c

1735

uint32_t reg;

sys/dev/pci/if_iavf.c

221

uint32_t major;

sys/dev/pci/if_iavf.c

222

uint32_t minor;

sys/dev/pci/if_iavf.c

237

uint32_t ring_len;

sys/dev/pci/if_iavf.c

240

uint32_t databuf_size;

sys/dev/pci/if_iavf.c

241

uint32_t max_pkt_size;

sys/dev/pci/if_iavf.c

242

uint32_t pad1;

sys/dev/pci/if_iavf.c

244

uint32_t rx_split_pos;

sys/dev/pci/if_iavf.c

245

uint32_t pad2;

sys/dev/pci/if_iavf.c

2536

uint32_t icr, ena;

sys/dev/pci/if_iavf.c

256

uint32_t pad;

sys/dev/pci/if_iavf.c

2607

iavf_find_link_speed(struct iavf_softc *sc, uint32_t link_speed)

sys/dev/pci/if_iavf.c

277

uint32_t rx_queues;

sys/dev/pci/if_iavf.c

278

uint32_t tx_queues;

sys/dev/pci/if_iavf.c

284

uint32_t vsi_type;

sys/dev/pci/if_iavf.c

2910

uint32_t *cap;

sys/dev/pci/if_iavf.c

2920

iaq.iaq_datalen = htole16(sizeof(uint32_t));

sys/dev/pci/if_iavf.c

294

uint32_t offload_flags;

sys/dev/pci/if_iavf.c

295

uint32_t rss_key_size;

sys/dev/pci/if_iavf.c

296

uint32_t rss_lut_size;

sys/dev/pci/if_iavf.c

325

uint32_t event;

sys/dev/pci/if_iavf.c

326

uint32_t link_speed;

sys/dev/pci/if_iavf.c

329

uint32_t severity;

sys/dev/pci/if_iavf.c

487

uint32_t filter_status;

sys/dev/pci/if_iavf.c

528

uint32_t atq_len_enable;

sys/dev/pci/if_iavf.c

529

uint32_t atq_tail_mask;

sys/dev/pci/if_iavf.c

530

uint32_t atq_head_mask;

sys/dev/pci/if_iavf.c

532

uint32_t arq_len_enable;

sys/dev/pci/if_iavf.c

533

uint32_t arq_tail_mask;

sys/dev/pci/if_iavf.c

534

uint32_t arq_head_mask;

sys/dev/pci/if_iavf.c

636

uint32_t sc_major_ver;

sys/dev/pci/if_iavf.c

637

uint32_t sc_minor_ver;

sys/dev/pci/if_iavf.c

642

uint32_t sc_vf_id;

sys/dev/pci/if_iavf.c

647

uint32_t sc_rss_key_size;

sys/dev/pci/if_iavf.c

648

uint32_t sc_rss_lut_size;

sys/dev/pci/if_iavf.c

801

#define iavf_dmamem_hi(_ixm) (uint32_t)(IAVF_DMA_DVA(_ixm) >> 32)

sys/dev/pci/if_iavf.c

806

#define iavf_dmamem_lo(_ixm) (uint32_t)IAVF_DMA_DVA(_ixm)

sys/dev/pci/if_iavf.c

964

uint32_t reg;

sys/dev/pci/if_ice.c

10063

uint32_t bw, uint8_t layer_num)

sys/dev/pci/if_ice.c

10142

enum ice_rl_type rl_type, uint32_t bw, uint8_t layer_num)

sys/dev/pci/if_ice.c

10191

enum ice_rl_type rl_type, uint32_t bw)

sys/dev/pci/if_ice.c

1035

uint32_t cnt, reg = 0, grst_timeout, uld_mask, reset_wait_cnt;

sys/dev/pci/if_ice.c

10658

uint32_t *q_teids, enum ice_disq_rst_src rst_src, uint16_t vmvf_num,

sys/dev/pci/if_ice.c

10738

uint32_t *q_teids;

sys/dev/pci/if_ice.c

10747

q_teids = (uint32_t *)malloc(q_teids_size, M_DEVBUF, M_NOWAIT|M_ZERO);

sys/dev/pci/if_ice.c

10832

uint32_t rxq_index)

sys/dev/pci/if_ice.c

10845

*((uint32_t *)(ice_rxq_ctx + (i * sizeof(uint32_t)))));

sys/dev/pci/if_ice.c

10848

i, le32toh(*((uint32_t *)(ice_rxq_ctx +

sys/dev/pci/if_ice.c

10849

(i * sizeof(uint32_t))))));

sys/dev/pci/if_ice.c

10893

uint32_t rxq_index)

sys/dev/pci/if_ice.c

10921

uint32_t rxdid = ICE_RXDID_FLEX_NIC;

sys/dev/pci/if_ice.c

10922

uint32_t regval;

sys/dev/pci/if_ice.c

1097

uint32_t cnt, reg, reset_wait_cnt, cfg_lock_timeout;

sys/dev/pci/if_ice.c

11018

ice_is_rxq_ready(struct ice_hw *hw, int pf_q, uint32_t *reg)

sys/dev/pci/if_ice.c

11020

uint32_t qrx_ctrl, qena_req, qena_stat;

sys/dev/pci/if_ice.c

11058

uint32_t qrx_ctrl = 0;

sys/dev/pci/if_ice.c

11138

uint32_t val;

sys/dev/pci/if_ice.c

11182

uint32_t val;

sys/dev/pci/if_ice.c

1151

uint32_t val = 0;

sys/dev/pci/if_ice.c

11886

uint32_t dyn_ctl;

sys/dev/pci/if_ice.c

11904

uint32_t dyn_ctl;

sys/dev/pci/if_ice.c

13345

uint32_t reg, val;

sys/dev/pci/if_ice.c

13400

uint32_t reg, val;

sys/dev/pci/if_ice.c

14815

ice_verify_pkg(struct ice_pkg_hdr *pkg, uint32_t len)

sys/dev/pci/if_ice.c

14817

uint32_t seg_count;

sys/dev/pci/if_ice.c

14818

uint32_t i;

sys/dev/pci/if_ice.c

14840

uint32_t off = le32toh(pkg->seg_offset[i]);

sys/dev/pci/if_ice.c

14868

ice_find_seg_in_pkg(struct ice_hw *hw, uint32_t seg_type,

sys/dev/pci/if_ice.c

14871

uint32_t i;

sys/dev/pci/if_ice.c

14928

ice_cfg_tx_topo(struct ice_softc *sc, uint8_t *buf, uint32_t len)

sys/dev/pci/if_ice.c

14938

uint32_t reg = 0;

sys/dev/pci/if_ice.c

15393

uint32_t

sys/dev/pci/if_ice.c

15396

uint32_t seg_id;

sys/dev/pci/if_ice.c

15414

uint32_t

sys/dev/pci/if_ice.c

15417

uint32_t sign_type;

sys/dev/pci/if_ice.c

1542

ICE_WRITE(hw, cq->rq.tail, (uint32_t)(cq->num_rq_entries - 1));

sys/dev/pci/if_ice.c

15452

ice_get_pkg_seg_by_idx(struct ice_pkg_hdr *pkg_hdr, uint32_t idx)

sys/dev/pci/if_ice.c

15469

ice_is_signing_seg_at_idx(struct ice_pkg_hdr *pkg_hdr, uint32_t idx)

sys/dev/pci/if_ice.c

15491

ice_is_signing_seg_type_at_idx(struct ice_pkg_hdr *pkg_hdr, uint32_t idx,

sys/dev/pci/if_ice.c

15492

uint32_t seg_id, uint32_t sign_type)

sys/dev/pci/if_ice.c

15516

ice_match_signing_seg(struct ice_pkg_hdr *pkg_hdr, uint32_t seg_id,

sys/dev/pci/if_ice.c

15517

uint32_t sign_type)

sys/dev/pci/if_ice.c

15520

uint32_t i;

sys/dev/pci/if_ice.c

15624

uint32_t sect_type)

sys/dev/pci/if_ice.c

15787

uint32_t i;

sys/dev/pci/if_ice.c

15862

uint32_t sect_type, uint32_t *offset, void *(*handler)(uint32_t sect_type,

sys/dev/pci/if_ice.c

15863

void *section, uint32_t index, uint32_t *offset))

sys/dev/pci/if_ice.c

15910

ice_label_enum_handler(uint32_t sect_type, void *section, uint32_t index,

sys/dev/pci/if_ice.c

15911

uint32_t *offset)

sys/dev/pci/if_ice.c

15944

ice_enum_labels(struct ice_seg *ice_seg, uint32_t type,

sys/dev/pci/if_ice.c

15973

ice_boost_tcam_handler(uint32_t sect_type, void *section, uint32_t index,

sys/dev/pci/if_ice.c

15974

uint32_t *offset)

sys/dev/pci/if_ice.c

16204

ice_is_last_download_buffer(struct ice_buf_hdr *buf, uint32_t idx,

sys/dev/pci/if_ice.c

16205

uint32_t count)

sys/dev/pci/if_ice.c

16235

uint16_t buf_size, bool last_buf, uint32_t *error_offset,

sys/dev/pci/if_ice.c

16236

uint32_t *error_info, struct ice_sq_cd *cd)

sys/dev/pci/if_ice.c

16283

uint32_t start, uint32_t count, bool indicate_last)

sys/dev/pci/if_ice.c

16288

uint32_t offset, info, i;

sys/dev/pci/if_ice.c

16358

uint32_t idx, uint32_t start, uint32_t count)

sys/dev/pci/if_ice.c

16362

uint32_t buf_count;

sys/dev/pci/if_ice.c

16388

uint32_t idx)

sys/dev/pci/if_ice.c

16392

uint32_t conf_idx;

sys/dev/pci/if_ice.c

16393

uint32_t start;

sys/dev/pci/if_ice.c

16394

uint32_t count;

sys/dev/pci/if_ice.c

16713

uint32_t i;

sys/dev/pci/if_ice.c

16755

ice_dwnld_cfg_bufs(struct ice_hw *hw, struct ice_buf *bufs, uint32_t count)

sys/dev/pci/if_ice.c

16914

uint32_t i;

sys/dev/pci/if_ice.c

17386

ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, uint32_t sid)

sys/dev/pci/if_ice.c

17388

uint32_t dst_len, sect_len, offset = 0;

sys/dev/pci/if_ice.c

17472

sect_len = (uint32_t)(le16toh(es->count) *

sys/dev/pci/if_ice.c

17476

dst_len = (uint32_t)(hw->blk[block_id].es.count *

sys/dev/pci/if_ice.c

17542

ice_sw_fv_handler(uint32_t sect_type, void *section, uint32_t index,

sys/dev/pci/if_ice.c

17543

uint32_t *offset)

sys/dev/pci/if_ice.c

17578

uint32_t offset;

sys/dev/pci/if_ice.c

1760

ice_debug_array(struct ice_hw *hw, uint64_t mask, uint32_t rowsize,

sys/dev/pci/if_ice.c

1761

uint32_t __unused groupsize, uint8_t *buf, size_t len)

sys/dev/pci/if_ice.c

17640

ice_init_pkg(struct ice_hw *hw, uint8_t *buf, uint32_t len)

sys/dev/pci/if_ice.c

17735

ice_copy_and_init_pkg(struct ice_hw *hw, const uint8_t *buf, uint32_t len)

sys/dev/pci/if_ice.c

190

uint32_t ice_debug = 0xffffffff & ~(ICE_DBG_AQ | ICE_DBG_TRACE);

sys/dev/pci/if_ice.c

1918

uint32_t total_delay = 0;

sys/dev/pci/if_ice.c

1920

uint32_t val = 0;

sys/dev/pci/if_ice.c

19461

ice_pkg_buf_alloc_section(struct ice_buf_build *bld, uint32_t type,

sys/dev/pci/if_ice.c

19580

static const uint32_t ice_sect_lkup[ICE_BLK_COUNT][ICE_SECT_COUNT] = {

sys/dev/pci/if_ice.c

19655

uint32_t

sys/dev/pci/if_ice.c

19676

uint32_t id;

sys/dev/pci/if_ice.c

19710

uint32_t id;

sys/dev/pci/if_ice.c

19746

uint32_t id;

sys/dev/pci/if_ice.c

19778

uint32_t id;

sys/dev/pci/if_ice.c

19814

uint16_t buf_size, bool last_buf, uint32_t *error_offset,

sys/dev/pci/if_ice.c

19815

uint32_t *error_info, struct ice_sq_cd *cd)

sys/dev/pci/if_ice.c

19855

ice_update_pkg_no_lock(struct ice_hw *hw, struct ice_buf *bufs, uint32_t count)

sys/dev/pci/if_ice.c

19858

uint32_t i;

sys/dev/pci/if_ice.c

19863

uint32_t offset, info;

sys/dev/pci/if_ice.c

19913

ice_update_pkg(struct ice_hw *hw, struct ice_buf *bufs, uint32_t count)

sys/dev/pci/if_ice.c

212

#define ICE_HI_DWORD(x) ((uint32_t)((((x) >> 16) >> 16) & 0xFFFFFFFF))

sys/dev/pci/if_ice.c

21235

uint32_t val;

sys/dev/pci/if_ice.c

213

#define ICE_LO_DWORD(x) ((uint32_t)((x) & 0xFFFFFFFF))

sys/dev/pci/if_ice.c

21416

uint32_t table = 0;

sys/dev/pci/if_ice.c

21671

ice_aq_suspend_sched_elems(struct ice_hw *hw, uint16_t elems_req, uint32_t *buf,

sys/dev/pci/if_ice.c

21691

ice_aq_resume_sched_elems(struct ice_hw *hw, uint16_t elems_req, uint32_t *buf,

sys/dev/pci/if_ice.c

21710

uint32_t *node_teids, bool suspend)

sys/dev/pci/if_ice.c

21714

uint32_t *buf;

sys/dev/pci/if_ice.c

21717

buf = (uint32_t *)ice_malloc(hw, buf_size);

sys/dev/pci/if_ice.c

21806

uint16_t *num_nodes_added, uint32_t *first_node_teid,

sys/dev/pci/if_ice.c

21815

uint32_t teid;

sys/dev/pci/if_ice.c

21917

uint16_t num_nodes, uint32_t *first_node_teid,

sys/dev/pci/if_ice.c

21961

uint16_t num_nodes, uint32_t *first_node_teid,

sys/dev/pci/if_ice.c

21964

uint32_t *first_teid_ptr = first_node_teid;

sys/dev/pci/if_ice.c

21967

uint32_t temp;

sys/dev/pci/if_ice.c

22030

uint32_t first_node_teid;

sys/dev/pci/if_ice.c

22185

uint32_t first_node_teid;

sys/dev/pci/if_ice.c

22335

uint32_t teid = le32toh(vsi_node->info.node_teid);

sys/dev/pci/if_ice.c

22373

uint32_t teid = le32toh(vsi_node->info.node_teid);

sys/dev/pci/if_ice.c

2279

uint32_t src_dword, mask;

sys/dev/pci/if_ice.c

2280

uint32_t dest_dword;

sys/dev/pci/if_ice.c

2297

mask = (uint32_t)~0;

sys/dev/pci/if_ice.c

2302

src_dword = *(uint32_t *)from;

sys/dev/pci/if_ice.c

23581

uint32_t ouisubtype;

sys/dev/pci/if_ice.c

23622

uint32_t ouisubtype;

sys/dev/pci/if_ice.c

23651

uint32_t ouisubtype;

sys/dev/pci/if_ice.c

23692

uint32_t ouisubtype;

sys/dev/pci/if_ice.c

23738

uint32_t ouisubtype;

sys/dev/pci/if_ice.c

23746

ouisubtype = (uint32_t)((ICE_DSCP_OUI << ICE_LLDP_TLV_OUI_S) |

sys/dev/pci/if_ice.c

23775

uint32_t ouisubtype;

sys/dev/pci/if_ice.c

23782

ouisubtype = (uint32_t)((ICE_DSCP_OUI << ICE_LLDP_TLV_OUI_S) |

sys/dev/pci/if_ice.c

23801

uint32_t ouisubtype;

sys/dev/pci/if_ice.c

23810

ouisubtype = (uint32_t)((ICE_DSCP_OUI << ICE_LLDP_TLV_OUI_S) |

sys/dev/pci/if_ice.c

23848

uint32_t ouisubtype;

sys/dev/pci/if_ice.c

23855

ouisubtype = (uint32_t)((ICE_DSCP_OUI << ICE_LLDP_TLV_OUI_S) |

sys/dev/pci/if_ice.c

2404

case sizeof(uint32_t):

sys/dev/pci/if_ice.c

24489

static const uint32_t ice_ptypes_mac_ofos[] = {

sys/dev/pci/if_ice.c

24501

static const uint32_t ice_ptypes_macvlan_il[] = {

sys/dev/pci/if_ice.c

24515

static const uint32_t ice_ptypes_ipv4_ofos[] = {

sys/dev/pci/if_ice.c

24529

static const uint32_t ice_ptypes_ipv4_ofos_all[] = {

sys/dev/pci/if_ice.c

24541

static const uint32_t ice_ptypes_ipv4_il[] = {

sys/dev/pci/if_ice.c

24555

static const uint32_t ice_ptypes_ipv6_ofos[] = {

sys/dev/pci/if_ice.c

24569

static const uint32_t ice_ptypes_ipv6_ofos_all[] = {

sys/dev/pci/if_ice.c

24581

static const uint32_t ice_ptypes_ipv6_il[] = {

sys/dev/pci/if_ice.c

24595

static const uint32_t ice_ptypes_ipv4_ofos_no_l4[] = {

sys/dev/pci/if_ice.c

24607

static const uint32_t ice_ptypes_ipv4_il_no_l4[] = {

sys/dev/pci/if_ice.c

24621

static const uint32_t ice_ptypes_ipv6_ofos_no_l4[] = {

sys/dev/pci/if_ice.c

24633

static const uint32_t ice_ptypes_ipv6_il_no_l4[] = {

sys/dev/pci/if_ice.c

24645

static const uint32_t ice_ptypes_arp_of[] = {

sys/dev/pci/if_ice.c

24659

static const uint32_t ice_ptypes_udp_il[] = {

sys/dev/pci/if_ice.c

24671

static const uint32_t ice_ptypes_tcp_il[] = {

sys/dev/pci/if_ice.c

24683

static const uint32_t ice_ptypes_sctp_il[] = {

sys/dev/pci/if_ice.c

24695

static const uint32_t ice_ptypes_icmp_of[] = {

sys/dev/pci/if_ice.c

24707

static const uint32_t ice_ptypes_icmp_il[] = {

sys/dev/pci/if_ice.c

24719

static const uint32_t ice_ptypes_gre_of[] = {

sys/dev/pci/if_ice.c

24731

static const uint32_t ice_ptypes_mac_il[] = {

sys/dev/pci/if_ice.c

24776

uint32_t hdrs;

sys/dev/pci/if_ice.c

2522

uint32_t *timeout, struct ice_sq_cd *cd)

sys/dev/pci/if_ice.c

25727

#define ICE_FLOW_SET_HDRS(seg, val) ((seg)->hdrs |= (uint32_t)(val))

sys/dev/pci/if_ice.c

25878

uint8_t segs_cnt, uint16_t vsi_handle, uint32_t conds)

sys/dev/pci/if_ice.c

2620

enum ice_aq_res_access_type access, uint32_t timeout)

sys/dev/pci/if_ice.c

2623

uint32_t delay = ICE_RES_POLLING_DELAY_MS;

sys/dev/pci/if_ice.c

2624

uint32_t time_left = timeout;

sys/dev/pci/if_ice.c

26736

uint32_t reg;

sys/dev/pci/if_ice.c

2683

uint32_t total_delay = 0;

sys/dev/pci/if_ice.c

26870

uint32_t val;

sys/dev/pci/if_ice.c

26997

ice_info_fwlog(struct ice_hw *hw, uint32_t rowsize, uint32_t __unused groupsize,

sys/dev/pci/if_ice.c

27342

uint32_t ouisubtype;

sys/dev/pci/if_ice.c

27517

uint32_t ouisubtype;

sys/dev/pci/if_ice.c

27573

uint32_t ouisubtype;

sys/dev/pci/if_ice.c

27574

uint32_t oui;

sys/dev/pci/if_ice.c

27681

uint32_t status, tlv_status = le32toh(cee_cfg->tlv_status);

sys/dev/pci/if_ice.c

27682

uint32_t ice_aqc_cee_status_mask, ice_aqc_cee_status_shift;

sys/dev/pci/if_ice.c

28616

ice_stat_update40(struct ice_hw *hw, uint32_t reg, bool prev_stat_loaded,

sys/dev/pci/if_ice.c

28655

ice_stat_update32(struct ice_hw *hw, uint32_t reg, bool prev_stat_loaded,

sys/dev/pci/if_ice.c

28658

uint32_t new_data;

sys/dev/pci/if_ice.c

28714

uint32_t repc;

sys/dev/pci/if_ice.c

29072

uint32_t info, data;

sys/dev/pci/if_ice.c

29140

uint32_t oicr;

sys/dev/pci/if_ice.c

29176

uint32_t reset;

sys/dev/pci/if_ice.c

2964

uint32_t retry = 0;

sys/dev/pci/if_ice.c

29779

uint32_t

sys/dev/pci/if_ice.c

30011

uint32_t reg;

sys/dev/pci/if_ice.c

30360

ice_read_pba_string(struct ice_hw *hw, uint8_t *pba_num, uint32_t pba_num_size)

sys/dev/pci/if_ice.c

30393

if (pba_num_size < (((uint32_t)pba_size * 2) + 1)) {

sys/dev/pci/if_ice.c

3431

uint32_t ice_get_flash_bank_offset(struct ice_hw *hw,

sys/dev/pci/if_ice.c

3437

uint32_t offset, size;

sys/dev/pci/if_ice.c

3506

ice_aq_read_nvm(struct ice_hw *hw, uint16_t module_typeid, uint32_t offset,

sys/dev/pci/if_ice.c

3552

ice_read_flat_nvm(struct ice_hw *hw, uint32_t offset, uint32_t *length,

sys/dev/pci/if_ice.c

3556

uint32_t inlen = *length;

sys/dev/pci/if_ice.c

3557

uint32_t bytes_read = 0;

sys/dev/pci/if_ice.c

3572

uint32_t read_size, sector_offset;

sys/dev/pci/if_ice.c

3614

uint32_t min_size = 0, max_size = ICE_AQC_NVM_MAX_OFFSET + 1;

sys/dev/pci/if_ice.c

3624

uint32_t offset = (max_size + min_size) / 2;

sys/dev/pci/if_ice.c

3625

uint32_t len = 1;

sys/dev/pci/if_ice.c

3668

uint32_t bytes = sizeof(uint16_t);

sys/dev/pci/if_ice.c

3724

ice_read_sr_pointer(struct ice_hw *hw, uint16_t offset, uint32_t *pointer)

sys/dev/pci/if_ice.c

3756

ice_read_sr_area_size(struct ice_hw *hw, uint16_t offset, uint32_t *size)

sys/dev/pci/if_ice.c

377

ice_usec_delay(uint32_t time, bool sleep)

sys/dev/pci/if_ice.c

3877

uint16_t module, uint32_t offset, uint8_t *data, uint32_t length)

sys/dev/pci/if_ice.c

3880

uint32_t start;

sys/dev/pci/if_ice.c

3915

uint32_t offset, uint16_t *data)

sys/dev/pci/if_ice.c

394

ice_msec_delay(uint32_t time, bool sleep)

sys/dev/pci/if_ice.c

3940

uint32_t *hdr_len)

sys/dev/pci/if_ice.c

3944

uint32_t hdr_len_dword;

sys/dev/pci/if_ice.c

3975

uint32_t *srev)

sys/dev/pci/if_ice.c

4005

uint32_t offset, uint16_t *data)

sys/dev/pci/if_ice.c

4008

uint32_t hdr_len;

sys/dev/pci/if_ice.c

4081

uint32_t offset, uint16_t *data)

sys/dev/pci/if_ice.c

4105

ice_get_orom_srev(struct ice_hw *hw, enum ice_bank_select bank, uint32_t *srev)

sys/dev/pci/if_ice.c

4107

uint32_t orom_size_word = hw->flash.banks.orom_size / 2;

sys/dev/pci/if_ice.c

4110

uint32_t css_start;

sys/dev/pci/if_ice.c

4111

uint32_t hdr_len;

sys/dev/pci/if_ice.c

4157

uint32_t offset;

sys/dev/pci/if_ice.c

4240

uint32_t combo_ver;

sys/dev/pci/if_ice.c

4278

uint32_t offset, uint16_t *data)

sys/dev/pci/if_ice.c

4386

uint32_t fla, gens_stat;

sys/dev/pci/if_ice.c

4522

uint32_t

sys/dev/pci/if_ice.c

4523

ice_get_num_per_func(struct ice_hw *hw, uint32_t max)

sys/dev/pci/if_ice.c

4622

uint32_t logical_id = le32toh(elem->logical_id);

sys/dev/pci/if_ice.c

4623

uint32_t phys_id = le32toh(elem->phys_id);

sys/dev/pci/if_ice.c

4624

uint32_t number = le32toh(elem->number);

sys/dev/pci/if_ice.c

4916

uint32_t number = le32toh(cap->number);

sys/dev/pci/if_ice.c

4917

uint32_t logical_id = le32toh(cap->logical_id);

sys/dev/pci/if_ice.c

4962

void *buf, uint32_t cap_count)

sys/dev/pci/if_ice.c

4965

uint32_t i;

sys/dev/pci/if_ice.c

5012

uint32_t number = le32toh(cap->number);

sys/dev/pci/if_ice.c

5032

uint32_t number = le32toh(cap->number);

sys/dev/pci/if_ice.c

5051

uint32_t number = le32toh(cap->number);

sys/dev/pci/if_ice.c

5134

void *buf, uint32_t cap_count)

sys/dev/pci/if_ice.c

5137

uint32_t i;

sys/dev/pci/if_ice.c

5203

uint32_t *cap_count, enum ice_adminq_opc opc, struct ice_sq_cd *cd)

sys/dev/pci/if_ice.c

5236

uint32_t cap_count = 0;

sys/dev/pci/if_ice.c

5270

uint32_t cap_count = 0;

sys/dev/pci/if_ice.c

5302

uint32_t num_funcs;

sys/dev/pci/if_ice.c

5608

uint32_t val, clk_src;

sys/dev/pci/if_ice.c

5714

ice_sched_find_node_by_teid(struct ice_sched_node *start_node, uint32_t teid)

sys/dev/pci/if_ice.c

5828

ice_sched_query_elem(struct ice_hw *hw, uint32_t node_teid,

sys/dev/pci/if_ice.c

5942

uint16_t num_nodes, uint32_t *node_teids)

sys/dev/pci/if_ice.c

6012

uint32_t teid = le32toh(node->info.node_teid);

sys/dev/pci/if_ice.c

6071

uint32_t teid = le32toh(node->info.node_teid);

sys/dev/pci/if_ice.c

6582

uint32_t i;

sys/dev/pci/if_ice.c

6894

ice_cfg_rl_burst_size(struct ice_hw *hw, uint32_t bytes)

sys/dev/pci/if_ice.c

7194

uint32_t val;

sys/dev/pci/if_ice.c

7492

static const uint32_t ice_blk_sids[ICE_BLK_COUNT][ICE_SID_OFF_COUNT] = {

sys/dev/pci/if_ice.c

7629

ice_calloc(hw, (uint32_t)(es->count * es->fvw),

sys/dev/pci/if_ice.c

8177

uint32_t act = 0;

sys/dev/pci/if_ice.c

8679

uint32_t act;

sys/dev/pci/if_ice.c

967

uint32_t fw_mode;

sys/dev/pci/if_ice.c

9934

static inline uint64_t round_up_64bit(uint64_t a, uint32_t b)

sys/dev/pci/if_ice.c

9991

ice_sched_bw_to_rl_profile(struct ice_hw *hw, uint32_t bw,

sys/dev/pci/if_icereg.h

10045

uint32_t ingress_table; /* bitmap, 3 bits per up */

sys/dev/pci/if_icereg.h

10062

uint32_t egress_table; /* same defines as for ingress table */

sys/dev/pci/if_icereg.h

10121

uint32_t outer_up_table; /* same structure and defines as ingress tbl */

sys/dev/pci/if_icereg.h

10143

uint32_t pasid_id;

sys/dev/pci/if_icereg.h

10200

uint32_t addr_high;

sys/dev/pci/if_icereg.h

10201

uint32_t addr_low;

sys/dev/pci/if_icereg.h

10225

uint32_t bcast_thresh_size;

sys/dev/pci/if_icereg.h

10226

uint32_t mcast_thresh_size;

sys/dev/pci/if_icereg.h

10233

uint32_t storm_ctrl_ctrl;

sys/dev/pci/if_icereg.h

10251

uint32_t reserved;

sys/dev/pci/if_icereg.h

10266

uint32_t addr_high;

sys/dev/pci/if_icereg.h

10267

uint32_t addr_low;

sys/dev/pci/if_icereg.h

10298

uint32_t act;

sys/dev/pci/if_icereg.h

10434

uint32_t act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */

sys/dev/pci/if_icereg.h

10496

uint32_t reserved2;

sys/dev/pci/if_icereg.h

10497

uint32_t addr_high;

sys/dev/pci/if_icereg.h

10498

uint32_t addr_low;

sys/dev/pci/if_icereg.h

10514

uint32_t reserved2;

sys/dev/pci/if_icereg.h

10515

uint32_t addr_high;

sys/dev/pci/if_icereg.h

10516

uint32_t addr_low;

sys/dev/pci/if_icereg.h

10530

uint32_t reserved;

sys/dev/pci/if_icereg.h

10531

uint32_t addr_high;

sys/dev/pci/if_icereg.h

10532

uint32_t addr_low;

sys/dev/pci/if_icereg.h

10536

uint32_t src_parent_teid;

sys/dev/pci/if_icereg.h

10537

uint32_t dest_parent_teid;

sys/dev/pci/if_icereg.h

10545

uint32_t teid[STRUCT_HACK_VAR_LEN];

sys/dev/pci/if_icereg.h

10585

uint32_t parent_teid;

sys/dev/pci/if_icereg.h

10586

uint32_t node_teid;

sys/dev/pci/if_icereg.h

10591

uint32_t parent_teid;

sys/dev/pci/if_icereg.h

10609

uint32_t teid[STRUCT_HACK_VAR_LEN];

sys/dev/pci/if_icereg.h

10617

uint32_t port_teid;

sys/dev/pci/if_icereg.h

10618

uint32_t reserved;

sys/dev/pci/if_icereg.h

10619

uint32_t addr_high;

sys/dev/pci/if_icereg.h

10620

uint32_t addr_low;

sys/dev/pci/if_icereg.h

10627

uint32_t up2tc;

sys/dev/pci/if_icereg.h

10629

uint32_t port_eir_prof_id;

sys/dev/pci/if_icereg.h

10630

uint32_t port_cir_prof_id;

sys/dev/pci/if_icereg.h

10632

uint32_t tc_node_prio;

sys/dev/pci/if_icereg.h

10635

uint32_t tc_node_teid[8]; /* Used for response, reserved in command */

sys/dev/pci/if_icereg.h

10649

uint32_t addr_high;

sys/dev/pci/if_icereg.h

10650

uint32_t addr_low;

sys/dev/pci/if_icereg.h

10678

uint32_t addr_high;

sys/dev/pci/if_icereg.h

10679

uint32_t addr_low;

sys/dev/pci/if_icereg.h

10683

uint32_t node_teid;

sys/dev/pci/if_icereg.h

10695

uint32_t addr_high;

sys/dev/pci/if_icereg.h

10696

uint32_t addr_low;

sys/dev/pci/if_icereg.h

10700

uint32_t node_teid;

sys/dev/pci/if_icereg.h

10711

uint32_t addr_high;

sys/dev/pci/if_icereg.h

10712

uint32_t addr_low;

sys/dev/pci/if_icereg.h

10748

uint32_t teid;

sys/dev/pci/if_icereg.h

10749

uint32_t num_nodes; /* Response only */

sys/dev/pci/if_icereg.h

10750

uint32_t addr_high;

sys/dev/pci/if_icereg.h

10751

uint32_t addr_low;

sys/dev/pci/if_icereg.h

10774

uint32_t reserved1;

sys/dev/pci/if_icereg.h

10775

uint32_t addr_high;

sys/dev/pci/if_icereg.h

10776

uint32_t addr_low;

sys/dev/pci/if_icereg.h

10926

uint32_t v_rev;

sys/dev/pci/if_icereg.h

10937

uint32_t addr_high;

sys/dev/pci/if_icereg.h

10938

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11003

uint32_t reserved2;

sys/dev/pci/if_icereg.h

11004

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11005

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11100

uint32_t reserved3; /* Aligns next field to 8-byte boundary */

sys/dev/pci/if_icereg.h

11157

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11158

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11203

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11204

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11220

uint32_t execution_time; /* in nanoseconds */

sys/dev/pci/if_icereg.h

11231

uint32_t i2c_clk_cntr;

sys/dev/pci/if_icereg.h

11232

uint32_t mdio_clk_cntr;

sys/dev/pci/if_icereg.h

11233

uint32_t sb_iosf_clk_cntr;

sys/dev/pci/if_icereg.h

11262

uint32_t reserved1;

sys/dev/pci/if_icereg.h

11263

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11264

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11269

uint32_t stores[4];

sys/dev/pci/if_icereg.h

11283

uint32_t data; /* Used for write sto only */

sys/dev/pci/if_icereg.h

11284

uint32_t addr_high; /* Used for read sto only */

sys/dev/pci/if_icereg.h

11285

uint32_t addr_low; /* Used for read sto only */

sys/dev/pci/if_icereg.h

11296

uint32_t data; /* Reserved for write command */

sys/dev/pci/if_icereg.h

11297

uint32_t addr_high; /* Reserved for write command */

sys/dev/pci/if_icereg.h

11298

uint32_t addr_low; /* Reserved for write command */

sys/dev/pci/if_icereg.h

11303

uint32_t reserved[2];

sys/dev/pci/if_icereg.h

11304

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11305

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11320

uint32_t reserved1;

sys/dev/pci/if_icereg.h

11321

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11322

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11330

uint32_t data;

sys/dev/pci/if_icereg.h

11331

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11332

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11501

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11502

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11570

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11571

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11599

uint32_t start_address;

sys/dev/pci/if_icereg.h

11644

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11645

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11713

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11714

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11741

uint32_t id;

sys/dev/pci/if_icereg.h

11742

uint32_t reserved;

sys/dev/pci/if_icereg.h

11743

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11744

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11749

uint32_t dword0_addr;

sys/dev/pci/if_icereg.h

11750

uint32_t dword0_value;

sys/dev/pci/if_icereg.h

11751

uint32_t dword1_addr;

sys/dev/pci/if_icereg.h

11752

uint32_t dword1_value;

sys/dev/pci/if_icereg.h

11757

uint32_t base_dword_addr;

sys/dev/pci/if_icereg.h

11758

uint32_t num_dwords;

sys/dev/pci/if_icereg.h

11759

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11760

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11816

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11817

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11842

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11843

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11853

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11854

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11891

uint32_t tlv_status;

sys/dev/pci/if_icereg.h

11918

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11919

uint32_t addr_low;

sys/dev/pci/if_icereg.h

11962

uint32_t addr_high;

sys/dev/pci/if_icereg.h

11963

uint32_t addr_low;

sys/dev/pci/if_icereg.h

12024

uint32_t reserved;

sys/dev/pci/if_icereg.h

12025

uint32_t addr_high;

sys/dev/pci/if_icereg.h

12026

uint32_t addr_low;

sys/dev/pci/if_icereg.h

12033

uint32_t reserved1;

sys/dev/pci/if_icereg.h

12034

uint32_t addr_high;

sys/dev/pci/if_icereg.h

12035

uint32_t addr_low;

sys/dev/pci/if_icereg.h

12044

uint32_t q_teid;

sys/dev/pci/if_icereg.h

12056

uint32_t parent_teid;

sys/dev/pci/if_icereg.h

12079

uint32_t blocked_cgds;

sys/dev/pci/if_icereg.h

12080

uint32_t addr_high;

sys/dev/pci/if_icereg.h

12081

uint32_t addr_low;

sys/dev/pci/if_icereg.h

12093

uint32_t parent_teid;

sys/dev/pci/if_icereg.h

12127

uint32_t blocked_cgds;

sys/dev/pci/if_icereg.h

12128

uint32_t addr_high;

sys/dev/pci/if_icereg.h

12129

uint32_t addr_low;

sys/dev/pci/if_icereg.h

12137

uint32_t q_teid;

sys/dev/pci/if_icereg.h

12142

uint32_t src_teid;

sys/dev/pci/if_icereg.h

12143

uint32_t dest_teid;

sys/dev/pci/if_icereg.h

12151

uint32_t addr_high;

sys/dev/pci/if_icereg.h

12152

uint32_t addr_low;

sys/dev/pci/if_icereg.h

12161

uint32_t qset_teid;

sys/dev/pci/if_icereg.h

12171

uint32_t parent_teid;

sys/dev/pci/if_icereg.h

12185

uint32_t addr_high;

sys/dev/pci/if_icereg.h

12186

uint32_t addr_low;

sys/dev/pci/if_icereg.h

12196

uint32_t src_parent_teid;

sys/dev/pci/if_icereg.h

12197

uint32_t dest_parent_teid;

sys/dev/pci/if_icereg.h

12207

uint32_t reserved1;

sys/dev/pci/if_icereg.h

12208

uint32_t addr_high;

sys/dev/pci/if_icereg.h

12209

uint32_t addr_low;

sys/dev/pci/if_icereg.h

12213

uint32_t error_offset;

sys/dev/pci/if_icereg.h

12214

uint32_t error_info;

sys/dev/pci/if_icereg.h

12215

uint32_t addr_high;

sys/dev/pci/if_icereg.h

12216

uint32_t addr_low;

sys/dev/pci/if_icereg.h

12221

uint32_t reserved1;

sys/dev/pci/if_icereg.h

12222

uint32_t reserved2;

sys/dev/pci/if_icereg.h

12223

uint32_t addr_high;

sys/dev/pci/if_icereg.h

12224

uint32_t addr_low;

sys/dev/pci/if_icereg.h

12242

uint32_t track_id;

sys/dev/pci/if_icereg.h

12251

uint32_t count;

sys/dev/pci/if_icereg.h

12264

uint32_t param_val;

sys/dev/pci/if_icereg.h

12265

uint32_t addr_high;

sys/dev/pci/if_icereg.h

12266

uint32_t addr_low;

sys/dev/pci/if_icereg.h

12271

uint32_t prtdcb_ruptq;

sys/dev/pci/if_icereg.h

12272

uint32_t qtx_ctl;

sys/dev/pci/if_icereg.h

12293

uint32_t idx; /* In table entries for tables, in bytes for memory */

sys/dev/pci/if_icereg.h

12294

uint32_t addr_high;

sys/dev/pci/if_icereg.h

12295

uint32_t addr_low;

sys/dev/pci/if_icereg.h

12388

uint32_t addr_high;

sys/dev/pci/if_icereg.h

12389

uint32_t addr_low;

sys/dev/pci/if_icereg.h

12396

uint32_t addr_high;

sys/dev/pci/if_icereg.h

12397

uint32_t addr_low;

sys/dev/pci/if_icereg.h

12409

uint32_t internal_data1;

sys/dev/pci/if_icereg.h

12411

uint32_t internal_data2;

sys/dev/pci/if_icereg.h

12416

uint32_t reserved[4];

sys/dev/pci/if_icereg.h

12440

uint32_t fw_rt_lsb;

sys/dev/pci/if_icereg.h

12449

uint32_t addr_high;

sys/dev/pci/if_icereg.h

12450

uint32_t addr_low;

sys/dev/pci/if_icereg.h

12493

uint32_t cookie_high;

sys/dev/pci/if_icereg.h

12494

uint32_t cookie_low;

sys/dev/pci/if_icereg.h

12946

uint32_t combo_ver; /* Combo Image Version number */

sys/dev/pci/if_icereg.h

12969

uint32_t command; /* NVM command: READ or WRITE */

sys/dev/pci/if_icereg.h

12970

uint32_t config; /* NVM command configuration */

sys/dev/pci/if_icereg.h

12971

uint32_t offset; /* offset to read/write, in bytes */

sys/dev/pci/if_icereg.h

12972

uint32_t data_size; /* size of data field, in bytes */

sys/dev/pci/if_icereg.h

12977

uint32_t regval; /* Storage for register value */

sys/dev/pci/if_icereg.h

13012

uint32_t rss; /* RSS Hash */

sys/dev/pci/if_icereg.h

13013

uint32_t fd_id; /* Flow Director filter ID */

sys/dev/pci/if_icereg.h

13038

uint32_t rss; /* RSS Hash */

sys/dev/pci/if_icereg.h

13039

uint32_t fd_id; /* Flow Director filter ID */

sys/dev/pci/if_icereg.h

13053

uint32_t reserved;

sys/dev/pci/if_icereg.h

13054

uint32_t fd_id;

sys/dev/pci/if_icereg.h

13244

uint32_t known:1;

sys/dev/pci/if_icereg.h

13245

uint32_t outer_ip:1;

sys/dev/pci/if_icereg.h

13246

uint32_t outer_ip_ver:2;

sys/dev/pci/if_icereg.h

13247

uint32_t outer_frag:1;

sys/dev/pci/if_icereg.h

13248

uint32_t tunnel_type:3;

sys/dev/pci/if_icereg.h

13249

uint32_t tunnel_end_prot:2;

sys/dev/pci/if_icereg.h

13250

uint32_t tunnel_end_frag:1;

sys/dev/pci/if_icereg.h

13251

uint32_t inner_prot:4;

sys/dev/pci/if_icereg.h

13252

uint32_t payload_layer:3;

sys/dev/pci/if_icereg.h

13403

uint32_t ts_high;

sys/dev/pci/if_icereg.h

13427

uint32_t rss_hash;

sys/dev/pci/if_icereg.h

13437

uint32_t flow_id;

sys/dev/pci/if_icereg.h

13443

uint32_t ts_high;

sys/dev/pci/if_icereg.h

13473

uint32_t rsvd; /* flex words 2-3 are reserved */

sys/dev/pci/if_icereg.h

13474

uint32_t ts_high;

sys/dev/pci/if_icereg.h

13505

uint32_t rsvd; /* flex words 2-3 are reserved */

sys/dev/pci/if_icereg.h

13506

uint32_t ts_high;

sys/dev/pci/if_icereg.h

13539

uint32_t ts_high;

sys/dev/pci/if_icereg.h

13561

uint32_t rss_hash;

sys/dev/pci/if_icereg.h

13578

uint32_t ts_high;

sys/dev/pci/if_icereg.h

13769

#define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(uint32_t))

sys/dev/pci/if_icereg.h

13771

#define ICE_TXQ_CTX_SZ (ICE_TXQ_CTX_SIZE_DWORDS * sizeof(uint32_t))

sys/dev/pci/if_icereg.h

13800

uint32_t rxmax; /* bigger than needed, see above for reason */

sys/dev/pci/if_icereg.h

13910

uint32_t tunneling_params;

sys/dev/pci/if_icereg.h

14024

uint32_t qlen; /* bigger than needed, see above for reason */

sys/dev/pci/if_icereg.h

14059

uint32_t q_len;

sys/dev/pci/if_icereg.h

14062

uint32_t wrt_ptr;

sys/dev/pci/if_icereg.h

14071

uint32_t cmpltn_cache[16];

sys/dev/pci/if_icereg.h

14079

uint32_t db;

sys/dev/pci/if_icereg.h

9520

uint32_t param0;

sys/dev/pci/if_icereg.h

9521

uint32_t param1;

sys/dev/pci/if_icereg.h

9522

uint32_t addr_high;

sys/dev/pci/if_icereg.h

9523

uint32_t addr_low;

sys/dev/pci/if_icereg.h

9528

uint32_t rom_ver;

sys/dev/pci/if_icereg.h

9529

uint32_t fw_build;

sys/dev/pci/if_icereg.h

9547

uint32_t addr_high;

sys/dev/pci/if_icereg.h

9548

uint32_t addr_low;

sys/dev/pci/if_icereg.h

9560

uint32_t reason;

sys/dev/pci/if_icereg.h

9562

uint32_t identifier;

sys/dev/pci/if_icereg.h

9583

uint32_t timeout;

sys/dev/pci/if_icereg.h

9589

uint32_t res_number;

sys/dev/pci/if_icereg.h

9605

uint32_t count;

sys/dev/pci/if_icereg.h

9606

uint32_t addr_high;

sys/dev/pci/if_icereg.h

9607

uint32_t addr_low;

sys/dev/pci/if_icereg.h

9661

uint32_t number;

sys/dev/pci/if_icereg.h

9663

uint32_t logical_id;

sys/dev/pci/if_icereg.h

9665

uint32_t phys_id;

sys/dev/pci/if_icereg.h

9686

uint32_t addr_high;

sys/dev/pci/if_icereg.h

9687

uint32_t addr_low;

sys/dev/pci/if_icereg.h

9711

uint32_t addr_high;

sys/dev/pci/if_icereg.h

9712

uint32_t addr_low;

sys/dev/pci/if_icereg.h

9742

uint32_t addr_high;

sys/dev/pci/if_icereg.h

9743

uint32_t addr_low;

sys/dev/pci/if_icereg.h

9843

uint32_t addr_high;

sys/dev/pci/if_icereg.h

9844

uint32_t addr_low;

sys/dev/pci/if_icereg.h

9862

uint32_t addr_high;

sys/dev/pci/if_icereg.h

9863

uint32_t addr_low;

sys/dev/pci/if_icereg.h

9890

uint32_t reserved;

sys/dev/pci/if_icereg.h

9899

uint32_t addr_high;

sys/dev/pci/if_icereg.h

9900

uint32_t addr_low;

sys/dev/pci/if_icereg.h

9958

uint32_t addr_high;

sys/dev/pci/if_icereg.h

9959

uint32_t addr_low;

sys/dev/pci/if_icereg.h

9972

uint32_t addr_high;

sys/dev/pci/if_icereg.h

9973

uint32_t addr_low;

sys/dev/pci/if_icereg.h

9985

uint32_t addr_high;

sys/dev/pci/if_icereg.h

9986

uint32_t addr_low;

sys/dev/pci/if_icevar.h

1003

uint32_t switching_mode;

sys/dev/pci/if_icevar.h

1008

uint32_t mgmt_mode;

sys/dev/pci/if_icevar.h

1013

uint32_t mgmt_protocols_mctp;

sys/dev/pci/if_icevar.h

1019

uint32_t os2bmc;

sys/dev/pci/if_icevar.h

1020

uint32_t valid_functions;

sys/dev/pci/if_icevar.h

1022

uint32_t active_tc_bitmap;

sys/dev/pci/if_icevar.h

1023

uint32_t maxtc;

sys/dev/pci/if_icevar.h

1026

uint32_t rss_table_size; /* 512 for PFs and 64 for VFs */

sys/dev/pci/if_icevar.h

1027

uint32_t rss_table_entry_width; /* RSS Entry width in bits */

sys/dev/pci/if_icevar.h

1030

uint32_t num_rxq; /* Number/Total Rx queues */

sys/dev/pci/if_icevar.h

1031

uint32_t rxq_first_id; /* First queue ID for Rx queues */

sys/dev/pci/if_icevar.h

1032

uint32_t num_txq; /* Number/Total Tx queues */

sys/dev/pci/if_icevar.h

1033

uint32_t txq_first_id; /* First queue ID for Tx queues */

sys/dev/pci/if_icevar.h

1036

uint32_t num_msix_vectors;

sys/dev/pci/if_icevar.h

1037

uint32_t msix_vector_first_id;

sys/dev/pci/if_icevar.h

1040

uint32_t max_mtu;

sys/dev/pci/if_icevar.h

1043

uint32_t num_wol_proxy_fltr;

sys/dev/pci/if_icevar.h

1044

uint32_t wol_proxy_vsi_seid;

sys/dev/pci/if_icevar.h

1047

uint32_t led_pin_num;

sys/dev/pci/if_icevar.h

1048

uint32_t sdp_pin_num;

sys/dev/pci/if_icevar.h

1094

uint32_t ext_topo_dev_img_ver_high[ICE_EXT_TOPO_DEV_IMG_COUNT];

sys/dev/pci/if_icevar.h

1095

uint32_t ext_topo_dev_img_ver_low[ICE_EXT_TOPO_DEV_IMG_COUNT];

sys/dev/pci/if_icevar.h

116

typedef uint32_t ice_bitmap_t;

sys/dev/pci/if_icevar.h

1170

uint32_t agg_id; /* aggregator group ID */

sys/dev/pci/if_icevar.h

1251

uint32_t srev; /* Security revision */

sys/dev/pci/if_icevar.h

1256

uint32_t eetrack;

sys/dev/pci/if_icevar.h

1257

uint32_t srev;

sys/dev/pci/if_icevar.h

1264

uint32_t nvm;

sys/dev/pci/if_icevar.h

1265

uint32_t orom;

sys/dev/pci/if_icevar.h

1272

uint32_t major; /* major high/low */

sys/dev/pci/if_icevar.h

1273

uint32_t minor; /* minor high/low */

sys/dev/pci/if_icevar.h

1274

uint32_t type; /* type high/low */

sys/dev/pci/if_icevar.h

1275

uint32_t rev; /* revision high/low */

sys/dev/pci/if_icevar.h

1276

uint32_t hash; /* SHA-1 hash word */

sys/dev/pci/if_icevar.h

1300

uint32_t nvm_ptr; /* Pointer to 1st NVM bank */

sys/dev/pci/if_icevar.h

1301

uint32_t nvm_size; /* Size of NVM bank */

sys/dev/pci/if_icevar.h

1302

uint32_t orom_ptr; /* Pointer to 1st OROM bank */

sys/dev/pci/if_icevar.h

1303

uint32_t orom_size; /* Size of OROM bank */

sys/dev/pci/if_icevar.h

1304

uint32_t netlist_ptr; /* Pointer to 1st Netlist bank */

sys/dev/pci/if_icevar.h

1305

uint32_t netlist_size; /* Size of Netlist bank */

sys/dev/pci/if_icevar.h

1318

uint32_t flash_size; /* Size of available flash in bytes */

sys/dev/pci/if_icevar.h

1506

uint32_t num_allocd_vfs; /* Number of allocated VFs */

sys/dev/pci/if_icevar.h

1507

uint32_t vf_base_id; /* Logical ID of the first VF */

sys/dev/pci/if_icevar.h

1508

uint32_t guar_num_vsi;

sys/dev/pci/if_icevar.h

1512

uint32_t mode;

sys/dev/pci/if_icevar.h

1519

uint32_t num_vfs_exposed; /* Total number of VFs exposed */

sys/dev/pci/if_icevar.h

1520

uint32_t num_vsi_allocd_to_host; /* Excluding EMP VSI */

sys/dev/pci/if_icevar.h

1521

uint32_t num_funcs;

sys/dev/pci/if_icevar.h

1524

uint32_t supported_sensors;

sys/dev/pci/if_icevar.h

1626

uint32_t bw;

sys/dev/pci/if_icevar.h

1635

uint32_t shared_bw;

sys/dev/pci/if_icevar.h

1641

uint32_t q_teid;

sys/dev/pci/if_icevar.h

1690

uint32_t agg_id;

sys/dev/pci/if_icevar.h

1811

uint32_t ouisubtype;

sys/dev/pci/if_icevar.h

1823

uint32_t seqno;

sys/dev/pci/if_icevar.h

1824

uint32_t ackno;

sys/dev/pci/if_icevar.h

1887

uint32_t numapps;

sys/dev/pci/if_icevar.h

1888

uint32_t tlv_status; /* CEE mode TLV status */

sys/dev/pci/if_icevar.h

2189

uint32_t vlan_id;

sys/dev/pci/if_icevar.h

2206

uint32_t src_addr;

sys/dev/pci/if_icevar.h

2207

uint32_t dst_addr;

sys/dev/pci/if_icevar.h

2213

uint32_t flow_label : 20;

sys/dev/pci/if_icevar.h

2214

uint32_t tc : 8;

sys/dev/pci/if_icevar.h

2215

uint32_t version : 4;

sys/dev/pci/if_icevar.h

2217

uint32_t val;

sys/dev/pci/if_icevar.h

2222

uint32_t be_ver_tc_flow;

sys/dev/pci/if_icevar.h

2233

uint32_t verification_tag;

sys/dev/pci/if_icevar.h

2234

uint32_t check;

sys/dev/pci/if_icevar.h

2247

uint32_t vni; /* only use lower 24-bits */

sys/dev/pci/if_icevar.h

2254

uint32_t teid;

sys/dev/pci/if_icevar.h

2272

uint32_t session_id;

sys/dev/pci/if_icevar.h

2279

uint32_t tni_flow;

sys/dev/pci/if_icevar.h

2343

uint32_t track_id;

sys/dev/pci/if_icevar.h

2439

uint32_t last_node_teid; /* scheduler last node info */

sys/dev/pci/if_icevar.h

2513

uint32_t bw; /* requested */

sys/dev/pci/if_icevar.h

2539

uint32_t act;

sys/dev/pci/if_icevar.h

2576

uint32_t priority;

sys/dev/pci/if_icevar.h

2733

#define ICE_IPV4_MAKE_PREFIX_MASK(prefix) ((uint32_t)((~0ULL) << (32 - (prefix))))

sys/dev/pci/if_icevar.h

2900

uint32_t addl_hdrs; /* protocol header fields */

sys/dev/pci/if_icevar.h

2925

#define ICE_FLOW_SET_HDRS(seg, val) ((seg)->hdrs |= (uint32_t)(val))

sys/dev/pci/if_icevar.h

2960

uint32_t hdrs; /* Bitmask indicating protocol headers present */

sys/dev/pci/if_icevar.h

3024

uint32_t dummy;

sys/dev/pci/if_icevar.h

3111

uint32_t seg_count;

sys/dev/pci/if_icevar.h

3112

uint32_t seg_offset[STRUCT_HACK_VAR_LEN];

sys/dev/pci/if_icevar.h

3129

uint32_t seg_type;

sys/dev/pci/if_icevar.h

3131

uint32_t seg_size;

sys/dev/pci/if_icevar.h

3142

uint32_t id;

sys/dev/pci/if_icevar.h

3152

uint32_t device_table_count;

sys/dev/pci/if_icevar.h

3157

uint32_t table_count;

sys/dev/pci/if_icevar.h

3158

uint32_t vers[STRUCT_HACK_VAR_LEN];

sys/dev/pci/if_icevar.h

3167

uint32_t buf_count;

sys/dev/pci/if_icevar.h

3181

uint32_t rsvd;

sys/dev/pci/if_icevar.h

3192

uint32_t seg_id;

sys/dev/pci/if_icevar.h

3193

uint32_t sign_type;

sys/dev/pci/if_icevar.h

3194

uint32_t signed_seg_idx;

sys/dev/pci/if_icevar.h

3195

uint32_t signed_buf_start;

sys/dev/pci/if_icevar.h

3196

uint32_t signed_buf_count;

sys/dev/pci/if_icevar.h

3204

uint32_t type;

sys/dev/pci/if_icevar.h

3393

uint32_t buf_idx;

sys/dev/pci/if_icevar.h

3395

uint32_t type;

sys/dev/pci/if_icevar.h

3397

uint32_t sect_idx;

sys/dev/pci/if_icevar.h

3399

uint32_t sect_type;

sys/dev/pci/if_icevar.h

3401

uint32_t entry_idx;

sys/dev/pci/if_icevar.h

3402

void *(*handler)(uint32_t sect_type, void *section, uint32_t index,

sys/dev/pci/if_icevar.h

3403

uint32_t *offset);

sys/dev/pci/if_icevar.h

3434

uint32_t offset;

sys/dev/pci/if_icevar.h

3435

uint32_t length;

sys/dev/pci/if_icevar.h

3587

uint32_t sid;

sys/dev/pci/if_icevar.h

3657

uint32_t prop_mask;

sys/dev/pci/if_icevar.h

3670

uint32_t sid;

sys/dev/pci/if_icevar.h

3695

uint32_t sid;

sys/dev/pci/if_icevar.h

3709

uint32_t val;

sys/dev/pci/if_icevar.h

3745

uint32_t sid;

sys/dev/pci/if_icevar.h

3784

uint32_t sid;

sys/dev/pci/if_icevar.h

3885

uint32_t psm_clk_freq;

sys/dev/pci/if_icevar.h

3936

uint32_t fw_build; /* firmware build number */

sys/dev/pci/if_icevar.h

3973

uint32_t pkg_seg_id;

sys/dev/pci/if_icevar.h

3974

uint32_t pkg_sign_type;

sys/dev/pci/if_icevar.h

3975

uint32_t active_track_id;

sys/dev/pci/if_icevar.h

3993

uint32_t pkg_size;

sys/dev/pci/if_icevar.h

4063

ice_set_state(volatile uint32_t *s, enum ice_state bit)

sys/dev/pci/if_icevar.h

4076

ice_clear_state(volatile uint32_t *s, enum ice_state bit)

sys/dev/pci/if_icevar.h

4089

static inline uint32_t

sys/dev/pci/if_icevar.h

4090

ice_testandset_state(volatile uint32_t *s, enum ice_state bit)

sys/dev/pci/if_icevar.h

4092

uint32_t expected = *s;

sys/dev/pci/if_icevar.h

4093

uint32_t previous;

sys/dev/pci/if_icevar.h

4107

static inline uint32_t

sys/dev/pci/if_icevar.h

4108

ice_testandclear_state(volatile uint32_t *s, enum ice_state bit)

sys/dev/pci/if_icevar.h

4110

uint32_t expected = *s;

sys/dev/pci/if_icevar.h

4111

uint32_t previous;

sys/dev/pci/if_icevar.h

4126

static inline uint32_t

sys/dev/pci/if_icevar.h

4127

ice_test_state(volatile uint32_t *s, enum ice_state bit)

sys/dev/pci/if_icevar.h

4132

static inline uint32_t ice_round_to_num(uint32_t N, uint32_t R)

sys/dev/pci/if_icevar.h

4151

static inline uint32_t

sys/dev/pci/if_icevar.h

4152

ice_popcount32(uint32_t n32)

sys/dev/pci/if_icevar.h

4169

typedef uint32_t ice_bitstr_t;

sys/dev/pci/if_icevar.h

4501

uint32_t tx_lpi_status;

sys/dev/pci/if_icevar.h

4502

uint32_t rx_lpi_status;

sys/dev/pci/if_icevar.h

4527

uint32_t corer_count;

sys/dev/pci/if_icevar.h

4528

uint32_t globr_count;

sys/dev/pci/if_icevar.h

4529

uint32_t empr_count;

sys/dev/pci/if_icevar.h

4530

uint32_t pfr_count;

sys/dev/pci/if_icevar.h

4533

uint32_t tx_mdd_count;

sys/dev/pci/if_icevar.h

4534

uint32_t rx_mdd_count;

sys/dev/pci/if_icevar.h

4569

uint32_t tail;

sys/dev/pci/if_icevar.h

4571

uint32_t q_teid;

sys/dev/pci/if_icevar.h

4572

uint32_t me;

sys/dev/pci/if_icevar.h

4616

uint32_t tail;

sys/dev/pci/if_icevar.h

4618

uint32_t me;

sys/dev/pci/if_icevar.h

574

ice_bitmap_from_array32(ice_bitmap_t *dst, uint32_t *src, uint16_t size)

sys/dev/pci/if_icevar.h

576

uint32_t remaining_bits, i;

sys/dev/pci/if_icevar.h

578

#define BITS_PER_U32 (sizeof(uint32_t) * 8)

sys/dev/pci/if_icevar.h

582

for (i = 0; i < (uint32_t)(size / BITS_PER_U32); i++) {

sys/dev/pci/if_icevar.h

583

uint32_t bit_offset = i * BITS_PER_U32;

sys/dev/pci/if_icevar.h

584

uint32_t entry = src[i];

sys/dev/pci/if_icevar.h

585

uint32_t j;

sys/dev/pci/if_icevar.h

598

uint32_t bit_offset = i * BITS_PER_U32;

sys/dev/pci/if_icevar.h

599

uint32_t entry = src[i];

sys/dev/pci/if_icevar.h

600

uint32_t j;

sys/dev/pci/if_icevar.h

935

uint32_t head;

sys/dev/pci/if_icevar.h

936

uint32_t tail;

sys/dev/pci/if_icevar.h

937

uint32_t len;

sys/dev/pci/if_icevar.h

938

uint32_t bah;

sys/dev/pci/if_icevar.h

939

uint32_t bal;

sys/dev/pci/if_icevar.h

940

uint32_t len_mask;

sys/dev/pci/if_icevar.h

941

uint32_t len_ena_mask;

sys/dev/pci/if_icevar.h

942

uint32_t len_crit_mask;

sys/dev/pci/if_icevar.h

943

uint32_t head_mask;

sys/dev/pci/if_icevar.h

964

uint32_t sq_cmd_timeout; /* send queue cmd write back timeout */

sys/dev/pci/if_igc.c

101

void igc_init_dmac(struct igc_softc *, uint32_t);

sys/dev/pci/if_igc.c

117

void igc_rx_checksum(uint32_t, struct mbuf *, uint32_t);

sys/dev/pci/if_igc.c

124

int igc_tx_ctx_setup(struct igc_txring *, struct mbuf *, int, uint32_t *,

sys/dev/pci/if_igc.c

125

uint32_t *);

sys/dev/pci/if_igc.c

128

void igc_set_queues(struct igc_softc *, uint32_t, uint32_t, int);

sys/dev/pci/if_igc.c

129

void igc_enable_queue(struct igc_softc *, uint32_t);

sys/dev/pci/if_igc.c

1309

uint32_t ptype, staterr = 0;

sys/dev/pci/if_igc.c

1319

uint32_t hash;

sys/dev/pci/if_igc.c

1444

igc_rx_checksum(uint32_t staterr, struct mbuf *m, uint32_t ptype)

sys/dev/pci/if_igc.c

1589

uint32_t reg_rctl = 0;

sys/dev/pci/if_igc.c

1705

uint32_t ivar, newitr = 0;

sys/dev/pci/if_igc.c

1734

igc_set_queues(struct igc_softc *sc, uint32_t entry, uint32_t vector, int type)

sys/dev/pci/if_igc.c

1737

uint32_t ivar, index;

sys/dev/pci/if_igc.c

1762

igc_enable_queue(struct igc_softc *sc, uint32_t eims)

sys/dev/pci/if_igc.c

1771

uint32_t mask;

sys/dev/pci/if_igc.c

1796

uint32_t reg_icr = IGC_READ_REG(&sc->hw, IGC_ICR);

sys/dev/pci/if_igc.c

1936

uint32_t tctl, txdctl = 0;

sys/dev/pci/if_igc.c

1948

IGC_WRITE_REG(hw, IGC_TDBAH(i), (uint32_t)(bus_addr >> 32));

sys/dev/pci/if_igc.c

1949

IGC_WRITE_REG(hw, IGC_TDBAL(i), (uint32_t)bus_addr);

sys/dev/pci/if_igc.c

2042

uint32_t *cmd_type_len, uint32_t *olinfo_status)

sys/dev/pci/if_igc.c

2046

uint32_t mss_l4len_idx = 0;

sys/dev/pci/if_igc.c

2047

uint32_t type_tucmd_mlhl = 0;

sys/dev/pci/if_igc.c

2048

uint32_t vlan_macip_lens = 0;

sys/dev/pci/if_igc.c

2058

uint32_t vtag = mp->m_pkthdr.ether_vtag;

sys/dev/pci/if_igc.c

2100

uint32_t hdrlen, thlen, paylen, outlen;

sys/dev/pci/if_igc.c

2247

uint32_t rctl, rxcsum, srrctl = 0;

sys/dev/pci/if_igc.c

2310

uint32_t rxdctl;

sys/dev/pci/if_igc.c

2316

IGC_WRITE_REG(hw, IGC_RDBAH(i), (uint32_t)(bus_addr >> 32));

sys/dev/pci/if_igc.c

2317

IGC_WRITE_REG(hw, IGC_RDBAL(i), (uint32_t)bus_addr);

sys/dev/pci/if_igc.c

2400

uint32_t rss_key[10], mrqc, reta, shift = 0;

sys/dev/pci/if_igc.c

2428

reta = reta | ( ((uint32_t) queue_id) << 24);

sys/dev/pci/if_igc.c

2467

uint32_t ctrl_ext;

sys/dev/pci/if_igc.c

2482

uint32_t ctrl_ext;

sys/dev/pci/if_igc.c

2578

uint32_t reg;

sys/dev/pci/if_igc.c

2713

uint32_t hi, lo;

sys/dev/pci/if_igc.c

504

uint32_t pba;

sys/dev/pci/if_igc.c

570

igc_init_dmac(struct igc_softc *sc, uint32_t pba)

sys/dev/pci/if_igc.c

573

uint32_t dmac, reg = ~IGC_DMACR_DMAC_EN;

sys/dev/pci/if_igc.c

856

uint32_t ctrl = 0;

sys/dev/pci/if_igc.c

971

uint32_t cmd_type_len;

sys/dev/pci/if_igc.c

972

uint32_t olinfo_status;

sys/dev/pci/if_igc.h

218

uint32_t eop_index;

sys/dev/pci/if_igc.h

247

uint32_t msix;

sys/dev/pci/if_igc.h

248

uint32_t eims;

sys/dev/pci/if_igc.h

249

uint32_t eitr_setting;

sys/dev/pci/if_igc.h

263

uint32_t me;

sys/dev/pci/if_igc.h

264

uint32_t watchdog_timer;

sys/dev/pci/if_igc.h

268

uint32_t next_avail_desc;

sys/dev/pci/if_igc.h

269

uint32_t next_to_clean;

sys/dev/pci/if_igc.h

279

uint32_t me;

sys/dev/pci/if_igc.h

283

uint32_t last_desc_filled;

sys/dev/pci/if_igc.h

284

uint32_t next_to_check;

sys/dev/pci/if_igc.h

303

uint32_t dmac;

sys/dev/pci/if_igc.h

310

uint32_t max_frame_size;

sys/dev/pci/if_igc.h

311

uint32_t rx_mbuf_sz;

sys/dev/pci/if_igc.h

312

uint32_t linkvec;

sys/dev/pci/if_igc.h

313

uint32_t msix_linkmask;

sys/dev/pci/if_igc.h

314

uint32_t msix_queuesmask;

sys/dev/pci/if_ipw.c

1024

uint32_t r, i;

sys/dev/pci/if_ipw.c

1048

uint32_t r;

sys/dev/pci/if_ipw.c

1081

ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len)

sys/dev/pci/if_ipw.c

110

MEM_READ_1(struct ipw_softc *sc, uint32_t addr)

sys/dev/pci/if_ipw.c

116

static __inline uint32_t

sys/dev/pci/if_ipw.c

117

MEM_READ_4(struct ipw_softc *sc, uint32_t addr)

sys/dev/pci/if_ipw.c

1401

uint32_t

sys/dev/pci/if_ipw.c

1402

ipw_read_table1(struct ipw_softc *sc, uint32_t off)

sys/dev/pci/if_ipw.c

1408

ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info)

sys/dev/pci/if_ipw.c

1414

ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len)

sys/dev/pci/if_ipw.c

1416

uint32_t addr, info;

sys/dev/pci/if_ipw.c

1418

uint32_t total;

sys/dev/pci/if_ipw.c

1441

uint32_t tmp;

sys/dev/pci/if_ipw.c

1464

uint32_t tmp;

sys/dev/pci/if_ipw.c

1550

uint32_t tmp, dst;

sys/dev/pci/if_ipw.c

1698

uint32_t data;

sys/dev/pci/if_ipw.c

1814

uint32_t data;

sys/dev/pci/if_ipw.c

635

uint32_t val;

sys/dev/pci/if_ipw.c

643

uint32_t val;

sys/dev/pci/if_ipw.c

723

uint32_t tmp;

sys/dev/pci/if_ipw.c

793

uint32_t state;

sys/dev/pci/if_ipw.c

798

state = letoh32(*mtod(sbuf->m, uint32_t *));

sys/dev/pci/if_ipw.c

82

int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t);

sys/dev/pci/if_ipw.c

90

uint32_t ipw_read_table1(struct ipw_softc *, uint32_t);

sys/dev/pci/if_ipw.c

91

void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t);

sys/dev/pci/if_ipw.c

92

int ipw_read_table2(struct ipw_softc *, uint32_t, void *,

sys/dev/pci/if_ipw.c

93

uint32_t *);

sys/dev/pci/if_ipw.c

931

uint32_t r, i;

sys/dev/pci/if_ipwreg.h

108

uint32_t version;

sys/dev/pci/if_ipwreg.h

109

uint32_t main_size; /* firmware size */

sys/dev/pci/if_ipwreg.h

110

uint32_t ucode_size; /* microcode size */

sys/dev/pci/if_ipwreg.h

115

uint32_t physaddr;

sys/dev/pci/if_ipwreg.h

116

uint32_t len;

sys/dev/pci/if_ipwreg.h

129

uint32_t len;

sys/dev/pci/if_ipwreg.h

144

uint32_t type;

sys/dev/pci/if_ipwreg.h

146

uint32_t subtype;

sys/dev/pci/if_ipwreg.h

160

uint32_t type;

sys/dev/pci/if_ipwreg.h

188

uint32_t subtype;

sys/dev/pci/if_ipwreg.h

189

uint32_t seq;

sys/dev/pci/if_ipwreg.h

190

uint32_t len;

sys/dev/pci/if_ipwreg.h

192

uint32_t status;

sys/dev/pci/if_ipwreg.h

217

uint32_t ciphers;

sys/dev/pci/if_ipwreg.h

232

uint32_t flags;

sys/dev/pci/if_ipwreg.h

236

uint32_t channels;

sys/dev/pci/if_ipwreg.h

241

uint32_t flags;

sys/dev/pci/if_ipwreg.h

248

uint32_t bss_chan;

sys/dev/pci/if_ipwreg.h

249

uint32_t ibss_chan;

sys/dev/pci/if_ipwreg.h

261

uint32_t optie_len;

sys/dev/pci/if_ipwvar.h

125

uint32_t table1_base;

sys/dev/pci/if_ipwvar.h

126

uint32_t table2_base;

sys/dev/pci/if_ipwvar.h

128

uint32_t txcur;

sys/dev/pci/if_ipwvar.h

129

uint32_t txold;

sys/dev/pci/if_ipwvar.h

130

uint32_t rxcur;

sys/dev/pci/if_iwi.c

1071

letoh32(*(uint32_t *)(notif + 1)) & 0xff));

sys/dev/pci/if_iwi.c

1085

uint32_t hw;

sys/dev/pci/if_iwi.c

1128

uint32_t hw;

sys/dev/pci/if_iwi.c

115

MEM_READ_1(struct iwi_softc *sc, uint32_t addr)

sys/dev/pci/if_iwi.c

1155

uint32_t r;

sys/dev/pci/if_iwi.c

121

static __inline uint32_t

sys/dev/pci/if_iwi.c

122

MEM_READ_4(struct iwi_softc *sc, uint32_t addr)

sys/dev/pci/if_iwi.c

1500

uint32_t tmp;

sys/dev/pci/if_iwi.c

1524

uint32_t tmp;

sys/dev/pci/if_iwi.c

1567

uint32_t tmp;

sys/dev/pci/if_iwi.c

1638

uint32_t sentinel, tmp, ctl, src, dst, sum, len, mlen;

sys/dev/pci/if_iwi.c

1774

uint32_t data;

sys/dev/pci/if_iwi.c

2020

uint32_t data;

sys/dev/pci/if_iwi.c

658

uint32_t val;

sys/dev/pci/if_iwi.c

728

uint32_t tmp;

sys/dev/pci/if_iwi.c

794

uint32_t tmp;

sys/dev/pci/if_iwireg.h

117

uint32_t reserved[2];

sys/dev/pci/if_iwireg.h

168

uint32_t status;

sys/dev/pci/if_iwireg.h

171

uint32_t count;

sys/dev/pci/if_iwireg.h

176

uint32_t reserved1[2];

sys/dev/pci/if_iwireg.h

194

uint32_t reserved1;

sys/dev/pci/if_iwireg.h

223

uint32_t iv[2];

sys/dev/pci/if_iwireg.h

225

uint32_t nseg;

sys/dev/pci/if_iwireg.h

229

uint32_t seg_addr[IWI_MAX_NSEG];

sys/dev/pci/if_iwireg.h

360

uint32_t reserved3;

sys/dev/pci/if_iwireg.h

366

uint32_t index;

sys/dev/pci/if_iwireg.h

97

uint32_t bootsz;

sys/dev/pci/if_iwireg.h

98

uint32_t ucodesz;

sys/dev/pci/if_iwireg.h

99

uint32_t mainsz;

sys/dev/pci/if_iwivar.h

79

uint32_t reg;

sys/dev/pci/if_iwm.c

10134

uint32_t dev_phy_addr;

sys/dev/pci/if_iwm.c

1044

uint32_t

sys/dev/pci/if_iwm.c

1045

iwm_read_prph_unlocked(struct iwm_softc *sc, uint32_t addr)

sys/dev/pci/if_iwm.c

1053

uint32_t

sys/dev/pci/if_iwm.c

1054

iwm_read_prph(struct iwm_softc *sc, uint32_t addr)

sys/dev/pci/if_iwm.c

1061

iwm_write_prph_unlocked(struct iwm_softc *sc, uint32_t addr, uint32_t val)

sys/dev/pci/if_iwm.c

1070

iwm_write_prph(struct iwm_softc *sc, uint32_t addr, uint32_t val)

sys/dev/pci/if_iwm.c

10723

uint32_t valid; /* (nonzero) valid, (0) log is empty */

sys/dev/pci/if_iwm.c

10724

uint32_t error_id; /* type of error */

sys/dev/pci/if_iwm.c

10725

uint32_t trm_hw_status0; /* TRM HW status */

sys/dev/pci/if_iwm.c

10726

uint32_t trm_hw_status1; /* TRM HW status */

sys/dev/pci/if_iwm.c

10727

uint32_t blink2; /* branch link */

sys/dev/pci/if_iwm.c

10728

uint32_t ilink1; /* interrupt link */

sys/dev/pci/if_iwm.c

10729

uint32_t ilink2; /* interrupt link */

sys/dev/pci/if_iwm.c

10730

uint32_t data1; /* error-specific data */

sys/dev/pci/if_iwm.c

10731

uint32_t data2; /* error-specific data */

sys/dev/pci/if_iwm.c

10732

uint32_t data3; /* error-specific data */

sys/dev/pci/if_iwm.c

10733

uint32_t bcon_time; /* beacon timer */

sys/dev/pci/if_iwm.c

10734

uint32_t tsf_low; /* network timestamp function timer */

sys/dev/pci/if_iwm.c

10735

uint32_t tsf_hi; /* network timestamp function timer */

sys/dev/pci/if_iwm.c

10736

uint32_t gp1; /* GP1 timer register */

sys/dev/pci/if_iwm.c

10737

uint32_t gp2; /* GP2 timer register */

sys/dev/pci/if_iwm.c

10738

uint32_t fw_rev_type; /* firmware revision type */

sys/dev/pci/if_iwm.c

10739

uint32_t major; /* uCode version major */

sys/dev/pci/if_iwm.c

10740

uint32_t minor; /* uCode version minor */

sys/dev/pci/if_iwm.c

10741

uint32_t hw_ver; /* HW Silicon version */

sys/dev/pci/if_iwm.c

10742

uint32_t brd_ver; /* HW board version */

sys/dev/pci/if_iwm.c

10743

uint32_t log_pc; /* log program counter */

sys/dev/pci/if_iwm.c

10744

uint32_t frame_ptr; /* frame pointer */

sys/dev/pci/if_iwm.c

10745

uint32_t stack_ptr; /* stack pointer */

sys/dev/pci/if_iwm.c

10746

uint32_t hcmd; /* last host command header */

sys/dev/pci/if_iwm.c

10747

uint32_t isr0; /* isr status register LMPM_NIC_ISR0:

sys/dev/pci/if_iwm.c

10749

uint32_t isr1; /* isr status register LMPM_NIC_ISR1:

sys/dev/pci/if_iwm.c

10751

uint32_t isr2; /* isr status register LMPM_NIC_ISR2:

sys/dev/pci/if_iwm.c

10753

uint32_t isr3; /* isr status register LMPM_NIC_ISR3:

sys/dev/pci/if_iwm.c

10755

uint32_t isr4; /* isr status register LMPM_NIC_ISR4:

sys/dev/pci/if_iwm.c

10757

uint32_t last_cmd_id; /* last HCMD id handled by the firmware */

sys/dev/pci/if_iwm.c

10758

uint32_t wait_event; /* wait event() caller address */

sys/dev/pci/if_iwm.c

10759

uint32_t l2p_control; /* L2pControlField */

sys/dev/pci/if_iwm.c

10760

uint32_t l2p_duration; /* L2pDurationField */

sys/dev/pci/if_iwm.c

10761

uint32_t l2p_mhvalid; /* L2pMhValidBits */

sys/dev/pci/if_iwm.c

10762

uint32_t l2p_addr_match; /* L2pAddrMatchStat */

sys/dev/pci/if_iwm.c

10763

uint32_t lmpm_pmg_sel; /* indicate which clocks are turned on

sys/dev/pci/if_iwm.c

10765

uint32_t u_timestamp; /* indicate when the date and time of the

sys/dev/pci/if_iwm.c

10767

uint32_t flow_handler; /* FH read/write pointers, RX credit */

sys/dev/pci/if_iwm.c

10778

uint32_t valid; /* (nonzero) valid, (0) log is empty */

sys/dev/pci/if_iwm.c

10779

uint32_t error_id; /* type of error */

sys/dev/pci/if_iwm.c

10780

uint32_t blink1; /* branch link */

sys/dev/pci/if_iwm.c

10781

uint32_t blink2; /* branch link */

sys/dev/pci/if_iwm.c

10782

uint32_t ilink1; /* interrupt link */

sys/dev/pci/if_iwm.c

10783

uint32_t ilink2; /* interrupt link */

sys/dev/pci/if_iwm.c

10784

uint32_t data1; /* error-specific data */

sys/dev/pci/if_iwm.c

10785

uint32_t data2; /* error-specific data */

sys/dev/pci/if_iwm.c

10786

uint32_t data3; /* error-specific data */

sys/dev/pci/if_iwm.c

10787

uint32_t umac_major;

sys/dev/pci/if_iwm.c

10788

uint32_t umac_minor;

sys/dev/pci/if_iwm.c

10789

uint32_t frame_pointer; /* core register 27*/

sys/dev/pci/if_iwm.c

1079

iwm_write_prph(sc, (uint32_t)addr, val & 0xffffffff);

sys/dev/pci/if_iwm.c

10790

uint32_t stack_pointer; /* core register 28 */

sys/dev/pci/if_iwm.c

10791

uint32_t cmd_header; /* latest host cmd sent to UMAC */

sys/dev/pci/if_iwm.c

10792

uint32_t nic_isr_pref; /* ISR status register */

sys/dev/pci/if_iwm.c

10795

#define ERROR_START_OFFSET (1 * sizeof(uint32_t))

sys/dev/pci/if_iwm.c

10796

#define ERROR_ELEM_SIZE (7 * sizeof(uint32_t))

sys/dev/pci/if_iwm.c

1080

iwm_write_prph(sc, (uint32_t)addr + 4, val >> 32);

sys/dev/pci/if_iwm.c

10802

uint32_t base;

sys/dev/pci/if_iwm.c

10812

if (iwm_read_mem(sc, base, &table, sizeof(table)/sizeof(uint32_t))) {

sys/dev/pci/if_iwm.c

1084

iwm_read_mem(struct iwm_softc *sc, uint32_t addr, void *buf, int dwords)

sys/dev/pci/if_iwm.c

1087

uint32_t *vals = buf;

sys/dev/pci/if_iwm.c

10871

iwm_desc_lookup(uint32_t num)

sys/dev/pci/if_iwm.c

10895

uint32_t base;

sys/dev/pci/if_iwm.c

10905

if (iwm_read_mem(sc, base, &table, sizeof(table)/sizeof(uint32_t))) {

sys/dev/pci/if_iwm.c

1101

iwm_write_mem(struct iwm_softc *sc, uint32_t addr, const void *buf, int dwords)

sys/dev/pci/if_iwm.c

11017

uint32_t offset = 0, nextoff = 0, nmpdu = 0, len;

sys/dev/pci/if_iwm.c

1104

const uint32_t *vals = buf;

sys/dev/pci/if_iwm.c

1110

uint32_t val = vals ? vals[offs] : 0;

sys/dev/pci/if_iwm.c

1121

iwm_write_mem32(struct iwm_softc *sc, uint32_t addr, uint32_t val)

sys/dev/pci/if_iwm.c

1127

iwm_poll_bit(struct iwm_softc *sc, int reg, uint32_t bits, uint32_t mask,

sys/dev/pci/if_iwm.c

11308

uint32_t action;

sys/dev/pci/if_iwm.c

11377

uint32_t wreg;

sys/dev/pci/if_iwm.c

11417

uint32_t r1, r2;

sys/dev/pci/if_iwm.c

11422

uint32_t *ict = sc->ict_dma.vaddr;

sys/dev/pci/if_iwm.c

11551

uint32_t inta_fh, inta_hw;

sys/dev/pci/if_iwm.c

1188

iwm_set_bits_mask_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits,

sys/dev/pci/if_iwm.c

11883

uint32_t hw_step;

sys/dev/pci/if_iwm.c

1189

uint32_t mask)

sys/dev/pci/if_iwm.c

1191

uint32_t val;

sys/dev/pci/if_iwm.c

1204

iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pci/if_iwm.c

1210

iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pci/if_iwm.c

1287

descsz = sizeof(uint32_t);

sys/dev/pci/if_iwm.c

1311

size = count * sizeof(uint32_t);

sys/dev/pci/if_iwm.c

151

#define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_)))

sys/dev/pci/if_iwm.c

1573

uint32_t v;

sys/dev/pci/if_iwm.c

2016

uint32_t hpm, wprot;

sys/dev/pci/if_iwm.c

2083

uint32_t r;

sys/dev/pci/if_iwm.c

2152

uint32_t mask, val, reg_val = 0;

sys/dev/pci/if_iwm.c

2409

sizeof(uint32_t),

sys/dev/pci/if_iwm.c

2501

uint32_t base;

sys/dev/pci/if_iwm.c

2515

/ sizeof(uint32_t);

sys/dev/pci/if_iwm.c

252

void iwm_fw_version_str(char *, size_t, uint32_t, uint32_t, uint32_t);

sys/dev/pci/if_iwm.c

254

uint32_t iwm_read_prph_unlocked(struct iwm_softc *, uint32_t);

sys/dev/pci/if_iwm.c

255

uint32_t iwm_read_prph(struct iwm_softc *, uint32_t);

sys/dev/pci/if_iwm.c

256

void iwm_write_prph_unlocked(struct iwm_softc *, uint32_t, uint32_t);

sys/dev/pci/if_iwm.c

257

void iwm_write_prph(struct iwm_softc *, uint32_t, uint32_t);

sys/dev/pci/if_iwm.c

258

int iwm_read_mem(struct iwm_softc *, uint32_t, void *, int);

sys/dev/pci/if_iwm.c

259

int iwm_write_mem(struct iwm_softc *, uint32_t, const void *, int);

sys/dev/pci/if_iwm.c

260

int iwm_write_mem32(struct iwm_softc *, uint32_t, uint32_t);

sys/dev/pci/if_iwm.c

261

int iwm_poll_bit(struct iwm_softc *, int, uint32_t, uint32_t, int);

sys/dev/pci/if_iwm.c

265

int iwm_set_bits_mask_prph(struct iwm_softc *, uint32_t, uint32_t,

sys/dev/pci/if_iwm.c

266

uint32_t);

sys/dev/pci/if_iwm.c

267

int iwm_set_bits_prph(struct iwm_softc *, uint32_t, uint32_t);

sys/dev/pci/if_iwm.c

268

int iwm_clear_bits_prph(struct iwm_softc *, uint32_t, uint32_t);

sys/dev/pci/if_iwm.c

2686

iwm_phy_db_get_section_data(struct iwm_softc *sc, uint32_t type, uint8_t **data,

sys/dev/pci/if_iwm.c

2809

uint32_t resp_len;

sys/dev/pci/if_iwm.c

2842

uint32_t duration, uint32_t max_delay)

sys/dev/pci/if_iwm.c

316

int iwm_phy_db_get_section_data(struct iwm_softc *, uint32_t, uint8_t **,

sys/dev/pci/if_iwm.c

322

void iwm_protect_session(struct iwm_softc *, struct iwm_node *, uint32_t,

sys/dev/pci/if_iwm.c

323

uint32_t);

sys/dev/pci/if_iwm.c

3316

uint32_t status;

sys/dev/pci/if_iwm.c

3555

uint32_t status;

sys/dev/pci/if_iwm.c

369

int iwm_firmware_load_sect(struct iwm_softc *, uint32_t, const uint8_t *,

sys/dev/pci/if_iwm.c

370

uint32_t);

sys/dev/pci/if_iwm.c

371

int iwm_firmware_load_chunk(struct iwm_softc *, uint32_t, const uint8_t *,

sys/dev/pci/if_iwm.c

372

uint32_t);

sys/dev/pci/if_iwm.c

3849

uint32_t mac_addr0, mac_addr1;

sys/dev/pci/if_iwm.c

3882

uint32_t sku;

sys/dev/pci/if_iwm.c

3896

uint32_t radio_cfg =

sys/dev/pci/if_iwm.c

3897

le32_to_cpup((uint32_t *)(phy_sku + IWM_RADIO_CFG_8000));

sys/dev/pci/if_iwm.c

3905

sku = le32_to_cpup((uint32_t *)(phy_sku + IWM_SKU_8000));

sys/dev/pci/if_iwm.c

391

int iwm_rx_hwdecrypt(struct iwm_softc *, struct mbuf *, uint32_t,

sys/dev/pci/if_iwm.c

395

void iwm_rx_frame(struct iwm_softc *, struct mbuf *, int, uint32_t, int, int,

sys/dev/pci/if_iwm.c

396

uint32_t, struct ieee80211_rxinfo *, struct mbuf_list *);

sys/dev/pci/if_iwm.c

4071

iwm_firmware_load_sect(struct iwm_softc *sc, uint32_t dst_addr,

sys/dev/pci/if_iwm.c

4072

const uint8_t *section, uint32_t byte_cnt)

sys/dev/pci/if_iwm.c

4075

uint32_t chunk_sz, offset;

sys/dev/pci/if_iwm.c

4080

uint32_t addr, len;

sys/dev/pci/if_iwm.c

4096

iwm_firmware_load_chunk(struct iwm_softc *sc, uint32_t dst_addr,

sys/dev/pci/if_iwm.c

4097

const uint8_t *chunk, uint32_t byte_cnt)

sys/dev/pci/if_iwm.c

413

int iwm_binding_cmd(struct iwm_softc *, struct iwm_node *, uint32_t);

sys/dev/pci/if_iwm.c

416

uint8_t, uint32_t, uint32_t, uint8_t, uint8_t);

sys/dev/pci/if_iwm.c

4169

uint32_t dlen;

sys/dev/pci/if_iwm.c

4170

uint32_t offset;

sys/dev/pci/if_iwm.c

418

struct iwm_phy_context_cmd *, uint32_t, uint32_t);

sys/dev/pci/if_iwm.c

4201

uint32_t val, last_read_idx = 0;

sys/dev/pci/if_iwm.c

4203

uint32_t dlen;

sys/dev/pci/if_iwm.c

4204

uint32_t offset;

sys/dev/pci/if_iwm.c

422

uint8_t, uint32_t, uint32_t, uint8_t, uint8_t);

sys/dev/pci/if_iwm.c

424

int iwm_send_cmd_pdu(struct iwm_softc *, uint32_t, uint32_t, uint16_t,

sys/dev/pci/if_iwm.c

427

uint32_t *);

sys/dev/pci/if_iwm.c

428

int iwm_send_cmd_pdu_status(struct iwm_softc *, uint32_t, uint16_t,

sys/dev/pci/if_iwm.c

429

const void *, uint32_t *);

sys/dev/pci/if_iwm.c

4394

uint32_t cmd_id;

sys/dev/pci/if_iwm.c

4600

((uint32_t *)ring->desc)[idx] =

sys/dev/pci/if_iwm.c

4603

idx * sizeof(uint32_t), sizeof(uint32_t),

sys/dev/pci/if_iwm.c

4619

uint32_t val;

sys/dev/pci/if_iwm.c

462

uint32_t iwm_scan_rate_n_flags(struct iwm_softc *, int, int);

sys/dev/pci/if_iwm.c

4737

iwm_rx_hwdecrypt(struct iwm_softc *sc, struct mbuf *m, uint32_t rx_pkt_status,

sys/dev/pci/if_iwm.c

474

struct iwm_mac_ctx_cmd *, uint32_t);

sys/dev/pci/if_iwm.c

477

int iwm_mac_ctxt_cmd(struct iwm_softc *, struct iwm_node *, uint32_t, int);

sys/dev/pci/if_iwm.c

4792

uint32_t rx_pkt_status, int is_shortpre, int rate_n_flags,

sys/dev/pci/if_iwm.c

4793

uint32_t device_timestamp, struct ieee80211_rxinfo *rxi,

sys/dev/pci/if_iwm.c

4882

uint32_t len;

sys/dev/pci/if_iwm.c

4883

uint32_t rx_pkt_status;

sys/dev/pci/if_iwm.c

490

struct ieee80211_channel *, uint8_t, uint8_t, uint32_t, uint8_t,

sys/dev/pci/if_iwm.c

4916

rx_pkt_status = le32toh(*(uint32_t *)(pktdata + sizeof(*rx_res) + len));

sys/dev/pci/if_iwm.c

5046

uint32_t rx_pkt_status, rate_n_flags, device_timestamp;

sys/dev/pci/if_iwm.c

5090

struct iwm_reorder_buffer *buffer, uint32_t reorder_data, uint32_t gp2)

sys/dev/pci/if_iwm.c

5144

uint32_t device_timestamp, struct ieee80211_rxinfo *rxi,

sys/dev/pci/if_iwm.c

5152

uint32_t reorder_data = le32toh(desc->reorder_data);

sys/dev/pci/if_iwm.c

520

void iwm_tt_tx_backoff(struct iwm_softc *, uint32_t);

sys/dev/pci/if_iwm.c

530

const char *iwm_desc_lookup(uint32_t);

sys/dev/pci/if_iwm.c

5344

uint32_t len, hdrlen, rate_n_flags, device_timestamp;

sys/dev/pci/if_iwm.c

544

int, struct iwm_reorder_buffer *, uint32_t, uint32_t);

sys/dev/pci/if_iwm.c

546

struct iwm_rx_mpdu_desc *, int, int, uint32_t,

sys/dev/pci/if_iwm.c

5624

uint32_t initial_rate = le32toh(tx_resp->initial_rate);

sys/dev/pci/if_iwm.c

5715

struct iwm_node *in, struct iwm_tx_ring *txq, uint32_t initial_rate,

sys/dev/pci/if_iwm.c

5846

uint32_t ssn;

sys/dev/pci/if_iwm.c

5847

uint32_t len = iwm_rx_packet_len(pkt);

sys/dev/pci/if_iwm.c

6028

uint32_t missed;

sys/dev/pci/if_iwm.c

6056

iwm_binding_cmd(struct iwm_softc *sc, struct iwm_node *in, uint32_t action)

sys/dev/pci/if_iwm.c

6060

uint32_t mac_id = IWM_FW_CMD_ID_AND_COLOR(in->in_id, in->in_color);

sys/dev/pci/if_iwm.c

6062

uint32_t status;

sys/dev/pci/if_iwm.c

6105

struct iwm_phy_context_cmd *cmd, uint32_t action, uint32_t apply_time)

sys/dev/pci/if_iwm.c

6194

uint8_t chains_static, uint8_t chains_dynamic, uint32_t action,

sys/dev/pci/if_iwm.c

6195

uint32_t apply_time, uint8_t sco, uint8_t vht_chan_width)

sys/dev/pci/if_iwm.c

622

if (dlen < sizeof(uint32_t))

sys/dev/pci/if_iwm.c

6246

uint8_t chains_static, uint8_t chains_dynamic, uint32_t action,

sys/dev/pci/if_iwm.c

6247

uint32_t apply_time, uint8_t sco, uint8_t vht_chan_width)

sys/dev/pci/if_iwm.c

6280

uint32_t addr_lo;

sys/dev/pci/if_iwm.c

632

memcpy(&fwone->fws_devoff, data, sizeof(uint32_t));

sys/dev/pci/if_iwm.c

635

fwone->fws_data = data + sizeof(uint32_t);

sys/dev/pci/if_iwm.c

636

fwone->fws_len = dlen - sizeof(uint32_t);

sys/dev/pci/if_iwm.c

6385

addr_lo = htole32((uint32_t)paddr);

sys/dev/pci/if_iwm.c

6386

memcpy(&desc->tbs[0].lo, &addr_lo, sizeof(uint32_t));

sys/dev/pci/if_iwm.c

6447

iwm_send_cmd_pdu(struct iwm_softc *sc, uint32_t id, uint32_t flags,

sys/dev/pci/if_iwm.c

6462

uint32_t *status)

sys/dev/pci/if_iwm.c

649

uint32_t ucode_type;

sys/dev/pci/if_iwm.c

6493

iwm_send_cmd_pdu_status(struct iwm_softc *sc, uint32_t id, uint16_t len,

sys/dev/pci/if_iwm.c

6494

const void *data, uint32_t *status)

sys/dev/pci/if_iwm.c

657

uint32_t ucode_type = le32toh(def_calib->ucode_type);

sys/dev/pci/if_iwm.c

6715

uint32_t flags;

sys/dev/pci/if_iwm.c

682

uint32_t major, uint32_t minor, uint32_t api)

sys/dev/pci/if_iwm.c

700

uint32_t tlv_type;

sys/dev/pci/if_iwm.c

702

uint32_t usniffer_img;

sys/dev/pci/if_iwm.c

703

uint32_t paging_mem_size;

sys/dev/pci/if_iwm.c

7225

uint32_t status, aggsize;

sys/dev/pci/if_iwm.c

7226

const uint32_t max_aggsize = (IWM_STA_FLG_MAX_AGG_SIZE_64K >>

sys/dev/pci/if_iwm.c

732

if (*(uint32_t *)fw->fw_rawdata != 0

sys/dev/pci/if_iwm.c

7375

uint32_t status;

sys/dev/pci/if_iwm.c

7416

uint32_t status;

sys/dev/pci/if_iwm.c

7523

uint32_t

sys/dev/pci/if_iwm.c

7526

uint32_t tx_ant;

sys/dev/pci/if_iwm.c

769

if (tlv_len < sizeof(uint32_t)) {

sys/dev/pci/if_iwm.c

774

= le32toh(*(uint32_t *)tlv_data);

sys/dev/pci/if_iwm.c

7848

static const uint32_t rates = (IWM_SCAN_CONFIG_RATE_1M |

sys/dev/pci/if_iwm.c

789

if (tlv_len < sizeof(uint32_t)) {

sys/dev/pci/if_iwm.c

8034

const uint32_t timeout = htole32(120);

sys/dev/pci/if_iwm.c

804

sc->sc_capaflags = le32toh(*(uint32_t *)tlv_data);

sys/dev/pci/if_iwm.c

812

uint32_t num_cpu;

sys/dev/pci/if_iwm.c

813

if (tlv_len != sizeof(uint32_t)) {

sys/dev/pci/if_iwm.c

817

num_cpu = le32toh(*(uint32_t *)tlv_data);

sys/dev/pci/if_iwm.c

8258

struct iwm_mac_ctx_cmd *cmd, uint32_t action)

sys/dev/pci/if_iwm.c

8348

uint32_t dtim_off;

sys/dev/pci/if_iwm.c

8368

iwm_mac_ctxt_cmd(struct iwm_softc *sc, struct iwm_node *in, uint32_t action,

sys/dev/pci/if_iwm.c

852

if (tlv_len != sizeof(uint32_t)) {

sys/dev/pci/if_iwm.c

856

sc->sc_fw_phy_config = le32toh(*(uint32_t *)tlv_data);

sys/dev/pci/if_iwm.c

8702

uint8_t chains_dynamic, uint32_t apply_time, uint8_t sco,

sys/dev/pci/if_iwm.c

8751

uint32_t duration;

sys/dev/pci/if_iwm.c

931

if (tlv_len != sizeof(uint32_t)) {

sys/dev/pci/if_iwm.c

935

paging_mem_size = le32toh(*(const uint32_t *)tlv_data);

sys/dev/pci/if_iwm.c

962

if (tlv_len != sizeof(uint32_t)) {

sys/dev/pci/if_iwm.c

9649

static const uint32_t

sys/dev/pci/if_iwm.c

967

le32toh(*(uint32_t *)tlv_data);

sys/dev/pci/if_iwm.c

9677

static const uint32_t

sys/dev/pci/if_iwm.c

975

if (tlv_len != sizeof(uint32_t) * 3) {

sys/dev/pci/if_iwm.c

9793

uint32_t cmd_id, flags = 0;

sys/dev/pci/if_iwm.c

981

le32toh(((uint32_t *)tlv_data)[0]),

sys/dev/pci/if_iwm.c

982

le32toh(((uint32_t *)tlv_data)[1]),

sys/dev/pci/if_iwm.c

983

le32toh(((uint32_t *)tlv_data)[2]));

sys/dev/pci/if_iwm.c

9930

iwm_tt_tx_backoff(struct iwm_softc *sc, uint32_t backoff)

sys/dev/pci/if_iwm.c

9934

.len = { sizeof(uint32_t), },

sys/dev/pci/if_iwm.c

9960

uint32_t offset = 0;

sys/dev/pci/if_iwmreg.h

1003

uint32_t cipher;

sys/dev/pci/if_iwmreg.h

1027

uint32_t ver; /* major/minor/API/serial */

sys/dev/pci/if_iwmreg.h

1030

uint32_t inst_size; /* bytes of runtime code */

sys/dev/pci/if_iwmreg.h

1031

uint32_t data_size; /* bytes of runtime data */

sys/dev/pci/if_iwmreg.h

1032

uint32_t init_size; /* bytes of init code */

sys/dev/pci/if_iwmreg.h

1033

uint32_t init_data_size; /* bytes of init data */

sys/dev/pci/if_iwmreg.h

1034

uint32_t boot_size; /* bytes of bootstrap code */

sys/dev/pci/if_iwmreg.h

1038

uint32_t build; /* build number */

sys/dev/pci/if_iwmreg.h

1039

uint32_t inst_size; /* bytes of runtime code */

sys/dev/pci/if_iwmreg.h

1040

uint32_t data_size; /* bytes of runtime data */

sys/dev/pci/if_iwmreg.h

1041

uint32_t init_size; /* bytes of init code */

sys/dev/pci/if_iwmreg.h

1042

uint32_t init_data_size; /* bytes of init data */

sys/dev/pci/if_iwmreg.h

1043

uint32_t boot_size; /* bytes of bootstrap code */

sys/dev/pci/if_iwmreg.h

1116

uint32_t type; /* see above */

sys/dev/pci/if_iwmreg.h

1117

uint32_t length; /* not including type/length fields */

sys/dev/pci/if_iwmreg.h

1122

uint32_t api_index;

sys/dev/pci/if_iwmreg.h

1123

uint32_t api_flags;

sys/dev/pci/if_iwmreg.h

1127

uint32_t api_index;

sys/dev/pci/if_iwmreg.h

1128

uint32_t api_capa;

sys/dev/pci/if_iwmreg.h

1140

uint32_t zero;

sys/dev/pci/if_iwmreg.h

1141

uint32_t magic;

sys/dev/pci/if_iwmreg.h

1143

uint32_t ver; /* major/minor/API/serial */

sys/dev/pci/if_iwmreg.h

1144

uint32_t build;

sys/dev/pci/if_iwmreg.h

1779

uint32_t unused;

sys/dev/pci/if_iwmreg.h

1792

return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF;

sys/dev/pci/if_iwmreg.h

1805

uint32_t lo;

sys/dev/pci/if_iwmreg.h

1841

uint32_t __pad;

sys/dev/pci/if_iwmreg.h

2103

uint32_t cmd_queue;

sys/dev/pci/if_iwmreg.h

2111

uint32_t status;

sys/dev/pci/if_iwmreg.h

2119

uint32_t valid;

sys/dev/pci/if_iwmreg.h

2144

uint32_t flow_trigger;

sys/dev/pci/if_iwmreg.h

2145

uint32_t event_trigger;

sys/dev/pci/if_iwmreg.h

2175

uint32_t phy_cfg;

sys/dev/pci/if_iwmreg.h

2211

uint32_t num_temps;

sys/dev/pci/if_iwmreg.h

2237

uint32_t space;

sys/dev/pci/if_iwmreg.h

2427

uint32_t flags;

sys/dev/pci/if_iwmreg.h

2428

uint32_t block_size;

sys/dev/pci/if_iwmreg.h

2429

uint32_t block_num;

sys/dev/pci/if_iwmreg.h

2430

uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS];

sys/dev/pci/if_iwmreg.h

2491

uint32_t timestamp;

sys/dev/pci/if_iwmreg.h

2492

uint32_t error_event_table_ptr; /* SRAM address for error log */

sys/dev/pci/if_iwmreg.h

2493

uint32_t log_event_table_ptr; /* SRAM address for event log */

sys/dev/pci/if_iwmreg.h

2494

uint32_t cpu_register_ptr;

sys/dev/pci/if_iwmreg.h

2495

uint32_t dbgm_config_ptr;

sys/dev/pci/if_iwmreg.h

2496

uint32_t alive_counter_ptr;

sys/dev/pci/if_iwmreg.h

2497

uint32_t scd_base_ptr; /* SRAM address for SCD */

sys/dev/pci/if_iwmreg.h

2513

uint32_t timestamp;

sys/dev/pci/if_iwmreg.h

2514

uint32_t error_event_table_ptr; /* SRAM address for error log */

sys/dev/pci/if_iwmreg.h

2515

uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */

sys/dev/pci/if_iwmreg.h

2516

uint32_t cpu_register_ptr;

sys/dev/pci/if_iwmreg.h

2517

uint32_t dbgm_config_ptr;

sys/dev/pci/if_iwmreg.h

2518

uint32_t alive_counter_ptr;

sys/dev/pci/if_iwmreg.h

2519

uint32_t scd_base_ptr; /* SRAM address for SCD */

sys/dev/pci/if_iwmreg.h

2520

uint32_t st_fwrd_addr; /* pointer to Store and forward */

sys/dev/pci/if_iwmreg.h

2521

uint32_t st_fwrd_size;

sys/dev/pci/if_iwmreg.h

2525

uint32_t error_info_addr; /* SRAM address for UMAC error log */

sys/dev/pci/if_iwmreg.h

2526

uint32_t dbg_print_buff_addr;

sys/dev/pci/if_iwmreg.h

2532

uint32_t ucode_minor;

sys/dev/pci/if_iwmreg.h

2533

uint32_t ucode_major;

sys/dev/pci/if_iwmreg.h

2538

uint32_t timestamp;

sys/dev/pci/if_iwmreg.h

2539

uint32_t error_event_table_ptr; /* SRAM address for error log */

sys/dev/pci/if_iwmreg.h

2540

uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */

sys/dev/pci/if_iwmreg.h

2541

uint32_t cpu_register_ptr;

sys/dev/pci/if_iwmreg.h

2542

uint32_t dbgm_config_ptr;

sys/dev/pci/if_iwmreg.h

2543

uint32_t alive_counter_ptr;

sys/dev/pci/if_iwmreg.h

2544

uint32_t scd_base_ptr; /* SRAM address for SCD */

sys/dev/pci/if_iwmreg.h

2545

uint32_t st_fwrd_addr; /* pointer to Store and forward */

sys/dev/pci/if_iwmreg.h

2546

uint32_t st_fwrd_size;

sys/dev/pci/if_iwmreg.h

2547

uint32_t umac_minor; /* UMAC version: minor */

sys/dev/pci/if_iwmreg.h

2548

uint32_t umac_major; /* UMAC version: major */

sys/dev/pci/if_iwmreg.h

2549

uint32_t error_info_addr; /* SRAM address for UMAC error log */

sys/dev/pci/if_iwmreg.h

2550

uint32_t dbg_print_buff_addr;

sys/dev/pci/if_iwmreg.h

2571

uint32_t flags;

sys/dev/pci/if_iwmreg.h

2572

uint32_t latency;

sys/dev/pci/if_iwmreg.h

2603

uint32_t error_type;

sys/dev/pci/if_iwmreg.h

2607

uint32_t error_service;

sys/dev/pci/if_iwmreg.h

2886

uint32_t id_and_color;

sys/dev/pci/if_iwmreg.h

2887

uint32_t action;

sys/dev/pci/if_iwmreg.h

2888

uint32_t id;

sys/dev/pci/if_iwmreg.h

2890

uint32_t apply_time;

sys/dev/pci/if_iwmreg.h

2891

uint32_t max_delay;

sys/dev/pci/if_iwmreg.h

2892

uint32_t depends_on;

sys/dev/pci/if_iwmreg.h

2893

uint32_t interval;

sys/dev/pci/if_iwmreg.h

2894

uint32_t duration;

sys/dev/pci/if_iwmreg.h

2908

uint32_t status;

sys/dev/pci/if_iwmreg.h

2909

uint32_t id;

sys/dev/pci/if_iwmreg.h

2910

uint32_t unique_id;

sys/dev/pci/if_iwmreg.h

2911

uint32_t id_and_color;

sys/dev/pci/if_iwmreg.h

2925

uint32_t timestamp;

sys/dev/pci/if_iwmreg.h

2926

uint32_t session_id;

sys/dev/pci/if_iwmreg.h

2927

uint32_t unique_id;

sys/dev/pci/if_iwmreg.h

2928

uint32_t id_and_color;

sys/dev/pci/if_iwmreg.h

2929

uint32_t action;

sys/dev/pci/if_iwmreg.h

2930

uint32_t status;

sys/dev/pci/if_iwmreg.h

2947

uint32_t id_and_color;

sys/dev/pci/if_iwmreg.h

2948

uint32_t action;

sys/dev/pci/if_iwmreg.h

2950

uint32_t macs[IWM_MAX_MACS_IN_BINDING];

sys/dev/pci/if_iwmreg.h

2951

uint32_t phy;

sys/dev/pci/if_iwmreg.h

2965

uint32_t id_and_color;

sys/dev/pci/if_iwmreg.h

2966

uint32_t action;

sys/dev/pci/if_iwmreg.h

2968

uint32_t macs[IWM_MAX_MACS_IN_BINDING];

sys/dev/pci/if_iwmreg.h

2969

uint32_t phy;

sys/dev/pci/if_iwmreg.h

2970

uint32_t lmac_id;

sys/dev/pci/if_iwmreg.h

2987

uint32_t id_and_color;

sys/dev/pci/if_iwmreg.h

2988

uint32_t quota;

sys/dev/pci/if_iwmreg.h

2989

uint32_t max_duration;

sys/dev/pci/if_iwmreg.h

3014

uint32_t id_and_color;

sys/dev/pci/if_iwmreg.h

3015

uint32_t quota;

sys/dev/pci/if_iwmreg.h

3016

uint32_t max_duration;

sys/dev/pci/if_iwmreg.h

3017

uint32_t low_latency;

sys/dev/pci/if_iwmreg.h

3089

uint32_t channel;

sys/dev/pci/if_iwmreg.h

3146

uint32_t id_and_color;

sys/dev/pci/if_iwmreg.h

3147

uint32_t action;

sys/dev/pci/if_iwmreg.h

3149

uint32_t apply_time;

sys/dev/pci/if_iwmreg.h

3150

uint32_t tx_param_color;

sys/dev/pci/if_iwmreg.h

3152

uint32_t txchain_info;

sys/dev/pci/if_iwmreg.h

3153

uint32_t rxchain_info;

sys/dev/pci/if_iwmreg.h

3154

uint32_t acquisition_data;

sys/dev/pci/if_iwmreg.h

3155

uint32_t dsp_cfg_flags;

sys/dev/pci/if_iwmreg.h

3160

uint32_t id_and_color;

sys/dev/pci/if_iwmreg.h

3161

uint32_t action;

sys/dev/pci/if_iwmreg.h

3163

uint32_t apply_time;

sys/dev/pci/if_iwmreg.h

3164

uint32_t tx_param_color;

sys/dev/pci/if_iwmreg.h

3166

uint32_t txchain_info;

sys/dev/pci/if_iwmreg.h

3167

uint32_t rxchain_info;

sys/dev/pci/if_iwmreg.h

3168

uint32_t acquisition_data;

sys/dev/pci/if_iwmreg.h

3169

uint32_t dsp_cfg_flags;

sys/dev/pci/if_iwmreg.h

3225

uint32_t system_timestamp;

sys/dev/pci/if_iwmreg.h

3227

uint32_t beacon_time_stamp;

sys/dev/pci/if_iwmreg.h

3231

uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT];

sys/dev/pci/if_iwmreg.h

3232

uint32_t rate_n_flags;

sys/dev/pci/if_iwmreg.h

3233

uint32_t byte_count;

sys/dev/pci/if_iwmreg.h

3345

uint32_t rss_hash;

sys/dev/pci/if_iwmreg.h

3346

uint32_t phy_data2;

sys/dev/pci/if_iwmreg.h

3349

uint32_t filter_match;

sys/dev/pci/if_iwmreg.h

3350

uint32_t phy_data3;

sys/dev/pci/if_iwmreg.h

3352

uint32_t rate_n_flags;

sys/dev/pci/if_iwmreg.h

3357

uint32_t gp2_on_air_rise;

sys/dev/pci/if_iwmreg.h

3361

uint32_t phy_data0;

sys/dev/pci/if_iwmreg.h

3362

uint32_t phy_data1;

sys/dev/pci/if_iwmreg.h

3391

uint32_t reorder_data;

sys/dev/pci/if_iwmreg.h

3403

uint32_t radio_flavor;

sys/dev/pci/if_iwmreg.h

3404

uint32_t radio_step;

sys/dev/pci/if_iwmreg.h

3405

uint32_t radio_dash;

sys/dev/pci/if_iwmreg.h

3422

uint32_t flags;

sys/dev/pci/if_iwmreg.h

3436

uint32_t mac_id;

sys/dev/pci/if_iwmreg.h

3437

uint32_t consec_missed_beacons_since_last_rx;

sys/dev/pci/if_iwmreg.h

3438

uint32_t consec_missed_beacons;

sys/dev/pci/if_iwmreg.h

3439

uint32_t num_expected_beacons;

sys/dev/pci/if_iwmreg.h

3440

uint32_t num_recvd_beacons;

sys/dev/pci/if_iwmreg.h

3452

uint32_t installed_ver;

sys/dev/pci/if_iwmreg.h

3453

uint32_t external_ver;

sys/dev/pci/if_iwmreg.h

3454

uint32_t status;

sys/dev/pci/if_iwmreg.h

3455

uint32_t duration;

sys/dev/pci/if_iwmreg.h

3498

uint32_t burst_check;

sys/dev/pci/if_iwmreg.h

3499

uint32_t burst_count;

sys/dev/pci/if_iwmreg.h

3500

uint32_t wait_for_silence_timeout_cnt;

sys/dev/pci/if_iwmreg.h

3501

uint32_t reserved[3];

sys/dev/pci/if_iwmreg.h

3505

uint32_t tx_on_a;

sys/dev/pci/if_iwmreg.h

3506

uint32_t tx_on_b;

sys/dev/pci/if_iwmreg.h

3507

uint32_t exec_time;

sys/dev/pci/if_iwmreg.h

3508

uint32_t probe_time;

sys/dev/pci/if_iwmreg.h

3509

uint32_t rssi_ant;

sys/dev/pci/if_iwmreg.h

3510

uint32_t reserved2;

sys/dev/pci/if_iwmreg.h

3514

uint32_t temperature; /* radio temperature */

sys/dev/pci/if_iwmreg.h

3515

uint32_t temperature_m; /* radio voltage */

sys/dev/pci/if_iwmreg.h

3517

uint32_t sleep_time;

sys/dev/pci/if_iwmreg.h

3518

uint32_t slots_out;

sys/dev/pci/if_iwmreg.h

3519

uint32_t slots_idle;

sys/dev/pci/if_iwmreg.h

3520

uint32_t ttl_timestamp;

sys/dev/pci/if_iwmreg.h

3522

uint32_t rx_enable_counter;

sys/dev/pci/if_iwmreg.h

3528

uint32_t num_of_sos_states;

sys/dev/pci/if_iwmreg.h

3532

uint32_t bogus_cts; /* CTS received when not expecting CTS */

sys/dev/pci/if_iwmreg.h

3533

uint32_t bogus_ack; /* ACK received when not expecting ACK */

sys/dev/pci/if_iwmreg.h

3534

uint32_t non_bssid_frames; /* number of frames with BSSID that

sys/dev/pci/if_iwmreg.h

3536

uint32_t filtered_frames; /* count frames that were dumped in the

sys/dev/pci/if_iwmreg.h

3538

uint32_t non_channel_beacons; /* beacons with our bss id but not on

sys/dev/pci/if_iwmreg.h

3540

uint32_t channel_beacons; /* beacons with our bss id and in our

sys/dev/pci/if_iwmreg.h

3542

uint32_t num_missed_bcon; /* number of missed beacons */

sys/dev/pci/if_iwmreg.h

3543

uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the

sys/dev/pci/if_iwmreg.h

3545

uint32_t ina_detection_search_time;/* total time (in 0.8us) searched

sys/dev/pci/if_iwmreg.h

3547

uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */

sys/dev/pci/if_iwmreg.h

3548

uint32_t interference_data_flag; /* flag for interference data

sys/dev/pci/if_iwmreg.h

3551

uint32_t channel_load; /* counts RX Enable time in uSec */

sys/dev/pci/if_iwmreg.h

3552

uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM

sys/dev/pci/if_iwmreg.h

3554

uint32_t beacon_rssi_a;

sys/dev/pci/if_iwmreg.h

3555

uint32_t beacon_rssi_b;

sys/dev/pci/if_iwmreg.h

3556

uint32_t beacon_rssi_c;

sys/dev/pci/if_iwmreg.h

3557

uint32_t beacon_energy_a;

sys/dev/pci/if_iwmreg.h

3558

uint32_t beacon_energy_b;

sys/dev/pci/if_iwmreg.h

3559

uint32_t beacon_energy_c;

sys/dev/pci/if_iwmreg.h

3560

uint32_t num_bt_kills;

sys/dev/pci/if_iwmreg.h

3561

uint32_t mac_id;

sys/dev/pci/if_iwmreg.h

3562

uint32_t directed_data_mpdu;

sys/dev/pci/if_iwmreg.h

3566

uint32_t ina_cnt;

sys/dev/pci/if_iwmreg.h

3567

uint32_t fina_cnt;

sys/dev/pci/if_iwmreg.h

3568

uint32_t plcp_err;

sys/dev/pci/if_iwmreg.h

3569

uint32_t crc32_err;

sys/dev/pci/if_iwmreg.h

3570

uint32_t overrun_err;

sys/dev/pci/if_iwmreg.h

3571

uint32_t early_overrun_err;

sys/dev/pci/if_iwmreg.h

3572

uint32_t crc32_good;

sys/dev/pci/if_iwmreg.h

3573

uint32_t false_alarm_cnt;

sys/dev/pci/if_iwmreg.h

3574

uint32_t fina_sync_err_cnt;

sys/dev/pci/if_iwmreg.h

3575

uint32_t sfd_timeout;

sys/dev/pci/if_iwmreg.h

3576

uint32_t fina_timeout;

sys/dev/pci/if_iwmreg.h

3577

uint32_t unresponded_rts;

sys/dev/pci/if_iwmreg.h

3578

uint32_t rxe_frame_limit_overrun;

sys/dev/pci/if_iwmreg.h

3579

uint32_t sent_ack_cnt;

sys/dev/pci/if_iwmreg.h

3580

uint32_t sent_cts_cnt;

sys/dev/pci/if_iwmreg.h

3581

uint32_t sent_ba_rsp_cnt;

sys/dev/pci/if_iwmreg.h

3582

uint32_t dsp_self_kill;

sys/dev/pci/if_iwmreg.h

3583

uint32_t mh_format_err;

sys/dev/pci/if_iwmreg.h

3584

uint32_t re_acq_main_rssi_sum;

sys/dev/pci/if_iwmreg.h

3585

uint32_t reserved;

sys/dev/pci/if_iwmreg.h

3589

uint32_t plcp_err;

sys/dev/pci/if_iwmreg.h

3590

uint32_t overrun_err;

sys/dev/pci/if_iwmreg.h

3591

uint32_t early_overrun_err;

sys/dev/pci/if_iwmreg.h

3592

uint32_t crc32_good;

sys/dev/pci/if_iwmreg.h

3593

uint32_t crc32_err;

sys/dev/pci/if_iwmreg.h

3594

uint32_t mh_format_err;

sys/dev/pci/if_iwmreg.h

3595

uint32_t agg_crc32_good;

sys/dev/pci/if_iwmreg.h

3596

uint32_t agg_mpdu_cnt;

sys/dev/pci/if_iwmreg.h

3597

uint32_t agg_cnt;

sys/dev/pci/if_iwmreg.h

3598

uint32_t unsupport_mcs;

sys/dev/pci/if_iwmreg.h

3604

uint32_t ba_timeout;

sys/dev/pci/if_iwmreg.h

3605

uint32_t ba_reschedule_frames;

sys/dev/pci/if_iwmreg.h

3606

uint32_t scd_query_agg_frame_cnt;

sys/dev/pci/if_iwmreg.h

3607

uint32_t scd_query_no_agg;

sys/dev/pci/if_iwmreg.h

3608

uint32_t scd_query_agg;

sys/dev/pci/if_iwmreg.h

3609

uint32_t scd_query_mismatch;

sys/dev/pci/if_iwmreg.h

3610

uint32_t frame_not_ready;

sys/dev/pci/if_iwmreg.h

3611

uint32_t underrun;

sys/dev/pci/if_iwmreg.h

3612

uint32_t bt_prio_kill;

sys/dev/pci/if_iwmreg.h

3613

uint32_t rx_ba_rsp_cnt;

sys/dev/pci/if_iwmreg.h

3616

uint32_t reserved2;

sys/dev/pci/if_iwmreg.h

3620

uint32_t ext_cca_narrow_ch20[1];

sys/dev/pci/if_iwmreg.h

3621

uint32_t ext_cca_narrow_ch40[2];

sys/dev/pci/if_iwmreg.h

3622

uint32_t ext_cca_narrow_ch80[3];

sys/dev/pci/if_iwmreg.h

3623

uint32_t ext_cca_narrow_ch160[4];

sys/dev/pci/if_iwmreg.h

3624

uint32_t last_tx_ch_width_indx;

sys/dev/pci/if_iwmreg.h

3625

uint32_t rx_detected_per_ch_width[4];

sys/dev/pci/if_iwmreg.h

3626

uint32_t success_per_ch_width[4];

sys/dev/pci/if_iwmreg.h

3627

uint32_t fail_per_ch_width[4];

sys/dev/pci/if_iwmreg.h

3631

uint32_t preamble_cnt;

sys/dev/pci/if_iwmreg.h

3632

uint32_t rx_detected_cnt;

sys/dev/pci/if_iwmreg.h

3633

uint32_t bt_prio_defer_cnt;

sys/dev/pci/if_iwmreg.h

3634

uint32_t bt_prio_kill_cnt;

sys/dev/pci/if_iwmreg.h

3635

uint32_t few_bytes_cnt;

sys/dev/pci/if_iwmreg.h

3636

uint32_t cts_timeout;

sys/dev/pci/if_iwmreg.h

3637

uint32_t ack_timeout;

sys/dev/pci/if_iwmreg.h

3638

uint32_t expected_ack_cnt;

sys/dev/pci/if_iwmreg.h

3639

uint32_t actual_ack_cnt;

sys/dev/pci/if_iwmreg.h

3640

uint32_t dump_msdu_cnt;

sys/dev/pci/if_iwmreg.h

3641

uint32_t burst_abort_next_frame_mismatch_cnt;

sys/dev/pci/if_iwmreg.h

3642

uint32_t burst_abort_missing_next_frame_cnt;

sys/dev/pci/if_iwmreg.h

3643

uint32_t cts_timeout_collision;

sys/dev/pci/if_iwmreg.h

3644

uint32_t ack_or_ba_timeout_collision;

sys/dev/pci/if_iwmreg.h

3651

uint32_t hi_priority_tx_req_cnt;

sys/dev/pci/if_iwmreg.h

3652

uint32_t hi_priority_tx_denied_cnt;

sys/dev/pci/if_iwmreg.h

3653

uint32_t lo_priority_tx_req_cnt;

sys/dev/pci/if_iwmreg.h

3654

uint32_t lo_priority_tx_denied_cnt;

sys/dev/pci/if_iwmreg.h

3655

uint32_t hi_priority_rx_req_cnt;

sys/dev/pci/if_iwmreg.h

3656

uint32_t hi_priority_rx_denied_cnt;

sys/dev/pci/if_iwmreg.h

3657

uint32_t lo_priority_rx_req_cnt;

sys/dev/pci/if_iwmreg.h

3658

uint32_t lo_priority_rx_denied_cnt;

sys/dev/pci/if_iwmreg.h

3663

uint32_t beacon_filtered;

sys/dev/pci/if_iwmreg.h

3664

uint32_t missed_beacons;

sys/dev/pci/if_iwmreg.h

3669

uint32_t beacon_filter_delta_time;

sys/dev/pci/if_iwmreg.h

3697

uint32_t flag;

sys/dev/pci/if_iwmreg.h

3768

uint32_t state;

sys/dev/pci/if_iwmreg.h

3769

uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER];

sys/dev/pci/if_iwmreg.h

3770

uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];

sys/dev/pci/if_iwmreg.h

3771

uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];

sys/dev/pci/if_iwmreg.h

3860

uint32_t beacon_time;

sys/dev/pci/if_iwmreg.h

3862

uint32_t bi;

sys/dev/pci/if_iwmreg.h

3863

uint32_t bi_reciprocal;

sys/dev/pci/if_iwmreg.h

3864

uint32_t dtim_interval;

sys/dev/pci/if_iwmreg.h

3865

uint32_t dtim_reciprocal;

sys/dev/pci/if_iwmreg.h

3866

uint32_t mcast_qid;

sys/dev/pci/if_iwmreg.h

3867

uint32_t beacon_template;

sys/dev/pci/if_iwmreg.h

3879

uint32_t beacon_time;

sys/dev/pci/if_iwmreg.h

3881

uint32_t bi;

sys/dev/pci/if_iwmreg.h

3882

uint32_t bi_reciprocal;

sys/dev/pci/if_iwmreg.h

3883

uint32_t beacon_template;

sys/dev/pci/if_iwmreg.h

3899

uint32_t is_assoc;

sys/dev/pci/if_iwmreg.h

3900

uint32_t dtim_time;

sys/dev/pci/if_iwmreg.h

3902

uint32_t bi;

sys/dev/pci/if_iwmreg.h

3903

uint32_t bi_reciprocal;

sys/dev/pci/if_iwmreg.h

3904

uint32_t dtim_interval;

sys/dev/pci/if_iwmreg.h

3905

uint32_t dtim_reciprocal;

sys/dev/pci/if_iwmreg.h

3906

uint32_t listen_interval;

sys/dev/pci/if_iwmreg.h

3907

uint32_t assoc_id;

sys/dev/pci/if_iwmreg.h

3908

uint32_t assoc_beacon_arrive_time;

sys/dev/pci/if_iwmreg.h

3920

uint32_t ctwin;

sys/dev/pci/if_iwmreg.h

3921

uint32_t opp_ps_enabled;

sys/dev/pci/if_iwmreg.h

3932

uint32_t ctwin;

sys/dev/pci/if_iwmreg.h

3940

uint32_t stats_interval;

sys/dev/pci/if_iwmreg.h

3954

uint32_t is_disc_extended;

sys/dev/pci/if_iwmreg.h

4039

uint32_t id_and_color;

sys/dev/pci/if_iwmreg.h

4040

uint32_t action;

sys/dev/pci/if_iwmreg.h

4042

uint32_t mac_type;

sys/dev/pci/if_iwmreg.h

4043

uint32_t tsf_id;

sys/dev/pci/if_iwmreg.h

4048

uint32_t cck_rates;

sys/dev/pci/if_iwmreg.h

4049

uint32_t ofdm_rates;

sys/dev/pci/if_iwmreg.h

4050

uint32_t protection_flags;

sys/dev/pci/if_iwmreg.h

4051

uint32_t cck_short_preamble;

sys/dev/pci/if_iwmreg.h

4052

uint32_t short_slot;

sys/dev/pci/if_iwmreg.h

4053

uint32_t filter_flags;

sys/dev/pci/if_iwmreg.h

4055

uint32_t qos_flags;

sys/dev/pci/if_iwmreg.h

4069

static inline uint32_t iwm_reciprocal(uint32_t v)

sys/dev/pci/if_iwmreg.h

4079

uint32_t get_set_flag;

sys/dev/pci/if_iwmreg.h

4080

uint32_t mac_id_n_color;

sys/dev/pci/if_iwmreg.h

4113

uint32_t flags;

sys/dev/pci/if_iwmreg.h

4114

uint32_t static_long;

sys/dev/pci/if_iwmreg.h

4115

uint32_t static_short;

sys/dev/pci/if_iwmreg.h

4129

uint32_t flags;

sys/dev/pci/if_iwmreg.h

4130

uint32_t static_long;

sys/dev/pci/if_iwmreg.h

4131

uint32_t static_short;

sys/dev/pci/if_iwmreg.h

4132

uint32_t ltr_cfg_values[IWM_LTR_VALID_STATES_NUM];

sys/dev/pci/if_iwmreg.h

4133

uint32_t ltr_short_idle_timeout;

sys/dev/pci/if_iwmreg.h

4239

uint32_t id_and_color;

sys/dev/pci/if_iwmreg.h

4244

uint32_t rx_data_timeout;

sys/dev/pci/if_iwmreg.h

4245

uint32_t tx_data_timeout;

sys/dev/pci/if_iwmreg.h

4246

uint32_t rx_data_timeout_uapsd;

sys/dev/pci/if_iwmreg.h

4247

uint32_t tx_data_timeout_uapsd;

sys/dev/pci/if_iwmreg.h

4275

uint32_t sta_id;

sys/dev/pci/if_iwmreg.h

4322

uint32_t bf_energy_delta;

sys/dev/pci/if_iwmreg.h

4323

uint32_t bf_roaming_energy_delta;

sys/dev/pci/if_iwmreg.h

4324

uint32_t bf_roaming_state;

sys/dev/pci/if_iwmreg.h

4325

uint32_t bf_temp_threshold;

sys/dev/pci/if_iwmreg.h

4326

uint32_t bf_temp_fast_filter;

sys/dev/pci/if_iwmreg.h

4327

uint32_t bf_temp_slow_filter;

sys/dev/pci/if_iwmreg.h

4328

uint32_t bf_enable_beacon_filter;

sys/dev/pci/if_iwmreg.h

4329

uint32_t bf_debug_flag;

sys/dev/pci/if_iwmreg.h

4330

uint32_t bf_escape_timer;

sys/dev/pci/if_iwmreg.h

4331

uint32_t ba_escape_timer;

sys/dev/pci/if_iwmreg.h

4332

uint32_t ba_enable_beacon_abort;

sys/dev/pci/if_iwmreg.h

4724

uint32_t reserved2;

sys/dev/pci/if_iwmreg.h

4725

uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM];

sys/dev/pci/if_iwmreg.h

4726

uint32_t bf_params;

sys/dev/pci/if_iwmreg.h

4916

uint32_t tx_flags;

sys/dev/pci/if_iwmreg.h

4922

uint32_t rate_n_flags;

sys/dev/pci/if_iwmreg.h

4928

uint32_t reserved3;

sys/dev/pci/if_iwmreg.h

4929

uint32_t life_time;

sys/dev/pci/if_iwmreg.h

4930

uint32_t dram_lsb_ptr;

sys/dev/pci/if_iwmreg.h

5109

uint32_t initial_rate;

sys/dev/pci/if_iwmreg.h

5119

uint32_t tfd_info;

sys/dev/pci/if_iwmreg.h

5174

uint32_t template_id;

sys/dev/pci/if_iwmreg.h

5175

uint32_t tim_idx;

sys/dev/pci/if_iwmreg.h

5176

uint32_t tim_size;

sys/dev/pci/if_iwmreg.h

5183

uint32_t ibss_mgr_status;

sys/dev/pci/if_iwmreg.h

5200

uint32_t queues_ctl;

sys/dev/pci/if_iwmreg.h

5212

uint32_t sta_id;

sys/dev/pci/if_iwmreg.h

5230

static inline uint32_t iwm_get_scd_ssn(struct iwm_tx_resp *tx_resp)

sys/dev/pci/if_iwmreg.h

5232

return le32_to_cpup((uint32_t *)&tx_resp->status +

sys/dev/pci/if_iwmreg.h

5332

uint32_t tx_flags;

sys/dev/pci/if_iwmreg.h

5333

uint32_t rate_n_flags;

sys/dev/pci/if_iwmreg.h

5350

uint32_t flags;

sys/dev/pci/if_iwmreg.h

5353

uint32_t iter_interval;

sys/dev/pci/if_iwmreg.h

5465

uint32_t reserved1;

sys/dev/pci/if_iwmreg.h

5473

uint32_t scan_flags;

sys/dev/pci/if_iwmreg.h

5474

uint32_t max_out_time;

sys/dev/pci/if_iwmreg.h

5475

uint32_t suspend_time;

sys/dev/pci/if_iwmreg.h

5477

uint32_t flags;

sys/dev/pci/if_iwmreg.h

5478

uint32_t filter_flags;

sys/dev/pci/if_iwmreg.h

5481

uint32_t scan_prio;

sys/dev/pci/if_iwmreg.h

5483

uint32_t iter_num;

sys/dev/pci/if_iwmreg.h

5484

uint32_t delay;

sys/dev/pci/if_iwmreg.h

5503

uint32_t time_after_last_iter;

sys/dev/pci/if_iwmreg.h

5504

uint32_t reserved;

sys/dev/pci/if_iwmreg.h

5521

uint32_t duration;

sys/dev/pci/if_iwmreg.h

5608

uint32_t tsf_low;

sys/dev/pci/if_iwmreg.h

5609

uint32_t tsf_high;

sys/dev/pci/if_iwmreg.h

5686

uint32_t flags;

sys/dev/pci/if_iwmreg.h

5687

uint32_t tx_chains;

sys/dev/pci/if_iwmreg.h

5688

uint32_t rx_chains;

sys/dev/pci/if_iwmreg.h

5689

uint32_t legacy_rates;

sys/dev/pci/if_iwmreg.h

5690

uint32_t out_of_channel_time;

sys/dev/pci/if_iwmreg.h

5691

uint32_t suspend_time;

sys/dev/pci/if_iwmreg.h

5755

uint32_t flags;

sys/dev/pci/if_iwmreg.h

5857

uint32_t flags;

sys/dev/pci/if_iwmreg.h

5858

uint32_t uid;

sys/dev/pci/if_iwmreg.h

5859

uint32_t ooc_priority;

sys/dev/pci/if_iwmreg.h

5870

uint32_t max_out_time;

sys/dev/pci/if_iwmreg.h

5871

uint32_t suspend_time;

sys/dev/pci/if_iwmreg.h

5872

uint32_t scan_priority;

sys/dev/pci/if_iwmreg.h

5881

uint32_t max_out_time[2];

sys/dev/pci/if_iwmreg.h

5882

uint32_t suspend_time[2];

sys/dev/pci/if_iwmreg.h

5883

uint32_t scan_priority;

sys/dev/pci/if_iwmreg.h

5895

uint32_t max_out_time[2];

sys/dev/pci/if_iwmreg.h

5896

uint32_t suspend_time[2];

sys/dev/pci/if_iwmreg.h

5897

uint32_t scan_priority;

sys/dev/pci/if_iwmreg.h

5908

uint32_t max_out_time[2];

sys/dev/pci/if_iwmreg.h

5909

uint32_t suspend_time[2];

sys/dev/pci/if_iwmreg.h

5910

uint32_t scan_priority;

sys/dev/pci/if_iwmreg.h

5923

uint32_t max_out_time[2];

sys/dev/pci/if_iwmreg.h

5924

uint32_t suspend_time[2];

sys/dev/pci/if_iwmreg.h

5925

uint32_t scan_priority;

sys/dev/pci/if_iwmreg.h

5945

uint32_t uid;

sys/dev/pci/if_iwmreg.h

5946

uint32_t flags;

sys/dev/pci/if_iwmreg.h

5960

uint32_t uid;

sys/dev/pci/if_iwmreg.h

5965

uint32_t time_from_last_iter;

sys/dev/pci/if_iwmreg.h

5966

uint32_t reserved;

sys/dev/pci/if_iwmreg.h

6002

uint32_t matched_profiles;

sys/dev/pci/if_iwmreg.h

6003

uint32_t last_scan_age;

sys/dev/pci/if_iwmreg.h

6004

uint32_t n_scans_done;

sys/dev/pci/if_iwmreg.h

6005

uint32_t gp2_d0u;

sys/dev/pci/if_iwmreg.h

6006

uint32_t gp2_invoked;

sys/dev/pci/if_iwmreg.h

6026

uint32_t uid;

sys/dev/pci/if_iwmreg.h

6031

uint32_t tsf_low;

sys/dev/pci/if_iwmreg.h

6032

uint32_t tsf_high;

sys/dev/pci/if_iwmreg.h

6273

uint32_t mac_id_n_color;

sys/dev/pci/if_iwmreg.h

6279

uint32_t station_flags;

sys/dev/pci/if_iwmreg.h

6280

uint32_t station_flags_msk;

sys/dev/pci/if_iwmreg.h

6288

uint32_t tfd_queue_msk;

sys/dev/pci/if_iwmreg.h

6342

uint32_t mac_id_n_color;

sys/dev/pci/if_iwmreg.h

6348

uint32_t station_flags;

sys/dev/pci/if_iwmreg.h

6349

uint32_t station_flags_msk;

sys/dev/pci/if_iwmreg.h

6358

uint32_t tfd_queue_msk;

sys/dev/pci/if_iwmreg.h

6460

uint32_t ctrl_flags;

sys/dev/pci/if_iwmreg.h

6464

uint32_t key_id;

sys/dev/pci/if_iwmreg.h

6465

uint32_t sta_id;

sys/dev/pci/if_iwmreg.h

6479

uint32_t mac_id_n_color;

sys/dev/pci/if_iwmreg.h

6512

uint32_t mode;

sys/dev/pci/if_iwmreg.h

6513

uint32_t enabled_modules;

sys/dev/pci/if_iwmreg.h

6553

uint32_t key;

sys/dev/pci/if_iwmreg.h

6554

uint32_t reserved2[5];

sys/dev/pci/if_iwmreg.h

6572

uint32_t status;

sys/dev/pci/if_iwmreg.h

6576

uint32_t n_channels;

sys/dev/pci/if_iwmreg.h

6577

uint32_t channels[0];

sys/dev/pci/if_iwmreg.h

6597

uint32_t status;

sys/dev/pci/if_iwmreg.h

6603

uint32_t n_channels;

sys/dev/pci/if_iwmreg.h

6604

uint32_t channels[0];

sys/dev/pci/if_iwmreg.h

6627

uint32_t status;

sys/dev/pci/if_iwmreg.h

6633

uint32_t n_channels;

sys/dev/pci/if_iwmreg.h

6634

uint32_t channels[0];

sys/dev/pci/if_iwmreg.h

6700

iwm_cmd_opcode(uint32_t cmdid)

sys/dev/pci/if_iwmreg.h

6706

iwm_cmd_groupid(uint32_t cmdid)

sys/dev/pci/if_iwmreg.h

6712

iwm_cmd_version(uint32_t cmdid)

sys/dev/pci/if_iwmreg.h

6717

static inline uint32_t

sys/dev/pci/if_iwmreg.h

6790

uint32_t len_n_flags;

sys/dev/pci/if_iwmreg.h

6803

static uint32_t

sys/dev/pci/if_iwmreg.h

6810

static uint32_t

sys/dev/pci/if_iwmreg.h

971

uint32_t flow_trigger;

sys/dev/pci/if_iwmreg.h

972

uint32_t event_trigger;

sys/dev/pci/if_iwmvar.h

169

uint32_t fws_len;

sys/dev/pci/if_iwmvar.h

170

uint32_t fws_devoff;

sys/dev/pci/if_iwmvar.h

174

uint32_t paging_mem_size;

sys/dev/pci/if_iwmvar.h

218

uint32_t _rx_page_order;

sys/dev/pci/if_iwmvar.h

221

uint32_t flags;

sys/dev/pci/if_iwmvar.h

224

uint32_t id;

sys/dev/pci/if_iwmvar.h

247

uint32_t fw_paging_size;

sys/dev/pci/if_iwmvar.h

317

uint32_t uc_error_event_table;

sys/dev/pci/if_iwmvar.h

318

uint32_t uc_umac_error_event_table;

sys/dev/pci/if_iwmvar.h

319

uint32_t uc_log_event_table;

sys/dev/pci/if_iwmvar.h

362

uint32_t ref;

sys/dev/pci/if_iwmvar.h

404

uint32_t consec_oldsn_ampdu_gp2;

sys/dev/pci/if_iwmvar.h

417

uint32_t rx_pkt_status;

sys/dev/pci/if_iwmvar.h

420

uint32_t rate_n_flags;

sys/dev/pci/if_iwmvar.h

421

uint32_t device_timestamp;

sys/dev/pci/if_iwmvar.h

469

uint32_t start_tidmask;

sys/dev/pci/if_iwmvar.h

470

uint32_t stop_tidmask;

sys/dev/pci/if_iwmvar.h

514

uint32_t sched_base;

sys/dev/pci/if_iwmvar.h

564

uint32_t sc_fh_init_mask;

sys/dev/pci/if_iwmvar.h

565

uint32_t sc_hw_init_mask;

sys/dev/pci/if_iwmvar.h

566

uint32_t sc_fh_mask;

sys/dev/pci/if_iwmvar.h

567

uint32_t sc_hw_mask;

sys/dev/pci/if_iwmvar.h

588

uint32_t sc_fw_phy_config;

sys/dev/pci/if_iwmvar.h

589

uint32_t sc_extra_phy_config;

sys/dev/pci/if_iwmvar.h

623

uint32_t sc_time_event_uid;

sys/dev/pci/if_iwmvar.h

684

uint32_t tfd_queue_msk;

sys/dev/pci/if_iwmvar.h

692

#define IWM_ICT_COUNT (IWM_ICT_SIZE / sizeof (uint32_t))

sys/dev/pci/if_iwn.c

1015

iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count)

sys/dev/pci/if_iwn.c

1018

uint32_t val, tmp;

sys/dev/pci/if_iwn.c

1179

size = IWN_RX_RING_COUNT * sizeof (uint32_t);

sys/dev/pci/if_iwn.c

119

int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int);

sys/dev/pci/if_iwn.c

143

void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t);

sys/dev/pci/if_iwn.c

1477

uint32_t addr;

sys/dev/pci/if_iwn.c

1559

uint32_t base, addr;

sys/dev/pci/if_iwn.c

1609

&sc->eeprom_crystal, sizeof (uint32_t));

sys/dev/pci/if_iwn.c

1616

iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr)

sys/dev/pci/if_iwn.c

173

int, uint32_t, struct iwn_txagg_status *);

sys/dev/pci/if_iwn.c

1908

uint32_t flags = 0;

sys/dev/pci/if_iwn.c

2007

uint32_t flags;

sys/dev/pci/if_iwn.c

2049

flags = letoh32(*(uint32_t *)(head + len));

sys/dev/pci/if_iwn.c

2098

ring->cur * sizeof (uint32_t), sizeof (uint32_t),

sys/dev/pci/if_iwn.c

2109

ring->cur * sizeof (uint32_t), sizeof (uint32_t),

sys/dev/pci/if_iwn.c

2556

uint8_t rate, uint8_t rflags, int nframes, uint32_t ssn,

sys/dev/pci/if_iwn.c

2661

uint32_t ssn;

sys/dev/pci/if_iwn.c

2708

uint32_t ssn;

sys/dev/pci/if_iwn.c

283

int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t,

sys/dev/pci/if_iwn.c

2915

uint32_t missed;

sys/dev/pci/if_iwn.c

2977

uint32_t *status = (uint32_t *)(desc + 1);

sys/dev/pci/if_iwn.c

3098

iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump,

sys/dev/pci/if_iwn.c

3099

sizeof (dump) / sizeof (uint32_t));

sys/dev/pci/if_iwn.c

3138

uint32_t r1, r2, tmp;

sys/dev/pci/if_iwn.c

3326

uint32_t flags;

sys/dev/pci/if_iwn.c

4083

cmd.binitval = htole32((uint32_t)(val - mod));

sys/dev/pci/if_iwn.c

4086

ni->ni_intval, letoh64(cmd.tstamp), (uint32_t)(val - mod)));

sys/dev/pci/if_iwn.c

4400

uint32_t flags;

sys/dev/pci/if_iwn.c

4441

uint32_t val;

sys/dev/pci/if_iwn.c

4605

uint32_t val, rxena, fa;

sys/dev/pci/if_iwn.c

4606

uint32_t energy[3], energy_min;

sys/dev/pci/if_iwn.c

4778

uint32_t max, skip_dtim;

sys/dev/pci/if_iwn.c

4811

if (max == (uint32_t)-1)

sys/dev/pci/if_iwn.c

4840

static const uint32_t btcoex_3wire[12] = {

sys/dev/pci/if_iwn.c

4941

uint32_t txmask;

sys/dev/pci/if_iwn.c

6254

IWN4965_SCHED_CTX_LEN / sizeof (uint32_t));

sys/dev/pci/if_iwn.c

6310

IWN5000_SCHED_CTX_LEN / sizeof (uint32_t));

sys/dev/pci/if_iwn.c

6394

size /= sizeof (uint32_t);

sys/dev/pci/if_iwn.c

6401

(const uint32_t *)ucode, size);

sys/dev/pci/if_iwn.c

6502

iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst,

sys/dev/pci/if_iwn.c

6574

const uint32_t *ptr;

sys/dev/pci/if_iwn.c

6576

uint32_t rev;

sys/dev/pci/if_iwn.c

6578

ptr = (const uint32_t *)fw->data;

sys/dev/pci/if_iwn.c

6631

uint32_t len;

sys/dev/pci/if_iwn.c

6705

if (len != sizeof(uint32_t)) {

sys/dev/pci/if_iwn.c

6717

if (len < sizeof(uint32_t))

sys/dev/pci/if_iwn.c

6719

if (len % sizeof(uint32_t))

sys/dev/pci/if_iwn.c

6757

if (fw->size < sizeof (uint32_t)) {

sys/dev/pci/if_iwn.c

6765

if (*(const uint32_t *)fw->data != 0) /* Legacy image. */

sys/dev/pci/if_iwn.c

6915

uint32_t tmp;

sys/dev/pci/if_iwn.c

850

static __inline uint32_t

sys/dev/pci/if_iwn.c

851

iwn_prph_read(struct iwn_softc *sc, uint32_t addr)

sys/dev/pci/if_iwn.c

859

iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)

sys/dev/pci/if_iwn.c

867

iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)

sys/dev/pci/if_iwn.c

873

iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)

sys/dev/pci/if_iwn.c

879

iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr,

sys/dev/pci/if_iwn.c

880

const uint32_t *data, int count)

sys/dev/pci/if_iwn.c

886

static __inline uint32_t

sys/dev/pci/if_iwn.c

887

iwn_mem_read(struct iwn_softc *sc, uint32_t addr)

sys/dev/pci/if_iwn.c

895

iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)

sys/dev/pci/if_iwn.c

903

iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data)

sys/dev/pci/if_iwn.c

905

uint32_t tmp;

sys/dev/pci/if_iwn.c

916

iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data,

sys/dev/pci/if_iwn.c

924

iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val,

sys/dev/pci/if_iwnreg.h

1000

uint32_t lookup_table[12];

sys/dev/pci/if_iwnreg.h

1003

uint32_t prio_boost;

sys/dev/pci/if_iwnreg.h

1032

uint32_t reserved;

sys/dev/pci/if_iwnreg.h

1033

uint32_t tempM;

sys/dev/pci/if_iwnreg.h

1034

uint32_t tempR;

sys/dev/pci/if_iwnreg.h

1161

uint32_t start;

sys/dev/pci/if_iwnreg.h

1162

uint32_t reserved1;

sys/dev/pci/if_iwnreg.h

1163

uint32_t flags;

sys/dev/pci/if_iwnreg.h

1164

uint32_t filter;

sys/dev/pci/if_iwnreg.h

1168

uint32_t duration;

sys/dev/pci/if_iwnreg.h

1195

uint32_t logptr;

sys/dev/pci/if_iwnreg.h

1196

uint32_t errptr;

sys/dev/pci/if_iwnreg.h

1197

uint32_t tstamp;

sys/dev/pci/if_iwnreg.h

1198

uint32_t valid;

sys/dev/pci/if_iwnreg.h

1276

uint32_t power[2];

sys/dev/pci/if_iwnreg.h

1278

uint32_t status; /* if nframes == 1 */

sys/dev/pci/if_iwnreg.h

1294

uint32_t power[2];

sys/dev/pci/if_iwnreg.h

1295

uint32_t info;

sys/dev/pci/if_iwnreg.h

1306

uint32_t status; /* if nframes == 1 */

sys/dev/pci/if_iwnreg.h

1314

uint32_t consecutive;

sys/dev/pci/if_iwnreg.h

1315

uint32_t total;

sys/dev/pci/if_iwnreg.h

1316

uint32_t expected;

sys/dev/pci/if_iwnreg.h

1317

uint32_t received;

sys/dev/pci/if_iwnreg.h

1334

uint32_t reserved1;

sys/dev/pci/if_iwnreg.h

1335

uint32_t agc;

sys/dev/pci/if_iwnreg.h

1347

uint32_t beacon;

sys/dev/pci/if_iwnreg.h

1385

uint32_t tbeacon;

sys/dev/pci/if_iwnreg.h

1389

uint32_t status;

sys/dev/pci/if_iwnreg.h

1410

uint32_t start;

sys/dev/pci/if_iwnreg.h

1415

uint32_t cca_ofdm;

sys/dev/pci/if_iwnreg.h

1416

uint32_t cca_cck;

sys/dev/pci/if_iwnreg.h

1417

uint32_t cca_time;

sys/dev/pci/if_iwnreg.h

1420

uint32_t ofdm[8];

sys/dev/pci/if_iwnreg.h

1421

uint32_t cck[8];

sys/dev/pci/if_iwnreg.h

1422

uint32_t stop;

sys/dev/pci/if_iwnreg.h

1423

uint32_t status;

sys/dev/pci/if_iwnreg.h

1435

uint32_t ina;

sys/dev/pci/if_iwnreg.h

1436

uint32_t fina;

sys/dev/pci/if_iwnreg.h

1437

uint32_t bad_plcp;

sys/dev/pci/if_iwnreg.h

1438

uint32_t bad_crc32;

sys/dev/pci/if_iwnreg.h

1439

uint32_t overrun;

sys/dev/pci/if_iwnreg.h

1440

uint32_t eoverrun;

sys/dev/pci/if_iwnreg.h

1441

uint32_t good_crc32;

sys/dev/pci/if_iwnreg.h

1442

uint32_t fa;

sys/dev/pci/if_iwnreg.h

1443

uint32_t bad_fina_sync;

sys/dev/pci/if_iwnreg.h

1444

uint32_t sfd_timeout;

sys/dev/pci/if_iwnreg.h

1445

uint32_t fina_timeout;

sys/dev/pci/if_iwnreg.h

1446

uint32_t no_rts_ack;

sys/dev/pci/if_iwnreg.h

1447

uint32_t rxe_limit;

sys/dev/pci/if_iwnreg.h

1448

uint32_t ack;

sys/dev/pci/if_iwnreg.h

1449

uint32_t cts;

sys/dev/pci/if_iwnreg.h

1450

uint32_t ba_resp;

sys/dev/pci/if_iwnreg.h

1451

uint32_t dsp_kill;

sys/dev/pci/if_iwnreg.h

1452

uint32_t bad_mh;

sys/dev/pci/if_iwnreg.h

1453

uint32_t rssi_sum;

sys/dev/pci/if_iwnreg.h

1454

uint32_t reserved;

sys/dev/pci/if_iwnreg.h

1458

uint32_t bad_cts;

sys/dev/pci/if_iwnreg.h

1459

uint32_t bad_ack;

sys/dev/pci/if_iwnreg.h

1460

uint32_t not_bss;

sys/dev/pci/if_iwnreg.h

1461

uint32_t filtered;

sys/dev/pci/if_iwnreg.h

1462

uint32_t bad_chan;

sys/dev/pci/if_iwnreg.h

1463

uint32_t beacons;

sys/dev/pci/if_iwnreg.h

1464

uint32_t missed_beacons;

sys/dev/pci/if_iwnreg.h

1465

uint32_t adc_saturated; /* time in 0.8us */

sys/dev/pci/if_iwnreg.h

1466

uint32_t ina_searched; /* time in 0.8us */

sys/dev/pci/if_iwnreg.h

1467

uint32_t noise[3];

sys/dev/pci/if_iwnreg.h

1468

uint32_t flags;

sys/dev/pci/if_iwnreg.h

1469

uint32_t load;

sys/dev/pci/if_iwnreg.h

1470

uint32_t fa;

sys/dev/pci/if_iwnreg.h

1471

uint32_t rssi[3];

sys/dev/pci/if_iwnreg.h

1472

uint32_t energy[3];

sys/dev/pci/if_iwnreg.h

1476

uint32_t bad_plcp;

sys/dev/pci/if_iwnreg.h

1477

uint32_t overrun;

sys/dev/pci/if_iwnreg.h

1478

uint32_t eoverrun;

sys/dev/pci/if_iwnreg.h

1479

uint32_t good_crc32;

sys/dev/pci/if_iwnreg.h

1480

uint32_t bad_crc32;

sys/dev/pci/if_iwnreg.h

1481

uint32_t bad_mh;

sys/dev/pci/if_iwnreg.h

1482

uint32_t good_ampdu_crc32;

sys/dev/pci/if_iwnreg.h

1483

uint32_t ampdu;

sys/dev/pci/if_iwnreg.h

1484

uint32_t fragment;

sys/dev/pci/if_iwnreg.h

1485

uint32_t reserved;

sys/dev/pci/if_iwnreg.h

1496

uint32_t preamble;

sys/dev/pci/if_iwnreg.h

1497

uint32_t rx_detected;

sys/dev/pci/if_iwnreg.h

1498

uint32_t bt_defer;

sys/dev/pci/if_iwnreg.h

1499

uint32_t bt_kill;

sys/dev/pci/if_iwnreg.h

1500

uint32_t short_len;

sys/dev/pci/if_iwnreg.h

1501

uint32_t cts_timeout;

sys/dev/pci/if_iwnreg.h

1502

uint32_t ack_timeout;

sys/dev/pci/if_iwnreg.h

1503

uint32_t exp_ack;

sys/dev/pci/if_iwnreg.h

1504

uint32_t ack;

sys/dev/pci/if_iwnreg.h

1505

uint32_t msdu;

sys/dev/pci/if_iwnreg.h

1506

uint32_t busrt_err1;

sys/dev/pci/if_iwnreg.h

1507

uint32_t burst_err2;

sys/dev/pci/if_iwnreg.h

1508

uint32_t cts_collision;

sys/dev/pci/if_iwnreg.h

1509

uint32_t ack_collision;

sys/dev/pci/if_iwnreg.h

1510

uint32_t ba_timeout;

sys/dev/pci/if_iwnreg.h

1511

uint32_t ba_resched;

sys/dev/pci/if_iwnreg.h

1512

uint32_t query_ampdu;

sys/dev/pci/if_iwnreg.h

1513

uint32_t query;

sys/dev/pci/if_iwnreg.h

1514

uint32_t query_ampdu_frag;

sys/dev/pci/if_iwnreg.h

1515

uint32_t query_mismatch;

sys/dev/pci/if_iwnreg.h

1516

uint32_t not_ready;

sys/dev/pci/if_iwnreg.h

1517

uint32_t underrun;

sys/dev/pci/if_iwnreg.h

1518

uint32_t bt_ht_kill;

sys/dev/pci/if_iwnreg.h

1519

uint32_t rx_ba_resp;

sys/dev/pci/if_iwnreg.h

1520

uint32_t reserved[2];

sys/dev/pci/if_iwnreg.h

1524

uint32_t temp;

sys/dev/pci/if_iwnreg.h

1525

uint32_t temp_m;

sys/dev/pci/if_iwnreg.h

1526

uint32_t burst_check;

sys/dev/pci/if_iwnreg.h

1527

uint32_t burst;

sys/dev/pci/if_iwnreg.h

1528

uint32_t reserved1[4];

sys/dev/pci/if_iwnreg.h

1529

uint32_t sleep;

sys/dev/pci/if_iwnreg.h

1530

uint32_t slot_out;

sys/dev/pci/if_iwnreg.h

1531

uint32_t slot_idle;

sys/dev/pci/if_iwnreg.h

1532

uint32_t ttl_tstamp;

sys/dev/pci/if_iwnreg.h

1533

uint32_t tx_ant_a;

sys/dev/pci/if_iwnreg.h

1534

uint32_t tx_ant_b;

sys/dev/pci/if_iwnreg.h

1535

uint32_t exec;

sys/dev/pci/if_iwnreg.h

1536

uint32_t probe;

sys/dev/pci/if_iwnreg.h

1537

uint32_t reserved2[2];

sys/dev/pci/if_iwnreg.h

1538

uint32_t rx_enabled;

sys/dev/pci/if_iwnreg.h

1539

uint32_t reserved3[3];

sys/dev/pci/if_iwnreg.h

1543

uint32_t flags;

sys/dev/pci/if_iwnreg.h

1554

uint32_t valid;

sys/dev/pci/if_iwnreg.h

1555

uint32_t id;

sys/dev/pci/if_iwnreg.h

1556

uint32_t pc;

sys/dev/pci/if_iwnreg.h

1557

uint32_t branch_link[2];

sys/dev/pci/if_iwnreg.h

1558

uint32_t interrupt_link[2];

sys/dev/pci/if_iwnreg.h

1559

uint32_t error_data[2];

sys/dev/pci/if_iwnreg.h

1560

uint32_t src_line;

sys/dev/pci/if_iwnreg.h

1561

uint32_t tsf;

sys/dev/pci/if_iwnreg.h

1562

uint32_t time[2];

sys/dev/pci/if_iwnreg.h

1567

uint32_t zero; /* Always 0, to differentiate from legacy. */

sys/dev/pci/if_iwnreg.h

1568

uint32_t signature;

sys/dev/pci/if_iwnreg.h

1572

uint32_t rev;

sys/dev/pci/if_iwnreg.h

1575

uint32_t build;

sys/dev/pci/if_iwnreg.h

1593

uint32_t len;

sys/dev/pci/if_iwnreg.h

1758

static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = {

sys/dev/pci/if_iwnreg.h

1768

static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = {

sys/dev/pci/if_iwnreg.h

180

#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24)

sys/dev/pci/if_iwnreg.h

1901

uint32_t rxtimeout;

sys/dev/pci/if_iwnreg.h

1902

uint32_t txtimeout;

sys/dev/pci/if_iwnreg.h

1903

uint32_t intval[5];

sys/dev/pci/if_iwnreg.h

1936

uint32_t min_ofdm_x1;

sys/dev/pci/if_iwnreg.h

1937

uint32_t max_ofdm_x1;

sys/dev/pci/if_iwnreg.h

1938

uint32_t min_ofdm_mrc_x1;

sys/dev/pci/if_iwnreg.h

1939

uint32_t max_ofdm_mrc_x1;

sys/dev/pci/if_iwnreg.h

1940

uint32_t min_ofdm_x4;

sys/dev/pci/if_iwnreg.h

1941

uint32_t max_ofdm_x4;

sys/dev/pci/if_iwnreg.h

1942

uint32_t min_ofdm_mrc_x4;

sys/dev/pci/if_iwnreg.h

1943

uint32_t max_ofdm_mrc_x4;

sys/dev/pci/if_iwnreg.h

1944

uint32_t min_cck_x4;

sys/dev/pci/if_iwnreg.h

1945

uint32_t max_cck_x4;

sys/dev/pci/if_iwnreg.h

1946

uint32_t min_cck_mrc_x4;

sys/dev/pci/if_iwnreg.h

1947

uint32_t max_cck_mrc_x4;

sys/dev/pci/if_iwnreg.h

1948

uint32_t min_energy_cck;

sys/dev/pci/if_iwnreg.h

1949

uint32_t energy_cck;

sys/dev/pci/if_iwnreg.h

1950

uint32_t energy_ofdm;

sys/dev/pci/if_iwnreg.h

37

#define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t))

sys/dev/pci/if_iwnreg.h

374

uint32_t addr;

sys/dev/pci/if_iwnreg.h

378

uint32_t reserved2;

sys/dev/pci/if_iwnreg.h

386

uint32_t reserved[2];

sys/dev/pci/if_iwnreg.h

390

uint32_t len;

sys/dev/pci/if_iwnreg.h

47

#define IWN_LOADDR(paddr) ((uint32_t)(paddr))

sys/dev/pci/if_iwnreg.h

499

uint32_t flags;

sys/dev/pci/if_iwnreg.h

516

uint32_t filter;

sys/dev/pci/if_iwnreg.h

537

uint32_t flags;

sys/dev/pci/if_iwnreg.h

538

uint32_t filter;

sys/dev/pci/if_iwnreg.h

548

uint32_t reserved3;

sys/dev/pci/if_iwnreg.h

552

uint32_t flags;

sys/dev/pci/if_iwnreg.h

553

uint32_t filter;

sys/dev/pci/if_iwnreg.h

567

uint32_t flags;

sys/dev/pci/if_iwnreg.h

568

uint32_t filter;

sys/dev/pci/if_iwnreg.h

576

uint32_t flags;

sys/dev/pci/if_iwnreg.h

594

uint32_t binitval;

sys/dev/pci/if_iwnreg.h

639

uint32_t htflags;

sys/dev/pci/if_iwnreg.h

647

uint32_t htmask;

sys/dev/pci/if_iwnreg.h

653

uint32_t reserved7;

sys/dev/pci/if_iwnreg.h

671

uint32_t htflags;

sys/dev/pci/if_iwnreg.h

672

uint32_t htmask;

sys/dev/pci/if_iwnreg.h

678

uint32_t reserved7;

sys/dev/pci/if_iwnreg.h

693

uint32_t flags;

sys/dev/pci/if_iwnreg.h

708

uint32_t scratch;

sys/dev/pci/if_iwnreg.h

725

uint32_t lifetime;

sys/dev/pci/if_iwnreg.h

728

uint32_t loaddr;

sys/dev/pci/if_iwnreg.h

754

uint32_t reserved2;

sys/dev/pci/if_iwnreg.h

760

uint32_t reserved3;

sys/dev/pci/if_iwnreg.h

765

uint32_t unit; /* multiplier (in usecs) */

sys/dev/pci/if_iwnreg.h

777

uint32_t flags;

sys/dev/pci/if_iwnreg.h

793

uint32_t enable;

sys/dev/pci/if_iwnreg.h

794

uint32_t start;

sys/dev/pci/if_iwnreg.h

797

uint32_t send;

sys/dev/pci/if_iwnreg.h

798

uint32_t apply;

sys/dev/pci/if_iwnreg.h

799

uint32_t reserved;

sys/dev/pci/if_iwnreg.h

805

uint32_t flags;

sys/dev/pci/if_iwnreg.h

811

uint32_t reserved;

sys/dev/pci/if_iwnreg.h

825

uint32_t rxtimeout;

sys/dev/pci/if_iwnreg.h

826

uint32_t txtimeout;

sys/dev/pci/if_iwnreg.h

827

uint32_t intval[5];

sys/dev/pci/if_iwnreg.h

828

uint32_t beacons;

sys/dev/pci/if_iwnreg.h

846

uint32_t max_out; /* (in usec) background scans */

sys/dev/pci/if_iwnreg.h

847

uint32_t pause_scan; /* (in usec) background scans */

sys/dev/pci/if_iwnreg.h

848

uint32_t flags;

sys/dev/pci/if_iwnreg.h

849

uint32_t filter;

sys/dev/pci/if_iwnreg.h

858

uint32_t flags;

sys/dev/pci/if_iwnreg.h

958

uint32_t kill_ack;

sys/dev/pci/if_iwnreg.h

959

uint32_t kill_cts;

sys/dev/pci/if_iwnreg.h

977

uint32_t kill_ack;

sys/dev/pci/if_iwnreg.h

978

uint32_t kill_cts;

sys/dev/pci/if_iwnreg.h

982

uint32_t lookup_table[12];

sys/dev/pci/if_iwnreg.h

995

uint32_t kill_ack;

sys/dev/pci/if_iwnreg.h

996

uint32_t kill_cts;

sys/dev/pci/if_iwnvar.h

109

uint32_t next_ampdu_id;

sys/dev/pci/if_iwnvar.h

120

uint32_t noise[3];

sys/dev/pci/if_iwnvar.h

121

uint32_t rssi[3];

sys/dev/pci/if_iwnvar.h

122

uint32_t ofdm_x1;

sys/dev/pci/if_iwnvar.h

123

uint32_t ofdm_mrc_x1;

sys/dev/pci/if_iwnvar.h

124

uint32_t ofdm_x4;

sys/dev/pci/if_iwnvar.h

125

uint32_t ofdm_mrc_x4;

sys/dev/pci/if_iwnvar.h

126

uint32_t cck_x4;

sys/dev/pci/if_iwnvar.h

127

uint32_t cck_mrc_x4;

sys/dev/pci/if_iwnvar.h

128

uint32_t bad_plcp_ofdm;

sys/dev/pci/if_iwnvar.h

129

uint32_t fa_ofdm;

sys/dev/pci/if_iwnvar.h

130

uint32_t bad_plcp_cck;

sys/dev/pci/if_iwnvar.h

131

uint32_t fa_cck;

sys/dev/pci/if_iwnvar.h

132

uint32_t low_fa;

sys/dev/pci/if_iwnvar.h

141

uint32_t energy_samples[10];

sys/dev/pci/if_iwnvar.h

143

uint32_t energy_cck;

sys/dev/pci/if_iwnvar.h

153

uint32_t textsz;

sys/dev/pci/if_iwnvar.h

155

uint32_t datasz;

sys/dev/pci/if_iwnvar.h

232

uint32_t fw_text_maxsz;

sys/dev/pci/if_iwnvar.h

233

uint32_t fw_data_maxsz;

sys/dev/pci/if_iwnvar.h

234

uint32_t fwsz;

sys/dev/pci/if_iwnvar.h

240

uint32_t sched_base;

sys/dev/pci/if_iwnvar.h

250

uint32_t *ict;

sys/dev/pci/if_iwnvar.h

273

uint32_t errptr;

sys/dev/pci/if_iwnvar.h

283

uint32_t rx_stats_flags;

sys/dev/pci/if_iwnvar.h

284

uint32_t rawtemp;

sys/dev/pci/if_iwnvar.h

287

uint32_t qfullmsk;

sys/dev/pci/if_iwnvar.h

289

uint32_t prom_base;

sys/dev/pci/if_iwnvar.h

295

uint32_t eeprom_crystal;

sys/dev/pci/if_iwnvar.h

308

uint32_t tlv_feature_flags;

sys/dev/pci/if_iwnvar.h

311

uint32_t int_mask;

sys/dev/pci/if_iwnvar.h

96

uint32_t *desc;

sys/dev/pci/if_iwx.c

10478

uint32_t valid; /* (nonzero) valid, (0) log is empty */

sys/dev/pci/if_iwx.c

10479

uint32_t error_id; /* type of error */

sys/dev/pci/if_iwx.c

10480

uint32_t trm_hw_status0; /* TRM HW status */

sys/dev/pci/if_iwx.c

10481

uint32_t trm_hw_status1; /* TRM HW status */

sys/dev/pci/if_iwx.c

10482

uint32_t blink2; /* branch link */

sys/dev/pci/if_iwx.c

10483

uint32_t ilink1; /* interrupt link */

sys/dev/pci/if_iwx.c

10484

uint32_t ilink2; /* interrupt link */

sys/dev/pci/if_iwx.c

10485

uint32_t data1; /* error-specific data */

sys/dev/pci/if_iwx.c

10486

uint32_t data2; /* error-specific data */

sys/dev/pci/if_iwx.c

10487

uint32_t data3; /* error-specific data */

sys/dev/pci/if_iwx.c

10488

uint32_t bcon_time; /* beacon timer */

sys/dev/pci/if_iwx.c

10489

uint32_t tsf_low; /* network timestamp function timer */

sys/dev/pci/if_iwx.c

10490

uint32_t tsf_hi; /* network timestamp function timer */

sys/dev/pci/if_iwx.c

10491

uint32_t gp1; /* GP1 timer register */

sys/dev/pci/if_iwx.c

10492

uint32_t gp2; /* GP2 timer register */

sys/dev/pci/if_iwx.c

10493

uint32_t fw_rev_type; /* firmware revision type */

sys/dev/pci/if_iwx.c

10494

uint32_t major; /* uCode version major */

sys/dev/pci/if_iwx.c

10495

uint32_t minor; /* uCode version minor */

sys/dev/pci/if_iwx.c

10496

uint32_t hw_ver; /* HW Silicon version */

sys/dev/pci/if_iwx.c

10497

uint32_t brd_ver; /* HW board version */

sys/dev/pci/if_iwx.c

10498

uint32_t log_pc; /* log program counter */

sys/dev/pci/if_iwx.c

10499

uint32_t frame_ptr; /* frame pointer */

sys/dev/pci/if_iwx.c

10500

uint32_t stack_ptr; /* stack pointer */

sys/dev/pci/if_iwx.c

10501

uint32_t hcmd; /* last host command header */

sys/dev/pci/if_iwx.c

10502

uint32_t isr0; /* isr status register LMPM_NIC_ISR0:

sys/dev/pci/if_iwx.c

10504

uint32_t isr1; /* isr status register LMPM_NIC_ISR1:

sys/dev/pci/if_iwx.c

10506

uint32_t isr2; /* isr status register LMPM_NIC_ISR2:

sys/dev/pci/if_iwx.c

10508

uint32_t isr3; /* isr status register LMPM_NIC_ISR3:

sys/dev/pci/if_iwx.c

10510

uint32_t isr4; /* isr status register LMPM_NIC_ISR4:

sys/dev/pci/if_iwx.c

10512

uint32_t last_cmd_id; /* last HCMD id handled by the firmware */

sys/dev/pci/if_iwx.c

10513

uint32_t wait_event; /* wait event() caller address */

sys/dev/pci/if_iwx.c

10514

uint32_t l2p_control; /* L2pControlField */

sys/dev/pci/if_iwx.c

10515

uint32_t l2p_duration; /* L2pDurationField */

sys/dev/pci/if_iwx.c

10516

uint32_t l2p_mhvalid; /* L2pMhValidBits */

sys/dev/pci/if_iwx.c

10517

uint32_t l2p_addr_match; /* L2pAddrMatchStat */

sys/dev/pci/if_iwx.c

10518

uint32_t lmpm_pmg_sel; /* indicate which clocks are turned on

sys/dev/pci/if_iwx.c

10520

uint32_t u_timestamp; /* indicate when the date and time of the

sys/dev/pci/if_iwx.c

10522

uint32_t flow_handler; /* FH read/write pointers, RX credit */

sys/dev/pci/if_iwx.c

10533

uint32_t valid; /* (nonzero) valid, (0) log is empty */

sys/dev/pci/if_iwx.c

10534

uint32_t error_id; /* type of error */

sys/dev/pci/if_iwx.c

10535

uint32_t blink1; /* branch link */

sys/dev/pci/if_iwx.c

10536

uint32_t blink2; /* branch link */

sys/dev/pci/if_iwx.c

10537

uint32_t ilink1; /* interrupt link */

sys/dev/pci/if_iwx.c

10538

uint32_t ilink2; /* interrupt link */

sys/dev/pci/if_iwx.c

10539

uint32_t data1; /* error-specific data */

sys/dev/pci/if_iwx.c

10540

uint32_t data2; /* error-specific data */

sys/dev/pci/if_iwx.c

10541

uint32_t data3; /* error-specific data */

sys/dev/pci/if_iwx.c

10542

uint32_t umac_major;

sys/dev/pci/if_iwx.c

10543

uint32_t umac_minor;

sys/dev/pci/if_iwx.c

10544

uint32_t frame_pointer; /* core register 27*/

sys/dev/pci/if_iwx.c

10545

uint32_t stack_pointer; /* core register 28 */

sys/dev/pci/if_iwx.c

10546

uint32_t cmd_header; /* latest host cmd sent to UMAC */

sys/dev/pci/if_iwx.c

10547

uint32_t nic_isr_pref; /* ISR status register */

sys/dev/pci/if_iwx.c

10550

#define ERROR_START_OFFSET (1 * sizeof(uint32_t))

sys/dev/pci/if_iwx.c

10551

#define ERROR_ELEM_SIZE (7 * sizeof(uint32_t))

sys/dev/pci/if_iwx.c

10557

uint32_t base;

sys/dev/pci/if_iwx.c

10558

uint32_t min_base = 0x400000;

sys/dev/pci/if_iwx.c

10570

if (iwx_read_mem(sc, base, &table, sizeof(table)/sizeof(uint32_t))) {

sys/dev/pci/if_iwx.c

10629

iwx_desc_lookup(uint32_t num)

sys/dev/pci/if_iwx.c

10653

uint32_t base;

sys/dev/pci/if_iwx.c

10654

uint32_t min_base = 0x400000;

sys/dev/pci/if_iwx.c

10667

if (iwx_read_mem(sc, base, &table, sizeof(table)/sizeof(uint32_t))) {

sys/dev/pci/if_iwx.c

10778

uint32_t offset = 0, nextoff = 0, nmpdu = 0, len;

sys/dev/pci/if_iwx.c

11096

uint32_t action;

sys/dev/pci/if_iwx.c

11110

uint32_t status, start, conf_id;

sys/dev/pci/if_iwx.c

1131

if (dlen < sizeof(uint32_t))

sys/dev/pci/if_iwx.c

11315

uint32_t *ict = sc->ict_dma.vaddr;

sys/dev/pci/if_iwx.c

1142

memcpy(&fwone->fws_devoff, data, sizeof(uint32_t));

sys/dev/pci/if_iwx.c

11447

uint32_t inta_fh, inta_hw;

sys/dev/pci/if_iwx.c

1145

fwone->fws_data = data + sizeof(uint32_t);

sys/dev/pci/if_iwx.c

1146

fwone->fws_len = dlen - sizeof(uint32_t);

sys/dev/pci/if_iwx.c

11559

uint32_t rf_id;

sys/dev/pci/if_iwx.c

1159

uint32_t ucode_type;

sys/dev/pci/if_iwx.c

1167

uint32_t ucode_type = le32toh(def_calib->ucode_type);

sys/dev/pci/if_iwx.c

1205

uint32_t tlv_type;

sys/dev/pci/if_iwx.c

12128

uint32_t val = 0;

sys/dev/pci/if_iwx.c

12295

uint32_t rf_id = IWX_CSR_HW_RFID_TYPE(sc->sc_hw_rf_id);

sys/dev/pci/if_iwx.c

1238

if (*(uint32_t *)fw->fw_rawdata != 0

sys/dev/pci/if_iwx.c

1275

if (tlv_len < sizeof(uint32_t)) {

sys/dev/pci/if_iwx.c

1280

= le32toh(*(uint32_t *)tlv_data);

sys/dev/pci/if_iwx.c

1295

if (tlv_len < sizeof(uint32_t)) {

sys/dev/pci/if_iwx.c

1310

sc->sc_capaflags = le32toh(*(uint32_t *)tlv_data);

sys/dev/pci/if_iwx.c

1318

uint32_t num_cpu;

sys/dev/pci/if_iwx.c

1319

if (tlv_len != sizeof(uint32_t)) {

sys/dev/pci/if_iwx.c

1323

num_cpu = le32toh(*(uint32_t *)tlv_data);

sys/dev/pci/if_iwx.c

135

#define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_)))

sys/dev/pci/if_iwx.c

1358

if (tlv_len != sizeof(uint32_t)) {

sys/dev/pci/if_iwx.c

1362

sc->sc_fw_phy_config = le32toh(*(uint32_t *)tlv_data);

sys/dev/pci/if_iwx.c

1421

if (tlv_len != sizeof(uint32_t)) {

sys/dev/pci/if_iwx.c

1428

if (tlv_len != sizeof(uint32_t)) {

sys/dev/pci/if_iwx.c

1433

le32toh(*(uint32_t *)tlv_data);

sys/dev/pci/if_iwx.c

1441

if (tlv_len != sizeof(uint32_t) * 3) {

sys/dev/pci/if_iwx.c

1447

le32toh(((uint32_t *)tlv_data)[0]),

sys/dev/pci/if_iwx.c

1448

le32toh(((uint32_t *)tlv_data)[1]),

sys/dev/pci/if_iwx.c

1449

le32toh(((uint32_t *)tlv_data)[2]));

sys/dev/pci/if_iwx.c

1657

uint32_t

sys/dev/pci/if_iwx.c

1666

uint32_t

sys/dev/pci/if_iwx.c

1667

iwx_read_prph_unlocked(struct iwx_softc *sc, uint32_t addr)

sys/dev/pci/if_iwx.c

1669

uint32_t mask = iwx_prph_addr_mask(sc);

sys/dev/pci/if_iwx.c

1675

uint32_t

sys/dev/pci/if_iwx.c

1676

iwx_read_prph(struct iwx_softc *sc, uint32_t addr)

sys/dev/pci/if_iwx.c

1683

iwx_write_prph_unlocked(struct iwx_softc *sc, uint32_t addr, uint32_t val)

sys/dev/pci/if_iwx.c

1685

uint32_t mask = iwx_prph_addr_mask(sc);

sys/dev/pci/if_iwx.c

1692

iwx_write_prph(struct iwx_softc *sc, uint32_t addr, uint32_t val)

sys/dev/pci/if_iwx.c

1698

uint32_t

sys/dev/pci/if_iwx.c

1699

iwx_read_umac_prph_unlocked(struct iwx_softc *sc, uint32_t addr)

sys/dev/pci/if_iwx.c

1704

uint32_t

sys/dev/pci/if_iwx.c

1705

iwx_read_umac_prph(struct iwx_softc *sc, uint32_t addr)

sys/dev/pci/if_iwx.c

1711

iwx_write_umac_prph_unlocked(struct iwx_softc *sc, uint32_t addr, uint32_t val)

sys/dev/pci/if_iwx.c

1717

iwx_write_umac_prph(struct iwx_softc *sc, uint32_t addr, uint32_t val)

sys/dev/pci/if_iwx.c

1723

iwx_read_mem(struct iwx_softc *sc, uint32_t addr, void *buf, int dwords)

sys/dev/pci/if_iwx.c

1726

uint32_t *vals = buf;

sys/dev/pci/if_iwx.c

1740

iwx_write_mem(struct iwx_softc *sc, uint32_t addr, const void *buf, int dwords)

sys/dev/pci/if_iwx.c

1743

const uint32_t *vals = buf;

sys/dev/pci/if_iwx.c

1749

uint32_t val = vals ? vals[offs] : 0;

sys/dev/pci/if_iwx.c

1760

iwx_write_mem32(struct iwx_softc *sc, uint32_t addr, uint32_t val)

sys/dev/pci/if_iwx.c

1766

iwx_poll_bit(struct iwx_softc *sc, int reg, uint32_t bits, uint32_t mask,

sys/dev/pci/if_iwx.c

1784

uint32_t access_req, ready, mask;

sys/dev/pci/if_iwx.c

1826

uint32_t access_req;

sys/dev/pci/if_iwx.c

1841

iwx_set_bits_mask_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits,

sys/dev/pci/if_iwx.c

1842

uint32_t mask)

sys/dev/pci/if_iwx.c

1844

uint32_t val;

sys/dev/pci/if_iwx.c

1857

iwx_set_bits_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pci/if_iwx.c

1863

iwx_clear_bits_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pci/if_iwx.c

1970

size = sizeof(uint32_t);

sys/dev/pci/if_iwx.c

2251

uint32_t v;

sys/dev/pci/if_iwx.c

245

void iwx_fw_version_str(char *, size_t, uint32_t, uint32_t, uint32_t);

sys/dev/pci/if_iwx.c

2462

uint32_t ready;

sys/dev/pci/if_iwx.c

251

uint32_t iwx_prph_addr_mask(struct iwx_softc *);

sys/dev/pci/if_iwx.c

252

uint32_t iwx_read_prph_unlocked(struct iwx_softc *, uint32_t);

sys/dev/pci/if_iwx.c

253

uint32_t iwx_read_prph(struct iwx_softc *, uint32_t);

sys/dev/pci/if_iwx.c

254

void iwx_write_prph_unlocked(struct iwx_softc *, uint32_t, uint32_t);

sys/dev/pci/if_iwx.c

255

void iwx_write_prph(struct iwx_softc *, uint32_t, uint32_t);

sys/dev/pci/if_iwx.c

256

uint32_t iwx_read_umac_prph_unlocked(struct iwx_softc *, uint32_t);

sys/dev/pci/if_iwx.c

257

uint32_t iwx_read_umac_prph(struct iwx_softc *, uint32_t);

sys/dev/pci/if_iwx.c

258

void iwx_write_umac_prph_unlocked(struct iwx_softc *, uint32_t, uint32_t);

sys/dev/pci/if_iwx.c

259

void iwx_write_umac_prph(struct iwx_softc *, uint32_t, uint32_t);

sys/dev/pci/if_iwx.c

260

int iwx_read_mem(struct iwx_softc *, uint32_t, void *, int);

sys/dev/pci/if_iwx.c

261

int iwx_write_mem(struct iwx_softc *, uint32_t, const void *, int);

sys/dev/pci/if_iwx.c

262

int iwx_write_mem32(struct iwx_softc *, uint32_t, uint32_t);

sys/dev/pci/if_iwx.c

263

int iwx_poll_bit(struct iwx_softc *, int, uint32_t, uint32_t, int);

sys/dev/pci/if_iwx.c

267

int iwx_set_bits_mask_prph(struct iwx_softc *, uint32_t, uint32_t,

sys/dev/pci/if_iwx.c

2670

uint32_t hpm, wprot;

sys/dev/pci/if_iwx.c

268

uint32_t);

sys/dev/pci/if_iwx.c

269

int iwx_set_bits_prph(struct iwx_softc *, uint32_t, uint32_t);

sys/dev/pci/if_iwx.c

270

int iwx_clear_bits_prph(struct iwx_softc *, uint32_t, uint32_t);

sys/dev/pci/if_iwx.c

2823

uint32_t mask, val, reg_val = 0;

sys/dev/pci/if_iwx.c

2927

uint32_t wr_idx;

sys/dev/pci/if_iwx.c

307

uint32_t);

sys/dev/pci/if_iwx.c

3079

uint32_t duration_tu)

sys/dev/pci/if_iwx.c

3088

uint32_t cmd_id;

sys/dev/pci/if_iwx.c

309

void iwx_init_channel_map(struct iwx_softc *, uint16_t *, uint32_t *, int);

sys/dev/pci/if_iwx.c

3108

uint32_t cmd_id;

sys/dev/pci/if_iwx.c

3161

uint32_t *channel_profile_v4, int nchan_profile)

sys/dev/pci/if_iwx.c

3167

uint32_t ch_flags;

sys/dev/pci/if_iwx.c

340

void iwx_flip_hw_address(uint32_t, uint32_t, uint8_t *);

sys/dev/pci/if_iwx.c

3441

uint32_t new_baid = 0;

sys/dev/pci/if_iwx.c

3494

uint32_t status;

sys/dev/pci/if_iwx.c

360

int iwx_rx_hwdecrypt(struct iwx_softc *, struct mbuf *, uint32_t,

sys/dev/pci/if_iwx.c

364

void iwx_rx_frame(struct iwx_softc *, struct mbuf *, int, uint32_t, int, int,

sys/dev/pci/if_iwx.c

365

uint32_t, struct ieee80211_rxinfo *, struct mbuf_list *);

sys/dev/pci/if_iwx.c

374

int iwx_binding_cmd(struct iwx_softc *, struct iwx_node *, uint32_t);

sys/dev/pci/if_iwx.c

377

uint8_t, uint8_t, uint32_t, uint8_t, uint8_t, int);

sys/dev/pci/if_iwx.c

379

uint8_t, uint8_t, uint32_t, uint8_t, uint8_t, int);

sys/dev/pci/if_iwx.c

381

uint8_t, uint32_t, uint32_t, uint8_t, uint8_t);

sys/dev/pci/if_iwx.c

383

int iwx_send_cmd_pdu(struct iwx_softc *, uint32_t, uint32_t, uint16_t,

sys/dev/pci/if_iwx.c

386

uint32_t *);

sys/dev/pci/if_iwx.c

387

int iwx_send_cmd_pdu_status(struct iwx_softc *, uint32_t, uint16_t,

sys/dev/pci/if_iwx.c

388

const void *, uint32_t *);

sys/dev/pci/if_iwx.c

3905

uint32_t mac_addr0, mac_addr1;

sys/dev/pci/if_iwx.c

391

uint32_t iwx_fw_rateidx_ofdm(uint8_t);

sys/dev/pci/if_iwx.c

392

uint32_t iwx_fw_rateidx_cck(uint8_t);

sys/dev/pci/if_iwx.c

394

struct ieee80211_frame *, uint16_t *, uint32_t *);

sys/dev/pci/if_iwx.c

3945

iwx_flip_hw_address(uint32_t mac_addr0, uint32_t mac_addr1, uint8_t *dest)

sys/dev/pci/if_iwx.c

3973

uint32_t mac_flags;

sys/dev/pci/if_iwx.c

4181

uint32_t sha1 = 0;

sys/dev/pci/if_iwx.c

4187

uint32_t size = 0;

sys/dev/pci/if_iwx.c

4192

uint32_t tlv_len, tlv_type;

sys/dev/pci/if_iwx.c

4211

if (tlv_len < sizeof(uint32_t))

sys/dev/pci/if_iwx.c

4214

sha1 = le32_to_cpup((const uint32_t *)data);

sys/dev/pci/if_iwx.c

422

struct iwx_scan_channel_params_v6 *, uint32_t, int);

sys/dev/pci/if_iwx.c

4233

uint32_t data_len;

sys/dev/pci/if_iwx.c

4239

if (le32_to_cpup((const uint32_t *)data) == 0xddddeeee)

sys/dev/pci/if_iwx.c

424

struct iwx_scan_channel_params_v7 *, uint32_t, int);

sys/dev/pci/if_iwx.c

4298

uint32_t tlv_len, tlv_type;

sys/dev/pci/if_iwx.c

432

struct iwx_mac_ctx_cmd *, uint32_t);

sys/dev/pci/if_iwx.c

435

int iwx_mac_ctxt_cmd(struct iwx_softc *, struct iwx_node *, uint32_t, int);

sys/dev/pci/if_iwx.c

436

int iwx_mld_mac_ctxt_cmd(struct iwx_softc *, struct iwx_node *, uint32_t,

sys/dev/pci/if_iwx.c

4463

uint32_t cmd_id;

sys/dev/pci/if_iwx.c

460

struct ieee80211_channel *, uint8_t, uint8_t, uint32_t, uint8_t,

sys/dev/pci/if_iwx.c

4762

iwx_rx_hwdecrypt(struct iwx_softc *sc, struct mbuf *m, uint32_t rx_pkt_status,

sys/dev/pci/if_iwx.c

4818

uint32_t rx_pkt_status, int is_shortpre, int rate_n_flags,

sys/dev/pci/if_iwx.c

4819

uint32_t device_timestamp, struct ieee80211_rxinfo *rxi,

sys/dev/pci/if_iwx.c

4865

uint32_t mod_type = (rate_n_flags &

sys/dev/pci/if_iwx.c

4868

uint32_t ridx;

sys/dev/pci/if_iwx.c

490

const char *iwx_desc_lookup(uint32_t);

sys/dev/pci/if_iwx.c

4992

uint32_t rx_pkt_status, rate_n_flags, device_timestamp;

sys/dev/pci/if_iwx.c

500

struct iwx_rx_mpdu_desc *, int, int, uint32_t,

sys/dev/pci/if_iwx.c

5035

uint32_t device_timestamp, struct ieee80211_rxinfo *rxi,

sys/dev/pci/if_iwx.c

5043

uint32_t reorder_data = le32toh(desc->reorder_data);

sys/dev/pci/if_iwx.c

5190

uint32_t len, hdrlen, rate_n_flags, device_timestamp;

sys/dev/pci/if_iwx.c

5410

uint32_t ssn;

sys/dev/pci/if_iwx.c

5411

uint32_t len = iwx_rx_packet_len(pkt);

sys/dev/pci/if_iwx.c

5532

uint32_t missed;

sys/dev/pci/if_iwx.c

5560

iwx_binding_cmd(struct iwx_softc *sc, struct iwx_node *in, uint32_t action)

sys/dev/pci/if_iwx.c

5564

uint32_t mac_id = IWX_FW_CMD_ID_AND_COLOR(in->in_id, in->in_color);

sys/dev/pci/if_iwx.c

5566

uint32_t status;

sys/dev/pci/if_iwx.c

5652

uint8_t chains_static, uint8_t chains_dynamic, uint32_t action, uint8_t sco,

sys/dev/pci/if_iwx.c

5715

uint8_t chains_static, uint8_t chains_dynamic, uint32_t action, uint8_t sco,

sys/dev/pci/if_iwx.c

5778

uint8_t chains_static, uint8_t chains_dynamic, uint32_t action,

sys/dev/pci/if_iwx.c

5779

uint32_t apply_time, uint8_t sco, uint8_t vht_chan_width)

sys/dev/pci/if_iwx.c

5976

iwx_send_cmd_pdu(struct iwx_softc *sc, uint32_t id, uint32_t flags,

sys/dev/pci/if_iwx.c

5991

uint32_t *status)

sys/dev/pci/if_iwx.c

6022

iwx_send_cmd_pdu_status(struct iwx_softc *sc, uint32_t id, uint16_t len,

sys/dev/pci/if_iwx.c

6023

const void *data, uint32_t *status)

sys/dev/pci/if_iwx.c

6071

uint32_t

sys/dev/pci/if_iwx.c

6086

uint32_t

sys/dev/pci/if_iwx.c

6107

struct ieee80211_frame *wh, uint16_t *flags, uint32_t *rate_n_flags)

sys/dev/pci/if_iwx.c

6230

uint32_t rate_n_flags;

sys/dev/pci/if_iwx.c

6527

uint32_t status;

sys/dev/pci/if_iwx.c

6728

uint32_t status, aggsize;

sys/dev/pci/if_iwx.c

6729

const uint32_t max_aggsize = (IWX_STA_FLG_MAX_AGG_SIZE_1024K >>

sys/dev/pci/if_iwx.c

6941

uint32_t aggsize, mpdu_dens;

sys/dev/pci/if_iwx.c

6942

const uint32_t max_aggsize = (IWX_STA_FLG_MAX_AGG_SIZE_4M >>

sys/dev/pci/if_iwx.c

7180

int n_ssids, uint32_t channel_cfg_flags)

sys/dev/pci/if_iwx.c

7223

int n_ssids, uint32_t channel_cfg_flags)

sys/dev/pci/if_iwx.c

728

uint32_t major, uint32_t minor, uint32_t api)

sys/dev/pci/if_iwx.c

7433

uint32_t suspend_time, max_out_time;

sys/dev/pci/if_iwx.c

745

uint32_t size = 0;

sys/dev/pci/if_iwx.c

7478

uint32_t suspend_time, max_out_time;

sys/dev/pci/if_iwx.c

7552

struct iwx_scan_channel_params_v6 *cp, uint32_t channel_cfg_flags,

sys/dev/pci/if_iwx.c

7566

struct iwx_scan_channel_params_v7 *cp, uint32_t channel_cfg_flags,

sys/dev/pci/if_iwx.c

7592

uint32_t bitmap_ssid = 0;

sys/dev/pci/if_iwx.c

7652

uint32_t bitmap_ssid = 0;

sys/dev/pci/if_iwx.c

7834

struct iwx_mac_ctx_cmd *cmd, uint32_t action)

sys/dev/pci/if_iwx.c

7932

uint32_t dtim_off;

sys/dev/pci/if_iwx.c

7953

iwx_mac_ctxt_cmd(struct iwx_softc *sc, struct iwx_node *in, uint32_t action,

sys/dev/pci/if_iwx.c

7998

uint32_t action, int assoc)

sys/dev/pci/if_iwx.c

805

uint32_t base_reg, end_reg;

sys/dev/pci/if_iwx.c

8103

uint32_t version;

sys/dev/pci/if_iwx.c

827

uint32_t addr, val;

sys/dev/pci/if_iwx.c

8481

uint32_t cmd_id;

sys/dev/pci/if_iwx.c

8585

uint32_t cmd_id;

sys/dev/pci/if_iwx.c

8701

uint32_t rate_n_flags;

sys/dev/pci/if_iwx.c

8716

uint32_t mod_type = (rate_n_flags & IWX_RATE_MCS_MOD_TYPE_MSK);

sys/dev/pci/if_iwx.c

8746

uint32_t ridx = (rate_n_flags & IWX_RATE_LEGACY_RATE_MSK);

sys/dev/pci/if_iwx.c

8784

uint32_t cmd_id;

sys/dev/pci/if_iwx.c

8806

uint8_t chains_dynamic, uint32_t apply_time, uint8_t sco,

sys/dev/pci/if_iwx.c

885

uint32_t ltr_val = IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |

sys/dev/pci/if_iwx.c

8861

uint32_t duration;

sys/dev/pci/if_iwx.c

917

uint32_t control_flags = 0;

sys/dev/pci/if_iwx.c

9244

uint32_t flags = IWX_SEC_KEY_FLAG_CIPHER_CCMP;

sys/dev/pci/if_iwx.c

9294

uint32_t status;

sys/dev/pci/if_iwx.c

9682

static const uint32_t

sys/dev/pci/if_iwx.c

9710

static const uint32_t

sys/dev/pci/if_iwx.c

9824

uint32_t cmd_id, flags = 0;

sys/dev/pci/if_iwx.c

997

uint32_t control_flags, scratch_size;

sys/dev/pci/if_iwxreg.h

127

uint32_t control_flags;

sys/dev/pci/if_iwxreg.h

128

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

1496

uint32_t flow_trigger;

sys/dev/pci/if_iwxreg.h

1497

uint32_t event_trigger;

sys/dev/pci/if_iwxreg.h

1525

uint32_t cipher;

sys/dev/pci/if_iwxreg.h

1549

uint32_t ver; /* major/minor/API/serial */

sys/dev/pci/if_iwxreg.h

1552

uint32_t inst_size; /* bytes of runtime code */

sys/dev/pci/if_iwxreg.h

1553

uint32_t data_size; /* bytes of runtime data */

sys/dev/pci/if_iwxreg.h

1554

uint32_t init_size; /* bytes of init code */

sys/dev/pci/if_iwxreg.h

1555

uint32_t init_data_size; /* bytes of init data */

sys/dev/pci/if_iwxreg.h

1556

uint32_t boot_size; /* bytes of bootstrap code */

sys/dev/pci/if_iwxreg.h

1560

uint32_t build; /* build number */

sys/dev/pci/if_iwxreg.h

1561

uint32_t inst_size; /* bytes of runtime code */

sys/dev/pci/if_iwxreg.h

1562

uint32_t data_size; /* bytes of runtime data */

sys/dev/pci/if_iwxreg.h

1563

uint32_t init_size; /* bytes of init code */

sys/dev/pci/if_iwxreg.h

1564

uint32_t init_data_size; /* bytes of init data */

sys/dev/pci/if_iwxreg.h

1565

uint32_t boot_size; /* bytes of bootstrap code */

sys/dev/pci/if_iwxreg.h

1652

uint32_t type; /* see above */

sys/dev/pci/if_iwxreg.h

1653

uint32_t length; /* not including type/length fields */

sys/dev/pci/if_iwxreg.h

1658

uint32_t api_index;

sys/dev/pci/if_iwxreg.h

1659

uint32_t api_flags;

sys/dev/pci/if_iwxreg.h

1663

uint32_t api_index;

sys/dev/pci/if_iwxreg.h

1664

uint32_t api_capa;

sys/dev/pci/if_iwxreg.h

1676

uint32_t zero;

sys/dev/pci/if_iwxreg.h

1677

uint32_t magic;

sys/dev/pci/if_iwxreg.h

1679

uint32_t ver; /* major/minor/API/serial */

sys/dev/pci/if_iwxreg.h

1680

uint32_t build;

sys/dev/pci/if_iwxreg.h

1717

uint32_t unused;

sys/dev/pci/if_iwxreg.h

1772

uint32_t __pad;

sys/dev/pci/if_iwxreg.h

178

uint32_t core_dump_size;

sys/dev/pci/if_iwxreg.h

179

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

1888

uint32_t cb_size;

sys/dev/pci/if_iwxreg.h

189

uint32_t platform_nvm_size;

sys/dev/pci/if_iwxreg.h

190

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

201

uint32_t early_debug_size;

sys/dev/pci/if_iwxreg.h

202

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

2115

uint32_t cmd_queue;

sys/dev/pci/if_iwxreg.h

2123

uint32_t status;

sys/dev/pci/if_iwxreg.h

2131

uint32_t valid;

sys/dev/pci/if_iwxreg.h

2143

uint32_t flow_trigger;

sys/dev/pci/if_iwxreg.h

2144

uint32_t event_trigger;

sys/dev/pci/if_iwxreg.h

2174

uint32_t phy_cfg;

sys/dev/pci/if_iwxreg.h

2210

uint32_t num_temps;

sys/dev/pci/if_iwxreg.h

222

uint32_t reserved1[4];

sys/dev/pci/if_iwxreg.h

2248

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

2255

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

226

uint32_t reserved2[16];

sys/dev/pci/if_iwxreg.h

2272

uint32_t flags;

sys/dev/pci/if_iwxreg.h

228

uint32_t reserved3[16];

sys/dev/pci/if_iwxreg.h

2305

uint32_t mac_sku_flags;

sys/dev/pci/if_iwxreg.h

2314

uint32_t tx_chains;

sys/dev/pci/if_iwxreg.h

2315

uint32_t rx_chains;

sys/dev/pci/if_iwxreg.h

2328

uint32_t lar_enabled;

sys/dev/pci/if_iwxreg.h

2340

uint32_t lar_enabled;

sys/dev/pci/if_iwxreg.h

2341

uint32_t n_channels;

sys/dev/pci/if_iwxreg.h

2342

uint32_t channel_profile[IWX_NUM_CHANNELS];

sys/dev/pci/if_iwxreg.h

2378

uint32_t error_event_table_ptr; /* SRAM address for error log */

sys/dev/pci/if_iwxreg.h

2379

uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */

sys/dev/pci/if_iwxreg.h

2380

uint32_t cpu_register_ptr;

sys/dev/pci/if_iwxreg.h

2381

uint32_t dbgm_config_ptr;

sys/dev/pci/if_iwxreg.h

2382

uint32_t alive_counter_ptr;

sys/dev/pci/if_iwxreg.h

2383

uint32_t scd_base_ptr; /* SRAM address for SCD */

sys/dev/pci/if_iwxreg.h

2384

uint32_t st_fwrd_addr; /* pointer to Store and forward */

sys/dev/pci/if_iwxreg.h

2385

uint32_t st_fwrd_size;

sys/dev/pci/if_iwxreg.h

2389

uint32_t ucode_major;

sys/dev/pci/if_iwxreg.h

2390

uint32_t ucode_minor;

sys/dev/pci/if_iwxreg.h

2395

uint32_t timestamp;

sys/dev/pci/if_iwxreg.h

2400

uint32_t error_info_addr; /* SRAM address for UMAC error log */

sys/dev/pci/if_iwxreg.h

2401

uint32_t dbg_print_buff_addr;

sys/dev/pci/if_iwxreg.h

2405

uint32_t umac_major; /* UMAC version: major */

sys/dev/pci/if_iwxreg.h

2406

uint32_t umac_minor; /* UMAC version: minor */

sys/dev/pci/if_iwxreg.h

2418

uint32_t data[3];

sys/dev/pci/if_iwxreg.h

2431

uint32_t size;

sys/dev/pci/if_iwxreg.h

2432

uint32_t enabled;

sys/dev/pci/if_iwxreg.h

2463

uint32_t flags;

sys/dev/pci/if_iwxreg.h

2464

uint32_t latency;

sys/dev/pci/if_iwxreg.h

2484

uint32_t init_flags;

sys/dev/pci/if_iwxreg.h

2511

uint32_t error_type;

sys/dev/pci/if_iwxreg.h

2515

uint32_t error_service;

sys/dev/pci/if_iwxreg.h

2545

uint32_t addr;

sys/dev/pci/if_iwxreg.h

2546

uint32_t val;

sys/dev/pci/if_iwxreg.h

2574

uint32_t data_type;

sys/dev/pci/if_iwxreg.h

2575

uint32_t ofs;

sys/dev/pci/if_iwxreg.h

2576

uint32_t len;

sys/dev/pci/if_iwxreg.h

2600

uint32_t base_reg;

sys/dev/pci/if_iwxreg.h

2601

uint32_t end_reg;

sys/dev/pci/if_iwxreg.h

2602

uint32_t write_ptr_reg;

sys/dev/pci/if_iwxreg.h

2603

uint32_t wrap_count;

sys/dev/pci/if_iwxreg.h

2621

uint32_t cfg_reg;

sys/dev/pci/if_iwxreg.h

2622

uint32_t write_ptr_reg;

sys/dev/pci/if_iwxreg.h

2623

uint32_t wrap_count;

sys/dev/pci/if_iwxreg.h

2757

uint32_t id;

sys/dev/pci/if_iwxreg.h

2758

uint32_t vif_type;

sys/dev/pci/if_iwxreg.h

2759

uint32_t stop_conf_ids;

sys/dev/pci/if_iwxreg.h

2760

uint32_t stop_delay;

sys/dev/pci/if_iwxreg.h

2785

uint32_t stop_consec_missed_bcon;

sys/dev/pci/if_iwxreg.h

2786

uint32_t stop_consec_missed_bcon_since_rx;

sys/dev/pci/if_iwxreg.h

2787

uint32_t reserved2[2];

sys/dev/pci/if_iwxreg.h

2788

uint32_t start_consec_missed_bcon;

sys/dev/pci/if_iwxreg.h

2789

uint32_t start_consec_missed_bcon_since_rx;

sys/dev/pci/if_iwxreg.h

2790

uint32_t reserved1[2];

sys/dev/pci/if_iwxreg.h

2812

uint32_t stop_offset;

sys/dev/pci/if_iwxreg.h

2813

uint32_t stop_threshold;

sys/dev/pci/if_iwxreg.h

2814

uint32_t start_offset;

sys/dev/pci/if_iwxreg.h

2815

uint32_t start_threshold;

sys/dev/pci/if_iwxreg.h

2823

uint32_t rssi;

sys/dev/pci/if_iwxreg.h

2877

uint32_t command_queue;

sys/dev/pci/if_iwxreg.h

2878

uint32_t bss;

sys/dev/pci/if_iwxreg.h

2879

uint32_t softap;

sys/dev/pci/if_iwxreg.h

2880

uint32_t p2p_go;

sys/dev/pci/if_iwxreg.h

2881

uint32_t p2p_client;

sys/dev/pci/if_iwxreg.h

2882

uint32_t p2p_device;

sys/dev/pci/if_iwxreg.h

2883

uint32_t ibss;

sys/dev/pci/if_iwxreg.h

2884

uint32_t tdls;

sys/dev/pci/if_iwxreg.h

2885

uint32_t reserved[4];

sys/dev/pci/if_iwxreg.h

2898

uint32_t id;

sys/dev/pci/if_iwxreg.h

2899

uint32_t action_bitmap;

sys/dev/pci/if_iwxreg.h

2900

uint32_t status_bitmap;

sys/dev/pci/if_iwxreg.h

2940

uint32_t thrshold;

sys/dev/pci/if_iwxreg.h

2943

uint32_t window;

sys/dev/pci/if_iwxreg.h

2944

uint32_t reserved[4];

sys/dev/pci/if_iwxreg.h

2970

uint32_t reserved[2];

sys/dev/pci/if_iwxreg.h

316

uint32_t control_flags;

sys/dev/pci/if_iwxreg.h

317

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

3198

uint32_t id_and_color;

sys/dev/pci/if_iwxreg.h

3199

uint32_t action;

sys/dev/pci/if_iwxreg.h

3200

uint32_t id;

sys/dev/pci/if_iwxreg.h

3202

uint32_t apply_time;

sys/dev/pci/if_iwxreg.h

3203

uint32_t max_delay;

sys/dev/pci/if_iwxreg.h

3204

uint32_t depends_on;

sys/dev/pci/if_iwxreg.h

3205

uint32_t interval;

sys/dev/pci/if_iwxreg.h

3206

uint32_t duration;

sys/dev/pci/if_iwxreg.h

3220

uint32_t status;

sys/dev/pci/if_iwxreg.h

3221

uint32_t id;

sys/dev/pci/if_iwxreg.h

3222

uint32_t unique_id;

sys/dev/pci/if_iwxreg.h

3223

uint32_t id_and_color;

sys/dev/pci/if_iwxreg.h

3237

uint32_t timestamp;

sys/dev/pci/if_iwxreg.h

3238

uint32_t session_id;

sys/dev/pci/if_iwxreg.h

3239

uint32_t unique_id;

sys/dev/pci/if_iwxreg.h

3240

uint32_t id_and_color;

sys/dev/pci/if_iwxreg.h

3241

uint32_t action;

sys/dev/pci/if_iwxreg.h

3242

uint32_t status;

sys/dev/pci/if_iwxreg.h

328

uint32_t pnvm_size;

sys/dev/pci/if_iwxreg.h

329

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

3300

uint32_t id_and_color;

sys/dev/pci/if_iwxreg.h

3301

uint32_t action;

sys/dev/pci/if_iwxreg.h

3302

uint32_t conf_id;

sys/dev/pci/if_iwxreg.h

3303

uint32_t duration_tu;

sys/dev/pci/if_iwxreg.h

3304

uint32_t repetition_count;

sys/dev/pci/if_iwxreg.h

3305

uint32_t interval;

sys/dev/pci/if_iwxreg.h

3319

uint32_t mac_id;

sys/dev/pci/if_iwxreg.h

3320

uint32_t status;

sys/dev/pci/if_iwxreg.h

3321

uint32_t start;

sys/dev/pci/if_iwxreg.h

3322

uint32_t conf_id;

sys/dev/pci/if_iwxreg.h

333

uint32_t offset;

sys/dev/pci/if_iwxreg.h

3339

uint32_t id_and_color;

sys/dev/pci/if_iwxreg.h

3340

uint32_t action;

sys/dev/pci/if_iwxreg.h

3342

uint32_t macs[IWX_MAX_MACS_IN_BINDING];

sys/dev/pci/if_iwxreg.h

3343

uint32_t phy;

sys/dev/pci/if_iwxreg.h

3344

uint32_t lmac_id;

sys/dev/pci/if_iwxreg.h

3361

uint32_t id_and_color;

sys/dev/pci/if_iwxreg.h

3362

uint32_t quota;

sys/dev/pci/if_iwxreg.h

3363

uint32_t max_duration;

sys/dev/pci/if_iwxreg.h

3433

uint32_t channel;

sys/dev/pci/if_iwxreg.h

345

uint32_t hwm_size;

sys/dev/pci/if_iwxreg.h

346

uint32_t debug_token_config;

sys/dev/pci/if_iwxreg.h

3478

uint32_t id_and_color;

sys/dev/pci/if_iwxreg.h

3479

uint32_t action;

sys/dev/pci/if_iwxreg.h

3482

uint32_t lmac_id;

sys/dev/pci/if_iwxreg.h

3483

uint32_t rxchain_info;

sys/dev/pci/if_iwxreg.h

3484

uint32_t dsp_cfg_flags;

sys/dev/pci/if_iwxreg.h

3485

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

3489

uint32_t id_and_color;

sys/dev/pci/if_iwxreg.h

3490

uint32_t action;

sys/dev/pci/if_iwxreg.h

3493

uint32_t lmac_id;

sys/dev/pci/if_iwxreg.h

3494

uint32_t rxchain_info; /* reserved in _VER_4 */

sys/dev/pci/if_iwxreg.h

3495

uint32_t dsp_cfg_flags;

sys/dev/pci/if_iwxreg.h

3496

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

3524

uint32_t id_and_color;

sys/dev/pci/if_iwxreg.h

3525

uint32_t action;

sys/dev/pci/if_iwxreg.h

3527

uint32_t apply_time;

sys/dev/pci/if_iwxreg.h

3528

uint32_t tx_param_color;

sys/dev/pci/if_iwxreg.h

3530

uint32_t txchain_info;

sys/dev/pci/if_iwxreg.h

3531

uint32_t rxchain_info;

sys/dev/pci/if_iwxreg.h

3532

uint32_t acquisition_data;

sys/dev/pci/if_iwxreg.h

3533

uint32_t dsp_cfg_flags;

sys/dev/pci/if_iwxreg.h

3538

uint32_t id_and_color;

sys/dev/pci/if_iwxreg.h

3539

uint32_t action;

sys/dev/pci/if_iwxreg.h

3541

uint32_t apply_time;

sys/dev/pci/if_iwxreg.h

3542

uint32_t tx_param_color;

sys/dev/pci/if_iwxreg.h

3544

uint32_t txchain_info;

sys/dev/pci/if_iwxreg.h

3545

uint32_t rxchain_info;

sys/dev/pci/if_iwxreg.h

3546

uint32_t acquisition_data;

sys/dev/pci/if_iwxreg.h

3547

uint32_t dsp_cfg_flags;

sys/dev/pci/if_iwxreg.h

356

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

3604

uint32_t system_timestamp;

sys/dev/pci/if_iwxreg.h

3606

uint32_t beacon_time_stamp;

sys/dev/pci/if_iwxreg.h

3610

uint32_t non_cfg_phy[IWX_RX_INFO_PHY_CNT];

sys/dev/pci/if_iwxreg.h

3611

uint32_t rate_n_flags;

sys/dev/pci/if_iwxreg.h

3612

uint32_t byte_count;

sys/dev/pci/if_iwxreg.h

366

uint32_t size;

sys/dev/pci/if_iwxreg.h

367

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

3725

uint32_t filter_match;

sys/dev/pci/if_iwxreg.h

3726

uint32_t phy_data3;

sys/dev/pci/if_iwxreg.h

3729

uint32_t rss_hash;

sys/dev/pci/if_iwxreg.h

3730

uint32_t phy_data2;

sys/dev/pci/if_iwxreg.h

3732

uint32_t partial_hash; /* ip/tcp header hash w/o some fields */

sys/dev/pci/if_iwxreg.h

3735

uint32_t rate_n_flags;

sys/dev/pci/if_iwxreg.h

3740

uint32_t gp2_on_air_rise;

sys/dev/pci/if_iwxreg.h

3747

uint32_t tsf_on_air_rise0;

sys/dev/pci/if_iwxreg.h

3748

uint32_t tsf_on_air_rise1;

sys/dev/pci/if_iwxreg.h

3752

uint32_t phy_data0;

sys/dev/pci/if_iwxreg.h

3755

uint32_t phy_data1;

sys/dev/pci/if_iwxreg.h

3758

uint32_t reserved[2];

sys/dev/pci/if_iwxreg.h

3764

uint32_t rss_hash;

sys/dev/pci/if_iwxreg.h

3765

uint32_t phy_data2;

sys/dev/pci/if_iwxreg.h

3768

uint32_t filter_match;

sys/dev/pci/if_iwxreg.h

3769

uint32_t phy_data3;

sys/dev/pci/if_iwxreg.h

3771

uint32_t rate_n_flags;

sys/dev/pci/if_iwxreg.h

3776

uint32_t gp2_on_air_rise;

sys/dev/pci/if_iwxreg.h

3779

uint32_t tsf_on_air_rise0;

sys/dev/pci/if_iwxreg.h

3780

uint32_t tsf_on_air_rise1;

sys/dev/pci/if_iwxreg.h

3783

uint32_t phy_data0;

sys/dev/pci/if_iwxreg.h

3784

uint32_t phy_data1;

sys/dev/pci/if_iwxreg.h

3810

uint32_t status;

sys/dev/pci/if_iwxreg.h

3811

uint32_t reorder_data;

sys/dev/pci/if_iwxreg.h

3856

uint32_t sta_tid;

sys/dev/pci/if_iwxreg.h

3857

uint32_t ba_info;

sys/dev/pci/if_iwxreg.h

3868

uint32_t radio_flavor;

sys/dev/pci/if_iwxreg.h

3869

uint32_t radio_step;

sys/dev/pci/if_iwxreg.h

3870

uint32_t radio_dash;

sys/dev/pci/if_iwxreg.h

3887

uint32_t flags;

sys/dev/pci/if_iwxreg.h

3901

uint32_t mac_id;

sys/dev/pci/if_iwxreg.h

3902

uint32_t consec_missed_beacons_since_last_rx;

sys/dev/pci/if_iwxreg.h

3903

uint32_t consec_missed_beacons;

sys/dev/pci/if_iwxreg.h

3904

uint32_t num_expected_beacons;

sys/dev/pci/if_iwxreg.h

3905

uint32_t num_recvd_beacons;

sys/dev/pci/if_iwxreg.h

3917

uint32_t installed_ver;

sys/dev/pci/if_iwxreg.h

3918

uint32_t external_ver;

sys/dev/pci/if_iwxreg.h

3919

uint32_t status;

sys/dev/pci/if_iwxreg.h

3920

uint32_t duration;

sys/dev/pci/if_iwxreg.h

395

uint32_t reserved[12];

sys/dev/pci/if_iwxreg.h

3963

uint32_t burst_check;

sys/dev/pci/if_iwxreg.h

3964

uint32_t burst_count;

sys/dev/pci/if_iwxreg.h

3965

uint32_t wait_for_silence_timeout_cnt;

sys/dev/pci/if_iwxreg.h

3966

uint32_t reserved[3];

sys/dev/pci/if_iwxreg.h

3970

uint32_t tx_on_a;

sys/dev/pci/if_iwxreg.h

3971

uint32_t tx_on_b;

sys/dev/pci/if_iwxreg.h

3972

uint32_t exec_time;

sys/dev/pci/if_iwxreg.h

3973

uint32_t probe_time;

sys/dev/pci/if_iwxreg.h

3974

uint32_t rssi_ant;

sys/dev/pci/if_iwxreg.h

3975

uint32_t reserved2;

sys/dev/pci/if_iwxreg.h

3979

uint32_t hi_priority_tx_req_cnt;

sys/dev/pci/if_iwxreg.h

3980

uint32_t hi_priority_tx_denied_cnt;

sys/dev/pci/if_iwxreg.h

3981

uint32_t lo_priority_tx_req_cnt;

sys/dev/pci/if_iwxreg.h

3982

uint32_t lo_priority_tx_denied_cnt;

sys/dev/pci/if_iwxreg.h

3983

uint32_t hi_priority_rx_req_cnt;

sys/dev/pci/if_iwxreg.h

3984

uint32_t hi_priority_rx_denied_cnt;

sys/dev/pci/if_iwxreg.h

3985

uint32_t lo_priority_rx_req_cnt;

sys/dev/pci/if_iwxreg.h

3986

uint32_t lo_priority_rx_denied_cnt;

sys/dev/pci/if_iwxreg.h

3990

uint32_t radio_temperature;

sys/dev/pci/if_iwxreg.h

3992

uint32_t sleep_time;

sys/dev/pci/if_iwxreg.h

3993

uint32_t slots_out;

sys/dev/pci/if_iwxreg.h

3994

uint32_t slots_idle;

sys/dev/pci/if_iwxreg.h

3995

uint32_t ttl_timestamp;

sys/dev/pci/if_iwxreg.h

3997

uint32_t rx_enable_counter;

sys/dev/pci/if_iwxreg.h

4003

uint32_t num_of_sos_states;

sys/dev/pci/if_iwxreg.h

4004

uint32_t beacon_filtered;

sys/dev/pci/if_iwxreg.h

4005

uint32_t missed_beacons;

sys/dev/pci/if_iwxreg.h

4010

uint32_t beacon_filter_delta_time;

sys/dev/pci/if_iwxreg.h

4019

uint32_t bogus_cts; /* CTS received when not expecting CTS */

sys/dev/pci/if_iwxreg.h

4020

uint32_t bogus_ack; /* ACK received when not expecting ACK */

sys/dev/pci/if_iwxreg.h

4021

uint32_t non_bssid_frames; /* number of frames with BSSID that

sys/dev/pci/if_iwxreg.h

4023

uint32_t filtered_frames; /* count frames that were dumped in the

sys/dev/pci/if_iwxreg.h

4025

uint32_t non_channel_beacons; /* beacons with our bss id but not on

sys/dev/pci/if_iwxreg.h

4027

uint32_t channel_beacons; /* beacons with our bss id and in our

sys/dev/pci/if_iwxreg.h

4029

uint32_t num_missed_bcon; /* number of missed beacons */

sys/dev/pci/if_iwxreg.h

4030

uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the

sys/dev/pci/if_iwxreg.h

4032

uint32_t ina_detection_search_time;/* total time (in 0.8us) searched

sys/dev/pci/if_iwxreg.h

4034

uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */

sys/dev/pci/if_iwxreg.h

4035

uint32_t interference_data_flag; /* flag for interference data

sys/dev/pci/if_iwxreg.h

4038

uint32_t channel_load; /* counts RX Enable time in uSec */

sys/dev/pci/if_iwxreg.h

4039

uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM

sys/dev/pci/if_iwxreg.h

4041

uint32_t beacon_rssi_a;

sys/dev/pci/if_iwxreg.h

4042

uint32_t beacon_rssi_b;

sys/dev/pci/if_iwxreg.h

4043

uint32_t beacon_rssi_c;

sys/dev/pci/if_iwxreg.h

4044

uint32_t beacon_energy_a;

sys/dev/pci/if_iwxreg.h

4045

uint32_t beacon_energy_b;

sys/dev/pci/if_iwxreg.h

4046

uint32_t beacon_energy_c;

sys/dev/pci/if_iwxreg.h

4047

uint32_t num_bt_kills;

sys/dev/pci/if_iwxreg.h

4048

uint32_t mac_id;

sys/dev/pci/if_iwxreg.h

4049

uint32_t directed_data_mpdu;

sys/dev/pci/if_iwxreg.h

4053

uint32_t ina_cnt;

sys/dev/pci/if_iwxreg.h

4054

uint32_t fina_cnt;

sys/dev/pci/if_iwxreg.h

4055

uint32_t plcp_err;

sys/dev/pci/if_iwxreg.h

4056

uint32_t crc32_err;

sys/dev/pci/if_iwxreg.h

4057

uint32_t overrun_err;

sys/dev/pci/if_iwxreg.h

4058

uint32_t early_overrun_err;

sys/dev/pci/if_iwxreg.h

4059

uint32_t crc32_good;

sys/dev/pci/if_iwxreg.h

4060

uint32_t false_alarm_cnt;

sys/dev/pci/if_iwxreg.h

4061

uint32_t fina_sync_err_cnt;

sys/dev/pci/if_iwxreg.h

4062

uint32_t sfd_timeout;

sys/dev/pci/if_iwxreg.h

4063

uint32_t fina_timeout;

sys/dev/pci/if_iwxreg.h

4064

uint32_t unresponded_rts;

sys/dev/pci/if_iwxreg.h

4065

uint32_t rxe_frame_limit_overrun;

sys/dev/pci/if_iwxreg.h

4066

uint32_t sent_ack_cnt;

sys/dev/pci/if_iwxreg.h

4067

uint32_t sent_cts_cnt;

sys/dev/pci/if_iwxreg.h

4068

uint32_t sent_ba_rsp_cnt;

sys/dev/pci/if_iwxreg.h

4069

uint32_t dsp_self_kill;

sys/dev/pci/if_iwxreg.h

407

uint32_t boot_stage_mirror;

sys/dev/pci/if_iwxreg.h

4070

uint32_t mh_format_err;

sys/dev/pci/if_iwxreg.h

4071

uint32_t re_acq_main_rssi_sum;

sys/dev/pci/if_iwxreg.h

4072

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

4076

uint32_t plcp_err;

sys/dev/pci/if_iwxreg.h

4077

uint32_t overrun_err;

sys/dev/pci/if_iwxreg.h

4078

uint32_t early_overrun_err;

sys/dev/pci/if_iwxreg.h

4079

uint32_t crc32_good;

sys/dev/pci/if_iwxreg.h

408

uint32_t ipc_status_mirror;

sys/dev/pci/if_iwxreg.h

4080

uint32_t crc32_err;

sys/dev/pci/if_iwxreg.h

4081

uint32_t mh_format_err;

sys/dev/pci/if_iwxreg.h

4082

uint32_t agg_crc32_good;

sys/dev/pci/if_iwxreg.h

4083

uint32_t agg_mpdu_cnt;

sys/dev/pci/if_iwxreg.h

4084

uint32_t agg_cnt;

sys/dev/pci/if_iwxreg.h

4085

uint32_t unsupport_mcs;

sys/dev/pci/if_iwxreg.h

409

uint32_t sleep_notif;

sys/dev/pci/if_iwxreg.h

410

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

4101

uint32_t ba_timeout;

sys/dev/pci/if_iwxreg.h

4102

uint32_t ba_reschedule_frames;

sys/dev/pci/if_iwxreg.h

4103

uint32_t scd_query_agg_frame_cnt;

sys/dev/pci/if_iwxreg.h

4104

uint32_t scd_query_no_agg;

sys/dev/pci/if_iwxreg.h

4105

uint32_t scd_query_agg;

sys/dev/pci/if_iwxreg.h

4106

uint32_t scd_query_mismatch;

sys/dev/pci/if_iwxreg.h

4107

uint32_t frame_not_ready;

sys/dev/pci/if_iwxreg.h

4108

uint32_t underrun;

sys/dev/pci/if_iwxreg.h

4109

uint32_t bt_prio_kill;

sys/dev/pci/if_iwxreg.h

4110

uint32_t rx_ba_rsp_cnt;

sys/dev/pci/if_iwxreg.h

4113

uint32_t reserved2;

sys/dev/pci/if_iwxreg.h

4117

uint32_t ext_cca_narrow_ch20[1];

sys/dev/pci/if_iwxreg.h

4118

uint32_t ext_cca_narrow_ch40[2];

sys/dev/pci/if_iwxreg.h

4119

uint32_t ext_cca_narrow_ch80[3];

sys/dev/pci/if_iwxreg.h

4120

uint32_t ext_cca_narrow_ch160[4];

sys/dev/pci/if_iwxreg.h

4121

uint32_t last_tx_ch_width_indx;

sys/dev/pci/if_iwxreg.h

4122

uint32_t rx_detected_per_ch_width[4];

sys/dev/pci/if_iwxreg.h

4123

uint32_t success_per_ch_width[4];

sys/dev/pci/if_iwxreg.h

4124

uint32_t fail_per_ch_width[4];

sys/dev/pci/if_iwxreg.h

4128

uint32_t preamble_cnt;

sys/dev/pci/if_iwxreg.h

4129

uint32_t rx_detected_cnt;

sys/dev/pci/if_iwxreg.h

4130

uint32_t bt_prio_defer_cnt;

sys/dev/pci/if_iwxreg.h

4131

uint32_t bt_prio_kill_cnt;

sys/dev/pci/if_iwxreg.h

4132

uint32_t few_bytes_cnt;

sys/dev/pci/if_iwxreg.h

4133

uint32_t cts_timeout;

sys/dev/pci/if_iwxreg.h

4134

uint32_t ack_timeout;

sys/dev/pci/if_iwxreg.h

4135

uint32_t expected_ack_cnt;

sys/dev/pci/if_iwxreg.h

4136

uint32_t actual_ack_cnt;

sys/dev/pci/if_iwxreg.h

4137

uint32_t dump_msdu_cnt;

sys/dev/pci/if_iwxreg.h

4138

uint32_t burst_abort_next_frame_mismatch_cnt;

sys/dev/pci/if_iwxreg.h

4139

uint32_t burst_abort_missing_next_frame_cnt;

sys/dev/pci/if_iwxreg.h

4140

uint32_t cts_timeout_collision;

sys/dev/pci/if_iwxreg.h

4141

uint32_t ack_or_ba_timeout_collision;

sys/dev/pci/if_iwxreg.h

4148

uint32_t beacon_counter[IWX_MAC_INDEX_AUX];

sys/dev/pci/if_iwxreg.h

4184

uint32_t air_time[IWX_MAC_INDEX_AUX];

sys/dev/pci/if_iwxreg.h

4185

uint32_t byte_count[IWX_MAC_INDEX_AUX];

sys/dev/pci/if_iwxreg.h

4186

uint32_t pkt_count[IWX_MAC_INDEX_AUX];

sys/dev/pci/if_iwxreg.h

4191

uint32_t flag;

sys/dev/pci/if_iwxreg.h

4220

uint32_t flags;

sys/dev/pci/if_iwxreg.h

4261

uint32_t cfg_mask;

sys/dev/pci/if_iwxreg.h

4262

uint32_t config_time_sec;

sys/dev/pci/if_iwxreg.h

4263

uint32_t type_id_mask;

sys/dev/pci/if_iwxreg.h

4316

uint32_t beacon_filter_average_energy;

sys/dev/pci/if_iwxreg.h

4317

uint32_t air_time;

sys/dev/pci/if_iwxreg.h

4318

uint32_t beacon_counter;

sys/dev/pci/if_iwxreg.h

4319

uint32_t beacon_average_energy;

sys/dev/pci/if_iwxreg.h

4320

uint32_t beacon_rssi_a;

sys/dev/pci/if_iwxreg.h

4321

uint32_t beacon_rssi_b;

sys/dev/pci/if_iwxreg.h

4322

uint32_t rx_bytes;

sys/dev/pci/if_iwxreg.h

4338

uint32_t rx_action;

sys/dev/pci/if_iwxreg.h

4339

uint32_t tx_action;

sys/dev/pci/if_iwxreg.h

4340

uint32_t cca_defers;

sys/dev/pci/if_iwxreg.h

4341

uint32_t beacon_filtered;

sys/dev/pci/if_iwxreg.h

4358

uint32_t beacon_filter_average_energy;

sys/dev/pci/if_iwxreg.h

4359

uint32_t air_time;

sys/dev/pci/if_iwxreg.h

4360

uint32_t beacon_counter;

sys/dev/pci/if_iwxreg.h

4361

uint32_t beacon_average_energy;

sys/dev/pci/if_iwxreg.h

4362

uint32_t beacon_rssi_a;

sys/dev/pci/if_iwxreg.h

4363

uint32_t beacon_rssi_b;

sys/dev/pci/if_iwxreg.h

4364

uint32_t rx_bytes;

sys/dev/pci/if_iwxreg.h

4386

uint32_t channel_load;

sys/dev/pci/if_iwxreg.h

4387

uint32_t channel_load_by_us;

sys/dev/pci/if_iwxreg.h

4388

uint32_t channel_load_not_by_us;

sys/dev/pci/if_iwxreg.h

4389

uint32_t clt;

sys/dev/pci/if_iwxreg.h

4390

uint32_t act;

sys/dev/pci/if_iwxreg.h

4391

uint32_t elp;

sys/dev/pci/if_iwxreg.h

4392

uint32_t rx_detected_per_ch_width[IWX_STATS_MAX_BW_INDEX];

sys/dev/pci/if_iwxreg.h

4393

uint32_t success_per_ch_width[IWX_STATS_MAX_BW_INDEX];

sys/dev/pci/if_iwxreg.h

4394

uint32_t fail_per_ch_width[IWX_STATS_MAX_BW_INDEX];

sys/dev/pci/if_iwxreg.h

4395

uint32_t last_tx_ch_width_indx;

sys/dev/pci/if_iwxreg.h

4407

uint32_t average_energy;

sys/dev/pci/if_iwxreg.h

4425

uint32_t time_stamp;

sys/dev/pci/if_iwxreg.h

4439

uint32_t time_stamp;

sys/dev/pci/if_iwxreg.h

4441

uint32_t per_phy_crc_error_stats[IWX_STATS_MAX_PHY_OPERATIONAL];

sys/dev/pci/if_iwxreg.h

4450

uint32_t time_stamp;

sys/dev/pci/if_iwxreg.h

4518

uint32_t state;

sys/dev/pci/if_iwxreg.h

4519

uint32_t watermark[IWX_SF_TRANSIENT_STATES_NUMBER];

sys/dev/pci/if_iwxreg.h

4520

uint32_t long_delay_timeouts[IWX_SF_NUM_SCENARIO][IWX_SF_NUM_TIMEOUT_TYPES];

sys/dev/pci/if_iwxreg.h

4521

uint32_t full_on_timeouts[IWX_SF_NUM_SCENARIO][IWX_SF_NUM_TIMEOUT_TYPES];

sys/dev/pci/if_iwxreg.h

460

uint32_t config;

sys/dev/pci/if_iwxreg.h

4602

uint32_t beacon_time;

sys/dev/pci/if_iwxreg.h

4604

uint32_t bi;

sys/dev/pci/if_iwxreg.h

4605

uint32_t bi_reciprocal;

sys/dev/pci/if_iwxreg.h

4606

uint32_t dtim_interval;

sys/dev/pci/if_iwxreg.h

4607

uint32_t dtim_reciprocal;

sys/dev/pci/if_iwxreg.h

4608

uint32_t mcast_qid;

sys/dev/pci/if_iwxreg.h

4609

uint32_t beacon_template;

sys/dev/pci/if_iwxreg.h

4621

uint32_t beacon_time;

sys/dev/pci/if_iwxreg.h

4623

uint32_t bi;

sys/dev/pci/if_iwxreg.h

4624

uint32_t bi_reciprocal;

sys/dev/pci/if_iwxreg.h

4625

uint32_t beacon_template;

sys/dev/pci/if_iwxreg.h

4659

uint32_t is_assoc;

sys/dev/pci/if_iwxreg.h

4660

uint32_t dtim_time;

sys/dev/pci/if_iwxreg.h

4662

uint32_t bi;

sys/dev/pci/if_iwxreg.h

4663

uint32_t reserved1;

sys/dev/pci/if_iwxreg.h

4664

uint32_t dtim_interval;

sys/dev/pci/if_iwxreg.h

4665

uint32_t data_policy;

sys/dev/pci/if_iwxreg.h

4666

uint32_t listen_interval;

sys/dev/pci/if_iwxreg.h

4667

uint32_t assoc_id;

sys/dev/pci/if_iwxreg.h

4668

uint32_t assoc_beacon_arrive_time;

sys/dev/pci/if_iwxreg.h

4680

uint32_t ctwin;

sys/dev/pci/if_iwxreg.h

4681

uint32_t opp_ps_enabled;

sys/dev/pci/if_iwxreg.h

4692

uint32_t ctwin;

sys/dev/pci/if_iwxreg.h

4700

uint32_t stats_interval;

sys/dev/pci/if_iwxreg.h

4714

uint32_t is_disc_extended;

sys/dev/pci/if_iwxreg.h

4799

uint32_t id_and_color;

sys/dev/pci/if_iwxreg.h

4800

uint32_t action;

sys/dev/pci/if_iwxreg.h

4802

uint32_t mac_type;

sys/dev/pci/if_iwxreg.h

4803

uint32_t tsf_id;

sys/dev/pci/if_iwxreg.h

4808

uint32_t cck_rates;

sys/dev/pci/if_iwxreg.h

4809

uint32_t ofdm_rates;

sys/dev/pci/if_iwxreg.h

4810

uint32_t protection_flags;

sys/dev/pci/if_iwxreg.h

4811

uint32_t cck_short_preamble;

sys/dev/pci/if_iwxreg.h

4812

uint32_t short_slot;

sys/dev/pci/if_iwxreg.h

4813

uint32_t filter_flags;

sys/dev/pci/if_iwxreg.h

4815

uint32_t qos_flags;

sys/dev/pci/if_iwxreg.h

483

uint32_t prph_scratch_size;

sys/dev/pci/if_iwxreg.h

484

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

4854

uint32_t ctwin;

sys/dev/pci/if_iwxreg.h

4868

uint32_t is_disc_extended;

sys/dev/pci/if_iwxreg.h

4912

uint32_t id_and_color;

sys/dev/pci/if_iwxreg.h

4913

uint32_t action;

sys/dev/pci/if_iwxreg.h

4915

uint32_t mac_type;

sys/dev/pci/if_iwxreg.h

4918

uint32_t filter_flags;

sys/dev/pci/if_iwxreg.h

4921

uint32_t eht_support;

sys/dev/pci/if_iwxreg.h

4922

uint32_t nic_not_ack_enabled;

sys/dev/pci/if_iwxreg.h

5067

uint32_t action;

sys/dev/pci/if_iwxreg.h

5068

uint32_t link_id;

sys/dev/pci/if_iwxreg.h

5069

uint32_t mac_id;

sys/dev/pci/if_iwxreg.h

5070

uint32_t phy_id;

sys/dev/pci/if_iwxreg.h

5073

uint32_t modify_mask;

sys/dev/pci/if_iwxreg.h

5074

uint32_t active;

sys/dev/pci/if_iwxreg.h

5075

uint32_t listen_lmac;

sys/dev/pci/if_iwxreg.h

5076

uint32_t cck_rates;

sys/dev/pci/if_iwxreg.h

5077

uint32_t ofdm_rates;

sys/dev/pci/if_iwxreg.h

5078

uint32_t cck_short_preamble;

sys/dev/pci/if_iwxreg.h

5079

uint32_t short_slot;

sys/dev/pci/if_iwxreg.h

5080

uint32_t protection_flags;

sys/dev/pci/if_iwxreg.h

5082

uint32_t qos_flags;

sys/dev/pci/if_iwxreg.h

5089

uint32_t bi;

sys/dev/pci/if_iwxreg.h

5090

uint32_t dtim_interval;

sys/dev/pci/if_iwxreg.h

5093

uint32_t flags;

sys/dev/pci/if_iwxreg.h

5094

uint32_t flags_mask;

sys/dev/pci/if_iwxreg.h

5104

uint32_t reserved1[8];

sys/dev/pci/if_iwxreg.h

5194

uint32_t sta_id;

sys/dev/pci/if_iwxreg.h

5195

uint32_t link_id;

sys/dev/pci/if_iwxreg.h

5200

uint32_t station_type;

sys/dev/pci/if_iwxreg.h

5201

uint32_t assoc_id;

sys/dev/pci/if_iwxreg.h

5202

uint32_t beamform_flags;

sys/dev/pci/if_iwxreg.h

5203

uint32_t mfp;

sys/dev/pci/if_iwxreg.h

5204

uint32_t mimo;

sys/dev/pci/if_iwxreg.h

5205

uint32_t mimo_protection;

sys/dev/pci/if_iwxreg.h

5206

uint32_t ack_enabled;

sys/dev/pci/if_iwxreg.h

5207

uint32_t trig_rnd_alloc;

sys/dev/pci/if_iwxreg.h

5208

uint32_t tx_ampdu_spacing;

sys/dev/pci/if_iwxreg.h

5209

uint32_t tx_ampdu_max_size;

sys/dev/pci/if_iwxreg.h

5210

uint32_t sp_length;

sys/dev/pci/if_iwxreg.h

5211

uint32_t uapsd_acs;

sys/dev/pci/if_iwxreg.h

5213

uint32_t htc_flags;

sys/dev/pci/if_iwxreg.h

5258

uint32_t sta_id;

sys/dev/pci/if_iwxreg.h

5259

uint32_t link_id;

sys/dev/pci/if_iwxreg.h

5264

uint32_t station_type;

sys/dev/pci/if_iwxreg.h

5265

uint32_t assoc_id;

sys/dev/pci/if_iwxreg.h

5266

uint32_t beamform_flags;

sys/dev/pci/if_iwxreg.h

5267

uint32_t mfp;

sys/dev/pci/if_iwxreg.h

5268

uint32_t mimo;

sys/dev/pci/if_iwxreg.h

5269

uint32_t mimo_protection;

sys/dev/pci/if_iwxreg.h

5270

uint32_t ack_enabled;

sys/dev/pci/if_iwxreg.h

5271

uint32_t trig_rnd_alloc;

sys/dev/pci/if_iwxreg.h

5272

uint32_t tx_ampdu_spacing;

sys/dev/pci/if_iwxreg.h

5273

uint32_t tx_ampdu_max_size;

sys/dev/pci/if_iwxreg.h

5274

uint32_t sp_length;

sys/dev/pci/if_iwxreg.h

5275

uint32_t uapsd_acs;

sys/dev/pci/if_iwxreg.h

5277

uint32_t htc_flags;

sys/dev/pci/if_iwxreg.h

5295

uint32_t sta_id;

sys/dev/pci/if_iwxreg.h

5298

static inline uint32_t iwx_reciprocal(uint32_t v)

sys/dev/pci/if_iwxreg.h

5339

uint32_t flags;

sys/dev/pci/if_iwxreg.h

5340

uint32_t static_long;

sys/dev/pci/if_iwxreg.h

5341

uint32_t static_short;

sys/dev/pci/if_iwxreg.h

5342

uint32_t ltr_cfg_values[IWX_LTR_VALID_STATES_NUM];

sys/dev/pci/if_iwxreg.h

5343

uint32_t ltr_short_idle_timeout;

sys/dev/pci/if_iwxreg.h

5449

uint32_t id_and_color;

sys/dev/pci/if_iwxreg.h

5454

uint32_t rx_data_timeout;

sys/dev/pci/if_iwxreg.h

5455

uint32_t tx_data_timeout;

sys/dev/pci/if_iwxreg.h

5456

uint32_t rx_data_timeout_uapsd;

sys/dev/pci/if_iwxreg.h

5457

uint32_t tx_data_timeout_uapsd;

sys/dev/pci/if_iwxreg.h

5480

uint32_t rxtimeout;

sys/dev/pci/if_iwxreg.h

5481

uint32_t txtimeout;

sys/dev/pci/if_iwxreg.h

5521

uint32_t sta_id;

sys/dev/pci/if_iwxreg.h

5575

uint32_t bf_energy_delta;

sys/dev/pci/if_iwxreg.h

5576

uint32_t bf_roaming_energy_delta;

sys/dev/pci/if_iwxreg.h

5577

uint32_t bf_roaming_state;

sys/dev/pci/if_iwxreg.h

5578

uint32_t bf_temp_threshold;

sys/dev/pci/if_iwxreg.h

5579

uint32_t bf_temp_fast_filter;

sys/dev/pci/if_iwxreg.h

5580

uint32_t bf_temp_slow_filter;

sys/dev/pci/if_iwxreg.h

5581

uint32_t bf_enable_beacon_filter;

sys/dev/pci/if_iwxreg.h

5582

uint32_t bf_debug_flag;

sys/dev/pci/if_iwxreg.h

5583

uint32_t bf_escape_timer;

sys/dev/pci/if_iwxreg.h

5584

uint32_t ba_escape_timer;

sys/dev/pci/if_iwxreg.h

5585

uint32_t ba_enable_beacon_abort;

sys/dev/pci/if_iwxreg.h

5586

uint32_t bf_threshold_absolute_low[2];

sys/dev/pci/if_iwxreg.h

5587

uint32_t bf_threshold_absolute_high[2];

sys/dev/pci/if_iwxreg.h

6133

uint32_t rx_chain_info;

sys/dev/pci/if_iwxreg.h

6134

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

6151

uint32_t chain_a_sad_mode;

sys/dev/pci/if_iwxreg.h

6152

uint32_t chain_b_sad_mode;

sys/dev/pci/if_iwxreg.h

6153

uint32_t mac_id;

sys/dev/pci/if_iwxreg.h

6154

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

6166

uint32_t phy_id;

sys/dev/pci/if_iwxreg.h

6196

uint32_t sta_id_mask;

sys/dev/pci/if_iwxreg.h

6210

uint32_t old_sta_id_mask;

sys/dev/pci/if_iwxreg.h

6211

uint32_t new_sta_id_mask;

sys/dev/pci/if_iwxreg.h

6212

uint32_t tid;

sys/dev/pci/if_iwxreg.h

6220

uint32_t baid;

sys/dev/pci/if_iwxreg.h

6229

uint32_t sta_id_mask;

sys/dev/pci/if_iwxreg.h

6230

uint32_t tid;

sys/dev/pci/if_iwxreg.h

6238

uint32_t action;

sys/dev/pci/if_iwxreg.h

6252

uint32_t baid;

sys/dev/pci/if_iwxreg.h

6283

uint32_t operation;

sys/dev/pci/if_iwxreg.h

6286

uint32_t sta_mask;

sys/dev/pci/if_iwxreg.h

6289

uint32_t flags;

sys/dev/pci/if_iwxreg.h

6290

uint32_t cb_size;

sys/dev/pci/if_iwxreg.h

6295

uint32_t sta_mask;

sys/dev/pci/if_iwxreg.h

6296

uint32_t tid;

sys/dev/pci/if_iwxreg.h

6299

uint32_t old_sta_mask;

sys/dev/pci/if_iwxreg.h

6300

uint32_t tid;

sys/dev/pci/if_iwxreg.h

6301

uint32_t new_sta_mask;

sys/dev/pci/if_iwxreg.h

6354

uint32_t action;

sys/dev/pci/if_iwxreg.h

6357

uint32_t sta_mask;

sys/dev/pci/if_iwxreg.h

6358

uint32_t key_id;

sys/dev/pci/if_iwxreg.h

6359

uint32_t key_flags;

sys/dev/pci/if_iwxreg.h

6367

uint32_t old_sta_mask;

sys/dev/pci/if_iwxreg.h

6368

uint32_t new_sta_mask;

sys/dev/pci/if_iwxreg.h

6369

uint32_t key_id;

sys/dev/pci/if_iwxreg.h

6370

uint32_t key_flags;

sys/dev/pci/if_iwxreg.h

6373

uint32_t sta_mask;

sys/dev/pci/if_iwxreg.h

6374

uint32_t key_id;

sys/dev/pci/if_iwxreg.h

6375

uint32_t key_flags;

sys/dev/pci/if_iwxreg.h

6525

uint32_t max_tx_op;

sys/dev/pci/if_iwxreg.h

6579

uint32_t flags;

sys/dev/pci/if_iwxreg.h

6580

uint32_t rate;

sys/dev/pci/if_iwxreg.h

6581

uint32_t amsdu_size;

sys/dev/pci/if_iwxreg.h

6582

uint32_t amsdu_enabled;

sys/dev/pci/if_iwxreg.h

6690

uint32_t pn_low;

sys/dev/pci/if_iwxreg.h

6726

uint32_t flags;

sys/dev/pci/if_iwxreg.h

6728

uint32_t rate_n_flags;

sys/dev/pci/if_iwxreg.h

6748

uint32_t offload_assist;

sys/dev/pci/if_iwxreg.h

6750

uint32_t rate_n_flags;

sys/dev/pci/if_iwxreg.h

682

uint32_t reserved1;

sys/dev/pci/if_iwxreg.h

6924

uint32_t initial_rate;

sys/dev/pci/if_iwxreg.h

6934

uint32_t tfd_info;

sys/dev/pci/if_iwxreg.h

6982

uint32_t initial_rate;

sys/dev/pci/if_iwxreg.h

6993

uint32_t tfd_info;

sys/dev/pci/if_iwxreg.h

7076

uint32_t flags;

sys/dev/pci/if_iwxreg.h

7081

uint32_t query_byte_cnt;

sys/dev/pci/if_iwxreg.h

7086

uint32_t wireless_time;

sys/dev/pci/if_iwxreg.h

7087

uint32_t tx_rate;

sys/dev/pci/if_iwxreg.h

7098

uint32_t ibss_mgr_status;

sys/dev/pci/if_iwxreg.h

7115

uint32_t queues_ctl;

sys/dev/pci/if_iwxreg.h

7127

uint32_t sta_id;

sys/dev/pci/if_iwxreg.h

7172

static inline uint32_t iwx_get_scd_ssn(struct iwx_tx_resp *tx_resp)

sys/dev/pci/if_iwxreg.h

7174

return le32_to_cpup((uint32_t *)&tx_resp->status +

sys/dev/pci/if_iwxreg.h

7274

uint32_t tx_flags;

sys/dev/pci/if_iwxreg.h

7275

uint32_t rate_n_flags;

sys/dev/pci/if_iwxreg.h

7292

uint32_t flags;

sys/dev/pci/if_iwxreg.h

7295

uint32_t iter_interval;

sys/dev/pci/if_iwxreg.h

7383

uint32_t time_after_last_iter;

sys/dev/pci/if_iwxreg.h

7384

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

7401

uint32_t duration;

sys/dev/pci/if_iwxreg.h

7553

uint32_t tx_chains;

sys/dev/pci/if_iwxreg.h

7554

uint32_t rx_chains;

sys/dev/pci/if_iwxreg.h

7576

uint32_t flags;

sys/dev/pci/if_iwxreg.h

7577

uint32_t tx_chains;

sys/dev/pci/if_iwxreg.h

7578

uint32_t rx_chains;

sys/dev/pci/if_iwxreg.h

7579

uint32_t legacy_rates;

sys/dev/pci/if_iwxreg.h

7580

uint32_t out_of_channel_time[IWX_SCAN_TWO_LMACS];

sys/dev/pci/if_iwxreg.h

7581

uint32_t suspend_time[IWX_SCAN_TWO_LMACS];

sys/dev/pci/if_iwxreg.h

7681

uint32_t flags;

sys/dev/pci/if_iwxreg.h

7708

uint32_t flags;

sys/dev/pci/if_iwxreg.h

7813

uint32_t flags;

sys/dev/pci/if_iwxreg.h

7814

uint32_t uid;

sys/dev/pci/if_iwxreg.h

7815

uint32_t ooc_priority;

sys/dev/pci/if_iwxreg.h

7826

uint32_t max_out_time;

sys/dev/pci/if_iwxreg.h

7827

uint32_t suspend_time;

sys/dev/pci/if_iwxreg.h

7828

uint32_t scan_priority;

sys/dev/pci/if_iwxreg.h

7837

uint32_t max_out_time[2];

sys/dev/pci/if_iwxreg.h

7838

uint32_t suspend_time[2];

sys/dev/pci/if_iwxreg.h

7839

uint32_t scan_priority;

sys/dev/pci/if_iwxreg.h

7851

uint32_t max_out_time[2];

sys/dev/pci/if_iwxreg.h

7852

uint32_t suspend_time[2];

sys/dev/pci/if_iwxreg.h

7853

uint32_t scan_priority;

sys/dev/pci/if_iwxreg.h

7864

uint32_t max_out_time[2];

sys/dev/pci/if_iwxreg.h

7865

uint32_t suspend_time[2];

sys/dev/pci/if_iwxreg.h

7866

uint32_t scan_priority;

sys/dev/pci/if_iwxreg.h

7879

uint32_t max_out_time[2];

sys/dev/pci/if_iwxreg.h

7880

uint32_t suspend_time[2];

sys/dev/pci/if_iwxreg.h

7881

uint32_t scan_priority;

sys/dev/pci/if_iwxreg.h

7928

uint32_t max_out_of_time[IWX_SCAN_TWO_LMACS];

sys/dev/pci/if_iwxreg.h

7929

uint32_t suspend_time[IWX_SCAN_TWO_LMACS];

sys/dev/pci/if_iwxreg.h

7930

uint32_t scan_priority;

sys/dev/pci/if_iwxreg.h

7984

uint32_t short_ssid[IWX_SCAN_SHORT_SSID_MAX_SIZE];

sys/dev/pci/if_iwxreg.h

8009

uint32_t uid;

sys/dev/pci/if_iwxreg.h

8010

uint32_t ooc_priority;

sys/dev/pci/if_iwxreg.h

8049

uint32_t max_out_of_time[IWX_SCAN_TWO_LMACS];

sys/dev/pci/if_iwxreg.h

8050

uint32_t suspend_time[IWX_SCAN_TWO_LMACS];

sys/dev/pci/if_iwxreg.h

8051

uint32_t scan_priority;

sys/dev/pci/if_iwxreg.h

8095

uint32_t uid;

sys/dev/pci/if_iwxreg.h

8096

uint32_t ooc_priority;

sys/dev/pci/if_iwxreg.h

8106

uint32_t uid;

sys/dev/pci/if_iwxreg.h

8107

uint32_t flags;

sys/dev/pci/if_iwxreg.h

8121

uint32_t uid;

sys/dev/pci/if_iwxreg.h

8126

uint32_t time_from_last_iter;

sys/dev/pci/if_iwxreg.h

8127

uint32_t reserved;

sys/dev/pci/if_iwxreg.h

8163

uint32_t matched_profiles;

sys/dev/pci/if_iwxreg.h

8164

uint32_t last_scan_age;

sys/dev/pci/if_iwxreg.h

8165

uint32_t n_scans_done;

sys/dev/pci/if_iwxreg.h

8166

uint32_t gp2_d0u;

sys/dev/pci/if_iwxreg.h

8167

uint32_t gp2_invoked;

sys/dev/pci/if_iwxreg.h

8187

uint32_t uid;

sys/dev/pci/if_iwxreg.h

8192

uint32_t tsf_low;

sys/dev/pci/if_iwxreg.h

8193

uint32_t tsf_high;

sys/dev/pci/if_iwxreg.h

8446

uint32_t mac_id_n_color;

sys/dev/pci/if_iwxreg.h

8452

uint32_t station_flags;

sys/dev/pci/if_iwxreg.h

8453

uint32_t station_flags_msk;

sys/dev/pci/if_iwxreg.h

8462

uint32_t tfd_queue_msk;

sys/dev/pci/if_iwxreg.h

8564

uint32_t ctrl_flags;

sys/dev/pci/if_iwxreg.h

8568

uint32_t key_id;

sys/dev/pci/if_iwxreg.h

8569

uint32_t sta_id;

sys/dev/pci/if_iwxreg.h

8583

uint32_t ctrl_flags;

sys/dev/pci/if_iwxreg.h

8585

uint32_t key_id;

sys/dev/pci/if_iwxreg.h

8586

uint32_t sta_id;

sys/dev/pci/if_iwxreg.h

8601

uint32_t mac_id_n_color;

sys/dev/pci/if_iwxreg.h

8634

uint32_t mode;

sys/dev/pci/if_iwxreg.h

8635

uint32_t enabled_modules;

sys/dev/pci/if_iwxreg.h

8659

uint32_t key;

sys/dev/pci/if_iwxreg.h

8660

uint32_t reserved2[5];

sys/dev/pci/if_iwxreg.h

8680

uint32_t status;

sys/dev/pci/if_iwxreg.h

8686

uint32_t n_channels;

sys/dev/pci/if_iwxreg.h

8687

uint32_t channels[0];

sys/dev/pci/if_iwxreg.h

8708

uint32_t status;

sys/dev/pci/if_iwxreg.h

8715

uint32_t n_channels;

sys/dev/pci/if_iwxreg.h

8716

uint32_t channels[];

sys/dev/pci/if_iwxreg.h

8745

uint32_t status;

sys/dev/pci/if_iwxreg.h

8752

uint32_t n_channels;

sys/dev/pci/if_iwxreg.h

8753

uint32_t channels[0];

sys/dev/pci/if_iwxreg.h

8815

iwx_cmd_opcode(uint32_t cmdid)

sys/dev/pci/if_iwxreg.h

8821

iwx_cmd_groupid(uint32_t cmdid)

sys/dev/pci/if_iwxreg.h

8827

iwx_cmd_version(uint32_t cmdid)

sys/dev/pci/if_iwxreg.h

8832

static inline uint32_t

sys/dev/pci/if_iwxreg.h

8905

uint32_t len_n_flags;

sys/dev/pci/if_iwxreg.h

8918

static uint32_t

sys/dev/pci/if_iwxreg.h

8925

static uint32_t

sys/dev/pci/if_iwxvar.h

153

uint32_t fws_len;

sys/dev/pci/if_iwxvar.h

154

uint32_t fws_devoff;

sys/dev/pci/if_iwxvar.h

212

uint32_t _rx_page_order;

sys/dev/pci/if_iwxvar.h

215

uint32_t flags;

sys/dev/pci/if_iwxvar.h

218

uint32_t id;

sys/dev/pci/if_iwxvar.h

296

uint32_t uc_lmac_error_event_table[2];

sys/dev/pci/if_iwxvar.h

297

uint32_t uc_umac_error_event_table;

sys/dev/pci/if_iwxvar.h

298

uint32_t uc_log_event_table;

sys/dev/pci/if_iwxvar.h

334

uint32_t ref;

sys/dev/pci/if_iwxvar.h

390

uint32_t rx_pkt_status;

sys/dev/pci/if_iwxvar.h

393

uint32_t rate_n_flags;

sys/dev/pci/if_iwxvar.h

394

uint32_t device_timestamp;

sys/dev/pci/if_iwxvar.h

448

uint32_t start_tidmask;

sys/dev/pci/if_iwxvar.h

449

uint32_t stop_tidmask;

sys/dev/pci/if_iwxvar.h

714

uint32_t sc_sku_id[3];

sys/dev/pci/if_iwxvar.h

715

uint32_t mac_addr_from_csr;

sys/dev/pci/if_iwxvar.h

724

uint32_t pnvm_size;

sys/dev/pci/if_iwxvar.h

726

uint32_t sc_pnvm_ver;

sys/dev/pci/if_iwxvar.h

753

uint32_t sc_fh_init_mask;

sys/dev/pci/if_iwxvar.h

754

uint32_t sc_hw_init_mask;

sys/dev/pci/if_iwxvar.h

755

uint32_t sc_fh_mask;

sys/dev/pci/if_iwxvar.h

756

uint32_t sc_hw_mask;

sys/dev/pci/if_iwxvar.h

796

uint32_t sc_time_event_uid;

sys/dev/pci/if_iwxvar.h

857

#define IWX_ICT_COUNT (IWX_ICT_SIZE / sizeof (uint32_t))

sys/dev/pci/if_ix.c

1033

ixgbe_enable_queue(struct ix_softc *sc, uint32_t vector)

sys/dev/pci/if_ix.c

1036

uint32_t mask;

sys/dev/pci/if_ix.c

1062

ixgbe_disable_queue(struct ix_softc *sc, uint32_t vector)

sys/dev/pci/if_ix.c

1065

uint32_t mask;

sys/dev/pci/if_ix.c

1146

uint32_t reg_eicr, mod_mask, msf_mask;

sys/dev/pci/if_ix.c

1447

uint32_t olinfo_status = 0, cmd_type_len;

sys/dev/pci/if_ix.c

1535

uint32_t fctrl;

sys/dev/pci/if_ix.c

158

void ixgbe_rx_offload(uint32_t, uint16_t, struct mbuf *);

sys/dev/pci/if_ix.c

1583

ixgbe_mc_array_itr(struct ixgbe_hw *hw, uint8_t **update_ptr, uint32_t *vmdq)

sys/dev/pci/if_ix.c

168

ixgbe_tx_ctx_setup(struct ix_txring *, struct mbuf *, uint32_t *,

sys/dev/pci/if_ix.c

169

uint32_t *);

sys/dev/pci/if_ix.c

1702

uint32_t reg;

sys/dev/pci/if_ix.c

172

uint8_t *ixgbe_mc_array_itr(struct ixgbe_hw *, uint8_t **, uint32_t *);

sys/dev/pci/if_ix.c

183

void ixgbe_enable_queue(struct ix_softc *, uint32_t);

sys/dev/pci/if_ix.c

185

void ixgbe_disable_queue(struct ix_softc *, uint32_t);

sys/dev/pci/if_ix.c

2048

uint32_t autoneg, err = 0;

sys/dev/pci/if_ix.c

2375

uint32_t txctrl;

sys/dev/pci/if_ix.c

2376

uint32_t hlreg;

sys/dev/pci/if_ix.c

2429

uint32_t dmatxctl, rttdcs;

sys/dev/pci/if_ix.c

249

uint32_t ctrl_ext;

sys/dev/pci/if_ix.c

2514

ixgbe_tx_offload(struct mbuf *mp, uint32_t *vlan_macip_lens,

sys/dev/pci/if_ix.c

2515

uint32_t *type_tucmd_mlhl, uint32_t *olinfo_status, uint32_t *cmd_type_len,

sys/dev/pci/if_ix.c

2516

uint32_t *mss_l4len_idx)

sys/dev/pci/if_ix.c

2560

uint32_t hdrlen, thlen, paylen, outlen;

sys/dev/pci/if_ix.c

2588

uint32_t *cmd_type_len, uint32_t *olinfo_status)

sys/dev/pci/if_ix.c

2592

uint32_t vlan_macip_lens = 0, type_tucmd_mlhl = 0;

sys/dev/pci/if_ix.c

2593

uint32_t mss_l4len_idx = 0;

sys/dev/pci/if_ix.c

2602

uint32_t vtag = mp->m_pkthdr.ether_vtag;

sys/dev/pci/if_ix.c

2915

uint32_t bufsz, fctrl, srrctl, rxcsum, rdrxctl;

sys/dev/pci/if_ix.c

2916

uint32_t hlreg;

sys/dev/pci/if_ix.c

2989

uint32_t psrtype = IXGBE_PSRTYPE_TCPHDR |

sys/dev/pci/if_ix.c

3021

uint32_t reta = 0, mrqc, rss_key[10];

sys/dev/pci/if_ix.c

3052

reta = reta | ( ((uint32_t) queue_id) << 24);

sys/dev/pci/if_ix.c

3154

uint32_t staterr = 0;

sys/dev/pci/if_ix.c

3165

uint32_t hash;

sys/dev/pci/if_ix.c

3316

ixgbe_rx_offload(uint32_t staterr, uint16_t vtag, struct mbuf *m)

sys/dev/pci/if_ix.c

3369

uint32_t paylen;

sys/dev/pci/if_ix.c

3407

uint32_t ctrl;

sys/dev/pci/if_ix.c

3446

uint32_t mask, fwsm;

sys/dev/pci/if_ix.c

3513

ixgbe_read_pci_cfg(struct ixgbe_hw *hw, uint32_t reg)

sys/dev/pci/if_ix.c

3516

uint32_t value;

sys/dev/pci/if_ix.c

3533

ixgbe_write_pci_cfg(struct ixgbe_hw *hw, uint32_t reg, uint16_t value)

sys/dev/pci/if_ix.c

3536

uint32_t rv;

sys/dev/pci/if_ix.c

3549

rv = (rv & 0xffff) | ((uint32_t)value << 16);

sys/dev/pci/if_ix.c

3564

uint32_t ivar, index;

sys/dev/pci/if_ix.c

3577

ivar &= ~((uint32_t)0xFF << (8 * (entry & 0x3)));

sys/dev/pci/if_ix.c

3578

ivar |= ((uint32_t)vector << (8 * (entry & 0x3)));

sys/dev/pci/if_ix.c

3590

ivar &= ~((uint32_t)0xFF << index);

sys/dev/pci/if_ix.c

3591

ivar |= ((uint32_t)vector << index);

sys/dev/pci/if_ix.c

3596

ivar &= ~((uint32_t)0xFF << index);

sys/dev/pci/if_ix.c

3597

ivar |= ((uint32_t)vector << index);

sys/dev/pci/if_ix.c

3610

uint32_t newitr;

sys/dev/pci/if_ix.c

3636

uint32_t err;

sys/dev/pci/if_ix.c

3662

uint32_t autoneg;

sys/dev/pci/if_ix.c

373

uint32_t ctrl_ext;

sys/dev/pci/if_ix.c

3741

uint32_t reg;

sys/dev/pci/if_ix.c

3971

uint32_t reg = ixc->reg;

sys/dev/pci/if_ix.c

4013

uint32_t i = rxr->me;

sys/dev/pci/if_ix.c

4040

uint32_t i = txr->me;

sys/dev/pci/if_ix.c

405

uint32_t ctrl_ext;

sys/dev/pci/if_ix.c

4061

uint32_t r;

sys/dev/pci/if_ix.c

609

uint32_t swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/pci/if_ix.c

750

uint32_t k, txdctl, rxdctl, rxctrl, mhadd, itr;

sys/dev/pci/if_ix.c

934

uint32_t gpie;

sys/dev/pci/if_ix.c

990

uint32_t rxpb, frame, size, tmp;

sys/dev/pci/if_ix.h

113

#define IXGBE_TX_BUFFER_SIZE ((uint32_t) 1514)

sys/dev/pci/if_ix.h

126

uint32_t eop_index;

sys/dev/pci/if_ix.h

155

uint32_t msix; /* This queue's MSIX vector */

sys/dev/pci/if_ix.h

156

uint32_t eims; /* This queue's EIMS bit */

sys/dev/pci/if_ix.h

157

uint32_t eitr_setting;

sys/dev/pci/if_ix.h

171

uint32_t me;

sys/dev/pci/if_ix.h

172

uint32_t tail;

sys/dev/pci/if_ix.h

173

uint32_t watchdog_timer;

sys/dev/pci/if_ix.h

177

uint32_t next_avail_desc;

sys/dev/pci/if_ix.h

178

uint32_t next_to_clean;

sys/dev/pci/if_ix.h

184

uint32_t txd_cmd;

sys/dev/pci/if_ix.h

197

uint32_t me;

sys/dev/pci/if_ix.h

198

uint32_t tail;

sys/dev/pci/if_ix.h

240

uint32_t shadow_vfta[IXGBE_VFTA_SIZE];

sys/dev/pci/if_ix.h

244

uint32_t fc; /* local flow ctrl setting */

sys/dev/pci/if_ix.h

247

uint32_t link_speed;

sys/dev/pci/if_ix.h

250

uint32_t linkvec;

sys/dev/pci/if_ix.h

254

uint32_t rx_mbuf_sz;

sys/dev/pci/if_ixgb.c

1599

uint32_t raidc;

sys/dev/pci/if_ixgb.c

1895

uint32_t ctrl;

sys/dev/pci/if_ixgb.c

1905

uint32_t val;

sys/dev/pci/if_ixgb.c

438

uint32_t temp_reg;

sys/dev/pci/if_ixl.c

1093

uint32_t crc;

sys/dev/pci/if_ixl.c

1124

uint32_t key[13];

sys/dev/pci/if_ixl.c

1128

uint32_t entries[128 / sizeof(uint32_t)];

sys/dev/pci/if_ixl.c

1132

uint32_t entries[512 / sizeof(uint32_t)];

sys/dev/pci/if_ixl.c

1324

static int ixl_sff_get_byte(struct ixl_softc *, uint8_t, uint32_t,

sys/dev/pci/if_ixl.c

1326

static int ixl_sff_set_byte(struct ixl_softc *, uint8_t, uint32_t,

sys/dev/pci/if_ixl.c

1463

#define ixl_dmamem_hi(_ixm) (uint32_t)(IXL_DMA_DVA(_ixm) >> 32)

sys/dev/pci/if_ixl.c

1468

#define ixl_dmamem_lo(_ixm) (uint32_t)IXL_DMA_DVA(_ixm)

sys/dev/pci/if_ixl.c

1493

uint32_t (*ic_rd_ctl)(struct ixl_softc *, uint32_t);

sys/dev/pci/if_ixl.c

1494

void (*ic_wr_ctl)(struct ixl_softc *, uint32_t,

sys/dev/pci/if_ixl.c

1495

uint32_t);

sys/dev/pci/if_ixl.c

1509

static inline uint32_t

sys/dev/pci/if_ixl.c

1510

ixl_rd_ctl(struct ixl_softc *sc, uint32_t r)

sys/dev/pci/if_ixl.c

1516

ixl_wr_ctl(struct ixl_softc *sc, uint32_t r, uint32_t v)

sys/dev/pci/if_ixl.c

1535

static uint32_t ixl_710_rd_ctl(struct ixl_softc *, uint32_t);

sys/dev/pci/if_ixl.c

1536

static void ixl_710_wr_ctl(struct ixl_softc *, uint32_t, uint32_t);

sys/dev/pci/if_ixl.c

1552

static uint32_t ixl_722_rd_ctl(struct ixl_softc *, uint32_t);

sys/dev/pci/if_ixl.c

1553

static void ixl_722_wr_ctl(struct ixl_softc *, uint32_t, uint32_t);

sys/dev/pci/if_ixl.c

159

uint32_t iaq_param[4];

sys/dev/pci/if_ixl.c

1642

uint32_t port, ari, func, val;

sys/dev/pci/if_ixl.c

2194

uint32_t v = ixl_rd_ctl(sc, I40E_PFQF_CTL_0);

sys/dev/pci/if_ixl.c

2239

uint32_t reg;

sys/dev/pci/if_ixl.c

2466

uint32_t reg;

sys/dev/pci/if_ixl.c

257

uint32_t number;

sys/dev/pci/if_ixl.c

258

uint32_t logical_id;

sys/dev/pci/if_ixl.c

259

uint32_t phys_id;

sys/dev/pci/if_ixl.c

2625

uint32_t r;

sys/dev/pci/if_ixl.c

2702

uint32_t reg;

sys/dev/pci/if_ixl.c

2720

uint32_t reg;

sys/dev/pci/if_ixl.c

3123

uint32_t reg;

sys/dev/pci/if_ixl.c

3141

uint32_t reg;

sys/dev/pci/if_ixl.c

344

uint32_t phy_type;

sys/dev/pci/if_ixl.c

3464

uint32_t icr;

sys/dev/pci/if_ixl.c

356

uint32_t eeer_val;

sys/dev/pci/if_ixl.c

3792

uint32_t fwbuild, fwver, apiver;

sys/dev/pci/if_ixl.c

416

uint32_t addr_hi;

sys/dev/pci/if_ixl.c

417

uint32_t addr_lo;

sys/dev/pci/if_ixl.c

425

uint32_t addr_hi;

sys/dev/pci/if_ixl.c

426

uint32_t addr_lo;

sys/dev/pci/if_ixl.c

4286

ixl_sff_get_byte(struct ixl_softc *sc, uint8_t dev, uint32_t reg, uint8_t *p)

sys/dev/pci/if_ixl.c

4327

ixl_sff_set_byte(struct ixl_softc *sc, uint8_t dev, uint32_t reg, uint8_t v)

sys/dev/pci/if_ixl.c

436

uint32_t _reserved;

sys/dev/pci/if_ixl.c

444

uint32_t addr_hi;

sys/dev/pci/if_ixl.c

445

uint32_t addr_lo;

sys/dev/pci/if_ixl.c

4638

uint32_t count;

sys/dev/pci/if_ixl.c

4639

uint32_t minsize;

sys/dev/pci/if_ixl.c

464

uint32_t addr_hi;

sys/dev/pci/if_ixl.c

465

uint32_t addr_lo;

sys/dev/pci/if_ixl.c

4739

uint32_t count;

sys/dev/pci/if_ixl.c

4926

uint32_t num_queues, base_queue;

sys/dev/pci/if_ixl.c

4927

uint32_t num_pf_int;

sys/dev/pci/if_ixl.c

4928

uint32_t num_vf_int;

sys/dev/pci/if_ixl.c

4929

uint32_t num_vfs;

sys/dev/pci/if_ixl.c

4930

uint32_t i, j;

sys/dev/pci/if_ixl.c

4931

uint32_t val;

sys/dev/pci/if_ixl.c

4979

uint32_t abs_queue_idx = base_queue + i;

sys/dev/pci/if_ixl.c

4980

uint32_t reg_block = 0;

sys/dev/pci/if_ixl.c

5011

uint32_t cnt = 0;

sys/dev/pci/if_ixl.c

5012

uint32_t cnt1 = 0;

sys/dev/pci/if_ixl.c

5013

uint32_t reg = 0;

sys/dev/pci/if_ixl.c

5014

uint32_t grst_del;

sys/dev/pci/if_ixl.c

5078

static uint32_t

sys/dev/pci/if_ixl.c

5079

ixl_710_rd_ctl(struct ixl_softc *sc, uint32_t r)

sys/dev/pci/if_ixl.c

5102

ixl_710_wr_ctl(struct ixl_softc *sc, uint32_t r, uint32_t v)

sys/dev/pci/if_ixl.c

5145

static uint32_t

sys/dev/pci/if_ixl.c

5146

ixl_722_rd_ctl(struct ixl_softc *sc, uint32_t r)

sys/dev/pci/if_ixl.c

5152

ixl_722_wr_ctl(struct ixl_softc *sc, uint32_t r, uint32_t v)

sys/dev/pci/if_ixl.c

516

uint32_t ingress_table;

sys/dev/pci/if_ixl.c

519

uint32_t egress_table;

sys/dev/pci/if_ixl.c

5222

uint32_t c_base;

sys/dev/pci/if_ixl.c

5354

uint32_t index;

sys/dev/pci/if_ixl.c

5427

const struct ixl_counter *counters, size_t n, uint32_t index)

sys/dev/pci/if_ixl.c

564

uint32_t outer_up_table; /* same as ingress/egress tables */

sys/dev/pci/if_ixl.c

592

uint32_t reserved[2];

sys/dev/pci/if_ixl.c

639

uint32_t reg;

sys/dev/pci/if_ixl.c

640

uint32_t val;

sys/dev/pci/if_ixl.c

641

uint32_t _reserved2;

sys/dev/pci/if_ixl.c

739

uint32_t addr_hi;

sys/dev/pci/if_ixl.c

740

uint32_t addr_lo;

sys/dev/pci/if_ixl.c

750

uint32_t addr_hi;

sys/dev/pci/if_ixl.c

751

uint32_t addr_lo;

sys/dev/pci/if_ixl.c

850

uint32_t filter_status;

sys/dev/pci/if_ixl.c

946

uint32_t atq_len_enable;

sys/dev/pci/if_ixl.c

947

uint32_t atq_tail_mask;

sys/dev/pci/if_ixl.c

948

uint32_t atq_head_mask;

sys/dev/pci/if_ixl.c

950

uint32_t arq_len_enable;

sys/dev/pci/if_ixl.c

951

uint32_t arq_tail_mask;

sys/dev/pci/if_ixl.c

952

uint32_t arq_head_mask;

sys/dev/pci/if_ixl.c

987

uint32_t hmc_count;

sys/dev/pci/if_ixl.c

988

uint32_t hmc_size;

sys/dev/pci/if_ixv.c

1038

uint32_t ctrl, vid, vfta, retry;

sys/dev/pci/if_ixv.c

1096

uint32_t mask;

sys/dev/pci/if_ixv.c

1141

uint32_t ivar, index;

sys/dev/pci/if_ixv.c

1347

uint32_t reg;

sys/dev/pci/if_ixv.c

1518

uint32_t reg = ixc->reg;

sys/dev/pci/if_ixv.c

1544

uint32_t i = rxr->me;

sys/dev/pci/if_ixv.c

1563

uint32_t i = txr->me;

sys/dev/pci/if_ixv.c

169

uint32_t reg;

sys/dev/pci/if_ixv.c

434

uint32_t mask;

sys/dev/pci/if_ixv.c

534

ixv_enable_queue(struct ix_softc *sc, uint32_t vector)

sys/dev/pci/if_ixv.c

537

uint32_t queue = 1 << vector;

sys/dev/pci/if_ixv.c

538

uint32_t mask;

sys/dev/pci/if_ixv.c

545

ixv_disable_queue(struct ix_softc *sc, uint32_t vector)

sys/dev/pci/if_ixv.c

549

uint32_t mask;

sys/dev/pci/if_ixv.c

694

ixv_mc_array_itr(struct ixgbe_hw *hw, uint8_t **update_ptr, uint32_t *vmdq)

sys/dev/pci/if_ixv.c

835

uint32_t txctrl, txdctl;

sys/dev/pci/if_ixv.c

84

static uint8_t *ixv_mc_array_itr(struct ixgbe_hw *, uint8_t **, uint32_t *);

sys/dev/pci/if_ixv.c

886

uint32_t reta = 0, mrqc, rss_key[10];

sys/dev/pci/if_ixv.c

914

reta |= ((uint32_t)queue_id) << 24;

sys/dev/pci/if_ixv.c

947

uint32_t reg, rxdctl, bufsz, psrtype;

sys/dev/pci/if_jme.c

1063

uint32_t gpr, pmcs;

sys/dev/pci/if_jme.c

1109

uint32_t cflags;

sys/dev/pci/if_jme.c

1339

uint32_t ghc, rxmac, txmac, txpause, gp1;

sys/dev/pci/if_jme.c

143

uint32_t val;

sys/dev/pci/if_jme.c

1442

uint32_t status;

sys/dev/pci/if_jme.c

1498

uint32_t status;

sys/dev/pci/if_jme.c

1590

uint32_t flags, status;

sys/dev/pci/if_jme.c

1788

uint32_t reg;

sys/dev/pci/if_jme.c

2076

uint32_t reg;

sys/dev/pci/if_jme.c

2097

uint32_t reg;

sys/dev/pci/if_jme.c

2239

uint32_t reg;

sys/dev/pci/if_jme.c

2255

uint32_t crc;

sys/dev/pci/if_jme.c

2256

uint32_t mchash[2];

sys/dev/pci/if_jme.c

2257

uint32_t rxcfg;

sys/dev/pci/if_jme.c

363

uint32_t reg;

sys/dev/pci/if_jme.c

379

reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;

sys/dev/pci/if_jme.c

403

uint32_t offset;

sys/dev/pci/if_jme.c

446

uint32_t par0, par1;

sys/dev/pci/if_jme.c

464

uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES];

sys/dev/pci/if_jme.c

525

CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]);

sys/dev/pci/if_jme.c

526

CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]);

sys/dev/pci/if_jme.c

527

CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]);

sys/dev/pci/if_jme.c

528

CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]);

sys/dev/pci/if_jme.c

542

uint32_t reg;

sys/dev/pci/if_jmereg.h

882

uint32_t dw0;

sys/dev/pci/if_jmereg.h

883

uint32_t dw1;

sys/dev/pci/if_jmereg.h

884

uint32_t dw2;

sys/dev/pci/if_jmereg.h

885

uint32_t dw3;

sys/dev/pci/if_jmereg.h

886

uint32_t dw4;

sys/dev/pci/if_jmereg.h

887

uint32_t dw5;

sys/dev/pci/if_jmereg.h

888

uint32_t dw6;

sys/dev/pci/if_jmereg.h

889

uint32_t dw7;

sys/dev/pci/if_jmereg.h

894

uint32_t flags;

sys/dev/pci/if_jmereg.h

895

uint32_t buflen;

sys/dev/pci/if_jmereg.h

896

uint32_t addr_hi;

sys/dev/pci/if_jmereg.h

897

uint32_t addr_lo;

sys/dev/pci/if_jmevar.h

186

uint32_t jme_tx_dma_size;

sys/dev/pci/if_jmevar.h

187

uint32_t jme_rx_dma_size;

sys/dev/pci/if_jmevar.h

189

uint32_t jme_caps;

sys/dev/pci/if_jmevar.h

196

uint32_t jme_workaround;

sys/dev/pci/if_jmevar.h

200

uint32_t jme_flags;

sys/dev/pci/if_jmevar.h

209

uint32_t jme_txcsr;

sys/dev/pci/if_jmevar.h

210

uint32_t jme_rxcsr;

sys/dev/pci/if_lii.c

110

int (*sc_memread)(struct lii_softc *, uint32_t,

sys/dev/pci/if_lii.c

111

uint32_t *);

sys/dev/pci/if_lii.c

1110

uint32_t hashes[2];

sys/dev/pci/if_lii.c

1111

uint32_t crc, val;

sys/dev/pci/if_lii.c

137

int lii_eeprom_read(struct lii_softc *, uint32_t, uint32_t *);

sys/dev/pci/if_lii.c

139

int lii_spi_read(struct lii_softc *, uint32_t, uint32_t *);

sys/dev/pci/if_lii.c

335

uint32_t val;

sys/dev/pci/if_lii.c

346

lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val)

sys/dev/pci/if_lii.c

422

lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val)

sys/dev/pci/if_lii.c

424

uint32_t v;

sys/dev/pci/if_lii.c

453

uint32_t offset = 0x100;

sys/dev/pci/if_lii.c

454

uint32_t val, val1, addr0 = 0, addr1 = 0;

sys/dev/pci/if_lii.c

509

uint32_t val;

sys/dev/pci/if_lii.c

540

uint32_t val;

sys/dev/pci/if_lii.c

570

uint32_t val;

sys/dev/pci/if_lii.c

612

uint32_t val;

sys/dev/pci/if_lii.c

845

uint32_t status;

sys/dev/pci/if_mcx.c

1078

uint32_t create_qp_start_hint; /* 24 bits */

sys/dev/pci/if_mcx.c

1093

uint32_t device_frequency_mhz;

sys/dev/pci/if_mcx.c

1094

uint32_t device_frequency_khz;

sys/dev/pci/if_mcx.c

1117

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1130

uint32_t cmd_field_select;

sys/dev/pci/if_mcx.c

1139

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1155

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1160

uint32_t vp_min_wqe_inline_mode;

sys/dev/pci/if_mcx.c

1162

uint32_t vp_mtu;

sys/dev/pci/if_mcx.c

1211

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1232

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1246

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1247

uint32_t cmd_uar;

sys/dev/pci/if_mcx.c

1261

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1263

uint32_t cmd_resd_lkey;

sys/dev/pci/if_mcx.c

1267

uint32_t eq_status;

sys/dev/pci/if_mcx.c

1280

uint32_t eq_reserved1;

sys/dev/pci/if_mcx.c

1281

uint32_t eq_page_offset;

sys/dev/pci/if_mcx.c

1283

uint32_t eq_uar_size;

sys/dev/pci/if_mcx.c

1286

uint32_t eq_reserved2;

sys/dev/pci/if_mcx.c

1289

uint32_t eq_log_page_size;

sys/dev/pci/if_mcx.c

1291

uint32_t eq_reserved4[3];

sys/dev/pci/if_mcx.c

1292

uint32_t eq_consumer_counter;

sys/dev/pci/if_mcx.c

1293

uint32_t eq_producer_counter;

sys/dev/pci/if_mcx.c

1295

uint32_t eq_reserved5[4];

sys/dev/pci/if_mcx.c

1324

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1325

uint32_t cmd_eqn;

sys/dev/pci/if_mcx.c

1333

uint32_t cmd_eqn;

sys/dev/pci/if_mcx.c

1340

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1351

uint32_t eq_event_data[7];

sys/dev/pci/if_mcx.c

1370

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1371

uint32_t cmd_pd;

sys/dev/pci/if_mcx.c

1385

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1386

uint32_t cmd_tdomain;

sys/dev/pci/if_mcx.c

1399

uint32_t cmd_disp_type;

sys/dev/pci/if_mcx.c

1404

uint32_t cmd_lro;

sys/dev/pci/if_mcx.c

1406

uint32_t cmd_inline_rqn;

sys/dev/pci/if_mcx.c

1407

uint32_t cmd_indir_table;

sys/dev/pci/if_mcx.c

1408

uint32_t cmd_tdomain;

sys/dev/pci/if_mcx.c

1412

uint32_t cmd_rx_hash_sel_outer;

sys/dev/pci/if_mcx.c

1421

uint32_t cmd_rx_hash_sel_inner;

sys/dev/pci/if_mcx.c

1428

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1429

uint32_t cmd_tirn;

sys/dev/pci/if_mcx.c

1437

uint32_t cmd_tirn;

sys/dev/pci/if_mcx.c

1444

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1457

uint32_t cmd_prio;

sys/dev/pci/if_mcx.c

1459

uint32_t cmd_tdomain;

sys/dev/pci/if_mcx.c

1466

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1467

uint32_t cmd_tisn;

sys/dev/pci/if_mcx.c

1475

uint32_t cmd_tisn;

sys/dev/pci/if_mcx.c

1482

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1510

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1511

uint32_t cmd_rqtn;

sys/dev/pci/if_mcx.c

1519

uint32_t cmd_rqtn;

sys/dev/pci/if_mcx.c

1526

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1531

uint32_t cq_status;

sys/dev/pci/if_mcx.c

1542

uint32_t cq_reserved1;

sys/dev/pci/if_mcx.c

1543

uint32_t cq_page_offset;

sys/dev/pci/if_mcx.c

1544

uint32_t cq_uar_size;

sys/dev/pci/if_mcx.c

1547

uint32_t cq_period_max_count;

sys/dev/pci/if_mcx.c

1549

uint32_t cq_eqn;

sys/dev/pci/if_mcx.c

1550

uint32_t cq_log_page_size;

sys/dev/pci/if_mcx.c

1552

uint32_t cq_reserved2;

sys/dev/pci/if_mcx.c

1553

uint32_t cq_last_notified;

sys/dev/pci/if_mcx.c

1554

uint32_t cq_last_solicit;

sys/dev/pci/if_mcx.c

1555

uint32_t cq_consumer_counter;

sys/dev/pci/if_mcx.c

1556

uint32_t cq_producer_counter;

sys/dev/pci/if_mcx.c

1578

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1579

uint32_t cmd_cqn;

sys/dev/pci/if_mcx.c

1587

uint32_t cmd_cqn;

sys/dev/pci/if_mcx.c

1594

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1602

uint32_t cmd_cqn;

sys/dev/pci/if_mcx.c

1609

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1614

uint32_t __reserved__;

sys/dev/pci/if_mcx.c

1615

uint32_t cq_lro;

sys/dev/pci/if_mcx.c

1616

uint32_t cq_lro_ack_seq_num;

sys/dev/pci/if_mcx.c

1617

uint32_t cq_rx_hash;

sys/dev/pci/if_mcx.c

1621

uint32_t cq_checksum;

sys/dev/pci/if_mcx.c

1622

uint32_t __reserved__;

sys/dev/pci/if_mcx.c

1623

uint32_t cq_flags;

sys/dev/pci/if_mcx.c

1630

uint32_t cq_lro_srqn;

sys/dev/pci/if_mcx.c

1631

uint32_t __reserved__[2];

sys/dev/pci/if_mcx.c

1632

uint32_t cq_byte_cnt;

sys/dev/pci/if_mcx.c

1660

uint32_t db_update_ci;

sys/dev/pci/if_mcx.c

1661

uint32_t db_arm_ci;

sys/dev/pci/if_mcx.c

1673

uint32_t wq_pd;

sys/dev/pci/if_mcx.c

1674

uint32_t wq_uar_page;

sys/dev/pci/if_mcx.c

1676

uint32_t wq_hw_counter;

sys/dev/pci/if_mcx.c

1677

uint32_t wq_sw_counter;

sys/dev/pci/if_mcx.c

1687

uint32_t sq_flags;

sys/dev/pci/if_mcx.c

1697

uint32_t sq_user_index;

sys/dev/pci/if_mcx.c

1698

uint32_t sq_cqn;

sys/dev/pci/if_mcx.c

1699

uint32_t sq_reserved1[5];

sys/dev/pci/if_mcx.c

1700

uint32_t sq_tis_lst_sz;

sys/dev/pci/if_mcx.c

1702

uint32_t sq_reserved2[2];

sys/dev/pci/if_mcx.c

1703

uint32_t sq_tis_num;

sys/dev/pci/if_mcx.c

1708

uint32_t sqs_byte_count;

sys/dev/pci/if_mcx.c

1709

uint32_t sqs_lkey;

sys/dev/pci/if_mcx.c

1715

uint32_t sqe_opcode_index;

sys/dev/pci/if_mcx.c

1719

uint32_t sqe_ds_sq_num;

sys/dev/pci/if_mcx.c

1721

uint32_t sqe_signature;

sys/dev/pci/if_mcx.c

1730

uint32_t sqe_mkey;

sys/dev/pci/if_mcx.c

1733

uint32_t sqe_reserved1;

sys/dev/pci/if_mcx.c

1734

uint32_t sqe_mss_csum;

sys/dev/pci/if_mcx.c

1737

uint32_t sqe_reserved2;

sys/dev/pci/if_mcx.c

1757

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1758

uint32_t cmd_sqn;

sys/dev/pci/if_mcx.c

1766

uint32_t cmd_sq_state;

sys/dev/pci/if_mcx.c

1771

uint32_t cmd_modify_hi;

sys/dev/pci/if_mcx.c

1772

uint32_t cmd_modify_lo;

sys/dev/pci/if_mcx.c

1780

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1788

uint32_t cmd_sqn;

sys/dev/pci/if_mcx.c

1795

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1801

uint32_t rq_flags;

sys/dev/pci/if_mcx.c

1811

uint32_t rq_user_index;

sys/dev/pci/if_mcx.c

1812

uint32_t rq_cqn;

sys/dev/pci/if_mcx.c

1813

uint32_t rq_reserved1;

sys/dev/pci/if_mcx.c

1814

uint32_t rq_rmpn;

sys/dev/pci/if_mcx.c

1815

uint32_t rq_reserved2[7];

sys/dev/pci/if_mcx.c

1820

uint32_t rqe_byte_count;

sys/dev/pci/if_mcx.c

1821

uint32_t rqe_lkey;

sys/dev/pci/if_mcx.c

1835

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1836

uint32_t cmd_rqn;

sys/dev/pci/if_mcx.c

1844

uint32_t cmd_rq_state;

sys/dev/pci/if_mcx.c

1849

uint32_t cmd_modify_hi;

sys/dev/pci/if_mcx.c

1850

uint32_t cmd_modify_lo;

sys/dev/pci/if_mcx.c

1858

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1866

uint32_t cmd_rqn;

sys/dev/pci/if_mcx.c

1873

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1889

uint32_t ft_table_miss_id;

sys/dev/pci/if_mcx.c

1902

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1903

uint32_t cmd_table_id;

sys/dev/pci/if_mcx.c

1917

uint32_t cmd_table_id;

sys/dev/pci/if_mcx.c

1924

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1938

uint32_t cmd_table_id;

sys/dev/pci/if_mcx.c

1945

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

1962

uint32_t mc_reserved0;

sys/dev/pci/if_mcx.c

1974

uint32_t mc_outer_ipv6_flow_label;

sys/dev/pci/if_mcx.c

1992

uint32_t cmd_table_id;

sys/dev/pci/if_mcx.c

1994

uint32_t cmd_start_flow_index;

sys/dev/pci/if_mcx.c

1996

uint32_t cmd_end_flow_index;

sys/dev/pci/if_mcx.c

2009

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

2010

uint32_t cmd_group_id;

sys/dev/pci/if_mcx.c

2016

uint32_t fc_group_id;

sys/dev/pci/if_mcx.c

2017

uint32_t fc_flow_tag;

sys/dev/pci/if_mcx.c

2018

uint32_t fc_action;

sys/dev/pci/if_mcx.c

2023

uint32_t fc_dest_list_size;

sys/dev/pci/if_mcx.c

2024

uint32_t fc_counter_list_size;

sys/dev/pci/if_mcx.c

2043

uint32_t cmd_table_id;

sys/dev/pci/if_mcx.c

2044

uint32_t cmd_group_id;

sys/dev/pci/if_mcx.c

2051

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

2065

uint32_t cmd_table_id;

sys/dev/pci/if_mcx.c

2066

uint32_t cmd_modify_enable_mask;

sys/dev/pci/if_mcx.c

2068

uint32_t cmd_flow_index;

sys/dev/pci/if_mcx.c

2076

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

2090

uint32_t cmd_table_id;

sys/dev/pci/if_mcx.c

2092

uint32_t cmd_flow_index;

sys/dev/pci/if_mcx.c

2099

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

2118

uint32_t cmd_table_id;

sys/dev/pci/if_mcx.c

2120

uint32_t cmd_flow_index;

sys/dev/pci/if_mcx.c

2127

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

2141

uint32_t cmd_table_id;

sys/dev/pci/if_mcx.c

2142

uint32_t cmd_group_id;

sys/dev/pci/if_mcx.c

2149

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

2155

uint32_t cmd_start_flow_index;

sys/dev/pci/if_mcx.c

2157

uint32_t cmd_end_flow_index;

sys/dev/pci/if_mcx.c

2159

uint32_t cmd_match_criteria_enable;

sys/dev/pci/if_mcx.c

2174

uint32_t cmd_table_id;

sys/dev/pci/if_mcx.c

2181

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

2201

uint32_t cmd_rqn;

sys/dev/pci/if_mcx.c

2208

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

2221

uint32_t cmd_sqn;

sys/dev/pci/if_mcx.c

2228

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

2240

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

2247

uint32_t db_recv_counter;

sys/dev/pci/if_mcx.c

2248

uint32_t db_send_counter;

sys/dev/pci/if_mcx.c

2278

uint32_t eq_cons;

sys/dev/pci/if_mcx.c

2286

uint32_t cq_cons;

sys/dev/pci/if_mcx.c

2287

uint32_t cq_count;

sys/dev/pci/if_mcx.c

2310

uint32_t rx_prod;

sys/dev/pci/if_mcx.c

2329

uint32_t tx_cons;

sys/dev/pci/if_mcx.c

2330

uint32_t tx_prod;

sys/dev/pci/if_mcx.c

2476

uint32_t sc_lkey;

sys/dev/pci/if_mcx.c

2507

uint32_t sc_mhz;

sys/dev/pci/if_mcx.c

2508

uint32_t sc_khz;

sys/dev/pci/if_mcx.c

2570

static int mcx_create_tir_indirect(struct mcx_softc *, int, uint32_t,

sys/dev/pci/if_mcx.c

2584

uint8_t *, uint32_t);

sys/dev/pci/if_mcx.c

2586

int, int, uint32_t);

sys/dev/pci/if_mcx.c

2636

static inline uint32_t

sys/dev/pci/if_mcx.c

2639

mcx_wr(struct mcx_softc *, bus_size_t, uint32_t);

sys/dev/pci/if_mcx.c

2727

mcx_get_id(uint32_t val)

sys/dev/pci/if_mcx.c

2745

uint32_t r;

sys/dev/pci/if_mcx.c

279

uint32_t cq_input_length;

sys/dev/pci/if_mcx.c

2798

mcx_bar(sc, MCX_CMDQ_ADDR_HI, sizeof(uint32_t),

sys/dev/pci/if_mcx.c

2801

mcx_bar(sc, MCX_CMDQ_ADDR_LO, sizeof(uint32_t),

sys/dev/pci/if_mcx.c

285

uint32_t cq_output_length;

sys/dev/pci/if_mcx.c

3104

uint32_t fw0, fw1;

sys/dev/pci/if_mcx.c

3126

uint32_t r;

sys/dev/pci/if_mcx.c

3134

mcx_bar(sc, MCX_STATE, sizeof(uint32_t),

sys/dev/pci/if_mcx.c

3161

static uint32_t

sys/dev/pci/if_mcx.c

3162

mcx_mix_u64(uint32_t xor, uint64_t u64)

sys/dev/pci/if_mcx.c

3170

static uint32_t

sys/dev/pci/if_mcx.c

3171

mcx_mix_u32(uint32_t xor, uint32_t u32)

sys/dev/pci/if_mcx.c

3178

static uint32_t

sys/dev/pci/if_mcx.c

3179

mcx_mix_u8(uint32_t xor, uint8_t u8)

sys/dev/pci/if_mcx.c

3187

mcx_mix_done(uint32_t xor)

sys/dev/pci/if_mcx.c

3198

const uint32_t *dwords = buf;

sys/dev/pci/if_mcx.c

3199

uint32_t xor = 0xff;

sys/dev/pci/if_mcx.c

320

uint32_t mb_block_number;

sys/dev/pci/if_mcx.c

3244

uint32_t ilen, uint32_t olen, uint8_t token)

sys/dev/pci/if_mcx.c

3290

mcx_bar(sc, MCX_CMDQ_DOORBELL, sizeof(uint32_t),

sys/dev/pci/if_mcx.c

3439

static uint32_t

sys/dev/pci/if_mcx.c

3442

uint32_t xor = 0xff;

sys/dev/pci/if_mcx.c

346

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

360

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

378

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

388

uint32_t cmd_argument;

sys/dev/pci/if_mcx.c

394

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

417

uint32_t rp_ext_eth_proto_cap;

sys/dev/pci/if_mcx.c

418

uint32_t rp_eth_proto_cap;

sys/dev/pci/if_mcx.c

420

uint32_t rp_ext_eth_proto_admin;

sys/dev/pci/if_mcx.c

421

uint32_t rp_eth_proto_admin;

sys/dev/pci/if_mcx.c

4222

uint32_t dest;

sys/dev/pci/if_mcx.c

423

uint32_t rp_ext_eth_proto_oper;

sys/dev/pci/if_mcx.c

424

uint32_t rp_eth_proto_oper;

sys/dev/pci/if_mcx.c

470

uint32_t rp_lane0_mapping;

sys/dev/pci/if_mcx.c

471

uint32_t rp_lane1_mapping;

sys/dev/pci/if_mcx.c

472

uint32_t rp_lane2_mapping;

sys/dev/pci/if_mcx.c

473

uint32_t rp_lane3_mapping;

sys/dev/pci/if_mcx.c

4806

uint32_t rq_flags;

sys/dev/pci/if_mcx.c

4883

rx->rx_doorbell, sizeof(uint32_t), BUS_DMASYNC_PREWRITE);

sys/dev/pci/if_mcx.c

4989

rx->rx_doorbell, sizeof(uint32_t), BUS_DMASYNC_POSTWRITE);

sys/dev/pci/if_mcx.c

5056

mcx_create_tir_indirect(struct mcx_softc *sc, int rqtn, uint32_t hash_sel,

sys/dev/pci/if_mcx.c

5246

tx->tx_doorbell, sizeof(uint32_t), BUS_DMASYNC_PREWRITE);

sys/dev/pci/if_mcx.c

5296

tx->tx_doorbell, sizeof(uint32_t), BUS_DMASYNC_POSTWRITE);

sys/dev/pci/if_mcx.c

5905

uint8_t *macaddr, uint32_t dest)

sys/dev/pci/if_mcx.c

5913

uint32_t *pdest;

sys/dev/pci/if_mcx.c

5942

pdest = (uint32_t *)

sys/dev/pci/if_mcx.c

5982

int ethertype, int ip_proto, uint32_t dest)

sys/dev/pci/if_mcx.c

5990

uint32_t *pdest;

sys/dev/pci/if_mcx.c

6019

pdest = (uint32_t *)

sys/dev/pci/if_mcx.c

657

uint32_t rm_reserved2;

sys/dev/pci/if_mcx.c

671

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

6782

rx->rx_doorbell, sizeof(uint32_t), BUS_DMASYNC_POSTWRITE);

sys/dev/pci/if_mcx.c

6786

rx->rx_doorbell, sizeof(uint32_t), BUS_DMASYNC_PREWRITE);

sys/dev/pci/if_mcx.c

6916

uint32_t flags, len;

sys/dev/pci/if_mcx.c

6990

uint32_t val;

sys/dev/pci/if_mcx.c

700

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

7091

uint32_t val;

sys/dev/pci/if_mcx.c

719

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

7306

uint32_t dest;

sys/dev/pci/if_mcx.c

737

uint32_t cmd_input_num_entries;

sys/dev/pci/if_mcx.c

745

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

746

uint32_t cmd_output_num_entries;

sys/dev/pci/if_mcx.c

7596

uint32_t dest;

sys/dev/pci/if_mcx.c

767

uint32_t cmd_syndrome;

sys/dev/pci/if_mcx.c

7823

uint32_t csum;

sys/dev/pci/if_mcx.c

7961

tx->tx_doorbell, sizeof(uint32_t), BUS_DMASYNC_POSTWRITE);

sys/dev/pci/if_mcx.c

7965

tx->tx_doorbell, sizeof(uint32_t), BUS_DMASYNC_PREWRITE);

sys/dev/pci/if_mcx.c

7992

uint32_t proto_cap;

sys/dev/pci/if_mcx.c

8036

uint32_t proto_oper;

sys/dev/pci/if_mcx.c

8037

uint32_t ext_proto_oper;

sys/dev/pci/if_mcx.c

8096

uint32_t media;

sys/dev/pci/if_mcx.c

8097

uint32_t ext_media;

sys/dev/pci/if_mcx.c

8208

uint32_t proto_oper = betoh32(ptys.rp_eth_proto_oper);

sys/dev/pci/if_mcx.c

8209

uint32_t ext_proto_oper = betoh32(ptys.rp_ext_eth_proto_oper);

sys/dev/pci/if_mcx.c

8253

static inline uint32_t

sys/dev/pci/if_mcx.c

8256

uint32_t word;

sys/dev/pci/if_mcx.c

8264

mcx_wr(struct mcx_softc *sc, bus_size_t r, uint32_t v)

sys/dev/pci/if_mcx.c

8278

uint32_t hi, lo, ni;

sys/dev/pci/if_mcx.c

909

uint32_t flags5;

sys/dev/pci/if_mcx.c

933

uint32_t flags6;

sys/dev/pci/if_mcx.c

987

uint32_t max_qp_mcg; /* 25 bits */

sys/dev/pci/if_msk.c

1558

msk_encap(struct sk_if_softc *sc_if, struct mbuf *m, uint32_t prod)

sys/dev/pci/if_msk.c

1565

uint32_t hiaddr;

sys/dev/pci/if_msk.c

1566

uint32_t next, last;

sys/dev/pci/if_msk.c

1634

uint32_t prod, free, used;

sys/dev/pci/if_msk.c

1717

uint16_t len, uint32_t rxstat)

sys/dev/pci/if_msk.c

1771

uint32_t cons;

sys/dev/pci/if_msk.c

186

void msk_rxeof(struct sk_if_softc *, struct mbuf_list *, uint16_t, uint32_t);

sys/dev/pci/if_msk.c

188

static unsigned int msk_encap(struct sk_if_softc *, struct mbuf *, uint32_t);

sys/dev/pci/if_msk.c

226

uint32_t reg;

sys/dev/pci/if_msk.c

2317

static uint32_t

sys/dev/pci/if_msk.c

2318

msk_mib_read32(struct sk_if_softc *sc_if, uint32_t r)

sys/dev/pci/if_msk.c

2334

return (((uint32_t)hi << 16) | (uint32_t) lo);

sys/dev/pci/if_msk.c

2338

msk_mib_read64(struct sk_if_softc *sc_if, uint32_t r)

sys/dev/pci/if_msk.c

2340

uint32_t hi, lo, xx;

sys/dev/pci/if_msk.c

291

static uint32_t msk_mib_read32(struct sk_if_softc *, uint32_t);

sys/dev/pci/if_msk.c

292

static uint64_t msk_mib_read64(struct sk_if_softc *, uint32_t);

sys/dev/pci/if_msk.c

598

uint32_t prod, head;

sys/dev/pci/if_msk.c

599

uint32_t hiaddr;

sys/dev/pci/if_mskvar.h

101

uint32_t sk_rx_hiaddr;

sys/dev/pci/if_mskvar.h

97

uint32_t sk_tx_hiaddr;

sys/dev/pci/if_mwx.c

1011

uint32_t tsf_lo, tsf_hi;

sys/dev/pci/if_mwx.c

1046

uint32_t intr, intr_sw;

sys/dev/pci/if_mwx.c

1047

uint32_t mask = MT_INT_RX_DONE_ALL|MT_INT_TX_DONE_ALL|MT_INT_MCU_CMD;

sys/dev/pci/if_mwx.c

1186

uint32_t hwid, hwrev;

sys/dev/pci/if_mwx.c

126

uint32_t mq_regbase;

sys/dev/pci/if_mwx.c

1390

uint32_t addr;

sys/dev/pci/if_mwx.c

1521

uint32_t addr;

sys/dev/pci/if_mwx.c

1569

uint32_t regbase)

sys/dev/pci/if_mwx.c

1668

uint32_t dmaaddr;

sys/dev/pci/if_mwx.c

1715

uint32_t buf0, len0, ctrl;

sys/dev/pci/if_mwx.c

1921

uint32_t buf0, buf1 = 0;

sys/dev/pci/if_mwx.c

1922

uint32_t len0, len1 = 0, ctrl;

sys/dev/pci/if_mwx.c

1968

uint32_t buf0, len0, ctrl;

sys/dev/pci/if_mwx.c

2083

uint32_t *data, rxd, type, flag;

sys/dev/pci/if_mwx.c

2086

data = mtod(m, uint32_t *);

sys/dev/pci/if_mwx.c

2144

uint32_t ctrl;

sys/dev/pci/if_mwx.c

221

uint32_t sc_mcu_seq;

sys/dev/pci/if_mwx.c

224

uint32_t mcu_cmd;

sys/dev/pci/if_mwx.c

2248

mwx_mcu_send_mbuf(struct mwx_softc *sc, uint32_t cmd, struct mbuf *m, int *seqp)

sys/dev/pci/if_mwx.c

225

uint32_t mcu_int;

sys/dev/pci/if_mwx.c

2253

uint32_t *txd, val;

sys/dev/pci/if_mwx.c

2270

txd = mtod(m, uint32_t *);

sys/dev/pci/if_mwx.c

2333

mwx_mcu_send_msg(struct mwx_softc *sc, uint32_t cmd, void *data, size_t len,

sys/dev/pci/if_mwx.c

2349

mwx_mcu_send_wait(struct mwx_softc *sc, uint32_t cmd, void *data, size_t len)

sys/dev/pci/if_mwx.c

2360

mwx_mcu_send_mbuf_wait(struct mwx_softc *sc, uint32_t cmd, struct mbuf *m)

sys/dev/pci/if_mwx.c

2374

uint32_t cmd, mcu_int = 0;

sys/dev/pci/if_mwx.c

238

uint32_t sc_rxfilter;

sys/dev/pci/if_mwx.c

2439

KASSERT(m_leadingspace(m) >= sizeof(uint32_t));

sys/dev/pci/if_mwx.c

2440

m = m_prepend(m, sizeof(uint32_t), M_DONTWAIT);

sys/dev/pci/if_mwx.c

2443

if (m->m_len < sizeof(uint32_t) * 2)

sys/dev/pci/if_mwx.c

2445

mcu_int = le32toh(mtod(m, uint32_t *)[1]);

sys/dev/pci/if_mwx.c

2480

mwx_mcu_wait_resp_int(struct mwx_softc *sc, uint32_t cmd, int seq,

sys/dev/pci/if_mwx.c

2481

uint32_t *val)

sys/dev/pci/if_mwx.c

2507

mwx_mcu_wait_resp_msg(struct mwx_softc *sc, uint32_t cmd, int seq,

sys/dev/pci/if_mwx.c

2667

uint32_t

sys/dev/pci/if_mwx.c

2668

mt7921_reg_addr(struct mwx_softc *sc, uint32_t reg)

sys/dev/pci/if_mwx.c

2671

uint32_t phys;

sys/dev/pci/if_mwx.c

2672

uint32_t mapped;

sys/dev/pci/if_mwx.c

2673

uint32_t size;

sys/dev/pci/if_mwx.c

2725

uint32_t ofs;

sys/dev/pci/if_mwx.c

2815

static inline uint32_t

sys/dev/pci/if_mwx.c

2816

mt7921_get_data_mode(struct mwx_softc *sc, uint32_t info)

sys/dev/pci/if_mwx.c

2818

uint32_t mode = DL_MODE_NEED_RSP;

sys/dev/pci/if_mwx.c

2841

static inline uint32_t

sys/dev/pci/if_mwx.c

2844

uint32_t ret = DL_MODE_NEED_RSP;

sys/dev/pci/if_mwx.c

2866

uint32_t reg, override = 0, option = 0;

sys/dev/pci/if_mwx.c

2906

uint32_t len, addr, mode, sec_info;

sys/dev/pci/if_mwx.c

2955

uint32_t len, addr, mode;

sys/dev/pci/if_mwx.c

3018

mt7921_mac_init_band(struct mwx_softc *sc, uint32_t band)

sys/dev/pci/if_mwx.c

3074

uint32_t op = semget ? PATCH_SEM_GET : PATCH_SEM_RELEASE;

sys/dev/pci/if_mwx.c

3076

uint32_t op;

sys/dev/pci/if_mwx.c

3115

mt7921_mcu_init_download(struct mwx_softc *sc, uint32_t addr,

sys/dev/pci/if_mwx.c

3116

uint32_t len, uint32_t mode)

sys/dev/pci/if_mwx.c

3119

uint32_t addr;

sys/dev/pci/if_mwx.c

3120

uint32_t len;

sys/dev/pci/if_mwx.c

3121

uint32_t mode;

sys/dev/pci/if_mwx.c

316

printf("%02X ", (uint32_t)data[l]);

sys/dev/pci/if_mwx.c

3177

mt7921_mcu_start_firmware(struct mwx_softc *sc, uint32_t addr, uint32_t option)

sys/dev/pci/if_mwx.c

3180

uint32_t option;

sys/dev/pci/if_mwx.c

3181

uint32_t addr;

sys/dev/pci/if_mwx.c

3198

uint32_t type;

sys/dev/pci/if_mwx.c

3199

uint32_t len;

sys/dev/pci/if_mwx.c

3237

uint32_t type, len;

sys/dev/pci/if_mwx.c

3317

mt7921_mcu_set_rts_thresh(struct mwx_softc *sc, uint32_t val, uint8_t band)

sys/dev/pci/if_mwx.c

3323

uint32_t len_thresh;

sys/dev/pci/if_mwx.c

3324

uint32_t pkt_thresh;

sys/dev/pci/if_mwx.c

3381

uint32_t delay;

sys/dev/pci/if_mwx.c

3382

uint32_t timestamp;

sys/dev/pci/if_mwx.c

3383

uint32_t applied_flag;

sys/dev/pci/if_mwx.c

353

int mwx_queue_alloc(struct mwx_softc *, struct mwx_queue *, int, uint32_t);

sys/dev/pci/if_mwx.c

3575

uint32_t flags;

sys/dev/pci/if_mwx.c

3676

uint32_t outband_freq;

sys/dev/pci/if_mwx.c

375

int mwx_mcu_send_mbuf(struct mwx_softc *, uint32_t, struct mbuf *, int *);

sys/dev/pci/if_mwx.c

376

int mwx_mcu_send_msg(struct mwx_softc *, uint32_t, void *, size_t, int *);

sys/dev/pci/if_mwx.c

377

int mwx_mcu_send_wait(struct mwx_softc *, uint32_t, void *, size_t);

sys/dev/pci/if_mwx.c

378

int mwx_mcu_send_mbuf_wait(struct mwx_softc *, uint32_t, struct mbuf *);

sys/dev/pci/if_mwx.c

380

int mwx_mcu_wait_resp_int(struct mwx_softc *, uint32_t, int, uint32_t *);

sys/dev/pci/if_mwx.c

381

int mwx_mcu_wait_resp_msg(struct mwx_softc *, uint32_t, int,

sys/dev/pci/if_mwx.c

389

uint32_t mt7921_reg_addr(struct mwx_softc *, uint32_t);

sys/dev/pci/if_mwx.c

3891

uint32_t val, reg_offset;

sys/dev/pci/if_mwx.c

3892

uint32_t cck = MT_TIMEOUT_CCK_DEF_VAL;

sys/dev/pci/if_mwx.c

3893

uint32_t ofdm = MT_TIMEOUT_OFDM_DEF_VAL;

sys/dev/pci/if_mwx.c

3894

uint32_t offset;

sys/dev/pci/if_mwx.c

3896

uint32_t sifs = is_2ghz ? 10 : 16;

sys/dev/pci/if_mwx.c

3897

uint32_t slottime = IEEE80211_DUR_DS_SHSLOT; /* XXX get from stack */

sys/dev/pci/if_mwx.c

394

void mt7921_mac_init_band(struct mwx_softc *sc, uint32_t);

sys/dev/pci/if_mwx.c

397

int mt7921_mcu_init_download(struct mwx_softc *, uint32_t,

sys/dev/pci/if_mwx.c

398

uint32_t, uint32_t);

sys/dev/pci/if_mwx.c

402

int mt7921_mcu_start_firmware(struct mwx_softc *, uint32_t,

sys/dev/pci/if_mwx.c

403

uint32_t);

sys/dev/pci/if_mwx.c

407

int mt7921_mcu_set_rts_thresh(struct mwx_softc *, uint32_t,

sys/dev/pci/if_mwx.c

4228

uint32_t *rxd, rxd0, rxd1, rxd2, rxd3, rxd4;

sys/dev/pci/if_mwx.c

4235

if (m->m_len < num_rxd * sizeof(uint32_t))

sys/dev/pci/if_mwx.c

4238

rxd = mtod(m, uint32_t *);

sys/dev/pci/if_mwx.c

4322

if (m->m_len < num_rxd * sizeof(uint32_t))

sys/dev/pci/if_mwx.c

4327

uint32_t v0 = le32toh(rxd[0]);

sys/dev/pci/if_mwx.c

4328

uint32_t v2 = le32toh(rxd[2]);

sys/dev/pci/if_mwx.c

434

uint32_t mt7921_mac_tx_rate_val(struct mwx_softc *);

sys/dev/pci/if_mwx.c

4503

hdr_gap = num_rxd * sizeof(uint32_t) + 2 * remove_pad;

sys/dev/pci/if_mwx.c

4539

uint32_t

sys/dev/pci/if_mwx.c

4543

uint32_t rate, mode;

sys/dev/pci/if_mwx.c

4573

uint32_t val;

sys/dev/pci/if_mwx.c

459

static inline uint32_t

sys/dev/pci/if_mwx.c

460

mwx_read(struct mwx_softc *sc, uint32_t reg)

sys/dev/pci/if_mwx.c

4632

uint32_t rate, val6;

sys/dev/pci/if_mwx.c

467

mwx_write(struct mwx_softc *sc, uint32_t reg, uint32_t val)

sys/dev/pci/if_mwx.c

4723

uint32_t val, p_fmt, omac_idx;

sys/dev/pci/if_mwx.c

4790

uint32_t cmd, mcu_int = 0;

sys/dev/pci/if_mwx.c

480

static inline uint32_t

sys/dev/pci/if_mwx.c

481

mwx_rmw(struct mwx_softc *sc, uint32_t reg, uint32_t val, uint32_t mask)

sys/dev/pci/if_mwx.c

489

static inline uint32_t

sys/dev/pci/if_mwx.c

490

mwx_set(struct mwx_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pci/if_mwx.c

495

static inline uint32_t

sys/dev/pci/if_mwx.c

496

mwx_clear(struct mwx_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pci/if_mwx.c

501

static inline uint32_t

sys/dev/pci/if_mwx.c

502

mwx_map_reg_l1(struct mwx_softc *sc, uint32_t reg)

sys/dev/pci/if_mwx.c

504

uint32_t offset = MT_HIF_REMAP_L1_GET_OFFSET(reg);

sys/dev/pci/if_mwx.c

505

uint32_t base = MT_HIF_REMAP_L1_GET_BASE(reg);

sys/dev/pci/if_mwx.c

519

mwx_poll(struct mwx_softc *sc, uint32_t reg, uint32_t val, uint32_t mask,

sys/dev/pci/if_mwx.c

522

uint32_t cur;

sys/dev/pci/if_mwxreg.h

1008

uint32_t rssi_th;

sys/dev/pci/if_mwxreg.h

1080

uint32_t beacon_scan_num;

sys/dev/pci/if_mwxreg.h

1095

uint32_t beacon_2g_num;

sys/dev/pci/if_mwxreg.h

1096

uint32_t beacon_5g_num;

sys/dev/pci/if_mwxreg.h

1102

uint32_t hw_sw_ver;

sys/dev/pci/if_mwxreg.h

1103

uint32_t patch_ver;

sys/dev/pci/if_mwxreg.h

1107

uint32_t patch_ver;

sys/dev/pci/if_mwxreg.h

1108

uint32_t subsys;

sys/dev/pci/if_mwxreg.h

1109

uint32_t feature;

sys/dev/pci/if_mwxreg.h

1110

uint32_t n_region;

sys/dev/pci/if_mwxreg.h

1111

uint32_t crc;

sys/dev/pci/if_mwxreg.h

1112

uint32_t reserved[11];

sys/dev/pci/if_mwxreg.h

1117

uint32_t type;

sys/dev/pci/if_mwxreg.h

1118

uint32_t offs;

sys/dev/pci/if_mwxreg.h

1119

uint32_t size;

sys/dev/pci/if_mwxreg.h

1121

uint32_t spec[13];

sys/dev/pci/if_mwxreg.h

1123

uint32_t addr;

sys/dev/pci/if_mwxreg.h

1124

uint32_t len;

sys/dev/pci/if_mwxreg.h

1125

uint32_t sec_key_idx;

sys/dev/pci/if_mwxreg.h

1126

uint32_t align_len;

sys/dev/pci/if_mwxreg.h

1127

uint32_t reserved[9];

sys/dev/pci/if_mwxreg.h

1141

uint32_t crc;

sys/dev/pci/if_mwxreg.h

1145

uint32_t decomp_crc;

sys/dev/pci/if_mwxreg.h

1146

uint32_t decomp_len;

sys/dev/pci/if_mwxreg.h

1147

uint32_t decomp_blk_sz;

sys/dev/pci/if_mwxreg.h

1149

uint32_t addr;

sys/dev/pci/if_mwxreg.h

1150

uint32_t len;

sys/dev/pci/if_mwxreg.h

1170

uint32_t conn_type;

sys/dev/pci/if_mwxreg.h

1195

uint32_t flags;

sys/dev/pci/if_mwxreg.h

392

volatile uint32_t buf0;

sys/dev/pci/if_mwxreg.h

393

volatile uint32_t ctrl;

sys/dev/pci/if_mwxreg.h

394

volatile uint32_t buf1;

sys/dev/pci/if_mwxreg.h

395

volatile uint32_t info;

sys/dev/pci/if_mwxreg.h

399

uint32_t buf0;

sys/dev/pci/if_mwxreg.h

402

uint32_t buf1;

sys/dev/pci/if_mwxreg.h

407

#define MT_TXD_SIZE (8 * sizeof(uint32_t))

sys/dev/pci/if_mwxreg.h

415

uint32_t txwi[8];

sys/dev/pci/if_mwxreg.h

829

uint32_t txd[8];

sys/dev/pci/if_mwxreg.h

844

uint32_t reserved[5];

sys/dev/pci/if_mwxreg.h

877

uint32_t txd[8];

sys/dev/pci/if_mwxreg.h

900

uint32_t rxd[6];

sys/dev/pci/if_mwxreg.h

914

uint32_t status; /* 0: success, others: fail */

sys/dev/pci/if_mwxreg.h

918

uint32_t reg;

sys/dev/pci/if_mwxreg.h

919

uint32_t val;

sys/dev/pci/if_mwxreg.h

971

uint32_t conn_type;

sys/dev/pci/if_mwxreg.h

995

uint32_t ssid_len;

sys/dev/pci/if_myx.c

2143

uint32_t mkc_counters[myx_ncounters];

sys/dev/pci/if_myx.c

2175

bemtoh32((uint32_t *)((uint8_t *)sts + mc->mc_offset));

sys/dev/pci/if_myx.c

974

uint32_t r;

sys/dev/pci/if_nep.c

1559

sc->sc_rbring = nep_dmamem_alloc(sc, NEP_NRBDESC * sizeof(uint32_t));

sys/dev/pci/if_nep.c

1742

uint32_t crc, hash[16];

sys/dev/pci/if_nep.c

444

uint32_t *sc_rbdesc;

sys/dev/pci/if_nep.c

471

uint64_t nep_read(struct nep_softc *, uint32_t);

sys/dev/pci/if_nep.c

472

void nep_write(struct nep_softc *, uint32_t, uint64_t);

sys/dev/pci/if_nep.c

791

nep_read(struct nep_softc *sc, uint32_t reg)

sys/dev/pci/if_nep.c

797

nep_write(struct nep_softc *sc, uint32_t reg, uint64_t value)

sys/dev/pci/if_nfe.c

1016

uint32_t tmp;

sys/dev/pci/if_nfe.c

1491

uint32_t filter;

sys/dev/pci/if_nfe.c

1541

uint32_t tmp;

sys/dev/pci/if_nfe.c

364

uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;

sys/dev/pci/if_nfe.c

405

uint32_t val;

sys/dev/pci/if_nfe.c

448

uint32_t ctl;

sys/dev/pci/if_nfe.c

478

uint32_t r;

sys/dev/pci/if_nfe.c

635

uint32_t vtag;

sys/dev/pci/if_nfe.c

857

uint32_t vtag = 0;

sys/dev/pci/if_nfereg.h

153

uint32_t physaddr;

sys/dev/pci/if_nfereg.h

168

uint32_t physaddr[2];

sys/dev/pci/if_nfereg.h

169

uint32_t vtag;

sys/dev/pci/if_nfevar.h

75

uint32_t rxtxctl;

sys/dev/pci/if_ngbe.c

112

int ngbe_fmgr_cmd_op(struct ngbe_hw *, uint32_t, uint32_t);

sys/dev/pci/if_ngbe.c

113

uint32_t ngbe_flash_read_dword(struct ngbe_hw *, uint32_t);

sys/dev/pci/if_ngbe.c

114

uint8_t ngbe_calculate_checksum(uint8_t *, uint32_t);

sys/dev/pci/if_ngbe.c

1142

isize = sizeof(uint32_t) * NGBE_ISB_MAX;

sys/dev/pci/if_ngbe.c

1148

sc->isb_base = (uint32_t *)sc->isbdma.dma_vaddr;

sys/dev/pci/if_ngbe.c

115

int ngbe_check_flash_load(struct ngbe_softc *, uint32_t);

sys/dev/pci/if_ngbe.c

117

int ngbe_check_mac_link(struct ngbe_hw *, uint32_t *, int *,

sys/dev/pci/if_ngbe.c

127

void ngbe_disable_queue(struct ngbe_softc *, uint32_t);

sys/dev/pci/if_ngbe.c

131

uint32_t *);

sys/dev/pci/if_ngbe.c

133

void ngbe_enable_queue(struct ngbe_softc *, uint32_t);

sys/dev/pci/if_ngbe.c

135

void ngbe_enable_rx_dma(struct ngbe_hw *, uint32_t);

sys/dev/pci/if_ngbe.c

141

uint32_t *, int *);

sys/dev/pci/if_ngbe.c

1504

ngbe_addr_list_itr(struct ngbe_hw *hw, uint8_t **mc_addr_ptr, uint32_t *vmdq)

sys/dev/pci/if_ngbe.c

152

uint32_t *, uint32_t, uint32_t, int);

sys/dev/pci/if_ngbe.c

1523

uint32_t fctrl, vlanctrl;

sys/dev/pci/if_ngbe.c

157

int ngbe_negotiate_fc(struct ngbe_softc *, uint32_t,

sys/dev/pci/if_ngbe.c

1573

uint32_t bufsz, mhadd, rxctrl, rxdctl, srrctl;

sys/dev/pci/if_ngbe.c

158

uint32_t, uint32_t, uint32_t, uint32_t, uint32_t);

sys/dev/pci/if_ngbe.c

1667

uint32_t reta = 0, rss_field, rss_key[10];

sys/dev/pci/if_ngbe.c

1680

reta = reta | (((uint32_t)queue_id) << 24);

sys/dev/pci/if_ngbe.c

170

int ngbe_phy_led_oem_chk(struct ngbe_softc *, uint32_t *);

sys/dev/pci/if_ngbe.c

1709

uint32_t txdctl;

sys/dev/pci/if_ngbe.c

171

int ngbe_phy_read_reg(struct ngbe_hw *, uint32_t, uint32_t,

sys/dev/pci/if_ngbe.c

173

int ngbe_phy_write_reg(struct ngbe_hw *, uint32_t, uint32_t,

sys/dev/pci/if_ngbe.c

1773

uint32_t eicr;

sys/dev/pci/if_ngbe.c

179

int ngbe_phy_setup_link(struct ngbe_softc *, uint32_t, int);

sys/dev/pci/if_ngbe.c

180

uint16_t ngbe_read_pci_cfg_word(struct ngbe_softc *, uint32_t);

sys/dev/pci/if_ngbe.c

182

int ngbe_acquire_swfw_sync(struct ngbe_softc *, uint32_t);

sys/dev/pci/if_ngbe.c

183

void ngbe_release_swfw_sync(struct ngbe_softc *, uint32_t);

sys/dev/pci/if_ngbe.c

1912

uint32_t rar_entries = hw->mac.num_rar_entries;

sys/dev/pci/if_ngbe.c

1913

uint32_t i, psrctl;

sys/dev/pci/if_ngbe.c

194

int ngbe_set_rar(struct ngbe_softc *, uint32_t, uint8_t *,

sys/dev/pci/if_ngbe.c

195

uint64_t, uint32_t);

sys/dev/pci/if_ngbe.c

197

void ngbe_set_rxpba(struct ngbe_hw *, int, uint32_t, int);

sys/dev/pci/if_ngbe.c

198

int ngbe_setup_copper_link(struct ngbe_softc *, uint32_t,

sys/dev/pci/if_ngbe.c

1999

uint32_t speed;

sys/dev/pci/if_ngbe.c

2050

return ngbe_negotiate_fc(sc, (uint32_t)technology_ability_reg,

sys/dev/pci/if_ngbe.c

2051

(uint32_t)lp_technology_ability_reg, NGBE_TAF_SYM_PAUSE,

sys/dev/pci/if_ngbe.c

2059

uint32_t mflcn, fccfg;

sys/dev/pci/if_ngbe.c

2060

uint32_t fcrtl, fcrth;

sys/dev/pci/if_ngbe.c

2061

uint32_t reg;

sys/dev/pci/if_ngbe.c

207

void ngbe_rx_checksum(uint32_t, struct mbuf *);

sys/dev/pci/if_ngbe.c

211

uint32_t *, uint32_t *);

sys/dev/pci/if_ngbe.c

214

uint32_t, ngbe_mc_addr_itr, int);

sys/dev/pci/if_ngbe.c

2172

ngbe_fmgr_cmd_op(struct ngbe_hw *hw, uint32_t cmd, uint32_t cmd_addr)

sys/dev/pci/if_ngbe.c

2174

uint32_t val;

sys/dev/pci/if_ngbe.c

2193

uint32_t

sys/dev/pci/if_ngbe.c

2194

ngbe_flash_read_dword(struct ngbe_hw *hw, uint32_t addr)

sys/dev/pci/if_ngbe.c

2204

ngbe_calculate_checksum(uint8_t *buffer, uint32_t length)

sys/dev/pci/if_ngbe.c

2206

uint32_t i;

sys/dev/pci/if_ngbe.c

2218

ngbe_check_flash_load(struct ngbe_softc *sc, uint32_t check_bit)

sys/dev/pci/if_ngbe.c

2221

uint32_t reg = 0;

sys/dev/pci/if_ngbe.c

2261

hw->phy.id = (uint32_t)phy_id;

sys/dev/pci/if_ngbe.c

2267

ngbe_check_mac_link(struct ngbe_hw *hw, uint32_t *speed, int *link_up,

sys/dev/pci/if_ngbe.c

2270

uint32_t status = 0;

sys/dev/pci/if_ngbe.c

2326

uint32_t mmngc;

sys/dev/pci/if_ngbe.c

2372

uint32_t offset;

sys/dev/pci/if_ngbe.c

238

uint32_t eeprom_cksum_devcap, devcap, led_conf;

sys/dev/pci/if_ngbe.c

2391

uint32_t newitr;

sys/dev/pci/if_ngbe.c

2457

ngbe_disable_queue(struct ngbe_softc *sc, uint32_t vector)

sys/dev/pci/if_ngbe.c

2460

uint32_t mask;

sys/dev/pci/if_ngbe.c

2470

uint32_t rxctrl, psrctrl;

sys/dev/pci/if_ngbe.c

2492

uint32_t secrxreg;

sys/dev/pci/if_ngbe.c

2507

ngbe_eepromcheck_cap(struct ngbe_softc *sc, uint16_t offset, uint32_t *data)

sys/dev/pci/if_ngbe.c

2511

uint32_t tmp;

sys/dev/pci/if_ngbe.c

2524

status = ngbe_host_interface_command(sc, (uint32_t *)&buffer,

sys/dev/pci/if_ngbe.c

2546

uint32_t mask;

sys/dev/pci/if_ngbe.c

2570

ngbe_enable_queue(struct ngbe_softc *sc, uint32_t vector)

sys/dev/pci/if_ngbe.c

2573

uint32_t mask;

sys/dev/pci/if_ngbe.c

2583

uint32_t val;

sys/dev/pci/if_ngbe.c

2603

ngbe_enable_rx_dma(struct ngbe_hw *hw, uint32_t reg)

sys/dev/pci/if_ngbe.c

2632

uint32_t olinfo_status = 0, cmd_type_len;

sys/dev/pci/if_ngbe.c

2763

ngbe_get_copper_link_capabilities(struct ngbe_hw *hw, uint32_t *speed,

sys/dev/pci/if_ngbe.c

2781

uint32_t swsm;

sys/dev/pci/if_ngbe.c

2842

uint32_t rar_high, rar_low;

sys/dev/pci/if_ngbe.c

2886

uint32_t efuse[2];

sys/dev/pci/if_ngbe.c

2932

uint32_t reg;

sys/dev/pci/if_ngbe.c

2941

ngbe_host_interface_command(struct ngbe_softc *sc, uint32_t *buffer,

sys/dev/pci/if_ngbe.c

2942

uint32_t length, uint32_t timeout, int return_data)

sys/dev/pci/if_ngbe.c

2945

uint32_t hicr, i, bi, dword_len;

sys/dev/pci/if_ngbe.c

2946

uint32_t hdr_size = sizeof(struct ngbe_hic_hdr);

sys/dev/pci/if_ngbe.c

2947

uint32_t buf[64] = {};

sys/dev/pci/if_ngbe.c

2960

if ((length % (sizeof(uint32_t))) != 0) {

sys/dev/pci/if_ngbe.c

3070

uint32_t dv_id, rx_pba;

sys/dev/pci/if_ngbe.c

3092

uint32_t dv_id;

sys/dev/pci/if_ngbe.c

3108

uint32_t fwsm;

sys/dev/pci/if_ngbe.c

3118

uint32_t vector = 0;

sys/dev/pci/if_ngbe.c

3142

ngbe_negotiate_fc(struct ngbe_softc *sc, uint32_t adv_reg, uint32_t lp_reg,

sys/dev/pci/if_ngbe.c

3143

uint32_t adv_sym, uint32_t adv_asm, uint32_t lp_sym, uint32_t lp_asm)

sys/dev/pci/if_ngbe.c

3179

uint32_t speed;

sys/dev/pci/if_ngbe.c

3224

uint32_t ts_state;

sys/dev/pci/if_ngbe.c

3336

ngbe_phy_led_oem_chk(struct ngbe_softc *sc, uint32_t *data)

sys/dev/pci/if_ngbe.c

3340

uint32_t tmp;

sys/dev/pci/if_ngbe.c

3353

status = ngbe_host_interface_command(sc, (uint32_t *)&buffer,

sys/dev/pci/if_ngbe.c

3378

ngbe_phy_read_reg(struct ngbe_hw *hw, uint32_t off, uint32_t page,

sys/dev/pci/if_ngbe.c

3396

ngbe_phy_write_reg(struct ngbe_hw *hw, uint32_t off, uint32_t page,

sys/dev/pci/if_ngbe.c

3502

ngbe_phy_setup_link(struct ngbe_softc *sc, uint32_t speed, int need_restart)

sys/dev/pci/if_ngbe.c

3578

ngbe_read_pci_cfg_word(struct ngbe_softc *sc, uint32_t reg)

sys/dev/pci/if_ngbe.c

3582

uint32_t value;

sys/dev/pci/if_ngbe.c

3607

ngbe_acquire_swfw_sync(struct ngbe_softc *sc, uint32_t mask)

sys/dev/pci/if_ngbe.c

3610

uint32_t gssr = 0;

sys/dev/pci/if_ngbe.c

3611

uint32_t swmask = mask;

sys/dev/pci/if_ngbe.c

3612

uint32_t fwmask = mask << 16;

sys/dev/pci/if_ngbe.c

3648

ngbe_release_swfw_sync(struct ngbe_softc *sc, uint32_t mask)

sys/dev/pci/if_ngbe.c

3680

uint32_t i, reset_status, rst_delay;

sys/dev/pci/if_ngbe.c

3681

uint32_t reset = 0;

sys/dev/pci/if_ngbe.c

371

static inline uint32_t

sys/dev/pci/if_ngbe.c

372

NGBE_READ_REG_MASK(struct ngbe_hw *hw, uint32_t reg, uint32_t mask)

sys/dev/pci/if_ngbe.c

374

uint32_t val;

sys/dev/pci/if_ngbe.c

383

NGBE_WRITE_REG_MASK(struct ngbe_hw *hw, uint32_t reg, uint32_t mask,

sys/dev/pci/if_ngbe.c

3834

error = ngbe_host_interface_command(sc, (uint32_t *)&fw_cmd,

sys/dev/pci/if_ngbe.c

384

uint32_t field)

sys/dev/pci/if_ngbe.c

3855

uint32_t ivar, index;

sys/dev/pci/if_ngbe.c

386

uint32_t val;

sys/dev/pci/if_ngbe.c

3863

ivar &= ~((uint32_t)0xff << index);

sys/dev/pci/if_ngbe.c

3864

ivar |= ((uint32_t)vector << index);

sys/dev/pci/if_ngbe.c

3870

ivar &= ~((uint32_t)0xff << index);

sys/dev/pci/if_ngbe.c

3871

ivar |= ((uint32_t)vector << index);

sys/dev/pci/if_ngbe.c

3880

uint32_t reg = 0;

sys/dev/pci/if_ngbe.c

3889

uint32_t vector, vector_bit, vector_reg;

sys/dev/pci/if_ngbe.c

395

static inline uint32_t

sys/dev/pci/if_ngbe.c

3950

ngbe_set_rar(struct ngbe_softc *sc, uint32_t index, uint8_t *addr,

sys/dev/pci/if_ngbe.c

3951

uint64_t pools, uint32_t enable_addr)

sys/dev/pci/if_ngbe.c

3954

uint32_t rar_entries = hw->mac.num_rar_entries;

sys/dev/pci/if_ngbe.c

3955

uint32_t rar_low, rar_high;

sys/dev/pci/if_ngbe.c

3978

rar_low = ((uint32_t)addr[5] | ((uint32_t)addr[4] << 8) |

sys/dev/pci/if_ngbe.c

3979

((uint32_t)addr[3] << 16) | ((uint32_t)addr[2] << 24));

sys/dev/pci/if_ngbe.c

3980

rar_high = ((uint32_t)addr[1] | ((uint32_t)addr[0] << 8));

sys/dev/pci/if_ngbe.c

3995

uint32_t srrctl;

sys/dev/pci/if_ngbe.c

4016

ngbe_set_rxpba(struct ngbe_hw *hw, int num_pb, uint32_t headroom, int strategy)

sys/dev/pci/if_ngbe.c

4018

uint32_t pbsize = hw->mac.rx_pb_size;

sys/dev/pci/if_ngbe.c

4019

uint32_t txpktsize, txpbthresh, rxpktsize = 0;

sys/dev/pci/if_ngbe.c

4049

ngbe_setup_copper_link(struct ngbe_softc *sc, uint32_t speed, int need_restart)

sys/dev/pci/if_ngbe.c

4136

uint32_t gpie;

sys/dev/pci/if_ngbe.c

4161

uint32_t psrtype;

sys/dev/pci/if_ngbe.c

4253

ngbe_rx_checksum(uint32_t staterr, struct mbuf *m)

sys/dev/pci/if_ngbe.c

4277

uint32_t staterr = 0;

sys/dev/pci/if_ngbe.c

4287

uint32_t hash;

sys/dev/pci/if_ngbe.c

4414

ngbe_tx_ctx_setup(struct tx_ring *txr, struct mbuf *m, uint32_t *cmd_type_len,

sys/dev/pci/if_ngbe.c

4415

uint32_t *olinfo_status)

sys/dev/pci/if_ngbe.c

4419

uint32_t vlan_macip_lens = 0, type_tucmd_mlhl = 0;

sys/dev/pci/if_ngbe.c

4428

uint32_t vtag = m->m_pkthdr.ether_vtag;

sys/dev/pci/if_ngbe.c

4516

uint32_t mc_addr_count, ngbe_mc_addr_itr next, int clear)

sys/dev/pci/if_ngbe.c

4518

uint32_t i, psrctl, vmdq;

sys/dev/pci/if_ngbe.c

4552

uint32_t status = 0;

sys/dev/pci/if_ngbe.c

563

uint32_t advertised = 0;

sys/dev/pci/if_ngbe.c

755

uint32_t rxdctl;

sys/dev/pci/if_ngbe.c

832

uint32_t reg, speed = 0;

sys/dev/pci/if_ngbe.c

95

uint32_t *);

sys/dev/pci/if_ngbereg.h

1002

uint32_t me;

sys/dev/pci/if_ngbereg.h

1003

uint32_t watchdog_timer;

sys/dev/pci/if_ngbereg.h

1007

uint32_t next_avail_desc;

sys/dev/pci/if_ngbereg.h

1008

uint32_t next_to_clean;

sys/dev/pci/if_ngbereg.h

1015

uint32_t me;

sys/dev/pci/if_ngbereg.h

1019

uint32_t last_desc_filled;

sys/dev/pci/if_ngbereg.h

1020

uint32_t next_to_check;

sys/dev/pci/if_ngbereg.h

1027

uint32_t msix;

sys/dev/pci/if_ngbereg.h

1028

uint32_t eims;

sys/dev/pci/if_ngbereg.h

1047

uint32_t led_conf;

sys/dev/pci/if_ngbereg.h

1048

uint32_t gphy_efuse[2];

sys/dev/pci/if_ngbereg.h

1049

uint32_t link_speed;

sys/dev/pci/if_ngbereg.h

1050

uint32_t linkvec;

sys/dev/pci/if_ngbereg.h

1057

uint32_t *isb_base;

sys/dev/pci/if_ngbereg.h

586

#define le32_to_cpup(x) (le32toh(*(const uint32_t *)(x)))

sys/dev/pci/if_ngbereg.h

588

do { *((uint32_t *)(x)) = le32_to_cpup((x)); } while (0)

sys/dev/pci/if_ngbereg.h

713

uint32_t address;

sys/dev/pci/if_ngbereg.h

738

uint32_t *);

sys/dev/pci/if_ngbereg.h

743

uint32_t *);

sys/dev/pci/if_ngbereg.h

744

int (*phy_led_oem_chk)(struct ngbe_softc *, uint32_t *);

sys/dev/pci/if_ngbereg.h

757

void (*enable_rx_dma)(struct ngbe_hw *, uint32_t);

sys/dev/pci/if_ngbereg.h

761

uint32_t);

sys/dev/pci/if_ngbereg.h

763

uint32_t);

sys/dev/pci/if_ngbereg.h

766

int (*setup_link)(struct ngbe_softc *, uint32_t,

sys/dev/pci/if_ngbereg.h

768

int (*check_link)(struct ngbe_hw *, uint32_t *,

sys/dev/pci/if_ngbereg.h

771

uint32_t *, int *);

sys/dev/pci/if_ngbereg.h

774

void (*setup_rxpba)(struct ngbe_hw *, int, uint32_t,

sys/dev/pci/if_ngbereg.h

778

int (*set_rar)(struct ngbe_softc *, uint32_t,

sys/dev/pci/if_ngbereg.h

779

uint8_t *, uint64_t, uint32_t);

sys/dev/pci/if_ngbereg.h

782

uint8_t *, uint32_t, ngbe_mc_addr_itr, int);

sys/dev/pci/if_ngbereg.h

803

int (*read_reg)(struct ngbe_hw *, uint32_t, uint32_t,

sys/dev/pci/if_ngbereg.h

805

int (*write_reg)(struct ngbe_hw *, uint32_t, uint32_t,

sys/dev/pci/if_ngbereg.h

807

int (*setup_link)(struct ngbe_softc *, uint32_t, int);

sys/dev/pci/if_ngbereg.h

818

uint32_t num_mc_addrs;

sys/dev/pci/if_ngbereg.h

819

uint32_t rar_used_count;

sys/dev/pci/if_ngbereg.h

820

uint32_t mta_in_use;

sys/dev/pci/if_ngbereg.h

821

uint32_t overflow_promisc;

sys/dev/pci/if_ngbereg.h

843

uint32_t mta_shadow[NGBE_MAX_MTA];

sys/dev/pci/if_ngbereg.h

845

uint32_t mcft_size;

sys/dev/pci/if_ngbereg.h

846

uint32_t vft_shadow[NGBE_MAX_VFTA_ENTRIES];

sys/dev/pci/if_ngbereg.h

847

uint32_t vft_size;

sys/dev/pci/if_ngbereg.h

848

uint32_t num_rar_entries;

sys/dev/pci/if_ngbereg.h

849

uint32_t rx_pb_size;

sys/dev/pci/if_ngbereg.h

850

uint32_t max_tx_queues;

sys/dev/pci/if_ngbereg.h

851

uint32_t max_rx_queues;

sys/dev/pci/if_ngbereg.h

859

uint32_t high_water;

sys/dev/pci/if_ngbereg.h

860

uint32_t low_water;

sys/dev/pci/if_ngbereg.h

872

uint32_t addr;

sys/dev/pci/if_ngbereg.h

873

uint32_t id;

sys/dev/pci/if_ngbereg.h

874

uint32_t phy_semaphore_mask;

sys/dev/pci/if_ngbereg.h

876

uint32_t autoneg_advertised;

sys/dev/pci/if_ngbereg.h

878

uint32_t force_speed;

sys/dev/pci/if_ngbereg.h

889

uint32_t subsystem_device_id;

sys/dev/pci/if_ngbereg.h

899

uint32_t cmd_type_len;

sys/dev/pci/if_ngbereg.h

900

uint32_t olinfo_status;

sys/dev/pci/if_ngbereg.h

904

uint32_t nxtseq_seed;

sys/dev/pci/if_ngbereg.h

905

uint32_t status;

sys/dev/pci/if_ngbereg.h

936

uint32_t data;

sys/dev/pci/if_ngbereg.h

943

uint32_t rss;

sys/dev/pci/if_ngbereg.h

951

uint32_t status_error;

sys/dev/pci/if_ngbereg.h

972

uint32_t vlan_macip_lens;

sys/dev/pci/if_ngbereg.h

973

uint32_t seqnum_seed;

sys/dev/pci/if_ngbereg.h

974

uint32_t type_tucmd_mlhl;

sys/dev/pci/if_ngbereg.h

975

uint32_t mss_l4len_idx;

sys/dev/pci/if_ngbereg.h

979

uint32_t eop_index;

sys/dev/pci/if_oce.c

2679

uint32_t reg;

sys/dev/pci/if_oce.c

271

uint32_t rss_cpuid;

sys/dev/pci/if_oce.c

2740

uint32_t pa, reg;

sys/dev/pci/if_oce.c

2743

pa = (uint32_t)((uint64_t)OCE_MEM_DVA(&sc->sc_mbx) >> 34);

sys/dev/pci/if_oce.c

2751

pa = (uint32_t)((uint64_t)OCE_MEM_DVA(&sc->sc_mbx) >> 4) & 0x3fffffff;

sys/dev/pci/if_oce.c

2942

uint32_t caps, caps_en;

sys/dev/pci/if_oce.c

3184

uint32_t old_pmac_id = sc->sc_pmac_id;

sys/dev/pci/if_oce.c

3217

oce_macaddr_add(struct oce_softc *sc, uint8_t *enaddr, uint32_t *pmac)

sys/dev/pci/if_oce.c

3235

oce_macaddr_del(struct oce_softc *sc, uint32_t pmac)

sys/dev/pci/if_oce.c

339

uint32_t sc_if_id; /* interface ID */

sys/dev/pci/if_oce.c

340

uint32_t sc_pmac_id; /* PMAC id */

sys/dev/pci/if_oce.c

343

uint32_t sc_pvid;

sys/dev/pci/if_oce.c

357

#define ADDR_HI(x) ((uint32_t)((uint64_t)(x) >> 32))

sys/dev/pci/if_oce.c

358

#define ADDR_LO(x) ((uint32_t)((uint64_t)(x) & 0xffffffff))

sys/dev/pci/if_oce.c

476

int oce_macaddr_add(struct oce_softc *, uint8_t *macaddr, uint32_t *pmac);

sys/dev/pci/if_oce.c

477

int oce_macaddr_del(struct oce_softc *, uint32_t pmac);

sys/dev/pci/if_oce.c

715

static inline uint32_t

sys/dev/pci/if_oce.c

723

static inline uint32_t

sys/dev/pci/if_oce.c

731

static inline uint32_t

sys/dev/pci/if_oce.c

740

oce_write_cfg(struct oce_softc *sc, bus_size_t off, uint32_t val)

sys/dev/pci/if_oce.c

748

oce_write_csr(struct oce_softc *sc, bus_size_t off, uint32_t val)

sys/dev/pci/if_oce.c

756

oce_write_db(struct oce_softc *sc, bus_size_t off, uint32_t val)

sys/dev/pci/if_oce.c

766

uint32_t reg;

sys/dev/pci/if_oce.c

775

uint32_t reg;

sys/dev/pci/if_ocereg.h

1005

uint32_t num_msi_msgs;

sys/dev/pci/if_ocereg.h

1009

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

1030

uint32_t misc_params;

sys/dev/pci/if_ocereg.h

1035

uint32_t future_use[2];

sys/dev/pci/if_ocereg.h

1042

uint32_t rsvd0[4];

sys/dev/pci/if_ocereg.h

1056

uint32_t write_length: 24;

sys/dev/pci/if_ocereg.h

1057

uint32_t rsvd: 7;

sys/dev/pci/if_ocereg.h

1058

uint32_t eof: 1;

sys/dev/pci/if_ocereg.h

1059

uint32_t write_offset;

sys/dev/pci/if_ocereg.h

1061

uint32_t descriptor_count;

sys/dev/pci/if_ocereg.h

1062

uint32_t buffer_length;

sys/dev/pci/if_ocereg.h

1063

uint32_t address_lower;

sys/dev/pci/if_ocereg.h

1064

uint32_t address_upper;

sys/dev/pci/if_ocereg.h

1073

uint32_t response_length;

sys/dev/pci/if_ocereg.h

1074

uint32_t actual_response_length;

sys/dev/pci/if_ocereg.h

1075

uint32_t actual_write_length;

sys/dev/pci/if_ocereg.h

1092

uint32_t rsvd0[30];

sys/dev/pci/if_ocereg.h

1096

uint32_t config_number;

sys/dev/pci/if_ocereg.h

1097

uint32_t asic_revision;

sys/dev/pci/if_ocereg.h

1098

uint32_t port_id; /* used for stats retrieval */

sys/dev/pci/if_ocereg.h

1099

uint32_t function_mode;

sys/dev/pci/if_ocereg.h

1102

uint32_t ulp_mode;

sys/dev/pci/if_ocereg.h

1103

uint32_t nic_wqid_base;

sys/dev/pci/if_ocereg.h

1104

uint32_t nic_wq_tot;

sys/dev/pci/if_ocereg.h

1105

uint32_t toe_wqid_base;

sys/dev/pci/if_ocereg.h

1106

uint32_t toe_wq_tot;

sys/dev/pci/if_ocereg.h

1107

uint32_t toe_rqid_base;

sys/dev/pci/if_ocereg.h

1108

uint32_t toe_rqid_tot;

sys/dev/pci/if_ocereg.h

1109

uint32_t toe_defrqid_base;

sys/dev/pci/if_ocereg.h

1110

uint32_t toe_defrqid_count;

sys/dev/pci/if_ocereg.h

1111

uint32_t lro_rqid_base;

sys/dev/pci/if_ocereg.h

1112

uint32_t lro_rqid_tot;

sys/dev/pci/if_ocereg.h

1113

uint32_t iscsi_icd_base;

sys/dev/pci/if_ocereg.h

1114

uint32_t iscsi_icd_count;

sys/dev/pci/if_ocereg.h

1116

uint32_t function_caps;

sys/dev/pci/if_ocereg.h

1117

uint32_t cqid_base;

sys/dev/pci/if_ocereg.h

1118

uint32_t cqid_tot;

sys/dev/pci/if_ocereg.h

1119

uint32_t eqid_base;

sys/dev/pci/if_ocereg.h

1120

uint32_t eqid_tot;

sys/dev/pci/if_ocereg.h

1219

uint32_t rsvd;

sys/dev/pci/if_ocereg.h

1225

uint32_t global_flags_mask;

sys/dev/pci/if_ocereg.h

1226

uint32_t global_flags;

sys/dev/pci/if_ocereg.h

1227

uint32_t iface_flags_mask;

sys/dev/pci/if_ocereg.h

1228

uint32_t iface_flags;

sys/dev/pci/if_ocereg.h

1229

uint32_t if_id;

sys/dev/pci/if_ocereg.h

1231

uint32_t num_mcast;

sys/dev/pci/if_ocereg.h

1251

uint32_t num_eq;

sys/dev/pci/if_ocereg.h

1253

uint32_t eq_id;

sys/dev/pci/if_ocereg.h

1254

uint32_t phase;

sys/dev/pci/if_ocereg.h

1255

uint32_t dm;

sys/dev/pci/if_ocereg.h

1260

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

1270

uint32_t if_id;

sys/dev/pci/if_ocereg.h

1275

uint32_t pmac_id;

sys/dev/pci/if_ocereg.h

1285

uint32_t if_id;

sys/dev/pci/if_ocereg.h

1286

uint32_t pmac_id;

sys/dev/pci/if_ocereg.h

1289

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

1298

uint32_t max_ioctl_bufsz;

sys/dev/pci/if_ocereg.h

1312

uint32_t enable;

sys/dev/pci/if_ocereg.h

1315

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

1328

uint32_t valid_capability_flags;

sys/dev/pci/if_ocereg.h

1329

uint32_t capability_flags;

sys/dev/pci/if_ocereg.h

1333

uint32_t valid_capability_flags;

sys/dev/pci/if_ocereg.h

1334

uint32_t capability_flags;

sys/dev/pci/if_ocereg.h

1343

uint32_t loopback_type;

sys/dev/pci/if_ocereg.h

1344

uint32_t num_pkts;

sys/dev/pci/if_ocereg.h

1346

uint32_t src_port;

sys/dev/pci/if_ocereg.h

1347

uint32_t dest_port;

sys/dev/pci/if_ocereg.h

1348

uint32_t pkt_size;

sys/dev/pci/if_ocereg.h

1351

uint32_t status;

sys/dev/pci/if_ocereg.h

1352

uint32_t num_txfer;

sys/dev/pci/if_ocereg.h

1353

uint32_t num_rx;

sys/dev/pci/if_ocereg.h

1354

uint32_t miscomp_off;

sys/dev/pci/if_ocereg.h

1355

uint32_t ticks_compl;

sys/dev/pci/if_ocereg.h

1585

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

1588

uint32_t last_seg_udp_len:14;

sys/dev/pci/if_ocereg.h

1589

uint32_t rsvd1:18;

sys/dev/pci/if_ocereg.h

1592

uint32_t lso_mss:14;

sys/dev/pci/if_ocereg.h

1593

uint32_t num_wqe:5;

sys/dev/pci/if_ocereg.h

1594

uint32_t rsvd4:2;

sys/dev/pci/if_ocereg.h

1595

uint32_t vlan:1;

sys/dev/pci/if_ocereg.h

1596

uint32_t lso:1;

sys/dev/pci/if_ocereg.h

1597

uint32_t tcpcs:1;

sys/dev/pci/if_ocereg.h

1598

uint32_t udpcs:1;

sys/dev/pci/if_ocereg.h

1599

uint32_t ipcs:1;

sys/dev/pci/if_ocereg.h

1600

uint32_t rsvd3:1;

sys/dev/pci/if_ocereg.h

1601

uint32_t rsvd2:1;

sys/dev/pci/if_ocereg.h

1602

uint32_t forward:1;

sys/dev/pci/if_ocereg.h

1603

uint32_t crc:1;

sys/dev/pci/if_ocereg.h

1604

uint32_t event:1;

sys/dev/pci/if_ocereg.h

1605

uint32_t complete:1;

sys/dev/pci/if_ocereg.h

1608

uint32_t vlan_tag:16;

sys/dev/pci/if_ocereg.h

1609

uint32_t total_length:16;

sys/dev/pci/if_ocereg.h

1612

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

1615

uint32_t rsvd1:18;

sys/dev/pci/if_ocereg.h

1616

uint32_t last_seg_udp_len:14;

sys/dev/pci/if_ocereg.h

1619

uint32_t complete:1;

sys/dev/pci/if_ocereg.h

1620

uint32_t event:1;

sys/dev/pci/if_ocereg.h

1621

uint32_t crc:1;

sys/dev/pci/if_ocereg.h

1622

uint32_t forward:1;

sys/dev/pci/if_ocereg.h

1623

uint32_t rsvd2:1;

sys/dev/pci/if_ocereg.h

1624

uint32_t rsvd3:1;

sys/dev/pci/if_ocereg.h

1625

uint32_t ipcs:1;

sys/dev/pci/if_ocereg.h

1626

uint32_t udpcs:1;

sys/dev/pci/if_ocereg.h

1627

uint32_t tcpcs:1;

sys/dev/pci/if_ocereg.h

1628

uint32_t lso:1;

sys/dev/pci/if_ocereg.h

1629

uint32_t vlan:1;

sys/dev/pci/if_ocereg.h

1630

uint32_t rsvd4:2;

sys/dev/pci/if_ocereg.h

1631

uint32_t num_wqe:5;

sys/dev/pci/if_ocereg.h

1632

uint32_t lso_mss:14;

sys/dev/pci/if_ocereg.h

1635

uint32_t total_length:16;

sys/dev/pci/if_ocereg.h

1636

uint32_t vlan_tag:16;

sys/dev/pci/if_ocereg.h

1639

uint32_t dw[4];

sys/dev/pci/if_ocereg.h

1648

uint32_t frag_pa_hi;

sys/dev/pci/if_ocereg.h

1650

uint32_t frag_pa_lo;

sys/dev/pci/if_ocereg.h

1652

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

1653

uint32_t frag_len;

sys/dev/pci/if_ocereg.h

1655

uint32_t dw[4];

sys/dev/pci/if_ocereg.h

1665

uint32_t status:4;

sys/dev/pci/if_ocereg.h

1666

uint32_t rsvd0:8;

sys/dev/pci/if_ocereg.h

1667

uint32_t port:2;

sys/dev/pci/if_ocereg.h

1668

uint32_t ct:2;

sys/dev/pci/if_ocereg.h

1669

uint32_t wqe_index:16;

sys/dev/pci/if_ocereg.h

167

uint32_t length;

sys/dev/pci/if_ocereg.h

1671

uint32_t rsvd1:5;

sys/dev/pci/if_ocereg.h

1672

uint32_t cast_enc:2;

sys/dev/pci/if_ocereg.h

1673

uint32_t lso:1;

sys/dev/pci/if_ocereg.h

1674

uint32_t nwh_bytes:8;

sys/dev/pci/if_ocereg.h

1675

uint32_t user_bytes:16;

sys/dev/pci/if_ocereg.h

1677

uint32_t rsvd2;

sys/dev/pci/if_ocereg.h

1679

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

1680

uint32_t rsvd3:4;

sys/dev/pci/if_ocereg.h

1681

uint32_t wq_id:11;

sys/dev/pci/if_ocereg.h

1682

uint32_t num_pkts:16;

sys/dev/pci/if_ocereg.h

1685

uint32_t wqe_index:16;

sys/dev/pci/if_ocereg.h

1686

uint32_t ct:2;

sys/dev/pci/if_ocereg.h

1687

uint32_t port:2;

sys/dev/pci/if_ocereg.h

1688

uint32_t rsvd0:8;

sys/dev/pci/if_ocereg.h

1689

uint32_t status:4;

sys/dev/pci/if_ocereg.h

1691

uint32_t user_bytes:16;

sys/dev/pci/if_ocereg.h

1692

uint32_t nwh_bytes:8;

sys/dev/pci/if_ocereg.h

1693

uint32_t lso:1;

sys/dev/pci/if_ocereg.h

1694

uint32_t cast_enc:2;

sys/dev/pci/if_ocereg.h

1695

uint32_t rsvd1:5;

sys/dev/pci/if_ocereg.h

1697

uint32_t rsvd2;

sys/dev/pci/if_ocereg.h

1699

uint32_t num_pkts:16;

sys/dev/pci/if_ocereg.h

1700

uint32_t wq_id:11;

sys/dev/pci/if_ocereg.h

1701

uint32_t rsvd3:4;

sys/dev/pci/if_ocereg.h

1702

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

1705

uint32_t dw[4];

sys/dev/pci/if_ocereg.h

1715

uint32_t frag_pa_hi;

sys/dev/pci/if_ocereg.h

1716

uint32_t frag_pa_lo;

sys/dev/pci/if_ocereg.h

1718

uint32_t dw[2];

sys/dev/pci/if_ocereg.h

1728

uint32_t ip_options:1;

sys/dev/pci/if_ocereg.h

1729

uint32_t port:1;

sys/dev/pci/if_ocereg.h

1730

uint32_t pkt_size:14;

sys/dev/pci/if_ocereg.h

1731

uint32_t vlan_tag:16;

sys/dev/pci/if_ocereg.h

1733

uint32_t num_fragments:3;

sys/dev/pci/if_ocereg.h

1734

uint32_t switched:1;

sys/dev/pci/if_ocereg.h

1735

uint32_t ct:2;

sys/dev/pci/if_ocereg.h

1736

uint32_t frag_index:10;

sys/dev/pci/if_ocereg.h

1737

uint32_t rsvd0:1;

sys/dev/pci/if_ocereg.h

1738

uint32_t vlan_tag_present:1;

sys/dev/pci/if_ocereg.h

1739

uint32_t mac_dst:6;

sys/dev/pci/if_ocereg.h

1740

uint32_t ip_ver:1;

sys/dev/pci/if_ocereg.h

1741

uint32_t l4_cksum_pass:1;

sys/dev/pci/if_ocereg.h

1742

uint32_t ip_cksum_pass:1;

sys/dev/pci/if_ocereg.h

1743

uint32_t udpframe:1;

sys/dev/pci/if_ocereg.h

1744

uint32_t tcpframe:1;

sys/dev/pci/if_ocereg.h

1745

uint32_t ipframe:1;

sys/dev/pci/if_ocereg.h

1746

uint32_t rss_hp:1;

sys/dev/pci/if_ocereg.h

1747

uint32_t error:1;

sys/dev/pci/if_ocereg.h

1749

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

175

uint32_t timeout;

sys/dev/pci/if_ocereg.h

1750

uint32_t hds_type:2;

sys/dev/pci/if_ocereg.h

1751

uint32_t lro_pkt:1;

sys/dev/pci/if_ocereg.h

1752

uint32_t rsvd4:1;

sys/dev/pci/if_ocereg.h

1753

uint32_t hds_hdr_size:12;

sys/dev/pci/if_ocereg.h

1754

uint32_t hds_hdr_frag_index:10;

sys/dev/pci/if_ocereg.h

1755

uint32_t rss_bank:1;

sys/dev/pci/if_ocereg.h

1756

uint32_t qnq:1;

sys/dev/pci/if_ocereg.h

1757

uint32_t pkt_type:2;

sys/dev/pci/if_ocereg.h

1758

uint32_t rss_flush:1;

sys/dev/pci/if_ocereg.h

176

uint32_t length;

sys/dev/pci/if_ocereg.h

1760

uint32_t rss_hash_value;

sys/dev/pci/if_ocereg.h

1763

uint32_t vlan_tag:16;

sys/dev/pci/if_ocereg.h

1764

uint32_t pkt_size:14;

sys/dev/pci/if_ocereg.h

1765

uint32_t port:1;

sys/dev/pci/if_ocereg.h

1766

uint32_t ip_options:1;

sys/dev/pci/if_ocereg.h

1768

uint32_t error:1;

sys/dev/pci/if_ocereg.h

1769

uint32_t rss_hp:1;

sys/dev/pci/if_ocereg.h

1770

uint32_t ipframe:1;

sys/dev/pci/if_ocereg.h

1771

uint32_t tcpframe:1;

sys/dev/pci/if_ocereg.h

1772

uint32_t udpframe:1;

sys/dev/pci/if_ocereg.h

1773

uint32_t ip_cksum_pass:1;

sys/dev/pci/if_ocereg.h

1774

uint32_t l4_cksum_pass:1;

sys/dev/pci/if_ocereg.h

1775

uint32_t ip_ver:1;

sys/dev/pci/if_ocereg.h

1776

uint32_t mac_dst:6;

sys/dev/pci/if_ocereg.h

1777

uint32_t vlan_tag_present:1;

sys/dev/pci/if_ocereg.h

1778

uint32_t rsvd0:1;

sys/dev/pci/if_ocereg.h

1779

uint32_t frag_index:10;

sys/dev/pci/if_ocereg.h

1780

uint32_t ct:2;

sys/dev/pci/if_ocereg.h

1781

uint32_t switched:1;

sys/dev/pci/if_ocereg.h

1782

uint32_t num_fragments:3;

sys/dev/pci/if_ocereg.h

1784

uint32_t rss_flush:1;

sys/dev/pci/if_ocereg.h

1785

uint32_t pkt_type:2;

sys/dev/pci/if_ocereg.h

1786

uint32_t qnq:1;

sys/dev/pci/if_ocereg.h

1787

uint32_t rss_bank:1;

sys/dev/pci/if_ocereg.h

1788

uint32_t hds_hdr_frag_index:10;

sys/dev/pci/if_ocereg.h

1789

uint32_t hds_hdr_size:12;

sys/dev/pci/if_ocereg.h

1790

uint32_t rsvd4:1;

sys/dev/pci/if_ocereg.h

1791

uint32_t lro_pkt:1;

sys/dev/pci/if_ocereg.h

1792

uint32_t hds_type:2;

sys/dev/pci/if_ocereg.h

1793

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

1795

uint32_t rss_hash_value;

sys/dev/pci/if_ocereg.h

1798

uint32_t dw[4];

sys/dev/pci/if_ocereg.h

1808

uint32_t ip_options:1;

sys/dev/pci/if_ocereg.h

1809

uint32_t vlan_tag_present:1;

sys/dev/pci/if_ocereg.h

1810

uint32_t pkt_size:14;

sys/dev/pci/if_ocereg.h

1811

uint32_t vlan_tag:16;

sys/dev/pci/if_ocereg.h

1813

uint32_t num_fragments:3;

sys/dev/pci/if_ocereg.h

1814

uint32_t switched:1;

sys/dev/pci/if_ocereg.h

1815

uint32_t ct:2;

sys/dev/pci/if_ocereg.h

1816

uint32_t frag_index:10;

sys/dev/pci/if_ocereg.h

1817

uint32_t rsvd0:1;

sys/dev/pci/if_ocereg.h

1818

uint32_t mac_dst:7;

sys/dev/pci/if_ocereg.h

1819

uint32_t ip_ver:1;

sys/dev/pci/if_ocereg.h

1820

uint32_t l4_cksum_pass:1;

sys/dev/pci/if_ocereg.h

1821

uint32_t ip_cksum_pass:1;

sys/dev/pci/if_ocereg.h

1822

uint32_t udpframe:1;

sys/dev/pci/if_ocereg.h

1823

uint32_t tcpframe:1;

sys/dev/pci/if_ocereg.h

1824

uint32_t ipframe:1;

sys/dev/pci/if_ocereg.h

1825

uint32_t rss_hp:1;

sys/dev/pci/if_ocereg.h

1826

uint32_t error:1;

sys/dev/pci/if_ocereg.h

1828

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

1829

uint32_t rsvd4:13;

sys/dev/pci/if_ocereg.h

1830

uint32_t hds_hdr_size:2;

sys/dev/pci/if_ocereg.h

1831

uint32_t hds_hdr_frag_index:8;

sys/dev/pci/if_ocereg.h

1832

uint32_t vlantag:1;

sys/dev/pci/if_ocereg.h

1833

uint32_t port:2;

sys/dev/pci/if_ocereg.h

1834

uint32_t rss_bank:1;

sys/dev/pci/if_ocereg.h

1835

uint32_t qnq:1;

sys/dev/pci/if_ocereg.h

1836

uint32_t pkt_type:2;

sys/dev/pci/if_ocereg.h

1837

uint32_t rss_flush:1;

sys/dev/pci/if_ocereg.h

1839

uint32_t rss_hash_value;

sys/dev/pci/if_ocereg.h

1842

uint32_t vlan_tag:16;

sys/dev/pci/if_ocereg.h

1843

uint32_t pkt_size:14;

sys/dev/pci/if_ocereg.h

1844

uint32_t vlan_tag_present:1;

sys/dev/pci/if_ocereg.h

1845

uint32_t ip_options:1;

sys/dev/pci/if_ocereg.h

1847

uint32_t error:1;

sys/dev/pci/if_ocereg.h

1848

uint32_t rss_hp:1;

sys/dev/pci/if_ocereg.h

1849

uint32_t ipframe:1;

sys/dev/pci/if_ocereg.h

1850

uint32_t tcpframe:1;

sys/dev/pci/if_ocereg.h

1851

uint32_t udpframe:1;

sys/dev/pci/if_ocereg.h

1852

uint32_t ip_cksum_pass:1;

sys/dev/pci/if_ocereg.h

1853

uint32_t l4_cksum_pass:1;

sys/dev/pci/if_ocereg.h

1854

uint32_t ip_ver:1;

sys/dev/pci/if_ocereg.h

1855

uint32_t mac_dst:7;

sys/dev/pci/if_ocereg.h

1856

uint32_t rsvd0:1;

sys/dev/pci/if_ocereg.h

1857

uint32_t frag_index:10;

sys/dev/pci/if_ocereg.h

1858

uint32_t ct:2;

sys/dev/pci/if_ocereg.h

1859

uint32_t switched:1;

sys/dev/pci/if_ocereg.h

1860

uint32_t num_fragments:3;

sys/dev/pci/if_ocereg.h

1862

uint32_t rss_flush:1;

sys/dev/pci/if_ocereg.h

1863

uint32_t pkt_type:2;

sys/dev/pci/if_ocereg.h

1864

uint32_t qnq:1;

sys/dev/pci/if_ocereg.h

1865

uint32_t rss_bank:1;

sys/dev/pci/if_ocereg.h

1866

uint32_t port:2;

sys/dev/pci/if_ocereg.h

1867

uint32_t vlantag:1;

sys/dev/pci/if_ocereg.h

1868

uint32_t hds_hdr_frag_index:8;

sys/dev/pci/if_ocereg.h

1869

uint32_t hds_hdr_size:2;

sys/dev/pci/if_ocereg.h

1870

uint32_t rsvd4:13;

sys/dev/pci/if_ocereg.h

1871

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

1873

uint32_t rss_hash_value;

sys/dev/pci/if_ocereg.h

1876

uint32_t dw[4];

sys/dev/pci/if_ocereg.h

188

uint32_t flags;

sys/dev/pci/if_ocereg.h

1899

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

1905

uint32_t dw[17];

sys/dev/pci/if_ocereg.h

1909

uint32_t dw4rsvd2:8;

sys/dev/pci/if_ocereg.h

191

uint32_t payload_length;

sys/dev/pci/if_ocereg.h

1910

uint32_t nic_wq_type:8;

sys/dev/pci/if_ocereg.h

1911

uint32_t dw4rsvd1:8;

sys/dev/pci/if_ocereg.h

1912

uint32_t num_pages:8;

sys/dev/pci/if_ocereg.h

1914

uint32_t dw5rsvd2:12;

sys/dev/pci/if_ocereg.h

1915

uint32_t wq_size:4;

sys/dev/pci/if_ocereg.h

1916

uint32_t dw5rsvd1:16;

sys/dev/pci/if_ocereg.h

1918

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

1919

uint32_t dw6rsvd1:31;

sys/dev/pci/if_ocereg.h

192

uint32_t tag[2];

sys/dev/pci/if_ocereg.h

1921

uint32_t dw7rsvd1:16;

sys/dev/pci/if_ocereg.h

1922

uint32_t cq_id:16;

sys/dev/pci/if_ocereg.h

1925

uint32_t num_pages:8;

sys/dev/pci/if_ocereg.h

1927

uint32_t dw4rsvd1:8;

sys/dev/pci/if_ocereg.h

193

uint32_t _rsvd;

sys/dev/pci/if_ocereg.h

1930

uint32_t ulp_mask:8;

sys/dev/pci/if_ocereg.h

1932

uint32_t nic_wq_type:8;

sys/dev/pci/if_ocereg.h

1933

uint32_t dw4rsvd2:8;

sys/dev/pci/if_ocereg.h

1935

uint32_t dw5rsvd1:16;

sys/dev/pci/if_ocereg.h

1936

uint32_t wq_size:4;

sys/dev/pci/if_ocereg.h

1937

uint32_t dw5rsvd2:12;

sys/dev/pci/if_ocereg.h

1939

uint32_t dw6rsvd1:31;

sys/dev/pci/if_ocereg.h

1940

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

1942

uint32_t cq_id:16;

sys/dev/pci/if_ocereg.h

1943

uint32_t dw7rsvd1:16;

sys/dev/pci/if_ocereg.h

1946

uint32_t dw8_20rsvd1[13];

sys/dev/pci/if_ocereg.h

1951

uint32_t dw4rsvd2:8;

sys/dev/pci/if_ocereg.h

1952

uint32_t nic_wq_type:8;

sys/dev/pci/if_ocereg.h

1953

uint32_t dw4rsvd1:8;

sys/dev/pci/if_ocereg.h

1954

uint32_t num_pages:8;

sys/dev/pci/if_ocereg.h

1956

uint32_t dw5rsvd2:12;

sys/dev/pci/if_ocereg.h

1957

uint32_t wq_size:4;

sys/dev/pci/if_ocereg.h

1958

uint32_t iface_id:16;

sys/dev/pci/if_ocereg.h

1960

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

1961

uint32_t dw6rsvd1:31;

sys/dev/pci/if_ocereg.h

1963

uint32_t dw7rsvd1:16;

sys/dev/pci/if_ocereg.h

1964

uint32_t cq_id:16;

sys/dev/pci/if_ocereg.h

1967

uint32_t num_pages:8;

sys/dev/pci/if_ocereg.h

1968

uint32_t dw4rsvd1:8;

sys/dev/pci/if_ocereg.h

1969

uint32_t nic_wq_type:8;

sys/dev/pci/if_ocereg.h

1970

uint32_t dw4rsvd2:8;

sys/dev/pci/if_ocereg.h

1972

uint32_t iface_id:16;

sys/dev/pci/if_ocereg.h

1973

uint32_t wq_size:4;

sys/dev/pci/if_ocereg.h

1974

uint32_t dw5rsvd2:12;

sys/dev/pci/if_ocereg.h

1976

uint32_t dw6rsvd1:31;

sys/dev/pci/if_ocereg.h

1977

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

1979

uint32_t cq_id:16;

sys/dev/pci/if_ocereg.h

1980

uint32_t dw7rsvd1:16;

sys/dev/pci/if_ocereg.h

1983

uint32_t dw8_20rsvd1[13];

sys/dev/pci/if_ocereg.h

2006

uint32_t rsvd2;

sys/dev/pci/if_ocereg.h

2009

uint32_t rsvd4[13];

sys/dev/pci/if_ocereg.h

2016

uint32_t db_offset;

sys/dev/pci/if_ocereg.h

2040

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

2053

uint32_t if_id;

sys/dev/pci/if_ocereg.h

2056

uint32_t is_rss_queue;

sys/dev/pci/if_ocereg.h

206

uint32_t extended_status:16;

sys/dev/pci/if_ocereg.h

207

uint32_t completion_status:16;

sys/dev/pci/if_ocereg.h

2086

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

209

uint32_t mq_tag[2];

sys/dev/pci/if_ocereg.h

2092

uint32_t rx_bytes_lsd; /* dword 0*/

sys/dev/pci/if_ocereg.h

2093

uint32_t rx_bytes_msd; /* dword 1*/

sys/dev/pci/if_ocereg.h

2094

uint32_t rx_total_frames; /* dword 2*/

sys/dev/pci/if_ocereg.h

2095

uint32_t rx_unicast_frames; /* dword 3*/

sys/dev/pci/if_ocereg.h

2096

uint32_t rx_multicast_frames; /* dword 4*/

sys/dev/pci/if_ocereg.h

2097

uint32_t rx_broadcast_frames; /* dword 5*/

sys/dev/pci/if_ocereg.h

2098

uint32_t rx_crc_errors; /* dword 6*/

sys/dev/pci/if_ocereg.h

2099

uint32_t rx_alignment_symbol_errors; /* dword 7*/

sys/dev/pci/if_ocereg.h

2100

uint32_t rx_pause_frames; /* dword 8*/

sys/dev/pci/if_ocereg.h

2101

uint32_t rx_control_frames; /* dword 9*/

sys/dev/pci/if_ocereg.h

2102

uint32_t rx_in_range_errors; /* dword 10*/

sys/dev/pci/if_ocereg.h

2103

uint32_t rx_out_range_errors; /* dword 11*/

sys/dev/pci/if_ocereg.h

2104

uint32_t rx_frame_too_long; /* dword 12*/

sys/dev/pci/if_ocereg.h

2105

uint32_t rx_address_match_errors; /* dword 13*/

sys/dev/pci/if_ocereg.h

2106

uint32_t rx_vlan_mismatch; /* dword 14*/

sys/dev/pci/if_ocereg.h

2107

uint32_t rx_dropped_too_small; /* dword 15*/

sys/dev/pci/if_ocereg.h

2108

uint32_t rx_dropped_too_short; /* dword 16*/

sys/dev/pci/if_ocereg.h

2109

uint32_t rx_dropped_header_too_small; /* dword 17*/

sys/dev/pci/if_ocereg.h

211

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

2110

uint32_t rx_dropped_tcp_length; /* dword 18*/

sys/dev/pci/if_ocereg.h

2111

uint32_t rx_dropped_runt; /* dword 19*/

sys/dev/pci/if_ocereg.h

2112

uint32_t rx_64_byte_packets; /* dword 20*/

sys/dev/pci/if_ocereg.h

2113

uint32_t rx_65_127_byte_packets; /* dword 21*/

sys/dev/pci/if_ocereg.h

2114

uint32_t rx_128_256_byte_packets; /* dword 22*/

sys/dev/pci/if_ocereg.h

2115

uint32_t rx_256_511_byte_packets; /* dword 23*/

sys/dev/pci/if_ocereg.h

2116

uint32_t rx_512_1023_byte_packets; /* dword 24*/

sys/dev/pci/if_ocereg.h

2117

uint32_t rx_1024_1518_byte_packets; /* dword 25*/

sys/dev/pci/if_ocereg.h

2118

uint32_t rx_1519_2047_byte_packets; /* dword 26*/

sys/dev/pci/if_ocereg.h

2119

uint32_t rx_2048_4095_byte_packets; /* dword 27*/

sys/dev/pci/if_ocereg.h

212

uint32_t async_event:1;

sys/dev/pci/if_ocereg.h

2120

uint32_t rx_4096_8191_byte_packets; /* dword 28*/

sys/dev/pci/if_ocereg.h

2121

uint32_t rx_8192_9216_byte_packets; /* dword 29*/

sys/dev/pci/if_ocereg.h

2122

uint32_t rx_ip_checksum_errs; /* dword 30*/

sys/dev/pci/if_ocereg.h

2123

uint32_t rx_tcp_checksum_errs; /* dword 31*/

sys/dev/pci/if_ocereg.h

2124

uint32_t rx_udp_checksum_errs; /* dword 32*/

sys/dev/pci/if_ocereg.h

2125

uint32_t rx_non_rss_packets; /* dword 33*/

sys/dev/pci/if_ocereg.h

2126

uint32_t rx_ipv4_packets; /* dword 34*/

sys/dev/pci/if_ocereg.h

2127

uint32_t rx_ipv6_packets; /* dword 35*/

sys/dev/pci/if_ocereg.h

2128

uint32_t rx_ipv4_bytes_lsd; /* dword 36*/

sys/dev/pci/if_ocereg.h

2129

uint32_t rx_ipv4_bytes_msd; /* dword 37*/

sys/dev/pci/if_ocereg.h

213

uint32_t hpi_buffer_cmpl:1;

sys/dev/pci/if_ocereg.h

2130

uint32_t rx_ipv6_bytes_lsd; /* dword 38*/

sys/dev/pci/if_ocereg.h

2131

uint32_t rx_ipv6_bytes_msd; /* dword 39*/

sys/dev/pci/if_ocereg.h

2132

uint32_t rx_chute1_packets; /* dword 40*/

sys/dev/pci/if_ocereg.h

2133

uint32_t rx_chute2_packets; /* dword 41*/

sys/dev/pci/if_ocereg.h

2134

uint32_t rx_chute3_packets; /* dword 42*/

sys/dev/pci/if_ocereg.h

2135

uint32_t rx_management_packets; /* dword 43*/

sys/dev/pci/if_ocereg.h

2136

uint32_t rx_switched_unicast_packets; /* dword 44*/

sys/dev/pci/if_ocereg.h

2137

uint32_t rx_switched_multicast_packets; /* dword 45*/

sys/dev/pci/if_ocereg.h

2138

uint32_t rx_switched_broadcast_packets; /* dword 46*/

sys/dev/pci/if_ocereg.h

2139

uint32_t tx_bytes_lsd; /* dword 47*/

sys/dev/pci/if_ocereg.h

214

uint32_t completed:1;

sys/dev/pci/if_ocereg.h

2140

uint32_t tx_bytes_msd; /* dword 48*/

sys/dev/pci/if_ocereg.h

2141

uint32_t tx_unicastframes; /* dword 49*/

sys/dev/pci/if_ocereg.h

2142

uint32_t tx_multicastframes; /* dword 50*/

sys/dev/pci/if_ocereg.h

2143

uint32_t tx_broadcastframes; /* dword 51*/

sys/dev/pci/if_ocereg.h

2144

uint32_t tx_pauseframes; /* dword 52*/

sys/dev/pci/if_ocereg.h

2145

uint32_t tx_controlframes; /* dword 53*/

sys/dev/pci/if_ocereg.h

2146

uint32_t tx_64_byte_packets; /* dword 54*/

sys/dev/pci/if_ocereg.h

2147

uint32_t tx_65_127_byte_packets; /* dword 55*/

sys/dev/pci/if_ocereg.h

2148

uint32_t tx_128_256_byte_packets; /* dword 56*/

sys/dev/pci/if_ocereg.h

2149

uint32_t tx_256_511_byte_packets; /* dword 57*/

sys/dev/pci/if_ocereg.h

215

uint32_t consumed:1;

sys/dev/pci/if_ocereg.h

2150

uint32_t tx_512_1023_byte_packets; /* dword 58*/

sys/dev/pci/if_ocereg.h

2151

uint32_t tx_1024_1518_byte_packets; /* dword 59*/

sys/dev/pci/if_ocereg.h

2152

uint32_t tx_1519_2047_byte_packets; /* dword 60*/

sys/dev/pci/if_ocereg.h

2153

uint32_t tx_2048_4095_byte_packets; /* dword 61*/

sys/dev/pci/if_ocereg.h

2154

uint32_t tx_4096_8191_byte_packets; /* dword 62*/

sys/dev/pci/if_ocereg.h

2155

uint32_t tx_8192_9216_byte_packets; /* dword 63*/

sys/dev/pci/if_ocereg.h

2156

uint32_t rxpp_fifo_overflow_drop; /* dword 64*/

sys/dev/pci/if_ocereg.h

2157

uint32_t rx_input_fifo_overflow_drop; /* dword 65*/

sys/dev/pci/if_ocereg.h

216

uint32_t rsvd0:3;

sys/dev/pci/if_ocereg.h

2162

uint32_t rx_drops_no_pbuf; /* dword 132*/

sys/dev/pci/if_ocereg.h

2163

uint32_t rx_drops_no_txpb; /* dword 133*/

sys/dev/pci/if_ocereg.h

2164

uint32_t rx_drops_no_erx_descr; /* dword 134*/

sys/dev/pci/if_ocereg.h

2165

uint32_t rx_drops_no_tpre_descr; /* dword 135*/

sys/dev/pci/if_ocereg.h

2166

uint32_t management_rx_port_packets; /* dword 136*/

sys/dev/pci/if_ocereg.h

2167

uint32_t management_rx_port_bytes; /* dword 137*/

sys/dev/pci/if_ocereg.h

2168

uint32_t management_rx_port_pause_frames;/* dword 138*/

sys/dev/pci/if_ocereg.h

2169

uint32_t management_rx_port_errors; /* dword 139*/

sys/dev/pci/if_ocereg.h

217

uint32_t async_type:8;

sys/dev/pci/if_ocereg.h

2170

uint32_t management_tx_port_packets; /* dword 140*/

sys/dev/pci/if_ocereg.h

2171

uint32_t management_tx_port_bytes; /* dword 141*/

sys/dev/pci/if_ocereg.h

2172

uint32_t management_tx_port_pause; /* dword 142*/

sys/dev/pci/if_ocereg.h

2173

uint32_t management_rx_port_rxfifo_overflow; /* dword 143*/

sys/dev/pci/if_ocereg.h

2174

uint32_t rx_drops_too_many_frags; /* dword 144*/

sys/dev/pci/if_ocereg.h

2175

uint32_t rx_drops_invalid_ring; /* dword 145*/

sys/dev/pci/if_ocereg.h

2176

uint32_t forwarded_packets; /* dword 146*/

sys/dev/pci/if_ocereg.h

2177

uint32_t rx_drops_mtu; /* dword 147*/

sys/dev/pci/if_ocereg.h

2178

uint32_t rsvd0[7];

sys/dev/pci/if_ocereg.h

2179

uint32_t port0_jabber_events;

sys/dev/pci/if_ocereg.h

218

uint32_t event_type:8;

sys/dev/pci/if_ocereg.h

2180

uint32_t port1_jabber_events;

sys/dev/pci/if_ocereg.h

2181

uint32_t rsvd1[6];

sys/dev/pci/if_ocereg.h

2185

uint32_t rsvd0[12];

sys/dev/pci/if_ocereg.h

2186

uint32_t rx_crc_errors;

sys/dev/pci/if_ocereg.h

2187

uint32_t rx_alignment_symbol_errors;

sys/dev/pci/if_ocereg.h

2188

uint32_t rx_pause_frames;

sys/dev/pci/if_ocereg.h

2189

uint32_t rx_priority_pause_frames;

sys/dev/pci/if_ocereg.h

219

uint32_t rsvd1:8;

sys/dev/pci/if_ocereg.h

2190

uint32_t rx_control_frames;

sys/dev/pci/if_ocereg.h

2191

uint32_t rx_in_range_errors;

sys/dev/pci/if_ocereg.h

2192

uint32_t rx_out_range_errors;

sys/dev/pci/if_ocereg.h

2193

uint32_t rx_frame_too_long;

sys/dev/pci/if_ocereg.h

2194

uint32_t rx_address_match_errors;

sys/dev/pci/if_ocereg.h

2195

uint32_t rx_dropped_too_small;

sys/dev/pci/if_ocereg.h

2196

uint32_t rx_dropped_too_short;

sys/dev/pci/if_ocereg.h

2197

uint32_t rx_dropped_header_too_small;

sys/dev/pci/if_ocereg.h

2198

uint32_t rx_dropped_tcp_length;

sys/dev/pci/if_ocereg.h

2199

uint32_t rx_dropped_runt;

sys/dev/pci/if_ocereg.h

2200

uint32_t rsvd1[10];

sys/dev/pci/if_ocereg.h

2201

uint32_t rx_ip_checksum_errs;

sys/dev/pci/if_ocereg.h

2202

uint32_t rx_tcp_checksum_errs;

sys/dev/pci/if_ocereg.h

2203

uint32_t rx_udp_checksum_errs;

sys/dev/pci/if_ocereg.h

2204

uint32_t rsvd2[7];

sys/dev/pci/if_ocereg.h

2205

uint32_t rx_switched_unicast_packets;

sys/dev/pci/if_ocereg.h

2206

uint32_t rx_switched_multicast_packets;

sys/dev/pci/if_ocereg.h

2207

uint32_t rx_switched_broadcast_packets;

sys/dev/pci/if_ocereg.h

2208

uint32_t rsvd3[3];

sys/dev/pci/if_ocereg.h

2209

uint32_t tx_pauseframes;

sys/dev/pci/if_ocereg.h

2210

uint32_t tx_priority_pauseframes;

sys/dev/pci/if_ocereg.h

2211

uint32_t tx_controlframes;

sys/dev/pci/if_ocereg.h

2212

uint32_t rsvd4[10];

sys/dev/pci/if_ocereg.h

2213

uint32_t rxpp_fifo_overflow_drop;

sys/dev/pci/if_ocereg.h

2214

uint32_t rx_input_fifo_overflow_drop;

sys/dev/pci/if_ocereg.h

2215

uint32_t pmem_fifo_overflow_drop;

sys/dev/pci/if_ocereg.h

2216

uint32_t jabber_events;

sys/dev/pci/if_ocereg.h

2217

uint32_t rsvd5[3];

sys/dev/pci/if_ocereg.h

222

uint32_t completion_status:16;

sys/dev/pci/if_ocereg.h

2222

uint32_t rsvd0[2];

sys/dev/pci/if_ocereg.h

2223

uint32_t rx_drops_no_pbuf;

sys/dev/pci/if_ocereg.h

2224

uint32_t rx_drops_no_txpb;

sys/dev/pci/if_ocereg.h

2225

uint32_t rx_drops_no_erx_descr;

sys/dev/pci/if_ocereg.h

2226

uint32_t rx_drops_no_tpre_descr;

sys/dev/pci/if_ocereg.h

2227

uint32_t rsvd1[6];

sys/dev/pci/if_ocereg.h

2228

uint32_t rx_drops_too_many_frags;

sys/dev/pci/if_ocereg.h

2229

uint32_t rx_drops_invalid_ring;

sys/dev/pci/if_ocereg.h

223

uint32_t extended_status:16;

sys/dev/pci/if_ocereg.h

2230

uint32_t forwarded_packets;

sys/dev/pci/if_ocereg.h

2231

uint32_t rx_drops_mtu;

sys/dev/pci/if_ocereg.h

2232

uint32_t rsvd2[14];

sys/dev/pci/if_ocereg.h

2236

uint32_t rx_drops_no_fragments[68];

sys/dev/pci/if_ocereg.h

2237

uint32_t rsvd[4];

sys/dev/pci/if_ocereg.h

2242

uint32_t rx_drops_no_fragments[44];

sys/dev/pci/if_ocereg.h

2243

uint32_t rsvd[4];

sys/dev/pci/if_ocereg.h

2247

uint32_t eth_red_drops;

sys/dev/pci/if_ocereg.h

2248

uint32_t rsvd[5];

sys/dev/pci/if_ocereg.h

225

uint32_t mq_tag[2];

sys/dev/pci/if_ocereg.h

2253

uint32_t rsvd0[OCE_TXP_SW_SZ];

sys/dev/pci/if_ocereg.h

2256

uint32_t rsvd1[18];

sys/dev/pci/if_ocereg.h

2261

uint32_t rsvd[48];

sys/dev/pci/if_ocereg.h

227

uint32_t rsvd1:8;

sys/dev/pci/if_ocereg.h

2270

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

228

uint32_t event_type:8;

sys/dev/pci/if_ocereg.h

2283

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

229

uint32_t async_type:8;

sys/dev/pci/if_ocereg.h

230

uint32_t rsvd0:3;

sys/dev/pci/if_ocereg.h

231

uint32_t consumed:1;

sys/dev/pci/if_ocereg.h

232

uint32_t completed:1;

sys/dev/pci/if_ocereg.h

2328

uint32_t rx_unknown_protos;

sys/dev/pci/if_ocereg.h

2329

uint32_t reserved_word69;

sys/dev/pci/if_ocereg.h

233

uint32_t hpi_buffer_cmpl:1;

sys/dev/pci/if_ocereg.h

234

uint32_t async_event:1;

sys/dev/pci/if_ocereg.h

2340

uint32_t rx_undersize_pkts;

sys/dev/pci/if_ocereg.h

2341

uint32_t rx_oversize_pkts;

sys/dev/pci/if_ocereg.h

2342

uint32_t rx_fragment_pkts;

sys/dev/pci/if_ocereg.h

2343

uint32_t rx_jabbers;

sys/dev/pci/if_ocereg.h

2346

uint32_t rx_in_range_errors;

sys/dev/pci/if_ocereg.h

2347

uint32_t rx_out_of_range_errors;

sys/dev/pci/if_ocereg.h

2348

uint32_t rx_address_match_errors;

sys/dev/pci/if_ocereg.h

2349

uint32_t rx_vlan_mismatch_errors;

sys/dev/pci/if_ocereg.h

235

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

2350

uint32_t rx_dropped_too_small;

sys/dev/pci/if_ocereg.h

2351

uint32_t rx_dropped_too_short;

sys/dev/pci/if_ocereg.h

2352

uint32_t rx_dropped_header_too_small;

sys/dev/pci/if_ocereg.h

2353

uint32_t rx_dropped_invalid_tcp_length;

sys/dev/pci/if_ocereg.h

2354

uint32_t rx_dropped_runt;

sys/dev/pci/if_ocereg.h

2355

uint32_t rx_ip_checksum_errors;

sys/dev/pci/if_ocereg.h

2356

uint32_t rx_tcp_checksum_errors;

sys/dev/pci/if_ocereg.h

2357

uint32_t rx_udp_checksum_errors;

sys/dev/pci/if_ocereg.h

2358

uint32_t rx_non_rss_pkts;

sys/dev/pci/if_ocereg.h

2372

uint32_t rx_fifo_overflow;

sys/dev/pci/if_ocereg.h

2373

uint32_t rx_input_fifo_overflow;

sys/dev/pci/if_ocereg.h

2375

uint32_t rx_drops_invalid_queue;

sys/dev/pci/if_ocereg.h

2376

uint32_t reserved_word141;

sys/dev/pci/if_ocereg.h

238

uint32_t dw[4];

sys/dev/pci/if_ocereg.h

2397

uint32_t reset_stats:8;

sys/dev/pci/if_ocereg.h

2398

uint32_t rsvd0:8;

sys/dev/pci/if_ocereg.h

2399

uint32_t port_number:16;

sys/dev/pci/if_ocereg.h

2401

uint32_t port_number:16;

sys/dev/pci/if_ocereg.h

2402

uint32_t rsvd0:8;

sys/dev/pci/if_ocereg.h

2403

uint32_t reset_stats:8;

sys/dev/pci/if_ocereg.h

2409

uint32_t pport_stats[164 - 4 + 1];

sys/dev/pci/if_ocereg.h

2460

uint32_t reset_stats:8;

sys/dev/pci/if_ocereg.h

2461

uint32_t rsvd0:8;

sys/dev/pci/if_ocereg.h

2462

uint32_t vport_number:16;

sys/dev/pci/if_ocereg.h

2464

uint32_t vport_number:16;

sys/dev/pci/if_ocereg.h

2465

uint32_t rsvd0:8;

sys/dev/pci/if_ocereg.h

2466

uint32_t reset_stats:8;

sys/dev/pci/if_ocereg.h

2472

uint32_t vport_stats[75 - 4 + 1];

sys/dev/pci/if_ocereg.h

2495

uint32_t if_id;

sys/dev/pci/if_ocereg.h

2498

uint32_t hash[OCE_HASH_TBL_SZ];

sys/dev/pci/if_ocereg.h

2503

uint32_t if_id;

sys/dev/pci/if_ocereg.h

2506

uint32_t hash[OCE_HASH_TBL_SZ];

sys/dev/pci/if_ocereg.h

269

uint32_t event_tag;

sys/dev/pci/if_ocereg.h

271

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

272

uint32_t async_event:1;

sys/dev/pci/if_ocereg.h

273

uint32_t rsvd2:6;

sys/dev/pci/if_ocereg.h

274

uint32_t event_type:8;

sys/dev/pci/if_ocereg.h

275

uint32_t event_code:8;

sys/dev/pci/if_ocereg.h

276

uint32_t rsvd1:8;

sys/dev/pci/if_ocereg.h

288

uint32_t event_tag;

sys/dev/pci/if_ocereg.h

290

uint32_t rsvd1:8;

sys/dev/pci/if_ocereg.h

291

uint32_t event_code:8;

sys/dev/pci/if_ocereg.h

292

uint32_t event_type:8;

sys/dev/pci/if_ocereg.h

293

uint32_t rsvd2:6;

sys/dev/pci/if_ocereg.h

294

uint32_t async_event:1;

sys/dev/pci/if_ocereg.h

295

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

298

uint32_t dw[4];

sys/dev/pci/if_ocereg.h

307

uint32_t event_tag;

sys/dev/pci/if_ocereg.h

308

uint32_t rsvd1;

sys/dev/pci/if_ocereg.h

309

uint32_t code;

sys/dev/pci/if_ocereg.h

313

uint32_t dw[6];

sys/dev/pci/if_ocereg.h

317

uint32_t dw4rsvd1:16;

sys/dev/pci/if_ocereg.h

318

uint32_t num_pages:16;

sys/dev/pci/if_ocereg.h

320

uint32_t async_evt_bitmap;

sys/dev/pci/if_ocereg.h

322

uint32_t cq_id:10;

sys/dev/pci/if_ocereg.h

323

uint32_t dw5rsvd2:2;

sys/dev/pci/if_ocereg.h

324

uint32_t ring_size:4;

sys/dev/pci/if_ocereg.h

325

uint32_t dw5rsvd1:16;

sys/dev/pci/if_ocereg.h

327

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

328

uint32_t dw6rsvd1:31;

sys/dev/pci/if_ocereg.h

330

uint32_t dw7rsvd1:21;

sys/dev/pci/if_ocereg.h

331

uint32_t async_cq_id:10;

sys/dev/pci/if_ocereg.h

332

uint32_t async_cq_valid:1;

sys/dev/pci/if_ocereg.h

335

uint32_t num_pages:16;

sys/dev/pci/if_ocereg.h

336

uint32_t dw4rsvd1:16;

sys/dev/pci/if_ocereg.h

338

uint32_t async_evt_bitmap;

sys/dev/pci/if_ocereg.h

340

uint32_t dw5rsvd1:16;

sys/dev/pci/if_ocereg.h

341

uint32_t ring_size:4;

sys/dev/pci/if_ocereg.h

342

uint32_t dw5rsvd2:2;

sys/dev/pci/if_ocereg.h

343

uint32_t cq_id:10;

sys/dev/pci/if_ocereg.h

345

uint32_t dw6rsvd1:31;

sys/dev/pci/if_ocereg.h

346

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

348

uint32_t async_cq_valid:1;

sys/dev/pci/if_ocereg.h

349

uint32_t async_cq_id:10;

sys/dev/pci/if_ocereg.h

350

uint32_t dw7rsvd1:21;

sys/dev/pci/if_ocereg.h

353

uint32_t dw8rsvd1;

sys/dev/pci/if_ocereg.h

487

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

500

uint32_t logical_link_status;

sys/dev/pci/if_ocereg.h

524

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

527

uint32_t dw;

sys/dev/pci/if_ocereg.h

580

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

583

uint32_t dw[2];

sys/dev/pci/if_ocereg.h

604

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

607

uint32_t dw[49];

sys/dev/pci/if_ocereg.h

637

uint32_t version;

sys/dev/pci/if_ocereg.h

638

uint32_t cap_flags;

sys/dev/pci/if_ocereg.h

639

uint32_t enable_flags;

sys/dev/pci/if_ocereg.h

647

uint32_t if_id;

sys/dev/pci/if_ocereg.h

648

uint32_t pmac_id;

sys/dev/pci/if_ocereg.h

650

uint32_t dw[4];

sys/dev/pci/if_ocereg.h

659

uint32_t if_id;

sys/dev/pci/if_ocereg.h

663

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

666

uint32_t dw;

sys/dev/pci/if_ocereg.h

674

uint32_t evnt;

sys/dev/pci/if_ocereg.h

680

uint32_t dw4rsvd1:16;

sys/dev/pci/if_ocereg.h

681

uint32_t num_pages:16;

sys/dev/pci/if_ocereg.h

683

uint32_t size:1;

sys/dev/pci/if_ocereg.h

684

uint32_t dw5rsvd2:1;

sys/dev/pci/if_ocereg.h

685

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

686

uint32_t dw5rsvd1:29;

sys/dev/pci/if_ocereg.h

688

uint32_t armed:1;

sys/dev/pci/if_ocereg.h

689

uint32_t dw6rsvd2:2;

sys/dev/pci/if_ocereg.h

690

uint32_t count:3;

sys/dev/pci/if_ocereg.h

691

uint32_t dw6rsvd1:26;

sys/dev/pci/if_ocereg.h

693

uint32_t dw7rsvd2:9;

sys/dev/pci/if_ocereg.h

694

uint32_t delay_mult:10;

sys/dev/pci/if_ocereg.h

695

uint32_t dw7rsvd1:13;

sys/dev/pci/if_ocereg.h

697

uint32_t dw8rsvd1;

sys/dev/pci/if_ocereg.h

699

uint32_t num_pages:16;

sys/dev/pci/if_ocereg.h

700

uint32_t dw4rsvd1:16;

sys/dev/pci/if_ocereg.h

702

uint32_t dw5rsvd1:29;

sys/dev/pci/if_ocereg.h

703

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

704

uint32_t dw5rsvd2:1;

sys/dev/pci/if_ocereg.h

705

uint32_t size:1;

sys/dev/pci/if_ocereg.h

707

uint32_t dw6rsvd1:26;

sys/dev/pci/if_ocereg.h

708

uint32_t count:3;

sys/dev/pci/if_ocereg.h

709

uint32_t dw6rsvd2:2;

sys/dev/pci/if_ocereg.h

710

uint32_t armed:1;

sys/dev/pci/if_ocereg.h

712

uint32_t dw7rsvd1:13;

sys/dev/pci/if_ocereg.h

713

uint32_t delay_mult:10;

sys/dev/pci/if_ocereg.h

714

uint32_t dw7rsvd2:9;

sys/dev/pci/if_ocereg.h

716

uint32_t dw8rsvd1;

sys/dev/pci/if_ocereg.h

751

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

758

uint32_t dw[5];

sys/dev/pci/if_ocereg.h

762

uint32_t dw4rsvd1:16;

sys/dev/pci/if_ocereg.h

763

uint32_t num_pages:16;

sys/dev/pci/if_ocereg.h

765

uint32_t eventable:1;

sys/dev/pci/if_ocereg.h

766

uint32_t dw5rsvd3:1;

sys/dev/pci/if_ocereg.h

767

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

768

uint32_t count:2;

sys/dev/pci/if_ocereg.h

769

uint32_t dw5rsvd2:12;

sys/dev/pci/if_ocereg.h

770

uint32_t nodelay:1;

sys/dev/pci/if_ocereg.h

771

uint32_t coalesce_wm:2;

sys/dev/pci/if_ocereg.h

772

uint32_t dw5rsvd1:12;

sys/dev/pci/if_ocereg.h

774

uint32_t armed:1;

sys/dev/pci/if_ocereg.h

775

uint32_t dw6rsvd2:1;

sys/dev/pci/if_ocereg.h

776

uint32_t eq_id:8;

sys/dev/pci/if_ocereg.h

777

uint32_t dw6rsvd1:22;

sys/dev/pci/if_ocereg.h

780

uint32_t num_pages:16;

sys/dev/pci/if_ocereg.h

781

uint32_t dw4rsvd1:16;

sys/dev/pci/if_ocereg.h

783

uint32_t dw5rsvd1:12;

sys/dev/pci/if_ocereg.h

784

uint32_t coalesce_wm:2;

sys/dev/pci/if_ocereg.h

785

uint32_t nodelay:1;

sys/dev/pci/if_ocereg.h

786

uint32_t dw5rsvd2:12;

sys/dev/pci/if_ocereg.h

787

uint32_t count:2;

sys/dev/pci/if_ocereg.h

788

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

789

uint32_t dw5rsvd3:1;

sys/dev/pci/if_ocereg.h

790

uint32_t eventable:1;

sys/dev/pci/if_ocereg.h

792

uint32_t dw6rsvd1:22;

sys/dev/pci/if_ocereg.h

793

uint32_t eq_id:8;

sys/dev/pci/if_ocereg.h

794

uint32_t dw6rsvd2:1;

sys/dev/pci/if_ocereg.h

795

uint32_t armed:1;

sys/dev/pci/if_ocereg.h

798

uint32_t dw7rsvd1;

sys/dev/pci/if_ocereg.h

800

uint32_t dw8rsvd1;

sys/dev/pci/if_ocereg.h

805

uint32_t dw4rsvd1:8;

sys/dev/pci/if_ocereg.h

806

uint32_t page_size:8;

sys/dev/pci/if_ocereg.h

807

uint32_t num_pages:16;

sys/dev/pci/if_ocereg.h

809

uint32_t eventable:1;

sys/dev/pci/if_ocereg.h

810

uint32_t dw5rsvd3:1;

sys/dev/pci/if_ocereg.h

811

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

812

uint32_t count:2;

sys/dev/pci/if_ocereg.h

813

uint32_t dw5rsvd2:11;

sys/dev/pci/if_ocereg.h

814

uint32_t autovalid:1;

sys/dev/pci/if_ocereg.h

815

uint32_t nodelay:1;

sys/dev/pci/if_ocereg.h

816

uint32_t coalesce_wm:2;

sys/dev/pci/if_ocereg.h

817

uint32_t dw5rsvd1:12;

sys/dev/pci/if_ocereg.h

819

uint32_t armed:1;

sys/dev/pci/if_ocereg.h

820

uint32_t dw6rsvd1:15;

sys/dev/pci/if_ocereg.h

821

uint32_t eq_id:16;

sys/dev/pci/if_ocereg.h

823

uint32_t dw7rsvd1:16;

sys/dev/pci/if_ocereg.h

824

uint32_t cqe_count:16;

sys/dev/pci/if_ocereg.h

827

uint32_t num_pages:16;

sys/dev/pci/if_ocereg.h

828

uint32_t page_size:8;

sys/dev/pci/if_ocereg.h

829

uint32_t dw4rsvd1:8;

sys/dev/pci/if_ocereg.h

831

uint32_t dw5rsvd1:12;

sys/dev/pci/if_ocereg.h

832

uint32_t coalesce_wm:2;

sys/dev/pci/if_ocereg.h

833

uint32_t nodelay:1;

sys/dev/pci/if_ocereg.h

834

uint32_t autovalid:1;

sys/dev/pci/if_ocereg.h

835

uint32_t dw5rsvd2:11;

sys/dev/pci/if_ocereg.h

836

uint32_t count:2;

sys/dev/pci/if_ocereg.h

837

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

838

uint32_t dw5rsvd3:1;

sys/dev/pci/if_ocereg.h

839

uint32_t eventable:1;

sys/dev/pci/if_ocereg.h

841

uint32_t eq_id:8;

sys/dev/pci/if_ocereg.h

842

uint32_t dw6rsvd1:15;

sys/dev/pci/if_ocereg.h

843

uint32_t armed:1;

sys/dev/pci/if_ocereg.h

845

uint32_t cqe_count:16;

sys/dev/pci/if_ocereg.h

846

uint32_t dw7rsvd1:16;

sys/dev/pci/if_ocereg.h

849

uint32_t dw8rsvd1;

sys/dev/pci/if_ocereg.h

884

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

890

uint32_t dw[5];

sys/dev/pci/if_ocereg.h

894

uint32_t dw4rsvd1:16;

sys/dev/pci/if_ocereg.h

895

uint32_t num_pages:16;

sys/dev/pci/if_ocereg.h

897

uint32_t cq_id:10;

sys/dev/pci/if_ocereg.h

898

uint32_t dw5rsvd2:2;

sys/dev/pci/if_ocereg.h

899

uint32_t ring_size:4;

sys/dev/pci/if_ocereg.h

900

uint32_t dw5rsvd1:16;

sys/dev/pci/if_ocereg.h

902

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

903

uint32_t dw6rsvd1:31;

sys/dev/pci/if_ocereg.h

905

uint32_t dw7rsvd1:21;

sys/dev/pci/if_ocereg.h

906

uint32_t async_cq_id:10;

sys/dev/pci/if_ocereg.h

907

uint32_t async_cq_valid:1;

sys/dev/pci/if_ocereg.h

910

uint32_t num_pages:16;

sys/dev/pci/if_ocereg.h

911

uint32_t dw4rsvd1:16;

sys/dev/pci/if_ocereg.h

913

uint32_t dw5rsvd1:16;

sys/dev/pci/if_ocereg.h

914

uint32_t ring_size:4;

sys/dev/pci/if_ocereg.h

915

uint32_t dw5rsvd2:2;

sys/dev/pci/if_ocereg.h

916

uint32_t cq_id:10;

sys/dev/pci/if_ocereg.h

918

uint32_t dw6rsvd1:31;

sys/dev/pci/if_ocereg.h

919

uint32_t valid:1;

sys/dev/pci/if_ocereg.h

921

uint32_t async_cq_valid:1;

sys/dev/pci/if_ocereg.h

922

uint32_t async_cq_id:10;

sys/dev/pci/if_ocereg.h

923

uint32_t dw7rsvd1:21;

sys/dev/pci/if_ocereg.h

926

uint32_t dw8rsvd1;

sys/dev/pci/if_ocereg.h

944

uint32_t mq_id:16;

sys/dev/pci/if_ocereg.h

945

uint32_t rsvd0:16;

sys/dev/pci/if_ocereg.h

959

uint32_t mq_id:16;

sys/dev/pci/if_ocereg.h

960

uint32_t rsvd0:16;

sys/dev/pci/if_ocereg.h

980

uint32_t rsvd0;

sys/dev/pci/if_ocereg.h

990

uint32_t rsvd0;

sys/dev/pci/if_pcn.c

1052

uint32_t csr0;

sys/dev/pci/if_pcn.c

1144

uint32_t tmd1, tmd2, tmd;

sys/dev/pci/if_pcn.c

1250

uint32_t rmd1;

sys/dev/pci/if_pcn.c

1439

uint32_t reg;

sys/dev/pci/if_pcn.c

1761

uint32_t crc;

sys/dev/pci/if_pcn.c

1861

uint32_t reg;

sys/dev/pci/if_pcn.c

1975

uint32_t rv;

sys/dev/pci/if_pcn.c

321

uint32_t sc_csr5; /* prototype CSR5 register */

sys/dev/pci/if_pcn.c

322

uint32_t sc_mode; /* prototype MODE register */

sys/dev/pci/if_pcn.c

487

static __inline uint32_t

sys/dev/pci/if_pcn.c

496

pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val)

sys/dev/pci/if_pcn.c

503

static __inline uint32_t

sys/dev/pci/if_pcn.c

512

pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val)

sys/dev/pci/if_pcn.c

570

uint32_t chipid, reg;

sys/dev/pci/if_pcn.c

622

uint32_t val;

sys/dev/pci/if_qwx_pci.c

1241

uint32_t id, uint32_t direction, uint32_t event_ring_index,

sys/dev/pci/if_qwx_pci.c

1394

uint32_t type, uint32_t irq, uint32_t intmod, size_t num_elements)

sys/dev/pci/if_qwx_pci.c

1464

uint32_t

sys/dev/pci/if_qwx_pci.c

1465

qwx_pci_read(struct qwx_softc *sc, uint32_t addr)

sys/dev/pci/if_qwx_pci.c

1473

qwx_pci_write(struct qwx_softc *sc, uint32_t addr, uint32_t val)

sys/dev/pci/if_qwx_pci.c

1481

qwx_pci_read_hw_version(struct qwx_softc *sc, uint32_t *major,

sys/dev/pci/if_qwx_pci.c

1482

uint32_t *minor)

sys/dev/pci/if_qwx_pci.c

1484

uint32_t soc_hw_version;

sys/dev/pci/if_qwx_pci.c

1493

uint32_t

sys/dev/pci/if_qwx_pci.c

1494

qwx_pcic_read32(struct qwx_softc *sc, uint32_t offset)

sys/dev/pci/if_qwx_pci.c

1498

uint32_t val;

sys/dev/pci/if_qwx_pci.c

1521

qwx_pcic_write32(struct qwx_softc *sc, uint32_t offset, uint32_t value)

sys/dev/pci/if_qwx_pci.c

1615

uint32_t msi_data_start = 0;

sys/dev/pci/if_qwx_pci.c

1616

uint32_t base_vector = 0;

sys/dev/pci/if_qwx_pci.c

1628

uint32_t num_irq = 0;

sys/dev/pci/if_qwx_pci.c

1684

uint32_t msi_data_start;

sys/dev/pci/if_qwx_pci.c

1685

uint32_t msi_data_count, msi_data_idx;

sys/dev/pci/if_qwx_pci.c

1686

uint32_t msi_irq_start;

sys/dev/pci/if_qwx_pci.c

1816

uint32_t

sys/dev/pci/if_qwx_pci.c

1817

qwx_pci_get_window_start(struct qwx_softc *sc, uint32_t offset)

sys/dev/pci/if_qwx_pci.c

1834

qwx_pci_select_window(struct qwx_softc *sc, uint32_t offset)

sys/dev/pci/if_qwx_pci.c

1837

uint32_t window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);

sys/dev/pci/if_qwx_pci.c

1852

qwx_pci_window_write32(struct qwx_softc *sc, uint32_t offset, uint32_t value)

sys/dev/pci/if_qwx_pci.c

1854

uint32_t window_start;

sys/dev/pci/if_qwx_pci.c

1874

uint32_t

sys/dev/pci/if_qwx_pci.c

1875

qwx_pci_window_read32(struct qwx_softc *sc, uint32_t offset)

sys/dev/pci/if_qwx_pci.c

1877

uint32_t window_start, val;

sys/dev/pci/if_qwx_pci.c

1902

uint32_t umac_window;

sys/dev/pci/if_qwx_pci.c

1903

uint32_t ce_window;

sys/dev/pci/if_qwx_pci.c

1904

uint32_t window;

sys/dev/pci/if_qwx_pci.c

1917

uint32_t val, msecs;

sys/dev/pci/if_qwx_pci.c

1945

uint32_t val;

sys/dev/pci/if_qwx_pci.c

1974

qwx_pci_set_link_reg(struct qwx_softc *sc, uint32_t offset, uint32_t value,

sys/dev/pci/if_qwx_pci.c

1975

uint32_t mask)

sys/dev/pci/if_qwx_pci.c

1977

uint32_t v;

sys/dev/pci/if_qwx_pci.c

2047

uint32_t val;

sys/dev/pci/if_qwx_pci.c

2087

uint32_t val;

sys/dev/pci/if_qwx_pci.c

2124

uint32_t val;

sys/dev/pci/if_qwx_pci.c

228

uint32_t intmod;

sys/dev/pci/if_qwx_pci.c

229

uint32_t ertype;

sys/dev/pci/if_qwx_pci.c

230

uint32_t msivec;

sys/dev/pci/if_qwx_pci.c

240

uint32_t chcfg;

sys/dev/pci/if_qwx_pci.c

241

uint32_t chtype;

sys/dev/pci/if_qwx_pci.c

242

uint32_t erindex;

sys/dev/pci/if_qwx_pci.c

2457

uint32_t chcfg;

sys/dev/pci/if_qwx_pci.c

2494

uint32_t intmod;

sys/dev/pci/if_qwx_pci.c

252

uint32_t reserved0;

sys/dev/pci/if_qwx_pci.c

253

uint32_t reserved1;

sys/dev/pci/if_qwx_pci.c

254

uint32_t reserved2;

sys/dev/pci/if_qwx_pci.c

2607

qwx_mhi_send_cmd(struct qwx_pci_softc *psc, uint32_t cmd, uint32_t chan)

sys/dev/pci/if_qwx_pci.c

264

uint32_t dword[2];

sys/dev/pci/if_qwx_pci.c

2750

uint32_t chcfg;

sys/dev/pci/if_qwx_pci.c

278

uint32_t mhi_chan_id;

sys/dev/pci/if_qwx_pci.c

279

uint32_t mhi_chan_state;

sys/dev/pci/if_qwx_pci.c

280

uint32_t mhi_chan_direction;

sys/dev/pci/if_qwx_pci.c

281

uint32_t mhi_chan_event_ring_index;

sys/dev/pci/if_qwx_pci.c

282

uint32_t db_addr;

sys/dev/pci/if_qwx_pci.c

283

uint32_t cmd_status;

sys/dev/pci/if_qwx_pci.c

2853

uint32_t off;

sys/dev/pci/if_qwx_pci.c

2854

uint32_t ee, state;

sys/dev/pci/if_qwx_pci.c

2950

uint32_t reg;

sys/dev/pci/if_qwx_pci.c

298

uint32_t mhi_er_type;

sys/dev/pci/if_qwx_pci.c

299

uint32_t mhi_er_irq;

sys/dev/pci/if_qwx_pci.c

300

uint32_t mhi_er_irq_moderation_ms;

sys/dev/pci/if_qwx_pci.c

301

uint32_t db_addr;

sys/dev/pci/if_qwx_pci.c

3082

const uint32_t msecs = 24, retries = 2;

sys/dev/pci/if_qwx_pci.c

3083

uint32_t reg;

sys/dev/pci/if_qwx_pci.c

3107

uint32_t reg;

sys/dev/pci/if_qwx_pci.c

3109

const uint32_t msecs = 2000, retries = 4;

sys/dev/pci/if_qwx_pci.c

3191

qwx_mhi_set_state(struct qwx_softc *sc, uint32_t state)

sys/dev/pci/if_qwx_pci.c

3193

uint32_t reg;

sys/dev/pci/if_qwx_pci.c

3211

uint32_t reg;

sys/dev/pci/if_qwx_pci.c

3265

uint32_t seq, reg, status = MHI_BHI_STATUS_RESET;

sys/dev/pci/if_qwx_pci.c

3321

uint32_t seq, reg, state = MHI_BHIE_TXVECSTATUS_STATUS_RESET;

sys/dev/pci/if_qwx_pci.c

3421

uint32_t seq, reg;

sys/dev/pci/if_qwx_pci.c

346

uint32_t sc_flags;

sys/dev/pci/if_qwx_pci.c

349

uint32_t register_window;

sys/dev/pci/if_qwx_pci.c

3496

uint32_t reg, state = MHI_BHIE_RXVECSTATUS_STATUS_RESET;

sys/dev/pci/if_qwx_pci.c

3499

const uint32_t msecs = 100, retries = 20;

sys/dev/pci/if_qwx_pci.c

352

uint32_t bhi_off;

sys/dev/pci/if_qwx_pci.c

353

uint32_t bhi_ee;

sys/dev/pci/if_qwx_pci.c

354

uint32_t bhie_off;

sys/dev/pci/if_qwx_pci.c

355

uint32_t mhi_state;

sys/dev/pci/if_qwx_pci.c

356

uint32_t max_chan;

sys/dev/pci/if_qwx_pci.c

3607

uint32_t old_ee = psc->bhi_ee;

sys/dev/pci/if_qwx_pci.c

3608

uint32_t old_mhi_state = psc->mhi_state;

sys/dev/pci/if_qwx_pci.c

3688

qwx_pci_intr_ctrl_event_mhi(struct qwx_pci_softc *psc, uint32_t mhi_state)

sys/dev/pci/if_qwx_pci.c

3698

qwx_pci_intr_ctrl_event_ee(struct qwx_pci_softc *psc, uint32_t ee)

sys/dev/pci/if_qwx_pci.c

3709

uint64_t ptr, uint32_t cmd_status)

sys/dev/pci/if_qwx_pci.c

3715

uint32_t tre1, chid;

sys/dev/pci/if_qwx_pci.c

3753

uint32_t tre0, tre1, type, code, chid, len;

sys/dev/pci/if_qwx_pci.c

3843

uint32_t tre0, tre1, code, chid, evlen, len;

sys/dev/pci/if_qwx_pci.c

392

uint32_t, uint32_t, uint32_t, size_t);

sys/dev/pci/if_qwx_pci.c

397

struct qwx_pci_event_ring *, uint32_t, uint32_t, uint32_t, size_t);

sys/dev/pci/if_qwx_pci.c

3976

uint32_t tre0, tre1, type, code, chid, len;

sys/dev/pci/if_qwx_pci.c

401

uint32_t qwx_pci_read(struct qwx_softc *, uint32_t);

sys/dev/pci/if_qwx_pci.c

402

void qwx_pci_write(struct qwx_softc *, uint32_t, uint32_t);

sys/dev/pci/if_qwx_pci.c

404

void qwx_pci_read_hw_version(struct qwx_softc *, uint32_t *, uint32_t *);

sys/dev/pci/if_qwx_pci.c

405

uint32_t qwx_pcic_read32(struct qwx_softc *, uint32_t);

sys/dev/pci/if_qwx_pci.c

406

void qwx_pcic_write32(struct qwx_softc *, uint32_t, uint32_t);

sys/dev/pci/if_qwx_pci.c

4077

uint32_t ee, state;

sys/dev/pci/if_qwx_pci.c

421

void qwx_pci_window_write32(struct qwx_softc *, uint32_t, uint32_t);

sys/dev/pci/if_qwx_pci.c

422

uint32_t qwx_pci_window_read32(struct qwx_softc *, uint32_t);

sys/dev/pci/if_qwx_pci.c

434

int qwx_mhi_send_cmd(struct qwx_pci_softc *psc, uint32_t, uint32_t);

sys/dev/pci/if_qwx_pci.c

452

void qwx_mhi_set_state(struct qwx_softc *, uint32_t);

sys/dev/pci/if_qwx_pci.c

461

void qwx_pci_intr_ctrl_event_mhi(struct qwx_pci_softc *, uint32_t);

sys/dev/pci/if_qwx_pci.c

462

void qwx_pci_intr_ctrl_event_ee(struct qwx_pci_softc *, uint32_t);

sys/dev/pci/if_qwx_pci.c

464

uint64_t, uint32_t);

sys/dev/pci/if_qwx_pci.c

479

void (*window_write32)(struct qwx_softc *, uint32_t, uint32_t);

sys/dev/pci/if_qwx_pci.c

480

uint32_t (*window_read32)(struct qwx_softc *, uint32_t);

sys/dev/pci/if_qwx_pci.c

726

int *num_vectors, uint32_t *user_base_data, uint32_t *base_vector)

sys/dev/pci/if_qwx_pci.c

758

uint32_t soc_hw_version_major, soc_hw_version_minor, sub_version;

sys/dev/pci/if_qwz_pci.c

1105

uint32_t id, uint32_t direction, uint32_t event_ring_index,

sys/dev/pci/if_qwz_pci.c

1234

uint32_t type, uint32_t irq, uint32_t intmod, size_t num_elements)

sys/dev/pci/if_qwz_pci.c

1304

uint32_t

sys/dev/pci/if_qwz_pci.c

1305

qwz_pci_read(struct qwz_softc *sc, uint32_t addr)

sys/dev/pci/if_qwz_pci.c

1313

qwz_pci_write(struct qwz_softc *sc, uint32_t addr, uint32_t val)

sys/dev/pci/if_qwz_pci.c

1321

qwz_pci_read_hw_version(struct qwz_softc *sc, uint32_t *major,

sys/dev/pci/if_qwz_pci.c

1322

uint32_t *minor)

sys/dev/pci/if_qwz_pci.c

1324

uint32_t soc_hw_version;

sys/dev/pci/if_qwz_pci.c

1333

uint32_t

sys/dev/pci/if_qwz_pci.c

1334

qwz_pcic_read32(struct qwz_softc *sc, uint32_t offset)

sys/dev/pci/if_qwz_pci.c

1338

uint32_t val;

sys/dev/pci/if_qwz_pci.c

1361

qwz_pcic_write32(struct qwz_softc *sc, uint32_t offset, uint32_t value)

sys/dev/pci/if_qwz_pci.c

1455

uint32_t msi_data_start = 0;

sys/dev/pci/if_qwz_pci.c

1456

uint32_t base_idx, base_vector = 0;

sys/dev/pci/if_qwz_pci.c

1470

uint32_t num_irq = 0;

sys/dev/pci/if_qwz_pci.c

1525

uint32_t msi_data_start;

sys/dev/pci/if_qwz_pci.c

1526

uint32_t msi_data_count, msi_data_idx;

sys/dev/pci/if_qwz_pci.c

1527

uint32_t msi_irq_start;

sys/dev/pci/if_qwz_pci.c

1657

uint32_t

sys/dev/pci/if_qwz_pci.c

1658

qwz_pci_get_window_start(struct qwz_softc *sc, uint32_t offset)

sys/dev/pci/if_qwz_pci.c

1675

qwz_pci_select_window(struct qwz_softc *sc, uint32_t offset)

sys/dev/pci/if_qwz_pci.c

1678

uint32_t window = FIELD_GET(ATH12K_PCI_WINDOW_VALUE_MASK, offset);

sys/dev/pci/if_qwz_pci.c

1699

qwz_pci_is_offset_within_mhi_region(uint32_t offset)

sys/dev/pci/if_qwz_pci.c

1705

qwz_pci_window_write32(struct qwz_softc *sc, uint32_t offset, uint32_t value)

sys/dev/pci/if_qwz_pci.c

1707

uint32_t window_start;

sys/dev/pci/if_qwz_pci.c

1734

uint32_t

sys/dev/pci/if_qwz_pci.c

1735

qwz_pci_window_read32(struct qwz_softc *sc, uint32_t offset)

sys/dev/pci/if_qwz_pci.c

1737

uint32_t window_start, val;

sys/dev/pci/if_qwz_pci.c

1769

uint32_t umac_window;

sys/dev/pci/if_qwz_pci.c

1770

uint32_t ce_window;

sys/dev/pci/if_qwz_pci.c

1771

uint32_t window;

sys/dev/pci/if_qwz_pci.c

1784

uint32_t val, msecs;

sys/dev/pci/if_qwz_pci.c

1812

uint32_t val;

sys/dev/pci/if_qwz_pci.c

1841

qwz_pci_set_link_reg(struct qwz_softc *sc, uint32_t offset, uint32_t value,

sys/dev/pci/if_qwz_pci.c

1842

uint32_t mask)

sys/dev/pci/if_qwz_pci.c

1844

uint32_t v;

sys/dev/pci/if_qwz_pci.c

1914

uint32_t val;

sys/dev/pci/if_qwz_pci.c

1954

uint32_t val;

sys/dev/pci/if_qwz_pci.c

1991

uint32_t val;

sys/dev/pci/if_qwz_pci.c

229

uint32_t intmod;

sys/dev/pci/if_qwz_pci.c

230

uint32_t ertype;

sys/dev/pci/if_qwz_pci.c

231

uint32_t msivec;

sys/dev/pci/if_qwz_pci.c

2324

uint32_t chcfg;

sys/dev/pci/if_qwz_pci.c

2361

uint32_t intmod;

sys/dev/pci/if_qwz_pci.c

241

uint32_t chcfg;

sys/dev/pci/if_qwz_pci.c

242

uint32_t chtype;

sys/dev/pci/if_qwz_pci.c

243

uint32_t erindex;

sys/dev/pci/if_qwz_pci.c

2474

qwz_mhi_send_cmd(struct qwz_pci_softc *psc, uint32_t cmd, uint32_t chan)

sys/dev/pci/if_qwz_pci.c

253

uint32_t reserved0;

sys/dev/pci/if_qwz_pci.c

254

uint32_t reserved1;

sys/dev/pci/if_qwz_pci.c

255

uint32_t reserved2;

sys/dev/pci/if_qwz_pci.c

2617

uint32_t chcfg;

sys/dev/pci/if_qwz_pci.c

265

uint32_t dword[2];

sys/dev/pci/if_qwz_pci.c

2720

uint32_t off;

sys/dev/pci/if_qwz_pci.c

2721

uint32_t ee, state;

sys/dev/pci/if_qwz_pci.c

279

uint32_t mhi_chan_id;

sys/dev/pci/if_qwz_pci.c

280

uint32_t mhi_chan_state;

sys/dev/pci/if_qwz_pci.c

281

uint32_t mhi_chan_direction;

sys/dev/pci/if_qwz_pci.c

2817

uint32_t reg;

sys/dev/pci/if_qwz_pci.c

282

uint32_t mhi_chan_event_ring_index;

sys/dev/pci/if_qwz_pci.c

283

uint32_t db_addr;

sys/dev/pci/if_qwz_pci.c

284

uint32_t cmd_status;

sys/dev/pci/if_qwz_pci.c

2949

const uint32_t msecs = 24, retries = 2;

sys/dev/pci/if_qwz_pci.c

2950

uint32_t reg;

sys/dev/pci/if_qwz_pci.c

2974

uint32_t reg;

sys/dev/pci/if_qwz_pci.c

2976

const uint32_t msecs = 2000, retries = 4;

sys/dev/pci/if_qwz_pci.c

299

uint32_t mhi_er_type;

sys/dev/pci/if_qwz_pci.c

300

uint32_t mhi_er_irq;

sys/dev/pci/if_qwz_pci.c

301

uint32_t mhi_er_irq_moderation_ms;

sys/dev/pci/if_qwz_pci.c

302

uint32_t db_addr;

sys/dev/pci/if_qwz_pci.c

3058

qwz_mhi_set_state(struct qwz_softc *sc, uint32_t state)

sys/dev/pci/if_qwz_pci.c

3060

uint32_t reg;

sys/dev/pci/if_qwz_pci.c

3078

uint32_t reg;

sys/dev/pci/if_qwz_pci.c

3132

uint32_t seq, reg, status = MHI_BHI_STATUS_RESET;

sys/dev/pci/if_qwz_pci.c

3188

uint32_t seq, reg, state = MHI_BHIE_TXVECSTATUS_STATUS_RESET;

sys/dev/pci/if_qwz_pci.c

3288

uint32_t seq, reg;

sys/dev/pci/if_qwz_pci.c

3360

uint32_t reg, state = MHI_BHIE_RXVECSTATUS_STATUS_RESET;

sys/dev/pci/if_qwz_pci.c

3363

const uint32_t msecs = 100, retries = 20;

sys/dev/pci/if_qwz_pci.c

347

uint32_t sc_flags;

sys/dev/pci/if_qwz_pci.c

3471

uint32_t old_ee = psc->bhi_ee;

sys/dev/pci/if_qwz_pci.c

3472

uint32_t old_mhi_state = psc->mhi_state;

sys/dev/pci/if_qwz_pci.c

350

uint32_t register_window;

sys/dev/pci/if_qwz_pci.c

353

uint32_t bhi_off;

sys/dev/pci/if_qwz_pci.c

354

uint32_t bhi_ee;

sys/dev/pci/if_qwz_pci.c

355

uint32_t bhie_off;

sys/dev/pci/if_qwz_pci.c

3552

qwz_pci_intr_ctrl_event_mhi(struct qwz_pci_softc *psc, uint32_t mhi_state)

sys/dev/pci/if_qwz_pci.c

356

uint32_t mhi_state;

sys/dev/pci/if_qwz_pci.c

3562

qwz_pci_intr_ctrl_event_ee(struct qwz_pci_softc *psc, uint32_t ee)

sys/dev/pci/if_qwz_pci.c

357

uint32_t max_chan;

sys/dev/pci/if_qwz_pci.c

3573

uint64_t ptr, uint32_t cmd_status)

sys/dev/pci/if_qwz_pci.c

3579

uint32_t tre1, chid;

sys/dev/pci/if_qwz_pci.c

3617

uint32_t tre0, tre1, type, code, chid, len;

sys/dev/pci/if_qwz_pci.c

3707

uint32_t tre0, tre1, code, chid, evlen, len;

sys/dev/pci/if_qwz_pci.c

3840

uint32_t tre0, tre1, type, code, chid, len;

sys/dev/pci/if_qwz_pci.c

393

uint32_t, uint32_t, uint32_t, size_t);

sys/dev/pci/if_qwz_pci.c

3941

uint32_t ee, state;

sys/dev/pci/if_qwz_pci.c

397

struct qwz_pci_event_ring *, uint32_t, uint32_t, uint32_t, size_t);

sys/dev/pci/if_qwz_pci.c

401

uint32_t qwz_pci_read(struct qwz_softc *, uint32_t);

sys/dev/pci/if_qwz_pci.c

402

void qwz_pci_write(struct qwz_softc *, uint32_t, uint32_t);

sys/dev/pci/if_qwz_pci.c

404

void qwz_pci_read_hw_version(struct qwz_softc *, uint32_t *, uint32_t *);

sys/dev/pci/if_qwz_pci.c

405

uint32_t qwz_pcic_read32(struct qwz_softc *, uint32_t);

sys/dev/pci/if_qwz_pci.c

406

void qwz_pcic_write32(struct qwz_softc *, uint32_t, uint32_t);

sys/dev/pci/if_qwz_pci.c

421

void qwz_pci_window_write32(struct qwz_softc *, uint32_t, uint32_t);

sys/dev/pci/if_qwz_pci.c

422

uint32_t qwz_pci_window_read32(struct qwz_softc *, uint32_t);

sys/dev/pci/if_qwz_pci.c

434

int qwz_mhi_send_cmd(struct qwz_pci_softc *psc, uint32_t, uint32_t);

sys/dev/pci/if_qwz_pci.c

452

void qwz_mhi_set_state(struct qwz_softc *, uint32_t);

sys/dev/pci/if_qwz_pci.c

461

void qwz_pci_intr_ctrl_event_mhi(struct qwz_pci_softc *, uint32_t);

sys/dev/pci/if_qwz_pci.c

462

void qwz_pci_intr_ctrl_event_ee(struct qwz_pci_softc *, uint32_t);

sys/dev/pci/if_qwz_pci.c

464

uint64_t, uint32_t);

sys/dev/pci/if_qwz_pci.c

479

void (*window_write32)(struct qwz_softc *, uint32_t, uint32_t);

sys/dev/pci/if_qwz_pci.c

480

uint32_t (*window_read32)(struct qwz_softc *, uint32_t);

sys/dev/pci/if_qwz_pci.c

651

int *num_vectors, uint32_t *user_base_data, uint32_t *base_vector)

sys/dev/pci/if_qwz_pci.c

683

uint32_t soc_hw_version_major, soc_hw_version_minor;

sys/dev/pci/if_rge.c

118

void rge_write_csi(struct rge_softc *, uint32_t, uint32_t);

sys/dev/pci/if_rge.c

119

uint32_t rge_read_csi(struct rge_softc *, uint32_t);

sys/dev/pci/if_rge.c

1221

uint32_t cmdsts;

sys/dev/pci/if_rge.c

1332

uint32_t rxstat, extsts;

sys/dev/pci/if_rge.c

1463

uint32_t txstat;

sys/dev/pci/if_rge.c

1580

uint32_t hashes[2];

sys/dev/pci/if_rge.c

1581

uint32_t rxfilt;

sys/dev/pci/if_rge.c

187

uint32_t hwrev;

sys/dev/pci/if_rge.c

3237

*(uint32_t *)&addr[0] = RGE_READ_4(sc, RGE_ADDR0);

sys/dev/pci/if_rge.c

3489

rge_write_csi(struct rge_softc *sc, uint32_t reg, uint32_t val)

sys/dev/pci/if_rge.c

3506

uint32_t

sys/dev/pci/if_rge.c

3507

rge_read_csi(struct rge_softc *sc, uint32_t reg)

sys/dev/pci/if_rge.c

3528

uint32_t tmp;

sys/dev/pci/if_rge.c

3539

uint32_t val;

sys/dev/pci/if_rge.c

3550

uint32_t tmp;

sys/dev/pci/if_rge.c

3569

uint32_t val;

sys/dev/pci/if_rge.c

3637

uint32_t tmp;

sys/dev/pci/if_rge.c

3654

uint32_t val;

sys/dev/pci/if_rge.c

372

uint32_t status;

sys/dev/pci/if_rge.c

3825

uint32_t reg;

sys/dev/pci/if_rge.c

453

uint32_t cmdsts, cflags = 0;

sys/dev/pci/if_rge.c

682

uint32_t rxconf, val;

sys/dev/pci/if_rgereg.h

213

uint32_t rge_cmdsts;

sys/dev/pci/if_rgereg.h

214

uint32_t rge_extsts;

sys/dev/pci/if_rgereg.h

216

uint32_t reserved[4];

sys/dev/pci/if_rgereg.h

236

uint32_t rsvd0;

sys/dev/pci/if_rgereg.h

237

uint32_t rsvd1;

sys/dev/pci/if_rgereg.h

243

uint32_t rss;

sys/dev/pci/if_rgereg.h

249

uint32_t rsvd2;

sys/dev/pci/if_rgereg.h

250

uint32_t rsvd3;

sys/dev/pci/if_rgereg.h

262

uint32_t rsvd4;

sys/dev/pci/if_rgereg.h

263

uint32_t rsvd5;

sys/dev/pci/if_rgereg.h

269

uint32_t rge_extsts;

sys/dev/pci/if_rgereg.h

270

uint32_t rge_cmdsts;

sys/dev/pci/if_rgereg.h

276

uint32_t rsvd8;

sys/dev/pci/if_rgereg.h

305

uint32_t rge_rx_er;

sys/dev/pci/if_rgereg.h

308

uint32_t rge_tx_1col;

sys/dev/pci/if_rgereg.h

309

uint32_t rge_tx_mcol;

sys/dev/pci/if_rgereg.h

312

uint32_t rge_rx_ok_mul;

sys/dev/pci/if_rgereg.h

429

uint32_t rge_flags;

sys/dev/pci/if_rgereg.h

432

uint32_t rge_intrs;

sys/dev/pci/if_rtwn.c

1617

rtwn_llt_write(struct rtwn_pci_softc *sc, uint32_t addr, uint32_t data)

sys/dev/pci/if_rtwn.c

1671

uint32_t reg;

sys/dev/pci/if_rtwn.c

168

uint32_t qfullmsk;

sys/dev/pci/if_rtwn.c

1802

uint32_t reg;

sys/dev/pci/if_rtwn.c

1890

uint32_t reg;

sys/dev/pci/if_rtwn.c

1992

uint32_t reg;

sys/dev/pci/if_rtwn.c

2094

uint32_t reg;

sys/dev/pci/if_rtwn.c

2180

uint32_t reg;

sys/dev/pci/if_rtwn.c

241

void rtwn_pci_write_4(void *, uint16_t, uint32_t);

sys/dev/pci/if_rtwn.c

244

uint32_t rtwn_pci_read_4(void *, uint16_t);

sys/dev/pci/if_rtwn.c

260

int rtwn_llt_write(struct rtwn_pci_softc *, uint32_t, uint32_t);

sys/dev/pci/if_rtwn.c

348

uint32_t lcsr = pci_conf_read(sc->sc_pc, sc->sc_tag,

sys/dev/pci/if_rtwn.c

774

rtwn_pci_write_4(void *cookie, uint16_t addr, uint32_t val)

sys/dev/pci/if_rtwn.c

800

uint32_t

sys/dev/pci/if_rtwn.c

804

uint32_t val;

sys/dev/pci/if_rtwn.c

820

uint32_t rxdw0, rxdw3;

sys/dev/pci/if_rtwn.c

835

uint32_t rptb1, rptb2;

sys/dev/pci/if_se.c

1048

uint32_t status;

sys/dev/pci/if_se.c

1094

se_encap(struct se_softc *sc, struct mbuf *m_head, uint32_t *txidx)

sys/dev/pci/if_se.c

1156

htole32((uint32_t)cd->se_tx_map[i]->dm_segs->ds_addr);

sys/dev/pci/if_se.c

1267

(uint32_t)sc->se_ldata.se_tx_dmamap->dm_segs[0].ds_addr);

sys/dev/pci/if_se.c

1269

(uint32_t)sc->se_ldata.se_rx_dmamap->dm_segs[0].ds_addr);

sys/dev/pci/if_se.c

148

uint32_t

sys/dev/pci/if_se.c

149

se_miibus_cmd(struct se_softc *, uint32_t);

sys/dev/pci/if_se.c

206

uint32_t val;

sys/dev/pci/if_se.c

315

uint32_t

sys/dev/pci/if_se.c

316

se_miibus_cmd(struct se_softc *sc, uint32_t ctrl)

sys/dev/pci/if_se.c

319

uint32_t val;

sys/dev/pci/if_se.c

337

uint32_t ctrl, val;

sys/dev/pci/if_se.c

354

uint32_t ctrl, val;

sys/dev/pci/if_se.c

373

uint32_t ctl, speed;

sys/dev/pci/if_se.c

445

uint32_t crc, hashes[2];

sys/dev/pci/if_se.c

866

desc->se_ptr = htole32((uint32_t)cd->se_rx_map[i]->dm_segs[0].ds_addr);

sys/dev/pci/if_se.c

905

uint32_t rxinfo, rxstat;

sys/dev/pci/if_se.c

972

uint32_t txstat;

sys/dev/pci/if_sis.c

328

uint32_t rxfilt, csrsave;

sys/dev/pci/if_sis.c

724

uint32_t reg;

sys/dev/pci/if_sis.c

749

uint32_t crc;

sys/dev/pci/if_stge.c

1049

uint32_t ac;

sys/dev/pci/if_stge.c

113

uint32_t stge_mii_bitbang_read(struct device *);

sys/dev/pci/if_stge.c

114

void stge_mii_bitbang_write(struct device *, uint32_t);

sys/dev/pci/if_stge.c

1471

uint32_t crc;

sys/dev/pci/if_stge.c

1472

uint32_t mchash[2];

sys/dev/pci/if_stge.c

1574

uint32_t

sys/dev/pci/if_stge.c

1588

stge_mii_bitbang_write(struct device *self, uint32_t val)

sys/dev/pci/if_stge.c

710

uint32_t txstat;

sys/dev/pci/if_stgereg.h

567

uint32_t sc_usefiber:1; /* if we're fiber */

sys/dev/pci/if_stgereg.h

568

uint32_t sc_stge1023:1; /* are we a 1023 */

sys/dev/pci/if_stgereg.h

569

uint32_t sc_DMACtrl; /* prototype DMACtrl register */

sys/dev/pci/if_stgereg.h

570

uint32_t sc_MACCtrl; /* prototype MacCtrl register */

sys/dev/pci/if_vgereg.h

589

uint32_t vge_addrlo;

sys/dev/pci/if_vgereg.h

606

uint32_t vge_sts;

sys/dev/pci/if_vgereg.h

607

uint32_t vge_ctl;

sys/dev/pci/if_vgereg.h

648

volatile uint32_t vge_sts;

sys/dev/pci/if_vgereg.h

649

volatile uint32_t vge_ctl;

sys/dev/pci/if_vgereg.h

650

volatile uint32_t vge_addrlo;

sys/dev/pci/if_vmx.c

1055

uint32_t rgen;

sys/dev/pci/if_vmx.c

1289

uint32_t pkts;

sys/dev/pci/if_vmx.c

1333

uint32_t paylen;

sys/dev/pci/if_vmx.c

1563

uint32_t offset = 0;

sys/dev/pci/if_vmx.c

1564

uint32_t hdrlen;

sys/dev/pci/if_vmx.c

1647

uint32_t rgen, gen;

sys/dev/pci/if_vmx.c

738

uint32_t rgen;

sys/dev/pci/if_vmx.c

739

uint32_t type = htole32(VMXNET3_BTYPE_HEAD << VMXNET3_RX_BTYPE_S);

sys/dev/pci/if_vte.c

1006

htole16(MCLBYTES - sizeof(uint32_t));

sys/dev/pci/if_vte.c

1013

htole16(MCLBYTES - sizeof(uint32_t));

sys/dev/pci/if_vte.c

1428

uint32_t crc;

sys/dev/pci/if_vte.c

944

m_adj(m, sizeof(uint32_t));

sys/dev/pci/if_vtereg.h

294

uint32_t drbp;

sys/dev/pci/if_vtereg.h

295

uint32_t drnp;

sys/dev/pci/if_vtereg.h

327

uint32_t dtbp;

sys/dev/pci/if_vtereg.h

328

uint32_t dtnp;

sys/dev/pci/if_vtereg.h

329

uint32_t __pad; /* Not actual descriptor member. */

sys/dev/pci/if_vtereg.h

361

#define VTE_RX_BUF_SIZE_MAX (MCLBYTES - sizeof(uint32_t))

sys/dev/pci/if_vtereg.h

407

uint32_t rx_frames;

sys/dev/pci/if_vtereg.h

408

uint32_t rx_bcast_frames;

sys/dev/pci/if_vtereg.h

409

uint32_t rx_mcast_frames;

sys/dev/pci/if_vtereg.h

410

uint32_t rx_runts;

sys/dev/pci/if_vtereg.h

411

uint32_t rx_crcerrs;

sys/dev/pci/if_vtereg.h

412

uint32_t rx_long_frames;

sys/dev/pci/if_vtereg.h

413

uint32_t rx_fifo_full;

sys/dev/pci/if_vtereg.h

414

uint32_t rx_desc_unavail;

sys/dev/pci/if_vtereg.h

415

uint32_t rx_pause_frames;

sys/dev/pci/if_vtereg.h

418

uint32_t tx_frames;

sys/dev/pci/if_vtereg.h

419

uint32_t tx_underruns;

sys/dev/pci/if_vtereg.h

420

uint32_t tx_late_colls;

sys/dev/pci/if_vtereg.h

421

uint32_t tx_pause_frames;

sys/dev/pci/if_wpi.c

1185

uint32_t flags;

sys/dev/pci/if_wpi.c

1240

ring->cur * sizeof (uint32_t), sizeof (uint32_t),

sys/dev/pci/if_wpi.c

1251

ring->cur * sizeof (uint32_t), sizeof (uint32_t),

sys/dev/pci/if_wpi.c

1404

uint32_t hw;

sys/dev/pci/if_wpi.c

1460

uint32_t *status = (uint32_t *)(desc + 1);

sys/dev/pci/if_wpi.c

1535

uint32_t i, offset, count;

sys/dev/pci/if_wpi.c

1560

offset = sc->errptr + sizeof (uint32_t);

sys/dev/pci/if_wpi.c

1563

wpi_mem_read_region_4(sc, offset, (uint32_t *)&dump,

sys/dev/pci/if_wpi.c

1564

sizeof (dump) / sizeof (uint32_t));

sys/dev/pci/if_wpi.c

1599

uint32_t r1, r2;

sys/dev/pci/if_wpi.c

1657

uint32_t flags;

sys/dev/pci/if_wpi.c

2188

cmd.binitval = htole32((uint32_t)(val - mod));

sys/dev/pci/if_wpi.c

2191

ni->ni_intval, letoh64(cmd.tstamp), (uint32_t)(val - mod)));

sys/dev/pci/if_wpi.c

2354

uint32_t max, skip_dtim;

sys/dev/pci/if_wpi.c

2383

if (max == (uint32_t)-1)

sys/dev/pci/if_wpi.c

2827

size /= sizeof (uint32_t);

sys/dev/pci/if_wpi.c

2834

(const uint32_t *)ucode, size);

sys/dev/pci/if_wpi.c

3196

uint32_t tmp;

sys/dev/pci/if_wpi.c

458

static __inline uint32_t

sys/dev/pci/if_wpi.c

459

wpi_prph_read(struct wpi_softc *sc, uint32_t addr)

sys/dev/pci/if_wpi.c

467

wpi_prph_write(struct wpi_softc *sc, uint32_t addr, uint32_t data)

sys/dev/pci/if_wpi.c

475

wpi_prph_setbits(struct wpi_softc *sc, uint32_t addr, uint32_t mask)

sys/dev/pci/if_wpi.c

481

wpi_prph_clrbits(struct wpi_softc *sc, uint32_t addr, uint32_t mask)

sys/dev/pci/if_wpi.c

487

wpi_prph_write_region_4(struct wpi_softc *sc, uint32_t addr,

sys/dev/pci/if_wpi.c

488

const uint32_t *data, int count)

sys/dev/pci/if_wpi.c

496

static __inline uint32_t

sys/dev/pci/if_wpi.c

497

wpi_mem_read(struct wpi_softc *sc, uint32_t addr)

sys/dev/pci/if_wpi.c

505

wpi_mem_write(struct wpi_softc *sc, uint32_t addr, uint32_t data)

sys/dev/pci/if_wpi.c

513

wpi_mem_read_region_4(struct wpi_softc *sc, uint32_t addr, uint32_t *data,

sys/dev/pci/if_wpi.c

523

wpi_read_prom_data(struct wpi_softc *sc, uint32_t addr, void *data, int count)

sys/dev/pci/if_wpi.c

526

uint32_t val;

sys/dev/pci/if_wpi.c

651

size = WPI_RX_RING_COUNT * sizeof (uint32_t);

sys/dev/pci/if_wpi.c

75

int wpi_read_prom_data(struct wpi_softc *, uint32_t, void *, int);

sys/dev/pci/if_wpireg.h

111

#define WPI_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24)

sys/dev/pci/if_wpireg.h

210

uint32_t txbase[8];

sys/dev/pci/if_wpireg.h

211

uint32_t next;

sys/dev/pci/if_wpireg.h

212

uint32_t reserved[2];

sys/dev/pci/if_wpireg.h

217

uint32_t flags;

sys/dev/pci/if_wpireg.h

221

uint32_t addr;

sys/dev/pci/if_wpireg.h

222

uint32_t len;

sys/dev/pci/if_wpireg.h

232

uint32_t duration;

sys/dev/pci/if_wpireg.h

233

uint32_t status;

sys/dev/pci/if_wpireg.h

237

uint32_t len;

sys/dev/pci/if_wpireg.h

279

uint32_t reserved3[2];

sys/dev/pci/if_wpireg.h

290

uint32_t flags;

sys/dev/pci/if_wpireg.h

301

uint32_t filter;

sys/dev/pci/if_wpireg.h

314

uint32_t flags;

sys/dev/pci/if_wpireg.h

315

uint32_t filter;

sys/dev/pci/if_wpireg.h

323

uint32_t flags;

sys/dev/pci/if_wpireg.h

341

uint32_t binitval;

sys/dev/pci/if_wpireg.h

372

uint32_t action;

sys/dev/pci/if_wpireg.h

375

uint32_t mask;

sys/dev/pci/if_wpireg.h

392

uint32_t flags;

sys/dev/pci/if_wpireg.h

412

uint32_t fnext;

sys/dev/pci/if_wpireg.h

413

uint32_t lifetime;

sys/dev/pci/if_wpireg.h

427

uint32_t which;

sys/dev/pci/if_wpireg.h

441

uint32_t unit; /* multiplier (in usecs) */

sys/dev/pci/if_wpireg.h

453

uint32_t flags;

sys/dev/pci/if_wpireg.h

458

uint32_t rxtimeout;

sys/dev/pci/if_wpireg.h

459

uint32_t txtimeout;

sys/dev/pci/if_wpireg.h

460

uint32_t intval[5];

sys/dev/pci/if_wpireg.h

478

uint32_t max_svc; /* background scans */

sys/dev/pci/if_wpireg.h

479

uint32_t pause_svc; /* background scans */

sys/dev/pci/if_wpireg.h

480

uint32_t flags;

sys/dev/pci/if_wpireg.h

481

uint32_t filter;

sys/dev/pci/if_wpireg.h

535

uint32_t kill_ack;

sys/dev/pci/if_wpireg.h

536

uint32_t kill_cts;

sys/dev/pci/if_wpireg.h

562

uint32_t flags;

sys/dev/pci/if_wpireg.h

573

uint32_t tbeacon;

sys/dev/pci/if_wpireg.h

578

uint32_t version;

sys/dev/pci/if_wpireg.h

585

uint32_t logptr;

sys/dev/pci/if_wpireg.h

586

uint32_t errptr;

sys/dev/pci/if_wpireg.h

587

uint32_t timestamp;

sys/dev/pci/if_wpireg.h

588

uint32_t valid;

sys/dev/pci/if_wpireg.h

594

uint32_t tbeacon;

sys/dev/pci/if_wpireg.h

598

uint32_t status;

sys/dev/pci/if_wpireg.h

613

uint32_t desc;

sys/dev/pci/if_wpireg.h

614

uint32_t time;

sys/dev/pci/if_wpireg.h

615

uint32_t blink[2];

sys/dev/pci/if_wpireg.h

616

uint32_t ilink[2];

sys/dev/pci/if_wpireg.h

617

uint32_t data;

sys/dev/pci/if_wpireg.h

622

uint32_t version;

sys/dev/pci/if_wpireg.h

623

uint32_t main_textsz;

sys/dev/pci/if_wpireg.h

624

uint32_t main_datasz;

sys/dev/pci/if_wpireg.h

625

uint32_t init_textsz;

sys/dev/pci/if_wpireg.h

626

uint32_t init_datasz;

sys/dev/pci/if_wpireg.h

627

uint32_t boot_textsz;

sys/dev/pci/if_wpireg.h

680

uint32_t addr; /* offset in EEPROM */

sys/dev/pci/if_wpireg.h

782

uint32_t rxtimeout;

sys/dev/pci/if_wpireg.h

783

uint32_t txtimeout;

sys/dev/pci/if_wpireg.h

784

uint32_t intval[5];

sys/dev/pci/if_wpivar.h

117

uint32_t textsz;

sys/dev/pci/if_wpivar.h

119

uint32_t datasz;

sys/dev/pci/if_wpivar.h

171

uint32_t errptr;

sys/dev/pci/if_wpivar.h

175

uint32_t qfullmsk;

sys/dev/pci/if_wpivar.h

90

uint32_t *desc;

sys/dev/pci/if_xge.c

237

uint32_t lval, hval;

sys/dev/pci/if_xge.c

278

uint32_t lval, hval;

sys/dev/pci/if_xge.c

302

uint32_t lval, hval;

sys/dev/pci/igc_api.c

219

uint32_t mc_addr_count)

sys/dev/pci/igc_api.c

303

igc_rar_set(struct igc_hw *hw, uint8_t *addr, uint32_t index)

sys/dev/pci/igc_api.h

28

int igc_rar_set(struct igc_hw *, uint8_t *, uint32_t);

sys/dev/pci/igc_api.h

29

void igc_update_mc_addr_list(struct igc_hw *, uint8_t *, uint32_t);

sys/dev/pci/igc_base.h

101

uint32_t data;

sys/dev/pci/igc_base.h

109

uint32_t rss; /* RSS hash */

sys/dev/pci/igc_base.h

117

uint32_t status_error; /* ext status/error */

sys/dev/pci/igc_base.h

25

uint32_t cmd_type_len;

sys/dev/pci/igc_base.h

26

uint32_t olinfo_status;

sys/dev/pci/igc_base.h

30

uint32_t nxtseq_seed;

sys/dev/pci/igc_base.h

31

uint32_t status;

sys/dev/pci/igc_base.h

37

uint32_t vlan_macip_lens;

sys/dev/pci/igc_base.h

39

uint32_t launch_time;

sys/dev/pci/igc_base.h

40

uint32_t seqnum_seed;

sys/dev/pci/igc_base.h

42

uint32_t type_tucmd_mlhl;

sys/dev/pci/igc_base.h

43

uint32_t mss_l4len_idx;

sys/dev/pci/igc_hw.h

155

uint32_t mrq; /* Multiple Rx queues */

sys/dev/pci/igc_hw.h

157

uint32_t rss; /* RSS hash */

sys/dev/pci/igc_hw.h

165

uint32_t status_error; /* ext status/error */

sys/dev/pci/igc_hw.h

176

uint32_t data;

sys/dev/pci/igc_hw.h

184

uint32_t data;

sys/dev/pci/igc_hw.h

202

void (*update_mc_addr_list)(struct igc_hw *, uint8_t *, uint32_t);

sys/dev/pci/igc_hw.h

207

void (*write_vfta)(struct igc_hw *, uint32_t, uint32_t);

sys/dev/pci/igc_hw.h

209

int (*rar_set)(struct igc_hw *, uint8_t *, uint32_t);

sys/dev/pci/igc_hw.h

237

int (*read_reg)(struct igc_hw *, uint32_t, uint16_t *);

sys/dev/pci/igc_hw.h

238

int (*read_reg_locked)(struct igc_hw *, uint32_t, uint16_t *);

sys/dev/pci/igc_hw.h

239

int (*read_reg_page)(struct igc_hw *, uint32_t, uint16_t *);

sys/dev/pci/igc_hw.h

244

int (*write_reg)(struct igc_hw *, uint32_t, uint16_t);

sys/dev/pci/igc_hw.h

245

int (*write_reg_locked)(struct igc_hw *, uint32_t, uint16_t);

sys/dev/pci/igc_hw.h

246

int (*write_reg_page)(struct igc_hw *, uint32_t, uint16_t);

sys/dev/pci/igc_hw.h

270

uint32_t mc_filter_type;

sys/dev/pci/igc_hw.h

282

uint32_t mta_shadow[MAX_MTA_REG];

sys/dev/pci/igc_hw.h

290

uint32_t max_frame_size;

sys/dev/pci/igc_hw.h

299

uint32_t addr;

sys/dev/pci/igc_hw.h

300

uint32_t id;

sys/dev/pci/igc_hw.h

301

uint32_t reset_delay_us; /* in usec */

sys/dev/pci/igc_hw.h

302

uint32_t revision;

sys/dev/pci/igc_hw.h

337

uint32_t high_water;

sys/dev/pci/igc_hw.h

338

uint32_t low_water;

sys/dev/pci/igc_hw.h

350

uint32_t mtu;

sys/dev/pci/igc_i225.c

1114

uint32_t ipcnfg, eeer;

sys/dev/pci/igc_i225.c

1126

uint32_t eee_su = IGC_READ_REG(hw, IGC_EEE_SU);

sys/dev/pci/igc_i225.c

181

uint32_t ctrl;

sys/dev/pci/igc_i225.c

272

uint32_t swfw_sync;

sys/dev/pci/igc_i225.c

273

uint32_t swmask = mask;

sys/dev/pci/igc_i225.c

274

uint32_t fwmask = mask << 16;

sys/dev/pci/igc_i225.c

28

uint32_t eecd = IGC_READ_REG(hw, IGC_EECD);

sys/dev/pci/igc_i225.c

323

uint32_t swfw_sync;

sys/dev/pci/igc_i225.c

348

uint32_t ctrl, phpm_reg;

sys/dev/pci/igc_i225.c

375

uint32_t swsm;

sys/dev/pci/igc_i225.c

537

uint32_t i, k, eewr = 0;

sys/dev/pci/igc_i225.c

538

uint32_t attempts = 100000;

sys/dev/pci/igc_i225.c

679

uint32_t eec = 0;

sys/dev/pci/igc_i225.c

699

igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw, uint32_t burst_counter)

sys/dev/pci/igc_i225.c

725

igc_write_erase_flash_command_i225(struct igc_hw *hw, uint32_t opcode,

sys/dev/pci/igc_i225.c

726

uint32_t address)

sys/dev/pci/igc_i225.c

728

uint32_t flswctl = 0;

sys/dev/pci/igc_i225.c

774

uint32_t block_sw_protect = 1;

sys/dev/pci/igc_i225.c

775

uint32_t i, flup, fw_valid_bit;

sys/dev/pci/igc_i225.c

867

uint32_t i, reg;

sys/dev/pci/igc_i225.c

895

uint32_t tw_system, ltrc, ltrv, ltr_min, ltr_max, scale_min, scale_max;

sys/dev/pci/igc_i225.h

22

int igc_set_flsw_flash_burst_counter_i225(struct igc_hw *, uint32_t);

sys/dev/pci/igc_i225.h

23

int igc_write_erase_flash_command_i225(struct igc_hw *, uint32_t, uint32_t);

sys/dev/pci/igc_mac.c

100

uint32_t i;

sys/dev/pci/igc_mac.c

162

igc_rar_set_generic(struct igc_hw *hw, uint8_t *addr, uint32_t index)

sys/dev/pci/igc_mac.c

164

uint32_t rar_low, rar_high;

sys/dev/pci/igc_mac.c

171

rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) |

sys/dev/pci/igc_mac.c

172

((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));

sys/dev/pci/igc_mac.c

174

rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));

sys/dev/pci/igc_mac.c

203

uint32_t hash_value, hash_mask;

sys/dev/pci/igc_mac.c

274

uint32_t mc_addr_count)

sys/dev/pci/igc_mac.c

276

uint32_t hash_value, hash_bit, hash_reg;

sys/dev/pci/igc_mac.c

285

for (i = 0; (uint32_t)i < mc_addr_count; i++) {

sys/dev/pci/igc_mac.c

420

uint32_t tctl;

sys/dev/pci/igc_mac.c

444

uint32_t fcrtl = 0, fcrth = 0;

sys/dev/pci/igc_mac.c

484

uint32_t ctrl;

sys/dev/pci/igc_mac.c

49

igc_write_vfta_generic(struct igc_hw *hw, uint32_t offset, uint32_t value)

sys/dev/pci/igc_mac.c

69

uint32_t i;

sys/dev/pci/igc_mac.c

712

uint32_t status;

sys/dev/pci/igc_mac.c

758

uint32_t swsm;

sys/dev/pci/igc_mac.c

810

uint32_t ctrl;

sys/dev/pci/igc_mac.h

21

void igc_update_mc_addr_list_generic(struct igc_hw *, uint8_t *, uint32_t);

sys/dev/pci/igc_mac.h

22

int igc_rar_set_generic(struct igc_hw *, uint8_t *, uint32_t);

sys/dev/pci/igc_mac.h

32

void igc_write_vfta_generic(struct igc_hw *, uint32_t, uint32_t);

sys/dev/pci/igc_nvm.c

106

uint32_t attempts = 100000;

sys/dev/pci/igc_nvm.c

107

uint32_t i, reg = 0;

sys/dev/pci/igc_nvm.c

140

uint32_t i, eerd = 0;

sys/dev/pci/igc_nvm.c

183

uint32_t rar_high, rar_low;

sys/dev/pci/igc_nvm.c

69

uint32_t ctrl_ext;

sys/dev/pci/igc_phy.c

100

uint32_t IGC_UNUSEDARG offset, uint16_t IGC_UNUSEDARG data)

sys/dev/pci/igc_phy.c

117

uint32_t manc;

sys/dev/pci/igc_phy.c

150

phy->id = (uint32_t)(phy_id << 16);

sys/dev/pci/igc_phy.c

156

phy->id |= (uint32_t)(phy_id & PHY_REVISION_MASK);

sys/dev/pci/igc_phy.c

157

phy->revision = (uint32_t)(phy_id & ~PHY_REVISION_MASK);

sys/dev/pci/igc_phy.c

172

igc_read_phy_reg_mdic(struct igc_hw *hw, uint32_t offset, uint16_t *data)

sys/dev/pci/igc_phy.c

175

uint32_t i, mdic = 0;

sys/dev/pci/igc_phy.c

230

igc_write_phy_reg_mdic(struct igc_hw *hw, uint32_t offset, uint16_t data)

sys/dev/pci/igc_phy.c

233

uint32_t i, mdic = 0;

sys/dev/pci/igc_phy.c

246

mdic = (((uint32_t)data) | (offset << IGC_MDIC_REG_SHIFT) |

sys/dev/pci/igc_phy.c

63

uint32_t IGC_UNUSEDARG offset, uint16_t IGC_UNUSEDARG *data)

sys/dev/pci/igc_phy.c

644

igc_phy_has_link_generic(struct igc_hw *hw, uint32_t iterations,

sys/dev/pci/igc_phy.c

645

uint32_t usec_interval, bool *success)

sys/dev/pci/igc_phy.c

700

uint32_t ctrl, timeout = 10000, phpm = 0;

sys/dev/pci/igc_phy.c

792

igc_write_phy_reg_gpy(struct igc_hw *hw, uint32_t offset, uint16_t data)

sys/dev/pci/igc_phy.c

828

igc_read_phy_reg_gpy(struct igc_hw *hw, uint32_t offset, uint16_t *data)

sys/dev/pci/igc_phy.h

14

int igc_null_read_reg(struct igc_hw *, uint32_t, uint16_t *);

sys/dev/pci/igc_phy.h

17

int igc_null_write_reg(struct igc_hw *, uint32_t, uint16_t);

sys/dev/pci/igc_phy.h

24

int igc_phy_has_link_generic(struct igc_hw *, uint32_t, uint32_t, bool *);

sys/dev/pci/igc_phy.h

27

int igc_read_phy_reg_mdic(struct igc_hw *, uint32_t offset, uint16_t *);

sys/dev/pci/igc_phy.h

28

int igc_write_phy_reg_mdic(struct igc_hw *, uint32_t offset, uint16_t);

sys/dev/pci/igc_phy.h

31

int igc_write_phy_reg_gpy(struct igc_hw *, uint32_t, uint16_t);

sys/dev/pci/igc_phy.h

32

int igc_read_phy_reg_gpy(struct igc_hw *, uint32_t, uint16_t *);

sys/dev/pci/iosf_pci.c

127

static uint32_t

sys/dev/pci/iosf_pci.c

128

iosf_pci_mbi_mdr_rd(struct iosf_mbi *mbi, uint32_t mcr, uint32_t mcrx)

sys/dev/pci/iosf_pci.c

142

iosf_pci_mbi_mdr_wr(struct iosf_mbi *mbi, uint32_t mcr, uint32_t mcrx,

sys/dev/pci/iosf_pci.c

143

uint32_t mdr)

sys/dev/pci/iosf_pci.c

48

static uint32_t iosf_pci_mbi_mdr_rd(struct iosf_mbi *, uint32_t, uint32_t);

sys/dev/pci/iosf_pci.c

49

static void iosf_pci_mbi_mdr_wr(struct iosf_mbi *, uint32_t, uint32_t,

sys/dev/pci/iosf_pci.c

50

uint32_t);

sys/dev/pci/ixgb_ee.c

109

uint32_t eecd_reg;

sys/dev/pci/ixgb_ee.c

110

uint32_t mask;

sys/dev/pci/ixgb_ee.c

154

uint32_t eecd_reg;

sys/dev/pci/ixgb_ee.c

155

uint32_t i;

sys/dev/pci/ixgb_ee.c

196

uint32_t eecd_reg;

sys/dev/pci/ixgb_ee.c

218

uint32_t eecd_reg;

sys/dev/pci/ixgb_ee.c

252

uint32_t eecd_reg;

sys/dev/pci/ixgb_ee.c

276

uint32_t eecd_reg;

sys/dev/pci/ixgb_ee.c

302

uint32_t eecd_reg;

sys/dev/pci/ixgb_ee.c

303

uint32_t i;

sys/dev/pci/ixgb_ee.c

72

ixgb_raise_clock(struct ixgb_hw *hw, uint32_t *eecd_reg)

sys/dev/pci/ixgb_ee.c

89

ixgb_lower_clock(struct ixgb_hw *hw, uint32_t *eecd_reg)

sys/dev/pci/ixgb_ee.h

88

uint32_t pba_number;

sys/dev/pci/ixgb_hw.c

1042

uint32_t status_reg;

sys/dev/pci/ixgb_hw.c

1189

uint32_t ctrl = IXGB_READ_REG(hw, CTRL0);

sys/dev/pci/ixgb_hw.c

130

uint32_t ctrl_reg;

sys/dev/pci/ixgb_hw.c

131

uint32_t icr_reg;

sys/dev/pci/ixgb_hw.c

187

uint32_t i;

sys/dev/pci/ixgb_hw.c

303

uint32_t i;

sys/dev/pci/ixgb_hw.c

304

uint32_t ctrl_reg;

sys/dev/pci/ixgb_hw.c

387

uint32_t i;

sys/dev/pci/ixgb_hw.c

444

uint32_t mc_addr_count, uint32_t pad)

sys/dev/pci/ixgb_hw.c

446

uint32_t hash_value;

sys/dev/pci/ixgb_hw.c

447

uint32_t i;

sys/dev/pci/ixgb_hw.c

448

uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */

sys/dev/pci/ixgb_hw.c

516

static uint32_t

sys/dev/pci/ixgb_hw.c

519

uint32_t hash_value = 0;

sys/dev/pci/ixgb_hw.c

565

ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value)

sys/dev/pci/ixgb_hw.c

567

uint32_t hash_bit, hash_reg;

sys/dev/pci/ixgb_hw.c

568

uint32_t mta_reg;

sys/dev/pci/ixgb_hw.c

593

ixgb_rar_set(struct ixgb_hw *hw, uint8_t *addr, uint32_t index)

sys/dev/pci/ixgb_hw.c

595

uint32_t rar_low, rar_high;

sys/dev/pci/ixgb_hw.c

60

static uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t *mc_addr);

sys/dev/pci/ixgb_hw.c

601

rar_low = ((uint32_t)addr[0] |

sys/dev/pci/ixgb_hw.c

602

((uint32_t)addr[1] << 8) |

sys/dev/pci/ixgb_hw.c

603

((uint32_t)addr[2] << 16) |

sys/dev/pci/ixgb_hw.c

604

((uint32_t)addr[3] << 24));

sys/dev/pci/ixgb_hw.c

606

rar_high = ((uint32_t)addr[4] |

sys/dev/pci/ixgb_hw.c

607

((uint32_t)addr[5] << 8) |

sys/dev/pci/ixgb_hw.c

62

static void ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value);

sys/dev/pci/ixgb_hw.c

623

uint32_t offset;

sys/dev/pci/ixgb_hw.c

639

uint32_t ctrl_reg;

sys/dev/pci/ixgb_hw.c

640

uint32_t pap_reg = 0; /* by default, assume no pause time */

sys/dev/pci/ixgb_hw.c

733

ixgb_read_phy_reg(struct ixgb_hw *hw, uint32_t reg_address,

sys/dev/pci/ixgb_hw.c

734

uint32_t phy_address, uint32_t device_type)

sys/dev/pci/ixgb_hw.c

736

uint32_t i;

sys/dev/pci/ixgb_hw.c

737

uint32_t data;

sys/dev/pci/ixgb_hw.c

738

uint32_t command = 0;

sys/dev/pci/ixgb_hw.c

74

uint32_t ixgb_mac_reset(struct ixgb_hw *hw);

sys/dev/pci/ixgb_hw.c

76

uint32_t

sys/dev/pci/ixgb_hw.c

79

uint32_t ctrl_reg;

sys/dev/pci/ixgb_hw.c

821

ixgb_write_phy_reg(struct ixgb_hw *hw, uint32_t reg_address,

sys/dev/pci/ixgb_hw.c

822

uint32_t phy_address, uint32_t device_type, uint16_t data)

sys/dev/pci/ixgb_hw.c

824

uint32_t i;

sys/dev/pci/ixgb_hw.c

825

uint32_t command = 0;

sys/dev/pci/ixgb_hw.c

832

IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data);

sys/dev/pci/ixgb_hw.c

899

uint32_t status_reg;

sys/dev/pci/ixgb_hw.c

900

uint32_t xpcss_reg;

sys/dev/pci/ixgb_hw.c

936

uint32_t newLFC, newRFC;

sys/dev/pci/ixgb_hw.c

961

volatile uint32_t temp_reg;

sys/dev/pci/ixgb_hw.h

597

uint32_t cmd_type_len;

sys/dev/pci/ixgb_hw.h

630

uint32_t cmd_type_len;

sys/dev/pci/ixgb_hw.h

689

uint32_t high_water; /* Flow Control High-water */

sys/dev/pci/ixgb_hw.h

690

uint32_t low_water; /* Flow Control Low-water */

sys/dev/pci/ixgb_hw.h

718

uint32_t phy_id; /* Phy Identifier */

sys/dev/pci/ixgb_hw.h

719

uint32_t phy_addr; /* XGMII address of Phy */

sys/dev/pci/ixgb_hw.h

722

uint32_t max_frame_size; /* Maximum frame size supported */

sys/dev/pci/ixgb_hw.h

723

uint32_t mc_filter_type; /* Multicast filter hash type */

sys/dev/pci/ixgb_hw.h

724

uint32_t num_mc_addrs; /* Number of current Multicast addrs */

sys/dev/pci/ixgb_hw.h

727

uint32_t num_tx_desc; /* Number of Transmit descriptors */

sys/dev/pci/ixgb_hw.h

728

uint32_t num_rx_desc; /* Number of Receive descriptors */

sys/dev/pci/ixgb_hw.h

729

uint32_t rx_buffer_size; /* Size of Receive buffer */

sys/dev/pci/ixgb_hw.h

738

uint32_t bar0; /* Base Address registers */

sys/dev/pci/ixgb_hw.h

739

uint32_t bar1;

sys/dev/pci/ixgb_hw.h

740

uint32_t bar2;

sys/dev/pci/ixgb_hw.h

741

uint32_t bar3;

sys/dev/pci/ixgb_hw.h

747

uint32_t lastLFC;

sys/dev/pci/ixgb_hw.h

748

uint32_t lastRFC;

sys/dev/pci/ixgb_hw.h

820

extern void ixgb_rar_set(struct ixgb_hw *hw, uint8_t *addr, uint32_t index);

sys/dev/pci/ixgb_hw.h

826

extern uint16_t ixgb_read_phy_reg(struct ixgb_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgb_hw.h

827

uint32_t phy_addr, uint32_t device_type);

sys/dev/pci/ixgb_hw.h

829

extern void ixgb_write_phy_reg(struct ixgb_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgb_hw.h

830

uint32_t phy_addr, uint32_t device_type,

sys/dev/pci/ixgb_hw.h

836

uint32_t mc_addr_count, uint32_t pad);

sys/dev/pci/ixgbe.c

102

static const uint32_t ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = {

sys/dev/pci/ixgbe.c

116

uint32_t eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));

sys/dev/pci/ixgbe.c

1174

uint32_t eerd;

sys/dev/pci/ixgbe.c

1176

uint32_t i;

sys/dev/pci/ixgbe.c

1238

uint32_t eewr;

sys/dev/pci/ixgbe.c

1303

int32_t ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, uint32_t ee_reg)

sys/dev/pci/ixgbe.c

1305

uint32_t i;

sys/dev/pci/ixgbe.c

1306

uint32_t reg;

sys/dev/pci/ixgbe.c

1341

uint32_t eec;

sys/dev/pci/ixgbe.c

1342

uint32_t i;

sys/dev/pci/ixgbe.c

1395

uint32_t timeout = 2000;

sys/dev/pci/ixgbe.c

1396

uint32_t i;

sys/dev/pci/ixgbe.c

1397

uint32_t swsm;

sys/dev/pci/ixgbe.c

1485

uint32_t swsm;

sys/dev/pci/ixgbe.c

1544

uint32_t eec;

sys/dev/pci/ixgbe.c

1570

uint32_t eec;

sys/dev/pci/ixgbe.c

1571

uint32_t mask;

sys/dev/pci/ixgbe.c

1572

uint32_t i;

sys/dev/pci/ixgbe.c

1625

uint32_t eec;

sys/dev/pci/ixgbe.c

1626

uint32_t i;

sys/dev/pci/ixgbe.c

1663

void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, uint32_t *eec)

sys/dev/pci/ixgbe.c

1682

void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, uint32_t *eec)

sys/dev/pci/ixgbe.c

1702

uint32_t eec;

sys/dev/pci/ixgbe.c

1908

int32_t ixgbe_set_rar_generic(struct ixgbe_hw *hw, uint32_t index, uint8_t *addr,

sys/dev/pci/ixgbe.c

1909

uint32_t vmdq, uint32_t enable_addr)

sys/dev/pci/ixgbe.c

1911

uint32_t rar_low, rar_high;

sys/dev/pci/ixgbe.c

1912

uint32_t rar_entries = hw->mac.num_rar_entries;

sys/dev/pci/ixgbe.c

1930

rar_low = ((uint32_t)addr[0] |

sys/dev/pci/ixgbe.c

1931

((uint32_t)addr[1] << 8) |

sys/dev/pci/ixgbe.c

1932

((uint32_t)addr[2] << 16) |

sys/dev/pci/ixgbe.c

1933

((uint32_t)addr[3] << 24));

sys/dev/pci/ixgbe.c

1941

rar_high |= ((uint32_t)addr[4] | ((uint32_t)addr[5] << 8));

sys/dev/pci/ixgbe.c

1959

int32_t ixgbe_clear_rar_generic(struct ixgbe_hw *hw, uint32_t index)

sys/dev/pci/ixgbe.c

1961

uint32_t rar_high;

sys/dev/pci/ixgbe.c

1962

uint32_t rar_entries = hw->mac.num_rar_entries;

sys/dev/pci/ixgbe.c

2000

uint32_t i;

sys/dev/pci/ixgbe.c

2001

uint32_t rar_entries = hw->mac.num_rar_entries;

sys/dev/pci/ixgbe.c

2067

void ixgbe_add_uc_addr(struct ixgbe_hw *hw, uint8_t *addr, uint32_t vmdq)

sys/dev/pci/ixgbe.c

2069

uint32_t rar_entries = hw->mac.num_rar_entries;

sys/dev/pci/ixgbe.c

2070

uint32_t rar;

sys/dev/pci/ixgbe.c

2107

uint32_t vector = 0;

sys/dev/pci/ixgbe.c

2144

uint32_t vector;

sys/dev/pci/ixgbe.c

2145

uint32_t vector_bit;

sys/dev/pci/ixgbe.c

2146

uint32_t vector_reg;

sys/dev/pci/ixgbe.c

2181

uint32_t mc_addr_count, ixgbe_mc_addr_itr next,

sys/dev/pci/ixgbe.c

2184

uint32_t i;

sys/dev/pci/ixgbe.c

2185

uint32_t vmdq;

sys/dev/pci/ixgbe.c

2267

uint32_t mflcn_reg, fccfg_reg;

sys/dev/pci/ixgbe.c

2268

uint32_t reg;

sys/dev/pci/ixgbe.c

2269

uint32_t fcrtl, fcrth;

sys/dev/pci/ixgbe.c

2380

reg = (uint32_t)hw->fc.pause_time * 0x00010001;

sys/dev/pci/ixgbe.c

2404

int32_t ixgbe_negotiate_fc(struct ixgbe_hw *hw, uint32_t adv_reg,

sys/dev/pci/ixgbe.c

2405

uint32_t lp_reg, uint32_t adv_sym,

sys/dev/pci/ixgbe.c

2406

uint32_t adv_asm, uint32_t lp_sym,

sys/dev/pci/ixgbe.c

2407

uint32_t lp_asm)

sys/dev/pci/ixgbe.c

2455

uint32_t pcs_anadv_reg, pcs_lpab_reg, linkstat;

sys/dev/pci/ixgbe.c

2492

uint32_t links2, anlp1_reg, autoc_reg, links;

sys/dev/pci/ixgbe.c

2546

return ixgbe_negotiate_fc(hw, (uint32_t)technology_ability_reg,

sys/dev/pci/ixgbe.c

2547

(uint32_t)lp_technology_ability_reg,

sys/dev/pci/ixgbe.c

2628

static uint32_t ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)

sys/dev/pci/ixgbe.c

2631

uint32_t pollcnt;

sys/dev/pci/ixgbe.c

2677

uint32_t i, poll;

sys/dev/pci/ixgbe.c

2741

int32_t ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe.c

2743

uint32_t gssr = 0;

sys/dev/pci/ixgbe.c

2744

uint32_t swmask = mask;

sys/dev/pci/ixgbe.c

2745

uint32_t fwmask = mask << 5;

sys/dev/pci/ixgbe.c

2746

uint32_t timeout = 200;

sys/dev/pci/ixgbe.c

2747

uint32_t i;

sys/dev/pci/ixgbe.c

275

uint32_t reg = 0, reg_bp = 0;

sys/dev/pci/ixgbe.c

2788

void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe.c

2790

uint32_t gssr;

sys/dev/pci/ixgbe.c

2791

uint32_t swmask = mask;

sys/dev/pci/ixgbe.c

2850

uint32_t *reg_val)

sys/dev/pci/ixgbe.c

2866

int32_t prot_autoc_write_generic(struct ixgbe_hw *hw, uint32_t reg_val,

sys/dev/pci/ixgbe.c

2881

uint32_t secrxreg;

sys/dev/pci/ixgbe.c

2900

int32_t ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, uint32_t regval)

sys/dev/pci/ixgbe.c

2917

int32_t ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, uint32_t index)

sys/dev/pci/ixgbe.c

2921

uint32_t autoc_reg = 0;

sys/dev/pci/ixgbe.c

2922

uint32_t led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);

sys/dev/pci/ixgbe.c

2967

int32_t ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, uint32_t index)

sys/dev/pci/ixgbe.c

2969

uint32_t autoc_reg = 0;

sys/dev/pci/ixgbe.c

2970

uint32_t led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);

sys/dev/pci/ixgbe.c

3054

int32_t ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, uint8_t *addr, uint32_t vmdq)

sys/dev/pci/ixgbe.c

3056

static const uint32_t NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;

sys/dev/pci/ixgbe.c

3057

uint32_t first_empty_rar = NO_EMPTY_RAR_FOUND;

sys/dev/pci/ixgbe.c

3058

uint32_t rar;

sys/dev/pci/ixgbe.c

3059

uint32_t rar_low, rar_high;

sys/dev/pci/ixgbe.c

3060

uint32_t addr_low, addr_high;

sys/dev/pci/ixgbe.c

3120

int32_t ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq)

sys/dev/pci/ixgbe.c

3122

uint32_t mpsar_lo, mpsar_hi;

sys/dev/pci/ixgbe.c

3123

uint32_t rar_entries = hw->mac.num_rar_entries;

sys/dev/pci/ixgbe.c

3173

int32_t ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq)

sys/dev/pci/ixgbe.c

3175

uint32_t mpsar;

sys/dev/pci/ixgbe.c

3176

uint32_t rar_entries = hw->mac.num_rar_entries;

sys/dev/pci/ixgbe.c

3227

int32_t ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, uint32_t vlan, bool vlvf_bypass)

sys/dev/pci/ixgbe.c

3230

uint32_t bits;

sys/dev/pci/ixgbe.c

3277

int32_t ixgbe_set_vfta_generic(struct ixgbe_hw *hw, uint32_t vlan, uint32_t vind,

sys/dev/pci/ixgbe.c

3280

uint32_t regidx, vfta_delta, vfta;

sys/dev/pci/ixgbe.c

3344

int32_t ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, uint32_t vlan, uint32_t vind,

sys/dev/pci/ixgbe.c

3345

bool vlan_on, uint32_t *vfta_delta, uint32_t vfta,

sys/dev/pci/ixgbe.c

3348

uint32_t bits;

sys/dev/pci/ixgbe.c

3428

uint32_t offset;

sys/dev/pci/ixgbe.c

3482

uint32_t links_reg, links_orig;

sys/dev/pci/ixgbe.c

3483

uint32_t i;

sys/dev/pci/ixgbe.c

3491

uint32_t sfp_cage_full;

sys/dev/pci/ixgbe.c

3599

uint8_t ixgbe_calculate_checksum(uint8_t *buffer, uint32_t length)

sys/dev/pci/ixgbe.c

3601

uint32_t i;

sys/dev/pci/ixgbe.c

3629

int32_t ixgbe_hic_unlocked(struct ixgbe_hw *hw, uint32_t *buffer, uint32_t length,

sys/dev/pci/ixgbe.c

3630

uint32_t timeout)

sys/dev/pci/ixgbe.c

3632

uint32_t hicr, i, fwsts;

sys/dev/pci/ixgbe.c

3654

if (length % sizeof(uint32_t)) {

sys/dev/pci/ixgbe.c

3707

int32_t ixgbe_host_interface_command(struct ixgbe_hw *hw, uint32_t *buffer,

sys/dev/pci/ixgbe.c

3708

uint32_t length, uint32_t timeout, bool return_data)

sys/dev/pci/ixgbe.c

3710

uint32_t hdr_size = sizeof(struct ixgbe_hic_hdr);

sys/dev/pci/ixgbe.c

3714

uint32_t bi;

sys/dev/pci/ixgbe.c

3715

uint32_t dword_len;

sys/dev/pci/ixgbe.c

3795

uint32_t gcr_ext, hlreg0, i, poll;

sys/dev/pci/ixgbe.c

3848

uint32_t pfdtxgswc;

sys/dev/pci/ixgbe.c

3849

uint32_t rxctrl;

sys/dev/pci/ixgbe.c

3870

uint32_t pfdtxgswc;

sys/dev/pci/ixgbe.c

3871

uint32_t rxctrl;

sys/dev/pci/ixgbe.c

3892

uint32_t fwsm;

sys/dev/pci/ixgbe.c

3910

uint32_t fwsm, manc, factps;

sys/dev/pci/ixgbe.c

3944

uint32_t speedcnt = 0;

sys/dev/pci/ixgbe.c

3945

uint32_t i = 0;

sys/dev/pci/ixgbe.c

434

uint32_t ctrl_ext;

sys/dev/pci/ixgbe.c

4395

int32_t ixgbe_set_rar(struct ixgbe_hw *hw, uint32_t index, uint8_t *addr,

sys/dev/pci/ixgbe.c

4396

uint32_t vmdq, uint32_t enable_addr)

sys/dev/pci/ixgbe.c

4410

int32_t ixgbe_set_vmdq(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq)

sys/dev/pci/ixgbe.c

4424

int32_t ixgbe_clear_vmdq(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq)

sys/dev/pci/ixgbe.c

4472

int32_t ixgbe_read_mbx(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size, uint16_t mbx_id)

sys/dev/pci/ixgbe.c

4497

int32_t ixgbe_poll_mbx(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size,

sys/dev/pci/ixgbe.c

4530

int32_t ixgbe_write_mbx(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size, uint16_t mbx_id)

sys/dev/pci/ixgbe.c

4689

static uint32_t ixgbe_read_mailbox_vf(struct ixgbe_hw *hw)

sys/dev/pci/ixgbe.c

4691

uint32_t vf_mailbox = IXGBE_READ_REG(hw, IXGBE_VFMAILBOX);

sys/dev/pci/ixgbe.c

4701

uint32_t vf_mailbox = ixgbe_read_mailbox_vf(hw);

sys/dev/pci/ixgbe.c

4711

uint32_t vf_mailbox = ixgbe_read_mailbox_vf(hw);

sys/dev/pci/ixgbe.c

4721

uint32_t vf_mailbox = ixgbe_read_mailbox_vf(hw);

sys/dev/pci/ixgbe.c

4738

static int32_t ixgbe_check_for_bit_vf(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe.c

4740

uint32_t vf_mailbox = ixgbe_read_mailbox_vf(hw);

sys/dev/pci/ixgbe.c

4817

uint32_t vf_mailbox;

sys/dev/pci/ixgbe.c

4859

int32_t ixgbe_read_posted_mbx(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size, uint16_t mbx_id)

sys/dev/pci/ixgbe.c

4888

int32_t ixgbe_write_posted_mbx(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size,

sys/dev/pci/ixgbe.c

4924

int32_t ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, uint32_t mask, int32_t index)

sys/dev/pci/ixgbe.c

4926

uint32_t pfmbicr = IXGBE_READ_REG(hw, IXGBE_PFMBICR(index));

sys/dev/pci/ixgbe.c

4943

uint32_t vf_shift = IXGBE_PFMBICR_SHIFT(vf_id);

sys/dev/pci/ixgbe.c

4956

uint32_t vf_shift = IXGBE_PFMBICR_SHIFT(vf_id);

sys/dev/pci/ixgbe.c

4958

uint32_t pfmbicr;

sys/dev/pci/ixgbe.c

4971

uint32_t vf_shift = IXGBE_PFMBICR_SHIFT(vf_id);

sys/dev/pci/ixgbe.c

4973

uint32_t pfmbicr;

sys/dev/pci/ixgbe.c

499

uint32_t i;

sys/dev/pci/ixgbe.c

4993

uint32_t vf_shift = IXGBE_PFMBICR_SHIFT(vf_id);

sys/dev/pci/ixgbe.c

500

uint32_t regval;

sys/dev/pci/ixgbe.c

5018

uint32_t vf_shift = IXGBE_PFVFLRE_SHIFT(vf_id);

sys/dev/pci/ixgbe.c

5019

uint32_t index = IXGBE_PFVFLRE_INDEX(vf_id);

sys/dev/pci/ixgbe.c

5021

uint32_t vflre = 0;

sys/dev/pci/ixgbe.c

5060

uint32_t pf_mailbox;

sys/dev/pci/ixgbe.c

5102

int32_t ixgbe_write_mbx_pf(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size,

sys/dev/pci/ixgbe.c

5105

uint32_t pf_mailbox;

sys/dev/pci/ixgbe.c

5152

static int32_t ixgbe_read_mbx_pf_legacy(struct ixgbe_hw *hw, uint32_t *msg,

sys/dev/pci/ixgbe.c

5189

int32_t ixgbe_read_mbx_pf(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size,

sys/dev/pci/ixgbe.c

5192

uint32_t pf_mailbox;

sys/dev/pci/ixgbe.c

5239

static int32_t ixgbe_write_mbx_vf_legacy(struct ixgbe_hw *hw, uint32_t *msg,

sys/dev/pci/ixgbe.c

5280

static int32_t ixgbe_read_mbx_vf_legacy(struct ixgbe_hw *hw, uint32_t *msg,

sys/dev/pci/ixgbe.c

5346

static int32_t ixgbe_write_mbx_pf_legacy(struct ixgbe_hw *hw, uint32_t *msg,

sys/dev/pci/ixgbe.c

57

void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, uint32_t *eec);

sys/dev/pci/ixgbe.c

58

void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, uint32_t *eec);

sys/dev/pci/ixgbe.c

67

int32_t prot_autoc_read_generic(struct ixgbe_hw *, bool *, uint32_t *);

sys/dev/pci/ixgbe.c

68

int32_t prot_autoc_write_generic(struct ixgbe_hw *, uint32_t, bool);

sys/dev/pci/ixgbe.c

681

uint32_t rar_high;

sys/dev/pci/ixgbe.c

682

uint32_t rar_low;

sys/dev/pci/ixgbe.c

73

int32_t ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, uint32_t mask,

sys/dev/pci/ixgbe.c

79

int32_t ixgbe_write_mbx_pf(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size,

sys/dev/pci/ixgbe.c

790

uint32_t reg;

sys/dev/pci/ixgbe.c

81

int32_t ixgbe_read_mbx_pf(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size,

sys/dev/pci/ixgbe.c

823

uint32_t reg_val;

sys/dev/pci/ixgbe.c

86

static const uint32_t ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = {

sys/dev/pci/ixgbe.c

871

int32_t ixgbe_led_on_generic(struct ixgbe_hw *hw, uint32_t index)

sys/dev/pci/ixgbe.c

873

uint32_t led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);

sys/dev/pci/ixgbe.c

894

int32_t ixgbe_led_off_generic(struct ixgbe_hw *hw, uint32_t index)

sys/dev/pci/ixgbe.c

896

uint32_t led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);

sys/dev/pci/ixgbe.c

90

static const uint32_t ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {

sys/dev/pci/ixgbe.c

922

uint32_t eec;

sys/dev/pci/ixgbe.c

94

static const uint32_t ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {

sys/dev/pci/ixgbe.c

98

static const uint32_t ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {

sys/dev/pci/ixgbe.h

141

extern uint16_t ixgbe_read_pci_cfg(struct ixgbe_hw *, uint32_t);

sys/dev/pci/ixgbe.h

144

extern void ixgbe_write_pci_cfg(struct ixgbe_hw *, uint32_t, uint16_t);

sys/dev/pci/ixgbe.h

176

int32_t ixgbe_led_on_generic(struct ixgbe_hw *hw, uint32_t index);

sys/dev/pci/ixgbe.h

177

int32_t ixgbe_led_off_generic(struct ixgbe_hw *hw, uint32_t index);

sys/dev/pci/ixgbe.h

189

int32_t ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, uint32_t ee_reg);

sys/dev/pci/ixgbe.h

191

int32_t ixgbe_set_rar_generic(struct ixgbe_hw *hw, uint32_t index, uint8_t *addr, uint32_t vmdq,

sys/dev/pci/ixgbe.h

192

uint32_t enable_addr);

sys/dev/pci/ixgbe.h

193

int32_t ixgbe_clear_rar_generic(struct ixgbe_hw *hw, uint32_t index);

sys/dev/pci/ixgbe.h

196

uint32_t mc_addr_count,

sys/dev/pci/ixgbe.h

200

int32_t ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, uint32_t regval);

sys/dev/pci/ixgbe.h

209

int32_t ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, uint32_t mask);

sys/dev/pci/ixgbe.h

210

void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, uint32_t mask);

sys/dev/pci/ixgbe.h

213

int32_t prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, uint32_t *reg_val);

sys/dev/pci/ixgbe.h

214

int32_t prot_autoc_write_generic(struct ixgbe_hw *hw, uint32_t reg_val, bool locked);

sys/dev/pci/ixgbe.h

216

int32_t ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, uint32_t index);

sys/dev/pci/ixgbe.h

217

int32_t ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, uint32_t index);

sys/dev/pci/ixgbe.h

219

int32_t ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq);

sys/dev/pci/ixgbe.h

220

int32_t ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq);

sys/dev/pci/ixgbe.h

221

int32_t ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, uint8_t *addr, uint32_t vmdq);

sys/dev/pci/ixgbe.h

223

int32_t ixgbe_set_vfta_generic(struct ixgbe_hw *hw, uint32_t vlan,

sys/dev/pci/ixgbe.h

224

uint32_t vind, bool vlan_on, bool);

sys/dev/pci/ixgbe.h

225

int32_t ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, uint32_t vlan, uint32_t vind,

sys/dev/pci/ixgbe.h

226

bool vlan_on, uint32_t*, uint32_t, bool);

sys/dev/pci/ixgbe.h

236

int32_t ixgbe_host_interface_command(struct ixgbe_hw *hw, uint32_t *buffer,

sys/dev/pci/ixgbe.h

237

uint32_t length, uint32_t timeout,

sys/dev/pci/ixgbe.h

239

int32_t ixgbe_hic_unlocked(struct ixgbe_hw *, uint32_t *buffer, uint32_t length, uint32_t timeout);

sys/dev/pci/ixgbe.h

253

int32_t ixgbe_negotiate_fc(struct ixgbe_hw *hw, uint32_t adv_reg, uint32_t lp_reg,

sys/dev/pci/ixgbe.h

254

uint32_t adv_sym, uint32_t adv_asm, uint32_t lp_sym, uint32_t lp_asm);

sys/dev/pci/ixgbe.h

274

int32_t ixgbe_set_rar(struct ixgbe_hw *hw, uint32_t index, uint8_t *addr,

sys/dev/pci/ixgbe.h

275

uint32_t vmdq, uint32_t enable_addr);

sys/dev/pci/ixgbe.h

276

int32_t ixgbe_set_vmdq(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq);

sys/dev/pci/ixgbe.h

277

int32_t ixgbe_clear_vmdq(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq);

sys/dev/pci/ixgbe.h

280

void ixgbe_add_uc_addr(struct ixgbe_hw *hw, uint8_t *addr, uint32_t vmdq);

sys/dev/pci/ixgbe.h

289

bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, uint32_t phy_addr);

sys/dev/pci/ixgbe.h

290

enum ixgbe_phy_type ixgbe_get_phy_type_from_id(uint32_t phy_id);

sys/dev/pci/ixgbe.h

294

int32_t ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe.h

295

uint32_t device_type, uint16_t *phy_data);

sys/dev/pci/ixgbe.h

296

int32_t ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe.h

297

uint32_t device_type, uint16_t phy_data);

sys/dev/pci/ixgbe.h

298

int32_t ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe.h

299

uint32_t device_type, uint16_t *phy_data);

sys/dev/pci/ixgbe.h

300

int32_t ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe.h

301

uint32_t device_type, uint16_t phy_data);

sys/dev/pci/ixgbe.h

364

uint32_t ixgbe_get_num_of_tx_queues_vf(struct ixgbe_hw *hw);

sys/dev/pci/ixgbe.h

365

uint32_t ixgbe_get_num_of_rx_queues_vf(struct ixgbe_hw *hw);

sys/dev/pci/ixgbe.h

371

int32_t ixgbe_set_rar_vf(struct ixgbe_hw *hw, uint32_t index, uint8_t *addr, uint32_t vmdq,

sys/dev/pci/ixgbe.h

372

uint32_t enable_addr);

sys/dev/pci/ixgbe.h

373

int32_t ixgbevf_set_uc_addr_vf(struct ixgbe_hw *hw, uint32_t index, uint8_t *addr);

sys/dev/pci/ixgbe.h

375

uint32_t mc_addr_count, ixgbe_mc_addr_itr,

sys/dev/pci/ixgbe.h

379

int32_t ixgbe_set_vfta_vf(struct ixgbe_hw *hw, uint32_t vlan, uint32_t vind,

sys/dev/pci/ixgbe.h

387

int32_t ixgbe_read_mbx(struct ixgbe_hw *, uint32_t *, uint16_t, uint16_t);

sys/dev/pci/ixgbe.h

388

int32_t ixgbe_poll_mbx(struct ixgbe_hw *, uint32_t *, uint16_t, uint16_t);

sys/dev/pci/ixgbe.h

389

int32_t ixgbe_write_mbx(struct ixgbe_hw *, uint32_t *, uint16_t, uint16_t);

sys/dev/pci/ixgbe.h

390

int32_t ixgbe_read_posted_mbx(struct ixgbe_hw *, uint32_t *, uint16_t, uint16_t);

sys/dev/pci/ixgbe.h

391

int32_t ixgbe_write_posted_mbx(struct ixgbe_hw *, uint32_t *, uint16_t, uint16_t);

sys/dev/pci/ixgbe_82598.c

1010

int32_t ixgbe_set_vfta_82598(struct ixgbe_hw *hw, uint32_t vlan, uint32_t vind,

sys/dev/pci/ixgbe_82598.c

1013

uint32_t regindex;

sys/dev/pci/ixgbe_82598.c

1014

uint32_t bitindex;

sys/dev/pci/ixgbe_82598.c

1015

uint32_t bits;

sys/dev/pci/ixgbe_82598.c

1016

uint32_t vftabyte;

sys/dev/pci/ixgbe_82598.c

1059

uint32_t offset;

sys/dev/pci/ixgbe_82598.c

1060

uint32_t vlanbyte;

sys/dev/pci/ixgbe_82598.c

1083

int32_t ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val)

sys/dev/pci/ixgbe_82598.c

1085

uint32_t atlas_ctl;

sys/dev/pci/ixgbe_82598.c

1107

int32_t ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t val)

sys/dev/pci/ixgbe_82598.c

1109

uint32_t atlas_ctl;

sys/dev/pci/ixgbe_82598.c

1138

uint32_t i;

sys/dev/pci/ixgbe_82598.c

1219

uint32_t autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);

sys/dev/pci/ixgbe_82598.c

1220

uint32_t pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;

sys/dev/pci/ixgbe_82598.c

1221

uint32_t pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;

sys/dev/pci/ixgbe_82598.c

1353

int32_t ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, uint32_t regval)

sys/dev/pci/ixgbe_82598.c

264

uint32_t regval;

sys/dev/pci/ixgbe_82598.c

265

uint32_t i;

sys/dev/pci/ixgbe_82598.c

309

uint32_t autoc = 0;

sys/dev/pci/ixgbe_82598.c

419

uint32_t fctrl_reg;

sys/dev/pci/ixgbe_82598.c

420

uint32_t rmcs_reg;

sys/dev/pci/ixgbe_82598.c

421

uint32_t reg;

sys/dev/pci/ixgbe_82598.c

422

uint32_t fcrtl, fcrth;

sys/dev/pci/ixgbe_82598.c

423

uint32_t link_speed = 0;

sys/dev/pci/ixgbe_82598.c

546

reg = (uint32_t)hw->fc.pause_time * 0x00010001;

sys/dev/pci/ixgbe_82598.c

568

uint32_t autoc_reg;

sys/dev/pci/ixgbe_82598.c

569

uint32_t links_reg;

sys/dev/pci/ixgbe_82598.c

570

uint32_t i;

sys/dev/pci/ixgbe_82598.c

615

uint32_t timeout;

sys/dev/pci/ixgbe_82598.c

654

uint32_t links_reg;

sys/dev/pci/ixgbe_82598.c

655

uint32_t i;

sys/dev/pci/ixgbe_82598.c

69

int32_t ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq);

sys/dev/pci/ixgbe_82598.c

70

int32_t ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq);

sys/dev/pci/ixgbe_82598.c

71

int32_t ixgbe_set_vfta_82598(struct ixgbe_hw *hw, uint32_t vlan,

sys/dev/pci/ixgbe_82598.c

72

uint32_t vind, bool vlan_on, bool vlvf_bypass);

sys/dev/pci/ixgbe_82598.c

74

int32_t ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val);

sys/dev/pci/ixgbe_82598.c

746

uint32_t curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);

sys/dev/pci/ixgbe_82598.c

747

uint32_t autoc = curr_autoc;

sys/dev/pci/ixgbe_82598.c

748

uint32_t link_mode = autoc & IXGBE_AUTOC_LMS_MASK;

sys/dev/pci/ixgbe_82598.c

75

int32_t ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t val);

sys/dev/pci/ixgbe_82598.c

822

uint32_t ctrl;

sys/dev/pci/ixgbe_82598.c

823

uint32_t gheccr;

sys/dev/pci/ixgbe_82598.c

824

uint32_t i;

sys/dev/pci/ixgbe_82598.c

825

uint32_t autoc;

sys/dev/pci/ixgbe_82598.c

84

int32_t ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, uint32_t regval);

sys/dev/pci/ixgbe_82598.c

954

int32_t ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq)

sys/dev/pci/ixgbe_82598.c

956

uint32_t rar_high;

sys/dev/pci/ixgbe_82598.c

957

uint32_t rar_entries = hw->mac.num_rar_entries;

sys/dev/pci/ixgbe_82598.c

98

uint32_t gcr = IXGBE_READ_REG(hw, IXGBE_GCR);

sys/dev/pci/ixgbe_82598.c

980

int32_t ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq)

sys/dev/pci/ixgbe_82598.c

982

uint32_t rar_high;

sys/dev/pci/ixgbe_82598.c

983

uint32_t rar_entries = hw->mac.num_rar_entries;

sys/dev/pci/ixgbe_82599.c

1058

uint32_t ctrl = 0;

sys/dev/pci/ixgbe_82599.c

1059

uint32_t i, autoc, autoc2;

sys/dev/pci/ixgbe_82599.c

1060

uint32_t curr_lms;

sys/dev/pci/ixgbe_82599.c

1213

int32_t ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg,

sys/dev/pci/ixgbe_82599.c

1216

uint32_t core_ctl;

sys/dev/pci/ixgbe_82599.c

1238

int32_t ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg,

sys/dev/pci/ixgbe_82599.c

1241

uint32_t core_ctl;

sys/dev/pci/ixgbe_82599.c

1330

uint32_t autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);

sys/dev/pci/ixgbe_82599.c

1331

uint32_t autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);

sys/dev/pci/ixgbe_82599.c

1332

uint32_t pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;

sys/dev/pci/ixgbe_82599.c

1333

uint32_t pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;

sys/dev/pci/ixgbe_82599.c

1334

uint32_t pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;

sys/dev/pci/ixgbe_82599.c

1415

int32_t ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, uint32_t regval)

sys/dev/pci/ixgbe_82599.c

156

uint32_t esdp;

sys/dev/pci/ixgbe_82599.c

1589

uint32_t anlp1_reg = 0;

sys/dev/pci/ixgbe_82599.c

1590

uint32_t i, autoc_reg, autoc2_reg;

sys/dev/pci/ixgbe_82599.c

1642

uint32_t esdp;

sys/dev/pci/ixgbe_82599.c

1700

uint32_t esdp;

sys/dev/pci/ixgbe_82599.c

287

uint32_t *reg_val)

sys/dev/pci/ixgbe_82599.c

316

int32_t prot_autoc_write_82599(struct ixgbe_hw *hw, uint32_t autoc, bool locked)

sys/dev/pci/ixgbe_82599.c

438

uint32_t autoc = 0;

sys/dev/pci/ixgbe_82599.c

606

uint32_t autoc2_reg;

sys/dev/pci/ixgbe_82599.c

632

uint32_t autoc_reg;

sys/dev/pci/ixgbe_82599.c

633

uint32_t links_reg;

sys/dev/pci/ixgbe_82599.c

634

uint32_t i;

sys/dev/pci/ixgbe_82599.c

69

int32_t ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg,

sys/dev/pci/ixgbe_82599.c

699

uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);

sys/dev/pci/ixgbe_82599.c

71

int32_t ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg,

sys/dev/pci/ixgbe_82599.c

722

uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);

sys/dev/pci/ixgbe_82599.c

768

uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);

sys/dev/pci/ixgbe_82599.c

77

int32_t ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, uint32_t regval);

sys/dev/pci/ixgbe_82599.c

78

int32_t prot_autoc_read_82599(struct ixgbe_hw *, bool *locked, uint32_t *reg_val);

sys/dev/pci/ixgbe_82599.c

79

int32_t prot_autoc_write_82599(struct ixgbe_hw *, uint32_t reg_val, bool locked);

sys/dev/pci/ixgbe_82599.c

803

uint32_t autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);

sys/dev/pci/ixgbe_82599.c

913

uint32_t pma_pmd_1g, link_mode;

sys/dev/pci/ixgbe_82599.c

915

uint32_t current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);

sys/dev/pci/ixgbe_82599.c

917

uint32_t orig_autoc = 0;

sys/dev/pci/ixgbe_82599.c

919

uint32_t autoc = current_autoc;

sys/dev/pci/ixgbe_82599.c

920

uint32_t autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);

sys/dev/pci/ixgbe_82599.c

921

uint32_t pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;

sys/dev/pci/ixgbe_82599.c

922

uint32_t links_reg;

sys/dev/pci/ixgbe_82599.c

923

uint32_t i;

sys/dev/pci/ixgbe_phy.c

1062

uint32_t time_out;

sys/dev/pci/ixgbe_phy.c

1063

uint32_t max_time_out = 10;

sys/dev/pci/ixgbe_phy.c

117

uint32_t swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_phy.c

1227

uint32_t i;

sys/dev/pci/ixgbe_phy.c

1391

uint32_t vendor_oui = 0;

sys/dev/pci/ixgbe_phy.c

1713

uint32_t vendor_oui = 0;

sys/dev/pci/ixgbe_phy.c

2052

uint32_t max_retry = 10;

sys/dev/pci/ixgbe_phy.c

2053

uint32_t retry = 0;

sys/dev/pci/ixgbe_phy.c

2054

uint32_t swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_phy.c

2178

uint32_t max_retry = 1;

sys/dev/pci/ixgbe_phy.c

2179

uint32_t retry = 0;

sys/dev/pci/ixgbe_phy.c

2180

uint32_t swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_phy.c

226

uint32_t swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_phy.c

2278

uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));

sys/dev/pci/ixgbe_phy.c

2313

uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));

sys/dev/pci/ixgbe_phy.c

2314

uint32_t data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);

sys/dev/pci/ixgbe_phy.c

2315

uint32_t clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);

sys/dev/pci/ixgbe_phy.c

2316

uint32_t bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);

sys/dev/pci/ixgbe_phy.c

2374

uint32_t i2cctl;

sys/dev/pci/ixgbe_phy.c

2405

uint32_t data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);

sys/dev/pci/ixgbe_phy.c

2407

uint32_t i = 0;

sys/dev/pci/ixgbe_phy.c

2408

uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));

sys/dev/pci/ixgbe_phy.c

2409

uint32_t timeout = 10;

sys/dev/pci/ixgbe_phy.c

2458

uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));

sys/dev/pci/ixgbe_phy.c

2459

uint32_t data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);

sys/dev/pci/ixgbe_phy.c

2495

uint32_t i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));

sys/dev/pci/ixgbe_phy.c

2529

void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl)

sys/dev/pci/ixgbe_phy.c

2531

uint32_t clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);

sys/dev/pci/ixgbe_phy.c

2532

uint32_t i = 0;

sys/dev/pci/ixgbe_phy.c

2533

uint32_t timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;

sys/dev/pci/ixgbe_phy.c

2534

uint32_t i2cctl_r = 0;

sys/dev/pci/ixgbe_phy.c

2565

void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl)

sys/dev/pci/ixgbe_phy.c

2588

int32_t ixgbe_set_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl, bool data)

sys/dev/pci/ixgbe_phy.c

2590

uint32_t data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);

sys/dev/pci/ixgbe_phy.c

2635

bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl)

sys/dev/pci/ixgbe_phy.c

2638

uint32_t data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);

sys/dev/pci/ixgbe_phy.c

2666

uint32_t i2cctl;

sys/dev/pci/ixgbe_phy.c

2667

uint32_t i;

sys/dev/pci/ixgbe_phy.c

2730

uint32_t status;

sys/dev/pci/ixgbe_phy.c

449

uint32_t mmngc;

sys/dev/pci/ixgbe_phy.c

473

bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, uint32_t phy_addr)

sys/dev/pci/ixgbe_phy.c

48

void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl);

sys/dev/pci/ixgbe_phy.c

49

void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, uint32_t *i2cctl);

sys/dev/pci/ixgbe_phy.c

499

uint32_t status;

sys/dev/pci/ixgbe_phy.c

50

int32_t ixgbe_set_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl, bool data);

sys/dev/pci/ixgbe_phy.c

51

bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, uint32_t *i2cctl);

sys/dev/pci/ixgbe_phy.c

510

hw->phy.id = (uint32_t)(phy_id_high << 16);

sys/dev/pci/ixgbe_phy.c

514

hw->phy.id |= (uint32_t)(phy_id_low & IXGBE_PHY_REVISION_MASK);

sys/dev/pci/ixgbe_phy.c

516

(uint32_t)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);

sys/dev/pci/ixgbe_phy.c

529

enum ixgbe_phy_type ixgbe_get_phy_type_from_id(uint32_t phy_id)

sys/dev/pci/ixgbe_phy.c

571

uint32_t i;

sys/dev/pci/ixgbe_phy.c

652

int32_t ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_phy.c

653

uint32_t device_type, uint16_t *phy_data)

sys/dev/pci/ixgbe_phy.c

655

uint32_t i, data, command;

sys/dev/pci/ixgbe_phy.c

734

int32_t ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_phy.c

735

uint32_t device_type, uint16_t *phy_data)

sys/dev/pci/ixgbe_phy.c

738

uint32_t gssr = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_phy.c

760

int32_t ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_phy.c

761

uint32_t device_type, uint16_t phy_data)

sys/dev/pci/ixgbe_phy.c

763

uint32_t i, command;

sys/dev/pci/ixgbe_phy.c

766

IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (uint32_t)phy_data);

sys/dev/pci/ixgbe_phy.c

834

int32_t ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_phy.c

835

uint32_t device_type, uint16_t phy_data)

sys/dev/pci/ixgbe_phy.c

838

uint32_t gssr = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_type.h

2932

#define __le32 uint32_t

sys/dev/pci/ixgbe_type.h

2941

#define __be32 uint32_t

sys/dev/pci/ixgbe_type.h

312

uint32_t etk_id;

sys/dev/pci/ixgbe_type.h

3190

uint32_t address;

sys/dev/pci/ixgbe_type.h

3199

uint32_t address;

sys/dev/pci/ixgbe_type.h

3399

typedef uint32_t ixgbe_autoneg_advertised;

sys/dev/pci/ixgbe_type.h

3401

typedef uint32_t ixgbe_link_speed;

sys/dev/pci/ixgbe_type.h

3777

uint32_t num_mc_addrs;

sys/dev/pci/ixgbe_type.h

3778

uint32_t rar_used_count;

sys/dev/pci/ixgbe_type.h

3779

uint32_t mta_in_use;

sys/dev/pci/ixgbe_type.h

3780

uint32_t overflow_promisc;

sys/dev/pci/ixgbe_type.h

3797

uint32_t high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */

sys/dev/pci/ixgbe_type.h

3798

uint32_t low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */

sys/dev/pci/ixgbe_type.h

3893

uint32_t *vmdq);

sys/dev/pci/ixgbe_type.h

3918

int32_t (*read_analog_reg8)(struct ixgbe_hw*, uint32_t, uint8_t*);

sys/dev/pci/ixgbe_type.h

3919

int32_t (*write_analog_reg8)(struct ixgbe_hw*, uint32_t, uint8_t);

sys/dev/pci/ixgbe_type.h

3921

int32_t (*enable_rx_dma)(struct ixgbe_hw *, uint32_t);

sys/dev/pci/ixgbe_type.h

3924

int32_t (*acquire_swfw_sync)(struct ixgbe_hw *, uint32_t);

sys/dev/pci/ixgbe_type.h

3925

void (*release_swfw_sync)(struct ixgbe_hw *, uint32_t);

sys/dev/pci/ixgbe_type.h

3927

int32_t (*prot_autoc_read)(struct ixgbe_hw *, bool *, uint32_t *);

sys/dev/pci/ixgbe_type.h

3928

int32_t (*prot_autoc_write)(struct ixgbe_hw *, uint32_t, bool);

sys/dev/pci/ixgbe_type.h

3942

int32_t (*led_on)(struct ixgbe_hw *, uint32_t);

sys/dev/pci/ixgbe_type.h

3943

int32_t (*led_off)(struct ixgbe_hw *, uint32_t);

sys/dev/pci/ixgbe_type.h

3944

int32_t (*blink_led_start)(struct ixgbe_hw *, uint32_t);

sys/dev/pci/ixgbe_type.h

3945

int32_t (*blink_led_stop)(struct ixgbe_hw *, uint32_t);

sys/dev/pci/ixgbe_type.h

3948

int32_t (*set_rar)(struct ixgbe_hw *, uint32_t, uint8_t *, uint32_t, uint32_t);

sys/dev/pci/ixgbe_type.h

3949

int32_t (*set_uc_addr)(struct ixgbe_hw *, uint32_t, uint8_t *);

sys/dev/pci/ixgbe_type.h

3950

int32_t (*clear_rar)(struct ixgbe_hw *, uint32_t);

sys/dev/pci/ixgbe_type.h

3951

int32_t (*insert_mac_addr)(struct ixgbe_hw *, uint8_t *, uint32_t);

sys/dev/pci/ixgbe_type.h

3952

int32_t (*set_vmdq)(struct ixgbe_hw *, uint32_t, uint32_t);

sys/dev/pci/ixgbe_type.h

3953

int32_t (*clear_vmdq)(struct ixgbe_hw *, uint32_t, uint32_t);

sys/dev/pci/ixgbe_type.h

3955

int32_t (*update_mc_addr_list)(struct ixgbe_hw *, uint8_t *, uint32_t,

sys/dev/pci/ixgbe_type.h

3962

int32_t (*set_vfta)(struct ixgbe_hw *, uint32_t, uint32_t, bool, bool);

sys/dev/pci/ixgbe_type.h

3963

int32_t (*set_vlvf)(struct ixgbe_hw *, uint32_t, uint32_t, bool, uint32_t *, uint32_t,

sys/dev/pci/ixgbe_type.h

3985

int32_t (*read_iosf_sb_reg)(struct ixgbe_hw *, uint32_t, uint32_t, uint32_t *);

sys/dev/pci/ixgbe_type.h

3986

int32_t (*write_iosf_sb_reg)(struct ixgbe_hw *, uint32_t, uint32_t, uint32_t);

sys/dev/pci/ixgbe_type.h

3994

int32_t (*read_reg)(struct ixgbe_hw *, uint32_t, uint32_t, uint16_t *);

sys/dev/pci/ixgbe_type.h

3995

int32_t (*write_reg)(struct ixgbe_hw *, uint32_t, uint32_t, uint16_t);

sys/dev/pci/ixgbe_type.h

3996

int32_t (*read_reg_mdi)(struct ixgbe_hw *, uint32_t, uint32_t, uint16_t *);

sys/dev/pci/ixgbe_type.h

3997

int32_t (*write_reg_mdi)(struct ixgbe_hw *, uint32_t, uint32_t, uint16_t);

sys/dev/pci/ixgbe_type.h

4043

uint32_t semaphore_delay;

sys/dev/pci/ixgbe_type.h

4057

uint32_t mta_shadow[IXGBE_MAX_MTA];

sys/dev/pci/ixgbe_type.h

4059

uint32_t mcft_size;

sys/dev/pci/ixgbe_type.h

4060

uint32_t vft_size;

sys/dev/pci/ixgbe_type.h

4061

uint32_t num_rar_entries;

sys/dev/pci/ixgbe_type.h

4062

uint32_t rar_highwater;

sys/dev/pci/ixgbe_type.h

4063

uint32_t rx_pb_size;

sys/dev/pci/ixgbe_type.h

4064

uint32_t max_tx_queues;

sys/dev/pci/ixgbe_type.h

4065

uint32_t max_rx_queues;

sys/dev/pci/ixgbe_type.h

4066

uint32_t orig_autoc;

sys/dev/pci/ixgbe_type.h

4068

uint32_t orig_autoc2;

sys/dev/pci/ixgbe_type.h

4076

uint32_t max_link_up_time;

sys/dev/pci/ixgbe_type.h

4082

uint32_t addr;

sys/dev/pci/ixgbe_type.h

4083

uint32_t id;

sys/dev/pci/ixgbe_type.h

4086

uint32_t revision;

sys/dev/pci/ixgbe_type.h

4088

uint32_t phy_semaphore_mask;

sys/dev/pci/ixgbe_type.h

4099

uint32_t nw_mng_if_sel;

sys/dev/pci/ixgbe_type.h

4279

int32_t (*read)(struct ixgbe_hw *, uint32_t *, uint16_t, uint16_t);

sys/dev/pci/ixgbe_type.h

4280

int32_t (*write)(struct ixgbe_hw *, uint32_t *, uint16_t, uint16_t);

sys/dev/pci/ixgbe_type.h

4281

int32_t (*read_posted)(struct ixgbe_hw *, uint32_t *, uint16_t, uint16_t);

sys/dev/pci/ixgbe_type.h

4282

int32_t (*write_posted)(struct ixgbe_hw *, uint32_t *, uint16_t, uint16_t);

sys/dev/pci/ixgbe_type.h

4290

uint32_t msgs_tx;

sys/dev/pci/ixgbe_type.h

4291

uint32_t msgs_rx;

sys/dev/pci/ixgbe_type.h

4293

uint32_t acks;

sys/dev/pci/ixgbe_type.h

4294

uint32_t reqs;

sys/dev/pci/ixgbe_type.h

4295

uint32_t rsts;

sys/dev/pci/ixgbe_type.h

4301

uint32_t timeout;

sys/dev/pci/ixgbe_type.h

4302

uint32_t usec_delay;

sys/dev/pci/ixgbe_type.h

4303

uint32_t vf_mailbox;

sys/dev/pci/ixgbe_type.h

4318

const uint32_t *mvals;

sys/dev/pci/ixgbe_type.h

4453

uint32_t logs;

sys/dev/pci/ixgbe_type.h

4454

uint32_t clear_off;

sys/dev/pci/ixgbe_type.h

711

uint32_t link_speed;

sys/dev/pci/ixgbe_vf.c

131

uint32_t vfsrrctl;

sys/dev/pci/ixgbe_vf.c

132

uint32_t vfdca_rxctrl;

sys/dev/pci/ixgbe_vf.c

133

uint32_t vfdca_txctrl;

sys/dev/pci/ixgbe_vf.c

211

uint32_t timeout = IXGBE_VF_INIT_TIMEOUT;

sys/dev/pci/ixgbe_vf.c

213

uint32_t msgbuf[IXGBE_VF_PERMADDR_MSG_LEN];

sys/dev/pci/ixgbe_vf.c

285

uint32_t reg_val;

sys/dev/pci/ixgbe_vf.c

320

static int32_t ixgbevf_write_msg_read_ack(struct ixgbe_hw *hw, uint32_t *msg,

sys/dev/pci/ixgbe_vf.c

321

uint32_t *retmsg, uint16_t size)

sys/dev/pci/ixgbe_vf.c

339

int32_t ixgbe_set_rar_vf(struct ixgbe_hw *hw, uint32_t index, uint8_t *addr,

sys/dev/pci/ixgbe_vf.c

340

uint32_t vmdq, uint32_t enable_addr)

sys/dev/pci/ixgbe_vf.c

342

uint32_t msgbuf[3];

sys/dev/pci/ixgbe_vf.c

374

uint32_t mc_addr_count, ixgbe_mc_addr_itr next,

sys/dev/pci/ixgbe_vf.c

377

uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE];

sys/dev/pci/ixgbe_vf.c

379

uint32_t vector;

sys/dev/pci/ixgbe_vf.c

380

uint32_t cnt, i;

sys/dev/pci/ixgbe_vf.c

381

uint32_t vmdq;

sys/dev/pci/ixgbe_vf.c

418

uint32_t msgbuf[2];

sys/dev/pci/ixgbe_vf.c

456

uint32_t msgbuf[2];

sys/dev/pci/ixgbe_vf.c

485

int32_t ixgbe_set_vfta_vf(struct ixgbe_hw *hw, uint32_t vlan, uint32_t vind,

sys/dev/pci/ixgbe_vf.c

488

uint32_t msgbuf[2];

sys/dev/pci/ixgbe_vf.c

509

uint32_t ixgbe_get_num_of_tx_queues_vf(struct ixgbe_hw *hw)

sys/dev/pci/ixgbe_vf.c

520

uint32_t ixgbe_get_num_of_rx_queues_vf(struct ixgbe_hw *hw)

sys/dev/pci/ixgbe_vf.c

540

int32_t ixgbevf_set_uc_addr_vf(struct ixgbe_hw *hw, uint32_t index, uint8_t *addr)

sys/dev/pci/ixgbe_vf.c

542

uint32_t msgbuf[3], msgbuf_chk;

sys/dev/pci/ixgbe_vf.c

599

uint32_t in_msg = 0;

sys/dev/pci/ixgbe_vf.c

600

uint32_t links_reg;

sys/dev/pci/ixgbe_vf.c

696

uint32_t msgbuf[2];

sys/dev/pci/ixgbe_vf.c

720

uint32_t msg[3];

sys/dev/pci/ixgbe_vf.c

747

uint32_t msg[5];

sys/dev/pci/ixgbe_x540.c

217

uint32_t ctrl, i;

sys/dev/pci/ixgbe_x540.c

218

uint32_t swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_x540.c

345

uint32_t eec;

sys/dev/pci/ixgbe_x540.c

614

uint32_t flup;

sys/dev/pci/ixgbe_x540.c

661

uint32_t i;

sys/dev/pci/ixgbe_x540.c

662

uint32_t reg;

sys/dev/pci/ixgbe_x540.c

69

int32_t ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, uint32_t mask);

sys/dev/pci/ixgbe_x540.c

691

int32_t ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe_x540.c

693

uint32_t swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;

sys/dev/pci/ixgbe_x540.c

694

uint32_t fwmask = swmask << 5;

sys/dev/pci/ixgbe_x540.c

695

uint32_t swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;

sys/dev/pci/ixgbe_x540.c

696

uint32_t timeout = 200;

sys/dev/pci/ixgbe_x540.c

697

uint32_t hwmask = 0;

sys/dev/pci/ixgbe_x540.c

698

uint32_t swfw_sync;

sys/dev/pci/ixgbe_x540.c

699

uint32_t i;

sys/dev/pci/ixgbe_x540.c

70

void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, uint32_t mask);

sys/dev/pci/ixgbe_x540.c

73

int32_t ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, uint32_t index);

sys/dev/pci/ixgbe_x540.c

74

int32_t ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, uint32_t index);

sys/dev/pci/ixgbe_x540.c

763

uint32_t rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |

sys/dev/pci/ixgbe_x540.c

788

void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe_x540.c

790

uint32_t swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);

sys/dev/pci/ixgbe_x540.c

791

uint32_t swfw_sync;

sys/dev/pci/ixgbe_x540.c

816

uint32_t timeout = 2000;

sys/dev/pci/ixgbe_x540.c

817

uint32_t i;

sys/dev/pci/ixgbe_x540.c

818

uint32_t swsm;

sys/dev/pci/ixgbe_x540.c

873

uint32_t swsm;

sys/dev/pci/ixgbe_x540.c

899

uint32_t rmask;

sys/dev/pci/ixgbe_x540.c

928

int32_t ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, uint32_t index)

sys/dev/pci/ixgbe_x540.c

930

uint32_t macc_reg;

sys/dev/pci/ixgbe_x540.c

931

uint32_t ledctl_reg;

sys/dev/pci/ixgbe_x540.c

969

int32_t ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, uint32_t index)

sys/dev/pci/ixgbe_x540.c

971

uint32_t macc_reg;

sys/dev/pci/ixgbe_x540.c

972

uint32_t ledctl_reg;

sys/dev/pci/ixgbe_x550.c

1009

uint32_t eec;

sys/dev/pci/ixgbe_x550.c

102

int32_t ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, uint32_t mask);

sys/dev/pci/ixgbe_x550.c

103

void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, uint32_t mask);

sys/dev/pci/ixgbe_x550.c

1054

IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (uint32_t)pfflp);

sys/dev/pci/ixgbe_x550.c

1055

IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (uint32_t)(pfflp >> 32));

sys/dev/pci/ixgbe_x550.c

1067

int32_t ixgbe_iosf_wait(struct ixgbe_hw *hw, uint32_t *ctrl)

sys/dev/pci/ixgbe_x550.c

1069

uint32_t i, command = 0;

sys/dev/pci/ixgbe_x550.c

108

int32_t ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_x550.c

109

uint32_t device_type, uint16_t *phy_data);

sys/dev/pci/ixgbe_x550.c

1099

int32_t ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_x550.c

110

int32_t ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_x550.c

1100

uint32_t device_type, uint32_t data)

sys/dev/pci/ixgbe_x550.c

1102

uint32_t gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;

sys/dev/pci/ixgbe_x550.c

1103

uint32_t command, error __unused;

sys/dev/pci/ixgbe_x550.c

111

uint32_t device_type, uint16_t phy_data);

sys/dev/pci/ixgbe_x550.c

1145

int32_t ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_x550.c

1146

uint32_t device_type, uint32_t *data)

sys/dev/pci/ixgbe_x550.c

1148

uint32_t gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;

sys/dev/pci/ixgbe_x550.c

1149

uint32_t command, error __unused;

sys/dev/pci/ixgbe_x550.c

1201

status = ixgbe_host_interface_command(hw, (uint32_t *)&token_cmd,

sys/dev/pci/ixgbe_x550.c

1239

status = ixgbe_host_interface_command(hw, (uint32_t *)&token_cmd,

sys/dev/pci/ixgbe_x550.c

124

int32_t ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, uint32_t led_idx);

sys/dev/pci/ixgbe_x550.c

125

int32_t ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, uint32_t led_idx);

sys/dev/pci/ixgbe_x550.c

1260

int32_t ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_x550.c

1261

uint32_t device_type, uint32_t data)

sys/dev/pci/ixgbe_x550.c

1275

status = ixgbe_host_interface_command(hw, (uint32_t *)&write_cmd,

sys/dev/pci/ixgbe_x550.c

1289

int32_t ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_x550.c

1290

uint32_t device_type, uint32_t *data)

sys/dev/pci/ixgbe_x550.c

1306

status = ixgbe_host_interface_command(hw, (uint32_t *)&hic.cmd,

sys/dev/pci/ixgbe_x550.c

1456

uint32_t link_ctrl;

sys/dev/pci/ixgbe_x550.c

1474

uint32_t flx_mask_st20;

sys/dev/pci/ixgbe_x550.c

1505

uint32_t lval, sval, flx_val;

sys/dev/pci/ixgbe_x550.c

1574

uint32_t lval, sval, flx_val;

sys/dev/pci/ixgbe_x550.c

1780

uint32_t status;

sys/dev/pci/ixgbe_x550.c

1867

uint32_t status;

sys/dev/pci/ixgbe_x550.c

1966

uint32_t reg_val;

sys/dev/pci/ixgbe_x550.c

2019

uint32_t store[FW_PHY_ACT_DATA_COUNT] = { 0 };

sys/dev/pci/ixgbe_x550.c

2043

uint32_t store[FW_PHY_ACT_DATA_COUNT] = { 0 };

sys/dev/pci/ixgbe_x550.c

2211

uint32_t hlreg0;

sys/dev/pci/ixgbe_x550.c

2249

uint32_t ctrl = 0;

sys/dev/pci/ixgbe_x550.c

2250

uint32_t i;

sys/dev/pci/ixgbe_x550.c

2252

uint32_t swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_x550.c

2380

uint32_t status;

sys/dev/pci/ixgbe_x550.c

2489

uint32_t reg_val;

sys/dev/pci/ixgbe_x550.c

2541

uint32_t reg_slice, reg_phy_int, slice_offset;

sys/dev/pci/ixgbe_x550.c

255

uint32_t retry;

sys/dev/pci/ixgbe_x550.c

2639

uint32_t reg_val;

sys/dev/pci/ixgbe_x550.c

2710

uint32_t reg_val;

sys/dev/pci/ixgbe_x550.c

2767

uint32_t ret;

sys/dev/pci/ixgbe_x550.c

2806

uint32_t status;

sys/dev/pci/ixgbe_x550.c

2868

uint32_t reg_val;

sys/dev/pci/ixgbe_x550.c

2937

const uint32_t mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;

sys/dev/pci/ixgbe_x550.c

2958

status = ixgbe_hic_unlocked(hw, (uint32_t *)&buffer, sizeof(buffer),

sys/dev/pci/ixgbe_x550.c

2982

const uint32_t mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;

sys/dev/pci/ixgbe_x550.c

2984

uint32_t current_word = 0;

sys/dev/pci/ixgbe_x550.c

2987

uint32_t i;

sys/dev/pci/ixgbe_x550.c

3015

status = ixgbe_hic_unlocked(hw, (uint32_t *)&buffer, sizeof(buffer),

sys/dev/pci/ixgbe_x550.c

3024

uint32_t reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +

sys/dev/pci/ixgbe_x550.c

3026

uint32_t value = IXGBE_READ_REG(hw, reg);

sys/dev/pci/ixgbe_x550.c

3071

status = ixgbe_host_interface_command(hw, (uint32_t *)&buffer,

sys/dev/pci/ixgbe_x550.c

3118

uint32_t buffer_size)

sys/dev/pci/ixgbe_x550.c

3154

if (buffer && ((uint32_t)start + (uint32_t)length > buffer_size))

sys/dev/pci/ixgbe_x550.c

3186

uint32_t buffer_size)

sys/dev/pci/ixgbe_x550.c

328

uint32_t swfw_mask = hw->phy.phy_semaphore_mask;

sys/dev/pci/ixgbe_x550.c

3384

status = ixgbe_host_interface_command(hw, (uint32_t *)&buffer,

sys/dev/pci/ixgbe_x550.c

3491

uint32_t rxctrl, pfdtxgswc;

sys/dev/pci/ixgbe_x550.c

3513

status = ixgbe_host_interface_command(hw, (uint32_t *)&fw_cmd,

sys/dev/pci/ixgbe_x550.c

3541

uint32_t save_autoneg;

sys/dev/pci/ixgbe_x550.c

3682

uint32_t pause, asm_dir, reg_val;

sys/dev/pci/ixgbe_x550.c

3771

uint32_t link_s1, lp_an_page_low, an_cntl_1;

sys/dev/pci/ixgbe_x550.c

3861

uint32_t info[FW_PHY_ACT_DATA_COUNT] = { 0 };

sys/dev/pci/ixgbe_x550.c

3916

uint32_t an_cntl = 0;

sys/dev/pci/ixgbe_x550.c

4002

uint32_t esdp;

sys/dev/pci/ixgbe_x550.c

4022

int32_t ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe_x550.c

404

uint32_t esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);

sys/dev/pci/ixgbe_x550.c

4045

void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe_x550.c

4062

int32_t ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe_x550.c

4064

uint32_t hmask = mask & ~IXGBE_GSSR_TOKEN_SM;

sys/dev/pci/ixgbe_x550.c

41

extern int32_t ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, uint32_t mask);

sys/dev/pci/ixgbe_x550.c

4112

void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, uint32_t mask)

sys/dev/pci/ixgbe_x550.c

4114

uint32_t hmask = mask & ~IXGBE_GSSR_TOKEN_SM;

sys/dev/pci/ixgbe_x550.c

4136

int32_t ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_x550.c

4137

uint32_t device_type, uint16_t *phy_data)

sys/dev/pci/ixgbe_x550.c

4140

uint32_t mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;

sys/dev/pci/ixgbe_x550.c

4164

int32_t ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_x550.c

4165

uint32_t device_type, uint16_t phy_data)

sys/dev/pci/ixgbe_x550.c

4168

uint32_t mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;

sys/dev/pci/ixgbe_x550.c

4197

uint32_t status;

sys/dev/pci/ixgbe_x550.c

42

extern void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, uint32_t mask);

sys/dev/pci/ixgbe_x550.c

4263

uint32_t status;

sys/dev/pci/ixgbe_x550.c

4319

int32_t ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, uint32_t led_idx)

sys/dev/pci/ixgbe_x550.c

4347

int32_t ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, uint32_t led_idx)

sys/dev/pci/ixgbe_x550.c

44

int32_t ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, uint32_t mask);

sys/dev/pci/ixgbe_x550.c

45

void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, uint32_t mask);

sys/dev/pci/ixgbe_x550.c

477

uint32_t (*data)[FW_PHY_ACT_DATA_COUNT])

sys/dev/pci/ixgbe_x550.c

497

rc = ixgbe_host_interface_command(hw, (uint32_t *)&hic.cmd,

sys/dev/pci/ixgbe_x550.c

536

uint32_t info[FW_PHY_ACT_DATA_COUNT] = { 0 };

sys/dev/pci/ixgbe_x550.c

591

uint32_t setup[FW_PHY_ACT_DATA_COUNT] = { 0 };

sys/dev/pci/ixgbe_x550.c

597

int32_t ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_x550.c

598

uint32_t device_type, uint16_t *phy_data)

sys/dev/pci/ixgbe_x550.c

603

int32_t ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_x550.c

604

uint32_t device_type, uint16_t phy_data)

sys/dev/pci/ixgbe_x550.c

61

uint32_t buffer_size);

sys/dev/pci/ixgbe_x550.c

699

uint32_t setup[FW_PHY_ACT_DATA_COUNT] = { 0 };

sys/dev/pci/ixgbe_x550.c

76

int32_t ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_x550.c

77

uint32_t device_type, uint32_t data);

sys/dev/pci/ixgbe_x550.c

78

int32_t ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_x550.c

79

uint32_t device_type, uint32_t *data);

sys/dev/pci/ixgbe_x550.c

82

int32_t ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_x550.c

83

uint32_t device_type, uint32_t data);

sys/dev/pci/ixgbe_x550.c

84

int32_t ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, uint32_t reg_addr,

sys/dev/pci/ixgbe_x550.c

85

uint32_t device_type, uint32_t *data);

sys/dev/pci/ixgbe_x550.c

883

uint32_t reg;

sys/dev/pci/ixgbe_x550.c

925

uint32_t tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;

sys/dev/pci/ixgbe_x550.c

980

uint32_t reg;

sys/dev/pci/ksmn.c

171

uint32_t m = ci->ci_model;

sys/dev/pci/ksmn.c

198

uint32_t

sys/dev/pci/ksmn.c

199

ksmn_read_reg(struct ksmn_softc *sc, uint32_t addr)

sys/dev/pci/ksmn.c

201

uint32_t reg;

sys/dev/pci/ksmn.c

215

uint32_t reg;

sys/dev/pci/ksmn.c

91

uint32_t ksmn_read_reg(struct ksmn_softc *, uint32_t);

sys/dev/pci/lpssreg.h

48

#define LPSS_REG_NUM (LPSS_REG_SIZE / sizeof(uint32_t))

sys/dev/pci/mfii.c

1129

io->sgl_offset0 = (uint32_t *)sge - (uint32_t *)io;

sys/dev/pci/mfii.c

1182

struct mfii_dmamem *mdm, uint32_t seq)

sys/dev/pci/mfii.c

1234

uint32_t code;

sys/dev/pci/mfii.c

153

uint32_t mlm_total_size;

sys/dev/pci/mfii.c

154

uint32_t mlm_reserved1[5];

sys/dev/pci/mfii.c

155

uint32_t mlm_num_lds;

sys/dev/pci/mfii.c

156

uint32_t mlm_reserved2;

sys/dev/pci/mfii.c

173

uint32_t flags;

sys/dev/pci/mfii.c

1808

mfii_mgmt(struct mfii_softc *sc, uint32_t opc, const union mfi_mbox *mbox,

sys/dev/pci/mfii.c

1826

mfii_do_mgmt(struct mfii_softc *sc, struct mfii_ccb *ccb, uint32_t opc,

sys/dev/pci/mfii.c

2699

uint16_t smid, uint8_t type, uint32_t flags)

sys/dev/pci/mfii.c

3274

uint32_t opc, flags = 0;

sys/dev/pci/mfii.c

3322

uint32_t cmd;

sys/dev/pci/mfii.c

345

uint32_t mfii_debug = 0

sys/dev/pci/mfii.c

3571

uint32_t opc;

sys/dev/pci/mfii.c

3575

uint32_t time, exec_freq;

sys/dev/pci/mfii.c

3708

uint32_t size;

sys/dev/pci/mfii.c

432

int mfii_mgmt(struct mfii_softc *, uint32_t,

sys/dev/pci/mfii.c

435

uint32_t, const union mfi_mbox *, void *, size_t,

sys/dev/pci/mfii.c

452

uint16_t, uint16_t, uint8_t, uint32_t);

sys/dev/pci/mfii.c

458

struct mfii_dmamem *, uint32_t);

sys/dev/pci/mmuagp.c

110

uint32_t apbase;

sys/dev/pci/mmuagp.c

317

attbase = (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK;

sys/dev/pci/mmuagp.c

355

uint32_t i;

sys/dev/pci/mmuagp.c

370

uint32_t i;

sys/dev/pci/mmuagp.c

427

uint32_t apbase;

sys/dev/pci/mpii.c

908

uint32_t address;

sys/dev/pci/mpii.c

962

address = MPII_PGAD_SAS_DEVICE_FORM_HANDLE | (uint32_t)dev->dev_handle;

sys/dev/pci/nhi.c

110

uint32_t nd_addr_lo;

sys/dev/pci/nhi.c

111

uint32_t nd_addr_hi;

sys/dev/pci/nhi.c

112

uint32_t nd_flags;

sys/dev/pci/nhi.c

113

uint32_t nd_reserved;

sys/dev/pci/nhi.c

131

#define NHI_TX_SIZE (256 * sizeof(uint32_t))

sys/dev/pci/nhi.c

145

uint32_t *sc_tx_buf[NHI_TX_NDESC];

sys/dev/pci/nhi.c

152

uint32_t sc_pdf;

sys/dev/pci/nhi.c

153

uint32_t sc_data;

sys/dev/pci/nhi.c

156

int nhi_conf_read(struct nhi_softc *, uint32_t, uint32_t, uint32_t,

sys/dev/pci/nhi.c

157

uint32_t, uint32_t *);

sys/dev/pci/nhi.c

158

int nhi_conf_write(struct nhi_softc *, uint32_t, uint32_t, uint32_t,

sys/dev/pci/nhi.c

159

uint32_t, uint32_t);

sys/dev/pci/nhi.c

206

uint32_t caps;

sys/dev/pci/nhi.c

245

rxb = nhi_dmamem_alloc(sc->sc_dmat, 4096, sizeof(uint32_t));

sys/dev/pci/nhi.c

302

uint32_t data;

sys/dev/pci/nhi.c

355

uint32_t rst;

sys/dev/pci/nhi.c

408

nhi_tx_enqueue(struct nhi_softc *sc, uint32_t pdf, void *buf, size_t len)

sys/dev/pci/nhi.c

412

uint32_t *txbuf;

sys/dev/pci/nhi.c

416

for (i = 0; i < len / sizeof(uint32_t); i++)

sys/dev/pci/nhi.c

417

txbuf[i] = htobe32(((uint32_t *)buf)[i]);

sys/dev/pci/nhi.c

422

txbuf, len + sizeof(uint32_t), NULL, BUS_DMA_WAITOK);

sys/dev/pci/nhi.c

459

nhi_conf_read(struct nhi_softc *sc, uint32_t addr, uint32_t adapter,

sys/dev/pci/nhi.c

460

uint32_t space, uint32_t seqno, uint32_t *data)

sys/dev/pci/nhi.c

462

uint32_t cmd[3];

sys/dev/pci/nhi.c

504

nhi_conf_write(struct nhi_softc *sc, uint32_t addr, uint32_t adapter,

sys/dev/pci/nhi.c

505

uint32_t space, uint32_t seqno, uint32_t data)

sys/dev/pci/nhi.c

507

uint32_t cmd[4];

sys/dev/pci/nhi.c

552

uint32_t prod, stat;

sys/dev/pci/nhi.c

563

uint32_t cmd[3];

sys/dev/pci/nhi.c

564

uint32_t adapter;

sys/dev/pci/nhi.c

565

uint32_t upg;

sys/dev/pci/nhi.c

566

uint32_t *resp;

sys/dev/pci/nhi.c

567

uint32_t pdf;

sys/dev/pci/pci.c

1106

uint32_t reg;

sys/dev/pci/pci.c

57

uint32_t mv_ma;

sys/dev/pci/pci.c

58

uint32_t mv_mau32;

sys/dev/pci/pci.c

59

uint32_t mv_md;

sys/dev/pci/pci.c

60

uint32_t mv_vc;

sys/dev/pci/pciide.c

4432

uint32_t scontrol, sstatus;

sys/dev/pci/pciide.c

7680

uint32_t scontrol, sstatus;

sys/dev/pci/pciide_rdc_reg.h

70

const uint32_t rdcide_udmaclk[] =

sys/dev/pci/pciide_sii3112_reg.h

340

static uint32_t

sys/dev/pci/pciide_sii3112_reg.h

343

uint32_t rv;

sys/dev/pci/pciide_sii3112_reg.h

354

static uint32_t

sys/dev/pci/pciide_sii3112_reg.h

369

ba5_write_4_ind(struct pciide_softc *sc, pcireg_t reg, uint32_t val)

sys/dev/pci/pciide_sii3112_reg.h

380

ba5_write_4(struct pciide_softc *sc, bus_size_t reg, uint32_t val)

sys/dev/pci/pcscp.c

305

sizeof(uint32_t) * MDL_SIZE);

sys/dev/pci/ppb.c

544

uint32_t bus_range[2];

sys/dev/pci/psp_pci.c

43

uint32_t capabilities;

sys/dev/pci/sdhc_pci.c

59

uint32_t sc_capmask;

sys/dev/pci/sdhc_pci.c

60

uint32_t sc_capmask2;

sys/dev/pci/sti_pci.c

173

uint32_t signature;

sys/dev/pci/sti_pci.c

382

uint32_t tmp32;

sys/dev/pci/tga.c

101

int tga_eraserows(void *, int, int, uint32_t);

sys/dev/pci/tga.c

102

int tga_erasecols(void *, int, int, int, uint32_t);

sys/dev/pci/tga.c

103

int tga_putchar(void *c, int row, int col, u_int uc, uint32_t attr);

sys/dev/pci/tga.c

1202

*(uint32_t *)(dst->ri_bits + dstb + y + x) =

sys/dev/pci/tga.c

1203

*(uint32_t *)(dst->ri_bits + srcb + y + x);

sys/dev/pci/tga.c

1251

*(uint32_t *)(dst->ri_bits + dstb + y + x) =

sys/dev/pci/tga.c

1252

*(uint32_t *)(dst->ri_bits + srcb + y + x);

sys/dev/pci/tga.c

1261

tga_putchar(void *c, int row, int col, u_int uc, uint32_t attr)

sys/dev/pci/tga.c

1325

tga_eraserows(void *c, int row, int num, uint32_t attr)

sys/dev/pci/tga.c

1379

tga_erasecols(void *c, int row, int col, int num, uint32_t attr)

sys/dev/pci/tga.c

711

int *curxp, int *curyp, uint32_t *attrp)

sys/dev/pci/tga.c

714

uint32_t defattr;

sys/dev/pci/tga.c

809

uint32_t defattr;

sys/dev/pci/tga.c

91

void **, int *, int *, uint32_t *);

sys/dev/pci/virtio_pci.c

1012

virtio_pci_set_msix_queue_vector(struct virtio_pci_softc *sc, uint32_t idx, uint16_t vector)

sys/dev/pci/virtio_pci.c

204

off + sizeof(uint32_t));

sys/dev/pci/virtio_pci.c

237

(off) + sizeof(uint32_t), (uint64_t)(val) >> 32); \

sys/dev/pci/virtio_pci.c

68

uint32_t virtio_pci_read_device_config_4(struct virtio_softc *, int);

sys/dev/pci/virtio_pci.c

72

void virtio_pci_write_device_config_4(struct virtio_softc *, int, uint32_t);

sys/dev/pci/virtio_pci.c

82

void virtio_pci_set_msix_queue_vector(struct virtio_pci_softc *, uint32_t, uint16_t);

sys/dev/pci/virtio_pci.c

921

uint32_t

sys/dev/pci/virtio_pci.c

935

index + sizeof(uint32_t));

sys/dev/pci/virtio_pci.c

959

int index, uint32_t value)

sys/dev/pci/virtio_pci.c

973

index + sizeof(uint32_t), value >> 32);

sys/dev/pci/virtio_pcireg.h

49

uint32_t offset; /* Offset within bar. */

sys/dev/pci/virtio_pcireg.h

50

uint32_t length; /* Length of the structure, in bytes. */

sys/dev/pci/virtio_pcireg.h

66

uint32_t notify_off_multiplier; /* Multiplier for queue_notify_off. */

sys/dev/pci/virtio_pcireg.h

76

uint32_t device_feature_select; /* read-write */

sys/dev/pci/virtio_pcireg.h

77

uint32_t device_feature; /* read-only for driver */

sys/dev/pci/virtio_pcireg.h

78

uint32_t driver_feature_select; /* read-write */

sys/dev/pci/virtio_pcireg.h

79

uint32_t driver_feature; /* read-write */

sys/dev/pci/xhci_pci.c

268

uint32_t cparams, xecp, eec;

sys/dev/pcmcia/cfxga.c

110

int *, int *, uint32_t *);

sys/dev/pcmcia/cfxga.c

1138

cfxga_erasecols(void *cookie, int row, int col, int num, uint32_t attr)

sys/dev/pcmcia/cfxga.c

1163

cfxga_eraserows(void *cookie, int row, int num, uint32_t attr)

sys/dev/pcmcia/cfxga.c

1192

cfxga_putchar(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/pcmcia/cfxga.c

145

int cfxga_erasecols(void *, int, int, int, uint32_t);

sys/dev/pcmcia/cfxga.c

146

int cfxga_eraserows(void *, int, int, uint32_t);

sys/dev/pcmcia/cfxga.c

147

int cfxga_putchar(void *, int, int, u_int, uint32_t);

sys/dev/pcmcia/cfxga.c

152

int cfxga_expand_char(struct cfxga_screen *, u_int, int, int, uint32_t);

sys/dev/pcmcia/cfxga.c

431

int *curxp, int *curyp, uint32_t *attrp)

sys/dev/pcmcia/cfxga.c

867

uint32_t attr)

sys/dev/pcmcia/if_malovar.h

200

uint32_t scanintvl;

sys/dev/pcmcia/if_malovar.h

201

uint32_t storecond;

sys/dev/pcmcia/if_malovar.h

202

uint32_t reportcond;

sys/dev/pcmcia/if_malovar.h

312

uint32_t pkgoffset;

sys/dev/pcmcia/if_malovar.h

313

uint32_t reserved1;

sys/dev/pcmcia/if_malovar.h

320

uint32_t status;

sys/dev/pcmcia/if_malovar.h

321

uint32_t control;

sys/dev/pcmcia/if_malovar.h

322

uint32_t pkgoffset;

sys/dev/pcmcia/if_malovar.h

65

uint32_t fw_version;

sys/dev/pcmcia/if_malovar.h

66

uint32_t wcbbase;

sys/dev/pcmcia/if_malovar.h

67

uint32_t rxpdrdptr;

sys/dev/pcmcia/if_malovar.h

68

uint32_t rxpdwrptr;

sys/dev/pcmcia/if_malovar.h

69

uint32_t fw_capinfo;

sys/dev/pv/hvs.c

122

uint32_t srb_datalen;

sys/dev/pv/hvs.c

157

uint32_t cmd_srbflags;

sys/dev/pv/hvs.c

158

uint32_t cmd_timeout;

sys/dev/pv/hvs.c

159

uint32_t cmd_qsortkey;

sys/dev/pv/hvs.c

521

uint32_t rlen;

sys/dev/pv/hvs.c

70

uint32_t hdr_op;

sys/dev/pv/hvs.c

701

const uint32_t protos[] = {

sys/dev/pv/hvs.c

71

uint32_t hdr_flags;

sys/dev/pv/hvs.c

72

uint32_t hdr_status;

sys/dev/pv/hvs.c

92

uint32_t chp_chflags;

sys/dev/pv/hvs.c

93

uint32_t chp_maxfer;

sys/dev/pv/hyperv.c

1109

hv_channel_lookup(struct hv_softc *sc, uint32_t relid)

sys/dev/pv/hyperv.c

1121

hv_channel_ring_create(struct hv_channel *ch, uint32_t buflen)

sys/dev/pv/hyperv.c

1293

hv_ring_put(struct hv_ring_data *wrd, uint8_t *data, uint32_t datalen)

sys/dev/pv/hyperv.c

1305

hv_ring_get(struct hv_ring_data *rrd, uint8_t *data, uint32_t datalen,

sys/dev/pv/hyperv.c

1320

hv_ring_avail(struct hv_ring_data *rd, uint32_t *towrite, uint32_t *toread)

sys/dev/pv/hyperv.c

1322

uint32_t ridx = rd->rd_ring->br_rindex;

sys/dev/pv/hyperv.c

1323

uint32_t widx = rd->rd_ring->br_windex;

sys/dev/pv/hyperv.c

1324

uint32_t r, w;

sys/dev/pv/hyperv.c

1342

uint32_t avail, oprod, datalen = sizeof(indices);

sys/dev/pv/hyperv.c

1379

hv_channel_send(struct hv_channel *ch, void *data, uint32_t datalen,

sys/dev/pv/hyperv.c

1380

uint64_t rid, int type, uint32_t flags)

sys/dev/pv/hyperv.c

1385

uint32_t pktlen, pktlen_aligned;

sys/dev/pv/hyperv.c

1418

uint32_t nsge, void *data, uint32_t datalen, uint64_t rid)

sys/dev/pv/hyperv.c

1423

uint32_t buflen, pktlen, pktlen_aligned;

sys/dev/pv/hyperv.c

1462

uint32_t nprp, void *data, uint32_t datalen, uint64_t rid)

sys/dev/pv/hyperv.c

1467

uint32_t buflen, pktlen, pktlen_aligned;

sys/dev/pv/hyperv.c

1505

hv_ring_peek(struct hv_ring_data *rrd, void *data, uint32_t datalen)

sys/dev/pv/hyperv.c

1507

uint32_t avail;

sys/dev/pv/hyperv.c

1520

hv_ring_read(struct hv_ring_data *rrd, void *data, uint32_t datalen,

sys/dev/pv/hyperv.c

1521

uint32_t offset)

sys/dev/pv/hyperv.c

1524

uint32_t avail;

sys/dev/pv/hyperv.c

1550

hv_channel_recv(struct hv_channel *ch, void *data, uint32_t datalen,

sys/dev/pv/hyperv.c

1551

uint32_t *rlen, uint64_t *rid, int raw)

sys/dev/pv/hyperv.c

1554

uint32_t offset, pktlen;

sys/dev/pv/hyperv.c

1610

uint32_t avail;

sys/dev/pv/hyperv.c

1621

uint32_t avail;

sys/dev/pv/hyperv.c

1637

hv_handle_alloc(struct hv_channel *ch, void *buffer, uint32_t buflen,

sys/dev/pv/hyperv.c

1638

uint32_t *handle)

sys/dev/pv/hyperv.c

1767

hv_handle_free(struct hv_channel *ch, uint32_t handle)

sys/dev/pv/hyperv.c

408

uint32_t control_hi = control >> 32;

sys/dev/pv/hyperv.c

409

uint32_t control_lo = control & 0xfffffffff;

sys/dev/pv/hyperv.c

410

uint32_t status_hi = 1;

sys/dev/pv/hyperv.c

411

uint32_t status_lo = 1;

sys/dev/pv/hyperv.c

820

const uint32_t versions[] = {

sys/dev/pv/hyperv.c

97

hv_channel_lookup(struct hv_softc *, uint32_t);

sys/dev/pv/hyperv.c

98

int hv_channel_ring_create(struct hv_channel *, uint32_t);

sys/dev/pv/hypervic.c

1050

uint32_t fwver, msgver, rlen;

sys/dev/pv/hypervic.c

225

hv_ic_negotiate(struct vmbus_icmsg_hdr *hdr, uint32_t *rlen, uint32_t fwver,

sys/dev/pv/hypervic.c

226

uint32_t msgver)

sys/dev/pv/hypervic.c

266

hdr->ic_dsize = sizeof(*msg) + 2 * sizeof(uint32_t) -

sys/dev/pv/hypervic.c

268

if (*rlen < sizeof(*msg) + 2 * sizeof(uint32_t))

sys/dev/pv/hypervic.c

269

*rlen = sizeof(*msg) + 2 * sizeof(uint32_t);

sys/dev/pv/hypervic.c

297

uint32_t rlen;

sys/dev/pv/hypervic.c

366

uint32_t rlen;

sys/dev/pv/hypervic.c

445

uint32_t rlen;

sys/dev/pv/hypervic.c

544

uint32_t vallen, uint32_t valtype)

sys/dev/pv/hypervic.c

585

uint32_t vallen, uint32_t valtype)

sys/dev/pv/hypervic.c

615

kvp_pool_import(struct kvp_pool *kvpl, const char *key, uint32_t keylen,

sys/dev/pv/hypervic.c

616

const char *val, uint32_t vallen, uint32_t valtype)

sys/dev/pv/hypervic.c

654

kvp_pool_export(struct kvp_pool *kvpl, uint32_t index, char *key,

sys/dev/pv/hypervic.c

655

uint32_t *keylen, char *val, uint32_t *vallen, uint32_t *valtype)

sys/dev/pv/hypervic.c

682

kvp_pool_remove(struct kvp_pool *kvpl, const char *key, uint32_t keylen)

sys/dev/pv/hypervic.c

708

uint32_t vallen)

sys/dev/pv/hypervic.c

732

*(uint32_t *)kpe->kpe_val);

sys/dev/pv/hypervic.c

74

uint32_t kpe_valtype;

sys/dev/pv/hypervicreg.h

152

uint32_t kvu_err;

sys/dev/pv/hypervicreg.h

160

uint32_t kvm_valtype;

sys/dev/pv/hypervicreg.h

161

uint32_t kvm_keylen;

sys/dev/pv/hypervicreg.h

162

uint32_t kvm_vallen;

sys/dev/pv/hypervicreg.h

168

uint32_t kvm_index;

sys/dev/pv/hypervicreg.h

169

uint32_t kvm_valtype;

sys/dev/pv/hypervicreg.h

170

uint32_t kvm_keylen;

sys/dev/pv/hypervicreg.h

171

uint32_t kvm_vallen;

sys/dev/pv/hypervicreg.h

177

uint32_t kvm_keylen;

sys/dev/pv/hypervicreg.h

48

#define VMBUS_IC_VERSION(major, minor) ((major) | (((uint32_t)(minor)) << 16))

sys/dev/pv/hypervicreg.h

53

uint32_t ph_flags;

sys/dev/pv/hypervicreg.h

54

uint32_t ph_msgsz;

sys/dev/pv/hypervicreg.h

59

uint32_t ic_fwver; /* framework version */

sys/dev/pv/hypervicreg.h

61

uint32_t ic_msgver; /* message version */

sys/dev/pv/hypervicreg.h

63

uint32_t ic_status; /* VMBUS_ICMSG_STATUS_ */

sys/dev/pv/hypervicreg.h

74

uint32_t ic_rsvd;

sys/dev/pv/hypervicreg.h

83

uint32_t ic_ver[0];

sys/dev/pv/hypervicreg.h

90

uint32_t ic_rsvd[8];

sys/dev/pv/hypervicreg.h

96

uint32_t ic_code;

sys/dev/pv/hypervicreg.h

97

uint32_t ic_timeo;

sys/dev/pv/hypervicreg.h

98

uint32_t ic_haltflags;

sys/dev/pv/hypervreg.h

155

uint32_t mp_connid;

sys/dev/pv/hypervreg.h

199

uint32_t hc_connid;

sys/dev/pv/hypervreg.h

200

uint32_t hc_rsvd;

sys/dev/pv/hypervreg.h

201

uint32_t hc_msgtype; /* VMBUS_MSGTYPE_ */

sys/dev/pv/hypervreg.h

202

uint32_t hc_dsize;

sys/dev/pv/hypervreg.h

226

#define VMBUS_VERSION_MAJOR(ver) (((uint32_t)(ver)) >> 16)

sys/dev/pv/hypervreg.h

227

#define VMBUS_VERSION_MINOR(ver) (((uint32_t)(ver)) & 0xffff)

sys/dev/pv/hypervreg.h

233

uint32_t gpa_len;

sys/dev/pv/hypervreg.h

234

uint32_t gpa_ofs;

sys/dev/pv/hypervreg.h

240

uint32_t gpa_len;

sys/dev/pv/hypervreg.h

241

uint32_t gpa_ofs;

sys/dev/pv/hypervreg.h

281

uint32_t msg_type; /* VMBUS_MSGTYPE_ */

sys/dev/pv/hypervreg.h

309

uint32_t mt_pending;

sys/dev/pv/hypervreg.h

310

uint32_t mt_armed;

sys/dev/pv/hypervreg.h

317

uint32_t mnf_state;

sys/dev/pv/hypervreg.h

318

uint32_t mnf_rsvd1;

sys/dev/pv/hypervreg.h

341

volatile uint32_t br_windex;

sys/dev/pv/hypervreg.h

342

volatile uint32_t br_rindex;

sys/dev/pv/hypervreg.h

356

volatile uint32_t br_imask;

sys/dev/pv/hypervreg.h

386

uint32_t cp_rsvd;

sys/dev/pv/hypervreg.h

387

uint32_t cp_gpa_cnt;

sys/dev/pv/hypervreg.h

393

uint32_t cp_rsvd;

sys/dev/pv/hypervreg.h

394

uint32_t cp_range_cnt;

sys/dev/pv/hypervreg.h

424

uint32_t chm_type; /* VMBUS_CHANMSG_* */

sys/dev/pv/hypervreg.h

425

uint32_t chm_rsvd;

sys/dev/pv/hypervreg.h

431

uint32_t chm_ver;

sys/dev/pv/hypervreg.h

432

uint32_t chm_rsvd;

sys/dev/pv/hypervreg.h

457

uint32_t chm_chanid;

sys/dev/pv/hypervreg.h

458

uint32_t chm_openid;

sys/dev/pv/hypervreg.h

459

uint32_t chm_gpadl;

sys/dev/pv/hypervreg.h

460

uint32_t chm_vcpuid;

sys/dev/pv/hypervreg.h

461

uint32_t chm_txbr_pgcnt;

sys/dev/pv/hypervreg.h

469

uint32_t chm_chanid;

sys/dev/pv/hypervreg.h

470

uint32_t chm_openid;

sys/dev/pv/hypervreg.h

471

uint32_t chm_status;

sys/dev/pv/hypervreg.h

477

uint32_t chm_chanid;

sys/dev/pv/hypervreg.h

478

uint32_t chm_gpadl;

sys/dev/pv/hypervreg.h

489

uint32_t chm_msgno;

sys/dev/pv/hypervreg.h

490

uint32_t chm_gpadl;

sys/dev/pv/hypervreg.h

499

uint32_t chm_chanid;

sys/dev/pv/hypervreg.h

500

uint32_t chm_gpadl;

sys/dev/pv/hypervreg.h

501

uint32_t chm_status;

sys/dev/pv/hypervreg.h

507

uint32_t chm_chanid;

sys/dev/pv/hypervreg.h

513

uint32_t chm_chanid;

sys/dev/pv/hypervreg.h

514

uint32_t chm_gpadl;

sys/dev/pv/hypervreg.h

520

uint32_t chm_chanid;

sys/dev/pv/hypervreg.h

526

uint32_t chm_chanid;

sys/dev/pv/hypervreg.h

535

uint32_t chm_chrev;

sys/dev/pv/hypervreg.h

536

uint32_t chm_svrctx_sz;

sys/dev/pv/hypervreg.h

542

uint32_t chm_chanid;

sys/dev/pv/hypervreg.h

546

uint32_t chm_connid;

sys/dev/pv/hypervvar.h

119

uint32_t sc_features;

sys/dev/pv/hypervvar.h

121

uint32_t sc_flags;

sys/dev/pv/hypervvar.h

129

uint32_t sc_vcpus[1]; /* XXX: per-cpu */

sys/dev/pv/hypervvar.h

154

volatile uint32_t sc_handle;

sys/dev/pv/hypervvar.h

207

int hv_handle_alloc(struct hv_channel *, void *, uint32_t, uint32_t *);

sys/dev/pv/hypervvar.h

208

void hv_handle_free(struct hv_channel *, uint32_t);

sys/dev/pv/hypervvar.h

215

int hv_channel_send(struct hv_channel *, void *, uint32_t, uint64_t,

sys/dev/pv/hypervvar.h

216

int, uint32_t);

sys/dev/pv/hypervvar.h

218

uint32_t, void *, uint32_t, uint64_t);

sys/dev/pv/hypervvar.h

220

uint32_t, void *, uint32_t, uint64_t);

sys/dev/pv/hypervvar.h

221

int hv_channel_recv(struct hv_channel *, void *, uint32_t, uint32_t *,

sys/dev/pv/hypervvar.h

50

uint32_t rd_size;

sys/dev/pv/hypervvar.h

52

uint32_t rd_prod;

sys/dev/pv/hypervvar.h

53

uint32_t rd_cons;

sys/dev/pv/hypervvar.h

54

uint32_t rd_dsize;

sys/dev/pv/hypervvar.h

65

uint32_t ch_id;

sys/dev/pv/hypervvar.h

72

uint32_t ch_ring_gpadl;

sys/dev/pv/hypervvar.h

78

uint32_t ch_vcpu;

sys/dev/pv/hypervvar.h

86

uint32_t ch_flags;

sys/dev/pv/if_hvn.c

111

uint32_t txd_id;

sys/dev/pv/if_hvn.c

1144

hvn_complete_cmd(struct hvn_softc *sc, uint32_t id)

sys/dev/pv/if_hvn.c

133

uint32_t sc_nvstid;

sys/dev/pv/if_hvn.c

140

uint32_t sc_rndisrid;

sys/dev/pv/if_hvn.c

1429

uint32_t off, len, type;

sys/dev/pv/if_hvn.c

1478

hvn_devget(struct hvn_softc *sc, caddr_t buf, uint32_t len)

sys/dev/pv/if_hvn.c

1500

hvn_rxeof(struct hvn_softc *sc, caddr_t buf, uint32_t len, struct mbuf_list *ml)

sys/dev/pv/if_hvn.c

1505

uint32_t csum, vlan;

sys/dev/pv/if_hvn.c

153

uint32_t sc_rx_hndl;

sys/dev/pv/if_hvn.c

156

uint32_t sc_tx_next;

sys/dev/pv/if_hvn.c

157

uint32_t sc_tx_avail;

sys/dev/pv/if_hvn.c

1580

hvn_rndis_complete(struct hvn_softc *sc, caddr_t buf, uint32_t len)

sys/dev/pv/if_hvn.c

1583

uint32_t id;

sys/dev/pv/if_hvn.c

1624

hvn_rndis_status(struct hvn_softc *sc, caddr_t buf, uint32_t len)

sys/dev/pv/if_hvn.c

1626

uint32_t status;

sys/dev/pv/if_hvn.c

1650

hvn_rndis_query(struct hvn_softc *sc, uint32_t oid, void *res, size_t *length)

sys/dev/pv/if_hvn.c

1705

hvn_rndis_set(struct hvn_softc *sc, uint32_t oid, void *data, size_t length)

sys/dev/pv/if_hvn.c

1756

uint32_t filter = 0;

sys/dev/pv/if_hvn.c

197

void hvn_rxeof(struct hvn_softc *, caddr_t, uint32_t, struct mbuf_list *);

sys/dev/pv/if_hvn.c

198

void hvn_rndis_complete(struct hvn_softc *, caddr_t, uint32_t);

sys/dev/pv/if_hvn.c

200

void hvn_rndis_status(struct hvn_softc *, caddr_t, uint32_t);

sys/dev/pv/if_hvn.c

201

int hvn_rndis_query(struct hvn_softc *, uint32_t, void *, size_t *);

sys/dev/pv/if_hvn.c

202

int hvn_rndis_set(struct hvn_softc *, uint32_t, void *, size_t);

sys/dev/pv/if_hvn.c

403

uint32_t filter = 0;

sys/dev/pv/if_hvn.c

501

size_t datalen, uint32_t type)

sys/dev/pv/if_hvn.c

564

uint32_t vlan;

sys/dev/pv/if_hvn.c

577

uint32_t csum = NDIS_TXCSUM_INFO_IPV4;

sys/dev/pv/if_hvn.c

631

uint32_t id = tid >> 32;

sys/dev/pv/if_hvn.c

78

uint32_t rc_id;

sys/dev/pv/if_hvn.c

86

uint32_t rc_cmplen;

sys/dev/pv/if_hvn.c

871

uint32_t state;

sys/dev/pv/if_hvn.c

883

const uint32_t protos[] = {

sys/dev/pv/if_hvn.c

891

uint32_t ndisver, ringsize;

sys/dev/pv/if_hvn.c

977

uint32_t rlen;

sys/dev/pv/if_hvnreg.h

100

uint32_t nvs_rsvd;

sys/dev/pv/if_hvnreg.h

110

uint32_t nvs_type; /* HVN_NVS_TYPE_NDIS_INIT */

sys/dev/pv/if_hvnreg.h

111

uint32_t nvs_ndis_major; /* NDIS_VERSION_MAJOR_ */

sys/dev/pv/if_hvnreg.h

112

uint32_t nvs_ndis_minor; /* NDIS_VERSION_MINOR_ */

sys/dev/pv/if_hvnreg.h

117

uint32_t nvs_type; /* HVN_NVS_TYPE_RXBUF_CONN */

sys/dev/pv/if_hvnreg.h

118

uint32_t nvs_gpadl; /* RXBUF vmbus GPADL */

sys/dev/pv/if_hvnreg.h

124

uint32_t nvs_start;

sys/dev/pv/if_hvnreg.h

125

uint32_t nvs_slotsz;

sys/dev/pv/if_hvnreg.h

126

uint32_t nvs_slotcnt;

sys/dev/pv/if_hvnreg.h

127

uint32_t nvs_end;

sys/dev/pv/if_hvnreg.h

131

uint32_t nvs_type; /* HVN_NVS_TYPE_RXBUF_CONNRESP */

sys/dev/pv/if_hvnreg.h

132

uint32_t nvs_status; /* HVN_NVS_STATUS_ */

sys/dev/pv/if_hvnreg.h

133

uint32_t nvs_nsect; /* # of elem in nvs_sect */

sys/dev/pv/if_hvnreg.h

139

uint32_t nvs_type; /* HVN_NVS_TYPE_RXBUF_DISCONN */

sys/dev/pv/if_hvnreg.h

145

uint32_t nvs_type; /* HVN_NVS_TYPE_CHIM_CONN */

sys/dev/pv/if_hvnreg.h

146

uint32_t nvs_gpadl; /* chimney buf vmbus GPADL */

sys/dev/pv/if_hvnreg.h

152

uint32_t nvs_type; /* HVN_NVS_TYPE_CHIM_CONNRESP */

sys/dev/pv/if_hvnreg.h

153

uint32_t nvs_status; /* HVN_NVS_STATUS_ */

sys/dev/pv/if_hvnreg.h

154

uint32_t nvs_sectsz; /* section size */

sys/dev/pv/if_hvnreg.h

159

uint32_t nvs_type; /* HVN_NVS_TYPE_CHIM_DISCONN */

sys/dev/pv/if_hvnreg.h

167

uint32_t nvs_type; /* HVN_NVS_TYPE_SUBCH_REQ */

sys/dev/pv/if_hvnreg.h

168

uint32_t nvs_op; /* HVN_NVS_SUBCH_OP_ */

sys/dev/pv/if_hvnreg.h

169

uint32_t nvs_nsubch;

sys/dev/pv/if_hvnreg.h

174

uint32_t nvs_type; /* HVN_NVS_TYPE_SUBCH_RESP */

sys/dev/pv/if_hvnreg.h

175

uint32_t nvs_status; /* HVN_NVS_STATUS_ */

sys/dev/pv/if_hvnreg.h

176

uint32_t nvs_nsubch;

sys/dev/pv/if_hvnreg.h

180

uint32_t nvs_type; /* HVN_NVS_TYPE_RNDIS */

sys/dev/pv/if_hvnreg.h

181

uint32_t nvs_rndis_mtype;/* HVN_NVS_RNDIS_MTYPE_ */

sys/dev/pv/if_hvnreg.h

190

uint32_t nvs_chim_idx;

sys/dev/pv/if_hvnreg.h

191

uint32_t nvs_chim_sz;

sys/dev/pv/if_hvnreg.h

196

uint32_t nvs_type; /* HVN_NVS_TYPE_RNDIS_ACK */

sys/dev/pv/if_hvnreg.h

197

uint32_t nvs_status; /* HVN_NVS_STATUS_ */

sys/dev/pv/if_hvnreg.h

79

uint32_t nvs_type;

sys/dev/pv/if_hvnreg.h

83

uint32_t nvs_type; /* HVN_NVS_TYPE_INIT */

sys/dev/pv/if_hvnreg.h

84

uint32_t nvs_ver_min;

sys/dev/pv/if_hvnreg.h

85

uint32_t nvs_ver_max;

sys/dev/pv/if_hvnreg.h

90

uint32_t nvs_type; /* HVN_NVS_TYPE_INIT_RESP */

sys/dev/pv/if_hvnreg.h

91

uint32_t nvs_ver; /* deprecated */

sys/dev/pv/if_hvnreg.h

92

uint32_t nvs_rsvd;

sys/dev/pv/if_hvnreg.h

93

uint32_t nvs_status; /* HVN_NVS_STATUS_ */

sys/dev/pv/if_hvnreg.h

98

uint32_t nvs_type; /* HVN_NVS_TYPE_NDIS_CONF */

sys/dev/pv/if_hvnreg.h

99

uint32_t nvs_mtu;

sys/dev/pv/if_vio.c

1120

vio_cksum_update(uint32_t cksum, uint16_t paylen)

sys/dev/pv/if_vio.c

235

uint32_t nentries;

sys/dev/pv/if_xnf.c

123

volatile uint32_t txr_prod;

sys/dev/pv/if_xnf.c

124

volatile uint32_t txr_prod_event;

sys/dev/pv/if_xnf.c

125

volatile uint32_t txr_cons;

sys/dev/pv/if_xnf.c

126

volatile uint32_t txr_cons_event;

sys/dev/pv/if_xnf.c

127

uint32_t txr_reserved[12];

sys/dev/pv/if_xnf.c

132

uint32_t txb_ndesc;

sys/dev/pv/if_xnf.c

176

uint32_t sc_rx_ref; /* grant table ref */

sys/dev/pv/if_xnf.c

177

uint32_t sc_rx_cons;

sys/dev/pv/if_xnf.c

186

uint32_t sc_tx_ref; /* grant table ref */

sys/dev/pv/if_xnf.c

187

uint32_t sc_tx_cons;

sys/dev/pv/if_xnf.c

189

uint32_t sc_tx_next; /* next buffer */

sys/dev/pv/if_xnf.c

205

int xnf_encap(struct xnf_softc *, struct mbuf *, uint32_t *);

sys/dev/pv/if_xnf.c

491

uint32_t prod, oprod;

sys/dev/pv/if_xnf.c

559

xnf_encap(struct xnf_softc *sc, struct mbuf *m_head, uint32_t *prod)

sys/dev/pv/if_xnf.c

565

uint32_t oprod = *prod;

sys/dev/pv/if_xnf.c

60

uint32_t rxq_ref;

sys/dev/pv/if_xnf.c

701

uint32_t cons;

sys/dev/pv/if_xnf.c

754

uint32_t cons;

sys/dev/pv/if_xnf.c

84

volatile uint32_t rxr_prod;

sys/dev/pv/if_xnf.c

845

uint32_t cons, prod, oprod;

sys/dev/pv/if_xnf.c

85

volatile uint32_t rxr_prod_event;

sys/dev/pv/if_xnf.c

86

volatile uint32_t rxr_cons;

sys/dev/pv/if_xnf.c

87

volatile uint32_t rxr_cons_event;

sys/dev/pv/if_xnf.c

88

uint32_t rxr_reserved[12];

sys/dev/pv/if_xnf.c

98

uint32_t txq_ref;

sys/dev/pv/ndis.h

122

#define NDIS_VLAN_INFO_SIZE sizeof(uint32_t)

sys/dev/pv/ndis.h

131

#define NDIS_RXCSUM_INFO_SIZE sizeof(uint32_t)

sys/dev/pv/ndis.h

143

#define NDIS_TXCSUM_INFO_SIZE sizeof(uint32_t)

sys/dev/pv/ndis.h

69

uint32_t ndis_flags; /* 0 */

sys/dev/pv/pvbus.c

154

uint32_t reg0, base;

sys/dev/pv/pvbus.c

156

uint32_t regs[3];

sys/dev/pv/pvbus.c

268

uint32_t regs[4];

sys/dev/pv/pvbus.c

280

uint32_t regs[4];

sys/dev/pv/pvbus.c

308

uint32_t regs[4];

sys/dev/pv/pvclock.c

110

static inline uint32_t

sys/dev/pv/pvclock.c

113

pvclock_read_done(const struct pvclock_time_info *, uint32_t);

sys/dev/pv/pvclock.c

115

pvclock_scale_delta(uint64_t, uint32_t, int);

sys/dev/pv/pvclock.c

187

uint32_t version;

sys/dev/pv/pvclock.c

275

static inline uint32_t

sys/dev/pv/pvclock.c

278

uint32_t version = ti->ti_version & ~0x1;

sys/dev/pv/pvclock.c

285

uint32_t version)

sys/dev/pv/pvclock.c

292

pvclock_scale_delta(uint64_t delta, uint32_t mul_frac, int shift)

sys/dev/pv/pvclock.c

301

lower = ((uint64_t)mul_frac * ((uint32_t)delta)) >> 32;

sys/dev/pv/pvclock.c

325

uint32_t version, mul_frac;

sys/dev/pv/pvclock.c

74

: "b" ((uint32_t)n), "c" ((uint32_t)(n >> 32)));

sys/dev/pv/pvreg.h

50

uint32_t wc_version;

sys/dev/pv/pvreg.h

51

uint32_t wc_sec;

sys/dev/pv/pvreg.h

52

uint32_t wc_nsec;

sys/dev/pv/pvreg.h

56

uint32_t ti_version;

sys/dev/pv/pvreg.h

57

uint32_t ti_pad0;

sys/dev/pv/pvreg.h

60

uint32_t ti_tsc_to_system_mul;

sys/dev/pv/pvvar.h

54

uint32_t hv_base;

sys/dev/pv/pvvar.h

55

uint32_t hv_features;

sys/dev/pv/vioblk.c

118

uint32_t sc_queued;

sys/dev/pv/vioblk.c

191

uint32_t size_max = virtio_read_device_config_4(vsc,

sys/dev/pv/vioblk.c

200

uint32_t seg_max = virtio_read_device_config_4(vsc,

sys/dev/pv/vioblkreg.h

78

uint32_t type; /* VIRTIO_BLK_T_* */

sys/dev/pv/vioblkreg.h

79

uint32_t ioprio;

sys/dev/pv/viocon.c

59

uint32_t id; /* Port number */

sys/dev/pv/viogpu.c

156

uint32_t defattr;

sys/dev/pv/viogpu.c

52

int viogpu_transfer_to_host_2d(struct viogpu_softc *sc, int, uint32_t,

sys/dev/pv/viogpu.c

53

uint32_t);

sys/dev/pv/viogpu.c

54

int viogpu_flush_resource(struct viogpu_softc *, int, uint32_t, uint32_t);

sys/dev/pv/viogpu.c

540

uint32_t width, uint32_t height)

sys/dev/pv/viogpu.c

569

viogpu_flush_resource(struct viogpu_softc *sc, int resource_id, uint32_t width,

sys/dev/pv/viogpu.c

570

uint32_t height)

sys/dev/pv/viogpu.c

61

int *, int *, uint32_t *);

sys/dev/pv/viogpu.c

655

void **cookiep, int *curxp, int *curyp, uint32_t *attrp)

sys/dev/pv/viogpu.h

44

#define __u32 uint32_t

sys/dev/pv/viogpu.h

46

#define __le32 uint32_t

sys/dev/pv/viomb.c

195

sizeof(uint32_t) * PGS_PER_REQ,

sys/dev/pv/vioscsi.c

126

uint32_t cmd_per_lun = virtio_read_device_config_4(vsc,

sys/dev/pv/vioscsi.c

128

uint32_t seg_max = virtio_read_device_config_4(vsc,

sys/dev/pv/vioscsi.c

132

uint32_t max_lun = virtio_read_device_config_4(vsc,

sys/dev/pv/vioscsireg.h

65

uint32_t sense_len;

sys/dev/pv/vioscsireg.h

66

uint32_t residual;

sys/dev/pv/virtioreg.h

160

uint32_t len;

sys/dev/pv/virtioreg.h

176

uint32_t id;

sys/dev/pv/virtioreg.h

178

uint32_t len;

sys/dev/pv/virtiovar.h

139

uint32_t vq_notify_off;

sys/dev/pv/virtiovar.h

152

uint32_t (*read_dev_cfg_4)(struct virtio_softc *, int);

sys/dev/pv/virtiovar.h

156

void (*write_dev_cfg_4)(struct virtio_softc *, int, uint32_t);

sys/dev/pv/vmmci.c

161

uint32_t cmd;

sys/dev/pv/vmt.c

1473

vm_rpc_open(struct vm_rpc *rpc, uint32_t proto)

sys/dev/pv/vmt.c

149

uint32_t v4_addr_type;

sys/dev/pv/vmt.c

150

uint32_t v4_addr_len;

sys/dev/pv/vmt.c

152

uint32_t v4_prefix_len;

sys/dev/pv/vmt.c

153

uint32_t v4_origin;

sys/dev/pv/vmt.c

1532

vm_rpc_send(const struct vm_rpc *rpc, const uint8_t *buf, uint32_t length)

sys/dev/pv/vmt.c

154

uint32_t v4_status;

sys/dev/pv/vmt.c

1570

frame.esi.word = (uint32_t)buf;

sys/dev/pv/vmt.c

158

uint32_t v6_addr_type;

sys/dev/pv/vmt.c

159

uint32_t v6_addr_len;

sys/dev/pv/vmt.c

1591

vm_rpc_get_data(const struct vm_rpc *rpc, char *data, uint32_t length,

sys/dev/pv/vmt.c

1607

frame.edi.word = (uint32_t)data;

sys/dev/pv/vmt.c

161

uint32_t v6_prefix_len;

sys/dev/pv/vmt.c

162

uint32_t v6_origin;

sys/dev/pv/vmt.c

163

uint32_t v6_status;

sys/dev/pv/vmt.c

1645

vm_rpc_get_length(const struct vm_rpc *rpc, uint32_t *length, uint16_t *dataid)

sys/dev/pv/vmt.c

167

uint32_t ni_mac_len;

sys/dev/pv/vmt.c

1685

uint32_t length)

sys/dev/pv/vmt.c

169

uint32_t ni_num_addrs;

sys/dev/pv/vmt.c

173

uint32_t nn_mac_len;

sys/dev/pv/vmt.c

174

uint32_t nn_num_addrs;

sys/dev/pv/vmt.c

178

uint32_t np_dns_config;

sys/dev/pv/vmt.c

179

uint32_t np_wins_config;

sys/dev/pv/vmt.c

180

uint32_t np_dhcpv4_config;

sys/dev/pv/vmt.c

181

uint32_t np_dhcpv6_config;

sys/dev/pv/vmt.c

185

uint32_t nl_version;

sys/dev/pv/vmt.c

186

uint32_t nl_nic_list;

sys/dev/pv/vmt.c

187

uint32_t nl_num_nics;

sys/dev/pv/vmt.c

191

uint32_t nl_num_routes;

sys/dev/pv/vmt.c

192

uint32_t nl_dns_config;

sys/dev/pv/vmt.c

193

uint32_t nl_wins_config;

sys/dev/pv/vmt.c

194

uint32_t nl_dhcpv4_config;

sys/dev/pv/vmt.c

195

uint32_t nl_dhcpv6_config;

sys/dev/pv/vmt.c

206

uint32_t word;

sys/dev/pv/vmt.c

209

uint32_t low;

sys/dev/pv/vmt.c

210

uint32_t high;

sys/dev/pv/vmt.c

230

uint32_t cookie1;

sys/dev/pv/vmt.c

231

uint32_t cookie2;

sys/dev/pv/vmt.c

269

int vm_rpc_open(struct vm_rpc *, uint32_t);

sys/dev/pv/vmt.c

271

int vm_rpc_send(const struct vm_rpc *, const uint8_t *, uint32_t);

sys/dev/pv/vmt.c

273

int vm_rpc_get_length(const struct vm_rpc *, uint32_t *, uint16_t *);

sys/dev/pv/vmt.c

274

int vm_rpc_get_data(const struct vm_rpc *, char *, uint32_t, uint16_t);

sys/dev/pv/vmt.c

275

int vm_rpc_send_rpci_tx_buf(struct vmt_softc *, const uint8_t *, uint32_t);

sys/dev/pv/vmt.c

493

uint32_t rlen;

sys/dev/pv/xbf.c

109

uint32_t rsp_pad2;

sys/dev/pv/xbf.c

124

volatile uint32_t xr_prod;

sys/dev/pv/xbf.c

125

volatile uint32_t xr_prod_event;

sys/dev/pv/xbf.c

126

volatile uint32_t xr_cons;

sys/dev/pv/xbf.c

127

volatile uint32_t xr_cons_event;

sys/dev/pv/xbf.c

128

uint32_t xr_reserved[12];

sys/dev/pv/xbf.c

146

uint32_t ccb_first; /* first descriptor */

sys/dev/pv/xbf.c

147

uint32_t ccb_last; /* last descriptor */

sys/dev/pv/xbf.c

172

uint32_t sc_type;

sys/dev/pv/xbf.c

173

uint32_t sc_unit;

sys/dev/pv/xbf.c

178

uint32_t sc_block_size;

sys/dev/pv/xbf.c

182

uint32_t sc_xr_cons;

sys/dev/pv/xbf.c

183

uint32_t sc_xr_prod;

sys/dev/pv/xbf.c

184

uint32_t sc_xr_size; /* in pages */

sys/dev/pv/xbf.c

186

uint32_t sc_xr_ref[XBF_MAX_RING_SIZE];

sys/dev/pv/xbf.c

349

uint32_t cons;

sys/dev/pv/xbf.c

612

uint32_t nblk = 0;

sys/dev/pv/xbf.c

67

uint32_t sge_ref;

sys/dev/pv/xbf.c

752

uint32_t id, chunk;

sys/dev/pv/xbf.c

766

id = (uint32_t)xrd->xrd_rsp.rsp_id;

sys/dev/pv/xbf.c

79

uint32_t req_pad;

sys/dev/pv/xbf.c

92

uint32_t req_pad;

sys/dev/pv/xbf.c

927

sc->sc_unit = (uint32_t)res;

sys/dev/pv/xbf.c

97

uint32_t req_gref[XBF_MAX_ISGE];

sys/dev/pv/xen.c

1179

uint32_t flags, *ptr;

sys/dev/pv/xen.c

1197

ptr = (uint32_t *)&ge->ge_table[ref];

sys/dev/pv/xen.c

266

uint32_t regs[4];

sys/dev/pv/xenreg.h

146

uint32_t version;

sys/dev/pv/xenreg.h

147

uint32_t pad0;

sys/dev/pv/xenreg.h

157

uint32_t tsc_to_system_mul;

sys/dev/pv/xenreg.h

247

uint32_t wc_version; /* Version counter: see vcpu_time_info_t. */

sys/dev/pv/xenreg.h

248

uint32_t wc_sec; /* Secs 00:00:00 UTC, Jan 1, 1970. */

sys/dev/pv/xenreg.h

249

uint32_t wc_nsec; /* Nsecs 00:00:00 UTC, Jan 1, 1970. */

sys/dev/pv/xenreg.h

264

uint32_t index; /* IN */

sys/dev/pv/xenreg.h

439

typedef uint32_t evtchn_port_t;

sys/dev/pv/xenreg.h

494

uint32_t status;

sys/dev/pv/xenreg.h

495

uint32_t vcpu; /* VCPU to which this channel is bound. */

sys/dev/pv/xenreg.h

504

uint32_t pirq; /* EVTCHNSTAT_pirq */

sys/dev/pv/xenreg.h

505

uint32_t virq; /* EVTCHNSTAT_virq */

sys/dev/pv/xenreg.h

524

uint32_t vcpu;

sys/dev/pv/xenreg.h

540

uint32_t cmd; /* EVTCHNOP_* */

sys/dev/pv/xenreg.h

607

typedef uint32_t grant_ref_t;

sys/dev/pv/xenreg.h

647

uint32_t frame;

sys/dev/pv/xenreg.h

668

uint32_t nr_frames;

sys/dev/pv/xenreg.h

669

uint32_t max_nr_frames;

sys/dev/pv/xenreg.h

682

uint32_t version;

sys/dev/pv/xenreg.h

694

uint32_t version;

sys/dev/pv/xenreg.h

772

uint32_t submap; /* OUT: 32-bit submap */

sys/dev/pv/xenstore.c

117

uint32_t xsm_read;

sys/dev/pv/xenstore.c

118

uint32_t xsm_dlen;

sys/dev/pv/xenstore.c

130

uint32_t xsr_req_cons;

sys/dev/pv/xenstore.c

131

uint32_t xsr_req_prod;

sys/dev/pv/xenstore.c

132

uint32_t xsr_rsp_cons;

sys/dev/pv/xenstore.c

133

uint32_t xsr_rsp_prod;

sys/dev/pv/xenstore.c

327

static inline uint32_t

sys/dev/pv/xenstore.c

330

uint32_t cons = req ? xsr->xsr_req_cons : xsr->xsr_rsp_cons;

sys/dev/pv/xenstore.c

331

uint32_t prod = req ? xsr->xsr_req_prod : xsr->xsr_rsp_prod;

sys/dev/pv/xenstore.c

459

uint32_t prod = xsr->xsr_req_prod & (XS_RING_SIZE - 1);

sys/dev/pv/xenstore.c

460

uint32_t avail = xs_ring_avail(xsr, 1);

sys/dev/pv/xenstore.c

486

uint32_t cons = xsr->xsr_rsp_cons & (XS_RING_SIZE - 1);

sys/dev/pv/xenstore.c

487

uint32_t avail = xs_ring_avail(xsr, 0);

sys/dev/pv/xenstore.c

517

uint32_t avail;

sys/dev/pv/xenstore.c

639

uint32_t dlen;

sys/dev/pv/xenstore.c

91

uint32_t xmh_type;

sys/dev/pv/xenstore.c

93

uint32_t xmh_rid;

sys/dev/pv/xenstore.c

95

uint32_t xmh_tid;

sys/dev/pv/xenstore.c

97

uint32_t xmh_len;

sys/dev/pv/xenvar.h

100

uint32_t sc_unplug;

sys/dev/pv/xenvar.h

145

typedef uint32_t xen_intr_handle_t;

sys/dev/pv/xenvar.h

183

uint32_t xst_id;

sys/dev/pv/xenvar.h

88

uint32_t sc_base;

sys/dev/pv/xenvar.h

90

uint32_t sc_features;

sys/dev/pv/xenvar.h

97

uint32_t sc_flags;

sys/dev/rasops/rasops.c

1033

rasops_erasecols(void *cookie, int row, int col, int num, uint32_t attr)

sys/dev/rasops/rasops.c

1232

rasops_putchar_rotated(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops.c

1272

rasops_erasecols_rotated(void *cookie, int row, int col, int num, uint32_t attr)

sys/dev/rasops/rasops.c

1327

rasops_eraserows_rotated(void *cookie, int row, int num, uint32_t attr)

sys/dev/rasops/rasops.c

133

uint32_t rs_defattr;

sys/dev/rasops/rasops.c

1374

int *curxp, int *curyp, uint32_t *attrp)

sys/dev/rasops/rasops.c

146

int rasops_pack_cattr(void *, int, int, int, uint32_t *);

sys/dev/rasops/rasops.c

147

int rasops_pack_mattr(void *, int, int, int, uint32_t *);

sys/dev/rasops/rasops.c

150

void rasops_unpack_attr(void *, uint32_t, int *, int *, int *);

sys/dev/rasops/rasops.c

1531

rasops_vcons_putchar(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops.c

1579

rasops_vcons_erasecols(void *cookie, int row, int col, int num, uint32_t attr)

sys/dev/rasops/rasops.c

158

int rasops_erasecols_rotated(void *, int, int, int, uint32_t);

sys/dev/rasops/rasops.c

159

int rasops_eraserows_rotated(void *, int, int, uint32_t);

sys/dev/rasops/rasops.c

160

int rasops_putchar_rotated(void *, int, int, u_int, uint32_t);

sys/dev/rasops/rasops.c

1651

rasops_vcons_eraserows(void *cookie, int row, int num, uint32_t attr)

sys/dev/rasops/rasops.c

1671

rasops_vcons_pack_attr(void *cookie, int fg, int bg, int flg, uint32_t *attr)

sys/dev/rasops/rasops.c

1679

rasops_vcons_unpack_attr(void *cookie, uint32_t attr, int *fg, int *bg,

sys/dev/rasops/rasops.c

1688

rasops_wronly_putchar(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops.c

1722

rasops_wronly_erasecols(void *cookie, int row, int col, int num, uint32_t attr)

sys/dev/rasops/rasops.c

1763

rasops_wronly_eraserows(void *cookie, int row, int num, uint32_t attr)

sys/dev/rasops/rasops.c

177

int rasops_vcons_putchar(void *, int, int, u_int, uint32_t);

sys/dev/rasops/rasops.c

1784

uint32_t attr;

sys/dev/rasops/rasops.c

179

int rasops_vcons_erasecols(void *, int, int, int, uint32_t);

sys/dev/rasops/rasops.c

181

int rasops_vcons_eraserows(void *, int, int, uint32_t);

sys/dev/rasops/rasops.c

182

int rasops_vcons_pack_attr(void *, int, int, int, uint32_t *);

sys/dev/rasops/rasops.c

183

void rasops_vcons_unpack_attr(void *, uint32_t, int *, int *, int *);

sys/dev/rasops/rasops.c

185

int rasops_wronly_putchar(void *, int, int, u_int, uint32_t);

sys/dev/rasops/rasops.c

187

int rasops_wronly_erasecols(void *, int, int, int, uint32_t);

sys/dev/rasops/rasops.c

189

int rasops_wronly_eraserows(void *, int, int, uint32_t);

sys/dev/rasops/rasops.c

283

uint32_t attr;

sys/dev/rasops/rasops.c

303

uint32_t attr;

sys/dev/rasops/rasops.c

538

rasops_pack_cattr(void *cookie, int fg, int bg, int flg, uint32_t *attr)

sys/dev/rasops/rasops.c

568

rasops_pack_mattr(void *cookie, int fg, int bg, int flg, uint32_t *attr)

sys/dev/rasops/rasops.c

873

rasops_unpack_attr(void *cookie, uint32_t attr, int *fg, int *bg, int *underline)

sys/dev/rasops/rasops.c

885

rasops_eraserows(void *cookie, int row, int num, uint32_t attr)

sys/dev/rasops/rasops.h

133

int (*ri_putchar)(void *, int, int, u_int, uint32_t);

sys/dev/rasops/rasops.h

135

int (*ri_erasecols)(void *, int, int, int, uint32_t);

sys/dev/rasops/rasops.h

137

int (*ri_eraserows)(void *, int, int, uint32_t);

sys/dev/rasops/rasops.h

138

int (*ri_pack_attr)(void *, int, int, int, uint32_t *);

sys/dev/rasops/rasops.h

171

int rasops_eraserows(void *, int, int, uint32_t);

sys/dev/rasops/rasops.h

172

int rasops_erasecols(void *, int, int, int, uint32_t);

sys/dev/rasops/rasops.h

174

int rasops_alloc_screen(void *, void **, int *, int *, uint32_t *);

sys/dev/rasops/rasops1.c

231

rasops1_putchar8(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops1.c

294

rasops1_putchar16(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops1.c

44

int rasops1_erasecols(void *, int, int, int, uint32_t);

sys/dev/rasops/rasops1.c

46

int rasops1_putchar(void *, int, int col, u_int, uint32_t);

sys/dev/rasops/rasops1.c

48

int rasops1_putchar8(void *, int, int col, u_int, uint32_t);

sys/dev/rasops/rasops1.c

49

int rasops1_putchar16(void *, int, int col, u_int, uint32_t);

sys/dev/rasops/rasops1.c

85

rasops1_putchar(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops15.c

108

rasops15_putchar(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops15.c

180

rasops15_makestamp(struct rasops_info *ri, uint32_t attr)

sys/dev/rasops/rasops15.c

208

rasops15_putchar8(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops15.c

284

rasops15_putchar12(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops15.c

364

rasops15_putchar16(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops15.c

41

int rasops15_putchar(void *, int, int, u_int, uint32_t attr);

sys/dev/rasops/rasops15.c

43

int rasops15_putchar8(void *, int, int, u_int, uint32_t attr);

sys/dev/rasops/rasops15.c

44

int rasops15_putchar12(void *, int, int, u_int, uint32_t attr);

sys/dev/rasops/rasops15.c

45

int rasops15_putchar16(void *, int, int, u_int, uint32_t attr);

sys/dev/rasops/rasops15.c

46

void rasops15_makestamp(struct rasops_info *, uint32_t);

sys/dev/rasops/rasops15.c

52

static uint32_t stamp_attr;

sys/dev/rasops/rasops24.c

109

rasops24_putchar(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops24.c

188

rasops24_makestamp(struct rasops_info *ri, uint32_t attr)

sys/dev/rasops/rasops24.c

229

rasops24_putchar8(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops24.c

307

rasops24_putchar12(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops24.c

392

rasops24_putchar16(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops24.c

42

int rasops24_putchar(void *, int, int, u_int, uint32_t attr);

sys/dev/rasops/rasops24.c

44

int rasops24_putchar8(void *, int, int, u_int, uint32_t attr);

sys/dev/rasops/rasops24.c

45

int rasops24_putchar12(void *, int, int, u_int, uint32_t attr);

sys/dev/rasops/rasops24.c

46

int rasops24_putchar16(void *, int, int, u_int, uint32_t attr);

sys/dev/rasops/rasops24.c

47

void rasops24_makestamp(struct rasops_info *, uint32_t);

sys/dev/rasops/rasops24.c

53

static uint32_t stamp_attr;

sys/dev/rasops/rasops32.c

41

int rasops32_putchar(void *, int, int, u_int, uint32_t);

sys/dev/rasops/rasops32.c

65

rasops32_putchar(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops32.c

68

uint32_t fb, clr[2];

sys/dev/rasops/rasops4.c

212

rasops4_putchar(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops4.c

224

rasops4_makestamp(struct rasops_info *ri, uint32_t attr)

sys/dev/rasops/rasops4.c

251

rasops4_putchar8(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops4.c

323

rasops4_putchar12(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops4.c

398

rasops4_putchar16(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops4.c

44

int rasops4_erasecols(void *, int, int, int, uint32_t);

sys/dev/rasops/rasops4.c

46

int rasops4_putchar(void *, int, int col, u_int, uint32_t);

sys/dev/rasops/rasops4.c

48

int rasops4_putchar8(void *, int, int col, u_int, uint32_t);

sys/dev/rasops/rasops4.c

49

int rasops4_putchar12(void *, int, int col, u_int, uint32_t);

sys/dev/rasops/rasops4.c

50

int rasops4_putchar16(void *, int, int col, u_int, uint32_t);

sys/dev/rasops/rasops4.c

51

void rasops4_makestamp(struct rasops_info *, uint32_t);

sys/dev/rasops/rasops4.c

57

static uint32_t stamp_attr;

sys/dev/rasops/rasops4.c

99

rasops4_putchar(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops8.c

165

rasops8_makestamp(struct rasops_info *ri, uint32_t attr)

sys/dev/rasops/rasops8.c

197

rasops8_putchar8(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops8.c

265

rasops8_putchar12(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops8.c

336

rasops8_putchar16(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops8.c

41

int rasops8_putchar(void *, int, int, u_int, uint32_t attr);

sys/dev/rasops/rasops8.c

43

int rasops8_putchar8(void *, int, int, u_int, uint32_t attr);

sys/dev/rasops/rasops8.c

44

int rasops8_putchar12(void *, int, int, u_int, uint32_t attr);

sys/dev/rasops/rasops8.c

45

int rasops8_putchar16(void *, int, int, u_int, uint32_t attr);

sys/dev/rasops/rasops8.c

46

void rasops8_makestamp(struct rasops_info *ri, uint32_t);

sys/dev/rasops/rasops8.c

52

static uint32_t stamp_attr;

sys/dev/rasops/rasops8.c

96

rasops8_putchar(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/rasops/rasops_bitops.h

40

NAME(erasecols)(void *cookie, int row, int col, int num, uint32_t attr)

sys/dev/rndis.h

100

uint32_t rm_len;

sys/dev/rndis.h

110

uint32_t rm_type;

sys/dev/rndis.h

111

uint32_t rm_len;

sys/dev/rndis.h

112

uint32_t rm_dataoffset;

sys/dev/rndis.h

113

uint32_t rm_datalen;

sys/dev/rndis.h

114

uint32_t rm_oobdataoffset;

sys/dev/rndis.h

115

uint32_t rm_oobdatalen;

sys/dev/rndis.h

116

uint32_t rm_oobdataelements;

sys/dev/rndis.h

117

uint32_t rm_pktinfooffset;

sys/dev/rndis.h

118

uint32_t rm_pktinfolen;

sys/dev/rndis.h

119

uint32_t rm_vchandle;

sys/dev/rndis.h

120

uint32_t rm_reserved;

sys/dev/rndis.h

125

uint32_t rm_size;

sys/dev/rndis.h

126

uint32_t rm_type; /* NDIS_PKTINFO_TYPE_ */

sys/dev/rndis.h

127

uint32_t rm_pktinfooffset;

sys/dev/rndis.h

148

uint32_t rm_type;

sys/dev/rndis.h

149

uint32_t rm_len;

sys/dev/rndis.h

150

uint32_t rm_rid;

sys/dev/rndis.h

151

uint32_t rm_status;

sys/dev/rndis.h

159

uint32_t rm_type;

sys/dev/rndis.h

160

uint32_t rm_len;

sys/dev/rndis.h

161

uint32_t rm_rid;

sys/dev/rndis.h

162

uint32_t rm_ver_major;

sys/dev/rndis.h

163

uint32_t rm_ver_minor;

sys/dev/rndis.h

164

uint32_t rm_max_xfersz;

sys/dev/rndis.h

168

uint32_t rm_type;

sys/dev/rndis.h

169

uint32_t rm_len;

sys/dev/rndis.h

170

uint32_t rm_rid;

sys/dev/rndis.h

171

uint32_t rm_status;

sys/dev/rndis.h

172

uint32_t rm_ver_major;

sys/dev/rndis.h

173

uint32_t rm_ver_minor;

sys/dev/rndis.h

174

uint32_t rm_devflags;

sys/dev/rndis.h

175

uint32_t rm_medium;

sys/dev/rndis.h

176

uint32_t rm_pktmaxcnt;

sys/dev/rndis.h

177

uint32_t rm_pktmaxsz;

sys/dev/rndis.h

178

uint32_t rm_align;

sys/dev/rndis.h

179

uint32_t rm_aflistoffset;

sys/dev/rndis.h

180

uint32_t rm_aflistsz;

sys/dev/rndis.h

187

uint32_t rm_type;

sys/dev/rndis.h

188

uint32_t rm_len;

sys/dev/rndis.h

189

uint32_t rm_rid;

sys/dev/rndis.h

197

uint32_t rm_type;

sys/dev/rndis.h

198

uint32_t rm_len;

sys/dev/rndis.h

199

uint32_t rm_rid;

sys/dev/rndis.h

200

uint32_t rm_oid;

sys/dev/rndis.h

201

uint32_t rm_infobuflen;

sys/dev/rndis.h

202

uint32_t rm_infobufoffset;

sys/dev/rndis.h

203

uint32_t rm_devicevchdl;

sys/dev/rndis.h

207

uint32_t rm_type;

sys/dev/rndis.h

208

uint32_t rm_len;

sys/dev/rndis.h

209

uint32_t rm_rid;

sys/dev/rndis.h

210

uint32_t rm_status;

sys/dev/rndis.h

211

uint32_t rm_infobuflen;

sys/dev/rndis.h

212

uint32_t rm_infobufoffset;

sys/dev/rndis.h

220

uint32_t rm_type;

sys/dev/rndis.h

221

uint32_t rm_len;

sys/dev/rndis.h

222

uint32_t rm_rid;

sys/dev/rndis.h

223

uint32_t rm_oid;

sys/dev/rndis.h

224

uint32_t rm_infobuflen;

sys/dev/rndis.h

225

uint32_t rm_infobufoffset;

sys/dev/rndis.h

226

uint32_t rm_devicevchdl;

sys/dev/rndis.h

230

uint32_t rm_type;

sys/dev/rndis.h

231

uint32_t rm_len;

sys/dev/rndis.h

232

uint32_t rm_rid;

sys/dev/rndis.h

233

uint32_t rm_status;

sys/dev/rndis.h

241

uint32_t rm_nameoffset;

sys/dev/rndis.h

242

uint32_t rm_namelen;

sys/dev/rndis.h

243

uint32_t rm_type;

sys/dev/rndis.h

244

uint32_t rm_valueoffset;

sys/dev/rndis.h

245

uint32_t rm_valuelen;

sys/dev/rndis.h

253

uint32_t rm_type;

sys/dev/rndis.h

254

uint32_t rm_len;

sys/dev/rndis.h

255

uint32_t rm_rid;

sys/dev/rndis.h

259

uint32_t rm_type;

sys/dev/rndis.h

260

uint32_t rm_len;

sys/dev/rndis.h

261

uint32_t rm_status;

sys/dev/rndis.h

262

uint32_t rm_adrreset;

sys/dev/rndis.h

269

uint32_t rm_type;

sys/dev/rndis.h

270

uint32_t rm_len;

sys/dev/rndis.h

271

uint32_t rm_status;

sys/dev/rndis.h

272

uint32_t rm_stbuflen;

sys/dev/rndis.h

273

uint32_t rm_stbufoffset;

sys/dev/rndis.h

283

uint32_t rm_diagstatus;

sys/dev/rndis.h

284

uint32_t rm_erroffset;

sys/dev/rndis.h

292

uint32_t rm_type;

sys/dev/rndis.h

293

uint32_t rm_len;

sys/dev/rndis.h

294

uint32_t rm_rid;

sys/dev/rndis.h

298

uint32_t rm_type;

sys/dev/rndis.h

299

uint32_t rm_len;

sys/dev/rndis.h

300

uint32_t rm_rid;

sys/dev/rndis.h

301

uint32_t rm_status;

sys/dev/rndis.h

99

uint32_t rm_type;

sys/dev/sbus/cgsix.c

70

int cgsix_ras_erasecols(void *, int, int, int, uint32_t);

sys/dev/sbus/cgsix.c

71

int cgsix_ras_eraserows(void *, int, int, uint32_t);

sys/dev/sbus/cgsix.c

897

cgsix_ras_erasecols(void *cookie, int row, int col, int n, uint32_t attr)

sys/dev/sbus/cgsix.c

941

cgsix_ras_eraserows(void *cookie, int row, int n, uint32_t attr)

sys/dev/sbus/mgx.c

127

uint32_t sc_dec; /* dec register template */

sys/dev/sbus/mgx.c

149

int mgx_ras_erasecols(void *, int, int, int, uint32_t);

sys/dev/sbus/mgx.c

150

int mgx_ras_eraserows(void *, int, int, uint32_t);

sys/dev/sbus/mgx.c

156

void mgx_write_4(vaddr_t, uint, uint32_t);

sys/dev/sbus/mgx.c

336

mgx_write_4(vaddr_t regs, uint offs, uint32_t val)

sys/dev/sbus/mgx.c

338

*(volatile uint32_t *)(regs + offs) = val;

sys/dev/sbus/mgx.c

710

mgx_ras_erasecols(void *v, int row, int col, int n, uint32_t attr)

sys/dev/sbus/mgx.c

740

mgx_ras_eraserows(void *v, int row, int n, uint32_t attr)

sys/dev/sbus/zx.c

153

void zx_fillrect(struct rasops_info *, int, int, int, int, uint32_t, int);

sys/dev/sbus/zx.c

155

int zx_putchar(void *, int, int, u_int, uint32_t);

sys/dev/sbus/zx.c

157

int zx_erasecols(void *, int, int, int, uint32_t);

sys/dev/sbus/zx.c

159

int zx_eraserows(void *, int, int, uint32_t);

sys/dev/sbus/zx.c

567

zx_fillrect(struct rasops_info *ri, int x, int y, int w, int h, uint32_t attr,

sys/dev/sbus/zx.c

644

zx_erasecols(void *cookie, int row, int col, int num, uint32_t attr)

sys/dev/sbus/zx.c

656

zx_eraserows(void *cookie, int row, int num, uint32_t attr)

sys/dev/sbus/zx.c

712

zx_putchar(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/sdmmc/if_bwfm_sdio.c

103

uint32_t sc_console_readidx;

sys/dev/sdmmc/if_bwfm_sdio.c

1045

bwfm_sdio_buscore_activate(struct bwfm_softc *bwfm, uint32_t rstvec)

sys/dev/sdmmc/if_bwfm_sdio.c

131

void bwfm_sdio_backplane(struct bwfm_sdio_softc *, uint32_t);

sys/dev/sdmmc/if_bwfm_sdio.c

132

uint8_t bwfm_sdio_read_1(struct bwfm_sdio_softc *, uint32_t);

sys/dev/sdmmc/if_bwfm_sdio.c

133

uint32_t bwfm_sdio_read_4(struct bwfm_sdio_softc *, uint32_t);

sys/dev/sdmmc/if_bwfm_sdio.c

134

void bwfm_sdio_write_1(struct bwfm_sdio_softc *, uint32_t,

sys/dev/sdmmc/if_bwfm_sdio.c

136

void bwfm_sdio_write_4(struct bwfm_sdio_softc *, uint32_t,

sys/dev/sdmmc/if_bwfm_sdio.c

137

uint32_t);

sys/dev/sdmmc/if_bwfm_sdio.c

139

struct sdmmc_function *, uint32_t, char *, size_t);

sys/dev/sdmmc/if_bwfm_sdio.c

141

struct sdmmc_function *, uint32_t, char *, size_t);

sys/dev/sdmmc/if_bwfm_sdio.c

142

uint32_t bwfm_sdio_ram_read_write(struct bwfm_sdio_softc *,

sys/dev/sdmmc/if_bwfm_sdio.c

143

uint32_t, char *, size_t, int);

sys/dev/sdmmc/if_bwfm_sdio.c

144

uint32_t bwfm_sdio_frame_read_write(struct bwfm_sdio_softc *,

sys/dev/sdmmc/if_bwfm_sdio.c

147

uint32_t bwfm_sdio_dev_read(struct bwfm_sdio_softc *, uint32_t);

sys/dev/sdmmc/if_bwfm_sdio.c

148

void bwfm_sdio_dev_write(struct bwfm_sdio_softc *, uint32_t,

sys/dev/sdmmc/if_bwfm_sdio.c

1486

uint32_t newidx;

sys/dev/sdmmc/if_bwfm_sdio.c

149

uint32_t);

sys/dev/sdmmc/if_bwfm_sdio.c

151

uint32_t bwfm_sdio_buscore_read(struct bwfm_softc *, uint32_t);

sys/dev/sdmmc/if_bwfm_sdio.c

152

void bwfm_sdio_buscore_write(struct bwfm_softc *, uint32_t,

sys/dev/sdmmc/if_bwfm_sdio.c

153

uint32_t);

sys/dev/sdmmc/if_bwfm_sdio.c

155

void bwfm_sdio_buscore_activate(struct bwfm_softc *, uint32_t);

sys/dev/sdmmc/if_bwfm_sdio.c

255

uint32_t reg;

sys/dev/sdmmc/if_bwfm_sdio.c

352

uint32_t clk, reg;

sys/dev/sdmmc/if_bwfm_sdio.c

545

bwfm_chip_set_active(bwfm, *(uint32_t *)ucode);

sys/dev/sdmmc/if_bwfm_sdio.c

593

uint32_t clkctl, devctl, req;

sys/dev/sdmmc/if_bwfm_sdio.c

654

uint32_t addr, shaddr;

sys/dev/sdmmc/if_bwfm_sdio.c

702

uint32_t clkctl, devctl, intstat, hostint;

sys/dev/sdmmc/if_bwfm_sdio.c

768

bwfm_sdio_backplane(struct bwfm_sdio_softc *sc, uint32_t bar0)

sys/dev/sdmmc/if_bwfm_sdio.c

783

bwfm_sdio_read_1(struct bwfm_sdio_softc *sc, uint32_t addr)

sys/dev/sdmmc/if_bwfm_sdio.c

803

uint32_t

sys/dev/sdmmc/if_bwfm_sdio.c

804

bwfm_sdio_read_4(struct bwfm_sdio_softc *sc, uint32_t addr)

sys/dev/sdmmc/if_bwfm_sdio.c

807

uint32_t bar0 = addr & ~BWFM_SDIO_SB_OFT_ADDR_MASK;

sys/dev/sdmmc/if_bwfm_sdio.c

808

uint32_t rv;

sys/dev/sdmmc/if_bwfm_sdio.c

831

bwfm_sdio_write_1(struct bwfm_sdio_softc *sc, uint32_t addr, uint8_t data)

sys/dev/sdmmc/if_bwfm_sdio.c

850

bwfm_sdio_write_4(struct bwfm_sdio_softc *sc, uint32_t addr, uint32_t data)

sys/dev/sdmmc/if_bwfm_sdio.c

853

uint32_t bar0 = addr & ~BWFM_SDIO_SB_OFT_ADDR_MASK;

sys/dev/sdmmc/if_bwfm_sdio.c

876

uint32_t reg, char *data, size_t size)

sys/dev/sdmmc/if_bwfm_sdio.c

896

uint32_t reg, char *data, size_t size)

sys/dev/sdmmc/if_bwfm_sdio.c

911

uint32_t

sys/dev/sdmmc/if_bwfm_sdio.c

912

bwfm_sdio_ram_read_write(struct bwfm_sdio_softc *sc, uint32_t reg,

sys/dev/sdmmc/if_bwfm_sdio.c

915

uint32_t sbaddr, sdaddr, off;

sys/dev/sdmmc/if_bwfm_sdio.c

92

uint32_t sc_bar0;

sys/dev/sdmmc/if_bwfm_sdio.c

950

uint32_t

sys/dev/sdmmc/if_bwfm_sdio.c

954

uint32_t addr;

sys/dev/sdmmc/if_bwfm_sdio.c

96

uint32_t sc_console_addr;

sys/dev/sdmmc/if_bwfm_sdio.c

971

uint32_t

sys/dev/sdmmc/if_bwfm_sdio.c

972

bwfm_sdio_dev_read(struct bwfm_sdio_softc *sc, uint32_t reg)

sys/dev/sdmmc/if_bwfm_sdio.c

980

bwfm_sdio_dev_write(struct bwfm_sdio_softc *sc, uint32_t reg, uint32_t val)

sys/dev/sdmmc/if_bwfm_sdio.c

987

uint32_t

sys/dev/sdmmc/if_bwfm_sdio.c

988

bwfm_sdio_buscore_read(struct bwfm_softc *bwfm, uint32_t reg)

sys/dev/sdmmc/if_bwfm_sdio.c

995

bwfm_sdio_buscore_write(struct bwfm_softc *bwfm, uint32_t reg, uint32_t val)

sys/dev/sdmmc/if_bwfm_sdio.h

181

uint32_t flags;

sys/dev/sdmmc/if_bwfm_sdio.h

182

uint32_t trap_addr;

sys/dev/sdmmc/if_bwfm_sdio.h

183

uint32_t assert_exp_addr;

sys/dev/sdmmc/if_bwfm_sdio.h

184

uint32_t assert_file_addr;

sys/dev/sdmmc/if_bwfm_sdio.h

185

uint32_t assert_line;

sys/dev/sdmmc/if_bwfm_sdio.h

186

uint32_t console_addr;

sys/dev/sdmmc/if_bwfm_sdio.h

187

uint32_t msgtrace_addr;

sys/dev/sdmmc/if_bwfm_sdio.h

189

uint32_t brpt_addr;

sys/dev/sdmmc/if_bwfm_sdio.h

193

uint32_t vcons_in;

sys/dev/sdmmc/if_bwfm_sdio.h

194

uint32_t vcons_out;

sys/dev/sdmmc/if_bwfm_sdio.h

195

uint32_t log_buf;

sys/dev/sdmmc/if_bwfm_sdio.h

196

uint32_t log_bufsz;

sys/dev/sdmmc/if_bwfm_sdio.h

197

uint32_t log_idx;

sys/dev/sdmmc/sdhc.c

162

uint32_t reg;

sys/dev/sdmmc/sdhc.c

175

uint32_t reg;

sys/dev/sdmmc/sdhc.c

188

uint32_t reg;

sys/dev/sdmmc/sdhc.c

204

uint32_t reg;

sys/dev/sdmmc/sdhc.c

246

uint32_t caps;

sys/dev/sdmmc/sdhc.c

423

uint32_t caps2 = HREAD4(hp, SDHC_CAPABILITIES2);

sys/dev/sdmmc/sdhcreg.h

261

uint32_t address;

sys/dev/sdmmc/sdhcreg.h

267

uint32_t address_lo;

sys/dev/sdmmc/sdhcreg.h

268

uint32_t address_hi;

sys/dev/sdmmc/sdmmc.c

688

sdmmc_send_if_cond(struct sdmmc_softc *sc, uint32_t card_ocr)

sys/dev/sdmmc/sdmmc_mem.c

108

uint32_t host_ocr;

sys/dev/sdmmc/sdmmc_mem.c

109

uint32_t card_ocr;

sys/dev/sdmmc/sdmmc_mem.c

110

uint32_t new_ocr;

sys/dev/sdmmc/sdmmc_mem.c

111

uint32_t ocr = 0;

sys/dev/sdmmc/sdmmc_mem.c

35

typedef struct { uint32_t _bits[512/32]; } __packed __aligned(4) sdmmc_bitfield512_t;

sys/dev/sdmmc/sdmmc_mem.c

460

sdmmc_mem_send_scr(struct sdmmc_softc *sc, uint32_t *scr)

sys/dev/sdmmc/sdmmc_mem.c

48

int sdmmc_mem_send_scr(struct sdmmc_softc *, uint32_t *);

sys/dev/sdmmc/sdmmc_mem.c

489

sdmmc_mem_decode_scr(struct sdmmc_softc *sc, uint32_t *raw_scr,

sys/dev/sdmmc/sdmmc_mem.c

49

int sdmmc_mem_decode_scr(struct sdmmc_softc *, uint32_t *,

sys/dev/sdmmc/sdmmc_mem.c

669

uint32_t tmp0, tmp1;

sys/dev/sdmmc/sdmmc_mem.c

743

uint32_t raw_scr[2];

sys/dev/sdmmc/sdmmcreg.h

285

(__bitfield((uint32_t *)(status), 400 + (group - 1) * 16, 16))

sys/dev/sdmmc/sdmmcvar.h

187

uint32_t sc_caps; /* host capability */

sys/dev/sdmmc/sdmmcvar.h

250

int sdmmc_send_if_cond(struct sdmmc_softc *, uint32_t);

sys/dev/softraid.c

5097

uint32_t sub_raidoff; /* ofs of sr part in underlying dev */

sys/dev/softraid.c

63

uint32_t sr_debug = 0

sys/dev/softraid_raid5.c

759

uint32_t *xa = a, *xb = b;

sys/dev/softraid_raid6.c

766

uint32_t *pbuf = p, *data = d;

sys/dev/softraid_raid6.c

776

uint32_t *qbuf = q, *data = d, x;

sys/dev/softraid_raid6.c

782

*qbuf++ ^= (((uint32_t)gn_map[x & 0xff]) |

sys/dev/softraid_raid6.c

783

((uint32_t)gn_map[(x >> 8) & 0xff] << 8) |

sys/dev/softraid_raid6.c

784

((uint32_t)gn_map[(x >> 16) & 0xff] << 16) |

sys/dev/softraid_raid6.c

785

((uint32_t)gn_map[(x >> 24) & 0xff] << 24));

sys/dev/spi/spivar.h

28

uint32_t sc_freq;

sys/dev/tc/bba.c

240

uint32_t ssr;

sys/dev/tc/bba.c

353

uint32_t ssr;

sys/dev/tc/bba.c

381

uint32_t ssr;

sys/dev/tc/bba.c

410

uint32_t ssr;

sys/dev/tc/bba.c

478

uint32_t ssr;

sys/dev/usb/dwc2/dwc2.c

1032

uint32_t mps = UGETW(ed->wMaxPacketSize);

sys/dev/usb/dwc2/dwc2.c

1033

uint32_t len;

sys/dev/usb/dwc2/dwc2.c

1035

uint32_t flags = 0;

sys/dev/usb/dwc2/dwc2.c

1036

uint32_t off = 0;

sys/dev/usb/dwc2/dwc2.c

1278

uint32_t intrs;

sys/dev/usb/dwc2/dwc2.h

60

#define u32 uint32_t

sys/dev/usb/ehci.c

1663

sizeof(uint32_t) * itd->slot, sizeof(uint32_t),

sys/dev/usb/ehci.c

3265

uint32_t link;

sys/dev/usb/ehci.c

3378

const uint32_t mps = UGETW(ed->wMaxPacketSize);

sys/dev/usb/ehci.c

3410

uint32_t froffs = offs;

sys/dev/usb/ehci.c

3509

uint32_t endp;

sys/dev/usb/ehci.c

3527

uint32_t addr = DMAADDR(&xfer->dmabuf, offs);

sys/dev/usb/ehci.c

3528

uint32_t page = EHCI_PAGE(addr + xfer->frlengths[i] - 1);

sys/dev/usb/ehci.c

691

uint32_t status;

sys/dev/usb/ehci.c

786

uint32_t status = 0;

sys/dev/usb/ehcivar.h

98

uint32_t ehci_xfer_flags;

sys/dev/usb/if_athn_usb.c

1050

uint32_t reg, imask;

sys/dev/usb/if_athn_usb.c

122

uint32_t athn_usb_read(struct athn_softc *, uint32_t);

sys/dev/usb/if_athn_usb.c

123

void athn_usb_write(struct athn_softc *, uint32_t, uint32_t);

sys/dev/usb/if_athn_usb.c

1908

if (len >= 4 && *(uint32_t *)buf == htobe32(0x00c60000)) {

sys/dev/usb/if_athn_usb.c

204

void athn_set_rxfilter(struct athn_softc *, uint32_t);

sys/dev/usb/if_athn_usb.c

646

uint32_t addr;

sys/dev/usb/if_athn_usb.c

925

uint32_t addrs[8], vals[8], addr;

sys/dev/usb/if_athn_usb.c

945

uint32_t

sys/dev/usb/if_athn_usb.c

946

athn_usb_read(struct athn_softc *sc, uint32_t addr)

sys/dev/usb/if_athn_usb.c

949

uint32_t val;

sys/dev/usb/if_athn_usb.c

964

athn_usb_write(struct athn_softc *sc, uint32_t addr, uint32_t val)

sys/dev/usb/if_athn_usb.h

117

uint32_t iv32;

sys/dev/usb/if_athn_usb.h

132

uint32_t capflags;

sys/dev/usb/if_athn_usb.h

155

uint32_t opmode;

sys/dev/usb/if_athn_usb.h

174

uint32_t ampdu_limit;

sys/dev/usb/if_athn_usb.h

241

uint32_t flags;

sys/dev/usb/if_athn_usb.h

362

uint32_t rs_evm[AR_MAX_CHAINS];

sys/dev/usb/if_athn_usb.h

93

uint32_t addr;

sys/dev/usb/if_athn_usb.h

94

uint32_t val;

sys/dev/usb/if_bwfm_usb.c

112

uint32_t magic; /* "HDR0" */

sys/dev/usb/if_bwfm_usb.c

113

uint32_t len; /* Length of file including header */

sys/dev/usb/if_bwfm_usb.c

114

uint32_t crc32; /* CRC from flag_version to end of file */

sys/dev/usb/if_bwfm_usb.c

115

uint32_t flag_version; /* 0:15 flags, 16:31 version */

sys/dev/usb/if_bwfm_usb.c

116

uint32_t offsets[TRX_MAX_OFFSET];/* Offsets of partitions from start of

sys/dev/usb/if_bwfm_usb.c

122

uint32_t state;

sys/dev/usb/if_bwfm_usb.c

123

uint32_t bytes;

sys/dev/usb/if_bwfm_usb.c

127

uint32_t chip; /* Chip id */

sys/dev/usb/if_bwfm_usb.c

128

uint32_t chiprev; /* Chip rev */

sys/dev/usb/if_bwfm_usb.c

129

uint32_t ramsize; /* Size of RAM */

sys/dev/usb/if_bwfm_usb.c

130

uint32_t remapbase; /* Current remap base address */

sys/dev/usb/if_bwfm_usb.c

131

uint32_t boardtype; /* Type of board */

sys/dev/usb/if_bwfm_usb.c

132

uint32_t boardrev; /* Board revision */

sys/dev/usb/if_bwfm_usb.c

164

uint32_t sc_chip;

sys/dev/usb/if_bwfm_usb.c

165

uint32_t sc_chiprev;

sys/dev/usb/if_bwfm_usb.c

448

uint32_t len;

sys/dev/usb/if_bwfm_usb.c

654

uint32_t rdlstate, rdlbytes, sent = 0, sendlen = 0;

sys/dev/usb/if_bwfm_usb.c

755

uint32_t len = 0;

sys/dev/usb/if_mtw.c

1006

uint32_t tmp;

sys/dev/usb/if_mtw.c

102

int mtw_read(struct mtw_softc *, uint16_t, uint32_t *);

sys/dev/usb/if_mtw.c

103

int mtw_read_cfg(struct mtw_softc *, uint16_t, uint32_t *);

sys/dev/usb/if_mtw.c

107

int mtw_write(struct mtw_softc *, uint16_t, uint32_t);

sys/dev/usb/if_mtw.c

1078

uint32_t tmp;

sys/dev/usb/if_mtw.c

108

int mtw_write_cfg(struct mtw_softc *, uint16_t, uint32_t);

sys/dev/usb/if_mtw.c

1115

uint32_t tmp;

sys/dev/usb/if_mtw.c

112

int mtw_set_region_4(struct mtw_softc *, uint16_t, uint32_t, int);

sys/dev/usb/if_mtw.c

1140

uint32_t tmp;

sys/dev/usb/if_mtw.c

1172

uint32_t tmp;

sys/dev/usb/if_mtw.c

1189

mtw_usb_dma_read(struct mtw_softc *sc, uint32_t *val)

sys/dev/usb/if_mtw.c

119

int mtw_usb_dma_read(struct mtw_softc *, uint32_t *);

sys/dev/usb/if_mtw.c

1198

mtw_usb_dma_write(struct mtw_softc *sc, uint32_t val)

sys/dev/usb/if_mtw.c

120

int mtw_usb_dma_write(struct mtw_softc *, uint32_t);

sys/dev/usb/if_mtw.c

1207

mtw_mcu_calibrate(struct mtw_softc *sc, int func, uint32_t val)

sys/dev/usb/if_mtw.c

121

int mtw_mcu_calibrate(struct mtw_softc *, int, uint32_t);

sys/dev/usb/if_mtw.c

1217

mtw_mcu_channel(struct mtw_softc *sc, uint32_t r1, uint32_t r2, uint32_t r4)

sys/dev/usb/if_mtw.c

122

int mtw_mcu_channel(struct mtw_softc *, uint32_t, uint32_t, uint32_t);

sys/dev/usb/if_mtw.c

1229

mtw_mcu_radio(struct mtw_softc *sc, int func, uint32_t val)

sys/dev/usb/if_mtw.c

123

int mtw_mcu_radio(struct mtw_softc *, int, uint32_t);

sys/dev/usb/if_mtw.c

1268

static __inline uint32_t

sys/dev/usb/if_mtw.c

1269

b4inc(uint32_t b32, int8_t delta)

sys/dev/usb/if_mtw.c

1430

uint32_t reg;

sys/dev/usb/if_mtw.c

1435

reg |= (uint32_t)val << 16;

sys/dev/usb/if_mtw.c

1625

uint32_t sta[3];

sys/dev/usb/if_mtw.c

1754

uint32_t tmp;

sys/dev/usb/if_mtw.c

1789

uint32_t attr;

sys/dev/usb/if_mtw.c

1917

uint32_t attr;

sys/dev/usb/if_mtw.c

1947

uint32_t sta[3];

sys/dev/usb/if_mtw.c

195

uint32_t reg;

sys/dev/usb/if_mtw.c

196

uint32_t val;

sys/dev/usb/if_mtw.c

2048

uint32_t flags;

sys/dev/usb/if_mtw.c

2183

uint32_t dmalen;

sys/dev/usb/if_mtw.c

2197

if (__predict_false(xferlen < sizeof(uint32_t) +

sys/dev/usb/if_mtw.c

2206

dmalen = letoh32(*(uint32_t *)buf) & MTW_RXD_LEN;

sys/dev/usb/if_mtw.c

246

uint32_t ver;

sys/dev/usb/if_mtw.c

2542

uint32_t tmp;

sys/dev/usb/if_mtw.c

2590

uint32_t tmp;

sys/dev/usb/if_mtw.c

2668

uint32_t tmp;

sys/dev/usb/if_mtw.c

2683

uint32_t tmp;

sys/dev/usb/if_mtw.c

2717

uint32_t tmp;

sys/dev/usb/if_mtw.c

2729

uint32_t tmp;

sys/dev/usb/if_mtw.c

2873

uint32_t tmp;

sys/dev/usb/if_mtw.c

2935

uint32_t rfb, rfs;

sys/dev/usb/if_mtw.c

2993

uint32_t tmp;

sys/dev/usb/if_mtw.c

3025

uint32_t tmp;

sys/dev/usb/if_mtw.c

3065

uint32_t tmp;

sys/dev/usb/if_mtw.c

3111

uint32_t tmp;

sys/dev/usb/if_mtw.c

3312

uint32_t tmp;

sys/dev/usb/if_mtw.c

352

uint32_t tmp;

sys/dev/usb/if_mtw.c

660

mtw_ucode_write(struct mtw_softc *sc, const uint8_t *fw, uint32_t len,

sys/dev/usb/if_mtw.c

661

uint32_t offset)

sys/dev/usb/if_mtw.c

667

uint32_t blksz, sent, tmp, xferlen;

sys/dev/usb/if_mtw.c

740

uint32_t tmp, iofs, dofs;

sys/dev/usb/if_mtw.c

877

mtw_read(struct mtw_softc *sc, uint16_t reg, uint32_t *val)

sys/dev/usb/if_mtw.c

879

uint32_t tmp;

sys/dev/usb/if_mtw.c

892

mtw_read_cfg(struct mtw_softc *sc, uint16_t reg, uint32_t *val)

sys/dev/usb/if_mtw.c

895

uint32_t tmp;

sys/dev/usb/if_mtw.c

940

mtw_write(struct mtw_softc *sc, uint16_t reg, uint32_t val)

sys/dev/usb/if_mtw.c

950

mtw_write_cfg(struct mtw_softc *sc, uint16_t reg, uint32_t val)

sys/dev/usb/if_mtw.c

98

uint32_t, uint32_t);

sys/dev/usb/if_mtw.c

993

mtw_set_region_4(struct mtw_softc *sc, uint16_t reg, uint32_t val, int count)

sys/dev/usb/if_mtwvar.h

146

uint32_t ilm_len;

sys/dev/usb/if_mtwvar.h

147

uint32_t dlm_len;

sys/dev/usb/if_mtwvar.h

197

uint32_t txpow20mhz[5];

sys/dev/usb/if_mtwvar.h

198

uint32_t txpow40mhz_2ghz[5];

sys/dev/usb/if_mtwvar.h

199

uint32_t txpow40mhz_5ghz[5];

sys/dev/usb/if_mtwvar.h

203

uint32_t rf_pa_mode[2];

sys/dev/usb/if_mtwvar.h

21

(sizeof (uint32_t) + \

sys/dev/usb/if_mue.c

1012

uint32_t h = 0, hashtbl[MUE_DP_SEL_VHF_HASH_LEN], reg, rxfilt;

sys/dev/usb/if_mue.c

1060

uint32_t total_len;

sys/dev/usb/if_mue.c

111

void mue_dataport_write(struct mue_softc *, uint32_t, uint32_t,

sys/dev/usb/if_mue.c

112

uint32_t, uint32_t *);

sys/dev/usb/if_mue.c

173

uint32_t

sys/dev/usb/if_mue.c

174

mue_csr_read(struct mue_softc *sc, uint32_t reg)

sys/dev/usb/if_mue.c

201

mue_csr_write(struct mue_softc *sc, uint32_t reg, uint32_t aval)

sys/dev/usb/if_mue.c

267

uint32_t val;

sys/dev/usb/if_mue.c

323

uint32_t flow, threshold;

sys/dev/usb/if_mue.c

423

uint32_t val;

sys/dev/usb/if_mue.c

439

uint32_t byte = 0;

sys/dev/usb/if_mue.c

471

uint32_t val;

sys/dev/usb/if_mue.c

513

mue_dataport_write(struct mue_softc *sc, uint32_t sel, uint32_t addr,

sys/dev/usb/if_mue.c

514

uint32_t cnt, uint32_t *data)

sys/dev/usb/if_mue.c

556

uint32_t val;

sys/dev/usb/if_mue.c

672

uint32_t val, reg;

sys/dev/usb/if_mue.c

94

uint32_t mue_csr_read(struct mue_softc *, uint32_t);

sys/dev/usb/if_mue.c

95

int mue_csr_write(struct mue_softc *, uint32_t, uint32_t);

sys/dev/usb/if_muereg.h

205

uint32_t rx_cmd_a;

sys/dev/usb/if_muereg.h

209

uint32_t rx_cmd_b;

sys/dev/usb/if_muereg.h

214

uint32_t tx_cmd_a;

sys/dev/usb/if_muereg.h

218

uint32_t tx_cmd_b;

sys/dev/usb/if_otus.c

115

void otus_write(struct otus_softc *, uint32_t, uint32_t);

sys/dev/usb/if_otus.c

1282

uint32_t phyctl;

sys/dev/usb/if_otus.c

139

uint32_t otus_phy_get_def(struct otus_softc *, uint32_t);

sys/dev/usb/if_otus.c

146

void otus_get_delta_slope(uint32_t, uint32_t *, uint32_t *);

sys/dev/usb/if_otus.c

1535

uint32_t lo, hi;

sys/dev/usb/if_otus.c

1635

uint32_t slottime;

sys/dev/usb/if_otus.c

1706

uint32_t

sys/dev/usb/if_otus.c

1707

otus_phy_get_def(struct otus_softc *sc, uint32_t reg)

sys/dev/usb/if_otus.c

1725

uint32_t tmp, offset;

sys/dev/usb/if_otus.c

1815

const uint32_t *vals;

sys/dev/usb/if_otus.c

1899

otus_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa)

sys/dev/usb/if_otus.c

1902

uint32_t exp, man;

sys/dev/usb/if_otus.c

1925

const uint32_t *vals;

sys/dev/usb/if_otus.c

1926

uint32_t coeff, exp, man, tmp;

sys/dev/usb/if_otus.c

1993

cmd.freq = htole32((uint32_t)c->ic_freq * 1000);

sys/dev/usb/if_otus.c

2142

uint32_t uid;

sys/dev/usb/if_otus.c

2215

uint32_t state = sc->led_state;

sys/dev/usb/if_otus.c

256

uint32_t in, out;

sys/dev/usb/if_otus.c

414

otus_load_firmware(struct otus_softc *sc, const char *name, uint32_t addr)

sys/dev/usb/if_otus.c

858

otus_write(struct otus_softc *sc, uint32_t reg, uint32_t val)

sys/dev/usb/if_otus.c

917

uint32_t regs[8], reg;

sys/dev/usb/if_otus.c

97

uint32_t);

sys/dev/usb/if_otusreg.h

153

uint32_t phyctl;

sys/dev/usb/if_otusreg.h

250

uint32_t freq;

sys/dev/usb/if_otusreg.h

251

uint32_t dynht2040;

sys/dev/usb/if_otusreg.h

252

uint32_t htena;

sys/dev/usb/if_otusreg.h

253

uint32_t dsc_exp;

sys/dev/usb/if_otusreg.h

254

uint32_t dsc_man;

sys/dev/usb/if_otusreg.h

255

uint32_t dsc_shgi_exp;

sys/dev/usb/if_otusreg.h

256

uint32_t dsc_shgi_man;

sys/dev/usb/if_otusreg.h

257

uint32_t check_loop_count;

sys/dev/usb/if_otusreg.h

262

uint32_t status;

sys/dev/usb/if_otusreg.h

267

uint32_t nf[3]; /* Noisefloor. */

sys/dev/usb/if_otusreg.h

268

uint32_t nf_ext[3]; /* Noisefloor ext. */

sys/dev/usb/if_otusreg.h

291

uint32_t phy;

sys/dev/usb/if_otusreg.h

352

static const uint32_t ar5416_phy_vals_5ghz_20mhz[] = {

sys/dev/usb/if_otusreg.h

422

static const uint32_t ar5416_phy_vals_5ghz_40mhz[] = {

sys/dev/usb/if_otusreg.h

493

static const uint32_t ar5416_phy_vals_2ghz_40mhz[] = {

sys/dev/usb/if_otusreg.h

563

static const uint32_t ar5416_phy_vals_2ghz_20mhz[] = {

sys/dev/usb/if_otusreg.h

643

static const uint32_t ar5416_banks_vals_5ghz[] = {

sys/dev/usb/if_otusreg.h

660

static const uint32_t ar5416_banks_vals_2ghz[] = {

sys/dev/usb/if_otusreg.h

715

uint32_t binBuildNumber;

sys/dev/usb/if_otusreg.h

727

uint32_t antCtrlChain[AR5416_MAX_CHAINS];

sys/dev/usb/if_otusreg.h

728

uint32_t antCtrlCommon;

sys/dev/usb/if_otusreg.h

966

uint32_t led_state;

sys/dev/usb/if_otusreg.h

968

const uint32_t *phy_vals;

sys/dev/usb/if_otusreg.h

971

uint32_t reg;

sys/dev/usb/if_otusreg.h

972

uint32_t val;

sys/dev/usb/if_ral.c

1015

uint32_t flags = RAL_TX_NEWSEQ;

sys/dev/usb/if_ral.c

111

uint16_t ural_txtime(int, int, uint32_t);

sys/dev/usb/if_ral.c

114

uint32_t, int, int);

sys/dev/usb/if_ral.c

131

void ural_rf_write(struct ural_softc *, uint8_t, uint32_t);

sys/dev/usb/if_ral.c

1481

ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val)

sys/dev/usb/if_ral.c

1483

uint32_t tmp;

sys/dev/usb/if_ral.c

1596

uint32_t tmp;

sys/dev/usb/if_ral.c

169

static const uint32_t ural_rf2522_r2[] = RAL_RF2522_R2;

sys/dev/usb/if_ral.c

170

static const uint32_t ural_rf2523_r2[] = RAL_RF2523_R2;

sys/dev/usb/if_ral.c

171

static const uint32_t ural_rf2524_r2[] = RAL_RF2524_R2;

sys/dev/usb/if_ral.c

172

static const uint32_t ural_rf2525_r2[] = RAL_RF2525_R2;

sys/dev/usb/if_ral.c

173

static const uint32_t ural_rf2525_hi_r2[] = RAL_RF2525_HI_R2;

sys/dev/usb/if_ral.c

174

static const uint32_t ural_rf2525e_r2[] = RAL_RF2525E_R2;

sys/dev/usb/if_ral.c

175

static const uint32_t ural_rf2526_hi_r2[] = RAL_RF2526_HI_R2;

sys/dev/usb/if_ral.c

176

static const uint32_t ural_rf2526_r2[] = RAL_RF2526_R2;

sys/dev/usb/if_ral.c

863

ural_txtime(int len, int rate, uint32_t flags)

sys/dev/usb/if_ral.c

909

uint32_t flags, int len, int rate)

sys/dev/usb/if_ralreg.h

149

uint32_t flags;

sys/dev/usb/if_ralreg.h

176

uint32_t iv;

sys/dev/usb/if_ralreg.h

177

uint32_t eiv;

sys/dev/usb/if_ralreg.h

181

uint32_t flags;

sys/dev/usb/if_ralreg.h

190

uint32_t iv;

sys/dev/usb/if_ralreg.h

191

uint32_t eiv;

sys/dev/usb/if_ralvar.h

110

uint32_t rf_regs[4];

sys/dev/usb/if_ralvar.h

83

uint32_t asic_rev;

sys/dev/usb/if_rsu.c

1068

uint32_t zero = 0; /* :-) */

sys/dev/usb/if_rsu.c

1085

uint32_t pktlen, ieslen;

sys/dev/usb/if_rsu.c

1182

sc->scan_pass, letoh32(*(uint32_t *)buf)));

sys/dev/usb/if_rsu.c

1282

uint32_t rxdw0, rxdw3;

sys/dev/usb/if_rsu.c

132

void rsu_write_4(struct rsu_softc *, uint16_t, uint32_t);

sys/dev/usb/if_rsu.c

137

uint32_t rsu_read_4(struct rsu_softc *, uint16_t);

sys/dev/usb/if_rsu.c

138

int rsu_fw_iocmd(struct rsu_softc *, uint32_t);

sys/dev/usb/if_rsu.c

1394

uint32_t rxdw0;

sys/dev/usb/if_rsu.c

1744

uint32_t reg;

sys/dev/usb/if_rsu.c

1826

uint32_t reg;

sys/dev/usb/if_rsu.c

2012

uint32_t reg;

sys/dev/usb/if_rsu.c

554

rsu_write_4(struct rsu_softc *sc, uint16_t addr, uint32_t val)

sys/dev/usb/if_rsu.c

594

uint32_t

sys/dev/usb/if_rsu.c

597

uint32_t val;

sys/dev/usb/if_rsu.c

605

rsu_fw_iocmd(struct rsu_softc *sc, uint32_t iocmd)

sys/dev/usb/if_rsu.c

622

uint32_t reg;

sys/dev/usb/if_rsu.c

646

uint32_t reg;

sys/dev/usb/if_rsu.c

773

uint32_t reg;

sys/dev/usb/if_rsureg.h

180

uint32_t regulatory;

sys/dev/usb/if_rsureg.h

198

uint32_t reserved1;

sys/dev/usb/if_rsureg.h

219

uint32_t reserved4;

sys/dev/usb/if_rsureg.h

225

uint32_t dmemsz;

sys/dev/usb/if_rsureg.h

226

uint32_t imemsz;

sys/dev/usb/if_rsureg.h

227

uint32_t sramsz;

sys/dev/usb/if_rsureg.h

228

uint32_t privsz;

sys/dev/usb/if_rsureg.h

231

uint32_t svnrev;

sys/dev/usb/if_rsureg.h

246

uint32_t reserved;

sys/dev/usb/if_rsureg.h

355

uint32_t active;

sys/dev/usb/if_rsureg.h

356

uint32_t limit;

sys/dev/usb/if_rsureg.h

357

uint32_t ssidlen;

sys/dev/usb/if_rsureg.h

389

uint32_t ssidlen;

sys/dev/usb/if_rsureg.h

395

uint32_t len;

sys/dev/usb/if_rsureg.h

396

uint32_t hoppattern;

sys/dev/usb/if_rsureg.h

397

uint32_t hopset;

sys/dev/usb/if_rsureg.h

398

uint32_t dwelltime;

sys/dev/usb/if_rsureg.h

403

uint32_t len;

sys/dev/usb/if_rsureg.h

404

uint32_t bintval;

sys/dev/usb/if_rsureg.h

405

uint32_t atim;

sys/dev/usb/if_rsureg.h

406

uint32_t dsconfig;

sys/dev/usb/if_rsureg.h

412

uint32_t len;

sys/dev/usb/if_rsureg.h

416

uint32_t privacy;

sys/dev/usb/if_rsureg.h

418

uint32_t networktype;

sys/dev/usb/if_rsureg.h

426

uint32_t inframode;

sys/dev/usb/if_rsureg.h

434

uint32_t ieslen;

sys/dev/usb/if_rsureg.h

476

uint32_t next;

sys/dev/usb/if_rsureg.h

477

uint32_t prev;

sys/dev/usb/if_rsureg.h

478

uint32_t networktype;

sys/dev/usb/if_rsureg.h

479

uint32_t fixed;

sys/dev/usb/if_rsureg.h

480

uint32_t lastscanned;

sys/dev/usb/if_rsureg.h

481

uint32_t associd;

sys/dev/usb/if_rsureg.h

482

uint32_t join_res;

sys/dev/usb/if_rsureg.h

490

uint32_t rxdw0;

sys/dev/usb/if_rsureg.h

501

uint32_t rxdw1;

sys/dev/usb/if_rsureg.h

504

uint32_t rxdw2;

sys/dev/usb/if_rsureg.h

510

uint32_t rxdw3;

sys/dev/usb/if_rsureg.h

518

uint32_t rxdw4;

sys/dev/usb/if_rsureg.h

519

uint32_t rxdw5;

sys/dev/usb/if_rsureg.h

524

uint32_t phydw0;

sys/dev/usb/if_rsureg.h

525

uint32_t phydw1;

sys/dev/usb/if_rsureg.h

526

uint32_t phydw2;

sys/dev/usb/if_rsureg.h

527

uint32_t phydw3;

sys/dev/usb/if_rsureg.h

528

uint32_t phydw4;

sys/dev/usb/if_rsureg.h

529

uint32_t phydw5;

sys/dev/usb/if_rsureg.h

530

uint32_t phydw6;

sys/dev/usb/if_rsureg.h

531

uint32_t phydw7;

sys/dev/usb/if_rsureg.h

543

uint32_t txdw0;

sys/dev/usb/if_rsureg.h

555

uint32_t txdw1;

sys/dev/usb/if_rsureg.h

574

uint32_t txdw2;

sys/dev/usb/if_rsureg.h

579

uint32_t txdw3;

sys/dev/usb/if_rsureg.h

585

uint32_t txdw4;

sys/dev/usb/if_rsureg.h

588

uint32_t txdw5;

sys/dev/usb/if_rum.c

1032

uint32_t flags = 0;

sys/dev/usb/if_rum.c

1378

uint32_t

sys/dev/usb/if_rum.c

1381

uint32_t val;

sys/dev/usb/if_rum.c

1408

rum_write(struct rum_softc *sc, uint16_t reg, uint32_t val)

sys/dev/usb/if_rum.c

141

uint16_t rum_txtime(int, int, uint32_t);

sys/dev/usb/if_rum.c

1410

uint32_t tmp = htole32(val);

sys/dev/usb/if_rum.c

144

uint32_t, uint16_t, int, int);

sys/dev/usb/if_rum.c

1442

uint32_t tmp;

sys/dev/usb/if_rum.c

1461

uint32_t val;

sys/dev/usb/if_rum.c

1488

rum_rf_write(struct rum_softc *sc, uint8_t reg, uint32_t val)

sys/dev/usb/if_rum.c

1490

uint32_t tmp;

sys/dev/usb/if_rum.c

151

uint32_t rum_read(struct rum_softc *, uint16_t);

sys/dev/usb/if_rum.c

1516

uint32_t tmp;

sys/dev/usb/if_rum.c

153

void rum_write(struct rum_softc *, uint16_t, uint32_t);

sys/dev/usb/if_rum.c

1541

uint32_t tmp;

sys/dev/usb/if_rum.c

1556

uint32_t tmp;

sys/dev/usb/if_rum.c

157

void rum_rf_write(struct rum_softc *, uint8_t, uint32_t);

sys/dev/usb/if_rum.c

1593

uint32_t tmp;

sys/dev/usb/if_rum.c

1713

uint32_t tmp;

sys/dev/usb/if_rum.c

1745

uint32_t tmp;

sys/dev/usb/if_rum.c

1760

uint32_t tmp;

sys/dev/usb/if_rum.c

1772

uint32_t tmp;

sys/dev/usb/if_rum.c

1785

uint32_t tmp;

sys/dev/usb/if_rum.c

187

uint32_t reg;

sys/dev/usb/if_rum.c

188

uint32_t val;

sys/dev/usb/if_rum.c

1923

uint32_t tmp;

sys/dev/usb/if_rum.c

202

uint32_t r1, r2, r3, r4;

sys/dev/usb/if_rum.c

2064

uint32_t tmp;

sys/dev/usb/if_rum.c

266

uint32_t tmp;

sys/dev/usb/if_rum.c

620

uint32_t tmp;

sys/dev/usb/if_rum.c

932

rum_txtime(int len, int rate, uint32_t flags)

sys/dev/usb/if_rum.c

978

uint32_t flags, uint16_t xflags, int len, int rate)

sys/dev/usb/if_rumreg.h

167

uint32_t flags;

sys/dev/usb/if_rumreg.h

193

uint32_t iv;

sys/dev/usb/if_rumreg.h

194

uint32_t eiv;

sys/dev/usb/if_rumreg.h

205

uint32_t flags;

sys/dev/usb/if_rumreg.h

215

uint32_t iv;

sys/dev/usb/if_rumreg.h

216

uint32_t eiv;

sys/dev/usb/if_rumreg.h

217

uint32_t reserved2[2];

sys/dev/usb/if_rumvar.h

111

uint32_t sta[6];

sys/dev/usb/if_rumvar.h

112

uint32_t rf_regs[4];

sys/dev/usb/if_run.c

1035

uint32_t tmp;

sys/dev/usb/if_run.c

1105

run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val)

sys/dev/usb/if_run.c

1107

uint32_t tmp;

sys/dev/usb/if_run.c

1128

uint32_t tmp;

sys/dev/usb/if_run.c

1160

uint32_t tmp;

sys/dev/usb/if_run.c

1179

uint32_t tmp;

sys/dev/usb/if_run.c

1211

uint32_t tmp;

sys/dev/usb/if_run.c

1233

uint32_t tmp;

sys/dev/usb/if_run.c

1255

static __inline uint32_t

sys/dev/usb/if_run.c

1256

b4inc(uint32_t b32, int8_t delta)

sys/dev/usb/if_run.c

1417

uint32_t tmp;

sys/dev/usb/if_run.c

1567

uint32_t reg;

sys/dev/usb/if_run.c

1572

reg |= (uint32_t)val << 16;

sys/dev/usb/if_run.c

1786

uint32_t tmp, sta[3];

sys/dev/usb/if_run.c

1937

uint32_t attr;

sys/dev/usb/if_run.c

2049

uint32_t attr;

sys/dev/usb/if_run.c

2079

uint32_t sta[3];

sys/dev/usb/if_run.c

2183

uint32_t flags;

sys/dev/usb/if_run.c

2197

rxwisize += sizeof(uint32_t);

sys/dev/usb/if_run.c

2323

uint32_t dmalen;

sys/dev/usb/if_run.c

2331

rxwisize += sizeof(uint32_t);

sys/dev/usb/if_run.c

2343

if (__predict_false(xferlen < sizeof (uint32_t) + rxwisize +

sys/dev/usb/if_run.c

2352

dmalen = letoh32(*(uint32_t *)buf) & 0xffff;

sys/dev/usb/if_run.c

2363

run_rx_frame(sc, buf + sizeof (uint32_t), dmalen, &ml);

sys/dev/usb/if_run.c

2452

txwisize += sizeof(uint32_t);

sys/dev/usb/if_run.c

2756

uint32_t tmp;

sys/dev/usb/if_run.c

2901

uint32_t r2, r3, r4;

sys/dev/usb/if_run.c

3023

uint32_t tmp;

sys/dev/usb/if_run.c

335

int run_read(struct run_softc *, uint16_t, uint32_t *);

sys/dev/usb/if_run.c

339

int run_write(struct run_softc *, uint16_t, uint32_t);

sys/dev/usb/if_run.c

342

int run_set_region_4(struct run_softc *, uint16_t, uint32_t, int);

sys/dev/usb/if_run.c

3446

uint32_t tmp;

sys/dev/usb/if_run.c

346

int run_rt2870_rf_write(struct run_softc *, uint8_t, uint32_t);

sys/dev/usb/if_run.c

3599

uint32_t tmp;

sys/dev/usb/if_run.c

3672

uint32_t tmp;

sys/dev/usb/if_run.c

3710

uint32_t tmp;

sys/dev/usb/if_run.c

3769

uint32_t tmp;

sys/dev/usb/if_run.c

3915

uint32_t tmp;

sys/dev/usb/if_run.c

4056

uint32_t tmp;

sys/dev/usb/if_run.c

4105

uint32_t tmp;

sys/dev/usb/if_run.c

432

uint32_t reg;

sys/dev/usb/if_run.c

433

uint32_t val;

sys/dev/usb/if_run.c

4430

uint32_t tmp;

sys/dev/usb/if_run.c

4491

uint32_t tmp;

sys/dev/usb/if_run.c

466

uint32_t r1, r2, r3, r4;

sys/dev/usb/if_run.c

4740

uint32_t tmp;

sys/dev/usb/if_run.c

538

uint32_t ver;

sys/dev/usb/if_run.c

770

txwisize += sizeof(uint32_t);

sys/dev/usb/if_run.c

826

uint32_t tmp;

sys/dev/usb/if_run.c

901

run_read(struct run_softc *sc, uint16_t reg, uint32_t *val)

sys/dev/usb/if_run.c

903

uint32_t tmp;

sys/dev/usb/if_run.c

941

run_write(struct run_softc *sc, uint16_t reg, uint32_t val)

sys/dev/usb/if_run.c

977

run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count)

sys/dev/usb/if_run.c

990

uint32_t tmp;

sys/dev/usb/if_runvar.h

176

uint32_t txpow20mhz[5];

sys/dev/usb/if_runvar.h

177

uint32_t txpow40mhz_2ghz[5];

sys/dev/usb/if_runvar.h

178

uint32_t txpow40mhz_5ghz[5];

sys/dev/usb/if_runvar.h

22

(sizeof (uint32_t) + \

sys/dev/usb/if_smsc.c

1168

uint32_t total_len;

sys/dev/usb/if_smsc.c

1173

uint32_t rxhdr;

sys/dev/usb/if_smsc.c

1365

uint32_t txhdr;

sys/dev/usb/if_smsc.c

1366

uint32_t frm_len = 0;

sys/dev/usb/if_smsc.c

164

int smsc_read_reg(struct smsc_softc *, uint32_t, uint32_t *);

sys/dev/usb/if_smsc.c

165

int smsc_write_reg(struct smsc_softc *, uint32_t, uint32_t);

sys/dev/usb/if_smsc.c

166

int smsc_wait_for_bits(struct smsc_softc *, uint32_t, uint32_t);

sys/dev/usb/if_smsc.c

220

smsc_read_reg(struct smsc_softc *sc, uint32_t off, uint32_t *data)

sys/dev/usb/if_smsc.c

223

uint32_t buf;

sys/dev/usb/if_smsc.c

242

smsc_write_reg(struct smsc_softc *sc, uint32_t off, uint32_t data)

sys/dev/usb/if_smsc.c

245

uint32_t buf;

sys/dev/usb/if_smsc.c

264

smsc_wait_for_bits(struct smsc_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/usb/if_smsc.c

266

uint32_t val;

sys/dev/usb/if_smsc.c

284

uint32_t addr;

sys/dev/usb/if_smsc.c

285

uint32_t val = 0;

sys/dev/usb/if_smsc.c

310

uint32_t addr;

sys/dev/usb/if_smsc.c

339

uint32_t flow;

sys/dev/usb/if_smsc.c

340

uint32_t afc_cfg;

sys/dev/usb/if_smsc.c

437

static inline uint32_t

sys/dev/usb/if_smsc.c

450

uint32_t hashtbl[2] = { 0, 0 };

sys/dev/usb/if_smsc.c

451

uint32_t hash;

sys/dev/usb/if_smsc.c

494

uint32_t val;

sys/dev/usb/if_smsc.c

533

uint32_t val;

sys/dev/usb/if_smsc.c

754

uint32_t reg_val;

sys/dev/usb/if_smsc.c

872

smsc_write_reg(sc, SMSC_VLAN1, (uint32_t)ETHERTYPE_VLAN);

sys/dev/usb/if_smsc.c

962

uint32_t mac_h, mac_l;

sys/dev/usb/if_smscreg.h

279

uint32_t sc_mac_csr;

sys/dev/usb/if_smscreg.h

280

uint32_t sc_rev_id;

sys/dev/usb/if_smscreg.h

298

uint32_t sc_flags;

sys/dev/usb/if_uaq.c

1086

uint32_t total_len;

sys/dev/usb/if_uaq.c

1356

uint32_t maxlen)

sys/dev/usb/if_uaq.c

214

uint32_t uc_cnt;

sys/dev/usb/if_uaq.c

215

uint32_t uc_buflen;

sys/dev/usb/if_uaq.c

216

uint32_t uc_bufmax;

sys/dev/usb/if_uaq.c

245

uint32_t sc_phy_cfg;

sys/dev/usb/if_uaq.c

269

uint32_t uaq_read_4(struct uaq_softc *, uint8_t, uint16_t, uint16_t);

sys/dev/usb/if_uaq.c

271

uint32_t);

sys/dev/usb/if_uaq.c

273

uint32_t);

sys/dev/usb/if_uaq.c

275

uint32_t);

sys/dev/usb/if_uaq.c

285

uint32_t, int);

sys/dev/usb/if_uaq.c

298

uint32_t);

sys/dev/usb/if_uaq.c

376

uint32_t

sys/dev/usb/if_uaq.c

379

uint32_t val;

sys/dev/usb/if_uaq.c

389

uint32_t val)

sys/dev/usb/if_uaq.c

401

uint32_t val)

sys/dev/usb/if_uaq.c

413

uint32_t val)

sys/dev/usb/if_uaq.c

651

uint32_t hash;

sys/dev/usb/if_uaq.c

844

uint32_t bufsize, int listlen)

sys/dev/usb/if_uath.c

1007

uath_write_reg(struct uath_softc *sc, uint32_t reg, uint32_t val)

sys/dev/usb/if_uath.c

1014

*(uint32_t *)write.data = htobe32(val);

sys/dev/usb/if_uath.c

1017

3 * sizeof (uint32_t), 0);

sys/dev/usb/if_uath.c

1026

uath_write_multi(struct uath_softc *sc, uint32_t reg, const void *data,

sys/dev/usb/if_uath.c

1038

(len == 0) ? sizeof (uint32_t) : 2 * sizeof (uint32_t) + len, 0);

sys/dev/usb/if_uath.c

1047

uath_read_reg(struct uath_softc *sc, uint32_t reg, uint32_t *val)

sys/dev/usb/if_uath.c

1060

*val = betoh32(*(uint32_t *)read.data);

sys/dev/usb/if_uath.c

1065

uath_read_eeprom(struct uath_softc *sc, uint32_t reg, void *odata)

sys/dev/usb/if_uath.c

1079

bcopy(read.data, odata, (len == 0) ? sizeof (uint32_t) : len);

sys/dev/usb/if_uath.c

1158

uint32_t hdr;

sys/dev/usb/if_uath.c

1179

hdr = betoh32(*(uint32_t *)data->buf);

sys/dev/usb/if_uath.c

1213

m->m_data = data->buf + sizeof (uint32_t);

sys/dev/usb/if_uath.c

1284

*(uint32_t *)data->buf = UATH_MAKECTL(1, sizeof (struct uath_tx_desc));

sys/dev/usb/if_uath.c

1285

desc = (struct uath_tx_desc *)(data->buf + sizeof (uint32_t));

sys/dev/usb/if_uath.c

1292

sizeof (uint32_t) + sizeof (struct uath_tx_desc), USBD_NO_COPY |

sys/dev/usb/if_uath.c

1350

desc = (struct uath_tx_desc *)(data->buf + sizeof (uint32_t));

sys/dev/usb/if_uath.c

1374

xferlen = sizeof (uint32_t) + sizeof (struct uath_tx_desc) + paylen;

sys/dev/usb/if_uath.c

1379

uint32_t iv;

sys/dev/usb/if_uath.c

140

int uath_cmd(struct uath_softc *, uint32_t, const void *, int, void *,

sys/dev/usb/if_uath.c

1408

*(uint32_t *)data->buf = UATH_MAKECTL(1, xferlen - sizeof (uint32_t));

sys/dev/usb/if_uath.c

142

int uath_cmd_write(struct uath_softc *, uint32_t, const void *, int, int);

sys/dev/usb/if_uath.c

143

int uath_cmd_read(struct uath_softc *, uint32_t, const void *, int, void *,

sys/dev/usb/if_uath.c

145

int uath_write_reg(struct uath_softc *, uint32_t, uint32_t);

sys/dev/usb/if_uath.c

146

int uath_write_multi(struct uath_softc *, uint32_t, const void *, int);

sys/dev/usb/if_uath.c

147

int uath_read_reg(struct uath_softc *, uint32_t, uint32_t *);

sys/dev/usb/if_uath.c

148

int uath_read_eeprom(struct uath_softc *, uint32_t, void *);

sys/dev/usb/if_uath.c

1567

uint32_t tmp;

sys/dev/usb/if_uath.c

1594

uint32_t reg, val;

sys/dev/usb/if_uath.c

1631

const uint32_t qid = htobe32(UATH_AC_TO_QID(ac));

sys/dev/usb/if_uath.c

166

int uath_set_rxfilter(struct uath_softc *, uint32_t, uint32_t);

sys/dev/usb/if_uath.c

1753

uath_set_rxfilter(struct uath_softc *sc, uint32_t filter, uint32_t flags)

sys/dev/usb/if_uath.c

1782

uint32_t val;

sys/dev/usb/if_uath.c

1821

uint32_t val;

sys/dev/usb/if_uath.c

1928

uint32_t val;

sys/dev/usb/if_uath.c

835

uint32_t val;

sys/dev/usb/if_uath.c

926

uath_cmd(struct uath_softc *sc, uint32_t code, const void *idata, int ilen,

sys/dev/usb/if_uath.c

991

uath_cmd_write(struct uath_softc *sc, uint32_t code, const void *data, int len,

sys/dev/usb/if_uath.c

999

uath_cmd_read(struct uath_softc *sc, uint32_t code, const void *idata,

sys/dev/usb/if_uathreg.h

103

uint32_t flags;

sys/dev/usb/if_uathreg.h

106

uint32_t paylen;

sys/dev/usb/if_uathreg.h

111

uint32_t magic1;

sys/dev/usb/if_uathreg.h

112

uint32_t magic2;

sys/dev/usb/if_uathreg.h

113

uint32_t magic3;

sys/dev/usb/if_uathreg.h

114

uint32_t magic4;

sys/dev/usb/if_uathreg.h

119

uint32_t len;

sys/dev/usb/if_uathreg.h

125

uint32_t reg;

sys/dev/usb/if_uathreg.h

126

uint32_t len;

sys/dev/usb/if_uathreg.h

132

uint32_t code;

sys/dev/usb/if_uathreg.h

133

uint32_t reserved;

sys/dev/usb/if_uathreg.h

134

uint32_t size;

sys/dev/usb/if_uathreg.h

140

uint32_t magic1;

sys/dev/usb/if_uathreg.h

141

uint32_t magic2;

sys/dev/usb/if_uathreg.h

142

uint32_t magic3;

sys/dev/usb/if_uathreg.h

147

uint32_t which;

sys/dev/usb/if_uathreg.h

151

uint32_t state;

sys/dev/usb/if_uathreg.h

158

uint32_t which;

sys/dev/usb/if_uathreg.h

159

uint32_t rate;

sys/dev/usb/if_uathreg.h

160

uint32_t mode;

sys/dev/usb/if_uathreg.h

165

uint32_t keyidx;

sys/dev/usb/if_uathreg.h

168

uint32_t magic1;

sys/dev/usb/if_uathreg.h

169

uint32_t size;

sys/dev/usb/if_uathreg.h

170

uint32_t reserved1;

sys/dev/usb/if_uathreg.h

171

uint32_t mask;

sys/dev/usb/if_uathreg.h

174

uint32_t flags;

sys/dev/usb/if_uathreg.h

175

uint32_t reserved3[2];

sys/dev/usb/if_uathreg.h

183

uint32_t magic1;

sys/dev/usb/if_uathreg.h

184

uint32_t reserved;

sys/dev/usb/if_uathreg.h

185

uint32_t size;

sys/dev/usb/if_uathreg.h

193

uint32_t flags;

sys/dev/usb/if_uathreg.h

194

uint32_t freq;

sys/dev/usb/if_uathreg.h

195

uint32_t magic1;

sys/dev/usb/if_uathreg.h

196

uint32_t magic2;

sys/dev/usb/if_uathreg.h

197

uint32_t reserved1;

sys/dev/usb/if_uathreg.h

198

uint32_t magic3;

sys/dev/usb/if_uathreg.h

199

uint32_t reserved2;

sys/dev/usb/if_uathreg.h

204

uint32_t qid;

sys/dev/usb/if_uathreg.h

207

uint32_t size;

sys/dev/usb/if_uathreg.h

208

uint32_t ac;

sys/dev/usb/if_uathreg.h

209

uint32_t aifsn;

sys/dev/usb/if_uathreg.h

210

uint32_t logcwmin;

sys/dev/usb/if_uathreg.h

211

uint32_t logcwmax;

sys/dev/usb/if_uathreg.h

212

uint32_t txop;

sys/dev/usb/if_uathreg.h

213

uint32_t acm;

sys/dev/usb/if_uathreg.h

214

uint32_t magic1;

sys/dev/usb/if_uathreg.h

215

uint32_t magic2;

sys/dev/usb/if_uathreg.h

220

uint32_t magic1;

sys/dev/usb/if_uathreg.h

221

uint32_t magic2;

sys/dev/usb/if_uathreg.h

226

uint32_t filter;

sys/dev/usb/if_uathreg.h

227

uint32_t flags;

sys/dev/usb/if_uathreg.h

232

uint32_t reserved1;

sys/dev/usb/if_uathreg.h

233

uint32_t flags1;

sys/dev/usb/if_uathreg.h

234

uint32_t flags2;

sys/dev/usb/if_uathreg.h

235

uint32_t reserved2;

sys/dev/usb/if_uathreg.h

236

uint32_t len;

sys/dev/usb/if_uathreg.h

245

(sizeof (uint32_t) + sizeof (struct uath_tx_desc) + IEEE80211_MAX_LEN)

sys/dev/usb/if_uathreg.h

248

(((sizeof (uint32_t) + sizeof (struct ieee80211_frame_min) + \

sys/dev/usb/if_uathreg.h

25

uint32_t flags;

sys/dev/usb/if_uathreg.h

28

uint32_t len;

sys/dev/usb/if_uathreg.h

31

uint32_t total;

sys/dev/usb/if_uathreg.h

32

uint32_t remain;

sys/dev/usb/if_uathreg.h

33

uint32_t rxtotal;

sys/dev/usb/if_uathreg.h

34

uint32_t pad[123];

sys/dev/usb/if_uathreg.h

41

uint32_t len;

sys/dev/usb/if_uathreg.h

42

uint32_t code;

sys/dev/usb/if_uathreg.h

76

uint32_t priv; /* driver private data */

sys/dev/usb/if_uathreg.h

77

uint32_t magic;

sys/dev/usb/if_uathreg.h

78

uint32_t reserved2[4];

sys/dev/usb/if_uathreg.h

82

uint32_t len;

sys/dev/usb/if_uathreg.h

83

uint32_t reserved1[8];

sys/dev/usb/if_uathreg.h

84

uint32_t rssi;

sys/dev/usb/if_uathreg.h

85

uint32_t freq;

sys/dev/usb/if_uathreg.h

86

uint32_t reserved2[5];

sys/dev/usb/if_uathreg.h

92

uint32_t len;

sys/dev/usb/if_uathreg.h

93

uint32_t priv; /* driver private data */

sys/dev/usb/if_uathreg.h

94

uint32_t type;

sys/dev/usb/if_uathreg.h

98

uint32_t magic;

sys/dev/usb/if_uathreg.h

99

uint32_t dest;

sys/dev/usb/if_umb.c

1297

uint32_t type;

sys/dev/usb/if_umb.c

1298

uint32_t tid;

sys/dev/usb/if_umb.c

1379

uint32_t infolen;

sys/dev/usb/if_umb.c

1380

uint32_t cid;

sys/dev/usb/if_umb.c

1411

uint32_t status;

sys/dev/usb/if_umb.c

1433

uint32_t status;

sys/dev/usb/if_umb.c

1445

umb_getinfobuf(void *in, int inlen, uint32_t offs, uint32_t sz,

sys/dev/usb/if_umb.c

1457

uint32_t *offsmember, uint32_t *sizemember)

sys/dev/usb/if_umb.c

1462

*sizemember = htole32((uint32_t)slen);

sys/dev/usb/if_umb.c

1464

*offsmember = htole32((uint32_t)*offs);

sys/dev/usb/if_umb.c

1467

*offs += umb_padding(buf, bufsz, *offs, sizeof (uint32_t), 0);

sys/dev/usb/if_umb.c

1599

uint32_t attempts_left;

sys/dev/usb/if_umb.c

180

void umb_ctrl_msg(struct umb_softc *, uint32_t, void *, int);

sys/dev/usb/if_umb.c

200

void umb_decode_cid(struct umb_softc *, uint32_t, void *, int);

sys/dev/usb/if_umb.c

2049

uint32_t avail_v4;

sys/dev/usb/if_umb.c

2050

uint32_t val;

sys/dev/usb/if_umb.c

2059

uint32_t avail_v6;

sys/dev/usb/if_umb.c

227

uint32_t umb_session_id = 0;

sys/dev/usb/if_umb.c

2434

uint32_t len;

sys/dev/usb/if_umb.c

2441

uint32_t hsig, psig;

sys/dev/usb/if_umb.c

2442

uint32_t ptrlen, dgentryoff;

sys/dev/usb/if_umb.c

2553

m = m_devget(dp, (int)dlen, sizeof(uint32_t));

sys/dev/usb/if_umb.c

2630

umb_ctrl_msg(struct umb_softc *sc, uint32_t req, void *data, int len)

sys/dev/usb/if_umb.c

2633

uint32_t tid;

sys/dev/usb/if_umb.c

2748

uint32_t classes;

sys/dev/usb/if_umb.c

2919

uint32_t status;

sys/dev/usb/if_umb.c

2920

uint32_t cid;

sys/dev/usb/if_umb.c

2921

uint32_t infolen;

sys/dev/usb/if_umb.c

2992

umb_decode_cid(struct umb_softc *sc, uint32_t cid, void *data, int len)

sys/dev/usb/if_umb.c

3044

uint32_t val;

sys/dev/usb/if_umb.c

3055

#define UMB_GET32(p) ((uint32_t)*p | (uint32_t)*(p + 1) << 8 | \

sys/dev/usb/if_umb.c

3056

(uint32_t)*(p + 2) << 16 |(uint32_t)*(p + 3) << 24)

sys/dev/usb/if_umb.c

368

uint32_t maxpktlen;

sys/dev/usb/if_umb.c

649

bpfattach(&ifp->if_bpf, ifp, DLT_LOOP, sizeof(uint32_t));

sys/dev/usb/if_umb.c

735

sc->sc_align = sizeof (uint32_t);

sys/dev/usb/if_umb.c

738

sc->sc_ndp_div = sizeof (uint32_t);

sys/dev/usb/if_umb.c

747

sc->sc_align = sc->sc_ndp_div = sizeof (uint32_t);

sys/dev/usb/if_umb.h

259

uint32_t preferredclasses;

sys/dev/usb/if_umb.h

279

uint32_t supportedclasses; /* what the hw supports */

sys/dev/usb/if_umb.h

280

uint32_t preferredclasses; /* what the user prefers */

sys/dev/usb/if_umb.h

281

uint32_t highestclass; /* what the network offers */

sys/dev/usb/if_umb.h

282

uint32_t cellclass;

sys/dev/usb/if_umb.h

342

uint32_t sc_maxpktlen;

sys/dev/usb/if_umb.h

355

uint32_t sc_flags;

sys/dev/usb/if_umb.h

384

uint32_t sc_tx_seq;

sys/dev/usb/if_umb.h

386

uint32_t sc_tid;

sys/dev/usb/if_upgt.c

130

struct usbd_pipe *, uint32_t *, int);

sys/dev/usb/if_upgt.c

133

uint32_t upgt_crc32_le(const void *, size_t);

sys/dev/usb/if_upgt.c

134

uint32_t upgt_chksum_le(const uint32_t *, size_t);

sys/dev/usb/if_upgt.c

1436

uint32_t addr;

sys/dev/usb/if_upgt.c

1535

mem->chksum = upgt_chksum_le((uint32_t *)txdesc,

sys/dev/usb/if_upgt.c

1932

mem->chksum = upgt_chksum_le((uint32_t *)filter,

sys/dev/usb/if_upgt.c

1992

mem->chksum = upgt_chksum_le((uint32_t *)chan,

sys/dev/usb/if_upgt.c

2067

mem->chksum = upgt_chksum_le((uint32_t *)led,

sys/dev/usb/if_upgt.c

2117

mem->chksum = upgt_chksum_le((uint32_t *)stats,

sys/dev/usb/if_upgt.c

2257

struct usbd_pipe *pipeh, uint32_t *size, int flags)

sys/dev/usb/if_upgt.c

2288

uint32_t

sys/dev/usb/if_upgt.c

2291

uint32_t crc;

sys/dev/usb/if_upgt.c

2305

uint32_t

sys/dev/usb/if_upgt.c

2306

upgt_chksum_le(const uint32_t *buf, size_t size)

sys/dev/usb/if_upgt.c

2309

uint32_t crc = 0;

sys/dev/usb/if_upgt.c

2311

for (i = 0; i < size; i += sizeof(uint32_t)) {

sys/dev/usb/if_upgt.c

552

uint32_t

sys/dev/usb/if_upgt.c

568

upgt_mem_free(struct upgt_softc *sc, uint32_t addr)

sys/dev/usb/if_upgt.c

618

uint32_t bra_option_type, bra_option_len;

sys/dev/usb/if_upgt.c

619

uint32_t *uc;

sys/dev/usb/if_upgt.c

626

uc = (uint32_t *)(sc->sc_fw + offset);

sys/dev/usb/if_upgt.c

631

uc = (uint32_t *)(sc->sc_fw + offset);

sys/dev/usb/if_upgt.c

736

uint32_t crc32;

sys/dev/usb/if_upgt.c

755

sizeof(uint32_t));

sys/dev/usb/if_upgt.c

787

*((uint32_t *)(data_cmd->buf) ) = crc32;

sys/dev/usb/if_upgt.c

86

uint32_t upgt_mem_alloc(struct upgt_softc *);

sys/dev/usb/if_upgt.c

87

void upgt_mem_free(struct upgt_softc *, uint32_t);

sys/dev/usb/if_upgt.c

893

mem->chksum = upgt_chksum_le((uint32_t *)eeprom,

sys/dev/usb/if_upgtvar.h

108

uint32_t type;

sys/dev/usb/if_upgtvar.h

109

uint32_t len;

sys/dev/usb/if_upgtvar.h

114

uint32_t unknown1;

sys/dev/usb/if_upgtvar.h

115

uint32_t memaddr_space_start;

sys/dev/usb/if_upgtvar.h

116

uint32_t memaddr_space_end;

sys/dev/usb/if_upgtvar.h

117

uint32_t unknown2;

sys/dev/usb/if_upgtvar.h

118

uint32_t unknown3;

sys/dev/usb/if_upgtvar.h

126

uint32_t startaddr;

sys/dev/usb/if_upgtvar.h

127

uint32_t len;

sys/dev/usb/if_upgtvar.h

128

uint32_t crc;

sys/dev/usb/if_upgtvar.h

139

uint32_t magic;

sys/dev/usb/if_upgtvar.h

142

uint32_t pad2;

sys/dev/usb/if_upgtvar.h

166

uint32_t pad1;

sys/dev/usb/if_upgtvar.h

198

uint32_t addr;

sys/dev/usb/if_upgtvar.h

199

uint32_t chksum;

sys/dev/usb/if_upgtvar.h

228

uint32_t reqid;

sys/dev/usb/if_upgtvar.h

265

uint32_t rxaddr;

sys/dev/usb/if_upgtvar.h

267

uint32_t rxhw;

sys/dev/usb/if_upgtvar.h

269

uint32_t unknown4;

sys/dev/usb/if_upgtvar.h

306

uint32_t pad2;

sys/dev/usb/if_upgtvar.h

337

uint32_t timestamp;

sys/dev/usb/if_upgtvar.h

338

uint32_t unknown3;

sys/dev/usb/if_upgtvar.h

360

uint32_t type;

sys/dev/usb/if_upgtvar.h

361

uint32_t pad2;

sys/dev/usb/if_upgtvar.h

362

uint32_t unknown1;

sys/dev/usb/if_upgtvar.h

363

uint32_t unknown2;

sys/dev/usb/if_upgtvar.h

383

uint32_t addr;

sys/dev/usb/if_upgtvar.h

429

uint32_t sc_memaddr_frame_start;

sys/dev/usb/if_upgtvar.h

430

uint32_t sc_memaddr_frame_end;

sys/dev/usb/if_upgtvar.h

431

uint32_t sc_memaddr_rx_start;

sys/dev/usb/if_upgtvar.h

83

uint32_t addr;

sys/dev/usb/if_ure.c

1102

uint32_t descsize, new_buflen;

sys/dev/usb/if_ure.c

1244

uint32_t bufsize, int listlen)

sys/dev/usb/if_ure.c

1292

uint32_t pwrctrl;

sys/dev/usb/if_ure.c

154

uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t);

sys/dev/usb/if_ure.c

155

int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t);

sys/dev/usb/if_ure.c

156

int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t);

sys/dev/usb/if_ure.c

157

int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t);

sys/dev/usb/if_ure.c

163

uint32_t ure_ocp_cmd_read(struct ure_softc *, uint16_t, int);

sys/dev/usb/if_ure.c

164

void ure_ocp_cmd_write(struct ure_softc *, uint16_t, int, uint32_t);

sys/dev/usb/if_ure.c

1689

uint32_t rx_fifo1, rx_fifo2;

sys/dev/usb/if_ure.c

1771

uint32_t reg = 0;

sys/dev/usb/if_ure.c

178

void ure_decap(struct ure_softc *, struct ure_chain *, uint32_t);

sys/dev/usb/if_ure.c

180

uint32_t);

sys/dev/usb/if_ure.c

188

uint32_t, int);

sys/dev/usb/if_ure.c

2373

uint32_t cflags, rxvlan;

sys/dev/usb/if_ure.c

2398

uint32_t cflags, rxvlan, vtag;

sys/dev/usb/if_ure.c

2431

uint32_t total_len;

sys/dev/usb/if_ure.c

2513

ure_decap(struct ure_softc *sc, struct ure_chain *c, uint32_t len)

sys/dev/usb/if_ure.c

2517

uint32_t hdrsize;

sys/dev/usb/if_ure.c

2582

uint32_t maxlen)

sys/dev/usb/if_ure.c

2586

uint32_t len, cflags = 0;

sys/dev/usb/if_ure.c

283

uint32_t val;

sys/dev/usb/if_ure.c

300

uint32_t val;

sys/dev/usb/if_ure.c

314

uint32_t

sys/dev/usb/if_ure.c

324

ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)

sys/dev/usb/if_ure.c

345

ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)

sys/dev/usb/if_ure.c

366

ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)

sys/dev/usb/if_ure.c

463

uint32_t

sys/dev/usb/if_ure.c

498

ure_ocp_cmd_write(struct ure_softc *sc, uint16_t addr, int type, uint32_t data)

sys/dev/usb/if_ure.c

596

uint32_t reg = 0;

sys/dev/usb/if_ure.c

865

uint32_t hashes[2] = { 0, 0 };

sys/dev/usb/if_ure.c

866

uint32_t hash;

sys/dev/usb/if_ure.c

867

uint32_t rxmode;

sys/dev/usb/if_urereg.h

573

uint32_t ure_pktlen;

sys/dev/usb/if_urereg.h

575

uint32_t ure_vlan;

sys/dev/usb/if_urereg.h

582

uint32_t ure_csum;

sys/dev/usb/if_urereg.h

586

uint32_t ure_rsvd2;

sys/dev/usb/if_urereg.h

587

uint32_t ure_rsvd3;

sys/dev/usb/if_urereg.h

588

uint32_t ure_rsvd4;

sys/dev/usb/if_urereg.h

592

uint32_t ure_pktlen;

sys/dev/usb/if_urereg.h

596

uint32_t ure_vlan;

sys/dev/usb/if_urereg.h

605

uint32_t ure_pktlen;

sys/dev/usb/if_urereg.h

608

uint32_t ure_vlan;

sys/dev/usb/if_urereg.h

609

uint32_t ure_csum;

sys/dev/usb/if_urereg.h

617

uint32_t ure_rsvd0;

sys/dev/usb/if_urereg.h

621

uint32_t ure_cmdstat;

sys/dev/usb/if_urereg.h

622

uint32_t ure_vlan;

sys/dev/usb/if_urereg.h

623

uint32_t ure_pktlen;

sys/dev/usb/if_urereg.h

624

uint32_t ure_signature;

sys/dev/usb/if_urereg.h

650

uint32_t uc_cnt;

sys/dev/usb/if_urereg.h

651

uint32_t uc_buflen;

sys/dev/usb/if_urereg.h

652

uint32_t uc_bufmax;

sys/dev/usb/if_urtw.c

1032

uint32_t rev;

sys/dev/usb/if_urtw.c

1080

urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data)

sys/dev/usb/if_urtw.c

1086

uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27;

sys/dev/usb/if_urtw.c

1087

uint32_t mask = 0x80000000, value = 0;

sys/dev/usb/if_urtw.c

1205

uint32_t data;

sys/dev/usb/if_urtw.c

1240

uint32_t data;

sys/dev/usb/if_urtw.c

1289

uint32_t data;

sys/dev/usb/if_urtw.c

1361

uint32_t data;

sys/dev/usb/if_urtw.c

1383

urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data)

sys/dev/usb/if_urtw.c

1590

urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data, uint8_t idx)

sys/dev/usb/if_urtw.c

1599

USETW(req.wLength, sizeof(uint32_t));

sys/dev/usb/if_urtw.c

1650

urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data, uint8_t idx)

sys/dev/usb/if_urtw.c

1658

USETW(req.wLength, sizeof(uint32_t));

sys/dev/usb/if_urtw.c

1665

urtw_set_mode(struct urtw_softc *sc, uint32_t mode)

sys/dev/usb/if_urtw.c

1679

urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val)

sys/dev/usb/if_urtw.c

1702

urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val)

sys/dev/usb/if_urtw.c

173

uint32_t reg;

sys/dev/usb/if_urtw.c

174

uint32_t val;

sys/dev/usb/if_urtw.c

2089

uint32_t data;

sys/dev/usb/if_urtw.c

2164

uint32_t data;

sys/dev/usb/if_urtw.c

238

static uint32_t urtw_8225_channel[] = {

sys/dev/usb/if_urtw.c

2723

urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data)

sys/dev/usb/if_urtw.c

2725

uint32_t phyw;

sys/dev/usb/if_urtw.c

2742

urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)

sys/dev/usb/if_urtw.c

2749

urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)

sys/dev/usb/if_urtw.c

3245

uint32_t data32;

sys/dev/usb/if_urtw.c

3400

uint32_t data;

sys/dev/usb/if_urtw.c

3510

uint32_t data;

sys/dev/usb/if_urtw.c

3524

data = ((uint32_t)aifs << 0) | /* AIFS, offset 0 */

sys/dev/usb/if_urtw.c

3525

((uint32_t)ecwmin << 8) | /* ECW minimum, offset 8 */

sys/dev/usb/if_urtw.c

3526

((uint32_t)ecwmax << 12); /* ECW maximum, offset 16 */

sys/dev/usb/if_urtw.c

496

usbd_status urtw_read32_c(struct urtw_softc *, int, uint32_t *, uint8_t);

sys/dev/usb/if_urtw.c

499

usbd_status urtw_write32_c(struct urtw_softc *, int, uint32_t, uint8_t);

sys/dev/usb/if_urtw.c

504

usbd_status urtw_eprom_read32(struct urtw_softc *, uint32_t,

sys/dev/usb/if_urtw.c

505

uint32_t *);

sys/dev/usb/if_urtw.c

514

usbd_status urtw_8187_write_phy(struct urtw_softc *, uint8_t, uint32_t);

sys/dev/usb/if_urtw.c

516

uint32_t);

sys/dev/usb/if_urtw.c

518

uint32_t);

sys/dev/usb/if_urtw.c

524

usbd_status urtw_8225_read(struct urtw_softc *, uint8_t, uint32_t *);

sys/dev/usb/if_urtw.c

536

usbd_status urtw_8180_set_anaparam(struct urtw_softc *, uint32_t);

sys/dev/usb/if_urtw.c

537

usbd_status urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t);

sys/dev/usb/if_urtw.c

598

uint32_t data;

sys/dev/usb/if_urtwn.c

1171

uint32_t rxdw0, rxdw3;

sys/dev/usb/if_urtwn.c

1308

uint32_t rxdw0;

sys/dev/usb/if_urtwn.c

1456

uint32_t pktlen;

sys/dev/usb/if_urtwn.c

1559

uint32_t pktlen;

sys/dev/usb/if_urtwn.c

1770

uint32_t reg;

sys/dev/usb/if_urtwn.c

1840

uint32_t reg;

sys/dev/usb/if_urtwn.c

1914

uint32_t reg;

sys/dev/usb/if_urtwn.c

1977

uint32_t reg;

sys/dev/usb/if_urtwn.c

2083

uint32_t reg;

sys/dev/usb/if_urtwn.c

2140

uint32_t reg;

sys/dev/usb/if_urtwn.c

2251

uint32_t reg = 0;

sys/dev/usb/if_urtwn.c

2335

uint32_t reg;

sys/dev/usb/if_urtwn.c

240

uint32_t chip;

sys/dev/usb/if_urtwn.c

366

void urtwn_write_4(void *, uint16_t, uint32_t);

sys/dev/usb/if_urtwn.c

371

uint32_t urtwn_read_4(void *, uint16_t);

sys/dev/usb/if_urtwn.c

372

int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t);

sys/dev/usb/if_urtwn.c

816

urtwn_write_4(void *cookie, uint16_t addr, uint32_t val)

sys/dev/usb/if_urtwn.c

860

uint32_t

sys/dev/usb/if_urtwn.c

864

uint32_t val;

sys/dev/usb/if_urtwn.c

872

urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data)

sys/dev/usb/if_urtwreg.h

314

uint32_t max_sens;

sys/dev/usb/if_urtwreg.h

315

uint32_t sens;

sys/dev/usb/if_urtwreg.h

364

uint32_t sc_tx_low_queued;

sys/dev/usb/if_urtwreg.h

365

uint32_t sc_tx_normal_queued;

sys/dev/usb/if_urtwreg.h

366

uint32_t sc_txidx;

sys/dev/usb/if_zyd.c

1007

static const uint32_t rfini[] = ZYD_AL2230_RF_B;

sys/dev/usb/if_zyd.c

1042

uint32_t r1, r2, r3;

sys/dev/usb/if_zyd.c

1065

static const uint32_t rfini_1[] = ZYD_AL7230B_RF_1;

sys/dev/usb/if_zyd.c

1066

static const uint32_t rfini_2[] = ZYD_AL7230B_RF_2;

sys/dev/usb/if_zyd.c

1119

uint32_t r1, r2;

sys/dev/usb/if_zyd.c

1121

static const uint32_t rfsc[] = ZYD_AL7230B_RF_SETCHANNEL;

sys/dev/usb/if_zyd.c

1157

static const uint32_t rfini[] = ZYD_AL2210_RF;

sys/dev/usb/if_zyd.c

1158

uint32_t tmp;

sys/dev/usb/if_zyd.c

1198

static const uint32_t rfprog[] = ZYD_AL2210_CHANTABLE;

sys/dev/usb/if_zyd.c

1199

uint32_t tmp;

sys/dev/usb/if_zyd.c

1227

static const uint32_t rfini[] = ZYD_GCT_RF;

sys/dev/usb/if_zyd.c

1256

static const uint32_t rfprog[] = ZYD_GCT_CHANTABLE;

sys/dev/usb/if_zyd.c

1273

static const uint32_t rfini[] = ZYD_MAXIM_RF;

sys/dev/usb/if_zyd.c

1310

static const uint32_t rfini[] = ZYD_MAXIM_RF;

sys/dev/usb/if_zyd.c

1312

uint32_t r1, r2;

sys/dev/usb/if_zyd.c

1354

static const uint32_t rfini[] = ZYD_MAXIM2_RF;

sys/dev/usb/if_zyd.c

1391

static const uint32_t rfini[] = ZYD_MAXIM2_RF;

sys/dev/usb/if_zyd.c

1393

uint32_t r1, r2;

sys/dev/usb/if_zyd.c

1506

uint32_t tmp;

sys/dev/usb/if_zyd.c

1593

uint32_t tmp;

sys/dev/usb/if_zyd.c

1650

uint32_t lo, hi;

sys/dev/usb/if_zyd.c

1680

uint32_t tmp;

sys/dev/usb/if_zyd.c

1692

uint32_t tmp;

sys/dev/usb/if_zyd.c

1717

uint32_t tmp;

sys/dev/usb/if_zyd.c

1729

uint32_t rxfilter;

sys/dev/usb/if_zyd.c

174

int zyd_read32(struct zyd_softc *, uint16_t, uint32_t *);

sys/dev/usb/if_zyd.c

1756

uint32_t tmp;

sys/dev/usb/if_zyd.c

177

int zyd_write32(struct zyd_softc *, uint16_t, uint32_t);

sys/dev/usb/if_zyd.c

178

int zyd_rfwrite(struct zyd_softc *, uint32_t);

sys/dev/usb/if_zyd.c

1833

uint32_t len;

sys/dev/usb/if_zyd.c

810

zyd_read32(struct zyd_softc *sc, uint16_t reg, uint32_t *val)

sys/dev/usb/if_zyd.c

864

zyd_write32(struct zyd_softc *sc, uint16_t reg, uint32_t val)

sys/dev/usb/if_zyd.c

877

zyd_rfwrite(struct zyd_softc *sc, uint32_t val)

sys/dev/usb/if_zyd.c

900

uint32_t tmp;

sys/dev/usb/if_zyd.c

910

uint32_t tmp;

sys/dev/usb/if_zyd.c

925

static const uint32_t rfini[] = ZYD_RFMD_RF;

sys/dev/usb/if_zyd.c

959

uint32_t r1, r2;

sys/dev/usb/if_zyd.c

977

static const uint32_t rfini[] = ZYD_AL2230_RF;

sys/dev/usb/if_zydreg.h

1115

uint32_t val;

sys/dev/usb/mbim.h

167

uint32_t type; /* message type */

sys/dev/usb/mbim.h

168

uint32_t len; /* message length */

sys/dev/usb/mbim.h

169

uint32_t tid; /* transaction id */

sys/dev/usb/mbim.h

173

uint32_t nfrag; /* total # of fragments */

sys/dev/usb/mbim.h

174

uint32_t currfrag; /* current fragment */

sys/dev/usb/mbim.h

184

uint32_t maxlen;

sys/dev/usb/mbim.h

195

uint32_t cid; /* command id */

sys/dev/usb/mbim.h

198

uint32_t op;

sys/dev/usb/mbim.h

199

uint32_t infolen;

sys/dev/usb/mbim.h

207

uint32_t cid; /* command id */

sys/dev/usb/mbim.h

208

uint32_t infolen;

sys/dev/usb/mbim.h

223

uint32_t err;

sys/dev/usb/mbim.h

235

uint32_t cid; /* command id */

sys/dev/usb/mbim.h

237

uint32_t infolen;

sys/dev/usb/mbim.h

275

uint32_t ready;

sys/dev/usb/mbim.h

277

uint32_t sid_offs;

sys/dev/usb/mbim.h

278

uint32_t sid_size;

sys/dev/usb/mbim.h

280

uint32_t icc_offs;

sys/dev/usb/mbim.h

281

uint32_t icc_size;

sys/dev/usb/mbim.h

285

uint32_t info;

sys/dev/usb/mbim.h

287

uint32_t no_pn;

sys/dev/usb/mbim.h

289

uint32_t offs;

sys/dev/usb/mbim.h

290

uint32_t size;

sys/dev/usb/mbim.h

298

uint32_t state;

sys/dev/usb/mbim.h

302

uint32_t hw_state;

sys/dev/usb/mbim.h

303

uint32_t sw_state;

sys/dev/usb/mbim.h

325

uint32_t type;

sys/dev/usb/mbim.h

331

uint32_t op;

sys/dev/usb/mbim.h

332

uint32_t pin_offs;

sys/dev/usb/mbim.h

333

uint32_t pin_size;

sys/dev/usb/mbim.h

334

uint32_t newpin_offs;

sys/dev/usb/mbim.h

335

uint32_t newpin_size;

sys/dev/usb/mbim.h

341

uint32_t type;

sys/dev/usb/mbim.h

345

uint32_t state;

sys/dev/usb/mbim.h

346

uint32_t remaining_attempts;

sys/dev/usb/mbim.h

355

uint32_t mode;

sys/dev/usb/mbim.h

360

uint32_t format;

sys/dev/usb/mbim.h

362

uint32_t minlen;

sys/dev/usb/mbim.h

363

uint32_t maxlen;

sys/dev/usb/mbim.h

382

uint32_t devtype;

sys/dev/usb/mbim.h

384

uint32_t cellclass; /* values: MBIM_CELLULAR_CLASS */

sys/dev/usb/mbim.h

385

uint32_t voiceclass;

sys/dev/usb/mbim.h

386

uint32_t simclass;

sys/dev/usb/mbim.h

387

uint32_t dataclass; /* values: MBIM_DATA_CLASS */

sys/dev/usb/mbim.h

388

uint32_t smscaps;

sys/dev/usb/mbim.h

389

uint32_t cntrlcaps;

sys/dev/usb/mbim.h

390

uint32_t max_sessions;

sys/dev/usb/mbim.h

392

uint32_t custdataclass_offs;

sys/dev/usb/mbim.h

393

uint32_t custdataclass_size;

sys/dev/usb/mbim.h

395

uint32_t devid_offs;

sys/dev/usb/mbim.h

396

uint32_t devid_size;

sys/dev/usb/mbim.h

398

uint32_t fwinfo_offs;

sys/dev/usb/mbim.h

399

uint32_t fwinfo_size;

sys/dev/usb/mbim.h

401

uint32_t hwinfo_offs;

sys/dev/usb/mbim.h

402

uint32_t hwinfo_size;

sys/dev/usb/mbim.h

404

uint32_t data[];

sys/dev/usb/mbim.h

408

uint32_t provid_offs;

sys/dev/usb/mbim.h

409

uint32_t provid_size;

sys/dev/usb/mbim.h

413

uint32_t regaction;

sys/dev/usb/mbim.h

414

uint32_t data_class;

sys/dev/usb/mbim.h

416

uint32_t data[];

sys/dev/usb/mbim.h

420

uint32_t nwerror;

sys/dev/usb/mbim.h

422

uint32_t regstate; /* values: MBIM_REGISTER_STATE */

sys/dev/usb/mbim.h

427

uint32_t regmode;

sys/dev/usb/mbim.h

429

uint32_t availclasses; /* values: MBIM_DATA_CLASS */

sys/dev/usb/mbim.h

430

uint32_t curcellclass; /* values: MBIM_CELLULAR_CLASS */

sys/dev/usb/mbim.h

432

uint32_t provid_offs;

sys/dev/usb/mbim.h

433

uint32_t provid_size;

sys/dev/usb/mbim.h

435

uint32_t provname_offs;

sys/dev/usb/mbim.h

436

uint32_t provname_size;

sys/dev/usb/mbim.h

438

uint32_t roamingtxt_offs;

sys/dev/usb/mbim.h

439

uint32_t roamingtxt_size;

sys/dev/usb/mbim.h

444

uint32_t regflag;

sys/dev/usb/mbim.h

446

uint32_t data[];

sys/dev/usb/mbim.h

452

uint32_t action;

sys/dev/usb/mbim.h

456

uint32_t nwerror;

sys/dev/usb/mbim.h

463

uint32_t state;

sys/dev/usb/mbim.h

465

uint32_t highest_dataclass;

sys/dev/usb/mbim.h

471

uint32_t rssi;

sys/dev/usb/mbim.h

472

uint32_t err_rate;

sys/dev/usb/mbim.h

473

uint32_t ss_intvl;

sys/dev/usb/mbim.h

474

uint32_t rssi_thr;

sys/dev/usb/mbim.h

475

uint32_t err_thr;

sys/dev/usb/mbim.h

479

uint32_t sessionid;

sys/dev/usb/mbim.h

483

uint32_t command;

sys/dev/usb/mbim.h

486

uint32_t access_offs;

sys/dev/usb/mbim.h

487

uint32_t access_size;

sys/dev/usb/mbim.h

490

uint32_t user_offs;

sys/dev/usb/mbim.h

491

uint32_t user_size;

sys/dev/usb/mbim.h

494

uint32_t passwd_offs;

sys/dev/usb/mbim.h

495

uint32_t passwd_size;

sys/dev/usb/mbim.h

499

uint32_t compression;

sys/dev/usb/mbim.h

505

uint32_t authprot;

sys/dev/usb/mbim.h

512

uint32_t iptype;

sys/dev/usb/mbim.h

522

uint32_t sessionid;

sys/dev/usb/mbim.h

529

uint32_t activation;

sys/dev/usb/mbim.h

531

uint32_t voice;

sys/dev/usb/mbim.h

532

uint32_t iptype;

sys/dev/usb/mbim.h

534

uint32_t nwerror;

sys/dev/usb/mbim.h

538

uint32_t prefixlen;

sys/dev/usb/mbim.h

539

uint32_t addr;

sys/dev/usb/mbim.h

543

uint32_t prefixlen;

sys/dev/usb/mbim.h

548

uint32_t sessionid;

sys/dev/usb/mbim.h

554

uint32_t ipv4_available;

sys/dev/usb/mbim.h

555

uint32_t ipv6_available;

sys/dev/usb/mbim.h

557

uint32_t ipv4_naddr;

sys/dev/usb/mbim.h

558

uint32_t ipv4_addroffs;

sys/dev/usb/mbim.h

559

uint32_t ipv6_naddr;

sys/dev/usb/mbim.h

560

uint32_t ipv6_addroffs;

sys/dev/usb/mbim.h

562

uint32_t ipv4_gwoffs;

sys/dev/usb/mbim.h

563

uint32_t ipv6_gwoffs;

sys/dev/usb/mbim.h

565

uint32_t ipv4_ndnssrv;

sys/dev/usb/mbim.h

566

uint32_t ipv4_dnssrvoffs;

sys/dev/usb/mbim.h

567

uint32_t ipv6_ndnssrv;

sys/dev/usb/mbim.h

568

uint32_t ipv6_dnssrvoffs;

sys/dev/usb/mbim.h

570

uint32_t ipv4_mtu;

sys/dev/usb/mbim.h

571

uint32_t ipv6_mtu;

sys/dev/usb/mbim.h

573

uint32_t data[];

sys/dev/usb/mbim.h

577

uint32_t in_discards;

sys/dev/usb/mbim.h

578

uint32_t in_errors;

sys/dev/usb/mbim.h

583

uint32_t out_errors;

sys/dev/usb/mbim.h

584

uint32_t out_discards;

sys/dev/usb/uaudio.c

3434

uint32_t size;

sys/dev/usb/ubcmtp.c

336

uint32_t sc_status;

sys/dev/usb/uchcom.c

185

void uchcom_calc_baudrate(struct uchcom_softc *, uint32_t, uint8_t *,

sys/dev/usb/uchcom.c

187

int uchcom_set_dte_rate(struct uchcom_softc *, uint32_t, uint16_t);

sys/dev/usb/uchcom.c

638

uchcom_calc_baudrate(struct uchcom_softc *sc, uint32_t rate, uint8_t *divisor,

sys/dev/usb/uchcom.c

641

uint32_t clk = 12000000;

sys/dev/usb/uchcom.c

666

uchcom_set_dte_rate(struct uchcom_softc *sc, uint32_t rate, uint16_t val)

sys/dev/usb/uchcom.c

929

uint32_t intrstat;

sys/dev/usb/ucom.c

1256

uint32_t route;

sys/dev/usb/ucom.c

186

uint32_t route;

sys/dev/usb/ucycom.c

107

uint32_t sc_icnt;

sys/dev/usb/ucycom.c

110

uint32_t sc_baud;

sys/dev/usb/ucycom.c

375

uint32_t baud = 0;

sys/dev/usb/udl.c

100

uint32_t, uint32_t, uint32_t, uint32_t);

sys/dev/usb/udl.c

104

usbd_status udl_poll(struct udl_softc *, uint32_t *);

sys/dev/usb/udl.c

1044

uint32_t x, uint32_t y)

sys/dev/usb/udl.c

1087

uint32_t x1, uint32_t x2, uint32_t y1, uint32_t y2)

sys/dev/usb/udl.c

109

uint32_t);

sys/dev/usb/udl.c

1116

uint32_t x, uint32_t y, uint32_t width, uint32_t height)

sys/dev/usb/udl.c

1122

uint32_t off, block;

sys/dev/usb/udl.c

1182

udl_poll(struct udl_softc *sc, uint32_t *buf)

sys/dev/usb/udl.c

1193

*buf = *(uint32_t *)lbuf;

sys/dev/usb/udl.c

124

void udl_cmd_insert_int_3(struct udl_softc *, uint32_t);

sys/dev/usb/udl.c

125

void udl_cmd_insert_int_4(struct udl_softc *, uint32_t);

sys/dev/usb/udl.c

126

void udl_cmd_insert_buf(struct udl_softc *, uint8_t *, uint32_t);

sys/dev/usb/udl.c

1267

uint16_t chip, uint32_t clock)

sys/dev/usb/udl.c

128

uint32_t);

sys/dev/usb/udl.c

129

int udl_cmd_insert_head_comp(struct udl_softc *, uint32_t);

sys/dev/usb/udl.c

135

void udl_cmd_write_reg_3(struct udl_softc *, uint8_t, uint32_t);

sys/dev/usb/udl.c

141

void udl_init_fb_offsets(struct udl_softc *, uint32_t, uint32_t,

sys/dev/usb/udl.c

142

uint32_t, uint32_t);

sys/dev/usb/udl.c

146

int udl_fb_buf_write(struct udl_softc *, uint8_t *, uint32_t,

sys/dev/usb/udl.c

147

uint32_t, uint16_t);

sys/dev/usb/udl.c

148

int udl_fb_block_write(struct udl_softc *, uint16_t, uint32_t,

sys/dev/usb/udl.c

149

uint32_t, uint32_t, uint32_t);

sys/dev/usb/udl.c

150

int udl_fb_line_write(struct udl_softc *, uint16_t, uint32_t,

sys/dev/usb/udl.c

151

uint32_t, uint32_t);

sys/dev/usb/udl.c

152

int udl_fb_off_write(struct udl_softc *, uint16_t, uint32_t,

sys/dev/usb/udl.c

154

int udl_fb_block_copy(struct udl_softc *, uint32_t, uint32_t,

sys/dev/usb/udl.c

155

uint32_t, uint32_t, uint32_t, uint32_t);

sys/dev/usb/udl.c

156

int udl_fb_line_copy(struct udl_softc *, uint32_t, uint32_t,

sys/dev/usb/udl.c

157

uint32_t, uint32_t, uint32_t);

sys/dev/usb/udl.c

1570

udl_cmd_insert_int_3(struct udl_softc *sc, uint32_t value)

sys/dev/usb/udl.c

1572

uint32_t lvalue;

sys/dev/usb/udl.c

158

int udl_fb_off_copy(struct udl_softc *, uint32_t, uint32_t,

sys/dev/usb/udl.c

1585

udl_cmd_insert_int_4(struct udl_softc *sc, uint32_t value)

sys/dev/usb/udl.c

1587

uint32_t lvalue;

sys/dev/usb/udl.c

1597

udl_cmd_insert_buf(struct udl_softc *sc, uint8_t *buf, uint32_t len)

sys/dev/usb/udl.c

160

int udl_fb_buf_write_comp(struct udl_softc *, uint8_t *, uint32_t,

sys/dev/usb/udl.c

1607

udl_cmd_insert_buf_comp(struct udl_softc *sc, uint8_t *buf, uint32_t len)

sys/dev/usb/udl.c

161

uint32_t, uint16_t);

sys/dev/usb/udl.c

1614

uint32_t bit_count, bit_pattern, bit_cur;

sys/dev/usb/udl.c

162

int udl_fb_block_write_comp(struct udl_softc *, uint16_t, uint32_t,

sys/dev/usb/udl.c

163

uint32_t, uint32_t, uint32_t);

sys/dev/usb/udl.c

164

int udl_fb_line_write_comp(struct udl_softc *, uint16_t, uint32_t,

sys/dev/usb/udl.c

165

uint32_t, uint32_t);

sys/dev/usb/udl.c

166

int udl_fb_off_write_comp(struct udl_softc *, uint16_t, uint32_t,

sys/dev/usb/udl.c

168

int udl_fb_block_copy_comp(struct udl_softc *, uint32_t, uint32_t,

sys/dev/usb/udl.c

169

uint32_t, uint32_t, uint32_t, uint32_t);

sys/dev/usb/udl.c

170

int udl_fb_line_copy_comp(struct udl_softc *, uint32_t, uint32_t,

sys/dev/usb/udl.c

1707

udl_cmd_insert_head_comp(struct udl_softc *sc, uint32_t len)

sys/dev/usb/udl.c

171

uint32_t, uint32_t, uint32_t);

sys/dev/usb/udl.c

172

int udl_fb_off_copy_comp(struct udl_softc *, uint32_t, uint32_t,

sys/dev/usb/udl.c

1791

udl_cmd_write_reg_3(struct udl_softc *sc, uint8_t reg, uint32_t val)

sys/dev/usb/udl.c

1920

uint32_t ui32;

sys/dev/usb/udl.c

1978

udl_init_fb_offsets(struct udl_softc *sc, uint32_t start16, uint32_t stride16,

sys/dev/usb/udl.c

1979

uint32_t start8, uint32_t stride8)

sys/dev/usb/udl.c

2115

udl_fb_buf_write(struct udl_softc *sc, uint8_t *buf, uint32_t x,

sys/dev/usb/udl.c

2116

uint32_t y, uint16_t width)

sys/dev/usb/udl.c

2119

uint32_t off;

sys/dev/usb/udl.c

2140

udl_fb_block_write(struct udl_softc *sc, uint16_t rgb16, uint32_t x,

sys/dev/usb/udl.c

2141

uint32_t y, uint32_t width, uint32_t height)

sys/dev/usb/udl.c

2143

uint32_t i;

sys/dev/usb/udl.c

2156

udl_fb_line_write(struct udl_softc *sc, uint16_t rgb16, uint32_t x,

sys/dev/usb/udl.c

2157

uint32_t y, uint32_t width)

sys/dev/usb/udl.c

2159

uint32_t off, block;

sys/dev/usb/udl.c

2182

udl_fb_off_write(struct udl_softc *sc, uint16_t rgb16, uint32_t off,

sys/dev/usb/udl.c

2187

uint32_t loff;

sys/dev/usb/udl.c

2213

udl_fb_block_copy(struct udl_softc *sc, uint32_t src_x, uint32_t src_y,

sys/dev/usb/udl.c

2214

uint32_t dst_x, uint32_t dst_y, uint32_t width, uint32_t height)

sys/dev/usb/udl.c

2230

udl_fb_line_copy(struct udl_softc *sc, uint32_t src_x, uint32_t src_y,

sys/dev/usb/udl.c

2231

uint32_t dst_x, uint32_t dst_y, uint32_t width)

sys/dev/usb/udl.c

2233

uint32_t src_off, dst_off, block;

sys/dev/usb/udl.c

2258

udl_fb_off_copy(struct udl_softc *sc, uint32_t src_off, uint32_t dst_off,

sys/dev/usb/udl.c

2261

uint32_t ldst_off, lsrc_off;

sys/dev/usb/udl.c

2281

udl_fb_buf_write_comp(struct udl_softc *sc, uint8_t *buf, uint32_t x,

sys/dev/usb/udl.c

2282

uint32_t y, uint16_t width)

sys/dev/usb/udl.c

2287

uint32_t off;

sys/dev/usb/udl.c

2329

udl_fb_block_write_comp(struct udl_softc *sc, uint16_t rgb16, uint32_t x,

sys/dev/usb/udl.c

2330

uint32_t y, uint32_t width, uint32_t height)

sys/dev/usb/udl.c

2332

uint32_t i;

sys/dev/usb/udl.c

2345

udl_fb_line_write_comp(struct udl_softc *sc, uint16_t rgb16, uint32_t x,

sys/dev/usb/udl.c

2346

uint32_t y, uint32_t width)

sys/dev/usb/udl.c

2348

uint32_t off, block;

sys/dev/usb/udl.c

2371

udl_fb_off_write_comp(struct udl_softc *sc, uint16_t rgb16, uint32_t off,

sys/dev/usb/udl.c

2378

uint32_t loff;

sys/dev/usb/udl.c

2425

udl_fb_block_copy_comp(struct udl_softc *sc, uint32_t src_x, uint32_t src_y,

sys/dev/usb/udl.c

2426

uint32_t dst_x, uint32_t dst_y, uint32_t width, uint32_t height)

sys/dev/usb/udl.c

2441

udl_fb_line_copy_comp(struct udl_softc *sc, uint32_t src_x, uint32_t src_y,

sys/dev/usb/udl.c

2442

uint32_t dst_x, uint32_t dst_y, uint32_t width)

sys/dev/usb/udl.c

2444

uint32_t src_off, dst_off, block;

sys/dev/usb/udl.c

2469

udl_fb_off_copy_comp(struct udl_softc *sc, uint32_t src_off, uint32_t dst_off,

sys/dev/usb/udl.c

2473

uint32_t ldst_off, lsrc_off;

sys/dev/usb/udl.c

608

void **cookiep, int *curxp, int *curyp, uint32_t *attrp)

sys/dev/usb/udl.c

81

void **, int *, int *, uint32_t *);

sys/dev/usb/udl.c

846

udl_erasecols(void *cookie, int row, int col, int num, uint32_t attr)

sys/dev/usb/udl.c

889

udl_eraserows(void *cookie, int row, int num, uint32_t attr)

sys/dev/usb/udl.c

91

int udl_erasecols(void *, int, int, int, uint32_t);

sys/dev/usb/udl.c

92

int udl_eraserows(void *, int, int, uint32_t);

sys/dev/usb/udl.c

93

int udl_putchar(void *, int, int, u_int, uint32_t);

sys/dev/usb/udl.c

931

udl_putchar(void *cookie, int row, int col, u_int uc, uint32_t attr)

sys/dev/usb/udl.c

937

uint32_t x, y, fg, bg;

sys/dev/usb/udl.c

96

uint32_t, uint32_t);

sys/dev/usb/udl.c

98

uint32_t, uint32_t, uint32_t, uint32_t);

sys/dev/usb/udl.c

988

uint32_t x, y;

sys/dev/usb/udl.h

101

(struct udl_softc *, uint16_t, uint32_t,

sys/dev/usb/udl.h

102

uint32_t, uint32_t);

sys/dev/usb/udl.h

104

(struct udl_softc *, uint16_t, uint32_t,

sys/dev/usb/udl.h

105

uint32_t, uint32_t, uint32_t);

sys/dev/usb/udl.h

107

(struct udl_softc *, uint8_t *, uint32_t,

sys/dev/usb/udl.h

108

uint32_t, uint16_t);

sys/dev/usb/udl.h

110

(struct udl_softc *, uint32_t, uint32_t,

sys/dev/usb/udl.h

113

(struct udl_softc *, uint32_t, uint32_t,

sys/dev/usb/udl.h

114

uint32_t, uint32_t, uint32_t);

sys/dev/usb/udl.h

116

(struct udl_softc *, uint32_t, uint32_t,

sys/dev/usb/udl.h

117

uint32_t, uint32_t, uint32_t, uint32_t);

sys/dev/usb/udl.h

283

uint32_t clock;

sys/dev/usb/udl.h

329

uint32_t bit_count;

sys/dev/usb/udl.h

330

uint32_t bit_pattern;

sys/dev/usb/udl.h

44

uint32_t off;

sys/dev/usb/udl.h

45

uint32_t off_save;

sys/dev/usb/udl.h

98

(struct udl_softc *, uint16_t, uint32_t,

sys/dev/usb/uhcireg.h

166

#define UHCI_TD_SET_MAXLEN(l) (((uint32_t)(l)-1) << 21)

sys/dev/usb/uhub.c

489

uint32_t stats = 0;

sys/dev/usb/uhub.c

501

stats |= (uint32_t)(xfer->buffer[i]) << (i * 8);

sys/dev/usb/uhub.c

62

uint32_t sc_status; /* status from last interrupt */

sys/dev/usb/ujoy.c

64

uint32_t coll_usage = ~0;

sys/dev/usb/ulpt.c

657

uint32_t len;

sys/dev/usb/umcs.c

102

int umcs_calc_baudrate(uint32_t, uint16_t *, uint8_t *);

sys/dev/usb/umcs.c

103

int umcs_set_baudrate(struct umcs_softc *, uint8_t, uint32_t);

sys/dev/usb/umcs.c

397

umcs_set_baudrate(struct umcs_softc *sc, uint8_t portno, uint32_t rate)

sys/dev/usb/umcs.c

438

static const uint32_t umcs_baudrate_divisors[] = {

sys/dev/usb/umcs.c

443

umcs_calc_baudrate(uint32_t rate, uint16_t *divisor, uint8_t *clk)

sys/dev/usb/ums.c

59

uint32_t sc_quirks;

sys/dev/usb/usb.c

955

uint32_t nframes, psize;

sys/dev/usb/usb_subr.c

1023

uint32_t mps, mps0;

sys/dev/usb/usb_subr.c

1345

usbd_get_routestring(struct usbd_device *dev, uint32_t *route)

sys/dev/usb/usb_subr.c

1348

uint32_t r;

sys/dev/usb/usb_subr.c

1376

uint8_t *bus, uint32_t *route, uint8_t *ifaceno)

sys/dev/usb/usb_subr.c

1379

uint32_t r;

sys/dev/usb/usbdi.c

901

void *data, uint16_t flags, int *actlen, uint32_t timeout)

sys/dev/usb/usbdi.h

133

int usbd_get_routestring(struct usbd_device *, uint32_t *);

sys/dev/usb/usbdi.h

135

uint32_t *, uint8_t *);

sys/dev/usb/usbpcap.h

28

uint32_t uph_status; /* USB status code */

sys/dev/usb/usbpcap.h

42

uint32_t uph_dlen; /* data length */

sys/dev/usb/usbpcap.h

57

uint32_t uip_offset;

sys/dev/usb/usbpcap.h

58

uint32_t uip_length;

sys/dev/usb/usbpcap.h

59

uint32_t uip_status;

sys/dev/usb/usbpcap.h

67

uint32_t uih_startframe;

sys/dev/usb/usbpcap.h

68

uint32_t uih_nframes; /* number of frame */

sys/dev/usb/usbpcap.h

69

uint32_t uih_errors; /* error count */

sys/dev/usb/usbpcap.h

81

uint32_t uih_startframe;

sys/dev/usb/usbpcap.h

82

uint32_t uih_nframes;

sys/dev/usb/usbpcap.h

83

uint32_t uih_errors;

sys/dev/usb/uslcom.c

427

uint32_t baudrate, flowctrl[4];

sys/dev/usb/usps.c

80

uint32_t sc_device_serial;

sys/dev/usb/utpms.c

227

uint32_t sc_buttons; /* Button state. */

sys/dev/usb/utpms.c

228

uint32_t sc_status; /* Status flags. */

sys/dev/usb/utpms.c

238

int compute_delta(struct utpms_softc *, int *, int *, int *, uint32_t *);

sys/dev/usb/utpms.c

433

uint32_t buttons;

sys/dev/usb/utpms.c

535

uint32_t * buttons)

sys/dev/usb/utvfu.c

1220

uint32_t actlen;

sys/dev/usb/utvfu.c

1310

uint32_t actlen;

sys/dev/usb/utvfu.c

390

uint32_t hdr;

sys/dev/usb/utvfu.c

976

uint32_t psize;

sys/dev/usb/utvfu.h

116

uint32_t psize;

sys/dev/usb/utwitch.c

202

uint32_t val;

sys/dev/usb/utwitch.c

302

utwitch_write_value_request(struct utwitch_softc *sc, uint32_t val)

sys/dev/usb/utwitch.c

304

uint32_t v;

sys/dev/usb/utwitch.c

314

memcpy(req + 2, &v, sizeof(uint32_t));

sys/dev/usb/utwitch.c

72

uint32_t sc_curval;

sys/dev/usb/utwitch.c

73

uint32_t sc_oldval;

sys/dev/usb/utwitch.c

86

void utwitch_write_value_request(struct utwitch_softc *, uint32_t);

sys/dev/usb/uvideo.c

1246

sizeof(uint32_t));

sys/dev/usb/uvideo.c

1301

sizeof(uint32_t));

sys/dev/usb/uvideo.c

1367

uint32_t fbuf_size;

sys/dev/usb/uvideo.c

1426

uint32_t fbuf_size, frame_ival, next_frame_ival;

sys/dev/usb/uvideo.c

148

uint32_t uvideo_vc_parse_max_packet_size(struct uvideo_softc *,

sys/dev/usb/uvideo.c

1487

uint32_t

sys/dev/usb/uvideo.c

1491

uint32_t psize;

sys/dev/usb/uvideo.c

1537

uint32_t psize;

sys/dev/usb/uvideo.c

1634

uint32_t psize;

sys/dev/usb/uvideo.c

1789

uint32_t frame_ival, nivals, min, max, step, diff;

sys/dev/usb/uvideo.c

2278

uint32_t dwMaxVideoFrameSize;

sys/dev/usb/uvideo.c

3711

uint32_t width, height;

sys/dev/usb/uvideo.c

413

uint32_t pixelformat;

sys/dev/usb/uvideo.h

639

uint32_t psize;

sys/dev/usb/uvideo.h

654

uint32_t fmt_flags;

sys/dev/usb/uvideo.h

671

uint32_t pixelformat;

sys/dev/usb/uvideo.h

673

uint32_t colorspace;

sys/dev/usb/uvideo.h

674

uint32_t xfer_func;

sys/dev/usb/uvideo.h

675

uint32_t ycbcr_enc;

sys/dev/usb/xhci.c

1027

uint32_t remain, int trb_idx, uint8_t code)

sys/dev/usb/xhci.c

1111

uint32_t flags;

sys/dev/usb/xhci.c

117

int xhci_cmd_set_address(struct xhci_softc *, uint8_t, uint64_t, uint32_t);

sys/dev/usb/xhci.c

1180

xhci_event_port_change(struct xhci_softc *sc, uint64_t paddr, uint32_t status)

sys/dev/usb/xhci.c

1183

uint32_t port = XHCI_TRB_PORTID(paddr);

sys/dev/usb/xhci.c

1354

static inline uint32_t

sys/dev/usb/xhci.c

1359

uint32_t mep, atl, mps = UGETW(ed->wMaxPacketSize);

sys/dev/usb/xhci.c

1386

static inline uint32_t

sys/dev/usb/xhci.c

1389

uint32_t ival = min(max(1, ed->bInterval), 255);

sys/dev/usb/xhci.c

1394

static inline uint32_t

sys/dev/usb/xhci.c

1397

uint32_t ival = min(max(1, ed->bInterval), 16);

sys/dev/usb/xhci.c

1406

uint32_t

sys/dev/usb/xhci.c

1412

uint32_t ival;

sys/dev/usb/xhci.c

1443

uint32_t

sys/dev/usb/xhci.c

1448

uint32_t mps = UGETW(ed->wMaxPacketSize);

sys/dev/usb/xhci.c

1450

uint32_t maxb = 0;

sys/dev/usb/xhci.c

1468

static inline uint32_t

sys/dev/usb/xhci.c

1490

uint32_t mps = UGETW(ed->wMaxPacketSize);

sys/dev/usb/xhci.c

1493

uint32_t route = 0, rhport = 0;

sys/dev/usb/xhci.c

1502

uint32_t port = hub->powersrc->portno;

sys/dev/usb/xhci.c

1503

uint32_t depth = hub->myhub->depth;

sys/dev/usb/xhci.c

2037

uint32_t reg;

sys/dev/usb/xhci.c

2166

uint32_t bsr)

sys/dev/usb/xhci.c

2457

uint32_t v;

sys/dev/usb/xhci.c

2862

static inline uint32_t

sys/dev/usb/xhci.c

2863

xhci_xfer_tdsize(struct usbd_xfer *xfer, uint32_t remain, uint32_t len)

sys/dev/usb/xhci.c

2865

uint32_t npkt, mps = UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize);

sys/dev/usb/xhci.c

2882

static inline uint32_t

sys/dev/usb/xhci.c

2883

xhci_xfer_tbc(struct usbd_xfer *xfer, uint32_t len, uint32_t *tlbpc)

sys/dev/usb/xhci.c

2885

uint32_t mps = UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize);

sys/dev/usb/xhci.c

2886

uint32_t maxb, tdpc, residue, tbc;

sys/dev/usb/xhci.c

2929

uint32_t flags, len = UGETW(xfer->request.wLength);

sys/dev/usb/xhci.c

295

uint32_t hcr;

sys/dev/usb/xhci.c

3043

uint32_t len, remain, flags;

sys/dev/usb/xhci.c

3044

uint32_t mps = UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize);

sys/dev/usb/xhci.c

3190

uint32_t len, remain, flags;

sys/dev/usb/xhci.c

3192

uint32_t tbc, tlbpc;

sys/dev/usb/xhci.c

418

uint32_t hcr;

sys/dev/usb/xhci.c

429

XOWRITE4(sc, XHCI_DCBAAP_LO, (uint32_t)paddr);

sys/dev/usb/xhci.c

430

XOWRITE4(sc, XHCI_DCBAAP_HI, (uint32_t)(paddr >> 32));

sys/dev/usb/xhci.c

437

XOWRITE4(sc, XHCI_CRCR_LO, ((uint32_t)paddr) | XHCI_CRCR_LO_RCS);

sys/dev/usb/xhci.c

438

XOWRITE4(sc, XHCI_CRCR_HI, (uint32_t)(paddr >> 32));

sys/dev/usb/xhci.c

448

XRWRITE4(sc, XHCI_ERSTBA_LO(0), (uint32_t)paddr);

sys/dev/usb/xhci.c

449

XRWRITE4(sc, XHCI_ERSTBA_HI(0), (uint32_t)(paddr >> 32));

sys/dev/usb/xhci.c

456

XRWRITE4(sc, XHCI_ERDP_LO(0), (uint32_t)paddr);

sys/dev/usb/xhci.c

457

XRWRITE4(sc, XHCI_ERDP_HI(0), (uint32_t)(paddr >> 32));

sys/dev/usb/xhci.c

573

uint32_t hcr;

sys/dev/usb/xhci.c

607

uint32_t hcr;

sys/dev/usb/xhci.c

703

uint32_t intrs;

sys/dev/usb/xhci.c

761

uint32_t status, flags;

sys/dev/usb/xhci.c

793

XRWRITE4(sc, XHCI_ERDP_LO(0), ((uint32_t)paddr) | XHCI_ERDP_LO_BUSY);

sys/dev/usb/xhci.c

794

XRWRITE4(sc, XHCI_ERDP_HI(0), (uint32_t)(paddr >> 32));

sys/dev/usb/xhci.c

828

xhci_event_xfer(struct xhci_softc *sc, uint64_t paddr, uint32_t status,

sys/dev/usb/xhci.c

829

uint32_t flags)

sys/dev/usb/xhci.c

834

uint32_t remain;

sys/dev/usb/xhci.c

85

void xhci_event_xfer(struct xhci_softc *, uint64_t, uint32_t, uint32_t);

sys/dev/usb/xhci.c

87

struct xhci_pipe *, uint32_t, int, uint8_t, uint8_t, uint8_t);

sys/dev/usb/xhci.c

89

uint32_t, int, uint8_t);

sys/dev/usb/xhci.c

91

void xhci_event_port_change(struct xhci_softc *, uint64_t, uint32_t);

sys/dev/usb/xhci.c

910

uint32_t

sys/dev/usb/xhci.c

915

uint32_t len = 0, type;

sys/dev/usb/xhci.c

936

struct xhci_pipe *xp, uint32_t remain, int trb_idx,

sys/dev/usb/xhcireg.h

252

uint32_t er_size;

sys/dev/usb/xhcireg.h

253

uint32_t er_rsvd;

sys/dev/usb/xhcireg.h

258

uint32_t info_lo;

sys/dev/usb/xhcireg.h

265

uint32_t info_hi;

sys/dev/usb/xhcireg.h

270

uint32_t tt;

sys/dev/usb/xhcireg.h

277

uint32_t state;

sys/dev/usb/xhcireg.h

281

uint32_t rsvd[4];

sys/dev/usb/xhcireg.h

285

uint32_t info_lo;

sys/dev/usb/xhcireg.h

302

uint32_t info_hi;

sys/dev/usb/xhcireg.h

319

uint32_t txinfo;

sys/dev/usb/xhcireg.h

323

uint32_t rsvd[3];

sys/dev/usb/xhcireg.h

328

uint32_t drop_flags;

sys/dev/usb/xhcireg.h

329

uint32_t add_flags;

sys/dev/usb/xhcireg.h

332

uint32_t rsvd[6];

sys/dev/usb/xhcireg.h

341

uint32_t trb_status;

sys/dev/usb/xhcireg.h

348

uint32_t trb_flags;

sys/dev/usb/xhcivar.h

100

uint32_t sc_ctxsize; /* 32/64 byte context structs */

sys/dev/usb/xhcivar.h

139

uint32_t reg;

sys/dev/usb/xhcivar.h

147

uint32_t reg;

sys/dev/usb/xhcivar.h

51

uint32_t index;

sys/dev/usb/xhcivar.h

52

uint32_t toggle; /* Producer/Consumer bit */

sys/dev/usb/xhcivar.h

99

uint32_t sc_pagesize; /* xHCI page size, minimum 4k */

sys/dev/vmm/vmm.c

173

vm_find(uint32_t id, struct vm **res)

sys/dev/vmm/vmm.c

328

vm_find_vcpu(struct vm *vm, uint32_t id)

sys/dev/vmm/vmm.h

108

uint32_t vrp_vm_id;

sys/dev/vmm/vmm.h

109

uint32_t vrp_vcpu_id;

sys/dev/vmm/vmm.h

128

uint32_t vpp_vm_id;

sys/dev/vmm/vmm.h

129

uint32_t vpp_vcpu_id;

sys/dev/vmm/vmm.h

130

uint32_t vpp_mask;

sys/dev/vmm/vmm.h

132

uint32_t vpp_pvclock_version;

sys/dev/vmm/vmm.h

180

uint32_t vm_id; /* [I] */

sys/dev/vmm/vmm.h

193

uint32_t vm_vcpu_ct; /* [v] */

sys/dev/vmm/vmm.h

252

int vm_find(uint32_t, struct vm **);

sys/dev/vmm/vmm.h

255

struct vcpu *vm_find_vcpu(struct vm *, uint32_t);

sys/dev/vmm/vmm.h

59

uint32_t vcp_id;

sys/dev/vmm/vmm.h

60

uint32_t vcp_poscbit;

sys/dev/vmm/vmm.h

61

uint32_t vcp_asid[VMM_MAX_VCPUS];

sys/dev/vmm/vmm.h

71

uint32_t vir_id;

sys/dev/vmm/vmm.h

86

uint32_t vtp_vm_id;

sys/dev/vmm/vmm.h

91

uint32_t vrp_vm_id;

sys/dev/vmm/vmm.h

92

uint32_t vrp_vcpu_id;

sys/dev/vmm/vmm.h

98

uint32_t vsp_vm_id;

sys/dev/wscons/wsdisplay.c

142

const struct wsscreen_descr *, void *, int, int, uint32_t);

sys/dev/wscons/wsdisplay.c

2691

uint32_t attr;

sys/dev/wscons/wsdisplay.c

277

uint32_t defattr)

sys/dev/wscons/wsdisplay.c

380

uint32_t defattr;

sys/dev/wscons/wsdisplay.c

802

int crow, uint32_t defattr)

sys/dev/wscons/wsdisplayvar.h

124

uint32_t attr;

sys/dev/wscons/wsdisplayvar.h

140

void **, int *, int *, uint32_t *);

sys/dev/wscons/wsdisplayvar.h

194

int, int, uint32_t);

sys/dev/wscons/wsdisplayvar.h

76

int (*putchar)(void *c, int row, int col, u_int uc, uint32_t attr);

sys/dev/wscons/wsdisplayvar.h

80

uint32_t);

sys/dev/wscons/wsdisplayvar.h

82

int (*eraserows)(void *c, int row, int nrows, uint32_t attr);

sys/dev/wscons/wsdisplayvar.h

84

uint32_t *attrp);

sys/dev/wscons/wsdisplayvar.h

85

void (*unpack_attr)(void *c, uint32_t attr, int *fg, int *bg,

sys/dev/wscons/wsemul_dumb.c

103

int ccol, int crow, void *cbcookie, uint32_t defattr)

sys/dev/wscons/wsemul_dumb.c

46

int, int, uint32_t);

sys/dev/wscons/wsemul_dumb.c

48

void *, int, int, void *, uint32_t);

sys/dev/wscons/wsemul_dumb.c

71

uint32_t defattr;

sys/dev/wscons/wsemul_dumb.c

78

int crow, uint32_t defattr)

sys/dev/wscons/wsemul_sun.c

105

uint32_t defattr; /* default attribute (rendition) */

sys/dev/wscons/wsemul_sun.c

113

uint32_t curattr, bkgdattr; /* currently used attribute */

sys/dev/wscons/wsemul_sun.c

114

uint32_t kernattr; /* attribute for kernel output */

sys/dev/wscons/wsemul_sun.c

132

const struct wsscreen_descr *, void *, int, int, uint32_t);

sys/dev/wscons/wsemul_sun.c

149

uint32_t *, uint32_t *);

sys/dev/wscons/wsemul_sun.c

164

uint32_t defattr)

sys/dev/wscons/wsemul_sun.c

197

int crow, uint32_t defattr)

sys/dev/wscons/wsemul_sun.c

241

int ccol, int crow, void *cbcookie, uint32_t defattr)

sys/dev/wscons/wsemul_sun.c

407

uint32_t attr, bkgdattr;

sys/dev/wscons/wsemul_sun.c

71

int, int, uint32_t);

sys/dev/wscons/wsemul_sun.c

73

void *, int, int, void *, uint32_t);

sys/dev/wscons/wsemul_sun.c

892

int fgcol, int bgcol, uint32_t *attr, uint32_t *bkgdattr)

sys/dev/wscons/wsemul_vt100.c

138

uint32_t defattr)

sys/dev/wscons/wsemul_vt100.c

153

int crow, uint32_t defattr)

sys/dev/wscons/wsemul_vt100.c

201

void *cookie, int ccol, int crow, void *cbcookie, uint32_t defattr)

sys/dev/wscons/wsemul_vt100.c

60

int, int, uint32_t);

sys/dev/wscons/wsemul_vt100.c

62

void *, int, int, void *, uint32_t);

sys/dev/wscons/wsemul_vt100.c

80

const struct wsscreen_descr *, void *, int, int, uint32_t);

sys/dev/wscons/wsemul_vt100_subr.c

231

uint32_t attr, bkgdattr;

sys/dev/wscons/wsemul_vt100_subr.c

40

uint32_t *, uint32_t *);

sys/dev/wscons/wsemul_vt100_subr.c

783

int bgcol, uint32_t *attr, uint32_t *bkgdattr)

sys/dev/wscons/wsemul_vt100var.h

38

uint32_t defattr; /* default attribute */

sys/dev/wscons/wsemul_vt100var.h

40

uint32_t kernattr; /* attribute for kernel output */

sys/dev/wscons/wsemul_vt100var.h

58

uint32_t curattr, bkgdattr; /* currently used attribute */

sys/dev/wscons/wsemul_vt100var.h

89

uint32_t savedattr, savedbkgdattr;

sys/dev/wscons/wsemulvar.h

67

int, int, uint32_t);

sys/dev/wscons/wsemulvar.h

69

int, int, void *, uint32_t);

sys/dev/wscons/wsemulvar.h

81

uint32_t inchar; /* character being reconstructed */

sys/dev/wscons/wsemulvar.h

82

uint32_t lbound; /* lower bound of above */

sys/dev/wscons/wsemulvar.h

85

uint32_t last_output; /* last printable character */

sys/dev/wscons/wsmux.c

885

uint32_t

sys/dev/wscons/wsmux.c

892

wsmux_set_layout(struct wsmux_softc *sc, uint32_t layout)

sys/dev/wscons/wsmuxvar.h

97

uint32_t wsmux_get_layout(struct wsmux_softc *);

sys/dev/wscons/wsmuxvar.h

98

void wsmux_set_layout(struct wsmux_softc *, uint32_t);

sys/dev/x86emu/x86emu.c

1006

static uint32_t

sys/dev/x86emu/x86emu.c

101

static void cmp_long_no_return (struct x86emu *, uint32_t d, uint32_t s);

sys/dev/x86emu/x86emu.c

1026

uint32_t

sys/dev/x86emu/x86emu.c

1058

static uint32_t

sys/dev/x86emu/x86emu.c

106

static uint32_t dec_long (struct x86emu *, uint32_t d);

sys/dev/x86emu/x86emu.c

109

static uint32_t inc_long (struct x86emu *, uint32_t d);

sys/dev/x86emu/x86emu.c

1090

write_back_long(struct x86emu *emu, uint32_t val)

sys/dev/x86emu/x86emu.c

112

static uint32_t or_long (struct x86emu *, uint32_t d, uint32_t s);

sys/dev/x86emu/x86emu.c

1120

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

1141

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

115

static uint32_t neg_long (struct x86emu *, uint32_t s);

sys/dev/x86emu/x86emu.c

1159

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

118

static uint32_t rcl_long (struct x86emu *, uint32_t d, uint8_t s);

sys/dev/x86emu/x86emu.c

1180

uint32_t srcoffset;

sys/dev/x86emu/x86emu.c

1195

uint32_t (*binop)(struct x86emu *, uint32_t, uint32_t))

sys/dev/x86emu/x86emu.c

1197

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

1198

uint32_t destval, *destreg, srcval;

sys/dev/x86emu/x86emu.c

121

static uint32_t rcr_long (struct x86emu *, uint32_t d, uint8_t s);

sys/dev/x86emu/x86emu.c

1216

uint32_t (*binop32)(struct x86emu *, uint32_t, uint32_t))

sys/dev/x86emu/x86emu.c

1228

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

124

static uint32_t rol_long (struct x86emu *, uint32_t d, uint8_t s);

sys/dev/x86emu/x86emu.c

1245

void (*binop)(struct x86emu *, uint32_t, uint32_t))

sys/dev/x86emu/x86emu.c

1247

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

1248

uint32_t destval, srcval;

sys/dev/x86emu/x86emu.c

1264

void (*binop32)(struct x86emu *, uint32_t, uint32_t))

sys/dev/x86emu/x86emu.c

127

static uint32_t ror_long (struct x86emu *, uint32_t d, uint8_t s);

sys/dev/x86emu/x86emu.c

1274

uint32_t (*binop)(struct x86emu *, uint32_t, uint32_t))

sys/dev/x86emu/x86emu.c

1276

uint32_t srcoffset;

sys/dev/x86emu/x86emu.c

1277

uint32_t *destreg, srcval;

sys/dev/x86emu/x86emu.c

1294

uint32_t srcoffset;

sys/dev/x86emu/x86emu.c

130

static uint32_t shl_long (struct x86emu *, uint32_t d, uint8_t s);

sys/dev/x86emu/x86emu.c

1311

uint32_t (*binop32)(struct x86emu *, uint32_t, uint32_t))

sys/dev/x86emu/x86emu.c

133

static uint32_t shr_long (struct x86emu *, uint32_t d, uint8_t s);

sys/dev/x86emu/x86emu.c

1332

uint32_t (*binop32)(struct x86emu *, uint32_t, uint32_t))

sys/dev/x86emu/x86emu.c

1335

uint32_t srcval;

sys/dev/x86emu/x86emu.c

136

static uint32_t sar_long (struct x86emu *, uint32_t d, uint8_t s);

sys/dev/x86emu/x86emu.c

1368

uint32_t srcoffset;

sys/dev/x86emu/x86emu.c

1369

uint32_t *destreg, srcval;

sys/dev/x86emu/x86emu.c

138

static uint32_t shld_long (struct x86emu *, uint32_t d, uint32_t fill, uint8_t s);

sys/dev/x86emu/x86emu.c

1395

*destreg = (uint32_t)res;

sys/dev/x86emu/x86emu.c

140

static uint32_t shrd_long (struct x86emu *, uint32_t d, uint32_t fill, uint8_t s);

sys/dev/x86emu/x86emu.c

1401

uint32_t srcoffset;

sys/dev/x86emu/x86emu.c

1404

uint32_t res;

sys/dev/x86emu/x86emu.c

143

static uint32_t sbb_long (struct x86emu *, uint32_t d, uint32_t s);

sys/dev/x86emu/x86emu.c

1456

uint32_t srcoffset;

sys/dev/x86emu/x86emu.c

146

static uint32_t sub_long (struct x86emu *, uint32_t d, uint32_t s);

sys/dev/x86emu/x86emu.c

149

static void test_long (struct x86emu *, uint32_t d, uint32_t s);

sys/dev/x86emu/x86emu.c

1493

uint32_t srcval, *destreg;

sys/dev/x86emu/x86emu.c

152

static uint32_t xor_long (struct x86emu *, uint32_t d, uint32_t s);

sys/dev/x86emu/x86emu.c

1541

uint32_t srcval;

sys/dev/x86emu/x86emu.c

155

static void imul_long (struct x86emu *, uint32_t s);

sys/dev/x86emu/x86emu.c

1573

uint32_t old_sp = emu->x86.R_ESP;

sys/dev/x86emu/x86emu.c

158

static void mul_long (struct x86emu *, uint32_t s);

sys/dev/x86emu/x86emu.c

161

static void idiv_long (struct x86emu *, uint32_t s);

sys/dev/x86emu/x86emu.c

1636

uint32_t imm;

sys/dev/x86emu/x86emu.c

164

static void div_long (struct x86emu *, uint32_t s);

sys/dev/x86emu/x86emu.c

168

static void push_long (struct x86emu *, uint32_t w);

sys/dev/x86emu/x86emu.c

170

static uint32_t pop_long (struct x86emu *);

sys/dev/x86emu/x86emu.c

1803

uint32_t(* const opc81_long_operation[])

sys/dev/x86emu/x86emu.c

1804

(struct x86emu *, uint32_t d, uint32_t s) =

sys/dev/x86emu/x86emu.c

1823

uint32_t destval, imm;

sys/dev/x86emu/x86emu.c

1917

uint32_t(* const opc83_long_operation[])

sys/dev/x86emu/x86emu.c

1918

(struct x86emu *, uint32_t s, uint32_t d) =

sys/dev/x86emu/x86emu.c

1937

uint32_t destval, imm;

sys/dev/x86emu/x86emu.c

1994

uint32_t *srcreg, destval, tmp;

sys/dev/x86emu/x86emu.c

2036

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

2056

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

2057

uint32_t *destreg, srcval;

sys/dev/x86emu/x86emu.c

2073

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

2118

uint32_t *destreg;

sys/dev/x86emu/x86emu.c

2140

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

2160

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

2168

uint32_t *srcreg;

sys/dev/x86emu/x86emu.c

2171

*srcreg = (uint32_t) destoffset;

sys/dev/x86emu/x86emu.c

2207

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

2208

uint32_t destval, *destreg;

sys/dev/x86emu/x86emu.c

2224

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

2254

uint32_t tmp;

sys/dev/x86emu/x86emu.c

2274

uint32_t tmp;

sys/dev/x86emu/x86emu.c

2294

uint32_t tmp;

sys/dev/x86emu/x86emu.c

2314

uint32_t tmp;

sys/dev/x86emu/x86emu.c

2334

uint32_t tmp;

sys/dev/x86emu/x86emu.c

2354

uint32_t tmp;

sys/dev/x86emu/x86emu.c

2374

uint32_t tmp;

sys/dev/x86emu/x86emu.c

2460

uint32_t flags;

sys/dev/x86emu/x86emu.c

2579

uint32_t count;

sys/dev/x86emu/x86emu.c

2609

uint32_t val;

sys/dev/x86emu/x86emu.c

2611

uint32_t count;

sys/dev/x86emu/x86emu.c

2702

uint32_t val1, val2;

sys/dev/x86emu/x86emu.c

2826

uint32_t count;

sys/dev/x86emu/x86emu.c

2892

uint32_t count;

sys/dev/x86emu/x86emu.c

2973

uint32_t val;

sys/dev/x86emu/x86emu.c

3187

uint32_t(* const opcD1_long_operation[])

sys/dev/x86emu/x86emu.c

3188

(struct x86emu *, uint32_t s, uint8_t d) =

sys/dev/x86emu/x86emu.c

3216

uint32_t destval;

sys/dev/x86emu/x86emu.c

3254

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

3278

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

3279

uint32_t imm, *destreg;

sys/dev/x86emu/x86emu.c

3299

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

3459

uint32_t destval;

sys/dev/x86emu/x86emu.c

3499

uint32_t destval;

sys/dev/x86emu/x86emu.c

366

static uint32_t

sys/dev/x86emu/x86emu.c

369

uint32_t fetched;

sys/dev/x86emu/x86emu.c

3945

uint32_t destval, srcval;

sys/dev/x86emu/x86emu.c

3955

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

4004

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

405

static uint32_t

sys/dev/x86emu/x86emu.c

4057

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

4096

uint32_t destoffset = 0;

sys/dev/x86emu/x86emu.c

4097

uint32_t destval, *destreg;

sys/dev/x86emu/x86emu.c

4134

uint32_t destoffset = 0;

sys/dev/x86emu/x86emu.c

4173

uint32_t destoffset = 0;

sys/dev/x86emu/x86emu.c

444

fetch_data_byte(struct x86emu *emu, uint32_t offset)

sys/dev/x86emu/x86emu.c

459

fetch_data_word(struct x86emu *emu, uint32_t offset)

sys/dev/x86emu/x86emu.c

46

static uint32_t fetch_long_imm (struct x86emu *);

sys/dev/x86emu/x86emu.c

47

static uint8_t fetch_data_byte (struct x86emu *, uint32_t offset);

sys/dev/x86emu/x86emu.c

473

static uint32_t

sys/dev/x86emu/x86emu.c

474

fetch_data_long(struct x86emu *emu, uint32_t offset)

sys/dev/x86emu/x86emu.c

48

static uint8_t fetch_byte (struct x86emu *, uint segment, uint32_t offset);

sys/dev/x86emu/x86emu.c

49

static uint16_t fetch_data_word (struct x86emu *, uint32_t offset);

sys/dev/x86emu/x86emu.c

490

fetch_byte(struct x86emu *emu, uint32_t segment, uint32_t offset)

sys/dev/x86emu/x86emu.c

492

return (*emu->emu_rdb) (emu, ((uint32_t) segment << 4) + offset);

sys/dev/x86emu/x86emu.c

50

static uint16_t fetch_word (struct x86emu *, uint32_t segment, uint32_t offset);

sys/dev/x86emu/x86emu.c

5045

uint32_t destoffset;

sys/dev/x86emu/x86emu.c

506

fetch_word(struct x86emu *emu, uint32_t segment, uint32_t offset)

sys/dev/x86emu/x86emu.c

5063

uint32_t srcval, *shiftreg, mask;

sys/dev/x86emu/x86emu.c

508

return (*emu->emu_rdw) (emu, ((uint32_t) segment << 4) + offset);

sys/dev/x86emu/x86emu.c

51

static uint32_t fetch_data_long (struct x86emu *, uint32_t offset);

sys/dev/x86emu/x86emu.c

5127

uint32_t srcval, *dstreg;

sys/dev/x86emu/x86emu.c

5167

uint32_t destval, *shiftreg;

sys/dev/x86emu/x86emu.c

52

static uint32_t fetch_long (struct x86emu *, uint32_t segment, uint32_t offset);

sys/dev/x86emu/x86emu.c

521

static uint32_t

sys/dev/x86emu/x86emu.c

522

fetch_long(struct x86emu *emu, uint32_t segment, uint32_t offset)

sys/dev/x86emu/x86emu.c

524

return (*emu->emu_rdl) (emu, ((uint32_t) segment << 4) + offset);

sys/dev/x86emu/x86emu.c

5257

hw_cpuid(uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *d)

sys/dev/x86emu/x86emu.c

53

static void store_data_byte (struct x86emu *, uint32_t offset, uint8_t val);

sys/dev/x86emu/x86emu.c

5386

uint32_t *destreg, srcval;

sys/dev/x86emu/x86emu.c

539

store_data_byte(struct x86emu *emu, uint32_t offset, uint8_t val)

sys/dev/x86emu/x86emu.c

54

static void store_byte (struct x86emu *, uint32_t segment, uint32_t offset, uint8_t val);

sys/dev/x86emu/x86emu.c

5400

*destreg = (uint32_t) res;

sys/dev/x86emu/x86emu.c

5407

uint32_t res;

sys/dev/x86emu/x86emu.c

5479

uint32_t *destreg;

sys/dev/x86emu/x86emu.c

55

static void store_data_word (struct x86emu *, uint32_t offset, uint16_t val);

sys/dev/x86emu/x86emu.c

5512

uint32_t *destreg;

sys/dev/x86emu/x86emu.c

5527

uint32_t srcval, mask;

sys/dev/x86emu/x86emu.c

556

store_data_word(struct x86emu *emu, uint32_t offset, uint16_t val)

sys/dev/x86emu/x86emu.c

56

static void store_word (struct x86emu *, uint32_t segment, uint32_t offset, uint16_t val);

sys/dev/x86emu/x86emu.c

5627

uint32_t *destreg;

sys/dev/x86emu/x86emu.c

5660

uint32_t *destreg;

sys/dev/x86emu/x86emu.c

57

static void store_data_long (struct x86emu *, uint32_t offset, uint32_t val);

sys/dev/x86emu/x86emu.c

573

store_data_long(struct x86emu *emu, uint32_t offset, uint32_t val)

sys/dev/x86emu/x86emu.c

58

static void store_long (struct x86emu *, uint32_t segment, uint32_t offset, uint32_t val);

sys/dev/x86emu/x86emu.c

590

store_byte(struct x86emu *emu, uint32_t segment, uint32_t offset, uint8_t val)

sys/dev/x86emu/x86emu.c

592

(*emu->emu_wrb) (emu, ((uint32_t) segment << 4) + offset, val);

sys/dev/x86emu/x86emu.c

5965

static uint32_t x86emu_parity_tab[8] =

sys/dev/x86emu/x86emu.c

607

store_word(struct x86emu *emu, uint32_t segment, uint32_t offset, uint16_t val)

sys/dev/x86emu/x86emu.c

6080

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

6081

uint32_t cc;

sys/dev/x86emu/x86emu.c

609

(*emu->emu_wrw) (emu, ((uint32_t) segment << 4) + offset, val);

sys/dev/x86emu/x86emu.c

61

static uint32_t* decode_rl_long_register(struct x86emu *);

sys/dev/x86emu/x86emu.c

6107

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

6108

uint32_t cc;

sys/dev/x86emu/x86emu.c

6131

static uint32_t

sys/dev/x86emu/x86emu.c

6132

adc_long(struct x86emu *emu, uint32_t d, uint32_t s)

sys/dev/x86emu/x86emu.c

6134

uint32_t lo; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

6135

uint32_t hi;

sys/dev/x86emu/x86emu.c

6136

uint32_t res;

sys/dev/x86emu/x86emu.c

6137

uint32_t cc;

sys/dev/x86emu/x86emu.c

6167

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

6168

uint32_t cc;

sys/dev/x86emu/x86emu.c

6190

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

6191

uint32_t cc;

sys/dev/x86emu/x86emu.c

6210

static uint32_t

sys/dev/x86emu/x86emu.c

6211

add_long(struct x86emu *emu, uint32_t d, uint32_t s)

sys/dev/x86emu/x86emu.c

6213

uint32_t lo; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

6214

uint32_t hi;

sys/dev/x86emu/x86emu.c

6215

uint32_t res;

sys/dev/x86emu/x86emu.c

6216

uint32_t cc;

sys/dev/x86emu/x86emu.c

624

store_long(struct x86emu *emu, uint32_t segment, uint32_t offset, uint32_t val)

sys/dev/x86emu/x86emu.c

626

(*emu->emu_wrl) (emu, ((uint32_t) segment << 4) + offset, val);

sys/dev/x86emu/x86emu.c

6281

static uint32_t

sys/dev/x86emu/x86emu.c

6282

and_long(struct x86emu *emu, uint32_t d, uint32_t s)

sys/dev/x86emu/x86emu.c

6284

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

6305

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

6306

uint32_t bc;

sys/dev/x86emu/x86emu.c

6335

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

6336

uint32_t bc;

sys/dev/x86emu/x86emu.c

6361

static uint32_t

sys/dev/x86emu/x86emu.c

6362

cmp_long(struct x86emu *emu, uint32_t d, uint32_t s)

sys/dev/x86emu/x86emu.c

6364

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

6365

uint32_t bc;

sys/dev/x86emu/x86emu.c

6381

cmp_long_no_return(struct x86emu *emu, uint32_t d, uint32_t s)

sys/dev/x86emu/x86emu.c

6393

uint32_t res = d;

sys/dev/x86emu/x86emu.c

64

static uint32_t* decode_rh_long_register(struct x86emu *);

sys/dev/x86emu/x86emu.c

6436

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

6437

uint32_t bc;

sys/dev/x86emu/x86emu.c

6460

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

6461

uint32_t bc;

sys/dev/x86emu/x86emu.c

6481

static uint32_t

sys/dev/x86emu/x86emu.c

6482

dec_long(struct x86emu *emu, uint32_t d)

sys/dev/x86emu/x86emu.c

6484

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

6485

uint32_t bc;

sys/dev/x86emu/x86emu.c

6508

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

6509

uint32_t cc;

sys/dev/x86emu/x86emu.c

6530

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

6531

uint32_t cc;

sys/dev/x86emu/x86emu.c

6549

static uint32_t

sys/dev/x86emu/x86emu.c

6550

inc_long(struct x86emu *emu, uint32_t d)

sys/dev/x86emu/x86emu.c

6552

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

6553

uint32_t cc;

sys/dev/x86emu/x86emu.c

66

static uint32_t decode_rl_address(struct x86emu *);

sys/dev/x86emu/x86emu.c

6610

static uint32_t

sys/dev/x86emu/x86emu.c

6611

or_long(struct x86emu *emu, uint32_t d, uint32_t s)

sys/dev/x86emu/x86emu.c

6613

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

6684

static uint32_t

sys/dev/x86emu/x86emu.c

6685

neg_long(struct x86emu *emu, uint32_t s)

sys/dev/x86emu/x86emu.c

6687

uint32_t res;

sys/dev/x86emu/x86emu.c

6688

uint32_t bc;

sys/dev/x86emu/x86emu.c

6691

res = (uint32_t) - s;

sys/dev/x86emu/x86emu.c

6807

static uint32_t

sys/dev/x86emu/x86emu.c

6808

rcl_long(struct x86emu *emu, uint32_t d, uint8_t s)

sys/dev/x86emu/x86emu.c

6810

uint32_t res, cnt, mask, cf;

sys/dev/x86emu/x86emu.c

6835

uint32_t res, cnt;

sys/dev/x86emu/x86emu.c

6836

uint32_t mask, cf, ocf = 0;

sys/dev/x86emu/x86emu.c

6913

uint32_t res, cnt;

sys/dev/x86emu/x86emu.c

6914

uint32_t mask, cf, ocf = 0;

sys/dev/x86emu/x86emu.c

6943

static uint32_t

sys/dev/x86emu/x86emu.c

6944

rcr_long(struct x86emu *emu, uint32_t d, uint8_t s)

sys/dev/x86emu/x86emu.c

6946

uint32_t res, cnt;

sys/dev/x86emu/x86emu.c

6947

uint32_t mask, cf, ocf = 0;

sys/dev/x86emu/x86emu.c

70

static uint32_t decode_and_fetch_long(struct x86emu *);

sys/dev/x86emu/x86emu.c

7050

static uint32_t

sys/dev/x86emu/x86emu.c

7051

rol_long(struct x86emu *emu, uint32_t d, uint8_t s)

sys/dev/x86emu/x86emu.c

7053

uint32_t res, cnt, mask;

sys/dev/x86emu/x86emu.c

7144

static uint32_t

sys/dev/x86emu/x86emu.c

7145

ror_long(struct x86emu *emu, uint32_t d, uint8_t s)

sys/dev/x86emu/x86emu.c

7147

uint32_t res, cnt, mask;

sys/dev/x86emu/x86emu.c

7254

static uint32_t

sys/dev/x86emu/x86emu.c

7255

shl_long(struct x86emu *emu, uint32_t d, uint8_t s)

sys/dev/x86emu/x86emu.c

736

static uint32_t *

sys/dev/x86emu/x86emu.c

7368

static uint32_t

sys/dev/x86emu/x86emu.c

7369

shr_long(struct x86emu *emu, uint32_t d, uint8_t s)

sys/dev/x86emu/x86emu.c

74

static uint32_t decode_and_fetch_long_imm8(struct x86emu *, uint8_t *);

sys/dev/x86emu/x86emu.c

7487

static uint32_t

sys/dev/x86emu/x86emu.c

7488

sar_long(struct x86emu *emu, uint32_t d, uint8_t s)

sys/dev/x86emu/x86emu.c

7490

uint32_t cnt, res, cf, mask, sf;

sys/dev/x86emu/x86emu.c

7566

static uint32_t

sys/dev/x86emu/x86emu.c

7567

shld_long(struct x86emu *emu, uint32_t d, uint32_t fill, uint8_t s)

sys/dev/x86emu/x86emu.c

761

static uint32_t *

sys/dev/x86emu/x86emu.c

7642

static uint32_t

sys/dev/x86emu/x86emu.c

7643

shrd_long(struct x86emu *emu, uint32_t d, uint32_t fill, uint8_t s)

sys/dev/x86emu/x86emu.c

767

static uint32_t *

sys/dev/x86emu/x86emu.c

7682

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

7683

uint32_t bc;

sys/dev/x86emu/x86emu.c

77

static uint32_t decode_and_fetch_long_disp(struct x86emu *, int16_t);

sys/dev/x86emu/x86emu.c

7708

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

7709

uint32_t bc;

sys/dev/x86emu/x86emu.c

7731

static uint32_t

sys/dev/x86emu/x86emu.c

7732

sbb_long(struct x86emu *emu, uint32_t d, uint32_t s)

sys/dev/x86emu/x86emu.c

7734

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

7735

uint32_t bc;

sys/dev/x86emu/x86emu.c

7760

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

7761

uint32_t bc;

sys/dev/x86emu/x86emu.c

7783

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

7784

uint32_t bc;

sys/dev/x86emu/x86emu.c

7803

static uint32_t

sys/dev/x86emu/x86emu.c

7804

sub_long(struct x86emu *emu, uint32_t d, uint32_t s)

sys/dev/x86emu/x86emu.c

7806

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

7807

uint32_t bc;

sys/dev/x86emu/x86emu.c

7829

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

7848

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

7865

test_long(struct x86emu *emu, uint32_t d, uint32_t s)

sys/dev/x86emu/x86emu.c

7867

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

7921

static uint32_t

sys/dev/x86emu/x86emu.c

7922

xor_long(struct x86emu *emu, uint32_t d, uint32_t s)

sys/dev/x86emu/x86emu.c

7924

uint32_t res; /* all operands in native machine order */

sys/dev/x86emu/x86emu.c

7982

imul_long(struct x86emu *emu, uint32_t s)

sys/dev/x86emu/x86emu.c

7987

emu->x86.R_EAX = (uint32_t)res;

sys/dev/x86emu/x86emu.c

8025

uint32_t res = emu->x86.R_AX * s;

sys/dev/x86emu/x86emu.c

8043

mul_long(struct x86emu *emu, uint32_t s)

sys/dev/x86emu/x86emu.c

8047

emu->x86.R_EAX = (uint32_t) res;

sys/dev/x86emu/x86emu.c

8048

emu->x86.R_EDX = (uint32_t) (res >> 32);

sys/dev/x86emu/x86emu.c

81

static void write_back_long(struct x86emu *, uint32_t);

sys/dev/x86emu/x86emu.c

810

static uint32_t

sys/dev/x86emu/x86emu.c

8117

idiv_long(struct x86emu *emu, uint32_t s)

sys/dev/x86emu/x86emu.c

813

uint32_t base = 0, i = 0, scale = 1;

sys/dev/x86emu/x86emu.c

8138

emu->x86.R_EAX = (uint32_t) div;

sys/dev/x86emu/x86emu.c

8139

emu->x86.R_EDX = (uint32_t) mod;

sys/dev/x86emu/x86emu.c

8149

uint32_t dvd, div, mod;

sys/dev/x86emu/x86emu.c

8173

uint32_t dvd, div, mod;

sys/dev/x86emu/x86emu.c

8175

dvd = (((uint32_t) emu->x86.R_DX) << 16) | emu->x86.R_AX;

sys/dev/x86emu/x86emu.c

8200

div_long(struct x86emu *emu, uint32_t s)

sys/dev/x86emu/x86emu.c

8209

div = dvd / (uint32_t) s;

sys/dev/x86emu/x86emu.c

8210

mod = dvd % (uint32_t) s;

sys/dev/x86emu/x86emu.c

8221

emu->x86.R_EAX = (uint32_t) div;

sys/dev/x86emu/x86emu.c

8222

emu->x86.R_EDX = (uint32_t) mod;

sys/dev/x86emu/x86emu.c

8240

uint32_t count = ((emu->x86.mode & SYSMODE_PREFIX_DATA) ?

sys/dev/x86emu/x86emu.c

8305

uint32_t count = ((emu->x86.mode & SYSMODE_PREFIX_DATA) ?

sys/dev/x86emu/x86emu.c

8378

push_long(struct x86emu *emu, uint32_t w)

sys/dev/x86emu/x86emu.c

8406

static uint32_t

sys/dev/x86emu/x86emu.c

8409

uint32_t res;

sys/dev/x86emu/x86emu.c

889

static uint32_t

sys/dev/x86emu/x86emu.c

89

static uint32_t adc_long (struct x86emu *, uint32_t d, uint32_t s);

sys/dev/x86emu/x86emu.c

893

uint32_t offset, sib;

sys/dev/x86emu/x86emu.c

92

static uint32_t add_long (struct x86emu *, uint32_t d, uint32_t s);

sys/dev/x86emu/x86emu.c

95

static uint32_t and_long (struct x86emu *, uint32_t d, uint32_t s);

sys/dev/x86emu/x86emu.c

98

static uint32_t cmp_long (struct x86emu *, uint32_t d, uint32_t s);

sys/dev/x86emu/x86emu.h

107

uint32_t register_flags;

sys/dev/x86emu/x86emu.h

131

uint32_t mode;

sys/dev/x86emu/x86emu.h

154

uint32_t cur_offset;

sys/dev/x86emu/x86emu.h

156

uint8_t (*emu_rdb)(struct x86emu *, uint32_t addr);

sys/dev/x86emu/x86emu.h

157

uint16_t (*emu_rdw)(struct x86emu *, uint32_t addr);

sys/dev/x86emu/x86emu.h

158

uint32_t (*emu_rdl)(struct x86emu *, uint32_t addr);

sys/dev/x86emu/x86emu.h

159

void (*emu_wrb)(struct x86emu *, uint32_t addr,uint8_t val);

sys/dev/x86emu/x86emu.h

160

void (*emu_wrw)(struct x86emu *, uint32_t addr, uint16_t val);

sys/dev/x86emu/x86emu.h

161

void (*emu_wrl)(struct x86emu *, uint32_t addr, uint32_t val);

sys/dev/x86emu/x86emu.h

165

uint32_t (*emu_inl)(struct x86emu *, uint16_t addr);

sys/dev/x86emu/x86emu.h

168

void (*emu_outl)(struct x86emu *, uint16_t addr, uint32_t val);

sys/dev/x86emu/x86emu.h

65

uint32_t e_reg;

sys/dev/x86emu/x86emu.h

81

uint32_t e_reg;

sys/dev/x86emu/x86emu_util.c

100

rdl(struct x86emu *emu, uint32_t addr)

sys/dev/x86emu/x86emu_util.c

130

wrb(struct x86emu *emu, uint32_t addr, uint8_t val)

sys/dev/x86emu/x86emu_util.c

146

wrw(struct x86emu *emu, uint32_t addr, uint16_t val)

sys/dev/x86emu/x86emu_util.c

172

wrl(struct x86emu *emu, uint32_t addr, uint32_t val)

sys/dev/x86emu/x86emu_util.c

53

rdb(struct x86emu *emu, uint32_t addr)

sys/dev/x86emu/x86emu_util.c

71

rdw(struct x86emu *emu, uint32_t addr)

sys/dev/x86emu/x86emu_util.c

99

static uint32_t

sys/isofs/cd9660/iso.h

46

typedef uint32_t cdino_t;

sys/isofs/udf/ecma167-udf.h

123

uint32_t tag_loc;

sys/isofs/udf/ecma167-udf.h

130

uint32_t lb_num;

sys/isofs/udf/ecma167-udf.h

137

uint32_t len;

sys/isofs/udf/ecma167-udf.h

138

uint32_t loc;

sys/isofs/udf/ecma167-udf.h

144

uint32_t len;

sys/isofs/udf/ecma167-udf.h

145

uint32_t lb_num;

sys/isofs/udf/ecma167-udf.h

152

uint32_t unique_id;

sys/isofs/udf/ecma167-udf.h

158

uint32_t len;

sys/isofs/udf/ecma167-udf.h

170

uint32_t ex_len;

sys/isofs/udf/ecma167-udf.h

171

uint32_t rec_len;

sys/isofs/udf/ecma167-udf.h

172

uint32_t inf_len;

sys/isofs/udf/ecma167-udf.h

246

uint32_t prev_num_dirs;

sys/isofs/udf/ecma167-udf.h

301

uint32_t vds_number;

sys/isofs/udf/ecma167-udf.h

309

uint32_t seq_num; /* MAX prevail */

sys/isofs/udf/ecma167-udf.h

310

uint32_t pvd_num; /* assigned by author; 0 is special as in it may only occur once */

sys/isofs/udf/ecma167-udf.h

316

uint32_t charset_list;

sys/isofs/udf/ecma167-udf.h

317

uint32_t max_charset_list;

sys/isofs/udf/ecma167-udf.h

327

uint32_t prev_vds_loc; /* location of predecessor _lov ? */

sys/isofs/udf/ecma167-udf.h

350

uint32_t seq_num;

sys/isofs/udf/ecma167-udf.h

362

uint32_t seq_num; /* MAX prevail */

sys/isofs/udf/ecma167-udf.h

365

uint32_t lb_size;

sys/isofs/udf/ecma167-udf.h

371

uint32_t mt_l; /* Partition map length */

sys/isofs/udf/ecma167-udf.h

372

uint32_t n_pm; /* Number of partition maps */

sys/isofs/udf/ecma167-udf.h

430

uint32_t st_size; /* size of EACH sparing table */

sys/isofs/udf/ecma167-udf.h

431

uint32_t st_loc[1]; /* locations of sparing tables */

sys/isofs/udf/ecma167-udf.h

443

uint32_t meta_file_lbn; /* logical block number for file entry within part_num */

sys/isofs/udf/ecma167-udf.h

444

uint32_t meta_mirror_file_lbn;

sys/isofs/udf/ecma167-udf.h

445

uint32_t meta_bitmap_file_lbn;

sys/isofs/udf/ecma167-udf.h

446

uint32_t alloc_unit_size; /* allocation unit size in blocks */

sys/isofs/udf/ecma167-udf.h

466

uint32_t org; /* partition relative address */

sys/isofs/udf/ecma167-udf.h

467

uint32_t map; /* absolute disc address (!) can be in partition, but doesn't have to be */

sys/isofs/udf/ecma167-udf.h

477

uint32_t seq_num;

sys/isofs/udf/ecma167-udf.h

486

uint32_t prev_vat;

sys/isofs/udf/ecma167-udf.h

495

uint32_t prev_vat;

sys/isofs/udf/ecma167-udf.h

496

uint32_t num_files;

sys/isofs/udf/ecma167-udf.h

497

uint32_t num_directories;

sys/isofs/udf/ecma167-udf.h

509

uint32_t num_bits; /* number of bits */

sys/isofs/udf/ecma167-udf.h

510

uint32_t num_bytes; /* bytes that contain it */

sys/isofs/udf/ecma167-udf.h

519

uint32_t l_ad; /* in bytes */

sys/isofs/udf/ecma167-udf.h

538

uint32_t seq_num; /* MAX prevailing */

sys/isofs/udf/ecma167-udf.h

546

uint32_t access_type; /* R/W, WORM etc. */

sys/isofs/udf/ecma167-udf.h

547

uint32_t start_loc; /* start of partition with given length */

sys/isofs/udf/ecma167-udf.h

548

uint32_t part_len;

sys/isofs/udf/ecma167-udf.h

560

uint32_t seq_num; /* MAX prevailing */

sys/isofs/udf/ecma167-udf.h

561

uint32_t alloc_desc_num;

sys/isofs/udf/ecma167-udf.h

575

uint32_t num_files;

sys/isofs/udf/ecma167-udf.h

576

uint32_t num_directories;

sys/isofs/udf/ecma167-udf.h

586

uint32_t integrity_type;

sys/isofs/udf/ecma167-udf.h

592

uint32_t num_part;

sys/isofs/udf/ecma167-udf.h

593

uint32_t l_iu;

sys/isofs/udf/ecma167-udf.h

594

uint32_t tables[1]; /* Freespace table, Sizetable, Implementation use */

sys/isofs/udf/ecma167-udf.h

605

uint32_t charset_list;

sys/isofs/udf/ecma167-udf.h

606

uint32_t max_charset_list;

sys/isofs/udf/ecma167-udf.h

607

uint32_t fileset_num; /* key! */

sys/isofs/udf/ecma167-udf.h

608

uint32_t fileset_desc_num;

sys/isofs/udf/ecma167-udf.h

644

uint32_t impl_attr_loc; /* offsets within this descriptor */

sys/isofs/udf/ecma167-udf.h

645

uint32_t appl_attr_loc; /* ditto */

sys/isofs/udf/ecma167-udf.h

653

uint32_t type;

sys/isofs/udf/ecma167-udf.h

656

uint32_t a_l;

sys/isofs/udf/ecma167-udf.h

663

uint32_t iu_l;

sys/isofs/udf/ecma167-udf.h

672

uint32_t au_l;

sys/isofs/udf/ecma167-udf.h

681

uint32_t d_l; /* length of times[] data following */

sys/isofs/udf/ecma167-udf.h

682

uint32_t existence; /* bitmask */

sys/isofs/udf/ecma167-udf.h

696

uint32_t iu_l; /* length of implementation use */

sys/isofs/udf/ecma167-udf.h

697

uint32_t major;

sys/isofs/udf/ecma167-udf.h

698

uint32_t minor;

sys/isofs/udf/ecma167-udf.h

707

uint32_t num_files;

sys/isofs/udf/ecma167-udf.h

708

uint32_t num_directories;

sys/isofs/udf/ecma167-udf.h

717

uint32_t uid;

sys/isofs/udf/ecma167-udf.h

718

uint32_t gid;

sys/isofs/udf/ecma167-udf.h

719

uint32_t perm;

sys/isofs/udf/ecma167-udf.h

723

uint32_t rec_len;

sys/isofs/udf/ecma167-udf.h

729

uint32_t ckpoint;

sys/isofs/udf/ecma167-udf.h

733

uint32_t l_ea; /* Length of extended attribute area */

sys/isofs/udf/ecma167-udf.h

734

uint32_t l_ad; /* Length of allocation descriptors */

sys/isofs/udf/ecma167-udf.h

747

uint32_t uid;

sys/isofs/udf/ecma167-udf.h

748

uint32_t gid;

sys/isofs/udf/ecma167-udf.h

749

uint32_t perm;

sys/isofs/udf/ecma167-udf.h

753

uint32_t rec_len;

sys/isofs/udf/ecma167-udf.h

761

uint32_t ckpoint;

sys/isofs/udf/ecma167-udf.h

762

uint32_t reserved1;

sys/isofs/udf/ecma167-udf.h

767

uint32_t l_ea; /* Length of extended attribute area */

sys/isofs/udf/ecma167-udf.h

768

uint32_t l_ad; /* Length of allocation descriptors */

sys/isofs/udf/ecma167-udf.h

785

uint32_t prev_entry;

sys/isofs/udf/ecma167-udf.h

786

uint32_t l_ad;

sys/isofs/udf/udf.h

37

typedef uint32_t udfino_t;

sys/isofs/udf/udf.h

65

uint32_t um_start;

sys/isofs/udf/udf.h

66

uint32_t um_realstart;

sys/isofs/udf/udf.h

67

uint32_t um_len;

sys/isofs/udf/udf.h

68

uint32_t um_reallen;

sys/isofs/udf/udf.h

69

uint32_t um_meta_start;

sys/isofs/udf/udf.h

70

uint32_t um_meta_len;

sys/isofs/udf/udf_extern.h

14

int udf_vat_get(struct umount *, uint32_t);

sys/isofs/udf/udf_extern.h

15

int udf_vat_map(struct umount *, uint32_t *);

sys/isofs/udf/udf_subr.c

190

udf_vat_get(struct umount *ump, uint32_t lb)

sys/isofs/udf/udf_subr.c

216

udf_vat_map(struct umount *ump, uint32_t *sector)

sys/isofs/udf/udf_subr.c

233

udf_vat_read(struct umount *ump, uint32_t *sector)

sys/isofs/udf/udf_subr.c

262

*sector = letoh32(*(uint32_t *)data) + ump->um_start;

sys/isofs/udf/udf_subr.c

48

int udf_vat_read(struct umount *, uint32_t *);

sys/isofs/udf/udf_subr.c

99

uint32_t sector = 256, mvds_start, mvds_end;

sys/isofs/udf/udf_vfsops.c

212

udf_mountfs(struct vnode *devvp, struct mount *mp, uint32_t lb, struct proc *p)

sys/isofs/udf/udf_vfsops.c

222

uint32_t sector, size, mvds_start, mvds_end;

sys/isofs/udf/udf_vfsops.c

223

uint32_t fsd_offset = 0;

sys/isofs/udf/udf_vfsops.c

554

uint32_t sector;

sys/isofs/udf/udf_vfsops.c

82

int udf_mountfs(struct vnode *, struct mount *, uint32_t, struct proc *);

sys/isofs/udf/udf_vnops.c

1224

uint32_t max_size;

sys/isofs/udf/udf_vnops.c

1273

uint32_t *max_size)

sys/isofs/udf/udf_vnops.c

1280

uint32_t icblen = 0;

sys/isofs/udf/udf_vnops.c

196

uint32_t perm;

sys/isofs/udf/udf_vnops.c

58

int udf_bmap_internal(struct unode *, off_t, daddr_t *, uint32_t *);

sys/isofs/udf/udf_vnops.c

968

uint32_t max_size;

sys/kern/kern_clock.c

89

uint32_t statclock_mask; /* [I] set of allowed offsets */

sys/kern/kern_clock.c

99

uint32_t var;

sys/kern/kern_clockintr.c

165

uint32_t ogen;

sys/kern/kern_clockintr.c

299

uint32_t mask)

sys/kern/kern_clockintr.c

303

uint32_t off;

sys/kern/kern_clockintr.c

367

clockintr_unbind(struct clockintr *cl, uint32_t flags)

sys/kern/kern_clockintr.c

421

clockintr_stagger(struct clockintr *cl, uint64_t period, uint32_t numer,

sys/kern/kern_clockintr.c

422

uint32_t denom)

sys/kern/kern_clockintr.c

570

uint32_t gen;

sys/kern/kern_fork.c

654

uint32_t i;

sys/kern/kern_fork.c

695

static uint32_t idx;

sys/kern/kern_malloc.c

323

uint32_t pval;

sys/kern/kern_synch.c

718

const uint32_t *abortp = SCARG(uap, abort);

sys/kern/kern_synch.c

762

uint32_t abort;

sys/kern/kern_timeout.c

205

uint32_t timeout_bucket(const struct timeout *);

sys/kern/kern_timeout.c

206

uint32_t timeout_maskwheel(uint32_t, const struct timespec *);

sys/kern/kern_timeout.c

552

uint32_t

sys/kern/kern_timeout.c

557

uint32_t level;

sys/kern/kern_timeout.c

584

uint32_t

sys/kern/kern_timeout.c

585

timeout_maskwheel(uint32_t level, const struct timespec *abstime)

sys/kern/kern_timeout.c

587

uint32_t hi, lo;

sys/kern/kern_uuid.c

71

uint32_t low;

sys/kern/sched_bsd.c

292

uint32_t

sys/kern/sched_bsd.c

293

decay_aftersleep(uint32_t estcpu, uint32_t slptime)

sys/kern/sched_bsd.c

296

uint32_t newcpu;

sys/kern/sched_bsd.c

494

uint32_t newcpu;

sys/kern/sched_bsd.c

506

setpriority(struct proc *p, uint32_t newcpu, uint8_t nice)

sys/kern/sched_bsd.c

536

uint32_t newcpu;

sys/kern/sched_bsd.c

63

uint32_t decay_aftersleep(uint32_t, uint32_t);

sys/kern/subr_disk.c

418

uint32_t psize;

sys/kern/subr_disk.c

448

uint32_t csum;

sys/kern/subr_disk.c

449

uint32_t size, partsize;

sys/kern/subr_disk.c

486

uint32_t partnum, partsize, partcsum;

sys/kern/subr_disk.c

593

uint32_t partnum;

sys/kern/subr_disk.c

735

uint32_t extoff = 0;

sys/kern/subr_kubsan.c

128

uint32_t sl_line;

sys/kern/subr_kubsan.c

129

uint32_t sl_column;

sys/kern/subr_kubsan.c

445

return ((uint32_t)val);

sys/kern/subr_kubsan.c

508

uint32_t *line = &src->sl_line;

sys/kern/subr_kubsan.c

509

uint32_t prev;

sys/kern/subr_kubsan.c

757

uint32_t *line = &src->sl_line;

sys/kern/subr_poison.c

36

uint32_t

sys/kern/subr_poison.c

59

uint32_t *ip = v;

sys/kern/subr_poison.c

61

uint32_t poison;

sys/kern/subr_poison.c

73

poison_check(void *v, size_t len, size_t *pidx, uint32_t *pval)

sys/kern/subr_poison.c

75

uint32_t *ip = v;

sys/kern/subr_poison.c

77

uint32_t poison;

sys/kern/subr_pool.c

1003

uint32_t pval;

sys/kern/subr_pool.c

1375

uint32_t pval;

sys/kern/subr_pool.c

1901

uint32_t pval;

sys/kern/subr_pool.c

741

uint32_t pval;

sys/kern/subr_witness.c

235

uint32_t w_index; /* Index in the relationship matrix */

sys/kern/subr_witness.c

2373

static uint32_t

sys/kern/subr_witness.c

2374

witness_hash_djb2(const uint8_t *key, uint32_t size)

sys/kern/subr_witness.c

2429

uint32_t hash;

sys/kern/subr_witness.c

2434

hash = (uint32_t)((uintptr_t)type ^ (uintptr_t)subtype) %

sys/kern/subr_witness.c

2448

uint32_t hash;

sys/kern/subr_witness.c

2459

hash = (uint32_t)((uintptr_t)w->w_type ^ (uintptr_t)w->w_subtype) %

sys/kern/subr_witness.c

259

uint32_t wh_size;

sys/kern/subr_witness.c

260

uint32_t wh_count;

sys/kern/subr_witness.c

353

static uint32_t witness_hash_djb2(const uint8_t *key, uint32_t size);

sys/kern/sys_futex.c

101

static int futex_wait(struct proc *, uint32_t *, uint32_t,

sys/kern/sys_futex.c

103

static int futex_wake(struct proc *, uint32_t *, uint32_t, int,

sys/kern/sys_futex.c

105

static int futex_requeue(struct proc *, uint32_t *, uint32_t,

sys/kern/sys_futex.c

106

uint32_t *, uint32_t, int, register_t *);

sys/kern/sys_futex.c

139

syscallarg(uint32_t *) f;

sys/kern/sys_futex.c

143

syscallarg(uint32_t *) g;

sys/kern/sys_futex.c

145

uint32_t *uaddr = SCARG(uap, f);

sys/kern/sys_futex.c

147

uint32_t val = SCARG(uap, val);

sys/kern/sys_futex.c

173

futex_addrs(struct proc *p, struct futex *f, uint32_t *uaddr, int flags)

sys/kern/sys_futex.c

212

uint32_t key = f->ft_off >> 3; /* watevs */

sys/kern/sys_futex.c

252

futex_wait(struct proc *p, uint32_t *uaddr, uint32_t val,

sys/kern/sys_futex.c

258

uint32_t cval;

sys/kern/sys_futex.c

359

futex_requeue(struct proc *p, uint32_t *uaddr, uint32_t n,

sys/kern/sys_futex.c

360

uint32_t *uaddr2, uint32_t m, int flags, register_t *retval)

sys/kern/sys_futex.c

366

uint32_t count = 0;

sys/kern/sys_futex.c

448

futex_wake(struct proc *p, uint32_t *uaddr, uint32_t n, int flags,

sys/kern/sys_futex.c

97

uint32_t fsq_id; /* [I] for lock ordering */

sys/lib/libkern/crc32c.h

103

static __inline uint32_t

sys/lib/libkern/crc32c.h

104

crc32c_byte(uint32_t ccrc, const uint8_t b)

sys/lib/libkern/crc32c.h

109

static __inline uint32_t __unused

sys/lib/libkern/crc32c.h

110

crc32c(uint32_t crc, const uint8_t *data, size_t len)

sys/lib/libkern/crc32c.h

36

static const uint32_t crc32c_lookup[] = {

sys/lib/libkern/milieu.h

123

typedef uint32_t bits32;

sys/lib/libsa/bcrypt_pbkdf.c

106

uint32_t count;

sys/lib/libsa/bcrypt_pbkdf.c

60

uint32_t cdata[BCRYPT_WORDS];

sys/miscfs/fuse/fusefs.h

42

uint32_t undef_op;

sys/msdosfs/denode.h

106

uint32_t fc_frcn; /* file relative cluster number */

sys/msdosfs/denode.h

107

uint32_t fc_fsrcn; /* filesystem relative cluster number */

sys/msdosfs/denode.h

143

uint32_t de_flag; /* flag bits */

sys/msdosfs/denode.h

145

uint32_t de_dirclust; /* cluster of the directory file containing this entry */

sys/msdosfs/denode.h

146

uint32_t de_diroffset; /* offset of this entry in the directory cluster */

sys/msdosfs/denode.h

147

uint32_t de_fndoffset; /* offset of found dir entry */

sys/msdosfs/denode.h

161

uint32_t de_StartCluster; /* starting cluster of file */

sys/msdosfs/denode.h

162

uint32_t de_FileSize; /* size of file in bytes */

sys/msdosfs/denode.h

251

uint32_t defid_dirclust; /* cluster this dir entry came from */

sys/msdosfs/denode.h

252

uint32_t defid_dirofs; /* offset of entry within the cluster */

sys/msdosfs/denode.h

254

uint32_t defid_gen; /* generation number */

sys/msdosfs/denode.h

298

int deextend(struct denode *, uint32_t, struct ucred *);

sys/msdosfs/denode.h

299

int deget(struct msdosfsmount *, uint32_t, uint32_t, struct denode **);

sys/msdosfs/denode.h

300

int detrunc(struct denode *, uint32_t, int, struct ucred *, struct proc *);

sys/msdosfs/denode.h

305

int readep(struct msdosfsmount *, uint32_t, uint32_t, struct buf **, struct direntry **);

sys/msdosfs/fat.h

100

int fatentry(int, struct msdosfsmount *, uint32_t, uint32_t *, uint32_t);

sys/msdosfs/fat.h

102

void fc_lookup(struct denode *, uint32_t, uint32_t *, uint32_t *);

sys/msdosfs/fat.h

104

int freeclusterchain(struct msdosfsmount *, uint32_t);

sys/msdosfs/fat.h

96

int pcbmap(struct denode *, uint32_t, daddr_t *, uint32_t *, int *);

sys/msdosfs/fat.h

97

int clusterfree(struct msdosfsmount *, uint32_t, uint32_t *);

sys/msdosfs/fat.h

98

int clusteralloc(struct msdosfsmount *, uint32_t, uint32_t, uint32_t *, uint32_t *);

sys/msdosfs/fat.h

99

int extendfile(struct denode *, uint32_t, struct buf **, uint32_t *, int);

sys/msdosfs/msdosfs_conv.c

101

uint32_t days;

sys/msdosfs/msdosfs_conv.c

102

uint32_t inc;

sys/msdosfs/msdosfs_conv.c

103

uint32_t year;

sys/msdosfs/msdosfs_conv.c

104

uint32_t month;

sys/msdosfs/msdosfs_conv.c

176

uint32_t lastseconds;

sys/msdosfs/msdosfs_conv.c

186

uint32_t seconds;

sys/msdosfs/msdosfs_conv.c

187

uint32_t m, month;

sys/msdosfs/msdosfs_conv.c

188

uint32_t y, year;

sys/msdosfs/msdosfs_conv.c

189

uint32_t days;

sys/msdosfs/msdosfs_conv.c

89

uint32_t lastday;

sys/msdosfs/msdosfs_denode.c

103

msdosfs_hashget(dev_t dev, uint32_t dirclust, uint32_t diroff)

sys/msdosfs/msdosfs_denode.c

181

deget(struct msdosfsmount *pmp, uint32_t dirclust, uint32_t diroffset,

sys/msdosfs/msdosfs_denode.c

320

uint32_t size;

sys/msdosfs/msdosfs_denode.c

375

detrunc(struct denode *dep, uint32_t length, int flags, struct ucred *cred,

sys/msdosfs/msdosfs_denode.c

381

uint32_t eofentry;

sys/msdosfs/msdosfs_denode.c

382

uint32_t chaintofree = 0;

sys/msdosfs/msdosfs_denode.c

516

deextend(struct denode *dep, uint32_t length, struct ucred *cred)

sys/msdosfs/msdosfs_denode.c

519

uint32_t count;

sys/msdosfs/msdosfs_denode.c

654

error = detrunc(dep, (uint32_t)0, 0, NOCRED, ap->a_p);

sys/msdosfs/msdosfs_denode.c

70

u_int msdosfs_dehash(dev_t, uint32_t, uint32_t);

sys/msdosfs/msdosfs_denode.c

77

static struct denode *msdosfs_hashget(dev_t, uint32_t, uint32_t);

sys/msdosfs/msdosfs_denode.c

90

msdosfs_dehash(dev_t dev, uint32_t dirclust, uint32_t diroff)

sys/msdosfs/msdosfs_fat.c

100

uint32_t bn, size;

sys/msdosfs/msdosfs_fat.c

135

pcbmap(struct denode *dep, uint32_t findcn, daddr_t *bnp, uint32_t *cnp,

sys/msdosfs/msdosfs_fat.c

139

uint32_t i;

sys/msdosfs/msdosfs_fat.c

140

uint32_t cn;

sys/msdosfs/msdosfs_fat.c

141

uint32_t prevcn = 0; /* XXX: prevcn could be used uninitialized */

sys/msdosfs/msdosfs_fat.c

142

uint32_t byteoffset;

sys/msdosfs/msdosfs_fat.c

143

uint32_t bn;

sys/msdosfs/msdosfs_fat.c

144

uint32_t bo;

sys/msdosfs/msdosfs_fat.c

146

uint32_t bp_bn = -1;

sys/msdosfs/msdosfs_fat.c

148

uint32_t bsize;

sys/msdosfs/msdosfs_fat.c

277

fc_lookup(struct denode *dep, uint32_t findcn, uint32_t *frcnp, uint32_t *fsrcnp)

sys/msdosfs/msdosfs_fat.c

280

uint32_t cn;

sys/msdosfs/msdosfs_fat.c

323

updatefats(struct msdosfsmount *pmp, struct buf *bp, uint32_t fatbn)

sys/msdosfs/msdosfs_fat.c

410

usemap_alloc(struct msdosfsmount *pmp, uint32_t cn)

sys/msdosfs/msdosfs_fat.c

419

usemap_free(struct msdosfsmount *pmp, uint32_t cn)

sys/msdosfs/msdosfs_fat.c

428

clusterfree(struct msdosfsmount *pmp, uint32_t cluster, uint32_t *oldcnp)

sys/msdosfs/msdosfs_fat.c

431

uint32_t oldcn;

sys/msdosfs/msdosfs_fat.c

469

fatentry(int function, struct msdosfsmount *pmp, uint32_t cn, uint32_t *oldcontents,

sys/msdosfs/msdosfs_fat.c

470

uint32_t newcontents)

sys/msdosfs/msdosfs_fat.c

473

uint32_t readcn;

sys/msdosfs/msdosfs_fat.c

474

uint32_t bn, bo, bsize, byteoffset;

sys/msdosfs/msdosfs_fat.c

572

fatchain(struct msdosfsmount *pmp, uint32_t start, uint32_t count, uint32_t fillwith)

sys/msdosfs/msdosfs_fat.c

575

uint32_t bn, bo, bsize, byteoffset, readcn, newc;

sys/msdosfs/msdosfs_fat.c

643

chainlength(struct msdosfsmount *pmp, uint32_t start, uint32_t count)

sys/msdosfs/msdosfs_fat.c

645

uint32_t idx, max_idx;

sys/msdosfs/msdosfs_fat.c

647

uint32_t len;

sys/msdosfs/msdosfs_fat.c

693

chainalloc(struct msdosfsmount *pmp, uint32_t start, uint32_t count,

sys/msdosfs/msdosfs_fat.c

694

uint32_t fillwith, uint32_t *retcluster, uint32_t *got)

sys/msdosfs/msdosfs_fat.c

697

uint32_t cl, n;

sys/msdosfs/msdosfs_fat.c

726

clusteralloc(struct msdosfsmount *pmp, uint32_t start, uint32_t count,

sys/msdosfs/msdosfs_fat.c

727

uint32_t *retcluster, uint32_t *got)

sys/msdosfs/msdosfs_fat.c

729

uint32_t idx;

sys/msdosfs/msdosfs_fat.c

730

uint32_t len, newst, foundl, cn, l;

sys/msdosfs/msdosfs_fat.c

731

uint32_t foundcn = 0; /* XXX: foundcn could be used uninitialized */

sys/msdosfs/msdosfs_fat.c

732

uint32_t fillwith = CLUST_EOFE;

sys/msdosfs/msdosfs_fat.c

813

freeclusterchain(struct msdosfsmount *pmp, uint32_t cluster)

sys/msdosfs/msdosfs_fat.c

817

uint32_t bn, bo, bsize, byteoffset;

sys/msdosfs/msdosfs_fat.c

818

uint32_t readcn, lbn = -1;

sys/msdosfs/msdosfs_fat.c

86

static void fatblock(struct msdosfsmount *, uint32_t, uint32_t *, uint32_t *,

sys/msdosfs/msdosfs_fat.c

87

uint32_t *);

sys/msdosfs/msdosfs_fat.c

875

uint32_t cn, readcn;

sys/msdosfs/msdosfs_fat.c

877

uint32_t bn, bo, bsize, byteoffset;

sys/msdosfs/msdosfs_fat.c

88

void updatefats(struct msdosfsmount *, struct buf *, uint32_t);

sys/msdosfs/msdosfs_fat.c

89

static __inline void usemap_free(struct msdosfsmount *, uint32_t);

sys/msdosfs/msdosfs_fat.c

90

static __inline void usemap_alloc(struct msdosfsmount *, uint32_t);

sys/msdosfs/msdosfs_fat.c

91

static int fatchain(struct msdosfsmount *, uint32_t, uint32_t, uint32_t);

sys/msdosfs/msdosfs_fat.c

92

int chainlength(struct msdosfsmount *, uint32_t, uint32_t);

sys/msdosfs/msdosfs_fat.c

93

int chainalloc(struct msdosfsmount *, uint32_t, uint32_t, uint32_t, uint32_t *,

sys/msdosfs/msdosfs_fat.c

937

extendfile(struct denode *dep, uint32_t count, struct buf **bpp, uint32_t *ncp,

sys/msdosfs/msdosfs_fat.c

94

uint32_t *);

sys/msdosfs/msdosfs_fat.c

941

uint32_t frcn;

sys/msdosfs/msdosfs_fat.c

942

uint32_t cn, got;

sys/msdosfs/msdosfs_fat.c

97

fatblock(struct msdosfsmount *pmp, uint32_t ofs, uint32_t *bnp, uint32_t *sizep,

sys/msdosfs/msdosfs_fat.c

98

uint32_t *bop)

sys/msdosfs/msdosfs_lookup.c

100

uint32_t scn; /* starting cluster number */

sys/msdosfs/msdosfs_lookup.c

1000

uint32_t cn;

sys/msdosfs/msdosfs_lookup.c

599

uint32_t dirclust, diroffset;

sys/msdosfs/msdosfs_lookup.c

723

uint32_t cn;

sys/msdosfs/msdosfs_lookup.c

797

uint32_t scn;

sys/msdosfs/msdosfs_lookup.c

882

readep(struct msdosfsmount *pmp, uint32_t dirclust, uint32_t diroffset,

sys/msdosfs/msdosfs_lookup.c

937

uint32_t offset = pdep->de_fndoffset;

sys/msdosfs/msdosfs_lookup.c

95

uint32_t cluster;

sys/msdosfs/msdosfs_vfsops.c

247

uint32_t fat_max_clusters;

sys/msdosfs/msdosfs_vnops.c

1235

uint32_t newcluster, pcl;

sys/msdosfs/msdosfs_vnops.c

1383

error = detrunc(ip, (uint32_t)0, IO_SYNC, cnp->cn_cred, cnp->cn_proc);

sys/msdosfs/msdosfs_vnops.c

1417

uint32_t dirsperblk;

sys/msdosfs/msdosfs_vnops.c

1418

uint32_t cn, lbn;

sys/msdosfs/msdosfs_vnops.c

1419

uint32_t fileno;

sys/msdosfs/msdosfs_vnops.c

1707

uint32_t cn;

sys/msdosfs/msdosfs_vnops.c

1722

msdosfs_bmaparray(struct vnode *vp, uint32_t cn, daddr_t *bnp, int *runp)

sys/msdosfs/msdosfs_vnops.c

1868

static uint32_t

sys/msdosfs/msdosfs_vnops.c

1884

return (uint32_t)(fileid | 0x80000000);

sys/msdosfs/msdosfs_vnops.c

232

uint32_t fileid;

sys/msdosfs/msdosfs_vnops.c

274

uint32_t dirsperblk;

sys/msdosfs/msdosfs_vnops.c

502

uint32_t n, diff, size, on;

sys/msdosfs/msdosfs_vnops.c

504

uint32_t cn;

sys/msdosfs/msdosfs_vnops.c

530

diff = dep->de_FileSize - (uint32_t)uio->uio_offset;

sys/msdosfs/msdosfs_vnops.c

571

uint32_t n, croffset;

sys/msdosfs/msdosfs_vnops.c

575

uint32_t osize;

sys/msdosfs/msdosfs_vnops.c

577

uint32_t count, lastcn, cn;

sys/msdosfs/msdosfs_vnops.c

78

static uint32_t fileidhash(uint64_t);

sys/msdosfs/msdosfs_vnops.c

80

int msdosfs_bmaparray(struct vnode *, uint32_t, daddr_t *, int *);

sys/msdosfs/msdosfs_vnops.c

896

uint32_t from_diroffset, to_diroffset;

sys/msdosfs/msdosfs_vnops.c

900

uint32_t cn, pcl;

sys/msdosfs/msdosfsmount.h

62

uint32_t pm_BlkPerSec; /* # of DEV_BSIZE blocks in MSDOSFS sector */

sys/msdosfs/msdosfsmount.h

63

uint32_t pm_FATsecs; /* actual number of fat sectors */

sys/msdosfs/msdosfsmount.h

64

uint32_t pm_fatblk; /* block # of first FAT */

sys/msdosfs/msdosfsmount.h

65

uint32_t pm_rootdirblk; /* block # (cluster # for FAT32) of root directory number */

sys/msdosfs/msdosfsmount.h

66

uint32_t pm_rootdirsize; /* size in blocks (not clusters) */

sys/msdosfs/msdosfsmount.h

67

uint32_t pm_firstcluster; /* block number of first cluster */

sys/msdosfs/msdosfsmount.h

68

uint32_t pm_nmbrofclusters; /* # of clusters in filesystem */

sys/msdosfs/msdosfsmount.h

69

uint32_t pm_maxcluster; /* maximum cluster number */

sys/msdosfs/msdosfsmount.h

70

uint32_t pm_freeclustercount; /* number of free clusters */

sys/msdosfs/msdosfsmount.h

71

uint32_t pm_cnshift; /* shift file offset right this amount to get a cluster number */

sys/msdosfs/msdosfsmount.h

72

uint32_t pm_crbomask; /* and a file offset with this mask to get cluster rel offset */

sys/msdosfs/msdosfsmount.h

73

uint32_t pm_bnshift; /* shift file offset right this amount to get a block number */

sys/msdosfs/msdosfsmount.h

74

uint32_t pm_bpcluster; /* bytes per cluster */

sys/msdosfs/msdosfsmount.h

75

uint32_t pm_fmod; /* ~0 if fs is modified, this can rollover to 0 */

sys/msdosfs/msdosfsmount.h

76

uint32_t pm_fatblocksize; /* size of fat blocks in bytes */

sys/msdosfs/msdosfsmount.h

77

uint32_t pm_fatblocksec; /* size of fat blocks in sectors */

sys/msdosfs/msdosfsmount.h

78

uint32_t pm_fatsize; /* size of fat in bytes */

sys/msdosfs/msdosfsmount.h

79

uint32_t pm_fatmask; /* mask to use for fat numbers */

sys/msdosfs/msdosfsmount.h

80

uint32_t pm_fsinfo; /* fsinfo block number */

sys/net/art.c

217

uint32_t k;

sys/net/art.c

324

const uint32_t *wan = (const uint32_t *)an->an_addr;

sys/net/art.c

325

const uint32_t *waddr = (const uint32_t *)addr;

sys/net/bfd.c

76

uint32_t bfd_my_discriminator; /* From this system */

sys/net/bfd.c

77

uint32_t bfd_your_discriminator; /* Received */

sys/net/bfd.c

78

uint32_t bfd_desired_min_tx_interval; /* in microseconds */

sys/net/bfd.c

79

uint32_t bfd_required_min_rx_interval; /* in microseconds */

sys/net/bfd.c

80

uint32_t bfd_required_min_echo_interval; /* in microseconds */

sys/net/bfd.h

110

uint32_t bn_lstate; /* SessionState */

sys/net/bfd.h

111

uint32_t bn_rstate; /* RemoteSessionState */

sys/net/bfd.h

112

uint32_t bn_ldiscr; /* LocalDiscr */

sys/net/bfd.h

113

uint32_t bn_rdiscr; /* RemoteDiscr */

sys/net/bfd.h

114

uint32_t bn_ldiag; /* LocalDiag */

sys/net/bfd.h

115

uint32_t bn_rdiag; /* RemoteDiag */

sys/net/bfd.h

116

uint32_t bn_mintx; /* DesiredMinTxInterval */

sys/net/bfd.h

117

uint32_t bn_req_minrx; /* RequiredMinRxInterval */

sys/net/bfd.h

118

uint32_t bn_rminrx; /* RemoteMinRxInterval */

sys/net/bfd.h

119

uint32_t bn_demand; /* DemandMode */

sys/net/bfd.h

120

uint32_t bn_rdemand; /* RemoteDemandMode */

sys/net/bfd.h

121

uint32_t bn_authtype; /* AuthType */

sys/net/bfd.h

122

uint32_t bn_rauthseq; /* RcvAuthSeq */

sys/net/bfd.h

123

uint32_t bn_lauthseq; /* XmitAuthSeq */

sys/net/bfd.h

124

uint32_t bn_authseqknown; /* AuthSeqKnown */

sys/net/bfd.h

148

uint32_t bc_minrx;

sys/net/bfd.h

149

uint32_t bc_mintx;

sys/net/bfd.h

150

uint32_t bc_minecho;

sys/net/bfd.h

63

uint32_t bs_localdiscr;

sys/net/bfd.h

69

uint32_t bs_mintx;

sys/net/bfd.h

70

uint32_t bs_minrx;

sys/net/bfd.h

72

uint32_t bs_minecho;

sys/net/bfd.h

73

uint32_t bs_localdiag;

sys/net/bfd.h

75

uint32_t bs_remotediscr;

sys/net/bfd.h

76

uint32_t bs_remotediag;

sys/net/fq_codel.c

192

static const uint32_t codel_intervals[] = {

sys/net/fq_codel.c

283

cp->intervals = (uint32_t *)codel_intervals;

sys/net/fq_codel.c

75

uint32_t *intervals;

sys/net/fq_codel.h

32

uint32_t qlength;

sys/net/fq_codel.h

33

uint32_t qlimit;

sys/net/fq_codel.h

35

uint32_t flows;

sys/net/fq_codel.h

36

uint32_t _unused; /* padding */

sys/net/fq_codel.h

38

uint32_t target;

sys/net/fq_codel.h

39

uint32_t interval;

sys/net/if.c

929

uint32_t ifcap;

sys/net/if.h

336

uint32_t ifie_flags; /* ieee80211com.ic_flags */

sys/net/if.h

337

uint32_t ifie_xflags; /* ieee80211com.ic xflags */

sys/net/if_aggr.c

1444

aggr_p_set_mtu(struct aggr_port *p, uint32_t mtu)

sys/net/if_aggr.c

2729

aggr_set_mtu(struct aggr_softc *sc, uint32_t mtu)

sys/net/if_aggr.c

2817

uint32_t hardmtu = ETHER_MAX_HARDMTU_LEN;

sys/net/if_aggr.c

2818

uint32_t capabilities = ~0;

sys/net/if_aggr.c

354

uint32_t p_mtu;

sys/net/if_aggr.c

402

uint32_t p_nselectch;

sys/net/if_aggr.c

483

static int aggr_set_mtu(struct aggr_softc *, uint32_t);

sys/net/if_aggr.c

487

static int aggr_p_set_mtu(struct aggr_port *, uint32_t);

sys/net/if_bpe.c

216

uint32_t itag, *itagp;

sys/net/if_bpe.c

287

itagp = (uint32_t *)(beh + 1);

sys/net/if_bpe.c

443

u_int hlen = sizeof(struct ether_header) + sizeof(uint32_t);

sys/net/if_bpe.c

577

bpe_set_group(struct bpe_softc *sc, uint32_t isid)

sys/net/if_bpe.c

593

uint32_t isid;

sys/net/if_bpe.c

62

uint32_t k_isid;

sys/net/if_bpe.c

723

bpe_find(struct ifnet *ifp0, uint32_t isid)

sys/net/if_bpe.c

741

uint32_t *itagp, itag;

sys/net/if_bpe.c

756

itagp = (uint32_t *)(beh + 1);

sys/net/if_bpe.c

783

if (!ALIGNED_POINTER(mtod(n, caddr_t) + off, uint32_t)) {

sys/net/if_bpe.c

99

static void bpe_set_group(struct bpe_softc *, uint32_t);

sys/net/if_bridge.h

521

uint32_t sc_brtmax; /* [m] max # addresses */

sys/net/if_bridge.h

522

uint32_t sc_brtcnt; /* [m] current # addrs */

sys/net/if_etherbridge.c

605

uint32_t flags = (uintptr_t)cookie;

sys/net/if_etherbridge.c

615

etherbridge_flush(struct etherbridge *eb, uint32_t flags)

sys/net/if_etherbridge.h

113

void etherbridge_flush(struct etherbridge *, uint32_t);

sys/net/if_etherip.c

711

uint32_t flow;

sys/net/if_etherip.c

775

uint32_t flow;

sys/net/if_gif.c

176

bpfattach(&ifp->if_bpf, ifp, DLT_LOOP, sizeof(uint32_t));

sys/net/if_gif.c

260

uint32_t shim;

sys/net/if_gif.c

266

shim = *mtod(m, uint32_t *) & MPLS_EXP_MASK;

sys/net/if_gif.c

344

uint32_t flow;

sys/net/if_gif.c

743

uint32_t flow;

sys/net/if_gif.c

856

uint32_t shim;

sys/net/if_gif.c

861

shim = *mtod(m, uint32_t *) & MPLS_EXP_MASK;

sys/net/if_gre.c

129

uint32_t gre_key;

sys/net/if_gre.c

1307

uint32_t flow;

sys/net/if_gre.c

1339

uint32_t shim;

sys/net/if_gre.c

1345

shim = *mtod(m, uint32_t *);

sys/net/if_gre.c

144

uint32_t gre_seq;

sys/net/if_gre.c

1500

if (!ALIGNED_POINTER(mtod(n, caddr_t) + off, uint32_t)) {

sys/net/if_gre.c

187

uint32_t t_key_mask;

sys/net/if_gre.c

191

uint32_t t_key;

sys/net/if_gre.c

1955

uint32_t shim;

sys/net/if_gre.c

1961

shim = bemtoh32(mtod(m, uint32_t *)) & MPLS_EXP_MASK;

sys/net/if_gre.c

2066

ip6->ip6_flow |= htonl((uint32_t)tos << 20);

sys/net/if_gre.c

268

uint32_t sc_ka_bias;

sys/net/if_gre.c

275

uint32_t gk_uptime;

sys/net/if_gre.c

276

uint32_t gk_random;

sys/net/if_gre.c

3300

uint32_t key;

sys/net/if_gre.c

3301

uint32_t min = GRE_KEY_MIN;

sys/net/if_gre.c

3302

uint32_t max = GRE_KEY_MAX;

sys/net/if_gre.c

3304

uint32_t mask = GRE_KEY_MASK;

sys/net/if_gre.c

3357

uint32_t mask, key;

sys/net/if_gre.c

4165

uint32_t ka, kb;

sys/net/if_gre.c

4166

uint32_t mask;

sys/net/if_gre.c

4244

uint32_t ka, kb;

sys/net/if_gre.c

4475

bpfattach(&sc->sc_bpf, ifp, DLT_LOOP, sizeof(uint32_t));

sys/net/if_gre.c

4511

uint32_t mask = 0;

sys/net/if_gre.c

4836

uint32_t session_id = sc->sc_tunnel.t_key;

sys/net/if_gre.c

4893

uint32_t session_id)

sys/net/if_gre.c

4899

uint32_t hdr;

sys/net/if_gre.c

4941

uint32_t hdr;

sys/net/if_gre.c

543

uint32_t hdr;

sys/net/if_gre.c

560

uint32_t index;

sys/net/if_gre.c

571

uint32_t sc_seq;

sys/net/if_gre.c

595

uint32_t);

sys/net/if_gre.c

676

bpfattach(&ifp->if_bpf, ifp, DLT_LOOP, sizeof(uint32_t));

sys/net/if_gre.c

743

bpfattach(&ifp->if_bpf, ifp, DLT_LOOP, sizeof(uint32_t));

sys/net/if_gre.c

992

uint32_t flow;

sys/net/if_mpe.c

224

uint32_t flow = bemtoh32(&ip6->ip6_flow);

sys/net/if_mpe.c

307

mpe_set_label(struct mpe_softc *sc, uint32_t label, unsigned int rdomain)

sys/net/if_mpe.c

445

uint32_t exp;

sys/net/if_mpe.c

489

uint32_t flow;

sys/net/if_mpip.c

130

bpfattach(&sc->sc_bpf, ifp, DLT_LOOP, sizeof(uint32_t));

sys/net/if_mpip.c

170

mpip_set_route(struct mpip_softc *sc, uint32_t shim, unsigned int rdomain)

sys/net/if_mpip.c

198

uint32_t shim;

sys/net/if_mpip.c

249

uint32_t label;

sys/net/if_mpip.c

473

uint32_t shim, exp;

sys/net/if_mpip.c

483

shim = *mtod(m, uint32_t *);

sys/net/if_mpip.c

490

uint32_t label;

sys/net/if_mpip.c

501

shim = *mtod(m, uint32_t *);

sys/net/if_mpip.c

526

shim = *mtod(m, uint32_t *);

sys/net/if_mpip.c

57

uint32_t sc_flow; /* xor for mbuf flowid */

sys/net/if_mpip.c

577

uint32_t flow;

sys/net/if_mpip.c

674

uint32_t shim;

sys/net/if_mpip.c

680

uint32_t exp, bos;

sys/net/if_mpip.c

746

uint32_t flow;

sys/net/if_mpip.c

770

*mtod(m, uint32_t *) = 0;

sys/net/if_mpip.c

776

uint32_t flow = 0;

sys/net/if_mpip.c

790

*mtod(m, uint32_t *) = shim;

sys/net/if_mpip.c

802

*mtod(m, uint32_t *) = shim;

sys/net/if_mpw.c

163

mpw_set_route(struct mpw_softc *sc, uint32_t label, unsigned int rdomain)

sys/net/if_mpw.c

196

uint32_t label;

sys/net/if_mpw.c

299

uint32_t shim;

sys/net/if_mpw.c

522

uint32_t exp;

sys/net/if_mpw.c

535

uint32_t flow;

sys/net/if_mpw.c

59

uint32_t sc_flow;

sys/net/if_mpw.c

599

if (!ALIGNED_POINTER(mtod(n, caddr_t) + off, uint32_t)) {

sys/net/if_mpw.c

60

uint32_t sc_type;

sys/net/if_mpw.c

654

uint32_t exp, bos;

sys/net/if_mpw.c

716

uint32_t flow = sc->sc_flow;

sys/net/if_pfsync.c

2114

uint32_t endtime, uint8_t status)

sys/net/if_pfsync.c

2752

uint32_t creatorid;

sys/net/if_pppoe.c

269

DLT_LOOP, sizeof(uint32_t));

sys/net/if_pppx.c

1058

ifp->if_hdrlen = sizeof(uint32_t); /* for BPF */

sys/net/if_pppx.c

1059

ifp->if_mtu = MAXMCLBYTES - sizeof(uint32_t);

sys/net/if_pppx.c

1072

bpfattach(&ifp->if_bpf, ifp, DLT_LOOP, sizeof(uint32_t));

sys/net/if_pppx.c

1130

uint32_t proto;

sys/net/if_pppx.c

1166

proto = ntohl(*mtod(m, uint32_t *));

sys/net/if_pppx.c

1167

m_adj(m, sizeof(uint32_t));

sys/net/if_pppx.c

1486

m = m_prepend(m, sizeof(uint32_t), M_DONTWAIT);

sys/net/if_pppx.c

1489

*mtod(m, uint32_t *) = htonl(m->m_pkthdr.ph_family);

sys/net/if_pppx.c

310

uint32_t proto;

sys/net/if_pppx.c

316

if (uio->uio_resid < sizeof(*th) + sizeof(uint32_t) ||

sys/net/if_pppx.c

385

proto = ntohl(*(uint32_t *)(th + 1));

sys/net/if_pppx.c

386

m_adj(top, sizeof(uint32_t));

sys/net/if_rport.c

125

bpfattach(&ifp->if_bpf, ifp, DLT_LOOP, sizeof(uint32_t));

sys/net/if_sec.c

158

bpfattach(&ifp->if_bpf, ifp, DLT_LOOP, sizeof(uint32_t));

sys/net/if_tun.c

1133

uint32_t af;

sys/net/if_tun.c

1137

af = *mtod(m0, uint32_t *);

sys/net/if_tun.h

115

uint32_t tun_if_capabilities; /* IFCAP_* from net/if.h */

sys/net/if_var.h

191

uint32_t if_mtu;

sys/net/if_var.h

192

uint32_t if_metric;

sys/net/if_var.h

194

uint32_t if_capabilities;

sys/net/if_var.h

195

uint32_t if_rdomain;

sys/net/if_var.h

200

uint32_t if_hardmtu; /* [d] maximum MTU device supports */

sys/net/if_veb.c

156

uint32_t p_protected;

sys/net/if_veb.c

158

uint32_t *p_vid_map;

sys/net/if_veb.c

2005

uint32_t *map;

sys/net/if_veb.c

2021

uint32_t e = map[w];

sys/net/if_veb.c

2064

static uint32_t *

sys/net/if_veb.c

2067

uint32_t *map;

sys/net/if_veb.c

2076

uint32_t e = 0;

sys/net/if_veb.c

2081

e |= (uint32_t)ifbrvm->ifbrvm_map[t + b] << (b * 8);

sys/net/if_veb.c

2090

veb_free_vid_map(uint32_t *map)

sys/net/if_veb.c

2097

uint32_t *map;

sys/net/if_veb.c

2109

veb_destroy_vid_map(uint32_t *map)

sys/net/if_veb.c

2127

veb_set_vid_map_set(uint32_t *nmap, const uint32_t *omap)

sys/net/if_veb.c

2133

veb_set_vid_map_or(uint32_t *nmap, const uint32_t *omap)

sys/net/if_veb.c

2145

veb_set_vid_map_andnot(uint32_t *nmap, const uint32_t *omap)

sys/net/if_veb.c

2157

uint32_t e = nmap[w];

sys/net/if_veb.c

2165

void (*apply)(uint32_t *, const uint32_t *);

sys/net/if_veb.c

2167

uint32_t *nmap = NULL, *omap = NULL;

sys/net/if_veb.c

2232

uint32_t *map;

sys/net/if_veb.c

63

#define VEB_VID_WORDS (VEB_VID_BYTES / sizeof(uint32_t))

sys/net/if_veb.c

661

uint32_t *map;

sys/net/if_vxlan.c

1516

uint32_t vni;

sys/net/if_vxlan.c

1541

uint32_t vni;

sys/net/if_vxlan.c

450

ip6->ip6_flow |= htonl((uint32_t)tos << 20);

sys/net/if_vxlan.c

67

uint32_t vxlan_flags;

sys/net/if_vxlan.c

687

if (!ALIGNED_POINTER(mtod(n, caddr_t) + off, uint32_t)) {

sys/net/if_vxlan.c

69

uint32_t vxlan_id;

sys/net/if_wg.c

100

uint32_t t;

sys/net/if_wg.c

101

uint32_t s_idx;

sys/net/if_wg.c

109

uint32_t t;

sys/net/if_wg.c

110

uint32_t s_idx;

sys/net/if_wg.c

111

uint32_t r_idx;

sys/net/if_wg.c

118

uint32_t t;

sys/net/if_wg.c

119

uint32_t r_idx;

sys/net/if_wg.c

125

uint32_t t;

sys/net/if_wg.c

126

uint32_t r_idx;

sys/net/if_wg.c

1318

wg_send_cookie(struct wg_softc *sc, struct cookie_macs *cm, uint32_t idx,

sys/net/if_wg.c

1401

switch (*mtod(m, uint32_t *)) {

sys/net/if_wg.c

159

uint32_t i_key;

sys/net/if_wg.c

196

uint32_t r_head;

sys/net/if_wg.c

197

uint32_t r_tail;

sys/net/if_wg.c

2009

uint32_t

sys/net/if_wg.c

2015

uint32_t key;

sys/net/if_wg.c

2045

wg_index_get(void *_sc, uint32_t key0)

sys/net/if_wg.c

2050

uint32_t key = key0 & sc->sc_index_mask;

sys/net/if_wg.c

2063

wg_index_drop(void *_sc, uint32_t key0)

sys/net/if_wg.c

2068

uint32_t key = key0 & sc->sc_index_mask;

sys/net/if_wg.c

2134

*mtod(m, uint32_t *) == WG_PKT_INITIATION) ||

sys/net/if_wg.c

2136

*mtod(m, uint32_t *) == WG_PKT_RESPONSE) ||

sys/net/if_wg.c

2138

*mtod(m, uint32_t *) == WG_PKT_COOKIE)) {

sys/net/if_wg.c

2148

NOISE_AUTHTAG_LEN && *mtod(m, uint32_t *) == WG_PKT_DATA) {

sys/net/if_wg.c

2785

bpfattach(&ifp->if_bpf, ifp, DLT_LOOP, sizeof(uint32_t));

sys/net/if_wg.c

341

void wg_send_cookie(struct wg_softc *, struct cookie_macs *, uint32_t,

sys/net/if_wg.c

364

uint32_t

sys/net/if_wg.c

367

wg_index_get(void *, uint32_t);

sys/net/if_wg.c

368

void wg_index_drop(void *, uint32_t);

sys/net/ifq.h

57

uint32_t ifq_oactives;

sys/net/ofp.h

122

uint32_t swp_number; /* Switch port number */

sys/net/ofp.h

127

uint32_t swp_config; /* Configuration flags */

sys/net/ofp.h

128

uint32_t swp_state; /* State flags */

sys/net/ofp.h

129

uint32_t swp_cur; /* Current features */

sys/net/ofp.h

130

uint32_t swp_advertised; /* Advertised by the port */

sys/net/ofp.h

131

uint32_t swp_supported; /* Supported by the port */

sys/net/ofp.h

132

uint32_t swp_peer; /* Advertised by peer */

sys/net/ofp.h

133

uint32_t swp_cur_speed; /* Current port speed in Kbps*/

sys/net/ofp.h

134

uint32_t swp_max_speed; /* Support port max speed in Kbps*/

sys/net/ofp.h

172

uint32_t swf_nbuffers; /* Max packets buffered */

sys/net/ofp.h

176

uint32_t swf_capabilities; /* Capability flags */

sys/net/ofp.h

177

uint32_t swf_actions; /* Supported action flags */

sys/net/ofp.h

203

uint32_t pin_buffer_id;

sys/net/ofp.h

259

uint32_t im_meter_id;

sys/net/ofp.h

266

uint32_t ie_experimenter;

sys/net/ofp.h

292

uint32_t ah_pad;

sys/net/ofp.h

299

uint32_t ao_port;

sys/net/ofp.h

332

uint32_t ag_group_id;

sys/net/ofp.h

351

uint32_t asq_queue_id;

sys/net/ofp.h

357

uint32_t pout_buffer_id;

sys/net/ofp.h

358

uint32_t pout_in_port;

sys/net/ofp.h

38

uint32_t oh_xid; /* transaction Id */

sys/net/ofp.h

475

uint32_t fm_buffer_id;

sys/net/ofp.h

476

uint32_t fm_out_port;

sys/net/ofp.h

477

uint32_t fm_out_group;

sys/net/ofp.h

496

uint32_t fr_duration_sec;

sys/net/ofp.h

497

uint32_t fr_duration_nsec;

sys/net/ofp.h

641

uint32_t b_watch_port;

sys/net/ofp.h

642

uint32_t b_watch_group;

sys/net/ofp.h

652

uint32_t gm_group_id;

sys/net/ofp.h

698

uint32_t fsr_out_port;

sys/net/ofp.h

699

uint32_t fsr_out_group;

sys/net/ofp.h

711

uint32_t fs_duration_sec;

sys/net/ofp.h

712

uint32_t fs_duration_nsec;

sys/net/ofp.h

728

uint32_t asr_out_port;

sys/net/ofp.h

729

uint32_t asr_out_group;

sys/net/ofp.h

739

uint32_t as_flow_count;

sys/net/ofp.h

750

uint32_t ts_active_count;

sys/net/ofp.h

782

uint32_t tf_config;

sys/net/ofp.h

783

uint32_t tf_max_entries;

sys/net/ofp.h

812

uint32_t tpoxm_oxm[0];

sys/net/ofp.h

818

uint32_t tfpexp_experimenter;

sys/net/ofp.h

819

uint32_t tfpexp_exp_type;

sys/net/ofp.h

820

uint32_t tfpexp_experimenter_data[0];

sys/net/ofp.h

824

uint32_t pt_port_no;

sys/net/ofp.h

838

uint32_t pt_duration_sec;

sys/net/ofp.h

839

uint32_t pt_duration_nsec;

sys/net/ofp.h

844

uint32_t gsr_group_id;

sys/net/ofp.h

857

uint32_t gs_group_id;

sys/net/ofp.h

858

uint32_t gs_ref_count;

sys/net/ofp.h

862

uint32_t gs_duration_sec;

sys/net/ofp.h

863

uint32_t gs_duration_nsec;

sys/net/ofp.h

872

uint32_t gd_group_id;

sys/net/ofp.h

890

uint32_t of_direction;

sys/net/pf.c

398

uint32_t wa = ntohl(a->pfsr_addr.addr32[i]);

sys/net/pf.c

399

uint32_t wb = ntohl(b->pfsr_addr.addr32[i]);

sys/net/pf.c

425

pf_statelim_find(uint32_t id)

sys/net/pf.c

437

pf_sourcelim_find(uint32_t id)

sys/net/pf.c

4383

uint32_t words[1];

sys/net/pf.c

7999

uint32_t hash;

sys/net/pf_ioctl.c

1093

pf_statelim_clr(uint32_t id, int rmst)

sys/net/pf_ioctl.c

117

struct pf_trans *pf_open_trans(uint32_t);

sys/net/pf_ioctl.c

118

struct pf_trans *pf_find_trans(uint32_t, uint64_t);

sys/net/pf_ioctl.c

123

struct pf_anchor *, uint32_t, struct pf_rule *);

sys/net/pf_ioctl.c

326

uint32_t unit = minor(dev);

sys/net/pf_ioctl.c

4231

pf_open_trans(uint32_t unit)

sys/net/pf_ioctl.c

4253

pf_find_trans(uint32_t unit, uint64_t ticket)

sys/net/pf_ioctl.c

4269

uint32_t rs_version, struct pf_rule *r)

sys/net/pf_lb.c

331

uint32_t

sys/net/pf_lb.c

332

pf_rand_addr(uint32_t mask)

sys/net/pf_lb.c

334

uint32_t addr;

sys/net/pf_lb.c

91

uint32_t hash32[2];

sys/net/pf_syncookies.c

101

uint32_t hiwat; /* absolute; # of states */

sys/net/pf_syncookies.c

102

uint32_t lowat;

sys/net/pf_syncookies.c

107

uint32_t pf_syncookie_mac(struct pf_pdesc *, union pf_syncookie,

sys/net/pf_syncookies.c

108

uint32_t);

sys/net/pf_syncookies.c

109

uint32_t pf_syncookie_generate(struct pf_pdesc *, uint16_t);

sys/net/pf_syncookies.c

184

uint32_t iss;

sys/net/pf_syncookies.c

199

uint32_t hash, ack, seq;

sys/net/pf_syncookies.c

281

uint32_t

sys/net/pf_syncookies.c

282

pf_syncookie_mac(struct pf_pdesc *pd, union pf_syncookie cookie, uint32_t seq)

sys/net/pf_syncookies.c

285

uint32_t siphash[2];

sys/net/pf_syncookies.c

313

uint32_t

sys/net/pf_syncookies.c

317

uint32_t iss, hash;

sys/net/pf_syncookies.c

356

uint32_t ack, seq;

sys/net/pfkeyv2.c

143

uint32_t kcb_reg; /* [s] Inc if SATYPE_MAX > 31 */

sys/net/pfkeyv2.c

144

uint32_t kcb_pid; /* [I] */

sys/net/pfkeyv2.c

164

static uint32_t pfkeyv2_seq = 1;

sys/net/pfkeyv2.c

541

uint32_t kcb_reg;

sys/net/pfkeyv2.h

100

uint32_t sadb_lifetime_allocations;

sys/net/pfkeyv2.h

109

uint32_t sadb_address_reserved;

sys/net/pfkeyv2.h

130

uint32_t sadb_sens_dpd;

sys/net/pfkeyv2.h

135

uint32_t sadb_sens_reserved;

sys/net/pfkeyv2.h

154

uint32_t sadb_comb_reserved;

sys/net/pfkeyv2.h

155

uint32_t sadb_comb_soft_allocations;

sys/net/pfkeyv2.h

156

uint32_t sadb_comb_hard_allocations;

sys/net/pfkeyv2.h

168

uint32_t sadb_supported_reserved;

sys/net/pfkeyv2.h

182

uint32_t sadb_spirange_min;

sys/net/pfkeyv2.h

183

uint32_t sadb_spirange_max;

sys/net/pfkeyv2.h

184

uint32_t sadb_spirange_reserved;

sys/net/pfkeyv2.h

199

uint32_t sadb_x_policy_seq;

sys/net/pfkeyv2.h

212

uint32_t sadb_x_tag_taglen;

sys/net/pfkeyv2.h

218

uint32_t sadb_x_replay_reserved;

sys/net/pfkeyv2.h

232

uint32_t sadb_x_tap_unit;

sys/net/pfkeyv2.h

238

uint32_t sadb_x_counter_pad;

sys/net/pfkeyv2.h

252

uint32_t sadb_x_mtu_mtu;

sys/net/pfkeyv2.h

258

uint32_t sadb_x_iface_unit;

sys/net/pfkeyv2.h

77

uint32_t sadb_msg_seq;

sys/net/pfkeyv2.h

78

uint32_t sadb_msg_pid;

sys/net/pfkeyv2.h

89

uint32_t sadb_sa_spi;

sys/net/pfkeyv2.h

94

uint32_t sadb_sa_flags;

sys/net/pfvar.h

1527

uint32_t id;

sys/net/pfvar.h

1559

uint32_t id;

sys/net/pfvar.h

1621

uint32_t id;

sys/net/pfvar.h

1639

uint32_t id;

sys/net/pfvar_priv.h

312

uint32_t pfstlim_id;

sys/net/pfvar_priv.h

423

uint32_t pfsrlim_id;

sys/net/pfvar_priv.h

600

uint32_t pft_unit; /* process id */

sys/net/pipex.c

1527

uint32_t flags, seq = 0, ack = 0;

sys/net/pipex.c

1779

uint32_t val32;

sys/net/pipex.c

2043

uint32_t ipsecflowinfo, struct netstack *nst)

sys/net/pipex.c

3038

uint32_t

sys/net/pipex.c

942

if (!ALIGNED_POINTER(mtod(m0, caddr_t), uint32_t)) {

sys/net/pipex.h

100

uint32_t rcv_acked; /* recv acked */

sys/net/pipex.h

106

uint32_t option_flags;

sys/net/pipex.h

111

uint32_t ns_nxt; /* send next */

sys/net/pipex.h

112

uint32_t nr_nxt; /* receive next */

sys/net/pipex.h

113

uint32_t ns_una; /* unacked */

sys/net/pipex.h

114

uint32_t nr_acked; /* recv acked */

sys/net/pipex.h

115

uint32_t ipsecflowinfo; /* IPsec flow id for NAT-T */

sys/net/pipex.h

193

struct pipex_session *, uint32_t,

sys/net/pipex.h

59

uint32_t ipackets; /* packets received from tunnel */

sys/net/pipex.h

60

uint32_t ierrors; /* error packets received from tunnel */

sys/net/pipex.h

62

uint32_t opackets; /* packets sent to tunnel */

sys/net/pipex.h

63

uint32_t oerrors; /* error packets on sending to tunnel */

sys/net/pipex.h

66

uint32_t idle_time; /* idle time in seconds */

sys/net/pipex.h

74

uint32_t pr_ppp_flags; /* PPP configuration flags */

sys/net/pipex.h

88

uint32_t pr_timeout_sec; /* Idle Timer */

sys/net/pipex.h

97

uint32_t snd_nxt; /* send next */

sys/net/pipex.h

98

uint32_t rcv_nxt; /* receive next */

sys/net/pipex.h

99

uint32_t snd_una; /* unacked */

sys/net/pipex_local.h

100

uint32_t snd_una; /* [s] send acked sequence */

sys/net/pipex_local.h

101

uint32_t rcv_acked; /* [s] recv acked sequence */

sys/net/pipex_local.h

142

uint32_t option_flags; /* [I] protocol options */

sys/net/pipex_local.h

143

uint32_t ipsecflowinfo; /* [I] IPsec SA flow id for NAT-T */

sys/net/pipex_local.h

192

uint32_t idle_time; /* [L] idle time in seconds */

sys/net/pipex_local.h

198

uint32_t timeout_sec; /* [I] idle timeout */

sys/net/pipex_local.h

209

uint32_t ppp_flags; /* [I] configure flags */

sys/net/pipex_local.h

472

uint32_t pipex_sockaddr_hash_key(struct sockaddr *);

sys/net/pipex_local.h

98

uint32_t snd_nxt; /* [s] send next */

sys/net/pipex_local.h

99

uint32_t rcv_nxt; /* [s] receive next */

sys/net/route.c

149

static uint32_t rt_hashjitter;

sys/net/route.c

165

struct rtentry *rt_match(const struct sockaddr *, uint32_t *, int,

sys/net/route.c

248

uint32_t *s = NULL;

sys/net/route.c

301

uint32_t *s = NULL;

sys/net/route.c

344

rt_match(const struct sockaddr *dst, uint32_t *src, int flags,

sys/net/route.c

411

rt_hash(struct rtentry *rt, const struct sockaddr *dst, uint32_t *src)

sys/net/route.c

413

uint32_t a, b, c;

sys/net/route.c

472

rtalloc_mpath(const struct sockaddr *dst, uint32_t *src, unsigned int rtableid)

sys/net/route.h

503

int rt_hash(struct rtentry *, const struct sockaddr *, uint32_t *);

sys/net/route.h

504

struct rtentry *rtalloc_mpath(const struct sockaddr *, uint32_t *, u_int);

sys/net/rtable.c

483

rtable_match(unsigned int rtableid, const struct sockaddr *dst, uint32_t *src)

sys/net/rtable.h

65

uint32_t *);

sys/net/rtsock.c

2037

uint32_t *words = (uint32_t *)&rtstat;

sys/net/rtsock.c

2040

CTASSERT(sizeof(rtstat) == (nitems(counters) * sizeof(uint32_t)));

sys/net/rtsock.c

2045

words[i] = (uint32_t)counters[i];

sys/net/toeplitz.c

162

uint32_t n32 = 0;

sys/net/toeplitz.c

176

uint32_t n32 = 0;

sys/net/toeplitz.h

43

uint32_t, uint32_t);

sys/net/toeplitz.h

45

uint32_t, uint32_t, uint16_t, uint16_t);

sys/net/toeplitz.h

73

stoeplitz_hash_n32(const struct stoeplitz_cache *scache, uint32_t n32)

sys/net/toeplitz.h

95

stoeplitz_hash_h32(const struct stoeplitz_cache *scache, uint32_t h32)

sys/net/wg_noise.c

1000

uint32_t s_idx;

sys/net/wg_noise.c

1001

uint32_t r_idx;

sys/net/wg_noise.c

1007

static uint32_t index;

sys/net/wg_noise.c

1013

static uint32_t

sys/net/wg_noise.c

1016

upcall_drop(void *x0, uint32_t x1) { }

sys/net/wg_noise.c

209

noise_create_initiation(struct noise_remote *r, uint32_t *s_idx,

sys/net/wg_noise.c

262

uint32_t s_idx, uint8_t ue[NOISE_PUBLIC_KEY_LEN],

sys/net/wg_noise.c

338

noise_create_response(struct noise_remote *r, uint32_t *s_idx, uint32_t *r_idx,

sys/net/wg_noise.c

38

static uint32_t noise_remote_handshake_index_get(struct noise_remote *);

sys/net/wg_noise.c

385

noise_consume_response(struct noise_remote *r, uint32_t s_idx, uint32_t r_idx,

sys/net/wg_noise.c

560

noise_remote_encrypt(struct noise_remote *r, uint32_t *r_idx, uint64_t *nonce,

sys/net/wg_noise.c

610

noise_remote_decrypt(struct noise_remote *r, uint32_t r_idx, uint64_t nonce,

sys/net/wg_noise.c

706

static uint32_t

sys/net/wg_noise.c

936

uint32_t nsec;

sys/net/wg_noise.c

993

uint32_t s_idx;

sys/net/wg_noise.h

121

uint32_t

sys/net/wg_noise.h

123

void (*u_index_drop)(void *, uint32_t);

sys/net/wg_noise.h

147

uint32_t *s_idx,

sys/net/wg_noise.h

155

uint32_t s_idx,

sys/net/wg_noise.h

162

uint32_t *s_idx,

sys/net/wg_noise.h

163

uint32_t *r_idx,

sys/net/wg_noise.h

169

uint32_t s_idx,

sys/net/wg_noise.h

170

uint32_t r_idx,

sys/net/wg_noise.h

182

uint32_t *r_idx,

sys/net/wg_noise.h

188

uint32_t r_idx,

sys/net/wg_noise.h

33

#define NOISE_TIMESTAMP_LEN (sizeof(uint64_t) + sizeof(uint32_t))

sys/net/wg_noise.h

67

uint32_t hs_local_index;

sys/net/wg_noise.h

68

uint32_t hs_remote_index;

sys/net/wg_noise.h

85

uint32_t kp_local_index;

sys/net/wg_noise.h

86

uint32_t kp_remote_index;

sys/net80211/ieee80211_node.c

1346

uint32_t assoc_fail = 0;

sys/net80211/ieee80211_node.h

122

uint32_t nrates;

sys/net80211/ieee80211_node.h

123

uint32_t rates[IEEE80211_VHT_RATESET_MAX_NRATES]; /* 500 kbit/s units */

sys/net80211/ieee80211_node.h

350

uint32_t ni_txbfcaps;

sys/net80211/ieee80211_node.h

361

uint32_t ni_vhtcaps;

sys/net80211/ieee80211_node.h

407

uint32_t ni_assoc_fail; /* assoc failure reasons */

sys/net80211/ieee80211_node.h

81

uint32_t nrates;

sys/net80211/ieee80211_node.h

82

uint32_t rates[IEEE80211_HT_RATESET_MAX_NRATES]; /* 500 kbit/s units */

sys/net80211/ieee80211_node.h

89

uint32_t mcs_mask;

sys/net80211/ieee80211_ra.c

100

uint32_t i, f;

sys/net80211/ieee80211_ra.c

533

uint32_t ntxstreams = 1;

sys/net80211/ieee80211_ra.c

545

uint32_t

sys/net80211/ieee80211_ra.c

548

uint32_t valid_mcs = 0;

sys/net80211/ieee80211_ra.c

56

uint32_t ieee80211_ra_valid_rates(struct ieee80211com *,

sys/net80211/ieee80211_ra.c

580

int mcs, uint32_t total, uint32_t fail)

sys/net80211/ieee80211_ra.c

84

ra_fixedp_split(uint32_t *i, uint32_t *f, uint64_t fp)

sys/net80211/ieee80211_ra.c

94

*f = (uint32_t)(tmp >> RA_FP_SHIFT);

sys/net80211/ieee80211_ra.h

29

uint32_t nprobe_pkts; /* Number of packets in current probe. */

sys/net80211/ieee80211_ra.h

30

uint32_t nprobe_fail; /* Number of failed packets. */

sys/net80211/ieee80211_ra.h

41

uint32_t valid_probes;

sys/net80211/ieee80211_ra.h

42

uint32_t valid_rates;

sys/net80211/ieee80211_ra.h

43

uint32_t candidate_rates;

sys/net80211/ieee80211_ra.h

44

uint32_t probed_rates;

sys/net80211/ieee80211_ra_vht.c

580

int mcs, int nss, uint32_t total, uint32_t fail)

sys/net80211/ieee80211_ra_vht.c

83

ra_vht_fixedp_split(uint32_t *i, uint32_t *f, uint64_t fp)

sys/net80211/ieee80211_ra_vht.c

93

*f = (uint32_t)(tmp >> RA_FP_SHIFT);

sys/net80211/ieee80211_ra_vht.c

99

uint32_t i, f;

sys/net80211/ieee80211_ra_vht.h

29

uint32_t nprobe_pkts; /* Number of packets in current probe. */

sys/net80211/ieee80211_ra_vht.h

30

uint32_t nprobe_fail; /* Number of failed packets. */

sys/net80211/ieee80211_var.h

276

uint32_t ic_bgscan_fail;

sys/net80211/ieee80211_var.h

386

uint32_t ic_vhtcaps;

sys/netinet/in_cksum.c

62

uint32_t l;

sys/netinet/ip_ah.c

537

uint32_t btsx, esn;

sys/netinet/ip_ecn.c

162

uint32_t x;

sys/netinet/ip_esp.c

349

uint32_t btsx, esn;

sys/netinet/ip_esp.c

693

uint32_t replay;

sys/netinet/ip_ipsp.h

618

uint32_t reserve_spi(u_int, u_int32_t, u_int32_t, union sockaddr_union *,

sys/netinet/tcp.h

142

uint32_t tcpi_rto; /* Retransmission timeout (usec). */

sys/netinet/tcp.h

143

uint32_t __tcpi_ato;

sys/netinet/tcp.h

144

uint32_t tcpi_snd_mss; /* Max segment size for send. */

sys/netinet/tcp.h

145

uint32_t tcpi_rcv_mss; /* Max segment size for recv. */

sys/netinet/tcp.h

147

uint32_t __tcpi_unacked;

sys/netinet/tcp.h

148

uint32_t __tcpi_sacked;

sys/netinet/tcp.h

149

uint32_t __tcpi_lost;

sys/netinet/tcp.h

150

uint32_t __tcpi_retrans;

sys/netinet/tcp.h

151

uint32_t __tcpi_fackets;

sys/netinet/tcp.h

154

uint32_t tcpi_last_data_sent; /* since last sent data. */

sys/netinet/tcp.h

155

uint32_t tcpi_last_ack_sent; /* since last sent ack. */

sys/netinet/tcp.h

156

uint32_t tcpi_last_data_recv; /* since last recv data. */

sys/netinet/tcp.h

157

uint32_t tcpi_last_ack_recv; /* since last recv ack. */

sys/netinet/tcp.h

160

uint32_t __tcpi_pmtu;

sys/netinet/tcp.h

161

uint32_t __tcpi_rcv_ssthresh;

sys/netinet/tcp.h

162

uint32_t tcpi_rtt; /* Smoothed RTT in usecs. */

sys/netinet/tcp.h

163

uint32_t tcpi_rttvar; /* RTT variance in usecs. */

sys/netinet/tcp.h

164

uint32_t tcpi_snd_ssthresh; /* Slow start threshold. */

sys/netinet/tcp.h

165

uint32_t tcpi_snd_cwnd; /* Send congestion window. */

sys/netinet/tcp.h

166

uint32_t __tcpi_advmss;

sys/netinet/tcp.h

167

uint32_t __tcpi_reordering;

sys/netinet/tcp.h

169

uint32_t __tcpi_rcv_rtt;

sys/netinet/tcp.h

170

uint32_t tcpi_rcv_space; /* Advertised recv window. */

sys/netinet/tcp.h

178

uint32_t tcpi_snd_wnd; /* Advertised send window. */

sys/netinet/tcp.h

179

uint32_t tcpi_snd_nxt; /* Next egress seqno */

sys/netinet/tcp.h

180

uint32_t tcpi_rcv_nxt; /* Next ingress seqno */

sys/netinet/tcp.h

181

uint32_t tcpi_toe_tid; /* HWTID for TOE endpoints */

sys/netinet/tcp.h

182

uint32_t tcpi_snd_rexmitpack; /* Retransmitted packets */

sys/netinet/tcp.h

183

uint32_t tcpi_rcv_ooopack; /* Out-of-order packets */

sys/netinet/tcp.h

184

uint32_t tcpi_snd_zerowin; /* Zero-sized windows sent */

sys/netinet/tcp.h

187

uint32_t tcpi_rttmin;

sys/netinet/tcp.h

188

uint32_t tcpi_max_sndwnd;

sys/netinet/tcp.h

189

uint32_t tcpi_rcv_adv;

sys/netinet/tcp.h

190

uint32_t tcpi_rcv_up;

sys/netinet/tcp.h

191

uint32_t tcpi_snd_una;

sys/netinet/tcp.h

192

uint32_t tcpi_snd_up;

sys/netinet/tcp.h

193

uint32_t tcpi_snd_wl1;

sys/netinet/tcp.h

194

uint32_t tcpi_snd_wl2;

sys/netinet/tcp.h

195

uint32_t tcpi_snd_max;

sys/netinet/tcp.h

196

uint32_t tcpi_ts_recent;

sys/netinet/tcp.h

197

uint32_t tcpi_ts_recent_age;

sys/netinet/tcp.h

198

uint32_t tcpi_rfbuf_cnt;

sys/netinet/tcp.h

199

uint32_t tcpi_rfbuf_ts;

sys/netinet/tcp.h

200

uint32_t tcpi_so_rcv_sb_cc;

sys/netinet/tcp.h

201

uint32_t tcpi_so_rcv_sb_hiwat;

sys/netinet/tcp.h

202

uint32_t tcpi_so_rcv_sb_lowat;

sys/netinet/tcp.h

203

uint32_t tcpi_so_rcv_sb_wat;

sys/netinet/tcp.h

204

uint32_t tcpi_so_snd_sb_cc;

sys/netinet/tcp.h

205

uint32_t tcpi_so_snd_sb_hiwat;

sys/netinet/tcp.h

206

uint32_t tcpi_so_snd_sb_lowat;

sys/netinet/tcp.h

207

uint32_t tcpi_so_snd_sb_wat;

sys/netinet/tcp_debug.h

81

uint32_t td_time;

sys/netinet/tcp_input.c

3122

static inline uint32_t

sys/netinet/tcp_input.c

3124

uint32_t rand[])

sys/netinet/tcp_input.c

3128

uint32_t src_port = satosin_const(src)->sin_port;

sys/netinet/tcp_input.c

3129

uint32_t dst_port = satosin_const(dst)->sin_port;

sys/netinet/tcp_input.c

3138

uint32_t src_port = satosin6_const(src)->sin6_port;

sys/netinet/tcp_input.c

3139

uint32_t dst_port = satosin6_const(dst)->sin6_port;

sys/netinet/tcp_input.c

3140

const uint32_t *src_addr6 =

sys/netinet/tcp_input.c

4250

((uint32_t *)optp)[0] != htonl(TCPOPT_TSTAMP_HDR))

sys/netinet/tcp_input.c

4316

uint32_t *hoptp = (uint32_t *)(head->tcp + 1);

sys/netinet/tcp_input.c

4317

uint32_t *toptp = (uint32_t *)(tail->tcp + 1);

sys/netinet/tcp_input.c

4353

uint32_t *hoptp = (uint32_t *)(head->tcp + 1);

sys/netinet/tcp_input.c

4354

uint32_t *toptp = (uint32_t *)(tail->tcp + 1);

sys/netinet/tcp_output.c

1341

struct rtentry *rt, uint32_t ifcap, u_int mtu)

sys/netinet/tcp_subr.c

1099

len = m->m_pkthdr.len - iphlen - th->th_off * sizeof(uint32_t);

sys/netinet/tcp_subr.c

1102

m_apply(m, iphlen + th->th_off * sizeof(uint32_t), len,

sys/netinet/tcp_subr.c

951

uint32_t words[2];

sys/netinet/tcp_timer.c

205

uint32_t rto;

sys/netinet/tcp_timer.c

410

uint32_t rto;

sys/netinet/tcp_usrreq.c

1432

const size_t buflen = bufitems * sizeof(uint32_t);

sys/netinet/tcp_usrreq.c

1434

uint32_t *buf;

sys/netinet/tcp_var.h

184

uint32_t ts_recent; /* timestamp echo data */

sys/netinet/tcp_var.h

185

uint32_t ts_modulate; /* modulation on timestamp */

sys/netinet/tcp_var.h

744

struct rtentry *, uint32_t, u_int);

sys/netinet/udp_usrreq.c

1297

const size_t buflen = bufitems * sizeof(uint32_t);

sys/netinet/udp_usrreq.c

1299

uint32_t *buf;

sys/netinet6/in6.h

414

int in6_cksum(struct mbuf *, uint8_t, uint32_t, uint32_t);

sys/netinet6/in6_cksum.c

109

uint32_t l;

sys/netinet6/in6_cksum.c

88

in6_cksum(struct mbuf *m, uint8_t nxt, uint32_t off, uint32_t len)

sys/netinet6/in6_cksum.c

98

uint32_t ph_len;

sys/netinet6/ip6_mroute.h

67

#define __NIFBITS (sizeof(uint32_t) * 8) /* bits per mask */

sys/netinet6/ip6_mroute.h

69

uint32_t ifs_bits[howmany(256, __NIFBITS)];

sys/netmpls/mpls.h

134

uint32_t imr_flags;

sys/netmpls/mpls.h

135

uint32_t imr_type; /* pseudowire type */

sys/netmpls/mpls_input.c

301

uint32_t x;

sys/nfs/nfs_bio.c

57

uint32_t nfs_bufqmax, nfs_bufqlen;

sys/nfs/nfs_serv.c

1002

uint32_t *tl;

sys/nfs/nfs_serv.c

1088

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_serv.c

110

uint32_t *tl = (uint32_t *)nfsm_dissect(infop, NFSX_UNSIGNED);

sys/nfs/nfs_serv.c

125

uint32_t *tl = (uint32_t *)nfsm_dissect(infop, NFSX_V3FH);

sys/nfs/nfs_serv.c

1371

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_serv.c

1393

tl = (uint32_t *)nfsm_dissect(&info, 2 * NFSX_UNSIGNED);

sys/nfs/nfs_serv.c

168

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_serv.c

2166

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_serv.c

2415

tl = (uint32_t *)nfsm_dissect(&info, 5 * NFSX_UNSIGNED);

sys/nfs/nfs_serv.c

2423

tl = (uint32_t *)nfsm_dissect(&info, 2 * NFSX_UNSIGNED);

sys/nfs/nfs_serv.c

2643

tl = (uint32_t *)nfsm_dissect(&info, 6 * NFSX_UNSIGNED);

sys/nfs/nfs_serv.c

2901

tl = (uint32_t *)nfsm_dissect(&info, 3 * NFSX_UNSIGNED);

sys/nfs/nfs_serv.c

305

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_serv.c

310

tl = (uint32_t *)nfsm_dissect(&info, 2 * NFSX_UNSIGNED);

sys/nfs/nfs_serv.c

421

uint32_t *tl = (uint32_t *)nfsm_dissect(infop, NFSX_UNSIGNED);

sys/nfs/nfs_serv.c

664

tl = (uint32_t *)nfsm_dissect(&info, 2 * NFSX_UNSIGNED);

sys/nfs/nfs_serv.c

669

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_serv.c

675

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_serv.c

856

tl = (uint32_t *)nfsm_dissect(&info, 5 * NFSX_UNSIGNED);

sys/nfs/nfs_serv.c

863

tl = (uint32_t *)nfsm_dissect(&info, 4 * NFSX_UNSIGNED);

sys/nfs/nfs_socket.c

1010

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_socket.c

1015

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_socket.c

1460

tl = (uint32_t *)nfsm_dissect(&info, 10 * NFSX_UNSIGNED);

sys/nfs/nfs_socket.c

1469

tl = (uint32_t *)nfsm_dissect(&info, 8 * NFSX_UNSIGNED);

sys/nfs/nfs_socket.c

1522

tl = (uint32_t *)nfsm_dissect(&info, 3 * NFSX_UNSIGNED);

sys/nfs/nfs_socket.c

1534

tl = (uint32_t *)

sys/nfs/nfs_socket.c

793

tl = (uint32_t *)nfsm_dissect(&info, 2 * NFSX_UNSIGNED);

sys/nfs/nfs_socket.c

985

tl = (uint32_t *)nfsm_dissect(&info, 3 * NFSX_UNSIGNED);

sys/nfs/nfs_srvsubs.c

402

uint32_t *tl;

sys/nfs/nfs_srvsubs.c

409

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_srvsubs.c

413

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_srvsubs.c

419

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_srvsubs.c

423

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_srvsubs.c

429

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_srvsubs.c

433

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_srvsubs.c

439

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_srvsubs.c

443

tl = (uint32_t *)nfsm_dissect(&info, 2 * NFSX_UNSIGNED);

sys/nfs/nfs_srvsubs.c

449

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_srvsubs.c

456

tl = (uint32_t *)nfsm_dissect(&info, 2 * NFSX_UNSIGNED);

sys/nfs/nfs_srvsubs.c

467

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_srvsubs.c

474

tl = (uint32_t *)nfsm_dissect(&info, 2 * NFSX_UNSIGNED);

sys/nfs/nfs_subs.c

773

uint32_t strlen;

sys/nfs/nfs_subs.c

778

iov[0].iov_len = sizeof(uint32_t);

sys/nfs/nfs_subs.c

784

io.uio_resid = sizeof(uint32_t) + len;

sys/nfs/nfs_vnops.c

1230

tl = (uint32_t *)nfsm_dissect(&info, 2 * NFSX_UNSIGNED);

sys/nfs/nfs_vnops.c

1324

tl = (uint32_t *)nfsm_dissect(&info,

sys/nfs/nfs_vnops.c

1386

uint32_t *tl;

sys/nfs/nfs_vnops.c

1391

tl = (uint32_t *)nfsm_dissect(infop, NFSX_UNSIGNED);

sys/nfs/nfs_vnops.c

1412

tl = (uint32_t *)nfsm_dissect(infop, NFSX_UNSIGNED);

sys/nfs/nfs_vnops.c

2379

tl = (uint32_t *)nfsm_dissect(&info, 2 * NFSX_UNSIGNED);

sys/nfs/nfs_vnops.c

2386

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_vnops.c

2394

tl = (uint32_t *)nfsm_dissect(&info,

sys/nfs/nfs_vnops.c

2401

tl = (uint32_t *)nfsm_dissect(&info,

sys/nfs/nfs_vnops.c

2453

tl = (uint32_t *)nfsm_dissect(&info,

sys/nfs/nfs_vnops.c

2456

tl = (uint32_t *)nfsm_dissect(&info,

sys/nfs/nfs_vnops.c

2479

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_vnops.c

2586

tl = (uint32_t *)nfsm_dissect(&info, 3 * NFSX_UNSIGNED);

sys/nfs/nfs_vnops.c

2595

tl = (uint32_t *)nfsm_dissect(&info, 3 * NFSX_UNSIGNED);

sys/nfs/nfs_vnops.c

2647

tl = (uint32_t *)nfsm_dissect(&info, 3 * NFSX_UNSIGNED);

sys/nfs/nfs_vnops.c

2667

tl = (uint32_t *)

sys/nfs/nfs_vnops.c

2712

tl = (uint32_t *)

sys/nfs/nfs_vnops.c

2729

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_vnops.c

2738

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_vnops.c

2957

tl = (uint32_t *)nfsm_dissect(&info, NFSX_V3WRITEVERF);

sys/nfs/nfs_vnops.c

367

tl = (uint32_t *)nfsm_dissect(&info, NFSX_UNSIGNED);

sys/nfs/nfs_vnops.c

686

uint32_t *tl;

sys/nfs/nfs_vnops.c

691

tl = (uint32_t *)nfsm_dissect(infop, NFSX_UNSIGNED);

sys/nfs/nfs_vnops.c

695

tl = (uint32_t *)nfsm_dissect(infop, 6 * NFSX_UNSIGNED);

sys/nfs/nfs_vnops.c

779

uint32_t *tl = (uint32_t *)nfsm_dissect(infop, NFSX_UNSIGNED);

sys/nfs/nfsm_subs.h

109

uint32_t *tl;

sys/nfs/nfsm_subs.h

117

tl = (uint32_t *)nfsm_dissect(infop, NFSX_UNSIGNED);

sys/nfs/nfsm_subs.h

139

uint32_t *tl = (uint32_t *)nfsm_dissect(infop, NFSX_UNSIGNED);

sys/nfs/nfsnode.h

139

extern uint32_t nfs_bufqlen, nfs_bufqmax;

sys/stand/efi/include/amd64/efibind.h

10

typedef uint32_t UINT32;

sys/stand/efi/include/arm/efibind.h

10

typedef uint32_t UINT32;

sys/stand/efi/include/arm/efibind.h

17

typedef uint32_t UINTN;

sys/stand/efi/include/arm64/efibind.h

10

typedef uint32_t UINT32;

sys/stand/efi/include/i386/efibind.h

10

typedef uint32_t UINT32;

sys/stand/efi/include/i386/efibind.h

17

typedef uint32_t UINTN;

sys/stand/efi/include/riscv64/efibind.h

10

typedef uint32_t UINT32;

sys/sys/clockintr.h

108

volatile uint32_t cq_gen; /* [o] cq_stat update generation */

sys/sys/clockintr.h

109

volatile uint32_t cq_dispatch; /* [o] dispatch is running */

sys/sys/clockintr.h

110

uint32_t cq_flags; /* [m] CQ_* flags; see below */

sys/sys/clockintr.h

135

void clockintr_stagger(struct clockintr *, uint64_t, uint32_t, uint32_t);

sys/sys/clockintr.h

136

void clockintr_unbind(struct clockintr *, uint32_t);

sys/sys/clockintr.h

138

uint64_t clockrequest_advance_random(struct clockrequest *, uint64_t, uint32_t);

sys/sys/clockintr.h

67

uint32_t cl_flags; /* [m] CLST_* flags */

sys/sys/clockintr.h

83

uint32_t cr_flags; /* [o] CR_* flags */

sys/sys/ctf.h

173

#define CTF_SIZE_TO_LSIZE_HI(s) ((uint32_t)((uint64_t)(s) >> 32))

sys/sys/ctf.h

174

#define CTF_SIZE_TO_LSIZE_LO(s) ((uint32_t)(s))

sys/sys/ctf.h

183

#define CTF_OFFSET_TO_LMEMHI(off) ((uint32_t)((uint64_t)(off) >> 32))

sys/sys/ctf.h

184

#define CTF_OFFSET_TO_LMEMLO(off) ((uint32_t)(off))

sys/sys/ctf.h

30

uint32_t cth_parlabel;

sys/sys/ctf.h

31

uint32_t cth_parname;

sys/sys/ctf.h

32

uint32_t cth_lbloff;

sys/sys/ctf.h

33

uint32_t cth_objtoff;

sys/sys/ctf.h

34

uint32_t cth_funcoff;

sys/sys/ctf.h

35

uint32_t cth_typeoff;

sys/sys/ctf.h

36

uint32_t cth_stroff;

sys/sys/ctf.h

37

uint32_t cth_strlen;

sys/sys/ctf.h

43

uint32_t ctl_label;

sys/sys/ctf.h

44

uint32_t ctl_typeidx;

sys/sys/ctf.h

48

uint32_t cts_name;

sys/sys/ctf.h

64

uint32_t ctt_lsizehi;

sys/sys/ctf.h

65

uint32_t ctt_lsizelo;

sys/sys/ctf.h

71

uint32_t cta_nelems;

sys/sys/ctf.h

75

uint32_t ctm_name;

sys/sys/ctf.h

85

uint32_t ctlm_offsethi;

sys/sys/ctf.h

86

uint32_t ctlm_offsetlo;

sys/sys/ctf.h

92

uint32_t cte_name;

sys/sys/exec_elf.h

678

uint32_t cpi_version; /* elfcore_procinfo version */

sys/sys/exec_elf.h

680

uint32_t cpi_cpisize; /* sizeof(elfcore_procinfo) */

sys/sys/exec_elf.h

681

uint32_t cpi_signo; /* killing signal */

sys/sys/exec_elf.h

682

uint32_t cpi_sigcode; /* signal code */

sys/sys/exec_elf.h

683

uint32_t cpi_sigpend; /* pending signals */

sys/sys/exec_elf.h

684

uint32_t cpi_sigmask; /* blocked signals */

sys/sys/exec_elf.h

685

uint32_t cpi_sigignore; /* ignored signals */

sys/sys/exec_elf.h

686

uint32_t cpi_sigcatch; /* signals being caught by user */

sys/sys/exec_elf.h

691

uint32_t cpi_ruid; /* real user ID */

sys/sys/exec_elf.h

692

uint32_t cpi_euid; /* effective user ID */

sys/sys/exec_elf.h

693

uint32_t cpi_svuid; /* saved user ID */

sys/sys/exec_elf.h

694

uint32_t cpi_rgid; /* real group ID */

sys/sys/exec_elf.h

695

uint32_t cpi_egid; /* effective group ID */

sys/sys/exec_elf.h

696

uint32_t cpi_svgid; /* saved group ID */

sys/sys/exec_elf.h

705

#define ELF32_NO_ADDR ((uint32_t) ~0) /* Indicates addr. not yet filled in */

sys/sys/fusebuf.h

49

uint32_t fi_flags; /* flags on transfer */

sys/sys/futex.h

26

int futex(volatile uint32_t *, int, int, const struct timespec *,

sys/sys/futex.h

27

volatile uint32_t *);

sys/sys/kstat.h

107

uint32_t v_u32;

sys/sys/malloc.h

395

int poison_check(void *, size_t, size_t *, uint32_t *);

sys/sys/malloc.h

396

uint32_t poison_value(void *);

sys/sys/pciio.h

61

uint32_t *pv_data;

sys/sys/proc.h

586

void setpriority(struct proc *, uint32_t, uint8_t);

sys/sys/rwlock.h

135

uint32_t rrwl_wcnt; /* # writers. */

sys/sys/sched.h

127

volatile uint32_t spc_whichqs;

sys/sys/select.h

70

typedef uint32_t __fd_mask;

sys/sys/syscallargs.h

400

syscallarg(uint32_t *) f;

sys/sys/syscallargs.h

404

syscallarg(uint32_t *) g;

sys/sys/sysctl.h

756

uint32_t f_flag; /* UINT: flags (see fcntl.h) */

sys/sys/sysctl.h

757

uint32_t f_iflags; /* UINT: internal flags */

sys/sys/sysctl.h

758

uint32_t f_type; /* INT: descriptor type */

sys/sys/sysctl.h

759

uint32_t f_count; /* UINT: reference count */

sys/sys/sysctl.h

760

uint32_t f_msgcount; /* UINT: references from msg queue */

sys/sys/sysctl.h

761

uint32_t f_usecount; /* INT: number active users */

sys/sys/sysctl.h

763

uint32_t f_uid; /* UID_T: descriptor credentials */

sys/sys/sysctl.h

764

uint32_t f_gid; /* GID_T: descriptor credentials */

sys/sys/sysctl.h

776

uint32_t v_type; /* ENUM: vnode type */

sys/sys/sysctl.h

777

uint32_t v_tag; /* ENUM: type of underlying data */

sys/sys/sysctl.h

778

uint32_t v_flag; /* UINT: vnode flags */

sys/sys/sysctl.h

779

uint32_t va_rdev; /* DEV_T: raw device */

sys/sys/sysctl.h

784

uint32_t va_mode; /* MODE_T: file access mode and type */

sys/sys/sysctl.h

785

uint32_t va_fsid; /* DEV_T: filesystem device */

sys/sys/sysctl.h

789

uint32_t so_type; /* SHORT: socket type */

sys/sys/sysctl.h

790

uint32_t so_state; /* SHORT: socket state */

sys/sys/sysctl.h

793

uint32_t so_protocol; /* SHORT: socket protocol type */

sys/sys/sysctl.h

794

uint32_t so_family; /* INT: socket domain family */

sys/sys/sysctl.h

796

uint32_t inp_lport; /* SHORT: local inet port */

sys/sys/sysctl.h

797

uint32_t inp_laddru[4]; /* STRUCT: local inet addr */

sys/sys/sysctl.h

798

uint32_t inp_fport; /* SHORT: foreign inet port */

sys/sys/sysctl.h

799

uint32_t inp_faddru[4]; /* STRUCT: foreign inet addr */

sys/sys/sysctl.h

804

uint32_t pipe_state; /* UINT: pipe status info */

sys/sys/sysctl.h

807

uint32_t kq_count; /* INT: number of pending events */

sys/sys/sysctl.h

808

uint32_t kq_state; /* INT: kqueue status information */

sys/sys/sysctl.h

810

uint32_t __unused1; /* INT: unused */

sys/sys/sysctl.h

813

uint32_t p_pid; /* PID_T: process id */

sys/sys/sysctl.h

815

uint32_t fd_ofileflags; /* CHAR: open file flags */

sys/sys/sysctl.h

816

uint32_t p_uid; /* UID_T: process credentials */

sys/sys/sysctl.h

817

uint32_t p_gid; /* GID_T: process credentials */

sys/sys/sysctl.h

818

uint32_t p_tid; /* PID_T: thread id */

sys/sys/sysctl.h

822

uint32_t inp_rtableid; /* UINT: Routing table identifier. */

sys/sys/sysctl.h

832

uint32_t inp_proto; /* CHAR: raw protocol id */

sys/sys/sysctl.h

833

uint32_t t_state; /* SHORT: tcp state */

sys/sys/sysctl.h

838

uint32_t va_nlink; /* NLINK_T: number of references to file */

sys/sys/systm.h

217

int copyin32(const uint32_t *, uint32_t *);

sys/sys/time.h

236

static inline uint32_t

sys/sys/time.h

261

tv->tv_usec = (long)(((uint64_t)1000000 * (uint32_t)(bt->frac >> 32)) >> 32);

sys/sys/timetc.h

88

uint32_t tk_version; /* version number */

sys/sys/uuid.h

49

uint32_t time_low;

sys/sys/vmmeter.h

65

uint32_t cntfork; /* number of fork() calls */

sys/sys/vmmeter.h

66

uint32_t cntvfork; /* number of vfork() calls */

sys/sys/vmmeter.h

67

uint32_t cnttfork; /* number of __tfork() calls */

sys/sys/vmmeter.h

68

uint32_t cntkthread; /* number of kernel threads created */

sys/tmpfs/tmpfs.h

255

uint32_t tf_gen;

sys/ufs/ext2fs/ext2fs.h

276

uint32_t mask;

sys/ufs/ext2fs/ext2fs_extents.h

43

uint32_t e_blk; /* first logical block */

sys/ufs/ext2fs/ext2fs_extents.h

46

uint32_t e_start_lo; /* low 32 bits of physical block */

sys/ufs/ext2fs/ext2fs_extents.h

53

uint32_t ei_blk; /* indexes logical blocks */

sys/ufs/ext2fs/ext2fs_extents.h

54

uint32_t ei_leaf_lo; /* points to physical block of the

sys/ufs/ext2fs/ext2fs_extents.h

68

uint32_t eh_gen; /* generation of extent tree */

sys/ufs/ext2fs/ext2fs_extents.h

76

uint32_t ec_blk; /* logical block */

sys/ufs/ext2fs/ext2fs_extents.h

77

uint32_t ec_len;

sys/ufs/ext2fs/ext2fs_extents.h

78

uint32_t ec_type;

sys/ufs/ffs/ffs_alloc.c

599

uint32_t pref;

sys/ufs/ffs/ffs_vfsops.c

103

ffs_checkrange(struct mount *mp, uint32_t ino)

sys/uvm/uvm_page.h

106

uint32_t pg_flags; /* [a] object flags */

sys/uvm/uvm_page.h

108

uint32_t pg_version; /* version count */

sys/uvm/uvm_page.h

109

uint32_t wire_count; /* [o] wired down map refs */

usr.bin/compress/zipopen.c

100

uint32_t x;

usr.bin/compress/zipopen.c

102

x = ((uint32_t)(get_byte(s) & 0xff));

usr.bin/compress/zipopen.c

103

x |= ((uint32_t)(get_byte(s) & 0xff))<<8;

usr.bin/compress/zipopen.c

104

x |= ((uint32_t)(get_byte(s) & 0xff))<<16;

usr.bin/compress/zipopen.c

105

x |= ((uint32_t)(get_byte(s) & 0xff))<<24;

usr.bin/compress/zipopen.c

130

uint32_t sig;

usr.bin/compress/zipopen.c

59

uint32_t z_time; /* timestamp (mtime) */

usr.bin/compress/zipopen.c

60

uint32_t z_crc; /* crc32 of uncompressed data */

usr.bin/compress/zipopen.c

61

uint32_t z_ocrc; /* crc32 of uncompressed data (from header) */

usr.bin/compress/zipopen.c

62

uint32_t z_hlen; /* length of the zip header */

usr.bin/compress/zipopen.c

97

static uint32_t

usr.bin/ctfconv/dw.c

257

if (psz == sizeof(uint32_t))

usr.bin/ctfconv/dw.c

42

static int dw_read_u32(struct dwbuf *, uint32_t *);

usr.bin/ctfconv/dw.c

494

uint32_t length = 0, abbroff = 0;

usr.bin/ctfconv/dw.c

524

nextoff = segoff + length + sizeof(uint32_t);

usr.bin/ctfconv/dw.c

85

dw_read_u32(struct dwbuf *d, uint32_t *v)

usr.bin/ctfconv/dw.h

43

uint32_t _u32;

usr.bin/ctfconv/elf.c

238

return sizeof(uint32_t);

usr.bin/ctfconv/elf.c

242

return sizeof(uint32_t);

usr.bin/ctfconv/elf.c

254

uint32_t v32 = val; \

usr.bin/ctfconv/generate.c

179

uint32_t size;

usr.bin/ctfconv/hash.c

174

static uint32_t

usr.bin/ctfconv/hash.c

177

uint32_t k;

usr.bin/ctfconv/hash.c

196

uint32_t hv;

usr.bin/ctfconv/hash.c

27

uint32_t hv;

usr.bin/ctfconv/hash.c

46

static uint32_t hash_interval(const char *, const char **);

usr.bin/ctfconv/itype.h

49

uint32_t it_size; /* CTF: size in byte or bits */

usr.bin/ctfconv/itype.h

50

uint32_t it_nelems; /* CTF: # of members or arguments */

usr.bin/ctfconv/parse.c

110

struct itype *it_new(uint64_t, size_t, const char *, uint32_t, uint16_t,

usr.bin/ctfconv/parse.c

1344

if (psz == sizeof(uint32_t))

usr.bin/ctfconv/parse.c

192

it_new(uint64_t index, size_t off, const char *name, uint32_t size,

usr.bin/ctfdump/ctfdump.c

352

uint32_t lbloff = cth.cth_lbloff;

usr.bin/ctfdump/ctfdump.c

367

uint32_t objtoff = cth.cth_objtoff;

usr.bin/ctfdump/ctfdump.c

420

uint32_t idx = 1, offset = cth.cth_typeoff;

usr.bin/ctfdump/ctfdump.c

421

uint32_t stroff = cth.cth_stroff;

usr.bin/ctfdump/ctfdump.c

430

uint32_t offset = 0;

usr.bin/ctfdump/ctfdump.c

455

uint32_t stroff, uint32_t *offset, uint32_t idx)

usr.bin/ctfdump/ctfdump.c

461

uint32_t eob, toff;

usr.bin/ctfdump/ctfdump.c

491

eob = *((uint32_t *)(p + toff));

usr.bin/ctfdump/ctfdump.c

492

toff += sizeof(uint32_t);

usr.bin/ctfdump/ctfdump.c

498

eob = *((uint32_t *)(p + toff));

usr.bin/ctfdump/ctfdump.c

499

toff += sizeof(uint32_t);

usr.bin/ctfdump/ctfdump.c

57

uint32_t, uint32_t *, uint32_t);

usr.bin/ctfdump/ctfdump.c

62

uint32_t);

usr.bin/ctfdump/ctfdump.c

647

uint32_t offset)

usr.bin/cu/cu.c

508

uint32_t unit;

usr.bin/cvs/hash.c

57

uint32_t hashv;

usr.bin/cvs/hash.c

73

uint32_t hashv;

usr.bin/dig/dig.c

1292

uint32_t num;

usr.bin/dig/dig.c

1461

uint32_t serial;

usr.bin/dig/dig.c

1705

uint32_t serial;

usr.bin/dig/dig.c

649

uint32_t num;

usr.bin/dig/dig.c

70

static uint32_t splitwidth = 0xffffffff;

usr.bin/dig/dig.h

139

uint32_t retries;

usr.bin/dig/dig.h

143

uint32_t ixfr_serial;

usr.bin/dig/dig.h

148

uint32_t msgcounter;

usr.bin/dig/dig.h

173

uint32_t first_rr_serial;

usr.bin/dig/dig.h

174

uint32_t second_rr_serial;

usr.bin/dig/dig.h

175

uint32_t msg_count;

usr.bin/dig/dig.h

176

uint32_t rr_count;

usr.bin/dig/dighost.c

1260

uint32_t code;

usr.bin/dig/dighost.c

1286

uint32_t num = 0;

usr.bin/dig/dighost.c

1718

uint32_t i, j;

usr.bin/dig/dighost.c

1902

uint32_t id;

usr.bin/dig/dighost.c

2151

uint32_t plen;

usr.bin/dig/dighost.c

2975

uint32_t ixfr_serial = query->lookup->ixfr_serial, serial;

usr.bin/dig/dighost.c

921

static uint32_t

usr.bin/dig/dighost.c

922

parse_bits(char *arg, uint32_t max) {

usr.bin/dig/dighost.c

923

uint32_t tmp;

usr.bin/dig/host.c

619

uint32_t serial = 0;

usr.bin/dig/lib/dns/dns_time.c

53

dns_time64_from32(uint32_t value) {

usr.bin/dig/lib/dns/dns_time.c

54

uint32_t now32;

usr.bin/dig/lib/dns/dns_time.c

59

now32 = (uint32_t) start;

usr.bin/dig/lib/dns/dns_time.c

71

dns_time32_totext(uint32_t value, isc_buffer_t *target) {

usr.bin/dig/lib/dns/dst_internal.h

77

uint32_t key_flags; /*%< flags of the public key */

usr.bin/dig/lib/dns/include/dns/rdata.h

119

uint32_t serial; /*%< host order */

usr.bin/dig/lib/dns/include/dns/rdata.h

120

uint32_t refresh; /*%< host order */

usr.bin/dig/lib/dns/include/dns/rdata.h

121

uint32_t retry; /*%< host order */

usr.bin/dig/lib/dns/include/dns/rdata.h

122

uint32_t expire; /*%< host order */

usr.bin/dig/lib/dns/include/dns/rdata.h

123

uint32_t minimum; /*%< host order */

usr.bin/dig/lib/dns/include/dns/rdataset.h

100

uint32_t count;

usr.bin/dig/lib/dns/include/dns/time.h

35

dns_time32_totext(uint32_t value, isc_buffer_t *target);

usr.bin/dig/lib/dns/include/dns/ttl.h

35

dns_ttl_totext(uint32_t src, int verbose,

usr.bin/dig/lib/dns/include/dns/types.h

56

typedef uint32_t dns_ttl_t;

usr.bin/dig/lib/dns/key.c

31

uint32_t ac;

usr.bin/dig/lib/dns/masterdump.c

247

uint32_t current_ttl;

usr.bin/dig/lib/dns/masterdump.c

70

uint32_t current_ttl;

usr.bin/dig/lib/dns/message.c

2529

uint32_t mbz;

usr.bin/dig/lib/dns/message.c

2608

uint32_t secs;

usr.bin/dig/lib/dns/message.c

2679

uint32_t serial;

usr.bin/dig/lib/dns/rdata.c

107

uint32_tobuffer(uint32_t, isc_buffer_t *target);

usr.bin/dig/lib/dns/rdata.c

110

uint16_tobuffer(uint32_t, isc_buffer_t *target);

usr.bin/dig/lib/dns/rdata.c

115

static uint32_t

usr.bin/dig/lib/dns/rdata.c

1308

uint32_tobuffer(uint32_t value, isc_buffer_t *target) {

usr.bin/dig/lib/dns/rdata.c

1319

uint16_tobuffer(uint32_t value, isc_buffer_t *target) {

usr.bin/dig/lib/dns/rdata.c

1338

static uint32_t

usr.bin/dig/lib/dns/rdata.c

1340

uint32_t value;

usr.bin/dig/lib/dns/rdata.c

366

uint32_t activelength;

usr.bin/dig/lib/dns/rdata/any_255/tsig_250.c

250

RETERR(uint32_tobuffer((uint32_t)(tsig->timesigned & 0xffffffffU),

usr.bin/dig/lib/dns/rdata/generic/doa_259.c

24

uint32_t n;

usr.bin/dig/lib/dns/rdata/generic/nsec3_50.c

49

uint32_t iterations;

usr.bin/dig/lib/dns/rdata/generic/nsec3param_51.c

49

uint32_t iterations;

usr.bin/dig/lib/dns/rdata/generic/zonemd_63.c

30

uint32_t n;

usr.bin/dig/lib/dns/rdataset.c

249

uint32_t val;

usr.bin/dig/lib/dns/ttl.c

70

dns_ttl_totext(uint32_t src, int verbose, isc_buffer_t *target) {

usr.bin/dig/lib/isc/buffer.c

232

uint32_t

usr.bin/dig/lib/isc/buffer.c

235

uint32_t result;

usr.bin/dig/lib/isc/buffer.c

255

isc__buffer_putuint32(isc_buffer_t *b, uint32_t val) {

usr.bin/dig/lib/isc/buffer.c

264

uint32_t vallo;

usr.bin/dig/lib/isc/buffer.c

269

vallo = (uint32_t)(val & 0xFFFFFFFF);

usr.bin/dig/lib/isc/hash.c

112

uint32_t

usr.bin/dig/lib/isc/hash.c

115

const uint32_t *previous_hashp)

usr.bin/dig/lib/isc/hash.c

117

uint32_t hval;

usr.bin/dig/lib/isc/hash.c

148

hval ^= (uint32_t) be[3];

usr.bin/dig/lib/isc/hash.c

150

hval ^= (uint32_t) be[2];

usr.bin/dig/lib/isc/hash.c

152

hval ^= (uint32_t) be[1];

usr.bin/dig/lib/isc/hash.c

154

hval ^= (uint32_t) be[0];

usr.bin/dig/lib/isc/hash.c

158

hval ^= (uint32_t) *be;

usr.bin/dig/lib/isc/hash.c

164

hval ^= (uint32_t) maptolower[be[3]];

usr.bin/dig/lib/isc/hash.c

166

hval ^= (uint32_t) maptolower[be[2]];

usr.bin/dig/lib/isc/hash.c

168

hval ^= (uint32_t) maptolower[be[1]];

usr.bin/dig/lib/isc/hash.c

170

hval ^= (uint32_t) maptolower[be[0]];

usr.bin/dig/lib/isc/hash.c

174

hval ^= (uint32_t) maptolower[*be];

usr.bin/dig/lib/isc/hash.c

97

static uint32_t fnv_offset_basis;

usr.bin/dig/lib/isc/include/isc/buffer.h

450

uint32_t

usr.bin/dig/lib/isc/include/isc/buffer.h

472

isc__buffer_putuint32(isc_buffer_t *b, uint32_t val);

usr.bin/dig/lib/isc/include/isc/buffer.h

690

uint32_t _val2 = (_val); \

usr.bin/dig/lib/isc/include/isc/hash.h

93

uint32_t

usr.bin/dig/lib/isc/include/isc/hash.h

96

const uint32_t *previous_hashp);

usr.bin/dig/lib/isc/include/isc/serial.h

34

isc_serial_gt(uint32_t a, uint32_t b);

usr.bin/dig/lib/isc/include/isc/serial.h

40

isc_serial_ge(uint32_t a, uint32_t b);

usr.bin/dig/lib/isc/include/isc/socket.h

99

uint32_t attributes; /*%< see below */

usr.bin/dig/lib/isc/serial.c

24

isc_serial_gt(uint32_t a, uint32_t b) {

usr.bin/dig/lib/isc/serial.c

29

isc_serial_ge(uint32_t a, uint32_t b) {

usr.bin/dig/lib/lwres/include/lwres/lwres.h

93

uint32_t family;

usr.bin/dig/lib/lwres/include/lwres/lwres.h

96

uint32_t zone;

usr.bin/dig/nslookup.c

526

uint32_t n;

usr.bin/dig/nslookup.c

538

uint32_t n;

usr.bin/dig/nslookup.c

550

uint32_t n;

usr.bin/dig/nslookup.c

562

uint32_t n;

usr.bin/file/magic-test.c

1274

uint32_t l;

usr.bin/file/magic-test.c

525

uint32_t value;

usr.bin/file/magic-test.c

536

value &= (uint32_t)ml->type_operand;

usr.bin/file/magic-test.c

538

value -= (uint32_t)ml->type_operand;

usr.bin/file/magic-test.c

540

value += (uint32_t)ml->type_operand;

usr.bin/file/magic-test.c

542

value /= (uint32_t)ml->type_operand;

usr.bin/file/magic-test.c

544

value %= (uint32_t)ml->type_operand;

usr.bin/file/magic-test.c

546

value *= (uint32_t)ml->type_operand;

usr.bin/file/magic-test.c

550

result = magic_test_unsigned(ml, value, (uint32_t)ml->test_unsigned);

usr.bin/file/magic-test.c

597

uint32_t value0;

usr.bin/file/magic-test.c

868

uint32_t value;

usr.bin/file/magic-test.c

883

value &= (uint32_t)ml->type_operand;

usr.bin/file/magic-test.c

885

value -= (uint32_t)ml->type_operand;

usr.bin/file/magic-test.c

887

value += (uint32_t)ml->type_operand;

usr.bin/file/magic-test.c

891

result = magic_test_unsigned(ml, value, (uint32_t)ml->test_unsigned);

usr.bin/ftp/main.c

232

uint32_t protocols;

usr.bin/jot/jot.c

254

uint32_t pow10 = 1;

usr.bin/jot/jot.c

255

uint32_t uintx = 0; /* Initialized to make gcc happy. */

usr.bin/lex/flexint.h

25

typedef uint32_t flex_uint32_t;

usr.bin/make/cond.c

932

uint32_t k;

usr.bin/make/dir.c

222

uint32_t);

usr.bin/make/dir.c

288

uint32_t hv)

usr.bin/make/dir.c

426

uint32_t hv; /* hash value for last component in file name */

usr.bin/make/generate.c

129

uint32_t i;

usr.bin/make/generate.c

130

uint32_t v;

usr.bin/make/generate.c

131

uint32_t h;

usr.bin/make/generate.c

132

uint32_t slots;

usr.bin/make/parse.c

1417

uint32_t hv;

usr.bin/make/parse.c

182

uint32_t hv;

usr.bin/make/suff.c

1111

uint32_t hv;

usr.bin/make/suff.c

150

static void reverse_hash_add_char(uint32_t *, const char *);

usr.bin/make/suff.c

151

static uint32_t reverse_hashi(const char *, const char **);

usr.bin/make/suff.c

188

reverse_hash_add_char(uint32_t *pk, const char *s)

usr.bin/make/suff.c

194

static uint32_t

usr.bin/make/suff.c

198

uint32_t k;

usr.bin/make/suff.c

216

uint32_t hv;

usr.bin/make/suff.c

356

uint32_t hv;

usr.bin/make/suff.c

430

uint32_t hv;

usr.bin/make/targ.c

192

uint32_t hv;

usr.bin/make/targ.c

211

Targ_mk_special_node(const char *name, size_t n, uint32_t hv,

usr.bin/make/targ.h

50

extern GNode *Targ_mk_special_node(const char *, size_t, uint32_t,

usr.bin/make/var.c

1118

uint32_t k;

usr.bin/make/var.c

1188

uint32_t k;

usr.bin/make/var.c

1309

uint32_t k;

usr.bin/make/var.c

1324

uint32_t k;

usr.bin/make/var.c

210

static int classify_var(const char *, const char **, uint32_t *, char *);

usr.bin/make/var.c

211

static Var *find_global_var(const char *, const char *, uint32_t);

usr.bin/make/var.c

212

static Var *find_global_var_without_env(const char *, const char *, uint32_t);

usr.bin/make/var.c

237

static char *get_expanded_value(const char *, const char *, int, uint32_t, char,

usr.bin/make/var.c

247

classify_var(const char *name, const char **enamePtr, uint32_t *pk, char *ext)

usr.bin/make/var.c

250

uint32_t k;

usr.bin/make/var.c

446

find_global_var_without_env(const char *name, const char *ename, uint32_t k)

usr.bin/make/var.c

484

find_global_var(const char *name, const char *ename, uint32_t k)

usr.bin/make/var.c

504

uint32_t k;

usr.bin/make/var.c

558

uint32_t k;

usr.bin/make/var.c

593

uint32_t k;

usr.bin/make/var.c

692

uint32_t k;

usr.bin/make/var.c

716

uint32_t k;

usr.bin/make/var.c

893

get_expanded_value(const char *name, const char *ename, int idx, uint32_t k,

usr.bin/make/var.c

984

uint32_t k;

usr.bin/mandoc/mandoc_xr.c

70

uint32_t hv;

usr.bin/nc/netcat.c

166

uint32_t protocols;

usr.bin/rsync/blocks.c

146

uint32_t fhash;

usr.bin/rsync/extern.h

188

uint32_t chksum_short; /* fast checksum */

usr.bin/rsync/extern.h

218

uint32_t s1; /* partial sum for computing fast hash */

usr.bin/rsync/extern.h

219

uint32_t s2; /* partial sum for computing fast hash */

usr.bin/rsync/extern.h

332

int io_read_uint(struct sess *, int, uint32_t *);

usr.bin/rsync/extern.h

339

int io_write_uint(struct sess *, int, uint32_t);

usr.bin/rsync/extern.h

389

uint32_t hash_fast(const void *, size_t);

usr.bin/rsync/flist.c

322

} else if (!io_write_uint(sess, fdout, (uint32_t)f->st.mtime)) {

usr.bin/rsync/flist.c

599

uint32_t uival;

usr.bin/rsync/hash.c

33

uint32_t

usr.bin/rsync/hash.c

37

uint32_t a = 0, /* part of a(k, l) */

usr.bin/rsync/ids.c

106

uint32_t id;

usr.bin/rsync/ids.c

270

uint32_t id;

usr.bin/rsync/io.c

430

io_write_uint(struct sess *sess, int fd, uint32_t val)

usr.bin/rsync/io.c

432

uint32_t nv;

usr.bin/rsync/io.c

436

if (!io_write_buf(sess, fd, &nv, sizeof(uint32_t))) {

usr.bin/rsync/io.c

450

return io_write_uint(sess, fd, (uint32_t)val);

usr.bin/rsync/io.c

634

io_read_uint(struct sess *sess, int fd, uint32_t *val)

usr.bin/rsync/io.c

636

uint32_t oval;

usr.bin/rsync/io.c

638

if (!io_read_buf(sess, fd, &oval, sizeof(uint32_t))) {

usr.bin/rsync/io.c

650

return io_read_uint(sess, fd, (uint32_t *)val);

usr.bin/rsync/sender.c

303

if (idx < 0 || (uint32_t)idx >= flsz) {

usr.bin/signify/crypto_api.h

15

typedef uint32_t crypto_uint32;

usr.bin/signify/signify.c

55

uint32_t kdfrounds;

usr.bin/signify/zsig.c

33

uint32_t mtime;

usr.bin/sndiod/sock.c

592

uint32_t rate, appbufsz;

usr.bin/snmp/smi.h

71

uint32_t tce_number;

usr.bin/snmp/snmpc.c

830

uint32_t index;

usr.bin/snmp/usm.c

261

uint32_t ivv;

usr.bin/snmp/usm.c

51

uint32_t boots;

usr.bin/snmp/usm.c

53

uint32_t time;

usr.bin/snmp/usm.c

60

uint32_t boots;

usr.bin/snmp/usm.c

608

usm_setbootstime(struct snmp_sec *sec, uint32_t boots, uint32_t time)

usr.bin/snmp/usm.c

61

uint32_t time;

usr.bin/snmp/usm.h

34

int usm_setbootstime(struct snmp_sec *, uint32_t, uint32_t);

usr.bin/ssh/addr.c

305

uint32_t n;

usr.bin/ssh/addr.h

32

uint32_t addr32[4];

usr.bin/ssh/addr.h

34

uint32_t scope_id; /* iface scope id for v6 */

usr.bin/ssh/auth2-chall.c

255

input_userauth_info_response(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/auth2-chall.c

47

static int input_userauth_info_response(int, uint32_t, struct ssh *);

usr.bin/ssh/auth2-gss.c

144

input_gssapi_token(int type, uint32_t plen, struct ssh *ssh)

usr.bin/ssh/auth2-gss.c

208

input_gssapi_errtok(int type, uint32_t plen, struct ssh *ssh)

usr.bin/ssh/auth2-gss.c

252

input_gssapi_exchange_complete(int type, uint32_t plen, struct ssh *ssh)

usr.bin/ssh/auth2-gss.c

280

input_gssapi_mic(int type, uint32_t plen, struct ssh *ssh)

usr.bin/ssh/auth2-gss.c

54

static int input_gssapi_token(int type, uint32_t plen, struct ssh *ssh);

usr.bin/ssh/auth2-gss.c

55

static int input_gssapi_mic(int type, uint32_t plen, struct ssh *ssh);

usr.bin/ssh/auth2-gss.c

56

static int input_gssapi_exchange_complete(int type, uint32_t plen, struct ssh *ssh);

usr.bin/ssh/auth2-gss.c

57

static int input_gssapi_errtok(int, uint32_t, struct ssh *);

usr.bin/ssh/auth2.c

174

input_service_request(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/auth2.c

259

input_userauth_request(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/auth2.c

88

static int input_service_request(int, uint32_t, struct ssh *);

usr.bin/ssh/auth2.c

89

static int input_userauth_request(int, uint32_t, struct ssh *);

usr.bin/ssh/authfd.c

263

uint32_t num, i;

usr.bin/ssh/channels.c

3330

channel_proxy_upstream(Channel *c, int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/channels.c

3413

uint32_t id;

usr.bin/ssh/channels.c

3442

channel_input_data(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/channels.c

3513

channel_input_extended_data(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/channels.c

3517

uint32_t tcode;

usr.bin/ssh/channels.c

3566

channel_input_ieof(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/channels.c

3591

channel_input_oclose(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/channels.c

3607

channel_input_open_confirmation(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/channels.c

3610

uint32_t remote_window, remote_maxpacket;

usr.bin/ssh/channels.c

3662

channel_input_open_failure(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/channels.c

3665

uint32_t reason;

usr.bin/ssh/channels.c

3699

channel_input_window_adjust(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/channels.c

3703

uint32_t adjust;

usr.bin/ssh/channels.c

3729

channel_input_status_confirm(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/channels.h

132

uint32_t remote_id; /* channel identifier for remote peer */

usr.bin/ssh/channels.h

146

uint32_t ctl_child_id; /* child session for mux controllers */

usr.bin/ssh/channels.h

326

int channel_proxy_upstream(Channel *, int, uint32_t, struct ssh *);

usr.bin/ssh/channels.h

330

int channel_input_data(int, uint32_t, struct ssh *);

usr.bin/ssh/channels.h

331

int channel_input_extended_data(int, uint32_t, struct ssh *);

usr.bin/ssh/channels.h

332

int channel_input_ieof(int, uint32_t, struct ssh *);

usr.bin/ssh/channels.h

333

int channel_input_oclose(int, uint32_t, struct ssh *);

usr.bin/ssh/channels.h

334

int channel_input_open_confirmation(int, uint32_t, struct ssh *);

usr.bin/ssh/channels.h

335

int channel_input_open_failure(int, uint32_t, struct ssh *);

usr.bin/ssh/channels.h

336

int channel_input_window_adjust(int, uint32_t, struct ssh *);

usr.bin/ssh/channels.h

337

int channel_input_status_confirm(int, uint32_t, struct ssh *);

usr.bin/ssh/clientloop.c

1903

client_input_channel_open(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/clientloop.c

1966

client_input_channel_req(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/clientloop.c

2344

uint32_t seq, void *_ctx)

usr.bin/ssh/clientloop.c

2654

client_input_global_request(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/clientloop.c

463

client_global_request_reply(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/clientloop.h

58

typedef void global_confirm_cb(struct ssh *, int, uint32_t, void *);

usr.bin/ssh/compat.c

45

uint32_t bugs;

usr.bin/ssh/crypto_api.h

19

typedef uint32_t crypto_uint32;

usr.bin/ssh/dispatch.c

38

dispatch_protocol_error(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/dispatch.c

52

dispatch_protocol_ignore(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/dispatch.c

89

uint32_t seqnr;

usr.bin/ssh/dispatch.h

39

typedef int dispatch_fn(int, uint32_t, struct ssh *);

usr.bin/ssh/dispatch.h

41

int dispatch_protocol_error(int, uint32_t, struct ssh *);

usr.bin/ssh/dispatch.h

42

int dispatch_protocol_ignore(int, uint32_t, struct ssh *);

usr.bin/ssh/kex.c

231

kex_protocol_error(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/kex.c

480

kex_input_ext_info(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/kex.c

484

uint32_t i, ninfo;

usr.bin/ssh/kex.c

527

kex_input_newkeys(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/kex.c

611

kex_input_kexinit(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/kex.c

63

static int kex_choose_conf(struct ssh *, uint32_t seq);

usr.bin/ssh/kex.c

64

static int kex_input_newkeys(int, uint32_t, struct ssh *);

usr.bin/ssh/kex.c

928

kex_choose_conf(struct ssh *ssh, uint32_t seq)

usr.bin/ssh/kex.h

215

int kex_input_kexinit(int, uint32_t, struct ssh *);

usr.bin/ssh/kex.h

216

int kex_input_ext_info(int, uint32_t, struct ssh *);

usr.bin/ssh/kex.h

217

int kex_protocol_error(int, uint32_t, struct ssh *);

usr.bin/ssh/kexgen.c

140

input_kex_gen_reply(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/kexgen.c

273

input_kex_gen_init(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/kexgen.c

42

static int input_kex_gen_init(int, uint32_t, struct ssh *);

usr.bin/ssh/kexgen.c

43

static int input_kex_gen_reply(int type, uint32_t seq, struct ssh *ssh);

usr.bin/ssh/kexgexc.c

139

input_kex_dh_gex_reply(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/kexgexc.c

50

static int input_kex_dh_gex_group(int, uint32_t, struct ssh *);

usr.bin/ssh/kexgexc.c

51

static int input_kex_dh_gex_reply(int, uint32_t, struct ssh *);

usr.bin/ssh/kexgexc.c

89

input_kex_dh_gex_group(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/kexgexs.c

121

input_kex_dh_gex_init(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/kexgexs.c

52

static int input_kex_dh_gex_request(int, uint32_t, struct ssh *);

usr.bin/ssh/kexgexs.c

53

static int input_kex_dh_gex_init(int, uint32_t, struct ssh *);

usr.bin/ssh/kexgexs.c

65

input_kex_dh_gex_request(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/libcrux_mlkem768_sha3.h

1176

domain_separator = (uint32_t)domain_separator + 1U;

usr.bin/ssh/libcrux_mlkem768_sha3.h

1518

(uint8_t)((uint32_t)core_num__u16__wrapping_add(~value0, 1U) >> 8U);

usr.bin/ssh/libcrux_mlkem768_sha3.h

1519

return (uint32_t)result & 1U;

usr.bin/ssh/libcrux_mlkem768_sha3.h

1536

uint8_t nr = (uint32_t)r |

usr.bin/ssh/libcrux_mlkem768_sha3.h

1537

((uint32_t)Eurydice_slice_index(lhs, i0, uint8_t, uint8_t *) ^

usr.bin/ssh/libcrux_mlkem768_sha3.h

1538

(uint32_t)Eurydice_slice_index(rhs, i0, uint8_t, uint8_t *));

usr.bin/ssh/libcrux_mlkem768_sha3.h

1564

((uint32_t)Eurydice_slice_index(lhs, i0, uint8_t, uint8_t *) &

usr.bin/ssh/libcrux_mlkem768_sha3.h

1565

(uint32_t)mask) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

1566

((uint32_t)Eurydice_slice_index(rhs, i0, uint8_t, uint8_t *) &

usr.bin/ssh/libcrux_mlkem768_sha3.h

1567

(uint32_t)~mask);

usr.bin/ssh/libcrux_mlkem768_sha3.h

1651

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)1);

usr.bin/ssh/libcrux_mlkem768_sha3.h

1990

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)36);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2026

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)3);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2062

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)41);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2098

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)18);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2159

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)44);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2195

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)10);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2231

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)45);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2267

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)2);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2303

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)62);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2339

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)6);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2375

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)43);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2411

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)15);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2447

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)61);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2483

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)28);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2519

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)55);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2555

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)25);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2591

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)21);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2627

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)56);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2663

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)27);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2699

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)20);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2735

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)39);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2771

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)8);

usr.bin/ssh/libcrux_mlkem768_sha3.h

2807

return core_num__u64__rotate_left(x, (uint32_t)(int32_t)14);

usr.bin/ssh/libcrux_mlkem768_sha3.h

3296

buffer[uu____0] = (uint32_t)buffer[uu____0] | 128U;

usr.bin/ssh/libcrux_mlkem768_sha3.h

346

static inline void core_num__u32__to_be_bytes(uint32_t src, uint8_t dst[4]) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

350

static inline void core_num__u32__to_le_bytes(uint32_t src, uint8_t dst[4]) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

3518

buffer[uu____0] = (uint32_t)buffer[uu____0] | 128U;

usr.bin/ssh/libcrux_mlkem768_sha3.h

354

static inline uint32_t core_num__u32__from_le_bytes(uint8_t buf[4]) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

3675

buffer[uu____0] = (uint32_t)buffer[uu____0] | 128U;

usr.bin/ssh/libcrux_mlkem768_sha3.h

3821

buffer[uu____0] = (uint32_t)buffer[uu____0] | 128U;

usr.bin/ssh/libcrux_mlkem768_sha3.h

386

static inline uint32_t core_num__u8__count_ones(uint8_t x0) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

394

static inline uint32_t core_num__i32__count_ones(int32_t x0) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

4113

buffer[uu____0] = (uint32_t)buffer[uu____0] | 128U;

usr.bin/ssh/libcrux_mlkem768_sha3.h

417

static inline uint64_t core_num__u64__rotate_left(uint64_t x0, uint32_t x1) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

431

static inline uint32_t Eurydice_min_u32(uint32_t x, uint32_t y) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

4336

buffer[uu____0] = (uint32_t)buffer[uu____0] | 128U;

usr.bin/ssh/libcrux_mlkem768_sha3.h

51

store32_le(uint8_t dst[4], uint32_t src)

usr.bin/ssh/libcrux_mlkem768_sha3.h

5389

static inline uint32_t libcrux_sha3_from_6c(libcrux_sha3_Algorithm v) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

5416

static inline libcrux_sha3_Algorithm libcrux_sha3_from_29(uint32_t v) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

5698

((int32_t)1 << (uint32_t)LIBCRUX_ML_KEM_VECTOR_TRAITS_BARRETT_SHIFT)

usr.bin/ssh/libcrux_mlkem768_sha3.h

5722

t >> (uint32_t)LIBCRUX_ML_KEM_VECTOR_TRAITS_BARRETT_SHIFT);

usr.bin/ssh/libcrux_mlkem768_sha3.h

5783

(uint32_t)LIBCRUX_ML_KEM_VECTOR_PORTABLE_ARITHMETIC_MONTGOMERY_SHIFT);

usr.bin/ssh/libcrux_mlkem768_sha3.h

5786

(uint32_t)LIBCRUX_ML_KEM_VECTOR_PORTABLE_ARITHMETIC_MONTGOMERY_SHIFT);

usr.bin/ssh/libcrux_mlkem768_sha3.h

5858

vec.elements[i0] = vec.elements[i0] >> (uint32_t)(int32_t)15;

usr.bin/ssh/libcrux_mlkem768_sha3.h

5944

static KRML_MUSTINLINE uint32_t

usr.bin/ssh/libcrux_mlkem768_sha3.h

5946

uint8_t n, uint32_t value) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

5947

return value & ((1U << (uint32_t)n) - 1U);

usr.bin/ssh/libcrux_mlkem768_sha3.h

5954

<< (uint32_t)coefficient_bits;

usr.bin/ssh/libcrux_mlkem768_sha3.h

60

store32_be(uint8_t dst[4], uint32_t src)

usr.bin/ssh/libcrux_mlkem768_sha3.h

601

static inline uint64_t core_num__u64__rotate_left(uint64_t x0, uint32_t x1);

usr.bin/ssh/libcrux_mlkem768_sha3.h

605

static inline uint32_t core_num__u8__count_ones(uint8_t x0);

usr.bin/ssh/libcrux_mlkem768_sha3.h

6330

(((((((uint32_t)libcrux_secrets_int_as_u8_f5(v.elements[0U]) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

6331

(uint32_t)libcrux_secrets_int_as_u8_f5(v.elements[1U]) << 1U) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

6332

(uint32_t)libcrux_secrets_int_as_u8_f5(v.elements[2U]) << 2U) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

6333

(uint32_t)libcrux_secrets_int_as_u8_f5(v.elements[3U]) << 3U) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

6334

(uint32_t)libcrux_secrets_int_as_u8_f5(v.elements[4U]) << 4U) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

6335

(uint32_t)libcrux_secrets_int_as_u8_f5(v.elements[5U]) << 5U) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

6336

(uint32_t)libcrux_secrets_int_as_u8_f5(v.elements[6U]) << 6U) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

6337

(uint32_t)libcrux_secrets_int_as_u8_f5(v.elements[7U]) << 7U;

usr.bin/ssh/libcrux_mlkem768_sha3.h

6339

(((((((uint32_t)libcrux_secrets_int_as_u8_f5(v.elements[8U]) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

6340

(uint32_t)libcrux_secrets_int_as_u8_f5(v.elements[9U]) << 1U) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

6341

(uint32_t)libcrux_secrets_int_as_u8_f5(v.elements[10U]) << 2U) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

6342

(uint32_t)libcrux_secrets_int_as_u8_f5(v.elements[11U]) << 3U) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

6343

(uint32_t)libcrux_secrets_int_as_u8_f5(v.elements[12U]) << 4U) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

6344

(uint32_t)libcrux_secrets_int_as_u8_f5(v.elements[13U]) << 5U) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

6345

(uint32_t)libcrux_secrets_int_as_u8_f5(v.elements[14U]) << 6U) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

6346

(uint32_t)libcrux_secrets_int_as_u8_f5(v.elements[15U]) << 7U;

usr.bin/ssh/libcrux_mlkem768_sha3.h

6372

(uint32_t)Eurydice_slice_index(v, (size_t)0U, uint8_t, uint8_t *) & 1U);

usr.bin/ssh/libcrux_mlkem768_sha3.h

6374

(uint32_t)Eurydice_slice_index(v, (size_t)0U, uint8_t, uint8_t *) >> 1U &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6377

(uint32_t)Eurydice_slice_index(v, (size_t)0U, uint8_t, uint8_t *) >> 2U &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6380

(uint32_t)Eurydice_slice_index(v, (size_t)0U, uint8_t, uint8_t *) >> 3U &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6383

(uint32_t)Eurydice_slice_index(v, (size_t)0U, uint8_t, uint8_t *) >> 4U &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6386

(uint32_t)Eurydice_slice_index(v, (size_t)0U, uint8_t, uint8_t *) >> 5U &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6389

(uint32_t)Eurydice_slice_index(v, (size_t)0U, uint8_t, uint8_t *) >> 6U &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6392

(uint32_t)Eurydice_slice_index(v, (size_t)0U, uint8_t, uint8_t *) >> 7U &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6395

(uint32_t)Eurydice_slice_index(v, (size_t)1U, uint8_t, uint8_t *) & 1U);

usr.bin/ssh/libcrux_mlkem768_sha3.h

6397

(uint32_t)Eurydice_slice_index(v, (size_t)1U, uint8_t, uint8_t *) >> 1U &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6400

(uint32_t)Eurydice_slice_index(v, (size_t)1U, uint8_t, uint8_t *) >> 2U &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6403

(uint32_t)Eurydice_slice_index(v, (size_t)1U, uint8_t, uint8_t *) >> 3U &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6406

(uint32_t)Eurydice_slice_index(v, (size_t)1U, uint8_t, uint8_t *) >> 4U &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6409

(uint32_t)Eurydice_slice_index(v, (size_t)1U, uint8_t, uint8_t *) >> 5U &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6412

(uint32_t)Eurydice_slice_index(v, (size_t)1U, uint8_t, uint8_t *) >> 6U &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6415

(uint32_t)Eurydice_slice_index(v, (size_t)1U, uint8_t, uint8_t *) >> 7U &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6448

uint8_t result0 = (uint32_t)libcrux_secrets_int_as_u8_f5(

usr.bin/ssh/libcrux_mlkem768_sha3.h

6451

(uint32_t)libcrux_secrets_int_as_u8_f5(Eurydice_slice_index(

usr.bin/ssh/libcrux_mlkem768_sha3.h

6453

uint8_t result1 = (uint32_t)libcrux_secrets_int_as_u8_f5(

usr.bin/ssh/libcrux_mlkem768_sha3.h

6456

(uint32_t)libcrux_secrets_int_as_u8_f5(Eurydice_slice_index(

usr.bin/ssh/libcrux_mlkem768_sha3.h

6458

uint8_t result2 = (uint32_t)libcrux_secrets_int_as_u8_f5(

usr.bin/ssh/libcrux_mlkem768_sha3.h

6461

(uint32_t)libcrux_secrets_int_as_u8_f5(Eurydice_slice_index(

usr.bin/ssh/libcrux_mlkem768_sha3.h

6463

uint8_t result3 = (uint32_t)libcrux_secrets_int_as_u8_f5(

usr.bin/ssh/libcrux_mlkem768_sha3.h

6466

(uint32_t)libcrux_secrets_int_as_u8_f5(Eurydice_slice_index(

usr.bin/ssh/libcrux_mlkem768_sha3.h

6516

(uint32_t)Eurydice_slice_index(bytes, (size_t)0U, uint8_t, uint8_t *) &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6519

(uint32_t)Eurydice_slice_index(bytes, (size_t)0U, uint8_t, uint8_t *) >>

usr.bin/ssh/libcrux_mlkem768_sha3.h

6523

(uint32_t)Eurydice_slice_index(bytes, (size_t)1U, uint8_t, uint8_t *) &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6526

(uint32_t)Eurydice_slice_index(bytes, (size_t)1U, uint8_t, uint8_t *) >>

usr.bin/ssh/libcrux_mlkem768_sha3.h

6530

(uint32_t)Eurydice_slice_index(bytes, (size_t)2U, uint8_t, uint8_t *) &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6533

(uint32_t)Eurydice_slice_index(bytes, (size_t)2U, uint8_t, uint8_t *) >>

usr.bin/ssh/libcrux_mlkem768_sha3.h

6537

(uint32_t)Eurydice_slice_index(bytes, (size_t)3U, uint8_t, uint8_t *) &

usr.bin/ssh/libcrux_mlkem768_sha3.h

6540

(uint32_t)Eurydice_slice_index(bytes, (size_t)3U, uint8_t, uint8_t *) >>

usr.bin/ssh/libcrux_mlkem768_sha3.h

6594

(uint32_t)libcrux_secrets_int_as_u8_f5(

usr.bin/ssh/libcrux_mlkem768_sha3.h

6597

(uint32_t)libcrux_secrets_int_as_u8_f5(

usr.bin/ssh/libcrux_mlkem768_sha3.h

6601

(uint32_t)libcrux_secrets_int_as_u8_f5(

usr.bin/ssh/libcrux_mlkem768_sha3.h

6604

(uint32_t)libcrux_secrets_int_as_u8_f5(

usr.bin/ssh/libcrux_mlkem768_sha3.h

6608

(uint32_t)libcrux_secrets_int_as_u8_f5(

usr.bin/ssh/libcrux_mlkem768_sha3.h

6611

(uint32_t)libcrux_secrets_int_as_u8_f5(

usr.bin/ssh/libcrux_mlkem768_sha3.h

7193

decompressed = (decompressed << 1U) + ((int32_t)1 << (uint32_t)(int32_t)10);

usr.bin/ssh/libcrux_mlkem768_sha3.h

7194

decompressed = decompressed >> (uint32_t)((int32_t)10 + (int32_t)1);

usr.bin/ssh/libcrux_mlkem768_sha3.h

7292

size_t step = (size_t)1U << (uint32_t)layer;

usr.bin/ssh/libcrux_mlkem768_sha3.h

7293

for (size_t i0 = (size_t)0U; i0 < (size_t)128U >> (uint32_t)layer; i0++) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

7500

decompressed = (decompressed << 1U) + ((int32_t)1 << (uint32_t)(int32_t)4);

usr.bin/ssh/libcrux_mlkem768_sha3.h

7501

decompressed = decompressed >> (uint32_t)((int32_t)4 + (int32_t)1);

usr.bin/ssh/libcrux_mlkem768_sha3.h

756

static KRML_MUSTINLINE uint32_t

usr.bin/ssh/libcrux_mlkem768_sha3.h

757

libcrux_secrets_int_public_integers_declassify_d8_df(uint32_t self) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

764

static KRML_MUSTINLINE int32_t libcrux_secrets_int_as_i32_b8(uint32_t self) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

7795

size_t step = (size_t)1U << (uint32_t)layer;

usr.bin/ssh/libcrux_mlkem768_sha3.h

7796

for (size_t i0 = (size_t)0U; i0 < (size_t)128U >> (uint32_t)layer; i0++) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

81

static inline uint32_t

usr.bin/ssh/libcrux_mlkem768_sha3.h

84

return (uint32_t)(src[0]) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

840

static KRML_MUSTINLINE uint32_t

usr.bin/ssh/libcrux_mlkem768_sha3.h

841

libcrux_secrets_int_public_integers_classify_27_df(uint32_t self) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

85

((uint32_t)(src[1]) << 8) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

86

((uint32_t)(src[2]) << 16) |

usr.bin/ssh/libcrux_mlkem768_sha3.h

861

static KRML_MUSTINLINE uint32_t libcrux_secrets_int_as_u32_a3(uint64_t self) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

863

(uint32_t)libcrux_secrets_int_public_integers_declassify_d8_49(self));

usr.bin/ssh/libcrux_mlkem768_sha3.h

869

static KRML_MUSTINLINE int16_t libcrux_secrets_int_as_i16_b8(uint32_t self) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

87

((uint32_t)(src[3]) << 24);

usr.bin/ssh/libcrux_mlkem768_sha3.h

8823

uint32_t random_bits_as_u32 =

usr.bin/ssh/libcrux_mlkem768_sha3.h

8824

(((uint32_t)Eurydice_slice_index(byte_chunk, (size_t)0U, uint8_t,

usr.bin/ssh/libcrux_mlkem768_sha3.h

8826

(uint32_t)Eurydice_slice_index(byte_chunk, (size_t)1U, uint8_t,

usr.bin/ssh/libcrux_mlkem768_sha3.h

8829

(uint32_t)Eurydice_slice_index(byte_chunk, (size_t)2U, uint8_t,

usr.bin/ssh/libcrux_mlkem768_sha3.h

8832

(uint32_t)Eurydice_slice_index(byte_chunk, (size_t)3U, uint8_t,

usr.bin/ssh/libcrux_mlkem768_sha3.h

8835

uint32_t even_bits = random_bits_as_u32 & 1431655765U;

usr.bin/ssh/libcrux_mlkem768_sha3.h

8836

uint32_t odd_bits = random_bits_as_u32 >> 1U & 1431655765U;

usr.bin/ssh/libcrux_mlkem768_sha3.h

8837

uint32_t coin_toss_outcomes = even_bits + odd_bits;

usr.bin/ssh/libcrux_mlkem768_sha3.h

8838

for (uint32_t i = 0U; i < 32U / 4U; i++) {

usr.bin/ssh/libcrux_mlkem768_sha3.h

8839

uint32_t outcome_set = i;

usr.bin/ssh/libcrux_mlkem768_sha3.h

8840

uint32_t outcome_set0 = outcome_set * 4U;

usr.bin/ssh/libcrux_mlkem768_sha3.h

8842

(int16_t)(coin_toss_outcomes >> (uint32_t)outcome_set0 & 3U);

usr.bin/ssh/libcrux_mlkem768_sha3.h

8844

(int16_t)(coin_toss_outcomes >> (uint32_t)(outcome_set0 + 2U) & 3U);

usr.bin/ssh/mac.c

151

mac_compute(struct sshmac *mac, uint32_t seqno,

usr.bin/ssh/mac.c

197

mac_check(struct sshmac *mac, uint32_t seqno,

usr.bin/ssh/mac.h

47

int mac_compute(struct sshmac *, uint32_t, const u_char *, int,

usr.bin/ssh/mac.h

49

int mac_check(struct sshmac *, uint32_t, const u_char *, size_t,

usr.bin/ssh/misc.c

1631

uint32_t

usr.bin/ssh/misc.c

1635

uint32_t v;

usr.bin/ssh/misc.c

1637

v = (uint32_t)p[0] << 24;

usr.bin/ssh/misc.c

1638

v |= (uint32_t)p[1] << 16;

usr.bin/ssh/misc.c

1639

v |= (uint32_t)p[2] << 8;

usr.bin/ssh/misc.c

1640

v |= (uint32_t)p[3];

usr.bin/ssh/misc.c

1645

uint32_t

usr.bin/ssh/misc.c

1649

uint32_t v;

usr.bin/ssh/misc.c

1651

v = (uint32_t)p[0];

usr.bin/ssh/misc.c

1652

v |= (uint32_t)p[1] << 8;

usr.bin/ssh/misc.c

1653

v |= (uint32_t)p[2] << 16;

usr.bin/ssh/misc.c

1654

v |= (uint32_t)p[3] << 24;

usr.bin/ssh/misc.c

1687

put_u32(void *vp, uint32_t v)

usr.bin/ssh/misc.c

1698

put_u32_le(void *vp, uint32_t v)

usr.bin/ssh/misc.h

163

uint32_t get_u32(const void *)

usr.bin/ssh/misc.h

169

void put_u32(void *, uint32_t)

usr.bin/ssh/misc.h

175

uint32_t get_u32_le(const void *)

usr.bin/ssh/misc.h

177

void put_u32_le(void *, uint32_t)

usr.bin/ssh/moduli.c

122

static uint32_t *TinySieve, tinybits;

usr.bin/ssh/moduli.c

125

static uint32_t *SmallSieve, smallbits, smallbase;

usr.bin/ssh/moduli.c

128

static uint32_t *LargeSieve, largewords, largetries, largenumbers;

usr.bin/ssh/moduli.c

129

static uint32_t largebits, largememory; /* megabytes */

usr.bin/ssh/moduli.c

132

int gen_candidates(FILE *, uint32_t, BIGNUM *);

usr.bin/ssh/moduli.c

133

int prime_test(FILE *, FILE *, uint32_t, uint32_t, char *, unsigned long,

usr.bin/ssh/moduli.c

140

qfileout(FILE * ofile, uint32_t otype, uint32_t otests, uint32_t otries,

usr.bin/ssh/moduli.c

141

uint32_t osize, uint32_t ogenerator, BIGNUM * omodulus)

usr.bin/ssh/moduli.c

174

sieve_large(uint32_t s32)

usr.bin/ssh/moduli.c

232

gen_candidates(FILE *out, uint32_t power, BIGNUM *start)

usr.bin/ssh/moduli.c

235

uint32_t j, r, s, t;

usr.bin/ssh/moduli.c

236

uint32_t smallwords = TINY_NUMBER >> 6;

usr.bin/ssh/moduli.c

237

uint32_t tinywords = TINY_NUMBER >> 6;

usr.bin/ssh/moduli.c

239

uint32_t i;

usr.bin/ssh/moduli.c

259

TinySieve = xcalloc(tinywords, sizeof(uint32_t));

usr.bin/ssh/moduli.c

262

SmallSieve = xcalloc(smallwords, sizeof(uint32_t));

usr.bin/ssh/moduli.c

265

LargeSieve = xcalloc(largewords, sizeof(uint32_t));

usr.bin/ssh/moduli.c

400

write_checkpoint(char *cpfile, uint32_t lineno)

usr.bin/ssh/moduli.c

529

prime_test(FILE *in, FILE *out, uint32_t trials, uint32_t generator_wanted,

usr.bin/ssh/moduli.c

534

uint32_t count_in = 0, count_out = 0, count_possible = 0;

usr.bin/ssh/moduli.c

535

uint32_t generator_known, in_tests, in_tries, in_type, in_size;

usr.bin/ssh/moduli.c

650

if ((uint32_t)BN_num_bits(p) != (in_size + 1)) {

usr.bin/ssh/moduli.c

671

uint32_t r = BN_mod_word(p, 10);

usr.bin/ssh/mux.c

627

mux_confirm_remote_forward(struct ssh *ssh, int type, uint32_t seq, void *ctxt)

usr.bin/ssh/packet.c

1062

uint32_t out_blocks;

usr.bin/ssh/packet.c

1469

ssh_packet_read_seqnr(struct ssh *ssh, u_char *typep, uint32_t *seqnr_p)

usr.bin/ssh/packet.c

1561

ssh_packet_read_poll2_mux(struct ssh *ssh, u_char *typep, uint32_t *seqnr_p)

usr.bin/ssh/packet.c

1599

ssh_packet_read_poll2(struct ssh *ssh, u_char *typep, uint32_t *seqnr_p)

usr.bin/ssh/packet.c

172

uint32_t rekey_interval; /* how often in seconds */

usr.bin/ssh/packet.c

1836

ssh_packet_read_poll_seqnr(struct ssh *ssh, u_char *typep, uint32_t *seqnr_p)

usr.bin/ssh/packet.c

2323

ssh_packet_set_rekey_limits(struct ssh *ssh, uint64_t bytes, uint32_t seconds)

usr.bin/ssh/packet.c

2671

sshpkt_put_u32(struct ssh *ssh, uint32_t val)

usr.bin/ssh/packet.c

2735

sshpkt_get_u32(struct ssh *ssh, uint32_t *valp)

usr.bin/ssh/packet.c

2864

uint32_t rnd = 0;

usr.bin/ssh/packet.c

87

uint32_t seqnr;

usr.bin/ssh/packet.c

88

uint32_t packets;

usr.bin/ssh/packet.h

124

int ssh_packet_read_poll2(struct ssh *, u_char *, uint32_t *seqnr_p);

usr.bin/ssh/packet.h

127

int ssh_packet_read_seqnr(struct ssh *, u_char *, uint32_t *seqnr_p);

usr.bin/ssh/packet.h

128

int ssh_packet_read_poll_seqnr(struct ssh *, u_char *, uint32_t *seqnr_p);

usr.bin/ssh/packet.h

165

void ssh_packet_set_rekey_limits(struct ssh *, uint64_t, uint32_t);

usr.bin/ssh/packet.h

185

int sshpkt_put_u32(struct ssh *ssh, uint32_t val);

usr.bin/ssh/packet.h

196

int sshpkt_get_u32(struct ssh *ssh, uint32_t *valp);

usr.bin/ssh/packet.h

72

uint32_t compat;

usr.bin/ssh/poly1305.c

15

(((uint32_t)((p)[0])) | \

usr.bin/ssh/poly1305.c

16

((uint32_t)((p)[1]) << 8) | \

usr.bin/ssh/poly1305.c

17

((uint32_t)((p)[2]) << 16) | \

usr.bin/ssh/poly1305.c

18

((uint32_t)((p)[3]) << 24))

usr.bin/ssh/poly1305.c

30

uint32_t t0,t1,t2,t3;

usr.bin/ssh/poly1305.c

31

uint32_t h0,h1,h2,h3,h4;

usr.bin/ssh/poly1305.c

32

uint32_t r0,r1,r2,r3,r4;

usr.bin/ssh/poly1305.c

33

uint32_t s1,s2,s3,s4;

usr.bin/ssh/poly1305.c

34

uint32_t b, nb;

usr.bin/ssh/poly1305.c

38

uint32_t g0,g1,g2,g3,g4;

usr.bin/ssh/poly1305.c

92

h0 = (uint32_t)t[0] & 0x3ffffff; c = (t[0] >> 26);

usr.bin/ssh/poly1305.c

93

t[1] += c; h1 = (uint32_t)t[1] & 0x3ffffff; b = (uint32_t)(t[1] >> 26);

usr.bin/ssh/poly1305.c

94

t[2] += b; h2 = (uint32_t)t[2] & 0x3ffffff; b = (uint32_t)(t[2] >> 26);

usr.bin/ssh/poly1305.c

95

t[3] += b; h3 = (uint32_t)t[3] & 0x3ffffff; b = (uint32_t)(t[3] >> 26);

usr.bin/ssh/poly1305.c

96

t[4] += b; h4 = (uint32_t)t[4] & 0x3ffffff; b = (uint32_t)(t[4] >> 26);

usr.bin/ssh/serverloop.c

398

server_input_keep_alive(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/serverloop.c

599

server_input_channel_open(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/serverloop.c

743

server_input_global_request(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/serverloop.c

848

server_input_channel_req(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/sftp-client.c

2015

uint32_t startid, ackid;

usr.bin/ssh/sftp-client.c

2234

uint32_t saved_perm;

usr.bin/ssh/sftp-common.h

36

uint32_t flags;

usr.bin/ssh/sftp-common.h

38

uint32_t uid;

usr.bin/ssh/sftp-common.h

39

uint32_t gid;

usr.bin/ssh/sftp-common.h

40

uint32_t perm;

usr.bin/ssh/sftp-common.h

41

uint32_t atime;

usr.bin/ssh/sftp-common.h

42

uint32_t mtime;

usr.bin/ssh/sftp-server.c

100

static void process_mkdir(uint32_t id);

usr.bin/ssh/sftp-server.c

101

static void process_rmdir(uint32_t id);

usr.bin/ssh/sftp-server.c

102

static void process_realpath(uint32_t id);

usr.bin/ssh/sftp-server.c

1024

process_fsetstat(uint32_t id)

usr.bin/ssh/sftp-server.c

103

static void process_rename(uint32_t id);

usr.bin/ssh/sftp-server.c

104

static void process_readlink(uint32_t id);

usr.bin/ssh/sftp-server.c

105

static void process_symlink(uint32_t id);

usr.bin/ssh/sftp-server.c

106

static void process_extended_posix_rename(uint32_t id);

usr.bin/ssh/sftp-server.c

107

static void process_extended_statvfs(uint32_t id);

usr.bin/ssh/sftp-server.c

1077

process_opendir(uint32_t id)

usr.bin/ssh/sftp-server.c

108

static void process_extended_fstatvfs(uint32_t id);

usr.bin/ssh/sftp-server.c

109

static void process_extended_hardlink(uint32_t id);

usr.bin/ssh/sftp-server.c

110

static void process_extended_fsync(uint32_t id);

usr.bin/ssh/sftp-server.c

1107

process_readdir(uint32_t id)

usr.bin/ssh/sftp-server.c

111

static void process_extended_lsetstat(uint32_t id);

usr.bin/ssh/sftp-server.c

112

static void process_extended_limits(uint32_t id);

usr.bin/ssh/sftp-server.c

113

static void process_extended_expand(uint32_t id);

usr.bin/ssh/sftp-server.c

114

static void process_extended_copy_data(uint32_t id);

usr.bin/ssh/sftp-server.c

115

static void process_extended_home_directory(uint32_t id);

usr.bin/ssh/sftp-server.c

116

static void process_extended_get_users_groups_by_id(uint32_t id);

usr.bin/ssh/sftp-server.c

1164

process_remove(uint32_t id)

usr.bin/ssh/sftp-server.c

117

static void process_extended(uint32_t id);

usr.bin/ssh/sftp-server.c

1181

process_mkdir(uint32_t id)

usr.bin/ssh/sftp-server.c

1202

process_rmdir(uint32_t id)

usr.bin/ssh/sftp-server.c

1219

process_realpath(uint32_t id)

usr.bin/ssh/sftp-server.c

123

void (*handler)(uint32_t);

usr.bin/ssh/sftp-server.c

1246

process_rename(uint32_t id)

usr.bin/ssh/sftp-server.c

1299

process_readlink(uint32_t id)

usr.bin/ssh/sftp-server.c

1324

process_symlink(uint32_t id)

usr.bin/ssh/sftp-server.c

1344

process_extended_posix_rename(uint32_t id)

usr.bin/ssh/sftp-server.c

1363

process_extended_statvfs(uint32_t id)

usr.bin/ssh/sftp-server.c

1382

process_extended_fstatvfs(uint32_t id)

usr.bin/ssh/sftp-server.c

1402

process_extended_hardlink(uint32_t id)

usr.bin/ssh/sftp-server.c

1421

process_extended_fsync(uint32_t id)

usr.bin/ssh/sftp-server.c

1439

process_extended_lsetstat(uint32_t id)

usr.bin/ssh/sftp-server.c

1488

process_extended_limits(uint32_t id)

usr.bin/ssh/sftp-server.c

1518

process_extended_expand(uint32_t id)

usr.bin/ssh/sftp-server.c

1577

process_extended_copy_data(uint32_t id)

usr.bin/ssh/sftp-server.c

1665

process_extended_home_directory(uint32_t id)

usr.bin/ssh/sftp-server.c

1692

process_extended_get_users_groups_by_id(uint32_t id)

usr.bin/ssh/sftp-server.c

1747

process_extended(uint32_t id)

usr.bin/ssh/sftp-server.c

1778

uint32_t id;

usr.bin/ssh/sftp-server.c

521

status_to_message(uint32_t status)

usr.bin/ssh/sftp-server.c

539

send_status_errmsg(uint32_t id, uint32_t status, const char *errmsg)

usr.bin/ssh/sftp-server.c

565

send_status(uint32_t id, uint32_t status)

usr.bin/ssh/sftp-server.c

571

send_data_or_handle(char type, uint32_t id, const u_char *data, int dlen)

usr.bin/ssh/sftp-server.c

587

send_data(uint32_t id, const u_char *data, int dlen)

usr.bin/ssh/sftp-server.c

594

send_handle(uint32_t id, int handle)

usr.bin/ssh/sftp-server.c

606

send_names(uint32_t id, int count, const Stat *stats)

usr.bin/ssh/sftp-server.c

629

send_attrib(uint32_t id, const Attrib *a)

usr.bin/ssh/sftp-server.c

646

send_statvfs(uint32_t id, struct statvfs *st)

usr.bin/ssh/sftp-server.c

732

process_open(uint32_t id)

usr.bin/ssh/sftp-server.c

734

uint32_t pflags;

usr.bin/ssh/sftp-server.c

774

process_close(uint32_t id)

usr.bin/ssh/sftp-server.c

789

process_read(uint32_t id)

usr.bin/ssh/sftp-server.c

793

uint32_t len;

usr.bin/ssh/sftp-server.c

844

process_write(uint32_t id)

usr.bin/ssh/sftp-server.c

88

static void process_open(uint32_t id);

usr.bin/ssh/sftp-server.c

889

process_do_stat(uint32_t id, int do_lstat)

usr.bin/ssh/sftp-server.c

89

static void process_close(uint32_t id);

usr.bin/ssh/sftp-server.c

90

static void process_read(uint32_t id);

usr.bin/ssh/sftp-server.c

91

static void process_write(uint32_t id);

usr.bin/ssh/sftp-server.c

915

process_stat(uint32_t id)

usr.bin/ssh/sftp-server.c

92

static void process_stat(uint32_t id);

usr.bin/ssh/sftp-server.c

921

process_lstat(uint32_t id)

usr.bin/ssh/sftp-server.c

927

process_fstat(uint32_t id)

usr.bin/ssh/sftp-server.c

93

static void process_lstat(uint32_t id);

usr.bin/ssh/sftp-server.c

94

static void process_fstat(uint32_t id);

usr.bin/ssh/sftp-server.c

95

static void process_setstat(uint32_t id);

usr.bin/ssh/sftp-server.c

96

static void process_fsetstat(uint32_t id);

usr.bin/ssh/sftp-server.c

97

static void process_opendir(uint32_t id);

usr.bin/ssh/sftp-server.c

977

process_setstat(uint32_t id)

usr.bin/ssh/sftp-server.c

98

static void process_readdir(uint32_t id);

usr.bin/ssh/sftp-server.c

99

static void process_remove(uint32_t id);

usr.bin/ssh/sk-api.h

57

uint32_t counter;

usr.bin/ssh/sk-api.h

65

uint32_t alg;

usr.bin/ssh/sk-api.h

84

uint32_t sk_api_version(void);

usr.bin/ssh/sk-api.h

87

int sk_enroll(uint32_t alg, const uint8_t *challenge, size_t challenge_len,

usr.bin/ssh/sk-api.h

92

int sk_sign(uint32_t alg, const uint8_t *data, size_t data_len,

usr.bin/ssh/sk-usbhid.c

1015

sk_sign(uint32_t alg, const uint8_t *data, size_t datalen,

usr.bin/ssh/sk-usbhid.c

124

uint32_t

usr.bin/ssh/sk-usbhid.c

580

pack_public_key(uint32_t alg, const fido_cred_t *cred,

usr.bin/ssh/sk-usbhid.c

706

sk_enroll(uint32_t alg, const uint8_t *challenge, size_t challenge_len,

usr.bin/ssh/sk-usbhid.c

78

uint32_t sk_api_version(void);

usr.bin/ssh/sk-usbhid.c

81

int sk_enroll(uint32_t alg, const uint8_t *challenge, size_t challenge_len,

usr.bin/ssh/sk-usbhid.c

86

int sk_sign(uint32_t alg, const uint8_t *data, size_t data_len,

usr.bin/ssh/sk-usbhid.c

972

pack_sig(uint32_t alg, fido_assert_t *assert,

usr.bin/ssh/sntrup761.c

1719

static void uint32_divmod_uint14(uint32_t *Q, uint16_t *r, uint32_t x, uint16_t m) {

usr.bin/ssh/sntrup761.c

1720

uint32_t qpart, mask, v = 0x80000000 / m;

usr.bin/ssh/sntrup761.c

1730

x += mask & (uint32_t)m;

usr.bin/ssh/sntrup761.c

1735

static uint16_t uint32_mod_uint14(uint32_t x, uint16_t m) {

usr.bin/ssh/sntrup761.c

1736

uint32_t Q;

usr.bin/ssh/sntrup761.c

1755

uint32_t m0 = M[i];

usr.bin/ssh/sntrup761.c

1756

uint32_t r = R[i] + R[i + 1] * m0;

usr.bin/ssh/sntrup761.c

1757

uint32_t m = M[i + 1] * m0;

usr.bin/ssh/sntrup761.c

1785

uint32_t bottomt[len / 2];

usr.bin/ssh/sntrup761.c

1788

uint32_t m = M[i] * (uint32_t)M[i + 1];

usr.bin/ssh/sntrup761.c

1808

uint32_t r1, r = bottomr[i / 2];

usr.bin/ssh/sntrup761.c

1941

static void Short_fromlist(small *out, const uint32_t *in) {

usr.bin/ssh/sntrup761.c

1942

uint32_t L[p];

usr.bin/ssh/sntrup761.c

1944

for (i = 0; i < w; ++i) L[i] = in[i] & (uint32_t)-2;

usr.bin/ssh/sntrup761.c

1945

for (i = w; i < p; ++i) L[i] = (in[i] & (uint32_t)-3) | 1;

usr.bin/ssh/sntrup761.c

1961

uint32_t L[p];

usr.bin/ssh/sntrup761.c

1968

uint32_t L[p];

usr.bin/ssh/sntrup761.c

559

#define crypto_int32_unsigned uint32_t

usr.bin/ssh/ssh-keygen.c

1001

uint32_t bits = 0;

usr.bin/ssh/ssh-keygen.c

122

static uint32_t certflags_flags = CERTOPT_DEFAULT;

usr.bin/ssh/ssh-keygen.c

166

int gen_candidates(FILE *, uint32_t, BIGNUM *);

usr.bin/ssh/ssh-keygen.c

167

int prime_test(FILE *, FILE *, uint32_t, uint32_t, char *, unsigned long,

usr.bin/ssh/ssh-keygen.c

172

type_bits_valid(int type, const char *name, uint32_t *bitsp)

usr.bin/ssh/ssh-keygen.c

2946

uint32_t generator_wanted = 0;

usr.bin/ssh/ssh-keygen.c

2963

generator_wanted = (uint32_t)strtonum(p, 1, UINT_MAX,

usr.bin/ssh/ssh-keygen.c

3288

uint32_t bits = 0;

usr.bin/ssh/ssh-keygen.c

3323

bits = (uint32_t)strtonum(optarg, 1, UINT32_MAX,

usr.bin/ssh/ssh-pkcs11.c

1631

char *label, CK_ULONG bits, CK_BYTE keyid, uint32_t *err)

usr.bin/ssh/ssh-pkcs11.c

1749

char *label, CK_ULONG bits, CK_BYTE keyid, uint32_t *err)

usr.bin/ssh/ssh-pkcs11.c

2079

unsigned int type, unsigned int bits, unsigned char keyid, uint32_t *err)

usr.bin/ssh/ssh-pkcs11.c

2145

unsigned char keyid, uint32_t *err)

usr.bin/ssh/ssh-pkcs11.h

41

unsigned int, unsigned char, uint32_t *);

usr.bin/ssh/ssh-pkcs11.h

44

uint32_t *);

usr.bin/ssh/ssh-sk-helper.c

110

uint32_t compat;

usr.bin/ssh/ssh-sk.c

48

uint32_t (*sk_api_version)(void);

usr.bin/ssh/ssh-sk.c

96

uint32_t version;

usr.bin/ssh/ssh.c

1902

ssh_confirm_remote_forward(struct ssh *ssh, int type, uint32_t seq, void *ctxt)

usr.bin/ssh/ssh_api.c

249

uint32_t seqnr;

usr.bin/ssh/sshbuf-getput-basic.c

138

sshbuf_peek_u32(const struct sshbuf *buf, size_t offset, uint32_t *valp)

usr.bin/ssh/sshbuf-getput-basic.c

239

uint32_t len;

usr.bin/ssh/sshbuf-getput-basic.c

304

uint32_t len;

usr.bin/ssh/sshbuf-getput-basic.c

400

sshbuf_put_u32(struct sshbuf *buf, uint32_t val)

usr.bin/ssh/sshbuf-getput-basic.c

462

sshbuf_poke_u32(struct sshbuf *buf, size_t offset, uint32_t val)

usr.bin/ssh/sshbuf-getput-basic.c

57

sshbuf_get_u32(struct sshbuf *buf, uint32_t *valp)

usr.bin/ssh/sshbuf.h

183

int sshbuf_get_u32(struct sshbuf *buf, uint32_t *valp);

usr.bin/ssh/sshbuf.h

187

int sshbuf_put_u32(struct sshbuf *buf, uint32_t val);

usr.bin/ssh/sshbuf.h

195

uint32_t *valp);

usr.bin/ssh/sshbuf.h

206

int sshbuf_poke_u32(struct sshbuf *buf, size_t offset, uint32_t val);

usr.bin/ssh/sshbuf.h

351

(((uint32_t)(((const u_char *)(p))[0]) << 24) | \

usr.bin/ssh/sshbuf.h

352

((uint32_t)(((const u_char *)(p))[1]) << 16) | \

usr.bin/ssh/sshbuf.h

353

((uint32_t)(((const u_char *)(p))[2]) << 8) | \

usr.bin/ssh/sshbuf.h

354

(uint32_t)(((const u_char *)(p))[3]))

usr.bin/ssh/sshbuf.h

373

const uint32_t __v = (v); \

usr.bin/ssh/sshconnect2.c

1068

input_userauth_passwd_changereq(int type, uint32_t seqnr, struct ssh *ssh)

usr.bin/ssh/sshconnect2.c

1941

input_userauth_info_req(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/sshconnect2.c

343

static int input_userauth_service_accept(int, uint32_t, struct ssh *);

usr.bin/ssh/sshconnect2.c

344

static int input_userauth_success(int, uint32_t, struct ssh *);

usr.bin/ssh/sshconnect2.c

345

static int input_userauth_failure(int, uint32_t, struct ssh *);

usr.bin/ssh/sshconnect2.c

346

static int input_userauth_banner(int, uint32_t, struct ssh *);

usr.bin/ssh/sshconnect2.c

347

static int input_userauth_error(int, uint32_t, struct ssh *);

usr.bin/ssh/sshconnect2.c

348

static int input_userauth_info_req(int, uint32_t, struct ssh *);

usr.bin/ssh/sshconnect2.c

349

static int input_userauth_pk_ok(int, uint32_t, struct ssh *);

usr.bin/ssh/sshconnect2.c

350

static int input_userauth_passwd_changereq(int, uint32_t, struct ssh *);

usr.bin/ssh/sshconnect2.c

361

static int input_gssapi_response(int type, uint32_t, struct ssh *);

usr.bin/ssh/sshconnect2.c

362

static int input_gssapi_token(int type, uint32_t, struct ssh *);

usr.bin/ssh/sshconnect2.c

363

static int input_gssapi_error(int, uint32_t, struct ssh *);

usr.bin/ssh/sshconnect2.c

364

static int input_gssapi_errtok(int, uint32_t, struct ssh *);

usr.bin/ssh/sshconnect2.c

484

input_userauth_service_accept(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/sshconnect2.c

555

input_userauth_error(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/sshconnect2.c

562

input_userauth_banner(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/sshconnect2.c

581

input_userauth_success(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/sshconnect2.c

600

input_userauth_success_unexpected(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/sshconnect2.c

614

input_userauth_failure(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/sshconnect2.c

674

input_userauth_pk_ok(int type, uint32_t seq, struct ssh *ssh)

usr.bin/ssh/sshconnect2.c

881

input_gssapi_response(int type, uint32_t plen, struct ssh *ssh)

usr.bin/ssh/sshconnect2.c

925

input_gssapi_token(int type, uint32_t plen, struct ssh *ssh)

usr.bin/ssh/sshconnect2.c

957

input_gssapi_errtok(int type, uint32_t plen, struct ssh *ssh)

usr.bin/ssh/sshconnect2.c

991

input_gssapi_error(int type, uint32_t plen, struct ssh *ssh)

usr.bin/ssh/sshkey.h

140

uint32_t sk_counter; /* U2F signature counter */

usr.bin/ssh/sshsig.c

243

uint32_t sversion;

usr.bin/ssh/umac.c

87

typedef uint32_t UINT32; /* 4 byte */

usr.bin/systat/pftop.c

1682

uint32_t n, count, start;

usr.bin/tcpbench/tcpbench.c

1351

uint32_t protocols = 0;

usr.bin/top/top.c

218

uint32_t *rtableidp;

usr.bin/top/top.c

219

uint32_t rtableid;

usr.bin/usbhidctl/usbhid.c

764

uint32_t repsize;

usr.sbin/bgpctl/bgpctl.c

1037

fmt_large_community(uint32_t d1, uint32_t d2, uint32_t d3)

usr.sbin/bgpctl/bgpctl.c

1050

uint32_t as4, u32;

usr.sbin/bgpctl/bgpctl.c

1424

uint32_t as;

usr.sbin/bgpctl/bgpctl.c

1543

uint32_t bgpid;

usr.sbin/bgpctl/bgpctl.c

1645

uint32_t pathid;

usr.sbin/bgpctl/bgpctl.c

1826

uint32_t as = 0;

usr.sbin/bgpctl/bgpctl.c

1848

seg_size = 2 + sizeof(uint32_t) * seg_len;

usr.sbin/bgpctl/bgpctl.c

746

fmt_flags(uint32_t flags, int sum)

usr.sbin/bgpctl/bgpctl.h

50

const char *fmt_flags(uint32_t, int);

usr.sbin/bgpctl/bgpctl.h

58

const char *fmt_large_community(uint32_t, uint32_t, uint32_t);

usr.sbin/bgpctl/mrtparser.c

269

uint32_t bid;

usr.sbin/bgpctl/mrtparser.c

414

uint32_t otm;

usr.sbin/bgpctl/mrtparser.c

457

uint32_t tmp32;

usr.sbin/bgpctl/mrtparser.c

536

uint32_t tmp32;

usr.sbin/bgpctl/mrtparser.c

562

if (ibuf_skip(msg, sizeof(uint32_t)) == -1)

usr.sbin/bgpctl/mrtparser.c

901

uint32_t sas, das, usec;

usr.sbin/bgpctl/mrtparser.c

963

uint32_t sas, das, usec;

usr.sbin/bgpctl/mrtparser.h

23

uint32_t bgp_id;

usr.sbin/bgpctl/mrtparser.h

24

uint32_t asnum;

usr.sbin/bgpctl/mrtparser.h

30

uint32_t bgp_id;

usr.sbin/bgpctl/mrtparser.h

44

uint32_t local_pref;

usr.sbin/bgpctl/mrtparser.h

45

uint32_t med;

usr.sbin/bgpctl/mrtparser.h

46

uint32_t path_id;

usr.sbin/bgpctl/mrtparser.h

56

uint32_t seqnum;

usr.sbin/bgpctl/mrtparser.h

67

uint32_t src_as;

usr.sbin/bgpctl/mrtparser.h

68

uint32_t dst_as;

usr.sbin/bgpctl/mrtparser.h

77

uint32_t src_as;

usr.sbin/bgpctl/mrtparser.h

78

uint32_t dst_as;

usr.sbin/bgpctl/output.c

738

uint32_t a, l1, l2;

usr.sbin/bgpctl/output.c

779

uint32_t as, pathid, val;

usr.sbin/bgpctl/output_json.c

553

uint32_t a, l1, l2;

usr.sbin/bgpctl/output_json.c

594

uint32_t as, pathid, val;

usr.sbin/bgpctl/parser.c

1053

parse_asnum(const char *word, size_t wordlen, uint32_t *asnum)

usr.sbin/bgpctl/parser.c

1057

uint32_t uval, uvalh = 0;

usr.sbin/bgpctl/parser.c

1152

getcommunity(char *s, int large, uint32_t *val, uint32_t *flag)

usr.sbin/bgpctl/parser.c

1177

setcommunity(struct community *c, uint32_t as, uint32_t data,

usr.sbin/bgpctl/parser.c

1178

uint32_t asflag, uint32_t dataflag)

usr.sbin/bgpctl/parser.c

1192

uint32_t as, data, asflag, dataflag;

usr.sbin/bgpctl/parser.c

1234

uint32_t dflag1, dflag2, dflag3;

usr.sbin/bgpctl/parser.c

1275

parseextvalue(int type, char *s, uint32_t *v, uint32_t *flag)

usr.sbin/bgpctl/parser.c

1280

uint32_t uvalh, uval;

usr.sbin/bgpctl/parser.c

1349

uint32_t uval, uval2, dflag1 = 0, dflag2 = 0;

usr.sbin/bgpctl/parser.c

1509

uint32_t u32;

usr.sbin/bgpctl/parser.c

475

int parse_asnum(const char *, size_t, uint32_t *);

usr.sbin/bgpctl/parser.h

81

uint32_t pathid;

usr.sbin/bgpd/bgpd.c

1055

uint32_t rtrid = imsg_get_id(&imsg);

usr.sbin/bgpd/bgpd.c

1070

uint32_t rtrid = imsg_get_id(&imsg);

usr.sbin/bgpd/bgpd.c

1495

bgpd_rtr_conn_teardown(uint32_t id)

usr.sbin/bgpd/bgpd.c

57

void bgpd_rtr_conn_teardown(uint32_t);

usr.sbin/bgpd/bgpd.c

747

uint32_t *as;

usr.sbin/bgpd/bgpd.c

75

uint32_t id;

usr.sbin/bgpd/bgpd.h

1034

uint32_t flags;

usr.sbin/bgpd/bgpd.h

1035

uint32_t data1;

usr.sbin/bgpd/bgpd.h

1036

uint32_t data2;

usr.sbin/bgpd/bgpd.h

1037

uint32_t data3;

usr.sbin/bgpd/bgpd.h

1046

uint32_t flags;

usr.sbin/bgpd/bgpd.h

1047

uint32_t path_id;

usr.sbin/bgpd/bgpd.h

1091

uint32_t peerid;

usr.sbin/bgpd/bgpd.h

1092

uint32_t groupid;

usr.sbin/bgpd/bgpd.h

1093

uint32_t remote_as;

usr.sbin/bgpd/bgpd.h

1313

uint32_t metric;

usr.sbin/bgpd/bgpd.h

1323

uint32_t as; /* must be first */

usr.sbin/bgpd/bgpd.h

1324

uint32_t maxlen; /* change type for better struct layout */

usr.sbin/bgpd/bgpd.h

1350

uint32_t as;

usr.sbin/bgpd/bgpd.h

1351

uint32_t num;

usr.sbin/bgpd/bgpd.h

1352

uint32_t *tas;

usr.sbin/bgpd/bgpd.h

1358

uint32_t entries;

usr.sbin/bgpd/bgpd.h

1477

uint32_t peer_id;

usr.sbin/bgpd/bgpd.h

1478

uint32_t group_id;

usr.sbin/bgpd/bgpd.h

1527

uint32_t get_bgpid(void);

usr.sbin/bgpd/bgpd.h

1552

int kr_nexthop_add(uint32_t, struct bgpd_addr *);

usr.sbin/bgpd/bgpd.h

1553

void kr_nexthop_delete(uint32_t, struct bgpd_addr *);

usr.sbin/bgpd/bgpd.h

1613

int bitmap_set(struct bitmap *, uint32_t);

usr.sbin/bgpd/bgpd.h

1614

int bitmap_test(struct bitmap *, uint32_t);

usr.sbin/bgpd/bgpd.h

1615

void bitmap_clear(struct bitmap *, uint32_t);

usr.sbin/bgpd/bgpd.h

1618

int bitmap_id_get(struct bitmap *, uint32_t *);

usr.sbin/bgpd/bgpd.h

1619

void bitmap_id_put(struct bitmap *, uint32_t);

usr.sbin/bgpd/bgpd.h

1632

int as_set_match(const struct as_set *, uint32_t);

usr.sbin/bgpd/bgpd.h

1639

void *set_match(const struct set_table *, uint32_t);

usr.sbin/bgpd/bgpd.h

1651

uint32_t);

usr.sbin/bgpd/bgpd.h

1661

const char *log_as(uint32_t);

usr.sbin/bgpd/bgpd.h

1672

uint32_t aspath_extract(const void *, int);

usr.sbin/bgpd/bgpd.h

218

uint32_t ethtag;

usr.sbin/bgpd/bgpd.h

233

uint32_t scope_id; /* iface scope id for v6 */

usr.sbin/bgpd/bgpd.h

304

uint32_t asnum;

usr.sbin/bgpd/bgpd.h

347

uint32_t bgpid;

usr.sbin/bgpd/bgpd.h

348

uint32_t clusterid;

usr.sbin/bgpd/bgpd.h

349

uint32_t as;

usr.sbin/bgpd/bgpd.h

423

uint32_t spi_in;

usr.sbin/bgpd/bgpd.h

424

uint32_t spi_out;

usr.sbin/bgpd/bgpd.h

504

uint32_t id;

usr.sbin/bgpd/bgpd.h

505

uint32_t groupid;

usr.sbin/bgpd/bgpd.h

506

uint32_t remote_as;

usr.sbin/bgpd/bgpd.h

507

uint32_t local_as;

usr.sbin/bgpd/bgpd.h

508

uint32_t max_prefix;

usr.sbin/bgpd/bgpd.h

509

uint32_t max_out_prefix;

usr.sbin/bgpd/bgpd.h

554

uint32_t prefix_cnt;

usr.sbin/bgpd/bgpd.h

555

uint32_t prefix_out_cnt;

usr.sbin/bgpd/bgpd.h

556

uint32_t pending_update;

usr.sbin/bgpd/bgpd.h

557

uint32_t pending_withdraw;

usr.sbin/bgpd/bgpd.h

623

uint32_t id;

usr.sbin/bgpd/bgpd.h

640

uint32_t serial;

usr.sbin/bgpd/bgpd.h

641

uint32_t refresh;

usr.sbin/bgpd/bgpd.h

642

uint32_t retry;

usr.sbin/bgpd/bgpd.h

643

uint32_t expire;

usr.sbin/bgpd/bgpd.h

849

uint32_t mplslabel;

usr.sbin/bgpd/bgpd.h

875

uint32_t remote_bgpid;

usr.sbin/bgpd/bgpd.h

954

uint32_t remote_id;

usr.sbin/bgpd/bgpd.h

955

uint32_t path_id;

usr.sbin/bgpd/bgpd.h

956

uint32_t local_pref;

usr.sbin/bgpd/bgpd.h

957

uint32_t med;

usr.sbin/bgpd/bgpd.h

958

uint32_t weight;

usr.sbin/bgpd/bgpd.h

959

uint32_t flags;

usr.sbin/bgpd/bgpd.h

990

uint32_t as_min;

usr.sbin/bgpd/bgpd.h

991

uint32_t as_max;

usr.sbin/bgpd/bgpd_imsg.c

116

uint32_t type;

usr.sbin/bgpd/bitmap.c

102

uint32_t max, elm;

usr.sbin/bgpd/bitmap.c

128

bitmap_test(struct bitmap *map, uint32_t bid)

usr.sbin/bgpd/bitmap.c

131

uint32_t max, elm;

usr.sbin/bgpd/bitmap.c

148

bitmap_clear(struct bitmap *map, uint32_t bid)

usr.sbin/bgpd/bitmap.c

151

uint32_t max, elm;

usr.sbin/bgpd/bitmap.c

172

uint32_t elm, max, end;

usr.sbin/bgpd/bitmap.c

191

bitmap_id_get(struct bitmap *map, uint32_t *bid)

usr.sbin/bgpd/bitmap.c

194

uint32_t elm, max, end;

usr.sbin/bgpd/bitmap.c

223

bitmap_id_put(struct bitmap *map, uint32_t bid)

usr.sbin/bgpd/bitmap.c

36

bitmap_getset(struct bitmap *map, uint64_t **ptr, uint32_t *max)

usr.sbin/bgpd/bitmap.c

51

uint32_t max;

usr.sbin/bgpd/bitmap.c

62

bitmap_resize(struct bitmap *map, uint32_t bid)

usr.sbin/bgpd/bitmap.c

65

uint32_t elm, size, oldmax, newmax;

usr.sbin/bgpd/bitmap.c

99

bitmap_set(struct bitmap *map, uint32_t bid)

usr.sbin/bgpd/chash.c

180

uint32_t max = CH_H2_SIZE * 7;

usr.sbin/bgpd/chash.c

181

uint32_t used = m->cs_num_elm + m->cs_num_tomb;

usr.sbin/bgpd/chash.c

190

uint32_t max = CH_H2_SIZE * 7;

usr.sbin/bgpd/chash.c

191

uint32_t used = m->cs_num_elm;

usr.sbin/bgpd/chash.c

205

uint32_t bucket = CH_H2(h);

usr.sbin/bgpd/chash.c

261

uint32_t bucket = CH_H2(h);

usr.sbin/bgpd/chash.c

299

uint32_t bucket = CH_H2(h);

usr.sbin/bgpd/chash.c

329

uint32_t bucket = CH_H2(h);

usr.sbin/bgpd/chash.c

359

uint32_t n;

usr.sbin/bgpd/chash.c

384

uint32_t n;

usr.sbin/bgpd/chash.c

414

uint32_t n;

usr.sbin/bgpd/chash.c

482

uint32_t n;

usr.sbin/bgpd/chash.c

595

ch_table_buddy(struct ch_table *t, uint64_t idx, uint32_t local_level,

usr.sbin/bgpd/chash.c

77

uint32_t cs_num_elm;

usr.sbin/bgpd/chash.c

78

uint32_t cs_num_tomb;

usr.sbin/bgpd/chash.c

79

uint32_t cs_num_ever_full;

usr.sbin/bgpd/chash.c

80

uint32_t cs_local_level;

usr.sbin/bgpd/chash.h

57

uint32_t ch_level;

usr.sbin/bgpd/chash.h

69

uint32_t ci_set_idx;

usr.sbin/bgpd/chash.h

70

uint32_t ci_grp_idx;

usr.sbin/bgpd/config.c

496

uint32_t

usr.sbin/bgpd/config.c

500

uint32_t ip = 0, cur, localnet;

usr.sbin/bgpd/control.c

249

uint32_t type;

usr.sbin/bgpd/control.c

548

uint32_t type;

usr.sbin/bgpd/kroute.c

1239

uint32_t a;

usr.sbin/bgpd/kroute.c

1642

uint32_t mplslabel = 0;

usr.sbin/bgpd/kroute.c

53

uint32_t rtseq;

usr.sbin/bgpd/kroute.c

572

uint32_t mplslabel = 0;

usr.sbin/bgpd/kroute.c

629

uint32_t mplslabel = 0;

usr.sbin/bgpd/kroute.c

64

uint32_t mplslabel;

usr.sbin/bgpd/kroute.c

77

uint32_t prefix_scope_id; /* because ... */

usr.sbin/bgpd/kroute.c

78

uint32_t nexthop_scope_id;

usr.sbin/bgpd/kroute.c

79

uint32_t mplslabel;

usr.sbin/bgpd/kroute.c

900

uint32_t tableid;

usr.sbin/bgpd/mrt.c

1053

uint32_t len)

usr.sbin/bgpd/mrt.c

224

uint32_t tmp;

usr.sbin/bgpd/mrt.c

43

static int mrt_dump_entry_v2(struct mrt *, struct rib_entry *, uint32_t);

usr.sbin/bgpd/mrt.c

46

uint16_t, uint32_t, int);

usr.sbin/bgpd/mrt.c

48

uint32_t);

usr.sbin/bgpd/mrt.c

683

mrt_dump_entry_v2(struct mrt *mrt, struct rib_entry *re, uint32_t snum)

usr.sbin/bgpd/mrt.c

938

uint16_t subtype, uint32_t len, int swap)

usr.sbin/bgpd/mrt.h

45

uint32_t timestamp;

usr.sbin/bgpd/mrt.h

48

uint32_t length;

usr.sbin/bgpd/parse.y

131

uint32_t as;

usr.sbin/bgpd/parse.y

132

uint32_t num;

usr.sbin/bgpd/parse.y

167

static void add_as_set(uint32_t);

usr.sbin/bgpd/parse.y

170

static void add_roa_set(struct prefixset_item *, uint32_t, uint8_t,

usr.sbin/bgpd/parse.y

174

static int merge_aspa_set(uint32_t, struct aspa_tas_l *, time_t);

usr.sbin/bgpd/parse.y

335

uint32_t uvalh = 0, uval;

usr.sbin/bgpd/parse.y

367

(uint32_t)$1);

usr.sbin/bgpd/parse.y

377

uint32_t uvalh = 0, uval;

usr.sbin/bgpd/parse.y

4338

getcommunity(char *s, int large, uint32_t *val, uint32_t *flag)

usr.sbin/bgpd/parse.y

4366

setcommunity(struct community *c, uint32_t as, uint32_t data,

usr.sbin/bgpd/parse.y

4367

uint32_t asflag, uint32_t dataflag)

usr.sbin/bgpd/parse.y

4381

uint32_t dflag1, dflag2, dflag3;

usr.sbin/bgpd/parse.y

4410

uint32_t as, data, asflag, dataflag;

usr.sbin/bgpd/parse.y

4476

parseextvalue(int type, char *s, uint32_t *v, uint32_t *flag)

usr.sbin/bgpd/parse.y

4481

uint32_t uvalh, uval;

usr.sbin/bgpd/parse.y

4560

uint32_t uval, uval2, dflag1 = 0, dflag2 = 0;

usr.sbin/bgpd/parse.y

4867

static uint32_t id = PEER_ID_STATIC_MIN;

usr.sbin/bgpd/parse.y

5378

aset = as_sets_new(&conf->as_sets, name, 0, sizeof(uint32_t));

usr.sbin/bgpd/parse.y

5387

add_as_set(uint32_t as)

usr.sbin/bgpd/parse.y

5433

add_roa_set(struct prefixset_item *npsi, uint32_t as, uint8_t max,

usr.sbin/bgpd/parse.y

5486

static uint32_t id;

usr.sbin/bgpd/parse.y

5521

merge_aspa_set(uint32_t as, struct aspa_tas_l *tas, time_t expires)

usr.sbin/bgpd/parse.y

5524

uint32_t i, num, *newtas;

usr.sbin/bgpd/parse.y

5542

newtas = recallocarray(aspa->tas, aspa->num, num, sizeof(uint32_t));

usr.sbin/bgpd/parse.y

5852

uint32_t u32;

usr.sbin/bgpd/pfkey.c

439

pfkey_reply(int sd, uint32_t *spi)

usr.sbin/bgpd/pfkey.c

44

static uint32_t sadb_msg_seq = 0;

usr.sbin/bgpd/pfkey.c

45

static uint32_t pid = 0; /* should pid_t but pfkey needs uint32_t */

usr.sbin/bgpd/pfkey.c

48

static int pfkey_reply(int, uint32_t *);

usr.sbin/bgpd/pfkey.c

505

uint8_t keylen, char *key, uint32_t *spi)

usr.sbin/bgpd/pfkey.c

51

uint32_t, uint8_t, int, char *, uint8_t, int, char *,

usr.sbin/bgpd/pfkey.c

522

uint32_t *spi)

usr.sbin/bgpd/pfkey.c

537

uint32_t spi_out = 0;

usr.sbin/bgpd/pfkey.c

538

uint32_t spi_in = 0;

usr.sbin/bgpd/pfkey.c

60

const struct bgpd_addr *src, const struct bgpd_addr *dst, uint32_t spi,

usr.sbin/bgpd/pfkey.c

817

pfkey_send_conf(struct imsgbuf *imsgbuf, uint32_t id, struct auth_config *auth)

usr.sbin/bgpd/printconf.c

1188

print_mrt(struct bgpd_config *conf, uint32_t pid, uint32_t gid,

usr.sbin/bgpd/printconf.c

1225

uint32_t prev_groupid;

usr.sbin/bgpd/printconf.c

58

void print_mrt(struct bgpd_config *, uint32_t, uint32_t,

usr.sbin/bgpd/printconf.c

624

uint32_t *as;

usr.sbin/bgpd/rde.c

111

static int ovs_match(uint8_t, uint32_t);

usr.sbin/bgpd/rde.c

112

static int avs_match(uint8_t, uint32_t);

usr.sbin/bgpd/rde.c

1233

sizeof(uint32_t));

usr.sbin/bgpd/rde.c

1238

ibuf_size(&ibuf) % sizeof(uint32_t) != 0)

usr.sbin/bgpd/rde.c

1240

nmemb = ibuf_size(&ibuf) / sizeof(uint32_t);

usr.sbin/bgpd/rde.c

135

uint32_t peerid;

usr.sbin/bgpd/rde.c

1381

sizeof(uint32_t));

usr.sbin/bgpd/rde.c

1385

aspa->num * sizeof(uint32_t)) == -1)

usr.sbin/bgpd/rde.c

1492

uint32_t fas, pathid;

usr.sbin/bgpd/rde.c

1731

uint32_t tmp;

usr.sbin/bgpd/rde.c

1798

uint32_t tmp;

usr.sbin/bgpd/rde.c

1930

pathid_conflict(struct rib_entry *re, uint32_t pathid)

usr.sbin/bgpd/rde.c

1946

static uint32_t

usr.sbin/bgpd/rde.c

1947

pathid_assign(struct rde_peer *peer, uint32_t path_id,

usr.sbin/bgpd/rde.c

1951

uint32_t path_id_tx;

usr.sbin/bgpd/rde.c

1979

rde_update_update(struct rde_peer *peer, uint32_t path_id,

usr.sbin/bgpd/rde.c

1984

uint32_t path_id_tx;

usr.sbin/bgpd/rde.c

2046

rde_update_withdraw(struct rde_peer *peer, uint32_t path_id,

usr.sbin/bgpd/rde.c

2084

uint32_t tmp32, zero = 0;

usr.sbin/bgpd/rde.c

2258

if (memcmp(t, &zero, sizeof(uint32_t)) == 0) {

usr.sbin/bgpd/rde.c

2752

uint32_t as;

usr.sbin/bgpd/rde.c

2830

uint32_t fas;

usr.sbin/bgpd/rde.c

2857

uint32_t id;

usr.sbin/bgpd/rde.c

4527

uint32_t

usr.sbin/bgpd/rde.c

4643

uint32_t path_id_tx;

usr.sbin/bgpd/rde.c

468

uint32_t peerid;

usr.sbin/bgpd/rde.c

4733

uint32_t i;

usr.sbin/bgpd/rde.c

4826

uint32_t i;

usr.sbin/bgpd/rde.c

4860

uint32_t path_id_tx;

usr.sbin/bgpd/rde.c

5012

uint8_t plen, uint32_t as)

usr.sbin/bgpd/rde.c

5021

ovs_match(uint8_t roa_vstate, uint32_t flag)

usr.sbin/bgpd/rde.c

5046

avs_match(uint8_t aspa_vstate, uint32_t flag)

usr.sbin/bgpd/rde.c

53

int rde_update_update(struct rde_peer *, uint32_t,

usr.sbin/bgpd/rde.c

55

void rde_update_withdraw(struct rde_peer *, uint32_t,

usr.sbin/bgpd/rde.c

93

struct bgpd_addr *, uint8_t, uint32_t);

usr.sbin/bgpd/rde.h

105

uint32_t adjout_bid;

usr.sbin/bgpd/rde.h

106

uint32_t remote_bgpid;

usr.sbin/bgpd/rde.h

107

uint32_t path_id_tx;

usr.sbin/bgpd/rde.h

136

uint32_t source_as; /* cached source_as */

usr.sbin/bgpd/rde.h

229

uint32_t flags; /* internally used */

usr.sbin/bgpd/rde.h

230

uint32_t med; /* multi exit disc */

usr.sbin/bgpd/rde.h

231

uint32_t lpref; /* local pref */

usr.sbin/bgpd/rde.h

232

uint32_t weight; /* low prio lpref */

usr.sbin/bgpd/rde.h

263

uint32_t costs;

usr.sbin/bgpd/rde.h

279

uint32_t adjoutlen;

usr.sbin/bgpd/rde.h

280

uint32_t adjoutavail;

usr.sbin/bgpd/rde.h

284

uint32_t refcnt;

usr.sbin/bgpd/rde.h

298

uint32_t path_id;

usr.sbin/bgpd/rde.h

299

uint32_t path_id_tx;

usr.sbin/bgpd/rde.h

333

uint32_t path_id_tx;

usr.sbin/bgpd/rde.h

349

uint32_t path_id_tx;

usr.sbin/bgpd/rde.h

371

uint32_t ctx_id;

usr.sbin/bgpd/rde.h

404

uint32_t rde_local_as(void);

usr.sbin/bgpd/rde.h

418

struct rde_peer *peer_get(uint32_t);

usr.sbin/bgpd/rde.h

419

struct rde_peer *peer_match(struct ctl_neighbor *, uint32_t);

usr.sbin/bgpd/rde.h

420

struct rde_peer *peer_add(uint32_t, struct peer_config *, struct filter_head *);

usr.sbin/bgpd/rde.h

425

uint32_t, enum eval_mode);

usr.sbin/bgpd/rde.h

470

uint32_t aspath_neighbor(struct aspath *);

usr.sbin/bgpd/rde.h

471

int aspath_loopfree(struct aspath *, uint32_t);

usr.sbin/bgpd/rde.h

473

int aspath_match(struct aspath *, struct filter_as *, uint32_t);

usr.sbin/bgpd/rde.h

474

u_char *aspath_prepend(struct aspath *, uint32_t, int, uint16_t *);

usr.sbin/bgpd/rde.h

475

u_char *aspath_override(struct aspath *, uint32_t, uint32_t,

usr.sbin/bgpd/rde.h

491

static inline uint32_t

usr.sbin/bgpd/rde.h

53

uint32_t pq_peer_id;

usr.sbin/bgpd/rde.h

597

int pt_writebuf(struct ibuf *, struct pt_entry *, int, int, uint32_t);

usr.sbin/bgpd/rde.h

670

struct prefix *prefix_get(struct rib *, struct rde_peer *, uint32_t,

usr.sbin/bgpd/rde.h

672

int prefix_update(struct rib *, struct rde_peer *, uint32_t,

usr.sbin/bgpd/rde.h

673

uint32_t, struct filterstate *, int, struct bgpd_addr *,

usr.sbin/bgpd/rde.h

675

int prefix_withdraw(struct rib *, struct rde_peer *, uint32_t,

usr.sbin/bgpd/rde.h

678

struct pt_entry *, uint32_t);

usr.sbin/bgpd/rde.h

685

uint32_t);

usr.sbin/bgpd/rde.h

769

struct adjout_prefix *adjout_prefix_get(struct rde_peer *, uint32_t,

usr.sbin/bgpd/rde.h

777

struct filterstate *, struct pt_entry *, uint32_t);

usr.sbin/bgpd/rde.h

800

struct pt_entry *, uint32_t);

usr.sbin/bgpd/rde.h

812

struct prefix *, uint32_t);

usr.sbin/bgpd/rde.h

822

struct rde_aspa *aspa_table_prep(uint32_t, size_t);

usr.sbin/bgpd/rde.h

823

void aspa_add_set(struct rde_aspa *, uint32_t, const uint32_t *,

usr.sbin/bgpd/rde.h

824

uint32_t);

usr.sbin/bgpd/rde_adjout.c

152

struct pt_entry *, uint32_t);

usr.sbin/bgpd/rde_adjout.c

156

uint32_t path_id_tx)

usr.sbin/bgpd/rde_adjout.c

183

struct pt_entry *pt, uint32_t path_id_tx)

usr.sbin/bgpd/rde_adjout.c

227

uint32_t path_id_tx)

usr.sbin/bgpd/rde_adjout.c

409

struct adjout_attr *, uint32_t);

usr.sbin/bgpd/rde_adjout.c

414

uint32_t);

usr.sbin/bgpd/rde_adjout.c

418

static inline uint32_t

usr.sbin/bgpd/rde_adjout.c

434

adjout_prefix_get(struct rde_peer *peer, uint32_t path_id_tx,

usr.sbin/bgpd/rde_adjout.c

438

uint32_t i;

usr.sbin/bgpd/rde_adjout.c

458

adjout_prefix_with_attrs(struct pt_entry *pte, uint32_t path_id_tx,

usr.sbin/bgpd/rde_adjout.c

462

uint32_t i;

usr.sbin/bgpd/rde_adjout.c

485

uint32_t i;

usr.sbin/bgpd/rde_adjout.c

510

uint32_t i;

usr.sbin/bgpd/rde_adjout.c

533

struct filterstate *state, struct pt_entry *pte, uint32_t path_id_tx)

usr.sbin/bgpd/rde_adjout.c

739

struct adjout_attr *attrs, uint32_t path_id_tx)

usr.sbin/bgpd/rde_adjout.c

778

uint32_t newlen, avail;

usr.sbin/bgpd/rde_adjout.c

796

adjout_prefix_alloc(struct pt_entry *pte, uint32_t path_id_tx)

usr.sbin/bgpd/rde_adjout.c

799

uint32_t i;

usr.sbin/bgpd/rde_adjout.c

829

uint32_t i, idx;

usr.sbin/bgpd/rde_aspa.c

114

aspa_cp_lookup(struct rde_aspa *ra, uint32_t cas, uint32_t pas)

usr.sbin/bgpd/rde_aspa.c

117

uint32_t i;

usr.sbin/bgpd/rde_aspa.c

133

uint32_t lim, x;

usr.sbin/bgpd/rde_aspa.c

172

uint32_t as, prevas = 0;

usr.sbin/bgpd/rde_aspa.c

188

seg_size = 2 + sizeof(uint32_t) * seg_len;

usr.sbin/bgpd/rde_aspa.c

33

uint32_t as;

usr.sbin/bgpd/rde_aspa.c

336

aspa_table_prep(uint32_t entries, size_t datasize)

usr.sbin/bgpd/rde_aspa.c

339

uint32_t hsize = 1024;

usr.sbin/bgpd/rde_aspa.c

34

uint32_t num;

usr.sbin/bgpd/rde_aspa.c

35

uint32_t *pas;

usr.sbin/bgpd/rde_aspa.c

380

aspa_add_set(struct rde_aspa *ra, uint32_t cas, const uint32_t *pas,

usr.sbin/bgpd/rde_aspa.c

381

uint32_t pascnt)

usr.sbin/bgpd/rde_aspa.c

384

uint32_t h, i;

usr.sbin/bgpd/rde_aspa.c

451

uint32_t i;

usr.sbin/bgpd/rde_aspa.c

47

uint32_t mask;

usr.sbin/bgpd/rde_aspa.c

48

uint32_t maxset;

usr.sbin/bgpd/rde_aspa.c

50

uint32_t *data;

usr.sbin/bgpd/rde_aspa.c

53

uint32_t curset;

usr.sbin/bgpd/rde_aspa.c

70

static inline uint32_t

usr.sbin/bgpd/rde_aspa.c

71

hash(uint32_t h)

usr.sbin/bgpd/rde_aspa.c

85

aspa_lookup(struct rde_aspa *ra, uint32_t asnum)

usr.sbin/bgpd/rde_aspa.c

88

uint32_t h;

usr.sbin/bgpd/rde_attr.c

331

static uint32_t aspath_extract_origin(const void *, uint16_t);

usr.sbin/bgpd/rde_attr.c

409

uint32_t as;

usr.sbin/bgpd/rde_attr.c

420

seg_size = 2 + sizeof(uint32_t) * seg_len;

usr.sbin/bgpd/rde_attr.c

439

seg_size = 2 + sizeof(uint32_t) * seg_len;

usr.sbin/bgpd/rde_attr.c

496

uint32_t

usr.sbin/bgpd/rde_attr.c

522

seg_size = 2 + sizeof(uint32_t) * seg_len;

usr.sbin/bgpd/rde_attr.c

544

static uint32_t

usr.sbin/bgpd/rde_attr.c

548

uint32_t as = AS_NONE;

usr.sbin/bgpd/rde_attr.c

559

seg_size = 2 + sizeof(uint32_t) * seg_len;

usr.sbin/bgpd/rde_attr.c

583

seg_size = 2 + sizeof(uint32_t) * seg_len;

usr.sbin/bgpd/rde_attr.c

589

clen += 2 + sizeof(uint32_t) * cnt;

usr.sbin/bgpd/rde_attr.c

625

seg_size = 2 + sizeof(uint32_t) * seg_len;

usr.sbin/bgpd/rde_attr.c

631

seg_size = 2 + sizeof(uint32_t) * cnt;

usr.sbin/bgpd/rde_attr.c

650

aspath_loopfree(struct aspath *aspath, uint32_t myAS)

usr.sbin/bgpd/rde_attr.c

659

seg_size = 2 + sizeof(uint32_t) * seg_len;

usr.sbin/bgpd/rde_attr.c

673

as_compare(struct filter_as *f, uint32_t as, uint32_t neighas)

usr.sbin/bgpd/rde_attr.c

675

uint32_t match;

usr.sbin/bgpd/rde_attr.c

711

aspath_match(struct aspath *aspath, struct filter_as *f, uint32_t neighas)

usr.sbin/bgpd/rde_attr.c

717

uint32_t as = AS_NONE;

usr.sbin/bgpd/rde_attr.c

739

seg_size = 2 + sizeof(uint32_t) * seg_len;

usr.sbin/bgpd/rde_attr.c

783

aspath_prepend(struct aspath *asp, uint32_t as, int quantum, uint16_t *len)

usr.sbin/bgpd/rde_attr.c

819

l = 2 + quantum * sizeof(uint32_t) + asp->len;

usr.sbin/bgpd/rde_attr.c

825

l = quantum * sizeof(uint32_t) + asp->len;

usr.sbin/bgpd/rde_attr.c

840

memcpy(p + wpos, &as, sizeof(uint32_t));

usr.sbin/bgpd/rde_attr.c

841

wpos += sizeof(uint32_t);

usr.sbin/bgpd/rde_attr.c

850

memcpy(p + wpos, &as, sizeof(uint32_t));

usr.sbin/bgpd/rde_attr.c

851

wpos += sizeof(uint32_t);

usr.sbin/bgpd/rde_attr.c

865

aspath_override(struct aspath *asp, uint32_t neighbor_as, uint32_t local_as,

usr.sbin/bgpd/rde_attr.c

869

uint32_t as;

usr.sbin/bgpd/rde_attr.c

887

seg_size = 2 + sizeof(uint32_t) * seg_len;

usr.sbin/bgpd/rde_attr.c

910

uint32_t as, lastas = 0;

usr.sbin/bgpd/rde_attr.c

927

seg_size = 2 + sizeof(uint32_t) * seg_len;

usr.sbin/bgpd/rde_community.c

32

apply_flag(uint32_t in, uint8_t flag, struct rde_peer *peer, uint32_t *out,

usr.sbin/bgpd/rde_community.c

33

uint32_t *mask)

usr.sbin/bgpd/rde_decide.c

125

uint32_t p1id, p2id;

usr.sbin/bgpd/rde_decide.c

262

p1cnt = a->len / sizeof(uint32_t);

usr.sbin/bgpd/rde_decide.c

264

p2cnt = a->len / sizeof(uint32_t);

usr.sbin/bgpd/rde_decide.c

536

uint32_t old_pathid_tx = 0;

usr.sbin/bgpd/rde_decide.c

595

uint32_t old_pathid_tx;

usr.sbin/bgpd/rde_filter.c

45

uint32_t metric;

usr.sbin/bgpd/rde_filter.c

79

uint32_t prep_as;

usr.sbin/bgpd/rde_peer.c

123

peer_get(uint32_t id)

usr.sbin/bgpd/rde_peer.c

137

peer_match(struct ctl_neighbor *n, uint32_t peerid)

usr.sbin/bgpd/rde_peer.c

156

peer_add(uint32_t id, struct peer_config *p_conf, struct filter_head *rules)

usr.sbin/bgpd/rde_peer.c

253

struct prefix *newpath, uint32_t old_pathid_tx, enum eval_mode mode)

usr.sbin/bgpd/rde_peer.c

303

uint32_t old_pathid_tx, enum eval_mode mode)

usr.sbin/bgpd/rde_peer.c

32

uint32_t old_pathid_tx;

usr.sbin/bgpd/rde_peer.c

391

uint32_t i;

usr.sbin/bgpd/rde_prefix.c

101

uint32_t refcnt;

usr.sbin/bgpd/rde_prefix.c

113

uint32_t adjoutlen;

usr.sbin/bgpd/rde_prefix.c

114

uint32_t adjoutavail;

usr.sbin/bgpd/rde_prefix.c

118

uint32_t refcnt;

usr.sbin/bgpd/rde_prefix.c

120

uint32_t ethtag;

usr.sbin/bgpd/rde_prefix.c

136

uint32_t adjoutlen;

usr.sbin/bgpd/rde_prefix.c

137

uint32_t adjoutavail;

usr.sbin/bgpd/rde_prefix.c

141

uint32_t refcnt;

usr.sbin/bgpd/rde_prefix.c

55

uint32_t adjoutlen;

usr.sbin/bgpd/rde_prefix.c

56

uint32_t adjoutavail;

usr.sbin/bgpd/rde_prefix.c

60

uint32_t refcnt;

usr.sbin/bgpd/rde_prefix.c

632

int add_path, uint32_t pathid)

usr.sbin/bgpd/rde_prefix.c

67

uint32_t adjoutlen;

usr.sbin/bgpd/rde_prefix.c

68

uint32_t adjoutavail;

usr.sbin/bgpd/rde_prefix.c

72

uint32_t refcnt;

usr.sbin/bgpd/rde_prefix.c

79

uint32_t adjoutlen;

usr.sbin/bgpd/rde_prefix.c

80

uint32_t adjoutavail;

usr.sbin/bgpd/rde_prefix.c

84

uint32_t refcnt;

usr.sbin/bgpd/rde_prefix.c

96

uint32_t adjoutlen;

usr.sbin/bgpd/rde_prefix.c

97

uint32_t adjoutavail;

usr.sbin/bgpd/rde_rib.c

1017

struct pt_entry *pte, uint32_t path_id_tx)

usr.sbin/bgpd/rde_rib.c

1023

uint32_t old_pathid_tx = 0;

usr.sbin/bgpd/rde_rib.c

1103

prefix_bypeer(struct rib_entry *re, struct rde_peer *peer, uint32_t path_id)

usr.sbin/bgpd/rde_rib.c

1129

struct rde_peer *peer, uint32_t path_id, uint32_t path_id_tx,

usr.sbin/bgpd/rde_rib.c

1248

uint32_t j;

usr.sbin/bgpd/rde_rib.c

821

struct rde_peer *, uint32_t, uint32_t, struct rde_aspath *,

usr.sbin/bgpd/rde_rib.c

829

struct pt_entry *, struct rde_peer *, uint32_t, uint32_t,

usr.sbin/bgpd/rde_rib.c

841

prefix_get(struct rib *rib, struct rde_peer *peer, uint32_t path_id,

usr.sbin/bgpd/rde_rib.c

857

prefix_update(struct rib *rib, struct rde_peer *peer, uint32_t path_id,

usr.sbin/bgpd/rde_rib.c

858

uint32_t path_id_tx, struct filterstate *state, int filtered,

usr.sbin/bgpd/rde_rib.c

913

struct rde_peer *peer, uint32_t path_id, uint32_t path_id_tx,

usr.sbin/bgpd/rde_rib.c

990

prefix_withdraw(struct rib *rib, struct rde_peer *peer, uint32_t path_id,

usr.sbin/bgpd/rde_sets.c

105

as_set_match(const struct as_set *aset, uint32_t asnum)

usr.sbin/bgpd/rde_sets.c

156

uint32_t *s;

usr.sbin/bgpd/rde_sets.c

192

const uint32_t *a = ap;

usr.sbin/bgpd/rde_sets.c

193

const uint32_t *b = bp;

usr.sbin/bgpd/rde_sets.c

211

set_match(const struct set_table *a, uint32_t asnum)

usr.sbin/bgpd/rde_trie.c

574

uint32_t as)

usr.sbin/bgpd/rde_trie.c

622

uint32_t as)

usr.sbin/bgpd/rde_trie.c

676

uint32_t as)

usr.sbin/bgpd/rde_trie.c

85

uint32_t v;

usr.sbin/bgpd/rde_update.c

1078

uint32_t path_id_tx, struct ibuf *buf)

usr.sbin/bgpd/rde_update.c

138

uint32_t tmp;

usr.sbin/bgpd/rde_update.c

167

uint32_t path_id_tx = 0;

usr.sbin/bgpd/rde_update.c

265

uint32_t addpath_prefix_list[2000]; /* XXX */

usr.sbin/bgpd/rde_update.c

364

struct prefix *new, uint32_t old_pathid_tx)

usr.sbin/bgpd/rde_update.c

569

uint32_t prep_as = peer->conf.local_as;

usr.sbin/bgpd/rde_update.c

593

uint32_t tmp32;

usr.sbin/bgpd/rtr.c

134

aspa_set_entry(struct aspa_set *aspa, uint32_t asnum)

usr.sbin/bgpd/rtr.c

136

uint32_t i, num, *newtas;

usr.sbin/bgpd/rtr.c

146

newtas = reallocarray(aspa->tas, num, sizeof(uint32_t));

usr.sbin/bgpd/rtr.c

152

(aspa->num - i) * sizeof(uint32_t));

usr.sbin/bgpd/rtr.c

167

uint32_t i;

usr.sbin/bgpd/rtr.c

322

uint32_t rtrid;

usr.sbin/bgpd/rtr.c

481

rtr_imsg_compose(int type, uint32_t id, pid_t pid, void *data, size_t datalen)

usr.sbin/bgpd/rtr.c

495

return aspa->num * sizeof(uint32_t);

usr.sbin/bgpd/rtr_proto.c

102

uint32_t prefix[4];

usr.sbin/bgpd/rtr_proto.c

103

uint32_t asnum;

usr.sbin/bgpd/rtr_proto.c

109

uint32_t asnum;

usr.sbin/bgpd/rtr_proto.c

115

uint32_t cas;

usr.sbin/bgpd/rtr_proto.c

121

uint32_t serial;

usr.sbin/bgpd/rtr_proto.c

122

uint32_t refresh;

usr.sbin/bgpd/rtr_proto.c

123

uint32_t retry;

usr.sbin/bgpd/rtr_proto.c

124

uint32_t expire;

usr.sbin/bgpd/rtr_proto.c

129

uint32_t serial;

usr.sbin/bgpd/rtr_proto.c

1401

rtr_new(uint32_t id, struct rtr_config_msg *conf)

usr.sbin/bgpd/rtr_proto.c

1441

rtr_get(uint32_t id)

usr.sbin/bgpd/rtr_proto.c

194

uint32_t id; /* rtr_config id */

usr.sbin/bgpd/rtr_proto.c

195

uint32_t serial;

usr.sbin/bgpd/rtr_proto.c

196

uint32_t refresh;

usr.sbin/bgpd/rtr_proto.c

197

uint32_t retry;

usr.sbin/bgpd/rtr_proto.c

198

uint32_t expire;

usr.sbin/bgpd/rtr_proto.c

199

uint32_t active;

usr.sbin/bgpd/rtr_proto.c

279

rtr_newmsg(struct rtr_session *rs, enum rtr_pdu_type type, uint32_t len,

usr.sbin/bgpd/rtr_proto.c

348

buf = rtr_newmsg(rs, ERROR_REPORT, 2 * sizeof(uint32_t) + len + mlen,

usr.sbin/bgpd/rtr_proto.c

394

buf = rtr_newmsg(rs, SERIAL_QUERY, sizeof(uint32_t), rs->session_id);

usr.sbin/bgpd/rtr_proto.c

42

uint32_t length;

usr.sbin/bgpd/rtr_proto.c

68

uint32_t serial;

usr.sbin/bgpd/rtr_proto.c

73

uint32_t serial;

usr.sbin/bgpd/rtr_proto.c

773

uint32_t cnt, i;

usr.sbin/bgpd/rtr_proto.c

780

cnt = ibuf_size(pdu) / sizeof(uint32_t);

usr.sbin/bgpd/rtr_proto.c

823

if ((aspa->tas = calloc(cnt, sizeof(uint32_t))) == NULL) {

usr.sbin/bgpd/rtr_proto.c

903

uint32_t t;

usr.sbin/bgpd/rtr_proto.c

92

uint32_t prefix;

usr.sbin/bgpd/rtr_proto.c

93

uint32_t asnum;

usr.sbin/bgpd/rtr_proto.c

988

uint32_t pdu_len, msg_len;

usr.sbin/bgpd/session.c

1192

uint32_t peerid;

usr.sbin/bgpd/session.c

1604

uint32_t id;

usr.sbin/bgpd/session.c

1652

getpeerbyid(struct bgpd_config *c, uint32_t peerid)

usr.sbin/bgpd/session.c

1680

session_template_clone(struct peer *p, struct sockaddr *ip, uint32_t id,

usr.sbin/bgpd/session.c

1681

uint32_t as)

usr.sbin/bgpd/session.c

1800

imsg_ctl_rde_msg(int type, uint32_t peerid, pid_t pid)

usr.sbin/bgpd/session.c

1813

imsg_rde(int type, uint32_t peerid, void *data, uint16_t datalen)

usr.sbin/bgpd/session.c

67

void imsg_rde(int, uint32_t, void *, uint16_t);

usr.sbin/bgpd/session.c

71

uint32_t, uint32_t);

usr.sbin/bgpd/session.h

153

uint32_t msg_queue_len;

usr.sbin/bgpd/session.h

154

uint32_t prefix_cnt;

usr.sbin/bgpd/session.h

155

uint32_t prefix_out_cnt;

usr.sbin/bgpd/session.h

156

uint32_t pending_update;

usr.sbin/bgpd/session.h

157

uint32_t pending_withdraw;

usr.sbin/bgpd/session.h

168

uint32_t spi_in;

usr.sbin/bgpd/session.h

169

uint32_t spi_out;

usr.sbin/bgpd/session.h

221

uint32_t local_bgpid;

usr.sbin/bgpd/session.h

222

uint32_t remote_bgpid;

usr.sbin/bgpd/session.h

288

int pfkey_send_conf(struct imsgbuf *, uint32_t, struct auth_config *);

usr.sbin/bgpd/session.h

307

struct rtr_session *rtr_new(uint32_t, struct rtr_config_msg *);

usr.sbin/bgpd/session.h

308

struct rtr_session *rtr_get(uint32_t);

usr.sbin/bgpd/session.h

326

void rtr_imsg_compose(int, uint32_t, pid_t, void *, size_t);

usr.sbin/bgpd/session.h

338

struct peer *getpeerbyid(struct bgpd_config *, uint32_t);

usr.sbin/bgpd/session.h

349

int imsg_ctl_rde_msg(int, uint32_t, pid_t);

usr.sbin/bgpd/session_bgp.c

257

errs += session_capa_add(opb, CAPA_AS4BYTE, sizeof(uint32_t));

usr.sbin/bgpd/session_bgp.c

674

parse_capabilities(struct peer *peer, struct ibuf *buf, uint32_t *as)

usr.sbin/bgpd/session_bgp.c

897

uint32_t as, bgpid;

usr.sbin/bgpd/util.c

1173

uint32_t scope_id)

usr.sbin/bgpd/util.c

165

log_as(uint32_t as)

usr.sbin/bgpd/util.c

180

uint32_t u32;

usr.sbin/bgpd/util.c

272

uint32_t i;

usr.sbin/bgpd/util.c

453

uint32_t as;

usr.sbin/bgpd/util.c

493

uint32_t as;

usr.sbin/bgpd/util.c

552

uint32_t

usr.sbin/bgpd/util.c

556

uint32_t as;

usr.sbin/bgpd/util.c

561

ptr += 2 + sizeof(uint32_t) * pos;

usr.sbin/bgpd/util.c

562

memcpy(&as, ptr, sizeof(uint32_t));

usr.sbin/bgpd/util.c

618

uint32_t as;

usr.sbin/bgpd/util.c

93

uint32_t vni;

usr.sbin/bgplgd/slowcgi.c

141

uint32_t app_status;

usr.sbin/bgplgd/slowcgi.c

729

uint32_t name_len, val_len;

usr.sbin/btrace/bt_parser.h

51

uint32_t bp_pbn; /* ID assigned by the kernel */

usr.sbin/btrace/bt_parser.h

65

uint32_t bf_val;

usr.sbin/crunchgen/mangle.c

48

uint32_t key[MAX_KEY_STR_LEN];

usr.sbin/dhcpd/parse.c

293

uint32_t value;

usr.sbin/dhcrelay6/dhcp.h

30

#define ENTERPRISENO_LEN sizeof(uint32_t)

usr.sbin/dhcrelay6/dhcpd.h

73

uint32_t pc_enterpriseno;

usr.sbin/dhcrelay6/dhcrelay6.c

111

uint32_t enterpriseno = OPENBSD_ENTERPRISENO;

usr.sbin/eeprom/optree.c

40

uint32_t cell;

usr.sbin/eeprom/optree.c

84

cell = *(uint32_t *)&opio->op_buf[i];

usr.sbin/eigrpctl/parser.c

402

uint32_t uval;

usr.sbin/eigrpd/eigrp.h

114

uint32_t flags;

usr.sbin/eigrpd/eigrp.h

115

uint32_t seq_num;

usr.sbin/eigrpd/eigrp.h

116

uint32_t ack_num;

usr.sbin/eigrpd/eigrp.h

152

uint32_t seq;

usr.sbin/eigrpd/eigrp.h

156

uint32_t delay;

usr.sbin/eigrpd/eigrp.h

157

uint32_t bandwidth;

usr.sbin/eigrpd/eigrp.h

170

uint32_t routerid;

usr.sbin/eigrpd/eigrp.h

171

uint32_t as;

usr.sbin/eigrpd/eigrp.h

172

uint32_t tag;

usr.sbin/eigrpd/eigrp.h

173

uint32_t metric;

usr.sbin/eigrpd/eigrp.h

33

#define EIGRP_INFINITE_METRIC ((uint32_t )(~0))

usr.sbin/eigrpd/eigrpd.c

540

imsg_compose_event(struct imsgev *iev, uint16_t type, uint32_t peerid,

usr.sbin/eigrpd/eigrpd.h

214

uint32_t ifaceid;

usr.sbin/eigrpd/eigrpd.h

216

uint32_t delay;

usr.sbin/eigrpd/eigrpd.h

217

uint32_t bandwidth;

usr.sbin/eigrpd/eigrpd.h

247

uint32_t bandwidth;

usr.sbin/eigrpd/eigrpd.h

248

uint32_t delay;

usr.sbin/eigrpd/eigrpd.h

262

uint32_t as;

usr.sbin/eigrpd/eigrpd.h

263

uint32_t metric;

usr.sbin/eigrpd/eigrpd.h

264

uint32_t tag;

usr.sbin/eigrpd/eigrpd.h

270

uint32_t hellos_sent;

usr.sbin/eigrpd/eigrpd.h

271

uint32_t hellos_recv;

usr.sbin/eigrpd/eigrpd.h

272

uint32_t updates_sent;

usr.sbin/eigrpd/eigrpd.h

273

uint32_t updates_recv;

usr.sbin/eigrpd/eigrpd.h

274

uint32_t queries_sent;

usr.sbin/eigrpd/eigrpd.h

275

uint32_t queries_recv;

usr.sbin/eigrpd/eigrpd.h

276

uint32_t replies_sent;

usr.sbin/eigrpd/eigrpd.h

277

uint32_t replies_recv;

usr.sbin/eigrpd/eigrpd.h

278

uint32_t acks_sent;

usr.sbin/eigrpd/eigrpd.h

279

uint32_t acks_recv;

usr.sbin/eigrpd/eigrpd.h

280

uint32_t squeries_sent;

usr.sbin/eigrpd/eigrpd.h

281

uint32_t squeries_recv;

usr.sbin/eigrpd/eigrpd.h

282

uint32_t sreplies_sent;

usr.sbin/eigrpd/eigrpd.h

283

uint32_t sreplies_recv;

usr.sbin/eigrpd/eigrpd.h

303

uint32_t seq_num;

usr.sbin/eigrpd/eigrpd.h

382

uint32_t delay;

usr.sbin/eigrpd/eigrpd.h

383

uint32_t bandwidth;

usr.sbin/eigrpd/eigrpd.h

409

uint32_t distance;

usr.sbin/eigrpd/eigrpd.h

410

uint32_t rdistance;

usr.sbin/eigrpd/eigrpd.h

411

uint32_t fdistance;

usr.sbin/eigrpd/eigrpd.h

415

uint32_t delay;

usr.sbin/eigrpd/eigrpd.h

416

uint32_t bandwidth;

usr.sbin/eigrpd/eigrpd.h

417

uint32_t mtu;

usr.sbin/eigrpd/eigrpd.h

485

void addscope(struct sockaddr_in6 *, uint32_t);

usr.sbin/eigrpd/eigrpd.h

493

int imsg_compose_event(struct imsgev *, uint16_t, uint32_t,

usr.sbin/eigrpd/eigrpe.c

208

eigrpe_imsg_compose_rde(int type, uint32_t peerid, pid_t pid,

usr.sbin/eigrpd/eigrpe.h

103

struct eigrp_iface *eigrp_if_lookup_id(uint32_t);

usr.sbin/eigrpd/eigrpe.h

122

struct nbr *nbr_find_peerid(uint32_t);

usr.sbin/eigrpd/eigrpe.h

129

void rtp_process_ack(struct nbr *, uint32_t);

usr.sbin/eigrpd/eigrpe.h

138

int gen_eigrp_hdr(struct ibuf *, uint16_t, uint8_t, uint32_t,

usr.sbin/eigrpd/eigrpe.h

140

int send_packet(struct eigrp_iface *, struct nbr *, uint32_t,

usr.sbin/eigrpd/eigrpe.h

150

int gen_mcast_seq_tlv(struct ibuf *, uint32_t);

usr.sbin/eigrpd/eigrpe.h

164

void send_hello(struct eigrp_iface *, struct seq_addr_head *, uint32_t);

usr.sbin/eigrpd/eigrpe.h

170

void send_update(struct eigrp_iface *, struct nbr *, uint32_t,

usr.sbin/eigrpd/eigrpe.h

172

void recv_update(struct nbr *, struct rinfo_head *, uint32_t);

usr.sbin/eigrpd/eigrpe.h

36

uint32_t seq_num;

usr.sbin/eigrpd/eigrpe.h

49

uint32_t peerid;

usr.sbin/eigrpd/eigrpe.h

62

uint32_t recv_seq;

usr.sbin/eigrpd/eigrpe.h

63

uint32_t next_mcast_seq;

usr.sbin/eigrpd/eigrpe.h

79

int eigrpe_imsg_compose_rde(int, uint32_t, pid_t, void *,

usr.sbin/eigrpd/hello.c

34

uint32_t mcast_seq)

usr.sbin/eigrpd/interface.c

283

static uint32_t ifacecnt = 1;

usr.sbin/eigrpd/interface.c

352

eigrp_if_lookup_id(uint32_t ifaceid)

usr.sbin/eigrpd/kroute.c

39

uint32_t rtseq;

usr.sbin/eigrpd/neighbor.c

150

static uint32_t peercnt = NBR_CNTSTART;

usr.sbin/eigrpd/neighbor.c

182

nbr_find_peerid(uint32_t peerid)

usr.sbin/eigrpd/packet.c

159

send_packet(struct eigrp_iface *ei, struct nbr *nbr, uint32_t flags,

usr.sbin/eigrpd/packet.c

257

uint32_t seq, ack;

usr.sbin/eigrpd/packet.c

49

uint32_t seq_num, uint16_t as)

usr.sbin/eigrpd/parse.y

110

static uint32_t get_rtr_id(void);

usr.sbin/eigrpd/parse.y

1235

static uint32_t

usr.sbin/eigrpd/parse.y

1239

uint32_t ip = 0, cur, localnet;

usr.sbin/eigrpd/parse.y

75

uint32_t delay;

usr.sbin/eigrpd/parse.y

76

uint32_t bandwidth;

usr.sbin/eigrpd/rde.c

158

rde_imsg_compose_eigrpe(int type, uint32_t peerid, pid_t pid, void *data,

usr.sbin/eigrpd/rde.h

131

int rde_imsg_compose_eigrpe(int, uint32_t, pid_t, void *,

usr.sbin/eigrpd/rde.h

142

uint32_t eigrp_composite_delay(uint32_t);

usr.sbin/eigrpd/rde.h

143

uint32_t eigrp_real_delay(uint32_t);

usr.sbin/eigrpd/rde.h

144

uint32_t eigrp_composite_bandwidth(uint32_t);

usr.sbin/eigrpd/rde.h

145

uint32_t eigrp_real_bandwidth(uint32_t);

usr.sbin/eigrpd/rde.h

159

struct rde_nbr *rde_nbr_find(uint32_t);

usr.sbin/eigrpd/rde.h

160

struct rde_nbr *rde_nbr_new(uint32_t, struct rde_nbr *);

usr.sbin/eigrpd/rde.h

30

uint32_t peerid;

usr.sbin/eigrpd/rde.h

31

uint32_t ifaceid;

usr.sbin/eigrpd/rde.h

68

uint32_t distance; /* local distance */

usr.sbin/eigrpd/rde.h

69

uint32_t rdistance; /* reported distance */

usr.sbin/eigrpd/rde.h

89

uint32_t fdistance;

usr.sbin/eigrpd/rde.h

90

uint32_t rdistance;

usr.sbin/eigrpd/rde_dual.c

1180

uint32_t old_fdistance;

usr.sbin/eigrpd/rde_dual.c

1271

rde_nbr_find(uint32_t peerid)

usr.sbin/eigrpd/rde_dual.c

1281

rde_nbr_new(uint32_t peerid, struct rde_nbr *new)

usr.sbin/eigrpd/rde_dual.c

305

static uint32_t

usr.sbin/eigrpd/rde_dual.c

306

safe_sum_uint32(uint32_t a, uint32_t b)

usr.sbin/eigrpd/rde_dual.c

313

return ((uint32_t )(~0));

usr.sbin/eigrpd/rde_dual.c

315

return ((uint32_t) total);

usr.sbin/eigrpd/rde_dual.c

318

static uint32_t

usr.sbin/eigrpd/rde_dual.c

319

safe_mul_uint32(uint32_t a, uint32_t b)

usr.sbin/eigrpd/rde_dual.c

326

return ((uint32_t )(~0));

usr.sbin/eigrpd/rde_dual.c

328

return ((uint32_t) total);

usr.sbin/eigrpd/rde_dual.c

331

uint32_t

usr.sbin/eigrpd/rde_dual.c

332

eigrp_composite_delay(uint32_t delay)

usr.sbin/eigrpd/rde_dual.c

339

uint32_t

usr.sbin/eigrpd/rde_dual.c

340

eigrp_real_delay(uint32_t delay)

usr.sbin/eigrpd/rde_dual.c

345

uint32_t

usr.sbin/eigrpd/rde_dual.c

346

eigrp_composite_bandwidth(uint32_t bandwidth)

usr.sbin/eigrpd/rde_dual.c

353

uint32_t

usr.sbin/eigrpd/rde_dual.c

354

eigrp_real_bandwidth(uint32_t bandwidth)

usr.sbin/eigrpd/rde_dual.c

360

return ((EIGRP_SCALING_FACTOR * (uint32_t)10000000) / bandwidth);

usr.sbin/eigrpd/rde_dual.c

363

static uint32_t

usr.sbin/eigrpd/rde_dual.c

364

route_composite_metric(uint8_t *kvalues, uint32_t delay, uint32_t bandwidth,

usr.sbin/eigrpd/rde_dual.c

368

uint32_t operand1, operand2, operand3;

usr.sbin/eigrpd/rde_dual.c

37

static uint32_t safe_sum_uint32(uint32_t, uint32_t);

usr.sbin/eigrpd/rde_dual.c

38

static uint32_t safe_mul_uint32(uint32_t, uint32_t);

usr.sbin/eigrpd/rde_dual.c

39

static uint32_t route_composite_metric(uint8_t *, uint32_t, uint32_t,

usr.sbin/eigrpd/rde_dual.c

393

distance = ((uint32_t )(~0));

usr.sbin/eigrpd/rde_dual.c

395

return ((uint32_t) distance);

usr.sbin/eigrpd/rde_dual.c

403

uint32_t delay, bandwidth;

usr.sbin/eigrpd/rde_dual.c

703

uint32_t distance = EIGRP_INFINITE_METRIC;

usr.sbin/eigrpd/rde_dual.c

874

uint32_t old_fdistance;

usr.sbin/eigrpd/rde_dual.c

942

uint32_t old_fdistance;

usr.sbin/eigrpd/rtp.c

165

uint32_t flags = 0;

usr.sbin/eigrpd/rtp.c

32

static struct packet *rtp_packet_new(struct nbr *, uint32_t, struct pbuf *);

usr.sbin/eigrpd/rtp.c

69

rtp_packet_new(struct nbr *nbr, uint32_t seq_num, struct pbuf *pbuf)

usr.sbin/eigrpd/rtp.c

95

rtp_process_ack(struct nbr *nbr, uint32_t ack_num)

usr.sbin/eigrpd/tlv.c

121

gen_mcast_seq_tlv(struct ibuf *buf, uint32_t seq)

usr.sbin/eigrpd/update.c

33

send_update(struct eigrp_iface *ei, struct nbr *nbr, uint32_t flags,

usr.sbin/eigrpd/update.c

94

recv_update(struct nbr *nbr, struct rinfo_head *rinfo_list, uint32_t flags)

usr.sbin/eigrpd/util.c

223

uint32_t a = ntohl(addr.s_addr);

usr.sbin/eigrpd/util.c

295

addscope(struct sockaddr_in6 *sin6, uint32_t id)

usr.sbin/httpd/config.c

354

uint32_t id;

usr.sbin/httpd/httpd.c

1190

auth_byid(struct serverauth *serverauth, uint32_t id)

usr.sbin/httpd/httpd.c

121

uint32_t opts = 0;

usr.sbin/httpd/httpd.c

1221

printb_flags(const uint32_t v, const char *bits)

usr.sbin/httpd/httpd.c

823

uint32_t av[4], bv[4], mv[4];

usr.sbin/httpd/httpd.c

881

uint32_t

usr.sbin/httpd/httpd.c

894

prefixlen2mask6(uint8_t prefixlen, uint32_t *mask)

usr.sbin/httpd/httpd.h

122

uint32_t cf_flags;

usr.sbin/httpd/httpd.h

315

uint32_t clt_id;

usr.sbin/httpd/httpd.h

319

uint32_t clt_srv_id;

usr.sbin/httpd/httpd.h

438

uint32_t log_id;

usr.sbin/httpd/httpd.h

454

uint32_t auth_id;

usr.sbin/httpd/httpd.h

460

uint32_t tt_id;

usr.sbin/httpd/httpd.h

461

uint32_t tt_keyrev;

usr.sbin/httpd/httpd.h

474

uint32_t id;

usr.sbin/httpd/httpd.h

475

uint32_t parent_id;

usr.sbin/httpd/httpd.h

492

uint32_t maxrequests;

usr.sbin/httpd/httpd.h

511

uint32_t tls_protocols;

usr.sbin/httpd/httpd.h

518

uint32_t flags;

usr.sbin/httpd/httpd.h

531

uint32_t auth_id;

usr.sbin/httpd/httpd.h

558

uint32_t id;

usr.sbin/httpd/httpd.h

584

uint32_t sc_flags;

usr.sbin/httpd/httpd.h

662

serverconfig_byid(uint32_t);

usr.sbin/httpd/httpd.h

727

struct in6_addr *prefixlen2mask6(uint8_t, uint32_t *);

usr.sbin/httpd/httpd.h

728

uint32_t prefixlen2mask(uint8_t);

usr.sbin/httpd/httpd.h

755

struct auth *auth_byid(struct serverauth *, uint32_t);

usr.sbin/httpd/httpd.h

758

const char *printb_flags(const uint32_t, const char *);

usr.sbin/httpd/httpd.h

791

int imsg_compose_event(struct imsgev *, uint16_t, uint32_t,

usr.sbin/httpd/httpd.h

793

int imsg_composev_event(struct imsgev *, uint16_t, uint32_t,

usr.sbin/httpd/logger.c

141

uint32_t id;

usr.sbin/httpd/logger.c

163

uint32_t id;

usr.sbin/httpd/logger.c

247

uint32_t id;

usr.sbin/httpd/logger.c

47

static uint32_t last_log_id = 0;

usr.sbin/httpd/parse.y

101

uint32_t last_server_id = 0;

usr.sbin/httpd/parse.y

102

uint32_t last_auth_id = 0;

usr.sbin/httpd/parse.y

649

uint32_t f;

usr.sbin/httpd/proc.c

707

imsg_compose_event(struct imsgev *iev, uint16_t type, uint32_t peerid,

usr.sbin/httpd/proc.c

720

imsg_composev_event(struct imsgev *iev, uint16_t type, uint32_t peerid,

usr.sbin/httpd/proc.c

747

uint16_t type, uint32_t peerid, int fd, void *data, uint16_t datalen)

usr.sbin/httpd/proc.c

770

uint16_t type, uint32_t peerid, int fd, const struct iovec *iov, int iovcnt)

usr.sbin/httpd/server.c

524

serverconfig_byid(uint32_t id)

usr.sbin/httpd/server.c

542

server_byid(uint32_t id)

usr.sbin/httpd/server.c

62

struct server *server_byid(uint32_t);

usr.sbin/httpd/server.c

78

uint32_t server_cltid;

usr.sbin/installboot/efi_installboot.c

487

uint32_t orig_csum, new_csum;

usr.sbin/installboot/efi_installboot.c

488

uint32_t ghsize, ghpartsize, ghpartnum, ghpartspersec;

usr.sbin/installboot/i386_installboot.c

618

uint32_t orig_csum, new_csum;

usr.sbin/installboot/i386_installboot.c

619

uint32_t ghsize, ghpartsize, ghpartnum, ghpartspersec;

usr.sbin/installboot/i386_softraid.c

100

uint32_t bootsize, inodeblk, inodedbl;

usr.sbin/installboot/i386_softraid.c

49

uint32_t poffset;

usr.sbin/ldapd/btree.c

100

uint32_t version;

usr.sbin/ldapd/btree.c

101

uint32_t flags;

usr.sbin/ldapd/btree.c

102

uint32_t psize; /* page size */

usr.sbin/ldapd/btree.c

107

uint32_t flags;

usr.sbin/ldapd/btree.c

111

uint32_t branch_pages;

usr.sbin/ldapd/btree.c

112

uint32_t leaf_pages;

usr.sbin/ldapd/btree.c

113

uint32_t overflow_pages;

usr.sbin/ldapd/btree.c

114

uint32_t revisions;

usr.sbin/ldapd/btree.c

115

uint32_t depth;

usr.sbin/ldapd/btree.c

183

uint32_t np_dsize; /* leaf data size */

usr.sbin/ldapd/btree.c

1841

btree_new_page(struct btree *bt, uint32_t flags)

usr.sbin/ldapd/btree.c

273

static struct mpage *btree_new_page(struct btree *bt, uint32_t flags);

usr.sbin/ldapd/btree.c

60

typedef uint32_t pgno_t;

usr.sbin/ldapd/btree.c

73

uint32_t flags;

usr.sbin/ldapd/btree.c

99

uint32_t magic;

usr.sbin/ldapd/imsgev.c

58

uint32_t pid, int fd, void *data, u_int16_t datalen)

usr.sbin/ldapd/parse.y

1240

uint32_t tls_protocols = TLS_PROTOCOLS_DEFAULT;

usr.sbin/ldapd/util.c

124

val->data = malloc(val->size + sizeof(uint32_t));

usr.sbin/ldapd/util.c

126

log_warn("malloc(%zu)", val->size + sizeof(uint32_t));

usr.sbin/ldapd/util.c

130

dest = (char *)val->data + sizeof(uint32_t);

usr.sbin/ldapd/util.c

131

destlen = val->size - sizeof(uint32_t);

usr.sbin/ldapd/util.c

140

len, destlen + sizeof(uint32_t));

usr.sbin/ldapd/util.c

142

*(uint32_t *)val->data = len;

usr.sbin/ldapd/util.c

143

val->size = destlen + sizeof(uint32_t);

usr.sbin/ldapd/util.c

173

if (val->size < sizeof(uint32_t))

usr.sbin/ldapd/util.c

176

len = *(uint32_t *)val->data;

usr.sbin/ldapd/util.c

182

src = (char *)val->data + sizeof(uint32_t);

usr.sbin/ldapd/util.c

183

srclen = val->size - sizeof(uint32_t);

usr.sbin/ldapd/uuid.c

66

static uint32_t seq_num;

usr.sbin/ldomctl/mdesc.c

515

uint32_t offset;

usr.sbin/ldomctl/mdesc.c

683

uint32_t

usr.sbin/ldomctl/mdesc.c

686

uint32_t size;

usr.sbin/ldomctl/mdesc.h

141

uint32_t md_size(const char *);

usr.sbin/ldomctl/mdesc.h

24

uint32_t transport_version;

usr.sbin/ldomctl/mdesc.h

25

uint32_t node_blk_sz;

usr.sbin/ldomctl/mdesc.h

26

uint32_t name_blk_sz;

usr.sbin/ldomctl/mdesc.h

27

uint32_t data_blk_sz;

usr.sbin/ldomctl/mdesc.h

47

uint32_t name_offset;

usr.sbin/ldomctl/mdesc.h

50

uint32_t data_len;

usr.sbin/ldomctl/mdesc.h

51

uint32_t data_offset;

usr.sbin/ldomctl/mdesc.h

90

uint32_t offset;

usr.sbin/ldomctl/mdesc.h

99

uint32_t offset;

usr.sbin/ldomctl/mdstore.c

102

uint32_t namelen;

usr.sbin/ldomctl/mdstore.c

113

uint32_t msg_type;

usr.sbin/ldomctl/mdstore.c

114

uint32_t payload_len;

usr.sbin/ldomctl/mdstore.c

119

uint32_t size;

usr.sbin/ldomctl/mdstore.c

130

uint32_t msg_type;

usr.sbin/ldomctl/mdstore.c

131

uint32_t payload_len;

usr.sbin/ldomctl/mdstore.c

136

uint32_t namelen;

usr.sbin/ldomctl/mdstore.c

143

uint32_t msg_type;

usr.sbin/ldomctl/mdstore.c

144

uint32_t payload_len;

usr.sbin/ldomctl/mdstore.c

147

uint32_t result;

usr.sbin/ldomctl/mdstore.c

275

int nmds, uint32_t config_size)

usr.sbin/ldomctl/mdstore.c

301

int nmds, uint32_t config_size)

usr.sbin/ldomctl/mdstore.c

329

int nmds, uint32_t config_size)

usr.sbin/ldomctl/mdstore.c

344

uint32_t size;

usr.sbin/ldomctl/mdstore.c

475

uint32_t total_size = 0;

usr.sbin/ldomctl/mdstore.c

58

uint32_t msg_type;

usr.sbin/ldomctl/mdstore.c

59

uint32_t payload_len;

usr.sbin/ldomctl/mdstore.c

67

uint32_t msg_type;

usr.sbin/ldomctl/mdstore.c

68

uint32_t payload_len;

usr.sbin/ldomctl/mdstore.c

73

uint32_t namelen;

usr.sbin/ldomctl/mdstore.c

78

uint32_t msg_type;

usr.sbin/ldomctl/mdstore.c

79

uint32_t payload_len;

usr.sbin/ldomctl/mdstore.c

84

uint32_t config_size;

usr.sbin/ldomctl/mdstore.c

86

uint32_t namelen;

usr.sbin/ldomctl/mdstore.c

91

uint32_t msg_type;

usr.sbin/ldomctl/mdstore.c

92

uint32_t payload_len;

usr.sbin/ldomctl/mdstore.c

97

uint32_t config_size;

usr.sbin/ldomctl/pri.c

36

uint32_t msg_type;

usr.sbin/ldomctl/pri.c

37

uint32_t payload_len;

usr.sbin/ldomctl/pri.c

46

uint32_t msg_type;

usr.sbin/ldomctl/pri.c

47

uint32_t payload_len;

usr.sbin/ldomctl/pri.c

57

uint32_t msg_type;

usr.sbin/ldomctl/pri.c

58

uint32_t payload_len;

usr.sbin/ldomd/ds.c

407

ldc_ack(struct ldc_conn *lc, uint32_t ackid)

usr.sbin/ldomd/ds.h

101

uint32_t msg_type;

usr.sbin/ldomd/ds.h

102

uint32_t payload_len;

usr.sbin/ldomd/ds.h

107

uint32_t msg_type;

usr.sbin/ldomd/ds.h

108

uint32_t payload_len;

usr.sbin/ldomd/ds.h

114

uint32_t msg_type;

usr.sbin/ldomd/ds.h

115

uint32_t payload_len;

usr.sbin/ldomd/ds.h

124

uint32_t msg_type;

usr.sbin/ldomd/ds.h

125

uint32_t payload_len;

usr.sbin/ldomd/ds.h

135

uint32_t msg_type;

usr.sbin/ldomd/ds.h

136

uint32_t payload_len;

usr.sbin/ldomd/ds.h

145

uint32_t msg_type;

usr.sbin/ldomd/ds.h

146

uint32_t payload_len;

usr.sbin/ldomd/ds.h

156

uint32_t msg_type;

usr.sbin/ldomd/ds.h

157

uint32_t payload_len;

usr.sbin/ldomd/ds.h

166

uint32_t msg_type;

usr.sbin/ldomd/ds.h

167

uint32_t payload_len;

usr.sbin/ldomd/ds.h

175

uint32_t msg_type;

usr.sbin/ldomd/ds.h

176

uint32_t payload_len;

usr.sbin/ldomd/ds.h

198

void ldc_ack(struct ldc_conn *, uint32_t);

usr.sbin/ldomd/ds.h

213

uint32_t ackid;

usr.sbin/ldomd/ds.h

36

uint32_t seqid;

usr.sbin/ldomd/ds.h

40

uint32_t ackid;

usr.sbin/ldomd/ds.h

76

uint32_t lc_tx_seqid;

usr.sbin/ldomd/hvctl.h

62

uint32_t del_reconf_gid;

usr.sbin/ldomd/hvctl.h

67

uint32_t guestid;

usr.sbin/ldomd/hvctl.h

71

uint32_t guestid;

usr.sbin/ldomd/hvctl.h

72

uint32_t code;

usr.sbin/ldomd/hvctl.h

76

uint32_t res;

usr.sbin/ldomd/hvctl.h

77

uint32_t resid;

usr.sbin/ldomd/hvctl.h

78

uint32_t infoid;

usr.sbin/ldomd/hvctl.h

79

uint32_t code;

usr.sbin/ldomd/var-config.c

46

uint32_t msg_type;

usr.sbin/ldomd/var-config.c

47

uint32_t payload_len;

usr.sbin/ldomd/var-config.c

49

uint32_t cmd;

usr.sbin/ldomd/var-config.c

57

uint32_t msg_type;

usr.sbin/ldomd/var-config.c

58

uint32_t payload_len;

usr.sbin/ldomd/var-config.c

60

uint32_t cmd;

usr.sbin/ldomd/var-config.c

61

uint32_t result;

usr.sbin/ldomd/var-config.c

70

uint32_t

usr.sbin/ldomd/var-config.c

94

uint32_t

usr.sbin/ldpd/adjacency.c

95

adj_del(struct adj *adj, uint32_t notif_status)

usr.sbin/ldpd/hello.c

159

uint32_t scope_id = 0;

usr.sbin/ldpd/hello.c

160

uint32_t conf_seqnum;

usr.sbin/ldpd/hello.c

29

static int gen_opt4_hello_prms_tlv(struct ibuf *, uint16_t, uint32_t);

usr.sbin/ldpd/hello.c

31

static int gen_ds_hello_prms_tlv(struct ibuf *, uint32_t);

usr.sbin/ldpd/hello.c

34

union ldpd_addr *, uint32_t *, uint16_t *);

usr.sbin/ldpd/hello.c

424

gen_opt4_hello_prms_tlv(struct ibuf *buf, uint16_t type, uint32_t value)

usr.sbin/ldpd/hello.c

450

gen_ds_hello_prms_tlv(struct ibuf *buf, uint32_t value)

usr.sbin/ldpd/hello.c

483

union ldpd_addr *addr, uint32_t *conf_number, uint16_t *trans_pref)

usr.sbin/ldpd/hello.c

536

if (tlv_len != sizeof(uint32_t))

usr.sbin/ldpd/hello.c

538

memcpy(conf_number, buf, sizeof(uint32_t));

usr.sbin/ldpd/hello.c

542

if (tlv_len != sizeof(uint32_t))

usr.sbin/ldpd/kroute.c

367

uint32_t rl;

usr.sbin/ldpd/kroute.c

41

uint32_t rtseq;

usr.sbin/ldpd/l2vpn.c

335

l2vpn_send_pw_status(struct lde_nbr *ln, uint32_t status, struct fec *fec)

usr.sbin/ldpd/l2vpn.c

351

l2vpn_send_pw_status_wcard(struct lde_nbr *ln, uint32_t status,

usr.sbin/ldpd/l2vpn.c

352

uint16_t pw_type, uint32_t group_id)

usr.sbin/ldpd/labelmapping.c

130

uint32_t label = NO_LABEL, reqid = 0;

usr.sbin/ldpd/labelmapping.c

131

uint32_t pw_status = 0;

usr.sbin/ldpd/labelmapping.c

246

uint32_t reqbuf, labelbuf, statusbuf;

usr.sbin/ldpd/labelmapping.c

34

static int gen_label_tlv(struct ibuf *, uint32_t);

usr.sbin/ldpd/labelmapping.c

36

uint16_t, uint32_t *);

usr.sbin/ldpd/labelmapping.c

37

static int gen_reqid_tlv(struct ibuf *, uint32_t);

usr.sbin/ldpd/labelmapping.c

443

gen_label_tlv(struct ibuf *buf, uint32_t label)

usr.sbin/ldpd/labelmapping.c

456

uint16_t len, uint32_t *label)

usr.sbin/ldpd/labelmapping.c

502

gen_reqid_tlv(struct ibuf *buf, uint32_t reqid)

usr.sbin/ldpd/labelmapping.c

514

gen_pw_status_tlv(struct ibuf *buf, uint32_t status)

usr.sbin/ldpd/labelmapping.c

571

uint32_t group_id, pwid;

usr.sbin/ldpd/labelmapping.c

624

err |= ibuf_add(buf, &group_id, sizeof(uint32_t));

usr.sbin/ldpd/labelmapping.c

627

err |= ibuf_add(buf, &pwid, sizeof(uint32_t));

usr.sbin/ldpd/labelmapping.c

783

memcpy(&map->fec.pwid.group_id, buf + off, sizeof(uint32_t));

usr.sbin/ldpd/labelmapping.c

785

off += sizeof(uint32_t);

usr.sbin/ldpd/labelmapping.c

791

if (pw_len < sizeof(uint32_t)) {

usr.sbin/ldpd/labelmapping.c

797

memcpy(&map->fec.pwid.pwid, buf + off, sizeof(uint32_t));

usr.sbin/ldpd/labelmapping.c

800

off += sizeof(uint32_t);

usr.sbin/ldpd/labelmapping.c

801

pw_len -= sizeof(uint32_t);

usr.sbin/ldpd/lde.c

1002

lde_send_notification(struct lde_nbr *ln, uint32_t status_code, uint32_t msg_id,

usr.sbin/ldpd/lde.c

1056

lde_nbr_new(uint32_t peerid, struct lde_nbr *new)

usr.sbin/ldpd/lde.c

1135

lde_nbr_find(uint32_t peerid)

usr.sbin/ldpd/lde.c

182

lde_imsg_compose_ldpe(int type, uint32_t peerid, pid_t pid, void *data,

usr.sbin/ldpd/lde.c

49

static struct lde_nbr *lde_nbr_new(uint32_t, struct lde_nbr *);

usr.sbin/ldpd/lde.c

51

static struct lde_nbr *lde_nbr_find(uint32_t);

usr.sbin/ldpd/lde.c

574

uint32_t

usr.sbin/ldpd/lde.c

577

static uint32_t label = MPLS_LABEL_RESERVED_MAX;

usr.sbin/ldpd/lde.c

911

lde_send_labelwithdraw_wcard(struct lde_nbr *ln, uint32_t label)

usr.sbin/ldpd/lde.c

923

uint32_t label)

usr.sbin/ldpd/lde.c

937

uint32_t label)

usr.sbin/ldpd/lde.c

951

uint32_t group_id)

usr.sbin/ldpd/lde.c

966

struct map *wcard, uint32_t label)

usr.sbin/ldpd/lde.h

105

uint32_t remote_label;

usr.sbin/ldpd/lde.h

116

uint32_t local_label;

usr.sbin/ldpd/lde.h

129

int lde_imsg_compose_ldpe(int, uint32_t, pid_t, void *, uint16_t);

usr.sbin/ldpd/lde.h

130

uint32_t lde_assign_label(void);

usr.sbin/ldpd/lde.h

139

void lde_send_labelwithdraw_wcard(struct lde_nbr *, uint32_t);

usr.sbin/ldpd/lde.h

141

uint16_t, uint32_t);

usr.sbin/ldpd/lde.h

143

uint32_t);

usr.sbin/ldpd/lde.h

145

uint32_t);

usr.sbin/ldpd/lde.h

147

struct map *, uint32_t);

usr.sbin/ldpd/lde.h

148

void lde_send_notification(struct lde_nbr *, uint32_t, uint32_t,

usr.sbin/ldpd/lde.h

175

uint32_t egress_label(enum fec_type);

usr.sbin/ldpd/lde.h

210

void l2vpn_send_pw_status(struct lde_nbr *, uint32_t, struct fec *);

usr.sbin/ldpd/lde.h

211

void l2vpn_send_pw_status_wcard(struct lde_nbr *, uint32_t,

usr.sbin/ldpd/lde.h

212

uint16_t, uint32_t);

usr.sbin/ldpd/lde.h

48

uint32_t pwid;

usr.sbin/ldpd/lde.h

59

uint32_t msg_id;

usr.sbin/ldpd/lde.h

73

uint32_t label;

usr.sbin/ldpd/lde.h

86

uint32_t peerid;

usr.sbin/ldpd/lde_lib.c

324

uint32_t

usr.sbin/ldpd/ldp.h

116

uint32_t lsr_id;

usr.sbin/ldpd/ldp.h

134

uint32_t id;

usr.sbin/ldpd/ldp.h

159

uint32_t value;

usr.sbin/ldpd/ldp.h

226

uint32_t lsr_id;

usr.sbin/ldpd/ldp.h

236

uint32_t status_code;

usr.sbin/ldpd/ldp.h

237

uint32_t msg_id;

usr.sbin/ldpd/ldp.h

313

uint32_t label;

usr.sbin/ldpd/ldp.h

321

uint32_t reqid;

usr.sbin/ldpd/ldp.h

329

uint32_t value;

usr.sbin/ldpd/ldpd.c

572

imsg_compose_event(struct imsgev *iev, uint16_t type, uint32_t peerid,

usr.sbin/ldpd/ldpd.h

198

uint32_t msg_id;

usr.sbin/ldpd/ldpd.h

207

uint32_t pwid;

usr.sbin/ldpd/ldpd.h

208

uint32_t group_id;

usr.sbin/ldpd/ldpd.h

220

uint32_t status_code;

usr.sbin/ldpd/ldpd.h

221

uint32_t msg_id;

usr.sbin/ldpd/ldpd.h

224

uint32_t label;

usr.sbin/ldpd/ldpd.h

225

uint32_t requestid;

usr.sbin/ldpd/ldpd.h

226

uint32_t pw_status;

usr.sbin/ldpd/ldpd.h

237

uint32_t status_code;

usr.sbin/ldpd/ldpd.h

238

uint32_t msg_id; /* network byte order */

usr.sbin/ldpd/ldpd.h

240

uint32_t pw_status;

usr.sbin/ldpd/ldpd.h

334

uint32_t pwid;

usr.sbin/ldpd/ldpd.h

337

uint32_t remote_group;

usr.sbin/ldpd/ldpd.h

339

uint32_t remote_status;

usr.sbin/ldpd/ldpd.h

433

uint32_t conf_seqnum;

usr.sbin/ldpd/ldpd.h

448

uint32_t local_label;

usr.sbin/ldpd/ldpd.h

449

uint32_t remote_label;

usr.sbin/ldpd/ldpd.h

460

uint32_t local_label;

usr.sbin/ldpd/ldpd.h

461

uint32_t remote_label;

usr.sbin/ldpd/ldpd.h

525

uint32_t local_label;

usr.sbin/ldpd/ldpd.h

526

uint32_t remote_label;

usr.sbin/ldpd/ldpd.h

534

uint32_t pwid;

usr.sbin/ldpd/ldpd.h

536

uint32_t local_label;

usr.sbin/ldpd/ldpd.h

537

uint32_t local_gid;

usr.sbin/ldpd/ldpd.h

539

uint32_t remote_label;

usr.sbin/ldpd/ldpd.h

540

uint32_t remote_gid;

usr.sbin/ldpd/ldpd.h

542

uint32_t status;

usr.sbin/ldpd/ldpd.h

587

void addscope(struct sockaddr_in6 *, uint32_t);

usr.sbin/ldpd/ldpd.h

596

int imsg_compose_event(struct imsgev *, uint16_t, uint32_t, pid_t,

usr.sbin/ldpd/ldpd.h

642

char *log_label(uint32_t);

usr.sbin/ldpd/ldpd.h

652

const char *status_code_name(uint32_t);

usr.sbin/ldpd/ldpe.c

205

ldpe_imsg_compose_lde(int type, uint32_t peerid, pid_t pid, void *data,

usr.sbin/ldpd/ldpe.h

103

uint32_t auth_spi_in;

usr.sbin/ldpd/ldpe.h

104

uint32_t auth_spi_out;

usr.sbin/ldpd/ldpe.h

172

void send_notification(struct tcp_conn *, uint32_t, uint32_t, uint16_t);

usr.sbin/ldpd/ldpe.h

173

void send_notification_rtlvs(struct nbr *, uint32_t, uint32_t, uint16_t,

usr.sbin/ldpd/ldpe.h

176

int gen_status_tlv(struct ibuf *, uint32_t, uint32_t, uint16_t);

usr.sbin/ldpd/ldpe.h

188

int gen_pw_status_tlv(struct ibuf *, uint32_t);

usr.sbin/ldpd/ldpe.h

198

int ldpe_imsg_compose_lde(int, uint32_t, pid_t, void *,

usr.sbin/ldpd/ldpe.h

225

void adj_del(struct adj *, uint32_t);

usr.sbin/ldpd/ldpe.h

240

uint32_t);

usr.sbin/ldpd/ldpe.h

242

struct nbr *nbr_find_ldpid(uint32_t);

usr.sbin/ldpd/ldpe.h

244

struct nbr *nbr_find_peerid(uint32_t);

usr.sbin/ldpd/ldpe.h

272

void session_shutdown(struct nbr *, uint32_t, uint32_t,

usr.sbin/ldpd/ldpe.h

273

uint32_t);

usr.sbin/ldpd/ldpe.h

86

uint32_t peerid; /* unique ID in DB */

usr.sbin/ldpd/ldpe.h

94

uint32_t raddr_scope; /* remote address scope (v6) */

usr.sbin/ldpd/ldpe.h

98

uint32_t conf_seqnum;

usr.sbin/ldpd/logmsg.c

106

log_label(uint32_t label)

usr.sbin/ldpd/logmsg.c

351

status_code_name(uint32_t status)

usr.sbin/ldpd/neighbor.c

223

uint32_t scope_id)

usr.sbin/ldpd/neighbor.c

318

static uint32_t peercnt = 1;

usr.sbin/ldpd/neighbor.c

333

nbr_find_ldpid(uint32_t lsr_id)

usr.sbin/ldpd/neighbor.c

350

nbr_find_peerid(uint32_t peerid)

usr.sbin/ldpd/notification.c

174

nm.pw_status = ntohl(*(uint32_t *)buf);

usr.sbin/ldpd/notification.c

259

gen_status_tlv(struct ibuf *buf, uint32_t status_code, uint32_t msg_id,

usr.sbin/ldpd/notification.c

77

send_notification(struct tcp_conn *tcp, uint32_t status_code, uint32_t msg_id,

usr.sbin/ldpd/notification.c

91

send_notification_rtlvs(struct nbr *nbr, uint32_t status_code, uint32_t msg_id,

usr.sbin/ldpd/packet.c

618

session_shutdown(struct nbr *nbr, uint32_t status, uint32_t msg_id,

usr.sbin/ldpd/packet.c

619

uint32_t msg_type)

usr.sbin/ldpd/parse.y

113

static uint32_t get_rtr_id(void);

usr.sbin/ldpd/parse.y

1633

static uint32_t

usr.sbin/ldpd/parse.y

1637

uint32_t ip = 0, cur, localnet;

usr.sbin/ldpd/pfkey.c

281

pfkey_reply(int sd, uint32_t *spip)

usr.sbin/ldpd/pfkey.c

32

uint32_t, uint8_t, int, char *, uint8_t, int, char *,

usr.sbin/ldpd/pfkey.c

34

static int pfkey_reply(int, uint32_t *);

usr.sbin/ldpd/pfkey.c

341

char *key, uint32_t *spi)

usr.sbin/ldpd/pfkey.c

358

uint32_t *spi)

usr.sbin/ldpd/pfkey.c

36

uint8_t, char *, uint32_t *);

usr.sbin/ldpd/pfkey.c

38

uint32_t *);

usr.sbin/ldpd/pfkey.c

46

static uint32_t sadb_msg_seq;

usr.sbin/ldpd/pfkey.c

47

static uint32_t pid; /* should pid_t but pfkey needs uint32_t */

usr.sbin/ldpd/pfkey.c

52

int af, union ldpd_addr *src, union ldpd_addr *dst, uint32_t spi,

usr.sbin/ldpd/util.c

222

uint32_t a = ntohl(addr.s_addr);

usr.sbin/ldpd/util.c

294

addscope(struct sockaddr_in6 *sin6, uint32_t id)

usr.sbin/lldp/lldp.c

1068

lldp_org_tlv_lookup(uint32_t type)

usr.sbin/lldp/lldp.c

1085

uint32_t type;

usr.sbin/lldp/lldp.c

732

uint32_t ifnum;

usr.sbin/lldp/lldp.c

83

uint32_t type; /* big enough for org tlv type too */

usr.sbin/lldp/lldp.c

866

uint32_t portid;

usr.sbin/lldpd/pdu.c

35

uint32_t

usr.sbin/lldpd/pdu.c

38

uint32_t u32;

usr.sbin/lldpd/pdu.c

40

u32 = (uint32_t)buf[0] << 24;

usr.sbin/lldpd/pdu.c

41

u32 |= (uint32_t)buf[1] << 16;

usr.sbin/lldpd/pdu.c

42

u32 |= (uint32_t)buf[2] << 8;

usr.sbin/lldpd/pdu.c

43

u32 |= (uint32_t)buf[3];

usr.sbin/lldpd/pdu.h

29

uint32_t pdu_u32(const uint8_t *);

usr.sbin/lpd/engine_lpr.c

195

lpr_allowedhost(uint32_t connid, const struct sockaddr *sa)

usr.sbin/lpd/engine_lpr.c

301

lpr_allowedhost_res(uint32_t connid, const char *hostname, const char *reject)

usr.sbin/lpd/engine_lpr.c

387

lpr_displayq(uint32_t connid, const char *prn, int lng, struct lp_jobfilter *jf)

usr.sbin/lpd/engine_lpr.c

426

lpr_displayq_res(uint32_t connid, int fd, const char *host, const char *cmd)

usr.sbin/lpd/engine_lpr.c

43

uint32_t connid;

usr.sbin/lpd/engine_lpr.c

435

lpr_rmjob(uint32_t connid, const char *prn, const char *agent,

usr.sbin/lpd/engine_lpr.c

479

lpr_rmjob_res(uint32_t connid, int fd, const char *host, const char *cmd)

usr.sbin/lpd/engine_lpr.c

488

lpr_recvjob(uint32_t connid, const char *hostfrom, const char *prn)

usr.sbin/lpd/engine_lpr.c

51

static void lpr_allowedhost(uint32_t, const struct sockaddr *);

usr.sbin/lpd/engine_lpr.c

52

static void lpr_allowedhost_res(uint32_t, const char *, const char *);

usr.sbin/lpd/engine_lpr.c

530

lpr_recvjob_res(uint32_t connid, int ack)

usr.sbin/lpd/engine_lpr.c

538

lpr_recvjob_cf(uint32_t connid, size_t size, const char *filename)

usr.sbin/lpd/engine_lpr.c

54

static void lpr_displayq(uint32_t, const char *, int, struct lp_jobfilter *);

usr.sbin/lpd/engine_lpr.c

55

static void lpr_displayq_res(uint32_t, int, const char *, const char *);

usr.sbin/lpd/engine_lpr.c

56

static void lpr_rmjob(uint32_t, const char *, const char *,

usr.sbin/lpd/engine_lpr.c

58

static void lpr_rmjob_res(uint32_t, int, const char *, const char *);

usr.sbin/lpd/engine_lpr.c

59

static void lpr_recvjob(uint32_t, const char*, const char *);

usr.sbin/lpd/engine_lpr.c

593

lpr_recvjob_df(uint32_t connid, size_t size, const char *filename)

usr.sbin/lpd/engine_lpr.c

60

static void lpr_recvjob_res(uint32_t, int);

usr.sbin/lpd/engine_lpr.c

61

static void lpr_recvjob_cf(uint32_t, size_t, const char *);

usr.sbin/lpd/engine_lpr.c

62

static void lpr_recvjob_df(uint32_t, size_t, const char *);

usr.sbin/lpd/engine_lpr.c

63

static void lpr_recvjob_clear(uint32_t);

usr.sbin/lpd/engine_lpr.c

64

static void lpr_recvjob_commit(uint32_t);

usr.sbin/lpd/engine_lpr.c

647

lpr_recvjob_clear(uint32_t connid)

usr.sbin/lpd/engine_lpr.c

65

static void lpr_recvjob_rollback(uint32_t);

usr.sbin/lpd/engine_lpr.c

681

lpr_recvjob_commit(uint32_t connid)

usr.sbin/lpd/engine_lpr.c

718

lpr_recvjob_rollback(uint32_t connid)

usr.sbin/lpd/engine_lpr.c

79

uint32_t connid;

usr.sbin/lpd/frontend.c

116

frontend_conn_closed(uint32_t connid)

usr.sbin/lpd/frontend.c

45

uint32_t id;

usr.sbin/lpd/frontend_lpr.c

105

lpr_conn(uint32_t connid, struct listener *l, int sock,

usr.sbin/lpd/frontend_lpr.c

53

uint32_t id;

usr.sbin/lpd/frontend_lpr.c

617

uint32_t connid = conn->id;

usr.sbin/lpd/lpd.h

115

void frontend_conn_closed(uint32_t);

usr.sbin/lpd/lpd.h

133

void lpr_conn(uint32_t, struct listener *, int, const struct sockaddr *);

usr.sbin/lpd/parse.y

96

uint32_t options;

usr.sbin/lpd/proc.c

326

m_compose(struct imsgproc *p, uint32_t type, uint32_t peerid, pid_t pid, int fd,

usr.sbin/lpd/proc.c

336

m_create(struct imsgproc *p, uint32_t type, uint32_t peerid, pid_t pid, int fd)

usr.sbin/lpd/proc.c

386

m_add_u32(struct imsgproc *p, uint32_t v)

usr.sbin/lpd/proc.c

460

m_get_u32(struct imsgproc *p, uint32_t *dst)

usr.sbin/lpd/proc.c

53

uint32_t type;

usr.sbin/lpd/proc.c

54

uint32_t peerid;

usr.sbin/lpd/proc.h

36

void m_compose(struct imsgproc *, uint32_t, uint32_t, pid_t, int, const void *,

usr.sbin/lpd/proc.h

38

void m_create(struct imsgproc *, uint32_t, uint32_t, pid_t, int);

usr.sbin/lpd/proc.h

42

void m_add_u32(struct imsgproc *, uint32_t);

usr.sbin/lpd/proc.h

52

void m_get_u32(struct imsgproc *, uint32_t *);

usr.sbin/lpd/resolver.c

138

uint32_t reqid;

usr.sbin/lpd/resolver.c

45

uint32_t id;

usr.sbin/lpd/resolver.c

53

uint32_t reqid;

usr.sbin/makefs/cd9660.h

140

uint32_t fileDataSector;

usr.sbin/makefs/cd9660.h

274

void cd9660_731(uint32_t, unsigned char *);

usr.sbin/makefs/cd9660.h

276

void cd9660_732(uint32_t, unsigned char *);

usr.sbin/makefs/cd9660.h

277

void cd9660_bothendian_dword(uint32_t dw, unsigned char *);

usr.sbin/makefs/cd9660/cd9660_conversion.c

101

cd9660_bothendian_dword(uint32_t dw, unsigned char *eightchar)

usr.sbin/makefs/cd9660/cd9660_conversion.c

103

uint32_t le, be;

usr.sbin/makefs/cd9660/cd9660_conversion.c

67

cd9660_731(uint32_t w, unsigned char *fourchar)

usr.sbin/makefs/cd9660/cd9660_conversion.c

86

cd9660_732(uint32_t w, unsigned char *fourchar)

usr.sbin/makefs/cd9660/cd9660_eltorito.c

486

uint32_t lba;

usr.sbin/makefs/cd9660/cd9660_eltorito.c

521

uint32_t apm32, part_status;

usr.sbin/makefs/cd9660/cd9660_eltorito.c

617

uint32_t apm32;

usr.sbin/makefs/ffs.c

120

static void ffs_write_file(union dinode *, uint32_t, void *, fsinfo_t *);

usr.sbin/makefs/ffs.c

121

static void ffs_write_inode(union dinode *, uint32_t, const fsinfo_t *);

usr.sbin/makefs/ffs.c

226

uint32_t rdsize, poffset;

usr.sbin/makefs/ffs.c

227

const uint32_t sectorsize = fsopts->sectorsize;

usr.sbin/makefs/ffs.c

228

const uint32_t fsize = ffs_opts->fsize;

usr.sbin/makefs/ffs.c

229

const uint32_t bsize = ffs_opts->bsize;

usr.sbin/makefs/ffs.c

309

uint32_t bpg;

usr.sbin/makefs/ffs.c

779

ffs_write_file(union dinode *din, uint32_t ino, void *buf, fsinfo_t *fsopts)

usr.sbin/makefs/ffs.c

917

ffs_write_inode(union dinode *dp, uint32_t ino, const fsinfo_t *fsopts)

usr.sbin/makefs/ffs.c

927

uint32_t initediblk;

usr.sbin/makefs/ffs.c

973

(uint32_t)(cgino + INOPB(fs)) > initediblk &&

usr.sbin/makefs/ffs/ffs_subr.c

159

if ((uint32_t)end >= cgp->cg_nclusterblks)

usr.sbin/makefs/makefs.c

275

NUM(uint32_t);

usr.sbin/makefs/makefs.h

137

uint32_t curinode; /* current inode */

usr.sbin/makefs/makefs.h

81

uint32_t ino; /* inode number used on target fs */

usr.sbin/makefs/makefs.h

82

uint32_t nlink; /* number of links to this entry */

usr.sbin/makefs/makefs.h

93

uint32_t type; /* type of entry */

usr.sbin/makefs/msdos/denode.h

318

int msdosfs_fh_enter(struct msdosfsmount *, uint32_t, uint32_t, uint32_t *);

usr.sbin/makefs/msdos/denode.h

319

int msdosfs_fh_remove(struct msdosfsmount *, uint32_t, uint32_t);

usr.sbin/makefs/msdos/denode.h

320

int msdosfs_fh_lookup(struct msdosfsmount *, uint32_t, uint32_t, uint32_t *);

usr.sbin/makefs/msdos/mkfs_msdos.h

37

AOPT(uint32_t, block_size, 1) \

usr.sbin/makefs/msdos/mkfs_msdos.h

45

AOPT(uint32_t, hidden_sectors, 0) \

usr.sbin/makefs/msdos/mkfs_msdos.h

53

AOPT(uint32_t, sectors_per_fat, 1) \

usr.sbin/makefs/msdos/mkfs_msdos.h

55

AOPT(uint32_t, size, 1) \

usr.sbin/makefs/msdos/mkfs_msdos.h

56

AOPT(uint32_t, volume_id, 0) \

usr.sbin/makefs/msdos/mkfs_msdos.h

63

uint32_t volume_id_set:1;

usr.sbin/makefs/msdos/mkfs_msdos.h

64

uint32_t media_descriptor_set:1;

usr.sbin/makefs/msdos/mkfs_msdos.h

65

uint32_t hidden_sectors_set:1;

usr.sbin/makefs/msdos/msdosfs_conv.c

100

uint32_t year;

usr.sbin/makefs/msdos/msdosfs_conv.c

101

uint32_t month;

usr.sbin/makefs/msdos/msdosfs_conv.c

85

uint32_t lastday;

usr.sbin/makefs/msdos/msdosfs_conv.c

98

uint32_t days;

usr.sbin/makefs/msdos/msdosfs_conv.c

99

uint32_t inc;

usr.sbin/mkuboot/mkuboot.c

151

uint32_t fsize;

usr.sbin/mkuboot/mkuboot.c

59

uint32_t ih_magic;

usr.sbin/mkuboot/mkuboot.c

60

uint32_t ih_hcrc;

usr.sbin/mkuboot/mkuboot.c

61

uint32_t ih_time;

usr.sbin/mkuboot/mkuboot.c

62

uint32_t ih_size;

usr.sbin/mkuboot/mkuboot.c

63

uint32_t ih_load;

usr.sbin/mkuboot/mkuboot.c

64

uint32_t ih_ep;

usr.sbin/mkuboot/mkuboot.c

65

uint32_t ih_dcrc;

usr.sbin/mopd/common/file.c

1161

uint32_t secoff;

usr.sbin/mopd/common/file.c

503

uint32_t e_machine, e_entry;

usr.sbin/mopd/common/file.c

504

uint32_t e_phoff, e_phentsize, e_phnum;

usr.sbin/mopd/common/file.c

693

uint32_t e_machine;

usr.sbin/mopd/common/file.c

694

uint32_t e_phentsize, e_phnum;

usr.sbin/mopd/common/file.c

937

if (mid == (uint32_t)-1) {

usr.sbin/mopd/common/file.c

939

if (mid != (uint32_t)-1) {

usr.sbin/mopd/common/file.c

944

if (mid == (uint32_t)-1) {

usr.sbin/npppctl/npppctl.c

457

humanize_duration(uint32_t sec, char *buf, int lbuf)

usr.sbin/npppctl/npppctl.c

58

static const char *humanize_duration (uint32_t, char *, int);

usr.sbin/npppd/common/debugutil.c

124

vlog_printf(uint32_t prio, const char *format, va_list ap)

usr.sbin/npppd/common/debugutil.c

231

status = vlog_printf((uint32_t)prio, fmt, ap);

usr.sbin/npppd/common/debugutil.h

65

int vlog_printf (uint32_t, const char *, va_list);

usr.sbin/npppd/common/hash.c

40

uint32_t (*hash_func) (const void *, int), int hsz)

usr.sbin/npppd/common/hash.h

43

uint32_t (*hash) (const void *, int);

usr.sbin/npppd/common/hash.h

53

hash_table *hash_create(int (*)(const void *, const void *), uint32_t (*) (const void *, int), int);

usr.sbin/npppd/common/net_utils.c

172

netmask2prefixlen(uint32_t mask)

usr.sbin/npppd/common/net_utils.h

36

int netmask2prefixlen(uint32_t);

usr.sbin/npppd/l2tp/l2tp.h

333

uint32_t

usr.sbin/npppd/l2tp/l2tp.h

438

uint32_t /** Sequencing required */

usr.sbin/npppd/l2tp/l2tp_call.c

479

uint32_t framing_type = 0;

usr.sbin/npppd/l2tp/l2tp_call.c

738

uint32_t val32;

usr.sbin/npppd/l2tp/l2tp_subr.h

60

static inline uint32_t

usr.sbin/npppd/l2tp/l2tp_subr.h

75

avp_set_val32(struct l2tp_avp *avp, uint32_t val)

usr.sbin/npppd/l2tp/l2tp_subr.h

89

static inline uint32_t

usr.sbin/npppd/l2tp/l2tpd.c

75

static inline uint32_t short_hash (const void *, int);

usr.sbin/npppd/npppd/ccp.c

117

uint32_t peer_bits, our_bits;

usr.sbin/npppd/npppd/ccp.c

286

uint32_t peer_bits, our_bits;

usr.sbin/npppd/npppd/chap.c

125

static void chap_log (chap *, uint32_t, const char *, ...) __printflike(3,4);

usr.sbin/npppd/npppd/chap.c

956

chap_log(chap *_this, uint32_t prio, const char *fmt, ...)

usr.sbin/npppd/npppd/fsm.c

760

fsm_log(fsm *f, uint32_t prio, const char *fmt, ...)

usr.sbin/npppd/npppd/fsm.h

162

void fsm_log(fsm *, uint32_t, const char *, ...) __attribute__((__format__ (__printf__, 3, 4)));

usr.sbin/npppd/npppd/lcp.c

1000

uint32_t magic;

usr.sbin/npppd/npppd/lcp.c

1179

uint32_t magic;

usr.sbin/npppd/npppd/lcp.c

429

uint32_t magic;

usr.sbin/npppd/npppd/mppe.c

250

uint32_t

usr.sbin/npppd/npppd/mppe.c

251

mppe_create_our_bits(mppe *_this, uint32_t peer_bits)

usr.sbin/npppd/npppd/mppe.c

253

uint32_t our_bits;

usr.sbin/npppd/npppd/mppe.c

523

mppe_log(mppe *_this, uint32_t prio, const char *fmt, ...)

usr.sbin/npppd/npppd/mppe.c

536

mppe_bits_to_string(uint32_t bits)

usr.sbin/npppd/npppd/mppe.c

83

static const char *mppe_bits_to_string(uint32_t);

usr.sbin/npppd/npppd/mppe.c

84

static void mppe_log(mppe *, uint32_t, const char *, ...) __printflike(3,4);

usr.sbin/npppd/npppd/npppd.c

113

static uint32_t str_hash(const void *, int);

usr.sbin/npppd/npppd/npppd.c

1525

npppd_assign_ip_addr(npppd *_this, npppd_ppp *ppp, uint32_t req_ip4)

usr.sbin/npppd/npppd/npppd.c

1527

uint32_t ip4, ip4mask;

usr.sbin/npppd/npppd/npppd.c

1984

static uint32_t

usr.sbin/npppd/npppd/npppd.c

1987

uint32_t hash = 0;

usr.sbin/npppd/npppd/npppd.c

94

static uint32_t str_hash(const void *, int);

usr.sbin/npppd/npppd/npppd.h

313

int npppd_assign_ip_addr(npppd *, npppd_ppp *, uint32_t);

usr.sbin/npppd/npppd/npppd.h

352

int npppd_ctl_add_started_ppp_id(struct npppd_ctl *, uint32_t);

usr.sbin/npppd/npppd/npppd_auth_local.h

38

uint32_t

usr.sbin/npppd/npppd/npppd_ctl.h

60

uint32_t duration_sec; /** Elapsed time */

usr.sbin/npppd/npppd/npppd_ctl.h

74

uint32_t ipackets; /** Numbers of input packets */

usr.sbin/npppd/npppd/npppd_ctl.h

75

uint32_t opackets; /** Numbers of output packets */

usr.sbin/npppd/npppd/npppd_ctl.h

76

uint32_t ierrors; /** Numbers of input error packets */

usr.sbin/npppd/npppd/npppd_ctl.h

77

uint32_t oerrors; /** Numbers of output error packets */

usr.sbin/npppd/npppd/npppd_iface.c

506

uint32_t af;

usr.sbin/npppd/npppd/npppd_iface.c

520

if (lpktp < sizeof(uint32_t)) {

usr.sbin/npppd/npppd/npppd_iface.c

525

lpktp -= sizeof(uint32_t);

usr.sbin/npppd/npppd/npppd_iface.c

545

uint32_t th;

usr.sbin/npppd/npppd/npppd_local.h

145

uint32_t boot_id;

usr.sbin/npppd/npppd/npppd_local.h

163

uint32_t secs;

usr.sbin/npppd/npppd/npppd_pool.c

280

uint32_t

usr.sbin/npppd/npppd/npppd_pool.c

296

if ((uint32_t)result == SHUFLLE_MARK) {

usr.sbin/npppd/npppd/npppd_pool.c

315

switch (npppd_pool_get_assignability(_this, (uint32_t)result,

usr.sbin/npppd/npppd/npppd_pool.c

319

return (uint32_t)result;

usr.sbin/npppd/npppd/npppd_pool.c

338

return (uint32_t)0;

usr.sbin/npppd/npppd/npppd_pool.c

342

npppd_is_ifcace_ip4addr(npppd *_this, uint32_t ip4addr)

usr.sbin/npppd/npppd/npppd_pool.c

360

uint32_t ip4;

usr.sbin/npppd/npppd/npppd_pool.c

479

npppd_pool_get_assignability(npppd_pool *_this, uint32_t ip4addr,

usr.sbin/npppd/npppd/npppd_pool.c

480

uint32_t ip4mask, struct sockaddr_npppd **psnp)

usr.sbin/npppd/npppd/npppd_pool.c

543

is_valid_host_address(uint32_t addr)

usr.sbin/npppd/npppd/npppd_pool.c

75

static int is_valid_host_address (uint32_t);

usr.sbin/npppd/npppd/npppd_pool.h

49

int npppd_pool_get_assignability (npppd_pool *, uint32_t, uint32_t, struct sockaddr_npppd **);

usr.sbin/npppd/npppd/npppd_pool.h

50

uint32_t npppd_pool_get_dynamic (npppd_pool *, npppd_ppp *);

usr.sbin/npppd/npppd/npppd_radius.c

324

(uint32_t)(ppp->ibytes & 0xFFFFFFFFU)); /* LSB 32bit */

usr.sbin/npppd/npppd/npppd_radius.c

328

(uint32_t)(ppp->obytes & 0xFFFFFFFFU)); /* LSB 32bit */

usr.sbin/npppd/npppd/npppd_radius.c

705

uint32_t cause = 0;

usr.sbin/npppd/npppd/npppd_subr.c

133

struct in_addr *gate, int mtu, const char *ifname, uint32_t rtm_flags)

usr.sbin/npppd/npppd/npppd_subr.c

288

const char *ifname, uint32_t rtm_flags, int mtu)

usr.sbin/npppd/npppd/npppd_subr.c

296

struct in_addr *gate, uint32_t rtm_flags)

usr.sbin/npppd/npppd/npppd_subr.c

63

static int in_route0(int, struct in_addr *, struct in_addr *, struct in_addr *, int, const char *, uint32_t);

usr.sbin/npppd/npppd/npppd_subr.h

38

int in_route_add (struct in_addr *, struct in_addr *, struct in_addr *, const char *, uint32_t, int);

usr.sbin/npppd/npppd/npppd_subr.h

39

int in_route_delete (struct in_addr *, struct in_addr *, struct in_addr *, uint32_t);

usr.sbin/npppd/npppd/pap.c

266

pap_log(pap *_this, uint32_t prio, const char *fmt, ...)

usr.sbin/npppd/npppd/pap.c

89

static void pap_log (pap *, uint32_t, const char *, ...) __printflike(3,4);

usr.sbin/npppd/npppd/ppp.c

1102

static uint32_t

usr.sbin/npppd/npppd/ppp.c

84

static uint32_t ppp_proto_bit(int);

usr.sbin/npppd/npppd/ppp.h

245

uint32_t lastauth;

usr.sbin/npppd/npppd/ppp.h

247

uint32_t magic_number;

usr.sbin/npppd/npppd/ppp.h

250

uint32_t peer_magic_number;

usr.sbin/npppd/npppd/ppp.h

276

uint32_t xxxmru;

usr.sbin/npppd/npppd/ppp.h

281

uint32_t /** doing dialin proxy */

usr.sbin/npppd/npppd/ppp.h

292

uint32_t state;

usr.sbin/npppd/npppd/ppp.h

311

uint32_t state;

usr.sbin/npppd/npppd/ppp.h

325

uint32_t state;

usr.sbin/npppd/npppd/ppp.h

349

uint32_t mppe_o_bits;

usr.sbin/npppd/npppd/ppp.h

350

uint32_t mppe_p_bits;

usr.sbin/npppd/npppd/ppp.h

578

uint32_t ipackets;

usr.sbin/npppd/npppd/ppp.h

580

uint32_t opackets;

usr.sbin/npppd/npppd/ppp.h

582

uint32_t ierrors;

usr.sbin/npppd/npppd/ppp.h

584

uint32_t oerrors;

usr.sbin/npppd/npppd/ppp.h

624

uint32_t auth_type;

usr.sbin/npppd/npppd/ppp.h

818

uint32_t mppe_create_our_bits (mppe *, uint32_t);

usr.sbin/npppd/npppd/radius_req.c

100

uint32_t ival;

usr.sbin/npppd/pppoe/pppoe.h

145

uint32_t acookie_next;

usr.sbin/npppd/pppoe/pppoe.h

148

uint32_t

usr.sbin/npppd/pppoe/pppoe_session.c

385

_this->acookie = *(uint32_t *)(ac_cookie->value);

usr.sbin/npppd/pppoe/pppoed.c

1108

static uint32_t

usr.sbin/npppd/pppoe/pppoed.c

119

(uint32_t (*) (const void *, int))session_id_hash,

usr.sbin/npppd/pppoe/pppoed.c

137

(uint32_t (*) (const void *, int))session_id_hash,

usr.sbin/npppd/pppoe/pppoed.c

93

static uint32_t session_id_hash (void *, size_t);

usr.sbin/npppd/pppoe/pppoed.c

974

tlv.length = ntohs(sizeof(uint32_t));

usr.sbin/npppd/pppoe/pppoed.c

977

sizeof(uint32_t));

usr.sbin/npppd/pptp/pptp.h

249

uint32_t /* flags */

usr.sbin/npppd/pptp/pptp.h

289

uint32_t echo_seq; /* identifier of Echo Request */

usr.sbin/npppd/pptp/pptp.h

307

uint32_t snd_una; /* next ack notification */

usr.sbin/npppd/pptp/pptp.h

308

uint32_t snd_nxt; /* next transmit sequence # */

usr.sbin/npppd/pptp/pptp.h

310

uint32_t rcv_nxt; /* received sequence # */

usr.sbin/npppd/pptp/pptp.h

311

uint32_t rcv_acked; /* latest acked received sequence # */

usr.sbin/npppd/pptp/pptp.h

351

void pptp_call_gre_input (pptp_call *, uint32_t, uint32_t, int, u_char *, int);

usr.sbin/npppd/pptp/pptp_call.c

470

pptp_call_gre_input(pptp_call *_this, uint32_t seq, uint32_t ack,

usr.sbin/npppd/pptp/pptp_call.c

597

PPTP_CALL_ASSERT(ALIGNED_POINTER(opkt, uint32_t));

usr.sbin/npppd/pptp/pptp_call.c

600

*(uint32_t *)opkt = htonl(_this->snd_nxt++);

usr.sbin/npppd/pptp/pptp_call.c

606

*(uint32_t *)opkt = htonl(_this->rcv_nxt - 1);

usr.sbin/npppd/pptp/pptp_local.h

111

uint32_t connect_speed;

usr.sbin/npppd/pptp/pptp_local.h

114

uint32_t physical_channel_id;

usr.sbin/npppd/pptp/pptp_local.h

120

uint32_t identifier;

usr.sbin/npppd/pptp/pptp_local.h

126

uint32_t identifier;

usr.sbin/npppd/pptp/pptp_local.h

137

uint32_t send_accm;

usr.sbin/npppd/pptp/pptp_local.h

138

uint32_t recv_accm;

usr.sbin/npppd/pptp/pptp_local.h

67

uint32_t magic_cookie;

usr.sbin/npppd/pptp/pptp_local.h

78

uint32_t framing_caps;

usr.sbin/npppd/pptp/pptp_local.h

79

uint32_t bearer_caps;

usr.sbin/npppd/pptp/pptp_local.h

91

uint32_t maximum_bps;

usr.sbin/npppd/pptp/pptp_local.h

92

uint32_t minimum_bps;

usr.sbin/npppd/pptp/pptp_local.h

93

uint32_t bearer_type;

usr.sbin/npppd/pptp/pptp_local.h

94

uint32_t framing_type;

usr.sbin/npppd/pptp/pptp_subr.c

49

pptp_framing_string(uint32_t bits)

usr.sbin/npppd/pptp/pptp_subr.c

66

pptp_bearer_string(uint32_t bits)

usr.sbin/npppd/pptp/pptp_subr.h

34

const char *pptp_framing_string (uint32_t);

usr.sbin/npppd/pptp/pptp_subr.h

35

const char *pptp_bearer_string (uint32_t);

usr.sbin/npppd/pptp/pptpd.c

687

uint32_t seq, ack, call_id;

usr.sbin/npppd/pptp/pptpd.c

764

seq = ntohl(*(uint32_t *)pkt);

usr.sbin/npppd/pptp/pptpd.c

775

ack = ntohl(*(uint32_t *)pkt);

usr.sbin/npppd/pptp/pptpd.c

91

static uint32_t pptp_call_hash (const void *, int);

usr.sbin/npppd/pptp/pptpd.c

917

static uint32_t

usr.sbin/nsd/buffer.h

334

buffer_write_u32_at(buffer_type *buffer, size_t at, uint32_t data)

usr.sbin/nsd/buffer.h

341

buffer_write_u32(buffer_type *buffer, uint32_t data)

usr.sbin/nsd/buffer.h

398

try_buffer_write_u32_at(buffer_type *buffer, size_t at, uint32_t data)

usr.sbin/nsd/buffer.h

407

try_buffer_write_u32(buffer_type *buffer, uint32_t data)

usr.sbin/nsd/buffer.h

477

static inline uint32_t

usr.sbin/nsd/buffer.h

480

assert(buffer_available_at(buffer, at, sizeof(uint32_t)));

usr.sbin/nsd/buffer.h

484

static inline uint32_t

usr.sbin/nsd/buffer.h

487

uint32_t result = buffer_read_u32_at(buffer, buffer->_position);

usr.sbin/nsd/buffer.h

488

buffer->_position += sizeof(uint32_t);

usr.sbin/nsd/difffile.c

107

diff_write_commit(const char* zone, uint32_t old_serial, uint32_t new_serial,

usr.sbin/nsd/difffile.c

108

uint32_t num_parts, uint8_t commit, const char* log_str,

usr.sbin/nsd/difffile.c

1160

apply_ixfr(nsd_type* nsd, FILE *in, uint32_t serialno,

usr.sbin/nsd/difffile.c

1161

uint32_t seq_nr, uint32_t seq_total,

usr.sbin/nsd/difffile.c

1166

uint32_t msglen, checklen, pkttype;

usr.sbin/nsd/difffile.c

1255

uint32_t ttl;

usr.sbin/nsd/difffile.c

1284

uint32_t serial;

usr.sbin/nsd/difffile.c

1288

buffer_remaining(packet) < sizeof(uint32_t) * 5)

usr.sbin/nsd/difffile.c

134

!write_32(df, (uint32_t) tv.tv_usec) ||

usr.sbin/nsd/difffile.c

1442

check_for_bad_serial(namedb_type* db, const char* zone_str, uint32_t old_serial)

usr.sbin/nsd/difffile.c

1454

uint32_t memserial = 0;

usr.sbin/nsd/difffile.c

1467

struct nsd_options* ATTR_UNUSED(opt), udb_base* taskudb, uint32_t xfrfilenr)

usr.sbin/nsd/difffile.c

1473

uint32_t old_serial, new_serial, num_parts, type;

usr.sbin/nsd/difffile.c

1475

uint32_t time_end_1, time_start_1;

usr.sbin/nsd/difffile.c

1477

uint32_t i;

usr.sbin/nsd/difffile.c

1685

sz += sizeof(uint32_t)*6 + sizeof(uint8_t)*2

usr.sbin/nsd/difffile.c

1701

uint32_t ttl = htonl(z->soa_rrset->rrs[0]->ttl);

usr.sbin/nsd/difffile.c

1704

memmove(p, &ttl, sizeof(uint32_t));

usr.sbin/nsd/difffile.c

1705

p += sizeof(uint32_t);

usr.sbin/nsd/difffile.c

1715

sizeof(uint32_t)*5);

usr.sbin/nsd/difffile.c

1901

TASKLIST(&e)->newserial = (uint32_t) answer_cookie;

usr.sbin/nsd/difffile.c

1982

TASKLIST(&e)->oldserial = (uint32_t)sz;

usr.sbin/nsd/difffile.c

1988

uint32_t old_serial, uint32_t new_serial, uint64_t filenumber)

usr.sbin/nsd/difffile.c

203

diff_read_32(FILE *in, uint32_t* result)

usr.sbin/nsd/difffile.c

226

uint32_t disklen;

usr.sbin/nsd/difffile.c

37

write_32(FILE *out, uint32_t val)

usr.sbin/nsd/difffile.c

52

uint32_t len = strlen(str);

usr.sbin/nsd/difffile.c

59

diff_write_packet(const char* zone, const char* pat, uint32_t old_serial,

usr.sbin/nsd/difffile.c

60

uint32_t new_serial, uint32_t seq_nr, uint8_t* data, size_t len,

usr.sbin/nsd/difffile.c

704

uint16_t type, uint16_t klass, uint32_t ttl,

usr.sbin/nsd/difffile.c

81

!write_32(df, (uint32_t) tv.tv_usec) ||

usr.sbin/nsd/difffile.c

85

!write_32(df, (uint32_t) tv.tv_usec) ||

usr.sbin/nsd/difffile.c

949

uint16_t type, uint16_t klass, uint32_t ttl,

usr.sbin/nsd/difffile.h

120

uint32_t size; /* size of this struct */

usr.sbin/nsd/difffile.h

125

uint32_t oldserial, newserial;

usr.sbin/nsd/difffile.h

157

uint32_t old_serial, uint32_t new_serial, uint64_t filenumber);

usr.sbin/nsd/difffile.h

32

void diff_write_packet(const char* zone, const char* pat, uint32_t old_serial,

usr.sbin/nsd/difffile.h

33

uint32_t new_serial, uint32_t seq_nr, uint8_t* data, size_t len,

usr.sbin/nsd/difffile.h

40

void diff_write_commit(const char* zone, uint32_t old_serial,

usr.sbin/nsd/difffile.h

41

uint32_t new_serial, uint32_t num_parts, uint8_t commit,

usr.sbin/nsd/difffile.h

54

int diff_read_32(FILE *in, uint32_t* result);

usr.sbin/nsd/difffile.h

62

uint16_t type, uint16_t klass, uint32_t ttl,

usr.sbin/nsd/difffile.h

68

uint16_t type, uint16_t klass, uint32_t ttl,

usr.sbin/nsd/difffile.h

75

struct nsd_options* opt, udb_base* taskudb, uint32_t xfrfilenr);

usr.sbin/nsd/dns.h

204

(MAXDOMAINLEN + sizeof(uint32_t) + 4*sizeof(uint16_t) + MAX_RDLENGTH)

usr.sbin/nsd/dnstap/dnstap.c

713

uint32_t *time_nsec, protobuf_c_boolean *has_time_nsec)

usr.sbin/nsd/dnstap/dnstap.c

742

uint32_t *rport, protobuf_c_boolean *has_rport,

usr.sbin/nsd/dnstap/dnstap.c

744

uint32_t *qport, protobuf_c_boolean *has_qport)

usr.sbin/nsd/edns.c

211

compare_1982(uint32_t a, uint32_t b)

usr.sbin/nsd/edns.c

214

const uint32_t cutoff = ((uint32_t) 1 << (32 - 1));

usr.sbin/nsd/edns.c

227

static uint32_t

usr.sbin/nsd/edns.c

228

subtract_1982(uint32_t a, uint32_t b)

usr.sbin/nsd/edns.c

231

const uint32_t cutoff = ((uint32_t) 1 << (32 - 1));

usr.sbin/nsd/edns.c

239

return ((uint32_t)0xffffffff) - (a-b-1);

usr.sbin/nsd/edns.c

245

void cookie_verify(query_type *q, struct nsd* nsd, uint32_t *now_p) {

usr.sbin/nsd/edns.c

247

uint32_t cookie_time, now_uint32;

usr.sbin/nsd/edns.c

265

now_uint32 = *now_p ? *now_p : (*now_p = (uint32_t)time(NULL));

usr.sbin/nsd/edns.c

314

void cookie_create(query_type *q, struct nsd* nsd, uint32_t *now_p)

usr.sbin/nsd/edns.c

317

uint32_t now_uint32;

usr.sbin/nsd/edns.c

322

now_uint32 = *now_p ? *now_p : (*now_p = (uint32_t)time(NULL));

usr.sbin/nsd/edns.h

108

void cookie_verify(struct query *q, struct nsd* nsd, uint32_t *now_p);

usr.sbin/nsd/edns.h

109

void cookie_create(struct query *q, struct nsd* nsd, uint32_t *now_p);

usr.sbin/nsd/ipc.c

608

uint32_t acl_num;

usr.sbin/nsd/ixfr.c

1087

uint32_t* serial, uint32_t* refresh, uint32_t* retry,

usr.sbin/nsd/ixfr.c

1088

uint32_t* expire, uint32_t* minimum, size_t* sz)

usr.sbin/nsd/ixfr.c

1114

static void store_soa(uint8_t* soa, struct zone* zone, uint32_t ttl,

usr.sbin/nsd/ixfr.c

1116

uint8_t* email, int email_len, uint32_t serial, uint32_t refresh,

usr.sbin/nsd/ixfr.c

1117

uint32_t retry, uint32_t expire, uint32_t minimum)

usr.sbin/nsd/ixfr.c

1146

void ixfr_store_add_newsoa(struct ixfr_store* ixfr_store, uint32_t ttl,

usr.sbin/nsd/ixfr.c

1150

uint32_t serial, refresh, retry, expire, minimum;

usr.sbin/nsd/ixfr.c

1195

void ixfr_store_add_oldsoa(struct ixfr_store* ixfr_store, uint32_t ttl,

usr.sbin/nsd/ixfr.c

1199

uint32_t serial, refresh, retry, expire, minimum;

usr.sbin/nsd/ixfr.c

1364

uint16_t klass, uint32_t ttl, uint8_t* rdata, size_t rdata_len,

usr.sbin/nsd/ixfr.c

1398

uint32_t ttl, uint8_t* rdata, size_t rdata_len)

usr.sbin/nsd/ixfr.c

1428

uint32_t ttl, uint8_t* rdata, size_t rdata_len)

usr.sbin/nsd/ixfr.c

1430

uint32_t serial;

usr.sbin/nsd/ixfr.c

1463

uint32_t* serial_x = (uint32_t*)x;

usr.sbin/nsd/ixfr.c

1464

uint32_t* serial_y = (uint32_t*)y;

usr.sbin/nsd/ixfr.c

1611

uint32_t qserial)

usr.sbin/nsd/ixfr.c

1722

int file_num, uint32_t* oldserial, uint32_t* newserial,

usr.sbin/nsd/ixfr.c

1943

uint32_t ttl;

usr.sbin/nsd/ixfr.c

2296

uint32_t dest_serial)

usr.sbin/nsd/ixfr.c

2346

uint32_t* dest_serial)

usr.sbin/nsd/ixfr.c

2434

uint32_t *dest_serial;

usr.sbin/nsd/ixfr.c

2444

uint32_t ttl,

usr.sbin/nsd/ixfr.c

2537

uint32_t category,

usr.sbin/nsd/ixfr.c

2555

const char* ixfrfile, uint32_t* dest_serial, int file_num)

usr.sbin/nsd/ixfr.c

2646

const char* zfile, int num_files, uint32_t *dest_serial)

usr.sbin/nsd/ixfr.c

2660

uint32_t serial;

usr.sbin/nsd/ixfr.c

437

static int parse_qserial(struct buffer* packet, uint32_t* qserial,

usr.sbin/nsd/ixfr.c

483

static uint32_t soa_rdata_get_serial(uint8_t* rdata, uint16_t rdlength)

usr.sbin/nsd/ixfr.c

491

static uint32_t soa_rr_get_serial(struct rr* rr)

usr.sbin/nsd/ixfr.c

497

uint32_t zone_get_current_serial(struct zone* zone)

usr.sbin/nsd/ixfr.c

611

uint32_t* end_serial)

usr.sbin/nsd/ixfr.c

766

uint32_t qserial = 0, current_serial = 0, end_serial = 0;

usr.sbin/nsd/ixfr.h

170

void ixfr_store_add_newsoa(struct ixfr_store* ixfr_store, uint32_t ttl,

usr.sbin/nsd/ixfr.h

181

void ixfr_store_add_oldsoa(struct ixfr_store* ixfr_store, uint32_t ttl,

usr.sbin/nsd/ixfr.h

190

uint32_t ttl, uint8_t* rdata, size_t rdata_len);

usr.sbin/nsd/ixfr.h

195

uint32_t ttl, uint8_t* rdata, size_t rdata_len);

usr.sbin/nsd/ixfr.h

222

uint32_t qserial);

usr.sbin/nsd/ixfr.h

234

uint32_t zone_get_current_serial(struct zone* zone);

usr.sbin/nsd/ixfr.h

249

int file_num, uint32_t* oldserial, uint32_t* newserial,

usr.sbin/nsd/ixfr.h

36

uint32_t oldest_serial;

usr.sbin/nsd/ixfr.h

40

uint32_t newest_serial;

usr.sbin/nsd/ixfr.h

61

uint32_t oldserial;

usr.sbin/nsd/ixfr.h

63

uint32_t newserial;

usr.sbin/nsd/ixfrcreate.c

1010

uint32_t ixfr_number)

usr.sbin/nsd/ixfrcreate.c

1079

uint32_t old_serial;

usr.sbin/nsd/ixfrcreate.c

124

uint32_t count = domain_count_rrsets(domain, zone);

usr.sbin/nsd/ixfrcreate.c

144

uint32_t serial)

usr.sbin/nsd/ixfrcreate.c

244

static int read_spool_u32(FILE* spool, uint32_t* val)

usr.sbin/nsd/ixfrcreate.c

275

uint32_t serial;

usr.sbin/nsd/ixfrcreate.c

30

static int spool_u32(FILE* out, uint32_t val)

usr.sbin/nsd/ixfrcreate.c

306

size_t dname_len, uint16_t tp, uint16_t kl, uint32_t ttl, uint8_t* buf,

usr.sbin/nsd/ixfrcreate.c

332

static int rrset_find_rdata(struct rrset* rrset, uint32_t ttl, uint8_t* rdata,

usr.sbin/nsd/ixfrcreate.c

371

uint32_t ttl;

usr.sbin/nsd/ixfrcreate.c

440

uint32_t ttl;

usr.sbin/nsd/ixfrcreate.c

516

uint32_t spool_type_count, i;

usr.sbin/nsd/ixfrcreate.c

585

uint32_t spool_type_count, i;

usr.sbin/nsd/ixfrcreate.c

801

uint32_t count = domain_count_rrsets(domain, zone);

usr.sbin/nsd/ixfrcreate.c

826

const char* zfile, int checknew, uint32_t old_serial,

usr.sbin/nsd/ixfrcreate.c

827

uint32_t new_serial)

usr.sbin/nsd/ixfrcreate.c

829

uint32_t file_oldserial = 0, file_newserial = 0;

usr.sbin/nsd/ixfrcreate.c

849

uint32_t file_oldserial = 0, file_newserial = 0;

usr.sbin/nsd/ixfrcreate.c

912

const char* zoptsname, const char* zfile, uint32_t ixfr_number,

usr.sbin/nsd/ixfrcreate.c

948

struct nsd* nsd, const char* zfile, uint32_t ixfr_number)

usr.sbin/nsd/ixfrcreate.h

20

uint32_t old_serial, new_serial;

usr.sbin/nsd/ixfrcreate.h

47

uint32_t ixfr_number);

usr.sbin/nsd/lookup3.c

1005

ref = hashlittle(b, len, (uint32_t)1);

usr.sbin/nsd/lookup3.c

1008

x = hashlittle(b, len, (uint32_t)1);

usr.sbin/nsd/lookup3.c

1009

y = hashlittle(b, len, (uint32_t)1);

usr.sbin/nsd/lookup3.c

1023

uint32_t h,i,state[HASHSTATE];

usr.sbin/nsd/lookup3.c

107

#define hashsize(n) ((uint32_t)1<<(n))

usr.sbin/nsd/lookup3.c

214

uint32_t hashword(

usr.sbin/nsd/lookup3.c

215

const uint32_t *k, /* the key, an array of uint32_t values */

usr.sbin/nsd/lookup3.c

217

uint32_t initval) /* the previous hash, or an arbitrary value */

usr.sbin/nsd/lookup3.c

219

uint32_t a,b,c;

usr.sbin/nsd/lookup3.c

222

a = b = c = raninit + (((uint32_t)length)<<2) + initval;

usr.sbin/nsd/lookup3.c

263

const uint32_t *k, /* the key, an array of uint32_t values */

usr.sbin/nsd/lookup3.c

265

uint32_t *pc, /* IN: seed OUT: primary hash value */

usr.sbin/nsd/lookup3.c

266

uint32_t *pb) /* IN: more seed OUT: secondary hash value */

usr.sbin/nsd/lookup3.c

268

uint32_t a,b,c;

usr.sbin/nsd/lookup3.c

271

a = b = c = raninit + ((uint32_t)(length<<2)) + *pc;

usr.sbin/nsd/lookup3.c

328

uint32_t hashlittle( const void *key, size_t length, uint32_t initval)

usr.sbin/nsd/lookup3.c

330

uint32_t a,b,c; /* internal state */

usr.sbin/nsd/lookup3.c

334

a = b = c = raninit + ((uint32_t)length) + initval;

usr.sbin/nsd/lookup3.c

338

const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */

usr.sbin/nsd/lookup3.c

389

case 11: c+=((uint32_t)k8[10])<<16; /* fall through */

usr.sbin/nsd/lookup3.c

390

case 10: c+=((uint32_t)k8[9])<<8; /* fall through */

usr.sbin/nsd/lookup3.c

393

case 7 : b+=((uint32_t)k8[6])<<16; /* fall through */

usr.sbin/nsd/lookup3.c

394

case 6 : b+=((uint32_t)k8[5])<<8; /* fall through */

usr.sbin/nsd/lookup3.c

397

case 3 : a+=((uint32_t)k8[2])<<16; /* fall through */

usr.sbin/nsd/lookup3.c

398

case 2 : a+=((uint32_t)k8[1])<<8; /* fall through */

usr.sbin/nsd/lookup3.c

412

a += k[0] + (((uint32_t)k[1])<<16);

usr.sbin/nsd/lookup3.c

413

b += k[2] + (((uint32_t)k[3])<<16);

usr.sbin/nsd/lookup3.c

414

c += k[4] + (((uint32_t)k[5])<<16);

usr.sbin/nsd/lookup3.c

424

case 12: c+=k[4]+(((uint32_t)k[5])<<16);

usr.sbin/nsd/lookup3.c

425

b+=k[2]+(((uint32_t)k[3])<<16);

usr.sbin/nsd/lookup3.c

426

a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/nsd/lookup3.c

428

case 11: c+=((uint32_t)k8[10])<<16; /* fall through */

usr.sbin/nsd/lookup3.c

430

b+=k[2]+(((uint32_t)k[3])<<16);

usr.sbin/nsd/lookup3.c

431

a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/nsd/lookup3.c

434

case 8 : b+=k[2]+(((uint32_t)k[3])<<16);

usr.sbin/nsd/lookup3.c

435

a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/nsd/lookup3.c

437

case 7 : b+=((uint32_t)k8[6])<<16; /* fall through */

usr.sbin/nsd/lookup3.c

439

a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/nsd/lookup3.c

442

case 4 : a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/nsd/lookup3.c

444

case 3 : a+=((uint32_t)k8[2])<<16; /* fall through */

usr.sbin/nsd/lookup3.c

459

a += ((uint32_t)k[1])<<8;

usr.sbin/nsd/lookup3.c

460

a += ((uint32_t)k[2])<<16;

usr.sbin/nsd/lookup3.c

461

a += ((uint32_t)k[3])<<24;

usr.sbin/nsd/lookup3.c

463

b += ((uint32_t)k[5])<<8;

usr.sbin/nsd/lookup3.c

464

b += ((uint32_t)k[6])<<16;

usr.sbin/nsd/lookup3.c

465

b += ((uint32_t)k[7])<<24;

usr.sbin/nsd/lookup3.c

467

c += ((uint32_t)k[9])<<8;

usr.sbin/nsd/lookup3.c

468

c += ((uint32_t)k[10])<<16;

usr.sbin/nsd/lookup3.c

469

c += ((uint32_t)k[11])<<24;

usr.sbin/nsd/lookup3.c

478

case 12: c+=((uint32_t)k[11])<<24;

usr.sbin/nsd/lookup3.c

480

case 11: c+=((uint32_t)k[10])<<16;

usr.sbin/nsd/lookup3.c

482

case 10: c+=((uint32_t)k[9])<<8;

usr.sbin/nsd/lookup3.c

486

case 8 : b+=((uint32_t)k[7])<<24;

usr.sbin/nsd/lookup3.c

488

case 7 : b+=((uint32_t)k[6])<<16;

usr.sbin/nsd/lookup3.c

490

case 6 : b+=((uint32_t)k[5])<<8;

usr.sbin/nsd/lookup3.c

494

case 4 : a+=((uint32_t)k[3])<<24;

usr.sbin/nsd/lookup3.c

496

case 3 : a+=((uint32_t)k[2])<<16;

usr.sbin/nsd/lookup3.c

498

case 2 : a+=((uint32_t)k[1])<<8;

usr.sbin/nsd/lookup3.c

525

uint32_t *pc, /* IN: primary initval, OUT: primary hash */

usr.sbin/nsd/lookup3.c

526

uint32_t *pb) /* IN: secondary initval, OUT: secondary hash */

usr.sbin/nsd/lookup3.c

528

uint32_t a,b,c; /* internal state */

usr.sbin/nsd/lookup3.c

532

a = b = c = raninit + ((uint32_t)length) + *pc;

usr.sbin/nsd/lookup3.c

537

const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */

usr.sbin/nsd/lookup3.c

588

case 11: c+=((uint32_t)k8[10])<<16; /* fall through */

usr.sbin/nsd/lookup3.c

589

case 10: c+=((uint32_t)k8[9])<<8; /* fall through */

usr.sbin/nsd/lookup3.c

592

case 7 : b+=((uint32_t)k8[6])<<16; /* fall through */

usr.sbin/nsd/lookup3.c

593

case 6 : b+=((uint32_t)k8[5])<<8; /* fall through */

usr.sbin/nsd/lookup3.c

596

case 3 : a+=((uint32_t)k8[2])<<16; /* fall through */

usr.sbin/nsd/lookup3.c

597

case 2 : a+=((uint32_t)k8[1])<<8; /* fall through */

usr.sbin/nsd/lookup3.c

611

a += k[0] + (((uint32_t)k[1])<<16);

usr.sbin/nsd/lookup3.c

612

b += k[2] + (((uint32_t)k[3])<<16);

usr.sbin/nsd/lookup3.c

613

c += k[4] + (((uint32_t)k[5])<<16);

usr.sbin/nsd/lookup3.c

623

case 12: c+=k[4]+(((uint32_t)k[5])<<16);

usr.sbin/nsd/lookup3.c

624

b+=k[2]+(((uint32_t)k[3])<<16);

usr.sbin/nsd/lookup3.c

625

a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/nsd/lookup3.c

627

case 11: c+=((uint32_t)k8[10])<<16; /* fall through */

usr.sbin/nsd/lookup3.c

629

b+=k[2]+(((uint32_t)k[3])<<16);

usr.sbin/nsd/lookup3.c

630

a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/nsd/lookup3.c

633

case 8 : b+=k[2]+(((uint32_t)k[3])<<16);

usr.sbin/nsd/lookup3.c

634

a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/nsd/lookup3.c

636

case 7 : b+=((uint32_t)k8[6])<<16; /* fall through */

usr.sbin/nsd/lookup3.c

638

a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/nsd/lookup3.c

641

case 4 : a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/nsd/lookup3.c

643

case 3 : a+=((uint32_t)k8[2])<<16; /* fall through */

usr.sbin/nsd/lookup3.c

658

a += ((uint32_t)k[1])<<8;

usr.sbin/nsd/lookup3.c

659

a += ((uint32_t)k[2])<<16;

usr.sbin/nsd/lookup3.c

660

a += ((uint32_t)k[3])<<24;

usr.sbin/nsd/lookup3.c

662

b += ((uint32_t)k[5])<<8;

usr.sbin/nsd/lookup3.c

663

b += ((uint32_t)k[6])<<16;

usr.sbin/nsd/lookup3.c

664

b += ((uint32_t)k[7])<<24;

usr.sbin/nsd/lookup3.c

666

c += ((uint32_t)k[9])<<8;

usr.sbin/nsd/lookup3.c

667

c += ((uint32_t)k[10])<<16;

usr.sbin/nsd/lookup3.c

668

c += ((uint32_t)k[11])<<24;

usr.sbin/nsd/lookup3.c

677

case 12: c+=((uint32_t)k[11])<<24;

usr.sbin/nsd/lookup3.c

678

case 11: c+=((uint32_t)k[10])<<16;

usr.sbin/nsd/lookup3.c

679

case 10: c+=((uint32_t)k[9])<<8;

usr.sbin/nsd/lookup3.c

681

case 8 : b+=((uint32_t)k[7])<<24;

usr.sbin/nsd/lookup3.c

682

case 7 : b+=((uint32_t)k[6])<<16;

usr.sbin/nsd/lookup3.c

683

case 6 : b+=((uint32_t)k[5])<<8;

usr.sbin/nsd/lookup3.c

685

case 4 : a+=((uint32_t)k[3])<<24;

usr.sbin/nsd/lookup3.c

686

case 3 : a+=((uint32_t)k[2])<<16;

usr.sbin/nsd/lookup3.c

687

case 2 : a+=((uint32_t)k[1])<<8;

usr.sbin/nsd/lookup3.c

69

static uint32_t raninit = 0xdeadbeef;

usr.sbin/nsd/lookup3.c

708

uint32_t hashbig( const void *key, size_t length, uint32_t initval)

usr.sbin/nsd/lookup3.c

710

uint32_t a,b,c;

usr.sbin/nsd/lookup3.c

714

a = b = c = raninit + ((uint32_t)length) + initval;

usr.sbin/nsd/lookup3.c

718

const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */

usr.sbin/nsd/lookup3.c

72

hash_set_raninit(uint32_t v)

usr.sbin/nsd/lookup3.c

769

case 11: c+=((uint32_t)k8[10])<<8; /* fall through */

usr.sbin/nsd/lookup3.c

770

case 10: c+=((uint32_t)k8[9])<<16; /* fall through */

usr.sbin/nsd/lookup3.c

771

case 9 : c+=((uint32_t)k8[8])<<24; /* fall through */

usr.sbin/nsd/lookup3.c

773

case 7 : b+=((uint32_t)k8[6])<<8; /* fall through */

usr.sbin/nsd/lookup3.c

774

case 6 : b+=((uint32_t)k8[5])<<16; /* fall through */

usr.sbin/nsd/lookup3.c

775

case 5 : b+=((uint32_t)k8[4])<<24; /* fall through */

usr.sbin/nsd/lookup3.c

777

case 3 : a+=((uint32_t)k8[2])<<8; /* fall through */

usr.sbin/nsd/lookup3.c

778

case 2 : a+=((uint32_t)k8[1])<<16; /* fall through */

usr.sbin/nsd/lookup3.c

779

case 1 : a+=((uint32_t)k8[0])<<24; break;

usr.sbin/nsd/lookup3.c

791

a += ((uint32_t)k[0])<<24;

usr.sbin/nsd/lookup3.c

792

a += ((uint32_t)k[1])<<16;

usr.sbin/nsd/lookup3.c

793

a += ((uint32_t)k[2])<<8;

usr.sbin/nsd/lookup3.c

794

a += ((uint32_t)k[3]);

usr.sbin/nsd/lookup3.c

795

b += ((uint32_t)k[4])<<24;

usr.sbin/nsd/lookup3.c

796

b += ((uint32_t)k[5])<<16;

usr.sbin/nsd/lookup3.c

797

b += ((uint32_t)k[6])<<8;

usr.sbin/nsd/lookup3.c

798

b += ((uint32_t)k[7]);

usr.sbin/nsd/lookup3.c

799

c += ((uint32_t)k[8])<<24;

usr.sbin/nsd/lookup3.c

800

c += ((uint32_t)k[9])<<16;

usr.sbin/nsd/lookup3.c

801

c += ((uint32_t)k[10])<<8;

usr.sbin/nsd/lookup3.c

802

c += ((uint32_t)k[11]);

usr.sbin/nsd/lookup3.c

812

case 11: c+=((uint32_t)k[10])<<8;

usr.sbin/nsd/lookup3.c

813

case 10: c+=((uint32_t)k[9])<<16;

usr.sbin/nsd/lookup3.c

814

case 9 : c+=((uint32_t)k[8])<<24;

usr.sbin/nsd/lookup3.c

816

case 7 : b+=((uint32_t)k[6])<<8;

usr.sbin/nsd/lookup3.c

817

case 6 : b+=((uint32_t)k[5])<<16;

usr.sbin/nsd/lookup3.c

818

case 5 : b+=((uint32_t)k[4])<<24;

usr.sbin/nsd/lookup3.c

820

case 3 : a+=((uint32_t)k[2])<<8;

usr.sbin/nsd/lookup3.c

821

case 2 : a+=((uint32_t)k[1])<<16;

usr.sbin/nsd/lookup3.c

822

case 1 : a+=((uint32_t)k[0])<<24;

usr.sbin/nsd/lookup3.c

840

uint32_t i;

usr.sbin/nsd/lookup3.c

841

uint32_t h=0;

usr.sbin/nsd/lookup3.c

862

uint32_t c[HASHSTATE], d[HASHSTATE], i=0, j=0, k, l, m=0, z;

usr.sbin/nsd/lookup3.c

863

uint32_t e[HASHSTATE],f[HASHSTATE],g[HASHSTATE],h[HASHSTATE];

usr.sbin/nsd/lookup3.c

864

uint32_t x[HASHSTATE],y[HASHSTATE];

usr.sbin/nsd/lookup3.c

865

uint32_t hlen;

usr.sbin/nsd/lookup3.c

878

e[l]=f[l]=g[l]=h[l]=x[l]=y[l]=~((uint32_t)0);

usr.sbin/nsd/lookup3.c

883

uint32_t finished=1;

usr.sbin/nsd/lookup3.c

932

uint32_t len;

usr.sbin/nsd/lookup3.c

934

uint32_t h;

usr.sbin/nsd/lookup3.c

936

uint32_t i;

usr.sbin/nsd/lookup3.c

938

uint32_t j;

usr.sbin/nsd/lookup3.c

940

uint32_t ref,x,y;

usr.sbin/nsd/lookup3.c

945

hashword((const uint32_t *)q, (sizeof(q)-1)/4, 13),

usr.sbin/nsd/lookup3.c

946

hashword((const uint32_t *)q, (sizeof(q)-5)/4, 13),

usr.sbin/nsd/lookup3.c

947

hashword((const uint32_t *)q, (sizeof(q)-9)/4, 13));

usr.sbin/nsd/lookup3.h

53

uint32_t hashword(const uint32_t *k, size_t length, uint32_t initval);

usr.sbin/nsd/lookup3.h

62

uint32_t hashlittle(const void *k, size_t length, uint32_t initval);

usr.sbin/nsd/lookup3.h

69

void hash_set_raninit(uint32_t v);

usr.sbin/nsd/namedb.c

87

uint32_t sw;

usr.sbin/nsd/namedb.h

111

uint32_t number; /* Unique domain name number. */

usr.sbin/nsd/namedb.h

112

uint32_t usage; /* number of ptrs to this from RRs(in rdata) and

usr.sbin/nsd/namedb.h

173

uint32_t ttl;

usr.sbin/nsd/namedb.h

228

static inline uint32_t

usr.sbin/nsd/nsd-checkzone.c

139

uint32_t ixfr_number = IXFR_NUMBER_DEFAULT;

usr.sbin/nsd/nsd-checkzone.c

157

ixfr_number = (uint32_t)atoi(optarg);

usr.sbin/nsd/nsd-checkzone.c

48

const char* oldzone, uint32_t ixfr_number, uint64_t ixfr_size)

usr.sbin/nsd/options.c

1553

marshal_u32(struct buffer* b, uint32_t v)

usr.sbin/nsd/options.c

1559

static uint32_t

usr.sbin/nsd/options.c

1643

uint32_t i, n;

usr.sbin/nsd/options.c

1664

uint32_t i, n;

usr.sbin/nsd/options.c

2049

if(!acl_addr_match_mask((uint32_t*)&acl->addr.addr6, (uint32_t*)&addr->sin6_addr,

usr.sbin/nsd/options.c

2050

(uint32_t*)&acl->range_mask.addr6, sizeof(struct in6_addr)))

usr.sbin/nsd/options.c

2054

if(!acl_addr_match_range_v6((uint32_t*)&acl->addr.addr6, (uint32_t*)&addr->sin6_addr,

usr.sbin/nsd/options.c

2055

(uint32_t*)&acl->range_mask.addr6, sizeof(struct in6_addr)))

usr.sbin/nsd/options.c

2077

if(!acl_addr_match_mask((uint32_t*)&acl->addr.addr, (uint32_t*)&addr->sin_addr,

usr.sbin/nsd/options.c

2078

(uint32_t*)&acl->range_mask.addr, sizeof(struct in_addr)))

usr.sbin/nsd/options.c

2082

if(!acl_addr_match_range_v4((uint32_t*)&acl->addr.addr, (uint32_t*)&addr->sin_addr,

usr.sbin/nsd/options.c

2083

(uint32_t*)&acl->range_mask.addr, sizeof(struct in_addr)))

usr.sbin/nsd/options.c

2170

acl_addr_match_mask(uint32_t* a, uint32_t* b, uint32_t* mask, size_t sz)

usr.sbin/nsd/options.c

2187

acl_addr_match_range_v4(uint32_t* minval, uint32_t* x, uint32_t* maxval, size_t sz)

usr.sbin/nsd/options.c

2203

acl_addr_match_range_v6(uint32_t* minval, uint32_t* x, uint32_t* maxval, size_t sz)

usr.sbin/nsd/options.h

258

uint32_t verifier_timeout;

usr.sbin/nsd/options.h

322

uint32_t max_refresh_time;

usr.sbin/nsd/options.h

324

uint32_t min_refresh_time;

usr.sbin/nsd/options.h

326

uint32_t max_retry_time;

usr.sbin/nsd/options.h

328

uint32_t min_retry_time;

usr.sbin/nsd/options.h

330

uint32_t min_expire_time;

usr.sbin/nsd/options.h

342

uint32_t ixfr_number;

usr.sbin/nsd/options.h

602

int acl_addr_match_mask(uint32_t* a, uint32_t* b, uint32_t* mask, size_t sz);

usr.sbin/nsd/options.h

603

int acl_addr_match_range_v6(uint32_t* minval, uint32_t* x, uint32_t* maxval, size_t sz);

usr.sbin/nsd/options.h

604

int acl_addr_match_range_v4(uint32_t* minval, uint32_t* x, uint32_t* maxval, size_t sz);

usr.sbin/nsd/packet.c

253

uint32_t ttl;

usr.sbin/nsd/packet.c

275

} else if (!buffer_available(packet, sizeof(uint32_t) + sizeof(uint16_t))) {

usr.sbin/nsd/packet.c

338

int packet_find_notify_serial(buffer_type *packet, uint32_t* serial)

usr.sbin/nsd/packet.c

51

packet_encode_rr(query_type *q, domain_type *owner, rr_type *rr, uint32_t ttl)

usr.sbin/nsd/packet.h

158

uint32_t ttl);

usr.sbin/nsd/packet.h

203

int packet_find_notify_serial(buffer_type *packet, uint32_t* serial);

usr.sbin/nsd/query.c

1614

query_process(query_type *q, nsd_type *nsd, uint32_t *now_p)

usr.sbin/nsd/query.c

1802

query_add_optional(query_type *q, nsd_type *nsd, uint32_t *now_p)

usr.sbin/nsd/query.c

1837

+ sizeof(uint32_t);

usr.sbin/nsd/query.c

1858

uint32_t serial = 0;

usr.sbin/nsd/query.c

1863

+ sizeof(uint32_t));

usr.sbin/nsd/query.c

309

uint32_t ttl,

usr.sbin/nsd/query.c

500

uint32_t acl_send = htonl(acl_num);

usr.sbin/nsd/query.c

501

uint32_t acl_xfr;

usr.sbin/nsd/query.c

533

uint32_t serial = 0;

usr.sbin/nsd/query.c

851

domain_type** to_closest_match, uint32_t ttl)

usr.sbin/nsd/query.h

241

query_state_type query_process(query_type *q, nsd_type *nsd, uint32_t *now_p);

usr.sbin/nsd/query.h

254

void query_add_optional(query_type *q, nsd_type *nsd, uint32_t *now_p);

usr.sbin/nsd/rdata.c

1477

uint32_t serial, refresh, retry, expire, minimum;

usr.sbin/nsd/rdata.c

1502

uint32_t serial, refresh, retry, expire, minimum;

usr.sbin/nsd/rdata.c

2141

uint32_t longitude;

usr.sbin/nsd/rdata.c

2142

uint32_t latitude;

usr.sbin/nsd/rdata.c

2143

uint32_t altitude;

usr.sbin/nsd/rdata.c

2146

uint32_t h;

usr.sbin/nsd/rdata.c

2147

uint32_t m;

usr.sbin/nsd/rdata.c

2149

uint32_t equator = (uint32_t)1 << 31; /* 2**31 */

usr.sbin/nsd/rdata.c

4171

retrieve_soa_rdata_serial(const struct rr* rr, uint32_t* serial)

usr.sbin/nsd/rdata.c

4182

retrieve_soa_rdata_minttl(const struct rr* rr, uint32_t* minttl)

usr.sbin/nsd/rdata.h

636

int retrieve_soa_rdata_serial(const struct rr* rr, uint32_t* serial);

usr.sbin/nsd/rdata.h

639

int retrieve_soa_rdata_minttl(const struct rr* rr, uint32_t* minttl);

usr.sbin/nsd/remote.c

1046

uint32_t serial = 0;

usr.sbin/nsd/rrl.c

197

a4.s_addr = (uint32_t)s;

usr.sbin/nsd/rrl.c

306

static void examine_query(query_type* query, uint32_t* hash, uint64_t* source,

usr.sbin/nsd/rrl.c

307

uint16_t* flags, uint32_t* lm)

usr.sbin/nsd/rrl.c

314

uint32_t r = 0x267fcd16;

usr.sbin/nsd/rrl.c

34

uint32_t rate;

usr.sbin/nsd/rrl.c

36

uint32_t hash;

usr.sbin/nsd/rrl.c

376

used_to_block(uint32_t rate, uint32_t counter, uint32_t lm)

usr.sbin/nsd/rrl.c

38

uint32_t counter;

usr.sbin/nsd/rrl.c

382

uint32_t rrl_update(query_type* query, uint32_t hash, uint64_t source,

usr.sbin/nsd/rrl.c

383

uint16_t flags, int32_t now, uint32_t lm)

usr.sbin/nsd/rrl.c

459

uint32_t hash;

usr.sbin/nsd/rrl.c

462

uint32_t lm = rrl_ratelimit;

usr.sbin/nsd/rrl.c

49

static uint32_t rrl_ratelimit = RRL_LIMIT; /* 2x qps */

usr.sbin/nsd/rrl.c

54

static uint32_t rrl_whitelist_ratelimit = RRL_WLIST_LIMIT; /* 2x qps */

usr.sbin/nsd/rrl.h

81

uint32_t rrl_update(query_type* query, uint32_t hash, uint64_t source,

usr.sbin/nsd/rrl.h

82

uint16_t flags, int32_t now, uint32_t lm);

usr.sbin/nsd/server.c

1517

uint32_t v;

usr.sbin/nsd/server.c

1526

uint32_t v = getpid() ^ time(NULL);

usr.sbin/nsd/server.c

3234

server_process_query(struct nsd *nsd, struct query *query, uint32_t *now_p)

usr.sbin/nsd/server.c

3240

server_process_query_udp(struct nsd *nsd, struct query *query, uint32_t *now_p)

usr.sbin/nsd/server.c

398

static uint32_t compression_table_capacity = 0;

usr.sbin/nsd/server.c

399

static uint32_t compression_table_size = 0;

usr.sbin/nsd/server.c

4149

uint32_t now = 0;

usr.sbin/nsd/server.c

4468

uint32_t now = 0;

usr.sbin/nsd/server.c

4748

uint32_t now = 0;

usr.sbin/nsd/server.c

5076

uint32_t now = 0;

usr.sbin/nsd/server.c

5352

uint32_t now = 0;

usr.sbin/nsd/simdzone/include/zone.h

323

uint32_t last_ttl;

usr.sbin/nsd/simdzone/include/zone.h

325

uint32_t dollar_ttl;

usr.sbin/nsd/simdzone/include/zone.h

327

uint32_t *ttl;

usr.sbin/nsd/simdzone/include/zone.h

330

uint32_t *default_ttl;

usr.sbin/nsd/simdzone/include/zone.h

387

uint32_t, // priority

usr.sbin/nsd/simdzone/include/zone.h

414

uint32_t, // ttl

usr.sbin/nsd/simdzone/include/zone.h

444

uint32_t include_limit;

usr.sbin/nsd/simdzone/include/zone.h

450

uint32_t default_ttl;

usr.sbin/nsd/simdzone/include/zone.h

455

uint32_t mask;

usr.sbin/nsd/simdzone/include/zone.h

621

uint32_t priority,

usr.sbin/nsd/simdzone/src/bench.c

126

const uint32_t supported = detect_supported_architectures();

usr.sbin/nsd/simdzone/src/bench.c

50

uint32_t instruction_set;

usr.sbin/nsd/simdzone/src/bench.c

92

uint32_t ttl,

usr.sbin/nsd/simdzone/src/fallback/name.h

31

uint32_t n;

usr.sbin/nsd/simdzone/src/fallback/text.h

13

static really_inline uint32_t unescape(const char *text, uint8_t *wire)

usr.sbin/nsd/simdzone/src/fallback/text.h

23

uint32_t o = d[0] * 100 + d[1] * 10 + d[2];

usr.sbin/nsd/simdzone/src/fallback/text.h

46

const uint32_t octet = unescape(text, wire);

usr.sbin/nsd/simdzone/src/fallback/text.h

64

const uint32_t octet = unescape(text, wire);

usr.sbin/nsd/simdzone/src/generic/algorithm.h

106

uint32_t value32 = (uint32_t)((value >> 32) ^ value);

usr.sbin/nsd/simdzone/src/generic/apl.h

18

uint32_t prefix;

usr.sbin/nsd/simdzone/src/generic/atma.h

115

uint32_t q;

usr.sbin/nsd/simdzone/src/generic/atma.h

91

uint32_t bad_chars = 0;

usr.sbin/nsd/simdzone/src/generic/base16.h

158

uint32_t q;

usr.sbin/nsd/simdzone/src/generic/base16.h

26

static const uint32_t base16_table_dec_32bit_d0[256] = {

usr.sbin/nsd/simdzone/src/generic/base16.h

51

static const uint32_t base16_table_dec_32bit_d1[256] = {

usr.sbin/nsd/simdzone/src/generic/base16.h

80

const uint32_t val1 = base16_table_dec_32bit_d0[(*s)[0]]

usr.sbin/nsd/simdzone/src/generic/base16.h

82

const uint32_t val2 = base16_table_dec_32bit_d0[(*s)[2]]

usr.sbin/nsd/simdzone/src/generic/base32.h

57

uint32_t state = 0;

usr.sbin/nsd/simdzone/src/generic/base64.h

114

static const uint32_t base64_table_dec_32bit_d1[256] = {

usr.sbin/nsd/simdzone/src/generic/base64.h

161

static const uint32_t base64_table_dec_32bit_d2[256] = {

usr.sbin/nsd/simdzone/src/generic/base64.h

208

static const uint32_t base64_table_dec_32bit_d3[256] = {

usr.sbin/nsd/simdzone/src/generic/base64.h

258

const uint32_t base64_table_dec_32bit_d0[256] = {

usr.sbin/nsd/simdzone/src/generic/base64.h

304

const uint32_t base64_table_dec_32bit_d1[256] = {

usr.sbin/nsd/simdzone/src/generic/base64.h

350

const uint32_t base64_table_dec_32bit_d2[256] = {

usr.sbin/nsd/simdzone/src/generic/base64.h

397

const uint32_t base64_table_dec_32bit_d3[256] = {

usr.sbin/nsd/simdzone/src/generic/base64.h

452

const uint32_t str

usr.sbin/nsd/simdzone/src/generic/base64.h

67

static const uint32_t base64_table_dec_32bit_d0[256] = {

usr.sbin/nsd/simdzone/src/generic/caa.h

65

uint32_t bad_chars = 0;

usr.sbin/nsd/simdzone/src/generic/cert.h

65

uint32_t value32 = (uint32_t)((value >> 32) ^ value);

usr.sbin/nsd/simdzone/src/generic/endian.h

144

static really_inline uint32_t bswap32(uint32_t x)

usr.sbin/nsd/simdzone/src/generic/eui.h

16

const uint32_t val1 = base16_table_dec_32bit_d0[s[0]]

usr.sbin/nsd/simdzone/src/generic/eui.h

18

const uint32_t val2 = base16_table_dec_32bit_d0[s[3]]

usr.sbin/nsd/simdzone/src/generic/format.h

129

rdata->octets += 1u + (uint32_t)length;

usr.sbin/nsd/simdzone/src/generic/format.h

145

rdata->octets += (uint32_t)length;

usr.sbin/nsd/simdzone/src/generic/format.h

292

for (uint32_t depth = 1; includer; depth++, includer = includer->includer) {

usr.sbin/nsd/simdzone/src/generic/gpos.h

21

uint32_t degrees;

usr.sbin/nsd/simdzone/src/generic/gpos.h

85

uint32_t degrees;

usr.sbin/nsd/simdzone/src/generic/ip4.h

16

uint32_t round = 0;

usr.sbin/nsd/simdzone/src/generic/ip4.h

19

uint32_t octet;

usr.sbin/nsd/simdzone/src/generic/ip6.h

105

uint32_t val;

usr.sbin/nsd/simdzone/src/generic/ip6.h

59

uint32_t new = *tp * 10 + (uint32_t)(pch - digits);

usr.sbin/nsd/simdzone/src/generic/loc.h

129

const char *text, size_t length, uint32_t *altitude)

usr.sbin/nsd/simdzone/src/generic/loc.h

14

const char *text, size_t length, uint32_t *degrees)

usr.sbin/nsd/simdzone/src/generic/loc.h

177

*altitude = (uint32_t)(10000000llu - centimeters);

usr.sbin/nsd/simdzone/src/generic/loc.h

179

*altitude = (uint32_t)(10000000llu + centimeters);

usr.sbin/nsd/simdzone/src/generic/loc.h

49

const char *text, size_t length, uint32_t *minutes)

usr.sbin/nsd/simdzone/src/generic/loc.h

74

const char *text, size_t length, uint32_t *seconds)

usr.sbin/nsd/simdzone/src/generic/name.h

107

const uint32_t octet = unescape(text+count, wire+count);

usr.sbin/nsd/simdzone/src/generic/nsap.h

37

uint32_t d0 = base16_table_dec_32bit_d0[data[0]];

usr.sbin/nsd/simdzone/src/generic/nsap.h

38

uint32_t d1 = base16_table_dec_32bit_d1[data[1]];

usr.sbin/nsd/simdzone/src/generic/nsec.h

31

uint32_t highest_window = 0;

usr.sbin/nsd/simdzone/src/generic/nsec.h

32

uint32_t windows[256] = { 0 };

usr.sbin/nsd/simdzone/src/generic/nsec.h

54

for (uint32_t window = 0; window <= highest_window; window++) {

usr.sbin/nsd/simdzone/src/generic/number.h

132

uint32_t number;

usr.sbin/nsd/simdzone/src/generic/number.h

16

uint32_t sum = (uint8_t)data[0] - '0';

usr.sbin/nsd/simdzone/src/generic/number.h

36

uint32_t sum = (uint8_t)data[0] - '0';

usr.sbin/nsd/simdzone/src/generic/number.h

54

const char *data, size_t length, uint32_t *number)

usr.sbin/nsd/simdzone/src/generic/number.h

68

*number = (uint32_t)sum;

usr.sbin/nsd/simdzone/src/generic/parser.h

195

extern void zone_vlog(parser_t *, uint32_t, const char *, va_list);

usr.sbin/nsd/simdzone/src/generic/parser.h

211

uint32_t category = ZONE_ERROR;

usr.sbin/nsd/simdzone/src/generic/parser.h

55

uint32_t value;

usr.sbin/nsd/simdzone/src/generic/parser.h

86

uint32_t value;

usr.sbin/nsd/simdzone/src/generic/parser.h

88

uint32_t has_value;

usr.sbin/nsd/simdzone/src/generic/svcb.h

107

uint32_t length;

usr.sbin/nsd/simdzone/src/generic/svcb.h

317

uint32_t o;

usr.sbin/nsd/simdzone/src/generic/svcb.h

355

uint32_t o;

usr.sbin/nsd/simdzone/src/generic/svcb.h

492

uint32_t number = (uint8_t)data[3] - '0';

usr.sbin/nsd/simdzone/src/generic/svcb.h

497

uint32_t leading_zero = number == 0;

usr.sbin/nsd/simdzone/src/generic/svcb.h

500

const uint32_t digit = (uint8_t)data[length] - '0';

usr.sbin/nsd/simdzone/src/generic/svcb.h

866

uint32_t errors = 0;

usr.sbin/nsd/simdzone/src/generic/text.h

13

static really_inline uint32_t unescape(const char *text, uint8_t *wire)

usr.sbin/nsd/simdzone/src/generic/text.h

16

uint32_t o;

usr.sbin/nsd/simdzone/src/generic/text.h

88

const uint32_t octet = unescape(text+count, wire+count);

usr.sbin/nsd/simdzone/src/generic/time.h

79

uint32_t time = htobe32((uint32_t)seconds);

usr.sbin/nsd/simdzone/src/generic/ttl.h

105

uint32_t ttl;

usr.sbin/nsd/simdzone/src/generic/ttl.h

13

static const uint32_t ttl_units[256] = {

usr.sbin/nsd/simdzone/src/generic/ttl.h

34

const char *data, size_t length, bool allow_units, uint32_t *ttl)

usr.sbin/nsd/simdzone/src/generic/ttl.h

93

*ttl = (uint32_t)sum;

usr.sbin/nsd/simdzone/src/generic/type.h

111

uint32_t value = (uint32_t)((prefix >> 32) ^ prefix);

usr.sbin/nsd/simdzone/src/generic/types.h

106

uint32_t number;

usr.sbin/nsd/simdzone/src/generic/types.h

88

#define check_int32(...) check_bytes(__VA_ARGS__, sizeof(uint32_t))

usr.sbin/nsd/simdzone/src/generic/types.h

977

uint32_t degrees, minutes, seconds;

usr.sbin/nsd/simdzone/src/generic/types.h

978

uint32_t latitude, longitude, altitude;

usr.sbin/nsd/simdzone/src/generic/wks.h

199

uint32_t input32 = (uint32_t)((input >> 32) ^ input);

usr.sbin/nsd/simdzone/src/haswell/simd.h

100

const uint64_t m0 = (uint32_t)_mm256_movemask_epi8(r0);

usr.sbin/nsd/simdzone/src/haswell/simd.h

101

const uint64_t m1 = (uint32_t)_mm256_movemask_epi8(r1);

usr.sbin/nsd/simdzone/src/haswell/simd.h

117

const uint64_t m0 = (uint32_t)_mm256_movemask_epi8(r0);

usr.sbin/nsd/simdzone/src/haswell/simd.h

118

const uint64_t m1 = (uint32_t)_mm256_movemask_epi8(r1);

usr.sbin/nsd/simdzone/src/haswell/simd.h

53

return (uint32_t)_mm256_movemask_epi8(r);

usr.sbin/nsd/simdzone/src/haswell/simd.h

63

return (uint32_t)_mm256_movemask_epi8(r);

usr.sbin/nsd/simdzone/src/isadetection.h

104

static inline uint32_t detect_supported_architectures(void) {

usr.sbin/nsd/simdzone/src/isadetection.h

113

static const uint32_t cpuid_avx2_bit = 1 << 5; ///< @private Bit 5 of EBX for EAX=0x7

usr.sbin/nsd/simdzone/src/isadetection.h

114

static const uint32_t cpuid_bmi1_bit = 1 << 3; ///< @private bit 3 of EBX for EAX=0x7

usr.sbin/nsd/simdzone/src/isadetection.h

115

static const uint32_t cpuid_bmi2_bit = 1 << 8; ///< @private bit 8 of EBX for EAX=0x7

usr.sbin/nsd/simdzone/src/isadetection.h

116

static const uint32_t cpuid_avx512f_bit = 1 << 16; ///< @private bit 16 of EBX for EAX=0x7

usr.sbin/nsd/simdzone/src/isadetection.h

117

static const uint32_t cpuid_avx512dq_bit = 1 << 17; ///< @private bit 17 of EBX for EAX=0x7

usr.sbin/nsd/simdzone/src/isadetection.h

118

static const uint32_t cpuid_avx512ifma_bit = 1 << 21; ///< @private bit 21 of EBX for EAX=0x7

usr.sbin/nsd/simdzone/src/isadetection.h

119

static const uint32_t cpuid_avx512pf_bit = 1 << 26; ///< @private bit 26 of EBX for EAX=0x7

usr.sbin/nsd/simdzone/src/isadetection.h

120

static const uint32_t cpuid_avx512er_bit = 1 << 27; ///< @private bit 27 of EBX for EAX=0x7

usr.sbin/nsd/simdzone/src/isadetection.h

121

static const uint32_t cpuid_avx512cd_bit = 1 << 28; ///< @private bit 28 of EBX for EAX=0x7

usr.sbin/nsd/simdzone/src/isadetection.h

122

static const uint32_t cpuid_avx512bw_bit = 1 << 30; ///< @private bit 30 of EBX for EAX=0x7

usr.sbin/nsd/simdzone/src/isadetection.h

123

static const uint32_t cpuid_avx512vl_bit = 1U << 31; ///< @private bit 31 of EBX for EAX=0x7

usr.sbin/nsd/simdzone/src/isadetection.h

124

static const uint32_t cpuid_avx512vbmi2_bit = 1 << 6; ///< @private bit 6 of ECX for EAX=0x7

usr.sbin/nsd/simdzone/src/isadetection.h

125

static const uint32_t cpuid_sse42_bit = 1 << 20; ///< @private bit 20 of ECX for EAX=0x1

usr.sbin/nsd/simdzone/src/isadetection.h

126

static const uint32_t cpuid_pclmulqdq_bit = 1 << 1; ///< @private bit 1 of ECX for EAX=0x1

usr.sbin/nsd/simdzone/src/isadetection.h

127

static const uint32_t cpuid_have_xgetbv_bit = 1 << 27; ///< @private bit 27 of ECX for EAX=0x1

usr.sbin/nsd/simdzone/src/isadetection.h

128

static const uint32_t cpuid_have_avx_bit = 1 << 28; ///< @private bit 28 of ECX for EAX=0x1

usr.sbin/nsd/simdzone/src/isadetection.h

131

uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)

usr.sbin/nsd/simdzone/src/isadetection.h

141

uint32_t level = *eax;

usr.sbin/nsd/simdzone/src/isadetection.h

144

uint32_t a = *eax, b, c = *ecx, d;

usr.sbin/nsd/simdzone/src/isadetection.h

153

static inline uint64_t xgetbv(uint32_t ecx)

usr.sbin/nsd/simdzone/src/isadetection.h

158

uint32_t a, c = ecx, d;

usr.sbin/nsd/simdzone/src/isadetection.h

165

static inline uint32_t detect_supported_architectures(void)

usr.sbin/nsd/simdzone/src/isadetection.h

167

uint32_t eax, ebx, ecx, edx;

usr.sbin/nsd/simdzone/src/isadetection.h

168

uint32_t host_isa = 0x0, host_avx_isa = 0x0;

usr.sbin/nsd/simdzone/src/isadetection.h

263

static inline uint32_t detect_supported_architectures(void) {

usr.sbin/nsd/simdzone/src/isadetection.h

90

static inline uint32_t detect_supported_architectures(void) {

usr.sbin/nsd/simdzone/src/isadetection.h

98

static inline uint32_t detect_supported_architectures(void) {

usr.sbin/nsd/simdzone/src/westmere/ip4.h

137

uint32_t dot_mask = (uint32_t)_mm_movemask_epi8(is_dot);

usr.sbin/nsd/simdzone/src/westmere/ip4.h

143

uint32_t non_digit_mask = (uint32_t)_mm_movemask_epi8(v);

usr.sbin/nsd/simdzone/src/westmere/ip4.h

146

uint32_t bad_mask = dot_mask ^ non_digit_mask;

usr.sbin/nsd/simdzone/src/westmere/ip4.h

147

uint32_t clip_mask = bad_mask ^ (bad_mask - 1);

usr.sbin/nsd/simdzone/src/westmere/ip4.h

148

uint32_t partition_mask = non_digit_mask & clip_mask;

usr.sbin/nsd/simdzone/src/westmere/ip4.h

150

const uint32_t length = (uint32_t)count_ones(clip_mask) - 1;

usr.sbin/nsd/simdzone/src/westmere/ip4.h

152

uint32_t hash_key = (partition_mask * 0x00CF7800) >> 24;

usr.sbin/nsd/simdzone/src/westmere/ip4.h

172

uint32_t check_mask = (uint32_t)_mm_movemask_epi8(checks);

usr.sbin/nsd/simdzone/src/westmere/ip4.h

176

uint32_t address = (uint32_t)_mm_cvtsi128_si32(_mm_packus_epi16(acc, acc));

usr.sbin/nsd/simdzone/src/westmere/simd.h

87

const uint32_t m0 = (uint16_t)_mm_movemask_epi8(r0);

usr.sbin/nsd/simdzone/src/westmere/simd.h

88

const uint32_t m1 = (uint16_t)_mm_movemask_epi8(r1);

usr.sbin/nsd/simdzone/src/westmere/time.h

101

bool is_leap_yr = (bool)is_leap_year((uint32_t)yr);

usr.sbin/nsd/simdzone/src/westmere/time.h

112

uint64_t days = 365 * (yr - 1970) + (uint64_t)leap_days((uint32_t)yr);

usr.sbin/nsd/simdzone/src/westmere/time.h

119

*time_in_second = (uint32_t)time_in_second64;

usr.sbin/nsd/simdzone/src/westmere/time.h

131

uint32_t time;

usr.sbin/nsd/simdzone/src/westmere/time.h

23

static inline uint32_t is_leap_year(uint32_t year) {

usr.sbin/nsd/simdzone/src/westmere/time.h

27

static inline uint32_t leap_days(uint32_t year) {

usr.sbin/nsd/simdzone/src/westmere/time.h

32

static bool sse_parse_time(const char *date_string, uint32_t *time_in_second) {

usr.sbin/nsd/simdzone/src/westmere/type.h

103

uint32_t value = (uint32_t)((prefix >> 32) ^ prefix);

usr.sbin/nsd/simdzone/src/zone.c

466

uint32_t priority,

usr.sbin/nsd/simdzone/src/zone.c

486

uint32_t priority,

usr.sbin/nsd/simdzone/src/zone.c

492

uint32_t priority,

usr.sbin/nsd/simdzone/src/zone.c

517

uint32_t priority,

usr.sbin/nsd/simdzone/src/zone.c

62

uint32_t instruction_set;

usr.sbin/nsd/simdzone/src/zone.c

83

const uint32_t supported = detect_supported_architectures();

usr.sbin/nsd/siphash.c

35

U32TO8_LE((p), (uint32_t)((v))); \

usr.sbin/nsd/siphash.c

36

U32TO8_LE((p) + 4, (uint32_t)((v) >> 32));

usr.sbin/nsd/siphash.c

65

printf("(%3d) v0 %08x %08x\n", (int)inlen, (uint32_t)(v0 >> 32), \

usr.sbin/nsd/siphash.c

66

(uint32_t)v0); \

usr.sbin/nsd/siphash.c

67

printf("(%3d) v1 %08x %08x\n", (int)inlen, (uint32_t)(v1 >> 32), \

usr.sbin/nsd/siphash.c

68

(uint32_t)v1); \

usr.sbin/nsd/siphash.c

69

printf("(%3d) v2 %08x %08x\n", (int)inlen, (uint32_t)(v2 >> 32), \

usr.sbin/nsd/siphash.c

70

(uint32_t)v2); \

usr.sbin/nsd/siphash.c

71

printf("(%3d) v3 %08x %08x\n", (int)inlen, (uint32_t)(v3 >> 32), \

usr.sbin/nsd/siphash.c

72

(uint32_t)v3); \

usr.sbin/nsd/tsig.c

100

uint32_t ttl = htonl(0);

usr.sbin/nsd/tsig.c

102

uint32_t signed_time_low = htonl(tsig->signed_time_low);

usr.sbin/nsd/tsig.c

395

uint32_t current_time_low;

usr.sbin/nsd/tsig.c

420

current_time_low = (uint32_t) current_time;

usr.sbin/nsd/tsig.c

423

tsig->rr_region, sizeof(uint16_t) + sizeof(uint32_t));

usr.sbin/nsd/tsig.c

510

tsig->signed_time_low = (uint32_t) current_time;

usr.sbin/nsd/tsig.c

586

uint32_t ttl;

usr.sbin/nsd/tsig.c

717

+ sizeof(uint32_t) /* TTL */

usr.sbin/nsd/tsig.c

721

+ sizeof(uint32_t) /* Signed time (low) */

usr.sbin/nsd/tsig.h

123

uint32_t signed_time_low;

usr.sbin/nsd/udb.c

379

static uint32_t

usr.sbin/nsd/udb.c

383

uint32_t h[sizeof(p)/sizeof(uint32_t)];

usr.sbin/nsd/udb.c

385

return hashword(h, sizeof(p)/sizeof(uint32_t), 0x8763);

usr.sbin/nsd/udb.c

391

uint32_t i = chunk_hash_ptr(to) & udb->ram_mask;

usr.sbin/nsd/udb.c

431

uint32_t i;

usr.sbin/nsd/udb.c

467

uint32_t i = chunk_hash_ptr(ptr->data) & udb->ram_mask;

usr.sbin/nsd/udb.c

477

uint32_t io = chunk_hash_ptr(old) & udb->ram_mask;

usr.sbin/nsd/util.c

751

static uint32_t crctab[] = {

usr.sbin/nsd/util.c

808

uint32_t

usr.sbin/nsd/util.c

809

compute_crc(uint32_t crc, uint8_t* data, size_t len)

usr.sbin/nsd/util.c

818

write_data_crc(FILE *file, const void *data, size_t size, uint32_t* crc)

usr.sbin/nsd/util.c

827

compare_serial(uint32_t a, uint32_t b)

usr.sbin/nsd/util.c

829

const uint32_t cutoff = ((uint32_t) 1 << (SERIAL_BITS - 1));

usr.sbin/nsd/util.h

184

int write_data_crc(FILE *file, const void *data, size_t size, uint32_t* crc);

usr.sbin/nsd/util.h

210

write_uint32(void *dst, uint32_t data)

usr.sbin/nsd/util.h

213

* (uint32_t *) dst = htonl(data);

usr.sbin/nsd/util.h

252

static inline uint32_t

usr.sbin/nsd/util.h

256

return ntohl(* (const uint32_t *) src);

usr.sbin/nsd/util.h

259

return ((uint32_t)p[0] << 24) | ((uint32_t)p[1] << 16) | ((uint32_t)p[2] << 8) | (uint32_t)p[3];

usr.sbin/nsd/util.h

359

uint32_t compute_crc(uint32_t crc, uint8_t* data, size_t len);

usr.sbin/nsd/util.h

367

int compare_serial(uint32_t a, uint32_t b);

usr.sbin/nsd/util/proxy_protocol.c

49

void (*write_uint32)(void* buf, uint32_t data);

usr.sbin/nsd/util/proxy_protocol.c

75

void (*write_uint32)(void* buf, uint32_t data)) {

usr.sbin/nsd/util/proxy_protocol.h

107

uint32_t src_addr;

usr.sbin/nsd/util/proxy_protocol.h

108

uint32_t dst_addr;

usr.sbin/nsd/util/proxy_protocol.h

142

void (*write_uint32)(void* buf, uint32_t data));

usr.sbin/nsd/xdp-server.c

174

uint32_t *len,

usr.sbin/nsd/xdp-server.c

188

static uint32_t parse_dns(struct nsd* nsd,

usr.sbin/nsd/xdp-server.c

189

uint32_t dnslen,

usr.sbin/nsd/xdp-server.c

219

uint32_t stock_frames;

usr.sbin/nsd/xdp-server.c

220

uint32_t idx_fq = 0;

usr.sbin/nsd/xdp-server.c

224

(uint32_t) xsk_umem_free_frames(xsk));

usr.sbin/nsd/xdp-server.c

230

for (uint32_t i = 0; i < stock_frames; ++i) {

usr.sbin/nsd/xdp-server.c

345

struct xsk_umem_info *umem, uint32_t queue_index) {

usr.sbin/nsd/xdp-server.c

347

uint32_t idx, reserved;

usr.sbin/nsd/xdp-server.c

388

for (uint32_t i = 0; i < XDP_NUM_FRAMES; ++i) {

usr.sbin/nsd/xdp-server.c

407

for (uint32_t i = 0; i < XSK_RING_PROD__NUM_DESCS; ++i) {

usr.sbin/nsd/xdp-server.c

446

for (uint32_t q_idx = 0; q_idx < xdp->queue_count; ++q_idx) {

usr.sbin/nsd/xdp-server.c

467

for (uint32_t i = 0; i < xdp->queue_count; ++i)

usr.sbin/nsd/xdp-server.c

475

for (uint32_t i = 0; i < xdp->queue_count; ++i) {

usr.sbin/nsd/xdp-server.c

69

uint32_t len;

usr.sbin/nsd/xdp-server.c

691

static uint32_t parse_dns(struct nsd* nsd, uint32_t dnslen,

usr.sbin/nsd/xdp-server.c

694

uint32_t now = 0;

usr.sbin/nsd/xdp-server.c

729

return (uint32_t) buffer_remaining(q->packet);

usr.sbin/nsd/xdp-server.c

740

uint32_t *len, struct query *query) {

usr.sbin/nsd/xdp-server.c

743

uint32_t dnslen = *len;

usr.sbin/nsd/xdp-server.c

744

uint32_t data_before_dnshdr_len = 0;

usr.sbin/nsd/xdp-server.c

770

dnslen -= (uint32_t) (sizeof(*eth) + sizeof(*ipv6) + sizeof(*udp));

usr.sbin/nsd/xdp-server.c

783

dnslen -= (uint32_t) (sizeof(*eth) + sizeof(*ipv4) + sizeof(*udp));

usr.sbin/nsd/xdp-server.c

871

uint32_t idx_rx = 0;

usr.sbin/nsd/xdp-server.c

872

uint32_t tx_idx = 0;

usr.sbin/nsd/xdp-server.c

886

uint32_t len = xsk_ring_cons__rx_desc(&xsk->rx, idx_rx++)->len;

usr.sbin/nsd/xdp-server.c

93

uint32_t queue_index);

usr.sbin/nsd/xdp-server.c

934

uint32_t len = umem_ptrs[i].len;

usr.sbin/nsd/xdp-server.c

951

uint32_t completed, idx_cq;

usr.sbin/nsd/xdp-server.c

959

for (uint32_t i = 0; i < completed; i++) {

usr.sbin/nsd/xdp-server.h

39

uint32_t umem_frame_free;

usr.sbin/nsd/xdp-server.h

48

uint32_t outstanding_tx;

usr.sbin/nsd/xdp-server.h

68

uint32_t bpf_prog_id;

usr.sbin/nsd/xdp-server.h

72

uint32_t interface_index;

usr.sbin/nsd/xdp-server.h

73

uint32_t queue_count;

usr.sbin/nsd/xdp-server.h

74

uint32_t queue_index;

usr.sbin/nsd/xdp-util.c

32

uint32_t queue_count = 0;

usr.sbin/nsd/xdp-util.h

108

uint32_t sum = 0;

usr.sbin/nsd/xdp-util.h

55

static inline void csum_add_data(uint32_t *result,

usr.sbin/nsd/xdp-util.h

57

uint32_t len) {

usr.sbin/nsd/xdp-util.h

71

static inline void csum_add_u16(uint32_t *result, uint16_t x) { *result += x; }

usr.sbin/nsd/xdp-util.h

76

static inline void csum_reduce(uint32_t *result) {

usr.sbin/nsd/xdp-util.h

85

uint32_t sum = 0;

usr.sbin/nsd/xfr-inspect.c

231

uint32_t pkttype, msglen, msglen2;

usr.sbin/nsd/xfr-inspect.c

342

uint32_t old_serial, new_serial, num_parts, type;

usr.sbin/nsd/xfr-inspect.c

344

uint32_t time_end_1, time_start_1;

usr.sbin/nsd/xfr-inspect.c

416

uint32_t pkttype, msglen, msglen2;

usr.sbin/nsd/xfr-inspect.c

51

xi_diff_read_32(FILE *in, uint32_t* result)

usr.sbin/nsd/xfr-inspect.c

74

uint32_t disklen;

usr.sbin/nsd/xfr-inspect.c

93

uint32_t old_serial, new_serial, num_parts, type;

usr.sbin/nsd/xfr-inspect.c

95

uint32_t time_end_1, time_start_1;

usr.sbin/nsd/xfrd-catalog-zones.c

1031

uint32_t serial)

usr.sbin/nsd/xfrd-catalog-zones.c

1039

&& try_buffer_write_u16(packet, 9 + 9 + 5 * sizeof(uint32_t))

usr.sbin/nsd/xfrd-catalog-zones.c

1118

xw->new_serial = (uint32_t)xfrd_time();

usr.sbin/nsd/xfrd-catalog-zones.c

116

uint32_t serial);

usr.sbin/nsd/xfrd-catalog-zones.c

132

const dname_type* owner, uint32_t serial)

usr.sbin/nsd/xfrd-catalog-zones.c

976

char id_label[sizeof(uint32_t)*2+1];

usr.sbin/nsd/xfrd-catalog-zones.c

977

uint32_t new_id = (uint32_t)random_generate(0x7fffffff);

usr.sbin/nsd/xfrd-catalog-zones.c

979

hex_ntop((void*)&new_id, sizeof(uint32_t), id_label, sizeof(id_label));

usr.sbin/nsd/xfrd-catalog-zones.c

98

uint32_t seq_nr; /* number of messages already handled */

usr.sbin/nsd/xfrd-catalog-zones.c

980

id_label[sizeof(uint32_t)*2] = 0;

usr.sbin/nsd/xfrd-catalog-zones.c

99

uint32_t old_serial, new_serial; /* host byte order */

usr.sbin/nsd/xfrd-catalog-zones.h

48

uint32_t serial;

usr.sbin/nsd/xfrd-catalog-zones.h

77

uint32_t serial;

usr.sbin/nsd/xfrd-disk.c

147

uint32_t filetime = 0;

usr.sbin/nsd/xfrd-disk.c

148

uint32_t numzones, i;

usr.sbin/nsd/xfrd-disk.c

193

uint32_t state, masnum, nextmas, round_num, timeout, backoff;

usr.sbin/nsd/xfrd-disk.c

286

(uint32_t)xfrd_time() - soa_disk_acquired_read

usr.sbin/nsd/xfrd-disk.c

287

> (uint32_t)soa_refresh))

usr.sbin/nsd/xfrd-disk.c

292

if(timeout != 0 && filetime + timeout < (uint32_t)xfrd_time()) {

usr.sbin/nsd/xfrd-disk.c

302

(uint32_t)xfrd_time() - soa_disk_acquired_read

usr.sbin/nsd/xfrd-disk.c

55

xfrd_read_i32(FILE *in, uint32_t* v)

usr.sbin/nsd/xfrd-tcp.c

605

buffer_write(packet, &soa->serial, sizeof(uint32_t));

usr.sbin/nsd/xfrd-tcp.c

606

buffer_write(packet, &soa->refresh, sizeof(uint32_t));

usr.sbin/nsd/xfrd-tcp.c

607

buffer_write(packet, &soa->retry, sizeof(uint32_t));

usr.sbin/nsd/xfrd-tcp.c

608

buffer_write(packet, &soa->expire, sizeof(uint32_t));

usr.sbin/nsd/xfrd-tcp.c

609

buffer_write(packet, &soa->minimum, sizeof(uint32_t));

usr.sbin/nsd/xfrd-tcp.h

66

uint32_t total_bytes;

usr.sbin/nsd/xfrd.c

1409

memcpy(&soa->serial, p, sizeof(uint32_t));

usr.sbin/nsd/xfrd.c

1410

memcpy(&soa->refresh, p+4, sizeof(uint32_t));

usr.sbin/nsd/xfrd.c

1411

memcpy(&soa->retry, p+8, sizeof(uint32_t));

usr.sbin/nsd/xfrd.c

1412

memcpy(&soa->expire, p+12, sizeof(uint32_t));

usr.sbin/nsd/xfrd.c

1413

memcpy(&soa->minimum, p+16, sizeof(uint32_t));

usr.sbin/nsd/xfrd.c

1525

uint32_t soa_serial, soa_nsd_serial;

usr.sbin/nsd/xfrd.c

2010

uint32_t tmp_serial = 0;

usr.sbin/nsd/xfrd.c

630

uint32_t soa_serial=0, after_serial=0;

usr.sbin/nsd/xfrd.c

716

task->zname)+sizeof(uint32_t)*6 + sizeof(uint8_t)*2) {

usr.sbin/nsd/xfrd.c

733

memmove(&soa.ttl, p, sizeof(uint32_t));

usr.sbin/nsd/xfrd.c

734

p += sizeof(uint32_t);

usr.sbin/nsd/xfrd.c

743

memmove(&soa.serial, p, sizeof(uint32_t));

usr.sbin/nsd/xfrd.c

744

p += sizeof(uint32_t);

usr.sbin/nsd/xfrd.c

745

memmove(&soa.refresh, p, sizeof(uint32_t));

usr.sbin/nsd/xfrd.c

746

p += sizeof(uint32_t);

usr.sbin/nsd/xfrd.c

747

memmove(&soa.retry, p, sizeof(uint32_t));

usr.sbin/nsd/xfrd.c

748

p += sizeof(uint32_t);

usr.sbin/nsd/xfrd.c

749

memmove(&soa.expire, p, sizeof(uint32_t));

usr.sbin/nsd/xfrd.c

750

p += sizeof(uint32_t);

usr.sbin/nsd/xfrd.c

751

memmove(&soa.minimum, p, sizeof(uint32_t));

usr.sbin/nsd/xfrd.h

139

uint32_t ttl;

usr.sbin/nsd/xfrd.h

145

uint32_t serial;

usr.sbin/nsd/xfrd.h

146

uint32_t refresh;

usr.sbin/nsd/xfrd.h

147

uint32_t retry;

usr.sbin/nsd/xfrd.h

148

uint32_t expire;

usr.sbin/nsd/xfrd.h

149

uint32_t minimum;

usr.sbin/nsd/xfrd.h

239

uint32_t msg_seq_nr; /* number of messages already handled */

usr.sbin/nsd/xfrd.h

240

uint32_t msg_old_serial, msg_new_serial; /* host byte order */

usr.sbin/nsd/zonec.c

209

uint32_t ttl,

usr.sbin/nsd/zonec.c

385

uint32_t category,

usr.sbin/nsd/zonec.c

499

uint32_t soa_minimum = 0;

usr.sbin/nsd/zparser.y

1256

zparser_init(const char *filename, uint32_t ttl, uint16_t klass,

usr.sbin/nsd/zparser.y

54

uint32_t ttl;

usr.sbin/ospf6d/lsupdate.c

570

static uint32_t

usr.sbin/ospfd/lsupdate.c

559

static uint32_t

usr.sbin/pcidump/pcidump.c

411

uint32_t data[64]; /* XXX this can be up to 32k of data */

usr.sbin/pcidump/pcidump.c

508

pcie_dcap_mps(uint32_t dcap)

usr.sbin/pcidump/pcidump.c

510

uint32_t shift = dcap & 0x7;

usr.sbin/pcidump/pcidump.c

515

pcie_dcsr_mps(uint32_t dcsr)

usr.sbin/pcidump/pcidump.c

517

uint32_t shift = (dcsr >> 5) & 0x7;

usr.sbin/pcidump/pcidump.c

522

pcie_dcsr_mrrs(uint32_t dcsr)

usr.sbin/pcidump/pcidump.c

524

uint32_t shift = (dcsr >> 12) & 0x7;

usr.sbin/pcidump/pcidump.c

621

uint32_t lower, upper;

usr.sbin/pstat/pstat.c

239

uint32_t mask = ~0;

usr.sbin/pstat/pstat.c

338

printf(format, ((uint32_t)v) & mask);

usr.sbin/rad/engine.c

193

uint32_t if_index;

usr.sbin/rad/engine.c

52

uint32_t if_index;

usr.sbin/rad/engine.c

595

find_engine_iface_by_id(uint32_t if_index)

usr.sbin/rad/engine.c

607

update_iface(uint32_t if_index)

usr.sbin/rad/engine.c

625

remove_iface(uint32_t if_index)

usr.sbin/rad/engine.c

66

void update_iface(uint32_t);

usr.sbin/rad/engine.c

67

void remove_iface(uint32_t);

usr.sbin/rad/engine.c

68

struct engine_iface *find_engine_iface_by_id(uint32_t);

usr.sbin/rad/frontend.c

1050

uint32_t if_vltime, if_pltime;

usr.sbin/rad/frontend.c

108

uint32_t if_index;

usr.sbin/rad/frontend.c

1122

uint32_t if_vltime, uint32_t if_pltime)

usr.sbin/rad/frontend.c

1167

uint32_t

usr.sbin/rad/frontend.c

1168

calc_autoconf_ltime(time_t t, uint32_t conf_ltime, uint32_t if_ltime)

usr.sbin/rad/frontend.c

1170

uint32_t ltime;

usr.sbin/rad/frontend.c

1204

uint32_t vltime, pltime;

usr.sbin/rad/frontend.c

143

struct ra_iface *find_ra_iface_by_id(uint32_t);

usr.sbin/rad/frontend.c

154

int, uint32_t, uint32_t);

usr.sbin/rad/frontend.c

159

uint32_t calc_autoconf_ltime(time_t, uint32_t, uint32_t);

usr.sbin/rad/frontend.c

545

uint32_t if_index;

usr.sbin/rad/frontend.c

721

find_ra_iface_by_id(uint32_t if_index)

usr.sbin/rad/frontend.c

778

uint32_t if_index;

usr.sbin/rad/rad.c

526

imsg_compose_event(struct imsgev *iev, uint16_t type, uint32_t peerid,

usr.sbin/rad/rad.c

83

uint32_t cmd_opts;

usr.sbin/rad/rad.h

100

uint32_t mtu;

usr.sbin/rad/rad.h

101

uint32_t rdns_lifetime;

usr.sbin/rad/rad.h

114

uint32_t vltime; /* valid lifetime */

usr.sbin/rad/rad.h

115

uint32_t pltime; /* preferred lifetime */

usr.sbin/rad/rad.h

116

uint32_t if_vltime; /* valid lifetime */

usr.sbin/rad/rad.h

117

uint32_t if_pltime; /* preferred lifetime */

usr.sbin/rad/rad.h

138

uint32_t if_index;

usr.sbin/rad/rad.h

145

uint32_t if_index;

usr.sbin/rad/rad.h

149

extern uint32_t cmd_opts;

usr.sbin/rad/rad.h

156

int imsg_compose_event(struct imsgev *, uint16_t, uint32_t, pid_t,

usr.sbin/rad/rad.h

86

uint32_t ltime; /* lifetime */

usr.sbin/rad/rad.h

97

uint32_t reachable_time;

usr.sbin/rad/rad.h

98

uint32_t retrans_timer;

usr.sbin/radiusctl/radiusctl.c

252

uint32_t u32val;

usr.sbin/radiusctl/radiusctl.c

489

uint32_t u32val;

usr.sbin/radiusctl/radiusctl.c

708

uint32_t maxseq = 999;

usr.sbin/radiusd/control.c

199

control_connbyid(uint32_t id)

usr.sbin/radiusd/control.c

330

control_conn_bind(uint32_t peerid, const char *modulename)

usr.sbin/radiusd/control.c

45

struct ctl_conn *control_connbyid(uint32_t);

usr.sbin/radiusd/control.h

30

uint32_t id;

usr.sbin/radiusd/control.h

43

void control_conn_bind(uint32_t, const char *);

usr.sbin/radiusd/eap2mschap_local.h

140

uint32_t vendor;

usr.sbin/radiusd/parse.y

263

$$.mask.addr.ipv4.s_addr = htonl((uint32_t)

usr.sbin/radiusd/radiusd.c

102

uint32_t, u_int, RADIUS_PACKET *);

usr.sbin/radiusd/radiusd.c

1124

uint32_t type, uint32_t id, pid_t pid, int fd, void *data, size_t datalen)

usr.sbin/radiusd/radiusd.c

1599

uint32_t imsg_type, const char *type_str)

usr.sbin/radiusd/radiusd.c

1876

imsg_compose_radius_packet(struct imsgbuf *ibuf, uint32_t type, u_int q_id,

usr.sbin/radiusd/radiusd.c

1940

imsg_compose_event(struct imsgev *iev, uint32_t type, uint32_t peerid,

usr.sbin/radiusd/radiusd.c

1952

imsg_composev_event(struct imsgev *iev, uint32_t type, uint32_t peerid,

usr.sbin/radiusd/radiusd.c

394

#define s6_addr32(_in6) ((uint32_t *)(_in6)->s6_addr)

usr.sbin/radiusd/radiusd.c

446

uint32_t acct_status;

usr.sbin/radiusd/radiusd.c

73

static const char *radius_acct_status_type_string(uint32_t);

usr.sbin/radiusd/radiusd.c

753

uint32_t acct_status;

usr.sbin/radiusd/radiusd.c

84

struct imsg *, uint32_t, const char *);

usr.sbin/radiusd/radiusd.c

991

radius_acct_status_type_string(uint32_t type)

usr.sbin/radiusd/radiusd.c

995

uint32_t type;

usr.sbin/radiusd/radiusd.h

60

uint32_t cap; /* module capability bits */

usr.sbin/radiusd/radiusd_ipcp.c

1093

uint32_t type, delay, uval;

usr.sbin/radiusd/radiusd_ipcp.c

112

uint32_t peerid;

usr.sbin/radiusd/radiusd_ipcp.c

1746

uint32_t u32;

usr.sbin/radiusd/radiusd_ipcp.c

1883

uint32_t mask;

usr.sbin/radiusd/radiusd_ipcp.c

783

uint32_t nas_port;

usr.sbin/radiusd/radiusd_ipcp.c

84

uint32_t session_timeout;

usr.sbin/radiusd/radiusd_ipcp.c

90

uint32_t nas_port;

usr.sbin/radiusd/radiusd_ipcp.h

72

uint32_t ipackets;

usr.sbin/radiusd/radiusd_ipcp.h

73

uint32_t opackets;

usr.sbin/radiusd/radiusd_local.h

207

uint32_t, uint32_t, pid_t, int, void *, size_t);

usr.sbin/radiusd/radiusd_local.h

213

int imsg_compose_event(struct imsgev *, uint32_t, uint32_t, pid_t,

usr.sbin/radiusd/radiusd_local.h

215

int imsg_composev_event (struct imsgev *, uint32_t, uint32_t,

usr.sbin/radiusd/radiusd_local.h

43

uint32_t addr32[4];

usr.sbin/radiusd/radiusd_local.h

81

uint32_t capabilities;

usr.sbin/radiusd/radiusd_module.c

218

module_send_message(struct module_base *base, uint32_t cmd, const char *fmt,

usr.sbin/radiusd/radiusd_module.c

321

module_common_radpkt(struct module_base *base, uint32_t imsg_type, u_int q_id,

usr.sbin/radiusd/radiusd_module.c

684

module_imsg_compose(struct module_base *base, uint32_t type, uint32_t id,

usr.sbin/radiusd/radiusd_module.c

697

module_imsg_composev(struct module_base *base, uint32_t type, uint32_t id,

usr.sbin/radiusd/radiusd_module.c

81

static int module_common_radpkt(struct module_base *, uint32_t, u_int,

usr.sbin/radiusd/radiusd_module.h

75

int module_send_message(struct module_base *, uint32_t,

usr.sbin/radiusd/radiusd_module.h

91

int module_imsg_compose(struct module_base *, uint32_t,

usr.sbin/radiusd/radiusd_module.h

92

uint32_t, pid_t, int, const void *, size_t);

usr.sbin/radiusd/radiusd_module.h

93

int module_imsg_composev(struct module_base *, uint32_t,

usr.sbin/radiusd/radiusd_module.h

94

uint32_t, pid_t, int, const struct iovec *, int);

usr.sbin/radiusd/radiusd_standard.c

41

uint32_t vendor;

usr.sbin/radiusd/radiusd_standard.c

42

uint32_t vtype;

usr.sbin/radiusd/radiusd_standard.c

428

uint32_t u32val;

usr.sbin/radiusd/radiusd_standard.c

446

uint32_t u32val;

usr.sbin/rdsetroot/rdsetroot.c

168

ip = (uint32_t *) (dataseg + rd_root_size_off);

usr.sbin/rdsetroot/rdsetroot.c

49

uint32_t *ip;

usr.sbin/relayd/agentx_control.c

176

struct rdr *agentxctl_rdr_byidx(uint32_t, enum agentx_request_type);

usr.sbin/relayd/agentx_control.c

178

struct relay *agentxctl_relay_byidx(uint32_t, enum agentx_request_type);

usr.sbin/relayd/agentx_control.c

180

struct router *agentxctl_router_byidx(uint32_t, enum agentx_request_type);

usr.sbin/relayd/agentx_control.c

182

struct netroute *agentxctl_netroute_byidx(uint32_t, enum agentx_request_type);

usr.sbin/relayd/agentx_control.c

184

struct host *agentxctl_host_byidx(uint32_t, enum agentx_request_type);

usr.sbin/relayd/agentx_control.c

186

struct rsession *agentxctl_session_byidx(uint32_t, uint32_t,

usr.sbin/relayd/agentx_control.c

189

struct table *agentxctl_table_byidx(uint32_t, enum agentx_request_type);

usr.sbin/relayd/agentx_control.c

524

agentxctl_rdr_byidx(uint32_t instanceidx, enum agentx_request_type type)

usr.sbin/relayd/agentx_control.c

589

agentxctl_relay_byidx(uint32_t instanceidx, enum agentx_request_type type)

usr.sbin/relayd/agentx_control.c

641

agentx_varbind_gauge32(sav, (uint32_t)value);

usr.sbin/relayd/agentx_control.c

645

agentx_varbind_gauge32(sav, (uint32_t)value);

usr.sbin/relayd/agentx_control.c

649

agentx_varbind_gauge32(sav, (uint32_t)value);

usr.sbin/relayd/agentx_control.c

653

agentx_varbind_gauge32(sav, (uint32_t)value);

usr.sbin/relayd/agentx_control.c

657

agentx_varbind_gauge32(sav, (uint32_t)value);

usr.sbin/relayd/agentx_control.c

661

agentx_varbind_gauge32(sav, (uint32_t)value);

usr.sbin/relayd/agentx_control.c

666

agentxctl_router_byidx(uint32_t instanceidx, enum agentx_request_type type)

usr.sbin/relayd/agentx_control.c

721

agentxctl_netroute_byidx(uint32_t instanceidx, enum agentx_request_type type)

usr.sbin/relayd/agentx_control.c

776

agentxctl_host_byidx(uint32_t instanceidx, enum agentx_request_type type)

usr.sbin/relayd/agentx_control.c

855

agentxctl_session_byidx(uint32_t sessidx, uint32_t relayidx,

usr.sbin/relayd/agentx_control.c

950

agentxctl_table_byidx(uint32_t instanceidx, enum agentx_request_type type)

usr.sbin/relayd/proc.c

708

imsg_compose_event(struct imsgev *iev, uint16_t type, uint32_t peerid,

usr.sbin/relayd/proc.c

721

imsg_composev_event(struct imsgev *iev, uint16_t type, uint32_t peerid,

usr.sbin/relayd/proc.c

748

uint16_t type, uint32_t peerid, int fd, void *data, uint16_t datalen)

usr.sbin/relayd/proc.c

771

uint16_t type, uint32_t peerid, int fd, const struct iovec *iov, int iovcnt)

usr.sbin/relayd/relay.c

2079

uint32_t protocols = 0;

usr.sbin/relayd/relayd.h

1430

int imsg_compose_event(struct imsgev *, uint16_t, uint32_t,

usr.sbin/relayd/relayd.h

1432

int imsg_composev_event(struct imsgev *, uint16_t, uint32_t,

usr.sbin/relayd/relayd.h

719

uint32_t tt_keyrev;

usr.sbin/rpki-client/as.c

119

as_check_covered(uint32_t min, uint32_t max,

usr.sbin/rpki-client/as.c

123

uint32_t amin, amax;

usr.sbin/rpki-client/as.c

28

as_id_parse(const ASN1_INTEGER *v, uint32_t *out)

usr.sbin/rpki-client/aspa.c

278

insert_vap(struct vap *v, uint32_t idx, uint32_t *p)

usr.sbin/rpki-client/aspa.c

77

uint32_t provider = 0;

usr.sbin/rpki-client/ccr.c

1280

uint32_t prev = 0, provider;

usr.sbin/rpki-client/ccr.c

1334

uint32_t asid, prev = 0;

usr.sbin/rpki-client/ccr.c

1453

parse_routerkeys(const char *fn, struct ccr *ccr, uint32_t asid,

usr.sbin/rpki-client/ccr.c

1521

uint32_t asid, prev = 0;

usr.sbin/rpki-client/constraints.c

517

uint32_t min, max;

usr.sbin/rpki-client/extern.h

268

uint32_t asid; /* asID of ROA (if 0, RFC 6483 sec 4) */

usr.sbin/rpki-client/extern.h

311

uint32_t asid;

usr.sbin/rpki-client/extern.h

351

uint32_t custasid; /* the customerASID */

usr.sbin/rpki-client/extern.h

352

uint32_t *providers; /* the providers */

usr.sbin/rpki-client/extern.h

364

uint32_t custasid;

usr.sbin/rpki-client/extern.h

365

uint32_t *providers;

usr.sbin/rpki-client/extern.h

385

uint32_t asid;

usr.sbin/rpki-client/extern.h

405

uint32_t asid;

usr.sbin/rpki-client/extern.h

423

uint32_t asid;

usr.sbin/rpki-client/extern.h

43

uint32_t min; /* minimum non-zero */

usr.sbin/rpki-client/extern.h

44

uint32_t max; /* maximum */

usr.sbin/rpki-client/extern.h

54

uint32_t id; /* singular identifier */

usr.sbin/rpki-client/extern.h

617

uint32_t certs; /* certificates */

usr.sbin/rpki-client/extern.h

618

uint32_t certs_fail; /* invalid certificate */

usr.sbin/rpki-client/extern.h

619

uint32_t certs_nonfunc; /* non-functional CA certificates */

usr.sbin/rpki-client/extern.h

620

uint32_t mfts; /* total number of manifests */

usr.sbin/rpki-client/extern.h

621

uint32_t mfts_gap; /* manifests with sequence gaps */

usr.sbin/rpki-client/extern.h

622

uint32_t mfts_fail; /* failing syntactic parse */

usr.sbin/rpki-client/extern.h

623

uint32_t roas; /* route origin authorizations */

usr.sbin/rpki-client/extern.h

624

uint32_t roas_fail; /* failing syntactic parse */

usr.sbin/rpki-client/extern.h

625

uint32_t roas_invalid; /* invalid resources */

usr.sbin/rpki-client/extern.h

626

uint32_t aspas; /* ASPA objects */

usr.sbin/rpki-client/extern.h

627

uint32_t aspas_fail; /* ASPA objects failing syntactic parse */

usr.sbin/rpki-client/extern.h

628

uint32_t aspas_invalid; /* ASPAs with invalid customerASID */

usr.sbin/rpki-client/extern.h

629

uint32_t brks; /* number of BGPsec Router Key (BRK) certs */

usr.sbin/rpki-client/extern.h

630

uint32_t crls; /* revocation lists */

usr.sbin/rpki-client/extern.h

631

uint32_t taks; /* signed TAL objects */

usr.sbin/rpki-client/extern.h

632

uint32_t vaps; /* total number of Validated ASPA Payloads */

usr.sbin/rpki-client/extern.h

633

uint32_t vaps_uniqs; /* total number of unique VAPs */

usr.sbin/rpki-client/extern.h

634

uint32_t vaps_pas; /* total number of providers */

usr.sbin/rpki-client/extern.h

635

uint32_t vaps_overflowed; /* VAPs with too many providers */

usr.sbin/rpki-client/extern.h

636

uint32_t vrps; /* total number of Validated ROA Payloads */

usr.sbin/rpki-client/extern.h

637

uint32_t vrps_uniqs; /* number of unique vrps */

usr.sbin/rpki-client/extern.h

638

uint32_t spls; /* signed prefix list */

usr.sbin/rpki-client/extern.h

639

uint32_t spls_fail; /* failing syntactic parse */

usr.sbin/rpki-client/extern.h

640

uint32_t spls_invalid; /* invalid spls */

usr.sbin/rpki-client/extern.h

641

uint32_t vsps; /* total number of Validated SPL Payloads */

usr.sbin/rpki-client/extern.h

642

uint32_t vsps_uniqs; /* number of unique vsps */

usr.sbin/rpki-client/extern.h

646

uint32_t del_files; /* number of files removed in cleanup */

usr.sbin/rpki-client/extern.h

647

uint32_t extra_files; /* number of superfluous files */

usr.sbin/rpki-client/extern.h

648

uint32_t del_extra_files;/* number of removed extra files */

usr.sbin/rpki-client/extern.h

649

uint32_t del_dirs; /* number of dirs removed in cleanup */

usr.sbin/rpki-client/extern.h

650

uint32_t new_files; /* moved from DIR_TEMP to DIR_VALID */

usr.sbin/rpki-client/extern.h

655

uint32_t tals; /* total number of locators */

usr.sbin/rpki-client/extern.h

656

uint32_t repos; /* repositories */

usr.sbin/rpki-client/extern.h

657

uint32_t rsync_repos; /* synced rsync repositories */

usr.sbin/rpki-client/extern.h

658

uint32_t rsync_fails; /* failed rsync repositories */

usr.sbin/rpki-client/extern.h

659

uint32_t http_repos; /* synced http repositories */

usr.sbin/rpki-client/extern.h

660

uint32_t http_fails; /* failed http repositories */

usr.sbin/rpki-client/extern.h

661

uint32_t rrdp_repos; /* synced rrdp repositories */

usr.sbin/rpki-client/extern.h

662

uint32_t rrdp_fails; /* failed rrdp repositories */

usr.sbin/rpki-client/extern.h

663

uint32_t skiplistentries; /* number of skiplist entries */

usr.sbin/rpki-client/extern.h

832

int as_id_parse(const ASN1_INTEGER *, uint32_t *);

usr.sbin/rpki-client/extern.h

835

int as_check_covered(uint32_t, uint32_t,

usr.sbin/rpki-client/validate.c

36

valid_as(struct auth *a, uint32_t min, uint32_t max)

usr.sbin/rpki-client/validate.c

443

uint32_t min, max;

usr.sbin/rpki-client/validate.c

90

uint32_t min, max;

usr.sbin/sa/extern.h

49

uint32_t ci_flags; /* flags; see below */

usr.sbin/slaacctl/parser.h

31

uint32_t if_index;

usr.sbin/slowcgi/slowcgi.c

158

uint32_t app_status;

usr.sbin/slowcgi/slowcgi.c

703

uint32_t name_len, val_len;

usr.sbin/smtpd/bounce.c

58

uint32_t msgid;

usr.sbin/smtpd/control.c

38

uint32_t id;

usr.sbin/smtpd/control.c

422

uint32_t msgid;

usr.sbin/smtpd/envelope.c

227

ascii_load_uint32(uint32_t *dest, char *buf)

usr.sbin/smtpd/envelope.c

498

ascii_dump_uint32(uint32_t src, char *dest, size_t len)

usr.sbin/smtpd/esc.c

110

uint32_t i;

usr.sbin/smtpd/lka.c

79

uint32_t msgid;

usr.sbin/smtpd/lka.c

80

uint32_t subsystems;

usr.sbin/smtpd/lka_filter.c

103

uint32_t phases;

usr.sbin/smtpd/lka_filter.c

1507

lka_report_smtp_tx_reset(const char *direction, struct timeval *tv, uint64_t reqid, uint32_t msgid)

usr.sbin/smtpd/lka_filter.c

1514

lka_report_smtp_tx_begin(const char *direction, struct timeval *tv, uint64_t reqid, uint32_t msgid)

usr.sbin/smtpd/lka_filter.c

1521

lka_report_smtp_tx_mail(const char *direction, struct timeval *tv, uint64_t reqid, uint32_t msgid, const char *address, int ok)

usr.sbin/smtpd/lka_filter.c

1541

lka_report_smtp_tx_rcpt(const char *direction, struct timeval *tv, uint64_t reqid, uint32_t msgid, const char *address, int ok)

usr.sbin/smtpd/lka_filter.c

1561

lka_report_smtp_tx_envelope(const char *direction, struct timeval *tv, uint64_t reqid, uint32_t msgid, uint64_t evpid)

usr.sbin/smtpd/lka_filter.c

1568

lka_report_smtp_tx_data(const char *direction, struct timeval *tv, uint64_t reqid, uint32_t msgid, int ok)

usr.sbin/smtpd/lka_filter.c

1588

lka_report_smtp_tx_commit(const char *direction, struct timeval *tv, uint64_t reqid, uint32_t msgid, size_t msgsz)

usr.sbin/smtpd/lka_filter.c

1595

lka_report_smtp_tx_rollback(const char *direction, struct timeval *tv, uint64_t reqid, uint32_t msgid)

usr.sbin/smtpd/lka_filter.c

173

uint32_t subsystems;

usr.sbin/smtpd/lka_filter.c

209

lka_proc_forked(const char *name, const char *tag, uint32_t subsystems, int fd)

usr.sbin/smtpd/mproc.c

224

m_compose(struct mproc *p, uint32_t type, uint32_t peerid, pid_t pid, int fd,

usr.sbin/smtpd/mproc.c

241

m_composev(struct mproc *p, uint32_t type, uint32_t peerid, pid_t pid,

usr.sbin/smtpd/mproc.c

265

m_create(struct mproc *p, uint32_t type, uint32_t peerid, pid_t pid, int fd)

usr.sbin/smtpd/mproc.c

394

m_add_u32(struct mproc *m, uint32_t u32)

usr.sbin/smtpd/mproc.c

449

m_add_msgid(struct mproc *m, uint32_t v)

usr.sbin/smtpd/mproc.c

503

m_get_u32(struct msg *m, uint32_t *u32)

usr.sbin/smtpd/mproc.c

575

m_get_msgid(struct msg *m, uint32_t *msgid)

usr.sbin/smtpd/mta.c

1999

mta_relay_show(struct mta_relay *r, struct mproc *p, uint32_t id, time_t t)

usr.sbin/smtpd/mta.c

479

uint32_t protos;

usr.sbin/smtpd/mta.c

74

static void mta_relay_show(struct mta_relay *, struct mproc *, uint32_t, time_t);

usr.sbin/smtpd/mta_session.c

167

static void mta_report_tx_reset(struct mta_session *, uint32_t);

usr.sbin/smtpd/mta_session.c

168

static void mta_report_tx_begin(struct mta_session *, uint32_t);

usr.sbin/smtpd/mta_session.c

169

static void mta_report_tx_mail(struct mta_session *, uint32_t, const char *, int);

usr.sbin/smtpd/mta_session.c

170

static void mta_report_tx_rcpt(struct mta_session *, uint32_t, const char *, int);

usr.sbin/smtpd/mta_session.c

171

static void mta_report_tx_envelope(struct mta_session *, uint32_t, uint64_t);

usr.sbin/smtpd/mta_session.c

172

static void mta_report_tx_data(struct mta_session *, uint32_t, int);

usr.sbin/smtpd/mta_session.c

173

static void mta_report_tx_commit(struct mta_session *, uint32_t, size_t);

usr.sbin/smtpd/mta_session.c

174

static void mta_report_tx_rollback(struct mta_session *, uint32_t);

usr.sbin/smtpd/mta_session.c

1807

mta_report_tx_reset(struct mta_session *s, uint32_t msgid)

usr.sbin/smtpd/mta_session.c

1816

mta_report_tx_begin(struct mta_session *s, uint32_t msgid)

usr.sbin/smtpd/mta_session.c

1825

mta_report_tx_mail(struct mta_session *s, uint32_t msgid, const char *address, int ok)

usr.sbin/smtpd/mta_session.c

1834

mta_report_tx_rcpt(struct mta_session *s, uint32_t msgid, const char *address, int ok)

usr.sbin/smtpd/mta_session.c

1843

mta_report_tx_envelope(struct mta_session *s, uint32_t msgid, uint64_t evpid)

usr.sbin/smtpd/mta_session.c

1852

mta_report_tx_data(struct mta_session *s, uint32_t msgid, int ok)

usr.sbin/smtpd/mta_session.c

1861

mta_report_tx_commit(struct mta_session *s, uint32_t msgid, size_t msgsz)

usr.sbin/smtpd/mta_session.c

1870

mta_report_tx_rollback(struct mta_session *s, uint32_t msgid)

usr.sbin/smtpd/parse.y

139

uint32_t options;

usr.sbin/smtpd/parse.y

98

static uint32_t last_dynchain_id = 1;

usr.sbin/smtpd/parser.c

37

uint32_t text_to_msgid(const char *);

usr.sbin/smtpd/parser.h

34

uint32_t u_msgid;

usr.sbin/smtpd/proxy.c

57

uint32_t src_addr;

usr.sbin/smtpd/proxy.c

58

uint32_t dst_addr;

usr.sbin/smtpd/queue.c

51

uint32_t msgid;

usr.sbin/smtpd/queue.c

677

static uint32_t msgid = 0;

usr.sbin/smtpd/queue_backend.c

159

queue_message_create(uint32_t *msgid)

usr.sbin/smtpd/queue_backend.c

175

queue_message_delete(uint32_t msgid)

usr.sbin/smtpd/queue_backend.c

208

queue_message_commit(uint32_t msgid)

usr.sbin/smtpd/queue_backend.c

285

queue_message_fd_r(uint32_t msgid)

usr.sbin/smtpd/queue_backend.c

362

queue_message_fd_rw(uint32_t msgid)

usr.sbin/smtpd/queue_backend.c

490

uint32_t msgid;

usr.sbin/smtpd/queue_backend.c

50

static int (*handler_message_create)(uint32_t *);

usr.sbin/smtpd/queue_backend.c

51

static int (*handler_message_commit)(uint32_t, const char*);

usr.sbin/smtpd/queue_backend.c

52

static int (*handler_message_delete)(uint32_t);

usr.sbin/smtpd/queue_backend.c

53

static int (*handler_message_fd_r)(uint32_t);

usr.sbin/smtpd/queue_backend.c

54

static int (*handler_envelope_create)(uint32_t, const char *, size_t, uint64_t *);

usr.sbin/smtpd/queue_backend.c

60

uint32_t, int *, void **);

usr.sbin/smtpd/queue_backend.c

606

queue_message_walk(struct envelope *ep, uint32_t msgid, int *done, void **data)

usr.sbin/smtpd/queue_backend.c

675

uint32_t

usr.sbin/smtpd/queue_backend.c

678

uint32_t msgid;

usr.sbin/smtpd/queue_backend.c

687

queue_generate_evpid(uint32_t msgid)

usr.sbin/smtpd/queue_backend.c

689

uint32_t rnd;

usr.sbin/smtpd/queue_backend.c

734

queue_api_on_message_create(int(*cb)(uint32_t *))

usr.sbin/smtpd/queue_backend.c

740

queue_api_on_message_commit(int(*cb)(uint32_t, const char *))

usr.sbin/smtpd/queue_backend.c

746

queue_api_on_message_delete(int(*cb)(uint32_t))

usr.sbin/smtpd/queue_backend.c

752

queue_api_on_message_fd_r(int(*cb)(uint32_t))

usr.sbin/smtpd/queue_backend.c

758

queue_api_on_envelope_create(int(*cb)(uint32_t, const char *, size_t, uint64_t *))

usr.sbin/smtpd/queue_backend.c

789

uint32_t, int *, void **))

usr.sbin/smtpd/queue_backend.c

96

queue_message_path(uint32_t msgid, char *buf, size_t len)

usr.sbin/smtpd/queue_fs.c

108

queue_fs_message_commit(uint32_t msgid, const char *path)

usr.sbin/smtpd/queue_fs.c

162

queue_fs_message_fd_r(uint32_t msgid)

usr.sbin/smtpd/queue_fs.c

181

queue_fs_message_delete(uint32_t msgid)

usr.sbin/smtpd/queue_fs.c

199

queue_fs_envelope_create(uint32_t msgid, const char *buf, size_t len,

usr.sbin/smtpd/queue_fs.c

284

uint32_t msgid;

usr.sbin/smtpd/queue_fs.c

306

uint32_t msgid, int *done, void **data)

usr.sbin/smtpd/queue_fs.c

374

uint32_t msgid;

usr.sbin/smtpd/queue_fs.c

529

fsqueue_message_path(uint32_t msgid, char *buf, size_t len)

usr.sbin/smtpd/queue_fs.c

539

fsqueue_message_incoming_path(uint32_t msgid, char *buf, size_t len)

usr.sbin/smtpd/queue_fs.c

55

static void fsqueue_message_path(uint32_t, char *, size_t);

usr.sbin/smtpd/queue_fs.c

56

static void fsqueue_message_incoming_path(uint32_t, char *, size_t);

usr.sbin/smtpd/queue_fs.c

67

queue_fs_message_create(uint32_t *msgid)

usr.sbin/smtpd/queue_null.c

22

queue_null_message_create(uint32_t *msgid)

usr.sbin/smtpd/queue_null.c

29

queue_null_message_commit(uint32_t msgid, const char *path)

usr.sbin/smtpd/queue_null.c

35

queue_null_message_delete(uint32_t msgid)

usr.sbin/smtpd/queue_null.c

41

queue_null_message_fd_r(uint32_t msgid)

usr.sbin/smtpd/queue_null.c

47

queue_null_envelope_create(uint32_t msgid, const char *buf, size_t len,

usr.sbin/smtpd/queue_proc.c

113

queue_proc_message_create(uint32_t *msgid)

usr.sbin/smtpd/queue_proc.c

129

queue_proc_message_commit(uint32_t msgid, const char *path)

usr.sbin/smtpd/queue_proc.c

150

queue_proc_message_delete(uint32_t msgid)

usr.sbin/smtpd/queue_proc.c

165

queue_proc_message_fd_r(uint32_t msgid)

usr.sbin/smtpd/queue_proc.c

177

queue_proc_envelope_create(uint32_t msgid, const char *buf, size_t len,

usr.sbin/smtpd/queue_proc.c

287

uint32_t version;

usr.sbin/smtpd/queue_ram.c

123

queue_ram_message_delete(uint32_t msgid)

usr.sbin/smtpd/queue_ram.c

145

queue_ram_message_fd_r(uint32_t msgid)

usr.sbin/smtpd/queue_ram.c

189

queue_ram_envelope_create(uint32_t msgid, const char *buf, size_t len,

usr.sbin/smtpd/queue_ram.c

42

get_message(uint32_t msgid)

usr.sbin/smtpd/queue_ram.c

54

queue_ram_message_create(uint32_t *msgid)

usr.sbin/smtpd/queue_ram.c

75

queue_ram_message_commit(uint32_t msgid, const char *path)

usr.sbin/smtpd/report_smtp.c

119

report_smtp_tx_reset(const char *direction, uint64_t qid, uint32_t msgid)

usr.sbin/smtpd/report_smtp.c

134

report_smtp_tx_begin(const char *direction, uint64_t qid, uint32_t msgid)

usr.sbin/smtpd/report_smtp.c

149

report_smtp_tx_mail(const char *direction, uint64_t qid, uint32_t msgid, const char *address, int ok)

usr.sbin/smtpd/report_smtp.c

166

report_smtp_tx_rcpt(const char *direction, uint64_t qid, uint32_t msgid, const char *address, int ok)

usr.sbin/smtpd/report_smtp.c

183

report_smtp_tx_envelope(const char *direction, uint64_t qid, uint32_t msgid, uint64_t evpid)

usr.sbin/smtpd/report_smtp.c

199

report_smtp_tx_data(const char *direction, uint64_t qid, uint32_t msgid, int ok)

usr.sbin/smtpd/report_smtp.c

215

report_smtp_tx_commit(const char *direction, uint64_t qid, uint32_t msgid, size_t msgsz)

usr.sbin/smtpd/report_smtp.c

231

report_smtp_tx_rollback(const char *direction, uint64_t qid, uint32_t msgid)

usr.sbin/smtpd/resolver.c

159

uint32_t reqid;

usr.sbin/smtpd/resolver.c

35

uint32_t id;

usr.sbin/smtpd/resolver.c

44

uint32_t reqid;

usr.sbin/smtpd/scheduler.c

302

msgid = *(uint32_t *)(imsg->data);

usr.sbin/smtpd/scheduler.c

40

static uint32_t *msgids;

usr.sbin/smtpd/scheduler.c

53

uint32_t msgid;

usr.sbin/smtpd/scheduler.c

54

uint32_t inflight;

usr.sbin/smtpd/scheduler_null.c

140

scheduler_null_messages(uint32_t from, uint32_t *dst, size_t size)

usr.sbin/smtpd/scheduler_null.c

23

static size_t scheduler_null_commit(uint32_t);

usr.sbin/smtpd/scheduler_null.c

24

static size_t scheduler_null_rollback(uint32_t);

usr.sbin/smtpd/scheduler_null.c

30

static size_t scheduler_null_messages(uint32_t, uint32_t *, size_t);

usr.sbin/smtpd/scheduler_null.c

72

scheduler_null_commit(uint32_t msgid)

usr.sbin/smtpd/scheduler_null.c

78

scheduler_null_rollback(uint32_t msgid)

usr.sbin/smtpd/scheduler_proc.c

101

uint32_t version;

usr.sbin/smtpd/scheduler_proc.c

138

scheduler_proc_commit(uint32_t msgid)

usr.sbin/smtpd/scheduler_proc.c

155

scheduler_proc_rollback(uint32_t msgid)

usr.sbin/smtpd/scheduler_proc.c

292

scheduler_proc_messages(uint32_t from, uint32_t *dst, size_t size)

usr.sbin/smtpd/scheduler_ramqueue.c

155

scheduler_backoff(time_t t0, time_t base, uint32_t step)

usr.sbin/smtpd/scheduler_ramqueue.c

161

scheduler_next(time_t t0, time_t base, uint32_t step)

usr.sbin/smtpd/scheduler_ramqueue.c

190

uint32_t msgid;

usr.sbin/smtpd/scheduler_ramqueue.c

236

scheduler_ram_commit(uint32_t msgid)

usr.sbin/smtpd/scheduler_ramqueue.c

263

scheduler_ram_rollback(uint32_t msgid)

usr.sbin/smtpd/scheduler_ramqueue.c

291

uint32_t msgid;

usr.sbin/smtpd/scheduler_ramqueue.c

31

uint32_t msgid;

usr.sbin/smtpd/scheduler_ramqueue.c

333

uint32_t msgid;

usr.sbin/smtpd/scheduler_ramqueue.c

360

uint32_t msgid;

usr.sbin/smtpd/scheduler_ramqueue.c

587

scheduler_ram_messages(uint32_t from, uint32_t *dst, size_t size)

usr.sbin/smtpd/scheduler_ramqueue.c

659

uint32_t msgid;

usr.sbin/smtpd/scheduler_ramqueue.c

697

uint32_t msgid;

usr.sbin/smtpd/scheduler_ramqueue.c

731

uint32_t msgid;

usr.sbin/smtpd/scheduler_ramqueue.c

765

uint32_t msgid;

usr.sbin/smtpd/scheduler_ramqueue.c

797

uint32_t msgid;

usr.sbin/smtpd/scheduler_ramqueue.c

92

static size_t scheduler_ram_commit(uint32_t);

usr.sbin/smtpd/scheduler_ramqueue.c

93

static size_t scheduler_ram_rollback(uint32_t);

usr.sbin/smtpd/scheduler_ramqueue.c

99

static size_t scheduler_ram_messages(uint32_t, uint32_t *, size_t);

usr.sbin/smtpd/smtp.c

157

uint32_t protos;

usr.sbin/smtpd/smtp_session.c

247

static void smtp_report_tx_reset(struct smtp_session *, uint32_t);

usr.sbin/smtpd/smtp_session.c

248

static void smtp_report_tx_begin(struct smtp_session *, uint32_t);

usr.sbin/smtpd/smtp_session.c

249

static void smtp_report_tx_mail(struct smtp_session *, uint32_t, const char *, int);

usr.sbin/smtpd/smtp_session.c

250

static void smtp_report_tx_rcpt(struct smtp_session *, uint32_t, const char *, int);

usr.sbin/smtpd/smtp_session.c

251

static void smtp_report_tx_envelope(struct smtp_session *, uint32_t, uint64_t);

usr.sbin/smtpd/smtp_session.c

252

static void smtp_report_tx_data(struct smtp_session *, uint32_t, int);

usr.sbin/smtpd/smtp_session.c

253

static void smtp_report_tx_commit(struct smtp_session *, uint32_t, size_t);

usr.sbin/smtpd/smtp_session.c

254

static void smtp_report_tx_rollback(struct smtp_session *, uint32_t);

usr.sbin/smtpd/smtp_session.c

2979

smtp_report_tx_reset(struct smtp_session *s, uint32_t msgid)

usr.sbin/smtpd/smtp_session.c

2988

smtp_report_tx_begin(struct smtp_session *s, uint32_t msgid)

usr.sbin/smtpd/smtp_session.c

2997

smtp_report_tx_mail(struct smtp_session *s, uint32_t msgid, const char *address, int ok)

usr.sbin/smtpd/smtp_session.c

3016

smtp_report_tx_rcpt(struct smtp_session *s, uint32_t msgid, const char *address, int ok)

usr.sbin/smtpd/smtp_session.c

3035

smtp_report_tx_envelope(struct smtp_session *s, uint32_t msgid, uint64_t evpid)

usr.sbin/smtpd/smtp_session.c

3044

smtp_report_tx_data(struct smtp_session *s, uint32_t msgid, int ok)

usr.sbin/smtpd/smtp_session.c

3053

smtp_report_tx_commit(struct smtp_session *s, uint32_t msgid, size_t msgsz)

usr.sbin/smtpd/smtp_session.c

3062

smtp_report_tx_rollback(struct smtp_session *s, uint32_t msgid)

usr.sbin/smtpd/smtp_session.c

701

uint32_t msgid;

usr.sbin/smtpd/smtp_session.c

98

uint32_t msgid;

usr.sbin/smtpd/smtpc.c

127

uint32_t protos;

usr.sbin/smtpd/smtpctl.c

311

srv_iter_messages(uint32_t *res)

usr.sbin/smtpd/smtpctl.c

313

static uint32_t *msgids = NULL, from = 0;

usr.sbin/smtpd/smtpctl.c

349

srv_iter_envelopes(uint32_t msgid, struct envelope *evp)

usr.sbin/smtpd/smtpctl.c

351

static uint32_t currmsgid = 0;

usr.sbin/smtpd/smtpctl.c

402

srv_iter_evpids(uint32_t msgid, uint64_t *evpid, int *offset)

usr.sbin/smtpd/smtpctl.c

434

uint32_t msgid;

usr.sbin/smtpd/smtpctl.c

723

uint32_t msgid;

usr.sbin/smtpd/smtpctl.c

746

uint32_t msgid;

usr.sbin/smtpd/smtpctl.c

873

uint32_t sc_flags;

usr.sbin/smtpd/smtpctl.c

992

uint32_t msgid;

usr.sbin/smtpd/smtpd-api.h

120

uint32_t version;

usr.sbin/smtpd/smtpd-api.h

226

static inline uint32_t

usr.sbin/smtpd/smtpd-api.h

233

msgid_to_evpid(uint32_t msgid)

usr.sbin/smtpd/smtpd-api.h

246

void queue_api_on_message_create(int(*)(uint32_t *));

usr.sbin/smtpd/smtpd-api.h

247

void queue_api_on_message_commit(int(*)(uint32_t, const char*));

usr.sbin/smtpd/smtpd-api.h

248

void queue_api_on_message_delete(int(*)(uint32_t));

usr.sbin/smtpd/smtpd-api.h

249

void queue_api_on_message_fd_r(int(*)(uint32_t));

usr.sbin/smtpd/smtpd-api.h

250

void queue_api_on_envelope_create(int(*)(uint32_t, const char *, size_t, uint64_t *));

usr.sbin/smtpd/smtpd-api.h

256

uint32_t, int *, void **));

usr.sbin/smtpd/smtpd-api.h

265

void scheduler_api_on_commit(size_t(*)(uint32_t));

usr.sbin/smtpd/smtpd-api.h

266

void scheduler_api_on_rollback(size_t(*)(uint32_t));

usr.sbin/smtpd/smtpd-api.h

272

void scheduler_api_on_messages(size_t(*)(uint32_t, uint32_t *, size_t));

usr.sbin/smtpd/smtpd.c

1348

m_add_u32(p_lka, (uint32_t)fp->filter_subsystem);

usr.sbin/smtpd/smtpd.h

1148

uint32_t msgid;

usr.sbin/smtpd/smtpd.h

1149

uint32_t peerid;

usr.sbin/smtpd/smtpd.h

1357

void lka_proc_forked(const char *, const char *, uint32_t, int);

usr.sbin/smtpd/smtpd.h

1373

void lka_report_smtp_tx_reset(const char *, struct timeval *, uint64_t, uint32_t);

usr.sbin/smtpd/smtpd.h

1374

void lka_report_smtp_tx_begin(const char *, struct timeval *, uint64_t, uint32_t);

usr.sbin/smtpd/smtpd.h

1375

void lka_report_smtp_tx_mail(const char *, struct timeval *, uint64_t, uint32_t, const char *, int);

usr.sbin/smtpd/smtpd.h

1376

void lka_report_smtp_tx_rcpt(const char *, struct timeval *, uint64_t, uint32_t, const char *, int);

usr.sbin/smtpd/smtpd.h

1377

void lka_report_smtp_tx_envelope(const char *, struct timeval *, uint64_t, uint32_t, uint64_t);

usr.sbin/smtpd/smtpd.h

1378

void lka_report_smtp_tx_commit(const char *, struct timeval *, uint64_t, uint32_t, size_t);

usr.sbin/smtpd/smtpd.h

1379

void lka_report_smtp_tx_data(const char *, struct timeval *, uint64_t, uint32_t, int);

usr.sbin/smtpd/smtpd.h

1380

void lka_report_smtp_tx_rollback(const char *, struct timeval *, uint64_t, uint32_t);

usr.sbin/smtpd/smtpd.h

1451

void m_compose(struct mproc *, uint32_t, uint32_t, pid_t, int, void *, size_t);

usr.sbin/smtpd/smtpd.h

1452

void m_composev(struct mproc *, uint32_t, uint32_t, pid_t, int,

usr.sbin/smtpd/smtpd.h

1455

void m_create(struct mproc *, uint32_t, uint32_t, pid_t, int);

usr.sbin/smtpd/smtpd.h

1458

void m_add_u32(struct mproc *, uint32_t);

usr.sbin/smtpd/smtpd.h

1465

void m_add_msgid(struct mproc *, uint32_t);

usr.sbin/smtpd/smtpd.h

1479

void m_get_u32(struct msg *, uint32_t *);

usr.sbin/smtpd/smtpd.h

1485

void m_get_msgid(struct msg *, uint32_t *);

usr.sbin/smtpd/smtpd.h

1525

uint32_t queue_generate_msgid(void);

usr.sbin/smtpd/smtpd.h

1526

uint64_t queue_generate_evpid(uint32_t);

usr.sbin/smtpd/smtpd.h

1529

int queue_message_create(uint32_t *);

usr.sbin/smtpd/smtpd.h

1530

int queue_message_delete(uint32_t);

usr.sbin/smtpd/smtpd.h

1531

int queue_message_commit(uint32_t);

usr.sbin/smtpd/smtpd.h

1532

int queue_message_fd_r(uint32_t);

usr.sbin/smtpd/smtpd.h

1533

int queue_message_fd_rw(uint32_t);

usr.sbin/smtpd/smtpd.h

1539

int queue_message_walk(struct envelope *, uint32_t, int *, void **);

usr.sbin/smtpd/smtpd.h

1550

void report_smtp_tx_reset(const char *, uint64_t, uint32_t);

usr.sbin/smtpd/smtpd.h

1551

void report_smtp_tx_begin(const char *, uint64_t, uint32_t);

usr.sbin/smtpd/smtpd.h

1552

void report_smtp_tx_mail(const char *, uint64_t, uint32_t, const char *, int);

usr.sbin/smtpd/smtpd.h

1553

void report_smtp_tx_rcpt(const char *, uint64_t, uint32_t, const char *, int);

usr.sbin/smtpd/smtpd.h

1554

void report_smtp_tx_envelope(const char *, uint64_t, uint32_t, uint64_t);

usr.sbin/smtpd/smtpd.h

1555

void report_smtp_tx_data(const char *, uint64_t, uint32_t, int);

usr.sbin/smtpd/smtpd.h

1556

void report_smtp_tx_commit(const char *, uint64_t, uint32_t, size_t);

usr.sbin/smtpd/smtpd.h

1557

void report_smtp_tx_rollback(const char *, uint64_t, uint32_t);

usr.sbin/smtpd/smtpd.h

1643

int table_check_use(struct table *, uint32_t, uint32_t);

usr.sbin/smtpd/smtpd.h

1644

int table_check_type(struct table *, uint32_t);

usr.sbin/smtpd/smtpd.h

1645

int table_check_service(struct table *, uint32_t);

usr.sbin/smtpd/smtpd.h

1669

uint32_t text_to_msgid(const char *);

usr.sbin/smtpd/smtpd.h

481

uint32_t version;

usr.sbin/smtpd/smtpd.h

554

uint32_t sc_opts;

usr.sbin/smtpd/smtpd.h

564

uint32_t sc_flags;

usr.sbin/smtpd/smtpd.h

569

uint32_t sc_queue_flags;

usr.sbin/smtpd/smtpd.h

869

uint32_t msgid;

usr.sbin/smtpd/smtpd.h

901

size_t (*commit)(uint32_t);

usr.sbin/smtpd/smtpd.h

902

size_t (*rollback)(uint32_t);

usr.sbin/smtpd/smtpd.h

911

size_t (*messages)(uint32_t, uint32_t *, size_t);

usr.sbin/smtpd/smtpd.h

984

uint32_t m_type;

usr.sbin/smtpd/smtpd.h

985

uint32_t m_peerid;

usr.sbin/smtpd/table.c

340

table_check_type(struct table *t, uint32_t mask)

usr.sbin/smtpd/table.c

346

table_check_service(struct table *t, uint32_t mask)

usr.sbin/smtpd/table.c

352

table_check_use(struct table *t, uint32_t tmask, uint32_t smask)

usr.sbin/smtpd/to.c

392

uint32_t

usr.sbin/smtpd/unpack_dns.c

25

static int unpack_u32(struct unpack *, uint32_t *);

usr.sbin/smtpd/unpack_dns.c

255

unpack_u32(struct unpack *p, uint32_t *u32)

usr.sbin/smtpd/unpack_dns.h

51

uint32_t rr_ttl;

usr.sbin/smtpd/unpack_dns.h

69

uint32_t serial;

usr.sbin/smtpd/unpack_dns.h

70

uint32_t refresh;

usr.sbin/smtpd/unpack_dns.h

71

uint32_t retry;

usr.sbin/smtpd/unpack_dns.h

72

uint32_t expire;

usr.sbin/smtpd/unpack_dns.h

73

uint32_t minimum;

usr.sbin/smtpd/util.c

680

static uint32_t id;

usr.sbin/snmpd/application.c

137

uint32_t snmp_unavailablecontexts;

usr.sbin/snmpd/application.c

138

uint32_t snmp_unknowncontexts;

usr.sbin/snmpd/application.c

142

enum appl_error appl_region(struct appl_context *, uint32_t, uint8_t,

usr.sbin/snmpd/application.c

348

uint32_t

usr.sbin/snmpd/application.c

42

(sizeof((uint32_t []) { __VA_ARGS__ }) / sizeof(uint32_t)) }

usr.sbin/snmpd/application.c

479

appl_region(struct appl_context *ctx, uint32_t timeout, uint8_t priority,

usr.sbin/snmpd/application.c

49

uint32_t aa_index;

usr.sbin/snmpd/application.c

52

uint32_t aa_uptime;

usr.sbin/snmpd/application.c

568

appl_register(const char *ctxname, uint32_t timeout, uint8_t priority,

usr.sbin/snmpd/application.c

570

uint32_t upper_bound, struct appl_backend *backend)

usr.sbin/snmpd/application.c

577

uint32_t lower_bound;

usr.sbin/snmpd/application.c

64

uint32_t ac_agentcap_lastchange;

usr.sbin/snmpd/application.c

680

uint8_t range_subid, uint32_t upper_bound, struct appl_backend *backend)

usr.sbin/snmpd/application.c

685

uint32_t lower_bound;

usr.sbin/snmpd/application.c

899

static uint32_t transactionid;

usr.sbin/snmpd/application.h

126

uint32_t appl_sysuptime(const char *);

usr.sbin/snmpd/application.h

135

enum appl_error appl_register(const char *, uint32_t, uint8_t, struct ber_oid *,

usr.sbin/snmpd/application.h

136

int, int, uint8_t, uint32_t, struct appl_backend *);

usr.sbin/snmpd/application.h

138

uint8_t, uint32_t, struct appl_backend *);

usr.sbin/snmpd/application_agentx.c

45

uint32_t conn_id;

usr.sbin/snmpd/application_agentx.c

62

uint32_t sess_id;

usr.sbin/snmpd/application_agentx.c

650

uint32_t timeout;

usr.sbin/snmpd/ax.c

1098

ax_oid_add(struct ax_oid *oid, uint32_t value)

usr.sbin/snmpd/ax.c

1106

static uint32_t

usr.sbin/snmpd/ax.c

1110

uint32_t packetid, plength;

usr.sbin/snmpd/ax.c

1127

uint32_t sessionid, uint32_t transactionid, uint32_t packetid,

usr.sbin/snmpd/ax.c

1175

ax_pdu_add_uint32(struct ax *ax, uint32_t value)

usr.sbin/snmpd/ax.c

1339

static uint32_t

usr.sbin/snmpd/ax.c

1342

uint32_t value;

usr.sbin/snmpd/ax.c

37

enum ax_pdu_type, uint8_t, uint32_t, uint32_t, uint32_t,

usr.sbin/snmpd/ax.c

39

static uint32_t ax_pdu_queue(struct ax *);

usr.sbin/snmpd/ax.c

41

static int ax_pdu_add_uint32(struct ax *, uint32_t);

usr.sbin/snmpd/ax.c

49

static uint32_t ax_pdutoh32(struct ax_pdu_header *, uint8_t *);

usr.sbin/snmpd/ax.c

502

uint32_t

usr.sbin/snmpd/ax.c

521

uint32_t

usr.sbin/snmpd/ax.c

522

ax_close(struct ax *ax, uint32_t sessionid,

usr.sbin/snmpd/ax.c

539

ax_get(struct ax *ax, uint32_t sessionid, uint32_t transactionid,

usr.sbin/snmpd/ax.c

540

uint32_t packetid, struct ax_ostring *context, struct ax_searchrange *srl,

usr.sbin/snmpd/ax.c

558

ax_getnext(struct ax *ax, uint32_t sessionid, uint32_t transactionid,

usr.sbin/snmpd/ax.c

559

uint32_t packetid, struct ax_ostring *context, struct ax_searchrange *srl,

usr.sbin/snmpd/ax.c

576

uint32_t

usr.sbin/snmpd/ax.c

577

ax_indexallocate(struct ax *ax, uint8_t flags, uint32_t sessionid,

usr.sbin/snmpd/ax.c

595

uint32_t

usr.sbin/snmpd/ax.c

596

ax_indexdeallocate(struct ax *ax, uint32_t sessionid,

usr.sbin/snmpd/ax.c

609

uint32_t

usr.sbin/snmpd/ax.c

610

ax_addagentcaps(struct ax *ax, uint32_t sessionid,

usr.sbin/snmpd/ax.c

625

uint32_t

usr.sbin/snmpd/ax.c

626

ax_removeagentcaps(struct ax *ax, uint32_t sessionid,

usr.sbin/snmpd/ax.c

639

uint32_t

usr.sbin/snmpd/ax.c

640

ax_register(struct ax *ax, uint8_t flags, uint32_t sessionid,

usr.sbin/snmpd/ax.c

642

uint8_t range_subid, struct ax_oid *subtree, uint32_t upperbound)

usr.sbin/snmpd/ax.c

669

uint32_t

usr.sbin/snmpd/ax.c

670

ax_unregister(struct ax *ax, uint32_t sessionid,

usr.sbin/snmpd/ax.c

672

struct ax_oid *subtree, uint32_t upperbound)

usr.sbin/snmpd/ax.c

695

ax_response(struct ax *ax, uint32_t sessionid, uint32_t transactionid,

usr.sbin/snmpd/ax.c

696

uint32_t packetid, uint32_t sysuptime, uint16_t error, uint16_t index,

usr.sbin/snmpd/ax.c

909

uint32_t upperbound)

usr.sbin/snmpd/ax.h

137

uint32_t aoi_id[AX_OID_MAX_LEN];

usr.sbin/snmpd/ax.h

143

uint32_t aos_slen;

usr.sbin/snmpd/ax.h

157

uint32_t aph_sessionid;

usr.sbin/snmpd/ax.h

158

uint32_t aph_transactionid;

usr.sbin/snmpd/ax.h

159

uint32_t aph_packetid;

usr.sbin/snmpd/ax.h

160

uint32_t aph_plength;

usr.sbin/snmpd/ax.h

168

uint32_t avb_uint32;

usr.sbin/snmpd/ax.h

192

uint32_t ap_upper_bound;

usr.sbin/snmpd/ax.h

198

uint32_t ap_upper_bound;

usr.sbin/snmpd/ax.h

221

uint32_t ap_uptime;

usr.sbin/snmpd/ax.h

234

uint32_t ax_open(struct ax *, uint8_t, struct ax_oid *,

usr.sbin/snmpd/ax.h

236

uint32_t ax_close(struct ax *, uint32_t, enum ax_close_reason);

usr.sbin/snmpd/ax.h

237

int ax_get(struct ax *, uint32_t, uint32_t, uint32_t, struct ax_ostring *,

usr.sbin/snmpd/ax.h

239

int ax_getnext(struct ax *, uint32_t, uint32_t, uint32_t, struct ax_ostring *,

usr.sbin/snmpd/ax.h

241

uint32_t ax_indexallocate(struct ax *, uint8_t, uint32_t,

usr.sbin/snmpd/ax.h

243

uint32_t ax_indexdeallocate(struct ax *, uint32_t,

usr.sbin/snmpd/ax.h

245

uint32_t ax_addagentcaps(struct ax *, uint32_t, struct ax_ostring *,

usr.sbin/snmpd/ax.h

247

uint32_t ax_removeagentcaps(struct ax *, uint32_t,

usr.sbin/snmpd/ax.h

249

uint32_t ax_register(struct ax *, uint8_t, uint32_t,

usr.sbin/snmpd/ax.h

251

uint32_t);

usr.sbin/snmpd/ax.h

252

uint32_t ax_unregister(struct ax *, uint32_t, struct ax_ostring *,

usr.sbin/snmpd/ax.h

253

uint8_t, uint8_t, struct ax_oid *, uint32_t);

usr.sbin/snmpd/ax.h

254

int ax_response(struct ax *, uint32_t, uint32_t, uint32_t,

usr.sbin/snmpd/ax.h

255

uint32_t, uint16_t, uint16_t, struct ax_varbind *, size_t);

usr.sbin/snmpd/ax.h

261

const char *ax_oidrange2string(struct ax_oid *, uint8_t, uint32_t);

usr.sbin/snmpd/ax.h

265

int ax_oid_add(struct ax_oid *, uint32_t);

usr.sbin/snmpd/mib.h

39

(sizeof((uint32_t []) { MIB_##__VA_ARGS__ }) / sizeof(uint32_t))}, #__VA_ARGS__

usr.sbin/snmpd/mib.y

59

uint32_t number;

usr.sbin/snmpd/mib.y

70

uint32_t *bo_id;

usr.sbin/snmpd/parse.y

1811

uint32_t npen = htonl(PEN_OPENBSD);

usr.sbin/snmpd/parse.y

809

uint32_t npen = htonl(enginepen);

usr.sbin/snmpd/proc.c

682

imsg_compose_event(struct imsgev *iev, uint16_t type, uint32_t peerid,

usr.sbin/snmpd/proc.c

695

imsg_composev_event(struct imsgev *iev, uint16_t type, uint32_t peerid,

usr.sbin/snmpd/proc.c

722

uint16_t type, uint32_t peerid, int fd, void *data, uint16_t datalen)

usr.sbin/snmpd/proc.c

745

uint16_t type, uint32_t peerid, int fd, const struct iovec *iov, int iovcnt)

usr.sbin/snmpd/snmpd.h

176

(sizeof((uint32_t []) { __VA_ARGS__ }) / sizeof(uint32_t)) }

usr.sbin/snmpd/snmpd.h

213

uint32_t sm_transactionid;

usr.sbin/snmpd/snmpe.c

742

int32_t error, uint32_t index, struct ber_element *varbindlist)

usr.sbin/snmpd/snmpe.h

27

int32_t, uint32_t, struct ber_element *);

usr.sbin/tcpdump/in_cksum.c

109

in_cksum_fini(uint32_t sum)

usr.sbin/tcpdump/in_cksum.c

122

in_cksum(const void *addr, size_t len, uint32_t sum)

usr.sbin/tcpdump/in_cksum.c

90

uint32_t

usr.sbin/tcpdump/in_cksum.c

91

in_cksum_add(const void *buf, size_t len, uint32_t sum)

usr.sbin/tcpdump/interface.h

301

extern uint32_t in_cksum_add(const void *, size_t, uint32_t);

usr.sbin/tcpdump/interface.h

302

extern uint16_t in_cksum_fini(uint32_t);

usr.sbin/tcpdump/interface.h

303

extern uint16_t in_cksum(const void *, size_t, uint32_t);

usr.sbin/tcpdump/interface.h

306

extern uint32_t wg_match(const u_char *, u_int);

usr.sbin/tcpdump/ospf.h

227

uint32_t auth_seq;

usr.sbin/tcpdump/print-802_11.c

646

uint32_t vhtcaps;

usr.sbin/tcpdump/print-802_11.c

648

uint32_t rxstbc, num_sts, max_ampdu, link_adapt;

usr.sbin/tcpdump/print-dhcp6.c

127

uint32_t iaid, t1, t2;

usr.sbin/tcpdump/print-dhcp6.c

172

uint32_t time, en;

usr.sbin/tcpdump/print-dhcp6.c

254

uint32_t status;

usr.sbin/tcpdump/print-dhcp6.c

284

uint32_t pltime, vltime;

usr.sbin/tcpdump/print-dhcp6.c

524

uint32_t pltime, vltime;

usr.sbin/tcpdump/print-dhcp6.c

737

uint32_t hdr;

usr.sbin/tcpdump/print-ether.c

173

uint32_t itag;

usr.sbin/tcpdump/print-gre.c

171

uint32_t key, vsid;

usr.sbin/tcpdump/print-gre.c

517

uint32_t hdr, ver, vlan, cos, en, sid, index;

usr.sbin/tcpdump/print-gre.c

704

uint32_t vni;

usr.sbin/tcpdump/print-gre.c

740

uint32_t vni = (htonl(vh->vni) & VXLAN_VNI_MASK) >>

usr.sbin/tcpdump/print-gre.c

804

uint32_t vni;

usr.sbin/tcpdump/print-gre.c

843

uint32_t w;

usr.sbin/tcpdump/print-gre.c

867

uint32_t vni;

usr.sbin/tcpdump/print-lldp.c

200

uint32_t ifidx;

usr.sbin/tcpdump/print-mpls.c

132

uint32_t cw, frag, seq;

usr.sbin/tcpdump/print-nsh.c

105

uint32_t field, len, proto;

usr.sbin/tcpdump/print-nsh.c

48

uint32_t base;

usr.sbin/tcpdump/print-nsh.c

65

uint32_t sp;

usr.sbin/tcpdump/print-nsh.c

86

uint32_t ch[4];

usr.sbin/tcpdump/print-ofp.c

106

uint32_t bmp;

usr.sbin/tcpdump/print-ofp.c

146

bmp = ntohl(*(uint32_t *)bp);

usr.sbin/tcpdump/print-ofp.c

673

uint32_t *w;

usr.sbin/tcpdump/print-ofp.c

680

w = (uint32_t *)bp;

usr.sbin/tcpdump/print-udp.c

328

uint32_t cksum = 0;

usr.sbin/tcpdump/print-wg.c

34

uint32_t type;

usr.sbin/tcpdump/print-wg.c

35

uint32_t sender;

usr.sbin/tcpdump/print-wg.c

40

uint32_t type;

usr.sbin/tcpdump/print-wg.c

41

uint32_t sender;

usr.sbin/tcpdump/print-wg.c

42

uint32_t receiver;

usr.sbin/tcpdump/print-wg.c

47

uint32_t type;

usr.sbin/tcpdump/print-wg.c

48

uint32_t receiver;

usr.sbin/tcpdump/print-wg.c

53

uint32_t type;

usr.sbin/tcpdump/print-wg.c

54

uint32_t receiver;

usr.sbin/tcpdump/print-wg.c

63

uint32_t

usr.sbin/tcpdump/print-wg.c

66

uint32_t type;

usr.sbin/tcpdump/print-wg.c

99

uint32_t type;

usr.sbin/unbound/cachedb/cachedb.c

741

uint32_t store_flags = qstate->query_flags;

usr.sbin/unbound/cachedb/redis.c

602

key, (int)data_len, (unsigned)(uint32_t)ttl);

usr.sbin/unbound/cachedb/redis.c

605

(unsigned)(uint32_t)ttl);

usr.sbin/unbound/daemon/cachedump.c

734

(uint32_t)flags, *worker->env.now, 0);

usr.sbin/unbound/daemon/daemon.c

552

hash_set_raninit((uint32_t)ub_random(daemon->rand));

usr.sbin/unbound/daemon/remote.c

3387

uint32_t serial = 0;

usr.sbin/unbound/daemon/remote.c

4162

uint32_t len = 0;

usr.sbin/unbound/daemon/remote.c

4448

uint32_t cmd;

usr.sbin/unbound/daemon/remote.c

4510

uint32_t cmd;

usr.sbin/unbound/daemon/remote.c

5470

uint32_t old_serial = 0, new_serial = 0;

usr.sbin/unbound/daemon/remote.c

5824

#define COPY_VAR_uint32_t(var) oldcfg->var = cfg->var; atomic_store((_Atomic uint32_t*)&cfg->var, newcfg->var); newcfg->var = 0;

usr.sbin/unbound/daemon/remote.c

6449

uint32_t cmd;

usr.sbin/unbound/daemon/remote.c

7087

uint32_t cmd;

usr.sbin/unbound/daemon/remote.c

7239

uint32_t cmd;

usr.sbin/unbound/daemon/remote.h

228

uint32_t service_read_cmd;

usr.sbin/unbound/daemon/stats.c

382

uint32_t len = 0;

usr.sbin/unbound/daemon/stats.c

425

if(len != (uint32_t)sizeof(*s))

usr.sbin/unbound/daemon/worker.c

1158

uint32_t serial = 0;

usr.sbin/unbound/daemon/worker.c

237

uint32_t c = (uint32_t)htonl(cmd);

usr.sbin/unbound/daemon/worker.c

419

uint32_t len = 0, cmd;

usr.sbin/unbound/daemon/worker.c

426

if(len != sizeof(uint32_t)) {

usr.sbin/unbound/daemon/worker.c

465

if(len != sizeof(uint32_t)) {

usr.sbin/unbound/dns64/dns64.c

198

static uint32_t

usr.sbin/unbound/dns64/dns64.c

201

uint32_t ipv4 = 0;

usr.sbin/unbound/dns64/dns64.c

228

ipv4_to_ptr(uint32_t ipv4, char ptr[], size_t nm_len)

usr.sbin/unbound/dnscrypt/dnscrypt.c

111

uint32_t hash,

usr.sbin/unbound/dnscrypt/dnscrypt.c

145

uint32_t hash)

usr.sbin/unbound/dnscrypt/dnscrypt.c

158

static uint32_t

usr.sbin/unbound/dnscrypt/dnscrypt.c

163

uint32_t h = 0;

usr.sbin/unbound/dnscrypt/dnscrypt.c

183

uint32_t hash)

usr.sbin/unbound/dnscrypt/dnscrypt.c

219

uint32_t hash)

usr.sbin/unbound/dnscrypt/dnscrypt.c

257

uint32_t hash;

usr.sbin/unbound/dnscrypt/dnscrypt.c

259

uint32_t nonce_hash;

usr.sbin/unbound/dnscrypt/dnscrypt.c

397

uint32_t rnd;

usr.sbin/unbound/dnscrypt/dnscrypt.c

700

uint32_t serial;

usr.sbin/unbound/dnscrypt/dnscrypt.c

85

static uint32_t

usr.sbin/unbound/dnstap/dnstap.c

329

uint32_t *time_nsec, protobuf_c_boolean *has_time_nsec)

usr.sbin/unbound/dnstap/dnstap.c

355

uint32_t *qport, protobuf_c_boolean *has_qport,

usr.sbin/unbound/dnstap/dnstap.c

357

uint32_t *rport, protobuf_c_boolean *has_rport)

usr.sbin/unbound/dnstap/dnstap_fstrm.c

125

uint32_t* control;

usr.sbin/unbound/dnstap/dnstap_fstrm.c

153

uint32_t* control;

usr.sbin/unbound/dnstap/dnstap_fstrm.c

175

uint32_t frametype = 0;

usr.sbin/unbound/dnstap/dnstap_fstrm.c

206

uint32_t field_type = sldns_read_uint32(pos);

usr.sbin/unbound/dnstap/dnstap_fstrm.c

207

uint32_t field_len = sldns_read_uint32(pos+4);

usr.sbin/unbound/dnstap/dnstap_fstrm.c

51

uint32_t* control;

usr.sbin/unbound/dnstap/dnstap_fstrm.c

77

uint32_t* control;

usr.sbin/unbound/dnstap/dnstap_fstrm.c

97

uint32_t* control;

usr.sbin/unbound/dnstap/dtstream.c

1175

uint32_t type = sldns_read_uint32(dtio->read_frame.buf +

usr.sbin/unbound/dnstap/dtstream.c

1177

uint32_t len = sldns_read_uint32(dtio->read_frame.buf +

usr.sbin/unbound/dnstap/dtstream.c

843

uint32_t sendlen = htonl(dtio->cur_msg_len);

usr.sbin/unbound/dnstap/dtstream.c

890

uint32_t sendlen;

usr.sbin/unbound/dnstap/dtstream.h

109

uint32_t frame_len;

usr.sbin/unbound/dnstap/unbound-dnstap-socket.c

1059

uint32_t l = (uint32_t)data->len;

usr.sbin/unbound/dnstap/unbound-dnstap-socket.c

596

protobuf_c_boolean has_time_nsec, uint32_t time_nsec)

usr.sbin/unbound/edns-subnet/addrtree.c

123

size_t (*sizefunc)(void *), void *env, uint32_t max_node_count)

usr.sbin/unbound/edns-subnet/addrtree.h

144

size_t (*sizefunc)(void *), void *env, uint32_t max_node_count);

usr.sbin/unbound/edns-subnet/addrtree.h

69

uint32_t node_count;

usr.sbin/unbound/edns-subnet/addrtree.h

72

uint32_t max_node_count;

usr.sbin/unbound/iterator/iter_scrub.c

136

len = sldns_read_uint16(rr->ttl_data+sizeof(uint32_t));

usr.sbin/unbound/iterator/iter_scrub.c

139

*nm = rr->ttl_data+sizeof(uint32_t)+sizeof(uint16_t)+offset;

usr.sbin/unbound/iterator/iter_scrub.c

205

*sname = rrset->rr_first->ttl_data + sizeof(uint32_t)

usr.sbin/unbound/iterator/iter_scrub.c

283

sizeof(uint32_t)+sizeof(uint16_t)+aliaslen);

usr.sbin/unbound/iterator/iter_scrub.c

287

sizeof(uint32_t)); /* RFC6672: synth CNAME TTL == DNAME TTL */

usr.sbin/unbound/iterator/iter_scrub.c

303

*sname = cn->rr_first->ttl_data + sizeof(uint32_t)+sizeof(uint16_t);

usr.sbin/unbound/libunbound/context.c

240

context_serialize_new_query(struct ctx_query* q, uint32_t* len)

usr.sbin/unbound/libunbound/context.c

251

*len = sizeof(uint32_t)*4 + slen;

usr.sbin/unbound/libunbound/context.c

255

sldns_write_uint32(p+sizeof(uint32_t), (uint32_t)q->querynum);

usr.sbin/unbound/libunbound/context.c

256

sldns_write_uint32(p+2*sizeof(uint32_t), (uint32_t)q->res->qtype);

usr.sbin/unbound/libunbound/context.c

257

sldns_write_uint32(p+3*sizeof(uint32_t), (uint32_t)q->res->qclass);

usr.sbin/unbound/libunbound/context.c

258

memmove(p+4*sizeof(uint32_t), q->res->qname, slen);

usr.sbin/unbound/libunbound/context.c

263

context_deserialize_new_query(struct ub_ctx* ctx, uint8_t* p, uint32_t len)

usr.sbin/unbound/libunbound/context.c

267

if(len < 4*sizeof(uint32_t)+1) {

usr.sbin/unbound/libunbound/context.c

272

q->querynum = (int)sldns_read_uint32(p+sizeof(uint32_t));

usr.sbin/unbound/libunbound/context.c

280

q->res->qtype = (int)sldns_read_uint32(p+2*sizeof(uint32_t));

usr.sbin/unbound/libunbound/context.c

281

q->res->qclass = (int)sldns_read_uint32(p+3*sizeof(uint32_t));

usr.sbin/unbound/libunbound/context.c

282

q->res->qname = strdup((char*)(p+4*sizeof(uint32_t)));

usr.sbin/unbound/libunbound/context.c

296

context_lookup_new_query(struct ub_ctx* ctx, uint8_t* p, uint32_t len)

usr.sbin/unbound/libunbound/context.c

300

if(len < 4*sizeof(uint32_t)+1) {

usr.sbin/unbound/libunbound/context.c

304

querynum = (int)sldns_read_uint32(p+sizeof(uint32_t));

usr.sbin/unbound/libunbound/context.c

315

uint32_t* len)

usr.sbin/unbound/libunbound/context.c

328

size_t size_of_uint32s = 6 * sizeof(uint32_t);

usr.sbin/unbound/libunbound/context.c

336

sldns_write_uint32(p+sizeof(uint32_t), (uint32_t)q->querynum);

usr.sbin/unbound/libunbound/context.c

337

sldns_write_uint32(p+2*sizeof(uint32_t), (uint32_t)err);

usr.sbin/unbound/libunbound/context.c

338

sldns_write_uint32(p+3*sizeof(uint32_t), (uint32_t)q->msg_security);

usr.sbin/unbound/libunbound/context.c

339

sldns_write_uint32(p+4*sizeof(uint32_t), (uint32_t)q->res->was_ratelimited);

usr.sbin/unbound/libunbound/context.c

340

sldns_write_uint32(p+5*sizeof(uint32_t), (uint32_t)wlen);

usr.sbin/unbound/libunbound/context.c

351

uint8_t* p, uint32_t len, int* err)

usr.sbin/unbound/libunbound/context.c

353

size_t size_of_uint32s = 6 * sizeof(uint32_t);

usr.sbin/unbound/libunbound/context.c

359

id = (int)sldns_read_uint32(p+sizeof(uint32_t));

usr.sbin/unbound/libunbound/context.c

362

*err = (int)sldns_read_uint32(p+2*sizeof(uint32_t));

usr.sbin/unbound/libunbound/context.c

363

q->msg_security = sldns_read_uint32(p+3*sizeof(uint32_t));

usr.sbin/unbound/libunbound/context.c

364

q->res->was_ratelimited = (int)sldns_read_uint32(p+4*sizeof(uint32_t));

usr.sbin/unbound/libunbound/context.c

365

wlen = (size_t)sldns_read_uint32(p+5*sizeof(uint32_t));

usr.sbin/unbound/libunbound/context.c

393

context_serialize_cancel(struct ctx_query* q, uint32_t* len)

usr.sbin/unbound/libunbound/context.c

398

uint8_t* p = (uint8_t*)reallocarray(NULL, 2, sizeof(uint32_t));

usr.sbin/unbound/libunbound/context.c

400

*len = 2*sizeof(uint32_t);

usr.sbin/unbound/libunbound/context.c

402

sldns_write_uint32(p+sizeof(uint32_t), (uint32_t)q->querynum);

usr.sbin/unbound/libunbound/context.c

407

uint8_t* p, uint32_t len)

usr.sbin/unbound/libunbound/context.c

411

if(len != 2*sizeof(uint32_t)) return NULL;

usr.sbin/unbound/libunbound/context.c

413

id = (int)sldns_read_uint32(p+sizeof(uint32_t));

usr.sbin/unbound/libunbound/context.c

419

context_serialize_quit(uint32_t* len)

usr.sbin/unbound/libunbound/context.c

421

uint32_t* p = (uint32_t*)malloc(sizeof(uint32_t));

usr.sbin/unbound/libunbound/context.c

424

*len = sizeof(uint32_t);

usr.sbin/unbound/libunbound/context.c

429

enum ub_ctx_cmd context_serial_getcmd(uint8_t* p, uint32_t len)

usr.sbin/unbound/libunbound/context.c

431

uint32_t v;

usr.sbin/unbound/libunbound/context.h

260

uint8_t* context_serialize_new_query(struct ctx_query* q, uint32_t* len);

usr.sbin/unbound/libunbound/context.h

273

struct sldns_buffer* pkt, uint32_t* len);

usr.sbin/unbound/libunbound/context.h

282

uint8_t* context_serialize_cancel(struct ctx_query* q, uint32_t* len);

usr.sbin/unbound/libunbound/context.h

289

uint8_t* context_serialize_quit(uint32_t* len);

usr.sbin/unbound/libunbound/context.h

297

enum ub_ctx_cmd context_serial_getcmd(uint8_t* p, uint32_t len);

usr.sbin/unbound/libunbound/context.h

307

uint8_t* p, uint32_t len);

usr.sbin/unbound/libunbound/context.h

317

uint8_t* p, uint32_t len);

usr.sbin/unbound/libunbound/context.h

328

uint8_t* p, uint32_t len, int* err);

usr.sbin/unbound/libunbound/context.h

338

uint8_t* p, uint32_t len);

usr.sbin/unbound/libunbound/libunbound.c

269

uint32_t len;

usr.sbin/unbound/libunbound/libunbound.c

270

uint32_t cmd = UB_LIBCMD_QUIT;

usr.sbin/unbound/libunbound/libunbound.c

274

(uint32_t)sizeof(cmd), 0);

usr.sbin/unbound/libunbound/libunbound.c

586

process_answer_detail(struct ub_ctx* ctx, uint8_t* msg, uint32_t len,

usr.sbin/unbound/libunbound/libunbound.c

651

process_answer(struct ub_ctx* ctx, uint8_t* msg, uint32_t len)

usr.sbin/unbound/libunbound/libunbound.c

674

uint32_t len;

usr.sbin/unbound/libunbound/libunbound.c

702

uint32_t len;

usr.sbin/unbound/libunbound/libunbound.c

839

uint32_t len = 0;

usr.sbin/unbound/libunbound/libunbound.c

901

uint32_t len = 0;

usr.sbin/unbound/libunbound/libworker.c

199

hash_set_raninit((uint32_t)ub_random(w->env->rnd));

usr.sbin/unbound/libunbound/libworker.c

266

handle_cancel(struct libworker* w, uint8_t* buf, uint32_t len)

usr.sbin/unbound/libunbound/libworker.c

287

libworker_do_cmd(struct libworker* w, uint8_t* msg, uint32_t len)

usr.sbin/unbound/libunbound/libworker.c

331

uint32_t m;

usr.sbin/unbound/libunbound/libworker.c

367

(uint32_t)sizeof(m), 0);

usr.sbin/unbound/libunbound/libworker.c

740

uint32_t len = 0;

usr.sbin/unbound/libunbound/libworker.c

816

handle_newq(struct libworker* w, uint8_t* buf, uint32_t len)

usr.sbin/unbound/libunbound/libworker.c

88

static void handle_newq(struct libworker* w, uint8_t* buf, uint32_t len);

usr.sbin/unbound/services/authzone.c

1098

az_domain_add_rr(struct auth_data* node, uint16_t rr_type, uint32_t rr_ttl,

usr.sbin/unbound/services/authzone.c

1168

uint32_t rr_ttl = sldns_wirerr_get_ttl(rr, rr_len, dname_len);

usr.sbin/unbound/services/authzone.c

1320

uint32_t rr_ttl, uint8_t* rr_data, uint16_t rr_rdlen)

usr.sbin/unbound/services/authzone.c

1420

uint16_t rr_class, uint32_t rr_ttl, uint8_t* rr_data,

usr.sbin/unbound/services/authzone.c

1442

uint16_t rr_class, uint32_t rr_ttl, uint8_t* rr_data,

usr.sbin/unbound/services/authzone.c

1808

uint32_t* serial, int* scheme, int* hashalgo, uint8_t** hash,

usr.sbin/unbound/services/authzone.c

1843

uint32_t serial2 = 0;

usr.sbin/unbound/services/authzone.c

1885

uint32_t soa_serial = 0;

usr.sbin/unbound/services/authzone.c

1909

uint32_t serial = 0;

usr.sbin/unbound/services/authzone.c

1996

auth_zone_get_serial(struct auth_zone* z, uint32_t* serial)

usr.sbin/unbound/services/authzone.c

3655

auth_zone_parse_notify_serial(sldns_buffer* pkt, uint32_t *serial)

usr.sbin/unbound/services/authzone.c

3772

xfr_serial_means_update(struct auth_xfer* xfr, uint32_t serial)

usr.sbin/unbound/services/authzone.c

3787

xfr_note_notify_serial(struct auth_xfer* xfr, int has_serial, uint32_t serial)

usr.sbin/unbound/services/authzone.c

3812

int has_serial, uint32_t serial, struct auth_master* fromhost)

usr.sbin/unbound/services/authzone.c

3832

uint32_t serial, int* refused)

usr.sbin/unbound/services/authzone.c

4249

uint32_t serial;

usr.sbin/unbound/services/authzone.c

4301

uint32_t* serial)

usr.sbin/unbound/services/authzone.c

4755

uint16_t* rr_class, uint32_t* rr_ttl, uint16_t* rr_rdlen,

usr.sbin/unbound/services/authzone.c

4820

uint32_t rr_ttl, uint16_t rr_rdlen, uint8_t* rr_rdata,

usr.sbin/unbound/services/authzone.c

4821

size_t rr_nextpos, uint32_t transfer_serial, uint32_t xfr_serial)

usr.sbin/unbound/services/authzone.c

4823

uint32_t startserial;

usr.sbin/unbound/services/authzone.c

4875

uint32_t rr_ttl;

usr.sbin/unbound/services/authzone.c

4878

uint32_t transfer_serial = 0;

usr.sbin/unbound/services/authzone.c

4904

uint32_t serial;

usr.sbin/unbound/services/authzone.c

5012

uint32_t rr_ttl;

usr.sbin/unbound/services/authzone.c

5013

uint32_t serial = 0;

usr.sbin/unbound/services/authzone.c

5922

uint32_t serial;

usr.sbin/unbound/services/authzone.c

6098

uint32_t sr = xfr->notify_serial;

usr.sbin/unbound/services/authzone.c

6530

uint32_t serial = 0;

usr.sbin/unbound/services/authzone.c

7339

compare_serial(uint32_t a, uint32_t b)

usr.sbin/unbound/services/authzone.c

7341

const uint32_t cutoff = ((uint32_t) 1 << (SERIAL_BITS - 1));

usr.sbin/unbound/services/authzone.c

795

rrset_add_rr(struct auth_rrset* rrset, uint32_t rr_ttl, uint8_t* rdata,

usr.sbin/unbound/services/authzone.c

865

rrset_create(struct auth_data* node, uint16_t rr_type, uint32_t rr_ttl,

usr.sbin/unbound/services/authzone.h

253

uint32_t notify_serial;

usr.sbin/unbound/services/authzone.h

270

uint32_t serial;

usr.sbin/unbound/services/authzone.h

423

uint32_t incoming_xfr_serial;

usr.sbin/unbound/services/authzone.h

628

uint32_t serial, int* refused);

usr.sbin/unbound/services/authzone.h

632

int auth_zone_parse_notify_serial(struct sldns_buffer* pkt, uint32_t *serial);

usr.sbin/unbound/services/authzone.h

647

int auth_zone_get_serial(struct auth_zone* z, uint32_t* serial);

usr.sbin/unbound/services/authzone.h

710

int compare_serial(uint32_t a, uint32_t b);

usr.sbin/unbound/services/cache/dns.c

1060

struct regional* region, uint32_t flags, time_t qstarttime,

usr.sbin/unbound/services/cache/dns.c

157

struct reply_info* qrep, uint32_t flags, struct regional* region,

usr.sbin/unbound/services/cache/dns.c

369

struct regional* region, struct delegpt* dp, uint32_t flags)

usr.sbin/unbound/services/cache/dns.h

126

struct reply_info* qrep, uint32_t flags, struct regional* region,

usr.sbin/unbound/services/cache/dns.h

212

struct regional* region, struct delegpt* dp, uint32_t flags);

usr.sbin/unbound/services/cache/dns.h

99

struct regional* region, uint32_t flags, time_t qstarttime,

usr.sbin/unbound/services/cache/rrset.c

283

uint16_t qtype, uint16_t qclass, uint32_t flags, time_t timenow,

usr.sbin/unbound/services/cache/rrset.c

533

uint16_t type, uint16_t dclass, uint32_t flags)

usr.sbin/unbound/services/cache/rrset.h

170

uint32_t flags, time_t timenow, int wr);

usr.sbin/unbound/services/cache/rrset.h

275

uint16_t type, uint16_t dclass, uint32_t flags);

usr.sbin/unbound/services/listen_dnsport.c

1537

int harden_large_queries, uint32_t http_max_streams,

usr.sbin/unbound/services/listen_dnsport.c

2532

int32_t stream_id, uint8_t* buf, size_t length, uint32_t* data_flags,

usr.sbin/unbound/services/listen_dnsport.c

2714

int32_t stream_id, uint8_t* buf, size_t length, uint32_t* data_flags,

usr.sbin/unbound/services/listen_dnsport.c

3553

const uint8_t* dcid, size_t dcidlen, uint32_t version)

usr.sbin/unbound/services/listen_dnsport.c

4366

doq_recv_stream_data_cb(ngtcp2_conn* ATTR_UNUSED(conn), uint32_t flags,

usr.sbin/unbound/services/listen_dnsport.c

4413

doq_stream_close_cb(ngtcp2_conn* ATTR_UNUSED(conn), uint32_t flags,

usr.sbin/unbound/services/listen_dnsport.c

5356

uint32_t flags = 0;

usr.sbin/unbound/services/listen_dnsport.h

215

int harden_large_queries, uint32_t http_max_streams,

usr.sbin/unbound/services/listen_dnsport.h

594

uint32_t version;

usr.sbin/unbound/services/listen_dnsport.h

625

uint32_t close_ecn;

usr.sbin/unbound/services/listen_dnsport.h

711

uint32_t version);

usr.sbin/unbound/services/rpz.c

1002

enum rpz_action a, uint16_t rrtype, uint16_t rrclass, uint32_t ttl,

usr.sbin/unbound/services/rpz.c

1024

enum rpz_action a, uint16_t rrtype, uint16_t rrclass, uint32_t ttl,

usr.sbin/unbound/services/rpz.c

1047

enum rpz_action a, uint16_t rrtype, uint16_t rrclass, uint32_t ttl,

usr.sbin/unbound/services/rpz.c

1078

size_t dnamelen, uint16_t rr_type, uint16_t rr_class, uint32_t rr_ttl,

usr.sbin/unbound/services/rpz.c

661

uint32_t ttl, uint8_t* rdata, size_t rdata_len, uint8_t* rr, size_t rr_len)

usr.sbin/unbound/services/rpz.c

750

enum rpz_action a, uint16_t rrtype, uint16_t rrclass, uint32_t ttl,

usr.sbin/unbound/services/rpz.c

801

enum rpz_action a, uint16_t rrtype, uint16_t rrclass, uint32_t ttl,

usr.sbin/unbound/services/rpz.c

824

uint16_t rrclass, uint32_t ttl, uint8_t* rdata, size_t rdata_len,

usr.sbin/unbound/services/rpz.c

967

uint16_t rrclass, uint32_t ttl, uint8_t* rdata, size_t rdata_len,

usr.sbin/unbound/services/rpz.h

146

size_t dnamelen, uint16_t rr_type, uint16_t rr_class, uint32_t rr_ttl,

usr.sbin/unbound/sldns/keyraw.c

125

uint32_t ac32 = 0;

usr.sbin/unbound/sldns/parseutil.c

170

int32_t offset = (int32_t)((uint32_t) time - (uint32_t) now);

usr.sbin/unbound/sldns/parseutil.c

211

uint32_t

usr.sbin/unbound/sldns/parseutil.c

215

uint32_t i = 0;

usr.sbin/unbound/sldns/parseutil.c

216

uint32_t seconds = 0;

usr.sbin/unbound/sldns/parseutil.c

217

const uint32_t maxint = 0xffffffff;

usr.sbin/unbound/sldns/parseutil.h

81

uint32_t sldns_str2period(const char *nptr, const char **endptr, int* overflow);

usr.sbin/unbound/sldns/sbuffer.h

45

INLINE uint32_t

usr.sbin/unbound/sldns/sbuffer.h

49

return ntohl(*(const uint32_t *) src);

usr.sbin/unbound/sldns/sbuffer.h

52

return ( ((uint32_t) p[0] << 24)

usr.sbin/unbound/sldns/sbuffer.h

53

| ((uint32_t) p[1] << 16)

usr.sbin/unbound/sldns/sbuffer.h

54

| ((uint32_t) p[2] << 8)

usr.sbin/unbound/sldns/sbuffer.h

548

sldns_buffer_write_u32_at(sldns_buffer *buffer, size_t at, uint32_t data)

usr.sbin/unbound/sldns/sbuffer.h

55

| (uint32_t) p[3]);

usr.sbin/unbound/sldns/sbuffer.h

573

sldns_buffer_write_u32(sldns_buffer *buffer, uint32_t data)

usr.sbin/unbound/sldns/sbuffer.h

676

INLINE uint32_t

usr.sbin/unbound/sldns/sbuffer.h

679

assert(sldns_buffer_available_at(buffer, at, sizeof(uint32_t)));

usr.sbin/unbound/sldns/sbuffer.h

688

INLINE uint32_t

usr.sbin/unbound/sldns/sbuffer.h

691

uint32_t result = sldns_buffer_read_u32_at(buffer, buffer->_position);

usr.sbin/unbound/sldns/sbuffer.h

692

buffer->_position += sizeof(uint32_t);

usr.sbin/unbound/sldns/sbuffer.h

76

sldns_write_uint32(void *dst, uint32_t data)

usr.sbin/unbound/sldns/sbuffer.h

79

* (uint32_t *) dst = htonl(data);

usr.sbin/unbound/sldns/str2wire.c

1776

uint32_t r;

usr.sbin/unbound/sldns/str2wire.c

1780

r = (uint32_t)strtol((char*)str, &end, 10);

usr.sbin/unbound/sldns/str2wire.c

1781

else r = (uint32_t)strtoul((char*)str, &end, 10);

usr.sbin/unbound/sldns/str2wire.c

2172

sldns_write_uint32(rd, (uint32_t)sldns_mktime_from_utc(&tm));

usr.sbin/unbound/sldns/str2wire.c

2176

uint32_t l = (uint32_t)strtol((char*)str, &end, 10);

usr.sbin/unbound/sldns/str2wire.c

2191

uint32_t low;

usr.sbin/unbound/sldns/str2wire.c

2197

low = (uint32_t)(t);

usr.sbin/unbound/sldns/str2wire.c

2208

uint32_t p = sldns_str2period(str, &end, &overflow);

usr.sbin/unbound/sldns/str2wire.c

2225

uint32_t meters = 0, cm = 0, val;

usr.sbin/unbound/sldns/str2wire.c

2230

meters = (uint32_t)strtol(my_str, &my_str, 10);

usr.sbin/unbound/sldns/str2wire.c

2233

cm = (uint32_t)strtol(my_str, &cm_endstr, 10);

usr.sbin/unbound/sldns/str2wire.c

2262

uint32_t latitude = 0;

usr.sbin/unbound/sldns/str2wire.c

2263

uint32_t longitude = 0;

usr.sbin/unbound/sldns/str2wire.c

2264

uint32_t altitude = 0;

usr.sbin/unbound/sldns/str2wire.c

2266

uint32_t equator = (uint32_t)1<<31; /* 2**31 */

usr.sbin/unbound/sldns/str2wire.c

2269

uint32_t h = 0;

usr.sbin/unbound/sldns/str2wire.c

2270

uint32_t m = 0;

usr.sbin/unbound/sldns/str2wire.c

2282

h = (uint32_t) strtol(my_str, &my_str, 10);

usr.sbin/unbound/sldns/str2wire.c

2292

m = (uint32_t) strtol(my_str, &my_str, 10);

usr.sbin/unbound/sldns/str2wire.c

2327

latitude = (uint32_t) s;

usr.sbin/unbound/sldns/str2wire.c

2340

h = (uint32_t) strtol(my_str, &my_str, 10);

usr.sbin/unbound/sldns/str2wire.c

2350

m = (uint32_t) strtol(my_str, &my_str, 10);

usr.sbin/unbound/sldns/str2wire.c

2385

longitude = (uint32_t) s;

usr.sbin/unbound/sldns/str2wire.c

2395

altitude = (uint32_t)(strtod(my_str, &my_str)*100.0 +

usr.sbin/unbound/sldns/str2wire.c

249

int* not_there, uint32_t* ttl, uint32_t default_ttl)

usr.sbin/unbound/sldns/str2wire.c

257

*ttl = (uint32_t) sldns_str2period(token, &endptr, &overflow);

usr.sbin/unbound/sldns/str2wire.c

321

size_t dname_len, uint16_t tp, uint16_t cl, uint32_t ttl, int question)

usr.sbin/unbound/sldns/str2wire.c

899

size_t* dname_len, uint32_t default_ttl, uint8_t* origin,

usr.sbin/unbound/sldns/str2wire.c

905

uint32_t ttl = 0;

usr.sbin/unbound/sldns/str2wire.c

948

size_t* dname_len, uint32_t default_ttl, uint8_t* origin,

usr.sbin/unbound/sldns/str2wire.c

977

uint32_t sldns_wirerr_get_ttl(uint8_t* rr, size_t len, size_t dname_len)

usr.sbin/unbound/sldns/str2wire.h

105

size_t* dname_len, uint32_t default_ttl, uint8_t* origin,

usr.sbin/unbound/sldns/str2wire.h

153

uint32_t sldns_wirerr_get_ttl(uint8_t* rr, size_t len, size_t dname_len);

usr.sbin/unbound/sldns/str2wire.h

262

uint32_t default_ttl;

usr.sbin/unbound/sldns/wire2str.c

1014

uint32_t ttl;

usr.sbin/unbound/sldns/wire2str.c

1687

uint32_t t;

usr.sbin/unbound/sldns/wire2str.c

1726

uint32_t longitude;

usr.sbin/unbound/sldns/wire2str.c

1727

uint32_t latitude;

usr.sbin/unbound/sldns/wire2str.c

1728

uint32_t altitude;

usr.sbin/unbound/sldns/wire2str.c

1731

uint32_t h;

usr.sbin/unbound/sldns/wire2str.c

1732

uint32_t m;

usr.sbin/unbound/sldns/wire2str.c

1734

uint32_t equator = (uint32_t)1 << 31; /* 2**31 */

usr.sbin/unbound/sldns/wire2str.c

2130

uint32_t lease_life; /* Requested or granted life of LLQ, in seconds */

usr.sbin/unbound/sldns/wire2str.c

2166

uint32_t lease;

usr.sbin/unbound/sldns/wire2str.c

491

uint32_t ttl;

usr.sbin/unbound/smallapp/unbound-anchor.c

715

sel = (int)arc4random_uniform((uint32_t)num);

usr.sbin/unbound/testcode/dohclient.c

128

uint32_t* data_flags, nghttp2_data_source* source,

usr.sbin/unbound/testcode/doqclient.c

1077

uint32_t client_chosen_version = NGTCP2_PROTO_VER_V1;

usr.sbin/unbound/testcode/doqclient.c

122

uint32_t quic_version;

usr.sbin/unbound/testcode/doqclient.c

1425

static uint32_t

usr.sbin/unbound/testcode/doqclient.c

1457

set_ecn(int fd, int family, uint32_t ecn)

usr.sbin/unbound/testcode/doqclient.c

1477

doq_client_send_pkt(struct doq_client_data* data, uint32_t ecn, uint8_t* buf,

usr.sbin/unbound/testcode/doqclient.c

1791

uint32_t flags;

usr.sbin/unbound/testcode/doqclient.c

937

recv_stream_data(ngtcp2_conn* ATTR_UNUSED(conn), uint32_t flags,

usr.sbin/unbound/testcode/fake_event.c

953

uint32_t ATTR_UNUSED(http_max_streams),

usr.sbin/unbound/testcode/pktview.c

131

uint32_t ttl;

usr.sbin/unbound/testcode/signit.c

165

uint32_t my_ttl = 3600;

usr.sbin/unbound/testcode/signit.c

53

uint32_t incep;

usr.sbin/unbound/testcode/signit.c

55

uint32_t expi;

usr.sbin/unbound/testcode/streamtcp.c

123

uint32_t serial)

usr.sbin/unbound/testcode/streamtcp.c

152

uint32_t serial = 0;

usr.sbin/unbound/testcode/streamtcp.c

162

serial = (uint32_t)atoi(strtype+5);

usr.sbin/unbound/testcode/streamtcp.c

169

serial = (uint32_t)atoi(strtype+7);

usr.sbin/unbound/testcode/testpkts.c

155

e->ixfr_soa_serial = (uint32_t)strtol(parse, (char**)&parse, 10);

usr.sbin/unbound/testcode/testpkts.c

589

pstate->default_ttl = (uint32_t)atoi(parse);

usr.sbin/unbound/testcode/testpkts.c

791

static uint32_t get_serial(uint8_t* p, size_t plen)

usr.sbin/unbound/testcode/testpkts.h

230

uint32_t ixfr_soa_serial;

usr.sbin/unbound/testcode/unitecs.c

161

uint32_t count;

usr.sbin/unbound/testcode/unitmain.c

466

uint32_t timestamp = 1559734385;

usr.sbin/unbound/testcode/unitmain.c

496

uint32_t timestamp = 0;

usr.sbin/unbound/testcode/unitmain.c

529

uint32_t timestamp = 1800 + 1;

usr.sbin/unbound/testcode/unitmain.c

560

uint32_t timestamp = 1559734700;

usr.sbin/unbound/testcode/unitmain.c

591

uint32_t timestamp = 1559734385;

usr.sbin/unbound/testcode/unitmain.c

621

uint32_t timestamp = 1559731985;

usr.sbin/unbound/testcode/unitmsgparse.c

322

uint32_t timenow = 0;

usr.sbin/unbound/util/config_file.c

570

cfg->val_date_override = (uint32_t)atoi(val);

usr.sbin/unbound/util/config_file.h

157

uint32_t http_max_streams;

usr.sbin/unbound/util/config_file.h

282

uint32_t max_ecs_tree_size_ipv4;

usr.sbin/unbound/util/config_file.h

283

uint32_t max_ecs_tree_size_ipv6;

usr.sbin/unbound/util/configparser.y

780

else cfg_parser->cfg->max_ecs_tree_size_ipv4 = (uint32_t)atoi($2);

usr.sbin/unbound/util/configparser.y

795

else cfg_parser->cfg->max_ecs_tree_size_ipv6 = (uint32_t)atoi($2);

usr.sbin/unbound/util/data/msgparse.c

159

static uint32_t

usr.sbin/unbound/util/data/msgparse.c

162

uint32_t f = 0;

usr.sbin/unbound/util/data/msgparse.c

173

uint16_t dclass, uint32_t rrset_flags)

usr.sbin/unbound/util/data/msgparse.c

181

h = hashlittle(&rrset_flags, sizeof(uint32_t), h);

usr.sbin/unbound/util/data/msgparse.c

200

uint32_t rrset_flags)

usr.sbin/unbound/util/data/msgparse.c

207

h = hashlittle(&rrset_flags, sizeof(uint32_t), h);

usr.sbin/unbound/util/data/msgparse.c

214

uint32_t rrset_flags, uint8_t* dname, size_t dnamelen,

usr.sbin/unbound/util/data/msgparse.c

227

hashvalue_type h, uint32_t rrset_flags, uint8_t* dname,

usr.sbin/unbound/util/data/msgparse.c

396

sldns_buffer* pkt, uint16_t datatype, uint32_t rrset_flags,

usr.sbin/unbound/util/data/msgparse.c

468

uint32_t* rrset_flags,

usr.sbin/unbound/util/data/msgparse.c

835

uint32_t rrset_flags = 0;

usr.sbin/unbound/util/data/msgparse.c

84

uint32_t rrset_flags, sldns_pkt_section section,

usr.sbin/unbound/util/data/msgparse.c

950

struct comm_reply* repinfo, uint32_t now, struct regional* region,

usr.sbin/unbound/util/data/msgparse.h

171

uint32_t flags;

usr.sbin/unbound/util/data/msgparse.h

347

uint16_t type, uint16_t dclass, uint32_t rrset_flags);

usr.sbin/unbound/util/data/msgparse.h

362

struct sldns_buffer* pkt, hashvalue_type h, uint32_t rrset_flags,

usr.sbin/unbound/util/data/msgreply.c

284

memmove(to, rr->ttl_data+sizeof(uint32_t), rr->size);

usr.sbin/unbound/util/data/msgreply.c

289

(rr->ttl_data - sldns_buffer_begin(pkt) + sizeof(uint32_t)));

usr.sbin/unbound/util/data/msgreply.h

146

uint32_t padding;

usr.sbin/unbound/util/data/packed_rrset.c

173

h = hashlittle(&key->flags, sizeof(uint32_t), h);

usr.sbin/unbound/util/data/packed_rrset.c

294

(uint32_t)(d->rr_ttl[i]-adjust));

usr.sbin/unbound/util/data/packed_rrset.h

103

uint32_t flags;

usr.sbin/unbound/util/edns.c

167

uint32_t timestamp)

usr.sbin/unbound/util/edns.c

182

const uint8_t* hash_input, uint32_t now)

usr.sbin/unbound/util/edns.c

185

uint32_t timestamp;

usr.sbin/unbound/util/edns.c

186

uint32_t subt_1982 = 0; /* Initialize for the compiler; unused value */

usr.sbin/unbound/util/edns.c

301

const uint8_t* hash_input, uint32_t now)

usr.sbin/unbound/util/edns.h

191

uint32_t timestamp);

usr.sbin/unbound/util/edns.h

208

const uint8_t* hash_input, uint32_t now);

usr.sbin/unbound/util/edns.h

246

const uint8_t* hash_input, uint32_t now);

usr.sbin/unbound/util/net_help.c

285

sa->sin6_scope_id = (uint32_t)atoi(s+1);

usr.sbin/unbound/util/netevent.c

1213

doq_set_ecn(int fd, int family, uint32_t ecn)

usr.sbin/unbound/util/netevent.c

1329

uint32_t ecn)

usr.sbin/unbound/util/netevent.c

1350

doq_send_pkt(struct comm_point* c, struct doq_pkt_addr* paddr, uint32_t ecn)

usr.sbin/unbound/util/netevent.c

1531

static uint32_t

usr.sbin/unbound/util/netevent.c

1614

uint32_t versions[2];

usr.sbin/unbound/util/netevent.c

1742

uint32_t version;

usr.sbin/unbound/util/netevent.c

5143

int32_t stream_id, uint32_t ATTR_UNUSED(error_code), void* cb_arg)

usr.sbin/unbound/util/netevent.c

6066

uint32_t http_max_streams, char* http_endpoint,

usr.sbin/unbound/util/netevent.c

6188

uint32_t http_max_streams, char* http_endpoint,

usr.sbin/unbound/util/netevent.h

1010

uint32_t error_code, void* cb_arg);

usr.sbin/unbound/util/netevent.h

1125

uint32_t ecn);

usr.sbin/unbound/util/netevent.h

293

uint32_t http2_max_streams;

usr.sbin/unbound/util/netevent.h

648

uint32_t http_max_streams, char* http_endpoint,

usr.sbin/unbound/util/netevent.h

943

uint32_t reads_count;

usr.sbin/unbound/util/proxy_protocol.c

49

void (*write_uint32)(void* buf, uint32_t data);

usr.sbin/unbound/util/proxy_protocol.c

75

void (*write_uint32)(void* buf, uint32_t data)) {

usr.sbin/unbound/util/proxy_protocol.h

107

uint32_t src_addr;

usr.sbin/unbound/util/proxy_protocol.h

108

uint32_t dst_addr;

usr.sbin/unbound/util/proxy_protocol.h

142

void (*write_uint32)(void* buf, uint32_t data));

usr.sbin/unbound/util/random.c

136

return (long)arc4random_uniform((uint32_t)x);

usr.sbin/unbound/util/rfc_1982.c

45

compare_1982(uint32_t a, uint32_t b)

usr.sbin/unbound/util/rfc_1982.c

48

const uint32_t cutoff = ((uint32_t) 1 << (32 - 1));

usr.sbin/unbound/util/rfc_1982.c

59

uint32_t

usr.sbin/unbound/util/rfc_1982.c

60

subtract_1982(uint32_t a, uint32_t b)

usr.sbin/unbound/util/rfc_1982.c

63

const uint32_t cutoff = ((uint32_t) 1 << (32 - 1));

usr.sbin/unbound/util/rfc_1982.c

71

return ((uint32_t)0xffffffff) - (a-b-1);

usr.sbin/unbound/util/rfc_1982.h

51

int compare_1982(uint32_t a, uint32_t b);

usr.sbin/unbound/util/rfc_1982.h

61

uint32_t subtract_1982(uint32_t a, uint32_t b);

usr.sbin/unbound/util/siphash.c

47

U32TO8_LE((p), (uint32_t)((v))); \

usr.sbin/unbound/util/siphash.c

48

U32TO8_LE((p) + 4, (uint32_t)((v) >> 32));

usr.sbin/unbound/util/siphash.c

77

printf("(%3d) v0 %08x %08x\n", (int)inlen, (uint32_t)(v0 >> 32), \

usr.sbin/unbound/util/siphash.c

78

(uint32_t)v0); \

usr.sbin/unbound/util/siphash.c

79

printf("(%3d) v1 %08x %08x\n", (int)inlen, (uint32_t)(v1 >> 32), \

usr.sbin/unbound/util/siphash.c

80

(uint32_t)v1); \

usr.sbin/unbound/util/siphash.c

81

printf("(%3d) v2 %08x %08x\n", (int)inlen, (uint32_t)(v2 >> 32), \

usr.sbin/unbound/util/siphash.c

82

(uint32_t)v2); \

usr.sbin/unbound/util/siphash.c

83

printf("(%3d) v3 %08x %08x\n", (int)inlen, (uint32_t)(v3 >> 32), \

usr.sbin/unbound/util/siphash.c

84

(uint32_t)v3); \

usr.sbin/unbound/util/storage/lookup3.c

1013

uint32_t c[HASHSTATE], d[HASHSTATE], i=0, j=0, k, l, m=0, z;

usr.sbin/unbound/util/storage/lookup3.c

1014

uint32_t e[HASHSTATE],f[HASHSTATE],g[HASHSTATE],h[HASHSTATE];

usr.sbin/unbound/util/storage/lookup3.c

1015

uint32_t x[HASHSTATE],y[HASHSTATE];

usr.sbin/unbound/util/storage/lookup3.c

1016

uint32_t hlen;

usr.sbin/unbound/util/storage/lookup3.c

1029

e[l]=f[l]=g[l]=h[l]=x[l]=y[l]=~((uint32_t)0);

usr.sbin/unbound/util/storage/lookup3.c

1034

uint32_t finished=1;

usr.sbin/unbound/util/storage/lookup3.c

1083

uint32_t len;

usr.sbin/unbound/util/storage/lookup3.c

1085

uint32_t h;

usr.sbin/unbound/util/storage/lookup3.c

1087

uint32_t i;

usr.sbin/unbound/util/storage/lookup3.c

1089

uint32_t j;

usr.sbin/unbound/util/storage/lookup3.c

1091

uint32_t ref,x,y;

usr.sbin/unbound/util/storage/lookup3.c

1096

hashword((const uint32_t *)q, (sizeof(q)-1)/4, 13),

usr.sbin/unbound/util/storage/lookup3.c

1097

hashword((const uint32_t *)q, (sizeof(q)-5)/4, 13),

usr.sbin/unbound/util/storage/lookup3.c

1098

hashword((const uint32_t *)q, (sizeof(q)-9)/4, 13));

usr.sbin/unbound/util/storage/lookup3.c

1156

ref = hashlittle(b, len, (uint32_t)1);

usr.sbin/unbound/util/storage/lookup3.c

1159

x = hashlittle(b, len, (uint32_t)1);

usr.sbin/unbound/util/storage/lookup3.c

116

#define hashsize(n) ((uint32_t)1<<(n))

usr.sbin/unbound/util/storage/lookup3.c

1160

y = hashlittle(b, len, (uint32_t)1);

usr.sbin/unbound/util/storage/lookup3.c

1174

uint32_t h,i,state[HASHSTATE];

usr.sbin/unbound/util/storage/lookup3.c

121

static uint32_t raninit = (uint32_t)0xdeadbeef;

usr.sbin/unbound/util/storage/lookup3.c

124

hash_set_raninit(uint32_t v)

usr.sbin/unbound/util/storage/lookup3.c

232

uint32_t hashword(

usr.sbin/unbound/util/storage/lookup3.c

233

const uint32_t *k, /* the key, an array of uint32_t values */

usr.sbin/unbound/util/storage/lookup3.c

235

uint32_t initval) /* the previous hash, or an arbitrary value */

usr.sbin/unbound/util/storage/lookup3.c

237

uint32_t a,b,c;

usr.sbin/unbound/util/storage/lookup3.c

240

a = b = c = raninit + (((uint32_t)length)<<2) + initval;

usr.sbin/unbound/util/storage/lookup3.c

285

const uint32_t *k, /* the key, an array of uint32_t values */

usr.sbin/unbound/util/storage/lookup3.c

287

uint32_t *pc, /* IN: seed OUT: primary hash value */

usr.sbin/unbound/util/storage/lookup3.c

288

uint32_t *pb) /* IN: more seed OUT: secondary hash value */

usr.sbin/unbound/util/storage/lookup3.c

290

uint32_t a,b,c;

usr.sbin/unbound/util/storage/lookup3.c

293

a = b = c = raninit + ((uint32_t)(length<<2)) + *pc;

usr.sbin/unbound/util/storage/lookup3.c

356

uint32_t hashlittle( const void *key, size_t length, uint32_t initval)

usr.sbin/unbound/util/storage/lookup3.c

358

uint32_t a,b,c; /* internal state */

usr.sbin/unbound/util/storage/lookup3.c

362

a = b = c = raninit + ((uint32_t)length) + initval;

usr.sbin/unbound/util/storage/lookup3.c

366

const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */

usr.sbin/unbound/util/storage/lookup3.c

417

case 11: c+=((uint32_t)k8[10])<<16;

usr.sbin/unbound/util/storage/lookup3.c

420

case 10: c+=((uint32_t)k8[9])<<8;

usr.sbin/unbound/util/storage/lookup3.c

427

case 7 : b+=((uint32_t)k8[6])<<16;

usr.sbin/unbound/util/storage/lookup3.c

430

case 6 : b+=((uint32_t)k8[5])<<8;

usr.sbin/unbound/util/storage/lookup3.c

437

case 3 : a+=((uint32_t)k8[2])<<16;

usr.sbin/unbound/util/storage/lookup3.c

440

case 2 : a+=((uint32_t)k8[1])<<8;

usr.sbin/unbound/util/storage/lookup3.c

456

a += k[0] + (((uint32_t)k[1])<<16);

usr.sbin/unbound/util/storage/lookup3.c

457

b += k[2] + (((uint32_t)k[3])<<16);

usr.sbin/unbound/util/storage/lookup3.c

458

c += k[4] + (((uint32_t)k[5])<<16);

usr.sbin/unbound/util/storage/lookup3.c

468

case 12: c+=k[4]+(((uint32_t)k[5])<<16);

usr.sbin/unbound/util/storage/lookup3.c

469

b+=k[2]+(((uint32_t)k[3])<<16);

usr.sbin/unbound/util/storage/lookup3.c

470

a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/unbound/util/storage/lookup3.c

472

case 11: c+=((uint32_t)k8[10])<<16;

usr.sbin/unbound/util/storage/lookup3.c

476

b+=k[2]+(((uint32_t)k[3])<<16);

usr.sbin/unbound/util/storage/lookup3.c

477

a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/unbound/util/storage/lookup3.c

482

case 8 : b+=k[2]+(((uint32_t)k[3])<<16);

usr.sbin/unbound/util/storage/lookup3.c

483

a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/unbound/util/storage/lookup3.c

485

case 7 : b+=((uint32_t)k8[6])<<16;

usr.sbin/unbound/util/storage/lookup3.c

489

a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/unbound/util/storage/lookup3.c

494

case 4 : a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/unbound/util/storage/lookup3.c

496

case 3 : a+=((uint32_t)k8[2])<<16;

usr.sbin/unbound/util/storage/lookup3.c

513

a += ((uint32_t)k[1])<<8;

usr.sbin/unbound/util/storage/lookup3.c

514

a += ((uint32_t)k[2])<<16;

usr.sbin/unbound/util/storage/lookup3.c

515

a += ((uint32_t)k[3])<<24;

usr.sbin/unbound/util/storage/lookup3.c

517

b += ((uint32_t)k[5])<<8;

usr.sbin/unbound/util/storage/lookup3.c

518

b += ((uint32_t)k[6])<<16;

usr.sbin/unbound/util/storage/lookup3.c

519

b += ((uint32_t)k[7])<<24;

usr.sbin/unbound/util/storage/lookup3.c

521

c += ((uint32_t)k[9])<<8;

usr.sbin/unbound/util/storage/lookup3.c

522

c += ((uint32_t)k[10])<<16;

usr.sbin/unbound/util/storage/lookup3.c

523

c += ((uint32_t)k[11])<<24;

usr.sbin/unbound/util/storage/lookup3.c

532

case 12: c+=((uint32_t)k[11])<<24;

usr.sbin/unbound/util/storage/lookup3.c

535

case 11: c+=((uint32_t)k[10])<<16;

usr.sbin/unbound/util/storage/lookup3.c

538

case 10: c+=((uint32_t)k[9])<<8;

usr.sbin/unbound/util/storage/lookup3.c

544

case 8 : b+=((uint32_t)k[7])<<24;

usr.sbin/unbound/util/storage/lookup3.c

547

case 7 : b+=((uint32_t)k[6])<<16;

usr.sbin/unbound/util/storage/lookup3.c

550

case 6 : b+=((uint32_t)k[5])<<8;

usr.sbin/unbound/util/storage/lookup3.c

556

case 4 : a+=((uint32_t)k[3])<<24;

usr.sbin/unbound/util/storage/lookup3.c

559

case 3 : a+=((uint32_t)k[2])<<16;

usr.sbin/unbound/util/storage/lookup3.c

562

case 2 : a+=((uint32_t)k[1])<<8;

usr.sbin/unbound/util/storage/lookup3.c

590

uint32_t *pc, /* IN: primary initval, OUT: primary hash */

usr.sbin/unbound/util/storage/lookup3.c

591

uint32_t *pb) /* IN: secondary initval, OUT: secondary hash */

usr.sbin/unbound/util/storage/lookup3.c

593

uint32_t a,b,c; /* internal state */

usr.sbin/unbound/util/storage/lookup3.c

597

a = b = c = raninit + ((uint32_t)length) + *pc;

usr.sbin/unbound/util/storage/lookup3.c

602

const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */

usr.sbin/unbound/util/storage/lookup3.c

653

case 11: c+=((uint32_t)k8[10])<<16;

usr.sbin/unbound/util/storage/lookup3.c

656

case 10: c+=((uint32_t)k8[9])<<8;

usr.sbin/unbound/util/storage/lookup3.c

663

case 7 : b+=((uint32_t)k8[6])<<16;

usr.sbin/unbound/util/storage/lookup3.c

666

case 6 : b+=((uint32_t)k8[5])<<8;

usr.sbin/unbound/util/storage/lookup3.c

673

case 3 : a+=((uint32_t)k8[2])<<16;

usr.sbin/unbound/util/storage/lookup3.c

676

case 2 : a+=((uint32_t)k8[1])<<8;

usr.sbin/unbound/util/storage/lookup3.c

692

a += k[0] + (((uint32_t)k[1])<<16);

usr.sbin/unbound/util/storage/lookup3.c

693

b += k[2] + (((uint32_t)k[3])<<16);

usr.sbin/unbound/util/storage/lookup3.c

694

c += k[4] + (((uint32_t)k[5])<<16);

usr.sbin/unbound/util/storage/lookup3.c

704

case 12: c+=k[4]+(((uint32_t)k[5])<<16);

usr.sbin/unbound/util/storage/lookup3.c

705

b+=k[2]+(((uint32_t)k[3])<<16);

usr.sbin/unbound/util/storage/lookup3.c

706

a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/unbound/util/storage/lookup3.c

708

case 11: c+=((uint32_t)k8[10])<<16;

usr.sbin/unbound/util/storage/lookup3.c

712

b+=k[2]+(((uint32_t)k[3])<<16);

usr.sbin/unbound/util/storage/lookup3.c

713

a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/unbound/util/storage/lookup3.c

718

case 8 : b+=k[2]+(((uint32_t)k[3])<<16);

usr.sbin/unbound/util/storage/lookup3.c

719

a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/unbound/util/storage/lookup3.c

721

case 7 : b+=((uint32_t)k8[6])<<16;

usr.sbin/unbound/util/storage/lookup3.c

725

a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/unbound/util/storage/lookup3.c

730

case 4 : a+=k[0]+(((uint32_t)k[1])<<16);

usr.sbin/unbound/util/storage/lookup3.c

732

case 3 : a+=((uint32_t)k8[2])<<16;

usr.sbin/unbound/util/storage/lookup3.c

749

a += ((uint32_t)k[1])<<8;

usr.sbin/unbound/util/storage/lookup3.c

750

a += ((uint32_t)k[2])<<16;

usr.sbin/unbound/util/storage/lookup3.c

751

a += ((uint32_t)k[3])<<24;

usr.sbin/unbound/util/storage/lookup3.c

753

b += ((uint32_t)k[5])<<8;

usr.sbin/unbound/util/storage/lookup3.c

754

b += ((uint32_t)k[6])<<16;

usr.sbin/unbound/util/storage/lookup3.c

755

b += ((uint32_t)k[7])<<24;

usr.sbin/unbound/util/storage/lookup3.c

757

c += ((uint32_t)k[9])<<8;

usr.sbin/unbound/util/storage/lookup3.c

758

c += ((uint32_t)k[10])<<16;

usr.sbin/unbound/util/storage/lookup3.c

759

c += ((uint32_t)k[11])<<24;

usr.sbin/unbound/util/storage/lookup3.c

768

case 12: c+=((uint32_t)k[11])<<24;

usr.sbin/unbound/util/storage/lookup3.c

771

case 11: c+=((uint32_t)k[10])<<16;

usr.sbin/unbound/util/storage/lookup3.c

774

case 10: c+=((uint32_t)k[9])<<8;

usr.sbin/unbound/util/storage/lookup3.c

780

case 8 : b+=((uint32_t)k[7])<<24;

usr.sbin/unbound/util/storage/lookup3.c

783

case 7 : b+=((uint32_t)k[6])<<16;

usr.sbin/unbound/util/storage/lookup3.c

786

case 6 : b+=((uint32_t)k[5])<<8;

usr.sbin/unbound/util/storage/lookup3.c

792

case 4 : a+=((uint32_t)k[3])<<24;

usr.sbin/unbound/util/storage/lookup3.c

795

case 3 : a+=((uint32_t)k[2])<<16;

usr.sbin/unbound/util/storage/lookup3.c

798

case 2 : a+=((uint32_t)k[1])<<8;

usr.sbin/unbound/util/storage/lookup3.c

821

uint32_t hashbig( const void *key, size_t length, uint32_t initval)

usr.sbin/unbound/util/storage/lookup3.c

823

uint32_t a,b,c;

usr.sbin/unbound/util/storage/lookup3.c

827

a = b = c = raninit + ((uint32_t)length) + initval;

usr.sbin/unbound/util/storage/lookup3.c

831

const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */

usr.sbin/unbound/util/storage/lookup3.c

882

case 11: c+=((uint32_t)k8[10])<<8;

usr.sbin/unbound/util/storage/lookup3.c

885

case 10: c+=((uint32_t)k8[9])<<16;

usr.sbin/unbound/util/storage/lookup3.c

888

case 9 : c+=((uint32_t)k8[8])<<24;

usr.sbin/unbound/util/storage/lookup3.c

892

case 7 : b+=((uint32_t)k8[6])<<8;

usr.sbin/unbound/util/storage/lookup3.c

895

case 6 : b+=((uint32_t)k8[5])<<16;

usr.sbin/unbound/util/storage/lookup3.c

898

case 5 : b+=((uint32_t)k8[4])<<24;

usr.sbin/unbound/util/storage/lookup3.c

902

case 3 : a+=((uint32_t)k8[2])<<8;

usr.sbin/unbound/util/storage/lookup3.c

905

case 2 : a+=((uint32_t)k8[1])<<16;

usr.sbin/unbound/util/storage/lookup3.c

908

case 1 : a+=((uint32_t)k8[0])<<24; break;

usr.sbin/unbound/util/storage/lookup3.c

920

a += ((uint32_t)k[0])<<24;

usr.sbin/unbound/util/storage/lookup3.c

921

a += ((uint32_t)k[1])<<16;

usr.sbin/unbound/util/storage/lookup3.c

922

a += ((uint32_t)k[2])<<8;

usr.sbin/unbound/util/storage/lookup3.c

923

a += ((uint32_t)k[3]);

usr.sbin/unbound/util/storage/lookup3.c

924

b += ((uint32_t)k[4])<<24;

usr.sbin/unbound/util/storage/lookup3.c

925

b += ((uint32_t)k[5])<<16;

usr.sbin/unbound/util/storage/lookup3.c

926

b += ((uint32_t)k[6])<<8;

usr.sbin/unbound/util/storage/lookup3.c

927

b += ((uint32_t)k[7]);

usr.sbin/unbound/util/storage/lookup3.c

928

c += ((uint32_t)k[8])<<24;

usr.sbin/unbound/util/storage/lookup3.c

929

c += ((uint32_t)k[9])<<16;

usr.sbin/unbound/util/storage/lookup3.c

930

c += ((uint32_t)k[10])<<8;

usr.sbin/unbound/util/storage/lookup3.c

931

c += ((uint32_t)k[11]);

usr.sbin/unbound/util/storage/lookup3.c

943

case 11: c+=((uint32_t)k[10])<<8;

usr.sbin/unbound/util/storage/lookup3.c

946

case 10: c+=((uint32_t)k[9])<<16;

usr.sbin/unbound/util/storage/lookup3.c

949

case 9 : c+=((uint32_t)k[8])<<24;

usr.sbin/unbound/util/storage/lookup3.c

955

case 7 : b+=((uint32_t)k[6])<<8;

usr.sbin/unbound/util/storage/lookup3.c

958

case 6 : b+=((uint32_t)k[5])<<16;

usr.sbin/unbound/util/storage/lookup3.c

961

case 5 : b+=((uint32_t)k[4])<<24;

usr.sbin/unbound/util/storage/lookup3.c

967

case 3 : a+=((uint32_t)k[2])<<8;

usr.sbin/unbound/util/storage/lookup3.c

970

case 2 : a+=((uint32_t)k[1])<<16;

usr.sbin/unbound/util/storage/lookup3.c

973

case 1 : a+=((uint32_t)k[0])<<24;

usr.sbin/unbound/util/storage/lookup3.c

991

uint32_t i;

usr.sbin/unbound/util/storage/lookup3.c

992

uint32_t h=0;

usr.sbin/unbound/util/storage/lookup3.h

53

uint32_t hashword(const uint32_t *k, size_t length, uint32_t initval);

usr.sbin/unbound/util/storage/lookup3.h

62

uint32_t hashlittle(const void *k, size_t length, uint32_t initval);

usr.sbin/unbound/util/storage/lookup3.h

69

void hash_set_raninit(uint32_t v);

usr.sbin/unbound/util/storage/lruhash.h

119

typedef uint32_t hashvalue_type;

usr.sbin/unbound/util/storage/slabhash.c

64

sl->mask = (uint32_t)(sl->size - 1);

usr.sbin/unbound/util/storage/slabhash.h

61

uint32_t mask;

usr.sbin/unbound/util/tcp_conn_limit.c

112

uint32_t limit;

usr.sbin/unbound/util/tcp_conn_limit.c

117

limit = (uint32_t)atoi(s2);

usr.sbin/unbound/util/tcp_conn_limit.c

88

socklen_t addrlen, int net, uint32_t limit,

usr.sbin/unbound/util/tcp_conn_limit.h

73

uint32_t limit;

usr.sbin/unbound/util/tcp_conn_limit.h

75

uint32_t count;

usr.sbin/unbound/util/tube.c

288

int tube_write_msg(struct tube* tube, uint8_t* buf, uint32_t len,

usr.sbin/unbound/util/tube.c

334

int tube_read_msg(struct tube* tube, uint8_t** buf, uint32_t* len,

usr.sbin/unbound/util/tube.c

609

int tube_write_msg(struct tube* tube, uint8_t* buf, uint32_t len,

usr.sbin/unbound/util/tube.c

623

int tube_read_msg(struct tube* tube, uint8_t** buf, uint32_t* len,

usr.sbin/unbound/util/tube.c

786

uint32_t len = 0;

usr.sbin/unbound/util/tube.h

121

uint32_t len;

usr.sbin/unbound/util/tube.h

153

int tube_write_msg(struct tube* tube, uint8_t* buf, uint32_t len,

usr.sbin/unbound/util/tube.h

173

int tube_read_msg(struct tube* tube, uint8_t** buf, uint32_t* len,

usr.sbin/unbound/util/tube.h

79

uint32_t cmd_len;

usr.sbin/unbound/validator/autotrust.c

1440

add_key(struct trust_anchor* tp, uint32_t ttl, uint8_t* rdata, size_t rdata_len)

usr.sbin/unbound/validator/autotrust.c

1663

ta = add_key(tp, (uint32_t)dd->rr_ttl[i],

usr.sbin/unbound/validator/val_neg.c

1061

uint16_t qtype, uint16_t qclass, uint32_t flags,

usr.sbin/unbound/validator/val_neg.c

1114

uint32_t flags;

usr.sbin/unbound/validator/val_nsec.c

53

static uint32_t

usr.sbin/unbound/validator/val_sigcrypt.c

1417

check_dates(struct val_env* ve, uint32_t unow, uint8_t* expi_p,

usr.sbin/unbound/validator/val_sigcrypt.c

1421

uint32_t expi, incep, now;

usr.sbin/unbound/validator/val_sigcrypt.c

1454

uint32_t skew = subtract_1982(incep, expi)/10;

usr.sbin/unbound/validator/val_sigcrypt.c

1455

if(skew < (uint32_t)ve->skew_min) skew = ve->skew_min;

usr.sbin/unbound/validator/val_sigcrypt.c

1456

if(skew > (uint32_t)ve->skew_max) skew = ve->skew_max;

usr.sbin/unbound/validator/val_sigcrypt.c

1469

uint32_t skew = subtract_1982(incep, expi)/10;

usr.sbin/unbound/validator/val_sigcrypt.c

1470

if(skew < (uint32_t)ve->skew_min) skew = ve->skew_min;

usr.sbin/unbound/validator/val_sigcrypt.c

1471

if(skew > (uint32_t)ve->skew_max) skew = ve->skew_max;

usr.sbin/unbound/validator/val_sigcrypt.c

1488

adjust_ttl(struct val_env* ve, uint32_t unow,

usr.sbin/unbound/validator/val_sigcrypt.c

1507

expittl = (int32_t)((uint32_t)expi - (uint32_t)now);

usr.sbin/unbound/validator/val_utils.c

395

static uint32_t

usr.sbin/unbound/validator/validator.c

172

val_env->bogus_ttl = (uint32_t)cfg->bogus_ttl;

usr.sbin/unbound/validator/validator.h

104

uint32_t bogus_ttl;

usr.sbin/unwindctl/unwindctl.c

278

static uint32_t last_if_index;

usr.sbin/vmctl/main.c

190

uint32_t type;

usr.sbin/vmctl/main.c

504

uint32_t id;

usr.sbin/vmctl/vmctl.c

232

uint32_t type;

usr.sbin/vmctl/vmctl.c

284

pause_vm(uint32_t pause_id, const char *name)

usr.sbin/vmctl/vmctl.c

301

uint32_t type;

usr.sbin/vmctl/vmctl.c

325

unpause_vm(uint32_t pause_id, const char *name)

usr.sbin/vmctl/vmctl.c

342

uint32_t type;

usr.sbin/vmctl/vmctl.c

376

terminate_vm(uint32_t terminate_id, const char *name, unsigned int flags)

usr.sbin/vmctl/vmctl.c

421

uint32_t type;

usr.sbin/vmctl/vmctl.c

45

uint32_t info_id;

usr.sbin/vmctl/vmctl.c

521

waitfor_vm(uint32_t terminate_id, const char *name)

usr.sbin/vmctl/vmctl.c

552

get_info_vm(uint32_t id, const char *name, enum actions action,

usr.sbin/vmctl/vmctl.c

573

check_info_id(const char *name, uint32_t id)

usr.sbin/vmctl/vmctl.c

617

uint32_t type;

usr.sbin/vmctl/vmctl.c

74

vm_start(uint32_t start_id, const char *name, size_t memsize, int nnics,

usr.sbin/vmctl/vmctl.h

102

void terminate_vm(uint32_t, const char *, unsigned int);

usr.sbin/vmctl/vmctl.h

104

void waitfor_vm(uint32_t, const char *);

usr.sbin/vmctl/vmctl.h

105

void pause_vm(uint32_t, const char *);

usr.sbin/vmctl/vmctl.h

107

void unpause_vm(uint32_t, const char *);

usr.sbin/vmctl/vmctl.h

109

int check_info_id(const char *, uint32_t);

usr.sbin/vmctl/vmctl.h

110

void get_info_vm(uint32_t, const char *, enum actions, unsigned int);

usr.sbin/vmctl/vmctl.h

45

uint32_t id;

usr.sbin/vmctl/vmctl.h

99

int vm_start(uint32_t, const char *, size_t, int, char **, int,

usr.sbin/vmd/arm64_vm.c

107

vcpu_assert_irq(uint32_t vm_id, uint32_t vcpu_id, int irq)

usr.sbin/vmd/arm64_vm.c

113

vcpu_deassert_irq(uint32_t vm_id, uint32_t vcpu_id, int irq)

usr.sbin/vmd/arm64_vm.c

135

set_return_data(struct vm_exit *vei, uint32_t data)

usr.sbin/vmd/arm64_vm.c

143

get_input_data(struct vm_exit *vei, uint32_t *data)

usr.sbin/vmd/config.c

188

config_setvm(struct privsep *ps, struct vmd_vm *vm, uint32_t peerid, uid_t uid)

usr.sbin/vmd/config.c

531

uint32_t peer_id;

usr.sbin/vmd/config.c

546

vm->vm_peerid = (uint32_t)-1;

usr.sbin/vmd/config.c

567

uint32_t peer_id;

usr.sbin/vmd/config.c

600

uint32_t peer_id;

usr.sbin/vmd/config.c

631

uint32_t peer_id;

usr.sbin/vmd/control.c

384

uint32_t peer_id = fd, type;

usr.sbin/vmd/control.c

41

uint32_t ctl_vmid;

usr.sbin/vmd/control.c

89

uint32_t peer_id, type;

usr.sbin/vmd/dhcp.c

54

uint32_t ltime;

usr.sbin/vmd/fw_cfg.c

149

uint32_t id = htole32(0x3);

usr.sbin/vmd/fw_cfg.c

176

uint32_t len = 0, control = fw->control;

usr.sbin/vmd/fw_cfg.c

216

uint32_t data = 0;

usr.sbin/vmd/fw_cfg.c

256

uint32_t data = 0;

usr.sbin/vmd/fw_cfg.c

379

uint32_t count = 0;

usr.sbin/vmd/fw_cfg.c

380

uint32_t *data;

usr.sbin/vmd/fw_cfg.c

41

uint32_t control;

usr.sbin/vmd/fw_cfg.c

47

uint32_t length;

usr.sbin/vmd/fw_cfg.c

52

uint32_t size;

usr.sbin/vmd/i8253.c

119

i8253_do_readback(uint32_t data)

usr.sbin/vmd/i8253.c

223

uint32_t out_data = 0;

usr.sbin/vmd/i8253.c

79

i8253_init(uint32_t vm_id)

usr.sbin/vmd/i8253.h

42

uint32_t vm_id; /* owning VM id */

usr.sbin/vmd/i8253.h

47

void i8253_init(uint32_t);

usr.sbin/vmd/i8253.h

52

void i8253_do_readback(uint32_t);

usr.sbin/vmd/i8259.c

587

uint32_t data = 0;

usr.sbin/vmd/loadfile_elf.c

112

static void setsegment(struct mem_segment_descriptor *, uint32_t,

usr.sbin/vmd/loadfile_elf.c

117

static uint32_t push_bootargs(bios_memmap_t *, size_t, bios_bootmac_t *);

usr.sbin/vmd/loadfile_elf.c

118

static size_t push_stack(uint32_t, uint32_t);

usr.sbin/vmd/loadfile_elf.c

145

setsegment(struct mem_segment_descriptor *sd, uint32_t base, size_t limit,

usr.sbin/vmd/loadfile_elf.c

215

uint32_t bootargsz;

usr.sbin/vmd/loadfile_elf.c

319

static uint32_t

usr.sbin/vmd/loadfile_elf.c

322

uint32_t memmap_sz, consdev_sz, bootmac_sz, i;

usr.sbin/vmd/loadfile_elf.c

324

uint32_t ba[1024];

usr.sbin/vmd/loadfile_elf.c

326

memmap_sz = 3 * sizeof(uint32_t) + n * sizeof(bios_memmap_t);

usr.sbin/vmd/loadfile_elf.c

331

i = memmap_sz / sizeof(uint32_t);

usr.sbin/vmd/loadfile_elf.c

339

consdev_sz = 3 * sizeof(uint32_t) + sizeof(bios_consdev_t);

usr.sbin/vmd/loadfile_elf.c

344

i += consdev_sz / sizeof(uint32_t);

usr.sbin/vmd/loadfile_elf.c

347

bootmac_sz = 3 * sizeof(uint32_t) +

usr.sbin/vmd/loadfile_elf.c

353

i += bootmac_sz / sizeof(uint32_t);

usr.sbin/vmd/loadfile_elf.c

361

return (i * sizeof(uint32_t));

usr.sbin/vmd/loadfile_elf.c

392

push_stack(uint32_t bootargsz, uint32_t end)

usr.sbin/vmd/loadfile_elf.c

394

uint32_t stack[1024];

usr.sbin/vmd/loadfile_elf.c

412

return (1024 - (loc - 1)) * sizeof(uint32_t);

usr.sbin/vmd/mc146818.c

166

mc146818_init(uint32_t vm_id, uint64_t memlo, uint64_t memhi)

usr.sbin/vmd/mc146818.c

233

rtc_update_rega(uint32_t data)

usr.sbin/vmd/mc146818.c

249

rtc_update_regb(uint32_t data)

usr.sbin/vmd/mc146818.c

282

uint32_t data = 0;

usr.sbin/vmd/mc146818.c

53

uint32_t vm_id;

usr.sbin/vmd/mc146818.h

18

void mc146818_init(uint32_t, uint64_t, uint64_t);

usr.sbin/vmd/ns8250.c

195

com_rcv(struct ns8250_dev *com, uint32_t vm_id, uint32_t vcpu_id)

usr.sbin/vmd/ns8250.c

248

vcpu_process_com_data(struct vm_exit *vei, uint32_t vm_id, uint32_t vcpu_id)

usr.sbin/vmd/ns8250.c

39

static void com_rcv(struct ns8250_dev *, uint32_t, uint32_t);

usr.sbin/vmd/ns8250.c

86

ns8250_init(int fd, uint32_t vmid)

usr.sbin/vmd/ns8250.h

72

uint32_t vmid;

usr.sbin/vmd/ns8250.h

74

uint32_t baudrate;

usr.sbin/vmd/ns8250.h

75

uint32_t pause_ct;

usr.sbin/vmd/ns8250.h

78

void ns8250_init(int, uint32_t);

usr.sbin/vmd/ns8250.h

80

uint8_t vcpu_process_com_data(struct vm_exit *, uint32_t, uint32_t);

usr.sbin/vmd/pci.c

341

uint32_t data = 0;

usr.sbin/vmd/pci.c

60

pci_add_bar(uint8_t id, uint32_t type, void *barfn, void *cookie)

usr.sbin/vmd/pci.h

105

uint32_t pci_addr_reg;

usr.sbin/vmd/pci.h

115

int pci_add_bar(uint8_t, uint32_t, void *, void *);

usr.sbin/vmd/pci.h

43

typedef int (*pci_cs_fn_t)(int dir, uint8_t reg, uint32_t *data);

usr.sbin/vmd/pci.h

44

typedef int (*pci_iobar_fn_t)(int dir, uint16_t reg, uint32_t *data, uint8_t *,

usr.sbin/vmd/pci.h

46

typedef int (*pci_mmiobar_fn_t)(int dir, uint32_t ofs, uint32_t *data);

usr.sbin/vmd/pci.h

60

uint32_t pd_cfg_space[PCI_CONFIG_SPACE_SIZE / 4];

usr.sbin/vmd/pci.h

74

uint32_t pd_bar[PCI_MAX_BARS];

usr.sbin/vmd/pci.h

75

uint32_t pd_cardbus_cis;

usr.sbin/vmd/pci.h

78

uint32_t pd_exp_rom_addr;

usr.sbin/vmd/pci.h

80

uint32_t pd_reserved0 : 24;

usr.sbin/vmd/pci.h

81

uint32_t pd_reserved1;

usr.sbin/vmd/pci.h

95

uint32_t pd_barsize[PCI_MAX_BARS];

usr.sbin/vmd/priv.c

548

uint32_t

usr.sbin/vmd/priv.c

549

vm_priv_addr(struct local_prefix *p, uint32_t vmid, int idx, int isvm)

usr.sbin/vmd/priv.c

585

vm_priv_addr6(struct local_prefix *p, uint32_t vmid, int idx, int isvm,

usr.sbin/vmd/priv.c

90

uint32_t imsg_type, peer_id;

usr.sbin/vmd/proc.c

449

uint32_t peer_id, type;

usr.sbin/vmd/proc.c

550

imsg_compose_event(struct imsgev *iev, uint32_t type, uint32_t peerid,

usr.sbin/vmd/proc.c

558

imsg_compose_event2(struct imsgev *iev, uint32_t type, uint32_t peerid,

usr.sbin/vmd/proc.c

571

imsg_composev_event(struct imsgev *iev, uint32_t type, uint32_t peerid,

usr.sbin/vmd/proc.c

593

uint32_t type, uint32_t peerid, int fd, void *data, size_t datalen)

usr.sbin/vmd/proc.c

608

proc_compose(struct privsep *ps, enum privsep_procid id, uint32_t type,

usr.sbin/vmd/proc.c

615

proc_composev_imsg(struct privsep *ps, enum privsep_procid id, uint32_t type,

usr.sbin/vmd/proc.c

616

uint32_t peerid, int fd, const struct iovec *iov, int iovcnt)

usr.sbin/vmd/proc.c

628

uint32_t type, const struct iovec *iov, int iovcnt)

usr.sbin/vmd/proc.c

635

uint32_t new_peerid)

usr.sbin/vmd/proc.c

639

uint32_t peerid, type;

usr.sbin/vmd/proc.c

646

if (new_peerid == (uint32_t)(-1))

usr.sbin/vmd/proc.h

141

int imsg_compose_event(struct imsgev *, uint32_t, uint32_t,

usr.sbin/vmd/proc.h

143

int imsg_compose_event2(struct imsgev *, uint32_t, uint32_t,

usr.sbin/vmd/proc.h

145

int imsg_composev_event(struct imsgev *, uint32_t, uint32_t,

usr.sbin/vmd/proc.h

149

uint32_t, uint32_t, int, void *, size_t);

usr.sbin/vmd/proc.h

151

uint32_t, void *data, size_t);

usr.sbin/vmd/proc.h

153

uint32_t, uint32_t, int, const struct iovec *, int);

usr.sbin/vmd/proc.h

155

uint32_t, const struct iovec *, int);

usr.sbin/vmd/proc.h

157

enum privsep_procid, uint32_t);

usr.sbin/vmd/psp.c

121

psp_launch_start(uint32_t *handle, int seves)

usr.sbin/vmd/psp.c

150

psp_launch_update(uint32_t handle, vaddr_t v, size_t len)

usr.sbin/vmd/psp.c

177

psp_encrypt_state(uint32_t handle, uint32_t asid, uint32_t vmid,

usr.sbin/vmd/psp.c

178

uint32_t vcpuid)

usr.sbin/vmd/psp.c

198

psp_launch_measure(uint32_t handle)

usr.sbin/vmd/psp.c

246

psp_launch_finish(uint32_t handle)

usr.sbin/vmd/psp.c

268

psp_activate(uint32_t handle, uint32_t asid)

usr.sbin/vmd/psp.c

292

psp_guest_shutdown(uint32_t handle)

usr.sbin/vmd/psp.c

93

psp_get_gstate(uint32_t handle, uint32_t *policy, uint32_t *asid,

usr.sbin/vmd/sev.c

44

uint32_t handle;

usr.sbin/vmd/vioblk.c

228

vioblk_cmd_name(uint32_t type)

usr.sbin/vmd/vioblk.c

251

uint32_t cmd_len;

usr.sbin/vmd/vioblk.c

396

uint32_t type;

usr.sbin/vmd/vioblk.c

40

static uint32_t vioblk_read(struct virtio_dev *, struct viodev_msg *, int *);

usr.sbin/vmd/vioblk.c

42

static uint32_t vioblk_dev_read(struct virtio_dev *, struct viodev_msg *);

usr.sbin/vmd/vioblk.c

531

uint32_t data = msg->data;

usr.sbin/vmd/vioblk.c

556

static uint32_t

usr.sbin/vmd/vioblk.c

559

uint32_t data = 0;

usr.sbin/vmd/vioblk.c

585

static uint32_t

usr.sbin/vmd/vioblk.c

589

uint32_t data = 0;

usr.sbin/vmd/vioblk.c

600

data = (uint32_t)(0xFFFFFFFF & vioblk->capacity);

usr.sbin/vmd/vioblk.c

608

data = (uint32_t)(vioblk->capacity >> 32);

usr.sbin/vmd/vionet.c

1004

data = dev->driver_feature & (uint32_t)(-1);

usr.sbin/vmd/vionet.c

1040

data = (uint32_t)(0xFFFFFFFF & pci_cfg->queue_desc);

usr.sbin/vmd/vionet.c

1043

data = (uint32_t)(pci_cfg->queue_desc >> 32);

usr.sbin/vmd/vionet.c

1046

data = (uint32_t)(0xFFFFFFFF & pci_cfg->queue_avail);

usr.sbin/vmd/vionet.c

1049

data = (uint32_t)(pci_cfg->queue_avail >> 32);

usr.sbin/vmd/vionet.c

1052

data = (uint32_t)(0xFFFFFFFF & pci_cfg->queue_used);

usr.sbin/vmd/vionet.c

1055

data = (uint32_t)(pci_cfg->queue_used >> 32);

usr.sbin/vmd/vionet.c

1069

uint32_t data = msg->data;

usr.sbin/vmd/vionet.c

1266

static uint32_t

usr.sbin/vmd/vionet.c

1269

uint32_t data = 0;

usr.sbin/vmd/vionet.c

1281

data = (uint32_t)(-1);

usr.sbin/vmd/vionet.c

1320

static uint32_t

usr.sbin/vmd/vionet.c

1324

uint32_t data = 0;

usr.sbin/vmd/vionet.c

72

static uint32_t vionet_read(struct virtio_dev *, struct viodev_msg *, int *);

usr.sbin/vmd/vionet.c

74

static uint32_t vionet_cfg_read(struct virtio_dev *, struct viodev_msg *);

usr.sbin/vmd/vionet.c

79

static uint32_t vionet_dev_read(struct virtio_dev *, struct viodev_msg *);

usr.sbin/vmd/vionet.c

840

uint32_t type;

usr.sbin/vmd/vionet.c

977

static uint32_t

usr.sbin/vmd/vionet.c

981

uint32_t data = 0;

usr.sbin/vmd/vionet.c

991

data = dev->device_feature & (uint32_t)(-1);

usr.sbin/vmd/vioqcow2.c

146

uint32_t backingsz;

usr.sbin/vmd/vioqcow2.c

212

uint32_t backingsz;

usr.sbin/vmd/vioqcow2.c

49

uint32_t version;

usr.sbin/vmd/vioqcow2.c

51

uint32_t backingsz;

usr.sbin/vmd/vioqcow2.c

52

uint32_t clustershift;

usr.sbin/vmd/vioqcow2.c

54

uint32_t cryptmethod;

usr.sbin/vmd/vioqcow2.c

55

uint32_t l1sz;

usr.sbin/vmd/vioqcow2.c

58

uint32_t refsz;

usr.sbin/vmd/vioqcow2.c

59

uint32_t snapcount;

usr.sbin/vmd/vioqcow2.c

65

uint32_t reforder; /* Bits = 1 << reforder */

usr.sbin/vmd/vioqcow2.c

66

uint32_t headersz;

usr.sbin/vmd/vioqcow2.c

78

uint32_t cryptmethod;

usr.sbin/vmd/vioqcow2.c

80

uint32_t l1sz;

usr.sbin/vmd/vioqcow2.c

86

uint32_t nsnap;

usr.sbin/vmd/vioqcow2.c

92

uint32_t refssz;

usr.sbin/vmd/vioqcow2.c

93

uint32_t headersz;

usr.sbin/vmd/vioscsi.c

1156

uint32_t rpl_length;

usr.sbin/vmd/vioscsi.c

1257

uint32_t read_lba;

usr.sbin/vmd/vioscsi.c

1389

uint32_t read_lba;

usr.sbin/vmd/vioscsi.c

1728

_lto4b((uint32_t)vioscsi->n_blocks, toc_data_p);

usr.sbin/vmd/vioscsi.c

1732

_lto2b((uint32_t)toc_data_len - 2, toc_data);

usr.sbin/vmd/vioscsi.c

2065

static uint32_t

usr.sbin/vmd/vioscsi.c

2066

vioscsi_io_cfg(struct virtio_dev *dev, int dir, uint8_t reg, uint32_t data,

usr.sbin/vmd/vioscsi.c

2070

uint32_t res = 0;

usr.sbin/vmd/vioscsi.c

2102

res = (uint32_t)(VIOSCSI_NUM_REQ_QUEUES);

usr.sbin/vmd/vioscsi.c

2109

res = (uint32_t)(VIOSCSI_SEG_MAX);

usr.sbin/vmd/vioscsi.c

2116

res = (uint32_t)(vioscsi->max_xfer);

usr.sbin/vmd/vioscsi.c

2123

res = (uint32_t)(VIOSCSI_CMD_PER_LUN);

usr.sbin/vmd/vioscsi.c

2133

res = (uint32_t)(VIOSCSI_SENSE_LEN);

usr.sbin/vmd/vioscsi.c

2140

res = (uint32_t)(VIOSCSI_CDB_LEN);

usr.sbin/vmd/vioscsi.c

2151

res = (uint32_t)(VIOSCSI_MAX_TARGET);

usr.sbin/vmd/vioscsi.c

2158

res = (uint32_t)(VIOSCSI_MAX_LUN);

usr.sbin/vmd/vioscsi.c

430

uint32_t type;

usr.sbin/vmd/vioscsi.c

53

static uint32_t vioscsi_io_cfg(struct virtio_dev *, int, uint8_t, uint32_t,

usr.sbin/vmd/vioscsi.c

56

static uint32_t vioscsi_read(struct virtio_dev *, struct viodev_msg *, int *);

usr.sbin/vmd/vioscsi.c

565

uint32_t data = msg->data;

usr.sbin/vmd/vioscsi.c

590

static uint32_t

usr.sbin/vmd/vioscsi.c

593

uint32_t data = 0;

usr.sbin/vmd/virtio.c

1414

uint32_t dev_cfg_len)

usr.sbin/vmd/virtio.c

147

uint32_t

usr.sbin/vmd/virtio.c

148

vring_size(uint32_t vq_size)

usr.sbin/vmd/virtio.c

150

uint32_t allocsize1, allocsize2;

usr.sbin/vmd/virtio.c

1690

uint32_t type;

usr.sbin/vmd/virtio.c

1742

uint32_t vmm_id = gdev->vmm_id;

usr.sbin/vmd/virtio.c

1779

virtio_pci_io(int dir, uint16_t reg, uint32_t *data, uint8_t *intr,

usr.sbin/vmd/virtio.c

324

virtio_io_dispatch(int dir, uint16_t reg, uint32_t *data, uint8_t *intr,

usr.sbin/vmd/virtio.c

337

*data = (uint32_t)(-1);

usr.sbin/vmd/virtio.c

347

*data = (uint32_t)(-1);

usr.sbin/vmd/virtio.c

356

uint32_t

usr.sbin/vmd/virtio.c

357

virtio_io_cfg(struct virtio_dev *dev, int dir, uint8_t reg, uint32_t data,

usr.sbin/vmd/virtio.c

361

uint32_t res = 0;

usr.sbin/vmd/virtio.c

553

res = dev->device_feature & (uint32_t)(-1);

usr.sbin/vmd/virtio.c

566

res = dev->driver_feature & (uint32_t)(-1);

usr.sbin/vmd/virtio.c

602

res = (uint32_t)(0xFFFFFFFF & pci_cfg->queue_desc);

usr.sbin/vmd/virtio.c

605

res = (uint32_t)(pci_cfg->queue_desc >> 32);

usr.sbin/vmd/virtio.c

608

res = (uint32_t)(0xFFFFFFFF & pci_cfg->queue_avail);

usr.sbin/vmd/virtio.c

611

res = (uint32_t)(pci_cfg->queue_avail >> 32);

usr.sbin/vmd/virtio.c

614

res = (uint32_t)(0xFFFFFFFF & pci_cfg->queue_used);

usr.sbin/vmd/virtio.c

617

res = (uint32_t)(pci_cfg->queue_used >> 32);

usr.sbin/vmd/virtio.c

632

virtio_io_isr(int dir, uint16_t reg, uint32_t *data, uint8_t *intr,

usr.sbin/vmd/virtio.c

658

virtio_io_notify(int dir, uint16_t reg, uint32_t *data, uint8_t *intr,

usr.sbin/vmd/virtio.c

82

static void virtio_pci_add_cap(uint8_t, uint8_t, uint8_t, uint32_t);

usr.sbin/vmd/virtio.c

85

static int virtio_io_dispatch(int, uint16_t, uint32_t *, uint8_t *, void *,

usr.sbin/vmd/virtio.c

851

vmmci_io(int dir, uint16_t reg, uint32_t *data, uint8_t *intr,

usr.sbin/vmd/virtio.c

87

static int virtio_io_isr(int, uint16_t, uint32_t *, uint8_t *, void *, uint8_t);

usr.sbin/vmd/virtio.c

88

static int virtio_io_notify(int, uint16_t, uint32_t *, uint8_t *, void *,

usr.sbin/vmd/virtio.h

148

uint32_t data; /* Data (if any) */

usr.sbin/vmd/virtio.h

156

uint32_t device_feature;

usr.sbin/vmd/virtio.h

157

uint32_t guest_feature;

usr.sbin/vmd/virtio.h

158

uint32_t queue_pfn;

usr.sbin/vmd/virtio.h

187

uint32_t qs;

usr.sbin/vmd/virtio.h

190

uint32_t mask;

usr.sbin/vmd/virtio.h

196

uint32_t vq_availoffset;

usr.sbin/vmd/virtio.h

202

uint32_t vq_usedoffset;

usr.sbin/vmd/virtio.h

259

uint32_t seg_max; /* maximum number of segments */

usr.sbin/vmd/virtio.h

278

uint32_t max_xfer;

usr.sbin/vmd/virtio.h

371

uint32_t vm_id; /* vmd(8) vm identifier [r] */

usr.sbin/vmd/virtio.h

372

uint32_t vmm_id; /* vmm(4) vm identifier [r] */

usr.sbin/vmd/virtio.h

388

uint32_t vring_size(uint32_t);

usr.sbin/vmd/virtio.h

391

int virtio_pci_io(int, uint16_t, uint32_t *, uint8_t *, void *, uint8_t);

usr.sbin/vmd/virtio.h

394

uint32_t virtio_io_cfg(struct virtio_dev *, int, uint8_t, uint32_t, uint8_t);

usr.sbin/vmd/virtio.h

407

int vmmci_io(int, uint16_t, uint32_t *, uint8_t *, void *, uint8_t);

usr.sbin/vmd/virtio.h

411

const char *vioblk_cmd_name(uint32_t);

usr.sbin/vmd/vm.c

1126

vcpu_halt(uint32_t vcpu_id)

usr.sbin/vmd/vm.c

1134

vcpu_unhalt(uint32_t vcpu_id)

usr.sbin/vmd/vm.c

1142

vcpu_signal_run(uint32_t vcpu_id)

usr.sbin/vmd/vm.c

313

uint32_t id, type;

usr.sbin/vmd/vm.c

499

vcpu_reset(uint32_t vmid, uint32_t vcpu_id, struct vcpu_reg_state *vrs)

usr.sbin/vmd/vm.c

812

uint32_t n = vrp->vrp_vcpu_id;

usr.sbin/vmd/vm.c

934

vcpu_intr(uint32_t vmm_id, uint32_t vcpu_id, uint8_t intr)

usr.sbin/vmd/vm_agentx.c

143

uint32_t type;

usr.sbin/vmd/vmd.c

101

uint32_t peer_id, type, vm_id = 0;

usr.sbin/vmd/vmd.c

1093

vm_claimid(const char *name, int uid, uint32_t *id)

usr.sbin/vmd/vmd.c

1125

struct vmd_vm **ret_vm, uint32_t id, uid_t uid)

usr.sbin/vmd/vmd.c

1129

uint32_t nid, rng;

usr.sbin/vmd/vmd.c

1729

uint32_t

usr.sbin/vmd/vmd.c

288

uint32_t peer_id, type;

usr.sbin/vmd/vmd.c

326

if (vm->vm_peerid != (uint32_t)-1) {

usr.sbin/vmd/vmd.c

387

config_setvm(ps, vm, (uint32_t)-1, vm->vm_uid);

usr.sbin/vmd/vmd.c

468

uint32_t type;

usr.sbin/vmd/vmd.c

484

uint32_t type;

usr.sbin/vmd/vmd.c

61

int vm_claimid(const char *, int, uint32_t *);

usr.sbin/vmd/vmd.c

941

vm_getbyvmid(uint32_t vmid)

usr.sbin/vmd/vmd.c

957

vm_getbyid(uint32_t id)

usr.sbin/vmd/vmd.c

972

uint32_t

usr.sbin/vmd/vmd.c

973

vm_id2vmid(uint32_t id, struct vmd_vm *vm)

usr.sbin/vmd/vmd.c

982

uint32_t

usr.sbin/vmd/vmd.c

983

vm_vmid2id(uint32_t vmid, struct vmd_vm *vm)

usr.sbin/vmd/vmd.h

101

#define IMSG_AGENTX_PEERID (uint32_t)-2

usr.sbin/vmd/vmd.h

157

uint32_t vmr_id;

usr.sbin/vmd/vmd.h

168

uint32_t vir_id;

usr.sbin/vmd/vmd.h

178

uint32_t vid_id;

usr.sbin/vmd/vmd.h

187

uint32_t vfr_id;

usr.sbin/vmd/vmd.h

195

uint32_t var_vmid;

usr.sbin/vmd/vmd.h

200

uint32_t var_vmid;

usr.sbin/vmd/vmd.h

212

uint32_t vmc_id;

usr.sbin/vmd/vmd.h

229

uint32_t vmc_asid[VMM_MAX_VCPUS];

usr.sbin/vmd/vmd.h

232

uint32_t vmc_poscbit;

usr.sbin/vmd/vmd.h

288

uint32_t sw_id;

usr.sbin/vmd/vmd.h

305

uint32_t vm_vmid; /* vmd(8) identifier */

usr.sbin/vmd/vmd.h

306

uint32_t vm_vmmid; /* vmm(4) identifier */

usr.sbin/vmd/vmd.h

307

uint32_t vm_peerid;

usr.sbin/vmd/vmd.h

310

uint32_t vm_sev_handle;

usr.sbin/vmd/vmd.h

311

uint32_t vm_sev_asid[VMM_MAX_VCPUS_PER_VM];

usr.sbin/vmd/vmd.h

312

uint32_t vm_poscbit;

usr.sbin/vmd/vmd.h

400

uint32_t vmd_nvm;

usr.sbin/vmd/vmd.h

403

uint32_t vmd_nswitches;

usr.sbin/vmd/vmd.h

469

struct vmd_vm *vm_getbyid(uint32_t);

usr.sbin/vmd/vmd.h

470

struct vmd_vm *vm_getbyvmid(uint32_t);

usr.sbin/vmd/vmd.h

471

uint32_t vm_id2vmid(uint32_t, struct vmd_vm *);

usr.sbin/vmd/vmd.h

472

uint32_t vm_vmid2id(uint32_t, struct vmd_vm *);

usr.sbin/vmd/vmd.h

478

struct vmd_vm **, uint32_t, uid_t);

usr.sbin/vmd/vmd.h

485

uint32_t prefixlen2mask(uint8_t);

usr.sbin/vmd/vmd.h

507

uint32_t vm_priv_addr(struct local_prefix *, uint32_t, int, int);

usr.sbin/vmd/vmd.h

508

int vm_priv_addr6(struct local_prefix *, uint32_t, int, int,

usr.sbin/vmd/vmd.h

523

int vcpu_reset(uint32_t, uint32_t, struct vcpu_reg_state *);

usr.sbin/vmd/vmd.h

534

void vcpu_assert_irq(uint32_t, uint32_t, int);

usr.sbin/vmd/vmd.h

535

void vcpu_deassert_irq(uint32_t, uint32_t, int);

usr.sbin/vmd/vmd.h

541

void set_return_data(struct vm_exit *, uint32_t);

usr.sbin/vmd/vmd.h

542

void get_input_data(struct vm_exit *, uint32_t *);

usr.sbin/vmd/vmd.h

546

void vcpu_halt(uint32_t);

usr.sbin/vmd/vmd.h

547

void vcpu_unhalt(uint32_t);

usr.sbin/vmd/vmd.h

548

void vcpu_signal_run(uint32_t);

usr.sbin/vmd/vmd.h

549

int vcpu_intr(uint32_t, uint32_t, uint8_t);

usr.sbin/vmd/vmd.h

568

int config_setvm(struct privsep *, struct vmd_vm *, uint32_t, uid_t);

usr.sbin/vmd/vmd.h

598

int psp_get_gstate(uint32_t, uint32_t *, uint32_t *, uint8_t *);

usr.sbin/vmd/vmd.h

599

int psp_launch_start(uint32_t *, int);

usr.sbin/vmd/vmd.h

600

int psp_launch_update(uint32_t, vaddr_t, size_t);

usr.sbin/vmd/vmd.h

601

int psp_encrypt_state(uint32_t, uint32_t, uint32_t, uint32_t);

usr.sbin/vmd/vmd.h

602

int psp_launch_measure(uint32_t);

usr.sbin/vmd/vmd.h

603

int psp_launch_finish(uint32_t);

usr.sbin/vmd/vmd.h

604

int psp_activate(uint32_t, uint32_t);

usr.sbin/vmd/vmd.h

605

int psp_guest_shutdown(uint32_t);

usr.sbin/vmd/vmm.c

115

uint32_t id = 0, vm_id, type;

usr.sbin/vmd/vmm.c

44

int vmm_start_vm(struct imsg *, uint32_t *, pid_t *);

usr.sbin/vmd/vmm.c

460

uint32_t type;

usr.sbin/vmd/vmm.c

599

vmm_start_vm(struct imsg *imsg, uint32_t *id, pid_t *pid)

usr.sbin/vmd/vmm.c

607

uint32_t peer_id;

usr.sbin/vmd/vmm.c

789

uint32_t peer_id;

usr.sbin/vmd/vmm.h

22

void set_return_data(struct vm_exit *, uint32_t);

usr.sbin/vmd/vmm.h

23

void get_input_data(struct vm_exit *, uint32_t *);

usr.sbin/vmd/x86_vm.c

1062

pte_size = sizeof(uint32_t);

usr.sbin/vmd/x86_vm.c

890

vcpu_assert_irq(uint32_t vmm_id, uint32_t vcpu_id, int irq)

usr.sbin/vmd/x86_vm.c

914

vcpu_deassert_irq(uint32_t vmm_id, uint32_t vcpu_id, int irq)

usr.sbin/vmd/x86_vm.c

937

set_return_data(struct vm_exit *vei, uint32_t data)

usr.sbin/vmd/x86_vm.c

967

get_input_data(struct vm_exit *vei, uint32_t *data)