distrib/special/more/more.c
1180
static regex_t reg;
distrib/special/more/more.c
1187
if ((rv = regcomp(®, buf, REG_NOSUB)) != 0) {
distrib/special/more/more.c
1189
regerror(rv, ®, ebuf, sizeof(ebuf));
distrib/special/more/more.c
1190
regfree(®);
distrib/special/more/more.c
1205
if ((rv = regexec(®, Line, 0, NULL, 0)) == 0) {
distrib/special/more/more.c
1238
regerror(rv, ®, ebuf, sizeof(ebuf));
lib/libc/arch/m88k/SYS.h
50
#define PIC_SAVE(reg) or reg, %r25, %r0
lib/libc/arch/m88k/SYS.h
51
#define PIC_RESTORE(reg) or %r25, reg, %r0
lib/libc/arch/m88k/SYS.h
60
#define PIC_LOAD(reg,sym) \
lib/libc/arch/m88k/SYS.h
63
ld reg, %r25, %r11
lib/libc/arch/m88k/SYS.h
64
#define PIC_STORE(reg,sym) \
lib/libc/arch/m88k/SYS.h
67
st reg, %r25, %r11
lib/libc/arch/m88k/SYS.h
69
#define PIC_LOAD(reg,sym) \
lib/libc/arch/m88k/SYS.h
71
ld reg, %r11, %r0
lib/libc/arch/m88k/SYS.h
72
#define PIC_STORE(reg,sym) \
lib/libc/arch/m88k/SYS.h
74
st reg, %r11, %r0
lib/libc/arch/sparc64/fpu/fpu_explode.c
298
__fpu_explode(fe, fp, type, reg)
lib/libc/arch/sparc64/fpu/fpu_explode.c
301
int type, reg;
lib/libc/arch/sparc64/fpu/fpu_explode.c
307
l[0] = __fpu_getreg64(reg & ~1);
lib/libc/arch/sparc64/fpu/fpu_explode.c
319
l[1] = __fpu_getreg64((reg & ~1) + 2);
lib/libc/arch/sparc64/fpu/fpu_explode.c
333
s = __fpu_getreg32(reg);
lib/libc/arch/sparc64/fpu/fpu_explode.c
357
reg));
lib/libpcap/gencode.c
2847
int reg;
lib/libpcap/gencode.c
2851
reg = alloc_reg();
lib/libpcap/gencode.c
2856
s->next->s.k = reg;
lib/libpcap/gencode.c
2858
a->regno = reg;
regress/sys/arch/sparc64/emul-ldqstq/badfreg/main.c
108
char *reg;
regress/sys/arch/sparc64/emul-ldqstq/badfreg/main.c
197
if (strcmp(fpt->reg, argv[1]) == 0 &&
regress/sys/ptrace/ptrace.c
54
struct reg regs;
sbin/atactl/atactl.c
1565
#define SMART_PRINTREG(str, reg) \
sbin/atactl/atactl.c
1567
data->cmd[0].reg, \
sbin/atactl/atactl.c
1568
data->cmd[1].reg, \
sbin/atactl/atactl.c
1569
data->cmd[2].reg, \
sbin/atactl/atactl.c
1570
data->cmd[3].reg, \
sbin/atactl/atactl.c
1571
data->cmd[4].reg)
sys/arch/alpha/alpha/machdep.c
1247
frametoreg(struct trapframe *framep, struct reg *regp)
sys/arch/alpha/alpha/machdep.c
1285
regtoframe(struct reg *regp, struct trapframe *framep)
sys/arch/alpha/alpha/machdep.c
130
void printregs(struct reg *);
sys/arch/alpha/alpha/machdep.c
1323
printregs(struct reg *regp)
sys/arch/alpha/alpha/machdep.c
1335
struct reg reg;
sys/arch/alpha/alpha/machdep.c
1337
frametoreg(framep, ®);
sys/arch/alpha/alpha/machdep.c
1338
reg.r_regs[R_SP] = alpha_pal_rdusp();
sys/arch/alpha/alpha/machdep.c
1341
printregs(®);
sys/arch/alpha/alpha/machdep.c
1390
frametoreg(frame, (struct reg *)ksc.sc_regs);
sys/arch/alpha/alpha/machdep.c
1478
regtoframe((struct reg *)ksc.sc_regs, p->p_md.md_tf);
sys/arch/alpha/alpha/mcclock.c
52
#define mc146818_write(dev, reg, datum) \
sys/arch/alpha/alpha/mcclock.c
53
(*(dev)->sc_busfns->mc_bf_write)(dev, reg, datum)
sys/arch/alpha/alpha/mcclock.c
54
#define mc146818_read(dev, reg) \
sys/arch/alpha/alpha/mcclock.c
55
(*(dev)->sc_busfns->mc_bf_read)(dev, reg)
sys/arch/alpha/alpha/process_machdep.c
121
process_write_regs(struct proc *p, struct reg *regs)
sys/arch/alpha/alpha/process_machdep.c
98
process_read_regs(struct proc *p, struct reg *regs)
sys/arch/alpha/alpha/trap.c
677
#define irp(p, reg) \
sys/arch/alpha/alpha/trap.c
678
((reg_to_framereg[(reg)] == -1) ? NULL : \
sys/arch/alpha/alpha/trap.c
679
&(p)->p_md.md_tf->tf_regs[reg_to_framereg[(reg)]])
sys/arch/alpha/include/asm.h
490
#define MSG(msg,reg,label) \
sys/arch/alpha/include/asm.h
491
lda reg, label; \
sys/arch/alpha/include/asm.h
596
#define LDGP(reg) \
sys/arch/alpha/include/asm.h
597
ldgp gp, 0(reg)
sys/arch/alpha/include/cpu.h
110
struct reg;
sys/arch/alpha/include/cpu.h
135
void frametoreg(struct trapframe *, struct reg *);
sys/arch/alpha/include/cpu.h
147
void regtoframe(struct reg *, struct trapframe *);
sys/arch/alpha/include/cpu.h
416
struct reg;
sys/arch/alpha/include/reg.h
97
void frametoreg(struct trapframe *, struct reg *);
sys/arch/alpha/include/reg.h
98
void regtoframe(struct reg *, struct trapframe *);
sys/arch/alpha/isa/mcclock_isa.c
103
mcclock_isa_write(struct mcclock_softc *mcsc, u_int reg, u_int datum)
sys/arch/alpha/isa/mcclock_isa.c
109
bus_space_write_1(iot, ioh, 0, reg);
sys/arch/alpha/isa/mcclock_isa.c
114
mcclock_isa_read(struct mcclock_softc *mcsc, u_int reg)
sys/arch/alpha/isa/mcclock_isa.c
120
bus_space_write_1(iot, ioh, 0, reg);
sys/arch/alpha/pci/apecs_pci.c
145
printf("apecs_conf_read: tag 0x%lx, reg 0x%lx -> %x @ %p%s\n", tag, reg,
sys/arch/alpha/pci/apecs_pci.c
193
reg, data, datap);
sys/arch/alpha/pci/cia_pci.c
193
printf("cia_conf_read: tag 0x%lx, reg 0x%lx -> %x @ %p%s\n", tag, reg,
sys/arch/alpha/pci/cia_pci.c
258
reg, data, datap);
sys/arch/alpha/pci/irongate.c
77
pcireg_t reg;
sys/arch/alpha/pci/irongate.c
95
reg = irongate_conf_read0(icp, tag, PCI_CLASS_REG);
sys/arch/alpha/pci/irongate.c
96
icp->ic_rev = PCI_REVISION(reg);
sys/arch/alpha/pci/lca_pci.c
163
printf("lca_conf_read: tag 0x%lx, reg 0x%lx -> %x @ %p%s\n", tag, reg,
sys/arch/alpha/pci/lca_pci.c
212
reg, data, datap);
sys/arch/alpha/pci/mcpciareg.h
301
#define CAP_REV(reg) ((reg) & 0xf)
sys/arch/alpha/pci/mcpciareg.h
302
#define HORSE_REV(reg) (((reg) >> 4) & 0xf)
sys/arch/alpha/pci/mcpciareg.h
303
#define SADDLE_REV(reg) (((reg) >> 8) & 0xf)
sys/arch/alpha/pci/mcpciareg.h
304
#define SADDLE_TYPE(reg) (((reg) >> 12) & 0x3)
sys/arch/alpha/pci/mcpciareg.h
305
#define EISA_PRESENT(reg) ((reg) & (1 << 15))
sys/arch/alpha/pci/mcpciareg.h
306
#define IS_MCPCIA_MAGIC(reg) (((reg) & 0xffff0000) == 0x6000000)
sys/arch/alpha/tc/mcclock_ioasic.c
103
return (sc->sc_dp[reg].datum);
sys/arch/alpha/tc/mcclock_ioasic.c
91
mcclock_ioasic_write(struct mcclock_softc *dev, u_int reg, u_int datum)
sys/arch/alpha/tc/mcclock_ioasic.c
95
sc->sc_dp[reg].datum = datum;
sys/arch/alpha/tc/mcclock_ioasic.c
99
mcclock_ioasic_read(struct mcclock_softc *dev, u_int reg)
sys/arch/amd64/amd64/cpu.c
1339
u_int64_t reg;
sys/arch/amd64/amd64/cpu.c
1351
reg = PATENTRY(0, PAT_WB) | PATENTRY(1, PAT_WC) |
sys/arch/amd64/amd64/cpu.c
1356
wrmsr(MSR_CR_PAT, reg);
sys/arch/amd64/amd64/efifb.c
427
int reg;
sys/arch/amd64/amd64/efifb.c
429
for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) {
sys/arch/amd64/amd64/efifb.c
430
if (!pci_mapreg_probe(pc, tag, reg, &type))
sys/arch/amd64/amd64/efifb.c
436
if (pci_mapreg_info(pc, tag, reg, type, &base, &size, NULL))
sys/arch/amd64/amd64/efifb.c
444
reg += 4;
sys/arch/amd64/amd64/efifb.c
458
int reg;
sys/arch/amd64/amd64/efifb.c
460
for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) {
sys/arch/amd64/amd64/efifb.c
461
if (!pci_mapreg_probe(pc, tag, reg, &type))
sys/arch/amd64/amd64/efifb.c
467
if (pci_mapreg_info(pc, tag, reg, type, &base, &size, NULL))
sys/arch/amd64/amd64/efifb.c
480
reg += 4;
sys/arch/amd64/amd64/identcpu.c
378
pcpuid(struct cpu_info *ci, const char *id, char reg, uint32_t val,
sys/arch/amd64/amd64/identcpu.c
382
pcpu0id3(id, reg, val, bits, 0, 0, NULL, 0, 0, NULL);
sys/arch/amd64/amd64/identcpu.c
384
printf("\n%s: cpuid %s e%cx=", ci->ci_dev->dv_xname, id, reg);
sys/arch/amd64/amd64/lapic.c
104
u_int32_t x2apic_readreg(int reg);
sys/arch/amd64/amd64/lapic.c
106
void x2apic_writereg(int reg, u_int32_t val);
sys/arch/amd64/amd64/lapic.c
109
u_int32_t i82489_readreg(int reg);
sys/arch/amd64/amd64/lapic.c
111
void i82489_writereg(int reg, u_int32_t val);
sys/arch/amd64/amd64/lapic.c
121
i82489_readreg(int reg)
sys/arch/amd64/amd64/lapic.c
124
+ reg));
sys/arch/amd64/amd64/lapic.c
134
i82489_writereg(int reg, u_int32_t val)
sys/arch/amd64/amd64/lapic.c
136
*((volatile u_int32_t *)(((volatile u_int8_t *)local_apic) + reg)) =
sys/arch/amd64/amd64/lapic.c
141
x2apic_readreg(int reg)
sys/arch/amd64/amd64/lapic.c
143
return rdmsr(MSR_X2APIC_BASE + (reg >> 4));
sys/arch/amd64/amd64/lapic.c
153
x2apic_writereg(int reg, u_int32_t val)
sys/arch/amd64/amd64/lapic.c
155
wrmsr(MSR_X2APIC_BASE + (reg >> 4), val);
sys/arch/amd64/amd64/lapic.c
722
int reg;
sys/arch/amd64/amd64/lapic.c
725
reg = LAPIC_LVTT + (pin << 4);
sys/arch/amd64/amd64/lapic.c
726
val = lapic_readreg(reg);
sys/arch/amd64/amd64/lapic.c
728
lapic_writereg(reg, val);
sys/arch/amd64/amd64/lapic.c
734
int reg;
sys/arch/amd64/amd64/lapic.c
737
reg = LAPIC_LVTT + (pin << 4);
sys/arch/amd64/amd64/lapic.c
738
val = lapic_readreg(reg);
sys/arch/amd64/amd64/lapic.c
740
lapic_writereg(reg, val);
sys/arch/amd64/amd64/machdep.c
2202
check_context(const struct reg *regs, struct trapframe *tf)
sys/arch/amd64/amd64/mpbios_intr_fixup.c
103
reg = pci_conf_read(pc, tag, NFORCE4_PNPIRQ3);
sys/arch/amd64/amd64/mpbios_intr_fixup.c
104
pin = (reg & NFORCE4_USB1_MASK) >> NFORCE4_USB1_SHIFT;
sys/arch/amd64/amd64/mpbios_intr_fixup.c
107
pin = (reg & NFORCE4_LAN_MASK) >> NFORCE4_LAN_SHIFT;
sys/arch/amd64/amd64/mpbios_intr_fixup.c
119
pcireg_t reg;
sys/arch/amd64/amd64/mpbios_intr_fixup.c
124
reg = pci_conf_read(pc, tag, NFORCE4_PNPIRQ2);
sys/arch/amd64/amd64/mpbios_intr_fixup.c
125
pin = (reg & NFORCE4_SATA1_MASK) >> NFORCE4_SATA1_SHIFT;
sys/arch/amd64/amd64/mpbios_intr_fixup.c
128
pin = (reg & NFORCE4_SATA2_MASK) >> NFORCE4_SATA2_SHIFT;
sys/arch/amd64/amd64/mpbios_intr_fixup.c
87
pcireg_t reg;
sys/arch/amd64/amd64/mpbios_intr_fixup.c
92
reg = pci_conf_read(pc, tag, NFORCE4_PNPIRQ2);
sys/arch/amd64/amd64/mpbios_intr_fixup.c
93
pin = (reg & NFORCE4_USB2_MASK) >> NFORCE4_USB2_SHIFT;
sys/arch/amd64/amd64/mpbios_intr_fixup.c
96
pin = (reg & NFORCE4_SATA1_MASK) >> NFORCE4_SATA1_SHIFT;
sys/arch/amd64/amd64/mpbios_intr_fixup.c
99
pin = (reg & NFORCE4_SATA2_MASK) >> NFORCE4_SATA2_SHIFT;
sys/arch/amd64/amd64/pctr.c
63
int i, num, reg;
sys/arch/amd64/amd64/pctr.c
66
reg = pctr_isamd ? MSR_K7_EVNTSEL0 : MSR_EVNTSEL0;
sys/arch/amd64/amd64/pctr.c
68
st->pctr_fn[i] = rdmsr(reg + i);
sys/arch/amd64/amd64/process_machdep.c
129
process_write_regs(struct proc *p, struct reg *regs)
sys/arch/amd64/amd64/process_machdep.c
85
process_read_regs(struct proc *p, struct reg *regs)
sys/arch/amd64/amd64/vmm_machdep.c
5718
uint8_t crnum, dir, reg;
sys/arch/amd64/amd64/vmm_machdep.c
5740
reg = (exit_qual & 0xf00) >> 8;
sys/arch/amd64/amd64/vmm_machdep.c
5745
switch (reg) {
sys/arch/amd64/include/asm.h
134
# define RETGUARD_SETUP_OFF(x, reg, off) \
sys/arch/amd64/include/asm.h
136
movq (__retguard_ ## x)(%rip), %reg; \
sys/arch/amd64/include/asm.h
137
xorq off(%rsp), %reg
sys/arch/amd64/include/asm.h
138
# define RETGUARD_SETUP(x, reg) \
sys/arch/amd64/include/asm.h
139
RETGUARD_SETUP_OFF(x, reg, 0)
sys/arch/amd64/include/asm.h
140
# define RETGUARD_CHECK(x, reg) \
sys/arch/amd64/include/asm.h
141
xorq (%rsp), %reg; \
sys/arch/amd64/include/asm.h
142
cmpq (__retguard_ ## x)(%rip), %reg; \
sys/arch/amd64/include/asm.h
147
# define RETGUARD_PUSH(reg) \
sys/arch/amd64/include/asm.h
148
pushq %reg
sys/arch/amd64/include/asm.h
149
# define RETGUARD_POP(reg) \
sys/arch/amd64/include/asm.h
150
popq %reg
sys/arch/amd64/include/asm.h
164
# define RETGUARD_SETUP_OFF(x, reg, off)
sys/arch/amd64/include/asm.h
165
# define RETGUARD_SETUP(x, reg)
sys/arch/amd64/include/asm.h
166
# define RETGUARD_CHECK(x, reg)
sys/arch/amd64/include/asm.h
167
# define RETGUARD_PUSH(reg)
sys/arch/amd64/include/asm.h
168
# define RETGUARD_POP(reg)
sys/arch/amd64/include/asm.h
186
#define JMP_RETPOLINE(reg) \
sys/arch/amd64/include/asm.h
192
69: mov %reg,(%rsp) ; \
sys/arch/amd64/include/cpufunc.h
403
xsetbv(uint32_t reg, uint64_t mask)
sys/arch/amd64/include/cpufunc.h
409
__asm volatile("xsetbv" :: "c" (reg), "a" (lo), "d" (hi) : "memory");
sys/arch/amd64/include/cpufunc.h
413
xgetbv(uint32_t reg)
sys/arch/amd64/include/cpufunc.h
417
__asm volatile("xgetbv" : "=a" (lo), "=d" (hi) : "c" (reg));
sys/arch/amd64/include/frameasm.h
191
#define CHECK_ASTPENDING(reg) movq CPUVAR(CURPROC),reg ; \
sys/arch/amd64/include/frameasm.h
192
cmpq $0, reg ; \
sys/arch/amd64/include/frameasm.h
194
cmpl $0, P_MD_ASTPENDING(reg) ; \
sys/arch/amd64/include/frameasm.h
197
#define CLEAR_ASTPENDING(reg) movl $0, P_MD_ASTPENDING(reg)
sys/arch/amd64/include/reg.h
122
int check_context(const struct reg *, struct trapframe *);
sys/arch/amd64/isa/clock.c
142
mc146818_read(void *sc, u_int reg)
sys/arch/amd64/isa/clock.c
144
outb(IO_RTC, reg);
sys/arch/amd64/isa/clock.c
150
mc146818_write(void *sc, u_int reg, u_int datum)
sys/arch/amd64/isa/clock.c
152
outb(IO_RTC, reg);
sys/arch/amd64/pci/aapic.c
60
pcireg_t reg;
sys/arch/amd64/pci/aapic.c
71
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, AMD8131_IOAPIC_CTL);
sys/arch/amd64/pci/aapic.c
72
reg |= AMD8131_IOAEN;
sys/arch/amd64/pci/aapic.c
73
pci_conf_write(pa->pa_pc, pa->pa_tag, AMD8131_IOAPIC_CTL, reg);
sys/arch/amd64/pci/aapic.c
78
reg = pci_conf_read(pa->pa_pc, tag, AMD8131_PCIX_MISC);
sys/arch/amd64/pci/aapic.c
79
reg &= ~AMD8131_NIOAMODE;
sys/arch/amd64/pci/aapic.c
80
pci_conf_write(pa->pa_pc, tag, AMD8131_PCIX_MISC, reg);
sys/arch/amd64/pci/pchb.c
100
#define AMD64HT_LDT_SEC_BUS_NUM(reg) (((reg) >> 8) & 0xff)
sys/arch/amd64/pci/pchb.c
341
int reg;
sys/arch/amd64/pci/pchb.c
343
reg = AMD64HT_LDT0_TYPE + i * 0x20;
sys/arch/amd64/pci/pchb.c
344
type = pci_conf_read(pa->pa_pc, pa->pa_tag, reg);
sys/arch/amd64/pci/pchb.c
349
reg = AMD64HT_LDT0_BUS + i * 0x20;
sys/arch/amd64/pci/pchb.c
350
bus = pci_conf_read(pa->pa_pc, pa->pa_tag, reg);
sys/arch/amd64/pci/pci_machdep.c
228
pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
sys/arch/amd64/pci/pci_machdep.c
233
KASSERT((reg & 0x3) == 0);
sys/arch/amd64/pci/pci_machdep.c
235
if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) {
sys/arch/amd64/pci/pci_machdep.c
240
(tag & 0x000ff00) << 4 | reg);
sys/arch/amd64/pci/pci_machdep.c
246
outl(PCI_MODE1_ADDRESS_REG, tag | reg);
sys/arch/amd64/pci/pci_machdep.c
255
pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
sys/arch/amd64/pci/pci_machdep.c
259
KASSERT((reg & 0x3) == 0);
sys/arch/amd64/pci/pci_machdep.c
261
if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) {
sys/arch/amd64/pci/pci_machdep.c
266
(tag & 0x000ff00) << 4 | reg, data);
sys/arch/amd64/pci/pci_machdep.c
272
outl(PCI_MODE1_ADDRESS_REG, tag | reg);
sys/arch/amd64/pci/pci_machdep.c
283
pcireg_t reg, table, type;
sys/arch/amd64/pci/pci_machdep.c
287
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
sys/arch/amd64/pci/pci_machdep.c
293
tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
sys/arch/amd64/pci/pci_machdep.c
308
pcireg_t reg;
sys/arch/amd64/pci/pci_machdep.c
311
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0)
sys/arch/amd64/pci/pci_machdep.c
314
tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
sys/arch/amd64/pci/pci_machdep.c
355
pcireg_t reg, mask;
sys/arch/amd64/pci/pci_machdep.c
358
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
sys/arch/amd64/pci/pci_machdep.c
362
if ((reg & PCI_MSI_MC_PVMASK) == 0)
sys/arch/amd64/pci/pci_machdep.c
365
if (reg & PCI_MSI_MC_C64) {
sys/arch/amd64/pci/pci_machdep.c
382
pcireg_t reg, mask;
sys/arch/amd64/pci/pci_machdep.c
385
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
sys/arch/amd64/pci/pci_machdep.c
389
if ((reg & PCI_MSI_MC_PVMASK) == 0)
sys/arch/amd64/pci/pci_machdep.c
392
if (reg & PCI_MSI_MC_C64) {
sys/arch/amd64/pci/pci_machdep.c
410
pcireg_t reg, addr;
sys/arch/amd64/pci/pci_machdep.c
413
if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0)
sys/arch/amd64/pci/pci_machdep.c
421
if (reg & PCI_MSI_MC_C64) {
sys/arch/amd64/pci/pci_machdep.c
429
pci_conf_write(pc, tag, off, reg | PCI_MSI_MC_MSIE);
sys/arch/amd64/pci/pci_machdep.c
439
pcireg_t reg;
sys/arch/amd64/pci/pci_machdep.c
445
if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®))
sys/arch/amd64/pci/pci_machdep.c
446
pci_conf_write(pc, tag, off, reg & ~PCI_MSI_MC_MSIE);
sys/arch/amd64/pci/pci_machdep.c
456
pcireg_t reg;
sys/arch/amd64/pci/pci_machdep.c
458
if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0)
sys/arch/amd64/pci/pci_machdep.c
461
reg = pci_conf_read(pc, tag, off);
sys/arch/amd64/pci/pci_machdep.c
462
mme = ((reg & PCI_MSI_MC_MME_MASK) >> PCI_MSI_MC_MME_SHIFT);
sys/arch/amd64/pci/pci_machdep.c
468
if (reg & PCI_MSI_MC_C64)
sys/arch/amd64/pci/pci_machdep.c
473
if (reg & PCI_MSI_MC_C64)
sys/arch/amd64/pci/pci_machdep.c
474
reg = pci_conf_read(pc, tag, off + PCI_MSI_MD64);
sys/arch/amd64/pci/pci_machdep.c
476
reg = pci_conf_read(pc, tag, off + PCI_MSI_MD32);
sys/arch/amd64/pci/pci_machdep.c
477
KASSERT(reg > 0);
sys/arch/amd64/pci/pci_machdep.c
478
idtvec = reg + vec;
sys/arch/amd64/pci/pci_machdep.c
489
pcireg_t reg;
sys/arch/amd64/pci/pci_machdep.c
493
pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0)
sys/arch/amd64/pci/pci_machdep.c
496
mmc = ((reg & PCI_MSI_MC_MMC_MASK) >> PCI_MSI_MC_MMC_SHIFT);
sys/arch/amd64/pci/pci_machdep.c
500
mme = ((reg & PCI_MSI_MC_MME_MASK) >> PCI_MSI_MC_MME_SHIFT);
sys/arch/amd64/pci/pci_machdep.c
503
reg &= ~PCI_MSI_MC_MME_MASK;
sys/arch/amd64/pci/pci_machdep.c
504
reg |= (mme << PCI_MSI_MC_MME_SHIFT);
sys/arch/amd64/pci/pci_machdep.c
505
pci_conf_write(pc, tag, off, reg);
sys/arch/amd64/pci/pci_machdep.c
515
pcireg_t reg;
sys/arch/amd64/pci/pci_machdep.c
519
pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0)
sys/arch/amd64/pci/pci_machdep.c
523
reg &= ~PCI_MSI_MC_MME_MASK;
sys/arch/amd64/pci/pci_machdep.c
524
pci_conf_write(pc, tag, off, reg);
sys/arch/amd64/pci/pci_machdep.c
538
pcireg_t reg;
sys/arch/amd64/pci/pci_machdep.c
542
pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0)
sys/arch/amd64/pci/pci_machdep.c
545
mme = ((reg & PCI_MSI_MC_MME_MASK) >> PCI_MSI_MC_MME_SHIFT);
sys/arch/amd64/pci/pci_machdep.c
583
pcireg_t reg;
sys/arch/amd64/pci/pci_machdep.c
586
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0)
sys/arch/amd64/pci/pci_machdep.c
589
KASSERT(entry <= PCI_MSIX_MC_TBLSZ(reg));
sys/arch/amd64/pci/pci_machdep.c
609
pcireg_t reg;
sys/arch/amd64/pci/pci_machdep.c
612
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0)
sys/arch/amd64/pci/pci_machdep.c
634
pcireg_t reg, addr;
sys/arch/amd64/pci/pci_machdep.c
638
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
sys/arch/amd64/pci/pci_machdep.c
641
KASSERT(entry <= PCI_MSIX_MC_TBLSZ(reg));
sys/arch/amd64/pci/pci_machdep.c
659
pci_conf_write(pc, tag, off, reg | PCI_MSIX_MC_MSIXE);
sys/arch/amd64/pci/pci_machdep.c
671
pcireg_t reg;
sys/arch/amd64/pci/pci_machdep.c
674
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0)
sys/arch/amd64/pci/pci_machdep.c
677
KASSERT(entry <= PCI_MSIX_MC_TBLSZ(reg));
sys/arch/amd64/pci/pci_machdep.c
694
pcireg_t reg;
sys/arch/amd64/pci/pci_machdep.c
699
pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0)
sys/arch/amd64/pci/pci_machdep.c
702
if (vec > PCI_MSIX_MC_TBLSZ(reg))
sys/arch/arm/arm/db_interface.c
381
db_fetch_reg(int reg, db_regs_t *db_regs)
sys/arch/arm/arm/db_interface.c
384
switch (reg) {
sys/arch/arm/arm/process_machdep.c
121
process_read_regs(struct proc *p, struct reg *regs)
sys/arch/arm/arm/process_machdep.c
155
process_write_regs(struct proc *p, struct reg *regs)
sys/arch/arm/arm/vm_machdep.c
62
int process_read_regs (struct proc *p, struct reg *regs);
sys/arch/arm/cortex/agtimer.c
285
uint32_t reg;
sys/arch/arm/cortex/agtimer.c
289
reg = agtimer_get_ctrl();
sys/arch/arm/cortex/agtimer.c
290
reg &= ~GTIMER_CNTP_CTL_IMASK;
sys/arch/arm/cortex/agtimer.c
291
reg |= GTIMER_CNTP_CTL_ENABLE;
sys/arch/arm/cortex/agtimer.c
293
agtimer_set_ctrl(reg);
sys/arch/arm/cortex/ampintc.c
318
int reg, oldreg;
sys/arch/arm/cortex/ampintc.c
326
reg = bus_space_read_1(sc->sc_iot, sc->sc_d_ioh, ICD_IPRn(i));
sys/arch/arm/cortex/ampintc.c
327
if (reg == oldreg)
sys/arch/arm/cortex/amptimer.c
219
uint32_t cycles, reg;
sys/arch/arm/cortex/amptimer.c
235
reg = bus_space_read_4(sc->sc_iot, sc->sc_pioh, PTIMER_CTRL);
sys/arch/arm/cortex/amptimer.c
236
if ((reg & (PTIMER_CTRL_ENABLE | PTIMER_CTRL_IRQEN)) !=
sys/arch/arm/include/armreg.h
46
#define CCSIDR_SETS(reg) \
sys/arch/arm/include/armreg.h
47
((((reg) & CCSIDR_SETS_MASK) >> CCSIDR_SETS_SHIFT) + 1)
sys/arch/arm/include/armreg.h
50
#define CCSIDR_WAYS(reg) \
sys/arch/arm/include/armreg.h
51
((((reg) & CCSIDR_WAYS_MASK) >> CCSIDR_WAYS_SHIFT) + 1)
sys/arch/arm/include/armreg.h
53
#define CCSIDR_LINE_SIZE(reg) (1 << (((reg) & CCSIDR_LINE_MASK) + 4))
sys/arch/arm/include/armreg.h
68
#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT)
sys/arch/arm/include/armreg.h
76
#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT)
sys/arch/arm/mainbus/mainbus.c
162
uint32_t *cell, *reg;
sys/arch/arm/mainbus/mainbus.c
175
reg = malloc(len, M_TEMP, M_WAITOK);
sys/arch/arm/mainbus/mainbus.c
176
OF_getpropintarray(node, "reg", reg, len);
sys/arch/arm/mainbus/mainbus.c
182
for (i = 0, cell = reg; i < len / line; i++) {
sys/arch/arm/mainbus/mainbus.c
199
free(reg, M_TEMP, len);
sys/arch/arm/simplebus/simplebus.c
171
uint32_t *cell, *reg;
sys/arch/arm/simplebus/simplebus.c
199
reg = malloc(len, M_TEMP, M_WAITOK);
sys/arch/arm/simplebus/simplebus.c
200
OF_getpropintarray(node, "reg", reg, len);
sys/arch/arm/simplebus/simplebus.c
206
for (i = 0, cell = reg; i < len / line; i++) {
sys/arch/arm/simplebus/simplebus.c
223
free(reg, M_TEMP, len);
sys/arch/arm64/arm64/intr.c
447
arm_intr_establish_fdt_imap(int node, int *reg, int nreg, int level,
sys/arch/arm64/arm64/intr.c
450
return arm_intr_establish_fdt_imap_cpu(node, reg, nreg, level, NULL,
sys/arch/arm64/arm64/intr.c
455
arm_intr_establish_fdt_imap_cpu(int node, int *reg, int nreg, int level,
sys/arch/arm64/arm64/intr.c
492
(reg[0] & map_mask[0]) == cell[0] &&
sys/arch/arm64/arm64/intr.c
493
(reg[1] & map_mask[1]) == cell[1] &&
sys/arch/arm64/arm64/intr.c
494
(reg[2] & map_mask[2]) == cell[2] &&
sys/arch/arm64/arm64/intr.c
495
(reg[3] & map_mask[3]) == cell[3] &&
sys/arch/arm64/arm64/machdep.c
1024
reg.addr = desc->PhysicalStart;
sys/arch/arm64/arm64/machdep.c
1025
reg.size = ptoa(desc->NumberOfPages);
sys/arch/arm64/arm64/machdep.c
1026
memreg_add(®);
sys/arch/arm64/arm64/machdep.c
1036
if (fdt_get_reg(node, i, ®))
sys/arch/arm64/arm64/machdep.c
1038
if (reg.size == 0)
sys/arch/arm64/arm64/machdep.c
1040
memreg_add(®);
sys/arch/arm64/arm64/machdep.c
1052
if (fdt_get_reg(node, 0, ®))
sys/arch/arm64/arm64/machdep.c
1054
if (reg.size == 0)
sys/arch/arm64/arm64/machdep.c
1056
memreg_remove(®);
sys/arch/arm64/arm64/machdep.c
1061
reg.addr = memstart;
sys/arch/arm64/arm64/machdep.c
1062
reg.size = memend - memstart;
sys/arch/arm64/arm64/machdep.c
1063
memreg_remove(®);
sys/arch/arm64/arm64/machdep.c
1186
memreg_add(const struct fdt_reg *reg)
sys/arch/arm64/arm64/machdep.c
1191
if (reg->addr == memreg[i].addr + memreg[i].size) {
sys/arch/arm64/arm64/machdep.c
1192
memreg[i].size += reg->size;
sys/arch/arm64/arm64/machdep.c
1195
if (reg->addr + reg->size == memreg[i].addr) {
sys/arch/arm64/arm64/machdep.c
1196
memreg[i].addr = reg->addr;
sys/arch/arm64/arm64/machdep.c
1197
memreg[i].size += reg->size;
sys/arch/arm64/arm64/machdep.c
1205
memreg[nmemreg++] = *reg;
sys/arch/arm64/arm64/machdep.c
1209
memreg_remove(const struct fdt_reg *reg)
sys/arch/arm64/arm64/machdep.c
1211
uint64_t start = reg->addr;
sys/arch/arm64/arm64/machdep.c
1212
uint64_t end = reg->addr + reg->size;
sys/arch/arm64/arm64/machdep.c
819
struct fdt_reg reg;
sys/arch/arm64/arm64/process_machdep.c
56
process_read_regs(struct proc *p, struct reg *regs)
sys/arch/arm64/arm64/process_machdep.c
87
process_write_regs(struct proc *p, struct reg *regs)
sys/arch/arm64/dev/acpipci.c
354
acpipci_conf_read(void *v, pcitag_t tag, int reg)
sys/arch/arm64/dev/acpipci.c
362
return bus_space_read_4(am->am_iot, am->am_ioh, tag | reg);
sys/arch/arm64/dev/acpipci.c
366
acpipci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
sys/arch/arm64/dev/acpipci.c
374
bus_space_write_4(am->am_iot, am->am_ioh, tag | reg, data);
sys/arch/arm64/dev/acpipci.c
768
acpipci_dummy_conf_read(void *v, pcitag_t tag, int reg)
sys/arch/arm64/dev/acpipci.c
774
acpipci_dummy_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
sys/arch/arm64/dev/agintc.c
608
int reg, oldreg;
sys/arch/arm64/dev/agintc.c
616
reg = bus_space_read_1(sc->sc_iot, sc->sc_r_ioh[hwcpu],
sys/arch/arm64/dev/agintc.c
618
if (reg == oldreg)
sys/arch/arm64/dev/agintc.c
925
uint32_t reg;
sys/arch/arm64/dev/agintc.c
931
reg = bus_space_read_4(sc->sc_iot, sc->sc_d_ioh, GICD_ICFGR(irq));
sys/arch/arm64/dev/agintc.c
932
reg &= ~GICD_ICFGR_TRIG_MASK(irq);
sys/arch/arm64/dev/agintc.c
934
reg |= GICD_ICFGR_TRIG_EDGE(irq);
sys/arch/arm64/dev/agintc.c
936
reg |= GICD_ICFGR_TRIG_LEVEL(irq);
sys/arch/arm64/dev/agintc.c
937
bus_space_write_4(sc->sc_iot, sc->sc_d_ioh, GICD_ICFGR(irq), reg);
sys/arch/arm64/dev/agtimer.c
327
uint32_t reg;
sys/arch/arm64/dev/agtimer.c
334
reg = agtimer_get_ctrl();
sys/arch/arm64/dev/agtimer.c
335
reg &= ~GTIMER_CNTV_CTL_IMASK;
sys/arch/arm64/dev/agtimer.c
336
reg |= GTIMER_CNTV_CTL_ENABLE;
sys/arch/arm64/dev/agtimer.c
338
agtimer_set_ctrl(reg);
sys/arch/arm64/dev/ampintc.c
302
int reg, oldreg;
sys/arch/arm64/dev/ampintc.c
310
reg = bus_space_read_1(sc->sc_iot, sc->sc_d_ioh, ICD_IPRn(i));
sys/arch/arm64/dev/ampintc.c
311
if (reg == oldreg)
sys/arch/arm64/dev/aplcpu.c
344
uint64_t reg;
sys/arch/arm64/dev/aplcpu.c
390
reg = bus_space_read_8(sc->sc_iot,
sys/arch/arm64/dev/aplcpu.c
392
if ((reg & DVFS_CMD_BUSY) == 0)
sys/arch/arm64/dev/aplcpu.c
396
if (reg & DVFS_CMD_BUSY)
sys/arch/arm64/dev/aplcpu.c
400
reg &= ~DVFS_CMD_PS1_MASK;
sys/arch/arm64/dev/aplcpu.c
401
reg |= (opp_level << DVFS_CMD_PS1_SHIFT);
sys/arch/arm64/dev/aplcpu.c
402
reg |= DVFS_CMD_SET;
sys/arch/arm64/dev/aplcpu.c
404
DVFS_CMD, reg);
sys/arch/arm64/dev/apldart.c
138
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/apldart.c
139
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/apldart.c
140
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/apldart.c
141
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/apldc.c
64
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/apldc.c
65
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/apldc.c
66
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/apldc.c
67
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/apldc.c
68
#define HSET4(sc, reg, bits) \
sys/arch/arm64/dev/apldc.c
69
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/arm64/dev/apldc.c
70
#define HCLR4(sc, reg, bits) \
sys/arch/arm64/dev/apldc.c
71
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/arm64/dev/apldma.c
72
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/apldma.c
73
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/apldma.c
74
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/apldma.c
75
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/apldog.c
38
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/apldog.c
39
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/apldog.c
40
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/apldog.c
41
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/apliic.c
159
uint32_t reg;
sys/arch/arm64/dev/apliic.c
163
reg = HREAD4(sc, I2C_SMSTA);
sys/arch/arm64/dev/apliic.c
164
if (reg & I2C_SMSTA_XEN)
sys/arch/arm64/dev/apliic.c
168
if (reg & I2C_SMSTA_MTN)
sys/arch/arm64/dev/apliic.c
171
HWRITE4(sc, I2C_SMSTA, reg);
sys/arch/arm64/dev/apliic.c
195
uint32_t reg;
sys/arch/arm64/dev/apliic.c
201
reg = HREAD4(sc, I2C_SMSTA);
sys/arch/arm64/dev/apliic.c
202
HWRITE4(sc, I2C_SMSTA, reg);
sys/arch/arm64/dev/apliic.c
223
reg = HREAD4(sc, I2C_MRXFIFO);
sys/arch/arm64/dev/apliic.c
224
if (reg & I2C_MRXFIFO_EMPTY)
sys/arch/arm64/dev/apliic.c
226
((uint8_t *)buf)[i] = reg & I2C_MRXFIFO_DATA_MASK;
sys/arch/arm64/dev/apliic.c
249
uint32_t reg[1];
sys/arch/arm64/dev/apliic.c
257
memset(reg, 0, sizeof(reg));
sys/arch/arm64/dev/apliic.c
258
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/arch/arm64/dev/apliic.c
270
ia.ia_addr = bemtoh32(®[0]);
sys/arch/arm64/dev/apliic.c
56
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/apliic.c
57
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/apliic.c
58
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/apliic.c
59
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/apliic.c
60
#define HSET4(sc, reg, bits) \
sys/arch/arm64/dev/apliic.c
61
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/arm64/dev/apliic.c
62
#define HCLR4(sc, reg, bits) \
sys/arch/arm64/dev/apliic.c
63
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/arm64/dev/aplintc.c
408
uint64_t reg;
sys/arch/arm64/dev/aplintc.c
413
reg = READ_SPECIALREG(APL_IPI_SR_EL1);
sys/arch/arm64/dev/aplintc.c
414
if (reg & APL_IPI_SR_EL1_PENDING) {
sys/arch/arm64/dev/aplintc.c
421
reg = READ_SPECIALREG(cntv_ctl_el0);
sys/arch/arm64/dev/aplintc.c
422
if ((reg & (CNTV_CTL_ENABLE | CNTV_CTL_IMASK | CNTV_CTL_ISTATUS)) ==
sys/arch/arm64/dev/aplintc.c
426
WRITE_SPECIALREG(cntv_ctl_el0, reg | CNTV_CTL_IMASK);
sys/arch/arm64/dev/aplintc.c
474
uint64_t reg;
sys/arch/arm64/dev/aplintc.c
483
reg = READ_SPECIALREG(cntv_ctl_el0);
sys/arch/arm64/dev/aplintc.c
484
WRITE_SPECIALREG(cntv_ctl_el0, reg & ~CNTV_CTL_IMASK);
sys/arch/arm64/dev/aplintc.c
83
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/aplintc.c
84
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/aplintc.c
85
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplintc.c
86
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplintc.c
87
#define HSET4(sc, reg, bits) \
sys/arch/arm64/dev/aplintc.c
88
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/arm64/dev/aplintc.c
89
#define HCLR4(sc, reg, bits) \
sys/arch/arm64/dev/aplintc.c
90
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/arm64/dev/aplmbox.c
42
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/aplmbox.c
43
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/aplmbox.c
44
#define HREAD8(sc, reg) \
sys/arch/arm64/dev/aplmbox.c
45
(bus_space_read_8((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/aplmbox.c
46
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplmbox.c
47
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplmbox.c
48
#define HWRITE8(sc, reg, val) \
sys/arch/arm64/dev/aplmbox.c
49
bus_space_write_8((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplmca.c
100
#define HSET4(sc, reg, bits) \
sys/arch/arm64/dev/aplmca.c
101
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/arm64/dev/aplmca.c
102
#define HCLR4(sc, reg, bits) \
sys/arch/arm64/dev/aplmca.c
103
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/arm64/dev/aplmca.c
96
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/aplmca.c
97
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/aplmca.c
98
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplmca.c
99
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplnco.c
42
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/aplnco.c
43
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/aplnco.c
44
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplnco.c
45
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplnco.c
46
#define HSET4(sc, reg, bits) \
sys/arch/arm64/dev/aplnco.c
47
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/arm64/dev/aplnco.c
48
#define HCLR4(sc, reg, bits) \
sys/arch/arm64/dev/aplnco.c
49
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/arm64/dev/aplpcie.c
101
#define LREAD4(sc, port, reg) \
sys/arch/arm64/dev/aplpcie.c
102
(bus_space_read_4((sc)->sc_iot, (sc)->sc_phy_ioh[port], (reg)))
sys/arch/arm64/dev/aplpcie.c
103
#define LWRITE4(sc, port, reg, val) \
sys/arch/arm64/dev/aplpcie.c
104
bus_space_write_4((sc)->sc_iot, (sc)->sc_phy_ioh[port], (reg), (val))
sys/arch/arm64/dev/aplpcie.c
105
#define LSET4(sc, port, reg, bits) \
sys/arch/arm64/dev/aplpcie.c
106
LWRITE4((sc), (port), (reg), LREAD4((sc), (port), (reg)) | (bits))
sys/arch/arm64/dev/aplpcie.c
107
#define LCLR4(sc, port, reg, bits) \
sys/arch/arm64/dev/aplpcie.c
108
LWRITE4((sc), (port), (reg), LREAD4((sc), (port), (reg)) & ~(bits))
sys/arch/arm64/dev/aplpcie.c
110
#define PREAD4(sc, port, reg) \
sys/arch/arm64/dev/aplpcie.c
111
(bus_space_read_4((sc)->sc_iot, (sc)->sc_port_ioh[(port)], (reg)))
sys/arch/arm64/dev/aplpcie.c
112
#define PWRITE4(sc, port, reg, val) \
sys/arch/arm64/dev/aplpcie.c
113
bus_space_write_4((sc)->sc_iot, (sc)->sc_port_ioh[(port)], (reg), (val))
sys/arch/arm64/dev/aplpcie.c
114
#define PSET4(sc, port, reg, bits) \
sys/arch/arm64/dev/aplpcie.c
115
PWRITE4((sc), (port), (reg), PREAD4((sc), (port), (reg)) | (bits))
sys/arch/arm64/dev/aplpcie.c
116
#define PCLR4(sc, port, reg, bits) \
sys/arch/arm64/dev/aplpcie.c
117
PWRITE4((sc), (port), (reg), PREAD4((sc), (port), (reg)) & ~(bits))
sys/arch/arm64/dev/aplpcie.c
443
uint32_t reg[5];
sys/arch/arm64/dev/aplpcie.c
453
if (OF_getpropintarray(node, "reg", reg, sizeof(reg)) != sizeof(reg))
sys/arch/arm64/dev/aplpcie.c
456
port = reg[0] >> 11;
sys/arch/arm64/dev/aplpcie.c
564
uint32_t reg[5];
sys/arch/arm64/dev/aplpcie.c
574
if (OF_getpropintarray(node, "reg", reg, sizeof(reg)) != sizeof(reg))
sys/arch/arm64/dev/aplpcie.c
577
port = reg[0] >> 11;
sys/arch/arm64/dev/aplpcie.c
699
uint32_t reg[5];
sys/arch/arm64/dev/aplpcie.c
707
reg, sizeof(reg)) != sizeof(reg))
sys/arch/arm64/dev/aplpcie.c
710
if (reg[0] == phys_hi)
sys/arch/arm64/dev/aplpcie.c
750
aplpcie_conf_read(void *v, pcitag_t tag, int reg)
sys/arch/arm64/dev/aplpcie.c
755
return HREAD4(sc, tag | reg);
sys/arch/arm64/dev/aplpcie.c
759
aplpcie_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
sys/arch/arm64/dev/aplpcie.c
764
HWRITE4(sc, tag | reg, data);
sys/arch/arm64/dev/aplpcie.c
771
uint32_t reg[5];
sys/arch/arm64/dev/aplpcie.c
782
if (OF_getpropintarray(node, "reg", reg,
sys/arch/arm64/dev/aplpcie.c
783
sizeof(reg)) != sizeof(reg))
sys/arch/arm64/dev/aplpcie.c
785
return reg[0] >> 11;
sys/arch/arm64/dev/aplpcie.c
794
uint32_t reg;
sys/arch/arm64/dev/aplpcie.c
798
reg = PREAD4(sc, port, PCIE_PORT_RID2SID(idx));
sys/arch/arm64/dev/aplpcie.c
801
if ((reg & PCIE_PORT_RID2SID_RID_MASK) == rid)
sys/arch/arm64/dev/aplpcie.c
805
if (reg & PCIE_PORT_RID2SID_VALID)
sys/arch/arm64/dev/aplpcie.c
809
reg = (sid << PCIE_PORT_RID2SID_SID_SHIFT) | rid |
sys/arch/arm64/dev/aplpcie.c
811
PWRITE4(sc, port, PCIE_PORT_RID2SID(idx), reg);
sys/arch/arm64/dev/aplpcie.c
814
if (PREAD4(sc, port, PCIE_PORT_RID2SID(idx)) != reg)
sys/arch/arm64/dev/aplpcie.c
826
uint32_t reg;
sys/arch/arm64/dev/aplpcie.c
830
reg = PREAD4(sc, port, PCIE_T6020_PORT_RID2SID(idx));
sys/arch/arm64/dev/aplpcie.c
833
if ((reg & PCIE_PORT_RID2SID_RID_MASK) == rid)
sys/arch/arm64/dev/aplpcie.c
837
if (reg & PCIE_PORT_RID2SID_VALID)
sys/arch/arm64/dev/aplpcie.c
841
reg = (sid << PCIE_PORT_RID2SID_SID_SHIFT) | rid |
sys/arch/arm64/dev/aplpcie.c
843
PWRITE4(sc, port, PCIE_T6020_PORT_RID2SID(idx), reg);
sys/arch/arm64/dev/aplpcie.c
846
if (PREAD4(sc, port, PCIE_T6020_PORT_RID2SID(idx)) != reg)
sys/arch/arm64/dev/aplpcie.c
87
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/aplpcie.c
88
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/aplpcie.c
89
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplpcie.c
90
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplpcie.c
92
#define RREAD4(sc, reg) \
sys/arch/arm64/dev/aplpcie.c
93
(bus_space_read_4((sc)->sc_iot, (sc)->sc_rc_ioh, (reg)))
sys/arch/arm64/dev/aplpcie.c
94
#define RWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplpcie.c
95
bus_space_write_4((sc)->sc_iot, (sc)->sc_rc_ioh, (reg), (val))
sys/arch/arm64/dev/aplpcie.c
952
uint32_t reg[4];
sys/arch/arm64/dev/aplpcie.c
956
reg[0] = bus << 16 | dev << 11 | fn << 8;
sys/arch/arm64/dev/aplpcie.c
957
reg[1] = reg[2] = 0;
sys/arch/arm64/dev/aplpcie.c
958
reg[3] = ih.ih_intrpin;
sys/arch/arm64/dev/aplpcie.c
96
#define RSET4(sc, reg, bits) \
sys/arch/arm64/dev/aplpcie.c
960
cookie = fdt_intr_establish_imap_cpu(sc->sc_node, reg,
sys/arch/arm64/dev/aplpcie.c
961
sizeof(reg), level, ci, func, arg, name);
sys/arch/arm64/dev/aplpcie.c
97
RWRITE4((sc), (reg), RREAD4((sc), (reg)) | (bits))
sys/arch/arm64/dev/aplpcie.c
98
#define RCLR4(sc, reg, bits) \
sys/arch/arm64/dev/aplpcie.c
99
RWRITE4((sc), (reg), RREAD4((sc), (reg)) & ~(bits))
sys/arch/arm64/dev/aplpinctrl.c
191
uint32_t reg;
sys/arch/arm64/dev/aplpinctrl.c
207
reg = HREAD4(sc, GPIO_PIN(pin));
sys/arch/arm64/dev/aplpinctrl.c
208
reg &= ~GPIO_PIN_FUNC_MASK;
sys/arch/arm64/dev/aplpinctrl.c
209
reg |= (func << GPIO_PIN_FUNC_SHIFT) & GPIO_PIN_FUNC_MASK;
sys/arch/arm64/dev/aplpinctrl.c
210
HWRITE4(sc, GPIO_PIN(pin), reg);
sys/arch/arm64/dev/aplpinctrl.c
222
uint32_t reg;
sys/arch/arm64/dev/aplpinctrl.c
226
reg = HREAD4(sc, GPIO_PIN(pin));
sys/arch/arm64/dev/aplpinctrl.c
227
reg &= ~GPIO_PIN_FUNC_MASK;
sys/arch/arm64/dev/aplpinctrl.c
228
reg &= ~GPIO_PIN_MODE_MASK;
sys/arch/arm64/dev/aplpinctrl.c
230
reg |= GPIO_PIN_MODE_OUTPUT;
sys/arch/arm64/dev/aplpinctrl.c
232
reg |= GPIO_PIN_MODE_INPUT;
sys/arch/arm64/dev/aplpinctrl.c
233
HWRITE4(sc, GPIO_PIN(pin), reg);
sys/arch/arm64/dev/aplpinctrl.c
242
uint32_t reg;
sys/arch/arm64/dev/aplpinctrl.c
247
reg = HREAD4(sc, GPIO_PIN(pin));
sys/arch/arm64/dev/aplpinctrl.c
248
val = !!(reg & GPIO_PIN_DATA);
sys/arch/arm64/dev/aplpinctrl.c
310
uint32_t reg;
sys/arch/arm64/dev/aplpinctrl.c
351
reg = HREAD4(sc, GPIO_PIN(pin));
sys/arch/arm64/dev/aplpinctrl.c
352
reg &= ~GPIO_PIN_DATA;
sys/arch/arm64/dev/aplpinctrl.c
353
reg &= ~GPIO_PIN_FUNC_MASK;
sys/arch/arm64/dev/aplpinctrl.c
354
reg &= ~GPIO_PIN_MODE_MASK;
sys/arch/arm64/dev/aplpinctrl.c
357
reg |= GPIO_PIN_MODE_IRQ_OFF;
sys/arch/arm64/dev/aplpinctrl.c
360
reg |= GPIO_PIN_MODE_IRQ_UP;
sys/arch/arm64/dev/aplpinctrl.c
363
reg |= GPIO_PIN_MODE_IRQ_DN;
sys/arch/arm64/dev/aplpinctrl.c
366
reg |= GPIO_PIN_MODE_IRQ_ANY;
sys/arch/arm64/dev/aplpinctrl.c
369
reg |= GPIO_PIN_MODE_IRQ_HI;
sys/arch/arm64/dev/aplpinctrl.c
372
reg |= GPIO_PIN_MODE_IRQ_LO;
sys/arch/arm64/dev/aplpinctrl.c
375
reg |= GPIO_PIN_INPUT_ENABLE;
sys/arch/arm64/dev/aplpinctrl.c
376
reg &= ~GPIO_PIN_GROUP_MASK;
sys/arch/arm64/dev/aplpinctrl.c
377
HWRITE4(sc, GPIO_PIN(pin), reg);
sys/arch/arm64/dev/aplpinctrl.c
387
uint32_t reg;
sys/arch/arm64/dev/aplpinctrl.c
397
reg = HREAD4(sc, GPIO_PIN(ih->ih_irq));
sys/arch/arm64/dev/aplpinctrl.c
398
reg &= ~GPIO_PIN_MODE_MASK;
sys/arch/arm64/dev/aplpinctrl.c
399
reg |= GPIO_PIN_MODE_IRQ_OFF;
sys/arch/arm64/dev/aplpinctrl.c
400
HWRITE4(sc, GPIO_PIN(ih->ih_irq), reg);
sys/arch/arm64/dev/aplpinctrl.c
413
uint32_t reg;
sys/arch/arm64/dev/aplpinctrl.c
417
reg = HREAD4(sc, GPIO_PIN(ih->ih_irq));
sys/arch/arm64/dev/aplpinctrl.c
418
reg &= ~GPIO_PIN_MODE_MASK;
sys/arch/arm64/dev/aplpinctrl.c
421
reg |= GPIO_PIN_MODE_IRQ_OFF;
sys/arch/arm64/dev/aplpinctrl.c
424
reg |= GPIO_PIN_MODE_IRQ_UP;
sys/arch/arm64/dev/aplpinctrl.c
427
reg |= GPIO_PIN_MODE_IRQ_DN;
sys/arch/arm64/dev/aplpinctrl.c
430
reg |= GPIO_PIN_MODE_IRQ_ANY;
sys/arch/arm64/dev/aplpinctrl.c
433
reg |= GPIO_PIN_MODE_IRQ_HI;
sys/arch/arm64/dev/aplpinctrl.c
436
reg |= GPIO_PIN_MODE_IRQ_LO;
sys/arch/arm64/dev/aplpinctrl.c
439
HWRITE4(sc, GPIO_PIN(ih->ih_irq), reg);
sys/arch/arm64/dev/aplpinctrl.c
448
uint32_t reg;
sys/arch/arm64/dev/aplpinctrl.c
452
reg = HREAD4(sc, GPIO_PIN(ih->ih_irq));
sys/arch/arm64/dev/aplpinctrl.c
453
reg &= ~GPIO_PIN_MODE_MASK;
sys/arch/arm64/dev/aplpinctrl.c
454
reg |= GPIO_PIN_MODE_IRQ_OFF;
sys/arch/arm64/dev/aplpinctrl.c
455
HWRITE4(sc, GPIO_PIN(ih->ih_irq), reg);
sys/arch/arm64/dev/aplpinctrl.c
54
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/aplpinctrl.c
55
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/aplpinctrl.c
56
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplpinctrl.c
57
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplpinctrl.c
58
#define HSET4(sc, reg, bits) \
sys/arch/arm64/dev/aplpinctrl.c
59
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/arm64/dev/aplpinctrl.c
60
#define HCLR4(sc, reg, bits) \
sys/arch/arm64/dev/aplpinctrl.c
61
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/arm64/dev/aplpmgr.c
130
if (OF_getpropintarray(node, "reg", reg,
sys/arch/arm64/dev/aplpmgr.c
131
sizeof(reg)) != sizeof(reg)) {
sys/arch/arm64/dev/aplpmgr.c
138
ps->ps_offset = reg[0];
sys/arch/arm64/dev/aplpmgr.c
43
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/aplpmgr.c
44
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/aplpmgr.c
45
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplpmgr.c
46
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplpmgr.c
99
uint32_t reg[2];
sys/arch/arm64/dev/aplpmu.c
136
uint32_t reg[2] = { 0x0, 0x10000 };
sys/arch/arm64/dev/aplpmu.c
149
if (OF_getpropintarray(node, "reg", reg,
sys/arch/arm64/dev/aplpmu.c
150
sizeof(reg)) != sizeof(reg))
sys/arch/arm64/dev/aplpmu.c
156
an->an_base = reg[0];
sys/arch/arm64/dev/aplpmu.c
157
an->an_size = reg[1];
sys/arch/arm64/dev/aplpwm.c
40
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/aplpwm.c
41
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/aplpwm.c
42
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplpwm.c
43
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplrtk.c
35
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/aplrtk.c
36
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/aplrtk.c
37
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplrtk.c
38
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplsart.c
48
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/aplsart.c
49
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/aplsart.c
50
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplsart.c
51
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplspi.c
100
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/arm64/dev/aplspi.c
101
#define HCLR4(sc, reg, bits) \
sys/arch/arm64/dev/aplspi.c
102
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/arm64/dev/aplspi.c
290
uint32_t reg[1];
sys/arch/arm64/dev/aplspi.c
296
memset(reg, 0, sizeof(reg));
sys/arch/arm64/dev/aplspi.c
303
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/arch/arm64/dev/aplspi.c
95
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/aplspi.c
96
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/aplspi.c
97
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplspi.c
98
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplspi.c
99
#define HSET4(sc, reg, bits) \
sys/arch/arm64/dev/aplspmi.c
108
if (OF_getpropintarray(node, "reg", reg,
sys/arch/arm64/dev/aplspmi.c
109
sizeof(reg)) != sizeof(reg))
sys/arch/arm64/dev/aplspmi.c
120
sa.sa_sid = reg[0];
sys/arch/arm64/dev/aplspmi.c
41
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/aplspmi.c
42
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/aplspmi.c
43
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/aplspmi.c
44
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/aplspmi.c
86
uint32_t reg[2];
sys/arch/arm64/dev/bcm2712_mip.c
45
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/bcm2712_mip.c
46
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/bcm2712_mip.c
47
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/bcm2712_mip.c
48
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/bcm2712_mip.c
49
#define HSET4(sc, reg, bits) \
sys/arch/arm64/dev/bcm2712_mip.c
50
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/arm64/dev/bcm2712_mip.c
51
#define HCLR4(sc, reg, bits) \
sys/arch/arm64/dev/bcm2712_mip.c
52
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/arm64/dev/bcm2836_intr.c
157
uint32_t phandle, reg[2];
sys/arch/arm64/dev/bcm2836_intr.c
184
if (OF_getpropintarray(node, "reg", reg, sizeof(reg)) != sizeof(reg))
sys/arch/arm64/dev/bcm2836_intr.c
187
if (bus_space_map(sc->sc_iot, reg[0], reg[1], 0, &sc->sc_lioh))
sys/arch/arm64/dev/efi_machdep.c
141
struct fdt_reg reg = { .addr = efi_smbios_table };
sys/arch/arm64/dev/efi_machdep.c
146
fa.fa_reg = ®
sys/arch/arm64/dev/mainbus.c
208
uint32_t *cell, *reg;
sys/arch/arm64/dev/mainbus.c
231
reg = malloc(len, M_TEMP, M_WAITOK);
sys/arch/arm64/dev/mainbus.c
232
OF_getpropintarray(node, "reg", reg, len);
sys/arch/arm64/dev/mainbus.c
238
for (i = 0, cell = reg; i < len / line; i++) {
sys/arch/arm64/dev/mainbus.c
255
free(reg, M_TEMP, len);
sys/arch/arm64/dev/pci_machdep.c
107
pcireg_t reg;
sys/arch/arm64/dev/pci_machdep.c
110
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0)
sys/arch/arm64/dev/pci_machdep.c
113
tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
sys/arch/arm64/dev/pci_machdep.c
122
pcireg_t reg;
sys/arch/arm64/dev/pci_machdep.c
126
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
sys/arch/arm64/dev/pci_machdep.c
129
KASSERT(vec <= PCI_MSIX_MC_TBLSZ(reg));
sys/arch/arm64/dev/pci_machdep.c
145
pci_conf_write(pc, tag, off, reg | PCI_MSIX_MC_MSIXE);
sys/arch/arm64/dev/pci_machdep.c
173
pcireg_t reg;
sys/arch/arm64/dev/pci_machdep.c
177
pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0)
sys/arch/arm64/dev/pci_machdep.c
180
mme = ((reg & PCI_MSI_MC_MME_MASK) >> PCI_MSI_MC_MME_SHIFT);
sys/arch/arm64/dev/pci_machdep.c
199
pcireg_t reg, table, type;
sys/arch/arm64/dev/pci_machdep.c
203
pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
sys/arch/arm64/dev/pci_machdep.c
206
if (vec > PCI_MSIX_MC_TBLSZ(reg))
sys/arch/arm64/dev/pci_machdep.c
32
pcireg_t reg;
sys/arch/arm64/dev/pci_machdep.c
36
pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0)
sys/arch/arm64/dev/pci_machdep.c
39
mmc = ((reg & PCI_MSI_MC_MMC_MASK) >> PCI_MSI_MC_MMC_SHIFT);
sys/arch/arm64/dev/pci_machdep.c
43
mme = ((reg & PCI_MSI_MC_MME_MASK) >> PCI_MSI_MC_MME_SHIFT);
sys/arch/arm64/dev/pci_machdep.c
46
reg &= ~PCI_MSI_MC_MME_MASK;
sys/arch/arm64/dev/pci_machdep.c
47
reg |= (mme << PCI_MSI_MC_MME_SHIFT);
sys/arch/arm64/dev/pci_machdep.c
48
pci_conf_write(pc, tag, off, reg);
sys/arch/arm64/dev/pci_machdep.c
57
pcireg_t reg;
sys/arch/arm64/dev/pci_machdep.c
60
if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0)
sys/arch/arm64/dev/pci_machdep.c
63
mme = ((reg & PCI_MSI_MC_MME_MASK) >> PCI_MSI_MC_MME_SHIFT);
sys/arch/arm64/dev/pci_machdep.c
66
if (reg & PCI_MSI_MC_C64) {
sys/arch/arm64/dev/pci_machdep.c
74
pci_conf_write(pc, tag, off, reg | PCI_MSI_MC_MSIE);
sys/arch/arm64/dev/pci_machdep.c
82
pcireg_t reg, table, type;
sys/arch/arm64/dev/pci_machdep.c
86
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
sys/arch/arm64/dev/pci_machdep.c
92
tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
sys/arch/arm64/dev/rpiclock.c
55
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/rpiclock.c
56
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/rpiclock.c
57
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/rpiclock.c
58
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/rpiclock.c
59
#define HSET4(sc, reg, bits) \
sys/arch/arm64/dev/rpiclock.c
60
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/arm64/dev/rpiclock.c
61
#define HCLR4(sc, reg, bits) \
sys/arch/arm64/dev/rpiclock.c
62
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/arm64/dev/rpigpio.c
391
uint32_t reg;
sys/arch/arm64/dev/rpigpio.c
399
reg = bus_space_read_4(sc->sc_iot, sc->sc_rio_ioh, bank->rio + RIO_IN);
sys/arch/arm64/dev/rpigpio.c
400
reg &= (1 << pin);
sys/arch/arm64/dev/rpigpio.c
401
val = (reg >> pin) & 1;
sys/arch/arm64/dev/rpigpio.c
414
uint32_t reg;
sys/arch/arm64/dev/rpigpio.c
421
reg = bus_space_read_4(sc->sc_iot, sc->sc_rio_ioh, bank->rio + RIO_OUT);
sys/arch/arm64/dev/rpigpio.c
425
reg |= (1 << pin);
sys/arch/arm64/dev/rpigpio.c
427
reg &= ~(1 << pin);
sys/arch/arm64/dev/rpigpio.c
428
bus_space_write_4(sc->sc_iot, sc->sc_rio_ioh, bank->rio + RIO_OUT, reg);
sys/arch/arm64/dev/rpipwm.c
32
#define HREAD4(sc, reg) \
sys/arch/arm64/dev/rpipwm.c
33
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/arm64/dev/rpipwm.c
34
#define HWRITE4(sc, reg, val) \
sys/arch/arm64/dev/rpipwm.c
35
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/arm64/dev/rpipwm.c
36
#define HSET4(sc, reg, bits) \
sys/arch/arm64/dev/rpipwm.c
37
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/arm64/dev/rpipwm.c
38
#define HCLR4(sc, reg, bits) \
sys/arch/arm64/dev/rpipwm.c
39
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/arm64/dev/rtkit.c
329
uint64_t reg[31];
sys/arch/arm64/dev/rtkit.c
418
for (i = 0; i < nitems(rg8.reg); i++)
sys/arch/arm64/dev/rtkit.c
419
printf("RTKit Crg8: reg[%d] %016llx\n", i, rg8.reg[i]);
sys/arch/arm64/dev/simplebus.c
188
uint32_t *cell, *reg;
sys/arch/arm64/dev/simplebus.c
216
reg = malloc(len, M_TEMP, M_WAITOK);
sys/arch/arm64/dev/simplebus.c
217
OF_getpropintarray(node, "reg", reg, len);
sys/arch/arm64/dev/simplebus.c
223
for (i = 0, cell = reg; i < len / line; i++) {
sys/arch/arm64/dev/simplebus.c
240
free(reg, M_TEMP, len);
sys/arch/arm64/dev/smmu.c
156
uint32_t reg;
sys/arch/arm64/dev/smmu.c
1587
uint32_t reg;
sys/arch/arm64/dev/smmu.c
1593
reg = smmu_v3_read_4(sc, SMMU_V3_IDR0);
sys/arch/arm64/dev/smmu.c
1594
if (!(reg & SMMU_V3_TTF_AA64)) {
sys/arch/arm64/dev/smmu.c
1598
if (reg & SMMU_V3_IDR0_S1P)
sys/arch/arm64/dev/smmu.c
1600
if (reg & SMMU_V3_IDR0_S2P)
sys/arch/arm64/dev/smmu.c
1602
if (reg & SMMU_V3_IDR0_ASID16)
sys/arch/arm64/dev/smmu.c
1604
if (reg & SMMU_V3_IDR0_PRI)
sys/arch/arm64/dev/smmu.c
1606
if (reg & SMMU_V3_IDR0_VMID16)
sys/arch/arm64/dev/smmu.c
1608
if (reg & SMMU_V3_IDR0_CD2L)
sys/arch/arm64/dev/smmu.c
1610
if (SMMU_V3_IDR0_ST_LEVEL(reg) == SMMU_V3_IDR0_ST_LEVEL_2)
sys/arch/arm64/dev/smmu.c
1613
reg = smmu_v3_read_4(sc, SMMU_V3_IDR1);
sys/arch/arm64/dev/smmu.c
1614
sc->v3.sc_cmdq.sq_size_log2 = SMMU_V3_IDR1_CMDQS(reg);
sys/arch/arm64/dev/smmu.c
1615
sc->v3.sc_eventq.sq_size_log2 = SMMU_V3_IDR1_EVENTQS(reg);
sys/arch/arm64/dev/smmu.c
1616
sc->v3.sc_priq.sq_size_log2 = SMMU_V3_IDR1_PRIQS(reg);
sys/arch/arm64/dev/smmu.c
1617
sc->v3.sc_sidsize = SMMU_V3_IDR1_SIDSIZE(reg);
sys/arch/arm64/dev/smmu.c
162
reg = smmu_gr0_read_4(sc, SMMU_IDR0);
sys/arch/arm64/dev/smmu.c
1621
reg = smmu_v3_read_4(sc, SMMU_V3_IDR5);
sys/arch/arm64/dev/smmu.c
1622
switch (SMMU_V3_IDR5_OAS(reg)) {
sys/arch/arm64/dev/smmu.c
163
if (reg & SMMU_IDR0_S1TS)
sys/arch/arm64/dev/smmu.c
1648
if (reg & SMMU_V3_IDR5_VAX)
sys/arch/arm64/dev/smmu.c
1655
reg = smmu_v3_read_4(sc, SMMU_V3_IDR3);
sys/arch/arm64/dev/smmu.c
1656
if ((reg & SMMU_V3_IDR3_STT) == 0) {
sys/arch/arm64/dev/smmu.c
1688
reg = smmu_v3_read_4(sc, SMMU_V3_GBPA);
sys/arch/arm64/dev/smmu.c
1689
reg |= SMMU_V3_GBPA_ABORT;
sys/arch/arm64/dev/smmu.c
1690
smmu_v3_write_4(sc, SMMU_V3_GBPA, reg | SMMU_V3_GBPA_UPDATE);
sys/arch/arm64/dev/smmu.c
172
if (reg & SMMU_IDR0_S2TS)
sys/arch/arm64/dev/smmu.c
176
if (reg & SMMU_IDR0_EXIDS)
sys/arch/arm64/dev/smmu.c
179
sc->sc_num_streams = 1 << SMMU_IDR0_NUMSIDB(reg);
sys/arch/arm64/dev/smmu.c
183
if (reg & SMMU_IDR0_SMS) {
sys/arch/arm64/dev/smmu.c
184
sc->sc_num_streams = SMMU_IDR0_NUMSMRG(reg);
sys/arch/arm64/dev/smmu.c
191
reg = smmu_gr0_read_4(sc, SMMU_IDR1);
sys/arch/arm64/dev/smmu.c
193
if (reg & SMMU_IDR1_PAGESIZE_64K)
sys/arch/arm64/dev/smmu.c
195
sc->sc_numpage = 1 << (SMMU_IDR1_NUMPAGENDXB(reg) + 1);
sys/arch/arm64/dev/smmu.c
198
sc->sc_num_context_banks = SMMU_IDR1_NUMCB(reg);
sys/arch/arm64/dev/smmu.c
199
sc->sc_num_s2_context_banks = SMMU_IDR1_NUMS2CB(reg);
sys/arch/arm64/dev/smmu.c
205
reg = smmu_gr0_read_4(sc, SMMU_IDR2);
sys/arch/arm64/dev/smmu.c
206
if (reg & SMMU_IDR2_VMID16S)
sys/arch/arm64/dev/smmu.c
209
switch (SMMU_IDR2_IAS(reg)) {
sys/arch/arm64/dev/smmu.c
230
switch (SMMU_IDR2_OAS(reg)) {
sys/arch/arm64/dev/smmu.c
251
switch (SMMU_IDR2_UBS(reg)) {
sys/arch/arm64/dev/smmu.c
305
reg = smmu_gr0_read_4(sc, SMMU_SMR(i));
sys/arch/arm64/dev/smmu.c
308
sc->sc_smr[i]->ss_id = (reg >> SMMU_SMR_ID_SHIFT) &
sys/arch/arm64/dev/smmu.c
310
sc->sc_smr[i]->ss_mask = (reg >> SMMU_SMR_MASK_SHIFT) &
sys/arch/arm64/dev/smmu.c
346
reg = smmu_gr0_read_4(sc, SMMU_SACR);
sys/arch/arm64/dev/smmu.c
348
reg &= ~SMMU_SACR_MMU500_CACHE_LOCK;
sys/arch/arm64/dev/smmu.c
349
reg |= SMMU_SACR_MMU500_SMTNMB_TLBEN |
sys/arch/arm64/dev/smmu.c
351
smmu_gr0_write_4(sc, SMMU_SACR, reg);
sys/arch/arm64/dev/smmu.c
353
reg = smmu_cb_read_4(sc, i, SMMU_CB_ACTLR);
sys/arch/arm64/dev/smmu.c
354
reg &= ~SMMU_CB_ACTLR_CPRE;
sys/arch/arm64/dev/smmu.c
355
smmu_cb_write_4(sc, i, SMMU_CB_ACTLR, reg);
sys/arch/arm64/dev/smmu.c
360
reg = smmu_gr0_read_4(sc, SMMU_SCR0);
sys/arch/arm64/dev/smmu.c
361
reg &= ~(SMMU_SCR0_CLIENTPD |
sys/arch/arm64/dev/smmu.c
365
reg |= SMMU_SCR0_USFCFG;
sys/arch/arm64/dev/smmu.c
368
reg &= ~SMMU_SCR0_USFCFG;
sys/arch/arm64/dev/smmu.c
370
reg |= SMMU_SCR0_GFRE | SMMU_SCR0_GFIE |
sys/arch/arm64/dev/smmu.c
374
reg |= SMMU_SCR0_EXIDENABLE;
sys/arch/arm64/dev/smmu.c
376
reg |= SMMU_SCR0_VMID16EN;
sys/arch/arm64/dev/smmu.c
379
smmu_gr0_write_4(sc, SMMU_SCR0, reg);
sys/arch/arm64/dev/smmu.c
391
uint32_t reg;
sys/arch/arm64/dev/smmu.c
393
reg = smmu_gr0_read_4(sc, SMMU_SGFSR);
sys/arch/arm64/dev/smmu.c
394
if (reg == 0)
sys/arch/arm64/dev/smmu.c
398
"SGFSYNR2 0x%08x\n", sc->sc_dev.dv_xname, reg,
sys/arch/arm64/dev/smmu.c
403
smmu_gr0_write_4(sc, SMMU_SGFSR, reg);
sys/arch/arm64/dev/smmu.c
413
uint32_t reg;
sys/arch/arm64/dev/smmu.c
415
reg = smmu_cb_read_4(sc, cbi->cbi_idx, SMMU_CB_FSR);
sys/arch/arm64/dev/smmu.c
416
if ((reg & SMMU_CB_FSR_MASK) == 0)
sys/arch/arm64/dev/smmu.c
420
"CBFRSYNRA 0x%08x\n", sc->sc_dev.dv_xname, reg,
sys/arch/arm64/dev/smmu.c
425
smmu_cb_write_4(sc, cbi->cbi_idx, SMMU_CB_FSR, reg);
sys/arch/arm64/dev/smmu.c
520
uint64_t reg;
sys/arch/arm64/dev/smmu.c
527
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, base + off + 4);
sys/arch/arm64/dev/smmu.c
528
reg <<= 32;
sys/arch/arm64/dev/smmu.c
529
reg |= bus_space_read_4(sc->sc_iot, sc->sc_ioh, base + off + 0);
sys/arch/arm64/dev/smmu.c
530
return reg;
sys/arch/arm64/dev/smmu.c
628
uint32_t iovabits, reg;
sys/arch/arm64/dev/smmu.c
691
reg = SMMU_CBA2R_VA64;
sys/arch/arm64/dev/smmu.c
693
reg |= (dom->sd_cb_idx + 1) << SMMU_CBA2R_VMID16_SHIFT;
sys/arch/arm64/dev/smmu.c
694
smmu_gr1_write_4(sc, SMMU_CBA2R(dom->sd_cb_idx), reg);
sys/arch/arm64/dev/smmu.c
697
reg = SMMU_CBAR_TYPE_S1_TRANS_S2_BYPASS |
sys/arch/arm64/dev/smmu.c
700
reg = SMMU_CBAR_TYPE_S2_TRANS;
sys/arch/arm64/dev/smmu.c
702
reg |= (dom->sd_cb_idx + 1) << SMMU_CBAR_VMID_SHIFT;
sys/arch/arm64/dev/smmu.c
704
smmu_gr1_write_4(sc, SMMU_CBAR(dom->sd_cb_idx), reg);
sys/arch/arm64/dev/smmu.c
707
reg = SMMU_CB_TCR2_AS | SMMU_CB_TCR2_SEP_UPSTREAM;
sys/arch/arm64/dev/smmu.c
710
reg |= SMMU_CB_TCR2_PASIZE_32BIT;
sys/arch/arm64/dev/smmu.c
713
reg |= SMMU_CB_TCR2_PASIZE_36BIT;
sys/arch/arm64/dev/smmu.c
716
reg |= SMMU_CB_TCR2_PASIZE_40BIT;
sys/arch/arm64/dev/smmu.c
719
reg |= SMMU_CB_TCR2_PASIZE_42BIT;
sys/arch/arm64/dev/smmu.c
722
reg |= SMMU_CB_TCR2_PASIZE_44BIT;
sys/arch/arm64/dev/smmu.c
725
reg |= SMMU_CB_TCR2_PASIZE_48BIT;
sys/arch/arm64/dev/smmu.c
728
smmu_cb_write_4(sc, dom->sd_cb_idx, SMMU_CB_TCR2, reg);
sys/arch/arm64/dev/smmu.c
744
reg = SMMU_CB_TCR_TG0_4KB | SMMU_CB_TCR_T0SZ(64 - iovabits);
sys/arch/arm64/dev/smmu.c
746
reg |= SMMU_CB_TCR_EPD1;
sys/arch/arm64/dev/smmu.c
749
reg |= SMMU_CB_TCR_S2_SL0_4KB_L0;
sys/arch/arm64/dev/smmu.c
751
reg |= SMMU_CB_TCR_S2_SL0_4KB_L1;
sys/arch/arm64/dev/smmu.c
754
reg |= SMMU_CB_TCR_S2_PASIZE_32BIT;
sys/arch/arm64/dev/smmu.c
757
reg |= SMMU_CB_TCR_S2_PASIZE_36BIT;
sys/arch/arm64/dev/smmu.c
760
reg |= SMMU_CB_TCR_S2_PASIZE_40BIT;
sys/arch/arm64/dev/smmu.c
763
reg |= SMMU_CB_TCR_S2_PASIZE_42BIT;
sys/arch/arm64/dev/smmu.c
766
reg |= SMMU_CB_TCR_S2_PASIZE_44BIT;
sys/arch/arm64/dev/smmu.c
769
reg |= SMMU_CB_TCR_S2_PASIZE_48BIT;
sys/arch/arm64/dev/smmu.c
774
reg |= SMMU_CB_TCR_IRGN0_WBWA | SMMU_CB_TCR_ORGN0_WBWA |
sys/arch/arm64/dev/smmu.c
777
reg |= SMMU_CB_TCR_IRGN0_NC | SMMU_CB_TCR_ORGN0_NC |
sys/arch/arm64/dev/smmu.c
779
smmu_cb_write_4(sc, dom->sd_cb_idx, SMMU_CB_TCR, reg);
sys/arch/arm64/dev/smmu.c
814
reg = SMMU_CB_SCTLR_M | SMMU_CB_SCTLR_TRE | SMMU_CB_SCTLR_AFE |
sys/arch/arm64/dev/smmu.c
817
reg |= SMMU_CB_SCTLR_ASIDPNE;
sys/arch/arm64/dev/smmu.c
818
smmu_cb_write_4(sc, dom->sd_cb_idx, SMMU_CB_SCTLR, reg);
sys/arch/arm64/dev/smmu.c
821
reg = SMMU_S2CR_TYPE_TRANS | dom->sd_cb_idx;
sys/arch/arm64/dev/smmu.c
823
reg |= SMMU_S2CR_EXIDVALID;
sys/arch/arm64/dev/smmu.c
824
smmu_gr0_write_4(sc, SMMU_S2CR(dom->sd_smr_idx), reg);
sys/arch/arm64/dev/smmu.c
828
reg = sc->sc_smr[dom->sd_smr_idx]->ss_id << SMMU_SMR_ID_SHIFT |
sys/arch/arm64/dev/smmu.c
831
reg |= SMMU_SMR_VALID;
sys/arch/arm64/dev/smmu.c
832
smmu_gr0_write_4(sc, SMMU_SMR(dom->sd_smr_idx), reg);
sys/arch/arm64/include/armreg.h
112
#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT)
sys/arch/arm64/include/armreg.h
120
#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT)
sys/arch/arm64/include/armreg.h
133
#define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT)
sys/arch/arm64/include/armreg.h
229
#define ICC_CTLR_EL1_PRIBITS(reg) \
sys/arch/arm64/include/armreg.h
230
(((reg) & ICC_CTLR_EL1_PRIBITS_MASK) >> ICC_CTLR_EL1_PRIBITS_SHIFT)
sys/arch/arm64/include/armreg.h
39
#define READ_SPECIALREG(reg) \
sys/arch/arm64/include/armreg.h
41
__asm volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \
sys/arch/arm64/include/armreg.h
44
#define WRITE_SPECIALREG(reg, val) \
sys/arch/arm64/include/armreg.h
45
__asm volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val))
sys/arch/arm64/include/armreg.h
50
#define CCSIDR_SETS(reg) \
sys/arch/arm64/include/armreg.h
51
((((reg) & CCSIDR_SETS_MASK) >> CCSIDR_SETS_SHIFT) + 1)
sys/arch/arm64/include/armreg.h
54
#define CCSIDR_WAYS(reg) \
sys/arch/arm64/include/armreg.h
55
((((reg) & CCSIDR_WAYS_MASK) >> CCSIDR_WAYS_SHIFT) + 1)
sys/arch/arm64/include/armreg.h
57
#define CCSIDR_LINE_SIZE(reg) (1 << (((reg) & CCSIDR_LINE_MASK) + 4))
sys/arch/arm64/include/armreg.h
61
#define CCSIDR_CCIDX_SETS(reg) \
sys/arch/arm64/include/armreg.h
62
((((reg) & CCSIDR_CCIDX_SETS_MASK) >> CCSIDR_CCIDX_SETS_SHIFT) + 1)
sys/arch/arm64/include/armreg.h
65
#define CCSIDR_CCIDX_WAYS(reg) \
sys/arch/arm64/include/armreg.h
66
((((reg) & CCSIDR_CCIDX_WAYS_MASK) >> CCSIDR_CCIDX_WAYS_SHIFT) + 1)
sys/arch/arm64/include/armreg.h
68
#define CCSIDR_CCIDX_LINE_SIZE(reg) \
sys/arch/arm64/include/armreg.h
69
(1 << (((reg) & CCSIDR_CCIDX_LINE_MASK) + 4))
sys/arch/arm64/include/asm.h
100
# define RETGUARD_PUSH(reg) \
sys/arch/arm64/include/asm.h
101
str reg, [sp, #-16]!
sys/arch/arm64/include/asm.h
103
# define RETGUARD_POP(reg) \
sys/arch/arm64/include/asm.h
104
ldr reg, [sp, #16]!
sys/arch/arm64/include/asm.h
119
# define RETGUARD_CALC_COOKIE(reg)
sys/arch/arm64/include/asm.h
120
# define RETGUARD_LOAD_RANDOM(x, reg)
sys/arch/arm64/include/asm.h
121
# define RETGUARD_SETUP(x, reg)
sys/arch/arm64/include/asm.h
122
# define RETGUARD_CHECK(x, reg)
sys/arch/arm64/include/asm.h
123
# define RETGUARD_PUSH(reg)
sys/arch/arm64/include/asm.h
124
# define RETGUARD_POP(reg)
sys/arch/arm64/include/asm.h
80
# define RETGUARD_CALC_COOKIE(reg) \
sys/arch/arm64/include/asm.h
81
eor reg, reg, x30
sys/arch/arm64/include/asm.h
83
# define RETGUARD_LOAD_RANDOM(x, reg) \
sys/arch/arm64/include/asm.h
84
adrp reg, __CONCAT(__retguard_, x); \
sys/arch/arm64/include/asm.h
85
ldr reg, [reg, :lo12:__CONCAT(__retguard_, x)]
sys/arch/arm64/include/asm.h
87
# define RETGUARD_SETUP(x, reg) \
sys/arch/arm64/include/asm.h
89
RETGUARD_LOAD_RANDOM(x, reg); \
sys/arch/arm64/include/asm.h
90
RETGUARD_CALC_COOKIE(reg)
sys/arch/arm64/include/asm.h
92
# define RETGUARD_CHECK(x, reg) \
sys/arch/arm64/include/asm.h
93
RETGUARD_CALC_COOKIE(reg); \
sys/arch/arm64/include/asm.h
95
subs reg, reg, x9; \
sys/arch/arm64/include/asm.h
96
cbz reg, 66f; \
sys/arch/arm64/stand/efiboot/efiacpi.c
440
uint64_t reg;
sys/arch/arm64/stand/efiboot/efiacpi.c
454
reg = htobe64(mpidr);
sys/arch/arm64/stand/efiboot/efiacpi.c
461
fdt_node_add_property(child, "reg", ®, sizeof(reg));
sys/arch/arm64/stand/efiboot/efiacpi.c
506
uint64_t reg[2];
sys/arch/arm64/stand/efiboot/efiacpi.c
510
reg[0] = htobe64(msi->base_address);
sys/arch/arm64/stand/efiboot/efiacpi.c
511
reg[1] = htobe64(0x1000);
sys/arch/arm64/stand/efiboot/efiacpi.c
518
fdt_node_add_property(child, "reg", reg, sizeof(reg));
sys/arch/arm64/stand/efiboot/efiacpi.c
545
uint64_t reg[2];
sys/arch/arm64/stand/efiboot/efiacpi.c
550
reg[0] = htobe64(its->base_address);
sys/arch/arm64/stand/efiboot/efiacpi.c
551
reg[1] = htobe64(0x20000);
sys/arch/arm64/stand/efiboot/efiacpi.c
559
fdt_node_add_property(child, "reg", reg, sizeof(reg));
sys/arch/arm64/stand/efiboot/efiacpi.c
571
uint64_t reg[4];
sys/arch/arm64/stand/efiboot/efiacpi.c
622
reg[0] = htobe64(gicd_base);
sys/arch/arm64/stand/efiboot/efiacpi.c
623
reg[1] = htobe64(0x1000);
sys/arch/arm64/stand/efiboot/efiacpi.c
624
reg[2] = htobe64(gicc_base);
sys/arch/arm64/stand/efiboot/efiacpi.c
625
reg[3] = htobe64(0x100);
sys/arch/arm64/stand/efiboot/efiacpi.c
631
reg[0] = htobe64(gicd_base);
sys/arch/arm64/stand/efiboot/efiacpi.c
632
reg[1] = htobe64(0x10000);
sys/arch/arm64/stand/efiboot/efiacpi.c
633
reg[2] = htobe64(gicr_base);
sys/arch/arm64/stand/efiboot/efiacpi.c
634
reg[3] = htobe64(gicr_size + gicr_stride);
sys/arch/arm64/stand/efiboot/efiacpi.c
643
fdt_node_set_property(node, "reg", reg, sizeof(reg));
sys/arch/arm64/stand/efiboot/efiacpi.c
658
uint64_t reg[2], reg_shift, reg_io_width;
sys/arch/arm64/stand/efiboot/efiacpi.c
701
reg[0] = htobe64(base_address->address);
sys/arch/arm64/stand/efiboot/efiacpi.c
702
reg[1] = htobe64(address_size);
sys/arch/arm64/stand/efiboot/efiacpi.c
703
fdt_node_set_property(node, "reg", reg, sizeof(reg));
sys/arch/arm64/stand/efiboot/efiacpi.c
772
uint64_t reg[2];
sys/arch/arm64/stand/efiboot/efiacpi.c
821
reg[0] = htobe64((uint64_t)rsdp);
sys/arch/arm64/stand/efiboot/efiacpi.c
822
reg[1] = htobe64(rsdp->rsdp_length);
sys/arch/arm64/stand/efiboot/efiacpi.c
826
fdt_node_set_property(node, "reg", reg, sizeof(reg));
sys/arch/arm64/stand/efiboot/efiboot.c
401
uint32_t reg[4];
sys/arch/arm64/stand/efiboot/efiboot.c
490
reg[0] = htobe32(base);
sys/arch/arm64/stand/efiboot/efiboot.c
492
reg[1] = reg[0];
sys/arch/arm64/stand/efiboot/efiboot.c
493
reg[0] = htobe32(base >> 32);
sys/arch/arm64/stand/efiboot/efiboot.c
496
reg[acells] = htobe32(size);
sys/arch/arm64/stand/efiboot/efiboot.c
498
reg[acells + 1] = reg[acells];
sys/arch/arm64/stand/efiboot/efiboot.c
499
reg[acells] = htobe32(size >> 32);
sys/arch/arm64/stand/efiboot/efiboot.c
509
fdt_node_add_property(child, "reg", reg, (acells + scells) * 4);
sys/arch/armv7/armv7/armv7_machdep.c
369
struct fdt_reg reg;
sys/arch/armv7/armv7/armv7_machdep.c
795
if (fdt_get_reg(node, i, ®))
sys/arch/armv7/armv7/armv7_machdep.c
797
if (reg.size == 0)
sys/arch/armv7/armv7/armv7_machdep.c
800
start = reg.addr;
sys/arch/armv7/armv7/armv7_machdep.c
801
end = MIN(reg.addr + reg.size, (paddr_t)-PAGE_SIZE);
sys/arch/armv7/armv7/intr.c
423
arm_intr_establish_fdt_imap(int node, int *reg, int nreg, int level,
sys/arch/armv7/armv7/intr.c
426
return arm_intr_establish_fdt_imap_cpu(node, reg, nreg, level, NULL,
sys/arch/armv7/armv7/intr.c
431
arm_intr_establish_fdt_imap_cpu(int node, int *reg, int nreg, int level,
sys/arch/armv7/armv7/intr.c
468
(reg[0] & map_mask[0]) == cell[0] &&
sys/arch/armv7/armv7/intr.c
469
(reg[1] & map_mask[1]) == cell[1] &&
sys/arch/armv7/armv7/intr.c
470
(reg[2] & map_mask[2]) == cell[2] &&
sys/arch/armv7/armv7/intr.c
471
(reg[3] & map_mask[3]) == cell[3] &&
sys/arch/armv7/broadcom/bcm2836_intr.c
147
uint32_t phandle, reg[2];
sys/arch/armv7/broadcom/bcm2836_intr.c
174
if (OF_getpropintarray(node, "reg", reg, sizeof(reg)) != sizeof(reg))
sys/arch/armv7/broadcom/bcm2836_intr.c
177
if (bus_space_map(sc->sc_iot, reg[0], reg[1], 0, &sc->sc_lioh))
sys/arch/armv7/exynos/ec_commands.h
1337
uint8_t reg;
sys/arch/armv7/exynos/ec_commands.h
1345
uint8_t reg;
sys/arch/armv7/exynos/ec_commands.h
1354
uint8_t reg;
sys/arch/armv7/exynos/ec_commands.h
675
uint8_t ctrl, reg, value;
sys/arch/armv7/exynos/ec_commands.h
676
} reg;
sys/arch/armv7/exynos/ec_commands.h
690
uint8_t reg;
sys/arch/armv7/exynos/ec_commands.h
704
} off, on, init, brightness, seq, reg, rgb, demo, set_params;
sys/arch/armv7/exynos/exclock.c
236
uint32_t reg, div, mux;
sys/arch/armv7/exynos/exclock.c
248
reg = HREAD4(sc, EXYNOS5420_DIV_FSYS1);
sys/arch/armv7/exynos/exclock.c
249
div = ((reg >> 20) & ((1 << 10) - 1)) + 1;
sys/arch/armv7/exynos/exclock.c
250
reg = HREAD4(sc, EXYNOS5420_SRC_FSYS);
sys/arch/armv7/exynos/exclock.c
251
mux = ((reg >> 16) & ((1 << 3) - 1));
sys/arch/armv7/exynos/exclock.c
265
reg = HREAD4(sc, EXYNOS5420_SRC_TOP6);
sys/arch/armv7/exynos/exclock.c
266
mux = ((reg >> 8) & ((1 << 1) - 1));
sys/arch/armv7/exynos/exclock.c
277
reg = HREAD4(sc, EXYNOS5420_RPLL_CON0);
sys/arch/armv7/exynos/exclock.c
278
mdiv = (reg >> 16) & 0x1ff;
sys/arch/armv7/exynos/exclock.c
279
pdiv = (reg >> 8) & 0x3f;
sys/arch/armv7/exynos/exclock.c
280
sdiv = (reg >> 0) & 0x7;
sys/arch/armv7/exynos/exclock.c
281
reg = HREAD4(sc, EXYNOS5420_RPLL_CON1);
sys/arch/armv7/exynos/exclock.c
282
kdiv = (reg >> 0) & 0xffff;
sys/arch/armv7/exynos/exclock.c
288
reg = HREAD4(sc, EXYNOS5420_SPLL_CON0);
sys/arch/armv7/exynos/exclock.c
289
mdiv = (reg >> 16) & 0x3ff;
sys/arch/armv7/exynos/exclock.c
290
pdiv = (reg >> 8) & 0x3f;
sys/arch/armv7/exynos/exclock.c
291
sdiv = (reg >> 0) & 0x7;
sys/arch/armv7/exynos/exclock.c
56
#define HREAD4(sc, reg) \
sys/arch/armv7/exynos/exclock.c
57
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/armv7/exynos/exclock.c
58
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/exynos/exclock.c
59
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/exynos/exclock.c
60
#define HSET4(sc, reg, bits) \
sys/arch/armv7/exynos/exclock.c
61
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/armv7/exynos/exclock.c
62
#define HCLR4(sc, reg, bits) \
sys/arch/armv7/exynos/exclock.c
63
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/armv7/exynos/exdisplay.c
129
struct fdt_reg reg;
sys/arch/armv7/exynos/exdisplay.c
130
if (fdt_get_reg(aa->aa_node, 0, ®))
sys/arch/armv7/exynos/exdisplay.c
133
mem.addr = reg.addr;
sys/arch/armv7/exynos/exdisplay.c
134
mem.size = reg.size;
sys/arch/armv7/exynos/exgpio.c
212
uint32_t reg;
sys/arch/armv7/exynos/exgpio.c
247
reg = HREAD4(sc, GPXCON(bank->addr));
sys/arch/armv7/exynos/exgpio.c
248
reg &= ~(0xf << (pin * 4));
sys/arch/armv7/exynos/exgpio.c
249
reg |= (func << (pin * 4));
sys/arch/armv7/exynos/exgpio.c
250
HWRITE4(sc, GPXCON(bank->addr), reg);
sys/arch/armv7/exynos/exgpio.c
252
reg = HREAD4(sc, GPXDAT(bank->addr));
sys/arch/armv7/exynos/exgpio.c
254
reg |= (1 << pin);
sys/arch/armv7/exynos/exgpio.c
256
reg &= ~(1 << pin);
sys/arch/armv7/exynos/exgpio.c
257
HWRITE4(sc, GPXDAT(bank->addr), reg);
sys/arch/armv7/exynos/exgpio.c
259
reg = HREAD4(sc, GPXPUD(bank->addr));
sys/arch/armv7/exynos/exgpio.c
260
reg &= ~(0x3 << (pin * 2));
sys/arch/armv7/exynos/exgpio.c
261
reg |= (pud << (pin * 2));
sys/arch/armv7/exynos/exgpio.c
262
HWRITE4(sc, GPXPUD(bank->addr), reg);
sys/arch/armv7/exynos/exgpio.c
264
reg = HREAD4(sc, GPXDRV(bank->addr));
sys/arch/armv7/exynos/exgpio.c
265
reg &= ~(0x3 << (pin * 2));
sys/arch/armv7/exynos/exgpio.c
266
reg |= (drv << (pin * 2));
sys/arch/armv7/exynos/exgpio.c
267
HWRITE4(sc, GPXDRV(bank->addr), reg);
sys/arch/armv7/exynos/exgpio.c
304
uint32_t reg;
sys/arch/armv7/exynos/exgpio.c
310
reg = HREAD4(ec->ec_sc, GPXDAT(ec->ec_bank->addr));
sys/arch/armv7/exynos/exgpio.c
311
reg &= (1 << pin);
sys/arch/armv7/exynos/exgpio.c
312
val = (reg >> pin) & 1;
sys/arch/armv7/exynos/exgpio.c
324
uint32_t reg;
sys/arch/armv7/exynos/exgpio.c
329
reg = HREAD4(ec->ec_sc, GPXDAT(ec->ec_bank->addr));
sys/arch/armv7/exynos/exgpio.c
333
reg |= (1 << pin);
sys/arch/armv7/exynos/exgpio.c
335
reg &= ~(1 << pin);
sys/arch/armv7/exynos/exgpio.c
336
HWRITE4(ec->ec_sc, GPXDAT(ec->ec_bank->addr), reg);
sys/arch/armv7/exynos/exgpio.c
42
#define HREAD4(sc, reg) \
sys/arch/armv7/exynos/exgpio.c
43
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/armv7/exynos/exgpio.c
44
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/exynos/exgpio.c
45
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/exynos/exiic.c
100
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/armv7/exynos/exiic.c
158
uint32_t reg[1];
sys/arch/armv7/exynos/exiic.c
163
memset(reg, 0, sizeof(reg));
sys/arch/armv7/exynos/exiic.c
170
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/arch/armv7/exynos/exiic.c
175
ia.ia_addr = bemtoh32(®[0]);
sys/arch/armv7/exynos/exiic.c
206
exiic_wait_state(struct exiic_softc *sc, uint32_t reg, uint32_t mask, uint32_t value)
sys/arch/armv7/exynos/exiic.c
210
state = HREAD4(sc, reg);
sys/arch/armv7/exynos/exiic.c
212
if (((state = HREAD4(sc, reg)) & mask) == value)
sys/arch/armv7/exynos/exiic.c
93
#define HREAD4(sc, reg) \
sys/arch/armv7/exynos/exiic.c
94
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/armv7/exynos/exiic.c
95
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/exynos/exiic.c
96
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/exynos/exiic.c
97
#define HSET4(sc, reg, bits) \
sys/arch/armv7/exynos/exiic.c
98
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/armv7/exynos/exiic.c
99
#define HCLR4(sc, reg, bits) \
sys/arch/armv7/exynos/exmct.c
70
uint32_t i, mask, reg;
sys/arch/armv7/exynos/exmct.c
92
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MCT_WRITE_STAT);
sys/arch/armv7/exynos/exmct.c
93
if (reg & mask) {
sys/arch/armv7/exynos/expower.c
31
#define HREAD4(sc, reg) \
sys/arch/armv7/exynos/expower.c
32
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/armv7/exynos/expower.c
33
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/exynos/expower.c
34
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/exynos/expower.c
35
#define HSET4(sc, reg, bits) \
sys/arch/armv7/exynos/expower.c
36
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/armv7/exynos/expower.c
37
#define HCLR4(sc, reg, bits) \
sys/arch/armv7/exynos/expower.c
38
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/armv7/imx/imxahci.c
126
uint32_t reg;
sys/arch/armv7/imx/imxahci.c
154
reg = regmap_read_4(rm, IOMUXC_GPR13);
sys/arch/armv7/imx/imxahci.c
155
reg &= ~IOMUXC_GPR13_SATA_MASK;
sys/arch/armv7/imx/imxahci.c
156
reg |= IOMUXC_GPR13_SATA_PHY_2_1104V |
sys/arch/armv7/imx/imxahci.c
163
regmap_write_4(rm, IOMUXC_GPR13, reg);
sys/arch/armv7/imx/imxahci.c
164
reg = regmap_read_4(rm, IOMUXC_GPR13);
sys/arch/armv7/imx/imxahci.c
165
reg |= IOMUXC_GPR13_SATA_PHY_1_MPLL_CLK_EN;
sys/arch/armv7/imx/imxahci.c
166
regmap_write_4(rm, IOMUXC_GPR13, reg);
sys/arch/armv7/imx/imxtemp.c
61
#define HREAD4(sc, reg) \
sys/arch/armv7/imx/imxtemp.c
62
regmap_read_4((sc)->sc_rm, (reg))
sys/arch/armv7/imx/imxtemp.c
63
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/imx/imxtemp.c
64
regmap_write_4((sc)->sc_rm, (reg), (val))
sys/arch/armv7/imx/imxtemp.c
65
#define HSET4(sc, reg, bits) \
sys/arch/armv7/imx/imxtemp.c
66
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/armv7/imx/imxtemp.c
67
#define HCLR4(sc, reg, bits) \
sys/arch/armv7/imx/imxtemp.c
68
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/armv7/marvell/mvacc.c
34
#define HREAD4(sc, reg) \
sys/arch/armv7/marvell/mvacc.c
35
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/armv7/marvell/mvacc.c
36
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/marvell/mvacc.c
37
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/marvell/mvacc.c
38
#define HSET4(sc, reg, bits) \
sys/arch/armv7/marvell/mvacc.c
39
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/armv7/marvell/mvacc.c
40
#define HCLR4(sc, reg, bits) \
sys/arch/armv7/marvell/mvacc.c
41
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/armv7/marvell/mvagc.c
28
#define HREAD4(sc, reg) \
sys/arch/armv7/marvell/mvagc.c
29
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/armv7/marvell/mvagc.c
30
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/marvell/mvagc.c
31
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/marvell/mvagc.c
32
#define HSET4(sc, reg, bits) \
sys/arch/armv7/marvell/mvagc.c
33
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/armv7/marvell/mvagc.c
34
#define HCLR4(sc, reg, bits) \
sys/arch/armv7/marvell/mvagc.c
35
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/armv7/marvell/mvahci.c
35
#define MVAHCI_READ(sc, reg) \
sys/arch/armv7/marvell/mvahci.c
36
bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
sys/arch/armv7/marvell/mvahci.c
37
#define MVAHCI_WRITE(sc, reg, val) \
sys/arch/armv7/marvell/mvahci.c
38
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/marvell/mvmbus.c
120
struct fdt_reg reg;
sys/arch/armv7/marvell/mvmbus.c
132
if (fdt_get_reg(mbusc, 0, ®))
sys/arch/armv7/marvell/mvmbus.c
136
if (bus_space_map(sc->sc_iot, reg.addr, reg.size, 0, &sc->sc_mbus_ioh))
sys/arch/armv7/marvell/mvmbus.c
139
if (fdt_get_reg(mbusc, 1, ®))
sys/arch/armv7/marvell/mvmbus.c
143
if (bus_space_map(sc->sc_iot, reg.addr, reg.size, 0, &sc->sc_sdram_ioh))
sys/arch/armv7/marvell/mvmbus.c
147
if (fdt_get_reg(mbusc, 2, ®) == 0)
sys/arch/armv7/marvell/mvmbus.c
148
if (bus_space_map(sc->sc_iot, reg.addr, reg.size, 0,
sys/arch/armv7/marvell/mvodog.c
33
#define HREAD4(sc, ioh, reg) \
sys/arch/armv7/marvell/mvodog.c
34
(bus_space_read_4((sc)->sc_iot, (ioh), (reg)))
sys/arch/armv7/marvell/mvodog.c
35
#define HWRITE4(sc, ioh, reg, val) \
sys/arch/armv7/marvell/mvodog.c
36
bus_space_write_4((sc)->sc_iot, (ioh), (reg), (val))
sys/arch/armv7/marvell/mvodog.c
37
#define HSET4(sc, ioh, reg, bits) \
sys/arch/armv7/marvell/mvodog.c
38
HWRITE4((sc), (ioh), (reg), HREAD4((sc), (ioh), (reg)) | (bits))
sys/arch/armv7/marvell/mvodog.c
39
#define HCLR4(sc, ioh, reg, bits) \
sys/arch/armv7/marvell/mvodog.c
40
HWRITE4((sc), (ioh), (reg), HREAD4((sc), (ioh), (reg)) & ~(bits))
sys/arch/armv7/marvell/mvortc.c
109
reg = bus_space_read_4(sc->sc_iot, sc->sc_soc_ioh, RTC_TIMING_CTL);
sys/arch/armv7/marvell/mvortc.c
110
reg &= ~RTC_PERIOD_MASK;
sys/arch/armv7/marvell/mvortc.c
111
reg |= (0x3ff << RTC_PERIOD_SHIFT);
sys/arch/armv7/marvell/mvortc.c
112
reg &= ~RTC_READ_DELAY_MASK;
sys/arch/armv7/marvell/mvortc.c
113
reg |= (0x1f << RTC_READ_DELAY_SHIFT);
sys/arch/armv7/marvell/mvortc.c
114
bus_space_write_4(sc->sc_iot, sc->sc_soc_ioh, RTC_TIMING_CTL, reg);
sys/arch/armv7/marvell/mvortc.c
124
mvortc_read(struct mvortc_softc *sc, int reg)
sys/arch/armv7/marvell/mvortc.c
135
sample = HREAD4(sc, reg);
sys/arch/armv7/marvell/mvortc.c
164
mvortc_write(struct mvortc_softc *sc, int reg, uint32_t val)
sys/arch/armv7/marvell/mvortc.c
168
HWRITE4(sc, reg, val);
sys/arch/armv7/marvell/mvortc.c
186
uint32_t reg;
sys/arch/armv7/marvell/mvortc.c
188
reg = mvortc_read(sc, RTC_CONF_TEST);
sys/arch/armv7/marvell/mvortc.c
189
if (reg & 0xff) {
sys/arch/armv7/marvell/mvortc.c
45
#define HREAD4(sc, reg) \
sys/arch/armv7/marvell/mvortc.c
46
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/armv7/marvell/mvortc.c
47
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/marvell/mvortc.c
48
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/marvell/mvortc.c
86
uint32_t reg;
sys/arch/armv7/marvell/mvpcie.c
321
uint32_t reg[5];
sys/arch/armv7/marvell/mvpcie.c
332
if (OF_getpropintarray(po->po_node, "reg", reg,
sys/arch/armv7/marvell/mvpcie.c
333
sizeof(reg)) != sizeof(reg))
sys/arch/armv7/marvell/mvpcie.c
342
po->po_dev = (reg[0] >> 11) & 0x1f;
sys/arch/armv7/marvell/mvpcie.c
343
po->po_fn = (reg[0] >> 8) & 0x7;
sys/arch/armv7/marvell/mvpcie.c
639
mvpcie_conf_read_bridge(struct mvpcie_port *po, int reg)
sys/arch/armv7/marvell/mvpcie.c
641
switch (reg) {
sys/arch/armv7/marvell/mvpcie.c
675
printf("%s: reg %x\n", __func__, reg);
sys/arch/armv7/marvell/mvpcie.c
682
mvpcie_conf_write_bridge(struct mvpcie_port *po, int reg, pcireg_t data)
sys/arch/armv7/marvell/mvpcie.c
684
switch (reg) {
sys/arch/armv7/marvell/mvpcie.c
726
printf("%s: reg %x data %x\n", __func__, reg, data);
sys/arch/armv7/marvell/mvpcie.c
732
mvpcie_conf_read(void *v, pcitag_t tag, int reg)
sys/arch/armv7/marvell/mvpcie.c
740
return mvpcie_conf_read_bridge(po, reg);
sys/arch/armv7/marvell/mvpcie.c
747
PCIE_CONF_FUNC(fn) | PCIE_CONF_REG(reg) | PCIE_CONF_ADDR_EN);
sys/arch/armv7/marvell/mvpcie.c
752
mvpcie_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
sys/arch/armv7/marvell/mvpcie.c
760
mvpcie_conf_write_bridge(po, reg, data);
sys/arch/armv7/marvell/mvpcie.c
768
PCIE_CONF_FUNC(fn) | PCIE_CONF_REG(reg) | PCIE_CONF_ADDR_EN);
sys/arch/armv7/marvell/mvpcie.c
77
#define HREAD4(po, reg) \
sys/arch/armv7/marvell/mvpcie.c
78
(bus_space_read_4((po)->po_iot, (po)->po_ioh, (reg)))
sys/arch/armv7/marvell/mvpcie.c
79
#define HWRITE4(po, reg, val) \
sys/arch/armv7/marvell/mvpcie.c
80
bus_space_write_4((po)->po_iot, (po)->po_ioh, (reg), (val))
sys/arch/armv7/marvell/mvpcie.c
81
#define HSET4(po, reg, bits) \
sys/arch/armv7/marvell/mvpcie.c
82
HWRITE4((po), (reg), HREAD4((po), (reg)) | (bits))
sys/arch/armv7/marvell/mvpcie.c
83
#define HCLR4(po, reg, bits) \
sys/arch/armv7/marvell/mvpcie.c
831
uint32_t reg[4];
sys/arch/armv7/marvell/mvpcie.c
836
reg[0] = bus << 16 | dev << 11 | fn << 8;
sys/arch/armv7/marvell/mvpcie.c
837
reg[1] = reg[2] = 0;
sys/arch/armv7/marvell/mvpcie.c
838
reg[3] = ih->ih_intrpin;
sys/arch/armv7/marvell/mvpcie.c
84
HWRITE4((po), (reg), HREAD4((po), (reg)) & ~(bits))
sys/arch/armv7/marvell/mvpcie.c
840
cookie = arm_intr_establish_fdt_imap_cpu(po->po_node, reg,
sys/arch/armv7/marvell/mvpcie.c
841
sizeof(reg), level, ci, func, arg, name);
sys/arch/armv7/marvell/mvpxa.c
36
#define MVPXA_READ(sc, reg) \
sys/arch/armv7/marvell/mvpxa.c
37
bus_space_read_4((sc)->sc_iot, (sc)->mbus_ioh, (reg))
sys/arch/armv7/marvell/mvpxa.c
38
#define MVPXA_WRITE(sc, reg, val) \
sys/arch/armv7/marvell/mvpxa.c
39
bus_space_write_4((sc)->sc_iot, (sc)->mbus_ioh, (reg), (val))
sys/arch/armv7/marvell/mvsysctrl.c
33
#define HREAD4(sc, reg) \
sys/arch/armv7/marvell/mvsysctrl.c
34
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/armv7/marvell/mvsysctrl.c
35
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/marvell/mvsysctrl.c
36
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/marvell/mvsysctrl.c
37
#define HSET4(sc, reg, bits) \
sys/arch/armv7/marvell/mvsysctrl.c
38
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/armv7/marvell/mvsysctrl.c
39
#define HCLR4(sc, reg, bits) \
sys/arch/armv7/marvell/mvsysctrl.c
40
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/armv7/marvell/mvxhci.c
38
#define MVXHCI_READ(sc, reg) \
sys/arch/armv7/marvell/mvxhci.c
39
bus_space_read_4((sc)->sc.iot, (sc)->mbus_ioh, (reg))
sys/arch/armv7/marvell/mvxhci.c
40
#define MVXHCI_WRITE(sc, reg, val) \
sys/arch/armv7/marvell/mvxhci.c
41
bus_space_write_4((sc)->sc.iot, (sc)->mbus_ioh, (reg), (val))
sys/arch/armv7/omap/amdisplay.c
127
preg(uint32_t reg, char *rn, struct amdisplay_softc *sc)
sys/arch/armv7/omap/amdisplay.c
131
read = HREAD4(sc, reg);
sys/arch/armv7/omap/amdisplay.c
180
uint32_t reg;
sys/arch/armv7/omap/amdisplay.c
194
reg = HREAD4(sc, LCD_SYSCONFIG);
sys/arch/armv7/omap/amdisplay.c
195
reg &= ~(LCD_SYSCONFIG_STANDBYMODE | LCD_SYSCONFIG_IDLEMODE);
sys/arch/armv7/omap/amdisplay.c
196
reg |= (0x2 << LCD_SYSCONFIG_STANDBYMODE_SHAMT)
sys/arch/armv7/omap/amdisplay.c
198
HWRITE4(sc, LCD_SYSCONFIG, reg);
sys/arch/armv7/omap/amdisplay.c
282
reg = HREAD4(sc, LCD_CTRL);
sys/arch/armv7/omap/amdisplay.c
283
reg &= ~LCD_CTRL_CLKDIV;
sys/arch/armv7/omap/amdisplay.c
284
reg |= (0x2 << LCD_CTRL_CLKDIV_SHAMT);
sys/arch/armv7/omap/amdisplay.c
287
reg |= LCD_CTRL_MODESEL;
sys/arch/armv7/omap/amdisplay.c
288
HWRITE4(sc, LCD_CTRL, reg);
sys/arch/armv7/omap/amdisplay.c
291
reg = HREAD4(sc, LCD_RASTER_CTRL);
sys/arch/armv7/omap/amdisplay.c
292
reg &= 0xF8000C7C;
sys/arch/armv7/omap/amdisplay.c
293
reg |= (LCD_RASTER_CTRL_LCDTFT)
sys/arch/armv7/omap/amdisplay.c
296
HWRITE4(sc, LCD_RASTER_CTRL, reg);
sys/arch/armv7/omap/amdisplay.c
308
reg = HREAD4(sc, LCD_LCDDMA_CTRL);
sys/arch/armv7/omap/amdisplay.c
309
reg &= ~(LCD_LCDDMA_CTRL_DMA_MASTER_PRIO
sys/arch/armv7/omap/amdisplay.c
315
reg |= (0x4 << LCD_LCDDMA_CTRL_BURST_SIZE_SHAMT)
sys/arch/armv7/omap/amdisplay.c
317
HWRITE4(sc, LCD_LCDDMA_CTRL, reg);
sys/arch/armv7/omap/amdisplay.c
328
reg = 0;
sys/arch/armv7/omap/amdisplay.c
329
reg |= (LCD_IRQ_EOF1 | LCD_IRQ_EOF0 | LCD_IRQ_PL | LCD_IRQ_FUF |
sys/arch/armv7/omap/amdisplay.c
332
HWRITE4(sc, LCD_IRQENABLE_SET, reg);
sys/arch/armv7/omap/amdisplay.c
396
uint32_t reg;
sys/arch/armv7/omap/amdisplay.c
398
reg = HREAD4(sc, LCD_IRQSTATUS);
sys/arch/armv7/omap/amdisplay.c
399
HWRITE4(sc, LCD_IRQSTATUS, reg);
sys/arch/armv7/omap/amdisplay.c
401
DPRINTF(25, ("%s: intr 0x%08x\n", DEVNAME(sc), reg));
sys/arch/armv7/omap/amdisplay.c
403
if (ISSET(reg, LCD_IRQ_PL)) {
sys/arch/armv7/omap/amdisplay.c
405
DEVNAME(sc), reg));
sys/arch/armv7/omap/amdisplay.c
413
if (ISSET(reg, LCD_IRQ_FUF)) {
sys/arch/armv7/omap/amdisplay.c
417
if (ISSET(reg, LCD_IRQ_SYNC)) {
sys/arch/armv7/omap/amdisplay.c
422
if (ISSET(reg, LCD_IRQ_RR_DONE)) {
sys/arch/armv7/omap/amdisplay.c
429
if (ISSET(reg, LCD_IRQ_EOF0)) {
sys/arch/armv7/omap/amdisplay.c
433
if (ISSET(reg, LCD_IRQ_EOF1)) {
sys/arch/armv7/omap/amdisplay.c
437
if (ISSET(reg, LCD_IRQ_DONE)) {
sys/arch/armv7/omap/amdisplay.c
449
if (ISSET(reg, LCD_IRQ_ACB)) {
sys/arch/armv7/omap/amdisplay.c
54
#define HREAD4(sc, reg) \
sys/arch/armv7/omap/amdisplay.c
55
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/armv7/omap/amdisplay.c
56
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/omap/amdisplay.c
57
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/omap/amdisplay.c
58
#define HSET4(sc, reg, bits) \
sys/arch/armv7/omap/amdisplay.c
59
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/armv7/omap/amdisplay.c
60
#define HCLR4(sc, reg, bits) \
sys/arch/armv7/omap/amdisplay.c
61
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/armv7/omap/dmtimer.c
103
void dmtimer_wait(int reg);
sys/arch/armv7/omap/dmtimer.c
262
dmtimer_wait(int reg)
sys/arch/armv7/omap/dmtimer.c
265
while (bus_space_read_4(sc->sc_iot, sc->sc_ioh[0], DM_TWPS) & reg)
sys/arch/armv7/omap/edma.c
72
#define TPCC_READ_4(sc, reg) \
sys/arch/armv7/omap/edma.c
73
(bus_space_read_4((sc)->sc_iot, (sc)->sc_tpcc, (reg)))
sys/arch/armv7/omap/edma.c
74
#define TPCC_WRITE_4(sc, reg, val) \
sys/arch/armv7/omap/edma.c
75
(bus_space_write_4((sc)->sc_iot, (sc)->sc_tpcc, (reg), (val)))
sys/arch/armv7/omap/edma.c
76
#define TPCC_SET(sc, reg, val) \
sys/arch/armv7/omap/edma.c
77
(TPCC_WRITE_4((sc), (reg), (TPCC_READ_4(sc, reg) | (val))))
sys/arch/armv7/omap/edma.c
78
#define TPCC_FILTSET(sc, reg, val, filt) \
sys/arch/armv7/omap/edma.c
79
(TPCC_WRITE_4((sc), (reg), (TPCC_READ_4(sc, reg) & (filt)) | (val)))
sys/arch/armv7/omap/gptimer.c
100
void gptimer_wait(int reg);
sys/arch/armv7/omap/gptimer.c
231
gptimer_wait(int reg)
sys/arch/armv7/omap/gptimer.c
233
while (bus_space_read_4(gptimer_iot, gptimer_ioh0, GP_TWPS) & reg)
sys/arch/armv7/omap/if_cpsw.c
684
cpsw_mii_wait(struct cpsw_softc * const sc, int reg)
sys/arch/armv7/omap/if_cpsw.c
689
if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg) & (1U << 31)) == 0)
sys/arch/armv7/omap/if_cpsw.c
697
cpsw_mii_readreg(struct device *dev, int phy, int reg)
sys/arch/armv7/omap/if_cpsw.c
706
((reg & 0x1F) << 21) | ((phy & 0x1F) << 16));
sys/arch/armv7/omap/if_cpsw.c
719
cpsw_mii_writereg(struct device *dev, int phy, int reg, int val)
sys/arch/armv7/omap/if_cpsw.c
730
((reg & 0x1F) << 21) | ((phy & 0x1F) << 16) | val);
sys/arch/armv7/omap/intc.c
72
#define INTC_ILR_PRI(reg) (((reg) >> 2) & 0x2f)
sys/arch/armv7/omap/nxphdmi.c
433
nxphdmi_read(struct nxphdmi_softc *sc, uint16_t reg, uint8_t *buf)
sys/arch/armv7/omap/nxphdmi.c
437
nxphdmi_set_page(sc, REGPAGE(reg));
sys/arch/armv7/omap/nxphdmi.c
439
if ((ret = iic_smbus_read_byte(sc->sc_tag, TDA_HDMI, REGADDR(reg),
sys/arch/armv7/omap/nxphdmi.c
443
DEVNAME(sc), REGADDR(reg), REGPAGE(reg), ret));
sys/arch/armv7/omap/nxphdmi.c
448
DEVNAME(sc), *buf, REGADDR(reg), REGPAGE(reg)));
sys/arch/armv7/omap/nxphdmi.c
454
nxphdmi_write(struct nxphdmi_softc *sc, uint16_t reg, uint8_t val)
sys/arch/armv7/omap/nxphdmi.c
457
uint8_t sendbuf[] = { REGADDR(reg), val };
sys/arch/armv7/omap/nxphdmi.c
459
nxphdmi_set_page(sc, REGPAGE(reg));
sys/arch/armv7/omap/nxphdmi.c
465
DEVNAME(sc), val, REGADDR(reg), REGPAGE(reg), ret));
sys/arch/armv7/omap/nxphdmi.c
470
DEVNAME(sc), val, REGADDR(reg), REGPAGE(reg)));
sys/arch/armv7/omap/nxphdmi.c
476
nxphdmi_write2(struct nxphdmi_softc *sc, uint16_t reg, uint16_t val)
sys/arch/armv7/omap/nxphdmi.c
479
uint8_t sendbuf[] = { REGADDR(reg), val >> 8, val & 0xff };
sys/arch/armv7/omap/nxphdmi.c
481
nxphdmi_set_page(sc, REGPAGE(reg));
sys/arch/armv7/omap/nxphdmi.c
487
DEVNAME(sc), val, REGADDR(reg), REGPAGE(reg), ret));
sys/arch/armv7/omap/nxphdmi.c
492
DEVNAME(sc), val, REGADDR(reg), REGPAGE(reg)));
sys/arch/armv7/omap/nxphdmi.c
499
nxphdmi_set(struct nxphdmi_softc *sc, uint16_t reg, uint8_t bits)
sys/arch/armv7/omap/nxphdmi.c
504
ret |= nxphdmi_read(sc, reg, &buf);
sys/arch/armv7/omap/nxphdmi.c
506
ret |= nxphdmi_write(sc, reg, buf);
sys/arch/armv7/omap/nxphdmi.c
512
nxphdmi_clear(struct nxphdmi_softc *sc, uint16_t reg, uint8_t bits)
sys/arch/armv7/omap/nxphdmi.c
517
ret |= nxphdmi_read(sc, reg, &buf);
sys/arch/armv7/omap/nxphdmi.c
519
ret |= nxphdmi_write(sc, reg, buf);
sys/arch/armv7/omap/nxphdmi.c
551
uint8_t reg;
sys/arch/armv7/omap/nxphdmi.c
565
nxphdmi_read(sc, TDA_INT_FLAGS_2, ®);
sys/arch/armv7/omap/nxphdmi.c
566
if (reg & INT_FLAGS_2_EDID_BLK_RD) {
sys/arch/armv7/omap/nxphdmi.c
580
reg = 0x00;
sys/arch/armv7/omap/nxphdmi.c
583
iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, TDA_HDMI, ®, 1,
sys/arch/armv7/omap/nxphdmi.c
588
reg++;
sys/arch/armv7/omap/nxphdmi.c
630
uint8_t reg, div;
sys/arch/armv7/omap/nxphdmi.c
69
#define REGPAGE(reg) (((reg) >> 8) & 0xff)
sys/arch/armv7/omap/nxphdmi.c
70
#define REGADDR(reg) ((reg) & 0xff)
sys/arch/armv7/omap/nxphdmi.c
718
reg = VIP_CNTRL_3_SYNC_HS;
sys/arch/armv7/omap/nxphdmi.c
720
reg |= VIP_CNTRL_3_H_TGL;
sys/arch/armv7/omap/nxphdmi.c
722
reg |= VIP_CNTRL_3_V_TGL;
sys/arch/armv7/omap/nxphdmi.c
723
nxphdmi_write(sc, TDA_VIP_CNTRL_3, reg);
sys/arch/armv7/omap/nxphdmi.c
725
reg = TBG_CNTRL_1_TGL_EN;
sys/arch/armv7/omap/nxphdmi.c
727
reg |= TBG_CNTRL_1_H_TGL;
sys/arch/armv7/omap/nxphdmi.c
729
reg |= TBG_CNTRL_1_V_TGL;
sys/arch/armv7/omap/nxphdmi.c
730
nxphdmi_write(sc, TDA_TBG_CNTRL_1, reg);
sys/arch/armv7/omap/omclock.c
134
uint32_t reg;
sys/arch/armv7/omap/omclock.c
137
reg = HREAD4(sc, base);
sys/arch/armv7/omap/omclock.c
139
reg &= ~MODULEMODE_MASK;
sys/arch/armv7/omap/omclock.c
141
reg |= MODULEMODE_ENABLED;
sys/arch/armv7/omap/omclock.c
143
reg |= MODULEMODE_DISABLED;
sys/arch/armv7/omap/omclock.c
146
reg |= (1U << idx);
sys/arch/armv7/omap/omclock.c
148
reg &= ~(1U << idx);
sys/arch/armv7/omap/omclock.c
150
HWRITE4(sc, base, reg);
sys/arch/armv7/omap/omclock.c
38
#define HREAD4(sc, reg) \
sys/arch/armv7/omap/omclock.c
39
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/armv7/omap/omclock.c
40
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/omap/omclock.c
41
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/omap/omclock.c
42
#define HSET4(sc, reg, bits) \
sys/arch/armv7/omap/omclock.c
43
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/armv7/omap/omclock.c
44
#define HCLR4(sc, reg, bits) \
sys/arch/armv7/omap/omclock.c
45
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/armv7/omap/omdisplay.c
889
u_int32_t reg;
sys/arch/armv7/omap/omdisplay.c
896
reg = bus_space_read_4(sc->sc_iot, sc->sc_dcioh, DISPC_CONTROL);
sys/arch/armv7/omap/omdisplay.c
900
if (reg & (DISPC_CONTROL_LCDENABLE|DISPC_CONTROL_DIGITALENABLE)) {
sys/arch/armv7/omap/omdisplay.c
948
reg = 0;
sys/arch/armv7/omap/omdisplay.c
950
reg |= DISPC_POL_FREQ_IHS;
sys/arch/armv7/omap/omdisplay.c
952
reg |= DISPC_POL_FREQ_IVS;
sys/arch/armv7/omap/omdisplay.c
953
bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_POL_FREQ, reg);
sys/arch/armv7/omap/omehci.c
117
uint32_t reg[2];
sys/arch/armv7/omap/omehci.c
155
if (OF_getpropintarray(node, "reg", reg, sizeof(reg)) != sizeof(reg))
sys/arch/armv7/omap/omehci.c
159
if (bus_space_map(sc->sc.iot, reg[0], reg[1], 0, &sc->sc.ioh)) {
sys/arch/armv7/omap/omehci.c
163
sc->sc.sc_size = reg[1];
sys/arch/armv7/omap/omehci.c
230
uint32_t i = 0, reg;
sys/arch/armv7/omap/omehci.c
299
reg = bus_space_read_4(sc->sc.iot, sc->uhh_ioh,
sys/arch/armv7/omap/omehci.c
302
reg &= ~(UHH_SYSCONFIG_SIDLEMODE_MASK |
sys/arch/armv7/omap/omehci.c
304
reg |= (UHH_SYSCONFIG_ENAWAKEUP |
sys/arch/armv7/omap/omehci.c
310
reg &= ~UHH_SYSCONFIG_IDLEMODE_MASK;
sys/arch/armv7/omap/omehci.c
311
reg |= UHH_SYSCONFIG_IDLEMODE_NOIDLE;
sys/arch/armv7/omap/omehci.c
312
reg &= ~UHH_SYSCONFIG_STANDBYMODE_MASK;
sys/arch/armv7/omap/omehci.c
313
reg |= UHH_SYSCONFIG_STANDBYMODE_NOSTDBY;
sys/arch/armv7/omap/omehci.c
316
reg);
sys/arch/armv7/omap/omehci.c
318
reg = bus_space_read_4(sc->sc.iot, sc->uhh_ioh,
sys/arch/armv7/omap/omehci.c
322
reg |= (UHH_HOSTCONFIG_ENA_INCR4 |
sys/arch/armv7/omap/omehci.c
325
reg &= ~UHH_HOSTCONFIG_ENA_INCR_ALIGN;
sys/arch/armv7/omap/omehci.c
329
reg &= ~UHH_HOSTCONFIG_P1_CONNECT_STATUS;
sys/arch/armv7/omap/omehci.c
331
reg &= ~UHH_HOSTCONFIG_P2_CONNECT_STATUS;
sys/arch/armv7/omap/omehci.c
333
reg &= ~UHH_HOSTCONFIG_P3_CONNECT_STATUS;
sys/arch/armv7/omap/omehci.c
339
reg &= ~UHH_HOSTCONFIG_P1_ULPI_BYPASS;
sys/arch/armv7/omap/omehci.c
341
reg |= UHH_HOSTCONFIG_P1_ULPI_BYPASS;
sys/arch/armv7/omap/omehci.c
343
reg |= UHH_HOSTCONFIG_APP_START_CLK;
sys/arch/armv7/omap/omehci.c
346
reg &= ~UHH_HOSTCONFIG_P1_MODE_MASK;
sys/arch/armv7/omap/omehci.c
347
reg &= ~UHH_HOSTCONFIG_P2_MODE_MASK;
sys/arch/armv7/omap/omehci.c
350
reg |= UHH_HOSTCONFIG_P1_MODE_UTMI_PHY;
sys/arch/armv7/omap/omehci.c
352
reg |= UHH_HOSTCONFIG_P1_MODE_HSIC;
sys/arch/armv7/omap/omehci.c
355
reg |= UHH_HOSTCONFIG_P2_MODE_UTMI_PHY;
sys/arch/armv7/omap/omehci.c
357
reg |= UHH_HOSTCONFIG_P2_MODE_HSIC;
sys/arch/armv7/omap/omehci.c
360
bus_space_write_4(sc->sc.iot, sc->uhh_ioh, OMAP_USBHOST_UHH_HOSTCONFIG, reg);
sys/arch/armv7/omap/omehci.c
377
reg = bus_space_read_4(sc->sc.iot, sc->sc.ioh, OMAP_USBHOST_USBCMD);
sys/arch/armv7/omap/omehci.c
378
reg &= 0xff00ffff;
sys/arch/armv7/omap/omehci.c
379
reg |= (1 << 16);
sys/arch/armv7/omap/omehci.c
380
bus_space_write_4(sc->sc.iot, sc->sc.ioh, OMAP_USBHOST_USBCMD, reg);
sys/arch/armv7/omap/omehci.c
394
uint32_t reg;
sys/arch/armv7/omap/omehci.c
396
reg = ULPI_FUNC_CTRL_RESET
sys/arch/armv7/omap/omehci.c
406
bus_space_write_4(sc->sc.iot, sc->sc.ioh, OMAP_USBHOST_INSNREG05_ULPI, reg);
sys/arch/armv7/omap/omgpio.c
188
#define READ4(sc, reg) omgpio_read4(sc, reg)
sys/arch/armv7/omap/omgpio.c
189
#define WRITE4(sc, reg, val) omgpio_write4(sc, reg, val)
sys/arch/armv7/omap/omgpio.c
220
omgpio_read4(struct omgpio_softc *sc, u_int32_t reg)
sys/arch/armv7/omap/omgpio.c
222
if(reg == -1)
sys/arch/armv7/omap/omgpio.c
225
return bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg));
sys/arch/armv7/omap/omgpio.c
229
omgpio_write4(struct omgpio_softc *sc, u_int32_t reg, u_int32_t val)
sys/arch/armv7/omap/omgpio.c
231
if(reg == -1)
sys/arch/armv7/omap/omgpio.c
234
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val));
sys/arch/armv7/omap/omgpio.c
485
u_int32_t reg;
sys/arch/armv7/omap/omgpio.c
488
reg = READ4(sc, sc->sc_regs.datain);
sys/arch/armv7/omap/omgpio.c
490
reg = READ4(sc, sc->sc_regs.dataout);
sys/arch/armv7/omap/omgpio.c
491
return (reg >> GPIO_PIN_TO_OFFSET(pin)) & 0x1;
sys/arch/armv7/omap/omgpio.c
527
u_int32_t reg;
sys/arch/armv7/omap/omgpio.c
531
reg = READ4(sc, sc->sc_regs.oe);
sys/arch/armv7/omap/omgpio.c
533
reg |= 1 << GPIO_PIN_TO_OFFSET(gpio);
sys/arch/armv7/omap/omgpio.c
535
reg &= ~(1 << GPIO_PIN_TO_OFFSET(gpio));
sys/arch/armv7/omap/omgpio.c
536
WRITE4(sc, sc->sc_regs.oe, reg);
sys/arch/armv7/omap/omgpio.c
544
u_int32_t reg;
sys/arch/armv7/omap/omgpio.c
545
reg = READ4(sc, sc->sc_regs.oe);
sys/arch/armv7/omap/omgpio.c
546
if (reg & (1 << GPIO_PIN_TO_OFFSET(gpio)))
sys/arch/armv7/omap/ommmc.c
221
#define HREAD4(sc, reg) \
sys/arch/armv7/omap/ommmc.c
222
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/armv7/omap/ommmc.c
223
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/omap/ommmc.c
224
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/omap/ommmc.c
225
#define HSET4(sc, reg, bits) \
sys/arch/armv7/omap/ommmc.c
226
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/armv7/omap/ommmc.c
227
#define HCLR4(sc, reg, bits) \
sys/arch/armv7/omap/ommmc.c
228
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/armv7/omap/ommmc.c
623
uint32_t reg;
sys/arch/armv7/omap/ommmc.c
661
reg = HREAD4(sc, MMCHS_HCTL);
sys/arch/armv7/omap/ommmc.c
662
reg &= ~MMCHS_HCTL_SDVS_MASK;
sys/arch/armv7/omap/ommmc.c
663
reg |= vdd;
sys/arch/armv7/omap/ommmc.c
664
HWRITE4(sc, MMCHS_HCTL, reg);
sys/arch/armv7/omap/ommmc.c
712
uint32_t reg;
sys/arch/armv7/omap/ommmc.c
746
reg = HREAD4(sc, MMCHS_SYSCTL);
sys/arch/armv7/omap/ommmc.c
747
reg &= ~MMCHS_SYSCTL_CLKD_MASK;
sys/arch/armv7/omap/ommmc.c
748
reg |= div << MMCHS_SYSCTL_CLKD_SH;
sys/arch/armv7/omap/ommmc.c
749
HWRITE4(sc, MMCHS_SYSCTL, reg);
sys/arch/armv7/omap/omrng.c
55
#define HREAD4(sc, reg) \
sys/arch/armv7/omap/omrng.c
56
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/armv7/omap/omrng.c
57
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/omap/omrng.c
58
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/omap/omrng.c
59
#define HSET4(sc, reg, bits) \
sys/arch/armv7/omap/omrng.c
60
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/armv7/omap/omrng.c
61
#define HCLR4(sc, reg, bits) \
sys/arch/armv7/omap/omrng.c
62
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/armv7/omap/prcm.c
120
u_int32_t reg;
sys/arch/armv7/omap/prcm.c
162
reg = bus_space_read_4(sc->sc_iot, sc->sc_prcm, PRCM_REVISION);
sys/arch/armv7/omap/prcm.c
163
printf(" rev %d.%d\n", reg >> 4 & 0xf, reg & 0xf);
sys/arch/armv7/omap/prcm.c
220
u_int32_t oreg, reg, mask;
sys/arch/armv7/omap/prcm.c
227
reg = oreg & ~mask;
sys/arch/armv7/omap/prcm.c
228
reg |=0x02;
sys/arch/armv7/omap/prcm.c
230
PRCM_AM335X_CLKSEL_TIMER2_CLK, reg);
sys/arch/armv7/omap/prcm.c
235
reg = oreg & ~mask;
sys/arch/armv7/omap/prcm.c
236
reg |=0x02;
sys/arch/armv7/omap/prcm.c
238
PRCM_AM335X_CLKSEL_TIMER3_CLK, reg);
sys/arch/armv7/omap/prcm.c
286
u_int32_t oreg, reg, mask;
sys/arch/armv7/omap/prcm.c
291
reg = (oreg &~mask) | (speed & mask);
sys/arch/armv7/omap/prcm.c
292
bus_space_write_4(sc->sc_iot, sc->sc_prcm, CM_CLKSEL_WKUP, reg);
sys/arch/armv7/omap/prcm.c
297
reg = (oreg & ~mask) | ( (speed << shift) & mask);
sys/arch/armv7/omap/prcm.c
298
bus_space_write_4(sc->sc_iot, sc->sc_prcm, CM_CLKSEL_PER, reg);
sys/arch/armv7/omap/prcm.c
400
int reg;
sys/arch/armv7/omap/prcm.c
403
reg = prcm_am335x_clkctrl(mod);
sys/arch/armv7/omap/prcm.c
404
clkctrl = bus_space_read_4(sc->sc_iot, sc->sc_prcm, reg);
sys/arch/armv7/omap/prcm.c
407
bus_space_write_4(sc->sc_iot, sc->sc_prcm, reg, clkctrl);
sys/arch/armv7/omap/prcm.c
410
while (bus_space_read_4(sc->sc_iot, sc->sc_prcm, reg) & 0x30000)
sys/arch/armv7/omap/prcm.c
419
int freg, ireg, reg;
sys/arch/armv7/omap/prcm.c
422
reg = bit >> 5;
sys/arch/armv7/omap/prcm.c
424
freg = prcm_fmask_addr[reg];
sys/arch/armv7/omap/prcm.c
425
ireg = prcm_imask_addr[reg];
sys/arch/armv7/omap/prcm.c
426
fmask = prcm_fmask_mask[reg];
sys/arch/armv7/omap/prcm.c
427
imask = prcm_imask_mask[reg];
sys/arch/armv7/omap/ti_iic.c
110
#define I2C_READ_REG(sc, reg) \
sys/arch/armv7/omap/ti_iic.c
111
bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, (reg))
sys/arch/armv7/omap/ti_iic.c
114
#define I2C_WRITE_REG(sc, reg, val) \
sys/arch/armv7/omap/ti_iic.c
115
bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/omap/ti_iic.c
597
uint32_t reg[1];
sys/arch/armv7/omap/ti_iic.c
602
memset(reg, 0, sizeof(reg));
sys/arch/armv7/omap/ti_iic.c
609
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/arch/armv7/omap/ti_iic.c
614
ia.ia_addr = bemtoh32(®[0]);
sys/arch/armv7/stand/efiboot/efiboot.c
383
uint32_t reg[4];
sys/arch/armv7/stand/efiboot/efiboot.c
456
reg[0] = htobe32(base);
sys/arch/armv7/stand/efiboot/efiboot.c
458
reg[1] = reg[0];
sys/arch/armv7/stand/efiboot/efiboot.c
459
reg[0] = htobe32(base >> 32);
sys/arch/armv7/stand/efiboot/efiboot.c
462
reg[acells] = htobe32(size);
sys/arch/armv7/stand/efiboot/efiboot.c
464
reg[acells + 1] = reg[acells];
sys/arch/armv7/stand/efiboot/efiboot.c
465
reg[acells] = htobe32(size >> 32);
sys/arch/armv7/stand/efiboot/efiboot.c
475
fdt_node_add_property(child, "reg", reg, (acells + scells) * 4);
sys/arch/armv7/sunxi/sxie.c
294
uint32_t reg;
sys/arch/armv7/sunxi/sxie.c
306
reg = SXIREAD4(sc, SXIE_MACA0);
sys/arch/armv7/sunxi/sxie.c
307
if (reg != 0) {
sys/arch/armv7/sunxi/sxie.c
308
sc->sc_ac.ac_enaddr[3] = reg >> 16 & 0xff;
sys/arch/armv7/sunxi/sxie.c
309
sc->sc_ac.ac_enaddr[4] = reg >> 8 & 0xff;
sys/arch/armv7/sunxi/sxie.c
310
sc->sc_ac.ac_enaddr[5] = reg & 0xff;
sys/arch/armv7/sunxi/sxie.c
311
reg = SXIREAD4(sc, SXIE_MACA1);
sys/arch/armv7/sunxi/sxie.c
312
sc->sc_ac.ac_enaddr[0] = reg >> 16 & 0xff;
sys/arch/armv7/sunxi/sxie.c
313
sc->sc_ac.ac_enaddr[1] = reg >> 8 & 0xff;
sys/arch/armv7/sunxi/sxie.c
314
sc->sc_ac.ac_enaddr[2] = reg & 0xff;
sys/arch/armv7/sunxi/sxie.c
319
reg = bus_space_read_4(sc->sc_iot, sc->sc_sid_ioh, 0x0);
sys/arch/armv7/sunxi/sxie.c
321
if (!have_mac && reg != 0) {
sys/arch/armv7/sunxi/sxie.c
323
sc->sc_ac.ac_enaddr[1] = reg & 0xff;
sys/arch/armv7/sunxi/sxie.c
324
reg = bus_space_read_4(sc->sc_iot, sc->sc_sid_ioh, 0x0c);
sys/arch/armv7/sunxi/sxie.c
325
sc->sc_ac.ac_enaddr[2] = reg >> 24 & 0xff;
sys/arch/armv7/sunxi/sxie.c
326
sc->sc_ac.ac_enaddr[3] = reg >> 16 & 0xff;
sys/arch/armv7/sunxi/sxie.c
327
sc->sc_ac.ac_enaddr[4] = reg >> 8 & 0xff;
sys/arch/armv7/sunxi/sxie.c
328
sc->sc_ac.ac_enaddr[5] = reg & 0xff;
sys/arch/armv7/sunxi/sxie.c
578
uint32_t fbc, reg;
sys/arch/armv7/sunxi/sxie.c
594
reg = SXIREAD4(sc, SXIE_RXIO);
sys/arch/armv7/sunxi/sxie.c
595
if (reg != 0x0143414d) { /* invalid packet */
sys/arch/armv7/sunxi/sxie.c
605
reg = SXIREAD4(sc, SXIE_RXIO);
sys/arch/armv7/sunxi/sxie.c
606
pktstat = (uint16_t)reg >> 16;
sys/arch/armv7/sunxi/sxie.c
607
pktlen = (int16_t)reg; /* length of useful data */
sys/arch/armv7/sunxi/sxie.c
690
sxie_miibus_readreg(struct device *dev, int phy, int reg)
sys/arch/armv7/sunxi/sxie.c
695
SXIWRITE4(sc, SXIE_MACMADR, phy << 8 | reg);
sys/arch/armv7/sunxi/sxie.c
712
sxie_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/arch/armv7/sunxi/sxie.c
717
SXIWRITE4(sc, SXIE_MACMADR, phy << 8 | reg);
sys/arch/armv7/vexpress/pciecam.c
292
pciecam_conf_read(void *v, pcitag_t tag, int reg)
sys/arch/armv7/vexpress/pciecam.c
299
return HREAD4(sc, PCIE_ADDR_OFFSET(bus, dev, fn, reg & ~0x3));
sys/arch/armv7/vexpress/pciecam.c
303
pciecam_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
sys/arch/armv7/vexpress/pciecam.c
310
HWRITE4(sc, PCIE_ADDR_OFFSET(bus, dev, fn, reg & ~0x3), data);
sys/arch/armv7/vexpress/pciecam.c
390
pcireg_t reg;
sys/arch/armv7/vexpress/pciecam.c
401
&off, ®) == 0)
sys/arch/armv7/vexpress/pciecam.c
404
if (reg & PCI_MSI_MC_C64) {
sys/arch/armv7/vexpress/pciecam.c
418
off, reg | PCI_MSI_MC_MSIE);
sys/arch/armv7/vexpress/pciecam.c
421
uint32_t reg[4];
sys/arch/armv7/vexpress/pciecam.c
425
reg[0] = bus << 16 | dev << 11 | fn << 8;
sys/arch/armv7/vexpress/pciecam.c
426
reg[1] = reg[2] = 0;
sys/arch/armv7/vexpress/pciecam.c
427
reg[3] = ih->ih_intrpin;
sys/arch/armv7/vexpress/pciecam.c
429
cookie = arm_intr_establish_fdt_imap_cpu(sc->sc_node, reg,
sys/arch/armv7/vexpress/pciecam.c
43
#define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
sys/arch/armv7/vexpress/pciecam.c
430
sizeof(reg), level, ci, func, arg, name);
sys/arch/armv7/vexpress/pciecam.c
47
((reg) & PCIE_REG_MASK))
sys/arch/armv7/vexpress/pciecam.c
49
#define HREAD4(sc, reg) \
sys/arch/armv7/vexpress/pciecam.c
50
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/armv7/vexpress/pciecam.c
51
#define HWRITE4(sc, reg, val) \
sys/arch/armv7/vexpress/pciecam.c
52
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/armv7/vexpress/pciecam.c
53
#define HSET4(sc, reg, bits) \
sys/arch/armv7/vexpress/pciecam.c
54
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/armv7/vexpress/pciecam.c
55
#define HCLR4(sc, reg, bits) \
sys/arch/armv7/vexpress/pciecam.c
56
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/armv7/xilinx/zqclock.c
156
uint32_t reg, val;
sys/arch/armv7/xilinx/zqclock.c
160
reg = SLCR_ARM_PLL_CTRL;
sys/arch/armv7/xilinx/zqclock.c
163
reg = SLCR_DDR_PLL_CTRL;
sys/arch/armv7/xilinx/zqclock.c
166
reg = SLCR_IO_PLL_CTRL;
sys/arch/armv7/xilinx/zqclock.c
170
val = zynq_slcr_read(sc->sc_rm, reg);
sys/arch/armv7/xilinx/zqreset.c
101
return regmap_read_4(rm, reg);
sys/arch/armv7/xilinx/zqreset.c
105
zynq_slcr_write(struct regmap *rm, uint32_t reg, uint32_t val)
sys/arch/armv7/xilinx/zqreset.c
110
regmap_write_4(rm, reg, val);
sys/arch/armv7/xilinx/zqreset.c
99
zynq_slcr_read(struct regmap *rm, uint32_t reg)
sys/arch/hppa/dev/apic.c
128
pcireg_t reg;
sys/arch/hppa/dev/apic.c
131
reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
sys/arch/hppa/dev/apic.c
133
printf(" pin=%d line=%d ", PCI_INTERRUPT_PIN(reg),
sys/arch/hppa/dev/apic.c
134
PCI_INTERRUPT_LINE(reg));
sys/arch/hppa/dev/apic.c
136
line = PCI_INTERRUPT_LINE(reg);
sys/arch/hppa/dev/apic.c
80
void apic_write(volatile struct elroy_regs *r, u_int32_t reg,
sys/arch/hppa/dev/apic.c
82
u_int32_t apic_read(volatile struct elroy_regs *r, u_int32_t reg);
sys/arch/hppa/dev/apic.c
85
apic_write(volatile struct elroy_regs *r, u_int32_t reg, u_int32_t val)
sys/arch/hppa/dev/apic.c
87
elroy_write32(&r->apic_addr, htole32(reg));
sys/arch/hppa/dev/apic.c
93
apic_read(volatile struct elroy_regs *r, u_int32_t reg)
sys/arch/hppa/dev/apic.c
95
elroy_write32(&r->apic_addr, htole32(reg));
sys/arch/hppa/dev/dino.c
328
dino_conf_read(void *v, pcitag_t tag, int reg)
sys/arch/hppa/dev/dino.c
339
r->pci_addr = tag | reg;
sys/arch/hppa/dev/dino.c
349
dino_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
sys/arch/hppa/dev/dino.c
360
r->pci_addr = tag | reg;
sys/arch/hppa/dev/dino.c
378
pcireg_t reg;
sys/arch/hppa/dev/dino.c
380
reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
sys/arch/hppa/dev/dino.c
382
if (PCI_INTERRUPT_LINE(reg) == 0xff)
sys/arch/hppa/dev/dino.c
385
*ihp = PCI_INTERRUPT_LINE(reg) + 1;
sys/arch/hppa/dev/dino.c
458
u_int32_t reg;
sys/arch/hppa/dev/dino.c
464
reg = sc->io_shadow;
sys/arch/hppa/dev/dino.c
465
reg |= 1 << ((bpa >> 23) & 0x1f);
sys/arch/hppa/dev/dino.c
466
if (reg & 0x80000001) {
sys/arch/hppa/dev/dino.c
473
if (reg != sc->io_shadow) {
sys/arch/hppa/dev/dino.c
479
r->io_addr_en |= reg;
sys/arch/hppa/dev/dino.c
480
sc->io_shadow = reg;
sys/arch/hppa/dev/dino.c
549
u_int32_t reg;
sys/arch/hppa/dev/dino.c
555
reg = sc->io_shadow;
sys/arch/hppa/dev/dino.c
556
reg |= 1 << ((*addrp >> 23) & 0x1f);
sys/arch/hppa/dev/dino.c
557
if (reg & 0x80000001) {
sys/arch/hppa/dev/dino.c
563
r->io_addr_en |= reg;
sys/arch/hppa/dev/dino.c
564
sc->io_shadow = reg;
sys/arch/hppa/dev/elroy.c
250
elroy_conf_read(void *v, pcitag_t tag, int reg)
sys/arch/hppa/dev/elroy.c
268
elroy_write32(&r->pci_conf_addr, htole32(tag | reg));
sys/arch/hppa/dev/elroy.c
285
elroy_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
sys/arch/hppa/dev/elroy.c
308
elroy_write32(&r->pci_conf_addr, htole32(tag | reg));
sys/arch/hppa/dev/elroy.c
66
pcireg_t elroy_conf_read(void *v, pcitag_t tag, int reg);
sys/arch/hppa/dev/elroy.c
67
void elroy_conf_write(void *v, pcitag_t tag, int reg,
sys/arch/hppa/dev/siop_sgc.c
146
u_int16_t reg;
sys/arch/hppa/dev/siop_sgc.c
148
reg = siop_sgc_r1(v, h, SIOP_SIST0);
sys/arch/hppa/dev/siop_sgc.c
149
reg |= siop_sgc_r1(v, h, SIOP_SIST1) << 8;
sys/arch/hppa/dev/siop_sgc.c
150
return reg;
sys/arch/hppa/dev/ssio.c
176
pcireg_t reg;
sys/arch/hppa/dev/ssio.c
220
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, SSIO_PCI_DMA_RC2);
sys/arch/hppa/dev/ssio.c
221
reg &= ~(SSIO_PCI_INT_TC1_MASK << SSIO_PCI_INT_TC1_SHIFT);
sys/arch/hppa/dev/ssio.c
222
reg |= 0x22 << SSIO_PCI_INT_TC1_SHIFT;
sys/arch/hppa/dev/ssio.c
223
pci_conf_write(pa->pa_pc, pa->pa_tag, SSIO_PCI_DMA_RC2, reg);
sys/arch/hppa/dev/ssio.c
225
reg = 0;
sys/arch/hppa/dev/ssio.c
226
reg |= 0x34 << SSIO_PCI_INT_RC1_SHIFT; /* SP1, SP2 */
sys/arch/hppa/dev/ssio.c
227
reg |= 0x07 << SSIO_PCI_INT_RC2_SHIFT; /* PP */
sys/arch/hppa/dev/ssio.c
228
reg |= 0x05 << SSIO_PCI_INT_RC3_SHIFT; /* IDE1 */
sys/arch/hppa/dev/ssio.c
229
pci_conf_write(pa->pa_pc, pa->pa_tag, SSIO_PCI_INT_TC2, reg);
sys/arch/hppa/dev/ssio.c
231
reg = 0;
sys/arch/hppa/dev/ssio.c
232
reg |= 0x10 << SSIO_PCI_INT_RC5_SHIFT; /* INTD# (USB) */
sys/arch/hppa/dev/ssio.c
233
pci_conf_write(pa->pa_pc, pa->pa_tag, SSIO_PCI_INT_RC4, reg);
sys/arch/hppa/dev/ssio.c
288
reg = pci_conf_read(pa->pa_pc, tag, PCI_CBMEM);
sys/arch/hppa/dev/ssio.c
291
PAGE0->mem_kbd.pz_hpa == reg)
sys/arch/hppa/gsc/harmony.c
441
u_int32_t reg;
sys/arch/hppa/gsc/harmony.c
451
reg = READ_REG(sc, HARMONY_DSTATUS);
sys/arch/hppa/gsc/harmony.c
452
if ((reg & (DSTATUS_PC | DSTATUS_RC)) == 0)
sys/arch/hppa/gsc/harmony.c
485
reg = READ_REG(sc, HARMONY_CNTL);
sys/arch/hppa/gsc/harmony.c
486
if ((reg & CNTL_C) == 0)
sys/arch/hppa/gsc/harmony.c
495
reg = READ_REG(sc, HARMONY_CNTL);
sys/arch/hppa/gsc/harmony.c
496
if ((reg & CNTL_C) == 0)
sys/arch/hppa/gsc/harmonyvar.h
108
#define READ_REG(sc, reg) \
sys/arch/hppa/gsc/harmonyvar.h
109
bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, (reg))
sys/arch/hppa/gsc/harmonyvar.h
110
#define WRITE_REG(sc, reg, val) \
sys/arch/hppa/gsc/harmonyvar.h
111
bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, (reg), (val))
sys/arch/hppa/gsc/harmonyvar.h
112
#define SYNC_REG(sc, reg, flags) \
sys/arch/hppa/gsc/harmonyvar.h
113
bus_space_barrier((sc)->sc_bt, (sc)->sc_bh, (reg), sizeof(u_int32_t), \
sys/arch/hppa/gsc/siop_gsc.c
142
u_int16_t reg;
sys/arch/hppa/gsc/siop_gsc.c
144
reg = siop_gsc_r1(v, h, SIOP_SIST0);
sys/arch/hppa/gsc/siop_gsc.c
145
reg |= siop_gsc_r1(v, h, SIOP_SIST1) << 8;
sys/arch/hppa/gsc/siop_gsc.c
146
return reg;
sys/arch/hppa/hppa/autoconf.c
381
int reg;
sys/arch/hppa/hppa/autoconf.c
383
for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) {
sys/arch/hppa/hppa/autoconf.c
384
addr = pci_conf_read(pa->pa_pc, pa->pa_tag, reg);
sys/arch/hppa/hppa/process_machdep.c
112
process_write_regs(struct proc *p, struct reg *regs)
sys/arch/hppa/hppa/process_machdep.c
40
process_read_regs(struct proc *p, struct reg *regs)
sys/arch/hppa/include/asm.h
100
fr17 .reg %fr17
sys/arch/hppa/include/asm.h
101
fr18 .reg %fr18
sys/arch/hppa/include/asm.h
102
fr19 .reg %fr19
sys/arch/hppa/include/asm.h
103
fr20 .reg %fr20
sys/arch/hppa/include/asm.h
104
fr21 .reg %fr21
sys/arch/hppa/include/asm.h
105
fr22 .reg %fr22
sys/arch/hppa/include/asm.h
106
fr23 .reg %fr23
sys/arch/hppa/include/asm.h
107
fr24 .reg %fr24
sys/arch/hppa/include/asm.h
108
fr25 .reg %fr25
sys/arch/hppa/include/asm.h
109
fr26 .reg %fr26
sys/arch/hppa/include/asm.h
110
fr27 .reg %fr27
sys/arch/hppa/include/asm.h
111
fr28 .reg %fr28
sys/arch/hppa/include/asm.h
112
fr29 .reg %fr29
sys/arch/hppa/include/asm.h
113
fr30 .reg %fr30
sys/arch/hppa/include/asm.h
114
fr31 .reg %fr31
sys/arch/hppa/include/asm.h
119
cr0 .reg %cr0
sys/arch/hppa/include/asm.h
120
cr8 .reg %cr8
sys/arch/hppa/include/asm.h
121
cr9 .reg %cr9
sys/arch/hppa/include/asm.h
122
cr10 .reg %cr10
sys/arch/hppa/include/asm.h
123
cr11 .reg %cr11
sys/arch/hppa/include/asm.h
124
cr12 .reg %cr12
sys/arch/hppa/include/asm.h
125
cr13 .reg %cr13
sys/arch/hppa/include/asm.h
126
cr14 .reg %cr14
sys/arch/hppa/include/asm.h
127
cr15 .reg %cr15
sys/arch/hppa/include/asm.h
128
cr16 .reg %cr16
sys/arch/hppa/include/asm.h
129
cr17 .reg %cr17
sys/arch/hppa/include/asm.h
130
cr18 .reg %cr18
sys/arch/hppa/include/asm.h
131
cr19 .reg %cr19
sys/arch/hppa/include/asm.h
132
cr20 .reg %cr20
sys/arch/hppa/include/asm.h
133
cr21 .reg %cr21
sys/arch/hppa/include/asm.h
134
cr22 .reg %cr22
sys/arch/hppa/include/asm.h
135
cr23 .reg %cr23
sys/arch/hppa/include/asm.h
136
cr24 .reg %cr24
sys/arch/hppa/include/asm.h
137
cr25 .reg %cr25
sys/arch/hppa/include/asm.h
138
cr26 .reg %cr26
sys/arch/hppa/include/asm.h
139
cr27 .reg %cr27
sys/arch/hppa/include/asm.h
140
cr28 .reg %cr28
sys/arch/hppa/include/asm.h
141
cr29 .reg %cr29
sys/arch/hppa/include/asm.h
142
cr30 .reg %cr30
sys/arch/hppa/include/asm.h
143
cr31 .reg %cr31
sys/arch/hppa/include/asm.h
145
rctr .reg %cr0
sys/arch/hppa/include/asm.h
146
pidr1 .reg %cr8
sys/arch/hppa/include/asm.h
147
pidr2 .reg %cr9
sys/arch/hppa/include/asm.h
148
ccr .reg %cr10
sys/arch/hppa/include/asm.h
149
sar .reg %cr11
sys/arch/hppa/include/asm.h
150
pidr3 .reg %cr12
sys/arch/hppa/include/asm.h
151
pidr4 .reg %cr13
sys/arch/hppa/include/asm.h
152
iva .reg %cr14
sys/arch/hppa/include/asm.h
153
eiem .reg %cr15
sys/arch/hppa/include/asm.h
154
itmr .reg %cr16
sys/arch/hppa/include/asm.h
155
pcsq .reg %cr17
sys/arch/hppa/include/asm.h
156
pcoq .reg %cr18
sys/arch/hppa/include/asm.h
157
iir .reg %cr19
sys/arch/hppa/include/asm.h
158
isr .reg %cr20
sys/arch/hppa/include/asm.h
159
ior .reg %cr21
sys/arch/hppa/include/asm.h
160
ipsw .reg %cr22
sys/arch/hppa/include/asm.h
161
eirr .reg %cr23
sys/arch/hppa/include/asm.h
162
tr0 .reg %cr24
sys/arch/hppa/include/asm.h
163
vtop .reg %cr25
sys/arch/hppa/include/asm.h
164
tr1 .reg %cr25
sys/arch/hppa/include/asm.h
165
tr2 .reg %cr26
sys/arch/hppa/include/asm.h
166
tr3 .reg %cr27
sys/arch/hppa/include/asm.h
167
tr4 .reg %cr28
sys/arch/hppa/include/asm.h
168
tr5 .reg %cr29
sys/arch/hppa/include/asm.h
169
tr6 .reg %cr30
sys/arch/hppa/include/asm.h
170
tr7 .reg %cr31
sys/arch/hppa/include/asm.h
175
rp .reg %r2
sys/arch/hppa/include/asm.h
176
arg3 .reg %r23
sys/arch/hppa/include/asm.h
177
arg2 .reg %r24
sys/arch/hppa/include/asm.h
178
arg1 .reg %r25
sys/arch/hppa/include/asm.h
179
arg0 .reg %r26
sys/arch/hppa/include/asm.h
180
dp .reg %r27
sys/arch/hppa/include/asm.h
181
ret0 .reg %r28
sys/arch/hppa/include/asm.h
182
ret1 .reg %r29
sys/arch/hppa/include/asm.h
183
sl .reg %r29
sys/arch/hppa/include/asm.h
184
sp .reg %r30
sys/arch/hppa/include/asm.h
189
t1 .reg %r22
sys/arch/hppa/include/asm.h
190
t2 .reg %r21
sys/arch/hppa/include/asm.h
191
t3 .reg %r20
sys/arch/hppa/include/asm.h
192
t4 .reg %r19
sys/arch/hppa/include/asm.h
197
ts1 .reg %sr2
sys/arch/hppa/include/asm.h
202
sret .reg %sr1 ; return value
sys/arch/hppa/include/asm.h
203
sarg .reg %sr1 ; argument
sys/arch/hppa/include/asm.h
208
farg0 .reg %fr5
sys/arch/hppa/include/asm.h
209
farg1 .reg %fr6
sys/arch/hppa/include/asm.h
210
farg2 .reg %fr7
sys/arch/hppa/include/asm.h
211
farg3 .reg %fr8
sys/arch/hppa/include/asm.h
212
fret .reg %fr4
sys/arch/hppa/include/asm.h
217
tf1 .reg %fr11
sys/arch/hppa/include/asm.h
218
tf2 .reg %fr10
sys/arch/hppa/include/asm.h
219
tf3 .reg %fr9
sys/arch/hppa/include/asm.h
220
tf4 .reg %fr8
sys/arch/hppa/include/asm.h
35
r0 .reg %r0
sys/arch/hppa/include/asm.h
36
r1 .reg %r1
sys/arch/hppa/include/asm.h
37
r2 .reg %r2
sys/arch/hppa/include/asm.h
38
r3 .reg %r3
sys/arch/hppa/include/asm.h
39
r4 .reg %r4
sys/arch/hppa/include/asm.h
40
r5 .reg %r5
sys/arch/hppa/include/asm.h
41
r6 .reg %r6
sys/arch/hppa/include/asm.h
42
r7 .reg %r7
sys/arch/hppa/include/asm.h
43
r8 .reg %r8
sys/arch/hppa/include/asm.h
44
r9 .reg %r9
sys/arch/hppa/include/asm.h
45
r10 .reg %r10
sys/arch/hppa/include/asm.h
46
r11 .reg %r11
sys/arch/hppa/include/asm.h
47
r12 .reg %r12
sys/arch/hppa/include/asm.h
48
r13 .reg %r13
sys/arch/hppa/include/asm.h
49
r14 .reg %r14
sys/arch/hppa/include/asm.h
50
r15 .reg %r15
sys/arch/hppa/include/asm.h
51
r16 .reg %r16
sys/arch/hppa/include/asm.h
52
r17 .reg %r17
sys/arch/hppa/include/asm.h
53
r18 .reg %r18
sys/arch/hppa/include/asm.h
54
r19 .reg %r19
sys/arch/hppa/include/asm.h
55
r20 .reg %r20
sys/arch/hppa/include/asm.h
56
r21 .reg %r21
sys/arch/hppa/include/asm.h
57
r22 .reg %r22
sys/arch/hppa/include/asm.h
58
r23 .reg %r23
sys/arch/hppa/include/asm.h
59
r24 .reg %r24
sys/arch/hppa/include/asm.h
60
r25 .reg %r25
sys/arch/hppa/include/asm.h
61
r26 .reg %r26
sys/arch/hppa/include/asm.h
62
r27 .reg %r27
sys/arch/hppa/include/asm.h
63
r28 .reg %r28
sys/arch/hppa/include/asm.h
64
r29 .reg %r29
sys/arch/hppa/include/asm.h
65
r30 .reg %r30
sys/arch/hppa/include/asm.h
66
r31 .reg %r31
sys/arch/hppa/include/asm.h
71
sr0 .reg %sr0
sys/arch/hppa/include/asm.h
72
sr1 .reg %sr1
sys/arch/hppa/include/asm.h
73
sr2 .reg %sr2
sys/arch/hppa/include/asm.h
74
sr3 .reg %sr3
sys/arch/hppa/include/asm.h
75
sr4 .reg %sr4
sys/arch/hppa/include/asm.h
76
sr5 .reg %sr5
sys/arch/hppa/include/asm.h
77
sr6 .reg %sr6
sys/arch/hppa/include/asm.h
78
sr7 .reg %sr7
sys/arch/hppa/include/asm.h
83
fr0 .reg %fr0
sys/arch/hppa/include/asm.h
84
fr1 .reg %fr1
sys/arch/hppa/include/asm.h
85
fr2 .reg %fr2
sys/arch/hppa/include/asm.h
86
fr3 .reg %fr3
sys/arch/hppa/include/asm.h
87
fr4 .reg %fr4
sys/arch/hppa/include/asm.h
88
fr5 .reg %fr5
sys/arch/hppa/include/asm.h
89
fr6 .reg %fr6
sys/arch/hppa/include/asm.h
90
fr7 .reg %fr7
sys/arch/hppa/include/asm.h
91
fr8 .reg %fr8
sys/arch/hppa/include/asm.h
92
fr9 .reg %fr9
sys/arch/hppa/include/asm.h
93
fr10 .reg %fr10
sys/arch/hppa/include/asm.h
94
fr11 .reg %fr11
sys/arch/hppa/include/asm.h
95
fr12 .reg %fr12
sys/arch/hppa/include/asm.h
96
fr13 .reg %fr13
sys/arch/hppa/include/asm.h
97
fr14 .reg %fr14
sys/arch/hppa/include/asm.h
98
fr15 .reg %fr15
sys/arch/hppa/include/asm.h
99
fr16 .reg %fr16
sys/arch/hppa/stand/libsa/cmd_hppa.c
895
dino_conf_read(u_int hpa, int dev, int fn, u_int reg)
sys/arch/hppa/stand/libsa/cmd_hppa.c
901
addr = (dev << 11) | (fn << 8) | reg;
sys/arch/hppa/stand/libsa/cmd_hppa.c
913
elroy_conf_read(u_int hpa, int dev, int fn, u_int reg)
sys/arch/hppa/stand/libsa/cmd_hppa.c
919
addr = (dev << 11) | (fn << 8) | reg;
sys/arch/i386/i386/cpu.c
499
u_int64_t reg;
sys/arch/i386/i386/cpu.c
512
reg = PATENTRY(0, PAT_WB) | PATENTRY(1, PAT_WC) |
sys/arch/i386/i386/cpu.c
517
wrmsr(MSR_CR_PAT, reg);
sys/arch/i386/i386/k6_mem.c
108
reg = rdmsr(UWCCR);
sys/arch/i386/i386/k6_mem.c
110
u_int32_t one = (reg & (0xffffffff << (32 * d))) >> (32 * d);
sys/arch/i386/i386/k6_mem.c
127
u_int64_t reg;
sys/arch/i386/i386/k6_mem.c
166
reg = rdmsr(UWCCR);
sys/arch/i386/i386/k6_mem.c
167
reg &= ~(0xffffffff << (32 * d));
sys/arch/i386/i386/k6_mem.c
168
reg |= mtrr << (32 * d);
sys/arch/i386/i386/k6_mem.c
169
wrmsr(UWCCR, reg);
sys/arch/i386/i386/k6_mem.c
182
u_int64_t reg;
sys/arch/i386/i386/k6_mem.c
192
reg = rdmsr(UWCCR);
sys/arch/i386/i386/k6_mem.c
193
reg &= ~(0xffffffff << (32 * d));
sys/arch/i386/i386/k6_mem.c
194
reg |= mtrr << (32 * d);
sys/arch/i386/i386/k6_mem.c
195
wrmsr(UWCCR, reg);
sys/arch/i386/i386/k6_mem.c
50
#define k6_reg_get(reg, addr, mask, wc, uc) do { \
sys/arch/i386/i386/k6_mem.c
51
addr = (reg) & 0xfffe0000; \
sys/arch/i386/i386/k6_mem.c
52
mask = ((reg) & 0x1fffc) >> 2; \
sys/arch/i386/i386/k6_mem.c
53
wc = ((reg) & 0x2) >> 1; \
sys/arch/i386/i386/k6_mem.c
54
uc = (reg) & 0x1; \
sys/arch/i386/i386/k6_mem.c
97
u_int64_t reg;
sys/arch/i386/i386/machdep.c
306
cyrix_read_reg(u_char reg)
sys/arch/i386/i386/machdep.c
308
outb(0x22, reg);
sys/arch/i386/i386/machdep.c
313
cyrix_write_reg(u_char reg, u_char data)
sys/arch/i386/i386/machdep.c
315
outb(0x22, reg);
sys/arch/i386/i386/mpbios_intr_fixup.c
103
reg = pci_conf_read(pc, tag, NFORCE4_PNPIRQ3);
sys/arch/i386/i386/mpbios_intr_fixup.c
104
pin = (reg & NFORCE4_USB1_MASK) >> NFORCE4_USB1_SHIFT;
sys/arch/i386/i386/mpbios_intr_fixup.c
107
pin = (reg & NFORCE4_LAN_MASK) >> NFORCE4_LAN_SHIFT;
sys/arch/i386/i386/mpbios_intr_fixup.c
119
pcireg_t reg;
sys/arch/i386/i386/mpbios_intr_fixup.c
124
reg = pci_conf_read(pc, tag, NFORCE4_PNPIRQ2);
sys/arch/i386/i386/mpbios_intr_fixup.c
125
pin = (reg & NFORCE4_SATA1_MASK) >> NFORCE4_SATA1_SHIFT;
sys/arch/i386/i386/mpbios_intr_fixup.c
128
pin = (reg & NFORCE4_SATA2_MASK) >> NFORCE4_SATA2_SHIFT;
sys/arch/i386/i386/mpbios_intr_fixup.c
87
pcireg_t reg;
sys/arch/i386/i386/mpbios_intr_fixup.c
92
reg = pci_conf_read(pc, tag, NFORCE4_PNPIRQ2);
sys/arch/i386/i386/mpbios_intr_fixup.c
93
pin = (reg & NFORCE4_USB2_MASK) >> NFORCE4_USB2_SHIFT;
sys/arch/i386/i386/mpbios_intr_fixup.c
96
pin = (reg & NFORCE4_SATA1_MASK) >> NFORCE4_SATA1_SHIFT;
sys/arch/i386/i386/mpbios_intr_fixup.c
99
pin = (reg & NFORCE4_SATA2_MASK) >> NFORCE4_SATA2_SHIFT;
sys/arch/i386/i386/p4tcc.c
126
if (tcc[i].reg != 0) /* enable it */
sys/arch/i386/i386/p4tcc.c
127
msreg |= tcc[i].reg << 1 | 1 << 4;
sys/arch/i386/i386/p4tcc.c
49
u_short reg;
sys/arch/i386/i386/p4tcc.c
83
tcc[TCC_LEVELS - 1].reg = 2;
sys/arch/i386/i386/p4tcc.c
90
tcc[TCC_LEVELS - 1].reg = 3;
sys/arch/i386/i386/p4tcc.c
91
tcc[TCC_LEVELS - 2].reg = 3;
sys/arch/i386/i386/pctr.c
58
int i, num, reg;
sys/arch/i386/i386/pctr.c
61
reg = pctr_isamd ? MSR_K7_EVNTSEL0 : P6MSR_CTRSEL0;
sys/arch/i386/i386/pctr.c
63
st->pctr_fn[i] = rdmsr(reg + i);
sys/arch/i386/i386/process_machdep.c
139
process_read_regs(struct proc *p, struct reg *regs)
sys/arch/i386/i386/process_machdep.c
234
process_write_regs(struct proc *p, struct reg *regs)
sys/arch/i386/include/i82489var.h
44
i82489_readreg(int reg)
sys/arch/i386/include/i82489var.h
47
+ reg));
sys/arch/i386/include/i82489var.h
51
i82489_writereg(int reg, u_int32_t val)
sys/arch/i386/include/i82489var.h
53
*((volatile u_int32_t *)(((volatile u_int8_t *)local_apic) + reg)) =
sys/arch/i386/isa/clock.c
142
mc146818_read(void *sc, u_int reg)
sys/arch/i386/isa/clock.c
148
outb(IO_RTC, reg);
sys/arch/i386/isa/clock.c
157
mc146818_write(void *sc, u_int reg, u_int datum)
sys/arch/i386/isa/clock.c
162
outb(IO_RTC, reg);
sys/arch/i386/pci/ali1543.c
144
#define ALI1543_INTR_PIRQ_IRQ(reg, clink) \
sys/arch/i386/pci/ali1543.c
145
(((reg) >> ((clink)*4)) & 0x0f)
sys/arch/i386/pci/ali1543.c
146
#define ALI1543_PIRQ(reg, clink) \
sys/arch/i386/pci/ali1543.c
147
ali1543_intr_shuffle_get[ALI1543_INTR_PIRQ_IRQ((reg), (clink))]
sys/arch/i386/pci/ali1543.c
180
pcireg_t reg;
sys/arch/i386/pci/ali1543.c
186
reg = pci_conf_read(ph->ph_pc, ph->ph_tag, ALI1543_INTR_CFG_REG);
sys/arch/i386/pci/ali1543.c
188
printf("ali1543: PIRQ reg 0x%08x\n", reg); /* XXX debug */
sys/arch/i386/pci/ali1543.c
190
val = ALI1543_PIRQ(reg, clink);
sys/arch/i386/pci/ali1543.c
202
pcireg_t reg;
sys/arch/i386/pci/ali1543.c
207
reg = pci_conf_read(ph->ph_pc, ph->ph_tag, ALI1543_INTR_CFG_REG);
sys/arch/i386/pci/ali1543.c
210
reg &= ~(0x0f << shift);
sys/arch/i386/pci/ali1543.c
211
reg |= (ali1543_intr_shuffle_set[irq] << shift);
sys/arch/i386/pci/ali1543.c
212
pci_conf_write(ph->ph_pc, ph->ph_tag, ALI1543_INTR_CFG_REG, reg);
sys/arch/i386/pci/amd756.c
138
pcireg_t reg;
sys/arch/i386/pci/amd756.c
144
reg = AMD756_GET_PIIRQSEL(ph);
sys/arch/i386/pci/amd756.c
145
val = (reg >> (4*clink)) & 0x0f;
sys/arch/i386/pci/amd756.c
157
pcireg_t reg;
sys/arch/i386/pci/amd756.c
162
reg = AMD756_GET_PIIRQSEL(ph);
sys/arch/i386/pci/amd756.c
164
reg &= ~(0x000f << (4*clink));
sys/arch/i386/pci/amd756.c
165
reg |= irq << (4*clink);
sys/arch/i386/pci/amd756.c
166
AMD756_SET_PIIRQSEL(ph, reg);
sys/arch/i386/pci/amd756.c
176
pcireg_t reg;
sys/arch/i386/pci/amd756.c
184
reg = AMD756_GET_EDGESEL(ph);
sys/arch/i386/pci/amd756.c
185
if (reg & (1 << i))
sys/arch/i386/pci/amd756.c
201
pcireg_t reg;
sys/arch/i386/pci/amd756.c
209
reg = AMD756_GET_PIIRQSEL(ph);
sys/arch/i386/pci/amd756.c
211
reg &= ~(1 << (4*i));
sys/arch/i386/pci/amd756.c
213
reg |= 1 << (4*i);
sys/arch/i386/pci/amd756.c
214
AMD756_SET_PIIRQSEL(ph, reg);
sys/arch/i386/pci/geodesc.c
100
printf(": unable to map registers at 0x%x\n", reg);
sys/arch/i386/pci/geodesc.c
104
if (cba != reg) {
sys/arch/i386/pci/geodesc.c
105
printf(": cba mismatch: cba 0x%x != reg 0x%x\n", cba, reg);
sys/arch/i386/pci/geodesc.c
93
pcireg_t reg;
sys/arch/i386/pci/geodesc.c
96
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, SC1100_F5_SCRATCHPAD);
sys/arch/i386/pci/geodesc.c
98
if (reg == 0 ||
sys/arch/i386/pci/geodesc.c
99
bus_space_map(sc->sc_iot, reg, 64, 0, &sc->sc_ioh)) {
sys/arch/i386/pci/gscpcib.c
155
int reg, shift;
sys/arch/i386/pci/gscpcib.c
158
reg = (pin < 32 ? GSCGPIO_GPDI0 : GSCGPIO_GPDI1);
sys/arch/i386/pci/gscpcib.c
160
data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);
sys/arch/i386/pci/gscpcib.c
169
int reg, shift;
sys/arch/i386/pci/gscpcib.c
172
reg = (pin < 32 ? GSCGPIO_GPDO0 : GSCGPIO_GPDO1);
sys/arch/i386/pci/gscpcib.c
174
data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);
sys/arch/i386/pci/gscpcib.c
180
bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data);
sys/arch/i386/pci/opti82c558.c
151
pcireg_t reg;
sys/arch/i386/pci/opti82c558.c
157
reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ);
sys/arch/i386/pci/opti82c558.c
158
val = VIPER_PIRQ(reg, clink);
sys/arch/i386/pci/opti82c558.c
169
pcireg_t reg;
sys/arch/i386/pci/opti82c558.c
174
reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ);
sys/arch/i386/pci/opti82c558.c
176
reg &= ~(VIPER_PIRQ_SELECT_MASK << shift);
sys/arch/i386/pci/opti82c558.c
177
reg |= (viper_pirq_encode[irq] << shift);
sys/arch/i386/pci/opti82c558.c
178
pci_conf_write(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ, reg);
sys/arch/i386/pci/opti82c558.c
187
pcireg_t reg;
sys/arch/i386/pci/opti82c558.c
195
reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ);
sys/arch/i386/pci/opti82c558.c
196
if ((reg >> (VIPER_CFG_TRIGGER_SHIFT + viper_pirq_encode[irq])) & 1)
sys/arch/i386/pci/opti82c558.c
209
pcireg_t reg;
sys/arch/i386/pci/opti82c558.c
216
reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ);
sys/arch/i386/pci/opti82c558.c
219
reg |= (1 << shift);
sys/arch/i386/pci/opti82c558.c
221
reg &= ~(1 << shift);
sys/arch/i386/pci/opti82c558.c
222
pci_conf_write(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ, reg);
sys/arch/i386/pci/opti82c558reg.h
65
#define VIPER_PIRQ(reg, x) (((reg) >> ((x) * VIPER_PIRQ_SELECT_SHIFT)) \
sys/arch/i386/pci/opti82c700.c
193
pcireg_t reg;
sys/arch/i386/pci/opti82c700.c
199
reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
sys/arch/i386/pci/opti82c700.c
200
val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
sys/arch/i386/pci/opti82c700.c
213
pcireg_t reg;
sys/arch/i386/pci/opti82c700.c
221
reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
sys/arch/i386/pci/opti82c700.c
222
reg &= ~(FIRESTAR_CFG_PIRQ_MASK << ofs);
sys/arch/i386/pci/opti82c700.c
223
reg |= (irq << ofs);
sys/arch/i386/pci/opti82c700.c
224
pci_conf_write(ph->ph_pc, ph->ph_tag, addrofs, reg);
sys/arch/i386/pci/opti82c700.c
234
pcireg_t reg;
sys/arch/i386/pci/opti82c700.c
248
reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
sys/arch/i386/pci/opti82c700.c
249
val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
sys/arch/i386/pci/opti82c700.c
252
val = ((reg >> ofs) >> FIRESTAR_TRIGGER_SHIFT) &
sys/arch/i386/pci/opti82c700.c
264
reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
sys/arch/i386/pci/opti82c700.c
265
val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
sys/arch/i386/pci/opti82c700.c
280
pcireg_t reg;
sys/arch/i386/pci/opti82c700.c
293
reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
sys/arch/i386/pci/opti82c700.c
294
val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
sys/arch/i386/pci/opti82c700.c
298
reg |= (FIRESTAR_TRIGGER_MASK <<
sys/arch/i386/pci/opti82c700.c
301
reg &= ~(FIRESTAR_TRIGGER_MASK <<
sys/arch/i386/pci/opti82c700.c
303
pci_conf_write(ph->ph_pc, ph->ph_tag, addrofs, reg);
sys/arch/i386/pci/opti82c700.c
313
reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
sys/arch/i386/pci/opti82c700.c
314
val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
sys/arch/i386/pci/pchb.c
112
#define AMD64HT_LDT_SEC_BUS_NUM(reg) (((reg) >> 8) & 0xff)
sys/arch/i386/pci/pchb.c
485
int reg;
sys/arch/i386/pci/pchb.c
487
reg = AMD64HT_LDT0_TYPE + i * 0x20;
sys/arch/i386/pci/pchb.c
488
type = pci_conf_read(pa->pa_pc, pa->pa_tag, reg);
sys/arch/i386/pci/pchb.c
493
reg = AMD64HT_LDT0_BUS + i * 0x20;
sys/arch/i386/pci/pchb.c
494
bus = pci_conf_read(pa->pa_pc, pa->pa_tag, reg);
sys/arch/i386/pci/pchb.c
81
#define PCISET_INTEL_BRIDGE_NUMBER(reg) (((reg) >> 8) & 0xff)
sys/arch/i386/pci/pchb.c
82
#define PCISET_INTEL_PCI_BUS_NUMBER(reg) (((reg) >> 16) & 0xff)
sys/arch/i386/pci/pci_bus_fixup.c
101
reg = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
sys/arch/i386/pci/pci_bus_fixup.c
102
if (PPB_BUSINFO_PRIMARY(reg) != bus) {
sys/arch/i386/pci/pci_bus_fixup.c
108
PPB_BUSINFO_PRIMARY(reg),
sys/arch/i386/pci/pci_bus_fixup.c
109
PPB_BUSINFO_SECONDARY(reg),
sys/arch/i386/pci/pci_bus_fixup.c
110
PPB_BUSINFO_SUBORDINATE(reg));
sys/arch/i386/pci/pci_bus_fixup.c
114
if (PPB_BUSINFO_SECONDARY(reg) <= bus) {
sys/arch/i386/pci/pci_bus_fixup.c
120
PPB_BUSINFO_PRIMARY(reg),
sys/arch/i386/pci/pci_bus_fixup.c
121
PPB_BUSINFO_SECONDARY(reg),
sys/arch/i386/pci/pci_bus_fixup.c
122
PPB_BUSINFO_SUBORDINATE(reg));
sys/arch/i386/pci/pci_bus_fixup.c
129
PPB_BUSINFO_SECONDARY(reg));
sys/arch/i386/pci/pci_bus_fixup.c
133
if (PPB_BUSINFO_SUBORDINATE(reg) < bus_sub) {
sys/arch/i386/pci/pci_bus_fixup.c
139
PPB_BUSINFO_PRIMARY(reg),
sys/arch/i386/pci/pci_bus_fixup.c
140
PPB_BUSINFO_SECONDARY(reg),
sys/arch/i386/pci/pci_bus_fixup.c
141
PPB_BUSINFO_SUBORDINATE(reg));
sys/arch/i386/pci/pci_bus_fixup.c
161
pcireg_t reg;
sys/arch/i386/pci/pci_bus_fixup.c
169
reg = pci_conf_read(pc, tag, PCI_ID_REG);
sys/arch/i386/pci/pci_bus_fixup.c
176
if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID)
sys/arch/i386/pci/pci_bus_fixup.c
179
if (PCI_VENDOR(reg) == 0)
sys/arch/i386/pci/pci_bus_fixup.c
182
qd = pci_lookup_quirkdata(PCI_VENDOR(reg), PCI_PRODUCT(reg));
sys/arch/i386/pci/pci_bus_fixup.c
184
reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
sys/arch/i386/pci/pci_bus_fixup.c
185
if (PCI_HDRTYPE_MULTIFN(reg) ||
sys/arch/i386/pci/pci_bus_fixup.c
194
reg = pci_conf_read(pc, tag, PCI_ID_REG);
sys/arch/i386/pci/pci_bus_fixup.c
197
if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID)
sys/arch/i386/pci/pci_bus_fixup.c
200
if (PCI_VENDOR(reg) == 0)
sys/arch/i386/pci/pci_bus_fixup.c
203
reg = pci_conf_read(pc, tag, PCI_CLASS_REG);
sys/arch/i386/pci/pci_bus_fixup.c
204
if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE &&
sys/arch/i386/pci/pci_bus_fixup.c
205
(PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI ||
sys/arch/i386/pci/pci_bus_fixup.c
206
PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) {
sys/arch/i386/pci/pci_bus_fixup.c
210
reg = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
sys/arch/i386/pci/pci_bus_fixup.c
211
reg &= 0xff000000;
sys/arch/i386/pci/pci_bus_fixup.c
212
reg |= bus | (bus_max << 8) | (0xff << 16);
sys/arch/i386/pci/pci_bus_fixup.c
213
pci_conf_write(pc, tag, PPB_REG_BUSINFO, reg);
sys/arch/i386/pci/pci_bus_fixup.c
219
reg &= 0xff000000;
sys/arch/i386/pci/pci_bus_fixup.c
220
reg |= bus | (bus_max << 8) | (bus_sub << 16);
sys/arch/i386/pci/pci_bus_fixup.c
221
pci_conf_write(pc, tag, PPB_REG_BUSINFO, reg);
sys/arch/i386/pci/pci_bus_fixup.c
54
pcireg_t reg;
sys/arch/i386/pci/pci_bus_fixup.c
62
reg = pci_conf_read(pc, tag, PCI_ID_REG);
sys/arch/i386/pci/pci_bus_fixup.c
69
if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID)
sys/arch/i386/pci/pci_bus_fixup.c
72
if (PCI_VENDOR(reg) == 0)
sys/arch/i386/pci/pci_bus_fixup.c
75
qd = pci_lookup_quirkdata(PCI_VENDOR(reg), PCI_PRODUCT(reg));
sys/arch/i386/pci/pci_bus_fixup.c
77
reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
sys/arch/i386/pci/pci_bus_fixup.c
78
if (PCI_HDRTYPE_MULTIFN(reg) ||
sys/arch/i386/pci/pci_bus_fixup.c
87
reg = pci_conf_read(pc, tag, PCI_ID_REG);
sys/arch/i386/pci/pci_bus_fixup.c
90
if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID)
sys/arch/i386/pci/pci_bus_fixup.c
93
if (PCI_VENDOR(reg) == 0)
sys/arch/i386/pci/pci_bus_fixup.c
96
reg = pci_conf_read(pc, tag, PCI_CLASS_REG);
sys/arch/i386/pci/pci_bus_fixup.c
97
if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE &&
sys/arch/i386/pci/pci_bus_fixup.c
98
(PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI ||
sys/arch/i386/pci/pci_bus_fixup.c
99
PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) {
sys/arch/i386/pci/pci_machdep.c
440
pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
sys/arch/i386/pci/pci_machdep.c
445
KASSERT((reg & 0x3) == 0);
sys/arch/i386/pci/pci_machdep.c
447
if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) {
sys/arch/i386/pci/pci_machdep.c
452
(tag.mode1 & 0x000ff00) << 4 | reg);
sys/arch/i386/pci/pci_machdep.c
460
outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg);
sys/arch/i386/pci/pci_machdep.c
467
data = inl(tag.mode2.port | reg);
sys/arch/i386/pci/pci_machdep.c
479
pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
sys/arch/i386/pci/pci_machdep.c
483
KASSERT((reg & 0x3) == 0);
sys/arch/i386/pci/pci_machdep.c
485
if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) {
sys/arch/i386/pci/pci_machdep.c
490
(tag.mode1 & 0x000ff00) << 4 | reg, data);
sys/arch/i386/pci/pci_machdep.c
498
outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg);
sys/arch/i386/pci/pci_machdep.c
505
outl(tag.mode2.port | reg, data);
sys/arch/i386/pci/pci_machdep.c
818
pcireg_t reg, addr;
sys/arch/i386/pci/pci_machdep.c
827
if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0)
sys/arch/i386/pci/pci_machdep.c
854
if (reg & PCI_MSI_MC_C64) {
sys/arch/i386/pci/pci_machdep.c
862
pci_conf_write(pc, tag, off, reg | PCI_MSI_MC_MSIE);
sys/arch/i386/pci/pci_machdep.c
894
pcireg_t reg;
sys/arch/i386/pci/pci_machdep.c
897
if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®))
sys/arch/i386/pci/pci_machdep.c
898
pci_conf_write(pc, tag, off, reg &= ~PCI_MSI_MC_MSIE);
sys/arch/i386/pci/pciide_machdep.c
158
uint64_t reg = 0;
sys/arch/i386/pci/pciide_machdep.c
168
reg = rdmsr(drive ? GCSC_ATAC_CH0D1_DMA :
sys/arch/i386/pci/pciide_machdep.c
176
reg |= GCSC_ATAC_DMA_SEL;
sys/arch/i386/pci/pciide_machdep.c
178
reg |= gcsc_udma_timings[drvp->UDMA_mode];
sys/arch/i386/pci/pciide_machdep.c
181
GCSC_ATAC_CH0D0_DMA, reg);
sys/arch/i386/pci/pciide_machdep.c
185
reg &= ~GCSC_ATAC_DMA_SEL;
sys/arch/i386/pci/pciide_machdep.c
187
reg |= gcsc_mdma_timings[drvp->DMA_mode];
sys/arch/i386/pci/pciide_machdep.c
190
GCSC_ATAC_CH0D0_DMA, reg);
sys/arch/i386/pci/pciide_machdep.c
195
GCSC_ATAC_CH0D0_DMA, reg | GCSC_ATAC_PIO_FORMAT);
sys/arch/i386/pci/piix.c
160
pcireg_t reg;
sys/arch/i386/pci/piix.c
171
reg = pci_conf_read(ph->ph_pc, ph->ph_tag, off);
sys/arch/i386/pci/piix.c
173
if ((reg >> shift) & PIIX_CFG_PIRQ_NONE)
sys/arch/i386/pci/piix.c
176
*irqp = PIIX_PIRQ(reg, clink);
sys/arch/i386/pci/piix.c
186
pcireg_t reg;
sys/arch/i386/pci/piix.c
197
reg = pci_conf_read(ph->ph_pc, ph->ph_tag, off);
sys/arch/i386/pci/piix.c
199
reg &= ~((PIIX_CFG_PIRQ_NONE | PIIX_CFG_PIRQ_MASK) << shift);
sys/arch/i386/pci/piix.c
200
reg |= irq << shift;
sys/arch/i386/pci/piix.c
201
pci_conf_write(ph->ph_pc, ph->ph_tag, off, reg);
sys/arch/i386/pci/piixreg.h
49
#define PIIX_PIRQ(reg, x) (((reg) >> ((x) << 3)) & 0xff)
sys/arch/i386/pci/sis85c503.c
124
pcireg_t reg;
sys/arch/i386/pci/sis85c503.c
129
reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
sys/arch/i386/pci/sis85c503.c
131
reg = SIS85C503_CFG_PIRQ_REG(reg, clink);
sys/arch/i386/pci/sis85c503.c
133
if (reg & SIS85C503_CFG_PIRQ_ROUTE_DISABLE)
sys/arch/i386/pci/sis85c503.c
136
*irqp = reg & SIS85C503_CFG_PIRQ_INTR_MASK;
sys/arch/i386/pci/sis85c503.c
146
pcireg_t reg;
sys/arch/i386/pci/sis85c503.c
151
reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
sys/arch/i386/pci/sis85c503.c
154
reg &= ~((SIS85C503_CFG_PIRQ_ROUTE_DISABLE |
sys/arch/i386/pci/sis85c503.c
156
reg |= (irq << shift);
sys/arch/i386/pci/sis85c503.c
158
reg);
sys/arch/i386/pci/sis85c503reg.h
46
#define SIS85C503_CFG_PIRQ_REG(reg, regofs) \
sys/arch/i386/pci/sis85c503reg.h
47
(((reg) >> SIS85C503_CFG_PIRQ_SHIFT(regofs)) & SIS85C503_CFG_PIRQ_MASK)
sys/arch/i386/pci/via8231.c
119
#define VIA8231_GET_TRIGGER_CNFG(reg, pirq) \
sys/arch/i386/pci/via8231.c
120
((reg) & (1 << (3 - (clink & 3))))
sys/arch/i386/pci/via8231.c
121
#define VIA8231_SET_TRIGGER_CNFG(reg, clink, cfg) \
sys/arch/i386/pci/via8231.c
122
(((reg) & ~(1 << (3 - (clink & 3)))) | ((cfg) << (3 - (clink & 3))))
sys/arch/i386/pci/via8231.c
124
#define VIA8231_GET_ROUTING_CNFG(reg, pirq) \
sys/arch/i386/pci/via8231.c
125
(((reg) >> via8231_routing_cnfg[(pirq)].shft) & \
sys/arch/i386/pci/via8231.c
128
#define VIA8231_SET_ROUTING_CNFG(reg, pirq, cfg) \
sys/arch/i386/pci/via8231.c
129
(((reg) & ~(via8231_routing_cnfg[(pirq)].mask << \
sys/arch/i386/pci/via8231.c
181
int reg, val;
sys/arch/i386/pci/via8231.c
187
reg = VIA8231_GET_ROUTING(ph);
sys/arch/i386/pci/via8231.c
188
val = VIA8231_GET_ROUTING_CNFG(reg, clink);
sys/arch/i386/pci/via8231.c
190
reg = VIA8237_GET_ROUTING(ph);
sys/arch/i386/pci/via8231.c
191
val = (reg >> ((clink & 3) * 4)) & 0xf;
sys/arch/i386/pci/via8231.c
204
int reg;
sys/arch/i386/pci/via8231.c
215
reg = VIA8231_GET_ROUTING(ph);
sys/arch/i386/pci/via8231.c
217
VIA8231_SET_ROUTING_CNFG(reg, clink, irq));
sys/arch/i386/pci/via8231.c
219
reg = VIA8237_GET_ROUTING(ph);
sys/arch/i386/pci/via8231.c
220
VIA8237_SET_ROUTING(ph, (reg & ~(0xf << (clink & 3))) |
sys/arch/i386/pci/via8231.c
231
int reg, clink, max, pciirq;
sys/arch/i386/pci/via8231.c
240
reg = VIA8231_LINK_LEGAL(clink)?
sys/arch/i386/pci/via8231.c
243
*triggerp = VIA8231_GET_TRIGGER_CNFG(reg, clink)?
sys/arch/i386/pci/via8231.c
256
int reg, clink, max, pciirq;
sys/arch/i386/pci/via8231.c
270
reg = VIA8231_LINK_LEGAL(clink)?
sys/arch/i386/pci/via8231.c
275
reg = VIA8231_SET_TRIGGER_CNFG(reg, clink,
sys/arch/i386/pci/via8231.c
279
reg = VIA8231_SET_TRIGGER_CNFG(reg, clink,
sys/arch/i386/pci/via8231.c
286
VIA8231_SET_TRIGGER(ph, reg);
sys/arch/i386/pci/via8231.c
288
VIA8237_SET_TRIGGER(ph, reg);
sys/arch/i386/pci/via82c586.c
109
#define VP3_PIRQ(reg, pirq) (((reg) >> vp3_cfg_intr_shift[(pirq)]) & \
sys/arch/i386/pci/via82c586.c
116
pcireg_t reg;
sys/arch/i386/pci/via82c586.c
124
reg = pci_conf_read(pc, tag, VP3_CFG_KBDMISCCTRL12_REG);
sys/arch/i386/pci/via82c586.c
125
reg |= VP3_CFG_MISCCTRL2_EISA4D04D1PORT_ENABLE <<
sys/arch/i386/pci/via82c586.c
127
pci_conf_write(pc, tag, VP3_CFG_KBDMISCCTRL12_REG, reg);
sys/arch/i386/pci/via82c586.c
151
pcireg_t reg;
sys/arch/i386/pci/via82c586.c
157
reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG);
sys/arch/i386/pci/via82c586.c
158
val = VP3_PIRQ(reg, clink);
sys/arch/i386/pci/via82c586.c
170
pcireg_t reg;
sys/arch/i386/pci/via82c586.c
175
reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG);
sys/arch/i386/pci/via82c586.c
178
reg &= ~(VP3_CFG_INTR_MASK << shift);
sys/arch/i386/pci/via82c586.c
179
reg |= (irq << shift);
sys/arch/i386/pci/via82c586.c
180
pci_conf_write(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG, reg);
sys/arch/i386/pci/via82c586.c
193
pcireg_t reg;
sys/arch/i386/pci/via82c586.c
202
reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
sys/arch/i386/pci/via82c586.c
204
if (VP3_TRIGGER(reg, i) == VP3_CFG_TRIGGER_EDGE)
sys/arch/i386/pci/via82c586.c
224
pcireg_t reg;
sys/arch/i386/pci/via82c586.c
232
reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
sys/arch/i386/pci/via82c586.c
237
reg &= ~(VP3_CFG_TRIGGER_MASK << shift);
sys/arch/i386/pci/via82c586.c
239
VP3_CFG_PIRQ_REG, reg);
sys/arch/i386/pci/via82c586.c
96
#define VP3_TRIGGER(reg, pirq) (((reg) >> vp3_cfg_trigger_shift[(pirq)]) & \
sys/arch/i386/pci/via82c586reg.h
40
#define VP3_CFG_MISCCTRL2_REG(reg) \
sys/arch/i386/pci/via82c586reg.h
41
(((reg) >> VP3_CFG_MISCCTRL2_SHIFT) & VP3_CFG_MISCCTRL2_MASK)
sys/arch/i386/stand/libsa/debug.c
39
struct reg reg;
sys/arch/i386/stand/libsa/debug.c
40
u_int32_t *const reg_values[] = { REG_VALUES(reg) };
sys/arch/i386/stand/libsa/debug_md.h
51
.globl reg
sys/arch/i386/stand/libsa/debug_md.h
55
extern struct reg reg;
sys/arch/landisk/dev/wdc_obio.c
150
wdc_obio_read_reg(struct channel_softc *chp, enum wdc_regs reg)
sys/arch/landisk/dev/wdc_obio.c
152
if (reg & _WDC_AUX)
sys/arch/landisk/dev/wdc_obio.c
154
(reg & _WDC_REGMASK) << 1));
sys/arch/landisk/dev/wdc_obio.c
157
(reg & _WDC_REGMASK) << 1));
sys/arch/landisk/dev/wdc_obio.c
161
wdc_obio_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
sys/arch/landisk/dev/wdc_obio.c
163
if (reg & _WDC_AUX)
sys/arch/landisk/dev/wdc_obio.c
165
(reg & _WDC_REGMASK) << 1, val);
sys/arch/landisk/dev/wdc_obio.c
168
(reg & _WDC_REGMASK) << 1, val);
sys/arch/landisk/dev/wdc_obio.c
67
u_int8_t wdc_obio_read_reg(struct channel_softc *chp, enum wdc_regs reg);
sys/arch/landisk/dev/wdc_obio.c
68
void wdc_obio_write_reg(struct channel_softc *chp, enum wdc_regs reg,
sys/arch/landisk/include/pci_machdep.h
69
#define pci_conf_read(v, tag, reg) \
sys/arch/landisk/include/pci_machdep.h
70
shpcic_conf_read(v, tag, reg)
sys/arch/landisk/include/pci_machdep.h
71
#define pci_conf_write(v, tag, reg, data) \
sys/arch/landisk/include/pci_machdep.h
72
shpcic_conf_write(v, tag, reg, data)
sys/arch/loongson/dev/bonito.c
1150
uint32_t reg;
sys/arch/loongson/dev/bonito.c
1175
reg = REGVAL(BONITO_PCIMAP);
sys/arch/loongson/dev/bonito.c
1177
BONITO_PCIMAP_WINBASE((reg & BONITO_PCIMAP_PCIMAP_LO0) >>
sys/arch/loongson/dev/bonito.c
1182
BONITO_PCIMAP_WINBASE((reg & BONITO_PCIMAP_PCIMAP_LO1) >>
sys/arch/loongson/dev/bonito.c
1187
BONITO_PCIMAP_WINBASE((reg & BONITO_PCIMAP_PCIMAP_LO2) >>
sys/arch/loongson/dev/bonito.c
1226
bonito_conf_read_early(pcitag_t tag, int reg)
sys/arch/loongson/dev/bonito.c
1228
return bonito_conf_read_internal(sys_platform->bonito_config, tag, reg);
sys/arch/loongson/dev/bonito.c
224
uint32_t reg;
sys/arch/loongson/dev/bonito.c
237
reg = PCI_REVISION(REGVAL(BONITO_PCI_REG(PCI_CLASS_REG)));
sys/arch/loongson/dev/bonito.c
240
BONITO_REV_FPGA(reg) ? "FPGA" : "ASIC",
sys/arch/loongson/dev/bonito.c
241
BONITO_REV_MAJOR(reg), BONITO_REV_MINOR(reg));
sys/arch/loongson/dev/bonito.c
297
reg = REGVAL(LOONGSON_PXARB_CFG);
sys/arch/loongson/dev/bonito.c
298
reg &= ~LOONGSON_PXARB_RUDE_DEV_MSK;
sys/arch/loongson/dev/bonito.c
299
reg |= 0xfe << LOONGSON_PXARB_RUDE_DEV_SHFT;
sys/arch/loongson/dev/bonito.c
300
REGVAL(LOONGSON_PXARB_CFG) = reg;
sys/arch/loongson/dev/glx.c
294
glx_fn0_read(int reg)
sys/arch/loongson/dev/glx.c
300
switch (reg) {
sys/arch/loongson/dev/glx.c
331
index = (reg - PCI_MAPREG_START) / 4;
sys/arch/loongson/dev/glx.c
358
glx_fn0_write(int reg, pcireg_t data)
sys/arch/loongson/dev/glx.c
363
switch (reg) {
sys/arch/loongson/dev/glx.c
395
index = (reg - PCI_MAPREG_START) / 4;
sys/arch/loongson/dev/glx.c
422
glx_fn2_read(int reg)
sys/arch/loongson/dev/glx.c
427
switch (reg) {
sys/arch/loongson/dev/glx.c
489
glx_fn2_write(int reg, pcireg_t data)
sys/arch/loongson/dev/glx.c
493
switch (reg) {
sys/arch/loongson/dev/glx.c
545
glx_fn3_read(int reg)
sys/arch/loongson/dev/glx.c
550
switch (reg) {
sys/arch/loongson/dev/glx.c
600
glx_fn3_write(int reg, pcireg_t data)
sys/arch/loongson/dev/glx.c
604
switch (reg) {
sys/arch/loongson/dev/glx.c
648
glx_fn4_read(int reg)
sys/arch/loongson/dev/glx.c
653
switch (reg) {
sys/arch/loongson/dev/glx.c
709
glx_fn4_write(int reg, pcireg_t data)
sys/arch/loongson/dev/glx.c
713
switch (reg) {
sys/arch/loongson/dev/glx.c
769
glx_fn5_read(int reg)
sys/arch/loongson/dev/glx.c
774
switch (reg) {
sys/arch/loongson/dev/glx.c
835
glx_fn5_write(int reg, pcireg_t data)
sys/arch/loongson/dev/glx.c
839
switch (reg) {
sys/arch/loongson/dev/htb.c
440
htb_conf_read_early(pcitag_t tag, int reg)
sys/arch/loongson/dev/htb.c
442
return htb_conf_read(NULL, tag, reg);
sys/arch/loongson/dev/kb3310.c
212
ykbec_write(struct ykbec_softc *mcsc, u_int reg, u_int datum)
sys/arch/loongson/dev/kb3310.c
218
bus_space_write_1(iot, ioh, 0, (reg >> 8) & 0xff);
sys/arch/loongson/dev/kb3310.c
219
bus_space_write_1(iot, ioh, 1, (reg >> 0) & 0xff);
sys/arch/loongson/dev/kb3310.c
224
ykbec_read(struct ykbec_softc *mcsc, u_int reg)
sys/arch/loongson/dev/kb3310.c
230
bus_space_write_1(iot, ioh, 0, (reg >> 8) & 0xff);
sys/arch/loongson/dev/kb3310.c
231
bus_space_write_1(iot, ioh, 1, (reg >> 0) & 0xff);
sys/arch/loongson/dev/kb3310.c
236
ykbec_read16(struct ykbec_softc *mcsc, u_int reg)
sys/arch/loongson/dev/kb3310.c
240
val = ykbec_read(mcsc, reg);
sys/arch/loongson/dev/kb3310.c
241
return (val << 8) | ykbec_read(mcsc, reg + 1);
sys/arch/loongson/dev/mcclock.c
48
#define mc146818_write(dev, reg, datum) \
sys/arch/loongson/dev/mcclock.c
49
(*(dev)->sc_busfns->mc_bf_write)(dev, reg, datum)
sys/arch/loongson/dev/mcclock.c
50
#define mc146818_read(dev, reg) \
sys/arch/loongson/dev/mcclock.c
51
(*(dev)->sc_busfns->mc_bf_read)(dev, reg)
sys/arch/loongson/dev/mcclock_isa.c
104
mcclock_isa_write(struct mcclock_softc *mcsc, u_int reg, u_int datum)
sys/arch/loongson/dev/mcclock_isa.c
110
bus_space_write_1(iot, ioh, 0, reg);
sys/arch/loongson/dev/mcclock_isa.c
115
mcclock_isa_read(struct mcclock_softc *mcsc, u_int reg)
sys/arch/loongson/dev/mcclock_isa.c
121
bus_space_write_1(iot, ioh, 0, reg);
sys/arch/loongson/dev/smfb.c
616
uint32_t reg;
sys/arch/loongson/dev/smfb.c
622
reg = bus_space_read_4(fb->mmiot, fb->mmioh,
sys/arch/loongson/dev/smfb.c
624
if ((reg & (VSC_FIFO_EMPTY | VSC_2DENGINE_BUSY)) ==
sys/arch/loongson/dev/smfb.c
628
reg = smfb_vgats_read(fb, 0x16);
sys/arch/loongson/dev/smfb.c
629
if ((reg & 0x18) == 0x10)
sys/arch/loongson/dev/smfb.c
72
#define DCR_READ(fb, reg) \
sys/arch/loongson/dev/smfb.c
73
bus_space_read_4((fb)->dcrt, (fb)->dcrh, (reg))
sys/arch/loongson/dev/smfb.c
74
#define DCR_WRITE(fb, reg, val) \
sys/arch/loongson/dev/smfb.c
75
bus_space_write_4((fb)->dcrt, (fb)->dcrh, (reg), (val))
sys/arch/loongson/dev/smfb.c
76
#define DPR_READ(fb, reg) \
sys/arch/loongson/dev/smfb.c
77
bus_space_read_4((fb)->dprt, (fb)->dprh, (reg))
sys/arch/loongson/dev/smfb.c
78
#define DPR_WRITE(fb, reg, val) \
sys/arch/loongson/dev/smfb.c
79
bus_space_write_4((fb)->dprt, (fb)->dprh, (reg), (val))
sys/arch/loongson/dev/stsec.c
217
stsec_read(struct stsec_softc *sc, uint reg, int *value)
sys/arch/loongson/dev/stsec.c
222
regno = sc->sc_base + reg;
sys/arch/loongson/dev/stsec.c
234
stsec_write(struct stsec_softc *sc, uint reg, int val)
sys/arch/loongson/dev/stsec.c
239
regno = sc->sc_base + reg;
sys/arch/loongson/dev/voyager.c
306
bus_addr_t reg;
sys/arch/loongson/dev/voyager.c
311
reg = VOYAGER_GPIO_DATA_HIGH;
sys/arch/loongson/dev/voyager.c
313
reg = VOYAGER_GPIO_DATA_LOW;
sys/arch/loongson/dev/voyager.c
317
data = bus_space_read_4(sc->sc_mmiot, sc->sc_mmioh, reg);
sys/arch/loongson/dev/voyager.c
325
bus_addr_t reg;
sys/arch/loongson/dev/voyager.c
330
reg = VOYAGER_GPIO_DATA_HIGH;
sys/arch/loongson/dev/voyager.c
332
reg = VOYAGER_GPIO_DATA_LOW;
sys/arch/loongson/dev/voyager.c
335
data = bus_space_read_4(sc->sc_mmiot, sc->sc_mmioh, reg);
sys/arch/loongson/dev/voyager.c
340
bus_space_write_4(sc->sc_mmiot, sc->sc_mmioh, reg, data);
sys/arch/loongson/dev/voyager.c
341
(void)bus_space_read_4(sc->sc_mmiot, sc->sc_mmioh, reg);
sys/arch/loongson/dev/voyager.c
348
bus_addr_t reg;
sys/arch/loongson/dev/voyager.c
353
reg = VOYAGER_GPIO_DIR_HIGH;
sys/arch/loongson/dev/voyager.c
355
reg = VOYAGER_GPIO_DIR_LOW;
sys/arch/loongson/dev/voyager.c
358
data = bus_space_read_4(sc->sc_mmiot, sc->sc_mmioh, reg);
sys/arch/loongson/dev/voyager.c
363
bus_space_write_4(sc->sc_mmiot, sc->sc_mmioh, reg, data);
sys/arch/loongson/dev/voyager.c
364
(void)bus_space_read_4(sc->sc_mmiot, sc->sc_mmioh, reg);
sys/arch/loongson/loongson/gdium_machdep.c
126
reg = pci_conf_read(pc, tag, 0xe0);
sys/arch/loongson/loongson/gdium_machdep.c
128
reg |= 0x00000003;
sys/arch/loongson/loongson/gdium_machdep.c
129
pci_conf_write(pc, tag, 0xe0, reg);
sys/arch/loongson/loongson/gdium_machdep.c
140
reg = pci_conf_read(pc, tag, 0xe0);
sys/arch/loongson/loongson/gdium_machdep.c
142
reg &= ~0x00000007;
sys/arch/loongson/loongson/gdium_machdep.c
143
reg |= 0x00000005;
sys/arch/loongson/loongson/gdium_machdep.c
144
pci_conf_write(pc, tag, 0xe0, reg);
sys/arch/loongson/loongson/gdium_machdep.c
85
pcireg_t reg;
sys/arch/loongson/loongson/generic2e_machdep.c
474
pcireg_t reg;
sys/arch/loongson/loongson/generic2e_machdep.c
483
reg = pci_conf_read(pc, tag, VIA686_ISA_ROM_CONTROL);
sys/arch/loongson/loongson/generic2e_machdep.c
484
reg |= VIA686_IO_RECOVERY_TIME | VIA686_ISA_REFRESH;
sys/arch/loongson/loongson/generic2e_machdep.c
485
pci_conf_write(pc, tag, VIA686_ISA_ROM_CONTROL, reg);
sys/arch/loongson/loongson/generic2e_machdep.c
487
reg = pci_conf_read(pc, tag, VIA686_KBC_DMA_MISC12);
sys/arch/loongson/loongson/generic2e_machdep.c
488
reg |= VIA686_CPU_RESET_SOURCE_INIT |
sys/arch/loongson/loongson/generic2e_machdep.c
495
reg &= ~VIA686_ISA_MASTER_TO_LINE_BUFFER;
sys/arch/loongson/loongson/generic2e_machdep.c
496
pci_conf_write(pc, tag, VIA686_KBC_DMA_MISC12, reg);
sys/arch/loongson/loongson/generic2e_machdep.c
502
reg = pci_conf_read(pc, tag, VIA686_MISC3_IDE_INTR);
sys/arch/loongson/loongson/generic2e_machdep.c
503
reg &= ~(VIA686_IDE_PRIMARY_CHAN_MASK | VIA686_IDE_SECONDARY_CHAN_MASK);
sys/arch/loongson/loongson/generic2e_machdep.c
504
reg |= (VIA686_IDE_IRQ14 << VIA686_IDE_PRIMARY_CHAN_SHIFT);
sys/arch/loongson/loongson/generic2e_machdep.c
505
reg |= (VIA686_IDE_IRQ15 << VIA686_IDE_SECONDARY_CHAN_SHIFT);
sys/arch/loongson/loongson/generic2e_machdep.c
506
reg |= VIA686_IDE_PGNT;
sys/arch/loongson/loongson/generic2e_machdep.c
507
pci_conf_write(pc, tag, VIA686_MISC3_IDE_INTR, reg);
sys/arch/loongson/loongson/generic2e_machdep.c
509
reg = pci_conf_read(pc, tag, VIA686_PNP_DMA_IRQ);
sys/arch/loongson/loongson/generic2e_machdep.c
510
reg &= ~(VIA686_DMA_FDC_MASK | VIA686_DMA_LPT_MASK);
sys/arch/loongson/loongson/generic2e_machdep.c
511
reg |= (2 << VIA686_DMA_FDC_SHIFT) | (3 << VIA686_DMA_LPT_SHIFT);
sys/arch/loongson/loongson/generic2e_machdep.c
512
reg &= ~(VIA686_IRQ_FDC_MASK | VIA686_IRQ_LPT_MASK);
sys/arch/loongson/loongson/generic2e_machdep.c
513
reg |= (6 << VIA686_IRQ_FDC_SHIFT) | (7 << VIA686_IRQ_LPT_SHIFT);
sys/arch/loongson/loongson/generic2e_machdep.c
514
reg &= ~(VIA686_IRQ_COM0_MASK | VIA686_IRQ_COM1_MASK);
sys/arch/loongson/loongson/generic2e_machdep.c
515
reg |= (4 << VIA686_IRQ_COM0_SHIFT) | (3 << VIA686_IRQ_COM1_SHIFT);
sys/arch/loongson/loongson/generic2e_machdep.c
517
reg = pci_conf_read(pc, tag, VIA686_PCI_LEVEL_PNP_IRQ2);
sys/arch/loongson/loongson/generic2e_machdep.c
518
reg &= ~(VIA686_PCI_IRQA_EDGE | VIA686_PCI_IRQB_EDGE |
sys/arch/loongson/loongson/generic2e_machdep.c
520
reg &= ~(VIA686_IRQ_PCIA_MASK | VIA686_IRQ_PCIB_MASK |
sys/arch/loongson/loongson/generic2e_machdep.c
522
reg |= (VIA686_IRQ_PCIA << VIA686_IRQ_PCIA_SHIFT) |
sys/arch/loongson/loongson/generic2e_machdep.c
575
reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
sys/arch/loongson/loongson/generic2e_machdep.c
576
reg &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
sys/arch/loongson/loongson/generic2e_machdep.c
577
reg |= VIA686_IRQ_PCIB << PCI_INTERRUPT_LINE_SHIFT;
sys/arch/loongson/loongson/generic2e_machdep.c
578
pci_conf_write(pc, tag, PCI_INTERRUPT_REG, reg);
sys/arch/loongson/loongson/generic2e_machdep.c
581
reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
sys/arch/loongson/loongson/generic2e_machdep.c
582
reg &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
sys/arch/loongson/loongson/generic2e_machdep.c
583
reg |= VIA686_IRQ_PCIC << PCI_INTERRUPT_LINE_SHIFT;
sys/arch/loongson/loongson/generic2e_machdep.c
584
pci_conf_write(pc, tag, PCI_INTERRUPT_REG, reg);
sys/arch/loongson/loongson/generic2e_machdep.c
587
reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
sys/arch/loongson/loongson/generic2e_machdep.c
588
reg &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
sys/arch/loongson/loongson/generic2e_machdep.c
589
reg |= VIA686_IRQ_PCIA << PCI_INTERRUPT_LINE_SHIFT;
sys/arch/loongson/loongson/generic2e_machdep.c
590
pci_conf_write(pc, tag, PCI_INTERRUPT_REG, reg);
sys/arch/loongson/loongson/generic3a_machdep.c
399
pcireg_t reg;
sys/arch/loongson/loongson/generic3a_machdep.c
437
reg = pci_conf_read(pc, tag, 0x40);
sys/arch/loongson/loongson/generic3a_machdep.c
438
reg |= 1u << 28;
sys/arch/loongson/loongson/generic3a_machdep.c
439
pci_conf_write(pc, tag, 0x40, reg);
sys/arch/loongson/loongson/generic3a_machdep.c
442
reg = HPET_REGVAL32(HPET_CONFIGURATION);
sys/arch/loongson/loongson/generic3a_machdep.c
443
HPET_REGVAL32(HPET_CONFIGURATION) = reg | 1u;
sys/arch/luna88k/cbus/i82365_cbus.c
249
int intlevel, irq, i, reg;
sys/arch/luna88k/cbus/i82365_cbus.c
315
reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_1);
sys/arch/luna88k/cbus/i82365_cbus.c
316
reg |= PCIC_CIRRUS_MISC_CTL_1_PULSE_MGMT_INTR;
sys/arch/luna88k/cbus/i82365_cbus.c
317
pcic_write(h, PCIC_CIRRUS_MISC_CTL_1, reg);
sys/arch/luna88k/cbus/i82365_cbus.c
344
int intlevel, irq, reg;
sys/arch/luna88k/cbus/i82365_cbus.c
362
reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_1);
sys/arch/luna88k/cbus/i82365_cbus.c
363
reg |= PCIC_CIRRUS_MISC_CTL_1_PULSE_SYS_IRQ;
sys/arch/luna88k/cbus/i82365_cbus.c
364
pcic_write(h, PCIC_CIRRUS_MISC_CTL_1, reg);
sys/arch/luna88k/cbus/i82365_cbus.c
382
reg = pcic_read(h, PCIC_INTR);
sys/arch/luna88k/cbus/i82365_cbus.c
383
reg &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE);
sys/arch/luna88k/cbus/i82365_cbus.c
384
pcic_write(h, PCIC_INTR, reg | irq);
sys/arch/luna88k/cbus/i82365_cbus.c
396
int intlevel, reg;
sys/arch/luna88k/cbus/i82365_cbus.c
411
reg = pcic_read(h, PCIC_INTR);
sys/arch/luna88k/cbus/i82365_cbus.c
412
reg &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE);
sys/arch/luna88k/cbus/i82365_cbus.c
413
pcic_write(h, PCIC_INTR, reg);
sys/arch/luna88k/cbus/i82365_cbus.c
418
reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_1);
sys/arch/luna88k/cbus/i82365_cbus.c
419
reg &= ~PCIC_CIRRUS_MISC_CTL_1_PULSE_SYS_IRQ;
sys/arch/luna88k/cbus/i82365_cbus.c
420
pcic_write(h, PCIC_CIRRUS_MISC_CTL_1, reg);
sys/arch/luna88k/stand/boot/if_le.c
108
void *reg, *mem;
sys/arch/luna88k/stand/boot/if_le.c
111
reg = (void *)LANCE_ADDR;
sys/arch/luna88k/stand/boot/if_le.c
114
if (badaddr(reg, 4) != 0)
sys/arch/luna88k/stand/boot/if_le.c
119
cookie = lance_attach(0, reg, mem, eaddr);
sys/arch/luna88k/stand/boot/lance.c
286
uint16_t reg;
sys/arch/luna88k/stand/boot/lance.c
300
reg = lereg->ler_rdp;
sys/arch/luna88k/stand/boot/lance.c
302
printf("le: init timeout (CSR=0x%x)\n", reg);
sys/arch/luna88k/stand/boot/lance.c
306
} while ((reg & LE_C0_IDON) == 0);
sys/arch/luna88k/stand/boot/lance.c
76
lance_attach(uint unit, void *reg, void *mem, uint8_t *eaddr)
sys/arch/luna88k/stand/boot/lance.c
90
sc->sc_reg = reg;
sys/arch/luna88k/stand/boot/sc.c
105
void *reg;
sys/arch/luna88k/stand/boot/sc.c
109
reg = (void *)SCSI_ADDR;
sys/arch/luna88k/stand/boot/sc.c
112
reg = (void *)(SCSI_ADDR + 0x40);
sys/arch/luna88k/stand/boot/sc.c
121
hs->sc_sd = (struct scsidevice *)reg;
sys/arch/luna88k/stand/boot/sio.c
227
sioreg(int reg, int val)
sys/arch/luna88k/stand/boot/sio.c
231
chan = CHANNEL(reg);
sys/arch/luna88k/stand/boot/sio.c
233
if (isStatusReg(reg)) {
sys/arch/luna88k/stand/boot/sio.c
234
if (REGNO(reg) != 0)
sys/arch/luna88k/stand/boot/sio.c
235
sio_addr[chan]->sio_cmd = REGNO(reg);
sys/arch/luna88k/stand/boot/sio.c
238
if (REGNO(reg) != 0)
sys/arch/luna88k/stand/boot/sio.c
239
sio_addr[chan]->sio_cmd = REGNO(reg);
sys/arch/m88k/include/cpu.h
287
#define PROC_PC(p) PC_REGS((struct reg *)((p)->p_md.md_tf))
sys/arch/m88k/include/db_machdep.h
60
typedef struct reg db_regs_t;
sys/arch/m88k/include/frame.h
40
struct reg tf_regs;
sys/arch/m88k/include/m88100.h
73
m88100_rewind_insn(struct reg *regs)
sys/arch/m88k/include/pcb.h
86
(((struct reg *)(&((p)->p_addr->u_pcb.user_state))))
sys/arch/m88k/m88k/db_interface.c
123
int reg = DMT_DREGBITS(t);
sys/arch/m88k/m88k/db_interface.c
128
ISSET(t, DMT_DAS) ? "" : ".usr", reg,
sys/arch/m88k/m88k/db_interface.c
144
ISSET(t, DMT_DAS) ? "" : ".usr", reg, a, reg+1, a+4);
sys/arch/m88k/m88k/db_interface.c
147
ISSET(t, DMT_DAS) ? "" : ".usr", reg, a);
sys/arch/m88k/m88k/db_interface.c
162
ISSET(t, DMT_DAS) ? "" : ".usr", reg, a);
sys/arch/m88k/m88k/db_trace.c
306
#define reg_bit(reg) 1 << (reg)
sys/arch/m88k/m88k/db_trace.c
309
save_reg(int reg, u_int value)
sys/arch/m88k/m88k/db_trace.c
311
reg &= 0x1f;
sys/arch/m88k/m88k/db_trace.c
312
if (trashed_list & reg_bit(reg))
sys/arch/m88k/m88k/db_trace.c
315
saved_reg[reg] = value;
sys/arch/m88k/m88k/db_trace.c
316
global_saved_list |= reg_bit(reg);
sys/arch/m88k/m88k/db_trace.c
317
local_saved_list |= reg_bit(reg);
sys/arch/m88k/m88k/db_trace.c
320
#define mark_reg_trashed(reg) trashed_list |= reg_bit((reg) & 0x1f)
sys/arch/m88k/m88k/db_trace.c
322
#define have_global_reg(reg) (global_saved_list & reg_bit(reg))
sys/arch/m88k/m88k/db_trace.c
323
#define have_local_reg(reg) (local_saved_list & reg_bit(reg))
sys/arch/m88k/m88k/db_trace.c
328
#define saved_reg_value(reg) saved_reg[(reg)]
sys/arch/m88k/m88k/db_trace.c
336
int reg, last_arg;
sys/arch/m88k/m88k/db_trace.c
348
for (reg = FIRST_ARG_REG; /*nothing */; reg++) {
sys/arch/m88k/m88k/db_trace.c
349
if (!have_local_reg(reg))
sys/arch/m88k/m88k/db_trace.c
352
u_int value = saved_reg_value(reg);
sys/arch/m88k/m88k/db_trace.c
356
if (reg == last_arg)
sys/arch/m88k/m88k/m88100_machdep.c
173
u_int v, reg, enbits;
sys/arch/m88k/m88k/m88100_machdep.c
182
reg = DMT_DREGBITS(dmtx);
sys/arch/m88k/m88k/m88100_machdep.c
197
if (reg != 0)
sys/arch/m88k/m88k/m88100_machdep.c
198
eframe->tf_r[reg] = v;
sys/arch/m88k/m88k/m88100_machdep.c
200
if (reg != 31)
sys/arch/m88k/m88k/m88100_machdep.c
201
eframe->tf_r[reg + 1] = v;
sys/arch/m88k/m88k/m88100_machdep.c
253
if (reg == 0)
sys/arch/m88k/m88k/m88100_machdep.c
256
printf("[r%d <- %08x]\n", reg, v);
sys/arch/m88k/m88k/m88100_machdep.c
258
if (reg != 0)
sys/arch/m88k/m88k/m88100_machdep.c
259
eframe->tf_r[reg] = v;
sys/arch/m88k/m88k/m88100_machdep.c
287
if (reg == 0)
sys/arch/m88k/m88k/m88100_machdep.c
290
printf("[r%d <- %08x]\n", reg, v);
sys/arch/m88k/m88k/m88100_machdep.c
292
if (reg != 0)
sys/arch/m88k/m88k/m88100_machdep.c
293
eframe->tf_r[reg] = v;
sys/arch/m88k/m88k/m88100_machdep.c
296
if (reg != 0)
sys/arch/m88k/m88k/m88100_machdep.c
297
eframe->tf_r[reg] = dmdx;
sys/arch/m88k/m88k/m8820x_machdep.c
197
m8820x_cmmu_set_reg(struct m8820x_cmmu *cmmu, int reg, u_int val)
sys/arch/m88k/m88k/m8820x_machdep.c
200
cmmu->cmmu_regs[reg] = val;
sys/arch/m88k/m88k/m8820x_machdep.c
206
m8820x_cmmu_set_reg_same_mode(struct m8820x_cmmu *cmmu, int reg, u_int val)
sys/arch/m88k/m88k/m8820x_machdep.c
209
cmmu->cmmu_regs[reg] = val;
sys/arch/m88k/m88k/process_machdep.c
73
process_read_regs(struct proc *p, struct reg *regs)
sys/arch/m88k/m88k/process_machdep.c
75
bcopy((caddr_t)USER_REGS(p), (caddr_t)regs, sizeof(struct reg));
sys/arch/m88k/m88k/process_machdep.c
82
process_write_regs(struct proc *p, struct reg *regs)
sys/arch/m88k/m88k/process_machdep.c
84
struct reg *procregs = (struct reg *)USER_REGS(p);
sys/arch/m88k/m88k/process_machdep.c
87
bcopy(regs, procregs, sizeof(struct reg));
sys/arch/m88k/m88k/process_machdep.c
99
struct reg *regs;
sys/arch/m88k/m88k/sig_machdep.c
229
if ((((struct reg *)&ksc.sc_regs)->epsr ^ tf->tf_regs.epsr) &
sys/arch/m88k/m88k/trap.c
1372
vaddr_t ss_branch_taken(u_int, vaddr_t, struct reg *);
sys/arch/m88k/m88k/trap.c
1426
ss_branch_taken(u_int inst, vaddr_t pc, struct reg *regs)
sys/arch/m88k/m88k/trap.c
1511
struct reg *sstf = USER_REGS(p);
sys/arch/macppc/dev/awacs.c
401
awacs_read_reg(struct awacs_softc *sc, int reg)
sys/arch/macppc/dev/awacs.c
405
return in32rb(addr + reg);
sys/arch/macppc/dev/awacs.c
409
awacs_write_reg(struct awacs_softc *sc, int reg, int val)
sys/arch/macppc/dev/awacs.c
413
out32rb(addr + reg, val);
sys/arch/macppc/dev/dfs.c
71
uint32_t hid1, reg;
sys/arch/macppc/dev/dfs.c
78
OF_getprop(OF_parent(ca->ca_node), "reg", ®, sizeof(reg));
sys/arch/macppc/dev/dfs.c
79
if (reg > ca->ca_reg[0])
sys/arch/macppc/dev/dfs.c
80
sc->sc_voltage = reg + ca->ca_reg[0];
sys/arch/macppc/dev/i2s.c
677
u_int reg = 0;
sys/arch/macppc/dev/i2s.c
692
reg = CLKSRC_45MHz;
sys/arch/macppc/dev/i2s.c
698
reg = CLKSRC_49MHz;
sys/arch/macppc/dev/i2s.c
70
u_int32_t reg[6], intr[6];
sys/arch/macppc/dev/i2s.c
712
reg |= MCLK_DIV1;
sys/arch/macppc/dev/i2s.c
715
reg |= MCLK_DIV3;
sys/arch/macppc/dev/i2s.c
718
reg |= MCLK_DIV5;
sys/arch/macppc/dev/i2s.c
721
reg |= ((mdiv / 2 - 1) << 24) & 0x1f000000;
sys/arch/macppc/dev/i2s.c
727
reg |= SCLK_DIV1;
sys/arch/macppc/dev/i2s.c
730
reg |= SCLK_DIV3;
sys/arch/macppc/dev/i2s.c
733
reg |= ((sdiv / 2 - 1) << 20) & 0x00f00000;
sys/arch/macppc/dev/i2s.c
737
reg |= SCLK_MASTER; /* XXX master mode */
sys/arch/macppc/dev/i2s.c
739
reg |= SERIAL_64x;
sys/arch/macppc/dev/i2s.c
765
in32rb(sc->sc_reg + I2S_FORMAT), reg));
sys/arch/macppc/dev/i2s.c
766
out32rb(sc->sc_reg + I2S_FORMAT, reg);
sys/arch/macppc/dev/i2s.c
77
OF_getprop(sc->sc_node, "reg", reg, sizeof reg);
sys/arch/macppc/dev/i2s.c
843
u_int32_t reg[2];
sys/arch/macppc/dev/i2s.c
849
OF_getprop(gpio, "reg", ®[0],
sys/arch/macppc/dev/i2s.c
85
reg[0] += ca->ca_reg[0];
sys/arch/macppc/dev/i2s.c
850
sizeof(reg[0])) != sizeof(reg[0]) ||
sys/arch/macppc/dev/i2s.c
851
OF_getprop(OF_parent(gpio), "reg", ®[1],
sys/arch/macppc/dev/i2s.c
852
sizeof(reg[1])) != sizeof(reg[1]))
sys/arch/macppc/dev/i2s.c
86
reg[2] += ca->ca_reg[2];
sys/arch/macppc/dev/i2s.c
860
return (reg[0] + reg[1]);
sys/arch/macppc/dev/i2s.c
87
reg[4] += ca->ca_reg[2];
sys/arch/macppc/dev/i2s.c
883
uint32_t reg;
sys/arch/macppc/dev/i2s.c
885
reg = 0;
sys/arch/macppc/dev/i2s.c
890
if (OF_getprop(gpio, "reg", ®, sizeof(reg)) == -1)
sys/arch/macppc/dev/i2s.c
891
OF_getprop(gpio, "AAPL,address", ®, sizeof(reg));
sys/arch/macppc/dev/i2s.c
893
if (reg > sc->sc_baseaddr)
sys/arch/macppc/dev/i2s.c
894
reg = (reg - sc->sc_baseaddr);
sys/arch/macppc/dev/i2s.c
898
sc->sc_hp = reg;
sys/arch/macppc/dev/i2s.c
90
reg[0] += sc->sc_baseaddr;
sys/arch/macppc/dev/i2s.c
902
sc->sc_spkr = reg;
sys/arch/macppc/dev/i2s.c
907
sc->sc_hp_detect = reg;
sys/arch/macppc/dev/i2s.c
91
reg[2] += sc->sc_baseaddr;
sys/arch/macppc/dev/i2s.c
917
sc->sc_hw_reset = reg;
sys/arch/macppc/dev/i2s.c
92
reg[4] += sc->sc_baseaddr;
sys/arch/macppc/dev/i2s.c
94
sc->sc_reg = mapiodev(reg[0], reg[1]);
sys/arch/macppc/dev/i2s.c
97
sc->sc_odma = mapiodev(reg[2], reg[3]); /* out */
sys/arch/macppc/dev/i2s.c
98
sc->sc_idma = mapiodev(reg[4], reg[5]); /* in */
sys/arch/macppc/dev/if_bm.c
885
bmac_mii_readreg(struct device *dev, int phy, int reg)
sys/arch/macppc/dev/if_bm.c
887
return mii_bitbang_readreg(dev, &bmac_mbo, phy, reg);
sys/arch/macppc/dev/if_bm.c
891
bmac_mii_writereg(struct device *dev, int phy, int reg, int val)
sys/arch/macppc/dev/if_bm.c
893
mii_bitbang_writereg(dev, &bmac_mbo, phy, reg, val);
sys/arch/macppc/dev/if_mc.c
77
#define NIC_GET(sc, reg) (in8rb(sc->sc_reg + MACE_REG(reg)))
sys/arch/macppc/dev/if_mc.c
79
#define NIC_PUT(sc, reg, val) (out8rb(sc->sc_reg + MACE_REG(reg), (val)))
sys/arch/macppc/dev/kiic.c
125
if (OF_getprop(node, "reg", ®, sizeof(reg)) > 0)
sys/arch/macppc/dev/kiic.c
126
sc->sc_busport = reg;
sys/arch/macppc/dev/kiic.c
146
kiic_readreg(struct kiic_softc *sc, int reg)
sys/arch/macppc/dev/kiic.c
148
u_char *addr = sc->sc_reg + sc->sc_regstep * reg;
sys/arch/macppc/dev/kiic.c
154
kiic_writereg(struct kiic_softc *sc, int reg, u_int val)
sys/arch/macppc/dev/kiic.c
156
u_char *addr = sc->sc_reg + sc->sc_regstep * reg;
sys/arch/macppc/dev/kiic.c
90
uint32_t reg;
sys/arch/macppc/dev/macgpio.c
114
ca2.ca_nreg = OF_getprop(child, "reg", reg, sizeof(reg));
sys/arch/macppc/dev/macgpio.c
121
ca2.ca_reg = reg;
sys/arch/macppc/dev/macgpio.c
95
u_int reg[20];
sys/arch/macppc/dev/maci2c.c
35
u_int32_t reg;
sys/arch/macppc/dev/maci2c.c
39
if (OF_getprop(node, "reg", ®, sizeof reg) != sizeof reg &&
sys/arch/macppc/dev/maci2c.c
40
OF_getprop(node, "i2c-address", ®, sizeof reg) != sizeof reg)
sys/arch/macppc/dev/maci2c.c
44
ia.ia_addr = (reg >> 1);
sys/arch/macppc/dev/mediabay.c
143
u_int reg[20], intr[5];
sys/arch/macppc/dev/mediabay.c
169
ca.ca_nreg = OF_getprop(child, "reg", reg, sizeof(reg));
sys/arch/macppc/dev/mediabay.c
175
ca.ca_reg = reg;
sys/arch/macppc/dev/openpic.c
149
openpic_read(int reg)
sys/arch/macppc/dev/openpic.c
151
char *addr = (void *)(openpic_base + reg);
sys/arch/macppc/dev/openpic.c
161
openpic_write(int reg, u_int val)
sys/arch/macppc/dev/openpic.c
163
char *addr = (void *)(openpic_base + reg);
sys/arch/macppc/dev/openpic.c
217
uint32_t reg = 0;
sys/arch/macppc/dev/openpic.c
221
if (OF_getprop(ca->ca_node, "big-endian", ®, sizeof reg) == 0)
sys/arch/macppc/dev/openpic.c
88
u_int openpic_read(int reg);
sys/arch/macppc/dev/openpic.c
89
void openpic_write(int reg, u_int val);
sys/arch/macppc/dev/smu.c
202
u_int32_t reg, intr, gpio, val;
sys/arch/macppc/dev/smu.c
216
OF_getprop(node, "reg", ®, sizeof reg) <= 0 ||
sys/arch/macppc/dev/smu.c
222
if (bus_space_map(sc->sc_memt, gpio + reg, 1, 0, &sc->sc_gpioh)) {
sys/arch/macppc/dev/smu.c
279
if (OF_getprop(node, "reg", ®, sizeof reg) <= 0 ||
sys/arch/macppc/dev/smu.c
296
fan->reg = reg;
sys/arch/macppc/dev/smu.c
335
if (OF_getprop(node, "reg", ®, sizeof reg) <= 0 ||
sys/arch/macppc/dev/smu.c
352
fan->reg = reg;
sys/arch/macppc/dev/smu.c
417
sensor->reg = val;
sys/arch/macppc/dev/smu.c
49
u_int8_t reg;
sys/arch/macppc/dev/smu.c
63
u_int8_t reg;
sys/arch/macppc/dev/smu.c
657
cmd->data[1] = fan->reg;
sys/arch/macppc/dev/smu.c
678
cmd->data[1] = 0x01 << fan->reg;
sys/arch/macppc/dev/smu.c
679
cmd->data[2] = cmd->data[2 + fan->reg * 2] = (rpm >> 8) & 0xff;
sys/arch/macppc/dev/smu.c
680
cmd->data[3] = cmd->data[3 + fan->reg * 2] = (rpm & 0xff);
sys/arch/macppc/dev/smu.c
685
cmd->data[1] = fan->reg;
sys/arch/macppc/dev/smu.c
701
cmd->data[1] = 0x01 << fan->reg;
sys/arch/macppc/dev/smu.c
702
cmd->data[2] = cmd->data[2 + fan->reg * 2] = (pwm >> 8) & 0xff;
sys/arch/macppc/dev/smu.c
703
cmd->data[3] = cmd->data[3 + fan->reg * 2] = (pwm & 0xff);
sys/arch/macppc/dev/smu.c
708
cmd->data[1] = fan->reg;
sys/arch/macppc/dev/smu.c
728
*rpm = (cmd->data[fan->reg * 2 + 1] << 8) |
sys/arch/macppc/dev/smu.c
729
cmd->data[fan->reg * 2 + 2];
sys/arch/macppc/dev/smu.c
734
cmd->data[1] = fan->reg;
sys/arch/macppc/dev/smu.c
756
cmd->data[1] = 0x01 << fan->reg;
sys/arch/macppc/dev/smu.c
760
*pwm = cmd->data[fan->reg * 2 + 2];
sys/arch/macppc/dev/smu.c
769
*rpm = (cmd->data[fan->reg * 2 + 1] << 8) |
sys/arch/macppc/dev/smu.c
770
cmd->data[fan->reg * 2 + 2];
sys/arch/macppc/dev/smu.c
775
cmd->data[1] = fan->reg;
sys/arch/macppc/dev/smu.c
829
cmd->data[0] = sensor->reg;
sys/arch/macppc/dev/snapper.c
520
uint8_t reg;
sys/arch/macppc/dev/snapper.c
523
reg = snapper_trebletab[(value >> 3) + 2];
sys/arch/macppc/dev/snapper.c
524
if (tas3004_write(sc, DEQ_TREBLE, ®) < 0)
sys/arch/macppc/dev/snapper.c
533
uint8_t reg;
sys/arch/macppc/dev/snapper.c
536
reg = snapper_basstab[(value >> 3) + 2];
sys/arch/macppc/dev/snapper.c
537
if (tas3004_write(sc, DEQ_BASS, ®) < 0)
sys/arch/macppc/dev/snapper.c
633
tas3004_write(struct snapper_softc *sc, u_int reg, const void *data)
sys/arch/macppc/dev/snapper.c
637
KASSERT(reg < sizeof tas3004_regsize);
sys/arch/macppc/dev/snapper.c
638
size = tas3004_regsize[reg];
sys/arch/macppc/dev/snapper.c
641
if (kiic_write(sc->sc_i2c, DEQaddr, reg, data, size))
sys/arch/macppc/dev/snapper.c
647
#define DEQ_WRITE(sc, reg, addr) \
sys/arch/macppc/dev/snapper.c
648
if (tas3004_write(sc, reg, addr)) goto err
sys/arch/macppc/dev/tumbler.c
322
uint8_t reg;
sys/arch/macppc/dev/tumbler.c
325
reg = tumbler_trebletab[(value >> 3) + 2];
sys/arch/macppc/dev/tumbler.c
326
if (tas3001_write(sc, DEQ_TREBLE, ®) < 0)
sys/arch/macppc/dev/tumbler.c
335
uint8_t reg;
sys/arch/macppc/dev/tumbler.c
338
reg = tumbler_basstab[(value >> 3) + 2];
sys/arch/macppc/dev/tumbler.c
339
if (tas3001_write(sc, DEQ_BASS, ®) < 0)
sys/arch/macppc/dev/tumbler.c
398
tas3001_write(struct tumbler_softc *sc, u_int reg, const void *data)
sys/arch/macppc/dev/tumbler.c
402
KASSERT(reg < sizeof tas3001_regsize);
sys/arch/macppc/dev/tumbler.c
403
size = tas3001_regsize[reg];
sys/arch/macppc/dev/tumbler.c
406
if (kiic_write(sc->sc_i2c, DEQaddr, reg, data, size))
sys/arch/macppc/dev/tumbler.c
412
#define DEQ_WRITE(sc, reg, addr) \
sys/arch/macppc/dev/tumbler.c
413
if (tas3001_write(sc, reg, addr)) goto err
sys/arch/macppc/dev/uni_n.c
101
uint32_t rev, reg[2];
sys/arch/macppc/dev/uni_n.c
105
OF_getprop(ca->ca_node, "reg", ®, sizeof(reg));
sys/arch/macppc/dev/uni_n.c
113
sc->sc_baseaddr = mapiodev(reg[1], PAGE_SIZE);
sys/arch/macppc/dev/uni_n.c
115
sc->sc_baseaddr = mapiodev(reg[0], PAGE_SIZE);
sys/arch/macppc/dev/uni_n.c
133
u_int32_t reg[20];
sys/arch/macppc/dev/uni_n.c
152
ca.ca_nreg = OF_getprop(node, "reg", reg, sizeof(reg));
sys/arch/macppc/dev/uni_n.c
153
ca.ca_reg = reg;
sys/arch/macppc/dev/viareg.h
104
write_via_reg(int ign, int reg, int val)
sys/arch/macppc/dev/viareg.h
106
volatile unsigned char *addr = Via1Base + reg;
sys/arch/macppc/dev/viareg.h
72
via_reg_and(int ign, int reg, int val)
sys/arch/macppc/dev/viareg.h
74
volatile unsigned char *addr = Via1Base + reg;
sys/arch/macppc/dev/viareg.h
80
via_reg_or(int ign, int reg, int val)
sys/arch/macppc/dev/viareg.h
82
volatile unsigned char *addr = Via1Base + reg;
sys/arch/macppc/dev/viareg.h
88
via_reg_xor(int ign, int reg, int val)
sys/arch/macppc/dev/viareg.h
90
volatile unsigned char *addr = Via1Base + reg;
sys/arch/macppc/dev/viareg.h
96
read_via_reg(int ign, int reg)
sys/arch/macppc/dev/viareg.h
98
volatile unsigned char *addr = Via1Base + reg;
sys/arch/macppc/dev/wdc_obio.c
591
wdc_obio_read_reg(struct channel_softc *chp, enum wdc_regs reg)
sys/arch/macppc/dev/wdc_obio.c
594
if (reg & _WDC_WRONLY) {
sys/arch/macppc/dev/wdc_obio.c
595
printf ("wdc_obio_read_reg: reading from a write-only register %d\n", reg);
sys/arch/macppc/dev/wdc_obio.c
599
if (reg & _WDC_AUX)
sys/arch/macppc/dev/wdc_obio.c
601
(reg & _WDC_REGMASK) << 4));
sys/arch/macppc/dev/wdc_obio.c
604
(reg & _WDC_REGMASK) << 4));
sys/arch/macppc/dev/wdc_obio.c
609
wdc_obio_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
sys/arch/macppc/dev/wdc_obio.c
612
if (reg & _WDC_RDONLY) {
sys/arch/macppc/dev/wdc_obio.c
613
printf ("wdc_obio_write_reg: writing to a read-only register %d\n", reg);
sys/arch/macppc/dev/wdc_obio.c
617
if (reg & _WDC_AUX)
sys/arch/macppc/dev/wdc_obio.c
619
(reg & _WDC_REGMASK) << 4, val);
sys/arch/macppc/dev/wdc_obio.c
622
(reg & _WDC_REGMASK) << 4, val);
sys/arch/macppc/dev/xlights.c
110
u_int32_t reg[4];
sys/arch/macppc/dev/xlights.c
115
OF_getprop(sc->sc_node, "reg", reg, sizeof(reg));
sys/arch/macppc/dev/zs.c
1017
u_int32_t reg[5];
sys/arch/macppc/dev/zs.c
1030
if (OF_getprop(escc_ch, "reg", reg, sizeof(reg)) < 8)
sys/arch/macppc/dev/zs.c
1032
zs_offset = reg[0];
sys/arch/macppc/dev/zs.c
1033
zs_size = reg[1];
sys/arch/macppc/dev/zs.c
1038
if (OF_getprop(obio, "assigned-addresses", reg, sizeof(reg)) < 12)
sys/arch/macppc/dev/zs.c
1040
zs_conschan = mapiodev(reg[2] + zs_offset, zs_size);
sys/arch/macppc/dev/zs.c
773
zs_read_reg(struct zs_chanstate *cs, u_char reg)
sys/arch/macppc/dev/zs.c
777
out8(cs->cs_reg_csr, reg);
sys/arch/macppc/dev/zs.c
785
zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val)
sys/arch/macppc/dev/zs.c
787
out8(cs->cs_reg_csr, reg);
sys/arch/macppc/include/z8530var.h
117
u_char zs_read_reg(struct zs_chanstate *cs, u_char reg);
sys/arch/macppc/include/z8530var.h
121
void zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val);
sys/arch/macppc/macppc/cpu.c
102
if (reg[0] >= PPC_MAXPROCS)
sys/arch/macppc/macppc/cpu.c
193
int *reg = ca->ca_reg;
sys/arch/macppc/macppc/cpu.c
200
ci = &cpu_info[reg[0]];
sys/arch/macppc/macppc/cpu.c
201
ci->ci_cpuid = reg[0];
sys/arch/macppc/macppc/cpu.c
96
int *reg = ca->ca_reg;
sys/arch/macppc/macppc/mainbus.c
115
nca.ca_reg = reg;
sys/arch/macppc/macppc/mainbus.c
116
reg[0] = cpucnt;
sys/arch/macppc/macppc/mainbus.c
125
nca.ca_reg = reg;
sys/arch/macppc/macppc/mainbus.c
126
reg[0] = 0;
sys/arch/macppc/macppc/mainbus.c
137
len = OF_getprop(node, "reg", reg, sizeof(reg));
sys/arch/macppc/macppc/mainbus.c
142
if ((hh_base = mapiodev(reg[0], reg[1])) != NULL) {
sys/arch/macppc/macppc/mainbus.c
144
unmapiodev(hh_base, reg[1]);
sys/arch/macppc/macppc/mainbus.c
148
nca.ca_reg = reg;
sys/arch/macppc/macppc/mainbus.c
149
reg[0] = 1;
sys/arch/macppc/macppc/mainbus.c
67
int reg[4], cpucnt;
sys/arch/macppc/pci/hpb.c
109
pcireg_t busdata, reg;
sys/arch/macppc/pci/hpb.c
116
reg = pci_conf_read(pc, tag, off + PCI_HT_INTR_DATA);
sys/arch/macppc/pci/hpb.c
122
sc->sc_nirq = ((reg >> 16) & 0xff);
sys/arch/macppc/pci/hpb.c
131
reg = pci_conf_read(pc, tag, off + PCI_HT_INTR_DATA);
sys/arch/macppc/pci/hpb.c
133
pci_conf_write(pc, tag, off + PCI_HT_INTR_DATA, reg | HT_MASK);
sys/arch/macppc/pci/hpb.c
134
irq = (reg >> 16) & 0xff;
sys/arch/macppc/pci/hpb.c
144
reg = pci_conf_read(pc, tag, off + PCI_HT_INTR_DATA);
sys/arch/macppc/pci/hpb.c
147
sc->sc_imap[irq].him_weoi = reg | HT_WAITEOI;
sys/arch/macppc/pci/hpb.c
205
pcireg_t reg;
sys/arch/macppc/pci/hpb.c
215
reg = pci_conf_read(pc, tag, sc->sc_off + PCI_HT_INTR_DATA);
sys/arch/macppc/pci/hpb.c
217
pci_conf_write(pc, tag, sc->sc_off + PCI_HT_INTR_DATA, reg | HT_MASK);
sys/arch/macppc/pci/hpb.c
219
reg &= ~(HT_ACTIVELOW | HT_EOI | HT_MASK);
sys/arch/macppc/pci/hpb.c
221
reg |= HT_ACTIVELOW | HT_EOI;
sys/arch/macppc/pci/hpb.c
223
pci_conf_write(pc, tag, sc->sc_off + PCI_HT_INTR_DATA, reg);
sys/arch/macppc/pci/hpb.c
234
pcireg_t reg;
sys/arch/macppc/pci/hpb.c
243
reg = pci_conf_read(pc, tag, sc->sc_off + PCI_HT_INTR_DATA);
sys/arch/macppc/pci/hpb.c
245
pci_conf_write(pc, tag, sc->sc_off + PCI_HT_INTR_DATA, reg | HT_MASK);
sys/arch/macppc/pci/ht.c
154
pcireg_t reg;
sys/arch/macppc/pci/ht.c
164
reg = bus_space_read_4(sc->sc_iot, sc->sc_config0_ioh, val);
sys/arch/macppc/pci/ht.c
165
reg = letoh32(reg);
sys/arch/macppc/pci/ht.c
171
reg = bus_space_read_4(sc->sc_memt, sc->sc_config0_memh, val);
sys/arch/macppc/pci/ht.c
174
reg = bus_space_read_4(sc->sc_memt, sc->sc_config1_memh, val);
sys/arch/macppc/pci/ht.c
177
printf("ht_conf_read: reg=%x\n", reg);
sys/arch/macppc/pci/ht.c
179
return reg;
sys/arch/macppc/pci/kauaiata.c
121
ca.ca_nreg = OF_getprop(node, "reg", reg, sizeof(reg));
sys/arch/macppc/pci/kauaiata.c
176
ca.ca_reg = reg;
sys/arch/macppc/pci/kauaiata.c
177
reg[0] = 0x2000; /* offset to wdc registers */
sys/arch/macppc/pci/kauaiata.c
178
reg[1] = reg[9] - 0x2000; /* map size of wdc registers */
sys/arch/macppc/pci/kauaiata.c
179
reg[2] = 0x1000; /* offset to dbdma registers */
sys/arch/macppc/pci/kauaiata.c
180
reg[3] = 0x1000; /* map size of dbdma registers */
sys/arch/macppc/pci/kauaiata.c
98
u_int32_t reg[20];
sys/arch/macppc/pci/macobio.c
106
u_int32_t reg[20];
sys/arch/macppc/pci/macobio.c
131
if (OF_getprop(node, "assigned-addresses", reg, sizeof(reg))
sys/arch/macppc/pci/macobio.c
132
== (sizeof (reg[0]) * 5))
sys/arch/macppc/pci/macobio.c
135
heathrow_FCR = mapiodev(reg[2] + HEATHROW_FCR_OFFSET,
sys/arch/macppc/pci/macobio.c
147
if (OF_getprop(node, "assigned-addresses", reg, sizeof(reg))
sys/arch/macppc/pci/macobio.c
148
== (sizeof (reg[0]) * 5))
sys/arch/macppc/pci/macobio.c
149
sc->obiomem = mapiodev(reg[2], 0x100);
sys/arch/macppc/pci/macobio.c
157
if (OF_getprop(node, "assigned-addresses", reg, sizeof(reg)) < 12)
sys/arch/macppc/pci/macobio.c
160
ca.ca_baseaddr = reg[2];
sys/arch/macppc/pci/macobio.c
198
ca.ca_nreg = OF_getprop(child, "reg", reg, sizeof(reg));
sys/arch/macppc/pci/macobio.c
205
ca.ca_reg = reg;
sys/arch/macppc/pci/mpcpcibus.c
444
u_int32_t reg, val = PCITAG_OFFSET(tag);
sys/arch/macppc/pci/mpcpcibus.c
449
reg = val | offset | 1;
sys/arch/macppc/pci/mpcpcibus.c
450
reg |= (offset >> 8) << 28;
sys/arch/macppc/pci/mpcpcibus.c
462
reg = 1 << (dev) | fcn << 8 | offset;
sys/arch/macppc/pci/mpcpcibus.c
469
reg = val | offset | 1;
sys/arch/macppc/pci/mpcpcibus.c
475
reg = 0x80000000 | val | offset;
sys/arch/macppc/pci/mpcpcibus.c
478
return reg;
sys/arch/macppc/pci/mpcpcibus.c
487
u_int32_t reg;
sys/arch/macppc/pci/mpcpcibus.c
501
reg = mpc_gen_config_reg(cpv, tag, offset);
sys/arch/macppc/pci/mpcpcibus.c
503
if (reg == 0xffffffff)
sys/arch/macppc/pci/mpcpcibus.c
519
bus_space_write_4(cp->lc_iot, cp->ioh_cf8, 0, reg);
sys/arch/macppc/pci/mpcpcibus.c
534
printf(" daddr %x reg %x",daddr, reg);
sys/arch/macppc/pci/mpcpcibus.c
546
u_int32_t reg;
sys/arch/macppc/pci/mpcpcibus.c
550
reg = mpc_gen_config_reg(cpv, tag, offset);
sys/arch/macppc/pci/mpcpcibus.c
553
if (reg == 0xffffffff)
sys/arch/macppc/pci/mpcpcibus.c
565
printf(" daddr %x reg %x",daddr, reg);
sys/arch/macppc/pci/mpcpcibus.c
572
bus_space_write_4(cp->lc_iot, cp->ioh_cf8, 0, reg);
sys/arch/macppc/pci/pci_machdep.c
103
if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg))
sys/arch/macppc/pci/pci_machdep.c
106
if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi))
sys/arch/macppc/pci/pci_machdep.c
108
if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi))
sys/arch/macppc/pci/pci_machdep.c
110
if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi))
sys/arch/macppc/pci/pci_machdep.c
139
pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
sys/arch/macppc/pci/pci_machdep.c
142
return (*(pc)->pc_conf_read)(pc->pc_conf_v, tag, reg);
sys/arch/macppc/pci/pci_machdep.c
148
pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
sys/arch/macppc/pci/pci_machdep.c
151
(*(pc)->pc_conf_write)(pc->pc_conf_v, tag, reg, data);
sys/arch/macppc/pci/pci_machdep.c
157
struct ofw_pci_register reg;
sys/arch/macppc/pci/pci_machdep.c
161
if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg))
sys/arch/macppc/pci/pci_machdep.c
173
reg.size_hi = intr[0];
sys/arch/macppc/pci/pci_machdep.c
174
if (ofw_intr_map(OF_parent(node), (uint32_t *)®, intr)) {
sys/arch/macppc/pci/pci_machdep.c
248
struct ofw_pci_register reg;
sys/arch/macppc/pci/pci_machdep.c
281
if (OF_getprop(snode, "reg", ®, sizeof(reg))
sys/arch/macppc/pci/pci_machdep.c
282
< sizeof(reg))
sys/arch/macppc/pci/pci_machdep.c
285
b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi);
sys/arch/macppc/pci/pci_machdep.c
286
d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi);
sys/arch/macppc/pci/pci_machdep.c
287
f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi);
sys/arch/macppc/pci/pci_machdep.c
302
if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg))
sys/arch/macppc/pci/pci_machdep.c
313
b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi);
sys/arch/macppc/pci/pci_machdep.c
314
d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi);
sys/arch/macppc/pci/pci_machdep.c
315
f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi);
sys/arch/macppc/pci/pci_machdep.c
75
struct ofw_pci_register reg;
sys/arch/mips64/include/asm.h
307
#define LOAD_XKPHYS(reg, cca) \
sys/arch/mips64/include/asm.h
308
li reg, cca | 0x10; \
sys/arch/mips64/include/asm.h
309
dsll reg, reg, 59
sys/arch/mips64/include/cpustate.h
32
#define SAVE_REG(reg, offs, base, bo) \
sys/arch/mips64/include/cpustate.h
33
REG_S reg, bo + (REGSZ * offs) (base)
sys/arch/mips64/include/cpustate.h
35
#define RESTORE_REG(reg, offs, base, bo) \
sys/arch/mips64/include/cpustate.h
36
REG_L reg, bo + (REGSZ * offs) (base)
sys/arch/mips64/include/pte.h
83
#define PTE_CLEAR_SWBITS(reg) \
sys/arch/mips64/include/pte.h
87
dins reg, zero, PG_FRAMEBITS, (PTE_BITS - 2 - PG_FRAMEBITS); \
sys/arch/mips64/include/pte.h
90
#define PTE_CLEAR_SWBITS(reg) \
sys/arch/mips64/include/pte.h
92
dsll reg, reg, (64 - PG_FRAMEBITS); \
sys/arch/mips64/include/pte.h
93
dsrl reg, reg, (64 - PG_FRAMEBITS)
sys/arch/mips64/mips64/process_machdep.c
82
process_read_regs(struct proc *p, struct reg *regs)
sys/arch/mips64/mips64/process_machdep.c
97
process_write_regs(struct proc *p, struct reg *regs)
sys/arch/octeon/dev/cn30xxfau.c
100
cn30xxfau_op_store_paddr(int noadd, int reg, int64_t value)
sys/arch/octeon/dev/cn30xxfau.c
106
((uint64_t)(reg & 0x7ff) << 0);
sys/arch/octeon/dev/cn30xxfau.c
84
cn30xxfau_op_load_paddr(int incval, int tagwait, int reg)
sys/arch/octeon/dev/cn30xxfau.c
91
((uint64_t)(reg & 0x7ff) << 0);
sys/arch/octeon/dev/cn30xxfauvar.h
85
int size, int reg)
sys/arch/octeon/dev/cn30xxfauvar.h
93
((uint64_t)(reg & 0x7ff) << 0);
sys/arch/octeon/dev/cn30xxgmx.c
61
#define AGL_GMX_RD8(sc, reg) \
sys/arch/octeon/dev/cn30xxgmx.c
63
(sc)->sc_port_gmx->sc_regh, (reg))
sys/arch/octeon/dev/cn30xxgmx.c
64
#define AGL_GMX_WR8(sc, reg, val) \
sys/arch/octeon/dev/cn30xxgmx.c
66
(sc)->sc_port_gmx->sc_regh, (reg), (val))
sys/arch/octeon/dev/cn30xxgmx.c
67
#define AGL_GMX_PORT_RD8(sc, reg) \
sys/arch/octeon/dev/cn30xxgmx.c
69
(sc)->sc_port_regh, (reg))
sys/arch/octeon/dev/cn30xxgmx.c
70
#define AGL_GMX_PORT_WR8(sc, reg, val) \
sys/arch/octeon/dev/cn30xxgmx.c
72
(sc)->sc_port_regh, (reg), (val))
sys/arch/octeon/dev/cn30xxgmx.c
74
#define PCS_READ_8(sc, reg) \
sys/arch/octeon/dev/cn30xxgmx.c
76
(reg))
sys/arch/octeon/dev/cn30xxgmx.c
77
#define PCS_WRITE_8(sc, reg, val) \
sys/arch/octeon/dev/cn30xxgmx.c
79
(reg), (val))
sys/arch/octeon/dev/cn30xxsmi.c
103
(reg << SMI_CMD_REG_ADR_SHIFT));
sys/arch/octeon/dev/cn30xxsmi.c
121
cn30xxsmi_write(struct cn30xxsmi_softc *sc, int phy_addr, int reg, int value)
sys/arch/octeon/dev/cn30xxsmi.c
131
(reg << SMI_CMD_REG_ADR_SHIFT));
sys/arch/octeon/dev/cn30xxsmi.c
144
phy_addr, reg, value);
sys/arch/octeon/dev/cn30xxsmi.c
167
int reg;
sys/arch/octeon/dev/cn30xxsmi.c
173
reg = OF_getpropint(phynode, "reg", UINT32_MAX);
sys/arch/octeon/dev/cn30xxsmi.c
174
if (reg == UINT32_MAX)
sys/arch/octeon/dev/cn30xxsmi.c
192
reg = cpn100_phys[port];
sys/arch/octeon/dev/cn30xxsmi.c
197
reg = nutm25_phys[port];
sys/arch/octeon/dev/cn30xxsmi.c
207
reg = 7 - port;
sys/arch/octeon/dev/cn30xxsmi.c
212
reg = cam0100_phys[port];
sys/arch/octeon/dev/cn30xxsmi.c
221
*preg = reg;
sys/arch/octeon/dev/cn30xxsmi.c
96
cn30xxsmi_read(struct cn30xxsmi_softc *sc, int phy_addr, int reg)
sys/arch/octeon/dev/cn30xxuart.c
248
volatile uint64_t *reg = (uint64_t *)(handle + (off << 3));
sys/arch/octeon/dev/cn30xxuart.c
250
*reg = value;
sys/arch/octeon/dev/cn30xxuart.c
251
(void)*reg;
sys/arch/octeon/dev/if_cnmac.c
1073
uint64_t reg;
sys/arch/octeon/dev/if_cnmac.c
1083
reg = octeon_xkphys_read_8(PIP_GBL_CFG);
sys/arch/octeon/dev/if_cnmac.c
1084
reg &= ~PIP_GBL_CFG_NIP_SHF_MASK;
sys/arch/octeon/dev/if_cnmac.c
1085
reg |= ETHER_ALIGN << PIP_GBL_CFG_NIP_SHF_SHIFT;
sys/arch/octeon/dev/if_cnmac.c
1086
octeon_xkphys_write_8(PIP_GBL_CFG, reg);
sys/arch/octeon/dev/if_cnmac.c
434
cnmac_mii_readreg(struct device *self, int phy_no, int reg)
sys/arch/octeon/dev/if_cnmac.c
437
return cn30xxsmi_read(sc->sc_smi, phy_no, reg);
sys/arch/octeon/dev/if_cnmac.c
441
cnmac_mii_writereg(struct device *self, int phy_no, int reg, int value)
sys/arch/octeon/dev/if_cnmac.c
444
cn30xxsmi_write(sc->sc_smi, phy_no, reg, value);
sys/arch/octeon/dev/if_ogx.c
1374
ogx_mii_readreg(struct device *self, int phy_no, int reg)
sys/arch/octeon/dev/if_ogx.c
1378
return cn30xxsmi_read(sc->sc_smi, phy_no, reg);
sys/arch/octeon/dev/if_ogx.c
1382
ogx_mii_writereg(struct device *self, int phy_no, int reg, int value)
sys/arch/octeon/dev/if_ogx.c
1386
cn30xxsmi_write(sc->sc_smi, phy_no, reg, value);
sys/arch/octeon/dev/if_ogx.c
182
#define PORT_RD_8(sc, reg) \
sys/arch/octeon/dev/if_ogx.c
183
bus_space_read_8((sc)->sc_iot, (sc)->sc_port_ioh, (reg))
sys/arch/octeon/dev/if_ogx.c
184
#define PORT_WR_8(sc, reg, val) \
sys/arch/octeon/dev/if_ogx.c
185
bus_space_write_8((sc)->sc_iot, (sc)->sc_port_ioh, (reg), (val))
sys/arch/octeon/dev/if_ogx.c
187
#define NEXUS_RD_8(sc, reg) \
sys/arch/octeon/dev/if_ogx.c
188
bus_space_read_8((sc)->sc_iot, (sc)->sc_nexus_ioh, (reg))
sys/arch/octeon/dev/if_ogx.c
189
#define NEXUS_WR_8(sc, reg, val) \
sys/arch/octeon/dev/if_ogx.c
190
bus_space_write_8((sc)->sc_iot, (sc)->sc_nexus_ioh, (reg), (val))
sys/arch/octeon/dev/if_ogx.c
192
#define FPA3_RD_8(node, reg) \
sys/arch/octeon/dev/if_ogx.c
193
bus_space_read_8((node)->node_iot, (node)->node_fpa3, (reg))
sys/arch/octeon/dev/if_ogx.c
194
#define FPA3_WR_8(node, reg, val) \
sys/arch/octeon/dev/if_ogx.c
195
bus_space_write_8((node)->node_iot, (node)->node_fpa3, (reg), (val))
sys/arch/octeon/dev/if_ogx.c
196
#define PKI_RD_8(node, reg) \
sys/arch/octeon/dev/if_ogx.c
197
bus_space_read_8((node)->node_iot, (node)->node_pki, (reg))
sys/arch/octeon/dev/if_ogx.c
198
#define PKI_WR_8(node, reg, val) \
sys/arch/octeon/dev/if_ogx.c
199
bus_space_write_8((node)->node_iot, (node)->node_pki, (reg), (val))
sys/arch/octeon/dev/if_ogx.c
200
#define PKO3_RD_8(node, reg) \
sys/arch/octeon/dev/if_ogx.c
201
bus_space_read_8((node)->node_iot, (node)->node_pko3, (reg))
sys/arch/octeon/dev/if_ogx.c
202
#define PKO3_WR_8(node, reg, val) \
sys/arch/octeon/dev/if_ogx.c
203
bus_space_write_8((node)->node_iot, (node)->node_pko3, (reg), (val))
sys/arch/octeon/dev/if_ogx.c
204
#define SSO_RD_8(node, reg) \
sys/arch/octeon/dev/if_ogx.c
205
bus_space_read_8((node)->node_iot, (node)->node_sso, (reg))
sys/arch/octeon/dev/if_ogx.c
206
#define SSO_WR_8(node, reg, val) \
sys/arch/octeon/dev/if_ogx.c
207
bus_space_write_8((node)->node_iot, (node)->node_sso, (reg), (val))
sys/arch/octeon/dev/octcf.c
154
#define OCTCF_REG_READ(wd, reg) \
sys/arch/octeon/dev/octcf.c
155
bus_space_read_2(wd->sc_iot, wd->sc_ioh, reg & 0x6)
sys/arch/octeon/dev/octcf.c
156
#define OCTCF_REG_WRITE(wd, reg, val) \
sys/arch/octeon/dev/octcf.c
157
bus_space_write_2(wd->sc_iot, wd->sc_ioh, reg & 0x6, val)
sys/arch/octeon/dev/octcit.c
536
uint64_t reg = CIU3_ISC_W1S(MBOX_INTSN(cpuid));
sys/arch/octeon/dev/octcit.c
538
CIU3_WR_8(sc, reg, CIU3_ISC_W1S_RAW);
sys/arch/octeon/dev/octcit.c
539
(void)CIU3_RD_8(sc, reg);
sys/arch/octeon/dev/octcit.c
546
uint64_t reg = CIU3_ISC_W1C(MBOX_INTSN(cpuid));
sys/arch/octeon/dev/octcit.c
548
CIU3_WR_8(sc, reg, CIU3_ISC_W1C_RAW);
sys/arch/octeon/dev/octcit.c
549
(void)CIU3_RD_8(sc, reg);
sys/arch/octeon/dev/octcit.c
68
#define CIU3_RD_8(sc, reg) \
sys/arch/octeon/dev/octcit.c
69
bus_space_read_8((sc)->sc_iot, (sc)->sc_ioh, (reg))
sys/arch/octeon/dev/octcit.c
70
#define CIU3_WR_8(sc, reg, val) \
sys/arch/octeon/dev/octcit.c
71
bus_space_write_8((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/octeon/dev/octgpio.c
142
uint64_t output_sel, reg, value;
sys/arch/octeon/dev/octgpio.c
148
reg = GPIO_XBIT_CFG(pin - sc->sc_xbit);
sys/arch/octeon/dev/octgpio.c
150
reg = GPIO_BIT_CFG(pin);
sys/arch/octeon/dev/octgpio.c
152
value = GPIO_RD_8(sc, reg);
sys/arch/octeon/dev/octgpio.c
173
GPIO_WR_8(sc, reg, value);
sys/arch/octeon/dev/octgpio.c
47
#define GPIO_RD_8(sc, reg) \
sys/arch/octeon/dev/octgpio.c
48
bus_space_read_8((sc)->sc_iot, (sc)->sc_ioh, (reg))
sys/arch/octeon/dev/octgpio.c
49
#define GPIO_WR_8(sc, reg, val) \
sys/arch/octeon/dev/octgpio.c
50
bus_space_write_8((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/octeon/dev/octiic.c
345
uint32_t reg[1];
sys/arch/octeon/dev/octiic.c
351
memset(reg, 0, sizeof(reg));
sys/arch/octeon/dev/octiic.c
358
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/arch/octeon/dev/octiic.c
363
ia.ia_addr = reg[0];
sys/arch/octeon/dev/octiic.c
371
octiic_reg_read(struct octiic_softc *sc, uint8_t reg, uint8_t *pval)
sys/arch/octeon/dev/octiic.c
378
((uint64_t)reg << TWSI_SW_TWSI_EOP_IA_S));
sys/arch/octeon/dev/octiic.c
394
octiic_reg_write(struct octiic_softc *sc, uint8_t reg, uint8_t val)
sys/arch/octeon/dev/octiic.c
401
((uint64_t)reg << TWSI_SW_TWSI_EOP_IA_S) | val);
sys/arch/octeon/dev/octiic.c
77
#define TWSI_RD_8(sc, reg) \
sys/arch/octeon/dev/octiic.c
78
bus_space_read_8((sc)->sc_iot, (sc)->sc_ioh, (reg))
sys/arch/octeon/dev/octiic.c
79
#define TWSI_WR_8(sc, reg, val) \
sys/arch/octeon/dev/octiic.c
80
bus_space_write_8((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/octeon/dev/octmmc.c
180
uint64_t reg;
sys/arch/octeon/dev/octmmc.c
238
reg = MMC_RD_8(sc, MIO_EMM_CFG);
sys/arch/octeon/dev/octmmc.c
239
reg &= ~((1u << OCTMMC_MAX_BUSES) - 1);
sys/arch/octeon/dev/octmmc.c
240
MMC_WR_8(sc, MIO_EMM_CFG, reg);
sys/arch/octeon/dev/octmmc.c
243
reg = MMC_RD_8(sc, MIO_EMM_INT);
sys/arch/octeon/dev/octmmc.c
244
MMC_WR_8(sc, MIO_EMM_INT, reg);
sys/arch/octeon/dev/octmmc.c
401
uint64_t reg;
sys/arch/octeon/dev/octmmc.c
423
reg = MMC_RD_8(sc, MIO_EMM_CFG);
sys/arch/octeon/dev/octmmc.c
424
reg |= 1u << bus->bus_id;
sys/arch/octeon/dev/octmmc.c
425
MMC_WR_8(sc, MIO_EMM_CFG, reg);
sys/arch/octeon/dev/octmmc.c
59
#define MMC_RD_8(sc, reg) \
sys/arch/octeon/dev/octmmc.c
60
bus_space_read_8((sc)->sc_iot, (sc)->sc_mmc_ioh, (reg))
sys/arch/octeon/dev/octmmc.c
61
#define MMC_WR_8(sc, reg, val) \
sys/arch/octeon/dev/octmmc.c
62
bus_space_write_8((sc)->sc_iot, (sc)->sc_mmc_ioh, (reg), (val))
sys/arch/octeon/dev/octmmc.c
63
#define DMA_WR_8(sc, reg, val) \
sys/arch/octeon/dev/octmmc.c
64
bus_space_write_8((sc)->sc_iot, (sc)->sc_dma_ioh, (reg), (val))
sys/arch/octeon/dev/octmmc.c
65
#define FIFO_WR_8(sc, reg, val) \
sys/arch/octeon/dev/octmmc.c
66
bus_space_write_8((sc)->sc_iot, (sc)->sc_fifo_ioh, (reg), (val))
sys/arch/octeon/dev/octrtc.c
196
twsi.reg = 0;
sys/arch/octeon/dev/octrtc.c
205
octeon_xkphys_write_8(MIO_TWS_SW_TWSI, twsi.reg);
sys/arch/octeon/dev/octrtc.c
209
twsi.reg = octeon_xkphys_read_8(MIO_TWS_SW_TWSI);
sys/arch/octeon/dev/octrtc.c
211
DPRINTF(("%#llX ", twsi.reg));
sys/arch/octeon/dev/octrtc.c
290
twsi.reg = 0;
sys/arch/octeon/dev/octrtc.c
298
octeon_xkphys_write_8(MIO_TWS_SW_TWSI, twsi.reg);
sys/arch/octeon/dev/octrtc.c
301
twsi.reg = octeon_xkphys_read_8(MIO_TWS_SW_TWSI);
sys/arch/octeon/dev/octrtc.c
65
uint64_t reg;
sys/arch/octeon/dev/octsctl.c
101
OF_getpropintarray(child, "reg", reg, sizeof(reg));
sys/arch/octeon/dev/octsctl.c
102
child_reg.addr = ((uint64_t)reg[0] << 32) | reg[1];
sys/arch/octeon/dev/octsctl.c
103
child_reg.size = ((uint64_t)reg[2] << 32) | reg[3];
sys/arch/octeon/dev/octsctl.c
73
uint32_t reg[4];
sys/arch/octeon/dev/octsctl.c
97
if (OF_getproplen(child, "reg") != sizeof(reg)) {
sys/arch/octeon/dev/octuctl.c
206
uint32_t reg[4];
sys/arch/octeon/dev/octuctl.c
260
if (OF_getproplen(node, "reg") != sizeof(reg))
sys/arch/octeon/dev/octuctl.c
263
OF_getpropintarray(node, "reg", reg, sizeof(reg));
sys/arch/octeon/dev/octuctl.c
264
uaa.aa_reg.addr = (((uint64_t)reg[0]) << 32) | reg[1];
sys/arch/octeon/dev/octuctl.c
265
uaa.aa_reg.size = (((uint64_t)reg[2]) << 32) | reg[3];
sys/arch/octeon/dev/octxctl.c
111
uint32_t reg[4];
sys/arch/octeon/dev/octxctl.c
125
if (OF_getproplen(child, "reg") != sizeof(reg)) {
sys/arch/octeon/dev/octxctl.c
129
OF_getpropintarray(child, "reg", reg, sizeof(reg));
sys/arch/octeon/dev/octxctl.c
130
child_reg.addr = ((uint64_t)reg[0] << 32) | reg[1];
sys/arch/octeon/dev/octxctl.c
131
child_reg.size = ((uint64_t)reg[2] << 32) | reg[3];
sys/arch/octeon/dev/octxctl.c
329
octxctl_dwc3_init(struct octxctl_softc *sc, struct fdt_reg *reg)
sys/arch/octeon/dev/octxctl.c
336
if (bus_space_map(sc->sc_iot, reg->addr, reg->size, 0, &ioh) != 0) {
sys/arch/octeon/dev/octxctl.c
375
bus_space_unmap(sc->sc_iot, ioh, reg->size);
sys/arch/octeon/dev/octxctl.c
38
#define XCTL_RD_8(sc, reg) \
sys/arch/octeon/dev/octxctl.c
39
bus_space_read_8((sc)->sc_iot, (sc)->sc_ioh, (reg))
sys/arch/octeon/dev/octxctl.c
40
#define XCTL_WR_8(sc, reg, val) \
sys/arch/octeon/dev/octxctl.c
41
bus_space_write_8((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/octeon/dev/ogxnexus.c
43
#define NEXUS_RD_8(sc, reg) \
sys/arch/octeon/dev/ogxnexus.c
44
bus_space_write_8((sc)->sc_iot, (sc)->sc_ioh, (reg))
sys/arch/octeon/dev/ogxnexus.c
45
#define NEXUS_WR_8(sc, reg, val) \
sys/arch/octeon/dev/ogxnexus.c
46
bus_space_write_8((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/octeon/dev/simplebus.c
154
uint32_t *cell, *reg;
sys/arch/octeon/dev/simplebus.c
174
reg = malloc(len, M_TEMP, M_WAITOK);
sys/arch/octeon/dev/simplebus.c
175
OF_getpropintarray(node, "reg", reg, len);
sys/arch/octeon/dev/simplebus.c
181
for (i = 0, cell = reg; i < len / line; i++) {
sys/arch/octeon/dev/simplebus.c
198
free(reg, M_TEMP, len);
sys/arch/octeon/include/pci_machdep.h
103
tag, reg, val);
sys/arch/octeon/include/pci_machdep.h
104
(*(pc)->pc_conf_write)(pc->pc_conf_v, tag, reg, val);
sys/arch/octeon/include/pci_machdep.h
84
pci_conf_read_db(void *cookie, pcitag_t tag, int reg,
sys/arch/octeon/include/pci_machdep.h
90
val = (*(pc)->pc_conf_read)(pc->pc_conf_v, tag, reg);
sys/arch/octeon/include/pci_machdep.h
92
tag, reg, val);
sys/arch/octeon/include/pci_machdep.h
97
pci_conf_write_db(void *cookie, pcitag_t tag, int reg, pcireg_t val,
sys/arch/octeon/octeon/machdep.c
1064
uint64_t reg = (uint64_t)tc->tc_priv;
sys/arch/octeon/octeon/machdep.c
1066
return octeon_xkphys_read_8(reg);
sys/arch/powerpc/ddb/db_disasm.c
1001
reg = "ibat2u";
sys/arch/powerpc/ddb/db_disasm.c
1004
reg = "ibat2l";
sys/arch/powerpc/ddb/db_disasm.c
1007
reg = "ibat3u";
sys/arch/powerpc/ddb/db_disasm.c
1010
reg = "ibat3l";
sys/arch/powerpc/ddb/db_disasm.c
1013
reg = "dbat0u";
sys/arch/powerpc/ddb/db_disasm.c
1016
reg = "dbat0l";
sys/arch/powerpc/ddb/db_disasm.c
1019
reg = "dbat1u";
sys/arch/powerpc/ddb/db_disasm.c
1022
reg = "dbat1l";
sys/arch/powerpc/ddb/db_disasm.c
1025
reg = "dbat2u";
sys/arch/powerpc/ddb/db_disasm.c
1028
reg = "dbat2l";
sys/arch/powerpc/ddb/db_disasm.c
1031
reg = "dbat3u";
sys/arch/powerpc/ddb/db_disasm.c
1034
reg = "dbat3l";
sys/arch/powerpc/ddb/db_disasm.c
1037
reg = "dabr";
sys/arch/powerpc/ddb/db_disasm.c
1040
reg = 0;
sys/arch/powerpc/ddb/db_disasm.c
1042
if (reg == 0) {
sys/arch/powerpc/ddb/db_disasm.c
1046
snprintf(lbuf, sizeof (lbuf), "%s", reg);
sys/arch/powerpc/ddb/db_disasm.c
1056
char *reg = NULL;
sys/arch/powerpc/ddb/db_disasm.c
1063
reg = "tbl";
sys/arch/powerpc/ddb/db_disasm.c
1066
reg = "tbu";
sys/arch/powerpc/ddb/db_disasm.c
1069
reg = 0;
sys/arch/powerpc/ddb/db_disasm.c
1071
if (reg == NULL) {
sys/arch/powerpc/ddb/db_disasm.c
1075
snprintf(lbuf, sizeof (lbuf), "%s", reg);
sys/arch/powerpc/ddb/db_disasm.c
933
char *reg;
sys/arch/powerpc/ddb/db_disasm.c
941
reg = "xer";
sys/arch/powerpc/ddb/db_disasm.c
944
reg = "lr";
sys/arch/powerpc/ddb/db_disasm.c
947
reg = "ctr";
sys/arch/powerpc/ddb/db_disasm.c
950
reg = "dsisr";
sys/arch/powerpc/ddb/db_disasm.c
953
reg = "dar";
sys/arch/powerpc/ddb/db_disasm.c
956
reg = "dec";
sys/arch/powerpc/ddb/db_disasm.c
959
reg = "sdr1";
sys/arch/powerpc/ddb/db_disasm.c
962
reg = "srr0";
sys/arch/powerpc/ddb/db_disasm.c
965
reg = "srr1";
sys/arch/powerpc/ddb/db_disasm.c
968
reg = "SPRG0";
sys/arch/powerpc/ddb/db_disasm.c
971
reg = "SPRG1";
sys/arch/powerpc/ddb/db_disasm.c
974
reg = "SPRG3";
sys/arch/powerpc/ddb/db_disasm.c
977
reg = "SPRG3";
sys/arch/powerpc/ddb/db_disasm.c
980
reg = "asr";
sys/arch/powerpc/ddb/db_disasm.c
983
reg = "aer";
sys/arch/powerpc/ddb/db_disasm.c
986
reg = "pvr";
sys/arch/powerpc/ddb/db_disasm.c
989
reg = "ibat0u";
sys/arch/powerpc/ddb/db_disasm.c
992
reg = "ibat0l";
sys/arch/powerpc/ddb/db_disasm.c
995
reg = "ibat1u";
sys/arch/powerpc/ddb/db_disasm.c
998
reg = "ibat1l";
sys/arch/powerpc/include/asm.h
100
twne reg, %r10
sys/arch/powerpc/include/asm.h
101
# define RETGUARD_SAVE(reg, loc) \
sys/arch/powerpc/include/asm.h
102
stw reg, loc
sys/arch/powerpc/include/asm.h
103
# define RETGUARD_LOAD(reg, loc) \
sys/arch/powerpc/include/asm.h
104
lwz reg, loc
sys/arch/powerpc/include/asm.h
118
# define RETGUARD_LOAD_RANDOM(x, reg)
sys/arch/powerpc/include/asm.h
119
# define RETGUARD_SETUP(x, reg, retreg)
sys/arch/powerpc/include/asm.h
120
# define RETGUARD_SETUP_LATE(x, reg, retreg)
sys/arch/powerpc/include/asm.h
121
# define RETGUARD_CHECK(x, reg, retreg)
sys/arch/powerpc/include/asm.h
122
# define RETGUARD_SAVE(reg, loc)
sys/arch/powerpc/include/asm.h
123
# define RETGUARD_LOAD(reg, loc)
sys/arch/powerpc/include/asm.h
79
# define RETGUARD_LOAD_RANDOM(x, reg) \
sys/arch/powerpc/include/asm.h
81
66: mflr reg; \
sys/arch/powerpc/include/asm.h
82
addis reg, reg, (__retguard_ ## x - 66b)@ha; \
sys/arch/powerpc/include/asm.h
83
lwz reg, ((__retguard_ ## x - 66b)@l)(reg)
sys/arch/powerpc/include/asm.h
85
# define RETGUARD_LOAD_RANDOM(x, reg) \
sys/arch/powerpc/include/asm.h
86
lis reg, (__retguard_ ## x)@ha; \
sys/arch/powerpc/include/asm.h
87
lwz reg, ((__retguard_ ## x)@l)(reg)
sys/arch/powerpc/include/asm.h
89
# define RETGUARD_SETUP(x, reg, retreg) \
sys/arch/powerpc/include/asm.h
91
RETGUARD_SETUP_LATE(x, reg, retreg)
sys/arch/powerpc/include/asm.h
92
# define RETGUARD_SETUP_LATE(x, reg, retreg) \
sys/arch/powerpc/include/asm.h
94
RETGUARD_LOAD_RANDOM(x, reg); \
sys/arch/powerpc/include/asm.h
95
xor reg, reg, retreg
sys/arch/powerpc/include/asm.h
96
# define RETGUARD_CHECK(x, reg, retreg) \
sys/arch/powerpc/include/asm.h
97
xor reg, reg, retreg; \
sys/arch/powerpc/powerpc/process_machdep.c
121
process_write_regs(struct proc *p, struct reg *regs)
sys/arch/powerpc/powerpc/process_machdep.c
46
process_read_regs(struct proc *p, struct reg *regs)
sys/arch/powerpc/powerpc/trap.c
105
#define SAVE_VEC_REG(reg, addr) \
sys/arch/powerpc/powerpc/trap.c
106
__asm__ volatile ("stvxl %0, 0, %1" :: "n"(reg),"r" (addr));
sys/arch/powerpc/powerpc/trap.c
182
#define LOAD_VEC_REG(reg, addr) \
sys/arch/powerpc/powerpc/trap.c
183
__asm__ volatile ("lvxl %0, 0, %1" :: "n"(reg), "r" (addr));
sys/arch/powerpc/powerpc/trap.c
581
int reg;
sys/arch/powerpc/powerpc/trap.c
587
reg = EXC_ALI_RST(frame->dsisr);
sys/arch/powerpc/powerpc/trap.c
588
fpr = &p->p_addr->u_pcb.pcb_fpu.fpr[reg];
sys/arch/powerpc64/dev/mainbus.c
205
uint32_t *cell, *reg;
sys/arch/powerpc64/dev/mainbus.c
228
reg = malloc(len, M_TEMP, M_WAITOK);
sys/arch/powerpc64/dev/mainbus.c
229
OF_getpropintarray(node, "reg", reg, len);
sys/arch/powerpc64/dev/mainbus.c
235
for (i = 0, cell = reg; i < len / line; i++) {
sys/arch/powerpc64/dev/mainbus.c
252
free(reg, M_TEMP, len);
sys/arch/powerpc64/dev/pci_machdep.c
100
KASSERT(vec <= PCI_MSIX_MC_TBLSZ(reg));
sys/arch/powerpc64/dev/pci_machdep.c
116
pci_conf_write(pc, tag, off, reg | PCI_MSIX_MC_MSIXE);
sys/arch/powerpc64/dev/pci_machdep.c
124
pcireg_t reg;
sys/arch/powerpc64/dev/pci_machdep.c
127
pci_get_capability(pc, tag, PCI_CAP_MSI, NULL, ®) == 0)
sys/arch/powerpc64/dev/pci_machdep.c
132
ihp->ih_type = (reg & PCI_MSI_MC_C64) ? PCI_MSI64 : PCI_MSI32;
sys/arch/powerpc64/dev/pci_machdep.c
143
pcireg_t reg, table, type;
sys/arch/powerpc64/dev/pci_machdep.c
147
pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
sys/arch/powerpc64/dev/pci_machdep.c
150
if (vec > PCI_MSIX_MC_TBLSZ(reg))
sys/arch/powerpc64/dev/pci_machdep.c
31
pcireg_t reg;
sys/arch/powerpc64/dev/pci_machdep.c
34
if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0)
sys/arch/powerpc64/dev/pci_machdep.c
37
if (reg & PCI_MSI_MC_C64) {
sys/arch/powerpc64/dev/pci_machdep.c
45
pci_conf_write(pc, tag, off, reg | PCI_MSI_MC_MSIE);
sys/arch/powerpc64/dev/pci_machdep.c
53
pcireg_t reg, table, type;
sys/arch/powerpc64/dev/pci_machdep.c
57
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
sys/arch/powerpc64/dev/pci_machdep.c
63
tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
sys/arch/powerpc64/dev/pci_machdep.c
78
pcireg_t reg;
sys/arch/powerpc64/dev/pci_machdep.c
81
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0)
sys/arch/powerpc64/dev/pci_machdep.c
84
tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
sys/arch/powerpc64/dev/pci_machdep.c
93
pcireg_t reg;
sys/arch/powerpc64/dev/pci_machdep.c
97
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
sys/arch/powerpc64/dev/phb.c
506
uint32_t reg[5];
sys/arch/powerpc64/dev/phb.c
514
reg, sizeof(reg)) != sizeof(reg))
sys/arch/powerpc64/dev/phb.c
517
if (reg[0] == phys_hi)
sys/arch/powerpc64/dev/phb.c
557
phb_conf_read(void *v, pcitag_t tag, int reg)
sys/arch/powerpc64/dev/phb.c
567
tag, reg, opal_phys(&data));
sys/arch/powerpc64/dev/phb.c
585
phb_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
sys/arch/powerpc64/dev/phb.c
590
opal_pci_config_write_word(sc->sc_phb_id, tag, reg, data);
sys/arch/powerpc64/dev/phb.c
680
uint32_t reg[4];
sys/arch/powerpc64/dev/phb.c
685
reg[0] = bus << 16 | dev << 11 | fn << 8;
sys/arch/powerpc64/dev/phb.c
686
reg[1] = reg[2] = 0;
sys/arch/powerpc64/dev/phb.c
687
reg[3] = ih.ih_intrpin;
sys/arch/powerpc64/dev/phb.c
694
cookie = fdt_intr_establish_imap(node, reg, sizeof(reg),
sys/arch/powerpc64/include/asm.h
63
# define RETGUARD_SETUP(x, reg) \
sys/arch/powerpc64/include/asm.h
66
addis reg, %r2, (__retguard_ ## x)@toc@ha; \
sys/arch/powerpc64/include/asm.h
67
ld reg, ((__retguard_ ## x)@toc@l)(reg); \
sys/arch/powerpc64/include/asm.h
68
xor reg, reg, %r0
sys/arch/powerpc64/include/asm.h
69
# define RETGUARD_CHECK(x, reg) \
sys/arch/powerpc64/include/asm.h
71
xor reg, reg, %r0; \
sys/arch/powerpc64/include/asm.h
74
tdne reg, %r12
sys/arch/powerpc64/include/asm.h
75
# define RETGUARD_SAVE(reg, loc) \
sys/arch/powerpc64/include/asm.h
76
std reg, loc
sys/arch/powerpc64/include/asm.h
77
# define RETGUARD_LOAD(reg, loc) \
sys/arch/powerpc64/include/asm.h
78
ld reg, loc
sys/arch/powerpc64/include/asm.h
92
# define RETGUARD_SETUP(x, reg)
sys/arch/powerpc64/include/asm.h
93
# define RETGUARD_CHECK(x, reg)
sys/arch/powerpc64/include/asm.h
94
# define RETGUARD_SAVE(reg, loc)
sys/arch/powerpc64/include/asm.h
95
# define RETGUARD_LOAD(reg, loc)
sys/arch/powerpc64/powerpc64/db_disasm.c
1001
reg = "ibat2u";
sys/arch/powerpc64/powerpc64/db_disasm.c
1004
reg = "ibat2l";
sys/arch/powerpc64/powerpc64/db_disasm.c
1007
reg = "ibat3u";
sys/arch/powerpc64/powerpc64/db_disasm.c
1010
reg = "ibat3l";
sys/arch/powerpc64/powerpc64/db_disasm.c
1013
reg = "dbat0u";
sys/arch/powerpc64/powerpc64/db_disasm.c
1016
reg = "dbat0l";
sys/arch/powerpc64/powerpc64/db_disasm.c
1019
reg = "dbat1u";
sys/arch/powerpc64/powerpc64/db_disasm.c
1022
reg = "dbat1l";
sys/arch/powerpc64/powerpc64/db_disasm.c
1025
reg = "dbat2u";
sys/arch/powerpc64/powerpc64/db_disasm.c
1028
reg = "dbat2l";
sys/arch/powerpc64/powerpc64/db_disasm.c
1031
reg = "dbat3u";
sys/arch/powerpc64/powerpc64/db_disasm.c
1034
reg = "dbat3l";
sys/arch/powerpc64/powerpc64/db_disasm.c
1037
reg = "dabr";
sys/arch/powerpc64/powerpc64/db_disasm.c
1040
reg = 0;
sys/arch/powerpc64/powerpc64/db_disasm.c
1042
if (reg == 0) {
sys/arch/powerpc64/powerpc64/db_disasm.c
1046
snprintf(lbuf, sizeof (lbuf), "%s", reg);
sys/arch/powerpc64/powerpc64/db_disasm.c
1056
char *reg = NULL;
sys/arch/powerpc64/powerpc64/db_disasm.c
1063
reg = "tbl";
sys/arch/powerpc64/powerpc64/db_disasm.c
1066
reg = "tbu";
sys/arch/powerpc64/powerpc64/db_disasm.c
1069
reg = 0;
sys/arch/powerpc64/powerpc64/db_disasm.c
1071
if (reg == NULL) {
sys/arch/powerpc64/powerpc64/db_disasm.c
1075
snprintf(lbuf, sizeof (lbuf), "%s", reg);
sys/arch/powerpc64/powerpc64/db_disasm.c
933
char *reg;
sys/arch/powerpc64/powerpc64/db_disasm.c
941
reg = "xer";
sys/arch/powerpc64/powerpc64/db_disasm.c
944
reg = "lr";
sys/arch/powerpc64/powerpc64/db_disasm.c
947
reg = "ctr";
sys/arch/powerpc64/powerpc64/db_disasm.c
950
reg = "dsisr";
sys/arch/powerpc64/powerpc64/db_disasm.c
953
reg = "dar";
sys/arch/powerpc64/powerpc64/db_disasm.c
956
reg = "dec";
sys/arch/powerpc64/powerpc64/db_disasm.c
959
reg = "sdr1";
sys/arch/powerpc64/powerpc64/db_disasm.c
962
reg = "srr0";
sys/arch/powerpc64/powerpc64/db_disasm.c
965
reg = "srr1";
sys/arch/powerpc64/powerpc64/db_disasm.c
968
reg = "SPRG0";
sys/arch/powerpc64/powerpc64/db_disasm.c
971
reg = "SPRG1";
sys/arch/powerpc64/powerpc64/db_disasm.c
974
reg = "SPRG3";
sys/arch/powerpc64/powerpc64/db_disasm.c
977
reg = "SPRG3";
sys/arch/powerpc64/powerpc64/db_disasm.c
980
reg = "asr";
sys/arch/powerpc64/powerpc64/db_disasm.c
983
reg = "aer";
sys/arch/powerpc64/powerpc64/db_disasm.c
986
reg = "pvr";
sys/arch/powerpc64/powerpc64/db_disasm.c
989
reg = "ibat0u";
sys/arch/powerpc64/powerpc64/db_disasm.c
992
reg = "ibat0l";
sys/arch/powerpc64/powerpc64/db_disasm.c
995
reg = "ibat1u";
sys/arch/powerpc64/powerpc64/db_disasm.c
998
reg = "ibat1l";
sys/arch/powerpc64/powerpc64/intr.c
334
fdt_intr_establish_imap(int node, int *reg, int nreg, int level,
sys/arch/powerpc64/powerpc64/intr.c
337
return fdt_intr_establish_imap_cpu(node, reg, nreg, level, NULL,
sys/arch/powerpc64/powerpc64/intr.c
342
fdt_intr_establish_imap_cpu(int node, int *reg, int nreg, int level,
sys/arch/powerpc64/powerpc64/intr.c
379
(reg[0] & map_mask[0]) == cell[0] &&
sys/arch/powerpc64/powerpc64/intr.c
380
(reg[1] & map_mask[1]) == cell[1] &&
sys/arch/powerpc64/powerpc64/intr.c
381
(reg[2] & map_mask[2]) == cell[2] &&
sys/arch/powerpc64/powerpc64/intr.c
382
(reg[3] & map_mask[3]) == cell[3] &&
sys/arch/powerpc64/powerpc64/machdep.c
187
struct fdt_reg reg;
sys/arch/powerpc64/powerpc64/machdep.c
283
if (fdt_get_reg(node, i, ®))
sys/arch/powerpc64/powerpc64/machdep.c
285
if (reg.size == 0)
sys/arch/powerpc64/powerpc64/machdep.c
287
memreg_add(®);
sys/arch/powerpc64/powerpc64/machdep.c
288
physmem += atop(reg.size);
sys/arch/powerpc64/powerpc64/machdep.c
289
physmax = MAX(physmax, reg.addr + reg.size);
sys/arch/powerpc64/powerpc64/machdep.c
298
if (fdt_get_reg(node, 0, ®))
sys/arch/powerpc64/powerpc64/machdep.c
300
if (reg.size == 0)
sys/arch/powerpc64/powerpc64/machdep.c
302
memreg_remove(®);
sys/arch/powerpc64/powerpc64/machdep.c
307
reg.addr = trunc_page(EXC_RSVD);
sys/arch/powerpc64/powerpc64/machdep.c
308
reg.size = round_page(EXC_END);
sys/arch/powerpc64/powerpc64/machdep.c
309
memreg_remove(®);
sys/arch/powerpc64/powerpc64/machdep.c
312
reg.addr = trunc_page((paddr_t)_start);
sys/arch/powerpc64/powerpc64/machdep.c
313
reg.size = round_page((paddr_t)_end) - reg.addr;
sys/arch/powerpc64/powerpc64/machdep.c
314
memreg_remove(®);
sys/arch/powerpc64/powerpc64/machdep.c
317
reg.addr = trunc_page((paddr_t)fdt);
sys/arch/powerpc64/powerpc64/machdep.c
318
reg.size = round_page((paddr_t)fdt + fdt_get_size(fdt)) - reg.addr;
sys/arch/powerpc64/powerpc64/machdep.c
319
memreg_remove(®);
sys/arch/powerpc64/powerpc64/machdep.c
356
memreg_add(const struct fdt_reg *reg)
sys/arch/powerpc64/powerpc64/machdep.c
361
if (reg->addr == memreg[i].addr + memreg[i].size) {
sys/arch/powerpc64/powerpc64/machdep.c
362
memreg[i].size += reg->size;
sys/arch/powerpc64/powerpc64/machdep.c
365
if (reg->addr + reg->size == memreg[i].addr) {
sys/arch/powerpc64/powerpc64/machdep.c
366
memreg[i].addr = reg->addr;
sys/arch/powerpc64/powerpc64/machdep.c
367
memreg[i].size += reg->size;
sys/arch/powerpc64/powerpc64/machdep.c
375
memreg[nmemreg++] = *reg;
sys/arch/powerpc64/powerpc64/machdep.c
379
memreg_remove(const struct fdt_reg *reg)
sys/arch/powerpc64/powerpc64/machdep.c
381
uint64_t start = reg->addr;
sys/arch/powerpc64/powerpc64/machdep.c
382
uint64_t end = reg->addr + reg->size;
sys/arch/powerpc64/powerpc64/pmap.c
921
struct fdt_reg reg;
sys/arch/powerpc64/powerpc64/pmap.c
930
reg.addr = start;
sys/arch/powerpc64/powerpc64/pmap.c
931
reg.size = end - start;
sys/arch/powerpc64/powerpc64/pmap.c
932
memreg_remove(®);
sys/arch/powerpc64/powerpc64/process_machdep.c
31
process_read_regs(struct proc *p, struct reg *regs)
sys/arch/powerpc64/powerpc64/process_machdep.c
97
process_write_regs(struct proc *p, struct reg *regs)
sys/arch/riscv64/dev/mainbus.c
190
uint32_t *cell, *reg;
sys/arch/riscv64/dev/mainbus.c
213
reg = malloc(len, M_TEMP, M_WAITOK);
sys/arch/riscv64/dev/mainbus.c
214
OF_getpropintarray(node, "reg", reg, len);
sys/arch/riscv64/dev/mainbus.c
220
for (i = 0, cell = reg; i < len / line; i++) {
sys/arch/riscv64/dev/mainbus.c
237
free(reg, M_TEMP, len);
sys/arch/riscv64/dev/mpfclock.c
90
#define HREAD4(sc, reg) \
sys/arch/riscv64/dev/mpfclock.c
91
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/riscv64/dev/mpfclock.c
92
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/mpfclock.c
93
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/mpfgpio.c
65
#define HREAD4(sc, reg) \
sys/arch/riscv64/dev/mpfgpio.c
66
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/riscv64/dev/mpfgpio.c
67
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/mpfgpio.c
68
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/mpfiic.c
348
uint32_t reg[1];
sys/arch/riscv64/dev/mpfiic.c
358
memset(reg, 0, sizeof(reg));
sys/arch/riscv64/dev/mpfiic.c
359
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/arch/riscv64/dev/mpfiic.c
371
ia.ia_addr = bemtoh32(®[0]);
sys/arch/riscv64/dev/mpfiic.c
81
#define HREAD4(sc, reg) \
sys/arch/riscv64/dev/mpfiic.c
82
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/riscv64/dev/mpfiic.c
83
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/mpfiic.c
84
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/pci_machdep.c
100
KASSERT(vec <= PCI_MSIX_MC_TBLSZ(reg));
sys/arch/riscv64/dev/pci_machdep.c
116
pci_conf_write(pc, tag, off, reg | PCI_MSIX_MC_MSIXE);
sys/arch/riscv64/dev/pci_machdep.c
150
pcireg_t reg, table, type;
sys/arch/riscv64/dev/pci_machdep.c
154
pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
sys/arch/riscv64/dev/pci_machdep.c
157
if (vec > PCI_MSIX_MC_TBLSZ(reg))
sys/arch/riscv64/dev/pci_machdep.c
31
pcireg_t reg;
sys/arch/riscv64/dev/pci_machdep.c
34
if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0)
sys/arch/riscv64/dev/pci_machdep.c
37
if (reg & PCI_MSI_MC_C64) {
sys/arch/riscv64/dev/pci_machdep.c
45
pci_conf_write(pc, tag, off, reg | PCI_MSI_MC_MSIE);
sys/arch/riscv64/dev/pci_machdep.c
53
pcireg_t reg, table, type;
sys/arch/riscv64/dev/pci_machdep.c
57
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
sys/arch/riscv64/dev/pci_machdep.c
63
tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
sys/arch/riscv64/dev/pci_machdep.c
78
pcireg_t reg;
sys/arch/riscv64/dev/pci_machdep.c
81
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0)
sys/arch/riscv64/dev/pci_machdep.c
84
tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
sys/arch/riscv64/dev/pci_machdep.c
93
pcireg_t reg;
sys/arch/riscv64/dev/pci_machdep.c
97
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
sys/arch/riscv64/dev/sfclock.c
125
uint32_t reg;
sys/arch/riscv64/dev/sfclock.c
127
reg = HREAD4(sc, off);
sys/arch/riscv64/dev/sfclock.c
128
pllr = PLLCFG_PLLR(reg);
sys/arch/riscv64/dev/sfclock.c
129
pllf = PLLCFG_PLLF(reg);
sys/arch/riscv64/dev/sfclock.c
130
pllq = PLLCFG_PLLQ(reg);
sys/arch/riscv64/dev/sfclock.c
139
uint32_t reg, div;
sys/arch/riscv64/dev/sfclock.c
147
reg = HREAD4(sc, HFPCLKPLLSEL);
sys/arch/riscv64/dev/sfclock.c
148
if (reg & HFPCLKPLLSEL_HFCLK)
sys/arch/riscv64/dev/sfclock.c
53
#define HREAD4(sc, reg) \
sys/arch/riscv64/dev/sfclock.c
54
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/riscv64/dev/sfclock.c
55
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/sfclock.c
56
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/sfgpio.c
182
uint32_t reg;
sys/arch/riscv64/dev/sfgpio.c
188
reg = HREAD4(sc, GPIO_INPUT_VAL);
sys/arch/riscv64/dev/sfgpio.c
189
val = (reg >> pin) & 1;
sys/arch/riscv64/dev/sfgpio.c
53
#define HREAD4(sc, reg) \
sys/arch/riscv64/dev/sfgpio.c
54
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/riscv64/dev/sfgpio.c
55
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/sfgpio.c
56
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/sfgpio.c
57
#define HSET4(sc, reg, bits) \
sys/arch/riscv64/dev/sfgpio.c
58
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/riscv64/dev/sfgpio.c
59
#define HCLR4(sc, reg, bits) \
sys/arch/riscv64/dev/sfgpio.c
60
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/riscv64/dev/sfuart.c
125
struct fdt_reg reg;
sys/arch/riscv64/dev/sfuart.c
130
if (fdt_get_reg(node, 0, ®))
sys/arch/riscv64/dev/sfuart.c
133
sfuartcnattach(fdt_cons_bs_tag, reg.addr);
sys/arch/riscv64/dev/sfuart.c
58
#define HREAD4(sc, reg) \
sys/arch/riscv64/dev/sfuart.c
59
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/riscv64/dev/sfuart.c
60
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/sfuart.c
61
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/sfuart.c
62
#define HSET4(sc, reg, bits) \
sys/arch/riscv64/dev/sfuart.c
63
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/riscv64/dev/sfuart.c
64
#define HCLR4(sc, reg, bits) \
sys/arch/riscv64/dev/sfuart.c
65
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/riscv64/dev/simplebus.c
165
uint32_t *cell, *reg;
sys/arch/riscv64/dev/simplebus.c
194
reg = malloc(len, M_TEMP, M_WAITOK);
sys/arch/riscv64/dev/simplebus.c
195
OF_getpropintarray(node, "reg", reg, len);
sys/arch/riscv64/dev/simplebus.c
201
for (i = 0, cell = reg; i < len / line; i++) {
sys/arch/riscv64/dev/simplebus.c
218
free(reg, M_TEMP, len);
sys/arch/riscv64/dev/smtclock.c
134
#define HREAD4(sc, reg) \
sys/arch/riscv64/dev/smtclock.c
135
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/riscv64/dev/smtclock.c
136
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/smtclock.c
137
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/smtclock.c
138
#define HSET4(sc, reg, bits) \
sys/arch/riscv64/dev/smtclock.c
139
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/riscv64/dev/smtclock.c
140
#define HCLR4(sc, reg, bits) \
sys/arch/riscv64/dev/smtclock.c
141
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/riscv64/dev/smtclock.c
145
uint16_t reg;
sys/arch/riscv64/dev/smtclock.c
151
uint16_t reg;
sys/arch/riscv64/dev/smtclock.c
328
uint32_t reg;
sys/arch/riscv64/dev/smtclock.c
349
reg = HREAD4(sc, clock->reg);
sys/arch/riscv64/dev/smtclock.c
350
switch (APBC_UARTX_CLK_RST_FNCLKSEL(reg)) {
sys/arch/riscv64/dev/smtclock.c
407
HWRITE4(sc, clock->reg, 0);
sys/arch/riscv64/dev/smtclock.c
413
HSET4(sc, clock->reg, (1U << clock->bit));
sys/arch/riscv64/dev/smtclock.c
415
HCLR4(sc, clock->reg, (1U << clock->bit));
sys/arch/riscv64/dev/smtclock.c
463
val = HREAD4(sc, reset->reg) & ~mask;
sys/arch/riscv64/dev/smtclock.c
468
HWRITE4(sc, reset->reg, val);
sys/arch/riscv64/dev/smtcomphy.c
80
#define HREAD4(sc, reg) \
sys/arch/riscv64/dev/smtcomphy.c
81
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/riscv64/dev/smtcomphy.c
82
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/smtcomphy.c
83
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/smtgpio.c
147
uint32_t reg;
sys/arch/riscv64/dev/smtgpio.c
153
reg = HREAD4(sc, offset + GPIO_PLR);
sys/arch/riscv64/dev/smtgpio.c
154
val = (reg >> pin) & 1;
sys/arch/riscv64/dev/smtgpio.c
36
#define HREAD4(sc, reg) \
sys/arch/riscv64/dev/smtgpio.c
37
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/riscv64/dev/smtgpio.c
38
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/smtgpio.c
39
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/smtgpio.c
40
#define HSET4(sc, reg, bits) \
sys/arch/riscv64/dev/smtgpio.c
41
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/riscv64/dev/smtgpio.c
42
#define HCLR4(sc, reg, bits) \
sys/arch/riscv64/dev/smtgpio.c
43
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/riscv64/dev/smtiic.c
299
uint32_t reg[1];
sys/arch/riscv64/dev/smtiic.c
304
memset(reg, 0, sizeof(reg));
sys/arch/riscv64/dev/smtiic.c
314
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/arch/riscv64/dev/smtiic.c
319
ia.ia_addr = bemtoh32(®[0]);
sys/arch/riscv64/dev/smtiic.c
76
#define HREAD4(sc, reg) \
sys/arch/riscv64/dev/smtiic.c
77
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/riscv64/dev/smtiic.c
78
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/smtiic.c
79
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/smtiic.c
80
#define HSET4(sc, reg, bits) \
sys/arch/riscv64/dev/smtiic.c
81
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/riscv64/dev/smtiic.c
82
#define HCLR4(sc, reg, bits) \
sys/arch/riscv64/dev/smtiic.c
83
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/riscv64/dev/smtpmic.c
121
smtpmic_reg_read(struct smtpmic_softc *sc, int reg)
sys/arch/riscv64/dev/smtpmic.c
123
uint8_t cmd = reg;
sys/arch/riscv64/dev/smtpmic.c
134
sc->sc_dev.dv_xname, reg);
sys/arch/riscv64/dev/smtpmic.c
142
smtpmic_reg_write(struct smtpmic_softc *sc, int reg, uint8_t val)
sys/arch/riscv64/dev/smtpmic.c
144
uint8_t cmd = reg;
sys/arch/riscv64/dev/smtpmic.c
154
sc->sc_dev.dv_xname, reg);
sys/arch/riscv64/dev/stfclock.c
1006
reg = HREAD4(sc, idx * 4);
sys/arch/riscv64/dev/stfclock.c
1007
reg &= ~CLKDIV_MASK;
sys/arch/riscv64/dev/stfclock.c
1008
reg |= (2 << CLKDIV_SHIFT);
sys/arch/riscv64/dev/stfclock.c
1009
HWRITE4(sc, idx * 4, reg);
sys/arch/riscv64/dev/stfclock.c
1013
reg = HREAD4(sc, idx * 4);
sys/arch/riscv64/dev/stfclock.c
1014
mux = (reg & CLKMUX_MASK) >> CLKMUX_SHIFT;
sys/arch/riscv64/dev/stfclock.c
1054
reg &= ~CLKDIV_MASK;
sys/arch/riscv64/dev/stfclock.c
1055
reg |= (div << CLKDIV_SHIFT);
sys/arch/riscv64/dev/stfclock.c
1056
HWRITE4(sc, idx * 4, reg);
sys/arch/riscv64/dev/stfclock.c
179
#define HREAD4(sc, reg) \
sys/arch/riscv64/dev/stfclock.c
180
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/riscv64/dev/stfclock.c
181
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/stfclock.c
182
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/stfclock.c
183
#define HSET4(sc, reg, bits) \
sys/arch/riscv64/dev/stfclock.c
184
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/riscv64/dev/stfclock.c
185
#define HCLR4(sc, reg, bits) \
sys/arch/riscv64/dev/stfclock.c
186
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/riscv64/dev/stfclock.c
331
uint32_t reg, div, mux;
sys/arch/riscv64/dev/stfclock.c
350
reg = HREAD4(sc, idx * 4);
sys/arch/riscv64/dev/stfclock.c
351
mux = (reg & CLKMUX_MASK) >> CLKMUX_SHIFT;
sys/arch/riscv64/dev/stfclock.c
352
div = (reg & CLKDIV_MASK) >> CLKDIV_SHIFT;
sys/arch/riscv64/dev/stfclock.c
385
mux = (reg >> 24) & 1;
sys/arch/riscv64/dev/stfclock.c
389
mux = (reg >> 24) & 1;
sys/arch/riscv64/dev/stfclock.c
501
uint32_t reg, div, mux;
sys/arch/riscv64/dev/stfclock.c
514
reg = HREAD4(sc, idx * 4);
sys/arch/riscv64/dev/stfclock.c
515
mux = (reg & CLKMUX_MASK) >> CLKMUX_SHIFT;
sys/arch/riscv64/dev/stfclock.c
516
div = (reg & CLKDIV_MASK) >> CLKDIV_SHIFT;
sys/arch/riscv64/dev/stfclock.c
557
uint32_t reg, div, mux;
sys/arch/riscv64/dev/stfclock.c
566
reg = HREAD4(sc, idx * 4);
sys/arch/riscv64/dev/stfclock.c
567
mux = (reg & CLKMUX_MASK) >> CLKMUX_SHIFT;
sys/arch/riscv64/dev/stfclock.c
594
reg &= ~CLKDIV_MASK;
sys/arch/riscv64/dev/stfclock.c
595
reg |= (div << CLKDIV_SHIFT);
sys/arch/riscv64/dev/stfclock.c
596
HWRITE4(sc, idx * 4, reg);
sys/arch/riscv64/dev/stfclock.c
648
uint32_t dacpd, dsmpd, fbdiv, frac, prediv, postdiv, reg;
sys/arch/riscv64/dev/stfclock.c
675
reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_PD_OFF);
sys/arch/riscv64/dev/stfclock.c
676
dacpd = (reg & PLL0DACPD_MASK) >> PLL0DACPD_SHIFT;
sys/arch/riscv64/dev/stfclock.c
677
dsmpd = (reg & PLL0DSMPD_MASK) >> PLL0DSMPD_SHIFT;
sys/arch/riscv64/dev/stfclock.c
679
reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_FBDIV_OFF);
sys/arch/riscv64/dev/stfclock.c
680
fbdiv = (reg & PLL0FBDIV_MASK) >> PLL0FBDIV_SHIFT;
sys/arch/riscv64/dev/stfclock.c
682
reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_FRAC_OFF);
sys/arch/riscv64/dev/stfclock.c
683
frac = (reg & PLLFRAC_MASK) >> PLLFRAC_SHIFT;
sys/arch/riscv64/dev/stfclock.c
684
postdiv = 1 << ((reg & PLLPOSTDIV1_MASK) >> PLLPOSTDIV1_SHIFT);
sys/arch/riscv64/dev/stfclock.c
686
reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_PREDIV_OFF);
sys/arch/riscv64/dev/stfclock.c
687
prediv = (reg & PLLPREDIV_MASK) >> PLLPREDIV_SHIFT;
sys/arch/riscv64/dev/stfclock.c
692
reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL_PD_OFF);
sys/arch/riscv64/dev/stfclock.c
693
dacpd = (reg & PLLDACPD_MASK) >> PLLDACPD_SHIFT;
sys/arch/riscv64/dev/stfclock.c
694
dsmpd = (reg & PLLDSMPD_MASK) >> PLLDSMPD_SHIFT;
sys/arch/riscv64/dev/stfclock.c
695
fbdiv = (reg & PLLFBDIV_MASK) >> PLLFBDIV_SHIFT;
sys/arch/riscv64/dev/stfclock.c
697
reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL_FRAC_OFF);
sys/arch/riscv64/dev/stfclock.c
698
frac = (reg & PLLFRAC_MASK) >> PLLFRAC_SHIFT;
sys/arch/riscv64/dev/stfclock.c
699
postdiv = 1 << ((reg & PLLPOSTDIV1_MASK) >> PLLPOSTDIV1_SHIFT);
sys/arch/riscv64/dev/stfclock.c
701
reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL_PREDIV_OFF);
sys/arch/riscv64/dev/stfclock.c
702
prediv = (reg & PLLPREDIV_MASK) >> PLLPREDIV_SHIFT;
sys/arch/riscv64/dev/stfclock.c
727
uint32_t dacpd, dsmpd, fbdiv, prediv, postdiv1, reg;
sys/arch/riscv64/dev/stfclock.c
761
reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_PD_OFF);
sys/arch/riscv64/dev/stfclock.c
762
reg &= ~(PLL0DACPD_MASK | PLL0DSMPD_MASK);
sys/arch/riscv64/dev/stfclock.c
763
reg |= dacpd << PLL0DACPD_SHIFT;
sys/arch/riscv64/dev/stfclock.c
764
reg |= dsmpd << PLL0DSMPD_SHIFT;
sys/arch/riscv64/dev/stfclock.c
765
regmap_write_4(sc->sc_rm, base + JH7110_PLL0_PD_OFF, reg);
sys/arch/riscv64/dev/stfclock.c
767
reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_PREDIV_OFF);
sys/arch/riscv64/dev/stfclock.c
768
reg &= ~PLLPREDIV_MASK;
sys/arch/riscv64/dev/stfclock.c
769
reg |= (prediv << PLLPREDIV_SHIFT);
sys/arch/riscv64/dev/stfclock.c
770
regmap_write_4(sc->sc_rm, base + JH7110_PLL0_PREDIV_OFF, reg);
sys/arch/riscv64/dev/stfclock.c
772
reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_FBDIV_OFF);
sys/arch/riscv64/dev/stfclock.c
773
reg &= ~PLL0FBDIV_MASK;
sys/arch/riscv64/dev/stfclock.c
774
reg |= fbdiv << PLL0FBDIV_SHIFT;
sys/arch/riscv64/dev/stfclock.c
775
regmap_write_4(sc->sc_rm, base + JH7110_PLL0_FBDIV_OFF, reg);
sys/arch/riscv64/dev/stfclock.c
777
reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_FRAC_OFF);
sys/arch/riscv64/dev/stfclock.c
778
reg &= ~PLLPOSTDIV1_MASK;
sys/arch/riscv64/dev/stfclock.c
779
reg |= postdiv1 << PLLPOSTDIV1_SHIFT;
sys/arch/riscv64/dev/stfclock.c
780
regmap_write_4(sc->sc_rm, base + JH7110_PLL0_FRAC_OFF, reg);
sys/arch/riscv64/dev/stfclock.c
864
uint32_t reg, div, mux;
sys/arch/riscv64/dev/stfclock.c
879
reg = HREAD4(sc, idx * 4);
sys/arch/riscv64/dev/stfclock.c
880
mux = (reg & CLKMUX_MASK) >> CLKMUX_SHIFT;
sys/arch/riscv64/dev/stfclock.c
881
div = (reg & CLKDIV_MASK) >> CLKDIV_SHIFT;
sys/arch/riscv64/dev/stfclock.c
885
mux = (reg >> 24) & 1;
sys/arch/riscv64/dev/stfclock.c
889
mux = (reg >> 24) & 1;
sys/arch/riscv64/dev/stfclock.c
985
uint32_t reg, div, mux;
sys/arch/riscv64/dev/stfpcie.c
100
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/riscv64/dev/stfpcie.c
101
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/stfpcie.c
102
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/stfpcie.c
239
uint32_t reg, stg;
sys/arch/riscv64/dev/stfpcie.c
301
reg = regmap_read_4(rm, stg_base + STG_RP_NEP);
sys/arch/riscv64/dev/stfpcie.c
302
reg |= STG_K_RP_NEP;
sys/arch/riscv64/dev/stfpcie.c
303
regmap_write_4(rm, stg_base + STG_RP_NEP, reg);
sys/arch/riscv64/dev/stfpcie.c
305
reg = regmap_read_4(rm, stg_base + STG_AWFUN);
sys/arch/riscv64/dev/stfpcie.c
306
reg &= ~STG_AWFUN_CKREF_SRC_MASK;
sys/arch/riscv64/dev/stfpcie.c
307
reg |= (2 << STG_AWFUN_CKREF_SRC_SHIFT);
sys/arch/riscv64/dev/stfpcie.c
308
regmap_write_4(rm, stg_base + STG_AWFUN, reg);
sys/arch/riscv64/dev/stfpcie.c
310
reg = regmap_read_4(rm, stg_base + STG_AWFUN);
sys/arch/riscv64/dev/stfpcie.c
311
reg |= STG_AWFUN_CLKREQ;
sys/arch/riscv64/dev/stfpcie.c
312
regmap_write_4(rm, stg_base + STG_AWFUN, reg);
sys/arch/riscv64/dev/stfpcie.c
395
reg = regmap_read_4(rm, stg_base + STG_ARFUN);
sys/arch/riscv64/dev/stfpcie.c
396
reg &= ~STG_ARFUN_AXI4_SLVL_MASK;
sys/arch/riscv64/dev/stfpcie.c
397
reg |= (i << STG_PHY_FUNC_SHIFT) << STG_ARFUN_AXI4_SLVL_SHIFT;
sys/arch/riscv64/dev/stfpcie.c
398
regmap_write_4(rm, stg_base + STG_ARFUN, reg);
sys/arch/riscv64/dev/stfpcie.c
399
reg = regmap_read_4(rm, stg_base + STG_AWFUN);
sys/arch/riscv64/dev/stfpcie.c
400
reg &= ~STG_AWFUN_AXI4_SLVL_MASK;
sys/arch/riscv64/dev/stfpcie.c
401
reg |= (i << STG_PHY_FUNC_SHIFT) << STG_AWFUN_AXI4_SLVL_SHIFT;
sys/arch/riscv64/dev/stfpcie.c
402
regmap_write_4(rm, stg_base + STG_AWFUN, reg);
sys/arch/riscv64/dev/stfpcie.c
404
reg = HREAD4(sc, PCIE_PCI_IOV_DW0);
sys/arch/riscv64/dev/stfpcie.c
405
reg |= PHY_FUNCTION_DIS;
sys/arch/riscv64/dev/stfpcie.c
406
HWRITE4(sc, PCIE_PCI_IOV_DW0, reg);
sys/arch/riscv64/dev/stfpcie.c
408
reg = regmap_read_4(rm, stg_base + STG_ARFUN);
sys/arch/riscv64/dev/stfpcie.c
409
reg &= ~STG_ARFUN_AXI4_SLVL_MASK;
sys/arch/riscv64/dev/stfpcie.c
410
regmap_write_4(rm, stg_base + STG_ARFUN, reg);
sys/arch/riscv64/dev/stfpcie.c
411
reg = regmap_read_4(rm, stg_base + STG_AWFUN);
sys/arch/riscv64/dev/stfpcie.c
412
reg &= ~STG_AWFUN_AXI4_SLVL_MASK;
sys/arch/riscv64/dev/stfpcie.c
413
regmap_write_4(rm, stg_base + STG_AWFUN, reg);
sys/arch/riscv64/dev/stfpcie.c
416
reg = HREAD4(sc, GEN_SETTINGS);
sys/arch/riscv64/dev/stfpcie.c
417
reg |= PORT_TYPE_RP;
sys/arch/riscv64/dev/stfpcie.c
418
HWRITE4(sc, GEN_SETTINGS, reg);
sys/arch/riscv64/dev/stfpcie.c
426
reg = HREAD4(sc, PCIE_BAR_WIN);
sys/arch/riscv64/dev/stfpcie.c
427
reg |= PFETCH_MEMWIN_64BADDR;
sys/arch/riscv64/dev/stfpcie.c
428
HWRITE4(sc, PCIE_BAR_WIN, reg);
sys/arch/riscv64/dev/stfpcie.c
431
reg = HREAD4(sc, PMSG_SUPPORT_RX);
sys/arch/riscv64/dev/stfpcie.c
432
reg &= ~PMSG_LTR_SUPPORT;
sys/arch/riscv64/dev/stfpcie.c
433
HWRITE4(sc, PMSG_SUPPORT_RX, reg);
sys/arch/riscv64/dev/stfpcie.c
472
reg = regmap_read_4(rm, stg_base + STG_LNKSTA);
sys/arch/riscv64/dev/stfpcie.c
473
if (reg & STG_DATA_LINK_ACTIVE)
sys/arch/riscv64/dev/stfpcie.c
790
uint32_t reg[5];
sys/arch/riscv64/dev/stfpcie.c
798
reg, sizeof(reg)) != sizeof(reg))
sys/arch/riscv64/dev/stfpcie.c
801
if (reg[0] == phys_hi)
sys/arch/riscv64/dev/stfpcie.c
841
stfpcie_conf_read(void *v, pcitag_t tag, int reg)
sys/arch/riscv64/dev/stfpcie.c
846
return bus_space_read_4(sc->sc_iot, sc->sc_cfg_ioh, tag | reg);
sys/arch/riscv64/dev/stfpcie.c
850
stfpcie_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
sys/arch/riscv64/dev/stfpcie.c
855
bus_space_write_4(sc->sc_iot, sc->sc_cfg_ioh, tag | reg, data);
sys/arch/riscv64/dev/stfpcie.c
934
uint32_t reg[4];
sys/arch/riscv64/dev/stfpcie.c
938
reg[0] = bus << 16 | dev << 11 | fn << 8;
sys/arch/riscv64/dev/stfpcie.c
939
reg[1] = reg[2] = 0;
sys/arch/riscv64/dev/stfpcie.c
940
reg[3] = ih.ih_intrpin;
sys/arch/riscv64/dev/stfpcie.c
942
cookie = fdt_intr_establish_imap_cpu(sc->sc_node, reg,
sys/arch/riscv64/dev/stfpcie.c
943
sizeof(reg), level, ci, func, arg, name);
sys/arch/riscv64/dev/stfpcie.c
99
#define HREAD4(sc, reg) \
sys/arch/riscv64/dev/stfpciephy.c
34
#define HREAD4(sc, reg) \
sys/arch/riscv64/dev/stfpciephy.c
35
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/riscv64/dev/stfpciephy.c
36
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/stfpciephy.c
37
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/stfpciephy.c
38
#define HSET4(sc, reg, bits) \
sys/arch/riscv64/dev/stfpciephy.c
39
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/arch/riscv64/dev/stfpciephy.c
40
#define HCLR4(sc, reg, bits) \
sys/arch/riscv64/dev/stfpciephy.c
41
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/arch/riscv64/dev/stfpinctrl.c
188
uint32_t reg;
sys/arch/riscv64/dev/stfpinctrl.c
197
reg = bus_space_read_4(sc->sc_iot, sc->sc_padctl_ioh,
sys/arch/riscv64/dev/stfpinctrl.c
199
reg |= (PAD_INPUT_ENABLE << PAD_SHIFT(pin));
sys/arch/riscv64/dev/stfpinctrl.c
200
reg |= (PAD_INPUT_SCHMITT_ENABLE << PAD_SHIFT(pin));
sys/arch/riscv64/dev/stfpinctrl.c
202
sc->sc_padctl_gpio + PAD_GPIO(pin), reg);
sys/arch/riscv64/dev/stfpinctrl.c
214
uint32_t reg;
sys/arch/riscv64/dev/stfpinctrl.c
220
reg = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, GPIODIN(pin));
sys/arch/riscv64/dev/stfpinctrl.c
221
val = (reg >> (pin % 32)) & 1;
sys/arch/riscv64/dev/stfpinctrl.c
285
uint32_t reg;
sys/arch/riscv64/dev/stfpinctrl.c
291
reg = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh,
sys/arch/riscv64/dev/stfpinctrl.c
293
val = (reg >> (pin % 32)) & 1;
sys/arch/riscv64/dev/stfpinctrl.c
305
uint32_t reg;
sys/arch/riscv64/dev/stfpinctrl.c
313
reg = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, JH7110_DOUT(pin));
sys/arch/riscv64/dev/stfpinctrl.c
314
reg &= ~(JH7110_DOUT_MASK << JH7110_DOUT_SHIFT(pin));
sys/arch/riscv64/dev/stfpinctrl.c
315
reg |= (val << JH7110_DOUT_SHIFT(pin));
sys/arch/riscv64/dev/stfpinctrl.c
316
bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, JH7110_DOUT(pin), reg);
sys/arch/riscv64/dev/stfrng.c
50
#define HREAD4(sc, reg) \
sys/arch/riscv64/dev/stfrng.c
51
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/riscv64/dev/stfrng.c
52
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/stfrng.c
53
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/stftemp.c
39
#define HREAD4(sc, reg) \
sys/arch/riscv64/dev/stftemp.c
40
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/riscv64/dev/stftemp.c
41
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/stftemp.c
42
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/dev/sxitimer.c
46
#define HREAD4(sc, reg) \
sys/arch/riscv64/dev/sxitimer.c
47
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/arch/riscv64/dev/sxitimer.c
48
#define HWRITE4(sc, reg, val) \
sys/arch/riscv64/dev/sxitimer.c
49
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/arch/riscv64/include/asm.h
80
#define RETGUARD_CALC_COOKIE(reg)
sys/arch/riscv64/include/asm.h
81
#define RETGUARD_LOAD_RANDOM(x, reg)
sys/arch/riscv64/include/asm.h
82
#define RETGUARD_SETUP(x, reg)
sys/arch/riscv64/include/asm.h
83
#define RETGUARD_CHECK(x, reg)
sys/arch/riscv64/include/asm.h
84
#define RETGUARD_PUSH(reg)
sys/arch/riscv64/include/asm.h
85
#define RETGUARD_POP(reg)
sys/arch/riscv64/riscv64/intr.c
410
riscv_intr_establish_fdt_imap_cpu(int node, int *reg, int nreg, int level,
sys/arch/riscv64/riscv64/intr.c
447
(reg[0] & map_mask[0]) == cell[0] &&
sys/arch/riscv64/riscv64/intr.c
448
(reg[1] & map_mask[1]) == cell[1] &&
sys/arch/riscv64/riscv64/intr.c
449
(reg[2] & map_mask[2]) == cell[2] &&
sys/arch/riscv64/riscv64/intr.c
450
(reg[3] & map_mask[3]) == cell[3] &&
sys/arch/riscv64/riscv64/machdep.c
555
struct fdt_reg reg;
sys/arch/riscv64/riscv64/machdep.c
770
reg.addr = desc->PhysicalStart;
sys/arch/riscv64/riscv64/machdep.c
771
reg.size = ptoa(desc->NumberOfPages);
sys/arch/riscv64/riscv64/machdep.c
772
memreg_add(®);
sys/arch/riscv64/riscv64/machdep.c
782
if (fdt_get_reg(node, i, ®))
sys/arch/riscv64/riscv64/machdep.c
784
if (reg.size == 0)
sys/arch/riscv64/riscv64/machdep.c
786
memreg_add(®);
sys/arch/riscv64/riscv64/machdep.c
795
if (fdt_get_reg(node, 0, ®))
sys/arch/riscv64/riscv64/machdep.c
797
if (reg.size == 0)
sys/arch/riscv64/riscv64/machdep.c
799
memreg_remove(®);
sys/arch/riscv64/riscv64/machdep.c
804
reg.addr = memstart;
sys/arch/riscv64/riscv64/machdep.c
805
reg.size = memend - memstart;
sys/arch/riscv64/riscv64/machdep.c
806
memreg_remove(®);
sys/arch/riscv64/riscv64/machdep.c
829
if (fdt_get_reg(node, i, ®))
sys/arch/riscv64/riscv64/machdep.c
831
if (reg.size == 0)
sys/arch/riscv64/riscv64/machdep.c
833
physmem += atop(reg.size);
sys/arch/riscv64/riscv64/machdep.c
952
memreg_add(const struct fdt_reg *reg)
sys/arch/riscv64/riscv64/machdep.c
957
if (reg->addr == memreg[i].addr + memreg[i].size) {
sys/arch/riscv64/riscv64/machdep.c
958
memreg[i].size += reg->size;
sys/arch/riscv64/riscv64/machdep.c
961
if (reg->addr + reg->size == memreg[i].addr) {
sys/arch/riscv64/riscv64/machdep.c
962
memreg[i].addr = reg->addr;
sys/arch/riscv64/riscv64/machdep.c
963
memreg[i].size += reg->size;
sys/arch/riscv64/riscv64/machdep.c
971
memreg[nmemreg++] = *reg;
sys/arch/riscv64/riscv64/machdep.c
975
memreg_remove(const struct fdt_reg *reg)
sys/arch/riscv64/riscv64/machdep.c
977
uint64_t start = reg->addr;
sys/arch/riscv64/riscv64/machdep.c
978
uint64_t end = reg->addr + reg->size;
sys/arch/riscv64/riscv64/process_machdep.c
53
process_read_regs(struct proc *p, struct reg *regs)
sys/arch/riscv64/riscv64/process_machdep.c
89
process_write_regs(struct proc *p, struct reg *regs)
sys/arch/riscv64/stand/efiboot/efiboot.c
362
uint32_t reg[4];
sys/arch/riscv64/stand/efiboot/efiboot.c
435
reg[0] = htobe32(base);
sys/arch/riscv64/stand/efiboot/efiboot.c
437
reg[1] = reg[0];
sys/arch/riscv64/stand/efiboot/efiboot.c
438
reg[0] = htobe32(base >> 32);
sys/arch/riscv64/stand/efiboot/efiboot.c
441
reg[acells] = htobe32(size);
sys/arch/riscv64/stand/efiboot/efiboot.c
443
reg[acells + 1] = reg[acells];
sys/arch/riscv64/stand/efiboot/efiboot.c
444
reg[acells] = htobe32(size >> 32);
sys/arch/riscv64/stand/efiboot/efiboot.c
454
fdt_node_add_property(child, "reg", reg, (acells + scells) * 4);
sys/arch/sh/dev/shpcic.c
321
shpcic_conf_read(void *v, pcitag_t tag, int reg)
sys/arch/sh/dev/shpcic.c
327
_reg_write_4(SH4_PCIPAR, tag | reg);
sys/arch/sh/dev/shpcic.c
336
shpcic_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
sys/arch/sh/dev/shpcic.c
341
_reg_write_4(SH4_PCIPAR, tag | reg);
sys/arch/sh/dev/shpcicvar.h
43
pcireg_t shpcic_conf_read(void *v, pcitag_t tag, int reg);
sys/arch/sh/dev/shpcicvar.h
44
void shpcic_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data);
sys/arch/sh/sh/process_machdep.c
143
process_read_regs(struct proc *p, struct reg *regs)
sys/arch/sh/sh/process_machdep.c
195
process_write_regs(struct proc *p, struct reg *regs)
sys/arch/sparc64/dev/beep.c
136
sc->sc_freqs[i].reg = 1 << (18 - i);
sys/arch/sparc64/dev/beep.c
137
sc->sc_freqs[i].freq = sc->sc_clk / sc->sc_freqs[i].reg;
sys/arch/sparc64/dev/beep.c
191
(sc->sc_freqs[selected].reg >> 24) & 0xff);
sys/arch/sparc64/dev/beep.c
193
(sc->sc_freqs[selected].reg >> 16) & 0xff);
sys/arch/sparc64/dev/beep.c
195
(sc->sc_freqs[selected].reg >> 8) & 0xff);
sys/arch/sparc64/dev/beep.c
197
(sc->sc_freqs[selected].reg >> 0) & 0xff);
sys/arch/sparc64/dev/beep.c
63
u_int32_t reg;
sys/arch/sparc64/dev/cbus.c
79
int reg;
sys/arch/sparc64/dev/cbus.c
84
if (OF_getprop(va->va_node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/arch/sparc64/dev/cbus.c
86
sc->sc_devhandle = reg;
sys/arch/sparc64/dev/ce4231.c
1073
u_int8_t reg;
sys/arch/sparc64/dev/ce4231.c
1081
reg = ce4231_read(sc, CS_IRQ_STATUS);
sys/arch/sparc64/dev/ce4231.c
1082
if (reg & CS_IRQ_PI) {
sys/arch/sparc64/dev/ce4231.c
1085
ce4231_write(sc, CS_IRQ_STATUS, reg & ~CS_IRQ_PI);
sys/arch/sparc64/dev/ce4231.c
1125
u_int8_t reg;
sys/arch/sparc64/dev/ce4231.c
1133
reg = ce4231_read(sc, CS_IRQ_STATUS);
sys/arch/sparc64/dev/ce4231.c
1134
if (reg & CS_IRQ_CI) {
sys/arch/sparc64/dev/ce4231.c
1137
ce4231_write(sc, CS_IRQ_STATUS, reg & ~CS_IRQ_CI);
sys/arch/sparc64/dev/ebus_mainbus.c
247
struct upa_reg reg;
sys/arch/sparc64/dev/ebus_mainbus.c
262
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/arch/sparc64/dev/ebus_mainbus.c
264
devhandle = (reg.ur_paddr >> 32) & 0x0fffffff;
sys/arch/sparc64/dev/ebusreg.h
69
#define EBUS_PADDR_FROM_REG(reg) ((((paddr_t)((reg)->hi)) << 32UL) | ((paddr_t)(reg)->lo))
sys/arch/sparc64/dev/ifb.c
1120
ifb_rop_common(struct ifb_softc *sc, bus_addr_t reg, int sx, int sy,
sys/arch/sparc64/dev/ifb.c
1141
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x61000001);
sys/arch/sparc64/dev/ifb.c
1142
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0);
sys/arch/sparc64/dev/ifb.c
1143
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x6301c080);
sys/arch/sparc64/dev/ifb.c
1144
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x80000000);
sys/arch/sparc64/dev/ifb.c
1145
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, rop);
sys/arch/sparc64/dev/ifb.c
1146
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, planemask);
sys/arch/sparc64/dev/ifb.c
1147
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0);
sys/arch/sparc64/dev/ifb.c
1148
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x64000303);
sys/arch/sparc64/dev/ifb.c
1154
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, IFB_COORDS(0, 0));
sys/arch/sparc64/dev/ifb.c
1155
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0);
sys/arch/sparc64/dev/ifb.c
1156
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x00030000);
sys/arch/sparc64/dev/ifb.c
1157
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x2200010d);
sys/arch/sparc64/dev/ifb.c
1159
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x33f01000 | dir);
sys/arch/sparc64/dev/ifb.c
1160
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, IFB_COORDS(dx, dy));
sys/arch/sparc64/dev/ifb.c
1161
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, IFB_COORDS(w, h));
sys/arch/sparc64/dev/ifb.c
1162
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, IFB_COORDS(sx, sy));
sys/arch/sparc64/dev/ifb.c
1170
bus_addr_t reg = IFB_REG_ENGINE;
sys/arch/sparc64/dev/ifb.c
1172
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 2);
sys/arch/sparc64/dev/ifb.c
1173
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 1);
sys/arch/sparc64/dev/ifb.c
1175
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x540101ff);
sys/arch/sparc64/dev/ifb.c
1177
ifb_rop_common(sc, reg, sx, sy, dx, dy, w, h, rop, planemask);
sys/arch/sparc64/dev/ifb.c
1185
bus_addr_t reg = JFB_REG_ENGINE;
sys/arch/sparc64/dev/ifb.c
1201
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x00400016);
sys/arch/sparc64/dev/ifb.c
1202
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x5b000002);
sys/arch/sparc64/dev/ifb.c
1203
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x5a000000);
sys/arch/sparc64/dev/ifb.c
1204
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, spr);
sys/arch/sparc64/dev/ifb.c
1205
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, splr);
sys/arch/sparc64/dev/ifb.c
1207
ifb_rop_common(sc, reg, sx, sy, dx, dy, w, h, rop, planemask);
sys/arch/sparc64/dev/ifb.c
1209
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x5a000001);
sys/arch/sparc64/dev/ifb.c
1210
bus_space_write_4(sc->sc_mem_t, sc->sc_reg_h, reg, 0x5b000001);
sys/arch/sparc64/dev/iommuvar.h
165
#define IOMMUREG_READ(is, reg) \
sys/arch/sparc64/dev/iommuvar.h
168
IOMMUREG(reg))
sys/arch/sparc64/dev/iommuvar.h
170
#define IOMMUREG_WRITE(is, reg, v) \
sys/arch/sparc64/dev/iommuvar.h
173
IOMMUREG(reg), \
sys/arch/sparc64/dev/led.c
153
u_int8_t reg;
sys/arch/sparc64/dev/led.c
156
reg = EPIC_ALERT_LED_ON;
sys/arch/sparc64/dev/led.c
158
reg = EPIC_ALERT_LED_OFF;
sys/arch/sparc64/dev/led.c
160
bus_space_write_1(sc->sc_iot, sc->sc_ioh, EPIC_DATA, reg);
sys/arch/sparc64/dev/lom.c
238
uint8_t reg, fw_rev, config, config2, config3;
sys/arch/sparc64/dev/lom.c
269
if (lom_read(sc, LOM_IDX_PROBE55, ®) || reg != 0x55 ||
sys/arch/sparc64/dev/lom.c
270
lom_read(sc, LOM_IDX_PROBEAA, ®) || reg != 0xaa ||
sys/arch/sparc64/dev/lom.c
380
lom_read(struct lom_softc *sc, uint8_t reg, uint8_t *val)
sys/arch/sparc64/dev/lom.c
383
return lom1_read(sc, reg, val);
sys/arch/sparc64/dev/lom.c
385
return lom2_read(sc, reg, val);
sys/arch/sparc64/dev/lom.c
389
lom_write(struct lom_softc *sc, uint8_t reg, uint8_t val)
sys/arch/sparc64/dev/lom.c
392
return lom1_write(sc, reg, val);
sys/arch/sparc64/dev/lom.c
394
return lom2_write(sc, reg, val);
sys/arch/sparc64/dev/lom.c
422
lom1_read(struct lom_softc *sc, uint8_t reg, uint8_t *val)
sys/arch/sparc64/dev/lom.c
428
return lom1_read_polled(sc, reg, val);
sys/arch/sparc64/dev/lom.c
430
lc.lc_cmd = reg;
sys/arch/sparc64/dev/lom.c
444
lom1_write(struct lom_softc *sc, uint8_t reg, uint8_t val)
sys/arch/sparc64/dev/lom.c
450
return lom1_write_polled(sc, reg, val);
sys/arch/sparc64/dev/lom.c
452
lc.lc_cmd = reg | LOM_IDX_WRITE;
sys/arch/sparc64/dev/lom.c
464
lom1_read_polled(struct lom_softc *sc, uint8_t reg, uint8_t *val)
sys/arch/sparc64/dev/lom.c
479
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LOM1_CMD, reg);
sys/arch/sparc64/dev/lom.c
496
lom1_write_polled(struct lom_softc *sc, uint8_t reg, uint8_t val)
sys/arch/sparc64/dev/lom.c
511
reg |= LOM_IDX_WRITE;
sys/arch/sparc64/dev/lom.c
512
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LOM1_CMD, reg);
sys/arch/sparc64/dev/lom.c
610
lom2_read(struct lom_softc *sc, uint8_t reg, uint8_t *val)
sys/arch/sparc64/dev/lom.c
616
return lom2_read_polled(sc, reg, val);
sys/arch/sparc64/dev/lom.c
618
lc.lc_cmd = reg;
sys/arch/sparc64/dev/lom.c
632
lom2_read_polled(struct lom_softc *sc, uint8_t reg, uint8_t *val)
sys/arch/sparc64/dev/lom.c
647
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LOM2_CMD, reg);
sys/arch/sparc64/dev/lom.c
664
lom2_write(struct lom_softc *sc, uint8_t reg, uint8_t val)
sys/arch/sparc64/dev/lom.c
670
return lom2_write_polled(sc, reg, val);
sys/arch/sparc64/dev/lom.c
672
lc.lc_cmd = reg | LOM_IDX_WRITE;
sys/arch/sparc64/dev/lom.c
684
lom2_write_polled(struct lom_softc *sc, uint8_t reg, uint8_t val)
sys/arch/sparc64/dev/lom.c
699
if (sc->sc_space == LOM_IDX_CMD_GENERIC && reg != LOM_IDX_CMD)
sys/arch/sparc64/dev/lom.c
700
reg |= LOM_IDX_WRITE;
sys/arch/sparc64/dev/lom.c
702
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LOM2_CMD, reg);
sys/arch/sparc64/dev/lom.c
741
if (reg == LOM_IDX_CMD)
sys/arch/sparc64/dev/machfb.c
595
uint32_t reg;
sys/arch/sparc64/dev/machfb.c
598
reg = bus_space_read_4(sc->sc_regt, sc->sc_regh, M64_GEN_TEST_CNTL);
sys/arch/sparc64/dev/machfb.c
599
reg &= ~M64_GEN_GUI_EN;
sys/arch/sparc64/dev/machfb.c
600
bus_space_write_4(sc->sc_regt, sc->sc_regh, M64_GEN_TEST_CNTL, reg);
sys/arch/sparc64/dev/machfb.c
603
reg = bus_space_read_4(sc->sc_regt, sc->sc_regh, M64_GEN_TEST_CNTL);
sys/arch/sparc64/dev/machfb.c
604
reg &= M64_GEN_GUI_EN;
sys/arch/sparc64/dev/machfb.c
605
bus_space_write_4(sc->sc_regt, sc->sc_regh, M64_GEN_TEST_CNTL, reg);
sys/arch/sparc64/dev/machfb.c
608
reg = bus_space_read_4(sc->sc_regt, sc->sc_regh, M64_BUS_CNTL);
sys/arch/sparc64/dev/machfb.c
609
reg |= M64_BUS_HOST_ERR_ACK | M64_BUS_FIFO_ERR_ACK;
sys/arch/sparc64/dev/machfb.c
610
bus_space_write_4(sc->sc_regt, sc->sc_regh, M64_BUS_CNTL, reg);
sys/arch/sparc64/dev/ofwi2c.c
62
u_int32_t reg[2];
sys/arch/sparc64/dev/ofwi2c.c
67
memset(reg, 0, sizeof(reg));
sys/arch/sparc64/dev/ofwi2c.c
74
if (OF_getprop(node, "reg", reg, sizeof(reg)) == -1)
sys/arch/sparc64/dev/ofwi2c.c
79
ia.ia_addr = (reg[0] << 7) | (reg[1] >> 1);
sys/arch/sparc64/dev/pci_machdep.c
135
struct ofw_pci_register reg;
sys/arch/sparc64/dev/pci_machdep.c
198
if (len < sizeof(reg))
sys/arch/sparc64/dev/pci_machdep.c
200
if (OF_getprop(node, "reg", (void *)®, sizeof(reg)) != len)
sys/arch/sparc64/dev/pci_machdep.c
203
if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi))
sys/arch/sparc64/dev/pci_machdep.c
205
if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi))
sys/arch/sparc64/dev/pci_machdep.c
207
if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi))
sys/arch/sparc64/dev/pci_machdep.c
256
struct ofw_pci_register reg;
sys/arch/sparc64/dev/pci_machdep.c
288
if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg))
sys/arch/sparc64/dev/pci_machdep.c
291
b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi);
sys/arch/sparc64/dev/pci_machdep.c
292
d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi);
sys/arch/sparc64/dev/pci_machdep.c
293
f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi);
sys/arch/sparc64/dev/pci_machdep.c
356
pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
sys/arch/sparc64/dev/pci_machdep.c
361
val = pc->conf_read(pc, tag, reg);
sys/arch/sparc64/dev/pci_machdep.c
367
pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
sys/arch/sparc64/dev/pci_machdep.c
370
pc->conf_write(pc, tag, reg, data);
sys/arch/sparc64/dev/pci_machdep.c
453
pcireg_t reg;
sys/arch/sparc64/dev/pci_machdep.c
459
pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0)
sys/arch/sparc64/dev/pci_machdep.c
462
if (vec > PCI_MSIX_MC_TBLSZ(reg))
sys/arch/sparc64/dev/pci_machdep.c
543
pcireg_t reg;
sys/arch/sparc64/dev/pci_machdep.c
546
if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0)
sys/arch/sparc64/dev/pci_machdep.c
549
if (reg & PCI_MSI_MC_C64) {
sys/arch/sparc64/dev/pci_machdep.c
557
pci_conf_write(pc, tag, off, reg | PCI_MSI_MC_MSIE);
sys/arch/sparc64/dev/pci_machdep.c
566
pcireg_t reg, table, type;
sys/arch/sparc64/dev/pci_machdep.c
571
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
sys/arch/sparc64/dev/pci_machdep.c
577
tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
sys/arch/sparc64/dev/pci_machdep.c
596
pci_conf_write(pc, tag, off, reg | PCI_MSIX_MC_MSIXE);
sys/arch/sparc64/dev/pci_machdep.c
604
pcireg_t reg, table, type;
sys/arch/sparc64/dev/pci_machdep.c
608
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
sys/arch/sparc64/dev/pci_machdep.c
614
tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
sys/arch/sparc64/dev/pci_machdep.c
629
pcireg_t reg;
sys/arch/sparc64/dev/pci_machdep.c
632
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0)
sys/arch/sparc64/dev/pci_machdep.c
635
tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
sys/arch/sparc64/dev/ppm.c
129
reg = bus_space_read_1(sc->sc_iot, sc->sc_gpiobankh, BBC_GPIOBANK_DATA);
sys/arch/sparc64/dev/ppm.c
130
reg &= 0x7f;
sys/arch/sparc64/dev/ppm.c
131
bus_space_write_1(sc->sc_iot, sc->sc_gpiobankh,BBC_GPIOBANK_INDEX, reg);
sys/arch/sparc64/dev/ppm.c
86
u_int8_t reg;
sys/arch/sparc64/dev/psycho.c
1119
psycho_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
sys/arch/sparc64/dev/psycho.c
1129
PCITAG_OFFSET(tag) + reg);
sys/arch/sparc64/dev/psycho.c
1140
psycho_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
sys/arch/sparc64/dev/psycho.c
1143
PCITAG_OFFSET(tag) + reg, data);
sys/arch/sparc64/dev/psychovar.h
134
#define psycho_psychoreg_read(sc, reg) \
sys/arch/sparc64/dev/psychovar.h
136
offsetof(struct psychoreg, reg))
sys/arch/sparc64/dev/psychovar.h
138
#define psycho_psychoreg_write(sc, reg, v) \
sys/arch/sparc64/dev/psychovar.h
140
offsetof(struct psychoreg, reg), (v))
sys/arch/sparc64/dev/psychovar.h
142
#define psycho_psychoreg_vaddr(sc, reg) \
sys/arch/sparc64/dev/psychovar.h
144
offsetof(struct psychoreg, reg))
sys/arch/sparc64/dev/psychovar.h
146
#define psycho_pcictl_read(sc, reg) \
sys/arch/sparc64/dev/psychovar.h
148
offsetof(struct pci_ctl, reg))
sys/arch/sparc64/dev/psychovar.h
150
#define psycho_pcictl_write(sc, reg, v) \
sys/arch/sparc64/dev/psychovar.h
152
offsetof(struct pci_ctl, reg), (v))
sys/arch/sparc64/dev/pyro.c
449
pyro_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
sys/arch/sparc64/dev/pyro.c
459
(PCITAG_OFFSET(tag) << 4) + reg);
sys/arch/sparc64/dev/pyro.c
470
pyro_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
sys/arch/sparc64/dev/pyro.c
473
(PCITAG_OFFSET(tag) << 4) + reg, data);
sys/arch/sparc64/dev/pyro.c
709
u_int64_t reg;
sys/arch/sparc64/dev/pyro.c
741
reg = bus_space_read_8(sc->sc_bust, sc->sc_csrh,
sys/arch/sparc64/dev/pyro.c
743
CLR(reg, FIRE_MSI_MAP_EQNUM);
sys/arch/sparc64/dev/pyro.c
744
SET(reg, CPU_INFO_UNIT(ci)); /* There's an eq per cpu. */
sys/arch/sparc64/dev/pyro.c
746
FIRE_MSI_MAP(msinum), reg);
sys/arch/sparc64/dev/pyro.c
751
reg = bus_space_read_8(sc->sc_bust, sc->sc_csrh,
sys/arch/sparc64/dev/pyro.c
753
SET(reg, FIRE_MSI_MAP_V);
sys/arch/sparc64/dev/pyro.c
755
FIRE_MSI_MAP(msinum), reg);
sys/arch/sparc64/dev/rtc.c
224
rtc_read_reg(struct rtc_softc *sc, bus_size_t reg)
sys/arch/sparc64/dev/rtc.c
226
bus_space_write_1(sc->sc_iot, sc->sc_ioh, RTC_ADDR, reg);
sys/arch/sparc64/dev/rtc.c
231
rtc_write_reg(struct rtc_softc *sc, bus_size_t reg, u_int8_t val)
sys/arch/sparc64/dev/rtc.c
233
bus_space_write_1(sc->sc_iot, sc->sc_ioh, RTC_ADDR, reg);
sys/arch/sparc64/dev/schizo.c
179
u_int64_t match, reg;
sys/arch/sparc64/dev/schizo.c
256
reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL);
sys/arch/sparc64/dev/schizo.c
258
reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT | SCZ_PCICTRL_ARB;
sys/arch/sparc64/dev/schizo.c
259
reg &= ~SCZ_PCICTRL_SBH_INT;
sys/arch/sparc64/dev/schizo.c
260
schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg);
sys/arch/sparc64/dev/schizo.c
262
reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG);
sys/arch/sparc64/dev/schizo.c
263
reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY |
sys/arch/sparc64/dev/schizo.c
265
schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg);
sys/arch/sparc64/dev/schizo.c
471
schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
sys/arch/sparc64/dev/schizo.c
481
PCITAG_OFFSET(tag) + reg);
sys/arch/sparc64/dev/schizo.c
492
schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
sys/arch/sparc64/dev/schizo.c
495
PCITAG_OFFSET(tag) + reg, data);
sys/arch/sparc64/dev/vbus.c
138
int *reg = NULL, nreg;
sys/arch/sparc64/dev/vbus.c
163
getprop(node, "reg", sizeof(*reg), &nreg, (void **)®);
sys/arch/sparc64/dev/vbus.c
168
if (vbus_cmp_cells(imap, reg, imap_mask, address_cells) &&
sys/arch/sparc64/dev/vbus.c
174
free(reg, M_DEVBUF, 0);
sys/arch/sparc64/dev/vbus.c
175
reg = NULL;
sys/arch/sparc64/dev/vbus.c
177
getprop(node, "reg", sizeof(*reg), &nreg, (void **)®);
sys/arch/sparc64/dev/vbus.c
178
devhandle = reg[0] & 0x0fffffff;
sys/arch/sparc64/dev/vpci.c
381
vpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
sys/arch/sparc64/dev/vpci.c
386
hv_pci_config_get(pbm->vp_devhandle, PCITAG_OFFSET(tag), reg, 4,
sys/arch/sparc64/dev/vpci.c
393
vpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
sys/arch/sparc64/dev/vpci.c
398
hv_pci_config_put(pbm->vp_devhandle, PCITAG_OFFSET(tag), reg, 4,
sys/arch/sparc64/dev/zs.c
566
zs_read_reg(struct zs_chanstate *cs, u_char reg)
sys/arch/sparc64/dev/zs.c
570
*cs->cs_reg_csr = reg;
sys/arch/sparc64/dev/zs.c
578
zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val)
sys/arch/sparc64/dev/zs.c
580
*cs->cs_reg_csr = reg;
sys/arch/sparc64/fpu/fpu_explode.c
232
fpu_explode(struct fpemu *fe, struct fpn *fp, int type, int reg)
sys/arch/sparc64/fpu/fpu_explode.c
237
xspace = (u_int64_t *)&fe->fe_fpstate->fs_regs[reg & ~1];
sys/arch/sparc64/fpu/fpu_explode.c
239
space = &fe->fe_fpstate->fs_regs[reg];
sys/arch/sparc64/fpu/fpu_explode.c
294
reg));
sys/arch/sparc64/include/z8530var.h
66
u_char zs_read_reg(struct zs_chanstate *cs, u_char reg);
sys/arch/sparc64/include/z8530var.h
70
void zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val);
sys/arch/sparc64/sparc64/cpu.c
466
#define HB_MC0_REFRESH_COUNT(reg) \
sys/arch/sparc64/sparc64/cpu.c
467
(((reg) & HB_MC0_REFRESH_COUNT_MASK) >> HB_MC0_REFRESH_COUNT_SHIFT)
sys/arch/sparc64/sparc64/cpu.c
524
uint64_t reg;
sys/arch/sparc64/sparc64/cpu.c
526
reg = ldxa(HB_MC0, ASI_PHYS_NON_CACHED);
sys/arch/sparc64/sparc64/cpu.c
527
reg |= HB_MC0_SELF_REFRESH;
sys/arch/sparc64/sparc64/cpu.c
528
stxa(HB_MC0, ASI_PHYS_NON_CACHED, reg);
sys/arch/sparc64/sparc64/cpu.c
529
reg = ldxa(HB_MC0, ASI_PHYS_NON_CACHED);
sys/arch/sparc64/sparc64/cpu.c
535
uint64_t reg;
sys/arch/sparc64/sparc64/cpu.c
537
reg = ldxa(HB_MC0, ASI_PHYS_NON_CACHED);
sys/arch/sparc64/sparc64/cpu.c
538
reg &= ~HB_MC0_SELF_REFRESH;
sys/arch/sparc64/sparc64/cpu.c
539
stxa(HB_MC0, ASI_PHYS_NON_CACHED, reg);
sys/arch/sparc64/sparc64/cpu.c
540
reg = ldxa(HB_MC0, ASI_PHYS_NON_CACHED);
sys/arch/sparc64/sparc64/cpu.c
549
uint64_t reg;
sys/arch/sparc64/sparc64/cpu.c
551
reg = ldxa(HB_MC0, ASI_PHYS_NON_CACHED);
sys/arch/sparc64/sparc64/cpu.c
552
count = HB_MC0_REFRESH_COUNT(reg);
sys/arch/sparc64/sparc64/cpu.c
555
reg &= ~HB_MC0_REFRESH_COUNT_MASK;
sys/arch/sparc64/sparc64/cpu.c
556
reg |= (new_count << HB_MC0_REFRESH_COUNT_SHIFT);
sys/arch/sparc64/sparc64/cpu.c
557
stxa(HB_MC0, ASI_PHYS_NON_CACHED, reg);
sys/arch/sparc64/sparc64/cpu.c
558
reg = ldxa(HB_MC0, ASI_PHYS_NON_CACHED);
sys/arch/sparc64/sparc64/cpu.c
560
if (new_div > div && (reg & HB_MC0_SELF_REFRESH) == 0) {
sys/arch/sparc64/sparc64/cpu.c
572
uint64_t reg, s;
sys/arch/sparc64/sparc64/cpu.c
582
reg = ldxa(HB_ESTAR, ASI_PHYS_NON_CACHED);
sys/arch/sparc64/sparc64/cpu.c
583
estar_mode = reg & HB_ESTAR_MODE_MASK;
sys/arch/sparc64/sparc64/cpu.c
587
reg &= ~HB_ESTAR_MODE_MASK;
sys/arch/sparc64/sparc64/cpu.c
595
stxa(HB_ESTAR, ASI_PHYS_NON_CACHED, reg | HB_ESTAR_MODE_DIV_2);
sys/arch/sparc64/sparc64/cpu.c
601
stxa(HB_ESTAR, ASI_PHYS_NON_CACHED, reg | HB_ESTAR_MODE_DIV_1);
sys/arch/sparc64/sparc64/cpu.c
610
stxa(HB_ESTAR, ASI_PHYS_NON_CACHED, reg | HB_ESTAR_MODE_DIV_2);
sys/arch/sparc64/sparc64/cpu.c
615
stxa(HB_ESTAR, ASI_PHYS_NON_CACHED, reg | new_estar_mode);
sys/arch/sparc64/sparc64/cpu.c
622
stxa(HB_ESTAR, ASI_PHYS_NON_CACHED, reg | HB_ESTAR_MODE_DIV_2);
sys/arch/sparc64/sparc64/cpu.c
627
stxa(HB_ESTAR, ASI_PHYS_NON_CACHED, reg | HB_ESTAR_MODE_DIV_1);
sys/arch/sparc64/sparc64/cpu.c
632
stxa(HB_ESTAR, ASI_PHYS_NON_CACHED, reg | new_estar_mode);
sys/arch/sparc64/sparc64/cpu.c
635
stxa(HB_ESTAR, ASI_PHYS_NON_CACHED, reg | new_estar_mode);
sys/arch/sparc64/sparc64/ofw_machdep.c
1014
if ((len = OF_getprop(node, "reg", ®, sizeof(reg))) <= 0)
sys/arch/sparc64/sparc64/ofw_machdep.c
844
int reg[10];
sys/arch/sparc64/sparc64/ofw_machdep.c
870
if ((len = OF_getprop(node, "reg", ®, sizeof(reg))) <= 0) {
sys/arch/sparc64/sparc64/ofw_machdep.c
898
OFW_PCI_PHYS_HI_DEVICE(reg[0]) - 1) & 3) + 1;
sys/arch/sparc64/sparc64/ofw_machdep.c
900
*interrupt, reg[0]));
sys/arch/sparc64/sparc64/ofw_machdep.c
904
reg[0] = 0;
sys/arch/sparc64/sparc64/ofw_machdep.c
905
OF_getprop(node, "reg", ®, sizeof(reg));
sys/arch/sparc64/sparc64/ofw_machdep.c
943
DPRINTF(("%x.", reg[i]));
sys/arch/sparc64/sparc64/ofw_machdep.c
975
if (compare_cells(imap, reg,
sys/arch/sparc64/sparc64/process_machdep.c
115
process_write_regs(struct proc *p, struct reg *regs)
sys/arch/sparc64/sparc64/process_machdep.c
76
process_read_regs(struct proc *p, struct reg *regs)
sys/arch/sparc64/sparc64/rbus_machdep.c
108
reg = addr[i].phys_hi & OFW_PCI_PHYS_HI_REGISTERMASK;
sys/arch/sparc64/sparc64/rbus_machdep.c
109
if (reg < PCI_CB_MEMBASE0 || reg > PCI_CB_IOLIMIT1)
sys/arch/sparc64/sparc64/rbus_machdep.c
47
int space, reg;
sys/arch/sparc64/sparc64/rbus_machdep.c
62
reg = addr[i].phys_hi & OFW_PCI_PHYS_HI_REGISTERMASK;
sys/arch/sparc64/sparc64/rbus_machdep.c
63
if (reg < PCI_CB_MEMBASE0 || reg > PCI_CB_IOLIMIT1)
sys/arch/sparc64/sparc64/rbus_machdep.c
93
int space, reg;
sys/dev/acpi/abl.c
100
int reg;
sys/dev/acpi/abl.c
131
reg = pci_conf_read(pc, tag, PCI_ID_REG);
sys/dev/acpi/abl.c
133
switch (PCI_VENDOR(reg)) {
sys/dev/acpi/acpi.c
1520
acpi_read_pmreg(struct acpi_softc *sc, int reg, int offset)
sys/dev/acpi/acpi.c
1530
if (sc->sc_hw_reduced && reg == ACPIREG_PM1B_CNT) {
sys/dev/acpi/acpi.c
1539
if (sc->sc_hw_reduced && reg == ACPIREG_PM1A_STS &&
sys/dev/acpi/acpi.c
1553
switch (reg) {
sys/dev/acpi/acpi.c
1567
reg = ACPIREG_GPE0_STS;
sys/dev/acpi/acpi.c
1575
reg = ACPIREG_GPE0_EN;
sys/dev/acpi/acpi.c
1580
if (reg >= ACPIREG_MAXREG || sc->sc_pmregs[reg].size == 0)
sys/dev/acpi/acpi.c
1584
ioh = sc->sc_pmregs[reg].ioh;
sys/dev/acpi/acpi.c
1585
size = sc->sc_pmregs[reg].size;
sys/dev/acpi/acpi.c
1586
if (size > sc->sc_pmregs[reg].access)
sys/dev/acpi/acpi.c
1587
size = sc->sc_pmregs[reg].access;
sys/dev/acpi/acpi.c
1602
sc->sc_pmregs[reg].name,
sys/dev/acpi/acpi.c
1603
sc->sc_pmregs[reg].addr, offset, regval);
sys/dev/acpi/acpi.c
1609
acpi_write_pmreg(struct acpi_softc *sc, int reg, int offset, int regval)
sys/dev/acpi/acpi.c
1618
if (sc->sc_hw_reduced && reg == ACPIREG_PM1A_STS &&
sys/dev/acpi/acpi.c
1635
if (sc->sc_hw_reduced && reg == ACPIREG_PM1A_CNT &&
sys/dev/acpi/acpi.c
1649
switch (reg) {
sys/dev/acpi/acpi.c
1667
reg = ACPIREG_GPE0_STS;
sys/dev/acpi/acpi.c
1675
reg = ACPIREG_GPE0_EN;
sys/dev/acpi/acpi.c
1681
if (reg >= ACPIREG_MAXREG)
sys/dev/acpi/acpi.c
1684
ioh = sc->sc_pmregs[reg].ioh;
sys/dev/acpi/acpi.c
1685
size = sc->sc_pmregs[reg].size;
sys/dev/acpi/acpi.c
1686
if (size > sc->sc_pmregs[reg].access)
sys/dev/acpi/acpi.c
1687
size = sc->sc_pmregs[reg].access;
sys/dev/acpi/acpi.c
1702
sc->sc_pmregs[reg].name, sc->sc_pmregs[reg].addr, offset, regval);
sys/dev/acpi/acpi.c
1713
int reg;
sys/dev/acpi/acpi.c
1715
for (reg = 0; reg < ACPIREG_MAXREG; reg++) {
sys/dev/acpi/acpi.c
1718
switch (reg) {
sys/dev/acpi/acpi.c
1735
if (reg == ACPIREG_PM1A_EN && addr) {
sys/dev/acpi/acpi.c
1762
if (reg == ACPIREG_PM1B_EN && addr) {
sys/dev/acpi/acpi.c
1819
if (reg == ACPIREG_GPE0_EN && addr) {
sys/dev/acpi/acpi.c
1840
if (reg == ACPIREG_GPE1_EN && addr) {
sys/dev/acpi/acpi.c
1852
&sc->sc_pmregs[reg].ioh);
sys/dev/acpi/acpi.c
1854
sc->sc_pmregs[reg].name = name;
sys/dev/acpi/acpi.c
1855
sc->sc_pmregs[reg].size = size;
sys/dev/acpi/acpi.c
1856
sc->sc_pmregs[reg].addr = addr;
sys/dev/acpi/acpi.c
1857
sc->sc_pmregs[reg].access = min(access, 4);
sys/dev/acpi/acpi.c
1865
int reg;
sys/dev/acpi/acpi.c
1867
for (reg = 0; reg < ACPIREG_MAXREG; reg++) {
sys/dev/acpi/acpi.c
1868
if (sc->sc_pmregs[reg].size && sc->sc_pmregs[reg].addr)
sys/dev/acpi/acpi.c
1869
bus_space_unmap(sc->sc_iot, sc->sc_pmregs[reg].ioh,
sys/dev/acpi/acpi.c
1870
sc->sc_pmregs[reg].size);
sys/dev/acpi/acpi.c
190
acpi_pci_conf_read_1(pci_chipset_tag_t pc, pcitag_t tag, int reg)
sys/dev/acpi/acpi.c
192
uint32_t val = pci_conf_read(pc, tag, reg & ~0x3);
sys/dev/acpi/acpi.c
193
return (val >> ((reg & 0x3) << 3));
sys/dev/acpi/acpi.c
197
acpi_pci_conf_read_2(pci_chipset_tag_t pc, pcitag_t tag, int reg)
sys/dev/acpi/acpi.c
199
uint32_t val = pci_conf_read(pc, tag, reg & ~0x2);
sys/dev/acpi/acpi.c
200
return (val >> ((reg & 0x2) << 3));
sys/dev/acpi/acpi.c
204
acpi_pci_conf_read_4(pci_chipset_tag_t pc, pcitag_t tag, int reg)
sys/dev/acpi/acpi.c
206
return pci_conf_read(pc, tag, reg);
sys/dev/acpi/acpi.c
210
acpi_pci_conf_write_1(pci_chipset_tag_t pc, pcitag_t tag, int reg, uint8_t val)
sys/dev/acpi/acpi.c
212
uint32_t tmp = pci_conf_read(pc, tag, reg & ~0x3);
sys/dev/acpi/acpi.c
213
tmp &= ~(0xff << ((reg & 0x3) << 3));
sys/dev/acpi/acpi.c
214
tmp |= (val << ((reg & 0x3) << 3));
sys/dev/acpi/acpi.c
215
pci_conf_write(pc, tag, reg & ~0x3, tmp);
sys/dev/acpi/acpi.c
219
acpi_pci_conf_write_2(pci_chipset_tag_t pc, pcitag_t tag, int reg, uint16_t val)
sys/dev/acpi/acpi.c
221
uint32_t tmp = pci_conf_read(pc, tag, reg & ~0x2);
sys/dev/acpi/acpi.c
222
tmp &= ~(0xffff << ((reg & 0x2) << 3));
sys/dev/acpi/acpi.c
223
tmp |= (val << ((reg & 0x2) << 3));
sys/dev/acpi/acpi.c
224
pci_conf_write(pc, tag, reg & ~0x2, tmp);
sys/dev/acpi/acpi.c
228
acpi_pci_conf_write_4(pci_chipset_tag_t pc, pcitag_t tag, int reg, uint32_t val)
sys/dev/acpi/acpi.c
230
pci_conf_write(pc, tag, reg, val);
sys/dev/acpi/acpi.c
242
int reg, idx;
sys/dev/acpi/acpi.c
262
for (reg = 0; reg < len; reg += access_size) {
sys/dev/acpi/acpi.c
266
*(uint8_t *)(pb + reg) =
sys/dev/acpi/acpi.c
267
bus_space_read_1(iot, ioh, reg);
sys/dev/acpi/acpi.c
269
reg+address, *(uint8_t *)(pb+reg));
sys/dev/acpi/acpi.c
272
*(uint16_t *)(pb + reg) =
sys/dev/acpi/acpi.c
273
bus_space_read_2(iot, ioh, reg);
sys/dev/acpi/acpi.c
275
reg+address, *(uint16_t *)(pb+reg));
sys/dev/acpi/acpi.c
278
*(uint32_t *)(pb + reg) =
sys/dev/acpi/acpi.c
279
bus_space_read_4(iot, ioh, reg);
sys/dev/acpi/acpi.c
289
bus_space_write_1(iot, ioh, reg,
sys/dev/acpi/acpi.c
290
*(uint8_t *)(pb + reg));
sys/dev/acpi/acpi.c
292
reg+address, *(uint8_t *)(pb+reg));
sys/dev/acpi/acpi.c
295
bus_space_write_2(iot, ioh, reg,
sys/dev/acpi/acpi.c
296
*(uint16_t *)(pb + reg));
sys/dev/acpi/acpi.c
298
reg+address, *(uint16_t *)(pb+reg));
sys/dev/acpi/acpi.c
301
bus_space_write_4(iot, ioh, reg,
sys/dev/acpi/acpi.c
302
*(uint32_t *)(pb + reg));
sys/dev/acpi/acpi.c
335
reg = ACPI_PCI_REG(address);
sys/dev/acpi/acpi.c
341
acpi_pci_conf_read_1(pc, tag, reg + idx);
sys/dev/acpi/acpi.c
345
acpi_pci_conf_read_2(pc, tag, reg + idx);
sys/dev/acpi/acpi.c
349
acpi_pci_conf_read_4(pc, tag, reg + idx);
sys/dev/acpi/acpi.c
359
acpi_pci_conf_write_1(pc, tag, reg + idx,
sys/dev/acpi/acpi.c
363
acpi_pci_conf_write_2(pc, tag, reg + idx,
sys/dev/acpi/acpi.c
367
acpi_pci_conf_write_4(pc, tag, reg + idx,
sys/dev/acpi/acpi.c
610
uint32_t reg;
sys/dev/acpi/acpi.c
698
reg = pci_conf_read(pc, tag, PCI_ID_REG);
sys/dev/acpi/acpi.c
699
if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID) {
sys/dev/acpi/acpi.c
708
reg = pci_conf_read(pc, tag, PCI_CLASS_REG);
sys/dev/acpi/acpi.c
709
if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE &&
sys/dev/acpi/acpi.c
710
PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI) {
sys/dev/acpi/acpi.c
711
reg = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
sys/dev/acpi/acpi.c
712
pci->sub = PPB_BUSINFO_SECONDARY(reg);
sys/dev/acpi/acpi.c
892
pcireg_t reg;
sys/dev/acpi/acpi.c
903
reg = pci_conf_read(pc, tag, offset + PCI_PMCSR);
sys/dev/acpi/acpi.c
904
pci_conf_write(pc, tag, offset + PCI_PMCSR, reg);
sys/dev/acpi/acpidmar.c
2005
iommu_read_4(struct iommu_softc *iommu, int reg)
sys/dev/acpi/acpidmar.c
2009
v = bus_space_read_4(iommu->iot, iommu->ioh, reg);
sys/dev/acpi/acpidmar.c
2014
iommu_write_4(struct iommu_softc *iommu, int reg, uint32_t v)
sys/dev/acpi/acpidmar.c
2016
bus_space_write_4(iommu->iot, iommu->ioh, reg, (uint32_t)v);
sys/dev/acpi/acpidmar.c
2020
iommu_read_8(struct iommu_softc *iommu, int reg)
sys/dev/acpi/acpidmar.c
2024
v = bus_space_read_8(iommu->iot, iommu->ioh, reg);
sys/dev/acpi/acpidmar.c
2029
iommu_write_8(struct iommu_softc *iommu, int reg, uint64_t v)
sys/dev/acpi/acpidmar.c
2031
bus_space_write_8(iommu->iot, iommu->ioh, reg, v);
sys/dev/acpi/acpidmar.c
2042
pcireg_t reg;
sys/dev/acpi/acpidmar.c
2053
reg = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
sys/dev/acpi/acpidmar.c
2054
bus = PPB_BUSINFO_SECONDARY(reg);
sys/dev/acpi/acpidmar.c
2067
reg = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
sys/dev/acpi/acpidmar.c
2068
sec = PPB_BUSINFO_SECONDARY(reg);
sys/dev/acpi/acpidmar.c
2069
sub = PPB_BUSINFO_SUBORDINATE(reg);
sys/dev/acpi/acpidmar.c
2402
pcireg_t reg;
sys/dev/acpi/acpidmar.c
2415
reg = pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG);
sys/dev/acpi/acpidmar.c
2422
if (PCI_CLASS(reg) == PCI_CLASS_DISPLAY &&
sys/dev/acpi/acpidmar.c
2423
PCI_SUBCLASS(reg) == PCI_SUBCLASS_DISPLAY_VGA) {
sys/dev/acpi/acpidmar.c
2426
if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE &&
sys/dev/acpi/acpidmar.c
2427
PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_ISA) {
sys/dev/acpi/acpiec.c
219
int reg;
sys/dev/acpi/acpiec.c
229
for (reg = 0; reg < len; reg++)
sys/dev/acpi/acpiec.c
230
buffer[reg] = acpiec_read_1(sc, addr + reg);
sys/dev/acpi/acpiec.c
238
int reg;
sys/dev/acpi/acpiec.c
248
for (reg = 0; reg < len; reg++)
sys/dev/acpi/acpiec.c
249
acpiec_write_1(sc, addr + reg, buffer[reg]);
sys/dev/acpi/acpiprt.c
259
pcireg_t reg;
sys/dev/acpi/acpiprt.c
391
reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
sys/dev/acpi/acpiprt.c
392
if (PCI_HDRTYPE_MULTIFN(reg))
sys/dev/acpi/acpiprt.c
399
reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
sys/dev/acpi/acpiprt.c
400
if (PCI_INTERRUPT_PIN(reg) == pin + 1) {
sys/dev/acpi/acpiprt.c
401
reg &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
sys/dev/acpi/acpiprt.c
402
reg |= irq._int << PCI_INTERRUPT_LINE_SHIFT;
sys/dev/acpi/acpiprt.c
403
pci_conf_write(pc, tag, PCI_INTERRUPT_REG, reg);
sys/dev/acpi/amdgpio.c
240
uint32_t reg;
sys/dev/acpi/amdgpio.c
242
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, pin * 4);
sys/dev/acpi/amdgpio.c
244
return !!(reg & AMDGPIO_CONF_RXSTATE);
sys/dev/acpi/amdgpio.c
251
uint32_t reg;
sys/dev/acpi/amdgpio.c
253
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, pin * 4);
sys/dev/acpi/amdgpio.c
254
reg |= AMDGPIO_CONF_TXSTATE_EN;
sys/dev/acpi/amdgpio.c
256
reg |= AMDGPIO_CONF_TXSTATE;
sys/dev/acpi/amdgpio.c
258
reg &= ~AMDGPIO_CONF_TXSTATE;
sys/dev/acpi/amdgpio.c
259
bus_space_write_4(sc->sc_memt, sc->sc_memh, pin * 4, reg);
sys/dev/acpi/amdgpio.c
267
uint32_t reg;
sys/dev/acpi/amdgpio.c
276
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, pin * 4);
sys/dev/acpi/amdgpio.c
277
reg &= ~(AMDGPIO_CONF_MASK | AMDGPIO_CONF_LEVEL |
sys/dev/acpi/amdgpio.c
280
reg |= AMDGPIO_CONF_LEVEL;
sys/dev/acpi/amdgpio.c
282
reg |= AMDGPIO_CONF_ACTLO;
sys/dev/acpi/amdgpio.c
284
reg |= AMDGPIO_CONF_ACTBOTH;
sys/dev/acpi/amdgpio.c
285
reg |= (AMDGPIO_CONF_INT_MASK | AMDGPIO_CONF_INT_EN);
sys/dev/acpi/amdgpio.c
286
bus_space_write_4(sc->sc_memt, sc->sc_memh, pin * 4, reg);
sys/dev/acpi/amdgpio.c
296
uint32_t reg;
sys/dev/acpi/amdgpio.c
300
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, pin * 4);
sys/dev/acpi/amdgpio.c
301
reg |= (AMDGPIO_CONF_INT_MASK | AMDGPIO_CONF_INT_EN);
sys/dev/acpi/amdgpio.c
302
bus_space_write_4(sc->sc_memt, sc->sc_memh, pin * 4, reg);
sys/dev/acpi/amdgpio.c
309
uint32_t reg;
sys/dev/acpi/amdgpio.c
313
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, pin * 4);
sys/dev/acpi/amdgpio.c
314
reg &= ~(AMDGPIO_CONF_INT_MASK | AMDGPIO_CONF_INT_EN);
sys/dev/acpi/amdgpio.c
315
bus_space_write_4(sc->sc_memt, sc->sc_memh, pin * 4, reg);
sys/dev/acpi/amdgpio.c
321
uint32_t reg;
sys/dev/acpi/amdgpio.c
324
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, pin * 4);
sys/dev/acpi/amdgpio.c
325
if (reg & AMDGPIO_CONF_INT_STS) {
sys/dev/acpi/amdgpio.c
332
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/amdgpio.c
335
pin * 4, reg);
sys/dev/acpi/amdgpio.c
339
reg &= ~(AMDGPIO_CONF_INT_MASK | AMDGPIO_CONF_INT_EN);
sys/dev/acpi/amdgpio.c
341
pin * 4, reg);
sys/dev/acpi/amdgpio.c
353
uint32_t reg;
sys/dev/acpi/amdgpio.c
374
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/amdgpio.c
376
reg |= AMDGPIO_IRQ_MASTER_EOI;
sys/dev/acpi/amdgpio.c
378
AMDGPIO_IRQ_MASTER, reg);
sys/dev/acpi/amdpmc.c
197
pcireg_t reg;
sys/dev/acpi/amdpmc.c
215
reg = pci_conf_read(pc, tag, PCI_ID_REG);
sys/dev/acpi/amdpmc.c
216
KASSERT(PCI_VENDOR(reg) == PCI_VENDOR_AMD);
sys/dev/acpi/amdpmc.c
218
switch (PCI_PRODUCT(reg)) {
sys/dev/acpi/aplgpio.c
184
uint32_t reg;
sys/dev/acpi/aplgpio.c
186
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/aplgpio.c
189
return !!(reg & APLGPIO_CONF_RXSTATE);
sys/dev/acpi/aplgpio.c
196
uint32_t reg;
sys/dev/acpi/aplgpio.c
198
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/aplgpio.c
201
reg |= APLGPIO_CONF_TXSTATE;
sys/dev/acpi/aplgpio.c
203
reg &= ~APLGPIO_CONF_TXSTATE;
sys/dev/acpi/aplgpio.c
205
APLGPIO_PAD_CFG0 + pin * 8, reg);
sys/dev/acpi/aplgpio.c
213
uint32_t reg;
sys/dev/acpi/aplgpio.c
221
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/aplgpio.c
223
reg &= ~(APLGPIO_CONF_RXEV_MASK | APLGPIO_CONF_RXINV);
sys/dev/acpi/aplgpio.c
225
reg |= APLGPIO_CONF_RXEV_EDGE;
sys/dev/acpi/aplgpio.c
227
reg |= APLGPIO_CONF_RXINV;
sys/dev/acpi/aplgpio.c
229
reg |= APLGPIO_CONF_RXEV_EDGE | APLGPIO_CONF_RXEV_ZERO;
sys/dev/acpi/aplgpio.c
231
APLGPIO_PAD_CFG0 + pin * 8, reg);
sys/dev/acpi/aplgpio.c
233
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/aplgpio.c
235
reg |= (1 << (pin % 32));
sys/dev/acpi/aplgpio.c
237
APLGPIO_IRQ_EN + (pin / 32) * 4, reg);
sys/dev/acpi/aplgpio.c
244
uint32_t reg;
sys/dev/acpi/aplgpio.c
248
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/aplgpio.c
250
reg |= (1 << (pin % 32));
sys/dev/acpi/aplgpio.c
252
APLGPIO_IRQ_EN + (pin / 32) * 4, reg);
sys/dev/acpi/aplgpio.c
259
uint32_t reg;
sys/dev/acpi/aplgpio.c
263
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/aplgpio.c
265
reg &= ~(1 << (pin % 32));
sys/dev/acpi/aplgpio.c
267
APLGPIO_IRQ_EN + (pin / 32) * 4, reg);
sys/dev/acpi/bytgpio.c
128
uint32_t reg;
sys/dev/acpi/bytgpio.c
190
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, sc->sc_pins[i] * 16);
sys/dev/acpi/bytgpio.c
196
if (reg & BYTGPIO_CONF_DIRECT_IRQ_EN)
sys/dev/acpi/bytgpio.c
199
reg &= ~BYTGPIO_CONF_GD_MASK;
sys/dev/acpi/bytgpio.c
200
bus_space_write_4(sc->sc_memt, sc->sc_memh, sc->sc_pins[i] * 16, reg);
sys/dev/acpi/bytgpio.c
217
uint32_t reg;
sys/dev/acpi/bytgpio.c
219
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, sc->sc_pins[pin] * 16 + 8);
sys/dev/acpi/bytgpio.c
220
return (reg & BYTGPIO_PAD_VAL);
sys/dev/acpi/bytgpio.c
227
uint32_t reg;
sys/dev/acpi/bytgpio.c
229
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, sc->sc_pins[pin] * 16 + 8);
sys/dev/acpi/bytgpio.c
231
reg |= BYTGPIO_PAD_VAL;
sys/dev/acpi/bytgpio.c
233
reg &= ~BYTGPIO_PAD_VAL;
sys/dev/acpi/bytgpio.c
234
bus_space_write_4(sc->sc_memt, sc->sc_memh, sc->sc_pins[pin] * 16 + 8, reg);
sys/dev/acpi/bytgpio.c
257
uint32_t reg;
sys/dev/acpi/bytgpio.c
264
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, sc->sc_pins[pin] * 16);
sys/dev/acpi/bytgpio.c
265
reg &= ~BYTGPIO_CONF_GD_MASK;
sys/dev/acpi/bytgpio.c
267
reg |= BYTGPIO_CONF_GD_LEVEL;
sys/dev/acpi/bytgpio.c
269
reg |= BYTGPIO_CONF_GD_TNE;
sys/dev/acpi/bytgpio.c
271
reg |= BYTGPIO_CONF_GD_TPE;
sys/dev/acpi/bytgpio.c
273
reg |= BYTGPIO_CONF_GD_TNE | BYTGPIO_CONF_GD_TPE;
sys/dev/acpi/bytgpio.c
274
bus_space_write_4(sc->sc_memt, sc->sc_memh, sc->sc_pins[pin] * 16, reg);
sys/dev/acpi/bytgpio.c
281
uint32_t reg;
sys/dev/acpi/bytgpio.c
285
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, sc->sc_pins[pin] * 16);
sys/dev/acpi/bytgpio.c
286
reg &= ~BYTGPIO_CONF_GD_MASK;
sys/dev/acpi/bytgpio.c
287
bus_space_write_4(sc->sc_memt, sc->sc_memh, sc->sc_pins[pin] * 16, reg);
sys/dev/acpi/bytgpio.c
295
uint32_t reg;
sys/dev/acpi/bytgpio.c
301
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/bytgpio.c
304
BYTGPIO_IRQ_TS_0 + (pin / 8), reg);
sys/dev/acpi/bytgpio.c
306
if (reg & (1 << (pin % 32))) {
sys/dev/acpi/ccpmic.c
137
ccpmic_read_1(struct ccpmic_softc *sc, uint8_t reg, int flags)
sys/dev/acpi/ccpmic.c
144
®, sizeof(reg), &val, sizeof(val), flags);
sys/dev/acpi/ccpmic.c
149
sc->sc_dev.dv_xname, reg);
sys/dev/acpi/ccpmic.c
157
ccpmic_write_1(struct ccpmic_softc *sc, uint8_t reg, uint8_t val, int flags)
sys/dev/acpi/ccpmic.c
163
®, sizeof(reg), &val, sizeof(val), flags);
sys/dev/acpi/ccpmic.c
168
sc->sc_dev.dv_xname, reg);
sys/dev/acpi/ccpmic.c
280
uint8_t reg, val;
sys/dev/acpi/ccpmic.c
296
reg = ccpmic_power_regmap[i].hi;
sys/dev/acpi/ccpmic.c
297
val = ccpmic_read_1(sc, reg, 0);
sys/dev/acpi/ccpmic.c
308
ccpmic_write_1(sc, reg, val | CCPMIC_PWR_SEL, 0);
sys/dev/acpi/ccpmic.c
325
uint8_t reg;
sys/dev/acpi/ccpmic.c
330
reg = ((pin < 8) ? CCPMIC_GPIO0P0CTLO : CCPMIC_GPIO1P0CTLO) + pin % 8;
sys/dev/acpi/ccpmic.c
331
ccpmic_write_1(sc, reg, CCPMIC_GPIOCTLO_INPUT, 0);
sys/dev/acpi/ccpmic.c
332
reg = ((pin < 8) ? CCPMIC_GPIO0P0CTLI : CCPMIC_GPIO1P0CTLI) + pin % 8;
sys/dev/acpi/ccpmic.c
333
return ccpmic_read_1(sc, reg, 0) & CCPMIC_GPIOCTLI_VALUE;
sys/dev/acpi/ccpmic.c
340
uint8_t reg;
sys/dev/acpi/ccpmic.c
343
reg = CCPMIC_GPIOPANELCTL;
sys/dev/acpi/ccpmic.c
344
ccpmic_write_1(sc, reg, CCPMIC_GPIOCTLO_OUTPUT | !!value, 0);
sys/dev/acpi/ccpmic.c
351
reg = ((pin < 8) ? CCPMIC_GPIO0P0CTLO : CCPMIC_GPIO1P0CTLO) + pin % 8;
sys/dev/acpi/ccpmic.c
352
ccpmic_write_1(sc, reg, CCPMIC_GPIOCTLO_OUTPUT | !!value, 0);
sys/dev/acpi/chvgpio.c
270
uint32_t reg;
sys/dev/acpi/chvgpio.c
274
reg = chvgpio_read_pad_cfg0(sc, pin);
sys/dev/acpi/chvgpio.c
275
return (reg & CHVGPIO_PAD_CFG0_GPIORXSTATE);
sys/dev/acpi/chvgpio.c
282
uint32_t reg;
sys/dev/acpi/chvgpio.c
286
reg = chvgpio_read_pad_cfg0(sc, pin);
sys/dev/acpi/chvgpio.c
288
reg |= CHVGPIO_PAD_CFG0_GPIOTXSTATE;
sys/dev/acpi/chvgpio.c
290
reg &= ~CHVGPIO_PAD_CFG0_GPIOTXSTATE;
sys/dev/acpi/chvgpio.c
291
chvgpio_write_pad_cfg0(sc, pin, reg);
sys/dev/acpi/chvgpio.c
299
uint32_t reg;
sys/dev/acpi/chvgpio.c
304
reg = chvgpio_read_pad_cfg0(sc, pin);
sys/dev/acpi/chvgpio.c
305
reg &= CHVGPIO_PAD_CFG0_INTSEL_MASK;
sys/dev/acpi/chvgpio.c
306
line = reg >> CHVGPIO_PAD_CFG0_INTSEL_SHIFT;
sys/dev/acpi/chvgpio.c
312
reg = chvgpio_read_pad_cfg1(sc, pin);
sys/dev/acpi/chvgpio.c
313
reg &= ~CHVGPIO_PAD_CFG1_INTWAKECFG_MASK;
sys/dev/acpi/chvgpio.c
314
reg &= ~CHVGPIO_PAD_CFG1_INVRXTX_MASK;
sys/dev/acpi/chvgpio.c
317
reg |= CHVGPIO_PAD_CFG1_INVRXTX_RXDATA;
sys/dev/acpi/chvgpio.c
320
reg |= CHVGPIO_PAD_CFG1_INTWAKECFG_LEVEL;
sys/dev/acpi/chvgpio.c
323
reg |= CHVGPIO_PAD_CFG1_INTWAKECFG_FALLING;
sys/dev/acpi/chvgpio.c
326
reg |= CHVGPIO_PAD_CFG1_INTWAKECFG_RISING;
sys/dev/acpi/chvgpio.c
329
reg |= CHVGPIO_PAD_CFG1_INTWAKECFG_BOTH;
sys/dev/acpi/chvgpio.c
336
chvgpio_write_pad_cfg1(sc, pin, reg);
sys/dev/acpi/chvgpio.c
338
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/chvgpio.c
341
CHVGPIO_INTERRUPT_MASK, reg | (1 << line));
sys/dev/acpi/chvgpio.c
348
uint32_t reg;
sys/dev/acpi/chvgpio.c
353
reg = chvgpio_read_pad_cfg0(sc, pin);
sys/dev/acpi/chvgpio.c
354
reg &= CHVGPIO_PAD_CFG0_INTSEL_MASK;
sys/dev/acpi/chvgpio.c
355
line = reg >> CHVGPIO_PAD_CFG0_INTSEL_SHIFT;
sys/dev/acpi/chvgpio.c
357
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/chvgpio.c
360
CHVGPIO_INTERRUPT_MASK, reg | (1 << line));
sys/dev/acpi/chvgpio.c
367
uint32_t reg;
sys/dev/acpi/chvgpio.c
372
reg = chvgpio_read_pad_cfg0(sc, pin);
sys/dev/acpi/chvgpio.c
373
reg &= CHVGPIO_PAD_CFG0_INTSEL_MASK;
sys/dev/acpi/chvgpio.c
374
line = reg >> CHVGPIO_PAD_CFG0_INTSEL_SHIFT;
sys/dev/acpi/chvgpio.c
376
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/chvgpio.c
379
CHVGPIO_INTERRUPT_MASK, reg & ~(1 << line));
sys/dev/acpi/chvgpio.c
386
uint32_t reg;
sys/dev/acpi/chvgpio.c
390
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/chvgpio.c
393
if ((reg & (1 << line)) == 0)
sys/dev/acpi/dsdt.c
2356
int n, reg;
sys/dev/acpi/dsdt.c
2400
reg = pci_conf_read(pc, tag, PCI_CLASS_REG);
sys/dev/acpi/dsdt.c
2401
if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE &&
sys/dev/acpi/dsdt.c
2402
PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI) {
sys/dev/acpi/dsdt.c
2403
reg = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
sys/dev/acpi/dsdt.c
2404
addr->bus = PPB_BUSINFO_SECONDARY(reg);
sys/dev/acpi/dsdt.c
2422
int reg;
sys/dev/acpi/dsdt.c
2430
for (reg = 0; reg < len; reg += access_size) {
sys/dev/acpi/dsdt.c
2436
address + reg, access_size, &value);
sys/dev/acpi/dsdt.c
2441
*(uint8_t *)(pb + reg) = value;
sys/dev/acpi/dsdt.c
2444
*(uint16_t *)(pb + reg) = value;
sys/dev/acpi/dsdt.c
2447
*(uint32_t *)(pb + reg) = value;
sys/dev/acpi/dsdt.c
2457
value = *(uint8_t *)(pb + reg);
sys/dev/acpi/dsdt.c
2460
value = *(uint16_t *)(pb + reg);
sys/dev/acpi/dsdt.c
2463
value = *(uint32_t *)(pb + reg);
sys/dev/acpi/dsdt.c
2471
address + reg, access_size, &value);
sys/dev/acpi/dsdt.h
338
uint16_t reg;
sys/dev/acpi/dwgpio.c
186
int reg;
sys/dev/acpi/dwgpio.c
193
reg = acpi_getpropint(node, "reg", -1);
sys/dev/acpi/dwgpio.c
194
if (reg != 0)
sys/dev/acpi/dwgpio.c
206
uint32_t reg;
sys/dev/acpi/dwgpio.c
212
reg = HREAD4(sc, GPIO_EXT_PORTA);
sys/dev/acpi/dwgpio.c
213
val = (reg >> pin) & 1;
sys/dev/acpi/dwgpio.c
43
#define HREAD4(sc, reg) \
sys/dev/acpi/dwgpio.c
44
(bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg)))
sys/dev/acpi/dwgpio.c
45
#define HWRITE4(sc, reg, val) \
sys/dev/acpi/dwgpio.c
46
bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (val))
sys/dev/acpi/dwgpio.c
47
#define HSET4(sc, reg, bits) \
sys/dev/acpi/dwgpio.c
48
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/acpi/dwgpio.c
49
#define HCLR4(sc, reg, bits) \
sys/dev/acpi/dwgpio.c
50
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/acpi/glkgpio.c
184
uint32_t reg;
sys/dev/acpi/glkgpio.c
186
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/glkgpio.c
189
return !!(reg & GLKGPIO_CONF_RXSTATE);
sys/dev/acpi/glkgpio.c
196
uint32_t reg;
sys/dev/acpi/glkgpio.c
198
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/glkgpio.c
201
reg |= GLKGPIO_CONF_TXSTATE;
sys/dev/acpi/glkgpio.c
203
reg &= ~GLKGPIO_CONF_TXSTATE;
sys/dev/acpi/glkgpio.c
205
GLKGPIO_PAD_CFG0 + pin * 16, reg);
sys/dev/acpi/glkgpio.c
213
uint32_t reg;
sys/dev/acpi/glkgpio.c
221
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/glkgpio.c
223
reg &= ~(GLKGPIO_CONF_RXEV_MASK | GLKGPIO_CONF_RXINV);
sys/dev/acpi/glkgpio.c
225
reg |= GLKGPIO_CONF_RXEV_EDGE;
sys/dev/acpi/glkgpio.c
227
reg |= GLKGPIO_CONF_RXINV;
sys/dev/acpi/glkgpio.c
229
reg |= GLKGPIO_CONF_RXEV_EDGE | GLKGPIO_CONF_RXEV_ZERO;
sys/dev/acpi/glkgpio.c
231
GLKGPIO_PAD_CFG0 + pin * 16, reg);
sys/dev/acpi/glkgpio.c
233
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/glkgpio.c
235
reg |= (1 << (pin % 32));
sys/dev/acpi/glkgpio.c
237
GLKGPIO_IRQ_EN + (pin / 32) * 4, reg);
sys/dev/acpi/glkgpio.c
244
uint32_t reg;
sys/dev/acpi/glkgpio.c
248
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/glkgpio.c
250
reg |= (1 << (pin % 32));
sys/dev/acpi/glkgpio.c
252
GLKGPIO_IRQ_EN + (pin / 32) * 4, reg);
sys/dev/acpi/glkgpio.c
259
uint32_t reg;
sys/dev/acpi/glkgpio.c
263
reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
sys/dev/acpi/glkgpio.c
265
reg &= ~(1 << (pin % 32));
sys/dev/acpi/glkgpio.c
267
GLKGPIO_IRQ_EN + (pin / 32) * 4, reg);
sys/dev/acpi/pchgpio.c
608
uint32_t reg;
sys/dev/acpi/pchgpio.c
616
reg = bus_space_read_4(sc->sc_memt[bar], sc->sc_memh[bar],
sys/dev/acpi/pchgpio.c
619
return !!(reg & PCHGPIO_CONF_RXSTATE);
sys/dev/acpi/pchgpio.c
627
uint32_t reg;
sys/dev/acpi/pchgpio.c
635
reg = bus_space_read_4(sc->sc_memt[bar], sc->sc_memh[bar],
sys/dev/acpi/pchgpio.c
638
reg |= PCHGPIO_CONF_TXSTATE;
sys/dev/acpi/pchgpio.c
640
reg &= ~PCHGPIO_CONF_TXSTATE;
sys/dev/acpi/pchgpio.c
642
sc->sc_padbar[bar] + pad * sc->sc_padsize, reg);
sys/dev/acpi/pchgpio.c
651
uint32_t reg;
sys/dev/acpi/pchgpio.c
669
reg = bus_space_read_4(sc->sc_memt[bar], sc->sc_memh[bar],
sys/dev/acpi/pchgpio.c
671
reg &= ~(PCHGPIO_CONF_RXEV_MASK | PCHGPIO_CONF_RXINV);
sys/dev/acpi/pchgpio.c
673
reg |= PCHGPIO_CONF_RXEV_EDGE;
sys/dev/acpi/pchgpio.c
675
reg |= PCHGPIO_CONF_RXINV;
sys/dev/acpi/pchgpio.c
677
reg |= PCHGPIO_CONF_RXEV_EDGE | PCHGPIO_CONF_RXEV_ZERO;
sys/dev/acpi/pchgpio.c
679
sc->sc_padbar[bar] + pad * sc->sc_padsize, reg);
sys/dev/acpi/pchgpio.c
681
reg = bus_space_read_4(sc->sc_memt[bar], sc->sc_memh[bar],
sys/dev/acpi/pchgpio.c
683
reg |= (1 << (pin - group->gpiobase));
sys/dev/acpi/pchgpio.c
685
sc->sc_device->gpi_ie + bank * 4, reg);
sys/dev/acpi/pchgpio.c
693
uint32_t reg;
sys/dev/acpi/pchgpio.c
707
reg = bus_space_read_4(sc->sc_memt[bar], sc->sc_memh[bar],
sys/dev/acpi/pchgpio.c
709
reg |= (1 << (pin - group->gpiobase));
sys/dev/acpi/pchgpio.c
711
sc->sc_device->gpi_ie + bank * 4, reg);
sys/dev/acpi/pchgpio.c
719
uint32_t reg;
sys/dev/acpi/pchgpio.c
733
reg = bus_space_read_4(sc->sc_memt[bar], sc->sc_memh[bar],
sys/dev/acpi/pchgpio.c
735
reg &= ~(1 << (pin - group->gpiobase));
sys/dev/acpi/pchgpio.c
737
sc->sc_device->gpi_ie + bank * 4, reg);
sys/dev/acpi/qcgpio.c
442
uint32_t reg;
sys/dev/acpi/qcgpio.c
448
reg = HREAD4(sc, off + TLMM_GPIO_IN_OUT(pin));
sys/dev/acpi/qcgpio.c
449
return !!(reg & TLMM_GPIO_IN_OUT_GPIO_IN);
sys/dev/acpi/qcgpio.c
477
uint32_t reg;
sys/dev/acpi/qcgpio.c
487
reg = HREAD4(sc, off + TLMM_GPIO_INTR_CFG(pin));
sys/dev/acpi/qcgpio.c
488
reg &= ~TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK;
sys/dev/acpi/qcgpio.c
489
reg &= ~TLMM_GPIO_INTR_CFG_INTR_POL_CTL;
sys/dev/acpi/qcgpio.c
492
reg |= TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_LEVEL;
sys/dev/acpi/qcgpio.c
495
reg |= TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_LEVEL |
sys/dev/acpi/qcgpio.c
499
reg |= TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_NEG |
sys/dev/acpi/qcgpio.c
503
reg |= TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_POS |
sys/dev/acpi/qcgpio.c
507
reg |= TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_BOTH;
sys/dev/acpi/qcgpio.c
514
reg &= ~TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK;
sys/dev/acpi/qcgpio.c
515
reg |= TLMM_GPIO_INTR_CFG_TARGET_PROC_RPM;
sys/dev/acpi/qcgpio.c
516
reg |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN;
sys/dev/acpi/qcgpio.c
517
reg |= TLMM_GPIO_INTR_CFG_INTR_ENABLE;
sys/dev/acpi/qcgpio.c
518
HWRITE4(sc, off + TLMM_GPIO_INTR_CFG(pin), reg);
sys/dev/acpi/qcgpio.c
59
#define HREAD4(sc, reg) \
sys/dev/acpi/qcgpio.c
60
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/acpi/qcgpio.c
61
#define HWRITE4(sc, reg, val) \
sys/dev/acpi/qcgpio.c
62
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/acpi/qcgpio.c
63
#define HSET4(sc, reg, bits) \
sys/dev/acpi/qcgpio.c
64
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/acpi/qcgpio.c
65
#define HCLR4(sc, reg, bits) \
sys/dev/acpi/qcgpio.c
66
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/acpi/qciic.c
51
#define HREAD4(sc, reg) \
sys/dev/acpi/qciic.c
52
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/acpi/qciic.c
53
#define HWRITE4(sc, reg, val) \
sys/dev/acpi/qciic.c
54
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/acpi/tipmic.c
164
tipmic_read_1(struct tipmic_softc *sc, uint8_t reg, int flags)
sys/dev/acpi/tipmic.c
171
®, sizeof(reg), &val, sizeof(val), flags);
sys/dev/acpi/tipmic.c
176
sc->sc_dev.dv_xname, reg);
sys/dev/acpi/tipmic.c
184
tipmic_write_1(struct tipmic_softc *sc, uint8_t reg, uint8_t val, int flags)
sys/dev/acpi/tipmic.c
190
®, sizeof(reg), &val, sizeof(val), flags);
sys/dev/acpi/tipmic.c
195
sc->sc_dev.dv_xname, reg);
sys/dev/acpi/tipmic.c
306
uint8_t reg;
sys/dev/acpi/tipmic.c
323
reg = tipmic_read_1(sc, TIPMIC_ADC_CTRL, 0);
sys/dev/acpi/tipmic.c
324
reg |= TIPMIC_ADC_CTRL_EN;
sys/dev/acpi/tipmic.c
325
tipmic_write_1(sc, TIPMIC_ADC_CTRL, reg, 0);
sys/dev/acpi/tipmic.c
328
reg |= TIPMIC_ADC_CTRL_CH_SYSTEMP;
sys/dev/acpi/tipmic.c
333
tipmic_write_1(sc, TIPMIC_ADC_CTRL, reg, 0);
sys/dev/acpi/tipmic.c
340
reg |= TIPMIC_ADC_CTRL_START;
sys/dev/acpi/tipmic.c
341
tipmic_write_1(sc, TIPMIC_ADC_CTRL, reg, 0);
sys/dev/acpi/tipmic.c
349
reg = tipmic_read_1(sc, TIPMIC_INTR_MASK, I2C_F_POLL);
sys/dev/acpi/tipmic.c
350
reg &= ~TIPMIC_INTR_MASK_ADC;
sys/dev/acpi/tipmic.c
351
tipmic_write_1(sc, TIPMIC_INTR_MASK, reg, I2C_F_POLL);
sys/dev/acpi/tipmic.c
363
reg = tipmic_read_1(sc, TIPMIC_INTR_MASK, I2C_F_POLL);
sys/dev/acpi/tipmic.c
364
reg |= TIPMIC_INTR_MASK_ADC;
sys/dev/acpi/tipmic.c
365
tipmic_write_1(sc, TIPMIC_INTR_MASK, reg, I2C_F_POLL);
sys/dev/acpi/tipmic.c
374
reg = tipmic_read_1(sc, TIPMIC_ADC_CTRL, 0);
sys/dev/acpi/tipmic.c
375
reg &= ~(TIPMIC_ADC_CTRL_EN | TIPMIC_ADC_CTRL_CH_MASK);
sys/dev/acpi/tipmic.c
376
tipmic_write_1(sc, TIPMIC_ADC_CTRL, reg, 0);
sys/dev/acpi/tipmic.c
407
uint8_t reg, val;
sys/dev/acpi/tipmic.c
423
reg = tipmic_power_regmap[i].hi;
sys/dev/acpi/tipmic.c
424
val = tipmic_read_1(sc, reg, 0);
sys/dev/acpi/tipmic.c
432
tipmic_write_1(sc, reg, val, 0);
sys/dev/adb/adb.h
56
#define ADBLISTEN(dev, reg) ((((u_int8_t)dev & 0x0f) << 4) | 0x08 | reg)
sys/dev/adb/adb.h
57
#define ADBTALK(dev, reg) ((((u_int8_t)dev & 0x0f) << 4) | 0x0c | reg)
sys/dev/atapiscsi/atapiscsi.c
476
u_int8_t reg = CHP_READ_REG(chp, wdr_sdh);
sys/dev/atapiscsi/atapiscsi.c
478
WDC_LOG_REG(chp, wdr_sdh, reg);
sys/dev/atapiscsi/atapiscsi.c
480
return ((reg & 0x10) == (drive << 4));
sys/dev/cardbus/cardbus.c
151
int reg;
sys/dev/cardbus/cardbus.c
183
reg = CARDBUS_ROM_REG;
sys/dev/cardbus/cardbus.c
187
reg = CARDBUS_BASE0_REG + (cardbus_space - 1) * 4;
sys/dev/cardbus/cardbus.c
194
pci_conf_write(pc, tag, reg, 0);
sys/dev/cardbus/cardbus.c
195
if (Cardbus_mapreg_map(ca->ca_ct, reg,
sys/dev/cardbus/cardbus.c
211
exrom = pci_conf_read(pc, tag, reg);
sys/dev/cardbus/cardbus.c
212
pci_conf_write(pc, tag, reg, exrom | 1);
sys/dev/cardbus/cardbus.c
241
exrom = pci_conf_read(pc, tag, reg);
sys/dev/cardbus/cardbus.c
242
pci_conf_write(pc, tag, reg, exrom & ~1);
sys/dev/cardbus/cardbus.c
259
pci_conf_write(pc, tag, reg, 0);
sys/dev/cardbus/cardbus.c
261
Cardbus_mapreg_unmap(ca->ca_ct, reg, bar_tag, bar_memh,
sys/dev/cardbus/cardbus_map.c
108
pci_conf_write(pc, tag, reg, base);
sys/dev/cardbus/cardbus_map.c
138
cardbus_mapreg_unmap(struct cardbus_softc *sc, int func, int reg,
sys/dev/cardbus/cardbus_map.c
161
pci_conf_write(pc, cardbustag, reg, 0);
sys/dev/cardbus/cardbus_map.c
68
cardbus_mapreg_map(struct cardbus_softc *sc, int func, int reg,
sys/dev/cardbus/cardbus_map.c
89
if (pci_mapreg_info(pc, tag, reg, type, &base, &size, &flags))
sys/dev/cardbus/cardbusvar.h
290
#define Cardbus_mapreg_map(ct, reg, type, busflags, tagp, handlep, basep, sizep) \
sys/dev/cardbus/cardbusvar.h
292
(reg), (type), (busflags), (tagp), (handlep), (basep), (sizep))
sys/dev/cardbus/cardbusvar.h
293
#define Cardbus_mapreg_unmap(ct, reg, tag, handle, size)\
sys/dev/cardbus/cardbusvar.h
295
(reg), (tag), (handle), (size))
sys/dev/cardbus/com_cardbus.c
105
pcireg_t reg;
sys/dev/cardbus/com_cardbus.c
178
csc->cc_reg = cp->reg;
sys/dev/cardbus/com_cardbus.c
295
pcireg_t reg;
sys/dev/cardbus/com_cardbus.c
304
reg = pci_conf_read(pc, csc->cc_tag, PCI_COMMAND_STATUS_REG);
sys/dev/cardbus/com_cardbus.c
305
reg &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
sys/dev/cardbus/com_cardbus.c
306
reg |= csc->cc_csr;
sys/dev/cardbus/com_cardbus.c
307
pci_conf_write(pc, csc->cc_tag, PCI_COMMAND_STATUS_REG, reg);
sys/dev/cardbus/com_cardbus.c
313
reg = pci_conf_read(pc, csc->cc_tag, PCI_BHLC_REG);
sys/dev/cardbus/com_cardbus.c
314
if (PCI_LATTIMER(reg) < 0x20) {
sys/dev/cardbus/com_cardbus.c
315
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
sys/dev/cardbus/com_cardbus.c
316
reg |= (0x20 << PCI_LATTIMER_SHIFT);
sys/dev/cardbus/com_cardbus.c
317
pci_conf_write(pc, csc->cc_tag, PCI_BHLC_REG, reg);
sys/dev/cardbus/if_acx_cardbus.c
278
pcireg_t reg;
sys/dev/cardbus/if_acx_cardbus.c
298
reg = pci_conf_read(pc, csc->sc_tag,
sys/dev/cardbus/if_acx_cardbus.c
300
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
sys/dev/cardbus/if_acx_cardbus.c
303
reg |= PCI_COMMAND_IO_ENABLE;
sys/dev/cardbus/if_acx_cardbus.c
306
reg);
sys/dev/cardbus/if_ath_cardbus.c
262
pcireg_t reg;
sys/dev/cardbus/if_ath_cardbus.c
278
reg = pci_conf_read(pc, csc->sc_tag,
sys/dev/cardbus/if_ath_cardbus.c
280
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
sys/dev/cardbus/if_ath_cardbus.c
282
reg);
sys/dev/cardbus/if_ath_cardbus.c
288
reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG);
sys/dev/cardbus/if_ath_cardbus.c
289
if (PCI_LATTIMER(reg) < 0x20) {
sys/dev/cardbus/if_ath_cardbus.c
290
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
sys/dev/cardbus/if_ath_cardbus.c
291
reg |= (0x20 << PCI_LATTIMER_SHIFT);
sys/dev/cardbus/if_ath_cardbus.c
292
pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg);
sys/dev/cardbus/if_athn_cardbus.c
232
pcireg_t reg;
sys/dev/cardbus/if_athn_cardbus.c
243
reg = pci_conf_read(pc, csc->sc_tag,
sys/dev/cardbus/if_athn_cardbus.c
245
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
sys/dev/cardbus/if_athn_cardbus.c
247
reg);
sys/dev/cardbus/if_athn_cardbus.c
254
reg = pci_conf_read(pc, csc->sc_tag, 0x40);
sys/dev/cardbus/if_athn_cardbus.c
255
if (reg & 0xff00)
sys/dev/cardbus/if_athn_cardbus.c
256
pci_conf_write(pc, csc->sc_tag, 0x40, reg & ~0xff00);
sys/dev/cardbus/if_athn_cardbus.c
259
reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG);
sys/dev/cardbus/if_athn_cardbus.c
260
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
sys/dev/cardbus/if_athn_cardbus.c
261
reg |= 168 << PCI_LATTIMER_SHIFT;
sys/dev/cardbus/if_athn_cardbus.c
262
pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg);
sys/dev/cardbus/if_atw_cardbus.c
309
pcireg_t reg;
sys/dev/cardbus/if_atw_cardbus.c
325
reg = pci_conf_read(pc, csc->sc_tag,
sys/dev/cardbus/if_atw_cardbus.c
327
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
sys/dev/cardbus/if_atw_cardbus.c
328
reg |= csc->sc_csr;
sys/dev/cardbus/if_atw_cardbus.c
330
reg);
sys/dev/cardbus/if_atw_cardbus.c
336
reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG);
sys/dev/cardbus/if_atw_cardbus.c
337
if (PCI_LATTIMER(reg) < 0x20) {
sys/dev/cardbus/if_atw_cardbus.c
338
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
sys/dev/cardbus/if_atw_cardbus.c
339
reg |= (0x20 << PCI_LATTIMER_SHIFT);
sys/dev/cardbus/if_atw_cardbus.c
340
pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg);
sys/dev/cardbus/if_bwi_cardbus.c
101
pcireg_t reg;
sys/dev/cardbus/if_bwi_cardbus.c
135
reg = (sc->sc_conf_read)(sc, PCI_SUBSYS_ID_REG);
sys/dev/cardbus/if_bwi_cardbus.c
139
sc->sc_pci_subvid = PCI_VENDOR(reg);
sys/dev/cardbus/if_bwi_cardbus.c
140
sc->sc_pci_subdid = PCI_PRODUCT(reg);
sys/dev/cardbus/if_bwi_cardbus.c
183
pcireg_t reg;
sys/dev/cardbus/if_bwi_cardbus.c
194
reg = pci_conf_read(pc, csc->csc_tag,
sys/dev/cardbus/if_bwi_cardbus.c
196
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
sys/dev/cardbus/if_bwi_cardbus.c
198
reg);
sys/dev/cardbus/if_bwi_cardbus.c
245
bwi_cardbus_conf_write(void *self, uint32_t reg, uint32_t val)
sys/dev/cardbus/if_bwi_cardbus.c
250
pci_conf_write(pc, csc->csc_tag, reg, val);
sys/dev/cardbus/if_bwi_cardbus.c
254
bwi_cardbus_conf_read(void *self, uint32_t reg)
sys/dev/cardbus/if_bwi_cardbus.c
259
return (pci_conf_read(pc, csc->csc_tag, reg));
sys/dev/cardbus/if_dc_cardbus.c
121
pcireg_t reg;
sys/dev/cardbus/if_dc_cardbus.c
210
reg = pci_conf_read(pc, ca->ca_tag, PCI_BHLC_REG);
sys/dev/cardbus/if_dc_cardbus.c
211
if (PCI_LATTIMER(reg) < 0x20) {
sys/dev/cardbus/if_dc_cardbus.c
212
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
sys/dev/cardbus/if_dc_cardbus.c
213
reg |= (0x20 << PCI_LATTIMER_SHIFT);
sys/dev/cardbus/if_dc_cardbus.c
214
pci_conf_write(pc, ca->ca_tag, PCI_BHLC_REG, reg);
sys/dev/cardbus/if_dc_cardbus.c
256
pcireg_t reg;
sys/dev/cardbus/if_dc_cardbus.c
260
reg = pci_conf_read(pc, csc->sc_tag, PCI_CFDA);
sys/dev/cardbus/if_dc_cardbus.c
261
if (reg & (DC_CFDA_SUSPEND|DC_CFDA_STANDBY)) {
sys/dev/cardbus/if_dc_cardbus.c
263
reg & ~(DC_CFDA_SUSPEND|DC_CFDA_STANDBY));
sys/dev/cardbus/if_dc_cardbus.c
279
reg = pci_conf_read(csc->sc_pc, csc->sc_tag, PCI_COMMAND_STATUS_REG);
sys/dev/cardbus/if_dc_cardbus.c
280
reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
sys/dev/cardbus/if_dc_cardbus.c
282
pci_conf_write(csc->sc_pc, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
sys/dev/cardbus/if_dc_cardbus.c
283
reg = pci_conf_read(csc->sc_pc, csc->sc_tag, PCI_COMMAND_STATUS_REG);
sys/dev/cardbus/if_fxp_cardbus.c
206
int reg;
sys/dev/cardbus/if_fxp_cardbus.c
212
reg = CARDBUS_BASE0_REG;
sys/dev/cardbus/if_fxp_cardbus.c
214
reg = CARDBUS_BASE1_REG;
sys/dev/cardbus/if_fxp_cardbus.c
215
Cardbus_mapreg_unmap(ct, reg, sc->sc_st, sc->sc_sh, csc->size);
sys/dev/cardbus/if_malo_cardbus.c
177
pcireg_t reg;
sys/dev/cardbus/if_malo_cardbus.c
190
reg = pci_conf_read(pc, csc->sc_tag,
sys/dev/cardbus/if_malo_cardbus.c
192
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
sys/dev/cardbus/if_malo_cardbus.c
194
reg);
sys/dev/cardbus/if_pgt_cardbus.c
225
pcireg_t reg;
sys/dev/cardbus/if_pgt_cardbus.c
236
reg = pci_conf_read(pc, csc->sc_tag,
sys/dev/cardbus/if_pgt_cardbus.c
238
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
sys/dev/cardbus/if_pgt_cardbus.c
240
reg);
sys/dev/cardbus/if_ral_cardbus.c
304
pcireg_t reg;
sys/dev/cardbus/if_ral_cardbus.c
315
reg = pci_conf_read(pc, csc->sc_tag,
sys/dev/cardbus/if_ral_cardbus.c
317
reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
sys/dev/cardbus/if_ral_cardbus.c
319
reg);
sys/dev/cardbus/if_re_cardbus.c
167
pcireg_t reg, command;
sys/dev/cardbus/if_re_cardbus.c
207
reg = pci_conf_read(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG);
sys/dev/cardbus/if_re_cardbus.c
208
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
sys/dev/cardbus/if_re_cardbus.c
209
reg |= csc->sc_csr;
sys/dev/cardbus/if_re_cardbus.c
210
pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
sys/dev/cardbus/if_re_cardbus.c
213
reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG);
sys/dev/cardbus/if_re_cardbus.c
214
if (PCI_LATTIMER(reg) < 0x20) {
sys/dev/cardbus/if_re_cardbus.c
215
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
sys/dev/cardbus/if_re_cardbus.c
216
reg |= (0x20 << PCI_LATTIMER_SHIFT);
sys/dev/cardbus/if_re_cardbus.c
217
pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg);
sys/dev/cardbus/if_rl_cardbus.c
228
pcireg_t reg, command;
sys/dev/cardbus/if_rl_cardbus.c
275
reg = pci_conf_read(pc, csc->sc_tag,
sys/dev/cardbus/if_rl_cardbus.c
277
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
sys/dev/cardbus/if_rl_cardbus.c
278
reg |= csc->sc_csr;
sys/dev/cardbus/if_rl_cardbus.c
280
PCI_COMMAND_STATUS_REG, reg);
sys/dev/cardbus/if_rl_cardbus.c
286
reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG);
sys/dev/cardbus/if_rl_cardbus.c
287
if (PCI_LATTIMER(reg) < 0x20) {
sys/dev/cardbus/if_rl_cardbus.c
288
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
sys/dev/cardbus/if_rl_cardbus.c
289
reg |= (0x20 << PCI_LATTIMER_SHIFT);
sys/dev/cardbus/if_rl_cardbus.c
290
pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg);
sys/dev/cardbus/if_rtw_cardbus.c
165
u_int32_t reg;
sys/dev/cardbus/if_rtw_cardbus.c
167
reg = RTW_READ(regs, RTW_CONFIG3);
sys/dev/cardbus/if_rtw_cardbus.c
169
RTW_WRITE(regs, RTW_CONFIG3, reg | RTW_CONFIG3_FUNCREGEN);
sys/dev/cardbus/if_rtw_cardbus.c
171
RTW_WRITE(regs, RTW_CONFIG3, reg & ~RTW_CONFIG3_FUNCREGEN);
sys/dev/cardbus/if_rtw_cardbus.c
378
pcireg_t reg;
sys/dev/cardbus/if_rtw_cardbus.c
383
reg = pci_conf_read(pc, csc->sc_tag, pmreg + 4) & 0x03;
sys/dev/cardbus/if_rtw_cardbus.c
385
if (reg == 3) {
sys/dev/cardbus/if_rtw_cardbus.c
395
if (reg != 0) {
sys/dev/cardbus/if_rtw_cardbus.c
397
sc->sc_dev.dv_xname, reg);
sys/dev/cardbus/if_rtw_cardbus.c
412
reg = pci_conf_read(pc, csc->sc_tag,
sys/dev/cardbus/if_rtw_cardbus.c
414
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
sys/dev/cardbus/if_rtw_cardbus.c
415
reg |= csc->sc_csr;
sys/dev/cardbus/if_rtw_cardbus.c
417
reg);
sys/dev/cardbus/if_rtw_cardbus.c
423
reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG);
sys/dev/cardbus/if_rtw_cardbus.c
424
if (PCI_LATTIMER(reg) < 0x20) {
sys/dev/cardbus/if_rtw_cardbus.c
425
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
sys/dev/cardbus/if_rtw_cardbus.c
426
reg |= (0x20 << PCI_LATTIMER_SHIFT);
sys/dev/cardbus/if_rtw_cardbus.c
427
pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg);
sys/dev/cardbus/puc_cardbus.c
120
if (pci_get_capability(pc, ca->ca_tag, PCI_CAP_PWRMGMT, ®,
sys/dev/cardbus/puc_cardbus.c
122
reg = pci_conf_read(pc, ca->ca_tag, reg + 4) & 3;
sys/dev/cardbus/puc_cardbus.c
123
if (reg) {
sys/dev/cardbus/puc_cardbus.c
125
sc->sc_dev.dv_xname, reg);
sys/dev/cardbus/puc_cardbus.c
126
pci_conf_write(pc, ca->ca_tag, reg + 4, 0);
sys/dev/cardbus/puc_cardbus.c
56
pcireg_t bhlc, reg;
sys/dev/cardbus/puc_cardbus.c
67
reg = pci_conf_read(pc, ca->ca_tag, PCI_SUBSYS_ID_REG);
sys/dev/cardbus/puc_cardbus.c
69
PCI_PRODUCT(ca->ca_id), PCI_VENDOR(reg), PCI_PRODUCT(reg)))
sys/dev/cardbus/puc_cardbus.c
86
pcireg_t reg;
sys/dev/cardbus/puc_cardbus.c
93
reg = pci_conf_read(pc, ca->ca_tag, PCI_SUBSYS_ID_REG);
sys/dev/cardbus/puc_cardbus.c
95
PCI_PRODUCT(ca->ca_id), PCI_VENDOR(reg), PCI_PRODUCT(reg));
sys/dev/fdt/acrtc.c
127
acrtc_read_reg(struct acrtc_softc *sc, uint8_t reg)
sys/dev/fdt/acrtc.c
129
return rsb_read_2(sc->sc_cookie, sc->sc_rta, reg);
sys/dev/fdt/acrtc.c
133
acrtc_write_reg(struct acrtc_softc *sc, uint8_t reg, uint16_t value)
sys/dev/fdt/acrtc.c
135
rsb_write_2(sc->sc_cookie, sc->sc_rta, reg, value);
sys/dev/fdt/acrtc.c
222
uint16_t reg;
sys/dev/fdt/acrtc.c
224
reg = acrtc_read_reg(sc, CK32K_OUT_CTRL1 + idx);
sys/dev/fdt/acrtc.c
225
reg &= ~CK32K_OUT_CTRL_PRE_DIV_MASK;
sys/dev/fdt/acrtc.c
226
reg &= ~CK32K_OUT_CTRL_MUX_SEL_MASK;
sys/dev/fdt/acrtc.c
227
reg &= ~CK32K_OUT_CTRL_POST_DIV_MASK;
sys/dev/fdt/acrtc.c
228
reg |= CK32K_OUT_CTRL_PRE_DIV_32K;
sys/dev/fdt/acrtc.c
229
reg |= CK32K_OUT_CTRL_MUX_SEL_32K;
sys/dev/fdt/acrtc.c
230
reg |= CK32K_OUT_CTRL_POST_DIV_32K;
sys/dev/fdt/acrtc.c
232
reg |= CK32K_OUT_CTRL_ENA;
sys/dev/fdt/acrtc.c
234
reg &= ~CK32K_OUT_CTRL_ENA;
sys/dev/fdt/acrtc.c
235
acrtc_write_reg(sc, CK32K_OUT_CTRL1 + idx, reg);
sys/dev/fdt/amlclock.c
106
#define HREAD4(sc, reg) \
sys/dev/fdt/amlclock.c
107
(regmap_read_4((sc)->sc_rm, (reg) << 2))
sys/dev/fdt/amlclock.c
108
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amlclock.c
109
regmap_write_4((sc)->sc_rm, (reg) << 2, (val))
sys/dev/fdt/amlclock.c
110
#define HSET4(sc, reg, bits) \
sys/dev/fdt/amlclock.c
111
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/amlclock.c
112
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/amlclock.c
113
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/amlclock.c
116
uint8_t reg;
sys/dev/fdt/amlclock.c
208
uint32_t reg, mux, div;
sys/dev/fdt/amlclock.c
211
reg = HREAD4(sc, offset);
sys/dev/fdt/amlclock.c
212
if (reg & HHI_SYS_CPU_CLK_FINAL_MUX_SEL) {
sys/dev/fdt/amlclock.c
219
if (reg & HHI_SYS_CPU_CLK_FINAL_DYN_MUX_SEL) {
sys/dev/fdt/amlclock.c
220
div = (reg & HHI_SYS_CPU_CLK_POSTMUX1) ?
sys/dev/fdt/amlclock.c
221
(HHI_SYS_CPU_CLK_MUX1_DIVN_TCNT(reg) + 1) : 1;
sys/dev/fdt/amlclock.c
222
mux = HHI_SYS_CPU_CLK_PREMUX1(reg);
sys/dev/fdt/amlclock.c
224
div = (reg & HHI_SYS_CPU_CLK_POSTMUX0) ?
sys/dev/fdt/amlclock.c
225
(HHI_SYS_CPU_CLK_MUX0_DIVN_TCNT(reg) + 1) : 1;
sys/dev/fdt/amlclock.c
226
mux = HHI_SYS_CPU_CLK_PREMUX0(reg);
sys/dev/fdt/amlclock.c
247
uint32_t reg, div;
sys/dev/fdt/amlclock.c
255
reg = HREAD4(sc, offset);
sys/dev/fdt/amlclock.c
261
if (reg & HHI_SYS_CPU_CLK_FINAL_MUX_SEL) {
sys/dev/fdt/amlclock.c
262
reg &= ~HHI_SYS_CPU_CLK_FINAL_MUX_SEL;
sys/dev/fdt/amlclock.c
263
HWRITE4(sc, offset, reg);
sys/dev/fdt/amlclock.c
274
reg |= HHI_SYS_CPU_CLK_FINAL_MUX_SEL;
sys/dev/fdt/amlclock.c
275
HWRITE4(sc, offset, reg);
sys/dev/fdt/amlclock.c
304
if (reg & HHI_SYS_CPU_CLK_FINAL_DYN_MUX_SEL) {
sys/dev/fdt/amlclock.c
306
reg = HREAD4(sc, offset);
sys/dev/fdt/amlclock.c
307
reg &= ~HHI_SYS_CPU_CLK_PREMUX0_MASK;
sys/dev/fdt/amlclock.c
309
reg |= HHI_SYS_CPU_CLK_PREMUX0_FCLK_DIV2;
sys/dev/fdt/amlclock.c
311
reg |= HHI_SYS_CPU_CLK_PREMUX0_FCLK_DIV3;
sys/dev/fdt/amlclock.c
312
HWRITE4(sc, offset, reg);
sys/dev/fdt/amlclock.c
317
reg = HREAD4(sc, offset);
sys/dev/fdt/amlclock.c
318
reg &= ~HHI_SYS_CPU_CLK_DYN_ENABLE;
sys/dev/fdt/amlclock.c
319
reg &= ~HHI_SYS_CPU_CLK_MUX0_DIVN_TCNT_MASK;
sys/dev/fdt/amlclock.c
320
reg |= ((div - 1) << HHI_SYS_CPU_CLK_MUX0_DIVN_TCNT_SHIFT);
sys/dev/fdt/amlclock.c
321
HWRITE4(sc, offset, reg);
sys/dev/fdt/amlclock.c
330
reg = HREAD4(sc, offset);
sys/dev/fdt/amlclock.c
331
reg &= ~HHI_SYS_CPU_CLK_FINAL_DYN_MUX_SEL;
sys/dev/fdt/amlclock.c
332
reg &= ~HHI_SYS_CPU_CLK_FINAL_MUX_SEL;
sys/dev/fdt/amlclock.c
333
HWRITE4(sc, offset, reg);
sys/dev/fdt/amlclock.c
337
reg = HREAD4(sc, offset);
sys/dev/fdt/amlclock.c
338
reg &= ~HHI_SYS_CPU_CLK_PREMUX1_MASK;
sys/dev/fdt/amlclock.c
340
reg |= HHI_SYS_CPU_CLK_PREMUX1_FCLK_DIV2;
sys/dev/fdt/amlclock.c
342
reg |= HHI_SYS_CPU_CLK_PREMUX1_FCLK_DIV3;
sys/dev/fdt/amlclock.c
343
HWRITE4(sc, offset, reg);
sys/dev/fdt/amlclock.c
348
reg = HREAD4(sc, offset);
sys/dev/fdt/amlclock.c
349
reg &= ~HHI_SYS_CPU_CLK_DYN_ENABLE;
sys/dev/fdt/amlclock.c
350
reg &= ~HHI_SYS_CPU_CLK_MUX1_DIVN_TCNT_MASK;
sys/dev/fdt/amlclock.c
351
reg |= ((div - 1) << HHI_SYS_CPU_CLK_MUX1_DIVN_TCNT_SHIFT);
sys/dev/fdt/amlclock.c
352
HWRITE4(sc, offset, reg);
sys/dev/fdt/amlclock.c
361
reg = HREAD4(sc, offset);
sys/dev/fdt/amlclock.c
362
reg |= HHI_SYS_CPU_CLK_FINAL_DYN_MUX_SEL;
sys/dev/fdt/amlclock.c
363
reg &= ~HHI_SYS_CPU_CLK_FINAL_MUX_SEL;
sys/dev/fdt/amlclock.c
364
HWRITE4(sc, offset, reg);
sys/dev/fdt/amlclock.c
375
uint32_t reg, div;
sys/dev/fdt/amlclock.c
395
reg = HREAD4(sc, offset);
sys/dev/fdt/amlclock.c
396
reg &= ~HHI_SYS_DPLL_OD_MASK;
sys/dev/fdt/amlclock.c
397
reg |= ((fls(div) - 1) << HHI_SYS_DPLL_OD_SHIFT);
sys/dev/fdt/amlclock.c
398
reg &= ~(HHI_SYS_DPLL_M_MASK | HHI_SYS_DPLL_N_MASK);
sys/dev/fdt/amlclock.c
399
reg |= (m << HHI_SYS_DPLL_M_SHIFT);
sys/dev/fdt/amlclock.c
400
reg |= (n << HHI_SYS_DPLL_N_SHIFT);
sys/dev/fdt/amlclock.c
401
HWRITE4(sc, offset, reg);
sys/dev/fdt/amlclock.c
420
uint32_t reg, mux, div;
sys/dev/fdt/amlclock.c
425
reg = HREAD4(sc, HHI_SYS_PLL_CNTL0);
sys/dev/fdt/amlclock.c
426
div = 1 << HHI_SYS_DPLL_OD(reg);
sys/dev/fdt/amlclock.c
427
m = HHI_SYS_DPLL_M(reg);
sys/dev/fdt/amlclock.c
428
n = HHI_SYS_DPLL_N(reg);
sys/dev/fdt/amlclock.c
431
reg = HREAD4(sc, HHI_SYS1_PLL_CNTL0);
sys/dev/fdt/amlclock.c
432
div = 1 << HHI_SYS_DPLL_OD(reg);
sys/dev/fdt/amlclock.c
433
m = HHI_SYS_DPLL_M(reg);
sys/dev/fdt/amlclock.c
434
n = HHI_SYS_DPLL_N(reg);
sys/dev/fdt/amlclock.c
450
reg = HREAD4(sc, HHI_MPEG_CLK_CNTL);
sys/dev/fdt/amlclock.c
451
mux = (reg >> 12) & 0x7;
sys/dev/fdt/amlclock.c
452
div = ((reg >> 0) & 0x7f) + 1;
sys/dev/fdt/amlclock.c
479
reg = HREAD4(sc, HHI_SD_EMMC_CLK_CNTL);
sys/dev/fdt/amlclock.c
480
mux = (reg >> 9) & 0x7;
sys/dev/fdt/amlclock.c
481
div = ((reg >> 0) & 0x7f) + 1;
sys/dev/fdt/amlclock.c
502
reg = HREAD4(sc, HHI_SD_EMMC_CLK_CNTL);
sys/dev/fdt/amlclock.c
503
mux = (reg >> 25) & 0x7;
sys/dev/fdt/amlclock.c
504
div = ((reg >> 16) & 0x7f) + 1;
sys/dev/fdt/amlclock.c
525
reg = HREAD4(sc, HHI_NAND_CLK_CNTL);
sys/dev/fdt/amlclock.c
526
mux = (reg >> 9) & 0x7;
sys/dev/fdt/amlclock.c
527
div = ((reg >> 0) & 0x7f) + 1;
sys/dev/fdt/amlclock.c
605
if (idx < sc->sc_ngates && sc->sc_gates[idx].reg != 0) {
sys/dev/fdt/amlclock.c
607
HSET4(sc, sc->sc_gates[idx].reg,
sys/dev/fdt/amlclock.c
610
HCLR4(sc, sc->sc_gates[idx].reg,
sys/dev/fdt/amldwusb.c
105
#define HREAD4(sc, reg) \
sys/dev/fdt/amldwusb.c
106
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/amldwusb.c
107
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amldwusb.c
108
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/amldwusb.c
109
#define HSET4(sc, reg, bits) \
sys/dev/fdt/amldwusb.c
110
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/amldwusb.c
111
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/amldwusb.c
112
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/amldwusb.c
148
uint32_t reg;
sys/dev/fdt/amldwusb.c
175
reg = HREAD4(sc, USB_R1);
sys/dev/fdt/amldwusb.c
176
reg &= ~USB_R1_U3H_FLADJ_30MHZ_REG_MASK;
sys/dev/fdt/amldwusb.c
177
reg |= (0x20 << USB_R1_U3H_FLADJ_30MHZ_REG_SHIFT);
sys/dev/fdt/amldwusb.c
178
HWRITE4(sc, USB_R1, reg);
sys/dev/fdt/amldwusb.c
182
reg = HREAD4(sc, USB_R5);
sys/dev/fdt/amldwusb.c
183
reg &= ~USB_R5_ID_DIG_TH_MASK;
sys/dev/fdt/amldwusb.c
184
reg |= (0xff << USB_R5_ID_DIG_TH_SHIFT);
sys/dev/fdt/amldwusb.c
185
HWRITE4(sc, USB_R5, reg);
sys/dev/fdt/amldwusb.c
218
uint32_t reg;
sys/dev/fdt/amldwusb.c
220
reg = HREAD4(sc, USB_R3);
sys/dev/fdt/amldwusb.c
221
reg &= ~USB_R3_P30_SSC_RANGE_MASK;
sys/dev/fdt/amldwusb.c
222
reg |= USB_R3_P30_SSC_ENABLE;
sys/dev/fdt/amldwusb.c
223
reg |= (2 << USB_R3_P30_SSC_RANGE_SHIFT);
sys/dev/fdt/amldwusb.c
224
reg |= USB_R3_P30_REF_SSP_EN;
sys/dev/fdt/amldwusb.c
225
HWRITE4(sc, USB_R3, reg);
sys/dev/fdt/amldwusb.c
229
reg = HREAD4(sc, USB_R2);
sys/dev/fdt/amldwusb.c
230
reg &= ~USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK;
sys/dev/fdt/amldwusb.c
231
reg |= (0x15 << USB_R2_P30_PCS_TX_DEEMPH_3P5DB_SHIFT);
sys/dev/fdt/amldwusb.c
232
HWRITE4(sc, USB_R2, reg);
sys/dev/fdt/amldwusb.c
233
reg = HREAD4(sc, USB_R2);
sys/dev/fdt/amldwusb.c
234
reg &= ~USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK;
sys/dev/fdt/amldwusb.c
235
reg |= (0x15 << USB_R2_P30_PCS_TX_DEEMPH_6DB_SHIFT);
sys/dev/fdt/amldwusb.c
236
HWRITE4(sc, USB_R2, reg);
sys/dev/fdt/amldwusb.c
241
reg = HREAD4(sc, USB_R1);
sys/dev/fdt/amldwusb.c
242
reg &= ~USB_R1_P30_PCS_TX_SWING_FULL_MASK;
sys/dev/fdt/amldwusb.c
243
reg |= (0x7f << USB_R1_P30_PCS_TX_SWING_FULL_SHIFT);
sys/dev/fdt/amldwusb.c
244
HWRITE4(sc, USB_R1, reg);
sys/dev/fdt/amliic.c
271
uint32_t reg[1];
sys/dev/fdt/amliic.c
276
memset(reg, 0, sizeof(reg));
sys/dev/fdt/amliic.c
286
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/dev/fdt/amliic.c
291
ia.ia_addr = bemtoh32(®[0]);
sys/dev/fdt/amliic.c
58
#define HREAD4(sc, reg) \
sys/dev/fdt/amliic.c
59
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/amliic.c
60
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amliic.c
61
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/amliic.c
62
#define HSET4(sc, reg, bits) \
sys/dev/fdt/amliic.c
63
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/amliic.c
64
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/amliic.c
65
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/amlmmc.c
108
#define HREAD4(sc, reg) \
sys/dev/fdt/amlmmc.c
109
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/amlmmc.c
110
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amlmmc.c
111
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/amlmmc.c
112
#define HSET4(sc, reg, bits) \
sys/dev/fdt/amlmmc.c
113
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/amlmmc.c
114
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/amlmmc.c
115
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/amlpciephy.c
117
uint32_t reg;
sys/dev/fdt/amlpciephy.c
129
reg = HREAD4(sc, PHY_R0);
sys/dev/fdt/amlpciephy.c
130
reg &= ~PHY_R0_PCIE_POWER_MASK;
sys/dev/fdt/amlpciephy.c
131
reg |= PHY_R0_PCIE_POWER_ON;
sys/dev/fdt/amlpciephy.c
132
HWRITE4(sc, PHY_R0, reg);
sys/dev/fdt/amlpciephy.c
146
reg = HREAD4(sc, PHY_R0);
sys/dev/fdt/amlpciephy.c
147
reg &= ~PHY_R0_MODE_MASK;
sys/dev/fdt/amlpciephy.c
148
reg |= PHY_R0_MODE_USB3;
sys/dev/fdt/amlpciephy.c
149
HWRITE4(sc, PHY_R0, reg);
sys/dev/fdt/amlpciephy.c
152
reg = amlpciephy_read(sc, 0x102d);
sys/dev/fdt/amlpciephy.c
153
reg |= (1 << 7);
sys/dev/fdt/amlpciephy.c
154
amlpciephy_write(sc, 0x102d, reg);
sys/dev/fdt/amlpciephy.c
156
reg = amlpciephy_read(sc, 0x1010);
sys/dev/fdt/amlpciephy.c
157
reg &= ~0xff0;
sys/dev/fdt/amlpciephy.c
158
reg |= 0x10;
sys/dev/fdt/amlpciephy.c
159
amlpciephy_write(sc, 0x1010, reg);
sys/dev/fdt/amlpciephy.c
162
reg = amlpciephy_read(sc, 0x1006);
sys/dev/fdt/amlpciephy.c
163
reg &= (1 << 6);
sys/dev/fdt/amlpciephy.c
164
reg |= (1 << 7);
sys/dev/fdt/amlpciephy.c
165
reg &= ~(0x7 << 8);
sys/dev/fdt/amlpciephy.c
166
reg |= (0x3 << 8);
sys/dev/fdt/amlpciephy.c
167
reg |= (1 << 11);
sys/dev/fdt/amlpciephy.c
168
amlpciephy_write(sc, 0x1006, reg);
sys/dev/fdt/amlpciephy.c
171
reg = amlpciephy_read(sc, 0x1002);
sys/dev/fdt/amlpciephy.c
172
reg &= ~0x3f80;
sys/dev/fdt/amlpciephy.c
173
reg |= (0x16 << 7);
sys/dev/fdt/amlpciephy.c
174
reg &= ~0x7f;
sys/dev/fdt/amlpciephy.c
175
reg |= (0x7f | (1 << 14));
sys/dev/fdt/amlpciephy.c
176
amlpciephy_write(sc, 0x1002, reg);
sys/dev/fdt/amlpciephy.c
179
reg = amlpciephy_read(sc, 0x30);
sys/dev/fdt/amlpciephy.c
180
reg &= ~(0xf << 4);
sys/dev/fdt/amlpciephy.c
181
reg |= (8 << 4);
sys/dev/fdt/amlpciephy.c
182
amlpciephy_write(sc, 0x30, reg);
sys/dev/fdt/amlpciephy.c
222
uint32_t reg;
sys/dev/fdt/amlpciephy.c
237
reg = HREAD4(sc, PHY_R5);
sys/dev/fdt/amlpciephy.c
248
return reg;
sys/dev/fdt/amlpciephy.c
45
#define HREAD4(sc, reg) \
sys/dev/fdt/amlpciephy.c
46
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/amlpciephy.c
47
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amlpciephy.c
48
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/amlpciephy.c
49
#define HSET4(sc, reg, bits) \
sys/dev/fdt/amlpciephy.c
50
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/amlpciephy.c
51
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/amlpciephy.c
52
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/amlpinctrl.c
390
uint32_t reg[20];
sys/dev/fdt/amlpinctrl.c
409
len > sizeof(reg) || (len / line) > nitems(addr)) {
sys/dev/fdt/amlpinctrl.c
415
OF_getpropintarray(child, "reg", reg, len);
sys/dev/fdt/amlpinctrl.c
416
for (i = 0, cell = reg; i < len / line; i++) {
sys/dev/fdt/amlpinctrl.c
519
uint32_t reg;
sys/dev/fdt/amlpinctrl.c
538
reg = bus_space_read_4(sc->sc_iot, sc->sc_mux_ioh, off);
sys/dev/fdt/amlpinctrl.c
539
reg &= ~(0xf << (((pin % 8) * 4) + bank->mux_bit));
sys/dev/fdt/amlpinctrl.c
540
reg |= (group->func << (((pin % 8) * 4) + bank->mux_bit));
sys/dev/fdt/amlpinctrl.c
541
bus_space_write_4(sc->sc_iot, sc->sc_mux_ioh, off, reg);
sys/dev/fdt/amlpinctrl.c
546
reg = bus_space_read_4(sc->sc_iot, sc->sc_pull_ioh, off);
sys/dev/fdt/amlpinctrl.c
548
reg |= (1 << (pin + bank->pull_bit));
sys/dev/fdt/amlpinctrl.c
550
reg &= ~(1 << (pin + bank->pull_bit));
sys/dev/fdt/amlpinctrl.c
551
bus_space_write_4(sc->sc_iot, sc->sc_pull_ioh, off, reg);
sys/dev/fdt/amlpinctrl.c
555
reg = bus_space_read_4(sc->sc_iot, sc->sc_pull_en_ioh, off);
sys/dev/fdt/amlpinctrl.c
557
reg |= (1 << (pin + bank->pull_en_bit));
sys/dev/fdt/amlpinctrl.c
559
reg &= ~(1 << (pin + bank->pull_en_bit));
sys/dev/fdt/amlpinctrl.c
560
bus_space_write_4(sc->sc_iot, sc->sc_pull_en_ioh, off, reg);
sys/dev/fdt/amlpinctrl.c
580
reg = bus_space_read_4(sc->sc_iot, sc->sc_ds_ioh, off);
sys/dev/fdt/amlpinctrl.c
581
reg &= ~(0x3 << (((pin % 16) * 2) + bank->ds_bit));
sys/dev/fdt/amlpinctrl.c
582
reg |= (ds << (((pin % 16) * 2) + bank->ds_bit));
sys/dev/fdt/amlpinctrl.c
583
bus_space_write_4(sc->sc_iot, sc->sc_ds_ioh, off, reg);
sys/dev/fdt/amlpinctrl.c
647
uint32_t reg;
sys/dev/fdt/amlpinctrl.c
659
reg = bus_space_read_4(sc->sc_iot, sc->sc_mux_ioh, off);
sys/dev/fdt/amlpinctrl.c
660
reg &= ~(0xf << (((pin % 8) * 4) + bank->mux_bit));
sys/dev/fdt/amlpinctrl.c
661
bus_space_write_4(sc->sc_iot, sc->sc_mux_ioh, off, reg);
sys/dev/fdt/amlpinctrl.c
669
reg = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, off);
sys/dev/fdt/amlpinctrl.c
671
reg &= ~(1 << (pin + bank->dir_bit));
sys/dev/fdt/amlpinctrl.c
673
reg |= (1 << (pin + bank->dir_bit));
sys/dev/fdt/amlpinctrl.c
674
bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, off, reg);
sys/dev/fdt/amlpinctrl.c
685
uint32_t reg;
sys/dev/fdt/amlpinctrl.c
698
reg = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, off);
sys/dev/fdt/amlpinctrl.c
699
val = (reg >> (pin + bank->in_bit)) & 1;
sys/dev/fdt/amlpinctrl.c
714
int reg;
sys/dev/fdt/amlpinctrl.c
731
reg = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, off);
sys/dev/fdt/amlpinctrl.c
733
reg |= (1 << (pin + bank->dir_bit));
sys/dev/fdt/amlpinctrl.c
735
reg &= ~(1 << (pin + bank->dir_bit));
sys/dev/fdt/amlpinctrl.c
736
bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, off, reg);
sys/dev/fdt/amlpinctrl.c
743
reg = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, off);
sys/dev/fdt/amlpinctrl.c
745
reg |= (1 << (pin + bank->out_bit));
sys/dev/fdt/amlpinctrl.c
747
reg &= ~(1 << (pin + bank->out_bit));
sys/dev/fdt/amlpinctrl.c
748
bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, off, reg);
sys/dev/fdt/amlpwm.c
50
#define HREAD4(sc, reg) \
sys/dev/fdt/amlpwm.c
51
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg) << 2))
sys/dev/fdt/amlpwm.c
52
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amlpwm.c
53
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg) << 2, (val))
sys/dev/fdt/amlpwm.c
54
#define HSET4(sc, reg, bits) \
sys/dev/fdt/amlpwm.c
55
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/amlpwm.c
56
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/amlpwm.c
57
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/amlpwrc.c
119
amlpwrc_toggle(struct regmap *rm, bus_size_t reg, uint32_t mask, int on)
sys/dev/fdt/amlpwrc.c
123
val = regmap_read_4(rm, reg << 2);
sys/dev/fdt/amlpwrc.c
128
regmap_write_4(rm, reg << 2, val);
sys/dev/fdt/amlpwrc.c
47
#define HREAD4(sc, reg) \
sys/dev/fdt/amlpwrc.c
48
(regmap_read_4((sc)->sc_rm, (reg) << 2))
sys/dev/fdt/amlpwrc.c
49
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amlpwrc.c
50
regmap_write_4((sc)->sc_rm, (reg) << 2, (val))
sys/dev/fdt/amlpwrc.c
51
#define HSET4(sc, reg, bits) \
sys/dev/fdt/amlpwrc.c
52
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/amlpwrc.c
53
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/amlpwrc.c
54
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/amlreset.c
35
#define HREAD4(sc, reg) \
sys/dev/fdt/amlreset.c
36
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/amlreset.c
37
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amlreset.c
38
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/amlreset.c
39
#define HSET4(sc, reg, bits) \
sys/dev/fdt/amlreset.c
40
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/amlreset.c
41
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/amlreset.c
42
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/amlrng.c
32
#define HREAD4(sc, reg) \
sys/dev/fdt/amlrng.c
33
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/amltemp.c
48
#define HREAD4(sc, reg) \
sys/dev/fdt/amltemp.c
49
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg) << 2))
sys/dev/fdt/amltemp.c
50
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amltemp.c
51
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg) << 2, (val))
sys/dev/fdt/amltemp.c
52
#define HSET4(sc, reg, bits) \
sys/dev/fdt/amltemp.c
53
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/amltemp.c
54
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/amltemp.c
55
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/amluart.c
119
struct fdt_reg reg;
sys/dev/fdt/amluart.c
124
if (fdt_get_reg(node, 0, ®))
sys/dev/fdt/amluart.c
127
amluartcnattach(fdt_cons_bs_tag, reg.addr);
sys/dev/fdt/amluart.c
143
uint32_t reg;
sys/dev/fdt/amluart.c
187
reg = HREAD4(sc, UART_MISC);
sys/dev/fdt/amluart.c
188
reg &= ~UART_MISC_TX_INT_CNT_MASK;
sys/dev/fdt/amluart.c
189
reg |= (32 << UART_MISC_TX_INT_CNT_SHIFT);
sys/dev/fdt/amluart.c
190
reg &= ~UART_MISC_RX_INT_CNT_MASK;
sys/dev/fdt/amluart.c
191
reg |= (1 << UART_MISC_RX_INT_CNT_SHIFT);
sys/dev/fdt/amluart.c
192
HWRITE4(sc, UART_MISC, reg);
sys/dev/fdt/amluart.c
54
#define HREAD4(sc, reg) \
sys/dev/fdt/amluart.c
55
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/amluart.c
56
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amluart.c
57
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/amluart.c
58
#define HSET4(sc, reg, bits) \
sys/dev/fdt/amluart.c
59
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/amluart.c
60
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/amluart.c
61
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/amlusbphy.c
83
#define HREAD4(sc, reg) \
sys/dev/fdt/amlusbphy.c
84
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/amlusbphy.c
85
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/amlusbphy.c
86
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/amlusbphy.c
87
#define HSET4(sc, reg, bits) \
sys/dev/fdt/amlusbphy.c
88
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/amlusbphy.c
89
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/amlusbphy.c
90
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/axppmic.c
314
uint8_t reg;
sys/dev/fdt/axppmic.c
412
axppmic_read_reg(struct axppmic_softc *sc, uint8_t reg)
sys/dev/fdt/axppmic.c
414
return sc->sc_read(sc, reg);
sys/dev/fdt/axppmic.c
418
axppmic_write_reg(struct axppmic_softc *sc, uint8_t reg, uint8_t value)
sys/dev/fdt/axppmic.c
420
sc->sc_write(sc, reg, value);
sys/dev/fdt/axppmic.c
469
axppmic_i2c_read(struct axppmic_softc *sc, uint8_t reg)
sys/dev/fdt/axppmic.c
477
error = iic_smbus_read_byte(tag, sc->sc_addr, reg, &value, flags);
sys/dev/fdt/axppmic.c
481
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/axppmic.c
489
axppmic_i2c_write(struct axppmic_softc *sc, uint8_t reg, uint8_t value)
sys/dev/fdt/axppmic.c
496
error = iic_smbus_write_byte(tag, sc->sc_addr, reg, value, flags);
sys/dev/fdt/axppmic.c
500
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/axppmic.c
545
axppmic_rsb_read(struct axppmic_softc *sc, uint8_t reg)
sys/dev/fdt/axppmic.c
547
return rsb_read_1(sc->sc_cookie, sc->sc_addr, reg);
sys/dev/fdt/axppmic.c
551
axppmic_rsb_write(struct axppmic_softc *sc, uint8_t reg, uint8_t value)
sys/dev/fdt/axppmic.c
553
rsb_write_1(sc->sc_cookie, sc->sc_addr, reg, value);
sys/dev/fdt/axppmic.c
596
uint8_t reg;
sys/dev/fdt/axppmic.c
599
reg = axppmic_read_reg(sc, AXP209_ADC_EN1);
sys/dev/fdt/axppmic.c
600
reg |= AXP209_ADC_EN1_ACIN;
sys/dev/fdt/axppmic.c
601
reg |= AXP209_ADC_EN1_VBUS;
sys/dev/fdt/axppmic.c
602
axppmic_write_reg(sc, AXP209_ADC_EN1, reg);
sys/dev/fdt/axppmic.c
779
uint32_t value, reg;
sys/dev/fdt/axppmic.c
796
reg = axppmic_read_reg(ar->ar_sc, ar->ar_vreg);
sys/dev/fdt/axppmic.c
798
(reg & ~ar->ar_vmask) | (value & ar->ar_vmask));
sys/dev/fdt/axppmic.c
806
uint8_t reg;
sys/dev/fdt/axppmic.c
808
reg = axppmic_read_reg(ar->ar_sc, ar->ar_ereg);
sys/dev/fdt/axppmic.c
809
reg &= ~ar->ar_emask;
sys/dev/fdt/axppmic.c
811
reg |= ar->ar_eval;
sys/dev/fdt/axppmic.c
813
reg |= ar->ar_dval;
sys/dev/fdt/axppmic.c
814
axppmic_write_reg(ar->ar_sc, ar->ar_ereg, reg);
sys/dev/fdt/axppmic.c
878
uint8_t reg = sc->sc_sensdata[i].reg;
sys/dev/fdt/axppmic.c
883
value = axppmic_read_reg(sc, reg);
sys/dev/fdt/axppmic.c
896
uint8_t reg = sc->sc_sensdata[i].reg;
sys/dev/fdt/axppmic.c
901
value = axppmic_read_reg(sc, reg);
sys/dev/fdt/axppmic.c
919
uint8_t reg = sc->sc_sensdata[i].reg;
sys/dev/fdt/axppmic.c
924
value = axppmic_read_reg(sc, reg);
sys/dev/fdt/axppmic.c
926
value = ((value & 0x7f) << 8) | axppmic_read_reg(sc, reg + 1);
sys/dev/fdt/axppmic.c
933
uint8_t reg = sc->sc_sensdata[i].reg;
sys/dev/fdt/axppmic.c
938
value = axppmic_read_reg(sc, reg);
sys/dev/fdt/axppmic.c
939
value = (value << 4) | axppmic_read_reg(sc, reg + 1);
sys/dev/fdt/bcm2711_pcie.c
1049
uint32_t reg[4];
sys/dev/fdt/bcm2711_pcie.c
1053
reg[0] = bus << 16 | dev << 11 | fn << 8;
sys/dev/fdt/bcm2711_pcie.c
1054
reg[1] = reg[2] = 0;
sys/dev/fdt/bcm2711_pcie.c
1055
reg[3] = ih.ih_intrpin;
sys/dev/fdt/bcm2711_pcie.c
1058
reg, sizeof(reg), level, ci, func, arg, name);
sys/dev/fdt/bcm2711_pcie.c
156
#define HREAD4(sc, reg) \
sys/dev/fdt/bcm2711_pcie.c
157
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/bcm2711_pcie.c
158
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcm2711_pcie.c
159
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcm2711_pcie.c
160
#define HSET4(sc, reg, bits) \
sys/dev/fdt/bcm2711_pcie.c
161
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/bcm2711_pcie.c
162
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/bcm2711_pcie.c
163
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/bcm2711_pcie.c
271
uint32_t reg;
sys/dev/fdt/bcm2711_pcie.c
397
reg = HREAD4(sc, sc->sc_pcie_hard_debug);
sys/dev/fdt/bcm2711_pcie.c
398
reg &= ~PCIE_HARD_DEBUG_SERDES_IDDQ;
sys/dev/fdt/bcm2711_pcie.c
399
HWRITE4(sc, sc->sc_pcie_hard_debug, reg);
sys/dev/fdt/bcm2711_pcie.c
402
reg = HREAD4(sc, PCIE_MISC_MISC_CTRL);
sys/dev/fdt/bcm2711_pcie.c
403
reg &= ~PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK;
sys/dev/fdt/bcm2711_pcie.c
405
reg |= PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128;
sys/dev/fdt/bcm2711_pcie.c
407
reg |= PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_512;
sys/dev/fdt/bcm2711_pcie.c
408
reg |= PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN;
sys/dev/fdt/bcm2711_pcie.c
409
reg |= PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE;
sys/dev/fdt/bcm2711_pcie.c
410
reg |= PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE;
sys/dev/fdt/bcm2711_pcie.c
411
reg |= PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE;
sys/dev/fdt/bcm2711_pcie.c
412
HWRITE4(sc, PCIE_MISC_MISC_CTRL, reg);
sys/dev/fdt/bcm2711_pcie.c
415
reg = HREAD4(sc, PCIE_RC_CFG_PRIV1_ID_VAL3);
sys/dev/fdt/bcm2711_pcie.c
416
reg &= ~PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_MASK;
sys/dev/fdt/bcm2711_pcie.c
417
reg |= (PCI_CLASS_BRIDGE << 16) | (PCI_SUBCLASS_BRIDGE_PCI << 8);
sys/dev/fdt/bcm2711_pcie.c
418
HWRITE4(sc, PCIE_RC_CFG_PRIV1_ID_VAL3, reg);
sys/dev/fdt/bcm2711_pcie.c
518
uint32_t reg;
sys/dev/fdt/bcm2711_pcie.c
521
reg = HREAD4(sc, PCIE_RGR1_SW_INIT_1);
sys/dev/fdt/bcm2711_pcie.c
523
reg |= PCIE_RGR1_SW_INIT_1_PERST;
sys/dev/fdt/bcm2711_pcie.c
525
reg &= ~PCIE_RGR1_SW_INIT_1_PERST;
sys/dev/fdt/bcm2711_pcie.c
526
HWRITE4(sc, PCIE_RGR1_SW_INIT_1, reg);
sys/dev/fdt/bcm2711_pcie.c
528
reg = HREAD4(sc, PCIE_MISC_PCIE_CTRL);
sys/dev/fdt/bcm2711_pcie.c
530
reg &= ~PCIE_MISC_PCIE_CTRL_PCIE_PERSTB;
sys/dev/fdt/bcm2711_pcie.c
532
reg |= PCIE_MISC_PCIE_CTRL_PCIE_PERSTB;
sys/dev/fdt/bcm2711_pcie.c
533
HWRITE4(sc, PCIE_MISC_PCIE_CTRL, reg);
sys/dev/fdt/bcm2711_pcie.c
571
uint32_t reg;
sys/dev/fdt/bcm2711_pcie.c
590
reg = HREAD4(sc, PCIE_RC_PL_PHY_CTL_15);
sys/dev/fdt/bcm2711_pcie.c
591
reg &= ~PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK;
sys/dev/fdt/bcm2711_pcie.c
592
reg |= 18 << PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_SHIFT;
sys/dev/fdt/bcm2711_pcie.c
593
HWRITE4(sc, PCIE_RC_PL_PHY_CTL_15, reg);
sys/dev/fdt/bcm2711_pcie.c
602
uint32_t reg;
sys/dev/fdt/bcm2711_pcie.c
605
reg = HREAD4(sc, sc->sc_pcie_hard_debug);
sys/dev/fdt/bcm2711_pcie.c
606
reg &= ~PCIE_HARD_DEBUG_CLKREQ_MASK;
sys/dev/fdt/bcm2711_pcie.c
610
reg |= PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE;
sys/dev/fdt/bcm2711_pcie.c
612
reg |= PCIE_HARD_DEBUG_L1SS_ENABLE;
sys/dev/fdt/bcm2711_pcie.c
615
HWRITE4(sc, sc->sc_pcie_hard_debug, reg);
sys/dev/fdt/bcm2711_pcie.c
619
reg = HREAD4(sc, PCIE_RC_CFG_PRIV1_ROOT_CAP);
sys/dev/fdt/bcm2711_pcie.c
620
reg &= ~PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK;
sys/dev/fdt/bcm2711_pcie.c
621
reg |= (1 << PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_SHIFT);
sys/dev/fdt/bcm2711_pcie.c
622
HWRITE4(sc, PCIE_RC_CFG_PRIV1_ROOT_CAP, reg);
sys/dev/fdt/bcm2711_pcie.c
629
uint32_t reg;
sys/dev/fdt/bcm2711_pcie.c
636
error = bcmpcie_mdio_read(sc, 0, MDIO_SSC_CNTL, ®);
sys/dev/fdt/bcm2711_pcie.c
639
reg |= MDIO_SSC_CNTL_OVRD_VAL | MDIO_SSC_CNTL_OVRD_EN;
sys/dev/fdt/bcm2711_pcie.c
640
error = bcmpcie_mdio_write(sc, 0, MDIO_SSC_CNTL, reg);
sys/dev/fdt/bcm2711_pcie.c
645
error = bcmpcie_mdio_read(sc, 0, MDIO_SSC_STATUS, ®);
sys/dev/fdt/bcm2711_pcie.c
649
if ((reg & MDIO_SSC_STATUS_SSC) && (reg & MDIO_SSC_STATUS_PLL_LOCK))
sys/dev/fdt/bcm2711_pcie.c
768
uint32_t reg;
sys/dev/fdt/bcm2711_pcie.c
777
reg = HREAD4(sc, PCIE_MISC_MISC_CTRL);
sys/dev/fdt/bcm2711_pcie.c
778
reg &= ~PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK;
sys/dev/fdt/bcm2711_pcie.c
779
reg |= (size << PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT);
sys/dev/fdt/bcm2711_pcie.c
780
HWRITE4(sc, PCIE_MISC_MISC_CTRL, reg);
sys/dev/fdt/bcm2711_pcie.c
787
uint32_t reg;
sys/dev/fdt/bcm2711_pcie.c
789
reg = HREAD4(sc, PCIE_MISC_PCIE_STATUS);
sys/dev/fdt/bcm2711_pcie.c
790
if ((reg & PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE) &&
sys/dev/fdt/bcm2711_pcie.c
791
(reg & PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP))
sys/dev/fdt/bcm2711_pcie.c
800
uint32_t reg;
sys/dev/fdt/bcm2711_pcie.c
804
reg = PCIE_RC_DL_MDIO_CMD_READ;
sys/dev/fdt/bcm2711_pcie.c
805
reg |= ((uint32_t)port << PCIE_RC_DL_MDIO_PORT_SHIFT);
sys/dev/fdt/bcm2711_pcie.c
806
reg |= ((uint32_t)addr << PCIE_RC_DL_MDIO_REGAD_SHIFT);
sys/dev/fdt/bcm2711_pcie.c
807
HWRITE4(sc, PCIE_RC_DL_MDIO_ADDR, reg);
sys/dev/fdt/bcm2711_pcie.c
811
reg = HREAD4(sc, PCIE_RC_DL_MDIO_RD_DATA);
sys/dev/fdt/bcm2711_pcie.c
812
if (reg & PCIE_RC_DL_MDIO_DATA_DONE)
sys/dev/fdt/bcm2711_pcie.c
821
*data = reg & PCIE_RC_DL_MDIO_DATA_MASK;
sys/dev/fdt/bcm2711_pcie.c
829
uint32_t reg;
sys/dev/fdt/bcm2711_pcie.c
833
reg = PCIE_RC_DL_MDIO_CMD_WRITE;
sys/dev/fdt/bcm2711_pcie.c
834
reg |= ((uint32_t)port << PCIE_RC_DL_MDIO_PORT_SHIFT);
sys/dev/fdt/bcm2711_pcie.c
835
reg |= ((uint32_t)addr << PCIE_RC_DL_MDIO_REGAD_SHIFT);
sys/dev/fdt/bcm2711_pcie.c
836
HWRITE4(sc, PCIE_RC_DL_MDIO_ADDR, reg);
sys/dev/fdt/bcm2711_pcie.c
841
reg = HREAD4(sc, PCIE_RC_DL_MDIO_WR_DATA);
sys/dev/fdt/bcm2711_pcie.c
842
if ((reg & PCIE_RC_DL_MDIO_DATA_DONE) == 0)
sys/dev/fdt/bcm2711_pcie.c
895
bcmpcie_conf_read(void *v, pcitag_t tag, int reg)
sys/dev/fdt/bcm2711_pcie.c
903
return HREAD4(sc, tag | reg);
sys/dev/fdt/bcm2711_pcie.c
907
return HREAD4(sc, PCIE_EXT_CFG_DATA + reg);
sys/dev/fdt/bcm2711_pcie.c
911
bcmpcie_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
sys/dev/fdt/bcm2711_pcie.c
919
HWRITE4(sc, tag | reg, data);
sys/dev/fdt/bcm2711_pcie.c
924
HWRITE4(sc, PCIE_EXT_CFG_DATA + reg, data);
sys/dev/fdt/bcm2711_rng.c
37
#define HREAD4(sc, reg) \
sys/dev/fdt/bcm2711_rng.c
38
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/bcm2711_rng.c
39
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcm2711_rng.c
40
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcm2711_tmon.c
34
#define HREAD4(sc, reg) \
sys/dev/fdt/bcm2711_tmon.c
35
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/bcm2835_bsc.c
283
uint32_t reg[1];
sys/dev/fdt/bcm2835_bsc.c
288
memset(reg, 0, sizeof(reg));
sys/dev/fdt/bcm2835_bsc.c
298
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/dev/fdt/bcm2835_bsc.c
303
ia.ia_addr = bemtoh32(®[0]);
sys/dev/fdt/bcm2835_bsc.c
64
#define HREAD4(sc, reg) \
sys/dev/fdt/bcm2835_bsc.c
65
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/bcm2835_bsc.c
66
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcm2835_bsc.c
67
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcm2835_dog.c
44
#define HREAD4(sc, reg) \
sys/dev/fdt/bcm2835_dog.c
45
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/bcm2835_dog.c
46
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcm2835_dog.c
47
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcm2835_dog.c
48
#define HSET4(sc, reg, bits) \
sys/dev/fdt/bcm2835_dog.c
49
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/bcm2835_dog.c
50
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/bcm2835_dog.c
51
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/bcm2835_gpio.c
151
int reg = (pin / 10);
sys/dev/fdt/bcm2835_gpio.c
155
val = HREAD4(sc, GPFSEL(reg));
sys/dev/fdt/bcm2835_gpio.c
157
HWRITE4(sc, GPFSEL(reg), val);
sys/dev/fdt/bcm2835_gpio.c
159
HWRITE4(sc, GPFSEL(reg), val);
sys/dev/fdt/bcm2835_gpio.c
165
int reg = (pin / 16);
sys/dev/fdt/bcm2835_gpio.c
169
val = HREAD4(sc, GPPULL(reg));
sys/dev/fdt/bcm2835_gpio.c
173
HWRITE4(sc, GPPULL(reg), val);
sys/dev/fdt/bcm2835_gpio.c
179
int reg = (pin / 32);
sys/dev/fdt/bcm2835_gpio.c
184
HWRITE4(sc, GPPUDCLK(reg), 1 << shift);
sys/dev/fdt/bcm2835_gpio.c
186
HWRITE4(sc, GPPUDCLK(reg), 0);
sys/dev/fdt/bcm2835_gpio.c
262
uint32_t reg;
sys/dev/fdt/bcm2835_gpio.c
268
reg = HREAD4(sc, GPLEV(pin / 32));
sys/dev/fdt/bcm2835_gpio.c
269
val = (reg >> (pin % 32)) & 1;
sys/dev/fdt/bcm2835_gpio.c
357
uint32_t reg;
sys/dev/fdt/bcm2835_gpio.c
367
reg = HREAD4(sc, GPFSEL(pin / 10));
sys/dev/fdt/bcm2835_gpio.c
368
func = (reg >> ((pin % 10) * 3)) & GPFSEL_MASK;
sys/dev/fdt/bcm2835_gpio.c
383
reg = HREAD4(sc, GPLEV(pin / 32));
sys/dev/fdt/bcm2835_gpio.c
384
state = (reg >> (pin % 32)) & 1;
sys/dev/fdt/bcm2835_gpio.c
60
#define HREAD4(sc, reg) \
sys/dev/fdt/bcm2835_gpio.c
61
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/bcm2835_gpio.c
62
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcm2835_gpio.c
63
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcm2835_rng.c
36
#define HREAD4(sc, reg) \
sys/dev/fdt/bcm2835_rng.c
37
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/bcm2835_rng.c
38
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcm2835_rng.c
39
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcm2835_temp.c
35
#define HREAD4(sc, reg) \
sys/dev/fdt/bcm2835_temp.c
36
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/bcm2835_temp.c
37
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcm2835_temp.c
38
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcmstbgpio.c
181
uint32_t reg;
sys/dev/fdt/bcmstbgpio.c
187
reg = HREAD4(sc, GIO_DATA(bank));
sys/dev/fdt/bcmstbgpio.c
188
val = !!(reg & (1U << pin));
sys/dev/fdt/bcmstbgpio.c
41
#define HREAD4(sc, reg) \
sys/dev/fdt/bcmstbgpio.c
42
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/bcmstbgpio.c
43
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcmstbgpio.c
44
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcmstbgpio.c
45
#define HSET4(sc, reg, bits) \
sys/dev/fdt/bcmstbgpio.c
46
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/bcmstbgpio.c
47
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/bcmstbgpio.c
48
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/bcmstbintc.c
37
#define HREAD4(sc, reg) \
sys/dev/fdt/bcmstbintc.c
38
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/bcmstbintc.c
39
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcmstbintc.c
40
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcmstbintc.c
41
#define HSET4(sc, reg, bits) \
sys/dev/fdt/bcmstbintc.c
42
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/bcmstbintc.c
43
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/bcmstbintc.c
44
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/bcmstbpinctrl.c
39
#define HREAD4(sc, reg) \
sys/dev/fdt/bcmstbpinctrl.c
40
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/bcmstbpinctrl.c
41
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcmstbpinctrl.c
42
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcmstbrescal.c
37
#define HREAD4(sc, reg) \
sys/dev/fdt/bcmstbrescal.c
38
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/bcmstbrescal.c
39
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcmstbrescal.c
40
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bcmstbrescal.c
41
#define HSET4(sc, reg, bits) \
sys/dev/fdt/bcmstbrescal.c
42
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/bcmstbrescal.c
43
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/bcmstbrescal.c
44
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/bcmstbreset.c
34
#define HREAD4(sc, reg) \
sys/dev/fdt/bcmstbreset.c
35
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/bcmstbreset.c
36
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/bcmstbreset.c
37
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/bd718x7.c
141
bd->bd_reg = sc->sc_regdata[i].reg;
sys/dev/fdt/bd718x7.c
191
bdpmic_reg_read(struct bdpmic_softc *sc, int reg)
sys/dev/fdt/bd718x7.c
193
uint8_t cmd = reg;
sys/dev/fdt/bd718x7.c
204
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/bd718x7.c
212
bdpmic_reg_write(struct bdpmic_softc *sc, int reg, uint8_t val)
sys/dev/fdt/bd718x7.c
214
uint8_t cmd = reg;
sys/dev/fdt/bd718x7.c
224
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/bd718x7.c
36
uint8_t reg, mask;
sys/dev/fdt/cdpcie.c
461
cdpcie_conf_read(void *v, pcitag_t tag, int reg)
sys/dev/fdt/cdpcie.c
469
return HREAD4(sc, reg);
sys/dev/fdt/cdpcie.c
480
return bus_space_read_4(sc->sc_iot, sc->sc_cfg_ioh, reg);
sys/dev/fdt/cdpcie.c
484
cdpcie_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
sys/dev/fdt/cdpcie.c
492
HWRITE4(sc, reg, data);
sys/dev/fdt/cdpcie.c
504
bus_space_write_4(sc->sc_iot, sc->sc_cfg_ioh, reg, data);
sys/dev/fdt/cdpcie.c
61
#define HREAD4(sc, reg) \
sys/dev/fdt/cdpcie.c
62
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/cdpcie.c
63
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/cdpcie.c
64
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/cdsdhc.c
68
#define HREAD4(sc, reg) \
sys/dev/fdt/cdsdhc.c
69
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/cdsdhc.c
70
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/cdsdhc.c
71
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/cduart.c
161
cduart_read(struct cduart_softc *sc, uint32_t reg)
sys/dev/fdt/cduart.c
163
return bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);
sys/dev/fdt/cduart.c
167
cduart_write(struct cduart_softc *sc, uint32_t reg, uint32_t val)
sys/dev/fdt/cduart.c
169
bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, val);
sys/dev/fdt/cduart.c
175
struct fdt_reg reg;
sys/dev/fdt/cduart.c
181
if (fdt_get_reg(node, 0, ®) != 0)
sys/dev/fdt/cduart.c
184
cduartcnattach(fdt_cons_bs_tag, reg.addr, B115200, TTYDEF_CFLAG);
sys/dev/fdt/com_fdt.c
52
struct fdt_reg reg;
sys/dev/fdt/com_fdt.c
65
if (fdt_get_reg(node, 0, ®))
sys/dev/fdt/com_fdt.c
88
if (bus_space_map(comconsiot, reg.addr, reg.size, 0, &comconsioh))
sys/dev/fdt/cwfg.c
401
cwfg_read(struct cwfg_softc *sc, uint8_t reg, uint8_t *val)
sys/dev/fdt/cwfg.c
403
return iic_smbus_read_byte(sc->sc_tag, sc->sc_addr, reg, val, 0);
sys/dev/fdt/cwfg.c
407
cwfg_write(struct cwfg_softc *sc, uint8_t reg, uint8_t val)
sys/dev/fdt/cwfg.c
409
return iic_smbus_write_byte(sc->sc_tag, sc->sc_addr, reg, val, 0);
sys/dev/fdt/dapmic.c
173
dapmic_reg_read(struct dapmic_softc *sc, int reg)
sys/dev/fdt/dapmic.c
175
uint8_t cmd = reg;
sys/dev/fdt/dapmic.c
186
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/dapmic.c
194
dapmic_reg_write(struct dapmic_softc *sc, int reg, uint8_t val)
sys/dev/fdt/dapmic.c
196
uint8_t cmd = reg;
sys/dev/fdt/dapmic.c
206
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/dapmic.c
310
uint8_t reg;
sys/dev/fdt/dapmic.c
316
reg = dapmic_reg_read(sc, ALARM_MO);
sys/dev/fdt/dapmic.c
317
reg &= ~ALARM_MO_TICK_TYPE;
sys/dev/fdt/dapmic.c
318
reg |= ALARM_MO_TICK_WAKE;
sys/dev/fdt/dapmic.c
319
dapmic_reg_write(sc, ALARM_MO, reg);
sys/dev/fdt/dapmic.c
322
reg = dapmic_reg_read(sc, ALARM_Y);
sys/dev/fdt/dapmic.c
323
reg |= ALARM_Y_TICK_ON;
sys/dev/fdt/dapmic.c
324
dapmic_reg_write(sc, ALARM_Y, reg);
sys/dev/fdt/dapmic.c
335
uint8_t reg;
sys/dev/fdt/dapmic.c
341
reg = dapmic_reg_read(sc, ALARM_Y);
sys/dev/fdt/dapmic.c
342
reg &= ~ALARM_Y_TICK_ON;
sys/dev/fdt/dapmic.c
343
dapmic_reg_write(sc, ALARM_Y, reg);
sys/dev/fdt/dwdog.c
41
#define HREAD4(sc, reg) \
sys/dev/fdt/dwdog.c
42
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/dwdog.c
43
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/dwdog.c
44
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/dwdog.c
45
#define HSET4(sc, reg, bits) \
sys/dev/fdt/dwdog.c
46
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/dwdog.c
47
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/dwdog.c
48
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/dwiic_fdt.c
152
uint32_t reg[1];
sys/dev/fdt/dwiic_fdt.c
157
memset(reg, 0, sizeof(reg));
sys/dev/fdt/dwiic_fdt.c
167
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/dev/fdt/dwiic_fdt.c
172
ia.ia_addr = bemtoh32(®[0]);
sys/dev/fdt/dwmmc.c
156
#define HREAD4(sc, reg) \
sys/dev/fdt/dwmmc.c
157
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/dwmmc.c
158
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/dwmmc.c
159
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/dwmmc.c
160
#define HSET4(sc, reg, bits) \
sys/dev/fdt/dwmmc.c
161
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/dwmmc.c
162
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/dwmmc.c
163
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/dwpcie.c
1001
reg = HREAD4(sc, PCIE_GLOBAL_CTRL);
sys/dev/fdt/dwpcie.c
1002
reg &= ~PCIE_GLOBAL_CTRL_DEVICE_TYPE_MASK;
sys/dev/fdt/dwpcie.c
1003
reg |= PCIE_GLOBAL_CTRL_DEVICE_TYPE_RC;
sys/dev/fdt/dwpcie.c
1004
HWRITE4(sc, PCIE_GLOBAL_CTRL, reg);
sys/dev/fdt/dwpcie.c
1008
reg = HREAD4(sc, PCIE_ARUSER);
sys/dev/fdt/dwpcie.c
1009
reg &= ~PCIE_AXUSER_DOMAIN_MASK;
sys/dev/fdt/dwpcie.c
1010
reg |= PCIE_AXUSER_DOMAIN_OUTER_SHARABLE;
sys/dev/fdt/dwpcie.c
1011
HWRITE4(sc, PCIE_ARUSER, reg);
sys/dev/fdt/dwpcie.c
1012
reg = HREAD4(sc, PCIE_AWUSER);
sys/dev/fdt/dwpcie.c
1013
reg &= ~PCIE_AXUSER_DOMAIN_MASK;
sys/dev/fdt/dwpcie.c
1014
reg |= PCIE_AXUSER_DOMAIN_OUTER_SHARABLE;
sys/dev/fdt/dwpcie.c
1015
HWRITE4(sc, PCIE_AWUSER, reg);
sys/dev/fdt/dwpcie.c
1018
reg = HREAD4(sc, PCIE_GLOBAL_CTRL);
sys/dev/fdt/dwpcie.c
1019
reg |= PCIE_GLOBAL_CTRL_APP_LTSSM_EN;
sys/dev/fdt/dwpcie.c
1020
HWRITE4(sc, PCIE_GLOBAL_CTRL, reg);
sys/dev/fdt/dwpcie.c
1045
uint32_t reg, mask;
sys/dev/fdt/dwpcie.c
1049
reg = HREAD4(sc, PCIE_GLOBAL_STATUS);
sys/dev/fdt/dwpcie.c
1050
return ((reg & mask) == mask);
sys/dev/fdt/dwpcie.c
1072
uint32_t reg;
sys/dev/fdt/dwpcie.c
1103
reg = bus_space_read_4(sc->sc_iot, sc->sc_glue_ioh, PCIE_CFG0);
sys/dev/fdt/dwpcie.c
1104
reg |= PCIE_CFG0_APP_LTSSM_EN;
sys/dev/fdt/dwpcie.c
1105
bus_space_write_4(sc->sc_iot, sc->sc_glue_ioh, PCIE_CFG0, reg);
sys/dev/fdt/dwpcie.c
1131
uint32_t reg;
sys/dev/fdt/dwpcie.c
1133
reg = bus_space_read_4(sc->sc_iot, sc->sc_glue_ioh, PCIE_STATUS12);
sys/dev/fdt/dwpcie.c
1134
if ((reg & PCIE_STATUS12_SMLH_LINK_UP) &&
sys/dev/fdt/dwpcie.c
1135
(reg & PCIE_STATUS12_RDLH_LINK_UP) &&
sys/dev/fdt/dwpcie.c
1136
(reg & PCIE_STATUS12_LTSSM_MASK) == PCIE_STATUS12_LTSSM_UP)
sys/dev/fdt/dwpcie.c
1147
uint32_t off, reg;
sys/dev/fdt/dwpcie.c
1194
reg = regmap_read_4(gpr, IOMUXC_GPR12);
sys/dev/fdt/dwpcie.c
1197
reg &= ~IMX8MQ_GPR_PCIE1_DEVICE_TYPE_MASK;
sys/dev/fdt/dwpcie.c
1198
reg |= IMX8MQ_GPR_PCIE1_DEVICE_TYPE_RC;
sys/dev/fdt/dwpcie.c
1201
reg &= ~IMX8MQ_GPR_PCIE2_DEVICE_TYPE_MASK;
sys/dev/fdt/dwpcie.c
1202
reg |= IMX8MQ_GPR_PCIE2_DEVICE_TYPE_RC;
sys/dev/fdt/dwpcie.c
1204
regmap_write_4(gpr, IOMUXC_GPR12, reg);
sys/dev/fdt/dwpcie.c
1209
reg = regmap_read_4(gpr, off);
sys/dev/fdt/dwpcie.c
1210
reg &= ~(IMX8MQ_GPR_PCIE_REF_USE_PAD |
sys/dev/fdt/dwpcie.c
1214
reg |= (IMX8MM_GPR_PCIE_AUX_EN |
sys/dev/fdt/dwpcie.c
1216
regmap_write_4(gpr, off, reg);
sys/dev/fdt/dwpcie.c
1218
reg = regmap_read_4(gpr, off);
sys/dev/fdt/dwpcie.c
1219
reg |= IMX8MM_GPR_PCIE_CMN_RST;
sys/dev/fdt/dwpcie.c
1220
regmap_write_4(gpr, off, reg);
sys/dev/fdt/dwpcie.c
1223
reg = regmap_read_4(gpr, off);
sys/dev/fdt/dwpcie.c
1224
reg &= ~(IMX8MQ_GPR_PCIE_REF_USE_PAD |
sys/dev/fdt/dwpcie.c
1228
reg |= (IMX8MM_GPR_PCIE_AUX_EN |
sys/dev/fdt/dwpcie.c
1230
regmap_write_4(gpr, off, reg);
sys/dev/fdt/dwpcie.c
1236
reg = regmap_read_4(gpr, off);
sys/dev/fdt/dwpcie.c
1237
reg |= IMX8MM_GPR_PCIE_CMN_RST;
sys/dev/fdt/dwpcie.c
1238
regmap_write_4(gpr, off, reg);
sys/dev/fdt/dwpcie.c
1248
reg = regmap_read_4(gpr, off);
sys/dev/fdt/dwpcie.c
1249
reg |= IMX8MQ_GPR_PCIE_REF_USE_PAD;
sys/dev/fdt/dwpcie.c
1250
regmap_write_4(gpr, off, reg);
sys/dev/fdt/dwpcie.c
1252
reg = regmap_read_4(gpr, off);
sys/dev/fdt/dwpcie.c
1253
reg &= ~IMX8MQ_GPR_PCIE_REF_USE_PAD;
sys/dev/fdt/dwpcie.c
1254
regmap_write_4(gpr, off, reg);
sys/dev/fdt/dwpcie.c
1293
reg = HREAD4(sc, 0x100000 + PCIE_RC_LCR);
sys/dev/fdt/dwpcie.c
1294
reg &= ~PCIE_RC_LCR_L1EL_MASK;
sys/dev/fdt/dwpcie.c
1295
reg |= PCIE_RC_LCR_L1EL_64US;
sys/dev/fdt/dwpcie.c
1296
HWRITE4(sc, 0x100000 + PCIE_RC_LCR, reg);
sys/dev/fdt/dwpcie.c
1300
reg = HREAD4(sc, PCIE_RC_LCR);
sys/dev/fdt/dwpcie.c
1301
reg &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
sys/dev/fdt/dwpcie.c
1302
reg |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
sys/dev/fdt/dwpcie.c
1303
HWRITE4(sc, PCIE_RC_LCR, reg);
sys/dev/fdt/dwpcie.c
1318
reg = HREAD4(sc, PCIE_RC_LCR);
sys/dev/fdt/dwpcie.c
1319
reg &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
sys/dev/fdt/dwpcie.c
1320
reg |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
sys/dev/fdt/dwpcie.c
1321
HWRITE4(sc, PCIE_RC_LCR, reg);
sys/dev/fdt/dwpcie.c
1323
reg = HREAD4(sc, PCIE_LINK_WIDTH_SPEED_CTRL);
sys/dev/fdt/dwpcie.c
1324
reg |= PCIE_LINK_WIDTH_SPEED_CTRL_CHANGE;
sys/dev/fdt/dwpcie.c
1325
HWRITE4(sc, PCIE_LINK_WIDTH_SPEED_CTRL, reg);
sys/dev/fdt/dwpcie.c
1499
uint32_t reg;
sys/dev/fdt/dwpcie.c
1501
reg = bus_space_read_4(sc->sc_iot, sc->sc_glue_ioh,
sys/dev/fdt/dwpcie.c
1503
if ((reg & PCIE_CLIENT_SMLH_LINK_UP) &&
sys/dev/fdt/dwpcie.c
1504
(reg & PCIE_CLIENT_RDLH_LINK_UP) &&
sys/dev/fdt/dwpcie.c
1505
(reg & PCIE_CLIENT_LTSSM_MASK) == PCIE_CLIENT_LTSSM_UP)
sys/dev/fdt/dwpcie.c
1724
dwpcie_atu_write(struct dwpcie_softc *sc, int index, off_t reg,
sys/dev/fdt/dwpcie.c
1729
IATU_OFFSET_UNROLL(index) + reg, val);
sys/dev/fdt/dwpcie.c
1738
HWRITE4(sc, IATU_OFFSET_VIEWPORT + reg, val);
sys/dev/fdt/dwpcie.c
1742
dwpcie_atu_read(struct dwpcie_softc *sc, int index, off_t reg)
sys/dev/fdt/dwpcie.c
1746
IATU_OFFSET_UNROLL(index) + reg);
sys/dev/fdt/dwpcie.c
1754
return HREAD4(sc, IATU_OFFSET_VIEWPORT + reg);
sys/dev/fdt/dwpcie.c
1767
uint32_t reg;
sys/dev/fdt/dwpcie.c
1780
reg = dwpcie_atu_read(sc, index, IATU_REGION_CTRL_2);
sys/dev/fdt/dwpcie.c
1781
if (reg & IATU_REGION_CTRL_2_REGION_EN)
sys/dev/fdt/dwpcie.c
1792
uint32_t reg;
sys/dev/fdt/dwpcie.c
1794
reg = HREAD4(sc, PCIE_PHY_DEBUG_R1);
sys/dev/fdt/dwpcie.c
1795
if ((reg & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) != 0 &&
sys/dev/fdt/dwpcie.c
1796
(reg & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING) == 0)
sys/dev/fdt/dwpcie.c
1820
uint32_t reg[5];
sys/dev/fdt/dwpcie.c
1828
reg, sizeof(reg)) != sizeof(reg))
sys/dev/fdt/dwpcie.c
1831
if (reg[0] == phys_hi)
sys/dev/fdt/dwpcie.c
1871
dwpcie_conf_read(void *v, pcitag_t tag, int reg)
sys/dev/fdt/dwpcie.c
1881
return HREAD4(sc, PCITAG_OFFSET(tag) | reg);
sys/dev/fdt/dwpcie.c
1896
ret = bus_space_read_4(sc->sc_iot, sc->sc_conf_ioh, reg);
sys/dev/fdt/dwpcie.c
190
#define HREAD4(sc, reg) \
sys/dev/fdt/dwpcie.c
1908
dwpcie_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
sys/dev/fdt/dwpcie.c
191
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/dwpcie.c
1917
HWRITE4(sc, PCITAG_OFFSET(tag) | reg, data);
sys/dev/fdt/dwpcie.c
192
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/dwpcie.c
193
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/dwpcie.c
1933
bus_space_write_4(sc->sc_iot, sc->sc_conf_ioh, reg, data);
sys/dev/fdt/dwpcie.c
194
#define HSET4(sc, reg, bits) \
sys/dev/fdt/dwpcie.c
195
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/dwpcie.c
196
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/dwpcie.c
197
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/dwpcie.c
2002
pcireg_t reg;
sys/dev/fdt/dwpcie.c
2005
if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0)
sys/dev/fdt/dwpcie.c
2008
reg = pci_conf_read(ihp->ih_pc, ihp->ih_tag, off);
sys/dev/fdt/dwpcie.c
2009
mme = ((reg & PCI_MSI_MC_MME_MASK) >> PCI_MSI_MC_MME_SHIFT);
sys/dev/fdt/dwpcie.c
2012
if (reg & PCI_MSI_MC_C64)
sys/dev/fdt/dwpcie.c
2047
if (reg & PCI_MSI_MC_C64)
sys/dev/fdt/dwpcie.c
2166
uint32_t reg[4];
sys/dev/fdt/dwpcie.c
2170
reg[0] = bus << 16 | dev << 11 | fn << 8;
sys/dev/fdt/dwpcie.c
2171
reg[1] = reg[2] = 0;
sys/dev/fdt/dwpcie.c
2172
reg[3] = ih.ih_intrpin;
sys/dev/fdt/dwpcie.c
2174
cookie = fdt_intr_establish_imap_cpu(sc->sc_node, reg,
sys/dev/fdt/dwpcie.c
2175
sizeof(reg), level, ci, func, arg, name);
sys/dev/fdt/dwpcie.c
777
pcireg_t reg;
sys/dev/fdt/dwpcie.c
782
reg = HREAD4(sc, ofs);
sys/dev/fdt/dwpcie.c
783
if (PCI_CAPLIST_CAP(reg) == capid) {
sys/dev/fdt/dwpcie.c
787
*value = reg;
sys/dev/fdt/dwpcie.c
790
ofs = PCI_CAPLIST_NEXT(reg);
sys/dev/fdt/dwpcie.c
799
uint32_t mode, width, reg;
sys/dev/fdt/dwpcie.c
826
reg = HREAD4(sc, PCIE_PORT_LINK_CTRL);
sys/dev/fdt/dwpcie.c
827
reg &= ~PCIE_PORT_LINK_CTRL_LANES_MASK;
sys/dev/fdt/dwpcie.c
828
reg |= mode;
sys/dev/fdt/dwpcie.c
829
HWRITE4(sc, PCIE_PORT_LINK_CTRL, reg);
sys/dev/fdt/dwpcie.c
831
reg = HREAD4(sc, PCIE_LINK_WIDTH_SPEED_CTRL);
sys/dev/fdt/dwpcie.c
832
reg &= ~PCIE_LINK_WIDTH_SPEED_CTRL_LANES_MASK;
sys/dev/fdt/dwpcie.c
833
reg |= width;
sys/dev/fdt/dwpcie.c
834
HWRITE4(sc, PCIE_LINK_WIDTH_SPEED_CTRL, reg);
sys/dev/fdt/dwpcie.c
836
reg = HREAD4(sc, PCIE_LINK_WIDTH_SPEED_CTRL);
sys/dev/fdt/dwpcie.c
837
reg |= PCIE_LINK_WIDTH_SPEED_CTRL_CHANGE;
sys/dev/fdt/dwpcie.c
838
HWRITE4(sc, PCIE_LINK_WIDTH_SPEED_CTRL, reg);
sys/dev/fdt/dwpcie.c
981
uint32_t reg;
sys/dev/fdt/dwpcie.c
989
reg = HREAD4(sc, PCIE_GLOBAL_CTRL);
sys/dev/fdt/dwpcie.c
990
reg &= ~PCIE_GLOBAL_CTRL_APP_LTSSM_EN;
sys/dev/fdt/dwpcie.c
991
HWRITE4(sc, PCIE_GLOBAL_CTRL, reg);
sys/dev/fdt/ehci_fdt.c
294
uint32_t *reg, val;
sys/dev/fdt/ehci_fdt.c
306
reg = malloc(len, M_TEMP, M_WAITOK);
sys/dev/fdt/ehci_fdt.c
307
OF_getpropintarray(node, "reg", reg, len);
sys/dev/fdt/ehci_fdt.c
318
size = reg[idx + 1];
sys/dev/fdt/ehci_fdt.c
319
if (bus_space_map(sc->sc.iot, reg[idx], size, 0, &ioh)) {
sys/dev/fdt/ehci_fdt.c
341
free(reg, M_TEMP, len);
sys/dev/fdt/es8316ac.c
354
escodec_read(struct escodec_softc *sc, uint8_t reg)
sys/dev/fdt/es8316ac.c
358
if (iic_smbus_read_byte(sc->sc_tag, sc->sc_addr, reg, &val, 0) != 0)
sys/dev/fdt/es8316ac.c
365
escodec_write(struct escodec_softc *sc, uint8_t reg, uint8_t val)
sys/dev/fdt/es8316ac.c
367
(void)iic_smbus_write_byte(sc->sc_tag, sc->sc_addr, reg, val, 0);
sys/dev/fdt/es8316ac.c
395
u_int reg[2];
sys/dev/fdt/es8316ac.c
421
.reg = {
sys/dev/fdt/es8316ac.c
441
.reg = {
sys/dev/fdt/es8316ac.c
458
.reg = {
sys/dev/fdt/es8316ac.c
481
.reg = {
sys/dev/fdt/es8316ac.c
505
.reg = {
sys/dev/fdt/es8316ac.c
539
val = escodec_read(sc, mix->reg[ch]);
sys/dev/fdt/es8316ac.c
549
escodec_write(sc, mix->reg[ch], val);
sys/dev/fdt/es8316ac.c
558
val = escodec_read(sc, mix->reg[0]);
sys/dev/fdt/es8316ac.c
563
escodec_write(sc, mix->reg[0], val);
sys/dev/fdt/es8316ac.c
588
val = escodec_read(sc, mix->reg[ch]);
sys/dev/fdt/es8316ac.c
601
val = escodec_read(sc, mix->reg[0]);
sys/dev/fdt/exrtc.c
41
#define HREAD4(sc, reg) \
sys/dev/fdt/exrtc.c
42
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/exrtc.c
43
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/exrtc.c
44
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/exuart.c
146
struct fdt_reg reg;
sys/dev/fdt/exuart.c
164
if (fdt_get_reg(node, 0, ®))
sys/dev/fdt/exuart.c
177
exuartcnattach(fdt_cons_bs_tag, reg.addr, B115200, TTYDEF_CFLAG);
sys/dev/fdt/fanpwr.c
252
fanpwr_read(struct fanpwr_softc *sc, int reg)
sys/dev/fdt/fanpwr.c
254
uint8_t cmd = reg;
sys/dev/fdt/fanpwr.c
266
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/fanpwr.c
274
fanpwr_write(struct fanpwr_softc *sc, int reg, uint8_t val)
sys/dev/fdt/fanpwr.c
276
uint8_t cmd = reg;
sys/dev/fdt/fanpwr.c
286
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/fusbtc.c
264
uint8_t reg;
sys/dev/fdt/fusbtc.c
322
reg = fusbtc_read_reg(sc, FUSB_CONTROL3);
sys/dev/fdt/fusbtc.c
323
reg |= FUSB_CONTROL3_AUTO_RETRY;
sys/dev/fdt/fusbtc.c
324
reg |= FUSB_CONTROL3_N_RETRIES(3);
sys/dev/fdt/fusbtc.c
325
fusbtc_write_reg(sc, FUSB_CONTROL3, reg);
sys/dev/fdt/fusbtc.c
329
reg = fusbtc_read_reg(sc, FUSB_CONTROL0);
sys/dev/fdt/fusbtc.c
330
reg &= ~FUSB_CONTROL0_INT_MASK;
sys/dev/fdt/fusbtc.c
331
fusbtc_write_reg(sc, FUSB_CONTROL0, reg);
sys/dev/fdt/fusbtc.c
384
uint8_t reg;
sys/dev/fdt/fusbtc.c
393
reg = fusbtc_read_reg(sc, FUSB_CONTROL0);
sys/dev/fdt/fusbtc.c
394
reg |= FUSB_CONTROL0_HOST_CUR0;
sys/dev/fdt/fusbtc.c
395
reg &= ~FUSB_CONTROL0_HOST_CUR1;
sys/dev/fdt/fusbtc.c
396
fusbtc_write_reg(sc, FUSB_CONTROL0, reg);
sys/dev/fdt/fusbtc.c
397
reg = fusbtc_read_reg(sc, FUSB_SWITCHES0);
sys/dev/fdt/fusbtc.c
398
reg &= ~(FUSB_SWITCHES0_VCONN_CC1 | FUSB_SWITCHES0_VCONN_CC2);
sys/dev/fdt/fusbtc.c
399
fusbtc_write_reg(sc, FUSB_SWITCHES0, reg);
sys/dev/fdt/fusbtc.c
422
uint8_t cc, reg;
sys/dev/fdt/fusbtc.c
443
reg = fusbtc_read_reg(sc, FUSB_STATUS0);
sys/dev/fdt/fusbtc.c
445
if ((reg & FUSB_STATUS0_COMP) == 0) {
sys/dev/fdt/fusbtc.c
449
reg = fusbtc_read_reg(sc, FUSB_STATUS0);
sys/dev/fdt/fusbtc.c
451
if ((reg & FUSB_STATUS0_COMP) == 0)
sys/dev/fdt/fusbtc.c
471
reg = fusbtc_read_reg(sc, FUSB_STATUS0);
sys/dev/fdt/fusbtc.c
472
reg &= FUSB_STATUS0_BC_LVL_MASK;
sys/dev/fdt/fusbtc.c
473
if (fusbtc_bclvl_to_typec(reg) == TYPEC_CC_OPEN) {
sys/dev/fdt/fusbtc.c
544
uint8_t reg;
sys/dev/fdt/fusbtc.c
549
reg = fusbtc_read_reg(sc, FUSB_STATUS0);
sys/dev/fdt/fusbtc.c
550
if ((reg & FUSB_STATUS0_COMP) == 0)
sys/dev/fdt/fusbtc.c
563
uint8_t reg;
sys/dev/fdt/fusbtc.c
565
reg = fusbtc_read_reg(sc, FUSB_SWITCHES1);
sys/dev/fdt/fusbtc.c
566
reg &= ~(FUSB_SWITCHES1_POWERROLE | FUSB_SWITCHES1_DATAROLE);
sys/dev/fdt/fusbtc.c
568
reg |= FUSB_SWITCHES1_POWERROLE;
sys/dev/fdt/fusbtc.c
570
reg |= FUSB_SWITCHES1_DATAROLE;
sys/dev/fdt/fusbtc.c
571
fusbtc_write_reg(sc, FUSB_SWITCHES1, reg);
sys/dev/fdt/fusbtc.c
587
uint8_t reg;
sys/dev/fdt/fusbtc.c
589
reg = fusbtc_read_reg(sc, FUSB_SWITCHES0);
sys/dev/fdt/fusbtc.c
590
reg &= ~(FUSB_SWITCHES0_PU_EN1 | FUSB_SWITCHES0_PU_EN2);
sys/dev/fdt/fusbtc.c
591
reg &= ~(FUSB_SWITCHES0_PD_EN1 | FUSB_SWITCHES0_PD_EN2);
sys/dev/fdt/fusbtc.c
594
reg |= FUSB_SWITCHES0_PU_EN1;
sys/dev/fdt/fusbtc.c
596
reg |= FUSB_SWITCHES0_PU_EN2;
sys/dev/fdt/fusbtc.c
600
reg |= FUSB_SWITCHES0_PD_EN1;
sys/dev/fdt/fusbtc.c
602
reg |= FUSB_SWITCHES0_PD_EN2;
sys/dev/fdt/fusbtc.c
604
fusbtc_write_reg(sc, FUSB_SWITCHES0, reg);
sys/dev/fdt/fusbtc.c
610
uint8_t reg;
sys/dev/fdt/fusbtc.c
612
reg = fusbtc_read_reg(sc, FUSB_SWITCHES0);
sys/dev/fdt/fusbtc.c
613
reg &= ~(FUSB_SWITCHES0_MEAS_CC1 | FUSB_SWITCHES0_MEAS_CC2);
sys/dev/fdt/fusbtc.c
614
reg &= ~(FUSB_SWITCHES0_VCONN_CC1 | FUSB_SWITCHES0_VCONN_CC2);
sys/dev/fdt/fusbtc.c
616
reg |= FUSB_SWITCHES0_MEAS_CC1;
sys/dev/fdt/fusbtc.c
618
reg |= FUSB_SWITCHES0_MEAS_CC2;
sys/dev/fdt/fusbtc.c
619
fusbtc_write_reg(sc, FUSB_SWITCHES0, reg);
sys/dev/fdt/fusbtc.c
621
reg = fusbtc_read_reg(sc, FUSB_SWITCHES1);
sys/dev/fdt/fusbtc.c
622
reg &= ~(FUSB_SWITCHES1_TXCC1 | FUSB_SWITCHES1_TXCC2);
sys/dev/fdt/fusbtc.c
624
reg |= FUSB_SWITCHES1_TXCC1;
sys/dev/fdt/fusbtc.c
626
reg |= FUSB_SWITCHES1_TXCC2;
sys/dev/fdt/fusbtc.c
627
fusbtc_write_reg(sc, FUSB_SWITCHES1, reg);
sys/dev/fdt/fusbtc.c
649
uint8_t reg;
sys/dev/fdt/fusbtc.c
650
reg = fusbtc_read_reg(sc, off);
sys/dev/fdt/fusbtc.c
651
reg |= val;
sys/dev/fdt/fusbtc.c
652
fusbtc_write_reg(sc, off, reg);
sys/dev/fdt/fusbtc.c
658
uint8_t reg;
sys/dev/fdt/fusbtc.c
659
reg = fusbtc_read_reg(sc, off);
sys/dev/fdt/fusbtc.c
660
reg &= ~val;
sys/dev/fdt/fusbtc.c
661
fusbtc_write_reg(sc, off, reg);
sys/dev/fdt/fusbtc.c
665
fusbtc_read_reg(struct fusbtc_softc *sc, uint8_t reg)
sys/dev/fdt/fusbtc.c
671
sc->sc_addr, ®, sizeof(reg), &val, sizeof(val), 0)) {
sys/dev/fdt/fusbtc.c
673
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/fusbtc.c
681
fusbtc_write_reg(struct fusbtc_softc *sc, uint8_t reg, uint8_t val)
sys/dev/fdt/fusbtc.c
685
sc->sc_addr, ®, sizeof(reg), &val, sizeof(val), 0)) {
sys/dev/fdt/fusbtc.c
687
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/hiclock.c
230
uint32_t reg, freq, div;
sys/dev/fdt/hiclock.c
248
reg = HREAD4(sc, 0x0b8);
sys/dev/fdt/hiclock.c
249
mux = (reg >> 6) & 0x1;
sys/dev/fdt/hiclock.c
253
reg = HREAD4(sc, 0x0b8);
sys/dev/fdt/hiclock.c
254
mux = (reg >> 4) & 0x3;
sys/dev/fdt/hiclock.c
269
reg = HREAD4(sc, 0x0b8);
sys/dev/fdt/hiclock.c
270
div = (reg >> 0) & 0xf;
sys/dev/fdt/hiclock.c
31
#define HREAD4(sc, reg) \
sys/dev/fdt/hiclock.c
313
uint32_t reg;
sys/dev/fdt/hiclock.c
317
reg = HREAD4(sc, 0x070);
sys/dev/fdt/hiclock.c
318
return reg * 1000000;
sys/dev/fdt/hiclock.c
32
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/hiclock.c
320
reg = HREAD4(sc, 0x074);
sys/dev/fdt/hiclock.c
321
return reg * 1000000;
sys/dev/fdt/hiclock.c
33
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/hiclock.c
335
uint32_t reg;
sys/dev/fdt/hiclock.c
339
reg = freq / 16000000;
sys/dev/fdt/hiclock.c
34
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/hiclock.c
340
reg |= (0xff << 16);
sys/dev/fdt/hiclock.c
341
bus_space_write_4(sc->sc_iot, sc->sc_ioh_set, 0x280, reg);
sys/dev/fdt/hiclock.c
344
reg = freq / 16000000;
sys/dev/fdt/hiclock.c
345
reg |= (0xff << 16);
sys/dev/fdt/hiclock.c
346
bus_space_write_4(sc->sc_iot, sc->sc_ioh_set, 0x270, reg);
sys/dev/fdt/if_cad.c
1603
cad_mii_oper(struct cad_softc *sc, int phy_no, int reg, uint32_t oper)
sys/dev/fdt/if_cad.c
1606
oper |= (reg << GEM_PHYMNTNC_REG_SHIFT) & GEM_PHYMNTNC_REG_MASK;
sys/dev/fdt/if_cad.c
1623
cad_mii_readreg(struct device *self, int phy_no, int reg)
sys/dev/fdt/if_cad.c
1628
cad_mii_oper(sc, phy_no, reg, GEM_PHYMNTNC_OP_READ);
sys/dev/fdt/if_cad.c
1633
if (reg == MII_EXTSR)
sys/dev/fdt/if_cad.c
1640
cad_mii_writereg(struct device *self, int phy_no, int reg, int val)
sys/dev/fdt/if_cad.c
1644
cad_mii_oper(sc, phy_no, reg, GEM_PHYMNTNC_OP_WRITE |
sys/dev/fdt/if_cad.c
311
#define HREAD4(sc, reg) \
sys/dev/fdt/if_cad.c
312
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/if_cad.c
313
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/if_cad.c
314
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/if_dwge.c
1000
if (reg & GMAC_STATUS_RI)
sys/dev/fdt/if_dwge.c
1003
if (reg & GMAC_STATUS_TI ||
sys/dev/fdt/if_dwge.c
1004
reg & GMAC_STATUS_TU)
sys/dev/fdt/if_dwge.c
1008
if (reg & GMAC_STATUS_MMC) {
sys/dev/fdt/if_dwge.c
1319
uint32_t reg;
sys/dev/fdt/if_dwge.c
1321
reg = 0;
sys/dev/fdt/if_dwge.c
1327
reg |= GMAC_MAC_FRM_FILT_PM;
sys/dev/fdt/if_dwge.c
1329
reg |= GMAC_MAC_FRM_FILT_PR;
sys/dev/fdt/if_dwge.c
1331
reg |= GMAC_MAC_FRM_FILT_HMC;
sys/dev/fdt/if_dwge.c
1351
dwge_write(sc, GMAC_MAC_FRM_FILT, reg);
sys/dev/fdt/if_dwge.c
860
dwge_mii_readreg(struct device *self, int phy, int reg)
sys/dev/fdt/if_dwge.c
868
reg << GMAC_GMII_ADDR_GR_SHIFT |
sys/dev/fdt/if_dwge.c
881
dwge_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/fdt/if_dwge.c
890
reg << GMAC_GMII_ADDR_GR_SHIFT |
sys/dev/fdt/if_dwge.c
995
uint32_t reg;
sys/dev/fdt/if_dwge.c
997
reg = dwge_read(sc, GMAC_STATUS);
sys/dev/fdt/if_dwge.c
998
dwge_write(sc, GMAC_STATUS, reg);
sys/dev/fdt/if_dwqe_fdt.c
426
uint32_t phandle, offset, reg, shift;
sys/dev/fdt/if_dwqe_fdt.c
457
reg = regmap_read_4(rm, offset);
sys/dev/fdt/if_dwqe_fdt.c
458
reg &= ~(((1U << 3) - 1) << shift);
sys/dev/fdt/if_dwqe_fdt.c
459
reg |= iface << shift;
sys/dev/fdt/if_dwqe_fdt.c
460
regmap_write_4(rm, offset, reg);
sys/dev/fdt/if_dwqe_fdt.c
565
uint32_t reg, clk_sel = 0;
sys/dev/fdt/if_dwqe_fdt.c
575
reg = RK3528_VPU_GRF_GMAC_CON5;
sys/dev/fdt/if_dwqe_fdt.c
577
reg = RK3528_VO_GRF_GMAC_CON;
sys/dev/fdt/if_dwqe_fdt.c
608
regmap_write_4(rm, reg, clk_sel);
sys/dev/fdt/if_dwxe.c
1211
uint32_t reg;
sys/dev/fdt/if_dwxe.c
1213
reg = 0;
sys/dev/fdt/if_dwxe.c
1219
reg |= DWXE_RX_FRM_FLT_RX_ALL_MULTICAST;
sys/dev/fdt/if_dwxe.c
1221
reg |= DWXE_RX_FRM_FLT_DIS_ADDR_FILTER;
sys/dev/fdt/if_dwxe.c
1223
reg |= DWXE_RX_FRM_FLT_HASH_MULTICAST;
sys/dev/fdt/if_dwxe.c
1243
dwxe_write(sc, DWXE_RX_FRM_FLT, reg);
sys/dev/fdt/if_dwxe.c
770
dwxe_mii_readreg(struct device *self, int phy, int reg)
sys/dev/fdt/if_dwxe.c
778
reg << DWXE_MDIO_CMD_PHY_REG_SHIFT |
sys/dev/fdt/if_dwxe.c
792
dwxe_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/fdt/if_dwxe.c
801
reg << DWXE_MDIO_CMD_PHY_REG_SHIFT |
sys/dev/fdt/if_dwxe.c
904
uint32_t reg;
sys/dev/fdt/if_dwxe.c
906
reg = dwxe_read(sc, DWXE_INT_STA);
sys/dev/fdt/if_dwxe.c
907
dwxe_write(sc, DWXE_INT_STA, reg);
sys/dev/fdt/if_dwxe.c
909
if (reg & DWXE_INT_STA_RX_INT)
sys/dev/fdt/if_dwxe.c
912
if (reg & DWXE_INT_STA_TX_INT ||
sys/dev/fdt/if_dwxe.c
913
reg & DWXE_INT_STA_TX_BUF_UA_INT)
sys/dev/fdt/if_fec.c
1168
fec_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/fdt/if_fec.c
1177
phy << ENET_MMFR_PA_SHIFT | reg << ENET_MMFR_RA_SHIFT);
sys/dev/fdt/if_fec.c
1187
fec_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/fdt/if_fec.c
1195
phy << ENET_MMFR_PA_SHIFT | reg << ENET_MMFR_RA_SHIFT |
sys/dev/fdt/if_fec.c
138
#define HREAD4(sc, reg) \
sys/dev/fdt/if_fec.c
139
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/if_fec.c
140
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/if_fec.c
141
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/if_fec.c
142
#define HSET4(sc, reg, bits) \
sys/dev/fdt/if_fec.c
143
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/if_fec.c
144
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/if_fec.c
145
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/if_fec.c
481
uint32_t reg;
sys/dev/fdt/if_fec.c
489
reg = fec_miibus_readreg(dev, phy, 0x0e);
sys/dev/fdt/if_fec.c
490
fec_miibus_writereg(dev, phy, 0x0e, reg & ~0x0100);
sys/dev/fdt/if_fec.c
497
reg = fec_miibus_readreg(dev, phy, 0x0e) & 0xffe3;
sys/dev/fdt/if_fec.c
498
fec_miibus_writereg(dev, phy, 0x0e, reg | 0x18);
sys/dev/fdt/if_fec.c
502
reg = fec_miibus_readreg(dev, phy, 0x1e);
sys/dev/fdt/if_fec.c
503
fec_miibus_writereg(dev, phy, 0x1e, reg | 0x0100);
sys/dev/fdt/if_mvneta.c
1244
uint32_t reg, txinprog, txfifoemp;
sys/dev/fdt/if_mvneta.c
1255
reg = MVNETA_READ(sc, MVNETA_RQC);
sys/dev/fdt/if_mvneta.c
1256
if (reg & MVNETA_RQC_ENQ_MASK)
sys/dev/fdt/if_mvneta.c
1258
MVNETA_WRITE(sc, MVNETA_RQC, MVNETA_RQC_DISQ_DISABLE(reg));
sys/dev/fdt/if_mvneta.c
1274
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/if_mvneta.c
1283
reg = MVNETA_READ(sc, MVNETA_RQC);
sys/dev/fdt/if_mvneta.c
1284
} while (reg & 0xff);
sys/dev/fdt/if_mvneta.c
1292
"0x%x\n", sc->sc_dev.dv_xname, reg);
sys/dev/fdt/if_mvneta.c
1297
reg = MVNETA_READ(sc, MVNETA_PS);
sys/dev/fdt/if_mvneta.c
1298
} while (!(reg & txfifoemp) || reg & txinprog);
sys/dev/fdt/if_mvneta.c
1304
reg = MVNETA_READ(sc, MVNETA_PS);
sys/dev/fdt/if_mvneta.c
1305
if (reg & txfifoemp && !(reg & txinprog))
sys/dev/fdt/if_mvneta.c
1310
cnt, reg);
sys/dev/fdt/if_mvneta.c
1845
bus_size_t reg;
sys/dev/fdt/if_mvneta.c
1928
if (c->reg == 0)
sys/dev/fdt/if_mvneta.c
1931
kstat_kv_u64(&kvs[i]) += (uint64_t)MVNETA_READ(sc, c->reg);
sys/dev/fdt/if_mvneta.c
237
mvneta_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/fdt/if_mvneta.c
240
return sc->sc_mdio->md_readreg(sc->sc_mdio->md_cookie, phy, reg);
sys/dev/fdt/if_mvneta.c
244
mvneta_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/fdt/if_mvneta.c
247
return sc->sc_mdio->md_writereg(sc->sc_mdio->md_cookie, phy, reg, val);
sys/dev/fdt/if_mvneta.c
289
uint32_t reg;
sys/dev/fdt/if_mvneta.c
294
reg = MVNETA_READ(sc, MVNETA_PS0);
sys/dev/fdt/if_mvneta.c
295
if (reg & MVNETA_PS0_LINKUP)
sys/dev/fdt/if_mvneta.c
301
else if (reg & MVNETA_PS0_GMIISPEED)
sys/dev/fdt/if_mvneta.c
303
else if (reg & MVNETA_PS0_MIISPEED)
sys/dev/fdt/if_mvneta.c
307
if (reg & MVNETA_PS0_FULLDX)
sys/dev/fdt/if_mvneta.c
84
#define MVNETA_READ(sc, reg) \
sys/dev/fdt/if_mvneta.c
85
bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
sys/dev/fdt/if_mvneta.c
86
#define MVNETA_WRITE(sc, reg, val) \
sys/dev/fdt/if_mvneta.c
87
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/if_mvneta.c
88
#define MVNETA_READ_FILTER(sc, reg, val, c) \
sys/dev/fdt/if_mvneta.c
89
bus_space_read_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c))
sys/dev/fdt/if_mvneta.c
90
#define MVNETA_WRITE_FILTER(sc, reg, val, c) \
sys/dev/fdt/if_mvneta.c
91
bus_space_write_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c))
sys/dev/fdt/if_mvnetareg.h
219
#define MVNETA_SMI_REGAD(reg) (((reg) & 0x1f) << 21)
sys/dev/fdt/if_mvpp.c
1326
uint32_t phy, reg;
sys/dev/fdt/if_mvpp.c
1547
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_INT_MASK_REG);
sys/dev/fdt/if_mvpp.c
1548
reg |= MVPP2_GMAC_INT_CAUSE_LINK_CHANGE;
sys/dev/fdt/if_mvpp.c
1549
mvpp2_gmac_write(sc, MVPP2_GMAC_INT_MASK_REG, reg);
sys/dev/fdt/if_mvpp.c
1553
reg = mvpp2_xlg_read(sc, MV_XLG_INTERRUPT_MASK_REG);
sys/dev/fdt/if_mvpp.c
1554
reg |= MV_XLG_INTERRUPT_LINK_CHANGE;
sys/dev/fdt/if_mvpp.c
1555
mvpp2_xlg_write(sc, MV_XLG_INTERRUPT_MASK_REG, reg);
sys/dev/fdt/if_mvpp.c
1576
uint32_t reg;
sys/dev/fdt/if_mvpp.c
1609
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_INT_MASK_REG);
sys/dev/fdt/if_mvpp.c
1610
reg |= MVPP2_GMAC_INT_CAUSE_LINK_CHANGE;
sys/dev/fdt/if_mvpp.c
1611
mvpp2_gmac_write(sc, MVPP2_GMAC_INT_MASK_REG, reg);
sys/dev/fdt/if_mvpp.c
1918
mvpp2_mii_readreg(struct device *self, int phy, int reg)
sys/dev/fdt/if_mvpp.c
1921
return sc->sc_mdio->md_readreg(sc->sc_mdio->md_cookie, phy, reg);
sys/dev/fdt/if_mvpp.c
1925
mvpp2_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/fdt/if_mvpp.c
1928
return sc->sc_mdio->md_writereg(sc->sc_mdio->md_cookie, phy, reg, val);
sys/dev/fdt/if_mvpp.c
1942
uint32_t reg;
sys/dev/fdt/if_mvpp.c
1949
reg = mvpp2_xlg_read(sc, MV_XLG_MAC_PORT_STATUS_REG);
sys/dev/fdt/if_mvpp.c
1950
if (reg & MV_XLG_MAC_PORT_STATUS_LINKSTATUS)
sys/dev/fdt/if_mvpp.c
1955
reg = mvpp2_gmac_read(sc, MVPP2_PORT_STATUS0_REG);
sys/dev/fdt/if_mvpp.c
1956
if (reg & MVPP2_PORT_STATUS0_LINKUP)
sys/dev/fdt/if_mvpp.c
1958
if (reg & MVPP2_PORT_STATUS0_FULLDX)
sys/dev/fdt/if_mvpp.c
1964
else if (reg & MVPP2_PORT_STATUS0_GMIISPEED)
sys/dev/fdt/if_mvpp.c
1966
else if (reg & MVPP2_PORT_STATUS0_MIISPEED)
sys/dev/fdt/if_mvpp.c
1978
uint32_t reg;
sys/dev/fdt/if_mvpp.c
1988
reg = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG);
sys/dev/fdt/if_mvpp.c
1989
reg &= ~MV_XLG_MAC_CTRL0_FORCELINKDOWN;
sys/dev/fdt/if_mvpp.c
1990
reg |= MV_XLG_MAC_CTRL0_FORCELINKPASS;
sys/dev/fdt/if_mvpp.c
1991
mvpp2_xlg_write(sc, MV_XLG_PORT_MAC_CTRL0_REG, reg);
sys/dev/fdt/if_mvpp.c
1993
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_AUTONEG_CONFIG);
sys/dev/fdt/if_mvpp.c
1994
reg &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
sys/dev/fdt/if_mvpp.c
1995
reg |= MVPP2_GMAC_FORCE_LINK_PASS;
sys/dev/fdt/if_mvpp.c
1996
reg &= ~MVPP2_GMAC_CONFIG_MII_SPEED;
sys/dev/fdt/if_mvpp.c
1997
reg &= ~MVPP2_GMAC_CONFIG_GMII_SPEED;
sys/dev/fdt/if_mvpp.c
1998
reg &= ~MVPP2_GMAC_CONFIG_FULL_DUPLEX;
sys/dev/fdt/if_mvpp.c
2006
reg |= MVPP2_GMAC_CONFIG_GMII_SPEED;
sys/dev/fdt/if_mvpp.c
2008
reg |= MVPP2_GMAC_CONFIG_MII_SPEED;
sys/dev/fdt/if_mvpp.c
2010
reg |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
sys/dev/fdt/if_mvpp.c
2011
mvpp2_gmac_write(sc, MVPP2_GMAC_AUTONEG_CONFIG, reg);
sys/dev/fdt/if_mvpp.c
2016
reg = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG);
sys/dev/fdt/if_mvpp.c
2017
reg &= ~MV_XLG_MAC_CTRL0_FORCELINKPASS;
sys/dev/fdt/if_mvpp.c
2018
reg |= MV_XLG_MAC_CTRL0_FORCELINKDOWN;
sys/dev/fdt/if_mvpp.c
2019
mvpp2_xlg_write(sc, MV_XLG_PORT_MAC_CTRL0_REG, reg);
sys/dev/fdt/if_mvpp.c
2021
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_AUTONEG_CONFIG);
sys/dev/fdt/if_mvpp.c
2022
reg &= ~MVPP2_GMAC_FORCE_LINK_PASS;
sys/dev/fdt/if_mvpp.c
2023
reg |= MVPP2_GMAC_FORCE_LINK_DOWN;
sys/dev/fdt/if_mvpp.c
2024
mvpp2_gmac_write(sc, MVPP2_GMAC_AUTONEG_CONFIG, reg);
sys/dev/fdt/if_mvpp.c
2046
uint32_t reg;
sys/dev/fdt/if_mvpp.c
2051
reg = mvpp2_xlg_read(sc, MV_XLG_INTERRUPT_CAUSE_REG);
sys/dev/fdt/if_mvpp.c
2052
if (reg & MV_XLG_INTERRUPT_LINK_CHANGE)
sys/dev/fdt/if_mvpp.c
2061
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_INT_CAUSE_REG);
sys/dev/fdt/if_mvpp.c
2062
if (reg & MVPP2_GMAC_INT_CAUSE_LINK_CHANGE)
sys/dev/fdt/if_mvpp.c
2076
uint32_t reg;
sys/dev/fdt/if_mvpp.c
2078
reg = mvpp2_read(sc->sc, MVPP2_ISR_RX_TX_CAUSE_REG(sc->sc_id));
sys/dev/fdt/if_mvpp.c
2079
if (reg & MVPP2_CAUSE_MISC_SUM_MASK) {
sys/dev/fdt/if_mvpp.c
2082
reg & ~MVPP2_CAUSE_MISC_SUM_MASK);
sys/dev/fdt/if_mvpp.c
2084
if (reg & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK)
sys/dev/fdt/if_mvpp.c
2086
(reg & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK) >>
sys/dev/fdt/if_mvpp.c
2089
if (reg & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK)
sys/dev/fdt/if_mvpp.c
2091
reg & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK);
sys/dev/fdt/if_mvpp.c
2351
uint32_t reg;
sys/dev/fdt/if_mvpp.c
2383
reg = mvpp2_read(sc->sc, MVPP2_TXQ_PENDING_REG);
sys/dev/fdt/if_mvpp.c
2384
reg &= ~MVPP2_TXQ_PENDING_MASK;
sys/dev/fdt/if_mvpp.c
2385
mvpp2_write(sc->sc, MVPP2_TXQ_PENDING_REG, reg);
sys/dev/fdt/if_mvpp.c
2399
reg = mvpp2_read(sc->sc, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
sys/dev/fdt/if_mvpp.c
2400
reg &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
sys/dev/fdt/if_mvpp.c
2401
reg |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
sys/dev/fdt/if_mvpp.c
2402
reg |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
sys/dev/fdt/if_mvpp.c
2403
mvpp2_write(sc->sc, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), reg);
sys/dev/fdt/if_mvpp.c
2454
uint32_t reg;
sys/dev/fdt/if_mvpp.c
2459
reg = mvpp2_mpcs_read(sc, MVPP22_MPCS_CLOCK_RESET);
sys/dev/fdt/if_mvpp.c
2460
reg |= MVPP22_MPCS_CLK_DIV_PHASE_SET;
sys/dev/fdt/if_mvpp.c
2461
reg &= ~MVPP22_MPCS_TX_SD_CLK_RESET;
sys/dev/fdt/if_mvpp.c
2462
reg &= ~MVPP22_MPCS_RX_SD_CLK_RESET;
sys/dev/fdt/if_mvpp.c
2463
reg &= ~MVPP22_MPCS_MAC_CLK_RESET;
sys/dev/fdt/if_mvpp.c
2464
mvpp2_mpcs_write(sc, MVPP22_MPCS_CLOCK_RESET, reg);
sys/dev/fdt/if_mvpp.c
2465
reg = mvpp2_xpcs_read(sc, MVPP22_XPCS_GLOBAL_CFG_0_REG);
sys/dev/fdt/if_mvpp.c
2466
reg &= ~MVPP22_XPCS_PCSRESET;
sys/dev/fdt/if_mvpp.c
2467
mvpp2_xpcs_write(sc, MVPP22_XPCS_GLOBAL_CFG_0_REG, reg);
sys/dev/fdt/if_mvpp.c
2473
uint32_t reg;
sys/dev/fdt/if_mvpp.c
2479
reg = mvpp2_mpcs_read(sc, MVPP22_MPCS_CLOCK_RESET);
sys/dev/fdt/if_mvpp.c
2480
reg &= ~MVPP22_MPCS_CLK_DIV_PHASE_SET;
sys/dev/fdt/if_mvpp.c
2481
reg |= MVPP22_MPCS_TX_SD_CLK_RESET;
sys/dev/fdt/if_mvpp.c
2482
reg |= MVPP22_MPCS_RX_SD_CLK_RESET;
sys/dev/fdt/if_mvpp.c
2483
reg |= MVPP22_MPCS_MAC_CLK_RESET;
sys/dev/fdt/if_mvpp.c
2484
mvpp2_mpcs_write(sc, MVPP22_MPCS_CLOCK_RESET, reg);
sys/dev/fdt/if_mvpp.c
2486
reg = mvpp2_xpcs_read(sc, MVPP22_XPCS_GLOBAL_CFG_0_REG);
sys/dev/fdt/if_mvpp.c
2487
reg |= MVPP22_XPCS_PCSRESET;
sys/dev/fdt/if_mvpp.c
2488
mvpp2_xpcs_write(sc, MVPP22_XPCS_GLOBAL_CFG_0_REG, reg);
sys/dev/fdt/if_mvpp.c
2495
uint32_t reg;
sys/dev/fdt/if_mvpp.c
2497
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_AUTONEG_CONFIG);
sys/dev/fdt/if_mvpp.c
2498
reg &= ~MVPP2_GMAC_FORCE_LINK_PASS;
sys/dev/fdt/if_mvpp.c
2499
reg |= MVPP2_GMAC_FORCE_LINK_DOWN;
sys/dev/fdt/if_mvpp.c
2500
mvpp2_gmac_write(sc, MVPP2_GMAC_AUTONEG_CONFIG, reg);
sys/dev/fdt/if_mvpp.c
2502
reg = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG);
sys/dev/fdt/if_mvpp.c
2503
reg &= ~MV_XLG_MAC_CTRL0_FORCELINKPASS;
sys/dev/fdt/if_mvpp.c
2504
reg |= MV_XLG_MAC_CTRL0_FORCELINKDOWN;
sys/dev/fdt/if_mvpp.c
2505
mvpp2_xlg_write(sc, MV_XLG_PORT_MAC_CTRL0_REG, reg);
sys/dev/fdt/if_mvpp.c
2528
reg = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL3_REG);
sys/dev/fdt/if_mvpp.c
2529
reg &= ~MV_XLG_MAC_CTRL3_MACMODESELECT_MASK;
sys/dev/fdt/if_mvpp.c
2532
reg |= MV_XLG_MAC_CTRL3_MACMODESELECT_10G;
sys/dev/fdt/if_mvpp.c
2534
reg |= MV_XLG_MAC_CTRL3_MACMODESELECT_GMAC;
sys/dev/fdt/if_mvpp.c
2535
mvpp2_xlg_write(sc, MV_XLG_PORT_MAC_CTRL3_REG, reg);
sys/dev/fdt/if_mvpp.c
2540
reg = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL1_REG);
sys/dev/fdt/if_mvpp.c
2541
reg &= ~MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_MASK;
sys/dev/fdt/if_mvpp.c
2542
reg |= ((MCLBYTES - MVPP2_MH_SIZE) / 2) <<
sys/dev/fdt/if_mvpp.c
2544
mvpp2_xlg_write(sc, MV_XLG_PORT_MAC_CTRL1_REG, reg);
sys/dev/fdt/if_mvpp.c
2546
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_CTRL_0_REG);
sys/dev/fdt/if_mvpp.c
2547
reg &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
sys/dev/fdt/if_mvpp.c
2548
reg |= ((MCLBYTES - MVPP2_MH_SIZE) / 2) <<
sys/dev/fdt/if_mvpp.c
2550
mvpp2_gmac_write(sc, MVPP2_GMAC_CTRL_0_REG, reg);
sys/dev/fdt/if_mvpp.c
2568
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_AUTONEG_CONFIG);
sys/dev/fdt/if_mvpp.c
2569
reg &= ~MVPP2_GMAC_FORCE_LINK_PASS;
sys/dev/fdt/if_mvpp.c
2570
reg &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
sys/dev/fdt/if_mvpp.c
2571
mvpp2_gmac_write(sc, MVPP2_GMAC_AUTONEG_CONFIG, reg);
sys/dev/fdt/if_mvpp.c
2573
reg = mvpp2_xlg_read(sc, MV_XLG_PORT_MAC_CTRL0_REG);
sys/dev/fdt/if_mvpp.c
2574
reg &= ~MV_XLG_MAC_CTRL0_FORCELINKPASS;
sys/dev/fdt/if_mvpp.c
2575
reg &= ~MV_XLG_MAC_CTRL0_FORCELINKDOWN;
sys/dev/fdt/if_mvpp.c
2576
mvpp2_xlg_write(sc, MV_XLG_PORT_MAC_CTRL0_REG, reg);
sys/dev/fdt/if_mvpp.c
2756
uint32_t reg;
sys/dev/fdt/if_mvpp.c
2767
reg = regmap_read_4(sc->sc->sc_rm, GENCONF_PORT_CTRL0);
sys/dev/fdt/if_mvpp.c
2768
reg |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;
sys/dev/fdt/if_mvpp.c
2769
regmap_write_4(sc->sc->sc_rm, GENCONF_PORT_CTRL0, reg);
sys/dev/fdt/if_mvpp.c
2770
reg = regmap_read_4(sc->sc->sc_rm, GENCONF_CTRL0);
sys/dev/fdt/if_mvpp.c
2772
reg |= GENCONF_CTRL0_PORT0_RGMII |
sys/dev/fdt/if_mvpp.c
2775
reg |= GENCONF_CTRL0_PORT1_RGMII_MII;
sys/dev/fdt/if_mvpp.c
2776
regmap_write_4(sc->sc->sc_rm, GENCONF_CTRL0, reg);
sys/dev/fdt/if_mvpp.c
2780
reg = regmap_read_4(sc->sc->sc_rm, GENCONF_PORT_CTRL0);
sys/dev/fdt/if_mvpp.c
2781
reg |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |
sys/dev/fdt/if_mvpp.c
2783
regmap_write_4(sc->sc->sc_rm, GENCONF_PORT_CTRL0, reg);
sys/dev/fdt/if_mvpp.c
2785
reg = regmap_read_4(sc->sc->sc_rm, GENCONF_CTRL0);
sys/dev/fdt/if_mvpp.c
2787
reg &= ~GENCONF_CTRL0_PORT0_RGMII;
sys/dev/fdt/if_mvpp.c
2789
reg &= ~GENCONF_CTRL0_PORT1_RGMII_MII;
sys/dev/fdt/if_mvpp.c
2790
regmap_write_4(sc->sc->sc_rm, GENCONF_CTRL0, reg);
sys/dev/fdt/if_mvpp.c
2795
reg = mvpp2_xpcs_read(sc, MVPP22_XPCS_GLOBAL_CFG_0_REG);
sys/dev/fdt/if_mvpp.c
2796
reg &= ~MVPP22_XPCS_PCSMODE_MASK;
sys/dev/fdt/if_mvpp.c
2797
reg &= ~MVPP22_XPCS_LANEACTIVE_MASK;
sys/dev/fdt/if_mvpp.c
2798
reg |= 2 << MVPP22_XPCS_LANEACTIVE_OFFS;
sys/dev/fdt/if_mvpp.c
2799
mvpp2_xpcs_write(sc, MVPP22_XPCS_GLOBAL_CFG_0_REG, reg);
sys/dev/fdt/if_mvpp.c
2800
reg = mvpp2_mpcs_read(sc, MVPP22_MPCS40G_COMMON_CONTROL);
sys/dev/fdt/if_mvpp.c
2801
reg &= ~MVPP22_MPCS_FORWARD_ERROR_CORRECTION_MASK;
sys/dev/fdt/if_mvpp.c
2802
mvpp2_mpcs_write(sc, MVPP22_MPCS40G_COMMON_CONTROL, reg);
sys/dev/fdt/if_mvpp.c
2803
reg = mvpp2_mpcs_read(sc, MVPP22_MPCS_CLOCK_RESET);
sys/dev/fdt/if_mvpp.c
2804
reg &= ~MVPP22_MPCS_CLK_DIVISION_RATIO_MASK;
sys/dev/fdt/if_mvpp.c
2805
reg |= MVPP22_MPCS_CLK_DIVISION_RATIO_DEFAULT;
sys/dev/fdt/if_mvpp.c
2806
mvpp2_mpcs_write(sc, MVPP22_MPCS_CLOCK_RESET, reg);
sys/dev/fdt/if_mvpp.c
2810
reg = regmap_read_4(sc->sc->sc_rm, GENCONF_PORT_CTRL1);
sys/dev/fdt/if_mvpp.c
2811
reg |= GENCONF_PORT_CTRL1_RESET(sc->sc_gop_id) |
sys/dev/fdt/if_mvpp.c
2813
regmap_write_4(sc->sc->sc_rm, GENCONF_PORT_CTRL1, reg);
sys/dev/fdt/if_mvpp.c
2815
reg = regmap_read_4(sc->sc->sc_rm, GENCONF_PORT_CTRL0);
sys/dev/fdt/if_mvpp.c
2816
reg |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;
sys/dev/fdt/if_mvpp.c
2817
regmap_write_4(sc->sc->sc_rm, GENCONF_PORT_CTRL0, reg);
sys/dev/fdt/if_mvpp.c
2819
reg = regmap_read_4(sc->sc->sc_rm, GENCONF_SOFT_RESET1);
sys/dev/fdt/if_mvpp.c
2820
reg |= GENCONF_SOFT_RESET1_GOP;
sys/dev/fdt/if_mvpp.c
2821
regmap_write_4(sc->sc->sc_rm, GENCONF_SOFT_RESET1, reg);
sys/dev/fdt/if_mvpp.c
2827
uint32_t reg;
sys/dev/fdt/if_mvpp.c
2830
reg = mvpp2_xlg_read(sc, MV_XLG_EXTERNAL_INTERRUPT_MASK_REG);
sys/dev/fdt/if_mvpp.c
2831
reg &= ~MV_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_XLG;
sys/dev/fdt/if_mvpp.c
2832
reg &= ~MV_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_GIG;
sys/dev/fdt/if_mvpp.c
2833
mvpp2_xlg_write(sc, MV_XLG_EXTERNAL_INTERRUPT_MASK_REG, reg);
sys/dev/fdt/if_mvpp.c
2836
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_INT_SUM_MASK_REG);
sys/dev/fdt/if_mvpp.c
2837
reg &= ~MVPP2_GMAC_INT_SUM_CAUSE_LINK_CHANGE;
sys/dev/fdt/if_mvpp.c
2838
mvpp2_gmac_write(sc, MVPP2_GMAC_INT_SUM_MASK_REG, reg);
sys/dev/fdt/if_mvpp.c
2844
uint32_t reg;
sys/dev/fdt/if_mvpp.c
2846
reg = mvpp2_gmac_read(sc, MVPP2_GMAC_INT_SUM_MASK_REG);
sys/dev/fdt/if_mvpp.c
2847
reg |= MVPP2_GMAC_INT_SUM_CAUSE_LINK_CHANGE;
sys/dev/fdt/if_mvpp.c
2848
mvpp2_gmac_write(sc, MVPP2_GMAC_INT_SUM_MASK_REG, reg);
sys/dev/fdt/if_mvpp.c
2851
reg = mvpp2_xlg_read(sc, MV_XLG_EXTERNAL_INTERRUPT_MASK_REG);
sys/dev/fdt/if_mvpp.c
2854
reg |= MV_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_XLG;
sys/dev/fdt/if_mvpp.c
2856
reg |= MV_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_GIG;
sys/dev/fdt/if_mvpp.c
2857
mvpp2_xlg_write(sc, MV_XLG_EXTERNAL_INTERRUPT_MASK_REG, reg);
sys/dev/fdt/if_mvpp.c
2865
uint32_t reg;
sys/dev/fdt/if_mvpp.c
2883
reg = mvpp2_read(sc->sc, MVPP2_TX_PORT_FLUSH_REG);
sys/dev/fdt/if_mvpp.c
2884
reg |= MVPP2_TX_PORT_FLUSH_MASK(sc->sc_id);
sys/dev/fdt/if_mvpp.c
2885
mvpp2_write(sc->sc, MVPP2_TX_PORT_FLUSH_REG, reg);
sys/dev/fdt/if_mvpp.c
2890
reg &= ~MVPP2_TX_PORT_FLUSH_MASK(sc->sc_id);
sys/dev/fdt/if_mvpp.c
2891
mvpp2_write(sc->sc, MVPP2_TX_PORT_FLUSH_REG, reg);
sys/dev/fdt/if_mvpp.c
2908
uint32_t reg;
sys/dev/fdt/if_mvpp.c
2911
reg = mvpp2_read(sc->sc, MVPP2_TXQ_PREF_BUF_REG);
sys/dev/fdt/if_mvpp.c
2912
reg |= MVPP2_TXQ_DRAIN_EN_MASK;
sys/dev/fdt/if_mvpp.c
2913
mvpp2_write(sc->sc, MVPP2_TXQ_PREF_BUF_REG, reg);
sys/dev/fdt/if_mvpp.c
2933
reg &= ~MVPP2_TXQ_DRAIN_EN_MASK;
sys/dev/fdt/if_mvpp.c
2934
mvpp2_write(sc->sc, MVPP2_TXQ_PREF_BUF_REG, reg);
sys/dev/fdt/if_mvpp.c
529
uint32_t reg;
sys/dev/fdt/if_mvpp.c
533
reg = (MVPP22_AXI_CODE_CACHE_WR_CACHE << MVPP22_AXI_ATTR_CACHE_OFFS) |
sys/dev/fdt/if_mvpp.c
535
mvpp2_write(sc, MVPP22_AXI_BM_WR_ATTR_REG, reg);
sys/dev/fdt/if_mvpp.c
536
mvpp2_write(sc, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, reg);
sys/dev/fdt/if_mvpp.c
537
mvpp2_write(sc, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, reg);
sys/dev/fdt/if_mvpp.c
538
mvpp2_write(sc, MVPP22_AXI_RX_DATA_WR_ATTR_REG, reg);
sys/dev/fdt/if_mvpp.c
540
reg = (MVPP22_AXI_CODE_CACHE_RD_CACHE << MVPP22_AXI_ATTR_CACHE_OFFS) |
sys/dev/fdt/if_mvpp.c
542
mvpp2_write(sc, MVPP22_AXI_BM_RD_ATTR_REG, reg);
sys/dev/fdt/if_mvpp.c
543
mvpp2_write(sc, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, reg);
sys/dev/fdt/if_mvpp.c
544
mvpp2_write(sc, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, reg);
sys/dev/fdt/if_mvpp.c
545
mvpp2_write(sc, MVPP22_AXI_TX_DATA_RD_ATTR_REG, reg);
sys/dev/fdt/if_mvpp.c
547
reg = (MVPP22_AXI_CODE_CACHE_NON_CACHE << MVPP22_AXI_CODE_CACHE_OFFS) |
sys/dev/fdt/if_mvpp.c
549
mvpp2_write(sc, MVPP22_AXI_RD_NORMAL_CODE_REG, reg);
sys/dev/fdt/if_mvpp.c
550
mvpp2_write(sc, MVPP22_AXI_WR_NORMAL_CODE_REG, reg);
sys/dev/fdt/if_mvpp.c
552
reg = (MVPP22_AXI_CODE_CACHE_RD_CACHE << MVPP22_AXI_CODE_CACHE_OFFS) |
sys/dev/fdt/if_mvpp.c
554
mvpp2_write(sc, MVPP22_AXI_RD_SNOOP_CODE_REG, reg);
sys/dev/fdt/if_mvpp.c
556
reg = (MVPP22_AXI_CODE_CACHE_WR_CACHE << MVPP22_AXI_CODE_CACHE_OFFS) |
sys/dev/fdt/if_mvpp.c
558
mvpp2_write(sc, MVPP22_AXI_WR_SNOOP_CODE_REG, reg);
sys/dev/fdt/if_mvpp.c
769
uint32_t reg;
sys/dev/fdt/if_mvpp.c
771
reg = mvpp2_read(sc, MVPP2_PRS_INIT_LOOKUP_REG);
sys/dev/fdt/if_mvpp.c
772
reg &= ~MVPP2_PRS_PORT_LU_MASK(port);
sys/dev/fdt/if_mvpp.c
773
reg |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
sys/dev/fdt/if_mvpp.c
774
mvpp2_write(sc, MVPP2_PRS_INIT_LOOKUP_REG, reg);
sys/dev/fdt/if_mvpp.c
776
reg = mvpp2_read(sc, MVPP2_PRS_MAX_LOOP_REG(port));
sys/dev/fdt/if_mvpp.c
777
reg &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
sys/dev/fdt/if_mvpp.c
778
reg |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
sys/dev/fdt/if_mvpp.c
779
mvpp2_write(sc, MVPP2_PRS_MAX_LOOP_REG(port), reg);
sys/dev/fdt/if_mvpp.c
781
reg = mvpp2_read(sc, MVPP2_PRS_INIT_OFFS_REG(port));
sys/dev/fdt/if_mvpp.c
782
reg &= ~MVPP2_PRS_INIT_OFF_MASK(port);
sys/dev/fdt/if_mvpp.c
783
reg |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
sys/dev/fdt/if_mvpp.c
784
mvpp2_write(sc, MVPP2_PRS_INIT_OFFS_REG(port), reg);
sys/dev/fdt/iicmux.c
249
uint32_t reg[1];
sys/dev/fdt/iicmux.c
254
memset(reg, 0, sizeof(reg));
sys/dev/fdt/iicmux.c
261
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/dev/fdt/iicmux.c
266
ia.ia_addr = bemtoh32(®[0]);
sys/dev/fdt/imxanatop.c
233
uint32_t bit_val, old_bit_val, reg;
sys/dev/fdt/imxanatop.c
240
reg = HREAD4(ir->ir_sc, ir->ir_reg_offset);
sys/dev/fdt/imxanatop.c
241
old_bit_val = (reg >> ir->ir_vol_bit_shift);
sys/dev/fdt/imxanatop.c
243
reg &= ~((1 << ir->ir_vol_bit_width) - 1) << ir->ir_vol_bit_shift;
sys/dev/fdt/imxanatop.c
244
reg |= (bit_val << ir->ir_vol_bit_shift);
sys/dev/fdt/imxanatop.c
245
HWRITE4(ir->ir_sc, ir->ir_reg_offset, reg);
sys/dev/fdt/imxanatop.c
249
reg = HREAD4(ir->ir_sc, ir->ir_delay_reg_offset);
sys/dev/fdt/imxanatop.c
250
reg >>= ir->ir_delay_bit_shift;
sys/dev/fdt/imxanatop.c
251
reg &= ((1 << ir->ir_delay_bit_width) - 1);
sys/dev/fdt/imxanatop.c
252
usecs = ((reg + 1) * steps * 64 * 1000000) / 24000000;
sys/dev/fdt/imxanatop.c
91
#define HREAD4(sc, reg) \
sys/dev/fdt/imxanatop.c
92
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/imxanatop.c
93
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/imxanatop.c
94
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/imxanatop.c
95
#define HSET4(sc, reg, bits) \
sys/dev/fdt/imxanatop.c
96
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/imxanatop.c
97
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/imxanatop.c
98
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/imxccm.c
1008
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
1011
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1037
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
1040
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1058
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
1061
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1085
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
1088
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1106
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
1109
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1129
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
1132
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1219
uint32_t mux, reg;
sys/dev/fdt/imxccm.c
1240
reg = regmap_read_4(sc->sc_anatop, pll0);
sys/dev/fdt/imxccm.c
1241
mux = (reg >> CCM_FRAC_PLL_REFCLK_SEL_SHIFT) &
sys/dev/fdt/imxccm.c
1266
reg = regmap_read_4(sc->sc_anatop, pll1);
sys/dev/fdt/imxccm.c
1267
reg &= ~(CCM_FRAC_PLL_FRAC_DIV_CTL_MASK << CCM_FRAC_PLL_FRAC_DIV_CTL_SHIFT);
sys/dev/fdt/imxccm.c
1268
reg |= divff << CCM_FRAC_PLL_FRAC_DIV_CTL_SHIFT;
sys/dev/fdt/imxccm.c
1269
reg &= ~(CCM_FRAC_PLL_INT_DIV_CTL_MASK << CCM_FRAC_PLL_INT_DIV_CTL_SHIFT);
sys/dev/fdt/imxccm.c
1270
reg |= (divfi - 1) << CCM_FRAC_PLL_INT_DIV_CTL_SHIFT;
sys/dev/fdt/imxccm.c
1271
regmap_write_4(sc->sc_anatop, pll1, reg);
sys/dev/fdt/imxccm.c
1273
reg = regmap_read_4(sc->sc_anatop, pll0);
sys/dev/fdt/imxccm.c
1274
reg &= ~CCM_FRAC_PLL_OUTPUT_DIV_VAL_MASK;
sys/dev/fdt/imxccm.c
1275
reg &= ~(CCM_FRAC_PLL_REFCLK_DIV_VAL_MASK << CCM_FRAC_PLL_REFCLK_DIV_VAL_SHIFT);
sys/dev/fdt/imxccm.c
1276
reg |= (divr - 1) << CCM_FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
sys/dev/fdt/imxccm.c
1277
regmap_write_4(sc->sc_anatop, pll0, reg);
sys/dev/fdt/imxccm.c
1279
reg = regmap_read_4(sc->sc_anatop, pll0);
sys/dev/fdt/imxccm.c
1280
reg |= CCM_FRAC_PLL_NEWDIV_VAL;
sys/dev/fdt/imxccm.c
1281
regmap_write_4(sc->sc_anatop, pll0, reg);
sys/dev/fdt/imxccm.c
1284
reg = regmap_read_4(sc->sc_anatop, pll0);
sys/dev/fdt/imxccm.c
1285
if (reg & CCM_FRAC_PLL_BYPASS)
sys/dev/fdt/imxccm.c
1287
if (reg & CCM_FRAC_PLL_POWERDOWN)
sys/dev/fdt/imxccm.c
1289
if (reg & CCM_FRAC_PLL_NEWDIV_ACK)
sys/dev/fdt/imxccm.c
1296
reg = regmap_read_4(sc->sc_anatop, pll0);
sys/dev/fdt/imxccm.c
1297
reg &= ~CCM_FRAC_PLL_NEWDIV_VAL;
sys/dev/fdt/imxccm.c
1298
regmap_write_4(sc->sc_anatop, pll0, reg);
sys/dev/fdt/imxccm.c
1308
uint32_t reg;
sys/dev/fdt/imxccm.c
1322
reg = HREAD4(sc, sc->sc_divs[idx].reg);
sys/dev/fdt/imxccm.c
1323
reg &= ~(sc->sc_divs[idx].mask << sc->sc_divs[idx].shift);
sys/dev/fdt/imxccm.c
1324
reg |= (div << sc->sc_divs[idx].shift);
sys/dev/fdt/imxccm.c
1325
HWRITE4(sc, sc->sc_divs[idx].reg, reg);
sys/dev/fdt/imxccm.c
1326
HCLR4(sc, sc->sc_predivs[idx].reg,
sys/dev/fdt/imxccm.c
1344
uint16_t reg;
sys/dev/fdt/imxccm.c
1475
if (idx >= sc->sc_ngates || sc->sc_gates[idx].reg == 0) {
sys/dev/fdt/imxccm.c
1476
if ((idx < sc->sc_ndivs && sc->sc_divs[idx].reg != 0) ||
sys/dev/fdt/imxccm.c
1477
(idx < sc->sc_nmuxs && sc->sc_muxs[idx].reg != 0))
sys/dev/fdt/imxccm.c
1483
reg = sc->sc_gates[idx].reg;
sys/dev/fdt/imxccm.c
1487
HSET4(sc, reg, 0x3 << (2 * pos));
sys/dev/fdt/imxccm.c
1489
HCLR4(sc, reg, 0x3 << (2 * pos));
sys/dev/fdt/imxccm.c
1497
uint32_t div, pre, reg, parent;
sys/dev/fdt/imxccm.c
1510
div = HREAD4(sc, sc->sc_divs[idx].reg);
sys/dev/fdt/imxccm.c
1527
if (idx < sc->sc_ngates && sc->sc_gates[idx].reg &&
sys/dev/fdt/imxccm.c
1528
idx < sc->sc_ndivs && sc->sc_divs[idx].reg &&
sys/dev/fdt/imxccm.c
1529
idx < sc->sc_npredivs && sc->sc_predivs[idx].reg) {
sys/dev/fdt/imxccm.c
1559
reg = HREAD4(sc, sc->sc_divs[idx].reg);
sys/dev/fdt/imxccm.c
1560
div = reg >> sc->sc_divs[idx].shift;
sys/dev/fdt/imxccm.c
1562
pre = reg >> sc->sc_predivs[idx].shift;
sys/dev/fdt/imxccm.c
1568
if (idx < sc->sc_ngates && sc->sc_gates[idx].reg &&
sys/dev/fdt/imxccm.c
1569
idx < sc->sc_ndivs && sc->sc_divs[idx].reg &&
sys/dev/fdt/imxccm.c
1570
idx < sc->sc_npredivs && sc->sc_predivs[idx].reg) {
sys/dev/fdt/imxccm.c
1611
reg = HREAD4(sc, sc->sc_divs[idx].reg);
sys/dev/fdt/imxccm.c
1612
div = reg >> sc->sc_divs[idx].shift;
sys/dev/fdt/imxccm.c
1614
pre = reg >> sc->sc_predivs[idx].shift;
sys/dev/fdt/imxccm.c
1628
if (idx < sc->sc_ngates && sc->sc_gates[idx].reg &&
sys/dev/fdt/imxccm.c
1629
idx < sc->sc_ndivs && sc->sc_divs[idx].reg &&
sys/dev/fdt/imxccm.c
1630
idx < sc->sc_npredivs && sc->sc_predivs[idx].reg) {
sys/dev/fdt/imxccm.c
1675
reg = HREAD4(sc, sc->sc_divs[idx].reg);
sys/dev/fdt/imxccm.c
1676
div = reg >> sc->sc_divs[idx].shift;
sys/dev/fdt/imxccm.c
1678
pre = reg >> sc->sc_predivs[idx].shift;
sys/dev/fdt/imxccm.c
1750
uint32_t reg, div, parent, parent_freq;
sys/dev/fdt/imxccm.c
176
#define HREAD4(sc, reg) \
sys/dev/fdt/imxccm.c
177
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/imxccm.c
178
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/imxccm.c
179
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/imxccm.c
180
#define HSET4(sc, reg, bits) \
sys/dev/fdt/imxccm.c
181
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/imxccm.c
182
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/imxccm.c
183
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/imxccm.c
1835
reg = HREAD4(sc, sc->sc_divs[idx].reg);
sys/dev/fdt/imxccm.c
1836
reg &= ~(sc->sc_divs[idx].mask << sc->sc_divs[idx].shift);
sys/dev/fdt/imxccm.c
1837
reg |= (div << sc->sc_divs[idx].shift);
sys/dev/fdt/imxccm.c
1838
HWRITE4(sc, sc->sc_divs[idx].reg, reg);
sys/dev/fdt/imxccm.c
186
uint16_t reg;
sys/dev/fdt/imxccm.c
1868
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1874
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
sys/dev/fdt/imxccm.c
1879
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1882
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
sys/dev/fdt/imxccm.c
1888
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1891
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
sys/dev/fdt/imxccm.c
1897
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1900
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
sys/dev/fdt/imxccm.c
1906
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1909
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
sys/dev/fdt/imxccm.c
1917
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
192
uint16_t reg;
sys/dev/fdt/imxccm.c
1920
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
sys/dev/fdt/imxccm.c
1925
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1928
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
sys/dev/fdt/imxccm.c
1933
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1936
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
sys/dev/fdt/imxccm.c
1941
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1944
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
sys/dev/fdt/imxccm.c
1949
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1952
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
sys/dev/fdt/imxccm.c
1957
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1960
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
sys/dev/fdt/imxccm.c
1965
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1968
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
sys/dev/fdt/imxccm.c
1977
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1983
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
sys/dev/fdt/imxccm.c
1988
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
1991
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
sys/dev/fdt/imxccm.c
1997
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
200
uint16_t reg;
sys/dev/fdt/imxccm.c
2000
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
sys/dev/fdt/imxccm.c
2006
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
2009
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
sys/dev/fdt/imxccm.c
2015
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
2018
HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
sys/dev/fdt/imxccm.c
566
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
569
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
589
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
592
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
612
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
615
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
633
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
636
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
691
uint32_t pll0, pll1, reg;
sys/dev/fdt/imxccm.c
757
reg = regmap_read_4(sc->sc_anatop, pll0);
sys/dev/fdt/imxccm.c
758
if (reg & CCM_INT_PLL_LOCK)
sys/dev/fdt/imxccm.c
776
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
779
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
799
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
802
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
828
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
831
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
849
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
852
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
870
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
873
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
893
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
896
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
916
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
919
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
939
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
942
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
962
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
965
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxccm.c
985
if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
sys/dev/fdt/imxccm.c
988
mux = HREAD4(sc, sc->sc_muxs[idx].reg);
sys/dev/fdt/imxdog.c
79
uint16_t reg;
sys/dev/fdt/imxdog.c
94
reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, WCR);
sys/dev/fdt/imxdog.c
95
reg &= ~WCR_WT_MASK;
sys/dev/fdt/imxdog.c
96
reg |= WCR_WT_SEC(WDOG_MAX_TIMEOUT_SEC);
sys/dev/fdt/imxdog.c
97
bus_space_write_2(sc->sc_iot, sc->sc_ioh, WCR, reg);
sys/dev/fdt/imxehci.c
126
uint32_t off, reg;
sys/dev/fdt/imxehci.c
197
reg = bus_space_read_4(sc->sc.iot, sc->nc_ioh, off);
sys/dev/fdt/imxehci.c
198
reg &= ~USBNC_USB_CTRL_OVER_CUR_DIS;
sys/dev/fdt/imxehci.c
200
reg |= USBNC_USB_CTRL_OVER_CUR_DIS;
sys/dev/fdt/imxehci.c
202
reg |= USBNC_USB_CTRL_OVER_CUR_POL;
sys/dev/fdt/imxehci.c
204
reg &= ~USBNC_USB_CTRL_OVER_CUR_POL;
sys/dev/fdt/imxehci.c
206
reg |= USBNC_USB_CTRL_PWR_POL;
sys/dev/fdt/imxehci.c
207
reg |= USBNC_USB_CTRL_NON_BURST;
sys/dev/fdt/imxehci.c
208
bus_space_write_4(sc->sc.iot, sc->nc_ioh, off, reg);
sys/dev/fdt/imxesdhc.c
220
#define HREAD4(sc, reg) \
sys/dev/fdt/imxesdhc.c
221
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/imxesdhc.c
222
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/imxesdhc.c
223
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/imxesdhc.c
224
#define HSET4(sc, reg, bits) \
sys/dev/fdt/imxesdhc.c
225
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/imxesdhc.c
226
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/imxesdhc.c
227
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/imxesdhc.c
299
int error = 1, node, reg;
sys/dev/fdt/imxesdhc.c
454
reg = OF_getpropint(node, "reg", -1);
sys/dev/fdt/imxesdhc.c
455
if (reg < 0 || reg >= SDMMC_MAX_FUNCTIONS)
sys/dev/fdt/imxesdhc.c
457
sc->sc_cookies[reg] = node;
sys/dev/fdt/imxesdhc.c
458
saa.cookies[reg] = &sc->sc_cookies[reg];
sys/dev/fdt/imxesdhc.c
737
uint32_t reg;
sys/dev/fdt/imxesdhc.c
745
reg = HREAD4(sc, SDHC_PROT_CTRL) & ~SDHC_PROT_CTRL_DTW_MASK;
sys/dev/fdt/imxesdhc.c
747
reg |= SDHC_PROT_CTRL_DTW_4BIT;
sys/dev/fdt/imxesdhc.c
749
reg |= SDHC_PROT_CTRL_DTW_8BIT;
sys/dev/fdt/imxesdhc.c
750
HWRITE4(sc, SDHC_PROT_CTRL, reg);
sys/dev/fdt/imxgpio.c
173
uint32_t reg;
sys/dev/fdt/imxgpio.c
176
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_DR);
sys/dev/fdt/imxgpio.c
177
reg &= (1 << pin);
sys/dev/fdt/imxgpio.c
178
val = (reg >> pin) & 1;
sys/dev/fdt/imxgpio.c
190
uint32_t reg;
sys/dev/fdt/imxgpio.c
192
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_DR);
sys/dev/fdt/imxgpio.c
196
reg |= (1 << pin);
sys/dev/fdt/imxgpio.c
198
reg &= ~(1 << pin);
sys/dev/fdt/imxgpio.c
199
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_DR, reg);
sys/dev/fdt/imxgpio.c
240
int s, val, reg, shift;
sys/dev/fdt/imxgpio.c
296
reg = GPIO_ICR1;
sys/dev/fdt/imxgpio.c
299
reg = GPIO_ICR2;
sys/dev/fdt/imxgpio.c
303
bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg,
sys/dev/fdt/imxgpio.c
304
bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg) & ~(0x3 << shift));
sys/dev/fdt/imxgpio.c
305
bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg,
sys/dev/fdt/imxgpio.c
306
bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg) | val << shift);
sys/dev/fdt/imxiic_fdt.c
124
uint32_t reg[1];
sys/dev/fdt/imxiic_fdt.c
129
memset(reg, 0, sizeof(reg));
sys/dev/fdt/imxiic_fdt.c
139
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/dev/fdt/imxiic_fdt.c
144
ia.ia_addr = bemtoh32(®[0]);
sys/dev/fdt/imxpwm.c
53
#define HREAD4(sc, reg) \
sys/dev/fdt/imxpwm.c
54
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/imxpwm.c
55
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/imxpwm.c
56
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/imxpwm.c
57
#define HSET4(sc, reg, bits) \
sys/dev/fdt/imxpwm.c
58
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/imxpwm.c
59
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/imxpwm.c
60
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/imxrtc.c
39
#define HREAD4(sc, reg) \
sys/dev/fdt/imxrtc.c
40
(regmap_read_4((sc)->sc_rm, (reg)))
sys/dev/fdt/imxrtc.c
41
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/imxrtc.c
42
regmap_write_4((sc)->sc_rm, (reg), (val))
sys/dev/fdt/imxspi.c
121
#define HREAD4(sc, reg) \
sys/dev/fdt/imxspi.c
122
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/imxspi.c
123
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/imxspi.c
124
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/imxspi.c
125
#define HSET4(sc, reg, bits) \
sys/dev/fdt/imxspi.c
126
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/imxspi.c
127
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/imxspi.c
128
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/imxspi.c
411
uint32_t reg[1];
sys/dev/fdt/imxspi.c
417
memset(reg, 0, sizeof(reg));
sys/dev/fdt/imxspi.c
424
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/dev/fdt/imxsrc.c
168
uint32_t reg;
sys/dev/fdt/imxsrc.c
187
reg = HREAD4(sc, sc->sc_resets[idx].reg);
sys/dev/fdt/imxsrc.c
189
reg |= sc->sc_resets[idx].bit;
sys/dev/fdt/imxsrc.c
191
reg &= ~sc->sc_resets[idx].bit;
sys/dev/fdt/imxsrc.c
192
HWRITE4(sc, sc->sc_resets[idx].reg, reg);
sys/dev/fdt/imxsrc.c
61
uint32_t reg;
sys/dev/fdt/imxsrc.c
92
#define HREAD4(sc, reg) \
sys/dev/fdt/imxsrc.c
93
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/imxsrc.c
94
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/imxsrc.c
95
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/imxsrc.c
96
#define HSET4(sc, reg, bits) \
sys/dev/fdt/imxsrc.c
97
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/imxsrc.c
98
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/imxsrc.c
99
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/imxtmu.c
54
#define HREAD4(sc, reg) \
sys/dev/fdt/imxtmu.c
55
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/imxtmu.c
56
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/imxtmu.c
57
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/imxtmu.c
58
#define HSET4(sc, reg, bits) \
sys/dev/fdt/imxtmu.c
59
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/imxtmu.c
60
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/imxtmu.c
61
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/imxuart.c
132
struct fdt_reg reg;
sys/dev/fdt/imxuart.c
139
if (fdt_get_reg(node, 0, ®))
sys/dev/fdt/imxuart.c
142
imxuartcnattach(fdt_cons_bs_tag, reg.addr, B115200, TTYDEF_CFLAG);
sys/dev/fdt/mtintc.c
117
int reg = (irq / 32) * 4;
sys/dev/fdt/mtintc.c
120
bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg,
sys/dev/fdt/mtintc.c
121
bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg) | 1U << bit);
sys/dev/fdt/mtxhci.c
62
#define HREAD4(sc, reg) \
sys/dev/fdt/mtxhci.c
63
bus_space_read_4((sc)->sc.iot, (sc)->sc_port_ioh, (reg))
sys/dev/fdt/mtxhci.c
64
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mtxhci.c
65
bus_space_write_4((sc)->sc.iot, (sc)->sc_port_ioh, (reg), (val))
sys/dev/fdt/mvclock.c
233
uint32_t reg;
sys/dev/fdt/mvclock.c
241
reg = regmap_read_4(rm, CP110_PM_CLOCK_GATING_CTRL);
sys/dev/fdt/mvclock.c
243
reg |= (1U << idx);
sys/dev/fdt/mvclock.c
245
reg &= ~(1U << idx);
sys/dev/fdt/mvclock.c
246
regmap_write_4(rm, CP110_PM_CLOCK_GATING_CTRL, reg);
sys/dev/fdt/mvclock.c
31
#define HREAD4(sc, reg) \
sys/dev/fdt/mvclock.c
32
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/mvclock.c
33
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvclock.c
34
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mvclock.c
35
#define HSET4(sc, reg, bits) \
sys/dev/fdt/mvclock.c
36
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/mvclock.c
37
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/mvclock.c
38
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/mvclock.c
412
uint32_t reg;
sys/dev/fdt/mvclock.c
414
reg = HREAD4(sc, PERIPH_CLK_DIS);
sys/dev/fdt/mvclock.c
415
reg &= ~(1 << idx);
sys/dev/fdt/mvclock.c
417
reg |= (1 << idx);
sys/dev/fdt/mvclock.c
418
HWRITE4(sc, PERIPH_CLK_DIS, reg);
sys/dev/fdt/mvclock.c
424
uint32_t reg;
sys/dev/fdt/mvclock.c
426
reg = HREAD4(sc, PERIPH_TBG_SEL);
sys/dev/fdt/mvclock.c
427
reg >>= idx;
sys/dev/fdt/mvclock.c
428
reg &= PERIPH_TBG_SEL_MASK;
sys/dev/fdt/mvclock.c
430
return clock_get_frequency_idx(sc->sc_cd.cd_node, reg);
sys/dev/fdt/mvclock.c
436
uint32_t reg = HREAD4(sc, off);
sys/dev/fdt/mvclock.c
437
return ((reg >> idx) & PERIPH_DIV_SEL_MASK);
sys/dev/fdt/mvclock.c
444
uint32_t reg = HREAD4(sc, off);
sys/dev/fdt/mvclock.c
445
return ((reg >> idx0) & PERIPH_DIV_SEL_MASK) *
sys/dev/fdt/mvclock.c
446
((reg >> idx1) & PERIPH_DIV_SEL_MASK);
sys/dev/fdt/mvclock.c
476
uint32_t reg, vcodiv;
sys/dev/fdt/mvclock.c
504
reg = HREAD4(sc, TBG_CTRL0);
sys/dev/fdt/mvclock.c
506
reg >>= TBG_A_FBDIV_SHIFT;
sys/dev/fdt/mvclock.c
508
reg >>= TBG_B_FBDIV_SHIFT;
sys/dev/fdt/mvclock.c
509
reg &= TBG_DIV_MASK;
sys/dev/fdt/mvclock.c
510
mult = reg << 2;
sys/dev/fdt/mvclock.c
512
reg = HREAD4(sc, TBG_CTRL7);
sys/dev/fdt/mvclock.c
514
reg >>= TBG_A_REFDIV_SHIFT;
sys/dev/fdt/mvclock.c
516
reg >>= TBG_B_REFDIV_SHIFT;
sys/dev/fdt/mvclock.c
517
reg &= TBG_DIV_MASK;
sys/dev/fdt/mvclock.c
518
div = reg;
sys/dev/fdt/mvdog.c
36
#define HREAD4(sc, reg) \
sys/dev/fdt/mvdog.c
37
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/mvdog.c
38
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvdog.c
39
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mvdog.c
40
#define HSET4(sc, reg, bits) \
sys/dev/fdt/mvdog.c
41
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/mvdog.c
42
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/mvdog.c
43
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/mvgpio.c
121
uint32_t reg;
sys/dev/fdt/mvgpio.c
127
reg = HREAD4(sc, GPIO_DIN);
sys/dev/fdt/mvgpio.c
128
reg ^= HREAD4(sc, GPIO_DINACTLOW);
sys/dev/fdt/mvgpio.c
129
reg &= (1 << pin);
sys/dev/fdt/mvgpio.c
130
val = (reg >> pin) & 1;
sys/dev/fdt/mvgpio.c
37
#define HREAD4(sc, reg) \
sys/dev/fdt/mvgpio.c
38
(regmap_read_4((sc)->sc_rm, (sc)->sc_offset + (reg)))
sys/dev/fdt/mvgpio.c
39
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvgpio.c
40
regmap_write_4((sc)->sc_rm, (sc)->sc_offset + (reg), (val))
sys/dev/fdt/mvgpio.c
41
#define HSET4(sc, reg, bits) \
sys/dev/fdt/mvgpio.c
42
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/mvgpio.c
43
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/mvgpio.c
44
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/mvicu.c
59
#define HREAD4(sc, reg) \
sys/dev/fdt/mvicu.c
60
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/mvicu.c
61
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvicu.c
62
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mviic.c
318
uint32_t reg[1];
sys/dev/fdt/mviic.c
323
memset(reg, 0, sizeof(reg));
sys/dev/fdt/mviic.c
333
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/dev/fdt/mviic.c
338
ia.ia_addr = bemtoh32(®[0]);
sys/dev/fdt/mviic.c
84
#define HREAD4(sc, reg) \
sys/dev/fdt/mviic.c
85
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/mviic.c
86
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mviic.c
87
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mviic.c
88
#define HSET4(sc, reg, bits) \
sys/dev/fdt/mviic.c
89
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/mviic.c
90
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/mviic.c
91
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/mvkpcie.c
127
#define HREAD4(sc, reg) \
sys/dev/fdt/mvkpcie.c
128
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/mvkpcie.c
129
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvkpcie.c
130
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mvkpcie.c
131
#define HSET4(sc, reg, bits) \
sys/dev/fdt/mvkpcie.c
132
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/mvkpcie.c
133
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/mvkpcie.c
134
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/mvkpcie.c
277
uint32_t reg;
sys/dev/fdt/mvkpcie.c
376
reg = HREAD4(sc, CTRL_CORE_CONFIG);
sys/dev/fdt/mvkpcie.c
377
reg &= ~CTRL_CORE_CONFIG_MODE_MASK;
sys/dev/fdt/mvkpcie.c
378
reg |= CTRL_CORE_CONFIG_MODE_DIRECT;
sys/dev/fdt/mvkpcie.c
379
HWRITE4(sc, CTRL_CORE_CONFIG, reg);
sys/dev/fdt/mvkpcie.c
397
reg = HREAD4(sc, LMI_DEBUG_CTRL);
sys/dev/fdt/mvkpcie.c
398
reg |= LMI_DEBUG_CTRL_DIS_ORD_CHK;
sys/dev/fdt/mvkpcie.c
399
HWRITE4(sc, LMI_DEBUG_CTRL, reg);
sys/dev/fdt/mvkpcie.c
401
reg = HREAD4(sc, PCIE_CORE_CTRL0);
sys/dev/fdt/mvkpcie.c
402
reg &= ~PCIE_CORE_CTRL0_GEN_MASK;
sys/dev/fdt/mvkpcie.c
403
reg |= PCIE_CORE_CTRL0_GEN_2;
sys/dev/fdt/mvkpcie.c
404
HWRITE4(sc, PCIE_CORE_CTRL0, reg);
sys/dev/fdt/mvkpcie.c
406
reg = HREAD4(sc, PCIE_CORE_CTRL0);
sys/dev/fdt/mvkpcie.c
407
reg &= ~PCIE_CORE_CTRL0_LANE_MASK;
sys/dev/fdt/mvkpcie.c
408
reg |= PCIE_CORE_CTRL0_LANE_1;
sys/dev/fdt/mvkpcie.c
409
HWRITE4(sc, PCIE_CORE_CTRL0, reg);
sys/dev/fdt/mvkpcie.c
569
uint32_t reg;
sys/dev/fdt/mvkpcie.c
571
reg = HREAD4(sc, LMI_CFG);
sys/dev/fdt/mvkpcie.c
572
return LMI_CFG_LTSSM_VAL(reg) >= LMI_CFG_LTSSM_L0;
sys/dev/fdt/mvkpcie.c
615
mvkpcie_conf_read_bridge(struct mvkpcie_softc *sc, int reg)
sys/dev/fdt/mvkpcie.c
617
switch (reg) {
sys/dev/fdt/mvkpcie.c
650
mvkpcie_conf_write_bridge(struct mvkpcie_softc *sc, int reg, pcireg_t data)
sys/dev/fdt/mvkpcie.c
660
uint32_t reg;
sys/dev/fdt/mvkpcie.c
671
reg = HREAD4(sc, PIO_CTRL);
sys/dev/fdt/mvkpcie.c
672
reg &= ~PIO_CTRL_TYPE_MASK;
sys/dev/fdt/mvkpcie.c
674
reg |= PIO_CTRL_TYPE_RD0;
sys/dev/fdt/mvkpcie.c
676
reg |= PIO_CTRL_TYPE_RD1;
sys/dev/fdt/mvkpcie.c
677
HWRITE4(sc, PIO_CTRL, reg);
sys/dev/fdt/mvkpcie.c
702
uint32_t reg;
sys/dev/fdt/mvkpcie.c
714
reg = HREAD4(sc, PIO_CTRL);
sys/dev/fdt/mvkpcie.c
715
reg &= ~PIO_CTRL_TYPE_MASK;
sys/dev/fdt/mvkpcie.c
717
reg |= PIO_CTRL_TYPE_WR0;
sys/dev/fdt/mvkpcie.c
719
reg |= PIO_CTRL_TYPE_WR1;
sys/dev/fdt/mvkpcie.c
720
HWRITE4(sc, PIO_CTRL, reg);
sys/dev/fdt/mvkpcie.c
805
uint32_t reg[4];
sys/dev/fdt/mvkpcie.c
809
reg[0] = bus << 16 | dev << 11 | fn << 8;
sys/dev/fdt/mvkpcie.c
810
reg[1] = reg[2] = 0;
sys/dev/fdt/mvkpcie.c
811
reg[3] = ih.ih_intrpin;
sys/dev/fdt/mvkpcie.c
813
cookie = fdt_intr_establish_imap_cpu(sc->sc_node, reg,
sys/dev/fdt/mvkpcie.c
814
sizeof(reg), level, ci, func, arg, name);
sys/dev/fdt/mvmdio.c
120
mvmdio_smi_readreg(struct device *dev, int phy, int reg)
sys/dev/fdt/mvmdio.c
139
smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg)
sys/dev/fdt/mvmdio.c
158
mvmdio_smi_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/fdt/mvmdio.c
177
smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg) |
sys/dev/fdt/mvmdio.c
50
#define MVNETA_READ(sc, reg) \
sys/dev/fdt/mvmdio.c
51
bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
sys/dev/fdt/mvmdio.c
52
#define MVNETA_WRITE(sc, reg, val) \
sys/dev/fdt/mvmdio.c
53
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mvpinctrl.c
300
uint32_t reg;
sys/dev/fdt/mvpinctrl.c
306
reg = HREAD4(sc, GPIO_INPUT);
sys/dev/fdt/mvpinctrl.c
307
reg &= (1 << pin);
sys/dev/fdt/mvpinctrl.c
308
val = (reg >> pin) & 1;
sys/dev/fdt/mvpinctrl.c
40
#define HREAD4(sc, reg) \
sys/dev/fdt/mvpinctrl.c
41
(regmap_read_4((sc)->sc_rm, (reg)))
sys/dev/fdt/mvpinctrl.c
42
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvpinctrl.c
43
regmap_write_4((sc)->sc_rm, (reg), (val))
sys/dev/fdt/mvpinctrl.c
44
#define HSET4(sc, reg, bits) \
sys/dev/fdt/mvpinctrl.c
45
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/mvpinctrl.c
46
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/mvpinctrl.c
47
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/mvrng.c
48
#define HREAD4(sc, reg) \
sys/dev/fdt/mvrng.c
49
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/mvrng.c
50
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvrng.c
51
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mvrng.c
52
#define HSET4(sc, reg, bits) \
sys/dev/fdt/mvrng.c
53
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/mvrng.c
54
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/mvrng.c
55
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/mvrtc.c
108
reg = bus_space_read_4(sc->sc_iot, sc->sc_soc_ioh, RTC_TIMING_CTL0);
sys/dev/fdt/mvrtc.c
109
reg &= ~RTC_TIMING_CTL0_WRCLK_PERIOD_MASK;
sys/dev/fdt/mvrtc.c
110
reg |= (0x3ff << RTC_TIMING_CTL0_WRCLK_PERIOD_SHIFT);
sys/dev/fdt/mvrtc.c
111
reg &= ~RTC_TIMING_CTL0_WRCLK_SETUP_MASK;
sys/dev/fdt/mvrtc.c
112
reg |= (0x29 << RTC_TIMING_CTL0_WRCLK_SETUP_SHIFT);
sys/dev/fdt/mvrtc.c
113
bus_space_write_4(sc->sc_iot, sc->sc_soc_ioh, RTC_TIMING_CTL0, reg);
sys/dev/fdt/mvrtc.c
114
reg = bus_space_read_4(sc->sc_iot, sc->sc_soc_ioh, RTC_TIMING_CTL1);
sys/dev/fdt/mvrtc.c
115
reg &= ~RTC_TIMING_CTL1_READ_DELAY_MASK;
sys/dev/fdt/mvrtc.c
116
reg |= (0x3f << RTC_TIMING_CTL1_READ_DELAY_SHIFT);
sys/dev/fdt/mvrtc.c
117
bus_space_write_4(sc->sc_iot, sc->sc_soc_ioh, RTC_TIMING_CTL1, reg);
sys/dev/fdt/mvrtc.c
44
#define HREAD4(sc, reg) \
sys/dev/fdt/mvrtc.c
45
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/mvrtc.c
46
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvrtc.c
47
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mvrtc.c
85
uint32_t reg;
sys/dev/fdt/mvspi.c
291
uint32_t reg[1];
sys/dev/fdt/mvspi.c
297
memset(reg, 0, sizeof(reg));
sys/dev/fdt/mvspi.c
304
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/dev/fdt/mvspi.c
81
#define HREAD4(sc, reg) \
sys/dev/fdt/mvspi.c
82
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/mvspi.c
83
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvspi.c
84
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mvspi.c
85
#define HSET4(sc, reg, bits) \
sys/dev/fdt/mvspi.c
86
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/mvspi.c
87
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/mvspi.c
88
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/mvsw.c
164
mvsw_read(struct mvsw_softc *sc, int reg)
sys/dev/fdt/mvsw.c
167
return md->md_readreg(md->md_cookie, sc->sc_reg, reg);
sys/dev/fdt/mvsw.c
171
mvsw_write(struct mvsw_softc *sc, int reg, int val)
sys/dev/fdt/mvsw.c
174
md->md_writereg(md->md_cookie, sc->sc_reg, reg, val);
sys/dev/fdt/mvsw.c
193
mvsw_smi_read(struct mvsw_softc *sc, int phy, int reg)
sys/dev/fdt/mvsw.c
199
MVSW_SMI_CMD_DEVAD(phy) | MVSW_SMI_CMD_REGAD(reg) |
sys/dev/fdt/mvsw.c
209
mvsw_smi_write(struct mvsw_softc *sc, int phy, int reg, int val)
sys/dev/fdt/mvsw.c
216
MVSW_SMI_CMD_DEVAD(phy) | MVSW_SMI_CMD_REGAD(reg) |
sys/dev/fdt/mvsw.c
239
mvsw_phy_read(struct mvsw_softc *sc, int phy, int reg)
sys/dev/fdt/mvsw.c
245
MVSW_SMI_CMD_DEVAD(phy) | MVSW_SMI_CMD_REGAD(reg) |
sys/dev/fdt/mvsw.c
255
mvsw_phy_write(struct mvsw_softc *sc, int phy, int reg, int val)
sys/dev/fdt/mvsw.c
262
MVSW_SMI_CMD_DEVAD(phy) | MVSW_SMI_CMD_REGAD(reg) |
sys/dev/fdt/mvtemp.c
190
mvtemp_read(struct mvtemp_softc *sc, int reg)
sys/dev/fdt/mvtemp.c
193
return regmap_read_4(sc->sc_rm, sc->sc_offs[reg]);
sys/dev/fdt/mvtemp.c
194
else if (reg == REG_STAT)
sys/dev/fdt/mvtemp.c
195
return bus_space_read_4(sc->sc_iot, sc->sc_stat_ioh, sc->sc_offs[reg]);
sys/dev/fdt/mvtemp.c
197
return bus_space_read_4(sc->sc_iot, sc->sc_ctrl_ioh, sc->sc_offs[reg]);
sys/dev/fdt/mvtemp.c
201
mvtemp_write(struct mvtemp_softc *sc, int reg, uint32_t val)
sys/dev/fdt/mvtemp.c
204
regmap_write_4(sc->sc_rm, sc->sc_offs[reg], val);
sys/dev/fdt/mvtemp.c
205
else if (reg == REG_STAT)
sys/dev/fdt/mvtemp.c
206
bus_space_write_4(sc->sc_iot, sc->sc_stat_ioh, sc->sc_offs[reg], val);
sys/dev/fdt/mvtemp.c
208
bus_space_write_4(sc->sc_iot, sc->sc_ctrl_ioh, sc->sc_offs[reg], val);
sys/dev/fdt/mvuart.c
134
struct fdt_reg reg;
sys/dev/fdt/mvuart.c
140
if (fdt_get_reg(node, 0, ®))
sys/dev/fdt/mvuart.c
143
mvuartcnattach(fdt_cons_bs_tag, reg.addr, B115200, TTYDEF_CFLAG);
sys/dev/fdt/mvuart.c
60
#define HREAD4(sc, reg) \
sys/dev/fdt/mvuart.c
61
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/mvuart.c
62
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/mvuart.c
63
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/mvuart.c
64
#define HSET4(sc, reg, bits) \
sys/dev/fdt/mvuart.c
65
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/mvuart.c
66
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/mvuart.c
67
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/ociic.c
314
uint32_t reg[1];
sys/dev/fdt/ociic.c
319
memset(reg, 0, sizeof(reg));
sys/dev/fdt/ociic.c
329
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/dev/fdt/ociic.c
334
ia.ia_addr = bemtoh32(®[0]);
sys/dev/fdt/ociic.c
73
ociic_read(struct ociic_softc *sc, bus_size_t reg)
sys/dev/fdt/ociic.c
75
return bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg);
sys/dev/fdt/ociic.c
79
ociic_write(struct ociic_softc *sc, bus_size_t reg, uint8_t value)
sys/dev/fdt/ociic.c
81
bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, value);
sys/dev/fdt/ociic.c
85
ociic_set(struct ociic_softc *sc, bus_size_t reg, uint8_t bits)
sys/dev/fdt/ociic.c
87
ociic_write(sc, reg, ociic_read(sc, reg) | bits);
sys/dev/fdt/ociic.c
91
ociic_clr(struct ociic_softc *sc, bus_size_t reg, uint8_t bits)
sys/dev/fdt/ociic.c
93
ociic_write(sc, reg, ociic_read(sc, reg) & ~bits);
sys/dev/fdt/pciecam.c
318
pciecam_conf_read(void *v, pcitag_t tag, int reg)
sys/dev/fdt/pciecam.c
325
return HREAD4(sc, PCIE_ADDR_OFFSET(bus, dev, fn, reg & ~0x3));
sys/dev/fdt/pciecam.c
329
pciecam_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
sys/dev/fdt/pciecam.c
336
HWRITE4(sc, PCIE_ADDR_OFFSET(bus, dev, fn, reg & ~0x3), data);
sys/dev/fdt/pciecam.c
436
uint32_t reg[4];
sys/dev/fdt/pciecam.c
440
reg[0] = bus << 16 | dev << 11 | fn << 8;
sys/dev/fdt/pciecam.c
441
reg[1] = reg[2] = 0;
sys/dev/fdt/pciecam.c
442
reg[3] = ih.ih_intrpin;
sys/dev/fdt/pciecam.c
444
cookie = fdt_intr_establish_imap_cpu(sc->sc_node, reg,
sys/dev/fdt/pciecam.c
445
sizeof(reg), level, ci, func, arg, name);
sys/dev/fdt/pciecam.c
49
#define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
sys/dev/fdt/pciecam.c
53
((reg) & PCIE_REG_MASK))
sys/dev/fdt/pciecam.c
55
#define HREAD4(sc, reg) \
sys/dev/fdt/pciecam.c
56
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/pciecam.c
57
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/pciecam.c
58
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/pciecam.c
59
#define HSET4(sc, reg, bits) \
sys/dev/fdt/pciecam.c
60
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/pciecam.c
61
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/pciecam.c
62
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/pinctrl.c
155
uint32_t reg = pins[i];
sys/dev/fdt/pinctrl.c
163
val = HREAD2(sc, reg);
sys/dev/fdt/pinctrl.c
165
val = HREAD4(sc, reg);
sys/dev/fdt/pinctrl.c
175
HWRITE2(sc, reg, val);
sys/dev/fdt/pinctrl.c
177
HWRITE4(sc, reg, val);
sys/dev/fdt/pinctrl.c
32
#define HREAD2(sc, reg) \
sys/dev/fdt/pinctrl.c
33
(bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/pinctrl.c
34
#define HWRITE2(sc, reg, val) \
sys/dev/fdt/pinctrl.c
35
bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/pinctrl.c
36
#define HREAD4(sc, reg) \
sys/dev/fdt/pinctrl.c
37
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/pinctrl.c
38
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/pinctrl.c
39
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/plgpio.c
124
uint32_t reg;
sys/dev/fdt/plgpio.c
130
reg = HREAD1(sc, GPIODATA(pin));
sys/dev/fdt/plgpio.c
131
val = !!reg;
sys/dev/fdt/plgpio.c
34
#define HREAD1(sc, reg) \
sys/dev/fdt/plgpio.c
35
(bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/plgpio.c
36
#define HWRITE1(sc, reg, val) \
sys/dev/fdt/plgpio.c
37
bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/plgpio.c
38
#define HSET1(sc, reg, bits) \
sys/dev/fdt/plgpio.c
39
HWRITE1((sc), (reg), HREAD1((sc), (reg)) | (bits))
sys/dev/fdt/plgpio.c
40
#define HCLR1(sc, reg, bits) \
sys/dev/fdt/plgpio.c
41
HWRITE1((sc), (reg), HREAD1((sc), (reg)) & ~(bits))
sys/dev/fdt/pluart_fdt.c
43
struct fdt_reg reg;
sys/dev/fdt/pluart_fdt.c
48
if (fdt_get_reg(node, 0, ®))
sys/dev/fdt/pluart_fdt.c
51
pluartcnattach(fdt_cons_bs_tag, reg.addr, B115200, TTYDEF_CFLAG);
sys/dev/fdt/qcaoss.c
180
uint32_t reg;
sys/dev/fdt/qcaoss.c
192
memcpy(®, data + i, sizeof(reg));
sys/dev/fdt/qcaoss.c
193
HWRITE4(sc, sc->sc_offset + sizeof(uint32_t) + i, reg);
sys/dev/fdt/qcaoss.c
53
#define HREAD4(sc, reg) \
sys/dev/fdt/qcaoss.c
54
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/qcaoss.c
55
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/qcaoss.c
56
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/qccpucp.c
40
#define RXREAD8(sc, reg) \
sys/dev/fdt/qccpucp.c
41
(bus_space_read_8((sc)->sc_iot, (sc)->sc_rx_ioh, (reg)))
sys/dev/fdt/qccpucp.c
42
#define RXWRITE8(sc, reg, val) \
sys/dev/fdt/qccpucp.c
43
bus_space_write_8((sc)->sc_iot, (sc)->sc_rx_ioh, (reg), (val))
sys/dev/fdt/qccpucp.c
45
#define TXWRITE4(sc, reg, val) \
sys/dev/fdt/qccpucp.c
46
bus_space_write_4((sc)->sc_iot, (sc)->sc_tx_ioh, (reg), (val))
sys/dev/fdt/qcgpio_fdt.c
221
uint32_t reg;
sys/dev/fdt/qcgpio_fdt.c
227
reg = HREAD4(sc, TLMM_GPIO_IN_OUT(pin));
sys/dev/fdt/qcgpio_fdt.c
228
val = !!(reg & TLMM_GPIO_IN_OUT_GPIO_IN);
sys/dev/fdt/qcgpio_fdt.c
274
uint32_t reg;
sys/dev/fdt/qcgpio_fdt.c
291
reg = HREAD4(sc, TLMM_GPIO_INTR_CFG(pin));
sys/dev/fdt/qcgpio_fdt.c
292
reg &= ~TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK;
sys/dev/fdt/qcgpio_fdt.c
293
reg &= ~TLMM_GPIO_INTR_CFG_INTR_POL_CTL;
sys/dev/fdt/qcgpio_fdt.c
296
reg |= TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_POS |
sys/dev/fdt/qcgpio_fdt.c
300
reg |= TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_NEG |
sys/dev/fdt/qcgpio_fdt.c
304
reg |= TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_BOTH;
sys/dev/fdt/qcgpio_fdt.c
307
reg |= TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_LEVEL |
sys/dev/fdt/qcgpio_fdt.c
311
reg |= TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_LEVEL;
sys/dev/fdt/qcgpio_fdt.c
318
reg &= ~TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK;
sys/dev/fdt/qcgpio_fdt.c
319
reg |= TLMM_GPIO_INTR_CFG_TARGET_PROC_RPM;
sys/dev/fdt/qcgpio_fdt.c
320
reg |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN;
sys/dev/fdt/qcgpio_fdt.c
321
reg |= TLMM_GPIO_INTR_CFG_INTR_ENABLE;
sys/dev/fdt/qcgpio_fdt.c
322
HWRITE4(sc, TLMM_GPIO_INTR_CFG(pin), reg);
sys/dev/fdt/qcgpio_fdt.c
52
#define HREAD4(sc, reg) \
sys/dev/fdt/qcgpio_fdt.c
53
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/qcgpio_fdt.c
54
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/qcgpio_fdt.c
55
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/qcgpio_fdt.c
56
#define HSET4(sc, reg, bits) \
sys/dev/fdt/qcgpio_fdt.c
57
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/qcgpio_fdt.c
58
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/qcgpio_fdt.c
59
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/qciic_fdt.c
312
uint32_t reg[1];
sys/dev/fdt/qciic_fdt.c
317
memset(reg, 0, sizeof(reg));
sys/dev/fdt/qciic_fdt.c
327
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/dev/fdt/qciic_fdt.c
332
ia.ia_addr = bemtoh32(®[0]);
sys/dev/fdt/qciic_fdt.c
51
#define HREAD4(sc, reg) \
sys/dev/fdt/qciic_fdt.c
52
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/qciic_fdt.c
53
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/qciic_fdt.c
54
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/qcipcc.c
155
uint32_t reg;
sys/dev/fdt/qcipcc.c
158
while ((reg = HREAD4(sc, IPCC_RECV_ID)) != ~0) {
sys/dev/fdt/qcipcc.c
159
HWRITE4(sc, IPCC_RECV_SIGNAL_CLEAR, reg);
sys/dev/fdt/qcipcc.c
161
client_id = (reg >> IPCC_CLIENT_ID_SHIFT) &
sys/dev/fdt/qcipcc.c
163
signal_id = (reg >> IPCC_SIGNAL_ID_SHIFT) &
sys/dev/fdt/qcipcc.c
41
#define HREAD4(sc, reg) \
sys/dev/fdt/qcipcc.c
42
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/qcipcc.c
43
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/qcipcc.c
44
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/qcmtx.c
34
#define HREAD4(sc, reg) \
sys/dev/fdt/qcmtx.c
35
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/qcmtx.c
36
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/qcmtx.c
37
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/qcpas.c
363
uint32_t reg[4];
sys/dev/fdt/qcpas.c
379
if (OF_getpropintarray(node, "reg", reg,
sys/dev/fdt/qcpas.c
380
sizeof(reg)) != sizeof(reg))
sys/dev/fdt/qcpas.c
383
sc->sc_mem_phys[i] = (uint64_t)reg[0] << 32 | reg[1];
sys/dev/fdt/qcpas.c
385
sc->sc_mem_size[i] = (uint64_t)reg[2] << 32 | reg[3];
sys/dev/fdt/qcpas.c
49
#define HREAD4(sc, reg) \
sys/dev/fdt/qcpas.c
50
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/qcpas.c
51
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/qcpas.c
52
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/qcpdc.c
37
#define HREAD4(sc, reg) \
sys/dev/fdt/qcpdc.c
38
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/qcpdc.c
39
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/qcpdc.c
40
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/qcpdc.c
41
#define HSET4(sc, reg, bits) \
sys/dev/fdt/qcpdc.c
42
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/qcpdc.c
43
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/qcpdc.c
44
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/qcpmic.c
112
uint8_t reg = 0;
sys/dev/fdt/qcpmic.c
116
addr, ®, sizeof(reg));
sys/dev/fdt/qcpmic.c
121
return reg;
sys/dev/fdt/qcpmicgpio.c
104
uint8_t reg;
sys/dev/fdt/qcpmicgpio.c
137
reg = qcpmicgpio_read(sc, GPIO_PIN_OFF(pin) + GPIO_TYPE);
sys/dev/fdt/qcpmicgpio.c
138
if (reg != GPIO_TYPE_VAL)
sys/dev/fdt/qcpmicgpio.c
141
reg = qcpmicgpio_read(sc, GPIO_PIN_OFF(pin) + GPIO_SUBTYPE);
sys/dev/fdt/qcpmicgpio.c
142
switch (reg) {
sys/dev/fdt/qcpmicgpio.c
156
sc->sc_dev.dv_xname, reg, pin);
sys/dev/fdt/qcpmicgpio.c
174
uint8_t reg;
sys/dev/fdt/qcpmicgpio.c
188
reg = qcpmicgpio_read(sc, GPIO_PIN_OFF(pin) + GPIO_PIN_MODE);
sys/dev/fdt/qcpmicgpio.c
189
reg &= ~(GPIO_PIN_MODE_DIR_MASK << GPIO_PIN_MODE_DIR_SHIFT);
sys/dev/fdt/qcpmicgpio.c
190
reg |= val << GPIO_PIN_MODE_DIR_SHIFT;
sys/dev/fdt/qcpmicgpio.c
191
qcpmicgpio_write(sc, GPIO_PIN_OFF(pin) + GPIO_PIN_MODE, reg);
sys/dev/fdt/qcpmicgpio.c
201
uint8_t reg;
sys/dev/fdt/qcpmicgpio.c
207
reg = qcpmicgpio_read(sc, GPIO_PIN_OFF(pin) + GPIO_PIN_MODE);
sys/dev/fdt/qcpmicgpio.c
209
reg >>= GPIO_PIN_MODE_DIR_LVMV_SHIFT;
sys/dev/fdt/qcpmicgpio.c
210
reg &= GPIO_PIN_MODE_DIR_LVMV_MASK;
sys/dev/fdt/qcpmicgpio.c
212
reg >>= GPIO_PIN_MODE_DIR_SHIFT;
sys/dev/fdt/qcpmicgpio.c
213
reg &= GPIO_PIN_MODE_DIR_MASK;
sys/dev/fdt/qcpmicgpio.c
216
if (reg == GPIO_PIN_MODE_DIR_DIGITAL_IN ||
sys/dev/fdt/qcpmicgpio.c
217
reg == GPIO_PIN_MODE_DIR_DIGITAL_IO) {
sys/dev/fdt/qcpmicgpio.c
218
reg = qcpmicgpio_read(sc, GPIO_PIN_OFF(pin) + GPIO_PIN_STATUS);
sys/dev/fdt/qcpmicgpio.c
219
val = !!(reg & GPIO_PIN_STATUS_ON);
sys/dev/fdt/qcpmicgpio.c
222
if (reg == GPIO_PIN_MODE_DIR_DIGITAL_OUT) {
sys/dev/fdt/qcpmicgpio.c
224
reg = qcpmicgpio_read(sc, GPIO_PIN_OFF(pin) +
sys/dev/fdt/qcpmicgpio.c
226
val = !!(reg & GPIO_PIN_LVMV_DOUT_CTL_INVERT);
sys/dev/fdt/qcpmicgpio.c
228
reg = qcpmicgpio_read(sc, GPIO_PIN_OFF(pin) +
sys/dev/fdt/qcpmicgpio.c
230
val = !!(reg & GPIO_PIN_MODE_VALUE);
sys/dev/fdt/qcpmicgpio.c
245
uint8_t reg;
sys/dev/fdt/qcpmicgpio.c
254
reg = qcpmicgpio_read(sc, GPIO_PIN_OFF(pin) +
sys/dev/fdt/qcpmicgpio.c
256
reg &= ~GPIO_PIN_LVMV_DOUT_CTL_INVERT;
sys/dev/fdt/qcpmicgpio.c
258
reg |= GPIO_PIN_LVMV_DOUT_CTL_INVERT;
sys/dev/fdt/qcpmicgpio.c
260
GPIO_PIN_LVMV_DOUT_CTL, reg);
sys/dev/fdt/qcpmicgpio.c
262
reg = qcpmicgpio_read(sc, GPIO_PIN_OFF(pin) + GPIO_PIN_MODE);
sys/dev/fdt/qcpmicgpio.c
263
reg &= ~GPIO_PIN_MODE_VALUE;
sys/dev/fdt/qcpmicgpio.c
265
reg |= GPIO_PIN_MODE_VALUE;
sys/dev/fdt/qcpmicgpio.c
266
qcpmicgpio_write(sc, GPIO_PIN_OFF(pin) + GPIO_PIN_MODE, reg);
sys/dev/fdt/qcpmicgpio.c
271
qcpmicgpio_read(struct qcpmicgpio_softc *sc, uint16_t reg)
sys/dev/fdt/qcpmicgpio.c
277
sc->sc_addr + reg, &val, sizeof(val));
sys/dev/fdt/qcpmicgpio.c
285
qcpmicgpio_write(struct qcpmicgpio_softc *sc, uint16_t reg, uint8_t val)
sys/dev/fdt/qcpmicgpio.c
290
sc->sc_addr + reg, &val, sizeof(val));
sys/dev/fdt/qcpon.c
76
uint32_t reg[2];
sys/dev/fdt/qcpon.c
80
reg, sizeof(reg)) != sizeof(reg)) {
sys/dev/fdt/qcpon.c
88
sc->sc_addr = reg[0];
sys/dev/fdt/qcpwm.c
153
uint8_t reg;
sys/dev/fdt/qcpwm.c
163
reg = qcpwm_read(sc, PWM_CHAN_OFF(chan) + PWM_SIZE_CLK);
sys/dev/fdt/qcpwm.c
166
refclk = (reg >> PWM_SIZE_CLK_HI_RES_SELECT_SHIFT) &
sys/dev/fdt/qcpwm.c
169
res = (reg >> PWM_SIZE_CLK_HI_RES_SIZE_SHIFT) &
sys/dev/fdt/qcpwm.c
174
refclk = (reg >> PWM_SIZE_CLK_SELECT_SHIFT) &
sys/dev/fdt/qcpwm.c
177
res = (reg >> PWM_SIZE_CLK_SIZE_SHIFT) &
sys/dev/fdt/qcpwm.c
186
reg = qcpwm_read(sc, PWM_CHAN_OFF(chan) + PWM_PREDIV_CLK);
sys/dev/fdt/qcpwm.c
187
exp = (reg >> PWM_PREDIV_CLK_EXP_SHIFT) &
sys/dev/fdt/qcpwm.c
189
prediv = (reg >> PWM_PREDIV_CLK_PREDIV_SHIFT) &
sys/dev/fdt/qcpwm.c
217
uint8_t reg;
sys/dev/fdt/qcpwm.c
226
reg = qcpwm_read(sc, PWM_CHAN_OFF(chan) + PWM_SIZE_CLK);
sys/dev/fdt/qcpwm.c
276
reg = qcpwm_read(sc, PWM_CHAN_OFF(chan) + PWM_TYPE_CONFIG);
sys/dev/fdt/qcpwm.c
277
reg |= PWM_TYPE_CONFIG_GLITCH_REMOVAL;
sys/dev/fdt/qcpwm.c
278
qcpwm_write(sc, PWM_CHAN_OFF(chan) + PWM_TYPE_CONFIG, reg);
sys/dev/fdt/qcpwm.c
280
reg = clksel << PWM_SIZE_CLK_SELECT_SHIFT;
sys/dev/fdt/qcpwm.c
283
reg |= PWM_SIZE_CLK_LPG_9BIT;
sys/dev/fdt/qcpwm.c
286
reg |= (ressel << PWM_SIZE_CLK_SIZE_SHIFT);
sys/dev/fdt/qcpwm.c
289
reg |= (ressel << PWM_SIZE_CLK_HI_RES_SIZE_SHIFT);
sys/dev/fdt/qcpwm.c
293
reg |= PWM_SIZE_CLK_LPG_LITE_9BIT;
sys/dev/fdt/qcpwm.c
296
qcpwm_write(sc, PWM_CHAN_OFF(chan) + PWM_SIZE_CLK, reg);
sys/dev/fdt/qcpwm.c
307
reg = PWM_ENABLE_CONTROL_BUFFER_TRISTATE;
sys/dev/fdt/qcpwm.c
309
reg |= PWM_ENABLE_CONTROL_OUTPUT;
sys/dev/fdt/qcpwm.c
310
reg |= PWM_ENABLE_CONTROL_SRC_PWM;
sys/dev/fdt/qcpwm.c
311
qcpwm_write(sc, PWM_CHAN_OFF(chan) + PWM_ENABLE_CONTROL, reg);
sys/dev/fdt/qcpwm.c
322
reg = qcpwm_read(sc, PWM_CHAN_OFF(chan) + PWM_TYPE_CONFIG);
sys/dev/fdt/qcpwm.c
323
reg &= ~PWM_TYPE_CONFIG_GLITCH_REMOVAL;
sys/dev/fdt/qcpwm.c
324
qcpwm_write(sc, PWM_CHAN_OFF(chan) + PWM_TYPE_CONFIG, reg);
sys/dev/fdt/qcpwm.c
330
qcpwm_read(struct qcpwm_softc *sc, uint16_t reg)
sys/dev/fdt/qcpwm.c
336
sc->sc_addr + reg, &val, sizeof(val));
sys/dev/fdt/qcpwm.c
344
qcpwm_write(struct qcpwm_softc *sc, uint16_t reg, uint8_t val)
sys/dev/fdt/qcpwm.c
349
sc->sc_addr + reg, &val, sizeof(val));
sys/dev/fdt/qcrng.c
33
#define HREAD4(sc, reg) \
sys/dev/fdt/qcrng.c
34
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/qcrtc.c
105
uint32_t reg, off;
sys/dev/fdt/qcrtc.c
110
sc->sc_addr + RTC_READ, ®, sizeof(reg));
sys/dev/fdt/qcrtc.c
123
tv->tv_sec = off + reg;
sys/dev/fdt/qcrtc.c
132
uint32_t reg, off;
sys/dev/fdt/qcrtc.c
136
sc->sc_addr + RTC_READ, ®, sizeof(reg));
sys/dev/fdt/qcrtc.c
143
off = tv->tv_sec - reg;
sys/dev/fdt/qcrtc.c
79
uint32_t reg[2];
sys/dev/fdt/qcrtc.c
82
reg, sizeof(reg)) != sizeof(reg)) {
sys/dev/fdt/qcrtc.c
90
sc->sc_addr = reg[0];
sys/dev/fdt/qcsdam.c
67
uint32_t reg;
sys/dev/fdt/qcsdam.c
70
®, sizeof(reg)) != sizeof(reg)) {
sys/dev/fdt/qcsdam.c
77
sc->sc_addr = reg;
sys/dev/fdt/qcsmem.c
166
uint32_t reg[4];
sys/dev/fdt/qcsmem.c
176
if (OF_getpropintarray(node, "reg", reg,
sys/dev/fdt/qcsmem.c
177
sizeof(reg)) != sizeof(reg)) {
sys/dev/fdt/qcsmem.c
181
sc->sc_aux_base = (bus_addr_t)reg[0] << 32 | reg[1];
sys/dev/fdt/qcsmem.c
182
sc->sc_aux_size = (bus_size_t)reg[2] << 32 | reg[3];
sys/dev/fdt/qcspmi.c
101
#define HREAD4(sc, obj, reg) \
sys/dev/fdt/qcspmi.c
102
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh[obj], (reg)))
sys/dev/fdt/qcspmi.c
103
#define HWRITE4(sc, obj, reg, val) \
sys/dev/fdt/qcspmi.c
104
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh[obj], (reg), (val))
sys/dev/fdt/qcspmi.c
105
#define HSET4(sc, obj, reg, bits) \
sys/dev/fdt/qcspmi.c
106
HWRITE4((sc), (obj), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/qcspmi.c
107
#define HCLR4(sc, obj, reg, bits) \
sys/dev/fdt/qcspmi.c
108
HWRITE4((sc), (obj), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/qcspmi.c
225
uint32_t reg[8];
sys/dev/fdt/qcspmi.c
227
if (OF_getpropintarray(spmi, "reg", reg,
sys/dev/fdt/qcspmi.c
228
sizeof(reg)) != sizeof(reg)) {
sys/dev/fdt/qcspmi.c
234
spmi_reg[0].addr = ((uint64_t)reg[0] << 32) | reg[1];
sys/dev/fdt/qcspmi.c
235
spmi_reg[0].size = ((uint64_t)reg[2] << 32) | reg[3];
sys/dev/fdt/qcspmi.c
236
spmi_reg[1].addr = ((uint64_t)reg[4] << 32) | reg[5];
sys/dev/fdt/qcspmi.c
237
spmi_reg[1].size = ((uint64_t)reg[6] << 32) | reg[7];
sys/dev/fdt/qcspmi.c
342
uint32_t reg[2];
sys/dev/fdt/qcspmi.c
345
if (OF_getpropintarray(node, "reg", reg,
sys/dev/fdt/qcspmi.c
346
sizeof(reg)) != sizeof(reg))
sys/dev/fdt/qcspmi.c
357
sa.sa_sid = reg[0];
sys/dev/fdt/qcspmi.c
382
uint32_t reg;
sys/dev/fdt/qcspmi.c
405
reg = HREAD4(sc, QCSPMI_REG_OBSRVR,
sys/dev/fdt/qcspmi.c
407
if (reg & SPMI_STATUS_DONE)
sys/dev/fdt/qcspmi.c
409
if (reg & SPMI_STATUS_FAILURE) {
sys/dev/fdt/qcspmi.c
413
if (reg & SPMI_STATUS_DENIED) {
sys/dev/fdt/qcspmi.c
417
if (reg & SPMI_STATUS_DROPPED) {
sys/dev/fdt/qcspmi.c
428
reg = HREAD4(sc, QCSPMI_REG_OBSRVR,
sys/dev/fdt/qcspmi.c
430
memcpy(cbuf, ®, MIN(len, 4));
sys/dev/fdt/qcspmi.c
435
reg = HREAD4(sc, QCSPMI_REG_OBSRVR,
sys/dev/fdt/qcspmi.c
437
memcpy(cbuf, ®, MIN(len, 4));
sys/dev/fdt/qcspmi.c
451
uint32_t reg;
sys/dev/fdt/qcspmi.c
472
memcpy(®, cbuf, MIN(len, 4));
sys/dev/fdt/qcspmi.c
474
SPMI_WDATA0, reg);
sys/dev/fdt/qcspmi.c
479
memcpy(®, cbuf, MIN(len, 4));
sys/dev/fdt/qcspmi.c
481
SPMI_WDATA1, reg);
sys/dev/fdt/qcspmi.c
491
reg = HREAD4(sc, QCSPMI_REG_CHNLS, SPMI_CHAN_OFF(sc, apid) +
sys/dev/fdt/qcspmi.c
493
if (reg & SPMI_STATUS_DONE)
sys/dev/fdt/qcspmi.c
499
if (reg & SPMI_STATUS_FAILURE ||
sys/dev/fdt/qcspmi.c
500
reg & SPMI_STATUS_DENIED ||
sys/dev/fdt/qcspmi.c
501
reg & SPMI_STATUS_DROPPED)
sys/dev/fdt/qcspmi.c
514
uint8_t reg[3];
sys/dev/fdt/qcspmi.c
532
(ih->ih_per << 8) | INTR_SET_TYPE, ®, sizeof(reg));
sys/dev/fdt/qcspmi.c
536
reg[0] &= ~(1U << ih->ih_pin);
sys/dev/fdt/qcspmi.c
537
reg[1] &= ~(1U << ih->ih_pin);
sys/dev/fdt/qcspmi.c
538
reg[2] &= ~(1U << ih->ih_pin);
sys/dev/fdt/qcspmi.c
542
reg[0] |= (1U << ih->ih_pin); /* edge */
sys/dev/fdt/qcspmi.c
543
reg[1] |= (1U << ih->ih_pin); /* rising */
sys/dev/fdt/qcspmi.c
546
reg[0] |= (1U << ih->ih_pin); /* edge */
sys/dev/fdt/qcspmi.c
547
reg[2] |= (1U << ih->ih_pin); /* falling */
sys/dev/fdt/qcspmi.c
550
reg[0] |= (1U << ih->ih_pin); /* edge */
sys/dev/fdt/qcspmi.c
551
reg[1] |= (1U << ih->ih_pin); /* rising */
sys/dev/fdt/qcspmi.c
552
reg[2] |= (1U << ih->ih_pin); /* falling */
sys/dev/fdt/qcspmi.c
555
reg[1] |= (1U << ih->ih_pin); /* high */
sys/dev/fdt/qcspmi.c
558
reg[2] |= (1U << ih->ih_pin); /* low */
sys/dev/fdt/qcspmi.c
567
(ih->ih_per << 8) | INTR_SET_TYPE, ®, sizeof(reg));
sys/dev/fdt/qcspmi.c
598
uint8_t reg[2];
sys/dev/fdt/qcspmi.c
605
(ih->ih_per << 8) | INTR_EN_SET, ®, 1);
sys/dev/fdt/qcspmi.c
609
if (!(reg[0] & (1U << ih->ih_pin))) {
sys/dev/fdt/qcspmi.c
610
reg[0] = (1U << ih->ih_pin);
sys/dev/fdt/qcspmi.c
611
reg[1] = (1U << ih->ih_pin);
sys/dev/fdt/qcspmi.c
614
®, 2);
sys/dev/fdt/qcspmi.c
625
uint8_t reg = (1U << ih->ih_pin);
sys/dev/fdt/qcspmi.c
629
(ih->ih_per << 8) | INTR_EN_CLR, ®, sizeof(reg));
sys/dev/fdt/qcspmi.c
649
uint8_t reg;
sys/dev/fdt/qcspmi.c
672
reg = 1U << ih->ih_pin;
sys/dev/fdt/qcspmi.c
675
®, sizeof(reg));
sys/dev/fdt/qctsens.c
111
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh_conf, TSENS_CTRL);
sys/dev/fdt/qctsens.c
112
if ((reg & TSENS_CTRL_EN) == 0)
sys/dev/fdt/qctsens.c
128
uint32_t phandle, reg;
sys/dev/fdt/qctsens.c
137
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh_conf, TSENS_CTRL);
sys/dev/fdt/qctsens.c
154
if ((reg & TSENS_CTRL_Sn_EN(sidx)) == 0)
sys/dev/fdt/qctsens.c
174
int32_t reg, temp;
sys/dev/fdt/qctsens.c
180
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/fdt/qctsens.c
182
temp = TSENS_Sn_TEMP(reg);
sys/dev/fdt/qctsens.c
183
if (reg & TSENS_Sn_VALID) {
sys/dev/fdt/qctsens.c
197
int32_t reg, temp;
sys/dev/fdt/qctsens.c
199
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, TSENS_Sn_STATUS(id));
sys/dev/fdt/qctsens.c
200
temp = 273150000 + 100000 * TSENS_Sn_TEMP(reg);
sys/dev/fdt/qctsens.c
202
if (reg & TSENS_Sn_VALID)
sys/dev/fdt/qctsens.c
89
uint32_t reg;
sys/dev/fdt/qcuart_fdt.c
40
struct fdt_reg reg;
sys/dev/fdt/qcuart_fdt.c
46
if (fdt_get_reg(node, 0, ®))
sys/dev/fdt/qcuart_fdt.c
49
qcuartcnattach(fdt_cons_bs_tag, reg.addr);
sys/dev/fdt/rkclock.c
1212
uint32_t reg, mux, div_con;
sys/dev/fdt/rkclock.c
1215
reg = HREAD4(sc, RK3308_CRU_CLKSEL_CON(0));
sys/dev/fdt/rkclock.c
1216
mux = (reg & RK3308_CRU_CORE_CLK_PLL_SEL_MASK) >>
sys/dev/fdt/rkclock.c
1218
div_con = (reg & RK3308_CRU_CLK_CORE_DIV_CON_MASK) >>
sys/dev/fdt/rkclock.c
1228
uint32_t reg, mux;
sys/dev/fdt/rkclock.c
1236
reg = HREAD4(sc, RK3308_CRU_CLKSEL_CON(0));
sys/dev/fdt/rkclock.c
1237
mux = (reg & RK3308_CRU_CORE_CLK_PLL_SEL_MASK) >>
sys/dev/fdt/rkclock.c
1285
uint32_t reg;
sys/dev/fdt/rkclock.c
1287
reg = HREAD4(sc, base + 0x0000);
sys/dev/fdt/rkclock.c
1288
postdiv1 = (reg & RK3308_CRU_PLL_POSTDIV1_MASK) >>
sys/dev/fdt/rkclock.c
1290
fbdiv = (reg & RK3308_CRU_PLL_FBDIV_MASK) >>
sys/dev/fdt/rkclock.c
1292
reg = HREAD4(sc, base + 0x0004);
sys/dev/fdt/rkclock.c
1293
dsmpd = (reg & RK3308_CRU_PLL_DSMPD);
sys/dev/fdt/rkclock.c
1294
postdiv2 = (reg & RK3308_CRU_PLL_POSTDIV2_MASK) >>
sys/dev/fdt/rkclock.c
1296
refdiv = (reg & RK3308_CRU_PLL_REFDIV_MASK) >>
sys/dev/fdt/rkclock.c
1298
reg = HREAD4(sc, base + 0x0008);
sys/dev/fdt/rkclock.c
1299
fracdiv = (reg & RK3308_CRU_PLL_FRACDIV_MASK) >>
sys/dev/fdt/rkclock.c
1448
uint32_t reg, mux, pll, div_con;
sys/dev/fdt/rkclock.c
1450
reg = HREAD4(sc, RK3308_CRU_CLKSEL_CON(2));
sys/dev/fdt/rkclock.c
1451
mux = (reg & 0x300) >> 8;
sys/dev/fdt/rkclock.c
1457
if ((reg >> 10) & 1)
sys/dev/fdt/rkclock.c
1828
uint32_t reg, mux, div_con;
sys/dev/fdt/rkclock.c
1831
reg = HREAD4(sc, RK3328_CRU_CLKSEL_CON(0));
sys/dev/fdt/rkclock.c
1832
mux = (reg & RK3328_CRU_CORE_CLK_PLL_SEL_MASK) >>
sys/dev/fdt/rkclock.c
1834
div_con = (reg & RK3328_CRU_CLK_CORE_DIV_CON_MASK) >>
sys/dev/fdt/rkclock.c
1844
uint32_t reg, mux;
sys/dev/fdt/rkclock.c
1852
reg = HREAD4(sc, RK3328_CRU_CLKSEL_CON(0));
sys/dev/fdt/rkclock.c
1853
mux = (reg & RK3328_CRU_CORE_CLK_PLL_SEL_MASK) >>
sys/dev/fdt/rkclock.c
1903
uint32_t reg;
sys/dev/fdt/rkclock.c
1905
reg = HREAD4(sc, base + 0x0000);
sys/dev/fdt/rkclock.c
1906
postdiv1 = (reg & RK3328_CRU_PLL_POSTDIV1_MASK) >>
sys/dev/fdt/rkclock.c
1908
fbdiv = (reg & RK3328_CRU_PLL_FBDIV_MASK) >>
sys/dev/fdt/rkclock.c
1910
reg = HREAD4(sc, base + 0x0004);
sys/dev/fdt/rkclock.c
1911
dsmpd = (reg & RK3328_CRU_PLL_DSMPD);
sys/dev/fdt/rkclock.c
1912
postdiv2 = (reg & RK3328_CRU_PLL_POSTDIV2_MASK) >>
sys/dev/fdt/rkclock.c
1914
refdiv = (reg & RK3328_CRU_PLL_REFDIV_MASK) >>
sys/dev/fdt/rkclock.c
1916
reg = HREAD4(sc, base + 0x0008);
sys/dev/fdt/rkclock.c
1917
fracdiv = (reg & RK3328_CRU_PLL_FRACDIV_MASK) >>
sys/dev/fdt/rkclock.c
2035
uint32_t reg;
sys/dev/fdt/rkclock.c
2110
reg = HREAD4(sc, base + 0x0008);
sys/dev/fdt/rkclock.c
2111
reg &= ~RK3328_CRU_PLL_FRACDIV_MASK;
sys/dev/fdt/rkclock.c
2112
reg |= fracdiv << RK3328_CRU_PLL_FRACDIV_SHIFT;
sys/dev/fdt/rkclock.c
2113
HWRITE4(sc, base + 0x0008, reg);
sys/dev/fdt/rkclock.c
2132
uint32_t reg;
sys/dev/fdt/rkclock.c
2161
reg = regmap_read_4(sc->sc_grf, RK3328_GRF_MAC_CON1);
sys/dev/fdt/rkclock.c
2162
if (reg & RK3328_GRF_GMAC2IO_RMII_EXTCLK_SEL)
sys/dev/fdt/rkclock.c
2179
uint32_t reg, mux;
sys/dev/fdt/rkclock.c
2201
reg = HREAD4(sc, RK3328_CRU_CLKSEL_CON(40));
sys/dev/fdt/rkclock.c
2202
mux = (reg & RK3328_CRU_VOP_DCLK_SRC_SEL_MASK) >>
sys/dev/fdt/rkclock.c
244
uint32_t reg;
sys/dev/fdt/rkclock.c
257
#define HREAD4(sc, reg) \
sys/dev/fdt/rkclock.c
258
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/rkclock.c
259
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkclock.c
260
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkclock.c
261
#define HSET4(sc, reg, bits) \
sys/dev/fdt/rkclock.c
262
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/rkclock.c
263
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/rkclock.c
2634
uint32_t reg;
sys/dev/fdt/rkclock.c
2636
reg = HREAD4(sc, base + 0x000c);
sys/dev/fdt/rkclock.c
2637
pll_work_mode = reg & RK3399_CRU_PLL_PLL_WORK_MODE_MASK;
sys/dev/fdt/rkclock.c
264
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/rkclock.c
2643
reg = HREAD4(sc, base + 0x0000);
sys/dev/fdt/rkclock.c
2644
fbdiv = (reg & RK3399_CRU_PLL_FBDIV_MASK) >>
sys/dev/fdt/rkclock.c
2646
reg = HREAD4(sc, base + 0x0004);
sys/dev/fdt/rkclock.c
2647
postdiv2 = (reg & RK3399_CRU_PLL_POSTDIV2_MASK) >>
sys/dev/fdt/rkclock.c
2649
postdiv1 = (reg & RK3399_CRU_PLL_POSTDIV1_MASK) >>
sys/dev/fdt/rkclock.c
2651
refdiv = (reg & RK3399_CRU_PLL_REFDIV_MASK) >>
sys/dev/fdt/rkclock.c
2780
uint32_t reg, mux, div_con;
sys/dev/fdt/rkclock.c
2783
reg = HREAD4(sc, clksel);
sys/dev/fdt/rkclock.c
2784
mux = (reg & RK3399_CRU_CORE_PLL_SEL_MASK) >>
sys/dev/fdt/rkclock.c
2786
div_con = (reg & RK3399_CRU_CLK_CORE_DIV_CON_MASK) >>
sys/dev/fdt/rkclock.c
2796
uint32_t reg, mux;
sys/dev/fdt/rkclock.c
2804
reg = HREAD4(sc, clksel);
sys/dev/fdt/rkclock.c
2805
mux = (reg & RK3399_CRU_CORE_PLL_SEL_MASK) >>
sys/dev/fdt/rkclock.c
3346
uint32_t bit, mask, reg;
sys/dev/fdt/rkclock.c
3350
reg = RK3528_CRU_SOFTRST_CON(25);
sys/dev/fdt/rkclock.c
3354
reg = RK3528_CRU_SOFTRST_CON(26);
sys/dev/fdt/rkclock.c
3358
reg = RK3528_CRU_SOFTRST_CON(26);
sys/dev/fdt/rkclock.c
3362
reg = RK3528_CRU_SOFTRST_CON(26);
sys/dev/fdt/rkclock.c
3366
reg = RK3528_CRU_SOFTRST_CON(26);
sys/dev/fdt/rkclock.c
3370
reg = RK3528_CRU_SOFTRST_CON(28);
sys/dev/fdt/rkclock.c
3374
reg = RK3528_CRU_SOFTRST_CON(30);
sys/dev/fdt/rkclock.c
3378
reg = RK3528_CRU_SOFTRST_CON(30);
sys/dev/fdt/rkclock.c
3382
reg = RK3528_CRU_SOFTRST_CON(30);
sys/dev/fdt/rkclock.c
3386
reg = RK3528_CRU_SOFTRST_CON(30);
sys/dev/fdt/rkclock.c
3390
reg = RK3528_CRU_SOFTRST_CON(42);
sys/dev/fdt/rkclock.c
3399
HWRITE4(sc, reg, mask << 16 | (on ? mask : 0));
sys/dev/fdt/rkclock.c
4415
uint32_t bit, mask, reg;
sys/dev/fdt/rkclock.c
4419
reg = RK3576_CRU_SOFTRST_CON(34);
sys/dev/fdt/rkclock.c
4423
reg = RK3576_CRU_SOFTRST_CON(34);
sys/dev/fdt/rkclock.c
4427
reg = RK3576_CRU_SOFTRST_CON(35);
sys/dev/fdt/rkclock.c
4431
reg = RK3576_CRU_SOFTRST_CON(42);
sys/dev/fdt/rkclock.c
4435
reg = RK3576_CRU_SOFTRST_CON(43);
sys/dev/fdt/rkclock.c
4439
reg = RK3576_CRU_SOFTRST_CON(47);
sys/dev/fdt/rkclock.c
4443
reg = RK3576_PHPTOPCRU_SOFTRST_CON(0);
sys/dev/fdt/rkclock.c
4447
reg = RK3576_PHPTOPCRU_SOFTRST_CON(0);
sys/dev/fdt/rkclock.c
4451
reg = RK3576_PHPTOPCRU_SOFTRST_CON(1);
sys/dev/fdt/rkclock.c
4455
reg = RK3576_PHPTOPCRU_SOFTRST_CON(1);
sys/dev/fdt/rkclock.c
4464
HWRITE4(sc, reg, mask << 16 | (on ? mask : 0));
sys/dev/fdt/rkclock.c
5045
uint32_t reg;
sys/dev/fdt/rkclock.c
5047
reg = HREAD4(sc, base);
sys/dev/fdt/rkclock.c
5048
m = (reg & RK3588_CRU_PLL_M_MASK) >> RK3588_CRU_PLL_M_SHIFT;
sys/dev/fdt/rkclock.c
5049
reg = HREAD4(sc, base + 4);
sys/dev/fdt/rkclock.c
5050
p = (reg & RK3588_CRU_PLL_P_MASK) >> RK3588_CRU_PLL_P_SHIFT;
sys/dev/fdt/rkclock.c
5051
s = (reg & RK3588_CRU_PLL_S_MASK) >> RK3588_CRU_PLL_S_SHIFT;
sys/dev/fdt/rkclock.c
5052
reg = HREAD4(sc, base + 8);
sys/dev/fdt/rkclock.c
5053
k = (reg & RK3588_CRU_PLL_K_MASK) >> RK3588_CRU_PLL_K_SHIFT;
sys/dev/fdt/rkclock.c
5133
uint32_t bit, mask, reg;
sys/dev/fdt/rkclock.c
5137
reg = RK3588_CRU_SOFTRST_CON(2);
sys/dev/fdt/rkclock.c
5141
reg = RK3588_CRU_SOFTRST_CON(2);
sys/dev/fdt/rkclock.c
5145
reg = RK3588_CRU_SOFTRST_CON(2);
sys/dev/fdt/rkclock.c
5149
reg = RK3588_CRU_SOFTRST_CON(2);
sys/dev/fdt/rkclock.c
5153
reg = RK3588_CRU_SOFTRST_CON(2);
sys/dev/fdt/rkclock.c
5157
reg = RK3588_CRU_SOFTRST_CON(3);
sys/dev/fdt/rkclock.c
5161
reg = RK3588_CRU_SOFTRST_CON(3);
sys/dev/fdt/rkclock.c
5165
reg = RK3588_CRU_SOFTRST_CON(3);
sys/dev/fdt/rkclock.c
5169
reg = RK3588_CRU_SOFTRST_CON(12);
sys/dev/fdt/rkclock.c
5173
reg = RK3588_CRU_SOFTRST_CON(12);
sys/dev/fdt/rkclock.c
5177
reg = RK3588_CRU_SOFTRST_CON(31);
sys/dev/fdt/rkclock.c
5181
reg = RK3588_CRU_SOFTRST_CON(31);
sys/dev/fdt/rkclock.c
5185
reg = RK3588_CRU_SOFTRST_CON(31);
sys/dev/fdt/rkclock.c
5189
reg = RK3588_CRU_SOFTRST_CON(31);
sys/dev/fdt/rkclock.c
5193
reg = RK3588_CRU_SOFTRST_CON(31);
sys/dev/fdt/rkclock.c
5197
reg = RK3588_CRU_SOFTRST_CON(32);
sys/dev/fdt/rkclock.c
5201
reg = RK3588_CRU_SOFTRST_CON(32);
sys/dev/fdt/rkclock.c
5205
reg = RK3588_CRU_SOFTRST_CON(32);
sys/dev/fdt/rkclock.c
5209
reg = RK3588_CRU_SOFTRST_CON(32);
sys/dev/fdt/rkclock.c
5213
reg = RK3588_CRU_SOFTRST_CON(32);
sys/dev/fdt/rkclock.c
5217
reg = RK3588_CRU_SOFTRST_CON(33);
sys/dev/fdt/rkclock.c
5221
reg = RK3588_CRU_SOFTRST_CON(33);
sys/dev/fdt/rkclock.c
5225
reg = RK3588_CRU_SOFTRST_CON(33);
sys/dev/fdt/rkclock.c
5229
reg = RK3588_CRU_SOFTRST_CON(33);
sys/dev/fdt/rkclock.c
5233
reg = RK3588_CRU_SOFTRST_CON(33);
sys/dev/fdt/rkclock.c
5237
reg = RK3588_CRU_SOFTRST_CON(33);
sys/dev/fdt/rkclock.c
5241
reg = RK3588_CRU_SOFTRST_CON(34);
sys/dev/fdt/rkclock.c
5245
reg = RK3588_CRU_SOFTRST_CON(35);
sys/dev/fdt/rkclock.c
5249
reg = RK3588_CRU_SOFTRST_CON(42);
sys/dev/fdt/rkclock.c
5253
reg = RK3588_CRU_SOFTRST_CON(42);
sys/dev/fdt/rkclock.c
5257
reg = RK3588_CRU_SOFTRST_CON(72);
sys/dev/fdt/rkclock.c
5261
reg = RK3588_CRU_SOFTRST_CON(72);
sys/dev/fdt/rkclock.c
5265
reg = RK3588_CRU_SOFTRST_CON(72);
sys/dev/fdt/rkclock.c
5269
reg = RK3588_CRU_SOFTRST_CON(72);
sys/dev/fdt/rkclock.c
5273
reg = RK3588_CRU_SOFTRST_CON(77);
sys/dev/fdt/rkclock.c
5277
reg = RK3588_CRU_SOFTRST_CON(77);
sys/dev/fdt/rkclock.c
5281
reg = RK3588_CRU_SOFTRST_CON(77);
sys/dev/fdt/rkclock.c
5285
reg = RK3588_PHPTOPCRU_SOFTRST_CON(0);
sys/dev/fdt/rkclock.c
5289
reg = RK3588_PHPTOPCRU_SOFTRST_CON(0);
sys/dev/fdt/rkclock.c
5293
reg = RK3588_PHPTOPCRU_SOFTRST_CON(0);
sys/dev/fdt/rkclock.c
5297
reg = RK3588_PHPTOPCRU_SOFTRST_CON(0);
sys/dev/fdt/rkclock.c
5306
HWRITE4(sc, reg, mask << 16 | (on ? mask : 0));
sys/dev/fdt/rkclock.c
575
uint32_t reg, mux, div_con;
sys/dev/fdt/rkclock.c
584
reg = HREAD4(sc, clk->reg);
sys/dev/fdt/rkclock.c
589
mux = (reg & clk->sel_mask) >> shift;
sys/dev/fdt/rkclock.c
594
div_con = (reg & clk->div_mask) >> shift;
sys/dev/fdt/rkclock.c
608
uint32_t reg, mux, div_con;
sys/dev/fdt/rkclock.c
620
reg = HREAD4(sc, clk->reg);
sys/dev/fdt/rkclock.c
625
mux = (reg & clk->sel_mask) >> sel_shift;
sys/dev/fdt/rkclock.c
665
HWRITE4(sc, clk->reg,
sys/dev/fdt/rkclock.c
696
HWRITE4(sc, clk->reg,
sys/dev/fdt/rkclock.c
725
HWRITE4(sc, clk->reg, clk->sel_mask << 16 | mux << shift);
sys/dev/fdt/rkclock.c
771
uint32_t reg;
sys/dev/fdt/rkclock.c
773
reg = HREAD4(sc, base);
sys/dev/fdt/rkclock.c
774
clkod = (reg & RK3288_CRU_PLL_CLKOD_MASK) >>
sys/dev/fdt/rkclock.c
776
clkr = (reg & RK3288_CRU_PLL_CLKR_MASK) >>
sys/dev/fdt/rkclock.c
778
reg = HREAD4(sc, base + 4);
sys/dev/fdt/rkclock.c
779
clkf = (reg & RK3288_CRU_PLL_CLKF_MASK) >>
sys/dev/fdt/rkclock.c
869
uint32_t reg, mux, div_con, aclk_div_con;
sys/dev/fdt/rkclock.c
881
reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(0));
sys/dev/fdt/rkclock.c
882
mux = (reg >> 15) & 0x1;
sys/dev/fdt/rkclock.c
883
div_con = (reg >> 8) & 0x1f;
sys/dev/fdt/rkclock.c
889
reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(13));
sys/dev/fdt/rkclock.c
890
mux = (reg >> 8) & 0x3;
sys/dev/fdt/rkclock.c
891
div_con = reg & 0x7f;
sys/dev/fdt/rkclock.c
896
reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(14));
sys/dev/fdt/rkclock.c
897
mux = (reg >> 8) & 0x3;
sys/dev/fdt/rkclock.c
898
div_con = reg & 0x7f;
sys/dev/fdt/rkclock.c
903
reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(15));
sys/dev/fdt/rkclock.c
904
mux = (reg >> 8) & 0x3;
sys/dev/fdt/rkclock.c
905
div_con = reg & 0x7f;
sys/dev/fdt/rkclock.c
910
reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(16));
sys/dev/fdt/rkclock.c
911
mux = (reg >> 8) & 0x3;
sys/dev/fdt/rkclock.c
912
div_con = reg & 0x7f;
sys/dev/fdt/rkclock.c
917
reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(3));
sys/dev/fdt/rkclock.c
918
mux = (reg >> 8) & 0x3;
sys/dev/fdt/rkclock.c
919
div_con = reg & 0x7f;
sys/dev/fdt/rkclock.c
924
reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(21));
sys/dev/fdt/rkclock.c
925
if (reg & 0x10)
sys/dev/fdt/rkclock.c
927
mux = (reg >> 0) & 0x3;
sys/dev/fdt/rkclock.c
928
div_con = (reg >> 8) & 0x1f;
sys/dev/fdt/rkclock.c
945
reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(1));
sys/dev/fdt/rkclock.c
946
mux = (reg >> 15) & 0x1;
sys/dev/fdt/rkclock.c
948
div_con = (reg >> 12) & 0x7;
sys/dev/fdt/rkclock.c
958
reg = HREAD4(sc, RK3288_CRU_CLKSEL_CON(10));
sys/dev/fdt/rkclock.c
959
mux = (reg >> 15) & 0x1;
sys/dev/fdt/rkclock.c
961
div_con = (reg >> 12) & 0x3;
sys/dev/fdt/rkclock.c
963
aclk_div_con = reg & 0xf;
sys/dev/fdt/rkcomphy.c
103
#define HREAD4(sc, reg) \
sys/dev/fdt/rkcomphy.c
104
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/rkcomphy.c
105
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkcomphy.c
106
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkcomphy.c
107
#define HSET4(sc, reg, bits) \
sys/dev/fdt/rkcomphy.c
108
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/rkcomphy.c
109
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/rkcomphy.c
110
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/rkcomphy.c
183
uint32_t reg;
sys/dev/fdt/rkcomphy.c
185
reg = HREAD4(sc, COMBO_PIPE_PHY_REG(5));
sys/dev/fdt/rkcomphy.c
186
reg |= COMBO_PIPE_PHY_GATE_TX_PCK_DLY_PLL_OFF;
sys/dev/fdt/rkcomphy.c
187
HWRITE4(sc, COMBO_PIPE_PHY_REG(5), reg);
sys/dev/fdt/rkcomphy.c
189
reg = HREAD4(sc, COMBO_PIPE_PHY_REG(6));
sys/dev/fdt/rkcomphy.c
190
reg &= ~COMBO_PIPE_PHY_PLL_KVCO_MASK_RK3528;
sys/dev/fdt/rkcomphy.c
191
reg |= COMBO_PIPE_PHY_PLL_KVCO_VALUE_RK3528;
sys/dev/fdt/rkcomphy.c
192
HWRITE4(sc, COMBO_PIPE_PHY_REG(6), reg);
sys/dev/fdt/rkcomphy.c
205
uint32_t grf, phy_grf, reg;
sys/dev/fdt/rkcomphy.c
228
reg = HREAD4(sc, COMBO_PIPE_PHY_REG(6));
sys/dev/fdt/rkcomphy.c
229
reg &= ~COMBO_PIPE_PHY_SSC_OFFSET_MASK;
sys/dev/fdt/rkcomphy.c
230
reg &= ~COMBO_PIPE_PHY_SSC_DIR_MASK;
sys/dev/fdt/rkcomphy.c
231
reg |= COMBO_PIPE_PHY_SSC_DIR_DOWN;
sys/dev/fdt/rkcomphy.c
232
HWRITE4(sc, COMBO_PIPE_PHY_REG(6), reg);
sys/dev/fdt/rkcomphy.c
256
uint32_t reg;
sys/dev/fdt/rkcomphy.c
258
reg = HREAD4(sc, COMBO_PIPE_PHY_REG(32));
sys/dev/fdt/rkcomphy.c
259
reg &= ~COMBO_PIPE_PHY_PLL_KVCO_MASK;
sys/dev/fdt/rkcomphy.c
260
reg |= COMBO_PIPE_PHY_PLL_KVCO_VALUE;
sys/dev/fdt/rkcomphy.c
261
HWRITE4(sc, COMBO_PIPE_PHY_REG(32), reg);
sys/dev/fdt/rkcomphy.c
265
reg = HREAD4(sc, COMBO_PIPE_PHY_REG(5));
sys/dev/fdt/rkcomphy.c
266
reg &= ~COMBO_PIPE_PHY_PLL_DIV_MASK;
sys/dev/fdt/rkcomphy.c
267
reg |= COMBO_PIPE_PHY_PLL_DIV_2;
sys/dev/fdt/rkcomphy.c
268
HWRITE4(sc, COMBO_PIPE_PHY_REG(5), reg);
sys/dev/fdt/rkcomphy.c
281
uint32_t freq, grf, phy_grf, reg;
sys/dev/fdt/rkcomphy.c
308
reg = HREAD4(sc, COMBO_PIPE_PHY_REG(31));
sys/dev/fdt/rkcomphy.c
309
reg &= ~COMBO_PIPE_PHY_SSC_OFFSET_MASK;
sys/dev/fdt/rkcomphy.c
310
reg &= ~COMBO_PIPE_PHY_SSC_DIR_MASK;
sys/dev/fdt/rkcomphy.c
311
reg |= COMBO_PIPE_PHY_SSC_DIR_DOWN;
sys/dev/fdt/rkcomphy.c
312
HWRITE4(sc, COMBO_PIPE_PHY_REG(31), reg);
sys/dev/fdt/rkcomphy.c
316
reg = HREAD4(sc, COMBO_PIPE_PHY_REG(14));
sys/dev/fdt/rkcomphy.c
317
reg |= COMBO_PIPE_PHY_CTLE_EN;
sys/dev/fdt/rkcomphy.c
318
HWRITE4(sc, COMBO_PIPE_PHY_REG(14), reg);
sys/dev/fdt/rkcomphy.c
359
reg = HREAD4(sc, COMBO_PIPE_PHY_REG(14));
sys/dev/fdt/rkcomphy.c
360
reg &= ~COMBO_PIPE_PHY_SSC_CNT_LO_MASK;
sys/dev/fdt/rkcomphy.c
361
reg |= COMBO_PIPE_PHY_SSC_CNT_LO_VALUE;
sys/dev/fdt/rkcomphy.c
362
HWRITE4(sc, COMBO_PIPE_PHY_REG(14), reg);
sys/dev/fdt/rkcomphy.c
363
reg = HREAD4(sc, COMBO_PIPE_PHY_REG(15));
sys/dev/fdt/rkcomphy.c
364
reg &= ~COMBO_PIPE_PHY_SSC_CNT_HI_MASK;
sys/dev/fdt/rkcomphy.c
365
reg |= COMBO_PIPE_PHY_SSC_CNT_HI_VALUE;
sys/dev/fdt/rkcomphy.c
366
HWRITE4(sc, COMBO_PIPE_PHY_REG(15), reg);
sys/dev/fdt/rkcomphy.c
381
reg = HREAD4(sc, COMBO_PIPE_PHY_REG(31));
sys/dev/fdt/rkcomphy.c
382
reg &= ~COMBO_PIPE_PHY_SSC_OFFSET_MASK;
sys/dev/fdt/rkcomphy.c
383
reg |= COMBO_PIPE_PHY_SSC_OFFSET_500PPM;
sys/dev/fdt/rkcomphy.c
384
reg &= ~COMBO_PIPE_PHY_SSC_DIR_MASK;
sys/dev/fdt/rkcomphy.c
385
reg |= COMBO_PIPE_PHY_SSC_DIR_DOWN;
sys/dev/fdt/rkcomphy.c
386
HWRITE4(sc, COMBO_PIPE_PHY_REG(31), reg);
sys/dev/fdt/rkcomphy.c
414
uint32_t reg;
sys/dev/fdt/rkcomphy.c
416
reg = HREAD4(sc, COMBO_PIPE_PHY_REG(32));
sys/dev/fdt/rkcomphy.c
417
reg &= ~COMBO_PIPE_PHY_PLL_KVCO_MASK;
sys/dev/fdt/rkcomphy.c
418
reg |= COMBO_PIPE_PHY_PLL_KVCO_VALUE_RK3588;
sys/dev/fdt/rkcomphy.c
419
HWRITE4(sc, COMBO_PIPE_PHY_REG(32), reg);
sys/dev/fdt/rkemmcphy.c
126
uint32_t impedance, freqsel, freq, reg;
sys/dev/fdt/rkemmcphy.c
182
reg = HREAD4(sc, GRF_EMMCPHY_STATUS);
sys/dev/fdt/rkemmcphy.c
183
if (reg & GRF_EMMCPHY_STATUS_CALDONE)
sys/dev/fdt/rkemmcphy.c
196
reg = HREAD4(sc, GRF_EMMCPHY_STATUS);
sys/dev/fdt/rkemmcphy.c
197
if (reg & GRF_EMMCPHY_STATUS_DLLRDY)
sys/dev/fdt/rkemmcphy.c
62
#define HREAD4(sc, reg) \
sys/dev/fdt/rkemmcphy.c
63
(regmap_read_4((sc)->sc_rm, (sc)->sc_off + (reg)))
sys/dev/fdt/rkemmcphy.c
64
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkemmcphy.c
65
regmap_write_4((sc)->sc_rm, (sc)->sc_off + (reg), (val))
sys/dev/fdt/rkgpio.c
210
uint32_t reg;
sys/dev/fdt/rkgpio.c
216
reg = (1 << (pin % 16)) << 16;
sys/dev/fdt/rkgpio.c
218
reg |= (1 << (pin % 16));
sys/dev/fdt/rkgpio.c
219
HWRITE4(sc, GPIO_SWPORT_DDR_L + (pin / 16) * 4, reg);
sys/dev/fdt/rkgpio.c
234
uint32_t reg;
sys/dev/fdt/rkgpio.c
241
reg = HREAD4(sc, GPIO_EXT_PORT);
sys/dev/fdt/rkgpio.c
243
reg = HREAD4(sc, GPIO_EXT_PORTA);
sys/dev/fdt/rkgpio.c
244
val = (reg >> pin) & 1;
sys/dev/fdt/rkgpio.c
256
uint32_t reg;
sys/dev/fdt/rkgpio.c
264
reg = (1 << (pin % 16)) << 16;
sys/dev/fdt/rkgpio.c
266
reg |= (1 << (pin % 16));
sys/dev/fdt/rkgpio.c
267
HWRITE4(sc, GPIO_SWPORT_DR_L + (pin / 16) * 4, reg);
sys/dev/fdt/rkgpio.c
71
#define HREAD4(sc, reg) \
sys/dev/fdt/rkgpio.c
72
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/rkgpio.c
73
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkgpio.c
74
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkgpio.c
75
#define HSET4(sc, reg, bits) \
sys/dev/fdt/rkgpio.c
76
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/rkgpio.c
77
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/rkgpio.c
78
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/rkiic.c
380
uint32_t reg[1];
sys/dev/fdt/rkiic.c
385
memset(reg, 0, sizeof(reg));
sys/dev/fdt/rkiic.c
395
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/dev/fdt/rkiic.c
400
ia.ia_addr = bemtoh32(®[0]);
sys/dev/fdt/rkiic.c
69
#define HREAD4(sc, reg) \
sys/dev/fdt/rkiic.c
70
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/rkiic.c
71
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkiic.c
72
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkiic.c
73
#define HSET4(sc, reg, bits) \
sys/dev/fdt/rkiic.c
74
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/rkiic.c
75
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/rkiic.c
76
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/rkiis.c
131
#define HREAD4(sc, reg) \
sys/dev/fdt/rkiis.c
132
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/rkiis.c
133
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkiis.c
134
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkiis.c
135
#define HSET4(sc, reg, bits) \
sys/dev/fdt/rkiis.c
136
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/rkiis.c
137
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/rkiis.c
138
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/rkpcie.c
524
rkpcie_conf_read(void *v, pcitag_t tag, int reg)
sys/dev/fdt/rkpcie.c
532
return HREAD4(sc, PCIE_RC_NORMAL_BASE + tag | reg);
sys/dev/fdt/rkpcie.c
536
return bus_space_read_4(sc->sc_iot, sc->sc_axi_ioh, tag | reg);
sys/dev/fdt/rkpcie.c
543
rkpcie_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
sys/dev/fdt/rkpcie.c
551
HWRITE4(sc, PCIE_RC_NORMAL_BASE + tag | reg, data);
sys/dev/fdt/rkpcie.c
556
bus_space_write_4(sc->sc_iot, sc->sc_axi_ioh, tag | reg, data);
sys/dev/fdt/rkpcie.c
91
#define HREAD4(sc, reg) \
sys/dev/fdt/rkpcie.c
92
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/rkpcie.c
93
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkpcie.c
94
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkpciephy.c
167
uint32_t grf, reg, stat;
sys/dev/fdt/rkpciephy.c
189
reg = RK3588_GRF_PCIE3PHY_LANE_MASK;
sys/dev/fdt/rkpciephy.c
194
reg |= RK3588_GRF_PCIE3PHY_LANE_AGGREGATE;
sys/dev/fdt/rkpciephy.c
198
reg |= RK3588_GRF_PCIE3PHY_LANE_BIFURCATE_0_1;
sys/dev/fdt/rkpciephy.c
201
reg |= RK3588_GRF_PCIE3PHY_LANE_BIFURCATE_2_3;
sys/dev/fdt/rkpciephy.c
203
regmap_write_4(phy, RK3588_PCIE3PHY_GRF_CMN_CON(0), reg);
sys/dev/fdt/rkpciephy.c
208
reg = RK3588_PHP_GRF_PCIE0L0_MASK | RK3588_PHP_GRF_PCIE0L1_MASK;
sys/dev/fdt/rkpciephy.c
211
reg |= RK3588_PHP_GRF_PCIE0L0_PCIE3;
sys/dev/fdt/rkpciephy.c
214
reg |= RK3588_PHP_GRF_PCIE0L1_PCIE3;
sys/dev/fdt/rkpciephy.c
215
regmap_write_4(pipe, RK3588_PHP_GRF_PCIESEL_CON, reg);
sys/dev/fdt/rkpinctrl.c
1157
regmap_write_4(rm, route->reg, route->val);
sys/dev/fdt/rkpinctrl.c
121
uint16_t reg;
sys/dev/fdt/rkpmic.c
737
uint8_t reg, vsel;
sys/dev/fdt/rkpmic.c
769
reg = rkpmic_reg_read(rr->rr_sc, rr->rr_vreg + sleep);
sys/dev/fdt/rkpmic.c
770
reg &= ~rr->rr_vmask;
sys/dev/fdt/rkpmic.c
771
reg |= vsel;
sys/dev/fdt/rkpmic.c
772
rkpmic_reg_write(rr->rr_sc, rr->rr_vreg + sleep, reg);
sys/dev/fdt/rkpmic.c
838
rkpmic_reg_read(struct rkpmic_softc *sc, int reg)
sys/dev/fdt/rkpmic.c
840
uint8_t cmd = reg;
sys/dev/fdt/rkpmic.c
845
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/rkpmic.c
853
rkpmic_reg_write(struct rkpmic_softc *sc, int reg, uint8_t val)
sys/dev/fdt/rkpmic.c
855
uint8_t cmd = reg;
sys/dev/fdt/rkpmic.c
859
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/rkpwm.c
44
#define HREAD4(sc, reg) \
sys/dev/fdt/rkpwm.c
45
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/rkpwm.c
46
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkpwm.c
47
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkpwm.c
48
#define HSET4(sc, reg, bits) \
sys/dev/fdt/rkpwm.c
49
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/rkpwm.c
50
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/rkpwm.c
51
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/rkrng.c
74
#define HREAD4(sc, reg) \
sys/dev/fdt/rkrng.c
75
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/rkrng.c
76
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkrng.c
77
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkspi.c
118
#define HREAD4(sc, reg) \
sys/dev/fdt/rkspi.c
119
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/rkspi.c
120
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkspi.c
121
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkspi.c
122
#define HSET4(sc, reg, bits) \
sys/dev/fdt/rkspi.c
123
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/rkspi.c
124
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/rkspi.c
125
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/rkspi.c
345
uint32_t reg[1];
sys/dev/fdt/rkspi.c
351
memset(reg, 0, sizeof(reg));
sys/dev/fdt/rkspi.c
358
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/dev/fdt/rktcphy.c
104
#define HREAD4(sc, reg) \
sys/dev/fdt/rktcphy.c
105
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/rktcphy.c
106
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rktcphy.c
107
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rktcphy.c
108
#define HSET4(sc, reg, bits) \
sys/dev/fdt/rktcphy.c
109
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/rktcphy.c
110
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/rktcphy.c
111
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/rktcphy.c
212
uint32_t reg;
sys/dev/fdt/rktcphy.c
215
reg = regmap_read_4(sc->sc_grf, GRF_USB3PHY_CON0(sc->sc_phy_ctrl_id));
sys/dev/fdt/rktcphy.c
217
reg |= USB3PHY_CON0_USB2_ONLY;
sys/dev/fdt/rktcphy.c
219
reg &= ~USB3PHY_CON0_USB2_ONLY;
sys/dev/fdt/rktcphy.c
221
reg |= (USB3PHY_CON0_USB2_ONLY) << 16;
sys/dev/fdt/rktcphy.c
222
regmap_write_4(sc->sc_grf, GRF_USB3PHY_CON0(sc->sc_phy_ctrl_id), reg);
sys/dev/fdt/rktcphy.c
225
reg = regmap_read_4(sc->sc_grf, GRF_USB3OTG_CON1(sc->sc_phy_ctrl_id));
sys/dev/fdt/rktcphy.c
227
reg |= USB3OTG_CON1_U3_DIS;
sys/dev/fdt/rktcphy.c
229
reg &= ~USB3OTG_CON1_U3_DIS;
sys/dev/fdt/rktcphy.c
231
reg |= (USB3OTG_CON1_U3_DIS) << 16;
sys/dev/fdt/rktcphy.c
232
regmap_write_4(sc->sc_grf, GRF_USB3OTG_CON1(sc->sc_phy_ctrl_id), reg);
sys/dev/fdt/rktcphy.c
239
uint32_t reg;
sys/dev/fdt/rktcphy.c
256
reg = HREAD4(sc, CMN_DIAG_HSCLK_SEL);
sys/dev/fdt/rktcphy.c
257
reg &= ~CMN_DIAG_HSCLK_SEL_PLL_MASK;
sys/dev/fdt/rktcphy.c
258
reg |= CMN_DIAG_HSCLK_SEL_PLL_CONFIG;
sys/dev/fdt/rktcphy.c
259
HWRITE4(sc, CMN_DIAG_HSCLK_SEL, reg);
sys/dev/fdt/rktcphy.c
303
reg = HREAD4(sc, PMA_CMN_CTRL1);
sys/dev/fdt/rktcphy.c
304
if (reg & PMA_CMN_CTRL1_READY)
sys/dev/fdt/rktemp.c
79
#define HREAD4(sc, reg) \
sys/dev/fdt/rktemp.c
80
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/rktemp.c
81
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rktemp.c
82
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkusbdpphy.c
101
uint32_t reg;
sys/dev/fdt/rkusbdpphy.c
152
reg = HREAD4(sc, USBDP_COMBO_PHY_REG(0xa2));
sys/dev/fdt/rkusbdpphy.c
153
if ((reg & USBDP_COMBO_PHY_LANE_MUX_MASK) &&
sys/dev/fdt/rkusbdpphy.c
154
(reg & USBDP_COMBO_PHY_LANE_EN_MASK)) {
sys/dev/fdt/rkusbdpphy.c
212
uint16_t reg, val;
sys/dev/fdt/rkusbdpphy.c
299
rkusbdpphy_init_regs[i].reg),
sys/dev/fdt/rkusbdpphy.c
308
rkusbdpphy_24m_refclk_init_regs[i].reg),
sys/dev/fdt/rkusbdpphy.c
315
rkusbdpphy_26m_refclk_init_regs[i].reg),
sys/dev/fdt/rkusbdpphy.c
51
#define HREAD4(sc, reg) \
sys/dev/fdt/rkusbdpphy.c
52
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/rkusbdpphy.c
53
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkusbdpphy.c
54
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/rkusbdpphy.c
55
#define HSET4(sc, reg, bits) \
sys/dev/fdt/rkusbdpphy.c
56
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/rkusbdpphy.c
57
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/rkusbdpphy.c
58
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/rkvop.c
148
#define HREAD4(sc, reg) \
sys/dev/fdt/rkvop.c
149
bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
sys/dev/fdt/rkvop.c
150
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/rkvop.c
151
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/scmi.c
201
struct fdt_reg reg;
sys/dev/fdt/scmi.c
217
fdt_get_reg(node, 0, ®)) {
sys/dev/fdt/scmi.c
222
if (bus_space_map(sc->sc_iot, reg.addr,
sys/dev/fdt/scmi.c
223
reg.size, 0, &sc->sc_ioh_tx)) {
sys/dev/fdt/scmi.c
263
struct fdt_reg reg;
sys/dev/fdt/scmi.c
297
fdt_get_reg(node, 0, ®)) {
sys/dev/fdt/scmi.c
301
if (bus_space_map(sc->sc_iot, reg.addr, reg.size, 0, &sc->sc_ioh_tx)) {
sys/dev/fdt/scmi.c
309
fdt_get_reg(node, 0, ®)) {
sys/dev/fdt/scmi.c
313
if (bus_space_map(sc->sc_iot, reg.addr, reg.size, 0, &sc->sc_ioh_rx)) {
sys/dev/fdt/sdhc_fdt.c
147
uint32_t reg, phandle, freq;
sys/dev/fdt/sdhc_fdt.c
309
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/fdt/sdhc_fdt.c
311
reg |= XENON_SYS_OP_CTRL_SLOT_ENABLE(sc->sc_sdhc_id);
sys/dev/fdt/sdhc_fdt.c
312
reg &= ~XENON_SYS_OP_CTRL_SDCLK_IDLEOFF_ENABLE(sc->sc_sdhc_id);
sys/dev/fdt/sdhc_fdt.c
313
reg &= ~XENON_SYS_OP_CTRL_AUTO_CLKGATE_DISABLE;
sys/dev/fdt/sdhc_fdt.c
315
XENON_SYS_OP_CTRL, reg);
sys/dev/fdt/sdhc_fdt.c
316
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/fdt/sdhc_fdt.c
318
reg |= XENON_SYS_EXT_OP_CTRL_PARALLEL_TRAN(sc->sc_sdhc_id);
sys/dev/fdt/sdhc_fdt.c
319
reg |= XENON_SYS_EXT_OP_CTRL_MASK_CMD_CONFLICT_ERR;
sys/dev/fdt/sdhc_fdt.c
321
XENON_SYS_EXT_OP_CTRL, reg);
sys/dev/fdt/sdhc_fdt.c
373
uint32_t reg;
sys/dev/fdt/sdhc_fdt.c
379
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/fdt/sdhc_fdt.c
381
reg |= (XENON_EMMC_PHY_PAD_CONTROL_FC_DQ_RECEN |
sys/dev/fdt/sdhc_fdt.c
387
XENON_EMMC_PHY_PAD_CONTROL, reg);
sys/dev/fdt/sdhc_fdt.c
388
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/fdt/sdhc_fdt.c
390
reg &= ~(XENON_EMMC_PHY_PAD_CONTROL1_FC_CMD_PD |
sys/dev/fdt/sdhc_fdt.c
392
reg |= (XENON_EMMC_PHY_PAD_CONTROL1_FC_CMD_PU |
sys/dev/fdt/sdhc_fdt.c
395
XENON_EMMC_PHY_PAD_CONTROL1, reg);
sys/dev/fdt/sdhc_fdt.c
401
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/fdt/sdhc_fdt.c
403
reg &= ~XENON_EMMC_PHY_TIMING_ADJUST_SDIO_MODE;
sys/dev/fdt/sdhc_fdt.c
405
XENON_EMMC_PHY_TIMING_ADJUST, reg);
sys/dev/fdt/sdhc_fdt.c
407
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/fdt/sdhc_fdt.c
409
reg &= ~(XENON_EMMC_PHY_PAD_CONTROL2_ZPR_MASK <<
sys/dev/fdt/sdhc_fdt.c
413
reg |= sc->sc_zpr << XENON_EMMC_PHY_PAD_CONTROL2_ZPR_SHIFT |
sys/dev/fdt/sdhc_fdt.c
416
XENON_EMMC_PHY_PAD_CONTROL2, reg);
sys/dev/fdt/sdhc_fdt.c
418
reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, SDHC_CLOCK_CTL);
sys/dev/fdt/sdhc_fdt.c
419
reg &= ~SDHC_SDCLK_ENABLE;
sys/dev/fdt/sdhc_fdt.c
420
bus_space_write_2(sc->sc_iot, sc->sc_ioh, SDHC_CLOCK_CTL, reg);
sys/dev/fdt/sdhc_fdt.c
422
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/fdt/sdhc_fdt.c
424
reg &= ~(XENON_EMMC_PHY_FUNC_CONTROL_DQ_DDR_MODE |
sys/dev/fdt/sdhc_fdt.c
426
reg |= XENON_EMMC_PHY_FUNC_CONTROL_DQ_ASYNC_MODE;
sys/dev/fdt/sdhc_fdt.c
428
XENON_EMMC_PHY_FUNC_CONTROL, reg);
sys/dev/fdt/sdhc_fdt.c
430
reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, SDHC_CLOCK_CTL);
sys/dev/fdt/sdhc_fdt.c
431
reg |= SDHC_SDCLK_ENABLE;
sys/dev/fdt/sdhc_fdt.c
432
bus_space_write_2(sc->sc_iot, sc->sc_ioh, SDHC_CLOCK_CTL, reg);
sys/dev/fdt/sdhc_fdt.c
434
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/fdt/sdhc_fdt.c
436
reg &= ~(XENON_SLOT_EMMC_CTRL_ENABLE_DATA_STROBE |
sys/dev/fdt/sdhc_fdt.c
439
XENON_SLOT_EMMC_CTRL, reg);
sys/dev/fdt/sdhc_fdt.c
441
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/fdt/sdhc_fdt.c
443
reg &= ~(XENON_EMMC_PHY_PAD_CONTROL1_FC_QSP_PD |
sys/dev/fdt/sdhc_fdt.c
446
XENON_EMMC_PHY_PAD_CONTROL1, reg);
sys/dev/fdt/sdhc_fdt.c
449
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/fdt/sdhc_fdt.c
451
reg |= XENON_EMMC_PHY_TIMING_ADJUST_SAMPL_INV_QSP_PHASE_SELECT;
sys/dev/fdt/sdhc_fdt.c
452
reg &= ~XENON_EMMC_PHY_TIMING_ADJUST_SLOW_MODE;
sys/dev/fdt/sdhc_fdt.c
455
reg |= XENON_EMMC_PHY_TIMING_ADJUST_SLOW_MODE;
sys/dev/fdt/sdhc_fdt.c
457
XENON_EMMC_PHY_TIMING_ADJUST, reg);
sys/dev/fdt/sdhc_fdt.c
459
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/fdt/sdhc_fdt.c
461
reg |= XENON_EMMC_PHY_TIMING_ADJUST_INIT;
sys/dev/fdt/sdhc_fdt.c
463
XENON_EMMC_PHY_TIMING_ADJUST, reg);
sys/dev/fdt/sdhc_fdt.c
466
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/fdt/sdhc_fdt.c
468
if (!(reg & XENON_EMMC_PHY_TIMING_ADJUST_INIT))
sys/dev/fdt/sdhc_fdt.c
477
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
sys/dev/fdt/sdhc_fdt.c
479
reg |= XENON_SYS_OP_CTRL_SDCLK_IDLEOFF_ENABLE(sc->sc_sdhc_id);
sys/dev/fdt/sdhc_fdt.c
481
XENON_SYS_OP_CTRL, reg);
sys/dev/fdt/sfp.c
156
uint8_t reg = sff->sff_page;
sys/dev/fdt/sfp.c
165
sff->sff_addr >> 1, ®, sizeof(reg),
sys/dev/fdt/sfp.c
168
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/simplefb.c
339
struct fdt_reg reg;
sys/dev/fdt/simplefb.c
347
if (fdt_get_reg(node, 0, ®))
sys/dev/fdt/simplefb.c
350
if (bus_space_map(iot, reg.addr, reg.size,
sys/dev/fdt/sncodec.c
384
sncodec_read(struct sncodec_softc *sc, int reg)
sys/dev/fdt/sncodec.c
386
uint8_t cmd = reg;
sys/dev/fdt/sncodec.c
397
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/sncodec.c
405
sncodec_write(struct sncodec_softc *sc, int reg, uint8_t val)
sys/dev/fdt/sncodec.c
407
uint8_t cmd = reg;
sys/dev/fdt/sncodec.c
417
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/ssdfb.c
368
uint8_t reg[2];
sys/dev/fdt/ssdfb.c
370
reg[0] = SSDFB_SET_DISPLAY_OFF;
sys/dev/fdt/ssdfb.c
371
ssdfb_write_command(sc, reg, 1);
sys/dev/fdt/ssdfb.c
373
reg[0] = SSDFB_SET_MEMORY_ADDRESSING_MODE;
sys/dev/fdt/ssdfb.c
374
reg[1] = 0x00; /* Horizontal Addressing Mode */
sys/dev/fdt/ssdfb.c
375
ssdfb_write_command(sc, reg, 2);
sys/dev/fdt/ssdfb.c
376
reg[0] = SSDFB_SET_PAGE_START_ADDRESS;
sys/dev/fdt/ssdfb.c
377
ssdfb_write_command(sc, reg, 1);
sys/dev/fdt/ssdfb.c
382
reg[0] = SSDFB_SET_DISPLAY_CLOCK_DIVIDE_RATIO;
sys/dev/fdt/ssdfb.c
383
reg[1] = 0xa0;
sys/dev/fdt/ssdfb.c
384
ssdfb_write_command(sc, reg, 2);
sys/dev/fdt/ssdfb.c
387
reg[0] = SSDFB_SET_DISPLAY_CLOCK_DIVIDE_RATIO;
sys/dev/fdt/ssdfb.c
388
reg[1] = 0x80;
sys/dev/fdt/ssdfb.c
389
ssdfb_write_command(sc, reg, 2);
sys/dev/fdt/ssdfb.c
391
reg[0] = SSDFB_SET_MULTIPLEX_RATIO;
sys/dev/fdt/ssdfb.c
392
reg[1] = 0x3f;
sys/dev/fdt/ssdfb.c
393
ssdfb_write_command(sc, reg, 2);
sys/dev/fdt/ssdfb.c
394
reg[0] = SSDFB_SET_DISPLAY_OFFSET;
sys/dev/fdt/ssdfb.c
395
reg[1] = OF_getpropint(sc->sc_node, "solomon,com-offset", 0);
sys/dev/fdt/ssdfb.c
396
ssdfb_write_command(sc, reg, 2);
sys/dev/fdt/ssdfb.c
397
reg[0] = SSDFB_SET_START_LINE | 0x00;
sys/dev/fdt/ssdfb.c
398
ssdfb_write_command(sc, reg, 1);
sys/dev/fdt/ssdfb.c
399
reg[0] = SSDFB_SET_COLUMN_DIRECTION_NORMAL;
sys/dev/fdt/ssdfb.c
401
reg[0] = SSDFB_SET_COLUMN_DIRECTION_REVERSE;
sys/dev/fdt/ssdfb.c
402
ssdfb_write_command(sc, reg, 1);
sys/dev/fdt/ssdfb.c
403
reg[0] = SSDFB_SET_COM_OUTPUT_DIRECTION_REMAP;
sys/dev/fdt/ssdfb.c
405
reg[0] = SSDFB_SET_COM_OUTPUT_DIRECTION_NORMAL;
sys/dev/fdt/ssdfb.c
406
ssdfb_write_command(sc, reg, 1);
sys/dev/fdt/ssdfb.c
407
reg[0] = SSDFB_SET_COM_PINS_HARD_CONF;
sys/dev/fdt/ssdfb.c
408
reg[1] = 0x12;
sys/dev/fdt/ssdfb.c
410
reg[1] &= ~(1 << 4);
sys/dev/fdt/ssdfb.c
412
reg[1] |= 1 << 5;
sys/dev/fdt/ssdfb.c
413
ssdfb_write_command(sc, reg, 2);
sys/dev/fdt/ssdfb.c
414
reg[0] = SSDFB_SET_CONTRAST_CONTROL;
sys/dev/fdt/ssdfb.c
415
reg[1] = sc->sc_brightness;
sys/dev/fdt/ssdfb.c
416
ssdfb_write_command(sc, reg, 2);
sys/dev/fdt/ssdfb.c
417
reg[0] = SSDFB_SET_PRE_CHARGE_PERIOD;
sys/dev/fdt/ssdfb.c
418
reg[1] = (OF_getpropint(sc->sc_node, "solomon,prechargep1", 2) & 0xf) << 0;
sys/dev/fdt/ssdfb.c
419
reg[1] |= (OF_getpropint(sc->sc_node, "solomon,prechargep2", 2) & 0xf) << 4;
sys/dev/fdt/ssdfb.c
420
ssdfb_write_command(sc, reg, 2);
sys/dev/fdt/ssdfb.c
423
reg[0] = SSDFB_SET_VCOM_DESELECT_LEVEL;
sys/dev/fdt/ssdfb.c
424
reg[1] = 0x34;
sys/dev/fdt/ssdfb.c
425
ssdfb_write_command(sc, reg, 2);
sys/dev/fdt/ssdfb.c
428
reg[0] = SSDFB_SET_VCOM_DESELECT_LEVEL;
sys/dev/fdt/ssdfb.c
429
reg[1] = 0x20;
sys/dev/fdt/ssdfb.c
430
ssdfb_write_command(sc, reg, 2);
sys/dev/fdt/ssdfb.c
432
reg[0] = SSDFB_CHARGE_PUMP;
sys/dev/fdt/ssdfb.c
433
reg[1] = 0x10;
sys/dev/fdt/ssdfb.c
435
reg[1] |= 1 << 2;
sys/dev/fdt/ssdfb.c
436
ssdfb_write_command(sc, reg, 2);
sys/dev/fdt/ssdfb.c
437
reg[0] = SSDFB_ENTIRE_DISPLAY_ON;
sys/dev/fdt/ssdfb.c
438
ssdfb_write_command(sc, reg, 1);
sys/dev/fdt/ssdfb.c
439
reg[0] = SSDFB_SET_DISPLAY_MODE_NORMAL;
sys/dev/fdt/ssdfb.c
440
ssdfb_write_command(sc, reg, 1);
sys/dev/fdt/ssdfb.c
444
reg[0] = SSDFB_SET_DISPLAY_ON;
sys/dev/fdt/ssdfb.c
445
ssdfb_write_command(sc, reg, 1);
sys/dev/fdt/ssdfb.c
452
uint8_t reg[3];
sys/dev/fdt/ssdfb.c
460
reg[0] = SSDFB_SET_COLUMN_RANGE;
sys/dev/fdt/ssdfb.c
461
reg[1] = sc->sc_column_range[0];
sys/dev/fdt/ssdfb.c
462
reg[2] = sc->sc_column_range[1];
sys/dev/fdt/ssdfb.c
463
ssdfb_write_command(sc, reg, 3);
sys/dev/fdt/ssdfb.c
468
reg[0] = SSDFB_SET_PAGE_RANGE;
sys/dev/fdt/ssdfb.c
469
reg[1] = sc->sc_page_range[0];
sys/dev/fdt/ssdfb.c
470
reg[2] = sc->sc_page_range[1];
sys/dev/fdt/ssdfb.c
471
ssdfb_write_command(sc, reg, 3);
sys/dev/fdt/ssdfb.c
596
uint8_t reg[2];
sys/dev/fdt/ssdfb.c
614
reg[0] = SSDFB_SET_DISPLAY_OFF;
sys/dev/fdt/ssdfb.c
615
ssdfb_write_command(sc, reg, 1);
sys/dev/fdt/ssdfb.c
617
reg[0] = SSDFB_SET_DISPLAY_ON;
sys/dev/fdt/ssdfb.c
618
ssdfb_write_command(sc, reg, 1);
sys/dev/fdt/ssdfb.c
620
reg[0] = SSDFB_SET_CONTRAST_CONTROL;
sys/dev/fdt/ssdfb.c
621
reg[1] = sc->sc_brightness = dp->curval;
sys/dev/fdt/ssdfb.c
622
ssdfb_write_command(sc, reg, 2);
sys/dev/fdt/sunxireg.h
18
#define SXIREAD1(sc, reg) \
sys/dev/fdt/sunxireg.h
19
(bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/sunxireg.h
20
#define SXIWRITE1(sc, reg, val) \
sys/dev/fdt/sunxireg.h
21
bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/sunxireg.h
22
#define SXISET1(sc, reg, bits) \
sys/dev/fdt/sunxireg.h
23
SXIWRITE1((sc), (reg), SXIREAD1((sc), (reg)) | (bits))
sys/dev/fdt/sunxireg.h
24
#define SXICLR1(sc, reg, bits) \
sys/dev/fdt/sunxireg.h
25
SXIWRITE1((sc), (reg), SXIREAD1((sc), (reg)) & ~(bits))
sys/dev/fdt/sunxireg.h
26
#define SXICMS1(sc, reg, mask, bits) \
sys/dev/fdt/sunxireg.h
27
SXIWRITE1((sc), (reg), (SXIREAD1((sc), (reg)) & ~(mask)) | (bits))
sys/dev/fdt/sunxireg.h
29
#define SXIREAD4(sc, reg) \
sys/dev/fdt/sunxireg.h
30
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/sunxireg.h
31
#define SXIWRITE4(sc, reg, val) \
sys/dev/fdt/sunxireg.h
32
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/sunxireg.h
33
#define SXISET4(sc, reg, bits) \
sys/dev/fdt/sunxireg.h
34
SXIWRITE4((sc), (reg), SXIREAD4((sc), (reg)) | (bits))
sys/dev/fdt/sunxireg.h
35
#define SXICLR4(sc, reg, bits) \
sys/dev/fdt/sunxireg.h
36
SXIWRITE4((sc), (reg), SXIREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/sunxireg.h
37
#define SXICMS4(sc, reg, mask, bits) \
sys/dev/fdt/sunxireg.h
38
SXIWRITE4((sc), (reg), (SXIREAD4((sc), (reg)) & ~(mask)) | (bits))
sys/dev/fdt/sxiccmu.c
1008
uint32_t reg, div;
sys/dev/fdt/sxiccmu.c
1017
reg = SXIREAD4(sc, A10_PLL1_CFG_REG);
sys/dev/fdt/sxiccmu.c
1018
k = A10_PLL1_FACTOR_K(reg) + 1;
sys/dev/fdt/sxiccmu.c
1019
m = A10_PLL1_FACTOR_M(reg) + 1;
sys/dev/fdt/sxiccmu.c
1020
n = A10_PLL1_FACTOR_N(reg);
sys/dev/fdt/sxiccmu.c
1021
p = 1 << A10_PLL1_OUT_EXT_DIVP(reg);
sys/dev/fdt/sxiccmu.c
1026
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
sys/dev/fdt/sxiccmu.c
1027
switch (reg & A10_CPU_CLK_SRC_SEL) {
sys/dev/fdt/sxiccmu.c
1042
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
sys/dev/fdt/sxiccmu.c
1043
div = 1 << A10_AXI_CLK_DIV_RATIO(reg);
sys/dev/fdt/sxiccmu.c
1047
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
sys/dev/fdt/sxiccmu.c
1048
div = 1 << A10_AHB_CLK_DIV_RATIO(reg);
sys/dev/fdt/sxiccmu.c
1076
uint32_t reg, div;
sys/dev/fdt/sxiccmu.c
1090
reg = SXIREAD4(sc, CCU_AHB1_APB1_CFG_REG);
sys/dev/fdt/sxiccmu.c
1091
div = CCU_AHB1_CLK_DIV_RATIO(reg);
sys/dev/fdt/sxiccmu.c
1092
switch (reg & CCU_AHB1_CLK_SRC_SEL) {
sys/dev/fdt/sxiccmu.c
1104
div *= CCU_AHB1_PRE_DIV(reg);
sys/dev/fdt/sxiccmu.c
1138
uint32_t reg, div;
sys/dev/fdt/sxiccmu.c
1143
reg = SXIREAD4(sc, A64_PLL_CPUX_CTRL_REG);
sys/dev/fdt/sxiccmu.c
1144
k = A64_PLL_CPUX_FACTOR_K(reg) + 1;
sys/dev/fdt/sxiccmu.c
1145
m = A64_PLL_CPUX_FACTOR_M(reg) + 1;
sys/dev/fdt/sxiccmu.c
1146
n = A64_PLL_CPUX_FACTOR_N(reg) + 1;
sys/dev/fdt/sxiccmu.c
1147
p = 1 << A64_PLL_CPUX_OUT_EXT_DIVP(reg);
sys/dev/fdt/sxiccmu.c
1150
reg = SXIREAD4(sc, A64_CPUX_AXI_CFG_REG);
sys/dev/fdt/sxiccmu.c
1151
switch (reg & A64_CPUX_CLK_SRC_SEL) {
sys/dev/fdt/sxiccmu.c
1178
reg = SXIREAD4(sc, CCU_AHB1_APB1_CFG_REG);
sys/dev/fdt/sxiccmu.c
1179
div = CCU_AHB1_CLK_DIV_RATIO(reg);
sys/dev/fdt/sxiccmu.c
1180
switch (reg & CCU_AHB1_CLK_SRC_SEL) {
sys/dev/fdt/sxiccmu.c
1192
div *= CCU_AHB1_PRE_DIV(reg);
sys/dev/fdt/sxiccmu.c
1199
reg = SXIREAD4(sc, CCU_AHB2_CFG_REG);
sys/dev/fdt/sxiccmu.c
1200
switch (reg & CCU_AHB2_CLK_CFG) {
sys/dev/fdt/sxiccmu.c
1229
uint32_t reg, div;
sys/dev/fdt/sxiccmu.c
1236
reg = SXIREAD4(sc, A80_AHB1_CLK_CFG_REG);
sys/dev/fdt/sxiccmu.c
1237
div = A80_AHB1_CLK_DIV_RATIO(reg);
sys/dev/fdt/sxiccmu.c
1238
switch (reg & A80_AHB1_SRC_CLK_SELECT) {
sys/dev/fdt/sxiccmu.c
1276
uint32_t reg, freq;
sys/dev/fdt/sxiccmu.c
1283
reg = SXIREAD4(sc, D1_PLL_CPU_CTRL_REG);
sys/dev/fdt/sxiccmu.c
1284
m = D1_PLL_CPU_FACTOR_M(reg) + 1;
sys/dev/fdt/sxiccmu.c
1285
n = D1_PLL_CPU_FACTOR_N(reg) + 1;
sys/dev/fdt/sxiccmu.c
1294
reg = SXIREAD4(sc, D1_RISCV_CLK_REG);
sys/dev/fdt/sxiccmu.c
1295
switch (reg & D1_RISCV_CLK_SEL) {
sys/dev/fdt/sxiccmu.c
1305
m = D1_RISCV_DIV_CFG_FACTOR_M(reg) + 1;
sys/dev/fdt/sxiccmu.c
1308
reg = SXIREAD4(sc, D1_PSI_CLK_REG);
sys/dev/fdt/sxiccmu.c
1311
m = D1_PSI_CLK_FACTOR_M(reg) + 1;
sys/dev/fdt/sxiccmu.c
1312
n = 1 << D1_PSI_CLK_FACTOR_N(reg);
sys/dev/fdt/sxiccmu.c
1348
uint32_t reg, div;
sys/dev/fdt/sxiccmu.c
1357
reg = SXIREAD4(sc, H3_PLL_CPUX_CTRL_REG);
sys/dev/fdt/sxiccmu.c
1358
k = H3_PLL_CPUX_FACTOR_K(reg) + 1;
sys/dev/fdt/sxiccmu.c
1359
m = H3_PLL_CPUX_FACTOR_M(reg) + 1;
sys/dev/fdt/sxiccmu.c
1360
n = H3_PLL_CPUX_FACTOR_N(reg) + 1;
sys/dev/fdt/sxiccmu.c
1361
p = 1 << H3_PLL_CPUX_OUT_EXT_DIVP(reg);
sys/dev/fdt/sxiccmu.c
1367
reg = SXIREAD4(sc, H3_CPUX_AXI_CFG_REG);
sys/dev/fdt/sxiccmu.c
1368
switch (reg & H3_CPUX_CLK_SRC_SEL) {
sys/dev/fdt/sxiccmu.c
1386
reg = SXIREAD4(sc, CCU_AHB1_APB1_CFG_REG);
sys/dev/fdt/sxiccmu.c
1387
div = CCU_AHB1_CLK_DIV_RATIO(reg);
sys/dev/fdt/sxiccmu.c
1388
switch (reg & CCU_AHB1_CLK_SRC_SEL) {
sys/dev/fdt/sxiccmu.c
1400
div *= CCU_AHB1_PRE_DIV(reg);
sys/dev/fdt/sxiccmu.c
1407
reg = SXIREAD4(sc, CCU_AHB2_CFG_REG);
sys/dev/fdt/sxiccmu.c
1408
switch (reg & CCU_AHB2_CLK_CFG) {
sys/dev/fdt/sxiccmu.c
1442
uint32_t reg, div;
sys/dev/fdt/sxiccmu.c
1447
reg = SXIREAD4(sc, H3_AHB0_CLK_REG);
sys/dev/fdt/sxiccmu.c
1448
switch (reg & H3_AHB0_CLK_SRC_SEL) {
sys/dev/fdt/sxiccmu.c
1462
div = H3_AHB0_CLK_PRE_DIV(reg) * H3_AHB0_CLK_RATIO(reg);
sys/dev/fdt/sxiccmu.c
1465
reg = SXIREAD4(sc, H3_APB0_CFG_REG);
sys/dev/fdt/sxiccmu.c
1466
div = H3_APB0_CLK_RATIO(reg);
sys/dev/fdt/sxiccmu.c
1483
uint32_t reg, m, n;
sys/dev/fdt/sxiccmu.c
1493
reg = SXIREAD4(sc, H6_AHB3_CFG_REG);
sys/dev/fdt/sxiccmu.c
1496
m = H6_AHB3_CLK_FACTOR_M(reg) + 1;
sys/dev/fdt/sxiccmu.c
1497
n = 1 << H6_AHB3_CLK_FACTOR_N(reg);
sys/dev/fdt/sxiccmu.c
1529
uint32_t reg, m, n;
sys/dev/fdt/sxiccmu.c
1539
reg = SXIREAD4(sc, H616_AHB3_CFG_REG);
sys/dev/fdt/sxiccmu.c
1542
m = H616_AHB3_CLK_FACTOR_M(reg) + 1;
sys/dev/fdt/sxiccmu.c
1543
n = 1 << H616_AHB3_CLK_FACTOR_N(reg);
sys/dev/fdt/sxiccmu.c
1571
uint32_t reg, div;
sys/dev/fdt/sxiccmu.c
1584
reg = SXIREAD4(sc, CCU_AHB1_APB1_CFG_REG);
sys/dev/fdt/sxiccmu.c
1585
div = CCU_AHB1_CLK_DIV_RATIO(reg);
sys/dev/fdt/sxiccmu.c
1586
switch (reg & CCU_AHB1_CLK_SRC_SEL) {
sys/dev/fdt/sxiccmu.c
1598
div *= CCU_AHB1_PRE_DIV(reg);
sys/dev/fdt/sxiccmu.c
1615
uint32_t reg, div;
sys/dev/fdt/sxiccmu.c
1629
reg = SXIREAD4(sc, CCU_AHB1_APB1_CFG_REG);
sys/dev/fdt/sxiccmu.c
1630
div = CCU_AHB1_CLK_DIV_RATIO(reg);
sys/dev/fdt/sxiccmu.c
1631
switch (reg & CCU_AHB1_CLK_SRC_SEL) {
sys/dev/fdt/sxiccmu.c
1643
div *= CCU_AHB1_PRE_DIV(reg);
sys/dev/fdt/sxiccmu.c
1650
reg = SXIREAD4(sc, CCU_AHB2_CFG_REG);
sys/dev/fdt/sxiccmu.c
1651
switch (reg & CCU_AHB2_CLK_CFG) {
sys/dev/fdt/sxiccmu.c
1691
uint32_t reg;
sys/dev/fdt/sxiccmu.c
1703
reg = SXIREAD4(sc, A10_PLL1_CFG_REG);
sys/dev/fdt/sxiccmu.c
1704
reg &= ~A10_PLL1_OUT_EXT_DIVP_MASK;
sys/dev/fdt/sxiccmu.c
1705
reg &= ~A10_PLL1_FACTOR_N_MASK;
sys/dev/fdt/sxiccmu.c
1706
reg &= ~A10_PLL1_FACTOR_K_MASK;
sys/dev/fdt/sxiccmu.c
1707
reg &= ~A10_PLL1_FACTOR_M_MASK;
sys/dev/fdt/sxiccmu.c
1708
reg |= (n << A10_PLL1_FACTOR_N_SHIFT);
sys/dev/fdt/sxiccmu.c
1709
reg |= ((k - 1) << A10_PLL1_FACTOR_K_SHIFT);
sys/dev/fdt/sxiccmu.c
1710
SXIWRITE4(sc, A10_PLL1_CFG_REG, reg);
sys/dev/fdt/sxiccmu.c
1717
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
sys/dev/fdt/sxiccmu.c
1718
reg &= ~A10_CPU_CLK_SRC_SEL;
sys/dev/fdt/sxiccmu.c
1719
reg |= A10_CPU_CLK_SRC_SEL_OSC24M;
sys/dev/fdt/sxiccmu.c
1720
SXIWRITE4(sc, A10_CPU_AHB_APB0_CFG_REG, reg);
sys/dev/fdt/sxiccmu.c
1725
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
sys/dev/fdt/sxiccmu.c
1726
reg &= ~A10_CPU_CLK_SRC_SEL;
sys/dev/fdt/sxiccmu.c
1727
reg |= A10_CPU_CLK_SRC_SEL_PLL1;
sys/dev/fdt/sxiccmu.c
1728
SXIWRITE4(sc, A10_CPU_AHB_APB0_CFG_REG, reg);
sys/dev/fdt/sxiccmu.c
1736
sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
sys/dev/fdt/sxiccmu.c
1752
uint32_t reg;
sys/dev/fdt/sxiccmu.c
1764
reg = SXIREAD4(sc, A10_PLL1_CFG_REG);
sys/dev/fdt/sxiccmu.c
1765
reg &= ~A10_PLL1_OUT_EXT_DIVP_MASK;
sys/dev/fdt/sxiccmu.c
1766
reg &= ~A10_PLL1_FACTOR_N_MASK;
sys/dev/fdt/sxiccmu.c
1767
reg &= ~A10_PLL1_FACTOR_K_MASK;
sys/dev/fdt/sxiccmu.c
1768
reg &= ~A10_PLL1_FACTOR_M_MASK;
sys/dev/fdt/sxiccmu.c
1769
reg |= (n << A10_PLL1_FACTOR_N_SHIFT);
sys/dev/fdt/sxiccmu.c
1770
reg |= ((k - 1) << A10_PLL1_FACTOR_K_SHIFT);
sys/dev/fdt/sxiccmu.c
1771
SXIWRITE4(sc, A10_PLL1_CFG_REG, reg);
sys/dev/fdt/sxiccmu.c
1778
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
sys/dev/fdt/sxiccmu.c
1779
reg &= ~A10_CPU_CLK_SRC_SEL;
sys/dev/fdt/sxiccmu.c
1780
reg |= A10_CPU_CLK_SRC_SEL_OSC24M;
sys/dev/fdt/sxiccmu.c
1781
SXIWRITE4(sc, A10_CPU_AHB_APB0_CFG_REG, reg);
sys/dev/fdt/sxiccmu.c
1786
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
sys/dev/fdt/sxiccmu.c
1787
reg &= ~A10_CPU_CLK_SRC_SEL;
sys/dev/fdt/sxiccmu.c
1788
reg |= A10_CPU_CLK_SRC_SEL_PLL1;
sys/dev/fdt/sxiccmu.c
1789
SXIWRITE4(sc, A10_CPU_AHB_APB0_CFG_REG, reg);
sys/dev/fdt/sxiccmu.c
1796
sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
sys/dev/fdt/sxiccmu.c
1818
sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
sys/dev/fdt/sxiccmu.c
1833
uint32_t reg;
sys/dev/fdt/sxiccmu.c
1845
reg = SXIREAD4(sc, A64_PLL_CPUX_CTRL_REG);
sys/dev/fdt/sxiccmu.c
1846
reg &= ~A64_PLL_CPUX_OUT_EXT_DIVP_MASK;
sys/dev/fdt/sxiccmu.c
1847
reg &= ~A64_PLL_CPUX_FACTOR_N_MASK;
sys/dev/fdt/sxiccmu.c
1848
reg &= ~A64_PLL_CPUX_FACTOR_K_MASK;
sys/dev/fdt/sxiccmu.c
1849
reg &= ~A64_PLL_CPUX_FACTOR_M_MASK;
sys/dev/fdt/sxiccmu.c
1850
reg |= ((n - 1) << A64_PLL_CPUX_FACTOR_N_SHIFT);
sys/dev/fdt/sxiccmu.c
1851
reg |= ((k - 1) << A64_PLL_CPUX_FACTOR_K_SHIFT);
sys/dev/fdt/sxiccmu.c
1852
SXIWRITE4(sc, A64_PLL_CPUX_CTRL_REG, reg);
sys/dev/fdt/sxiccmu.c
1863
reg = SXIREAD4(sc, A64_CPUX_AXI_CFG_REG);
sys/dev/fdt/sxiccmu.c
1864
reg &= ~A64_CPUX_CLK_SRC_SEL;
sys/dev/fdt/sxiccmu.c
1865
reg |= A64_CPUX_CLK_SRC_SEL_OSC24M;
sys/dev/fdt/sxiccmu.c
1866
SXIWRITE4(sc, A64_CPUX_AXI_CFG_REG, reg);
sys/dev/fdt/sxiccmu.c
1871
reg = SXIREAD4(sc, A64_CPUX_AXI_CFG_REG);
sys/dev/fdt/sxiccmu.c
1872
reg &= ~A64_CPUX_CLK_SRC_SEL;
sys/dev/fdt/sxiccmu.c
1873
reg |= A64_CPUX_CLK_SRC_SEL_PLL_CPUX;
sys/dev/fdt/sxiccmu.c
1874
SXIWRITE4(sc, A64_CPUX_AXI_CFG_REG, reg);
sys/dev/fdt/sxiccmu.c
1881
sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
sys/dev/fdt/sxiccmu.c
1903
sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
sys/dev/fdt/sxiccmu.c
1929
uint32_t reg, m, n;
sys/dev/fdt/sxiccmu.c
1955
reg = SXIREAD4(sc, offset);
sys/dev/fdt/sxiccmu.c
1956
reg &= ~D1_SMHC_CLK_SRC_SEL;
sys/dev/fdt/sxiccmu.c
1957
reg |= clk_src;
sys/dev/fdt/sxiccmu.c
1958
reg &= ~D1_SMHC_FACTOR_N_MASK;
sys/dev/fdt/sxiccmu.c
1959
reg |= n << D1_SMHC_FACTOR_N_SHIFT;
sys/dev/fdt/sxiccmu.c
1960
reg &= ~D1_SMHC_FACTOR_M_MASK;
sys/dev/fdt/sxiccmu.c
1961
reg |= m << D1_SMHC_FACTOR_M_SHIFT;
sys/dev/fdt/sxiccmu.c
1962
SXIWRITE4(sc, offset, reg);
sys/dev/fdt/sxiccmu.c
1988
uint32_t reg, lock_time;
sys/dev/fdt/sxiccmu.c
2001
reg = SXIREAD4(sc, H3_PLL_CPUX_CTRL_REG);
sys/dev/fdt/sxiccmu.c
2002
reg &= ~H3_PLL_CPUX_ENABLE;
sys/dev/fdt/sxiccmu.c
2003
SXIWRITE4(sc, H3_PLL_CPUX_CTRL_REG, reg);
sys/dev/fdt/sxiccmu.c
2006
reg &= ~H3_PLL_CPUX_OUT_EXT_DIVP_MASK;
sys/dev/fdt/sxiccmu.c
2007
reg &= ~H3_PLL_CPUX_FACTOR_N_MASK;
sys/dev/fdt/sxiccmu.c
2008
reg &= ~H3_PLL_CPUX_FACTOR_K_MASK;
sys/dev/fdt/sxiccmu.c
2009
reg &= ~H3_PLL_CPUX_FACTOR_M_MASK;
sys/dev/fdt/sxiccmu.c
2010
reg |= ((n - 1) << H3_PLL_CPUX_FACTOR_N_SHIFT);
sys/dev/fdt/sxiccmu.c
2011
reg |= ((k - 1) << H3_PLL_CPUX_FACTOR_K_SHIFT);
sys/dev/fdt/sxiccmu.c
2012
SXIWRITE4(sc, H3_PLL_CPUX_CTRL_REG, reg);
sys/dev/fdt/sxiccmu.c
2015
reg |= H3_PLL_CPUX_ENABLE;
sys/dev/fdt/sxiccmu.c
2016
SXIWRITE4(sc, H3_PLL_CPUX_CTRL_REG, reg);
sys/dev/fdt/sxiccmu.c
2025
reg = SXIREAD4(sc, H3_CPUX_AXI_CFG_REG);
sys/dev/fdt/sxiccmu.c
2026
reg &= ~H3_CPUX_CLK_SRC_SEL;
sys/dev/fdt/sxiccmu.c
2027
reg |= H3_CPUX_CLK_SRC_SEL_OSC24M;
sys/dev/fdt/sxiccmu.c
2028
SXIWRITE4(sc, H3_CPUX_AXI_CFG_REG, reg);
sys/dev/fdt/sxiccmu.c
2035
reg = SXIREAD4(sc, H3_CPUX_AXI_CFG_REG);
sys/dev/fdt/sxiccmu.c
2036
reg &= ~H3_CPUX_CLK_SRC_SEL;
sys/dev/fdt/sxiccmu.c
2037
reg |= H3_CPUX_CLK_SRC_SEL_PLL_CPUX;
sys/dev/fdt/sxiccmu.c
2038
SXIWRITE4(sc, H3_CPUX_AXI_CFG_REG, reg);
sys/dev/fdt/sxiccmu.c
2047
sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
sys/dev/fdt/sxiccmu.c
2072
uint32_t reg, m, n;
sys/dev/fdt/sxiccmu.c
2096
reg = SXIREAD4(sc, offset);
sys/dev/fdt/sxiccmu.c
2097
reg &= ~H6_SMHC_CLK_SRC_SEL;
sys/dev/fdt/sxiccmu.c
2098
reg |= clk_src;
sys/dev/fdt/sxiccmu.c
2099
reg &= ~H6_SMHC_FACTOR_N_MASK;
sys/dev/fdt/sxiccmu.c
2100
reg |= n << H6_SMHC_FACTOR_N_SHIFT;
sys/dev/fdt/sxiccmu.c
2101
reg &= ~H6_SMHC_FACTOR_M_MASK;
sys/dev/fdt/sxiccmu.c
2102
reg |= m << H6_SMHC_FACTOR_M_SHIFT;
sys/dev/fdt/sxiccmu.c
2103
SXIWRITE4(sc, offset, reg);
sys/dev/fdt/sxiccmu.c
2171
sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
sys/dev/fdt/sxiccmu.c
2193
sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
sys/dev/fdt/sxiccmu.c
2215
int reg, bit;
sys/dev/fdt/sxiccmu.c
2220
(sc->sc_gates[idx].reg == 0 && sc->sc_gates[idx].bit == 0)) {
sys/dev/fdt/sxiccmu.c
2226
if (sc->sc_gates[idx].reg == 0xffff && sc->sc_gates[idx].bit == 0xff)
sys/dev/fdt/sxiccmu.c
2229
reg = sc->sc_gates[idx].reg;
sys/dev/fdt/sxiccmu.c
2233
SXISET4(sc, reg, (1U << bit));
sys/dev/fdt/sxiccmu.c
2235
SXICLR4(sc, reg, (1U << bit));
sys/dev/fdt/sxiccmu.c
2243
int reg, bit;
sys/dev/fdt/sxiccmu.c
2248
(sc->sc_resets[idx].reg == 0 && sc->sc_gates[idx].bit == 0)) {
sys/dev/fdt/sxiccmu.c
2253
reg = sc->sc_resets[idx].reg;
sys/dev/fdt/sxiccmu.c
2257
SXICLR4(sc, reg, (1U << bit));
sys/dev/fdt/sxiccmu.c
2259
SXISET4(sc, reg, (1U << bit));
sys/dev/fdt/sxiccmu.c
48
uint16_t reg;
sys/dev/fdt/sxiccmu.c
584
uint32_t reg[2];
sys/dev/fdt/sxiccmu.c
597
if (OF_getpropintarray(node, "reg", reg, sizeof(reg)) == sizeof(reg)) {
sys/dev/fdt/sxiccmu.c
598
error = bus_space_map(clock->sc_iot, reg[0], reg[1], 0,
sys/dev/fdt/sxiccmu.c
663
uint32_t reg, k, m, n, freq;
sys/dev/fdt/sxiccmu.c
667
reg = SXIREAD4(sc, 0);
sys/dev/fdt/sxiccmu.c
668
k = CCU_PLL6_FACTOR_K(reg) + 1;
sys/dev/fdt/sxiccmu.c
669
m = CCU_PLL6_FACTOR_M(reg) + 1;
sys/dev/fdt/sxiccmu.c
670
n = CCU_PLL6_FACTOR_N(reg);
sys/dev/fdt/sxiccmu.c
692
uint32_t reg;
sys/dev/fdt/sxiccmu.c
698
reg = SXIREAD4(sc, 0);
sys/dev/fdt/sxiccmu.c
702
reg |= CCU_PLL6_SATA_CLK_EN;
sys/dev/fdt/sxiccmu.c
704
reg &= ~CCU_PLL6_SATA_CLK_EN;
sys/dev/fdt/sxiccmu.c
710
reg |= CCU_PLL6_ENABLE;
sys/dev/fdt/sxiccmu.c
712
SXIWRITE4(sc, 0, reg);
sys/dev/fdt/sxiccmu.c
723
uint32_t reg, m, n, freq;
sys/dev/fdt/sxiccmu.c
726
reg = SXIREAD4(sc, 0);
sys/dev/fdt/sxiccmu.c
727
m = CCU_APB1_CLK_RAT_M(reg);
sys/dev/fdt/sxiccmu.c
728
n = CCU_APB1_CLK_RAT_N(reg);
sys/dev/fdt/sxiccmu.c
729
idx = CCU_APB1_CLK_SRC_SEL(reg);
sys/dev/fdt/sxiccmu.c
743
uint32_t reg, post_div, clk_ratio, freq;
sys/dev/fdt/sxiccmu.c
746
reg = SXIREAD4(sc, 0);
sys/dev/fdt/sxiccmu.c
747
idx = CCU_CPUS_CLK_SRC_SEL(reg);
sys/dev/fdt/sxiccmu.c
748
post_div = (idx == 2 ? CCU_CPUS_POST_DIV(reg): 0);
sys/dev/fdt/sxiccmu.c
749
clk_ratio = CCU_CPUS_CLK_RATIO(reg);
sys/dev/fdt/sxiccmu.c
761
uint32_t reg, freq;
sys/dev/fdt/sxiccmu.c
763
reg = SXIREAD4(sc, 0);
sys/dev/fdt/sxiccmu.c
765
return freq / (CCU_APBS_CLK_RATIO(reg) + 1);
sys/dev/fdt/sxiccmu.c
809
uint32_t reg, m, n;
sys/dev/fdt/sxiccmu.c
833
reg = SXIREAD4(sc, 0);
sys/dev/fdt/sxiccmu.c
834
reg &= ~CCU_SDx_CLK_SRC_SEL_MASK;
sys/dev/fdt/sxiccmu.c
835
reg |= clk_src;
sys/dev/fdt/sxiccmu.c
836
reg &= ~CCU_SDx_CLK_DIV_RATIO_N_MASK;
sys/dev/fdt/sxiccmu.c
837
reg |= n << CCU_SDx_CLK_DIV_RATIO_N_SHIFT;
sys/dev/fdt/sxiccmu.c
838
reg &= ~CCU_SDx_CLK_DIV_RATIO_M_MASK;
sys/dev/fdt/sxiccmu.c
839
reg |= m << CCU_SDx_CLK_DIV_RATIO_M_SHIFT;
sys/dev/fdt/sxiccmu.c
840
SXIWRITE4(sc, 0, reg);
sys/dev/fdt/sxiccmu.c
876
int reg = cells[0] / 32;
sys/dev/fdt/sxiccmu.c
881
SXISET4(sc, reg * 4, (1U << bit));
sys/dev/fdt/sxiccmu.c
883
SXICLR4(sc, reg * 4, (1U << bit));
sys/dev/fdt/sxiccmu.c
892
int reg = cells[0] / 32;
sys/dev/fdt/sxiccmu.c
896
SXICLR4(sc, reg * 4, (1U << bit));
sys/dev/fdt/sxiccmu.c
898
SXISET4(sc, reg * 4, (1U << bit));
sys/dev/fdt/sxiccmu.c
949
uint32_t reg, div;
sys/dev/fdt/sxiccmu.c
958
reg = SXIREAD4(sc, A10_PLL1_CFG_REG);
sys/dev/fdt/sxiccmu.c
959
k = A10_PLL1_FACTOR_K(reg) + 1;
sys/dev/fdt/sxiccmu.c
960
m = A10_PLL1_FACTOR_M(reg) + 1;
sys/dev/fdt/sxiccmu.c
961
n = A10_PLL1_FACTOR_N(reg);
sys/dev/fdt/sxiccmu.c
962
p = 1 << A10_PLL1_OUT_EXT_DIVP(reg);
sys/dev/fdt/sxiccmu.c
970
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
sys/dev/fdt/sxiccmu.c
971
switch (reg & A10_CPU_CLK_SRC_SEL) {
sys/dev/fdt/sxiccmu.c
986
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
sys/dev/fdt/sxiccmu.c
987
div = 1 << A10_AXI_CLK_DIV_RATIO(reg);
sys/dev/fdt/sxiccmu.c
991
reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG);
sys/dev/fdt/sxiccmu.c
992
div = 1 << A10_AHB_CLK_DIV_RATIO(reg);
sys/dev/fdt/sximmc.c
284
#define MMC_WRITE(sc, reg, val) \
sys/dev/fdt/sximmc.c
285
bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
sys/dev/fdt/sximmc.c
286
#define MMC_READ(sc, reg) \
sys/dev/fdt/sximmc.c
287
bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
sys/dev/fdt/sxipio.c
426
uint32_t reg;
sys/dev/fdt/sxipio.c
432
reg = SXIREAD4(sc, SXIPIO_DAT(port));
sys/dev/fdt/sxipio.c
433
reg &= (1 << pin);
sys/dev/fdt/sxipio.c
434
val = (reg >> pin) & 1;
sys/dev/fdt/sxipio.c
447
uint32_t reg;
sys/dev/fdt/sxipio.c
452
reg = SXIREAD4(sc, SXIPIO_DAT(port));
sys/dev/fdt/sxipio.c
456
reg |= (1 << pin);
sys/dev/fdt/sxipio.c
458
reg &= ~(1 << pin);
sys/dev/fdt/sxipio.c
459
SXIWRITE4(sc, SXIPIO_DAT(port), reg);
sys/dev/fdt/sxipio.c
544
uint32_t reg;
sys/dev/fdt/sxipio.c
560
reg = SXIREAD4(sc, SXIPIO_CFG(port, pin));
sys/dev/fdt/sxipio.c
562
mux = (reg >> off) & 0x7;
sys/dev/fdt/sxipio.c
581
reg = SXIREAD4(sc, SXIPIO_DAT(port));
sys/dev/fdt/sxipio.c
582
state = (reg >> pin) & 1;
sys/dev/fdt/sxipwm.c
186
uint32_t reg;
sys/dev/fdt/sxipwm.c
213
reg = HREAD4(sc, PWM_CTRL_REG);
sys/dev/fdt/sxipwm.c
214
if (reg & PWM0_RDY)
sys/dev/fdt/sxipwm.c
217
reg |= (PWM_CH0_EN | SCLK_CH0_GATING);
sys/dev/fdt/sxipwm.c
219
reg &= ~(PWM_CH0_EN | SCLK_CH0_GATING);
sys/dev/fdt/sxipwm.c
221
reg &= ~PWM_CH0_ACT_STA;
sys/dev/fdt/sxipwm.c
223
reg |= PWM_CH0_ACT_STA;
sys/dev/fdt/sxipwm.c
224
reg &= ~PWM_CH0_PRESCAL;
sys/dev/fdt/sxipwm.c
225
reg |= sxipwm_prescalers[prescaler].value;
sys/dev/fdt/sxipwm.c
226
HWRITE4(sc, PWM_CTRL_REG, reg);
sys/dev/fdt/sxipwm.c
228
reg = ((cycles - 1) << PWM_CH0_CYCLES_SHIFT) |
sys/dev/fdt/sxipwm.c
230
HWRITE4(sc, PWM_CH0_PERIOD, reg);
sys/dev/fdt/sxipwm.c
45
#define HREAD4(sc, reg) \
sys/dev/fdt/sxipwm.c
46
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/sxipwm.c
47
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/sxipwm.c
48
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/sxirintc.c
32
#define HREAD4(sc, reg) \
sys/dev/fdt/sxirintc.c
33
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/sxirintc.c
34
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/sxirintc.c
35
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/sxirintc.c
36
#define HSET4(sc, reg, bits) \
sys/dev/fdt/sxirintc.c
37
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/sxirintc.c
38
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/sxirintc.c
39
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/sxirsb.c
109
uint32_t reg;
sys/dev/fdt/sxirsb.c
131
reg = OF_getpropint(node, "reg", 0);
sys/dev/fdt/sxirsb.c
132
if (reg == 0)
sys/dev/fdt/sxirsb.c
143
ra.ra_da = reg;
sys/dev/fdt/sxirsb.c
144
ra.ra_rta = sxirsb_rta(reg);
sys/dev/fdt/sxirsb.c
176
uint32_t reg;
sys/dev/fdt/sxirsb.c
225
reg = OF_getpropint(node, "reg", 0);
sys/dev/fdt/sxirsb.c
226
if (reg == 0)
sys/dev/fdt/sxirsb.c
229
rta = sxirsb_rta(reg);
sys/dev/fdt/sxirsb.c
231
HWRITE4(sc, RSB_DAR, (rta << 16 | reg));
sys/dev/fdt/sxirsb.c
241
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/sxirsb.c
60
#define HREAD4(sc, reg) \
sys/dev/fdt/sxirsb.c
61
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/sxirsb.c
62
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/sxirsb.c
63
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/sxirsb.c
64
#define HSET4(sc, reg, bits) \
sys/dev/fdt/sxirsb.c
65
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/fdt/sxirsb.c
66
#define HCLR4(sc, reg, bits) \
sys/dev/fdt/sxirsb.c
67
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/fdt/sxirtc.c
216
uint32_t reg;
sys/dev/fdt/sxirtc.c
218
reg = SXIREAD4(sc, sc->sc_yymmdd);
sys/dev/fdt/sxirtc.c
220
clock_secs_to_ymdhms(reg * SECDAY, &dt);
sys/dev/fdt/sxirtc.c
222
dt.dt_day = reg & 0x1f;
sys/dev/fdt/sxirtc.c
223
dt.dt_mon = reg >> 8 & 0x0f;
sys/dev/fdt/sxirtc.c
224
dt.dt_year = (reg >> 16 & sc->year_mask) + sc->base_year;
sys/dev/fdt/sxirtc.c
227
reg = SXIREAD4(sc, sc->sc_hhmmss);
sys/dev/fdt/sxirtc.c
228
dt.dt_sec = reg & 0x3f;
sys/dev/fdt/sxirtc.c
229
dt.dt_min = reg >> 8 & 0x3f;
sys/dev/fdt/sxirtc.c
230
dt.dt_hour = reg >> 16 & 0x1f;
sys/dev/fdt/sxirtc.c
231
dt.dt_wday = reg >> 29 & 0x07;
sys/dev/fdt/sxisid.c
39
#define HREAD4(sc, reg) \
sys/dev/fdt/sxisid.c
40
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/sxisid.c
41
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/sxisid.c
42
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/sxitemp.c
60
#define HREAD4(sc, reg) \
sys/dev/fdt/sxitemp.c
61
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/sxitemp.c
62
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/sxitemp.c
63
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/sxits.c
46
#define HREAD4(sc, reg) \
sys/dev/fdt/sxits.c
47
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/fdt/sxits.c
48
#define HWRITE4(sc, reg, val) \
sys/dev/fdt/sxits.c
49
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/fdt/sxitwi.c
308
uint32_t reg[1];
sys/dev/fdt/sxitwi.c
313
memset(reg, 0, sizeof(reg));
sys/dev/fdt/sxitwi.c
323
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/dev/fdt/sxitwi.c
328
ia.ia_addr = bemtoh32(®[0]);
sys/dev/fdt/sxitwi.c
336
sxitwi_read_4(struct sxitwi_softc *sc, u_int reg)
sys/dev/fdt/sxitwi.c
338
KASSERT(reg < TWSI_NREG);
sys/dev/fdt/sxitwi.c
339
return bus_space_read_4(sc->sc_iot, sc->sc_ioh, sc->sc_regs[reg]);
sys/dev/fdt/sxitwi.c
343
sxitwi_write_4(struct sxitwi_softc *sc, u_int reg, u_int val)
sys/dev/fdt/sxitwi.c
345
KASSERT(reg < TWSI_NREG);
sys/dev/fdt/sxitwi.c
346
bus_space_write_4(sc->sc_iot, sc->sc_ioh, sc->sc_regs[reg], val);
sys/dev/fdt/sypwr.c
112
uint8_t reg;
sys/dev/fdt/sypwr.c
121
reg = sypwr_read(sc, SY8106A_VOUT1_SEL);
sys/dev/fdt/sypwr.c
122
reg &= ~SY8106A_VOUT1_SEL_I2C;
sys/dev/fdt/sypwr.c
123
sypwr_write(sc, SY8106A_VOUT1_SEL, reg);
sys/dev/fdt/sypwr.c
132
sypwr_read(struct sypwr_softc *sc, int reg)
sys/dev/fdt/sypwr.c
134
uint8_t cmd = reg;
sys/dev/fdt/sypwr.c
146
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/sypwr.c
154
sypwr_write(struct sypwr_softc *sc, int reg, uint8_t val)
sys/dev/fdt/sypwr.c
156
uint8_t cmd = reg;
sys/dev/fdt/sypwr.c
166
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/sypwr.c
75
uint8_t reg;
sys/dev/fdt/sypwr.c
90
reg = sypwr_read(sc, SY8106A_VOUT1_SEL);
sys/dev/fdt/sypwr.c
91
if (reg & SY8106A_VOUT1_SEL_I2C || sc->sc_fixed_microvolt != 0) {
sys/dev/fdt/tascodec.c
372
tascodec_read(struct tascodec_softc *sc, int reg)
sys/dev/fdt/tascodec.c
374
uint8_t cmd = reg;
sys/dev/fdt/tascodec.c
385
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/tascodec.c
393
tascodec_write(struct tascodec_softc *sc, int reg, uint8_t val)
sys/dev/fdt/tascodec.c
395
uint8_t cmd = reg;
sys/dev/fdt/tascodec.c
405
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/tcpci.c
490
uint8_t reg;
sys/dev/fdt/tcpci.c
492
reg = TCPC_MSG_HDR_INFO_PD_REV20;
sys/dev/fdt/tcpci.c
494
reg |= TCPC_MSG_HDR_INFO_PWR_ROLE;
sys/dev/fdt/tcpci.c
496
reg |= TCPC_MSG_HDR_INFO_DATA_ROLE;
sys/dev/fdt/tcpci.c
498
tcpci_write_reg8(sc, TCPC_MSG_HDR_INFO, reg);
sys/dev/fdt/tcpci.c
551
tcpci_read_reg8(struct tcpci_softc *sc, uint8_t reg)
sys/dev/fdt/tcpci.c
557
sc->sc_addr, ®, sizeof(reg), &val, sizeof(val), 0)) {
sys/dev/fdt/tcpci.c
559
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/tcpci.c
567
tcpci_write_reg8(struct tcpci_softc *sc, uint8_t reg, uint8_t val)
sys/dev/fdt/tcpci.c
571
sc->sc_addr, ®, sizeof(reg), &val, sizeof(val), 0)) {
sys/dev/fdt/tcpci.c
573
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/tcpci.c
579
tcpci_read_reg16(struct tcpci_softc *sc, uint8_t reg)
sys/dev/fdt/tcpci.c
585
sc->sc_addr, ®, sizeof(reg), &val, sizeof(val), 0)) {
sys/dev/fdt/tcpci.c
587
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/tcpci.c
595
tcpci_write_reg16(struct tcpci_softc *sc, uint8_t reg, uint16_t val)
sys/dev/fdt/tcpci.c
599
sc->sc_addr, ®, sizeof(reg), &val, sizeof(val), 0)) {
sys/dev/fdt/tcpci.c
601
sc->sc_dev.dv_xname, reg);
sys/dev/fdt/tipd.c
231
tipd_read_4(struct tipd_softc *sc, uint8_t reg, uint32_t *val)
sys/dev/fdt/tipd.c
238
sc->sc_addr, ®, sizeof(reg), buf, sizeof(buf), 0);
sys/dev/fdt/tipd.c
248
tipd_read_8(struct tipd_softc *sc, uint8_t reg, uint64_t *val)
sys/dev/fdt/tipd.c
255
sc->sc_addr, ®, sizeof(reg), buf, sizeof(buf), 0);
sys/dev/fdt/tipd.c
265
tipd_write_4(struct tipd_softc *sc, uint8_t reg, uint32_t val)
sys/dev/fdt/tipd.c
275
sc->sc_addr, ®, sizeof(reg), buf, sizeof(buf), 0);
sys/dev/fdt/tipd.c
282
tipd_write_8(struct tipd_softc *sc, uint8_t reg, uint64_t val)
sys/dev/fdt/tipd.c
292
sc->sc_addr, ®, sizeof(reg), buf, sizeof(buf), 0);
sys/dev/fdt/tipd.c
305
uint8_t reg = TPS_DATA1;
sys/dev/fdt/tipd.c
324
sc->sc_addr, ®, sizeof(reg), buf, sizeof(buf), 0);
sys/dev/fdt/tipd.c
354
sc->sc_addr, ®, sizeof(reg), buf, sizeof(buf), 0);
sys/dev/fdt/xhci_fdt.c
324
uint32_t reg;
sys/dev/fdt/xhci_fdt.c
327
reg = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USB3_GCTL);
sys/dev/fdt/xhci_fdt.c
328
reg &= ~USB3_GCTL_PRTCAPDIR_MASK;
sys/dev/fdt/xhci_fdt.c
329
reg |= USB3_GCTL_PRTCAPDIR_HOST;
sys/dev/fdt/xhci_fdt.c
330
bus_space_write_4(sc->sc.iot, sc->sc.ioh, USB3_GCTL, reg);
sys/dev/fdt/xhci_fdt.c
334
reg = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USB3_GUSB2PHYCFG0);
sys/dev/fdt/xhci_fdt.c
335
reg &= ~USB3_GUSB2PHYCFG0_USBTRDTIM(0xf);
sys/dev/fdt/xhci_fdt.c
337
reg |= USB3_GUSB2PHYCFG0_PHYIF;
sys/dev/fdt/xhci_fdt.c
338
reg |= USB3_GUSB2PHYCFG0_USBTRDTIM(0x5);
sys/dev/fdt/xhci_fdt.c
340
reg &= ~USB3_GUSB2PHYCFG0_PHYIF;
sys/dev/fdt/xhci_fdt.c
341
reg |= USB3_GUSB2PHYCFG0_USBTRDTIM(0x9);
sys/dev/fdt/xhci_fdt.c
344
reg &= ~USB3_GUSB2PHYCFG0_U2_FREECLK_EXISTS;
sys/dev/fdt/xhci_fdt.c
346
reg &= ~USB3_GUSB2PHYCFG0_ENBLSLPM;
sys/dev/fdt/xhci_fdt.c
348
reg &= ~USB3_GUSB2PHYCFG0_SUSPENDUSB20;
sys/dev/fdt/xhci_fdt.c
349
bus_space_write_4(sc->sc.iot, sc->sc.ioh, USB3_GUSB2PHYCFG0, reg);
sys/dev/fdt/xhci_fdt.c
352
reg = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USB3_GUCTL1);
sys/dev/fdt/xhci_fdt.c
354
reg |= USB3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
sys/dev/fdt/xhci_fdt.c
355
bus_space_write_4(sc->sc.iot, sc->sc.ioh, USB3_GUCTL1, reg);
sys/dev/fdt/xhci_fdt.c
600
uint32_t phy_reg[2], reg;
sys/dev/fdt/xhci_fdt.c
621
reg = bus_space_read_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL0);
sys/dev/fdt/xhci_fdt.c
622
reg &= ~IMX8MQ_PHY_CTRL0_FSEL_MASK;
sys/dev/fdt/xhci_fdt.c
623
reg |= IMX8MQ_PHY_CTRL0_FSEL_24M;
sys/dev/fdt/xhci_fdt.c
624
bus_space_write_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL0, reg);
sys/dev/fdt/xhci_fdt.c
626
reg = bus_space_read_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL6);
sys/dev/fdt/xhci_fdt.c
627
reg &= ~(IMX8MQ_PHY_CTRL6_ALT_CLK_SEL | IMX8MQ_PHY_CTRL6_ALT_CLK_EN);
sys/dev/fdt/xhci_fdt.c
628
bus_space_write_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL6, reg);
sys/dev/fdt/xhci_fdt.c
630
reg = bus_space_read_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL1);
sys/dev/fdt/xhci_fdt.c
631
reg &= ~(IMX8MQ_PHY_CTRL1_VDATSRCENB0 | IMX8MQ_PHY_CTRL1_VDATDETENB0);
sys/dev/fdt/xhci_fdt.c
632
reg |= IMX8MQ_PHY_CTRL1_RESET | IMX8MQ_PHY_CTRL1_ATERESET;
sys/dev/fdt/xhci_fdt.c
633
bus_space_write_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL1, reg);
sys/dev/fdt/xhci_fdt.c
635
reg = bus_space_read_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL0);
sys/dev/fdt/xhci_fdt.c
636
reg |= IMX8MQ_PHY_CTRL0_REF_SSP_EN;
sys/dev/fdt/xhci_fdt.c
637
bus_space_write_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL0, reg);
sys/dev/fdt/xhci_fdt.c
639
reg = bus_space_read_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL2);
sys/dev/fdt/xhci_fdt.c
640
reg |= IMX8MQ_PHY_CTRL2_TXENABLEN0 | IMX8MQ_PHY_CTRL2_OTG_DISABLE;
sys/dev/fdt/xhci_fdt.c
641
bus_space_write_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL2, reg);
sys/dev/fdt/xhci_fdt.c
645
reg = bus_space_read_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL1);
sys/dev/fdt/xhci_fdt.c
646
reg &= ~(IMX8MQ_PHY_CTRL1_RESET | IMX8MQ_PHY_CTRL1_ATERESET);
sys/dev/fdt/xhci_fdt.c
647
bus_space_write_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL1, reg);
sys/dev/fdt/xhci_fdt.c
657
uint32_t phy_reg[2], reg;
sys/dev/fdt/xhci_fdt.c
678
reg = bus_space_read_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL1);
sys/dev/fdt/xhci_fdt.c
679
reg &= ~(IMX8MQ_PHY_CTRL1_VDATSRCENB0 | IMX8MQ_PHY_CTRL1_VDATDETENB0);
sys/dev/fdt/xhci_fdt.c
680
reg |= IMX8MQ_PHY_CTRL1_RESET | IMX8MQ_PHY_CTRL1_ATERESET;
sys/dev/fdt/xhci_fdt.c
681
bus_space_write_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL1, reg);
sys/dev/fdt/xhci_fdt.c
683
reg = bus_space_read_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL0);
sys/dev/fdt/xhci_fdt.c
684
reg |= IMX8MQ_PHY_CTRL0_REF_SSP_EN;
sys/dev/fdt/xhci_fdt.c
685
bus_space_write_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL0, reg);
sys/dev/fdt/xhci_fdt.c
687
reg = bus_space_read_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL2);
sys/dev/fdt/xhci_fdt.c
688
reg |= IMX8MQ_PHY_CTRL2_TXENABLEN0;
sys/dev/fdt/xhci_fdt.c
689
bus_space_write_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL2, reg);
sys/dev/fdt/xhci_fdt.c
691
reg = bus_space_read_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL1);
sys/dev/fdt/xhci_fdt.c
692
reg &= ~(IMX8MQ_PHY_CTRL1_RESET | IMX8MQ_PHY_CTRL1_ATERESET);
sys/dev/fdt/xhci_fdt.c
693
bus_space_write_4(sc->sc.iot, sc->ph_ioh, IMX8MQ_PHY_CTRL1, reg);
sys/dev/i2c/abx80x.c
108
uint8_t reg;
sys/dev/i2c/abx80x.c
116
reg = abcrtc_reg_read(sc, ABX8XX_CTRL);
sys/dev/i2c/abx80x.c
117
reg &= ~(ABX8XX_CTRL_ARST | ABX8XX_CTRL_12_24);
sys/dev/i2c/abx80x.c
118
reg |= ABX8XX_CTRL_WRITE;
sys/dev/i2c/abx80x.c
119
abcrtc_reg_write(sc, ABX8XX_CTRL, reg);
sys/dev/i2c/abx80x.c
170
abcrtc_reg_read(struct abcrtc_softc *sc, int reg)
sys/dev/i2c/abx80x.c
172
uint8_t cmd = reg;
sys/dev/i2c/abx80x.c
183
sc->sc_dev.dv_xname, reg);
sys/dev/i2c/abx80x.c
191
abcrtc_reg_write(struct abcrtc_softc *sc, int reg, uint8_t data)
sys/dev/i2c/abx80x.c
193
uint8_t cmd = reg;
sys/dev/i2c/abx80x.c
207
sc->sc_dev.dv_xname, reg);
sys/dev/i2c/abx80x.c
252
uint8_t reg;
sys/dev/i2c/abx80x.c
279
reg = abcrtc_reg_read(sc, ABX8XX_OSS);
sys/dev/i2c/abx80x.c
280
reg &= ~ABX8XX_OSS_OF;
sys/dev/i2c/abx80x.c
281
abcrtc_reg_write(sc, ABX8XX_OSS, reg);
sys/dev/i2c/abx80x.c
291
uint8_t reg = ABX8XX_TRICKLE_ENABLE;
sys/dev/i2c/abx80x.c
295
reg |= ABX8XX_TRICKLE_DIODE_STANDARD;
sys/dev/i2c/abx80x.c
297
reg |= ABX8XX_TRICKLE_DIODE_SCHOTTKY;
sys/dev/i2c/abx80x.c
303
reg |= ABX8XX_TRICKLE_RESISTOR_0;
sys/dev/i2c/abx80x.c
306
reg |= ABX8XX_TRICKLE_RESISTOR_3;
sys/dev/i2c/abx80x.c
309
reg |= ABX8XX_TRICKLE_RESISTOR_6;
sys/dev/i2c/abx80x.c
312
reg |= ABX8XX_TRICKLE_RESISTOR_11;
sys/dev/i2c/abx80x.c
319
abcrtc_reg_write(sc, ABX8XX_TRICKLE, reg);
sys/dev/i2c/ad741x.c
161
u_int8_t cmd, reg;
sys/dev/i2c/ad741x.c
167
reg = (sc->sc_config & AD741X_CONFMASK) | (0 << 5);
sys/dev/i2c/ad741x.c
169
sc->sc_addr, &cmd, sizeof cmd, ®, sizeof reg, 0))
sys/dev/i2c/ad741x.c
183
reg = (reg & AD741X_CONFMASK) | (4 << 5);
sys/dev/i2c/ad741x.c
185
sc->sc_addr, &cmd, sizeof cmd, ®, sizeof reg, 0))
sys/dev/i2c/ad741x.c
197
reg = (reg & AD741X_CONFMASK) | (i << 5);
sys/dev/i2c/ad741x.c
199
sc->sc_addr, &cmd, sizeof cmd, ®, sizeof reg, 0))
sys/dev/i2c/asc7611.c
220
andl_readreg(struct andl_softc *sc, uint8_t reg)
sys/dev/i2c/asc7611.c
225
sc->sc_addr, ®, sizeof reg, &data, sizeof data, 0);
sys/dev/i2c/asc7611.c
231
andl_writereg(struct andl_softc *sc, uint8_t reg, uint8_t data)
sys/dev/i2c/asc7611.c
234
sc->sc_addr, ®, sizeof reg, &data, sizeof data, 0);
sys/dev/i2c/ds3231.c
133
dsxrtc_reg_read(struct dsxrtc_softc *sc, int reg)
sys/dev/i2c/ds3231.c
135
uint8_t cmd = reg;
sys/dev/i2c/ds3231.c
146
sc->sc_dev.dv_xname, reg);
sys/dev/i2c/ds3231.c
154
dsxrtc_reg_write(struct dsxrtc_softc *sc, int reg, uint8_t val)
sys/dev/i2c/ds3231.c
156
uint8_t cmd = reg;
sys/dev/i2c/ds3231.c
166
sc->sc_dev.dv_xname, reg);
sys/dev/i2c/i2c_scan.c
358
u_int8_t reg, val;
sys/dev/i2c/i2c_scan.c
362
for (reg = 0x00; reg < 0x09; reg++) {
sys/dev/i2c/i2c_scan.c
363
if (iicprobe(reg) == 0xff)
sys/dev/i2c/i2c_scan.c
365
if (iicprobe(reg) == 0x00)
sys/dev/i2c/i2c_scan.c
367
if (val == iicprobe(reg))
sys/dev/i2c/i2c_scan.c
373
for (reg = 0x0a; reg < 0xfc; reg++) {
sys/dev/i2c/i2c_scan.c
374
if (iicprobe(reg) != val)
sys/dev/i2c/iatp.c
677
iatp_read_reg(struct iatp_softc *sc, uint16_t reg, size_t len, void *val)
sys/dev/i2c/iatp.c
679
uint8_t cmd[2] = { reg & 0xff, (reg >> 8) & 0xff };
sys/dev/i2c/iatp.c
693
iatp_write_reg(struct iatp_softc *sc, uint16_t reg, size_t len, void *val)
sys/dev/i2c/iatp.c
699
cmd[0] = reg & 0xff;
sys/dev/i2c/iatp.c
700
cmd[1] = (reg >> 8) & 0xff;
sys/dev/i2c/ietp.c
153
uint16_t buf, reg;
sys/dev/i2c/ietp.c
193
reg = pattern >= 0x01 ? IETP_IC_TYPE : IETP_OSM_VERSION;
sys/dev/i2c/ietp.c
194
if (ietp_iic_read_reg(sc, reg, sizeof(buf), &buf) != 0) {
sys/dev/i2c/ietp.c
391
ietp_iic_read_reg(struct ietp_softc *sc, uint16_t reg, size_t len, void *val)
sys/dev/i2c/ietp.c
394
reg & 0xff,
sys/dev/i2c/ietp.c
395
reg >> 8,
sys/dev/i2c/ietp.c
403
ietp_iic_write_reg(struct ietp_softc *sc, uint16_t reg, uint16_t val)
sys/dev/i2c/ietp.c
406
reg & 0xff,
sys/dev/i2c/ietp.c
407
reg >> 8,
sys/dev/i2c/isl1208.c
131
islrtc_reg_read(struct islrtc_softc *sc, int reg)
sys/dev/i2c/isl1208.c
133
uint8_t cmd = reg;
sys/dev/i2c/isl1208.c
144
sc->sc_dev.dv_xname, reg);
sys/dev/i2c/isl1208.c
152
islrtc_reg_write(struct islrtc_softc *sc, int reg, uint8_t val)
sys/dev/i2c/isl1208.c
154
uint8_t cmd = reg;
sys/dev/i2c/isl1208.c
164
sc->sc_dev.dv_xname, reg);
sys/dev/i2c/isl1208.c
215
uint8_t reg;
sys/dev/i2c/isl1208.c
231
reg = islrtc_reg_read(sc, ISL1208_SR);
sys/dev/i2c/isl1208.c
232
if (reg == 0xff) {
sys/dev/i2c/isl1208.c
236
islrtc_reg_write(sc, ISL1208_SR, reg | ISL1208_SR_WRTC);
sys/dev/i2c/isl1208.c
244
islrtc_reg_write(sc, ISL1208_SR, reg & ~ISL1208_SR_WRTC);
sys/dev/i2c/lis331dl.c
121
s[i].value = (int8_t)lisa_readreg(sc, lisa_axis[i].reg);
sys/dev/i2c/lis331dl.c
126
lisa_readreg(struct lisa_softc *sc, uint8_t reg)
sys/dev/i2c/lis331dl.c
131
sc->sc_addr, ®, sizeof reg, &data, sizeof data, 0);
sys/dev/i2c/lis331dl.c
137
lisa_writereg(struct lisa_softc *sc, uint8_t reg, uint8_t data)
sys/dev/i2c/lis331dl.c
140
sc->sc_addr, ®, sizeof reg, &data, sizeof data, 0);
sys/dev/i2c/lis331dl.c
37
const uint8_t reg;
sys/dev/i2c/lm78_i2c.c
106
cmd = reg;
sys/dev/i2c/lm78_i2c.c
116
lm_i2c_writereg(struct lm_softc *lmsc, int reg, int val)
sys/dev/i2c/lm78_i2c.c
123
cmd = reg;
sys/dev/i2c/lm78_i2c.c
99
lm_i2c_readreg(struct lm_softc *lmsc, int reg)
sys/dev/i2c/mcp794xx.c
136
mcprtc_reg_read(struct mcprtc_softc *sc, int reg)
sys/dev/i2c/mcp794xx.c
138
uint8_t cmd = reg;
sys/dev/i2c/mcp794xx.c
149
sc->sc_dev.dv_xname, reg);
sys/dev/i2c/mcp794xx.c
157
mcprtc_reg_write(struct mcprtc_softc *sc, int reg, uint8_t val)
sys/dev/i2c/mcp794xx.c
159
uint8_t cmd = reg;
sys/dev/i2c/mcp794xx.c
169
sc->sc_dev.dv_xname, reg);
sys/dev/i2c/mcp794xx.c
216
uint8_t reg;
sys/dev/i2c/mcp794xx.c
241
reg = mcprtc_reg_read(sc, oscoff);
sys/dev/i2c/mcp794xx.c
242
reg &= ~oscbit;
sys/dev/i2c/mcp794xx.c
243
mcprtc_reg_write(sc, oscoff, reg);
sys/dev/i2c/mcp794xx.c
246
reg = mcprtc_reg_read(sc, MCP794XX_DW);
sys/dev/i2c/mcp794xx.c
247
if ((reg & MCP794XX_DW_OSCRUN) == 0)
sys/dev/i2c/mcp794xx.c
262
reg = mcprtc_reg_read(sc, oscoff);
sys/dev/i2c/mcp794xx.c
263
reg |= oscbit;
sys/dev/i2c/mcp794xx.c
264
mcprtc_reg_write(sc, oscoff, reg);
sys/dev/i2c/pca9548.c
415
uint32_t reg[1];
sys/dev/i2c/pca9548.c
420
memset(reg, 0, sizeof(reg));
sys/dev/i2c/pca9548.c
427
if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
sys/dev/i2c/pca9548.c
432
ia.ia_addr = bemtoh32(®[0]);
sys/dev/i2c/pcf85063.c
109
uint8_t reg;
sys/dev/i2c/pcf85063.c
123
reg = pcyrtc_reg_read(sc, PCF85063_CONTROL1);
sys/dev/i2c/pcf85063.c
124
reg &= ~PCF85063_CONTROL1_12_24;
sys/dev/i2c/pcf85063.c
125
reg &= ~PCF85063_CONTROL1_STOP;
sys/dev/i2c/pcf85063.c
126
pcyrtc_reg_write(sc, PCF85063_CONTROL1, reg);
sys/dev/i2c/pcf85063.c
151
uint8_t reg;
sys/dev/i2c/pcf85063.c
158
reg = pcyrtc_reg_read(sc, PCF85063_SECONDS);
sys/dev/i2c/pcf85063.c
159
if (reg & PCF85063_SECONDS_OS) {
sys/dev/i2c/pcf85063.c
160
reg &= ~PCF85063_SECONDS_OS;
sys/dev/i2c/pcf85063.c
161
pcyrtc_reg_write(sc, PCF85063_SECONDS, reg);
sys/dev/i2c/pcf85063.c
168
pcyrtc_reg_read(struct pcyrtc_softc *sc, int reg)
sys/dev/i2c/pcf85063.c
170
uint8_t cmd = reg;
sys/dev/i2c/pcf85063.c
180
sc->sc_dev.dv_xname, reg);
sys/dev/i2c/pcf85063.c
188
pcyrtc_reg_write(struct pcyrtc_softc *sc, int reg, uint8_t val)
sys/dev/i2c/pcf85063.c
190
uint8_t cmd = reg;
sys/dev/i2c/pcf85063.c
197
sc->sc_dev.dv_xname, reg);
sys/dev/i2c/pcf8523.c
125
uint8_t reg;
sys/dev/i2c/pcf8523.c
141
reg = pcfrtc_reg_read(sc, PCF8523_CONTROL3);
sys/dev/i2c/pcf8523.c
142
reg &= ~PCF8523_CONTROL3_PM_MASK;
sys/dev/i2c/pcf8523.c
143
pcfrtc_reg_write(sc, PCF8523_CONTROL3, reg);
sys/dev/i2c/pcf8523.c
144
reg = pcfrtc_reg_read(sc, PCF8523_CONTROL1);
sys/dev/i2c/pcf8523.c
145
reg &= ~PCF8523_CONTROL1_12_24;
sys/dev/i2c/pcf8523.c
146
reg &= ~PCF8523_CONTROL1_STOP;
sys/dev/i2c/pcf8523.c
147
pcfrtc_reg_write(sc, PCF8523_CONTROL1, reg);
sys/dev/i2c/pcf8523.c
150
reg = pcfrtc_reg_read(sc, PCF8523_CONTROL3);
sys/dev/i2c/pcf8523.c
151
printf(": battery %s\n", (reg & PCF8523_CONTROL3_BLF) ? "low" : "ok");
sys/dev/i2c/pcf8523.c
174
uint8_t reg;
sys/dev/i2c/pcf8523.c
181
reg = pcfrtc_reg_read(sc, PCF8523_SECONDS);
sys/dev/i2c/pcf8523.c
182
if (reg & PCF8523_SECONDS_OS) {
sys/dev/i2c/pcf8523.c
183
reg &= ~PCF8523_SECONDS_OS;
sys/dev/i2c/pcf8523.c
184
pcfrtc_reg_write(sc, PCF8523_SECONDS, reg);
sys/dev/i2c/pcf8523.c
191
pcfrtc_reg_read(struct pcfrtc_softc *sc, int reg)
sys/dev/i2c/pcf8523.c
193
uint8_t cmd = reg;
sys/dev/i2c/pcf8523.c
203
sc->sc_dev.dv_xname, reg);
sys/dev/i2c/pcf8523.c
211
pcfrtc_reg_write(struct pcfrtc_softc *sc, int reg, uint8_t val)
sys/dev/i2c/pcf8523.c
213
uint8_t cmd = reg;
sys/dev/i2c/pcf8523.c
220
sc->sc_dev.dv_xname, reg);
sys/dev/i2c/pcf8563.c
112
uint8_t reg;
sys/dev/i2c/pcf8563.c
125
reg = pcxrtc_reg_read(sc, PCF8563_CONTROL1);
sys/dev/i2c/pcf8563.c
126
reg &= ~PCF8563_CONTROL1_STOP;
sys/dev/i2c/pcf8563.c
127
pcxrtc_reg_write(sc, PCF8563_CONTROL1, reg);
sys/dev/i2c/pcf8563.c
130
reg = pcxrtc_reg_read(sc, PCF8563_SECONDS);
sys/dev/i2c/pcf8563.c
131
printf(": battery %s\n", (reg & PCF8563_SECONDS_VL) ? "low" : "ok");
sys/dev/i2c/pcf8563.c
163
pcxrtc_reg_read(struct pcxrtc_softc *sc, int reg)
sys/dev/i2c/pcf8563.c
165
uint8_t cmd = reg;
sys/dev/i2c/pcf8563.c
173
sc->sc_dev.dv_xname, reg);
sys/dev/i2c/pcf8563.c
181
pcxrtc_reg_write(struct pcxrtc_softc *sc, int reg, uint8_t val)
sys/dev/i2c/pcf8563.c
183
uint8_t cmd = reg;
sys/dev/i2c/pcf8563.c
190
sc->sc_dev.dv_xname, reg);
sys/dev/i2c/rs5c372.c
226
ricohrtc_reg_write(struct ricohrtc_softc *sc, int reg, uint8_t val)
sys/dev/i2c/rs5c372.c
231
reg &= 0xf;
sys/dev/i2c/rs5c372.c
232
cmd = (reg << 4);
sys/dev/i2c/rs5c372.c
237
sc->sc_dev.dv_xname, reg);
sys/dev/i2c/spdmem_i2c.c
112
spdmem_iic_read(struct spdmem_softc *v, uint8_t reg)
sys/dev/i2c/spdmem_i2c.c
119
®, sizeof reg, &val, sizeof val, 0);
sys/dev/i2c/w83793g.c
280
wbng_readreg(struct wbng_softc *sc, uint8_t reg)
sys/dev/i2c/w83793g.c
285
sc->sc_addr, ®, sizeof reg, &data, sizeof data, 0);
sys/dev/i2c/w83793g.c
291
wbng_writereg(struct wbng_softc *sc, uint8_t reg, uint8_t data)
sys/dev/i2c/w83793g.c
294
sc->sc_addr, ®, sizeof reg, &data, sizeof data, 0);
sys/dev/i2c/w83795g.c
197
int i, reg;
sys/dev/i2c/w83795g.c
206
reg = NVT_VSEN1 + i;
sys/dev/i2c/w83795g.c
207
data = nvt_readreg(sc, reg);
sys/dev/i2c/w83795g.c
209
if (reg != NVT_3VDD && reg != NVT_3VSB && reg != NVT_VBAT)
sys/dev/i2c/w83795g.c
282
nvt_readreg(struct nvt_softc *sc, uint8_t reg)
sys/dev/i2c/w83795g.c
287
sc->sc_addr, ®, sizeof reg, &data, sizeof data, 0);
sys/dev/i2c/w83795g.c
293
nvt_writereg(struct nvt_softc *sc, uint8_t reg, uint8_t data)
sys/dev/i2c/w83795g.c
296
sc->sc_addr, ®, sizeof reg, &data, sizeof data, 0);
sys/dev/i2c/w83l784r.c
273
int data, reg = sc->sc_wbenv_sensors[n].reg;
sys/dev/i2c/w83l784r.c
275
data = wbenv_readreg(sc, reg);
sys/dev/i2c/w83l784r.c
285
int data, reg = sc->sc_wbenv_sensors[n].reg;
sys/dev/i2c/w83l784r.c
287
data = wbenv_readreg(sc, reg);
sys/dev/i2c/w83l784r.c
299
sdata = wbenv_readreg(sc, sc->sc_wbenv_sensors[n].reg);
sys/dev/i2c/w83l784r.c
313
sc->sc_addr[sc->sc_wbenv_sensors[n].reg],
sys/dev/i2c/w83l784r.c
325
if (sc->sc_wbenv_sensors[n].reg == W83L784R_FAN1)
sys/dev/i2c/w83l784r.c
330
data = wbenv_readreg(sc, sc->sc_wbenv_sensors[n].reg);
sys/dev/i2c/w83l784r.c
347
if (sc->sc_wbenv_sensors[n].reg == W83L784R_FAN1)
sys/dev/i2c/w83l784r.c
352
data = wbenv_readreg(sc, sc->sc_wbenv_sensors[n].reg);
sys/dev/i2c/w83l784r.c
363
wbenv_readreg(struct wbenv_softc *sc, u_int8_t reg)
sys/dev/i2c/w83l784r.c
368
sc->sc_addr[0], ®, sizeof reg, &data, sizeof data, 0);
sys/dev/i2c/w83l784r.c
374
wbenv_writereg(struct wbenv_softc *sc, u_int8_t reg, u_int8_t data)
sys/dev/i2c/w83l784r.c
377
sc->sc_addr[0], ®, sizeof reg, &data, sizeof data, 0);
sys/dev/i2c/w83l784r.c
69
u_int8_t reg;
sys/dev/ic/aacvar.h
202
#define AAC_SETREG4(sc, reg, val) \
sys/dev/ic/aacvar.h
203
bus_space_write_4((sc)->aac_memt, (sc)->aac_memh, (reg), (val))
sys/dev/ic/aacvar.h
204
#define AAC_GETREG4(sc, reg) \
sys/dev/ic/aacvar.h
205
bus_space_read_4((sc)->aac_memt, (sc)->aac_memh, (reg))
sys/dev/ic/aacvar.h
206
#define AAC_SETREG2(sc, reg, val) \
sys/dev/ic/aacvar.h
207
bus_space_write_2((sc)->aac_memt, (sc)->aac_memh, (reg), (val))
sys/dev/ic/aacvar.h
208
#define AAC_GETREG2(sc, reg) \
sys/dev/ic/aacvar.h
209
bus_space_read_2((sc)->aac_memt, (sc)->aac_memh, (reg))
sys/dev/ic/aacvar.h
210
#define AAC_SETREG1(sc, reg, val) \
sys/dev/ic/aacvar.h
211
bus_space_write_1((sc)->aac_memt, (sc)->aac_memh, (reg), (val))
sys/dev/ic/aacvar.h
212
#define AAC_GETREG1(sc, reg) \
sys/dev/ic/aacvar.h
213
bus_space_read_1((sc)->aac_memt, (sc)->aac_memh, (reg))
sys/dev/ic/ac97.c
1052
si->reg == AC97_REG_EXT_AUDIO_CTRL;
sys/dev/ic/ac97.c
1056
ac97_read(as, si->reg, &val);
sys/dev/ic/ac97.c
1058
DPRINTFN(5, ("read(%x) = %x\n", si->reg, val));
sys/dev/ic/ac97.c
1068
if (si->reg == AC97_REG_RECORD_SELECT) {
sys/dev/ic/ac97.c
1072
} else if (si->reg == AC97_REG_SURR_MASTER) {
sys/dev/ic/ac97.c
1125
error = ac97_write(as, si->reg, (val & ~mask) | newval);
sys/dev/ic/ac97.c
130
u_int8_t reg;
sys/dev/ic/ac97.c
1331
ac97_read(as, si->reg, &val);
sys/dev/ic/ac97.c
1333
DPRINTFN(5, ("read(%x) = %x\n", si->reg, val));
sys/dev/ic/ac97.c
1406
if (as->source_info[i].reg == AC97_REG_HEADPHONE_VOLUME)
sys/dev/ic/ac97.c
1407
as->source_info[i].reg = AC97_REG_MASTER_VOLUME;
sys/dev/ic/ac97.c
1408
else if (as->source_info[i].reg == AC97_REG_MASTER_VOLUME)
sys/dev/ic/ac97.c
1409
as->source_info[i].reg = AC97_REG_HEADPHONE_VOLUME;
sys/dev/ic/ac97.c
1435
if (as->source_info[i].reg == AC97_REG_SURR_MASTER)
sys/dev/ic/ac97.c
1436
as->source_info[i].reg = AC97_REG_MASTER_VOLUME;
sys/dev/ic/ac97.c
1437
else if (as->source_info[i].reg == AC97_REG_MASTER_VOLUME)
sys/dev/ic/ac97.c
1438
as->source_info[i].reg = AC97_REG_SURR_MASTER;
sys/dev/ic/ac97.c
1488
u_int16_t reg;
sys/dev/ic/ac97.c
1491
ac97_read(as, AC97_VT_REG_TEST, ®);
sys/dev/ic/ac97.c
1494
reg &= ~(AC97_VT_LVL);
sys/dev/ic/ac97.c
1497
reg &= ~(AC97_VT_LCTF | AC97_VT_STF);
sys/dev/ic/ac97.c
1500
reg |= AC97_VT_BPDC;
sys/dev/ic/ac97.c
1502
ac97_write(as, AC97_VT_REG_TEST, reg);
sys/dev/ic/ac97.c
598
ac97_read(struct ac97_softc *as, u_int8_t reg, u_int16_t *val)
sys/dev/ic/ac97.c
603
(reg != AC97_REG_VENDOR_ID1 && reg != AC97_REG_VENDOR_ID2 &&
sys/dev/ic/ac97.c
604
reg != AC97_REG_RESET)) ||
sys/dev/ic/ac97.c
606
*val = as->shadow_reg[reg >> 1];
sys/dev/ic/ac97.c
610
if ((error = as->host_if->read(as->host_if->arg, reg, val)))
sys/dev/ic/ac97.c
611
*val = as->shadow_reg[reg >> 1];
sys/dev/ic/ac97.c
616
ac97_write(struct ac97_softc *as, u_int8_t reg, u_int16_t val)
sys/dev/ic/ac97.c
618
as->shadow_reg[reg >> 1] = val;
sys/dev/ic/ac97.c
619
return (as->host_if->write(as->host_if->arg, reg, val));
sys/dev/ic/ac97.c
632
ac97_write(as, si->reg, si->default_value);
sys/dev/ic/ac97.h
47
int (*read)(void *arg, u_int8_t reg, u_int16_t *val);
sys/dev/ic/ac97.h
48
int (*write)(void *arg, u_int8_t reg, u_int16_t val);
sys/dev/ic/ac97.h
96
#define AC97_CAPS_ENHANCEMENT(reg) (((reg) >> 10) & 0x1f)
sys/dev/ic/acx.c
1427
uint16_t reg;
sys/dev/ic/acx.c
1433
reg = CSR_READ_2(sc, ACXREG_SOFT_RESET);
sys/dev/ic/acx.c
1434
CSR_WRITE_2(sc, ACXREG_SOFT_RESET, reg | ACXRV_SOFT_RESET);
sys/dev/ic/acx.c
1436
CSR_WRITE_2(sc, ACXREG_SOFT_RESET, reg);
sys/dev/ic/acx.c
1443
reg = CSR_READ_2(sc, ACXREG_ECPU_CTRL);
sys/dev/ic/acx.c
1444
if (!(reg & ACXRV_ECPU_HALT)) {
sys/dev/ic/acx.c
1480
acx_read_phyreg(struct acx_softc *sc, uint32_t reg, uint8_t *val)
sys/dev/ic/acx.c
1485
CSR_WRITE_4(sc, ACXREG_PHY_ADDR, reg);
sys/dev/ic/acx.c
1496
ifp->if_xname, reg);
sys/dev/ic/acx.c
1507
acx_write_phyreg(struct acx_softc *sc, uint32_t reg, uint8_t val)
sys/dev/ic/acx.c
1510
CSR_WRITE_4(sc, ACXREG_PHY_ADDR, reg);
sys/dev/ic/acx.c
1546
uint16_t reg;
sys/dev/ic/acx.c
1548
reg = CSR_READ_2(sc, ACXREG_INTR_STATUS);
sys/dev/ic/acx.c
1549
if (reg & ACXRV_INTR_FCS_THRESH) {
sys/dev/ic/acx.c
2624
uint16_t reg;
sys/dev/ic/acx.c
2626
reg = CSR_READ_2(sc, ACXREG_INTR_STATUS);
sys/dev/ic/acx.c
2627
if (reg & ACXRV_INTR_CMD_FINI) {
sys/dev/ic/acxreg.h
88
#define ACXREG(reg, val) [ACXREG_##reg] = val
sys/dev/ic/acxvar.h
76
#define CSR_READ_1(sc, reg) \
sys/dev/ic/acxvar.h
78
(sc)->chip_ioreg[(reg)])
sys/dev/ic/acxvar.h
79
#define CSR_READ_2(sc, reg) \
sys/dev/ic/acxvar.h
81
(sc)->chip_ioreg[(reg)])
sys/dev/ic/acxvar.h
82
#define CSR_READ_4(sc, reg) \
sys/dev/ic/acxvar.h
84
(sc)->chip_ioreg[(reg)])
sys/dev/ic/acxvar.h
86
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/ic/acxvar.h
88
(sc)->chip_ioreg[(reg)], val)
sys/dev/ic/acxvar.h
89
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/ic/acxvar.h
91
(sc)->chip_ioreg[(reg)], val)
sys/dev/ic/acxvar.h
93
#define CSR_SETB_2(sc, reg, b) \
sys/dev/ic/acxvar.h
94
CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (b))
sys/dev/ic/acxvar.h
95
#define CSR_CLRB_2(sc, reg, b) \
sys/dev/ic/acxvar.h
96
CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & (~(b)))
sys/dev/ic/ahci.c
403
u_int32_t reg, cap, pi;
sys/dev/ic/ahci.c
433
reg = ahci_read(sc, AHCI_REG_VS);
sys/dev/ic/ahci.c
434
switch (reg) {
sys/dev/ic/ahci.c
455
printf(" unsupported AHCI revision 0x%08x\n", reg);
sys/dev/ic/aic6915.c
107
#define sf_funcreg_read(sc, reg) \
sys/dev/ic/aic6915.c
108
bus_space_read_4((sc)->sc_st, (sc)->sc_sh_func, (reg))
sys/dev/ic/aic6915.c
109
#define sf_funcreg_write(sc, reg, val) \
sys/dev/ic/aic6915.c
110
bus_space_write_4((sc)->sc_st, (sc)->sc_sh_func, (reg), (val))
sys/dev/ic/aic6915.c
113
sf_reg_read(struct sf_softc *sc, bus_addr_t reg)
sys/dev/ic/aic6915.c
118
reg);
sys/dev/ic/aic6915.c
1195
uint32_t reg;
sys/dev/ic/aic6915.c
1197
reg = sf_genreg_read(sc, SF_EEPROM_BASE + (offset & ~3));
sys/dev/ic/aic6915.c
1199
return ((reg >> (8 * (offset & 3))) & 0xff);
sys/dev/ic/aic6915.c
123
return (bus_space_read_4(sc->sc_st, sc->sc_sh, reg));
sys/dev/ic/aic6915.c
1263
uint32_t hash, slot, reg;
sys/dev/ic/aic6915.c
1268
reg = sf_genreg_read(sc, SF_HASH_BASE + (slot * 0x10));
sys/dev/ic/aic6915.c
1269
reg |= 1 << (hash & 0xf);
sys/dev/ic/aic6915.c
127
sf_reg_write(struct sf_softc *sc, bus_addr_t reg, uint32_t val)
sys/dev/ic/aic6915.c
1270
sf_genreg_write(sc, SF_HASH_BASE + (slot * 0x10), reg);
sys/dev/ic/aic6915.c
132
reg);
sys/dev/ic/aic6915.c
1361
sf_mii_read(struct device *self, int phy, int reg)
sys/dev/ic/aic6915.c
1368
v = sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg));
sys/dev/ic/aic6915.c
138
bus_space_write_4(sc->sc_st, sc->sc_sh, reg, val);
sys/dev/ic/aic6915.c
1389
sf_mii_write(struct device *self, int phy, int reg, int val)
sys/dev/ic/aic6915.c
1394
sf_genreg_write(sc, SF_MII_PHY_REG(phy, reg), val);
sys/dev/ic/aic6915.c
1397
if ((sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg)) &
sys/dev/ic/aic6915.c
141
#define sf_genreg_read(sc, reg) \
sys/dev/ic/aic6915.c
142
sf_reg_read((sc), (reg) + SF_GENREG_OFFSET)
sys/dev/ic/aic6915.c
143
#define sf_genreg_write(sc, reg, val) \
sys/dev/ic/aic6915.c
144
sf_reg_write((sc), (reg) + SF_GENREG_OFFSET, (val))
sys/dev/ic/aic7xxx_openbsd.h
321
ahc_pci_read_config(ahc_dev_softc_t pci, int reg, int width)
sys/dev/ic/aic7xxx_openbsd.h
323
return (pci_conf_read(pci->pa_pc, pci->pa_tag, reg));
sys/dev/ic/aic7xxx_openbsd.h
327
ahc_pci_write_config(ahc_dev_softc_t pci, int reg, uint32_t value, int width)
sys/dev/ic/aic7xxx_openbsd.h
329
pci_conf_write(pci->pa_pc, pci->pa_tag, reg, value);
sys/dev/ic/anvar.h
49
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/ic/anvar.h
50
bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val)
sys/dev/ic/anvar.h
52
#define CSR_READ_2(sc, reg) \
sys/dev/ic/anvar.h
53
bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg)
sys/dev/ic/anvar.h
60
#define CSR_WRITE_MULTI_STREAM_2(sc, reg, val, count) \
sys/dev/ic/anvar.h
61
bus_space_write_multi_stream_2(sc->sc_iot, sc->sc_ioh, reg, val, count)
sys/dev/ic/anvar.h
62
#define CSR_READ_MULTI_STREAM_2(sc, reg, buf, count) \
sys/dev/ic/anvar.h
63
bus_space_read_multi_stream_2(sc->sc_iot, sc->sc_ioh, reg, buf, count)
sys/dev/ic/ar5008.c
1215
uint32_t reg;
sys/dev/ic/ar5008.c
1218
reg = AR_READ(sc, AR_ISR_S0_S);
sys/dev/ic/ar5008.c
1219
mask |= MS(reg, AR_ISR_S0_QCU_TXOK);
sys/dev/ic/ar5008.c
1220
mask |= MS(reg, AR_ISR_S0_QCU_TXDESC);
sys/dev/ic/ar5008.c
1222
reg = AR_READ(sc, AR_ISR_S1_S);
sys/dev/ic/ar5008.c
1223
mask |= MS(reg, AR_ISR_S1_QCU_TXERR);
sys/dev/ic/ar5008.c
1224
mask |= MS(reg, AR_ISR_S1_QCU_TXEOL);
sys/dev/ic/ar5008.c
1830
uint32_t reg;
sys/dev/ic/ar5008.c
1832
reg = IEEE80211_IS_CHAN_2GHZ(c) ?
sys/dev/ic/ar5008.c
1835
reg |= IEEE80211_IS_CHAN_2GHZ(c) ?
sys/dev/ic/ar5008.c
1839
reg |= AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE;
sys/dev/ic/ar5008.c
1841
AR_WRITE(sc, AR_PHY_MODE, reg);
sys/dev/ic/ar5008.c
1918
uint32_t coeff, exp, man, reg;
sys/dev/ic/ar5008.c
1925
reg = AR_READ(sc, AR_PHY_TIMING3);
sys/dev/ic/ar5008.c
1926
reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp);
sys/dev/ic/ar5008.c
1927
reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man);
sys/dev/ic/ar5008.c
1928
AR_WRITE(sc, AR_PHY_TIMING3, reg);
sys/dev/ic/ar5008.c
1935
reg = AR_READ(sc, AR_PHY_HALFGI);
sys/dev/ic/ar5008.c
1936
reg = RW(reg, AR_PHY_HALFGI_DSC_EXP, exp);
sys/dev/ic/ar5008.c
1937
reg = RW(reg, AR_PHY_HALFGI_DSC_MAN, man);
sys/dev/ic/ar5008.c
1938
AR_WRITE(sc, AR_PHY_HALFGI, reg);
sys/dev/ic/ar5008.c
2003
uint32_t reg;
sys/dev/ic/ar5008.c
2007
reg = AR_READ(sc, AR_PHY_CCA(i));
sys/dev/ic/ar5008.c
2009
nf[i] = MS(reg, AR9280_PHY_MINCCA_PWR);
sys/dev/ic/ar5008.c
2011
nf[i] = MS(reg, AR_PHY_MINCCA_PWR);
sys/dev/ic/ar5008.c
2014
reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
sys/dev/ic/ar5008.c
2016
nf_ext[i] = MS(reg, AR9280_PHY_EXT_MINCCA_PWR);
sys/dev/ic/ar5008.c
2018
nf_ext[i] = MS(reg, AR_PHY_EXT_MINCCA_PWR);
sys/dev/ic/ar5008.c
2027
uint32_t reg;
sys/dev/ic/ar5008.c
2031
reg = AR_READ(sc, AR_PHY_CCA(i));
sys/dev/ic/ar5008.c
2032
reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]);
sys/dev/ic/ar5008.c
2033
AR_WRITE(sc, AR_PHY_CCA(i), reg);
sys/dev/ic/ar5008.c
2035
reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
sys/dev/ic/ar5008.c
2036
reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);
sys/dev/ic/ar5008.c
2037
AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg);
sys/dev/ic/ar5008.c
2145
uint32_t mode, reg;
sys/dev/ic/ar5008.c
2148
reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0);
sys/dev/ic/ar5008.c
2150
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, log);
sys/dev/ic/ar5008.c
2151
AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg);
sys/dev/ic/ar5008.c
2188
uint32_t reg, i_coff_denom, q_coff_denom;
sys/dev/ic/ar5008.c
2236
reg = AR_READ(sc, AR_PHY_TIMING_CTRL4(i));
sys/dev/ic/ar5008.c
2237
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, i_coff);
sys/dev/ic/ar5008.c
2238
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, q_coff);
sys/dev/ic/ar5008.c
2239
AR_WRITE(sc, AR_PHY_TIMING_CTRL4(i), reg);
sys/dev/ic/ar5008.c
2256
uint32_t reg, gain_mismatch_i, gain_mismatch_q;
sys/dev/ic/ar5008.c
2287
reg = AR_READ(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
sys/dev/ic/ar5008.c
2288
reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IGAIN, gain_mismatch_i);
sys/dev/ic/ar5008.c
2289
reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QGAIN, gain_mismatch_q);
sys/dev/ic/ar5008.c
2290
AR_WRITE(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), reg);
sys/dev/ic/ar5008.c
2308
uint32_t reg;
sys/dev/ic/ar5008.c
2340
reg = AR_READ(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
sys/dev/ic/ar5008.c
2341
reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QDC,
sys/dev/ic/ar5008.c
2343
reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IDC,
sys/dev/ic/ar5008.c
2345
AR_WRITE(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), reg);
sys/dev/ic/ar5008.c
2412
uint32_t mask[4], reg;
sys/dev/ic/ar5008.c
2448
reg =
sys/dev/ic/ar5008.c
2453
AR_WRITE(sc, AR_PHY_BIN_MASK_1, reg);
sys/dev/ic/ar5008.c
2454
AR_WRITE(sc, AR_PHY_VIT_MASK2_M_46_61, reg);
sys/dev/ic/ar5008.c
2457
reg = m[31] << 28 | m[32] << 26 | m[33] << 24 |
sys/dev/ic/ar5008.c
2461
AR_WRITE(sc, AR_PHY_BIN_MASK_2, reg);
sys/dev/ic/ar5008.c
2462
AR_WRITE(sc, AR_PHY_VIT_MASK2_M_31_45, reg);
sys/dev/ic/ar5008.c
2465
reg =
sys/dev/ic/ar5008.c
2470
AR_WRITE(sc, AR_PHY_BIN_MASK_3, reg);
sys/dev/ic/ar5008.c
2471
AR_WRITE(sc, AR_PHY_VIT_MASK2_M_16_30, reg);
sys/dev/ic/ar5008.c
2473
reg =
sys/dev/ic/ar5008.c
2478
AR_WRITE(sc, AR_PHY_MASK_CTL, reg);
sys/dev/ic/ar5008.c
2479
AR_WRITE(sc, AR_PHY_VIT_MASK2_M_00_15, reg);
sys/dev/ic/ar5008.c
2481
reg = p[15] << 28 | p[14] << 26 | p[13] << 24 |
sys/dev/ic/ar5008.c
2485
AR_WRITE(sc, AR_PHY_BIN_MASK2_1, reg);
sys/dev/ic/ar5008.c
2486
AR_WRITE(sc, AR_PHY_VIT_MASK2_P_15_01, reg);
sys/dev/ic/ar5008.c
2488
reg = p[30] << 28 | p[29] << 26 | p[28] << 24 |
sys/dev/ic/ar5008.c
2492
AR_WRITE(sc, AR_PHY_BIN_MASK2_2, reg);
sys/dev/ic/ar5008.c
2493
AR_WRITE(sc, AR_PHY_VIT_MASK2_P_30_16, reg);
sys/dev/ic/ar5008.c
2495
reg = p[45] << 28 | p[44] << 26 | p[43] << 24 |
sys/dev/ic/ar5008.c
2499
AR_WRITE(sc, AR_PHY_BIN_MASK2_3, reg);
sys/dev/ic/ar5008.c
2500
AR_WRITE(sc, AR_PHY_VIT_MASK2_P_45_31, reg);
sys/dev/ic/ar5008.c
2502
reg =
sys/dev/ic/ar5008.c
2507
AR_WRITE(sc, AR_PHY_BIN_MASK2_4, reg);
sys/dev/ic/ar5008.c
2508
AR_WRITE(sc, AR_PHY_VIT_MASK2_P_61_46, reg);
sys/dev/ic/ar5008.c
2519
uint32_t reg;
sys/dev/ic/ar5008.c
2614
reg = AR_READ(sc, AR_PCU_MISC_MODE2);
sys/dev/ic/ar5008.c
2616
reg &= ~AR_PCU_MISC_MODE2_HWWAR1;
sys/dev/ic/ar5008.c
2618
reg &= ~AR_PCU_MISC_MODE2_HWWAR2;
sys/dev/ic/ar5008.c
2619
AR_WRITE(sc, AR_PCU_MISC_MODE2, reg);
sys/dev/ic/ar5008.c
281
uint32_t reg;
sys/dev/ic/ar5008.c
284
reg = AR_READ(sc, AR_EEPROM_OFFSET(addr));
sys/dev/ic/ar5008.c
2847
uint32_t reg;
sys/dev/ic/ar5008.c
2849
reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
sys/dev/ic/ar5008.c
2850
reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55);
sys/dev/ic/ar5008.c
2851
AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
sys/dev/ic/ar5008.c
2853
reg = AR_READ(sc, AR_PHY_AGC_CTL1);
sys/dev/ic/ar5008.c
2854
reg = RW(reg, AR_PHY_AGC_CTL1_COARSE_LOW, high ? -70 : -64);
sys/dev/ic/ar5008.c
2855
reg = RW(reg, AR_PHY_AGC_CTL1_COARSE_HIGH, high ? -12 : -14);
sys/dev/ic/ar5008.c
2856
AR_WRITE(sc, AR_PHY_AGC_CTL1, reg);
sys/dev/ic/ar5008.c
2858
reg = AR_READ(sc, AR_PHY_FIND_SIG);
sys/dev/ic/ar5008.c
2859
reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78);
sys/dev/ic/ar5008.c
286
reg = AR_READ(sc, AR_EEPROM_STATUS_DATA);
sys/dev/ic/ar5008.c
2860
AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
sys/dev/ic/ar5008.c
2868
uint32_t reg;
sys/dev/ic/ar5008.c
287
if (!(reg & (AR_EEPROM_STATUS_DATA_BUSY |
sys/dev/ic/ar5008.c
2870
reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
sys/dev/ic/ar5008.c
2871
reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50);
sys/dev/ic/ar5008.c
2872
reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40);
sys/dev/ic/ar5008.c
2873
reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48);
sys/dev/ic/ar5008.c
2874
AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
sys/dev/ic/ar5008.c
2876
reg = AR_READ(sc, AR_PHY_SFCORR);
sys/dev/ic/ar5008.c
2877
reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77);
sys/dev/ic/ar5008.c
2878
reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64);
sys/dev/ic/ar5008.c
2879
reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16);
sys/dev/ic/ar5008.c
2880
AR_WRITE(sc, AR_PHY_SFCORR, reg);
sys/dev/ic/ar5008.c
2882
reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
sys/dev/ic/ar5008.c
2883
reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50);
sys/dev/ic/ar5008.c
2884
reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40);
sys/dev/ic/ar5008.c
2885
reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77);
sys/dev/ic/ar5008.c
2886
reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64);
sys/dev/ic/ar5008.c
2887
AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
sys/dev/ic/ar5008.c
289
*val = MS(reg, AR_EEPROM_STATUS_DATA_VAL);
sys/dev/ic/ar5008.c
2897
uint32_t reg;
sys/dev/ic/ar5008.c
2899
reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
sys/dev/ic/ar5008.c
2900
reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127);
sys/dev/ic/ar5008.c
2901
reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127);
sys/dev/ic/ar5008.c
2902
reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63);
sys/dev/ic/ar5008.c
2903
AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
sys/dev/ic/ar5008.c
2905
reg = AR_READ(sc, AR_PHY_SFCORR);
sys/dev/ic/ar5008.c
2906
reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127);
sys/dev/ic/ar5008.c
2907
reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127);
sys/dev/ic/ar5008.c
2908
reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31);
sys/dev/ic/ar5008.c
2909
AR_WRITE(sc, AR_PHY_SFCORR, reg);
sys/dev/ic/ar5008.c
2911
reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
sys/dev/ic/ar5008.c
2912
reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127);
sys/dev/ic/ar5008.c
2913
reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127);
sys/dev/ic/ar5008.c
2914
reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127);
sys/dev/ic/ar5008.c
2915
reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127);
sys/dev/ic/ar5008.c
2916
AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
sys/dev/ic/ar5008.c
2926
uint32_t reg;
sys/dev/ic/ar5008.c
2928
reg = AR_READ(sc, AR_PHY_CCK_DETECT);
sys/dev/ic/ar5008.c
2929
reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8);
sys/dev/ic/ar5008.c
2930
AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
sys/dev/ic/ar5008.c
2937
uint32_t reg;
sys/dev/ic/ar5008.c
2939
reg = AR_READ(sc, AR_PHY_FIND_SIG);
sys/dev/ic/ar5008.c
2940
reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4);
sys/dev/ic/ar5008.c
2941
AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
sys/dev/ic/ar5008.c
2948
uint32_t reg;
sys/dev/ic/ar5008.c
2950
reg = AR_READ(sc, AR_PHY_TIMING5);
sys/dev/ic/ar5008.c
2951
reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2);
sys/dev/ic/ar5008.c
2952
AR_WRITE(sc, AR_PHY_TIMING5, reg);
sys/dev/ic/ar5008.c
382
uint32_t reg;
sys/dev/ic/ar5008.c
391
reg = AR_READ(sc, AR7010_GPIO_OUT);
sys/dev/ic/ar5008.c
393
reg |= 1 << pin;
sys/dev/ic/ar5008.c
395
reg &= ~(1 << pin);
sys/dev/ic/ar5008.c
396
AR_WRITE(sc, AR7010_GPIO_OUT, reg);
sys/dev/ic/ar5008.c
398
reg = AR_READ(sc, AR_GPIO_IN_OUT);
sys/dev/ic/ar5008.c
400
reg |= 1 << pin;
sys/dev/ic/ar5008.c
402
reg &= ~(1 << pin);
sys/dev/ic/ar5008.c
403
AR_WRITE(sc, AR_GPIO_IN_OUT, reg);
sys/dev/ic/ar5008.c
411
uint32_t reg;
sys/dev/ic/ar5008.c
417
reg = AR_READ(sc, AR_GPIO_OE_OUT);
sys/dev/ic/ar5008.c
418
reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
sys/dev/ic/ar5008.c
419
reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2);
sys/dev/ic/ar5008.c
420
AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
sys/dev/ic/ar5008.c
428
uint32_t reg;
sys/dev/ic/ar5008.c
440
reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux));
sys/dev/ic/ar5008.c
442
reg = (reg & ~0x1f0) | (reg & 0x1f0) << 1;
sys/dev/ic/ar5008.c
443
reg &= ~(0x1f << (off * 5));
sys/dev/ic/ar5008.c
444
reg |= (type & 0x1f) << (off * 5);
sys/dev/ic/ar5008.c
445
AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg);
sys/dev/ic/ar5008.c
447
reg = AR_READ(sc, AR_GPIO_OE_OUT);
sys/dev/ic/ar5008.c
448
reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
sys/dev/ic/ar5008.c
449
reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2);
sys/dev/ic/ar5008.c
450
AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
sys/dev/ic/ar5008.c
457
uint32_t reg;
sys/dev/ic/ar5008.c
461
reg = AR_READ(sc, AR_GPIO_INPUT_MUX2);
sys/dev/ic/ar5008.c
462
reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);
sys/dev/ic/ar5008.c
463
AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg);
sys/dev/ic/ar5008reg.h
43
#define AR_IS_ANALOG_REG(reg) ((reg) >= 0x7800 && (reg) <= 0x78b4)
sys/dev/ic/ar5416.c
186
uint32_t phy, reg;
sys/dev/ic/ar5416.c
201
reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
sys/dev/ic/ar5416.c
203
reg |= AR_PHY_CCK_TX_CTRL_JAPAN;
sys/dev/ic/ar5416.c
205
reg &= ~AR_PHY_CCK_TX_CTRL_JAPAN;
sys/dev/ic/ar5416.c
206
AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
sys/dev/ic/ar5416.c
243
uint32_t reg, offset;
sys/dev/ic/ar5416.c
261
reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
sys/dev/ic/ar5416.c
262
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
sys/dev/ic/ar5416.c
264
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
sys/dev/ic/ar5416.c
266
AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
sys/dev/ic/ar5416.c
272
reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
sys/dev/ic/ar5416.c
273
reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_MARGIN,
sys/dev/ic/ar5416.c
275
reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_ATTEN,
sys/dev/ic/ar5416.c
277
AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
sys/dev/ic/ar5416.c
283
reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
sys/dev/ic/ar5416.c
284
reg = RW(reg, AR_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);
sys/dev/ic/ar5416.c
285
AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
sys/dev/ic/ar5416.c
287
reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
sys/dev/ic/ar5416.c
288
reg = RW(reg, AR_PHY_GAIN_2GHZ_RXTX_MARGIN,
sys/dev/ic/ar5416.c
290
AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
sys/dev/ic/ar5416.c
292
reg = AR_READ(sc, AR_PHY_SETTLING);
sys/dev/ic/ar5416.c
293
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
sys/dev/ic/ar5416.c
294
AR_WRITE(sc, AR_PHY_SETTLING, reg);
sys/dev/ic/ar5416.c
296
reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
sys/dev/ic/ar5416.c
297
reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
sys/dev/ic/ar5416.c
298
reg = RW(reg, AR_PHY_DESIRED_SZ_PGA, modal->pgaDesiredSize);
sys/dev/ic/ar5416.c
299
AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
sys/dev/ic/ar5416.c
301
reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
sys/dev/ic/ar5416.c
302
reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
sys/dev/ic/ar5416.c
303
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
sys/dev/ic/ar5416.c
304
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
sys/dev/ic/ar5416.c
305
AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
sys/dev/ic/ar5416.c
307
reg = AR_READ(sc, AR_PHY_RF_CTL3);
sys/dev/ic/ar5416.c
308
reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
sys/dev/ic/ar5416.c
309
AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
sys/dev/ic/ar5416.c
311
reg = AR_READ(sc, AR_PHY_CCA(0));
sys/dev/ic/ar5416.c
312
reg = RW(reg, AR_PHY_CCA_THRESH62, modal->thresh62);
sys/dev/ic/ar5416.c
313
AR_WRITE(sc, AR_PHY_CCA(0), reg);
sys/dev/ic/ar5416.c
315
reg = AR_READ(sc, AR_PHY_EXT_CCA(0));
sys/dev/ic/ar5416.c
316
reg = RW(reg, AR_PHY_EXT_CCA_THRESH62, modal->thresh62);
sys/dev/ic/ar5416.c
317
AR_WRITE(sc, AR_PHY_EXT_CCA(0), reg);
sys/dev/ic/ar5416.c
320
reg = AR_READ(sc, AR_PHY_RF_CTL2);
sys/dev/ic/ar5416.c
321
reg = RW(reg, AR_PHY_TX_END_DATA_START,
sys/dev/ic/ar5416.c
323
reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
sys/dev/ic/ar5416.c
324
AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
sys/dev/ic/ar5416.c
328
reg = AR_READ(sc, AR_PHY_SETTLING);
sys/dev/ic/ar5416.c
329
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
sys/dev/ic/ar5416.c
330
AR_WRITE(sc, AR_PHY_SETTLING, reg);
sys/dev/ic/ar5416.c
436
uint32_t reg, offset;
sys/dev/ic/ar5416.c
462
reg = AR_READ(sc, AR_PHY_TPCRG1);
sys/dev/ic/ar5416.c
463
reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);
sys/dev/ic/ar5416.c
464
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);
sys/dev/ic/ar5416.c
465
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);
sys/dev/ic/ar5416.c
466
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_3, xpdgains[2]);
sys/dev/ic/ar5416.c
467
AR_WRITE(sc, AR_PHY_TPCRG1, reg);
sys/dev/ic/ar5416.c
483
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_0);
sys/dev/ic/ar5416.c
484
reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
sys/dev/ic/ar5416.c
485
AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg);
sys/dev/ic/ar5416.c
487
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_1);
sys/dev/ic/ar5416.c
488
reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
sys/dev/ic/ar5416.c
489
AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg);
sys/dev/ic/ar5416.c
491
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL7);
sys/dev/ic/ar5416.c
492
reg = RW(reg, AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, txgain);
sys/dev/ic/ar5416.c
493
AR_WRITE(sc, AR_PHY_TX_PWRCTRL7, reg);
sys/dev/ic/ar5416.c
502
reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP,
sys/dev/ic/ar5416.c
504
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1,
sys/dev/ic/ar5416.c
506
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2,
sys/dev/ic/ar5416.c
508
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3,
sys/dev/ic/ar5416.c
510
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4,
sys/dev/ic/ar5416.c
512
AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg);
sys/dev/ic/ar5416.c
739
uint8_t rev, reg;
sys/dev/ic/ar5416.c
748
reg = (AR_READ(sc, AR_PHY(256)) >> 24) & 0xff;
sys/dev/ic/ar5416.c
749
reg = (reg & 0xf0) >> 4 | (reg & 0x0f) << 4;
sys/dev/ic/ar5416.c
751
rev = ar5416_reverse_bits(reg, 8);
sys/dev/ic/ar5xxx.c
1271
ar5k_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t bits,
sys/dev/ic/ar5xxx.c
1292
data = ar5k_bitswap(reg, bits);
sys/dev/ic/ar5xxx.c
646
ar5k_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag,
sys/dev/ic/ar5xxx.c
653
data = AR5K_REG_READ(reg);
sys/dev/ic/ar9003.c
1772
uint32_t reg;
sys/dev/ic/ar9003.c
1774
reg = IEEE80211_IS_CHAN_2GHZ(c) ?
sys/dev/ic/ar9003.c
1778
reg |= AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE;
sys/dev/ic/ar9003.c
1780
AR_WRITE(sc, AR_PHY_MODE, reg);
sys/dev/ic/ar9003.c
1856
uint32_t coeff, exp, man, reg;
sys/dev/ic/ar9003.c
1863
reg = AR_READ(sc, AR_PHY_TIMING3);
sys/dev/ic/ar9003.c
1864
reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp);
sys/dev/ic/ar9003.c
1865
reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man);
sys/dev/ic/ar9003.c
1866
AR_WRITE(sc, AR_PHY_TIMING3, reg);
sys/dev/ic/ar9003.c
1873
reg = AR_READ(sc, AR_PHY_SGI_DELTA);
sys/dev/ic/ar9003.c
1874
reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp);
sys/dev/ic/ar9003.c
1875
reg = RW(reg, AR_PHY_SGI_DSC_MAN, man);
sys/dev/ic/ar9003.c
1876
AR_WRITE(sc, AR_PHY_SGI_DELTA, reg);
sys/dev/ic/ar9003.c
1943
uint32_t reg;
sys/dev/ic/ar9003.c
1947
reg = AR_READ(sc, AR_PHY_CCA(i));
sys/dev/ic/ar9003.c
1948
nf[i] = MS(reg, AR_PHY_MINCCA_PWR);
sys/dev/ic/ar9003.c
1951
reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
sys/dev/ic/ar9003.c
1952
nf_ext[i] = MS(reg, AR_PHY_EXT_MINCCA_PWR);
sys/dev/ic/ar9003.c
1961
uint32_t reg;
sys/dev/ic/ar9003.c
1965
reg = AR_READ(sc, AR_PHY_CCA(i));
sys/dev/ic/ar9003.c
1966
reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]);
sys/dev/ic/ar9003.c
1967
AR_WRITE(sc, AR_PHY_CCA(i), reg);
sys/dev/ic/ar9003.c
1969
reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
sys/dev/ic/ar9003.c
1970
reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);
sys/dev/ic/ar9003.c
1971
AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg);
sys/dev/ic/ar9003.c
2077
uint32_t reg;
sys/dev/ic/ar9003.c
2102
reg = AR_READ(sc, AR_PHY_AGC_CONTROL);
sys/dev/ic/ar9003.c
2103
if (!(reg & AR_PHY_AGC_CONTROL_CAL))
sys/dev/ic/ar9003.c
2121
uint32_t reg;
sys/dev/ic/ar9003.c
2124
reg = AR_READ(sc, AR_PHY_TIMING4);
sys/dev/ic/ar9003.c
2125
reg = RW(reg, AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, 10);
sys/dev/ic/ar9003.c
2126
AR_WRITE(sc, AR_PHY_TIMING4, reg);
sys/dev/ic/ar9003.c
2155
uint32_t reg, i_coff_denom, q_coff_denom;
sys/dev/ic/ar9003.c
2201
reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i));
sys/dev/ic/ar9003.c
2202
reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, i_coff);
sys/dev/ic/ar9003.c
2203
reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, q_coff);
sys/dev/ic/ar9003.c
2204
AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg);
sys/dev/ic/ar9003.c
2340
uint32_t reg;
sys/dev/ic/ar9003.c
2344
reg = AR_READ(sc, AR_PHY_TX_IQCAL_CONTROL_1);
sys/dev/ic/ar9003.c
2345
reg = RW(reg, AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT);
sys/dev/ic/ar9003.c
2346
AR_WRITE(sc, AR_PHY_TX_IQCAL_CONTROL_1, reg);
sys/dev/ic/ar9003.c
2352
reg = AR_READ(sc, AR_PHY_TX_IQCAL_START);
sys/dev/ic/ar9003.c
2353
if (!(reg & AR_PHY_TX_IQCAL_START_DO_CAL))
sys/dev/ic/ar9003.c
2362
reg = AR_READ(sc, AR_PHY_TX_IQCAL_STATUS_B(i));
sys/dev/ic/ar9003.c
2363
if (reg & AR_PHY_TX_IQCAL_STATUS_FAILED)
sys/dev/ic/ar9003.c
237
uint32_t reg;
sys/dev/ic/ar9003.c
2372
reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j));
sys/dev/ic/ar9003.c
2373
res[j * 2 + 0] = reg;
sys/dev/ic/ar9003.c
2377
reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j));
sys/dev/ic/ar9003.c
2378
res[j * 2 + 1] = reg & 0xffff;
sys/dev/ic/ar9003.c
2386
reg = AR_READ(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i));
sys/dev/ic/ar9003.c
2387
reg = RW(reg, AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
sys/dev/ic/ar9003.c
2389
AR_WRITE(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i), reg);
sys/dev/ic/ar9003.c
2391
reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i));
sys/dev/ic/ar9003.c
2392
reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF,
sys/dev/ic/ar9003.c
2394
reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF,
sys/dev/ic/ar9003.c
2396
AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg);
sys/dev/ic/ar9003.c
240
reg = AR_READ(sc, AR_EEPROM_OFFSET(addr));
sys/dev/ic/ar9003.c
242
reg = AR_READ(sc, AR_EEPROM_STATUS_DATA);
sys/dev/ic/ar9003.c
243
if (!(reg & (AR_EEPROM_STATUS_DATA_BUSY |
sys/dev/ic/ar9003.c
2430
uint32_t reg, ht20mask, ht40mask;
sys/dev/ic/ar9003.c
2437
reg = AR_READ(sc, AR_PHY_PAPRD_AM2AM);
sys/dev/ic/ar9003.c
2438
reg = RW(reg, AR_PHY_PAPRD_AM2AM_MASK, ht20mask);
sys/dev/ic/ar9003.c
2439
AR_WRITE(sc, AR_PHY_PAPRD_AM2AM, reg);
sys/dev/ic/ar9003.c
2442
reg = AR_READ(sc, AR_PHY_PAPRD_AM2PM);
sys/dev/ic/ar9003.c
2443
reg = RW(reg, AR_PHY_PAPRD_AM2PM_MASK, ht20mask);
sys/dev/ic/ar9003.c
2444
AR_WRITE(sc, AR_PHY_PAPRD_AM2PM, reg);
sys/dev/ic/ar9003.c
2446
reg = AR_READ(sc, AR_PHY_PAPRD_HT40);
sys/dev/ic/ar9003.c
2447
reg = RW(reg, AR_PHY_PAPRD_HT40_MASK, ht40mask);
sys/dev/ic/ar9003.c
2448
AR_WRITE(sc, AR_PHY_PAPRD_HT40, reg);
sys/dev/ic/ar9003.c
245
*val = MS(reg, AR_EEPROM_STATUS_DATA_VAL);
sys/dev/ic/ar9003.c
2454
reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(i));
sys/dev/ic/ar9003.c
2455
reg = RW(reg, AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT, 181);
sys/dev/ic/ar9003.c
2456
reg = RW(reg, AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT, 361);
sys/dev/ic/ar9003.c
2457
reg &= ~AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA;
sys/dev/ic/ar9003.c
2458
reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENA;
sys/dev/ic/ar9003.c
2459
reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENA;
sys/dev/ic/ar9003.c
2460
AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(i), reg);
sys/dev/ic/ar9003.c
2462
reg = AR_READ(sc, AR_PHY_PAPRD_CTRL0_B(i));
sys/dev/ic/ar9003.c
2463
reg = RW(reg, AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH, 3);
sys/dev/ic/ar9003.c
2464
AR_WRITE(sc, AR_PHY_PAPRD_CTRL0_B(i), reg);
sys/dev/ic/ar9003.c
2477
reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL1);
sys/dev/ic/ar9003.c
2478
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING, 28);
sys/dev/ic/ar9003.c
2479
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP, 0x30);
sys/dev/ic/ar9003.c
2480
reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_RX_BB_GAIN_FORCE;
sys/dev/ic/ar9003.c
2481
reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_IQCORR_ENABLE;
sys/dev/ic/ar9003.c
2482
reg |= AR_PHY_PAPRD_TRAINER_CNTL1_LB_ENABLE;
sys/dev/ic/ar9003.c
2483
reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TX_GAIN_FORCE;
sys/dev/ic/ar9003.c
2484
reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TRAIN_ENABLE;
sys/dev/ic/ar9003.c
2485
AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL1, reg);
sys/dev/ic/ar9003.c
2489
reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL3);
sys/dev/ic/ar9003.c
2490
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN, 4);
sys/dev/ic/ar9003.c
2491
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN, 4);
sys/dev/ic/ar9003.c
2492
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES, 7);
sys/dev/ic/ar9003.c
2493
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL, 1);
sys/dev/ic/ar9003.c
2495
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -3);
sys/dev/ic/ar9003.c
2497
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -6);
sys/dev/ic/ar9003.c
2498
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE, -15);
sys/dev/ic/ar9003.c
2499
reg |= AR_PHY_PAPRD_TRAINER_CNTL3_BBTXMIX_DISABLE;
sys/dev/ic/ar9003.c
2500
AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL3, reg);
sys/dev/ic/ar9003.c
2502
reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL4);
sys/dev/ic/ar9003.c
2503
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA, 0);
sys/dev/ic/ar9003.c
2504
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR, 400);
sys/dev/ic/ar9003.c
2505
reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES, 100);
sys/dev/ic/ar9003.c
2506
AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL4, reg);
sys/dev/ic/ar9003.c
2509
reg = AR_READ(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i));
sys/dev/ic/ar9003.c
2510
reg = RW(reg, AR_PHY_PAPRD_PRE_POST_SCALING, scaling[i]);
sys/dev/ic/ar9003.c
2511
AR_WRITE(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i), reg);
sys/dev/ic/ar9003.c
2544
uint32_t reg;
sys/dev/ic/ar9003.c
2550
reg = AR_READ(sc, AR_PHY_TPC_19);
sys/dev/ic/ar9003.c
2551
atemp = MS(reg, AR_PHY_TPC_19_ALPHA_THERM);
sys/dev/ic/ar9003.c
2552
avolt = MS(reg, AR_PHY_TPC_19_ALPHA_VOLT);
sys/dev/ic/ar9003.c
2554
reg = AR_READ(sc, AR_PHY_TPC_18);
sys/dev/ic/ar9003.c
2555
tempcal = MS(reg, AR_PHY_TPC_18_THERM_CAL);
sys/dev/ic/ar9003.c
2556
voltcal = MS(reg, AR_PHY_TPC_18_VOLT_CAL);
sys/dev/ic/ar9003.c
2558
reg = AR_READ(sc, AR_PHY_BB_THERM_ADC_4);
sys/dev/ic/ar9003.c
2559
temp = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_THERM);
sys/dev/ic/ar9003.c
2560
volt = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_VOLT);
sys/dev/ic/ar9003.c
2576
uint32_t reg;
sys/dev/ic/ar9003.c
2578
reg = AR_READ(sc, AR_PHY_TX_FORCED_GAIN);
sys/dev/ic/ar9003.c
2579
reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN,
sys/dev/ic/ar9003.c
2581
reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN,
sys/dev/ic/ar9003.c
2583
reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXMXRGAIN,
sys/dev/ic/ar9003.c
2585
reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNA,
sys/dev/ic/ar9003.c
2587
reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNB,
sys/dev/ic/ar9003.c
2589
reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNC,
sys/dev/ic/ar9003.c
2591
reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGND,
sys/dev/ic/ar9003.c
2593
reg &= ~AR_PHY_TX_FORCED_GAIN_ENABLE_PAL;
sys/dev/ic/ar9003.c
2594
reg &= ~AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN;
sys/dev/ic/ar9003.c
2595
AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, reg);
sys/dev/ic/ar9003.c
2597
reg = AR_READ(sc, AR_PHY_TPC_1);
sys/dev/ic/ar9003.c
2598
reg = RW(reg, AR_PHY_TPC_1_FORCED_DAC_GAIN, 0);
sys/dev/ic/ar9003.c
2599
reg &= ~AR_PHY_TPC_1_FORCE_DAC_GAIN;
sys/dev/ic/ar9003.c
2600
AR_WRITE(sc, AR_PHY_TPC_1, reg);
sys/dev/ic/ar9003.c
2924
uint32_t reg;
sys/dev/ic/ar9003.c
2934
reg = AR_READ(sc, AR_PHY_PA_GAIN123_B(chain));
sys/dev/ic/ar9003.c
2935
reg = RW(reg, AR_PHY_PA_GAIN123_PA_GAIN1, sc->gain1[chain]);
sys/dev/ic/ar9003.c
2936
AR_WRITE(sc, AR_PHY_PA_GAIN123_B(chain), reg);
sys/dev/ic/ar9003.c
2939
reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(chain));
sys/dev/ic/ar9003.c
2940
reg = RW(reg, AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL, sc->trainpow);
sys/dev/ic/ar9003.c
2941
AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(chain), reg);
sys/dev/ic/ar9003.c
298
uint32_t reg;
sys/dev/ic/ar9003.c
301
reg = AR_READ(sc, AR_OTP_BASE(addr));
sys/dev/ic/ar9003.c
303
reg = AR_READ(sc, AR_OTP_STATUS);
sys/dev/ic/ar9003.c
304
if (MS(reg, AR_OTP_STATUS_TYPE) == AR_OTP_STATUS_VALID) {
sys/dev/ic/ar9003.c
3112
uint32_t reg;
sys/dev/ic/ar9003.c
3180
reg = AR_READ(sc, AR_PCU_MISC_MODE2);
sys/dev/ic/ar9003.c
3181
reg &= ~AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE;
sys/dev/ic/ar9003.c
3182
reg |= AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX;
sys/dev/ic/ar9003.c
3183
reg |= AR_PCU_MISC_MODE2_ENABLE_AGGWEP;
sys/dev/ic/ar9003.c
3184
AR_WRITE(sc, AR_PCU_MISC_MODE2, reg);
sys/dev/ic/ar9003.c
3265
uint32_t reg;
sys/dev/ic/ar9003.c
3267
reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
sys/dev/ic/ar9003.c
3268
reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55);
sys/dev/ic/ar9003.c
3269
AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
sys/dev/ic/ar9003.c
3271
reg = AR_READ(sc, AR_PHY_AGC);
sys/dev/ic/ar9003.c
3272
reg = RW(reg, AR_PHY_AGC_COARSE_LOW, high ? -70 : -64);
sys/dev/ic/ar9003.c
3273
reg = RW(reg, AR_PHY_AGC_COARSE_HIGH, high ? -12 : -14);
sys/dev/ic/ar9003.c
3274
AR_WRITE(sc, AR_PHY_AGC, reg);
sys/dev/ic/ar9003.c
3276
reg = AR_READ(sc, AR_PHY_FIND_SIG);
sys/dev/ic/ar9003.c
3277
reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78);
sys/dev/ic/ar9003.c
3278
AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
sys/dev/ic/ar9003.c
3285
uint32_t reg;
sys/dev/ic/ar9003.c
3287
reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
sys/dev/ic/ar9003.c
3288
reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50);
sys/dev/ic/ar9003.c
3289
reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40);
sys/dev/ic/ar9003.c
3290
reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48);
sys/dev/ic/ar9003.c
3291
AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
sys/dev/ic/ar9003.c
3293
reg = AR_READ(sc, AR_PHY_SFCORR);
sys/dev/ic/ar9003.c
3294
reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77);
sys/dev/ic/ar9003.c
3295
reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64);
sys/dev/ic/ar9003.c
3296
reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16);
sys/dev/ic/ar9003.c
3297
AR_WRITE(sc, AR_PHY_SFCORR, reg);
sys/dev/ic/ar9003.c
3299
reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
sys/dev/ic/ar9003.c
3300
reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50);
sys/dev/ic/ar9003.c
3301
reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40);
sys/dev/ic/ar9003.c
3302
reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77);
sys/dev/ic/ar9003.c
3303
reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64);
sys/dev/ic/ar9003.c
3304
AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
sys/dev/ic/ar9003.c
3314
uint32_t reg;
sys/dev/ic/ar9003.c
3316
reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
sys/dev/ic/ar9003.c
3317
reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127);
sys/dev/ic/ar9003.c
3318
reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127);
sys/dev/ic/ar9003.c
3319
reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63);
sys/dev/ic/ar9003.c
3320
AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
sys/dev/ic/ar9003.c
3322
reg = AR_READ(sc, AR_PHY_SFCORR);
sys/dev/ic/ar9003.c
3323
reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127);
sys/dev/ic/ar9003.c
3324
reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127);
sys/dev/ic/ar9003.c
3325
reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31);
sys/dev/ic/ar9003.c
3326
AR_WRITE(sc, AR_PHY_SFCORR, reg);
sys/dev/ic/ar9003.c
3328
reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
sys/dev/ic/ar9003.c
3329
reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127);
sys/dev/ic/ar9003.c
3330
reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127);
sys/dev/ic/ar9003.c
3331
reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127);
sys/dev/ic/ar9003.c
3332
reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127);
sys/dev/ic/ar9003.c
3333
AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
sys/dev/ic/ar9003.c
3343
uint32_t reg;
sys/dev/ic/ar9003.c
3345
reg = AR_READ(sc, AR_PHY_CCK_DETECT);
sys/dev/ic/ar9003.c
3346
reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8);
sys/dev/ic/ar9003.c
3347
AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
sys/dev/ic/ar9003.c
3354
uint32_t reg;
sys/dev/ic/ar9003.c
3356
reg = AR_READ(sc, AR_PHY_FIND_SIG);
sys/dev/ic/ar9003.c
3357
reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4);
sys/dev/ic/ar9003.c
3358
AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
sys/dev/ic/ar9003.c
3365
uint32_t reg;
sys/dev/ic/ar9003.c
3367
reg = AR_READ(sc, AR_PHY_TIMING5);
sys/dev/ic/ar9003.c
3368
reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2);
sys/dev/ic/ar9003.c
3369
AR_WRITE(sc, AR_PHY_TIMING5, reg);
sys/dev/ic/ar9003.c
511
uint32_t reg;
sys/dev/ic/ar9003.c
514
reg = AR_READ(sc, AR_GPIO_IN_OUT);
sys/dev/ic/ar9003.c
516
reg |= 1 << pin;
sys/dev/ic/ar9003.c
518
reg &= ~(1 << pin);
sys/dev/ic/ar9003.c
519
AR_WRITE(sc, AR_GPIO_IN_OUT, reg);
sys/dev/ic/ar9003.c
526
uint32_t reg;
sys/dev/ic/ar9003.c
528
reg = AR_READ(sc, AR_GPIO_OE_OUT);
sys/dev/ic/ar9003.c
529
reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
sys/dev/ic/ar9003.c
530
reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2);
sys/dev/ic/ar9003.c
531
AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
sys/dev/ic/ar9003.c
538
uint32_t reg;
sys/dev/ic/ar9003.c
544
reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux));
sys/dev/ic/ar9003.c
545
reg &= ~(0x1f << (off * 5));
sys/dev/ic/ar9003.c
546
reg |= (type & 0x1f) << (off * 5);
sys/dev/ic/ar9003.c
547
AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg);
sys/dev/ic/ar9003.c
549
reg = AR_READ(sc, AR_GPIO_OE_OUT);
sys/dev/ic/ar9003.c
550
reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
sys/dev/ic/ar9003.c
551
reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2);
sys/dev/ic/ar9003.c
552
AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
sys/dev/ic/ar9003.c
559
uint32_t reg;
sys/dev/ic/ar9003.c
563
reg = AR_READ(sc, AR_GPIO_INPUT_MUX2);
sys/dev/ic/ar9003.c
564
reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);
sys/dev/ic/ar9003.c
565
AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg);
sys/dev/ic/ar9003.c
816
uint32_t reg;
sys/dev/ic/ar9003.c
819
reg = AR_READ(sc, AR_RXBP_THRESH);
sys/dev/ic/ar9003.c
820
reg = RW(reg, AR_RXBP_THRESH_HP, 1);
sys/dev/ic/ar9003.c
821
reg = RW(reg, AR_RXBP_THRESH_LP, 1);
sys/dev/ic/ar9003.c
822
AR_WRITE(sc, AR_RXBP_THRESH, reg);
sys/dev/ic/ar9003reg.h
224
#define AR_IS_ANALOG_REG(reg) ((reg) >= 0x16000 && (reg) <= 0x17000)
sys/dev/ic/ar9280.c
179
uint32_t phy, reg, ndiv = 0;
sys/dev/ic/ar9280.c
201
reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
sys/dev/ic/ar9280.c
203
reg |= AR_PHY_CCK_TX_CTRL_JAPAN;
sys/dev/ic/ar9280.c
205
reg &= ~AR_PHY_CCK_TX_CTRL_JAPAN;
sys/dev/ic/ar9280.c
206
AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
sys/dev/ic/ar9280.c
227
reg = AR_READ(sc, AR_AN_SYNTH9);
sys/dev/ic/ar9280.c
228
reg = RW(reg, AR_AN_SYNTH9_REFDIVA, 1);
sys/dev/ic/ar9280.c
229
AR_WRITE(sc, AR_AN_SYNTH9, reg);
sys/dev/ic/ar9280.c
246
uint32_t reg, offset;
sys/dev/ic/ar9280.c
263
reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
sys/dev/ic/ar9280.c
264
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
sys/dev/ic/ar9280.c
266
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
sys/dev/ic/ar9280.c
268
AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
sys/dev/ic/ar9280.c
271
reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
sys/dev/ic/ar9280.c
272
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
sys/dev/ic/ar9280.c
274
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
sys/dev/ic/ar9280.c
276
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
sys/dev/ic/ar9280.c
278
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
sys/dev/ic/ar9280.c
280
AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
sys/dev/ic/ar9280.c
286
reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
sys/dev/ic/ar9280.c
287
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,
sys/dev/ic/ar9280.c
289
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,
sys/dev/ic/ar9280.c
291
AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
sys/dev/ic/ar9280.c
294
reg = AR_READ(sc, AR_AN_RF2G1_CH0);
sys/dev/ic/ar9280.c
295
reg = RW(reg, AR_AN_RF2G1_CH0_OB, modal->ob);
sys/dev/ic/ar9280.c
296
reg = RW(reg, AR_AN_RF2G1_CH0_DB, modal->db);
sys/dev/ic/ar9280.c
297
AR_WRITE(sc, AR_AN_RF2G1_CH0, reg);
sys/dev/ic/ar9280.c
301
reg = AR_READ(sc, AR_AN_RF2G1_CH1);
sys/dev/ic/ar9280.c
302
reg = RW(reg, AR_AN_RF2G1_CH1_OB, modal->ob_ch1);
sys/dev/ic/ar9280.c
303
reg = RW(reg, AR_AN_RF2G1_CH1_DB, modal->db_ch1);
sys/dev/ic/ar9280.c
304
AR_WRITE(sc, AR_AN_RF2G1_CH1, reg);
sys/dev/ic/ar9280.c
308
reg = AR_READ(sc, AR_AN_RF5G1_CH0);
sys/dev/ic/ar9280.c
309
reg = RW(reg, AR_AN_RF5G1_CH0_OB5, modal->ob);
sys/dev/ic/ar9280.c
310
reg = RW(reg, AR_AN_RF5G1_CH0_DB5, modal->db);
sys/dev/ic/ar9280.c
311
AR_WRITE(sc, AR_AN_RF5G1_CH0, reg);
sys/dev/ic/ar9280.c
315
reg = AR_READ(sc, AR_AN_RF5G1_CH1);
sys/dev/ic/ar9280.c
316
reg = RW(reg, AR_AN_RF5G1_CH1_OB5, modal->ob_ch1);
sys/dev/ic/ar9280.c
317
reg = RW(reg, AR_AN_RF5G1_CH1_DB5, modal->db_ch1);
sys/dev/ic/ar9280.c
318
AR_WRITE(sc, AR_AN_RF5G1_CH1, reg);
sys/dev/ic/ar9280.c
322
reg = AR_READ(sc, AR_AN_TOP2);
sys/dev/ic/ar9280.c
329
reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, 0);
sys/dev/ic/ar9280.c
331
reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);
sys/dev/ic/ar9280.c
333
reg |= AR_AN_TOP2_LOCALBIAS;
sys/dev/ic/ar9280.c
335
reg &= ~AR_AN_TOP2_LOCALBIAS;
sys/dev/ic/ar9280.c
336
AR_WRITE(sc, AR_AN_TOP2, reg);
sys/dev/ic/ar9280.c
340
reg = AR_READ(sc, AR_PHY_XPA_CFG);
sys/dev/ic/ar9280.c
342
reg |= AR_PHY_FORCE_XPA_CFG;
sys/dev/ic/ar9280.c
344
reg &= ~AR_PHY_FORCE_XPA_CFG;
sys/dev/ic/ar9280.c
345
AR_WRITE(sc, AR_PHY_XPA_CFG, reg);
sys/dev/ic/ar9280.c
347
reg = AR_READ(sc, AR_PHY_SETTLING);
sys/dev/ic/ar9280.c
348
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
sys/dev/ic/ar9280.c
349
AR_WRITE(sc, AR_PHY_SETTLING, reg);
sys/dev/ic/ar9280.c
351
reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
sys/dev/ic/ar9280.c
352
reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
sys/dev/ic/ar9280.c
353
AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
sys/dev/ic/ar9280.c
355
reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
sys/dev/ic/ar9280.c
356
reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
sys/dev/ic/ar9280.c
357
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
sys/dev/ic/ar9280.c
358
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
sys/dev/ic/ar9280.c
359
AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
sys/dev/ic/ar9280.c
361
reg = AR_READ(sc, AR_PHY_RF_CTL3);
sys/dev/ic/ar9280.c
362
reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
sys/dev/ic/ar9280.c
363
AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
sys/dev/ic/ar9280.c
365
reg = AR_READ(sc, AR_PHY_CCA(0));
sys/dev/ic/ar9280.c
366
reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
sys/dev/ic/ar9280.c
367
AR_WRITE(sc, AR_PHY_CCA(0), reg);
sys/dev/ic/ar9280.c
369
reg = AR_READ(sc, AR_PHY_EXT_CCA0);
sys/dev/ic/ar9280.c
370
reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
sys/dev/ic/ar9280.c
371
AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);
sys/dev/ic/ar9280.c
374
reg = AR_READ(sc, AR_PHY_RF_CTL2);
sys/dev/ic/ar9280.c
375
reg = RW(reg, AR_PHY_TX_END_DATA_START,
sys/dev/ic/ar9280.c
377
reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
sys/dev/ic/ar9280.c
378
AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
sys/dev/ic/ar9280.c
382
reg = AR_READ(sc, AR_PHY_SETTLING);
sys/dev/ic/ar9280.c
383
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
sys/dev/ic/ar9280.c
384
AR_WRITE(sc, AR_PHY_SETTLING, reg);
sys/dev/ic/ar9280.c
387
reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
sys/dev/ic/ar9280.c
388
reg = RW(reg, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
sys/dev/ic/ar9280.c
390
AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
sys/dev/ic/ar9280.c
394
reg = AR_READ(sc, AR_AN_TOP1);
sys/dev/ic/ar9280.c
398
reg |= AR_AN_TOP1_DACLPMODE;
sys/dev/ic/ar9280.c
400
reg &= ~AR_AN_TOP1_DACLPMODE;
sys/dev/ic/ar9280.c
401
AR_WRITE(sc, AR_AN_TOP1, reg);
sys/dev/ic/ar9280.c
405
reg = AR_READ(sc, AR_PHY_FRAME_CTL);
sys/dev/ic/ar9280.c
406
reg = RW(reg, AR_PHY_FRAME_CTL_TX_CLIP,
sys/dev/ic/ar9280.c
408
AR_WRITE(sc, AR_PHY_FRAME_CTL, reg);
sys/dev/ic/ar9280.c
410
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL9);
sys/dev/ic/ar9280.c
411
reg = RW(reg, AR_PHY_TX_DESIRED_SCALE_CCK,
sys/dev/ic/ar9280.c
413
AR_WRITE(sc, AR_PHY_TX_PWRCTRL9, reg);
sys/dev/ic/ar9280.c
574
uint32_t reg;
sys/dev/ic/ar9280.c
579
reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
sys/dev/ic/ar9280.c
580
sc->tx_gain_tbl[i] = MS(reg, AR_PHY_TX_GAIN);
sys/dev/ic/ar9280.c
591
uint32_t reg;
sys/dev/ic/ar9280.c
594
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);
sys/dev/ic/ar9280.c
595
pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
sys/dev/ic/ar9280.c
618
reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
sys/dev/ic/ar9280.c
619
reg = RW(reg, AR_PHY_TX_GAIN, txgain);
sys/dev/ic/ar9280.c
620
AR_WRITE(sc, AR_PHY_TX_GAIN_TBL(i), reg);
sys/dev/ic/ar9285.c
200
uint32_t reg, offset = 0x1000;
sys/dev/ic/ar9285.c
207
reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0);
sys/dev/ic/ar9285.c
208
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, modal->iqCalI);
sys/dev/ic/ar9285.c
209
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, modal->iqCalQ);
sys/dev/ic/ar9285.c
210
AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg);
sys/dev/ic/ar9285.c
213
reg = AR_READ(sc, AR_PHY_GAIN_2GHZ);
sys/dev/ic/ar9285.c
214
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
sys/dev/ic/ar9285.c
216
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
sys/dev/ic/ar9285.c
218
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
sys/dev/ic/ar9285.c
220
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
sys/dev/ic/ar9285.c
222
AR_WRITE(sc, AR_PHY_GAIN_2GHZ, reg);
sys/dev/ic/ar9285.c
225
reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
sys/dev/ic/ar9285.c
226
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
sys/dev/ic/ar9285.c
228
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
sys/dev/ic/ar9285.c
230
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
sys/dev/ic/ar9285.c
232
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
sys/dev/ic/ar9285.c
234
AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
sys/dev/ic/ar9285.c
240
reg = AR_READ(sc, AR_PHY_RXGAIN);
sys/dev/ic/ar9285.c
241
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);
sys/dev/ic/ar9285.c
242
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);
sys/dev/ic/ar9285.c
243
AR_WRITE(sc, AR_PHY_RXGAIN, reg);
sys/dev/ic/ar9285.c
246
reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
sys/dev/ic/ar9285.c
247
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);
sys/dev/ic/ar9285.c
248
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);
sys/dev/ic/ar9285.c
249
AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
sys/dev/ic/ar9285.c
253
reg = AR_READ(sc, AR_PHY_MULTICHAIN_GAIN_CTL);
sys/dev/ic/ar9285.c
254
reg = RW(reg, AR9285_PHY_ANT_DIV_CTL_ALL, 0);
sys/dev/ic/ar9285.c
255
reg = RW(reg, AR9285_PHY_ANT_DIV_CTL,
sys/dev/ic/ar9285.c
257
reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_LNACONF,
sys/dev/ic/ar9285.c
259
reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_LNACONF,
sys/dev/ic/ar9285.c
261
reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_GAINTB,
sys/dev/ic/ar9285.c
263
reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_GAINTB,
sys/dev/ic/ar9285.c
265
AR_WRITE(sc, AR_PHY_MULTICHAIN_GAIN_CTL, reg);
sys/dev/ic/ar9285.c
266
reg = AR_READ(sc, AR_PHY_MULTICHAIN_GAIN_CTL); /* Flush. */
sys/dev/ic/ar9285.c
268
reg = AR_READ(sc, AR_PHY_CCK_DETECT);
sys/dev/ic/ar9285.c
270
reg |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
sys/dev/ic/ar9285.c
272
reg &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
sys/dev/ic/ar9285.c
273
AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
sys/dev/ic/ar9285.c
274
reg = AR_READ(sc, AR_PHY_CCK_DETECT); /* Flush. */
sys/dev/ic/ar9285.c
324
reg = AR_READ(sc, AR9285_AN_RF2G3);
sys/dev/ic/ar9285.c
325
reg = RW(reg, AR9271_AN_RF2G3_OB_CCK, ob [0]);
sys/dev/ic/ar9285.c
326
reg = RW(reg, AR9271_AN_RF2G3_OB_PSK, ob [1]);
sys/dev/ic/ar9285.c
327
reg = RW(reg, AR9271_AN_RF2G3_OB_QAM, ob [2]);
sys/dev/ic/ar9285.c
328
reg = RW(reg, AR9271_AN_RF2G3_DB1, db1[0]);
sys/dev/ic/ar9285.c
329
AR_WRITE(sc, AR9285_AN_RF2G3, reg);
sys/dev/ic/ar9285.c
332
reg = AR_READ(sc, AR9285_AN_RF2G4);
sys/dev/ic/ar9285.c
333
reg = RW(reg, AR9271_AN_RF2G4_DB2, db2[0]);
sys/dev/ic/ar9285.c
334
AR_WRITE(sc, AR9285_AN_RF2G4, reg);
sys/dev/ic/ar9285.c
340
reg = AR_READ(sc, AR9285_AN_RF2G3);
sys/dev/ic/ar9285.c
341
reg = RW(reg, AR9285_AN_RF2G3_OB_0, ob [0]);
sys/dev/ic/ar9285.c
342
reg = RW(reg, AR9285_AN_RF2G3_OB_1, ob [1]);
sys/dev/ic/ar9285.c
343
reg = RW(reg, AR9285_AN_RF2G3_OB_2, ob [2]);
sys/dev/ic/ar9285.c
344
reg = RW(reg, AR9285_AN_RF2G3_OB_3, ob [3]);
sys/dev/ic/ar9285.c
345
reg = RW(reg, AR9285_AN_RF2G3_OB_4, ob [4]);
sys/dev/ic/ar9285.c
346
reg = RW(reg, AR9285_AN_RF2G3_DB1_0, db1[0]);
sys/dev/ic/ar9285.c
347
reg = RW(reg, AR9285_AN_RF2G3_DB1_1, db1[1]);
sys/dev/ic/ar9285.c
348
reg = RW(reg, AR9285_AN_RF2G3_DB1_2, db1[2]);
sys/dev/ic/ar9285.c
349
AR_WRITE(sc, AR9285_AN_RF2G3, reg);
sys/dev/ic/ar9285.c
352
reg = AR_READ(sc, AR9285_AN_RF2G4);
sys/dev/ic/ar9285.c
353
reg = RW(reg, AR9285_AN_RF2G4_DB1_3, db1[3]);
sys/dev/ic/ar9285.c
354
reg = RW(reg, AR9285_AN_RF2G4_DB1_4, db1[4]);
sys/dev/ic/ar9285.c
355
reg = RW(reg, AR9285_AN_RF2G4_DB2_0, db2[0]);
sys/dev/ic/ar9285.c
356
reg = RW(reg, AR9285_AN_RF2G4_DB2_1, db2[1]);
sys/dev/ic/ar9285.c
357
reg = RW(reg, AR9285_AN_RF2G4_DB2_2, db2[2]);
sys/dev/ic/ar9285.c
358
reg = RW(reg, AR9285_AN_RF2G4_DB2_3, db2[3]);
sys/dev/ic/ar9285.c
359
reg = RW(reg, AR9285_AN_RF2G4_DB2_4, db2[4]);
sys/dev/ic/ar9285.c
360
AR_WRITE(sc, AR9285_AN_RF2G4, reg);
sys/dev/ic/ar9285.c
365
reg = AR_READ(sc, AR_PHY_SETTLING);
sys/dev/ic/ar9285.c
366
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
sys/dev/ic/ar9285.c
367
AR_WRITE(sc, AR_PHY_SETTLING, reg);
sys/dev/ic/ar9285.c
369
reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
sys/dev/ic/ar9285.c
370
reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
sys/dev/ic/ar9285.c
371
AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
sys/dev/ic/ar9285.c
373
reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
sys/dev/ic/ar9285.c
374
reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
sys/dev/ic/ar9285.c
375
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
sys/dev/ic/ar9285.c
376
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
sys/dev/ic/ar9285.c
377
AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
sys/dev/ic/ar9285.c
379
reg = AR_READ(sc, AR_PHY_RF_CTL3);
sys/dev/ic/ar9285.c
380
reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
sys/dev/ic/ar9285.c
381
AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
sys/dev/ic/ar9285.c
383
reg = AR_READ(sc, AR_PHY_CCA(0));
sys/dev/ic/ar9285.c
384
reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
sys/dev/ic/ar9285.c
385
AR_WRITE(sc, AR_PHY_CCA(0), reg);
sys/dev/ic/ar9285.c
387
reg = AR_READ(sc, AR_PHY_EXT_CCA0);
sys/dev/ic/ar9285.c
388
reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
sys/dev/ic/ar9285.c
389
AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);
sys/dev/ic/ar9285.c
392
reg = AR_READ(sc, AR_PHY_RF_CTL2);
sys/dev/ic/ar9285.c
393
reg = RW(reg, AR_PHY_TX_END_PA_ON,
sys/dev/ic/ar9285.c
395
reg = RW(reg, AR_PHY_TX_END_DATA_START,
sys/dev/ic/ar9285.c
397
AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
sys/dev/ic/ar9285.c
400
reg = AR_READ(sc, AR_PHY_SETTLING);
sys/dev/ic/ar9285.c
401
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
sys/dev/ic/ar9285.c
402
AR_WRITE(sc, AR_PHY_SETTLING, reg);
sys/dev/ic/ar9285.c
420
uint32_t svg[7], reg, ccomp_svg;
sys/dev/ic/ar9285.c
448
reg = AR_READ(sc, AR9285_AN_RF2G8);
sys/dev/ic/ar9285.c
449
reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
sys/dev/ic/ar9285.c
450
AR_WRITE(sc, AR9285_AN_RF2G8, reg);
sys/dev/ic/ar9285.c
452
reg = AR_READ(sc, AR9285_AN_RF2G7);
sys/dev/ic/ar9285.c
453
reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
sys/dev/ic/ar9285.c
454
AR_WRITE(sc, AR9285_AN_RF2G7, reg);
sys/dev/ic/ar9285.c
456
reg = AR_READ(sc, AR9285_AN_RF2G6);
sys/dev/ic/ar9285.c
458
ccomp_svg = MS(reg, AR9285_AN_RF2G6_CCOMP);
sys/dev/ic/ar9285.c
460
reg = RW(reg, AR9285_AN_RF2G6_CCOMP, 0xf);
sys/dev/ic/ar9285.c
461
AR_WRITE(sc, AR9285_AN_RF2G6, reg);
sys/dev/ic/ar9285.c
503
reg = AR_READ(sc, AR9285_AN_RF2G6);
sys/dev/ic/ar9285.c
504
reg = RW(reg, AR9285_AN_RF2G6_CCOMP, ccomp_svg);
sys/dev/ic/ar9285.c
505
AR_WRITE(sc, AR9285_AN_RF2G6, reg);
sys/dev/ic/ar9285.c
523
uint32_t svg[7], reg, rf2g3_svg;
sys/dev/ic/ar9285.c
545
reg = AR_READ(sc, AR9285_AN_RF2G8);
sys/dev/ic/ar9285.c
546
reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
sys/dev/ic/ar9285.c
547
AR_WRITE(sc, AR9285_AN_RF2G8, reg);
sys/dev/ic/ar9285.c
549
reg = AR_READ(sc, AR9285_AN_RF2G7);
sys/dev/ic/ar9285.c
550
reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
sys/dev/ic/ar9285.c
551
AR_WRITE(sc, AR9285_AN_RF2G7, reg);
sys/dev/ic/ar9285.c
554
reg = rf2g3_svg = AR_READ(sc, AR9285_AN_RF2G3);
sys/dev/ic/ar9285.c
556
reg = RW(reg, AR9271_AN_RF2G3_CCOMP, 0xfff);
sys/dev/ic/ar9285.c
557
AR_WRITE(sc, AR9285_AN_RF2G3, reg);
sys/dev/ic/ar9285.c
567
reg = AR_READ(sc, AR9285_AN_RF2G6);
sys/dev/ic/ar9285.c
568
reg |= AR9271_AN_RF2G6_OFFS(i);
sys/dev/ic/ar9285.c
569
AR_WRITE(sc, AR9285_AN_RF2G6, reg);
sys/dev/ic/ar9285.c
573
reg &= ~AR9271_AN_RF2G6_OFFS(i);
sys/dev/ic/ar9285.c
574
AR_WRITE(sc, AR9285_AN_RF2G6, reg);
sys/dev/ic/ar9285.c
660
uint32_t reg, mask, clcgain, rf2g5_svg;
sys/dev/ic/ar9285.c
673
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL7);
sys/dev/ic/ar9285.c
674
maxgain = MS(reg, AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
sys/dev/ic/ar9285.c
676
reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
sys/dev/ic/ar9285.c
677
clcgain = MS(reg, AR_PHY_TX_GAIN_CLC);
sys/dev/ic/ar9285.c
686
reg = AR_READ(sc, AR_PHY_CLC_TBL(i));
sys/dev/ic/ar9285.c
687
if (MS(reg, AR_PHY_CLC_I0) == 0)
sys/dev/ic/ar9285.c
689
if (MS(reg, AR_PHY_CLC_Q0) == 0)
sys/dev/ic/ar9285.c
697
rf2g5_svg = reg = AR_READ(sc, AR9285_AN_RF2G5);
sys/dev/ic/ar9285.c
699
reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x5);
sys/dev/ic/ar9285.c
701
reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x4);
sys/dev/ic/ar9285.c
702
AR_WRITE(sc, AR9285_AN_RF2G5, reg);
sys/dev/ic/ar9285.c
749
uint32_t reg;
sys/dev/ic/ar9285.c
766
reg = AR_READ(sc, AR_PHY_TPCRG1);
sys/dev/ic/ar9285.c
767
reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);
sys/dev/ic/ar9285.c
768
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);
sys/dev/ic/ar9285.c
769
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);
sys/dev/ic/ar9285.c
770
AR_WRITE(sc, AR_PHY_TPCRG1, reg);
sys/dev/ic/ar9285.c
776
reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP, overlap);
sys/dev/ic/ar9285.c
777
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1, boundaries[0]);
sys/dev/ic/ar9285.c
778
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2, boundaries[1]);
sys/dev/ic/ar9285.c
779
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3, boundaries[2]);
sys/dev/ic/ar9285.c
780
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4, boundaries[3]);
sys/dev/ic/ar9285.c
781
AR_WRITE(sc, AR_PHY_TPCRG5, reg);
sys/dev/ic/ar9287.c
173
uint32_t reg, offset;
sys/dev/ic/ar9287.c
184
reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
sys/dev/ic/ar9287.c
185
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
sys/dev/ic/ar9287.c
187
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
sys/dev/ic/ar9287.c
189
AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
sys/dev/ic/ar9287.c
191
reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
sys/dev/ic/ar9287.c
192
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
sys/dev/ic/ar9287.c
194
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
sys/dev/ic/ar9287.c
196
AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
sys/dev/ic/ar9287.c
198
reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
sys/dev/ic/ar9287.c
199
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,
sys/dev/ic/ar9287.c
201
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,
sys/dev/ic/ar9287.c
203
AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
sys/dev/ic/ar9287.c
206
reg = AR_READ(sc, AR_PHY_SETTLING);
sys/dev/ic/ar9287.c
208
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
sys/dev/ic/ar9287.c
210
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
sys/dev/ic/ar9287.c
211
AR_WRITE(sc, AR_PHY_SETTLING, reg);
sys/dev/ic/ar9287.c
213
reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
sys/dev/ic/ar9287.c
214
reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
sys/dev/ic/ar9287.c
215
AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
sys/dev/ic/ar9287.c
217
reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
sys/dev/ic/ar9287.c
218
reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
sys/dev/ic/ar9287.c
219
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
sys/dev/ic/ar9287.c
220
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
sys/dev/ic/ar9287.c
221
AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
sys/dev/ic/ar9287.c
223
reg = AR_READ(sc, AR_PHY_RF_CTL3);
sys/dev/ic/ar9287.c
224
reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
sys/dev/ic/ar9287.c
225
AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
sys/dev/ic/ar9287.c
227
reg = AR_READ(sc, AR_PHY_CCA(0));
sys/dev/ic/ar9287.c
228
reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
sys/dev/ic/ar9287.c
229
AR_WRITE(sc, AR_PHY_CCA(0), reg);
sys/dev/ic/ar9287.c
231
reg = AR_READ(sc, AR_PHY_EXT_CCA0);
sys/dev/ic/ar9287.c
232
reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
sys/dev/ic/ar9287.c
233
AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);
sys/dev/ic/ar9287.c
235
reg = AR_READ(sc, AR9287_AN_RF2G3_CH0);
sys/dev/ic/ar9287.c
236
reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1);
sys/dev/ic/ar9287.c
237
reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2);
sys/dev/ic/ar9287.c
238
reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck);
sys/dev/ic/ar9287.c
239
reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk);
sys/dev/ic/ar9287.c
240
reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);
sys/dev/ic/ar9287.c
241
reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);
sys/dev/ic/ar9287.c
242
AR_WRITE(sc, AR9287_AN_RF2G3_CH0, reg);
sys/dev/ic/ar9287.c
246
reg = AR_READ(sc, AR9287_AN_RF2G3_CH1);
sys/dev/ic/ar9287.c
247
reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1);
sys/dev/ic/ar9287.c
248
reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2);
sys/dev/ic/ar9287.c
249
reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck);
sys/dev/ic/ar9287.c
250
reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk);
sys/dev/ic/ar9287.c
251
reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);
sys/dev/ic/ar9287.c
252
reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);
sys/dev/ic/ar9287.c
253
AR_WRITE(sc, AR9287_AN_RF2G3_CH1, reg);
sys/dev/ic/ar9287.c
257
reg = AR_READ(sc, AR_PHY_RF_CTL2);
sys/dev/ic/ar9287.c
258
reg = RW(reg, AR_PHY_TX_END_DATA_START, modal->txFrameToDataStart);
sys/dev/ic/ar9287.c
259
reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
sys/dev/ic/ar9287.c
260
AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
sys/dev/ic/ar9287.c
262
reg = AR_READ(sc, AR9287_AN_TOP2);
sys/dev/ic/ar9287.c
263
reg = RW(reg, AR9287_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);
sys/dev/ic/ar9287.c
264
AR_WRITE(sc, AR9287_AN_TOP2, reg);
sys/dev/ic/ar9287.c
350
uint32_t reg, offset;
sys/dev/ic/ar9287.c
374
reg = AR_READ(sc, AR_PHY_TPCRG1);
sys/dev/ic/ar9287.c
375
reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);
sys/dev/ic/ar9287.c
376
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);
sys/dev/ic/ar9287.c
377
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);
sys/dev/ic/ar9287.c
378
AR_WRITE(sc, AR_PHY_TPCRG1, reg);
sys/dev/ic/ar9287.c
390
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_0);
sys/dev/ic/ar9287.c
391
reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
sys/dev/ic/ar9287.c
392
AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg);
sys/dev/ic/ar9287.c
394
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_1);
sys/dev/ic/ar9287.c
395
reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
sys/dev/ic/ar9287.c
396
AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg);
sys/dev/ic/ar9287.c
399
reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset);
sys/dev/ic/ar9287.c
400
reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_PWR, txpower);
sys/dev/ic/ar9287.c
401
AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset, reg);
sys/dev/ic/ar9287.c
413
reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP,
sys/dev/ic/ar9287.c
415
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1,
sys/dev/ic/ar9287.c
417
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2,
sys/dev/ic/ar9287.c
419
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3,
sys/dev/ic/ar9287.c
421
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4,
sys/dev/ic/ar9287.c
423
AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg);
sys/dev/ic/ar9287.c
541
uint32_t reg;
sys/dev/ic/ar9287.c
545
reg = AR_READ(sc, AR9287_AN_TXPC0);
sys/dev/ic/ar9287.c
546
reg = RW(reg, AR9287_AN_TXPC0_TXPCMODE,
sys/dev/ic/ar9287.c
548
AR_WRITE(sc, AR9287_AN_TXPC0, reg);
sys/dev/ic/ar9287.c
558
uint32_t reg;
sys/dev/ic/ar9287.c
560
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);
sys/dev/ic/ar9287.c
561
pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
sys/dev/ic/ar9287.c
579
reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11);
sys/dev/ic/ar9287.c
580
reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp);
sys/dev/ic/ar9287.c
581
AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11, reg);
sys/dev/ic/ar9287.c
583
reg = AR_READ(sc, AR_PHY_CH1_TX_PWRCTRL11);
sys/dev/ic/ar9287.c
584
reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp);
sys/dev/ic/ar9287.c
585
AR_WRITE(sc, AR_PHY_CH1_TX_PWRCTRL11, reg);
sys/dev/ic/ar9287.c
606
uint32_t reg;
sys/dev/ic/ar9287.c
622
reg = AR_READ(sc, AR_AHB_MODE);
sys/dev/ic/ar9287.c
623
reg = RW(reg, AR_AHB_CUSTOM_BURST, AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
sys/dev/ic/ar9287.c
624
AR_WRITE(sc, AR_AHB_MODE, reg);
sys/dev/ic/ar9380.c
301
uint32_t reg;
sys/dev/ic/ar9380.c
311
reg = AR_READ(sc, AR9485_PHY_65NM_CH0_TOP2);
sys/dev/ic/ar9380.c
312
reg = RW(reg, AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL,
sys/dev/ic/ar9380.c
314
AR_WRITE(sc, AR9485_PHY_65NM_CH0_TOP2, reg);
sys/dev/ic/ar9380.c
316
reg = AR_READ(sc, AR_PHY_65NM_CH0_TOP);
sys/dev/ic/ar9380.c
317
reg = RW(reg, AR_PHY_65NM_CH0_TOP_XPABIASLVL,
sys/dev/ic/ar9380.c
319
AR_WRITE(sc, AR_PHY_65NM_CH0_TOP, reg);
sys/dev/ic/ar9380.c
320
reg = AR_READ(sc, AR_PHY_65NM_CH0_THERM);
sys/dev/ic/ar9380.c
321
reg = RW(reg, AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB,
sys/dev/ic/ar9380.c
323
reg |= AR_PHY_65NM_CH0_THERM_XPASHORT2GND;
sys/dev/ic/ar9380.c
324
AR_WRITE(sc, AR_PHY_65NM_CH0_THERM, reg);
sys/dev/ic/ar9380.c
328
reg = AR_READ(sc, AR_PHY_SWITCH_COM);
sys/dev/ic/ar9380.c
329
reg = RW(reg, AR_SWITCH_TABLE_COM_ALL, modal->antCtrlCommon);
sys/dev/ic/ar9380.c
330
AR_WRITE(sc, AR_PHY_SWITCH_COM, reg);
sys/dev/ic/ar9380.c
331
reg = AR_READ(sc, AR_PHY_SWITCH_COM_2);
sys/dev/ic/ar9380.c
332
reg = RW(reg, AR_SWITCH_TABLE_COM_2_ALL, modal->antCtrlCommon2);
sys/dev/ic/ar9380.c
333
AR_WRITE(sc, AR_PHY_SWITCH_COM_2, reg);
sys/dev/ic/ar9380.c
337
reg = AR_READ(sc, AR_PHY_SWITCH_CHAIN(i));
sys/dev/ic/ar9380.c
338
reg = RW(reg, AR_SWITCH_TABLE_ALL, modal->antCtrlChain[i]);
sys/dev/ic/ar9380.c
339
AR_WRITE(sc, AR_PHY_SWITCH_CHAIN(i), reg);
sys/dev/ic/ar9380.c
344
reg = AR_READ(sc, AR_PHY_MC_GAIN_CTRL);
sys/dev/ic/ar9380.c
345
reg = RW(reg, AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL,
sys/dev/ic/ar9380.c
348
reg |= AR_PHY_MC_GAIN_CTRL_ENABLE_ANT_DIV;
sys/dev/ic/ar9380.c
350
reg &= ~AR_PHY_MC_GAIN_CTRL_ENABLE_ANT_DIV;
sys/dev/ic/ar9380.c
351
AR_WRITE(sc, AR_PHY_MC_GAIN_CTRL, reg);
sys/dev/ic/ar9380.c
352
reg = AR_READ(sc, AR_PHY_CCK_DETECT);
sys/dev/ic/ar9380.c
354
reg |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
sys/dev/ic/ar9380.c
356
reg &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
sys/dev/ic/ar9380.c
357
AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
sys/dev/ic/ar9380.c
362
reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS1);
sys/dev/ic/ar9380.c
363
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_0, 5);
sys/dev/ic/ar9380.c
364
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_1, 5);
sys/dev/ic/ar9380.c
365
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_2, 5);
sys/dev/ic/ar9380.c
366
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_3, 5);
sys/dev/ic/ar9380.c
367
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_4, 5);
sys/dev/ic/ar9380.c
368
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_5, 5);
sys/dev/ic/ar9380.c
369
AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS1, reg);
sys/dev/ic/ar9380.c
371
reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS2);
sys/dev/ic/ar9380.c
372
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_0, 5);
sys/dev/ic/ar9380.c
373
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_1, 5);
sys/dev/ic/ar9380.c
374
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_2, 5);
sys/dev/ic/ar9380.c
375
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_3, 5);
sys/dev/ic/ar9380.c
376
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_4, 5);
sys/dev/ic/ar9380.c
377
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_5, 5);
sys/dev/ic/ar9380.c
378
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_6, 5);
sys/dev/ic/ar9380.c
379
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_7, 5);
sys/dev/ic/ar9380.c
380
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_8, 5);
sys/dev/ic/ar9380.c
381
AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS2, reg);
sys/dev/ic/ar9380.c
383
reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS4);
sys/dev/ic/ar9380.c
384
reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_0, 5);
sys/dev/ic/ar9380.c
385
reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_1, 5);
sys/dev/ic/ar9380.c
386
reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_2, 5);
sys/dev/ic/ar9380.c
387
AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS4, reg);
sys/dev/ic/ar9380.c
419
reg = AR_READ(sc, AR_PHY_EXT_ATTEN_CTL(i));
sys/dev/ic/ar9380.c
420
reg = RW(reg, AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, db);
sys/dev/ic/ar9380.c
421
reg = RW(reg, AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, margin);
sys/dev/ic/ar9380.c
422
AR_WRITE(sc, AR_PHY_EXT_ATTEN_CTL(i), reg);
sys/dev/ic/ar9380.c
434
reg = AR_READ(sc, AR9485_PHY_CH0_XTAL);
sys/dev/ic/ar9380.c
435
reg = RW(reg, AR9485_PHY_CH0_XTAL_CAPINDAC,
sys/dev/ic/ar9380.c
437
reg = RW(reg, AR9485_PHY_CH0_XTAL_CAPOUTDAC,
sys/dev/ic/ar9380.c
439
AR_WRITE(sc, AR9485_PHY_CH0_XTAL, reg);
sys/dev/ic/ar9380.c
484
uint32_t reg;
sys/dev/ic/ar9380.c
492
reg = ar9486_pmu_read(sc, AR_PHY_PMU2);
sys/dev/ic/ar9380.c
493
reg = (reg & ~0xffc00000) | 0x10000000;
sys/dev/ic/ar9380.c
494
ar9485_pmu_write(sc, AR_PHY_PMU2, reg);
sys/dev/ic/ar9380.c
511
uint32_t reg;
sys/dev/ic/ar9380.c
520
reg = AR_READ(sc, AR_PHY_AGC_CONTROL);
sys/dev/ic/ar9380.c
521
reg = RW(reg, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
sys/dev/ic/ar9380.c
522
AR_WRITE(sc, AR_PHY_AGC_CONTROL, reg);
sys/dev/ic/ar9380.c
523
reg = AR_READ(sc, AR_PHY_CCK_SPUR_MIT);
sys/dev/ic/ar9380.c
524
reg = RW(reg, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0);
sys/dev/ic/ar9380.c
525
reg &= ~AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT;
sys/dev/ic/ar9380.c
526
AR_WRITE(sc, AR_PHY_CCK_SPUR_MIT, reg);
sys/dev/ic/ar9380.c
532
reg = AR_READ(sc, AR_PHY_AGC_CONTROL);
sys/dev/ic/ar9380.c
533
reg = RW(reg, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
sys/dev/ic/ar9380.c
534
AR_WRITE(sc, AR_PHY_AGC_CONTROL, reg);
sys/dev/ic/ar9380.c
536
reg = AR_READ(sc, AR_PHY_CCK_SPUR_MIT);
sys/dev/ic/ar9380.c
537
reg = RW(reg, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, freq);
sys/dev/ic/ar9380.c
538
reg = RW(reg, AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
sys/dev/ic/ar9380.c
539
reg = RW(reg, AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 0x2);
sys/dev/ic/ar9380.c
540
reg |= AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT;
sys/dev/ic/ar9380.c
541
AR_WRITE(sc, AR_PHY_CCK_SPUR_MIT, reg);
sys/dev/ic/ar9380.c
551
uint32_t reg;
sys/dev/ic/ar9380.c
565
reg = AR_READ(sc, AR_PHY_TIMING11);
sys/dev/ic/ar9380.c
566
reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
sys/dev/ic/ar9380.c
567
reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
sys/dev/ic/ar9380.c
568
reg &= ~AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC;
sys/dev/ic/ar9380.c
569
reg &= ~AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR;
sys/dev/ic/ar9380.c
570
AR_WRITE(sc, AR_PHY_TIMING11, reg);
sys/dev/ic/ar9380.c
577
reg = AR_READ(sc, AR_PHY_SPUR_REG);
sys/dev/ic/ar9380.c
578
reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
sys/dev/ic/ar9380.c
579
reg &= ~AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI;
sys/dev/ic/ar9380.c
580
reg &= ~AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT;
sys/dev/ic/ar9380.c
581
reg &= ~AR_PHY_SPUR_REG_ENABLE_MASK_PPM;
sys/dev/ic/ar9380.c
582
AR_WRITE(sc, AR_PHY_SPUR_REG, reg);
sys/dev/ic/ar9380.c
613
reg = AR_READ(sc, AR_PHY_GEN_CTRL);
sys/dev/ic/ar9380.c
616
(reg & AR_PHY_GC_DYN2040_PRI_CH) == 0;
sys/dev/ic/ar9380.c
620
(reg & AR_PHY_GC_DYN2040_PRI_CH) != 0;
sys/dev/ic/ar9380.c
632
reg = AR_READ(sc, AR_PHY_TIMING11);
sys/dev/ic/ar9380.c
633
reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
sys/dev/ic/ar9380.c
634
reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
sys/dev/ic/ar9380.c
635
reg |= AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC;
sys/dev/ic/ar9380.c
636
reg |= AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR;
sys/dev/ic/ar9380.c
637
AR_WRITE(sc, AR_PHY_TIMING11, reg);
sys/dev/ic/ar9380.c
639
reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
sys/dev/ic/ar9380.c
641
reg |= AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD;
sys/dev/ic/ar9380.c
643
reg &= ~AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD;
sys/dev/ic/ar9380.c
644
AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
sys/dev/ic/ar9380.c
648
reg = AR_READ(sc, AR_PHY_SPUR_REG);
sys/dev/ic/ar9380.c
649
reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
sys/dev/ic/ar9380.c
650
reg = RW(reg, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
sys/dev/ic/ar9380.c
651
reg |= AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI;
sys/dev/ic/ar9380.c
653
reg |= AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT;
sys/dev/ic/ar9380.c
654
reg |= AR_PHY_SPUR_REG_ENABLE_MASK_PPM;
sys/dev/ic/ar9380.c
655
AR_WRITE(sc, AR_PHY_SPUR_REG, reg);
sys/dev/ic/ar9380.c
666
reg = AR_READ(sc, AR_PHY_PILOT_SPUR_MASK);
sys/dev/ic/ar9380.c
667
reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, idx);
sys/dev/ic/ar9380.c
668
reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0x0c);
sys/dev/ic/ar9380.c
669
AR_WRITE(sc, AR_PHY_PILOT_SPUR_MASK, reg);
sys/dev/ic/ar9380.c
671
reg = AR_READ(sc, AR_PHY_SPUR_MASK_A);
sys/dev/ic/ar9380.c
672
reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, idx);
sys/dev/ic/ar9380.c
673
reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
sys/dev/ic/ar9380.c
674
AR_WRITE(sc, AR_PHY_SPUR_MASK_A, reg);
sys/dev/ic/ar9380.c
676
reg = AR_READ(sc, AR_PHY_CHAN_SPUR_MASK);
sys/dev/ic/ar9380.c
677
reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, idx);
sys/dev/ic/ar9380.c
678
reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0x0c);
sys/dev/ic/ar9380.c
679
AR_WRITE(sc, AR_PHY_CHAN_SPUR_MASK, reg);
sys/dev/ic/ar9380.c
841
uint32_t reg;
sys/dev/ic/ar9380.c
855
reg = AR_READ(sc, AR_PHY_TPC_11_B(i));
sys/dev/ic/ar9380.c
856
reg = RW(reg, AR_PHY_TPC_11_OLPC_GAIN_DELTA, corr);
sys/dev/ic/ar9380.c
857
AR_WRITE(sc, AR_PHY_TPC_11_B(i), reg);
sys/dev/ic/ar9380.c
860
reg = AR_READ(sc, AR_PHY_TPC_6_B(i));
sys/dev/ic/ar9380.c
861
reg = RW(reg, AR_PHY_TPC_6_ERROR_EST_MODE, 3);
sys/dev/ic/ar9380.c
862
AR_WRITE(sc, AR_PHY_TPC_6_B(i), reg);
sys/dev/ic/ar9380.c
880
reg = AR_READ(sc, AR_PHY_TPC_19);
sys/dev/ic/ar9380.c
881
reg = RW(reg, AR_PHY_TPC_19_ALPHA_THERM, slope);
sys/dev/ic/ar9380.c
882
AR_WRITE(sc, AR_PHY_TPC_19, reg);
sys/dev/ic/ar9380.c
884
reg = AR_READ(sc, AR_PHY_TPC_18);
sys/dev/ic/ar9380.c
885
reg = RW(reg, AR_PHY_TPC_18_THERM_CAL, temp0);
sys/dev/ic/ar9380.c
886
AR_WRITE(sc, AR_PHY_TPC_18, reg);
sys/dev/ic/athn.c
1138
uint32_t reg;
sys/dev/ic/athn.c
1148
reg = AR_READ(sc, AR_GPIO_INPUT_MUX1);
sys/dev/ic/athn.c
1149
reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,
sys/dev/ic/athn.c
1151
AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);
sys/dev/ic/athn.c
1160
reg = AR_READ(sc, AR_GPIO_INPUT_MUX1);
sys/dev/ic/athn.c
1161
reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,
sys/dev/ic/athn.c
1163
reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY,
sys/dev/ic/athn.c
1165
AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);
sys/dev/ic/athn.c
1177
uint32_t reg;
sys/dev/ic/athn.c
1205
reg = AR_READ(sc, AR_GPIO_PDPU);
sys/dev/ic/athn.c
1206
reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2));
sys/dev/ic/athn.c
1207
reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2);
sys/dev/ic/athn.c
1208
AR_WRITE(sc, AR_GPIO_PDPU, reg);
sys/dev/ic/athn.c
1773
uint32_t reg;
sys/dev/ic/athn.c
1779
reg = AR_READ(sc, AR_TXCFG);
sys/dev/ic/athn.c
1781
reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B);
sys/dev/ic/athn.c
1785
reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B);
sys/dev/ic/athn.c
1787
reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B);
sys/dev/ic/athn.c
1788
AR_WRITE(sc, AR_TXCFG, reg);
sys/dev/ic/athn.c
1791
reg = AR_READ(sc, AR_RXCFG);
sys/dev/ic/athn.c
1792
reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B);
sys/dev/ic/athn.c
1793
AR_WRITE(sc, AR_RXCFG, reg);
sys/dev/ic/athn.c
1816
uint32_t reg, ftrig;
sys/dev/ic/athn.c
1818
reg = AR_READ(sc, AR_TXCFG);
sys/dev/ic/athn.c
1819
ftrig = MS(reg, AR_TXCFG_FTRIG);
sys/dev/ic/athn.c
1826
reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1);
sys/dev/ic/athn.c
1827
AR_WRITE(sc, AR_TXCFG, reg);
sys/dev/ic/athn.c
2031
uint32_t tsfhi, tsflo, tsftu, reg;
sys/dev/ic/athn.c
2067
reg = AR_READ(sc, AR_RSSI_THR);
sys/dev/ic/athn.c
2068
reg = RW(reg, AR_RSSI_THR_BM_THR, 10);
sys/dev/ic/athn.c
2069
AR_WRITE(sc, AR_RSSI_THR, reg);
sys/dev/ic/athn.c
2127
uint32_t reg;
sys/dev/ic/athn.c
2132
reg = AR_READ(sc, AR_STA_ID1);
sys/dev/ic/athn.c
2133
reg &= ~AR_STA_ID1_ADHOC;
sys/dev/ic/athn.c
2134
reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE;
sys/dev/ic/athn.c
2135
AR_WRITE(sc, AR_STA_ID1, reg);
sys/dev/ic/athn.c
2141
reg = AR_READ(sc, AR_STA_ID1);
sys/dev/ic/athn.c
2142
reg &= ~AR_STA_ID1_STA_AP;
sys/dev/ic/athn.c
2143
reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE;
sys/dev/ic/athn.c
2144
AR_WRITE(sc, AR_STA_ID1, reg);
sys/dev/ic/athn.c
2150
reg = AR_READ(sc, AR_STA_ID1);
sys/dev/ic/athn.c
2151
reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP);
sys/dev/ic/athn.c
2152
reg |= AR_STA_ID1_KSRCH_MODE;
sys/dev/ic/athn.c
2153
AR_WRITE(sc, AR_STA_ID1, reg);
sys/dev/ic/athn.c
2244
uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi;
sys/dev/ic/athn.c
2296
reg = ops->gpio_read(sc, sc->rfsilent_pin);
sys/dev/ic/athn.c
2298
reg = !reg;
sys/dev/ic/athn.c
2299
if (!reg) {
sys/dev/ic/athn.c
2330
reg = AR_READ(sc, AR_AES_MUTE_MASK1);
sys/dev/ic/athn.c
2332
reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff);
sys/dev/ic/athn.c
2333
reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT,
sys/dev/ic/athn.c
2336
AR_WRITE(sc, AR_AES_MUTE_MASK1, reg);
sys/dev/ic/athn.c
2593
uint32_t reg;
sys/dev/ic/athn.c
2652
reg = AR_READ(sc, AR_RX_FILTER);
sys/dev/ic/athn.c
2653
reg = (reg & ~AR_RX_FILTER_BEACON) |
sys/dev/ic/athn.c
2655
AR_WRITE(sc, AR_RX_FILTER, reg);
sys/dev/ic/athn.c
2762
uint32_t reg = AR_READ(sc, AR_TIME_OUT);
sys/dev/ic/athn.c
2763
reg = RW(reg, AR_TIME_OUT_ACK, ackto * athn_clock_rate(sc));
sys/dev/ic/athn.c
2764
AR_WRITE(sc, AR_TIME_OUT, reg);
sys/dev/ic/athn.c
2773
uint32_t reg = AR_READ(sc, AR_TIME_OUT);
sys/dev/ic/athn.c
2779
reg = RW(reg, AR_TIME_OUT_CTS, ctsto * athn_clock_rate(sc));
sys/dev/ic/athn.c
2780
AR_WRITE(sc, AR_TIME_OUT, reg);
sys/dev/ic/athn.c
2788
uint32_t reg = AR_READ(sc, AR_USEC);
sys/dev/ic/athn.c
2789
reg = RW(reg, AR_USEC_USEC, clockrate - 1);
sys/dev/ic/athn.c
2790
AR_WRITE(sc, AR_USEC, reg);
sys/dev/ic/athn.c
534
reg = AR_READ(sc, AR_PHY_ERR);
sys/dev/ic/athn.c
535
reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING |
sys/dev/ic/athn.c
537
AR_WRITE(sc, AR_PHY_ERR, reg);
sys/dev/ic/athn.c
538
if (reg != 0)
sys/dev/ic/athn.c
565
uint32_t reg;
sys/dev/ic/athn.c
567
reg = AR_READ(sc, AR_SREV);
sys/dev/ic/athn.c
568
if (MS(reg, AR_SREV_ID) == 0xff) {
sys/dev/ic/athn.c
569
sc->mac_ver = MS(reg, AR_SREV_VERSION2);
sys/dev/ic/athn.c
570
sc->mac_rev = MS(reg, AR_SREV_REVISION2);
sys/dev/ic/athn.c
571
if (!(reg & AR_SREV_TYPE2_HOST_MODE))
sys/dev/ic/athn.c
574
sc->mac_ver = MS(reg, AR_SREV_VERSION);
sys/dev/ic/athn.c
575
sc->mac_rev = MS(reg, AR_SREV_REVISION);
sys/dev/ic/athnreg.h
1471
#define AR_READ(sc, reg) \
sys/dev/ic/athnreg.h
1472
(sc)->ops.read((sc), (reg))
sys/dev/ic/athnreg.h
1474
#define AR_WRITE(sc, reg, val) \
sys/dev/ic/athnreg.h
1475
(sc)->ops.write((sc), (reg), (val))
sys/dev/ic/athnreg.h
1480
#define AR_SETBITS(sc, reg, mask) \
sys/dev/ic/athnreg.h
1481
AR_WRITE(sc, reg, AR_READ(sc, reg) | (mask))
sys/dev/ic/athnreg.h
1483
#define AR_CLRBITS(sc, reg, mask) \
sys/dev/ic/athnreg.h
1484
AR_WRITE(sc, reg, AR_READ(sc, reg) & ~(mask))
sys/dev/ic/atw.c
1759
u_int32_t reg;
sys/dev/ic/atw.c
1812
reg = ATW_READ(sc, ATW_PLCPHD);
sys/dev/ic/atw.c
1813
reg &= ~ATW_PLCPHD_SERVICE_MASK;
sys/dev/ic/atw.c
1814
reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK),
sys/dev/ic/atw.c
1816
ATW_WRITE(sc, ATW_PLCPHD, reg);
sys/dev/ic/atw.c
1830
u_int32_t reg;
sys/dev/ic/atw.c
1833
reg = sc->sc_bbpctl_wr |
sys/dev/ic/atw.c
1838
ATW_WRITE(sc, ATW_BBPCTL, reg);
sys/dev/ic/atw.c
1868
u_int32_t reg;
sys/dev/ic/atw.c
1883
reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK);
sys/dev/ic/atw.c
1885
ATW_WRITE(sc, ATW_BBPCTL, reg);
sys/dev/ic/atw.c
1897
sc->sc_dev.dv_xname, reg);
sys/dev/ic/atw.c
1901
*val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK);
sys/dev/ic/atw.c
1916
uint32_t bits, mask, reg;
sys/dev/ic/atw.c
1935
reg = ATW_SYNRF_SELSYN;
sys/dev/ic/atw.c
1939
ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF);
sys/dev/ic/atw.c
1940
ATW_WRITE(sc, ATW_SYNRF, reg);
sys/dev/ic/atw.c
1944
reg |= ATW_SYNRF_SYNDATA;
sys/dev/ic/atw.c
1946
reg &= ~ATW_SYNRF_SYNDATA;
sys/dev/ic/atw.c
1947
ATW_WRITE(sc, ATW_SYNRF, reg);
sys/dev/ic/atw.c
1948
ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK);
sys/dev/ic/atw.c
1949
ATW_WRITE(sc, ATW_SYNRF, reg);
sys/dev/ic/atw.c
1951
ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF);
sys/dev/ic/atw.c
1965
u_int32_t reg;
sys/dev/ic/atw.c
1982
reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK);
sys/dev/ic/atw.c
1984
ATW_WRITE(sc, ATW_SYNCTL, reg);
sys/dev/ic/atw.c
1996
sc->sc_dev.dv_xname, reg);
sys/dev/ic/atw.c
2160
u_int32_t reg;
sys/dev/ic/atw.c
2190
reg = ATW_READ(sc, ATW_MACTEST);
sys/dev/ic/atw.c
2191
reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID;
sys/dev/ic/atw.c
2192
reg &= ~ATW_MACTEST_KEYID_MASK;
sys/dev/ic/atw.c
2193
reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK);
sys/dev/ic/atw.c
2194
ATW_WRITE(sc, ATW_MACTEST, reg);
sys/dev/ic/atw.c
440
#define PRINTREG(sc, reg) \
sys/dev/ic/atw.c
441
ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \
sys/dev/ic/atw.c
442
sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg)))
sys/dev/ic/atw.c
546
u_int32_t reg;
sys/dev/ic/atw.c
664
reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK);
sys/dev/ic/atw.c
668
reg |= ATW_SYNCTL_CS1;
sys/dev/ic/atw.c
671
reg |= ATW_SYNCTL_CS0;
sys/dev/ic/atw.c
677
sc->sc_synctl_rd = reg | ATW_SYNCTL_RD;
sys/dev/ic/atw.c
678
sc->sc_synctl_wr = reg | ATW_SYNCTL_WR;
sys/dev/ic/atw.c
680
reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK);
sys/dev/ic/atw.c
684
reg |= ATW_BBPCTL_TWI;
sys/dev/ic/atw.c
687
reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO |
sys/dev/ic/atw.c
698
sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR;
sys/dev/ic/atw.c
699
sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD;
sys/dev/ic/atw.c
766
reg = ATW_READ(sc, ATW_PAR0);
sys/dev/ic/atw.c
767
ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK);
sys/dev/ic/atw.c
768
ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK);
sys/dev/ic/atw.c
769
ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK);
sys/dev/ic/atw.c
770
ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK);
sys/dev/ic/atw.c
771
reg = ATW_READ(sc, ATW_PAR1);
sys/dev/ic/atw.c
772
ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK);
sys/dev/ic/atw.c
773
ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK);
sys/dev/ic/atwreg.h
79
#define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))
sys/dev/ic/atwvar.h
420
#define ATW_READ(sc, reg) \
sys/dev/ic/atwvar.h
421
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
sys/dev/ic/atwvar.h
423
#define ATW_WRITE(sc, reg, val) \
sys/dev/ic/atwvar.h
424
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/ic/atwvar.h
426
#define ATW_SET(sc, reg, mask) \
sys/dev/ic/atwvar.h
427
ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) | (mask))
sys/dev/ic/atwvar.h
429
#define ATW_CLR(sc, reg, mask) \
sys/dev/ic/atwvar.h
430
ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) & ~(mask))
sys/dev/ic/atwvar.h
432
#define ATW_ISSET(sc, reg, mask) \
sys/dev/ic/atwvar.h
433
(ATW_READ((sc), (reg)) & (mask))
sys/dev/ic/ax88190.c
153
ax88190_mii_readreg(struct device *self, int phy, int reg)
sys/dev/ic/ax88190.c
155
return (mii_bitbang_readreg(self, &ax88190_mii_bitbang_ops, phy, reg));
sys/dev/ic/ax88190.c
159
ax88190_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/ax88190.c
161
mii_bitbang_writereg(self, &ax88190_mii_bitbang_ops, phy, reg, val);
sys/dev/ic/bcmgenet.c
112
genet_mii_readreg(struct device *dev, int phy, int reg)
sys/dev/ic/bcmgenet.c
120
__SHIFTIN(reg, GENET_MDIO_REG));
sys/dev/ic/bcmgenet.c
128
sc->sc_dev.dv_xname, phy, reg);
sys/dev/ic/bcmgenet.c
133
genet_mii_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/ic/bcmgenet.c
141
__SHIFTIN(reg, GENET_MDIO_REG));
sys/dev/ic/bcmgenet.c
149
sc->sc_dev.dv_xname, phy, reg);
sys/dev/ic/bcmgenet.c
79
#define RD4(sc, reg) \
sys/dev/ic/bcmgenet.c
80
bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
sys/dev/ic/bcmgenet.c
81
#define WR4(sc, reg, val) \
sys/dev/ic/bcmgenet.c
82
bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
sys/dev/ic/bwfm.c
1387
uint32_t reg;
sys/dev/ic/bwfm.c
1399
reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
sys/dev/ic/bwfm.c
1401
return (reg & (1 << 2)) != 0;
sys/dev/ic/bwfm.c
1408
reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
sys/dev/ic/bwfm.c
1410
return reg != 0;
sys/dev/ic/bwfm.c
1413
reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
sys/dev/ic/bwfm.c
1415
return reg != 0;
sys/dev/ic/bwfm.c
1418
reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
sys/dev/ic/bwfm.c
1420
return (reg & BWFM_CHIP_REG_SR_CONTROL0_ENABLE) != 0;
sys/dev/ic/bwfm.c
1425
reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
sys/dev/ic/bwfm.c
1427
return (reg & (BWFM_CHIP_REG_RETENTION_CTL_MACPHY_DIS |
sys/dev/ic/bwfm.c
1433
reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
sys/dev/ic/bwfm.c
1435
if ((reg & BWFM_CHIP_REG_PMUCAPABILITIES_SR_SUPP) == 0)
sys/dev/ic/bwfm.c
1438
reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
sys/dev/ic/bwfm.c
1440
return (reg & (BWFM_CHIP_REG_RETENTION_CTL_MACPHY_DIS |
sys/dev/ic/bwivar.h
74
#define CSR_READ_4(sc, reg) \
sys/dev/ic/bwivar.h
75
bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
sys/dev/ic/bwivar.h
76
#define CSR_READ_2(sc, reg) \
sys/dev/ic/bwivar.h
77
bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
sys/dev/ic/bwivar.h
79
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/ic/bwivar.h
80
bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/ic/bwivar.h
81
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/ic/bwivar.h
82
bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/ic/bwivar.h
84
#define CSR_SETBITS_4(sc, reg, bits) \
sys/dev/ic/bwivar.h
85
CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
sys/dev/ic/bwivar.h
86
#define CSR_SETBITS_2(sc, reg, bits) \
sys/dev/ic/bwivar.h
87
CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
sys/dev/ic/bwivar.h
89
#define CSR_FILT_SETBITS_4(sc, reg, filt, bits) \
sys/dev/ic/bwivar.h
90
CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
sys/dev/ic/bwivar.h
91
#define CSR_FILT_SETBITS_2(sc, reg, filt, bits) \
sys/dev/ic/bwivar.h
92
CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
sys/dev/ic/bwivar.h
94
#define CSR_CLRBITS_4(sc, reg, bits) \
sys/dev/ic/bwivar.h
95
CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
sys/dev/ic/bwivar.h
96
#define CSR_CLRBITS_2(sc, reg, bits) \
sys/dev/ic/bwivar.h
97
CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
sys/dev/ic/ciss.c
885
bus_size_t reg;
sys/dev/ic/ciss.c
895
reg = CISS_OUTQ64_HI;
sys/dev/ic/ciss.c
897
reg = CISS_OUTQ64_LO;
sys/dev/ic/ciss.c
899
reg = CISS_OUTQ;
sys/dev/ic/ciss.c
900
while ((id = bus_space_read_4(sc->iot, sc->ioh, reg)) != 0xffffffff) {
sys/dev/ic/ciss.c
901
if (reg == CISS_OUTQ64_HI)
sys/dev/ic/ciss.c
904
else if (reg == CISS_OUTQ64_LO)
sys/dev/ic/com.c
1645
com_read_reg(struct com_softc *sc, bus_size_t reg)
sys/dev/ic/com.c
1647
reg <<= sc->sc_reg_shift;
sys/dev/ic/com.c
1650
return bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);
sys/dev/ic/com.c
1652
return bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg);
sys/dev/ic/com.c
1656
com_write_reg(struct com_softc *sc, bus_size_t reg, uint8_t value)
sys/dev/ic/com.c
1658
reg <<= sc->sc_reg_shift;
sys/dev/ic/com.c
1661
bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, value);
sys/dev/ic/com.c
1663
bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, value);
sys/dev/ic/com.c
1672
comcn_read_reg(bus_size_t reg)
sys/dev/ic/com.c
1674
reg <<= comcons_reg_shift;
sys/dev/ic/com.c
1677
return bus_space_read_4(comconsiot, comconsioh, reg);
sys/dev/ic/com.c
1679
return bus_space_read_1(comconsiot, comconsioh, reg);
sys/dev/ic/com.c
1683
comcn_write_reg(bus_size_t reg, uint8_t value)
sys/dev/ic/com.c
1685
reg <<= comcons_reg_shift;
sys/dev/ic/com.c
1688
bus_space_write_4(comconsiot, comconsioh, reg, value);
sys/dev/ic/com.c
1690
bus_space_write_1(comconsiot, comconsioh, reg, value);
sys/dev/ic/cyreg.h
105
#define cd_read_reg(cy,reg) bus_space_read_1(cy->cy_memt, cy->cy_memh, \
sys/dev/ic/cyreg.h
106
cy->cy_chip_offs+(((reg<<1))<<cy->cy_bustype))
sys/dev/ic/cyreg.h
108
#define cd_write_reg(cy,reg,val) bus_space_write_1(cy->cy_memt, cy->cy_memh, \
sys/dev/ic/cyreg.h
109
cy->cy_chip_offs+(((reg<<1))<<cy->cy_bustype), \
sys/dev/ic/cyreg.h
115
#define cd_read_reg_sc(sc,chip,reg) bus_space_read_1(sc->sc_memt, \
sys/dev/ic/cyreg.h
118
(((reg<<1))<<sc->sc_bustype))
sys/dev/ic/cyreg.h
120
#define cd_write_reg_sc(sc,chip,reg,val) bus_space_write_1(sc->sc_memt, \
sys/dev/ic/cyreg.h
123
(((reg<<1))<<sc->sc_bustype), \
sys/dev/ic/dc.c
1375
u_int32_t reg;
sys/dev/ic/dc.c
1389
reg = (p[0] | (p[1] << 8)) << 16;
sys/dev/ic/dc.c
1390
CSR_WRITE_4(sc, DC_WATCHDOG, reg);
sys/dev/ic/dc.c
1394
reg = (p[0] | (p[1] << 8)) << 16;
sys/dev/ic/dc.c
1395
CSR_WRITE_4(sc, DC_WATCHDOG, reg);
sys/dev/ic/dc.c
1569
u_int32_t reg;
sys/dev/ic/dc.c
1599
reg = CSR_READ_4(sc, DC_AL_PAR0);
sys/dev/ic/dc.c
1600
sc->sc_arpcom.ac_enaddr[0] = (reg & 0xff);
sys/dev/ic/dc.c
1601
sc->sc_arpcom.ac_enaddr[1] = (reg >> 8) & 0xff;
sys/dev/ic/dc.c
1602
sc->sc_arpcom.ac_enaddr[2] = (reg >> 16) & 0xff;
sys/dev/ic/dc.c
1603
sc->sc_arpcom.ac_enaddr[3] = (reg >> 24) & 0xff;
sys/dev/ic/dc.c
1604
reg = CSR_READ_4(sc, DC_AL_PAR1);
sys/dev/ic/dc.c
1605
sc->sc_arpcom.ac_enaddr[4] = (reg & 0xff);
sys/dev/ic/dc.c
1606
sc->sc_arpcom.ac_enaddr[5] = (reg >> 8) & 0xff;
sys/dev/ic/dc.c
195
#define DC_SETBIT(sc, reg, x) \
sys/dev/ic/dc.c
196
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
sys/dev/ic/dc.c
198
#define DC_CLRBIT(sc, reg, x) \
sys/dev/ic/dc.c
199
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
sys/dev/ic/dc.c
627
dc_miibus_readreg(struct device *self, int phy, int reg)
sys/dev/ic/dc.c
655
switch(reg) {
sys/dev/ic/dc.c
683
(phy << 23) | (reg << 18));
sys/dev/ic/dc.c
696
switch(reg) {
sys/dev/ic/dc.c
720
sc->sc_dev.dv_xname, reg);
sys/dev/ic/dc.c
735
frame.mii_regaddr = reg;
sys/dev/ic/dc.c
748
dc_miibus_writereg(struct device *self, int phy, int reg, int data)
sys/dev/ic/dc.c
763
(phy << 23) | (reg << 10) | data);
sys/dev/ic/dc.c
772
switch(reg) {
sys/dev/ic/dc.c
796
sc->sc_dev.dv_xname, reg);
sys/dev/ic/dc.c
805
frame.mii_regaddr = reg;
sys/dev/ic/dcreg.h
778
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/ic/dcreg.h
779
bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val)
sys/dev/ic/dcreg.h
781
#define CSR_READ_4(sc, reg) \
sys/dev/ic/dcreg.h
782
bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg)
sys/dev/ic/dl10019.c
197
dl10019_mii_readreg(struct device *self, int phy, int reg)
sys/dev/ic/dl10019.c
205
return (mii_bitbang_readreg(self, ops, phy, reg));
sys/dev/ic/dl10019.c
209
dl10019_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/dl10019.c
217
mii_bitbang_writereg(self, ops, phy, reg, val);
sys/dev/ic/dp8390var.h
147
#define NIC_GET(t, h, reg) bus_space_read_1(t, h, \
sys/dev/ic/dp8390var.h
148
((sc)->sc_reg_map[reg]))
sys/dev/ic/dp8390var.h
149
#define NIC_PUT(t, h, reg, val) bus_space_write_1(t, h, \
sys/dev/ic/dp8390var.h
150
((sc)->sc_reg_map[reg]), (val))
sys/dev/ic/dwhdmi.c
325
dwhdmi_read(struct dwhdmi_softc *sc, bus_size_t reg)
sys/dev/ic/dwhdmi.c
331
val = bus_space_read_1(sc->sc_bst, sc->sc_bsh, reg);
sys/dev/ic/dwhdmi.c
334
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg * 4) & 0xff;
sys/dev/ic/dwhdmi.c
345
dwhdmi_write(struct dwhdmi_softc *sc, bus_size_t reg, uint8_t val)
sys/dev/ic/dwhdmi.c
349
bus_space_write_1(sc->sc_bst, sc->sc_bsh, reg, val);
sys/dev/ic/dwhdmi.c
352
bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg * 4, val);
sys/dev/ic/dwhdmiphy.c
179
uint8_t reg;
sys/dev/ic/dwhdmiphy.c
181
reg = dwhdmi_read(sc, HDMI_PHY_CONF0);
sys/dev/ic/dwhdmiphy.c
182
reg &= ~HDMI_PHY_CONF0_PDZ_MASK;
sys/dev/ic/dwhdmiphy.c
183
reg |= (enable << HDMI_PHY_CONF0_PDZ_OFFSET);
sys/dev/ic/dwhdmiphy.c
184
dwhdmi_write(sc, HDMI_PHY_CONF0, reg);
sys/dev/ic/dwhdmiphy.c
190
uint8_t reg;
sys/dev/ic/dwhdmiphy.c
192
reg = dwhdmi_read(sc, HDMI_PHY_CONF0);
sys/dev/ic/dwhdmiphy.c
193
reg &= ~HDMI_PHY_CONF0_ENTMDS_MASK;
sys/dev/ic/dwhdmiphy.c
194
reg |= (enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);
sys/dev/ic/dwhdmiphy.c
195
dwhdmi_write(sc, HDMI_PHY_CONF0, reg);
sys/dev/ic/dwhdmiphy.c
201
uint8_t reg;
sys/dev/ic/dwhdmiphy.c
203
reg = dwhdmi_read(sc, HDMI_PHY_CONF0);
sys/dev/ic/dwhdmiphy.c
204
reg &= ~HDMI_PHY_CONF0_GEN2_PDDQ_MASK;
sys/dev/ic/dwhdmiphy.c
205
reg |= (enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);
sys/dev/ic/dwhdmiphy.c
206
dwhdmi_write(sc, HDMI_PHY_CONF0, reg);
sys/dev/ic/dwhdmiphy.c
212
uint8_t reg;
sys/dev/ic/dwhdmiphy.c
214
reg = dwhdmi_read(sc, HDMI_PHY_CONF0);
sys/dev/ic/dwhdmiphy.c
215
reg &= ~HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
sys/dev/ic/dwhdmiphy.c
216
reg |= (enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);
sys/dev/ic/dwhdmiphy.c
217
dwhdmi_write(sc, HDMI_PHY_CONF0, reg);
sys/dev/ic/dwhdmiphy.c
223
uint8_t reg;
sys/dev/ic/dwhdmiphy.c
225
reg = dwhdmi_read(sc, HDMI_PHY_CONF0);
sys/dev/ic/dwhdmiphy.c
226
reg &= ~HDMI_PHY_CONF0_SELDATAENPOL_MASK;
sys/dev/ic/dwhdmiphy.c
227
reg |= (enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);
sys/dev/ic/dwhdmiphy.c
228
dwhdmi_write(sc, HDMI_PHY_CONF0, reg);
sys/dev/ic/dwhdmiphy.c
234
uint8_t reg;
sys/dev/ic/dwhdmiphy.c
236
reg = dwhdmi_read(sc, HDMI_PHY_CONF0);
sys/dev/ic/dwhdmiphy.c
237
reg &= ~HDMI_PHY_CONF0_SELDIPIF_MASK;
sys/dev/ic/dwhdmiphy.c
238
reg |= (enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);
sys/dev/ic/dwhdmiphy.c
239
dwhdmi_write(sc, HDMI_PHY_CONF0, reg);
sys/dev/ic/dwhdmiphy.c
245
uint8_t reg;
sys/dev/ic/dwhdmiphy.c
247
reg = dwhdmi_read(sc, HDMI_PHY_CONF0);
sys/dev/ic/dwhdmiphy.c
248
reg &= ~HDMI_PHY_CONF0_SVSRET_MASK;
sys/dev/ic/dwhdmiphy.c
249
reg |= (enable << HDMI_PHY_CONF0_SVSRET_OFFSET);
sys/dev/ic/dwhdmiphy.c
250
dwhdmi_write(sc, HDMI_PHY_CONF0, reg);
sys/dev/ic/dwiic.c
139
uint32_t reg;
sys/dev/ic/dwiic.c
144
reg = dwiic_read(sc, DW_IC_COMP_TYPE);
sys/dev/ic/dwiic.c
145
if (reg != DW_IC_COMP_TYPE_VALUE) {
sys/dev/ic/dwiic.c
147
sc->sc_dev.dv_xname, reg));
sys/dev/ic/dwiic.c
175
reg = dwiic_read(sc, DW_IC_COMP_VERSION);
sys/dev/ic/dwiic.c
176
if (reg >= DW_IC_SDA_HOLD_MIN_VERS)
sys/dev/ic/dwiic.c
182
reg = dwiic_read(sc, DW_IC_COMP_PARAM_1);
sys/dev/ic/dwiic.c
183
tx_fifo_depth = DW_IC_TX_FIFO_DEPTH(reg);
sys/dev/ic/dwiic.c
184
rx_fifo_depth = DW_IC_RX_FIFO_DEPTH(reg);
sys/dev/ic/dwqe.c
1014
reg = dwqe_read(sc, GMAC_MAC_CONF);
sys/dev/ic/dwqe.c
1015
reg |= GMAC_MAC_CONF_IPC;
sys/dev/ic/dwqe.c
1016
dwqe_write(sc, GMAC_MAC_CONF, reg);
sys/dev/ic/dwqe.c
1025
uint32_t reg;
sys/dev/ic/dwqe.c
1037
reg = dwqe_read(sc, GMAC_MAC_CONF);
sys/dev/ic/dwqe.c
1038
reg &= ~GMAC_MAC_CONF_RE;
sys/dev/ic/dwqe.c
1039
dwqe_write(sc, GMAC_MAC_CONF, reg);
sys/dev/ic/dwqe.c
1042
reg = dwqe_read(sc, GMAC_CHAN_RX_CONTROL(0));
sys/dev/ic/dwqe.c
1043
reg &= ~GMAC_CHAN_RX_CONTROL_SR;
sys/dev/ic/dwqe.c
1044
dwqe_write(sc, GMAC_CHAN_RX_CONTROL(0), reg);
sys/dev/ic/dwqe.c
1047
reg = dwqe_read(sc, GMAC_CHAN_TX_CONTROL(0));
sys/dev/ic/dwqe.c
1048
reg &= ~GMAC_CHAN_TX_CONTROL_ST;
sys/dev/ic/dwqe.c
1049
dwqe_write(sc, GMAC_CHAN_TX_CONTROL(0), reg);
sys/dev/ic/dwqe.c
1052
reg = dwqe_read(sc, GMAC_MTL_CHAN_TX_OP_MODE(0));
sys/dev/ic/dwqe.c
1053
reg |= GMAC_MTL_CHAN_TX_OP_MODE_FTQ;
sys/dev/ic/dwqe.c
1054
dwqe_write(sc, GMAC_MTL_CHAN_TX_OP_MODE(0), reg);
sys/dev/ic/dwqe.c
1057
reg = dwqe_read(sc, GMAC_MTL_CHAN_TX_OP_MODE(0));
sys/dev/ic/dwqe.c
1058
if ((reg & GMAC_MTL_CHAN_TX_OP_MODE_FTQ) == 0)
sys/dev/ic/dwqe.c
1068
reg = dwqe_read(sc, GMAC_MAC_CONF);
sys/dev/ic/dwqe.c
1069
reg &= ~GMAC_MAC_CONF_TE;
sys/dev/ic/dwqe.c
1070
dwqe_write(sc, GMAC_MAC_CONF, reg);
sys/dev/ic/dwqe.c
1126
uint32_t reg;
sys/dev/ic/dwqe.c
1128
reg = 0;
sys/dev/ic/dwqe.c
1134
reg |= GMAC_MAC_PACKET_FILTER_PM;
sys/dev/ic/dwqe.c
1136
reg |= GMAC_MAC_PACKET_FILTER_PR |
sys/dev/ic/dwqe.c
1139
reg |= GMAC_MAC_PACKET_FILTER_HMC;
sys/dev/ic/dwqe.c
1159
dwqe_write(sc, GMAC_MAC_PACKET_FILTER, reg);
sys/dev/ic/dwqe.c
117
uint32_t reg;
sys/dev/ic/dwqe.c
120
reg = dwqe_read(sc, GMAC_VLAN_TAG_CTRL);
sys/dev/ic/dwqe.c
121
reg |= GMAC_VLAN_TAG_CTRL_EVLRXS | GMAC_VLAN_TAG_CTRL_STRIP_ALWAYS;
sys/dev/ic/dwqe.c
122
dwqe_write(sc, GMAC_VLAN_TAG_CTRL, reg);
sys/dev/ic/dwqe.c
130
uint32_t reg;
sys/dev/ic/dwqe.c
132
reg = dwqe_read(sc, GMAC_VLAN_TAG_INCL);
sys/dev/ic/dwqe.c
135
reg |= GMAC_VLAN_TAG_INCL_INSERT;
sys/dev/ic/dwqe.c
141
reg &= ~GMAC_VLAN_TAG_INCL_CSVL;
sys/dev/ic/dwqe.c
144
reg |= GMAC_VLAN_TAG_INCL_VLTI;
sys/dev/ic/dwqe.c
146
dwqe_write(sc, GMAC_VLAN_TAG_INCL, reg);
sys/dev/ic/dwqe.c
507
dwqe_mii_readreg(struct device *self, int phy, int reg)
sys/dev/ic/dwqe.c
515
(reg << GMAC_MAC_MDIO_ADDR_RDA_SHIFT) |
sys/dev/ic/dwqe.c
530
dwqe_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/dwqe.c
539
(reg << GMAC_MAC_MDIO_ADDR_RDA_SHIFT) |
sys/dev/ic/dwqe.c
639
uint32_t reg;
sys/dev/ic/dwqe.c
641
reg = dwqe_read(sc, GMAC_INT_STATUS);
sys/dev/ic/dwqe.c
642
dwqe_write(sc, GMAC_INT_STATUS, reg);
sys/dev/ic/dwqe.c
644
reg = dwqe_read(sc, GMAC_CHAN_STATUS(0));
sys/dev/ic/dwqe.c
645
dwqe_write(sc, GMAC_CHAN_STATUS(0), reg);
sys/dev/ic/dwqe.c
647
if (reg & GMAC_CHAN_STATUS_RI)
sys/dev/ic/dwqe.c
650
if (reg & GMAC_CHAN_STATUS_TI)
sys/dev/ic/dwqe.c
863
uint32_t mode, reg, fifosz, tqs, rqs;
sys/dev/ic/dwqe.c
933
reg = dwqe_read(sc, GMAC_CHAN_RX_CONTROL(0));
sys/dev/ic/dwqe.c
934
reg |= GMAC_CHAN_RX_CONTROL_SR;
sys/dev/ic/dwqe.c
935
dwqe_write(sc, GMAC_CHAN_RX_CONTROL(0), reg);
sys/dev/ic/dwqe.c
938
reg = dwqe_read(sc, GMAC_CHAN_TX_CONTROL(0));
sys/dev/ic/dwqe.c
939
reg |= GMAC_CHAN_TX_CONTROL_ST;
sys/dev/ic/dwqe.c
940
dwqe_write(sc, GMAC_CHAN_TX_CONTROL(0), reg);
sys/dev/ic/dwqe.c
989
reg = dwqe_read(sc, GMAC_QX_TX_FLOW_CTRL(0));
sys/dev/ic/dwqe.c
990
reg |= 0xffffU << GMAC_QX_TX_FLOW_CTRL_PT_SHIFT;
sys/dev/ic/dwqe.c
991
reg |= GMAC_QX_TX_FLOW_CTRL_TFE;
sys/dev/ic/dwqe.c
992
dwqe_write(sc, GMAC_QX_TX_FLOW_CTRL(0), reg);
sys/dev/ic/dwqe.c
993
reg = dwqe_read(sc, GMAC_RX_FLOW_CTRL);
sys/dev/ic/dwqe.c
994
reg |= GMAC_RX_FLOW_CTRL_RFE;
sys/dev/ic/dwqe.c
995
dwqe_write(sc, GMAC_RX_FLOW_CTRL, reg);
sys/dev/ic/elink3.c
1703
ep_mii_readreg(struct device *self, int phy, int reg)
sys/dev/ic/elink3.c
1720
ep_mii_sendbits(sc, reg, 5);
sys/dev/ic/elink3.c
1747
ep_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/elink3.c
1761
ep_mii_sendbits(sc, reg, 5);
sys/dev/ic/elink3.c
230
ep_w1_reg(struct ep_softc *sc, int reg)
sys/dev/ic/elink3.c
234
switch (reg) {
sys/dev/ic/elink3.c
238
return (reg);
sys/dev/ic/elink3.c
240
return (reg + 0x10);
sys/dev/ic/elink3.c
242
return (reg);
sys/dev/ic/fxp.c
1570
fxp_mdi_read(struct device *self, int phy, int reg)
sys/dev/ic/fxp.c
1577
(FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
sys/dev/ic/fxp.c
1596
fxp_mdi_write(struct device *self, int phy, int reg, int value)
sys/dev/ic/fxp.c
1602
(FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
sys/dev/ic/fxp.c
201
u_int16_t reg;
sys/dev/ic/fxp.c
209
reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
sys/dev/ic/fxp.c
211
reg = FXP_EEPROM_EECS;
sys/dev/ic/fxp.c
212
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/dev/ic/fxp.c
214
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
sys/dev/ic/fxp.c
216
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/dev/ic/fxp.c
553
u_int16_t reg;
sys/dev/ic/fxp.c
562
reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
sys/dev/ic/fxp.c
564
reg = FXP_EEPROM_EECS;
sys/dev/ic/fxp.c
566
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/dev/ic/fxp.c
568
reg | FXP_EEPROM_EESK);
sys/dev/ic/fxp.c
570
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/dev/ic/fxp.c
603
u_int16_t reg;
sys/dev/ic/fxp.c
613
reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
sys/dev/ic/fxp.c
615
reg = FXP_EEPROM_EECS;
sys/dev/ic/fxp.c
617
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/dev/ic/fxp.c
619
reg | FXP_EEPROM_EESK);
sys/dev/ic/fxp.c
621
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/dev/ic/fxp.c
629
reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
sys/dev/ic/fxp.c
631
reg = FXP_EEPROM_EECS;
sys/dev/ic/fxp.c
633
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/dev/ic/fxp.c
635
reg | FXP_EEPROM_EESK);
sys/dev/ic/fxp.c
637
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/dev/ic/fxp.c
640
reg = FXP_EEPROM_EECS;
sys/dev/ic/fxp.c
647
reg | FXP_EEPROM_EESK);
sys/dev/ic/fxp.c
652
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
sys/dev/ic/fxpvar.h
151
#define CSR_READ_2(sc, reg) \
sys/dev/ic/fxpvar.h
152
bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
sys/dev/ic/fxpvar.h
153
#define CSR_READ_4(sc, reg) \
sys/dev/ic/fxpvar.h
154
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
sys/dev/ic/fxpvar.h
155
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/ic/fxpvar.h
156
bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/ic/fxpvar.h
157
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/ic/fxpvar.h
158
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/ic/gem.c
1286
gem_mii_readreg(struct device *self, int phy, int reg)
sys/dev/ic/gem.c
1296
printf("gem_mii_readreg: phy %d reg %d\n", phy, reg);
sys/dev/ic/gem.c
1300
v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) |
sys/dev/ic/gem.c
1316
gem_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/gem.c
1327
phy, reg, val);
sys/dev/ic/gem.c
1333
(reg << GEM_MIF_REG_SHIFT) |
sys/dev/ic/gem.c
1408
gem_pcs_readreg(struct device *self, int phy, int reg)
sys/dev/ic/gem.c
1416
printf("gem_pcs_readreg: phy %d reg %d\n", phy, reg);
sys/dev/ic/gem.c
1422
switch (reg) {
sys/dev/ic/gem.c
1424
reg = GEM_MII_CONTROL;
sys/dev/ic/gem.c
1427
reg = GEM_MII_STATUS;
sys/dev/ic/gem.c
1430
reg = GEM_MII_ANAR;
sys/dev/ic/gem.c
1433
reg = GEM_MII_ANLPAR;
sys/dev/ic/gem.c
1441
return bus_space_read_4(t, pcs, reg);
sys/dev/ic/gem.c
1445
gem_pcs_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/gem.c
1455
phy, reg, val);
sys/dev/ic/gem.c
1461
if (reg == MII_ANAR)
sys/dev/ic/gem.c
1464
switch (reg) {
sys/dev/ic/gem.c
1467
reg = GEM_MII_CONTROL;
sys/dev/ic/gem.c
1470
reg = GEM_MII_STATUS;
sys/dev/ic/gem.c
1473
reg = GEM_MII_ANAR;
sys/dev/ic/gem.c
1476
reg = GEM_MII_ANLPAR;
sys/dev/ic/gem.c
1482
bus_space_write_4(t, pcs, reg, val);
sys/dev/ic/gem.c
1487
if (reg == GEM_MII_ANAR || reset) {
sys/dev/ic/gem.c
474
u_int32_t reg;
sys/dev/ic/gem.c
477
reg = bus_space_read_4(sc->sc_bustag, h, r);
sys/dev/ic/gem.c
478
if ((reg & clr) == 0 && (reg & set) == set)
sys/dev/ic/hme.c
1020
hme_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/hme.c
1053
(reg << HME_MIF_FO_REGAD_SHIFT) |
sys/dev/ic/hme.c
964
hme_mii_readreg(struct device *self, int phy, int reg)
sys/dev/ic/hme.c
996
(reg << HME_MIF_FO_REGAD_SHIFT);
sys/dev/ic/i82365.c
1064
int reg;
sys/dev/ic/i82365.c
1069
reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
sys/dev/ic/i82365.c
1070
reg &= ~mem_map_index[window].memenable;
sys/dev/ic/i82365.c
1071
pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
sys/dev/ic/i82365.c
1221
int reg;
sys/dev/ic/i82365.c
1236
reg = pcic_read(h, PCIC_IOCTL);
sys/dev/ic/i82365.c
1237
reg &= ~io_map_index[win].ioctlmask;
sys/dev/ic/i82365.c
1238
reg |= io_map_index[win].ioctlbits[h->io[win].width];
sys/dev/ic/i82365.c
1239
pcic_write(h, PCIC_IOCTL, reg);
sys/dev/ic/i82365.c
1241
reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
sys/dev/ic/i82365.c
1242
reg |= io_map_index[win].ioenable;
sys/dev/ic/i82365.c
1243
pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
sys/dev/ic/i82365.c
1295
int reg;
sys/dev/ic/i82365.c
1300
reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
sys/dev/ic/i82365.c
1301
reg &= ~io_map_index[window].ioenable;
sys/dev/ic/i82365.c
1302
pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
sys/dev/ic/i82365.c
132
int vendor, reg;
sys/dev/ic/i82365.c
1332
int cardtype, reg, win;
sys/dev/ic/i82365.c
1347
reg = pcic_read(h, PCIC_VG469_VSELECT);
sys/dev/ic/i82365.c
1348
reg &= ~PCIC_VG469_VSELECT_VCC;
sys/dev/ic/i82365.c
1349
pcic_write(h, PCIC_VG469_VSELECT, reg);
sys/dev/ic/i82365.c
1386
reg = pcic_read(h, PCIC_IF_STATUS);
sys/dev/ic/i82365.c
1387
if (!(reg & PCIC_IF_STATUS_POWERACTIVE)) {
sys/dev/ic/i82365.c
1388
printf("pcic_chip_socket_enable: status %x\n", reg);
sys/dev/ic/i82365.c
140
reg = pcic_read(h, -1);
sys/dev/ic/i82365.c
1402
reg = pcic_read(h, PCIC_INTR);
sys/dev/ic/i82365.c
1403
reg &= ~PCIC_INTR_CARDTYPE_MASK;
sys/dev/ic/i82365.c
1404
reg |= ((cardtype == PCMCIA_IFTYPE_IO) ?
sys/dev/ic/i82365.c
1407
reg |= h->ih_irq;
sys/dev/ic/i82365.c
1408
pcic_write(h, PCIC_INTR, reg);
sys/dev/ic/i82365.c
1412
((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg));
sys/dev/ic/i82365.c
142
if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) ==
sys/dev/ic/i82365.c
144
reg = pcic_read(h, -1);
sys/dev/ic/i82365.c
145
if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) {
sys/dev/ic/i82365.c
146
if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS)
sys/dev/ic/i82365.c
153
reg = pcic_read(h, PCIC_IDENT);
sys/dev/ic/i82365.c
155
switch (reg) {
sys/dev/ic/i82365.c
173
reg = pcic_read(h, PCIC_VG468_MISC);
sys/dev/ic/i82365.c
174
reg |= PCIC_VG468_MISC_VADEMREV;
sys/dev/ic/i82365.c
175
pcic_write(h, PCIC_VG468_MISC, reg);
sys/dev/ic/i82365.c
177
reg = pcic_read(h, PCIC_IDENT);
sys/dev/ic/i82365.c
179
if (reg & PCIC_IDENT_VADEM_MASK) {
sys/dev/ic/i82365.c
180
if ((reg & 7) >= 4)
sys/dev/ic/i82365.c
185
reg = pcic_read(h, PCIC_VG468_MISC);
sys/dev/ic/i82365.c
186
reg &= ~PCIC_VG468_MISC_VADEMREV;
sys/dev/ic/i82365.c
187
pcic_write(h, PCIC_VG468_MISC, reg);
sys/dev/ic/i82365.c
196
int vendor, count, i, reg;
sys/dev/ic/i82365.c
216
if (pcic_ident_ok(reg = pcic_read(&sc->handle[0], PCIC_IDENT))) {
sys/dev/ic/i82365.c
224
DPRINTF((" 0x%02x", reg));
sys/dev/ic/i82365.c
233
if (pcic_ident_ok(reg = pcic_read(&sc->handle[1], PCIC_IDENT))) {
sys/dev/ic/i82365.c
241
DPRINTF((" 0x%02x", reg));
sys/dev/ic/i82365.c
257
if (pcic_ident_ok(reg = pcic_read(&sc->handle[2],
sys/dev/ic/i82365.c
266
DPRINTF((" 0x%02x", reg));
sys/dev/ic/i82365.c
275
if (pcic_ident_ok(reg = pcic_read(&sc->handle[3],
sys/dev/ic/i82365.c
284
DPRINTF((" 0x%02x\n", reg));
sys/dev/ic/i82365.c
506
int reg;
sys/dev/ic/i82365.c
529
reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2);
sys/dev/ic/i82365.c
530
if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) {
sys/dev/ic/i82365.c
533
reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND;
sys/dev/ic/i82365.c
534
pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg);
sys/dev/ic/i82365.c
539
reg = pcic_read(h, PCIC_IF_STATUS);
sys/dev/ic/i82365.c
541
if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) ==
sys/dev/ic/i82365.c
944
int reg;
sys/dev/ic/i82365.c
974
reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
sys/dev/ic/i82365.c
975
reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16);
sys/dev/ic/i82365.c
976
pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
sys/dev/ic/ibm561.c
472
ibm561_regcont10bit(struct ibm561data *data, u_int16_t reg, u_int16_t val)
sys/dev/ic/ibm561.c
479
ibm561_regbegin(struct ibm561data *data, u_int16_t reg)
sys/dev/ic/ibm561.c
481
data->ramdac_wr(data->cookie, IBM561_ADDR_LOW, reg & 0xff);
sys/dev/ic/ibm561.c
482
data->ramdac_wr(data->cookie, IBM561_ADDR_HIGH, (reg >> 8) & 0xff);
sys/dev/ic/ibm561.c
486
ibm561_regcont(struct ibm561data *data, u_int16_t reg, u_int8_t val)
sys/dev/ic/ibm561.c
488
data->ramdac_wr(data->cookie, reg, val);
sys/dev/ic/ibm561.c
492
ibm561_regwr(struct ibm561data *data, u_int16_t reg, u_int8_t val)
sys/dev/ic/ibm561.c
494
ibm561_regbegin(data, reg);
sys/dev/ic/if_wireg.h
100
#define CSR_READ_1(sc, reg) \
sys/dev/ic/if_wireg.h
102
(sc->sc_pci ? reg * 2: reg))
sys/dev/ic/if_wireg.h
84
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/ic/if_wireg.h
86
(sc->sc_pci ? reg * 2: reg), (val))
sys/dev/ic/if_wireg.h
87
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/ic/if_wireg.h
89
(sc->sc_pci ? reg * 2: reg), (val))
sys/dev/ic/if_wireg.h
90
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/ic/if_wireg.h
92
(sc->sc_pci ? reg * 2: reg), val)
sys/dev/ic/if_wireg.h
94
#define CSR_READ_4(sc, reg) \
sys/dev/ic/if_wireg.h
96
(sc->sc_pci ? reg * 2: reg))
sys/dev/ic/if_wireg.h
97
#define CSR_READ_2(sc, reg) \
sys/dev/ic/if_wireg.h
99
(sc->sc_pci ? reg * 2: reg))
sys/dev/ic/imxiic.c
297
imxiic_read_1(struct imxiic_softc *sc, int reg)
sys/dev/ic/imxiic.c
299
reg <<= sc->sc_reg_shift;
sys/dev/ic/imxiic.c
301
return bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg);
sys/dev/ic/imxiic.c
305
imxiic_write_1(struct imxiic_softc *sc, int reg, uint8_t val)
sys/dev/ic/imxiic.c
307
reg <<= sc->sc_reg_shift;
sys/dev/ic/imxiic.c
309
bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val);
sys/dev/ic/imxiic.c
62
#define HREAD1(sc, reg) \
sys/dev/ic/imxiic.c
63
imxiic_read_1((sc), (reg))
sys/dev/ic/imxiic.c
64
#define HWRITE1(sc, reg, val) \
sys/dev/ic/imxiic.c
65
imxiic_write_1((sc), (reg), (val))
sys/dev/ic/imxiic.c
66
#define HSET1(sc, reg, bits) \
sys/dev/ic/imxiic.c
67
HWRITE1((sc), (reg), HREAD1((sc), (reg)) | (bits))
sys/dev/ic/imxiic.c
68
#define HCLR1(sc, reg, bits) \
sys/dev/ic/imxiic.c
69
HWRITE1((sc), (reg), HREAD1((sc), (reg)) & ~(bits))
sys/dev/ic/ispi.c
162
ispi_read(struct ispi_softc *sc, int reg)
sys/dev/ic/ispi.c
164
uint32_t val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);
sys/dev/ic/ispi.c
165
DPRINTF(("%s: %s(0x%x) = 0x%x\n", sc->sc_dev.dv_xname, __func__, reg,
sys/dev/ic/ispi.c
171
ispi_write(struct ispi_softc *sc, int reg, uint32_t val)
sys/dev/ic/ispi.c
173
DPRINTF(("%s: %s(0x%x, 0x%x)\n", sc->sc_dev.dv_xname, __func__, reg,
sys/dev/ic/ispi.c
175
bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, val);
sys/dev/ic/ispi.c
179
ispi_lpss_read(struct ispi_softc *sc, int reg)
sys/dev/ic/ispi.c
181
return ispi_read(sc, sc->sc_lpss_reg_offset + reg);
sys/dev/ic/ispi.c
185
ispi_lpss_write(struct ispi_softc *sc, int reg, uint32_t val)
sys/dev/ic/ispi.c
187
ispi_write(sc, sc->sc_lpss_reg_offset + reg, val);
sys/dev/ic/ispivar.h
81
void ispi_write(struct ispi_softc *sc, int reg, uint32_t val);
sys/dev/ic/ispivar.h
82
uint32_t ispi_read(struct ispi_softc *sc, int reg);
sys/dev/ic/lm78.c
704
data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);
sys/dev/ic/lm78.c
720
sdata = sc->lm_readreg(sc, sc->lm_sensors[n].reg);
sys/dev/ic/lm78.c
745
if (sc->lm_sensors[n].reg == LM_FAN1 ||
sys/dev/ic/lm78.c
746
sc->lm_sensors[n].reg == LM_FAN2) {
sys/dev/ic/lm78.c
748
if (sc->lm_sensors[n].reg == LM_FAN1)
sys/dev/ic/lm78.c
754
data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);
sys/dev/ic/lm78.c
790
data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);
sys/dev/ic/lm78.c
810
data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);
sys/dev/ic/lm78.c
823
data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);
sys/dev/ic/lm78.c
843
sdata = sc->lm_readreg(sc, sc->lm_sensors[n].reg) << 1;
sys/dev/ic/lm78.c
844
sdata += sc->lm_readreg(sc, sc->lm_sensors[n].reg + 1) >> 7;
sys/dev/ic/lm78.c
867
if (sc->lm_sensors[n].reg == LM_FAN1 ||
sys/dev/ic/lm78.c
868
sc->lm_sensors[n].reg == LM_FAN2 ||
sys/dev/ic/lm78.c
869
sc->lm_sensors[n].reg == LM_FAN3) {
sys/dev/ic/lm78.c
871
fan = (sc->lm_sensors[n].reg - LM_FAN1);
sys/dev/ic/lm78.c
876
if (sc->lm_sensors[n].reg == LM_FAN1 ||
sys/dev/ic/lm78.c
877
sc->lm_sensors[n].reg == LM_FAN2) {
sys/dev/ic/lm78.c
879
if (sc->lm_sensors[n].reg == LM_FAN1)
sys/dev/ic/lm78.c
883
} else if (sc->lm_sensors[n].reg == LM_FAN3) {
sys/dev/ic/lm78.c
886
} else if (sc->lm_sensors[n].reg == WB_BANK0_FAN4 ||
sys/dev/ic/lm78.c
887
sc->lm_sensors[n].reg == WB_BANK0_FAN5) {
sys/dev/ic/lm78.c
889
if (sc->lm_sensors[n].reg == WB_BANK0_FAN4)
sys/dev/ic/lm78.c
895
data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);
sys/dev/ic/lm78.c
911
datah = sc->lm_readreg(sc, sc->lm_sensors[n].reg);
sys/dev/ic/lm78.c
912
datal = sc->lm_readreg(sc, sc->lm_sensors[n].reg + 1);
sys/dev/ic/lm78.c
927
int reg, shift, data, divisor = 1;
sys/dev/ic/lm78.c
929
switch (sc->lm_sensors[n].reg) {
sys/dev/ic/lm78.c
931
reg = 0x47; shift = 0;
sys/dev/ic/lm78.c
934
reg = 0x47; shift = 4;
sys/dev/ic/lm78.c
937
reg = 0x5b; shift = 0;
sys/dev/ic/lm78.c
940
reg = 0x5b; shift = 4;
sys/dev/ic/lm78.c
943
reg = 0x5c; shift = 0;
sys/dev/ic/lm78.c
946
reg = 0x5c; shift = 4;
sys/dev/ic/lm78.c
949
reg = 0x9e; shift = 0;
sys/dev/ic/lm78.c
952
reg = 0;
sys/dev/ic/lm78.c
956
data = sc->lm_readreg(sc, sc->lm_sensors[n].reg);
sys/dev/ic/lm78.c
961
if (reg != 0)
sys/dev/ic/lm78.c
962
divisor = (sc->lm_readreg(sc, reg) >> shift) & 0x7;
sys/dev/ic/lm78.c
978
sdata = sc->lm_readreg(sc, sc->lm_sensors[n].reg) << 1;
sys/dev/ic/lm78.c
979
sdata += sc->lm_readreg(sc, sc->lm_sensors[n].reg + 1) >> 7;
sys/dev/ic/lm78var.h
134
u_int8_t reg;
sys/dev/ic/mc146818reg.h
151
u_int mc146818_read(void *sc, u_int reg);
sys/dev/ic/mc146818reg.h
152
void mc146818_write(void *sc, u_int reg, u_int datum);
sys/dev/ic/mpi.c
1221
u_int32_t reg;
sys/dev/ic/mpi.c
1234
reg = mpi_pop_reply(sc);
sys/dev/ic/mpi.c
1235
if (reg == 0xffffffff) {
sys/dev/ic/mpi.c
1245
mpi_reply(sc, reg);
sys/dev/ic/mpi.c
913
u_int32_t reg;
sys/dev/ic/mpi.c
919
while ((reg = mpi_pop_reply(sc)) != 0xffffffff) {
sys/dev/ic/mpi.c
920
mpi_reply(sc, reg);
sys/dev/ic/mpi.c
928
mpi_reply(struct mpi_softc *sc, u_int32_t reg)
sys/dev/ic/mpi.c
937
DNPRINTF(MPI_D_INTR, "%s: mpi_reply reg: 0x%08x\n", DEVNAME(sc), reg);
sys/dev/ic/mpi.c
939
if (reg & MPI_REPLY_QUEUE_ADDRESS) {
sys/dev/ic/mpi.c
940
reply_dva = (reg & MPI_REPLY_QUEUE_ADDRESS_MASK) << 1;
sys/dev/ic/mpi.c
953
switch (reg & MPI_REPLY_QUEUE_TYPE_MASK) {
sys/dev/ic/mpi.c
955
id = reg & MPI_REPLY_QUEUE_CONTEXT;
sys/dev/ic/mtd8xx.c
214
mtd_mii_command(struct mtd_softc *sc, int opcode, int phy, int reg)
sys/dev/ic/mtd8xx.c
229
data = opcode | (phy << 7) | (reg << 2);
sys/dev/ic/mtd8xx.c
249
mtd_miibus_readreg(struct device *self, int phy, int reg)
sys/dev/ic/mtd8xx.c
254
return (phy ? 0 : (int)CSR_READ_2(MTD_PHYCSR + (reg << 1)));
sys/dev/ic/mtd8xx.c
258
miir = mtd_mii_command(sc, MII_OPCODE_RD, phy, reg);
sys/dev/ic/mtd8xx.c
278
mtd_miibus_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/mtd8xx.c
284
CSR_WRITE_2(MTD_PHYCSR + (reg << 1), val);
sys/dev/ic/mtd8xx.c
288
miir = mtd_mii_command(sc, MII_OPCODE_WR, phy, reg);
sys/dev/ic/mtd8xxreg.h
200
#define CSR_READ_1(reg) bus_space_read_1(sc->sc_bust, sc->sc_bush, reg)
sys/dev/ic/mtd8xxreg.h
201
#define CSR_WRITE_1(reg, val) \
sys/dev/ic/mtd8xxreg.h
202
bus_space_write_1(sc->sc_bust, sc->sc_bush, reg, val)
sys/dev/ic/mtd8xxreg.h
204
#define CSR_READ_2(reg) bus_space_read_2(sc->sc_bust, sc->sc_bush, reg)
sys/dev/ic/mtd8xxreg.h
205
#define CSR_WRITE_2(reg, vat) \
sys/dev/ic/mtd8xxreg.h
206
bus_space_write_2(sc->sc_bust, sc->sc_bush, reg, val)
sys/dev/ic/mtd8xxreg.h
208
#define CSR_READ_4(reg) bus_space_read_4(sc->sc_bust, sc->sc_bush, reg)
sys/dev/ic/mtd8xxreg.h
209
#define CSR_WRITE_4(reg, val) \
sys/dev/ic/mtd8xxreg.h
210
bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val)
sys/dev/ic/mtd8xxreg.h
212
#define CSR_SETBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) | (val))
sys/dev/ic/mtd8xxreg.h
213
#define CSR_CLRBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) & ~(val))
sys/dev/ic/ncr53c9xvar.h
386
#define NCR_READ_REG(sc, reg) \
sys/dev/ic/ncr53c9xvar.h
387
(*(sc)->sc_glue->gl_read_reg)((sc), (reg))
sys/dev/ic/ncr53c9xvar.h
388
#define NCR_WRITE_REG(sc, reg, val) \
sys/dev/ic/ncr53c9xvar.h
389
(*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))
sys/dev/ic/nvme.c
305
u_int32_t reg;
sys/dev/ic/nvme.c
317
reg = nvme_read4(sc, NVME_VS);
sys/dev/ic/nvme.c
318
if (reg == 0xffffffff) {
sys/dev/ic/nvme.c
323
printf("NVMe %d.%d\n", NVME_VS_MJR(reg), NVME_VS_MNR(reg));
sys/dev/ic/osiopvar.h
64
#define osiop_read_1(sc, reg) \
sys/dev/ic/osiopvar.h
65
bus_space_read_1((sc)->sc_bst, (sc)->sc_reg, reg)
sys/dev/ic/osiopvar.h
66
#define osiop_write_1(sc, reg, val) \
sys/dev/ic/osiopvar.h
67
bus_space_write_1((sc)->sc_bst, (sc)->sc_reg, reg, val)
sys/dev/ic/osiopvar.h
69
#define osiop_read_4(sc, reg) \
sys/dev/ic/osiopvar.h
70
bus_space_read_4((sc)->sc_bst, (sc)->sc_reg, reg)
sys/dev/ic/osiopvar.h
71
#define osiop_write_4(sc, reg, val) \
sys/dev/ic/osiopvar.h
72
bus_space_write_4((sc)->sc_bst, (sc)->sc_reg, reg, val)
sys/dev/ic/pcdisplayvar.h
58
_pcdisplay_6845_read(struct pcdisplay_handle *ph, int reg)
sys/dev/ic/pcdisplayvar.h
60
bus_space_write_1(ph->ph_iot, ph->ph_ioh_6845, MC6845_INDEX, reg);
sys/dev/ic/pcdisplayvar.h
65
_pcdisplay_6845_write(struct pcdisplay_handle *ph, int reg, u_int8_t val)
sys/dev/ic/pcdisplayvar.h
67
bus_space_write_1(ph->ph_iot, ph->ph_ioh_6845, MC6845_INDEX, reg);
sys/dev/ic/pcdisplayvar.h
71
#define pcdisplay_6845_read(ph, reg) \
sys/dev/ic/pcdisplayvar.h
72
_pcdisplay_6845_read(ph, offsetof(struct reg_mc6845, reg))
sys/dev/ic/pcdisplayvar.h
73
#define pcdisplay_6845_write(ph, reg, val) \
sys/dev/ic/pcdisplayvar.h
74
_pcdisplay_6845_write(ph, offsetof(struct reg_mc6845, reg), val)
sys/dev/ic/pgt.c
1181
u_int32_t reg;
sys/dev/ic/pgt.c
1198
reg = pgt_read_4(sc, PGT_REG_CTRL_STAT);
sys/dev/ic/pgt.c
1199
if (reg & PGT_CTRL_STAT_SLEEPMODE)
sys/dev/ic/pgt.c
1202
reg = pgt_read_4(sc, PGT_REG_INT_STAT);
sys/dev/ic/pgt.c
1203
if (reg == 0)
sys/dev/ic/pgt.c
1206
pgt_write_4_flush(sc, PGT_REG_INT_ACK, reg);
sys/dev/ic/pgt.c
1207
if (reg & PGT_INT_STAT_INIT)
sys/dev/ic/pgt.c
1209
if (reg & PGT_INT_STAT_UPDATE) {
sys/dev/ic/pgt.c
1224
if (reg & PGT_INT_STAT_SLEEP && !(reg & PGT_INT_STAT_WAKEUP))
sys/dev/ic/pgt.c
1226
if (reg & PGT_INT_STAT_WAKEUP)
sys/dev/ic/pgt.c
1234
if (reg & ~PGT_INT_STAT_SOURCES && sc->sc_debug & SC_DEBUG_UNEXPECTED) {
sys/dev/ic/pgt.c
1237
reg & ~PGT_INT_STAT_SOURCES,
sys/dev/ic/pgt.c
1762
uint32_t reg;
sys/dev/ic/pgt.c
1772
reg = pgt_read_4(sc, PGT_REG_CTRL_STAT);
sys/dev/ic/pgt.c
1773
if (!(reg & PGT_CTRL_STAT_SLEEPMODE))
sys/dev/ic/pgt.c
1776
if (!(reg & PGT_CTRL_STAT_SLEEPMODE)) {
sys/dev/ic/pgt.c
284
int error, reg, dirreg, fwoff, ucodeoff, fwlen;
sys/dev/ic/pgt.c
315
reg = PGT_FIRMWARE_INTERNAL_OFFSET;
sys/dev/ic/pgt.c
317
pgt_write_4_flush(sc, PGT_REG_DIR_MEM_BASE, reg);
sys/dev/ic/pgt.c
329
reg += 4;
sys/dev/ic/pgt.c
336
reg += 4;
sys/dev/ic/pgt.c
343
reg = pgt_read_4(sc, PGT_REG_CTRL_STAT);
sys/dev/ic/pgt.c
344
reg &= ~(PGT_CTRL_STAT_RESET | PGT_CTRL_STAT_CLOCKRUN);
sys/dev/ic/pgt.c
345
reg |= PGT_CTRL_STAT_RAMBOOT;
sys/dev/ic/pgt.c
346
pgt_write_4_flush(sc, PGT_REG_CTRL_STAT, reg);
sys/dev/ic/pgt.c
350
reg |= PGT_CTRL_STAT_RESET;
sys/dev/ic/pgt.c
351
pgt_write_4(sc, PGT_REG_CTRL_STAT, reg);
sys/dev/ic/pgt.c
355
reg &= ~PGT_CTRL_STAT_RESET;
sys/dev/ic/pgt.c
356
pgt_write_4(sc, PGT_REG_CTRL_STAT, reg);
sys/dev/ic/pgt.c
640
uint32_t reg;
sys/dev/ic/pgt.c
642
reg = pgt_read_4(sc, PGT_REG_CTRL_STAT);
sys/dev/ic/pgt.c
643
reg &= ~(PGT_CTRL_STAT_RESET | PGT_CTRL_STAT_RAMBOOT);
sys/dev/ic/pgt.c
644
pgt_write_4(sc, PGT_REG_CTRL_STAT, reg);
sys/dev/ic/pgt.c
648
reg |= PGT_CTRL_STAT_RESET;
sys/dev/ic/pgt.c
649
pgt_write_4(sc, PGT_REG_CTRL_STAT, reg);
sys/dev/ic/pgt.c
653
reg &= ~PGT_CTRL_STAT_RESET;
sys/dev/ic/pgt.c
654
pgt_write_4(sc, PGT_REG_CTRL_STAT, reg);
sys/dev/ic/qcuart.c
62
#define HREAD4(sc, reg) \
sys/dev/ic/qcuart.c
63
(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
sys/dev/ic/qcuart.c
64
#define HWRITE4(sc, reg, val) \
sys/dev/ic/qcuart.c
65
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/ic/qcuart.c
66
#define HSET4(sc, reg, bits) \
sys/dev/ic/qcuart.c
67
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/ic/qcuart.c
68
#define HCLR4(sc, reg, bits) \
sys/dev/ic/qcuart.c
69
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/ic/r92creg.h
1812
uint16_t reg;
sys/dev/ic/re.c
2486
uint32_t reg;
sys/dev/ic/re.c
2513
reg = CSR_READ_4(sc, RE_DTCCR_LO);
sys/dev/ic/re.c
2514
if (!ISSET(reg, RE_DTCCR_CMD))
sys/dev/ic/re.c
2525
if (ISSET(reg, RE_DTCCR_CMD))
sys/dev/ic/re.c
363
re_gmii_readreg(struct device *self, int phy, int reg)
sys/dev/ic/re.c
374
if (reg == RL_GMEDIASTAT) {
sys/dev/ic/re.c
379
CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
sys/dev/ic/re.c
399
re_gmii_writereg(struct device *dev, int phy, int reg, int data)
sys/dev/ic/re.c
405
CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
sys/dev/ic/re.c
422
re_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/ic/re.c
432
rval = re_gmii_readreg(dev, phy, reg);
sys/dev/ic/re.c
442
switch(reg) {
sys/dev/ic/re.c
473
printf("%s: bad phy register %x\n", sc->sc_dev.dv_xname, reg);
sys/dev/ic/re.c
487
re_miibus_writereg(struct device *dev, int phy, int reg, int data)
sys/dev/ic/re.c
496
re_gmii_writereg(dev, phy, reg, data);
sys/dev/ic/re.c
506
switch(reg) {
sys/dev/ic/re.c
530
printf("%s: bad phy register %x\n", sc->sc_dev.dv_xname, reg);
sys/dev/ic/rt2560.c
144
uint32_t reg;
sys/dev/ic/rt2560.c
151
uint8_t reg;
sys/dev/ic/rt2560.c
2051
rt2560_bbp_write(struct rt2560_softc *sc, uint8_t reg, uint8_t val)
sys/dev/ic/rt2560.c
2066
tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val;
sys/dev/ic/rt2560.c
2069
DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val));
sys/dev/ic/rt2560.c
2073
rt2560_bbp_read(struct rt2560_softc *sc, uint8_t reg)
sys/dev/ic/rt2560.c
2088
val = RT2560_BBP_BUSY | reg << 8;
sys/dev/ic/rt2560.c
2103
rt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val)
sys/dev/ic/rt2560.c
2119
(reg & 0x3);
sys/dev/ic/rt2560.c
2123
sc->rf_regs[reg] = val;
sys/dev/ic/rt2560.c
2125
DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff));
sys/dev/ic/rt2560.c
2519
sc->bbp_prom[i].reg = val >> 8;
sys/dev/ic/rt2560.c
2549
rt2560_bbp_write(sc, rt2560_def_bbp[i].reg,
sys/dev/ic/rt2560.c
2555
if (sc->bbp_prom[i].reg == 0xff)
sys/dev/ic/rt2560.c
2557
rt2560_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
sys/dev/ic/rt2560.c
2605
RAL_WRITE(sc, rt2560_def_mac[i].reg, rt2560_def_mac[i].val);
sys/dev/ic/rt2560reg.h
303
#define RAL_READ(sc, reg) \
sys/dev/ic/rt2560reg.h
304
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
sys/dev/ic/rt2560reg.h
306
#define RAL_WRITE(sc, reg, val) \
sys/dev/ic/rt2560reg.h
307
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/ic/rt2560var.h
137
uint8_t reg;
sys/dev/ic/rt2661.c
166
uint32_t reg;
sys/dev/ic/rt2661.c
173
uint8_t reg;
sys/dev/ic/rt2661.c
2045
rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val)
sys/dev/ic/rt2661.c
2060
tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;
sys/dev/ic/rt2661.c
2063
DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val));
sys/dev/ic/rt2661.c
2067
rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg)
sys/dev/ic/rt2661.c
2082
val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8;
sys/dev/ic/rt2661.c
2097
rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)
sys/dev/ic/rt2661.c
2113
(reg & 3);
sys/dev/ic/rt2661.c
2117
sc->rf_regs[reg] = val;
sys/dev/ic/rt2661.c
2119
DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff));
sys/dev/ic/rt2661.c
2502
sc->bbp_prom[i].reg = val >> 8;
sys/dev/ic/rt2661.c
2504
DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg,
sys/dev/ic/rt2661.c
2528
rt2661_bbp_write(sc, rt2661_def_bbp[i].reg,
sys/dev/ic/rt2661.c
2534
if (sc->bbp_prom[i].reg == 0)
sys/dev/ic/rt2661.c
2536
rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
sys/dev/ic/rt2661.c
2613
RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
sys/dev/ic/rt2661reg.h
329
RAL_READ(struct rt2661_softc *sc, bus_size_t reg)
sys/dev/ic/rt2661reg.h
332
return bus_space_read_4(sc->sc_st, sc->sc_sh, reg);
sys/dev/ic/rt2661reg.h
345
RAL_WRITE(struct rt2661_softc *sc, bus_size_t reg, uint32_t val)
sys/dev/ic/rt2661reg.h
348
bus_space_write_4(sc->sc_st, sc->sc_sh, reg, val);
sys/dev/ic/rt2661reg.h
352
RAL_WRITE_1(struct rt2661_softc *sc, bus_size_t reg, uint8_t val)
sys/dev/ic/rt2661reg.h
355
bus_space_write_1(sc->sc_st, sc->sc_sh, reg, val);
sys/dev/ic/rt2661reg.h
367
#define RAL_RW_BARRIER_1(sc, reg) \
sys/dev/ic/rt2661reg.h
368
bus_space_barrier((sc)->sc_st, (sc)->sc_sh, (reg), 1, \
sys/dev/ic/rt2661var.h
147
uint8_t reg;
sys/dev/ic/rt2860.c
1011
uint16_t reg;
sys/dev/ic/rt2860.c
1039
reg = RT3070_EFUSE_DATA3 - (addr & 0xc);
sys/dev/ic/rt2860.c
1040
tmp = RAL_READ(sc, reg);
sys/dev/ic/rt2860.c
1050
uint16_t reg;
sys/dev/ic/rt2860.c
1078
reg = RT3290_EFUSE_DATA3 + (addr & 0xc);
sys/dev/ic/rt2860.c
1079
tmp = RAL_READ(sc, reg);
sys/dev/ic/rt2860.c
167
uint32_t reg;
sys/dev/ic/rt2860.c
174
uint8_t reg;
sys/dev/ic/rt2860.c
1882
rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
sys/dev/ic/rt2860.c
1898
RT2860_BBP_CSR_KICK | reg << 8 | val);
sys/dev/ic/rt2860.c
1906
rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg)
sys/dev/ic/rt2860.c
1923
RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8);
sys/dev/ic/rt2860.c
1945
rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val)
sys/dev/ic/rt2860.c
1962
(val & 0x3fffff) << 2 | (reg & 3);
sys/dev/ic/rt2860.c
1967
rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg)
sys/dev/ic/rt2860.c
198
uint8_t reg;
sys/dev/ic/rt2860.c
1982
tmp = RT3070_RF_KICK | reg << 8;
sys/dev/ic/rt2860.c
2000
rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
sys/dev/ic/rt2860.c
2015
tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;
sys/dev/ic/rt2860.c
218
uint32_t tmp, reg;
sys/dev/ic/rt2860.c
224
reg = RT2860_PCI_CFG;
sys/dev/ic/rt2860.c
226
reg = RT2860_ASIC_VER_ID;
sys/dev/ic/rt2860.c
230
tmp = RAL_READ(sc, reg);
sys/dev/ic/rt2860.c
2483
rt3090_rf_write(sc, rt3572_def_rf[i].reg,
sys/dev/ic/rt2860.c
2488
rt3090_rf_write(sc, rt3090_def_rf[i].reg,
sys/dev/ic/rt2860.c
2585
rt3090_rf_write(sc, rt5392_def_rf[i].reg,
sys/dev/ic/rt2860.c
2590
rt3090_rf_write(sc, rt3290_def_rf[i].reg,
sys/dev/ic/rt2860.c
2595
rt3090_rf_write(sc, rt5390_def_rf[i].reg,
sys/dev/ic/rt2860.c
2842
if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff)
sys/dev/ic/rt2860.c
2844
rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);
sys/dev/ic/rt2860.c
3218
sc->bbp[i].reg = val >> 8;
sys/dev/ic/rt2860.c
3219
DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val));
sys/dev/ic/rt2860.c
3226
sc->rf[i].reg = val >> 8;
sys/dev/ic/rt2860.c
3227
DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg,
sys/dev/ic/rt2860.c
3358
uint32_t reg;
sys/dev/ic/rt2860.c
3361
reg = val;
sys/dev/ic/rt2860.c
3363
reg |= (uint32_t)val << 16;
sys/dev/ic/rt2860.c
3365
sc->txpow20mhz[ridx] = reg;
sys/dev/ic/rt2860.c
3366
sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
sys/dev/ic/rt2860.c
3367
sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
sys/dev/ic/rt2860.c
3504
rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg,
sys/dev/ic/rt2860.c
3542
rt2860_mcu_bbp_write(sc, rt3290_def_bbp[i].reg,
sys/dev/ic/rt2860.c
3547
rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg,
sys/dev/ic/rt2860.c
3756
RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val);
sys/dev/ic/rt2860.c
3848
if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)
sys/dev/ic/rt2860.c
3850
rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
sys/dev/ic/rt2860reg.h
1099
#define RAL_READ(sc, reg) \
sys/dev/ic/rt2860reg.h
1100
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
sys/dev/ic/rt2860reg.h
1102
#define RAL_WRITE(sc, reg, val) \
sys/dev/ic/rt2860reg.h
1103
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/ic/rt2860var.h
175
uint8_t reg;
sys/dev/ic/rtl80x9.c
108
u_int8_t reg;
sys/dev/ic/rtl80x9.c
118
reg = NIC_GET(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG2);
sys/dev/ic/rtl80x9.c
119
reg &= ~(RTL3_CONFIG2_PL1|RTL3_CONFIG2_PL0);
sys/dev/ic/rtl80x9.c
134
reg |= RTL3_CONFIG2_PL1|RTL3_CONFIG2_PL0;
sys/dev/ic/rtl80x9.c
137
NIC_PUT(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG2, reg);
sys/dev/ic/rtl80x9.c
140
reg = NIC_GET(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG3);
sys/dev/ic/rtl80x9.c
142
reg |= RTL3_CONFIG3_FUDUP;
sys/dev/ic/rtl80x9.c
144
reg &= ~RTL3_CONFIG3_FUDUP;
sys/dev/ic/rtl80x9.c
145
NIC_PUT(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG3, reg);
sys/dev/ic/rtl81x9.c
1240
rl_miibus_readreg(struct device *self, int phy, int reg)
sys/dev/ic/rtl81x9.c
1254
switch (reg) {
sys/dev/ic/rtl81x9.c
1283
frame.mii_regaddr = reg;
sys/dev/ic/rtl81x9.c
1290
rl_miibus_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/rtl81x9.c
1300
switch (reg) {
sys/dev/ic/rtl81x9.c
1326
frame.mii_regaddr = reg;
sys/dev/ic/rtsx.c
68
#define READ4(sc, reg) \
sys/dev/ic/rtsx.c
69
(bus_space_read_4((sc)->iot, (sc)->ioh, (reg)))
sys/dev/ic/rtsx.c
70
#define WRITE4(sc, reg, val) \
sys/dev/ic/rtsx.c
71
bus_space_write_4((sc)->iot, (sc)->ioh, (reg), (val))
sys/dev/ic/rtsx.c
73
#define RTSX_READ(sc, reg, val) \
sys/dev/ic/rtsx.c
731
u_int32_t reg;
sys/dev/ic/rtsx.c
737
reg = READ4(sc, RTSX_HAIMR);
sys/dev/ic/rtsx.c
738
if (!(reg & RTSX_HAIMR_BUSY))
sys/dev/ic/rtsx.c
742
*val = (reg & 0xff);
sys/dev/ic/rtsx.c
75
int err = rtsx_read((sc), (reg), (val)); \
sys/dev/ic/rtsx.c
750
u_int32_t reg;
sys/dev/ic/rtsx.c
758
reg = READ4(sc, RTSX_HAIMR);
sys/dev/ic/rtsx.c
759
if (!(reg & RTSX_HAIMR_BUSY)) {
sys/dev/ic/rtsx.c
760
if (val != (reg & 0xff))
sys/dev/ic/rtsx.c
80
#define RTSX_WRITE(sc, reg, val) \
sys/dev/ic/rtsx.c
82
int err = rtsx_write((sc), (reg), 0xff, (val)); \
sys/dev/ic/rtsx.c
87
#define RTSX_CLR(sc, reg, bits) \
sys/dev/ic/rtsx.c
89
int err = rtsx_write((sc), (reg), (bits), 0); \
sys/dev/ic/rtsx.c
890
rtsx_hostcmd(u_int32_t *cmdbuf, int *n, u_int8_t cmd, u_int16_t reg,
sys/dev/ic/rtsx.c
896
((u_int32_t)(reg & 0x3fff) << 16) |
sys/dev/ic/rtsx.c
905
u_int16_t reg;
sys/dev/ic/rtsx.c
910
for (reg = 0xFDA0; reg < 0xFDAE; reg++)
sys/dev/ic/rtsx.c
911
(void)rtsx_read(sc, reg, &sc->regs[i++]);
sys/dev/ic/rtsx.c
912
for (reg = 0xFD52; reg < 0xFD69; reg++)
sys/dev/ic/rtsx.c
913
(void)rtsx_read(sc, reg, &sc->regs[i++]);
sys/dev/ic/rtsx.c
914
for (reg = 0xFE20; reg < 0xFE34; reg++)
sys/dev/ic/rtsx.c
915
(void)rtsx_read(sc, reg, &sc->regs[i++]);
sys/dev/ic/rtsx.c
932
u_int16_t reg;
sys/dev/ic/rtsx.c
94
#define RTSX_SET(sc, reg, bits) \
sys/dev/ic/rtsx.c
945
for (reg = 0xFDA0; reg < 0xFDAE; reg++)
sys/dev/ic/rtsx.c
946
(void)rtsx_write(sc, reg, 0xff, sc->regs[i++]);
sys/dev/ic/rtsx.c
947
for (reg = 0xFD52; reg < 0xFD69; reg++)
sys/dev/ic/rtsx.c
948
(void)rtsx_write(sc, reg, 0xff, sc->regs[i++]);
sys/dev/ic/rtsx.c
949
for (reg = 0xFE20; reg < 0xFE34; reg++)
sys/dev/ic/rtsx.c
950
(void)rtsx_write(sc, reg, 0xff, sc->regs[i++]);
sys/dev/ic/rtsx.c
96
int err = rtsx_write((sc), (reg), (bits), 0xff);\
sys/dev/ic/rtw.c
4139
#define RTW_BBP_WRITE_OR_RETURN(reg, val) \
sys/dev/ic/rtw.c
4140
if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \
sys/dev/ic/rtw.c
4736
u_int32_t mask, reg;
sys/dev/ic/rtw.c
4744
reg = RTW8180_PHYCFG_HST;
sys/dev/ic/rtw.c
4745
RTW_WRITE(regs, RTW8180_PHYCFG, reg);
sys/dev/ic/rtw.c
4759
reg |= RTW8180_PHYCFG_HST_DATA;
sys/dev/ic/rtw.c
4761
reg &= ~RTW8180_PHYCFG_HST_DATA;
sys/dev/ic/rtw.c
4763
reg |= RTW8180_PHYCFG_HST_CLK;
sys/dev/ic/rtw.c
4764
RTW_WRITE(regs, RTW8180_PHYCFG, reg);
sys/dev/ic/rtw.c
4769
reg &= ~RTW8180_PHYCFG_HST_CLK;
sys/dev/ic/rtw.c
4770
RTW_WRITE(regs, RTW8180_PHYCFG, reg);
sys/dev/ic/rtw.c
4779
reg |= RTW8180_PHYCFG_HST_EN;
sys/dev/ic/rtw.c
4780
KASSERT((reg & RTW8180_PHYCFG_HST_CLK) == 0);
sys/dev/ic/rtw.c
4781
RTW_WRITE(regs, RTW8180_PHYCFG, reg);
sys/dev/ic/rtw.c
4824
reg |= RTW8180_PHYCFG_HST_DATA;
sys/dev/ic/rtw.c
4826
reg &= ~RTW8180_PHYCFG_HST_DATA;
sys/dev/ic/rtw.c
4828
reg |= RTW8180_PHYCFG_HST_CLK;
sys/dev/ic/rtw.c
4829
RTW_WRITE(regs, RTW8180_PHYCFG, reg);
sys/dev/ic/rtw.c
4834
reg &= ~RTW8180_PHYCFG_HST_CLK;
sys/dev/ic/rtw.c
4835
RTW_WRITE(regs, RTW8180_PHYCFG, reg);
sys/dev/ic/rtw.c
4853
rtw_rf_macbangbits(struct rtw_regs *regs, u_int32_t reg)
sys/dev/ic/rtw.c
4857
RTW_DPRINTF(RTW_DEBUG_PHY, ("%s: %#08x\n", __func__, reg));
sys/dev/ic/rtw.c
4859
RTW_WRITE(regs, RTW8180_PHYCFG, RTW8180_PHYCFG_MAC_POLL | reg);
sys/dev/ic/rtw.c
4989
u_int32_t reg;
sys/dev/ic/rtw.c
4996
reg = rtw_grf5101_mac_crypt(addr, val);
sys/dev/ic/rtw.c
4999
reg = rtw_maxim_swizzle(addr, val);
sys/dev/ic/rtw.c
5008
reg = LSHIFT(addr, RTW8180_PHYCFG_MAC_PHILIPS_ADDR_MASK) |
sys/dev/ic/rtw.c
5016
reg |= RTW8180_PHYCFG_MAC_RFTYPE_RFMD;
sys/dev/ic/rtw.c
5019
reg |= RTW8180_PHYCFG_MAC_RFTYPE_INTERSIL;
sys/dev/ic/rtw.c
5022
reg |= RTW8180_PHYCFG_MAC_RFTYPE_PHILIPS;
sys/dev/ic/rtw.c
5029
return rtw_rf_macbangbits(&sc->sc_regs, reg);
sys/dev/ic/rtwn.c
1064
uint32_t reg;
sys/dev/ic/rtwn.c
1118
reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
sys/dev/ic/rtwn.c
1119
reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
sys/dev/ic/rtwn.c
1120
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
sys/dev/ic/rtwn.c
1123
reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
sys/dev/ic/rtwn.c
1124
reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
sys/dev/ic/rtwn.c
1125
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
sys/dev/ic/rtwn.c
1144
reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
sys/dev/ic/rtwn.c
1145
reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
sys/dev/ic/rtwn.c
1146
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
sys/dev/ic/rtwn.c
1149
reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
sys/dev/ic/rtwn.c
1150
reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
sys/dev/ic/rtwn.c
1151
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
sys/dev/ic/rtwn.c
1246
uint32_t reg;
sys/dev/ic/rtwn.c
1248
reg = rtwn_read_4(sc, R92C_RRSR);
sys/dev/ic/rtwn.c
1250
reg |= R92C_RRSR_SHORT;
sys/dev/ic/rtwn.c
1252
reg &= ~R92C_RRSR_SHORT;
sys/dev/ic/rtwn.c
1253
rtwn_write_4(sc, R92C_RRSR, reg);
sys/dev/ic/rtwn.c
1259
uint32_t reg;
sys/dev/ic/rtwn.c
1261
reg = rtwn_read_4(sc, R92C_WMAC_TRXPTCL_CTL);
sys/dev/ic/rtwn.c
1263
reg |= R92C_WMAC_TRXPTCL_CTL_SHORT;
sys/dev/ic/rtwn.c
1265
reg &= ~R92C_WMAC_TRXPTCL_CTL_SHORT;
sys/dev/ic/rtwn.c
1266
rtwn_write_4(sc, R92C_WMAC_TRXPTCL_CTL, reg);
sys/dev/ic/rtwn.c
1691
uint16_t reg;
sys/dev/ic/rtwn.c
1699
reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN);
sys/dev/ic/rtwn.c
1700
if (!(reg & R92C_SYS_FUNC_EN_CPUEN))
sys/dev/ic/rtwn.c
1705
rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
sys/dev/ic/rtwn.c
1712
tsleep_nsec(®, 0, "rtwnrst", SEC_TO_NSEC(1));
sys/dev/ic/rtwn.c
1756
uint32_t reg;
sys/dev/ic/rtwn.c
1840
reg = rtwn_read_4(sc, R92C_MCUFWDL);
sys/dev/ic/rtwn.c
1841
reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY;
sys/dev/ic/rtwn.c
1842
rtwn_write_4(sc, R92C_MCUFWDL, reg);
sys/dev/ic/rtwn.c
1844
reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN);
sys/dev/ic/rtwn.c
1846
reg & ~R92C_SYS_FUNC_EN_CPUEN);
sys/dev/ic/rtwn.c
1848
reg | R92C_SYS_FUNC_EN_CPUEN);
sys/dev/ic/rtwn.c
1875
uint32_t reg, type;
sys/dev/ic/rtwn.c
1899
reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
sys/dev/ic/rtwn.c
1900
type = (reg >> off) & 0x10;
sys/dev/ic/rtwn.c
1903
reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
sys/dev/ic/rtwn.c
1904
reg |= 0x100000;
sys/dev/ic/rtwn.c
1905
rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
sys/dev/ic/rtwn.c
1908
reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
sys/dev/ic/rtwn.c
1909
reg |= 0x10;
sys/dev/ic/rtwn.c
1910
rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
sys/dev/ic/rtwn.c
1913
reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
sys/dev/ic/rtwn.c
1914
reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH;
sys/dev/ic/rtwn.c
1915
rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
sys/dev/ic/rtwn.c
1917
reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
sys/dev/ic/rtwn.c
1918
reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH;
sys/dev/ic/rtwn.c
1919
rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
sys/dev/ic/rtwn.c
1951
reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
sys/dev/ic/rtwn.c
1952
reg &= ~(0x10 << off) | (type << off);
sys/dev/ic/rtwn.c
1953
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg);
sys/dev/ic/rtwn.c
1992
uint8_t reg;
sys/dev/ic/rtwn.c
2004
reg = rtwn_read_1(sc, 0x16);
sys/dev/ic/rtwn.c
2005
reg = (reg & ~0xf0) | 0x90;
sys/dev/ic/rtwn.c
2006
rtwn_write_1(sc, 0x16, reg);
sys/dev/ic/rtwn.c
2087
uint32_t reg;
sys/dev/ic/rtwn.c
2091
reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
sys/dev/ic/rtwn.c
2092
reg = RW(reg, R92C_TXAGC_A_CCK1, power[RTWN_POWER_CCK1]);
sys/dev/ic/rtwn.c
2093
rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
sys/dev/ic/rtwn.c
2094
reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
sys/dev/ic/rtwn.c
2095
reg = RW(reg, R92C_TXAGC_A_CCK2, power[RTWN_POWER_CCK2]);
sys/dev/ic/rtwn.c
2096
reg = RW(reg, R92C_TXAGC_A_CCK55, power[RTWN_POWER_CCK55]);
sys/dev/ic/rtwn.c
2097
reg = RW(reg, R92C_TXAGC_A_CCK11, power[RTWN_POWER_CCK11]);
sys/dev/ic/rtwn.c
2098
rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
sys/dev/ic/rtwn.c
2100
reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
sys/dev/ic/rtwn.c
2101
reg = RW(reg, R92C_TXAGC_B_CCK1, power[RTWN_POWER_CCK1]);
sys/dev/ic/rtwn.c
2102
reg = RW(reg, R92C_TXAGC_B_CCK2, power[RTWN_POWER_CCK2]);
sys/dev/ic/rtwn.c
2103
reg = RW(reg, R92C_TXAGC_B_CCK55, power[RTWN_POWER_CCK55]);
sys/dev/ic/rtwn.c
2104
rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
sys/dev/ic/rtwn.c
2105
reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
sys/dev/ic/rtwn.c
2106
reg = RW(reg, R92C_TXAGC_B_CCK11, power[RTWN_POWER_CCK11]);
sys/dev/ic/rtwn.c
2107
rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
sys/dev/ic/rtwn.c
2413
uint32_t reg;
sys/dev/ic/rtwn.c
2426
reg = rtwn_read_2(sc, R92C_WMAC_TRXPTCL_CTL);
sys/dev/ic/rtwn.c
2427
reg &= ~R92C_WMAC_TRXPTCL_CTL_BW_MASK;
sys/dev/ic/rtwn.c
2428
reg |= R92C_WMAC_TRXPTCL_CTL_BW_40;
sys/dev/ic/rtwn.c
2429
rtwn_write_2(sc, R92C_WMAC_TRXPTCL_CTL, reg);
sys/dev/ic/rtwn.c
2437
reg = rtwn_read_1(sc, R92C_RRSR + 2);
sys/dev/ic/rtwn.c
2438
reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5;
sys/dev/ic/rtwn.c
2439
rtwn_write_1(sc, R92C_RRSR + 2, reg);
sys/dev/ic/rtwn.c
2447
reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM);
sys/dev/ic/rtwn.c
2448
reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4;
sys/dev/ic/rtwn.c
2449
rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);
sys/dev/ic/rtwn.c
2451
reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF);
sys/dev/ic/rtwn.c
2452
reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10;
sys/dev/ic/rtwn.c
2453
rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);
sys/dev/ic/rtwn.c
2461
reg = rtwn_bb_read(sc, 0x818);
sys/dev/ic/rtwn.c
2462
reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26;
sys/dev/ic/rtwn.c
2463
rtwn_bb_write(sc, 0x818, reg);
sys/dev/ic/rtwn.c
2472
reg = rtwn_read_2(sc, R92C_WMAC_TRXPTCL_CTL);
sys/dev/ic/rtwn.c
2473
reg &= ~R92C_WMAC_TRXPTCL_CTL_BW_MASK;
sys/dev/ic/rtwn.c
2474
rtwn_write_2(sc, R92C_WMAC_TRXPTCL_CTL, reg);
sys/dev/ic/rtwn.c
2494
reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);
sys/dev/ic/rtwn.c
2495
reg = (reg & ~0x00000700) | 0x7 << 8;
sys/dev/ic/rtwn.c
2496
rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
sys/dev/ic/rtwn.c
2497
reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);
sys/dev/ic/rtwn.c
2498
reg = (reg & ~0x00007000) | 0x5 << 12;
sys/dev/ic/rtwn.c
2499
rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
sys/dev/ic/rtwn.c
2502
reg = rtwn_bb_read(sc, R92C_OFDM0_TX_PSDO_NOISE_WEIGHT);
sys/dev/ic/rtwn.c
2503
reg &= ~0xc0000000;
sys/dev/ic/rtwn.c
2504
rtwn_bb_write(sc, R92C_OFDM0_TX_PSDO_NOISE_WEIGHT, reg);
sys/dev/ic/rtwn.c
2508
reg = rtwn_bb_read(sc,
sys/dev/ic/rtwn.c
2510
reg |= 0x30000000;
sys/dev/ic/rtwn.c
2512
R92C_OFDM0_TX_PSDO_NOISE_WEIGHT, reg);
sys/dev/ic/rtwn.c
2521
reg = rtwn_bb_read(sc, R88F_RX_DFIR);
sys/dev/ic/rtwn.c
2522
reg = (reg & ~0x00f00000) | 0x3 << 15;
sys/dev/ic/rtwn.c
2523
rtwn_bb_write(sc, R88F_RX_DFIR, reg);
sys/dev/ic/rtwn.c
2665
uint32_t hssi_param1, reg;
sys/dev/ic/rtwn.c
2858
reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
sys/dev/ic/rtwn.c
2859
reg &= ~0xff;
sys/dev/ic/rtwn.c
2860
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg | 0x50);
sys/dev/ic/rtwn.c
2861
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg | xa_agc);
sys/dev/ic/rtwn.c
2863
reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
sys/dev/ic/rtwn.c
2864
reg &= ~0xff;
sys/dev/ic/rtwn.c
2865
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg | 0x50);
sys/dev/ic/rtwn.c
2866
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg | xb_agc);
sys/dev/ic/rtwn.c
2906
uint32_t reg, val, x;
sys/dev/ic/rtwn.c
2912
reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain));
sys/dev/ic/rtwn.c
2913
val = ((reg >> 22) & 0x3ff);
sys/dev/ic/rtwn.c
2917
reg &= ~0x3ff;
sys/dev/ic/rtwn.c
2918
reg |= (((x * val) >> 8) & 0x3ff);
sys/dev/ic/rtwn.c
2919
rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg);
sys/dev/ic/rtwn.c
2921
reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD);
sys/dev/ic/rtwn.c
2923
reg |= 0x80000000;
sys/dev/ic/rtwn.c
2925
reg &= ~0x80000000;
sys/dev/ic/rtwn.c
2926
rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg);
sys/dev/ic/rtwn.c
2932
reg = rtwn_bb_read(sc, R92C_OFDM0_TXAFE(chain));
sys/dev/ic/rtwn.c
2933
reg &= ~0xf0000000;
sys/dev/ic/rtwn.c
2934
reg |= ((tx_c & 0x3c0) << 22);
sys/dev/ic/rtwn.c
2935
rtwn_bb_write(sc, R92C_OFDM0_TXAFE(chain), reg);
sys/dev/ic/rtwn.c
2937
reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain));
sys/dev/ic/rtwn.c
2938
reg &= ~0x003f0000;
sys/dev/ic/rtwn.c
2939
reg |= ((tx_c & 0x3f) << 16);
sys/dev/ic/rtwn.c
2940
rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg);
sys/dev/ic/rtwn.c
2942
reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD);
sys/dev/ic/rtwn.c
2944
reg |= 0x20000000;
sys/dev/ic/rtwn.c
2946
reg &= ~0x20000000;
sys/dev/ic/rtwn.c
2947
rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg);
sys/dev/ic/rtwn.c
2952
reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQIMBALANCE(chain));
sys/dev/ic/rtwn.c
2953
reg &= ~0x3ff;
sys/dev/ic/rtwn.c
2954
reg |= (rx[0] & 0x3ff);
sys/dev/ic/rtwn.c
2955
rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg);
sys/dev/ic/rtwn.c
2957
reg &= ~0xfc00;
sys/dev/ic/rtwn.c
2958
reg |= ((rx[1] & 0x03f) << 10);
sys/dev/ic/rtwn.c
2959
rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg);
sys/dev/ic/rtwn.c
2962
reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQEXTANTA);
sys/dev/ic/rtwn.c
2963
reg &= ~0xf0000000;
sys/dev/ic/rtwn.c
2964
reg |= ((rx[1] & 0x3c0) << 22);
sys/dev/ic/rtwn.c
2965
rtwn_bb_write(sc, R92C_OFDM0_RXIQEXTANTA, reg);
sys/dev/ic/rtwn.c
2967
reg = rtwn_bb_read(sc, R92C_OFDM0_AGCRSSITABLE);
sys/dev/ic/rtwn.c
2968
reg &= ~0xf000;
sys/dev/ic/rtwn.c
2969
reg |= ((rx[1] & 0x3c0) << 6);
sys/dev/ic/rtwn.c
2970
rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, reg);
sys/dev/ic/rtwn.c
3165
uint32_t reg;
sys/dev/ic/rtwn.c
3211
reg = rtwn_read_4(sc, R92C_RRSR);
sys/dev/ic/rtwn.c
3213
reg = RW(reg, R92C_RRSR_RATE_BITMAP,
sys/dev/ic/rtwn.c
3216
reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL);
sys/dev/ic/rtwn.c
3218
rtwn_write_4(sc, R92C_RRSR, reg);
sys/dev/ic/rtwn.c
3290
reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);
sys/dev/ic/rtwn.c
3291
reg |= R92C_RFMOD_CCK_EN;
sys/dev/ic/rtwn.c
3292
rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
sys/dev/ic/rtwn.c
3293
reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);
sys/dev/ic/rtwn.c
3294
reg |= R92C_RFMOD_OFDM_EN;
sys/dev/ic/rtwn.c
3295
rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
sys/dev/ic/rtwn.c
466
uint32_t reg[R92C_MAX_CHAINS], val;
sys/dev/ic/rtwn.c
468
reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
sys/dev/ic/rtwn.c
470
reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
sys/dev/ic/rtwn.c
473
reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);
sys/dev/ic/rtwn.c
477
RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
sys/dev/ic/rtwn.c
483
reg[0] | R92C_HSSI_PARAM2_READ_EDGE);
sys/dev/ic/rtwn.c
506
uint32_t reg;
sys/dev/ic/rtwn.c
509
reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);
sys/dev/ic/rtwn.c
510
reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr);
sys/dev/ic/rtwn.c
511
reg &= ~R92C_EFUSE_CTRL_VALID;
sys/dev/ic/rtwn.c
512
rtwn_write_4(sc, R92C_EFUSE_CTRL, reg);
sys/dev/ic/rtwn.c
515
reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);
sys/dev/ic/rtwn.c
516
if (reg & R92C_EFUSE_CTRL_VALID)
sys/dev/ic/rtwn.c
517
return (MS(reg, R92C_EFUSE_CTRL_DATA));
sys/dev/ic/rtwn.c
530
uint32_t reg;
sys/dev/ic/rtwn.c
540
reg = rtwn_read_4(sc, R92C_EFUSE_TEST);
sys/dev/ic/rtwn.c
541
reg = RW(reg, R92C_EFUSE_TEST_SEL, 0);
sys/dev/ic/rtwn.c
542
rtwn_write_4(sc, R92C_EFUSE_TEST, reg);
sys/dev/ic/rtwn.c
548
reg = rtwn_efuse_read_1(sc, addr);
sys/dev/ic/rtwn.c
549
if (reg == 0xff)
sys/dev/ic/rtwn.c
555
(reg & 0x1f) == 0x0f) {
sys/dev/ic/rtwn.c
556
tmp = (reg & 0xe0) >> 5;
sys/dev/ic/rtwn.c
557
reg = rtwn_efuse_read_1(sc, addr);
sys/dev/ic/rtwn.c
559
if ((reg & 0x0f) != 0x0f)
sys/dev/ic/rtwn.c
560
off = ((reg & 0xf0) >> 1) | tmp;
sys/dev/ic/rtwn.c
564
off = reg >> 4;
sys/dev/ic/rtwn.c
565
msk = reg & 0xf;
sys/dev/ic/rtwn.c
591
uint16_t reg;
sys/dev/ic/rtwn.c
594
reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL);
sys/dev/ic/rtwn.c
595
if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {
sys/dev/ic/rtwn.c
597
reg | R92C_SYS_ISO_CTRL_PWC_EV12V);
sys/dev/ic/rtwn.c
600
reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN);
sys/dev/ic/rtwn.c
601
if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {
sys/dev/ic/rtwn.c
603
reg | R92C_SYS_FUNC_EN_ELDR);
sys/dev/ic/rtwn.c
605
reg = rtwn_read_2(sc, R92C_SYS_CLKR);
sys/dev/ic/rtwn.c
606
if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=
sys/dev/ic/rtwn.c
609
reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);
sys/dev/ic/rtwn.c
616
uint32_t reg;
sys/dev/ic/rtwn.c
623
reg = rtwn_read_4(sc, R92C_SYS_CFG);
sys/dev/ic/rtwn.c
624
if (reg & R92C_SYS_CFG_TRP_VAUX_EN)
sys/dev/ic/rtwn.c
629
if (reg & R92C_SYS_CFG_TYPE_92C) {
sys/dev/ic/rtwn.c
639
if (reg & R92C_SYS_CFG_VENDOR_UMC) {
sys/dev/ic/rtwn.c
641
if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0)
sys/dev/ic/rtwn.c
649
if ((reg & 0xf000) == 0)
sys/dev/ic/rtwn.c
902
u_int32_t reg;
sys/dev/ic/rtwn.c
906
reg = rtwn_read_4(sc, R92C_RRSR);
sys/dev/ic/rtwn.c
907
reg = RW(reg, R92C_RRSR_RATE_BITMAP, rates);
sys/dev/ic/rtwn.c
908
rtwn_write_4(sc, R92C_RRSR, reg);
sys/dev/ic/rtwn.c
948
uint8_t reg;
sys/dev/ic/rtwn.c
954
reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0;
sys/dev/ic/rtwn.c
956
reg |= R92C_LEDCFG2_DIS;
sys/dev/ic/rtwn.c
958
reg |= R92C_LEDCFG2_EN;
sys/dev/ic/rtwn.c
959
rtwn_write_1(sc, R92C_LEDCFG2, reg);
sys/dev/ic/rtwn.c
963
reg = rtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON;
sys/dev/ic/rtwn.c
964
rtwn_write_1(sc, R92C_LEDCFG1, reg |
sys/dev/ic/rtwn.c
967
reg = rtwn_read_1(sc, R92C_LEDCFG1) &
sys/dev/ic/rtwn.c
969
rtwn_write_1(sc, R92C_LEDCFG1, reg);
sys/dev/ic/rtwn.c
972
reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0;
sys/dev/ic/rtwn.c
973
rtwn_write_1(sc, R92C_LEDCFG2, reg | R92C_LEDCFG2_EN);
sys/dev/ic/rtwn.c
975
reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0x90;
sys/dev/ic/rtwn.c
977
reg | R92C_LEDCFG0_DIS);
sys/dev/ic/rtwn.c
983
reg = rtwn_read_1(sc, R92C_LEDCFG0) & 0x70;
sys/dev/ic/rtwn.c
985
reg |= R92C_LEDCFG0_DIS;
sys/dev/ic/rtwn.c
986
rtwn_write_1(sc, R92C_LEDCFG0, reg);
sys/dev/ic/rtwreg.h
1135
#define RTW_ISSET(regs, reg, mask) \
sys/dev/ic/rtwreg.h
1136
(RTW_READ((regs), (reg)) & (mask))
sys/dev/ic/rtwreg.h
1138
#define RTW_CLR(regs, reg, mask) \
sys/dev/ic/rtwreg.h
1139
RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask))
sys/dev/ic/rtwreg.h
71
#define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))
sys/dev/ic/s3_617.h
100
#define SET_FIELD(reg, field) ((reg & ~(field##_MASK)) | field)
sys/dev/ic/s3_617.h
101
#define GET_FIELD(reg, field) (reg & ~(field##_MASK))
sys/dev/ic/smc83c170.c
1061
u_int32_t reg;
sys/dev/ic/smc83c170.c
1085
reg = bus_space_read_4(st, sh, EPIC_GENCTL);
sys/dev/ic/smc83c170.c
1086
bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA);
sys/dev/ic/smc83c170.c
1119
u_int16_t reg;
sys/dev/ic/smc83c170.c
1139
reg = EECTL_ENABLE|EECTL_EECS;
sys/dev/ic/smc83c170.c
1141
reg |= EECTL_EEDI;
sys/dev/ic/smc83c170.c
1142
bus_space_write_4(st, sh, EPIC_EECTL, reg);
sys/dev/ic/smc83c170.c
1144
bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK);
sys/dev/ic/smc83c170.c
1146
bus_space_write_4(st, sh, EPIC_EECTL, reg);
sys/dev/ic/smc83c170.c
1152
reg = EECTL_ENABLE|EECTL_EECS;
sys/dev/ic/smc83c170.c
1154
reg |= EECTL_EEDI;
sys/dev/ic/smc83c170.c
1155
bus_space_write_4(st, sh, EPIC_EECTL, reg);
sys/dev/ic/smc83c170.c
1157
bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK);
sys/dev/ic/smc83c170.c
1159
bus_space_write_4(st, sh, EPIC_EECTL, reg);
sys/dev/ic/smc83c170.c
1164
reg = EECTL_ENABLE|EECTL_EECS;
sys/dev/ic/smc83c170.c
1167
bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK);
sys/dev/ic/smc83c170.c
1171
bus_space_write_4(st, sh, EPIC_EECTL, reg);
sys/dev/ic/smc83c170.c
1317
epic_mii_read(struct device *self, int phy, int reg)
sys/dev/ic/smc83c170.c
1325
MMCTL_ARG(phy, reg, MMCTL_READ));
sys/dev/ic/smc83c170.c
1338
epic_mii_write(struct device *self, int phy, int reg, int val)
sys/dev/ic/smc83c170.c
1347
MMCTL_ARG(phy, reg, MMCTL_WRITE));
sys/dev/ic/smc83c170reg.h
274
#define MMCTL_ARG(phy, reg, cmd) (((phy) << 9) | ((reg) << 4) | (cmd))
sys/dev/ic/smc91cxx.c
1161
smc91cxx_mii_readreg(struct device *self, int phy, int reg)
sys/dev/ic/smc91cxx.c
1168
val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg);
sys/dev/ic/smc91cxx.c
1176
smc91cxx_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/ic/smc91cxx.c
1182
mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val);
sys/dev/ic/tcic2.c
1076
int reg, size2, iotiny, wbase, hwwin, wscnt;
sys/dev/ic/tcic2.c
1103
reg = TCIC_ICTL_ENA | TCIC_ICTL_QUIET;
sys/dev/ic/tcic2.c
1104
reg |= (h->sock << TCIC_ICTL_SS_SHIFT) & TCIC_ICTL_SS_MASK;
sys/dev/ic/tcic2.c
1105
reg |= iotiny | tcic_iowidth_map[h->io[win].width];
sys/dev/ic/tcic2.c
1107
reg |= TCIC_ICTL_PASS16;
sys/dev/ic/tcic2.c
1113
reg |= wscnt & TCIC_ICTL_WSCNT_MASK;
sys/dev/ic/tcic2.c
1114
tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg);
sys/dev/ic/tcic2.c
1183
int reg, hwwin;
sys/dev/ic/tcic2.c
1189
reg = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin));
sys/dev/ic/tcic2.c
1190
reg &= ~TCIC_ICTL_ENA;
sys/dev/ic/tcic2.c
1191
tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg);
sys/dev/ic/tcic2.c
1200
int cardtype, reg, win;
sys/dev/ic/tcic2.c
1210
reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
sys/dev/ic/tcic2.c
1211
reg |= TCIC_ILOCK_CWAIT;
sys/dev/ic/tcic2.c
1212
reg &= ~(TCIC_ILOCK_CRESET|TCIC_ILOCK_CRESENA);
sys/dev/ic/tcic2.c
1213
tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
sys/dev/ic/tcic2.c
1219
reg = TCIC_PWR_VCC_N(h->sock) | TCIC_PWR_VPP_N(h->sock) | h->sc->pwrena;
sys/dev/ic/tcic2.c
1221
reg |= TCIC_PWR_VCC5V;
sys/dev/ic/tcic2.c
1222
tcic_write_1(h, TCIC_R_PWR, reg);
sys/dev/ic/tcic2.c
1226
reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
sys/dev/ic/tcic2.c
1227
reg |= TCIC_ILOCK_CRESENA;
sys/dev/ic/tcic2.c
1228
tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
sys/dev/ic/tcic2.c
1230
reg |= TCIC_ILOCK_CRESET;
sys/dev/ic/tcic2.c
1231
tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
sys/dev/ic/tcic2.c
1237
reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
sys/dev/ic/tcic2.c
1238
reg &= ~(TCIC_ILOCK_CRESET);
sys/dev/ic/tcic2.c
1239
tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
sys/dev/ic/tcic2.c
1264
reg = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock));
sys/dev/ic/tcic2.c
1265
reg &= ~TCIC_SCF1_IRQ_MASK;
sys/dev/ic/tcic2.c
1267
reg = 0;
sys/dev/ic/tcic2.c
1269
reg |= ((cardtype == PCMCIA_IFTYPE_IO) ?
sys/dev/ic/tcic2.c
1271
reg |= tcic_irqmap[h->ih_irq]; /* enable interrupts */
sys/dev/ic/tcic2.c
1272
reg &= ~TCIC_SCF1_IRQOD;
sys/dev/ic/tcic2.c
1273
tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), reg);
sys/dev/ic/tcic2.c
1277
((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg));
sys/dev/ic/tcic2.c
312
int i, reg;
sys/dev/ic/tcic2.c
327
reg = TCIC_WAIT_SYNC | TCIC_WAIT_CCLK | TCIC_WAIT_RISING;
sys/dev/ic/tcic2.c
328
reg |= (tcic_ns2wscnt(250) & TCIC_WAIT_COUNT_MASK);
sys/dev/ic/tcic2.c
329
tcic_write_aux_1(sc->iot, sc->ioh, TCIC_AR_WCTL, TCIC_R_WCTL_WAIT, reg);
sys/dev/ic/tcic2.c
330
reg = TCIC_SYSCFG_MPSEL_RI | TCIC_SYSCFG_MCSFULL;
sys/dev/ic/tcic2.c
331
tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg);
sys/dev/ic/tcic2.c
332
reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK);
sys/dev/ic/tcic2.c
333
reg |= TCIC_ILOCK_HOLD_CCLK;
sys/dev/ic/tcic2.c
334
tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK, reg);
sys/dev/ic/tcic2.c
347
reg = tcic_read_1(&sc->handle[0], TCIC_R_IENA);
sys/dev/ic/tcic2.c
349
(reg & ~TCIC_IENA_CFG_MASK) | TCIC_IENA_CFG_HIGH);
sys/dev/ic/tcic2.c
350
reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG);
sys/dev/ic/tcic2.c
352
(reg & ~TCIC_SYSCFG_IRQ_MASK) | tcic_irqmap[sc->irq]);
sys/dev/ic/tcic2.c
368
reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG);
sys/dev/ic/tcic2.c
369
reg &= ~TCIC_SYSCFG_AUTOBUSY;
sys/dev/ic/tcic2.c
370
tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg);
sys/dev/ic/tcic2.c
504
int reg;
sys/dev/ic/tcic2.c
510
reg = tcic_read_ind_2(h, TCIC_IR_SCF2_N(h->sock));
sys/dev/ic/tcic2.c
511
tcic_write_ind_2(h, TCIC_IR_SCF2_N(h->sock), reg & ~TCIC_SCF2_MCD);
sys/dev/ic/tcic2.c
514
reg = tcic_read_2(h, TCIC_R_IENA);
sys/dev/ic/tcic2.c
515
tcic_write_2(h, TCIC_R_IENA, reg |= TCIC_IENA_CDCHG);
sys/dev/ic/tcic2.c
518
h->sstat = reg = tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_STAT_MASK;
sys/dev/ic/tcic2.c
519
if (reg & TCIC_SSTAT_CD)
sys/dev/ic/tcic2.c
731
int val, reg;
sys/dev/ic/tcic2.c
749
reg = TCIC_IR_SCF1_N(h->sock);
sys/dev/ic/tcic2.c
750
val = tcic_read_ind_2(h, reg);
sys/dev/ic/tcic2.c
751
tcic_write_ind_2(h, reg, (val & ~TCIC_SCF1_IRQ_MASK)|TCIC_SCF1_IRQOFF);
sys/dev/ic/tcic2.c
752
reg = TCIC_IR_SCF2_N(h->sock);
sys/dev/ic/tcic2.c
753
val = tcic_read_ind_2(h, reg);
sys/dev/ic/tcic2.c
754
tcic_write_ind_2(h, reg,
sys/dev/ic/tcic2.c
834
int reg, hwwin, wscnt;
sys/dev/ic/tcic2.c
852
reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) &
sys/dev/ic/tcic2.c
855
reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) &
sys/dev/ic/tcic2.c
858
tcic_write_ind_2(h, TCIC_WR_MBASE_N(hwwin), reg);
sys/dev/ic/tcic2.c
861
reg = 0;
sys/dev/ic/tcic2.c
862
reg = ((h->mem[win].offset >> TCIC_MEM_SHIFT) & TCIC_MMAP_ADDR_MASK);
sys/dev/ic/tcic2.c
863
reg |= (kind == PCMCIA_MEM_ATTR) ? TCIC_MMAP_ATTR : 0;
sys/dev/ic/tcic2.c
865
win, hwwin, reg));
sys/dev/ic/tcic2.c
866
tcic_write_ind_2(h, TCIC_WR_MMAP_N(hwwin), reg);
sys/dev/ic/tcic2.c
871
reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)) & TCIC_MCTL_WSCNT_MASK;
sys/dev/ic/tcic2.c
872
reg |= TCIC_MCTL_ENA|TCIC_MCTL_QUIET;
sys/dev/ic/tcic2.c
873
reg |= mem8 ? TCIC_MCTL_B8 : 0;
sys/dev/ic/tcic2.c
874
reg |= (h->sock << TCIC_MCTL_SS_SHIFT) & TCIC_MCTL_SS_MASK;
sys/dev/ic/tcic2.c
891
reg |= wscnt & TCIC_MCTL_WSCNT_MASK;
sys/dev/ic/tcic2.c
893
tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg);
sys/dev/ic/tcic2.c
982
int reg, hwwin;
sys/dev/ic/tcic2.c
988
reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin));
sys/dev/ic/tcic2.c
989
reg &= ~TCIC_MCTL_ENA;
sys/dev/ic/tcic2.c
990
tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg);
sys/dev/ic/tcic2var.h
188
tcic_read_1(struct tcic_handle *h, int reg)
sys/dev/ic/tcic2var.h
190
return (bus_space_read_1(h->sc->iot, h->sc->ioh, reg));
sys/dev/ic/tcic2var.h
195
tcic_read_2(struct tcic_handle *h, int reg)
sys/dev/ic/tcic2var.h
197
return (bus_space_read_2(h->sc->iot, h->sc->ioh, reg));
sys/dev/ic/tcic2var.h
202
tcic_read_4(struct tcic_handle *h, int reg)
sys/dev/ic/tcic2var.h
205
val = bus_space_read_2(h->sc->iot, h->sc->ioh, reg);
sys/dev/ic/tcic2var.h
206
val |= bus_space_read_2(h->sc->iot, h->sc->ioh, reg+2) << 16;
sys/dev/ic/tcic2var.h
212
tcic_write_1(struct tcic_handle *h, int reg, int data)
sys/dev/ic/tcic2var.h
214
bus_space_write_1(h->sc->iot, h->sc->ioh, reg, (data));
sys/dev/ic/tcic2var.h
219
tcic_write_2(struct tcic_handle *h, int reg, int data)
sys/dev/ic/tcic2var.h
221
bus_space_write_2(h->sc->iot, h->sc->ioh, reg, (data));
sys/dev/ic/tcic2var.h
226
tcic_write_4(struct tcic_handle *h, int reg, int data)
sys/dev/ic/tcic2var.h
228
bus_space_write_2(h->sc->iot, h->sc->ioh, reg, (data));
sys/dev/ic/tcic2var.h
229
bus_space_write_2(h->sc->iot, h->sc->ioh, reg+2, (data)>>16);
sys/dev/ic/tcic2var.h
234
tcic_read_ind_2(struct tcic_handle *h, int reg)
sys/dev/ic/tcic2var.h
238
tcic_write_4(h, TCIC_R_ADDR, reg|TCIC_ADDR_INDREG);
sys/dev/ic/tcic2var.h
246
tcic_write_ind_2(struct tcic_handle *h, int reg, int data)
sys/dev/ic/tcic2var.h
250
tcic_write_4(h, TCIC_R_ADDR, reg|TCIC_ADDR_INDREG);
sys/dev/ic/tcic2var.h
286
int reg)
sys/dev/ic/tcic2var.h
291
val = bus_space_read_1(iot, ioh, reg);
sys/dev/ic/tcic2var.h
309
int reg, int val)
sys/dev/ic/tcic2var.h
314
bus_space_write_1(iot, ioh, reg, val);
sys/dev/ic/tea5757.c
103
u_int32_t reg;
sys/dev/ic/tea5757.c
106
reg = stereo | lock | TEA5757_SEARCH_START;
sys/dev/ic/tea5757.c
107
reg |= dir ? TEA5757_SEARCH_UP : TEA5757_SEARCH_DOWN;
sys/dev/ic/tea5757.c
108
tea5757_hardware_write(tea, reg);
sys/dev/ic/tea5757.c
114
reg = tea->read(tea->iot, tea->ioh, tea->offset);
sys/dev/ic/tea5757.c
115
} while ((reg & TEA5757_FREQ) == 0 && ++co < 200);
sys/dev/ic/tireg.h
988
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/ic/tireg.h
989
bus_space_write_4(sc->ti_btag, sc->ti_bhandle, (reg), (val))
sys/dev/ic/tireg.h
991
#define CSR_READ_4(sc, reg) \
sys/dev/ic/tireg.h
992
bus_space_read_4(sc->ti_btag, sc->ti_bhandle, (reg))
sys/dev/ic/tireg.h
994
#define TI_SETBIT(sc, reg, x) \
sys/dev/ic/tireg.h
995
CSR_WRITE_4(sc, (reg), (CSR_READ_4(sc, (reg)) | (x)))
sys/dev/ic/tireg.h
996
#define TI_CLRBIT(sc, reg, x) \
sys/dev/ic/tireg.h
997
CSR_WRITE_4(sc, (reg), (CSR_READ_4(sc, (reg)) & ~(x)))
sys/dev/ic/ufshci.c
1312
uint32_t reg;
sys/dev/ic/ufshci.c
1319
reg = ufshci_doorbell_read(sc);
sys/dev/ic/ufshci.c
1320
if (reg == 0)
sys/dev/ic/ufshci.c
1325
printf("%s: timeout (reg=0x%x)\n", __func__, reg);
sys/dev/ic/ufshci.c
1882
uint32_t blocks, reg;
sys/dev/ic/ufshci.c
1998
reg = UFSHCI_READ_4(my->sc, UFSHCI_REG_UTRLDBR);
sys/dev/ic/ufshci.c
1999
if ((reg & (1U << slot)) == 0)
sys/dev/ic/ufshci.c
427
uint32_t reg;
sys/dev/ic/ufshci.c
455
reg = UFSHCI_READ_4(sc, UFSHCI_REG_HCS);
sys/dev/ic/ufshci.c
456
if (reg & UFSHCI_REG_HCS_DP)
sys/dev/ic/ufshci.c
523
uint32_t reg;
sys/dev/ic/ufshci.c
525
reg = UFSHCI_READ_4(sc, UFSHCI_REG_UTRLDBR);
sys/dev/ic/ufshci.c
527
return reg;
sys/dev/ic/ufshci.c
533
uint32_t reg;
sys/dev/ic/ufshci.c
535
reg = (1U << slot);
sys/dev/ic/ufshci.c
537
UFSHCI_WRITE_4(sc, UFSHCI_REG_UTRLDBR, reg);
sys/dev/ic/ufshci.c
543
uint32_t reg;
sys/dev/ic/ufshci.c
548
reg = UFSHCI_READ_4(sc, UFSHCI_REG_UTRLDBR);
sys/dev/ic/ufshci.c
549
if ((reg & (1U << slot)) == 0)
sys/dev/ic/vgavar.h
103
_vga_attr_read(struct vga_handle *vh, int reg)
sys/dev/ic/vgavar.h
110
vga_raw_write(vh, VGA_ATC_INDEX, reg);
sys/dev/ic/vgavar.h
122
_vga_attr_write(struct vga_handle *vh, int reg, u_int8_t val)
sys/dev/ic/vgavar.h
127
vga_raw_write(vh, VGA_ATC_INDEX, reg);
sys/dev/ic/vgavar.h
137
_vga_ts_read(struct vga_handle *vh, int reg)
sys/dev/ic/vgavar.h
139
vga_raw_write(vh, VGA_TS_INDEX, reg);
sys/dev/ic/vgavar.h
144
_vga_ts_write(struct vga_handle *vh, int reg, u_int8_t val)
sys/dev/ic/vgavar.h
146
vga_raw_write(vh, VGA_TS_INDEX, reg);
sys/dev/ic/vgavar.h
151
_vga_gdc_read(struct vga_handle *vh, int reg)
sys/dev/ic/vgavar.h
153
vga_raw_write(vh, VGA_GDC_INDEX, reg);
sys/dev/ic/vgavar.h
158
_vga_gdc_write(struct vga_handle *vh, int reg, u_int8_t val)
sys/dev/ic/vgavar.h
160
vga_raw_write(vh, VGA_GDC_INDEX, reg);
sys/dev/ic/vgavar.h
164
#define vga_attr_read(vh, reg) \
sys/dev/ic/vgavar.h
165
_vga_attr_read(vh, offsetof(struct reg_vgaattr, reg))
sys/dev/ic/vgavar.h
166
#define vga_attr_write(vh, reg, val) \
sys/dev/ic/vgavar.h
167
_vga_attr_write(vh, offsetof(struct reg_vgaattr, reg), val)
sys/dev/ic/vgavar.h
168
#define vga_ts_read(vh, reg) \
sys/dev/ic/vgavar.h
169
_vga_ts_read(vh, offsetof(struct reg_vgats, reg))
sys/dev/ic/vgavar.h
170
#define vga_ts_write(vh, reg, val) \
sys/dev/ic/vgavar.h
171
_vga_ts_write(vh, offsetof(struct reg_vgats, reg), val)
sys/dev/ic/vgavar.h
172
#define vga_gdc_read(vh, reg) \
sys/dev/ic/vgavar.h
173
_vga_gdc_read(vh, offsetof(struct reg_vgagdc, reg))
sys/dev/ic/vgavar.h
174
#define vga_gdc_write(vh, reg, val) \
sys/dev/ic/vgavar.h
175
_vga_gdc_write(vh, offsetof(struct reg_vgagdc, reg), val)
sys/dev/ic/vgavar.h
177
#define vga_6845_read(vh, reg) \
sys/dev/ic/vgavar.h
178
pcdisplay_6845_read(&(vh)->vh_ph, reg)
sys/dev/ic/vgavar.h
179
#define vga_6845_write(vh, reg, val) \
sys/dev/ic/vgavar.h
180
pcdisplay_6845_write(&(vh)->vh_ph, reg, val)
sys/dev/ic/vgavar.h
94
#define vga_raw_read(vh, reg) \
sys/dev/ic/vgavar.h
95
bus_space_read_1(vh->vh_iot, vh->vh_ioh_vga, reg)
sys/dev/ic/vgavar.h
96
#define vga_raw_write(vh, reg, value) \
sys/dev/ic/vgavar.h
97
bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, reg, value)
sys/dev/ic/w83l518d.c
45
wb_idx_read(struct wb_softc *wb, uint8_t reg)
sys/dev/ic/w83l518d.c
47
bus_space_write_1(wb->wb_iot, wb->wb_ioh, WB_SD_INDEX, reg);
sys/dev/ic/w83l518d.c
52
wb_idx_write(struct wb_softc *wb, uint8_t reg, uint8_t val)
sys/dev/ic/w83l518d.c
54
bus_space_write_1(wb->wb_iot, wb->wb_ioh, WB_SD_INDEX, reg);
sys/dev/ic/w83l518d.c
59
wb_read(struct wb_softc *wb, uint8_t reg)
sys/dev/ic/w83l518d.c
61
return bus_space_read_1(wb->wb_iot, wb->wb_ioh, reg);
sys/dev/ic/w83l518d.c
65
wb_write(struct wb_softc *wb, uint8_t reg, uint8_t val)
sys/dev/ic/w83l518d.c
67
bus_space_write_1(wb->wb_iot, wb->wb_ioh, reg, val);
sys/dev/ic/wdc.c
292
wdc_default_read_reg(struct channel_softc *chp, enum wdc_regs reg)
sys/dev/ic/wdc.c
295
if (reg & _WDC_WRONLY) {
sys/dev/ic/wdc.c
296
printf ("wdc_default_read_reg: reading from a write-only register %d\n", reg);
sys/dev/ic/wdc.c
300
if (reg & _WDC_AUX)
sys/dev/ic/wdc.c
302
reg & _WDC_REGMASK));
sys/dev/ic/wdc.c
305
reg & _WDC_REGMASK));
sys/dev/ic/wdc.c
309
wdc_default_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
sys/dev/ic/wdc.c
312
if (reg & _WDC_RDONLY) {
sys/dev/ic/wdc.c
313
printf ("wdc_default_write_reg: writing to a read-only register %d\n", reg);
sys/dev/ic/wdc.c
317
if (reg & _WDC_AUX)
sys/dev/ic/wdc.c
319
reg & _WDC_REGMASK, val);
sys/dev/ic/wdc.c
322
reg & _WDC_REGMASK, val);
sys/dev/ic/wdc.c
326
wdc_default_lba48_write_reg(struct channel_softc *chp, enum wdc_regs reg,
sys/dev/ic/wdc.c
330
CHP_WRITE_REG(chp, reg, val >> 8);
sys/dev/ic/wdc.c
331
CHP_WRITE_REG(chp, reg, val);
sys/dev/ic/wdcevent.h
101
enum wdc_regs reg, u_int16_t val) {
sys/dev/ic/wdcevent.h
104
record[0] = reg;
sys/dev/ic/wdcevent.h
129
#define WDC_LOG_REG(chp, reg, val)
sys/dev/ic/wdcvar.h
118
u_int8_t (*read_reg)(struct channel_softc *, enum wdc_regs reg);
sys/dev/ic/wdcvar.h
119
void (*write_reg)(struct channel_softc *, enum wdc_regs reg,
sys/dev/ic/wdcvar.h
121
void (*lba48_write_reg)(struct channel_softc *, enum wdc_regs reg,
sys/dev/ic/xl.c
429
xl_miibus_readreg(struct device *self, int phy, int reg)
sys/dev/ic/xl.c
440
frame.mii_regaddr = reg;
sys/dev/ic/xl.c
447
xl_miibus_writereg(struct device *self, int phy, int reg, int data)
sys/dev/ic/xl.c
458
frame.mii_regaddr = reg;
sys/dev/ic/xlreg.h
643
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/ic/xlreg.h
644
bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val)
sys/dev/ic/xlreg.h
645
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/ic/xlreg.h
646
bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val)
sys/dev/ic/xlreg.h
647
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/ic/xlreg.h
648
bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val)
sys/dev/ic/xlreg.h
650
#define CSR_READ_4(sc, reg) \
sys/dev/ic/xlreg.h
651
bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg)
sys/dev/ic/xlreg.h
652
#define CSR_READ_2(sc, reg) \
sys/dev/ic/xlreg.h
653
bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg)
sys/dev/ic/xlreg.h
654
#define CSR_READ_1(sc, reg) \
sys/dev/ic/xlreg.h
655
bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg)
sys/dev/ic/z8530sc.c
166
uint8_t *reg, v;
sys/dev/ic/z8530sc.c
189
reg = cs->cs_creg; /* current regs */
sys/dev/ic/z8530sc.c
192
zs_write_reg(cs, 1, reg[1] & ~ZSWR1_IMASK);
sys/dev/ic/z8530sc.c
195
zs_write_reg(cs, 4, reg[4]);
sys/dev/ic/z8530sc.c
198
zs_write_reg(cs, 10, reg[10]);
sys/dev/ic/z8530sc.c
201
zs_write_reg(cs, 3, reg[3] & ~ZSWR3_RX_ENABLE);
sys/dev/ic/z8530sc.c
202
zs_write_reg(cs, 5, reg[5] & ~ZSWR5_TX_ENABLE);
sys/dev/ic/z8530sc.c
205
zs_write_reg(cs, 6, reg[6]);
sys/dev/ic/z8530sc.c
206
if (reg[15] & ZSWR15_ENABLE_ENHANCED)
sys/dev/ic/z8530sc.c
208
zs_write_reg(cs, 7, reg[7]);
sys/dev/ic/z8530sc.c
219
zs_write_reg(cs, 2, reg[2]);
sys/dev/ic/z8530sc.c
221
zs_write_reg(cs, 9, reg[9]);
sys/dev/ic/z8530sc.c
225
zs_write_reg(cs, 14, reg[14] & ~ZSWR14_BAUD_ENA);
sys/dev/ic/z8530sc.c
233
zs_write_reg(cs, 11, reg[11]);
sys/dev/ic/z8530sc.c
236
zs_write_reg(cs, 12, reg[12]);
sys/dev/ic/z8530sc.c
237
zs_write_reg(cs, 13, reg[13]);
sys/dev/ic/z8530sc.c
240
zs_write_reg(cs, 14, reg[14]);
sys/dev/ic/z8530sc.c
243
zs_write_reg(cs, 15, reg[15]);
sys/dev/ic/z8530sc.c
255
zs_write_reg(cs, 3, reg[3]);
sys/dev/ic/z8530sc.c
256
zs_write_reg(cs, 5, reg[5]);
sys/dev/ic/z8530sc.c
266
if (reg[15] & ZSWR15_ENABLE_ENHANCED)
sys/dev/ic/z8530sc.c
267
zs_write_reg(cs, 7, reg[16]);
sys/dev/ic/z8530sc.c
270
zs_write_reg(cs, 1, reg[1]);
sys/dev/ipmi.c
320
bt_read(struct ipmi_softc *sc, int reg)
sys/dev/ipmi.c
322
return bmc_read(sc, reg);
sys/dev/ipmi.c
326
bt_write(struct ipmi_softc *sc, int reg, uint8_t data)
sys/dev/ipmi.c
337
bmc_write(sc, reg, data);
sys/dev/isa/ad1848.c
1008
reg = ad_read(sc, SP_LEFT_INPUT_CONTROL);
sys/dev/isa/ad1848.c
1009
reg &= INPUT_SOURCE_MASK;
sys/dev/isa/ad1848.c
1010
ad_write(sc, SP_LEFT_INPUT_CONTROL, (inp | reg));
sys/dev/isa/ad1848.c
1012
reg = ad_read(sc, SP_RIGHT_INPUT_CONTROL);
sys/dev/isa/ad1848.c
1013
reg &= INPUT_SOURCE_MASK;
sys/dev/isa/ad1848.c
1014
ad_write(sc, SP_RIGHT_INPUT_CONTROL, (inp | reg));
sys/dev/isa/ad1848.c
1281
u_char reg;
sys/dev/isa/ad1848.c
1285
reg = ad_read(sc, SP_INTERFACE_CONFIG);
sys/dev/isa/ad1848.c
1286
ad_write(sc, SP_INTERFACE_CONFIG, (reg & ~PLAYBACK_ENABLE));
sys/dev/isa/ad1848.c
1300
u_char reg;
sys/dev/isa/ad1848.c
1304
reg = ad_read(sc, SP_INTERFACE_CONFIG);
sys/dev/isa/ad1848.c
1305
ad_write(sc, SP_INTERFACE_CONFIG, (reg & ~CAPTURE_ENABLE));
sys/dev/isa/ad1848.c
1320
u_char reg;
sys/dev/isa/ad1848.c
1345
reg = ad_read(sc, SP_INTERFACE_CONFIG);
sys/dev/isa/ad1848.c
1346
ad_write(sc, SP_INTERFACE_CONFIG, (CAPTURE_ENABLE | reg));
sys/dev/isa/ad1848.c
1361
u_char reg;
sys/dev/isa/ad1848.c
1377
reg = ad_read(sc, SP_INTERFACE_CONFIG);
sys/dev/isa/ad1848.c
1378
ad_write(sc, SP_INTERFACE_CONFIG, (PLAYBACK_ENABLE | reg));
sys/dev/isa/ad1848.c
161
ad_read(struct ad1848_softc *sc, int reg)
sys/dev/isa/ad1848.c
165
ADWRITE(sc, AD1848_IADDR, (reg & 0xff) | sc->MCE_bit);
sys/dev/isa/ad1848.c
173
ad_write(struct ad1848_softc *sc, int reg, int data)
sys/dev/isa/ad1848.c
175
ADWRITE(sc, AD1848_IADDR, (reg & 0xff) | sc->MCE_bit);
sys/dev/isa/ad1848.c
605
u_char reg;
sys/dev/isa/ad1848.c
607
reg = ad_read(sc, mixer_channel_info[device].left_reg);
sys/dev/isa/ad1848.c
612
reg & 0xFE);
sys/dev/isa/ad1848.c
615
reg | 0x80);
sys/dev/isa/ad1848.c
620
reg | 0x01);
sys/dev/isa/ad1848.c
623
reg & ~0x80);
sys/dev/isa/ad1848.c
631
reg = ad_read(sc, mixer_channel_info[device].right_reg);
sys/dev/isa/ad1848.c
634
ad_write(sc, mixer_channel_info[device].right_reg, reg | 0x80);
sys/dev/isa/ad1848.c
636
ad_write(sc, mixer_channel_info[device].right_reg, reg & ~0x80);
sys/dev/isa/ad1848.c
645
u_char reg;
sys/dev/isa/ad1848.c
653
reg = ad_read(sc, info->left_reg) & (info->atten_mask);
sys/dev/isa/ad1848.c
655
reg |= ((atten & info->atten_bits) << 2);
sys/dev/isa/ad1848.c
657
reg |= ((atten & info->atten_bits));
sys/dev/isa/ad1848.c
659
ad_write(sc, info->left_reg, reg);
sys/dev/isa/ad1848.c
666
reg = ad_read(sc, info->right_reg);
sys/dev/isa/ad1848.c
667
reg &= (info->atten_mask);
sys/dev/isa/ad1848.c
668
ad_write(sc, info->right_reg, (atten & info->atten_bits) | reg);
sys/dev/isa/ad1848.c
691
u_char reg, gain;
sys/dev/isa/ad1848.c
698
reg = ad_read(sc, SP_LEFT_INPUT_CONTROL);
sys/dev/isa/ad1848.c
699
reg &= INPUT_GAIN_MASK;
sys/dev/isa/ad1848.c
700
ad_write(sc, SP_LEFT_INPUT_CONTROL, (gain & 0x0f) | reg);
sys/dev/isa/ad1848.c
703
reg = ad_read(sc, SP_RIGHT_INPUT_CONTROL);
sys/dev/isa/ad1848.c
704
reg &= INPUT_GAIN_MASK;
sys/dev/isa/ad1848.c
705
ad_write(sc, SP_RIGHT_INPUT_CONTROL, (gain & 0x0f) | reg);
sys/dev/isa/ad1848.c
732
u_char reg;
sys/dev/isa/ad1848.c
738
reg = ad_read(sc, SP_LEFT_INPUT_CONTROL);
sys/dev/isa/ad1848.c
740
reg | INPUT_MIC_GAIN_ENABLE);
sys/dev/isa/ad1848.c
743
reg = ad_read(sc, SP_LEFT_INPUT_CONTROL);
sys/dev/isa/ad1848.c
745
reg & ~INPUT_MIC_GAIN_ENABLE);
sys/dev/isa/ad1848.c
993
u_char inp, reg;
sys/dev/isa/ess.c
1144
u_int8_t reg;
sys/dev/isa/ess.c
1164
reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO_CTRL);
sys/dev/isa/ess.c
1166
reg &= ~ESS_AUDIO_CTRL_MONO;
sys/dev/isa/ess.c
1167
reg |= ESS_AUDIO_CTRL_STEREO;
sys/dev/isa/ess.c
1169
reg |= ESS_AUDIO_CTRL_MONO;
sys/dev/isa/ess.c
1170
reg &= ~ESS_AUDIO_CTRL_STEREO;
sys/dev/isa/ess.c
1172
ess_write_x_reg(sc, ESS_XCMD_AUDIO_CTRL, reg);
sys/dev/isa/ess.c
1174
reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO1_CTRL1);
sys/dev/isa/ess.c
1176
reg |= ESS_AUDIO1_CTRL1_FIFO_SIZE;
sys/dev/isa/ess.c
1178
reg &= ~ESS_AUDIO1_CTRL1_FIFO_SIZE;
sys/dev/isa/ess.c
1180
reg |= ESS_AUDIO1_CTRL1_FIFO_STEREO;
sys/dev/isa/ess.c
1182
reg &= ~ESS_AUDIO1_CTRL1_FIFO_STEREO;
sys/dev/isa/ess.c
1185
reg |= ESS_AUDIO1_CTRL1_FIFO_SIGNED;
sys/dev/isa/ess.c
1187
reg &= ~ESS_AUDIO1_CTRL1_FIFO_SIGNED;
sys/dev/isa/ess.c
1188
reg |= ESS_AUDIO1_CTRL1_FIFO_CONNECT;
sys/dev/isa/ess.c
1189
ess_write_x_reg(sc, ESS_XCMD_AUDIO1_CTRL1, reg);
sys/dev/isa/ess.c
1205
reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO1_CTRL2);
sys/dev/isa/ess.c
1206
reg &= ~(ESS_AUDIO1_CTRL2_DMA_READ | ESS_AUDIO1_CTRL2_ADC_ENABLE);
sys/dev/isa/ess.c
1207
reg |= ESS_AUDIO1_CTRL2_FIFO_ENABLE | ESS_AUDIO1_CTRL2_AUTO_INIT;
sys/dev/isa/ess.c
1208
ess_write_x_reg(sc, ESS_XCMD_AUDIO1_CTRL2, reg);
sys/dev/isa/ess.c
1218
u_int8_t reg;
sys/dev/isa/ess.c
1238
reg = ess_read_mix_reg(sc, ESS_MREG_AUDIO2_CTRL2);
sys/dev/isa/ess.c
1240
reg |= ESS_AUDIO2_CTRL2_FIFO_SIZE;
sys/dev/isa/ess.c
1242
reg &= ~ESS_AUDIO2_CTRL2_FIFO_SIZE;
sys/dev/isa/ess.c
1244
reg |= ESS_AUDIO2_CTRL2_CHANNELS;
sys/dev/isa/ess.c
1246
reg &= ~ESS_AUDIO2_CTRL2_CHANNELS;
sys/dev/isa/ess.c
1249
reg |= ESS_AUDIO2_CTRL2_FIFO_SIGNED;
sys/dev/isa/ess.c
1251
reg &= ~ESS_AUDIO2_CTRL2_FIFO_SIGNED;
sys/dev/isa/ess.c
1252
ess_write_mix_reg(sc, ESS_MREG_AUDIO2_CTRL2, reg);
sys/dev/isa/ess.c
1265
reg = ess_read_mix_reg(sc, ESS_MREG_AUDIO2_CTRL1);
sys/dev/isa/ess.c
1267
reg |= ESS_AUDIO2_CTRL1_XFER_SIZE;
sys/dev/isa/ess.c
1269
reg &= ~ESS_AUDIO2_CTRL1_XFER_SIZE;
sys/dev/isa/ess.c
1270
reg |= ESS_AUDIO2_CTRL1_DEMAND_8;
sys/dev/isa/ess.c
1271
reg |= ESS_AUDIO2_CTRL1_DAC_ENABLE | ESS_AUDIO2_CTRL1_FIFO_ENABLE |
sys/dev/isa/ess.c
1273
ess_write_mix_reg(sc, ESS_MREG_AUDIO2_CTRL1, reg);
sys/dev/isa/ess.c
1283
u_int8_t reg;
sys/dev/isa/ess.c
1303
reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO_CTRL);
sys/dev/isa/ess.c
1305
reg &= ~ESS_AUDIO_CTRL_MONO;
sys/dev/isa/ess.c
1306
reg |= ESS_AUDIO_CTRL_STEREO;
sys/dev/isa/ess.c
1308
reg |= ESS_AUDIO_CTRL_MONO;
sys/dev/isa/ess.c
1309
reg &= ~ESS_AUDIO_CTRL_STEREO;
sys/dev/isa/ess.c
1311
ess_write_x_reg(sc, ESS_XCMD_AUDIO_CTRL, reg);
sys/dev/isa/ess.c
1313
reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO1_CTRL1);
sys/dev/isa/ess.c
1315
reg |= ESS_AUDIO1_CTRL1_FIFO_SIZE;
sys/dev/isa/ess.c
1317
reg &= ~ESS_AUDIO1_CTRL1_FIFO_SIZE;
sys/dev/isa/ess.c
1319
reg |= ESS_AUDIO1_CTRL1_FIFO_STEREO;
sys/dev/isa/ess.c
1321
reg &= ~ESS_AUDIO1_CTRL1_FIFO_STEREO;
sys/dev/isa/ess.c
1324
reg |= ESS_AUDIO1_CTRL1_FIFO_SIGNED;
sys/dev/isa/ess.c
1326
reg &= ~ESS_AUDIO1_CTRL1_FIFO_SIGNED;
sys/dev/isa/ess.c
1327
reg |= ESS_AUDIO1_CTRL1_FIFO_CONNECT;
sys/dev/isa/ess.c
1328
ess_write_x_reg(sc, ESS_XCMD_AUDIO1_CTRL1, reg);
sys/dev/isa/ess.c
1344
reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO1_CTRL2);
sys/dev/isa/ess.c
1345
reg |= ESS_AUDIO1_CTRL2_DMA_READ | ESS_AUDIO1_CTRL2_ADC_ENABLE;
sys/dev/isa/ess.c
1346
reg |= ESS_AUDIO1_CTRL2_FIFO_ENABLE | ESS_AUDIO1_CTRL2_AUTO_INIT;
sys/dev/isa/ess.c
1347
ess_write_x_reg(sc, ESS_XCMD_AUDIO1_CTRL2, reg);
sys/dev/isa/ess.c
1395
u_int8_t reg;
sys/dev/isa/ess.c
1401
reg = EREAD1(sc->sc_iot, sc->sc_ioh, ESS_DSP_RW_STATUS);
sys/dev/isa/ess.c
1402
if ((reg & ESS_DSP_READ_OFLOW) == 0) {
sys/dev/isa/ess.c
1406
reg = EREAD1(sc->sc_iot, sc->sc_ioh, ESS_CLEAR_INTR);
sys/dev/isa/ess.c
1424
u_int8_t reg;
sys/dev/isa/ess.c
1430
reg = ess_read_mix_reg(sc, ESS_MREG_AUDIO2_CTRL2);
sys/dev/isa/ess.c
1431
if ((reg & ESS_AUDIO2_CTRL2_IRQ_LATCH) == 0) {
sys/dev/isa/ess.c
1435
reg &= ~ESS_AUDIO2_CTRL2_IRQ_LATCH;
sys/dev/isa/ess.c
1436
ess_write_mix_reg(sc, ESS_MREG_AUDIO2_CTRL2, reg);
sys/dev/isa/ess.c
2392
ess_write_x_reg(struct ess_softc *sc, u_char reg, u_char val)
sys/dev/isa/ess.c
2396
DPRINTFN(2,("ess_write_x_reg: %02x=%02x\n", reg, val));
sys/dev/isa/ess.c
2397
if ((error = ess_wdsp(sc, reg)) == 0)
sys/dev/isa/ess.c
2407
ess_read_x_reg(struct ess_softc *sc, u_char reg)
sys/dev/isa/ess.c
2413
error = ess_wdsp(sc, reg);
sys/dev/isa/ess.c
2415
DPRINTF(("Error reading extended register 0x%02x\n", reg));
sys/dev/isa/ess.c
2418
DPRINTFN(2,("ess_read_x_reg: %02x=%02x\n", reg, val));
sys/dev/isa/ess.c
2423
ess_clear_xreg_bits(struct ess_softc *sc, u_char reg, u_char mask)
sys/dev/isa/ess.c
2425
if (ess_write_x_reg(sc, reg, ess_read_x_reg(sc, reg) & ~mask) == -1)
sys/dev/isa/ess.c
2427
reg));
sys/dev/isa/ess.c
2431
ess_set_xreg_bits(struct ess_softc *sc, u_char reg, u_char mask)
sys/dev/isa/ess.c
2433
if (ess_write_x_reg(sc, reg, ess_read_x_reg(sc, reg) | mask) == -1)
sys/dev/isa/ess.c
2435
reg));
sys/dev/isa/ess.c
2443
ess_write_mix_reg(struct ess_softc *sc, u_char reg, u_char val)
sys/dev/isa/ess.c
2448
DPRINTFN(2,("ess_write_mix_reg: %x=%x\n", reg, val));
sys/dev/isa/ess.c
2451
EWRITE1(iot, ioh, ESS_MIX_REG_SELECT, reg);
sys/dev/isa/ess.c
2460
ess_read_mix_reg(struct ess_softc *sc, u_char reg)
sys/dev/isa/ess.c
2467
EWRITE1(iot, ioh, ESS_MIX_REG_SELECT, reg);
sys/dev/isa/ess.c
2471
DPRINTFN(2,("ess_read_mix_reg: %x=%x\n", reg, val));
sys/dev/isa/ess.c
2476
ess_clear_mreg_bits(struct ess_softc *sc, u_char reg, u_char mask)
sys/dev/isa/ess.c
2478
ess_write_mix_reg(sc, reg, ess_read_mix_reg(sc, reg) & ~mask);
sys/dev/isa/ess.c
2482
ess_set_mreg_bits(struct ess_softc *sc, u_char reg, u_char mask)
sys/dev/isa/ess.c
2484
ess_write_mix_reg(sc, reg, ess_read_mix_reg(sc, reg) | mask);
sys/dev/isa/ess.c
2488
ess_read_multi_mix_reg(struct ess_softc *sc, u_char reg, u_int8_t *datap,
sys/dev/isa/ess.c
2495
EWRITE1(iot, ioh, ESS_MIX_REG_SELECT, reg);
sys/dev/isa/fins.c
324
fins_read(bus_space_tag_t iot, bus_space_handle_t ioh, int reg)
sys/dev/isa/fins.c
326
bus_space_write_1(iot, ioh, FINS_ADDR, reg);
sys/dev/isa/fins.c
331
fins_read_2(bus_space_tag_t iot, bus_space_handle_t ioh, int reg)
sys/dev/isa/fins.c
335
bus_space_write_1(iot, ioh, FINS_ADDR, reg);
sys/dev/isa/fins.c
337
bus_space_write_1(iot, ioh, FINS_ADDR, reg + 1);
sys/dev/isa/fins.c
342
fins_write(bus_space_tag_t iot, bus_space_handle_t ioh, int reg, u_int8_t val)
sys/dev/isa/fins.c
344
bus_space_write_1(iot, ioh, FINS_ADDR, reg);
sys/dev/isa/fins.c
349
fins_read_sens(struct fins_softc *sc, int reg)
sys/dev/isa/fins.c
351
return (fins_read(sc->sc_iot, sc->sc_ioh_sens, reg));
sys/dev/isa/fins.c
355
fins_read_sens_2(struct fins_softc *sc, int reg)
sys/dev/isa/fins.c
357
return (fins_read_2(sc->sc_iot, sc->sc_ioh_sens, reg));
sys/dev/isa/fins.c
361
fins_read_wdog(struct fins_softc *sc, int reg)
sys/dev/isa/fins.c
363
return (bus_space_read_1(sc->sc_iot, sc->sc_ioh_wdog, reg));
sys/dev/isa/fins.c
367
fins_write_wdog(struct fins_softc *sc, int reg, u_int8_t val)
sys/dev/isa/fins.c
369
bus_space_write_1(sc->sc_iot, sc->sc_ioh_wdog, reg, val);
sys/dev/isa/gscsio.c
94
#define ACB_READ(reg) \
sys/dev/isa/gscsio.c
95
bus_space_read_1(sc->sc_iot, acb->ioh, (reg))
sys/dev/isa/gscsio.c
96
#define ACB_WRITE(reg, val) \
sys/dev/isa/gscsio.c
97
bus_space_write_1(sc->sc_iot, acb->ioh, (reg), (val))
sys/dev/isa/i82365_isasubr.c
187
int irq, ist, reg;
sys/dev/isa/i82365_isasubr.c
201
reg = pcic_read(h, PCIC_INTR);
sys/dev/isa/i82365_isasubr.c
202
reg &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE);
sys/dev/isa/i82365_isasubr.c
203
pcic_write(h, PCIC_INTR, reg | irq);
sys/dev/isa/i82365_isasubr.c
215
int reg;
sys/dev/isa/i82365_isasubr.c
221
reg = pcic_read(h, PCIC_INTR);
sys/dev/isa/i82365_isasubr.c
222
reg &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE);
sys/dev/isa/i82365_isasubr.c
223
pcic_write(h, PCIC_INTR, reg);
sys/dev/isa/if_ef_isapnp.c
787
ef_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/isa/if_ef_isapnp.c
817
ef_mii_writeb(sc, (reg & i) ? 1 : 0);
sys/dev/isa/if_ef_isapnp.c
858
ef_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/isa/if_ef_isapnp.c
882
ef_mii_writeb(sc, (reg & i) ? 1 : 0);
sys/dev/isa/lm78_isa.c
256
lm_isa_readreg(struct lm_softc *lmsc, int reg)
sys/dev/isa/lm78_isa.c
260
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LMC_ADDR, reg);
sys/dev/isa/lm78_isa.c
265
lm_isa_writereg(struct lm_softc *lmsc, int reg, int val)
sys/dev/isa/lm78_isa.c
269
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LMC_ADDR, reg);
sys/dev/isa/nsclpcsio_isa.c
183
#define GPIO_READ(sc, reg) \
sys/dev/isa/nsclpcsio_isa.c
185
(sc)->sc_ld_ioh[SIO_LDN_GPIO], (reg))
sys/dev/isa/nsclpcsio_isa.c
186
#define GPIO_WRITE(sc, reg, val) \
sys/dev/isa/nsclpcsio_isa.c
188
(sc)->sc_ld_ioh[SIO_LDN_GPIO], (reg), (val))
sys/dev/isa/nsclpcsio_isa.c
189
#define TMS_WRITE(sc, reg, val) \
sys/dev/isa/nsclpcsio_isa.c
191
(sc)->sc_ld_ioh[SIO_LDN_TMS], (reg), (val))
sys/dev/isa/nsclpcsio_isa.c
192
#define TMS_READ(sc, reg) \
sys/dev/isa/nsclpcsio_isa.c
194
(sc)->sc_ld_ioh[SIO_LDN_TMS], (reg))
sys/dev/isa/nsclpcsio_isa.c
195
#define VLM_WRITE(sc, reg, val) \
sys/dev/isa/nsclpcsio_isa.c
197
(sc)->sc_ld_ioh[SIO_LDN_VLM], (reg), (val))
sys/dev/isa/nsclpcsio_isa.c
198
#define VLM_READ(sc, reg) \
sys/dev/isa/nsclpcsio_isa.c
200
(sc)->sc_ld_ioh[SIO_LDN_VLM], (reg))
sys/dev/isa/nsclpcsio_isa.c
541
int port, shift, reg;
sys/dev/isa/nsclpcsio_isa.c
549
reg = SIO_GPDI0;
sys/dev/isa/nsclpcsio_isa.c
552
reg = SIO_GPDI1;
sys/dev/isa/nsclpcsio_isa.c
555
reg = SIO_GPDI2;
sys/dev/isa/nsclpcsio_isa.c
558
reg = SIO_GPDI3;
sys/dev/isa/nsclpcsio_isa.c
562
data = GPIO_READ(sc, reg);
sys/dev/isa/nsclpcsio_isa.c
571
int port, shift, reg;
sys/dev/isa/nsclpcsio_isa.c
579
reg = SIO_GPDO0;
sys/dev/isa/nsclpcsio_isa.c
582
reg = SIO_GPDO1;
sys/dev/isa/nsclpcsio_isa.c
585
reg = SIO_GPDO2;
sys/dev/isa/nsclpcsio_isa.c
588
reg = SIO_GPDO3;
sys/dev/isa/nsclpcsio_isa.c
592
data = GPIO_READ(sc, reg);
sys/dev/isa/nsclpcsio_isa.c
598
GPIO_WRITE(sc, reg, data);
sys/dev/isa/sch311x.c
169
u_int8_t reg);
sys/dev/isa/sch311x.c
171
u_int8_t reg, u_int8_t val);
sys/dev/isa/sch311x.c
176
u_int8_t schsio_hwm_read(struct schsio_softc *sc, u_int8_t reg);
sys/dev/isa/sch311x.c
209
u_int8_t reg)
sys/dev/isa/sch311x.c
211
bus_space_write_1(iot, ioh, SCHSIO_PORT_INDEX, reg);
sys/dev/isa/sch311x.c
217
u_int8_t reg, u_int8_t val)
sys/dev/isa/sch311x.c
219
bus_space_write_1(iot, ioh, SCHSIO_PORT_INDEX, reg);
sys/dev/isa/sch311x.c
229
u_int8_t reg;
sys/dev/isa/sch311x.c
237
reg = schsio_config_read(iot, ioh, SCHSIO_IDX_DEVICE);
sys/dev/isa/sch311x.c
242
switch (reg) {
sys/dev/isa/sch311x.c
251
ia->ia_aux = (void *)(u_long) reg;
sys/dev/isa/sch311x.c
461
schsio_hwm_read(struct schsio_softc *sc, u_int8_t reg)
sys/dev/isa/sch311x.c
463
bus_space_write_1(sc->sc_iot, sc->sc_ioh_rr, SCHSIO_HWM_INDEX, reg);
sys/dev/isa/sch311x.c
470
u_int8_t reg;
sys/dev/isa/sch311x.c
472
reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh_rr, SCHSIO_WDT_GPIO);
sys/dev/isa/sch311x.c
473
if ((reg & SCHSIO_WDT_GPIO_MASK) != SCHSIO_WDT_GPIO_OUT) {
sys/dev/isa/sch311x.c
475
reg &= ~0x0f;
sys/dev/isa/sch311x.c
476
reg |= SCHSIO_WDT_GPIO_OUT;
sys/dev/isa/sch311x.c
478
SCHSIO_WDT_GPIO, reg);
sys/dev/isa/sch311x.c
490
reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh_rr, SCHSIO_WDT_CTRL);
sys/dev/isa/sch311x.c
491
if (reg & SCHSIO_WDT_CTRL_TRIGGERED) {
sys/dev/isa/sch311x.c
493
reg &= ~SCHSIO_WDT_CTRL_TRIGGERED;
sys/dev/isa/sch311x.c
495
SCHSIO_WDT_CTRL, reg);
sys/dev/isa/sch311x.c
499
reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh_rr, SCHSIO_WDT_CFG);
sys/dev/isa/sch311x.c
500
reg &= ~(SCHSIO_WDT_CFG_MSEN | SCHSIO_WDT_CFG_KBDEN);
sys/dev/isa/sch311x.c
501
bus_space_write_1(sc->sc_iot, sc->sc_ioh_rr, SCHSIO_WDT_CFG, reg);
sys/dev/isa/sch311x.c
510
uint8_t val, minute, reg;
sys/dev/isa/sch311x.c
523
reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh_rr,
sys/dev/isa/sch311x.c
526
reg |= SCHSIO_WDT_TO_SECONDS;
sys/dev/isa/sch311x.c
528
reg &= ~SCHSIO_WDT_TO_SECONDS;
sys/dev/isa/sch311x.c
531
reg);
sys/dev/isa/tcic2_isa.c
310
int irq, ist, val, reg;
sys/dev/isa/tcic2_isa.c
340
reg = TCIC_IR_SCF1_N(h->sock);
sys/dev/isa/tcic2_isa.c
341
val = (tcic_read_ind_2(h, reg) & (~TCIC_SCF1_IRQ_MASK)) | irqmap[irq];
sys/dev/isa/tcic2_isa.c
342
tcic_write_ind_2(h, reg, val);
sys/dev/isa/tcic2_isa.c
352
int val, reg;
sys/dev/isa/tcic2_isa.c
358
reg = TCIC_IR_SCF1_N(h->sock);
sys/dev/isa/tcic2_isa.c
359
val = tcic_read_ind_2(h, reg);
sys/dev/isa/tcic2_isa.c
361
tcic_write_ind_2(h, reg, val);
sys/dev/isa/uguru.c
117
uint8_t reg;
sys/dev/isa/uguru.c
37
#define UGURU_READ(iot, ioh, reg) \
sys/dev/isa/uguru.c
38
bus_space_read_1((iot), (ioh), (reg))
sys/dev/isa/uguru.c
39
#define UGURU_WRITE(iot, ioh, reg, val) \
sys/dev/isa/uguru.c
40
bus_space_write_1((iot), (ioh), (reg), (val))
sys/dev/isa/uguru.c
936
uint8_t reg = sc->uguru_sensors[n].reg;
sys/dev/isa/uguru.c
947
if (uguru_write_multi(iot, ioh, idx, ®, sizeof(reg)) ||
sys/dev/isa/uguru.c
955
if (uguru_write_multi(iot, ioh, idx + 1, ®, sizeof(reg)) ||
sys/dev/isa/uguru.c
966
idx, reg, val, data[0], data[1], data[2]);
sys/dev/isa/uguru.c
974
uint16_t reg;
sys/dev/isa/uguru.c
978
reg = sc->uguru_sensors[n].reg | 0x0880;
sys/dev/isa/uguru.c
979
if (uguru_ac5_read(sc->sc_iot, sc->sc_ioh, reg, &val, sizeof(val)))
sys/dev/isa/uguru.c
988
uint16_t reg, void *data, int count)
sys/dev/isa/uguru.c
992
buf[0] = reg >> 8;
sys/dev/isa/uguru.c
993
buf[1] = reg & 0xff;
sys/dev/isa/viasio.c
148
u_int8_t reg;
sys/dev/isa/viasio.c
155
reg = viasio_conf_read(iot, ioh, VT1211_ID);
sys/dev/isa/viasio.c
156
DPRINTF(("viasio_probe: id 0x%02x\n", reg));
sys/dev/isa/viasio.c
159
if (reg == VT1211_ID_VT1211) {
sys/dev/isa/viasio.c
176
u_int8_t reg;
sys/dev/isa/viasio.c
190
reg = viasio_conf_read(sc->sc_iot, sc->sc_ioh, VT1211_REV);
sys/dev/isa/viasio.c
191
printf(": VT1211 rev 0x%02x", reg);
sys/dev/isa/wbsio.c
100
reg = wbsio_conf_read(iot, ioh, WBSIO_ID);
sys/dev/isa/wbsio.c
101
DPRINTF(("wbsio_probe: id 0x%02x\n", reg));
sys/dev/isa/wbsio.c
104
switch (reg) {
sys/dev/isa/wbsio.c
136
u_int8_t devid, reg, reg0, reg1;
sys/dev/isa/wbsio.c
204
reg = wbsio_conf_read(sc->sc_iot, sc->sc_ioh, WBSIO_REV);
sys/dev/isa/wbsio.c
205
printf(" rev 0x%02x", reg);
sys/dev/isa/wbsio.c
93
u_int8_t reg;
sys/dev/microcode/siop/ncr53cxxx.c
1113
int reg, size;
sys/dev/microcode/siop/ncr53cxxx.c
1115
reg = CheckRegister(i);
sys/dev/microcode/siop/ncr53cxxx.c
1116
if (reg < 0)
sys/dev/microcode/siop/ncr53cxxx.c
1119
inst0 |= reg << 16;
sys/dev/microcode/siop/ncr53cxxx.c
1120
if (reg == 8)
sys/dev/microcode/siop/ncr53cxxx.c
1130
if ((reg & 0x3) + size > 4)
sys/dev/microcode/siop/ncr53cxxx.c
1340
int reg;
sys/dev/microcode/siop/ncr53cxxx.c
1370
reg = CheckRegister (tokenix);
sys/dev/microcode/siop/ncr53cxxx.c
1371
if (reg < 0) { /* Not register, must be data */
sys/dev/microcode/siop/ncr53cxxx.c
1375
reg = CheckRegister (tokenix+2);
sys/dev/microcode/siop/ncr53cxxx.c
1376
if (reg < 0)
sys/dev/microcode/siop/ncr53cxxx.c
1378
inst0 = 0x78000000 | (data << 8) | reg << 16;
sys/dev/microcode/siop/ncr53cxxx.c
1380
fprintf (listfp, "Move data to register: %02x %d\n", data, reg);
sys/dev/microcode/siop/ncr53cxxx.c
1423
if (reg != data && reg != 8 && data != 8)
sys/dev/microcode/siop/ncr53cxxx.c
1425
if (reg == data) { /* A register read/modify/write */
sys/dev/microcode/siop/ncr53cxxx.c
1427
fprintf (listfp, "Read/modify register: %02x %d %d\n", inst0 >> 8, op, reg);
sys/dev/microcode/siop/ncr53cxxx.c
1429
inst0 |= 0x78000000 | (op << 24) | (reg << 16);
sys/dev/microcode/siop/ncr53cxxx.c
1432
if (reg == 8) { /* MOVE SFBR <> TO reg */
sys/dev/microcode/siop/ncr53cxxx.c
1440
fprintf (listfp, "Move register to SFBR: %02x %d %d\n", inst0 >> 8, op, reg);
sys/dev/microcode/siop/ncr53cxxx.c
1442
inst0 |= 0x70000000 | (op << 24) | (reg << 16);
sys/dev/microcode/siop/ncr53cxxx.c
1449
if (reg == 8) /* move SFBR to reg */
sys/dev/microcode/siop/ncr53cxxx.c
1452
inst0 = 0x72000000 | (reg << 16);
sys/dev/mii/acphy.c
144
int reg;
sys/dev/mii/acphy.c
161
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/acphy.c
162
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/amphy.c
134
int reg;
sys/dev/mii/amphy.c
151
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/amphy.c
152
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/atphy.c
348
uint32_t reg;
sys/dev/mii/atphy.c
355
reg = PHY_READ(sc, ATPHY_SCR);
sys/dev/mii/atphy.c
357
reg |= ATPHY_SCR_AUTO_X_MODE;
sys/dev/mii/atphy.c
359
reg &= ~ATPHY_SCR_MAC_PDOWN;
sys/dev/mii/atphy.c
361
reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;
sys/dev/mii/atphy.c
363
reg |= ATPHY_SCR_POLARITY_REVERSAL;
sys/dev/mii/atphy.c
364
PHY_WRITE(sc, ATPHY_SCR, reg);
sys/dev/mii/bmtphy.c
128
int reg;
sys/dev/mii/bmtphy.c
148
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/bmtphy.c
149
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/brgphy.c
1005
int reg;
sys/dev/mii/brgphy.c
1023
for (i = 0; dspcode[i].reg != 0; i++)
sys/dev/mii/brgphy.c
1024
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
sys/dev/mii/brgphy.c
1033
int reg;
sys/dev/mii/brgphy.c
1043
for (i = 0; dspcode[i].reg != 0; i++)
sys/dev/mii/brgphy.c
1044
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
sys/dev/mii/brgphy.c
1070
int reg;
sys/dev/mii/brgphy.c
1079
for (i = 0; dspcode[i].reg != 0; i++)
sys/dev/mii/brgphy.c
1080
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
sys/dev/mii/brgphy.c
1087
int reg;
sys/dev/mii/brgphy.c
1100
for (i = 0; dspcode[i].reg != 0; i++)
sys/dev/mii/brgphy.c
1101
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
sys/dev/mii/brgphy.c
1108
int reg;
sys/dev/mii/brgphy.c
1117
for (i = 0; dspcode[i].reg != 0; i++)
sys/dev/mii/brgphy.c
1118
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
sys/dev/mii/brgphy.c
1125
int reg;
sys/dev/mii/brgphy.c
1140
for (i = 0; dspcode[i].reg != 0; i++)
sys/dev/mii/brgphy.c
1141
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
sys/dev/mii/brgphy.c
1149
int reg;
sys/dev/mii/brgphy.c
1160
for (i = 0; dspcode[i].reg != 0; i++)
sys/dev/mii/brgphy.c
1161
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
sys/dev/mii/brgphy.c
311
int reg, speed = 0, gig;
sys/dev/mii/brgphy.c
331
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/brgphy.c
332
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/brgphy.c
418
reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
sys/dev/mii/brgphy.c
419
if (reg & BMSR_LINK) {
sys/dev/mii/brswphy.c
129
#define SPEED_PORT_FE(reg, port) (((reg) >> (port)) & 1)
sys/dev/mii/brswphy.c
130
#define SPEED_PORT_GE(reg, port) (((reg) >> 2 * (port)) & 3)
sys/dev/mii/brswphy.c
168
static int brswphy_read16(struct mii_softc *sc, uint8_t page, uint8_t reg,
sys/dev/mii/brswphy.c
170
static int brswphy_read32(struct mii_softc *sc, uint8_t page, uint8_t reg,
sys/dev/mii/brswphy.c
172
static int brswphy_op(struct mii_softc *sc, uint8_t page, uint8_t reg,
sys/dev/mii/brswphy.c
234
int reg;
sys/dev/mii/brswphy.c
254
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/brswphy.c
255
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/brswphy.c
334
brswphy_op(struct mii_softc *sc, uint8_t page, uint8_t reg, uint16_t op)
sys/dev/mii/brswphy.c
348
v = (reg << 8) | op;
sys/dev/mii/brswphy.c
366
brswphy_read16(struct mii_softc *sc, uint8_t page, uint8_t reg, uint16_t *val)
sys/dev/mii/brswphy.c
370
ret = brswphy_op(sc, page, reg, REG_MII_ADDR_READ);
sys/dev/mii/brswphy.c
380
brswphy_read32(struct mii_softc *sc, uint8_t page, uint8_t reg, uint32_t *val)
sys/dev/mii/brswphy.c
384
ret = brswphy_op(sc, page, reg, REG_MII_ADDR_READ);
sys/dev/mii/ciphy.c
144
int reg, speed, gig;
sys/dev/mii/ciphy.c
161
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/ciphy.c
162
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/dcphy.c
178
int reg;
sys/dev/mii/dcphy.c
273
reg = CSR_READ_4(dc_sc, DC_10BTSTAT);
sys/dev/mii/dcphy.c
274
if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100)) {
sys/dev/mii/dcphy.c
311
int reg, anlpar, tstat = 0;
sys/dev/mii/dcphy.c
319
reg = CSR_READ_4(dc_sc, DC_10BTSTAT);
sys/dev/mii/dcphy.c
320
if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))
sys/dev/mii/dcphy.c
365
if (!(reg & DC_TSTAT_LS100))
sys/dev/mii/dcphy.c
367
else if (!(reg & DC_TSTAT_LS10))
sys/dev/mii/dcphy.c
67
#define DC_SETBIT(sc, reg, x) \
sys/dev/mii/dcphy.c
68
CSR_WRITE_4(sc, reg, \
sys/dev/mii/dcphy.c
69
CSR_READ_4(sc, reg) | x)
sys/dev/mii/dcphy.c
71
#define DC_CLRBIT(sc, reg, x) \
sys/dev/mii/dcphy.c
72
CSR_WRITE_4(sc, reg, \
sys/dev/mii/dcphy.c
73
CSR_READ_4(sc, reg) & ~x)
sys/dev/mii/eephy.c
152
int reg, page;
sys/dev/mii/eephy.c
181
reg = PHY_READ(sc, E1000_ESSR);
sys/dev/mii/eephy.c
182
if ((reg & E1000_ESSR_HWCFG_MODE) == E1000_ESSR_RGMII_COPPER) {
sys/dev/mii/eephy.c
183
reg |= E1000_ESSR_DIS_FC;
sys/dev/mii/eephy.c
184
PHY_WRITE(sc, E1000_ESSR, reg);
sys/dev/mii/eephy.c
193
reg = PHY_READ(sc, E1000_SCR);
sys/dev/mii/eephy.c
194
reg &= ~E1000_SCR_MODE_MASK;
sys/dev/mii/eephy.c
195
reg |= E1000_SCR_MODE_1000BX;
sys/dev/mii/eephy.c
196
PHY_WRITE(sc, E1000_SCR, reg);
sys/dev/mii/eephy.c
210
reg = PHY_READ(sc, E1000_GCR1);
sys/dev/mii/eephy.c
211
mode = reg & E1000_GCR1_MODE_MASK;
sys/dev/mii/eephy.c
218
reg &= ~E1000_GCR1_MODE_MASK;
sys/dev/mii/eephy.c
219
reg |= E1000_GCR1_RESET | mode;
sys/dev/mii/eephy.c
220
PHY_WRITE(sc, E1000_GCR1, reg);
sys/dev/mii/eephy.c
242
int reg, i;
sys/dev/mii/eephy.c
244
reg = PHY_READ(sc, E1000_CR);
sys/dev/mii/eephy.c
245
reg |= E1000_CR_RESET;
sys/dev/mii/eephy.c
246
PHY_WRITE(sc, E1000_CR, reg);
sys/dev/mii/eephy.c
250
reg = PHY_READ(sc, E1000_CR);
sys/dev/mii/eephy.c
251
if (!(reg & E1000_CR_RESET))
sys/dev/mii/eephy.c
258
reg = PHY_READ(sc, E1000_SCR);
sys/dev/mii/eephy.c
261
reg |= E1000_SCR_ASSERT_CRS_ON_TX;
sys/dev/mii/eephy.c
268
reg |= (E1000_SCR_AUTO_X_MODE >> 1);
sys/dev/mii/eephy.c
273
reg &= ~E1000_SCR_AUTO_X_MODE;
sys/dev/mii/eephy.c
275
reg |= E1000_SCR_AUTO_X_MODE;
sys/dev/mii/eephy.c
281
reg &= ~E3000_SCR_EN_DETECT_MASK;
sys/dev/mii/eephy.c
288
reg &= ~E1000_SCR_EN_DETECT_MASK;
sys/dev/mii/eephy.c
294
reg &= ~E3000_SCR_SCRAMBLER_DISABLE;
sys/dev/mii/eephy.c
301
reg |= E3000_SCR_REG8_NEXT_PAGE;
sys/dev/mii/eephy.c
303
PHY_WRITE(sc, E1000_SCR, reg);
sys/dev/mii/eephy.c
308
reg = PHY_READ(sc, E1000_ESCR);
sys/dev/mii/eephy.c
309
reg |= E1000_ESCR_TX_CLK_25;
sys/dev/mii/eephy.c
310
PHY_WRITE(sc, E1000_ESCR, reg);
sys/dev/mii/eephy.c
316
reg = (0x0b << 8) | (0x05 << 4) | 0x04; /* XXX */
sys/dev/mii/eephy.c
317
PHY_WRITE(sc, 0x16, reg);
sys/dev/mii/eephy.c
323
reg = PHY_READ(sc, E1000_CR);
sys/dev/mii/eephy.c
324
PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET);
sys/dev/mii/eephy.c
465
uint32_t reg = prop[i + 1];
sys/dev/mii/eephy.c
472
val = PHY_READ(sc, reg);
sys/dev/mii/eephy.c
476
PHY_WRITE(sc, reg, val);
sys/dev/mii/gentbi.c
168
int reg;
sys/dev/mii/gentbi.c
185
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/gentbi.c
186
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/icsphy.c
151
int reg;
sys/dev/mii/icsphy.c
171
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/icsphy.c
172
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/inphy.c
151
int reg;
sys/dev/mii/inphy.c
171
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/inphy.c
172
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/iophy.c
146
int reg;
sys/dev/mii/iophy.c
166
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/iophy.c
167
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/ipgphy.c
134
uint32_t gig, reg, speed;
sys/dev/mii/ipgphy.c
151
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/ipgphy.c
152
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/ipgphy.c
237
reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
sys/dev/mii/ipgphy.c
238
if (reg & BMSR_LINK) {
sys/dev/mii/ipgphy.c
352
uint32_t reg = 0;
sys/dev/mii/ipgphy.c
355
reg = PHY_READ(sc, MII_ANAR);
sys/dev/mii/ipgphy.c
356
reg &= ~(ANAR_PAUSE_SYM | ANAR_PAUSE_ASYM);
sys/dev/mii/ipgphy.c
357
reg |= ANAR_NP;
sys/dev/mii/ipgphy.c
360
reg |= ANAR_10 | ANAR_10_FD | ANAR_TX | ANAR_TX_FD;
sys/dev/mii/ipgphy.c
363
reg |= ANAR_PAUSE_SYM | ANAR_PAUSE_ASYM;
sys/dev/mii/ipgphy.c
365
PHY_WRITE(sc, MII_ANAR, reg | ANAR_CSMA);
sys/dev/mii/ipgphy.c
367
reg = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
sys/dev/mii/ipgphy.c
369
reg |= GTCR_ADV_MS;
sys/dev/mii/ipgphy.c
370
PHY_WRITE(sc, MII_100T2CR, reg);
sys/dev/mii/ipgphy.c
396
uint32_t reg;
sys/dev/mii/ipgphy.c
401
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/ipgphy.c
402
reg &= ~(BMCR_AUTOEN | BMCR_FDX);
sys/dev/mii/ipgphy.c
403
PHY_WRITE(sc, MII_BMCR, reg);
sys/dev/mii/lxtphy.c
160
int reg;
sys/dev/mii/lxtphy.c
180
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/lxtphy.c
181
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/mii_bitbang.c
115
int reg)
sys/dev/mii/mii_bitbang.c
124
mii_bitbang_sendbits(sc, ops, reg, 5);
sys/dev/mii/mii_bitbang.c
163
int phy, int reg, int val)
sys/dev/mii/mii_bitbang.c
171
mii_bitbang_sendbits(sc, ops, reg, 5);
sys/dev/mii/mii_physubr.c
235
int reg;
sys/dev/mii/mii_physubr.c
251
reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
sys/dev/mii/mii_physubr.c
252
if (reg & BMSR_LINK) {
sys/dev/mii/mii_physubr.c
284
int reg, i;
sys/dev/mii/mii_physubr.c
287
reg = BMCR_RESET;
sys/dev/mii/mii_physubr.c
289
reg = BMCR_RESET | BMCR_ISO;
sys/dev/mii/mii_physubr.c
290
PHY_WRITE(sc, MII_BMCR, reg);
sys/dev/mii/mii_physubr.c
304
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/mii_physubr.c
305
if ((reg & BMCR_RESET) == 0)
sys/dev/mii/mii_physubr.c
311
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/mlphy.c
206
int other_inst, reg;
sys/dev/mii/mlphy.c
297
reg = PHY_READ(other, MII_BMSR) |
sys/dev/mii/mlphy.c
300
reg = PHY_READ(sc, MII_BMSR) |
sys/dev/mii/mlphy.c
304
if (reg & BMSR_LINK) {
sys/dev/mii/mlphy.c
355
int reg;
sys/dev/mii/mlphy.c
358
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/mlphy.c
359
reg &= ~BMCR_AUTOEN;
sys/dev/mii/mlphy.c
360
PHY_WRITE(sc, MII_BMCR, reg);
sys/dev/mii/mtdphy.c
113
int reg;
sys/dev/mii/mtdphy.c
132
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/mtdphy.c
133
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/nsgphy.c
157
int reg;
sys/dev/mii/nsgphy.c
177
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/nsgphy.c
178
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/nsphy.c
147
int reg;
sys/dev/mii/nsphy.c
167
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/nsphy.c
168
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/nsphy.c
178
reg = PHY_READ(sc, MII_NSPHY_PCR);
sys/dev/mii/nsphy.c
184
reg |= PCR_LED4MODE;
sys/dev/mii/nsphy.c
191
reg |= PCR_CIMDIS;
sys/dev/mii/nsphy.c
197
reg |= PCR_FLINK100;
sys/dev/mii/nsphy.c
204
reg |= PCR_CONGCTRL | PCR_TXREADYSEL;
sys/dev/mii/nsphy.c
206
PHY_WRITE(sc, MII_NSPHY_PCR, reg);
sys/dev/mii/nsphyter.c
150
int reg;
sys/dev/mii/nsphyter.c
170
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/nsphyter.c
171
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/qsphy.c
145
int reg;
sys/dev/mii/qsphy.c
165
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/qsphy.c
166
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/rdcphy.c
165
int reg;
sys/dev/mii/rdcphy.c
185
reg = PHY_READ(&sc->sc_mii, MII_BMCR);
sys/dev/mii/rdcphy.c
186
PHY_WRITE(&sc->sc_mii, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/rgephy.c
153
int anar, reg, speed, gig = 0;
sys/dev/mii/rgephy.c
173
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/rgephy.c
174
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/rgephy.c
261
reg = PHY_READ(sc, RL_GMEDIASTAT);
sys/dev/mii/rgephy.c
262
if (reg & RL_GMEDIASTAT_LINK) {
sys/dev/mii/rgephy.c
269
reg = PHY_READ(sc, RGEPHY_F_SR);
sys/dev/mii/rgephy.c
270
if (reg & RGEPHY_F_SR_LINK) {
sys/dev/mii/rgephy.c
274
reg = PHY_READ(sc, RGEPHY_SR);
sys/dev/mii/rgephy.c
275
if (reg & RGEPHY_SR_LINK) {
sys/dev/mii/sqphy.c
148
int reg;
sys/dev/mii/sqphy.c
168
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/sqphy.c
169
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/tlphy.c
184
int reg;
sys/dev/mii/tlphy.c
207
reg = PHY_READ(&sc->sc_mii, MII_BMCR);
sys/dev/mii/tlphy.c
208
PHY_WRITE(&sc->sc_mii, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/tqphy.c
147
int reg;
sys/dev/mii/tqphy.c
167
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/tqphy.c
168
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/ukphy.c
144
int reg;
sys/dev/mii/ukphy.c
164
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/ukphy.c
165
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/urlphy.c
136
int reg;
sys/dev/mii/urlphy.c
187
reg = PHY_READ(sc, URLPHY_MSR) | PHY_READ(sc, URLPHY_MSR);
sys/dev/mii/urlphy.c
188
if (reg & URLPHY_MSR_LINK) {
sys/dev/mii/xmphy.c
138
int reg;
sys/dev/mii/xmphy.c
158
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/xmphy.c
159
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/mii/xmphy.c
212
reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
sys/dev/mii/xmphy.c
213
if (reg & BMSR_LINK) {
sys/dev/mii/ytphy.c
178
int reg;
sys/dev/mii/ytphy.c
198
reg = PHY_READ(sc, MII_BMCR);
sys/dev/mii/ytphy.c
199
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
sys/dev/ofw/fdt.c
637
fdt_translate_reg(void *node, struct fdt_reg *reg)
sys/dev/ofw/fdt.c
657
return fdt_translate_reg(parent, reg);
sys/dev/ofw/fdt.c
691
if (reg->addr < from || (reg->addr + reg->size) > (from + size))
sys/dev/ofw/fdt.c
699
reg->addr -= from;
sys/dev/ofw/fdt.c
700
reg->addr += to;
sys/dev/ofw/fdt.c
701
return fdt_translate_reg(parent, reg);
sys/dev/ofw/fdt.c
712
fdt_get_reg(void *node, int idx, struct fdt_reg *reg)
sys/dev/ofw/fdt.c
717
if (node == NULL || reg == NULL)
sys/dev/ofw/fdt.c
738
reg->addr = betoh32(in[off]);
sys/dev/ofw/fdt.c
740
reg->addr = (reg->addr << 32) + betoh32(in[off + 1]);
sys/dev/ofw/fdt.c
742
reg->size = betoh32(in[off + ac]);
sys/dev/ofw/fdt.c
744
reg->size = (reg->size << 32) + betoh32(in[off + ac + 1]);
sys/dev/ofw/fdt.c
746
return fdt_translate_reg(parent, reg);
sys/dev/ofw/ofw_misc.c
573
uint32_t reg[2], bits[2] = {};
sys/dev/ofw/ofw_misc.c
579
if (OF_getpropintarray(node, "reg", reg, sizeof(reg)) != sizeof(reg))
sys/dev/ofw/ofw_misc.c
587
nc->nc_addr = reg[0];
sys/dev/ofw/ofw_misc.c
588
nc->nc_size = reg[1];
sys/dev/pci/agp_ali.c
103
pcireg_t reg;
sys/dev/pci/agp_ali.c
132
reg = pci_conf_read(asc->asc_pc, asc->asc_tag, AGP_ALI_ATTBASE);
sys/dev/pci/agp_ali.c
133
reg = (reg & 0xff) | gatt->ag_physical;
sys/dev/pci/agp_ali.c
134
pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_ALI_ATTBASE, reg);
sys/dev/pci/agp_ali.c
137
reg = pci_conf_read(asc->asc_pc, asc->asc_tag, AGP_ALI_TLBCTRL);
sys/dev/pci/agp_ali.c
138
reg = (reg & ~0xff) | 0x10;
sys/dev/pci/agp_ali.c
139
pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_ALI_TLBCTRL, reg);
sys/dev/pci/agp_ali.c
224
pcireg_t reg;
sys/dev/pci/agp_ali.c
232
reg = pci_conf_read(asc->asc_pc, asc->asc_tag, AGP_ALI_ATTBASE);
sys/dev/pci/agp_ali.c
233
reg &= ~0xff;
sys/dev/pci/agp_ali.c
234
reg |= i;
sys/dev/pci/agp_ali.c
235
pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_ALI_ATTBASE, reg);
sys/dev/pci/agp_ali.c
260
pcireg_t reg;
sys/dev/pci/agp_ali.c
262
reg = pci_conf_read(asc->asc_pc, asc->asc_tag, AGP_ALI_TLBCTRL);
sys/dev/pci/agp_ali.c
263
reg &= ~0xff;
sys/dev/pci/agp_ali.c
264
reg |= 0x90;
sys/dev/pci/agp_ali.c
265
pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_ALI_TLBCTRL, reg);
sys/dev/pci/agp_ali.c
266
reg &= ~0xff;
sys/dev/pci/agp_ali.c
267
reg |= 0x10;
sys/dev/pci/agp_ali.c
268
pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_ALI_TLBCTRL, reg);
sys/dev/pci/agp_amd.c
176
pcireg_t reg;
sys/dev/pci/agp_amd.c
218
reg = pci_conf_read(asc->asc_pc, asc->asc_tag, AGP_AMD751_MODECTRL);
sys/dev/pci/agp_amd.c
219
reg &= ~0x00ff00ff;
sys/dev/pci/agp_amd.c
220
reg |= (AGP_AMD751_MODECTRL_SYNEN) | (AGP_AMD751_MODECTRL2_GPDCE << 16);
sys/dev/pci/agp_amd.c
221
pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_AMD751_MODECTRL, reg);
sys/dev/pci/agp_amd.c
298
pcireg_t reg;
sys/dev/pci/agp_amd.c
311
reg = pci_conf_read(asc->asc_pc, asc->asc_tag, AGP_AMD751_APCTRL);
sys/dev/pci/agp_amd.c
312
reg = (reg & ~0x06) | (vas << 1);
sys/dev/pci/agp_amd.c
313
pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_AMD751_APCTRL, reg);
sys/dev/pci/agp_i810.c
233
pcireg_t memtype, reg;
sys/dev/pci/agp_i810.c
342
reg = pci_conf_read(bpa.pa_pc, bpa.pa_tag, AGP_I830_GCC0);
sys/dev/pci/agp_i810.c
343
gcc1 = (u_int16_t)(reg >> 16);
sys/dev/pci/agp_i810.c
391
reg = pci_conf_read(bpa.pa_pc, bpa.pa_tag, AGP_I855_GCC1);
sys/dev/pci/agp_i810.c
392
gcc1 = (u_int16_t)(reg >> 16);
sys/dev/pci/agp_intel.c
135
pcireg_t reg;
sys/dev/pci/agp_intel.c
221
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, AGP_I840_MCHCFG);
sys/dev/pci/agp_intel.c
222
reg |= MCHCFG_AAGN;
sys/dev/pci/agp_intel.c
223
pci_conf_write(pa->pa_pc, pa->pa_tag, AGP_I840_MCHCFG, reg);
sys/dev/pci/agp_intel.c
227
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, AGP_INTEL_AGPCMD);
sys/dev/pci/agp_intel.c
228
reg |= AGPCMD_AGPEN;
sys/dev/pci/agp_intel.c
230
reg);
sys/dev/pci/agp_intel.c
231
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, AGP_I840_MCHCFG);
sys/dev/pci/agp_intel.c
232
reg |= MCHCFG_AAGN;
sys/dev/pci/agp_intel.c
234
reg);
sys/dev/pci/agp_intel.c
237
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, AGP_INTEL_NBXCFG);
sys/dev/pci/agp_intel.c
238
reg &= ~NBXCFG_APAE;
sys/dev/pci/agp_intel.c
239
reg |= NBXCFG_AAGN;
sys/dev/pci/agp_intel.c
240
pci_conf_write(pa->pa_pc, pa->pa_tag, AGP_INTEL_NBXCFG, reg);
sys/dev/pci/agp_intel.c
258
reg = pci_conf_read(isc->isc_pc, isc->isc_tag,
sys/dev/pci/agp_intel.c
261
AGP_INTEL_ERRCMD, reg);
sys/dev/pci/agp_intel.c
447
pcireg_t reg;
sys/dev/pci/agp_intel.c
455
reg = pci_conf_read(isc->isc_pc, isc->isc_tag,
sys/dev/pci/agp_intel.c
457
reg &= ~AGPCTRL_GTLB;
sys/dev/pci/agp_intel.c
459
AGP_INTEL_AGPCTRL, reg);
sys/dev/pci/agp_intel.c
461
reg | AGPCTRL_GTLB);
sys/dev/pci/agp_sis.c
103
pcireg_t reg;
sys/dev/pci/agp_sis.c
137
reg = pci_conf_read(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL);
sys/dev/pci/agp_sis.c
138
reg |= (0x05 << 24) | 3;
sys/dev/pci/agp_sis.c
139
pci_conf_write(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL, reg);
sys/dev/pci/agp_sis.c
204
pcireg_t reg;
sys/dev/pci/agp_sis.c
217
reg = pci_conf_read(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL);
sys/dev/pci/agp_sis.c
218
reg &= ~0x00000070;
sys/dev/pci/agp_sis.c
219
reg |= gws << 4;
sys/dev/pci/agp_sis.c
220
pci_conf_write(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL, reg);
sys/dev/pci/agp_sis.c
246
pcireg_t reg;
sys/dev/pci/agp_sis.c
248
reg = pci_conf_read(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_TLBFLUSH);
sys/dev/pci/agp_sis.c
249
reg &= 0xffffff00;
sys/dev/pci/agp_sis.c
250
reg |= 0x02;
sys/dev/pci/agp_sis.c
251
pci_conf_write(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_TLBFLUSH, reg);
sys/dev/pci/agp_via.c
256
pcireg_t reg;
sys/dev/pci/agp_via.c
269
reg = pci_conf_read(vsc->vsc_pc, vsc->vsc_tag, vsc->regs[REG_APSIZE]);
sys/dev/pci/agp_via.c
270
reg &= ~0xff;
sys/dev/pci/agp_via.c
271
reg |= apsize;
sys/dev/pci/agp_via.c
272
pci_conf_write(vsc->vsc_pc, vsc->vsc_tag, vsc->regs[REG_APSIZE], reg);
sys/dev/pci/ahd_pci.c
943
u_int reg;
sys/dev/pci/ahd_pci.c
957
for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
sys/dev/pci/ahd_pci.c
961
pci_status[i] = ahd_inb(ahd, reg);
sys/dev/pci/ahd_pci.c
963
ahd_outb(ahd, reg, pci_status[i]);
sys/dev/pci/alipm.c
143
pcireg_t iobase, reg;
sys/dev/pci/alipm.c
147
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
sys/dev/pci/alipm.c
148
if ((reg & PCI_STATUS_CAPLIST_SUPPORT) == 0) {
sys/dev/pci/alipm.c
159
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, ALIPM_CONF);
sys/dev/pci/alipm.c
160
if ((reg & ALIPM_CONF_SMBEN) == 0) {
sys/dev/pci/alipm.c
165
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, ALIPM_SMB_HOSTC);
sys/dev/pci/alipm.c
166
if ((reg & ALIPM_SMB_HOSTC_HSTEN) == 0) {
sys/dev/pci/alipm.c
178
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, ALIPM_SMB_HOSTX);
sys/dev/pci/alipm.c
179
if ((reg & ALIPM_SMB_HOSTC_HSTEN) == 0) {
sys/dev/pci/alipm.c
185
switch (reg & ALIPM_SMB_HOSTC_CLOCK) {
sys/dev/pci/amas.c
60
#define AMAS_REG_BL_ADDR(reg) (((reg) >> 16) & 0xffff)
sys/dev/pci/amdiic.c
192
amdiic_read(struct amdiic_softc *sc, u_int8_t reg)
sys/dev/pci/amdiic.c
200
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMD8111_SMB_SC_DATA, reg);
sys/dev/pci/amdiic.c
208
amdiic_write(struct amdiic_softc *sc, u_int8_t reg, u_int8_t val)
sys/dev/pci/amdiic.c
216
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AMD8111_SMB_SC_DATA, reg);
sys/dev/pci/amdpcib.c
114
pcireg_t reg;
sys/dev/pci/amdpcib.c
119
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, AMD8111_HPET);
sys/dev/pci/amdpcib.c
120
if (reg & AMD8111_HPET_ENA &&
sys/dev/pci/amdpcib.c
121
bus_space_map(sc->sc_hpet_iot, reg & AMD8111_HPET_BASE,
sys/dev/pci/amdpm.c
216
pcireg_t cfg_reg, reg;
sys/dev/pci/amdpm.c
232
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, AMDPM_PMPTR);
sys/dev/pci/amdpm.c
233
if (AMDPM_PMBASE(reg) == 0 ||
sys/dev/pci/amdpm.c
234
bus_space_map(sc->sc_iot, AMDPM_PMBASE(reg), AMDPM_PMSIZE,
sys/dev/pci/amdpm.c
287
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, NFPM_PMPTR);
sys/dev/pci/amdpm.c
288
if (AMDPM_PMBASE(reg) == 0 ||
sys/dev/pci/amdpm.c
289
bus_space_map(sc->sc_iot, AMDPM_PMBASE(reg), AMDPM_SMB_SIZE, 0,
sys/dev/pci/amdpm.c
341
u_int32_t reg;
sys/dev/pci/amdpm.c
345
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, AMDPM_RNGDATA);
sys/dev/pci/amdpm.c
346
enqueue_randomness(reg);
sys/dev/pci/arc.c
1025
u_int32_t reg, intrstat, obmsg, error;
sys/dev/pci/arc.c
1045
reg = arc_read(sc, ARC_RD_OUTB_DOORBELL);
sys/dev/pci/arc.c
1046
arc_write(sc, ARC_RD_OUTB_DOORBELL, reg);
sys/dev/pci/arc.c
1047
if (reg & ARC_RD_I2D_DATA_WRITE_OK) {
sys/dev/pci/arc.c
1056
if (reg & ARC_RD_I2D_MESSAGE_CMD_DONE) {
sys/dev/pci/arc.c
1077
reg = pmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
sys/dev/pci/arc.c
1078
cmd = (struct arc_io_cmd *)(kva + ((reg & 0xFFFFFFF0) -
sys/dev/pci/arc.c
1084
error = (reg & ARC_RD_REPLY_QUEUE_ERR);
sys/dev/pci/arc.c
1121
u_int32_t reg, cdb_len;
sys/dev/pci/arc.c
1148
reg = ccb->ccb_cmd_post;
sys/dev/pci/arc.c
1177
reg |= ARC_RA_POST_QUEUE_BIGFRAME;
sys/dev/pci/arc.c
1178
arc_write(sc, ARC_RA_POST_QUEUE, reg);
sys/dev/pci/arc.c
1185
reg = reg | ((cdb_len - 1) >> 6) | 1;
sys/dev/pci/arc.c
1188
arc_write(sc, ARC_RC_INB_POSTQ_LOW, reg);
sys/dev/pci/arc.c
1332
u_int32_t reg, error, write_ptr;
sys/dev/pci/arc.c
1341
reg = arc_read(sc, ARC_RA_REPLY_QUEUE);
sys/dev/pci/arc.c
1342
error = (reg & ARC_RA_REPLY_QUEUE_ERR)? 1:0;
sys/dev/pci/arc.c
1345
reg = arc_read(sc, ARC_RC_OUTB_REPLYQ_LOW);
sys/dev/pci/arc.c
1346
error = (reg & ARC_RC_REPLY_QUEUE_ERR);
sys/dev/pci/arc.c
1354
reg = 0xffffffff;
sys/dev/pci/arc.c
1358
reg = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
sys/dev/pci/arc.c
1359
if (reg == 0)
sys/dev/pci/arc.c
1363
error = (reg & ARC_RD_REPLY_QUEUE_ERR);
sys/dev/pci/arc.c
1366
if (reg == 0xffffffff) {
sys/dev/pci/arc.c
1377
((reg << ARC_RA_REPLY_QUEUE_ADDR_SHIFT) -
sys/dev/pci/arc.c
1382
cmd = (struct arc_io_cmd *)(kva + ((reg & 0xFFFFFFE0) -
sys/dev/pci/arc.c
2274
u_int32_t reg, rwlen, write_ok, read_ok;
sys/dev/pci/arc.c
2285
reg = arc_read(sc, ARC_RA_OUTB_DOORBELL);
sys/dev/pci/arc.c
2288
reg = arc_read(sc, ARC_RC_OUTB_DOORBELL);
sys/dev/pci/arc.c
2291
reg = arc_read(sc, ARC_RD_OUTB_DOORBELL);
sys/dev/pci/arc.c
2369
while ((reg = arc_read(sc, ARC_RA_OUTB_DOORBELL)) == 0)
sys/dev/pci/arc.c
2371
arc_write(sc, ARC_RA_OUTB_DOORBELL, reg);
sys/dev/pci/arc.c
2372
write_ok = reg & ARC_RA_OUTB_DOORBELL_WRITE_OK;
sys/dev/pci/arc.c
2373
read_ok = reg & ARC_RA_OUTB_DOORBELL_READ_OK;
sys/dev/pci/arc.c
2376
while ((reg = arc_read(sc, ARC_RC_OUTB_DOORBELL)) == 0)
sys/dev/pci/arc.c
2378
arc_write(sc, ARC_RC_OUTB_DOORBELL_CLR, reg);
sys/dev/pci/arc.c
2379
write_ok = reg & ARC_RC_I2D_DATA_WRITE_OK;
sys/dev/pci/arc.c
2380
read_ok = reg & ARC_RC_I2D_DATA_READ_OK;
sys/dev/pci/arc.c
2383
while ((reg = arc_read(sc, ARC_RD_OUTB_DOORBELL)) == 0)
sys/dev/pci/arc.c
2385
arc_write(sc, ARC_RD_OUTB_DOORBELL_CLR, reg);
sys/dev/pci/arc.c
2386
write_ok = reg & ARC_RD_I2D_DATA_WRITE_OK;
sys/dev/pci/arc.c
2387
read_ok = reg & ARC_RD_I2D_DATA_READ_OK;
sys/dev/pci/arc.c
2390
DNPRINTF(ARC_D_DB, "%s: reg: 0x%08x\n", DEVNAME(sc), reg);
sys/dev/pci/arc.c
878
u_int32_t reg, intrstat, error;
sys/dev/pci/arc.c
895
reg = arc_read(sc, ARC_RA_OUTB_DOORBELL);
sys/dev/pci/arc.c
896
arc_write(sc, ARC_RA_OUTB_DOORBELL, reg);
sys/dev/pci/arc.c
897
if (reg & ARC_RA_OUTB_DOORBELL_WRITE_OK)
sys/dev/pci/arc.c
904
while ((reg = arc_read(sc, ARC_RA_REPLY_QUEUE)) != 0xffffffff) {
sys/dev/pci/arc.c
907
((reg << ARC_RA_REPLY_QUEUE_ADDR_SHIFT) -
sys/dev/pci/arc.c
915
error = (reg & ARC_RA_REPLY_QUEUE_ERR)? 1:0;
sys/dev/pci/arc.c
929
u_int32_t reg, intrstat, obmsg, error;
sys/dev/pci/arc.c
946
reg = arc_read(sc, ARC_RC_OUTB_DOORBELL);
sys/dev/pci/arc.c
947
arc_write(sc, ARC_RC_OUTB_DOORBELL_CLR, reg);
sys/dev/pci/arc.c
948
if (reg & ARC_RC_I2D_DATA_WRITE_OK) {
sys/dev/pci/arc.c
957
if (reg & ARC_RC_I2D_MESSAGE_CMD_DONE) {
sys/dev/pci/arc.c
973
reg = arc_read(sc, ARC_RC_OUTB_REPLYQ_LOW);
sys/dev/pci/arc.c
974
cmd = (struct arc_io_cmd *)(kva + ((reg & 0xFFFFFFE0) -
sys/dev/pci/arc.c
982
error = (reg & ARC_RC_REPLY_QUEUE_ERR);
sys/dev/pci/auacer.c
299
auacer_read_codec(void *v, u_int8_t reg, u_int16_t *val)
sys/dev/pci/auacer.c
306
reg |= ALI_CPR_ADDR_READ;
sys/dev/pci/auacer.c
309
reg |= ALI_CPR_ADDR_SECONDARY;
sys/dev/pci/auacer.c
311
WRITE2(sc, ALI_CPR_ADDR, reg);
sys/dev/pci/auacer.c
317
reg, *val));
sys/dev/pci/auacer.c
323
auacer_write_codec(void *v, u_int8_t reg, u_int16_t val)
sys/dev/pci/auacer.c
328
reg, val));
sys/dev/pci/auacer.c
335
reg |= ALI_CPR_ADDR_SECONDARY;
sys/dev/pci/auacer.c
337
WRITE2(sc, ALI_CPR_ADDR, reg);
sys/dev/pci/auacer.c
355
u_int32_t reg;
sys/dev/pci/auacer.c
358
reg = READ4(sc, ALI_SCR);
sys/dev/pci/auacer.c
359
if ((reg & 2) == 0) /* Cold required */
sys/dev/pci/auacer.c
360
reg |= 2;
sys/dev/pci/auacer.c
362
reg |= 1; /* Warm */
sys/dev/pci/auacer.c
363
reg &= ~0x80000000; /* ACLink on */
sys/dev/pci/auacer.c
364
WRITE4(sc, ALI_SCR, reg);
sys/dev/pci/auacer.c
377
reg = READ4(sc, ALI_RTSR);
sys/dev/pci/auacer.c
378
if (reg & 0x80) /* primary codec */
sys/dev/pci/auacer.c
380
WRITE4(sc, ALI_RTSR, reg | 0x80);
sys/dev/pci/auglx.c
332
auglx_read_codec(void *v, u_int8_t reg, u_int16_t *val)
sys/dev/pci/auglx.c
338
codec_cntl = RW_CMD | ((u_int32_t)reg << 24) | CMD_NEW;
sys/dev/pci/auglx.c
357
if ((codec_status & STS_NEW) && (codec_status >> 24 == reg))
sys/dev/pci/auglx.c
369
sc->sc_dev.dv_xname, reg, *val));
sys/dev/pci/auglx.c
374
auglx_write_codec(void *v, u_int8_t reg, u_int16_t val)
sys/dev/pci/auglx.c
381
sc->sc_dev.dv_xname, reg, val));
sys/dev/pci/auglx.c
384
codec_cntl = ((u_int32_t)reg << 24) | CMD_NEW | val;
sys/dev/pci/auich.c
538
auich_read_codec(void *v, u_int8_t reg, u_int16_t *val)
sys/dev/pci/auich.c
553
*val = bus_space_read_2(sc->iot_mix, sc->mix_ioh, reg);
sys/dev/pci/auich.c
555
sc->sc_dev.dv_xname, reg, *val));
sys/dev/pci/auich.c
560
auich_write_codec(void *v, u_int8_t reg, u_int16_t val)
sys/dev/pci/auich.c
571
sc->sc_dev.dv_xname, reg, val));
sys/dev/pci/auich.c
572
bus_space_write_2(sc->iot_mix, sc->mix_ioh, reg, val);
sys/dev/pci/auixp.c
1124
auixp_read_codec(void *aux, u_int8_t reg, u_int16_t *result)
sys/dev/pci/auixp.c
1141
data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
sys/dev/pci/auixp.c
1157
reg, data >> ATI_REG_PHYS_IN_DATA_SHIFT));
sys/dev/pci/auixp.c
1165
if (reg < 0x7c)
sys/dev/pci/auixp.c
1167
sc->sc_dev.dv_xname, reg);
sys/dev/pci/auixp.c
1173
auixp_write_codec(void *aux, u_int8_t reg, u_int16_t data)
sys/dev/pci/auixp.c
1181
DPRINTF(("write ac'97 codec reg 0x%x = 0x%08x\n", reg, data));
sys/dev/pci/auixp.c
1191
(((u_int32_t) reg) << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
sys/dev/pci/autri.c
1026
u_int32_t reg, cr[5];
sys/dev/pci/autri.c
1138
reg = TREAD4(sc,AUTRI_LFO_GC_CIR) & ~0x0000003f;
sys/dev/pci/autri.c
1139
TWRITE4(sc,AUTRI_LFO_GC_CIR, reg | channel);
sys/dev/pci/autri.c
1259
int reg;
sys/dev/pci/autri.c
1261
reg = (ch & 0x20) ? AUTRI_AINTEN_B : AUTRI_AINTEN_A;
sys/dev/pci/autri.c
1264
autri_reg_set_4(sc, reg, 1 << ch);
sys/dev/pci/autri.c
1270
int reg;
sys/dev/pci/autri.c
1272
reg = (ch & 0x20) ? AUTRI_AINTEN_B : AUTRI_AINTEN_A;
sys/dev/pci/autri.c
1275
autri_reg_clear_4(sc, reg, 1 << ch);
sys/dev/pci/autri.c
1281
int reg;
sys/dev/pci/autri.c
1284
reg = (ch & 0x20) ? AUTRI_START_B : AUTRI_START_A;
sys/dev/pci/autri.c
1288
autri_reg_set_4(sc, reg, chmask);
sys/dev/pci/autri.c
1294
int reg;
sys/dev/pci/autri.c
1297
reg = (ch & 0x20) ? AUTRI_STOP_B : AUTRI_STOP_A;
sys/dev/pci/autri.c
1301
autri_reg_set_4(sc, reg, chmask);
sys/dev/pci/autri.c
355
u_int32_t reg, ready;
sys/dev/pci/autri.c
410
reg = TREAD4(sc, addr);
sys/dev/pci/autri.c
411
if (reg & ready)
sys/dev/pci/autri.c
588
pcireg_t reg;
sys/dev/pci/autri.c
601
reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
sys/dev/pci/autri.c
602
pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & 0xffff0000);
sys/dev/pci/autri.c
605
reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
sys/dev/pci/autri.c
606
pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg | 0x00040000);
sys/dev/pci/autri.c
609
reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
sys/dev/pci/autri.c
610
pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & ~0x00040000);
sys/dev/pci/autri.c
618
reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
sys/dev/pci/autri.c
619
pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & 0xffff0000);
sys/dev/pci/autri.c
622
reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
sys/dev/pci/autri.c
623
pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg | 0x00010000);
sys/dev/pci/autri.c
626
reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
sys/dev/pci/autri.c
627
pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & ~0x00010000);
sys/dev/pci/autri.c
635
reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
sys/dev/pci/autri.c
636
pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & 0xffff0000);
sys/dev/pci/autri.c
639
reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
sys/dev/pci/autri.c
640
pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg | 0x000c0000);
sys/dev/pci/autri.c
643
reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
sys/dev/pci/autri.c
644
pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & ~0x00040000);
sys/dev/pci/autri.c
654
reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
sys/dev/pci/autri.c
655
pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & 0xffff0000);
sys/dev/pci/autri.c
658
reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
sys/dev/pci/autri.c
659
pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg | 0x000c0000);
sys/dev/pci/autri.c
662
reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);
sys/dev/pci/autri.c
663
pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & ~0x00040000);
sys/dev/pci/autri.c
707
u_int32_t reg;
sys/dev/pci/autri.c
710
reg = ENDLP_IE;
sys/dev/pci/autri.c
713
reg |= BANK_B_EN;
sys/dev/pci/autri.c
715
autri_reg_set_4(sc,AUTRI_LFO_GC_CIR,reg);
sys/dev/pci/autri.c
723
u_int32_t reg;
sys/dev/pci/autri.c
725
reg = (ENDLP_IE | MIDLP_IE);
sys/dev/pci/autri.c
726
autri_reg_clear_4(sc,AUTRI_LFO_GC_CIR,reg);
sys/dev/pci/autri.c
769
reg = TREAD4(sc,AUTRI_LFO_GC_CIR) & ~0x0000003f;
sys/dev/pci/autri.c
770
TWRITE4(sc,AUTRI_LFO_GC_CIR, reg | ch);
sys/dev/pci/auvia.c
422
auvia_write_codec(void *addr, u_int8_t reg, u_int16_t val)
sys/dev/pci/auvia.c
430
AUVIA_CODEC_PRIVALID | AUVIA_CODEC_INDEX(reg) | val);
sys/dev/pci/auvia.c
437
auvia_read_codec(void *addr, u_int8_t reg, u_int16_t *val)
sys/dev/pci/auvia.c
445
AUVIA_CODEC_PRIVALID | AUVIA_CODEC_READ | AUVIA_CODEC_INDEX(reg));
sys/dev/pci/auvia.c
538
int reg, mode;
sys/dev/pci/auvia.c
550
reg = AC97_REG_PCM_FRONT_DAC_RATE;
sys/dev/pci/auvia.c
554
reg = AC97_REG_PCM_LR_ADC_RATE;
sys/dev/pci/auvia.c
600
if (codec->vtbl->set_rate(codec, reg, &p->sample_rate))
sys/dev/pci/auvia.c
605
reg = AC97_REG_PCM_SURR_DAC_RATE;
sys/dev/pci/auvia.c
607
&& codec->vtbl->set_rate(codec, reg,
sys/dev/pci/auvia.c
610
reg = AC97_REG_PCM_LFE_DAC_RATE;
sys/dev/pci/auvia.c
612
&& codec->vtbl->set_rate(codec, reg,
sys/dev/pci/azalia.c
341
azalia_pci_read(pci_chipset_tag_t pc, pcitag_t pa, int reg)
sys/dev/pci/azalia.c
343
return (pci_conf_read(pc, pa, (reg & ~0x03)) >>
sys/dev/pci/azalia.c
344
((reg & 0x03) * 8) & 0xff);
sys/dev/pci/azalia.c
348
azalia_pci_write(pci_chipset_tag_t pc, pcitag_t pa, int reg, uint8_t val)
sys/dev/pci/azalia.c
352
pcival = pci_conf_read(pc, pa, (reg & ~0x03));
sys/dev/pci/azalia.c
353
pcival &= ~(0xff << ((reg & 0x03) * 8));
sys/dev/pci/azalia.c
354
pcival |= (val << ((reg & 0x03) * 8));
sys/dev/pci/azalia.c
355
pci_conf_write(pc, pa, (reg & ~0x03), pcival);
sys/dev/pci/azalia.c
362
uint8_t reg;
sys/dev/pci/azalia.c
383
reg = azalia_pci_read(az->pc, az->tag, ATI_PCIE_SNOOP_REG);
sys/dev/pci/azalia.c
384
reg &= ATI_PCIE_SNOOP_MASK;
sys/dev/pci/azalia.c
385
reg |= ATI_PCIE_SNOOP_ENABLE;
sys/dev/pci/azalia.c
386
azalia_pci_write(az->pc, az->tag, ATI_PCIE_SNOOP_REG, reg);
sys/dev/pci/azalia.c
410
reg = azalia_pci_read(az->pc, az->tag,
sys/dev/pci/azalia.c
412
reg |= NVIDIA_HDA_STR_COH_ENABLE;
sys/dev/pci/azalia.c
414
NVIDIA_HDA_OSTR_COH_REG, reg);
sys/dev/pci/azalia.c
416
reg = azalia_pci_read(az->pc, az->tag,
sys/dev/pci/azalia.c
418
reg |= NVIDIA_HDA_STR_COH_ENABLE;
sys/dev/pci/azalia.c
420
NVIDIA_HDA_ISTR_COH_REG, reg);
sys/dev/pci/azalia.c
422
reg = azalia_pci_read(az->pc, az->tag,
sys/dev/pci/azalia.c
424
reg &= NVIDIA_PCIE_SNOOP_MASK;
sys/dev/pci/azalia.c
425
reg |= NVIDIA_PCIE_SNOOP_ENABLE;
sys/dev/pci/azalia.c
427
NVIDIA_PCIE_SNOOP_REG, reg);
sys/dev/pci/azalia.c
429
reg = azalia_pci_read(az->pc, az->tag,
sys/dev/pci/azalia.c
431
if ((reg & NVIDIA_PCIE_SNOOP_ENABLE) !=
sys/dev/pci/azalia.c
486
reg = azalia_pci_read(az->pc, az->tag,
sys/dev/pci/azalia.c
488
reg &= INTEL_PCIE_NOSNOOP_MASK;
sys/dev/pci/azalia.c
490
INTEL_PCIE_NOSNOOP_REG, reg);
sys/dev/pci/azalia.c
537
uint8_t reg;
sys/dev/pci/azalia.c
565
reg = azalia_pci_read(sc->pc, sc->tag, ICH_PCI_MMC);
sys/dev/pci/azalia.c
566
reg &= ~(ICH_PCI_MMC_ME);
sys/dev/pci/azalia.c
567
azalia_pci_write(sc->pc, sc->tag, ICH_PCI_MMC, reg);
sys/dev/pci/berkwdt.c
137
u_int8_t reg;
sys/dev/pci/berkwdt.c
142
reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PCWD_PCI_CS2);
sys/dev/pci/berkwdt.c
143
if (reg & WD_PCI_WDIS) {
sys/dev/pci/berkwdt.c
151
u_int8_t reg;
sys/dev/pci/berkwdt.c
158
reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PCWD_PCI_CS2);
sys/dev/pci/berkwdt.c
159
if (!(reg & WD_PCI_WDIS)) {
sys/dev/pci/berkwdt.c
183
u_int8_t reg;
sys/dev/pci/berkwdt.c
193
reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PCWD_PCI_CS1);
sys/dev/pci/berkwdt.c
194
if (reg & WD_PCI_WTRP) {
sys/dev/pci/berkwdt.c
197
if (reg & WD_PCI_TTRP)
sys/dev/pci/berkwdt.c
201
reg &= WD_PCI_R2DS;
sys/dev/pci/berkwdt.c
202
reg |= WD_PCI_WTRP;
sys/dev/pci/berkwdt.c
203
bus_space_write_1(sc->sc_iot, sc->sc_ioh, PCWD_PCI_CS1, reg);
sys/dev/pci/cac_pci.c
160
pcireg_t reg;
sys/dev/pci/cac_pci.c
176
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, i);
sys/dev/pci/cac_pci.c
178
if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) {
sys/dev/pci/cac_pci.c
179
if (ior == -1 && PCI_MAPREG_IO_SIZE(reg) != 0)
sys/dev/pci/cac_pci.c
182
if (memr == -1 && PCI_MAPREG_MEM_SIZE(reg) != 0)
sys/dev/pci/ciss_pci.c
140
pcireg_t reg;
sys/dev/pci/ciss_pci.c
151
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
sys/dev/pci/ciss_pci.c
152
if (PCI_VENDOR(reg) == PCI_VENDOR_COMPAQ &&
sys/dev/pci/ciss_pci.c
153
(PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA5I ||
sys/dev/pci/ciss_pci.c
154
PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA532 ||
sys/dev/pci/ciss_pci.c
155
PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA5312))
sys/dev/pci/com_pci.c
32
#define HREAD4(sc, reg) \
sys/dev/pci/com_pci.c
33
(bus_space_read_4((sc)->sc.sc_iot, (sc)->sc.sc_ioh, (reg)))
sys/dev/pci/com_pci.c
34
#define HWRITE4(sc, reg, val) \
sys/dev/pci/com_pci.c
35
bus_space_write_4((sc)->sc.sc_iot, (sc)->sc.sc_ioh, (reg), (val))
sys/dev/pci/com_pci.c
36
#define HSET4(sc, reg, bits) \
sys/dev/pci/com_pci.c
37
HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
sys/dev/pci/com_pci.c
38
#define HCLR4(sc, reg, bits) \
sys/dev/pci/com_pci.c
39
HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
sys/dev/pci/cy82c693.c
76
cy82c693_read(const struct cy82c693_handle *cyhc, int reg)
sys/dev/pci/cy82c693.c
83
bus_space_write_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 0, reg);
sys/dev/pci/cy82c693.c
90
cy82c693_write(const struct cy82c693_handle *cyhc, int reg, u_int8_t val)
sys/dev/pci/cy82c693.c
95
bus_space_write_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 0, reg);
sys/dev/pci/cz.c
201
#define CZ_PLX_READ(cz, reg) \
sys/dev/pci/cz.c
202
bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg))
sys/dev/pci/cz.c
203
#define CZ_PLX_WRITE(cz, reg, val) \
sys/dev/pci/cz.c
205
(reg), (val))
sys/dev/pci/cz.c
211
#define CZ_FPGA_READ(cz, reg) \
sys/dev/pci/cz.c
212
bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg))
sys/dev/pci/cz.c
213
#define CZ_FPGA_WRITE(cz, reg, val) \
sys/dev/pci/cz.c
214
bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val))
sys/dev/pci/cz.c
441
u_int32_t reg;
sys/dev/pci/cz.c
443
reg = CZ_PLX_READ(cz, PLX_CONTROL);
sys/dev/pci/cz.c
444
CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR);
sys/dev/pci/cz.c
447
CZ_PLX_WRITE(cz, PLX_CONTROL, reg);
sys/dev/pci/cz.c
451
reg = CZ_PLX_READ(cz, PLX_CONTROL);
sys/dev/pci/cz.c
452
CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG);
sys/dev/pci/cz.c
454
CZ_PLX_WRITE(cz, PLX_CONTROL, reg);
sys/dev/pci/czreg.h
221
#define ZFIRM_CHNCTL_OFF(chan, reg) \
sys/dev/pci/czreg.h
222
(ZFIRM_BRDCTL_SIZE + ((chan) * ZFIRM_CHNCTL_SIZE) + (reg))
sys/dev/pci/czreg.h
223
#define ZFIRM_BUFCTL_OFF(chan, reg) \
sys/dev/pci/czreg.h
225
((chan) * ZFIRM_BUFCTL_SIZE) + (reg))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1412
uint32_t reg, uint32_t acc_flags);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1416
uint32_t reg, uint32_t acc_flags,
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1419
uint32_t reg, uint32_t v,
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1424
uint32_t reg, uint32_t v,
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1428
uint32_t reg, uint32_t v, uint32_t xcc_id);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1467
#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1468
#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1470
#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0)
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1471
#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0)
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1473
#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1474
#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1476
#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1477
#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1478
#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1481
#define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst)
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1482
#define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst)
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1483
#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1484
#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1485
#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1486
#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1487
#define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1488
#define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1489
#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1490
#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1491
#define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1492
#define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1493
#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1494
#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1495
#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1496
#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1497
#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1498
#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1499
#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1500
#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1501
#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1502
#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1503
#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1504
#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1505
#define WREG32_P(reg, val, mask) \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1507
uint32_t tmp_ = RREG32(reg); \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1510
WREG32(reg, tmp_); \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1512
#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1513
#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1514
#define WREG32_PLL_P(reg, val, mask) \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1516
uint32_t tmp_ = RREG32_PLL(reg); \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1519
WREG32_PLL(reg, tmp_); \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1530
#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1532
#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1533
#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1535
#define REG_SET_FIELD(orig_val, reg, field, field_val) \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1536
(((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1537
(REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1539
#define REG_GET_FIELD(value, reg, field) \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1540
(((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1542
#define WREG32_FIELD(reg, field, val) \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1543
WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1545
#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1546
WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1635
u32 reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu.h
1637
u32 reg, u32 v);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
198
uint32_t i = 0, reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
206
for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
207
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
208
for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
209
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
210
for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
211
reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
212
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
213
for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
214
reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
215
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
134
uint32_t i = 0, reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
148
for (reg = regSDMA_RLC0_RB_CNTL; reg <= regSDMA_RLC0_DOORBELL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
149
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
150
for (reg = regSDMA_RLC0_STATUS; reg <= regSDMA_RLC0_CSA_ADDR_HI; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
151
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
152
for (reg = regSDMA_RLC0_IB_SUB_REMAIN;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
153
reg <= regSDMA_RLC0_MINOR_PTR_UPDATE; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
154
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
155
for (reg = regSDMA_RLC0_MIDCMD_DATA0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
156
reg <= regSDMA_RLC0_MIDCMD_CNTL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
157
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
227
unsigned int reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
260
reg = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
274
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX), reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
291
uint32_t reg, hqd_base, hqd_end, data;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
302
for (reg = hqd_base; reg <= hqd_end; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
303
WREG32_XCC(reg, mqd_hqd[reg - hqd_base], inst);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
215
uint32_t reg, hqd_base, data;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
226
for (reg = hqd_base;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
227
reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
228
WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
346
uint32_t i = 0, reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
361
for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
362
reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
363
DUMP_REG(reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
448
uint32_t i = 0, reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
456
for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
457
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
458
for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
459
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
460
for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
461
reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
462
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
463
for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
464
reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
465
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
186
uint32_t reg, hqd_base, data;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
212
for (reg = hqd_base;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
213
reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
214
WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
332
uint32_t i = 0, reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
347
for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
348
reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
349
DUMP_REG(reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
434
uint32_t i = 0, reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
442
for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
443
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
444
for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
445
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
446
for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
447
reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
448
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
449
for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
450
reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
451
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
171
uint32_t reg, hqd_base, data;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
197
for (reg = hqd_base;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
198
reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
199
WREG32(reg, mqd_hqd[reg - hqd_base]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
317
uint32_t i = 0, reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
332
for (reg = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
333
reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
334
DUMP_REG(reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
419
uint32_t i = 0, reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
427
for (reg = regSDMA0_QUEUE0_RB_CNTL;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
428
reg <= regSDMA0_QUEUE0_RB_WPTR_HI; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
429
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
430
for (reg = regSDMA0_QUEUE0_RB_RPTR_ADDR_HI;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
431
reg <= regSDMA0_QUEUE0_DOORBELL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
432
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
433
for (reg = regSDMA0_QUEUE0_DOORBELL_LOG;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
434
reg <= regSDMA0_QUEUE0_DOORBELL_LOG; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
435
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
436
for (reg = regSDMA0_QUEUE0_DOORBELL_OFFSET;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
437
reg <= regSDMA0_QUEUE0_RB_PREEMPT; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
438
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
439
for (reg = regSDMA0_QUEUE0_MIDCMD_DATA0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
440
reg <= regSDMA0_QUEUE0_MIDCMD_CNTL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
441
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
109
uint32_t i = 0, reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
124
for (reg = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
125
reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
126
DUMP_REG(reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
142
uint32_t i = 0, reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
153
for (reg = first_reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
154
reg <= last_reg; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
155
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
166
uint32_t reg, wptr_val, data;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
176
for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
177
WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
208
uint32_t i = 0, reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
228
for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
229
DUMP_REG(reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
300
uint32_t i = 0, reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
308
for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
309
DUMP_REG(sdma_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
310
for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
311
reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
312
DUMP_REG(sdma_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
161
uint32_t reg, wptr_val, data;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
186
for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
187
WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
200
for (reg = mmCP_HQD_EOP_EVENTS; reg <= mmCP_HQD_ERROR; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
201
WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
232
uint32_t i = 0, reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
252
for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
253
DUMP_REG(reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
323
uint32_t i = 0, reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
331
for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
332
DUMP_REG(sdma_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
333
for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
334
reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
335
DUMP_REG(sdma_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
336
for (reg = mmSDMA0_RLC0_CSA_ADDR_LO; reg <= mmSDMA0_RLC0_CSA_ADDR_HI;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
337
reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
338
DUMP_REG(sdma_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
339
for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg <= mmSDMA0_RLC0_DUMMY_REG;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
340
reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
341
DUMP_REG(sdma_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
342
for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg <= mmSDMA0_RLC0_MIDCMD_CNTL;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
343
reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
344
DUMP_REG(sdma_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
230
uint32_t reg, hqd_base, data;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
240
for (reg = hqd_base;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
241
reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
242
WREG32_XCC(reg, mqd_hqd[reg - hqd_base], inst);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
357
uint32_t i = 0, reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
372
for (reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
373
reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
374
DUMP_REG(reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
459
uint32_t i = 0, reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
467
for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
468
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
469
for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
470
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
471
for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
472
reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
473
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
474
for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
475
reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
476
DUMP_REG(sdma_rlc_reg_offset + reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1726
static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1740
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1754
static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1768
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1782
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1786
WREG32(reg, val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1798
static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
1803
r = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
204
gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
223
u32 reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
227
reg = amdgpu_display_hpd_get_gpio_reg(adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
230
if (gpio->reg == reg) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1292
static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1294
dev_err(adev->dev, "Invalid callback to read register 0x%04X\n", reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1299
static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1301
dev_err(adev->dev, "Invalid callback to read register 0x%llX\n", reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1316
static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1319
"Invalid callback to write register 0x%04X with 0x%08X\n", reg,
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1324
static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1327
"Invalid callback to write register 0x%llX with 0x%08X\n", reg,
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1342
static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1345
reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1350
static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t reg)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1352
dev_err(adev->dev, "Invalid callback to read register 0x%llX\n", reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1367
static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1371
reg, v);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1375
static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, uint64_t v)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1379
reg, v);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1395
uint32_t block, uint32_t reg)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1399
reg, block);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1417
uint32_t reg, uint32_t v)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1421
reg, block, v);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1517
u32 tmp, reg, and_mask, or_mask;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1524
reg = registers[i + 0];
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1531
tmp = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1538
WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1788
uint32_t reg, flags;
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1835
reg = amdgpu_asic_get_config_memsize(adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
1837
if ((reg != 0) && (reg != 0xffffffff))
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
728
uint32_t reg, uint32_t acc_flags)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
735
if ((reg * 4) < adev->rmmio_size) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
739
ret = amdgpu_kiq_rreg(adev, reg, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
742
ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
745
ret = adev->pcie_rreg(adev, reg * 4);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
748
trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7581
u32 reg)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7590
WREG32(address, reg * 4);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7598
u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
7606
WREG32(address, reg * 4);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
788
uint32_t reg, uint32_t acc_flags,
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
796
if ((reg * 4) < adev->rmmio_size) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
803
ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, GET_INST(GC, xcc_id));
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
807
ret = amdgpu_kiq_rreg(adev, reg, xcc_id);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
810
ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
813
ret = adev->pcie_rreg(adev, reg * 4);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
856
uint32_t reg, uint32_t v,
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
862
if ((reg * 4) < adev->rmmio_size) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
866
amdgpu_kiq_wreg(adev, reg, v, 0);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
869
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
872
adev->pcie_wreg(adev, reg * 4, v);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
875
trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
889
uint32_t reg, uint32_t v,
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
898
if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
899
return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
900
} else if ((reg * 4) >= adev->rmmio_size) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
901
adev->pcie_wreg(adev, reg * 4, v);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
903
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
919
uint32_t reg, uint32_t v,
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
927
if ((reg * 4) < adev->rmmio_size) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
934
amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, GET_INST(GC, xcc_id));
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
938
amdgpu_kiq_wreg(adev, reg, v, xcc_id);
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
941
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
944
adev->pcie_wreg(adev, reg * 4, v);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
1060
uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
1072
return amdgpu_mes_rreg(adev, reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
1085
amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
1130
dev_err(adev->dev, "failed to read reg:%x\n", reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
1134
void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id)
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
1148
amdgpu_mes_wreg(adev, reg, v);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
1157
amdgpu_ring_emit_wreg(ring, reg, v);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
1197
dev_err(adev->dev, "failed to write reg:%x\n", reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
616
uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.h
617
void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
959
u32 tmp, reg, i;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
963
reg = hub->vm_context0_cntl + hub->ctx_distance * i;
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
966
RREG32_SOC15_IP(GC, reg) :
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
967
RREG32_SOC15_IP(MMHUB, reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
975
WREG32_SOC15_IP(GC, reg, tmp) :
sys/dev/pci/drm/amd/amdgpu/amdgpu_gmc.c
976
WREG32_SOC15_IP(MMHUB, reg, tmp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_imu.h
45
u32 reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_imu.h
50
#define IMU_RLC_RAM_GOLDEN_VALUE(ip, inst, reg, data, addr_mask) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_imu.h
51
{ ip##_HWIP, inst, reg##_BASE_IDX, reg, data, addr_mask }
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
467
const struct amdgpu_hwip_reg_entry *reg, u32 count)
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
476
adev->jpeg.reg_list = reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
547
static inline bool amdgpu_jpeg_reg_valid(u32 reg)
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
549
if (reg < JPEG_REG_RANGE_START || reg > JPEG_REG_RANGE_END ||
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
550
(reg >= JPEG_ATOMIC_RANGE_START && reg <= JPEG_ATOMIC_RANGE_END))
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
571
u32 i, reg, res, cond, type;
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
575
reg = CP_PACKETJ_GET_REG(ib->ptr[i]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
586
!amdgpu_jpeg_reg_valid(reg)) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.c
593
!amdgpu_jpeg_reg_valid(reg)) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h
177
const struct amdgpu_hwip_reg_entry *reg, u32 count);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
439
uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg)
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
454
op_input.read_reg.reg_offset = reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
466
dev_err(adev->dev, "failed to read reg (0x%x)\n", reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
477
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
483
op_input.write_reg.reg_offset = reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.c
496
dev_err(adev->dev, "failed to write reg (0x%x)\n", reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
427
uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mes.h
429
uint32_t reg, uint32_t val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_mode.h
567
u32 reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
1299
int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
1305
if (reg >= PSP_REG_LAST)
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
1310
psp_prep_reg_prog_cmd_buf(cmd, reg, value);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
1313
dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.h
587
int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
386
#define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.h
387
(adev->reg_offset[hwip][ip_inst][segment] + (reg))
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
273
void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
275
void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ring.h
276
void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/amdgpu_rlc.h
261
bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h
39
TP_PROTO(unsigned did, uint32_t reg, uint32_t value),
sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h
40
TP_ARGS(did, reg, value),
sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h
43
__field(uint32_t, reg)
sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h
48
__entry->reg = reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h
53
(unsigned long)__entry->reg,
sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h
58
TP_PROTO(unsigned did, uint32_t reg, uint32_t value),
sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h
59
TP_ARGS(did, reg, value),
sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h
62
__field(uint32_t, reg)
sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h
67
__entry->reg = reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_trace.h
72
(unsigned long)__entry->reg,
sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h
200
#define WREG32_SOC15_UMSCH(reg, value) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_umsch_mm.h
202
uint32_t reg_offset = adev->reg_offset[VCN_HWIP][0][reg##_BASE_IDX] + reg; \
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
1002
unsigned int reg = ctx->reg + i;
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
1009
switch (reg) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
1025
DRM_ERROR("Invalid reg 0x%X!\n", reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
1052
ctx->reg = CP_PACKET0_GET_REG(cmd);
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
99
unsigned int reg, count;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
1560
const struct amdgpu_hwip_reg_entry *reg, u32 count)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.c
1566
adev->vcn.reg_list = reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
101
#define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
106
addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
162
#define SOC24_DPG_MODE_OFFSET(ip, inst_idx, reg) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
167
addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
565
const struct amdgpu_hwip_reg_entry *reg, u32 count);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
80
#define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
84
((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
90
#define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
96
((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
746
uint32_t reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
751
reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
761
reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
764
reg = 0;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
768
if (reg & 1)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
771
if (reg & 0x80000000)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
774
if (!reg) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
780
return reg;
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
783
static bool amdgpu_virt_init_req_data(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
849
uint32_t reg = amdgpu_virt_init_detect_asic(adev);
sys/dev/pci/drm/amd/amdgpu/amdgpu_virt.c
851
is_sriov = amdgpu_virt_init_req_data(adev, reg);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
587
static void vpe_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
592
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
596
static void vpe_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
605
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/atom.h
122
u32 reg, uint32_t val); /* filled by driver */
sys/dev/pci/drm/amd/amdgpu/atom.h
123
uint32_t (*reg_read)(struct card_info *info, uint32_t reg); /* filled by driver */
sys/dev/pci/drm/amd/amdgpu/atom.h
125
u32 reg, uint32_t val); /* filled by driver */
sys/dev/pci/drm/amd/amdgpu/atom.h
126
uint32_t (*mc_read)(struct card_info *info, uint32_t reg); /* filled by driver */
sys/dev/pci/drm/amd/amdgpu/atom.h
128
u32 reg, uint32_t val); /* filled by driver */
sys/dev/pci/drm/amd/amdgpu/atom.h
129
uint32_t (*pll_read)(struct card_info *info, uint32_t reg); /* filled by driver */
sys/dev/pci/drm/amd/amdgpu/cik.c
152
static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/cik.c
158
WREG32(mmPCIE_INDEX, reg);
sys/dev/pci/drm/amd/amdgpu/cik.c
165
static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/cik.c
170
WREG32(mmPCIE_INDEX, reg);
sys/dev/pci/drm/amd/amdgpu/cik.c
177
static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/cik.c
183
WREG32(mmSMC_IND_INDEX_0, (reg));
sys/dev/pci/drm/amd/amdgpu/cik.c
189
static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/cik.c
194
WREG32(mmSMC_IND_INDEX_0, (reg));
sys/dev/pci/drm/amd/amdgpu/cik.c
199
static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/cik.c
205
WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
sys/dev/pci/drm/amd/amdgpu/cik.c
211
static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/cik.c
216
WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
sys/dev/pci/drm/amd/amdgpu/cik.c
221
static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/cik.c
227
WREG32(mmDIDT_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/cik.c
233
static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/cik.c
238
WREG32(mmDIDT_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
866
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
869
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/cikd.h
220
#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
sys/dev/pci/drm/amd/amdgpu/cikd.h
221
((reg) & 0xFFFF) | \
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
103
.reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
108
.reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
113
.reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
118
.reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
173
u32 block_offset, u32 reg)
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
179
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
187
u32 block_offset, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
192
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3147
u32 reg;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3154
reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3157
reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3160
reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3268
uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
3314
disp_int = RREG32(interrupt_status_offsets[hpd].reg);
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
87
uint32_t reg;
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
93
.reg = mmDISP_INTERRUPT_STATUS,
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
98
.reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
104
.reg = mmDISP_INTERRUPT_STATUS,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
109
.reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
114
.reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
119
.reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
124
.reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
129
.reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
136
u32 block_offset, u32 reg)
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
142
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
150
u32 block_offset, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
156
reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3085
uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3122
u32 reg;
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3129
reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3132
reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3135
reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
3206
disp_int = RREG32(interrupt_status_offsets[hpd].reg);
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
98
uint32_t reg;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
102
.reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
107
.reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
112
.reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
117
.reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
124
u32 block_offset, u32 reg)
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
130
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
138
u32 block_offset, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
143
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3101
uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3138
u32 reg;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3145
reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3148
reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3151
reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
3222
disp_int = RREG32(interrupt_status_offsets[hpd].reg);
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
86
uint32_t reg;
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
92
.reg = mmDISP_INTERRUPT_STATUS,
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
97
.reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4001
bool wc, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4006
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8301
u32 reg, pre_data, data;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8303
reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8306
pre_data = RREG32_NO_KIQ(reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8308
pre_data = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8335
uint32_t reg;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8344
reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8345
if (offset == reg)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8987
static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8996
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9004
static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9022
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9027
static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9030
gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9652
uint32_t i, j, k, reg, index = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9677
for (reg = 0; reg < reg_count; reg++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9678
if (i && gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9681
adev->gfx.ip_dump_compute_queues[index + reg]);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9684
gc_cp_reg_list_10[reg].reg_name,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9685
adev->gfx.ip_dump_compute_queues[index + reg]);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9707
for (reg = 0; reg < reg_count; reg++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9709
gc_gfx_queue_reg_list_10[reg].reg_name,
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9710
adev->gfx.ip_dump_gfx_queues[index + reg]);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9721
uint32_t i, j, k, reg, index = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9745
for (reg = 0; reg < reg_count; reg++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9746
if (i && gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9747
adev->gfx.ip_dump_compute_queues[index + reg] =
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9750
adev->gfx.ip_dump_compute_queues[index + reg] =
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9752
gc_cp_reg_list_10[reg]));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9775
for (reg = 0; reg < reg_count; reg++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9776
adev->gfx.ip_dump_gfx_queues[index + reg] =
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9778
gc_gfx_queue_reg_list_10[reg]));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
336
static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
511
bool wc, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
516
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5573
u32 reg, pre_data, data;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5576
reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5578
pre_data = RREG32_NO_KIQ(reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5580
pre_data = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5598
amdgpu_ring_emit_wreg(ring, reg, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6252
static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6261
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6269
static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6287
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6292
static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6295
gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7021
uint32_t i, j, k, reg, index = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7046
for (reg = 0; reg < reg_count; reg++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7047
if (i && gc_cp_reg_list_11[reg].reg_offset == regCP_MEC_ME1_HEADER_DUMP)
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7050
adev->gfx.ip_dump_compute_queues[index + reg]);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7053
gc_cp_reg_list_11[reg].reg_name,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7054
adev->gfx.ip_dump_compute_queues[index + reg]);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7076
for (reg = 0; reg < reg_count; reg++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7078
gc_gfx_queue_reg_list_11[reg].reg_name,
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7079
adev->gfx.ip_dump_gfx_queues[index + reg]);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7090
uint32_t i, j, k, reg, index = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7113
for (reg = 0; reg < reg_count; reg++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7115
gc_cp_reg_list_11[reg].reg_offset ==
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7117
adev->gfx.ip_dump_compute_queues[index + reg] =
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7121
adev->gfx.ip_dump_compute_queues[index + reg] =
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7123
gc_cp_reg_list_11[reg]));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7146
for (reg = 0; reg < reg_count; reg++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7147
adev->gfx.ip_dump_gfx_queues[index + reg] =
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7149
gc_gfx_queue_reg_list_11[reg]));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
281
static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3961
u32 reg, data;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3963
reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3965
data = RREG32_NO_KIQ(reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3967
data = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3981
uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3982
amdgpu_ring_emit_wreg(ring, reg, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4636
static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4645
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4654
uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4672
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4677
static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4680
gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5105
uint32_t i, j, k, reg, index = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5130
for (reg = 0; reg < reg_count; reg++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5132
gc_cp_reg_list_12[reg].reg_name,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5133
adev->gfx.ip_dump_compute_queues[index + reg]);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5155
for (reg = 0; reg < reg_count; reg++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5157
gc_gfx_queue_reg_list_12[reg].reg_name,
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5158
adev->gfx.ip_dump_gfx_queues[index + reg]);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5169
uint32_t i, j, k, reg, index = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5192
for (reg = 0; reg < reg_count; reg++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5193
adev->gfx.ip_dump_compute_queues[index + reg] =
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5195
gc_cp_reg_list_12[reg]));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5218
for (reg = 0; reg < reg_count; reg++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5219
adev->gfx.ip_dump_gfx_queues[index + reg] =
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5221
gc_gfx_queue_reg_list_12[reg]));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2342
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2349
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3180
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3187
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6306
static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6315
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6323
static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6342
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1161
bool wc, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1167
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5157
u32 reg, data;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5159
reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5161
data = RREG32_NO_KIQ(reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5188
uint32_t reg;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5197
reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5198
if (offset == reg)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5857
static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5866
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5874
static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5892
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5897
static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5900
gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
6947
const struct soc15_reg_entry *reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
6955
if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset ||
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
6956
gfx_v9_0_ras_fields[i].seg != reg->seg ||
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
6957
gfx_v9_0_ras_fields[i].inst != reg->inst)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7252
uint32_t i, j, k, reg, index = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7277
for (reg = 0; reg < reg_count; reg++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7278
if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7281
adev->gfx.ip_dump_compute_queues[index + reg]);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7284
gc_cp_reg_list_9[reg].reg_name,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7285
adev->gfx.ip_dump_compute_queues[index + reg]);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7297
uint32_t i, j, k, reg, index = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7321
for (reg = 0; reg < reg_count; reg++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7322
if (i && gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7323
adev->gfx.ip_dump_compute_queues[index + reg] =
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7326
adev->gfx.ip_dump_compute_queues[index + reg] =
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7328
gc_cp_reg_list_9[reg]));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
827
const struct soc15_reg_entry *reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
836
if (gfx_v9_4_ras_fields[i].reg_offset != reg->reg_offset ||
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
837
gfx_v9_4_ras_fields[i].seg != reg->seg ||
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
838
gfx_v9_4_ras_fields[i].inst != reg->inst)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1463
const struct soc15_reg_entry *reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1472
if (gfx_v9_4_2_ras_fields[i].reg_offset != reg->reg_offset ||
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1473
gfx_v9_4_2_ras_fields[i].seg != reg->seg ||
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1474
gfx_v9_4_2_ras_fields[i].inst != reg->inst)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1818
WREG32_SOC15_RLC_EX(reg, GC, 0, regSQ_IND_INDEX,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
883
WREG32_SOC15_RLC_SHADOW_EX(reg, GC, 0, regGRBM_GFX_INDEX, data);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1672
u32 reg, pre_data, data;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1674
reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1676
pre_data = RREG32_NO_KIQ(reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1678
pre_data = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1701
uint32_t reg;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1714
reg = adev->reg_offset[entry->hwip][inst][entry->segment] +
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1715
entry->reg;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1716
if (offset == reg)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2992
static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2997
reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3003
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3011
static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3016
reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3031
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3036
static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3039
gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
361
static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
363
uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
372
return reg;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
376
bool wc, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
378
reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
383
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4580
uint32_t num_xcc, reg, num_inst;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4620
for (reg = 0; reg < reg_count; reg++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4621
if (i && gc_cp_reg_list_9_4_3[reg].reg_offset ==
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4628
reg]);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4632
gc_cp_reg_list_9_4_3[reg].reg_name,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4635
reg]);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4648
uint32_t num_xcc, reg, num_inst;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4683
for (reg = 0; reg < reg_count; reg++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4684
if (i && gc_cp_reg_list_9_4_3[reg].reg_offset ==
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4688
inst_offset + reg] =
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4694
inst_offset + reg] =
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4696
gc_cp_reg_list_9_4_3[reg],
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
713
WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data);
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
426
uint32_t reg;
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
429
reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
431
reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
433
amdgpu_ring_emit_wreg(ring, reg, pasid);
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
418
uint32_t reg;
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
421
reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
423
reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
425
amdgpu_ring_emit_wreg(ring, reg, pasid);
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
454
uint32_t reg;
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
457
reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
459
reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
461
amdgpu_ring_emit_wreg(ring, reg, pasid);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
363
uint32_t reg;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
367
reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
369
reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8);
sys/dev/pci/drm/amd/amdgpu/gmc_v6_0.c
370
amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
480
uint32_t reg;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
483
reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
485
reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c
486
amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
671
uint32_t reg;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
674
reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
676
reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
sys/dev/pci/drm/amd/amdgpu/gmc_v8_0.c
677
amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1037
uint32_t reg;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1044
reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1046
reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1048
amdgpu_ring_emit_wreg(ring, reg, pasid);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
417
u32 bits, i, tmp, reg;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
430
reg = ecc_umc_mcumc_ctrl_addrs[i];
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
431
tmp = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
433
WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
436
reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
437
tmp = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
439
WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
444
reg = ecc_umc_mcumc_ctrl_addrs[i];
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
445
tmp = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
447
WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
450
reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
451
tmp = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
453
WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
469
u32 tmp, reg, bits, i, j;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
484
reg = hub->vm_context0_cntl + i;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
495
tmp = RREG32_SOC15_IP(MMHUB, reg);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
497
tmp = RREG32_XCC(reg, j);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
502
WREG32_SOC15_IP(MMHUB, reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
504
WREG32_XCC(reg, tmp, j);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
512
reg = hub->vm_context0_cntl + i;
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
523
tmp = RREG32_SOC15_IP(MMHUB, reg);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
525
tmp = RREG32_XCC(reg, j);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
530
WREG32_SOC15_IP(MMHUB, reg, tmp);
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
532
WREG32_XCC(reg, tmp, j);
sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c
329
u32 reg, data;
sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c
334
reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c
335
reg |= entry->addr_mask;
sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c
338
if (entry->reg == regGCMC_VM_AGP_BASE)
sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c
340
else if (entry->reg == regGCMC_VM_AGP_TOP)
sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c
342
else if (entry->reg == regGCMC_VM_FB_LOCATION_BASE)
sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c
344
else if (entry->reg == regGCMC_VM_FB_LOCATION_TOP)
sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c
348
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg);
sys/dev/pci/drm/amd/amdgpu/imu_v11_0_3.c
112
u32 reg, data;
sys/dev/pci/drm/amd/amdgpu/imu_v11_0_3.c
117
reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
sys/dev/pci/drm/amd/amdgpu/imu_v11_0_3.c
118
reg |= entry->addr_mask;
sys/dev/pci/drm/amd/amdgpu/imu_v11_0_3.c
121
if (entry->reg == regGCMC_VM_AGP_BASE)
sys/dev/pci/drm/amd/amdgpu/imu_v11_0_3.c
123
else if (entry->reg == regGCMC_VM_AGP_TOP)
sys/dev/pci/drm/amd/amdgpu/imu_v11_0_3.c
125
else if (entry->reg == regGCMC_VM_FB_LOCATION_BASE)
sys/dev/pci/drm/amd/amdgpu/imu_v11_0_3.c
127
else if (entry->reg == regGCMC_VM_FB_LOCATION_TOP)
sys/dev/pci/drm/amd/amdgpu/imu_v11_0_3.c
131
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg);
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
262
u32 reg, data;
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
267
reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
268
reg |= entry->addr_mask;
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
270
if (entry->reg == regGCMC_VM_AGP_BASE)
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
272
else if (entry->reg == regGCMC_VM_AGP_TOP)
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
274
else if (entry->reg == regGCMC_VM_FB_LOCATION_BASE)
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
276
else if (entry->reg == regGCMC_VM_FB_LOCATION_TOP)
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
280
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg);
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
306
u32 reg, u32 data)
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
308
if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_LOCATION_BASE))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
310
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_LOCATION_TOP))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
312
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_OFFSET))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
314
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_BASE))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
316
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_BOT))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
318
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_TOP))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
320
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
322
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
324
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
326
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
328
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_END))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
330
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
332
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
334
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
336
else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB))
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
346
u32 reg, data, val_h = 0, val_l = TRANSFER_RAM_MASK;
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
353
reg = regs[i + 0];
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
355
data = imu_v12_init_gfxhub_settings(adev, reg, data);
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
356
if (reg == SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX)) {
sys/dev/pci/drm/amd/amdgpu/imu_v12_0.c
361
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg | val_l);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
121
reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
122
reg_offset = (reg << 2);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
127
reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
128
reg_offset = (reg << 2);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
354
uint32_t reg, uint32_t val,
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
358
uint32_t reg_offset = (reg << 2);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
399
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
402
uint32_t reg_offset = (reg << 2);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
61
uint32_t reg, reg_offset, val, mask, i;
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
637
u32 i, reg, res, cond, type;
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
64
reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
642
reg = CP_PACKETJ_GET_REG(ib->ptr[i]);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
65
reg_offset = (reg << 2);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
650
if (reg >= JPEG_V1_REG_RANGE_START && reg <= JPEG_V1_REG_RANGE_END)
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
655
if (reg != JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_HIGH &&
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
656
reg != JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_LOW &&
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
657
reg != JPEG_V1_LMI_JPEG_READ_64BIT_BAR_HIGH &&
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
658
reg != JPEG_V1_LMI_JPEG_READ_64BIT_BAR_LOW &&
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
659
reg != JPEG_V1_REG_CTX_INDEX &&
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
660
reg != JPEG_V1_REG_CTX_DATA) {
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
665
if (reg != JPEG_V1_REG_CTX_DATA)
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
669
if (reg != JPEG_V1_REG_SOFT_RESET)
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
70
reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
71
reg_offset = (reg << 2);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
82
reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
83
reg_offset = (reg << 2);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
88
reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
89
reg_offset = (reg << 2);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
94
reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
95
reg_offset = (reg << 2);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
613
void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
616
uint32_t reg_offset = (reg << 2);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
655
void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
657
uint32_t reg_offset = (reg << 2);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.h
54
void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.h
58
void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
886
void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
893
reg = NORMALIZE_JPEG_REG_OFFSET(reg);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
895
reg_offset = (reg << 2);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
934
void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
940
reg = NORMALIZE_JPEG_REG_OFFSET(reg);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
942
reg_offset = (reg << 2);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.h
70
void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.h
71
void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
404
u32 reg, data, mask;
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
409
reg = SOC15_REG_OFFSET(JPEG, jpeg_inst, regJPEG_SYS_INT_EN);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
413
WREG32_P(reg, data, mask);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
417
WREG32_P(reg, data, mask);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
392
uint32_t value, reg;
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
455
reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
459
reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
464
WREG32(reg, value);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
467
if (!(RREG32(reg) & value))
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
417
uint32_t value, reg;
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
480
reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
484
reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
489
WREG32(reg, value);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
492
if (!(RREG32(reg) & value))
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
758
const struct soc15_reg_entry *reg,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
765
if (mmhub_v1_0_ras_fields[i].reg_offset != reg->reg_offset)
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
1232
const struct soc15_reg_entry *reg,
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
1241
if(mmhub_v1_7_ras_fields[i].reg_offset != reg->reg_offset)
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
1593
const struct soc15_reg_entry *reg,
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
1602
if (mmhub_v9_4_ras_fields[i].reg_offset != reg->reg_offset)
sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h
130
#define MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h
132
init_table, (reg), \
sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h
138
#define MMSCH_V1_0_INSERT_DIRECT_WT(reg, value) { \
sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h
140
init_table, (reg), \
sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h
146
#define MMSCH_V1_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
sys/dev/pci/drm/amd/amdgpu/mmsch_v1_0.h
148
init_table, (reg), \
sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h
314
#define MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h
316
init_table, (reg), \
sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h
322
#define MMSCH_V2_0_INSERT_DIRECT_WT(reg, value) { \
sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h
324
init_table, (reg), \
sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h
330
#define MMSCH_V2_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
sys/dev/pci/drm/amd/amdgpu/mmsch_v2_0.h
332
init_table, (reg), \
sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h
103
#define MMSCH_V3_0_INSERT_DIRECT_WT(reg, value) { \
sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h
106
direct_wt.cmd_header.reg_offset = reg; \
sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h
113
#define MMSCH_V3_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h
116
direct_poll.cmd_header.reg_offset = reg; \
sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h
92
#define MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
sys/dev/pci/drm/amd/amdgpu/mmsch_v3_0.h
95
direct_rd_mod_wt.cmd_header.reg_offset = reg; \
sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h
104
#define MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h
107
direct_rd_mod_wt.cmd_header.reg_offset = reg; \
sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h
115
#define MMSCH_V4_0_INSERT_DIRECT_WT(reg, value) { \
sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h
118
direct_wt.cmd_header.reg_offset = reg; \
sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h
125
#define MMSCH_V4_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
sys/dev/pci/drm/amd/amdgpu/mmsch_v4_0.h
128
direct_poll.cmd_header.reg_offset = reg; \
sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h
103
#define MMSCH_V5_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h
106
direct_rd_mod_wt.cmd_header.reg_offset = reg; \
sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h
114
#define MMSCH_V5_0_INSERT_DIRECT_WT(reg, value) { \
sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h
117
direct_wt.cmd_header.reg_offset = reg; \
sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h
124
#define MMSCH_V5_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
sys/dev/pci/drm/amd/amdgpu/mmsch_v5_0.h
127
direct_poll.cmd_header.reg_offset = reg; \
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
121
u32 reg;
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
140
reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
142
reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0,
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
145
reg);
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
66
u32 reg;
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
68
reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
70
if (reg != event)
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
85
u8 reg;
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
88
reg = RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE);
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
89
if (reg & 2)
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
65
u32 reg;
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
67
reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
68
if (reg == IDH_FAIL)
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
70
if (reg == IDH_UNRECOV_ERR_NOTIFICATION)
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
72
else if (reg != event)
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
88
u8 reg;
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
91
reg = RREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE);
sys/dev/pci/drm/amd/amdgpu/mxgpu_nv.c
92
if (reg & 2)
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
321
u32 reg;
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
325
reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
326
reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
327
WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
330
reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
331
while (reg & mask) {
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
339
reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
345
u32 reg;
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
347
reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
348
reg = REG_SET_FIELD(reg, MAILBOX_CONTROL,
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
350
WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
356
u32 reg;
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
358
reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
359
reg = REG_SET_FIELD(reg, MAILBOX_MSGBUF_TRN_DW0,
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
361
WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
369
u32 reg;
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
374
reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
375
if (!(reg & mask))
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
379
reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
380
if (reg != event)
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
393
u32 reg;
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
395
reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
396
while (!(reg & mask)) {
sys/dev/pci/drm/amd/amdgpu/mxgpu_vi.c
405
reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
112
u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
117
u32 doorbell_range = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
131
WREG32(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
137
u32 reg = instance ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE) :
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
140
u32 doorbell_range = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
152
WREG32(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
533
uint32_t reg, reg_data;
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
538
reg = RREG32_SOC15(NBIO, 0, mmBIF_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
542
if ((reg & BIF_RB_CNTL__RB_ENABLE_MASK) == 0) {
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
543
reg = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
544
if (reg & BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK) {
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
102
WREG32(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
91
u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
94
u32 doorbell_range = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
101
WREG32(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
70
u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
73
u32 doorbell_range = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
81
WREG32(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
87
u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_0.c
89
u32 doorbell_range = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
109
WREG32_PCIE_PORT(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
116
u32 reg = instance == 0 ?
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
120
u32 doorbell_range = RREG32_PCIE_PORT(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
133
WREG32_PCIE_PORT(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
139
u32 reg;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
142
reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
143
reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
146
WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
68
u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_CSDMA_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
69
u32 doorbell_range = RREG32_PCIE_PORT(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
84
WREG32_PCIE_PORT(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
91
u32 reg = instance == 0 ?
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
94
u32 doorbell_range = RREG32_PCIE_PORT(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
111
u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
112
u32 doorbell_range = RREG32_PCIE_PORT(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
127
WREG32_PCIE_PORT(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
133
u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
134
u32 doorbell_range = RREG32_PCIE_PORT(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
147
WREG32_PCIE_PORT(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
153
u32 reg;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
155
reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
156
reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
159
WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
141
u32 reg, doorbell_range;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
144
reg = instance +
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
159
reg = instance + 0x4 + 0x1 +
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
163
reg = instance + 0x4 +
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
168
doorbell_range = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
176
WREG32(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
182
u32 reg;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
187
reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE_ALDE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
189
reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
191
reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
193
doorbell_range = RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
205
WREG32(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
104
WREG32_PCIE_PORT(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
110
u32 reg;
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
112
reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
113
reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
116
WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
68
u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_CSDMA_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
69
u32 doorbell_range = RREG32_PCIE_PORT(reg);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
84
WREG32_PCIE_PORT(reg, doorbell_range);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
90
u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
91
u32 doorbell_range = RREG32_PCIE_PORT(reg);
sys/dev/pci/drm/amd/amdgpu/nv.c
278
static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/nv.c
287
WREG32(address, (reg));
sys/dev/pci/drm/amd/amdgpu/nv.c
293
static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/nv.c
301
WREG32(address, (reg));
sys/dev/pci/drm/amd/amdgpu/nvd.h
39
#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
sys/dev/pci/drm/amd/amdgpu/nvd.h
40
((reg) & 0xFFFF) | \
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
301
uint32_t reg;
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
303
reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000);
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
304
return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
804
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
808
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1077
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1081
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1723
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1727
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1731
static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1734
sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1319
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1323
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1327
static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1330
sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1298
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1302
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1306
static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1312
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1219
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1223
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1227
static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1233
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1222
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1226
amdgpu_ring_write(ring, reg);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1230
static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1236
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1222
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1228
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1232
static void sdma_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1238
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/si.c
1032
static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/si.c
1038
WREG32(AMDGPU_PCIE_INDEX, reg);
sys/dev/pci/drm/amd/amdgpu/si.c
1045
static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/si.c
1050
WREG32(AMDGPU_PCIE_INDEX, reg);
sys/dev/pci/drm/amd/amdgpu/si.c
1057
static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/si.c
1063
WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
sys/dev/pci/drm/amd/amdgpu/si.c
1070
static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/si.c
1075
WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
sys/dev/pci/drm/amd/amdgpu/si.c
1082
static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/si.c
1088
WREG32(mmSMC_IND_INDEX_0, (reg));
sys/dev/pci/drm/amd/amdgpu/si.c
1094
static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/si.c
1099
WREG32(mmSMC_IND_INDEX_0, (reg));
sys/dev/pci/drm/amd/amdgpu/si.c
1104
static u32 si_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/si.c
1110
WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
sys/dev/pci/drm/amd/amdgpu/si.c
1116
static void si_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/si.c
1121
WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
sys/dev/pci/drm/amd/amdgpu/si.c
2384
static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/si.c
2390
WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
sys/dev/pci/drm/amd/amdgpu/si.c
2396
static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/si.c
2401
WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
sys/dev/pci/drm/amd/amdgpu/si.c
2406
static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/si.c
2412
WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
sys/dev/pci/drm/amd/amdgpu/si.c
2418
static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/si.c
2423
WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
sys/dev/pci/drm/amd/amdgpu/si_dma.c
469
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/si_dma.c
472
amdgpu_ring_write(ring, (0xf << 16) | reg);
sys/dev/pci/drm/amd/amdgpu/sid.h
327
#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
sys/dev/pci/drm/amd/amdgpu/sid.h
328
((reg) & 0xFFFF) | \
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
117
uint32_t reg = 0;
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
119
reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
120
reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
121
reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
122
reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
128
reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE,
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
130
reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
132
WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CON, reg);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
176
uint32_t reg, reg_c_tx_abrt_source;
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
187
reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
189
} while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
195
reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
197
if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) {
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
274
u32 bytes_sent, reg, ret = I2C_OK;
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
298
reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
299
if (!REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) {
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
310
reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT,
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
318
reg = REG_SET_FIELD(reg,
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
323
reg = REG_SET_FIELD(reg,
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
328
reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 0);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
329
WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
384
uint32_t reg = 0;
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
389
reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 0);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
391
reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 1);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
397
reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD,
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
401
reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD,
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
404
WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
422
reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
423
data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
445
uint32_t reg = 0;
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
448
reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
449
WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
452
reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ABORT, 1);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
453
WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
51
uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
53
reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0);
sys/dev/pci/drm/amd/amdgpu/smu_v11_0_i2c.c
54
WREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT, reg);
sys/dev/pci/drm/amd/amdgpu/soc15.c
240
static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/soc15.c
249
WREG32(address, ((reg) & 0x1ff));
sys/dev/pci/drm/amd/amdgpu/soc15.c
255
static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/soc15.c
263
WREG32(address, ((reg) & 0x1ff));
sys/dev/pci/drm/amd/amdgpu/soc15.c
268
static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/soc15.c
277
WREG32(address, (reg));
sys/dev/pci/drm/amd/amdgpu/soc15.c
283
static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/soc15.c
291
WREG32(address, (reg));
sys/dev/pci/drm/amd/amdgpu/soc15.c
296
static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/soc15.c
302
WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/soc15.c
308
static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/soc15.c
313
WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/soc15.c
318
static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/soc15.c
324
WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/soc15.c
330
static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/soc15.c
335
WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/soc15.c
476
u32 tmp, reg;
sys/dev/pci/drm/amd/amdgpu/soc15.c
481
reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
sys/dev/pci/drm/amd/amdgpu/soc15.c
487
RREG32_SOC15_IP(GC, reg) : RREG32(reg);
sys/dev/pci/drm/amd/amdgpu/soc15.c
493
if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
sys/dev/pci/drm/amd/amdgpu/soc15.c
494
reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
sys/dev/pci/drm/amd/amdgpu/soc15.c
495
reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
sys/dev/pci/drm/amd/amdgpu/soc15.c
496
reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
sys/dev/pci/drm/amd/amdgpu/soc15.c
497
WREG32_RLC(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/soc15.c
500
WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
sys/dev/pci/drm/amd/amdgpu/soc15.h
100
#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
sys/dev/pci/drm/amd/amdgpu/soc15.h
101
{ ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
sys/dev/pci/drm/amd/amdgpu/soc15.h
103
#define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT
sys/dev/pci/drm/amd/amdgpu/soc15.h
41
u32 reg;
sys/dev/pci/drm/amd/amdgpu/soc15.h
50
u32 reg;
sys/dev/pci/drm/amd/amdgpu/soc15.h
90
#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
sys/dev/pci/drm/amd/amdgpu/soc15.h
91
#define SOC15_REG_ENTRY_STR(ip, inst, reg) \
sys/dev/pci/drm/amd/amdgpu/soc15.h
92
{ ip##_HWIP, inst, reg##_BASE_IDX, reg, #reg }
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
100
#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
102
(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)), \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
103
#reg, expected_value, mask)
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
105
#define SOC15_WAIT_ON_RREG_OFFSET(ip, inst, reg, offset, expected_value, mask) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
107
(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg) + (offset)), \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
108
#reg, expected_value, mask)
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
110
#define WREG32_RLC(reg, value) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
111
__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP, 0)
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
113
#define WREG32_RLC_EX(prefix, reg, value, inst) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
122
WREG32(r1, (reg | 0x80000000)); \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
131
pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg); \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
133
WREG32(reg, value); \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
138
#define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
139
__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP, inst)
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
142
#define RREG32_RLC(reg) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
143
__RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP, 0)
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
145
#define WREG32_RLC_NO_KIQ(reg, value, hwip) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
146
__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0)
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
148
#define RREG32_RLC_NO_KIQ(reg, hwip) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
149
__RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0)
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
151
#define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
153
uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
169
#define RREG32_SOC15_RLC(ip, inst, reg) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
170
__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip##_HWIP, inst)
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
172
#define WREG32_SOC15_RLC(ip, inst, reg, value) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
174
uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
178
#define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
180
uint32_t target_reg = adev->reg_offset[GC_HWIP][inst][reg##_BASE_IDX] + reg;\
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
184
#define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
185
__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
186
(__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
188
~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
191
#define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
192
__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AMDGPU_REGS_RLC, ip##_HWIP, inst)
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
194
#define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
195
__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP, inst)
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
198
#define RREG32_SOC15_EXT(ip, inst, reg, ext) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
199
RREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
202
#define WREG32_SOC15_EXT(ip, inst, reg, ext, value) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
203
WREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
36
#define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
37
#define SOC15_REG_OFFSET1(ip, inst, reg, offset) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
38
(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
40
#define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
42
amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
43
WREG32(reg, value))
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
45
#define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
47
amdgpu_sriov_rreg(adev, reg, flag, hwip, inst) : \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
48
RREG32(reg))
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
50
#define WREG32_FIELD15(ip, idx, reg, field, val) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
51
__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
53
adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
55
~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
59
__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
61
adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
66
#define RREG32_SOC15(ip, inst, reg) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
67
__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
70
#define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP, 0)
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
72
#define RREG32_SOC15_IP_NO_KIQ(ip, reg, inst) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
74
#define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
75
__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
78
#define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
79
__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)) + \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
82
#define WREG32_SOC15(ip, inst, reg, value) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
83
__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
86
#define WREG32_SOC15_IP(ip, reg, value) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
87
__WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP, 0)
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
89
#define WREG32_SOC15_IP_NO_KIQ(ip, reg, value, inst) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
90
__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
92
#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
93
__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
96
#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
sys/dev/pci/drm/amd/amdgpu/soc15_common.h
97
__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \
sys/dev/pci/drm/amd/amdgpu/soc15d.h
41
#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
sys/dev/pci/drm/amd/amdgpu/soc15d.h
42
((reg) & 0xFFFF) | \
sys/dev/pci/drm/amd/amdgpu/soc15d.h
74
#define PACKETJ(reg, r, cond, type) ((reg & 0x3FFFF) | \
sys/dev/pci/drm/amd/amdgpu/soc21.c
193
static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/soc21.c
202
WREG32(address, (reg));
sys/dev/pci/drm/amd/amdgpu/soc21.c
208
static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/soc21.c
216
WREG32(address, (reg));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1067
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1070
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1301
uint32_t reg = amdgpu_ib_get_value(ib, i);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1303
reg -= p->adev->reg_offset[UVD_HWIP][0][1];
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1304
reg += p->adev->reg_offset[UVD_HWIP][1][1];
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1306
amdgpu_ib_set_value(ib, i, reg);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1369
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1375
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1384
static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1391
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1437
uint32_t reg, uint32_t val,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1441
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1460
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1463
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
741
static void vce_v4_0_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
745
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
764
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
767
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c
56
void vcn_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c
60
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c
80
void vcn_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c
84
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.h
37
void vcn_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.h
41
void vcn_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1617
uint32_t reg, uint32_t val,
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1624
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1652
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1658
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1772
uint32_t reg, uint32_t val,
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1776
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1795
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1798
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
2102
uint32_t reg = amdgpu_ib_get_value(ib, i);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
2105
if (reg == PACKET0(p->adev->vcn.inst[0].internal.data0, 0)) {
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
2107
} else if (reg == PACKET0(p->adev->vcn.inst[0].internal.data1, 0)) {
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
2109
} else if (reg == PACKET0(p->adev->vcn.inst[0].internal.cmd, 0)) {
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1593
void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1599
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1628
uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1633
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1763
void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1767
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1785
void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1788
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h
34
extern void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h
39
uint32_t reg, uint32_t val);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h
47
extern void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.h
51
extern void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
2002
uint32_t reg = amdgpu_ib_get_value(ib, i);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
2005
if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.data0, 0)) {
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
2007
} else if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.data1, 0)) {
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
2009
} else if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.cmd, 0) &&
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1531
void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1536
reg = NORMALIZE_VCN_REG_OFFSET(reg);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1539
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1544
void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1549
reg = NORMALIZE_VCN_REG_OFFSET(reg);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1552
amdgpu_ring_write(ring, reg << 2);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.h
35
void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.h
38
void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
sys/dev/pci/drm/amd/amdgpu/vi.c
297
static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/vi.c
303
WREG32_NO_KIQ(mmPCIE_INDEX, reg);
sys/dev/pci/drm/amd/amdgpu/vi.c
310
static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/vi.c
315
WREG32_NO_KIQ(mmPCIE_INDEX, reg);
sys/dev/pci/drm/amd/amdgpu/vi.c
322
static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/vi.c
328
WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
sys/dev/pci/drm/amd/amdgpu/vi.c
334
static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/vi.c
339
WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
sys/dev/pci/drm/amd/amdgpu/vi.c
348
static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/vi.c
354
WREG32(mmMP0PUB_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/vi.c
360
static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/vi.c
365
WREG32(mmMP0PUB_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/vi.c
370
static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/vi.c
376
WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
sys/dev/pci/drm/amd/amdgpu/vi.c
382
static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/vi.c
387
WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
sys/dev/pci/drm/amd/amdgpu/vi.c
392
static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/vi.c
398
WREG32(mmDIDT_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/vi.c
404
static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/vi.c
409
WREG32(mmDIDT_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/vi.c
414
static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
sys/dev/pci/drm/amd/amdgpu/vi.c
420
WREG32(mmGC_CAC_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/vi.c
426
static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
sys/dev/pci/drm/amd/amdgpu/vi.c
431
WREG32(mmGC_CAC_IND_INDEX, (reg));
sys/dev/pci/drm/amd/amdgpu/vid.h
96
#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
sys/dev/pci/drm/amd/amdgpu/vid.h
97
((reg) & 0xFFFF) | \
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1783
union dmub_gpint_data_register reg, test;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1788
reg.bits.status = 1;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1789
reg.bits.command_code = command_code;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1790
reg.bits.param = param;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1792
cgs_write_register(adev->dm.cgs_device, 0x34c0 + 0x01f8, reg.all);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1798
reg.bits.status = 0;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1802
if (test.all == reg.all)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
46
TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
47
TP_ARGS(count, reg, value),
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
50
__field(uint32_t, reg)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
55
__entry->reg = reg;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
61
(unsigned long)__entry->reg,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
66
TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
67
TP_ARGS(count, reg, value));
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
70
TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
71
TP_ARGS(count, reg, value));
sys/dev/pci/drm/amd/display/dc/basics/conversion.c
131
uint16_t *reg,
sys/dev/pci/drm/amd/display/dc/basics/conversion.c
135
matrix[i] = int_frac_to_fixed_point(reg[i], 2, 13);
sys/dev/pci/drm/amd/display/dc/basics/conversion.h
45
uint16_t *reg,
sys/dev/pci/drm/amd/display/dc/bios/bios_parser_helper.c
50
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/bios/bios_parser_helper.c
51
(bios->regs->reg)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
46
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
47
(clk_mgr->regs->reg)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
46
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
47
(clk_mgr->regs->reg)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
46
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
47
(clk_mgr->regs->reg)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
42
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
43
(clk_mgr->regs->reg)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
52
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
53
(clk_mgr->regs->reg)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
57
uint32_t reg = 0;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
60
reg = REG_READ(DAL_RESP_REG);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
61
if (reg)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
74
return reg;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c
56
uint32_t reg = 0;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c
59
reg = REG_READ(DAL_RESP_REG);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c
60
if (reg)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c
73
return reg;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
71
(CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
37
(MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
168
(CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
53
#define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
62
(MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
54
(MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
88
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
89
(clk_mgr->regs->reg)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
96
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
97
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
109
uint32_t reg = 0;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
113
reg = REG_READ(DAL_RESP_REG);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
114
if (reg)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
126
return reg;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
53
uint32_t reg = 0;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
56
reg = REG_READ(DAL_RESP_REG);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
57
if (reg)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
69
return reg;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c
104
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c
105
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c
96
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c
97
(clk_mgr->regs->reg)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
127
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
128
(clk_mgr->regs->reg)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
135
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
136
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
53
#define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
46
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
47
(clk_mgr->regs->reg)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
54
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
55
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
109
return reg;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
39
uint32_t reg = 0;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
42
reg = REG_READ(DAL_RESP_REG);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
43
if (reg)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
52
return reg;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
94
uint32_t reg = 0;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
98
reg = REG_READ(DAL_RESP_REG);
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
99
if (reg)
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
35
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
36
(dccg_dcn->regs->reg)
sys/dev/pci/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c
34
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c
35
(dccg_dcn->regs->reg)
sys/dev/pci/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c
34
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c
35
(dccg_dcn->regs->reg)
sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c
33
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c
34
(dccg_dcn->regs->reg)
sys/dev/pci/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c
33
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c
34
(dccg_dcn->regs->reg)
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
34
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
35
(dccg_dcn->regs->reg)
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
36
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
37
(dccg_dcn->regs->reg)
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
33
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
34
(dccg_dcn->regs->reg)
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
33
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
34
(dccg_dcn->regs->reg)
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
43
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
44
(dccg_dcn->regs->reg)
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
40
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dce/dce_abm.c
41
(abm_dce->regs->reg)
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
1328
const struct dce_audio_registers *reg,
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
1344
audio->regs = reg;
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
1354
const struct dce_audio_registers *reg,
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
1370
audio->regs = reg;
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
39
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
40
(aud->regs->reg)
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
46
#define IX_REG(reg)\
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.c
47
ix ## reg
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
150
const struct dce_audio_registers *reg,
sys/dev/pci/drm/amd/display/dc/dce/dce_audio.h
158
const struct dce_audio_registers *reg,
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
38
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
39
(clk_mgr_dce->regs->reg)
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
41
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.c
42
(clk_src->regs->reg)
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
37
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dce/dce_dmcu.c
38
(dmcu_dce->regs->reg)
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
33
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dce/dce_i2c_hw.c
34
dce_i2c_hw->regs->reg
sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c
30
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dce/dce_ipp.c
31
(ipp_dce->regs->reg)
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
61
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
62
(enc110->link_regs->reg)
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
64
#define AUX_REG(reg)\
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
65
(enc110->aux_regs->reg)
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
67
#define HPD_REG(reg)\
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
68
(enc110->hpd_regs->reg)
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
90
#define DIG_REG(reg)\
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
91
(reg + enc110->offsets.dig)
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
93
#define DP_REG(reg)\
sys/dev/pci/drm/amd/display/dc/dce/dce_link_encoder.c
94
(reg + enc110->offsets.dp)
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
32
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c
33
dce_mi->regs->reg
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
33
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c
34
(opp110->regs->reg)
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
42
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
43
dce_panel_cntl->regs->reg
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
34
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
35
(enc110->regs->reg)
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
32
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c
33
(xfm_dce->regs->reg)
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c
42
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c
43
(dce_abm->regs->reg)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c
39
#define DCP_REG(reg)\
sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c
40
(reg + cp110->offsets.dcp_offset)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c
41
#define DMIF_REG(reg)\
sys/dev/pci/drm/amd/display/dc/dce110/dce110_compressor.c
42
(reg + cp110->offsets.dmif_offset)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
48
#define CRTC_REG(reg) (reg + tg110->offsets.crtc)
sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator.c
49
#define DCP_REG(reg) (reg + tg110->offsets.dcp)
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c
38
#define DCP_REG(reg)\
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c
39
(reg + cp110->offsets.dcp_offset)
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c
40
#define DMIF_REG(reg)\
sys/dev/pci/drm/amd/display/dc/dce112/dce112_compressor.c
41
(reg + cp110->offsets.dmif_offset)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
48
#define CRTC_REG_UPDATE(reg, field, val) \
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
49
CRTC_REG_UPDATE_N(reg, 1, FD(reg##__##field), val)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
51
#define CRTC_REG_UPDATE_2(reg, field1, val1, field2, val2) \
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
52
CRTC_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
54
#define CRTC_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3) \
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
55
CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
57
#define CRTC_REG_UPDATE_4(reg, field1, val1, field2, val2, field3, val3, field4, val4) \
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
58
CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3, FD(reg##__##field4), val4)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
60
#define CRTC_REG_UPDATE_5(reg, field1, val1, field2, val2, field3, val3, field4, val4, field5, val5) \
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
61
CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3, FD(reg##__##field4), val4, FD(reg##__##field5), val5)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
63
#define CRTC_REG_SET(reg, field, val) \
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
64
CRTC_REG_SET_N(reg, 1, FD(reg##__##field), val)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
66
#define CRTC_REG_SET_2(reg, field1, val1, field2, val2) \
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
67
CRTC_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
69
#define CRTC_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
70
CRTC_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c
83
#define CRTC_REG(reg) (reg + tg110->offsets.crtc)
sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c
84
#define DCP_REG(reg) (reg + tg110->offsets.dcp)
sys/dev/pci/drm/amd/display/dc/dce60/dce60_timing_generator.c
85
#define DMIF_REG(reg) (reg + tg110->offsets.dmif)
sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c
83
#define CRTC_REG(reg) (reg + tg110->offsets.crtc)
sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c
84
#define DCP_REG(reg) (reg + tg110->offsets.dcp)
sys/dev/pci/drm/amd/display/dc/dce80/dce80_timing_generator.c
85
#define DMIF_REG(reg) (reg + tg110->offsets.dmif)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
103
REG_SET(reg->start_slope_cntl_b, 0,
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
105
REG_SET(reg->start_slope_cntl_g, 0,
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
107
REG_SET(reg->start_slope_cntl_r, 0,
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
110
REG_SET(reg->start_end_cntl1_b, 0,
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
112
REG_SET_2(reg->start_end_cntl2_b, 0,
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
116
REG_SET(reg->start_end_cntl1_g, 0,
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
118
REG_SET_2(reg->start_end_cntl2_g, 0,
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
122
REG_SET(reg->start_end_cntl1_r, 0,
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
124
REG_SET_2(reg->start_end_cntl2_r, 0,
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
128
for (reg_region_cur = reg->region_start;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
129
reg_region_cur <= reg->region_end;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
32
#define REG(reg) reg
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
39
reg->shifts.field_name, reg->masks.field_name
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
44
const struct color_matrices_reg *reg)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
49
for (cur_csc_reg = reg->csc_c11_c12;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
50
cur_csc_reg <= reg->csc_c33_c34;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
67
const struct color_matrices_reg *reg)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
72
for (cur_csc_reg = reg->csc_c11_c12;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
73
cur_csc_reg <= reg->csc_c33_c34; cur_csc_reg++) {
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
88
const struct xfer_func_reg *reg)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
93
REG_SET_2(reg->start_cntl_b, 0,
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
96
REG_SET_2(reg->start_cntl_g, 0,
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
99
REG_SET_2(reg->start_cntl_r, 0,
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h
100
const struct xfer_func_reg *reg);
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h
119
const struct color_matrices_reg *reg);
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.h
95
const struct color_matrices_reg *reg);
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c
32
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c
33
dwbc10->dwbc_regs->reg
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.c
30
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_ipp.c
31
(ippn10->regs->reg)
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
33
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
34
dwbc20->dwbc_regs->reg
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
36
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
37
dwbc20->dwbc_regs->reg
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.c
31
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_vmid.c
32
vmid->regs->reg
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.c
42
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_link_encoder.c
43
(enc10->link_regs->reg)
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
29
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_mpc.c
30
mpc201->mpc_regs->reg
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_opp.c
30
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_opp.c
31
(oppn201->regs->reg)
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
43
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
44
(enc10->link_regs->reg)
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c
35
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_afmt.c
36
(afmt3->regs->reg)
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
34
#define REG(reg) reg
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
41
reg->shifts.field_name, reg->masks.field_name
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
46
const struct dcn3_xfer_func_reg *reg)
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
51
REG_SET_2(reg->start_cntl_b, 0,
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
54
REG_SET_2(reg->start_cntl_g, 0,
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
57
REG_SET_2(reg->start_cntl_r, 0,
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
61
REG_SET(reg->start_slope_cntl_b, 0, //linear slope at start of curve
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
63
REG_SET(reg->start_slope_cntl_g, 0,
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
65
REG_SET(reg->start_slope_cntl_r, 0,
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
68
REG_SET(reg->start_end_cntl1_b, 0,
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
70
REG_SET(reg->start_end_cntl1_g, 0,
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
72
REG_SET(reg->start_end_cntl1_r, 0,
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
75
REG_SET_2(reg->start_end_cntl2_b, 0,
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
78
REG_SET_2(reg->start_end_cntl2_g, 0,
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
81
REG_SET_2(reg->start_end_cntl2_r, 0,
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
85
for (reg_region_cur = reg->region_start;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
86
reg_region_cur <= reg->region_end;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c
33
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c
34
mcif_wb30->mcif_wb_regs->reg
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.c
34
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_vpg.c
35
(vpg3->regs->reg)
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
41
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
42
dcn301_panel_cntl->regs->reg
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.c
36
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_afmt.c
37
(afmt31->regs->reg)
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.c
35
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_apg.c
36
(apg31->regs->reg)
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.c
35
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_vpg.c
36
(vpg31->regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1366
#define HPD_REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1367
(enc10->hpd_regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1397
#define AUX_REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1398
(enc10->aux_regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1412
#define AUX_REG_UPDATE_2(reg, f1, v1, f2, v2) \
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1413
AUX_REG_UPDATE_N(reg, 2,\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1414
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1415
FN(reg, f2), v2)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
41
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
42
(enc10->link_regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
38
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
39
(enc1->regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
300
#define AUX_REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
301
(enc10->aux_regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
41
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
42
(enc10->link_regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
38
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
39
(enc1->regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c
208
#define AUX_REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c
209
(enc10->aux_regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c
40
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c
41
(enc10->link_regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
36
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
37
(enc1->regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c
40
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c
41
(enc10->link_regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
47
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
48
(enc10->link_regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
57
#define AUX_REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
58
(enc10->aux_regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
39
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
40
(enc1->regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c
49
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c
50
(enc10->link_regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c
56
#define AUX_REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c
57
(enc10->aux_regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
38
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
39
(enc1->regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c
46
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c
47
(enc10->link_regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c
53
#define AUX_REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c
54
(enc10->aux_regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c
37
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c
38
(enc10->link_regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
38
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
39
(enc1->regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
48
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
49
(enc10->link_regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
55
#define AUX_REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
56
(enc10->aux_regs->reg)
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
41
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
42
(enc1->regs->reg)
sys/dev/pci/drm/amd/display/dc/dm_services.h
151
#define dm_write_reg_soc15(ctx, reg, inst_offset, value) \
sys/dev/pci/drm/amd/display/dc/dm_services.h
152
dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__)
sys/dev/pci/drm/amd/display/dc/dm_services.h
154
#define dm_read_reg_soc15(ctx, reg, inst_offset) \
sys/dev/pci/drm/amd/display/dc/dm_services.h
155
dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
36
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
37
optc1->tg_regs->reg
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
41
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
42
dpp->tf_regs->reg
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
326
struct xfer_func_reg *reg)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
328
reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
329
reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
330
reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
331
reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
332
reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
333
reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
334
reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
335
reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
337
reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
338
reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
339
reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
340
reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
341
reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
342
reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
343
reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
344
reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
345
reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
346
reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
347
reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
348
reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
353
struct xfer_func_reg *reg)
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
355
reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
356
reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
357
reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
358
reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
359
reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
360
reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
361
reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
362
reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
364
reg->shifts.field_region_end = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
365
reg->masks.field_region_end = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
366
reg->shifts.field_region_end_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
367
reg->masks.field_region_end_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
368
reg->shifts.field_region_end_base = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
369
reg->masks.field_region_end_base = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
370
reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
371
reg->masks.field_region_linear_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
372
reg->shifts.exp_region_start = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
373
reg->masks.exp_region_start = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
374
reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
375
reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
42
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
43
dpp->tf_regs->reg
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
43
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
44
dpp->tf_regs->reg
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
41
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c
42
dpp->tf_regs->reg
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
36
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
37
dpp->tf_regs->reg
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
415
struct xfer_func_reg *reg)
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
417
reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
418
reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
419
reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
420
reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
421
reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
422
reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
423
reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
424
reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
426
reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
427
reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
428
reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
429
reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
430
reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
431
reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
432
reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
433
reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
434
reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
435
reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
436
reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
437
reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
34
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
35
dpp->tf_regs->reg
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
33
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
34
dpp->tf_regs->reg
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
669
struct dcn3_xfer_func_reg *reg)
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
671
reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
672
reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
673
reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
674
reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
675
reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
676
reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
677
reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
678
reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
680
reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
681
reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
682
reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
683
reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
684
reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
685
reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
686
reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
687
reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
688
reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
689
reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
690
reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
691
reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
170
struct dcn3_xfer_func_reg *reg)
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
173
reg->shifts.field_region_start_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
174
reg->masks.field_region_start_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
175
reg->shifts.field_offset = dpp->tf_shift->CM_GAMCOR_RAMA_OFFSET_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
176
reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
178
reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
179
reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
180
reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
181
reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
182
reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
183
reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
184
reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
185
reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
187
reg->shifts.field_region_end = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
188
reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
189
reg->shifts.field_region_end_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
190
reg->masks.field_region_end_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
191
reg->shifts.field_region_end_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
192
reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
193
reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
194
reg->masks.field_region_linear_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
195
reg->shifts.exp_region_start = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
196
reg->masks.exp_region_start = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
197
reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
198
reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
33
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
34
dpp->tf_regs->reg
sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
31
#define REG(reg) dpp->tf_regs->reg
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
35
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
36
dpp->tf_regs->reg
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c
42
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c
43
dpp->tf_regs->reg
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
43
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
44
dpp->tf_regs->reg
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
51
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
52
dsc20->dsc_regs->reg
sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
48
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
49
dsc20->dsc_regs->reg
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
35
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
36
dsc401->dsc_regs->reg
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h
60
const struct dcn3_xfer_func_reg *reg);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
33
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
34
dwbc30->dwbc_regs->reg
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
36
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
37
dwbc30->dwbc_regs->reg
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
50
struct dcn3_xfer_func_reg *reg)
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
52
reg->shifts.field_region_start_base = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
53
reg->masks.field_region_start_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
54
reg->shifts.field_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_OFFSET_B;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
55
reg->masks.field_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_OFFSET_B;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
57
reg->shifts.exp_region0_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
58
reg->masks.exp_region0_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
59
reg->shifts.exp_region0_num_segments = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
60
reg->masks.exp_region0_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
61
reg->shifts.exp_region1_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
62
reg->masks.exp_region1_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
63
reg->shifts.exp_region1_num_segments = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
64
reg->masks.exp_region1_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
66
reg->shifts.field_region_end = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
67
reg->masks.field_region_end = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
68
reg->shifts.field_region_end_slope = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
69
reg->masks.field_region_end_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
70
reg->shifts.field_region_end_base = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
71
reg->masks.field_region_end_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
72
reg->shifts.field_region_linear_slope = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
73
reg->masks.field_region_linear_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
74
reg->shifts.exp_region_start = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
75
reg->masks.exp_region_start = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
76
reg->shifts.exp_resion_start_segment = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
77
reg->masks.exp_resion_start_segment = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.c
27
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.c
28
dwbc30->dwbc_regs->reg
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c
64
BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c
70
BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c
71
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
56
BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
60
BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
66
BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
67
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c
54
BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c
40
BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c
46
BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c
47
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c
29
BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c
43
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/gpio/hw_ddc.c
44
(ddc->regs->reg)
sys/dev/pci/drm/amd/display/dc/gpio/hw_generic.c
44
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/gpio/hw_generic.c
45
(generic->regs->reg)
sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.c
39
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/gpio/hw_gpio.c
40
(gpio->regs->reg)
sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.c
42
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/gpio/hw_hpd.c
43
(hpd->regs->reg)
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
34
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c
35
(enc3->regs->reg)
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
34
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c
35
(enc3->regs->reg)
sys/dev/pci/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c
34
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c
35
(enc3->regs->reg)
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
35
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
36
hubbub1->regs->reg
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
31
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
32
hubbub1->regs->reg
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
41
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
42
hubbub1->regs->reg
sys/dev/pci/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c
30
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c
31
hubbub1->regs->reg
sys/dev/pci/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c
43
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c
44
hubbub1->regs->reg
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
31
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
32
hubbub1->regs->reg
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
42
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
43
hubbub1->regs->reg
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
36
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
37
hubbub1->regs->reg
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
405
uint32_t reg;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
407
reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
408
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
409
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
410
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
412
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
413
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
414
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
415
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
417
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
418
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
419
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
420
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
422
reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
423
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
424
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
425
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
427
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
428
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
429
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
430
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
432
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
433
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
434
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
435
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
437
reg = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
438
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
439
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
440
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.c
29
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.c
30
hubbub1->regs->reg
sys/dev/pci/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.c
40
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.c
41
hubbub1->regs->reg
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
37
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
38
hubbub2->regs->reg
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
38
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
39
hubbub2->regs->reg
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
830
uint32_t reg;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
832
reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
833
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
834
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
835
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
837
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
838
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
839
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
840
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
842
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
843
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
844
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
845
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
847
reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
848
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
849
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
850
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
852
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
853
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
854
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
855
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
857
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
858
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
859
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
860
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
862
reg = REG_READ(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
863
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
864
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
865
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
867
reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
868
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
869
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
870
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
872
reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
873
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
874
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
875
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
341
uint32_t reg;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
343
reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
344
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
345
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
346
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
348
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
349
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
350
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
351
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
353
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
354
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
355
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
356
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
358
reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
359
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
360
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
361
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
363
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
364
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
365
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
366
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
368
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
369
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
370
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
371
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
373
reg = REG_READ(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
374
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
375
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
376
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
378
reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
379
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
380
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
381
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
383
reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
384
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
385
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
386
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
388
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
389
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
390
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
391
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
393
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
394
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
395
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
396
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
40
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
41
hubbub2->regs->reg
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
37
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
38
hubbub2->regs->reg
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
500
uint32_t reg;
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
502
reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
503
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
505
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
506
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
508
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
509
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
511
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_MALL_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
512
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_MALL_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
514
reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
515
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
517
reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
518
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
520
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
521
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
522
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
523
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
524
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
525
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
526
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
527
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
529
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
530
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
531
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
532
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
533
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
534
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
535
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
536
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
538
reg = REG_READ(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
539
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
541
reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
542
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
543
reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
544
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
546
reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
547
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, reg);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
548
reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A);
sys/dev/pci/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
549
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B, reg);
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
31
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
32
hubp1->hubp_regs->reg
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
37
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
38
hubp2->hubp_regs->reg
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c
32
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c
33
hubp201->hubp_regs->reg
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
38
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
39
hubp21->hubp_regs->reg
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
35
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
36
hubp2->hubp_regs->reg
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c
32
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c
33
hubp2->hubp_regs->reg
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
32
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
33
hubp2->hubp_regs->reg
sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
30
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
31
hubp2->hubp_regs->reg
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
33
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
34
hubp2->hubp_regs->reg
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c
33
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c
34
hws->regs->reg
sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
64
#define HW_REG_CRTC(reg, id)\
sys/dev/pci/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
65
(reg + reg_offsets[id].crtc)
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
119
#define HW_REG_BLND(reg, id)\
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
120
(reg + reg_offsets[id].blnd)
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
122
#define HW_REG_CRTC(reg, id)\
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
123
(reg + reg_offsets[id].crtc)
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
93
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
94
hws->regs->reg
sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c
62
#define HW_REG_CRTC(reg, id)\
sys/dev/pci/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c
63
(reg + reg_offsets[id].crtc)
sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
43
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
44
hws->regs->reg
sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
76
#define HW_REG_CRTC(reg, id)\
sys/dev/pci/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
77
(reg + reg_offsets[id].crtc)
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
68
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
69
hws->regs->reg
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
67
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
68
hws->regs->reg
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
46
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
47
hws->regs->reg
sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
44
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
45
hws->regs->reg
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
62
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
63
hws->regs->reg
sys/dev/pci/drm/amd/display/dc/hwss/dcn301/dcn301_hwseq.c
35
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hwss/dcn301/dcn301_hwseq.c
36
hws->regs->reg
sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c
37
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c
38
hws->regs->reg
sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c
38
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c
39
hws->regs->reg
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
60
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
61
hws->regs->reg
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
62
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
63
hws->regs->reg
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
60
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
61
hws->regs->reg
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
66
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
67
hws->regs->reg
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
44
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
45
hws->regs->reg
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
100
FN(reg, f4), v4,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
101
FN(reg, f5), v5,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
102
FN(reg, f6), v6)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
104
#define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
106
REG_SET_N(reg, 7, init_value, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
107
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
108
FN(reg, f2), v2,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
109
FN(reg, f3), v3,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
110
FN(reg, f4), v4,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
111
FN(reg, f5), v5,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
112
FN(reg, f6), v6,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
113
FN(reg, f7), v7)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
115
#define REG_SET_8(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
117
REG_SET_N(reg, 8, init_value, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
118
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
119
FN(reg, f2), v2,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
120
FN(reg, f3), v3,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
121
FN(reg, f4), v4,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
122
FN(reg, f5), v5,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
123
FN(reg, f6), v6,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
124
FN(reg, f7), v7,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
125
FN(reg, f8), v8)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
127
#define REG_SET_9(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
129
REG_SET_N(reg, 9, init_value, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
130
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
131
FN(reg, f2), v2, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
132
FN(reg, f3), v3, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
133
FN(reg, f4), v4, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
134
FN(reg, f5), v5, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
135
FN(reg, f6), v6, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
136
FN(reg, f7), v7, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
137
FN(reg, f8), v8, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
138
FN(reg, f9), v9)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
140
#define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
142
REG_SET_N(reg, 10, init_value, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
143
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
144
FN(reg, f2), v2, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
145
FN(reg, f3), v3, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
146
FN(reg, f4), v4, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
147
FN(reg, f5), v5, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
148
FN(reg, f6), v6, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
149
FN(reg, f7), v7, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
150
FN(reg, f8), v8, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
151
FN(reg, f9), v9, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
152
FN(reg, f10), v10)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
234
#define REG_UPDATE_2(reg, f1, v1, f2, v2) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
235
REG_UPDATE_N(reg, 2,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
236
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
237
FN(reg, f2), v2)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
239
#define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
240
REG_UPDATE_N(reg, 3, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
241
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
242
FN(reg, f2), v2, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
243
FN(reg, f3), v3)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
245
#define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
246
REG_UPDATE_N(reg, 4, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
247
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
248
FN(reg, f2), v2, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
249
FN(reg, f3), v3, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
250
FN(reg, f4), v4)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
252
#define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
253
REG_UPDATE_N(reg, 5, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
254
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
255
FN(reg, f2), v2, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
256
FN(reg, f3), v3, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
257
FN(reg, f4), v4, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
258
FN(reg, f5), v5)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
260
#define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
261
REG_UPDATE_N(reg, 6, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
262
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
263
FN(reg, f2), v2, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
264
FN(reg, f3), v3, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
265
FN(reg, f4), v4, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
266
FN(reg, f5), v5, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
267
FN(reg, f6), v6)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
269
#define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
270
REG_UPDATE_N(reg, 7, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
271
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
272
FN(reg, f2), v2, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
273
FN(reg, f3), v3, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
274
FN(reg, f4), v4, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
275
FN(reg, f5), v5, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
276
FN(reg, f6), v6, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
277
FN(reg, f7), v7)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
279
#define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
280
REG_UPDATE_N(reg, 8, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
281
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
282
FN(reg, f2), v2, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
283
FN(reg, f3), v3, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
284
FN(reg, f4), v4, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
285
FN(reg, f5), v5, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
286
FN(reg, f6), v6, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
287
FN(reg, f7), v7, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
288
FN(reg, f8), v8)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
290
#define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
291
REG_UPDATE_N(reg, 9, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
292
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
293
FN(reg, f2), v2, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
294
FN(reg, f3), v3, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
295
FN(reg, f4), v4, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
296
FN(reg, f5), v5, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
297
FN(reg, f6), v6, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
298
FN(reg, f7), v7, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
299
FN(reg, f8), v8, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
300
FN(reg, f9), v9)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
302
#define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
303
REG_UPDATE_N(reg, 10, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
304
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
305
FN(reg, f2), v2, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
306
FN(reg, f3), v3, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
307
FN(reg, f4), v4, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
308
FN(reg, f5), v5, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
309
FN(reg, f6), v6, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
310
FN(reg, f7), v7, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
311
FN(reg, f8), v8, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
312
FN(reg, f9), v9, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
313
FN(reg, f10), v10)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
315
#define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
317
REG_UPDATE_N(reg, 14, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
318
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
319
FN(reg, f2), v2, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
320
FN(reg, f3), v3, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
321
FN(reg, f4), v4, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
322
FN(reg, f5), v5, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
323
FN(reg, f6), v6, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
324
FN(reg, f7), v7, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
325
FN(reg, f8), v8, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
326
FN(reg, f9), v9, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
327
FN(reg, f10), v10, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
328
FN(reg, f11), v11, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
329
FN(reg, f12), v12, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
330
FN(reg, f13), v13, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
331
FN(reg, f14), v14)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
333
#define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
335
REG_UPDATE_N(reg, 19, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
336
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
337
FN(reg, f2), v2, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
338
FN(reg, f3), v3, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
339
FN(reg, f4), v4, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
340
FN(reg, f5), v5, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
341
FN(reg, f6), v6, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
342
FN(reg, f7), v7, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
343
FN(reg, f8), v8, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
344
FN(reg, f9), v9, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
345
FN(reg, f10), v10, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
346
FN(reg, f11), v11, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
347
FN(reg, f12), v12, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
348
FN(reg, f13), v13, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
349
FN(reg, f14), v14, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
350
FN(reg, f15), v15, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
351
FN(reg, f16), v16, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
352
FN(reg, f17), v17, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
353
FN(reg, f18), v18, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
354
FN(reg, f19), v19)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
356
#define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
358
REG_UPDATE_N(reg, 20, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
359
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
360
FN(reg, f2), v2, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
361
FN(reg, f3), v3, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
362
FN(reg, f4), v4, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
363
FN(reg, f5), v5, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
364
FN(reg, f6), v6, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
365
FN(reg, f7), v7, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
366
FN(reg, f8), v8, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
367
FN(reg, f9), v9, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
368
FN(reg, f10), v10, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
369
FN(reg, f11), v11, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
370
FN(reg, f12), v12, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
371
FN(reg, f13), v13, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
372
FN(reg, f14), v14, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
373
FN(reg, f15), v15, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
374
FN(reg, f16), v16, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
375
FN(reg, f17), v17, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
376
FN(reg, f18), v18, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
377
FN(reg, f19), v19, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
378
FN(reg, f20), v20)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
382
#define REG_UPDATE_SEQ_2(reg, f1, v1, f2, v2) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
383
{ uint32_t val = REG_UPDATE(reg, f1, v1); \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
384
REG_SET(reg, val, f2, v2); }
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
386
#define REG_UPDATE_SEQ_3(reg, f1, v1, f2, v2, f3, v3) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
387
{ uint32_t val = REG_UPDATE(reg, f1, v1); \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
388
val = REG_SET(reg, val, f2, v2); \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
389
REG_SET(reg, val, f3, v3); }
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
454
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
455
FN(reg, f2), v2)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
478
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
479
FN(reg, f2), v2)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
513
FN(reg, f1), v1)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
517
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
518
FN(reg, f2), v2)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
67
#define REG_SET_2(reg, init_value, f1, v1, f2, v2) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
68
REG_SET_N(reg, 2, init_value, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
69
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
70
FN(reg, f2), v2)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
72
#define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
73
REG_SET_N(reg, 3, init_value, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
74
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
75
FN(reg, f2), v2,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
76
FN(reg, f3), v3)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
78
#define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
79
REG_SET_N(reg, 4, init_value, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
80
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
81
FN(reg, f2), v2,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
82
FN(reg, f3), v3,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
83
FN(reg, f4), v4)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
85
#define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
87
REG_SET_N(reg, 5, init_value, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
88
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
89
FN(reg, f2), v2,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
90
FN(reg, f3), v3,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
91
FN(reg, f4), v4,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
92
FN(reg, f5), v5)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
94
#define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
96
REG_SET_N(reg, 6, init_value, \
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
97
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
98
FN(reg, f2), v2,\
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
99
FN(reg, f3), v3,\
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
174
BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
175
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
178
BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
179
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
176
(BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
177
reg ## block ## id ## _ ## reg_name)
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
180
(BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
181
reg ## reg_name)
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
181
BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
182
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
185
BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
186
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
185
BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
186
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
189
BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
190
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
173
BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
174
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
177
BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
178
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
152
BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
153
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
156
BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
157
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
151
BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
152
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
155
BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
156
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
165
BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
166
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
169
BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
170
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c
33
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c
34
mcif_wb20->mcif_wb_regs->reg
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c
33
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c
34
mcif_wb30->mcif_wb_regs->reg
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.c
30
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.c
32
->reg
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
29
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
30
mpc10->mpc_regs->reg
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
246
struct xfer_func_reg *reg)
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
250
reg->shifts.exp_region0_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
251
reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
252
reg->shifts.exp_region0_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
253
reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
254
reg->shifts.exp_region1_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
255
reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
256
reg->shifts.exp_region1_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
257
reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
258
reg->shifts.field_region_end = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
259
reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
260
reg->shifts.field_region_end_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
261
reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
262
reg->shifts.field_region_end_base = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
263
reg->masks.field_region_end_base = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
264
reg->shifts.field_region_linear_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
265
reg->masks.field_region_linear_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
266
reg->shifts.exp_region_start = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
267
reg->masks.exp_region_start = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
268
reg->shifts.exp_resion_start_segment = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
269
reg->masks.exp_resion_start_segment = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
33
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
34
mpc20->mpc_regs->reg
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
203
struct dcn3_xfer_func_reg *reg)
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
207
reg->shifts.field_region_start_base = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
208
reg->masks.field_region_start_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
209
reg->shifts.field_offset = mpc30->mpc_shift->MPCC_OGAM_RAMA_OFFSET_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
210
reg->masks.field_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_OFFSET_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
212
reg->shifts.exp_region0_lut_offset = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
213
reg->masks.exp_region0_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
214
reg->shifts.exp_region0_num_segments = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
215
reg->masks.exp_region0_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
216
reg->shifts.exp_region1_lut_offset = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
217
reg->masks.exp_region1_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
218
reg->shifts.exp_region1_num_segments = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
219
reg->masks.exp_region1_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
221
reg->shifts.field_region_end = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
222
reg->masks.field_region_end = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
223
reg->shifts.field_region_end_slope = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
224
reg->masks.field_region_end_slope = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
225
reg->shifts.field_region_end_base = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
226
reg->masks.field_region_end_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
227
reg->shifts.field_region_linear_slope = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
228
reg->masks.field_region_linear_slope = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
229
reg->shifts.exp_region_start = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
230
reg->masks.exp_region_start = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
231
reg->shifts.exp_resion_start_segment = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
232
reg->masks.exp_resion_start_segment = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
33
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
34
mpc30->mpc_regs->reg
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
141
struct dcn3_xfer_func_reg *reg)
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
143
reg->shifts.exp_region0_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
144
reg->masks.exp_region0_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
145
reg->shifts.exp_region0_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
146
reg->masks.exp_region0_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
147
reg->shifts.exp_region1_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
148
reg->masks.exp_region1_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
149
reg->shifts.exp_region1_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
150
reg->masks.exp_region1_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
152
reg->shifts.field_region_end = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
153
reg->masks.field_region_end = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
154
reg->shifts.field_region_end_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
155
reg->masks.field_region_end_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
156
reg->shifts.field_region_end_base = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
157
reg->masks.field_region_end_base = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
158
reg->shifts.field_region_linear_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
159
reg->masks.field_region_linear_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
160
reg->shifts.exp_region_start = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
161
reg->masks.exp_region_start = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
162
reg->shifts.exp_resion_start_segment = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
163
reg->masks.exp_resion_start_segment = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
34
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
35
mpc30->mpc_regs->reg
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
33
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
34
mpc401->mpc_regs->reg
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
31
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
32
(oppn10->regs->reg)
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
31
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
32
(oppn20->regs->reg)
sys/dev/pci/drm/amd/display/dc/opp/dcn35/dcn35_opp.c
30
#define REG(reg) ((const struct dcn35_opp_registers *)(oppn20->regs))->reg
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
32
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
33
optc1->tg_regs->reg
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
30
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
31
optc1->tg_regs->reg
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
31
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
32
optc1->tg_regs->reg
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
35
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
36
optc1->tg_regs->reg
sys/dev/pci/drm/amd/display/dc/optc/dcn301/dcn301_optc.c
35
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/optc/dcn301/dcn301_optc.c
36
optc1->tg_regs->reg
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
33
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
34
optc1->tg_regs->reg
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
35
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
36
optc1->tg_regs->reg
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
35
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
36
optc1->tg_regs->reg
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
37
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
38
optc1->tg_regs->reg
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
14
#define REG(reg)\
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
15
optc1->tg_regs->reg
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
35
#define REG(reg) \
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
36
(pg_cntl_dcn->regs->reg)
sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c
410
#define REG(reg) mm ## reg
sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c
457
#define REG(reg) mm ## reg
sys/dev/pci/drm/amd/display/dc/resource/dce112/dce112_resource.c
437
#define REG(reg) mm ## reg
sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c
443
#define REG(reg) mm ## reg
sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c
449
#define REG(reg) mm ## reg
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
129
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
130
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
133
.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
134
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
137
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
138
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
141
.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
142
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
145
.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
146
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
149
.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
150
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
153
.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
154
reg ## block ## id ## _ ## temp_name
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
160
.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
161
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
164
.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
165
reg ## reg_name ## _ ## block ## id
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
197
.reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
198
reg ## block ## _ ## inst ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
673
.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
675
reg ## reg_name_pre ## id ## _ ## reg_name_post
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
146
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
147
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
150
.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
151
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
154
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
155
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
158
.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
159
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
162
.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
163
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
166
.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
167
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
170
.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
171
reg ## block ## id ## _ ## temp_name
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
177
.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
178
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
181
.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
182
reg ## reg_name ## _ ## block ## id
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
203
.reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
204
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
214
.reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
215
reg ## block ## _ ## inst ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
680
.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
682
reg ## reg_name_pre ## id ## _ ## reg_name_post
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
163
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
164
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
167
.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
168
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
171
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
172
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
175
.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
176
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
179
.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
180
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
183
.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
184
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
187
.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
188
reg ## block ## id ## _ ## temp_name
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
194
.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
195
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
198
.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
199
reg ## reg_name ## _ ## block ## id
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
672
.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
674
reg ## reg_name_pre ## id ## _ ## reg_name_post
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
149
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
150
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
153
.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
154
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
157
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
158
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
161
.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
162
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
165
.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
166
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
169
.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
170
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
173
.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
174
reg ## block ## id ## _ ## temp_name
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
180
.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
181
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
184
.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
185
reg ## reg_name ## _ ## block ## id
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
667
.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
669
reg ## reg_name_pre ## id ## _ ## reg_name_post
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
118
REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
119
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
121
REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
127
REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
128
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
131
REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
132
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
135
REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
138
REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
139
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
142
REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
143
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
146
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
147
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
149
REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
150
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
153
.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
154
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
157
REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
158
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
161
REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
162
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
165
.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
166
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
169
REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
170
reg ## block ## id ## _ ## temp_name
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
176
REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
177
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
180
REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
181
reg ## reg_name ## _ ## block ## id
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
199
(ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
526
.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
528
reg ## reg_name_pre ## id ## _ ## reg_name_post
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
118
REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
119
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
121
REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
122
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
127
REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
128
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
131
REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
132
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
135
REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
138
REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
139
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
142
REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
143
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
146
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
147
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
149
REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
150
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
153
.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
154
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
157
REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
158
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
161
REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
162
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
165
.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
166
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
169
REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
170
reg ## block ## id ## _ ## temp_name
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
173
REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
174
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
180
REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
181
reg ## reg_name ## _ ## block ## id
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
198
(ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
522
.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
524
reg ## reg_name_pre ## id ## _ ## reg_name_post
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
132
REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
133
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
136
REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
142
REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
143
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
146
REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
147
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
150
REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
153
REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
154
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
157
REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
158
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
161
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
162
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
165
REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
166
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
169
.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
170
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
173
REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
174
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
177
REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
178
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
181
.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
182
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
185
REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
186
reg ## block ## id ## _ ## temp_name
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
192
REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
193
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
196
REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
197
reg ## reg_name ## _ ## block ## id
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
548
.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
550
reg ## reg_name_pre ## id ## _ ## reg_name_post
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
112
REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
113
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
116
REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
122
REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
123
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
126
REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
127
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
130
REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
133
REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
134
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
137
REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
138
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
141
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
142
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
145
REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
146
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
149
.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
150
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
153
REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
154
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
157
REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
158
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
161
.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
162
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
165
REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
166
reg ## block ## id ## _ ## temp_name
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
172
REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
173
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
176
REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
177
reg ## reg_name ## _ ## block ## id
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
528
.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
530
reg ## reg_name_pre ## id ## _ ## reg_name_post
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
117
REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
118
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
121
REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
127
REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
128
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
131
REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
132
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
135
REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
138
REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
139
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
142
REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
143
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
146
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
147
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
150
REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
151
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
154
.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
155
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
158
REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
159
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
162
REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
163
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
166
.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
167
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
170
REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
171
reg ## block ## id ## _ ## temp_name
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
177
REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
178
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
181
REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
182
reg ## reg_name ## _ ## block ## id
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
529
.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
531
reg ## reg_name_pre ## id ## _ ## reg_name_post
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
100
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
102
REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
103
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
108
REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
109
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
112
REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
113
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
119
REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
120
reg ## block ## id ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
122
REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
125
REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
126
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
129
REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
130
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
133
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
134
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
136
REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
137
reg ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
140
.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
141
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
144
REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
145
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
148
REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
149
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
152
.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
153
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
156
REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
157
reg ## block ## id ## _ ## temp_name
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
160
REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
161
reg ## block ## id ## _ ## reg_name
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
167
REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
168
reg ## reg_name ## _ ## block ## id
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
185
(ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
501
.reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
503
reg ## reg_name_pre ## id ## _ ## reg_name_post
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
99
REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
473
union dmub_gpint_data_register reg);
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
476
union dmub_gpint_data_register reg);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
368
union dmub_gpint_data_register reg)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
370
REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
374
union dmub_gpint_data_register reg)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
378
reg.bits.status = 0;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
381
return test.all == reg.all;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
42
#define DMUB_SR(reg) REG_OFFSET(reg),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
49
#define DMUB_SF(reg, field) FD_MASK(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c
53
#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
157
#define DMUB_SR(reg) uint32_t reg;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
164
#define DMUB_SF(reg, field) uint8_t reg##__##field;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
170
#define DMUB_SF(reg, field) uint32_t reg##__##field;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
231
union dmub_gpint_data_register reg);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
234
union dmub_gpint_data_register reg);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn21.c
41
#define DMUB_SR(reg) REG_OFFSET(reg),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn21.c
48
#define DMUB_SF(reg, field) FD_MASK(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn21.c
52
#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
42
#define DMUB_SR(reg) REG_OFFSET(reg),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
49
#define DMUB_SF(reg, field) FD_MASK(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c
53
#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn301.c
41
#define DMUB_SR(reg) REG_OFFSET(reg),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn301.c
48
#define DMUB_SF(reg, field) FD_MASK(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn301.c
52
#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn302.c
41
#define DMUB_SR(reg) REG_OFFSET(reg),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn302.c
48
#define DMUB_SF(reg, field) FD_MASK(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn302.c
52
#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn303.c
42
#define DMUB_SR(reg) REG_OFFSET(reg),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn303.c
49
#define DMUB_SF(reg, field) FD_MASK(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn303.c
53
#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
317
union dmub_gpint_data_register reg)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
319
REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
323
union dmub_gpint_data_register reg)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
327
reg.bits.status = 0;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
330
return test.all == reg.all;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
37
#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
40
#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
47
#define DMUB_SF(reg, field) FD_MASK(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c
51
#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
158
#define DMUB_SR(reg) uint32_t reg;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
165
#define DMUB_SF(reg, field) uint8_t reg##__##field;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
171
#define DMUB_SF(reg, field) uint32_t reg##__##field;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
228
union dmub_gpint_data_register reg);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
231
union dmub_gpint_data_register reg);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn314.c
43
#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn314.c
48
#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn314.c
55
#define DMUB_SF(reg, field) FD_MASK(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn314.c
59
#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn315.c
43
#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn315.c
48
#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn315.c
55
#define DMUB_SF(reg, field) FD_MASK(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn315.c
59
#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn316.c
43
#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn316.c
48
#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn316.c
55
#define DMUB_SF(reg, field) FD_MASK(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn316.c
59
#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
342
union dmub_gpint_data_register reg)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
344
REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
348
union dmub_gpint_data_register reg)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
352
reg.bits.status = 0;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
355
return test.all == reg.all;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
38
#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
46
#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
51
#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c
55
#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
174
#define DMUB_SR(reg) uint32_t reg;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
181
#define DMUB_SF(reg, field) uint8_t reg##__##field;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
187
#define DMUB_SF(reg, field) uint32_t reg##__##field;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
239
union dmub_gpint_data_register reg);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
242
union dmub_gpint_data_register reg);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
348
union dmub_gpint_data_register reg)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
350
REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
354
union dmub_gpint_data_register reg)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
358
reg.bits.status = 0;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
361
return test.all == reg.all;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
38
#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
44
#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
49
#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c
53
#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
176
#define DMUB_SR(reg) uint32_t reg;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
183
#define DMUB_SF(reg, field) uint8_t reg##__##field;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
189
#define DMUB_SF(reg, field) uint32_t reg##__##field;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
246
union dmub_gpint_data_register reg);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
249
union dmub_gpint_data_register reg);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn351.c
14
#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn351.c
21
#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn351.c
26
#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn351.c
30
#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn36.c
14
#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn36.c
21
#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn36.c
26
#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn36.c
30
#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
17
#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
20
#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
27
#define DMUB_SF(reg, field) FD_MASK(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
31
#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
328
union dmub_gpint_data_register reg)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
330
REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
334
union dmub_gpint_data_register reg)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
338
reg.bits.status = 0;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c
341
return test.all == reg.all;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
176
#define DMUB_SR(reg) uint32_t reg;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
183
#define DMUB_SF(reg, field) uint8_t reg##__##field;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
189
#define DMUB_SF(reg, field) uint32_t reg##__##field;
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
243
union dmub_gpint_data_register reg);
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
246
union dmub_gpint_data_register reg);
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
100
FN(reg, f2), v2, \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
101
FN(reg, f3), v3)
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
103
#define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
104
REG_UPDATE_N(reg, 4, \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
105
FN(reg, f1), v1, \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
106
FN(reg, f2), v2, \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
107
FN(reg, f3), v3, \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
108
FN(reg, f4), v4)
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
43
#define REG(reg) (REGS)->offset.reg
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
51
#define REG_READ(reg) ((CTX)->funcs.reg_read((CTX)->user_ctx, REG(reg)))
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
53
#define REG_WRITE(reg, val) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
54
((CTX)->funcs.reg_write((CTX)->user_ctx, REG(reg), (val)))
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
65
#define REG_SET_2(reg, init_value, f1, v1, f2, v2) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
66
REG_SET_N(reg, 2, init_value, \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
67
FN(reg, f1), v1, \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
68
FN(reg, f2), v2)
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
70
#define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
71
REG_SET_N(reg, 3, init_value, \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
72
FN(reg, f1), v1, \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
73
FN(reg, f2), v2, \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
74
FN(reg, f3), v3)
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
76
#define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
77
REG_SET_N(reg, 4, init_value, \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
78
FN(reg, f1), v1, \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
79
FN(reg, f2), v2, \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
80
FN(reg, f3), v3, \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
81
FN(reg, f4), v4)
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
92
#define REG_UPDATE_2(reg, f1, v1, f2, v2) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
93
REG_UPDATE_N(reg, 2,\
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
94
FN(reg, f1), v1,\
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
95
FN(reg, f2), v2)
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
97
#define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
98
REG_UPDATE_N(reg, 3, \
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
99
FN(reg, f1), v1, \
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
1021
union dmub_gpint_data_register reg;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
1033
reg.bits.status = 1;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
1034
reg.bits.command_code = command_code;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
1035
reg.bits.param = param;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
1037
dmub->hw_funcs.set_gpint(dmub, reg);
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
1042
if (dmub->hw_funcs.is_gpint_acked(dmub, reg))
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
596
const struct dmub_region *reg =
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
600
out->fb[i].cpu_addr = (uint8_t *)params->cpu_gart_addr + reg->base;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
601
out->fb[i].gpu_addr = params->gpu_gart_addr + reg->base;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
603
out->fb[i].cpu_addr = (uint8_t *)params->cpu_fb_addr + reg->base;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
604
out->fb[i].gpu_addr = params->gpu_fb_addr + reg->base;
sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c
607
out->fb[i].size = reg->top - reg->base;
sys/dev/pci/drm/amd/include/cgs_common.h
120
#define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
sys/dev/pci/drm/amd/include/cgs_common.h
121
#define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK
sys/dev/pci/drm/amd/include/cgs_common.h
123
#define CGS_REG_SET_FIELD(orig_val, reg, field, field_val) \
sys/dev/pci/drm/amd/include/cgs_common.h
124
(((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) | \
sys/dev/pci/drm/amd/include/cgs_common.h
125
(CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field))))
sys/dev/pci/drm/amd/include/cgs_common.h
127
#define CGS_REG_GET_FIELD(value, reg, field) \
sys/dev/pci/drm/amd/include/cgs_common.h
128
(((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field))
sys/dev/pci/drm/amd/include/cgs_common.h
130
#define CGS_WREG32_FIELD(device, reg, field, val) \
sys/dev/pci/drm/amd/include/cgs_common.h
131
cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
sys/dev/pci/drm/amd/include/cgs_common.h
133
#define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \
sys/dev/pci/drm/amd/include/cgs_common.h
134
cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2768
u32 load_line_slope, reg;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2779
reg = RREG32(mmCG_CAC_CTRL) & ~CG_CAC_CTRL__CAC_WINDOW_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2780
reg |= (si_pi->powertune_data->cac_window << CG_CAC_CTRL__CAC_WINDOW__SHIFT);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2781
WREG32(mmCG_CAC_CTRL, reg);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4890
u32 reg;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4968
reg = 0xffff << CG_AT__CG_R__SHIFT | 0 << CG_AT__CG_L__SHIFT;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4969
table->initialState.level.aT = cpu_to_be32(reg);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4994
reg = SQ_POWER_THROTTLE__MIN_POWER_MASK |
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4996
table->initialState.level.SQPowerThrottle = cpu_to_be32(reg);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
4998
reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK |
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5001
table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5048
u32 reg;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5164
reg = SQ_POWER_THROTTLE__MIN_POWER_MASK | SQ_POWER_THROTTLE__MAX_POWER_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5165
table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5167
reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK | SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK | SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5168
table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
106
u32 i, reg = 0;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
112
reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg]
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
114
if (!baco_cmd_handler(hwmgr, entry[i].cmd, reg, entry[i].mask,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
27
static bool baco_wait_register(struct pp_hwmgr *hwmgr, u32 reg, u32 mask, u32 value)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
34
data = RREG32(reg);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
44
static bool baco_cmd_handler(struct pp_hwmgr *hwmgr, u32 command, u32 reg, u32 mask,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
53
WREG32(reg, value << shift);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
56
data = RREG32(reg);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
58
WREG32(reg, data);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
61
ret = baco_wait_register(hwmgr, reg, mask, value);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
86
u32 i, reg = 0;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
92
reg = entry[i].reg_offset;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/common_baco.c
93
if (!baco_cmd_handler(hwmgr, entry[i].cmd, reg, entry[i].mask,
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
337
uint32_t reg;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
340
reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
341
if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) ==
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_baco.c
39
uint32_t reg;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_baco.c
44
reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_baco.c
46
if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_baco.c
55
uint32_t reg;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_baco.c
57
reg = RREG32(mmBACO_CNTL);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_baco.c
59
if (reg & BACO_CNTL__BACO_MODE_MASK)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu9_baco.c
34
uint32_t reg, data;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu9_baco.c
43
reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu9_baco.c
45
if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu9_baco.c
55
uint32_t reg;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu9_baco.c
57
reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu9_baco.c
59
if (reg & BACO_CNTL__BACO_MODE_MASK)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
137
#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
138
#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
140
#define PHM_SET_FIELD(origval, reg, field, fieldval) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
141
(((origval) & ~PHM_FIELD_MASK(reg, field)) | \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
142
(PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
144
#define PHM_GET_FIELD(value, reg, field) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
145
(((value) & PHM_FIELD_MASK(reg, field)) >> \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
146
PHM_FIELD_SHIFT(reg, field))
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
151
#define PHM_READ_FIELD(device, reg, field) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
152
PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
154
#define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
155
PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
156
reg, field)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
158
#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
159
PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
160
reg, field)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
162
#define PHM_WRITE_FIELD(device, reg, field, fieldval) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
163
cgs_write_register(device, mm##reg, PHM_SET_FIELD( \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
164
cgs_read_register(device, mm##reg), reg, field, fieldval))
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
166
#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
167
cgs_write_ind_register(device, port, ix##reg, \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
168
PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
169
reg, field, fieldval))
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
171
#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
172
cgs_write_ind_register(device, port, ix##reg, \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
173
PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
174
reg, field, fieldval))
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
180
#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
181
PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
183
#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
184
PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
185
<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
191
#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
192
PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
194
#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
195
PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
196
(fieldval) << PHM_FIELD_SHIFT(reg, field), \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
197
PHM_FIELD_MASK(reg, field))
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
205
#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
206
PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
208
#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
209
PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
210
(fieldval) << PHM_FIELD_SHIFT(reg, field), \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
211
PHM_FIELD_MASK(reg, field))
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
219
#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
220
PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
222
#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
223
PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
224
(fieldval) << PHM_FIELD_SHIFT(reg, field), \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
225
PHM_FIELD_MASK(reg, field))
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
232
#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
234
mm##reg, value, mask)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
236
#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
237
PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
238
(fieldval) << PHM_FIELD_SHIFT(reg, field), \
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu_helper.h
239
PHM_FIELD_MASK(reg, field))
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_baco.c
42
uint32_t reg;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_baco.c
48
reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_baco.c
50
if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_baco.c
60
uint32_t reg;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_baco.c
62
reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega20_baco.c
64
if (reg & BACO_CNTL__BACO_MODE_MASK)
sys/dev/pci/drm/amd/pm/powerplay/inc/polaris10_pwrvirus.h
34
uint32_t reg;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c
52
uint32_t reg;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c
54
reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c
56
phm_wait_for_register_unequal(hwmgr, reg,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c
462
uint32_t reg, data;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c
465
reg = pvirus->reg;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c
467
if (reg != 0xffffffff)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c
468
cgs_write_register(hwmgr->device, reg, data);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c
62
uint32_t reg;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c
66
reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_103);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c
68
ret = phm_wait_for_register_unequal(hwmgr, reg,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c
76
reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c
78
ret = phm_wait_for_register_unequal(hwmgr, reg,
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c
73
uint32_t reg;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c
75
reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c
77
phm_wait_for_register_unequal(hwmgr, reg,
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2987
uint32_t reg;
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2989
reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2990
smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
2999
reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
3000
smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
2307
u32 reg, gfxoff_status;
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
2309
reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);
sys/dev/pci/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
2310
gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c
147
uint32_t reg;
sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c
151
reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);
sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c
152
gfxOff_Status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
626
uint32_t reg;
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
630
reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL);
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
631
gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
114
u32 reg;
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
117
reg = RREG32(smu->resp_reg);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
118
if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0)
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
124
return reg;
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
326
u32 reg;
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
341
reg = __smu_cmn_poll_stat(smu);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
342
res = __smu_cmn_reg2errno(smu, reg);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
343
if (reg == SMU_RESP_NONE || res == -EREMOTEIO)
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
371
u32 reg;
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
374
reg = __smu_cmn_poll_stat(smu);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
375
res = __smu_cmn_reg2errno(smu, reg);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
429
u32 reg;
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
459
reg = __smu_cmn_poll_stat(smu);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
460
res = __smu_cmn_reg2errno(smu, reg);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
461
if (reg == SMU_RESP_NONE || res == -EREMOTEIO) {
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
462
__smu_cmn_reg_print_error(smu, reg, index, param, msg);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
467
reg = __smu_cmn_poll_stat(smu);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
468
res = __smu_cmn_reg2errno(smu, reg);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
472
__smu_cmn_reg_print_error(smu, reg, index, param, msg);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
477
smu_get_message_name(smu, msg), index, param, reg, *read_arg);
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
480
smu_get_message_name(smu, msg), index, param, reg);
sys/dev/pci/drm/apple/apldcp.c
138
uint64_t reg[2];
sys/dev/pci/drm/apple/apldcp.c
156
if (OF_getpropint64array(node, "reg", reg,
sys/dev/pci/drm/apple/apldcp.c
157
sizeof(reg)) != sizeof(reg))
sys/dev/pci/drm/apple/apldcp.c
168
return (reg[0] + (addr - start)) | PMAP_NOCACHE;
sys/dev/pci/drm/apple/apldcp.c
173
return (reg[0] + (trunc_addr - start)) | PMAP_NOCACHE;
sys/dev/pci/drm/apple/apldrm.c
323
uint64_t reg[2];
sys/dev/pci/drm/apple/apldrm.c
331
if (OF_getpropint64array(node, "reg", reg,
sys/dev/pci/drm/apple/apldrm.c
332
sizeof(reg)) == sizeof(reg))
sys/dev/pci/drm/apple/apldrm.c
333
rasops_claim_framebuffer(reg[0], reg[1], self);
sys/dev/pci/drm/apple/dcp-internal.h
57
u64 reg;
sys/dev/pci/drm/apple/iomfb_template.c
394
memdesc->reg = 0;
sys/dev/pci/drm/apple/iomfb_template.c
439
dcp->memdesc[id].reg = req->paddr;
sys/dev/pci/drm/drm_linux.c
2988
pcireg_t reg;
sys/dev/pci/drm/drm_linux.c
2997
reg = pci_conf_read(pdev->pc, pdev->tag, offset);
sys/dev/pci/drm/drm_linux.c
2998
capid = PCI_PCIE_ECAP_ID(reg);
sys/dev/pci/drm/drm_linux.c
3001
offset = PCI_PCIE_ECAP_NEXT(reg);
sys/dev/pci/drm/drm_linux.c
3009
reg = pci_conf_read(pdev->pc, pdev->tag, offset + RBCAP0);
sys/dev/pci/drm/drm_linux.c
3011
if ((reg & (1 << (nsize + 4))) == 0) {
sys/dev/pci/drm/drm_linux.c
3016
reg = pci_conf_read(pdev->pc, pdev->tag, offset + RBCTRL0);
sys/dev/pci/drm/drm_linux.c
3017
if ((reg & RBCTRL_BARINDEX_MASK) != 0) {
sys/dev/pci/drm/drm_linux.c
3022
reg &= ~RBCTRL_BARSIZE_MASK;
sys/dev/pci/drm/drm_linux.c
3023
reg |= (nsize << RBCTRL_BARSIZE_SHIFT) & RBCTRL_BARSIZE_MASK;
sys/dev/pci/drm/drm_linux.c
3025
pci_conf_write(pdev->pc, pdev->tag, offset + RBCTRL0, reg);
sys/dev/pci/drm/drm_linux.c
3890
uint64_t reg[16] = {};
sys/dev/pci/drm/drm_linux.c
3895
len = OF_getpropint64array((uintptr_t)np, "reg", reg, sizeof(reg));
sys/dev/pci/drm/drm_linux.c
3899
res->start = reg[2 * idx];
sys/dev/pci/drm/drm_linux.c
3900
res->end = reg[2 * idx] + reg[2 * idx + 1] - 1;
sys/dev/pci/drm/drm_mipi_dsi.c
168
u32 reg;
sys/dev/pci/drm/drm_mipi_dsi.c
175
ret = of_property_read_u32(node, "reg", ®);
sys/dev/pci/drm/drm_mipi_dsi.c
182
info.channel = reg;
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
20
#define _BXT_PHY(phy, reg) \
sys/dev/pci/drm/i915/display/bxt_dpio_phy_regs.h
21
_MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
sys/dev/pci/drm/i915/display/dvo_ch7017.c
381
#define DUMP(reg) \
sys/dev/pci/drm/i915/display/dvo_ch7017.c
383
ch7017_read(dvo, reg, &val); \
sys/dev/pci/drm/i915/display/dvo_ch7017.c
384
DRM_DEBUG_KMS(#reg ": %02x\n", val); \
sys/dev/pci/drm/i915/display/i9xx_plane.c
912
u32 reg;
sys/dev/pci/drm/i915/display/i9xx_plane.c
919
reg = intel_de_read_fw(display, DSPSURF(display, i9xx_plane));
sys/dev/pci/drm/i915/display/i9xx_plane.c
920
intel_de_write_fw(display, DSPSURF(display, i9xx_plane), reg);
sys/dev/pci/drm/i915/display/i9xx_plane.c
923
reg = intel_de_read_fw(display, DSPADDR(display, i9xx_plane));
sys/dev/pci/drm/i915/display/i9xx_plane.c
924
intel_de_write_fw(display, DSPADDR(display, i9xx_plane), reg);
sys/dev/pci/drm/i915/display/i9xx_wm.c
657
u32 reg;
sys/dev/pci/drm/i915/display/i9xx_wm.c
679
reg = intel_de_read(display, DSPFW1(display));
sys/dev/pci/drm/i915/display/i9xx_wm.c
680
reg &= ~DSPFW_SR_MASK;
sys/dev/pci/drm/i915/display/i9xx_wm.c
681
reg |= FW_WM(wm, SR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
682
intel_de_write(display, DSPFW1(display), reg);
sys/dev/pci/drm/i915/display/i9xx_wm.c
683
drm_dbg_kms(display->drm, "DSPFW1 register is %x\n", reg);
sys/dev/pci/drm/i915/display/i9xx_wm.c
706
reg = intel_de_read(display, DSPFW3(display));
sys/dev/pci/drm/i915/display/i9xx_wm.c
707
reg &= ~DSPFW_HPLL_CURSOR_MASK;
sys/dev/pci/drm/i915/display/i9xx_wm.c
708
reg |= FW_WM(wm, HPLL_CURSOR);
sys/dev/pci/drm/i915/display/i9xx_wm.c
709
intel_de_write(display, DSPFW3(display), reg);
sys/dev/pci/drm/i915/display/i9xx_wm.c
710
drm_dbg_kms(display->drm, "DSPFW3 register is %x\n", reg);
sys/dev/pci/drm/i915/display/intel_color.c
1338
i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_color.c
1343
intel_dsb_reg_write(crtc_state->dsb_color, reg, val);
sys/dev/pci/drm/i915/display/intel_color.c
1345
intel_de_write_fw(display, reg, val);
sys/dev/pci/drm/i915/display/intel_color.c
1349
i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_color.c
1354
intel_dsb_reg_write_indexed(crtc_state->dsb_color, reg, val);
sys/dev/pci/drm/i915/display/intel_color.c
1356
intel_de_write_fw(display, reg, val);
sys/dev/pci/drm/i915/display/intel_combo_phy.c
105
reg.reg, val, mask, expected_val);
sys/dev/pci/drm/i915/display/intel_combo_phy.c
95
enum phy phy, i915_reg_t reg, u32 mask,
sys/dev/pci/drm/i915/display/intel_combo_phy.c
98
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_ddi.c
1552
static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_ddi.c
1557
intel_de_rmw(display, reg, clk_sel_mask, clk_sel);
sys/dev/pci/drm/i915/display/intel_ddi.c
1563
intel_de_rmw(display, reg, clk_off, 0);
sys/dev/pci/drm/i915/display/intel_ddi.c
1568
static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_ddi.c
1573
intel_de_rmw(display, reg, 0, clk_off);
sys/dev/pci/drm/i915/display/intel_ddi.c
1578
static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_ddi.c
1581
return !(intel_de_read(display, reg) & clk_off);
sys/dev/pci/drm/i915/display/intel_ddi.c
1585
_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_ddi.c
1590
id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
sys/dev/pci/drm/i915/display/intel_ddi.c
2555
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_ddi.c
2563
reg = DDI_BUF_CTL(port);
sys/dev/pci/drm/i915/display/intel_ddi.c
2567
reg = XELPDP_PORT_BUF_CTL1(display, port);
sys/dev/pci/drm/i915/display/intel_ddi.c
2572
intel_de_rmw(display, reg, 0, set_bits);
sys/dev/pci/drm/i915/display/intel_ddi.c
2574
ret = intel_de_wait_custom(display, reg,
sys/dev/pci/drm/i915/display/intel_ddi.c
3057
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_ddi.c
3065
reg = DDI_BUF_CTL(port);
sys/dev/pci/drm/i915/display/intel_ddi.c
3069
reg = XELPDP_PORT_BUF_CTL1(display, port);
sys/dev/pci/drm/i915/display/intel_ddi.c
3074
intel_de_rmw(display, reg, clr_bits, 0);
sys/dev/pci/drm/i915/display/intel_ddi.c
3076
ret = intel_de_wait_custom(display, reg,
sys/dev/pci/drm/i915/display/intel_ddi.c
3439
i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port);
sys/dev/pci/drm/i915/display/intel_ddi.c
3442
val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_ddi.c
3451
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_ddi.c
3452
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_ddi.c
3463
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_de.h
100
val = __intel_de_rmw_nowl(display, reg, clear, set);
sys/dev/pci/drm/i915/display/intel_de.h
102
intel_dmc_wl_put(display, reg);
sys/dev/pci/drm/i915/display/intel_de.h
109
i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_de.h
112
return intel_wait_for_register(__to_uncore(display), reg, mask,
sys/dev/pci/drm/i915/display/intel_de.h
118
i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_de.h
122
return __intel_wait_for_register(__to_uncore(display), reg, mask,
sys/dev/pci/drm/i915/display/intel_de.h
127
intel_de_wait(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_de.h
132
intel_dmc_wl_get(display, reg);
sys/dev/pci/drm/i915/display/intel_de.h
134
ret = __intel_de_wait_for_register_nowl(display, reg, mask, value,
sys/dev/pci/drm/i915/display/intel_de.h
137
intel_dmc_wl_put(display, reg);
sys/dev/pci/drm/i915/display/intel_de.h
143
intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_de.h
148
intel_dmc_wl_get(display, reg);
sys/dev/pci/drm/i915/display/intel_de.h
150
ret = intel_wait_for_register_fw(__to_uncore(display), reg, mask,
sys/dev/pci/drm/i915/display/intel_de.h
153
intel_dmc_wl_put(display, reg);
sys/dev/pci/drm/i915/display/intel_de.h
159
intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_de.h
166
intel_dmc_wl_get(display, reg);
sys/dev/pci/drm/i915/display/intel_de.h
168
ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
sys/dev/pci/drm/i915/display/intel_de.h
172
intel_dmc_wl_put(display, reg);
sys/dev/pci/drm/i915/display/intel_de.h
178
intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_de.h
181
return intel_de_wait(display, reg, mask, mask, timeout_ms);
sys/dev/pci/drm/i915/display/intel_de.h
185
intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_de.h
188
return intel_de_wait(display, reg, mask, 0, timeout_ms);
sys/dev/pci/drm/i915/display/intel_de.h
200
intel_de_read_fw(struct intel_display *display, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_de.h
204
val = intel_uncore_read_fw(__to_uncore(display), reg);
sys/dev/pci/drm/i915/display/intel_de.h
205
trace_i915_reg_rw(false, reg, val, sizeof(val), true);
sys/dev/pci/drm/i915/display/intel_de.h
21
intel_de_read(struct intel_display *display, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_de.h
211
intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_de.h
213
trace_i915_reg_rw(true, reg, val, sizeof(val), true);
sys/dev/pci/drm/i915/display/intel_de.h
214
intel_uncore_write_fw(__to_uncore(display), reg, val);
sys/dev/pci/drm/i915/display/intel_de.h
218
intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_de.h
220
return intel_uncore_read_notrace(__to_uncore(display), reg);
sys/dev/pci/drm/i915/display/intel_de.h
224
intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_de.h
226
intel_uncore_write_notrace(__to_uncore(display), reg, val);
sys/dev/pci/drm/i915/display/intel_de.h
231
i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_de.h
234
intel_dsb_reg_write(dsb, reg, val);
sys/dev/pci/drm/i915/display/intel_de.h
236
intel_de_write_fw(display, reg, val);
sys/dev/pci/drm/i915/display/intel_de.h
25
intel_dmc_wl_get(display, reg);
sys/dev/pci/drm/i915/display/intel_de.h
27
val = intel_uncore_read(__to_uncore(display), reg);
sys/dev/pci/drm/i915/display/intel_de.h
29
intel_dmc_wl_put(display, reg);
sys/dev/pci/drm/i915/display/intel_de.h
35
intel_de_read8(struct intel_display *display, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_de.h
39
intel_dmc_wl_get(display, reg);
sys/dev/pci/drm/i915/display/intel_de.h
41
val = intel_uncore_read8(__to_uncore(display), reg);
sys/dev/pci/drm/i915/display/intel_de.h
43
intel_dmc_wl_put(display, reg);
sys/dev/pci/drm/i915/display/intel_de.h
67
intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_de.h
69
intel_dmc_wl_get(display, reg);
sys/dev/pci/drm/i915/display/intel_de.h
71
intel_uncore_posting_read(__to_uncore(display), reg);
sys/dev/pci/drm/i915/display/intel_de.h
73
intel_dmc_wl_put(display, reg);
sys/dev/pci/drm/i915/display/intel_de.h
77
intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_de.h
79
intel_dmc_wl_get(display, reg);
sys/dev/pci/drm/i915/display/intel_de.h
81
intel_uncore_write(__to_uncore(display), reg, val);
sys/dev/pci/drm/i915/display/intel_de.h
83
intel_dmc_wl_put(display, reg);
sys/dev/pci/drm/i915/display/intel_de.h
87
__intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_de.h
90
return intel_uncore_rmw(__to_uncore(display), reg, clear, set);
sys/dev/pci/drm/i915/display/intel_de.h
94
intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
sys/dev/pci/drm/i915/display/intel_de.h
98
intel_dmc_wl_get(display, reg);
sys/dev/pci/drm/i915/display/intel_display.c
157
const char *name, u32 reg, int ref_freq)
sys/dev/pci/drm/i915/display/intel_display.c
162
val = vlv_cck_read(drm, reg);
sys/dev/pci/drm/i915/display/intel_display.c
173
const char *name, u32 reg)
sys/dev/pci/drm/i915/display/intel_display.c
183
hpll = vlv_get_cck_clock(drm, name, reg, dev_priv->hpll_freq);
sys/dev/pci/drm/i915/display/intel_display.h
440
const char *name, u32 reg, int ref_freq);
sys/dev/pci/drm/i915/display/intel_display.h
442
const char *name, u32 reg);
sys/dev/pci/drm/i915/display/intel_display_irq.c
326
i915_reg_t reg = PIPESTAT(display, pipe);
sys/dev/pci/drm/i915/display/intel_display_irq.c
342
intel_de_write(display, reg, enable_mask | status_mask);
sys/dev/pci/drm/i915/display/intel_display_irq.c
343
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_display_irq.c
350
i915_reg_t reg = PIPESTAT(display, pipe);
sys/dev/pci/drm/i915/display/intel_display_irq.c
366
intel_de_write(display, reg, enable_mask | status_mask);
sys/dev/pci/drm/i915/display/intel_display_irq.c
367
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_display_irq.c
527
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_display_irq.c
559
reg = PIPESTAT(display, pipe);
sys/dev/pci/drm/i915/display/intel_display_irq.c
560
pipe_stats[pipe] = intel_de_read(display, reg) & status_mask;
sys/dev/pci/drm/i915/display/intel_display_irq.c
573
intel_de_write(display, reg, pipe_stats[pipe]);
sys/dev/pci/drm/i915/display/intel_display_irq.c
574
intel_de_write(display, reg, enable_mask);
sys/dev/pci/drm/i915/display/intel_display_irq.c
65
intel_display_irq_regs_assert_irr_is_zero(struct intel_display *display, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_display_irq.c
67
intel_dmc_wl_get(display, reg);
sys/dev/pci/drm/i915/display/intel_display_irq.c
69
gen2_assert_iir_is_zero(to_intel_uncore(display->drm), reg);
sys/dev/pci/drm/i915/display/intel_display_irq.c
71
intel_dmc_wl_put(display, reg);
sys/dev/pci/drm/i915/display/intel_display_power.c
1073
i915_reg_t reg = DBUF_CTL_S(slice);
sys/dev/pci/drm/i915/display/intel_display_power.c
1076
intel_de_rmw(display, reg, DBUF_POWER_REQUEST,
sys/dev/pci/drm/i915/display/intel_display_power.c
1078
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_display_power.c
1081
state = intel_de_read(display, reg) & DBUF_POWER_STATE;
sys/dev/pci/drm/i915/display/intel_display_power.c
1438
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_display_power.c
1442
reg = GEN7_MSG_CTL;
sys/dev/pci/drm/i915/display/intel_display_power.c
1445
reg = HSW_NDE_RSTWRN_OPT;
sys/dev/pci/drm/i915/display/intel_display_power.c
1452
intel_de_rmw(display, reg, reset_bits, enable ? reset_bits : 0);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1560
u32 reg, val, expected, actual;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1573
reg = CHV_CMN_DW0_CH0;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1575
reg = CHV_CMN_DW6_CH1;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1578
val = vlv_dpio_read(display->drm, phy, reg);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
1618
reg, val);
sys/dev/pci/drm/i915/display/intel_display_power_well.c
313
if (regs->kvmr.reg)
sys/dev/pci/drm/i915/display/intel_display_reg_defs.h
39
#define _MMIO_PIPE2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->pipe_offsets[(pipe)] - \
sys/dev/pci/drm/i915/display/intel_display_reg_defs.h
41
DISPLAY_MMIO_BASE(display) + (reg))
sys/dev/pci/drm/i915/display/intel_display_reg_defs.h
42
#define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \
sys/dev/pci/drm/i915/display/intel_display_reg_defs.h
44
DISPLAY_MMIO_BASE(display) + (reg))
sys/dev/pci/drm/i915/display/intel_display_reg_defs.h
45
#define _MMIO_CURSOR2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->cursor_offsets[(pipe)] - \
sys/dev/pci/drm/i915/display/intel_display_reg_defs.h
47
DISPLAY_MMIO_BASE(display) + (reg))
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
109
intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
113
dkl_phy_set_hip_idx(display, reg);
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
114
intel_de_posting_read(display, DKL_REG_MMIO(reg));
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
24
dkl_phy_set_hip_idx(struct intel_display *display, struct intel_dkl_phy_reg reg)
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
26
enum tc_port tc_port = DKL_REG_TC_PORT(reg);
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
34
HIP_INDEX_VAL(tc_port, reg.bank_idx));
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
47
intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
53
dkl_phy_set_hip_idx(display, reg);
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
54
val = intel_de_read(display, DKL_REG_MMIO(reg));
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
70
intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val)
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
74
dkl_phy_set_hip_idx(display, reg);
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
75
intel_de_write(display, DKL_REG_MMIO(reg), val);
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
91
intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set)
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
95
dkl_phy_set_hip_idx(display, reg);
sys/dev/pci/drm/i915/display/intel_dkl_phy.c
96
intel_de_rmw(display, DKL_REG_MMIO(reg), clear, set);
sys/dev/pci/drm/i915/display/intel_dkl_phy.h
17
intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg);
sys/dev/pci/drm/i915/display/intel_dkl_phy.h
19
intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val);
sys/dev/pci/drm/i915/display/intel_dkl_phy.h
21
intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set);
sys/dev/pci/drm/i915/display/intel_dkl_phy.h
23
intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg);
sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h
14
u32 reg:24;
sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h
26
(TC_PORT_1 + ((__reg).reg - _DKL_PHY1_BASE) / (_DKL_PHY2_BASE - _DKL_PHY1_BASE))
sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h
29
#define DKL_REG_MMIO(__reg) _MMIO((__reg).reg)
sys/dev/pci/drm/i915/display/intel_dkl_phy_regs.h
43
.reg = _DKL_REG_PHY_BASE(tc_port) + \
sys/dev/pci/drm/i915/display/intel_dmc.c
525
enum intel_dmc_id dmc_id, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_dmc.c
527
u32 offset = i915_mmio_reg_offset(reg);
sys/dev/pci/drm/i915/display/intel_dmc.c
535
enum intel_dmc_id dmc_id, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_dmc.c
537
u32 offset = i915_mmio_reg_offset(reg);
sys/dev/pci/drm/i915/display/intel_dmc.c
547
i915_reg_t reg, u32 data)
sys/dev/pci/drm/i915/display/intel_dmc.c
549
return is_dmc_evt_ctl_reg(display, dmc_id, reg) &&
sys/dev/pci/drm/i915/display/intel_dmc.c
585
i915_reg_t reg, u32 data)
sys/dev/pci/drm/i915/display/intel_dmc.c
587
if (!is_dmc_evt_ctl_reg(display, dmc_id, reg))
sys/dev/pci/drm/i915/display/intel_dmc.c
596
is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data))
sys/dev/pci/drm/i915/display/intel_dmc.c
601
is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg, data))
sys/dev/pci/drm/i915/display/intel_dmc.c
668
i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];
sys/dev/pci/drm/i915/display/intel_dmc.c
670
found = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_dmc.c
674
if (is_dmc_evt_ctl_reg(display, dmc_id, reg)) {
sys/dev/pci/drm/i915/display/intel_dmc.c
681
dmc_id, i, i915_mmio_reg_offset(reg), expected, found);
sys/dev/pci/drm/i915/display/intel_dmc.c
825
i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];
sys/dev/pci/drm/i915/display/intel_dmc.c
828
if (!is_event_handler(display, dmc_id, event_id, reg, data))
sys/dev/pci/drm/i915/display/intel_dmc.c
831
intel_de_write(display, reg, enable ? data : dmc_evt_ctl_disable());
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
477
#define _DMC_REG(i915, dmc_id, reg) \
sys/dev/pci/drm/i915/display/intel_dmc_regs.h
478
((reg) - __DMC_REG_MMIO_BASE + _DMC_REG_MMIO_BASE(i915, dmc_id))
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
228
static bool intel_dmc_wl_reg_in_range(i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
231
u32 offset = i915_mmio_reg_offset(reg);
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
244
i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
256
if (intel_dmc_wl_reg_in_range(reg, powered_off_ranges))
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
275
if (ranges && intel_dmc_wl_reg_in_range(reg, ranges))
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
435
void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
445
if (i915_mmio_reg_valid(reg) &&
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
446
!intel_dmc_wl_check_range(display, reg, wl->dc_state))
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
468
void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
478
if (i915_mmio_reg_valid(reg) &&
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
479
!intel_dmc_wl_check_range(display, reg, wl->dc_state))
sys/dev/pci/drm/i915/display/intel_dmc_wl.h
36
void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg);
sys/dev/pci/drm/i915/display/intel_dmc_wl.h
37
void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg);
sys/dev/pci/drm/i915/display/intel_dp.c
4838
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_dp.c
4846
u32 val = intel_de_read(display, reg) & ~dip_enable;
sys/dev/pci/drm/i915/display/intel_dp.c
4859
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_dp.c
4860
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1096
int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
1099
return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
534
int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
546
return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
646
int reg = dp_phy == DP_PHY_DPRX ?
sys/dev/pci/drm/i915/display/intel_dp_link_training.c
653
ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
515
i915_reg_t reg, u32 mask, u32 expected,
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
522
val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
532
phy, &vaf, reg.reg, val, (val & ~mask) | expected,
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
549
#define _CHK(reg, mask, exp, fmt, ...) \
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
550
__phy_reg_verify_state(display, phy, reg, mask, exp, fmt, \
sys/dev/pci/drm/i915/display/intel_dsb.c
289
u32 opcode, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_dsb.c
304
return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg);
sys/dev/pci/drm/i915/display/intel_dsb.c
307
static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_dsb.c
311
reg);
sys/dev/pci/drm/i915/display/intel_dsb.c
328
i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_dsb.c
346
if (!intel_dsb_prev_ins_is_indexed_write(dsb, reg))
sys/dev/pci/drm/i915/display/intel_dsb.c
349
i915_mmio_reg_offset(reg));
sys/dev/pci/drm/i915/display/intel_dsb.c
366
i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_dsb.c
371
i915_mmio_reg_offset(reg));
sys/dev/pci/drm/i915/display/intel_dsb.c
384
i915_reg_t reg, u32 mask, u32 val)
sys/dev/pci/drm/i915/display/intel_dsb.c
389
i915_mmio_reg_offset(reg));
sys/dev/pci/drm/i915/display/intel_dsb.c
514
i915_reg_t reg, u32 mask, u32 val,
sys/dev/pci/drm/i915/display/intel_dsb.c
529
i915_mmio_reg_offset(reg));
sys/dev/pci/drm/i915/display/intel_dsb.h
40
i915_reg_t reg, u32 val);
sys/dev/pci/drm/i915/display/intel_dsb.h
42
i915_reg_t reg, u32 val);
sys/dev/pci/drm/i915/display/intel_dsb.h
44
i915_reg_t reg, u32 mask, u32 val);
sys/dev/pci/drm/i915/display/intel_dsb.h
62
i915_reg_t reg, u32 mask, u32 val,
sys/dev/pci/drm/i915/display/intel_fdi.c
1000
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_fdi.c
1004
reg = FDI_RX_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
1005
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
1009
intel_de_write(display, reg, temp | FDI_RX_PLL_ENABLE);
sys/dev/pci/drm/i915/display/intel_fdi.c
1011
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
1015
intel_de_rmw(display, reg, 0, FDI_PCDCLK);
sys/dev/pci/drm/i915/display/intel_fdi.c
1016
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
1020
reg = FDI_TX_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
1021
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
1023
intel_de_write(display, reg, temp | FDI_TX_PLL_ENABLE);
sys/dev/pci/drm/i915/display/intel_fdi.c
1025
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
1053
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_fdi.c
1060
reg = FDI_RX_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
1061
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
1064
intel_de_write(display, reg, temp & ~FDI_RX_ENABLE);
sys/dev/pci/drm/i915/display/intel_fdi.c
1066
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
1078
reg = FDI_RX_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
1079
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
1090
intel_de_write(display, reg, temp);
sys/dev/pci/drm/i915/display/intel_fdi.c
1092
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
442
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_fdi.c
446
reg = FDI_TX_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
447
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
455
intel_de_write(display, reg, temp);
sys/dev/pci/drm/i915/display/intel_fdi.c
457
reg = FDI_RX_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
458
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
466
intel_de_write(display, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
sys/dev/pci/drm/i915/display/intel_fdi.c
469
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
474
intel_de_rmw(display, reg, 0, FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
sys/dev/pci/drm/i915/display/intel_fdi.c
483
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_fdi.c
498
reg = FDI_RX_IMR(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
499
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
502
intel_de_write(display, reg, temp);
sys/dev/pci/drm/i915/display/intel_fdi.c
503
intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
507
reg = FDI_TX_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
508
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
513
intel_de_write(display, reg, temp | FDI_TX_ENABLE);
sys/dev/pci/drm/i915/display/intel_fdi.c
515
reg = FDI_RX_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
516
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
519
intel_de_write(display, reg, temp | FDI_RX_ENABLE);
sys/dev/pci/drm/i915/display/intel_fdi.c
521
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
530
reg = FDI_RX_IIR(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
532
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
537
intel_de_write(display, reg, temp | FDI_RX_BIT_LOCK);
sys/dev/pci/drm/i915/display/intel_fdi.c
552
reg = FDI_RX_IIR(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
554
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
558
intel_de_write(display, reg,
sys/dev/pci/drm/i915/display/intel_fdi.c
584
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_fdi.c
596
reg = FDI_RX_IMR(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
597
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
600
intel_de_write(display, reg, temp);
sys/dev/pci/drm/i915/display/intel_fdi.c
602
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
606
reg = FDI_TX_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
607
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
615
intel_de_write(display, reg, temp | FDI_TX_ENABLE);
sys/dev/pci/drm/i915/display/intel_fdi.c
620
reg = FDI_RX_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
621
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
629
intel_de_write(display, reg, temp | FDI_RX_ENABLE);
sys/dev/pci/drm/i915/display/intel_fdi.c
631
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
641
reg = FDI_RX_IIR(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
642
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
645
intel_de_write(display, reg,
sys/dev/pci/drm/i915/display/intel_fdi.c
660
reg = FDI_TX_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
661
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
669
intel_de_write(display, reg, temp);
sys/dev/pci/drm/i915/display/intel_fdi.c
671
reg = FDI_RX_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
672
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
680
intel_de_write(display, reg, temp);
sys/dev/pci/drm/i915/display/intel_fdi.c
682
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
692
reg = FDI_RX_IIR(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
693
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
696
intel_de_write(display, reg,
sys/dev/pci/drm/i915/display/intel_fdi.c
719
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_fdi.c
733
reg = FDI_RX_IMR(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
734
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
737
intel_de_write(display, reg, temp);
sys/dev/pci/drm/i915/display/intel_fdi.c
739
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
748
reg = FDI_TX_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
749
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
752
intel_de_write(display, reg, temp);
sys/dev/pci/drm/i915/display/intel_fdi.c
754
reg = FDI_RX_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
755
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
759
intel_de_write(display, reg, temp);
sys/dev/pci/drm/i915/display/intel_fdi.c
762
reg = FDI_TX_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
763
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
770
intel_de_write(display, reg, temp | FDI_TX_ENABLE);
sys/dev/pci/drm/i915/display/intel_fdi.c
775
reg = FDI_RX_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
776
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
779
intel_de_write(display, reg, temp | FDI_RX_ENABLE);
sys/dev/pci/drm/i915/display/intel_fdi.c
781
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
785
reg = FDI_RX_IIR(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
786
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
790
(intel_de_read(display, reg) & FDI_RX_BIT_LOCK)) {
sys/dev/pci/drm/i915/display/intel_fdi.c
791
intel_de_write(display, reg,
sys/dev/pci/drm/i915/display/intel_fdi.c
817
reg = FDI_RX_IIR(pipe);
sys/dev/pci/drm/i915/display/intel_fdi.c
818
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fdi.c
822
(intel_de_read(display, reg) & FDI_RX_SYMBOL_LOCK)) {
sys/dev/pci/drm/i915/display/intel_fdi.c
823
intel_de_write(display, reg,
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
102
if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
106
intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
107
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
117
i915_reg_t reg = PIPESTAT(display, pipe);
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
124
intel_de_write(display, reg,
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
126
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
128
if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS)
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
97
i915_reg_t reg = PIPESTAT(display, crtc->pipe);
sys/dev/pci/drm/i915/display/intel_hdcp.c
820
u32 reg[2];
sys/dev/pci/drm/i915/display/intel_hdcp.c
824
u32 reg[2];
sys/dev/pci/drm/i915/display/intel_hdcp.c
828
u32 reg;
sys/dev/pci/drm/i915/display/intel_hdcp.c
866
an.reg[0] = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_hdcp.c
868
an.reg[1] = intel_de_read(display,
sys/dev/pci/drm/i915/display/intel_hdcp.c
888
bksv.reg[0]);
sys/dev/pci/drm/i915/display/intel_hdcp.c
890
bksv.reg[1]);
sys/dev/pci/drm/i915/display/intel_hdcp.c
933
ri.reg = 0;
sys/dev/pci/drm/i915/display/intel_hdcp.c
939
ri.reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1000
intel_de_write(display, reg, crtc_state->infoframes.gcp);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1010
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1017
reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1019
reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1021
reg = TVIDEO_DIP_GCP(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1025
crtc_state->infoframes.gcp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1059
i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1060
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1074
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1075
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1095
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1096
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1117
i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1118
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1131
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1132
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1144
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1145
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1166
i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1167
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1181
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1182
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1202
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1203
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1221
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1223
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1232
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1233
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1246
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1248
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1259
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1260
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1267
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1268
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1576
u32 reg;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1584
intel_de_write(display, HDCP_RPRIME(display, cpu_transcoder, port), ri.reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
288
i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_hdmi.c
289
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
300
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
315
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
316
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
341
i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_hdmi.c
342
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
363
i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_hdmi.c
364
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
378
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
393
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
394
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
437
i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_hdmi.c
438
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
449
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
465
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
466
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
874
i915_reg_t reg = VIDEO_DIP_CTL;
sys/dev/pci/drm/i915/display/intel_hdmi.c
875
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
902
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
903
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
922
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_hdmi.c
923
intel_de_posting_read(display, reg);
sys/dev/pci/drm/i915/display/intel_hdmi.c
985
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_hdmi.c
992
reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_hdmi.c
994
reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_hdmi.c
996
reg = TVIDEO_DIP_GCP(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_lspcon.c
362
u16 reg;
sys/dev/pci/drm/i915/display/intel_lspcon.c
372
reg = LSPCON_PARADE_AVI_IF_WRITE_OFFSET;
sys/dev/pci/drm/i915/display/intel_lspcon.c
374
ret = drm_dp_dpcd_write(aux, reg, data, 8);
sys/dev/pci/drm/i915/display/intel_lspcon.c
387
reg = LSPCON_PARADE_AVI_IF_CTRL;
sys/dev/pci/drm/i915/display/intel_lspcon.c
389
ret = drm_dp_dpcd_write(aux, reg, &avi_if_ctrl, 1);
sys/dev/pci/drm/i915/display/intel_lspcon.c
392
reg, block_count);
sys/dev/pci/drm/i915/display/intel_lspcon.c
441
u16 reg;
sys/dev/pci/drm/i915/display/intel_lspcon.c
444
reg = LSPCON_MCA_AVI_IF_WRITE_OFFSET;
sys/dev/pci/drm/i915/display/intel_lspcon.c
448
ret = drm_dp_dpcd_write(aux, reg, (void *)data, 1);
sys/dev/pci/drm/i915/display/intel_lspcon.c
455
drm_err(aux->drm_dev, "DPCD write failed at:0x%x\n", reg);
sys/dev/pci/drm/i915/display/intel_lspcon.c
459
val++; reg++; data++;
sys/dev/pci/drm/i915/display/intel_lspcon.c
463
reg = LSPCON_MCA_AVI_IF_CTRL;
sys/dev/pci/drm/i915/display/intel_lspcon.c
464
ret = drm_dp_dpcd_read(aux, reg, &val, 1);
sys/dev/pci/drm/i915/display/intel_lspcon.c
466
drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
sys/dev/pci/drm/i915/display/intel_lspcon.c
474
ret = drm_dp_dpcd_write(aux, reg, &val, 1);
sys/dev/pci/drm/i915/display/intel_lspcon.c
476
drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
sys/dev/pci/drm/i915/display/intel_lspcon.c
481
ret = drm_dp_dpcd_read(aux, reg, &val, 1);
sys/dev/pci/drm/i915/display/intel_lspcon.c
483
drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
sys/dev/pci/drm/i915/display/intel_lspcon.c
616
u16 reg = LSPCON_MCA_AVI_IF_CTRL;
sys/dev/pci/drm/i915/display/intel_lspcon.c
618
ret = drm_dp_dpcd_read(aux, reg, &val, 1);
sys/dev/pci/drm/i915/display/intel_lspcon.c
620
drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
sys/dev/pci/drm/i915/display/intel_lspcon.c
631
u16 reg = LSPCON_PARADE_AVI_IF_CTRL;
sys/dev/pci/drm/i915/display/intel_lspcon.c
633
ret = drm_dp_dpcd_read(aux, reg, &val, 1);
sys/dev/pci/drm/i915/display/intel_lspcon.c
635
drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
sys/dev/pci/drm/i915/display/intel_lvds.c
115
ret = intel_lvds_port_enabled(display, lvds_encoder->reg, pipe);
sys/dev/pci/drm/i915/display/intel_lvds.c
131
tmp = intel_de_read(display, lvds_encoder->reg);
sys/dev/pci/drm/i915/display/intel_lvds.c
313
intel_de_write(display, lvds_encoder->reg, temp);
sys/dev/pci/drm/i915/display/intel_lvds.c
327
intel_de_rmw(display, lvds_encoder->reg, 0, LVDS_PORT_EN);
sys/dev/pci/drm/i915/display/intel_lvds.c
330
intel_de_posting_read(display, lvds_encoder->reg);
sys/dev/pci/drm/i915/display/intel_lvds.c
352
intel_de_rmw(display, lvds_encoder->reg, LVDS_PORT_EN, 0);
sys/dev/pci/drm/i915/display/intel_lvds.c
353
intel_de_posting_read(display, lvds_encoder->reg);
sys/dev/pci/drm/i915/display/intel_lvds.c
73
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_lvds.c
820
val = intel_de_read(display, lvds_encoder->reg);
sys/dev/pci/drm/i915/display/intel_lvds.c
939
lvds_encoder->reg = lvds_reg;
sys/dev/pci/drm/i915/display/intel_pch_display.c
251
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_pch_display.c
262
reg = TRANS_CHICKEN2(pipe);
sys/dev/pci/drm/i915/display/intel_pch_display.c
263
val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_pch_display.c
272
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_pch_display.c
275
reg = PCH_TRANSCONF(pipe);
sys/dev/pci/drm/i915/display/intel_pch_display.c
276
val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_pch_display.c
307
intel_de_write(display, reg, val | TRANS_ENABLE);
sys/dev/pci/drm/i915/display/intel_pch_display.c
308
if (intel_de_wait_for_set(display, reg, TRANS_STATE_ENABLE, 100))
sys/dev/pci/drm/i915/display/intel_pch_display.c
317
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_pch_display.c
326
reg = PCH_TRANSCONF(pipe);
sys/dev/pci/drm/i915/display/intel_pch_display.c
327
intel_de_rmw(display, reg, TRANS_ENABLE, 0);
sys/dev/pci/drm/i915/display/intel_pch_display.c
329
if (intel_de_wait_for_clear(display, reg, TRANS_STATE_ENABLE, 50))
sys/dev/pci/drm/i915/display/intel_pch_display.c
421
i915_reg_t reg = TRANS_DP_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_pch_display.c
424
temp = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_pch_display.c
441
intel_de_write(display, reg, temp);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
283
u32 reg, tmp;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
310
reg = HAS_PCH_LPT_LP(display) ? SBI_GEN0 : SBI_DBUFF0;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
311
tmp = intel_sbi_read(display, reg, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
313
intel_sbi_write(display, reg, tmp, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
321
u32 reg, tmp;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
325
reg = HAS_PCH_LPT_LP(display) ? SBI_GEN0 : SBI_DBUFF0;
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
326
tmp = intel_sbi_read(display, reg, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pch_refclk.c
328
intel_sbi_write(display, reg, tmp, SBI_ICLK);
sys/dev/pci/drm/i915/display/intel_pmdemand.c
539
#define update_reg(reg, field, mask) do { \
sys/dev/pci/drm/i915/display/intel_pmdemand.c
540
u32 current_val = serialized ? 0 : REG_FIELD_GET((mask), *(reg)); \
sys/dev/pci/drm/i915/display/intel_pmdemand.c
544
*(reg) &= ~(mask); \
sys/dev/pci/drm/i915/display/intel_pmdemand.c
545
*(reg) |= REG_FIELD_PREP((mask), max3(old_val, new_val, current_val)); \
sys/dev/pci/drm/i915/display/intel_pps_regs.h
16
#define _MMIO_PPS(display, pps_idx, reg) \
sys/dev/pci/drm/i915/display/intel_pps_regs.h
17
_MMIO((display)->pps.mmio_base - PPS_BASE + (reg) + (pps_idx) * 0x100)
sys/dev/pci/drm/i915/display/intel_psr.c
3152
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_psr.c
3161
reg = EDP_PSR2_STATUS(display, cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_psr.c
3164
reg = psr_status_reg(display, cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_psr.c
3170
err = intel_de_wait_for_clear(display, reg, mask, 50);
sys/dev/pci/drm/i915/display/intel_sbi.c
16
static int intel_sbi_rw(struct intel_display *display, u16 reg,
sys/dev/pci/drm/i915/display/intel_sbi.c
29
intel_de_write_fw(display, SBI_ADDR, SBI_ADDR_VALUE(reg));
sys/dev/pci/drm/i915/display/intel_sbi.c
46
drm_err(display->drm, "error during SBI read of reg %x\n", reg);
sys/dev/pci/drm/i915/display/intel_sbi.c
66
u32 intel_sbi_read(struct intel_display *display, u16 reg,
sys/dev/pci/drm/i915/display/intel_sbi.c
71
intel_sbi_rw(display, reg, destination, &result, true);
sys/dev/pci/drm/i915/display/intel_sbi.c
76
void intel_sbi_write(struct intel_display *display, u16 reg, u32 value,
sys/dev/pci/drm/i915/display/intel_sbi.c
79
intel_sbi_rw(display, reg, destination, &value, false);
sys/dev/pci/drm/i915/display/intel_sbi.h
22
u32 intel_sbi_read(struct intel_display *display, u16 reg,
sys/dev/pci/drm/i915/display/intel_sbi.h
24
void intel_sbi_write(struct intel_display *display, u16 reg, u32 value,
sys/dev/pci/drm/i915/display/intel_sdvo.h
21
i915_reg_t reg, enum port port);
sys/dev/pci/drm/i915/display/intel_sdvo.h
29
i915_reg_t reg, enum port port)
sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h
16
#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h
17
_SNPS_PHY_A_BASE + (reg))
sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h
18
#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h
19
#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
sys/dev/pci/drm/i915/display/intel_snps_phy_regs.h
20
(reg) + (ln) * 0x10))
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
351
#define _MMIO_CHV_SPCSC(plane_id, reg) \
sys/dev/pci/drm/i915/display/intel_sprite_regs.h
352
_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
sys/dev/pci/drm/i915/display/intel_tc.c
1044
i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
sys/dev/pci/drm/i915/display/intel_tc.c
1048
return intel_de_read(display, reg) & XELPDP_TCSS_POWER_STATE;
sys/dev/pci/drm/i915/display/intel_tc.c
1104
i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
sys/dev/pci/drm/i915/display/intel_tc.c
1112
val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_tc.c
1117
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_tc.c
1151
i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
sys/dev/pci/drm/i915/display/intel_tc.c
1156
val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_tc.c
1161
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/intel_tc.c
1168
i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
sys/dev/pci/drm/i915/display/intel_tc.c
1172
return intel_de_read(display, reg) & XELPDP_TC_PHY_OWNERSHIP;
sys/dev/pci/drm/i915/display/intel_tc.c
300
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_tc.c
308
reg = TCSS_DDI_STATUS(tc_port);
sys/dev/pci/drm/i915/display/intel_tc.c
311
reg = PORT_TX_DFLEXPA1(tc->phy_fia);
sys/dev/pci/drm/i915/display/intel_tc.c
316
val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/intel_vblank.c
484
i915_reg_t reg = PIPEDSL(display, pipe);
sys/dev/pci/drm/i915/display/intel_vblank.c
487
line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
sys/dev/pci/drm/i915/display/intel_vblank.c
489
line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
sys/dev/pci/drm/i915/display/skl_watermark.c
660
static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
sys/dev/pci/drm/i915/display/skl_watermark.c
663
REG_FIELD_GET(PLANE_BUF_START_MASK, reg),
sys/dev/pci/drm/i915/display/skl_watermark.c
664
REG_FIELD_GET(PLANE_BUF_END_MASK, reg));
sys/dev/pci/drm/i915/display/vlv_dsi.c
103
i915_reg_t reg,
sys/dev/pci/drm/i915/display/vlv_dsi.c
114
intel_de_write(display, reg, val);
sys/dev/pci/drm/i915/display/vlv_dsi.c
119
i915_reg_t reg,
sys/dev/pci/drm/i915/display/vlv_dsi.c
125
u32 val = intel_de_read(display, reg);
sys/dev/pci/drm/i915/display/vlv_sideband.c
24
u32 vlv_dpio_read(struct drm_device *drm, enum dpio_phy phy, int reg)
sys/dev/pci/drm/i915/display/vlv_sideband.c
30
val = vlv_iosf_sb_read(drm, unit, reg);
sys/dev/pci/drm/i915/display/vlv_sideband.c
38
phy, reg, val);
sys/dev/pci/drm/i915/display/vlv_sideband.c
44
enum dpio_phy phy, int reg, u32 val)
sys/dev/pci/drm/i915/display/vlv_sideband.c
49
vlv_iosf_sb_write(drm, unit, reg, val);
sys/dev/pci/drm/i915/display/vlv_sideband.h
106
static inline u32 vlv_flisdsi_read(struct drm_device *drm, u32 reg)
sys/dev/pci/drm/i915/display/vlv_sideband.h
108
return vlv_iosf_sb_read(drm, VLV_IOSF_SB_FLISDSI, reg);
sys/dev/pci/drm/i915/display/vlv_sideband.h
111
static inline void vlv_flisdsi_write(struct drm_device *drm, u32 reg, u32 val)
sys/dev/pci/drm/i915/display/vlv_sideband.h
113
vlv_iosf_sb_write(drm, VLV_IOSF_SB_FLISDSI, reg, val);
sys/dev/pci/drm/i915/display/vlv_sideband.h
21
static inline u32 vlv_bunit_read(struct drm_device *drm, u32 reg)
sys/dev/pci/drm/i915/display/vlv_sideband.h
23
return vlv_iosf_sb_read(drm, VLV_IOSF_SB_BUNIT, reg);
sys/dev/pci/drm/i915/display/vlv_sideband.h
26
static inline void vlv_bunit_write(struct drm_device *drm, u32 reg, u32 val)
sys/dev/pci/drm/i915/display/vlv_sideband.h
28
vlv_iosf_sb_write(drm, VLV_IOSF_SB_BUNIT, reg, val);
sys/dev/pci/drm/i915/display/vlv_sideband.h
41
static inline u32 vlv_cck_read(struct drm_device *drm, u32 reg)
sys/dev/pci/drm/i915/display/vlv_sideband.h
43
return vlv_iosf_sb_read(drm, VLV_IOSF_SB_CCK, reg);
sys/dev/pci/drm/i915/display/vlv_sideband.h
46
static inline void vlv_cck_write(struct drm_device *drm, u32 reg, u32 val)
sys/dev/pci/drm/i915/display/vlv_sideband.h
48
vlv_iosf_sb_write(drm, VLV_IOSF_SB_CCK, reg, val);
sys/dev/pci/drm/i915/display/vlv_sideband.h
61
static inline u32 vlv_ccu_read(struct drm_device *drm, u32 reg)
sys/dev/pci/drm/i915/display/vlv_sideband.h
63
return vlv_iosf_sb_read(drm, VLV_IOSF_SB_CCU, reg);
sys/dev/pci/drm/i915/display/vlv_sideband.h
66
static inline void vlv_ccu_write(struct drm_device *drm, u32 reg, u32 val)
sys/dev/pci/drm/i915/display/vlv_sideband.h
68
vlv_iosf_sb_write(drm, VLV_IOSF_SB_CCU, reg, val);
sys/dev/pci/drm/i915/display/vlv_sideband.h
82
u32 vlv_dpio_read(struct drm_device *drm, enum dpio_phy phy, int reg);
sys/dev/pci/drm/i915/display/vlv_sideband.h
84
enum dpio_phy phy, int reg, u32 val);
sys/dev/pci/drm/i915/display/vlv_sideband.h
86
static inline u32 vlv_dpio_read(struct drm_device *drm, int phy, int reg)
sys/dev/pci/drm/i915/display/vlv_sideband.h
91
int phy, int reg, u32 val)
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1652
const u32 reg = engine->mmio_base + 0x420;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1674
*cmd++ = reg;
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1677
*cmd++ = reg;
sys/dev/pci/drm/i915/gt/agp_intel_gtt.c
51
u_int32_t reg;
sys/dev/pci/drm/i915/gt/agp_intel_gtt.c
55
reg = pci_conf_read(bpa->pa_pc, bpa->pa_tag, I915_IFPADDR);
sys/dev/pci/drm/i915/gt/agp_intel_gtt.c
56
if (reg & 0x1) {
sys/dev/pci/drm/i915/gt/agp_intel_gtt.c
57
addr = (bus_addr_t)reg;
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
190
i915_reg_t reg = gen12_get_aux_inv_reg(engine);
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
196
return i915_mmio_reg_valid(reg) && !HAS_FLAT_CCS(engine->i915);
sys/dev/pci/drm/i915/gt/intel_engine.h
153
intel_read_status_page(const struct intel_engine_cs *engine, int reg)
sys/dev/pci/drm/i915/gt/intel_engine.h
156
return READ_ONCE(engine->status_page.addr[reg]);
sys/dev/pci/drm/i915/gt/intel_engine.h
160
intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
sys/dev/pci/drm/i915/gt/intel_engine.h
167
drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
sys/dev/pci/drm/i915/gt/intel_engine.h
168
WRITE_ONCE(engine->status_page.addr[reg], value);
sys/dev/pci/drm/i915/gt/intel_engine.h
169
drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1138
[RENDER_CLASS].reg = GEN8_RTCR,
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1139
[VIDEO_DECODE_CLASS].reg = GEN8_M1TCR, /* , GEN8_M2TCR */
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1140
[VIDEO_ENHANCEMENT_CLASS].reg = GEN8_VTCR,
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1141
[COPY_ENGINE_CLASS].reg = GEN8_BTCR,
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1144
[RENDER_CLASS].reg = GEN12_GFX_TLB_INV_CR,
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1145
[VIDEO_DECODE_CLASS].reg = GEN12_VD_TLB_INV_CR,
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1146
[VIDEO_ENHANCEMENT_CLASS].reg = GEN12_VE_TLB_INV_CR,
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1147
[COPY_ENGINE_CLASS].reg = GEN12_BLT_TLB_INV_CR,
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1148
[COMPUTE_CLASS].reg = GEN12_COMPCTX_TLB_INV_CR,
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1158
[VIDEO_DECODE_CLASS].reg = GEN12_VD_TLB_INV_CR,
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1159
[VIDEO_ENHANCEMENT_CLASS].reg = GEN12_VE_TLB_INV_CR,
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1160
[OTHER_CLASS].reg = XELPMP_GSC_TLB_INV_CR,
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1166
union intel_engine_tlb_inv_reg reg;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1211
(!regs[class].reg.reg &&
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1212
!regs[class].mcr_reg.reg)))
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1215
reg = regs[class];
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1225
reg.reg = GEN8_M2TCR;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1234
engine->tlb_inv.reg = reg;
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1728
if (!_reg[engine->id].reg)
sys/dev/pci/drm/i915/gt/intel_engine_types.h
354
i915_reg_t reg;
sys/dev/pci/drm/i915/gt/intel_engine_types.h
360
union intel_engine_tlb_inv_reg reg;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
140
i915_reg_t reg = FENCE_REG(fence->id);
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
142
intel_uncore_write_fw(uncore, reg, val);
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
143
intel_uncore_posting_read_fw(uncore, reg);
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
165
i915_reg_t reg = FENCE_REG(fence->id);
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
167
intel_uncore_write_fw(uncore, reg, val);
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
168
intel_uncore_posting_read_fw(uncore, reg);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
188
i915_reg_t r = { .reg = mcr.reg };
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
208
i915_mcr_reg_t reg, u8 rw_flag,
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
266
val = intel_uncore_read_fw(uncore, mcr_reg_cast(reg));
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
268
intel_uncore_write_fw(uncore, mcr_reg_cast(reg), value);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
285
i915_mcr_reg_t reg, u8 rw_flag,
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
294
fw_domains = intel_uncore_forcewake_for_reg(uncore, mcr_reg_cast(reg),
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
304
val = rw_with_mcr_steering_fw(gt, reg, rw_flag, group, instance, value);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
437
i915_mcr_reg_t reg,
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
440
return rw_with_mcr_steering(gt, reg, FW_REG_READ, group, instance, 0);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
456
void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value,
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
459
rw_with_mcr_steering(gt, reg, FW_REG_WRITE, group, instance, value);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
473
i915_mcr_reg_t reg, u32 value)
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
486
intel_uncore_write(gt->uncore, mcr_reg_cast(reg), value);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
504
void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
515
intel_uncore_write_fw(gt->uncore, mcr_reg_cast(reg), value);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
538
u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_mcr_reg_t reg,
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
541
u32 val = intel_gt_mcr_read_any(gt, reg);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
543
intel_gt_mcr_multicast_write(gt, reg, (val & ~clear) | set);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
563
i915_mcr_reg_t reg,
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
566
u32 offset = i915_mmio_reg_offset(reg);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
663
i915_mcr_reg_t reg,
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
669
if (reg_needs_read_steering(gt, reg, type)) {
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
694
u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg)
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
702
if (reg_needs_read_steering(gt, reg, type)) {
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
704
return rw_with_mcr_steering_fw(gt, reg,
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
710
return intel_uncore_read_fw(gt->uncore, mcr_reg_cast(reg));
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
725
u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg)
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
731
if (reg_needs_read_steering(gt, reg, type)) {
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
733
return rw_with_mcr_steering(gt, reg,
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
739
return intel_uncore_read(gt->uncore, mcr_reg_cast(reg));
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
845
i915_mcr_reg_t reg,
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
855
#define done ((intel_gt_mcr_read_any(gt, reg) & mask) == value)
sys/dev/pci/drm/i915/gt/intel_gt_mcr.h
17
i915_mcr_reg_t reg,
sys/dev/pci/drm/i915/gt/intel_gt_mcr.h
19
u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.h
20
u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.h
23
i915_mcr_reg_t reg, u32 value,
sys/dev/pci/drm/i915/gt/intel_gt_mcr.h
26
i915_mcr_reg_t reg, u32 value);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.h
28
i915_mcr_reg_t reg, u32 value);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.h
30
u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_mcr_reg_t reg,
sys/dev/pci/drm/i915/gt/intel_gt_mcr.h
34
i915_mcr_reg_t reg,
sys/dev/pci/drm/i915/gt/intel_gt_mcr.h
44
i915_mcr_reg_t reg,
sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c
18
i915_reg_t reg;
sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c
21
reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c
24
reg = GEN8_GT_IMR(2);
sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c
26
reg = GEN6_PMIMR;
sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c
29
intel_uncore_write(uncore, reg, mask);
sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c
65
i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c
69
intel_uncore_write(uncore, reg, reset_mask);
sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c
70
intel_uncore_write(uncore, reg, reset_mask);
sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c
71
intel_uncore_posting_read(uncore, reg);
sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c
79
i915_reg_t reg;
sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c
82
reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c
85
reg = GEN8_GT_IER(2);
sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c
87
reg = GEN6_PMIER;
sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c
90
intel_uncore_write(uncore, reg, mask);
sys/dev/pci/drm/i915/gt/intel_gtt.c
558
fw = intel_uncore_forcewake_for_reg(gt->uncore, _MMIO(XEHP_PAT_INDEX(0).reg),
sys/dev/pci/drm/i915/gt/intel_lrc.c
1717
i915_reg_t reg;
sys/dev/pci/drm/i915/gt/intel_lrc.c
1727
*batch++ = i915_mmio_reg_offset(lri->reg);
sys/dev/pci/drm/i915/gt/intel_rc6.c
739
static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)
sys/dev/pci/drm/i915/gt/intel_rc6.c
762
upper = intel_uncore_read_fw(uncore, reg);
sys/dev/pci/drm/i915/gt/intel_rc6.c
768
lower = intel_uncore_read_fw(uncore, reg);
sys/dev/pci/drm/i915/gt/intel_rc6.c
772
upper = intel_uncore_read_fw(uncore, reg);
sys/dev/pci/drm/i915/gt/intel_rc6.c
789
i915_reg_t reg = rc6->res_reg[id];
sys/dev/pci/drm/i915/gt/intel_rc6.c
797
fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
sys/dev/pci/drm/i915/gt/intel_rc6.c
807
time_hw = vlv_residency_raw(uncore, reg);
sys/dev/pci/drm/i915/gt/intel_rc6.c
819
time_hw = intel_uncore_read_fw(uncore, reg);
sys/dev/pci/drm/i915/gt/intel_rc6.c
856
i915_reg_t reg = gt->rc6.res_reg[id];
sys/dev/pci/drm/i915/gt/intel_rc6.c
861
intel_uncore_read(gt->uncore, reg),
sys/dev/pci/drm/i915/gt/intel_reset.c
563
const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
sys/dev/pci/drm/i915/gt/intel_reset.c
570
ack = intel_uncore_read_fw(uncore, reg);
sys/dev/pci/drm/i915/gt/intel_reset.c
589
intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
sys/dev/pci/drm/i915/gt/intel_reset.c
590
ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
sys/dev/pci/drm/i915/gt/intel_reset.c
596
intel_uncore_read_fw(uncore, reg));
sys/dev/pci/drm/i915/gt/intel_rps.c
75
static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/gt/intel_rps.c
77
intel_uncore_write_fw(uncore, reg, val);
sys/dev/pci/drm/i915/gt/intel_tlb.c
34
engine->tlb_inv.reg.mcr_reg,
sys/dev/pci/drm/i915/gt/intel_tlb.c
41
engine->tlb_inv.reg.reg,
sys/dev/pci/drm/i915/gt/intel_tlb.c
73
engine->tlb_inv.reg.mcr_reg,
sys/dev/pci/drm/i915/gt/intel_tlb.c
77
engine->tlb_inv.reg.reg,
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1033
intel_uncore_read_fw(uncore, wa->reg);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1038
*cs++ = i915_mmio_reg_offset(wa->reg);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
139
wa->reg,
sys/dev/pci/drm/i915/gt/intel_workarounds.c
148
unsigned int addr = i915_mmio_reg_offset(wa->reg);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1748
name, from, i915_mmio_reg_offset(wa->reg),
sys/dev/pci/drm/i915/gt/intel_workarounds.c
177
if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) {
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1782
intel_uncore_read_fw(uncore, wa->reg);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1788
intel_uncore_write_fw(uncore, wa->reg, val);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
179
} else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) {
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1794
intel_uncore_read_fw(uncore, wa->reg);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1830
intel_uncore_read_fw(uncore, wa->reg),
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1861
whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1864
.reg = reg
sys/dev/pci/drm/i915/gt/intel_workarounds.c
187
i915_mmio_reg_offset(wa_->reg),
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1873
wa.reg.reg |= flags;
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1878
whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1881
.mcr_reg = reg,
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1891
wa.mcr_reg.reg |= flags;
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1896
whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1898
whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1902
whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1904
whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
206
GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) ==
sys/dev/pci/drm/i915/gt/intel_workarounds.c
207
i915_mmio_reg_offset(wa_[1].reg));
sys/dev/pci/drm/i915/gt/intel_workarounds.c
208
if (i915_mmio_reg_offset(wa_[1].reg) >
sys/dev/pci/drm/i915/gt/intel_workarounds.c
209
i915_mmio_reg_offset(wa_[0].reg))
sys/dev/pci/drm/i915/gt/intel_workarounds.c
216
static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
sys/dev/pci/drm/i915/gt/intel_workarounds.c
2179
i915_mmio_reg_offset(wa->reg));
sys/dev/pci/drm/i915/gt/intel_workarounds.c
220
.reg = reg,
sys/dev/pci/drm/i915/gt/intel_workarounds.c
230
static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg,
sys/dev/pci/drm/i915/gt/intel_workarounds.c
234
.mcr_reg = reg,
sys/dev/pci/drm/i915/gt/intel_workarounds.c
246
wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
248
wa_add(wal, reg, clear, set, clear | set, false);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
252
wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
254
wa_mcr_add(wal, reg, clear, set, clear | set, false);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
258
wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
260
wa_write_clr_set(wal, reg, ~0, set);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
264
wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
266
wa_write_clr_set(wal, reg, set, set);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
270
wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
272
wa_mcr_write_clr_set(wal, reg, set, set);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
276
wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
278
wa_write_clr_set(wal, reg, clr, 0);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
282
wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
284
wa_mcr_write_clr_set(wal, reg, clr, 0);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
299
wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
3003
if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg)))
sys/dev/pci/drm/i915/gt/intel_workarounds.c
301
wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
3012
u32 offset = i915_mmio_reg_offset(wa->reg);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
305
wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
307
wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
3092
if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
sys/dev/pci/drm/i915/gt/intel_workarounds.c
311
wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
313
wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
317
wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
319
wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
323
wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
sys/dev/pci/drm/i915/gt/intel_workarounds.c
326
wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
sys/dev/pci/drm/i915/gt/intel_workarounds.c
330
wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg,
sys/dev/pci/drm/i915/gt/intel_workarounds.c
333
wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
sys/dev/pci/drm/i915/gt/intel_workarounds_types.h
17
i915_reg_t reg;
sys/dev/pci/drm/i915/gt/selftest_lrc.c
300
u32 reg;
sys/dev/pci/drm/i915/gt/selftest_lrc.c
384
int dw = find_offset(hw, t->reg);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
390
t->reg,
sys/dev/pci/drm/i915/gt/selftest_mocs.c
197
u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
sys/dev/pci/drm/i915/gt/selftest_mocs.c
205
if (!mcr_range(engine->i915, reg) && **vaddr != expect) {
sys/dev/pci/drm/i915/gt/selftest_mocs.c
211
reg += 4;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1003
return find_reg(i915, reg, wo, ARRAY_SIZE(wo));
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1007
u32 a, u32 b, i915_reg_t reg)
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1009
if (a == b && !writeonly_reg(engine->i915, reg)) {
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1011
i915_mmio_reg_offset(reg), a);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1024
i915_reg_t reg))
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1043
if (i915_mmio_reg_offset(wa->reg) &
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1047
if (!fn(engine, a[i], b[i], wa->reg))
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
180
i915_reg_t reg = i < engine->whitelist.count ?
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
181
engine->whitelist.list[i].reg :
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
184
return i915_mmio_reg_offset(reg);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
24
u32 reg;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
418
static bool wo_register(struct intel_engine_cs *engine, u32 reg)
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
423
if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
429
wo_registers[i].reg == reg)
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
436
static bool timestamp(const struct intel_engine_cs *engine, u32 reg)
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
438
reg = (reg - engine->mmio_base) & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
439
switch (reg) {
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
450
static bool ro_register(u32 reg)
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
452
if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
465
u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
467
if (ro_register(reg))
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
520
u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
529
if (wo_register(engine, reg))
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
532
if (timestamp(engine, reg))
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
535
ro_reg = ro_register(reg);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
561
reg &= RING_FORCE_TO_NONPRIV_ADDRESS_MASK;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
569
engine->name, reg);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
573
*cs++ = reg;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
581
*cs++ = reg;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
586
*cs++ = reg;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
594
*cs++ = reg;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
599
*cs++ = reg;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
608
*cs++ = reg;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
650
engine->name, reg);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
661
engine->name, reg);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
693
engine->name, err, reg);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
697
engine->name, reg, results[0]);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
700
engine->name, reg, results[0], rsvd);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
870
u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
873
reg &= RING_FORCE_TO_NONPRIV_ADDRESS_MASK;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
876
*cs++ = reg;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
906
u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
908
if (ro_register(reg))
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
912
reg &= RING_FORCE_TO_NONPRIV_ADDRESS_MASK;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
914
*cs++ = reg;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
952
i915_reg_t reg;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
957
i915_reg_t reg,
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
961
u32 offset = i915_mmio_reg_offset(reg);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
965
i915_mmio_reg_offset(tbl->reg) == offset)
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
973
static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
981
return find_reg(i915, reg, pardon, ARRAY_SIZE(pardon));
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
985
u32 a, u32 b, i915_reg_t reg)
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
987
if (a != b && !pardon_reg(engine->i915, reg)) {
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
989
i915_mmio_reg_offset(reg), a, b);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
996
static bool writeonly_reg(struct drm_i915_private *i915, i915_reg_t reg)
sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h
89
i915_reg_t reg;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
274
__mmio_reg_add(struct temp_regset *regset, struct guc_mmio_reg *reg)
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
308
*slot = *reg;
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
349
#define GUC_MMIO_REG_ADD(gt, regset, reg, masked) \
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
352
i915_mmio_reg_offset(reg), \
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
363
i915_mcr_reg_t reg, u32 flags)
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
375
intel_gt_mcr_get_nonterminated_steering(gt, reg, &group, &inst);
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
378
return guc_mmio_reg_add(gt, regset, i915_mmio_reg_offset(reg), flags);
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
381
#define GUC_MCR_REG_ADD(gt, regset, reg, masked) \
sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c
384
(reg), \
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1377
if (offset == match->list[j].reg.reg)
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1385
if (offset == matchext->extlist[j].reg.reg) {
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1515
if (regs[i].offset == reg_ipehr.reg)
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1517
else if (regs[i].offset == reg_instdone.reg)
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
250
i915_mcr_reg_t reg;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
266
ext->reg = _MMIO(i915_mmio_reg_offset(extlist->reg));
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
429
ptr[i].offset = match->list[i].reg.reg;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
440
ptr[i].offset = matchext->extlist[j].reg.reg;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
863
struct guc_mmio_reg *reg)
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
871
if (guc_capture_data_extracted(buf, fullsize, (void *)reg))
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
874
read += guc_capture_log_remove_dw(guc, buf, ®->offset);
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
875
read += guc_capture_log_remove_dw(guc, buf, ®->value);
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
876
read += guc_capture_log_remove_dw(guc, buf, ®->flags);
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
877
read += guc_capture_log_remove_dw(guc, buf, ®->mask);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1288
u32 reg;
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1291
reg = intel_uncore_read(gt->uncore, RPM_CONFIG0);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1293
return 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
sys/dev/pci/drm/i915/gt/uc/intel_huc.c
315
huc->status[INTEL_HUC_AUTH_BY_GUC].reg = GEN11_HUC_KERNEL_LOAD_INFO;
sys/dev/pci/drm/i915/gt/uc/intel_huc.c
319
huc->status[INTEL_HUC_AUTH_BY_GUC].reg = HUC_STATUS2;
sys/dev/pci/drm/i915/gt/uc/intel_huc.c
325
huc->status[INTEL_HUC_AUTH_BY_GSC].reg = GEN11_HUC_KERNEL_LOAD_INFO;
sys/dev/pci/drm/i915/gt/uc/intel_huc.c
329
huc->status[INTEL_HUC_AUTH_BY_GSC].reg = HECI_FWSTS(MTL_GSC_HECI1_BASE, 5);
sys/dev/pci/drm/i915/gt/uc/intel_huc.c
488
huc->status[type].reg,
sys/dev/pci/drm/i915/gt/uc/intel_huc.c
497
huc->status[type].reg.reg);
sys/dev/pci/drm/i915/gt/uc/intel_huc.c
505
delta_ms, huc->status[type].reg.reg, count, ret);
sys/dev/pci/drm/i915/gt/uc/intel_huc.c
514
huc->status[type].reg.reg, count, ret);
sys/dev/pci/drm/i915/gt/uc/intel_huc.c
598
status = intel_uncore_read(gt->uncore, huc->status[type].reg);
sys/dev/pci/drm/i915/gt/uc/intel_huc.c
706
intel_uncore_read(gt->uncore, huc->status[INTEL_HUC_AUTH_BY_GUC].reg));
sys/dev/pci/drm/i915/gt/uc/intel_huc.h
38
i915_reg_t reg;
sys/dev/pci/drm/i915/gvt/aperture_gm.c
136
struct i915_fence_reg *reg;
sys/dev/pci/drm/i915/gvt/aperture_gm.c
144
reg = vgpu->fence.regs[fence];
sys/dev/pci/drm/i915/gvt/aperture_gm.c
145
if (drm_WARN_ON(&i915->drm, !reg))
sys/dev/pci/drm/i915/gvt/aperture_gm.c
148
fence_reg_lo = FENCE_REG_GEN6_LO(reg->id);
sys/dev/pci/drm/i915/gvt/aperture_gm.c
149
fence_reg_hi = FENCE_REG_GEN6_HI(reg->id);
sys/dev/pci/drm/i915/gvt/aperture_gm.c
171
struct i915_fence_reg *reg;
sys/dev/pci/drm/i915/gvt/aperture_gm.c
183
reg = vgpu->fence.regs[i];
sys/dev/pci/drm/i915/gvt/aperture_gm.c
184
i915_unreserve_fence(reg);
sys/dev/pci/drm/i915/gvt/aperture_gm.c
196
struct i915_fence_reg *reg;
sys/dev/pci/drm/i915/gvt/aperture_gm.c
206
reg = i915_reserve_fence(gvt->gt->ggtt);
sys/dev/pci/drm/i915/gvt/aperture_gm.c
207
if (IS_ERR(reg))
sys/dev/pci/drm/i915/gvt/aperture_gm.c
210
vgpu->fence.regs[i] = reg;
sys/dev/pci/drm/i915/gvt/aperture_gm.c
223
reg = vgpu->fence.regs[i];
sys/dev/pci/drm/i915/gvt/aperture_gm.c
224
if (!reg)
sys/dev/pci/drm/i915/gvt/aperture_gm.c
226
i915_unreserve_fence(reg);
sys/dev/pci/drm/i915/gvt/edid.c
441
int reg;
sys/dev/pci/drm/i915/gvt/edid.c
445
reg = AUX_CH_CTL;
sys/dev/pci/drm/i915/gvt/edid.c
448
reg = AUX_CH_DATA1;
sys/dev/pci/drm/i915/gvt/edid.c
451
reg = AUX_CH_DATA2;
sys/dev/pci/drm/i915/gvt/edid.c
454
reg = AUX_CH_DATA3;
sys/dev/pci/drm/i915/gvt/edid.c
457
reg = AUX_CH_DATA4;
sys/dev/pci/drm/i915/gvt/edid.c
460
reg = AUX_CH_DATA5;
sys/dev/pci/drm/i915/gvt/edid.c
463
reg = -1;
sys/dev/pci/drm/i915/gvt/edid.c
466
return reg;
sys/dev/pci/drm/i915/gvt/edid.c
490
int reg = get_aux_ch_reg(offset);
sys/dev/pci/drm/i915/gvt/edid.c
492
if (reg != AUX_CH_CTL) {
sys/dev/pci/drm/i915/gvt/gvt.h
459
#define vgpu_vreg_t(vgpu, reg) \
sys/dev/pci/drm/i915/gvt/gvt.h
460
(*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
sys/dev/pci/drm/i915/gvt/gvt.h
463
#define vgpu_vreg64_t(vgpu, reg) \
sys/dev/pci/drm/i915/gvt/gvt.h
464
(*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
sys/dev/pci/drm/i915/gvt/handlers.c
1092
unsigned int reg)
sys/dev/pci/drm/i915/gvt/handlers.c
1097
if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A)))
sys/dev/pci/drm/i915/gvt/handlers.c
1099
else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_B)) ||
sys/dev/pci/drm/i915/gvt/handlers.c
1100
reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B)))
sys/dev/pci/drm/i915/gvt/handlers.c
1102
else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_C)) ||
sys/dev/pci/drm/i915/gvt/handlers.c
1103
reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C)))
sys/dev/pci/drm/i915/gvt/handlers.c
1105
else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_D)) ||
sys/dev/pci/drm/i915/gvt/handlers.c
1106
reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))
sys/dev/pci/drm/i915/gvt/handlers.c
1118
unsigned int reg, int len, bool data_valid)
sys/dev/pci/drm/i915/gvt/handlers.c
1133
vgpu_vreg(vgpu, reg) = value;
sys/dev/pci/drm/i915/gvt/handlers.c
1136
return trigger_aux_channel_interrupt(vgpu, reg);
sys/dev/pci/drm/i915/gvt/handlers.c
2159
#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
sys/dev/pci/drm/i915/gvt/handlers.c
2160
ret = setup_mmio_info(gvt, i915_mmio_reg_offset(reg), \
sys/dev/pci/drm/i915/gvt/handlers.c
2166
#define MMIO_DH(reg, d, r, w) \
sys/dev/pci/drm/i915/gvt/handlers.c
2167
MMIO_F(reg, 4, 0, 0, 0, d, r, w)
sys/dev/pci/drm/i915/gvt/handlers.c
2169
#define MMIO_DFH(reg, d, f, r, w) \
sys/dev/pci/drm/i915/gvt/handlers.c
2170
MMIO_F(reg, 4, f, 0, 0, d, r, w)
sys/dev/pci/drm/i915/gvt/handlers.c
2172
#define MMIO_GM(reg, d, r, w) \
sys/dev/pci/drm/i915/gvt/handlers.c
2173
MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
sys/dev/pci/drm/i915/gvt/handlers.c
2175
#define MMIO_GM_RDR(reg, d, r, w) \
sys/dev/pci/drm/i915/gvt/handlers.c
2176
MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
sys/dev/pci/drm/i915/gvt/handlers.c
2178
#define MMIO_RO(reg, d, f, rm, r, w) \
sys/dev/pci/drm/i915/gvt/handlers.c
2179
MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
sys/dev/pci/drm/i915/gvt/handlers.c
767
static inline bool in_whitelist(u32 reg)
sys/dev/pci/drm/i915/gvt/handlers.c
775
if (reg > array[mid].reg)
sys/dev/pci/drm/i915/gvt/handlers.c
777
else if (reg < array[mid].reg)
sys/dev/pci/drm/i915/gvt/interrupt.c
168
unsigned int reg)
sys/dev/pci/drm/i915/gvt/interrupt.c
174
if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg)
sys/dev/pci/drm/i915/gvt/interrupt.c
196
unsigned int reg, void *p_data, unsigned int bytes)
sys/dev/pci/drm/i915/gvt/interrupt.c
202
trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
sys/dev/pci/drm/i915/gvt/interrupt.c
203
(vgpu_vreg(vgpu, reg) ^ imr));
sys/dev/pci/drm/i915/gvt/interrupt.c
205
vgpu_vreg(vgpu, reg) = imr;
sys/dev/pci/drm/i915/gvt/interrupt.c
226
unsigned int reg, void *p_data, unsigned int bytes)
sys/dev/pci/drm/i915/gvt/interrupt.c
231
u32 virtual_ier = vgpu_vreg(vgpu, reg);
sys/dev/pci/drm/i915/gvt/interrupt.c
233
trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier,
sys/dev/pci/drm/i915/gvt/interrupt.c
243
vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;
sys/dev/pci/drm/i915/gvt/interrupt.c
244
vgpu_vreg(vgpu, reg) |= ier;
sys/dev/pci/drm/i915/gvt/interrupt.c
265
unsigned int reg, void *p_data, unsigned int bytes)
sys/dev/pci/drm/i915/gvt/interrupt.c
273
trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),
sys/dev/pci/drm/i915/gvt/interrupt.c
274
(vgpu_vreg(vgpu, reg) ^ ier));
sys/dev/pci/drm/i915/gvt/interrupt.c
276
vgpu_vreg(vgpu, reg) = ier;
sys/dev/pci/drm/i915/gvt/interrupt.c
278
info = regbase_to_irq_info(gvt, ier_to_regbase(reg));
sys/dev/pci/drm/i915/gvt/interrupt.c
303
int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
sys/dev/pci/drm/i915/gvt/interrupt.c
308
iir_to_regbase(reg));
sys/dev/pci/drm/i915/gvt/interrupt.c
311
trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
sys/dev/pci/drm/i915/gvt/interrupt.c
312
(vgpu_vreg(vgpu, reg) ^ iir));
sys/dev/pci/drm/i915/gvt/interrupt.c
317
vgpu_vreg(vgpu, reg) &= ~iir;
sys/dev/pci/drm/i915/gvt/interrupt.h
198
int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
sys/dev/pci/drm/i915/gvt/interrupt.h
201
unsigned int reg, void *p_data, unsigned int bytes);
sys/dev/pci/drm/i915/gvt/interrupt.h
203
unsigned int reg, void *p_data, unsigned int bytes);
sys/dev/pci/drm/i915/gvt/interrupt.h
205
unsigned int reg, void *p_data, unsigned int bytes);
sys/dev/pci/drm/i915/gvt/mmio.c
60
#define reg_is_mmio(gvt, reg) \
sys/dev/pci/drm/i915/gvt/mmio.c
61
(reg >= 0 && reg < gvt->device_info.mmio_size)
sys/dev/pci/drm/i915/gvt/mmio.c
63
#define reg_is_gtt(gvt, reg) \
sys/dev/pci/drm/i915/gvt/mmio.c
64
(reg >= gvt->device_info.gtt_start_offset \
sys/dev/pci/drm/i915/gvt/mmio.c
65
&& reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
sys/dev/pci/drm/i915/gvt/mmio.h
71
intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int reg);
sys/dev/pci/drm/i915/gvt/mmio_context.c
193
offset.reg = regs[ring_id];
sys/dev/pci/drm/i915/gvt/mmio_context.c
197
offset.reg += 4;
sys/dev/pci/drm/i915/gvt/mmio_context.c
201
offset.reg = 0xb020;
sys/dev/pci/drm/i915/gvt/mmio_context.c
205
offset.reg += 4;
sys/dev/pci/drm/i915/gvt/mmio_context.c
234
i915_mmio_reg_valid(mmio->reg); mmio++) {
sys/dev/pci/drm/i915/gvt/mmio_context.c
238
*cs++ = i915_mmio_reg_offset(mmio->reg);
sys/dev/pci/drm/i915/gvt/mmio_context.c
239
*cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16);
sys/dev/pci/drm/i915/gvt/mmio_context.c
371
i915_reg_t reg;
sys/dev/pci/drm/i915/gvt/mmio_context.c
382
reg = _MMIO(regs[engine->id]);
sys/dev/pci/drm/i915/gvt/mmio_context.c
389
fw = intel_uncore_forcewake_for_reg(uncore, reg,
sys/dev/pci/drm/i915/gvt/mmio_context.c
396
intel_uncore_write_fw(uncore, reg, 0x1);
sys/dev/pci/drm/i915/gvt/mmio_context.c
398
if (wait_for_atomic(intel_uncore_read_fw(uncore, reg) == 0, 50))
sys/dev/pci/drm/i915/gvt/mmio_context.c
402
vgpu_vreg_t(vgpu, reg) = 0;
sys/dev/pci/drm/i915/gvt/mmio_context.c
433
offset.reg = regs[engine->id];
sys/dev/pci/drm/i915/gvt/mmio_context.c
447
offset.reg += 4;
sys/dev/pci/drm/i915/gvt/mmio_context.c
451
l3_offset.reg = 0xb020;
sys/dev/pci/drm/i915/gvt/mmio_context.c
465
l3_offset.reg += 4;
sys/dev/pci/drm/i915/gvt/mmio_context.c
496
i915_mmio_reg_valid(mmio->reg); mmio++) {
sys/dev/pci/drm/i915/gvt/mmio_context.c
509
vgpu_vreg_t(pre, mmio->reg) =
sys/dev/pci/drm/i915/gvt/mmio_context.c
510
intel_uncore_read_fw(uncore, mmio->reg);
sys/dev/pci/drm/i915/gvt/mmio_context.c
512
vgpu_vreg_t(pre, mmio->reg) &=
sys/dev/pci/drm/i915/gvt/mmio_context.c
514
old_v = vgpu_vreg_t(pre, mmio->reg);
sys/dev/pci/drm/i915/gvt/mmio_context.c
517
intel_uncore_read_fw(uncore, mmio->reg);
sys/dev/pci/drm/i915/gvt/mmio_context.c
52
i915_reg_t reg;
sys/dev/pci/drm/i915/gvt/mmio_context.c
533
new_v = vgpu_vreg_t(next, mmio->reg) |
sys/dev/pci/drm/i915/gvt/mmio_context.c
536
new_v = vgpu_vreg_t(next, mmio->reg);
sys/dev/pci/drm/i915/gvt/mmio_context.c
546
intel_uncore_write_fw(uncore, mmio->reg, new_v);
sys/dev/pci/drm/i915/gvt/mmio_context.c
551
i915_mmio_reg_offset(mmio->reg),
sys/dev/pci/drm/i915/gvt/mmio_context.c
611
i915_mmio_reg_valid(mmio->reg); mmio++) {
sys/dev/pci/drm/i915/gvt/mmio_context.c
614
intel_gvt_mmio_set_sr_in_ctx(gvt, mmio->reg.reg);
sys/dev/pci/drm/i915/gvt/reg.h
77
typeof(_reg) (reg) = (_reg); \
sys/dev/pci/drm/i915/gvt/reg.h
78
(((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
sys/dev/pci/drm/i915/gvt/reg.h
79
(((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
sys/dev/pci/drm/i915/gvt/reg.h
80
(((reg) == 0x5008C || (reg) == 0x5009C) ? (PIPE_C) : \
sys/dev/pci/drm/i915/gvt/reg.h
84
typeof(_reg) (reg) = (_reg); \
sys/dev/pci/drm/i915/gvt/reg.h
85
(((reg) == 0x50080 || (reg) == 0x50088 || (reg) == 0x5008C) ? \
sys/dev/pci/drm/i915/gvt/reg.h
87
(((reg) == 0x50090 || (reg) == 0x50098 || (reg) == 0x5009C) ? \
sys/dev/pci/drm/i915/gvt/scheduler.c
271
i915_reg_t reg;
sys/dev/pci/drm/i915/gvt/scheduler.c
273
reg = RING_INSTDONE(engine->mmio_base);
sys/dev/pci/drm/i915/gvt/scheduler.c
274
vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
sys/dev/pci/drm/i915/gvt/scheduler.c
275
intel_uncore_read(uncore, reg);
sys/dev/pci/drm/i915/gvt/scheduler.c
277
reg = RING_ACTHD(engine->mmio_base);
sys/dev/pci/drm/i915/gvt/scheduler.c
278
vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
sys/dev/pci/drm/i915/gvt/scheduler.c
279
intel_uncore_read(uncore, reg);
sys/dev/pci/drm/i915/gvt/scheduler.c
281
reg = RING_ACTHD_UDW(engine->mmio_base);
sys/dev/pci/drm/i915/gvt/scheduler.c
282
vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
sys/dev/pci/drm/i915/gvt/scheduler.c
283
intel_uncore_read(uncore, reg);
sys/dev/pci/drm/i915/gvt/trace.h
276
TP_PROTO(int id, char *reg_name, unsigned int reg, unsigned int new_val,
sys/dev/pci/drm/i915/gvt/trace.h
279
TP_ARGS(id, reg_name, reg, new_val, old_val, changed),
sys/dev/pci/drm/i915/gvt/trace.h
284
__field(unsigned int, reg)
sys/dev/pci/drm/i915/gvt/trace.h
293
__entry->reg = reg;
sys/dev/pci/drm/i915/gvt/trace.h
300
__entry->id, __entry->buf, __entry->reg, __entry->new_val,
sys/dev/pci/drm/i915/gvt/trace.h
347
TP_PROTO(int old_id, int new_id, char *action, unsigned int reg,
sys/dev/pci/drm/i915/gvt/trace.h
350
TP_ARGS(old_id, new_id, action, reg, old_val, new_val),
sys/dev/pci/drm/i915/gvt/trace.h
356
__field(unsigned int, reg)
sys/dev/pci/drm/i915/gvt/trace.h
365
__entry->reg = reg;
sys/dev/pci/drm/i915/gvt/trace.h
372
__entry->buf, __entry->reg,
sys/dev/pci/drm/i915/i915_cmd_parser.c
1147
const struct drm_i915_reg_descriptor *reg = NULL;
sys/dev/pci/drm/i915/i915_cmd_parser.c
1150
for (; !reg && (count > 0); ++table, --count)
sys/dev/pci/drm/i915/i915_cmd_parser.c
1151
reg = __find_reg(table->regs, table->num_regs, addr);
sys/dev/pci/drm/i915/i915_cmd_parser.c
1153
return reg;
sys/dev/pci/drm/i915/i915_cmd_parser.c
1265
const u32 step = desc->reg.step ? desc->reg.step : length;
sys/dev/pci/drm/i915/i915_cmd_parser.c
1268
for (offset = desc->reg.offset; offset < length;
sys/dev/pci/drm/i915/i915_cmd_parser.c
1270
const u32 reg_addr = cmd[offset] & desc->reg.mask;
sys/dev/pci/drm/i915/i915_cmd_parser.c
1271
const struct drm_i915_reg_descriptor *reg =
sys/dev/pci/drm/i915/i915_cmd_parser.c
1274
if (!reg) {
sys/dev/pci/drm/i915/i915_cmd_parser.c
1284
if (reg->mask) {
sys/dev/pci/drm/i915/i915_cmd_parser.c
1299
(cmd[offset + 1] & reg->mask) != reg->value)) {
sys/dev/pci/drm/i915/i915_cmd_parser.c
157
} reg;
sys/dev/pci/drm/i915/i915_cmd_parser.c
229
.reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
sys/dev/pci/drm/i915/i915_cmd_parser.c
231
.reg = { .offset = 1, .mask = 0x007FFFFC },
sys/dev/pci/drm/i915/i915_cmd_parser.c
238
.reg = { .offset = 1, .mask = 0x007FFFFC },
sys/dev/pci/drm/i915/i915_cmd_parser.c
322
.reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),
sys/dev/pci/drm/i915/i915_cmd_parser.c
486
.reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
sys/dev/pci/drm/i915/i915_cmd_parser.c
489
.reg = { .offset = 1, .mask = 0x007FFFFC } ),
sys/dev/pci/drm/i915/i915_cmd_parser.c
492
.reg = { .offset = 1, .mask = 0x007FFFFC } ),
sys/dev/pci/drm/i915/i915_cmd_parser.c
494
.reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),
sys/dev/pci/drm/i915/i915_debugfs.c
482
i915_mmio_reg_offset(wa->reg),
sys/dev/pci/drm/i915/i915_gem.c
867
struct i915_fence_reg *reg = &to_gt(i915)->ggtt->fence_regs[i];
sys/dev/pci/drm/i915/i915_gem.c
881
if (!reg->vma)
sys/dev/pci/drm/i915/i915_gem.c
884
GEM_BUG_ON(i915_vma_has_userfault(reg->vma));
sys/dev/pci/drm/i915/i915_gem.c
885
reg->dirty = true;
sys/dev/pci/drm/i915/i915_hwmon.c
79
i915_reg_t reg, u32 clear, u32 set)
sys/dev/pci/drm/i915/i915_hwmon.c
88
intel_uncore_rmw(uncore, reg, clear, set);
sys/dev/pci/drm/i915/i915_ioctl.c
45
struct drm_i915_reg_read *reg = data;
sys/dev/pci/drm/i915/i915_ioctl.c
62
entry_offset == (reg->offset & -entry->size))
sys/dev/pci/drm/i915/i915_ioctl.c
71
flags = reg->offset & (entry->size - 1);
sys/dev/pci/drm/i915/i915_ioctl.c
75
reg->val = intel_uncore_read64_2x32(uncore,
sys/dev/pci/drm/i915/i915_ioctl.c
79
reg->val = intel_uncore_read64(uncore,
sys/dev/pci/drm/i915/i915_ioctl.c
82
reg->val = intel_uncore_read(uncore, entry->offset_ldw);
sys/dev/pci/drm/i915/i915_ioctl.c
84
reg->val = intel_uncore_read16(uncore,
sys/dev/pci/drm/i915/i915_ioctl.c
87
reg->val = intel_uncore_read8(uncore,
sys/dev/pci/drm/i915/i915_irq.c
100
u32 val = intel_uncore_read(uncore, reg);
sys/dev/pci/drm/i915/i915_irq.c
107
i915_mmio_reg_offset(reg), val);
sys/dev/pci/drm/i915/i915_irq.c
108
intel_uncore_write(uncore, reg, 0xffffffff);
sys/dev/pci/drm/i915/i915_irq.c
109
intel_uncore_posting_read(uncore, reg);
sys/dev/pci/drm/i915/i915_irq.c
110
intel_uncore_write(uncore, reg, 0xffffffff);
sys/dev/pci/drm/i915/i915_irq.c
111
intel_uncore_posting_read(uncore, reg);
sys/dev/pci/drm/i915/i915_irq.c
176
i915_reg_t reg;
sys/dev/pci/drm/i915/i915_irq.c
185
reg = GEN7_L3CDERRST1(slice);
sys/dev/pci/drm/i915/i915_irq.c
187
error_status = intel_uncore_read(&dev_priv->uncore, reg);
sys/dev/pci/drm/i915/i915_irq.c
192
intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
sys/dev/pci/drm/i915/i915_irq.c
193
intel_uncore_posting_read(&dev_priv->uncore, reg);
sys/dev/pci/drm/i915/i915_irq.c
98
void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
sys/dev/pci/drm/i915/i915_irq.h
43
void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg);
sys/dev/pci/drm/i915/i915_perf.c
1335
__store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)
sys/dev/pci/drm/i915/i915_perf.c
1348
*cs++ = i915_mmio_reg_offset(reg);
sys/dev/pci/drm/i915/i915_perf.c
1358
__read_reg(struct intel_context *ce, i915_reg_t reg, u32 ggtt_offset)
sys/dev/pci/drm/i915/i915_perf.c
1369
err = __store_reg_to_mem(rq, reg, ggtt_offset);
sys/dev/pci/drm/i915/i915_perf.c
1456
static bool oa_find_reg_in_lri(u32 *state, u32 reg, u32 *offset, u32 end)
sys/dev/pci/drm/i915/i915_perf.c
1464
if (state[idx] == reg) {
sys/dev/pci/drm/i915/i915_perf.c
1474
static u32 oa_context_image_offset(struct intel_context *ce, u32 reg)
sys/dev/pci/drm/i915/i915_perf.c
1491
if (oa_find_reg_in_lri(state, reg, &offset, len))
sys/dev/pci/drm/i915/i915_perf.c
1503
i915_reg_t reg = GEN12_OACTXCONTROL(ce->engine->mmio_base);
sys/dev/pci/drm/i915/i915_perf.c
1511
offset = oa_context_image_offset(ce, i915_mmio_reg_offset(reg));
sys/dev/pci/drm/i915/i915_perf.c
1934
bool save, i915_reg_t reg, u32 offset,
sys/dev/pci/drm/i915/i915_perf.c
1947
*cs++ = i915_mmio_reg_offset(reg) + 4 * d;
sys/dev/pci/drm/i915/i915_perf.c
2441
i915_reg_t reg)
sys/dev/pci/drm/i915/i915_perf.c
2443
u32 mmio = i915_mmio_reg_offset(reg);
sys/dev/pci/drm/i915/i915_perf.c
2498
i915_reg_t reg;
sys/dev/pci/drm/i915/i915_perf.c
2543
*cs++ = i915_mmio_reg_offset(flex->reg);
sys/dev/pci/drm/i915/i915_perf.c
2811
regs[i].value = oa_config_flex_reg(oa_config, regs[i].reg);
sys/dev/pci/drm/i915/i915_perf.c
3229
u32 reg, shift;
sys/dev/pci/drm/i915/i915_perf.c
3232
reg = intel_uncore_read(to_gt(i915)->uncore, RPM_CONFIG0);
sys/dev/pci/drm/i915/i915_perf.c
3235
reg);
sys/dev/pci/drm/i915/i915_perf.c
4526
static u32 mask_reg_value(u32 reg, u32 val)
sys/dev/pci/drm/i915/i915_perf.c
4533
if (REG_EQUAL(reg, HALF_SLICE_CHICKEN2))
sys/dev/pci/drm/i915/i915_perf.c
4541
if (REG_EQUAL(reg, WAIT_FOR_RC6_EXIT))
sys/dev/pci/drm/i915/i915_reg.h
1193
#define GEN7_PARITY_ERROR_ROW(reg) \
sys/dev/pci/drm/i915/i915_reg.h
1194
(((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
sys/dev/pci/drm/i915/i915_reg.h
1195
#define GEN7_PARITY_ERROR_BANK(reg) \
sys/dev/pci/drm/i915/i915_reg.h
1196
(((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
sys/dev/pci/drm/i915/i915_reg.h
1197
#define GEN7_PARITY_ERROR_SUBBANK(reg) \
sys/dev/pci/drm/i915/i915_reg.h
1198
(((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
sys/dev/pci/drm/i915/i915_reg_defs.h
178
u32 reg;
sys/dev/pci/drm/i915/i915_reg_defs.h
181
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
sys/dev/pci/drm/i915/i915_reg_defs.h
184
u32 reg;
sys/dev/pci/drm/i915/i915_reg_defs.h
187
#define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) })
sys/dev/pci/drm/i915/i915_reg_defs.h
197
_Generic((r), i915_reg_t: (r).reg, i915_mcr_reg_t: (r).reg)
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
41
#define MMIO_F(reg, s) do { \
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
43
ret = iter->handle_mmio_cb(iter, i915_mmio_reg_offset(reg), s); \
sys/dev/pci/drm/i915/intel_gvt_mmio_table.c
48
#define MMIO_D(reg) MMIO_F(reg, 4)
sys/dev/pci/drm/i915/intel_uncore.c
1217
gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
sys/dev/pci/drm/i915/intel_uncore.c
1797
const i915_reg_t reg,
sys/dev/pci/drm/i915/intel_uncore.c
1804
i915_mmio_reg_offset(reg)))
sys/dev/pci/drm/i915/intel_uncore.c
1811
const i915_reg_t reg,
sys/dev/pci/drm/i915/intel_uncore.c
1818
i915_mmio_reg_offset(reg));
sys/dev/pci/drm/i915/intel_uncore.c
1823
const i915_reg_t reg, const bool read)
sys/dev/pci/drm/i915/intel_uncore.c
1832
__unclaimed_previous_reg_debug(uncore, reg, read);
sys/dev/pci/drm/i915/intel_uncore.c
1839
const i915_reg_t reg, const bool read)
sys/dev/pci/drm/i915/intel_uncore.c
1844
__unclaimed_reg_debug(uncore, reg, read);
sys/dev/pci/drm/i915/intel_uncore.c
1850
vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
1851
u##x val = __raw_uncore_read##x(uncore, reg); \
sys/dev/pci/drm/i915/intel_uncore.c
1852
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
sys/dev/pci/drm/i915/intel_uncore.c
1865
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
sys/dev/pci/drm/i915/intel_uncore.c
1870
gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
1872
val = __raw_uncore_read##x(uncore, reg); \
sys/dev/pci/drm/i915/intel_uncore.c
1878
gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
1881
val = __raw_uncore_read##x(uncore, reg); \
sys/dev/pci/drm/i915/intel_uncore.c
1901
u32 offset = i915_mmio_reg_offset(reg); \
sys/dev/pci/drm/i915/intel_uncore.c
1907
unclaimed_reg_debug = unclaimed_reg_debug_header(uncore, reg, true)
sys/dev/pci/drm/i915/intel_uncore.c
1911
unclaimed_reg_debug_footer(uncore, reg, true); \
sys/dev/pci/drm/i915/intel_uncore.c
1913
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
sys/dev/pci/drm/i915/intel_uncore.c
1945
fwtable_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) \
sys/dev/pci/drm/i915/intel_uncore.c
1952
val = __raw_uncore_read##x(uncore, reg); \
sys/dev/pci/drm/i915/intel_uncore.c
1957
fwtable_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) {
sys/dev/pci/drm/i915/intel_uncore.c
1958
return __fwtable_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg));
sys/dev/pci/drm/i915/intel_uncore.c
1971
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
sys/dev/pci/drm/i915/intel_uncore.c
1978
gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
1980
__raw_uncore_write##x(uncore, reg, val); \
sys/dev/pci/drm/i915/intel_uncore.c
1986
gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
1989
__raw_uncore_write##x(uncore, reg, val); \
sys/dev/pci/drm/i915/intel_uncore.c
2007
u32 offset = i915_mmio_reg_offset(reg); \
sys/dev/pci/drm/i915/intel_uncore.c
2010
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
sys/dev/pci/drm/i915/intel_uncore.c
2013
unclaimed_reg_debug = unclaimed_reg_debug_header(uncore, reg, false)
sys/dev/pci/drm/i915/intel_uncore.c
2017
unclaimed_reg_debug_footer(uncore, reg, false); \
sys/dev/pci/drm/i915/intel_uncore.c
2022
gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
2026
__raw_uncore_write##x(uncore, reg, val); \
sys/dev/pci/drm/i915/intel_uncore.c
2035
fwtable_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
2041
__raw_uncore_write##x(uncore, reg, val); \
sys/dev/pci/drm/i915/intel_uncore.c
2046
fwtable_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
sys/dev/pci/drm/i915/intel_uncore.c
2048
return __fwtable_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg));
sys/dev/pci/drm/i915/intel_uncore.c
2061
vgpu_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
2062
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
sys/dev/pci/drm/i915/intel_uncore.c
2063
__raw_uncore_write##x(uncore, reg, val); \
sys/dev/pci/drm/i915/intel_uncore.c
2768
i915_reg_t reg,
sys/dev/pci/drm/i915/intel_uncore.c
2776
#define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
sys/dev/pci/drm/i915/intel_uncore.c
2817
i915_reg_t reg,
sys/dev/pci/drm/i915/intel_uncore.c
2825
intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
sys/dev/pci/drm/i915/intel_uncore.c
2835
reg, mask, value,
sys/dev/pci/drm/i915/intel_uncore.c
2843
reg),
sys/dev/pci/drm/i915/intel_uncore.c
2848
trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
sys/dev/pci/drm/i915/intel_uncore.c
2917
i915_reg_t reg, unsigned int op)
sys/dev/pci/drm/i915/intel_uncore.c
2927
fw_domains = uncore->funcs.read_fw_domains(uncore, reg);
sys/dev/pci/drm/i915/intel_uncore.c
2930
fw_domains |= uncore->funcs.write_fw_domains(uncore, reg);
sys/dev/pci/drm/i915/intel_uncore.c
950
#define NEEDS_FORCE_WAKE(reg) ({ \
sys/dev/pci/drm/i915/intel_uncore.c
951
u32 __reg = (reg); \
sys/dev/pci/drm/i915/intel_uncore.h
261
i915_reg_t reg, unsigned int op);
sys/dev/pci/drm/i915/intel_uncore.h
287
i915_reg_t reg,
sys/dev/pci/drm/i915/intel_uncore.h
295
i915_reg_t reg,
sys/dev/pci/drm/i915/intel_uncore.h
300
return __intel_wait_for_register(uncore, reg, mask, value, 2,
sys/dev/pci/drm/i915/intel_uncore.h
305
i915_reg_t reg,
sys/dev/pci/drm/i915/intel_uncore.h
313
i915_reg_t reg,
sys/dev/pci/drm/i915/intel_uncore.h
319
return __intel_wait_for_register_fw(uncore, reg, mask, value,
sys/dev/pci/drm/i915/intel_uncore.h
323
#define IS_GSI_REG(reg) ((reg) < 0x40000)
sys/dev/pci/drm/i915/intel_uncore.h
328
i915_reg_t reg) \
sys/dev/pci/drm/i915/intel_uncore.h
330
u32 offset = i915_mmio_reg_offset(reg); \
sys/dev/pci/drm/i915/intel_uncore.h
338
i915_reg_t reg, u##x__ val) \
sys/dev/pci/drm/i915/intel_uncore.h
340
u32 offset = i915_mmio_reg_offset(reg); \
sys/dev/pci/drm/i915/intel_uncore.h
360
i915_reg_t reg) \
sys/dev/pci/drm/i915/intel_uncore.h
362
return uncore->funcs.mmio_read##s__(uncore, reg, (trace__)); \
sys/dev/pci/drm/i915/intel_uncore.h
367
i915_reg_t reg, u##x__ val) \
sys/dev/pci/drm/i915/intel_uncore.h
369
uncore->funcs.mmio_write##s__(uncore, reg, val, (trace__)); \
sys/dev/pci/drm/i915/intel_uncore.h
437
i915_reg_t reg, u32 clear, u32 set)
sys/dev/pci/drm/i915/intel_uncore.h
441
old = intel_uncore_read(uncore, reg);
sys/dev/pci/drm/i915/intel_uncore.h
443
intel_uncore_write(uncore, reg, val);
sys/dev/pci/drm/i915/intel_uncore.h
448
i915_reg_t reg, u32 clear, u32 set)
sys/dev/pci/drm/i915/intel_uncore.h
452
old = intel_uncore_read_fw(uncore, reg);
sys/dev/pci/drm/i915/intel_uncore.h
455
intel_uncore_write_fw(uncore, reg, val);
sys/dev/pci/drm/i915/intel_uncore.h
489
i915_reg_t reg, u32 val,
sys/dev/pci/drm/i915/intel_uncore.h
494
intel_uncore_write(uncore, reg, val);
sys/dev/pci/drm/i915/intel_uncore.h
495
reg_val = intel_uncore_read(uncore, reg);
sys/dev/pci/drm/i915/intel_uncore.h
519
#define raw_reg_read(base, reg) \
sys/dev/pci/drm/i915/intel_uncore.h
520
readl(base + i915_mmio_reg_offset(reg))
sys/dev/pci/drm/i915/intel_uncore.h
521
#define raw_reg_write(base, reg, value) \
sys/dev/pci/drm/i915/intel_uncore.h
522
writel(value, base + i915_mmio_reg_offset(reg))
sys/dev/pci/drm/i915/selftests/intel_uncore.c
161
const struct reg *r;
sys/dev/pci/drm/i915/selftests/intel_uncore.c
212
u32 __iomem *reg = intel_uncore_regs(uncore) + engine->mmio_base + r->offset;
sys/dev/pci/drm/i915/selftests/intel_uncore.c
235
val = readl(reg);
sys/dev/pci/drm/i915/selftests/intel_uncore.c
262
if (wait_for(readl(reg) == 0, 100)) {
sys/dev/pci/drm/i915/selftests/intel_uncore.c
264
engine->name, r->name, readl(reg), fw_domains);
sys/dev/pci/drm/i915/selftests/intel_uncore.c
305
i915_reg_t reg = { offset };
sys/dev/pci/drm/i915/selftests/intel_uncore.c
307
intel_uncore_posting_read_fw(uncore, reg);
sys/dev/pci/drm/i915/selftests/intel_uncore.c
316
i915_reg_t reg = { offset };
sys/dev/pci/drm/i915/selftests/intel_uncore.c
324
intel_uncore_posting_read_fw(uncore, reg);
sys/dev/pci/drm/i915/selftests/mock_uncore.c
29
nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { }
sys/dev/pci/drm/i915/selftests/mock_uncore.c
36
nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return 0; }
sys/dev/pci/drm/i915/soc/intel_gmch.c
185
unsigned int reg = DISPLAY_VER(display) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
sys/dev/pci/drm/i915/soc/intel_gmch.c
188
if (pci_read_config_word(i915->gmch.pdev, reg, &gmch_ctrl)) {
sys/dev/pci/drm/i915/soc/intel_gmch.c
201
if (pci_write_config_word(i915->gmch.pdev, reg, gmch_ctrl)) {
sys/dev/pci/drm/i915/vlv_suspend.c
284
i915_reg_t reg = VLV_GTLC_PW_STATUS;
sys/dev/pci/drm/i915/vlv_suspend.c
296
intel_uncore_read_notrace(&i915->uncore, reg)) & mask)
sys/dev/pci/drm/i915/vlv_suspend.c
300
trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
sys/dev/pci/drm/include/linux/pci.h
143
pci_read_config_dword(struct pci_dev *pdev, int reg, u32 *val)
sys/dev/pci/drm/include/linux/pci.h
145
*val = pci_conf_read(pdev->pc, pdev->tag, reg);
sys/dev/pci/drm/include/linux/pci.h
150
pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val)
sys/dev/pci/drm/include/linux/pci.h
154
v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2));
sys/dev/pci/drm/include/linux/pci.h
155
*val = (v >> ((reg & 0x2) * 8));
sys/dev/pci/drm/include/linux/pci.h
160
pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val)
sys/dev/pci/drm/include/linux/pci.h
164
v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3));
sys/dev/pci/drm/include/linux/pci.h
165
*val = (v >> ((reg & 0x3) * 8));
sys/dev/pci/drm/include/linux/pci.h
170
pci_write_config_dword(struct pci_dev *pdev, int reg, u32 val)
sys/dev/pci/drm/include/linux/pci.h
172
pci_conf_write(pdev->pc, pdev->tag, reg, val);
sys/dev/pci/drm/include/linux/pci.h
177
pci_write_config_word(struct pci_dev *pdev, int reg, u16 val)
sys/dev/pci/drm/include/linux/pci.h
181
v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2));
sys/dev/pci/drm/include/linux/pci.h
182
v &= ~(0xffff << ((reg & 0x2) * 8));
sys/dev/pci/drm/include/linux/pci.h
183
v |= (val << ((reg & 0x2) * 8));
sys/dev/pci/drm/include/linux/pci.h
184
pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x2), v);
sys/dev/pci/drm/include/linux/pci.h
189
pci_write_config_byte(struct pci_dev *pdev, int reg, u8 val)
sys/dev/pci/drm/include/linux/pci.h
193
v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3));
sys/dev/pci/drm/include/linux/pci.h
194
v &= ~(0xff << ((reg & 0x3) * 8));
sys/dev/pci/drm/include/linux/pci.h
195
v |= (val << ((reg & 0x3) * 8));
sys/dev/pci/drm/include/linux/pci.h
196
pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x3), v);
sys/dev/pci/drm/include/linux/pci.h
202
int reg, u16 *val)
sys/dev/pci/drm/include/linux/pci.h
208
v = pci_conf_read(bus->pc, tag, (reg & ~0x2));
sys/dev/pci/drm/include/linux/pci.h
209
*val = (v >> ((reg & 0x2) * 8));
sys/dev/pci/drm/include/linux/pci.h
215
int reg, u8 *val)
sys/dev/pci/drm/include/linux/pci.h
221
v = pci_conf_read(bus->pc, tag, (reg & ~0x3));
sys/dev/pci/drm/include/linux/pci.h
222
*val = (v >> ((reg & 0x3) * 8));
sys/dev/pci/drm/include/linux/pci.h
228
int reg, u8 val)
sys/dev/pci/drm/include/linux/pci.h
234
v = pci_conf_read(bus->pc, tag, (reg & ~0x3));
sys/dev/pci/drm/include/linux/pci.h
235
v &= ~(0xff << ((reg & 0x3) * 8));
sys/dev/pci/drm/include/linux/pci.h
236
v |= (val << ((reg & 0x3) * 8));
sys/dev/pci/drm/include/linux/pci.h
237
pci_conf_write(bus->pc, tag, (reg & ~0x3), v);
sys/dev/pci/drm/include/uapi/drm/radeon_drm.h
276
unsigned char cmd_type, reg, n_bufs, flags;
sys/dev/pci/drm/radeon/atombios_encoders.c
1534
uint32_t temp, reg;
sys/dev/pci/drm/radeon/atombios_encoders.c
1539
reg = R600_BIOS_3_SCRATCH;
sys/dev/pci/drm/radeon/atombios_encoders.c
1541
reg = RADEON_BIOS_3_SCRATCH;
sys/dev/pci/drm/radeon/atombios_encoders.c
1544
temp = RREG32(reg);
sys/dev/pci/drm/radeon/atombios_encoders.c
1546
WREG32(reg, (ATOM_S3_TV1_ACTIVE |
sys/dev/pci/drm/radeon/atombios_encoders.c
1549
WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
sys/dev/pci/drm/radeon/atombios_encoders.c
1551
WREG32(reg, 0);
sys/dev/pci/drm/radeon/atombios_encoders.c
1559
WREG32(reg, temp);
sys/dev/pci/drm/radeon/atombios_encoders.c
1619
u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
sys/dev/pci/drm/radeon/atombios_encoders.c
1620
WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
sys/dev/pci/drm/radeon/atombios_encoders.c
1622
WREG32(RADEON_BIOS_3_SCRATCH, reg);
sys/dev/pci/drm/radeon/cik.c
154
u32 reg, u32 *val)
sys/dev/pci/drm/radeon/cik.c
156
switch (reg) {
sys/dev/pci/drm/radeon/cik.c
169
*val = RREG32(reg);
sys/dev/pci/drm/radeon/cik.c
179
u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
sys/dev/pci/drm/radeon/cik.c
185
WREG32(CIK_DIDT_IND_INDEX, (reg));
sys/dev/pci/drm/radeon/cik.c
191
void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
sys/dev/pci/drm/radeon/cik.c
196
WREG32(CIK_DIDT_IND_INDEX, (reg));
sys/dev/pci/drm/radeon/cik.c
237
u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg)
sys/dev/pci/drm/radeon/cik.c
243
WREG32(PCIE_INDEX, reg);
sys/dev/pci/drm/radeon/cik.c
250
void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
sys/dev/pci/drm/radeon/cik.c
255
WREG32(PCIE_INDEX, reg);
sys/dev/pci/drm/radeon/cik.c
3430
rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
sys/dev/pci/drm/radeon/cik.c
5541
uint32_t reg;
sys/dev/pci/drm/radeon/cik.c
5543
reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2);
sys/dev/pci/drm/radeon/cik.c
5545
reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2);
sys/dev/pci/drm/radeon/cik.c
5546
rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
sys/dev/pci/drm/radeon/cik_sdma.c
113
u32 reg;
sys/dev/pci/drm/radeon/cik_sdma.c
116
reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
sys/dev/pci/drm/radeon/cik_sdma.c
118
reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
sys/dev/pci/drm/radeon/cik_sdma.c
120
WREG32(reg, (ring->wptr << 2) & 0x3fffc);
sys/dev/pci/drm/radeon/cik_sdma.c
121
(void)RREG32(reg);
sys/dev/pci/drm/radeon/cik_sdma.c
65
u32 rptr, reg;
sys/dev/pci/drm/radeon/cik_sdma.c
71
reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET;
sys/dev/pci/drm/radeon/cik_sdma.c
73
reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET;
sys/dev/pci/drm/radeon/cik_sdma.c
75
rptr = RREG32(reg);
sys/dev/pci/drm/radeon/cik_sdma.c
92
u32 reg;
sys/dev/pci/drm/radeon/cik_sdma.c
95
reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
sys/dev/pci/drm/radeon/cik_sdma.c
97
reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
sys/dev/pci/drm/radeon/cik_sdma.c
99
return (RREG32(reg) & 0x3fffc) >> 2;
sys/dev/pci/drm/radeon/cikd.h
1682
#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
sys/dev/pci/drm/radeon/cikd.h
1683
(((reg) >> 2) & 0xFFFF) | \
sys/dev/pci/drm/radeon/dce6_afmt.c
35
u32 block_offset, u32 reg)
sys/dev/pci/drm/radeon/dce6_afmt.c
41
WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
sys/dev/pci/drm/radeon/dce6_afmt.c
49
u32 block_offset, u32 reg, u32 v)
sys/dev/pci/drm/radeon/dce6_afmt.c
55
WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
sys/dev/pci/drm/radeon/dce6_afmt.c
58
AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));
sys/dev/pci/drm/radeon/dce6_afmt.h
35
u32 dce6_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg);
sys/dev/pci/drm/radeon/dce6_afmt.h
36
void dce6_endpoint_wreg(struct radeon_device *rdev, u32 offset, u32 reg, u32 v);
sys/dev/pci/drm/radeon/evergreen.c
101
u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
sys/dev/pci/drm/radeon/evergreen.c
107
WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
sys/dev/pci/drm/radeon/evergreen.c
1094
u32 reg, u32 *val)
sys/dev/pci/drm/radeon/evergreen.c
1096
switch (reg) {
sys/dev/pci/drm/radeon/evergreen.c
1104
*val = RREG32(reg);
sys/dev/pci/drm/radeon/evergreen.c
113
void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
sys/dev/pci/drm/radeon/evergreen.c
118
WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
sys/dev/pci/drm/radeon/evergreen.c
57
u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
sys/dev/pci/drm/radeon/evergreen.c
63
WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
sys/dev/pci/drm/radeon/evergreen.c
69
void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
sys/dev/pci/drm/radeon/evergreen.c
74
WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
sys/dev/pci/drm/radeon/evergreen.c
79
u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
sys/dev/pci/drm/radeon/evergreen.c
85
WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
sys/dev/pci/drm/radeon/evergreen.c
91
void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
sys/dev/pci/drm/radeon/evergreen.c
96
WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
sys/dev/pci/drm/radeon/evergreen_cs.c
1051
unsigned idx, unsigned reg)
sys/dev/pci/drm/radeon/evergreen_cs.c
1055
switch (reg) {
sys/dev/pci/drm/radeon/evergreen_cs.c
1060
idx, reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1065
pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);
sys/dev/pci/drm/radeon/evergreen_cs.c
1074
unsigned reg, i;
sys/dev/pci/drm/radeon/evergreen_cs.c
1079
reg = pkt->reg;
sys/dev/pci/drm/radeon/evergreen_cs.c
1080
for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
sys/dev/pci/drm/radeon/evergreen_cs.c
1081
r = evergreen_packet0_check(p, pkt, idx, reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1095
static int evergreen_cs_handle_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
sys/dev/pci/drm/radeon/evergreen_cs.c
1103
switch (reg) {
sys/dev/pci/drm/radeon/evergreen_cs.c
1147
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1159
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1166
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1176
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1218
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1230
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1242
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1254
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1277
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1280
tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
sys/dev/pci/drm/radeon/evergreen_cs.c
1290
tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
sys/dev/pci/drm/radeon/evergreen_cs.c
1299
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1315
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1324
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1338
tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1346
tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
sys/dev/pci/drm/radeon/evergreen_cs.c
1358
tmp = (reg - CB_COLOR0_INFO) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1364
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1376
tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
sys/dev/pci/drm/radeon/evergreen_cs.c
1382
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1398
tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1406
tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
sys/dev/pci/drm/radeon/evergreen_cs.c
1418
tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1427
tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
sys/dev/pci/drm/radeon/evergreen_cs.c
1443
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1460
tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c);
sys/dev/pci/drm/radeon/evergreen_cs.c
1471
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1488
tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8;
sys/dev/pci/drm/radeon/evergreen_cs.c
1500
tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1503
dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1517
tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1520
dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1534
tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1545
tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1559
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1562
tmp = (reg - CB_COLOR0_BASE) / 0x3c;
sys/dev/pci/drm/radeon/evergreen_cs.c
1575
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1578
tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
sys/dev/pci/drm/radeon/evergreen_cs.c
1588
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1706
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1714
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1720
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1728
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1734
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
1743
dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
sys/dev/pci/drm/radeon/evergreen_cs.c
1757
static inline bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg)
sys/dev/pci/drm/radeon/evergreen_cs.c
1762
i = (reg >> 7);
sys/dev/pci/drm/radeon/evergreen_cs.c
1766
m = 1 << ((reg >> 2) & 31);
sys/dev/pci/drm/radeon/evergreen_cs.c
1781
unsigned start_reg, end_reg, reg;
sys/dev/pci/drm/radeon/evergreen_cs.c
2310
for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) {
sys/dev/pci/drm/radeon/evergreen_cs.c
2311
if (evergreen_is_safe_reg(p, reg))
sys/dev/pci/drm/radeon/evergreen_cs.c
2313
r = evergreen_cs_handle_reg(p, reg, idx);
sys/dev/pci/drm/radeon/evergreen_cs.c
2327
for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) {
sys/dev/pci/drm/radeon/evergreen_cs.c
2328
if (evergreen_is_safe_reg(p, reg))
sys/dev/pci/drm/radeon/evergreen_cs.c
2330
r = evergreen_cs_handle_reg(p, reg, idx);
sys/dev/pci/drm/radeon/evergreen_cs.c
2585
reg = radeon_get_ib_value(p, idx+1) << 2;
sys/dev/pci/drm/radeon/evergreen_cs.c
2586
if (!evergreen_is_safe_reg(p, reg)) {
sys/dev/pci/drm/radeon/evergreen_cs.c
2588
reg, idx + 1);
sys/dev/pci/drm/radeon/evergreen_cs.c
2612
reg = radeon_get_ib_value(p, idx+3) << 2;
sys/dev/pci/drm/radeon/evergreen_cs.c
2613
if (!evergreen_is_safe_reg(p, reg)) {
sys/dev/pci/drm/radeon/evergreen_cs.c
2615
reg, idx + 3);
sys/dev/pci/drm/radeon/evergreen_cs.c
2719
reg = radeon_get_ib_value(p, idx + 1) << 2;
sys/dev/pci/drm/radeon/evergreen_cs.c
2720
if (!evergreen_is_safe_reg(p, reg)) {
sys/dev/pci/drm/radeon/evergreen_cs.c
2722
reg, idx + 1);
sys/dev/pci/drm/radeon/evergreen_cs.c
2746
reg = radeon_get_ib_value(p, idx + 5) << 2;
sys/dev/pci/drm/radeon/evergreen_cs.c
2747
if (!evergreen_is_safe_reg(p, reg)) {
sys/dev/pci/drm/radeon/evergreen_cs.c
2749
reg, idx + 5);
sys/dev/pci/drm/radeon/evergreen_cs.c
3317
static bool evergreen_vm_reg_valid(u32 reg)
sys/dev/pci/drm/radeon/evergreen_cs.c
3320
if (reg >= 0x28000)
sys/dev/pci/drm/radeon/evergreen_cs.c
3324
switch (reg) {
sys/dev/pci/drm/radeon/evergreen_cs.c
3434
DRM_DEBUG("Invalid register 0x%x in CS\n", reg);
sys/dev/pci/drm/radeon/evergreen_cs.c
3444
u32 start_reg, end_reg, reg, i;
sys/dev/pci/drm/radeon/evergreen_cs.c
3500
reg = ib[idx + 1] * 4;
sys/dev/pci/drm/radeon/evergreen_cs.c
3501
if (!evergreen_vm_reg_valid(reg))
sys/dev/pci/drm/radeon/evergreen_cs.c
3505
reg = ib[idx + 5] * 4;
sys/dev/pci/drm/radeon/evergreen_cs.c
3506
if (!evergreen_vm_reg_valid(reg))
sys/dev/pci/drm/radeon/evergreen_cs.c
3512
reg = ib[idx + 3] * 4;
sys/dev/pci/drm/radeon/evergreen_cs.c
3513
if (!evergreen_vm_reg_valid(reg))
sys/dev/pci/drm/radeon/evergreen_cs.c
3527
reg = start_reg + (4 * i);
sys/dev/pci/drm/radeon/evergreen_cs.c
3528
if (!evergreen_vm_reg_valid(reg))
sys/dev/pci/drm/radeon/evergreen_cs.c
3552
reg = start_reg;
sys/dev/pci/drm/radeon/evergreen_cs.c
3553
if (!evergreen_vm_reg_valid(reg)) {
sys/dev/pci/drm/radeon/evergreen_cs.c
3559
reg = start_reg + (4 * i);
sys/dev/pci/drm/radeon/evergreen_cs.c
3560
if (!evergreen_vm_reg_valid(reg)) {
sys/dev/pci/drm/radeon/evergreen_cs.c
3573
reg = start_reg;
sys/dev/pci/drm/radeon/evergreen_cs.c
3574
if (!evergreen_vm_reg_valid(reg)) {
sys/dev/pci/drm/radeon/evergreen_cs.c
3580
reg = start_reg + (4 * i);
sys/dev/pci/drm/radeon/evergreen_cs.c
3581
if (!evergreen_vm_reg_valid(reg)) {
sys/dev/pci/drm/radeon/evergreend.h
1534
#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
sys/dev/pci/drm/radeon/evergreend.h
1535
(((reg) >> 2) & 0xFFFF) | \
sys/dev/pci/drm/radeon/ni.c
47
u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
sys/dev/pci/drm/radeon/ni.c
53
WREG32(TN_SMC_IND_INDEX_0, (reg));
sys/dev/pci/drm/radeon/ni.c
59
void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
sys/dev/pci/drm/radeon/ni.c
64
WREG32(TN_SMC_IND_INDEX_0, (reg));
sys/dev/pci/drm/radeon/ni.c
836
u32 reg, u32 *val)
sys/dev/pci/drm/radeon/ni.c
838
switch (reg) {
sys/dev/pci/drm/radeon/ni.c
847
*val = RREG32(reg);
sys/dev/pci/drm/radeon/ni_dma.c
103
u32 reg;
sys/dev/pci/drm/radeon/ni_dma.c
106
reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;
sys/dev/pci/drm/radeon/ni_dma.c
108
reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;
sys/dev/pci/drm/radeon/ni_dma.c
110
WREG32(reg, (ring->wptr << 2) & 0x3fffc);
sys/dev/pci/drm/radeon/ni_dma.c
55
u32 rptr, reg;
sys/dev/pci/drm/radeon/ni_dma.c
61
reg = DMA_RB_RPTR + DMA0_REGISTER_OFFSET;
sys/dev/pci/drm/radeon/ni_dma.c
63
reg = DMA_RB_RPTR + DMA1_REGISTER_OFFSET;
sys/dev/pci/drm/radeon/ni_dma.c
65
rptr = RREG32(reg);
sys/dev/pci/drm/radeon/ni_dma.c
82
u32 reg;
sys/dev/pci/drm/radeon/ni_dma.c
85
reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;
sys/dev/pci/drm/radeon/ni_dma.c
87
reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;
sys/dev/pci/drm/radeon/ni_dma.c
89
return (RREG32(reg) & 0x3fffc) >> 2;
sys/dev/pci/drm/radeon/ni_dpm.c
1687
u32 reg;
sys/dev/pci/drm/radeon/ni_dpm.c
1751
reg = CG_R(0xffff) | CG_L(0);
sys/dev/pci/drm/radeon/ni_dpm.c
1752
table->initialState.level.aT = cpu_to_be32(reg);
sys/dev/pci/drm/radeon/ni_dpm.c
1781
reg = MIN_POWER_MASK | MAX_POWER_MASK;
sys/dev/pci/drm/radeon/ni_dpm.c
1782
table->initialState.level.SQPowerThrottle = cpu_to_be32(reg);
sys/dev/pci/drm/radeon/ni_dpm.c
1784
reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
sys/dev/pci/drm/radeon/ni_dpm.c
1785
table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
sys/dev/pci/drm/radeon/ni_dpm.c
1806
u32 reg;
sys/dev/pci/drm/radeon/ni_dpm.c
1929
reg = MIN_POWER_MASK | MAX_POWER_MASK;
sys/dev/pci/drm/radeon/ni_dpm.c
1930
table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg);
sys/dev/pci/drm/radeon/ni_dpm.c
1932
reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
sys/dev/pci/drm/radeon/ni_dpm.c
1933
table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3145
u32 reg;
sys/dev/pci/drm/radeon/ni_dpm.c
3154
reg = RREG32(CG_CAC_CTRL) & ~(TID_CNT_MASK | TID_UNIT_MASK);
sys/dev/pci/drm/radeon/ni_dpm.c
3155
reg |= (TID_CNT(ni_pi->cac_weights->tid_cnt) |
sys/dev/pci/drm/radeon/ni_dpm.c
3157
WREG32(CG_CAC_CTRL, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3211
u32 reg;
sys/dev/pci/drm/radeon/ni_dpm.c
3220
reg = RREG32_CG(CG_CAC_REGION_1_WEIGHT_0) & ~(WEIGHT_TCP_SIG0_MASK |
sys/dev/pci/drm/radeon/ni_dpm.c
3223
reg |= (WEIGHT_TCP_SIG0(ni_pi->cac_weights->weight_tcp_sig0) |
sys/dev/pci/drm/radeon/ni_dpm.c
3226
WREG32_CG(CG_CAC_REGION_1_WEIGHT_0, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3228
reg = RREG32_CG(CG_CAC_REGION_1_WEIGHT_1) & ~(WEIGHT_TCC_EN0_MASK |
sys/dev/pci/drm/radeon/ni_dpm.c
3231
reg |= (WEIGHT_TCC_EN0(ni_pi->cac_weights->weight_tcc_en0) |
sys/dev/pci/drm/radeon/ni_dpm.c
3234
WREG32_CG(CG_CAC_REGION_1_WEIGHT_1, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3236
reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_0) & ~(WEIGHT_CB_EN0_MASK |
sys/dev/pci/drm/radeon/ni_dpm.c
3240
reg |= (WEIGHT_CB_EN0(ni_pi->cac_weights->weight_cb_en0) |
sys/dev/pci/drm/radeon/ni_dpm.c
3244
WREG32_CG(CG_CAC_REGION_2_WEIGHT_0, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3246
reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_1) & ~(WEIGHT_DB_SIG0_MASK |
sys/dev/pci/drm/radeon/ni_dpm.c
3250
reg |= (WEIGHT_DB_SIG0(ni_pi->cac_weights->weight_db_sig0) |
sys/dev/pci/drm/radeon/ni_dpm.c
3254
WREG32_CG(CG_CAC_REGION_2_WEIGHT_1, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3256
reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_2) & ~(WEIGHT_SXM_SIG0_MASK |
sys/dev/pci/drm/radeon/ni_dpm.c
3261
reg |= (WEIGHT_SXM_SIG0(ni_pi->cac_weights->weight_sxm_sig0) |
sys/dev/pci/drm/radeon/ni_dpm.c
3266
WREG32_CG(CG_CAC_REGION_2_WEIGHT_2, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3268
reg = RREG32_CG(CG_CAC_REGION_3_WEIGHT_0) & ~(WEIGHT_XBR_0_MASK |
sys/dev/pci/drm/radeon/ni_dpm.c
3272
reg |= (WEIGHT_XBR_0(ni_pi->cac_weights->weight_xbr_0) |
sys/dev/pci/drm/radeon/ni_dpm.c
3276
WREG32_CG(CG_CAC_REGION_3_WEIGHT_0, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3278
reg = RREG32_CG(CG_CAC_REGION_3_WEIGHT_1) & ~(WEIGHT_SPI_SIG1_MASK |
sys/dev/pci/drm/radeon/ni_dpm.c
3283
reg |= (WEIGHT_SPI_SIG1(ni_pi->cac_weights->weight_spi_sig1) |
sys/dev/pci/drm/radeon/ni_dpm.c
3288
WREG32_CG(CG_CAC_REGION_3_WEIGHT_1, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3290
reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_0) & ~(WEIGHT_LDS_SIG0_MASK |
sys/dev/pci/drm/radeon/ni_dpm.c
3293
reg |= (WEIGHT_LDS_SIG0(ni_pi->cac_weights->weight_lds_sig0) |
sys/dev/pci/drm/radeon/ni_dpm.c
3296
WREG32_CG(CG_CAC_REGION_4_WEIGHT_0, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3298
reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_1) & ~(WEIGHT_BIF_MASK |
sys/dev/pci/drm/radeon/ni_dpm.c
3303
reg |= (WEIGHT_BIF(ni_pi->cac_weights->weight_bif) |
sys/dev/pci/drm/radeon/ni_dpm.c
3308
WREG32_CG(CG_CAC_REGION_4_WEIGHT_1, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3310
reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_2) & ~(WEIGHT_VGT_SIG1_MASK |
sys/dev/pci/drm/radeon/ni_dpm.c
3315
reg |= (WEIGHT_VGT_SIG1(ni_pi->cac_weights->weight_vgt_sig1) |
sys/dev/pci/drm/radeon/ni_dpm.c
3320
WREG32_CG(CG_CAC_REGION_4_WEIGHT_2, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3322
reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_3) & ~(WEIGHT_DC_SIG3_MASK |
sys/dev/pci/drm/radeon/ni_dpm.c
3327
reg |= (WEIGHT_DC_SIG3(ni_pi->cac_weights->weight_dc_sig3) |
sys/dev/pci/drm/radeon/ni_dpm.c
3332
WREG32_CG(CG_CAC_REGION_4_WEIGHT_3, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3334
reg = RREG32_CG(CG_CAC_REGION_5_WEIGHT_0) & ~(WEIGHT_SQ_VSP_MASK |
sys/dev/pci/drm/radeon/ni_dpm.c
3336
reg |= (WEIGHT_SQ_VSP(ni_pi->cac_weights->weight_sq_vsp) |
sys/dev/pci/drm/radeon/ni_dpm.c
3338
WREG32_CG(CG_CAC_REGION_5_WEIGHT_0, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3340
reg = RREG32_CG(CG_CAC_REGION_5_WEIGHT_1) & ~(WEIGHT_SQ_GPR_MASK);
sys/dev/pci/drm/radeon/ni_dpm.c
3341
reg |= WEIGHT_SQ_GPR(ni_pi->cac_weights->weight_sq_gpr);
sys/dev/pci/drm/radeon/ni_dpm.c
3342
WREG32_CG(CG_CAC_REGION_5_WEIGHT_1, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3344
reg = RREG32_CG(CG_CAC_REGION_4_OVERRIDE_4) & ~(OVR_MODE_SPARE_0_MASK |
sys/dev/pci/drm/radeon/ni_dpm.c
3348
reg |= (OVR_MODE_SPARE_0(ni_pi->cac_weights->ovr_mode_spare_0) |
sys/dev/pci/drm/radeon/ni_dpm.c
3352
WREG32_CG(CG_CAC_REGION_4_OVERRIDE_4, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3354
reg = RREG32(SQ_CAC_THRESHOLD) & ~(VSP_MASK |
sys/dev/pci/drm/radeon/ni_dpm.c
3357
reg |= (VSP(ni_pi->cac_weights->vsp) |
sys/dev/pci/drm/radeon/ni_dpm.c
3360
WREG32(SQ_CAC_THRESHOLD, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3362
reg = (MCDW_WR_ENABLE |
sys/dev/pci/drm/radeon/ni_dpm.c
3367
WREG32(MC_CG_CONFIG, reg);
sys/dev/pci/drm/radeon/ni_dpm.c
3369
reg = (READ_WEIGHT(ni_pi->cac_weights->mc_read_weight) |
sys/dev/pci/drm/radeon/ni_dpm.c
3372
WREG32(MC_CG_DATAPORT, reg);
sys/dev/pci/drm/radeon/nid.h
1148
#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
sys/dev/pci/drm/radeon/nid.h
1149
(((reg) >> 2) & 0xFFFF) | \
sys/dev/pci/drm/radeon/r100.c
1291
unsigned reg)
sys/dev/pci/drm/radeon/r100.c
1302
idx, reg);
sys/dev/pci/drm/radeon/r100.c
1315
if (reg == RADEON_SRC_PITCH_OFFSET) {
sys/dev/pci/drm/radeon/r100.c
1399
unsigned reg;
sys/dev/pci/drm/radeon/r100.c
1405
reg = pkt->reg;
sys/dev/pci/drm/radeon/r100.c
1411
if ((reg >> 7) > n) {
sys/dev/pci/drm/radeon/r100.c
1415
if (((reg + (pkt->count << 2)) >> 7) > n) {
sys/dev/pci/drm/radeon/r100.c
1420
j = (reg >> 7);
sys/dev/pci/drm/radeon/r100.c
1421
m = 1 << ((reg >> 2) & 31);
sys/dev/pci/drm/radeon/r100.c
1423
r = check(p, pkt, idx, reg);
sys/dev/pci/drm/radeon/r100.c
1433
reg += 4;
sys/dev/pci/drm/radeon/r100.c
1460
uint32_t header, h_idx, reg;
sys/dev/pci/drm/radeon/r100.c
1471
if (waitreloc.reg != RADEON_WAIT_UNTIL ||
sys/dev/pci/drm/radeon/r100.c
1493
reg = R100_CP_PACKET0_GET_REG(header);
sys/dev/pci/drm/radeon/r100.c
1507
switch (reg) {
sys/dev/pci/drm/radeon/r100.c
1582
unsigned idx, unsigned reg)
sys/dev/pci/drm/radeon/r100.c
1598
switch (reg) {
sys/dev/pci/drm/radeon/r100.c
1603
idx, reg);
sys/dev/pci/drm/radeon/r100.c
1612
r = r100_reloc_pitch_offset(p, pkt, idx, reg);
sys/dev/pci/drm/radeon/r100.c
1620
idx, reg);
sys/dev/pci/drm/radeon/r100.c
1633
idx, reg);
sys/dev/pci/drm/radeon/r100.c
1645
i = (reg - RADEON_PP_TXOFFSET_0) / 24;
sys/dev/pci/drm/radeon/r100.c
1649
idx, reg);
sys/dev/pci/drm/radeon/r100.c
1672
i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
sys/dev/pci/drm/radeon/r100.c
1676
idx, reg);
sys/dev/pci/drm/radeon/r100.c
1690
i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
sys/dev/pci/drm/radeon/r100.c
1694
idx, reg);
sys/dev/pci/drm/radeon/r100.c
1708
i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
sys/dev/pci/drm/radeon/r100.c
1712
idx, reg);
sys/dev/pci/drm/radeon/r100.c
1730
idx, reg);
sys/dev/pci/drm/radeon/r100.c
1801
idx, reg);
sys/dev/pci/drm/radeon/r100.c
1824
i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
sys/dev/pci/drm/radeon/r100.c
1832
i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
sys/dev/pci/drm/radeon/r100.c
1839
i = (reg - RADEON_PP_TXFILTER_0) / 24;
sys/dev/pci/drm/radeon/r100.c
1853
i = (reg - RADEON_PP_TXFORMAT_0) / 24;
sys/dev/pci/drm/radeon/r100.c
1907
i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
sys/dev/pci/drm/radeon/r100.c
1915
pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);
sys/dev/pci/drm/radeon/r100.c
2909
uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
sys/dev/pci/drm/radeon/r100.c
2915
WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
sys/dev/pci/drm/radeon/r100.c
2923
void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
sys/dev/pci/drm/radeon/r100.c
2928
WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
sys/dev/pci/drm/radeon/r100.c
2955
uint32_t reg, value;
sys/dev/pci/drm/radeon/r100.c
2963
reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
sys/dev/pci/drm/radeon/r100.c
2966
seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
sys/dev/pci/drm/radeon/r100.c
3112
int r100_set_surface_reg(struct radeon_device *rdev, int reg,
sys/dev/pci/drm/radeon/r100.c
3116
int surf_index = reg * 16;
sys/dev/pci/drm/radeon/r100.c
3153
DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
sys/dev/pci/drm/radeon/r100.c
3160
void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
sys/dev/pci/drm/radeon/r100.c
3162
int surf_index = reg * 16;
sys/dev/pci/drm/radeon/r100.c
371
tmp = RREG32(voltage->gpio.reg);
sys/dev/pci/drm/radeon/r100.c
376
WREG32(voltage->gpio.reg, tmp);
sys/dev/pci/drm/radeon/r100.c
380
tmp = RREG32(voltage->gpio.reg);
sys/dev/pci/drm/radeon/r100.c
385
WREG32(voltage->gpio.reg, tmp);
sys/dev/pci/drm/radeon/r100.c
4122
uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
sys/dev/pci/drm/radeon/r100.c
4128
writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
sys/dev/pci/drm/radeon/r100.c
4134
void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
sys/dev/pci/drm/radeon/r100.c
4139
writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
sys/dev/pci/drm/radeon/r100.c
4144
u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
sys/dev/pci/drm/radeon/r100.c
4148
if (reg < rdev->rio_mem_size) {
sys/dev/pci/drm/radeon/r100.c
4149
val = bus_space_read_4(rdev->iot, rdev->rio_mem, reg);
sys/dev/pci/drm/radeon/r100.c
4156
RADEON_MM_INDEX, reg);
sys/dev/pci/drm/radeon/r100.c
4166
void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
sys/dev/pci/drm/radeon/r100.c
4168
if (reg < rdev->rio_mem_size) {
sys/dev/pci/drm/radeon/r100.c
4171
bus_space_write_4(rdev->iot, rdev->rio_mem, reg, v);
sys/dev/pci/drm/radeon/r100.c
4176
RADEON_MM_INDEX, reg);
sys/dev/pci/drm/radeon/r100_track.h
92
unsigned idx, unsigned reg);
sys/dev/pci/drm/radeon/r100_track.h
97
unsigned reg);
sys/dev/pci/drm/radeon/r100d.h
59
#define PACKET0(reg, n) (CP_PACKET0 | \
sys/dev/pci/drm/radeon/r100d.h
60
REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
sys/dev/pci/drm/radeon/r200.c
147
unsigned idx, unsigned reg)
sys/dev/pci/drm/radeon/r200.c
162
switch (reg) {
sys/dev/pci/drm/radeon/r200.c
167
idx, reg);
sys/dev/pci/drm/radeon/r200.c
176
r = r100_reloc_pitch_offset(p, pkt, idx, reg);
sys/dev/pci/drm/radeon/r200.c
184
idx, reg);
sys/dev/pci/drm/radeon/r200.c
197
idx, reg);
sys/dev/pci/drm/radeon/r200.c
212
i = (reg - R200_PP_TXOFFSET_0) / 24;
sys/dev/pci/drm/radeon/r200.c
216
idx, reg);
sys/dev/pci/drm/radeon/r200.c
264
i = (reg - R200_PP_TXOFFSET_0) / 24;
sys/dev/pci/drm/radeon/r200.c
265
face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
sys/dev/pci/drm/radeon/r200.c
269
idx, reg);
sys/dev/pci/drm/radeon/r200.c
287
idx, reg);
sys/dev/pci/drm/radeon/r200.c
364
idx, reg);
sys/dev/pci/drm/radeon/r200.c
397
i = (reg - R200_PP_TXSIZE_0) / 32;
sys/dev/pci/drm/radeon/r200.c
408
i = (reg - R200_PP_TXPITCH_0) / 32;
sys/dev/pci/drm/radeon/r200.c
418
i = (reg - R200_PP_TXFILTER_0) / 32;
sys/dev/pci/drm/radeon/r200.c
435
i = (reg - R200_PP_TXMULTI_CTL_0) / 32;
sys/dev/pci/drm/radeon/r200.c
443
i = (reg - R200_PP_TXFORMAT_X_0) / 32;
sys/dev/pci/drm/radeon/r200.c
474
i = (reg - R200_PP_TXFORMAT_0) / 32;
sys/dev/pci/drm/radeon/r200.c
532
i = (reg - R200_PP_CUBIC_FACES_0) / 32;
sys/dev/pci/drm/radeon/r200.c
540
pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);
sys/dev/pci/drm/radeon/r300.c
1000
i = (reg - 0x4400) >> 2;
sys/dev/pci/drm/radeon/r300.c
1028
i = (reg - 0x4500) >> 2;
sys/dev/pci/drm/radeon/r300.c
1066
i = (reg - 0x4480) >> 2;
sys/dev/pci/drm/radeon/r300.c
1083
idx, reg);
sys/dev/pci/drm/radeon/r300.c
1125
idx, reg);
sys/dev/pci/drm/radeon/r300.c
1169
reg, idx, idx_value);
sys/dev/pci/drm/radeon/r300.c
60
uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
sys/dev/pci/drm/radeon/r300.c
629
unsigned idx, unsigned reg)
sys/dev/pci/drm/radeon/r300.c
643
switch (reg) {
sys/dev/pci/drm/radeon/r300.c
649
idx, reg);
sys/dev/pci/drm/radeon/r300.c
656
r = r100_reloc_pitch_offset(p, pkt, idx, reg);
sys/dev/pci/drm/radeon/r300.c
66
WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
sys/dev/pci/drm/radeon/r300.c
664
i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
sys/dev/pci/drm/radeon/r300.c
668
idx, reg);
sys/dev/pci/drm/radeon/r300.c
681
idx, reg);
sys/dev/pci/drm/radeon/r300.c
706
i = (reg - R300_TX_OFFSET_0) >> 2;
sys/dev/pci/drm/radeon/r300.c
710
idx, reg);
sys/dev/pci/drm/radeon/r300.c
72
void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
sys/dev/pci/drm/radeon/r300.c
77
WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
sys/dev/pci/drm/radeon/r300.c
783
idx, reg);
sys/dev/pci/drm/radeon/r300.c
799
i = (reg - 0x4E38) >> 2;
sys/dev/pci/drm/radeon/r300.c
868
idx, reg);
sys/dev/pci/drm/radeon/r300.c
914
i = (reg - 0x44C0) >> 2;
sys/dev/pci/drm/radeon/r300d.h
60
#define PACKET0(reg, n) (CP_PACKET0 | \
sys/dev/pci/drm/radeon/r300d.h
61
REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
sys/dev/pci/drm/radeon/r420.c
165
u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
sys/dev/pci/drm/radeon/r420.c
171
WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
sys/dev/pci/drm/radeon/r420.c
177
void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
sys/dev/pci/drm/radeon/r420.c
182
WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
sys/dev/pci/drm/radeon/r600.c
120
u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
sys/dev/pci/drm/radeon/r600.c
126
WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
sys/dev/pci/drm/radeon/r600.c
1277
uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
sys/dev/pci/drm/radeon/r600.c
1283
WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
sys/dev/pci/drm/radeon/r600.c
1290
void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
sys/dev/pci/drm/radeon/r600.c
1295
WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
sys/dev/pci/drm/radeon/r600.c
132
void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
sys/dev/pci/drm/radeon/r600.c
137
WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
sys/dev/pci/drm/radeon/r600.c
142
u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
sys/dev/pci/drm/radeon/r600.c
148
WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
sys/dev/pci/drm/radeon/r600.c
154
void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
sys/dev/pci/drm/radeon/r600.c
159
WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
sys/dev/pci/drm/radeon/r600.c
175
u32 reg, u32 *val)
sys/dev/pci/drm/radeon/r600.c
177
switch (reg) {
sys/dev/pci/drm/radeon/r600.c
183
*val = RREG32(reg);
sys/dev/pci/drm/radeon/r600.c
2395
u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
sys/dev/pci/drm/radeon/r600.c
2401
WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
sys/dev/pci/drm/radeon/r600.c
2408
void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
sys/dev/pci/drm/radeon/r600.c
2413
WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
sys/dev/pci/drm/radeon/r600.c
2819
rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
sys/dev/pci/drm/radeon/r600.c
3028
int r600_set_surface_reg(struct radeon_device *rdev, int reg,
sys/dev/pci/drm/radeon/r600.c
3036
void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
sys/dev/pci/drm/radeon/r600_cs.c
1022
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/r600_cs.c
1040
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/r600_cs.c
1082
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/r600_cs.c
1085
tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
sys/dev/pci/drm/radeon/r600_cs.c
1096
tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
sys/dev/pci/drm/radeon/r600_cs.c
1105
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/r600_cs.c
1140
dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
sys/dev/pci/drm/radeon/r600_cs.c
1143
tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
sys/dev/pci/drm/radeon/r600_cs.c
1153
tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
sys/dev/pci/drm/radeon/r600_cs.c
1166
tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
sys/dev/pci/drm/radeon/r600_cs.c
1178
tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
sys/dev/pci/drm/radeon/r600_cs.c
1200
tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
sys/dev/pci/drm/radeon/r600_cs.c
1203
dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
sys/dev/pci/drm/radeon/r600_cs.c
1212
dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
sys/dev/pci/drm/radeon/r600_cs.c
1231
tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
sys/dev/pci/drm/radeon/r600_cs.c
1234
dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
sys/dev/pci/drm/radeon/r600_cs.c
1243
dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
sys/dev/pci/drm/radeon/r600_cs.c
1262
tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
sys/dev/pci/drm/radeon/r600_cs.c
1279
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/r600_cs.c
1282
tmp = (reg - CB_COLOR0_BASE) / 4;
sys/dev/pci/drm/radeon/r600_cs.c
1294
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/r600_cs.c
1307
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/r600_cs.c
1377
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/r600_cs.c
1386
"0x%04X\n", reg);
sys/dev/pci/drm/radeon/r600_cs.c
1395
dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
sys/dev/pci/drm/radeon/r600_cs.c
1615
static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
sys/dev/pci/drm/radeon/r600_cs.c
1619
i = (reg >> 7);
sys/dev/pci/drm/radeon/r600_cs.c
1621
dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
sys/dev/pci/drm/radeon/r600_cs.c
1624
m = 1 << ((reg >> 2) & 31);
sys/dev/pci/drm/radeon/r600_cs.c
1627
dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
sys/dev/pci/drm/radeon/r600_cs.c
1639
unsigned start_reg, end_reg, reg;
sys/dev/pci/drm/radeon/r600_cs.c
1923
reg = start_reg + (4 * i);
sys/dev/pci/drm/radeon/r600_cs.c
1924
r = r600_cs_check_reg(p, reg, idx+1+i);
sys/dev/pci/drm/radeon/r600_cs.c
1939
reg = start_reg + (4 * i);
sys/dev/pci/drm/radeon/r600_cs.c
1940
r = r600_cs_check_reg(p, reg, idx+1+i);
sys/dev/pci/drm/radeon/r600_cs.c
2239
reg = radeon_get_ib_value(p, idx+1) << 2;
sys/dev/pci/drm/radeon/r600_cs.c
2240
if (!r600_is_safe_reg(p, reg, idx+1))
sys/dev/pci/drm/radeon/r600_cs.c
2263
reg = radeon_get_ib_value(p, idx+3) << 2;
sys/dev/pci/drm/radeon/r600_cs.c
2264
if (!r600_is_safe_reg(p, reg, idx+3))
sys/dev/pci/drm/radeon/r600_cs.c
836
uint32_t header, h_idx, reg, wait_reg_mem_info;
sys/dev/pci/drm/radeon/r600_cs.c
890
reg = R600_CP_PACKET0_GET_REG(header);
sys/dev/pci/drm/radeon/r600_cs.c
909
} else if (reg == vline_start_end[0]) {
sys/dev/pci/drm/radeon/r600_cs.c
923
unsigned idx, unsigned reg)
sys/dev/pci/drm/radeon/r600_cs.c
927
switch (reg) {
sys/dev/pci/drm/radeon/r600_cs.c
932
idx, reg);
sys/dev/pci/drm/radeon/r600_cs.c
937
pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);
sys/dev/pci/drm/radeon/r600_cs.c
946
unsigned reg, i;
sys/dev/pci/drm/radeon/r600_cs.c
951
reg = pkt->reg;
sys/dev/pci/drm/radeon/r600_cs.c
952
for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
sys/dev/pci/drm/radeon/r600_cs.c
953
r = r600_packet0_check(p, pkt, idx, reg);
sys/dev/pci/drm/radeon/r600_cs.c
971
static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
sys/dev/pci/drm/radeon/r600_cs.c
978
i = (reg >> 7);
sys/dev/pci/drm/radeon/r600_cs.c
980
dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
sys/dev/pci/drm/radeon/r600_cs.c
983
m = 1 << ((reg >> 2) & 31);
sys/dev/pci/drm/radeon/r600_cs.c
987
switch (reg) {
sys/dev/pci/drm/radeon/r600d.h
1584
#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
sys/dev/pci/drm/radeon/r600d.h
1585
(((reg) >> 2) & 0xFFFF) | \
sys/dev/pci/drm/radeon/radeon.h
1073
unsigned reg;
sys/dev/pci/drm/radeon/radeon.h
1081
unsigned idx, unsigned reg);
sys/dev/pci/drm/radeon/radeon.h
1864
int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
sys/dev/pci/drm/radeon/radeon.h
1939
int (*set_reg)(struct radeon_device *rdev, int reg,
sys/dev/pci/drm/radeon/radeon.h
1942
void (*clear_reg)(struct radeon_device *rdev, int reg);
sys/dev/pci/drm/radeon/radeon.h
2497
uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
sys/dev/pci/drm/radeon/radeon.h
2498
void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
sys/dev/pci/drm/radeon/radeon.h
2499
static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
sys/dev/pci/drm/radeon/radeon.h
2503
if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
sys/dev/pci/drm/radeon/radeon.h
2504
return readl(((void __iomem *)rdev->rmmio) + reg);
sys/dev/pci/drm/radeon/radeon.h
2506
return r100_mm_rreg_slow(rdev, reg);
sys/dev/pci/drm/radeon/radeon.h
2508
static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
sys/dev/pci/drm/radeon/radeon.h
2511
if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
sys/dev/pci/drm/radeon/radeon.h
2512
writel(v, ((void __iomem *)rdev->rmmio) + reg);
sys/dev/pci/drm/radeon/radeon.h
2514
r100_mm_wreg_slow(rdev, reg, v);
sys/dev/pci/drm/radeon/radeon.h
2517
u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
sys/dev/pci/drm/radeon/radeon.h
2518
void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
sys/dev/pci/drm/radeon/radeon.h
2546
#define RREG8(reg) readb((rdev->rmmio) + (reg))
sys/dev/pci/drm/radeon/radeon.h
2547
#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
sys/dev/pci/drm/radeon/radeon.h
2548
#define RREG16(reg) readw((rdev->rmmio) + (reg))
sys/dev/pci/drm/radeon/radeon.h
2549
#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
sys/dev/pci/drm/radeon/radeon.h
2550
#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
sys/dev/pci/drm/radeon/radeon.h
2551
#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
sys/dev/pci/drm/radeon/radeon.h
2552
#define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \
sys/dev/pci/drm/radeon/radeon.h
2553
r100_mm_rreg(rdev, (reg), false))
sys/dev/pci/drm/radeon/radeon.h
2554
#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
sys/dev/pci/drm/radeon/radeon.h
2555
#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
sys/dev/pci/drm/radeon/radeon.h
2558
#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
sys/dev/pci/drm/radeon/radeon.h
2559
#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
sys/dev/pci/drm/radeon/radeon.h
2560
#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
sys/dev/pci/drm/radeon/radeon.h
2561
#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
sys/dev/pci/drm/radeon/radeon.h
2562
#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
sys/dev/pci/drm/radeon/radeon.h
2563
#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
sys/dev/pci/drm/radeon/radeon.h
2564
#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
sys/dev/pci/drm/radeon/radeon.h
2565
#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
sys/dev/pci/drm/radeon/radeon.h
2566
#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
sys/dev/pci/drm/radeon/radeon.h
2567
#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
sys/dev/pci/drm/radeon/radeon.h
2568
#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
sys/dev/pci/drm/radeon/radeon.h
2569
#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
sys/dev/pci/drm/radeon/radeon.h
2570
#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
sys/dev/pci/drm/radeon/radeon.h
2571
#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
sys/dev/pci/drm/radeon/radeon.h
2572
#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
sys/dev/pci/drm/radeon/radeon.h
2573
#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
sys/dev/pci/drm/radeon/radeon.h
2574
#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
sys/dev/pci/drm/radeon/radeon.h
2575
#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
sys/dev/pci/drm/radeon/radeon.h
2576
#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
sys/dev/pci/drm/radeon/radeon.h
2577
#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
sys/dev/pci/drm/radeon/radeon.h
2578
#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
sys/dev/pci/drm/radeon/radeon.h
2579
#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
sys/dev/pci/drm/radeon/radeon.h
2580
#define WREG32_P(reg, val, mask) \
sys/dev/pci/drm/radeon/radeon.h
2582
uint32_t tmp_ = RREG32(reg); \
sys/dev/pci/drm/radeon/radeon.h
2585
WREG32(reg, tmp_); \
sys/dev/pci/drm/radeon/radeon.h
2587
#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
sys/dev/pci/drm/radeon/radeon.h
2588
#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
sys/dev/pci/drm/radeon/radeon.h
2589
#define WREG32_PLL_P(reg, val, mask) \
sys/dev/pci/drm/radeon/radeon.h
2591
uint32_t tmp_ = RREG32_PLL(reg); \
sys/dev/pci/drm/radeon/radeon.h
2594
WREG32_PLL(reg, tmp_); \
sys/dev/pci/drm/radeon/radeon.h
2596
#define WREG32_SMC_P(reg, val, mask) \
sys/dev/pci/drm/radeon/radeon.h
2598
uint32_t tmp_ = RREG32_SMC(reg); \
sys/dev/pci/drm/radeon/radeon.h
2601
WREG32_SMC(reg, tmp_); \
sys/dev/pci/drm/radeon/radeon.h
2603
#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
sys/dev/pci/drm/radeon/radeon.h
2604
#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
sys/dev/pci/drm/radeon/radeon.h
2605
#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
sys/dev/pci/drm/radeon/radeon.h
2618
uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
sys/dev/pci/drm/radeon/radeon.h
2619
void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
sys/dev/pci/drm/radeon/radeon.h
2620
u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
sys/dev/pci/drm/radeon/radeon.h
2621
void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
sys/dev/pci/drm/radeon/radeon.h
2622
u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
sys/dev/pci/drm/radeon/radeon.h
2623
void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
sys/dev/pci/drm/radeon/radeon.h
2624
u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
sys/dev/pci/drm/radeon/radeon.h
2625
void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
sys/dev/pci/drm/radeon/radeon.h
2626
u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
sys/dev/pci/drm/radeon/radeon.h
2627
void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
sys/dev/pci/drm/radeon/radeon.h
2628
u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
sys/dev/pci/drm/radeon/radeon.h
2629
void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
sys/dev/pci/drm/radeon/radeon.h
2630
u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
sys/dev/pci/drm/radeon/radeon.h
2631
void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
sys/dev/pci/drm/radeon/radeon.h
2632
u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
sys/dev/pci/drm/radeon/radeon.h
2633
void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
sys/dev/pci/drm/radeon/radeon.h
3001
u32 reg, u32 mask,
sys/dev/pci/drm/radeon/radeon.h
677
uint32_t reg[32];
sys/dev/pci/drm/radeon/radeon.h
680
int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
sys/dev/pci/drm/radeon/radeon.h
681
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
sys/dev/pci/drm/radeon/radeon_asic.c
140
u32 reg, u32 *val)
sys/dev/pci/drm/radeon/radeon_asic.c
53
static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
sys/dev/pci/drm/radeon/radeon_asic.c
55
DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
sys/dev/pci/drm/radeon/radeon_asic.c
70
static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
sys/dev/pci/drm/radeon/radeon_asic.c
73
reg, v);
sys/dev/pci/drm/radeon/radeon_asic.h
200
extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
sys/dev/pci/drm/radeon/radeon_asic.h
201
extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
sys/dev/pci/drm/radeon/radeon_asic.h
216
uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
sys/dev/pci/drm/radeon/radeon_asic.h
217
void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
sys/dev/pci/drm/radeon/radeon_asic.h
241
uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
sys/dev/pci/drm/radeon/radeon_asic.h
242
void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
sys/dev/pci/drm/radeon/radeon_asic.h
266
uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
sys/dev/pci/drm/radeon/radeon_asic.h
267
void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
sys/dev/pci/drm/radeon/radeon_asic.h
285
uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
sys/dev/pci/drm/radeon/radeon_asic.h
286
void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
sys/dev/pci/drm/radeon/radeon_asic.h
318
uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
sys/dev/pci/drm/radeon/radeon_asic.h
319
void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
sys/dev/pci/drm/radeon/radeon_asic.h
338
int r600_set_surface_reg(struct radeon_device *rdev, int reg,
sys/dev/pci/drm/radeon/radeon_asic.h
341
void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
sys/dev/pci/drm/radeon/radeon_asic.h
365
extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
sys/dev/pci/drm/radeon/radeon_asic.h
366
extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
sys/dev/pci/drm/radeon/radeon_asic.h
388
u32 reg, u32 *val);
sys/dev/pci/drm/radeon/radeon_asic.h
551
u32 reg, u32 *val);
sys/dev/pci/drm/radeon/radeon_asic.h
655
u32 reg, u32 *val);
sys/dev/pci/drm/radeon/radeon_asic.h
752
u32 reg, u32 *val);
sys/dev/pci/drm/radeon/radeon_asic.h
784
uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
sys/dev/pci/drm/radeon/radeon_asic.h
785
void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
sys/dev/pci/drm/radeon/radeon_asic.h
83
void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
sys/dev/pci/drm/radeon/radeon_asic.h
84
uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
sys/dev/pci/drm/radeon/radeon_asic.h
871
u32 reg, u32 *val);
sys/dev/pci/drm/radeon/radeon_asic.h
90
int r100_set_surface_reg(struct radeon_device *rdev, int reg,
sys/dev/pci/drm/radeon/radeon_asic.h
93
void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
sys/dev/pci/drm/radeon/radeon_atombios.c
222
gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
sys/dev/pci/drm/radeon/radeon_atombios.c
240
u32 reg;
sys/dev/pci/drm/radeon/radeon_atombios.c
245
reg = SI_DC_GPIO_HPD_A;
sys/dev/pci/drm/radeon/radeon_atombios.c
247
reg = EVERGREEN_DC_GPIO_HPD_A;
sys/dev/pci/drm/radeon/radeon_atombios.c
249
reg = AVIVO_DC_GPIO_HPD_A;
sys/dev/pci/drm/radeon/radeon_atombios.c
252
if (gpio->reg == reg) {
sys/dev/pci/drm/radeon/radeon_audio.c
288
u32 radeon_audio_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg)
sys/dev/pci/drm/radeon/radeon_audio.c
291
return rdev->audio.funcs->endpoint_rreg(rdev, offset, reg);
sys/dev/pci/drm/radeon/radeon_audio.c
297
u32 reg, u32 v)
sys/dev/pci/drm/radeon/radeon_audio.c
300
rdev->audio.funcs->endpoint_wreg(rdev, offset, reg, v);
sys/dev/pci/drm/radeon/radeon_audio.c
57
static u32 radeon_audio_rreg(struct radeon_device *rdev, u32 offset, u32 reg)
sys/dev/pci/drm/radeon/radeon_audio.c
59
return RREG32(reg);
sys/dev/pci/drm/radeon/radeon_audio.c
63
u32 reg, u32 v)
sys/dev/pci/drm/radeon/radeon_audio.c
65
WREG32(reg, v);
sys/dev/pci/drm/radeon/radeon_audio.h
32
#define RREG32_ENDPOINT(block, reg) \
sys/dev/pci/drm/radeon/radeon_audio.h
33
radeon_audio_endpoint_rreg(rdev, (block), (reg))
sys/dev/pci/drm/radeon/radeon_audio.h
34
#define WREG32_ENDPOINT(block, reg, v) \
sys/dev/pci/drm/radeon/radeon_audio.h
35
radeon_audio_endpoint_wreg(rdev, (block), (reg), (v))
sys/dev/pci/drm/radeon/radeon_audio.h
38
u32 (*endpoint_rreg)(struct radeon_device *rdev, u32 offset, u32 reg);
sys/dev/pci/drm/radeon/radeon_audio.h
40
u32 offset, u32 reg, u32 v);
sys/dev/pci/drm/radeon/radeon_audio.h
74
u32 offset, u32 reg);
sys/dev/pci/drm/radeon/radeon_audio.h
76
u32 offset, u32 reg, u32 v);
sys/dev/pci/drm/radeon/radeon_combios.c
2756
rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
sys/dev/pci/drm/radeon/radeon_combios.c
2764
rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
sys/dev/pci/drm/radeon/radeon_combios.c
2889
uint32_t reg, val, and_mask, or_mask;
sys/dev/pci/drm/radeon/radeon_combios.c
2908
reg = (id & 0x1fff) * 4;
sys/dev/pci/drm/radeon/radeon_combios.c
2911
WREG32(reg, val);
sys/dev/pci/drm/radeon/radeon_combios.c
2914
reg = (id & 0x1fff) * 4;
sys/dev/pci/drm/radeon/radeon_combios.c
2919
val = RREG32(reg);
sys/dev/pci/drm/radeon/radeon_combios.c
2921
WREG32(reg, val);
sys/dev/pci/drm/radeon/radeon_combios.c
2937
reg = RBIOS8(index);
sys/dev/pci/drm/radeon/radeon_combios.c
2943
reg, val);
sys/dev/pci/drm/radeon/radeon_combios.c
2963
reg = (id & 0x1fff) * 4;
sys/dev/pci/drm/radeon/radeon_combios.c
2965
WREG32(reg, val);
sys/dev/pci/drm/radeon/radeon_combios.c
2968
reg = (id & 0x1fff) * 4;
sys/dev/pci/drm/radeon/radeon_combios.c
2973
val = RREG32(reg);
sys/dev/pci/drm/radeon/radeon_combios.c
2975
WREG32(reg, val);
sys/dev/pci/drm/radeon/radeon_combios.c
2983
reg = id & 0x1fff;
sys/dev/pci/drm/radeon/radeon_combios.c
2988
val = RREG32_PLL(reg);
sys/dev/pci/drm/radeon/radeon_combios.c
2990
WREG32_PLL(reg, val);
sys/dev/pci/drm/radeon/radeon_combios.c
2993
reg = id & 0x1fff;
sys/dev/pci/drm/radeon/radeon_combios.c
2998
reg, val);
sys/dev/pci/drm/radeon/radeon_cs.c
768
pkt->reg = R100_CP_PACKET0_GET_REG(header);
sys/dev/pci/drm/radeon/radeon_cs.c
772
pkt->reg = R600_CP_PACKET0_GET_REG(header);
sys/dev/pci/drm/radeon/radeon_cursor.c
75
u32 reg;
sys/dev/pci/drm/radeon/radeon_cursor.c
78
reg = RADEON_CRTC_GEN_CNTL;
sys/dev/pci/drm/radeon/radeon_cursor.c
81
reg = RADEON_CRTC2_GEN_CNTL;
sys/dev/pci/drm/radeon/radeon_cursor.c
86
WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN);
sys/dev/pci/drm/radeon/radeon_device.c
206
u32 tmp, reg, and_mask, or_mask;
sys/dev/pci/drm/radeon/radeon_device.c
213
reg = registers[i + 0];
sys/dev/pci/drm/radeon/radeon_device.c
220
tmp = RREG32(reg);
sys/dev/pci/drm/radeon/radeon_device.c
224
WREG32(reg, tmp);
sys/dev/pci/drm/radeon/radeon_device.c
280
rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
sys/dev/pci/drm/radeon/radeon_device.c
293
int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
sys/dev/pci/drm/radeon/radeon_device.c
300
*reg = rdev->scratch.reg[i];
sys/dev/pci/drm/radeon/radeon_device.c
315
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
sys/dev/pci/drm/radeon/radeon_device.c
320
if (rdev->scratch.reg[i] == reg) {
sys/dev/pci/drm/radeon/radeon_device.c
669
uint32_t reg;
sys/dev/pci/drm/radeon/radeon_device.c
689
reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
sys/dev/pci/drm/radeon/radeon_device.c
692
reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
sys/dev/pci/drm/radeon/radeon_device.c
696
reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
sys/dev/pci/drm/radeon/radeon_device.c
699
if (reg & EVERGREEN_CRTC_MASTER_EN)
sys/dev/pci/drm/radeon/radeon_device.c
702
reg = RREG32(AVIVO_D1CRTC_CONTROL) |
sys/dev/pci/drm/radeon/radeon_device.c
704
if (reg & AVIVO_CRTC_EN) {
sys/dev/pci/drm/radeon/radeon_device.c
708
reg = RREG32(RADEON_CRTC_GEN_CNTL) |
sys/dev/pci/drm/radeon/radeon_device.c
710
if (reg & RADEON_CRTC_EN) {
sys/dev/pci/drm/radeon/radeon_device.c
718
reg = RREG32(R600_CONFIG_MEMSIZE);
sys/dev/pci/drm/radeon/radeon_device.c
720
reg = RREG32(RADEON_CONFIG_MEMSIZE);
sys/dev/pci/drm/radeon/radeon_device.c
722
if (reg)
sys/dev/pci/drm/radeon/radeon_device.c
844
static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
sys/dev/pci/drm/radeon/radeon_device.c
849
r = rdev->pll_rreg(rdev, reg);
sys/dev/pci/drm/radeon/radeon_device.c
862
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
sys/dev/pci/drm/radeon/radeon_device.c
866
rdev->pll_wreg(rdev, reg, val);
sys/dev/pci/drm/radeon/radeon_device.c
878
static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
sys/dev/pci/drm/radeon/radeon_device.c
883
r = rdev->mc_rreg(rdev, reg);
sys/dev/pci/drm/radeon/radeon_device.c
896
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
sys/dev/pci/drm/radeon/radeon_device.c
900
rdev->mc_wreg(rdev, reg, val);
sys/dev/pci/drm/radeon/radeon_device.c
912
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
sys/dev/pci/drm/radeon/radeon_device.c
916
WREG32(reg*4, val);
sys/dev/pci/drm/radeon/radeon_device.c
928
static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
sys/dev/pci/drm/radeon/radeon_device.c
933
r = RREG32(reg*4);
sys/dev/pci/drm/radeon/radeon_device.c
946
static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
sys/dev/pci/drm/radeon/radeon_device.c
950
WREG32_IO(reg*4, val);
sys/dev/pci/drm/radeon/radeon_device.c
962
static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
sys/dev/pci/drm/radeon/radeon_device.c
967
r = RREG32_IO(reg*4);
sys/dev/pci/drm/radeon/radeon_i2c.c
103
u32 reg;
sys/dev/pci/drm/radeon/radeon_i2c.c
106
reg = RADEON_GPIO_MONID;
sys/dev/pci/drm/radeon/radeon_i2c.c
109
reg = RADEON_GPIO_DVI_DDC;
sys/dev/pci/drm/radeon/radeon_i2c.c
111
reg = RADEON_GPIO_CRT2_DDC;
sys/dev/pci/drm/radeon/radeon_i2c.c
114
if (rec->a_clk_reg == reg) {
sys/dev/pci/drm/radeon/radeon_i2c.c
430
u32 tmp, reg;
sys/dev/pci/drm/radeon/radeon_i2c.c
438
reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
sys/dev/pci/drm/radeon/radeon_i2c.c
479
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
sys/dev/pci/drm/radeon/radeon_i2c.c
482
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
sys/dev/pci/drm/radeon/radeon_i2c.c
495
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
sys/dev/pci/drm/radeon/radeon_i2c.c
498
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
sys/dev/pci/drm/radeon/radeon_i2c.c
501
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
sys/dev/pci/drm/radeon/radeon_i2c.c
514
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
sys/dev/pci/drm/radeon/radeon_i2c.c
517
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
sys/dev/pci/drm/radeon/radeon_i2c.c
535
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
sys/dev/pci/drm/radeon/radeon_i2c.c
538
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
sys/dev/pci/drm/radeon/radeon_i2c.c
541
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
sys/dev/pci/drm/radeon/radeon_i2c.c
570
WREG32(i2c_cntl_0, reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
602
WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
sys/dev/pci/drm/radeon/radeon_i2c.c
630
WREG32(i2c_cntl_0, reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
682
u32 tmp, reg;
sys/dev/pci/drm/radeon/radeon_i2c.c
743
reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
sys/dev/pci/drm/radeon/radeon_i2c.c
746
reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
sys/dev/pci/drm/radeon/radeon_i2c.c
749
reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
sys/dev/pci/drm/radeon/radeon_i2c.c
752
reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
sys/dev/pci/drm/radeon/radeon_i2c.c
777
WREG32(AVIVO_DC_I2C_CONTROL1, reg);
sys/dev/pci/drm/radeon/radeon_i2c.c
819
WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
sys/dev/pci/drm/radeon/radeon_i2c.c
862
WREG32(AVIVO_DC_I2C_CONTROL1, reg);
sys/dev/pci/drm/radeon/radeon_irq_kms.c
608
u32 reg, u32 mask,
sys/dev/pci/drm/radeon/radeon_irq_kms.c
611
u32 tmp = RREG32(reg);
sys/dev/pci/drm/radeon/radeon_irq_kms.c
619
WREG32(reg, tmp |= mask);
sys/dev/pci/drm/radeon/radeon_irq_kms.c
622
WREG32(reg, tmp & ~mask);
sys/dev/pci/drm/radeon/radeon_mode.h
480
u32 reg;
sys/dev/pci/drm/radeon/radeon_object.c
557
struct radeon_surface_reg *reg;
sys/dev/pci/drm/radeon/radeon_object.c
575
reg = &rdev->surface_regs[i];
sys/dev/pci/drm/radeon/radeon_object.c
576
if (!reg->bo)
sys/dev/pci/drm/radeon/radeon_object.c
579
old_object = reg->bo;
sys/dev/pci/drm/radeon/radeon_object.c
589
reg = &rdev->surface_regs[steal];
sys/dev/pci/drm/radeon/radeon_object.c
590
old_object = reg->bo;
sys/dev/pci/drm/radeon/radeon_object.c
599
reg->bo = bo;
sys/dev/pci/drm/radeon/radeon_object.c
611
struct radeon_surface_reg *reg;
sys/dev/pci/drm/radeon/radeon_object.c
616
reg = &rdev->surface_regs[bo->surface_reg];
sys/dev/pci/drm/radeon/radeon_object.c
619
reg->bo = NULL;
sys/dev/pci/drm/radeon/radeon_uvd.c
647
switch (pkt->reg + i*4) {
sys/dev/pci/drm/radeon/radeon_uvd.c
665
pkt->reg + i*4);
sys/dev/pci/drm/radeon/rs400.c
298
uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
sys/dev/pci/drm/radeon/rs400.c
304
WREG32(RS480_NB_MC_INDEX, reg & 0xff);
sys/dev/pci/drm/radeon/rs400.c
311
void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
sys/dev/pci/drm/radeon/rs400.c
316
WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
sys/dev/pci/drm/radeon/rs600.c
238
tmp = RREG32(voltage->gpio.reg);
sys/dev/pci/drm/radeon/rs600.c
243
WREG32(voltage->gpio.reg, tmp);
sys/dev/pci/drm/radeon/rs600.c
247
tmp = RREG32(voltage->gpio.reg);
sys/dev/pci/drm/radeon/rs600.c
252
WREG32(voltage->gpio.reg, tmp);
sys/dev/pci/drm/radeon/rs600.c
930
uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
sys/dev/pci/drm/radeon/rs600.c
936
WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
sys/dev/pci/drm/radeon/rs600.c
943
void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
sys/dev/pci/drm/radeon/rs600.c
948
WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
sys/dev/pci/drm/radeon/rs690.c
651
uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
sys/dev/pci/drm/radeon/rs690.c
657
WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
sys/dev/pci/drm/radeon/rs690.c
664
void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
sys/dev/pci/drm/radeon/rs690.c
669
WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
sys/dev/pci/drm/radeon/rv515.c
196
uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
sys/dev/pci/drm/radeon/rv515.c
202
WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
sys/dev/pci/drm/radeon/rv515.c
210
void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
sys/dev/pci/drm/radeon/rv515.c
215
WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
sys/dev/pci/drm/radeon/rv515d.h
200
#define PACKET0(reg, n) (CP_PACKET0 | \
sys/dev/pci/drm/radeon/rv515d.h
201
REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
sys/dev/pci/drm/radeon/rv770d.h
985
#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
sys/dev/pci/drm/radeon/rv770d.h
986
(((reg) >> 2) & 0xFFFF) | \
sys/dev/pci/drm/radeon/si.c
1288
u32 reg, u32 *val)
sys/dev/pci/drm/radeon/si.c
1290
switch (reg) {
sys/dev/pci/drm/radeon/si.c
1300
*val = RREG32(reg);
sys/dev/pci/drm/radeon/si.c
3346
rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
sys/dev/pci/drm/radeon/si.c
4358
uint32_t reg;
sys/dev/pci/drm/radeon/si.c
4360
reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2);
sys/dev/pci/drm/radeon/si.c
4362
reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2);
sys/dev/pci/drm/radeon/si.c
4363
rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
sys/dev/pci/drm/radeon/si.c
4391
static bool si_vm_reg_valid(u32 reg)
sys/dev/pci/drm/radeon/si.c
4394
if (reg >= 0x28000)
sys/dev/pci/drm/radeon/si.c
4398
if (reg >= 0xB000 && reg < 0xC000)
sys/dev/pci/drm/radeon/si.c
4402
switch (reg) {
sys/dev/pci/drm/radeon/si.c
4432
DRM_ERROR("Invalid register 0x%x in CS\n", reg);
sys/dev/pci/drm/radeon/si.c
4461
u32 start_reg, reg, i;
sys/dev/pci/drm/radeon/si.c
4470
reg = start_reg;
sys/dev/pci/drm/radeon/si.c
4471
if (!si_vm_reg_valid(reg)) {
sys/dev/pci/drm/radeon/si.c
4477
reg = start_reg + (4 * i);
sys/dev/pci/drm/radeon/si.c
4478
if (!si_vm_reg_valid(reg)) {
sys/dev/pci/drm/radeon/si.c
4491
reg = start_reg;
sys/dev/pci/drm/radeon/si.c
4492
if (!si_vm_reg_valid(reg)) {
sys/dev/pci/drm/radeon/si.c
4498
reg = start_reg + (4 * i);
sys/dev/pci/drm/radeon/si.c
4499
if (!si_vm_reg_valid(reg)) {
sys/dev/pci/drm/radeon/si.c
4516
u32 start_reg, end_reg, reg, i;
sys/dev/pci/drm/radeon/si.c
4567
reg = ib[idx + 3] * 4;
sys/dev/pci/drm/radeon/si.c
4568
if (!si_vm_reg_valid(reg))
sys/dev/pci/drm/radeon/si.c
4580
reg = start_reg + (4 * i);
sys/dev/pci/drm/radeon/si.c
4581
if (!si_vm_reg_valid(reg))
sys/dev/pci/drm/radeon/si.c
4589
reg = ib[idx + 5] * 4;
sys/dev/pci/drm/radeon/si.c
4590
if (!si_vm_reg_valid(reg))
sys/dev/pci/drm/radeon/si.c
4596
reg = ib[idx + 3] * 4;
sys/dev/pci/drm/radeon/si.c
4597
if (!si_vm_reg_valid(reg))
sys/dev/pci/drm/radeon/si.c
4611
reg = start_reg + (4 * i);
sys/dev/pci/drm/radeon/si.c
4612
if (!si_vm_reg_valid(reg))
sys/dev/pci/drm/radeon/si.c
4634
u32 start_reg, reg, i;
sys/dev/pci/drm/radeon/si.c
4670
reg = ib[idx + 3] * 4;
sys/dev/pci/drm/radeon/si.c
4671
if (!si_vm_reg_valid(reg))
sys/dev/pci/drm/radeon/si.c
4683
reg = start_reg + (4 * i);
sys/dev/pci/drm/radeon/si.c
4684
if (!si_vm_reg_valid(reg))
sys/dev/pci/drm/radeon/si.c
4692
reg = ib[idx + 5] * 4;
sys/dev/pci/drm/radeon/si.c
4693
if (!si_vm_reg_valid(reg))
sys/dev/pci/drm/radeon/si.c
4699
reg = ib[idx + 3] * 4;
sys/dev/pci/drm/radeon/si.c
4700
if (!si_vm_reg_valid(reg))
sys/dev/pci/drm/radeon/si_dpm.c
2595
u32 load_line_slope, reg;
sys/dev/pci/drm/radeon/si_dpm.c
2606
reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
2607
reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
sys/dev/pci/drm/radeon/si_dpm.c
2608
WREG32(CG_CAC_CTRL, reg);
sys/dev/pci/drm/radeon/si_dpm.c
4316
u32 reg;
sys/dev/pci/drm/radeon/si_dpm.c
4394
reg = CG_R(0xffff) | CG_L(0);
sys/dev/pci/drm/radeon/si_dpm.c
4395
table->initialState.level.aT = cpu_to_be32(reg);
sys/dev/pci/drm/radeon/si_dpm.c
4422
reg = MIN_POWER_MASK | MAX_POWER_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
4423
table->initialState.level.SQPowerThrottle = cpu_to_be32(reg);
sys/dev/pci/drm/radeon/si_dpm.c
4425
reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
4426
table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
sys/dev/pci/drm/radeon/si_dpm.c
4448
u32 reg;
sys/dev/pci/drm/radeon/si_dpm.c
4563
reg = MIN_POWER_MASK | MAX_POWER_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
4564
table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg);
sys/dev/pci/drm/radeon/si_dpm.c
4566
reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
sys/dev/pci/drm/radeon/si_dpm.c
4567
table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
sys/dev/pci/drm/radeon/sid.h
1586
#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
sys/dev/pci/drm/radeon/sid.h
1587
(((reg) >> 2) & 0xFFFF) | \
sys/dev/pci/emuxki.c
2318
emuxki_ac97_read(void *arg, u_int8_t reg, u_int16_t *val)
sys/dev/pci/emuxki.c
2323
bus_space_write_1(sc->sc_iot, sc->sc_ioh, EMU_AC97ADDR, reg);
sys/dev/pci/emuxki.c
2331
emuxki_ac97_write(void *arg, u_int8_t reg, u_int16_t val)
sys/dev/pci/emuxki.c
2336
bus_space_write_1(sc->sc_iot, sc->sc_ioh, EMU_AC97ADDR, reg);
sys/dev/pci/emuxki.c
576
emuxki_read(struct emuxki_softc *sc, u_int16_t chano, u_int32_t reg)
sys/dev/pci/emuxki.c
581
ptr = ((((u_int32_t) reg) << 16) &
sys/dev/pci/emuxki.c
585
if (reg & 0xff000000) {
sys/dev/pci/emuxki.c
586
size = (reg >> 24) & 0x3f;
sys/dev/pci/emuxki.c
587
offset = (reg >> 16) & 0x1f;
sys/dev/pci/emuxki.c
599
u_int32_t reg, u_int32_t data)
sys/dev/pci/emuxki.c
604
ptr = ((((u_int32_t) reg) << 16) &
sys/dev/pci/emuxki.c
613
if (reg & 0xff000000) {
sys/dev/pci/emuxki.c
614
size = (reg >> 24) & 0x3f;
sys/dev/pci/emuxki.c
615
offset = (reg >> 16) & 0x1f;
sys/dev/pci/emuxki.c
618
(emuxki_read(sc, chano, reg & 0xffff) & ~mask);
sys/dev/pci/emuxkireg.h
49
#define EMU_MKSUBREG(sz, idx, reg) (((sz) << 24) | ((idx) << 16) | (reg))
sys/dev/pci/envy.c
1009
envy_ccs_read(struct envy_softc *sc, int reg)
sys/dev/pci/envy.c
1013
val = bus_space_read_1(sc->ccs_iot, sc->ccs_ioh, reg);
sys/dev/pci/envy.c
1020
envy_ccs_write(struct envy_softc *sc, int reg, int val)
sys/dev/pci/envy.c
1022
bus_space_write_1(sc->ccs_iot, sc->ccs_ioh, reg, val);
sys/dev/pci/envy.c
1028
envy_mt_read_1(struct envy_softc *sc, int reg)
sys/dev/pci/envy.c
1032
val = bus_space_read_1(sc->mt_iot, sc->mt_ioh, reg);
sys/dev/pci/envy.c
1039
envy_mt_write_1(struct envy_softc *sc, int reg, int val)
sys/dev/pci/envy.c
1041
bus_space_write_1(sc->mt_iot, sc->mt_ioh, reg, val);
sys/dev/pci/envy.c
1047
envy_mt_read_2(struct envy_softc *sc, int reg)
sys/dev/pci/envy.c
1051
val = bus_space_read_2(sc->mt_iot, sc->mt_ioh, reg);
sys/dev/pci/envy.c
1058
envy_mt_write_2(struct envy_softc *sc, int reg, int val)
sys/dev/pci/envy.c
1060
bus_space_write_2(sc->mt_iot, sc->mt_ioh, reg, val);
sys/dev/pci/envy.c
1066
envy_mt_read_4(struct envy_softc *sc, int reg)
sys/dev/pci/envy.c
1070
val = bus_space_read_4(sc->mt_iot, sc->mt_ioh, reg);
sys/dev/pci/envy.c
1077
envy_mt_write_4(struct envy_softc *sc, int reg, int val)
sys/dev/pci/envy.c
1079
bus_space_write_4(sc->mt_iot, sc->mt_ioh, reg, val);
sys/dev/pci/envy.c
1110
envy_gpio_setstate(struct envy_softc *sc, int reg)
sys/dev/pci/envy.c
1113
envy_ccs_write(sc, ENVY_CCS_GPIODATA0, reg & 0xff);
sys/dev/pci/envy.c
1114
envy_ccs_write(sc, ENVY_CCS_GPIODATA1, (reg >> 8) & 0xff);
sys/dev/pci/envy.c
1115
envy_ccs_write(sc, ENVY_CCS_GPIODATA2, (reg >> 16) & 0xff);
sys/dev/pci/envy.c
1117
envy_cci_write(sc, ENVY_CCI_GPIODATA, reg);
sys/dev/pci/envy.c
1167
int reg;
sys/dev/pci/envy.c
1169
reg = envy_gpio_getstate(sc);
sys/dev/pci/envy.c
1170
reg |= (sda | scl);
sys/dev/pci/envy.c
1171
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
1173
reg &= ~sda;
sys/dev/pci/envy.c
1174
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
1176
reg &= ~scl;
sys/dev/pci/envy.c
1177
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
1184
int reg;
sys/dev/pci/envy.c
1186
reg = envy_gpio_getstate(sc);
sys/dev/pci/envy.c
1187
reg &= ~sda;
sys/dev/pci/envy.c
1188
reg |= scl;
sys/dev/pci/envy.c
1189
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
1191
reg |= sda;
sys/dev/pci/envy.c
1192
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
1198
int mask, reg;
sys/dev/pci/envy.c
1200
reg = envy_gpio_getstate(sc);
sys/dev/pci/envy.c
1203
reg &= ~sda;
sys/dev/pci/envy.c
1204
reg |= (val & mask) ? sda : 0;
sys/dev/pci/envy.c
1205
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
1207
reg |= scl;
sys/dev/pci/envy.c
1208
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
1210
reg &= ~scl;
sys/dev/pci/envy.c
1211
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
1215
reg |= scl;
sys/dev/pci/envy.c
1216
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
1218
reg &= ~scl;
sys/dev/pci/envy.c
1219
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
1326
envy_ac97_read_codec(void *hdl, u_int8_t reg, u_int16_t *result)
sys/dev/pci/envy.c
1335
envy_mt_write_1(sc, ENVY_MT_AC97_IDX, reg & 0x7f);
sys/dev/pci/envy.c
1351
envy_ac97_write_codec(void *hdl, u_int8_t reg, u_int16_t data)
sys/dev/pci/envy.c
1360
envy_mt_write_1(sc, ENVY_MT_AC97_IDX, reg & 0x7f);
sys/dev/pci/envy.c
1414
int i, reg;
sys/dev/pci/envy.c
1494
reg = ~ENVY_CCS_INT_MT;
sys/dev/pci/envy.c
1496
reg &= ~ENVY_CCS_INT_MIDI0;
sys/dev/pci/envy.c
1511
int reg, shift, src;
sys/dev/pci/envy.c
1514
reg = envy_mt_read_4(sc, ENVY_MT_HTSRC);
sys/dev/pci/envy.c
1515
DPRINTF("%s: outsrc=%x\n", DEVNAME(sc), reg);
sys/dev/pci/envy.c
1517
src = (reg >> shift) & ENVY_MT_HTSRC_MASK;
sys/dev/pci/envy.c
1526
reg = envy_mt_read_2(sc, ENVY_MT_OUTSRC);
sys/dev/pci/envy.c
1527
DPRINTF("%s: outsrc=%x\n", DEVNAME(sc), reg);
sys/dev/pci/envy.c
1529
src = (reg >> shift) & 3;
sys/dev/pci/envy.c
1535
reg = envy_mt_read_4(sc, ENVY_MT_INSEL);
sys/dev/pci/envy.c
1536
DPRINTF("%s: insel=%x\n", DEVNAME(sc), reg);
sys/dev/pci/envy.c
1537
reg = (reg >> (out * 4)) & 0xf;
sys/dev/pci/envy.c
1539
return ENVY_MIX_OUTSRC_LINEIN + (reg & 7);
sys/dev/pci/envy.c
1541
return ENVY_MIX_OUTSRC_SPDIN + (reg >> 3);
sys/dev/pci/envy.c
1547
int reg, shift, mask, sel;
sys/dev/pci/envy.c
1561
reg = envy_mt_read_4(sc, ENVY_MT_HTSRC);
sys/dev/pci/envy.c
1562
reg = (reg & ~mask) | (sel << shift);
sys/dev/pci/envy.c
1563
envy_mt_write_4(sc, ENVY_MT_HTSRC, reg);
sys/dev/pci/envy.c
1564
DPRINTF("%s: outsrc <- %x\n", DEVNAME(sc), reg);
sys/dev/pci/envy.c
1580
reg = envy_mt_read_4(sc, ENVY_MT_INSEL);
sys/dev/pci/envy.c
1581
reg = (reg & ~mask) | (sel << shift);
sys/dev/pci/envy.c
1582
envy_mt_write_4(sc, ENVY_MT_INSEL, reg);
sys/dev/pci/envy.c
1583
DPRINTF("%s: insel <- %x\n", DEVNAME(sc), reg);
sys/dev/pci/envy.c
1600
reg = envy_mt_read_2(sc, ENVY_MT_OUTSRC);
sys/dev/pci/envy.c
1601
reg = (reg & ~mask) | (sel << shift);
sys/dev/pci/envy.c
1602
envy_mt_write_2(sc, ENVY_MT_OUTSRC, reg);
sys/dev/pci/envy.c
1603
DPRINTF("%s: outsrc <- %x\n", DEVNAME(sc), reg);
sys/dev/pci/envy.c
1610
int reg, src, sel;
sys/dev/pci/envy.c
1612
reg = envy_mt_read_2(sc, ENVY_MT_SPDROUTE);
sys/dev/pci/envy.c
1613
DPRINTF("%s: spdroute=%x\n", DEVNAME(sc), reg);
sys/dev/pci/envy.c
1614
src = (out == 0) ? reg : reg >> 2;
sys/dev/pci/envy.c
1622
sel = (out == 0) ? reg >> 8 : reg >> 12;
sys/dev/pci/envy.c
1633
int reg, shift, mask, sel;
sys/dev/pci/envy.c
1635
reg = envy_mt_read_2(sc, ENVY_MT_SPDROUTE);
sys/dev/pci/envy.c
1648
reg = (reg & ~mask) | (sel << shift);
sys/dev/pci/envy.c
1665
reg = (reg & ~mask) | (sel << shift);
sys/dev/pci/envy.c
1666
envy_mt_write_2(sc, ENVY_MT_SPDROUTE, reg);
sys/dev/pci/envy.c
1667
DPRINTF("%s: spdroute <- %x\n", DEVNAME(sc), reg);
sys/dev/pci/envy.c
1673
int reg;
sys/dev/pci/envy.c
1676
reg = envy_mt_read_1(sc, ENVY_MT_MONDATA + ch);
sys/dev/pci/envy.c
1677
*val = 0x7f - (reg & 0x7f);
sys/dev/pci/envy.c
1683
int reg;
sys/dev/pci/envy.c
1686
reg = 0x7f - val;
sys/dev/pci/envy.c
1687
DPRINTF("%s: mon=%d/%d <- %d\n", DEVNAME(sc), reg, ch, val);
sys/dev/pci/envy.c
1688
envy_mt_write_1(sc, ENVY_MT_MONDATA + ch, reg);
sys/dev/pci/envy.c
1901
int i, rate, reg;
sys/dev/pci/envy.c
1926
reg = envy_mt_read_1(sc, ENVY_MT_FMT);
sys/dev/pci/envy.c
1928
reg |= ENVY_MT_FMT_128X;
sys/dev/pci/envy.c
1930
reg &= ~ENVY_MT_FMT_128X;
sys/dev/pci/envy.c
1931
envy_mt_write_1(sc, ENVY_MT_FMT, reg);
sys/dev/pci/envy.c
1937
reg = envy_mt_read_1(sc, ENVY_MT_RATE);
sys/dev/pci/envy.c
1938
reg &= ~ENVY_MT_RATEMASK;
sys/dev/pci/envy.c
1939
reg |= envy_rates[i].reg;
sys/dev/pci/envy.c
1940
envy_mt_write_1(sc, ENVY_MT_RATE, reg);
sys/dev/pci/envy.c
1998
unsigned int reg, hwpos, cnt;
sys/dev/pci/envy.c
2044
reg = envy_mt_read_2(sc, ENVY_MT_PBUFSZ);
sys/dev/pci/envy.c
2045
hwpos = sc->obuf.bufsz - 4 * (reg + 1);
sys/dev/pci/envy.c
2049
DEVNAME(sc), reg, sc->obuf.swpos, hwpos);
sys/dev/pci/envy.c
2079
reg = envy_mt_read_2(sc, ENVY_MT_RBUFSZ);
sys/dev/pci/envy.c
2080
hwpos = sc->ibuf.bufsz - 4 * (reg + 1);
sys/dev/pci/envy.c
2084
DEVNAME(sc), reg, sc->ibuf.swpos, hwpos);
sys/dev/pci/envy.c
219
int rate, reg;
sys/dev/pci/envy.c
2456
unsigned int i, reg;
sys/dev/pci/envy.c
2460
reg = envy_ccs_read(sc, ENVY_CCS_MIDISTAT0);
sys/dev/pci/envy.c
2461
if (reg & ENVY_MIDISTAT_IEMPTY(sc))
sys/dev/pci/envy.c
2480
reg = envy_ccs_read(sc, ENVY_CCS_INTMASK);
sys/dev/pci/envy.c
2481
reg &= ~ENVY_CCS_INT_MIDI0;
sys/dev/pci/envy.c
2482
envy_ccs_write(sc, ENVY_CCS_INTMASK, reg);
sys/dev/pci/envy.c
2490
unsigned int reg;
sys/dev/pci/envy.c
2496
reg = envy_ccs_read(sc, ENVY_CCS_INTMASK);
sys/dev/pci/envy.c
2497
reg |= ENVY_CCS_INT_MIDI0;
sys/dev/pci/envy.c
2498
envy_ccs_write(sc, ENVY_CCS_INTMASK, reg);
sys/dev/pci/envy.c
371
int bits, i, reg;
sys/dev/pci/envy.c
389
reg = envy_gpio_getstate(sc);
sys/dev/pci/envy.c
390
reg &= ~csmask;
sys/dev/pci/envy.c
391
reg |= cs;
sys/dev/pci/envy.c
392
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
397
reg &= ~(clk | dout);
sys/dev/pci/envy.c
398
reg |= (bits & 0x8000) ? dout : 0;
sys/dev/pci/envy.c
399
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
402
reg |= clk;
sys/dev/pci/envy.c
403
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
408
reg |= csmask;
sys/dev/pci/envy.c
409
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
434
int i, reg;
sys/dev/pci/envy.c
447
reg = envy_gpio_getstate(sc);
sys/dev/pci/envy.c
448
reg &= ~(AP192K_AK5385_PWR | AP192K_AK5385_SPD_MASK);
sys/dev/pci/envy.c
449
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
450
reg |= AP192K_AK5385_PWR;
sys/dev/pci/envy.c
451
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
457
int bits, i, reg;
sys/dev/pci/envy.c
459
reg = envy_gpio_getstate(sc);
sys/dev/pci/envy.c
460
reg &= ~AP192K_GPIO_CSMASK;
sys/dev/pci/envy.c
461
reg |= AP192K_GPIO_CS(dev);
sys/dev/pci/envy.c
462
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
467
reg &= ~(AP192K_GPIO_CLK | AP192K_GPIO_DOUT);
sys/dev/pci/envy.c
468
reg |= (bits & 0x8000) ? AP192K_GPIO_DOUT : 0;
sys/dev/pci/envy.c
469
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
472
reg |= AP192K_GPIO_CLK;
sys/dev/pci/envy.c
473
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
478
reg |= AP192K_GPIO_CSMASK;
sys/dev/pci/envy.c
479
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
486
int reg;
sys/dev/pci/envy.c
489
reg = envy_gpio_getstate(sc) & ~(AP192K_AK5385_SPD_MASK);
sys/dev/pci/envy.c
491
reg |= AP192K_AK5385_CKS0 | AP192K_AK5385_DFS1;
sys/dev/pci/envy.c
493
reg |= AP192K_AK5385_DFS0;
sys/dev/pci/envy.c
494
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
513
int bits, i, reg;
sys/dev/pci/envy.c
515
reg = envy_gpio_getstate(sc);
sys/dev/pci/envy.c
516
reg |= (EWX_GPIO_CSMASK | EWX_GPIO_CLK);
sys/dev/pci/envy.c
517
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
522
reg &= ~(EWX_GPIO_CLK | EWX_GPIO_DOUT);
sys/dev/pci/envy.c
523
reg |= (bits & 0x8000) ? EWX_GPIO_DOUT : 0;
sys/dev/pci/envy.c
524
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
527
reg |= EWX_GPIO_CLK;
sys/dev/pci/envy.c
528
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
533
reg &= ~EWX_GPIO_CSMASK;
sys/dev/pci/envy.c
534
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
537
reg |= EWX_GPIO_CSMASK;
sys/dev/pci/envy.c
538
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
560
int i, reg;
sys/dev/pci/envy.c
582
reg = envy_gpio_getstate(sc);
sys/dev/pci/envy.c
583
reg |= REVO51_MUTE;
sys/dev/pci/envy.c
584
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
590
int attn, bits, mask, reg;
sys/dev/pci/envy.c
595
reg = envy_gpio_getstate(sc);
sys/dev/pci/envy.c
596
reg &= ~REVO51_GPIO_CSMASK;
sys/dev/pci/envy.c
597
reg |= REVO51_GPIO_CS(dev);
sys/dev/pci/envy.c
598
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
603
reg &= ~(REVO51_GPIO_CLK | REVO51_GPIO_DOUT);
sys/dev/pci/envy.c
604
reg |= (bits & mask) ? REVO51_GPIO_DOUT : 0;
sys/dev/pci/envy.c
605
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
608
reg |= REVO51_GPIO_CLK;
sys/dev/pci/envy.c
609
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
613
reg |= REVO51_GPIO_CSMASK;
sys/dev/pci/envy.c
614
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
707
int reg;
sys/dev/pci/envy.c
710
reg = envy_gpio_getstate(sc) & ~(JULIA_AK5385_MASK);
sys/dev/pci/envy.c
712
reg |= JULIA_AK5385_CKS0 | JULIA_AK5385_DFS1;
sys/dev/pci/envy.c
714
reg |= JULIA_AK5385_DFS0;
sys/dev/pci/envy.c
715
envy_gpio_setstate(sc, reg);
sys/dev/pci/envy.c
789
int reg;
sys/dev/pci/envy.c
791
reg = AK4358_SPEED_DEFAULT & ~(AK4358_SPEED_DFS0 | AK4358_SPEED_DFS1);
sys/dev/pci/envy.c
793
reg |= AK4358_SPEED_DFS1;
sys/dev/pci/envy.c
795
reg |= AK4358_SPEED_DFS0;
sys/dev/pci/envy.c
798
reg &= ~AK4358_SPEED_RSTN;
sys/dev/pci/envy.c
799
envy_codec_write(sc, 0, AK4358_SPEED, reg);
sys/dev/pci/envy.c
802
reg |= AK4358_SPEED_RSTN;
sys/dev/pci/envy.c
803
envy_codec_write(sc, 0, AK4358_SPEED, reg);
sys/dev/pci/esa.c
1111
esa_read_codec(void *aux, u_int8_t reg, u_int16_t *result)
sys/dev/pci/esa.c
1119
bus_space_write_1(iot, ioh, ESA_CODEC_COMMAND, (reg & 0x7f) | 0x80);
sys/dev/pci/esa.c
1129
esa_write_codec(void *aux, u_int8_t reg, u_int16_t data)
sys/dev/pci/esa.c
1140
bus_space_write_1(iot, ioh, ESA_CODEC_COMMAND, reg & 0x7f);
sys/dev/pci/eso.c
473
eso_write_ctlreg(struct eso_softc *sc, uint8_t reg, uint8_t val)
sys/dev/pci/eso.c
478
eso_write_cmd(sc, reg);
sys/dev/pci/eso.c
504
eso_read_ctlreg(struct eso_softc *sc, uint8_t reg)
sys/dev/pci/eso.c
507
eso_write_cmd(sc, reg);
sys/dev/pci/eso.c
512
eso_write_mixreg(struct eso_softc *sc, uint8_t reg, uint8_t val)
sys/dev/pci/eso.c
516
bus_space_write_1(sc->sc_sb_iot, sc->sc_sb_ioh, ESO_SB_MIXERADDR, reg);
sys/dev/pci/eso.c
521
eso_read_mixreg(struct eso_softc *sc, uint8_t reg)
sys/dev/pci/eso.c
525
bus_space_write_1(sc->sc_sb_iot, sc->sc_sb_ioh, ESO_SB_MIXERADDR, reg);
sys/dev/pci/fms.c
263
fms_read_codec(void *addr, u_int8_t reg, u_int16_t *val)
sys/dev/pci/fms.c
279
reg | FM_CODEC_CMD_READ);
sys/dev/pci/fms.c
296
fms_write_codec(void *addr, u_int8_t reg, u_int16_t val)
sys/dev/pci/fms.c
313
bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_CMD, reg);
sys/dev/pci/glxpcib.c
507
int reg, off = 0;
sys/dev/pci/glxpcib.c
509
reg = AMD5536_GPIO_IN_EN;
sys/dev/pci/glxpcib.c
514
reg += off;
sys/dev/pci/glxpcib.c
515
data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);
sys/dev/pci/glxpcib.c
518
reg = AMD5536_GPIO_READ_BACK + off;
sys/dev/pci/glxpcib.c
520
reg = AMD5536_GPIO_OUT_VAL + off;
sys/dev/pci/glxpcib.c
522
data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);
sys/dev/pci/glxpcib.c
532
int reg;
sys/dev/pci/glxpcib.c
534
reg = AMD5536_GPIO_OUT_VAL;
sys/dev/pci/glxpcib.c
537
reg += AMD5536_GPIOH_OFFSET;
sys/dev/pci/glxpcib.c
544
bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data);
sys/dev/pci/glxpcib.c
551
int n, reg[7], val[7], nreg = 0, off = 0;
sys/dev/pci/glxpcib.c
558
reg[nreg] = AMD5536_GPIO_IN_EN + off;
sys/dev/pci/glxpcib.c
564
reg[nreg] = AMD5536_GPIO_OUT_EN + off;
sys/dev/pci/glxpcib.c
570
reg[nreg] = AMD5536_GPIO_OD_EN + off;
sys/dev/pci/glxpcib.c
576
reg[nreg] = AMD5536_GPIO_PU_EN + off;
sys/dev/pci/glxpcib.c
582
reg[nreg] = AMD5536_GPIO_PD_EN + off;
sys/dev/pci/glxpcib.c
588
reg[nreg] = AMD5536_GPIO_IN_INVRT_EN + off;
sys/dev/pci/glxpcib.c
594
reg[nreg] = AMD5536_GPIO_OUT_INVRT_EN + off;
sys/dev/pci/glxpcib.c
602
bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg[n],
sys/dev/pci/ichwdt.c
113
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ICH_WDT_CONF);
sys/dev/pci/ichwdt.c
114
DPRINTF((": conf 0x%x", reg));
sys/dev/pci/ichwdt.c
117
sc->sc_divisor = (reg & ICH_WDT_CONF_PRE ? 32 : 32768);
sys/dev/pci/ichwdt.c
118
printf(": %s clock", (reg & ICH_WDT_CONF_PRE ? "1MHz" : "1kHz"));
sys/dev/pci/ichwdt.c
121
reg &= ~ICH_WDT_CONF_INT_MASK;
sys/dev/pci/ichwdt.c
122
reg |= ICH_WDT_CONF_INT_DIS;
sys/dev/pci/ichwdt.c
123
pci_conf_write(sc->sc_pc, sc->sc_tag, ICH_WDT_CONF, reg);
sys/dev/pci/ichwdt.c
126
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ICH_WDT_RELOAD);
sys/dev/pci/ichwdt.c
127
if (reg & ICH_WDT_RELOAD_TIMEOUT) {
sys/dev/pci/ichwdt.c
77
ichwdt_unlock_write(struct ichwdt_softc *sc, int reg, u_int32_t val)
sys/dev/pci/ichwdt.c
84
bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, val);
sys/dev/pci/ichwdt.c
99
u_int32_t reg;
sys/dev/pci/if_age.c
1084
uint32_t reg;
sys/dev/pci/if_age.c
1086
reg = CSR_READ_4(sc, AGE_MAC_CFG);
sys/dev/pci/if_age.c
1087
reg &= ~MAC_CFG_FULL_DUPLEX;
sys/dev/pci/if_age.c
1088
reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC);
sys/dev/pci/if_age.c
1089
reg &= ~MAC_CFG_SPEED_MASK;
sys/dev/pci/if_age.c
1095
reg |= MAC_CFG_SPEED_10_100;
sys/dev/pci/if_age.c
1098
reg |= MAC_CFG_SPEED_1000;
sys/dev/pci/if_age.c
1102
reg |= MAC_CFG_FULL_DUPLEX;
sys/dev/pci/if_age.c
1104
reg |= MAC_CFG_TX_FC;
sys/dev/pci/if_age.c
1106
reg |= MAC_CFG_RX_FC;
sys/dev/pci/if_age.c
1109
CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
sys/dev/pci/if_age.c
1485
uint32_t reg;
sys/dev/pci/if_age.c
1492
if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
sys/dev/pci/if_age.c
1499
reg);
sys/dev/pci/if_age.c
1513
uint32_t reg, fsize;
sys/dev/pci/if_age.c
1606
reg = CSR_READ_4(sc, AGE_MASTER_CFG);
sys/dev/pci/if_age.c
1607
reg &= ~MASTER_MTIMER_ENB;
sys/dev/pci/if_age.c
1609
reg &= ~MASTER_ITIMER_ENB;
sys/dev/pci/if_age.c
1611
reg |= MASTER_ITIMER_ENB;
sys/dev/pci/if_age.c
1612
CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);
sys/dev/pci/if_age.c
1668
reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);
sys/dev/pci/if_age.c
1669
rxf_lo = reg / 16;
sys/dev/pci/if_age.c
1672
rxf_hi = (reg * 7) / 8;
sys/dev/pci/if_age.c
1675
reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);
sys/dev/pci/if_age.c
1676
rrd_lo = reg / 8;
sys/dev/pci/if_age.c
1677
rrd_hi = (reg * 7) / 8;
sys/dev/pci/if_age.c
1761
reg = CSR_READ_4(sc, AGE_MAC_CFG);
sys/dev/pci/if_age.c
1762
reg |= MAC_CFG_RXCSUM_ENB;
sys/dev/pci/if_age.c
1769
CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
sys/dev/pci/if_age.c
1790
uint32_t reg;
sys/dev/pci/if_age.c
1826
if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
sys/dev/pci/if_age.c
1832
sc->sc_dev.dv_xname, reg);
sys/dev/pci/if_age.c
1957
uint32_t reg;
sys/dev/pci/if_age.c
1960
reg = CSR_READ_4(sc, AGE_MAC_CFG);
sys/dev/pci/if_age.c
1961
if ((reg & MAC_CFG_TX_ENB) != 0) {
sys/dev/pci/if_age.c
1962
reg &= ~MAC_CFG_TX_ENB;
sys/dev/pci/if_age.c
1963
CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
sys/dev/pci/if_age.c
1966
reg = CSR_READ_4(sc, AGE_DMA_CFG);
sys/dev/pci/if_age.c
1967
if ((reg & DMA_CFG_RD_ENB) != 0) {
sys/dev/pci/if_age.c
1968
reg &= ~DMA_CFG_RD_ENB;
sys/dev/pci/if_age.c
1969
CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
sys/dev/pci/if_age.c
1984
uint32_t reg;
sys/dev/pci/if_age.c
1987
reg = CSR_READ_4(sc, AGE_MAC_CFG);
sys/dev/pci/if_age.c
1988
if ((reg & MAC_CFG_RX_ENB) != 0) {
sys/dev/pci/if_age.c
1989
reg &= ~MAC_CFG_RX_ENB;
sys/dev/pci/if_age.c
1990
CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
sys/dev/pci/if_age.c
1993
reg = CSR_READ_4(sc, AGE_DMA_CFG);
sys/dev/pci/if_age.c
1994
if ((reg & DMA_CFG_WR_ENB) != 0) {
sys/dev/pci/if_age.c
1995
reg &= ~DMA_CFG_WR_ENB;
sys/dev/pci/if_age.c
1996
CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
sys/dev/pci/if_age.c
2149
uint32_t reg;
sys/dev/pci/if_age.c
2151
reg = CSR_READ_4(sc, AGE_MAC_CFG);
sys/dev/pci/if_age.c
2152
reg &= ~MAC_CFG_VLAN_TAG_STRIP;
sys/dev/pci/if_age.c
2154
reg |= MAC_CFG_VLAN_TAG_STRIP;
sys/dev/pci/if_age.c
2155
CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
sys/dev/pci/if_age.c
303
age_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_age.c
313
MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
sys/dev/pci/if_age.c
323
sc->sc_dev.dv_xname, phy, reg);
sys/dev/pci/if_age.c
334
age_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_age.c
345
MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
sys/dev/pci/if_age.c
356
sc->sc_dev.dv_xname, phy, reg);
sys/dev/pci/if_age.c
392
uint32_t reg;
sys/dev/pci/if_age.c
395
reg = CSR_READ_4(sc, AGE_MAC_CFG);
sys/dev/pci/if_age.c
399
reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
sys/dev/pci/if_age.c
400
CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
sys/dev/pci/if_age.c
510
uint32_t ea[2], reg;
sys/dev/pci/if_age.c
513
reg = CSR_READ_4(sc, AGE_SPI_CTRL);
sys/dev/pci/if_age.c
514
if ((reg & SPI_VPD_ENB) != 0) {
sys/dev/pci/if_age.c
516
reg &= ~SPI_VPD_ENB;
sys/dev/pci/if_age.c
517
CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
sys/dev/pci/if_age.c
530
reg = CSR_READ_4(sc, AGE_TWSI_CTRL);
sys/dev/pci/if_age.c
531
if ((reg & TWSI_CTRL_SW_LD_START) == 0)
sys/dev/pci/if_age.c
556
uint16_t reg, pn;
sys/dev/pci/if_age.c
584
reg = age_miibus_readreg(&sc->sc_dev, sc->age_phyaddr,
sys/dev/pci/if_age.c
586
if ((reg & PHY_CDTC_ENB) == 0)
sys/dev/pci/if_age.c
590
reg = age_miibus_readreg(&sc->sc_dev, sc->age_phyaddr,
sys/dev/pci/if_age.c
592
if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) {
sys/dev/pci/if_age.c
606
reg = age_miibus_readreg(&sc->sc_dev, sc->age_phyaddr,
sys/dev/pci/if_age.c
609
ATPHY_DBG_DATA, reg | 0x03);
sys/dev/pci/if_agereg.h
863
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_agereg.h
864
bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_agereg.h
865
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_agereg.h
866
bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_agereg.h
867
#define CSR_READ_2(sc, reg) \
sys/dev/pci/if_agereg.h
868
bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
sys/dev/pci/if_agereg.h
869
#define CSR_READ_4(sc, reg) \
sys/dev/pci/if_agereg.h
870
bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
sys/dev/pci/if_alc.c
165
alc_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_alc.c
174
v = alc_mii_readreg_816x(dev, phy, reg);
sys/dev/pci/if_alc.c
176
v = alc_mii_readreg_813x(dev, phy, reg);
sys/dev/pci/if_alc.c
182
alc_mii_readreg_813x(struct device *dev, int phy, int reg)
sys/dev/pci/if_alc.c
195
reg == MII_EXTSR)
sys/dev/pci/if_alc.c
199
MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
sys/dev/pci/if_alc.c
2023
uint32_t reg;
sys/dev/pci/if_alc.c
2026
reg = CSR_READ_4(sc, ALC_MAC_CFG);
sys/dev/pci/if_alc.c
2027
reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
sys/dev/pci/if_alc.c
2033
reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
sys/dev/pci/if_alc.c
2038
reg |= MAC_CFG_SPEED_10_100;
sys/dev/pci/if_alc.c
2041
reg |= MAC_CFG_SPEED_1000;
sys/dev/pci/if_alc.c
2045
reg |= MAC_CFG_FULL_DUPLEX;
sys/dev/pci/if_alc.c
2047
reg |= MAC_CFG_TX_FC;
sys/dev/pci/if_alc.c
2049
reg |= MAC_CFG_RX_FC;
sys/dev/pci/if_alc.c
2051
CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
sys/dev/pci/if_alc.c
2058
uint32_t *reg;
sys/dev/pci/if_alc.c
2072
for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
sys/dev/pci/if_alc.c
2073
reg++) {
sys/dev/pci/if_alc.c
2078
for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
sys/dev/pci/if_alc.c
2079
reg++) {
sys/dev/pci/if_alc.c
209
sc->sc_dev.dv_xname, phy, reg);
sys/dev/pci/if_alc.c
2092
uint32_t *reg;
sys/dev/pci/if_alc.c
2106
for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
sys/dev/pci/if_alc.c
2107
reg++) {
sys/dev/pci/if_alc.c
2108
*reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
sys/dev/pci/if_alc.c
2112
for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
sys/dev/pci/if_alc.c
2113
reg++) {
sys/dev/pci/if_alc.c
2114
*reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
sys/dev/pci/if_alc.c
217
alc_mii_readreg_816x(struct device *dev, int phy, int reg)
sys/dev/pci/if_alc.c
228
MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg));
sys/dev/pci/if_alc.c
238
sc->sc_dev.dv_xname, phy, reg);
sys/dev/pci/if_alc.c
246
alc_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_alc.c
254
alc_mii_writereg_816x(dev, phy, reg, val);
sys/dev/pci/if_alc.c
256
alc_mii_writereg_813x(dev, phy, reg, val);
sys/dev/pci/if_alc.c
2561
uint32_t reg;
sys/dev/pci/if_alc.c
2563
reg = CSR_READ_4(sc, ALC_MISC3);
sys/dev/pci/if_alc.c
2564
reg &= ~MISC3_25M_BY_SW;
sys/dev/pci/if_alc.c
2565
reg |= MISC3_25M_NOTO_INTNL;
sys/dev/pci/if_alc.c
2566
CSR_WRITE_4(sc, ALC_MISC3, reg);
sys/dev/pci/if_alc.c
2567
reg = CSR_READ_4(sc, ALC_MISC);
sys/dev/pci/if_alc.c
2573
reg &= ~MISC_PSW_OCP_MASK;
sys/dev/pci/if_alc.c
2574
reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT);
sys/dev/pci/if_alc.c
2575
reg &= ~MISC_INTNLOSC_OPEN;
sys/dev/pci/if_alc.c
2576
CSR_WRITE_4(sc, ALC_MISC, reg);
sys/dev/pci/if_alc.c
2577
CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);
sys/dev/pci/if_alc.c
2578
reg = CSR_READ_4(sc, ALC_MISC2);
sys/dev/pci/if_alc.c
2579
reg &= ~MISC2_CALB_START;
sys/dev/pci/if_alc.c
2580
CSR_WRITE_4(sc, ALC_MISC2, reg);
sys/dev/pci/if_alc.c
2581
CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START);
sys/dev/pci/if_alc.c
2583
reg &= ~MISC_INTNLOSC_OPEN;
sys/dev/pci/if_alc.c
2586
reg &= ~MISC_ISO_ENB;
sys/dev/pci/if_alc.c
2587
CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);
sys/dev/pci/if_alc.c
2588
CSR_WRITE_4(sc, ALC_MISC, reg);
sys/dev/pci/if_alc.c
2596
uint32_t reg, pmcfg = 0;
sys/dev/pci/if_alc.c
260
alc_mii_writereg_813x(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_alc.c
2614
reg = CSR_READ_4(sc, ALC_MASTER_CFG);
sys/dev/pci/if_alc.c
2615
reg |= MASTER_OOB_DIS_OFF | MASTER_RESET;
sys/dev/pci/if_alc.c
2616
CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
sys/dev/pci/if_alc.c
2636
reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
sys/dev/pci/if_alc.c
2637
if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC |
sys/dev/pci/if_alc.c
2645
reg);
sys/dev/pci/if_alc.c
2650
reg = CSR_READ_4(sc, ALC_MASTER_CFG);
sys/dev/pci/if_alc.c
2651
reg |= MASTER_CLK_SEL_DIS;
sys/dev/pci/if_alc.c
2652
CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
sys/dev/pci/if_alc.c
2659
reg = CSR_READ_4(sc, ALC_MISC3);
sys/dev/pci/if_alc.c
2660
reg &= ~MISC3_25M_BY_SW;
sys/dev/pci/if_alc.c
2661
reg |= MISC3_25M_NOTO_INTNL;
sys/dev/pci/if_alc.c
2662
CSR_WRITE_4(sc, ALC_MISC3, reg);
sys/dev/pci/if_alc.c
2663
reg = CSR_READ_4(sc, ALC_MISC);
sys/dev/pci/if_alc.c
2664
reg &= ~MISC_INTNLOSC_OPEN;
sys/dev/pci/if_alc.c
2666
reg &= ~MISC_ISO_ENB;
sys/dev/pci/if_alc.c
2667
CSR_WRITE_4(sc, ALC_MISC, reg);
sys/dev/pci/if_alc.c
268
MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
sys/dev/pci/if_alc.c
2684
uint32_t reg, rxf_hi, rxf_lo;
sys/dev/pci/if_alc.c
278
sc->sc_dev.dv_xname, phy, reg);
sys/dev/pci/if_alc.c
2803
reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;
sys/dev/pci/if_alc.c
2805
reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;
sys/dev/pci/if_alc.c
2806
CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
sys/dev/pci/if_alc.c
2811
reg = CSR_READ_4(sc, ALC_MASTER_CFG);
sys/dev/pci/if_alc.c
2812
reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
sys/dev/pci/if_alc.c
2813
reg |= MASTER_SA_TIMER_ENB;
sys/dev/pci/if_alc.c
2815
reg |= MASTER_IM_RX_TIMER_ENB;
sys/dev/pci/if_alc.c
2818
reg |= MASTER_IM_TX_TIMER_ENB;
sys/dev/pci/if_alc.c
2819
CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
sys/dev/pci/if_alc.c
282
alc_mii_writereg_816x(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_alc.c
2893
reg = (sc->alc_max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
sys/dev/pci/if_alc.c
2896
reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB;
sys/dev/pci/if_alc.c
2897
CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg);
sys/dev/pci/if_alc.c
2899
reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<
sys/dev/pci/if_alc.c
2903
reg >>= 1;
sys/dev/pci/if_alc.c
2904
reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &
sys/dev/pci/if_alc.c
2906
reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB;
sys/dev/pci/if_alc.c
2907
CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
sys/dev/pci/if_alc.c
2909
reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT |
sys/dev/pci/if_alc.c
2913
CSR_WRITE_4(sc, ALC_HQTD_CFG, reg);
sys/dev/pci/if_alc.c
2914
reg = WRR_PRI_RESTRICT_NONE;
sys/dev/pci/if_alc.c
2915
reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT |
sys/dev/pci/if_alc.c
2919
CSR_WRITE_4(sc, ALC_WRR, reg);
sys/dev/pci/if_alc.c
293
((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) |
sys/dev/pci/if_alc.c
2935
reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
sys/dev/pci/if_alc.c
2936
reg &= SRAM_RX_FIFO_LEN_MASK;
sys/dev/pci/if_alc.c
2937
reg *= 8;
sys/dev/pci/if_alc.c
2938
if (reg > 8 * 1024)
sys/dev/pci/if_alc.c
2939
reg -= RX_FIFO_PAUSE_816X_RSVD;
sys/dev/pci/if_alc.c
2941
reg -= RX_BUF_SIZE_MAX;
sys/dev/pci/if_alc.c
2942
reg /= 8;
sys/dev/pci/if_alc.c
2944
((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
sys/dev/pci/if_alc.c
2951
reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
sys/dev/pci/if_alc.c
2952
rxf_hi = (reg * 8) / 10;
sys/dev/pci/if_alc.c
2953
rxf_lo = (reg * 3) / 10;
sys/dev/pci/if_alc.c
2968
reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
sys/dev/pci/if_alc.c
2970
reg |= RXQ_CFG_RSS_MODE_DIS;
sys/dev/pci/if_alc.c
2972
reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT <<
sys/dev/pci/if_alc.c
2976
reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
sys/dev/pci/if_alc.c
2980
reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
sys/dev/pci/if_alc.c
2982
CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
sys/dev/pci/if_alc.c
2985
reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;
sys/dev/pci/if_alc.c
2986
reg |= sc->alc_rcb;
sys/dev/pci/if_alc.c
2988
reg |= DMA_CFG_CMB_ENB;
sys/dev/pci/if_alc.c
2990
reg |= DMA_CFG_SMB_ENB;
sys/dev/pci/if_alc.c
2992
reg |= DMA_CFG_SMB_DIS;
sys/dev/pci/if_alc.c
2993
reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) <<
sys/dev/pci/if_alc.c
2995
reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) <<
sys/dev/pci/if_alc.c
2997
reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
sys/dev/pci/if_alc.c
2999
reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
sys/dev/pci/if_alc.c
3005
reg |= DMA_CFG_RD_CHNL_SEL_2;
sys/dev/pci/if_alc.c
3010
reg |= DMA_CFG_RD_CHNL_SEL_4;
sys/dev/pci/if_alc.c
3014
CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
sys/dev/pci/if_alc.c
3029
reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
sys/dev/pci/if_alc.c
3036
reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
sys/dev/pci/if_alc.c
3038
reg |= MAC_CFG_SPEED_10_100;
sys/dev/pci/if_alc.c
304
sc->sc_dev.dv_xname, phy, reg);
sys/dev/pci/if_alc.c
3040
reg |= MAC_CFG_SPEED_1000;
sys/dev/pci/if_alc.c
3041
CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
sys/dev/pci/if_alc.c
3071
uint32_t reg;
sys/dev/pci/if_alc.c
3091
reg = CSR_READ_4(sc, ALC_DMA_CFG);
sys/dev/pci/if_alc.c
3092
reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB);
sys/dev/pci/if_alc.c
3093
reg |= DMA_CFG_SMB_DIS;
sys/dev/pci/if_alc.c
3094
CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
sys/dev/pci/if_alc.c
3104
reg = CSR_READ_4(sc, ALC_PM_CFG);
sys/dev/pci/if_alc.c
3105
if ((reg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB))!= 0) {
sys/dev/pci/if_alc.c
3106
reg &= ~(PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB);
sys/dev/pci/if_alc.c
3107
CSR_WRITE_4(sc, ALC_PM_CFG, reg);
sys/dev/pci/if_alc.c
313
uint32_t reg;
sys/dev/pci/if_alc.c
3141
uint32_t reg;
sys/dev/pci/if_alc.c
3146
reg = CSR_READ_4(sc, ALC_MAC_CFG);
sys/dev/pci/if_alc.c
3147
if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
sys/dev/pci/if_alc.c
3148
reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
sys/dev/pci/if_alc.c
3149
CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
sys/dev/pci/if_alc.c
3152
reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
sys/dev/pci/if_alc.c
3153
if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0)
sys/dev/pci/if_alc.c
3159
sc->sc_dev.dv_xname, reg);
sys/dev/pci/if_alc.c
3192
uint32_t reg;
sys/dev/pci/if_alc.c
3196
reg = CSR_READ_4(sc, ALC_RXQ_CFG);
sys/dev/pci/if_alc.c
3198
if ((reg & RXQ_CFG_ENB) != 0) {
sys/dev/pci/if_alc.c
3199
reg &= ~RXQ_CFG_ENB;
sys/dev/pci/if_alc.c
3200
CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
sys/dev/pci/if_alc.c
3203
if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) {
sys/dev/pci/if_alc.c
3204
reg &= ~RXQ_CFG_QUEUE0_ENB;
sys/dev/pci/if_alc.c
3205
CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
sys/dev/pci/if_alc.c
3209
reg = CSR_READ_4(sc, ALC_TXQ_CFG);
sys/dev/pci/if_alc.c
3210
if ((reg & TXQ_CFG_ENB) != 0) {
sys/dev/pci/if_alc.c
3211
reg &= ~TXQ_CFG_ENB;
sys/dev/pci/if_alc.c
3212
CSR_WRITE_4(sc, ALC_TXQ_CFG, reg);
sys/dev/pci/if_alc.c
3216
reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
sys/dev/pci/if_alc.c
3217
if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
sys/dev/pci/if_alc.c
3223
sc->sc_dev.dv_xname, reg);
sys/dev/pci/if_alc.c
3322
uint32_t reg;
sys/dev/pci/if_alc.c
3324
reg = CSR_READ_4(sc, ALC_MAC_CFG);
sys/dev/pci/if_alc.c
3326
reg |= MAC_CFG_VLAN_TAG_STRIP;
sys/dev/pci/if_alc.c
3328
reg &= ~MAC_CFG_VLAN_TAG_STRIP;
sys/dev/pci/if_alc.c
3329
CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
sys/dev/pci/if_alc.c
342
reg = CSR_READ_4(sc, ALC_MAC_CFG);
sys/dev/pci/if_alc.c
343
reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
sys/dev/pci/if_alc.c
344
CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
sys/dev/pci/if_alc.c
351
alc_miidbg_readreg(struct alc_softc *sc, int reg)
sys/dev/pci/if_alc.c
354
reg);
sys/dev/pci/if_alc.c
361
alc_miidbg_writereg(struct alc_softc *sc, int reg, int val)
sys/dev/pci/if_alc.c
364
reg);
sys/dev/pci/if_alc.c
370
alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg)
sys/dev/pci/if_alc.c
375
CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |
sys/dev/pci/if_alc.c
392
sc->sc_dev.dv_xname, devaddr, reg);
sys/dev/pci/if_alc.c
400
alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val)
sys/dev/pci/if_alc.c
405
CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |
sys/dev/pci/if_alc.c
423
sc->sc_dev.dv_xname, devaddr, reg);
sys/dev/pci/if_alc.c
650
uint32_t reg;
sys/dev/pci/if_alc.c
656
reg = CSR_READ_4(sc, ALC_SLD);
sys/dev/pci/if_alc.c
657
if ((reg & (SLD_PROGRESS | SLD_START)) == 0)
sys/dev/pci/if_alc.c
662
CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START);
sys/dev/pci/if_alc.c
665
reg = CSR_READ_4(sc, ALC_SLD);
sys/dev/pci/if_alc.c
666
if ((reg & SLD_START) == 0)
sys/dev/pci/if_alc.c
678
reg = CSR_READ_4(sc, ALC_EEPROM_LD);
sys/dev/pci/if_alc.c
679
if ((reg & (EEPROM_LD_EEPROM_EXIST |
sys/dev/pci/if_alc.c
682
reg = CSR_READ_4(sc, ALC_EEPROM_LD);
sys/dev/pci/if_alc.c
683
if ((reg & (EEPROM_LD_PROGRESS |
sys/dev/pci/if_alc.c
689
CSR_WRITE_4(sc, ALC_EEPROM_LD, reg |
sys/dev/pci/if_alc.c
693
reg = CSR_READ_4(sc, ALC_EEPROM_LD);
sys/dev/pci/if_alc.c
694
if ((reg & EEPROM_LD_START) == 0)
sys/dev/pci/if_alcreg.h
1473
#define CSR_WRITE_4(_sc, reg, val) \
sys/dev/pci/if_alcreg.h
1474
bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_alcreg.h
1475
#define CSR_WRITE_2(_sc, reg, val) \
sys/dev/pci/if_alcreg.h
1476
bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_alcreg.h
1477
#define CSR_WRITE_1(_sc, reg, val) \
sys/dev/pci/if_alcreg.h
1478
bus_space_write_1((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_alcreg.h
1479
#define CSR_READ_2(_sc, reg) \
sys/dev/pci/if_alcreg.h
1480
bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
sys/dev/pci/if_alcreg.h
1481
#define CSR_READ_4(_sc, reg) \
sys/dev/pci/if_alcreg.h
1482
bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
sys/dev/pci/if_ale.c
1102
uint32_t reg;
sys/dev/pci/if_ale.c
1105
reg = CSR_READ_4(sc, ALE_MAC_CFG);
sys/dev/pci/if_ale.c
1106
reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
sys/dev/pci/if_ale.c
1112
reg |= MAC_CFG_SPEED_10_100;
sys/dev/pci/if_ale.c
1115
reg |= MAC_CFG_SPEED_1000;
sys/dev/pci/if_ale.c
1119
reg |= MAC_CFG_FULL_DUPLEX;
sys/dev/pci/if_ale.c
1121
reg |= MAC_CFG_TX_FC;
sys/dev/pci/if_ale.c
1123
reg |= MAC_CFG_RX_FC;
sys/dev/pci/if_ale.c
1125
CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
sys/dev/pci/if_ale.c
1132
uint32_t *reg;
sys/dev/pci/if_ale.c
1135
for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
sys/dev/pci/if_ale.c
1140
for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
sys/dev/pci/if_ale.c
1152
uint32_t *reg;
sys/dev/pci/if_ale.c
1159
for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
sys/dev/pci/if_ale.c
1160
*reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
sys/dev/pci/if_ale.c
1164
for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
sys/dev/pci/if_ale.c
1165
*reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
sys/dev/pci/if_ale.c
129
ale_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_ale.c
139
reg == MII_EXTSR)
sys/dev/pci/if_ale.c
143
MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
sys/dev/pci/if_ale.c
153
sc->sc_dev.dv_xname, phy, reg);
sys/dev/pci/if_ale.c
1552
uint32_t reg;
sys/dev/pci/if_ale.c
1568
if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
sys/dev/pci/if_ale.c
1575
reg);
sys/dev/pci/if_ale.c
1585
uint32_t reg, rxf_hi, rxf_lo;
sys/dev/pci/if_ale.c
161
ale_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_ale.c
1667
reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
sys/dev/pci/if_ale.c
1668
reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
sys/dev/pci/if_ale.c
1669
CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
sys/dev/pci/if_ale.c
1670
reg = CSR_READ_4(sc, ALE_MASTER_CFG);
sys/dev/pci/if_ale.c
1671
reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
sys/dev/pci/if_ale.c
1672
reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
sys/dev/pci/if_ale.c
1674
reg |= MASTER_IM_RX_TIMER_ENB;
sys/dev/pci/if_ale.c
1676
reg |= MASTER_IM_TX_TIMER_ENB;
sys/dev/pci/if_ale.c
1677
CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
sys/dev/pci/if_ale.c
1709
reg = sc->ale_max_frame_size;
sys/dev/pci/if_ale.c
1711
reg = (sc->ale_max_frame_size * 2) / 3;
sys/dev/pci/if_ale.c
1713
reg = sc->ale_max_frame_size / 2;
sys/dev/pci/if_ale.c
1715
roundup(reg, TX_JUMBO_THRESH_UNIT) >>
sys/dev/pci/if_ale.c
172
MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
sys/dev/pci/if_ale.c
1720
reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
sys/dev/pci/if_ale.c
1722
reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
sys/dev/pci/if_ale.c
1724
CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
sys/dev/pci/if_ale.c
1728
reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
sys/dev/pci/if_ale.c
1730
(((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
sys/dev/pci/if_ale.c
1734
reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
sys/dev/pci/if_ale.c
1735
rxf_hi = (reg * 7) / 10;
sys/dev/pci/if_ale.c
1736
rxf_lo = (reg * 3)/ 10;
sys/dev/pci/if_ale.c
1753
reg = 0;
sys/dev/pci/if_ale.c
1755
reg |= DMA_CFG_TXCMB_ENB;
sys/dev/pci/if_ale.c
1758
sc->ale_dma_rd_burst | reg |
sys/dev/pci/if_ale.c
1787
reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
sys/dev/pci/if_ale.c
1791
reg |= MAC_CFG_SPEED_10_100;
sys/dev/pci/if_ale.c
1793
reg |= MAC_CFG_SPEED_1000;
sys/dev/pci/if_ale.c
1794
CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
sys/dev/pci/if_ale.c
182
sc->sc_dev.dv_xname, phy, reg);
sys/dev/pci/if_ale.c
1825
uint32_t reg;
sys/dev/pci/if_ale.c
1845
reg = CSR_READ_4(sc, ALE_TXQ_CFG);
sys/dev/pci/if_ale.c
1846
reg &= ~TXQ_CFG_ENB;
sys/dev/pci/if_ale.c
1847
CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
sys/dev/pci/if_ale.c
1848
reg = CSR_READ_4(sc, ALE_RXQ_CFG);
sys/dev/pci/if_ale.c
1849
reg &= ~RXQ_CFG_ENB;
sys/dev/pci/if_ale.c
1850
CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
sys/dev/pci/if_ale.c
1851
reg = CSR_READ_4(sc, ALE_DMA_CFG);
sys/dev/pci/if_ale.c
1852
reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
sys/dev/pci/if_ale.c
1853
CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
sys/dev/pci/if_ale.c
1880
uint32_t reg;
sys/dev/pci/if_ale.c
1883
reg = CSR_READ_4(sc, ALE_MAC_CFG);
sys/dev/pci/if_ale.c
1884
if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
sys/dev/pci/if_ale.c
1885
reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
sys/dev/pci/if_ale.c
1886
CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
sys/dev/pci/if_ale.c
1890
reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
sys/dev/pci/if_ale.c
1891
if (reg == 0)
sys/dev/pci/if_ale.c
1897
sc->sc_dev.dv_xname, reg);
sys/dev/pci/if_ale.c
191
uint32_t reg;
sys/dev/pci/if_ale.c
1953
uint32_t reg;
sys/dev/pci/if_ale.c
1955
reg = CSR_READ_4(sc, ALE_MAC_CFG);
sys/dev/pci/if_ale.c
1956
reg &= ~MAC_CFG_VLAN_TAG_STRIP;
sys/dev/pci/if_ale.c
1958
reg |= MAC_CFG_VLAN_TAG_STRIP;
sys/dev/pci/if_ale.c
1959
CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
sys/dev/pci/if_ale.c
222
reg = CSR_READ_4(sc, ALE_MAC_CFG);
sys/dev/pci/if_ale.c
223
reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
sys/dev/pci/if_ale.c
224
CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
sys/dev/pci/if_ale.c
270
uint32_t ea[2], reg;
sys/dev/pci/if_ale.c
273
reg = CSR_READ_4(sc, ALE_SPI_CTRL);
sys/dev/pci/if_ale.c
274
if ((reg & SPI_VPD_ENB) != 0) {
sys/dev/pci/if_ale.c
275
reg &= ~SPI_VPD_ENB;
sys/dev/pci/if_ale.c
276
CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
sys/dev/pci/if_ale.c
289
reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
sys/dev/pci/if_ale.c
290
if ((reg & TWSI_CTRL_SW_LD_START) == 0)
sys/dev/pci/if_alereg.h
947
#define CSR_WRITE_4(_sc, reg, val) \
sys/dev/pci/if_alereg.h
948
bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_alereg.h
949
#define CSR_WRITE_2(_sc, reg, val) \
sys/dev/pci/if_alereg.h
950
bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_alereg.h
951
#define CSR_WRITE_1(_sc, reg, val) \
sys/dev/pci/if_alereg.h
952
bus_space_write_1((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_alereg.h
953
#define CSR_READ_2(_sc, reg) \
sys/dev/pci/if_alereg.h
954
bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
sys/dev/pci/if_alereg.h
955
#define CSR_READ_4(_sc, reg) \
sys/dev/pci/if_alereg.h
956
bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
sys/dev/pci/if_aq_pci.c
1883
uint32_t tid0, tid1, reg, *data, size;
sys/dev/pci/if_aq_pci.c
1896
for (reg = reg0, data = data0, size = size0;
sys/dev/pci/if_aq_pci.c
1897
size >= 4; reg += 4, data++, size -= 4) {
sys/dev/pci/if_aq_pci.c
1898
*data = AQ_READ_REG(sc, reg);
sys/dev/pci/if_aq_pci.c
614
#define AQ_READ_REG(sc, reg) \
sys/dev/pci/if_aq_pci.c
615
bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
sys/dev/pci/if_aq_pci.c
616
#define AQ_READ_REGS(sc, reg, p, cnt) \
sys/dev/pci/if_aq_pci.c
617
bus_space_read_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (p), (cnt));
sys/dev/pci/if_aq_pci.c
619
#define AQ_WRITE_REG(sc, reg, val) \
sys/dev/pci/if_aq_pci.c
620
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/pci/if_aq_pci.c
622
#define AQ_WRITE_REG_BIT(sc, reg, mask, val) \
sys/dev/pci/if_aq_pci.c
625
_v = AQ_READ_REG((sc), (reg)); \
sys/dev/pci/if_aq_pci.c
629
AQ_WRITE_REG((sc), (reg), _v); \
sys/dev/pci/if_aq_pci.c
632
#define AQ_READ64_REG(sc, reg) \
sys/dev/pci/if_aq_pci.c
633
((uint64_t)AQ_READ_REG(sc, reg) | \
sys/dev/pci/if_aq_pci.c
634
(((uint64_t)AQ_READ_REG(sc, (reg) + 4)) << 32))
sys/dev/pci/if_aq_pci.c
636
#define AQ_WRITE64_REG(sc, reg, val) \
sys/dev/pci/if_aq_pci.c
638
AQ_WRITE_REG(sc, reg, (uint32_t)val); \
sys/dev/pci/if_aq_pci.c
639
AQ_WRITE_REG(sc, reg + 4, (uint32_t)(val >> 32)); \
sys/dev/pci/if_athn_pci.c
113
pcireg_t memtype, reg;
sys/dev/pci/if_athn_pci.c
139
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x40);
sys/dev/pci/if_athn_pci.c
140
if (reg & 0xff00)
sys/dev/pci/if_athn_pci.c
141
pci_conf_write(pa->pa_pc, pa->pa_tag, 0x40, reg & ~0xff00);
sys/dev/pci/if_athn_pci.c
147
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
sys/dev/pci/if_athn_pci.c
148
if (PCI_CACHELINE(reg) == 0) {
sys/dev/pci/if_athn_pci.c
149
reg &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT);
sys/dev/pci/if_athn_pci.c
150
reg |= 8 << PCI_CACHELINE_SHIFT;
sys/dev/pci/if_athn_pci.c
152
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
sys/dev/pci/if_athn_pci.c
153
reg |= 168 << PCI_LATTIMER_SHIFT;
sys/dev/pci/if_athn_pci.c
154
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, reg);
sys/dev/pci/if_athn_pci.c
157
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
sys/dev/pci/if_athn_pci.c
158
subsysid = PCI_PRODUCT(reg);
sys/dev/pci/if_athn_pci.c
231
pcireg_t reg;
sys/dev/pci/if_athn_pci.c
234
reg = pci_conf_read(psc->sc_pc, psc->sc_tag, 0x40);
sys/dev/pci/if_athn_pci.c
235
if (reg & 0xff00)
sys/dev/pci/if_athn_pci.c
236
pci_conf_write(psc->sc_pc, psc->sc_tag, 0x40, reg & ~0xff00);
sys/dev/pci/if_athn_pci.c
272
pcireg_t reg;
sys/dev/pci/if_athn_pci.c
275
reg = pci_conf_read(psc->sc_pc, psc->sc_tag,
sys/dev/pci/if_athn_pci.c
277
reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1);
sys/dev/pci/if_athn_pci.c
279
psc->sc_cap_off + PCI_PCIE_LCSR, reg);
sys/dev/pci/if_bce.c
1201
bce_mii_read(struct device *self, int phy, int reg)
sys/dev/pci/if_bce.c
1214
(MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */
sys/dev/pci/if_bce.c
1226
"0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val);
sys/dev/pci/if_bce.c
1234
bce_mii_write(struct device *self, int phy, int reg, int val)
sys/dev/pci/if_bce.c
1248
BCE_MIPHY(phy) | BCE_MIREG(reg));
sys/dev/pci/if_bce.c
1261
"= 0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val);
sys/dev/pci/if_bce.c
1270
u_int32_t reg;
sys/dev/pci/if_bce.c
1273
reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL);
sys/dev/pci/if_bce.c
1274
if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD))
sys/dev/pci/if_bce.c
1276
reg | EXC_FD);
sys/dev/pci/if_bce.c
1277
else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD)
sys/dev/pci/if_bce.c
1279
reg & ~EXC_FD);
sys/dev/pci/if_bge.c
1004
bge_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_bge.c
1022
BGE_MIPHY(phy)|BGE_MIREG(reg));
sys/dev/pci/if_bge.c
1057
bge_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_bge.c
1064
(reg == MII_100T2CR || reg == BRGPHY_MII_AUXCTL))
sys/dev/pci/if_bge.c
1080
BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
sys/dev/pci/if_bge.c
2592
pcireg_t pm_ctl, memtype, subid, reg;
sys/dev/pci/if_bge.c
2692
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, sc->bge_expcap +
sys/dev/pci/if_bge.c
2694
sc->bge_mps = 128 << (reg & 0x7);
sys/dev/pci/if_bge.c
2701
reg = pci_conf_read(pa->pa_pc, pa->pa_tag,
sys/dev/pci/if_bge.c
2703
reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1);
sys/dev/pci/if_bge.c
2705
sc->bge_expcap + PCI_PCIE_LCSR, reg);
sys/dev/pci/if_bge.c
2891
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE);
sys/dev/pci/if_bge.c
2892
reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
sys/dev/pci/if_bge.c
2895
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg);
sys/dev/pci/if_bge.c
4641
bge_stop_block(struct bge_softc *sc, bus_size_t reg, u_int32_t bit)
sys/dev/pci/if_bge.c
4645
BGE_CLRBIT(sc, reg, bit);
sys/dev/pci/if_bge.c
4648
if ((CSR_READ_4(sc, reg) & bit) == 0)
sys/dev/pci/if_bge.c
4654
sc->bge_dev.dv_xname, (u_long) reg, bit));
sys/dev/pci/if_bge.c
4890
bus_size_t reg;
sys/dev/pci/if_bge.c
4991
if (bge_kstat_tpl[i].reg != 0)
sys/dev/pci/if_bge.c
4993
bge_kstat_tpl[i].reg);
sys/dev/pci/if_bgereg.h
2733
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_bgereg.h
2734
bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)
sys/dev/pci/if_bgereg.h
2736
#define CSR_READ_4(sc, reg) \
sys/dev/pci/if_bgereg.h
2737
bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)
sys/dev/pci/if_bgereg.h
2739
#define BGE_SETBIT(sc, reg, x) \
sys/dev/pci/if_bgereg.h
2740
CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
sys/dev/pci/if_bgereg.h
2741
#define BGE_CLRBIT(sc, reg, x) \
sys/dev/pci/if_bgereg.h
2742
CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
sys/dev/pci/if_bgereg.h
2745
#define APE_WRITE_4(sc, reg, val) \
sys/dev/pci/if_bgereg.h
2746
bus_space_write_4(sc->bge_apetag, sc->bge_apehandle, reg, val)
sys/dev/pci/if_bgereg.h
2748
#define APE_READ_4(sc, reg) \
sys/dev/pci/if_bgereg.h
2749
bus_space_read_4(sc->bge_apetag, sc->bge_apehandle, reg)
sys/dev/pci/if_bgereg.h
2751
#define APE_SETBIT(sc, reg, x) \
sys/dev/pci/if_bgereg.h
2752
APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x)))
sys/dev/pci/if_bgereg.h
2753
#define APE_CLRBIT(sc, reg, x) \
sys/dev/pci/if_bgereg.h
2754
APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x)))
sys/dev/pci/if_bgereg.h
2756
#define PCI_SETBIT(pc, tag, reg, x) \
sys/dev/pci/if_bgereg.h
2757
pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x)))
sys/dev/pci/if_bgereg.h
2758
#define PCI_CLRBIT(pc, tag, reg, x) \
sys/dev/pci/if_bgereg.h
2759
pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x)))
sys/dev/pci/if_bnx.c
1090
bnx_miibus_read_reg(struct device *dev, int phy, int reg)
sys/dev/pci/if_bnx.c
1102
if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
sys/dev/pci/if_bnx.c
1103
reg += 0x10;
sys/dev/pci/if_bnx.c
1116
val = BNX_MIPHY(phy) | BNX_MIREG(reg) |
sys/dev/pci/if_bnx.c
1137
"reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);
sys/dev/pci/if_bnx.c
1144
(u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff);
sys/dev/pci/if_bnx.c
1168
bnx_miibus_write_reg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_bnx.c
1176
phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff);
sys/dev/pci/if_bnx.c
1184
if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
sys/dev/pci/if_bnx.c
1185
reg += 0x10;
sys/dev/pci/if_bnx.c
1198
val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val |
sys/dev/pci/if_bnx.c
3524
u_int32_t reg, val;
sys/dev/pci/if_bnx.c
3580
reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE);
sys/dev/pci/if_bnx.c
3584
__FILE__, __LINE__); reg = 0);
sys/dev/pci/if_bnx.c
3586
if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
sys/dev/pci/if_bnx.c
3590
(reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK),
sys/dev/pci/if_bnx.c
3597
reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE);
sys/dev/pci/if_bnx.c
3598
if (reg & (BNX_PORT_FEATURE_ASF_ENABLED |
sys/dev/pci/if_bnxreg.h
676
#define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val)
sys/dev/pci/if_bnxreg.h
677
#define REG_WR16(sc, reg, val) bus_space_write_2(sc->bnx_btag, sc->bnx_bhandle, reg, val)
sys/dev/pci/if_bnxreg.h
678
#define REG_RD(sc, reg) bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg)
sys/dev/pci/if_bnxreg.h
682
#define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
sys/dev/pci/if_bnxreg.h
683
#define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
sys/dev/pci/if_bnxreg.h
684
#define PCI_SETBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x)))
sys/dev/pci/if_bnxreg.h
685
#define PCI_CLRBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x)))
sys/dev/pci/if_bwfm_pci.c
1823
bwfm_pci_buscore_read(struct bwfm_softc *bwfm, uint32_t reg)
sys/dev/pci/if_bwfm_pci.c
1828
page = reg & ~(BWFM_PCI_BAR0_REG_SIZE - 1);
sys/dev/pci/if_bwfm_pci.c
1829
offset = reg & (BWFM_PCI_BAR0_REG_SIZE - 1);
sys/dev/pci/if_bwfm_pci.c
1835
bwfm_pci_buscore_write(struct bwfm_softc *bwfm, uint32_t reg, uint32_t val)
sys/dev/pci/if_bwfm_pci.c
1840
page = reg & ~(BWFM_PCI_BAR0_REG_SIZE - 1);
sys/dev/pci/if_bwfm_pci.c
1841
offset = reg & (BWFM_PCI_BAR0_REG_SIZE - 1);
sys/dev/pci/if_bwfm_pci.c
1857
uint32_t reg;
sys/dev/pci/if_bwfm_pci.c
1861
reg = pci_conf_read(sc->sc_pc, sc->sc_tag,
sys/dev/pci/if_bwfm_pci.c
1864
reg & ~BWFM_PCI_CFGREG_LINK_STATUS_CTRL_ASPM_ENAB);
sys/dev/pci/if_bwfm_pci.c
1873
BWFM_PCI_CFGREG_LINK_STATUS_CTRL, reg);
sys/dev/pci/if_bwfm_pci.c
1894
reg = bus_space_read_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
sys/dev/pci/if_bwfm_pci.c
1897
DEVNAME(sc), cfg_offset[i], reg));
sys/dev/pci/if_bwfm_pci.c
1899
BWFM_PCI_PCIE2REG_CONFIGDATA, reg);
sys/dev/pci/if_bwfm_pci.c
1905
reg = bwfm_pci_intr_status(sc);
sys/dev/pci/if_bwfm_pci.c
1906
if (reg != 0xffffffff)
sys/dev/pci/if_bwfm_pci.c
1907
bwfm_pci_intr_ack(sc, reg);
sys/dev/pci/if_bwfm_pci.c
2267
uint32_t reg;
sys/dev/pci/if_bwfm_pci.c
2274
reg = bus_space_read_4(sc->sc_tcm_iot, sc->sc_tcm_ioh,
sys/dev/pci/if_bwfm_pci.c
2276
if (reg == 0)
sys/dev/pci/if_bwfm_pci.c
2299
uint32_t reg;
sys/dev/pci/if_bwfm_pci.c
2301
reg = bus_space_read_4(sc->sc_tcm_iot, sc->sc_tcm_ioh,
sys/dev/pci/if_bwfm_pci.c
2303
if (reg == 0)
sys/dev/pci/if_bwfm_pci.c
2309
if (reg & BWFM_PCI_D2H_DEV_D3_ACK) {
sys/dev/pci/if_bwfm_pci.c
2315
if (reg & ~BWFM_PCI_D2H_DEV_D3_ACK)
sys/dev/pci/if_bwfm_pci.c
2316
printf("%s: handle MB data 0x%08x\n", DEVNAME(sc), reg);
sys/dev/pci/if_bwfm_pci.c
441
uint32_t idx_offset, reg;
sys/dev/pci/if_bwfm_pci.c
463
reg = bus_space_read_4(sc->sc_pcie_iot, sc->sc_pcie_ioh,
sys/dev/pci/if_bwfm_pci.c
466
BWFM_PCI_PCIE2REG_CONFIGDATA, reg);
sys/dev/pci/if_bwi_pci.c
138
pcireg_t memtype, reg;
sys/dev/pci/if_bwi_pci.c
156
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
sys/dev/pci/if_bwi_pci.c
160
sc->sc_pci_subvid = PCI_VENDOR(reg);
sys/dev/pci/if_bwi_pci.c
161
sc->sc_pci_subdid = PCI_PRODUCT(reg);
sys/dev/pci/if_bwi_pci.c
234
bwi_pci_conf_write(void *self, uint32_t reg, uint32_t val)
sys/dev/pci/if_bwi_pci.c
238
pci_conf_write(psc->psc_pc, psc->psc_pcitag, reg, val);
sys/dev/pci/if_bwi_pci.c
242
bwi_pci_conf_read(void *self, uint32_t reg)
sys/dev/pci/if_bwi_pci.c
246
return (pci_conf_read(psc->psc_pc, psc->psc_pcitag, reg));
sys/dev/pci/if_cas.c
1430
cas_mii_readreg(struct device *self, int phy, int reg)
sys/dev/pci/if_cas.c
1440
printf("cas_mii_readreg: phy %d reg %d\n", phy, reg);
sys/dev/pci/if_cas.c
1444
v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) |
sys/dev/pci/if_cas.c
1460
cas_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/pci/if_cas.c
1471
phy, reg, val);
sys/dev/pci/if_cas.c
1477
(reg << CAS_MIF_REG_SHIFT) |
sys/dev/pci/if_cas.c
1542
cas_pcs_readreg(struct device *self, int phy, int reg)
sys/dev/pci/if_cas.c
1550
printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg);
sys/dev/pci/if_cas.c
1556
switch (reg) {
sys/dev/pci/if_cas.c
1558
reg = CAS_MII_CONTROL;
sys/dev/pci/if_cas.c
1561
reg = CAS_MII_STATUS;
sys/dev/pci/if_cas.c
1564
reg = CAS_MII_ANAR;
sys/dev/pci/if_cas.c
1567
reg = CAS_MII_ANLPAR;
sys/dev/pci/if_cas.c
1575
return bus_space_read_4(t, pcs, reg);
sys/dev/pci/if_cas.c
1579
cas_pcs_writereg(struct device *self, int phy, int reg, int val)
sys/dev/pci/if_cas.c
1589
phy, reg, val);
sys/dev/pci/if_cas.c
1595
if (reg == MII_ANAR)
sys/dev/pci/if_cas.c
1598
switch (reg) {
sys/dev/pci/if_cas.c
1601
reg = CAS_MII_CONTROL;
sys/dev/pci/if_cas.c
1604
reg = CAS_MII_STATUS;
sys/dev/pci/if_cas.c
1607
reg = CAS_MII_ANAR;
sys/dev/pci/if_cas.c
1610
reg = CAS_MII_ANLPAR;
sys/dev/pci/if_cas.c
1616
bus_space_write_4(t, pcs, reg, val);
sys/dev/pci/if_cas.c
1621
if (reg == CAS_MII_ANAR || reset)
sys/dev/pci/if_cas.c
658
u_int32_t reg;
sys/dev/pci/if_cas.c
661
reg = bus_space_read_4(sc->sc_memt, h, r);
sys/dev/pci/if_cas.c
662
if ((reg & clr) == 0 && (reg & set) == set)
sys/dev/pci/if_em.c
1649
u_int32_t reg;
sys/dev/pci/if_em.c
1660
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
sys/dev/pci/if_em.c
1661
sc->hw.revision_id = PCI_REVISION(reg);
sys/dev/pci/if_em.c
1663
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
sys/dev/pci/if_em.c
1664
sc->hw.subsystem_vendor_id = PCI_VENDOR(reg);
sys/dev/pci/if_em.c
1665
sc->hw.subsystem_id = PCI_PRODUCT(reg);
sys/dev/pci/if_em.c
1684
uint32_t reg;
sys/dev/pci/if_em.c
1693
reg = EM_READ_REG(&sc->hw, E1000_FEXTNVM7);
sys/dev/pci/if_em.c
1694
reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
sys/dev/pci/if_em.c
1695
EM_WRITE_REG(&sc->hw, E1000_FEXTNVM7, reg);
sys/dev/pci/if_em.c
1697
reg = EM_READ_REG(&sc->hw, E1000_FEXTNVM9);
sys/dev/pci/if_em.c
1698
reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
sys/dev/pci/if_em.c
1700
EM_WRITE_REG(&sc->hw, E1000_FEXTNVM9, reg);
sys/dev/pci/if_em.c
2939
uint32_t reg;
sys/dev/pci/if_em.c
2940
reg = E1000_READ_REG(&sc->hw, RXDCTL(que->me));
sys/dev/pci/if_em.c
2941
reg |= E1000_RXDCTL_QUEUE_ENABLE;
sys/dev/pci/if_em.c
2942
E1000_WRITE_REG(&sc->hw, RXDCTL(que->me), reg);
sys/dev/pci/if_em.c
3316
em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
sys/dev/pci/if_em.c
3321
val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3);
sys/dev/pci/if_em.c
3322
if (reg & 0x2) {
sys/dev/pci/if_em.c
3329
pci_conf_write(pa->pa_pc, pa->pa_tag, reg & ~0x3, val);
sys/dev/pci/if_em.c
3333
em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
sys/dev/pci/if_em.c
3338
val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3);
sys/dev/pci/if_em.c
3339
if (reg & 0x2)
sys/dev/pci/if_em.c
3368
em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value)
sys/dev/pci/if_em.c
3677
uint32_t reg;
sys/dev/pci/if_em.c
3803
if (c->reg == 0)
sys/dev/pci/if_em.c
3807
E1000_REG_TR(hw, c->reg)); /* wtf */
sys/dev/pci/if_em.c
562
uint32_t reg = EM_READ_REG(&sc->hw, E1000_STATUS);
sys/dev/pci/if_em.c
563
sc->hw.bus_func = (reg & E1000_STATUS_FUNC_MASK) >>
sys/dev/pci/if_em_hw.c
11561
uint16_t reg;
sys/dev/pci/if_em_hw.c
11565
®);
sys/dev/pci/if_em_hw.c
11570
reg & ~E1000_KMRNCTRLSTA_K1_ENABLE);
sys/dev/pci/if_em_hw.c
11580
reg);
sys/dev/pci/if_em_hw.c
11589
ret_val = em_read_phy_reg(hw, I217_INBAND_CTRL, ®);
sys/dev/pci/if_em_hw.c
11594
reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
sys/dev/pci/if_em_hw.c
11598
reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
sys/dev/pci/if_em_hw.c
11604
reg |= 50 <<
sys/dev/pci/if_em_hw.c
11611
ret_val = em_write_phy_reg(hw, I217_INBAND_CTRL, reg);
sys/dev/pci/if_em_hw.c
11666
uint32_t reg = 0;
sys/dev/pci/if_em_hw.c
11688
reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
sys/dev/pci/if_em_hw.c
11689
reg |= E1000_CTRL_FRCSPD;
sys/dev/pci/if_em_hw.c
11690
E1000_WRITE_REG(hw, CTRL, reg);
sys/dev/pci/if_em_hw.c
11899
em_translate_82542_register(uint32_t reg)
sys/dev/pci/if_em_hw.c
11907
switch (reg) {
sys/dev/pci/if_em_hw.c
11909
reg = 0x00040;
sys/dev/pci/if_em_hw.c
11912
reg = 0x00108;
sys/dev/pci/if_em_hw.c
11915
reg = 0x00110;
sys/dev/pci/if_em_hw.c
11918
reg = 0x00114;
sys/dev/pci/if_em_hw.c
11921
reg = 0x00118;
sys/dev/pci/if_em_hw.c
11924
reg = 0x00120;
sys/dev/pci/if_em_hw.c
11927
reg = 0x00128;
sys/dev/pci/if_em_hw.c
11930
reg = 0x00138;
sys/dev/pci/if_em_hw.c
11933
reg = 0x0013C;
sys/dev/pci/if_em_hw.c
11936
reg = 0x00140;
sys/dev/pci/if_em_hw.c
11939
reg = 0x00148;
sys/dev/pci/if_em_hw.c
11942
reg = 0x00150;
sys/dev/pci/if_em_hw.c
11945
reg = 0x00160;
sys/dev/pci/if_em_hw.c
11948
reg = 0x00168;
sys/dev/pci/if_em_hw.c
11951
reg = 0x00200;
sys/dev/pci/if_em_hw.c
11954
reg = 0x00420;
sys/dev/pci/if_em_hw.c
11957
reg = 0x00424;
sys/dev/pci/if_em_hw.c
11960
reg = 0x00428;
sys/dev/pci/if_em_hw.c
11963
reg = 0x00430;
sys/dev/pci/if_em_hw.c
11966
reg = 0x00438;
sys/dev/pci/if_em_hw.c
11969
reg = 0x00440;
sys/dev/pci/if_em_hw.c
11972
reg = 0x00600;
sys/dev/pci/if_em_hw.c
11975
reg = 0x08010;
sys/dev/pci/if_em_hw.c
11978
reg = 0x08018;
sys/dev/pci/if_em_hw.c
11984
return (reg);
sys/dev/pci/if_em_hw.c
2095
uint32_t reg;
sys/dev/pci/if_em_hw.c
2102
reg = E1000_READ_REG(hw, PCS_CFG0);
sys/dev/pci/if_em_hw.c
2103
reg |= E1000_PCS_CFG_PCS_EN;
sys/dev/pci/if_em_hw.c
2104
E1000_WRITE_REG(hw, PCS_CFG0, reg);
sys/dev/pci/if_em_hw.c
2107
reg = E1000_READ_REG(hw, CTRL_EXT);
sys/dev/pci/if_em_hw.c
2108
reg &= ~E1000_CTRL_EXT_SDP3_DATA;
sys/dev/pci/if_em_hw.c
2109
E1000_WRITE_REG(hw, CTRL_EXT, reg);
sys/dev/pci/if_em_hw.c
2128
uint32_t ctrl, ctrl_ext, reg;
sys/dev/pci/if_em_hw.c
2181
reg = E1000_READ_REG(hw, PCS_LCTL);
sys/dev/pci/if_em_hw.c
2182
reg |= E1000_PCS_LCTL_FORCE_FCTRL;
sys/dev/pci/if_em_hw.c
2183
reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
sys/dev/pci/if_em_hw.c
2184
reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
sys/dev/pci/if_em_hw.c
2186
E1000_WRITE_REG(hw, PCS_LCTL, reg);
sys/dev/pci/if_em_hw.c
2193
reg = E1000_READ_REG(hw, CONNSW);
sys/dev/pci/if_em_hw.c
2194
reg |= E1000_CONNSW_ENRGSRC;
sys/dev/pci/if_em_hw.c
2195
E1000_WRITE_REG(hw, CONNSW, reg);
sys/dev/pci/if_em_hw.c
4954
uint16_t reg = BM_PHY_REG_NUM(reg_addr);
sys/dev/pci/if_em_hw.c
4985
ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE, reg);
sys/dev/pci/if_em_hw.c
5071
uint16_t reg = BM_PHY_REG_NUM(reg_addr);
sys/dev/pci/if_em_hw.c
5102
((MAX_PHY_REG_ADDRESS & reg) == 0) &&
sys/dev/pci/if_em_hw.c
5119
ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg,
sys/dev/pci/if_em_hw.c
5122
ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg,
sys/dev/pci/if_em_hw.c
5521
uint32_t reg = 0;
sys/dev/pci/if_em_hw.c
5529
reg = E1000_READ_REG(hw, MDIC);
sys/dev/pci/if_em_hw.c
5530
ext_mdio = !!(reg & E1000_MDIC_DEST);
sys/dev/pci/if_em_hw.c
5535
reg = E1000_READ_REG(hw, MDICNFG);
sys/dev/pci/if_em_hw.c
5536
ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
sys/dev/pci/if_em_hw.c
5963
int32_t reg;
sys/dev/pci/if_em_hw.c
5996
reg = E1000_READ_REG(hw, PHY_CTRL);
sys/dev/pci/if_em_hw.c
5997
E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE
sys/dev/pci/if_em_hw.c
7054
uint32_t i, reg = 0;
sys/dev/pci/if_em_hw.c
7058
reg = E1000_READ_REG(hw, EERD);
sys/dev/pci/if_em_hw.c
7060
reg = E1000_READ_REG(hw, EEWR);
sys/dev/pci/if_em_hw.c
7062
if (reg & E1000_EEPROM_RW_REG_DONE) {
sys/dev/pci/if_em_hw.h
2877
#define GG82563_REG(page, reg) \
sys/dev/pci/if_em_hw.h
2878
(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
sys/dev/pci/if_em_hw.h
3431
#define PHY_REG(page, reg) \
sys/dev/pci/if_em_hw.h
3432
(((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
sys/dev/pci/if_em_hw.h
3797
#define E1000_INVM_DATA_REG(reg) (0x12120 + 4*(reg))
sys/dev/pci/if_em_hw.h
3822
#define BM_PHY_REG(page, reg) \
sys/dev/pci/if_em_hw.h
3823
(((reg) & MAX_PHY_REG_ADDRESS) |\
sys/dev/pci/if_em_hw.h
3825
(((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
sys/dev/pci/if_em_hw.h
413
int32_t em_read_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
sys/dev/pci/if_em_hw.h
416
int32_t em_write_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
sys/dev/pci/if_em_hw.h
434
void em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value);
sys/dev/pci/if_em_hw.h
435
void em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value);
sys/dev/pci/if_em_hw.h
436
int32_t em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value);
sys/dev/pci/if_em_hw.h
443
#define E1000_READ_REG_IO(a, reg) \
sys/dev/pci/if_em_hw.h
444
em_read_reg_io((a), E1000_##reg)
sys/dev/pci/if_em_hw.h
445
#define E1000_WRITE_REG_IO(a, reg, val) \
sys/dev/pci/if_em_hw.h
446
em_write_reg_io((a), E1000_##reg, val)
sys/dev/pci/if_em_osdep.h
100
reg : em_translate_82542_register(reg))
sys/dev/pci/if_em_osdep.h
104
#define E1000_READ_REG(hw, reg) \
sys/dev/pci/if_em_osdep.h
107
E1000_REG_TR(hw, E1000_##reg))
sys/dev/pci/if_em_osdep.h
109
#define E1000_WRITE_REG(hw, reg, value) \
sys/dev/pci/if_em_osdep.h
112
E1000_REG_TR(hw, E1000_##reg), \
sys/dev/pci/if_em_osdep.h
115
#define EM_READ_REG(hw, reg) \
sys/dev/pci/if_em_osdep.h
118
reg)
sys/dev/pci/if_em_osdep.h
120
#define EM_WRITE_REG(hw, reg, value) \
sys/dev/pci/if_em_osdep.h
123
reg, value)
sys/dev/pci/if_em_osdep.h
125
#define EM_READ_REG_ARRAY(hw, reg, index) \
sys/dev/pci/if_em_osdep.h
128
reg + ((index) << 2))
sys/dev/pci/if_em_osdep.h
130
#define EM_WRITE_REG_ARRAY(hw, reg, index, value) \
sys/dev/pci/if_em_osdep.h
133
reg + ((index) << 2), value)
sys/dev/pci/if_em_osdep.h
135
#define E1000_READ_REG_ARRAY(hw, reg, index) \
sys/dev/pci/if_em_osdep.h
138
E1000_REG_TR(hw, E1000_##reg) + ((index) << 2))
sys/dev/pci/if_em_osdep.h
140
#define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \
sys/dev/pci/if_em_osdep.h
143
E1000_REG_TR(hw, E1000_##reg) + ((index) << 2), \
sys/dev/pci/if_em_osdep.h
149
#define E1000_WRITE_REG_ARRAY_BYTE(hw, reg, index, value) \
sys/dev/pci/if_em_osdep.h
152
E1000_REG_TR(hw, E1000_##reg) + index, \
sys/dev/pci/if_em_osdep.h
155
#define E1000_WRITE_REG_ARRAY_WORD(hw, reg, index, value) \
sys/dev/pci/if_em_osdep.h
158
E1000_REG_TR(hw, E1000_##reg) + (index << 1), \
sys/dev/pci/if_em_osdep.h
161
#define E1000_READ_ICH_FLASH_REG(hw, reg) \
sys/dev/pci/if_em_osdep.h
164
((struct em_osdep *)(hw)->back)->em_flashoffset + reg)
sys/dev/pci/if_em_osdep.h
166
#define E1000_READ_ICH_FLASH_REG16(hw, reg) \
sys/dev/pci/if_em_osdep.h
169
((struct em_osdep *)(hw)->back)->em_flashoffset + reg)
sys/dev/pci/if_em_osdep.h
171
#define E1000_READ_ICH_FLASH_REG32(hw, reg) \
sys/dev/pci/if_em_osdep.h
174
((struct em_osdep *)(hw)->back)->em_flashoffset + reg)
sys/dev/pci/if_em_osdep.h
177
#define E1000_WRITE_ICH_FLASH_REG8(hw, reg, value) \
sys/dev/pci/if_em_osdep.h
180
((struct em_osdep *)(hw)->back)->em_flashoffset + reg, \
sys/dev/pci/if_em_osdep.h
183
#define E1000_WRITE_ICH_FLASH_REG16(hw, reg, value) \
sys/dev/pci/if_em_osdep.h
186
((struct em_osdep *)(hw)->back)->em_flashoffset + reg, \
sys/dev/pci/if_em_osdep.h
189
#define E1000_WRITE_ICH_FLASH_REG32(hw, reg, value) \
sys/dev/pci/if_em_osdep.h
192
((struct em_osdep *)(hw)->back)->em_flashoffset + reg, \
sys/dev/pci/if_em_osdep.h
98
#define E1000_REG_TR(hw, reg) \
sys/dev/pci/if_em_soc.c
110
data |= (reg << MDIO_COMMAND_PHY_REG_OFFSET);
sys/dev/pci/if_em_soc.c
128
DEVNAME(sc), phy, reg);
sys/dev/pci/if_em_soc.c
49
gcu_miibus_readreg(struct em_hw *hw, int phy, int reg)
sys/dev/pci/if_em_soc.c
62
data |= (reg << MDIO_COMMAND_PHY_REG_OFFSET);
sys/dev/pci/if_em_soc.c
80
DEVNAME(sc), phy, reg);
sys/dev/pci/if_em_soc.c
90
DEVNAME(sc), phy, reg);
sys/dev/pci/if_em_soc.c
97
gcu_miibus_writereg(struct em_hw *hw, int phy, int reg, int val)
sys/dev/pci/if_epic_pci.c
104
pcireg_t reg;
sys/dev/pci/if_epic_pci.c
107
reg = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
sys/dev/pci/if_epic_pci.c
110
if (esp->subsysid == reg)
sys/dev/pci/if_et.c
306
et_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_et.c
316
__SHIFTIN(reg, ET_MII_ADDR_REG);
sys/dev/pci/if_et.c
332
sc->sc_dev.dv_xname, phy, reg);
sys/dev/pci/if_et.c
349
et_miibus_writereg(struct device *dev, int phy, int reg, int val0)
sys/dev/pci/if_et.c
359
__SHIFTIN(reg, ET_MII_ADDR_REG);
sys/dev/pci/if_et.c
375
sc->sc_dev.dv_xname, phy, reg);
sys/dev/pci/if_et.c
376
et_miibus_readreg(dev, phy, reg);
sys/dev/pci/if_etreg.h
352
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_etreg.h
353
bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_etreg.h
354
#define CSR_READ_4(sc, reg) \
sys/dev/pci/if_etreg.h
355
bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
sys/dev/pci/if_iavf.c
1638
uint32_t reg;
sys/dev/pci/if_iavf.c
1656
reg = iavf_rd(sc, I40E_VFINT_DYN_CTL01);
sys/dev/pci/if_iavf.c
1657
reg |= I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK |
sys/dev/pci/if_iavf.c
1659
iavf_wr(sc, I40E_VFINT_DYN_CTL01, reg);
sys/dev/pci/if_iavf.c
1690
reg = iavf_rd(sc, I40E_VFINT_DYN_CTL01);
sys/dev/pci/if_iavf.c
1691
reg |= (IAVF_NOITR << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT);
sys/dev/pci/if_iavf.c
1692
iavf_wr(sc, I40E_VFINT_DYN_CTL01, reg);
sys/dev/pci/if_iavf.c
1735
uint32_t reg;
sys/dev/pci/if_iavf.c
1736
reg = iavf_rd(sc, I40E_VFGEN_RSTAT) &
sys/dev/pci/if_iavf.c
1738
if (reg == IAVF_VFR_VFACTIVE ||
sys/dev/pci/if_iavf.c
1739
reg == IAVF_VFR_COMPLETED)
sys/dev/pci/if_iavf.c
964
uint32_t reg;
sys/dev/pci/if_iavf.c
965
reg = iavf_rd(sc, I40E_VFGEN_RSTAT) &
sys/dev/pci/if_iavf.c
967
if (reg == IAVF_VFR_VFACTIVE ||
sys/dev/pci/if_iavf.c
968
reg == IAVF_VFR_COMPLETED)
sys/dev/pci/if_ice.c
1035
uint32_t cnt, reg = 0, grst_timeout, uld_mask, reset_wait_cnt;
sys/dev/pci/if_ice.c
1046
reg = ICE_READ(hw, GLGEN_RSTAT);
sys/dev/pci/if_ice.c
1047
if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
sys/dev/pci/if_ice.c
1071
reg = ICE_READ(hw, GLNVM_ULD) & uld_mask;
sys/dev/pci/if_ice.c
1072
if (reg == uld_mask) {
sys/dev/pci/if_ice.c
1081
"GLNVM_ULD = 0x%x\n", reg);
sys/dev/pci/if_ice.c
1097
uint32_t cnt, reg, reset_wait_cnt, cfg_lock_timeout;
sys/dev/pci/if_ice.c
11018
ice_is_rxq_ready(struct ice_hw *hw, int pf_q, uint32_t *reg)
sys/dev/pci/if_ice.c
11032
*reg = qrx_ctrl;
sys/dev/pci/if_ice.c
1114
reg = ICE_READ(hw, PFGEN_CTRL);
sys/dev/pci/if_ice.c
1116
ICE_WRITE(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
sys/dev/pci/if_ice.c
1126
reg = ICE_READ(hw, PFGEN_CTRL);
sys/dev/pci/if_ice.c
1127
if (!(reg & PFGEN_CTRL_PFSWR_M))
sys/dev/pci/if_ice.c
13345
uint32_t reg, val;
sys/dev/pci/if_ice.c
13350
reg = vsi->rx_qmap[rxq->me];
sys/dev/pci/if_ice.c
13351
val = ICE_READ(hw, QINT_RQCTL(reg));
sys/dev/pci/if_ice.c
13353
ICE_WRITE(hw, QINT_RQCTL(reg), val);
sys/dev/pci/if_ice.c
13400
uint32_t reg, val;
sys/dev/pci/if_ice.c
13405
reg = vsi->tx_qmap[txq->me];
sys/dev/pci/if_ice.c
13406
val = ICE_READ(hw, QINT_TQCTL(reg));
sys/dev/pci/if_ice.c
13408
ICE_WRITE(hw, QINT_TQCTL(reg), val);
sys/dev/pci/if_ice.c
14938
uint32_t reg = 0;
sys/dev/pci/if_ice.c
15059
reg = ICE_READ(hw, GLGEN_RSTAT);
sys/dev/pci/if_ice.c
15060
if (reg & GLGEN_RSTAT_DEVSTATE_M) {
sys/dev/pci/if_ice.c
196
#define ICE_READ(hw, reg) \
sys/dev/pci/if_ice.c
197
bus_space_read_4((hw)->hw_sc->sc_st, (hw)->hw_sc->sc_sh, (reg))
sys/dev/pci/if_ice.c
199
#define ICE_READ_8(hw, reg) \
sys/dev/pci/if_ice.c
200
bus_space_read_8((hw)->hw_sc->sc_st, (hw)->hw_sc->sc_sh, (reg))
sys/dev/pci/if_ice.c
202
#define ICE_WRITE(hw, reg, val) \
sys/dev/pci/if_ice.c
203
bus_space_write_4((hw)->hw_sc->sc_st, (hw)->hw_sc->sc_sh, (reg), (val))
sys/dev/pci/if_ice.c
205
#define ICE_WRITE_RAW(hw, reg, val) \
sys/dev/pci/if_ice.c
206
bus_space_write_raw_4((hw)->hw_sc->sc_st, (hw)->hw_sc->sc_sh, (reg), \
sys/dev/pci/if_ice.c
26736
uint32_t reg;
sys/dev/pci/if_ice.c
26741
reg = ICE_READ(hw, GL_MDET_TX_TCLAN);
sys/dev/pci/if_ice.c
26742
if (reg & GL_MDET_TX_TCLAN_VALID_M) {
sys/dev/pci/if_ice.c
26743
uint8_t pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
sys/dev/pci/if_ice.c
26745
uint16_t vf_num = (reg & GL_MDET_TX_TCLAN_VF_NUM_M) >>
sys/dev/pci/if_ice.c
26747
uint8_t event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
sys/dev/pci/if_ice.c
26749
uint16_t queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
sys/dev/pci/if_ice.c
26767
reg = ICE_READ(hw, GL_MDET_TX_PQM);
sys/dev/pci/if_ice.c
26768
if (reg & GL_MDET_TX_PQM_VALID_M) {
sys/dev/pci/if_ice.c
26769
uint8_t pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
sys/dev/pci/if_ice.c
26771
uint16_t vf_num = (reg & GL_MDET_TX_PQM_VF_NUM_M) >>
sys/dev/pci/if_ice.c
26773
uint8_t event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
sys/dev/pci/if_ice.c
26775
uint16_t queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
sys/dev/pci/if_ice.c
26792
reg = ICE_READ(hw, GL_MDET_RX);
sys/dev/pci/if_ice.c
26793
if (reg & GL_MDET_RX_VALID_M) {
sys/dev/pci/if_ice.c
26794
uint8_t pf_num = (reg & GL_MDET_RX_PF_NUM_M) >>
sys/dev/pci/if_ice.c
26796
uint16_t vf_num = (reg & GL_MDET_RX_VF_NUM_M) >>
sys/dev/pci/if_ice.c
26798
uint8_t event = (reg & GL_MDET_RX_MAL_TYPE_M) >>
sys/dev/pci/if_ice.c
26800
uint16_t queue = (reg & GL_MDET_RX_QNUM_M) >>
sys/dev/pci/if_ice.c
26820
reg = ICE_READ(hw, PF_MDET_TX_TCLAN);
sys/dev/pci/if_ice.c
26821
if (reg & PF_MDET_TX_TCLAN_VALID_M) {
sys/dev/pci/if_ice.c
26829
reg = ICE_READ(hw, PF_MDET_TX_PQM);
sys/dev/pci/if_ice.c
26830
if (reg & PF_MDET_TX_PQM_VALID_M) {
sys/dev/pci/if_ice.c
26838
reg = ICE_READ(hw, PF_MDET_RX);
sys/dev/pci/if_ice.c
26839
if (reg & PF_MDET_RX_VALID_M) {
sys/dev/pci/if_ice.c
28616
ice_stat_update40(struct ice_hw *hw, uint32_t reg, bool prev_stat_loaded,
sys/dev/pci/if_ice.c
28619
uint64_t new_data = ICE_READ_8(hw, reg) & (BIT_ULL(40) - 1);
sys/dev/pci/if_ice.c
28655
ice_stat_update32(struct ice_hw *hw, uint32_t reg, bool prev_stat_loaded,
sys/dev/pci/if_ice.c
28660
new_data = ICE_READ(hw, reg);
sys/dev/pci/if_ice.c
30011
uint32_t reg;
sys/dev/pci/if_ice.c
30013
reg = ICE_READ(hw, PRTDCB_GENS);
sys/dev/pci/if_ice.c
30014
return (uint8_t)((reg & PRTDCB_GENS_DCBX_STATUS_M) >>
sys/dev/pci/if_ice.c
3326
ice_aq_fwlog_register(struct ice_hw *hw, bool reg)
sys/dev/pci/if_ice.c
3332
if (reg)
sys/dev/pci/if_igc.c
2578
uint32_t reg;
sys/dev/pci/if_igc.c
2718
if (c->reg == 0)
sys/dev/pci/if_igc.c
2721
kstat_kv_u64(&kvs[i]) += IGC_READ_REG(hw, c->reg);
sys/dev/pci/if_igc.c
573
uint32_t dmac, reg = ~IGC_DMACR_DMAC_EN;
sys/dev/pci/if_igc.c
580
IGC_WRITE_REG(hw, IGC_DMACR, reg);
sys/dev/pci/if_igc.c
591
reg = IGC_READ_REG(hw, IGC_FCRTC);
sys/dev/pci/if_igc.c
592
reg &= ~IGC_FCRTC_RTH_COAL_MASK;
sys/dev/pci/if_igc.c
593
reg |= ((hwm << IGC_FCRTC_RTH_COAL_SHIFT)
sys/dev/pci/if_igc.c
595
IGC_WRITE_REG(hw, IGC_FCRTC, reg);
sys/dev/pci/if_igc.c
600
reg = IGC_READ_REG(hw, IGC_DMACR);
sys/dev/pci/if_igc.c
601
reg &= ~IGC_DMACR_DMACTHR_MASK;
sys/dev/pci/if_igc.c
602
reg |= ((dmac << IGC_DMACR_DMACTHR_SHIFT)
sys/dev/pci/if_igc.c
606
reg |= (IGC_DMACR_DMAC_EN | IGC_DMACR_DMAC_LX_MASK);
sys/dev/pci/if_igc.c
617
reg |= ((sc->dmac * 5) >> 6);
sys/dev/pci/if_igc.c
619
reg |= (sc->dmac >> 5);
sys/dev/pci/if_igc.c
621
IGC_WRITE_REG(hw, IGC_DMACR, reg);
sys/dev/pci/if_igc.c
626
reg = IGC_READ_REG(hw, IGC_DMCTLX);
sys/dev/pci/if_igc.c
627
reg |= IGC_DMCTLX_DCFLUSH_DIS;
sys/dev/pci/if_igc.c
636
reg |= 0xA;
sys/dev/pci/if_igc.c
638
reg |= 0x4;
sys/dev/pci/if_igc.c
640
IGC_WRITE_REG(hw, IGC_DMCTLX, reg);
sys/dev/pci/if_igc.c
647
reg = IGC_READ_REG(hw, IGC_PCIEMISC);
sys/dev/pci/if_igc.c
648
reg &= ~IGC_PCIEMISC_LX_DECISION;
sys/dev/pci/if_igc.c
649
IGC_WRITE_REG(hw, IGC_PCIEMISC, reg);
sys/dev/pci/if_igc.h
335
#define IGC_READ_REG(a, reg) \
sys/dev/pci/if_igc.h
337
((struct igc_osdep *)(a)->back)->os_memh, reg)
sys/dev/pci/if_igc.h
338
#define IGC_WRITE_REG(a, reg, value) \
sys/dev/pci/if_igc.h
340
((struct igc_osdep *)(a)->back)->os_memh, reg, value)
sys/dev/pci/if_igc.h
341
#define IGC_READ_REG_ARRAY(a, reg, off) \
sys/dev/pci/if_igc.h
343
((struct igc_osdep *)(a)->back)->os_memh, (reg + ((off) << 2)))
sys/dev/pci/if_igc.h
344
#define IGC_WRITE_REG_ARRAY(a, reg, off, value) \
sys/dev/pci/if_igc.h
347
(reg + ((off) << 2)),value)
sys/dev/pci/if_ipwreg.h
282
#define CSR_READ_1(sc, reg) \
sys/dev/pci/if_ipwreg.h
283
bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
sys/dev/pci/if_ipwreg.h
285
#define CSR_READ_2(sc, reg) \
sys/dev/pci/if_ipwreg.h
286
bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
sys/dev/pci/if_ipwreg.h
288
#define CSR_READ_4(sc, reg) \
sys/dev/pci/if_ipwreg.h
289
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
sys/dev/pci/if_ipwreg.h
291
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_ipwreg.h
292
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_ipwreg.h
294
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_ipwreg.h
295
bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_ipwreg.h
297
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_ipwreg.h
298
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_ipwreg.h
300
#define CSR_WRITE_MULTI_1(sc, reg, buf, len) \
sys/dev/pci/if_ipwreg.h
301
bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \
sys/dev/pci/if_iwi.c
2247
CSR_WRITE_4(sc, data->reg, data->map->dm_segs[0].ds_addr);
sys/dev/pci/if_iwi.c
606
data->reg = IWI_CSR_RX_BASE + i * 4;
sys/dev/pci/if_iwi.c
923
CSR_WRITE_4(sc, data->reg, data->map->dm_segs[0].ds_addr);
sys/dev/pci/if_iwi.c
930
CSR_WRITE_4(sc, data->reg, data->map->dm_segs[0].ds_addr);
sys/dev/pci/if_iwireg.h
457
#define CSR_READ_1(sc, reg) \
sys/dev/pci/if_iwireg.h
458
bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
sys/dev/pci/if_iwireg.h
460
#define CSR_READ_2(sc, reg) \
sys/dev/pci/if_iwireg.h
461
bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
sys/dev/pci/if_iwireg.h
463
#define CSR_READ_4(sc, reg) \
sys/dev/pci/if_iwireg.h
464
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
sys/dev/pci/if_iwireg.h
470
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_iwireg.h
471
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_iwireg.h
473
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_iwireg.h
474
bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_iwireg.h
476
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_iwireg.h
477
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_iwivar.h
79
uint32_t reg;
sys/dev/pci/if_iwm.c
1127
iwm_poll_bit(struct iwm_softc *sc, int reg, uint32_t bits, uint32_t mask,
sys/dev/pci/if_iwm.c
1131
if ((IWM_READ(sc, reg) & mask) == (bits & mask)) {
sys/dev/pci/if_iwm.c
11714
pcireg_t reg, memtype;
sys/dev/pci/if_iwm.c
11739
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);
sys/dev/pci/if_iwm.c
11740
pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);
sys/dev/pci/if_iwm.c
11758
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
sys/dev/pci/if_iwm.c
11760
if (reg & PCI_COMMAND_INTERRUPT_DISABLE)
sys/dev/pci/if_iwm.c
11761
reg &= ~PCI_COMMAND_INTERRUPT_DISABLE;
sys/dev/pci/if_iwm.c
11763
PCI_COMMAND_STATUS_REG, reg);
sys/dev/pci/if_iwm.c
1188
iwm_set_bits_mask_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits,
sys/dev/pci/if_iwm.c
1194
val = iwm_read_prph(sc, reg) & mask;
sys/dev/pci/if_iwm.c
1196
iwm_write_prph(sc, reg, val);
sys/dev/pci/if_iwm.c
1204
iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)
sys/dev/pci/if_iwm.c
1206
return iwm_set_bits_mask_prph(sc, reg, bits, ~0);
sys/dev/pci/if_iwm.c
1210
iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)
sys/dev/pci/if_iwm.c
1212
return iwm_set_bits_mask_prph(sc, reg, 0, ~bits);
sys/dev/pci/if_iwm.c
12156
pcireg_t reg;
sys/dev/pci/if_iwm.c
12162
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);
sys/dev/pci/if_iwm.c
12163
pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);
sys/dev/pci/if_iwm.c
12167
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
sys/dev/pci/if_iwm.c
12169
if (reg & PCI_COMMAND_INTERRUPT_DISABLE)
sys/dev/pci/if_iwm.c
12170
reg &= ~PCI_COMMAND_INTERRUPT_DISABLE;
sys/dev/pci/if_iwm.c
12172
PCI_COMMAND_STATUS_REG, reg);
sys/dev/pci/if_iwmreg.h
6821
#define IWM_READ(sc, reg) \
sys/dev/pci/if_iwmreg.h
6822
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
sys/dev/pci/if_iwmreg.h
6824
#define IWM_WRITE(sc, reg, val) \
sys/dev/pci/if_iwmreg.h
6825
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_iwmreg.h
6827
#define IWM_WRITE_1(sc, reg, val) \
sys/dev/pci/if_iwmreg.h
6828
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_iwmreg.h
6830
#define IWM_SETBITS(sc, reg, mask) \
sys/dev/pci/if_iwmreg.h
6831
IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask))
sys/dev/pci/if_iwmreg.h
6833
#define IWM_CLRBITS(sc, reg, mask) \
sys/dev/pci/if_iwmreg.h
6834
IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))
sys/dev/pci/if_iwn.c
337
pcireg_t memtype, reg;
sys/dev/pci/if_iwn.c
356
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);
sys/dev/pci/if_iwn.c
357
if (reg & 0xff00)
sys/dev/pci/if_iwn.c
358
pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);
sys/dev/pci/if_iwn.c
361
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);
sys/dev/pci/if_iwn.c
362
if (reg & PCI_COMMAND_INTERRUPT_DISABLE) {
sys/dev/pci/if_iwn.c
364
reg &= ~PCI_COMMAND_INTERRUPT_DISABLE;
sys/dev/pci/if_iwn.c
366
PCI_COMMAND_STATUS_REG, reg);
sys/dev/pci/if_iwn.c
4779
pcireg_t reg;
sys/dev/pci/if_iwn.c
4796
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
sys/dev/pci/if_iwn.c
4798
if (!(reg & PCI_PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */
sys/dev/pci/if_iwn.c
6815
pcireg_t reg;
sys/dev/pci/if_iwn.c
6830
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
sys/dev/pci/if_iwn.c
6833
if (reg & PCI_PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */
sys/dev/pci/if_iwn.c
799
pcireg_t reg;
sys/dev/pci/if_iwn.c
802
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);
sys/dev/pci/if_iwn.c
803
if (reg & 0xff00)
sys/dev/pci/if_iwn.c
804
pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);
sys/dev/pci/if_iwnreg.h
2096
#define IWN_READ(sc, reg) \
sys/dev/pci/if_iwnreg.h
2097
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
sys/dev/pci/if_iwnreg.h
2099
#define IWN_WRITE(sc, reg, val) \
sys/dev/pci/if_iwnreg.h
2100
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_iwnreg.h
2102
#define IWN_WRITE_1(sc, reg, val) \
sys/dev/pci/if_iwnreg.h
2103
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_iwnreg.h
2105
#define IWN_SETBITS(sc, reg, mask) \
sys/dev/pci/if_iwnreg.h
2106
IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask))
sys/dev/pci/if_iwnreg.h
2108
#define IWN_CLRBITS(sc, reg, mask) \
sys/dev/pci/if_iwnreg.h
2109
IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask))
sys/dev/pci/if_iwx.c
12174
pcireg_t reg, memtype;
sys/dev/pci/if_iwx.c
12202
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);
sys/dev/pci/if_iwx.c
12203
pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);
sys/dev/pci/if_iwx.c
12221
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
sys/dev/pci/if_iwx.c
12223
if (reg & PCI_COMMAND_INTERRUPT_DISABLE)
sys/dev/pci/if_iwx.c
12224
reg &= ~PCI_COMMAND_INTERRUPT_DISABLE;
sys/dev/pci/if_iwx.c
12226
PCI_COMMAND_STATUS_REG, reg);
sys/dev/pci/if_iwx.c
12663
pcireg_t reg;
sys/dev/pci/if_iwx.c
12669
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);
sys/dev/pci/if_iwx.c
12670
pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);
sys/dev/pci/if_iwx.c
12674
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
sys/dev/pci/if_iwx.c
12676
if (reg & PCI_COMMAND_INTERRUPT_DISABLE)
sys/dev/pci/if_iwx.c
12677
reg &= ~PCI_COMMAND_INTERRUPT_DISABLE;
sys/dev/pci/if_iwx.c
12679
PCI_COMMAND_STATUS_REG, reg);
sys/dev/pci/if_iwx.c
1766
iwx_poll_bit(struct iwx_softc *sc, int reg, uint32_t bits, uint32_t mask,
sys/dev/pci/if_iwx.c
1770
if ((IWX_READ(sc, reg) & mask) == (bits & mask)) {
sys/dev/pci/if_iwx.c
1841
iwx_set_bits_mask_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits,
sys/dev/pci/if_iwx.c
1847
val = iwx_read_prph(sc, reg) & mask;
sys/dev/pci/if_iwx.c
1849
iwx_write_prph(sc, reg, val);
sys/dev/pci/if_iwx.c
1857
iwx_set_bits_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits)
sys/dev/pci/if_iwx.c
1859
return iwx_set_bits_mask_prph(sc, reg, bits, ~0);
sys/dev/pci/if_iwx.c
1863
iwx_clear_bits_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits)
sys/dev/pci/if_iwx.c
1865
return iwx_set_bits_mask_prph(sc, reg, 0, ~bits);
sys/dev/pci/if_iwxreg.h
8936
#define IWX_READ(sc, reg) \
sys/dev/pci/if_iwxreg.h
8937
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
sys/dev/pci/if_iwxreg.h
8939
#define IWX_WRITE(sc, reg, val) \
sys/dev/pci/if_iwxreg.h
8940
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_iwxreg.h
8942
#define IWX_WRITE_1(sc, reg, val) \
sys/dev/pci/if_iwxreg.h
8943
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_iwxreg.h
8945
#define IWX_SETBITS(sc, reg, mask) \
sys/dev/pci/if_iwxreg.h
8946
IWX_WRITE(sc, reg, IWX_READ(sc, reg) | (mask))
sys/dev/pci/if_iwxreg.h
8948
#define IWX_CLRBITS(sc, reg, mask) \
sys/dev/pci/if_iwxreg.h
8949
IWX_WRITE(sc, reg, IWX_READ(sc, reg) & ~(mask))
sys/dev/pci/if_ix.c
1702
uint32_t reg;
sys/dev/pci/if_ix.c
1708
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
sys/dev/pci/if_ix.c
1709
sc->hw.revision_id = PCI_REVISION(reg);
sys/dev/pci/if_ix.c
1711
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
sys/dev/pci/if_ix.c
1712
sc->hw.subsystem_vendor_id = PCI_VENDOR(reg);
sys/dev/pci/if_ix.c
1713
sc->hw.subsystem_device_id = PCI_PRODUCT(reg);
sys/dev/pci/if_ix.c
3513
ixgbe_read_pci_cfg(struct ixgbe_hw *hw, uint32_t reg)
sys/dev/pci/if_ix.c
3519
if (reg & 0x2) {
sys/dev/pci/if_ix.c
3521
reg &= ~0x2;
sys/dev/pci/if_ix.c
3524
value = pci_conf_read(pa->pa_pc, pa->pa_tag, reg);
sys/dev/pci/if_ix.c
3533
ixgbe_write_pci_cfg(struct ixgbe_hw *hw, uint32_t reg, uint16_t value)
sys/dev/pci/if_ix.c
3540
if (reg & 0x2) {
sys/dev/pci/if_ix.c
3542
reg &= ~0x2;
sys/dev/pci/if_ix.c
3545
rv = pci_conf_read(pa->pa_pc, pa->pa_tag, reg);
sys/dev/pci/if_ix.c
3550
pci_conf_write(pa->pa_pc, pa->pa_tag, reg, rv);
sys/dev/pci/if_ix.c
3741
uint32_t reg;
sys/dev/pci/if_ix.c
3971
uint32_t reg = ixc->reg;
sys/dev/pci/if_ix.c
3974
if (reg == 0)
sys/dev/pci/if_ix.c
3979
v = IXGBE_READ_REG(hw, reg + 4);
sys/dev/pci/if_ix.c
3981
v = ix_read36(hw, reg, reg + 4);
sys/dev/pci/if_ix.c
3983
v = IXGBE_READ_REG(hw, reg);
sys/dev/pci/if_ixgb.c
868
u_int32_t reg;
sys/dev/pci/if_ixgb.c
879
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
sys/dev/pci/if_ixgb.c
880
sc->hw.revision_id = PCI_REVISION(reg);
sys/dev/pci/if_ixgb.c
882
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
sys/dev/pci/if_ixgb.c
883
sc->hw.subsystem_vendor_id = PCI_VENDOR(reg);
sys/dev/pci/if_ixgb.c
884
sc->hw.subsystem_id = PCI_PRODUCT(reg);
sys/dev/pci/if_ixgb_osdep.h
78
#define IXGB_READ_REG(a, reg) \
sys/dev/pci/if_ixgb_osdep.h
81
IXGB_##reg)
sys/dev/pci/if_ixgb_osdep.h
83
#define IXGB_WRITE_REG(a, reg, value) \
sys/dev/pci/if_ixgb_osdep.h
86
IXGB_##reg, value)
sys/dev/pci/if_ixgb_osdep.h
88
#define IXGB_READ_REG_ARRAY(a, reg, offset) \
sys/dev/pci/if_ixgb_osdep.h
91
(IXGB_##reg + ((offset) << 2)))
sys/dev/pci/if_ixgb_osdep.h
93
#define IXGB_WRITE_REG_ARRAY(a, reg, offset, value) \
sys/dev/pci/if_ixgb_osdep.h
96
(IXGB_##reg + ((offset) << 2)), value)
sys/dev/pci/if_ixl.c
2239
uint32_t reg;
sys/dev/pci/if_ixl.c
2294
reg = ixl_rd(sc, I40E_QRX_ENA(i));
sys/dev/pci/if_ixl.c
2295
SET(reg, I40E_QRX_ENA_QENA_REQ_MASK);
sys/dev/pci/if_ixl.c
2296
ixl_wr(sc, I40E_QRX_ENA(i), reg);
sys/dev/pci/if_ixl.c
2298
reg = ixl_rd(sc, I40E_QTX_ENA(i));
sys/dev/pci/if_ixl.c
2299
SET(reg, I40E_QTX_ENA_QENA_REQ_MASK);
sys/dev/pci/if_ixl.c
2300
ixl_wr(sc, I40E_QTX_ENA(i), reg);
sys/dev/pci/if_ixl.c
2466
uint32_t reg;
sys/dev/pci/if_ixl.c
2478
reg = ixl_rd(sc, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE));
sys/dev/pci/if_ixl.c
2479
CLR(reg, I40E_QINT_RQCTL_CAUSE_ENA_MASK);
sys/dev/pci/if_ixl.c
2480
ixl_wr(sc, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), reg);
sys/dev/pci/if_ixl.c
2482
reg = ixl_rd(sc, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE));
sys/dev/pci/if_ixl.c
2483
CLR(reg, I40E_QINT_TQCTL_CAUSE_ENA_MASK);
sys/dev/pci/if_ixl.c
2484
ixl_wr(sc, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), reg);
sys/dev/pci/if_ixl.c
2510
reg = ixl_rd(sc, I40E_QTX_ENA(i));
sys/dev/pci/if_ixl.c
2511
CLR(reg, I40E_QTX_ENA_QENA_REQ_MASK);
sys/dev/pci/if_ixl.c
2512
ixl_wr(sc, I40E_QTX_ENA(i), reg);
sys/dev/pci/if_ixl.c
2514
reg = ixl_rd(sc, I40E_QRX_ENA(i));
sys/dev/pci/if_ixl.c
2515
CLR(reg, I40E_QRX_ENA_QENA_REQ_MASK);
sys/dev/pci/if_ixl.c
2516
ixl_wr(sc, I40E_QRX_ENA(i), reg);
sys/dev/pci/if_ixl.c
2624
bus_size_t reg;
sys/dev/pci/if_ixl.c
2628
reg = I40E_GLLAN_TXPRE_QDIS(qid / 128);
sys/dev/pci/if_ixl.c
2631
r = ixl_rd(sc, reg);
sys/dev/pci/if_ixl.c
2636
ixl_wr(sc, reg, r);
sys/dev/pci/if_ixl.c
2702
uint32_t reg;
sys/dev/pci/if_ixl.c
2706
reg = ixl_rd(sc, ena);
sys/dev/pci/if_ixl.c
2707
if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK))
sys/dev/pci/if_ixl.c
2720
uint32_t reg;
sys/dev/pci/if_ixl.c
2724
reg = ixl_rd(sc, ena);
sys/dev/pci/if_ixl.c
2725
if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK) == 0)
sys/dev/pci/if_ixl.c
3123
uint32_t reg;
sys/dev/pci/if_ixl.c
3127
reg = ixl_rd(sc, ena);
sys/dev/pci/if_ixl.c
3128
if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK))
sys/dev/pci/if_ixl.c
3141
uint32_t reg;
sys/dev/pci/if_ixl.c
3145
reg = ixl_rd(sc, ena);
sys/dev/pci/if_ixl.c
3146
if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK) == 0)
sys/dev/pci/if_ixl.c
4286
ixl_sff_get_byte(struct ixl_softc *sc, uint8_t dev, uint32_t reg, uint8_t *p)
sys/dev/pci/if_ixl.c
4298
htolem32(¶m->reg, reg);
sys/dev/pci/if_ixl.c
4305
dev, reg, lemtoh16(&iaq->iaq_retval));
sys/dev/pci/if_ixl.c
4327
ixl_sff_set_byte(struct ixl_softc *sc, uint8_t dev, uint32_t reg, uint8_t v)
sys/dev/pci/if_ixl.c
4339
htolem32(¶m->reg, reg);
sys/dev/pci/if_ixl.c
4347
dev, reg, v, lemtoh16(&iaq->iaq_retval));
sys/dev/pci/if_ixl.c
5013
uint32_t reg = 0;
sys/dev/pci/if_ixl.c
5027
reg = ixl_rd(sc, I40E_GLGEN_RSTAT);
sys/dev/pci/if_ixl.c
5028
if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
sys/dev/pci/if_ixl.c
5032
if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
sys/dev/pci/if_ixl.c
5039
reg = ixl_rd(sc, I40E_GLNVM_ULD);
sys/dev/pci/if_ixl.c
5040
reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
sys/dev/pci/if_ixl.c
5042
if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
sys/dev/pci/if_ixl.c
5048
if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
sys/dev/pci/if_ixl.c
5051
"(I40E_GLNVM_ULD = 0x%x)\n", reg);
sys/dev/pci/if_ixl.c
5060
reg = ixl_rd(sc, I40E_PFGEN_CTRL);
sys/dev/pci/if_ixl.c
5061
ixl_wr(sc, I40E_PFGEN_CTRL, reg | I40E_PFGEN_CTRL_PFSWR_MASK);
sys/dev/pci/if_ixl.c
5063
reg = ixl_rd(sc, I40E_PFGEN_CTRL);
sys/dev/pci/if_ixl.c
5064
if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
sys/dev/pci/if_ixl.c
5068
if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
sys/dev/pci/if_ixl.c
5070
"(I40E_PFGEN_CTRL= 0x%x)\n", reg);
sys/dev/pci/if_ixl.c
639
uint32_t reg;
sys/dev/pci/if_ixv.c
1000
reg &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
sys/dev/pci/if_ixv.c
1001
reg &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
sys/dev/pci/if_ixv.c
1002
reg |= bufsz;
sys/dev/pci/if_ixv.c
1003
reg |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
sys/dev/pci/if_ixv.c
1004
IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), reg);
sys/dev/pci/if_ixv.c
1262
pcireg_t reg;
sys/dev/pci/if_ixv.c
1312
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, off);
sys/dev/pci/if_ixv.c
1313
pci_conf_write(pa->pa_pc, pa->pa_tag, off, reg | PCI_MSIX_MC_MSIXE);
sys/dev/pci/if_ixv.c
1347
uint32_t reg;
sys/dev/pci/if_ixv.c
1518
uint32_t reg = ixc->reg;
sys/dev/pci/if_ixv.c
1521
if (reg == 0)
sys/dev/pci/if_ixv.c
1525
v = ixv_read36(hw, reg, reg + 4);
sys/dev/pci/if_ixv.c
1527
v = IXGBE_READ_REG(hw, reg);
sys/dev/pci/if_ixv.c
169
uint32_t reg;
sys/dev/pci/if_ixv.c
175
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
sys/dev/pci/if_ixv.c
176
sc->hw.revision_id = PCI_REVISION(reg);
sys/dev/pci/if_ixv.c
178
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
sys/dev/pci/if_ixv.c
179
sc->hw.subsystem_vendor_id = PCI_VENDOR(reg);
sys/dev/pci/if_ixv.c
180
sc->hw.subsystem_device_id = PCI_PRODUCT(reg);
sys/dev/pci/if_ixv.c
947
uint32_t reg, rxdctl, bufsz, psrtype;
sys/dev/pci/if_ixv.c
999
reg = IXGBE_READ_REG(hw, IXGBE_VFSRRCTL(i));
sys/dev/pci/if_jme.c
140
jme_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_jme.c
151
SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
sys/dev/pci/if_jme.c
160
sc->sc_dev.dv_xname, phy, reg);
sys/dev/pci/if_jme.c
171
jme_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_jme.c
1788
uint32_t reg;
sys/dev/pci/if_jme.c
182
SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
sys/dev/pci/if_jme.c
1843
reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
sys/dev/pci/if_jme.c
1844
reg |= TXMAC_THRESH_1_PKT;
sys/dev/pci/if_jme.c
1845
reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
sys/dev/pci/if_jme.c
1846
CSR_WRITE_4(sc, JME_TXMAC, reg);
sys/dev/pci/if_jme.c
1906
reg = CSR_READ_4(sc, JME_PMCS);
sys/dev/pci/if_jme.c
1907
reg &= ~PMCS_WOL_ENB_MASK;
sys/dev/pci/if_jme.c
1908
CSR_WRITE_4(sc, JME_PMCS, reg);
sys/dev/pci/if_jme.c
191
sc->sc_dev.dv_xname, phy, reg);
sys/dev/pci/if_jme.c
1915
reg = CSR_READ_4(sc, JME_RXMAC);
sys/dev/pci/if_jme.c
1916
reg |= RXMAC_PAD_10BYTES;
sys/dev/pci/if_jme.c
1917
reg |= RXMAC_CSUM_ENB;
sys/dev/pci/if_jme.c
1918
CSR_WRITE_4(sc, JME_RXMAC, reg);
sys/dev/pci/if_jme.c
1921
reg = CSR_READ_4(sc, JME_GPREG0);
sys/dev/pci/if_jme.c
1922
reg &= ~GPREG0_PCC_UNIT_MASK;
sys/dev/pci/if_jme.c
1924
reg |= GPREG0_PCC_UNIT_US;
sys/dev/pci/if_jme.c
1932
reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
sys/dev/pci/if_jme.c
1937
reg &= ~GPREG0_POST_DW0_ENB;
sys/dev/pci/if_jme.c
1939
reg &= ~GPREG0_PME_ENB;
sys/dev/pci/if_jme.c
1941
reg &= ~GPREG0_PHY_ADDR_MASK;
sys/dev/pci/if_jme.c
1942
reg |= sc->jme_phyaddr;
sys/dev/pci/if_jme.c
1943
CSR_WRITE_4(sc, JME_GPREG0, reg);
sys/dev/pci/if_jme.c
1947
reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
sys/dev/pci/if_jme.c
1950
reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
sys/dev/pci/if_jme.c
1952
reg |= PCCTX_COAL_TXQ0;
sys/dev/pci/if_jme.c
1953
CSR_WRITE_4(sc, JME_PCCTX, reg);
sys/dev/pci/if_jme.c
1957
reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
sys/dev/pci/if_jme.c
1960
reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
sys/dev/pci/if_jme.c
1962
CSR_WRITE_4(sc, JME_PCCRX0, reg);
sys/dev/pci/if_jme.c
2076
uint32_t reg;
sys/dev/pci/if_jme.c
2079
reg = CSR_READ_4(sc, JME_TXCSR);
sys/dev/pci/if_jme.c
2080
if ((reg & TXCSR_TX_ENB) == 0)
sys/dev/pci/if_jme.c
2082
reg &= ~TXCSR_TX_ENB;
sys/dev/pci/if_jme.c
2083
CSR_WRITE_4(sc, JME_TXCSR, reg);
sys/dev/pci/if_jme.c
2097
uint32_t reg;
sys/dev/pci/if_jme.c
2100
reg = CSR_READ_4(sc, JME_RXCSR);
sys/dev/pci/if_jme.c
2101
if ((reg & RXCSR_RX_ENB) == 0)
sys/dev/pci/if_jme.c
2103
reg &= ~RXCSR_RX_ENB;
sys/dev/pci/if_jme.c
2104
CSR_WRITE_4(sc, JME_RXCSR, reg);
sys/dev/pci/if_jme.c
2239
uint32_t reg;
sys/dev/pci/if_jme.c
2241
reg = CSR_READ_4(sc, JME_RXMAC);
sys/dev/pci/if_jme.c
2242
reg &= ~RXMAC_VLAN_ENB;
sys/dev/pci/if_jme.c
2244
reg |= RXMAC_VLAN_ENB;
sys/dev/pci/if_jme.c
2245
CSR_WRITE_4(sc, JME_RXMAC, reg);
sys/dev/pci/if_jme.c
363
uint32_t reg;
sys/dev/pci/if_jme.c
368
reg = CSR_READ_4(sc, JME_SMBCSR);
sys/dev/pci/if_jme.c
369
if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
sys/dev/pci/if_jme.c
379
reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
sys/dev/pci/if_jme.c
380
CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
sys/dev/pci/if_jme.c
383
reg = CSR_READ_4(sc, JME_SMBINTF);
sys/dev/pci/if_jme.c
384
if ((reg & SMBINTF_CMD_TRIGGER) == 0)
sys/dev/pci/if_jme.c
393
reg = CSR_READ_4(sc, JME_SMBINTF);
sys/dev/pci/if_jme.c
394
*val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
sys/dev/pci/if_jme.c
402
uint8_t fup, reg, val;
sys/dev/pci/if_jme.c
419
if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
sys/dev/pci/if_jme.c
421
if (reg >= JME_PAR0 &&
sys/dev/pci/if_jme.c
422
reg < JME_PAR0 + ETHER_ADDR_LEN) {
sys/dev/pci/if_jme.c
426
eaddr[reg - JME_PAR0] = val;
sys/dev/pci/if_jme.c
542
uint32_t reg;
sys/dev/pci/if_jme.c
591
reg = CSR_READ_4(sc, JME_CHIPMODE);
sys/dev/pci/if_jme.c
592
if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
sys/dev/pci/if_jme.c
599
(reg & CHIPMODE_FPGA_REV_MASK) >>
sys/dev/pci/if_jme.c
604
sc->jme_revfm = (reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT;
sys/dev/pci/if_jme.c
614
reg = CSR_READ_4(sc, JME_SMBCSR);
sys/dev/pci/if_jme.c
615
if (reg & SMBCSR_EEPROM_PRESENT)
sys/dev/pci/if_jme.c
617
if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
sys/dev/pci/if_jmevar.h
223
#define CSR_WRITE_4(_sc, reg, val) \
sys/dev/pci/if_jmevar.h
224
bus_space_write_4((_sc)->jme_mem_bt, (_sc)->jme_mem_bh, (reg), (val))
sys/dev/pci/if_jmevar.h
225
#define CSR_READ_4(_sc, reg) \
sys/dev/pci/if_jmevar.h
226
bus_space_read_4((_sc)->jme_mem_bt, (_sc)->jme_mem_bh, (reg))
sys/dev/pci/if_lge.c
159
#define LGE_SETBIT(sc, reg, x) \
sys/dev/pci/if_lge.c
160
CSR_WRITE_4(sc, reg, \
sys/dev/pci/if_lge.c
161
CSR_READ_4(sc, reg) | (x))
sys/dev/pci/if_lge.c
163
#define LGE_CLRBIT(sc, reg, x) \
sys/dev/pci/if_lge.c
164
CSR_WRITE_4(sc, reg, \
sys/dev/pci/if_lge.c
165
CSR_READ_4(sc, reg) & ~(x))
sys/dev/pci/if_lge.c
223
lge_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_lge.c
236
CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
sys/dev/pci/if_lge.c
251
lge_miibus_writereg(struct device *dev, int phy, int reg, int data)
sys/dev/pci/if_lge.c
257
(data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
sys/dev/pci/if_lgereg.h
527
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_lgereg.h
528
bus_space_write_4(sc->lge_btag, sc->lge_bhandle, reg, val)
sys/dev/pci/if_lgereg.h
530
#define CSR_READ_2(sc, reg) \
sys/dev/pci/if_lgereg.h
531
bus_space_read_2(sc->lge_btag, sc->lge_bhandle, reg)
sys/dev/pci/if_lgereg.h
533
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_lgereg.h
534
bus_space_write_2(sc->lge_btag, sc->lge_bhandle, reg, val)
sys/dev/pci/if_lgereg.h
536
#define CSR_READ_4(sc, reg) \
sys/dev/pci/if_lgereg.h
537
bus_space_read_4(sc->lge_btag, sc->lge_bhandle, reg)
sys/dev/pci/if_lgereg.h
539
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_lgereg.h
540
bus_space_write_1(sc->lge_btag, sc->lge_bhandle, reg, val)
sys/dev/pci/if_lgereg.h
542
#define CSR_READ_1(sc, reg) \
sys/dev/pci/if_lgereg.h
543
bus_space_read_1(sc->lge_btag, sc->lge_bhandle, reg)
sys/dev/pci/if_lii.c
168
#define LII_READ_4(sc,reg) \
sys/dev/pci/if_lii.c
169
bus_space_read_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg))
sys/dev/pci/if_lii.c
170
#define LII_READ_2(sc,reg) \
sys/dev/pci/if_lii.c
171
bus_space_read_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg))
sys/dev/pci/if_lii.c
172
#define LII_READ_1(sc,reg) \
sys/dev/pci/if_lii.c
173
bus_space_read_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg))
sys/dev/pci/if_lii.c
174
#define LII_WRITE_4(sc,reg,val) \
sys/dev/pci/if_lii.c
175
bus_space_write_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))
sys/dev/pci/if_lii.c
176
#define LII_WRITE_2(sc,reg,val) \
sys/dev/pci/if_lii.c
177
bus_space_write_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))
sys/dev/pci/if_lii.c
178
#define LII_WRITE_1(sc,reg,val) \
sys/dev/pci/if_lii.c
179
bus_space_write_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))
sys/dev/pci/if_lii.c
346
lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val)
sys/dev/pci/if_lii.c
348
return pci_vpd_read(sc->sc_pc, sc->sc_tag, reg, 1, (pcireg_t *)val);
sys/dev/pci/if_lii.c
422
lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val)
sys/dev/pci/if_lii.c
428
LII_WRITE_4(sc, LII_SF_ADDR, reg);
sys/dev/pci/if_lii.c
506
lii_mii_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_lii.c
512
val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT;
sys/dev/pci/if_lii.c
530
reg);
sys/dev/pci/if_lii.c
537
lii_mii_writereg(struct device *dev, int phy, int reg, int data)
sys/dev/pci/if_lii.c
543
val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT;
sys/dev/pci/if_lii.c
562
reg);
sys/dev/pci/if_mcx.c
3610
mcx_access_hca_reg(struct mcx_softc *sc, uint16_t reg, int op, void *data,
sys/dev/pci/if_mcx.c
3630
in->cmd_register_id = htobe16(reg);
sys/dev/pci/if_mcx.c
3648
(op == MCX_REG_OP_WRITE ? "write" : "read"), reg);
sys/dev/pci/if_mcx.c
3655
reg);
sys/dev/pci/if_mcx.c
3663
reg, out->cmd_status, betoh32(out->cmd_syndrome));
sys/dev/pci/if_msk.c
1985
u_int16_t reg;
sys/dev/pci/if_msk.c
2006
reg = SK_YU_READ_2(sc_if, YUKON_PAR);
sys/dev/pci/if_msk.c
2007
DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg));
sys/dev/pci/if_msk.c
2010
reg |= YU_PAR_MIB_CLR;
sys/dev/pci/if_msk.c
2011
DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg));
sys/dev/pci/if_msk.c
2013
SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
sys/dev/pci/if_msk.c
2017
reg &= ~YU_PAR_MIB_CLR;
sys/dev/pci/if_msk.c
2018
SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
sys/dev/pci/if_msk.c
2031
reg = YU_SMR_DATA_BLIND(0x1c) |
sys/dev/pci/if_msk.c
2037
reg |= YU_SMR_MFL_JUMBO;
sys/dev/pci/if_msk.c
2039
SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
sys/dev/pci/if_msk.c
2051
reg = sk_win_read_2(sc_if->sk_softc,
sys/dev/pci/if_msk.c
2053
SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
sys/dev/pci/if_msk.c
226
uint32_t reg;
sys/dev/pci/if_msk.c
2427
kstat_kv_u32(&kvs[i]) = msk_mib_read32(sc_if, m->reg);
sys/dev/pci/if_msk.c
2430
kstat_kv_u64(&kvs[i]) = msk_mib_read64(sc_if, m->reg);
sys/dev/pci/if_msk.c
345
sk_win_read_4(struct sk_softc *sc, u_int32_t reg)
sys/dev/pci/if_msk.c
347
return CSR_READ_4(sc, reg);
sys/dev/pci/if_msk.c
351
sk_win_read_2(struct sk_softc *sc, u_int32_t reg)
sys/dev/pci/if_msk.c
353
return CSR_READ_2(sc, reg);
sys/dev/pci/if_msk.c
357
sk_win_read_1(struct sk_softc *sc, u_int32_t reg)
sys/dev/pci/if_msk.c
359
return CSR_READ_1(sc, reg);
sys/dev/pci/if_msk.c
363
sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x)
sys/dev/pci/if_msk.c
365
CSR_WRITE_4(sc, reg, x);
sys/dev/pci/if_msk.c
369
sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x)
sys/dev/pci/if_msk.c
371
CSR_WRITE_2(sc, reg, x);
sys/dev/pci/if_msk.c
375
sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x)
sys/dev/pci/if_msk.c
377
CSR_WRITE_1(sc, reg, x);
sys/dev/pci/if_msk.c
381
msk_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_msk.c
388
YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
sys/dev/pci/if_msk.c
409
phy, reg, val));
sys/dev/pci/if_msk.c
415
msk_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_msk.c
421
phy, reg, val));
sys/dev/pci/if_msk.c
425
YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
sys/dev/pci/if_msk.c
751
int reg;
sys/dev/pci/if_msk.c
846
for (reg = SK_TO0;reg <= SK_TO11; reg++)
sys/dev/pci/if_msk.c
847
sk_win_write_1(sc, reg, 36);
sys/dev/pci/if_msk.c
849
for (reg = SK_TO0;reg <= SK_TO11; reg++)
sys/dev/pci/if_msk.c
850
sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36);
sys/dev/pci/if_mwx.c
2668
mt7921_reg_addr(struct mwx_softc *sc, uint32_t reg)
sys/dev/pci/if_mwx.c
2721
if (reg < 0x100000)
sys/dev/pci/if_mwx.c
2722
return reg;
sys/dev/pci/if_mwx.c
2727
if (reg < fixed_map[i].phys)
sys/dev/pci/if_mwx.c
2730
ofs = reg - fixed_map[i].phys;
sys/dev/pci/if_mwx.c
2737
if ((reg >= 0x18000000 && reg < 0x18c00000) ||
sys/dev/pci/if_mwx.c
2738
(reg >= 0x70000000 && reg < 0x78000000) ||
sys/dev/pci/if_mwx.c
2739
(reg >= 0x7c000000 && reg < 0x7c400000))
sys/dev/pci/if_mwx.c
2740
return mwx_map_reg_l1(sc, reg);
sys/dev/pci/if_mwx.c
2743
DEVNAME(sc), reg);
sys/dev/pci/if_mwx.c
2866
uint32_t reg, override = 0, option = 0;
sys/dev/pci/if_mwx.c
2869
reg = mwx_read(sc, MT_CONN_ON_MISC) & MT_TOP_MISC2_FW_N9_RDY;
sys/dev/pci/if_mwx.c
2870
if (reg != 0) {
sys/dev/pci/if_mwx.c
460
mwx_read(struct mwx_softc *sc, uint32_t reg)
sys/dev/pci/if_mwx.c
462
reg = mt7921_reg_addr(sc, reg);
sys/dev/pci/if_mwx.c
463
return bus_space_read_4(sc->sc_st, sc->sc_memh, reg);
sys/dev/pci/if_mwx.c
467
mwx_write(struct mwx_softc *sc, uint32_t reg, uint32_t val)
sys/dev/pci/if_mwx.c
469
reg = mt7921_reg_addr(sc, reg);
sys/dev/pci/if_mwx.c
470
bus_space_write_4(sc->sc_st, sc->sc_memh, reg, val);
sys/dev/pci/if_mwx.c
481
mwx_rmw(struct mwx_softc *sc, uint32_t reg, uint32_t val, uint32_t mask)
sys/dev/pci/if_mwx.c
483
reg = mt7921_reg_addr(sc, reg);
sys/dev/pci/if_mwx.c
484
val |= bus_space_read_4(sc->sc_st, sc->sc_memh, reg) & ~mask;
sys/dev/pci/if_mwx.c
485
bus_space_write_4(sc->sc_st, sc->sc_memh, reg, val);
sys/dev/pci/if_mwx.c
490
mwx_set(struct mwx_softc *sc, uint32_t reg, uint32_t bits)
sys/dev/pci/if_mwx.c
492
return mwx_rmw(sc, reg, bits, 0);
sys/dev/pci/if_mwx.c
496
mwx_clear(struct mwx_softc *sc, uint32_t reg, uint32_t bits)
sys/dev/pci/if_mwx.c
498
return mwx_rmw(sc, reg, 0, bits);
sys/dev/pci/if_mwx.c
502
mwx_map_reg_l1(struct mwx_softc *sc, uint32_t reg)
sys/dev/pci/if_mwx.c
504
uint32_t offset = MT_HIF_REMAP_L1_GET_OFFSET(reg);
sys/dev/pci/if_mwx.c
505
uint32_t base = MT_HIF_REMAP_L1_GET_BASE(reg);
sys/dev/pci/if_mwx.c
519
mwx_poll(struct mwx_softc *sc, uint32_t reg, uint32_t val, uint32_t mask,
sys/dev/pci/if_mwx.c
524
reg = mt7921_reg_addr(sc, reg);
sys/dev/pci/if_mwx.c
527
cur = bus_space_read_4(sc->sc_st, sc->sc_memh, reg) & mask;
sys/dev/pci/if_mwx.c
534
DEVNAME(sc), reg, val, mask, cur);
sys/dev/pci/if_mwxreg.h
918
uint32_t reg;
sys/dev/pci/if_myx.c
330
int reg;
sys/dev/pci/if_myx.c
333
®, NULL) == 0)
sys/dev/pci/if_myx.c
336
reg += PCI_PCIE_DCSR;
sys/dev/pci/if_myx.c
337
dcsr = pci_conf_read(sc->sc_pc, pa->pa_tag, reg);
sys/dev/pci/if_myx.c
341
pci_conf_write(sc->sc_pc, pa->pa_tag, reg, dcsr);
sys/dev/pci/if_nep.c
791
nep_read(struct nep_softc *sc, uint32_t reg)
sys/dev/pci/if_nep.c
793
return (bus_space_read_8(sc->sc_memt, sc->sc_memh, reg));
sys/dev/pci/if_nep.c
797
nep_write(struct nep_softc *sc, uint32_t reg, uint64_t value)
sys/dev/pci/if_nep.c
799
bus_space_write_8(sc->sc_memt, sc->sc_memh, reg, value);
sys/dev/pci/if_nep.c
803
nep_mii_readreg(struct device *self, int phy, int reg)
sys/dev/pci/if_nep.c
810
frame |= (reg << MIF_FRAME_REG_SHIFT) | (phy << MIF_FRAME_PHY_SHIFT);
sys/dev/pci/if_nep.c
824
nep_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/pci/if_nep.c
831
frame |= (reg << MIF_FRAME_REG_SHIFT) | (phy << MIF_FRAME_PHY_SHIFT);
sys/dev/pci/if_nfe.c
402
nfe_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_nfe.c
415
NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
sys/dev/pci/if_nfe.c
439
sc->sc_dev.dv_xname, phy, reg, val));
sys/dev/pci/if_nfe.c
445
nfe_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_nfe.c
459
ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
sys/dev/pci/if_nfereg.h
193
#define NFE_READ(sc, reg) \
sys/dev/pci/if_nfereg.h
194
bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg))
sys/dev/pci/if_nfereg.h
196
#define NFE_WRITE(sc, reg, val) \
sys/dev/pci/if_nfereg.h
197
bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (val))
sys/dev/pci/if_ngbe.c
2061
uint32_t reg;
sys/dev/pci/if_ngbe.c
2162
reg = hw->fc.pause_time * 0x00010000;
sys/dev/pci/if_ngbe.c
2163
NGBE_WRITE_REG(hw, NGBE_RDB_RFCV, reg);
sys/dev/pci/if_ngbe.c
2221
uint32_t reg = 0;
sys/dev/pci/if_ngbe.c
2229
reg = NGBE_READ_REG(hw, NGBE_SPI_ILDR_STATUS);
sys/dev/pci/if_ngbe.c
2230
if (!(reg & check_bit))
sys/dev/pci/if_ngbe.c
2603
ngbe_enable_rx_dma(struct ngbe_hw *hw, uint32_t reg)
sys/dev/pci/if_ngbe.c
2613
if (reg & NGBE_RDB_PB_CTL_PBEN)
sys/dev/pci/if_ngbe.c
2932
uint32_t reg;
sys/dev/pci/if_ngbe.c
2934
reg = NGBE_READ_REG(hw, NGBE_GPIO_INTSTATUS);
sys/dev/pci/if_ngbe.c
2935
NGBE_WRITE_REG(hw, NGBE_GPIO_EOI, reg);
sys/dev/pci/if_ngbe.c
3578
ngbe_read_pci_cfg_word(struct ngbe_softc *sc, uint32_t reg)
sys/dev/pci/if_ngbe.c
3585
if (reg & 0x2) {
sys/dev/pci/if_ngbe.c
3587
reg &= ~0x2;
sys/dev/pci/if_ngbe.c
3589
value = pci_conf_read(pa->pa_pc, pa->pa_tag, reg);
sys/dev/pci/if_ngbe.c
372
NGBE_READ_REG_MASK(struct ngbe_hw *hw, uint32_t reg, uint32_t mask)
sys/dev/pci/if_ngbe.c
376
val = NGBE_READ_REG(hw, reg);
sys/dev/pci/if_ngbe.c
383
NGBE_WRITE_REG_MASK(struct ngbe_hw *hw, uint32_t reg, uint32_t mask,
sys/dev/pci/if_ngbe.c
388
val = NGBE_READ_REG(hw, reg);
sys/dev/pci/if_ngbe.c
3880
uint32_t reg = 0;
sys/dev/pci/if_ngbe.c
3882
reg = NGBE_READ_REG(hw, NGBE_CFG_PORT_ST);
sys/dev/pci/if_ngbe.c
3883
bus->lan_id = NGBE_CFG_PORT_ST_LAN_ID(reg);
sys/dev/pci/if_ngbe.c
392
NGBE_WRITE_REG(hw, reg, val);
sys/dev/pci/if_ngbe.c
832
uint32_t reg, speed = 0;
sys/dev/pci/if_ngbe.c
872
reg = NGBE_READ_REG(hw, NGBE_MAC_RX_CFG);
sys/dev/pci/if_ngbe.c
873
NGBE_WRITE_REG(hw, NGBE_MAC_RX_CFG, reg);
sys/dev/pci/if_ngbe.c
875
reg = NGBE_READ_REG(hw, NGBE_MAC_WDG_TIMEOUT);
sys/dev/pci/if_ngbe.c
876
NGBE_WRITE_REG(hw, NGBE_MAC_WDG_TIMEOUT, reg);
sys/dev/pci/if_ngbereg.h
1076
#define NGBE_READ_REG(a, reg) \
sys/dev/pci/if_ngbereg.h
1078
((struct ngbe_osdep *)(a)->back)->os_memh, reg)
sys/dev/pci/if_ngbereg.h
1079
#define NGBE_WRITE_REG(a, reg, value) \
sys/dev/pci/if_ngbereg.h
1081
((struct ngbe_osdep *)(a)->back)->os_memh, reg, value)
sys/dev/pci/if_ngbereg.h
1082
#define NGBE_READ_REG_ARRAY(a, reg, offset) \
sys/dev/pci/if_ngbereg.h
1084
((struct ngbe_osdep *)(a)->back)->os_memh, (reg + ((offset) << 2)))
sys/dev/pci/if_ngbereg.h
1085
#define NGBE_WRITE_REG_ARRAY(a, reg, offset, value) \
sys/dev/pci/if_ngbereg.h
1088
(reg + ((offset) << 2)), value)
sys/dev/pci/if_nge.c
180
#define NGE_SETBIT(sc, reg, x) \
sys/dev/pci/if_nge.c
181
CSR_WRITE_4(sc, reg, \
sys/dev/pci/if_nge.c
182
CSR_READ_4(sc, reg) | (x))
sys/dev/pci/if_nge.c
184
#define NGE_CLRBIT(sc, reg, x) \
sys/dev/pci/if_nge.c
185
CSR_WRITE_4(sc, reg, \
sys/dev/pci/if_nge.c
186
CSR_READ_4(sc, reg) & ~(x))
sys/dev/pci/if_nge.c
495
nge_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_nge.c
505
frame.mii_regaddr = reg;
sys/dev/pci/if_nge.c
512
nge_miibus_writereg(struct device *dev, int phy, int reg, int data)
sys/dev/pci/if_nge.c
523
frame.mii_regaddr = reg;
sys/dev/pci/if_ngereg.h
659
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_ngereg.h
660
bus_space_write_4(sc->nge_btag, sc->nge_bhandle, reg, val)
sys/dev/pci/if_ngereg.h
662
#define CSR_READ_4(sc, reg) \
sys/dev/pci/if_ngereg.h
663
bus_space_read_4(sc->nge_btag, sc->nge_bhandle, reg)
sys/dev/pci/if_oce.c
2679
uint32_t reg;
sys/dev/pci/if_oce.c
2683
reg = oce_read_csr(sc, MPU_EP_SEMAPHORE(sc));
sys/dev/pci/if_oce.c
2686
if ((reg & MPU_EP_SEM_STAGE_MASK) <= POST_STAGE_AWAITING_HOST_RDY) {
sys/dev/pci/if_oce.c
2687
reg = (reg & ~MPU_EP_SEM_STAGE_MASK) | POST_STAGE_CHIP_RESET;
sys/dev/pci/if_oce.c
2688
oce_write_csr(sc, MPU_EP_SEMAPHORE(sc), reg);
sys/dev/pci/if_oce.c
2698
reg = oce_read_csr(sc, MPU_EP_SEMAPHORE(sc));
sys/dev/pci/if_oce.c
2699
if (reg & MPU_EP_SEM_ERROR) {
sys/dev/pci/if_oce.c
2700
printf(": POST failed: %#x\n", reg);
sys/dev/pci/if_oce.c
2703
if ((reg & MPU_EP_SEM_STAGE_MASK) == POST_STAGE_ARMFW_READY) {
sys/dev/pci/if_oce.c
2715
printf(": POST timed out: %#x\n", reg);
sys/dev/pci/if_oce.c
2740
uint32_t pa, reg;
sys/dev/pci/if_oce.c
2744
reg = PD_MPU_MBOX_DB_HI | (pa << PD_MPU_MBOX_DB_ADDR_SHIFT);
sys/dev/pci/if_oce.c
2749
oce_write_db(sc, PD_MPU_MBOX_DB, reg);
sys/dev/pci/if_oce.c
2752
reg = pa << PD_MPU_MBOX_DB_ADDR_SHIFT;
sys/dev/pci/if_oce.c
2757
oce_write_db(sc, PD_MPU_MBOX_DB, reg);
sys/dev/pci/if_oce.c
648
pcireg_t memtype, reg;
sys/dev/pci/if_oce.c
652
reg = OCE_BAR_CFG_BE2;
sys/dev/pci/if_oce.c
654
reg = OCE_BAR_CFG;
sys/dev/pci/if_oce.c
656
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, reg);
sys/dev/pci/if_oce.c
657
if (pci_mapreg_map(pa, reg, memtype, 0, &sc->sc_cfg_iot,
sys/dev/pci/if_oce.c
668
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, OCE_INTF_REG_OFFSET);
sys/dev/pci/if_oce.c
669
if (OCE_SLI_SIGNATURE(reg) != OCE_INTF_VALID_SIG) {
sys/dev/pci/if_oce.c
673
if (OCE_SLI_REVISION(reg) != OCE_INTF_SLI_REV4) {
sys/dev/pci/if_oce.c
677
if (OCE_SLI_IFTYPE(reg) == OCE_INTF_IF_TYPE_1)
sys/dev/pci/if_oce.c
679
if (OCE_SLI_HINT1(reg) == OCE_INTF_FUNC_RESET_REQD)
sys/dev/pci/if_oce.c
685
reg = OCE_BAR_CSR;
sys/dev/pci/if_oce.c
686
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, reg);
sys/dev/pci/if_oce.c
687
if (pci_mapreg_map(pa, reg, memtype, 0, &sc->sc_csr_iot,
sys/dev/pci/if_oce.c
694
reg = OCE_BAR_DB;
sys/dev/pci/if_oce.c
695
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, reg);
sys/dev/pci/if_oce.c
696
if (pci_mapreg_map(pa, reg, memtype, 0, &sc->sc_db_iot,
sys/dev/pci/if_oce.c
766
uint32_t reg;
sys/dev/pci/if_oce.c
768
reg = oce_read_cfg(sc, PCI_INTR_CTRL);
sys/dev/pci/if_oce.c
769
oce_write_cfg(sc, PCI_INTR_CTRL, reg | HOSTINTR_MASK);
sys/dev/pci/if_oce.c
775
uint32_t reg;
sys/dev/pci/if_oce.c
777
reg = oce_read_cfg(sc, PCI_INTR_CTRL);
sys/dev/pci/if_oce.c
778
oce_write_cfg(sc, PCI_INTR_CTRL, reg & ~HOSTINTR_MASK);
sys/dev/pci/if_ocereg.h
149
#define OCE_SLI_FUNCTION(reg) ((reg) & 0x1)
sys/dev/pci/if_ocereg.h
150
#define OCE_SLI_REVISION(reg) (((reg) >> 4) & 0xf)
sys/dev/pci/if_ocereg.h
151
#define OCE_SLI_FAMILY(reg) (((reg) >> 8) & 0xf)
sys/dev/pci/if_ocereg.h
152
#define OCE_SLI_IFTYPE(reg) (((reg) >> 12) & 0xf)
sys/dev/pci/if_ocereg.h
153
#define OCE_SLI_HINT1(reg) (((reg) >> 16) & 0xff)
sys/dev/pci/if_ocereg.h
154
#define OCE_SLI_HINT2(reg) (((reg) >> 24) & 0x1f)
sys/dev/pci/if_ocereg.h
155
#define OCE_SLI_SIGNATURE(reg) (((reg) >> 29) & 0x7)
sys/dev/pci/if_pcn.c
1439
uint32_t reg;
sys/dev/pci/if_pcn.c
1578
reg = pcn_bcr_read(sc, LE_BCR18);
sys/dev/pci/if_pcn.c
1584
reg |= LE_B18_BREADE|LE_B18_BWRITE;
sys/dev/pci/if_pcn.c
1588
reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO;
sys/dev/pci/if_pcn.c
1591
pcn_bcr_write(sc, LE_BCR18, reg);
sys/dev/pci/if_pcn.c
1861
uint32_t reg;
sys/dev/pci/if_pcn.c
1867
reg = pcn_bcr_read(sc, LE_BCR2);
sys/dev/pci/if_pcn.c
1868
reg |= LE_B2_ASEL;
sys/dev/pci/if_pcn.c
1869
pcn_bcr_write(sc, LE_BCR2, reg);
sys/dev/pci/if_pcn.c
1874
reg = pcn_bcr_read(sc, LE_BCR2);
sys/dev/pci/if_pcn.c
1875
reg &= ~LE_B2_ASEL;
sys/dev/pci/if_pcn.c
1876
pcn_bcr_write(sc, LE_BCR2, reg);
sys/dev/pci/if_pcn.c
1878
reg = pcn_csr_read(sc, LE_CSR15);
sys/dev/pci/if_pcn.c
1879
reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) |
sys/dev/pci/if_pcn.c
1881
pcn_csr_write(sc, LE_CSR15, reg);
sys/dev/pci/if_pcn.c
1885
reg = LE_B9_FDEN;
sys/dev/pci/if_pcn.c
1887
reg |= LE_B9_AUIFD;
sys/dev/pci/if_pcn.c
1888
pcn_bcr_write(sc, LE_BCR9, reg);
sys/dev/pci/if_pcn.c
1972
pcn_mii_readreg(struct device *self, int phy, int reg)
sys/dev/pci/if_pcn.c
1977
pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT));
sys/dev/pci/if_pcn.c
1991
pcn_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/pci/if_pcn.c
1995
pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT));
sys/dev/pci/if_pcn.c
488
pcn_csr_read(struct pcn_softc *sc, int reg)
sys/dev/pci/if_pcn.c
491
bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg);
sys/dev/pci/if_pcn.c
496
pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val)
sys/dev/pci/if_pcn.c
499
bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg);
sys/dev/pci/if_pcn.c
504
pcn_bcr_read(struct pcn_softc *sc, int reg)
sys/dev/pci/if_pcn.c
507
bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg);
sys/dev/pci/if_pcn.c
512
pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val)
sys/dev/pci/if_pcn.c
515
bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg);
sys/dev/pci/if_pcn.c
570
uint32_t chipid, reg;
sys/dev/pci/if_pcn.c
742
reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff;
sys/dev/pci/if_pcn.c
743
if (reg != 0)
sys/dev/pci/if_qwx_pci.c
2950
uint32_t reg;
sys/dev/pci/if_qwx_pci.c
2953
reg = qwx_pcic_read32(sc, MHI_STATUS);
sys/dev/pci/if_qwx_pci.c
2955
DNPRINTF(QWX_D_MHI, "%s: MHISTATUS 0x%x\n", sc->sc_dev.dv_xname, reg);
sys/dev/pci/if_qwx_pci.c
2961
if (force || (reg & MHI_STATUS_SYSERR_MASK)) {
sys/dev/pci/if_qwx_pci.c
3083
uint32_t reg;
sys/dev/pci/if_qwx_pci.c
3089
reg = qwx_pci_read(sc, MHI_CTRL);
sys/dev/pci/if_qwx_pci.c
3090
DNPRINTF(QWX_D_MHI, "%s: MHI_CTRL is 0x%x\n", __func__, reg);
sys/dev/pci/if_qwx_pci.c
3091
if ((reg & MHI_CTRL_RESET_MASK) == 0)
sys/dev/pci/if_qwx_pci.c
3107
uint32_t reg;
sys/dev/pci/if_qwx_pci.c
3115
reg = qwx_pci_read(sc, MHI_STATUS);
sys/dev/pci/if_qwx_pci.c
3116
DNPRINTF(QWX_D_MHI, "%s: MHI_STATUS is 0x%x\n", __func__, reg);
sys/dev/pci/if_qwx_pci.c
3117
if (reg & MHI_STATUS_READY_MASK) {
sys/dev/pci/if_qwx_pci.c
3118
reg &= ~MHI_STATUS_READY_MASK;
sys/dev/pci/if_qwx_pci.c
3119
qwx_pci_write(sc, MHI_STATUS, reg);
sys/dev/pci/if_qwx_pci.c
3193
uint32_t reg;
sys/dev/pci/if_qwx_pci.c
3195
reg = qwx_pci_read(sc, MHI_CTRL);
sys/dev/pci/if_qwx_pci.c
3198
reg &= ~MHI_CTRL_MHISTATE_MASK;
sys/dev/pci/if_qwx_pci.c
3199
reg |= (state << MHI_CTRL_MHISTATE_SHFT) & MHI_CTRL_MHISTATE_MASK;
sys/dev/pci/if_qwx_pci.c
3201
reg |= MHI_CTRL_RESET_MASK;
sys/dev/pci/if_qwx_pci.c
3203
qwx_pci_write(sc, MHI_CTRL, reg);
sys/dev/pci/if_qwx_pci.c
3211
uint32_t reg;
sys/dev/pci/if_qwx_pci.c
3214
reg = qwx_pci_read(sc, MHI_CHDBOFF);
sys/dev/pci/if_qwx_pci.c
3217
psc->wake_db = reg + 8 * MHI_DEV_WAKE_DB;
sys/dev/pci/if_qwx_pci.c
3222
ring->db_addr = reg + (8 * ring->mhi_chan_id);
sys/dev/pci/if_qwx_pci.c
3225
reg = qwx_pci_read(sc, MHI_ERDBOFF);
sys/dev/pci/if_qwx_pci.c
3229
ring->db_addr = reg + (8 * i);
sys/dev/pci/if_qwx_pci.c
3254
reg = qwx_pci_read(sc, MHI_CFG);
sys/dev/pci/if_qwx_pci.c
3255
reg &= ~(MHI_CFG_NER_MASK | MHI_CFG_NHWER_MASK);
sys/dev/pci/if_qwx_pci.c
3256
reg |= QWX_NUM_EVENT_CTX << MHI_CFG_NER_SHFT;
sys/dev/pci/if_qwx_pci.c
3257
qwx_pci_write(sc, MHI_CFG, reg);
sys/dev/pci/if_qwx_pci.c
3265
uint32_t seq, reg, status = MHI_BHI_STATUS_RESET;
sys/dev/pci/if_qwx_pci.c
3300
reg = qwx_pci_read(sc, psc->bhi_off + MHI_BHI_STATUS);
sys/dev/pci/if_qwx_pci.c
3301
status = (reg & MHI_BHI_STATUS_MASK) >> MHI_BHI_STATUS_SHFT;
sys/dev/pci/if_qwx_pci.c
3306
reg = qwx_pci_read(sc, psc->bhi_off + MHI_BHI_STATUS);
sys/dev/pci/if_qwx_pci.c
3307
status = (reg & MHI_BHI_STATUS_MASK) >> MHI_BHI_STATUS_SHFT;
sys/dev/pci/if_qwx_pci.c
3321
uint32_t seq, reg, state = MHI_BHIE_TXVECSTATUS_STATUS_RESET;
sys/dev/pci/if_qwx_pci.c
3388
reg = qwx_pci_read(sc, psc->bhie_off + MHI_BHIE_TXVECDB_OFFS);
sys/dev/pci/if_qwx_pci.c
3389
reg &= ~MHI_BHIE_TXVECDB_SEQNUM_BMSK;
sys/dev/pci/if_qwx_pci.c
3390
reg |= seq << MHI_BHIE_TXVECDB_SEQNUM_SHFT;
sys/dev/pci/if_qwx_pci.c
3391
qwx_pci_write(sc, psc->bhie_off + MHI_BHIE_TXVECDB_OFFS, reg);
sys/dev/pci/if_qwx_pci.c
3400
reg = qwx_pci_read(sc,
sys/dev/pci/if_qwx_pci.c
3402
state = (reg & MHI_BHIE_TXVECSTATUS_STATUS_BMSK) >>
sys/dev/pci/if_qwx_pci.c
3421
uint32_t seq, reg;
sys/dev/pci/if_qwx_pci.c
3481
reg = qwx_pci_read(sc, psc->bhie_off + MHI_BHIE_RXVECDB_OFFS);
sys/dev/pci/if_qwx_pci.c
3482
reg &= ~MHI_BHIE_RXVECDB_SEQNUM_BMSK;
sys/dev/pci/if_qwx_pci.c
3483
reg |= seq << MHI_BHIE_RXVECDB_SEQNUM_SHFT;
sys/dev/pci/if_qwx_pci.c
3484
qwx_pci_write(sc, psc->bhie_off + MHI_BHIE_RXVECDB_OFFS, reg);
sys/dev/pci/if_qwx_pci.c
3496
uint32_t reg, state = MHI_BHIE_RXVECSTATUS_STATUS_RESET;
sys/dev/pci/if_qwx_pci.c
3516
reg = qwx_pci_read(sc,
sys/dev/pci/if_qwx_pci.c
3518
state = (reg & MHI_BHIE_RXVECSTATUS_STATUS_BMSK) >>
sys/dev/pci/if_qwx_pci.c
761
pcireg_t memtype, reg;
sys/dev/pci/if_qwx_pci.c
809
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
sys/dev/pci/if_qwx_pci.c
810
reg |= PCI_COMMAND_MASTER_ENABLE;
sys/dev/pci/if_qwx_pci.c
811
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);
sys/dev/pci/if_qwz_pci.c
2817
uint32_t reg;
sys/dev/pci/if_qwz_pci.c
2820
reg = qwz_pcic_read32(sc, MHI_STATUS);
sys/dev/pci/if_qwz_pci.c
2822
DNPRINTF(QWZ_D_MHI, "%s: MHISTATUS 0x%x\n", sc->sc_dev.dv_xname, reg);
sys/dev/pci/if_qwz_pci.c
2828
if (force || (reg & MHI_STATUS_SYSERR_MASK)) {
sys/dev/pci/if_qwz_pci.c
2950
uint32_t reg;
sys/dev/pci/if_qwz_pci.c
2956
reg = qwz_pci_read(sc, MHI_CTRL);
sys/dev/pci/if_qwz_pci.c
2957
DNPRINTF(QWZ_D_MHI, "%s: MHI_CTRL is 0x%x\n", __func__, reg);
sys/dev/pci/if_qwz_pci.c
2958
if ((reg & MHI_CTRL_RESET_MASK) == 0)
sys/dev/pci/if_qwz_pci.c
2974
uint32_t reg;
sys/dev/pci/if_qwz_pci.c
2982
reg = qwz_pci_read(sc, MHI_STATUS);
sys/dev/pci/if_qwz_pci.c
2983
DNPRINTF(QWZ_D_MHI, "%s: MHI_STATUS is 0x%x\n", __func__, reg);
sys/dev/pci/if_qwz_pci.c
2984
if (reg & MHI_STATUS_READY_MASK) {
sys/dev/pci/if_qwz_pci.c
2985
reg &= ~MHI_STATUS_READY_MASK;
sys/dev/pci/if_qwz_pci.c
2986
qwz_pci_write(sc, MHI_STATUS, reg);
sys/dev/pci/if_qwz_pci.c
3060
uint32_t reg;
sys/dev/pci/if_qwz_pci.c
3062
reg = qwz_pci_read(sc, MHI_CTRL);
sys/dev/pci/if_qwz_pci.c
3065
reg &= ~MHI_CTRL_MHISTATE_MASK;
sys/dev/pci/if_qwz_pci.c
3066
reg |= (state << MHI_CTRL_MHISTATE_SHFT) & MHI_CTRL_MHISTATE_MASK;
sys/dev/pci/if_qwz_pci.c
3068
reg |= MHI_CTRL_RESET_MASK;
sys/dev/pci/if_qwz_pci.c
3070
qwz_pci_write(sc, MHI_CTRL, reg);
sys/dev/pci/if_qwz_pci.c
3078
uint32_t reg;
sys/dev/pci/if_qwz_pci.c
3081
reg = qwz_pci_read(sc, MHI_CHDBOFF);
sys/dev/pci/if_qwz_pci.c
3084
psc->wake_db = reg + 8 * MHI_DEV_WAKE_DB;
sys/dev/pci/if_qwz_pci.c
3089
ring->db_addr = reg + (8 * ring->mhi_chan_id);
sys/dev/pci/if_qwz_pci.c
3092
reg = qwz_pci_read(sc, MHI_ERDBOFF);
sys/dev/pci/if_qwz_pci.c
3096
ring->db_addr = reg + (8 * i);
sys/dev/pci/if_qwz_pci.c
3121
reg = qwz_pci_read(sc, MHI_CFG);
sys/dev/pci/if_qwz_pci.c
3122
reg &= ~(MHI_CFG_NER_MASK | MHI_CFG_NHWER_MASK);
sys/dev/pci/if_qwz_pci.c
3123
reg |= QWZ_NUM_EVENT_CTX << MHI_CFG_NER_SHFT;
sys/dev/pci/if_qwz_pci.c
3124
qwz_pci_write(sc, MHI_CFG, reg);
sys/dev/pci/if_qwz_pci.c
3132
uint32_t seq, reg, status = MHI_BHI_STATUS_RESET;
sys/dev/pci/if_qwz_pci.c
3167
reg = qwz_pci_read(sc, psc->bhi_off + MHI_BHI_STATUS);
sys/dev/pci/if_qwz_pci.c
3168
status = (reg & MHI_BHI_STATUS_MASK) >> MHI_BHI_STATUS_SHFT;
sys/dev/pci/if_qwz_pci.c
3173
reg = qwz_pci_read(sc, psc->bhi_off + MHI_BHI_STATUS);
sys/dev/pci/if_qwz_pci.c
3174
status = (reg & MHI_BHI_STATUS_MASK) >> MHI_BHI_STATUS_SHFT;
sys/dev/pci/if_qwz_pci.c
3188
uint32_t seq, reg, state = MHI_BHIE_TXVECSTATUS_STATUS_RESET;
sys/dev/pci/if_qwz_pci.c
3255
reg = qwz_pci_read(sc, psc->bhie_off + MHI_BHIE_TXVECDB_OFFS);
sys/dev/pci/if_qwz_pci.c
3256
reg &= ~MHI_BHIE_TXVECDB_SEQNUM_BMSK;
sys/dev/pci/if_qwz_pci.c
3257
reg |= seq << MHI_BHIE_TXVECDB_SEQNUM_SHFT;
sys/dev/pci/if_qwz_pci.c
3258
qwz_pci_write(sc, psc->bhie_off + MHI_BHIE_TXVECDB_OFFS, reg);
sys/dev/pci/if_qwz_pci.c
3267
reg = qwz_pci_read(sc,
sys/dev/pci/if_qwz_pci.c
3269
state = (reg & MHI_BHIE_TXVECSTATUS_STATUS_BMSK) >>
sys/dev/pci/if_qwz_pci.c
3288
uint32_t seq, reg;
sys/dev/pci/if_qwz_pci.c
3345
reg = qwz_pci_read(sc, psc->bhie_off + MHI_BHIE_RXVECDB_OFFS);
sys/dev/pci/if_qwz_pci.c
3346
reg &= ~MHI_BHIE_RXVECDB_SEQNUM_BMSK;
sys/dev/pci/if_qwz_pci.c
3347
reg |= seq << MHI_BHIE_RXVECDB_SEQNUM_SHFT;
sys/dev/pci/if_qwz_pci.c
3348
qwz_pci_write(sc, psc->bhie_off + MHI_BHIE_RXVECDB_OFFS, reg);
sys/dev/pci/if_qwz_pci.c
3360
uint32_t reg, state = MHI_BHIE_RXVECSTATUS_STATUS_RESET;
sys/dev/pci/if_qwz_pci.c
3380
reg = qwz_pci_read(sc,
sys/dev/pci/if_qwz_pci.c
3382
state = (reg & MHI_BHIE_RXVECSTATUS_STATUS_BMSK) >>
sys/dev/pci/if_qwz_pci.c
686
pcireg_t memtype, reg;
sys/dev/pci/if_qwz_pci.c
734
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
sys/dev/pci/if_qwz_pci.c
735
reg |= PCI_COMMAND_MASTER_ENABLE;
sys/dev/pci/if_qwz_pci.c
736
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);
sys/dev/pci/if_re_pci.c
127
pcireg_t reg;
sys/dev/pci/if_re_pci.c
181
reg = pci_conf_read(pc, pa->pa_tag, offset + PCI_PCIE_LCSR);
sys/dev/pci/if_re_pci.c
182
reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1 |
sys/dev/pci/if_re_pci.c
184
pci_conf_write(pc, pa->pa_tag, offset + PCI_PCIE_LCSR, reg);
sys/dev/pci/if_rge.c
144
uint16_t reg;
sys/dev/pci/if_rge.c
1663
uint16_t reg;
sys/dev/pci/if_rge.c
1672
rtl8125_mac_bps[i].reg,
sys/dev/pci/if_rge.c
1676
rtl8125_mac_bps[i].reg, 0);
sys/dev/pci/if_rge.c
1678
if (rtl8125_mac_bps[i].reg < 0xf9f8)
sys/dev/pci/if_rge.c
1680
rtl8125_mac_bps[i].reg, 0);
sys/dev/pci/if_rge.c
1702
rge_write_mac_ocp(sc, rtl8125b_mac_bps[i].reg,
sys/dev/pci/if_rge.c
1728
for (reg = 0xf812; reg <= 0xf9f6; reg += 2)
sys/dev/pci/if_rge.c
1729
rge_write_mac_ocp(sc, reg, 0);
sys/dev/pci/if_rge.c
1750
rtl8125d_2_mac_bps[i].reg,
sys/dev/pci/if_rge.c
1754
rtl8125d_2_mac_bps[i].reg, 0);
sys/dev/pci/if_rge.c
1757
for (reg = 0xf884; reg <= 0xf9f6; reg += 2)
sys/dev/pci/if_rge.c
1758
rge_write_mac_ocp(sc, reg, 0);
sys/dev/pci/if_rge.c
186
pcireg_t reg;
sys/dev/pci/if_rge.c
1921
rge_write_ephy(sc, mac_r25_ephy[i].reg, mac_r25_ephy[i].val);
sys/dev/pci/if_rge.c
1945
rge_write_ephy(sc, mac_r25b_ephy[i].reg, mac_r25b_ephy[i].val);
sys/dev/pci/if_rge.c
1954
rge_r27_write_ephy(sc, mac_r27_ephy[i].reg,
sys/dev/pci/if_rge.c
288
reg = pci_conf_read(pa->pa_pc, pa->pa_tag,
sys/dev/pci/if_rge.c
290
reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1 |
sys/dev/pci/if_rge.c
293
reg);
sys/dev/pci/if_rge.c
3140
mac_r25_mcu[i].reg, mac_r25_mcu[i].val);
sys/dev/pci/if_rge.c
3152
mac_r25b_mcu[i].reg, mac_r25b_mcu[i].val);
sys/dev/pci/if_rge.c
3156
mac_r25d_1_mcu[i].reg,
sys/dev/pci/if_rge.c
3163
mac_r25d_1_mcu[i].reg,
sys/dev/pci/if_rge.c
3170
mac_r25d_1_mcu[i].reg,
sys/dev/pci/if_rge.c
3175
mac_r25d_2_mcu[i].reg,
sys/dev/pci/if_rge.c
3182
mac_r25d_2_mcu[i].reg,
sys/dev/pci/if_rge.c
3187
mac_r26_1_mcu[i].reg, mac_r26_1_mcu[i].val);
sys/dev/pci/if_rge.c
3193
mac_r26_1_mcu[i].reg, mac_r26_1_mcu[i].val);
sys/dev/pci/if_rge.c
3197
mac_r26_2_mcu[i].reg, mac_r26_2_mcu[i].val);
sys/dev/pci/if_rge.c
3201
mac_r27_mcu[i].reg, mac_r27_mcu[i].val);
sys/dev/pci/if_rge.c
3207
mac_r27_mcu[i].reg, mac_r27_mcu[i].val);
sys/dev/pci/if_rge.c
3246
uint16_t reg;
sys/dev/pci/if_rge.c
3257
for (reg = 0xfc28; reg < 0xfc48; reg += 2)
sys/dev/pci/if_rge.c
3258
rge_write_mac_ocp(sc, reg, 0);
sys/dev/pci/if_rge.c
3489
rge_write_csi(struct rge_softc *sc, uint32_t reg, uint32_t val)
sys/dev/pci/if_rge.c
3494
RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |
sys/dev/pci/if_rge.c
3507
rge_read_csi(struct rge_softc *sc, uint32_t reg)
sys/dev/pci/if_rge.c
3511
RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |
sys/dev/pci/if_rge.c
3526
rge_write_mac_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val)
sys/dev/pci/if_rge.c
3530
tmp = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT;
sys/dev/pci/if_rge.c
3537
rge_read_mac_ocp(struct rge_softc *sc, uint16_t reg)
sys/dev/pci/if_rge.c
3541
val = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT;
sys/dev/pci/if_rge.c
3548
rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val)
sys/dev/pci/if_rge.c
3553
tmp = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT;
sys/dev/pci/if_rge.c
3567
rge_read_ephy(struct rge_softc *sc, uint16_t reg)
sys/dev/pci/if_rge.c
3572
val = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT;
sys/dev/pci/if_rge.c
3588
rge_check_ephy_ext_add(struct rge_softc *sc, uint16_t reg)
sys/dev/pci/if_rge.c
3592
val = (reg >> 12);
sys/dev/pci/if_rge.c
3595
return reg & 0x0fff;
sys/dev/pci/if_rge.c
3599
rge_r27_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val)
sys/dev/pci/if_rge.c
3601
rge_write_ephy(sc, rge_check_ephy_ext_add(sc, reg), val);
sys/dev/pci/if_rge.c
3605
rge_write_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg, uint16_t val)
sys/dev/pci/if_rge.c
3609
phyaddr = addr ? addr : RGE_PHYBASE + (reg / 8);
sys/dev/pci/if_rge.c
3612
off = addr ? reg : 0x10 + (reg % 8);
sys/dev/pci/if_rge.c
3620
rge_read_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg)
sys/dev/pci/if_rge.c
3624
phyaddr = addr ? addr : RGE_PHYBASE + (reg / 8);
sys/dev/pci/if_rge.c
3627
off = addr ? reg : 0x10 + (reg % 8);
sys/dev/pci/if_rge.c
3635
rge_write_phy_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val)
sys/dev/pci/if_rge.c
3640
tmp = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT;
sys/dev/pci/if_rge.c
3652
rge_read_phy_ocp(struct rge_softc *sc, uint16_t reg)
sys/dev/pci/if_rge.c
3657
val = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT;
sys/dev/pci/if_rge.c
3825
uint32_t reg;
sys/dev/pci/if_rge.c
3852
reg = RGE_READ_4(sc, RGE_DTCCR_LO);
sys/dev/pci/if_rge.c
3853
if (!ISSET(reg, RGE_DTCCR_CMD))
sys/dev/pci/if_rge.c
3864
if (ISSET(reg, RGE_DTCCR_CMD))
sys/dev/pci/if_rgereg.h
443
#define RGE_WRITE_4(sc, reg, val) \
sys/dev/pci/if_rgereg.h
444
bus_space_write_4(sc->rge_btag, sc->rge_bhandle, reg, val)
sys/dev/pci/if_rgereg.h
445
#define RGE_WRITE_2(sc, reg, val) \
sys/dev/pci/if_rgereg.h
446
bus_space_write_2(sc->rge_btag, sc->rge_bhandle, reg, val)
sys/dev/pci/if_rgereg.h
447
#define RGE_WRITE_1(sc, reg, val) \
sys/dev/pci/if_rgereg.h
448
bus_space_write_1(sc->rge_btag, sc->rge_bhandle, reg, val)
sys/dev/pci/if_rgereg.h
450
#define RGE_READ_4(sc, reg) \
sys/dev/pci/if_rgereg.h
451
bus_space_read_4(sc->rge_btag, sc->rge_bhandle, reg)
sys/dev/pci/if_rgereg.h
452
#define RGE_READ_2(sc, reg) \
sys/dev/pci/if_rgereg.h
453
bus_space_read_2(sc->rge_btag, sc->rge_bhandle, reg)
sys/dev/pci/if_rgereg.h
454
#define RGE_READ_1(sc, reg) \
sys/dev/pci/if_rgereg.h
455
bus_space_read_1(sc->rge_btag, sc->rge_bhandle, reg)
sys/dev/pci/if_rgereg.h
457
#define RGE_SETBIT_4(sc, reg, val) \
sys/dev/pci/if_rgereg.h
458
RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) | (val))
sys/dev/pci/if_rgereg.h
459
#define RGE_SETBIT_2(sc, reg, val) \
sys/dev/pci/if_rgereg.h
460
RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) | (val))
sys/dev/pci/if_rgereg.h
461
#define RGE_SETBIT_1(sc, reg, val) \
sys/dev/pci/if_rgereg.h
462
RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) | (val))
sys/dev/pci/if_rgereg.h
464
#define RGE_CLRBIT_4(sc, reg, val) \
sys/dev/pci/if_rgereg.h
465
RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) & ~(val))
sys/dev/pci/if_rgereg.h
466
#define RGE_CLRBIT_2(sc, reg, val) \
sys/dev/pci/if_rgereg.h
467
RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) & ~(val))
sys/dev/pci/if_rgereg.h
468
#define RGE_CLRBIT_1(sc, reg, val) \
sys/dev/pci/if_rgereg.h
469
RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) & ~(val))
sys/dev/pci/if_rgereg.h
471
#define RGE_EPHY_SETBIT(sc, reg, val) \
sys/dev/pci/if_rgereg.h
472
rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) | (val))
sys/dev/pci/if_rgereg.h
474
#define RGE_EPHY_CLRBIT(sc, reg, val) \
sys/dev/pci/if_rgereg.h
475
rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) & ~(val))
sys/dev/pci/if_rgereg.h
477
#define RGE_PHY_SETBIT(sc, reg, val) \
sys/dev/pci/if_rgereg.h
478
rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) | (val))
sys/dev/pci/if_rgereg.h
480
#define RGE_PHY_CLRBIT(sc, reg, val) \
sys/dev/pci/if_rgereg.h
481
rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) & ~(val))
sys/dev/pci/if_rgereg.h
483
#define RGE_MAC_SETBIT(sc, reg, val) \
sys/dev/pci/if_rgereg.h
484
rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) | (val))
sys/dev/pci/if_rgereg.h
486
#define RGE_MAC_CLRBIT(sc, reg, val) \
sys/dev/pci/if_rgereg.h
487
rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) & ~(val))
sys/dev/pci/if_rgereg.h
490
uint16_t reg;
sys/dev/pci/if_rgereg.h
946
uint16_t reg;
sys/dev/pci/if_rgereg.h
974
uint16_t reg;
sys/dev/pci/if_rtwn.c
1270
uint16_t reg;
sys/dev/pci/if_rtwn.c
1278
reg = rtwn_pci_read_1(sc, R92C_SYS_FUNC_EN);
sys/dev/pci/if_rtwn.c
1279
reg |= R92C_SYS_FUNC_EN_BB_GLB_RST;
sys/dev/pci/if_rtwn.c
1280
rtwn_pci_write_1(sc, R92C_SYS_FUNC_EN, reg);
sys/dev/pci/if_rtwn.c
1281
reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST;
sys/dev/pci/if_rtwn.c
1282
rtwn_pci_write_1(sc, R92C_SYS_FUNC_EN, reg);
sys/dev/pci/if_rtwn.c
1283
reg = rtwn_pci_read_2(sc, R92C_CR);
sys/dev/pci/if_rtwn.c
1284
reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
sys/dev/pci/if_rtwn.c
1288
rtwn_pci_write_2(sc, R92C_CR, reg);
sys/dev/pci/if_rtwn.c
1304
uint16_t reg;
sys/dev/pci/if_rtwn.c
1339
reg = rtwn_pci_read_2(sc, R92C_CR);
sys/dev/pci/if_rtwn.c
1340
reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
sys/dev/pci/if_rtwn.c
1344
rtwn_pci_write_2(sc, R92C_CR, reg);
sys/dev/pci/if_rtwn.c
1671
uint32_t reg;
sys/dev/pci/if_rtwn.c
1693
reg = rtwn_pci_read_4(sc, R92C_APS_FSMCO);
sys/dev/pci/if_rtwn.c
1694
reg |= (R92C_APS_FSMCO_SOP_ABG |
sys/dev/pci/if_rtwn.c
1697
rtwn_pci_write_4(sc, R92C_APS_FSMCO, reg);
sys/dev/pci/if_rtwn.c
1711
reg = rtwn_pci_read_4(sc, R92C_AFE_XTAL_CTRL);
sys/dev/pci/if_rtwn.c
1712
reg &= (~0x00024800); /* XXX magic from linux */
sys/dev/pci/if_rtwn.c
1713
rtwn_pci_write_4(sc, R92C_AFE_XTAL_CTRL, reg);
sys/dev/pci/if_rtwn.c
1756
reg = rtwn_pci_read_4(sc, R92C_AFE_XTAL_CTRL + 2);
sys/dev/pci/if_rtwn.c
1757
reg &= 0xfd; /* XXX magic from linux */
sys/dev/pci/if_rtwn.c
1758
rtwn_pci_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg);
sys/dev/pci/if_rtwn.c
1764
reg = rtwn_pci_read_1(sc, R92C_GPIO_IO_SEL);
sys/dev/pci/if_rtwn.c
1765
if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) {
sys/dev/pci/if_rtwn.c
1787
reg = rtwn_pci_read_2(sc, R92C_CR);
sys/dev/pci/if_rtwn.c
1788
reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
sys/dev/pci/if_rtwn.c
1792
rtwn_pci_write_2(sc, R92C_CR, reg);
sys/dev/pci/if_rtwn.c
1802
uint32_t reg;
sys/dev/pci/if_rtwn.c
1876
reg = rtwn_pci_read_2(sc, R92C_CR);
sys/dev/pci/if_rtwn.c
1877
reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
sys/dev/pci/if_rtwn.c
1881
rtwn_pci_write_2(sc, R92C_CR, reg);
sys/dev/pci/if_rtwn.c
1890
uint32_t reg;
sys/dev/pci/if_rtwn.c
1965
reg = rtwn_pci_read_2(sc, R92C_CR);
sys/dev/pci/if_rtwn.c
1966
reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
sys/dev/pci/if_rtwn.c
1970
rtwn_pci_write_2(sc, R92C_CR, reg);
sys/dev/pci/if_rtwn.c
1992
uint32_t reg;
sys/dev/pci/if_rtwn.c
2052
reg = rtwn_pci_read_2(sc, R92C_TRXDMA_CTRL);
sys/dev/pci/if_rtwn.c
2053
reg &= ~R92C_TRXDMA_CTRL_QMAP_M;
sys/dev/pci/if_rtwn.c
2054
reg |= trxdma;
sys/dev/pci/if_rtwn.c
2055
rtwn_pci_write_2(sc, R92C_TRXDMA_CTRL, reg);
sys/dev/pci/if_rtwn.c
2094
uint32_t reg;
sys/dev/pci/if_rtwn.c
2097
reg = rtwn_pci_read_4(sc, R92C_MCUFWDL);
sys/dev/pci/if_rtwn.c
2098
reg = RW(reg, R92C_MCUFWDL_PAGE, page);
sys/dev/pci/if_rtwn.c
2099
rtwn_pci_write_4(sc, R92C_MCUFWDL, reg);
sys/dev/pci/if_rtwn.c
2156
if (rtl8188eu_mac[i].reg == R92C_GPIO_MUXCFG)
sys/dev/pci/if_rtwn.c
2158
rtwn_pci_write_1(sc, rtl8188eu_mac[i].reg,
sys/dev/pci/if_rtwn.c
2164
rtwn_pci_write_1(sc, rtl8192cu_mac[i].reg,
sys/dev/pci/if_rtwn.c
2170
rtwn_pci_write_1(sc, rtl8192ce_mac[i].reg,
sys/dev/pci/if_rtwn.c
2180
uint32_t reg;
sys/dev/pci/if_rtwn.c
2225
reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO);
sys/dev/pci/if_rtwn.c
2226
reg = (reg & ~0x00000003) | 0x2;
sys/dev/pci/if_rtwn.c
2227
rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
sys/dev/pci/if_rtwn.c
2229
reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO);
sys/dev/pci/if_rtwn.c
2230
reg = (reg & ~0x00300033) | 0x00200022;
sys/dev/pci/if_rtwn.c
2231
rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
sys/dev/pci/if_rtwn.c
2233
reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING);
sys/dev/pci/if_rtwn.c
2234
reg = (reg & ~0xff000000) | 0x45 << 24;
sys/dev/pci/if_rtwn.c
2235
rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
sys/dev/pci/if_rtwn.c
2237
reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
sys/dev/pci/if_rtwn.c
2238
reg = (reg & ~0x000000ff) | 0x23;
sys/dev/pci/if_rtwn.c
2239
rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
sys/dev/pci/if_rtwn.c
2241
reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
sys/dev/pci/if_rtwn.c
2242
reg = (reg & ~0x00000030) | 1 << 4;
sys/dev/pci/if_rtwn.c
2243
rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
sys/dev/pci/if_rtwn.c
2245
reg = rtwn_bb_read(sc, 0xe74);
sys/dev/pci/if_rtwn.c
2246
reg = (reg & ~0x0c000000) | 2 << 26;
sys/dev/pci/if_rtwn.c
2247
rtwn_bb_write(sc, 0xe74, reg);
sys/dev/pci/if_rtwn.c
2248
reg = rtwn_bb_read(sc, 0xe78);
sys/dev/pci/if_rtwn.c
2249
reg = (reg & ~0x0c000000) | 2 << 26;
sys/dev/pci/if_rtwn.c
2250
rtwn_bb_write(sc, 0xe78, reg);
sys/dev/pci/if_rtwn.c
2251
reg = rtwn_bb_read(sc, 0xe7c);
sys/dev/pci/if_rtwn.c
2252
reg = (reg & ~0x0c000000) | 2 << 26;
sys/dev/pci/if_rtwn.c
2253
rtwn_bb_write(sc, 0xe7c, reg);
sys/dev/pci/if_rtwn.c
2254
reg = rtwn_bb_read(sc, 0xe80);
sys/dev/pci/if_rtwn.c
2255
reg = (reg & ~0x0c000000) | 2 << 26;
sys/dev/pci/if_rtwn.c
2256
rtwn_bb_write(sc, 0xe80, reg);
sys/dev/pci/if_rtwn.c
2257
reg = rtwn_bb_read(sc, 0xe88);
sys/dev/pci/if_rtwn.c
2258
reg = (reg & ~0x0c000000) | 2 << 26;
sys/dev/pci/if_rtwn.c
2259
rtwn_bb_write(sc, 0xe88, reg);
sys/dev/pci/if_se.c
186
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_se.c
187
bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, reg, val)
sys/dev/pci/if_se.c
188
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_se.c
189
bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, reg, val)
sys/dev/pci/if_se.c
190
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_se.c
191
bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, reg, val)
sys/dev/pci/if_se.c
193
#define CSR_READ_4(sc, reg) \
sys/dev/pci/if_se.c
194
bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, reg)
sys/dev/pci/if_se.c
195
#define CSR_READ_2(sc, reg) \
sys/dev/pci/if_se.c
196
bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, reg)
sys/dev/pci/if_se.c
197
#define CSR_READ_1(sc, reg) \
sys/dev/pci/if_se.c
198
bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, reg)
sys/dev/pci/if_se.c
276
pcireg_t reg;
sys/dev/pci/if_se.c
287
reg = pci_conf_read(pa.pa_pc, pa.pa_tag, 0x48);
sys/dev/pci/if_se.c
288
pci_conf_write(pa.pa_pc, pa.pa_tag, 0x48, reg & ~0x02);
sys/dev/pci/if_se.c
308
pci_conf_write(pa.pa_pc, pa.pa_tag, 0x48, reg);
sys/dev/pci/if_se.c
334
se_miibus_readreg(struct device *self, int phy, int reg)
sys/dev/pci/if_se.c
339
ctrl = (phy << GMI_PHY_SHIFT) | (reg << GMI_REG_SHIFT) |
sys/dev/pci/if_se.c
344
sc->sc_dev.dv_xname, reg);
sys/dev/pci/if_se.c
351
se_miibus_writereg(struct device *self, int phy, int reg, int data)
sys/dev/pci/if_se.c
356
ctrl = (phy << GMI_PHY_SHIFT) | (reg << GMI_REG_SHIFT) |
sys/dev/pci/if_se.c
361
sc->sc_dev.dv_xname, reg);
sys/dev/pci/if_sf_pci.c
104
reg = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SF_PCI_MEMBA);
sys/dev/pci/if_sf_pci.c
105
switch (reg) {
sys/dev/pci/if_sf_pci.c
109
reg, 0, &memt, &memh, &memsize, NULL, 0) == 0);
sys/dev/pci/if_sf_pci.c
116
(reg == (PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT)) ?
sys/dev/pci/if_sf_pci.c
97
pcireg_t reg;
sys/dev/pci/if_sis.c
148
#define SIS_SETBIT(sc, reg, x) \
sys/dev/pci/if_sis.c
149
CSR_WRITE_4(sc, reg, \
sys/dev/pci/if_sis.c
150
CSR_READ_4(sc, reg) | (x))
sys/dev/pci/if_sis.c
152
#define SIS_CLRBIT(sc, reg, x) \
sys/dev/pci/if_sis.c
153
CSR_WRITE_4(sc, reg, \
sys/dev/pci/if_sis.c
154
CSR_READ_4(sc, reg) & ~(x))
sys/dev/pci/if_sis.c
310
u_int32_t reg;
sys/dev/pci/if_sis.c
313
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x48);
sys/dev/pci/if_sis.c
314
pci_conf_write(pa->pa_pc, pa->pa_tag, 0x48, reg | 0x40);
sys/dev/pci/if_sis.c
321
pci_conf_write(pa->pa_pc, pa->pa_tag, 0x48, reg & ~0x40);
sys/dev/pci/if_sis.c
546
sis_miibus_readreg(struct device *self, int phy, int reg)
sys/dev/pci/if_sis.c
566
return CSR_READ_4(sc, NS_BMCR + (reg * 4));
sys/dev/pci/if_sis.c
582
(phy << 11) | (reg << 6) | SIS_PHYOP_READ);
sys/dev/pci/if_sis.c
606
frame.mii_regaddr = reg;
sys/dev/pci/if_sis.c
614
sis_miibus_writereg(struct device *self, int phy, int reg, int data)
sys/dev/pci/if_sis.c
622
CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
sys/dev/pci/if_sis.c
639
(reg << 6) | SIS_PHYOP_WRITE);
sys/dev/pci/if_sis.c
654
frame.mii_regaddr = reg;
sys/dev/pci/if_sis.c
724
uint32_t reg;
sys/dev/pci/if_sis.c
727
reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
sys/dev/pci/if_sis.c
728
CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
sys/dev/pci/if_sis.c
730
reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
sys/dev/pci/if_sis.c
731
if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
sys/dev/pci/if_sis.c
734
sc->sc_dev.dv_xname, reg);
sys/dev/pci/if_sisreg.h
474
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_sisreg.h
475
bus_space_write_4(sc->sis_btag, sc->sis_bhandle, reg, val)
sys/dev/pci/if_sisreg.h
477
#define CSR_READ_4(sc, reg) \
sys/dev/pci/if_sisreg.h
478
bus_space_read_4(sc->sis_btag, sc->sis_bhandle, reg)
sys/dev/pci/if_sk.c
1990
while(bhack[i].reg) {
sys/dev/pci/if_sk.c
1992
SK_PHYADDR_BCOM, bhack[i].reg,
sys/dev/pci/if_sk.c
203
sk_win_read_4(struct sk_softc *sc, u_int32_t reg)
sys/dev/pci/if_sk.c
205
return CSR_READ_4(sc, reg);
sys/dev/pci/if_sk.c
2086
u_int16_t reg;
sys/dev/pci/if_sk.c
209
sk_win_read_2(struct sk_softc *sc, u_int32_t reg)
sys/dev/pci/if_sk.c
211
return CSR_READ_2(sc, reg);
sys/dev/pci/if_sk.c
215
sk_win_read_1(struct sk_softc *sc, u_int32_t reg)
sys/dev/pci/if_sk.c
2153
reg = SK_YU_READ_2(sc_if, YUKON_PAR);
sys/dev/pci/if_sk.c
2154
DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
sys/dev/pci/if_sk.c
2157
reg |= YU_PAR_MIB_CLR;
sys/dev/pci/if_sk.c
2158
DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
sys/dev/pci/if_sk.c
2160
SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
sys/dev/pci/if_sk.c
2164
reg &= ~YU_PAR_MIB_CLR;
sys/dev/pci/if_sk.c
2165
SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
sys/dev/pci/if_sk.c
217
return CSR_READ_1(sc, reg);
sys/dev/pci/if_sk.c
2191
reg = sk_win_read_2(sc_if->sk_softc,
sys/dev/pci/if_sk.c
2193
SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
sys/dev/pci/if_sk.c
221
sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x)
sys/dev/pci/if_sk.c
223
CSR_WRITE_4(sc, reg, x);
sys/dev/pci/if_sk.c
227
sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x)
sys/dev/pci/if_sk.c
229
CSR_WRITE_2(sc, reg, x);
sys/dev/pci/if_sk.c
233
sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x)
sys/dev/pci/if_sk.c
235
CSR_WRITE_1(sc, reg, x);
sys/dev/pci/if_sk.c
2382
u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
sys/dev/pci/if_sk.c
2383
reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
sys/dev/pci/if_sk.c
2384
SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
sys/dev/pci/if_sk.c
239
sk_xmac_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_sk.c
249
SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
sys/dev/pci/if_sk.c
270
sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_sk.c
277
SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
sys/dev/pci/if_sk.c
321
sk_marv_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_sk.c
331
phy, reg));
sys/dev/pci/if_sk.c
336
YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
sys/dev/pci/if_sk.c
357
phy, reg, val));
sys/dev/pci/if_sk.c
363
sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_sk.c
369
phy, reg, val));
sys/dev/pci/if_sk.c
373
YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
sys/dev/pci/if_sk.c
420
u_int32_t reg, hashes[2];
sys/dev/pci/if_sk.c
424
reg = SK_XM_READ_4(sc_if, XM_MODE);
sys/dev/pci/if_sk.c
425
reg &= ~(XM_MODE_RX_NOBROAD | XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH |
sys/dev/pci/if_sk.c
432
reg |= XM_MODE_RX_USE_STATION;
sys/dev/pci/if_sk.c
441
reg |= XM_MODE_RX_PROMISC;
sys/dev/pci/if_sk.c
443
reg |= XM_MODE_RX_USE_HASH;
sys/dev/pci/if_sk.c
446
reg |= XM_MODE_RX_USE_HASH;
sys/dev/pci/if_sk.c
466
SK_XM_WRITE_4(sc_if, XM_MODE, reg);
sys/dev/pci/if_skreg.h
106
#define SK_IF_READ_4(sc_if, skip, reg) \
sys/dev/pci/if_skreg.h
107
sk_win_read_4(sc_if->sk_softc, reg + \
sys/dev/pci/if_skreg.h
109
#define SK_IF_READ_2(sc_if, skip, reg) \
sys/dev/pci/if_skreg.h
110
sk_win_read_2(sc_if->sk_softc, reg + \
sys/dev/pci/if_skreg.h
112
#define SK_IF_READ_1(sc_if, skip, reg) \
sys/dev/pci/if_skreg.h
113
sk_win_read_1(sc_if->sk_softc, reg + \
sys/dev/pci/if_skreg.h
116
#define SK_IF_WRITE_4(sc_if, skip, reg, val) \
sys/dev/pci/if_skreg.h
118
reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
sys/dev/pci/if_skreg.h
119
#define SK_IF_WRITE_2(sc_if, skip, reg, val) \
sys/dev/pci/if_skreg.h
121
reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
sys/dev/pci/if_skreg.h
122
#define SK_IF_WRITE_1(sc_if, skip, reg, val) \
sys/dev/pci/if_skreg.h
124
reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
sys/dev/pci/if_skreg.h
1369
#define SK_Y2_PCI_REG(reg) ((reg) + SK_Y2_PCI_BASE)
sys/dev/pci/if_skreg.h
1386
#define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \
sys/dev/pci/if_skreg.h
1390
#define SK_XM_READ_4(sc, reg) \
sys/dev/pci/if_skreg.h
1392
SK_XMAC_REG(sc, reg)) & 0xFFFF) | \
sys/dev/pci/if_skreg.h
1394
SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16))
sys/dev/pci/if_skreg.h
1396
#define SK_XM_WRITE_4(sc, reg, val) \
sys/dev/pci/if_skreg.h
1397
sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \
sys/dev/pci/if_skreg.h
1399
sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \
sys/dev/pci/if_skreg.h
1402
#define SK_XM_READ_4(sc, reg) \
sys/dev/pci/if_skreg.h
1403
sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg))
sys/dev/pci/if_skreg.h
1405
#define SK_XM_WRITE_4(sc, reg, val) \
sys/dev/pci/if_skreg.h
1406
sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val))
sys/dev/pci/if_skreg.h
1409
#define SK_XM_READ_2(sc, reg) \
sys/dev/pci/if_skreg.h
1410
sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg))
sys/dev/pci/if_skreg.h
1412
#define SK_XM_WRITE_2(sc, reg, val) \
sys/dev/pci/if_skreg.h
1413
sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val)
sys/dev/pci/if_skreg.h
1415
#define SK_XM_SETBIT_4(sc, reg, x) \
sys/dev/pci/if_skreg.h
1416
SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x))
sys/dev/pci/if_skreg.h
1418
#define SK_XM_CLRBIT_4(sc, reg, x) \
sys/dev/pci/if_skreg.h
1419
SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x))
sys/dev/pci/if_skreg.h
1421
#define SK_XM_SETBIT_2(sc, reg, x) \
sys/dev/pci/if_skreg.h
1422
SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x))
sys/dev/pci/if_skreg.h
1424
#define SK_XM_CLRBIT_2(sc, reg, x) \
sys/dev/pci/if_skreg.h
1425
SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x))
sys/dev/pci/if_skreg.h
1428
#define SK_YU_REG(sc, reg) \
sys/dev/pci/if_skreg.h
1429
((reg) + SK_MARV1_BASE + \
sys/dev/pci/if_skreg.h
1432
#define SK_YU_READ_4(sc, reg) \
sys/dev/pci/if_skreg.h
1433
sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg)))
sys/dev/pci/if_skreg.h
1435
#define SK_YU_READ_2(sc, reg) \
sys/dev/pci/if_skreg.h
1436
sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg)))
sys/dev/pci/if_skreg.h
1438
#define SK_YU_WRITE_4(sc, reg, val) \
sys/dev/pci/if_skreg.h
1439
sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
sys/dev/pci/if_skreg.h
1441
#define SK_YU_WRITE_2(sc, reg, val) \
sys/dev/pci/if_skreg.h
1442
sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
sys/dev/pci/if_skreg.h
1444
#define SK_YU_SETBIT_4(sc, reg, x) \
sys/dev/pci/if_skreg.h
1445
SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x))
sys/dev/pci/if_skreg.h
1447
#define SK_YU_CLRBIT_4(sc, reg, x) \
sys/dev/pci/if_skreg.h
1448
SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x))
sys/dev/pci/if_skreg.h
1450
#define SK_YU_SETBIT_2(sc, reg, x) \
sys/dev/pci/if_skreg.h
1451
SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x))
sys/dev/pci/if_skreg.h
1453
#define SK_YU_CLRBIT_2(sc, reg, x) \
sys/dev/pci/if_skreg.h
1454
SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x))
sys/dev/pci/if_skreg.h
1517
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_skreg.h
1518
bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
sys/dev/pci/if_skreg.h
1519
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_skreg.h
1520
bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
sys/dev/pci/if_skreg.h
1521
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_skreg.h
1522
bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
sys/dev/pci/if_skreg.h
1524
#define CSR_READ_4(sc, reg) \
sys/dev/pci/if_skreg.h
1525
bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg))
sys/dev/pci/if_skreg.h
1526
#define CSR_READ_2(sc, reg) \
sys/dev/pci/if_skreg.h
1527
bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg))
sys/dev/pci/if_skreg.h
1528
#define CSR_READ_1(sc, reg) \
sys/dev/pci/if_skreg.h
1529
bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg))
sys/dev/pci/if_skreg.h
635
#define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE)
sys/dev/pci/if_skreg.h
76
#define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN)
sys/dev/pci/if_skreg.h
79
#define SK_REG(reg) ((reg) & SK_REG_MASK)
sys/dev/pci/if_skvar.h
163
int reg;
sys/dev/pci/if_ste.c
112
#define STE_SETBIT4(sc, reg, x) \
sys/dev/pci/if_ste.c
113
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
sys/dev/pci/if_ste.c
115
#define STE_CLRBIT4(sc, reg, x) \
sys/dev/pci/if_ste.c
116
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
sys/dev/pci/if_ste.c
118
#define STE_SETBIT2(sc, reg, x) \
sys/dev/pci/if_ste.c
119
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)
sys/dev/pci/if_ste.c
121
#define STE_CLRBIT2(sc, reg, x) \
sys/dev/pci/if_ste.c
122
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)
sys/dev/pci/if_ste.c
124
#define STE_SETBIT1(sc, reg, x) \
sys/dev/pci/if_ste.c
125
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
sys/dev/pci/if_ste.c
127
#define STE_CLRBIT1(sc, reg, x) \
sys/dev/pci/if_ste.c
128
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
sys/dev/pci/if_ste.c
327
ste_miibus_readreg(struct device *self, int phy, int reg)
sys/dev/pci/if_ste.c
338
frame.mii_regaddr = reg;
sys/dev/pci/if_ste.c
345
ste_miibus_writereg(struct device *self, int phy, int reg, int data)
sys/dev/pci/if_ste.c
353
frame.mii_regaddr = reg;
sys/dev/pci/if_stereg.h
446
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_stereg.h
447
bus_space_write_4(sc->ste_btag, sc->ste_bhandle, reg, val)
sys/dev/pci/if_stereg.h
448
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_stereg.h
449
bus_space_write_2(sc->ste_btag, sc->ste_bhandle, reg, val)
sys/dev/pci/if_stereg.h
450
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_stereg.h
451
bus_space_write_1(sc->ste_btag, sc->ste_bhandle, reg, val)
sys/dev/pci/if_stereg.h
453
#define CSR_READ_4(sc, reg) \
sys/dev/pci/if_stereg.h
454
bus_space_read_4(sc->ste_btag, sc->ste_bhandle, reg)
sys/dev/pci/if_stereg.h
455
#define CSR_READ_2(sc, reg) \
sys/dev/pci/if_stereg.h
456
bus_space_read_2(sc->ste_btag, sc->ste_bhandle, reg)
sys/dev/pci/if_stereg.h
457
#define CSR_READ_1(sc, reg) \
sys/dev/pci/if_stereg.h
458
bus_space_read_1(sc->ste_btag, sc->ste_bhandle, reg)
sys/dev/pci/if_stge.c
1526
stge_mii_readreg(struct device *self, int phy, int reg)
sys/dev/pci/if_stge.c
1529
return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg));
sys/dev/pci/if_stge.c
1538
stge_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/pci/if_stge.c
1541
mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val);
sys/dev/pci/if_stgereg.h
47
#define CSR_WRITE_4(_sc, reg, val) \
sys/dev/pci/if_stgereg.h
48
bus_space_write_4((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
sys/dev/pci/if_stgereg.h
49
#define CSR_WRITE_2(_sc, reg, val) \
sys/dev/pci/if_stgereg.h
50
bus_space_write_2((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
sys/dev/pci/if_stgereg.h
51
#define CSR_WRITE_1(_sc, reg, val) \
sys/dev/pci/if_stgereg.h
52
bus_space_write_1((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
sys/dev/pci/if_stgereg.h
54
#define CSR_READ_4(_sc, reg) \
sys/dev/pci/if_stgereg.h
55
bus_space_read_4((_sc)->sc_st, (_sc)->sc_sh, (reg))
sys/dev/pci/if_stgereg.h
56
#define CSR_READ_2(_sc, reg) \
sys/dev/pci/if_stgereg.h
57
bus_space_read_2((_sc)->sc_st, (_sc)->sc_sh, (reg))
sys/dev/pci/if_stgereg.h
58
#define CSR_READ_1(_sc, reg) \
sys/dev/pci/if_stgereg.h
59
bus_space_read_1((_sc)->sc_st, (_sc)->sc_sh, (reg))
sys/dev/pci/if_tl.c
292
tl_dio_read8(struct tl_softc *sc, int reg)
sys/dev/pci/if_tl.c
294
CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
sys/dev/pci/if_tl.c
295
return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
sys/dev/pci/if_tl.c
299
tl_dio_read16(struct tl_softc *sc, int reg)
sys/dev/pci/if_tl.c
301
CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
sys/dev/pci/if_tl.c
302
return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
sys/dev/pci/if_tl.c
306
tl_dio_read32(struct tl_softc *sc, int reg)
sys/dev/pci/if_tl.c
308
CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
sys/dev/pci/if_tl.c
309
return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
sys/dev/pci/if_tl.c
313
tl_dio_write8(struct tl_softc *sc, int reg, int val)
sys/dev/pci/if_tl.c
315
CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
sys/dev/pci/if_tl.c
316
CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
sys/dev/pci/if_tl.c
320
tl_dio_write16(struct tl_softc *sc, int reg, int val)
sys/dev/pci/if_tl.c
322
CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
sys/dev/pci/if_tl.c
323
CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
sys/dev/pci/if_tl.c
327
tl_dio_write32(struct tl_softc *sc, int reg, int val)
sys/dev/pci/if_tl.c
329
CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
sys/dev/pci/if_tl.c
330
CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
sys/dev/pci/if_tl.c
334
tl_dio_setbit(struct tl_softc *sc, int reg, int bit)
sys/dev/pci/if_tl.c
338
CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
sys/dev/pci/if_tl.c
339
f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
sys/dev/pci/if_tl.c
341
CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
sys/dev/pci/if_tl.c
345
tl_dio_clrbit(struct tl_softc *sc, int reg, int bit)
sys/dev/pci/if_tl.c
349
CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
sys/dev/pci/if_tl.c
350
f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
sys/dev/pci/if_tl.c
352
CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
sys/dev/pci/if_tl.c
356
tl_dio_setbit16(struct tl_softc *sc, int reg, int bit)
sys/dev/pci/if_tl.c
360
CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
sys/dev/pci/if_tl.c
361
f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
sys/dev/pci/if_tl.c
363
CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
sys/dev/pci/if_tl.c
367
tl_dio_clrbit16(struct tl_softc *sc, int reg, int bit)
sys/dev/pci/if_tl.c
371
CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
sys/dev/pci/if_tl.c
372
f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
sys/dev/pci/if_tl.c
374
CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
sys/dev/pci/if_tl.c
677
tl_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_tl.c
685
frame.mii_regaddr = reg;
sys/dev/pci/if_tl.c
692
tl_miibus_writereg(struct device *dev, int phy, int reg, int data)
sys/dev/pci/if_tl.c
700
frame.mii_regaddr = reg;
sys/dev/pci/if_tlreg.h
500
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_tlreg.h
501
bus_space_write_4(sc->tl_btag, sc->tl_bhandle, reg, val)
sys/dev/pci/if_tlreg.h
502
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_tlreg.h
503
bus_space_write_2(sc->tl_btag, sc->tl_bhandle, reg, val)
sys/dev/pci/if_tlreg.h
504
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_tlreg.h
505
bus_space_write_1(sc->tl_btag, sc->tl_bhandle, reg, val)
sys/dev/pci/if_tlreg.h
507
#define CSR_READ_4(sc, reg) \
sys/dev/pci/if_tlreg.h
508
bus_space_read_4(sc->tl_btag, sc->tl_bhandle, reg)
sys/dev/pci/if_tlreg.h
509
#define CSR_READ_2(sc, reg) \
sys/dev/pci/if_tlreg.h
510
bus_space_read_2(sc->tl_btag, sc->tl_bhandle, reg)
sys/dev/pci/if_tlreg.h
511
#define CSR_READ_1(sc, reg) \
sys/dev/pci/if_tlreg.h
512
bus_space_read_1(sc->tl_btag, sc->tl_bhandle, reg)
sys/dev/pci/if_txpreg.h
614
#define WRITE_REG(sc,reg,val) \
sys/dev/pci/if_txpreg.h
615
bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, reg, val)
sys/dev/pci/if_txpreg.h
616
#define READ_REG(sc,reg) \
sys/dev/pci/if_txpreg.h
617
bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, reg)
sys/dev/pci/if_vge.c
299
vge_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_vge.c
313
CSR_WRITE_1(sc, VGE_MIIADDR, reg);
sys/dev/pci/if_vge.c
337
vge_miibus_writereg(struct device *dev, int phy, int reg, int data)
sys/dev/pci/if_vge.c
349
CSR_WRITE_1(sc, VGE_MIIADDR, reg);
sys/dev/pci/if_vgevar.h
100
bus_space_write_4(sc->vge_btag, sc->vge_bhandle, reg, val)
sys/dev/pci/if_vgevar.h
101
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_vgevar.h
102
bus_space_write_2(sc->vge_btag, sc->vge_bhandle, reg, val)
sys/dev/pci/if_vgevar.h
103
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_vgevar.h
104
bus_space_write_1(sc->vge_btag, sc->vge_bhandle, reg, val)
sys/dev/pci/if_vgevar.h
106
#define CSR_READ_4(sc, reg) \
sys/dev/pci/if_vgevar.h
107
bus_space_read_4(sc->vge_btag, sc->vge_bhandle, reg)
sys/dev/pci/if_vgevar.h
108
#define CSR_READ_2(sc, reg) \
sys/dev/pci/if_vgevar.h
109
bus_space_read_2(sc->vge_btag, sc->vge_bhandle, reg)
sys/dev/pci/if_vgevar.h
110
#define CSR_READ_1(sc, reg) \
sys/dev/pci/if_vgevar.h
111
bus_space_read_1(sc->vge_btag, sc->vge_bhandle, reg)
sys/dev/pci/if_vgevar.h
113
#define CSR_SETBIT_1(sc, reg, x) \
sys/dev/pci/if_vgevar.h
114
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
sys/dev/pci/if_vgevar.h
115
#define CSR_SETBIT_2(sc, reg, x) \
sys/dev/pci/if_vgevar.h
116
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
sys/dev/pci/if_vgevar.h
117
#define CSR_SETBIT_4(sc, reg, x) \
sys/dev/pci/if_vgevar.h
118
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
sys/dev/pci/if_vgevar.h
120
#define CSR_CLRBIT_1(sc, reg, x) \
sys/dev/pci/if_vgevar.h
121
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
sys/dev/pci/if_vgevar.h
122
#define CSR_CLRBIT_2(sc, reg, x) \
sys/dev/pci/if_vgevar.h
123
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
sys/dev/pci/if_vgevar.h
124
#define CSR_CLRBIT_4(sc, reg, x) \
sys/dev/pci/if_vgevar.h
125
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
sys/dev/pci/if_vgevar.h
99
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_vic.c
973
u_int32_t reg;
sys/dev/pci/if_vic.c
976
reg = (sc->sc_cap & VIC_CMD_HWCAP_VPROM) ? VIC_VPROM : VIC_LLADDR;
sys/dev/pci/if_vic.c
978
bus_space_barrier(sc->sc_iot, sc->sc_ioh, reg, ETHER_ADDR_LEN,
sys/dev/pci/if_vic.c
980
bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, reg, sc->sc_lladdr,
sys/dev/pci/if_vic.c
984
if (reg == VIC_VPROM)
sys/dev/pci/if_vmx.c
181
#define READ_BAR0(sc, reg) bus_space_read_4((sc)->sc_iot0, (sc)->sc_ioh0, reg)
sys/dev/pci/if_vmx.c
182
#define READ_BAR1(sc, reg) bus_space_read_4((sc)->sc_iot1, (sc)->sc_ioh1, reg)
sys/dev/pci/if_vmx.c
183
#define WRITE_BAR0(sc, reg, val) \
sys/dev/pci/if_vmx.c
184
bus_space_write_4((sc)->sc_iot0, (sc)->sc_ioh0, reg, val)
sys/dev/pci/if_vmx.c
185
#define WRITE_BAR1(sc, reg, val) \
sys/dev/pci/if_vmx.c
186
bus_space_write_4((sc)->sc_iot1, (sc)->sc_ioh1, reg, val)
sys/dev/pci/if_vr.c
177
#define VR_SETBIT(sc, reg, x) \
sys/dev/pci/if_vr.c
178
CSR_WRITE_1(sc, reg, \
sys/dev/pci/if_vr.c
179
CSR_READ_1(sc, reg) | (x))
sys/dev/pci/if_vr.c
181
#define VR_CLRBIT(sc, reg, x) \
sys/dev/pci/if_vr.c
182
CSR_WRITE_1(sc, reg, \
sys/dev/pci/if_vr.c
183
CSR_READ_1(sc, reg) & ~(x))
sys/dev/pci/if_vr.c
185
#define VR_SETBIT16(sc, reg, x) \
sys/dev/pci/if_vr.c
186
CSR_WRITE_2(sc, reg, \
sys/dev/pci/if_vr.c
187
CSR_READ_2(sc, reg) | (x))
sys/dev/pci/if_vr.c
189
#define VR_CLRBIT16(sc, reg, x) \
sys/dev/pci/if_vr.c
190
CSR_WRITE_2(sc, reg, \
sys/dev/pci/if_vr.c
191
CSR_READ_2(sc, reg) & ~(x))
sys/dev/pci/if_vr.c
193
#define VR_SETBIT32(sc, reg, x) \
sys/dev/pci/if_vr.c
194
CSR_WRITE_4(sc, reg, \
sys/dev/pci/if_vr.c
195
CSR_READ_4(sc, reg) | (x))
sys/dev/pci/if_vr.c
197
#define VR_CLRBIT32(sc, reg, x) \
sys/dev/pci/if_vr.c
198
CSR_WRITE_4(sc, reg, \
sys/dev/pci/if_vr.c
199
CSR_READ_4(sc, reg) & ~(x))
sys/dev/pci/if_vr.c
272
vr_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_vr.c
289
frame.mii_regaddr = reg;
sys/dev/pci/if_vr.c
296
vr_miibus_writereg(struct device *dev, int phy, int reg, int data)
sys/dev/pci/if_vr.c
313
frame.mii_regaddr = reg;
sys/dev/pci/if_vrreg.h
543
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_vrreg.h
544
bus_space_write_4(sc->vr_btag, sc->vr_bhandle, reg, val)
sys/dev/pci/if_vrreg.h
545
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_vrreg.h
546
bus_space_write_2(sc->vr_btag, sc->vr_bhandle, reg, val)
sys/dev/pci/if_vrreg.h
547
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_vrreg.h
548
bus_space_write_1(sc->vr_btag, sc->vr_bhandle, reg, val)
sys/dev/pci/if_vrreg.h
550
#define CSR_READ_4(sc, reg) \
sys/dev/pci/if_vrreg.h
551
bus_space_read_4(sc->vr_btag, sc->vr_bhandle, reg)
sys/dev/pci/if_vrreg.h
552
#define CSR_READ_2(sc, reg) \
sys/dev/pci/if_vrreg.h
553
bus_space_read_2(sc->vr_btag, sc->vr_bhandle, reg)
sys/dev/pci/if_vrreg.h
554
#define CSR_READ_1(sc, reg) \
sys/dev/pci/if_vrreg.h
555
bus_space_read_1(sc->vr_btag, sc->vr_bhandle, reg)
sys/dev/pci/if_vte.c
114
vte_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_vte.c
120
(phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT));
sys/dev/pci/if_vte.c
129
sc->sc_dev.dv_xname, phy, reg);
sys/dev/pci/if_vte.c
137
vte_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/pci/if_vte.c
144
(phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT));
sys/dev/pci/if_vte.c
153
sc->sc_dev.dv_xname, phy, reg);
sys/dev/pci/if_vtereg.h
450
#define CSR_WRITE_2(_sc, reg, val) \
sys/dev/pci/if_vtereg.h
451
bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
sys/dev/pci/if_vtereg.h
452
#define CSR_READ_2(_sc, reg) \
sys/dev/pci/if_vtereg.h
453
bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
sys/dev/pci/if_wb.c
162
#define WB_SETBIT(sc, reg, x) \
sys/dev/pci/if_wb.c
163
CSR_WRITE_4(sc, reg, \
sys/dev/pci/if_wb.c
164
CSR_READ_4(sc, reg) | x)
sys/dev/pci/if_wb.c
166
#define WB_CLRBIT(sc, reg, x) \
sys/dev/pci/if_wb.c
167
CSR_WRITE_4(sc, reg, \
sys/dev/pci/if_wb.c
168
CSR_READ_4(sc, reg) & ~x)
sys/dev/pci/if_wb.c
452
wb_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/pci/if_wb.c
460
frame.mii_regaddr = reg;
sys/dev/pci/if_wb.c
467
wb_miibus_writereg(struct device *dev, int phy, int reg, int data)
sys/dev/pci/if_wb.c
475
frame.mii_regaddr = reg;
sys/dev/pci/if_wbreg.h
385
#define CSR_WRITE_4(sc, reg, val) \
sys/dev/pci/if_wbreg.h
386
bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val)
sys/dev/pci/if_wbreg.h
387
#define CSR_WRITE_2(sc, reg, val) \
sys/dev/pci/if_wbreg.h
388
bus_space_write_2(sc->wb_btag, sc->wb_bhandle, reg, val)
sys/dev/pci/if_wbreg.h
389
#define CSR_WRITE_1(sc, reg, val) \
sys/dev/pci/if_wbreg.h
390
bus_space_write_1(sc->wb_btag, sc->wb_bhandle, reg, val)
sys/dev/pci/if_wbreg.h
392
#define CSR_READ_4(sc, reg) \
sys/dev/pci/if_wbreg.h
393
bus_space_read_4(sc->wb_btag, sc->wb_bhandle, reg)
sys/dev/pci/if_wbreg.h
394
#define CSR_READ_2(sc, reg) \
sys/dev/pci/if_wbreg.h
395
bus_space_read_2(sc->wb_btag, sc->wb_bhandle, reg)
sys/dev/pci/if_wbreg.h
396
#define CSR_READ_1(sc, reg) \
sys/dev/pci/if_wbreg.h
397
bus_space_read_1(sc->wb_btag, sc->wb_bhandle, reg)
sys/dev/pci/if_wpi.c
180
pcireg_t memtype, reg;
sys/dev/pci/if_wpi.c
199
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);
sys/dev/pci/if_wpi.c
200
reg &= ~0xff00;
sys/dev/pci/if_wpi.c
201
pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg);
sys/dev/pci/if_wpi.c
2355
pcireg_t reg;
sys/dev/pci/if_wpi.c
2368
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
sys/dev/pci/if_wpi.c
2370
if (!(reg & PCI_PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */
sys/dev/pci/if_wpi.c
3062
pcireg_t reg;
sys/dev/pci/if_wpi.c
3066
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_CLASS_REG);
sys/dev/pci/if_wpi.c
3067
rev = PCI_REVISION(reg);
sys/dev/pci/if_wpi.c
406
pcireg_t reg;
sys/dev/pci/if_wpi.c
409
reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);
sys/dev/pci/if_wpi.c
410
reg &= ~0xff00;
sys/dev/pci/if_wpi.c
411
pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg);
sys/dev/pci/if_wpireg.h
818
#define WPI_READ(sc, reg) \
sys/dev/pci/if_wpireg.h
819
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
sys/dev/pci/if_wpireg.h
821
#define WPI_WRITE(sc, reg, val) \
sys/dev/pci/if_wpireg.h
822
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
sys/dev/pci/if_wpireg.h
828
#define WPI_SETBITS(sc, reg, mask) \
sys/dev/pci/if_wpireg.h
829
WPI_WRITE(sc, reg, WPI_READ(sc, reg) | (mask))
sys/dev/pci/if_wpireg.h
831
#define WPI_CLRBITS(sc, reg, mask) \
sys/dev/pci/if_wpireg.h
832
WPI_WRITE(sc, reg, WPI_READ(sc, reg) & ~(mask))
sys/dev/pci/if_xge.c
713
uint64_t reg;
sys/dev/pci/if_xge.c
718
reg = PIF_RCSR(ADAPTER_STATUS);
sys/dev/pci/if_xge.c
719
if ((reg & (RMAC_REMOTE_FAULT|RMAC_LOCAL_FAULT)) == 0)
sys/dev/pci/igc_defines.h
1150
#define GG82563_REG(page, reg) \
sys/dev/pci/igc_defines.h
1151
(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
sys/dev/pci/igc_i225.c
867
uint32_t i, reg;
sys/dev/pci/igc_i225.c
873
reg = IGC_READ_REG(hw, IGC_EECD);
sys/dev/pci/igc_i225.c
874
if (reg & IGC_EECD_FLUDONE_I225) {
sys/dev/pci/igc_nvm.c
107
uint32_t i, reg = 0;
sys/dev/pci/igc_nvm.c
113
reg = IGC_READ_REG(hw, IGC_EERD);
sys/dev/pci/igc_nvm.c
115
reg = IGC_READ_REG(hw, IGC_EEWR);
sys/dev/pci/igc_nvm.c
117
if (reg & IGC_NVM_RW_REG_DONE)
sys/dev/pci/ips.c
1867
u_int32_t reg;
sys/dev/pci/ips.c
1871
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IPS_REG_CCC);
sys/dev/pci/ips.c
1872
if ((reg & IPS_REG_CCC_SEM) == 0)
sys/dev/pci/ips.c
1894
u_int8_t reg;
sys/dev/pci/ips.c
1896
reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, IPS_REG_HIS);
sys/dev/pci/ips.c
1897
bus_space_write_1(sc->sc_iot, sc->sc_ioh, IPS_REG_HIS, reg);
sys/dev/pci/ips.c
1898
if (reg != 0xff && (reg & IPS_REG_HIS_SCE))
sys/dev/pci/ips.c
1937
u_int32_t reg;
sys/dev/pci/ips.c
1939
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IPS_REG_OIM);
sys/dev/pci/ips.c
1940
reg &= ~IPS_REG_OIM_DS;
sys/dev/pci/ips.c
1941
bus_space_write_4(sc->sc_iot, sc->sc_ioh, IPS_REG_OIM, reg);
sys/dev/pci/ips.c
1954
u_int32_t reg;
sys/dev/pci/ips.c
1956
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IPS_REG_OQP);
sys/dev/pci/ips.c
1957
DPRINTF(IPS_D_XFER, ("%s: status 0x%08x\n", sc->sc_dev.dv_xname, reg));
sys/dev/pci/ips.c
1959
return (reg);
sys/dev/pci/ixgb_ee.h
105
uint16_t ixgb_read_eeprom(struct ixgb_hw *hw, uint16_t reg);
sys/dev/pci/ixgb_ee.h
111
void ixgb_write_eeprom(struct ixgb_hw *hw, uint16_t reg, uint16_t data);
sys/dev/pci/ixgbe.c
1306
uint32_t reg;
sys/dev/pci/ixgbe.c
1313
reg = IXGBE_READ_REG(hw, IXGBE_EERD);
sys/dev/pci/ixgbe.c
1315
reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
sys/dev/pci/ixgbe.c
1317
if (reg & IXGBE_EEPROM_RW_REG_DONE) {
sys/dev/pci/ixgbe.c
2268
uint32_t reg;
sys/dev/pci/ixgbe.c
2380
reg = (uint32_t)hw->fc.pause_time * 0x00010001;
sys/dev/pci/ixgbe.c
2382
IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
sys/dev/pci/ixgbe.c
275
uint32_t reg = 0, reg_bp = 0;
sys/dev/pci/ixgbe.c
312
reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
sys/dev/pci/ixgbe.c
336
reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
sys/dev/pci/ixgbe.c
348
reg |= IXGBE_PCS1GANA_ASM_PAUSE;
sys/dev/pci/ixgbe.c
349
reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
sys/dev/pci/ixgbe.c
370
reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
sys/dev/pci/ixgbe.c
390
IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
sys/dev/pci/ixgbe.c
391
reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
sys/dev/pci/ixgbe.c
395
reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
sys/dev/pci/ixgbe.c
397
IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
sys/dev/pci/ixgbe.c
398
DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
sys/dev/pci/ixgbe.c
417
DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
sys/dev/pci/ixgbe.c
790
uint32_t reg;
sys/dev/pci/ixgbe.c
795
reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
sys/dev/pci/ixgbe.c
796
bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
sys/dev/pci/ixgbe.c
800
reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
sys/dev/pci/ixgbe.c
801
if (reg & IXGBE_FACTPS_LFS)
sys/dev/pci/ixgbe.h
149
#define IXGBE_READ_REG(a, reg) \
sys/dev/pci/ixgbe.h
151
((struct ixgbe_osdep *)(a)->back)->os_memh, reg)
sys/dev/pci/ixgbe.h
152
#define IXGBE_WRITE_REG(a, reg, value) \
sys/dev/pci/ixgbe.h
154
((struct ixgbe_osdep *)(a)->back)->os_memh, reg, value)
sys/dev/pci/ixgbe.h
155
#define IXGBE_READ_REG_ARRAY(a, reg, offset) \
sys/dev/pci/ixgbe.h
157
((struct ixgbe_osdep *)(a)->back)->os_memh, (reg + ((offset) << 2)))
sys/dev/pci/ixgbe.h
158
#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) \
sys/dev/pci/ixgbe.h
160
((struct ixgbe_osdep *)(a)->back)->os_memh, (reg + ((offset) << 2)), value)
sys/dev/pci/ixgbe.h
345
int32_t ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, uint8_t addr, uint16_t reg,
sys/dev/pci/ixgbe.h
347
int32_t ixgbe_read_i2c_combined_generic(struct ixgbe_hw *, uint8_t addr, uint16_t reg,
sys/dev/pci/ixgbe.h
350
uint16_t reg, uint16_t *val);
sys/dev/pci/ixgbe.h
351
int32_t ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, uint8_t addr, uint16_t reg,
sys/dev/pci/ixgbe.h
353
int32_t ixgbe_write_i2c_combined_generic(struct ixgbe_hw *, uint8_t addr, uint16_t reg,
sys/dev/pci/ixgbe.h
356
uint16_t reg, uint16_t val);
sys/dev/pci/ixgbe_82598.c
1083
int32_t ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val)
sys/dev/pci/ixgbe_82598.c
1090
IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
sys/dev/pci/ixgbe_82598.c
1107
int32_t ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t val)
sys/dev/pci/ixgbe_82598.c
1113
atlas_ctl = (reg << 8) | val;
sys/dev/pci/ixgbe_82598.c
421
uint32_t reg;
sys/dev/pci/ixgbe_82598.c
546
reg = (uint32_t)hw->fc.pause_time * 0x00010001;
sys/dev/pci/ixgbe_82598.c
548
IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
sys/dev/pci/ixgbe_82598.c
74
int32_t ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val);
sys/dev/pci/ixgbe_82598.c
75
int32_t ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t val);
sys/dev/pci/ixgbe_82599.c
1213
int32_t ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg,
sys/dev/pci/ixgbe_82599.c
1221
(reg << 8));
sys/dev/pci/ixgbe_82599.c
1238
int32_t ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg,
sys/dev/pci/ixgbe_82599.c
1245
core_ctl = (reg << 8) | val;
sys/dev/pci/ixgbe_82599.c
69
int32_t ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg,
sys/dev/pci/ixgbe_82599.c
71
int32_t ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg,
sys/dev/pci/ixgbe_phy.c
114
uint16_t reg, uint16_t *val,
sys/dev/pci/ixgbe_phy.c
126
reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
sys/dev/pci/ixgbe_phy.c
127
csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
sys/dev/pci/ixgbe_phy.c
140
if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
sys/dev/pci/ixgbe_phy.c
192
uint16_t reg, uint16_t *val)
sys/dev/pci/ixgbe_phy.c
194
return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE);
sys/dev/pci/ixgbe_phy.c
207
uint16_t reg, uint16_t *val)
sys/dev/pci/ixgbe_phy.c
209
return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE);
sys/dev/pci/ixgbe_phy.c
224
uint16_t reg, uint16_t val, bool lock)
sys/dev/pci/ixgbe_phy.c
232
reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
sys/dev/pci/ixgbe_phy.c
233
csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
sys/dev/pci/ixgbe_phy.c
248
if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
sys/dev/pci/ixgbe_phy.c
2731
uint16_t reg;
sys/dev/pci/ixgbe_phy.c
2738
®);
sys/dev/pci/ixgbe_phy.c
2743
reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
sys/dev/pci/ixgbe_phy.c
2747
reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
sys/dev/pci/ixgbe_phy.c
2752
reg);
sys/dev/pci/ixgbe_phy.c
288
uint8_t addr, uint16_t reg, uint16_t val)
sys/dev/pci/ixgbe_phy.c
290
return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE);
sys/dev/pci/ixgbe_phy.c
304
uint8_t addr, uint16_t reg, uint16_t val)
sys/dev/pci/ixgbe_phy.c
306
return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE);
sys/dev/pci/ixgbe_type.h
4009
int32_t (*read_i2c_combined)(struct ixgbe_hw *, uint8_t addr, uint16_t reg, uint16_t *val);
sys/dev/pci/ixgbe_type.h
4010
int32_t (*write_i2c_combined)(struct ixgbe_hw *, uint8_t addr, uint16_t reg, uint16_t val);
sys/dev/pci/ixgbe_type.h
4011
int32_t (*read_i2c_combined_unlocked)(struct ixgbe_hw *, uint8_t addr, uint16_t reg,
sys/dev/pci/ixgbe_type.h
4013
int32_t (*write_i2c_combined_unlocked)(struct ixgbe_hw *, uint8_t addr, uint16_t reg,
sys/dev/pci/ixgbe_type.h
4027
int32_t (*read_link)(struct ixgbe_hw *, uint8_t addr, uint16_t reg, uint16_t *val);
sys/dev/pci/ixgbe_type.h
4028
int32_t (*read_link_unlocked)(struct ixgbe_hw *, uint8_t addr, uint16_t reg,
sys/dev/pci/ixgbe_type.h
4030
int32_t (*write_link)(struct ixgbe_hw *, uint8_t addr, uint16_t reg, uint16_t val);
sys/dev/pci/ixgbe_type.h
4031
int32_t (*write_link_unlocked)(struct ixgbe_hw *, uint8_t addr, uint16_t reg,
sys/dev/pci/ixgbe_x540.c
662
uint32_t reg;
sys/dev/pci/ixgbe_x540.c
668
reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
sys/dev/pci/ixgbe_x540.c
669
if (reg & IXGBE_EEC_FLUDONE) {
sys/dev/pci/ixgbe_x550.c
1781
uint16_t reg;
sys/dev/pci/ixgbe_x550.c
1788
®);
sys/dev/pci/ixgbe_x550.c
1791
!(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
sys/dev/pci/ixgbe_x550.c
1797
®);
sys/dev/pci/ixgbe_x550.c
1800
!(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
sys/dev/pci/ixgbe_x550.c
1807
®);
sys/dev/pci/ixgbe_x550.c
1813
if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
sys/dev/pci/ixgbe_x550.c
1817
} else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
sys/dev/pci/ixgbe_x550.c
1821
®);
sys/dev/pci/ixgbe_x550.c
1827
if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
sys/dev/pci/ixgbe_x550.c
1836
IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
sys/dev/pci/ixgbe_x550.c
1839
!(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
sys/dev/pci/ixgbe_x550.c
1844
IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
sys/dev/pci/ixgbe_x550.c
185
int32_t ixgbe_read_cs4227(struct ixgbe_hw *hw, uint16_t reg, uint16_t *value)
sys/dev/pci/ixgbe_x550.c
1850
if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
sys/dev/pci/ixgbe_x550.c
1868
uint16_t reg;
sys/dev/pci/ixgbe_x550.c
187
return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
sys/dev/pci/ixgbe_x550.c
1887
IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
sys/dev/pci/ixgbe_x550.c
1892
reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
sys/dev/pci/ixgbe_x550.c
1896
IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
sys/dev/pci/ixgbe_x550.c
1905
®);
sys/dev/pci/ixgbe_x550.c
1910
reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
sys/dev/pci/ixgbe_x550.c
1915
reg);
sys/dev/pci/ixgbe_x550.c
1923
®);
sys/dev/pci/ixgbe_x550.c
1928
reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
sys/dev/pci/ixgbe_x550.c
1933
reg);
sys/dev/pci/ixgbe_x550.c
1941
®);
sys/dev/pci/ixgbe_x550.c
1946
reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
sys/dev/pci/ixgbe_x550.c
1950
reg);
sys/dev/pci/ixgbe_x550.c
198
int32_t ixgbe_write_cs4227(struct ixgbe_hw *hw, uint16_t reg, uint16_t value)
sys/dev/pci/ixgbe_x550.c
200
return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
sys/dev/pci/ixgbe_x550.c
211
int32_t ixgbe_read_pe(struct ixgbe_hw *hw, uint8_t reg, uint8_t *value)
sys/dev/pci/ixgbe_x550.c
216
status = hw->phy.ops.read_i2c_byte_unlocked(hw, reg, IXGBE_PE,
sys/dev/pci/ixgbe_x550.c
232
int32_t ixgbe_write_pe(struct ixgbe_hw *hw, uint8_t reg, uint8_t value)
sys/dev/pci/ixgbe_x550.c
237
status = hw->phy.ops.write_i2c_byte_unlocked(hw, reg, IXGBE_PE,
sys/dev/pci/ixgbe_x550.c
2381
uint16_t reg;
sys/dev/pci/ixgbe_x550.c
2386
®);
sys/dev/pci/ixgbe_x550.c
2394
if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
sys/dev/pci/ixgbe_x550.c
2398
®);
sys/dev/pci/ixgbe_x550.c
2403
reg &= ~IXGBE_MDIO_POWER_UP_STALL;
sys/dev/pci/ixgbe_x550.c
2408
reg);
sys/dev/pci/ixgbe_x550.c
257
uint8_t reg;
sys/dev/pci/ixgbe_x550.c
260
status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
sys/dev/pci/ixgbe_x550.c
263
reg |= IXGBE_PE_BIT1;
sys/dev/pci/ixgbe_x550.c
264
status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
sys/dev/pci/ixgbe_x550.c
268
status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
sys/dev/pci/ixgbe_x550.c
271
reg &= ~IXGBE_PE_BIT1;
sys/dev/pci/ixgbe_x550.c
272
status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
sys/dev/pci/ixgbe_x550.c
276
status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
sys/dev/pci/ixgbe_x550.c
279
reg &= ~IXGBE_PE_BIT1;
sys/dev/pci/ixgbe_x550.c
280
status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
sys/dev/pci/ixgbe_x550.c
286
status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
sys/dev/pci/ixgbe_x550.c
289
reg |= IXGBE_PE_BIT1;
sys/dev/pci/ixgbe_x550.c
290
status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
sys/dev/pci/ixgbe_x550.c
3024
uint32_t reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
sys/dev/pci/ixgbe_x550.c
3026
uint32_t value = IXGBE_READ_REG(hw, reg);
sys/dev/pci/ixgbe_x550.c
883
uint32_t reg;
sys/dev/pci/ixgbe_x550.c
888
reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
sys/dev/pci/ixgbe_x550.c
889
reg &= ~IXGBE_DMACR_DMAC_EN;
sys/dev/pci/ixgbe_x550.c
890
IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
sys/dev/pci/ixgbe_x550.c
899
reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
sys/dev/pci/ixgbe_x550.c
902
reg &= ~IXGBE_DMACR_DMACWT_MASK;
sys/dev/pci/ixgbe_x550.c
903
reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
sys/dev/pci/ixgbe_x550.c
905
reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
sys/dev/pci/ixgbe_x550.c
906
reg |= IXGBE_DMACR_EN_MNG_IND;
sys/dev/pci/ixgbe_x550.c
909
reg |= IXGBE_DMACR_DMAC_EN;
sys/dev/pci/ixgbe_x550.c
910
IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
sys/dev/pci/ixgbe_x550.c
925
uint32_t tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
sys/dev/pci/ixgbe_x550.c
948
reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
sys/dev/pci/ixgbe_x550.c
949
reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
sys/dev/pci/ixgbe_x550.c
964
reg |= (rx_pb_size > maxframe_size_kb) ?
sys/dev/pci/ixgbe_x550.c
967
IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
sys/dev/pci/ixgbe_x550.c
980
uint32_t reg;
sys/dev/pci/ixgbe_x550.c
985
reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
sys/dev/pci/ixgbe_x550.c
986
reg &= ~IXGBE_DMACR_DMAC_EN;
sys/dev/pci/ixgbe_x550.c
987
IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
sys/dev/pci/ixgbe_x550.c
992
reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
sys/dev/pci/ixgbe_x550.c
993
reg |= IXGBE_DMACR_DMAC_EN;
sys/dev/pci/ixgbe_x550.c
994
IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
sys/dev/pci/ksmn.c
201
uint32_t reg;
sys/dev/pci/ksmn.c
206
reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, SMN_17H_DATA_R);
sys/dev/pci/ksmn.c
208
return reg;
sys/dev/pci/ksmn.c
215
uint32_t reg;
sys/dev/pci/ksmn.c
221
reg = ksmn_read_reg(sc, SMU_17H_CCD_THM(sc->sc_ccd_offset, i));
sys/dev/pci/ksmn.c
222
if (reg & CURTMP_CCD_VALID) {
sys/dev/pci/ksmn.c
237
pcireg_t reg;
sys/dev/pci/ksmn.c
240
reg = ksmn_read_reg(sc, SMU_17H_THM);
sys/dev/pci/ksmn.c
241
raw = GET_CURTMP(reg);
sys/dev/pci/ksmn.c
242
if ((reg & CURTMP_17H_RANGE_SEL) != 0)
sys/dev/pci/ksmn.c
255
reg = ksmn_read_reg(sc,
sys/dev/pci/ksmn.c
257
s->value = (reg & CURTMP_CCD_MASK) * 125000 - offset +
sys/dev/pci/maestro.c
1531
wp_reg_read(struct maestro_softc *sc, int reg)
sys/dev/pci/maestro.c
1533
bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_INDEX, reg);
sys/dev/pci/maestro.c
1538
wp_reg_write(struct maestro_softc *sc, int reg, wpreg_t data)
sys/dev/pci/maestro.c
1540
bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_INDEX, reg);
sys/dev/pci/maestro.c
1545
apu_setindex(struct maestro_softc *sc, int reg)
sys/dev/pci/maestro.c
1549
wp_reg_write(sc, WPREG_CRAM_PTR, reg);
sys/dev/pci/maestro.c
1553
PORT_DSP_DATA) == reg)
sys/dev/pci/maestro.c
1555
bus_space_write_2(sc->iot, sc->ioh, PORT_DSP_DATA, reg);
sys/dev/pci/maestro.c
1562
wp_apu_read(struct maestro_softc *sc, int ch, int reg)
sys/dev/pci/maestro.c
1566
apu_setindex(sc, ((unsigned)ch << 4) + reg);
sys/dev/pci/maestro.c
1572
wp_apu_write(struct maestro_softc *sc, int ch, int reg, wpreg_t data)
sys/dev/pci/maestro.c
1576
apu_setindex(sc, ((unsigned)ch << 4) + reg);
sys/dev/pci/maestro.c
1627
wc_reg_read(struct maestro_softc *sc, int reg)
sys/dev/pci/maestro.c
1629
bus_space_write_2(sc->iot, sc->ioh, PORT_WAVCACHE_INDEX, reg);
sys/dev/pci/maestro.c
1634
wc_reg_write(struct maestro_softc *sc, int reg, wcreg_t data)
sys/dev/pci/maestro.c
1636
bus_space_write_2(sc->iot, sc->ioh, PORT_WAVCACHE_INDEX, reg);
sys/dev/pci/maestro.c
739
int reg;
sys/dev/pci/maestro.c
774
for (reg = WAVCACHE_PCMBAR; reg < WAVCACHE_PCMBAR + 4; reg++)
sys/dev/pci/maestro.c
775
wc_reg_write(sc, reg,
sys/dev/pci/mfi_pci.c
104
pcireg_t reg;
sys/dev/pci/mfi_pci.c
118
reg = pci_mapreg_type(pa->pa_pc, pa->pa_tag, regbar);
sys/dev/pci/mfi_pci.c
119
if (pci_mapreg_map(pa, regbar, reg, 0,
sys/dev/pci/mmuagp.c
192
pcireg_t reg;
sys/dev/pci/mmuagp.c
196
reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);
sys/dev/pci/mmuagp.c
197
if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||
sys/dev/pci/mmuagp.c
198
PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI)
sys/dev/pci/mmuagp.c
201
reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
sys/dev/pci/mmuagp.c
202
if (PCI_VENDOR(reg) != PCI_VENDOR_NVIDIA || PCI_PRODUCT(reg) != devid)
sys/dev/pci/mmuagp.c
212
pcireg_t reg;
sys/dev/pci/mmuagp.c
216
reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);
sys/dev/pci/mmuagp.c
217
if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||
sys/dev/pci/mmuagp.c
218
PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI)
sys/dev/pci/mmuagp.c
221
reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
sys/dev/pci/mmuagp.c
222
if (PCI_VENDOR(reg) != PCI_VENDOR_VIATECH ||
sys/dev/pci/mmuagp.c
223
PCI_PRODUCT(reg) != PCI_PRODUCT_VIATECH_K8HTB_AGP)
sys/dev/pci/nviic.c
146
pcireg_t reg;
sys/dev/pci/nviic.c
171
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, baseregs[i]);
sys/dev/pci/nviic.c
172
if (NVI_SMBASE(reg) == 0 ||
sys/dev/pci/nviic.c
173
bus_space_map(sc->sc_iot, NVI_SMBASE(reg), NVI_SMBASE_SIZE,
sys/dev/pci/pccbb.c
1006
pccbb_pcmcia_read(struct pcic_handle *ph, int reg)
sys/dev/pci/pccbb.c
1009
PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ);
sys/dev/pci/pccbb.c
1012
PCCBB_PCMCIA_OFFSET + reg);
sys/dev/pci/pccbb.c
1016
pccbb_pcmcia_write(struct pcic_handle *ph, int reg, int val)
sys/dev/pci/pccbb.c
1019
PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE);
sys/dev/pci/pccbb.c
1021
bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg,
sys/dev/pci/pccbb.c
1467
pcireg_t reg;
sys/dev/pci/pccbb.c
1473
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);
sys/dev/pci/pccbb.c
1474
reg &= ~CB_BCR_INTR_IREQ_ENABLE;
sys/dev/pci/pccbb.c
1475
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg);
sys/dev/pci/pccbb.c
1479
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL);
sys/dev/pci/pccbb.c
1481
reg |= PCI113X_CBCTRL_PCI_INTR;
sys/dev/pci/pccbb.c
1482
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg);
sys/dev/pci/pccbb.c
1524
pcireg_t reg;
sys/dev/pci/pccbb.c
1547
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);
sys/dev/pci/pccbb.c
1548
reg |= CB_BCR_INTR_IREQ_ENABLE;
sys/dev/pci/pccbb.c
1549
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg);
sys/dev/pci/pccbb.c
1553
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL);
sys/dev/pci/pccbb.c
1555
reg &= ~PCI113X_CBCTRL_PCI_INTR;
sys/dev/pci/pccbb.c
1556
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg);
sys/dev/pci/pccbb.c
1854
int reg;
sys/dev/pci/pccbb.c
1860
reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
sys/dev/pci/pccbb.c
1863
reg &= ~PCIC_ADDRWIN_ENABLE_IO0;
sys/dev/pci/pccbb.c
1866
reg &= ~PCIC_ADDRWIN_ENABLE_IO1;
sys/dev/pci/pccbb.c
1869
Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg);
sys/dev/pci/pccbb.c
2175
int reg;
sys/dev/pci/pccbb.c
2222
reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
sys/dev/pci/pccbb.c
2223
reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16);
sys/dev/pci/pccbb.c
2224
Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg);
sys/dev/pci/pccbb.c
2335
int reg;
sys/dev/pci/pccbb.c
2341
reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
sys/dev/pci/pccbb.c
2342
reg &= ~(1 << window);
sys/dev/pci/pccbb.c
2343
Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg);
sys/dev/pci/pccbb.c
2775
u_int32_t reg;
sys/dev/pci/pccbb.c
2832
reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK);
sys/dev/pci/pccbb.c
2834
reg |= CB_SOCKET_MASK_CD;
sys/dev/pci/pccbb.c
2835
bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg);
sys/dev/pci/pccbb.c
2838
reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT);
sys/dev/pci/pccbb.c
2839
bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg);
sys/dev/pci/pccbb.c
573
pcireg_t reg;
sys/dev/pci/pccbb.c
583
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);
sys/dev/pci/pccbb.c
584
reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA);
sys/dev/pci/pccbb.c
585
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg);
sys/dev/pci/pccbb.c
608
pcireg_t reg;
sys/dev/pci/pccbb.c
617
reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
sys/dev/pci/pccbb.c
619
reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
sys/dev/pci/pccbb.c
621
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);
sys/dev/pci/pccbb.c
626
reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG);
sys/dev/pci/pccbb.c
627
if (PCI_CB_LATENCY(reg) < 0x20) {
sys/dev/pci/pccbb.c
628
reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT);
sys/dev/pci/pccbb.c
629
reg |= (0x20 << PCI_CB_LATENCY_SHIFT);
sys/dev/pci/pccbb.c
630
pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg);
sys/dev/pci/pccbb.c
633
PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG)));
sys/dev/pci/pccbb.c
638
reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
sys/dev/pci/pccbb.c
639
if (PCI_LATTIMER(reg) < 0x10) {
sys/dev/pci/pccbb.c
640
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
sys/dev/pci/pccbb.c
641
reg |= (0x10 << PCI_LATTIMER_SHIFT);
sys/dev/pci/pccbb.c
642
pci_conf_write(pc, tag, PCI_BHLC_REG, reg);
sys/dev/pci/pccbb.c
645
PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG)));
sys/dev/pci/pccbb.c
648
reg = pci_conf_read(pc, tag, PCI_BCR_INTR);
sys/dev/pci/pccbb.c
649
reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */
sys/dev/pci/pccbb.c
650
reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */
sys/dev/pci/pccbb.c
651
reg |= CB_BCR_RESET_ENABLE; /* assert reset */
sys/dev/pci/pccbb.c
652
pci_conf_write(pc, tag, PCI_BCR_INTR, reg);
sys/dev/pci/pccbb.c
656
reg = pci_conf_read(pc, tag, PCI_CBCTRL);
sys/dev/pci/pccbb.c
659
reg |= PCI113X_CBCTRL_PCI_IRQ_ENA;
sys/dev/pci/pccbb.c
661
reg |= PCI113X_CBCTRL_PCI_CSC;
sys/dev/pci/pccbb.c
663
reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK);
sys/dev/pci/pccbb.c
664
pci_conf_write(pc, tag, PCI_CBCTRL, reg);
sys/dev/pci/pccbb.c
677
reg = pci_conf_read(pc, tag, PCI12XX_MFUNC);
sys/dev/pci/pccbb.c
678
if (reg == PCI12XX_MFUNC_DEFAULT) {
sys/dev/pci/pccbb.c
679
reg &= ~PCI12XX_MFUNC_PIN0;
sys/dev/pci/pccbb.c
680
reg |= PCI12XX_MFUNC_PIN0_INTA;
sys/dev/pci/pccbb.c
683
reg &= ~PCI12XX_MFUNC_PIN1;
sys/dev/pci/pccbb.c
684
reg |= PCI12XX_MFUNC_PIN1_INTB;
sys/dev/pci/pccbb.c
686
pci_conf_write(pc, tag, PCI12XX_MFUNC, reg);
sys/dev/pci/pccbb.c
698
reg = pci_conf_read(pc, tag, PCI_SYSCTRL);
sys/dev/pci/pccbb.c
699
reg |= PCI12XX_SYSCTRL_VCCPROT;
sys/dev/pci/pccbb.c
700
pci_conf_write(pc, tag, PCI_SYSCTRL, reg);
sys/dev/pci/pccbb.c
701
reg = pci_conf_read(pc, tag, PCI_CBCTRL);
sys/dev/pci/pccbb.c
702
reg |= PCI12XX_CBCTRL_CSC;
sys/dev/pci/pccbb.c
703
pci_conf_write(pc, tag, PCI_CBCTRL, reg);
sys/dev/pci/pccbb.c
707
reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL);
sys/dev/pci/pccbb.c
708
reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL;
sys/dev/pci/pccbb.c
709
pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg);
sys/dev/pci/pccbb.c
711
reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL);
sys/dev/pci/pccbb.c
713
sc->sc_dev.dv_xname, reg));
sys/dev/pci/pccbb.c
714
reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
sys/dev/pci/pccbb.c
716
reg &= ~TOPIC_SLOT_CTRL_SWDETECT;
sys/dev/pci/pccbb.c
717
DPRINTF(("0x%x\n", reg));
sys/dev/pci/pccbb.c
718
pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg);
sys/dev/pci/pccbb.c
722
reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL);
sys/dev/pci/pccbb.c
724
sc->sc_dev.dv_xname, reg));
sys/dev/pci/pccbb.c
725
reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
sys/dev/pci/pccbb.c
727
reg &= ~TOPIC_SLOT_CTRL_SWDETECT;
sys/dev/pci/pccbb.c
728
reg |= TOPIC97_SLOT_CTRL_PCIINT;
sys/dev/pci/pccbb.c
729
reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP);
sys/dev/pci/pccbb.c
730
DPRINTF(("0x%x\n", reg));
sys/dev/pci/pccbb.c
731
pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg);
sys/dev/pci/pccbb.c
748
sc->sc_dev.dv_xname, reg));
sys/dev/pci/pccbb.c
749
reg = pci_conf_read(pc, tag, O2MICRO_RESERVED1);
sys/dev/pci/pccbb.c
750
pci_conf_write(pc, tag, O2MICRO_RESERVED1, reg &
sys/dev/pci/pccbb.c
752
reg = pci_conf_read(pc, tag, O2MICRO_RESERVED2);
sys/dev/pci/pccbb.c
753
pci_conf_write(pc, tag, O2MICRO_RESERVED2, reg &
sys/dev/pci/pccbb.c
93
#define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg)))
sys/dev/pci/pccbb.c
94
#define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val)))
sys/dev/pci/pci.c
1106
uint32_t reg;
sys/dev/pci/pci.c
1113
if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0)
sys/dev/pci/pci.c
1117
reg &= 0x0000ffff;
sys/dev/pci/pci.c
1118
reg &= ~PCI_VPD_OPFLAG;
sys/dev/pci/pci.c
1119
reg |= PCI_VPD_ADDRESS(offset);
sys/dev/pci/pci.c
1120
pci_conf_write(pc, tag, ofs, reg);
sys/dev/pci/pci.c
1131
reg = pci_conf_read(pc, tag, ofs);
sys/dev/pci/pci.c
1132
} while ((reg & PCI_VPD_OPFLAG) == 0);
sys/dev/pci/pci.c
1614
pcireg_t reg;
sys/dev/pci/pci.c
1617
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0)
sys/dev/pci/pci.c
1620
tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
sys/dev/pci/pci.c
1630
pcireg_t reg;
sys/dev/pci/pci.c
1633
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0)
sys/dev/pci/pci.c
1636
tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
sys/dev/pci/pci.c
1645
pcireg_t reg;
sys/dev/pci/pci.c
1648
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0)
sys/dev/pci/pci.c
1656
tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
sys/dev/pci/pci.c
1667
*mc = reg;
sys/dev/pci/pci.c
1675
pcireg_t reg;
sys/dev/pci/pci.c
1679
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
sys/dev/pci/pci.c
1687
tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
sys/dev/pci/pci.c
1708
pcireg_t reg;
sys/dev/pci/pci.c
1714
®) == 0)
sys/dev/pci/pci.c
1717
return (PCI_MSIX_MC_TBLSZ(reg) + 1);
sys/dev/pci/pci.c
244
pcireg_t bhlc, reg;
sys/dev/pci/pci.c
269
PCI_CAP_MSI, &off, ®)) {
sys/dev/pci/pci.c
272
if (reg & PCI_MSI_MC_C64) {
sys/dev/pci/pci.c
281
pd->pd_msi_mc = reg;
sys/dev/pci/pci.c
322
pcireg_t bhlc, reg;
sys/dev/pci/pci.c
344
reg = pci_conf_read(sc->sc_pc, pd->pd_tag,
sys/dev/pci/pci.c
347
(reg & 0xffff0000) | (pd->pd_csr & 0x0000ffff));
sys/dev/pci/pci.c
354
PCI_CAP_MSI, &off, ®)) {
sys/dev/pci/pci.c
357
if (reg & PCI_MSI_MC_C64) {
sys/dev/pci/pci.c
525
int i, reg, reg_start, reg_end;
sys/dev/pci/pci.c
557
for (reg = reg_start, i = 0; reg < reg_end; reg += 4, i++) {
sys/dev/pci/pci.c
558
address = pci_conf_read(pc, tag, reg);
sys/dev/pci/pci.c
559
pci_conf_write(pc, tag, reg, 0xffffffff);
sys/dev/pci/pci.c
560
pd->pd_mask[i] = pci_conf_read(pc, tag, reg);
sys/dev/pci/pci.c
561
pci_conf_write(pc, tag, reg, address);
sys/dev/pci/pci.c
607
pcireg_t reg;
sys/dev/pci/pci.c
610
reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
sys/dev/pci/pci.c
611
if (!(reg & PCI_STATUS_CAPLIST_SUPPORT))
sys/dev/pci/pci.c
615
reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
sys/dev/pci/pci.c
616
switch (PCI_HDRTYPE_TYPE(reg)) {
sys/dev/pci/pci.c
637
reg = pci_conf_read(pc, tag, ofs);
sys/dev/pci/pci.c
638
if (PCI_CAPLIST_CAP(reg) == capid) {
sys/dev/pci/pci.c
642
*value = reg;
sys/dev/pci/pci.c
645
ofs = PCI_CAPLIST_NEXT(reg);
sys/dev/pci/pci.c
655
pcireg_t reg;
sys/dev/pci/pci.c
666
reg = pci_conf_read(pc, tag, ofs);
sys/dev/pci/pci.c
667
if (PCI_HT_CAP(reg) == capid) {
sys/dev/pci/pci.c
671
*value = reg;
sys/dev/pci/pci.c
674
ofs = PCI_CAPLIST_NEXT(reg);
sys/dev/pci/pci.c
684
pcireg_t reg;
sys/dev/pci/pci.c
698
reg = pci_conf_read(pc, tag, ofs);
sys/dev/pci/pci.c
699
if (PCI_PCIE_ECAP_ID(reg) == capid) {
sys/dev/pci/pci.c
703
*value = reg;
sys/dev/pci/pci.c
706
ofs = PCI_PCIE_ECAP_NEXT(reg);
sys/dev/pci/pci.c
742
pcireg_t reg;
sys/dev/pci/pci.c
746
reg = pci_conf_read(pc, tag, offset + PCI_PMCSR);
sys/dev/pci/pci.c
747
return (reg & PCI_PMCSR_STATE_MASK);
sys/dev/pci/pci.c
755
pcireg_t id, reg;
sys/dev/pci/pci.c
786
reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
sys/dev/pci/pci.c
787
reg &= ~PCI_COMMAND_IO_ENABLE;
sys/dev/pci/pci.c
788
reg &= ~PCI_COMMAND_MEM_ENABLE;
sys/dev/pci/pci.c
789
reg &= ~PCI_COMMAND_MASTER_ENABLE;
sys/dev/pci/pci.c
790
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);
sys/dev/pci/pci.c
792
reg = pci_conf_read(pc, tag, offset + PCI_PMCSR);
sys/dev/pci/pci.c
793
if ((reg & PCI_PMCSR_STATE_MASK) != state) {
sys/dev/pci/pci.c
794
ostate = reg & PCI_PMCSR_STATE_MASK;
sys/dev/pci/pci.c
797
(reg & ~PCI_PMCSR_STATE_MASK) | state);
sys/dev/pci/pci.c
896
int reg, reg_start, reg_end, reg_rom;
sys/dev/pci/pci.c
926
for (reg = reg_start; reg < reg_end; reg += 4) {
sys/dev/pci/pci.c
927
if (!pci_mapreg_probe(pc, tag, reg, &type))
sys/dev/pci/pci.c
930
if (pci_mapreg_info(pc, tag, reg, type, &base, &size, &flags))
sys/dev/pci/pci.c
968
pci_conf_write(pc, tag, reg, 0);
sys/dev/pci/pci.c
970
pci_conf_write(pc, tag, reg + 4, 0);
sys/dev/pci/pci.c
981
pci_conf_write(pc, tag, reg, 0);
sys/dev/pci/pci.c
987
reg += 4;
sys/dev/pci/pci_map.c
100
mask = pci_conf_read(pc, tag, reg);
sys/dev/pci/pci_map.c
101
pci_conf_write(pc, tag, reg, address);
sys/dev/pci/pci_map.c
131
obsd_pci_mem_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type,
sys/dev/pci/pci_map.c
140
if (reg < PCI_MAPREG_START ||
sys/dev/pci/pci_map.c
146
reg >= PCI_MAPREG_END ||
sys/dev/pci/pci_map.c
148
(reg & 3))
sys/dev/pci/pci_map.c
151
if (is64bit && (reg + 4) >= PCI_MAPREG_END)
sys/dev/pci/pci_map.c
169
address = pci_conf_read(pc, tag, reg);
sys/dev/pci/pci_map.c
170
pci_conf_write(pc, tag, reg, PCI_MAPREG_MEM_ADDR_MASK);
sys/dev/pci/pci_map.c
171
mask = pci_conf_read(pc, tag, reg);
sys/dev/pci/pci_map.c
172
pci_conf_write(pc, tag, reg, address);
sys/dev/pci/pci_map.c
174
address1 = pci_conf_read(pc, tag, reg + 4);
sys/dev/pci/pci_map.c
175
pci_conf_write(pc, tag, reg + 4, 0xffffffff);
sys/dev/pci/pci_map.c
176
mask1 = pci_conf_read(pc, tag, reg + 4);
sys/dev/pci/pci_map.c
177
pci_conf_write(pc, tag, reg + 4, address1);
sys/dev/pci/pci_map.c
258
pci_mapreg_type(pci_chipset_tag_t pc, pcitag_t tag, int reg)
sys/dev/pci/pci_map.c
260
return (_PCI_MAPREG_TYPEBITS(pci_conf_read(pc, tag, reg)));
sys/dev/pci/pci_map.c
264
pci_mapreg_probe(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *typep)
sys/dev/pci/pci_map.c
274
address = pci_conf_read(pc, tag, reg);
sys/dev/pci/pci_map.c
275
pci_conf_write(pc, tag, reg, 0xffffffff);
sys/dev/pci/pci_map.c
276
mask = pci_conf_read(pc, tag, reg);
sys/dev/pci/pci_map.c
277
pci_conf_write(pc, tag, reg, address);
sys/dev/pci/pci_map.c
291
pci_mapreg_info(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type,
sys/dev/pci/pci_map.c
296
return (obsd_pci_io_find(pc, tag, reg, type, basep, sizep,
sys/dev/pci/pci_map.c
299
return (obsd_pci_mem_find(pc, tag, reg, type, basep, sizep,
sys/dev/pci/pci_map.c
304
pci_mapreg_assign(struct pci_attach_args *pa, int reg, pcireg_t type,
sys/dev/pci/pci_map.c
312
if ((rv = pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, type,
sys/dev/pci/pci_map.c
338
pci_conf_write(pa->pa_pc, pa->pa_tag, reg, base);
sys/dev/pci/pci_map.c
340
pci_conf_write(pa->pa_pc, pa->pa_tag, reg + 4,
sys/dev/pci/pci_map.c
363
pci_mapreg_map(struct pci_attach_args *pa, int reg, pcireg_t type, int flags,
sys/dev/pci/pci_map.c
373
if ((rv = pci_mapreg_assign(pa, reg, type, &base, &size)) != 0)
sys/dev/pci/pci_map.c
66
obsd_pci_io_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type,
sys/dev/pci/pci_map.c
72
if (reg < PCI_MAPREG_START ||
sys/dev/pci/pci_map.c
78
reg >= PCI_MAPREG_END ||
sys/dev/pci/pci_map.c
80
(reg & 3))
sys/dev/pci/pci_map.c
98
address = pci_conf_read(pc, tag, reg);
sys/dev/pci/pci_map.c
99
pci_conf_write(pc, tag, reg, 0xffffffff);
sys/dev/pci/pciide.c
138
pciide_pci_read(pci_chipset_tag_t pc, pcitag_t pa, int reg)
sys/dev/pci/pciide.c
140
return (pci_conf_read(pc, pa, (reg & ~0x03)) >>
sys/dev/pci/pciide.c
141
((reg & 0x03) * 8) & 0xff);
sys/dev/pci/pciide.c
145
pciide_pci_write(pci_chipset_tag_t pc, pcitag_t pa, int reg, u_int8_t val)
sys/dev/pci/pciide.c
149
pcival = pci_conf_read(pc, pa, (reg & ~0x03));
sys/dev/pci/pciide.c
150
pcival &= ~(0xff << ((reg & 0x03) * 8));
sys/dev/pci/pciide.c
151
pcival |= (val << ((reg & 0x03) * 8));
sys/dev/pci/pciide.c
152
pci_conf_write(pc, pa, (reg & ~0x03), pcival);
sys/dev/pci/pciide.c
2811
u_int8_t reg, ich = 0;
sys/dev/pci/pciide.c
2854
reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP);
sys/dev/pci/pciide.c
2855
if ((reg & ICH5_SATA_MAP_COMBINED) == 0) {
sys/dev/pci/pciide.c
2856
reg = pciide_pci_read(pa->pa_pc, pa->pa_tag,
sys/dev/pci/pciide.c
2858
reg |= ICH5_SATA_PI_PRI_NATIVE |
sys/dev/pci/pciide.c
2861
ICH5_SATA_PI, reg);
sys/dev/pci/pciide.c
2866
reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP) &
sys/dev/pci/pciide.c
2868
if (reg != ICH6_SATA_MAP_CMB_PRI &&
sys/dev/pci/pciide.c
2869
reg != ICH6_SATA_MAP_CMB_SEC) {
sys/dev/pci/pciide.c
2870
reg = pciide_pci_read(pa->pa_pc, pa->pa_tag,
sys/dev/pci/pciide.c
2872
reg |= ICH5_SATA_PI_PRI_NATIVE |
sys/dev/pci/pciide.c
2876
ICH5_SATA_PI, reg);
sys/dev/pci/pciide.c
2886
reg = pciide_pci_read(sc->sc_pc, sc->sc_tag,
sys/dev/pci/pciide.c
2889
ICH5_SATA_MAP, reg);
sys/dev/pci/pciide.c
4115
int interface, i, reg;
sys/dev/pci/pciide.c
4143
reg = 0xa2 + channel * 16;
sys/dev/pci/pciide.c
4145
pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]);
sys/dev/pci/pciide.c
4669
int chan, reg;
sys/dev/pci/pciide.c
4685
for (reg = 0; reg < IDEDMA_NREGS; reg++) {
sys/dev/pci/pciide.c
4687
if (size > (IDEDMA_SCH_OFFSET - reg))
sys/dev/pci/pciide.c
4688
size = IDEDMA_SCH_OFFSET - reg;
sys/dev/pci/pciide.c
4691
satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg,
sys/dev/pci/pciide.c
4692
size, &sl->regs[chan].dma_iohs[reg]) != 0) {
sys/dev/pci/pciide.c
4697
chan].ba5_IDEDMA_CMD + reg,
sys/dev/pci/pciide.c
4803
sii3114_read_reg(struct channel_softc *chp, enum wdc_regs reg)
sys/dev/pci/pciide.c
4809
if (reg & _WDC_AUX)
sys/dev/pci/pciide.c
4811
sl->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK));
sys/dev/pci/pciide.c
4814
sl->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 0));
sys/dev/pci/pciide.c
4818
sii3114_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
sys/dev/pci/pciide.c
4824
if (reg & _WDC_AUX)
sys/dev/pci/pciide.c
4826
sl->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val);
sys/dev/pci/pciide.c
4829
sl->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK],
sys/dev/pci/pciide.c
7178
pdc203xx_read_reg(struct channel_softc *chp, enum wdc_regs reg)
sys/dev/pci/pciide.c
7185
if (reg & _WDC_AUX) {
sys/dev/pci/pciide.c
7187
ps->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK));
sys/dev/pci/pciide.c
7190
ps->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 0);
sys/dev/pci/pciide.c
7196
pdc203xx_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
sys/dev/pci/pciide.c
7202
if (reg & _WDC_AUX)
sys/dev/pci/pciide.c
7204
ps->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val);
sys/dev/pci/pciide.c
7207
ps->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK],
sys/dev/pci/pciide.c
7793
svwsata_read_reg(struct channel_softc *chp, enum wdc_regs reg)
sys/dev/pci/pciide.c
7795
if (reg & _WDC_AUX) {
sys/dev/pci/pciide.c
7797
(reg & _WDC_REGMASK) << 2));
sys/dev/pci/pciide.c
7800
(reg & _WDC_REGMASK) << 2));
sys/dev/pci/pciide.c
7805
svwsata_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val)
sys/dev/pci/pciide.c
7807
if (reg & _WDC_AUX) {
sys/dev/pci/pciide.c
7809
(reg & _WDC_REGMASK) << 2, val);
sys/dev/pci/pciide.c
7812
(reg & _WDC_REGMASK) << 2, val);
sys/dev/pci/pciide.c
7817
svwsata_lba48_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int16_t val)
sys/dev/pci/pciide.c
7819
if (reg & _WDC_AUX) {
sys/dev/pci/pciide.c
7821
(reg & _WDC_REGMASK) << 2, val);
sys/dev/pci/pciide.c
7824
(reg & _WDC_REGMASK) << 2, val);
sys/dev/pci/pciide.c
7900
u_int32_t reg;
sys/dev/pci/pciide.c
7901
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL);
sys/dev/pci/pciide.c
7902
reg &= ~ATP860_CTRL_INT;
sys/dev/pci/pciide.c
7903
pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg);
sys/dev/pci/pciide_sii3112_reg.h
341
ba5_read_4_ind(struct pciide_softc *sc, pcireg_t reg)
sys/dev/pci/pciide_sii3112_reg.h
347
pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg);
sys/dev/pci/pciide_sii3112_reg.h
355
ba5_read_4(struct pciide_softc *sc, bus_size_t reg)
sys/dev/pci/pciide_sii3112_reg.h
360
return (bus_space_read_4(sl->ba5_st, sl->ba5_sh, reg));
sys/dev/pci/pciide_sii3112_reg.h
362
return (ba5_read_4_ind(sc, reg));
sys/dev/pci/pciide_sii3112_reg.h
365
#define BA5_READ_4(sc, chan, reg) \
sys/dev/pci/pciide_sii3112_reg.h
366
ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg)
sys/dev/pci/pciide_sii3112_reg.h
369
ba5_write_4_ind(struct pciide_softc *sc, pcireg_t reg, uint32_t val)
sys/dev/pci/pciide_sii3112_reg.h
374
pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg);
sys/dev/pci/pciide_sii3112_reg.h
380
ba5_write_4(struct pciide_softc *sc, bus_size_t reg, uint32_t val)
sys/dev/pci/pciide_sii3112_reg.h
385
bus_space_write_4(sl->ba5_st, sl->ba5_sh, reg, val);
sys/dev/pci/pciide_sii3112_reg.h
387
ba5_write_4_ind(sc, reg, val);
sys/dev/pci/pciide_sii3112_reg.h
390
#define BA5_WRITE_4(sc, chan, reg, val) \
sys/dev/pci/pciide_sii3112_reg.h
391
ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val))
sys/dev/pci/pcireg.h
424
#define _PCI_MAPREG_TYPEBITS(reg) \
sys/dev/pci/pcireg.h
425
(PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \
sys/dev/pci/pcireg.h
426
reg & PCI_MAPREG_TYPE_MASK : \
sys/dev/pci/pcireg.h
427
reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK))
sys/dev/pci/pcireg.h
653
#define PCI_MSIX_MC_TBLSZ(reg) \
sys/dev/pci/pcireg.h
654
(((reg) & PCI_MSIX_MC_TBLSZ_MASK) >> PCI_MSIX_MC_TBLSZ_SHIFT)
sys/dev/pci/pcscp.c
317
pcscp_read_reg(struct ncr53c9x_softc *sc, int reg)
sys/dev/pci/pcscp.c
321
return PCSCP_READ_REG(esc, reg);
sys/dev/pci/pcscp.c
325
pcscp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v)
sys/dev/pci/pcscp.c
329
PCSCP_WRITE_REG(esc, reg, v);
sys/dev/pci/pcscp.c
84
#define READ_DMAREG(sc, reg) \
sys/dev/pci/pcscp.c
85
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
sys/dev/pci/pcscp.c
86
#define WRITE_DMAREG(sc, reg, var) \
sys/dev/pci/pcscp.c
87
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var))
sys/dev/pci/pcscp.c
89
#define PCSCP_READ_REG(sc, reg) \
sys/dev/pci/pcscp.c
90
bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2)
sys/dev/pci/pcscp.c
91
#define PCSCP_WRITE_REG(sc, reg, val) \
sys/dev/pci/pcscp.c
92
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2, (val))
sys/dev/pci/ppb.c
161
pcireg_t busdata, reg, blr;
sys/dev/pci/ppb.c
217
&sc->sc_cap_off, ®) && (reg & PCI_PCIE_XCAP_SI)) {
sys/dev/pci/ppb.c
238
reg = pci_conf_read(pc, pa->pa_tag,
sys/dev/pci/ppb.c
240
reg |= (PCI_PCIE_SLCSR_HPE | PCI_PCIE_SLCSR_PDE);
sys/dev/pci/ppb.c
242
sc->sc_cap_off + PCI_PCIE_SLCSR, reg);
sys/dev/pci/ppb.c
416
pcireg_t blr, reg;
sys/dev/pci/ppb.c
433
if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®)) {
sys/dev/pci/ppb.c
436
if (reg & PCI_MSI_MC_C64) {
sys/dev/pci/ppb.c
445
sc->sc_msi_mc = reg;
sys/dev/pci/ppb.c
489
if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®)) {
sys/dev/pci/ppb.c
492
if (reg & PCI_MSI_MC_C64) {
sys/dev/pci/ppb.c
509
reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
sys/dev/pci/ppb.c
511
(reg & 0xffff0000) | (sc->sc_csr & 0x0000ffff));
sys/dev/pci/ppb.c
580
int reg, reg_start, reg_end, reg_rom;
sys/dev/pci/ppb.c
632
for (reg = reg_start; reg < reg_end; reg += 4) {
sys/dev/pci/ppb.c
633
if (pci_mapreg_probe(pc, tag, reg, &type) == 0)
sys/dev/pci/ppb.c
643
reg += 4;
sys/dev/pci/ppb.c
743
pcireg_t reg;
sys/dev/pci/ppb.c
755
reg = pci_conf_read(sc->sc_pc, sc->sc_tag,
sys/dev/pci/ppb.c
757
if (reg & PCI_PCIE_SLCSR_PDC) {
sys/dev/pci/ppb.c
758
if (reg & PCI_PCIE_SLCSR_PDS)
sys/dev/pci/ppb.c
765
sc->sc_cap_off + PCI_PCIE_SLCSR, reg);
sys/dev/pci/sdhc_pci.c
115
int reg;
sys/dev/pci/sdhc_pci.c
177
for (reg = SDHC_PCI_BAR_START + SDHC_PCI_FIRST_BAR(slotinfo) * 4;
sys/dev/pci/sdhc_pci.c
178
reg < SDHC_PCI_BAR_END && nslots > 0;
sys/dev/pci/sdhc_pci.c
179
reg += 4, nslots--) {
sys/dev/pci/sdhc_pci.c
180
if (!pci_mapreg_probe(pa->pa_pc, pa->pa_tag, reg, &type))
sys/dev/pci/sdhc_pci.c
183
if (type == PCI_MAPREG_TYPE_IO || pci_mapreg_map(pa, reg,
sys/dev/pci/sdhc_pci.c
186
sc->sc.sc_dev.dv_xname, reg);
sys/dev/pci/sdhc_pci.c
194
sc->sc.sc_dev.dv_xname, reg);
sys/dev/pci/sdhc_pci.c
197
reg += 4;
sys/dev/pci/sdhc_pci.c
230
pcireg_t id, reg;
sys/dev/pci/sdhc_pci.c
242
reg = pci_conf_read(pa->pa_pc, tag, SDHC_PCI_GENERAL_CTL);
sys/dev/pci/sdhc_pci.c
243
reg |= MMC_SD_DIS;
sys/dev/pci/sdhc_pci.c
244
pci_conf_write(pa->pa_pc, tag, SDHC_PCI_GENERAL_CTL, reg);
sys/dev/pci/sdhc_pci.c
265
sdhc_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, uint8_t val)
sys/dev/pci/sdhc_pci.c
269
tmp = pci_conf_read(pc, tag, reg & ~0x3);
sys/dev/pci/sdhc_pci.c
270
tmp &= ~(0xff << ((reg & 0x3) * 8));
sys/dev/pci/sdhc_pci.c
271
tmp |= (val << ((reg & 0x3) * 8));
sys/dev/pci/sdhc_pci.c
272
pci_conf_write(pc, tag, reg & ~0x3, tmp);
sys/dev/pci/sdhc_pci.c
304
pcireg_t reg;
sys/dev/pci/sdhc_pci.c
306
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, GL9755_WT);
sys/dev/pci/sdhc_pci.c
307
reg |= GL9755_WT_EN;
sys/dev/pci/sdhc_pci.c
308
pci_conf_write(sc->sc_pc, sc->sc_tag, GL9755_WT, reg);
sys/dev/pci/sdhc_pci.c
314
pcireg_t reg;
sys/dev/pci/sdhc_pci.c
316
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, GL9755_WT);
sys/dev/pci/sdhc_pci.c
317
reg &= ~GL9755_WT_EN;
sys/dev/pci/sdhc_pci.c
318
pci_conf_write(sc->sc_pc, sc->sc_tag, GL9755_WT, reg);
sys/dev/pci/sdhc_pci.c
395
pcireg_t reg;
sys/dev/pci/sdhc_pci.c
399
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, GL9755_PECONF);
sys/dev/pci/sdhc_pci.c
400
reg &= ~GL9755_PECONF_LFCLK;
sys/dev/pci/sdhc_pci.c
401
reg &= ~GL9755_PECONF_DMACLK;
sys/dev/pci/sdhc_pci.c
405
reg |= GL9755_PECONF_INVERT_CD;
sys/dev/pci/sdhc_pci.c
407
reg |= GL9755_PECONF_INVERT_WP;
sys/dev/pci/sdhc_pci.c
410
pci_conf_write(sc->sc_pc, sc->sc_tag, GL9755_PECONF, reg);
sys/dev/pci/sdhc_pci.c
413
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, GL9755_SERDES);
sys/dev/pci/sdhc_pci.c
414
reg &= ~GL9755_SERDES_SCP_DIS;
sys/dev/pci/sdhc_pci.c
415
pci_conf_write(sc->sc_pc, sc->sc_tag, GL9755_SERDES, reg);
sys/dev/pci/sv.c
1001
reg &= ~SV_MUTE_BIT;
sys/dev/pci/sv.c
1002
sv_write_indirect(sc, ports[idx].l_port, reg);
sys/dev/pci/sv.c
1005
reg = sv_read_indirect(sc, ports[idx].r_port);
sys/dev/pci/sv.c
1007
reg |= SV_MUTE_BIT;
sys/dev/pci/sv.c
1009
reg &= ~SV_MUTE_BIT;
sys/dev/pci/sv.c
1010
sv_write_indirect(sc, ports[idx].r_port, reg);
sys/dev/pci/sv.c
1036
reg = sv_read_indirect(sc, ports[idx].l_port);
sys/dev/pci/sv.c
1037
reg &= ~(ports[idx].mask);
sys/dev/pci/sv.c
1039
reg |= lval;
sys/dev/pci/sv.c
1040
sv_write_indirect(sc, ports[idx].l_port, reg);
sys/dev/pci/sv.c
1043
reg = sv_read_indirect(sc, ports[idx].r_port);
sys/dev/pci/sv.c
1044
reg &= ~(ports[idx].mask);
sys/dev/pci/sv.c
1047
reg |= rval;
sys/dev/pci/sv.c
1049
sv_write_indirect(sc, ports[idx].r_port, reg);
sys/dev/pci/sv.c
1073
reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL);
sys/dev/pci/sv.c
1074
reg &= ~SV_REC_SOURCE_MASK;
sys/dev/pci/sv.c
1075
reg |= (((cp->un.ord) << SV_REC_SOURCE_SHIFT) & SV_REC_SOURCE_MASK);
sys/dev/pci/sv.c
1076
sv_write_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL, reg);
sys/dev/pci/sv.c
1078
reg = sv_read_indirect(sc, SV_RIGHT_ADC_INPUT_CONTROL);
sys/dev/pci/sv.c
1079
reg &= ~SV_REC_SOURCE_MASK;
sys/dev/pci/sv.c
1080
reg |= (((cp->un.ord) << SV_REC_SOURCE_SHIFT) & SV_REC_SOURCE_MASK);
sys/dev/pci/sv.c
1081
sv_write_indirect(sc, SV_RIGHT_ADC_INPUT_CONTROL, reg);
sys/dev/pci/sv.c
1097
reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL);
sys/dev/pci/sv.c
1098
reg &= ~SV_REC_GAIN_MASK;
sys/dev/pci/sv.c
1099
reg |= val;
sys/dev/pci/sv.c
1100
sv_write_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL, reg);
sys/dev/pci/sv.c
1102
reg = sv_read_indirect(sc, SV_RIGHT_ADC_INPUT_CONTROL);
sys/dev/pci/sv.c
1103
reg &= ~SV_REC_GAIN_MASK;
sys/dev/pci/sv.c
1104
reg |= val;
sys/dev/pci/sv.c
1105
sv_write_indirect(sc, SV_RIGHT_ADC_INPUT_CONTROL, reg);
sys/dev/pci/sv.c
1115
reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL);
sys/dev/pci/sv.c
1117
reg |= SV_MIC_BOOST_BIT;
sys/dev/pci/sv.c
1119
reg &= ~SV_MIC_BOOST_BIT;
sys/dev/pci/sv.c
1122
sv_write_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL, reg);
sys/dev/pci/sv.c
1129
reg = sv_read_indirect(sc, SV_SRS_SPACE_CONTROL);
sys/dev/pci/sv.c
1131
reg &= ~SV_SRS_SPACE_ONOFF;
sys/dev/pci/sv.c
1133
reg |= SV_SRS_SPACE_ONOFF;
sys/dev/pci/sv.c
1136
sv_write_indirect(sc, SV_SRS_SPACE_CONTROL, reg);
sys/dev/pci/sv.c
1148
u_int8_t reg;
sys/dev/pci/sv.c
1160
reg = sv_read_indirect(sc, ports[idx].l_port);
sys/dev/pci/sv.c
1161
cp->un.ord = ((reg & SV_MUTE_BIT) ? 1 : 0);
sys/dev/pci/sv.c
1176
reg = sv_read_indirect(sc, ports[idx].l_port);
sys/dev/pci/sv.c
1177
reg &= ports[idx].mask;
sys/dev/pci/sv.c
1179
val = AUDIO_MAX_GAIN - ((reg * AUDIO_MAX_GAIN) / ports[idx].mask);
sys/dev/pci/sv.c
1184
reg = sv_read_indirect(sc, ports[idx].r_port);
sys/dev/pci/sv.c
1185
reg &= ports[idx].mask;
sys/dev/pci/sv.c
1187
val = AUDIO_MAX_GAIN - ((reg * AUDIO_MAX_GAIN) / ports[idx].mask);
sys/dev/pci/sv.c
1201
reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL);
sys/dev/pci/sv.c
1202
cp->un.ord = ((reg & SV_REC_SOURCE_MASK) >> SV_REC_SOURCE_SHIFT);
sys/dev/pci/sv.c
1213
reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL) & SV_REC_GAIN_MASK;
sys/dev/pci/sv.c
1215
(((unsigned int)reg) * AUDIO_MAX_GAIN) / SV_REC_GAIN_MASK;
sys/dev/pci/sv.c
1223
reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL);
sys/dev/pci/sv.c
1224
cp->un.ord = ((reg & SV_MIC_BOOST_BIT) ? 1 : 0);
sys/dev/pci/sv.c
1233
reg = sv_read_indirect(sc, SV_SRS_SPACE_CONTROL);
sys/dev/pci/sv.c
1235
cp->un.ord = ((reg & SV_SRS_SPACE_ONOFF) ? 0 : 1);
sys/dev/pci/sv.c
173
sv_write(struct sv_softc *sc, u_int8_t reg, u_int8_t val)
sys/dev/pci/sv.c
175
bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val);
sys/dev/pci/sv.c
179
sv_read(struct sv_softc *sc, u_int8_t reg)
sys/dev/pci/sv.c
181
return (bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg));
sys/dev/pci/sv.c
185
sv_read_indirect(struct sv_softc *sc, u_int8_t reg)
sys/dev/pci/sv.c
192
iaddr |= (reg & SV_IADDR_MASK);
sys/dev/pci/sv.c
199
sv_write_indirect(struct sv_softc *sc, u_int8_t reg, u_int8_t val)
sys/dev/pci/sv.c
203
if (reg > 0x3f) {
sys/dev/pci/sv.c
209
if (reg == SV_DMA_DATA_FORMAT)
sys/dev/pci/sv.c
215
iaddr |= (reg & SV_IADDR_MASK);
sys/dev/pci/sv.c
242
u_int8_t reg;
sys/dev/pci/sv.c
303
reg = sv_read(sc, SV_CODEC_CONTROL);
sys/dev/pci/sv.c
304
reg |= SV_CTL_RESET;
sys/dev/pci/sv.c
305
sv_write(sc, SV_CODEC_CONTROL, reg);
sys/dev/pci/sv.c
308
reg = sv_read(sc, SV_CODEC_CONTROL);
sys/dev/pci/sv.c
309
reg &= ~SV_CTL_RESET;
sys/dev/pci/sv.c
310
reg |= SV_CTL_INTA | SV_CTL_ENHANCED;
sys/dev/pci/sv.c
313
sv_write(sc, SV_CODEC_CONTROL, reg);
sys/dev/pci/sv.c
317
sv_write(sc, SV_CODEC_CONTROL, reg);
sys/dev/pci/sv.c
322
reg = sv_read(sc, SV_CODEC_INTMASK);
sys/dev/pci/sv.c
323
reg &= ~(SV_INTMASK_DMAA | SV_INTMASK_DMAC);
sys/dev/pci/sv.c
324
reg |= SV_INTMASK_UD | SV_INTMASK_SINT | SV_INTMASK_MIDI;
sys/dev/pci/sv.c
325
sv_write(sc, SV_CODEC_INTMASK, reg);
sys/dev/pci/sv.c
464
u_int8_t reg;
sys/dev/pci/sv.c
526
reg = sv_read(sc, SV_CODEC_INTMASK);
sys/dev/pci/sv.c
527
reg &= ~(SV_INTMASK_DMAA | SV_INTMASK_DMAC);
sys/dev/pci/sv.c
528
reg |= SV_INTMASK_UD | SV_INTMASK_SINT | SV_INTMASK_MIDI;
sys/dev/pci/sv.c
529
sv_write(sc, SV_CODEC_INTMASK, reg);
sys/dev/pci/sv.c
559
u_int8_t reg;
sys/dev/pci/sv.c
593
reg = sv_read_indirect(sc, SV_DMA_DATA_FORMAT);
sys/dev/pci/sv.c
594
reg &= ~(SV_DMAA_FORMAT16 | SV_DMAC_FORMAT16 | SV_DMAA_STEREO |
sys/dev/pci/sv.c
596
reg |= (mode);
sys/dev/pci/sv.c
597
sv_write_indirect(sc, SV_DMA_DATA_FORMAT, reg);
sys/dev/pci/sv.c
984
u_int8_t reg;
sys/dev/pci/sv.c
997
reg = sv_read_indirect(sc, ports[idx].l_port);
sys/dev/pci/sv.c
999
reg |= SV_MUTE_BIT;
sys/dev/pci/tcpcib.c
188
u_int32_t reg, wdtbase;
sys/dev/pci/tcpcib.c
200
reg = bus_space_read_4(sc->sc_hpet_iot, sc->sc_hpet_ioh,
sys/dev/pci/tcpcib.c
203
tc->tc_frequency = 1000000000000000ULL / reg;
sys/dev/pci/tcpcib.c
220
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, E600_LPC_WDTBA);
sys/dev/pci/tcpcib.c
221
wdtbase = reg & 0xffff;
sys/dev/pci/tcpcib.c
223
if (reg & (1U << 31) && wdtbase) {
sys/dev/pci/tcpcib.c
234
reg = bus_space_read_1(sc->sc_wdt_iot, sc->sc_wdt_ioh,
sys/dev/pci/tcpcib.c
236
if (reg & E600_WDT_RR1_TIMEOUT) {
sys/dev/pci/tcpcib.c
246
reg = bus_space_read_1(sc->sc_wdt_iot, sc->sc_wdt_ioh,
sys/dev/pci/tcpcib.c
248
if (reg & E600_WDT_WDTLR_LOCK) {
sys/dev/pci/tga.c
659
u_int32_t reg;
sys/dev/pci/tga.c
661
reg = TGARREG(dc, TGA_REG_SISR);
sys/dev/pci/tga.c
662
if (( reg & 0x00010001) != 0x00010001) {
sys/dev/pci/tga.c
664
if ((reg & 0x1f) != 0) {
sys/dev/pci/tga.c
666
TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f));
sys/dev/pci/tgavar.h
140
#define TGARREG(dc,reg) (bus_space_read_4((dc)->dc_memt, (dc)->dc_regs, \
sys/dev/pci/tgavar.h
141
(reg) << 2))
sys/dev/pci/tgavar.h
144
#define TGAWREG(dc,reg,val) bus_space_write_4((dc)->dc_memt, (dc)->dc_regs, \
sys/dev/pci/tgavar.h
145
(reg) << 2, (val))
sys/dev/pci/tgavar.h
148
#define TGAWALREG(dc,reg,alias,val) bus_space_write_4( \
sys/dev/pci/tgavar.h
150
((alias) * TGA_CREGS_ALIAS) + ((reg) << 2), \
sys/dev/pci/tgavar.h
154
#define TGAREGWB(dc,reg, nregs) bus_space_barrier( \
sys/dev/pci/tgavar.h
156
((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_WRITE)
sys/dev/pci/tgavar.h
159
#define TGAREGRB(dc,reg, nregs) bus_space_barrier( \
sys/dev/pci/tgavar.h
161
((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_READ)
sys/dev/pci/tgavar.h
164
#define TGAREGRWB(dc,reg, nregs) bus_space_barrier( \
sys/dev/pci/tgavar.h
166
((reg) << 2), 4 * (nregs), \
sys/dev/pci/vga_pci.c
192
pcireg_t reg;
sys/dev/pci/vga_pci.c
201
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
sys/dev/pci/vga_pci.c
202
reg |= PCI_COMMAND_MASTER_ENABLE;
sys/dev/pci/vga_pci.c
203
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);
sys/dev/pci/virtio_pci.c
379
pcireg_t reg[4];
sys/dev/pci/virtio_pci.c
383
if (!pci_get_capability(pc, tag, PCI_CAP_VENDSPEC, &offset, &v.reg[0]))
sys/dev/pci/virtio_pci.c
389
v.reg[i] = pci_conf_read(pc, tag, offset + i * 4);
sys/dev/pci/virtio_pci.c
405
pcireg_t reg[8];
sys/dev/pci/virtio_pci.c
412
if (!pci_get_capability(pc, tag, PCI_CAP_VENDSPEC, &offset, &v->reg[0]))
sys/dev/pci/virtio_pci.c
417
v->reg[i] = pci_conf_read(pc, tag, offset + i * 4);
sys/dev/pci/virtio_pci.c
433
v->reg[i] = pci_conf_read(pc, tag, offset + i * 4);
sys/dev/pci/virtio_pci.c
483
int reg;
sys/dev/pci/virtio_pci.c
487
reg = PCI_MAPREG_START + i * 4;
sys/dev/pci/virtio_pci.c
488
type = pci_mapreg_type(sc->sc_pc, sc->sc_ptag, reg);
sys/dev/pci/virtio_pci.c
489
if (pci_mapreg_map(pa, reg, type, 0, &sc->sc_bars_iot[j],
sys/dev/pci/xhci_pci.c
131
pcireg_t reg;
sys/dev/pci/xhci_pci.c
134
reg = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_CBMEM);
sys/dev/pci/xhci_pci.c
135
if (pci_mapreg_map(pa, PCI_CBMEM, reg, 0, &psc->sc.iot, &psc->sc.ioh,
sys/dev/pci/yds.c
1600
u_int32_t reg;
sys/dev/pci/yds.c
1622
reg = pci_conf_read(pc, sc->sc_pcitag, YDS_PCI_DSCTRL);
sys/dev/pci/yds.c
1623
pci_conf_write(pc, sc->sc_pcitag, YDS_PCI_DSCTRL, reg | YDS_DSCTRL_WRST);
sys/dev/pci/yds.c
1630
reg = pci_conf_read(pc, sc->sc_pcitag, YDS_PCI_DSCTRL);
sys/dev/pci/yds.c
1632
reg & ~YDS_DSCTRL_CRST);
sys/dev/pci/yds.c
1682
reg | YDS_DSCTRL_CRST);
sys/dev/pci/yds.c
1685
reg & ~YDS_DSCTRL_CRST);
sys/dev/pci/yds.c
548
pcireg_t reg;
sys/dev/pci/yds.c
557
reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, YDS_PCI_LEGACY);
sys/dev/pci/yds.c
558
reg &= ~0x8133c03f; /* these bits are out of interest */
sys/dev/pci/yds.c
559
reg |= (YDS_PCI_EX_LEGACY_IMOD | YDS_PCI_LEGACY_FMEN |
sys/dev/pci/yds.c
562
reg |= YDS_PCI_EX_LEGACY_SMOD_DISABLE;
sys/dev/pci/yds.c
564
pci_conf_write(sc->sc_pc, sc->sc_pcitag, YDS_PCI_LEGACY, reg);
sys/dev/pci/yds.c
573
YDS_PCI_LEGACY, reg | (i << (0+16)));
sys/dev/pci/yds.c
590
reg |= (i << (0+16));
sys/dev/pci/yds.c
596
reg &= ~YDS_PCI_LEGACY_FMEN;
sys/dev/pci/yds.c
598
YDS_PCI_LEGACY, reg);
sys/dev/pci/yds.c
610
YDS_PCI_LEGACY, reg | (i << (4+16)));
sys/dev/pci/yds.c
626
reg |= (i << (4+16));
sys/dev/pci/yds.c
632
reg &= ~(YDS_PCI_LEGACY_MEN | YDS_PCI_LEGACY_MIEN);
sys/dev/pci/yds.c
634
YDS_PCI_LEGACY, reg);
sys/dev/pci/yds.c
650
pcireg_t reg;
sys/dev/pci/yds.c
694
reg = pci_conf_read(pc, pa->pa_tag, YDS_PCI_LEGACY);
sys/dev/pci/yds.c
696
reg & YDS_PCI_LEGACY_LAD);
sys/dev/pci/yds.c
815
yds_read_codec(void *sc_, u_int8_t reg, u_int16_t *data)
sys/dev/pci/yds.c
819
YWRITE2(sc->sc, AC97_CMD_ADDR, AC97_CMD_READ | AC97_ID(sc->id) | reg);
sys/dev/pci/yds.c
840
yds_write_codec(void *sc_, u_int8_t reg, u_int16_t data)
sys/dev/pci/yds.c
844
YWRITE2(sc->sc, AC97_CMD_ADDR, AC97_CMD_WRITE | AC97_ID(sc->id) | reg);
sys/dev/pci/yds.c
864
pcireg_t reg;
sys/dev/pci/yds.c
867
reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, YDS_PCI_DSCTRL);
sys/dev/pci/yds.c
868
if (reg & 0x03) {
sys/dev/pci/yds.c
870
YDS_PCI_DSCTRL, reg & ~0x03);
sys/dev/pci/yds.c
872
YDS_PCI_DSCTRL, reg | 0x03);
sys/dev/pci/yds.c
874
YDS_PCI_DSCTRL, reg & ~0x03);
sys/dev/pcmcia/com_pcmcia.c
360
int reg;
sys/dev/pcmcia/com_pcmcia.c
364
reg = pcmcia_ccr_read(pf, PCMCIA_CCR_OPTION);
sys/dev/pcmcia/com_pcmcia.c
365
if (reg & 0x08) {
sys/dev/pcmcia/com_pcmcia.c
366
reg &= ~0x08;
sys/dev/pcmcia/com_pcmcia.c
367
pcmcia_ccr_write(pf, PCMCIA_CCR_OPTION, reg);
sys/dev/pcmcia/if_ep_pcmcia.c
202
int reg;
sys/dev/pcmcia/if_ep_pcmcia.c
206
reg = pcmcia_ccr_read(pf, PCMCIA_CCR_OPTION);
sys/dev/pcmcia/if_ep_pcmcia.c
207
if (reg & 0x08) {
sys/dev/pcmcia/if_ep_pcmcia.c
208
reg &= ~0x08;
sys/dev/pcmcia/if_ep_pcmcia.c
209
pcmcia_ccr_write(pf, PCMCIA_CCR_OPTION, reg);
sys/dev/pcmcia/if_malovar.h
20
#define MALO_READ_1(sc, reg) \
sys/dev/pcmcia/if_malovar.h
21
bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg))
sys/dev/pcmcia/if_malovar.h
22
#define MALO_READ_2(sc, reg) \
sys/dev/pcmcia/if_malovar.h
23
bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, (reg))
sys/dev/pcmcia/if_malovar.h
24
#define MALO_READ_MULTI_2(sc, reg, off, size) \
sys/dev/pcmcia/if_malovar.h
25
bus_space_read_raw_multi_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (off), \
sys/dev/pcmcia/if_malovar.h
27
#define MALO_WRITE_1(sc, reg, val) \
sys/dev/pcmcia/if_malovar.h
28
bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/pcmcia/if_malovar.h
29
#define MALO_WRITE_2(sc, reg, val) \
sys/dev/pcmcia/if_malovar.h
30
bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
sys/dev/pcmcia/if_malovar.h
31
#define MALO_WRITE_MULTI_2(sc, reg, off, size) \
sys/dev/pcmcia/if_malovar.h
32
bus_space_write_raw_multi_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (off), \
sys/dev/pcmcia/if_xe.c
891
xe_mdi_read(struct device *self, int phy, int reg)
sys/dev/pcmcia/if_xe.c
903
xe_mdi_pulse_bits(sc, reg, 5); /* PHY register */
sys/dev/pcmcia/if_xe.c
913
("xe_mdi_read: phy %d reg %d -> %x\n", phy, reg, data));
sys/dev/pcmcia/if_xe.c
919
xe_mdi_write(struct device *self, int phy, int reg, int value)
sys/dev/pcmcia/if_xe.c
929
xe_mdi_pulse_bits(sc, reg, 5); /* PHY register */
sys/dev/pcmcia/if_xe.c
935
("xe_mdi_write: phy %d reg %d val %x\n", phy, reg, value));
sys/dev/pcmcia/pcmcia.c
392
int reg;
sys/dev/pcmcia/pcmcia.c
457
reg = (pf->cfe->number & PCMCIA_CCR_OPTION_CFINDEX);
sys/dev/pcmcia/pcmcia.c
458
reg |= PCMCIA_CCR_OPTION_LEVIREQ;
sys/dev/pcmcia/pcmcia.c
460
reg |= PCMCIA_CCR_OPTION_FUNC_ENABLE;
sys/dev/pcmcia/pcmcia.c
462
reg |= PCMCIA_CCR_OPTION_ADDR_DECODE;
sys/dev/pcmcia/pcmcia.c
464
reg |= PCMCIA_CCR_OPTION_IREQ_ENABLE;
sys/dev/pcmcia/pcmcia.c
468
pcmcia_ccr_write(pf, PCMCIA_CCR_OPTION, reg);
sys/dev/pcmcia/pcmcia.c
470
reg = 0;
sys/dev/pcmcia/pcmcia.c
473
reg |= PCMCIA_CCR_STATUS_IOIS8;
sys/dev/pcmcia/pcmcia.c
475
reg |= PCMCIA_CCR_STATUS_AUDIO;
sys/dev/pcmcia/pcmcia.c
476
pcmcia_ccr_write(pf, PCMCIA_CCR_STATUS, reg);
sys/dev/pcmcia/pcmcia.c
588
int reg;
sys/dev/pcmcia/pcmcia.c
626
reg = pcmcia_ccr_read(pf, PCMCIA_CCR_OPTION);
sys/dev/pcmcia/pcmcia.c
627
reg |= PCMCIA_CCR_OPTION_ADDR_DECODE;
sys/dev/pcmcia/pcmcia.c
628
pcmcia_ccr_write(pf, PCMCIA_CCR_OPTION, reg);
sys/dev/pcmcia/pcmcia.c
638
int s, ihcnt, hiipl, reg;
sys/dev/pcmcia/pcmcia.c
720
reg = pcmcia_ccr_read(pf, PCMCIA_CCR_OPTION);
sys/dev/pcmcia/pcmcia.c
721
reg |= PCMCIA_CCR_OPTION_IREQ_ENABLE;
sys/dev/pcmcia/pcmcia.c
722
pcmcia_ccr_write(pf, PCMCIA_CCR_OPTION, reg);
sys/dev/pcmcia/pcmcia.c
724
reg = pcmcia_ccr_read(pf, PCMCIA_CCR_STATUS);
sys/dev/pcmcia/pcmcia.c
725
reg |= PCMCIA_CCR_STATUS_INTRACK;
sys/dev/pcmcia/pcmcia.c
726
pcmcia_ccr_write(pf, PCMCIA_CCR_STATUS, reg);
sys/dev/pcmcia/pcmcia.c
738
int s, reg, ihcnt, hiipl;
sys/dev/pcmcia/pcmcia.c
779
reg = pcmcia_ccr_read(pf, PCMCIA_CCR_OPTION);
sys/dev/pcmcia/pcmcia.c
780
reg &= ~PCMCIA_CCR_OPTION_IREQ_ENABLE;
sys/dev/pcmcia/pcmcia.c
781
pcmcia_ccr_write(pf, PCMCIA_CCR_OPTION, reg);
sys/dev/pcmcia/pcmcia.c
828
int reg, ret, ret2;
sys/dev/pcmcia/pcmcia.c
843
reg = pcmcia_ccr_read(pf, PCMCIA_CCR_STATUS);
sys/dev/pcmcia/pcmcia.c
844
if (reg & PCMCIA_CCR_STATUS_INTR) {
sys/dev/pcmcia/pcmcia.c
848
reg = pcmcia_ccr_read(pf, PCMCIA_CCR_STATUS);
sys/dev/pcmcia/pcmcia.c
851
reg, reg & ~PCMCIA_CCR_STATUS_INTR);
sys/dev/pcmcia/pcmcia.c
854
reg & ~PCMCIA_CCR_STATUS_INTR);
sys/dev/pcmcia/pcmcia_cis.c
1060
reg = pcmcia_tuple_read_1(tuple, idx);
sys/dev/pcmcia/pcmcia_cis.c
1066
if (reg & PCMCIA_TPCE_IF_MWAIT)
sys/dev/pcmcia/pcmcia_cis.c
1068
if (reg & PCMCIA_TPCE_IF_RDYBSY)
sys/dev/pcmcia/pcmcia_cis.c
1070
if (reg & PCMCIA_TPCE_IF_WP)
sys/dev/pcmcia/pcmcia_cis.c
1072
if (reg & PCMCIA_TPCE_IF_BVD)
sys/dev/pcmcia/pcmcia_cis.c
1074
cfe->iftype = reg & PCMCIA_TPCE_IF_IFTYPE;
sys/dev/pcmcia/pcmcia_cis.c
1076
reg = pcmcia_tuple_read_1(tuple, idx);
sys/dev/pcmcia/pcmcia_cis.c
1079
power = reg & PCMCIA_TPCE_FS_POWER_MASK;
sys/dev/pcmcia/pcmcia_cis.c
1080
timing = reg & PCMCIA_TPCE_FS_TIMING;
sys/dev/pcmcia/pcmcia_cis.c
1081
iospace = reg & PCMCIA_TPCE_FS_IOSPACE;
sys/dev/pcmcia/pcmcia_cis.c
1082
irq = reg & PCMCIA_TPCE_FS_IRQ;
sys/dev/pcmcia/pcmcia_cis.c
1083
memspace = reg & PCMCIA_TPCE_FS_MEMSPACE_MASK;
sys/dev/pcmcia/pcmcia_cis.c
1084
misc = reg & PCMCIA_TPCE_FS_MISC;
sys/dev/pcmcia/pcmcia_cis.c
1090
reg = pcmcia_tuple_read_1(tuple, idx);
sys/dev/pcmcia/pcmcia_cis.c
1095
if ((reg >> j) & 0x01) {
sys/dev/pcmcia/pcmcia_cis.c
1113
reg = pcmcia_tuple_read_1(tuple, idx);
sys/dev/pcmcia/pcmcia_cis.c
1116
if ((reg & PCMCIA_TPCE_TD_RESERVED_MASK) !=
sys/dev/pcmcia/pcmcia_cis.c
1119
if ((reg & PCMCIA_TPCE_TD_RDYBSY_MASK) !=
sys/dev/pcmcia/pcmcia_cis.c
1122
if ((reg & PCMCIA_TPCE_TD_WAIT_MASK) !=
sys/dev/pcmcia/pcmcia_cis.c
1133
reg = pcmcia_tuple_read_1(tuple, idx);
sys/dev/pcmcia/pcmcia_cis.c
1138
if (reg & PCMCIA_TPCE_IO_BUSWIDTH_8BIT)
sys/dev/pcmcia/pcmcia_cis.c
1140
if (reg & PCMCIA_TPCE_IO_BUSWIDTH_16BIT)
sys/dev/pcmcia/pcmcia_cis.c
1143
reg & PCMCIA_TPCE_IO_IOADDRLINES_MASK;
sys/dev/pcmcia/pcmcia_cis.c
1145
if (reg & PCMCIA_TPCE_IO_HASRANGE) {
sys/dev/pcmcia/pcmcia_cis.c
1146
reg = pcmcia_tuple_read_1(tuple, idx);
sys/dev/pcmcia/pcmcia_cis.c
1149
cfe->num_iospace = 1 + (reg &
sys/dev/pcmcia/pcmcia_cis.c
1162
switch (reg & PCMCIA_TPCE_IO_RANGE_ADDRSIZE_MASK) {
sys/dev/pcmcia/pcmcia_cis.c
1179
switch (reg &
sys/dev/pcmcia/pcmcia_cis.c
1214
reg = pcmcia_tuple_read_1(tuple, idx);
sys/dev/pcmcia/pcmcia_cis.c
1220
if (reg & PCMCIA_TPCE_IR_SHARE)
sys/dev/pcmcia/pcmcia_cis.c
1222
if (reg & PCMCIA_TPCE_IR_PULSE)
sys/dev/pcmcia/pcmcia_cis.c
1224
if (reg & PCMCIA_TPCE_IR_LEVEL)
sys/dev/pcmcia/pcmcia_cis.c
1227
if (reg & PCMCIA_TPCE_IR_HASMASK) {
sys/dev/pcmcia/pcmcia_cis.c
1238
(1 << (reg & PCMCIA_TPCE_IR_IRQ));
sys/dev/pcmcia/pcmcia_cis.c
1271
reg = pcmcia_tuple_read_1(tuple, idx);
sys/dev/pcmcia/pcmcia_cis.c
1274
cfe->num_memspace = (reg &
sys/dev/pcmcia/pcmcia_cis.c
1287
((reg & PCMCIA_TPCE_MS_LENGTH_SIZE_MASK) >>
sys/dev/pcmcia/pcmcia_cis.c
1290
((reg & PCMCIA_TPCE_MS_CARDADDR_SIZE_MASK) >>
sys/dev/pcmcia/pcmcia_cis.c
1293
(reg & PCMCIA_TPCE_MS_HOSTADDR) ? cardaddrsize : 0;
sys/dev/pcmcia/pcmcia_cis.c
1340
reg = pcmcia_tuple_read_1(tuple, idx);
sys/dev/pcmcia/pcmcia_cis.c
1346
if (reg & PCMCIA_TPCE_MI_PWRDOWN)
sys/dev/pcmcia/pcmcia_cis.c
1348
if (reg & PCMCIA_TPCE_MI_READONLY)
sys/dev/pcmcia/pcmcia_cis.c
1350
if (reg & PCMCIA_TPCE_MI_AUDIO)
sys/dev/pcmcia/pcmcia_cis.c
1352
cfe->maxtwins = reg & PCMCIA_TPCE_MI_MAXTWINS;
sys/dev/pcmcia/pcmcia_cis.c
1354
while (reg & PCMCIA_TPCE_MI_EXT) {
sys/dev/pcmcia/pcmcia_cis.c
1355
reg = pcmcia_tuple_read_1(tuple, idx);
sys/dev/pcmcia/pcmcia_cis.c
746
u_int reg, dtype, dspeed;
sys/dev/pcmcia/pcmcia_cis.c
748
reg = pcmcia_tuple_read_1(tuple, 0);
sys/dev/pcmcia/pcmcia_cis.c
749
dtype = reg & PCMCIA_DTYPE_MASK;
sys/dev/pcmcia/pcmcia_cis.c
750
dspeed = reg & PCMCIA_DSPEED_MASK;
sys/dev/pcmcia/pcmcia_cis.c
910
u_int reg, rasz, rmsz, rfsz;
sys/dev/pcmcia/pcmcia_cis.c
913
reg = pcmcia_tuple_read_1(tuple, 0);
sys/dev/pcmcia/pcmcia_cis.c
914
rasz = 1 + ((reg & PCMCIA_TPCC_RASZ_MASK) >>
sys/dev/pcmcia/pcmcia_cis.c
916
rmsz = 1 + ((reg & PCMCIA_TPCC_RMSZ_MASK) >>
sys/dev/pcmcia/pcmcia_cis.c
918
rfsz = ((reg & PCMCIA_TPCC_RFSZ_MASK) >>
sys/dev/pcmcia/pcmcia_cis.c
972
u_int reg, reg2;
sys/dev/pcmcia/pcmcia_cis.c
979
reg = pcmcia_tuple_read_1(tuple, idx);
sys/dev/pcmcia/pcmcia_cis.c
981
intface = reg & PCMCIA_TPCE_INDX_INTFACE;
sys/dev/pcmcia/pcmcia_cis.c
982
def = reg & PCMCIA_TPCE_INDX_DEFAULT;
sys/dev/pcmcia/pcmcia_cis.c
983
num = reg & PCMCIA_TPCE_INDX_NUM_MASK;
sys/dev/pv/viomb.c
385
u_int32_t reg;
sys/dev/pv/viomb.c
388
reg = virtio_read_device_config_4(vsc, VIRTIO_BALLOON_CONFIG_NUM_PAGES);
sys/dev/pv/viomb.c
389
sc->sc_npages = letoh32(reg);
sys/dev/pv/viomb.c
390
reg = virtio_read_device_config_4(vsc, VIRTIO_BALLOON_CONFIG_ACTUAL);
sys/dev/pv/viomb.c
391
sc->sc_actual = letoh32(reg);
sys/dev/sbus/agten.c
353
ibm561_write(struct agten_softc *sc, u_int32_t reg, u_int32_t value)
sys/dev/sbus/agten.c
359
*(volatile u_int32_t *)(sc->sc_p9100 + P9100_RAMDAC_REGISTER(reg)) =
sys/dev/sbus/be.c
1232
be_mii_readreg(struct device *self, int phy, int reg)
sys/dev/sbus/be.c
1244
be_mii_sendbits(sc, phy, reg, 5);
sys/dev/sbus/be.c
1260
be_mii_writereg(struct device *self, int phy, int reg, int val)
sys/dev/sbus/be.c
1272
be_mii_sendbits(sc, phy, reg, 5);
sys/dev/sbus/bwtwo.c
92
#define FBC_READ(sc, reg) \
sys/dev/sbus/bwtwo.c
93
bus_space_read_1((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg))
sys/dev/sbus/bwtwo.c
94
#define FBC_WRITE(sc, reg, val) \
sys/dev/sbus/bwtwo.c
95
bus_space_write_1((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), (val))
sys/dev/sbus/cgsixreg.h
314
#define BT_WRITE(sc, reg, val) \
sys/dev/sbus/cgsixreg.h
315
bus_space_write_4((sc)->sc_bustag, (sc)->sc_bt_regs, (reg), (val))
sys/dev/sbus/cgsixreg.h
316
#define BT_READ(sc, reg) \
sys/dev/sbus/cgsixreg.h
317
bus_space_read_4((sc)->sc_bustag, (sc)->sc_bt_regs, (reg))
sys/dev/sbus/cgsixreg.h
318
#define BT_BARRIER(sc,reg,flags) \
sys/dev/sbus/cgsixreg.h
319
bus_space_barrier((sc)->sc_bustag, (sc)->sc_bt_regs, (reg), \
sys/dev/sbus/cgthree.c
114
#define FBC_READ(sc, reg) \
sys/dev/sbus/cgthree.c
115
bus_space_read_1((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg))
sys/dev/sbus/cgthree.c
116
#define FBC_WRITE(sc, reg, val) \
sys/dev/sbus/cgthree.c
117
bus_space_write_1((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), (val))
sys/dev/sbus/cgthree.c
75
#define BT_WRITE(sc, reg, val) \
sys/dev/sbus/cgthree.c
76
bus_space_write_4((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), (val))
sys/dev/sbus/cgthree.c
77
#define BT_READ(sc, reg) \
sys/dev/sbus/cgthree.c
78
bus_space_read_4((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg))
sys/dev/sbus/cgthree.c
79
#define BT_BARRIER(sc,reg,flags) \
sys/dev/sbus/cgthree.c
80
bus_space_barrier((sc)->sc_bustag, (sc)->sc_ctrl_regs, (reg), \
sys/dev/sbus/cs4231.c
1188
u_int8_t reg, status;
sys/dev/sbus/cs4231.c
1210
reg = cs4231_read(sc, CS_IRQ_STATUS);
sys/dev/sbus/cs4231.c
1211
if (reg & CS_AFS_PI) {
sys/dev/sbus/cs4231.c
1215
if (reg & CS_AFS_CI) {
sys/dev/sbus/esp_sbus.c
554
esp_read_reg(struct ncr53c9x_softc *sc, int reg)
sys/dev/sbus/esp_sbus.c
559
v = bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4);
sys/dev/sbus/esp_sbus.c
561
if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag)
sys/dev/sbus/esp_sbus.c
562
printf("RD:%x <%s> %x\n", reg * 4,
sys/dev/sbus/esp_sbus.c
563
((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v);
sys/dev/sbus/esp_sbus.c
569
esp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v)
sys/dev/sbus/esp_sbus.c
574
if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag)
sys/dev/sbus/esp_sbus.c
575
printf("WR:%x <%s> %x\n", reg * 4,
sys/dev/sbus/esp_sbus.c
576
((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v);
sys/dev/sbus/esp_sbus.c
578
bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v);
sys/dev/sbus/esp_sbus.c
582
esp_rdreg1(struct ncr53c9x_softc *sc, int reg)
sys/dev/sbus/esp_sbus.c
586
return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg));
sys/dev/sbus/esp_sbus.c
590
esp_wrreg1(struct ncr53c9x_softc *sc, int reg, u_char v)
sys/dev/sbus/esp_sbus.c
594
bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v);
sys/dev/sbus/magma.c
217
#define CD1400_READ_REG(cd,reg) \
sys/dev/sbus/magma.c
218
bus_space_read_1((cd)->cd_regt, (cd)->cd_regh, (reg))
sys/dev/sbus/magma.c
219
#define CD1400_WRITE_REG(cd,reg,value) \
sys/dev/sbus/magma.c
220
bus_space_write_1((cd)->cd_regt, (cd)->cd_regh, (reg), (value))
sys/dev/sdmmc/if_bwfm_sdio.c
255
uint32_t reg;
sys/dev/sdmmc/if_bwfm_sdio.c
313
reg = bwfm_sdio_read_1(sc, BWFM_SDIO_FUNC1_SLEEPCSR);
sys/dev/sdmmc/if_bwfm_sdio.c
314
if (!(reg & BWFM_SDIO_FUNC1_SLEEPCSR_KSO)) {
sys/dev/sdmmc/if_bwfm_sdio.c
315
reg |= BWFM_SDIO_FUNC1_SLEEPCSR_KSO;
sys/dev/sdmmc/if_bwfm_sdio.c
316
bwfm_sdio_write_1(sc, BWFM_SDIO_FUNC1_SLEEPCSR, reg);
sys/dev/sdmmc/if_bwfm_sdio.c
352
uint32_t clk, reg;
sys/dev/sdmmc/if_bwfm_sdio.c
453
reg = bwfm_sdio_read_1(sc, BWFM_SDIO_FUNC1_WAKEUPCTRL);
sys/dev/sdmmc/if_bwfm_sdio.c
454
reg |= BWFM_SDIO_FUNC1_WAKEUPCTRL_HTWAIT;
sys/dev/sdmmc/if_bwfm_sdio.c
455
bwfm_sdio_write_1(sc, BWFM_SDIO_FUNC1_WAKEUPCTRL, reg);
sys/dev/sdmmc/if_bwfm_sdio.c
876
uint32_t reg, char *data, size_t size)
sys/dev/sdmmc/if_bwfm_sdio.c
884
err = sdmmc_io_read_region_1(sf, reg, data, size);
sys/dev/sdmmc/if_bwfm_sdio.c
886
err = sdmmc_io_read_multi_1(sf, reg, data, size);
sys/dev/sdmmc/if_bwfm_sdio.c
896
uint32_t reg, char *data, size_t size)
sys/dev/sdmmc/if_bwfm_sdio.c
903
err = sdmmc_io_write_region_1(sf, reg, data, size);
sys/dev/sdmmc/if_bwfm_sdio.c
912
bwfm_sdio_ram_read_write(struct bwfm_sdio_softc *sc, uint32_t reg,
sys/dev/sdmmc/if_bwfm_sdio.c
921
sbaddr = reg + off;
sys/dev/sdmmc/if_bwfm_sdio.c
972
bwfm_sdio_dev_read(struct bwfm_sdio_softc *sc, uint32_t reg)
sys/dev/sdmmc/if_bwfm_sdio.c
976
return bwfm_sdio_read_4(sc, core->co_base + reg);
sys/dev/sdmmc/if_bwfm_sdio.c
980
bwfm_sdio_dev_write(struct bwfm_sdio_softc *sc, uint32_t reg, uint32_t val)
sys/dev/sdmmc/if_bwfm_sdio.c
984
bwfm_sdio_write_4(sc, core->co_base + reg, val);
sys/dev/sdmmc/if_bwfm_sdio.c
988
bwfm_sdio_buscore_read(struct bwfm_softc *bwfm, uint32_t reg)
sys/dev/sdmmc/if_bwfm_sdio.c
991
return bwfm_sdio_read_4(sc, reg);
sys/dev/sdmmc/if_bwfm_sdio.c
995
bwfm_sdio_buscore_write(struct bwfm_softc *bwfm, uint32_t reg, uint32_t val)
sys/dev/sdmmc/if_bwfm_sdio.c
998
bwfm_sdio_write_4(sc, reg, val);
sys/dev/sdmmc/sdhc.c
162
uint32_t reg;
sys/dev/sdmmc/sdhc.c
165
reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3);
sys/dev/sdmmc/sdhc.c
166
return (reg >> ((offset & 3) * 8)) & 0xff;
sys/dev/sdmmc/sdhc.c
175
uint32_t reg;
sys/dev/sdmmc/sdhc.c
178
reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2);
sys/dev/sdmmc/sdhc.c
179
return (reg >> ((offset & 2) * 8)) & 0xffff;
sys/dev/sdmmc/sdhc.c
188
uint32_t reg;
sys/dev/sdmmc/sdhc.c
191
reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3);
sys/dev/sdmmc/sdhc.c
192
reg &= ~(0xff << ((offset & 3) * 8));
sys/dev/sdmmc/sdhc.c
193
reg |= (value << ((offset & 3) * 8));
sys/dev/sdmmc/sdhc.c
194
bus_space_write_4(hp->iot, hp->ioh, offset & ~3, reg);
sys/dev/sdmmc/sdhc.c
204
uint32_t reg;
sys/dev/sdmmc/sdhc.c
225
reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2);
sys/dev/sdmmc/sdhc.c
226
reg &= ~(0xffff << ((offset & 2) * 8));
sys/dev/sdmmc/sdhc.c
227
reg |= (value << ((offset & 2) * 8));
sys/dev/sdmmc/sdhc.c
228
bus_space_write_4(hp->iot, hp->ioh, offset & ~2, reg);
sys/dev/sdmmc/sdhc.c
73
#define HREAD1(hp, reg) \
sys/dev/sdmmc/sdhc.c
74
(sdhc_read_1((hp), (reg)))
sys/dev/sdmmc/sdhc.c
75
#define HREAD2(hp, reg) \
sys/dev/sdmmc/sdhc.c
76
(sdhc_read_2((hp), (reg)))
sys/dev/sdmmc/sdhc.c
77
#define HREAD4(hp, reg) \
sys/dev/sdmmc/sdhc.c
776
int reg;
sys/dev/sdmmc/sdhc.c
78
(bus_space_read_4((hp)->iot, (hp)->ioh, (reg)))
sys/dev/sdmmc/sdhc.c
784
reg = HREAD1(hp, SDHC_HOST_CTL);
sys/dev/sdmmc/sdhc.c
785
reg &= ~SDHC_4BIT_MODE;
sys/dev/sdmmc/sdhc.c
787
reg &= ~SDHC_8BIT_MODE;
sys/dev/sdmmc/sdhc.c
79
#define HWRITE1(hp, reg, val) \
sys/dev/sdmmc/sdhc.c
790
reg |= SDHC_4BIT_MODE;
sys/dev/sdmmc/sdhc.c
793
reg |= SDHC_8BIT_MODE;
sys/dev/sdmmc/sdhc.c
795
HWRITE1(hp, SDHC_HOST_CTL, reg);
sys/dev/sdmmc/sdhc.c
80
sdhc_write_1((hp), (reg), (val))
sys/dev/sdmmc/sdhc.c
81
#define HWRITE2(hp, reg, val) \
sys/dev/sdmmc/sdhc.c
82
sdhc_write_2((hp), (reg), (val))
sys/dev/sdmmc/sdhc.c
83
#define HWRITE4(hp, reg, val) \
sys/dev/sdmmc/sdhc.c
84
bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val))
sys/dev/sdmmc/sdhc.c
85
#define HCLR1(hp, reg, bits) \
sys/dev/sdmmc/sdhc.c
86
HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits))
sys/dev/sdmmc/sdhc.c
87
#define HCLR2(hp, reg, bits) \
sys/dev/sdmmc/sdhc.c
88
HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits))
sys/dev/sdmmc/sdhc.c
89
#define HSET1(hp, reg, bits) \
sys/dev/sdmmc/sdhc.c
90
HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits))
sys/dev/sdmmc/sdhc.c
91
#define HSET2(hp, reg, bits) \
sys/dev/sdmmc/sdhc.c
92
HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits))
sys/dev/sdmmc/sdmmc_cis.c
100
cis->product = sdmmc_io_read_1(sf0, reg++);
sys/dev/sdmmc/sdmmc_cis.c
101
cis->product |= sdmmc_io_read_1(sf0, reg++) << 8;
sys/dev/sdmmc/sdmmc_cis.c
107
reg += tpllen;
sys/dev/sdmmc/sdmmc_cis.c
113
cis->cis1_major = sdmmc_io_read_1(sf0, reg++);
sys/dev/sdmmc/sdmmc_cis.c
114
cis->cis1_minor = sdmmc_io_read_1(sf0, reg++);
sys/dev/sdmmc/sdmmc_cis.c
118
ch = sdmmc_io_read_1(sf0, reg + i);
sys/dev/sdmmc/sdmmc_cis.c
130
reg += tpllen - 2;
sys/dev/sdmmc/sdmmc_cis.c
136
reg += tpllen;
sys/dev/sdmmc/sdmmc_cis.c
42
int reg;
sys/dev/sdmmc/sdmmc_cis.c
46
reg = SD_IO_CCCR_CISPTR + (sf->number * SD_IO_CCCR_SIZE);
sys/dev/sdmmc/sdmmc_cis.c
47
cisptr |= sdmmc_io_read_1(sf0, reg + 0) << 0;
sys/dev/sdmmc/sdmmc_cis.c
48
cisptr |= sdmmc_io_read_1(sf0, reg + 1) << 8;
sys/dev/sdmmc/sdmmc_cis.c
49
cisptr |= sdmmc_io_read_1(sf0, reg + 2) << 16;
sys/dev/sdmmc/sdmmc_cis.c
58
int reg;
sys/dev/sdmmc/sdmmc_cis.c
64
reg = (int)sdmmc_cisptr(sf);
sys/dev/sdmmc/sdmmc_cis.c
65
if (reg < SD_IO_CIS_START ||
sys/dev/sdmmc/sdmmc_cis.c
66
reg >= (SD_IO_CIS_START+SD_IO_CIS_SIZE-16)) {
sys/dev/sdmmc/sdmmc_cis.c
67
printf("%s: bad CIS ptr %#x\n", DEVNAME(sf->sc), reg);
sys/dev/sdmmc/sdmmc_cis.c
72
tplcode = sdmmc_io_read_1(sf0, reg++);
sys/dev/sdmmc/sdmmc_cis.c
78
tpllen = sdmmc_io_read_1(sf0, reg++);
sys/dev/sdmmc/sdmmc_cis.c
85
reg += tpllen;
sys/dev/sdmmc/sdmmc_cis.c
88
cis->function = sdmmc_io_read_1(sf0, reg);
sys/dev/sdmmc/sdmmc_cis.c
89
reg += tpllen;
sys/dev/sdmmc/sdmmc_cis.c
95
reg += tpllen;
sys/dev/sdmmc/sdmmc_cis.c
98
cis->manufacturer = sdmmc_io_read_1(sf0, reg++);
sys/dev/sdmmc/sdmmc_cis.c
99
cis->manufacturer |= sdmmc_io_read_1(sf0, reg++) << 8;
sys/dev/sdmmc/sdmmc_io.c
364
int reg, u_char *datap, int arg)
sys/dev/sdmmc/sdmmc_io.c
379
arg |= (reg & SD_ARG_CMD52_REG_MASK) <<
sys/dev/sdmmc/sdmmc_io.c
404
bus_dmamap_t dmap, int reg, u_char *datap, int len, int arg)
sys/dev/sdmmc/sdmmc_io.c
421
arg |= (reg & SD_ARG_CMD53_REG_MASK) <<
sys/dev/sdmmc/sdmmc_io.c
450
int reg, u_char *datap, int len, int arg)
sys/dev/sdmmc/sdmmc_io.c
455
return sdmmc_io_rw_extended_subr(sc, sf, NULL, reg,
sys/dev/sdmmc/sdmmc_io.c
472
error = sdmmc_io_rw_extended_subr(sc, sf, sc->sc_dmap, reg,
sys/dev/sdmmc/sdmmc_io.c
488
sdmmc_io_read_1(struct sdmmc_function *sf, int reg)
sys/dev/sdmmc/sdmmc_io.c
494
(void)sdmmc_io_rw_direct(sf->sc, sf, reg, (u_char *)&data,
sys/dev/sdmmc/sdmmc_io.c
500
sdmmc_io_write_1(struct sdmmc_function *sf, int reg, u_int8_t data)
sys/dev/sdmmc/sdmmc_io.c
504
(void)sdmmc_io_rw_direct(sf->sc, sf, reg, (u_char *)&data,
sys/dev/sdmmc/sdmmc_io.c
509
sdmmc_io_read_2(struct sdmmc_function *sf, int reg)
sys/dev/sdmmc/sdmmc_io.c
515
(void)sdmmc_io_rw_extended_subr(sf->sc, sf, NULL, reg,
sys/dev/sdmmc/sdmmc_io.c
521
sdmmc_io_write_2(struct sdmmc_function *sf, int reg, u_int16_t data)
sys/dev/sdmmc/sdmmc_io.c
525
(void)sdmmc_io_rw_extended_subr(sf->sc, sf, NULL, reg,
sys/dev/sdmmc/sdmmc_io.c
530
sdmmc_io_read_4(struct sdmmc_function *sf, int reg)
sys/dev/sdmmc/sdmmc_io.c
536
(void)sdmmc_io_rw_extended_subr(sf->sc, sf, NULL, reg,
sys/dev/sdmmc/sdmmc_io.c
542
sdmmc_io_write_4(struct sdmmc_function *sf, int reg, u_int32_t data)
sys/dev/sdmmc/sdmmc_io.c
546
(void)sdmmc_io_rw_extended_subr(sf->sc, sf, NULL, reg,
sys/dev/sdmmc/sdmmc_io.c
551
sdmmc_io_read_multi_1(struct sdmmc_function *sf, int reg, u_char *data,
sys/dev/sdmmc/sdmmc_io.c
561
error = sdmmc_io_rw_extended(sf->sc, sf, reg, data,
sys/dev/sdmmc/sdmmc_io.c
570
error = sdmmc_io_rw_extended(sf->sc, sf, reg, data, datalen,
sys/dev/sdmmc/sdmmc_io.c
577
sdmmc_io_write_multi_1(struct sdmmc_function *sf, int reg, u_char *data,
sys/dev/sdmmc/sdmmc_io.c
587
error = sdmmc_io_rw_extended(sf->sc, sf, reg, data,
sys/dev/sdmmc/sdmmc_io.c
596
error = sdmmc_io_rw_extended(sf->sc, sf, reg, data, datalen,
sys/dev/sdmmc/sdmmc_io.c
603
sdmmc_io_read_region_1(struct sdmmc_function *sf, int reg, u_char *data,
sys/dev/sdmmc/sdmmc_io.c
613
error = sdmmc_io_rw_extended(sf->sc, sf, reg, data,
sys/dev/sdmmc/sdmmc_io.c
618
reg += blocks * sf->cur_blklen;
sys/dev/sdmmc/sdmmc_io.c
624
error = sdmmc_io_rw_extended(sf->sc, sf, reg, data, datalen,
sys/dev/sdmmc/sdmmc_io.c
631
sdmmc_io_write_region_1(struct sdmmc_function *sf, int reg, u_char *data,
sys/dev/sdmmc/sdmmc_io.c
641
error = sdmmc_io_rw_extended(sf->sc, sf, reg, data,
sys/dev/sdmmc/sdmmc_io.c
646
reg += blocks * sf->cur_blklen;
sys/dev/sdmmc/sdmmc_io.c
652
error = sdmmc_io_rw_extended(sf->sc, sf, reg, data, datalen,
sys/dev/sdmmc/sdmmc_io.c
660
int reg, u_char *datap)
sys/dev/sdmmc/sdmmc_io.c
665
return sdmmc_io_rw_direct(sc, sf, reg, datap,
sys/dev/spdmem.c
345
spdmem_read(struct spdmem_softc *sc, uint8_t reg)
sys/dev/spdmem.c
347
return (*sc->sc_read)(sc, reg);
sys/dev/tc/asc.c
77
asc_read_reg(struct ncr53c9x_softc *sc, int reg)
sys/dev/tc/asc.c
83
reg * sizeof(u_int32_t)) & 0xff;
sys/dev/tc/asc.c
89
asc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val)
sys/dev/tc/asc.c
94
reg * sizeof(u_int32_t), val);
sys/dev/tc/bba.c
585
bba_codec_iwrite(struct am7930_softc *sc, int reg, uint8_t val)
sys/dev/tc/bba.c
587
DPRINTF(("bba_codec_iwrite(): sc=%p, reg=%02x, val=%02x\n", sc, reg, val));
sys/dev/tc/bba.c
588
bba_codec_dwrite(sc, AM7930_DREG_CR, reg);
sys/dev/tc/bba.c
594
bba_codec_iwrite16(struct am7930_softc *sc, int reg, uint16_t val)
sys/dev/tc/bba.c
596
DPRINTF(("bba_codec_iwrite16(): sc=%p, reg=%02x, val=%04x\n", sc, reg, val));
sys/dev/tc/bba.c
597
bba_codec_dwrite(sc, AM7930_DREG_CR, reg);
sys/dev/tc/bba.c
605
bba_codec_iread(struct am7930_softc *sc, int reg)
sys/dev/tc/bba.c
609
DPRINTF(("bba_codec_iread(): sc=%p, reg=%02x\n", sc, reg));
sys/dev/tc/bba.c
610
bba_codec_dwrite(sc, AM7930_DREG_CR, reg);
sys/dev/tc/bba.c
619
bba_codec_iread16(struct am7930_softc *sc, int reg)
sys/dev/tc/bba.c
623
DPRINTF(("bba_codec_iread16(): sc=%p, reg=%02x\n", sc, reg));
sys/dev/tc/bba.c
624
bba_codec_dwrite(sc, AM7930_DREG_CR, reg);
sys/dev/tc/bba.c
634
bba_codec_dwrite(struct am7930_softc *asc, int reg, uint8_t val)
sys/dev/tc/bba.c
639
bus_space_write_4(sc->sc_bst, sc->sc_codec_bsh, reg << 2, val << 8);
sys/dev/tc/bba.c
641
bus_space_write_4(sc->sc_bst, sc->sc_codec_bsh, reg << 6, val);
sys/dev/tc/bba.c
647
bba_codec_dread(struct am7930_softc *asc, int reg)
sys/dev/tc/bba.c
652
return (bus_space_read_4(sc->sc_bst, sc->sc_codec_bsh, reg << 2) >> 8) &
sys/dev/tc/bba.c
655
return bus_space_read_4(sc->sc_bst, sc->sc_codec_bsh, reg << 6) & 0xff;
sys/dev/tc/zs_ioasic.c
532
zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
sys/dev/tc/zs_ioasic.c
537
zc->zc_csr = reg << 8;
sys/dev/tc/zs_ioasic.c
547
zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
sys/dev/tc/zs_ioasic.c
551
zc->zc_csr = reg << 8;
sys/dev/usb/dwc2/dwc2_core.h
1268
#define dwc2_readl(hsotg, reg) \
sys/dev/usb/dwc2/dwc2_core.h
1270
(reg))
sys/dev/usb/dwc2/dwc2_core.h
1271
#define dwc2_writel(hsotg, data, reg) \
sys/dev/usb/dwc2/dwc2_core.h
1273
(reg), (data))
sys/dev/usb/dwc2/dwc2_core.h
1391
int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
sys/dev/usb/dwc2/dwc2_core.h
1393
int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
sys/dev/usb/if_athn_usb.c
1050
uint32_t reg, imask;
sys/dev/usb/if_athn_usb.c
1060
reg = AR_READ(sc, AR_RX_FILTER);
sys/dev/usb/if_athn_usb.c
1061
reg = (reg & ~AR_RX_FILTER_MYBEACON) |
sys/dev/usb/if_athn_usb.c
1063
AR_WRITE(sc, AR_RX_FILTER, reg);
sys/dev/usb/if_athn_usb.c
1120
reg = AR_READ(sc, AR_RX_FILTER);
sys/dev/usb/if_athn_usb.c
1121
reg = (reg & ~AR_RX_FILTER_BEACON) |
sys/dev/usb/if_athn_usb.c
1123
AR_WRITE(sc, AR_RX_FILTER, reg);
sys/dev/usb/if_aue.c
253
#define AUE_SETBIT(sc, reg, x) \
sys/dev/usb/if_aue.c
254
aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) | (x))
sys/dev/usb/if_aue.c
256
#define AUE_CLRBIT(sc, reg, x) \
sys/dev/usb/if_aue.c
257
aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) & ~(x))
sys/dev/usb/if_aue.c
260
aue_csr_read_1(struct aue_softc *sc, int reg)
sys/dev/usb/if_aue.c
272
USETW(req.wIndex, reg);
sys/dev/usb/if_aue.c
279
sc->aue_dev.dv_xname, reg, usbd_errstr(err)));
sys/dev/usb/if_aue.c
287
aue_csr_read_2(struct aue_softc *sc, int reg)
sys/dev/usb/if_aue.c
299
USETW(req.wIndex, reg);
sys/dev/usb/if_aue.c
306
sc->aue_dev.dv_xname, reg, usbd_errstr(err)));
sys/dev/usb/if_aue.c
314
aue_csr_write_1(struct aue_softc *sc, int reg, int aval)
sys/dev/usb/if_aue.c
327
USETW(req.wIndex, reg);
sys/dev/usb/if_aue.c
334
sc->aue_dev.dv_xname, reg, usbd_errstr(err)));
sys/dev/usb/if_aue.c
342
aue_csr_write_2(struct aue_softc *sc, int reg, int aval)
sys/dev/usb/if_aue.c
355
USETW(req.wIndex, reg);
sys/dev/usb/if_aue.c
362
sc->aue_dev.dv_xname, reg, usbd_errstr(err)));
sys/dev/usb/if_aue.c
429
aue_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/usb/if_aue.c
462
aue_csr_write_1(sc, AUE_PHY_CTL, reg | AUE_PHYCTL_READ);
sys/dev/usb/if_aue.c
476
sc->aue_dev.dv_xname, __func__, phy, reg, val));
sys/dev/usb/if_aue.c
483
aue_miibus_writereg(struct device *dev, int phy, int reg, int data)
sys/dev/usb/if_aue.c
497
sc->aue_dev.dv_xname, __func__, phy, reg, data));
sys/dev/usb/if_aue.c
502
aue_csr_write_1(sc, AUE_PHY_CTL, reg | AUE_PHYCTL_WRITE);
sys/dev/usb/if_axe.c
259
axe_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/usb/if_axe.c
277
DPRINTF(("axe_miibus_readreg: phy 0x%x reg 0x%x\n", phy, reg));
sys/dev/usb/if_axe.c
292
err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, val);
sys/dev/usb/if_axe.c
301
phy, reg, UGETW(val)));
sys/dev/usb/if_axe.c
304
if ((sc->axe_flags & AX772) != 0 && reg == MII_BMSR) {
sys/dev/usb/if_axe.c
318
axe_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/usb/if_axe.c
333
err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, uval);
sys/dev/usb/if_axen.c
169
axen_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/usb/if_axen.c
185
err = axen_cmd(sc, AXEN_CMD_MII_READ_REG, reg, phy, &val);
sys/dev/usb/if_axen.c
195
phy, reg, ival));
sys/dev/usb/if_axen.c
197
if (reg == MII_BMSR) {
sys/dev/usb/if_axen.c
205
axen_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/usb/if_axen.c
219
err = axen_cmd(sc, AXEN_CMD_MII_WRITE_REG, reg, phy, &uval);
sys/dev/usb/if_axen.c
222
phy, reg, val));
sys/dev/usb/if_cue.c
142
#define CUE_SETBIT(sc, reg, x) \
sys/dev/usb/if_cue.c
143
cue_csr_write_1(sc, reg, cue_csr_read_1(sc, reg) | (x))
sys/dev/usb/if_cue.c
145
#define CUE_CLRBIT(sc, reg, x) \
sys/dev/usb/if_cue.c
146
cue_csr_write_1(sc, reg, cue_csr_read_1(sc, reg) & ~(x))
sys/dev/usb/if_cue.c
149
cue_csr_read_1(struct cue_softc *sc, int reg)
sys/dev/usb/if_cue.c
161
USETW(req.wIndex, reg);
sys/dev/usb/if_cue.c
168
sc->cue_dev.dv_xname, reg, usbd_errstr(err)));
sys/dev/usb/if_cue.c
173
sc->cue_dev.dv_xname, reg, val));
sys/dev/usb/if_cue.c
179
cue_csr_read_2(struct cue_softc *sc, int reg)
sys/dev/usb/if_cue.c
191
USETW(req.wIndex, reg);
sys/dev/usb/if_cue.c
197
sc->cue_dev.dv_xname, reg, UGETW(val)));
sys/dev/usb/if_cue.c
201
sc->cue_dev.dv_xname, reg, usbd_errstr(err)));
sys/dev/usb/if_cue.c
209
cue_csr_write_1(struct cue_softc *sc, int reg, int val)
sys/dev/usb/if_cue.c
218
sc->cue_dev.dv_xname, reg, val));
sys/dev/usb/if_cue.c
223
USETW(req.wIndex, reg);
sys/dev/usb/if_cue.c
230
sc->cue_dev.dv_xname, reg, usbd_errstr(err)));
sys/dev/usb/if_cue.c
235
sc->cue_dev.dv_xname, reg, cue_csr_read_1(sc, reg)));
sys/dev/usb/if_cue.c
242
cue_csr_write_2(struct cue_softc *sc, int reg, int aval)
sys/dev/usb/if_cue.c
253
sc->cue_dev.dv_xname, reg, aval));
sys/dev/usb/if_cue.c
259
USETW(req.wIndex, reg);
sys/dev/usb/if_cue.c
266
sc->cue_dev.dv_xname, reg, usbd_errstr(err)));
sys/dev/usb/if_mos.c
188
mos_reg_read_1(struct mos_softc *sc, int reg)
sys/dev/usb/if_mos.c
200
USETW(req.wIndex, reg);
sys/dev/usb/if_mos.c
206
DPRINTF(("mos_reg_read_1 error, reg: %d\n", reg));
sys/dev/usb/if_mos.c
214
mos_reg_read_2(struct mos_softc *sc, int reg)
sys/dev/usb/if_mos.c
228
USETW(req.wIndex, reg);
sys/dev/usb/if_mos.c
234
DPRINTF(("mos_reg_read_2 error, reg: %d\n", reg));
sys/dev/usb/if_mos.c
242
mos_reg_write_1(struct mos_softc *sc, int reg, int aval)
sys/dev/usb/if_mos.c
256
USETW(req.wIndex, reg);
sys/dev/usb/if_mos.c
262
DPRINTF(("mos_reg_write_1 error, reg: %d\n", reg));
sys/dev/usb/if_mos.c
270
mos_reg_write_2(struct mos_softc *sc, int reg, int aval)
sys/dev/usb/if_mos.c
284
USETW(req.wIndex, reg);
sys/dev/usb/if_mos.c
290
DPRINTF(("mos_reg_write_2 error, reg: %d\n", reg));
sys/dev/usb/if_mos.c
373
mos_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/usb/if_mos.c
388
mos_reg_write_1(sc, MOS_PHY_STS, (reg & MOS_PHYSTS_PHYREG) |
sys/dev/usb/if_mos.c
407
mos_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/usb/if_mos.c
420
mos_reg_write_1(sc, MOS_PHY_STS, (reg & MOS_PHYSTS_PHYREG) |
sys/dev/usb/if_mtw.c
1007
uint16_t reg;
sys/dev/usb/if_mtw.c
1039
reg = MTW_EFUSE_DATA0 + (addr & 0xc);
sys/dev/usb/if_mtw.c
1040
if ((error = mtw_read(sc, reg, &tmp)) != 0)
sys/dev/usb/if_mtw.c
1076
mtw_rf_read(struct mtw_softc *sc, uint8_t bank, uint8_t reg, uint8_t *val)
sys/dev/usb/if_mtw.c
1095
tmp = MTW_RF_CSR_KICK | (bank & 0xf) << shift | reg << 8;
sys/dev/usb/if_mtw.c
1113
mtw_rf_write(struct mtw_softc *sc, uint8_t bank, uint8_t reg, uint8_t val)
sys/dev/usb/if_mtw.c
1133
reg << 8 | val;
sys/dev/usb/if_mtw.c
1138
mtw_bbp_read(struct mtw_softc *sc, uint8_t reg, uint8_t *val)
sys/dev/usb/if_mtw.c
1152
tmp = MTW_BBP_CSR_READ | MTW_BBP_CSR_KICK | reg << MTW_BBP_ADDR_SHIFT;
sys/dev/usb/if_mtw.c
1170
mtw_bbp_write(struct mtw_softc *sc, uint8_t reg, uint8_t val)
sys/dev/usb/if_mtw.c
1184
tmp = MTW_BBP_CSR_KICK | reg << MTW_BBP_ADDR_SHIFT | val;
sys/dev/usb/if_mtw.c
1430
uint32_t reg;
sys/dev/usb/if_mtw.c
1433
reg = val;
sys/dev/usb/if_mtw.c
1435
reg |= (uint32_t)val << 16;
sys/dev/usb/if_mtw.c
1437
sc->txpow20mhz[ridx] = reg;
sys/dev/usb/if_mtw.c
1438
sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
sys/dev/usb/if_mtw.c
1439
sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
sys/dev/usb/if_mtw.c
195
uint32_t reg;
sys/dev/usb/if_mtw.c
202
uint8_t reg;
sys/dev/usb/if_mtw.c
216
uint8_t reg;
sys/dev/usb/if_mtw.c
2831
if ((error = mtw_bbp_write(sc, mt7601_def_bbp[i].reg,
sys/dev/usb/if_mtw.c
2848
error = mtw_rf_write(sc, 0, mt7601_rf_bank0[i].reg,
sys/dev/usb/if_mtw.c
2855
error = mtw_rf_write(sc, 4, mt7601_rf_bank4[i].reg,
sys/dev/usb/if_mtw.c
2862
error = mtw_rf_write(sc, 5, mt7601_rf_bank5[i].reg,
sys/dev/usb/if_mtw.c
3155
mtw_write(sc, mt7601_def_mac[i].reg,
sys/dev/usb/if_mtw.c
877
mtw_read(struct mtw_softc *sc, uint16_t reg, uint32_t *val)
sys/dev/usb/if_mtw.c
882
error = mtw_read_region_1(sc, reg,
sys/dev/usb/if_mtw.c
892
mtw_read_cfg(struct mtw_softc *sc, uint16_t reg, uint32_t *val)
sys/dev/usb/if_mtw.c
901
USETW(req.wIndex, reg);
sys/dev/usb/if_mtw.c
913
mtw_read_region_1(struct mtw_softc *sc, uint16_t reg,
sys/dev/usb/if_mtw.c
921
USETW(req.wIndex, reg);
sys/dev/usb/if_mtw.c
927
mtw_write_2(struct mtw_softc *sc, uint16_t reg, uint16_t val)
sys/dev/usb/if_mtw.c
934
USETW(req.wIndex, reg);
sys/dev/usb/if_mtw.c
940
mtw_write(struct mtw_softc *sc, uint16_t reg, uint32_t val)
sys/dev/usb/if_mtw.c
944
if ((error = mtw_write_2(sc, reg, val & 0xffff)) == 0)
sys/dev/usb/if_mtw.c
945
error = mtw_write_2(sc, reg + 2, val >> 16);
sys/dev/usb/if_mtw.c
950
mtw_write_cfg(struct mtw_softc *sc, uint16_t reg, uint32_t val)
sys/dev/usb/if_mtw.c
958
USETW(req.wIndex, reg);
sys/dev/usb/if_mtw.c
979
mtw_write_region_1(struct mtw_softc *sc, uint16_t reg,
sys/dev/usb/if_mtw.c
987
USETW(req.wIndex, reg);
sys/dev/usb/if_mtw.c
993
mtw_set_region_4(struct mtw_softc *sc, uint16_t reg, uint32_t val, int count)
sys/dev/usb/if_mtw.c
997
for (; count > 0 && error == 0; count--, reg += 4)
sys/dev/usb/if_mtw.c
998
error = mtw_write(sc, reg, val);
sys/dev/usb/if_mue.c
1012
uint32_t h = 0, hashtbl[MUE_DP_SEL_VHF_HASH_LEN], reg, rxfilt;
sys/dev/usb/if_mue.c
1017
reg = (sc->mue_flags & LAN7500) ? MUE_RFE_CTL : MUE_7800_RFE_CTL;
sys/dev/usb/if_mue.c
1018
rxfilt = mue_csr_read(sc, reg);
sys/dev/usb/if_mue.c
1047
mue_csr_write(sc, reg, rxfilt);
sys/dev/usb/if_mue.c
134
#define MUE_SETBIT(sc, reg, x) \
sys/dev/usb/if_mue.c
135
mue_csr_write(sc, reg, mue_csr_read(sc, reg) | (x))
sys/dev/usb/if_mue.c
137
#define MUE_CLRBIT(sc, reg, x) \
sys/dev/usb/if_mue.c
138
mue_csr_write(sc, reg, mue_csr_read(sc, reg) & ~(x))
sys/dev/usb/if_mue.c
174
mue_csr_read(struct mue_softc *sc, uint32_t reg)
sys/dev/usb/if_mue.c
187
USETW(req.wIndex, reg);
sys/dev/usb/if_mue.c
193
sc->mue_dev.dv_xname, reg, usbd_errstr(err)));
sys/dev/usb/if_mue.c
201
mue_csr_write(struct mue_softc *sc, uint32_t reg, uint32_t aval)
sys/dev/usb/if_mue.c
214
USETW(req.wIndex, reg);
sys/dev/usb/if_mue.c
220
sc->mue_dev.dv_xname, reg, usbd_errstr(err)));
sys/dev/usb/if_mue.c
264
mue_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/usb/if_mue.c
280
MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
sys/dev/usb/if_mue.c
292
mue_miibus_writereg(struct device *dev, int phy, int reg, int data)
sys/dev/usb/if_mue.c
308
MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
sys/dev/usb/if_mue.c
672
uint32_t val, reg;
sys/dev/usb/if_mue.c
674
reg = (sc->mue_flags & LAN7500) ? MUE_ADDR_FILTX : MUE_7800_ADDR_FILTX;
sys/dev/usb/if_mue.c
678
mue_csr_write(sc, reg + 4, val);
sys/dev/usb/if_mue.c
681
mue_csr_write(sc, reg, val | MUE_ADDR_FILTX_VALID);
sys/dev/usb/if_otus.c
1707
otus_phy_get_def(struct otus_softc *sc, uint32_t reg)
sys/dev/usb/if_otus.c
1712
if (AR_PHY(ar5416_phy_regs[i]) == reg)
sys/dev/usb/if_otus.c
858
otus_write(struct otus_softc *sc, uint32_t reg, uint32_t val)
sys/dev/usb/if_otus.c
860
sc->write_buf[sc->write_idx].reg = htole32(reg);
sys/dev/usb/if_otus.c
917
uint32_t regs[8], reg;
sys/dev/usb/if_otus.c
923
reg = AR_EEPROM_OFFSET;
sys/dev/usb/if_otus.c
925
for (j = 0; j < 8; j++, reg += 4)
sys/dev/usb/if_otus.c
926
regs[j] = htole32(reg);
sys/dev/usb/if_otusreg.h
102
#define AR_PHY(reg) (AR_PHY_BASE + (reg) * 4)
sys/dev/usb/if_otusreg.h
971
uint32_t reg;
sys/dev/usb/if_ral.c
1363
ural_read(struct ural_softc *sc, uint16_t reg)
sys/dev/usb/if_ral.c
1372
USETW(req.wIndex, reg);
sys/dev/usb/if_ral.c
1385
ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len)
sys/dev/usb/if_ral.c
1393
USETW(req.wIndex, reg);
sys/dev/usb/if_ral.c
1404
ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val)
sys/dev/usb/if_ral.c
1412
USETW(req.wIndex, reg);
sys/dev/usb/if_ral.c
1423
ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len)
sys/dev/usb/if_ral.c
1431
USETW(req.wIndex, reg);
sys/dev/usb/if_ral.c
1442
ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val)
sys/dev/usb/if_ral.c
1456
tmp = reg << 8 | val;
sys/dev/usb/if_ral.c
1461
ural_bbp_read(struct ural_softc *sc, uint8_t reg)
sys/dev/usb/if_ral.c
1466
val = RAL_BBP_WRITE | reg << 8;
sys/dev/usb/if_ral.c
1481
ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val)
sys/dev/usb/if_ral.c
1495
tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3);
sys/dev/usb/if_ral.c
1500
sc->rf_regs[reg] = val;
sys/dev/usb/if_ral.c
1502
DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff));
sys/dev/usb/if_ral.c
156
uint16_t reg;
sys/dev/usb/if_ral.c
163
uint8_t reg;
sys/dev/usb/if_ral.c
1821
ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val);
sys/dev/usb/if_ral.c
1826
if (sc->bbp_prom[i].reg == 0xff)
sys/dev/usb/if_ral.c
1828
ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
sys/dev/usb/if_ral.c
1897
ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val);
sys/dev/usb/if_ralvar.h
115
uint8_t reg;
sys/dev/usb/if_rsu.c
1744
uint32_t reg;
sys/dev/usb/if_rsu.c
1804
reg = rsu_read_2(sc, R92S_SYS_CLKR);
sys/dev/usb/if_rsu.c
1805
reg = (reg & ~R92S_SWHW_SEL) | R92S_FWHW_SEL;
sys/dev/usb/if_rsu.c
1806
rsu_write_2(sc, R92S_SYS_CLKR, reg);
sys/dev/usb/if_rsu.c
1826
uint32_t reg;
sys/dev/usb/if_rsu.c
1835
reg = rsu_read_2(sc, R92S_SYS_CLKR);
sys/dev/usb/if_rsu.c
1836
if (reg & R92S_FWHW_SEL) {
sys/dev/usb/if_rsu.c
1838
reg & ~(R92S_SWHW_SEL | R92S_FWHW_SEL));
sys/dev/usb/if_rsu.c
1847
reg = rsu_read_1(sc, R92S_AFE_MISC);
sys/dev/usb/if_rsu.c
1848
rsu_write_1(sc, R92S_AFE_MISC, reg | R92S_AFE_MISC_BGEN);
sys/dev/usb/if_rsu.c
1849
rsu_write_1(sc, R92S_AFE_MISC, reg | R92S_AFE_MISC_BGEN |
sys/dev/usb/if_rsu.c
1873
reg = rsu_read_1(sc, R92S_AFE_PLL_CTRL);
sys/dev/usb/if_rsu.c
1874
rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x11);
sys/dev/usb/if_rsu.c
1876
rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x51);
sys/dev/usb/if_rsu.c
1878
rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x11);
sys/dev/usb/if_rsu.c
1905
reg = rsu_read_2(sc, R92S_SYS_CLKR);
sys/dev/usb/if_rsu.c
1906
reg = (reg & ~R92S_SWHW_SEL) | R92S_FWHW_SEL;
sys/dev/usb/if_rsu.c
1907
rsu_write_2(sc, R92S_SYS_CLKR, reg);
sys/dev/usb/if_rsu.c
1922
reg = rsu_read_1(sc, R92S_TCR);
sys/dev/usb/if_rsu.c
1923
if ((reg & (R92S_TCR_IMEM_CHK_RPT | R92S_TCR_EMEM_CHK_RPT)) ==
sys/dev/usb/if_rsu.c
1930
reg = rsu_read_1(sc, R92S_CR);
sys/dev/usb/if_rsu.c
1931
rsu_write_1(sc, R92S_CR, reg & ~R92S_CR_TXDMA_EN);
sys/dev/usb/if_rsu.c
1933
rsu_write_1(sc, R92S_CR, reg | R92S_CR_TXDMA_EN);
sys/dev/usb/if_rsu.c
2012
uint32_t reg;
sys/dev/usb/if_rsu.c
2065
reg = rsu_read_2(sc, R92S_TCR);
sys/dev/usb/if_rsu.c
2066
if (reg & R92S_TCR_IMEM_CODE_DONE)
sys/dev/usb/if_rsu.c
2070
if (ntries == 10 || !(reg & R92S_TCR_IMEM_CHK_RPT)) {
sys/dev/usb/if_rsu.c
2086
reg = rsu_read_2(sc, R92S_TCR);
sys/dev/usb/if_rsu.c
2087
if (reg & R92S_TCR_EMEM_CODE_DONE)
sys/dev/usb/if_rsu.c
2091
if (ntries == 10 || !(reg & R92S_TCR_EMEM_CHK_RPT)) {
sys/dev/usb/if_rsu.c
622
uint32_t reg;
sys/dev/usb/if_rsu.c
625
reg = rsu_read_4(sc, R92S_EFUSE_CTRL);
sys/dev/usb/if_rsu.c
626
reg = RW(reg, R92S_EFUSE_CTRL_ADDR, addr);
sys/dev/usb/if_rsu.c
627
reg &= ~R92S_EFUSE_CTRL_VALID;
sys/dev/usb/if_rsu.c
628
rsu_write_4(sc, R92S_EFUSE_CTRL, reg);
sys/dev/usb/if_rsu.c
631
reg = rsu_read_4(sc, R92S_EFUSE_CTRL);
sys/dev/usb/if_rsu.c
632
if (reg & R92S_EFUSE_CTRL_VALID)
sys/dev/usb/if_rsu.c
633
return (MS(reg, R92S_EFUSE_CTRL_DATA));
sys/dev/usb/if_rsu.c
646
uint32_t reg;
sys/dev/usb/if_rsu.c
651
reg = rsu_read_1(sc, R92S_EE_9346CR);
sys/dev/usb/if_rsu.c
652
if ((reg & (R92S_9356SEL | R92S_EEPROM_EN)) != R92S_EEPROM_EN)
sys/dev/usb/if_rsu.c
656
reg = rsu_read_1(sc, R92S_EFUSE_TEST + 3);
sys/dev/usb/if_rsu.c
657
rsu_write_1(sc, R92S_EFUSE_TEST + 3, reg | 0x80);
sys/dev/usb/if_rsu.c
659
rsu_write_1(sc, R92S_EFUSE_TEST + 3, reg & ~0x80);
sys/dev/usb/if_rsu.c
664
reg = rsu_efuse_read_1(sc, addr);
sys/dev/usb/if_rsu.c
665
if (reg == 0xff)
sys/dev/usb/if_rsu.c
668
off = reg >> 4;
sys/dev/usb/if_rsu.c
669
msk = reg & 0xf;
sys/dev/usb/if_rsu.c
773
uint32_t reg;
sys/dev/usb/if_rsu.c
781
reg = rsu_read_1(sc, R92S_GPIO_CTRL);
sys/dev/usb/if_rsu.c
782
if (reg != 0xff && (reg & R92S_GPIO_WPS))
sys/dev/usb/if_rsu.c
787
reg = rsu_read_4(sc, R92S_IOCMD_DATA);
sys/dev/usb/if_rsu.c
788
DPRINTFN(8, ("RSSI=%d%%\n", reg >> 4));
sys/dev/usb/if_rum.c
1379
rum_read(struct rum_softc *sc, uint16_t reg)
sys/dev/usb/if_rum.c
1383
rum_read_multi(sc, reg, &val, sizeof val);
sys/dev/usb/if_rum.c
1389
rum_read_multi(struct rum_softc *sc, uint16_t reg, void *buf, int len)
sys/dev/usb/if_rum.c
1397
USETW(req.wIndex, reg);
sys/dev/usb/if_rum.c
1408
rum_write(struct rum_softc *sc, uint16_t reg, uint32_t val)
sys/dev/usb/if_rum.c
1412
rum_write_multi(sc, reg, &tmp, sizeof tmp);
sys/dev/usb/if_rum.c
1416
rum_write_multi(struct rum_softc *sc, uint16_t reg, void *buf, size_t len)
sys/dev/usb/if_rum.c
1428
USETW(req.wIndex, reg + offset);
sys/dev/usb/if_rum.c
1440
rum_bbp_write(struct rum_softc *sc, uint8_t reg, uint8_t val)
sys/dev/usb/if_rum.c
1454
tmp = RT2573_BBP_BUSY | (reg & 0x7f) << 8 | val;
sys/dev/usb/if_rum.c
1459
rum_bbp_read(struct rum_softc *sc, uint8_t reg)
sys/dev/usb/if_rum.c
1473
val = RT2573_BBP_BUSY | RT2573_BBP_READ | reg << 8;
sys/dev/usb/if_rum.c
1488
rum_rf_write(struct rum_softc *sc, uint8_t reg, uint32_t val)
sys/dev/usb/if_rum.c
1503
(reg & 3);
sys/dev/usb/if_rum.c
1507
sc->rf_regs[reg] = val;
sys/dev/usb/if_rum.c
1509
DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0xfffff));
sys/dev/usb/if_rum.c
187
uint32_t reg;
sys/dev/usb/if_rum.c
1878
if (sc->bbp_prom[i].reg == 0 || sc->bbp_prom[i].reg == 0xff)
sys/dev/usb/if_rum.c
1880
DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg,
sys/dev/usb/if_rum.c
1906
rum_bbp_write(sc, rum_def_bbp[i].reg, rum_def_bbp[i].val);
sys/dev/usb/if_rum.c
1910
if (sc->bbp_prom[i].reg == 0 || sc->bbp_prom[i].reg == 0xff)
sys/dev/usb/if_rum.c
1912
rum_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
sys/dev/usb/if_rum.c
1931
rum_write(sc, rum_def_mac[i].reg, rum_def_mac[i].val);
sys/dev/usb/if_rum.c
194
uint8_t reg;
sys/dev/usb/if_rum.c
2102
uint16_t reg = RT2573_MCU_CODE_BASE;
sys/dev/usb/if_rum.c
2106
for (; size >= 4; reg += 4, ucode += 4, size -= 4)
sys/dev/usb/if_rum.c
2107
rum_write(sc, reg, UGETDW(ucode));
sys/dev/usb/if_rumvar.h
117
uint8_t reg;
sys/dev/usb/if_run.c
1022
reg = RT3070_EFUSE_DATA3 - (addr & 0xc);
sys/dev/usb/if_run.c
1023
if ((error = run_read(sc, reg, &tmp)) != 0)
sys/dev/usb/if_run.c
1036
uint16_t reg;
sys/dev/usb/if_run.c
1068
reg = RT3070_EFUSE_DATA3 - (addr & 0xc);
sys/dev/usb/if_run.c
1069
if ((error = run_read(sc, reg, &tmp)) != 0)
sys/dev/usb/if_run.c
1105
run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val)
sys/dev/usb/if_run.c
1121
(val & 0x3fffff) << 2 | (reg & 3);
sys/dev/usb/if_run.c
1126
run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val)
sys/dev/usb/if_run.c
1140
tmp = RT3070_RF_KICK | reg << 8;
sys/dev/usb/if_run.c
1158
run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val)
sys/dev/usb/if_run.c
1172
tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;
sys/dev/usb/if_run.c
1177
run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val)
sys/dev/usb/if_run.c
1191
tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8;
sys/dev/usb/if_run.c
1209
run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val)
sys/dev/usb/if_run.c
1223
tmp = RT2860_BBP_CSR_KICK | reg << 8 | val;
sys/dev/usb/if_run.c
1450
sc->bbp[i].reg = val >> 8;
sys/dev/usb/if_run.c
1451
DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg,
sys/dev/usb/if_run.c
1460
sc->rf[i].reg = val >> 8;
sys/dev/usb/if_run.c
1461
DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg,
sys/dev/usb/if_run.c
1567
uint32_t reg;
sys/dev/usb/if_run.c
1570
reg = val;
sys/dev/usb/if_run.c
1572
reg |= (uint32_t)val << 16;
sys/dev/usb/if_run.c
1574
sc->txpow20mhz[ridx] = reg;
sys/dev/usb/if_run.c
1575
sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
sys/dev/usb/if_run.c
1576
sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
sys/dev/usb/if_run.c
3447
uint8_t reg, rf, txpow_bound;
sys/dev/usb/if_run.c
3501
run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg,
sys/dev/usb/if_run.c
3515
reg = 2;
sys/dev/usb/if_run.c
3520
run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg,
sys/dev/usb/if_run.c
3526
run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg,
sys/dev/usb/if_run.c
3535
reg = 3;
sys/dev/usb/if_run.c
3542
rf |= (reg << 6);
sys/dev/usb/if_run.c
3551
rf |= (reg << 6);
sys/dev/usb/if_run.c
3821
run_bbp_write(sc, rt5592_def_bbp[i].reg,
sys/dev/usb/if_run.c
3830
run_bbp_write(sc, rt5390_def_bbp[i].reg,
sys/dev/usb/if_run.c
3883
run_bbp_write(sc, rt2860_def_bbp[i].reg,
sys/dev/usb/if_run.c
3928
run_rt3070_rf_write(sc, rt3572_def_rf[i].reg,
sys/dev/usb/if_run.c
3933
run_rt3070_rf_write(sc, rt3070_def_rf[i].reg,
sys/dev/usb/if_run.c
4067
run_rt3070_rf_write(sc, rt3593_def_rf[i].reg,
sys/dev/usb/if_run.c
4123
run_rt3070_rf_write(sc, rt5592_def_rf[i].reg,
sys/dev/usb/if_run.c
4130
run_rt3070_rf_write(sc, rt5392_def_rf[i].reg,
sys/dev/usb/if_run.c
4143
run_rt3070_rf_write(sc, rt5390_def_rf[i].reg,
sys/dev/usb/if_run.c
4303
if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff)
sys/dev/usb/if_run.c
4305
run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);
sys/dev/usb/if_run.c
432
uint32_t reg;
sys/dev/usb/if_run.c
439
uint8_t reg;
sys/dev/usb/if_run.c
4571
run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val);
sys/dev/usb/if_run.c
4649
if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)
sys/dev/usb/if_run.c
4651
run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
sys/dev/usb/if_run.c
487
uint8_t reg;
sys/dev/usb/if_run.c
510
uint8_t reg;
sys/dev/usb/if_run.c
901
run_read(struct run_softc *sc, uint16_t reg, uint32_t *val)
sys/dev/usb/if_run.c
906
error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof tmp);
sys/dev/usb/if_run.c
915
run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len)
sys/dev/usb/if_run.c
922
USETW(req.wIndex, reg);
sys/dev/usb/if_run.c
928
run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val)
sys/dev/usb/if_run.c
935
USETW(req.wIndex, reg);
sys/dev/usb/if_run.c
941
run_write(struct run_softc *sc, uint16_t reg, uint32_t val)
sys/dev/usb/if_run.c
945
if ((error = run_write_2(sc, reg, val & 0xffff)) == 0)
sys/dev/usb/if_run.c
946
error = run_write_2(sc, reg + 2, val >> 16);
sys/dev/usb/if_run.c
951
run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf,
sys/dev/usb/if_run.c
962
error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8);
sys/dev/usb/if_run.c
970
USETW(req.wIndex, reg);
sys/dev/usb/if_run.c
977
run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count)
sys/dev/usb/if_run.c
981
for (; count > 0 && error == 0; count--, reg += 4)
sys/dev/usb/if_run.c
982
error = run_write(sc, reg, val);
sys/dev/usb/if_run.c
991
uint16_t reg;
sys/dev/usb/if_runvar.h
171
uint8_t reg;
sys/dev/usb/if_smsc.c
264
smsc_wait_for_bits(struct smsc_softc *sc, uint32_t reg, uint32_t bits)
sys/dev/usb/if_smsc.c
270
if ((err = smsc_read_reg(sc, reg, &val)) != 0)
sys/dev/usb/if_smsc.c
281
smsc_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/usb/if_smsc.c
293
addr = (phy << 11) | (reg << 6) | SMSC_MII_READ;
sys/dev/usb/if_smsc.c
307
smsc_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/usb/if_smsc.c
324
addr = (phy << 11) | (reg << 6) | SMSC_MII_WRITE;
sys/dev/usb/if_uaq.c
354
uaq_read_1(struct uaq_softc *sc, uint8_t cmd, uint16_t reg, uint16_t index)
sys/dev/usb/if_uaq.c
358
uaq_read_mem(sc, cmd, reg, index, &val, 1);
sys/dev/usb/if_uaq.c
359
DPRINTFN(4, ("uaq_read_1: cmd %x reg %x index %x = %x\n", cmd, reg,
sys/dev/usb/if_uaq.c
365
uaq_read_2(struct uaq_softc *sc, uint8_t cmd, uint16_t reg, uint16_t index)
sys/dev/usb/if_uaq.c
369
uaq_read_mem(sc, cmd, reg, index, &val, 2);
sys/dev/usb/if_uaq.c
370
DPRINTFN(4, ("uaq_read_2: cmd %x reg %x index %x = %x\n", cmd, reg,
sys/dev/usb/if_uaq.c
377
uaq_read_4(struct uaq_softc *sc, uint8_t cmd, uint16_t reg, uint16_t index)
sys/dev/usb/if_uaq.c
381
uaq_read_mem(sc, cmd, reg, index, &val, 4);
sys/dev/usb/if_uaq.c
382
DPRINTFN(4, ("uaq_read_4: cmd %x reg %x index %x = %x\n", cmd, reg,
sys/dev/usb/if_uaq.c
388
uaq_write_1(struct uaq_softc *sc, uint8_t cmd, uint16_t reg, uint16_t index,
sys/dev/usb/if_uaq.c
393
DPRINTFN(4, ("uaq_write_1: cmd %x reg %x index %x: %x\n", cmd, reg,
sys/dev/usb/if_uaq.c
396
return (uaq_write_mem(sc, cmd, reg, index, &temp, 1));
sys/dev/usb/if_uaq.c
400
uaq_write_2(struct uaq_softc *sc, uint8_t cmd, uint16_t reg, uint16_t index,
sys/dev/usb/if_uaq.c
405
DPRINTFN(4, ("uaq_write_2: cmd %x reg %x index %x: %x\n", cmd, reg,
sys/dev/usb/if_uaq.c
408
return (uaq_write_mem(sc, cmd, reg, index, &temp, 2));
sys/dev/usb/if_uaq.c
412
uaq_write_4(struct uaq_softc *sc, uint8_t cmd, uint16_t reg, uint16_t index,
sys/dev/usb/if_uaq.c
417
DPRINTFN(4, ("uaq_write_4: cmd %x reg %x index %x: %x\n", cmd, reg,
sys/dev/usb/if_uaq.c
420
return (uaq_write_mem(sc, cmd, reg, index, &temp, 4));
sys/dev/usb/if_uath.c
1007
uath_write_reg(struct uath_softc *sc, uint32_t reg, uint32_t val)
sys/dev/usb/if_uath.c
1012
write.reg = htobe32(reg);
sys/dev/usb/if_uath.c
1020
sc->sc_dev.dv_xname, reg);
sys/dev/usb/if_uath.c
1026
uath_write_multi(struct uath_softc *sc, uint32_t reg, const void *data,
sys/dev/usb/if_uath.c
1032
write.reg = htobe32(reg);
sys/dev/usb/if_uath.c
1041
sc->sc_dev.dv_xname, len, reg);
sys/dev/usb/if_uath.c
1047
uath_read_reg(struct uath_softc *sc, uint32_t reg, uint32_t *val)
sys/dev/usb/if_uath.c
1052
reg = htobe32(reg);
sys/dev/usb/if_uath.c
1053
error = uath_cmd_read(sc, UATH_CMD_READ_MAC, ®, sizeof reg, &read,
sys/dev/usb/if_uath.c
1057
sc->sc_dev.dv_xname, betoh32(reg));
sys/dev/usb/if_uath.c
1065
uath_read_eeprom(struct uath_softc *sc, uint32_t reg, void *odata)
sys/dev/usb/if_uath.c
1070
reg = htobe32(reg);
sys/dev/usb/if_uath.c
1071
error = uath_cmd_read(sc, UATH_CMD_READ_EEPROM, ®, sizeof reg,
sys/dev/usb/if_uath.c
1075
sc->sc_dev.dv_xname, betoh32(reg));
sys/dev/usb/if_uath.c
1594
uint32_t reg, val;
sys/dev/usb/if_uath.c
1614
for (reg = 0x09; reg <= 0x24; reg++) {
sys/dev/usb/if_uath.c
1615
if (reg == 0x0b || reg == 0x0c)
sys/dev/usb/if_uath.c
1618
if ((error = uath_read_reg(sc, reg, &val)) != 0)
sys/dev/usb/if_uath.c
1620
DPRINTFN(2, ("reg 0x%02x=0x%08x\n", reg, val));
sys/dev/usb/if_uathreg.h
125
uint32_t reg;
sys/dev/usb/if_udav.c
134
#define UDAV_SETBIT(sc, reg, x) \
sys/dev/usb/if_udav.c
135
udav_csr_write1(sc, reg, udav_csr_read1(sc, reg) | (x))
sys/dev/usb/if_udav.c
137
#define UDAV_CLRBIT(sc, reg, x) \
sys/dev/usb/if_udav.c
138
udav_csr_write1(sc, reg, udav_csr_read1(sc, reg) & ~(x))
sys/dev/usb/if_udav.c
1424
udav_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/usb/if_udav.c
1436
sc->sc_dev.dv_xname, __func__, phy, reg));
sys/dev/usb/if_udav.c
1457
UDAV_EPAR_PHY_ADR0 | (reg & UDAV_EPAR_EROA_MASK));
sys/dev/usb/if_udav.c
1475
sc->sc_dev.dv_xname, __func__, phy, reg, data16));
sys/dev/usb/if_udav.c
1481
udav_miibus_writereg(struct device *dev, int phy, int reg, int data)
sys/dev/usb/if_udav.c
1492
sc->sc_dev.dv_xname, __func__, phy, reg, data));
sys/dev/usb/if_udav.c
1513
UDAV_EPAR_PHY_ADR0 | (reg & UDAV_EPAR_EROA_MASK));
sys/dev/usb/if_ure.c
1327
uint16_t reg;
sys/dev/usb/if_ure.c
1360
reg = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB);
sys/dev/usb/if_ure.c
1361
reg &= ~URE_PWD_DN_SCALE_MASK;
sys/dev/usb/if_ure.c
1362
reg |= URE_PWD_DN_SCALE(96);
sys/dev/usb/if_ure.c
1363
ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, reg);
sys/dev/usb/if_ure.c
1389
reg = URE_LPM_TIMER_500MS;
sys/dev/usb/if_ure.c
1391
reg = URE_LPM_TIMER_500US;
sys/dev/usb/if_ure.c
1393
URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM | reg);
sys/dev/usb/if_ure.c
1395
reg = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB);
sys/dev/usb/if_ure.c
1396
reg &= ~URE_SEN_VAL_MASK;
sys/dev/usb/if_ure.c
1397
reg |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE;
sys/dev/usb/if_ure.c
1398
ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, reg);
sys/dev/usb/if_ure.c
1427
uint16_t reg;
sys/dev/usb/if_ure.c
1495
reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA);
sys/dev/usb/if_ure.c
1498
reg |= URE_CUR_LINK_OK;
sys/dev/usb/if_ure.c
1500
reg &= ~URE_CUR_LINK_OK;
sys/dev/usb/if_ure.c
1502
reg | URE_POLL_LINK_CHG);
sys/dev/usb/if_ure.c
1519
reg = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB);
sys/dev/usb/if_ure.c
1522
reg |= URE_FLOW_CTRL_PATCH_2;
sys/dev/usb/if_ure.c
1523
reg &= ~URE_AUTO_SPEEDUP;
sys/dev/usb/if_ure.c
1524
ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, reg);
sys/dev/usb/if_ure.c
1535
reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA);
sys/dev/usb/if_ure.c
1536
reg &= ~URE_CUR_LINK_OK;
sys/dev/usb/if_ure.c
1539
reg |= URE_CUR_LINK_OK;
sys/dev/usb/if_ure.c
1541
reg | URE_POLL_LINK_CHG);
sys/dev/usb/if_ure.c
1572
uint16_t reg;
sys/dev/usb/if_ure.c
1643
reg = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB);
sys/dev/usb/if_ure.c
1644
reg &= ~URE_AUTO_SPEEDUP;
sys/dev/usb/if_ure.c
1647
reg |= URE_FLOW_CTRL_PATCH_2;
sys/dev/usb/if_ure.c
1648
ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, reg);
sys/dev/usb/if_ure.c
1659
reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA);
sys/dev/usb/if_ure.c
1660
reg &= ~URE_CUR_LINK_OK;
sys/dev/usb/if_ure.c
1663
reg |= URE_CUR_LINK_OK;
sys/dev/usb/if_ure.c
1665
reg | URE_POLL_LINK_CHG);
sys/dev/usb/if_ure.c
1676
reg = ure_phy_read(sc, 0xa5b4);
sys/dev/usb/if_ure.c
1677
if (reg == 0xffff)
sys/dev/usb/if_ure.c
1679
ure_phy_write(sc, 0xa5b4, reg & ~0x8000);
sys/dev/usb/if_ure.c
1771
uint32_t reg = 0;
sys/dev/usb/if_ure.c
1861
reg = ure_read_2(sc, URE_PLA_RXFIFO_FULL, URE_MCU_TYPE_PLA);
sys/dev/usb/if_ure.c
1862
reg &= ~URE_RXFIFO_FULL_MASK;
sys/dev/usb/if_ure.c
1864
reg | 0x0008);
sys/dev/usb/if_ure.c
1938
uint16_t reg;
sys/dev/usb/if_ure.c
1942
reg = ure_phy_read(sc, URE_OCP_PHY_STATUS) &
sys/dev/usb/if_ure.c
1945
if (reg == desired)
sys/dev/usb/if_ure.c
1948
if (reg == URE_PHY_STAT_LAN_ON ||
sys/dev/usb/if_ure.c
1949
reg == URE_PHY_STAT_PWRDN ||
sys/dev/usb/if_ure.c
1950
reg == URE_PHY_STAT_EXT_INIT)
sys/dev/usb/if_ure.c
1959
return reg;
sys/dev/usb/if_ure.c
1990
uint8_t reg;
sys/dev/usb/if_ure.c
2000
reg = ure_read_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB);
sys/dev/usb/if_ure.c
2001
reg &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
sys/dev/usb/if_ure.c
2002
ure_write_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, reg);
sys/dev/usb/if_ure.c
2003
reg |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
sys/dev/usb/if_ure.c
2004
ure_write_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, reg);
sys/dev/usb/if_ure.c
214
#define URE_SETBIT_1(sc, reg, index, x) \
sys/dev/usb/if_ure.c
215
ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x))
sys/dev/usb/if_ure.c
216
#define URE_SETBIT_2(sc, reg, index, x) \
sys/dev/usb/if_ure.c
217
ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x))
sys/dev/usb/if_ure.c
218
#define URE_SETBIT_4(sc, reg, index, x) \
sys/dev/usb/if_ure.c
219
ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x))
sys/dev/usb/if_ure.c
221
#define URE_CLRBIT_1(sc, reg, index, x) \
sys/dev/usb/if_ure.c
222
ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x))
sys/dev/usb/if_ure.c
223
#define URE_CLRBIT_2(sc, reg, index, x) \
sys/dev/usb/if_ure.c
224
ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x))
sys/dev/usb/if_ure.c
225
#define URE_CLRBIT_4(sc, reg, index, x) \
sys/dev/usb/if_ure.c
226
ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x))
sys/dev/usb/if_ure.c
281
ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)
sys/dev/usb/if_ure.c
287
shift = (reg & 3) << 3;
sys/dev/usb/if_ure.c
288
reg &= ~3;
sys/dev/usb/if_ure.c
290
ure_read_mem(sc, reg, index, &temp, 4);
sys/dev/usb/if_ure.c
298
ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index)
sys/dev/usb/if_ure.c
304
shift = (reg & 2) << 3;
sys/dev/usb/if_ure.c
305
reg &= ~3;
sys/dev/usb/if_ure.c
307
ure_read_mem(sc, reg, index, &temp, 4);
sys/dev/usb/if_ure.c
315
ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index)
sys/dev/usb/if_ure.c
319
ure_read_mem(sc, reg, index, &temp, 4);
sys/dev/usb/if_ure.c
324
ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
sys/dev/usb/if_ure.c
331
shift = reg & 3;
sys/dev/usb/if_ure.c
334
if (reg & 3) {
sys/dev/usb/if_ure.c
337
reg &= ~3;
sys/dev/usb/if_ure.c
341
return (ure_write_mem(sc, reg, index | byen, &temp, 4));
sys/dev/usb/if_ure.c
345
ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
sys/dev/usb/if_ure.c
352
shift = reg & 2;
sys/dev/usb/if_ure.c
355
if (reg & 2) {
sys/dev/usb/if_ure.c
358
reg &= ~3;
sys/dev/usb/if_ure.c
362
return (ure_write_mem(sc, reg, index | byen, &temp, 4));
sys/dev/usb/if_ure.c
366
ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
sys/dev/usb/if_ure.c
371
return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4));
sys/dev/usb/if_ure.c
389
uint16_t reg;
sys/dev/usb/if_ure.c
392
reg = (addr & 0x0fff) | 0xb000;
sys/dev/usb/if_ure.c
394
return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA));
sys/dev/usb/if_ure.c
400
uint16_t reg;
sys/dev/usb/if_ure.c
403
reg = (addr & 0x0fff) | 0xb000;
sys/dev/usb/if_ure.c
405
ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data);
sys/dev/usb/if_ure.c
523
ure_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/usb/if_ure.c
532
if (reg == RL_GMEDIASTAT)
sys/dev/usb/if_ure.c
536
val = ure_phy_read(sc, URE_OCP_BASE_MII + reg * 2);
sys/dev/usb/if_ure.c
543
ure_miibus_writereg(struct device *dev, int phy, int reg, int val)
sys/dev/usb/if_ure.c
548
ure_phy_write(sc, URE_OCP_BASE_MII + reg * 2, val); /* htole16? */
sys/dev/usb/if_ure.c
596
uint32_t reg = 0;
sys/dev/usb/if_ure.c
609
reg = sc->ure_rxbufsz - URE_FRAMELEN(ifp->if_mtu);
sys/dev/usb/if_ure.c
611
reg -= sizeof(struct ure_rxpkt_v2) + URE_8157_BUF_ALIGN;
sys/dev/usb/if_ure.c
613
reg -= sizeof(struct ure_rxpkt) + URE_RX_BUF_ALIGN;
sys/dev/usb/if_ure.c
620
reg / URE_8157_BUF_ALIGN : reg / URE_RX_BUF_ALIGN);
sys/dev/usb/if_ure.c
628
reg = ure_read_2(sc, URE_USB_L1_CTRL,
sys/dev/usb/if_ure.c
630
reg &= ~0x0f;
sys/dev/usb/if_ure.c
632
URE_MCU_TYPE_USB, reg | 0x01);
sys/dev/usb/if_ure.c
636
reg / 4);
sys/dev/usb/if_ure.c
639
reg = URE_COALESCE_SUPER / 8;
sys/dev/usb/if_ure.c
642
reg = URE_COALESCE_HIGH / 8;
sys/dev/usb/if_ure.c
645
reg = URE_COALESCE_SLOW / 8;
sys/dev/usb/if_ure.c
649
reg);
sys/dev/usb/if_ure.c
689
int anar, gig, err, reg;
sys/dev/usb/if_ure.c
696
reg = ure_phy_read(sc, URE_OCP_10GBT_CTRL);
sys/dev/usb/if_ure.c
697
if (reg == 0xffff)
sys/dev/usb/if_ure.c
699
reg &= ~URE_ADV_2500TFDX;
sys/dev/usb/if_ure.c
702
reg &= ~URE_ADV_5000TFDX;
sys/dev/usb/if_ure.c
710
reg |= URE_ADV_2500TFDX;
sys/dev/usb/if_ure.c
712
reg |= URE_ADV_5000TFDX;
sys/dev/usb/if_ure.c
715
reg |= URE_ADV_2500TFDX | URE_ADV_5000TFDX;
sys/dev/usb/if_ure.c
719
reg |= URE_ADV_2500TFDX;
sys/dev/usb/if_ure.c
745
ure_phy_write(sc, URE_OCP_10GBT_CTRL, reg);
sys/dev/usb/if_ure.c
917
uint16_t reg;
sys/dev/usb/if_ure.c
920
reg = ure_read_2(sc, URE_PLA_RCR1, URE_MCU_TYPE_PLA);
sys/dev/usb/if_ure.c
921
reg &= ~(URE_INNER_VLAN | URE_OUTER_VLAN);
sys/dev/usb/if_ure.c
923
reg |= (URE_INNER_VLAN | URE_OUTER_VLAN);
sys/dev/usb/if_ure.c
924
ure_write_2(sc, URE_PLA_RCR1, URE_MCU_TYPE_PLA, reg);
sys/dev/usb/if_ure.c
926
reg = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA);
sys/dev/usb/if_ure.c
927
reg &= ~URE_CPCR_RX_VLAN;
sys/dev/usb/if_ure.c
929
reg |= URE_CPCR_RX_VLAN;
sys/dev/usb/if_ure.c
930
ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, reg);
sys/dev/usb/if_url.c
1268
url_int_miibus_readreg(struct device *dev, int phy, int reg)
sys/dev/usb/if_url.c
1279
sc->sc_dev.dv_xname, __func__, phy, reg));
sys/dev/usb/if_url.c
129
#define URL_SETBIT(sc, reg, x) \
sys/dev/usb/if_url.c
1298
switch (reg) {
sys/dev/usb/if_url.c
130
url_csr_write_1(sc, reg, url_csr_read_1(sc, reg) | (x))
sys/dev/usb/if_url.c
1300
reg = URL_BMCR;
sys/dev/usb/if_url.c
1303
reg = URL_BMSR;
sys/dev/usb/if_url.c
1311
reg = URL_ANAR;
sys/dev/usb/if_url.c
1314
reg = URL_ANLP;
sys/dev/usb/if_url.c
1317
reg = URL_MSR;
sys/dev/usb/if_url.c
132
#define URL_SETBIT2(sc, reg, x) \
sys/dev/usb/if_url.c
1321
sc->sc_dev.dv_xname, __func__, reg);
sys/dev/usb/if_url.c
1327
if (reg == URL_MSR)
sys/dev/usb/if_url.c
1328
val = url_csr_read_1(sc, reg);
sys/dev/usb/if_url.c
133
url_csr_write_2(sc, reg, url_csr_read_2(sc, reg) | (x))
sys/dev/usb/if_url.c
1330
val = url_csr_read_2(sc, reg);
sys/dev/usb/if_url.c
1334
sc->sc_dev.dv_xname, __func__, phy, reg, val));
sys/dev/usb/if_url.c
1341
url_int_miibus_writereg(struct device *dev, int phy, int reg, int data)
sys/dev/usb/if_url.c
135
#define URL_CLRBIT(sc, reg, x) \
sys/dev/usb/if_url.c
1351
sc->sc_dev.dv_xname, __func__, phy, reg, data));
sys/dev/usb/if_url.c
136
url_csr_write_1(sc, reg, url_csr_read_1(sc, reg) & ~(x))
sys/dev/usb/if_url.c
1370
switch (reg) {
sys/dev/usb/if_url.c
1372
reg = URL_BMCR;
sys/dev/usb/if_url.c
1375
reg = URL_BMSR;
sys/dev/usb/if_url.c
138
#define URL_CLRBIT2(sc, reg, x) \
sys/dev/usb/if_url.c
1382
reg = URL_ANAR;
sys/dev/usb/if_url.c
1385
reg = URL_ANLP;
sys/dev/usb/if_url.c
1388
reg = URL_MSR;
sys/dev/usb/if_url.c
139
url_csr_write_2(sc, reg, url_csr_read_2(sc, reg) & ~(x))
sys/dev/usb/if_url.c
1392
sc->sc_dev.dv_xname, __func__, reg);
sys/dev/usb/if_url.c
1397
if (reg == URL_MSR)
sys/dev/usb/if_url.c
1398
url_csr_write_1(sc, reg, data);
sys/dev/usb/if_url.c
1400
url_csr_write_2(sc, reg, data);
sys/dev/usb/if_url.c
1427
url_ext_miibus_redreg(struct device *dev, int phy, int reg)
sys/dev/usb/if_url.c
1433
sc->sc_dev.dv_xname, __func__, phy, reg));
sys/dev/usb/if_url.c
1452
(reg | URL_PHYCNT_PHYOWN) & ~URL_PHYCNT_RWCR);
sys/dev/usb/if_url.c
1464
sc->sc_dev.dv_xname, __func__, phy, reg, val));
sys/dev/usb/if_url.c
1471
url_ext_miibus_writereg(struct device *dev, int phy, int reg, int data)
sys/dev/usb/if_url.c
1476
sc->sc_dev.dv_xname, __func__, phy, reg, data));
sys/dev/usb/if_url.c
1490
url_csr_write_1(sc, URL_PHYCNT, reg | URL_PHYCNT_RWCR); /* Write */
sys/dev/usb/if_url.c
392
url_csr_read_1(struct url_softc *sc, int reg)
sys/dev/usb/if_url.c
399
return (url_mem(sc, URL_CMD_READMEM, reg, &val, 1) ? 0 : val);
sys/dev/usb/if_url.c
404
url_csr_read_2(struct url_softc *sc, int reg)
sys/dev/usb/if_url.c
412
return (url_mem(sc, URL_CMD_READMEM, reg, &val, 2) ? 0 : UGETW(val));
sys/dev/usb/if_url.c
417
url_csr_write_1(struct url_softc *sc, int reg, int aval)
sys/dev/usb/if_url.c
424
return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 1) ? -1 : 0);
sys/dev/usb/if_url.c
429
url_csr_write_2(struct url_softc *sc, int reg, int aval)
sys/dev/usb/if_url.c
438
return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 2) ? -1 : 0);
sys/dev/usb/if_url.c
443
url_csr_write_4(struct url_softc *sc, int reg, int aval)
sys/dev/usb/if_url.c
452
return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 4) ? -1 : 0);
sys/dev/usb/if_urtw.c
173
uint32_t reg;
sys/dev/usb/if_urtw.c
178
uint8_t reg;
sys/dev/usb/if_urtw.c
2028
if (rate == urtw_ratetable[i].reg)
sys/dev/usb/if_urtw.c
2042
return (urtw_ratetable[i].reg);
sys/dev/usb/if_urtw.c
2868
urtw_8225_write(sc, urtw_8225_rf_part1[i].reg,
sys/dev/usb/if_urtw.c
2892
urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg,
sys/dev/usb/if_urtw.c
2902
urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg,
sys/dev/usb/if_urtw.c
3276
urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg,
sys/dev/usb/if_urtw.c
3324
urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg,
sys/dev/usb/if_urtw.c
3333
urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg,
sys/dev/usb/if_urtw.c
3713
urtw_write8_idx_m(sc, urtw_8187b_regtbl[i].reg,
sys/dev/usb/if_urtw.c
3833
urtw_8225_write(sc, urtw_8225v2_b_rf[i].reg,
sys/dev/usb/if_urtwn.c
1770
uint32_t reg;
sys/dev/usb/if_urtwn.c
1791
reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL);
sys/dev/usb/if_urtwn.c
1792
if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) {
sys/dev/usb/if_urtwn.c
1794
reg | R92C_LDOV12D_CTRL_LDV12_EN);
sys/dev/usb/if_urtwn.c
1826
reg = urtwn_read_2(sc, R92C_CR);
sys/dev/usb/if_urtwn.c
1827
reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
sys/dev/usb/if_urtwn.c
1831
urtwn_write_2(sc, R92C_CR, reg);
sys/dev/usb/if_urtwn.c
1840
uint32_t reg;
sys/dev/usb/if_urtwn.c
1847
reg = urtwn_read_4(sc, R92C_SYS_SWR_CTRL2);
sys/dev/usb/if_urtwn.c
1848
reg &= 0xff0fffff;
sys/dev/usb/if_urtwn.c
1849
reg |= 0x00500000;
sys/dev/usb/if_urtwn.c
1850
urtwn_write_4(sc, R92C_SYS_SWR_CTRL2, reg);
sys/dev/usb/if_urtwn.c
1903
reg = urtwn_read_2(sc, R92C_CR);
sys/dev/usb/if_urtwn.c
1904
reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
sys/dev/usb/if_urtwn.c
1907
urtwn_write_2(sc, R92C_CR, reg);
sys/dev/usb/if_urtwn.c
1914
uint32_t reg;
sys/dev/usb/if_urtwn.c
1966
reg = urtwn_read_2(sc, R92C_CR);
sys/dev/usb/if_urtwn.c
1967
reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
sys/dev/usb/if_urtwn.c
1970
urtwn_write_2(sc, R92C_CR, reg);
sys/dev/usb/if_urtwn.c
1977
uint32_t reg;
sys/dev/usb/if_urtwn.c
2026
reg = urtwn_read_2(sc, R92C_CR);
sys/dev/usb/if_urtwn.c
2027
reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
sys/dev/usb/if_urtwn.c
2030
urtwn_write_2(sc, R92C_CR, reg);
sys/dev/usb/if_urtwn.c
2083
uint32_t reg;
sys/dev/usb/if_urtwn.c
2086
reg = urtwn_read_4(sc, R92C_MCUFWDL);
sys/dev/usb/if_urtwn.c
2087
reg = RW(reg, R92C_MCUFWDL_PAGE, page);
sys/dev/usb/if_urtwn.c
2088
urtwn_write_4(sc, R92C_MCUFWDL, reg);
sys/dev/usb/if_urtwn.c
2140
uint32_t reg;
sys/dev/usb/if_urtwn.c
2217
reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);
sys/dev/usb/if_urtwn.c
2218
reg &= ~R92C_TRXDMA_CTRL_QMAP_M;
sys/dev/usb/if_urtwn.c
2220
reg |= R92C_TRXDMA_CTRL_QMAP_3EP;
sys/dev/usb/if_urtwn.c
2223
reg |= R92C_TRXDMA_CTRL_QMAP_HQ;
sys/dev/usb/if_urtwn.c
2225
reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ;
sys/dev/usb/if_urtwn.c
2227
urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);
sys/dev/usb/if_urtwn.c
2251
uint32_t reg = 0;
sys/dev/usb/if_urtwn.c
2273
reg = urtwn_read_4(sc, R92C_TDECTRL);
sys/dev/usb/if_urtwn.c
2274
reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, ndesc);
sys/dev/usb/if_urtwn.c
2275
urtwn_write_4(sc, R92C_TDECTRL, reg);
sys/dev/usb/if_urtwn.c
2309
urtwn_write_1(sc, rtl8188eu_mac[i].reg,
sys/dev/usb/if_urtwn.c
2315
urtwn_write_1(sc, rtl8188ftv_mac[i].reg,
sys/dev/usb/if_urtwn.c
2320
urtwn_write_1(sc, rtl8192eu_mac[i].reg,
sys/dev/usb/if_urtwn.c
2325
urtwn_write_1(sc, rtl8192cu_mac[i].reg,
sys/dev/usb/if_urtwn.c
2335
uint32_t reg;
sys/dev/usb/if_urtwn.c
2389
reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);
sys/dev/usb/if_urtwn.c
2390
reg = (reg & ~0x00000003) | 0x2;
sys/dev/usb/if_urtwn.c
2391
urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
sys/dev/usb/if_urtwn.c
2393
reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);
sys/dev/usb/if_urtwn.c
2394
reg = (reg & ~0x00300033) | 0x00200022;
sys/dev/usb/if_urtwn.c
2395
urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
sys/dev/usb/if_urtwn.c
2397
reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);
sys/dev/usb/if_urtwn.c
2398
reg = (reg & ~0xff000000) | 0x45 << 24;
sys/dev/usb/if_urtwn.c
2399
urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
sys/dev/usb/if_urtwn.c
2401
reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
sys/dev/usb/if_urtwn.c
2402
reg = (reg & ~0x000000ff) | 0x23;
sys/dev/usb/if_urtwn.c
2403
urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
sys/dev/usb/if_urtwn.c
2405
reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
sys/dev/usb/if_urtwn.c
2406
reg = (reg & ~0x00000030) | 1 << 4;
sys/dev/usb/if_urtwn.c
2407
urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
sys/dev/usb/if_urtwn.c
2409
reg = urtwn_bb_read(sc, 0xe74);
sys/dev/usb/if_urtwn.c
2410
reg = (reg & ~0x0c000000) | 2 << 26;
sys/dev/usb/if_urtwn.c
2411
urtwn_bb_write(sc, 0xe74, reg);
sys/dev/usb/if_urtwn.c
2412
reg = urtwn_bb_read(sc, 0xe78);
sys/dev/usb/if_urtwn.c
2413
reg = (reg & ~0x0c000000) | 2 << 26;
sys/dev/usb/if_urtwn.c
2414
urtwn_bb_write(sc, 0xe78, reg);
sys/dev/usb/if_urtwn.c
2415
reg = urtwn_bb_read(sc, 0xe7c);
sys/dev/usb/if_urtwn.c
2416
reg = (reg & ~0x0c000000) | 2 << 26;
sys/dev/usb/if_urtwn.c
2417
urtwn_bb_write(sc, 0xe7c, reg);
sys/dev/usb/if_urtwn.c
2418
reg = urtwn_bb_read(sc, 0xe80);
sys/dev/usb/if_urtwn.c
2419
reg = (reg & ~0x0c000000) | 2 << 26;
sys/dev/usb/if_urtwn.c
2420
urtwn_bb_write(sc, 0xe80, reg);
sys/dev/usb/if_urtwn.c
2421
reg = urtwn_bb_read(sc, 0xe88);
sys/dev/usb/if_urtwn.c
2422
reg = (reg & ~0x0c000000) | 2 << 26;
sys/dev/usb/if_urtwn.c
2423
urtwn_bb_write(sc, 0xe88, reg);
sys/dev/usb/if_urtwn.c
2447
reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);
sys/dev/usb/if_urtwn.c
2449
RW(reg, R92C_AFE_XTAL_CTRL_ADDR, xtal | xtal << 6));
sys/dev/usb/if_urtwn.c
2452
reg = urtwn_bb_read(sc, R92C_AFE_CTRL3);
sys/dev/usb/if_urtwn.c
2454
RW(reg, R92C_AFE_CTRL3_ADDR, xtal | xtal << 6));
sys/dev/usb/if_urtwn.c
2465
uint8_t reg;
sys/dev/usb/if_urtwn.c
2467
reg = urtwn_read_1(sc, R92E_RXDMA_PRO);
sys/dev/usb/if_urtwn.c
2468
reg &= ~0x30;
sys/dev/usb/if_urtwn.c
2471
urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x1e);
sys/dev/usb/if_urtwn.c
2474
urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x2e);
sys/dev/usb/if_zyd.c
1012
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
1073
error = zyd_write16(sc, phyini_1[i].reg, phyini_1[i].val);
sys/dev/usb/if_zyd.c
1084
error = zyd_write16(sc, phyini_2[i].reg, phyini_2[i].val);
sys/dev/usb/if_zyd.c
1095
error = zyd_write16(sc, phyini_3[i].reg, phyini_3[i].val);
sys/dev/usb/if_zyd.c
1165
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
1232
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
1279
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
1324
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
1360
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
1405
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
1527
for (; phyp->reg != 0; phyp++) {
sys/dev/usb/if_zyd.c
1528
if ((error = zyd_write16(sc, phyp->reg, phyp->val)) != 0)
sys/dev/usb/if_zyd.c
750
zyd_cmd_read(struct zyd_softc *sc, const void *reg, size_t regsize, int olen)
sys/dev/usb/if_zyd.c
762
bcopy(reg, cmd.data, regsize);
sys/dev/usb/if_zyd.c
795
zyd_read16(struct zyd_softc *sc, uint16_t reg, uint16_t *val)
sys/dev/usb/if_zyd.c
800
reg = htole16(reg);
sys/dev/usb/if_zyd.c
801
error = zyd_cmd_read(sc, ®, sizeof(reg), sizeof(*odata));
sys/dev/usb/if_zyd.c
810
zyd_read32(struct zyd_softc *sc, uint16_t reg, uint32_t *val)
sys/dev/usb/if_zyd.c
816
regs[0] = htole16(ZYD_REG32_HI(reg));
sys/dev/usb/if_zyd.c
817
regs[1] = htole16(ZYD_REG32_LO(reg));
sys/dev/usb/if_zyd.c
854
zyd_write16(struct zyd_softc *sc, uint16_t reg, uint16_t val)
sys/dev/usb/if_zyd.c
858
io.reg = htole16(reg);
sys/dev/usb/if_zyd.c
864
zyd_write32(struct zyd_softc *sc, uint16_t reg, uint32_t val)
sys/dev/usb/if_zyd.c
868
io[0].reg = htole16(ZYD_REG32_HI(reg));
sys/dev/usb/if_zyd.c
870
io[1].reg = htole16(ZYD_REG32_LO(reg));
sys/dev/usb/if_zyd.c
930
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
982
error = zyd_write16(sc, phyini[i].reg, phyini[i].val);
sys/dev/usb/if_zyd.c
988
error = zyd_write16(sc, phy2230s[i].reg,
sys/dev/usb/if_zydreg.h
1065
uint16_t reg;
sys/dev/usb/if_zydreg.h
1067
#define ZYD_REG32_LO(reg) (reg)
sys/dev/usb/if_zydreg.h
1068
#define ZYD_REG32_HI(reg) \
sys/dev/usb/if_zydreg.h
1069
((reg) + ((((reg) & 0xf000) == 0x9000) ? 2 : 1))
sys/dev/usb/if_zydreg.h
1109
uint16_t reg;
sys/dev/usb/if_zydreg.h
1114
uint16_t reg;
sys/dev/usb/moscom.c
293
moscom_set(void *vsc, int portno, int reg, int onoff)
sys/dev/usb/moscom.c
298
switch (reg) {
sys/dev/usb/moscom.c
380
moscom_cmd(struct moscom_softc *sc, int reg, int val)
sys/dev/usb/moscom.c
388
USETW(req.wIndex, reg);
sys/dev/usb/ohci.c
295
u_int32_t reg;
sys/dev/usb/ohci.c
302
reg = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK;
sys/dev/usb/ohci.c
308
sc->sc_control = reg;
sys/dev/usb/ohci.c
313
reg |= OHCI_HCFS_SUSPEND;
sys/dev/usb/ohci.c
314
OWRITE4(sc, OHCI_CONTROL, reg);
sys/dev/usb/ohci.c
329
reg = sc->sc_control;
sys/dev/usb/ohci.c
331
reg = OREAD4(sc, OHCI_CONTROL);
sys/dev/usb/ohci.c
332
reg |= OHCI_HCFS_RESUME;
sys/dev/usb/ohci.c
333
OWRITE4(sc, OHCI_CONTROL, reg);
sys/dev/usb/ohci.c
335
reg = (reg & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL;
sys/dev/usb/ohci.c
336
OWRITE4(sc, OHCI_CONTROL, reg);
sys/dev/usb/ohci.c
338
reg = (OREAD4(sc, OHCI_FM_REMAINING) & OHCI_FIT) ^ OHCI_FIT;
sys/dev/usb/ohci.c
339
reg |= OHCI_FSMPS(sc->sc_ival) | sc->sc_ival;
sys/dev/usb/ohci.c
340
OWRITE4(sc, OHCI_FM_INTERVAL, reg);
sys/dev/usb/ohci.c
344
reg = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
sys/dev/usb/ohci.c
345
OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, reg | OHCI_NOCP);
sys/dev/usb/ohci.c
348
OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, reg);
sys/dev/usb/uark.c
190
uark_set(void *vsc, int portno, int reg, int onoff)
sys/dev/usb/uark.c
194
switch (reg) {
sys/dev/usb/ubsa.c
432
ubsa_set(void *addr, int portno, int reg, int onoff)
sys/dev/usb/ubsa.c
437
switch (reg) {
sys/dev/usb/uchcom.c
826
uchcom_set(void *arg, int portno, int reg, int onoff)
sys/dev/usb/uchcom.c
833
switch (reg) {
sys/dev/usb/ucomvar.h
44
void (*ucom_set)(void *sc, int portno, int reg, int onoff);
sys/dev/usb/ucycom.c
508
ucycom_set(void *addr, int portno, int reg, int onoff)
sys/dev/usb/ucycom.c
513
switch (reg) {
sys/dev/usb/udl.c
1782
udl_cmd_write_reg_1(struct udl_softc *sc, uint8_t reg, uint8_t val)
sys/dev/usb/udl.c
1786
udl_cmd_insert_int_1(sc, reg);
sys/dev/usb/udl.c
1791
udl_cmd_write_reg_3(struct udl_softc *sc, uint8_t reg, uint32_t val)
sys/dev/usb/udl.c
1793
udl_cmd_write_reg_1(sc, reg + 0, (val >> 16) & 0xff);
sys/dev/usb/udl.c
1794
udl_cmd_write_reg_1(sc, reg + 1, (val >> 8) & 0xff);
sys/dev/usb/udl.c
1795
udl_cmd_write_reg_1(sc, reg + 2, (val >> 0) & 0xff);
sys/dev/usb/uftdi.c
969
uftdi_set(void *vsc, int portno, int reg, int onoff)
sys/dev/usb/uftdi.c
976
reg, onoff));
sys/dev/usb/uftdi.c
978
switch (reg) {
sys/dev/usb/uipaq.c
316
uipaq_set(void *addr, int portno, int reg, int onoff)
sys/dev/usb/uipaq.c
320
switch (reg) {
sys/dev/usb/uipaq.c
332
sc->sc_dev.dv_xname, reg, onoff);
sys/dev/usb/ukspan.c
440
ukspan_set(void *addr, int portno, int reg, int onoff)
sys/dev/usb/ukspan.c
444
DPRINTF("set %#x = %#x\n", reg, onoff);
sys/dev/usb/ukspan.c
446
switch (reg) {
sys/dev/usb/ukspan.c
459
printf("%s: unhandled reg %#x\n", devname, reg);
sys/dev/usb/umcs.c
321
umcs_get_reg(struct umcs_softc *sc, uint8_t reg, uint8_t *data)
sys/dev/usb/umcs.c
328
USETW(req.wIndex, reg);
sys/dev/usb/umcs.c
338
umcs_set_reg(struct umcs_softc *sc, uint8_t reg, uint8_t data)
sys/dev/usb/umcs.c
345
USETW(req.wIndex, reg);
sys/dev/usb/umcs.c
355
umcs_get_uart_reg(struct umcs_softc *sc, uint8_t portno, uint8_t reg,
sys/dev/usb/umcs.c
366
USETW(req.wIndex, reg);
sys/dev/usb/umcs.c
376
umcs_set_uart_reg(struct umcs_softc *sc, uint8_t portno, uint8_t reg,
sys/dev/usb/umcs.c
387
USETW(req.wIndex, reg);
sys/dev/usb/umcs.c
504
umcs_set(void *self, int portno, int reg, int onoff)
sys/dev/usb/umcs.c
511
switch (reg) {
sys/dev/usb/umct.c
327
umct_set(void *addr, int portno, int reg, int onoff)
sys/dev/usb/umct.c
331
switch (reg) {
sys/dev/usb/umodem.c
611
umodem_set(void *addr, int portno, int reg, int onoff)
sys/dev/usb/umodem.c
615
switch (reg) {
sys/dev/usb/umsm.c
617
umsm_set(void *addr, int portno, int reg, int onoff)
sys/dev/usb/umsm.c
623
switch (reg) {
sys/dev/usb/uplcom.c
484
uplcom_set(void *addr, int portno, int reg, int onoff)
sys/dev/usb/uplcom.c
488
switch (reg) {
sys/dev/usb/uslcom.c
392
uslcom_set(void *vsc, int portno, int reg, int onoff)
sys/dev/usb/uslcom.c
398
switch (reg) {
sys/dev/usb/uslhcom.c
383
uslhcom_set(void *arg, int portno, int reg, int onoff)
sys/dev/usb/uslhcom.c
390
switch (reg) {
sys/dev/usb/uticom.c
486
uticom_set(void *addr, int portno, int reg, int onoff)
sys/dev/usb/uticom.c
490
switch (reg) {
sys/dev/usb/uvscom.c
539
uvscom_set(void *addr, int portno, int reg, int onoff)
sys/dev/usb/uvscom.c
543
switch (reg) {
sys/dev/usb/uxrcom.c
256
uxrcom_set(void *vsc, int portno, int reg, int onoff)
sys/dev/usb/uxrcom.c
265
switch (reg) {
sys/dev/usb/xhci.c
2037
uint32_t reg;
sys/dev/usb/xhci.c
2040
reg = XOREAD4(sc, XHCI_CRCR_LO);
sys/dev/usb/xhci.c
2041
if ((reg & XHCI_CRCR_LO_CRR) == 0)
sys/dev/usb/xhci.c
2044
XOWRITE4(sc, XHCI_CRCR_LO, reg | XHCI_CRCR_LO_CA);
sys/dev/usb/xhci.c
2049
reg = XOREAD4(sc, XHCI_CRCR_LO) & XHCI_CRCR_LO_CRR;
sys/dev/usb/xhci.c
2050
if (!reg)
sys/dev/usb/xhci.c
2054
if (reg) {
sys/dev/usb/xhcivar.h
139
uint32_t reg;
sys/dev/usb/xhcivar.h
140
reg = bus_space_read_4(iot, ioh, offset & ~3);
sys/dev/usb/xhcivar.h
141
return (reg >> ((offset & 3) * 8)) & 0xff;
sys/dev/usb/xhcivar.h
147
uint32_t reg;
sys/dev/usb/xhcivar.h
148
reg = bus_space_read_4(iot, ioh, offset & ~2);
sys/dev/usb/xhcivar.h
149
return (reg >> ((offset & 2) * 8)) & 0xffff;
sys/dev/x86emu/x86emu.c
1099
common_inc_word_long(struct x86emu *emu, union x86emu_register *reg)
sys/dev/x86emu/x86emu.c
1102
reg->I32_reg.e_reg = inc_long(emu, reg->I32_reg.e_reg);
sys/dev/x86emu/x86emu.c
1104
reg->I16_reg.x_reg = inc_word(emu, reg->I16_reg.x_reg);
sys/dev/x86emu/x86emu.c
1108
common_dec_word_long(struct x86emu *emu, union x86emu_register *reg)
sys/dev/x86emu/x86emu.c
1111
reg->I32_reg.e_reg = dec_long(emu, reg->I32_reg.e_reg);
sys/dev/x86emu/x86emu.c
1113
reg->I16_reg.x_reg = dec_word(emu, reg->I16_reg.x_reg);
sys/dev/x86emu/x86emu.c
1348
common_push_word_long(struct x86emu *emu, union x86emu_register *reg)
sys/dev/x86emu/x86emu.c
1351
push_long(emu, reg->I32_reg.e_reg);
sys/dev/x86emu/x86emu.c
1353
push_word(emu, reg->I16_reg.x_reg);
sys/dev/x86emu/x86emu.c
1357
common_pop_word_long(struct x86emu *emu, union x86emu_register *reg)
sys/dev/x86emu/x86emu.c
1360
reg->I32_reg.e_reg = pop_long(emu);
sys/dev/x86emu/x86emu.c
1362
reg->I16_reg.x_reg = pop_word(emu);
sys/dev/x86emu/x86emu.c
641
decode_rm_byte_register(struct x86emu *emu, int reg)
sys/dev/x86emu/x86emu.c
643
switch (reg) {
sys/dev/x86emu/x86emu.c
689
decode_rm_word_register(struct x86emu *emu, int reg)
sys/dev/x86emu/x86emu.c
691
switch (reg) {
sys/dev/x86emu/x86emu.c
737
decode_rm_long_register(struct x86emu *emu, int reg)
sys/dev/x86emu/x86emu.c
739
switch (reg) {
sys/kern/exec_elf.c
1544
struct reg intreg;
sys/kern/sys_process.c
172
size = sizeof(struct reg);
sys/kern/sys_process.c
176
size = sizeof(struct reg);
sys/stand/efi/include/efiprot.h
396
#define EFI_PCI_ADDRESS(bus,dev,func,reg) \
sys/stand/efi/include/efiprot.h
397
( (UINT64) ( (((UINTN)bus) << 24) + (((UINTN)dev) << 16) + (((UINTN)func) << 8) + ((UINTN)reg) ))
sys/sys/ptrace.h
105
struct reg;
sys/sys/ptrace.h
115
int process_read_regs(struct proc *_t, struct reg *);
sys/sys/ptrace.h
121
int process_write_regs(struct proc *_t, struct reg *);
sys/sys/videoio.h
6231
u_int64_t reg;
usr.bin/awk/lex.c
179
bool reg = false; /* true => return a REGEXPR now */
usr.bin/awk/lex.c
193
if (reg) {
usr.bin/awk/lex.c
194
reg = false;
usr.bin/awk/lex.c
557
reg = true;
usr.bin/dc/bcode.c
1473
v = stack_tos(&bmachine.reg[idx]);
usr.bin/dc/bcode.c
237
bmachine.reg = calloc(bmachine.reg_array_size,
usr.bin/dc/bcode.c
238
sizeof(bmachine.reg[0]));
usr.bin/dc/bcode.c
239
if (bmachine.reg == NULL)
usr.bin/dc/bcode.c
258
stack_init(&bmachine.reg[i]);
usr.bin/dc/bcode.c
45
struct stack *reg;
usr.bin/dc/bcode.c
830
v = stack_tos(&bmachine.reg[idx]);
usr.bin/dc/bcode.c
852
stack_set_tos(&bmachine.reg[idx], val);
usr.bin/dc/bcode.c
865
stack = &bmachine.reg[idx];
usr.bin/dc/bcode.c
889
stack_push(&bmachine.reg[idx], value);
usr.bin/dc/bcode.c
896
int reg;
usr.bin/dc/bcode.c
902
reg = readreg();
usr.bin/dc/bcode.c
903
if (reg >= 0) {
usr.bin/dc/bcode.c
913
stack = &bmachine.reg[reg];
usr.bin/dc/bcode.c
929
int reg;
usr.bin/dc/bcode.c
935
reg = readreg();
usr.bin/dc/bcode.c
936
if (reg >= 0) {
usr.bin/dc/bcode.c
953
stack = &bmachine.reg[reg];
usr.bin/mandoc/roff.c
3014
struct roffreg *reg;
usr.bin/mandoc/roff.c
3017
reg = r->regtab;
usr.bin/mandoc/roff.c
3019
while (reg != NULL && (reg->key.sz != len ||
usr.bin/mandoc/roff.c
3020
strncmp(reg->key.p, name, len) != 0))
usr.bin/mandoc/roff.c
3021
reg = reg->next;
usr.bin/mandoc/roff.c
3023
if (NULL == reg) {
usr.bin/mandoc/roff.c
3025
reg = mandoc_malloc(sizeof(struct roffreg));
usr.bin/mandoc/roff.c
3026
reg->key.p = mandoc_strndup(name, len);
usr.bin/mandoc/roff.c
3027
reg->key.sz = len;
usr.bin/mandoc/roff.c
3028
reg->val = 0;
usr.bin/mandoc/roff.c
3029
reg->step = 0;
usr.bin/mandoc/roff.c
3030
reg->next = r->regtab;
usr.bin/mandoc/roff.c
3031
r->regtab = reg;
usr.bin/mandoc/roff.c
3035
reg->val += val;
usr.bin/mandoc/roff.c
3037
reg->val -= val;
usr.bin/mandoc/roff.c
3039
reg->val = val;
usr.bin/mandoc/roff.c
3041
reg->step = step;
usr.bin/mandoc/roff.c
3085
struct roffreg *reg;
usr.bin/mandoc/roff.c
3094
for (reg = r->regtab; reg; reg = reg->next) {
usr.bin/mandoc/roff.c
3095
if (len == reg->key.sz &&
usr.bin/mandoc/roff.c
3096
0 == strncmp(name, reg->key.p, len)) {
usr.bin/mandoc/roff.c
3099
reg->val += reg->step;
usr.bin/mandoc/roff.c
3102
reg->val -= reg->step;
usr.bin/mandoc/roff.c
3107
return reg->val;
usr.bin/mandoc/roff.c
3118
struct roffreg *reg;
usr.bin/mandoc/roff.c
3127
for (reg = r->regtab; reg; reg = reg->next)
usr.bin/mandoc/roff.c
3128
if (len == reg->key.sz &&
usr.bin/mandoc/roff.c
3129
0 == strncmp(name, reg->key.p, len))
usr.bin/mandoc/roff.c
3136
roff_freereg(struct roffreg *reg)
usr.bin/mandoc/roff.c
3140
while (NULL != reg) {
usr.bin/mandoc/roff.c
3141
free(reg->key.p);
usr.bin/mandoc/roff.c
3142
old_reg = reg;
usr.bin/mandoc/roff.c
3143
reg = reg->next;
usr.bin/mandoc/roff.c
3185
struct roffreg *reg, **prev;
usr.bin/mandoc/roff.c
3197
reg = *prev;
usr.bin/mandoc/roff.c
3198
if (reg == NULL || !strcmp(name, reg->key.p))
usr.bin/mandoc/roff.c
3200
prev = ®->next;
usr.bin/mandoc/roff.c
3202
if (reg != NULL) {
usr.bin/mandoc/roff.c
3203
*prev = reg->next;
usr.bin/mandoc/roff.c
3204
free(reg->key.p);
usr.bin/mandoc/roff.c
3205
free(reg);
usr.bin/mg/region.c
356
region_get_data(struct region *reg, char *buf, int len)
usr.bin/mg/region.c
361
off = reg->r_offset;
usr.bin/mg/region.c
362
lp = reg->r_linep;
usr.bin/mg/undo.c
266
struct region reg;
usr.bin/mg/undo.c
273
memset(®, 0, sizeof(reg));
usr.bin/mg/undo.c
274
reg.r_linep = lp;
usr.bin/mg/undo.c
275
reg.r_offset = offset;
usr.bin/mg/undo.c
276
reg.r_size = size;
usr.bin/mg/undo.c
286
rec->region.r_size += reg.r_size;
usr.bin/mg/undo.c
297
memmove(&rec->region, ®, sizeof(struct region));
usr.bin/mg/undo.c
313
struct region reg;
usr.bin/mg/undo.c
320
memset(®, 0, sizeof(reg));
usr.bin/mg/undo.c
321
reg.r_linep = lp;
usr.bin/mg/undo.c
322
reg.r_offset = offset;
usr.bin/mg/undo.c
323
reg.r_size = size;
usr.bin/mg/undo.c
345
memmove(&rec->region, ®, sizeof(struct region));
usr.bin/mg/undo.c
347
rec->content = malloc(reg.r_size + 1);
usr.bin/mg/undo.c
353
region_get_data(®, rec->content, reg.r_size);
usr.bin/pkill/pkill.c
149
regex_t reg;
usr.bin/pkill/pkill.c
294
if ((rv = regcomp(®, *argv, REG_EXTENDED)) != 0) {
usr.bin/pkill/pkill.c
295
regerror(rv, ®, buf, sizeof(buf));
usr.bin/pkill/pkill.c
308
rv = regexec(®, mstr, 1, ®match, 0);
usr.bin/pkill/pkill.c
317
regerror(rv, ®, buf, sizeof(buf));
usr.bin/pkill/pkill.c
322
regfree(®);
usr.bin/rdist/gram.y
177
regex_t reg;
usr.bin/rdist/gram.y
182
ecode = regcomp(®, nl->n_name, REG_NOSUB);
usr.bin/rdist/gram.y
184
regerror(ecode, ®, ebuf,
usr.bin/rdist/gram.y
188
regfree(®);
usr.bin/tmux/window-copy.c
3562
u_int first, u_int last, regex_t *reg)
usr.bin/tmux/window-copy.c
3599
if (regexec(reg, buf, 1, ®match, eflags) == 0 &&
usr.bin/tmux/window-copy.c
3629
u_int first, u_int last, regex_t *reg)
usr.bin/tmux/window-copy.c
3659
reg, eflags))
usr.bin/tmux/window-copy.c
4006
regex_t reg;
usr.bin/tmux/window-copy.c
4014
if (regcomp(®, sbuf, cflags) != 0) {
usr.bin/tmux/window-copy.c
4025
&px, &sx, i, fx, gd->sx, ®);
usr.bin/tmux/window-copy.c
4038
&px, &sx, i - 1, 0, fx + 1, ®);
usr.bin/tmux/window-copy.c
4041
®, &px, &sx, &i, endline);
usr.bin/tmux/window-copy.c
4055
regfree(®);
usr.bin/tmux/window-copy.c
4321
regex_t reg;
usr.bin/tmux/window-copy.c
4344
if (regcomp(®, sbuf, cflags) != 0) {
usr.bin/tmux/window-copy.c
4370
&px, &width, py, px, sx, ®);
usr.bin/tmux/window-copy.c
4430
regfree(®);
usr.sbin/pcidump/pcidump.c
1002
if (pci_read(bus, dev, func, PCI_ID_REG, ®) != 0)
usr.sbin/pcidump/pcidump.c
1005
PCI_VENDOR(reg), PCI_PRODUCT(reg));
usr.sbin/pcidump/pcidump.c
1007
if (pci_read(bus, dev, func, PCI_COMMAND_STATUS_REG, ®) != 0)
usr.sbin/pcidump/pcidump.c
1010
PCI_COMMAND_STATUS_REG, reg & 0xffff, (reg >> 16) & 0xffff);
usr.sbin/pcidump/pcidump.c
1012
if (pci_read(bus, dev, func, PCI_CLASS_REG, ®) != 0)
usr.sbin/pcidump/pcidump.c
1014
class = PCI_CLASS(reg);
usr.sbin/pcidump/pcidump.c
1015
subclass = PCI_SUBCLASS(reg);
usr.sbin/pcidump/pcidump.c
1021
PCI_INTERFACE(reg), PCI_REVISION(reg));
usr.sbin/pcidump/pcidump.c
1023
if (pci_read(bus, dev, func, PCI_BHLC_REG, ®) != 0)
usr.sbin/pcidump/pcidump.c
1027
PCI_BIST(reg), PCI_HDRTYPE(reg),
usr.sbin/pcidump/pcidump.c
1028
PCI_LATTIMER(reg), PCI_CACHELINE(reg));
usr.sbin/pcidump/pcidump.c
1030
switch (PCI_HDRTYPE_TYPE(reg)) {
usr.sbin/pcidump/pcidump.c
1050
u_int32_t reg;
usr.sbin/pcidump/pcidump.c
1054
if (pci_read(bus, dev, func, i, ®) != 0) {
usr.sbin/pcidump/pcidump.c
1062
printf(" %08x", reg);
usr.sbin/pcidump/pcidump.c
1081
pci_read(int bus, int dev, int func, u_int32_t reg, u_int32_t *val)
usr.sbin/pcidump/pcidump.c
1090
io.pi_reg = reg;
usr.sbin/pcidump/pcidump.c
1103
pci_readmask(int bus, int dev, int func, u_int32_t reg, u_int32_t *val)
usr.sbin/pcidump/pcidump.c
1112
io.pi_reg = reg;
usr.sbin/pcidump/pcidump.c
636
u_int32_t reg;
usr.sbin/pcidump/pcidump.c
638
if (pci_read(bus, dev, func, ptr, ®) != 0)
usr.sbin/pcidump/pcidump.c
642
reg & PCI_MSI_MC_MSIE ? "yes" : "no",
usr.sbin/pcidump/pcidump.c
643
(1 << ((reg & PCI_MSI_MC_MMC_MASK) >> PCI_MSI_MC_MMC_SHIFT)),
usr.sbin/pcidump/pcidump.c
644
(1 << ((reg & PCI_MSI_MC_MME_MASK) >> PCI_MSI_MC_MME_SHIFT)));
usr.sbin/pcidump/pcidump.c
650
u_int32_t reg;
usr.sbin/pcidump/pcidump.c
653
if ((pci_read(bus, dev, func, ptr, ®) != 0) ||
usr.sbin/pcidump/pcidump.c
658
reg & PCI_MSIX_MC_MSIXE ? "yes" : "no",
usr.sbin/pcidump/pcidump.c
659
PCI_MSIX_MC_TBLSZ(reg) + 1,
usr.sbin/pcidump/pcidump.c
667
u_int32_t reg;
usr.sbin/pcidump/pcidump.c
675
if (pci_read(bus, dev, func, ptr, ®) != 0)
usr.sbin/pcidump/pcidump.c
678
if (PCI_PCIE_ECAP_ID(reg) == 0xffff &&
usr.sbin/pcidump/pcidump.c
679
PCI_PCIE_ECAP_NEXT(reg) == PCI_PCIE_ECAP_LAST)
usr.sbin/pcidump/pcidump.c
682
ecap = PCI_PCIE_ECAP_ID(reg);
usr.sbin/pcidump/pcidump.c
697
ptr = PCI_PCIE_ECAP_NEXT(reg);
usr.sbin/pcidump/pcidump.c
705
u_int32_t reg;
usr.sbin/pcidump/pcidump.c
708
if (pci_read(bus, dev, func, PCI_COMMAND_STATUS_REG, ®) != 0)
usr.sbin/pcidump/pcidump.c
710
if (!(reg & PCI_STATUS_CAPLIST_SUPPORT))
usr.sbin/pcidump/pcidump.c
713
if (pci_read(bus, dev, func, ptr, ®) != 0)
usr.sbin/pcidump/pcidump.c
715
ptr = PCI_CAPLIST_PTR(reg);
usr.sbin/pcidump/pcidump.c
717
if (pci_read(bus, dev, func, ptr, ®) != 0)
usr.sbin/pcidump/pcidump.c
719
cap = PCI_CAPLIST_CAP(reg);
usr.sbin/pcidump/pcidump.c
742
ptr = PCI_CAPLIST_NEXT(reg);
usr.sbin/pcidump/pcidump.c
752
u_int32_t reg, reg1;
usr.sbin/pcidump/pcidump.c
756
if (pci_read(bus, dev, func, bar, ®) != 0 ||
usr.sbin/pcidump/pcidump.c
762
if (reg == 0 && reg1 == 0) {
usr.sbin/pcidump/pcidump.c
763
printf("empty (%08x)\n", reg);
usr.sbin/pcidump/pcidump.c
767
switch (PCI_MAPREG_TYPE(reg)) {
usr.sbin/pcidump/pcidump.c
770
if (PCI_MAPREG_MEM_PREFETCHABLE(reg))
usr.sbin/pcidump/pcidump.c
774
switch (PCI_MAPREG_MEM_TYPE(reg)) {
usr.sbin/pcidump/pcidump.c
781
PCI_MAPREG_MEM_ADDR(reg),
usr.sbin/pcidump/pcidump.c
786
mem = reg;
usr.sbin/pcidump/pcidump.c
789
if (pci_read(bus, dev, func, bar, ®) != 0 ||
usr.sbin/pcidump/pcidump.c
793
mem |= (u_int64_t)reg << 32;
usr.sbin/pcidump/pcidump.c
806
PCI_MAPREG_IO_ADDR(reg),
usr.sbin/pcidump/pcidump.c
816
u_int32_t reg;
usr.sbin/pcidump/pcidump.c
820
if (pci_read(bus, dev, func, PCI_CARDBUS_CIS_REG, ®) != 0)
usr.sbin/pcidump/pcidump.c
822
printf("\t0x%04x: Cardbus CIS: %08x\n", PCI_CARDBUS_CIS_REG, reg);
usr.sbin/pcidump/pcidump.c
824
if (pci_read(bus, dev, func, PCI_SUBSYS_ID_REG, ®) != 0)
usr.sbin/pcidump/pcidump.c
827
PCI_SUBSYS_ID_REG, PCI_VENDOR(reg), PCI_PRODUCT(reg));
usr.sbin/pcidump/pcidump.c
829
if (pci_read(bus, dev, func, PCI_ROM_REG, ®) != 0)
usr.sbin/pcidump/pcidump.c
832
PCI_ROM_REG, reg);
usr.sbin/pcidump/pcidump.c
834
if (pci_read(bus, dev, func, 0x38, ®) != 0)
usr.sbin/pcidump/pcidump.c
836
printf("\t0x%04x: %08x\n", 0x38, reg);
usr.sbin/pcidump/pcidump.c
838
if (pci_read(bus, dev, func, PCI_INTERRUPT_REG, ®) != 0)
usr.sbin/pcidump/pcidump.c
841
" Max Lat: %02x\n", PCI_INTERRUPT_REG, PCI_INTERRUPT_PIN(reg),
usr.sbin/pcidump/pcidump.c
842
PCI_INTERRUPT_LINE(reg), PCI_MIN_GNT(reg), PCI_MAX_LAT(reg));
usr.sbin/pcidump/pcidump.c
855
u_int32_t reg, iobaseh, pmbaseh, pmlimith;
usr.sbin/pcidump/pcidump.c
860
if (pci_read(bus, dev, func, PCI_PRIBUS_1, ®) != 0)
usr.sbin/pcidump/pcidump.c
864
PCI_PRIBUS_1, (reg >> 0) & 0xff, (reg >> 8) & 0xff,
usr.sbin/pcidump/pcidump.c
865
(reg >> 16) & 0xff, (reg >> 24) & 0xff);
usr.sbin/pcidump/pcidump.c
867
if (pci_read(bus, dev, func, PCI_IOBASEL_1, ®) != 0)
usr.sbin/pcidump/pcidump.c
872
"Secondary Status: %04x\n", PCI_IOBASEL_1, (reg >> 0 ) & 0xff,
usr.sbin/pcidump/pcidump.c
873
(reg >> 8) & 0xff, (reg >> 16) & 0xffff);
usr.sbin/pcidump/pcidump.c
874
base = (reg & 0x00f0) << 8 | (iobaseh & 0xffff) << 16;
usr.sbin/pcidump/pcidump.c
875
limit = (reg & 0xf000) | (iobaseh & 0xffff0000) | 0xfff;
usr.sbin/pcidump/pcidump.c
879
if (pci_read(bus, dev, func, PCI_MEMBASE_1, ®) != 0)
usr.sbin/pcidump/pcidump.c
882
PCI_MEMBASE_1, (reg >> 0) & 0xffff, (reg >> 16) & 0xffff);
usr.sbin/pcidump/pcidump.c
883
base = (reg & 0xfff0) << 16;
usr.sbin/pcidump/pcidump.c
884
limit = (reg & 0xfff00000) | 0xfffff;
usr.sbin/pcidump/pcidump.c
888
if (pci_read(bus, dev, func, PCI_PMBASEL_1, ®) != 0)
usr.sbin/pcidump/pcidump.c
896
(reg >> 0) & 0xffff, (reg >> 16) & 0xffff);
usr.sbin/pcidump/pcidump.c
897
base = (reg & 0xfff0) << 16 | (u_int64_t)pmbaseh << 32;
usr.sbin/pcidump/pcidump.c
898
limit = (reg & 0xfff00000) | (u_int64_t)pmlimith << 32 | 0xfffff;
usr.sbin/pcidump/pcidump.c
914
if (pci_read(bus, dev, func, PCI_EXROMADDR_1, ®) != 0)
usr.sbin/pcidump/pcidump.c
917
PCI_PPB_ROM_REG, reg);
usr.sbin/pcidump/pcidump.c
919
if (pci_read(bus, dev, func, PCI_INTERRUPT_REG, ®) != 0)
usr.sbin/pcidump/pcidump.c
923
PCI_INTERRUPT_REG, PCI_INTERRUPT_PIN(reg),
usr.sbin/pcidump/pcidump.c
924
PCI_INTERRUPT_LINE(reg), reg >> 16);
usr.sbin/pcidump/pcidump.c
930
u_int32_t reg;
usr.sbin/pcidump/pcidump.c
932
if (pci_read(bus, dev, func, PCI_MAPREG_START, ®) != 0)
usr.sbin/pcidump/pcidump.c
935
PCI_MAPREG_START, reg);
usr.sbin/pcidump/pcidump.c
937
if (pci_read(bus, dev, func, PCI_PRIBUS_2, ®) != 0)
usr.sbin/pcidump/pcidump.c
941
PCI_PRIBUS_2, (reg >> 0) & 0xff, (reg >> 8) & 0xff,
usr.sbin/pcidump/pcidump.c
942
(reg >> 16) & 0xff, (reg >> 24) & 0xff);
usr.sbin/pcidump/pcidump.c
944
if (pci_read(bus, dev, func, PCI_MEMBASE0_2, ®) != 0)
usr.sbin/pcidump/pcidump.c
946
printf("\t0x%04x: Memory Base 0: %08x\n", PCI_MEMBASE0_2, reg);
usr.sbin/pcidump/pcidump.c
948
if (pci_read(bus, dev, func, PCI_MEMLIMIT0_2, ®) != 0)
usr.sbin/pcidump/pcidump.c
950
printf("\t0x%04x: Memory Limit 0: %08x\n", PCI_MEMLIMIT0_2, reg);
usr.sbin/pcidump/pcidump.c
952
if (pci_read(bus, dev, func, PCI_MEMBASE1_2, ®) != 0)
usr.sbin/pcidump/pcidump.c
954
printf("\t0x%04x: Memory Base 1: %08x\n", PCI_MEMBASE1_2, reg);
usr.sbin/pcidump/pcidump.c
956
if (pci_read(bus, dev, func, PCI_MEMLIMIT1_2, ®) != 0)
usr.sbin/pcidump/pcidump.c
958
printf("\t0x%04x: Memory Limit 1: %08x\n", PCI_MEMLIMIT1_2, reg);
usr.sbin/pcidump/pcidump.c
960
if (pci_read(bus, dev, func, PCI_IOBASE0_2, ®) != 0)
usr.sbin/pcidump/pcidump.c
962
printf("\t0x%04x: I/O Base 0: %08x\n", PCI_IOBASE0_2, reg);
usr.sbin/pcidump/pcidump.c
964
if (pci_read(bus, dev, func, PCI_IOLIMIT0_2, ®) != 0)
usr.sbin/pcidump/pcidump.c
966
printf("\t0x%04x: I/O Limit 0: %08x\n", PCI_IOLIMIT0_2, reg);
usr.sbin/pcidump/pcidump.c
968
if (pci_read(bus, dev, func, PCI_IOBASE1_2, ®) != 0)
usr.sbin/pcidump/pcidump.c
970
printf("\t0x%04x: I/O Base 1: %08x\n", PCI_IOBASE1_2, reg);
usr.sbin/pcidump/pcidump.c
972
if (pci_read(bus, dev, func, PCI_IOLIMIT1_2, ®) != 0)
usr.sbin/pcidump/pcidump.c
974
printf("\t0x%04x: I/O Limit 1: %08x\n", PCI_IOLIMIT1_2, reg);
usr.sbin/pcidump/pcidump.c
976
if (pci_read(bus, dev, func, PCI_INTERRUPT_REG, ®) != 0)
usr.sbin/pcidump/pcidump.c
980
PCI_INTERRUPT_REG, PCI_INTERRUPT_PIN(reg),
usr.sbin/pcidump/pcidump.c
981
PCI_INTERRUPT_LINE(reg), reg >> 16);
usr.sbin/pcidump/pcidump.c
983
if (pci_read(bus, dev, func, PCI_SUBVEND_2, ®) != 0)
usr.sbin/pcidump/pcidump.c
986
PCI_SUBVEND_2, PCI_VENDOR(reg), PCI_PRODUCT(reg));
usr.sbin/pcidump/pcidump.c
988
if (pci_read(bus, dev, func, PCI_PCCARDIF_2, ®) != 0)
usr.sbin/pcidump/pcidump.c
991
PCI_PCCARDIF_2, reg);
usr.sbin/pcidump/pcidump.c
997
u_int32_t reg;
usr.sbin/portmap/portmap.c
287
struct pmap reg;
usr.sbin/portmap/portmap.c
317
if (!svc_getargs(xprt, xdr_pmap, (caddr_t)®)) {
usr.sbin/portmap/portmap.c
327
fnd = find_service(reg.pm_prog, reg.pm_vers, reg.pm_prot);
usr.sbin/portmap/portmap.c
328
if (fnd && fnd->pml_map.pm_vers == reg.pm_vers) {
usr.sbin/portmap/portmap.c
329
if (fnd->pml_map.pm_port == reg.pm_port)
usr.sbin/portmap/portmap.c
336
reg.pm_prog, reg.pm_vers, reg.pm_port);
usr.sbin/portmap/portmap.c
338
if (reg.pm_port & ~0xffff)
usr.sbin/portmap/portmap.c
345
if ((reg.pm_port < IPPORT_RESERVED ||
usr.sbin/portmap/portmap.c
346
reg.pm_port == NFS_PORT) &&
usr.sbin/portmap/portmap.c
363
pml->pml_map = reg;
usr.sbin/portmap/portmap.c
392
if (!svc_getargs(xprt, xdr_pmap, (caddr_t)®)) {
usr.sbin/portmap/portmap.c
397
if ((pml->pml_map.pm_prog != reg.pm_prog) ||
usr.sbin/portmap/portmap.c
398
(pml->pml_map.pm_vers != reg.pm_vers)) {
usr.sbin/portmap/portmap.c
432
if (!svc_getargs(xprt, xdr_pmap, (caddr_t)®)) {
usr.sbin/portmap/portmap.c
436
fnd = find_service(reg.pm_prog, reg.pm_vers, reg.pm_prot);
usr.sbin/vmd/pci.c
293
uint16_t reg, b_hi, b_lo;
usr.sbin/vmd/pci.c
299
reg = vei->vei.vei_port;
usr.sbin/vmd/pci.c
307
if (reg >= b_lo && reg < b_hi) {
usr.sbin/vmd/pci.c
309
reg = reg - b_lo;
usr.sbin/vmd/pci.c
319
"%%rip=0x%llx)", (uint64_t)reg, dir,
usr.sbin/vmd/pci.c
327
if (fn(dir, reg, &vei->vei.vei_data, &intr, cookie, sz))
usr.sbin/vmd/pci.h
43
typedef int (*pci_cs_fn_t)(int dir, uint8_t reg, uint32_t *data);
usr.sbin/vmd/pci.h
44
typedef int (*pci_iobar_fn_t)(int dir, uint16_t reg, uint32_t *data, uint8_t *,
usr.sbin/vmd/vioblk.c
532
uint16_t reg = msg->reg;
usr.sbin/vmd/vioblk.c
536
switch (reg & 0xFF00) {
usr.sbin/vmd/vioblk.c
538
(void)virtio_io_cfg(dev, VEI_DIR_OUT, (reg & 0x00FF), data, sz);
usr.sbin/vmd/vioblk.c
550
log_debug("%s: no handler for reg 0x%04x", __func__, reg);
usr.sbin/vmd/vioblk.c
560
uint16_t reg = msg->reg;
usr.sbin/vmd/vioblk.c
563
switch (reg & 0xFF00) {
usr.sbin/vmd/vioblk.c
565
data = virtio_io_cfg(dev, VEI_DIR_IN, (uint8_t)reg, 0, sz);
usr.sbin/vmd/vioblk.c
579
log_debug("%s: no handler for reg 0x%04x", __func__, reg);
usr.sbin/vmd/vioblk.c
590
uint16_t reg = msg->reg;
usr.sbin/vmd/vioblk.c
593
switch (reg & 0xFF) {
usr.sbin/vmd/vioblk.c
627
log_warnx("%s: invalid register 0x%04x", __func__, reg);
usr.sbin/vmd/vionet.c
1058
log_warnx("%s: invalid register 0x%04x", __func__, reg);
usr.sbin/vmd/vionet.c
1070
uint16_t reg = msg->reg & 0xFF;
usr.sbin/vmd/vionet.c
1074
DPRINTF("%s: write reg=%d data=0x%x", __func__, msg->reg, data);
usr.sbin/vmd/vionet.c
1077
switch (reg) {
usr.sbin/vmd/vionet.c
1254
log_warnx("%s: invalid register 0x%04x", __func__, reg);
usr.sbin/vmd/vionet.c
1270
uint16_t reg = msg->reg;
usr.sbin/vmd/vionet.c
1272
switch (reg & 0xFF00) {
usr.sbin/vmd/vionet.c
1291
log_debug("%s: no handler for reg 0x%04x", __func__, reg);
usr.sbin/vmd/vionet.c
1300
uint16_t reg = msg->reg;
usr.sbin/vmd/vionet.c
1302
switch (reg & 0xFF00) {
usr.sbin/vmd/vionet.c
1316
log_debug("%s: no handler for reg 0x%04x", __func__, reg);
usr.sbin/vmd/vionet.c
1325
uint16_t reg = msg->reg & 0xFF;
usr.sbin/vmd/vionet.c
1327
switch (reg) {
usr.sbin/vmd/vionet.c
1334
data = (uint8_t)vionet->mac[reg - VIRTIO_NET_CONFIG_MAC];
usr.sbin/vmd/vionet.c
1337
log_warnx("%s: invalid register 0x%04x", __func__, reg);
usr.sbin/vmd/vionet.c
982
uint16_t reg = msg->reg & 0x00FF;
usr.sbin/vmd/vionet.c
985
switch (reg) {
usr.sbin/vmd/vioscsi.c
2066
vioscsi_io_cfg(struct virtio_dev *dev, int dir, uint8_t reg, uint32_t data,
usr.sbin/vmd/vioscsi.c
2077
dir ? "READ" : "WRITE", vioscsi_reg_name(reg), sz);
usr.sbin/vmd/vioscsi.c
2080
switch (reg) {
usr.sbin/vmd/vioscsi.c
2094
log_warnx("%s: invalid register 0x%04x", __func__, reg);
usr.sbin/vmd/vioscsi.c
2098
switch (reg) {
usr.sbin/vmd/vioscsi.c
2164
log_warnx("%s: invalid register 0x%04x", __func__, reg);
usr.sbin/vmd/vioscsi.c
320
vioscsi_reg_name(uint8_t reg)
usr.sbin/vmd/vioscsi.c
322
switch (reg) {
usr.sbin/vmd/vioscsi.c
566
uint16_t reg = msg->reg;
usr.sbin/vmd/vioscsi.c
570
switch (reg & 0xFF00) {
usr.sbin/vmd/vioscsi.c
572
(void)virtio_io_cfg(dev, VEI_DIR_OUT, (reg & 0xFF), data, sz);
usr.sbin/vmd/vioscsi.c
575
(void)vioscsi_io_cfg(dev, VEI_DIR_OUT, (reg & 0xFF), data, sz);
usr.sbin/vmd/vioscsi.c
584
log_debug("%s: no handler for reg 0x%04x", __func__, reg);
usr.sbin/vmd/vioscsi.c
594
uint16_t reg = msg->reg;
usr.sbin/vmd/vioscsi.c
597
switch (reg & 0xFF00) {
usr.sbin/vmd/vioscsi.c
599
data = virtio_io_cfg(dev, VEI_DIR_IN, (reg & 0xFF), 0, sz);
usr.sbin/vmd/vioscsi.c
602
data = vioscsi_io_cfg(dev, VEI_DIR_IN, (reg & 0xFF), 0, sz);
usr.sbin/vmd/vioscsi.c
613
log_debug("%s: no handler for reg 0x%04x", __func__, reg);
usr.sbin/vmd/virtio.c
124
virtio_reg_name(uint8_t reg)
usr.sbin/vmd/virtio.c
126
switch (reg) {
usr.sbin/vmd/virtio.c
1779
virtio_pci_io(int dir, uint16_t reg, uint32_t *data, uint8_t *intr,
usr.sbin/vmd/virtio.c
1789
msg.reg = reg;
usr.sbin/vmd/virtio.c
1841
virtio_reg_name(msg.reg));
usr.sbin/vmd/virtio.c
324
virtio_io_dispatch(int dir, uint16_t reg, uint32_t *data, uint8_t *intr,
usr.sbin/vmd/virtio.c
328
uint8_t actual = (uint8_t)reg;
usr.sbin/vmd/virtio.c
330
switch (reg & 0xFF00) {
usr.sbin/vmd/virtio.c
345
DPRINTF("%s: no handler for reg 0x%04x", __func__, reg);
usr.sbin/vmd/virtio.c
357
virtio_io_cfg(struct virtio_dev *dev, int dir, uint8_t reg, uint32_t data,
usr.sbin/vmd/virtio.c
365
switch (reg) {
usr.sbin/vmd/virtio.c
544
log_warnx("%s: invalid register 0x%04x", __func__, reg);
usr.sbin/vmd/virtio.c
547
switch (reg) {
usr.sbin/vmd/virtio.c
620
log_warnx("%s: invalid register 0x%04x", __func__, reg);
usr.sbin/vmd/virtio.c
625
virtio1_reg_name(reg), sz, (dir == VEI_DIR_OUT) ? "w" : "r",
usr.sbin/vmd/virtio.c
632
virtio_io_isr(int dir, uint16_t reg, uint32_t *data, uint8_t *intr,
usr.sbin/vmd/virtio.c
639
dev->pci_id, reg, sz,
usr.sbin/vmd/virtio.c
658
virtio_io_notify(int dir, uint16_t reg, uint32_t *data, uint8_t *intr,
usr.sbin/vmd/virtio.c
667
DPRINTF("%s: reg=0x%04x, sz=%u, vq_idx=%u, dir=%s", __func__, reg, sz,
usr.sbin/vmd/virtio.c
851
vmmci_io(int dir, uint16_t reg, uint32_t *data, uint8_t *intr,
usr.sbin/vmd/virtio.c
866
switch (reg) {
usr.sbin/vmd/virtio.c
871
virtio_reg_name(reg));
usr.sbin/vmd/virtio.c
893
switch (reg) {
usr.sbin/vmd/virtio.c
96
virtio1_reg_name(uint16_t reg)
usr.sbin/vmd/virtio.c
98
switch (reg) {
usr.sbin/vmd/virtio.h
138
uint16_t reg; /* VirtIO register */
usr.sbin/vmd/x86_mmio.c
326
str_reg(int reg) {
usr.sbin/vmd/x86_mmio.c
327
switch (reg) {
