common/lib/libc/misc/ubsan.c
1192
HandleTypeMismatch(false, &pData->mLocation, pData->mType, __BIT(pData->mLogAlignment), pData->mTypeCheckKind, ulPointer);
common/lib/libc/misc/ubsan.c
1201
HandleTypeMismatch(true, &pData->mLocation, pData->mType, __BIT(pData->mLogAlignment), pData->mTypeCheckKind, ulPointer);
common/lib/libc/misc/ubsan.c
129
#define UBSAN_ABORT __BIT(0)
common/lib/libc/misc/ubsan.c
130
#define UBSAN_STDOUT __BIT(1)
common/lib/libc/misc/ubsan.c
131
#define UBSAN_STDERR __BIT(2)
common/lib/libc/misc/ubsan.c
132
#define UBSAN_SYSLOG __BIT(3)
common/lib/libc/misc/ubsan.c
1381
zWidth = __BIT(__SHIFTOUT(pType->mTypeInfo, ~NUMBER_SIGNED_BIT));
common/lib/libc/misc/ubsan.c
91
#define ACK_REPORTED __BIT(31)
lib/libnvmm/libnvmm_x86.c
1994
if (val & __BIT(7))
lib/libnvmm/libnvmm_x86.c
1997
if (val & __BIT(15))
lib/libnvmm/libnvmm_x86.c
2000
if (val & __BIT(31))
lib/libpthread/pthread_int.h
162
#define PT_CANCEL_DISABLED __BIT(0)
lib/libpthread/pthread_int.h
163
#define PT_CANCEL_ASYNC __BIT(1)
lib/libpthread/pthread_int.h
164
#define PT_CANCEL_PENDING __BIT(2)
lib/libpthread/pthread_int.h
165
#define PT_CANCEL_CANCELLED __BIT(3)
sbin/efi/bootvar.h
38
#define LOAD_OPTION_ACTIVE __BIT(0)
sbin/efi/bootvar.h
40
#define LOAD_OPTION_FORCE_RECONNECT __BIT(1)
sbin/efi/bootvar.h
41
#define LOAD_OPTION_HIDDEN __BIT(3)
sbin/efi/bootvar.h
44
#define LOAD_OPTION_CATEGORY_APP __BIT(8)
sbin/efi/defs.h
38
#define DEBUG_STRUCT_BIT __BIT(0)
sbin/efi/defs.h
39
#define DEBUG_DATA_BIT __BIT(1)
sbin/efi/defs.h
40
#define DEBUG_EFI_IOC_BIT __BIT(2)
sbin/efi/defs.h
42
#define DEBUG_BRIEF_BIT __BIT(16)
sbin/efi/defs.h
43
#define DEBUG_VERBOSE_BIT __BIT(17)
sbin/efi/devpath3.c
418
#define SASINFO_SATA_BIT __BIT(4)
sbin/efi/devpath3.c
419
#define SASINFO_EXTERNAL_BIT __BIT(5)
sbin/efi/devpath3.c
420
#define SASINFO_EXPANDER_BIT __BIT(6)
sbin/efi/devpath5.c
66
#define BIOS_STATUS_ENABLED __BIT(8)
sbin/efi/devpath5.c
67
#define BIOS_STATUS_FAILED __BIT(9)
sbin/efi/showvar.c
61
#define EFI_OS_INDICATIONS_BOOT_TO_FW_UI __BIT(0)
sbin/efi/showvar.c
62
#define EFI_OS_INDICATIONS_TIMESTAMP_REVOCATION __BIT(1)
sbin/efi/showvar.c
63
#define EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED __BIT(2)
sbin/efi/showvar.c
64
#define EFI_OS_INDICATIONS_FMP_CAPSULE_SUPPORTED __BIT(3)
sbin/efi/showvar.c
65
#define EFI_OS_INDICATIONS_CAPSULE_RESULT_VAR_SUPPORTED __BIT(4)
sbin/efi/showvar.c
66
#define EFI_OS_INDICATIONS_START_OS_RECOVERY __BIT(5)
sbin/efi/showvar.c
67
#define EFI_OS_INDICATIONS_START_PLATFORM_RECOVERY __BIT(6)
sbin/efi/showvar.c
68
#define EFI_OS_INDICATIONS_JSON_CONFIG_DATA_REFRESH __BIT(7)
sbin/efi/showvar.c
83
#define EFI_BOOT_OPTION_SUPPORT_KEY __BIT(0) // 0x00000001
sbin/efi/showvar.c
84
#define EFI_BOOT_OPTION_SUPPORT_APP __BIT(1) // 0x00000002
sbin/efi/showvar.c
85
#define EFI_BOOT_OPTION_SUPPORT_SYSPREP __BIT(4) // 0x00000010
sbin/nvmectl/nvme.h
139
#define NVME_CE_PAGE_CS_CCC __BIT(4)
sbin/nvmectl/nvme.h
140
#define NVME_CE_PAGE_CS_NIC __BIT(3)
sbin/nvmectl/nvme.h
141
#define NVME_CE_PAGE_CS_NCC __BIT(2)
sbin/nvmectl/nvme.h
142
#define NVME_CE_PAGE_CS_LBCC __BIT(1)
sbin/nvmectl/nvme.h
143
#define NVME_CE_PAGE_CS_CSUPP __BIT(0)
sbin/nvmectl/nvme.h
76
#define NVME_HEALTH_PAGE_CW_VOLATILE_MEMORY_BACKUP __BIT(4)
sbin/nvmectl/nvme.h
77
#define NVME_HEALTH_PAGE_CW_READ_ONLY __BIT(3)
sbin/nvmectl/nvme.h
78
#define NVME_HEALTH_PAGE_CW_DEVICE_RELIABLITY __BIT(2)
sbin/nvmectl/nvme.h
79
#define NVME_HEALTH_PAGE_CW_TEMPERTURE __BIT(1)
sbin/nvmectl/nvme.h
80
#define NVME_HEALTH_PAGE_CW_AVAIL_SPARE __BIT(0)
sbin/route/rtutil.h
35
#define RT_AFLAG __BIT(0) /* show address field */
sbin/route/rtutil.h
36
#define RT_TFLAG __BIT(1) /* show tag field */
sbin/route/rtutil.h
37
#define RT_VFLAG __BIT(2) /* show verbose statistics */
sbin/route/rtutil.h
38
#define RT_NFLAG __BIT(3) /* numeric output */
sbin/route/rtutil.h
39
#define RT_LFLAG __BIT(4) /* don't show LLINFO entries */
sys/arch/aarch64/include/armreg.h
1000
#define SCTLR_SED __BIT(8)
sys/arch/aarch64/include/armreg.h
1001
#define SCTLR_UMA __BIT(9)
sys/arch/aarch64/include/armreg.h
1002
#define SCTLR_EnRCTX __BIT(10)
sys/arch/aarch64/include/armreg.h
1003
#define SCTLR_EOS __BIT(11)
sys/arch/aarch64/include/armreg.h
1004
#define SCTLR_I __BIT(12)
sys/arch/aarch64/include/armreg.h
1005
#define SCTLR_EnDB __BIT(13)
sys/arch/aarch64/include/armreg.h
1006
#define SCTLR_DZE __BIT(14)
sys/arch/aarch64/include/armreg.h
1007
#define SCTLR_UCT __BIT(15)
sys/arch/aarch64/include/armreg.h
1008
#define SCTLR_nTWI __BIT(16)
sys/arch/aarch64/include/armreg.h
1009
#define SCTLR_nTWE __BIT(18)
sys/arch/aarch64/include/armreg.h
1010
#define SCTLR_WXN __BIT(19)
sys/arch/aarch64/include/armreg.h
1011
#define SCTLR_TSCXT __BIT(20)
sys/arch/aarch64/include/armreg.h
1012
#define SCTLR_IESB __BIT(21)
sys/arch/aarch64/include/armreg.h
1013
#define SCTLR_EIS __BIT(22)
sys/arch/aarch64/include/armreg.h
1014
#define SCTLR_SPAN __BIT(23)
sys/arch/aarch64/include/armreg.h
1015
#define SCTLR_E0E __BIT(24)
sys/arch/aarch64/include/armreg.h
1016
#define SCTLR_EE __BIT(25)
sys/arch/aarch64/include/armreg.h
1017
#define SCTLR_UCI __BIT(26)
sys/arch/aarch64/include/armreg.h
1018
#define SCTLR_EnDA __BIT(27)
sys/arch/aarch64/include/armreg.h
1019
#define SCTLR_nTLSMD __BIT(28)
sys/arch/aarch64/include/armreg.h
1020
#define SCTLR_LSMAOE __BIT(29)
sys/arch/aarch64/include/armreg.h
1021
#define SCTLR_EnIB __BIT(30)
sys/arch/aarch64/include/armreg.h
1022
#define SCTLR_EnIA __BIT(31)
sys/arch/aarch64/include/armreg.h
1023
#define SCTLR_BT0 __BIT(35)
sys/arch/aarch64/include/armreg.h
1024
#define SCTLR_BT1 __BIT(36)
sys/arch/aarch64/include/armreg.h
1025
#define SCTLR_ITFSB __BIT(37)
sys/arch/aarch64/include/armreg.h
1028
#define SCTLR_ATA0 __BIT(42)
sys/arch/aarch64/include/armreg.h
1029
#define SCTLR_ATA __BIT(43)
sys/arch/aarch64/include/armreg.h
1030
#define SCTLR_DSSBS __BIT(44)
sys/arch/aarch64/include/armreg.h
1051
#define SPSEL_SP __BIT(0); // use SP_EL0 at all exception levels
sys/arch/aarch64/include/armreg.h
1057
#define SPSR_N __BIT(31) // Negative
sys/arch/aarch64/include/armreg.h
1058
#define SPSR_Z __BIT(30) // Zero
sys/arch/aarch64/include/armreg.h
1059
#define SPSR_C __BIT(29) // Carry
sys/arch/aarch64/include/armreg.h
1060
#define SPSR_V __BIT(28) // oVerflow
sys/arch/aarch64/include/armreg.h
1061
#define SPSR_A32_Q __BIT(27) // A32: Overflow
sys/arch/aarch64/include/armreg.h
1062
#define SPSR_A32_IT1 __BIT(26) // A32: IT[1]
sys/arch/aarch64/include/armreg.h
1063
#define SPSR_A32_IT0 __BIT(25) // A32: IT[0]
sys/arch/aarch64/include/armreg.h
1064
#define SPSR_PAN __BIT(22) // Privileged Access Never
sys/arch/aarch64/include/armreg.h
1065
#define SPSR_SS __BIT(21) // Software Step
sys/arch/aarch64/include/armreg.h
1067
#define SPSR_IL __BIT(20) // Instruction Length
sys/arch/aarch64/include/armreg.h
1069
#define SPSR_IT7 __BIT(15) // A32: IT[7]
sys/arch/aarch64/include/armreg.h
1070
#define SPSR_IT6 __BIT(14) // A32: IT[6]
sys/arch/aarch64/include/armreg.h
1071
#define SPSR_IT5 __BIT(13) // A32: IT[5]
sys/arch/aarch64/include/armreg.h
1072
#define SPSR_IT4 __BIT(12) // A32: IT[4]
sys/arch/aarch64/include/armreg.h
1073
#define SPSR_IT3 __BIT(11) // A32: IT[3]
sys/arch/aarch64/include/armreg.h
1074
#define SPSR_IT2 __BIT(10) // A32: IT[2]
sys/arch/aarch64/include/armreg.h
1076
#define SPSR_A64_D __BIT(9) // A64: Debug Exception Mask
sys/arch/aarch64/include/armreg.h
1077
#define SPSR_A32_E __BIT(9) // A32: BE Endian Mode
sys/arch/aarch64/include/armreg.h
1078
#define SPSR_A __BIT(8) // Async abort (SError) Mask
sys/arch/aarch64/include/armreg.h
1079
#define SPSR_I __BIT(7) // IRQ Mask
sys/arch/aarch64/include/armreg.h
1080
#define SPSR_F __BIT(6) // FIQ Mask
sys/arch/aarch64/include/armreg.h
1081
#define SPSR_A32_T __BIT(5) // A32 Thumb Mode
sys/arch/aarch64/include/armreg.h
1082
#define SPSR_A32 __BIT(4) // A32 Mode (a part of SPSR_M)
sys/arch/aarch64/include/armreg.h
1106
#define TCR_TCMA1 __BIT(58) /* ARMv8.5-MemTag control when ADDR[59:55] = 0b11111 */
sys/arch/aarch64/include/armreg.h
1107
#define TCR_TCMA0 __BIT(57) /* ARMv8.5-MemTag control when ADDR[59:55] = 0b00000 */
sys/arch/aarch64/include/armreg.h
1108
#define TCR_E0PD1 __BIT(56) /* ARMv8.5-E0PD Faulting control for EL0 by TTBR1 */
sys/arch/aarch64/include/armreg.h
1109
#define TCR_E0PD0 __BIT(55) /* ARMv8.5-E0PD Faulting control for EL0 by TTBR0 */
sys/arch/aarch64/include/armreg.h
1110
#define TCR_NFD1 __BIT(54) /* SVE Non-fault translation table walk disable (TTBR1) */
sys/arch/aarch64/include/armreg.h
1111
#define TCR_NFD0 __BIT(53) /* SVE Non-fault translation table walk disable (TTBR0) */
sys/arch/aarch64/include/armreg.h
1112
#define TCR_TBID1 __BIT(52) /* ARMv8.3-PAuth TBI for instruction addr (TTBR1) */
sys/arch/aarch64/include/armreg.h
1113
#define TCR_TBID0 __BIT(51) /* ARMv8.3-PAuth TBI for instruction addr (TTBR0) */
sys/arch/aarch64/include/armreg.h
1114
#define TCR_HWU162 __BIT(50) /* ARMv8.1-TTPBHA bit[62] of PTE (TTBR1) */
sys/arch/aarch64/include/armreg.h
1115
#define TCR_HWU161 __BIT(49) /* ARMv8.1-TTPBHA bit[61] of PTE (TTBR1) */
sys/arch/aarch64/include/armreg.h
1116
#define TCR_HWU160 __BIT(48) /* ARMv8.1-TTPBHA bit[60] of PTE (TTBR1) */
sys/arch/aarch64/include/armreg.h
1117
#define TCR_HWU159 __BIT(47) /* ARMv8.1-TTPBHA bit[59] of PTE (TTBR1) */
sys/arch/aarch64/include/armreg.h
1118
#define TCR_HWU062 __BIT(46) /* ARMv8.1-TTPBHA bit[62] of PTE (TTBR0) */
sys/arch/aarch64/include/armreg.h
1119
#define TCR_HWU061 __BIT(45) /* ARMv8.1-TTPBHA bit[61] of PTE (TTBR0) */
sys/arch/aarch64/include/armreg.h
1120
#define TCR_HWU060 __BIT(44) /* ARMv8.1-TTPBHA bit[60] of PTE (TTBR0) */
sys/arch/aarch64/include/armreg.h
1121
#define TCR_HWU059 __BIT(43) /* ARMv8.1-TTPBHA bit[59] of PTE (TTBR0) */
sys/arch/aarch64/include/armreg.h
1122
#define TCR_HPD1 __BIT(42) /* ARMv8.1-HPD Hierarchical Permission (TTBR1) */
sys/arch/aarch64/include/armreg.h
1123
#define TCR_HPD0 __BIT(41) /* ARMv8.1-HPD Hierarchical Permission (TTBR0) */
sys/arch/aarch64/include/armreg.h
1124
#define TCR_HD __BIT(40) /* ARMv8.1-TTHM Hardware Dirty flag */
sys/arch/aarch64/include/armreg.h
1125
#define TCR_HA __BIT(39) /* ARMv8.1-TTHM Hardware Access flag */
sys/arch/aarch64/include/armreg.h
1126
#define TCR_TBI1 __BIT(38) /* ignore Top Byte TTBR1_EL1 */
sys/arch/aarch64/include/armreg.h
1127
#define TCR_TBI0 __BIT(37) /* ignore Top Byte TTBR0_EL1 */
sys/arch/aarch64/include/armreg.h
1128
#define TCR_AS64K __BIT(36) /* Use 64K ASIDs */
sys/arch/aarch64/include/armreg.h
1155
#define TCR_EPD1 __BIT(23) /* Walk Disable for TTBR1_EL1 */
sys/arch/aarch64/include/armreg.h
1156
#define TCR_A1 __BIT(22) /* ASID is in TTBR1_EL1 */
sys/arch/aarch64/include/armreg.h
116
#define CTR_EL0_DIC __BIT(29) // Instruction cache requirement
sys/arch/aarch64/include/armreg.h
117
#define CTR_EL0_IDC __BIT(28) // Data Cache clean requirement
sys/arch/aarch64/include/armreg.h
1176
#define TCR_EPD0 __BIT(7) /* Walk Disable for TTBR0 */
sys/arch/aarch64/include/armreg.h
1184
#define TCR_EL2_MTX __BIT(33) // Extended memory tag checking
sys/arch/aarch64/include/armreg.h
1185
#define TCR_EL2_DS __BIT(32) // 52-bit output address (FEAT_LPA2)
sys/arch/aarch64/include/armreg.h
1187
#define TCR_EL2_TCMA __BIT(30) // Unchecked accesses control (FEAT_MTE2)
sys/arch/aarch64/include/armreg.h
1188
#define TCR_EL2_TBID __BIT(29) // Top Byte Instruction address matching (FEAT_PAuth)
sys/arch/aarch64/include/armreg.h
1189
#define TCR_EL2_HWU62 __BIT(28) // Hardware use bit 62 (FEAT_HPDS2)
sys/arch/aarch64/include/armreg.h
1190
#define TCR_EL2_HWU61 __BIT(27) // Hardware use bit 61 (FEAT_HPDS2)
sys/arch/aarch64/include/armreg.h
1191
#define TCR_EL2_HWU60 __BIT(26) // Hardware use bit 60 (FEAT_HPDS2)
sys/arch/aarch64/include/armreg.h
1192
#define TCR_EL2_HWU59 __BIT(25) // Hardware use bit 59 (FEAT_HPDS2)
sys/arch/aarch64/include/armreg.h
1193
#define TCR_EL2_HPD __BIT(24) // Hierarchical Permission Disables (FEAT_HPDS)
sys/arch/aarch64/include/armreg.h
1195
#define TCR_EL2_HD __BIT(22) // Hardware management of dirty state (FEAT_HAFDBS)
sys/arch/aarch64/include/armreg.h
1196
#define TCR_EL2_HA __BIT(21) // Hardware Access flag update (FEAT_HAFDBS)
sys/arch/aarch64/include/armreg.h
1197
#define TCR_EL2_TBI __BIT(20) // Top Byte Ignored
sys/arch/aarch64/include/armreg.h
1250
#define VTCR_EL2_HAFT __BIT(44) // Hardware managed Access Flag (FEAT_HAFT)
sys/arch/aarch64/include/armreg.h
1252
#define VTCR_EL2_TL0 __BIT(41) // TopLevel0 permission attribute control (FEAT_THE)
sys/arch/aarch64/include/armreg.h
1253
#define VTCR_EL2_GCSH __BIT(40) // Assured translations for guarded control stacks (FEAT_THE+FEAT_GCS)
sys/arch/aarch64/include/armreg.h
1255
#define VTCR_EL2_D128 __BIT(38) // VMSAv9-128 (FEAT_D128)
sys/arch/aarch64/include/armreg.h
1256
#define VTCR_EL2_S2POE __BIT(37) // Enable stage 2 Permission Overlay (FEAT_S2POE)
sys/arch/aarch64/include/armreg.h
1257
#define VTCR_EL2_S2PIE __BIT(36) // Select Permission Model. (FEAT_S2PIE)
sys/arch/aarch64/include/armreg.h
1258
#define VTCR_EL2_TL1 __BIT(35) // TopLevel1 permission attribute control (FEAT_THE)
sys/arch/aarch64/include/armreg.h
1259
#define VTCR_EL2_AO __BIT(34) // AssuredOnly attribute enable (FEAT_THE)
sys/arch/aarch64/include/armreg.h
1260
#define VTCR_EL2_SL2 __BIT(33) // Stage 2 starting level (FEAT_LPA2)
sys/arch/aarch64/include/armreg.h
1261
#define VTCR_EL2_DS __BIT(32) // 52-bit output address (FEAT_LPA2)
sys/arch/aarch64/include/armreg.h
1263
#define VTCR_EL2_NSA __BIT(30) // Non-secure S2 translation output address space (FEAT_SEL2)
sys/arch/aarch64/include/armreg.h
1264
#define VTCR_EL2_NSW __BIT(29) // Non-secure S2 translation table address space (FEAT_SEL2)
sys/arch/aarch64/include/armreg.h
1265
#define VTCR_EL2_HWU62 __BIT(28) // Hardware use bit 62 (FEAT_HPDS2)
sys/arch/aarch64/include/armreg.h
1266
#define VTCR_EL2_HWU61 __BIT(27) // Hardware use bit 61 (FEAT_HPDS2)
sys/arch/aarch64/include/armreg.h
1267
#define VTCR_EL2_HWU60 __BIT(26) // Hardware use bit 60 (FEAT_HPDS2)
sys/arch/aarch64/include/armreg.h
1268
#define VTCR_EL2_HWU59 __BIT(25) // Hardware use bit 59 (FEAT_HPDS2)
sys/arch/aarch64/include/armreg.h
1270
#define VTCR_EL2_HD __BIT(22) // Hardware Dirty state management (FEAT_HAFDBS)
sys/arch/aarch64/include/armreg.h
1271
#define VTCR_EL2_HA __BIT(21) // Hardware Access flag management (FEAT_HAFDBS)
sys/arch/aarch64/include/armreg.h
1272
#define VTCR_EL2_VS __BIT(19) // VMID size (FEAT_VMID16)
sys/arch/aarch64/include/armreg.h
130
#define DCZID_DZP __BIT(4) // Data Zero Prohibited
sys/arch/aarch64/include/armreg.h
1327
#define DBGBCR_HMC __BIT(13)
sys/arch/aarch64/include/armreg.h
1330
#define DBGBCR_E __BIT(0)
sys/arch/aarch64/include/armreg.h
136
#define FPCR_AHP __BIT(26) // Alternative Half Precision
sys/arch/aarch64/include/armreg.h
137
#define FPCR_DN __BIT(25) // Default Nan Control
sys/arch/aarch64/include/armreg.h
138
#define FPCR_FZ __BIT(24) // Flush-To-Zero
sys/arch/aarch64/include/armreg.h
1401
#define DBGWCR_WT __BIT(20)
sys/arch/aarch64/include/armreg.h
1404
#define DBGWCR_HMC __BIT(13)
sys/arch/aarch64/include/armreg.h
1408
#define DBGWCR_E __BIT(0)
sys/arch/aarch64/include/armreg.h
1449
#define MDSCR_RXFULL __BIT(30) // for EDSCR.RXfull
sys/arch/aarch64/include/armreg.h
145
#define FPCR_FZ16 __BIT(19) // Flush-To-Zero for FP16
sys/arch/aarch64/include/armreg.h
1450
#define MDSCR_TXFULL __BIT(29) // for EDSCR.TXfull
sys/arch/aarch64/include/armreg.h
1451
#define MDSCR_RXO __BIT(27) // for EDSCR.RXO
sys/arch/aarch64/include/armreg.h
1452
#define MDSCR_TXU __BIT(26) // for EDSCR.TXU
sys/arch/aarch64/include/armreg.h
1454
#define MDSCR_TDA __BIT(21) // for EDSCR.TDA
sys/arch/aarch64/include/armreg.h
1455
#define MDSCR_MDE __BIT(15) // Monitor debug events
sys/arch/aarch64/include/armreg.h
1456
#define MDSCR_HDE __BIT(14) // for EDSCR.HDE
sys/arch/aarch64/include/armreg.h
1457
#define MDSCR_KDE __BIT(13) // Local debug enable
sys/arch/aarch64/include/armreg.h
1458
#define MDSCR_TDCC __BIT(12) // Trap Debug CommCh access
sys/arch/aarch64/include/armreg.h
1459
#define MDSCR_ERR __BIT(6) // for EDSCR.ERR
sys/arch/aarch64/include/armreg.h
1460
#define MDSCR_SS __BIT(0) // Software step
sys/arch/aarch64/include/armreg.h
147
#define FPCR_IDE __BIT(15) // Input Denormal Exception enable
sys/arch/aarch64/include/armreg.h
1473
#define PMCCFILTR_P __BIT(31) // Don't count cycles in EL1
sys/arch/aarch64/include/armreg.h
1474
#define PMCCFILTR_U __BIT(30) // Don't count cycles in EL0
sys/arch/aarch64/include/armreg.h
1475
#define PMCCFILTR_NSK __BIT(29) // Don't count cycles in NS EL1
sys/arch/aarch64/include/armreg.h
1476
#define PMCCFILTR_NSU __BIT(28) // Don't count cycles in NS EL0
sys/arch/aarch64/include/armreg.h
1477
#define PMCCFILTR_NSH __BIT(27) // Don't count cycles in NS EL2
sys/arch/aarch64/include/armreg.h
1478
#define PMCCFILTR_M __BIT(26) // Don't count cycles in EL3
sys/arch/aarch64/include/armreg.h
148
#define FPCR_IXE __BIT(12) // IneXact Exception enable
sys/arch/aarch64/include/armreg.h
1488
#define PMCNTEN_C __BIT(31) // Enable the cycle counter
sys/arch/aarch64/include/armreg.h
149
#define FPCR_UFE __BIT(11) // UnderFlow Exception enable
sys/arch/aarch64/include/armreg.h
1497
#define PMCR_LP __BIT(7) // Long event counter enable
sys/arch/aarch64/include/armreg.h
1498
#define PMCR_LC __BIT(6) // Long cycle counter enable
sys/arch/aarch64/include/armreg.h
1499
#define PMCR_DP __BIT(5) // Disable cycle counter when event
sys/arch/aarch64/include/armreg.h
150
#define FPCR_OFE __BIT(10) // OverFlow Exception enable
sys/arch/aarch64/include/armreg.h
1501
#define PMCR_X __BIT(4) // Enable export of events
sys/arch/aarch64/include/armreg.h
1502
#define PMCR_D __BIT(3) // Clock divider
sys/arch/aarch64/include/armreg.h
1503
#define PMCR_C __BIT(2) // Cycle counter reset
sys/arch/aarch64/include/armreg.h
1504
#define PMCR_P __BIT(1) // Event counter reset
sys/arch/aarch64/include/armreg.h
1505
#define PMCR_E __BIT(0) // Enable
sys/arch/aarch64/include/armreg.h
151
#define FPCR_DZE __BIT(9) // Divide by Zero Exception enable
sys/arch/aarch64/include/armreg.h
1514
#define PMEVTYPER_P __BIT(31) // Don't count events in EL1
sys/arch/aarch64/include/armreg.h
1515
#define PMEVTYPER_U __BIT(30) // Don't count events in EL0
sys/arch/aarch64/include/armreg.h
1516
#define PMEVTYPER_NSK __BIT(29) // Don't count events in NS EL1
sys/arch/aarch64/include/armreg.h
1517
#define PMEVTYPER_NSU __BIT(28) // Don't count events in NS EL0
sys/arch/aarch64/include/armreg.h
1518
#define PMEVTYPER_NSH __BIT(27) // Count events in NS EL2
sys/arch/aarch64/include/armreg.h
1519
#define PMEVTYPER_M __BIT(26) // Don't count events in EL3
sys/arch/aarch64/include/armreg.h
152
#define FPCR_IOE __BIT(8) // Invalid Operation Exception enable
sys/arch/aarch64/include/armreg.h
1520
#define PMEVTYPER_MT __BIT(25) // Count events on all CPUs with same
sys/arch/aarch64/include/armreg.h
1527
#define PMINTEN_C __BIT(31) // for the cycle counter
sys/arch/aarch64/include/armreg.h
1534
#define PMOVS_C __BIT(31) // for the cycle counter
sys/arch/aarch64/include/armreg.h
1559
#define CNTHCTL_EVNTDIR __BIT(3)
sys/arch/aarch64/include/armreg.h
1560
#define CNTHCTL_EVNTEN __BIT(2)
sys/arch/aarch64/include/armreg.h
1561
#define CNTHCTL_EL1PCEN __BIT(1)
sys/arch/aarch64/include/armreg.h
1562
#define CNTHCTL_EL1PCTEN __BIT(0)
sys/arch/aarch64/include/armreg.h
1567
#define CNTKCTL_EL0PTEN __BIT(9) // EL0 access for CNTP CVAL/TVAL/CTL
sys/arch/aarch64/include/armreg.h
1569
#define CNTKCTL_EL0VTEN __BIT(8) // EL0 access for CNTV CVAL/TVAL/CTL
sys/arch/aarch64/include/armreg.h
1572
#define CNTKCTL_EVNTDIR __BIT(3)
sys/arch/aarch64/include/armreg.h
1573
#define CNTKCTL_EVNTEN __BIT(2)
sys/arch/aarch64/include/armreg.h
1574
#define CNTKCTL_EL0VCTEN __BIT(1) // EL0 access for CNTVCT and CNTFRQ
sys/arch/aarch64/include/armreg.h
1576
#define CNTKCTL_EL0PCTEN __BIT(0) // EL0 access for CNTPCT and CNTFRQ
sys/arch/aarch64/include/armreg.h
158
#define FPSR_N32 __BIT(31) // AARCH32 Negative
sys/arch/aarch64/include/armreg.h
159
#define FPSR_Z32 __BIT(30) // AARCH32 Zero
sys/arch/aarch64/include/armreg.h
160
#define FPSR_C32 __BIT(29) // AARCH32 Carry
sys/arch/aarch64/include/armreg.h
1604
#define CNTCTL_ISTATUS __BIT(2) // Interrupt Asserted
sys/arch/aarch64/include/armreg.h
1605
#define CNTCTL_IMASK __BIT(1) // Timer Interrupt is Masked
sys/arch/aarch64/include/armreg.h
1606
#define CNTCTL_ENABLE __BIT(0) // Timer Enabled
sys/arch/aarch64/include/armreg.h
161
#define FPSR_V32 __BIT(28) // AARCH32 Overflow
sys/arch/aarch64/include/armreg.h
162
#define FPSR_QC __BIT(27) // SIMD Saturation
sys/arch/aarch64/include/armreg.h
163
#define FPSR_IDC __BIT(7) // Input Denormal Cumulative status
sys/arch/aarch64/include/armreg.h
164
#define FPSR_IXC __BIT(4) // IneXact Cumulative status
sys/arch/aarch64/include/armreg.h
165
#define FPSR_UFC __BIT(3) // UnderFlow Cumulative status
sys/arch/aarch64/include/armreg.h
166
#define FPSR_OFC __BIT(2) // OverFlow Cumulative status
sys/arch/aarch64/include/armreg.h
167
#define FPSR_DZC __BIT(1) // Divide by Zero Cumulative status
sys/arch/aarch64/include/armreg.h
1679
#define ICC_SRE_EL1_DIB __BIT(2)
sys/arch/aarch64/include/armreg.h
168
#define FPSR_IOC __BIT(0) // Invalid Operation Cumulative status
sys/arch/aarch64/include/armreg.h
1680
#define ICC_SRE_EL1_DFB __BIT(1)
sys/arch/aarch64/include/armreg.h
1681
#define ICC_SRE_EL1_SRE __BIT(0)
sys/arch/aarch64/include/armreg.h
1684
#define ICC_SRE_EL2_EN __BIT(3)
sys/arch/aarch64/include/armreg.h
1685
#define ICC_SRE_EL2_DIB __BIT(2)
sys/arch/aarch64/include/armreg.h
1686
#define ICC_SRE_EL2_DFB __BIT(1)
sys/arch/aarch64/include/armreg.h
1687
#define ICC_SRE_EL2_SRE __BIT(0)
sys/arch/aarch64/include/armreg.h
1693
#define ICC_CTLR_EL1_A3V __BIT(15)
sys/arch/aarch64/include/armreg.h
1694
#define ICC_CTLR_EL1_SEIS __BIT(14)
sys/arch/aarch64/include/armreg.h
1697
#define ICC_CTLR_EL1_PMHE __BIT(6)
sys/arch/aarch64/include/armreg.h
1698
#define ICC_CTLR_EL1_EOImode __BIT(1)
sys/arch/aarch64/include/armreg.h
1699
#define ICC_CTLR_EL1_CBPR __BIT(0)
sys/arch/aarch64/include/armreg.h
1702
#define ICC_IGRPEN_EL1_Enable __BIT(0)
sys/arch/aarch64/include/armreg.h
1706
#define ICC_SGIR_EL1_IRM __BIT(40)
sys/arch/aarch64/include/armreg.h
174
#define NZCV_N __BIT(31) // Negative
sys/arch/aarch64/include/armreg.h
175
#define NZCV_Z __BIT(30) // Zero
sys/arch/aarch64/include/armreg.h
176
#define NZCV_C __BIT(29) // Carry
sys/arch/aarch64/include/armreg.h
177
#define NZCV_V __BIT(28) // Overflow
sys/arch/aarch64/include/armreg.h
200
#define CCSIDR_WT __BIT(31) // OBSOLETE: Write-through supported
sys/arch/aarch64/include/armreg.h
201
#define CCSIDR_WB __BIT(30) // OBSOLETE: Write-back supported
sys/arch/aarch64/include/armreg.h
202
#define CCSIDR_RA __BIT(29) // OBSOLETE: Read-allocation supported
sys/arch/aarch64/include/armreg.h
203
#define CCSIDR_WA __BIT(28) // OBSOLETE: Write-allocation supported
sys/arch/aarch64/include/armreg.h
516
#define MPIDR_RES1 __BIT(31)
sys/arch/aarch64/include/armreg.h
517
#define MPIDR_U __BIT(30) // 1 = Uni-Processor System
sys/arch/aarch64/include/armreg.h
518
#define MPIDR_MT __BIT(24) // 1 = SMT(AFF0 is logical)
sys/arch/aarch64/include/armreg.h
633
#define CPACR_TTA __BIT(28) // System Register Access Traps
sys/arch/aarch64/include/armreg.h
644
#define CSSELR_IND __BIT(0) // Instruction not Data bit
sys/arch/aarch64/include/armreg.h
651
#define DAIF_D __BIT(9) // Debug Exception Mask
sys/arch/aarch64/include/armreg.h
652
#define DAIF_A __BIT(8) // SError Abort Mask
sys/arch/aarch64/include/armreg.h
653
#define DAIF_I __BIT(7) // IRQ Mask
sys/arch/aarch64/include/armreg.h
654
#define DAIF_F __BIT(6) // FIQ Mask
sys/arch/aarch64/include/armreg.h
720
#define ESR_IL __BIT(25) // Instruction Length (1=32-bit)
sys/arch/aarch64/include/armreg.h
722
#define ESR_ISS_CV __BIT(24) // common
sys/arch/aarch64/include/armreg.h
724
#define ESR_ISS_WFX_TRAP_INSN __BIT(0) // for ESR_EC_WFX
sys/arch/aarch64/include/armreg.h
731
#define ESR_ISS_SYSREG_DIRECTION __BIT(0) // for ESR_EC_SYS_REG
sys/arch/aarch64/include/armreg.h
737
#define ESR_ISS_MRC_DIRECTION __BIT(0) // for ESR_EC_CP15_RT
sys/arch/aarch64/include/armreg.h
742
#define ESR_ISS_MCRR_DIRECTION __BIT(0) // for ESR_EC_CP15_RRT
sys/arch/aarch64/include/armreg.h
745
#define ESR_ISS_INSNABORT_EA __BIT(9) // for ESC_RC_INSN_ABT_EL[01]
sys/arch/aarch64/include/armreg.h
746
#define ESR_ISS_INSNABORT_S1PTW __BIT(7) // for ESC_RC_INSN_ABT_EL[01]
sys/arch/aarch64/include/armreg.h
748
#define ESR_ISS_DATAABORT_ISV __BIT(24) // for ESC_RC_DATA_ABT_EL[01]
sys/arch/aarch64/include/armreg.h
750
#define ESR_ISS_DATAABORT_SSE __BIT(21) // for ESC_RC_DATA_ABT_EL[01]
sys/arch/aarch64/include/armreg.h
752
#define ESR_ISS_DATAABORT_SF __BIT(15) // for ESC_RC_DATA_ABT_EL[01]
sys/arch/aarch64/include/armreg.h
753
#define ESR_ISS_DATAABORT_AR __BIT(14) // for ESC_RC_DATA_ABT_EL[01]
sys/arch/aarch64/include/armreg.h
754
#define ESR_ISS_DATAABORT_EA __BIT(9) // for ESC_RC_DATA_ABT_EL[01]
sys/arch/aarch64/include/armreg.h
755
#define ESR_ISS_DATAABORT_CM __BIT(8) // for ESC_RC_DATA_ABT_EL[01]
sys/arch/aarch64/include/armreg.h
756
#define ESR_ISS_DATAABORT_S1PTW __BIT(7) // for ESC_RC_DATA_ABT_EL[01]
sys/arch/aarch64/include/armreg.h
757
#define ESR_ISS_DATAABORT_WnR __BIT(6) // for ESC_RC_DATA_ABT_EL[01]
sys/arch/aarch64/include/armreg.h
803
#define HCR_EL2_TWEDEN __BIT(59) // TWE Delay Enable (FEAT_TWED)
sys/arch/aarch64/include/armreg.h
804
#define HCR_EL2_TID5 __BIT(58) // Trap ID group 5 (FEAT_MTE2)
sys/arch/aarch64/include/armreg.h
805
#define HCR_EL2_DCT __BIT(57) // Default Cacheability Tagging (FEAT_MTE2)
sys/arch/aarch64/include/armreg.h
806
#define HCR_EL2_ATA __BIT(56) // Allocation Tag Access (FEAT_MTE2)
sys/arch/aarch64/include/armreg.h
807
#define HCR_EL2_TTLBOS __BIT(55) // Trap TLB maintenance OS (FEAT_EVT)
sys/arch/aarch64/include/armreg.h
808
#define HCR_EL2_TTLBIS __BIT(54) // Trap TLB maintenance IS (FEAT_EVT)
sys/arch/aarch64/include/armreg.h
809
#define HCR_EL2_ENSCXT __BIT(53) // Enable SCXTNUM_EL[01] access (FEAT_CSV2)
sys/arch/aarch64/include/armreg.h
810
#define HCR_EL2_TOCU __BIT(52) // Trap PoU cache maintenance
sys/arch/aarch64/include/armreg.h
811
#define HCR_EL2_AMVOFFEN __BIT(51) // Activity Monitors Virtual Offsets Enable (FEAT_AMUv1p1)
sys/arch/aarch64/include/armreg.h
812
#define HCR_EL2_TICAB __BIT(50) // Trap IC all broadcast maintenance.
sys/arch/aarch64/include/armreg.h
813
#define HCR_EL2_TID4 __BIT(49) // Trap ID group 4 (FEAT_EVT)
sys/arch/aarch64/include/armreg.h
814
#define HCR_EL2_GPF __BIT(48) // Granule Protection Faults (FEAT_RME)
sys/arch/aarch64/include/armreg.h
815
#define HCR_EL2_FIEN __BIT(47) // Fault Injection Enable (FEAT_RASv1p1)
sys/arch/aarch64/include/armreg.h
816
#define HCR_EL2_FWB __BIT(46) // Forced Write-Back (FEAT_S2FWB)
sys/arch/aarch64/include/armreg.h
817
#define HCR_EL2_NV2 __BIT(45) // Nested Virtualization (FEAT_NV2)
sys/arch/aarch64/include/armreg.h
818
#define HCR_EL2_AT __BIT(44) // Address Translation (FEAT_NV)
sys/arch/aarch64/include/armreg.h
819
#define HCR_EL2_NV1 __BIT(43) // Nested Virtualization (FEAT_NV2/FEAT_NV)
sys/arch/aarch64/include/armreg.h
820
#define HCR_EL2_NV __BIT(42) // Nested Virtualization (FEAT_NV2/FEAT_NV)
sys/arch/aarch64/include/armreg.h
821
#define HCR_EL2_API __BIT(41) // Pointer Authentication instruction (FEAT_PAuth)
sys/arch/aarch64/include/armreg.h
822
#define HCR_EL2_APK __BIT(40) // Pointer Authentication key (FEAT_PAuth)
sys/arch/aarch64/include/armreg.h
823
#define HCR_EL2_TME __BIT(39) // TME enable (FEAT_TME)
sys/arch/aarch64/include/armreg.h
824
#define HCR_EL2_MIOCNCE __BIT(38) // Mismatched Inner/Outer Cacheable Non-Coherency Enable,
sys/arch/aarch64/include/armreg.h
825
#define HCR_EL2_TEA __BIT(37) // Route synchronous External abort exceptions to EL2 (FEAT_RAS)
sys/arch/aarch64/include/armreg.h
826
#define HCR_EL2_TERR __BIT(36) // Trap accesses of Error Record registers (FEAT_RAS)
sys/arch/aarch64/include/armreg.h
827
#define HCR_EL2_TLOR __BIT(35) // Trap LOR registers (FEAT_LOR)
sys/arch/aarch64/include/armreg.h
828
#define HCR_EL2_VHE __BIT(34) // EL2 Host (FEAT_VHE)
sys/arch/aarch64/include/armreg.h
829
#define HCR_EL2_ID __BIT(33) // stage2 IC disable
sys/arch/aarch64/include/armreg.h
830
#define HCR_EL2_CD __BIT(32) // stage2 DC disable
sys/arch/aarch64/include/armreg.h
831
#define HCR_EL2_RW __BIT(31) // register width
sys/arch/aarch64/include/armreg.h
832
#define HCR_EL2_TRVM __BIT(30) // trap VM control regs read
sys/arch/aarch64/include/armreg.h
833
#define HCR_EL2_HCD __BIT(29) // HVC disable
sys/arch/aarch64/include/armreg.h
834
#define HCR_EL2_TDZ __BIT(28) // trap DC ZVA
sys/arch/aarch64/include/armreg.h
835
#define HCR_EL2_TGE __BIT(27) // trap general exceptions
sys/arch/aarch64/include/armreg.h
836
#define HCR_EL2_TVM __BIT(26) // trap VM control regs write
sys/arch/aarch64/include/armreg.h
837
#define HCR_EL2_TTLB __BIT(25) // trap TLB maintenance op
sys/arch/aarch64/include/armreg.h
838
#define HCR_EL2_TPU __BIT(24) // trap IC {IVAU,IALLU,IALLUIS},DC CVAU
sys/arch/aarch64/include/armreg.h
839
#define HCR_EL2_TPC __BIT(23) // trap DC {IVAC,CIVAC,CVAC}
sys/arch/aarch64/include/armreg.h
840
#define HCR_EL2_TSW __BIT(22) // trap DC {ISW,CSW,CISW}
sys/arch/aarch64/include/armreg.h
841
#define HCR_EL2_TACR __BIT(21) // trap ACTRL_EL1 access
sys/arch/aarch64/include/armreg.h
842
#define HCR_EL2_TIDCP __BIT(20) // trap IMPLEMENTATION DEFINED system regs
sys/arch/aarch64/include/armreg.h
843
#define HCR_EL2_TSC __BIT(19) // trap SMC
sys/arch/aarch64/include/armreg.h
844
#define HCR_EL2_TID3 __BIT(18) // trap ID group3 regs
sys/arch/aarch64/include/armreg.h
845
#define HCR_EL2_TID2 __BIT(17) // trap ID group2 regs
sys/arch/aarch64/include/armreg.h
846
#define HCR_EL2_TID1 __BIT(16) // trap ID group1 regs
sys/arch/aarch64/include/armreg.h
847
#define HCR_EL2_TID0 __BIT(15) // trap ID group0 regs
sys/arch/aarch64/include/armreg.h
848
#define HCR_EL2_TWE __BIT(14) // trap WFE
sys/arch/aarch64/include/armreg.h
849
#define HCR_EL2_TWI __BIT(13) // trap WFI
sys/arch/aarch64/include/armreg.h
850
#define HCR_EL2_DC __BIT(12) // default cacheability
sys/arch/aarch64/include/armreg.h
852
#define HCR_EL2_FB __BIT(9) // force broadcast TLBI and IC
sys/arch/aarch64/include/armreg.h
853
#define HCR_EL2_VSE __BIT(8) // inject Virtual SError
sys/arch/aarch64/include/armreg.h
854
#define HCR_EL2_VI __BIT(7) // inject Virtual IRQ
sys/arch/aarch64/include/armreg.h
855
#define HCR_EL2_VF __BIT(6) // inject Virtual FIQ
sys/arch/aarch64/include/armreg.h
856
#define HCR_EL2_AMO __BIT(5) // trap SError/AsyncAbort
sys/arch/aarch64/include/armreg.h
857
#define HCR_EL2_IMO __BIT(4) // trap IRQ
sys/arch/aarch64/include/armreg.h
858
#define HCR_EL2_FMO __BIT(3) // trap FIQ
sys/arch/aarch64/include/armreg.h
859
#define HCR_EL2_PTW __BIT(2) // Protect table walk
sys/arch/aarch64/include/armreg.h
860
#define HCR_EL2_SWIO __BIT(1) // override DC ISW to DC CISW
sys/arch/aarch64/include/armreg.h
861
#define HCR_EL2_VM __BIT(0) // enable stage2 translation
sys/arch/aarch64/include/armreg.h
866
#define HPFAR_EL2_NS __BIT(63) // Faulting IPA address space (FEAT_SEL2)
sys/arch/aarch64/include/armreg.h
875
#define HSTR_EL2_T15 __BIT(15)
sys/arch/aarch64/include/armreg.h
877
#define HSTR_EL2_T13 __BIT(13)
sys/arch/aarch64/include/armreg.h
878
#define HSTR_EL2_T12 __BIT(12)
sys/arch/aarch64/include/armreg.h
879
#define HSTR_EL2_T11 __BIT(11)
sys/arch/aarch64/include/armreg.h
880
#define HSTR_EL2_T10 __BIT(10)
sys/arch/aarch64/include/armreg.h
881
#define HSTR_EL2_T9 __BIT(9)
sys/arch/aarch64/include/armreg.h
882
#define HSTR_EL2_T8 __BIT(8)
sys/arch/aarch64/include/armreg.h
883
#define HSTR_EL2_T7 __BIT(7)
sys/arch/aarch64/include/armreg.h
884
#define HSTR_EL2_T6 __BIT(6)
sys/arch/aarch64/include/armreg.h
885
#define HSTR_EL2_T5 __BIT(5)
sys/arch/aarch64/include/armreg.h
887
#define HSTR_EL2_T3 __BIT(3)
sys/arch/aarch64/include/armreg.h
888
#define HSTR_EL2_T2 __BIT(2)
sys/arch/aarch64/include/armreg.h
889
#define HSTR_EL2_T1 __BIT(1)
sys/arch/aarch64/include/armreg.h
890
#define HSTR_EL2_T0 __BIT(0)
sys/arch/aarch64/include/armreg.h
896
#define MDCR_EL2_HPMFZS __BIT(36) // Hyp Performance Monitors Freeze-on-SPE event (FEAT_SPEv1p2)
sys/arch/aarch64/include/armreg.h
898
#define MDCR_EL2_HPMFZO __BIT(29) // Hyp Performance Monitors Freeze-on-overflow (FEAT_PMUv3p7)
sys/arch/aarch64/include/armreg.h
899
#define MDCR_EL2_MTPME __BIT(28) // Multi-threaded PMU Enable (FEAT_MTPMU and not EL3)
sys/arch/aarch64/include/armreg.h
900
#define MDCR_EL2_TDCC __BIT(27) // Trap DCC. (FEAT_FGT)
sys/arch/aarch64/include/armreg.h
901
#define MDCR_EL2_HLP __BIT(26) // Hypervisor Long event counter enable. (FEAT_PMUv3p5)
sys/arch/aarch64/include/armreg.h
903
#define MDCR_EL2_HCCD __BIT(23) // Hypervisor Cycle Counter Disable. (FEAT_PMUv3p5)
sys/arch/aarch64/include/armreg.h
905
#define MDCR_EL2_TTRF __BIT(19) // Trap Trace Filter Control. (FEAT_TRF)
sys/arch/aarch64/include/armreg.h
907
#define MDCR_EL2_HPMD __BIT(17) // Guest Performance Monitor Disable. (FEAT_PMUv3p1 and FEAT_Debugv8p2)
sys/arch/aarch64/include/armreg.h
909
#define MDCR_EL2_TPMS __BIT(14) // Trap Performance Monitor Sampling. (FEAT_SPE)
sys/arch/aarch64/include/armreg.h
911
#define MDCR_EL2_TDRA __BIT(11) // Trap Debug ROM Address register access.
sys/arch/aarch64/include/armreg.h
912
#define MDCR_EL2_TDOSA __BIT(10) // Trap debug OS-related register access. (FEAT_DoubleLock)
sys/arch/aarch64/include/armreg.h
913
#define MDCR_EL2_TDA __BIT(9) // Trap Debug Access.
sys/arch/aarch64/include/armreg.h
914
#define MDCR_EL2_TDE __BIT(8) // Trap Debug Exceptions.
sys/arch/aarch64/include/armreg.h
915
#define MDCR_EL2_HPME __BIT(7) // Enable [MDCR_EL2.HPMN .. (N-1)] event counters.
sys/arch/aarch64/include/armreg.h
916
#define MDCR_EL2_TPM __BIT(6) // Trap Performance Monitor accesses. (FEAT_PMUv3)
sys/arch/aarch64/include/armreg.h
917
#define MDCR_EL2_TPMCR __BIT(5) // Trap PMCR{_EL0,} access. (FEAT_PMUv3)
sys/arch/aarch64/include/armreg.h
918
#define MDCR_EL2_HPMN __BIT(4, 0) // Event counters range split. (FEAT_PMUv3)
sys/arch/aarch64/include/armreg.h
924
#define L2CTLR_CPUCACHEPROT __BIT(22) // CPU Cache Protection
sys/arch/aarch64/include/armreg.h
925
#define L2CTLR_SCUL2CACHEPROT __BIT(21) // SCU-L2 Cache Protection
sys/arch/aarch64/include/armreg.h
926
#define L2CTLR_L2_INPUT_LATENCY __BIT(5) // L2 Data RAM input latency
sys/arch/aarch64/include/armreg.h
927
#define L2CTLR_L2_OUTPUT_LATENCY __BIT(0) // L2 Data RAM output latency
sys/arch/aarch64/include/armreg.h
959
#define PAR_NS __BIT(9) // F=0 non-secure
sys/arch/aarch64/include/armreg.h
965
#define PAR_S __BIT(9) // F=1 failure stage
sys/arch/aarch64/include/armreg.h
966
#define PAR_PTW __BIT(8) // F=1 partial table walk
sys/arch/aarch64/include/armreg.h
968
#define PAR_F __BIT(0) // translation failed
sys/arch/aarch64/include/armreg.h
992
#define SCTLR_M __BIT(0)
sys/arch/aarch64/include/armreg.h
993
#define SCTLR_A __BIT(1)
sys/arch/aarch64/include/armreg.h
994
#define SCTLR_C __BIT(2)
sys/arch/aarch64/include/armreg.h
995
#define SCTLR_SA __BIT(3)
sys/arch/aarch64/include/armreg.h
996
#define SCTLR_SA0 __BIT(4)
sys/arch/aarch64/include/armreg.h
997
#define SCTLR_CP15BEN __BIT(5)
sys/arch/aarch64/include/armreg.h
998
#define SCTLR_nAA __BIT(6)
sys/arch/aarch64/include/armreg.h
999
#define SCTLR_ITD __BIT(7)
sys/arch/aarch64/include/cpu.h
105
#define LPI_SAVE_RESTORE_CORE __BIT(0)
sys/arch/aarch64/include/cpu.h
106
#define LPI_SAVE_RESTORE_TRACE __BIT(1)
sys/arch/aarch64/include/cpu.h
107
#define LPI_SAVE_RESTORE_GICR __BIT(2)
sys/arch/aarch64/include/cpu.h
108
#define LPI_SAVE_RESTORE_GICD __BIT(3)
sys/arch/aarch64/include/cpufunc.h
143
#define AARCH64_ADDRTOP_TAG __BIT(55) /* ECR_EL1.TBI[01]=1 */
sys/arch/aarch64/include/cpufunc.h
144
#define AARCH64_ADDRTOP_MSB __BIT(63) /* ECR_EL1.TBI[01]=0 */
sys/arch/aarch64/include/pte.h
106
#define LX_TYPE __BIT(1)
sys/arch/aarch64/include/pte.h
110
#define LX_VALID __BIT(0)
sys/arch/aarch64/include/pte.h
115
#define AARCH64_MAX_PA __BIT(48)
sys/arch/aarch64/include/pte.h
51
#define LX_TBL_NSTABLE __BIT(63) /* inherited next level */
sys/arch/aarch64/include/pte.h
57
#define LX_TBL_UXNTABLE __BIT(60) /* inherited next level */
sys/arch/aarch64/include/pte.h
58
#define LX_TBL_PXNTABLE __BIT(59) /* inherited next level */
sys/arch/aarch64/include/pte.h
64
#define LX_BLKPAG_UXN __BIT(54) /* Unprivileged Execute Never */
sys/arch/aarch64/include/pte.h
65
#define LX_BLKPAG_XN __BIT(54) /* Execute Never (EL2) */
sys/arch/aarch64/include/pte.h
66
#define LX_BLKPAG_PXN __BIT(53) /* Privileged Execute Never */
sys/arch/aarch64/include/pte.h
69
#define LX_BLKPAG_CONTIG __BIT(52) /* Hint of TLB cache */
sys/arch/aarch64/include/pte.h
70
#define LX_BLKPAG_DBM __BIT(51) /* Dirty Bit Modifier (V8.1) */
sys/arch/aarch64/include/pte.h
71
#define LX_BLKPAG_GP __BIT(50) /* Guarded Page (V8.5) */
sys/arch/aarch64/include/pte.h
74
#define LX_BLKPAG_NG __BIT(11) /* Not Global */
sys/arch/aarch64/include/pte.h
75
#define LX_S2_BLKPAG_FnXS __BIT(11)
sys/arch/aarch64/include/pte.h
76
#define LX_BLKPAG_AF __BIT(10) /* Access Flag */
sys/arch/aarch64/include/pte.h
81
#define LX_BLKPAG_AP __BIT(7)
sys/arch/aarch64/include/pte.h
84
#define LX_BLKPAG_APUSER __BIT(6)
sys/arch/aarch64/include/pte.h
85
#define LX_S2_BLKPAG_AP1_RES1 __BIT(6) /* EL2 */
sys/arch/aarch64/include/pte.h
91
#define LX_BLKPAG_NS __BIT(5)
sys/arch/alpha/alpha/interrupt.c
521
const uintptr_t si_bit = __BIT(level);
sys/arch/alpha/alpha/pmap.c
607
#define TLB_CTX_F_ASM __BIT(0)
sys/arch/alpha/alpha/pmap.c
608
#define TLB_CTX_F_IMB __BIT(1)
sys/arch/alpha/alpha/pmap.c
609
#define TLB_CTX_F_KIMB __BIT(2)
sys/arch/alpha/alpha/pmap.c
610
#define TLB_CTX_F_PV __BIT(3)
sys/arch/alpha/alpha/pmap.c
611
#define TLB_CTX_F_MULTI __BIT(4)
sys/arch/alpha/include/alpha_cpu.h
272
#define ALPHA_AESR_SWC __BIT(0) /* software completion */
sys/arch/alpha/include/alpha_cpu.h
273
#define ALPHA_AESR_INV __BIT(1) /* invalid operation */
sys/arch/alpha/include/alpha_cpu.h
274
#define ALPHA_AESR_DZE __BIT(2) /* division by zero */
sys/arch/alpha/include/alpha_cpu.h
275
#define ALPHA_AESR_OVF __BIT(3) /* overflow */
sys/arch/alpha/include/alpha_cpu.h
276
#define ALPHA_AESR_UNF __BIT(4) /* underflow */
sys/arch/alpha/include/alpha_cpu.h
277
#define ALPHA_AESR_INE __BIT(5) /* inexact result */
sys/arch/alpha/include/alpha_cpu.h
278
#define ALPHA_AESR_IOV __BIT(6) /* integer overflow */
sys/arch/alpha/include/fpu.h
100
#define IEEE_STATUS_DNO __BIT(22) /* Denormal Operand */
sys/arch/alpha/include/fpu.h
101
#define IEEE_STATUS_INE __BIT(21) /* Inexact Result */
sys/arch/alpha/include/fpu.h
102
#define IEEE_STATUS_UNF __BIT(20) /* Underflow */
sys/arch/alpha/include/fpu.h
103
#define IEEE_STATUS_OVF __BIT(19) /* Overflow */
sys/arch/alpha/include/fpu.h
104
#define IEEE_STATUS_DZE __BIT(18) /* Division By Zero */
sys/arch/alpha/include/fpu.h
105
#define IEEE_STATUS_INV __BIT(17) /* Invalid Operation */
sys/arch/alpha/include/fpu.h
107
#define IEEE_TRAP_ENABLE_DNO __BIT(6) /* Denormal Operation trap */
sys/arch/alpha/include/fpu.h
108
#define IEEE_TRAP_ENABLE_INE __BIT(5) /* Inexact Result trap */
sys/arch/alpha/include/fpu.h
109
#define IEEE_TRAP_ENABLE_UNF __BIT(4) /* Underflow trap */
sys/arch/alpha/include/fpu.h
110
#define IEEE_TRAP_ENABLE_OVF __BIT(3) /* Overflow trap */
sys/arch/alpha/include/fpu.h
111
#define IEEE_TRAP_ENABLE_DZE __BIT(2) /* Division By Zero trap */
sys/arch/alpha/include/fpu.h
112
#define IEEE_TRAP_ENABLE_INV __BIT(1) /* Invalid Operation trap */
sys/arch/alpha/include/fpu.h
114
#define IEEE_INHERIT __BIT(14)
sys/arch/alpha/include/fpu.h
115
#define IEEE_MAP_UMZ __BIT(13) /* Map underflowed outputs to zero */
sys/arch/alpha/include/fpu.h
116
#define IEEE_MAP_DMZ __BIT(12) /* Map denormal inputs to zero */
sys/arch/alpha/include/fpu.h
51
#define FPCR_SUM __BIT(63) /* Summary (OR of all exception bits) */
sys/arch/alpha/include/fpu.h
52
#define FPCR_INED __BIT(62) /* Inexact trap Disable */
sys/arch/alpha/include/fpu.h
53
#define FPCR_UNFD __BIT(61) /* Underflow trap Disable */
sys/arch/alpha/include/fpu.h
54
#define FPCR_UNDZ __BIT(60) /* Underflow to Zero */
sys/arch/alpha/include/fpu.h
60
#define FPCR_IOV __BIT(57) /* Integer Overflow */
sys/arch/alpha/include/fpu.h
61
#define FPCR_INE __BIT(56) /* Inexact Result */
sys/arch/alpha/include/fpu.h
62
#define FPCR_UNF __BIT(55) /* Underflow */
sys/arch/alpha/include/fpu.h
63
#define FPCR_OVF __BIT(54) /* Overflow */
sys/arch/alpha/include/fpu.h
64
#define FPCR_DZE __BIT(53) /* Division By Zero */
sys/arch/alpha/include/fpu.h
65
#define FPCR_INV __BIT(52) /* Invalid Operation */
sys/arch/alpha/include/fpu.h
66
#define FPCR_OVFD __BIT(51) /* Overflow trap Disable */
sys/arch/alpha/include/fpu.h
67
#define FPCR_DZED __BIT(50) /* Division By Zero trap Disable */
sys/arch/alpha/include/fpu.h
68
#define FPCR_INVD __BIT(49) /* Invalid Operation trap Disable */
sys/arch/alpha/include/fpu.h
69
#define FPCR_DNZ __BIT(48) /* Denormal Operands to Zero */
sys/arch/alpha/include/fpu.h
70
#define FPCR_DNOD __BIT(47) /* Denormal Operation tap Disable */
sys/arch/alpha/include/intr.h
121
#define SOFTINT_CLOCK_MASK __BIT(SOFTINT_CLOCK)
sys/arch/alpha/include/intr.h
122
#define SOFTINT_BIO_MASK __BIT(SOFTINT_BIO)
sys/arch/alpha/include/intr.h
123
#define SOFTINT_NET_MASK __BIT(SOFTINT_NET)
sys/arch/alpha/include/intr.h
124
#define SOFTINT_SERIAL_MASK __BIT(SOFTINT_SERIAL)
sys/arch/alpha/include/proc.h
65
#define MDLWP_FPACTIVE __BIT(63) /* FPU is active on LWP's PCU CPU */
sys/arch/alpha/pci/lcareg.h
67
#define MEMC_CAR_BCE __BIT(0) /* Bcache enable */
sys/arch/alpha/pci/lcareg.h
68
#define MEMC_CAR_ETP __BIT(2) /* Enable tag parity check */
sys/arch/alpha/pci/lcareg.h
69
#define MEMC_CAR_WWP __BIT(3) /* Write wrong tag parity */
sys/arch/alpha/pci/lcareg.h
70
#define MEMC_CAR_ECE __BIT(4) /* Enable Bcache ECC */
sys/arch/alpha/pci/lcareg.h
74
#define MEMC_CAR_WHD __BIT(14) /* Write Hold Time */
sys/arch/alpha/pci/lcareg.h
75
#define MEMC_CAR_PWR __BIT(15) /* Power Saving */
sys/arch/alpha/pci/lcareg.h
77
#define MEMC_CAR_HIT __BIT(31) /* Bcache hit */
sys/arch/alpha/pci/pci_6600.c
138
pc->pc_eligible_cpus |= __BIT(ci->ci_cpuid);
sys/arch/alpha/pci/pci_6600.c
295
if ((dec_6600_intr_enables & __BIT(irq)) == 0)
sys/arch/alpha/pci/pci_6600.c
299
(pc->pc_eligible_cpus & __BIT(cpuno)) == 0)
sys/arch/alpha/pci/pci_6600.c
302
if (dec_6600_cpu_intr_enables[cpuno] & __BIT(irq))
sys/arch/alpha/pci/pci_6600.c
322
volatile uint64_t * const dim0 = (pc->pc_eligible_cpus & __BIT(0)) ?
sys/arch/alpha/pci/pci_6600.c
324
volatile uint64_t * const dim1 = (pc->pc_eligible_cpus & __BIT(1)) ?
sys/arch/alpha/pci/pci_6600.c
326
volatile uint64_t * const dim2 = (pc->pc_eligible_cpus & __BIT(2)) ?
sys/arch/alpha/pci/pci_6600.c
328
volatile uint64_t * const dim3 = (pc->pc_eligible_cpus & __BIT(3)) ?
sys/arch/alpha/pci/pci_6600.c
354
dec_6600_intr_enables |= __BIT(irq);
sys/arch/alpha/pci/pci_6600.c
364
dec_6600_intr_enables &= ~__BIT(irq);
sys/arch/alpha/pci/pci_6600.c
372
const uint64_t intr_bit = __BIT(irq);
sys/arch/alpha/pci/pci_6600.c
377
KASSERT(pc->pc_eligible_cpus & __BIT(ci->ci_cpuid));
sys/arch/alpha/pci/pci_machdep.c
298
if ((pc->pc_eligible_cpus & __BIT(ci->ci_cpuid)) == 0) {
sys/arch/alpha/pci/sioreg.h
90
#define PIRQ_RTCTRL_NOT_ROUTED __BIT(7) /* 0 == interrupt routed */
sys/arch/alpha/pci/tsreg.h
153
# define WSBA3_DAC __BIT(39)
sys/arch/alpha/pci/tsreg.h
154
# define WSBA_SG __BIT(1)
sys/arch/alpha/pci/tsreg.h
155
# define WSBA_ENA __BIT(0)
sys/arch/alpha/pci/tsreg.h
186
#define PCTL_FDSC __BIT(0) /* fast discard enable */
sys/arch/alpha/pci/tsreg.h
187
#define PCTL_FBTB __BIT(1) /* fast back-to-back enable */
sys/arch/alpha/pci/tsreg.h
188
#define PCTL_THDIS __BIT(2) /* disable TLB anti-thrash (debug) */
sys/arch/alpha/pci/tsreg.h
189
#define PCTL_CHAINDIS __BIT(3) /* disable chaining */
sys/arch/alpha/pci/tsreg.h
190
#define PCTL_TGTLAT __BIT(4) /* target latency timers enable */
sys/arch/alpha/pci/tsreg.h
191
#define PCTL_HOLE __BIT(5) /* 512KB->1M hole enable */
sys/arch/alpha/pci/tsreg.h
192
#define PCTL_MWIN __BIT(6) /* monster window enable */
sys/arch/alpha/pci/tsreg.h
194
#define PCTL_PPRI __BIT(15) /* arbiter priority group for Pchip */
sys/arch/alpha/pci/tsreg.h
195
#define PCTL_ECCEN __BIT(18) /* ECC enable for DMA and SGTE */
sys/arch/alpha/pci/tsreg.h
196
#define PCTL_PADM __BIT(19) /* PADbus mode */
sys/arch/alpha/pci/tsreg.h
202
#define PCTL_FDSDIS __BIT(42) /* fast DMA start and SGTE disable */
sys/arch/alpha/pci/tsreg.h
203
#define PCTL_FDWDIS __BIT(43) /* fast DMA read cache block disable */
sys/arch/alpha/pci/tsreg.h
204
#define PCTL_PTEVRFY __BIT(44) /* PTE verify for DMA read */
sys/arch/alpha/pci/tsreg.h
205
#define PCTL_RPP __BIT(45) /* remote Pchip present */
sys/arch/alpha/tlsb/tlsb.c
165
tlsb_found |= __BIT(node);
sys/arch/alpha/tlsb/tlsb.c
167
ionodes |= __BIT(node);
sys/arch/alpha/tlsb/tlsb.c
198
if ((ionodes & __BIT(node)) == 0) {
sys/arch/amd64/stand/prekern/prng.c
39
#define CPUID_SEF_RDSEED __BIT(18)
sys/arch/amiga/amiga/gayle.h
17
#define GAYLE_CCMEM_DETECT __BIT(6)
sys/arch/amiga/amiga/gayle.h
18
#define GAYLE_CCMEM_BVD1 __BIT(5)
sys/arch/amiga/amiga/gayle.h
19
#define GAYLE_CCMEM_BVD2 __BIT(4)
sys/arch/amiga/amiga/gayle.h
20
#define GAYLE_CCMEM_WP __BIT(3)
sys/arch/amiga/amiga/gayle.h
21
#define GAYLE_CCMEM_BUSY __BIT(2)
sys/arch/amiga/amiga/gayle.h
23
#define GAYLE_CCIO_STSCHG __BIT(5)
sys/arch/amiga/amiga/gayle.h
24
#define GAYLE_CCIO_SPKR __BIT(4)
sys/arch/amiga/amiga/gayle.h
25
#define GAYLE_CCIO_IREQ __BIT(2)
sys/arch/amiga/amiga/gayle.h
30
#define GAYLE_INT_IDE __BIT(7)
sys/arch/amiga/amiga/gayle.h
31
#define GAYLE_INT_DETECT __BIT(6)
sys/arch/amiga/amiga/gayle.h
32
#define GAYLE_INT_BVD1 __BIT(5)
sys/arch/amiga/amiga/gayle.h
33
#define GAYLE_INT_STSCHG __BIT(5)
sys/arch/amiga/amiga/gayle.h
34
#define GAYLE_INT_BVD2 __BIT(4)
sys/arch/amiga/amiga/gayle.h
35
#define GAYLE_INT_SPKR __BIT(4)
sys/arch/amiga/amiga/gayle.h
36
#define GAYLE_INT_WP __BIT(3)
sys/arch/amiga/amiga/gayle.h
37
#define GAYLE_INT_BUSY __BIT(2)
sys/arch/amiga/amiga/gayle.h
38
#define GAYLE_INT_IREQ __BIT(2)
sys/arch/amiga/amiga/gayle.h
39
#define GAYLE_INT_IDEACK0 __BIT(1)
sys/arch/amiga/amiga/gayle.h
40
#define GAYLE_INT_IDEACK1 __BIT(0)
sys/arch/amiga/clockport/flipperreg.h
43
#define FLIPPER_HOSTCTL_CODECSEL __BIT(0)
sys/arch/amiga/clockport/flipperreg.h
44
#define FLIPPER_HOSTCTL_IRQDIS __BIT(4)
sys/arch/amiga/clockport/flipperreg.h
45
#define FLIPPER_HOSTCTL_QUERYVER __BIT(5)
sys/arch/amiga/clockport/flipperreg.h
46
#define FLIPPER_HOSTCTL_HENCLK __BIT(6)
sys/arch/amiga/clockport/flipperreg.h
47
#define FLIPPER_HOSTCTL_RESET __BIT(7)
sys/arch/amiga/dev/mntvareg.h
103
#define MNTVA_COLORMODE16 __BIT(0)
sys/arch/amiga/dev/mntvareg.h
104
#define MNTVA_COLORMODE32 __BIT(1)
sys/arch/amiga/dev/mntvareg.h
66
#define MNTVA_BLITTER_FILL __BIT(0) /* fill [x1,y1]-[x2,y2] */
sys/arch/amiga/dev/mntvareg.h
67
#define MNTVA_BLITTER_COPY __BIT(1) /* copy [x3,y3]-[x4,y4] to
sys/arch/amiga/dev/mntvareg.h
78
#define MNTVA_COLORMODE16 __BIT(0)
sys/arch/amiga/dev/mntvareg.h
79
#define MNTVA_COLORMODE32 __BIT(1)
sys/arch/amiga/dev/mntvareg.h
91
#define MNTVA_BLITTER_FILL __BIT(0) /* fill [x1,y1]-[x2,y2] */
sys/arch/amiga/dev/mntvareg.h
92
#define MNTVA_BLITTER_COPY __BIT(1) /* copy [x3,y3]-[x4,y4] to
sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c
67
#define LUT_GCR_RRE __BIT(0)
sys/arch/arm/acpi/acpi_pci_machdep.h
50
#define ACPI_PCI_FLAG_NO_MCFG __BIT(0) /* ignore MCFG table */
sys/arch/arm/acpi/sbsawdt_acpi.c
64
#define C_WCS_WS1 __BIT(2)
sys/arch/arm/acpi/sbsawdt_acpi.c
65
#define C_WCS_WS0 __BIT(1)
sys/arch/arm/acpi/sbsawdt_acpi.c
66
#define C_WCS_EN __BIT(0)
sys/arch/arm/altera/cycv_reg.h
100
#define CYCV_RSTMGR_CTRL_SWCOLDRSTREQ __BIT(0)
sys/arch/arm/altera/cycv_reg.h
103
#define CYCV_RSTMGR_MPUMODRST_CPU1 __BIT(1)
sys/arch/arm/altera/cycv_reg.h
20
#define CYCV_CLKMGR_CTRL_SAFEMODE __BIT(0)
sys/arch/arm/altera/cycv_reg.h
21
#define CYCV_CLKMGR_CTRL_ENSFMDWR __BIT(2)
sys/arch/arm/altera/cycv_reg.h
24
#define CYCV_CLKMGR_BYPASS_MAINPLL __BIT(0)
sys/arch/arm/altera/cycv_reg.h
25
#define CYCV_CLKMGR_BYPASS_SDRPLL __BIT(1)
sys/arch/arm/altera/cycv_reg.h
26
#define CYCV_CLKMGR_BYPASS_SDRPLLSRC __BIT(2)
sys/arch/arm/altera/cycv_reg.h
27
#define CYCV_CLKMGR_BYPASS_PERPLL __BIT(3)
sys/arch/arm/altera/cycv_reg.h
28
#define CYCV_CLKMGR_BYPASS_PERPLLSRC __BIT(4)
sys/arch/arm/altera/cycv_reg.h
31
#define CYCV_CLKMGR_INT_MAINPLLACHIEVED __BIT(0)
sys/arch/arm/altera/cycv_reg.h
32
#define CYCV_CLKMGR_INT_PERPLLACHIEVED __BIT(1)
sys/arch/arm/altera/cycv_reg.h
33
#define CYCV_CLKMGR_INT_SDRPLLACHIEVED __BIT(2)
sys/arch/arm/altera/cycv_reg.h
34
#define CYCV_CLKMGR_INT_MAINPLLLOST __BIT(3)
sys/arch/arm/altera/cycv_reg.h
35
#define CYCV_CLKMGR_INT_PERPLLLOST __BIT(4)
sys/arch/arm/altera/cycv_reg.h
36
#define CYCV_CLKMGR_INT_SDRPLLLOST __BIT(5)
sys/arch/arm/altera/cycv_reg.h
37
#define CYCV_CLKMGR_INTER_MAINPLLLOCKED __BIT(6)
sys/arch/arm/altera/cycv_reg.h
38
#define CYCV_CLKMGR_INTER_PERPLLLOCKED __BIT(7)
sys/arch/arm/altera/cycv_reg.h
39
#define CYCV_CLKMGR_INTER_SDRPLLLOCKED __BIT(8)
sys/arch/arm/altera/cycv_reg.h
65
#define CYCV_CLKMGR_MAIN_PLL_L4SRC_L4SP __BIT(1)
sys/arch/arm/altera/cycv_reg.h
66
#define CYCV_CLKMGR_MAIN_PLL_L4SRC_L4MP __BIT(0)
sys/arch/arm/amlogic/gxlphy.c
51
#define TSTCNTL_READ __BIT(15)
sys/arch/arm/amlogic/gxlphy.c
52
#define TSTCNTL_WRITE __BIT(14)
sys/arch/arm/amlogic/gxlphy.c
54
#define TSTCNTL_TEST_MODE __BIT(10)
sys/arch/arm/amlogic/gxlphy.c
64
#define LPI_STATUS_RSV12 __BIT(12)
sys/arch/arm/amlogic/meson6_timer.c
63
#define MESON_TIMER_MUX_TIMERD_EN __BIT(19)
sys/arch/arm/amlogic/meson6_timer.c
64
#define MESON_TIMER_MUX_TIMERC_EN __BIT(18)
sys/arch/arm/amlogic/meson6_timer.c
65
#define MESON_TIMER_MUX_TIMERB_EN __BIT(17)
sys/arch/arm/amlogic/meson6_timer.c
66
#define MESON_TIMER_MUX_TIMERA_EN __BIT(16)
sys/arch/arm/amlogic/meson6_timer.c
67
#define MESON_TIMER_MUX_TIMERD_MODE __BIT(15)
sys/arch/arm/amlogic/meson6_timer.c
68
#define MESON_TIMER_MUX_TIMERC_MODE __BIT(14)
sys/arch/arm/amlogic/meson6_timer.c
69
#define MESON_TIMER_MUX_TIMERB_MODE __BIT(13)
sys/arch/arm/amlogic/meson6_timer.c
70
#define MESON_TIMER_MUX_TIMERA_MODE __BIT(12)
sys/arch/arm/amlogic/meson8b_clkc.c
185
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(30)), /* enable */
sys/arch/arm/amlogic/meson8b_clkc.c
189
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(31)), /* l */
sys/arch/arm/amlogic/meson8b_clkc.c
190
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(29)), /* reset */
sys/arch/arm/amlogic/meson8b_clkc.c
201
__BIT(0), /* sel */
sys/arch/arm/amlogic/meson8b_clkc.c
219
__BIT(7), /* sel */
sys/arch/arm/amlogic/meson8b_clkc.c
240
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(30)), /* enable */
sys/arch/arm/amlogic/meson8b_clkc.c
244
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(31)), /* l */
sys/arch/arm/amlogic/meson8b_clkc.c
245
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(29)), /* reset */
sys/arch/arm/amlogic/meson8b_clkc.c
255
__BIT(12), /* div */
sys/arch/arm/amlogic/meson8b_clkc.c
260
MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BIT(15)), /* sdm_enable */
sys/arch/arm/amlogic/meson8b_clkc.c
262
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(25)), /* ssen */
sys/arch/arm/amlogic/meson8b_clkc.c
266
MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */
sys/arch/arm/amlogic/meson8b_clkc.c
272
MESON_CLK_PLL_REG(HHI_MPLL_CNTL9, __BIT(15)), /* sdm_enable */
sys/arch/arm/amlogic/meson8b_clkc.c
57
#define HHI_SYS_CPU_CLK_CNTL0_CLKSEL __BIT(7)
sys/arch/arm/amlogic/meson8b_clkc.c
68
#define HHI_SYS_PLL_CNTL_LOCK __BIT(31)
sys/arch/arm/amlogic/meson8b_pinctrl.c
169
.mask = __BIT(_gpiobit) \
sys/arch/arm/amlogic/meson8b_pinctrl.c
174
.mask = __BIT(_gpiobit) \
sys/arch/arm/amlogic/meson8b_pinctrl.c
179
.mask = __BIT(_gpiobit) \
sys/arch/arm/amlogic/meson8b_pinctrl.c
184
.mask = __BIT(_pullbit) \
sys/arch/arm/amlogic/meson8b_pinctrl.c
189
.mask = __BIT(_pullbit) \
sys/arch/arm/amlogic/meson8b_pinctrl.c
285
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/meson8b_pinctrl.c
290
.mask = __BIT(_bit + 16) \
sys/arch/arm/amlogic/meson8b_pinctrl.c
295
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/meson8b_pinctrl.c
300
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/meson8b_pinctrl.c
305
.mask = __BIT(_bit + 16) \
sys/arch/arm/amlogic/meson_canvasreg.h
45
#define DC_CAV_LUT_DATAH_YWRAP __BIT(23)
sys/arch/arm/amlogic/meson_canvasreg.h
46
#define DC_CAV_LUT_DATAH_XWRAP __BIT(22)
sys/arch/arm/amlogic/meson_canvasreg.h
50
#define DC_CAV_LUT_ADDR_WR_EN __BIT(9)
sys/arch/arm/amlogic/meson_canvasreg.h
51
#define DC_CAV_LUT_ADDR_RD_EN __BIT(8)
sys/arch/arm/amlogic/meson_clk.h
112
.u.gate.mask = __BIT(_bit), \
sys/arch/arm/amlogic/meson_clk.h
130
#define MESON_CLK_DIV_POWER_OF_TWO __BIT(0)
sys/arch/arm/amlogic/meson_clk.h
131
#define MESON_CLK_DIV_SET_RATE_PARENT __BIT(1)
sys/arch/arm/amlogic/meson_clk.h
132
#define MESON_CLK_DIV_CPU_SCALE_TABLE __BIT(2)
sys/arch/arm/amlogic/meson_clk.h
51
.mask = __BIT(_bit), \
sys/arch/arm/amlogic/meson_clk.h
97
#define MESON_CLK_GATE_SET_TO_DISABLE __BIT(0)
sys/arch/arm/amlogic/meson_dwmac.c
54
#define CLKGEN_ENABLE __BIT(12)
sys/arch/arm/amlogic/meson_dwmac.c
55
#define RMII_CLK_I_INVERTED __BIT(11)
sys/arch/arm/amlogic/meson_dwmac.c
56
#define PHY_CLK_ENABLE __BIT(10)
sys/arch/arm/amlogic/meson_dwmac.c
59
#define PHY_INTERFACE_SEL __BIT(0)
sys/arch/arm/amlogic/meson_genfb.c
69
#define INTERLACE __BIT(0)
sys/arch/arm/amlogic/meson_genfb.c
70
#define DBLSCAN __BIT(1)
sys/arch/arm/amlogic/meson_i2c.c
47
#define MESONI2C_CTRL_START __BIT(0)
sys/arch/arm/amlogic/meson_i2c.c
48
#define MESONI2C_CTRL_ACK_IGNORE __BIT(1)
sys/arch/arm/amlogic/meson_i2c.c
49
#define MESONI2C_CTRL_STATUS __BIT(2)
sys/arch/arm/amlogic/meson_i2c.c
50
#define MESONI2C_CTRL_ERROR __BIT(3)
sys/arch/arm/amlogic/meson_i2c.c
64
#define MESONI2C_SLAVE_SCL_LOW_EN __BIT(28)
sys/arch/arm/amlogic/meson_pinctrl.c
146
val |= __BIT(group->bit);
sys/arch/arm/amlogic/meson_pinctrl.c
148
val &= ~__BIT(group->bit);
sys/arch/arm/amlogic/meson_platform.c
78
#define MESON8B_WATCHDOG_TC_ENABLE __BIT(19)
sys/arch/arm/amlogic/meson_platform.c
86
#define MESONGX_WATCHDOG_CNTL_CLK_EN __BIT(24)
sys/arch/arm/amlogic/meson_platform.c
87
#define MESONGX_WATCHDOG_CNTL_SYS_RESET_N_EN __BIT(21)
sys/arch/arm/amlogic/meson_platform.c
88
#define MESONGX_WATCHDOG_CNTL_WDOG_EN __BIT(18)
sys/arch/arm/amlogic/meson_pwm.c
47
#define MESON_PWM_MISC_AB_B_CLK_EN __BIT(23)
sys/arch/arm/amlogic/meson_pwm.c
49
#define MESON_PWM_MISC_AB_A_CLK_EN __BIT(15)
sys/arch/arm/amlogic/meson_pwm.c
53
#define MESON_PWM_MISC_AB_DS_B_EN __BIT(3)
sys/arch/arm/amlogic/meson_pwm.c
54
#define MESON_PWM_MISC_AB_DS_A_EN __BIT(2)
sys/arch/arm/amlogic/meson_pwm.c
55
#define MESON_PWM_MISC_AB_PWM_B_EN __BIT(1)
sys/arch/arm/amlogic/meson_pwm.c
56
#define MESON_PWM_MISC_AB_PWM_A_EN __BIT(0)
sys/arch/arm/amlogic/meson_resets.c
42
#define RESET_MASK(index) __BIT((index) % 32)
sys/arch/arm/amlogic/meson_rtcreg.h
39
#define AO_RTC_REG0_UNUSED_23 __BIT(23)
sys/arch/arm/amlogic/meson_rtcreg.h
40
#define AO_RTC_REG0_SERIAL_BUSY __BIT(22)
sys/arch/arm/amlogic/meson_rtcreg.h
41
#define AO_RTC_REG0_UNUSED_21 __BIT(21)
sys/arch/arm/amlogic/meson_rtcreg.h
42
#define AO_RTC_REG0_SCLK_STATIC __BIT(20)
sys/arch/arm/amlogic/meson_rtcreg.h
44
#define AO_RTC_REG0_SERIAL_START __BIT(17)
sys/arch/arm/amlogic/meson_rtcreg.h
45
#define AO_RTC_REG0_ONE_SHOT_POLARITY __BIT(16)
sys/arch/arm/amlogic/meson_rtcreg.h
46
#define AO_RTC_REG0_RESERVED_15_11 __BIT(15,11)
sys/arch/arm/amlogic/meson_rtcreg.h
48
#define AO_RTC_REG0_RESERVED_7_6 __BIT(7,6)
sys/arch/arm/amlogic/meson_rtcreg.h
49
#define AO_RTC_REG0_TEST_MODE __BIT(5)
sys/arch/arm/amlogic/meson_rtcreg.h
50
#define AO_RTC_REG0_TEST_CLK __BIT(4)
sys/arch/arm/amlogic/meson_rtcreg.h
51
#define AO_RTC_REG0_TEST_BYPASS __BIT(3)
sys/arch/arm/amlogic/meson_rtcreg.h
52
#define AO_RTC_REG0_SDI __BIT(2)
sys/arch/arm/amlogic/meson_rtcreg.h
53
#define AO_RTC_REG0_SEN __BIT(1)
sys/arch/arm/amlogic/meson_rtcreg.h
54
#define AO_RTC_REG0_SCLK __BIT(0)
sys/arch/arm/amlogic/meson_rtcreg.h
59
#define AO_RTC_REG1_GPO_TO_DIG __BIT(3)
sys/arch/arm/amlogic/meson_rtcreg.h
60
#define AO_RTC_REG1_GPI_TO_DIG __BIT(2)
sys/arch/arm/amlogic/meson_rtcreg.h
61
#define AO_RTC_REG1_S_READY __BIT(1)
sys/arch/arm/amlogic/meson_rtcreg.h
62
#define AO_RTC_REG1_SDO __BIT(0)
sys/arch/arm/amlogic/meson_rtcreg.h
67
#define AO_RTC_REG3_USE_CLK_TB __BIT(29)
sys/arch/arm/amlogic/meson_rtcreg.h
68
#define AO_RTC_REG3_USE_NIKE_D_RTC __BIT(28)
sys/arch/arm/amlogic/meson_rtcreg.h
72
#define AO_RTC_REG3_MSR_BUSY __BIT(20)
sys/arch/arm/amlogic/meson_rtcreg.h
73
#define AO_RTC_REG3_UNUSED_19 __BIT(19)
sys/arch/arm/amlogic/meson_rtcreg.h
74
#define AO_RTC_REG3_FAST_CLK_MODE __BIT(18)
sys/arch/arm/amlogic/meson_rtcreg.h
75
#define AO_RTC_REG3_COUNT_ALWAYS __BIT(17)
sys/arch/arm/amlogic/meson_rtcreg.h
76
#define AO_RTC_REG3_MSR_EN __BIT(16)
sys/arch/arm/amlogic/meson_rtcreg.h
77
#define AO_RTC_REG3_MSR_GATE_TIME __BIT(15,0)
sys/arch/arm/amlogic/meson_rtcreg.h
93
#define RTC_SEC_ADJUST_PENDING __BIT(25)
sys/arch/arm/amlogic/meson_rtcreg.h
94
#define RTC_SEC_ADJUST_INC __BIT(24)
sys/arch/arm/amlogic/meson_rtcreg.h
95
#define RTC_SEC_ADJUST_VALID __BIT(23)
sys/arch/arm/amlogic/meson_rtcreg.h
96
#define RTC_SEC_ADJUST_MONITOR __BIT(22)
sys/arch/arm/amlogic/meson_rtcreg.h
97
#define RTC_SEC_ADJUST_RESERVED __BIT(21)
sys/arch/arm/amlogic/meson_sdhcreg.h
102
#define SD_MISC_STOP_MODE __BIT(28)
sys/arch/arm/amlogic/meson_sdhcreg.h
110
#define SD_INT_ADDL_SDIO_DAT1 __BIT(14)
sys/arch/arm/amlogic/meson_sdhcreg.h
111
#define SD_INT_TXFIFO __BIT(13)
sys/arch/arm/amlogic/meson_sdhcreg.h
112
#define SD_INT_RXFIFO __BIT(12)
sys/arch/arm/amlogic/meson_sdhcreg.h
113
#define SD_INT_DMA_DONE __BIT(11)
sys/arch/arm/amlogic/meson_sdhcreg.h
114
#define SD_INT_SDIO_DAT1 __BIT(10)
sys/arch/arm/amlogic/meson_sdhcreg.h
115
#define SD_INT_TXFIFO_THRES __BIT(9)
sys/arch/arm/amlogic/meson_sdhcreg.h
116
#define SD_INT_RXFIFO_THRES __BIT(8)
sys/arch/arm/amlogic/meson_sdhcreg.h
117
#define SD_INT_DATA_COMPLETE __BIT(7)
sys/arch/arm/amlogic/meson_sdhcreg.h
118
#define SD_INT_PACK_CRC_ERROR __BIT(6)
sys/arch/arm/amlogic/meson_sdhcreg.h
119
#define SD_INT_PACK_TIMEOUT __BIT(5)
sys/arch/arm/amlogic/meson_sdhcreg.h
120
#define SD_INT_PACK_COMPLETE __BIT(4)
sys/arch/arm/amlogic/meson_sdhcreg.h
121
#define SD_INT_DATA_BIT0_CHG __BIT(3)
sys/arch/arm/amlogic/meson_sdhcreg.h
122
#define SD_INT_RESP_CRC_ERROR __BIT(2)
sys/arch/arm/amlogic/meson_sdhcreg.h
123
#define SD_INT_RESP_TIMEOUT __BIT(1)
sys/arch/arm/amlogic/meson_sdhcreg.h
124
#define SD_INT_RESP_COMPLETE __BIT(0)
sys/arch/arm/amlogic/meson_sdhcreg.h
131
#define SD_SRST_DMA_IF __BIT(5)
sys/arch/arm/amlogic/meson_sdhcreg.h
132
#define SD_SRST_DPHY_TX __BIT(4)
sys/arch/arm/amlogic/meson_sdhcreg.h
133
#define SD_SRST_DPHY_RX __BIT(3)
sys/arch/arm/amlogic/meson_sdhcreg.h
134
#define SD_SRST_TX_FIFO __BIT(2)
sys/arch/arm/amlogic/meson_sdhcreg.h
135
#define SD_SRST_RX_FIFO __BIT(1)
sys/arch/arm/amlogic/meson_sdhcreg.h
136
#define SD_SRST_MAIN_CTRL __BIT(0)
sys/arch/arm/amlogic/meson_sdhcreg.h
140
#define SD_ENHC_DMA_RX_RESP __BIT(16)
sys/arch/arm/amlogic/meson_sdhcreg.h
141
#define SD_ENHC_DMA_TX_RESP __BIT(17)
sys/arch/arm/amlogic/meson_sdhcreg.h
49
#define SD_SEND_R1B __BIT(12)
sys/arch/arm/amlogic/meson_sdhcreg.h
50
#define SD_SEND_DATA_STOP __BIT(11)
sys/arch/arm/amlogic/meson_sdhcreg.h
51
#define SD_SEND_DATA_DIRECTION __BIT(10)
sys/arch/arm/amlogic/meson_sdhcreg.h
52
#define SD_SEND_RESPONSE_NO_CRC __BIT(9)
sys/arch/arm/amlogic/meson_sdhcreg.h
53
#define SD_SEND_RESPONSE_LENGTH __BIT(8)
sys/arch/arm/amlogic/meson_sdhcreg.h
54
#define SD_SEND_COMMAND_HAS_DATA __BIT(7)
sys/arch/arm/amlogic/meson_sdhcreg.h
55
#define SD_SEND_COMMAND_HAS_RESP __BIT(6)
sys/arch/arm/amlogic/meson_sdhcreg.h
59
#define SD_CNTL_DAT0_INT_SEL __BIT(28)
sys/arch/arm/amlogic/meson_sdhcreg.h
60
#define SD_CNTL_SDIO_IRQ_MODE __BIT(27)
sys/arch/arm/amlogic/meson_sdhcreg.h
65
#define SD_CNTL_TX_CRC_CHECK __BIT(3)
sys/arch/arm/amlogic/meson_sdhcreg.h
66
#define SD_CNTL_DDR_MODE __BIT(2)
sys/arch/arm/amlogic/meson_sdhcreg.h
72
#define SD_STAT_CMD __BIT(5)
sys/arch/arm/amlogic/meson_sdhcreg.h
74
#define SD_STAT_BUSY __BIT(0)
sys/arch/arm/amlogic/meson_sdhcreg.h
79
#define SD_CLKC_CLK_JIC __BIT(24)
sys/arch/arm/amlogic/meson_sdhcreg.h
85
#define SD_CLKC_MOD_CLK_ENABLE __BIT(15)
sys/arch/arm/amlogic/meson_sdhcreg.h
86
#define SD_CLKC_SD_CLK_ENABLE __BIT(14)
sys/arch/arm/amlogic/meson_sdhcreg.h
87
#define SD_CLKC_RX_CLK_ENABLE __BIT(13)
sys/arch/arm/amlogic/meson_sdhcreg.h
88
#define SD_CLKC_TX_CLK_ENABLE __BIT(12)
sys/arch/arm/amlogic/meson_sdhcreg.h
91
#define SD_PDMA_TXFIFO_FILL __BIT(31)
sys/arch/arm/amlogic/meson_sdhcreg.h
97
#define SD_PDMA_DMA_URGENT __BIT(4)
sys/arch/arm/amlogic/meson_sdhcreg.h
99
#define SD_PDMA_DMA_MODE __BIT(0)
sys/arch/arm/amlogic/meson_sdioreg.h
100
#define SDIO_MULT_MS_SCLK_ALWAYS __BIT(3)
sys/arch/arm/amlogic/meson_sdioreg.h
101
#define SDIO_MULT_STREAM_ENABLE __BIT(4)
sys/arch/arm/amlogic/meson_sdioreg.h
102
#define SDIO_MULT_STREAM_8BIT_MODE __BIT(5)
sys/arch/arm/amlogic/meson_sdioreg.h
104
#define SDIO_MULT_WRITE_READ_OUT_INDEX __BIT(8)
sys/arch/arm/amlogic/meson_sdioreg.h
105
#define SDIO_MULT_DATA_CATCH_READOUT_EN __BIT(9)
sys/arch/arm/amlogic/meson_sdioreg.h
106
#define SDIO_MULT_DAT0_DATA_ON_DAT1 __BIT(10)
sys/arch/arm/amlogic/meson_sdioreg.h
107
#define SDIO_MULT_DAT1_DATA_SWAPPED __BIT(11)
sys/arch/arm/amlogic/meson_sdioreg.h
113
#define SDIO_EXT_DATA_RW_NO_CRC16 __BIT(30)
sys/arch/arm/amlogic/meson_sdioreg.h
114
#define SDIO_EXT_CRC_STATUS_4LINE __BIT(31)
sys/arch/arm/amlogic/meson_sdioreg.h
45
#define SDIO_SEND_RESPONSE_NO_CRC __BIT(16)
sys/arch/arm/amlogic/meson_sdioreg.h
46
#define SDIO_SEND_RESPONSE_DATA __BIT(17)
sys/arch/arm/amlogic/meson_sdioreg.h
47
#define SDIO_SEND_RESPONSE_CRC7_FROM_8 __BIT(18)
sys/arch/arm/amlogic/meson_sdioreg.h
48
#define SDIO_SEND_CHECK_BUSY_DAT0 __BIT(19)
sys/arch/arm/amlogic/meson_sdioreg.h
49
#define SDIO_SEND_COMMAND_HAS_DATA __BIT(20)
sys/arch/arm/amlogic/meson_sdioreg.h
50
#define SDIO_SEND_USE_INT_WINDOW __BIT(21)
sys/arch/arm/amlogic/meson_sdioreg.h
54
#define SDIO_CONF_COMMAND_DISABLE_CRC __BIT(10)
sys/arch/arm/amlogic/meson_sdioreg.h
55
#define SDIO_CONF_COMMAND_OUT_AT_POSEDGE __BIT(11)
sys/arch/arm/amlogic/meson_sdioreg.h
57
#define SDIO_CONF_NO_DELAY_DATA __BIT(18)
sys/arch/arm/amlogic/meson_sdioreg.h
58
#define SDIO_CONF_DATA_LATCH_AT_NEGEDGE __BIT(19)
sys/arch/arm/amlogic/meson_sdioreg.h
59
#define SDIO_CONF_BUS_WIDTH __BIT(20)
sys/arch/arm/amlogic/meson_sdioreg.h
65
#define SDIO_IRQS_CMD_BUSY __BIT(4)
sys/arch/arm/amlogic/meson_sdioreg.h
66
#define SDIO_IRQS_RESPONSE_CRC7_OK __BIT(5)
sys/arch/arm/amlogic/meson_sdioreg.h
67
#define SDIO_IRQS_DATA_READ_CRC16_OK __BIT(6)
sys/arch/arm/amlogic/meson_sdioreg.h
68
#define SDIO_IRQS_DATA_WRITE_CRC16_OK __BIT(7)
sys/arch/arm/amlogic/meson_sdioreg.h
69
#define SDIO_IRQS_IF_INT __BIT(8)
sys/arch/arm/amlogic/meson_sdioreg.h
70
#define SDIO_IRQS_CMD_INT __BIT(9)
sys/arch/arm/amlogic/meson_sdioreg.h
71
#define SDIO_IRQS_SOFT_INT __BIT(10)
sys/arch/arm/amlogic/meson_sdioreg.h
72
#define SDIO_IRQS_SET_SOFT_INT __BIT(11)
sys/arch/arm/amlogic/meson_sdioreg.h
73
#define SDIO_IRQS_STATUS_INFO __BIT(15,12)
sys/arch/arm/amlogic/meson_sdioreg.h
74
#define SDIO_IRQS_TIMING_OUT_INT __BIT(16)
sys/arch/arm/amlogic/meson_sdioreg.h
75
#define SDIO_IRQS_AMRISC_TIMING_OUT_INTEN __BIT(17)
sys/arch/arm/amlogic/meson_sdioreg.h
76
#define SDIO_IRQS_ARC_TIMING_OUT_INTEN __BIT(18)
sys/arch/arm/amlogic/meson_sdioreg.h
82
#define SDIO_IRQC_AMRISC_IF_INTEN __BIT(0)
sys/arch/arm/amlogic/meson_sdioreg.h
83
#define SDIO_IRQC_AMRISC_CMD_INTEN __BIT(1)
sys/arch/arm/amlogic/meson_sdioreg.h
84
#define SDIO_IRQC_AMRISC_SOFT_INTEN __BIT(2)
sys/arch/arm/amlogic/meson_sdioreg.h
85
#define SDIO_IRQC_ARC_IF_INTEN __BIT(3)
sys/arch/arm/amlogic/meson_sdioreg.h
86
#define SDIO_IRQC_ARC_CMD_INTEN __BIT(4)
sys/arch/arm/amlogic/meson_sdioreg.h
87
#define SDIO_IRQC_ARC_SOFT_INTEN __BIT(5)
sys/arch/arm/amlogic/meson_sdioreg.h
90
#define SDIO_IRQC_FORCE_ENABLE __BIT(14)
sys/arch/arm/amlogic/meson_sdioreg.h
91
#define SDIO_IRQC_SOFT_RESET __BIT(15)
sys/arch/arm/amlogic/meson_sdioreg.h
95
#define SDIO_IRQC_FORCE_HALT __BIT(30)
sys/arch/arm/amlogic/meson_sdioreg.h
96
#define SDIO_IRQC_HALT_HOLE __BIT(31)
sys/arch/arm/amlogic/meson_sdioreg.h
99
#define SDIO_MULT_MS_ENABLE __BIT(2)
sys/arch/arm/amlogic/meson_thermal.c
126
#define TS_AO_CALIB_SIGN_MASK __BIT(15)
sys/arch/arm/amlogic/meson_thermal.c
41
#define TS_CFG_REG1_ANA_EN_VCM __BIT(10)
sys/arch/arm/amlogic/meson_thermal.c
42
#define TS_CFG_REG1_ANA_EN_VBG __BIT(9)
sys/arch/arm/amlogic/meson_thermal.c
43
#define TS_CFG_REG1_FILTER_EN __BIT(5)
sys/arch/arm/amlogic/meson_thermal.c
44
#define TS_CFG_REG1_DEM_EN __BIT(3)
sys/arch/arm/amlogic/meson_uart.h
39
#define UART_CONTROL_TX_INT_EN __BIT(28)
sys/arch/arm/amlogic/meson_uart.h
40
#define UART_CONTROL_RX_INT_EN __BIT(27)
sys/arch/arm/amlogic/meson_uart.h
41
#define UART_CONTROL_CLEAR_ERR __BIT(24)
sys/arch/arm/amlogic/meson_uart.h
42
#define UART_CONTROL_RX_RESET __BIT(23)
sys/arch/arm/amlogic/meson_uart.h
43
#define UART_CONTROL_TX_RESET __BIT(22)
sys/arch/arm/amlogic/meson_uart.h
44
#define UART_CONTROL_RX_EN __BIT(13)
sys/arch/arm/amlogic/meson_uart.h
45
#define UART_CONTROL_TX_EN __BIT(12)
sys/arch/arm/amlogic/meson_uart.h
47
#define UART_STATUS_RX_BUSY __BIT(26)
sys/arch/arm/amlogic/meson_uart.h
48
#define UART_STATUS_TX_BUSY __BIT(25)
sys/arch/arm/amlogic/meson_uart.h
49
#define UART_STATUS_TX_EMPTY __BIT(22)
sys/arch/arm/amlogic/meson_uart.h
50
#define UART_STATUS_TX_FULL __BIT(21)
sys/arch/arm/amlogic/meson_uart.h
51
#define UART_STATUS_RX_EMPTY __BIT(20)
sys/arch/arm/amlogic/meson_uart.h
52
#define UART_STATUS_BREAK __BIT(17)
sys/arch/arm/amlogic/meson_usbctrl.c
100
#define USB_R5_ID_DIG_SYNC __BIT(0)
sys/arch/arm/amlogic/meson_usbctrl.c
46
#define U2P_R0_DRV_VBUS __BIT(5)
sys/arch/arm/amlogic/meson_usbctrl.c
47
#define U2P_R0_ID_PULLUP __BIT(4)
sys/arch/arm/amlogic/meson_usbctrl.c
48
#define U2P_R0_POWER_ON_RESET __BIT(3)
sys/arch/arm/amlogic/meson_usbctrl.c
49
#define U2P_R0_HAST_MODE __BIT(2)
sys/arch/arm/amlogic/meson_usbctrl.c
50
#define U2P_R0_POWER_OK __BIT(1)
sys/arch/arm/amlogic/meson_usbctrl.c
51
#define U2P_R0_HOST_DEVICE __BIT(0)
sys/arch/arm/amlogic/meson_usbctrl.c
53
#define U2P_R1_VBUS_VALID __BIT(3)
sys/arch/arm/amlogic/meson_usbctrl.c
54
#define U2P_R1_OTG_SESSION_VALID __BIT(2)
sys/arch/arm/amlogic/meson_usbctrl.c
55
#define U2P_R1_ID_DIG __BIT(1)
sys/arch/arm/amlogic/meson_usbctrl.c
56
#define U2P_R1_PHY_READY __BIT(0)
sys/arch/arm/amlogic/meson_usbctrl.c
62
#define USB_R0_U2D_ACT __BIT(31)
sys/arch/arm/amlogic/meson_usbctrl.c
65
#define USB_R0_P30_LANE0_EXT_PCLK_REQ __BIT(18)
sys/arch/arm/amlogic/meson_usbctrl.c
66
#define USB_R0_P30_LANE0_TX2RX_LOOPBACK __BIT(17)
sys/arch/arm/amlogic/meson_usbctrl.c
70
#define USB_R1_U3H_HOST_MSI_ENABLE __BIT(18)
sys/arch/arm/amlogic/meson_usbctrl.c
71
#define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT __BIT(17)
sys/arch/arm/amlogic/meson_usbctrl.c
72
#define USB_R1_U3H_HOST_U3_PORT_DISABLE __BIT(16)
sys/arch/arm/amlogic/meson_usbctrl.c
76
#define USB_R1_U3H_PME_ENABLE __BIT(1)
sys/arch/arm/amlogic/meson_usbctrl.c
77
#define USB_R1_U3H_BIGENDIAN_GS __BIT(0)
sys/arch/arm/amlogic/meson_usbctrl.c
82
#define USB_R3_P30_REF_SSP_EN __BIT(13)
sys/arch/arm/amlogic/meson_usbctrl.c
85
#define USB_R3_P30_SSC_ENABLE __BIT(0)
sys/arch/arm/amlogic/meson_usbctrl.c
87
#define USB_R4_P21_ONLY __BIT(4)
sys/arch/arm/amlogic/meson_usbctrl.c
89
#define USB_R4_P21_SLEEP_M0 __BIT(1)
sys/arch/arm/amlogic/meson_usbctrl.c
90
#define USB_R4_P21_PORT_RESET_0 __BIT(0)
sys/arch/arm/amlogic/meson_usbctrl.c
94
#define USB_R5_ID_DIG_IRQ __BIT(7)
sys/arch/arm/amlogic/meson_usbctrl.c
95
#define USB_R5_ID_DIG_CURR __BIT(6)
sys/arch/arm/amlogic/meson_usbctrl.c
96
#define USB_R5_ID_DIG_EN_1 __BIT(5)
sys/arch/arm/amlogic/meson_usbctrl.c
97
#define USB_R5_ID_DIG_EN_0 __BIT(4)
sys/arch/arm/amlogic/meson_usbctrl.c
99
#define USB_R5_ID_DIG_REG __BIT(1)
sys/arch/arm/amlogic/meson_usbphy.c
44
#define PREI_USB_PHY_CFG_CLK_32K_ALT_SEL __BIT(15)
sys/arch/arm/amlogic/meson_usbphy.c
49
#define PREI_USB_PHY_CTRL_POR __BIT(15)
sys/arch/arm/amlogic/meson_usbphy.c
50
#define PREI_USB_PHY_CTRL_CLK_DET __BIT(8)
sys/arch/arm/amlogic/meson_usbphy.c
52
#define PREI_USB_PHY_ADP_BC_ACA_FLOATING __BIT(26)
sys/arch/arm/amlogic/meson_usbphy.c
53
#define PREI_USB_PHY_ADP_BC_ACA_ENABLE __BIT(16)
sys/arch/arm/amlogic/meson_vpureg.h
105
#define VPP_MISC_OSD2_PREBLEND __BIT(17)
sys/arch/arm/amlogic/meson_vpureg.h
106
#define VPP_MISC_OSD1_PREBLEND __BIT(16)
sys/arch/arm/amlogic/meson_vpureg.h
107
#define VPP_MISC_OSD2_POSTBLEND __BIT(13)
sys/arch/arm/amlogic/meson_vpureg.h
108
#define VPP_MISC_OSD1_POSTBLEND __BIT(12)
sys/arch/arm/amlogic/meson_vpureg.h
109
#define VPP_MISC_POSTBLEND __BIT(7)
sys/arch/arm/amlogic/meson_vpureg.h
110
#define VPP_MISC_PREBLEND __BIT(6)
sys/arch/arm/amlogic/meson_vpureg.h
117
#define VPP_OSD_VSC_CTRL0_VSCALE_EN __BIT(24)
sys/arch/arm/amlogic/meson_vpureg.h
118
#define VPP_OSC_VSC_CTRL0_INTERLACE __BIT(23)
sys/arch/arm/amlogic/meson_vpureg.h
130
#define VPP_OSD_HSC_CTRL0_HSCALE_EN __BIT(22)
sys/arch/arm/amlogic/meson_vpureg.h
135
#define VPP_OSD_SC_CTRL0_OSC_SC_DIN_OSD1_ALPHA_MODE __BIT(14)
sys/arch/arm/amlogic/meson_vpureg.h
136
#define VPP_OSD_SC_CTRL0_OSC_SC_DIN_OSD2_ALPHA_MODE __BIT(13)
sys/arch/arm/amlogic/meson_vpureg.h
137
#define VPP_OSD_SC_CTRL0_OSC_SC_ALPHA_MODE __BIT(12)
sys/arch/arm/amlogic/meson_vpureg.h
139
#define VPP_OSD_SC_CTRL0_OSD_SC_PATH_EN __BIT(3)
sys/arch/arm/amlogic/meson_vpureg.h
57
#define VIU_OSD_CTRL_STAT_ENABLE __BIT(21)
sys/arch/arm/amlogic/meson_vpureg.h
59
#define VIU_OSD_CTRL_STAT_BLK3_ENABLE __BIT(3)
sys/arch/arm/amlogic/meson_vpureg.h
60
#define VIU_OSD_CTRL_STAT_BLK2_ENABLE __BIT(2)
sys/arch/arm/amlogic/meson_vpureg.h
61
#define VIU_OSD_CTRL_STAT_BLK1_ENABLE __BIT(1)
sys/arch/arm/amlogic/meson_vpureg.h
62
#define VIU_OSD_CTRL_STAT_BLK0_ENABLE __BIT(0)
sys/arch/arm/amlogic/meson_vpureg.h
70
#define VIU_OSD_BLK_CFG_W0_LITTLE_ENDIAN __BIT(15)
sys/arch/arm/amlogic/meson_vpureg.h
71
#define VIU_OSD_BLK_CFG_W0_RPT_Y __BIT(14)
sys/arch/arm/amlogic/meson_vpureg.h
81
#define VIU_OSD_BLK_CFG_W0_RGB_EN __BIT(7)
sys/arch/arm/amlogic/meson_vpureg.h
82
#define VIU_OSD_BLK_CFG_W0_TC_ALPHA_EN __BIT(6)
sys/arch/arm/amlogic/meson_vpureg.h
90
#define VIU_OSD_BLK_CFG_W0_INTERLACE_EN __BIT(1)
sys/arch/arm/amlogic/meson_vpureg.h
91
#define VIU_OSD_BLK_CFG_W0_INTERLACE_SEL_ODD __BIT(0)
sys/arch/arm/amlogic/meson_wdt.c
46
#define WATCHDOG_TC_ENABLE __BIT(19)
sys/arch/arm/amlogic/mesong12_clkc.c
101
#define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_BGR_START __BIT(19)
sys/arch/arm/amlogic/mesong12_clkc.c
104
#define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_BY_IMP __BIT(7)
sys/arch/arm/amlogic/mesong12_clkc.c
105
#define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_CAL_EN __BIT(6)
sys/arch/arm/amlogic/mesong12_clkc.c
106
#define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_CAL_RSTN __BIT(5)
sys/arch/arm/amlogic/mesong12_clkc.c
107
#define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_EDGEDRV_EN __BIT(4)
sys/arch/arm/amlogic/mesong12_clkc.c
108
#define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_EN0 __BIT(3)
sys/arch/arm/amlogic/mesong12_clkc.c
109
#define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_IN_EN __BIT(2)
sys/arch/arm/amlogic/mesong12_clkc.c
110
#define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_SEL_PW __BIT(1)
sys/arch/arm/amlogic/mesong12_clkc.c
111
#define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_SEL_STR __BIT(0)
sys/arch/arm/amlogic/mesong12_clkc.c
1278
if ((CLK_READ(sc, clk->u.mux.reg) & __BIT(11)) == 0) {
sys/arch/arm/amlogic/mesong12_clkc.c
1352
CLK_WRITE(sc, clk->u.mux.reg, val & ~__BIT(11));
sys/arch/arm/amlogic/mesong12_clkc.c
1355
#define MESON_PLL_CNTL_REG_LOCK __BIT(31)
sys/arch/arm/amlogic/mesong12_clkc.c
1356
#define MESON_PLL_CNTL_REG_RST __BIT(29)
sys/arch/arm/amlogic/mesong12_clkc.c
1357
#define MESON_PLL_CNTL_REG_EN __BIT(28)
sys/arch/arm/amlogic/mesong12_clkc.c
1401
CLK_WRITE(sc, clk->u.mux.reg, val | __BIT(11));
sys/arch/arm/amlogic/mesong12_clkc.c
187
MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BIT(28)), /* enable */ \
sys/arch/arm/amlogic/mesong12_clkc.c
191
MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BIT(31)), /* l */ \
sys/arch/arm/amlogic/mesong12_clkc.c
192
MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BIT(29)), /* reset */ \
sys/arch/arm/amlogic/mesong12_clkc.c
205
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BIT(28)), /* enable */ \
sys/arch/arm/amlogic/mesong12_clkc.c
209
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BIT(31)), /* l */ \
sys/arch/arm/amlogic/mesong12_clkc.c
210
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BIT(29)), /* reset */ \
sys/arch/arm/amlogic/mesong12_clkc.c
223
MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BIT(28)), /* enable */ \
sys/arch/arm/amlogic/mesong12_clkc.c
227
MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BIT(31)), /* l */ \
sys/arch/arm/amlogic/mesong12_clkc.c
228
MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BIT(29)), /* reset */ \
sys/arch/arm/amlogic/mesong12_clkc.c
306
MESON_CLK_PLL_REG(HHI_MPLL_CNTL1, __BIT(30)), /* sdm_enable */ \
sys/arch/arm/amlogic/mesong12_clkc.c
308
MESON_CLK_PLL_REG(HHI_MPLL_CNTL1, __BIT(29)), /* ssen */ \
sys/arch/arm/amlogic/mesong12_clkc.c
314
MESON_CLK_PLL_REG(HHI_MPLL_CNTL3, __BIT(30)), /* sdm_enable */ \
sys/arch/arm/amlogic/mesong12_clkc.c
316
MESON_CLK_PLL_REG(HHI_MPLL_CNTL3, __BIT(29)), /* ssen */ \
sys/arch/arm/amlogic/mesong12_clkc.c
322
MESON_CLK_PLL_REG(HHI_MPLL_CNTL5, __BIT(30)), /* sdm_enable */ \
sys/arch/arm/amlogic/mesong12_clkc.c
324
MESON_CLK_PLL_REG(HHI_MPLL_CNTL5, __BIT(29)), /* ssen */ \
sys/arch/arm/amlogic/mesong12_clkc.c
350
__BIT(5), /* sel */ \
sys/arch/arm/amlogic/mesong12_clkc.c
54
#define HHI_PCIE_PLL_CNTL0_PCIE_APLL_LOCK __BIT(31)
sys/arch/arm/amlogic/mesong12_clkc.c
55
#define HHI_PCIE_PLL_CNTL0_PCIE_HCSL_CAL_DONE __BIT(30)
sys/arch/arm/amlogic/mesong12_clkc.c
56
#define HHI_PCIE_PLL_CNTL0_PCIE_APLL_RESET __BIT(29)
sys/arch/arm/amlogic/mesong12_clkc.c
57
#define HHI_PCIE_PLL_CNTL0_PCIE_APLL_EN __BIT(28)
sys/arch/arm/amlogic/mesong12_clkc.c
58
#define HHI_PCIE_PLL_CNTL0_PCIE_APLL_VCO_DIV_SEL __BIT(27)
sys/arch/arm/amlogic/mesong12_clkc.c
59
#define HHI_PCIE_PLL_CNTL0_PCIE_APLL_AFC_START __BIT(26)
sys/arch/arm/amlogic/mesong12_clkc.c
64
#define HHI_PCIE_PLL_CNTL1_PCIE_APLL_SDM_EN __BIT(12)
sys/arch/arm/amlogic/mesong12_clkc.c
74
#define HHI_PCIE_PLL_CNTL3_PCIE_APLL_AFC_BYPASS_EN __BIT(31)
sys/arch/arm/amlogic/mesong12_clkc.c
77
#define HHI_PCIE_PLL_CNTL3_PCIE_APLL_AFC_NT __BIT(19)
sys/arch/arm/amlogic/mesong12_clkc.c
79
#define HHI_PCIE_PLL_CNTL3_PCIE_APLL_BIAS_LPF_EN __BIT(16)
sys/arch/arm/amlogic/mesong12_clkc.c
791
__BIT(26), /* div */ \
sys/arch/arm/amlogic/mesong12_clkc.c
803
__BIT(2), /* sel */ \
sys/arch/arm/amlogic/mesong12_clkc.c
809
__BIT(18), /* sel */ \
sys/arch/arm/amlogic/mesong12_clkc.c
815
__BIT(10), /* sel */ \
sys/arch/arm/amlogic/mesong12_clkc.c
821
__BIT(11), /* sel */ \
sys/arch/arm/amlogic/mesong12_clkc.c
829
__BIT(11), /* sel */ \
sys/arch/arm/amlogic/mesong12_clkc.c
84
#define HHI_PCIE_PLL_CNTL4_PCIE_APLL_SHIFT_EN __BIT(31)
sys/arch/arm/amlogic/mesong12_clkc.c
851
__BIT(2), /* sel */ \
sys/arch/arm/amlogic/mesong12_clkc.c
869
__BIT(18), /* sel */ \
sys/arch/arm/amlogic/mesong12_clkc.c
87
#define HHI_PCIE_PLL_CNTL4_PCIE_APLL_VCTRL_MON_EN __BIT(23)
sys/arch/arm/amlogic/mesong12_clkc.c
875
__BIT(10), /* sel */ \
sys/arch/arm/amlogic/mesong12_clkc.c
881
__BIT(11), /* sel */ \
sys/arch/arm/amlogic/mesong12_clkc.c
903
MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BIT(28)), /* enable */ \
sys/arch/arm/amlogic/mesong12_clkc.c
907
MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BIT(30)), /* l */ \
sys/arch/arm/amlogic/mesong12_clkc.c
908
MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BIT(29)), /* reset */ \
sys/arch/arm/amlogic/mesong12_clkc.c
91
#define HHI_PCIE_PLL_CNTL4_PCIE_APLL_LPF_SF __BIT(11)
sys/arch/arm/amlogic/mesong12_clkc.c
92
#define HHI_PCIE_PLL_CNTL4_PCIE_APLL_LVR_OD_EN __BIT(10)
sys/arch/arm/amlogic/mesong12_clkc.c
93
#define HHI_PCIE_PLL_CNTL4_PCIE_APLL_REFCLK_MON_EN __BIT(9)
sys/arch/arm/amlogic/mesong12_clkc.c
939
__BIT(18), /* sel */ \
sys/arch/arm/amlogic/mesong12_clkc.c
94
#define HHI_PCIE_PLL_CNTL4_PCIE_APLL_FBKCLK_MON_EN __BIT(8)
sys/arch/arm/amlogic/mesong12_clkc.c
95
#define HHI_PCIE_PLL_CNTL4_PCIE_APLL_LOAD __BIT(7)
sys/arch/arm/amlogic/mesong12_clkc.c
951
MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BIT(28)), /* enable */ \
sys/arch/arm/amlogic/mesong12_clkc.c
955
MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BIT(31)), /* l */ \
sys/arch/arm/amlogic/mesong12_clkc.c
956
MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BIT(29)), /* reset */ \
sys/arch/arm/amlogic/mesong12_clkc.c
96
#define HHI_PCIE_PLL_CNTL4_PCIE_APLL_LOAD_EN __BIT(6)
sys/arch/arm/amlogic/mesong12_clkc.c
99
#define HHI_PCIE_PLL_CNTL5_PCIE_HCSL_BGP_EN __BIT(27)
sys/arch/arm/amlogic/mesong12_usb2phy.c
100
#define USB2PHY_R16_USB2_MPLL_TDC_MODE __BIT(20)
sys/arch/arm/amlogic/mesong12_usb2phy.c
106
#define USB2PHY_R17_USB2_MPLL_FILTER_MODE __BIT(23)
sys/arch/arm/amlogic/mesong12_usb2phy.c
109
#define USB2PHY_R17_USB2_MPLL_FIX_EN __BIT(16)
sys/arch/arm/amlogic/mesong12_usb2phy.c
112
#define USB2PHY_R18_USB2_MPLL_ACG_RANGE __BIT(31)
sys/arch/arm/amlogic/mesong12_usb2phy.c
120
#define USB2PHY_R18_USB2_MPLL_DCO_CLK_SEL __BIT(13)
sys/arch/arm/amlogic/mesong12_usb2phy.c
121
#define USB2PHY_R18_USB2_MPLL_DCO_M_EN __BIT(12)
sys/arch/arm/amlogic/mesong12_usb2phy.c
127
#define USB2PHY_R20_BYPASS_CAL_DONE_R5 __BIT(31)
sys/arch/arm/amlogic/mesong12_usb2phy.c
130
#define USB2PHY_R20_USB2_BGR_START __BIT(21)
sys/arch/arm/amlogic/mesong12_usb2phy.c
133
#define USB2PHY_R20_USB2_EDGE_DRV_EN __BIT(13)
sys/arch/arm/amlogic/mesong12_usb2phy.c
135
#define USB2PHY_R20_USB2_DMON_EN __BIT(8)
sys/arch/arm/amlogic/mesong12_usb2phy.c
136
#define USB2PHY_R20_BYPASS_OTG_DET __BIT(7)
sys/arch/arm/amlogic/mesong12_usb2phy.c
137
#define USB2PHY_R20_USB2_CAL_CODE_R5 __BIT(6)
sys/arch/arm/amlogic/mesong12_usb2phy.c
138
#define USB2PHY_R20_USB2_AMON_EN __BIT(5)
sys/arch/arm/amlogic/mesong12_usb2phy.c
139
#define USB2PHY_R20_USB2_OTG_VBUSDET_EN __BIT(4)
sys/arch/arm/amlogic/mesong12_usb2phy.c
141
#define USB2PHY_R20_USB2_IDDET_EN __BIT(0)
sys/arch/arm/amlogic/mesong12_usb2phy.c
146
#define USB2PHY_R21_USB2_TX_STRG_PD __BIT(3)
sys/arch/arm/amlogic/mesong12_usb2phy.c
147
#define USB2PHY_R21_USB2_OTG_ACA_EN __BIT(2)
sys/arch/arm/amlogic/mesong12_usb2phy.c
148
#define USB2PHY_R21_USB2_CAL_ACK_EN __BIT(1)
sys/arch/arm/amlogic/mesong12_usb2phy.c
149
#define USB2PHY_R21_USB2_BGR_FORCE __BIT(0)
sys/arch/arm/amlogic/mesong12_usb2phy.c
52
#define USB2PHY_R04_TEST_BYPASS_MODE_EN __BIT(27)
sys/arch/arm/amlogic/mesong12_usb2phy.c
53
#define USB2PHY_R04_I_C2L_CAL_DONE __BIT(26)
sys/arch/arm/amlogic/mesong12_usb2phy.c
54
#define USB2PHY_R04_I_C2L_CAL_RESET_N __BIT(25)
sys/arch/arm/amlogic/mesong12_usb2phy.c
55
#define USB2PHY_R04_I_C2L_CAL_EN __BIT(24)
sys/arch/arm/amlogic/mesong12_usb2phy.c
66
#define USB2PHY_R13_I_C2L_FSLS_RX_EN __BIT(30)
sys/arch/arm/amlogic/mesong12_usb2phy.c
67
#define USB2PHY_R13_I_C2L_HS_RX_EN __BIT(29)
sys/arch/arm/amlogic/mesong12_usb2phy.c
68
#define USB2PHY_R13_I_C2L_FS_OE __BIT(28)
sys/arch/arm/amlogic/mesong12_usb2phy.c
69
#define USB2PHY_R13_I_C2L_HS_OE __BIT(27)
sys/arch/arm/amlogic/mesong12_usb2phy.c
70
#define USB2PHY_R13_I_C2L_LS_EN __BIT(26)
sys/arch/arm/amlogic/mesong12_usb2phy.c
71
#define USB2PHY_R13_I_C2L_FS_EN __BIT(25)
sys/arch/arm/amlogic/mesong12_usb2phy.c
72
#define USB2PHY_R13_I_C2L_HS_EN __BIT(24)
sys/arch/arm/amlogic/mesong12_usb2phy.c
73
#define USB2PHY_R13_BYPASS_HOST_DISCONNECT_ENABLE __BIT(23)
sys/arch/arm/amlogic/mesong12_usb2phy.c
74
#define USB2PHY_R13_BYPASS_HOST_DISCONNECT_VALUE __BIT(22)
sys/arch/arm/amlogic/mesong12_usb2phy.c
75
#define USB2PHY_R13_CLEAR_HOLD_HS_DISCONNECT __BIT(21)
sys/arch/arm/amlogic/mesong12_usb2phy.c
77
#define USB2PHY_R13_UPDATE_PMA_SIGNALS __BIT(15)
sys/arch/arm/amlogic/mesong12_usb2phy.c
78
#define USB2PHY_R13_LOAD_STAT __BIT(14)
sys/arch/arm/amlogic/mesong12_usb2phy.c
82
#define USB2PHY_R14_I_C2L_ASSERT_SINGLE_ENABLE_ZERO __BIT(6)
sys/arch/arm/amlogic/mesong12_usb2phy.c
83
#define USB2PHY_R14_I_C2L_DATA_16_8 __BIT(5)
sys/arch/arm/amlogic/mesong12_usb2phy.c
84
#define USB2PHY_R14_PG_RSTN __BIT(4)
sys/arch/arm/amlogic/mesong12_usb2phy.c
86
#define USB2PHY_R14_I_RPU_SW1_EN __BIT(1)
sys/arch/arm/amlogic/mesong12_usb2phy.c
87
#define USB2PHY_R14_I_RDP_EN __BIT(0)
sys/arch/arm/amlogic/mesong12_usb2phy.c
90
#define USB2PHY_R16_USB2_MPLL_LOCK_DIG __BIT(31)
sys/arch/arm/amlogic/mesong12_usb2phy.c
91
#define USB2PHY_R16_USB2_MPLL_LOCK __BIT(30)
sys/arch/arm/amlogic/mesong12_usb2phy.c
92
#define USB2PHY_R16_USB2_MPLL_RESET __BIT(29)
sys/arch/arm/amlogic/mesong12_usb2phy.c
93
#define USB2PHY_R16_USB2_MPLL_EN __BIT(28)
sys/arch/arm/amlogic/mesong12_usb2phy.c
94
#define USB2PHY_R16_USB2_MPLL_FAST_LOCK __BIT(27)
sys/arch/arm/amlogic/mesong12_usb2phy.c
95
#define USB2PHY_R16_USB2_MPLL_LOCK_F __BIT(26)
sys/arch/arm/amlogic/mesong12_usb2phy.c
97
#define USB2PHY_R16_USB2_MPLL_DCO_SDM_EN __BIT(23)
sys/arch/arm/amlogic/mesong12_usb2phy.c
98
#define USB2PHY_R16_USB2_MPLL_LOAD __BIT(22)
sys/arch/arm/amlogic/mesong12_usb2phy.c
99
#define USB2PHY_R16_USB2_MPLL_SDM_EN __BIT(21)
sys/arch/arm/amlogic/mesong12_usb3pciephy.c
235
val |= __BIT(7);
sys/arch/arm/amlogic/mesong12_usb3pciephy.c
251
val |= __BIT(11);
sys/arch/arm/amlogic/mesong12_usb3pciephy.c
261
val |= __BIT(14);
sys/arch/arm/amlogic/mesong12_usb3pciephy.c
44
#define USB3PCIEPHY_R1_PHY_REF_CLKDIV2 __BIT(24)
sys/arch/arm/amlogic/mesong12_usb3pciephy.c
57
#define USB3PCIEPHY_R4_PHY_CR_CAP_ADDR __BIT(19)
sys/arch/arm/amlogic/mesong12_usb3pciephy.c
58
#define USB3PCIEPHY_R4_PHY_CR_CAP_DATA __BIT(18)
sys/arch/arm/amlogic/mesong12_usb3pciephy.c
60
#define USB3PCIEPHY_R4_PHY_CR_READ __BIT(1)
sys/arch/arm/amlogic/mesong12_usb3pciephy.c
61
#define USB3PCIEPHY_R4_PHY_CR_WRITE __BIT(0)
sys/arch/arm/amlogic/mesong12_usb3pciephy.c
63
#define USB3PCIEPHY_R5_PHY_BS_OUT __BIT(17)
sys/arch/arm/amlogic/mesong12_usb3pciephy.c
64
#define USB3PCIEPHY_R5_PHY_CR_ACK __BIT(16)
sys/arch/arm/amlogic/mesong12a_pinctrl.c
162
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesong12a_pinctrl.c
167
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesong12a_pinctrl.c
172
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesong12a_pinctrl.c
177
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesong12a_pinctrl.c
182
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesong12a_pinctrl.c
292
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesong12a_pinctrl.c
297
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesong12a_pinctrl.c
302
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesong12a_pinctrl.c
307
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesong12a_pinctrl.c
312
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesongx_mmc.c
102
#define STATUS_CORE_BUSY __BIT(31)
sys/arch/arm/amlogic/mesongx_mmc.c
103
#define STATUS_DESC_BUSY __BIT(30)
sys/arch/arm/amlogic/mesongx_mmc.c
104
#define STATUS_BUS_FSM __BIT(29,26)
sys/arch/arm/amlogic/mesongx_mmc.c
105
#define STATUS_DS __BIT(25)
sys/arch/arm/amlogic/mesongx_mmc.c
106
#define STATUS_CMD_I __BIT(24)
sys/arch/arm/amlogic/mesongx_mmc.c
108
#define STATUS_IRQ_SDIO __BIT(15)
sys/arch/arm/amlogic/mesongx_mmc.c
109
#define STATUS_RESP_STATUS __BIT(14)
sys/arch/arm/amlogic/mesongx_mmc.c
110
#define STATUS_END_OF_CHAIN __BIT(13)
sys/arch/arm/amlogic/mesongx_mmc.c
111
#define STATUS_DESC_TIMEOUT __BIT(12)
sys/arch/arm/amlogic/mesongx_mmc.c
112
#define STATUS_RESP_TIMEOUT __BIT(11)
sys/arch/arm/amlogic/mesongx_mmc.c
113
#define STATUS_RESP_ERR __BIT(10)
sys/arch/arm/amlogic/mesongx_mmc.c
114
#define STATUS_DESC_ERR __BIT(9)
sys/arch/arm/amlogic/mesongx_mmc.c
115
#define STATUS_TXD_ERR __BIT(8)
sys/arch/arm/amlogic/mesongx_mmc.c
120
#define IRQ_EN_CFG_SECURE __BIT(16)
sys/arch/arm/amlogic/mesongx_mmc.c
121
#define IRQ_EN_IRQ_SDIO __BIT(15)
sys/arch/arm/amlogic/mesongx_mmc.c
122
#define IRQ_EN_RESP_STATUS __BIT(14)
sys/arch/arm/amlogic/mesongx_mmc.c
123
#define IRQ_EN_END_OF_CHAIN __BIT(13)
sys/arch/arm/amlogic/mesongx_mmc.c
124
#define IRQ_EN_DESC_TIMEOUT __BIT(12)
sys/arch/arm/amlogic/mesongx_mmc.c
125
#define IRQ_EN_RESP_TIMEOUT __BIT(11)
sys/arch/arm/amlogic/mesongx_mmc.c
126
#define IRQ_EN_RESP_ERR __BIT(10)
sys/arch/arm/amlogic/mesongx_mmc.c
127
#define IRQ_EN_DESC_ERR __BIT(9)
sys/arch/arm/amlogic/mesongx_mmc.c
128
#define IRQ_EN_TXD_ERR __BIT(8)
sys/arch/arm/amlogic/mesongx_mmc.c
140
#define MESONGX_MMC_FLAGS_OWNER __BIT(31)
sys/arch/arm/amlogic/mesongx_mmc.c
141
#define MESONGX_MMC_FLAGS_ERROR __BIT(30)
sys/arch/arm/amlogic/mesongx_mmc.c
143
#define MESONGX_MMC_FLAGS_DATA_NUM __BIT(23)
sys/arch/arm/amlogic/mesongx_mmc.c
144
#define MESONGX_MMC_FLAGS_RESP_NUM __BIT(22)
sys/arch/arm/amlogic/mesongx_mmc.c
145
#define MESONGX_MMC_FLAGS_RESP_128 __BIT(21)
sys/arch/arm/amlogic/mesongx_mmc.c
146
#define MESONGX_MMC_FLAGS_RESP_NOCRC __BIT(20)
sys/arch/arm/amlogic/mesongx_mmc.c
147
#define MESONGX_MMC_FLAGS_DATA_WR __BIT(19)
sys/arch/arm/amlogic/mesongx_mmc.c
148
#define MESONGX_MMC_FLAGS_DATA_IO __BIT(18)
sys/arch/arm/amlogic/mesongx_mmc.c
149
#define MESONGX_MMC_FLAGS_NO_CMD __BIT(17)
sys/arch/arm/amlogic/mesongx_mmc.c
150
#define MESONGX_MMC_FLAGS_NO_RESP __BIT(16)
sys/arch/arm/amlogic/mesongx_mmc.c
152
#define MESONGX_MMC_FLAGS_END_OF_CHAIN __BIT(11)
sys/arch/arm/amlogic/mesongx_mmc.c
153
#define MESONGX_MMC_FLAGS_R1B __BIT(10)
sys/arch/arm/amlogic/mesongx_mmc.c
154
#define MESONGX_MMC_FLAGS_BLOCK_MODE __BIT(9)
sys/arch/arm/amlogic/mesongx_mmc.c
158
#define MESONGX_MMC_DATA_BIG_ENDIAN __BIT(1)
sys/arch/arm/amlogic/mesongx_mmc.c
159
#define MESONGX_MMC_DATA_SRAM __BIT(0)
sys/arch/arm/amlogic/mesongx_mmc.c
161
#define MESONGX_MMC_RESP_SRAM __BIT(0)
sys/arch/arm/amlogic/mesongx_mmc.c
48
#define CLOCK_CFG_V2_IRQ_SDIO_SLEEP __BIT(25)
sys/arch/arm/amlogic/mesongx_mmc.c
49
#define CLOCK_CFG_V2_ALWAYS_ON __BIT(24)
sys/arch/arm/amlogic/mesongx_mmc.c
52
#define CLOCK_CFG_V3_IRQ_SDIO_SLEEP __BIT(29)
sys/arch/arm/amlogic/mesongx_mmc.c
53
#define CLOCK_CFG_V3_ALWAYS_ON __BIT(28)
sys/arch/arm/amlogic/mesongx_mmc.c
65
#define ADJUST_CALI_RISE __BIT(14)
sys/arch/arm/amlogic/mesongx_mmc.c
66
#define ADJUST_ADJ_ENABLE __BIT(13)
sys/arch/arm/amlogic/mesongx_mmc.c
67
#define ADJUST_CALI_ENABLE __BIT(12)
sys/arch/arm/amlogic/mesongx_mmc.c
71
#define CALOUT_CALI_VLD __BIT(7)
sys/arch/arm/amlogic/mesongx_mmc.c
76
#define START_DESC_BUSY __BIT(1)
sys/arch/arm/amlogic/mesongx_mmc.c
77
#define START_DESC_INT __BIT(0)
sys/arch/arm/amlogic/mesongx_mmc.c
80
#define CFG_ERR_ABORT __BIT(27)
sys/arch/arm/amlogic/mesongx_mmc.c
81
#define CFG_IRQ_DS __BIT(26)
sys/arch/arm/amlogic/mesongx_mmc.c
82
#define CFG_TXD_RETRY __BIT(25)
sys/arch/arm/amlogic/mesongx_mmc.c
83
#define CFG_TXD_ADD_ERR __BIT(24)
sys/arch/arm/amlogic/mesongx_mmc.c
84
#define CFG_AUTO_CLK __BIT(23)
sys/arch/arm/amlogic/mesongx_mmc.c
85
#define CFG_STOP_CLK __BIT(22)
sys/arch/arm/amlogic/mesongx_mmc.c
86
#define CFG_CMD_LOW __BIT(21)
sys/arch/arm/amlogic/mesongx_mmc.c
87
#define CFG_CHK_DS __BIT(20)
sys/arch/arm/amlogic/mesongx_mmc.c
88
#define CFG_IGNORE_OWNER __BIT(19)
sys/arch/arm/amlogic/mesongx_mmc.c
89
#define CFG_SDCLK_ALWAYS_ON __BIT(18)
sys/arch/arm/amlogic/mesongx_mmc.c
90
#define CFG_BLK_GAP_IP __BIT(17)
sys/arch/arm/amlogic/mesongx_mmc.c
91
#define CFG_OUT_FALL __BIT(16)
sys/arch/arm/amlogic/mesongx_mmc.c
93
#define CFG_RESP_TIMEOUT __BIT(11,8)
sys/arch/arm/amlogic/mesongx_mmc.c
95
#define CFG_DC_UGT __BIT(3)
sys/arch/arm/amlogic/mesongx_mmc.c
96
#define CFG_DDR __BIT(2)
sys/arch/arm/amlogic/mesongx_wdt.c
45
#define CNTL_CLK_DIV_EN __BIT(25)
sys/arch/arm/amlogic/mesongx_wdt.c
46
#define CNTL_CLK_EN __BIT(24)
sys/arch/arm/amlogic/mesongx_wdt.c
47
#define CNTL_SYS_RESET_N_EN __BIT(21)
sys/arch/arm/amlogic/mesongx_wdt.c
48
#define CNTL_WATCHDOG_EN __BIT(18)
sys/arch/arm/amlogic/mesongxbb_clkc.c
100
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(31)), /* l */
sys/arch/arm/amlogic/mesongxbb_clkc.c
101
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(29)), /* reset */
sys/arch/arm/amlogic/mesongxbb_clkc.c
110
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(30)), /* enable */
sys/arch/arm/amlogic/mesongxbb_clkc.c
114
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(31)), /* l */
sys/arch/arm/amlogic/mesongxbb_clkc.c
115
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(29)), /* reset */
sys/arch/arm/amlogic/mesongxbb_clkc.c
125
__BIT(12), /* div */
sys/arch/arm/amlogic/mesongxbb_clkc.c
130
MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BIT(15)), /* sdm_enable */
sys/arch/arm/amlogic/mesongxbb_clkc.c
132
MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(25)), /* ssen */
sys/arch/arm/amlogic/mesongxbb_clkc.c
136
MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */
sys/arch/arm/amlogic/mesongxbb_clkc.c
142
MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */
sys/arch/arm/amlogic/mesongxbb_clkc.c
61
#define HHI_SYS_PLL_CNTL_LOCK __BIT(31)
sys/arch/arm/amlogic/mesongxbb_clkc.c
96
MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(30)), /* enable */
sys/arch/arm/amlogic/mesongxbb_pinctrl.c
208
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesongxbb_pinctrl.c
213
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesongxbb_pinctrl.c
218
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesongxbb_pinctrl.c
223
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesongxbb_pinctrl.c
228
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesongxbb_pinctrl.c
369
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesongxbb_pinctrl.c
374
.mask = __BIT(_bit + 16) \
sys/arch/arm/amlogic/mesongxbb_pinctrl.c
379
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesongxbb_pinctrl.c
384
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesongxbb_pinctrl.c
389
.mask = __BIT(_bit + 16) \
sys/arch/arm/amlogic/mesongxl_pinctrl.c
184
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesongxl_pinctrl.c
189
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesongxl_pinctrl.c
194
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesongxl_pinctrl.c
199
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesongxl_pinctrl.c
204
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesongxl_pinctrl.c
289
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesongxl_pinctrl.c
294
.mask = __BIT(_bit + 16) \
sys/arch/arm/amlogic/mesongxl_pinctrl.c
299
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesongxl_pinctrl.c
304
.mask = __BIT(_bit) \
sys/arch/arm/amlogic/mesongxl_pinctrl.c
309
.mask = __BIT(_bit + 16) \
sys/arch/arm/amlogic/mesongxl_usb2phy.c
43
#define REG0_POWER_ON_RESET __BIT(22)
sys/arch/arm/amlogic/mesongxl_usb2phy.c
44
#define REG0_ID_PULLUP __BIT(13)
sys/arch/arm/amlogic/mesongxl_usb2phy.c
45
#define REG0_DP_PULLDOWN __BIT(6)
sys/arch/arm/amlogic/mesongxl_usb2phy.c
46
#define REG0_DM_PULLDOWN __BIT(5)
sys/arch/arm/amlogic/mesongxl_usb3phy.c
43
#define REG0_U2D_ACT __BIT(31)
sys/arch/arm/amlogic/mesongxl_usb3phy.c
49
#define REG4_P21_SLEEP_M0 __BIT(1)
sys/arch/arm/amlogic/mesongxl_usb3phy.c
53
#define REG5_ID_DIG_EN_1 __BIT(5)
sys/arch/arm/amlogic/mesongxl_usb3phy.c
54
#define REG5_ID_DIG_EN_0 __BIT(4)
sys/arch/arm/apple/apple_dart.c
50
#define DART_PARAMS2_BYPASS_SUPPORT __BIT(0)
sys/arch/arm/apple/apple_dart.c
52
#define DART_TLB_OP_BUSY __BIT(2)
sys/arch/arm/apple/apple_dart.c
53
#define DART_TLB_OP_FLUSH __BIT(20)
sys/arch/arm/apple/apple_dart.c
56
#define DART_ERR_FLAG __BIT(31)
sys/arch/arm/apple/apple_dart.c
59
#define DART_ERR_READ_FAULT __BIT(4)
sys/arch/arm/apple/apple_dart.c
60
#define DART_ERR_WRITE_FAULT __BIT(3)
sys/arch/arm/apple/apple_dart.c
61
#define DART_ERR_NOPTE __BIT(2)
sys/arch/arm/apple/apple_dart.c
62
#define DART_ERR_NOPMD __BIT(1)
sys/arch/arm/apple/apple_dart.c
63
#define DART_ERR_NOTTBR __BIT(0)
sys/arch/arm/apple/apple_dart.c
67
#define DART_CONFIG_LOCK __BIT(15)
sys/arch/arm/apple/apple_dart.c
69
#define DART_TCR_TRANSLATE_ENABLE __BIT(7)
sys/arch/arm/apple/apple_dart.c
70
#define DART_TCR_BYPASS_DART __BIT(8)
sys/arch/arm/apple/apple_dart.c
71
#define DART_TCR_BYPASS_DAPF __BIT(12)
sys/arch/arm/apple/apple_dart.c
73
#define DART_TTBR_VALID __BIT(31)
sys/arch/arm/apple/apple_dart.c
93
#define DART_L2_VALID __BIT(0)
sys/arch/arm/apple/apple_dart.c
94
#define DART_L2_FULL_PAGE __BIT(1)
sys/arch/arm/apple/apple_iic.c
61
#define I2C_MTXFIFO_START __BIT(8)
sys/arch/arm/apple/apple_iic.c
62
#define I2C_MTXFIFO_STOP __BIT(9)
sys/arch/arm/apple/apple_iic.c
63
#define I2C_MTXFIFO_READ __BIT(10)
sys/arch/arm/apple/apple_iic.c
66
#define I2C_MRXFIFO_EMPTY __BIT(8)
sys/arch/arm/apple/apple_iic.c
68
#define I2C_SMSTA_MTN __BIT(21)
sys/arch/arm/apple/apple_iic.c
69
#define I2C_SMSTA_XEN __BIT(27)
sys/arch/arm/apple/apple_iic.c
70
#define I2C_SMSTA_XBUSY __BIT(28)
sys/arch/arm/apple/apple_iic.c
73
#define I2C_CTL_MTR __BIT(9)
sys/arch/arm/apple/apple_iic.c
74
#define I2C_CTL_MRR __BIT(10)
sys/arch/arm/apple/apple_iic.c
75
#define I2C_CTL_EN __BIT(11)
sys/arch/arm/apple/apple_intc.c
145
AIC_WRITE(sc, AIC_AFFINITY(is->is_irq), __BIT(0));
sys/arch/arm/apple/apple_intc.c
181
if ((mask & __BIT(LOCALPIC_SOURCE_TIMER)) != 0) {
sys/arch/arm/apple/apple_intc.c
193
if ((mask & __BIT(LOCALPIC_SOURCE_TIMER)) != 0) {
sys/arch/arm/apple/apple_intc.c
212
atomic_or_32(&pc->pc_ipimask, __BIT(ipi));
sys/arch/arm/apple/apple_intc.c
213
AIC_WRITE(sc, AIC_IPI_SEND, __BIT(target));
sys/arch/arm/apple/apple_intc.c
294
const uint32_t pending = __BIT(intno & 0x1f);
sys/arch/arm/apple/apple_intc.c
327
__BIT(evdata & 0x1f));
sys/arch/arm/apple/apple_intc.c
432
ipimask &= ~__BIT(ipi);
sys/arch/arm/apple/apple_intc.c
76
#define AIC_IPI_OTHER __BIT(0)
sys/arch/arm/apple/apple_intc.c
82
#define AIC_MASK_BIT(irqno) __BIT((irqno) & 0x1f)
sys/arch/arm/apple/apple_mbox.c
61
#define MBOX_A2I_CTRL_FULL __BIT(16)
sys/arch/arm/apple/apple_mbox.c
63
#define MBOX_I2A_CTRL_EMPTY __BIT(17)
sys/arch/arm/apple/apple_nvme.c
71
#define ANS_CPU_CTRL_RUN __BIT(4)
sys/arch/arm/apple/apple_nvme.c
80
#define ANS_PRP_NULL_CHECK __BIT(11)
sys/arch/arm/apple/apple_nvme.c
82
#define ANS_LINEAR_SQ_CTRL_EN __BIT(0)
sys/arch/arm/apple/apple_nvme.c
98
#define ANS_NVMMU_TCB_WRITE __BIT(0)
sys/arch/arm/apple/apple_nvme.c
99
#define ANS_NVMMU_TCB_READ __BIT(1)
sys/arch/arm/apple/apple_pcie.c
68
#define PCIE_CORE_LANE_CONF_REFCLK0REQ __BIT(0)
sys/arch/arm/apple/apple_pcie.c
69
#define PCIE_CORE_LANE_CONF_REFCLK1REQ __BIT(1)
sys/arch/arm/apple/apple_pcie.c
70
#define PCIE_CORE_LANE_CONF_REFCLK0ACK __BIT(2)
sys/arch/arm/apple/apple_pcie.c
71
#define PCIE_CORE_LANE_CONF_REFCLK1ACK __BIT(3)
sys/arch/arm/apple/apple_pcie.c
72
#define PCIE_CORE_LANE_CONF_REFCLK0EN __BIT(9)
sys/arch/arm/apple/apple_pcie.c
73
#define PCIE_CORE_LANE_CONF_REFCLK1EN __BIT(10)
sys/arch/arm/apple/apple_pcie.c
75
#define PCIE_CORE_LANE_CTRL_CFGACC __BIT(15)
sys/arch/arm/apple/apple_pcie.c
78
#define PCIE_PORT_LTSSM_CTRL_START __BIT(0)
sys/arch/arm/apple/apple_pcie.c
80
#define PCIE_PORT_MSI_CTRL_EN __BIT(0)
sys/arch/arm/apple/apple_pcie.c
85
#define PCIE_PORT_LINK_STAT_UP __BIT(0)
sys/arch/arm/apple/apple_pcie.c
87
#define PCIE_PORT_APPCLK_EN __BIT(0)
sys/arch/arm/apple/apple_pcie.c
88
#define PCIE_PORT_APPCLK_CGDIS __BIT(8)
sys/arch/arm/apple/apple_pcie.c
90
#define PCIE_PORT_STAT_READY __BIT(0)
sys/arch/arm/apple/apple_pcie.c
92
#define PCIE_PORT_REFCLK_EN __BIT(0)
sys/arch/arm/apple/apple_pcie.c
93
#define PCIE_PORT_REFCLK_CGDIS __BIT(8)
sys/arch/arm/apple/apple_pcie.c
95
#define PCIE_PORT_PERST_DIS __BIT(0)
sys/arch/arm/apple/apple_pinctrl.c
66
#define GPIO_PIN_INPUT_ENABLE __BIT(9)
sys/arch/arm/apple/apple_pinctrl.c
77
#define GPIO_PIN_DATA __BIT(0)
sys/arch/arm/apple/apple_rtkit.c
172
if ((state->epmap & __BIT(endpoint)) == 0)
sys/arch/arm/apple/apple_rtkit.c
354
if ((state->epmap & __BIT(endpoint)) == 0)
sys/arch/arm/apple/apple_rtkit.c
58
#define RTKIT_MGMT_STARTEP_START __BIT(1)
sys/arch/arm/apple/apple_rtkit.c
60
#define RTKIT_MGMT_EPMAP_LAST __BIT(51)
sys/arch/arm/apple/apple_rtkit.c
65
#define RTKIT_MGMT_EPMAP_MORE __BIT(0)
sys/arch/arm/apple/apple_smc.c
101
#define APLSMC_BE __BIT(0)
sys/arch/arm/apple/apple_smc.c
102
#define APLSMC_HIDDEN __BIT(1)
sys/arch/arm/apple/apple_wdog.c
46
#define WDOG_SYS_CTL_ENABLE __BIT(2)
sys/arch/arm/arm/arm_machdep.c
245
l->l_md.md_astpending |= __BIT(1);
sys/arch/arm/arm/arm_machdep.c
257
l->l_md.md_astpending |= __BIT(0);
sys/arch/arm/arm/arm_machdep.c
277
l->l_md.md_astpending |= __BIT(0);
sys/arch/arm/arm/cpu_subr.c
118
return (atomic_load_acquire(&arm_cpu_hatched[off]) & __BIT(bit)) != 0;
sys/arch/arm/arm/cpu_subr.c
126
const u_long bit = __BIT(cpuindex % CPUINDEX_DIVISOR);
sys/arch/arm/arm/cpu_subr.c
139
const u_long bit = __BIT(cpuindex % CPUINDEX_DIVISOR);
sys/arch/arm/arm/cpu_subr.c
98
const u_long bit = __BIT(cpuno % CPUINDEX_DIVISOR);
sys/arch/arm/arm/cpufunc.c
1474
__BIT(9 + CPU_CT_xSIZE_SIZE(isize)
sys/arch/arm/arm/cpufunc.c
1481
__BIT(9 + CPU_CT_xSIZE_SIZE(isize) - CPU_CT_xSIZE_ASSOC(isize));
sys/arch/arm/arm/cpufunc.c
1500
__BIT(9 + CPU_CT_xSIZE_SIZE(dsize)
sys/arch/arm/arm/cpufunc.c
1507
__BIT(9 + CPU_CT_xSIZE_SIZE(dsize) - CPU_CT_xSIZE_ASSOC(dsize));
sys/arch/arm/arm/cpufunc.c
3020
diagset |= __BIT(24);
sys/arch/arm/arm/cpufunc.c
3024
diagset |= __BIT(12);
sys/arch/arm/arm/disassem.c
910
if (__SHIFTOUT(insn, __BIT(21)))
sys/arch/arm/arm32/arm32_machdep.c
834
VPRINTX(__BIT(cpuindex));
sys/arch/arm/broadcom/bcm2835_aux.c
144
sc->sc_clk[BCMAUX_CLOCK_UART].mask = __BIT(0);
sys/arch/arm/broadcom/bcm2835_aux.c
148
sc->sc_clk[BCMAUX_CLOCK_SPI1].mask = __BIT(1);
sys/arch/arm/broadcom/bcm2835_aux.c
152
sc->sc_clk[BCMAUX_CLOCK_SPI2].mask = __BIT(2);
sys/arch/arm/broadcom/bcm2835_bscreg.h
34
#define __BIT32(x) ((uint32_t)__BIT(x))
sys/arch/arm/broadcom/bcm2835_cm.h
35
#define CM_CTL_FLIP __BIT(8)
sys/arch/arm/broadcom/bcm2835_cm.h
36
#define CM_CTL_BUSY __BIT(7)
sys/arch/arm/broadcom/bcm2835_cm.h
37
#define CM_CTL_KILL __BIT(5)
sys/arch/arm/broadcom/bcm2835_cm.h
38
#define CM_CTL_ENAB __BIT(4)
sys/arch/arm/broadcom/bcm2835_cm.h
39
#define CM_CTL_SRC __BIT(0,3)
sys/arch/arm/broadcom/bcm2835_dmac.c
158
if ((__BIT(index) & sc->sc_channelmask) == 0)
sys/arch/arm/broadcom/bcm2835_dmac.c
211
if ((sc->sc_channelmask & __BIT(index)) == 0)
sys/arch/arm/broadcom/bcm2835_dmac.c
336
if ((sc->sc_channelmask & __BIT(index)) == 0)
sys/arch/arm/broadcom/bcm2835_dmac.h
35
#define DMAC_CS_RESET __BIT(31)
sys/arch/arm/broadcom/bcm2835_dmac.h
36
#define DMAC_CS_ABORT __BIT(30)
sys/arch/arm/broadcom/bcm2835_dmac.h
37
#define DMAC_CS_DISDEBUG __BIT(29)
sys/arch/arm/broadcom/bcm2835_dmac.h
38
#define DMAC_CS_WAIT_FOR_OUTSTANDING_WRITES __BIT(28)
sys/arch/arm/broadcom/bcm2835_dmac.h
41
#define DMAC_CS_ERROR __BIT(8)
sys/arch/arm/broadcom/bcm2835_dmac.h
42
#define DMAC_CS_WAITING_FOR_OUTSTANDING_WRITES __BIT(6)
sys/arch/arm/broadcom/bcm2835_dmac.h
43
#define DMAC_CS_DREQ_STOPS_DMA __BIT(5)
sys/arch/arm/broadcom/bcm2835_dmac.h
44
#define DMAC_CS_PAUSED __BIT(4)
sys/arch/arm/broadcom/bcm2835_dmac.h
45
#define DMAC_CS_DREQ __BIT(3)
sys/arch/arm/broadcom/bcm2835_dmac.h
46
#define DMAC_CS_INT __BIT(2)
sys/arch/arm/broadcom/bcm2835_dmac.h
47
#define DMAC_CS_END __BIT(1)
sys/arch/arm/broadcom/bcm2835_dmac.h
48
#define DMAC_CS_ACTIVE __BIT(0)
sys/arch/arm/broadcom/bcm2835_dmac.h
58
#define DMAC_DEBUG_LITE __BIT(28)
sys/arch/arm/broadcom/bcm2835_dmac.h
63
#define DMAC_DEBUG_READ_ERROR __BIT(2)
sys/arch/arm/broadcom/bcm2835_dmac.h
64
#define DMAC_DEBUG_FIFO_ERROR __BIT(1)
sys/arch/arm/broadcom/bcm2835_dmac.h
65
#define DMAC_DEBUG_READ_LAST_NOT_SET_ERROR __BIT(0)
sys/arch/arm/broadcom/bcm2835_dmac.h
72
#define DMAC_TI_NO_WIDE_BURSTS __BIT(26)
sys/arch/arm/broadcom/bcm2835_dmac.h
76
#define DMAC_TI_SRC_IGNORE __BIT(11)
sys/arch/arm/broadcom/bcm2835_dmac.h
77
#define DMAC_TI_SRC_DREQ __BIT(10)
sys/arch/arm/broadcom/bcm2835_dmac.h
78
#define DMAC_TI_SRC_WIDTH __BIT(9)
sys/arch/arm/broadcom/bcm2835_dmac.h
79
#define DMAC_TI_SRC_INC __BIT(8)
sys/arch/arm/broadcom/bcm2835_dmac.h
80
#define DMAC_TI_DEST_IGNORE __BIT(7)
sys/arch/arm/broadcom/bcm2835_dmac.h
81
#define DMAC_TI_DEST_DREQ __BIT(6)
sys/arch/arm/broadcom/bcm2835_dmac.h
82
#define DMAC_TI_DEST_WIDTH __BIT(5)
sys/arch/arm/broadcom/bcm2835_dmac.h
83
#define DMAC_TI_DEST_INC __BIT(4)
sys/arch/arm/broadcom/bcm2835_dmac.h
84
#define DMAC_TI_WAIT_RESP __BIT(3)
sys/arch/arm/broadcom/bcm2835_dmac.h
85
#define DMAC_TI_TDMODE __BIT(1)
sys/arch/arm/broadcom/bcm2835_dmac.h
86
#define DMAC_TI_INTEN __BIT(0)
sys/arch/arm/broadcom/bcm2835_gpio.c
421
pending &= ~__BIT(bit - 1);
sys/arch/arm/broadcom/bcm2835_gpio.c
427
clear_level |= __BIT(bit - 1);
sys/arch/arm/broadcom/bcm2835_gpio.c
479
mask = __BIT(pin);
sys/arch/arm/broadcom/bcm2835_gpio.c
536
mask = __BIT(eint->eint_num);
sys/arch/arm/broadcom/bcm2835_intr.c
295
#define BCM2836_INTBIT_GPUPENDING __BIT(8)
sys/arch/arm/broadcom/bcm2835_intr.c
297
#define BCM2835_INTBIT_PENDING1 __BIT(8)
sys/arch/arm/broadcom/bcm2835_intr.c
298
#define BCM2835_INTBIT_PENDING2 __BIT(9)
sys/arch/arm/broadcom/bcm2835_intr.c
419
const uint32_t oldipl_mask = __BIT(oldipl);
sys/arch/arm/broadcom/bcm2835_intr.c
688
#define BCM2836MP_GPU_IRQ __BIT(8)
sys/arch/arm/broadcom/bcm2835_intr.c
689
#define BCM2836MP_PMU_IRQ __BIT(9)
sys/arch/arm/broadcom/bcm2835_intr.c
731
__BIT(cpuid));
sys/arch/arm/broadcom/bcm2835_intr.c
770
__BIT(cpuid));
sys/arch/arm/broadcom/bcm2835_intr.c
842
BCM2836_LOCAL_MAILBOX0_SETN(cpuid), __BIT(ipi));
sys/arch/arm/broadcom/bcm2835_intr.c
888
ipimask &= ~__BIT(ipi);
sys/arch/arm/broadcom/bcm2835_pwm.h
33
#define PWM_CTL_MSEN2 __BIT(15)
sys/arch/arm/broadcom/bcm2835_pwm.h
34
#define PWM_CTL_USEF2 __BIT(13)
sys/arch/arm/broadcom/bcm2835_pwm.h
35
#define PWM_CTL_POLA2 __BIT(12)
sys/arch/arm/broadcom/bcm2835_pwm.h
36
#define PWM_CTL_SBIT2 __BIT(11)
sys/arch/arm/broadcom/bcm2835_pwm.h
37
#define PWM_CTL_RPTL2 __BIT(10)
sys/arch/arm/broadcom/bcm2835_pwm.h
38
#define PWM_CTL_MODE2 __BIT(9)
sys/arch/arm/broadcom/bcm2835_pwm.h
39
#define PWM_CTL_PWEN2 __BIT(8)
sys/arch/arm/broadcom/bcm2835_pwm.h
40
#define PWM_CTL_MSEN1 __BIT(7)
sys/arch/arm/broadcom/bcm2835_pwm.h
41
#define PWM_CTL_CLRF1 __BIT(6)
sys/arch/arm/broadcom/bcm2835_pwm.h
42
#define PWM_CTL_USEF1 __BIT(5)
sys/arch/arm/broadcom/bcm2835_pwm.h
43
#define PWM_CTL_POLA1 __BIT(4)
sys/arch/arm/broadcom/bcm2835_pwm.h
44
#define PWM_CTL_SBIT1 __BIT(3)
sys/arch/arm/broadcom/bcm2835_pwm.h
45
#define PWM_CTL_RPTL1 __BIT(2)
sys/arch/arm/broadcom/bcm2835_pwm.h
46
#define PWM_CTL_MODE1 __BIT(1)
sys/arch/arm/broadcom/bcm2835_pwm.h
47
#define PWM_CTL_PWEN1 __BIT(0)
sys/arch/arm/broadcom/bcm2835_pwm.h
48
#define PWM_CTL_WRITEZERO (__BITS(16,31)|__BIT(14))
sys/arch/arm/broadcom/bcm2835_pwm.h
50
#define PWM_STA_STA4 __BIT(12)
sys/arch/arm/broadcom/bcm2835_pwm.h
51
#define PWM_STA_STA3 __BIT(11)
sys/arch/arm/broadcom/bcm2835_pwm.h
52
#define PWM_STA_STA2 __BIT(10)
sys/arch/arm/broadcom/bcm2835_pwm.h
53
#define PWM_STA_STA1 __BIT(9)
sys/arch/arm/broadcom/bcm2835_pwm.h
54
#define PWM_STA_BERR __BIT(8)
sys/arch/arm/broadcom/bcm2835_pwm.h
55
#define PWM_STA_GAPO4 __BIT(7)
sys/arch/arm/broadcom/bcm2835_pwm.h
56
#define PWM_STA_GAPO3 __BIT(6)
sys/arch/arm/broadcom/bcm2835_pwm.h
57
#define PWM_STA_GAPO2 __BIT(5)
sys/arch/arm/broadcom/bcm2835_pwm.h
58
#define PWM_STA_GAPO1 __BIT(4)
sys/arch/arm/broadcom/bcm2835_pwm.h
59
#define PWM_STA_RERR1 __BIT(3)
sys/arch/arm/broadcom/bcm2835_pwm.h
60
#define PWM_STA_WERR1 __BIT(2)
sys/arch/arm/broadcom/bcm2835_pwm.h
61
#define PWM_STA_EMPT1 __BIT(1)
sys/arch/arm/broadcom/bcm2835_pwm.h
62
#define PWM_STA_FULL1 __BIT(0)
sys/arch/arm/broadcom/bcm2835_pwm.h
65
#define PWM_DMAC_ENAB __BIT(31)
sys/arch/arm/broadcom/bcm2835_rng.c
48
#define RNG_CTRL_EN __BIT(0)
sys/arch/arm/broadcom/bcm2835_sdhost.c
54
#define SDCMD_NEW __BIT(15)
sys/arch/arm/broadcom/bcm2835_sdhost.c
55
#define SDCMD_FAIL __BIT(14)
sys/arch/arm/broadcom/bcm2835_sdhost.c
56
#define SDCMD_BUSY __BIT(11)
sys/arch/arm/broadcom/bcm2835_sdhost.c
57
#define SDCMD_NORESP __BIT(10)
sys/arch/arm/broadcom/bcm2835_sdhost.c
58
#define SDCMD_LONGRESP __BIT(9)
sys/arch/arm/broadcom/bcm2835_sdhost.c
59
#define SDCMD_WRITE __BIT(7)
sys/arch/arm/broadcom/bcm2835_sdhost.c
60
#define SDCMD_READ __BIT(6)
sys/arch/arm/broadcom/bcm2835_sdhost.c
71
#define SDHSTS_BUSY __BIT(10)
sys/arch/arm/broadcom/bcm2835_sdhost.c
72
#define SDHSTS_BLOCK __BIT(9)
sys/arch/arm/broadcom/bcm2835_sdhost.c
73
#define SDHSTS_SDIO __BIT(8)
sys/arch/arm/broadcom/bcm2835_sdhost.c
74
#define SDHSTS_REW_TO __BIT(7)
sys/arch/arm/broadcom/bcm2835_sdhost.c
75
#define SDHSTS_CMD_TO __BIT(6)
sys/arch/arm/broadcom/bcm2835_sdhost.c
76
#define SDHSTS_CRC16_E __BIT(5)
sys/arch/arm/broadcom/bcm2835_sdhost.c
77
#define SDHSTS_CRC7_E __BIT(4)
sys/arch/arm/broadcom/bcm2835_sdhost.c
78
#define SDHSTS_FIFO_E __BIT(3)
sys/arch/arm/broadcom/bcm2835_sdhost.c
79
#define SDHSTS_DATA __BIT(0)
sys/arch/arm/broadcom/bcm2835_sdhost.c
81
#define SDVDD_POWER __BIT(0)
sys/arch/arm/broadcom/bcm2835_sdhost.c
86
#define SDHCFG_BUSY_EN __BIT(10)
sys/arch/arm/broadcom/bcm2835_sdhost.c
87
#define SDHCFG_BLOCK_EN __BIT(8)
sys/arch/arm/broadcom/bcm2835_sdhost.c
88
#define SDHCFG_SDIO_EN __BIT(5)
sys/arch/arm/broadcom/bcm2835_sdhost.c
89
#define SDHCFG_DATA_EN __BIT(4)
sys/arch/arm/broadcom/bcm2835_sdhost.c
90
#define SDHCFG_SLOW __BIT(3)
sys/arch/arm/broadcom/bcm2835_sdhost.c
91
#define SDHCFG_WIDE_EXT __BIT(2)
sys/arch/arm/broadcom/bcm2835_sdhost.c
92
#define SDHCFG_WIDE_INT __BIT(1)
sys/arch/arm/broadcom/bcm2835_sdhost.c
93
#define SDHCFG_REL_CMD __BIT(0)
sys/arch/arm/broadcom/bcm2835_spireg.h
34
#define __BIT32(x) ((uint32_t)__BIT(x))
sys/arch/arm/broadcom/bcm2835_tmr.c
54
#define BCM2835_STIMER_M0 __BIT(0)
sys/arch/arm/broadcom/bcm2835_tmr.c
55
#define BCM2835_STIMER_M1 __BIT(1)
sys/arch/arm/broadcom/bcm2835_tmr.c
56
#define BCM2835_STIMER_M2 __BIT(2)
sys/arch/arm/broadcom/bcm2835_tmr.c
57
#define BCM2835_STIMER_M3 __BIT(3)
sys/arch/arm/broadcom/bcm2835_vcaudio.c
395
int perr = (le32toh(msg.u.complete.count) & __BIT(30)) != 0;
sys/arch/arm/broadcom/bcm2838_pcie.c
50
#define PHYS_HI_RELO __BIT(31)
sys/arch/arm/broadcom/bcm2838_pcie.c
51
#define PHYS_HI_PREFETCH __BIT(30)
sys/arch/arm/broadcom/bcm2838_pcie.c
52
#define PHYS_HI_ALIASED __BIT(29)
sys/arch/arm/broadcom/bcm2838_pcie.h
112
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ __BIT(1)
sys/arch/arm/broadcom/bcm2838_pcie.h
113
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ __BIT(27)
sys/arch/arm/broadcom/bcm2838_pcie.h
137
#define PCIE_RGR1_SW_INIT_1_PERST __BIT(0)
sys/arch/arm/broadcom/bcm2838_pcie.h
138
#define PCIE_RGR1_SW_INIT_1_INIT __BIT(1)
sys/arch/arm/broadcom/bcm2838_pcie.h
54
#define PCIE_RC_DL_MDIO_READ __BIT(0)
sys/arch/arm/broadcom/bcm2838_pcie.h
55
#define PCIE_RC_DL_MDIO_DATA_DONE __BIT(31)
sys/arch/arm/broadcom/bcm2838_pcie.h
59
#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN __BIT(12)
sys/arch/arm/broadcom/bcm2838_pcie.h
60
#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE __BIT(13)
sys/arch/arm/broadcom/bcm2838_pcie.h
89
#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB __BIT(2)
sys/arch/arm/broadcom/bcm2838_pcie.h
90
#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST __BIT(0)
sys/arch/arm/broadcom/bcm2838_pcie.h
93
#define PCIE_MISC_PCIE_STATUS_PCIE_PORT __BIT(7)
sys/arch/arm/broadcom/bcm2838_pcie.h
94
#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23 __BIT(6)
sys/arch/arm/broadcom/bcm2838_pcie.h
95
#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE __BIT(5)
sys/arch/arm/broadcom/bcm2838_pcie.h
96
#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP __BIT(4)
sys/arch/arm/broadcom/bcm53xx_mdio.c
115
if (__BIT(phy) & MII_INTERNAL) {
sys/arch/arm/broadcom/bcm53xx_reg.h
1049
#define BCM_NAND_IDM_IO_CONTROL_APB_LE_MODE_BIT __BIT(24)
sys/arch/arm/broadcom/bcm53xx_reg.h
174
#define CAPABILITY_JTAG_PRESENT __BIT(22)
sys/arch/arm/broadcom/bcm53xx_reg.h
179
#define CAPABILITY_BIG_ENDIAN __BIT(2)
sys/arch/arm/broadcom/bcm53xx_reg.h
183
#define CORECTL_UART_CLK_EN __BIT(3)
sys/arch/arm/broadcom/bcm53xx_reg.h
184
#define CORECTL_GPIO_ASYNC_INT_EN __BIT(2)
sys/arch/arm/broadcom/bcm53xx_reg.h
185
#define CORECTL_UART_CLK_OVERRIDE __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
188
#define INTSTATUS_WDRESET __BIT(31) // WO2C
sys/arch/arm/broadcom/bcm53xx_reg.h
189
#define INTSTATUS_UARTINT __BIT(6) // RO
sys/arch/arm/broadcom/bcm53xx_reg.h
190
#define INTSTATUS_GPIOINT __BIT(0) // RO
sys/arch/arm/broadcom/bcm53xx_reg.h
193
#define INTMASK_UARTINT __BIT(6) // 1 = enabled
sys/arch/arm/broadcom/bcm53xx_reg.h
194
#define INTMASK_GPIOINT __BIT(0) // 1 = enabled
sys/arch/arm/broadcom/bcm53xx_reg.h
218
#define CAPABILITY2_GSIO_PRESENT __BIT(1) // SPI exists
sys/arch/arm/broadcom/bcm53xx_reg.h
221
#define GSIOCTL_STARTBUSY __BIT(31)
sys/arch/arm/broadcom/bcm53xx_reg.h
222
#define GSIOCTL_GSIOMODE __BIT(30) // 0 = SPI
sys/arch/arm/broadcom/bcm53xx_reg.h
223
#define GSIOCTL_ERROR __BIT(23)
sys/arch/arm/broadcom/bcm53xx_reg.h
224
#define GSIOCTL_BIGENDIAN __BIT(22)
sys/arch/arm/broadcom/bcm53xx_reg.h
225
#define GSIOCTL_GSIOGO __BIT(21)
sys/arch/arm/broadcom/bcm53xx_reg.h
261
#define SRA_RST __BIT(2)
sys/arch/arm/broadcom/bcm53xx_reg.h
262
#define SRA_WRITE __BIT(1)
sys/arch/arm/broadcom/bcm53xx_reg.h
263
#define SRA_GORDYN __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
273
#define MIIMGT_BYP __BIT(10)
sys/arch/arm/broadcom/bcm53xx_reg.h
274
#define MIIMGT_EXT __BIT(9)
sys/arch/arm/broadcom/bcm53xx_reg.h
275
#define MIIMGT_BSY __BIT(8)
sys/arch/arm/broadcom/bcm53xx_reg.h
276
#define MIIMGT_PRE __BIT(7)
sys/arch/arm/broadcom/bcm53xx_reg.h
302
#define RNG_JCLK_BYP_SRC __BIT(5)
sys/arch/arm/broadcom/bcm53xx_reg.h
303
#define RNG_JCLK_BYP_SEL __BIT(4)
sys/arch/arm/broadcom/bcm53xx_reg.h
304
#define RNG_RBG2X __BIT(1)
sys/arch/arm/broadcom/bcm53xx_reg.h
305
#define RNG_RBGEN __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
313
#define RNG_INT_OFF __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
333
#define CRUCTL_SW_RESET __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
353
#define USB2_CONTROL_PLL_PCIEUSB3_RESET __BIT(1) // inverted 1=normal
sys/arch/arm/broadcom/bcm53xx_reg.h
354
#define USB2_CONTROL_PLL_USB2_RESET __BIT(0) // inverted 1=normal
sys/arch/arm/broadcom/bcm53xx_reg.h
373
#define STRAP_DDR3 __BIT(9)
sys/arch/arm/broadcom/bcm53xx_reg.h
374
#define STRAP_P5_VOLT_15 __BIT(8)
sys/arch/arm/broadcom/bcm53xx_reg.h
376
#define STRAP_PCIE0_MODE __BIT(5)
sys/arch/arm/broadcom/bcm53xx_reg.h
377
#define STRAP_USB3_SEL __BIT(4)
sys/arch/arm/broadcom/bcm53xx_reg.h
378
#define STRAP_EX_EXTCLK __BIT(3)
sys/arch/arm/broadcom/bcm53xx_reg.h
379
#define STRAP_HW_FWDG_EN __BIT(2)
sys/arch/arm/broadcom/bcm53xx_reg.h
380
#define STRAP_LED_SERIAL_MODE __BIT(1)
sys/arch/arm/broadcom/bcm53xx_reg.h
381
#define STRAP_BISR_BYPASS_AUTOLOAD __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
402
#define DMU_CRU_RESET_IPROC __BIT(1)
sys/arch/arm/broadcom/bcm53xx_reg.h
403
#define DMU_CRU_RESET_CMICD __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
420
#define CTL_82_ZQCS_ROTATE __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
424
#define CTL_86_INHIBIT_DRAM_CMD __BIT(16)
sys/arch/arm/broadcom/bcm53xx_reg.h
425
#define CTL_86_DIS_RD_INTRLV __BIT(8)
sys/arch/arm/broadcom/bcm53xx_reg.h
429
#define CTL_87_IN_ORDER_ACCEPT __BIT(24)
sys/arch/arm/broadcom/bcm53xx_reg.h
431
#define CTL_87_REDUC __BIT(8)
sys/arch/arm/broadcom/bcm53xx_reg.h
435
#define PLL_STATUS_LOCK_LOST __BIT(26)
sys/arch/arm/broadcom/bcm53xx_reg.h
437
#define PLL_STATUS_CLOCKING_4X __BIT(13)
sys/arch/arm/broadcom/bcm53xx_reg.h
439
#define PLL_STATUS_LOCK __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
539
#define PCIE_PHYLINKUP __BIT(3)
sys/arch/arm/broadcom/bcm53xx_reg.h
540
#define PCIE_DL_ACTIVE __BIT(2)
sys/arch/arm/broadcom/bcm53xx_reg.h
541
#define PCIE_RX_LOS_TIMEOUT __BIT(1)
sys/arch/arm/broadcom/bcm53xx_reg.h
542
#define PCIE_LINK_IN_L1 __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
545
#define STRAP_PCIE_USER_FOR_CE_GEN1 __BIT(3)
sys/arch/arm/broadcom/bcm53xx_reg.h
546
#define STRAP_PCIE_USER_FOR_CE_1LANE __BIT(2)
sys/arch/arm/broadcom/bcm53xx_reg.h
547
#define STRAP_PCIE_IF_ENABLE __BIT(1)
sys/arch/arm/broadcom/bcm53xx_reg.h
548
#define STRAP_PCIE_USER_RC_MODE __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
561
#define MSI_INTR_EN_EQ_5 __BIT(5)
sys/arch/arm/broadcom/bcm53xx_reg.h
562
#define MSI_INTR_EN_EQ_4 __BIT(4)
sys/arch/arm/broadcom/bcm53xx_reg.h
563
#define MSI_INTR_EN_EQ_3 __BIT(3)
sys/arch/arm/broadcom/bcm53xx_reg.h
564
#define MSI_INTR_EN_EQ_2 __BIT(2)
sys/arch/arm/broadcom/bcm53xx_reg.h
565
#define MSI_INTR_EN_EQ_1 __BIT(1)
sys/arch/arm/broadcom/bcm53xx_reg.h
566
#define MSI_INTR_EN_EQ_0 __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
571
#define EQ_ENABLE __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
577
#define EQ_OVERFLOW __BIT(6)
sys/arch/arm/broadcom/bcm53xx_reg.h
581
#define RC_EN_INTD __BIT(3)
sys/arch/arm/broadcom/bcm53xx_reg.h
582
#define RC_EN_INTC __BIT(2)
sys/arch/arm/broadcom/bcm53xx_reg.h
583
#define RC_EN_INTB __BIT(1)
sys/arch/arm/broadcom/bcm53xx_reg.h
584
#define RC_EN_INTA __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
587
#define RC_INTD __BIT(3)
sys/arch/arm/broadcom/bcm53xx_reg.h
588
#define RC_INTC __BIT(2)
sys/arch/arm/broadcom/bcm53xx_reg.h
589
#define RC_INTB __BIT(1)
sys/arch/arm/broadcom/bcm53xx_reg.h
590
#define RC_INTA __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
593
#define IARR0_ADDR __BIT(31,15)
sys/arch/arm/broadcom/bcm53xx_reg.h
594
#define IARR0_VALID __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
597
#define IARR1_ADDR __BIT(31,20)
sys/arch/arm/broadcom/bcm53xx_reg.h
598
#define IARR1_SIZE __BIT(7,0)
sys/arch/arm/broadcom/bcm53xx_reg.h
601
#define IARR2_ADDR __BIT(31,20)
sys/arch/arm/broadcom/bcm53xx_reg.h
602
#define IARR2_SIZE __BIT(7,0)
sys/arch/arm/broadcom/bcm53xx_reg.h
605
#define INTR_EN_PCIE_ERR_ATTN __BIT(2)
sys/arch/arm/broadcom/bcm53xx_reg.h
606
#define INTR_EN_PAXB_ECC_2B_ATTN __BIT(1)
sys/arch/arm/broadcom/bcm53xx_reg.h
607
#define INTR_EN_PCIE_IN_WAKE_B __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
610
#define PCIE_OVERFLOW_UNDERFLOW_INTR __BIT(10)
sys/arch/arm/broadcom/bcm53xx_reg.h
611
#define PCIE_AXI_MASTER_RRESP_SLV_ERR_INTR __BIT(9)
sys/arch/arm/broadcom/bcm53xx_reg.h
612
#define PCIE_AXI_MASTER_RRESP_DECERR_INTR __BIT(8)
sys/arch/arm/broadcom/bcm53xx_reg.h
613
#define PCIE_ECRC_ERR_INTR __BIT(7)
sys/arch/arm/broadcom/bcm53xx_reg.h
614
#define PCIE_CMPL_TIMEROUT_INTR __BIT(6)
sys/arch/arm/broadcom/bcm53xx_reg.h
615
#define PCIE_ERR_ATTN_INTR __BIT(5)
sys/arch/arm/broadcom/bcm53xx_reg.h
616
#define PCIE_IN_WAKE_B_INTR __BIT(4)
sys/arch/arm/broadcom/bcm53xx_reg.h
617
#define PCIE_REPLAY_BUF_2B_ECC_ERR_INTR __BIT(3)
sys/arch/arm/broadcom/bcm53xx_reg.h
618
#define PCIE_RD_CMPL_BUF_1_2B_ECC_ERR_INTR __BIT(2)
sys/arch/arm/broadcom/bcm53xx_reg.h
619
#define PCIE_RD_CMPL_BUF_0_2B_ECC_ERR_INTR __BIT(1)
sys/arch/arm/broadcom/bcm53xx_reg.h
620
#define PCIE_WR_DATA_BUF_2B_ECC_ERR_INTR __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
635
#define CLK_POLICY_FREQ_PRIVED __BIT(31)
sys/arch/arm/broadcom/bcm53xx_reg.h
646
#define CLK_APB_DIV_PRIVED __BIT(31)
sys/arch/arm/broadcom/bcm53xx_reg.h
650
#define CLK_APB_DIV_TRIGGER_PRIVED __BIT(31)
sys/arch/arm/broadcom/bcm53xx_reg.h
651
#define CLK_APB_DIV_TRIGGER_OVERRIDE __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
703
#define AXCACHE_WA __BIT(3)
sys/arch/arm/broadcom/bcm53xx_reg.h
704
#define AXCACHE_RA __BIT(2)
sys/arch/arm/broadcom/bcm53xx_reg.h
705
#define AXCACHE_C __BIT(1)
sys/arch/arm/broadcom/bcm53xx_reg.h
706
#define AXCACHE_B __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
707
#define IO_CONTROL_DIRECT_UARTCLKSEL __BIT(17)
sys/arch/arm/broadcom/bcm53xx_reg.h
708
#define IO_CONTROL_DIRECT_CLK_250_SEL __BIT(6)
sys/arch/arm/broadcom/bcm53xx_reg.h
709
#define IO_CONTROL_DIRECT_DIRECT_GMII_MODE __BIT(5)
sys/arch/arm/broadcom/bcm53xx_reg.h
710
#define IO_CONTROL_DIRECT_TX_CLK_OUT_INVERT_EN __BIT(4)
sys/arch/arm/broadcom/bcm53xx_reg.h
711
#define IO_CONTROL_DIRECT_DEST_SYNC_MODE_EN __BIT(3)
sys/arch/arm/broadcom/bcm53xx_reg.h
712
#define IO_CONTROL_DIRECT_SOURCE_SYNC_MODE_EN __BIT(2)
sys/arch/arm/broadcom/bcm53xx_reg.h
713
#define IO_CONTROL_DIRECT_CLK_GATING_EN __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
715
#define RESET_CONTROL_RESET __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
734
#define TXDB_FLAG_SF __BIT(31) // Start oF Frame
sys/arch/arm/broadcom/bcm53xx_reg.h
735
#define TXDB_FLAG_EF __BIT(30) // End oF Frame
sys/arch/arm/broadcom/bcm53xx_reg.h
736
#define TXDB_FLAG_IC __BIT(29) // Interrupt on Completion
sys/arch/arm/broadcom/bcm53xx_reg.h
737
#define TXDB_FLAG_ET __BIT(28) // End Of Table
sys/arch/arm/broadcom/bcm53xx_reg.h
745
#define RXDB_FLAG_SF __BIT(31) // Start oF Frame (ignored)
sys/arch/arm/broadcom/bcm53xx_reg.h
746
#define RXDB_FLAG_EF __BIT(30) // End oF Frame (ignored)
sys/arch/arm/broadcom/bcm53xx_reg.h
747
#define RXDB_FLAG_IC __BIT(29) // Interrupt on Completion
sys/arch/arm/broadcom/bcm53xx_reg.h
748
#define RXDB_FLAG_ET __BIT(28) // End Of Table
sys/arch/arm/broadcom/bcm53xx_reg.h
755
#define RXSTS_VLAN_PRESENT __BIT(18)
sys/arch/arm/broadcom/bcm53xx_reg.h
756
#define RXSTS_CRC_ERROR __BIT(19)
sys/arch/arm/broadcom/bcm53xx_reg.h
757
#define RXSTS_OVERSIZED __BIT(20)
sys/arch/arm/broadcom/bcm53xx_reg.h
758
#define RXSTS_CTF_HIT __BIT(21)
sys/arch/arm/broadcom/bcm53xx_reg.h
759
#define RXSTS_CTF_ERROR __BIT(22)
sys/arch/arm/broadcom/bcm53xx_reg.h
760
#define RXSTS_PKT_OVERFLOW __BIT(23)
sys/arch/arm/broadcom/bcm53xx_reg.h
764
#define ENABLE_DEL_G_TXC __BIT(21)
sys/arch/arm/broadcom/bcm53xx_reg.h
765
#define ENABLE_DEL_G_RXC __BIT(20)
sys/arch/arm/broadcom/bcm53xx_reg.h
768
#define TXQ_FLUSH __BIT(8)
sys/arch/arm/broadcom/bcm53xx_reg.h
769
#define NWAY_AUTO_POLL_EN __BIT(7)
sys/arch/arm/broadcom/bcm53xx_reg.h
771
#define MIB_RD_RESET_EN __BIT(4)
sys/arch/arm/broadcom/bcm53xx_reg.h
772
#define RGMII_LINK_STATUS_SEL __BIT(3)
sys/arch/arm/broadcom/bcm53xx_reg.h
773
#define CPU_FLOW_CTRL_ON __BIT(2)
sys/arch/arm/broadcom/bcm53xx_reg.h
774
#define RXQ_OVERFLOW_CTRL_SEL __BIT(1)
sys/arch/arm/broadcom/bcm53xx_reg.h
775
#define TXARB_STRICT_MODE __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
780
#define TXQECCUNCORRECTED __BIT(31)
sys/arch/arm/broadcom/bcm53xx_reg.h
781
#define TXQECCCORRECTED __BIT(30)
sys/arch/arm/broadcom/bcm53xx_reg.h
782
#define RXQECCUNCORRECTED __BIT(29)
sys/arch/arm/broadcom/bcm53xx_reg.h
783
#define RXQECCCORRECTED __BIT(28)
sys/arch/arm/broadcom/bcm53xx_reg.h
784
#define XMTINT_3 __BIT(27)
sys/arch/arm/broadcom/bcm53xx_reg.h
785
#define XMTINT_2 __BIT(26)
sys/arch/arm/broadcom/bcm53xx_reg.h
786
#define XMTINT_1 __BIT(25)
sys/arch/arm/broadcom/bcm53xx_reg.h
787
#define XMTINT_0 __BIT(24)
sys/arch/arm/broadcom/bcm53xx_reg.h
788
#define RCVINT __BIT(16)
sys/arch/arm/broadcom/bcm53xx_reg.h
789
#define XMTUF __BIT(15)
sys/arch/arm/broadcom/bcm53xx_reg.h
790
#define RCVFIFOOF __BIT(14)
sys/arch/arm/broadcom/bcm53xx_reg.h
791
#define RCVDESCUF __BIT(13)
sys/arch/arm/broadcom/bcm53xx_reg.h
792
#define DESCPROTOERR __BIT(12)
sys/arch/arm/broadcom/bcm53xx_reg.h
793
#define DATAERR __BIT(11)
sys/arch/arm/broadcom/bcm53xx_reg.h
794
#define DESCERR __BIT(10)
sys/arch/arm/broadcom/bcm53xx_reg.h
795
#define INT_SW_LINK_ST_CHG __BIT(8)
sys/arch/arm/broadcom/bcm53xx_reg.h
796
#define INT_TIMEOUT __BIT(7)
sys/arch/arm/broadcom/bcm53xx_reg.h
797
#define MIB_TX_INT __BIT(6)
sys/arch/arm/broadcom/bcm53xx_reg.h
798
#define MIB_RX_INT __BIT(5)
sys/arch/arm/broadcom/bcm53xx_reg.h
799
#define MDIOINT __BIT(4)
sys/arch/arm/broadcom/bcm53xx_reg.h
800
#define NWAYLINKSTATINT __BIT(3)
sys/arch/arm/broadcom/bcm53xx_reg.h
801
#define TXQ_FLUSH_DONEINT __BIT(2)
sys/arch/arm/broadcom/bcm53xx_reg.h
802
#define MIB_TX_OVERFLOW __BIT(1)
sys/arch/arm/broadcom/bcm53xx_reg.h
803
#define MIB_RX_OVERFLOW __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
834
#define XMTCTL_DMA_ACT_INDEX __BIT(13)
sys/arch/arm/broadcom/bcm53xx_reg.h
835
#define XMTCTL_PARITY_DIS __BIT(11)
sys/arch/arm/broadcom/bcm53xx_reg.h
837
#define XMTCTL_BURST_ALIGN_EN __BIT(5)
sys/arch/arm/broadcom/bcm53xx_reg.h
838
#define XMTCTL_DMA_LOOPBACK __BIT(2)
sys/arch/arm/broadcom/bcm53xx_reg.h
839
#define XMTCTL_SUSPEND __BIT(1)
sys/arch/arm/broadcom/bcm53xx_reg.h
840
#define XMTCTL_ENABLE __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
861
#define RCVCTL_DMA_ACT_INDEX __BIT(13)
sys/arch/arm/broadcom/bcm53xx_reg.h
862
#define RCVCTL_PARITY_DIS __BIT(11)
sys/arch/arm/broadcom/bcm53xx_reg.h
863
#define RCVCTL_OFLOW_CONTINUE __BIT(10)
sys/arch/arm/broadcom/bcm53xx_reg.h
864
#define RCVCTL_SEPRXHDRDESC __BIT(9)
sys/arch/arm/broadcom/bcm53xx_reg.h
866
#define RCVCTL_ENABLE __BIT(0)
sys/arch/arm/broadcom/bcm53xx_reg.h
887
#define RUNT_FILTER_DIS __BIT(30)
sys/arch/arm/broadcom/bcm53xx_reg.h
888
#define OOB_EFC_EN __BIT(29)
sys/arch/arm/broadcom/bcm53xx_reg.h
889
#define IGNORE_TX_PAUSE __BIT(28)
sys/arch/arm/broadcom/bcm53xx_reg.h
890
#define PRBL_ENA __BIT(27)
sys/arch/arm/broadcom/bcm53xx_reg.h
891
#define RX_ERR_DIS __BIT(26)
sys/arch/arm/broadcom/bcm53xx_reg.h
892
#define LINE_LOOPBACK __BIT(25)
sys/arch/arm/broadcom/bcm53xx_reg.h
893
#define NO_LENGTH_CHECK __BIT(24)
sys/arch/arm/broadcom/bcm53xx_reg.h
894
#define CNTRL_FRM_ENA __BIT(23)
sys/arch/arm/broadcom/bcm53xx_reg.h
895
#define ENA_EXT_CONFIG __BIT(22)
sys/arch/arm/broadcom/bcm53xx_reg.h
896
#define EN_INTERNAL_TX_CRS __BIT(21)
sys/arch/arm/broadcom/bcm53xx_reg.h
897
#define SW_OVERRIDE_RX __BIT(18)
sys/arch/arm/broadcom/bcm53xx_reg.h
898
#define SW_OVERRIDE_TX __BIT(17)
sys/arch/arm/broadcom/bcm53xx_reg.h
899
#define MAC_LOOP_CON __BIT(16)
sys/arch/arm/broadcom/bcm53xx_reg.h
900
#define LOOP_ENA __BIT(15)
sys/arch/arm/broadcom/bcm53xx_reg.h
901
#define RCS_CORRUPT_URUN_EN __BIT(14)
sys/arch/arm/broadcom/bcm53xx_reg.h
902
#define SW_RESET __BIT(13)
sys/arch/arm/broadcom/bcm53xx_reg.h
903
#define OVERFLOW_EN __BIT(12)
sys/arch/arm/broadcom/bcm53xx_reg.h
904
#define RX_LOW_LATENCY_EN __BIT(11)
sys/arch/arm/broadcom/bcm53xx_reg.h
905
#define HD_ENA __BIT(10)
sys/arch/arm/broadcom/bcm53xx_reg.h
906
#define TX_ADDR_INS __BIT(9)
sys/arch/arm/broadcom/bcm53xx_reg.h
907
#define PAUSE_IGNORE __BIT(8)
sys/arch/arm/broadcom/bcm53xx_reg.h
908
#define PAUSE_FWD __BIT(7)
sys/arch/arm/broadcom/bcm53xx_reg.h
909
#define CRC_FWD __BIT(6)
sys/arch/arm/broadcom/bcm53xx_reg.h
910
#define PAD_EN __BIT(5)
sys/arch/arm/broadcom/bcm53xx_reg.h
911
#define PROMISC_EN __BIT(4)
sys/arch/arm/broadcom/bcm53xx_reg.h
917
#define RX_ENA __BIT(1)
sys/arch/arm/broadcom/bcm53xx_reg.h
918
#define TX_ENA __BIT(0)
sys/arch/arm/cortex/a9tmr_reg.h
64
#define TMR_CTL_WDOG_MODE __BIT(3) // WDOG mode
sys/arch/arm/cortex/a9tmr_reg.h
65
#define TMR_CTL_INT_ENABLE __BIT(2) // INT 29/30 is enabled
sys/arch/arm/cortex/a9tmr_reg.h
66
#define TMR_CTL_AUTO_RELOAD __BIT(1)
sys/arch/arm/cortex/a9tmr_reg.h
67
#define TMR_CTL_ENABLE __BIT(0)
sys/arch/arm/cortex/a9tmr_reg.h
69
#define TMR_INT_EVENT __BIT(0) // [W1C] timer reached 0
sys/arch/arm/cortex/a9tmr_reg.h
70
#define TMR_RST_EVENT __BIT(0) // [W1C] wdog timer reached 0
sys/arch/arm/cortex/a9tmr_reg.h
87
#define TMR_GBL_CTL_PRESCALER __BIT(15,8)
sys/arch/arm/cortex/a9tmr_reg.h
88
#define TMR_GBL_CTL_AUTO_INC __BIT(3) // Auto Increment is enabled
sys/arch/arm/cortex/a9tmr_reg.h
89
#define TMR_GBL_CTL_INT_ENABLE __BIT(2) // [banked] INT 27 is enabled
sys/arch/arm/cortex/a9tmr_reg.h
90
#define TMR_GBL_CTL_CMP_ENABLE __BIT(1) // [banked]
sys/arch/arm/cortex/a9tmr_reg.h
91
#define TMR_GBL_CTL_ENABLE __BIT(0)
sys/arch/arm/cortex/gic.c
422
KASSERTMSG(sc->sc_gic_valid_lines[group] & __BIT(irq),
sys/arch/arm/cortex/gic.c
425
(uint32_t)__BIT(irq));
sys/arch/arm/cortex/gic.c
456
if (is->is_type == IST_LEVEL && (old_cfg & __BIT(1)) != 0) {
sys/arch/arm/cortex/gic.c
459
new_cfg |= __BIT(1) << twopair_shift;
sys/arch/arm/cortex/gic_reg.h
143
#define GICD_CTRL_RWP __BIT(31) // GICv3
sys/arch/arm/cortex/gic_reg.h
144
#define GICD_CTRL_E1NWF __BIT(7) // GICv3
sys/arch/arm/cortex/gic_reg.h
145
#define GICD_CTRL_DS __BIT(6) // GICv3
sys/arch/arm/cortex/gic_reg.h
146
#define GICD_CTRL_ARE_NS __BIT(4) // GICv3
sys/arch/arm/cortex/gic_reg.h
147
#define GICD_CTRL_EnableGrp1S __BIT(2) // Secure only
sys/arch/arm/cortex/gic_reg.h
148
#define GICD_CTRL_EnableGrp1A __BIT(1) // GICv3
sys/arch/arm/cortex/gic_reg.h
149
#define GICD_CTRL_Enable __BIT(0)
sys/arch/arm/cortex/gic_reg.h
151
#define GICD_TYPER_No1N __BIT(25) // GICv3
sys/arch/arm/cortex/gic_reg.h
152
#define GICD_TYPER_A3V __BIT(24) // GICv3
sys/arch/arm/cortex/gic_reg.h
154
#define GICD_TYPER_DVIS __BIT(18) // GICv3
sys/arch/arm/cortex/gic_reg.h
155
#define GICD_TYPER_LPIS __BIT(17) // GICv3
sys/arch/arm/cortex/gic_reg.h
156
#define GICD_TYPER_MBIS __BIT(16) // GICv3
sys/arch/arm/cortex/gic_reg.h
158
#define GICD_TYPER_SecurityExtn __BIT(10)
sys/arch/arm/cortex/gic_reg.h
189
#define GICD_SGIR_NSATT __BIT(15)
sys/arch/arm/cortex/gic_reg.h
193
#define GICD_IROUTER_Interrupt_Routing_mode __BIT(31)
sys/arch/arm/cortex/gic_reg.h
223
#define GICR_CTLR_UWP __BIT(31)
sys/arch/arm/cortex/gic_reg.h
224
#define GICR_CTLR_DPG1S __BIT(26)
sys/arch/arm/cortex/gic_reg.h
225
#define GICR_CTLR_DPG1NS __BIT(25)
sys/arch/arm/cortex/gic_reg.h
226
#define GICR_CTLR_DPG0 __BIT(24)
sys/arch/arm/cortex/gic_reg.h
227
#define GICR_CTLR_RWP __BIT(3)
sys/arch/arm/cortex/gic_reg.h
228
#define GICR_CTLR_Enable_LPIs __BIT(0)
sys/arch/arm/cortex/gic_reg.h
237
#define GICR_TYPER_DPGS __BIT(5)
sys/arch/arm/cortex/gic_reg.h
238
#define GICR_TYPER_Last __BIT(4)
sys/arch/arm/cortex/gic_reg.h
239
#define GICR_TYPER_DirectLPI __BIT(3)
sys/arch/arm/cortex/gic_reg.h
240
#define GICR_TYPER_VLPIS __BIT(1)
sys/arch/arm/cortex/gic_reg.h
241
#define GICR_TYPER_PLPIS __BIT(0)
sys/arch/arm/cortex/gic_reg.h
243
#define GICR_WAKER_ChildrenAsleep __BIT(2)
sys/arch/arm/cortex/gic_reg.h
244
#define GICR_WAKER_ProcessorSleep __BIT(1)
sys/arch/arm/cortex/gic_reg.h
252
#define GICR_PENDBASER_PTZ __BIT(62)
sys/arch/arm/cortex/gic_reg.h
278
#define GIC_LPICONF_Res1 __BIT(1)
sys/arch/arm/cortex/gic_reg.h
279
#define GIC_LPICONF_Enable __BIT(0)
sys/arch/arm/cortex/gic_reg.h
334
#define GITS_CTLR_Quiescent __BIT(31)
sys/arch/arm/cortex/gic_reg.h
336
#define GITS_CTLR_ImDe __BIT(1)
sys/arch/arm/cortex/gic_reg.h
337
#define GITS_CTLR_Enabled __BIT(0)
sys/arch/arm/cortex/gic_reg.h
344
#define GITS_TYPER_VMOVP __BIT(37)
sys/arch/arm/cortex/gic_reg.h
345
#define GITS_TYPER_CIL __BIT(36)
sys/arch/arm/cortex/gic_reg.h
348
#define GITS_TYPER_PTA __BIT(19)
sys/arch/arm/cortex/gic_reg.h
349
#define GITS_TYPER_SEIS __BIT(18)
sys/arch/arm/cortex/gic_reg.h
353
#define GITS_TYPER_CCT __BIT(2)
sys/arch/arm/cortex/gic_reg.h
354
#define GITS_TYPER_Virtual __BIT(1)
sys/arch/arm/cortex/gic_reg.h
355
#define GITS_TYPER_Physical __BIT(0)
sys/arch/arm/cortex/gic_reg.h
357
#define GITS_CBASER_Valid __BIT(63)
sys/arch/arm/cortex/gic_reg.h
365
#define GITS_CWRITER_Retry __BIT(0)
sys/arch/arm/cortex/gic_reg.h
368
#define GITS_CREADR_Stalled __BIT(0)
sys/arch/arm/cortex/gic_reg.h
370
#define GITS_BASER_Valid __BIT(63)
sys/arch/arm/cortex/gic_reg.h
371
#define GITS_BASER_Indirect __BIT(62)
sys/arch/arm/cortex/gic_reg.h
72
#define GICC_CTRL_V1_Enable __BIT(0) // GICv1
sys/arch/arm/cortex/gic_reg.h
74
#define GICC_CTRL_V2_EnableGrp0 __BIT(0) // GICv2 !Secure | Secure
sys/arch/arm/cortex/gic_reg.h
75
#define GICC_CTRL_V2_EnableGrp1 __BIT(1) // GICv2 !Secure | Secure
sys/arch/arm/cortex/gic_reg.h
77
#define GICC_CTRL_V2S_EOImodeNS __BIT(9) // GICv2 Secure
sys/arch/arm/cortex/gic_reg.h
78
#define GICC_CTRL_V2S_IRQBypDisGrp1 __BIT(6) // GICv2 Secure
sys/arch/arm/cortex/gic_reg.h
79
#define GICC_CTRL_V2S_FIQBypDisGrp1 __BIT(4) // GICv2 Secure
sys/arch/arm/cortex/gic_reg.h
81
#define GICC_CTRL_V2NS_EOImodeNS __BIT(10) // GICv2 !Secure
sys/arch/arm/cortex/gic_reg.h
82
#define GICC_CTRL_V2NS_EOImodeS __BIT(9) // GICv2 !Secure
sys/arch/arm/cortex/gic_reg.h
83
#define GICC_CTRL_V2NS_IRQBypDisGrp1 __BIT(8) // GICv2 !Secure
sys/arch/arm/cortex/gic_reg.h
84
#define GICC_CTRL_V2NS_FIQBypDisGrp1 __BIT(7) // GICv2 !Secure
sys/arch/arm/cortex/gic_reg.h
85
#define GICC_CTRL_V2NS_IRQBypDisGrp0 __BIT(6) // GICv2 !Secure
sys/arch/arm/cortex/gic_reg.h
86
#define GICC_CTRL_V2NS_FIQBypDisGrp0 __BIT(5) // GICv2 !Secure
sys/arch/arm/cortex/gic_reg.h
87
#define GICC_CTRL_V2NS_CPBR __BIT(4) // GICv2 !Secure
sys/arch/arm/cortex/gic_reg.h
88
#define GICC_CTRL_V2NS_FIQEn __BIT(3) // GICv2 !Secure
sys/arch/arm/cortex/gic_reg.h
89
#define GICC_CTRL_V2NS_AckCtl __BIT(2) // GICv2 !Secure
sys/arch/arm/cortex/gicv3.c
388
return __SHIFTIN(__BIT(aff0), ICC_SGIR_EL1_TargetList) |
sys/arch/arm/cortex/gicv3.c
542
mask &= ~__BIT(bit - 1);
sys/arch/arm/cortex/gicv3.c
559
mask &= ~__BIT(bit - 1);
sys/arch/arm/cortex/gicv3.h
65
#define GICV3_QUIRK_RK3399 __BIT(0) /* Rockchip RK3399 GIC-500 */
sys/arch/arm/cortex/gicv3_its.c
172
cmd.dw[2] |= __BIT(63);
sys/arch/arm/cortex/gicv3_its.c
195
cmd.dw[2] = itt_addr | __BIT(63);
sys/arch/arm/cortex/gicv3_its.c
398
if ((dev->dev_eventid[index] & __BIT(bit)) == 0) {
sys/arch/arm/cortex/gicv3_its.c
421
KASSERT((dev->dev_eventid[index] & __BIT(bit)) == 0);
sys/arch/arm/cortex/gicv3_its.c
422
dev->dev_eventid[index] |= __BIT(bit);
sys/arch/arm/cortex/gicv3_its.c
444
KASSERT((dev->dev_eventid[index] & __BIT(bit)) != 0);
sys/arch/arm/cortex/gicv3_its.c
445
dev->dev_eventid[index] &= ~__BIT(bit);
sys/arch/arm/cortex/gtmr_var.h
41
#define GTMR_FLAG_SUN50I_A64_UNSTABLE_TIMER __BIT(0)
sys/arch/arm/cortex/gtmr_var.h
42
#define GTMR_FLAG_CPU_REGISTERS_NOT_FW_CONFIGURED __BIT(1)
sys/arch/arm/cortex/pl310.c
151
sc->sc_waymask = __BIT(arm_scache.dcache_ways) - 1;
sys/arch/arm/cortex/pl310_reg.h
138
#define PREFETCHCTL_DBLLINEF_EN __BIT(30)
sys/arch/arm/cortex/pl310_reg.h
139
#define PREFETCHCTL_INSTRPREF_EN __BIT(29)
sys/arch/arm/cortex/pl310_reg.h
140
#define PREFETCHCTL_DATAPREF_EN __BIT(28)
sys/arch/arm/cortex/pl310_reg.h
141
#define PREFETCHCTL_DBLLINEF_WRAP_DA __BIT(27)
sys/arch/arm/cortex/pl310_reg.h
142
#define PREFETCHCTL_PREF_DROP_EN __BIT(24)
sys/arch/arm/cortex/pl310_reg.h
143
#define PREFETCHCTL_INCRDBL_LINEF_EN __BIT(23)
sys/arch/arm/cortex/pl310_reg.h
144
#define PREFETCHCTL_NOSAMEID_EXCL_SEQ_EN __BIT(21)
sys/arch/arm/cortex/pl310_reg.h
152
#define POWERCTL_DYNCLKGATE __BIT(1)
sys/arch/arm/cortex/pl310_reg.h
153
#define POWERCTL_STANDBY __BIT(0)
sys/arch/arm/cortex/pl310_reg.h
49
#define CACHE_TYPE_DATA_BANKING __BIT(31)
sys/arch/arm/cortex/pl310_reg.h
51
#define CACHE_TYPE_HARVARD __BIT(24)
sys/arch/arm/cortex/pl310_reg.h
55
#define CACHE_TYPE_xASSOC __BIT(6)
sys/arch/arm/cortex/pl310_reg.h
59
#define CTL_ENABLE __BIT(1)
sys/arch/arm/cortex/pl310_reg.h
61
#define AUXCTL_RSVD31 __BIT(31)
sys/arch/arm/cortex/pl310_reg.h
62
#define AUXCTL_EARLY_BRESP_EN __BIT(30)
sys/arch/arm/cortex/pl310_reg.h
63
#define AUXCTL_I_PREFETCH __BIT(29)
sys/arch/arm/cortex/pl310_reg.h
64
#define AUXCTL_D_PREFETCH __BIT(28)
sys/arch/arm/cortex/pl310_reg.h
65
#define AUXCTL_NS_INT_ACC_CTL __BIT(27)
sys/arch/arm/cortex/pl310_reg.h
66
#define AUXCTL_NS_INT_LOCK_EN __BIT(26)
sys/arch/arm/cortex/pl310_reg.h
67
#define AUXCTL_CACHE_REPL_RR __BIT(25)
sys/arch/arm/cortex/pl310_reg.h
73
#define AUXCTL_SHARED_ATT_OVR __BIT(22)
sys/arch/arm/cortex/pl310_reg.h
74
#define AUXCTL_PARITY_EN __BIT(21)
sys/arch/arm/cortex/pl310_reg.h
75
#define AUXCTL_EVT_MON_BUS_EN __BIT(20)
sys/arch/arm/cortex/pl310_reg.h
85
#define AUXCTL_ASSOCIATIVITY __BIT(16)
sys/arch/arm/cortex/pl310_reg.h
86
#define AUXCTL_SH_ATTR_INV_ENA __BIT(13)
sys/arch/arm/cortex/pl310_reg.h
87
#define AUXCTL_EXCL_CACHE_CFG __BIT(12)
sys/arch/arm/cortex/pl310_reg.h
88
#define AUXCTL_ST_BUF_DEV_LIM_EN __BIT(11)
sys/arch/arm/cortex/pl310_reg.h
89
#define AUXCTL_HIPRO_SO_DEV_EN __BIT(10)
sys/arch/arm/cortex/pl310_reg.h
90
#define AUXCTL_FULL_LINE_WR0 __BIT(0)
sys/arch/arm/cortex/scu_reg.h
53
#define SCU_CTL_IC_STANDBY_ENA __BIT(6)
sys/arch/arm/cortex/scu_reg.h
54
#define SCU_CTL_SCU_STANDBY_ENA __BIT(5)
sys/arch/arm/cortex/scu_reg.h
55
#define SCU_CTL_FORCE_PORT0_ENA __BIT(4)
sys/arch/arm/cortex/scu_reg.h
56
#define SCU_CTL_SPECULATIVE_LINEFILL_ENA __BIT(3)
sys/arch/arm/cortex/scu_reg.h
57
#define SCU_CTL_SCU_RAM_PARITY_ENA __BIT(2)
sys/arch/arm/cortex/scu_reg.h
58
#define SCU_CTL_ADDR_FILTER_ENA __BIT(1)
sys/arch/arm/cortex/scu_reg.h
59
#define SCU_CTL_SCU_ENA __BIT(0)
sys/arch/arm/cortex/scu_reg.h
69
#define SCU_CFG_CPUn_SMP(n) __BIT(4+(n))
sys/arch/arm/cortex/scu_reg.h
70
#define SCU_CFG_CPU3_SMP __BIT(7)
sys/arch/arm/cortex/scu_reg.h
71
#define SCU_CFG_CPU2_SMP __BIT(6)
sys/arch/arm/cortex/scu_reg.h
72
#define SCU_CFG_CPU1_SMP __BIT(5)
sys/arch/arm/cortex/scu_reg.h
73
#define SCU_CFG_CPU0_SMP __BIT(4)
sys/arch/arm/cortex/scu_reg.h
76
#define SCU_DIAG_DISABLE_MIGBIT __BIT(0)
sys/arch/arm/fdt/pcihost_fdtvar.h
30
#define PHYS_HI_RELO __BIT(31)
sys/arch/arm/fdt/pcihost_fdtvar.h
31
#define PHYS_HI_PREFETCH __BIT(30)
sys/arch/arm/fdt/pcihost_fdtvar.h
32
#define PHYS_HI_ALIASED __BIT(29)
sys/arch/arm/fdt/plfb_fdt.c
66
#define LCDCONTROL_PWR __BIT(11)
sys/arch/arm/fdt/plfb_fdt.c
67
#define LCDCONTROL_BGR __BIT(8)
sys/arch/arm/fdt/plfb_fdt.c
70
#define LCDCONTROL_EN __BIT(0)
sys/arch/arm/gemini/gemini_gmac.c
68
#define MDIN __BIT(3)
sys/arch/arm/gemini/gemini_gmac.c
69
#define MDOUT __BIT(2)
sys/arch/arm/gemini/gemini_gmac.c
70
#define MDCLK __BIT(1)
sys/arch/arm/gemini/gemini_gmac.c
71
#define MDTOPHY __BIT(0)
sys/arch/arm/gemini/gemini_gmacreg.h
124
#define INT1_TOE_IQ3_FULL __BIT(31) /* TOE Intr Queue3 Full */
sys/arch/arm/gemini/gemini_gmacreg.h
125
#define INT1_TOE_IQ2_FULL __BIT(30) /* TOE Intr Queue2 Full */
sys/arch/arm/gemini/gemini_gmacreg.h
126
#define INT1_TOE_IQ1_FULL __BIT(29) /* TOE Intr Queue1 Full */
sys/arch/arm/gemini/gemini_gmacreg.h
127
#define INT1_TOE_IQ0_FULL __BIT(28) /* TOE Intr Queue0 Full */
sys/arch/arm/gemini/gemini_gmacreg.h
128
#define INT1_TOE_IQ3_NONEMPTY __BIT(27) /* TOE Intr Queue3 !Empty */
sys/arch/arm/gemini/gemini_gmacreg.h
129
#define INT1_TOE_IQ2_NONEMPTY __BIT(26) /* TOE Intr Queue2 !Empty */
sys/arch/arm/gemini/gemini_gmacreg.h
130
#define INT1_TOE_IQ1_NONEMPTY __BIT(25) /* TOE Intr Queue1 !Empty */
sys/arch/arm/gemini/gemini_gmacreg.h
131
#define INT1_TOE_IQ0_NONEMPTY __BIT(24) /* TOE Intr Queue0 !Empty */
sys/arch/arm/gemini/gemini_gmacreg.h
132
#define INT1_HWTQ13_EOF __BIT(23) /* GMAC1 HW TX Queue3 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
133
#define INT1_HWTQ12_EOF __BIT(22) /* GMAC1 HW TX Queue2 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
134
#define INT1_HWTQ11_EOF __BIT(21) /* GMAC1 HW TX Queue1 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
135
#define INT1_HWTQ10_EOF __BIT(20) /* GMAC1 HW TX Queue0 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
136
#define INT1_HWTQ03_EOF __BIT(19) /* GMAC0 HW TX Queue3 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
137
#define INT1_HWTQ02_EOF __BIT(18) /* GMAC0 HW TX Queue2 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
138
#define INT1_HWTQ01_EOF __BIT(17) /* GMAC0 HW TX Queue1 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
139
#define INT1_HWTQ00_EOF __BIT(16) /* GMAC0 HW TX Queue0 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
140
#define INT1_CLASS_Q_EOF(n) __BIT((n)+2) /* Classfication Q[n] EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
141
#define INT1_DEF_RXQ1_EOF __BIT(1) /* GMAC1 Default RX Queue EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
142
#define INT1_DEF_RXQ0_EOF __BIT(0) /* GMAC0 Default RX Queue EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
161
#define INT2_TOE_QFULL(n) __BIT((n)-32) /* TOE (32-63) Q[n] Full */
sys/arch/arm/gemini/gemini_gmacreg.h
169
#define INT3_TOE_QFULL(n) __BIT((n)) /* TOE (0-31) Q[n] Full */
sys/arch/arm/gemini/gemini_gmacreg.h
177
#define INT4_TX_FAIL0 __BIT(23) /* GMAC0 TX fail */
sys/arch/arm/gemini/gemini_gmacreg.h
178
#define INT4_TX_FAIL1 __BIT(23+8) /* GMAC1 TX fail */
sys/arch/arm/gemini/gemini_gmacreg.h
180
#define INT4_MIB_HEMIWRAP0 __BIT(22) /* GMAC0 MIB counters 1/2 */
sys/arch/arm/gemini/gemini_gmacreg.h
181
#define INT4_MIB_HEMIWRAP1 __BIT(22+8) /* GMAC1 MIB counters 1/2 */
sys/arch/arm/gemini/gemini_gmacreg.h
183
#define INT4_RX_XON0 __BIT(21) /* GMAC0 RX Pause On */
sys/arch/arm/gemini/gemini_gmacreg.h
184
#define INT4_RX_XON1 __BIT(21+8) /* GMAC1 RX Pause On */
sys/arch/arm/gemini/gemini_gmacreg.h
186
#define INT4_TX_XON0 __BIT(20) /* GMAC0 TX Pause On */
sys/arch/arm/gemini/gemini_gmacreg.h
187
#define INT4_TX_XON1 __BIT(20+8) /* GMAC1 TX Pause On */
sys/arch/arm/gemini/gemini_gmacreg.h
189
#define INT4_RX_XOFF0 __BIT(19) /* GMAC0 RX Pause Off */
sys/arch/arm/gemini/gemini_gmacreg.h
190
#define INT4_RX_XOFF1 __BIT(19+8) /* GMAC1 RX Pause Off */
sys/arch/arm/gemini/gemini_gmacreg.h
192
#define INT4_TX_XOFF0 __BIT(18) /* GMAC0 TX Pause Off */
sys/arch/arm/gemini/gemini_gmacreg.h
193
#define INT4_TX_XOFF1 __BIT(18+8) /* GMAC1 TX Pause Off */
sys/arch/arm/gemini/gemini_gmacreg.h
195
#define INT4_RX_FIFO_OVRN0 __BIT(17) /* GMAC0 RX FIFO overrun */
sys/arch/arm/gemini/gemini_gmacreg.h
196
#define INT4_RX_FIFO_OVRN1 __BIT(17+8) /* GMAC1 RX FIFO overrun */
sys/arch/arm/gemini/gemini_gmacreg.h
198
#define INT4_RGMII_STSCHG0 __BIT(16) /* GMAC0 RGMII status change */
sys/arch/arm/gemini/gemini_gmacreg.h
199
#define INT4_RGMII_STSCHG1 __BIT(16+8) /* GMAC1 RGMII status change */
sys/arch/arm/gemini/gemini_gmacreg.h
201
#define INT4_CLASS_Q_FULL(n) __BIT((n)+2) /* Classification Q[n] Full */
sys/arch/arm/gemini/gemini_gmacreg.h
202
#define INT4_HW_FREEQ_EMPTY __BIT(1) /* HW Free Q empty */
sys/arch/arm/gemini/gemini_gmacreg.h
203
#define INT4_SW_FREEQ_EMPTY __BIT(0) /* SW Free Q empty */
sys/arch/arm/gemini/gemini_gmacreg.h
245
#define DMAVR_RXDMA_ENABLE __BIT(31)
sys/arch/arm/gemini/gemini_gmacreg.h
246
#define DMAVR_TXDMA_ENABLE __BIT(30)
sys/arch/arm/gemini/gemini_gmacreg.h
247
#define DMAVR_LOOPBACK __BIT(29)
sys/arch/arm/gemini/gemini_gmacreg.h
248
#define DMAVR_DROP_SMALL_ACK __BIT(28)
sys/arch/arm/gemini/gemini_gmacreg.h
332
#define RXFILTER_PROMISC_ALL __BIT(4)
sys/arch/arm/gemini/gemini_gmacreg.h
333
#define RXFILTER_PROMISC __BIT(3)
sys/arch/arm/gemini/gemini_gmacreg.h
334
#define RXFILTER_BROADCAST __BIT(2)
sys/arch/arm/gemini/gemini_gmacreg.h
335
#define RXFILTER_MULTICAST __BIT(1)
sys/arch/arm/gemini/gemini_gmacreg.h
336
#define RXFILTER_UNICAST __BIT(0)
sys/arch/arm/gemini/gemini_gmacreg.h
343
#define CONFIG0_PORT1_CLASSIFY_QCHECK_EN __BIT(29)
sys/arch/arm/gemini/gemini_gmacreg.h
344
#define CONFIG0_PORT0_CLASSIFY_QCHECK_EN __BIT(28)
sys/arch/arm/gemini/gemini_gmacreg.h
345
#define CONFIG0_PORT1_TOE_ALMOSTFULL_EN __BIT(27)
sys/arch/arm/gemini/gemini_gmacreg.h
346
#define CONFIG0_PORT0_TOE_ALMOSTFULL_EN __BIT(26)
sys/arch/arm/gemini/gemini_gmacreg.h
347
#define CONFIG0_PORT1_RX_HW_QCHECK_EN __BIT(25)
sys/arch/arm/gemini/gemini_gmacreg.h
348
#define CONFIG0_PORT0_RX_HW_QCHECK_EN __BIT(24)
sys/arch/arm/gemini/gemini_gmacreg.h
349
#define CONFIG0_RX_ER_DETECTING_INDEX_DIS __BIT(23)
sys/arch/arm/gemini/gemini_gmacreg.h
350
#define CONFIG0_IPV6_STRICT_ORDER __BIT(22)
sys/arch/arm/gemini/gemini_gmacreg.h
351
#define CONFIG0_INVERSE_RXC_RGMII __BIT(21)
sys/arch/arm/gemini/gemini_gmacreg.h
352
#define CONFIG0_R_LATCHED_MMII __BIT(20)
sys/arch/arm/gemini/gemini_gmacreg.h
353
#define CONFIG0_VLAN_TAG_REMOVAL __BIT(19)
sys/arch/arm/gemini/gemini_gmacreg.h
354
#define CONFIG0_IPV6_RX_CHECKSUM_ENABLE __BIT(18)
sys/arch/arm/gemini/gemini_gmacreg.h
355
#define CONFIG0_IPV4_RX_CHECKSUM_ENABLE __BIT(17)
sys/arch/arm/gemini/gemini_gmacreg.h
356
#define CONFIG0_RGMII_INBAND_STATUS_ENABLE __BIT(16)
sys/arch/arm/gemini/gemini_gmacreg.h
357
#define CONFIG0_TX_FLOWCTL_ENABLE __BIT(15)
sys/arch/arm/gemini/gemini_gmacreg.h
358
#define CONFIG0_RX_FLOWCTL_ENABLE __BIT(14)
sys/arch/arm/gemini/gemini_gmacreg.h
359
#define CONFIG0_SIM_TEST __BIT(13)
sys/arch/arm/gemini/gemini_gmacreg.h
378
#define CONFIG0_DROP_16COLL_ENABLE __BIT(3)
sys/arch/arm/gemini/gemini_gmacreg.h
379
#define CONFIG0_LOOPBACK __BIT(2)
sys/arch/arm/gemini/gemini_gmacreg.h
380
#define CONFIG0_RX_DISABLE __BIT(1)
sys/arch/arm/gemini/gemini_gmacreg.h
381
#define CONFIG0_TX_DISABLE __BIT(0)
sys/arch/arm/gemini/gemini_gmacreg.h
389
#define STATUS_DUPLEX_FULL __BIT(3)
sys/arch/arm/gemini/gemini_gmacreg.h
394
#define STATUS_LINK_ON __BIT(0)
sys/arch/arm/gemini/gemini_gmacreg.h
396
#define DESC0_DROP __BIT(31)
sys/arch/arm/gemini/gemini_gmacreg.h
397
#define DESC0_DERR __BIT(30)
sys/arch/arm/gemini/gemini_gmacreg.h
398
#define DESC0_PERR __BIT(29)
sys/arch/arm/gemini/gemini_gmacreg.h
427
#define DESC0_TXSTS_OK __BIT(22) /* TX successful */
sys/arch/arm/gemini/gemini_gmacreg.h
443
#define DESC3_SOF __BIT(31)
sys/arch/arm/gemini/gemini_gmacreg.h
444
#define DESC3_EOF __BIT(30)
sys/arch/arm/gemini/gemini_gmacreg.h
445
#define DESC3_EOFIE __BIT(29)
sys/arch/arm/gemini/gemini_gmacreg.h
447
#define DESC3_RX_CTL __BIT(28)
sys/arch/arm/gemini/gemini_gmacreg.h
448
#define DESC3_RX_OSQ __BIT(27)
sys/arch/arm/gemini/gemini_gmacreg.h
449
#define DESC3_RX_OPT __BIT(26)
sys/arch/arm/gemini/gemini_gmacreg.h
450
#define DESC3_RX_ABN __BIT(25)
sys/arch/arm/gemini/gemini_gmacreg.h
451
#define DESC3_RX_DACK __BIT(24)
sys/arch/arm/gemini/gemini_gmacreg.h
56
#define INT0_TXDERR1 __BIT(31) /* GMAC1 AHB bus err while TX */
sys/arch/arm/gemini/gemini_gmacreg.h
57
#define INT0_TXPERR1 __BIT(30) /* GMAC1 TX descriptor error */
sys/arch/arm/gemini/gemini_gmacreg.h
58
#define INT0_TXDERR0 __BIT(29) /* GMAC0 AHB bus err while TX */
sys/arch/arm/gemini/gemini_gmacreg.h
59
#define INT0_TXPERR0 __BIT(28) /* GMAC0 TX descriptor error */
sys/arch/arm/gemini/gemini_gmacreg.h
60
#define INT0_RXDERR1 __BIT(27) /* GMAC1 AHB bus err while RX */
sys/arch/arm/gemini/gemini_gmacreg.h
61
#define INT0_RXPERR1 __BIT(26) /* GMAC1 RX descriptor error */
sys/arch/arm/gemini/gemini_gmacreg.h
62
#define INT0_RXDERR0 __BIT(25) /* GMAC0 AHB bus err while RX */
sys/arch/arm/gemini/gemini_gmacreg.h
63
#define INT0_RXPERR0 __BIT(24) /* GMAC0 RX descriptor error */
sys/arch/arm/gemini/gemini_gmacreg.h
64
#define INT0_SWTXQ15_FIN __BIT(23) /* GMAC1 SW TX queue 5 finish */
sys/arch/arm/gemini/gemini_gmacreg.h
65
#define INT0_SWTXQ14_FIN __BIT(22) /* GMAC1 SW TX queue 4 finish */
sys/arch/arm/gemini/gemini_gmacreg.h
66
#define INT0_SWTXQ13_FIN __BIT(21) /* GMAC1 SW TX queue 3 finish */
sys/arch/arm/gemini/gemini_gmacreg.h
67
#define INT0_SWTXQ12_FIN __BIT(20) /* GMAC1 SW TX queue 2 finish */
sys/arch/arm/gemini/gemini_gmacreg.h
68
#define INT0_SWTXQ11_FIN __BIT(19) /* GMAC1 SW TX queue 1 finish */
sys/arch/arm/gemini/gemini_gmacreg.h
69
#define INT0_SWTXQ10_FIN __BIT(18) /* GMAC1 SW TX queue 0 finish */
sys/arch/arm/gemini/gemini_gmacreg.h
70
#define INT0_SWTXQ1n_FIN(n) __BIT(18 + n)
sys/arch/arm/gemini/gemini_gmacreg.h
72
#define INT0_SWTXQ05_FIN __BIT(17) /* GMAC0 SW TX queue 5 finish */
sys/arch/arm/gemini/gemini_gmacreg.h
73
#define INT0_SWTXQ04_FIN __BIT(16) /* GMAC0 SW TX queue 4 finish */
sys/arch/arm/gemini/gemini_gmacreg.h
74
#define INT0_SWTXQ03_FIN __BIT(15) /* GMAC0 SW TX queue 3 finish */
sys/arch/arm/gemini/gemini_gmacreg.h
75
#define INT0_SWTXQ02_FIN __BIT(14) /* GMAC0 SW TX queue 2 finish */
sys/arch/arm/gemini/gemini_gmacreg.h
76
#define INT0_SWTXQ01_FIN __BIT(13) /* GMAC0 SW TX queue 1 finish */
sys/arch/arm/gemini/gemini_gmacreg.h
77
#define INT0_SWTXQ00_FIN __BIT(12) /* GMAC0 SW TX queue 0 finish */
sys/arch/arm/gemini/gemini_gmacreg.h
78
#define INT0_SWTXQ0n_FIN(n) __BIT(12 + n)
sys/arch/arm/gemini/gemini_gmacreg.h
81
#define INT0_SWTXQ15_EOF __BIT(11) /* GMAC1 SW TX queue 5 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
82
#define INT0_SWTXQ14_EOF __BIT(10) /* GMAC1 SW TX queue 4 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
83
#define INT0_SWTXQ13_EOF __BIT( 9) /* GMAC1 SW TX queue 3 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
84
#define INT0_SWTXQ12_EOF __BIT( 8) /* GMAC1 SW TX queue 2 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
85
#define INT0_SWTXQ11_EOF __BIT( 7) /* GMAC1 SW TX queue 1 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
86
#define INT0_SWTXQ10_EOF __BIT( 6) /* GMAC1 SW TX queue 0 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
87
#define INT0_SWTXQ1n_EOF(n) __BIT( 6 + n)
sys/arch/arm/gemini/gemini_gmacreg.h
89
#define INT0_SWTXQ05_EOF __BIT( 5) /* GMAC0 SW TX queue 5 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
90
#define INT0_SWTXQ04_EOF __BIT( 4) /* GMAC0 SW TX queue 4 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
91
#define INT0_SWTXQ03_EOF __BIT( 3) /* GMAC0 SW TX queue 3 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
92
#define INT0_SWTXQ02_EOF __BIT( 2) /* GMAC0 SW TX queue 2 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
93
#define INT0_SWTXQ01_EOF __BIT( 1) /* GMAC0 SW TX queue 1 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
94
#define INT0_SWTXQ00_EOF __BIT( 0) /* GMAC0 SW TX queue 0 EOF */
sys/arch/arm/gemini/gemini_gmacreg.h
95
#define INT0_SWTXQ0n_EOF(n) __BIT( n)
sys/arch/arm/gemini/gemini_gpio.c
168
uint32_t irq_mask = __BIT(is->is_irq);
sys/arch/arm/gemini/gemini_icu.c
175
const uint32_t oldipl_mask = __BIT(oldipl);
sys/arch/arm/gemini/gemini_icu.c
195
const uint32_t irq_mask = __BIT(is->is_irq);
sys/arch/arm/gemini/gemini_lpc.c
19
# define CFGCTL_WAITKEY __BIT(1)
sys/arch/arm/gemini/gemini_reg.h
100
#define WDT_WDCR_INTR_ENB __BIT(2) /* Timer System Interrupt Enable */
sys/arch/arm/gemini/gemini_reg.h
101
#define WDT_WDCR_RESET_ENB __BIT(1) /* Timer System Reset Enable */
sys/arch/arm/gemini/gemini_reg.h
102
#define WDT_WDCR_ENB __BIT(0) /* Timer Enable */
sys/arch/arm/gemini/gemini_reg.h
105
#define WDT_WDSTATUS_ZERO __BIT(0) /* non-zero if timer counted down to zero! */
sys/arch/arm/gemini/gemini_reg.h
108
#define WDT_WDCLEAR_CLEAR __BIT(0) /* write this bit to clear Status */
sys/arch/arm/gemini/gemini_reg.h
129
#define TIMER_TMCR_TMnUPDOWN(n) __BIT(9 + (n) - 1)
sys/arch/arm/gemini/gemini_reg.h
130
#define TIMER_TMCR_TMnOFENABLE(n) __BIT((((n) - 1) * 3) + 2)
sys/arch/arm/gemini/gemini_reg.h
131
#define TIMER_TMCR_TMnCLOCK(n) __BIT((((n) - 1) * 3) + 1)
sys/arch/arm/gemini/gemini_reg.h
132
#define TIMER_TMCR_TMnENABLE(n) __BIT((((n) - 1) * 3) + 0)
sys/arch/arm/gemini/gemini_reg.h
140
#define TIMER_INTRSTATE_TMnOVFLOW(n) __BIT((((n) -1) * 3) + 2)
sys/arch/arm/gemini/gemini_reg.h
141
#define TIMER_INTRSTATE_TMnMATCH2(n) __BIT((((n) -1) * 3) + 1)
sys/arch/arm/gemini/gemini_reg.h
142
#define TIMER_INTRSTATE_TMnMATCH1(n) __BIT((((n) -1) * 3) + 0)
sys/arch/arm/gemini/gemini_reg.h
145
#define TIMER_INTRMASK_TMnOVFLOW(n) __BIT((((n) -1) * 3) + 2)
sys/arch/arm/gemini/gemini_reg.h
146
#define TIMER_INTRMASK_TMnMATCH2(n) __BIT((((n) -1) * 3) + 1)
sys/arch/arm/gemini/gemini_reg.h
147
#define TIMER_INTRMASK_TMnMATCH1(n) __BIT((((n) -1) * 3) + 0)
sys/arch/arm/gemini/gemini_reg.h
193
# define LPCHC_CSR_STO __BIT(23) /* Sync Time Out */
sys/arch/arm/gemini/gemini_reg.h
194
# define LPCHC_CSR_SERR __BIT(22) /* Sync Error */
sys/arch/arm/gemini/gemini_reg.h
196
# define LPCHC_CSR_STOE __BIT(7) /* Sync Time Out Enable */
sys/arch/arm/gemini/gemini_reg.h
197
# define LPCHC_CSR_SERRE __BIT(6) /* Sync Error Enable */
sys/arch/arm/gemini/gemini_reg.h
199
# define LPCHC_CSR_BEN __BIT(0) /* Bridge Enable */
sys/arch/arm/gemini/gemini_reg.h
202
# define LPCHC_IRQCTL_SIRQEN __BIT(7) /* Serial IRQ Enable */
sys/arch/arm/gemini/gemini_reg.h
203
# define LPCHC_IRQCTL_SIRQMS __BIT(6) /* Serial IRQ Mode Select */
sys/arch/arm/gemini/gemini_reg.h
271
#define PCI_CFG_CMD_ENB __BIT(31) /* Enable */
sys/arch/arm/gemini/gemini_reg.h
294
#define CFG_REG_CTL2_INTSTS_INTD __BIT(28 + 3)
sys/arch/arm/gemini/gemini_reg.h
295
#define CFG_REG_CTL2_INTSTS_INTC __BIT(28 + 2)
sys/arch/arm/gemini/gemini_reg.h
296
#define CFG_REG_CTL2_INTSTS_INTB __BIT(28 + 1)
sys/arch/arm/gemini/gemini_reg.h
297
#define CFG_REG_CTL2_INTSTS_INTA __BIT(28 + 0)
sys/arch/arm/gemini/gemini_reg.h
299
#define CFG_REG_CTL2_INTMASK_CMDERR __BIT(16 + 11)
sys/arch/arm/gemini/gemini_reg.h
300
#define CFG_REG_CTL2_INTMASK_PARERR __BIT(16 + 10)
sys/arch/arm/gemini/gemini_reg.h
301
#define CFG_REG_CTL2_INTMASK_INTD __BIT(16 + 9)
sys/arch/arm/gemini/gemini_reg.h
302
#define CFG_REG_CTL2_INTMASK_INTC __BIT(16 + 8)
sys/arch/arm/gemini/gemini_reg.h
303
#define CFG_REG_CTL2_INTMASK_INTB __BIT(16 + 7)
sys/arch/arm/gemini/gemini_reg.h
304
#define CFG_REG_CTL2_INTMASK_INTA __BIT(16 + 6)
sys/arch/arm/gemini/gemini_reg.h
306
#define CFG_REG_CTL2_INTMASK_MABRT_RX __BIT(16 + 5)
sys/arch/arm/gemini/gemini_reg.h
307
#define CFG_REG_CTL2_INTMASK_TABRT_RX __BIT(16 + 4)
sys/arch/arm/gemini/gemini_reg.h
308
#define CFG_REG_CTL2_INTMASK_TABRT_TX __BIT(16 + 3)
sys/arch/arm/gemini/gemini_reg.h
309
#define CFG_REG_CTL2_INTMASK_RETRY4 __BIT(16 + 2)
sys/arch/arm/gemini/gemini_reg.h
310
#define CFG_REG_CTL2_INTMASK_SERR_RX __BIT(16 + 1)
sys/arch/arm/gemini/gemini_reg.h
311
#define CFG_REG_CTL2_INTMASK_PERR_RX __BIT(16 + 0)
sys/arch/arm/gemini/gemini_reg.h
312
#define PCI_CFG_REG_CTL2_RESa __BIT(15)
sys/arch/arm/gemini/gemini_reg.h
314
#define CFG_REG_CTL2_MSTPRI_REQn(n) __BIT(8 + (n))
sys/arch/arm/gemini/gemini_reg.h
74
#define GLOBAL_RESET_GLOBAL __BIT(31) /* Global Soft Reset */
sys/arch/arm/gemini/gemini_reg.h
75
#define GLOBAL_RESET_CPU1 __BIT(30) /* CPU#1 reset hold */
sys/arch/arm/gemini/gemini_reg.h
76
#define GLOBAL_RESET_GMAC1 __BIT(6) /* GMAC1 reset hold */
sys/arch/arm/gemini/gemini_reg.h
77
#define GLOBAL_RESET_GMAC0 __BIT(5) /* CGMAC reset hold */
sys/arch/arm/gemini/gemini_reg.h
80
#define GLOBAL_CPU0_IPICPU1 __BIT(31) /* IPI to CPU#1 */
sys/arch/arm/gemini/gemini_reg.h
82
#define GLOBAL_CPU1_IPICPU0 __BIT(31) /* IPI to CPU#0 */
sys/arch/arm/gemini/gemini_reg.h
96
#define WDT_WDCR_CLKSRC __BIT(4) /* Timer Clock Source: 5 MHz clock */
sys/arch/arm/gemini/gemini_reg.h
99
#define WDT_WDCR_EXTSIG_ENB __BIT(3) /* Timer External Signal Enable */
sys/arch/arm/imx/if_enet.c
745
gaddr[__SHIFTOUT(crc, __BIT(31))] |= __BIT(hashidx);
sys/arch/arm/imx/if_enetreg.h
101
# define ENET_MIBC_MIB_DIS __BIT(31)
sys/arch/arm/imx/if_enetreg.h
102
# define ENET_MIBC_MIB_IDLE __BIT(30)
sys/arch/arm/imx/if_enetreg.h
103
# define ENET_MIBC_MIB_CLEAR __BIT(29)
sys/arch/arm/imx/if_enetreg.h
106
# define ENET_RCR_GRS __BIT(31)
sys/arch/arm/imx/if_enetreg.h
107
# define ENET_RCR_NLC __BIT(30)
sys/arch/arm/imx/if_enetreg.h
109
# define ENET_RCR_CFEN __BIT(15)
sys/arch/arm/imx/if_enetreg.h
110
# define ENET_RCR_CRCFWD __BIT(14)
sys/arch/arm/imx/if_enetreg.h
111
# define ENET_RCR_PAUFWD __BIT(13)
sys/arch/arm/imx/if_enetreg.h
112
# define ENET_RCR_PADEN __BIT(12)
sys/arch/arm/imx/if_enetreg.h
113
# define ENET_RCR_RMII_10T __BIT(9)
sys/arch/arm/imx/if_enetreg.h
114
# define ENET_RCR_RMII_MODE __BIT(8)
sys/arch/arm/imx/if_enetreg.h
115
# define ENET_RCR_RGMII_EN __BIT(6)
sys/arch/arm/imx/if_enetreg.h
116
# define ENET_RCR_FCE __BIT(5)
sys/arch/arm/imx/if_enetreg.h
117
# define ENET_RCR_BC_REJ __BIT(4)
sys/arch/arm/imx/if_enetreg.h
118
# define ENET_RCR_PROM __BIT(3)
sys/arch/arm/imx/if_enetreg.h
119
# define ENET_RCR_MII_MODE __BIT(2)
sys/arch/arm/imx/if_enetreg.h
120
# define ENET_RCR_DRT __BIT(1)
sys/arch/arm/imx/if_enetreg.h
121
# define ENET_RCR_LOOP __BIT(0)
sys/arch/arm/imx/if_enetreg.h
124
# define ENET_TCR_FDEN __BIT(2)
sys/arch/arm/imx/if_enetreg.h
142
# define ENET_TFWR_STRFWD __BIT(8)
sys/arch/arm/imx/if_enetreg.h
165
# define ENET_TACC_PROCHK __BIT(4)
sys/arch/arm/imx/if_enetreg.h
166
# define ENET_TACC_IPCHK __BIT(3)
sys/arch/arm/imx/if_enetreg.h
167
# define ENET_TACC_SHIFT16 __BIT(0)
sys/arch/arm/imx/if_enetreg.h
169
# define ENET_RACC_SHIFT16 __BIT(7)
sys/arch/arm/imx/if_enetreg.h
170
# define ENET_RACC_LINEDIS __BIT(6)
sys/arch/arm/imx/if_enetreg.h
171
# define ENET_RACC_PRODIS __BIT(2)
sys/arch/arm/imx/if_enetreg.h
172
# define ENET_RACC_IPDIS __BIT(1)
sys/arch/arm/imx/if_enetreg.h
173
# define ENET_RACC_PADREM __BIT(0)
sys/arch/arm/imx/if_enetreg.h
266
#define TXFLAGS1_R __BIT(31) /* Ready */
sys/arch/arm/imx/if_enetreg.h
267
#define TXFLAGS1_T1 __BIT(30) /* TX software owner1 */
sys/arch/arm/imx/if_enetreg.h
268
#define TXFLAGS1_W __BIT(29) /* Wrap */
sys/arch/arm/imx/if_enetreg.h
269
#define TXFLAGS1_T2 __BIT(28) /* TX software owner2 */
sys/arch/arm/imx/if_enetreg.h
270
#define TXFLAGS1_L __BIT(27) /* Last in frame */
sys/arch/arm/imx/if_enetreg.h
271
#define TXFLAGS1_TC __BIT(26) /* Transmit CRC */
sys/arch/arm/imx/if_enetreg.h
272
#define TXFLAGS1_ABC __BIT(25) /* Append bad CRC */
sys/arch/arm/imx/if_enetreg.h
276
#define TXFLAGS2_INT __BIT(30) /* Interrupt */
sys/arch/arm/imx/if_enetreg.h
277
#define TXFLAGS2_TS __BIT(29) /* Timestamp */
sys/arch/arm/imx/if_enetreg.h
278
#define TXFLAGS2_PINS __BIT(28) /* Insert Proto csum */
sys/arch/arm/imx/if_enetreg.h
279
#define TXFLAGS2_IINS __BIT(27) /* Insert IP csum */
sys/arch/arm/imx/if_enetreg.h
280
#define TXFLAGS2_TXE __BIT(15) /* Transmit error */
sys/arch/arm/imx/if_enetreg.h
281
#define TXFLAGS2_UE __BIT(13) /* Underflow error */
sys/arch/arm/imx/if_enetreg.h
282
#define TXFLAGS2_EE __BIT(12) /* Excess colls Err */
sys/arch/arm/imx/if_enetreg.h
283
#define TXFLAGS2_FE __BIT(11) /* Frame Error */
sys/arch/arm/imx/if_enetreg.h
284
#define TXFLAGS2_LCE __BIT(10) /* Late collision Err */
sys/arch/arm/imx/if_enetreg.h
285
#define TXFLAGS2_OE __BIT(9) /* Overflow Error */
sys/arch/arm/imx/if_enetreg.h
286
#define TXFLAGS2_TSE __BIT(8) /* Timestamp Error */
sys/arch/arm/imx/if_enetreg.h
289
#define TXFLAGS3_BDU __BIT(31)
sys/arch/arm/imx/if_enetreg.h
298
#define RXFLAGS1_E __BIT(31) /* Empty */
sys/arch/arm/imx/if_enetreg.h
299
#define RXFLAGS1_R1 __BIT(30) /* RX software owner1 */
sys/arch/arm/imx/if_enetreg.h
300
#define RXFLAGS1_W __BIT(29) /* Wrap */
sys/arch/arm/imx/if_enetreg.h
301
#define RXFLAGS1_R2 __BIT(28) /* RX software owner2 */
sys/arch/arm/imx/if_enetreg.h
302
#define RXFLAGS1_L __BIT(27) /* Last in frame */
sys/arch/arm/imx/if_enetreg.h
303
#define RXFLAGS1_M __BIT(24) /* Miss */
sys/arch/arm/imx/if_enetreg.h
304
#define RXFLAGS1_BC __BIT(23) /* Broadcast */
sys/arch/arm/imx/if_enetreg.h
305
#define RXFLAGS1_MC __BIT(22) /* Multicast */
sys/arch/arm/imx/if_enetreg.h
306
#define RXFLAGS1_LG __BIT(21) /* Length Violation */
sys/arch/arm/imx/if_enetreg.h
307
#define RXFLAGS1_NO __BIT(20) /* Non-Octet aligned */
sys/arch/arm/imx/if_enetreg.h
308
#define RXFLAGS1_CR __BIT(18) /* CRC or frame error */
sys/arch/arm/imx/if_enetreg.h
309
#define RXFLAGS1_OV __BIT(17) /* Overrun */
sys/arch/arm/imx/if_enetreg.h
310
#define RXFLAGS1_TR __BIT(16) /* Truncated */
sys/arch/arm/imx/if_enetreg.h
314
#define RXFLAGS2_ME __BIT(31) /* MAC error */
sys/arch/arm/imx/if_enetreg.h
315
#define RXFLAGS2_PE __BIT(26) /* PHY error */
sys/arch/arm/imx/if_enetreg.h
316
#define RXFLAGS2_CE __BIT(25) /* Collision */
sys/arch/arm/imx/if_enetreg.h
317
#define RXFLAGS2_UC __BIT(24) /* Unicast */
sys/arch/arm/imx/if_enetreg.h
318
#define RXFLAGS2_INT __BIT(23) /* RXB/RXF interrupt */
sys/arch/arm/imx/if_enetreg.h
320
#define RXFLAGS2_ICE __BIT(5) /* IP csum error */
sys/arch/arm/imx/if_enetreg.h
321
#define RXFLAGS2_PCR __BIT(4) /* Proto csum error */
sys/arch/arm/imx/if_enetreg.h
322
#define RXFLAGS2_VLAN __BIT(2) /* VLAN */
sys/arch/arm/imx/if_enetreg.h
323
#define RXFLAGS2_IPV6 __BIT(1) /* IPv6 frame */
sys/arch/arm/imx/if_enetreg.h
324
#define RXFLAGS2_FRAG __BIT(0) /* IPv4 fragment */
sys/arch/arm/imx/if_enetreg.h
335
#define RXFLAGS3_BDU __BIT(31)
sys/arch/arm/imx/if_enetreg.h
39
# define ENET_EIR_BABR __BIT(30)
sys/arch/arm/imx/if_enetreg.h
40
# define ENET_EIR_BABT __BIT(29)
sys/arch/arm/imx/if_enetreg.h
41
# define ENET_EIR_GRA __BIT(28)
sys/arch/arm/imx/if_enetreg.h
42
# define ENET_EIR_TXF __BIT(27)
sys/arch/arm/imx/if_enetreg.h
43
# define ENET_EIR_TXB __BIT(26)
sys/arch/arm/imx/if_enetreg.h
44
# define ENET_EIR_RXF __BIT(25)
sys/arch/arm/imx/if_enetreg.h
45
# define ENET_EIR_RXB __BIT(24)
sys/arch/arm/imx/if_enetreg.h
46
# define ENET_EIR_MII __BIT(23)
sys/arch/arm/imx/if_enetreg.h
47
# define ENET_EIR_EBERR __BIT(22)
sys/arch/arm/imx/if_enetreg.h
48
# define ENET_EIR_LC __BIT(21)
sys/arch/arm/imx/if_enetreg.h
49
# define ENET_EIR_RL __BIT(20)
sys/arch/arm/imx/if_enetreg.h
50
# define ENET_EIR_UN __BIT(19)
sys/arch/arm/imx/if_enetreg.h
51
# define ENET_EIR_PLR __BIT(18)
sys/arch/arm/imx/if_enetreg.h
52
# define ENET_EIR_WAKEUP __BIT(17)
sys/arch/arm/imx/if_enetreg.h
53
# define ENET_EIR_TS_AVAIL __BIT(16)
sys/arch/arm/imx/if_enetreg.h
54
# define ENET_EIR_TS_TIMER __BIT(15)
sys/arch/arm/imx/if_enetreg.h
55
# define ENET_EIR_RXFLUSH_2 __BIT(14) /* imx7 */
sys/arch/arm/imx/if_enetreg.h
56
# define ENET_EIR_RXFLUSH_1 __BIT(13) /* imx7 */
sys/arch/arm/imx/if_enetreg.h
57
# define ENET_EIR_RXFLUSH_0 __BIT(12) /* imx7 */
sys/arch/arm/imx/if_enetreg.h
58
# define ENET_EIR_TXF2 __BIT(7) /* imx7 */
sys/arch/arm/imx/if_enetreg.h
59
# define ENET_EIR_TXB2 __BIT(6) /* imx7 */
sys/arch/arm/imx/if_enetreg.h
60
# define ENET_EIR_RXF2 __BIT(5) /* imx7 */
sys/arch/arm/imx/if_enetreg.h
61
# define ENET_EIR_RXB2 __BIT(4) /* imx7 */
sys/arch/arm/imx/if_enetreg.h
62
# define ENET_EIR_TXF1 __BIT(3) /* imx7 */
sys/arch/arm/imx/if_enetreg.h
63
# define ENET_EIR_TXB1 __BIT(2) /* imx7 */
sys/arch/arm/imx/if_enetreg.h
64
# define ENET_EIR_RXF1 __BIT(1) /* imx7 */
sys/arch/arm/imx/if_enetreg.h
65
# define ENET_EIR_RXB1 __BIT(1) /* imx7 */
sys/arch/arm/imx/if_enetreg.h
68
# define ENET_RDAR_ACTIVE __BIT(24)
sys/arch/arm/imx/if_enetreg.h
70
# define ENET_TDAR_ACTIVE __BIT(24)
sys/arch/arm/imx/if_enetreg.h
73
# define ENET_ECR_SVLANDBL __BIT(11) /* imx7 */
sys/arch/arm/imx/if_enetreg.h
74
# define ENET_ECR_VLANUE2ND __BIT(10) /* imx7 */
sys/arch/arm/imx/if_enetreg.h
75
# define ENET_ECR_SVLANEN __BIT(9) /* imx7 */
sys/arch/arm/imx/if_enetreg.h
76
# define ENET_ECR_DBSWP __BIT(8)
sys/arch/arm/imx/if_enetreg.h
77
# define ENET_ECR_STOPEN __BIT(7)
sys/arch/arm/imx/if_enetreg.h
78
# define ENET_ECR_DBGEN __BIT(6)
sys/arch/arm/imx/if_enetreg.h
79
# define ENET_ECR_SPEED __BIT(5)
sys/arch/arm/imx/if_enetreg.h
80
# define ENET_ECR_EN1588 __BIT(4)
sys/arch/arm/imx/if_enetreg.h
81
# define ENET_ECR_SLEEP __BIT(3)
sys/arch/arm/imx/if_enetreg.h
82
# define ENET_ECR_MAGICEN __BIT(2)
sys/arch/arm/imx/if_enetreg.h
83
# define ENET_ECR_ETHEREN __BIT(1)
sys/arch/arm/imx/if_enetreg.h
84
# define ENET_ECR_RESET __BIT(0)
sys/arch/arm/imx/if_enetreg.h
96
# define ENET_MSCR_HOLDTIME __BIT(10, 8)
sys/arch/arm/imx/if_enetreg.h
97
# define ENET_MSCR_DIS_PRE __BIT(7)
sys/arch/arm/imx/imx23_apbdma.c
52
#define APBDMA_CMD_HALTONTERMINATE __BIT(8)
sys/arch/arm/imx/imx23_apbdma.c
53
#define APBDMA_CMD_WAIT4ENDCMD __BIT(7)
sys/arch/arm/imx/imx23_apbdma.c
54
#define APBDMA_CMD_SEMAPHORE __BIT(6)
sys/arch/arm/imx/imx23_apbdma.c
55
#define APBDMA_CMD_NANDWAIT4READY __BIT(5)
sys/arch/arm/imx/imx23_apbdma.c
56
#define APBDMA_CMD_NANDLOCK __BIT(4)
sys/arch/arm/imx/imx23_apbdma.c
57
#define APBDMA_CMD_IRQONCMPLT __BIT(3)
sys/arch/arm/imx/imx23_apbdma.c
58
#define APBDMA_CMD_CHAIN __BIT(2)
sys/arch/arm/imx/imx23_apbdma.c
70
#define F_APBH_DMA __BIT(0)
sys/arch/arm/imx/imx23_apbdma.c
71
#define F_APBX_DMA __BIT(1)
sys/arch/arm/imx/imx23_apbdma.h
69
#define WAIT4ENDCMD __BIT(7)
sys/arch/arm/imx/imx23_apbdma.h
70
#define SEMAPHORE __BIT(6)
sys/arch/arm/imx/imx23_apbdma.h
71
#define NANDWAIT4READY __BIT(5)
sys/arch/arm/imx/imx23_apbdma.h
72
#define NANDLOCK __BIT(4)
sys/arch/arm/imx/imx23_apbdma.h
73
#define IRQONCMPLT __BIT(3)
sys/arch/arm/imx/imx23_apbdma.h
74
#define CHAIN __BIT(2)
sys/arch/arm/imx/imx23_apbdmareg.h
49
#define HW_APB_CTRL0_SFTRST __BIT(31)
sys/arch/arm/imx/imx23_apbdmareg.h
50
#define HW_APB_CTRL0_CLKGATE __BIT(30)
sys/arch/arm/imx/imx23_apbhdmareg.h
100
#define HW_APBH_CTRL2_CH0_ERROR_STATUS __BIT(16)
sys/arch/arm/imx/imx23_apbhdmareg.h
102
#define HW_APBH_CTRL2_CH7_ERROR_IRQ __BIT(7)
sys/arch/arm/imx/imx23_apbhdmareg.h
103
#define HW_APBH_CTRL2_CH6_ERROR_IRQ __BIT(6)
sys/arch/arm/imx/imx23_apbhdmareg.h
104
#define HW_APBH_CTRL2_CH5_ERROR_IRQ __BIT(5)
sys/arch/arm/imx/imx23_apbhdmareg.h
105
#define HW_APBH_CTRL2_CH4_ERROR_IRQ __BIT(4)
sys/arch/arm/imx/imx23_apbhdmareg.h
106
#define HW_APBH_CTRL2_CH3_ERROR_IRQ __BIT(3)
sys/arch/arm/imx/imx23_apbhdmareg.h
107
#define HW_APBH_CTRL2_CH2_ERROR_IRQ __BIT(2)
sys/arch/arm/imx/imx23_apbhdmareg.h
108
#define HW_APBH_CTRL2_CH1_ERROR_IRQ __BIT(1)
sys/arch/arm/imx/imx23_apbhdmareg.h
109
#define HW_APBH_CTRL2_CH0_ERROR_IRQ __BIT(0)
sys/arch/arm/imx/imx23_apbhdmareg.h
171
#define HW_APBH_CH1_CMD_HALTONTERMINATE __BIT(8)
sys/arch/arm/imx/imx23_apbhdmareg.h
172
#define HW_APBH_CH1_CMD_WAIT4ENDCMD __BIT(7)
sys/arch/arm/imx/imx23_apbhdmareg.h
173
#define HW_APBH_CH1_CMD_SEMAPHORE __BIT(6)
sys/arch/arm/imx/imx23_apbhdmareg.h
174
#define HW_APBH_CH1_CMD_NANDWAIT4READY __BIT(5)
sys/arch/arm/imx/imx23_apbhdmareg.h
175
#define HW_APBH_CH1_CMD_NANDLOCK __BIT(4)
sys/arch/arm/imx/imx23_apbhdmareg.h
176
#define HW_APBH_CH1_CMD_IRQONCMPLT __BIT(3)
sys/arch/arm/imx/imx23_apbhdmareg.h
177
#define HW_APBH_CH1_CMD_CHAIN __BIT(2)
sys/arch/arm/imx/imx23_apbhdmareg.h
202
#define HW_APBH_CH1_DEBUG1_REQ __BIT(31)
sys/arch/arm/imx/imx23_apbhdmareg.h
203
#define HW_APBH_CH1_DEBUG1_BURST __BIT(30)
sys/arch/arm/imx/imx23_apbhdmareg.h
204
#define HW_APBH_CH1_DEBUG1_KICK __BIT(29)
sys/arch/arm/imx/imx23_apbhdmareg.h
205
#define HW_APBH_CH1_DEBUG1_END __BIT(28)
sys/arch/arm/imx/imx23_apbhdmareg.h
206
#define HW_APBH_CH1_DEBUG1_SENSE __BIT(27)
sys/arch/arm/imx/imx23_apbhdmareg.h
207
#define HW_APBH_CH1_DEBUG1_READY __BIT(26)
sys/arch/arm/imx/imx23_apbhdmareg.h
208
#define HW_APBH_CH1_DEBUG1_LOCK __BIT(25)
sys/arch/arm/imx/imx23_apbhdmareg.h
209
#define HW_APBH_CH1_DEBUG1_NEXTCMDADDRVALID __BIT(24)
sys/arch/arm/imx/imx23_apbhdmareg.h
210
#define HW_APBH_CH1_DEBUG1_RD_FIFO_EMPTY __BIT(23)
sys/arch/arm/imx/imx23_apbhdmareg.h
211
#define HW_APBH_CH1_DEBUG1_RD_FIFO_FULL __BIT(22)
sys/arch/arm/imx/imx23_apbhdmareg.h
212
#define HW_APBH_CH1_DEBUG1_WR_FIFO_EMPTY __BIT(21)
sys/arch/arm/imx/imx23_apbhdmareg.h
213
#define HW_APBH_CH1_DEBUG1_WR_FIFO_FULL __BIT(20)
sys/arch/arm/imx/imx23_apbhdmareg.h
48
#define HW_APBH_CTRL0_SFTRST __BIT(31)
sys/arch/arm/imx/imx23_apbhdmareg.h
49
#define HW_APBH_CTRL0_CLKGATE __BIT(30)
sys/arch/arm/imx/imx23_apbhdmareg.h
50
#define HW_APBH_CTRL0_AHB_BURST8_EN __BIT(29)
sys/arch/arm/imx/imx23_apbhdmareg.h
51
#define HW_APBH_CTRL0_APB_BURST4_EN __BIT(28)
sys/arch/arm/imx/imx23_apbhdmareg.h
66
#define HW_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN __BIT(23)
sys/arch/arm/imx/imx23_apbhdmareg.h
67
#define HW_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN __BIT(22)
sys/arch/arm/imx/imx23_apbhdmareg.h
68
#define HW_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN __BIT(21)
sys/arch/arm/imx/imx23_apbhdmareg.h
69
#define HW_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN __BIT(20)
sys/arch/arm/imx/imx23_apbhdmareg.h
70
#define HW_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN __BIT(19)
sys/arch/arm/imx/imx23_apbhdmareg.h
71
#define HW_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN __BIT(18)
sys/arch/arm/imx/imx23_apbhdmareg.h
72
#define HW_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN __BIT(17)
sys/arch/arm/imx/imx23_apbhdmareg.h
73
#define HW_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN __BIT(16)
sys/arch/arm/imx/imx23_apbhdmareg.h
75
#define HW_APBH_CTRL1_CH7_CMDCMPLT_IRQ __BIT(7)
sys/arch/arm/imx/imx23_apbhdmareg.h
76
#define HW_APBH_CTRL1_CH6_CMDCMPLT_IRQ __BIT(6)
sys/arch/arm/imx/imx23_apbhdmareg.h
77
#define HW_APBH_CTRL1_CH5_CMDCMPLT_IRQ __BIT(5)
sys/arch/arm/imx/imx23_apbhdmareg.h
78
#define HW_APBH_CTRL1_CH4_CMDCMPLT_IRQ __BIT(4)
sys/arch/arm/imx/imx23_apbhdmareg.h
79
#define HW_APBH_CTRL1_CH3_CMDCMPLT_IRQ __BIT(3)
sys/arch/arm/imx/imx23_apbhdmareg.h
80
#define HW_APBH_CTRL1_CH2_CMDCMPLT_IRQ __BIT(2)
sys/arch/arm/imx/imx23_apbhdmareg.h
81
#define HW_APBH_CTRL1_CH1_CMDCMPLT_IRQ __BIT(1)
sys/arch/arm/imx/imx23_apbhdmareg.h
82
#define HW_APBH_CTRL1_CH0_CMDCMPLT_IRQ __BIT(0)
sys/arch/arm/imx/imx23_apbhdmareg.h
93
#define HW_APBH_CTRL2_CH7_ERROR_STATUS __BIT(23)
sys/arch/arm/imx/imx23_apbhdmareg.h
94
#define HW_APBH_CTRL2_CH6_ERROR_STATUS __BIT(22)
sys/arch/arm/imx/imx23_apbhdmareg.h
95
#define HW_APBH_CTRL2_CH5_ERROR_STATUS __BIT(21)
sys/arch/arm/imx/imx23_apbhdmareg.h
96
#define HW_APBH_CTRL2_CH4_ERROR_STATUS __BIT(20)
sys/arch/arm/imx/imx23_apbhdmareg.h
97
#define HW_APBH_CTRL2_CH3_ERROR_STATUS __BIT(19)
sys/arch/arm/imx/imx23_apbhdmareg.h
98
#define HW_APBH_CTRL2_CH2_ERROR_STATUS __BIT(18)
sys/arch/arm/imx/imx23_apbhdmareg.h
99
#define HW_APBH_CTRL2_CH1_ERROR_STATUS __BIT(17)
sys/arch/arm/imx/imx23_clkctrlreg.h
100
#define HW_CLKCTRL_HBUS_BUSY __BIT(29)
sys/arch/arm/imx/imx23_clkctrlreg.h
101
#define HW_CLKCTRL_HBUS_DCP_AS_ENABLE __BIT(28)
sys/arch/arm/imx/imx23_clkctrlreg.h
102
#define HW_CLKCTRL_HBUS_PXP_AS_ENABLE __BIT(27)
sys/arch/arm/imx/imx23_clkctrlreg.h
103
#define HW_CLKCTRL_HBUS_APBHDMA_AS_ENABLE __BIT(26)
sys/arch/arm/imx/imx23_clkctrlreg.h
104
#define HW_CLKCTRL_HBUS_APBXDMA_AS_ENABLE __BIT(25)
sys/arch/arm/imx/imx23_clkctrlreg.h
105
#define HW_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE __BIT(24)
sys/arch/arm/imx/imx23_clkctrlreg.h
106
#define HW_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE __BIT(23)
sys/arch/arm/imx/imx23_clkctrlreg.h
107
#define HW_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE __BIT(22)
sys/arch/arm/imx/imx23_clkctrlreg.h
108
#define HW_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE __BIT(21)
sys/arch/arm/imx/imx23_clkctrlreg.h
109
#define HW_CLKCTRL_HBUS_AUTO_SLOW_MODE __BIT(20)
sys/arch/arm/imx/imx23_clkctrlreg.h
110
#define HW_CLKCTRL_HBUS_RSRVD2 __BIT(19)
sys/arch/arm/imx/imx23_clkctrlreg.h
113
#define HW_CLKCTRL_HBUS_DIV_FRAC_EN __BIT(5)
sys/arch/arm/imx/imx23_clkctrlreg.h
121
#define HW_CLKCTRL_XBUS_BUSY __BIT(31)
sys/arch/arm/imx/imx23_clkctrlreg.h
123
#define HW_CLKCTRL_XBUS_RSVD1 __BIT(10)
sys/arch/arm/imx/imx23_clkctrlreg.h
134
#define HW_CLKCTRL_XTAL_UART_CLK_GATE __BIT(31)
sys/arch/arm/imx/imx23_clkctrlreg.h
135
#define HW_CLKCTRL_XTAL_FILT_CLK24M_GATE __BIT(30)
sys/arch/arm/imx/imx23_clkctrlreg.h
136
#define HW_CLKCTRL_XTAL_PWM_CLK24M_GATE __BIT(29)
sys/arch/arm/imx/imx23_clkctrlreg.h
137
#define HW_CLKCTRL_XTAL_DRI_CLK24M_GATE __BIT(28)
sys/arch/arm/imx/imx23_clkctrlreg.h
138
#define HW_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE __BIT(27)
sys/arch/arm/imx/imx23_clkctrlreg.h
139
#define HW_CLKCTRL_XTAL_TIMROT_CLK32K_GATE __BIT(26)
sys/arch/arm/imx/imx23_clkctrlreg.h
148
#define HW_CLKCTRL_PIX_CLKGATE __BIT(31)
sys/arch/arm/imx/imx23_clkctrlreg.h
149
#define HW_CLKCTRL_PIX_RSRVD2 __BIT(30)
sys/arch/arm/imx/imx23_clkctrlreg.h
150
#define HW_CLKCTRL_PIX_BUSY __BIT(29)
sys/arch/arm/imx/imx23_clkctrlreg.h
152
#define HW_CLKCTRL_PIX_DIV_FRAC_EN __BIT(12)
sys/arch/arm/imx/imx23_clkctrlreg.h
160
#define HW_CLKCTRL_SSP_CLKGATE __BIT(31)
sys/arch/arm/imx/imx23_clkctrlreg.h
161
#define HW_CLKCTRL_SSP_RSVD3 __BIT(30)
sys/arch/arm/imx/imx23_clkctrlreg.h
162
#define HW_CLKCTRL_SSP_BUSY __BIT(29)
sys/arch/arm/imx/imx23_clkctrlreg.h
164
#define HW_CLKCTRL_SSP_RSVD1 __BIT(9)
sys/arch/arm/imx/imx23_clkctrlreg.h
172
#define HW_CLKCTRL_GPMI_CLKGATE __BIT(31)
sys/arch/arm/imx/imx23_clkctrlreg.h
173
#define HW_CLKCTRL_GPMI_RSVD3 __BIT(30)
sys/arch/arm/imx/imx23_clkctrlreg.h
174
#define HW_CLKCTRL_GPMI_BUSY __BIT(29)
sys/arch/arm/imx/imx23_clkctrlreg.h
176
#define HW_CLKCTRL_GPMI_RSVD1 __BIT(10)
sys/arch/arm/imx/imx23_clkctrlreg.h
177
#define HW_CLKCTRL_GPMI_DIV __BIT(9, 0)
sys/arch/arm/imx/imx23_clkctrlreg.h
184
#define HW_CLKCTRL_SPDIF_CLKGATE __BIT(31)
sys/arch/arm/imx/imx23_clkctrlreg.h
192
#define HW_CLKCTRL_EMI_CLKGATE __BIT(31)
sys/arch/arm/imx/imx23_clkctrlreg.h
193
#define HW_CLKCTRL_EMI_SYNC_MODE_EN __BIT(30)
sys/arch/arm/imx/imx23_clkctrlreg.h
194
#define HW_CLKCTRL_EMI_BUSY_REF_XTAL __BIT(29)
sys/arch/arm/imx/imx23_clkctrlreg.h
195
#define HW_CLKCTRL_EMI_BUSY_REF_EMI __BIT(28)
sys/arch/arm/imx/imx23_clkctrlreg.h
196
#define HW_CLKCTRL_EMI_BUSY_REF_CPU __BIT(27)
sys/arch/arm/imx/imx23_clkctrlreg.h
197
#define HW_CLKCTRL_EMI_BUSY_SYNC_MODE __BIT(26)
sys/arch/arm/imx/imx23_clkctrlreg.h
199
#define HW_CLKCTRL_EMI_RSVD4 __BIT(17)
sys/arch/arm/imx/imx23_clkctrlreg.h
200
#define HW_CLKCTRL_EMI_RSVD3 __BIT(16)
sys/arch/arm/imx/imx23_clkctrlreg.h
211
#define HW_CLKCTRL_SAIF_CLKGATE __BIT(31)
sys/arch/arm/imx/imx23_clkctrlreg.h
212
#define HW_CLKCTRL_SAIF_RSRVD2 __BIT(30)
sys/arch/arm/imx/imx23_clkctrlreg.h
213
#define HW_CLKCTRL_SAIF_BUSY __BIT(29)
sys/arch/arm/imx/imx23_clkctrlreg.h
215
#define HW_CLKCTRL_SAIF_DIV_FRAC_EN __BIT(16)
sys/arch/arm/imx/imx23_clkctrlreg.h
223
#define HW_CLKCTRL_TV_CLK_TV108M_GATE __BIT(31)
sys/arch/arm/imx/imx23_clkctrlreg.h
224
#define HW_CLKCTRL_TV_CLK_TV_GATE __BIT(30)
sys/arch/arm/imx/imx23_clkctrlreg.h
232
#define HW_CLKCTRL_ETM_CLKGATE __BIT(31)
sys/arch/arm/imx/imx23_clkctrlreg.h
233
#define HW_CLKCTRL_ETM_RSRVD2 __BIT(30)
sys/arch/arm/imx/imx23_clkctrlreg.h
234
#define HW_CLKCTRL_ETM_BUSY __BIT(29)
sys/arch/arm/imx/imx23_clkctrlreg.h
236
#define HW_CLKCTRL_ETM_DIV_FRAC_EN __BIT(6)
sys/arch/arm/imx/imx23_clkctrlreg.h
247
#define HW_CLKCTRL_FRAC_CLKGATEIO __BIT(31)
sys/arch/arm/imx/imx23_clkctrlreg.h
248
#define HW_CLKCTRL_FRAC_IO_STABLE __BIT(30)
sys/arch/arm/imx/imx23_clkctrlreg.h
250
#define HW_CLKCTRL_FRAC_CLKGATEPIX __BIT(23)
sys/arch/arm/imx/imx23_clkctrlreg.h
251
#define HW_CLKCTRL_FRAC_PIX_STABLE __BIT(22)
sys/arch/arm/imx/imx23_clkctrlreg.h
253
#define HW_CLKCTRL_FRAC_CLKGATEEMI __BIT(15)
sys/arch/arm/imx/imx23_clkctrlreg.h
254
#define HW_CLKCTRL_FRAC_EMI_STABLE __BIT(14)
sys/arch/arm/imx/imx23_clkctrlreg.h
256
#define HW_CLKCTRL_FRAC_CLKGATECPU __BIT(7)
sys/arch/arm/imx/imx23_clkctrlreg.h
257
#define HW_CLKCTRL_FRAC_CPU_STABLE __BIT(6)
sys/arch/arm/imx/imx23_clkctrlreg.h
268
#define HW_CLKCTRL_FRAC1_CLKGATEVID __BIT(31)
sys/arch/arm/imx/imx23_clkctrlreg.h
269
#define HW_CLKCTRL_FRAC1_VID_STABLE __BIT(30)
sys/arch/arm/imx/imx23_clkctrlreg.h
281
#define HW_CLKCTRL_CLKSEQ_BYPASS_ETM __BIT(8)
sys/arch/arm/imx/imx23_clkctrlreg.h
282
#define HW_CLKCTRL_CLKSEQ_BYPASS_CPU __BIT(7)
sys/arch/arm/imx/imx23_clkctrlreg.h
283
#define HW_CLKCTRL_CLKSEQ_BYPASS_EMI __BIT(6)
sys/arch/arm/imx/imx23_clkctrlreg.h
284
#define HW_CLKCTRL_CLKSEQ_BYPASS_SSP __BIT(5)
sys/arch/arm/imx/imx23_clkctrlreg.h
285
#define HW_CLKCTRL_CLKSEQ_BYPASS_GPMI __BIT(4)
sys/arch/arm/imx/imx23_clkctrlreg.h
286
#define HW_CLKCTRL_CLKSEQ_BYPASS_IR __BIT(3)
sys/arch/arm/imx/imx23_clkctrlreg.h
287
#define HW_CLKCTRL_CLKSEQ_RSRVD0 __BIT(2)
sys/arch/arm/imx/imx23_clkctrlreg.h
288
#define HW_CLKCTRL_CLKSEQ_BYPASS_PIX __BIT(1)
sys/arch/arm/imx/imx23_clkctrlreg.h
289
#define HW_CLKCTRL_CLKSEQ_BYPASS_SAIF __BIT(0)
sys/arch/arm/imx/imx23_clkctrlreg.h
297
#define HW_CLKCTRL_RESET_CHIP __BIT(1)
sys/arch/arm/imx/imx23_clkctrlreg.h
298
#define HW_CLKCTRL_RESET_DIG __BIT(0)
sys/arch/arm/imx/imx23_clkctrlreg.h
54
#define HW_CLKCTRL_PLLCTRL0_RSRVD3 __BIT(19)
sys/arch/arm/imx/imx23_clkctrlreg.h
55
#define HW_CLKCTRL_PLLCTRL0_EN_USB_CLKS __BIT(18)
sys/arch/arm/imx/imx23_clkctrlreg.h
56
#define HW_CLKCTRL_PLLCTRL0_RSRVD2 __BIT(17)
sys/arch/arm/imx/imx23_clkctrlreg.h
57
#define HW_CLKCTRL_PLLCTRL0_POWER __BIT(16)
sys/arch/arm/imx/imx23_clkctrlreg.h
65
#define HW_CLKCTRL_PLLCTRL1_LOCK __BIT(31)
sys/arch/arm/imx/imx23_clkctrlreg.h
66
#define HW_CLKCTRL_PLLCTRL1_FORCE_LOCK __BIT(30)
sys/arch/arm/imx/imx23_clkctrlreg.h
79
#define HW_CLKCTRL_CPU_BUSY_REF_XTAL __BIT(29)
sys/arch/arm/imx/imx23_clkctrlreg.h
80
#define HW_CLKCTRL_CPU_BUSY_REF_CPU __BIT(28)
sys/arch/arm/imx/imx23_clkctrlreg.h
81
#define HW_CLKCTRL_CPU_RSVD5 __BIT(27)
sys/arch/arm/imx/imx23_clkctrlreg.h
82
#define HW_CLKCTRL_CPU_DIV_XTAL_FRAC_EN __BIT(26)
sys/arch/arm/imx/imx23_clkctrlreg.h
85
#define HW_CLKCTRL_CPU_INTERRUPT_WAIT __BIT(12)
sys/arch/arm/imx/imx23_clkctrlreg.h
86
#define HW_CLKCTRL_CPU_RSVD3 __BIT(11)
sys/arch/arm/imx/imx23_clkctrlreg.h
87
#define HW_CLKCTRL_CPU_RSVD2 __BIT(10)
sys/arch/arm/imx/imx23_digctlreg.h
100
#define HW_DIGCTL_STATUS_WRITTEN __BIT(0)
sys/arch/arm/imx/imx23_digctlreg.h
123
#define HW_DIGCTL_RAMCTRL_RAM_REPAIR_EN __BIT(0)
sys/arch/arm/imx/imx23_digctlreg.h
179
#define HW_DIGCTL_SJTAGDBG_SJTAG_TDO __BIT(10)
sys/arch/arm/imx/imx23_digctlreg.h
180
#define HW_DIGCTL_SJTAGDBG_SJTAG_TDI __BIT(9)
sys/arch/arm/imx/imx23_digctlreg.h
181
#define HW_DIGCTL_SJTAGDBG_SJTAG_MODE __BIT(8)
sys/arch/arm/imx/imx23_digctlreg.h
183
#define HW_DIGCTL_SJTAGDBG_ACTIVE __BIT(3)
sys/arch/arm/imx/imx23_digctlreg.h
184
#define HW_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE __BIT(2)
sys/arch/arm/imx/imx23_digctlreg.h
185
#define HW_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA __BIT(1)
sys/arch/arm/imx/imx23_digctlreg.h
186
#define HW_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE __BIT(0)
sys/arch/arm/imx/imx23_digctlreg.h
221
#define HW_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE __BIT(10)
sys/arch/arm/imx/imx23_digctlreg.h
222
#define HW_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE __BIT(9)
sys/arch/arm/imx/imx23_digctlreg.h
223
#define HW_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN __BIT(8)
sys/arch/arm/imx/imx23_digctlreg.h
225
#define HW_DIGCTL_OCRAM_BIST_CSR_FAIL __BIT(3)
sys/arch/arm/imx/imx23_digctlreg.h
226
#define HW_DIGCTL_OCRAM_BIST_CSR_PASS __BIT(2)
sys/arch/arm/imx/imx23_digctlreg.h
227
#define HW_DIGCTL_OCRAM_BIST_CSR_DONE __BIT(1)
sys/arch/arm/imx/imx23_digctlreg.h
228
#define HW_DIGCTL_OCRAM_BIST_CSR_START __BIT(0)
sys/arch/arm/imx/imx23_digctlreg.h
48
#define HW_DIGCTL_CTRL_RSVD3 __BIT(31)
sys/arch/arm/imx/imx23_digctlreg.h
49
#define HW_DIGCTL_CTRL_XTAL24M_GATE __BIT(30)
sys/arch/arm/imx/imx23_digctlreg.h
50
#define HW_DIGCTL_CTRL_TRAP_IRQ __BIT(29)
sys/arch/arm/imx/imx23_digctlreg.h
52
#define HW_DIGCTL_CTRL_CACHE_BIST_TMODE __BIT(26)
sys/arch/arm/imx/imx23_digctlreg.h
53
#define HW_DIGCTL_CTRL_LCD_BIST_CLKEN __BIT(25)
sys/arch/arm/imx/imx23_digctlreg.h
54
#define HW_DIGCTL_CTRL_LCD_BIST_START __BIT(24)
sys/arch/arm/imx/imx23_digctlreg.h
55
#define HW_DIGCTL_CTRL_DCP_BIST_CLKEN __BIT(23)
sys/arch/arm/imx/imx23_digctlreg.h
56
#define HW_DIGCTL_CTRL_DCP_BIST_START __BIT(22)
sys/arch/arm/imx/imx23_digctlreg.h
57
#define HW_DIGCTL_CTRL_ARM_BIST_CLKEN __BIT(21)
sys/arch/arm/imx/imx23_digctlreg.h
58
#define HW_DIGCTL_CTRL_USB_TESTMODE __BIT(20)
sys/arch/arm/imx/imx23_digctlreg.h
59
#define HW_DIGCTL_CTRL_ANALOG_TESTMODE __BIT(19)
sys/arch/arm/imx/imx23_digctlreg.h
60
#define HW_DIGCTL_CTRL_DIGITAL_TESTMODE __BIT(18)
sys/arch/arm/imx/imx23_digctlreg.h
61
#define HW_DIGCTL_CTRL_ARM_BIST_START __BIT(17)
sys/arch/arm/imx/imx23_digctlreg.h
62
#define HW_DIGCTL_CTRL_UART_LOOPBACK __BIT(16)
sys/arch/arm/imx/imx23_digctlreg.h
63
#define HW_DIGCTL_CTRL_SAIF_LOOPBACK __BIT(15)
sys/arch/arm/imx/imx23_digctlreg.h
65
#define HW_DIGCTL_CTRL_SAIF_CLKMST_SEL __BIT(12)
sys/arch/arm/imx/imx23_digctlreg.h
66
#define HW_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL __BIT(11)
sys/arch/arm/imx/imx23_digctlreg.h
67
#define HW_DIGCTL_CTRL_RSVD1 __BIT(10)
sys/arch/arm/imx/imx23_digctlreg.h
68
#define HW_DIGCTL_CTRL_SY_ENDIAN __BIT(9)
sys/arch/arm/imx/imx23_digctlreg.h
69
#define HW_DIGCTL_CTRL_SY_SFTRST __BIT(8)
sys/arch/arm/imx/imx23_digctlreg.h
70
#define HW_DIGCTL_CTRL_SY_CLKGATE __BIT(7)
sys/arch/arm/imx/imx23_digctlreg.h
71
#define HW_DIGCTL_CTRL_USE_SERIAL_JTAG __BIT(6)
sys/arch/arm/imx/imx23_digctlreg.h
72
#define HW_DIGCTL_CTRL_TRAP_IN_RANGE __BIT(5)
sys/arch/arm/imx/imx23_digctlreg.h
73
#define HW_DIGCTL_CTRL_TRAP_ENABLE __BIT(4)
sys/arch/arm/imx/imx23_digctlreg.h
74
#define HW_DIGCTL_CTRL_DEBUG_DISABLE __BIT(3)
sys/arch/arm/imx/imx23_digctlreg.h
75
#define HW_DIGCTL_CTRL_USB_CLKGATE __BIT(2)
sys/arch/arm/imx/imx23_digctlreg.h
76
#define HW_DIGCTL_CTRL_JTAG_SHIELD __BIT(1)
sys/arch/arm/imx/imx23_digctlreg.h
77
#define HW_DIGCTL_CTRL_LATCH_ENTROPY __BIT(0)
sys/arch/arm/imx/imx23_digctlreg.h
87
#define HW_DIGCTL_STATUS_USB_HS_PRESENT __BIT(31)
sys/arch/arm/imx/imx23_digctlreg.h
88
#define HW_DIGCTL_STATUS_USB_OTG_PRESENT __BIT(30)
sys/arch/arm/imx/imx23_digctlreg.h
89
#define HW_DIGCTL_STATUS_USB_HOST_PRESENT __BIT(29)
sys/arch/arm/imx/imx23_digctlreg.h
90
#define HW_DIGCTL_STATUS_USB_DEVICE_PRESENT __BIT(28)
sys/arch/arm/imx/imx23_digctlreg.h
92
#define HW_DIGCTL_STATUS_DCP_BIST_FAIL __BIT(10)
sys/arch/arm/imx/imx23_digctlreg.h
93
#define HW_DIGCTL_STATUS_DCP_BIST_PASS __BIT(9)
sys/arch/arm/imx/imx23_digctlreg.h
94
#define HW_DIGCTL_STATUS_DCP_BIST_DONE __BIT(8)
sys/arch/arm/imx/imx23_digctlreg.h
95
#define HW_DIGCTL_STATUS_LCD_BIST_FAIL __BIT(7)
sys/arch/arm/imx/imx23_digctlreg.h
96
#define HW_DIGCTL_STATUS_LCD_BIST_PASS __BIT(6)
sys/arch/arm/imx/imx23_digctlreg.h
97
#define HW_DIGCTL_STATUS_LCD_BIST_DONE __BIT(5)
sys/arch/arm/imx/imx23_digctlreg.h
98
#define HW_DIGCTL_STATUS_JTAG_IN_USE __BIT(4)
sys/arch/arm/imx/imx23_digfiltreg.h
105
#define HW_AUDIOOUT_STAT_DAC_PRESENT __BIT(31)
sys/arch/arm/imx/imx23_digfiltreg.h
116
#define HW_AUDIOOUT_DACSRR_OSR __BIT(31)
sys/arch/arm/imx/imx23_digfiltreg.h
118
#define HW_AUDIOOUT_DACSRR_RSRVD2 __BIT(27)
sys/arch/arm/imx/imx23_digfiltreg.h
134
#define HW_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT __BIT(28)
sys/arch/arm/imx/imx23_digfiltreg.h
136
#define HW_AUDIOOUT_DACVOLUME_EN_ZCD __BIT(25)
sys/arch/arm/imx/imx23_digfiltreg.h
137
#define HW_AUDIOOUT_DACVOLUME_MUTE_LEFT __BIT(24)
sys/arch/arm/imx/imx23_digfiltreg.h
140
#define HW_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT __BIT(12)
sys/arch/arm/imx/imx23_digfiltreg.h
142
#define HW_AUDIOOUT_DACVOLUME_MUTE_RIGHT __BIT(8)
sys/arch/arm/imx/imx23_digfiltreg.h
153
#define HW_AUDIOOUT_DACDEBUG_ENABLE_DACDMA __BIT(31)
sys/arch/arm/imx/imx23_digfiltreg.h
157
#define HW_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS __BIT(5)
sys/arch/arm/imx/imx23_digfiltreg.h
158
#define HW_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS __BIT(4)
sys/arch/arm/imx/imx23_digfiltreg.h
159
#define HW_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE __BIT(3)
sys/arch/arm/imx/imx23_digfiltreg.h
160
#define HW_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE __BIT(2)
sys/arch/arm/imx/imx23_digfiltreg.h
161
#define HW_AUDIOOUT_DACDEBUG_DMA_PREQ __BIT(1)
sys/arch/arm/imx/imx23_digfiltreg.h
162
#define HW_AUDIOOUT_DACDEBUG_FIFO_STATUS __BIT(0)
sys/arch/arm/imx/imx23_digfiltreg.h
173
#define HW_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING __BIT(28)
sys/arch/arm/imx/imx23_digfiltreg.h
175
#define HW_AUDIOOUT_HPVOL_EN_MSTR_ZCD __BIT(25)
sys/arch/arm/imx/imx23_digfiltreg.h
176
#define HW_AUDIOOUT_HPVOL_MUTE __BIT(24)
sys/arch/arm/imx/imx23_digfiltreg.h
178
#define HW_AUDIOOUT_HPVOL_SELECT __BIT(16)
sys/arch/arm/imx/imx23_digfiltreg.h
179
#define HW_AUDIOOUT_HPVOL_RSRVD2 __BIT(15)
sys/arch/arm/imx/imx23_digfiltreg.h
181
#define HW_AUDIOOUT_HPVOL_RSRVD1 __BIT(7)
sys/arch/arm/imx/imx23_digfiltreg.h
203
#define HW_AUDIOOUT_PWRDN_SPEAKER __BIT(24)
sys/arch/arm/imx/imx23_digfiltreg.h
205
#define HW_AUDIOOUT_PWRDN_SELFBIAS __BIT(20)
sys/arch/arm/imx/imx23_digfiltreg.h
207
#define HW_AUDIOOUT_PWRDN_RIGHT_ADC __BIT(16)
sys/arch/arm/imx/imx23_digfiltreg.h
209
#define HW_AUDIOOUT_PWRDN_DAC __BIT(12)
sys/arch/arm/imx/imx23_digfiltreg.h
211
#define HW_AUDIOOUT_PWRDN_ADC __BIT(8)
sys/arch/arm/imx/imx23_digfiltreg.h
213
#define HW_AUDIOOUT_PWRDN_CAPLESS __BIT(4)
sys/arch/arm/imx/imx23_digfiltreg.h
215
#define HW_AUDIOOUT_PWRDN_HEADPHONE __BIT(0)
sys/arch/arm/imx/imx23_digfiltreg.h
226
#define HW_AUDIOOUT_REFCTRL_FASTSETTLING __BIT(26)
sys/arch/arm/imx/imx23_digfiltreg.h
227
#define HW_AUDIOOUT_REFCTRL_RAISE_REF __BIT(25)
sys/arch/arm/imx/imx23_digfiltreg.h
228
#define HW_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS __BIT(24)
sys/arch/arm/imx/imx23_digfiltreg.h
229
#define HW_AUDIOOUT_REFCTRL_RSRVD3 __BIT(23)
sys/arch/arm/imx/imx23_digfiltreg.h
231
#define HW_AUDIOOUT_REFCTRL_LOW_PWR __BIT(19)
sys/arch/arm/imx/imx23_digfiltreg.h
232
#define HW_AUDIOOUT_REFCTRL_LW_REF __BIT(18)
sys/arch/arm/imx/imx23_digfiltreg.h
234
#define HW_AUDIOOUT_REFCTRL_RSRVD2 __BIT(15)
sys/arch/arm/imx/imx23_digfiltreg.h
235
#define HW_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD __BIT(14)
sys/arch/arm/imx/imx23_digfiltreg.h
236
#define HW_AUDIOOUT_REFCTRL_ADJ_ADC __BIT(13)
sys/arch/arm/imx/imx23_digfiltreg.h
237
#define HW_AUDIOOUT_REFCTRL_ADJ_VAG __BIT(12)
sys/arch/arm/imx/imx23_digfiltreg.h
240
#define HW_AUDIOOUT_REFCTRL_RSRVD1 __BIT(3)
sys/arch/arm/imx/imx23_digfiltreg.h
241
#define HW_AUDIOOUT_REFCTRL_DAC_ADJ __BIT(2, 0)
sys/arch/arm/imx/imx23_digfiltreg.h
252
#define HW_AUDIOOUT_ANACTRL_SHORT_CM_STS __BIT(28)
sys/arch/arm/imx/imx23_digfiltreg.h
254
#define HW_AUDIOOUT_ANACTRL_SHORT_LR_STS __BIT(24)
sys/arch/arm/imx/imx23_digfiltreg.h
256
#define HW_AUDIOOUT_ANACTRL_SHORTMODE_CM __BIT(21, 20)
sys/arch/arm/imx/imx23_digfiltreg.h
257
#define HW_AUDIOOUT_ANACTRL_RSRVD5 __BIT(19)
sys/arch/arm/imx/imx23_digfiltreg.h
261
#define HW_AUDIOOUT_ANACTRL_RSRVD3 __BIT(11)
sys/arch/arm/imx/imx23_digfiltreg.h
264
#define HW_AUDIOOUT_ANACTRL_HP_HOLD_GND __BIT(5)
sys/arch/arm/imx/imx23_digfiltreg.h
265
#define HW_AUDIOOUT_ANACTRL_HP_CLASSAB __BIT(4)
sys/arch/arm/imx/imx23_digfiltreg.h
276
#define HW_AUDIOOUT_TEST_RSRVD4 __BIT(31)
sys/arch/arm/imx/imx23_digfiltreg.h
278
#define HW_AUDIOOUT_TEST_RSRVD3 __BIT(27)
sys/arch/arm/imx/imx23_digfiltreg.h
279
#define HW_AUDIOOUT_TEST_TM_ADCIN_TOHP __BIT(26)
sys/arch/arm/imx/imx23_digfiltreg.h
280
#define HW_AUDIOOUT_TEST_TM_LOOP __BIT(25)
sys/arch/arm/imx/imx23_digfiltreg.h
281
#define HW_AUDIOOUT_TEST_TM_HPCOMMON __BIT(24)
sys/arch/arm/imx/imx23_digfiltreg.h
285
#define HW_AUDIOOUT_TEST_VAG_CLASSA __BIT(13)
sys/arch/arm/imx/imx23_digfiltreg.h
286
#define HW_AUDIOOUT_TEST_VAG_DOUBLE_I __BIT(12)
sys/arch/arm/imx/imx23_digfiltreg.h
288
#define HW_AUDIOOUT_TEST_ADCTODAC_LOOP __BIT(3)
sys/arch/arm/imx/imx23_digfiltreg.h
289
#define HW_AUDIOOUT_TEST_DAC_CLASSA __BIT(2)
sys/arch/arm/imx/imx23_digfiltreg.h
290
#define HW_AUDIOOUT_TEST_DAC_DOUBLE_I __BIT(1)
sys/arch/arm/imx/imx23_digfiltreg.h
291
#define HW_AUDIOOUT_TEST_DAC_DIS_RTZ __BIT(0)
sys/arch/arm/imx/imx23_digfiltreg.h
302
#define HW_AUDIOOUT_BISTCTRL_FAIL __BIT(3)
sys/arch/arm/imx/imx23_digfiltreg.h
303
#define HW_AUDIOOUT_BISTCTRL_PASS __BIT(2)
sys/arch/arm/imx/imx23_digfiltreg.h
304
#define HW_AUDIOOUT_BISTCTRL_DONE __BIT(1)
sys/arch/arm/imx/imx23_digfiltreg.h
305
#define HW_AUDIOOUT_BISTCTRL_START __BIT(0)
sys/arch/arm/imx/imx23_digfiltreg.h
339
#define HW_AUDIOOUT_ANACLKCTRL_CLKGATE __BIT(31)
sys/arch/arm/imx/imx23_digfiltreg.h
341
#define HW_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK __BIT(4)
sys/arch/arm/imx/imx23_digfiltreg.h
342
#define HW_AUDIOOUT_ANACLKCTRL_RSRVD2 __BIT(3)
sys/arch/arm/imx/imx23_digfiltreg.h
365
#define HW_AUDIOOUT_SPEAKERCTRL_MUTE __BIT(24)
sys/arch/arm/imx/imx23_digfiltreg.h
54
#define HW_AUDIOIN_CTRL_SFTRST __BIT(31)
sys/arch/arm/imx/imx23_digfiltreg.h
55
#define HW_AUDIOIN_CTRL_CLKGATE __BIT(30)
sys/arch/arm/imx/imx23_digfiltreg.h
59
#define HW_AUDIOIN_CTRL_LR_SWAP __BIT(10)
sys/arch/arm/imx/imx23_digfiltreg.h
60
#define HW_AUDIOIN_CTRL_EDGE_SYNC __BIT(9)
sys/arch/arm/imx/imx23_digfiltreg.h
61
#define HW_AUDIOIN_CTRL_INVERT_1BIT __BIT(8)
sys/arch/arm/imx/imx23_digfiltreg.h
62
#define HW_AUDIOIN_CTRL_OFFSET_ENABLE __BIT(7)
sys/arch/arm/imx/imx23_digfiltreg.h
63
#define HW_AUDIOIN_CTRL_HPF_ENABLE __BIT(6)
sys/arch/arm/imx/imx23_digfiltreg.h
64
#define HW_AUDIOIN_CTRL_WORD_LENGTH __BIT(5)
sys/arch/arm/imx/imx23_digfiltreg.h
65
#define HW_AUDIOIN_CTRL_LOOPBACK __BIT(4)
sys/arch/arm/imx/imx23_digfiltreg.h
66
#define HW_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ __BIT(3)
sys/arch/arm/imx/imx23_digfiltreg.h
67
#define HW_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ __BIT(2)
sys/arch/arm/imx/imx23_digfiltreg.h
68
#define HW_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN __BIT(1)
sys/arch/arm/imx/imx23_digfiltreg.h
69
#define HW_AUDIOIN_CTRL_RUN __BIT(0)
sys/arch/arm/imx/imx23_digfiltreg.h
78
#define HW_AUDIOOUT_CTRL_SFTRST __BIT(31)
sys/arch/arm/imx/imx23_digfiltreg.h
79
#define HW_AUDIOOUT_CTRL_CLKGATE __BIT(30)
sys/arch/arm/imx/imx23_digfiltreg.h
82
#define HW_AUDIOOUT_CTRL_RSRVD3 __BIT(15)
sys/arch/arm/imx/imx23_digfiltreg.h
83
#define HW_AUDIOOUT_CTRL_LR_SWAP __BIT(14)
sys/arch/arm/imx/imx23_digfiltreg.h
84
#define HW_AUDIOOUT_CTRL_EDGE_SYNC __BIT(13)
sys/arch/arm/imx/imx23_digfiltreg.h
85
#define HW_AUDIOOUT_CTRL_INVERT_1BIT __BIT(12)
sys/arch/arm/imx/imx23_digfiltreg.h
88
#define HW_AUDIOOUT_CTRL_RSRVD1 __BIT(7)
sys/arch/arm/imx/imx23_digfiltreg.h
89
#define HW_AUDIOOUT_CTRL_WORD_LENGTH __BIT(6)
sys/arch/arm/imx/imx23_digfiltreg.h
90
#define HW_AUDIOOUT_CTRL_DAC_ZERO_ENABLE __BIT(5)
sys/arch/arm/imx/imx23_digfiltreg.h
91
#define HW_AUDIOOUT_CTRL_LOOPBACK __BIT(4)
sys/arch/arm/imx/imx23_digfiltreg.h
92
#define HW_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ __BIT(3)
sys/arch/arm/imx/imx23_digfiltreg.h
93
#define HW_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ __BIT(2)
sys/arch/arm/imx/imx23_digfiltreg.h
94
#define HW_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN __BIT(1)
sys/arch/arm/imx/imx23_digfiltreg.h
95
#define HW_AUDIOOUT_CTRL_RUN __BIT(0)
sys/arch/arm/imx/imx23_icollreg.h
148
#define HW_ICOLL_LEVELACK_IRQLEVELACK __BIT(3, 0)
sys/arch/arm/imx/imx23_icollreg.h
158
#define HW_ICOLL_CTRL_SFTRST __BIT(31)
sys/arch/arm/imx/imx23_icollreg.h
159
#define HW_ICOLL_CTRL_CLKGATE __BIT(30)
sys/arch/arm/imx/imx23_icollreg.h
162
#define HW_ICOLL_CTRL_BYPASS_FSM __BIT(20)
sys/arch/arm/imx/imx23_icollreg.h
163
#define HW_ICOLL_CTRL_NO_NESTING __BIT(19)
sys/arch/arm/imx/imx23_icollreg.h
164
#define HW_ICOLL_CTRL_ARM_RSE_MODE __BIT(18)
sys/arch/arm/imx/imx23_icollreg.h
165
#define HW_ICOLL_CTRL_FIQ_FINAL_ENABLE __BIT(17)
sys/arch/arm/imx/imx23_icollreg.h
166
#define HW_ICOLL_CTRL_IRQ_FINAL_ENABLE __BIT(16)
sys/arch/arm/imx/imx23_icollreg.h
232
#define HW_ICOLL_INTERRUPT_ENFIQ __BIT(4)
sys/arch/arm/imx/imx23_icollreg.h
233
#define HW_ICOLL_INTERRUPT_SOFTIRQ __BIT(3)
sys/arch/arm/imx/imx23_icollreg.h
234
#define HW_ICOLL_INTERRUPT_ENABLE __BIT(2)
sys/arch/arm/imx/imx23_icollreg.h
246
#define HW_ICOLL_INTERRUPT0_ENFIQ __BIT(4)
sys/arch/arm/imx/imx23_icollreg.h
247
#define HW_ICOLL_INTERRUPT0_SOFTIRQ __BIT(3)
sys/arch/arm/imx/imx23_icollreg.h
248
#define HW_ICOLL_INTERRUPT0_ENABLE __BIT(2)
sys/arch/arm/imx/imx23_icollreg.h
260
#define HW_ICOLL_INTERRUPT127_ENFIQ __BIT(4)
sys/arch/arm/imx/imx23_icollreg.h
261
#define HW_ICOLL_INTERRUPT127_SOFTIRQ __BIT(3)
sys/arch/arm/imx/imx23_icollreg.h
262
#define HW_ICOLL_INTERRUPT127_ENABLE __BIT(2)
sys/arch/arm/imx/imx23_icollreg.h
277
#define HW_ICOLL_DEBUG_FIQ __BIT(17)
sys/arch/arm/imx/imx23_icollreg.h
278
#define HW_ICOLL_DEBUG_IRQ __BIT(16)
sys/arch/arm/imx/imx23_mmcreg.h
122
#define HW_SSP_CTRL1_SDIO_IRQ __BIT(31)
sys/arch/arm/imx/imx23_mmcreg.h
123
#define HW_SSP_CTRL1_SDIO_IRQ_EN __BIT(30)
sys/arch/arm/imx/imx23_mmcreg.h
124
#define HW_SSP_CTRL1_RESP_ERR_IRQ __BIT(29)
sys/arch/arm/imx/imx23_mmcreg.h
125
#define HW_SSP_CTRL1_RESP_ERR_IRQ_EN __BIT(28)
sys/arch/arm/imx/imx23_mmcreg.h
126
#define HW_SSP_CTRL1_RESP_TIMEOUT_IRQ __BIT(27)
sys/arch/arm/imx/imx23_mmcreg.h
127
#define HW_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN __BIT(26)
sys/arch/arm/imx/imx23_mmcreg.h
128
#define HW_SSP_CTRL1_DATA_TIMEOUT_IRQ __BIT(25)
sys/arch/arm/imx/imx23_mmcreg.h
129
#define HW_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN __BIT(24)
sys/arch/arm/imx/imx23_mmcreg.h
130
#define HW_SSP_CTRL1_DATA_CRC_IRQ __BIT(23)
sys/arch/arm/imx/imx23_mmcreg.h
131
#define HW_SSP_CTRL1_DATA_CRC_IRQ_EN __BIT(22)
sys/arch/arm/imx/imx23_mmcreg.h
132
#define HW_SSP_CTRL1_FIFO_UNDERRUN_IRQ __BIT(21)
sys/arch/arm/imx/imx23_mmcreg.h
133
#define HW_SSP_CTRL1_FIFO_UNDERRUN_EN __BIT(20)
sys/arch/arm/imx/imx23_mmcreg.h
134
#define HW_SSP_CTRL1_RSVD3 __BIT(19)
sys/arch/arm/imx/imx23_mmcreg.h
135
#define HW_SSP_CTRL1_RSVD2 __BIT(18)
sys/arch/arm/imx/imx23_mmcreg.h
136
#define HW_SSP_CTRL1_RECV_TIMEOUT_IRQ __BIT(17)
sys/arch/arm/imx/imx23_mmcreg.h
137
#define HW_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN __BIT(16)
sys/arch/arm/imx/imx23_mmcreg.h
138
#define HW_SSP_CTRL1_FIFO_OVERRUN_IRQ __BIT(15)
sys/arch/arm/imx/imx23_mmcreg.h
139
#define HW_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN __BIT(14)
sys/arch/arm/imx/imx23_mmcreg.h
140
#define HW_SSP_CTRL1_DMA_ENABLE __BIT(13)
sys/arch/arm/imx/imx23_mmcreg.h
141
#define HW_SSP_CTRL1_RSVD1 __BIT(12)
sys/arch/arm/imx/imx23_mmcreg.h
142
#define HW_SSP_CTRL1_SLAVE_OUT_DISABLE __BIT(11)
sys/arch/arm/imx/imx23_mmcreg.h
143
#define HW_SSP_CTRL1_PHASE __BIT(10)
sys/arch/arm/imx/imx23_mmcreg.h
144
#define HW_SSP_CTRL1_POLARITY __BIT(9)
sys/arch/arm/imx/imx23_mmcreg.h
145
#define HW_SSP_CTRL1_SLAVE_MODE __BIT(8)
sys/arch/arm/imx/imx23_mmcreg.h
189
#define HW_SSP_STATUS_PRESENT __BIT(31)
sys/arch/arm/imx/imx23_mmcreg.h
190
#define HW_SSP_STATUS_RSVD5 __BIT(30)
sys/arch/arm/imx/imx23_mmcreg.h
191
#define HW_SSP_STATUS_SD_PRESENT __BIT(29)
sys/arch/arm/imx/imx23_mmcreg.h
192
#define HW_SSP_STATUS_CARD_DETECT __BIT(28)
sys/arch/arm/imx/imx23_mmcreg.h
194
#define HW_SSP_STATUS_DMASENSE __BIT(21)
sys/arch/arm/imx/imx23_mmcreg.h
195
#define HW_SSP_STATUS_DMATERM __BIT(20)
sys/arch/arm/imx/imx23_mmcreg.h
196
#define HW_SSP_STATUS_DMAREQ __BIT(19)
sys/arch/arm/imx/imx23_mmcreg.h
197
#define HW_SSP_STATUS_DMAEND __BIT(18)
sys/arch/arm/imx/imx23_mmcreg.h
198
#define HW_SSP_STATUS_SDIO_IRQ __BIT(17)
sys/arch/arm/imx/imx23_mmcreg.h
199
#define HW_SSP_STATUS_RESP_CRC_ERR __BIT(16)
sys/arch/arm/imx/imx23_mmcreg.h
200
#define HW_SSP_STATUS_RESP_ERR __BIT(15)
sys/arch/arm/imx/imx23_mmcreg.h
201
#define HW_SSP_STATUS_RESP_TIMEOUT __BIT(14)
sys/arch/arm/imx/imx23_mmcreg.h
202
#define HW_SSP_STATUS_DATA_CRC_ERR __BIT(13)
sys/arch/arm/imx/imx23_mmcreg.h
203
#define HW_SSP_STATUS_TIMEOUT __BIT(12)
sys/arch/arm/imx/imx23_mmcreg.h
204
#define HW_SSP_STATUS_RECV_TIMEOUT_STAT __BIT(11)
sys/arch/arm/imx/imx23_mmcreg.h
205
#define HW_SSP_STATUS_RSVD3 __BIT(10)
sys/arch/arm/imx/imx23_mmcreg.h
206
#define HW_SSP_STATUS_FIFO_OVRFLW __BIT(9)
sys/arch/arm/imx/imx23_mmcreg.h
207
#define HW_SSP_STATUS_FIFO_FULL __BIT(8)
sys/arch/arm/imx/imx23_mmcreg.h
208
#define HW_SSP_STATUS_RSVD2 __BIT(7, 6)
sys/arch/arm/imx/imx23_mmcreg.h
209
#define HW_SSP_STATUS_FIFO_EMPTY __BIT(5)
sys/arch/arm/imx/imx23_mmcreg.h
210
#define HW_SSP_STATUS_FIFO_UNDRFLW __BIT(4)
sys/arch/arm/imx/imx23_mmcreg.h
211
#define HW_SSP_STATUS_CMD_BUSY __BIT(3)
sys/arch/arm/imx/imx23_mmcreg.h
212
#define HW_SSP_STATUS_DATA_BUSY __BIT(2)
sys/arch/arm/imx/imx23_mmcreg.h
213
#define HW_SSP_STATUS_RSVD1 __BIT(1)
sys/arch/arm/imx/imx23_mmcreg.h
214
#define HW_SSP_STATUS_BUSY __BIT(0)
sys/arch/arm/imx/imx23_mmcreg.h
222
#define HW_SSP_DEBUG_DATA_STALL __BIT(27)
sys/arch/arm/imx/imx23_mmcreg.h
225
#define HW_SSP_DEBUG_CMD_OE __BIT(19)
sys/arch/arm/imx/imx23_mmcreg.h
229
#define HW_SSP_DEBUG_SSP_CMD __BIT(9)
sys/arch/arm/imx/imx23_mmcreg.h
230
#define HW_SSP_DEBUG_SSP_RESP __BIT(8)
sys/arch/arm/imx/imx23_mmcreg.h
51
#define HW_SSP_CTRL0_SFTRST __BIT(31)
sys/arch/arm/imx/imx23_mmcreg.h
52
#define HW_SSP_CTRL0_CLKGATE __BIT(30)
sys/arch/arm/imx/imx23_mmcreg.h
53
#define HW_SSP_CTRL0_RUN __BIT(29)
sys/arch/arm/imx/imx23_mmcreg.h
54
#define HW_SSP_CTRL0_SDIO_IRQ_CHECK __BIT(28)
sys/arch/arm/imx/imx23_mmcreg.h
55
#define HW_SSP_CTRL0_LOCK_CS __BIT(27)
sys/arch/arm/imx/imx23_mmcreg.h
56
#define HW_SSP_CTRL0_IGNORE_CRC __BIT(26)
sys/arch/arm/imx/imx23_mmcreg.h
57
#define HW_SSP_CTRL0_READ __BIT(25)
sys/arch/arm/imx/imx23_mmcreg.h
58
#define HW_SSP_CTRL0_DATA_XFER __BIT(24)
sys/arch/arm/imx/imx23_mmcreg.h
60
#define HW_SSP_CTRL0_WAIT_FOR_IRQ __BIT(21)
sys/arch/arm/imx/imx23_mmcreg.h
61
#define HW_SSP_CTRL0_WAIT_FOR_CMD __BIT(20)
sys/arch/arm/imx/imx23_mmcreg.h
62
#define HW_SSP_CTRL0_LONG_RESP __BIT(19)
sys/arch/arm/imx/imx23_mmcreg.h
63
#define HW_SSP_CTRL0_CHECK_RESP __BIT(18)
sys/arch/arm/imx/imx23_mmcreg.h
64
#define HW_SSP_CTRL0_GET_RESP __BIT(17)
sys/arch/arm/imx/imx23_mmcreg.h
65
#define HW_SSP_CTRL0_ENABLE __BIT(16)
sys/arch/arm/imx/imx23_mmcreg.h
77
#define HW_SSP_CMD0_SLOW_CLKING_EN __BIT(22)
sys/arch/arm/imx/imx23_mmcreg.h
78
#define HW_SSP_CMD0_CONT_CLKING_EN __BIT(21)
sys/arch/arm/imx/imx23_mmcreg.h
79
#define HW_SSP_CMD0_APPEND_8CYC __BIT(20)
sys/arch/arm/imx/imx23_pinctrlreg.h
1025
#define HW_PINCTRL_DRIVE9_RSRVD7 __BIT(31)
sys/arch/arm/imx/imx23_pinctrlreg.h
1026
#define HW_PINCTRL_DRIVE9_BANK2_PIN15_V __BIT(30)
sys/arch/arm/imx/imx23_pinctrlreg.h
1028
#define HW_PINCTRL_DRIVE9_RSRVD6 __BIT(27)
sys/arch/arm/imx/imx23_pinctrlreg.h
1029
#define HW_PINCTRL_DRIVE9_BANK2_PIN14_V __BIT(26)
sys/arch/arm/imx/imx23_pinctrlreg.h
1031
#define HW_PINCTRL_DRIVE9_RSRVD5 __BIT(23)
sys/arch/arm/imx/imx23_pinctrlreg.h
1032
#define HW_PINCTRL_DRIVE9_BANK2_PIN13_V __BIT(22)
sys/arch/arm/imx/imx23_pinctrlreg.h
1034
#define HW_PINCTRL_DRIVE9_RSRVD4 __BIT(19)
sys/arch/arm/imx/imx23_pinctrlreg.h
1035
#define HW_PINCTRL_DRIVE9_BANK2_PIN12_V __BIT(18)
sys/arch/arm/imx/imx23_pinctrlreg.h
1037
#define HW_PINCTRL_DRIVE9_RSRVD3 __BIT(15)
sys/arch/arm/imx/imx23_pinctrlreg.h
1038
#define HW_PINCTRL_DRIVE9_BANK2_PIN11_V __BIT(14)
sys/arch/arm/imx/imx23_pinctrlreg.h
1040
#define HW_PINCTRL_DRIVE9_RSRVD2 __BIT(11)
sys/arch/arm/imx/imx23_pinctrlreg.h
1041
#define HW_PINCTRL_DRIVE9_BANK2_PIN10_V __BIT(10)
sys/arch/arm/imx/imx23_pinctrlreg.h
1043
#define HW_PINCTRL_DRIVE9_RSRVD1 __BIT(7)
sys/arch/arm/imx/imx23_pinctrlreg.h
1044
#define HW_PINCTRL_DRIVE9_BANK2_PIN09_V __BIT(6)
sys/arch/arm/imx/imx23_pinctrlreg.h
1057
#define HW_PINCTRL_DRIVE10_RSRVD7 __BIT(31)
sys/arch/arm/imx/imx23_pinctrlreg.h
1058
#define HW_PINCTRL_DRIVE10_BANK2_PIN23_V __BIT(30)
sys/arch/arm/imx/imx23_pinctrlreg.h
1060
#define HW_PINCTRL_DRIVE10_RSRVD6 __BIT(27)
sys/arch/arm/imx/imx23_pinctrlreg.h
1061
#define HW_PINCTRL_DRIVE10_BANK2_PIN22_V __BIT(26)
sys/arch/arm/imx/imx23_pinctrlreg.h
1063
#define HW_PINCTRL_DRIVE10_RSRVD5 __BIT(23)
sys/arch/arm/imx/imx23_pinctrlreg.h
1064
#define HW_PINCTRL_DRIVE10_BANK2_PIN21_V __BIT(22)
sys/arch/arm/imx/imx23_pinctrlreg.h
1066
#define HW_PINCTRL_DRIVE10_RSRVD4 __BIT(19)
sys/arch/arm/imx/imx23_pinctrlreg.h
1067
#define HW_PINCTRL_DRIVE10_BANK2_PIN20_V __BIT(18)
sys/arch/arm/imx/imx23_pinctrlreg.h
1069
#define HW_PINCTRL_DRIVE10_RSRVD3 __BIT(15)
sys/arch/arm/imx/imx23_pinctrlreg.h
1070
#define HW_PINCTRL_DRIVE10_BANK2_PIN19_V __BIT(14)
sys/arch/arm/imx/imx23_pinctrlreg.h
1072
#define HW_PINCTRL_DRIVE10_RSRVD2 __BIT(11)
sys/arch/arm/imx/imx23_pinctrlreg.h
1073
#define HW_PINCTRL_DRIVE10_BANK2_PIN18_V __BIT(10)
sys/arch/arm/imx/imx23_pinctrlreg.h
1075
#define HW_PINCTRL_DRIVE10_RSRVD1 __BIT(7)
sys/arch/arm/imx/imx23_pinctrlreg.h
1076
#define HW_PINCTRL_DRIVE10_BANK2_PIN17_V __BIT(6)
sys/arch/arm/imx/imx23_pinctrlreg.h
1078
#define HW_PINCTRL_DRIVE10_RSRVD0 __BIT(3)
sys/arch/arm/imx/imx23_pinctrlreg.h
1079
#define HW_PINCTRL_DRIVE10_BANK2_PIN16_V __BIT(2)
sys/arch/arm/imx/imx23_pinctrlreg.h
1090
#define HW_PINCTRL_DRIVE11_RSRVD7 __BIT(31)
sys/arch/arm/imx/imx23_pinctrlreg.h
1091
#define HW_PINCTRL_DRIVE11_BANK2_PIN31_V __BIT(30)
sys/arch/arm/imx/imx23_pinctrlreg.h
1093
#define HW_PINCTRL_DRIVE11_RSRVD6 __BIT(27)
sys/arch/arm/imx/imx23_pinctrlreg.h
1094
#define HW_PINCTRL_DRIVE11_BANK2_PIN30_V __BIT(26)
sys/arch/arm/imx/imx23_pinctrlreg.h
1096
#define HW_PINCTRL_DRIVE11_RSRVD5 __BIT(23)
sys/arch/arm/imx/imx23_pinctrlreg.h
1097
#define HW_PINCTRL_DRIVE11_BANK2_PIN29_V __BIT(22)
sys/arch/arm/imx/imx23_pinctrlreg.h
1100
#define HW_PINCTRL_DRIVE11_BANK2_PIN28_MA __BIT(17, 16)
sys/arch/arm/imx/imx23_pinctrlreg.h
1103
#define HW_PINCTRL_DRIVE11_RSRVD2 __BIT(11)
sys/arch/arm/imx/imx23_pinctrlreg.h
1104
#define HW_PINCTRL_DRIVE11_BANK2_PIN26_V __BIT(10)
sys/arch/arm/imx/imx23_pinctrlreg.h
1106
#define HW_PINCTRL_DRIVE11_RSRVD1 __BIT(7)
sys/arch/arm/imx/imx23_pinctrlreg.h
1107
#define HW_PINCTRL_DRIVE11_BANK2_PIN25_V __BIT(6)
sys/arch/arm/imx/imx23_pinctrlreg.h
1109
#define HW_PINCTRL_DRIVE11_RSRVD0 __BIT(3)
sys/arch/arm/imx/imx23_pinctrlreg.h
1110
#define HW_PINCTRL_DRIVE11_BANK2_PIN24_V __BIT(2)
sys/arch/arm/imx/imx23_pinctrlreg.h
1121
#define HW_PINCTRL_DRIVE12_RSRVD7 __BIT(31)
sys/arch/arm/imx/imx23_pinctrlreg.h
1122
#define HW_PINCTRL_DRIVE12_BANK3_PIN07_V __BIT(30)
sys/arch/arm/imx/imx23_pinctrlreg.h
1124
#define HW_PINCTRL_DRIVE12_RSRVD6 __BIT(27)
sys/arch/arm/imx/imx23_pinctrlreg.h
1125
#define HW_PINCTRL_DRIVE12_BANK3_PIN06_V __BIT(26)
sys/arch/arm/imx/imx23_pinctrlreg.h
1127
#define HW_PINCTRL_DRIVE12_RSRVD5 __BIT(23)
sys/arch/arm/imx/imx23_pinctrlreg.h
1128
#define HW_PINCTRL_DRIVE12_BANK3_PIN05_V __BIT(22)
sys/arch/arm/imx/imx23_pinctrlreg.h
1130
#define HW_PINCTRL_DRIVE12_RSRVD4 __BIT(19)
sys/arch/arm/imx/imx23_pinctrlreg.h
1131
#define HW_PINCTRL_DRIVE12_BANK3_PIN04_V __BIT(18)
sys/arch/arm/imx/imx23_pinctrlreg.h
1133
#define HW_PINCTRL_DRIVE12_RSRVD3 __BIT(15)
sys/arch/arm/imx/imx23_pinctrlreg.h
1134
#define HW_PINCTRL_DRIVE12_BANK3_PIN03_V __BIT(14)
sys/arch/arm/imx/imx23_pinctrlreg.h
1136
#define HW_PINCTRL_DRIVE12_RSRVD2 __BIT(11)
sys/arch/arm/imx/imx23_pinctrlreg.h
1137
#define HW_PINCTRL_DRIVE12_BANK3_PIN02_V __BIT(10)
sys/arch/arm/imx/imx23_pinctrlreg.h
1139
#define HW_PINCTRL_DRIVE12_RSRVD1 __BIT(7)
sys/arch/arm/imx/imx23_pinctrlreg.h
1140
#define HW_PINCTRL_DRIVE12_BANK3_PIN01_V __BIT(6)
sys/arch/arm/imx/imx23_pinctrlreg.h
1142
#define HW_PINCTRL_DRIVE12_RSRVD0 __BIT(3)
sys/arch/arm/imx/imx23_pinctrlreg.h
1143
#define HW_PINCTRL_DRIVE12_BANK3_PIN00_V __BIT(2)
sys/arch/arm/imx/imx23_pinctrlreg.h
1154
#define HW_PINCTRL_DRIVE13_RSRVD7 __BIT(31)
sys/arch/arm/imx/imx23_pinctrlreg.h
1155
#define HW_PINCTRL_DRIVE13_BANK3_PIN15_V __BIT(30)
sys/arch/arm/imx/imx23_pinctrlreg.h
1157
#define HW_PINCTRL_DRIVE13_RSRVD6 __BIT(27)
sys/arch/arm/imx/imx23_pinctrlreg.h
1158
#define HW_PINCTRL_DRIVE13_BANK3_PIN14_V __BIT(26)
sys/arch/arm/imx/imx23_pinctrlreg.h
1160
#define HW_PINCTRL_DRIVE13_RSRVD5 __BIT(23)
sys/arch/arm/imx/imx23_pinctrlreg.h
1161
#define HW_PINCTRL_DRIVE13_BANK3_PIN13_V __BIT(22)
sys/arch/arm/imx/imx23_pinctrlreg.h
1163
#define HW_PINCTRL_DRIVE13_RSRVD4 __BIT(19)
sys/arch/arm/imx/imx23_pinctrlreg.h
1164
#define HW_PINCTRL_DRIVE13_BANK3_PIN12_V __BIT(18)
sys/arch/arm/imx/imx23_pinctrlreg.h
1166
#define HW_PINCTRL_DRIVE13_RSRVD3 __BIT(15)
sys/arch/arm/imx/imx23_pinctrlreg.h
1167
#define HW_PINCTRL_DRIVE13_BANK3_PIN11_V __BIT(14)
sys/arch/arm/imx/imx23_pinctrlreg.h
1169
#define HW_PINCTRL_DRIVE13_RSRVD2 __BIT(11)
sys/arch/arm/imx/imx23_pinctrlreg.h
1170
#define HW_PINCTRL_DRIVE13_BANK3_PIN10_V __BIT(10)
sys/arch/arm/imx/imx23_pinctrlreg.h
1172
#define HW_PINCTRL_DRIVE13_RSRVD1 __BIT(7)
sys/arch/arm/imx/imx23_pinctrlreg.h
1173
#define HW_PINCTRL_DRIVE13_BANK3_PIN09_V __BIT(6)
sys/arch/arm/imx/imx23_pinctrlreg.h
1175
#define HW_PINCTRL_DRIVE13_RSRVD0 __BIT(3)
sys/arch/arm/imx/imx23_pinctrlreg.h
1176
#define HW_PINCTRL_DRIVE13_BANK3_PIN08_V __BIT(2)
sys/arch/arm/imx/imx23_pinctrlreg.h
1188
#define HW_PINCTRL_DRIVE14_RSRVD5 __BIT(23)
sys/arch/arm/imx/imx23_pinctrlreg.h
1189
#define HW_PINCTRL_DRIVE14_BANK3_PIN21_V __BIT(22)
sys/arch/arm/imx/imx23_pinctrlreg.h
1191
#define HW_PINCTRL_DRIVE14_RSRVD4 __BIT(19)
sys/arch/arm/imx/imx23_pinctrlreg.h
1192
#define HW_PINCTRL_DRIVE14_BANK3_PIN20_V __BIT(18)
sys/arch/arm/imx/imx23_pinctrlreg.h
1194
#define HW_PINCTRL_DRIVE14_RSRVD3 __BIT(15)
sys/arch/arm/imx/imx23_pinctrlreg.h
1195
#define HW_PINCTRL_DRIVE14_BANK3_PIN19_V __BIT(14)
sys/arch/arm/imx/imx23_pinctrlreg.h
1197
#define HW_PINCTRL_DRIVE14_RSRVD2 __BIT(11)
sys/arch/arm/imx/imx23_pinctrlreg.h
1198
#define HW_PINCTRL_DRIVE14_BANK3_PIN18_V __BIT(10)
sys/arch/arm/imx/imx23_pinctrlreg.h
1200
#define HW_PINCTRL_DRIVE14_RSRVD1 __BIT(7)
sys/arch/arm/imx/imx23_pinctrlreg.h
1201
#define HW_PINCTRL_DRIVE14_BANK3_PIN17_V __BIT(6)
sys/arch/arm/imx/imx23_pinctrlreg.h
1203
#define HW_PINCTRL_DRIVE14_RSRVD0 __BIT(3)
sys/arch/arm/imx/imx23_pinctrlreg.h
1204
#define HW_PINCTRL_DRIVE14_BANK3_PIN16_V __BIT(2)
sys/arch/arm/imx/imx23_pinctrlreg.h
1224
#define HW_PINCTRL_PULL2_BANK2_PIN28 __BIT(28)
sys/arch/arm/imx/imx23_pinctrlreg.h
1225
#define HW_PINCTRL_PULL2_BANK2_PIN27 __BIT(27)
sys/arch/arm/imx/imx23_pinctrlreg.h
1227
#define HW_PINCTRL_PULL2_BANK2_PIN08 __BIT(8)
sys/arch/arm/imx/imx23_pinctrlreg.h
1229
#define HW_PINCTRL_PULL2_BANK2_PIN05 __BIT(5)
sys/arch/arm/imx/imx23_pinctrlreg.h
1230
#define HW_PINCTRL_PULL2_BANK2_PIN04 __BIT(4)
sys/arch/arm/imx/imx23_pinctrlreg.h
1231
#define HW_PINCTRL_PULL2_BANK2_PIN03 __BIT(3)
sys/arch/arm/imx/imx23_pinctrlreg.h
1232
#define HW_PINCTRL_PULL2_BANK2_PIN02 __BIT(2)
sys/arch/arm/imx/imx23_pinctrlreg.h
1233
#define HW_PINCTRL_PULL2_BANK2_PIN01 __BIT(1)
sys/arch/arm/imx/imx23_pinctrlreg.h
1234
#define HW_PINCTRL_PULL2_BANK2_PIN00 __BIT(0)
sys/arch/arm/imx/imx23_pinctrlreg.h
1245
#define HW_PINCTRL_PULL3_BANK3_PIN17 __BIT(17)
sys/arch/arm/imx/imx23_pinctrlreg.h
1246
#define HW_PINCTRL_PULL3_BANK3_PIN16 __BIT(16)
sys/arch/arm/imx/imx23_pinctrlreg.h
1247
#define HW_PINCTRL_PULL3_BANK3_PIN15 __BIT(15)
sys/arch/arm/imx/imx23_pinctrlreg.h
1248
#define HW_PINCTRL_PULL3_BANK3_PIN14 __BIT(14)
sys/arch/arm/imx/imx23_pinctrlreg.h
1249
#define HW_PINCTRL_PULL3_BANK3_PIN13 __BIT(13)
sys/arch/arm/imx/imx23_pinctrlreg.h
1250
#define HW_PINCTRL_PULL3_BANK3_PIN12 __BIT(12)
sys/arch/arm/imx/imx23_pinctrlreg.h
1251
#define HW_PINCTRL_PULL3_BANK3_PIN11 __BIT(11)
sys/arch/arm/imx/imx23_pinctrlreg.h
1252
#define HW_PINCTRL_PULL3_BANK3_PIN10 __BIT(10)
sys/arch/arm/imx/imx23_pinctrlreg.h
1253
#define HW_PINCTRL_PULL3_BANK3_PIN09 __BIT(9)
sys/arch/arm/imx/imx23_pinctrlreg.h
1254
#define HW_PINCTRL_PULL3_BANK3_PIN08 __BIT(8)
sys/arch/arm/imx/imx23_pinctrlreg.h
1255
#define HW_PINCTRL_PULL3_BANK3_PIN07 __BIT(7)
sys/arch/arm/imx/imx23_pinctrlreg.h
1256
#define HW_PINCTRL_PULL3_BANK3_PIN06 __BIT(6)
sys/arch/arm/imx/imx23_pinctrlreg.h
1257
#define HW_PINCTRL_PULL3_BANK3_PIN05 __BIT(5)
sys/arch/arm/imx/imx23_pinctrlreg.h
1258
#define HW_PINCTRL_PULL3_BANK3_PIN04 __BIT(4)
sys/arch/arm/imx/imx23_pinctrlreg.h
1259
#define HW_PINCTRL_PULL3_BANK3_PIN03 __BIT(3)
sys/arch/arm/imx/imx23_pinctrlreg.h
1260
#define HW_PINCTRL_PULL3_BANK3_PIN02 __BIT(2)
sys/arch/arm/imx/imx23_pinctrlreg.h
1261
#define HW_PINCTRL_PULL3_BANK3_PIN01 __BIT(1)
sys/arch/arm/imx/imx23_pinctrlreg.h
1262
#define HW_PINCTRL_PULL3_BANK3_PIN00 __BIT(0)
sys/arch/arm/imx/imx23_pinctrlreg.h
48
#define HW_PINCTRL_CTRL_SFTRST __BIT(31)
sys/arch/arm/imx/imx23_pinctrlreg.h
49
#define HW_PINCTRL_CTRL_CLKGATE __BIT(30)
sys/arch/arm/imx/imx23_pinctrlreg.h
51
#define HW_PINCTRL_CTRL_PRESENT3 __BIT(27)
sys/arch/arm/imx/imx23_pinctrlreg.h
52
#define HW_PINCTRL_CTRL_PRESENT2 __BIT(26)
sys/arch/arm/imx/imx23_pinctrlreg.h
53
#define HW_PINCTRL_CTRL_PRESENT1 __BIT(25)
sys/arch/arm/imx/imx23_pinctrlreg.h
54
#define HW_PINCTRL_CTRL_PRESENT0 __BIT(24)
sys/arch/arm/imx/imx23_pinctrlreg.h
55
#define HW_PINCTRL_CTRL_RSRVD1 __BIT(23, 3)
sys/arch/arm/imx/imx23_pinctrlreg.h
57
#define HW_PINCTRL_CTRL_IRQOUT1 __BIT(1)
sys/arch/arm/imx/imx23_pinctrlreg.h
58
#define HW_PINCTRL_CTRL_IRQOUT0 __BIT(0)
sys/arch/arm/imx/imx23_rtcreg.h
126
#define HW_RTC_PERSISTENT0_AUTO_RESTART __BIT(17)
sys/arch/arm/imx/imx23_rtcreg.h
127
#define HW_RTC_PERSISTENT0_DISABLE_PSWITCH __BIT(16)
sys/arch/arm/imx/imx23_rtcreg.h
129
#define HW_RTC_PERSISTENT0_DISABLE_XTALOK __BIT(13)
sys/arch/arm/imx/imx23_rtcreg.h
131
#define HW_RTC_PERSISTENT0_ALARM_WAKE __BIT(7)
sys/arch/arm/imx/imx23_rtcreg.h
132
#define HW_RTC_PERSISTENT0_XTAL32_FREQ __BIT(6)
sys/arch/arm/imx/imx23_rtcreg.h
133
#define HW_RTC_PERSISTENT0_XTAL32KHZ_PWRUP __BIT(5)
sys/arch/arm/imx/imx23_rtcreg.h
134
#define HW_RTC_PERSISTENT0_XTAL24MHZ_PWRUP __BIT(4)
sys/arch/arm/imx/imx23_rtcreg.h
135
#define HW_RTC_PERSISTENT0_LCK_SECS __BIT(3)
sys/arch/arm/imx/imx23_rtcreg.h
136
#define HW_RTC_PERSISTENT0_ALARM_EN __BIT(2)
sys/arch/arm/imx/imx23_rtcreg.h
137
#define HW_RTC_PERSISTENT0_ALARM_WAKE_EN __BIT(1)
sys/arch/arm/imx/imx23_rtcreg.h
138
#define HW_RTC_PERSISTENT0_CLOCKSOURCE __BIT(0)
sys/arch/arm/imx/imx23_rtcreg.h
199
#define HW_RTC_DEBUG_WATCHDOG_RESET_MASK __BIT(1)
sys/arch/arm/imx/imx23_rtcreg.h
200
#define HW_RTC_DEBUG_WATCHDOG_RESET __BIT(0)
sys/arch/arm/imx/imx23_rtcreg.h
48
#define HW_RTC_CTRL_SFTRST __BIT(31)
sys/arch/arm/imx/imx23_rtcreg.h
49
#define HW_RTC_CTRL_CLKGATE __BIT(30)
sys/arch/arm/imx/imx23_rtcreg.h
51
#define HW_RTC_CTRL_SUPPRESS_COPY2ANALOG __BIT(6)
sys/arch/arm/imx/imx23_rtcreg.h
52
#define HW_RTC_CTRL_FORCE_UPDATE __BIT(5)
sys/arch/arm/imx/imx23_rtcreg.h
53
#define HW_RTC_CTRL_WATCHDOGEN __BIT(4)
sys/arch/arm/imx/imx23_rtcreg.h
54
#define HW_RTC_CTRL_ONEMSEC_IRQ __BIT(3)
sys/arch/arm/imx/imx23_rtcreg.h
55
#define HW_RTC_CTRL_ALARM_IRQ __BIT(2)
sys/arch/arm/imx/imx23_rtcreg.h
56
#define HW_RTC_CTRL_ONEMSEC_IRQ_EN __BIT(1)
sys/arch/arm/imx/imx23_rtcreg.h
57
#define HW_RTC_CTRL_ALARM_IRQ_EN __BIT(0)
sys/arch/arm/imx/imx23_rtcreg.h
67
#define HW_RTC_STAT_RTC_PRESENT __BIT(31)
sys/arch/arm/imx/imx23_rtcreg.h
68
#define HW_RTC_STAT_ALARM_PRESENT __BIT(30)
sys/arch/arm/imx/imx23_rtcreg.h
69
#define HW_RTC_STAT_WATCHDOG_PRESENT __BIT(29)
sys/arch/arm/imx/imx23_rtcreg.h
70
#define HW_RTC_STAT_XTAL32000_PRESENT __BIT(28)
sys/arch/arm/imx/imx23_rtcreg.h
71
#define HW_RTC_STAT_XTAL32768_PRESENT __BIT(27)
sys/arch/arm/imx/imx23_rtcreg.h
73
#define HW_RTC_STAT_STALE_REGS __BIT(23, 16)
sys/arch/arm/imx/imx23_rtcreg.h
74
#define HW_RTC_STAT_NEW_REGS __BIT(15, 8)
sys/arch/arm/imx/imx23_rtcreg.h
75
#define HW_RTC_STAT_RSVD0 __BIT(7, 0)
sys/arch/arm/imx/imx23_timrotreg.h
110
#define HW_TIMROT_TIMCTRL1_IRQ __BIT(15)
sys/arch/arm/imx/imx23_timrotreg.h
111
#define HW_TIMROT_TIMCTRL1_IRQ_EN __BIT(14)
sys/arch/arm/imx/imx23_timrotreg.h
113
#define HW_TIMROT_TIMCTRL1_POLARITY __BIT(8)
sys/arch/arm/imx/imx23_timrotreg.h
114
#define HW_TIMROT_TIMCTRL1_UPDATE __BIT(7)
sys/arch/arm/imx/imx23_timrotreg.h
115
#define HW_TIMROT_TIMCTRL1_RELOAD __BIT(6)
sys/arch/arm/imx/imx23_timrotreg.h
136
#define HW_TIMROT_TIMCTRL2_IRQ __BIT(15)
sys/arch/arm/imx/imx23_timrotreg.h
137
#define HW_TIMROT_TIMCTRL2_IRQ_EN __BIT(14)
sys/arch/arm/imx/imx23_timrotreg.h
139
#define HW_TIMROT_TIMCTRL2_POLARITY __BIT(8)
sys/arch/arm/imx/imx23_timrotreg.h
140
#define HW_TIMROT_TIMCTRL2_UPDATE __BIT(7)
sys/arch/arm/imx/imx23_timrotreg.h
141
#define HW_TIMROT_TIMCTRL2_RELOAD __BIT(6)
sys/arch/arm/imx/imx23_timrotreg.h
143
#define HW_TIMROT_TIMCTRL2_SELECT __BIT(3, 0)
sys/arch/arm/imx/imx23_timrotreg.h
163
#define HW_TIMROT_TIMCTRL3_IRQ __BIT(15)
sys/arch/arm/imx/imx23_timrotreg.h
164
#define HW_TIMROT_TIMCTRL3_IRQ_EN __BIT(14)
sys/arch/arm/imx/imx23_timrotreg.h
166
#define HW_TIMROT_TIMCTRL3_DUTY_VALID __BIT(10)
sys/arch/arm/imx/imx23_timrotreg.h
167
#define HW_TIMROT_TIMCTRL3_DUTY_CYCLE __BIT(9)
sys/arch/arm/imx/imx23_timrotreg.h
168
#define HW_TIMROT_TIMCTRL3_POLARITY __BIT(8)
sys/arch/arm/imx/imx23_timrotreg.h
169
#define HW_TIMROT_TIMCTRL3_UPDATE __BIT(7)
sys/arch/arm/imx/imx23_timrotreg.h
170
#define HW_TIMROT_TIMCTRL3_RELOAD __BIT(6)
sys/arch/arm/imx/imx23_timrotreg.h
48
#define HW_TIMROT_ROTCTRL_SFTRST __BIT(31)
sys/arch/arm/imx/imx23_timrotreg.h
49
#define HW_TIMROT_ROTCTRL_CLKGATE __BIT(30)
sys/arch/arm/imx/imx23_timrotreg.h
50
#define HW_TIMROT_ROTCTRL_ROTARY_PRESENT __BIT(29)
sys/arch/arm/imx/imx23_timrotreg.h
51
#define HW_TIMROT_ROTCTRL_TIM3_PRESENT __BIT(28)
sys/arch/arm/imx/imx23_timrotreg.h
52
#define HW_TIMROT_ROTCTRL_TIM2_PRESENT __BIT(27)
sys/arch/arm/imx/imx23_timrotreg.h
53
#define HW_TIMROT_ROTCTRL_TIM1_PRESENT __BIT(26)
sys/arch/arm/imx/imx23_timrotreg.h
54
#define HW_TIMROT_ROTCTRL_TIM0_PRESENT __BIT(25)
sys/arch/arm/imx/imx23_timrotreg.h
58
#define HW_TIMROT_ROTCTRL_RELATIVE __BIT(12)
sys/arch/arm/imx/imx23_timrotreg.h
60
#define HW_TIMROT_ROTCTRL_POLARITY_B __BIT(9)
sys/arch/arm/imx/imx23_timrotreg.h
61
#define HW_TIMROT_ROTCTRL_POLARITY_A __BIT(8)
sys/arch/arm/imx/imx23_timrotreg.h
62
#define HW_TIMROT_ROTCTRL_RSRVD2 __BIT(7)
sys/arch/arm/imx/imx23_timrotreg.h
64
#define HW_TIMROT_ROTCTRL_RSRVD1 __BIT(3)
sys/arch/arm/imx/imx23_timrotreg.h
84
#define HW_TIMROT_TIMCTRL0_IRQ __BIT(15)
sys/arch/arm/imx/imx23_timrotreg.h
85
#define HW_TIMROT_TIMCTRL0_IRQ_EN __BIT(14)
sys/arch/arm/imx/imx23_timrotreg.h
87
#define HW_TIMROT_TIMCTRL0_POLARITY __BIT(8)
sys/arch/arm/imx/imx23_timrotreg.h
88
#define HW_TIMROT_TIMCTRL0_UPDATE __BIT(7)
sys/arch/arm/imx/imx23_timrotreg.h
89
#define HW_TIMROT_TIMCTRL0_RELOAD __BIT(6)
sys/arch/arm/imx/imx23_usbphyreg.h
105
#define HW_USBPHY_CTRL_SFTRST __BIT(31)
sys/arch/arm/imx/imx23_usbphyreg.h
106
#define HW_USBPHY_CTRL_CLKGATE __BIT(30)
sys/arch/arm/imx/imx23_usbphyreg.h
107
#define HW_USBPHY_CTRL_UTMI_SUSPENDM __BIT(29)
sys/arch/arm/imx/imx23_usbphyreg.h
108
#define HW_USBPHY_CTRL_HOST_FORCE_LS_SE0 __BIT(28)
sys/arch/arm/imx/imx23_usbphyreg.h
110
#define HW_USBPHY_CTRL_DATA_ON_LRADC __BIT(13)
sys/arch/arm/imx/imx23_usbphyreg.h
111
#define HW_USBPHY_CTRL_DEVPLUGIN_IRQ __BIT(12)
sys/arch/arm/imx/imx23_usbphyreg.h
112
#define HW_USBPHY_CTRL_ENIRQDEVPLUGIN __BIT(11)
sys/arch/arm/imx/imx23_usbphyreg.h
113
#define HW_USBPHY_CTRL_RESUME_IRQ __BIT(10)
sys/arch/arm/imx/imx23_usbphyreg.h
114
#define HW_USBPHY_CTRL_ENIRQRESUMEDETECT __BIT(9)
sys/arch/arm/imx/imx23_usbphyreg.h
115
#define HW_USBPHY_CTRL_RSVD2 __BIT(8)
sys/arch/arm/imx/imx23_usbphyreg.h
116
#define HW_USBPHY_CTRL_ENOTGIDDETECT __BIT(7)
sys/arch/arm/imx/imx23_usbphyreg.h
117
#define HW_USBPHY_CTRL_RSVD1 __BIT(6)
sys/arch/arm/imx/imx23_usbphyreg.h
118
#define HW_USBPHY_CTRL_DEVPLUGIN_POLARITY __BIT(5)
sys/arch/arm/imx/imx23_usbphyreg.h
119
#define HW_USBPHY_CTRL_ENDEVPLUGINDETECT __BIT(4)
sys/arch/arm/imx/imx23_usbphyreg.h
120
#define HW_USBPHY_CTRL_HOSTDISCONDETECT_IRQ __BIT(3)
sys/arch/arm/imx/imx23_usbphyreg.h
121
#define HW_USBPHY_CTRL_ENIRQHOSTDISCON __BIT(2)
sys/arch/arm/imx/imx23_usbphyreg.h
122
#define HW_USBPHY_CTRL_ENHOSTDISCONDETECT __BIT(1)
sys/arch/arm/imx/imx23_usbphyreg.h
123
#define HW_USBPHY_CTRL_RSVD0 __BIT(0)
sys/arch/arm/imx/imx23_usbphyreg.h
131
#define HW_USBPHY_STATUS_RESUME_STATUS __BIT(10)
sys/arch/arm/imx/imx23_usbphyreg.h
132
#define HW_USBPHY_STATUS_RSVD3 __BIT(9)
sys/arch/arm/imx/imx23_usbphyreg.h
133
#define HW_USBPHY_STATUS_OTGID_STATUS __BIT(8)
sys/arch/arm/imx/imx23_usbphyreg.h
134
#define HW_USBPHY_STATUS_RSVD2 __BIT(7)
sys/arch/arm/imx/imx23_usbphyreg.h
135
#define HW_USBPHY_STATUS_DEVPLUGIN_STATUS __BIT(6)
sys/arch/arm/imx/imx23_usbphyreg.h
137
#define HW_USBPHY_STATUS_HOSTDISCONDETECT_STATUS __BIT(3)
sys/arch/arm/imx/imx23_usbphyreg.h
148
#define HW_USBPHY_DEBUG_RSVD3 __BIT(31)
sys/arch/arm/imx/imx23_usbphyreg.h
149
#define HW_USBPHY_DEBUG_CLKGATE __BIT(30)
sys/arch/arm/imx/imx23_usbphyreg.h
150
#define HW_USBPHY_DEBUG_HOST_RESUME_DEBUG __BIT(29)
sys/arch/arm/imx/imx23_usbphyreg.h
152
#define HW_USBPHY_DEBUG_ENSQUELCHRESET __BIT(24)
sys/arch/arm/imx/imx23_usbphyreg.h
156
#define HW_USBPHY_DEBUG_ENTX2RXCOUNT __BIT(12)
sys/arch/arm/imx/imx23_usbphyreg.h
161
#define HW_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD __BIT(1)
sys/arch/arm/imx/imx23_usbphyreg.h
162
#define HW_USBPHY_DEBUG_OTGIDPIOLOCK __BIT(0)
sys/arch/arm/imx/imx23_usbphyreg.h
183
#define HW_USBPHY_DEBUG1_ENTX2TX __BIT(12)
sys/arch/arm/imx/imx23_usbphyreg.h
208
#define HW_USBPHY_IP_TSTI_TX_DP __BIT(18)
sys/arch/arm/imx/imx23_usbphyreg.h
209
#define HW_USBPHY_IP_TSTI_TX_DM __BIT(17)
sys/arch/arm/imx/imx23_usbphyreg.h
210
#define HW_USBPHY_IP_ANALOG_TESTMODE __BIT(16)
sys/arch/arm/imx/imx23_usbphyreg.h
212
#define HW_USBPHY_IP_EN_USB_CLKS __BIT(2)
sys/arch/arm/imx/imx23_usbphyreg.h
213
#define HW_USBPHY_IP_PLL_LOCKED __BIT(1)
sys/arch/arm/imx/imx23_usbphyreg.h
214
#define HW_USBPHY_IP_PLL_POWER __BIT(0)
sys/arch/arm/imx/imx23_usbphyreg.h
49
#define HW_USBPHY_PWD_RXPWDRX __BIT(20)
sys/arch/arm/imx/imx23_usbphyreg.h
50
#define HW_USBPHY_PWD_RXPWDDIFF __BIT(19)
sys/arch/arm/imx/imx23_usbphyreg.h
51
#define HW_USBPHY_PWD_RXPWD1PT1 __BIT(18)
sys/arch/arm/imx/imx23_usbphyreg.h
52
#define HW_USBPHY_PWD_RXPWDENV __BIT(17)
sys/arch/arm/imx/imx23_usbphyreg.h
54
#define HW_USBPHY_PWD_TXPWDV2I __BIT(12)
sys/arch/arm/imx/imx23_usbphyreg.h
55
#define HW_USBPHY_PWD_TXPWDIBIAS __BIT(11)
sys/arch/arm/imx/imx23_usbphyreg.h
56
#define HW_USBPHY_PWD_TXPWDFS __BIT(10)
sys/arch/arm/imx/imx23_usbphyreg.h
69
#define HW_USBPHY_TX_USBPHY_TX_SYNC_INVERT __BIT(25)
sys/arch/arm/imx/imx23_usbphyreg.h
70
#define HW_USBPHY_TX_USBPHY_TX_SYNC_MUX __BIT(24)
sys/arch/arm/imx/imx23_usbphyreg.h
72
#define HW_USBPHY_TX_TXENCAL45DP __BIT(21)
sys/arch/arm/imx/imx23_usbphyreg.h
73
#define HW_USBPHY_TX_RSVD3 __BIT(20)
sys/arch/arm/imx/imx23_usbphyreg.h
76
#define HW_USBPHY_TX_TXENCAL45DN __BIT(13)
sys/arch/arm/imx/imx23_usbphyreg.h
77
#define HW_USBPHY_TX_RSVD1 __BIT(12)
sys/arch/arm/imx/imx23_usbphyreg.h
91
#define HW_USBPHY_RX_RXDBYPASS __BIT(22)
sys/arch/arm/imx/imx23_usbphyreg.h
94
#define HW_USBPHY_RX_RSVD0 __BIT(3)
sys/arch/arm/imx/imx31_gpio.c
154
pending &= ~__BIT(irq);
sys/arch/arm/imx/imx31_gpio.c
172
uint32_t irq_mask = __BIT(is->is_irq);
sys/arch/arm/imx/imx51_ccm.c
519
if (dp_mfn & __BIT(26))
sys/arch/arm/imx/imx51_ccmreg.h
113
#define CDCR_SW_PERIPH_CLK_DIV_REQ __BIT(6)
sys/arch/arm/imx/imx51_ccmreg.h
125
#define CSR2_EPDC_ASM_ACTIVE __BIT(13)
sys/arch/arm/imx/imx51_ccmreg.h
126
#define CSR2_EPXP_ASM_ACTIVE __BIT(12)
sys/arch/arm/imx/imx51_ccmreg.h
127
#define CSR2_ELCDIF_ASM_ACTIVE __BIT(11)
sys/arch/arm/imx/imx51_ccmreg.h
128
#define CSR2_SYS_CLK_XTAL_ACTIVE __BIT(10)
sys/arch/arm/imx/imx51_ccmreg.h
129
#define CSR2_ELCDIF_PIX_BUSY __BIT(9)
sys/arch/arm/imx/imx51_ccmreg.h
130
#define CSR2_EPDC_PIX_BUSY __BIT(8)
sys/arch/arm/imx/imx51_ccmreg.h
131
#define CSR2_MSHC_XMSCKI_BUSY __BIT(7)
sys/arch/arm/imx/imx51_ccmreg.h
132
#define CSR2_BCH_BUSY __BIT(6)
sys/arch/arm/imx/imx51_ccmreg.h
133
#define CSR2_GPMI_BUSY __BIT(5)
sys/arch/arm/imx/imx51_ccmreg.h
134
#define CSR2_EPDC_AXI_BUSY __BIT(4)
sys/arch/arm/imx/imx51_ccmreg.h
135
#define CSR2_DISPLAY_AXI_BUSY __BIT(3)
sys/arch/arm/imx/imx51_ccmreg.h
136
#define CSR2_DDR_CLK_REF_PLL_BUSY __BIT(2)
sys/arch/arm/imx/imx51_ccmreg.h
137
#define CSR2_SYS_CLK_REF_PLL_BUSY __BIT(1)
sys/arch/arm/imx/imx51_ccmreg.h
138
#define CSR2_SYS_CLK_REF_XTAL_BUSY __BIT(0)
sys/arch/arm/imx/imx51_ccmreg.h
166
#define EPDC_ASM_EN __BIT(9)
sys/arch/arm/imx/imx51_ccmreg.h
37
#define CCR_FPM_MULT __BIT(12)
sys/arch/arm/imx/imx51_ccmreg.h
38
#define CCR_COSC_EN __BIT(12)
sys/arch/arm/imx/imx51_ccmreg.h
42
#define CCSR_LP_APM __BIT(9)
sys/arch/arm/imx/imx51_ccmreg.h
46
#define CCSR_PLL1_SW_CLK_SEL __BIT(2)
sys/arch/arm/imx/imx51_ccmreg.h
47
#define CCSR_PLL2_SW_CLK_SEL __BIT(1)
sys/arch/arm/imx/imx51_ccmreg.h
48
#define CCSR_PLL3_SW_CLK_SEL __BIT(0)
sys/arch/arm/imx/imx51_ccmreg.h
51
#define CBCDR_DDR_HIGH_FREQ_CLK_SEL __BIT(30)
sys/arch/arm/imx/imx51_ccmreg.h
56
#define CBCDR_EMI_CLK_SEL __BIT(26)
sys/arch/arm/imx/imx51_ccmreg.h
57
#define CBCDR_PERIPH_CLK_SEL __BIT(25)
sys/arch/arm/imx/imx51_ccmreg.h
71
#define CBCMR_PERCLK_LP_APM_SEL __BIT(1)
sys/arch/arm/imx/imx51_ccmreg.h
72
#define CBCMR_PERCLK_IPG_SEL __BIT(0)
sys/arch/arm/imx/imx51_ccmreg.h
77
#define CSCMR1_ESDHC2_CLK_SEL __BIT(20)
sys/arch/arm/imx/imx51_ccmreg.h
78
#define CSCMR1_ESDHC4_CLK_SEL __BIT(19)
sys/arch/arm/imx/imx51_ccmreg.h
82
#define CSCMR1_ESDHC3_CLK_SEL __BIT(19)
sys/arch/arm/imx/imx51_ccmreg.h
83
#define CSCMR1_ESDHC4_CLK_SEL __BIT(18)
sys/arch/arm/imx/imx51_dpllreg.h
37
#define DP_CTL_HFSM __BIT(7)
sys/arch/arm/imx/imx51_dpllreg.h
41
#define DP_CTL_REF_CLK_DIV __BIT(10)
sys/arch/arm/imx/imx51_dpllreg.h
42
#define DP_CTL_DPDCK0_2_EN __BIT(12)
sys/arch/arm/imx/imx51_ipuv3.c
836
reg &= ~__BIT(CH_PANNEL_BG);
sys/arch/arm/imx/imx51_ipuv3.c
848
IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_PRI_1, __BIT(CH_PANNEL_BG));
sys/arch/arm/imx/imx51_ipuv3.c
852
reg |= __BIT(CH_PANNEL_BG);
sys/arch/arm/imx/imx51_ipuv3.c
856
reg |= __BIT(CH_PANNEL_BG);
sys/arch/arm/imx/imx51_ipuv3.c
863
IPUV3_WRITE(sc, cm, IPU_CM_CUR_BUF_0, __BIT(CH_PANNEL_BG));
sys/arch/arm/imx/imx51_ipuv3reg.h
100
#define CM_DISP_GEN_MCU_CSI_VSYNC_DEST __BIT(23)
sys/arch/arm/imx/imx51_ipuv3reg.h
101
#define CM_DISP_GEN_MCU_MAX_BURST_STOP __BIT(22)
sys/arch/arm/imx/imx51_ipuv3reg.h
109
#define CM_MEM_START __BIT(31)
sys/arch/arm/imx/imx51_ipuv3reg.h
113
#define CM_GPR_IPU_CH_BUF1_RDY1_CLR __BIT(31)
sys/arch/arm/imx/imx51_ipuv3reg.h
114
#define CM_GPR_IPU_CH_BUF1_RDY0_CLR __BIT(30)
sys/arch/arm/imx/imx51_ipuv3reg.h
115
#define CM_GPR_IPU_CH_BUF0_RDY1_CLR __BIT(29)
sys/arch/arm/imx/imx51_ipuv3reg.h
116
#define CM_GPR_IPU_CH_BUF0_RDY0_CLR __BIT(28)
sys/arch/arm/imx/imx51_ipuv3reg.h
117
#define CM_GPR_IPU_ALT_CH_BUF1_RDY1_CLR __BIT(27)
sys/arch/arm/imx/imx51_ipuv3reg.h
118
#define CM_GPR_IPU_ALT_CH_BUF1_RDY0_CLR __BIT(26)
sys/arch/arm/imx/imx51_ipuv3reg.h
119
#define CM_GPR_IPU_ALT_CH_BUF0_RDY1_CLR __BIT(25)
sys/arch/arm/imx/imx51_ipuv3reg.h
120
#define CM_GPR_IPU_ALT_CH_BUF0_RDY0_CLR __BIT(24)
sys/arch/arm/imx/imx51_ipuv3reg.h
121
#define CM_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS __BIT(23)
sys/arch/arm/imx/imx51_ipuv3reg.h
122
#define CM_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS __BIT(22)
sys/arch/arm/imx/imx51_ipuv3reg.h
123
#define CM_GPR_IPU_CH_BUF2_RDY1_CLR __BIT(21)
sys/arch/arm/imx/imx51_ipuv3reg.h
124
#define CM_GPR_IPU_CH_BUF2_RDY0_CLR __BIT(20)
sys/arch/arm/imx/imx51_ipuv3reg.h
125
#define CM_GPR_IPU_GP(n) __BIT((n))
sys/arch/arm/imx/imx51_ipuv3reg.h
260
#define DI_GENERAL_DISP_CLOCK_INIT __BIT(23)
sys/arch/arm/imx/imx51_ipuv3reg.h
261
#define DI_GENERAL_MASK_SEL __BIT(22)
sys/arch/arm/imx/imx51_ipuv3reg.h
262
#define DI_GENERAL_VSYNC_EXT __BIT(21)
sys/arch/arm/imx/imx51_ipuv3reg.h
263
#define DI_GENERAL_CLK_EXT __BIT(20)
sys/arch/arm/imx/imx51_ipuv3reg.h
265
#define DI_GENERAL_POLARITY_DISP_CLK __BIT(17)
sys/arch/arm/imx/imx51_ipuv3reg.h
267
#define DI_GENERAL_ERR_TREATMENT __BIT(11)
sys/arch/arm/imx/imx51_ipuv3reg.h
268
#define DI_GENERAL_ERM_VSYNC_SEL __BIT(10)
sys/arch/arm/imx/imx51_ipuv3reg.h
288
#define DI_SW_GEN1_CNT_AUTO_RELOAD __BIT(28)
sys/arch/arm/imx/imx51_ipuv3reg.h
300
#define DI_SYNC_AS_GEN_SYNC_START_EN __BIT(28)
sys/arch/arm/imx/imx51_ipuv3reg.h
316
#define DI_POL_DRDY_POLARITY_17 __BIT(6)
sys/arch/arm/imx/imx51_ipuv3reg.h
317
#define DI_POL_DRDY_POLARITY_16 __BIT(5)
sys/arch/arm/imx/imx51_ipuv3reg.h
318
#define DI_POL_DRDY_POLARITY_15 __BIT(4)
sys/arch/arm/imx/imx51_ipuv3reg.h
319
#define DI_POL_DRDY_POLARITY_14 __BIT(3)
sys/arch/arm/imx/imx51_ipuv3reg.h
320
#define DI_POL_DRDY_POLARITY_13 __BIT(2)
sys/arch/arm/imx/imx51_ipuv3reg.h
321
#define DI_POL_DRDY_POLARITY_12 __BIT(1)
sys/arch/arm/imx/imx51_ipuv3reg.h
322
#define DI_POL_DRDY_POLARITY_11 __BIT(0)
sys/arch/arm/imx/imx51_ipuv3reg.h
37
#define CM_CONF_CSI_SEL __BIT(31)
sys/arch/arm/imx/imx51_ipuv3reg.h
38
#define CM_CONF_IC_INPUT __BIT(30)
sys/arch/arm/imx/imx51_ipuv3reg.h
39
#define CM_CONF_CSI1_DATA_SOURCE __BIT(29)
sys/arch/arm/imx/imx51_ipuv3reg.h
40
#define CM_CONF_CSI0_DATA_SOURCE __BIT(28)
sys/arch/arm/imx/imx51_ipuv3reg.h
41
#define CM_CONF_VDI_DMFC_SYNC __BIT(27)
sys/arch/arm/imx/imx51_ipuv3reg.h
42
#define CM_CONF_IC_DMFC_SYNC __BIT(26)
sys/arch/arm/imx/imx51_ipuv3reg.h
43
#define CM_CONF_IC_DMFC_SEL __BIT(25)
sys/arch/arm/imx/imx51_ipuv3reg.h
44
#define CM_CONF_ISP_DOUBLE_FLOW __BIT(24)
sys/arch/arm/imx/imx51_ipuv3reg.h
45
#define CM_CONF_IDMAC_DISABLE __BIT(22)
sys/arch/arm/imx/imx51_ipuv3reg.h
46
#define CM_CONF_IPU_DIAGBUS_ON __BIT(21)
sys/arch/arm/imx/imx51_ipuv3reg.h
48
#define CM_CONF_VDI_EN __BIT(12)
sys/arch/arm/imx/imx51_ipuv3reg.h
49
#define CM_CONF_SISG_EN __BIT(11)
sys/arch/arm/imx/imx51_ipuv3reg.h
490
#define DMFC_RD_CHAN_WM_EN_0 __BIT(17)
sys/arch/arm/imx/imx51_ipuv3reg.h
50
#define CM_CONF_DMFC_EN __BIT(10)
sys/arch/arm/imx/imx51_ipuv3reg.h
508
#define DMFC_WR_CHAN_DEF_WM_EN_2C __BIT(25)
sys/arch/arm/imx/imx51_ipuv3reg.h
51
#define CM_CONF_DC_EN __BIT(9)
sys/arch/arm/imx/imx51_ipuv3reg.h
511
#define DMFC_WR_CHAN_DEF_WM_EN_1C __BIT(17)
sys/arch/arm/imx/imx51_ipuv3reg.h
514
#define DMFC_WR_CHAN_DEF_WM_EN_2 __BIT(9)
sys/arch/arm/imx/imx51_ipuv3reg.h
517
#define DMFC_WR_CHAN_DEF_WM_EN_1 __BIT(1)
sys/arch/arm/imx/imx51_ipuv3reg.h
52
#define CM_CONF_SMFC_EN __BIT(8)
sys/arch/arm/imx/imx51_ipuv3reg.h
53
#define CM_CONF_DI1_EN __BIT(7)
sys/arch/arm/imx/imx51_ipuv3reg.h
534
#define DMFC_DP_CHAN_DEF_WM_EN_6F __BIT(25)
sys/arch/arm/imx/imx51_ipuv3reg.h
537
#define DMFC_DP_CHAN_DEF_WM_EN_6B __BIT(17)
sys/arch/arm/imx/imx51_ipuv3reg.h
54
#define CM_CONF_DI0_EN __BIT(6)
sys/arch/arm/imx/imx51_ipuv3reg.h
540
#define DMFC_DP_CHAN_DEF_WM_EN_5F __BIT(9)
sys/arch/arm/imx/imx51_ipuv3reg.h
543
#define DMFC_DP_CHAN_DEF_WM_EN_5B __BIT(1)
sys/arch/arm/imx/imx51_ipuv3reg.h
545
#define DMFC_GENERAL1_WAIT4EOT_9 __BIT(24)
sys/arch/arm/imx/imx51_ipuv3reg.h
546
#define DMFC_GENERAL1_WAIT4EOT_6F __BIT(23)
sys/arch/arm/imx/imx51_ipuv3reg.h
547
#define DMFC_GENERAL1_WAIT4EOT_6B __BIT(22)
sys/arch/arm/imx/imx51_ipuv3reg.h
548
#define DMFC_GENERAL1_WAIT4EOT_5F __BIT(21)
sys/arch/arm/imx/imx51_ipuv3reg.h
549
#define DMFC_GENERAL1_WAIT4EOT_5B __BIT(20)
sys/arch/arm/imx/imx51_ipuv3reg.h
55
#define CM_CONF_DP_EN __BIT(5)
sys/arch/arm/imx/imx51_ipuv3reg.h
550
#define DMFC_GENERAL1_WAIT4EOT_4 __BIT(19)
sys/arch/arm/imx/imx51_ipuv3reg.h
551
#define DMFC_GENERAL1_WAIT4EOT_3 __BIT(18)
sys/arch/arm/imx/imx51_ipuv3reg.h
552
#define DMFC_GENERAL1_WAIT4EOT_2 __BIT(17)
sys/arch/arm/imx/imx51_ipuv3reg.h
553
#define DMFC_GENERAL1_WAIT4EOT_1 __BIT(16)
sys/arch/arm/imx/imx51_ipuv3reg.h
56
#define CM_CONF_ISP_EN __BIT(4)
sys/arch/arm/imx/imx51_ipuv3reg.h
57
#define CM_CONF_IRT_EN __BIT(3)
sys/arch/arm/imx/imx51_ipuv3reg.h
58
#define CM_CONF_IC_EN __BIT(2)
sys/arch/arm/imx/imx51_ipuv3reg.h
583
#define DMFC_DP_CHAN_DEF_ALT_WM_EN_6F_ALT __BIT(25)
sys/arch/arm/imx/imx51_ipuv3reg.h
586
#define DMFC_DP_CHAN_DEF_ALT_WM_EN_6B_ALT __BIT(17)
sys/arch/arm/imx/imx51_ipuv3reg.h
589
#define DMFC_DP_CHAN_DEF_ALT_WM_EN_5B_ALT __BIT(1)
sys/arch/arm/imx/imx51_ipuv3reg.h
59
#define CM_CONF_CSI1_EN __BIT(1)
sys/arch/arm/imx/imx51_ipuv3reg.h
591
#define DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT __BIT(23)
sys/arch/arm/imx/imx51_ipuv3reg.h
592
#define DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT __BIT(22)
sys/arch/arm/imx/imx51_ipuv3reg.h
593
#define DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT __BIT(20)
sys/arch/arm/imx/imx51_ipuv3reg.h
594
#define DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT __BIT(17)
sys/arch/arm/imx/imx51_ipuv3reg.h
596
#define DMFC_STAT_IC_BUFFER_EMPTY __BIT(25)
sys/arch/arm/imx/imx51_ipuv3reg.h
597
#define DMFC_STAT_IC_BUFFER_FULL __BIT(24)
sys/arch/arm/imx/imx51_ipuv3reg.h
598
#define DMFC_STAT_FIFO_EMPTY(n) __BIT(12 + (n))
sys/arch/arm/imx/imx51_ipuv3reg.h
599
#define DMFC_STAT_FIFO_FULL(n) __BIT((n))
sys/arch/arm/imx/imx51_ipuv3reg.h
60
#define CM_CONF_CSI0_EN __BIT(0)
sys/arch/arm/imx/imx51_ipuv3reg.h
613
#define DP_FG_EN_SYNC __BIT(0)
sys/arch/arm/imx/imx51_ipuv3reg.h
614
#define DP_DP_GWAM_SYNC __BIT(2)
sys/arch/arm/imx/imx51_ipuv3reg.h
98
#define CM_DISP_GEN_DI1_COUNTER_RELEASE __BIT(25)
sys/arch/arm/imx/imx51_ipuv3reg.h
99
#define CM_DISP_GEN_DI0_COUNTER_RELEASE __BIT(24)
sys/arch/arm/imx/imx51_tzic.c
241
const uint32_t oldipl_mask = __BIT(oldipl);
sys/arch/arm/imx/imx51_tzicreg.h
34
#define INTCNTL_NSEN_MASK __BIT(31)
sys/arch/arm/imx/imx51_tzicreg.h
35
#define INTCNTL_NSEN __BIT(16)
sys/arch/arm/imx/imx51_tzicreg.h
36
#define INTCNTL_EN __BIT(0)
sys/arch/arm/imx/imx51reg.h
179
#define USBCTRL_OWIR __BIT(31) /* OTG Wakeup interrupt request */
sys/arch/arm/imx/imx51reg.h
181
#define USBCTRL_OUIE __BIT(28) /* OTG Wake-up interrupt enable */
sys/arch/arm/imx/imx51reg.h
183
#define USBCTRL_OPM __BIT(24) /* OTG Power Mask */
sys/arch/arm/imx/imx51reg.h
184
#define USBCTRL_ICVOL __BIT(23) /* Host1 IC_USB voltage status */
sys/arch/arm/imx/imx51reg.h
185
#define USBCTRL_ICTPIE __BIT(19) /* IC USB TP interrupt enable */
sys/arch/arm/imx/imx51reg.h
186
#define USBCTRL_UBPCKE __BIT(18) /* Bypass clock enable */
sys/arch/arm/imx/imx51reg.h
187
#define USBCTRL_H1TCKOEN __BIT(17) /* Host1 ULPO PHY clock enable */
sys/arch/arm/imx/imx51reg.h
188
#define USBCTRL_ICTPC __BIT(16) /* Clear IC TP interrupt flag */
sys/arch/arm/imx/imx51reg.h
189
#define USBCTRL_H1WIR __BIT(15) /* Host1 wakeup interrupt request */
sys/arch/arm/imx/imx51reg.h
191
#define USBCTRL_H1UIE __BIT(12) /* Host1 ILPI interrupt enable */
sys/arch/arm/imx/imx51reg.h
192
#define USBCTRL_H1WIE __BIT(11) /* Host1 wakeup interrupt enable */
sys/arch/arm/imx/imx51reg.h
194
#define USBCTRL_H1PM __BIT(8) /* Host1 power mask */
sys/arch/arm/imx/imx51reg.h
195
#define USBCTRL_OHSTLL __BIT(7) /* OTG ULPI TLL enable */
sys/arch/arm/imx/imx51reg.h
196
#define USBCTRL_H1HSTLL __BIT(6) /* Host1 ULPI TLL enable */
sys/arch/arm/imx/imx51reg.h
197
#define USBCTRL_H1DISFSTTL __BIT(4) /* Host1 serial TLL disable */
sys/arch/arm/imx/imx51reg.h
198
#define USBCTRL_OTCKOEN __BIT(1) /* OTG ULPI PHY clock enable */
sys/arch/arm/imx/imx51reg.h
199
#define USBCTRL_BPE __BIT(0) /* Bypass enable */
sys/arch/arm/imx/imx51reg.h
202
#define PHYCTRL0_VLOAD __BIT(31)
sys/arch/arm/imx/imx51reg.h
204
#define PHYCTRL0_CONF2 __BIT(26)
sys/arch/arm/imx/imx51reg.h
205
#define PHYCTRL0_CONF3 __BIT(25)
sys/arch/arm/imx/imx51reg.h
206
#define PHYCTRL0_CHGRDETEN __BIT(24)
sys/arch/arm/imx/imx51reg.h
207
#define PHYCTRL0_CHGRDETON __BIT(23)
sys/arch/arm/imx/imx51reg.h
209
#define PHYCTRL0_SUSPENDM __BIT(12)
sys/arch/arm/imx/imx51reg.h
210
#define PHYCTRL0_RESET __BIT(11)
sys/arch/arm/imx/imx51reg.h
211
#define PHYCTRL0_UTMI_ON_CLOCK __BIT(10)
sys/arch/arm/imx/imx51reg.h
212
#define PHYCTRL0_OTG_OVER_CUR_POL __BIT(9)
sys/arch/arm/imx/imx51reg.h
213
#define PHYCTRL0_OTG_OVER_CUR_DIS __BIT(8)
sys/arch/arm/imx/imx51reg.h
214
#define PHYCTRL0_OTG_XCVR_CLK_SEL __BIT(7)
sys/arch/arm/imx/imx51reg.h
215
#define PHYCTRL0_H1_OVER_CUR_POL __BIT(6)
sys/arch/arm/imx/imx51reg.h
216
#define PHYCTRL0_H1_OVER_CUR_DIS __BIT(5)
sys/arch/arm/imx/imx51reg.h
217
#define PHYCTRL0_H1_XCVR_CLK_SEL __BIT(4)
sys/arch/arm/imx/imx51reg.h
218
#define PHYCTRL0_PWR_POL __BIT(3)
sys/arch/arm/imx/imx51reg.h
219
#define PHYCTRL0_CHRGDET __BIT(2)
sys/arch/arm/imx/imx51reg.h
220
#define PHYCTRL0_CHRGDET_INT_EN __BIT(1)
sys/arch/arm/imx/imx51reg.h
221
#define PHYCTRL0_CHRGDET_INT_FLG __BIT(0)
sys/arch/arm/imx/imx51reg.h
229
#define USBCTRL1_UH3_EXT_CLK_EN __BIT(27)
sys/arch/arm/imx/imx51reg.h
230
#define USBCTRL1_UH2_EXT_CLK_EN __BIT(26)
sys/arch/arm/imx/imx51reg.h
231
#define USBCTRL1_UH1_EXT_CLK_EN __BIT(25)
sys/arch/arm/imx/imx51reg.h
232
#define USBCTRL1_OTG_EXT_CLK_EN __BIT(24)
sys/arch/arm/imx/imx51reg.h
238
#define USB_CLKONOFF_CTRL_H1_AHBCLK_OFF __BIT(18)
sys/arch/arm/imx/imx51reg.h
239
#define USB_CLKONOFF_CTRL_OTG_AHBCLK_OFF __BIT(17)
sys/arch/arm/imx/imx51reg.h
281
#define IOMUX_CONFIG_SION __BIT(4)
sys/arch/arm/imx/imx51reg.h
291
#define PAD_CTL_HVE __BIT(13)
sys/arch/arm/imx/imx51reg.h
292
#define PAD_CTL_DDR_INPUT __BIT(9)
sys/arch/arm/imx/imx51reg.h
293
#define PAD_CTL_HYS __BIT(8)
sys/arch/arm/imx/imx51reg.h
294
#define PAD_CTL_PKE __BIT(7)
sys/arch/arm/imx/imx51reg.h
295
#define PAD_CTL_PUE __BIT(6)
sys/arch/arm/imx/imx51reg.h
303
#define PAD_CTL_ODE __BIT(3) /* opendrain */
sys/arch/arm/imx/imx51reg.h
309
#define PAD_CTL_SRE __BIT(0)
sys/arch/arm/imx/imxcspireg.h
42
#define CSPI_CON_SSPOL __BIT(7) /* SPI SS Polarity Select */
sys/arch/arm/imx/imxcspireg.h
43
#define CSPI_CON_SSCTL __BIT(6) /* In master mode, this bit
sys/arch/arm/imx/imxcspireg.h
47
#define CSPI_CON_PHA __BIT(5) /* PHA */
sys/arch/arm/imx/imxcspireg.h
48
#define CSPI_CON_POL __BIT(4) /* POL */
sys/arch/arm/imx/imxcspireg.h
49
#define CSPI_CON_SMC __BIT(3) /* SMC */
sys/arch/arm/imx/imxcspireg.h
50
#define CSPI_CON_XCH __BIT(2) /* XCH */
sys/arch/arm/imx/imxcspireg.h
51
#define CSPI_CON_MODE __BIT(1) /* MODE */
sys/arch/arm/imx/imxcspireg.h
52
#define CSPI_CON_ENABLE __BIT(0) /* EN */
sys/arch/arm/imx/imxcspireg.h
55
#define CSPI_IMX31_INTR_TC_EN __BIT(8) /* TX Complete */
sys/arch/arm/imx/imxcspireg.h
56
#define CSPI_IMX31_INTR_BO_EN __BIT(7) /* Bit Counter Overflow */
sys/arch/arm/imx/imxcspireg.h
57
#define CSPI_IMX35_INTR_TC_EN __BIT(7) /* TX Complete */
sys/arch/arm/imx/imxcspireg.h
58
#define CSPI_INTR_RO_EN __BIT(6) /* RXFIFO Overflow */
sys/arch/arm/imx/imxcspireg.h
59
#define CSPI_INTR_RF_EN __BIT(5) /* RXFIFO Full */
sys/arch/arm/imx/imxcspireg.h
60
#define CSPI_INTR_RH_EN __BIT(4) /* RXFIFO Half Full */
sys/arch/arm/imx/imxcspireg.h
61
#define CSPI_INTR_RR_EN __BIT(3) /* RXFIFO Ready */
sys/arch/arm/imx/imxcspireg.h
62
#define CSPI_INTR_TF_EN __BIT(2) /* TXFIFO Full */
sys/arch/arm/imx/imxcspireg.h
63
#define CSPI_INTR_TH_EN __BIT(1) /* TXFIFO Half Empty */
sys/arch/arm/imx/imxcspireg.h
64
#define CSPI_INTR_TE_EN __BIT(0) /* TXFIFO Empty */
sys/arch/arm/imx/imxcspireg.h
67
#define CSPI_IMX31_STAT_CLR_TC __BIT(8) /* Clear TC of status register */
sys/arch/arm/imx/imxcspireg.h
68
#define CSPI_IMX31_STAT_CLR_BO __BIT(7) /* Clear BO of status register */
sys/arch/arm/imx/imxcspireg.h
70
#define CSPI_IMX35_STAT_CLR_TC __BIT(7) /* Clear TC of status register */
sys/arch/arm/imx/imxcspireg.h
72
#define CSPI_STAT_RO __BIT(6) /* RXFIFO Overflow */
sys/arch/arm/imx/imxcspireg.h
73
#define CSPI_STAT_RF __BIT(5) /* RXFIFO Full */
sys/arch/arm/imx/imxcspireg.h
74
#define CSPI_STAT_RH __BIT(4) /* RXFIFO Half Full */
sys/arch/arm/imx/imxcspireg.h
75
#define CSPI_STAT_RR __BIT(3) /* RXFIFO Ready */
sys/arch/arm/imx/imxcspireg.h
76
#define CSPI_STAT_TF __BIT(2) /* TXFIFO Full */
sys/arch/arm/imx/imxcspireg.h
77
#define CSPI_STAT_TH __BIT(1) /* TXFIFO Half Empty */
sys/arch/arm/imx/imxcspireg.h
78
#define CSPI_STAT_TE __BIT(0) /* TXFIFO Empty */
sys/arch/arm/imx/imxecspireg.h
41
#define ECSPI_CON_SMC __BIT(3) /* SMC */
sys/arch/arm/imx/imxecspireg.h
42
#define ECSPI_CON_XCH __BIT(2) /* XCH */
sys/arch/arm/imx/imxecspireg.h
43
#define ECSPI_CON_HW __BIT(1) /* HW */
sys/arch/arm/imx/imxecspireg.h
44
#define ECSPI_CON_ENABLE __BIT(0) /* EN */
sys/arch/arm/imx/imxecspireg.h
55
#define ECSPI_INTR_TC_EN __BIT(7) /* TX Complete */
sys/arch/arm/imx/imxecspireg.h
56
#define ECSPI_INTR_RO_EN __BIT(6) /* RXFIFO Overflow */
sys/arch/arm/imx/imxecspireg.h
57
#define ECSPI_INTR_RF_EN __BIT(5) /* RXFIFO Full */
sys/arch/arm/imx/imxecspireg.h
58
#define ECSPI_INTR_RD_EN __BIT(4) /* RXFIFO Data Request */
sys/arch/arm/imx/imxecspireg.h
59
#define ECSPI_INTR_RR_EN __BIT(3) /* RXFIFO Ready */
sys/arch/arm/imx/imxecspireg.h
60
#define ECSPI_INTR_TF_EN __BIT(2) /* TXFIFO Full */
sys/arch/arm/imx/imxecspireg.h
61
#define ECSPI_INTR_TD_EN __BIT(1) /* TXFIFO Data Request */
sys/arch/arm/imx/imxecspireg.h
62
#define ECSPI_INTR_TE_EN __BIT(0) /* TXFIFO Empty */
sys/arch/arm/imx/imxecspireg.h
65
#define ECSPI_STAT_CLR_TC __BIT(7) /* Clear Transfer Completed */
sys/arch/arm/imx/imxecspireg.h
66
#define ECSPI_STAT_CLR_RO __BIT(6) /* Clear RXFIFO Overflow */
sys/arch/arm/imx/imxecspireg.h
68
#define ECSPI_STAT_RF __BIT(5)
sys/arch/arm/imx/imxecspireg.h
69
#define ECSPI_STAT_RDR __BIT(4)
sys/arch/arm/imx/imxecspireg.h
70
#define ECSPI_STAT_RR __BIT(3)
sys/arch/arm/imx/imxecspireg.h
71
#define ECSPI_STAT_TF __BIT(2)
sys/arch/arm/imx/imxecspireg.h
72
#define ECSPI_STAT_TDR __BIT(1)
sys/arch/arm/imx/imxecspireg.h
73
#define ECSPI_STAT_TE __BIT(0)
sys/arch/arm/imx/imxepitreg.h
31
#define EPITCR_EN __BIT(0)
sys/arch/arm/imx/imxepitreg.h
32
#define EPITCR_ENMOD __BIT(1)
sys/arch/arm/imx/imxepitreg.h
33
#define EPITCR_OCIEN __BIT(2)
sys/arch/arm/imx/imxepitreg.h
34
#define EPITCR_RLD __BIT(3)
sys/arch/arm/imx/imxepitreg.h
36
#define EPITCR_SWR __BIT(16)
sys/arch/arm/imx/imxepitreg.h
37
#define EPITCR_IOVW __BIT(17)
sys/arch/arm/imx/imxepitreg.h
38
#define EPITCR_DBGEN __BIT(18)
sys/arch/arm/imx/imxepitreg.h
39
#define EPITCR_WAITEN __BIT(19)
sys/arch/arm/imx/imxepitreg.h
40
#define EPITCR_DOZEN __BIT(20) /* not in iMX51 */
sys/arch/arm/imx/imxepitreg.h
41
#define EPITCR_STOPEN __BIT(21)
sys/arch/arm/imx/imxgpio.c
142
pending &= ~__BIT(irq);
sys/arch/arm/imx/imxgpio.c
180
uint32_t irq_mask = __BIT(is->is_irq);
sys/arch/arm/imx/imxgpio.c
234
val = __SHIFTOUT(GPIO_READ(gpio, GPIO_DR), __BIT(pin));
sys/arch/arm/imx/imxgpio.c
243
uint32_t mask = __BIT(pin);
sys/arch/arm/imx/imxgpio.c
265
uint32_t mask = __BIT(pin);
sys/arch/arm/imx/imxgpio.c
305
uint32_t mask = __BIT(pin);
sys/arch/arm/imx/imxkppreg.h
42
#define KPSR_KRIE __BIT(9)
sys/arch/arm/imx/imxkppreg.h
43
#define KPSR_KDIE __BIT(8)
sys/arch/arm/imx/imxkppreg.h
44
#define KPSR_KRSS __BIT(3)
sys/arch/arm/imx/imxkppreg.h
45
#define KPSR_KDSC __BIT(2)
sys/arch/arm/imx/imxkppreg.h
46
#define KPSR_KPKR __BIT(1)
sys/arch/arm/imx/imxkppreg.h
47
#define KPSR_KPKD __BIT(0)
sys/arch/arm/imx/imxpciereg.h
124
#define PCIE_PL_PFLR_FORCE_LINK __BIT(15)
sys/arch/arm/imx/imxpciereg.h
137
#define PCIE_PL_DEBUG1_XMLH_LINK_UP __BIT(4)
sys/arch/arm/imx/imxpciereg.h
138
#define PCIE_PL_DEBUG1_XMLH_LINK_IN_TRAINING __BIT(29)
sys/arch/arm/imx/imxpciereg.h
158
#define PCIE_PL_G2CR_DIRECTED_SPEED_CHANGE __BIT(17)
sys/arch/arm/imx/imxpciereg.h
161
#define PCIE_PL_PHY_STATUS_ACK __BIT(16)
sys/arch/arm/imx/imxpciereg.h
164
#define PCIE_PL_PHY_CTRL_RD __BIT(19)
sys/arch/arm/imx/imxpciereg.h
165
#define PCIE_PL_PHY_CTRL_WR __BIT(18)
sys/arch/arm/imx/imxpciereg.h
166
#define PCIE_PL_PHY_CTRL_CAP_DAT __BIT(17)
sys/arch/arm/imx/imxpciereg.h
167
#define PCIE_PL_PHY_CTRL_CAP_ADR __BIT(16)
sys/arch/arm/imx/imxpciereg.h
187
#define PCIE_PL_IATURC1_TD __BIT(8)
sys/arch/arm/imx/imxpciereg.h
197
#define PCIE_PL_IATURC2_REGION_ENABLE __BIT(31)
sys/arch/arm/imx/imxpciereg.h
223
#define ATEOVRD_EN __BIT(2)
sys/arch/arm/imx/imxpciereg.h
224
#define REF_USB2_EN __BIT(1)
sys/arch/arm/imx/imxpciereg.h
225
#define REF_CLKDIV2 __BIT(0)
sys/arch/arm/imx/imxpciereg.h
228
#define RES_ACK_IN_OVRD __BIT(15)
sys/arch/arm/imx/imxpciereg.h
229
#define RES_ACK_IN __BIT(14)
sys/arch/arm/imx/imxpciereg.h
230
#define RES_REQ_IN_OVRD __BIT(13)
sys/arch/arm/imx/imxpciereg.h
231
#define RES_REQ_IN __BIT(12)
sys/arch/arm/imx/imxpciereg.h
232
#define RTUNE_REQ_OVRD __BIT(11)
sys/arch/arm/imx/imxpciereg.h
233
#define RTUNE_REQ __BIT(10)
sys/arch/arm/imx/imxpciereg.h
234
#define MPLL_MULTIPLIER_OVRD __BIT(9)
sys/arch/arm/imx/imxpciereg.h
236
#define MPLL_EN_OVRD __BIT(1)
sys/arch/arm/imx/imxpciereg.h
237
#define MPLL_EN __BIT(0)
sys/arch/arm/imx/imxpciereg.h
269
#define PCIE_PHY_RX_OVRD_IN_LO_RX_PLL_EN_OVRD __BIT(3)
sys/arch/arm/imx/imxpciereg.h
270
#define PCIE_PHY_RX_OVRD_IN_LO_RX_DATA_EN_OVRD __BIT(5)
sys/arch/arm/imx/imxpciereg.h
279
#define PCIE_PHY_RX_ASIC_OUT_LOS __BIT(2)
sys/arch/arm/imx/imxpciereg.h
280
#define PCIE_PHY_RX_ASIC_OUT_PLL_STATE __BIT(1)
sys/arch/arm/imx/imxpciereg.h
281
#define PCIE_PHY_RX_ASIC_OUT_VALID __BIT(0)
sys/arch/arm/imx/imxpwmreg.h
34
#define PWM_CR_STOPEN __BIT(25)
sys/arch/arm/imx/imxpwmreg.h
35
#define PWM_CR_DOZEN __BIT(24)
sys/arch/arm/imx/imxpwmreg.h
36
#define PWM_CR_WAITEN __BIT(23)
sys/arch/arm/imx/imxpwmreg.h
37
#define PWM_CR_DBGEN __BIT(22)
sys/arch/arm/imx/imxpwmreg.h
38
#define PWM_CR_BCTR __BIT(21)
sys/arch/arm/imx/imxpwmreg.h
39
#define PWM_CR_HCTR __BIT(20)
sys/arch/arm/imx/imxpwmreg.h
46
#define PWM_CR_SWR __BIT(3)
sys/arch/arm/imx/imxpwmreg.h
48
#define PWM_CR_EN __BIT(0)
sys/arch/arm/imx/imxpwmreg.h
50
#define PWM_SR_FWE __BIT(6)
sys/arch/arm/imx/imxpwmreg.h
51
#define PWM_SR_CMP __BIT(5)
sys/arch/arm/imx/imxpwmreg.h
52
#define PWM_SR_ROV __BIT(4)
sys/arch/arm/imx/imxpwmreg.h
53
#define PWM_SR_FE __BIT(3)
sys/arch/arm/imx/imxpwmreg.h
56
#define PWM_IR_CIE __BIT(2)
sys/arch/arm/imx/imxpwmreg.h
57
#define PWM_IR_RIE __BIT(1)
sys/arch/arm/imx/imxpwmreg.h
58
#define PWM_IR_FIE __BIT(0)
sys/arch/arm/imx/imxsdmareg.h
52
#define SDMA_RESET_RESCHED __BIT(1)
sys/arch/arm/imx/imxsdmareg.h
53
#define SDMA_RESET_RESET __BIT(0)
sys/arch/arm/imx/imxsdmareg.h
82
#define ONCE_STAT_RCV __BIT(11)
sys/arch/arm/imx/imxsdmareg.h
83
#define ONCE_STAT_EDR __BIT(10)
sys/arch/arm/imx/imxsdmareg.h
84
#define ONCE_STAT_ODR __BIT(9)
sys/arch/arm/imx/imxsdmareg.h
85
#define ONCE_STAT_SWB __BIT(8)
sys/arch/arm/imx/imxsdmareg.h
86
#define ONCE_STAT_MST __BIT(7)
sys/arch/arm/imx/imxsnvsreg.h
43
#define SNVS_LPLR_GPR_HL __BIT(5)
sys/arch/arm/imx/imxsnvsreg.h
44
#define SNVS_LPLR_MC_HL __BIT(4)
sys/arch/arm/imx/imxsnvsreg.h
45
#define SNVS_LPLR_LPCALB_HL __BIT(3)
sys/arch/arm/imx/imxsnvsreg.h
46
#define SNVS_LPLR_SRTC_HL __BIT(2)
sys/arch/arm/imx/imxsnvsreg.h
48
#define SNVS_LPCR_PK_OVERRIDE __BIT(23)
sys/arch/arm/imx/imxsnvsreg.h
49
#define SNVS_LPCR_PK_EN __BIT(22)
sys/arch/arm/imx/imxsnvsreg.h
54
#define SNVS_LPCR_LPCALB_EN __BIT(8)
sys/arch/arm/imx/imxsnvsreg.h
55
#define SNVS_LPCR_PWR_GLITCH_EN __BIT(7)
sys/arch/arm/imx/imxsnvsreg.h
56
#define SNVS_LPCR_TOP __BIT(6)
sys/arch/arm/imx/imxsnvsreg.h
57
#define SNVS_LPCR_DP_EN __BIT(5)
sys/arch/arm/imx/imxsnvsreg.h
58
#define SNVS_LPCR_SRTC_INV_EN __BIT(4)
sys/arch/arm/imx/imxsnvsreg.h
59
#define SNVS_LPCR_LPWUI_EN __BIT(3)
sys/arch/arm/imx/imxsnvsreg.h
60
#define SNVS_LPCR_MC_ENV __BIT(2)
sys/arch/arm/imx/imxsnvsreg.h
61
#define SNVS_LPCR_LPTA_EN __BIT(1)
sys/arch/arm/imx/imxsnvsreg.h
62
#define SNVS_LPCR_SRTC_ENV __BIT(0)
sys/arch/arm/imx/imxsnvsreg.h
64
#define SNVS_LPSR_SPO __BIT(18)
sys/arch/arm/imx/imxsnvsreg.h
65
#define SNVS_LPSR_EO __BIT(17)
sys/arch/arm/imx/imxsnvsreg.h
66
#define SNVS_LPSR_MCR __BIT(2)
sys/arch/arm/imx/imxsnvsreg.h
67
#define SNVS_LPSR_SRTCR __BIT(1)
sys/arch/arm/imx/imxsnvsreg.h
68
#define SNVS_LPSR_LPTA __BIT(0)
sys/arch/arm/imx/imxspi.c
195
contrl |= __SHIFTIN(__BIT(slave), ECSPI_CON_MODE);
sys/arch/arm/imx/imxspi.c
199
config &= ~(__SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL) |
sys/arch/arm/imx/imxspi.c
200
__SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL) |
sys/arch/arm/imx/imxspi.c
201
__SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA));
sys/arch/arm/imx/imxspi.c
208
config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA);
sys/arch/arm/imx/imxspi.c
212
config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL);
sys/arch/arm/imx/imxspi.c
213
config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL);
sys/arch/arm/imx/imxspi.c
217
config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA);
sys/arch/arm/imx/imxspi.c
218
config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL);
sys/arch/arm/imx/imxspi.c
219
config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL);
sys/arch/arm/imx/imxspi.c
224
config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SSB_CTL);
sys/arch/arm/imx/imxssireg.h
36
#define SCR_CLK_IST __BIT(9)
sys/arch/arm/imx/imxssireg.h
37
#define SCR_TCH_EN __BIT(8)
sys/arch/arm/imx/imxssireg.h
38
#define SCR_SYS_CLK_EN __BIT(7)
sys/arch/arm/imx/imxssireg.h
44
#define SCR_SYN __BIT(4)
sys/arch/arm/imx/imxssireg.h
45
#define SCR_NET __BIT(3)
sys/arch/arm/imx/imxssireg.h
46
#define SCR_RE __BIT(2)
sys/arch/arm/imx/imxssireg.h
47
#define SCR_TE __BIT(1)
sys/arch/arm/imx/imxssireg.h
48
#define SCR_SSIEN __BIT(0)
sys/arch/arm/imx/imxssireg.h
51
#define SI_RDMAE __BIT(22)
sys/arch/arm/imx/imxssireg.h
52
#define SI_RIE __BIT(21)
sys/arch/arm/imx/imxssireg.h
53
#define SI_TDMAE __BIT(20)
sys/arch/arm/imx/imxssireg.h
54
#define SI_TIE __BIT(19)
sys/arch/arm/imx/imxssireg.h
55
#define SI_CMDAU_EN __BIT(18)
sys/arch/arm/imx/imxssireg.h
56
#define SI_CMDDU_EN __BIT(17)
sys/arch/arm/imx/imxssireg.h
57
#define SI_RXT_EN __BIT(16)
sys/arch/arm/imx/imxssireg.h
58
#define SI_RDR1_EN __BIT(15)
sys/arch/arm/imx/imxssireg.h
59
#define SI_RDR0_EN __BIT(14)
sys/arch/arm/imx/imxssireg.h
60
#define SI_TDE1_EN __BIT(13)
sys/arch/arm/imx/imxssireg.h
61
#define SI_TDE0_EN __BIT(12)
sys/arch/arm/imx/imxssireg.h
62
#define SI_ROE1_EN __BIT(11)
sys/arch/arm/imx/imxssireg.h
63
#define SI_ROE0_EN __BIT(10)
sys/arch/arm/imx/imxssireg.h
64
#define SI_TUE1_EN __BIT(9)
sys/arch/arm/imx/imxssireg.h
65
#define SI_TUE0_EN __BIT(8)
sys/arch/arm/imx/imxssireg.h
66
#define SI_RFS_EN __BIT(7)
sys/arch/arm/imx/imxssireg.h
67
#define SI_TFS_EN __BIT(6)
sys/arch/arm/imx/imxssireg.h
68
#define SI_RLS_EN __BIT(5)
sys/arch/arm/imx/imxssireg.h
69
#define SI_TLS_EN __BIT(4)
sys/arch/arm/imx/imxssireg.h
70
#define SI_RFF1_EN __BIT(3)
sys/arch/arm/imx/imxssireg.h
71
#define SI_RFF0_EN __BIT(2)
sys/arch/arm/imx/imxssireg.h
72
#define SI_TFE1_EN __BIT(1)
sys/arch/arm/imx/imxssireg.h
73
#define SI_TFE0_EN __BIT(0)
sys/arch/arm/imx/imxssireg.h
76
#define CR_XEX __BIT(10)
sys/arch/arm/imx/imxssireg.h
77
#define CR_XBIT __BIT(9)
sys/arch/arm/imx/imxssireg.h
78
#define CR_FEN1 __BIT(8)
sys/arch/arm/imx/imxssireg.h
79
#define CR_FEN0 __BIT(7)
sys/arch/arm/imx/imxssireg.h
80
#define CR_FDIR __BIT(6)
sys/arch/arm/imx/imxssireg.h
81
#define CR_XDIR __BIT(5)
sys/arch/arm/imx/imxssireg.h
82
#define CR_SHFD __BIT(4)
sys/arch/arm/imx/imxssireg.h
85
#define CR_SCKP __BIT(3)
sys/arch/arm/imx/imxssireg.h
86
#define CR_FSI __BIT(2)
sys/arch/arm/imx/imxssireg.h
87
#define CR_FSL __BIT(1)
sys/arch/arm/imx/imxssireg.h
88
#define CR_EFS __BIT(0)
sys/arch/arm/imx/imxuartreg.h
103
#define IMX_UCR2_SRST __BIT(0) /* rw */
sys/arch/arm/imx/imxuartreg.h
104
#define IMX_UCR2_RXEN __BIT(1) /* rw */
sys/arch/arm/imx/imxuartreg.h
105
#define IMX_UCR2_TXEN __BIT(2) /* rw */
sys/arch/arm/imx/imxuartreg.h
106
#define IMX_UCR2_ATEN __BIT(3) /* rw */
sys/arch/arm/imx/imxuartreg.h
107
#define IMX_UCR2_RTSEN __BIT(4) /* rw */
sys/arch/arm/imx/imxuartreg.h
108
#define IMX_UCR2_WS __BIT(5) /* rw */
sys/arch/arm/imx/imxuartreg.h
109
#define IMX_UCR2_STPB __BIT(6) /* rw */
sys/arch/arm/imx/imxuartreg.h
110
#define IMX_UCR2_PROE __BIT(7) /* rw */
sys/arch/arm/imx/imxuartreg.h
111
#define IMX_UCR2_PREN __BIT(8) /* rw */
sys/arch/arm/imx/imxuartreg.h
113
#define IMX_UCR2_ESCEN __BIT(11) /* rw */
sys/arch/arm/imx/imxuartreg.h
114
#define IMX_UCR2_CTS __BIT(12) /* rw */
sys/arch/arm/imx/imxuartreg.h
115
#define IMX_UCR2_CTSC __BIT(13) /* rw */
sys/arch/arm/imx/imxuartreg.h
116
#define IMX_UCR2_IRTS __BIT(14) /* rw */
sys/arch/arm/imx/imxuartreg.h
117
#define IMX_UCR2_ESCI __BIT(15) /* rw */
sys/arch/arm/imx/imxuartreg.h
122
#define IMX_UCR3_ACIEN __BIT(0) /* rw */
sys/arch/arm/imx/imxuartreg.h
123
#define IMX_UCR3_INVT __BIT(1) /* rw */
sys/arch/arm/imx/imxuartreg.h
124
#define IMX_UCR3_RXDMUXSEL __BIT(2) /* rw */
sys/arch/arm/imx/imxuartreg.h
125
#define IMX_UCR3_DTRDEN __BIT(3) /* rw */
sys/arch/arm/imx/imxuartreg.h
126
#define IMX_UCR3_AWAKEN __BIT(4) /* rw */
sys/arch/arm/imx/imxuartreg.h
127
#define IMX_UCR3_AIRINTEN __BIT(5) /* rw */
sys/arch/arm/imx/imxuartreg.h
128
#define IMX_UCR3_RXDSEN __BIT(6) /* rw */
sys/arch/arm/imx/imxuartreg.h
129
#define IMX_UCR3_ADNIMP __BIT(7) /* rw */
sys/arch/arm/imx/imxuartreg.h
130
#define IMX_UCR3_RI __BIT(8) /* rw */
sys/arch/arm/imx/imxuartreg.h
131
#define IMX_UCR3_DCD __BIT(9) /* rw */
sys/arch/arm/imx/imxuartreg.h
132
#define IMX_UCR3_DSR __BIT(10) /* rw */
sys/arch/arm/imx/imxuartreg.h
133
#define IMX_UCR3_FRAERREN __BIT(11) /* rw */
sys/arch/arm/imx/imxuartreg.h
134
#define IMX_UCR3_PARERREN __BIT(12) /* rw */
sys/arch/arm/imx/imxuartreg.h
135
#define IMX_UCR3_DTREN __BIT(13) /* rw */
sys/arch/arm/imx/imxuartreg.h
141
#define IMX_UCR4_DREN __BIT(0) /* rw */
sys/arch/arm/imx/imxuartreg.h
142
#define IMX_UCR4_OREN __BIT(1) /* rw */
sys/arch/arm/imx/imxuartreg.h
143
#define IMX_UCR4_BKEN __BIT(2) /* rw */
sys/arch/arm/imx/imxuartreg.h
144
#define IMX_UCR4_TCEN __BIT(3) /* rw */
sys/arch/arm/imx/imxuartreg.h
145
#define IMX_UCR4_LPBYP __BIT(4) /* rw */
sys/arch/arm/imx/imxuartreg.h
146
#define IMX_UCR4_IRSC __BIT(5) /* rw */
sys/arch/arm/imx/imxuartreg.h
147
#define IMX_UCR4_IDDMAEN __BIT(6) /* rw */
sys/arch/arm/imx/imxuartreg.h
148
#define IMX_UCR4_WKEN __BIT(7) /* rw */
sys/arch/arm/imx/imxuartreg.h
149
#define IMX_UCR4_ENIRI __BIT(8) /* rw */
sys/arch/arm/imx/imxuartreg.h
150
#define IMX_UCR4_INVR __BIT(9) /* rw */
sys/arch/arm/imx/imxuartreg.h
158
#define IMX_UFCR_DCEDTE __BIT(6) /* rw */
sys/arch/arm/imx/imxuartreg.h
171
#define IMX_USR1_AWAKE __BIT(4) /* w1c */
sys/arch/arm/imx/imxuartreg.h
172
#define IMX_USR1_AIRINT __BIT(5) /* w1c */
sys/arch/arm/imx/imxuartreg.h
173
#define IMX_USR1_RXDS __BIT(6) /* ro */
sys/arch/arm/imx/imxuartreg.h
174
#define IMX_USR1_DTRD __BIT(7) /* w1c */
sys/arch/arm/imx/imxuartreg.h
175
#define IMX_USR1_AGTIM __BIT(8) /* w1c */
sys/arch/arm/imx/imxuartreg.h
176
#define IMX_USR1_RRDY __BIT(9) /* ro */
sys/arch/arm/imx/imxuartreg.h
177
#define IMX_USR1_FRAMERR __BIT(10) /* w1c */
sys/arch/arm/imx/imxuartreg.h
178
#define IMX_USR1_ESCF __BIT(11) /* w1c */
sys/arch/arm/imx/imxuartreg.h
179
#define IMX_USR1_RTSD __BIT(12) /* w1c */
sys/arch/arm/imx/imxuartreg.h
180
#define IMX_USR1_TRDY __BIT(13) /* ro */
sys/arch/arm/imx/imxuartreg.h
181
#define IMX_USR1_RTSS __BIT(14) /* ro */
sys/arch/arm/imx/imxuartreg.h
182
#define IMX_USR1_PARITYERR __BIT(15) /* w1c */
sys/arch/arm/imx/imxuartreg.h
187
#define IMX_USR2_RDR __BIT(0)
sys/arch/arm/imx/imxuartreg.h
188
#define IMX_USR2_ORE __BIT(1) /* w1c */
sys/arch/arm/imx/imxuartreg.h
189
#define IMX_USR2_BRCD __BIT(2) /* w1c */
sys/arch/arm/imx/imxuartreg.h
190
#define IMX_USR2_TXDC __BIT(3) /* ro */
sys/arch/arm/imx/imxuartreg.h
191
#define IMX_USR2_RTSF __BIT(4) /* w1c */
sys/arch/arm/imx/imxuartreg.h
192
#define IMX_USR2_DCDIN __BIT(5) /* ro */
sys/arch/arm/imx/imxuartreg.h
193
#define IMX_USR2_DCDDELT __BIT(6) /* rw */
sys/arch/arm/imx/imxuartreg.h
194
#define IMX_USR2_WAKE __BIT(7) /* w1c */
sys/arch/arm/imx/imxuartreg.h
195
#define IMX_USR2_IRINT __BIT(8) /* rw */
sys/arch/arm/imx/imxuartreg.h
196
#define IMX_USR2_RIIN __BIT(9) /* ro */
sys/arch/arm/imx/imxuartreg.h
197
#define IMX_USR2_RIDELT __BIT(10) /* w1c */
sys/arch/arm/imx/imxuartreg.h
198
#define IMX_USR2_ACST __BIT(11) /* rw */
sys/arch/arm/imx/imxuartreg.h
199
#define IMX_USR2_IDLE __BIT(12) /* w1c */
sys/arch/arm/imx/imxuartreg.h
200
#define IMX_USR2_DTRF __BIT(13) /* rw */
sys/arch/arm/imx/imxuartreg.h
201
#define IMX_USR2_TXFE __BIT(14) /* ro */
sys/arch/arm/imx/imxuartreg.h
202
#define IMX_USR2_ADET __BIT(15) /* w1c */
sys/arch/arm/imx/imxuartreg.h
239
#define IMX_UTS_SOFTRST __BIT(0) /* rw */
sys/arch/arm/imx/imxuartreg.h
241
#define IMX_UTS_RXFULL __BIT(3) /* rw */
sys/arch/arm/imx/imxuartreg.h
242
#define IMX_UTS_TXFUL __BIT(4) /* rw */
sys/arch/arm/imx/imxuartreg.h
243
#define IMX_UTS_RXEMPTY __BIT(5) /* rw */
sys/arch/arm/imx/imxuartreg.h
244
#define IMX_UTS_TXEMPTY __BIT(5) /* rw */
sys/arch/arm/imx/imxuartreg.h
246
#define IMX_UTS_RXDBG __BIT(9) /* rw */
sys/arch/arm/imx/imxuartreg.h
247
#define IMX_UTS_LOOPIR __BIT(10) /* rw */
sys/arch/arm/imx/imxuartreg.h
248
#define IMX_UTS_DBGEN __BIT(11) /* rw */
sys/arch/arm/imx/imxuartreg.h
249
#define IMX_UTS_LOOP __BIT(12) /* rw */
sys/arch/arm/imx/imxuartreg.h
250
#define IMX_UTS_FRCPERR __BIT(13) /* rw */
sys/arch/arm/imx/imxuartreg.h
68
#define IMX_URXD_PRERR __BIT(10) /* ro */
sys/arch/arm/imx/imxuartreg.h
69
#define IMX_URXD_BRK __BIT(11) /* ro */
sys/arch/arm/imx/imxuartreg.h
70
#define IMX_URXD_FRMERR __BIT(12) /* ro */
sys/arch/arm/imx/imxuartreg.h
71
#define IMX_URXD_OVRRUN __BIT(13) /* ro */
sys/arch/arm/imx/imxuartreg.h
72
#define IMX_URXD_ERR __BIT(14) /* ro */
sys/arch/arm/imx/imxuartreg.h
73
#define IMX_URXD_CHARDY __BIT(15) /* ro */
sys/arch/arm/imx/imxuartreg.h
84
#define IMX_UCR1_UARTEN __BIT(0) /* rw */
sys/arch/arm/imx/imxuartreg.h
85
#define IMX_UCR1_DOZE __BIT(1) /* rw */
sys/arch/arm/imx/imxuartreg.h
86
#define IMX_UCR1_ATDMAEN __BIT(2) /* rw */
sys/arch/arm/imx/imxuartreg.h
87
#define IMX_UCR1_TXDMAEN __BIT(3) /* rw */
sys/arch/arm/imx/imxuartreg.h
88
#define IMX_UCR1_SNDBRK __BIT(4) /* rw */
sys/arch/arm/imx/imxuartreg.h
89
#define IMX_UCR1_RTSDEN __BIT(5) /* rw */
sys/arch/arm/imx/imxuartreg.h
90
#define IMX_UCR1_TXMPTYEN __BIT(6) /* rw */
sys/arch/arm/imx/imxuartreg.h
91
#define IMX_UCR1_IREN __BIT(7) /* rw */
sys/arch/arm/imx/imxuartreg.h
92
#define IMX_UCR1_RXDMAEN __BIT(8) /* rw */
sys/arch/arm/imx/imxuartreg.h
93
#define IMX_UCR1_RRDYEN __BIT(9) /* rw */
sys/arch/arm/imx/imxuartreg.h
95
#define IMX_UCR1_IDEN __BIT(12) /* rw */
sys/arch/arm/imx/imxuartreg.h
96
#define IMX_UCR1_TRDYEN __BIT(13) /* rw */
sys/arch/arm/imx/imxuartreg.h
97
#define IMX_UCR1_ADBR __BIT(14) /* rw */
sys/arch/arm/imx/imxuartreg.h
98
#define IMX_UCR1_ADEN __BIT(15) /* rw */
sys/arch/arm/imx/imxuartvar.h
117
#define IMXUART_PEND_PARAM __BIT(0)
sys/arch/arm/imx/imxuartvar.h
118
#define IMXUART_PEND_SPEED __BIT(1)
sys/arch/arm/imx/imxuartvar.h
71
#define IMXUART_HW_FLOW __BIT(0)
sys/arch/arm/imx/imxuartvar.h
72
#define IMXUART_HW_DEV_OK __BIT(1)
sys/arch/arm/imx/imxuartvar.h
73
#define IMXUART_HW_CONSOLE __BIT(2)
sys/arch/arm/imx/imxuartvar.h
74
#define IMXUART_HW_KGDB __BIT(3)
sys/arch/arm/imx/imxuartvar.h
81
#define IMXUART_RX_TTY_BLOCKED __BIT(0)
sys/arch/arm/imx/imxuartvar.h
82
#define IMXUART_RX_TTY_OVERFLOWED __BIT(1)
sys/arch/arm/imx/imxuartvar.h
83
#define IMXUART_RX_IBUF_BLOCKED __BIT(2)
sys/arch/arm/imx/imxuartvar.h
84
#define IMXUART_RX_IBUF_OVERFLOWED __BIT(3)
sys/arch/arm/imx/imxusbreg.h
102
#define PORTSC_PTS2 __BIT(25) /* iMX6,7 */
sys/arch/arm/imx/imxusbreg.h
104
#define PORTSC_STS __BIT(29) /* serial transceiver select */
sys/arch/arm/imx/imxusbreg.h
105
#define PORTSC_PTW __BIT(28) /* parallel transceiver width */
sys/arch/arm/imx/imxusbreg.h
109
#define PORTSC_PFSC __BIT(24) /* port force full speed */
sys/arch/arm/imx/imxusbreg.h
110
#define PORTSC_PHCD __BIT(23) /* PHY low power suspend */
sys/arch/arm/imx/imxusbreg.h
36
#define HWHOST_HC __BIT(0)
sys/arch/arm/imx/imxusbreg.h
39
#define HWDEVICE_DC __BIT(0)
sys/arch/arm/imx/imxusbreg.h
47
#define ULPI_WU __BIT(31)
sys/arch/arm/imx/imxusbreg.h
48
#define ULPI_RUN __BIT(30)
sys/arch/arm/imx/imxusbreg.h
49
#define ULPI_RW __BIT(29)
sys/arch/arm/imx/imxusbreg.h
50
#define ULPI_SS __BIT(27)
sys/arch/arm/imx/imxusbreg.h
57
#define OTGSC_DPIE __BIT(30)
sys/arch/arm/imx/imxusbreg.h
58
#define OTGSC_1MSE __BIT(29)
sys/arch/arm/imx/imxusbreg.h
59
#define OTGSC_BSEIE __BIT(28)
sys/arch/arm/imx/imxusbreg.h
60
#define OTGSC_BSVIE __BIT(27)
sys/arch/arm/imx/imxusbreg.h
61
#define OTGSC_ASVIE __BIT(26)
sys/arch/arm/imx/imxusbreg.h
62
#define OTGSC_AVVIE __BIT(25)
sys/arch/arm/imx/imxusbreg.h
63
#define OTGSC_IDIE __BIT(24)
sys/arch/arm/imx/imxusbreg.h
64
#define OTGSC_DPIS __BIT(22)
sys/arch/arm/imx/imxusbreg.h
65
#define OTGSC_1MSS __BIT(21)
sys/arch/arm/imx/imxusbreg.h
66
#define OTGSC_BSEIS __BIT(20)
sys/arch/arm/imx/imxusbreg.h
67
#define OTGSC_BSVIS __BIT(19)
sys/arch/arm/imx/imxusbreg.h
68
#define OTGSC_ASVIS __BIT(18)
sys/arch/arm/imx/imxusbreg.h
69
#define OTGSC_AVVIS __BIT(17)
sys/arch/arm/imx/imxusbreg.h
70
#define OTGSC_IDIS __BIT(16)
sys/arch/arm/imx/imxusbreg.h
71
#define OTGSC_DPS __BIT(14)
sys/arch/arm/imx/imxusbreg.h
72
#define OTGSC_1MST __BIT(13)
sys/arch/arm/imx/imxusbreg.h
73
#define OTGSC_BSE __BIT(12)
sys/arch/arm/imx/imxusbreg.h
74
#define OTGSC_BSV __BIT(11)
sys/arch/arm/imx/imxusbreg.h
75
#define OTGSC_ASV __BIT(10)
sys/arch/arm/imx/imxusbreg.h
76
#define OTGSC_AVV __BIT( 9)
sys/arch/arm/imx/imxusbreg.h
77
#define OTGSC_ID __BIT( 8)
sys/arch/arm/imx/imxusbreg.h
78
#define OTGSC_IDPU __BIT( 5)
sys/arch/arm/imx/imxusbreg.h
79
#define OTGSC_DP __BIT( 4)
sys/arch/arm/imx/imxusbreg.h
80
#define OTGSC_OT __BIT( 3)
sys/arch/arm/imx/imxusbreg.h
81
#define OTGSC_VC __BIT( 1)
sys/arch/arm/imx/imxusbreg.h
82
#define OTGSC_VD __BIT( 0)
sys/arch/arm/imx/imxusbreg.h
84
#define USBMODE_VBPS __BIT(5) /* Vbus power selectt */
sys/arch/arm/imx/imxusbreg.h
85
#define USBMODE_SDIS __BIT(4) /* Stream disable mode 1=act */
sys/arch/arm/imx/imxusbreg.h
86
#define USBMODE_SLOM __BIT(3) /* setup lockouts on */
sys/arch/arm/imx/imxusbreg.h
87
#define USBMODE_ES __BIT(2) /* Endian Select ES=1 */
sys/arch/arm/imx/imxwdogreg.h
57
#define WCR_WDZST __BIT(0) /* watchdog low power */
sys/arch/arm/imx/imxwdogreg.h
58
#define WCR_WDBG __BIT(1) /* watchdog debug enable */
sys/arch/arm/imx/imxwdogreg.h
59
#define WCR_WDE __BIT(2) /* watchdog enable */
sys/arch/arm/imx/imxwdogreg.h
60
#define WCR_WDT __BIT(3) /* timeout assertion */
sys/arch/arm/imx/imxwdogreg.h
61
#define WCR_SRS __BIT(4) /* software reset signal */
sys/arch/arm/imx/imxwdogreg.h
62
#define WCR_WDA __BIT(5) /* ipp_wdog* assertion */
sys/arch/arm/imx/imxwdogreg.h
63
#define WCR_WDW __BIT(7) /* disable for wait */
sys/arch/arm/imx/imxwdogreg.h
73
#define WRSR_SFTW __BIT(0) /* reset is the result of a
sys/arch/arm/imx/imxwdogreg.h
75
#define WRSR_TOUT __BIT(1) /* reset is the result of a
sys/arch/arm/imx/imxwdogreg.h
78
#define WRSR_CMON __BIT(2)
sys/arch/arm/imx/imxwdogreg.h
79
#define WRSR_EXT __BIT(3)
sys/arch/arm/imx/imxwdogreg.h
80
#define WRSR_JRST __BIT(5)
sys/arch/arm/imx/imxwdogreg.h
82
#define WRSR_PWR __BIT(4)
sys/arch/arm/imx/imxwdogreg.h
87
#define WICR_WTIS __BIT(14) /* interrupt status [w1c] */
sys/arch/arm/imx/imxwdogreg.h
88
#define WICR_WIE __BIT(15) /* interrupt enable */
sys/arch/arm/imx/imxwdogreg.h
92
#define WMCR_PDE __BIT(0) /* power down enable */
sys/arch/arm/include/armreg.h
274
#define PJ4B_AUXCTL_FW __BIT(0) /* Cache and TLB updates broadcast */
sys/arch/arm/include/armreg.h
275
#define PJ4B_AUXCTL_SMPNAMP __BIT(6) /* 0 = AMP, 1 = SMP */
sys/arch/arm/include/armreg.h
276
#define PJ4B_AUXCTL_L1PARITY __BIT(9) /* L1 parity checking */
sys/arch/arm/include/armreg.h
279
#define PJ4B_AUXFMC0_L2EN __BIT(0) /* Tightly-Coupled L2 cache enable */
sys/arch/arm/include/armreg.h
280
#define PJ4B_AUXFMC0_SMPNAMP __BIT(1) /* 0 = AMP, 1 = SMP */
sys/arch/arm/include/armreg.h
281
#define PJ4B_AUXFMC0_L1PARITY __BIT(2) /* alias of PJ4B_AUXCTL_L1PARITY */
sys/arch/arm/include/armreg.h
282
#define PJ4B_AUXFMC0_DCSLFD __BIT(2) /* Disable DC Speculative linefill */
sys/arch/arm/include/armreg.h
283
#define PJ4B_AUXFMC0_FW __BIT(8) /* alias of PJ4B_AUXCTL_FW*/
sys/arch/arm/include/armreg.h
286
#define CORTEXA5_ACTLR_FW __BIT(0)
sys/arch/arm/include/armreg.h
287
#define CORTEXA5_ACTLR_SMP __BIT(6) /* Inner Cache Shared is cacheable */
sys/arch/arm/include/armreg.h
288
#define CORTEXA5_ACTLR_EXCL __BIT(7) /* Exclusive L1/L2 cache control */
sys/arch/arm/include/armreg.h
291
#define CORTEXA7_ACTLR_L1ALIAS __BIT(0) /* Enables L1 cache alias checks */
sys/arch/arm/include/armreg.h
292
#define CORTEXA7_ACTLR_L2EN __BIT(1) /* Enables L2 cache */
sys/arch/arm/include/armreg.h
293
#define CORTEXA7_ACTLR_SMP __BIT(6) /* SMP */
sys/arch/arm/include/armreg.h
296
#define CORTEXA8_ACTLR_L1ALIAS __BIT(0) /* Enables L1 cache alias checks */
sys/arch/arm/include/armreg.h
297
#define CORTEXA8_ACTLR_L2EN __BIT(1) /* Enables L2 cache */
sys/arch/arm/include/armreg.h
310
#define CORTEXA15_ACTLR_BTB __BIT(0) /* Cache and TLB updates broadcast */
sys/arch/arm/include/armreg.h
311
#define CORTEXA15_ACTLR_SMP __BIT(6) /* SMP */
sys/arch/arm/include/armreg.h
312
#define CORTEXA15_ACTLR_IOBEU __BIT(15) /* In order issue in Branch Exec Unit */
sys/arch/arm/include/armreg.h
313
#define CORTEXA15_ACTLR_SDEH __BIT(31) /* snoop-delayed exclusive handling */
sys/arch/arm/include/armreg.h
316
#define CORTEXA17_ACTLR_SMP __BIT(6) /* SMP */
sys/arch/arm/include/armreg.h
317
#define CORTEXA17_ACTLR_ASSE __BIT(3) /* ACE STREX Signaling Enable */
sys/arch/arm/include/armreg.h
318
#define CORTEXA17_ACTLR_L2PF __BIT(2) /* Enable L2 prefetch */
sys/arch/arm/include/armreg.h
319
#define CORTEXA17_ACTLR_L1PF __BIT(1) /* Enable L1 prefetch */
sys/arch/arm/include/armreg.h
445
#define ARM11_PMCCTL_E __BIT(0) /* enable all three counters */
sys/arch/arm/include/armreg.h
446
#define ARM11_PMCCTL_P __BIT(1) /* reset both Count Registers to zero */
sys/arch/arm/include/armreg.h
447
#define ARM11_PMCCTL_C __BIT(2) /* reset the Cycle Counter Register to zero */
sys/arch/arm/include/armreg.h
448
#define ARM11_PMCCTL_D __BIT(3) /* cycle count divide by 64 */
sys/arch/arm/include/armreg.h
449
#define ARM11_PMCCTL_EC0 __BIT(4) /* Enable Counter Register 0 interrupt */
sys/arch/arm/include/armreg.h
450
#define ARM11_PMCCTL_EC1 __BIT(5) /* Enable Counter Register 1 interrupt */
sys/arch/arm/include/armreg.h
451
#define ARM11_PMCCTL_ECC __BIT(6) /* Enable Cycle Counter interrupt */
sys/arch/arm/include/armreg.h
452
#define ARM11_PMCCTL_SBZa __BIT(7) /* UNP/SBZ */
sys/arch/arm/include/armreg.h
453
#define ARM11_PMCCTL_CR0 __BIT(8) /* Count Register 0 overflow flag */
sys/arch/arm/include/armreg.h
454
#define ARM11_PMCCTL_CR1 __BIT(9) /* Count Register 1 overflow flag */
sys/arch/arm/include/armreg.h
455
#define ARM11_PMCCTL_CCR __BIT(10) /* Cycle Count Register overflow flag */
sys/arch/arm/include/armreg.h
456
#define ARM11_PMCCTL_X __BIT(11) /* Enable Export of the events to the event bus */
sys/arch/arm/include/armreg.h
490
#define PMCR_D __BIT(3)
sys/arch/arm/include/armreg.h
491
#define PMCR_E __BIT(0)
sys/arch/arm/include/armreg.h
494
#define PMINTEN_C __BIT(31)
sys/arch/arm/include/armreg.h
496
#define PMCNTEN_C __BIT(31)
sys/arch/arm/include/armreg.h
500
#define PMOVS_C __BIT(31)
sys/arch/arm/include/armreg.h
504
#define PMEVTYPER_P __BIT(31)
sys/arch/arm/include/armreg.h
505
#define PMEVTYPER_U __BIT(30)
sys/arch/arm/include/armreg.h
509
#define CORTEX_CNTENS_C __BIT(31) /* Enables the cycle counter */
sys/arch/arm/include/armreg.h
510
#define CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */
sys/arch/arm/include/armreg.h
511
#define CORTEX_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */
sys/arch/arm/include/armreg.h
515
#define L2CTRL_ICPRES __BIT(23) // Interrupt Controller is present
sys/arch/arm/include/armreg.h
518
#define TTBR_C __BIT(0) /* without MPE */
sys/arch/arm/include/armreg.h
519
#define TTBR_S __BIT(1)
sys/arch/arm/include/armreg.h
520
#define TTBR_IMP __BIT(2)
sys/arch/arm/include/armreg.h
526
#define TTBR_NOS __BIT(5)
sys/arch/arm/include/armreg.h
527
#define TTBR_IRGN_MASK (__BIT(6) | __BIT(0))
sys/arch/arm/include/armreg.h
529
#define TTBR_IRGN_WBWA __BIT(6)
sys/arch/arm/include/armreg.h
530
#define TTBR_IRGN_WT __BIT(0)
sys/arch/arm/include/armreg.h
531
#define TTBR_IRGN_WBNWA (__BIT(0) | __BIT(6))
sys/arch/arm/include/armreg.h
534
#define TTBCR_S_EAE __BIT(31) // Extended Address Extension
sys/arch/arm/include/armreg.h
535
#define TTBCR_S_PD1 __BIT(5) // Don't use TTBR1
sys/arch/arm/include/armreg.h
536
#define TTBCR_S_PD0 __BIT(4) // Don't use TTBR0
sys/arch/arm/include/armreg.h
539
#define TTBCR_L_EAE __BIT(31) // Extended Address Extension
sys/arch/arm/include/armreg.h
543
#define TTBCR_L_EPD1 __BIT(23) // Don't use TTBR1
sys/arch/arm/include/armreg.h
544
#define TTBCR_L_A1 __BIT(22) // ASID is in TTBR1
sys/arch/arm/include/armreg.h
549
#define TTBCR_L_EPD0 __BIT(7) // Don't use TTBR0
sys/arch/arm/include/armreg.h
559
#define PRRR_NS1 __BIT(19) // Normal Shareable S=1 is Shareable
sys/arch/arm/include/armreg.h
560
#define PRRR_NS0 __BIT(18) // Normal Shareable S=0 is Shareable
sys/arch/arm/include/armreg.h
561
#define PRRR_DS1 __BIT(17) // Device Shareable S=1 is Shareable
sys/arch/arm/include/armreg.h
562
#define PRRR_DS0 __BIT(16) // Device Shareable S=0 is Shareable
sys/arch/arm/include/armreg.h
570
#define MPIDR_MP __BIT(31) /* 1 = Have MP Extension */
sys/arch/arm/include/armreg.h
571
#define MPIDR_U __BIT(30) /* 1 = Uni-Processor System */
sys/arch/arm/include/armreg.h
572
#define MPIDR_MT __BIT(24) /* 1 = SMT(AFF0 is logical) */
sys/arch/arm/include/armreg.h
591
#define CNTCTL_ISTATUS __BIT(2) // Interrupt is pending
sys/arch/arm/include/armreg.h
592
#define CNTCTL_IMASK __BIT(1) // Mask Interrupt
sys/arch/arm/include/armreg.h
593
#define CNTCTL_ENABLE __BIT(0) // Timer Enabled
sys/arch/arm/include/armreg.h
595
#define CNTKCTL_PL0PTEN __BIT(9) /* PL0 Physical Timer Enable */
sys/arch/arm/include/armreg.h
596
#define CNTKCTL_PL0VTEN __BIT(8) /* PL0 Virtual Timer Enable */
sys/arch/arm/include/armreg.h
598
#define CNTKCTL_EVNTDIR __BIT(3) /* CNTVCT Event Dir (1->0) */
sys/arch/arm/include/armreg.h
599
#define CNTKCTL_EVNTEN __BIT(2) /* CNTVCT Event Enable */
sys/arch/arm/include/armreg.h
600
#define CNTKCTL_PL0VCTEN __BIT(1) /* PL0 Virtual Counter Enable */
sys/arch/arm/include/armreg.h
601
#define CNTKCTL_PL0PCTEN __BIT(0) /* PL0 Physical Counter Enable */
sys/arch/arm/include/armreg.h
605
#define CNTHCTL_EVNTDIR __BIT(3)
sys/arch/arm/include/armreg.h
606
#define CNTHCTL_EVNTEN __BIT(2)
sys/arch/arm/include/armreg.h
607
#define CNTHCTL_PL1PCEN __BIT(1)
sys/arch/arm/include/armreg.h
608
#define CNTHCTL_PL1PCTEN __BIT(0)
sys/arch/arm/include/armreg.h
612
#define ARM_A5_TLBDATA_NS_WALK __BIT(55)
sys/arch/arm/include/armreg.h
613
#define ARM_A5_TLBDATA_NS_PAGE __BIT(54)
sys/arch/arm/include/armreg.h
614
#define ARM_A5_TLBDATA_XN __BIT(53)
sys/arch/arm/include/armreg.h
616
#define ARM_A5_TLBDATA_B __BIT(49)
sys/arch/arm/include/armreg.h
617
#define ARM_A5_TLBDATA_C __BIT(48)
sys/arch/arm/include/armreg.h
618
#define ARM_A5_TLBDATA_S __BIT(47)
sys/arch/arm/include/armreg.h
627
#define ARM_A5_TLBDATA_nG __BIT(1)
sys/arch/arm/include/armreg.h
628
#define ARM_A5_TLBDATA_VALID __BIT(0)
sys/arch/arm/include/armreg.h
642
#define ARM_A7_TLBDATA2_S2OVR __BIT(75-64)
sys/arch/arm/include/armreg.h
656
#define ARM_A7_TLBDATA2_XN2 __BIT(71-64)
sys/arch/arm/include/armreg.h
657
#define ARM_A7_TLBDATA2_XN1 __BIT(70-64)
sys/arch/arm/include/armreg.h
658
#define ARM_A7_TLBDATA2_PXN __BIT(69-64)
sys/arch/arm/include/armreg.h
662
#define ARM_A7_TLBDATA1_NS __BIT(40-32)
sys/arch/arm/include/armreg.h
665
#define ARM_A7_TLBDATA1_nG __BIT(34-32)
sys/arch/arm/include/armreg.h
671
#define ARM_A7_TLBDATA0_NS_WALK __BIT(4)
sys/arch/arm/include/armreg.h
682
#define ARM_TLBDATA_VALID __BIT(0)
sys/arch/arm/include/armreg.h
684
#define ARM_TLBDATAOP_WAY __BIT(31)
sys/arch/arm/marvell/armadaxp.c
623
irq_mask &= ~__BIT(n);
sys/arch/arm/marvell/armadaxp.c
638
irq_mask &= ~__BIT(n);
sys/arch/arm/marvell/armadaxpreg.h
371
#define L2_AUX_FLUSH_ON_POWERDOWN __BIT(3)
sys/arch/arm/marvell/armadaxpreg.h
372
#define L2_AUX_ECC_ENABLE __BIT(20)
sys/arch/arm/marvell/armadaxpreg.h
373
#define L2_AUX_PARITY_ENABLE __BIT(21)
sys/arch/arm/marvell/armadaxpreg.h
374
#define L2_AUX_INVAL_UCE __BIT(22)
sys/arch/arm/marvell/mvsoc_intr.c
82
const uint32_t oldipl_mask = __BIT(oldipl);
sys/arch/arm/nvidia/tegra124_car.c
1547
rst->mask = __BIT(reset_id % 32);
sys/arch/arm/nvidia/tegra124_carreg.h
100
#define CAR_PLLU_BASE_CLKENABLE_HSIC __BIT(22)
sys/arch/arm/nvidia/tegra124_carreg.h
101
#define CAR_PLLU_BASE_CLKENABLE_USB __BIT(21)
sys/arch/arm/nvidia/tegra124_carreg.h
102
#define CAR_PLLU_BASE_VCO_FREQ __BIT(20)
sys/arch/arm/nvidia/tegra124_carreg.h
107
#define CAR_PLLD_BASE_BYPASS __BIT(31)
sys/arch/arm/nvidia/tegra124_carreg.h
108
#define CAR_PLLD_BASE_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra124_carreg.h
109
#define CAR_PLLD_BASE_REF_DIS __BIT(29)
sys/arch/arm/nvidia/tegra124_carreg.h
110
#define CAR_PLLD_BASE_LOCK __BIT(27)
sys/arch/arm/nvidia/tegra124_carreg.h
111
#define CAR_PLLD_BASE_CLKENABLE_CSI __BIT(26)
sys/arch/arm/nvidia/tegra124_carreg.h
112
#define CAR_PLLD_BASE_DSIA_CLK_SRC __BIT(25)
sys/arch/arm/nvidia/tegra124_carreg.h
113
#define CAR_PLLD_BASE_CSI_CLK_SRC __BIT(23)
sys/arch/arm/nvidia/tegra124_carreg.h
121
#define CAR_PLLX_BASE_BYPASS __BIT(31)
sys/arch/arm/nvidia/tegra124_carreg.h
122
#define CAR_PLLX_BASE_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra124_carreg.h
123
#define CAR_PLLX_BASE_REF_DIS __BIT(29)
sys/arch/arm/nvidia/tegra124_carreg.h
124
#define CAR_PLLX_BASE_LOCK __BIT(27)
sys/arch/arm/nvidia/tegra124_carreg.h
130
#define CAR_PLLX_MISC_FO_LP_DISABLE __BIT(29)
sys/arch/arm/nvidia/tegra124_carreg.h
131
#define CAR_PLLX_MISC_FO_G_DISABLE __BIT(28)
sys/arch/arm/nvidia/tegra124_carreg.h
133
#define CAR_PLLX_MISC_LOCK_ENABLE __BIT(18)
sys/arch/arm/nvidia/tegra124_carreg.h
136
#define CAR_PLLE_BASE_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra124_carreg.h
137
#define CAR_PLLE_BASE_LOCK_OVERRIDE __BIT(29)
sys/arch/arm/nvidia/tegra124_carreg.h
138
#define CAR_PLLE_BASE_FDIV48 __BIT(28)
sys/arch/arm/nvidia/tegra124_carreg.h
145
#define CAR_PLLE_MISC_IDDQ_SWCTL __BIT(14)
sys/arch/arm/nvidia/tegra124_carreg.h
146
#define CAR_PLLE_MISC_IDDQ_OVERRIDE __BIT(13)
sys/arch/arm/nvidia/tegra124_carreg.h
147
#define CAR_PLLE_MISC_LOCK __BIT(11)
sys/arch/arm/nvidia/tegra124_carreg.h
148
#define CAR_PLLE_MISC_LOCK_ENABLE __BIT(9)
sys/arch/arm/nvidia/tegra124_carreg.h
151
#define CAR_PLLD2_BASE_BYPASS __BIT(31)
sys/arch/arm/nvidia/tegra124_carreg.h
152
#define CAR_PLLD2_BASE_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra124_carreg.h
153
#define CAR_PLLD2_BASE_REF_DIS __BIT(29)
sys/arch/arm/nvidia/tegra124_carreg.h
154
#define CAR_PLLD2_BASE_FREQLOCK __BIT(28)
sys/arch/arm/nvidia/tegra124_carreg.h
155
#define CAR_PLLD2_BASE_LOCK __BIT(27)
sys/arch/arm/nvidia/tegra124_carreg.h
159
#define CAR_PLLD2_BASE_LOCK_OVERRIDE __BIT(24)
sys/arch/arm/nvidia/tegra124_carreg.h
161
#define CAR_PLLD2_BASE_IDDQ __BIT(19)
sys/arch/arm/nvidia/tegra124_carreg.h
162
#define CAR_PLLD2_BASE_PTS __BIT(16)
sys/arch/arm/nvidia/tegra124_carreg.h
167
#define CAR_PLLD2_MISC_EN_FSTLCK __BIT(31)
sys/arch/arm/nvidia/tegra124_carreg.h
168
#define CAR_PLLD2_MISC_LOCK_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra124_carreg.h
171
#define CAR_PLLD2_MISC_KVCO __BIT(24)
sys/arch/arm/nvidia/tegra124_carreg.h
218
#define CAR_CLKSRC_UART_DIV_ENB __BIT(24)
sys/arch/arm/nvidia/tegra124_carreg.h
295
#define CAR_DEV_L_CACHE2 __BIT(31)
sys/arch/arm/nvidia/tegra124_carreg.h
296
#define CAR_DEV_L_I2S0 __BIT(30)
sys/arch/arm/nvidia/tegra124_carreg.h
297
#define CAR_DEV_L_VCP __BIT(29)
sys/arch/arm/nvidia/tegra124_carreg.h
298
#define CAR_DEV_L_HOST1X __BIT(28)
sys/arch/arm/nvidia/tegra124_carreg.h
299
#define CAR_DEV_L_DISP1 __BIT(27)
sys/arch/arm/nvidia/tegra124_carreg.h
300
#define CAR_DEV_L_DISP2 __BIT(26)
sys/arch/arm/nvidia/tegra124_carreg.h
301
#define CAR_DEV_L_ISP __BIT(23)
sys/arch/arm/nvidia/tegra124_carreg.h
302
#define CAR_DEV_L_USBD __BIT(22)
sys/arch/arm/nvidia/tegra124_carreg.h
303
#define CAR_DEV_L_VI __BIT(20)
sys/arch/arm/nvidia/tegra124_carreg.h
304
#define CAR_DEV_L_I2S2 __BIT(18)
sys/arch/arm/nvidia/tegra124_carreg.h
305
#define CAR_DEV_L_PWM __BIT(17)
sys/arch/arm/nvidia/tegra124_carreg.h
306
#define CAR_DEV_L_SDMMC4 __BIT(15)
sys/arch/arm/nvidia/tegra124_carreg.h
307
#define CAR_DEV_L_SDMMC1 __BIT(14)
sys/arch/arm/nvidia/tegra124_carreg.h
308
#define CAR_DEV_L_I2C1 __BIT(12)
sys/arch/arm/nvidia/tegra124_carreg.h
309
#define CAR_DEV_L_I2S1 __BIT(11)
sys/arch/arm/nvidia/tegra124_carreg.h
310
#define CAR_DEV_L_SPDIF __BIT(10)
sys/arch/arm/nvidia/tegra124_carreg.h
311
#define CAR_DEV_L_SDMMC2 __BIT(9)
sys/arch/arm/nvidia/tegra124_carreg.h
312
#define CAR_DEV_L_GPIO __BIT(8)
sys/arch/arm/nvidia/tegra124_carreg.h
313
#define CAR_DEV_L_UARTB __BIT(7)
sys/arch/arm/nvidia/tegra124_carreg.h
314
#define CAR_DEV_L_UARTA __BIT(6)
sys/arch/arm/nvidia/tegra124_carreg.h
315
#define CAR_DEV_L_TMR __BIT(5
sys/arch/arm/nvidia/tegra124_carreg.h
316
#define CAR_DEV_L_RTC __BIT(4)
sys/arch/arm/nvidia/tegra124_carreg.h
317
#define CAR_DEV_L_ISPB __BIT(3)
sys/arch/arm/nvidia/tegra124_carreg.h
318
#define CAR_DEV_L_CPU __BIT(0)
sys/arch/arm/nvidia/tegra124_carreg.h
320
#define CAR_DEV_U_XUSB_DEV __BIT(31)
sys/arch/arm/nvidia/tegra124_carreg.h
321
#define CAR_DEV_U_DEV1_OUT __BIT(30)
sys/arch/arm/nvidia/tegra124_carreg.h
322
#define CAR_DEV_U_DEV2_OUT __BIT(29)
sys/arch/arm/nvidia/tegra124_carreg.h
323
#define CAR_DEV_U_SUS_OUT __BIT(28)
sys/arch/arm/nvidia/tegra124_carreg.h
324
#define CAR_DEV_U_MSENC __BIT(27)
sys/arch/arm/nvidia/tegra124_carreg.h
325
#define CAR_DEV_U_XUSB_HOST __BIT(25)
sys/arch/arm/nvidia/tegra124_carreg.h
326
#define CAR_DEV_U_CRAM2 __BIT(24)
sys/arch/arm/nvidia/tegra124_carreg.h
327
#define CAR_DEV_U_IRAMD __BIT(23)
sys/arch/arm/nvidia/tegra124_carreg.h
328
#define CAR_DEV_U_IRAMC __BIT(22)
sys/arch/arm/nvidia/tegra124_carreg.h
329
#define CAR_DEV_U_IRAMB __BIT(21)
sys/arch/arm/nvidia/tegra124_carreg.h
330
#define CAR_DEV_U_IRAMA __BIT(20)
sys/arch/arm/nvidia/tegra124_carreg.h
331
#define CAR_DEV_U_TSEC __BIT(19)
sys/arch/arm/nvidia/tegra124_carreg.h
332
#define CAR_DEV_U_DSIB __BIT(18)
sys/arch/arm/nvidia/tegra124_carreg.h
333
#define CAR_DEV_U_I2C_SLOW __BIT(17)
sys/arch/arm/nvidia/tegra124_carreg.h
334
#define CAR_DEV_U_DTV __BIT(15)
sys/arch/arm/nvidia/tegra124_carreg.h
335
#define CAR_DEV_U_SOC_THERM __BIT(14)
sys/arch/arm/nvidia/tegra124_carreg.h
336
#define CAR_DEV_U_TRACECLKIN __BIT(13)
sys/arch/arm/nvidia/tegra124_carreg.h
337
#define CAR_DEV_U_AVPUCQ __BIT(11)
sys/arch/arm/nvidia/tegra124_carreg.h
338
#define CAR_DEV_U_CSITE __BIT(9)
sys/arch/arm/nvidia/tegra124_carreg.h
339
#define CAR_DEV_U_AFI __BIT(8)
sys/arch/arm/nvidia/tegra124_carreg.h
340
#define CAR_DEV_U_OWR __BIT(7)
sys/arch/arm/nvidia/tegra124_carreg.h
341
#define CAR_DEV_U_PCIE __BIT(6)
sys/arch/arm/nvidia/tegra124_carreg.h
342
#define CAR_DEV_U_SDMMC3 __BIT(5)
sys/arch/arm/nvidia/tegra124_carreg.h
343
#define CAR_DEV_U_SPI4 __BIT(4)
sys/arch/arm/nvidia/tegra124_carreg.h
344
#define CAR_DEV_U_I2C3 __BIT(3)
sys/arch/arm/nvidia/tegra124_carreg.h
345
#define CAR_DEV_U_UARTD __BIT(1)
sys/arch/arm/nvidia/tegra124_carreg.h
347
#define CAR_DEV_H_BSEV __BIT(31)
sys/arch/arm/nvidia/tegra124_carreg.h
348
#define CAR_DEV_H_BSEA __BIT(30)
sys/arch/arm/nvidia/tegra124_carreg.h
349
#define CAR_DEV_H_VDE __BIT(29)
sys/arch/arm/nvidia/tegra124_carreg.h
35
#define CAR_RST_SOURCE_WDT_EN __BIT(5)
sys/arch/arm/nvidia/tegra124_carreg.h
350
#define CAR_DEV_H_USB3 __BIT(27)
sys/arch/arm/nvidia/tegra124_carreg.h
351
#define CAR_DEV_H_USB2 __BIT(26)
sys/arch/arm/nvidia/tegra124_carreg.h
352
#define CAR_DEV_H_EMC __BIT(25)
sys/arch/arm/nvidia/tegra124_carreg.h
353
#define CAR_DEV_H_MIPI_CAL __BIT(24)
sys/arch/arm/nvidia/tegra124_carreg.h
354
#define CAR_DEV_H_UARTC __BIT(23)
sys/arch/arm/nvidia/tegra124_carreg.h
355
#define CAR_DEV_H_I2C2 __BIT(22)
sys/arch/arm/nvidia/tegra124_carreg.h
356
#define CAR_DEV_H_CSI __BIT(20)
sys/arch/arm/nvidia/tegra124_carreg.h
357
#define CAR_DEV_H_HDMI __BIT(19)
sys/arch/arm/nvidia/tegra124_carreg.h
358
#define CAR_DEV_H_HSI __BIT(18)
sys/arch/arm/nvidia/tegra124_carreg.h
359
#define CAR_DEV_H_DSI __BIT(16)
sys/arch/arm/nvidia/tegra124_carreg.h
36
#define CAR_RST_SOURCE_WDT_SEL __BIT(4)
sys/arch/arm/nvidia/tegra124_carreg.h
360
#define CAR_DEV_H_I2C5 __BIT(15)
sys/arch/arm/nvidia/tegra124_carreg.h
361
#define CAR_DEV_H_SPI3 __BIT(14)
sys/arch/arm/nvidia/tegra124_carreg.h
362
#define CAR_DEV_H_SPI2 __BIT(12)
sys/arch/arm/nvidia/tegra124_carreg.h
363
#define CAR_DEV_H_JTAG2TBC __BIT(11)
sys/arch/arm/nvidia/tegra124_carreg.h
364
#define CAR_DEV_H_SNOR __BIT(10)
sys/arch/arm/nvidia/tegra124_carreg.h
365
#define CAR_DEV_H_SPI1 __BIT(9)
sys/arch/arm/nvidia/tegra124_carreg.h
366
#define CAR_DEV_H_KFUSE __BIT(8)
sys/arch/arm/nvidia/tegra124_carreg.h
367
#define CAR_DEV_H_FUSE __BIT(7)
sys/arch/arm/nvidia/tegra124_carreg.h
368
#define CAR_DEV_H_PMC __BIT(6)
sys/arch/arm/nvidia/tegra124_carreg.h
369
#define CAR_DEV_H_STAT_MON __BIT(5)
sys/arch/arm/nvidia/tegra124_carreg.h
37
#define CAR_RST_SOURCE_WDT_SYS_RST_EN __BIT(2)
sys/arch/arm/nvidia/tegra124_carreg.h
370
#define CAR_DEV_H_KBC __BIT(4)
sys/arch/arm/nvidia/tegra124_carreg.h
371
#define CAR_DEV_H_APBDMA __BIT(2)
sys/arch/arm/nvidia/tegra124_carreg.h
372
#define CAR_DEV_H_AHBDMA __BIT(1)
sys/arch/arm/nvidia/tegra124_carreg.h
373
#define CAR_DEV_H_MEM __BIT(0)
sys/arch/arm/nvidia/tegra124_carreg.h
375
#define CAR_DEV_V_HDA __BIT(29)
sys/arch/arm/nvidia/tegra124_carreg.h
376
#define CAR_DEV_V_SATA __BIT(28)
sys/arch/arm/nvidia/tegra124_carreg.h
377
#define CAR_DEV_V_SATA_OOB __BIT(27)
sys/arch/arm/nvidia/tegra124_carreg.h
378
#define CAR_DEV_V_ACTMON __BIT(23)
sys/arch/arm/nvidia/tegra124_carreg.h
379
#define CAR_DEV_V_ATOMICS __BIT(16)
sys/arch/arm/nvidia/tegra124_carreg.h
38
#define CAR_RST_SOURCE_WDT_COP_RST_EN __BIT(1)
sys/arch/arm/nvidia/tegra124_carreg.h
380
#define CAR_DEV_V_HDA2CODEC_2X __BIT(15)
sys/arch/arm/nvidia/tegra124_carreg.h
381
#define CAR_DEV_V_DAM2 __BIT(14)
sys/arch/arm/nvidia/tegra124_carreg.h
382
#define CAR_DEV_V_DAM1 __BIT(13)
sys/arch/arm/nvidia/tegra124_carreg.h
383
#define CAR_DEV_V_DAM0 __BIT(12)
sys/arch/arm/nvidia/tegra124_carreg.h
384
#define CAR_DEV_V_APBIF __BIT(11)
sys/arch/arm/nvidia/tegra124_carreg.h
385
#define CAR_DEV_V_AUDIO __BIT(10)
sys/arch/arm/nvidia/tegra124_carreg.h
386
#define CAR_DEV_V_SPI6 __BIT(9)
sys/arch/arm/nvidia/tegra124_carreg.h
387
#define CAR_DEV_V_SPI5 __BIT(8)
sys/arch/arm/nvidia/tegra124_carreg.h
388
#define CAR_DEV_V_I2C4 __BIT(7)
sys/arch/arm/nvidia/tegra124_carreg.h
389
#define CAR_DEV_V_I2S4 __BIT(6)
sys/arch/arm/nvidia/tegra124_carreg.h
39
#define CAR_RST_SOURCE_WDT_CPU_RST_EN __BIT(0)
sys/arch/arm/nvidia/tegra124_carreg.h
390
#define CAR_DEV_V_I2S3 __BIT(5)
sys/arch/arm/nvidia/tegra124_carreg.h
391
#define CAR_DEV_V_TSENSOR __BIT(4)
sys/arch/arm/nvidia/tegra124_carreg.h
392
#define CAR_DEV_V_MSELECT __BIT(3)
sys/arch/arm/nvidia/tegra124_carreg.h
393
#define CAR_DEV_V_CPULP __BIT(1)
sys/arch/arm/nvidia/tegra124_carreg.h
394
#define CAR_DEV_V_CPUG __BIT(0)
sys/arch/arm/nvidia/tegra124_carreg.h
396
#define CAR_DEV_W_XUSB_SS __BIT(28)
sys/arch/arm/nvidia/tegra124_carreg.h
397
#define CAR_DEV_W_DVFS __BIT(27)
sys/arch/arm/nvidia/tegra124_carreg.h
398
#define CAR_DEV_W_ADX0 __BIT(26)
sys/arch/arm/nvidia/tegra124_carreg.h
399
#define CAR_DEV_W_AMX0 __BIT(25)
sys/arch/arm/nvidia/tegra124_carreg.h
400
#define CAR_DEV_W_ENTROPY __BIT(21)
sys/arch/arm/nvidia/tegra124_carreg.h
401
#define CAR_DEV_W_XUSB __BIT(15)
sys/arch/arm/nvidia/tegra124_carreg.h
402
#define CAR_DEV_W_XUSB_PADCTL __BIT(14)
sys/arch/arm/nvidia/tegra124_carreg.h
403
#define CAR_DEV_W_CEC __BIT(8)
sys/arch/arm/nvidia/tegra124_carreg.h
404
#define CAR_DEV_W_SATACOLD __BIT(1)
sys/arch/arm/nvidia/tegra124_carreg.h
405
#define CAR_DEV_W_HDA2HDMICODEC __BIT(0)
sys/arch/arm/nvidia/tegra124_carreg.h
407
#define CAR_DEV_X_AMX1 __BIT(25)
sys/arch/arm/nvidia/tegra124_carreg.h
408
#define CAR_DEV_X_GPU __BIT(24)
sys/arch/arm/nvidia/tegra124_carreg.h
409
#define CAR_DEV_X_SOR0 __BIT(22)
sys/arch/arm/nvidia/tegra124_carreg.h
410
#define CAR_DEV_X_DPAUX __BIT(21)
sys/arch/arm/nvidia/tegra124_carreg.h
411
#define CAR_DEV_X_ADX1 __BIT(20)
sys/arch/arm/nvidia/tegra124_carreg.h
412
#define CAR_DEV_X_VIC __BIT(18)
sys/arch/arm/nvidia/tegra124_carreg.h
413
#define CAR_DEV_X_CLK72MHZ __BIT(17)
sys/arch/arm/nvidia/tegra124_carreg.h
414
#define CAR_DEV_X_HDMI_AUDIO __BIT(16)
sys/arch/arm/nvidia/tegra124_carreg.h
415
#define CAR_DEV_X_EMC_DLL __BIT(14)
sys/arch/arm/nvidia/tegra124_carreg.h
416
#define CAR_DEV_X_VIM2_CLK __BIT(11)
sys/arch/arm/nvidia/tegra124_carreg.h
417
#define CAR_DEV_X_I2C6 __BIT(6)
sys/arch/arm/nvidia/tegra124_carreg.h
418
#define CAR_DEV_X_CAM_MCLK2 __BIT(5)
sys/arch/arm/nvidia/tegra124_carreg.h
419
#define CAR_DEV_X_CAM_MCLK __BIT(4)
sys/arch/arm/nvidia/tegra124_carreg.h
420
#define CAR_DEV_X_SPARE __BIT(0)
sys/arch/arm/nvidia/tegra124_carreg.h
463
#define CAR_CLKSRC_SATA_AUX_CLK_ENB __BIT(24)
sys/arch/arm/nvidia/tegra124_carreg.h
480
#define CAR_UTMIP_PLL_CFG1_PLLU_POWERUP __BIT(17)
sys/arch/arm/nvidia/tegra124_carreg.h
481
#define CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN __BIT(16)
sys/arch/arm/nvidia/tegra124_carreg.h
482
#define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP __BIT(15)
sys/arch/arm/nvidia/tegra124_carreg.h
483
#define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN __BIT(14)
sys/arch/arm/nvidia/tegra124_carreg.h
489
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP __BIT(5)
sys/arch/arm/nvidia/tegra124_carreg.h
49
#define CAR_PLLP_BASE_BYPASS __BIT(31)
sys/arch/arm/nvidia/tegra124_carreg.h
490
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN __BIT(4)
sys/arch/arm/nvidia/tegra124_carreg.h
491
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP __BIT(3)
sys/arch/arm/nvidia/tegra124_carreg.h
492
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN __BIT(2)
sys/arch/arm/nvidia/tegra124_carreg.h
493
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP __BIT(1)
sys/arch/arm/nvidia/tegra124_carreg.h
494
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN __BIT(0)
sys/arch/arm/nvidia/tegra124_carreg.h
497
#define CAR_PLLE_AUX_SS_SEQ_INCLUDE __BIT(31)
sys/arch/arm/nvidia/tegra124_carreg.h
498
#define CAR_PLLE_AUX_REF_SEL_PLLREFE __BIT(28)
sys/arch/arm/nvidia/tegra124_carreg.h
50
#define CAR_PLLP_BASE_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra124_carreg.h
500
#define CAR_PLLE_AUX_SEQ_START_STATE __BIT(25)
sys/arch/arm/nvidia/tegra124_carreg.h
501
#define CAR_PLLE_AUX_SEQ_ENABLE __BIT(24)
sys/arch/arm/nvidia/tegra124_carreg.h
504
#define CAR_PLLE_AUX_FAST_PT __BIT(7)
sys/arch/arm/nvidia/tegra124_carreg.h
505
#define CAR_PLLE_AUX_SS_SWCTL __BIT(6)
sys/arch/arm/nvidia/tegra124_carreg.h
506
#define CAR_PLLE_AUX_CONFIG_SWCTL __BIT(5)
sys/arch/arm/nvidia/tegra124_carreg.h
507
#define CAR_PLLE_AUX_ENABLE_SWCTL __BIT(4)
sys/arch/arm/nvidia/tegra124_carreg.h
508
#define CAR_PLLE_AUX_USE_LOCKDET __BIT(3)
sys/arch/arm/nvidia/tegra124_carreg.h
509
#define CAR_PLLE_AUX_REF_SRC __BIT(2)
sys/arch/arm/nvidia/tegra124_carreg.h
51
#define CAR_PLLP_BASE_REF_DIS __BIT(29)
sys/arch/arm/nvidia/tegra124_carreg.h
510
#define CAR_PLLE_AUX_CML1_OEN __BIT(1)
sys/arch/arm/nvidia/tegra124_carreg.h
511
#define CAR_PLLE_AUX_CML0_OEN __BIT(0)
sys/arch/arm/nvidia/tegra124_carreg.h
515
#define CAR_SATA_PLL_CFG0_SEQ_START_STATE __BIT(25)
sys/arch/arm/nvidia/tegra124_carreg.h
516
#define CAR_SATA_PLL_CFG0_SEQ_ENABLE __BIT(24)
sys/arch/arm/nvidia/tegra124_carreg.h
517
#define CAR_SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE __BIT(7)
sys/arch/arm/nvidia/tegra124_carreg.h
518
#define CAR_SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE __BIT(6)
sys/arch/arm/nvidia/tegra124_carreg.h
519
#define CAR_SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5)
sys/arch/arm/nvidia/tegra124_carreg.h
52
#define CAR_PLLP_BASE_OVERRIDE __BIT(28)
sys/arch/arm/nvidia/tegra124_carreg.h
520
#define CAR_SATA_PLL_CFG0_SEQ_IN_SWCTL __BIT(4)
sys/arch/arm/nvidia/tegra124_carreg.h
521
#define CAR_SATA_PLL_CFG0_PADPLL_USE_LOCKDET __BIT(2)
sys/arch/arm/nvidia/tegra124_carreg.h
522
#define CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE __BIT(1)
sys/arch/arm/nvidia/tegra124_carreg.h
523
#define CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL __BIT(0)
sys/arch/arm/nvidia/tegra124_carreg.h
53
#define CAR_PLLP_BASE_LOCK __BIT(27)
sys/arch/arm/nvidia/tegra124_carreg.h
532
#define CAR_PLLREFE_BASE_BYPASS __BIT(31)
sys/arch/arm/nvidia/tegra124_carreg.h
533
#define CAR_PLLREFE_BASE_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra124_carreg.h
534
#define CAR_PLLREFE_BASE_REF_DIS __BIT(29)
sys/arch/arm/nvidia/tegra124_carreg.h
536
#define CAR_PLLREFE_BASE_KVCO __BIT(26)
sys/arch/arm/nvidia/tegra124_carreg.h
542
#define CAR_PLLREFE_MISC_LOCK_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra124_carreg.h
543
#define CAR_PLLREFE_MISC_LOCK_OVERRIDE __BIT(29)
sys/arch/arm/nvidia/tegra124_carreg.h
544
#define CAR_PLLREFE_MISC_LOCK __BIT(24)
sys/arch/arm/nvidia/tegra124_carreg.h
545
#define CAR_PLLREFE_MISC_IDDQ __BIT(16)
sys/arch/arm/nvidia/tegra124_carreg.h
549
#define CAR_XUSBIO_PLL_CFG0_SEQ_START_STATE __BIT(25)
sys/arch/arm/nvidia/tegra124_carreg.h
550
#define CAR_XUSBIO_PLL_CFG0_SEQ_ENABLE __BIT(24)
sys/arch/arm/nvidia/tegra124_carreg.h
551
#define CAR_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET __BIT(6)
sys/arch/arm/nvidia/tegra124_carreg.h
552
#define CAR_XUSBIO_PLL_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5)
sys/arch/arm/nvidia/tegra124_carreg.h
553
#define CAR_XUSBIO_PLL_CFG0_SEQ_IN_SWCTL __BIT(4)
sys/arch/arm/nvidia/tegra124_carreg.h
554
#define CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_OVERRIDE __BIT(3)
sys/arch/arm/nvidia/tegra124_carreg.h
555
#define CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL __BIT(2)
sys/arch/arm/nvidia/tegra124_carreg.h
556
#define CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE __BIT(1)
sys/arch/arm/nvidia/tegra124_carreg.h
557
#define CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL __BIT(0)
sys/arch/arm/nvidia/tegra124_carreg.h
573
#define CAR_CLKSRC_XUSB_SS_HS_CLK_BYPASS __BIT(25)
sys/arch/arm/nvidia/tegra124_carreg.h
574
#define CAR_CLKSRC_XUSB_SS_SS_CLK_BYPASS __BIT(24)
sys/arch/arm/nvidia/tegra124_carreg.h
60
#define CAR_PLLP_OUTA_OUT2_OVRRIDE __BIT(18)
sys/arch/arm/nvidia/tegra124_carreg.h
61
#define CAR_PLLP_OUTA_OUT2_CLKEN __BIT(17)
sys/arch/arm/nvidia/tegra124_carreg.h
62
#define CAR_PLLP_OUTA_OUT2_RSTN __BIT(16)
sys/arch/arm/nvidia/tegra124_carreg.h
64
#define CAR_PLLP_OUTA_OUT1_OVRRIDE __BIT(2)
sys/arch/arm/nvidia/tegra124_carreg.h
65
#define CAR_PLLP_OUTA_OUT1_CLKEN __BIT(1)
sys/arch/arm/nvidia/tegra124_carreg.h
66
#define CAR_PLLP_OUTA_OUT1_RSTN __BIT(0)
sys/arch/arm/nvidia/tegra124_carreg.h
69
#define CAR_PLLP_OUTB_OUT4_OVRRIDE __BIT(18)
sys/arch/arm/nvidia/tegra124_carreg.h
70
#define CAR_PLLP_OUTB_OUT4_CLKEN __BIT(17)
sys/arch/arm/nvidia/tegra124_carreg.h
71
#define CAR_PLLP_OUTB_OUT4_RSTN __BIT(16)
sys/arch/arm/nvidia/tegra124_carreg.h
73
#define CAR_PLLP_OUTB_OUT3_OVRRIDE __BIT(2)
sys/arch/arm/nvidia/tegra124_carreg.h
74
#define CAR_PLLP_OUTB_OUT3_CLKEN __BIT(1)
sys/arch/arm/nvidia/tegra124_carreg.h
75
#define CAR_PLLP_OUTB_OUT3_RSTN __BIT(0)
sys/arch/arm/nvidia/tegra124_carreg.h
78
#define CAR_PLLP_OUTC_OUT5_OVERRIDE __BIT(18)
sys/arch/arm/nvidia/tegra124_carreg.h
79
#define CAR_PLLP_OUTC_OUT5_CLKEN __BIT(17)
sys/arch/arm/nvidia/tegra124_carreg.h
80
#define CAR_PLLP_OUTC_OUT5_RSTN __BIT(16)
sys/arch/arm/nvidia/tegra124_carreg.h
84
#define CAR_PLLC_BASE_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra124_carreg.h
85
#define CAR_PLLC_BASE_REF_DIS __BIT(29)
sys/arch/arm/nvidia/tegra124_carreg.h
86
#define CAR_PLLC_BASE_LOCK_OVERRIDE __BIT(28)
sys/arch/arm/nvidia/tegra124_carreg.h
87
#define CAR_PLLC_BASE_LOCK __BIT(27)
sys/arch/arm/nvidia/tegra124_carreg.h
93
#define CAR_PLLU_BASE_BYPASS __BIT(31)
sys/arch/arm/nvidia/tegra124_carreg.h
94
#define CAR_PLLU_BASE_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra124_carreg.h
95
#define CAR_PLLU_BASE_REF_DIS __BIT(29)
sys/arch/arm/nvidia/tegra124_carreg.h
96
#define CAR_PLLU_BASE_LOCK __BIT(27)
sys/arch/arm/nvidia/tegra124_carreg.h
97
#define CAR_PLLU_BASE_CLKENABLE_48M __BIT(25)
sys/arch/arm/nvidia/tegra124_carreg.h
98
#define CAR_PLLU_BASE_OVERRIDE __BIT(24)
sys/arch/arm/nvidia/tegra124_carreg.h
99
#define CAR_PLLU_BASE_CLKENABLE_ICUSB __BIT(23)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
121
#define XUSB_PADCTL_OC_DET_OC_DETECTED_VBUS_PAD2 __BIT(22)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
122
#define XUSB_PADCTL_OC_DET_OC_DETECTED_VBUS_PAD1 __BIT(21)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
123
#define XUSB_PADCTL_OC_DET_OC_DETECTED_VBUS_PAD0 __BIT(20)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
124
#define XUSB_PADCTL_OC_DET_OC_DETECTED3 __BIT(19)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
125
#define XUSB_PADCTL_OC_DET_OC_DETECTED2 __BIT(18)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
126
#define XUSB_PADCTL_OC_DET_OC_DETECTED1 __BIT(17)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
127
#define XUSB_PADCTL_OC_DET_OC_DETECTED0 __BIT(16)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
128
#define XUSB_PADCTL_OC_DET_VBUS_ENABLE1 __BIT(9)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
129
#define XUSB_PADCTL_OC_DET_VBUS_ENABLE0 __BIT(8)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
130
#define XUSB_PADCTL_OC_DET_VBUS_ENABLE2 __BIT(4)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
132
#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN __BIT(26)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
133
#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY __BIT(25)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
134
#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN __BIT(24)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
135
#define XUSB_PADCTL_ELPG_PROGRAM_SSP1_ELPG_VCORE_DOWN __BIT(22)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
136
#define XUSB_PADCTL_ELPG_PROGRAM_SSP1_ELPG_CLAMP_EN_EARLY __BIT(21)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
137
#define XUSB_PADCTL_ELPG_PROGRAM_SSP1_ELPG_CLAMP_EN __BIT(20)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
138
#define XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_VCORE_DOWN __BIT(18)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
139
#define XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN_EARLY __BIT(17)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
140
#define XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN __BIT(16)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
142
#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI __BIT(21)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
143
#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 __BIT(20)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
144
#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD __BIT(19)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
153
#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR __BIT(2)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
154
#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP __BIT(1)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
155
#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP __BIT(0)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
157
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD_TRK __BIT(13)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
158
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD __BIT(12)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
167
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 __BIT(6)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
169
#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET __BIT(27)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
170
#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE __BIT(24)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
171
#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PWR_OVRD __BIT(3)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
172
#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST __BIT(1)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
173
#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_IDDQ __BIT(0)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
175
#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD __BIT(1)
sys/arch/arm/nvidia/tegra124_xusbpadreg.h
176
#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ __BIT(0)
sys/arch/arm/nvidia/tegra210_car.c
1637
rst->mask = __BIT(reset_id % 32);
sys/arch/arm/nvidia/tegra210_carreg.h
100
#define CAR_PLLU_BASE_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra210_carreg.h
101
#define CAR_PLLU_BASE_REF_DIS __BIT(29)
sys/arch/arm/nvidia/tegra210_carreg.h
102
#define CAR_PLLU_BASE_LOCK __BIT(27)
sys/arch/arm/nvidia/tegra210_carreg.h
103
#define CAR_PLLU_BASE_CLKENABLE_48M __BIT(25)
sys/arch/arm/nvidia/tegra210_carreg.h
104
#define CAR_PLLU_BASE_OVERRIDE __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
105
#define CAR_PLLU_BASE_CLKENABLE_ICUSB __BIT(23)
sys/arch/arm/nvidia/tegra210_carreg.h
106
#define CAR_PLLU_BASE_CLKENABLE_HSIC __BIT(22)
sys/arch/arm/nvidia/tegra210_carreg.h
107
#define CAR_PLLU_BASE_CLKENABLE_USB __BIT(21)
sys/arch/arm/nvidia/tegra210_carreg.h
114
#define CAR_PLLU_OUTA_OUT2_OVRRIDE __BIT(18)
sys/arch/arm/nvidia/tegra210_carreg.h
115
#define CAR_PLLU_OUTA_OUT2_CLKEN __BIT(17)
sys/arch/arm/nvidia/tegra210_carreg.h
116
#define CAR_PLLU_OUTA_OUT2_RSTN __BIT(16)
sys/arch/arm/nvidia/tegra210_carreg.h
118
#define CAR_PLLU_OUTA_OUT1_OVRRIDE __BIT(2)
sys/arch/arm/nvidia/tegra210_carreg.h
119
#define CAR_PLLU_OUTA_OUT1_CLKEN __BIT(1)
sys/arch/arm/nvidia/tegra210_carreg.h
120
#define CAR_PLLU_OUTA_OUT1_RSTN __BIT(0)
sys/arch/arm/nvidia/tegra210_carreg.h
123
#define CAR_PLLU_MISC_IDDQ __BIT(31)
sys/arch/arm/nvidia/tegra210_carreg.h
124
#define CAR_PLLU_MISC_FREQLOCK __BIT(30)
sys/arch/arm/nvidia/tegra210_carreg.h
125
#define CAR_PLLU_MISC_EN_LCKDET __BIT(29)
sys/arch/arm/nvidia/tegra210_carreg.h
128
#define CAR_PLLU_MISC_KVCO __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
132
#define CAR_PLLD_BASE_BYPASS __BIT(31)
sys/arch/arm/nvidia/tegra210_carreg.h
133
#define CAR_PLLD_BASE_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra210_carreg.h
134
#define CAR_PLLD_BASE_REF_DIS __BIT(29)
sys/arch/arm/nvidia/tegra210_carreg.h
135
#define CAR_PLLD_BASE_LOCK __BIT(27)
sys/arch/arm/nvidia/tegra210_carreg.h
136
#define CAR_PLLD_BASE_DSIA_CLK_SRC __BIT(25)
sys/arch/arm/nvidia/tegra210_carreg.h
137
#define CAR_PLLD_BASE_CSI_CLK_SRC __BIT(23)
sys/arch/arm/nvidia/tegra210_carreg.h
145
#define CAR_PLLX_BASE_BYPASS __BIT(31)
sys/arch/arm/nvidia/tegra210_carreg.h
146
#define CAR_PLLX_BASE_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra210_carreg.h
147
#define CAR_PLLX_BASE_REF_DIS __BIT(29)
sys/arch/arm/nvidia/tegra210_carreg.h
148
#define CAR_PLLX_BASE_LOCK __BIT(27)
sys/arch/arm/nvidia/tegra210_carreg.h
154
#define CAR_PLLX_MISC_FO_G_DISABLE __BIT(28)
sys/arch/arm/nvidia/tegra210_carreg.h
156
#define CAR_PLLX_MISC_LOCK_ENABLE __BIT(18)
sys/arch/arm/nvidia/tegra210_carreg.h
159
#define CAR_PLLE_BASE_ENABLE __BIT(31)
sys/arch/arm/nvidia/tegra210_carreg.h
160
#define CAR_PLLE_BASE_LOCK_OVERRIDE __BIT(30)
sys/arch/arm/nvidia/tegra210_carreg.h
161
#define CAR_PLLE_BASE_FDIV4B __BIT(29)
sys/arch/arm/nvidia/tegra210_carreg.h
169
#define CAR_PLLE_MISC_ENABLE __BIT(15)
sys/arch/arm/nvidia/tegra210_carreg.h
170
#define CAR_PLLE_MISC_IDDQ_SWCTL __BIT(14)
sys/arch/arm/nvidia/tegra210_carreg.h
171
#define CAR_PLLE_MISC_IDDQ_OVERRIDE __BIT(13)
sys/arch/arm/nvidia/tegra210_carreg.h
172
#define CAR_PLLE_MISC_LOCK __BIT(11)
sys/arch/arm/nvidia/tegra210_carreg.h
173
#define CAR_PLLE_MISC_LOCK_ENABLE __BIT(9)
sys/arch/arm/nvidia/tegra210_carreg.h
174
#define CAR_PLLE_MISC_PTS __BIT(8)
sys/arch/arm/nvidia/tegra210_carreg.h
178
#define CAR_PLLE_MISC_KVCO __BIT(0)
sys/arch/arm/nvidia/tegra210_carreg.h
181
#define CAR_PLLD2_BASE_BYPASS __BIT(31)
sys/arch/arm/nvidia/tegra210_carreg.h
182
#define CAR_PLLD2_BASE_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra210_carreg.h
183
#define CAR_PLLD2_BASE_REF_DIS __BIT(29)
sys/arch/arm/nvidia/tegra210_carreg.h
184
#define CAR_PLLD2_BASE_FREQLOCK __BIT(28)
sys/arch/arm/nvidia/tegra210_carreg.h
185
#define CAR_PLLD2_BASE_LOCK __BIT(27)
sys/arch/arm/nvidia/tegra210_carreg.h
189
#define CAR_PLLD2_BASE_LOCK_OVERRIDE __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
191
#define CAR_PLLD2_BASE_IDDQ __BIT(18)
sys/arch/arm/nvidia/tegra210_carreg.h
192
#define CAR_PLLD2_BASE_PTS __BIT(16)
sys/arch/arm/nvidia/tegra210_carreg.h
197
#define CAR_PLLD2_MISC_LOCK_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra210_carreg.h
199
#define CAR_PLLD2_MISC_KVCO __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
249
#define CAR_CLKSRC_UART_DIV_ENB __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
305
#define CAR_DEV_L_CACHE2 __BIT(31)
sys/arch/arm/nvidia/tegra210_carreg.h
306
#define CAR_DEV_L_I2S1 __BIT(30)
sys/arch/arm/nvidia/tegra210_carreg.h
307
#define CAR_DEV_L_HOST1X __BIT(28)
sys/arch/arm/nvidia/tegra210_carreg.h
308
#define CAR_DEV_L_DISP1 __BIT(27)
sys/arch/arm/nvidia/tegra210_carreg.h
309
#define CAR_DEV_L_DISP2 __BIT(26)
sys/arch/arm/nvidia/tegra210_carreg.h
310
#define CAR_DEV_L_ISP __BIT(23)
sys/arch/arm/nvidia/tegra210_carreg.h
311
#define CAR_DEV_L_USBD __BIT(22)
sys/arch/arm/nvidia/tegra210_carreg.h
312
#define CAR_DEV_L_VI __BIT(20)
sys/arch/arm/nvidia/tegra210_carreg.h
313
#define CAR_DEV_L_I2S3 __BIT(18)
sys/arch/arm/nvidia/tegra210_carreg.h
314
#define CAR_DEV_L_PWM __BIT(17)
sys/arch/arm/nvidia/tegra210_carreg.h
315
#define CAR_DEV_L_SDMMC4 __BIT(15)
sys/arch/arm/nvidia/tegra210_carreg.h
316
#define CAR_DEV_L_SDMMC1 __BIT(14)
sys/arch/arm/nvidia/tegra210_carreg.h
317
#define CAR_DEV_L_I2C1 __BIT(12)
sys/arch/arm/nvidia/tegra210_carreg.h
318
#define CAR_DEV_L_I2S2 __BIT(11)
sys/arch/arm/nvidia/tegra210_carreg.h
319
#define CAR_DEV_L_SPDIF __BIT(10)
sys/arch/arm/nvidia/tegra210_carreg.h
320
#define CAR_DEV_L_SDMMC2 __BIT(9)
sys/arch/arm/nvidia/tegra210_carreg.h
321
#define CAR_DEV_L_GPIO __BIT(8)
sys/arch/arm/nvidia/tegra210_carreg.h
322
#define CAR_DEV_L_UARTB __BIT(7)
sys/arch/arm/nvidia/tegra210_carreg.h
323
#define CAR_DEV_L_UARTA __BIT(6)
sys/arch/arm/nvidia/tegra210_carreg.h
324
#define CAR_DEV_L_TMR __BIT(5)
sys/arch/arm/nvidia/tegra210_carreg.h
325
#define CAR_DEV_L_RTC __BIT(4)
sys/arch/arm/nvidia/tegra210_carreg.h
326
#define CAR_DEV_L_ISPB __BIT(3)
sys/arch/arm/nvidia/tegra210_carreg.h
327
#define CAR_DEV_L_TRIG_SYS __BIT(2)
sys/arch/arm/nvidia/tegra210_carreg.h
328
#define CAR_DEV_L_COP __BIT(1)
sys/arch/arm/nvidia/tegra210_carreg.h
329
#define CAR_DEV_L_CPU __BIT(0)
sys/arch/arm/nvidia/tegra210_carreg.h
331
#define CAR_DEV_U_XUSB_DEV __BIT(31)
sys/arch/arm/nvidia/tegra210_carreg.h
332
#define CAR_DEV_U_DEV1_OUT __BIT(30)
sys/arch/arm/nvidia/tegra210_carreg.h
333
#define CAR_DEV_U_DEV2_OUT __BIT(29)
sys/arch/arm/nvidia/tegra210_carreg.h
334
#define CAR_DEV_U_SUS_OUT __BIT(28)
sys/arch/arm/nvidia/tegra210_carreg.h
335
#define CAR_DEV_U_MSENC __BIT(27)
sys/arch/arm/nvidia/tegra210_carreg.h
336
#define CAR_DEV_U_XUSB_HOST __BIT(25)
sys/arch/arm/nvidia/tegra210_carreg.h
337
#define CAR_DEV_U_CRAM2 __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
338
#define CAR_DEV_U_IRAMD __BIT(23)
sys/arch/arm/nvidia/tegra210_carreg.h
339
#define CAR_DEV_U_IRAMC __BIT(22)
sys/arch/arm/nvidia/tegra210_carreg.h
340
#define CAR_DEV_U_IRAMB __BIT(21)
sys/arch/arm/nvidia/tegra210_carreg.h
341
#define CAR_DEV_U_IRAMA __BIT(20)
sys/arch/arm/nvidia/tegra210_carreg.h
342
#define CAR_DEV_U_TSEC __BIT(19)
sys/arch/arm/nvidia/tegra210_carreg.h
343
#define CAR_DEV_U_DSIB __BIT(18)
sys/arch/arm/nvidia/tegra210_carreg.h
344
#define CAR_DEV_U_I2C_SLOW __BIT(17)
sys/arch/arm/nvidia/tegra210_carreg.h
345
#define CAR_DEV_U_DTV __BIT(15)
sys/arch/arm/nvidia/tegra210_carreg.h
346
#define CAR_DEV_U_SOC_THERM __BIT(14)
sys/arch/arm/nvidia/tegra210_carreg.h
347
#define CAR_DEV_U_PCIEXCLK __BIT(10)
sys/arch/arm/nvidia/tegra210_carreg.h
348
#define CAR_DEV_U_CSITE __BIT(9)
sys/arch/arm/nvidia/tegra210_carreg.h
349
#define CAR_DEV_U_AFI __BIT(8)
sys/arch/arm/nvidia/tegra210_carreg.h
35
#define CAR_RST_SOURCE_WDT_EN __BIT(5)
sys/arch/arm/nvidia/tegra210_carreg.h
350
#define CAR_DEV_U_PCIE __BIT(6)
sys/arch/arm/nvidia/tegra210_carreg.h
351
#define CAR_DEV_U_SDMMC3 __BIT(5)
sys/arch/arm/nvidia/tegra210_carreg.h
352
#define CAR_DEV_U_SPI4 __BIT(4)
sys/arch/arm/nvidia/tegra210_carreg.h
353
#define CAR_DEV_U_I2C3 __BIT(3)
sys/arch/arm/nvidia/tegra210_carreg.h
354
#define CAR_DEV_U_UARTD __BIT(1)
sys/arch/arm/nvidia/tegra210_carreg.h
356
#define CAR_DEV_H_BSEV __BIT(31)
sys/arch/arm/nvidia/tegra210_carreg.h
357
#define CAR_DEV_H_USB2 __BIT(26)
sys/arch/arm/nvidia/tegra210_carreg.h
358
#define CAR_DEV_H_EMC __BIT(25)
sys/arch/arm/nvidia/tegra210_carreg.h
359
#define CAR_DEV_H_MIPI_CAL __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
36
#define CAR_RST_SOURCE_WDT_SEL __BIT(4)
sys/arch/arm/nvidia/tegra210_carreg.h
360
#define CAR_DEV_H_UARTC __BIT(23)
sys/arch/arm/nvidia/tegra210_carreg.h
361
#define CAR_DEV_H_I2C2 __BIT(22)
sys/arch/arm/nvidia/tegra210_carreg.h
362
#define CAR_DEV_H_CSI __BIT(20)
sys/arch/arm/nvidia/tegra210_carreg.h
363
#define CAR_DEV_H_DSI __BIT(16)
sys/arch/arm/nvidia/tegra210_carreg.h
364
#define CAR_DEV_H_I2C5 __BIT(15)
sys/arch/arm/nvidia/tegra210_carreg.h
365
#define CAR_DEV_H_SPI3 __BIT(14)
sys/arch/arm/nvidia/tegra210_carreg.h
366
#define CAR_DEV_H_SPI2 __BIT(12)
sys/arch/arm/nvidia/tegra210_carreg.h
367
#define CAR_DEV_H_SPI1 __BIT(9)
sys/arch/arm/nvidia/tegra210_carreg.h
368
#define CAR_DEV_H_KFUSE __BIT(8)
sys/arch/arm/nvidia/tegra210_carreg.h
369
#define CAR_DEV_H_FUSE __BIT(7)
sys/arch/arm/nvidia/tegra210_carreg.h
37
#define CAR_RST_SOURCE_WDT_SYS_RST_EN __BIT(2)
sys/arch/arm/nvidia/tegra210_carreg.h
370
#define CAR_DEV_H_PMC __BIT(6)
sys/arch/arm/nvidia/tegra210_carreg.h
371
#define CAR_DEV_H_STAT_MON __BIT(5)
sys/arch/arm/nvidia/tegra210_carreg.h
372
#define CAR_DEV_H_APBDMA __BIT(2)
sys/arch/arm/nvidia/tegra210_carreg.h
373
#define CAR_DEV_H_AHBDMA __BIT(1)
sys/arch/arm/nvidia/tegra210_carreg.h
374
#define CAR_DEV_H_MEM __BIT(0)
sys/arch/arm/nvidia/tegra210_carreg.h
376
#define CAR_DEV_V_HDA __BIT(29)
sys/arch/arm/nvidia/tegra210_carreg.h
377
#define CAR_DEV_V_SATA __BIT(28)
sys/arch/arm/nvidia/tegra210_carreg.h
378
#define CAR_DEV_V_SATA_OOB __BIT(27)
sys/arch/arm/nvidia/tegra210_carreg.h
379
#define CAR_DEV_V_EXTPERIPH3 __BIT(26)
sys/arch/arm/nvidia/tegra210_carreg.h
38
#define CAR_RST_SOURCE_WDT_COP_RST_EN __BIT(1)
sys/arch/arm/nvidia/tegra210_carreg.h
380
#define CAR_DEV_V_EXTPERIPH2 __BIT(25)
sys/arch/arm/nvidia/tegra210_carreg.h
381
#define CAR_DEV_V_EXTPERIPH1 __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
382
#define CAR_DEV_V_ACTMON __BIT(23)
sys/arch/arm/nvidia/tegra210_carreg.h
383
#define CAR_DEV_V_SPDIF_DOUBLER __BIT(22)
sys/arch/arm/nvidia/tegra210_carreg.h
384
#define CAR_DEV_V_ATOMICS __BIT(16)
sys/arch/arm/nvidia/tegra210_carreg.h
385
#define CAR_DEV_V_HDA2CODEC_2X __BIT(15)
sys/arch/arm/nvidia/tegra210_carreg.h
386
#define CAR_DEV_V_APB2APE __BIT(11)
sys/arch/arm/nvidia/tegra210_carreg.h
387
#define CAR_DEV_V_AHUB __BIT(10)
sys/arch/arm/nvidia/tegra210_carreg.h
388
#define CAR_DEV_V_I2C4 __BIT(7)
sys/arch/arm/nvidia/tegra210_carreg.h
389
#define CAR_DEV_V_I2S5 __BIT(6)
sys/arch/arm/nvidia/tegra210_carreg.h
39
#define CAR_RST_SOURCE_WDT_CPU_RST_EN __BIT(0)
sys/arch/arm/nvidia/tegra210_carreg.h
390
#define CAR_DEV_V_I2S4 __BIT(5)
sys/arch/arm/nvidia/tegra210_carreg.h
391
#define CAR_DEV_V_TSENSOR __BIT(4)
sys/arch/arm/nvidia/tegra210_carreg.h
392
#define CAR_DEV_V_MSELECT __BIT(3)
sys/arch/arm/nvidia/tegra210_carreg.h
393
#define CAR_DEV_V_CPULP __BIT(1)
sys/arch/arm/nvidia/tegra210_carreg.h
394
#define CAR_DEV_V_CPUG __BIT(0)
sys/arch/arm/nvidia/tegra210_carreg.h
396
#define CAR_DEV_W_MC1 __BIT(30)
sys/arch/arm/nvidia/tegra210_carreg.h
397
#define CAR_DEV_W_EMC_DLL __BIT(29)
sys/arch/arm/nvidia/tegra210_carreg.h
398
#define CAR_DEV_W_XUSB_SS __BIT(28)
sys/arch/arm/nvidia/tegra210_carreg.h
399
#define CAR_DEV_W_DVFS __BIT(27)
sys/arch/arm/nvidia/tegra210_carreg.h
400
#define CAR_DEV_W_ENTROPY __BIT(21)
sys/arch/arm/nvidia/tegra210_carreg.h
401
#define CAR_DEV_W_DSIB_LP __BIT(20)
sys/arch/arm/nvidia/tegra210_carreg.h
402
#define CAR_DEV_W_DSIA_LP __BIT(19)
sys/arch/arm/nvidia/tegra210_carreg.h
403
#define CAR_DEV_W_CILEF __BIT(18)
sys/arch/arm/nvidia/tegra210_carreg.h
404
#define CAR_DEV_W_CILCD __BIT(17)
sys/arch/arm/nvidia/tegra210_carreg.h
405
#define CAR_DEV_W_CILAB __BIT(16)
sys/arch/arm/nvidia/tegra210_carreg.h
406
#define CAR_DEV_W_XUSB __BIT(15)
sys/arch/arm/nvidia/tegra210_carreg.h
407
#define CAR_DEV_W_XUSB_PADCTL __BIT(14)
sys/arch/arm/nvidia/tegra210_carreg.h
408
#define CAR_DEV_W_MIPI_IOBIST __BIT(13)
sys/arch/arm/nvidia/tegra210_carreg.h
409
#define CAR_DEV_W_SATA_IOBIST __BIT(12)
sys/arch/arm/nvidia/tegra210_carreg.h
410
#define CAR_DEV_W_EMC_IOBIST __BIT(10)
sys/arch/arm/nvidia/tegra210_carreg.h
411
#define CAR_DEV_W_PCIE2_IOBIST __BIT(9)
sys/arch/arm/nvidia/tegra210_carreg.h
412
#define CAR_DEV_W_CEC __BIT(8)
sys/arch/arm/nvidia/tegra210_carreg.h
413
#define CAR_DEV_W_PCIERX5 __BIT(7)
sys/arch/arm/nvidia/tegra210_carreg.h
414
#define CAR_DEV_W_PCIERX4 __BIT(6)
sys/arch/arm/nvidia/tegra210_carreg.h
415
#define CAR_DEV_W_PCIERX3 __BIT(5)
sys/arch/arm/nvidia/tegra210_carreg.h
416
#define CAR_DEV_W_PCIERX2 __BIT(4)
sys/arch/arm/nvidia/tegra210_carreg.h
417
#define CAR_DEV_W_PCIERX1 __BIT(3)
sys/arch/arm/nvidia/tegra210_carreg.h
418
#define CAR_DEV_W_PCIERX0 __BIT(2)
sys/arch/arm/nvidia/tegra210_carreg.h
419
#define CAR_DEV_W_SATACOLD __BIT(1)
sys/arch/arm/nvidia/tegra210_carreg.h
420
#define CAR_DEV_W_HDA2HDMICODEC __BIT(0)
sys/arch/arm/nvidia/tegra210_carreg.h
422
#define CAR_DEV_X_PLLG_REF __BIT(29)
sys/arch/arm/nvidia/tegra210_carreg.h
423
#define CAR_DEV_X_PLLA_ADSP __BIT(28)
sys/arch/arm/nvidia/tegra210_carreg.h
424
#define CAR_DEV_X_PLLP_ADSP __BIT(27)
sys/arch/arm/nvidia/tegra210_carreg.h
425
#define CAR_DEV_X_HPLL_ADSP __BIT(26)
sys/arch/arm/nvidia/tegra210_carreg.h
426
#define CAR_DEV_X_DBGAPB __BIT(25)
sys/arch/arm/nvidia/tegra210_carreg.h
427
#define CAR_DEV_X_GPU __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
428
#define CAR_DEV_X_SOR1 __BIT(23)
sys/arch/arm/nvidia/tegra210_carreg.h
429
#define CAR_DEV_X_SOR0 __BIT(22)
sys/arch/arm/nvidia/tegra210_carreg.h
430
#define CAR_DEV_X_DPAUX __BIT(21)
sys/arch/arm/nvidia/tegra210_carreg.h
431
#define CAR_DEV_X_VIC __BIT(18)
sys/arch/arm/nvidia/tegra210_carreg.h
432
#define CAR_DEV_X_UART_FST_MIPI_CAL __BIT(17)
sys/arch/arm/nvidia/tegra210_carreg.h
433
#define CAR_DEV_X_EMC_DLL __BIT(14)
sys/arch/arm/nvidia/tegra210_carreg.h
434
#define CAR_DEV_X_VIM2_CLK __BIT(11)
sys/arch/arm/nvidia/tegra210_carreg.h
435
#define CAR_DEV_X_MC_BBC __BIT(10)
sys/arch/arm/nvidia/tegra210_carreg.h
436
#define CAR_DEV_X_MC_CPU __BIT(9)
sys/arch/arm/nvidia/tegra210_carreg.h
437
#define CAR_DEV_X_MC_CBPA __BIT(8)
sys/arch/arm/nvidia/tegra210_carreg.h
438
#define CAR_DEV_X_MC_CAPA __BIT(7)
sys/arch/arm/nvidia/tegra210_carreg.h
439
#define CAR_DEV_X_I2C6 __BIT(6)
sys/arch/arm/nvidia/tegra210_carreg.h
440
#define CAR_DEV_X_CAM_MCLK2 __BIT(5)
sys/arch/arm/nvidia/tegra210_carreg.h
441
#define CAR_DEV_X_CAM_MCLK __BIT(4)
sys/arch/arm/nvidia/tegra210_carreg.h
442
#define CAR_DEV_X_ETR __BIT(3)
sys/arch/arm/nvidia/tegra210_carreg.h
443
#define CAR_DEV_X_SPARE __BIT(0)
sys/arch/arm/nvidia/tegra210_carreg.h
445
#define CAR_DEV_Y_PLLP_OUT_CPU __BIT(31)
sys/arch/arm/nvidia/tegra210_carreg.h
446
#define CAR_DEV_Y_SOR_SAFE __BIT(30)
sys/arch/arm/nvidia/tegra210_carreg.h
447
#define CAR_DEV_Y_IQC1 __BIT(29)
sys/arch/arm/nvidia/tegra210_carreg.h
448
#define CAR_DEV_Y_IQC2 __BIT(28)
sys/arch/arm/nvidia/tegra210_carreg.h
449
#define CAR_DEV_Y_NVENC __BIT(27)
sys/arch/arm/nvidia/tegra210_carreg.h
450
#define CAR_DEV_Y_ADSPNEON __BIT(26)
sys/arch/arm/nvidia/tegra210_carreg.h
451
#define CAR_DEV_Y_ADSPSCU __BIT(25)
sys/arch/arm/nvidia/tegra210_carreg.h
452
#define CAR_DEV_Y_ADSPWDT __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
453
#define CAR_DEV_Y_ADSPDBG __BIT(23)
sys/arch/arm/nvidia/tegra210_carreg.h
454
#define CAR_DEV_Y_ADSPPERIPH __BIT(22)
sys/arch/arm/nvidia/tegra210_carreg.h
455
#define CAR_DEV_Y_ADSPINTF __BIT(21)
sys/arch/arm/nvidia/tegra210_carreg.h
456
#define CAR_DEV_Y_UARTAPE __BIT(20)
sys/arch/arm/nvidia/tegra210_carreg.h
457
#define CAR_DEV_Y_QSPI __BIT(19)
sys/arch/arm/nvidia/tegra210_carreg.h
458
#define CAR_DEV_Y_USB2_TRK __BIT(18)
sys/arch/arm/nvidia/tegra210_carreg.h
459
#define CAR_DEV_Y_HSIC_TRK __BIT(17)
sys/arch/arm/nvidia/tegra210_carreg.h
460
#define CAR_DEV_Y_VI_I2C __BIT(16)
sys/arch/arm/nvidia/tegra210_carreg.h
461
#define CAR_DEV_Y_DPAUX __BIT(15)
sys/arch/arm/nvidia/tegra210_carreg.h
462
#define CAR_DEV_Y_TSECB __BIT(14)
sys/arch/arm/nvidia/tegra210_carreg.h
463
#define CAR_DEV_Y_PEX_USB_UPHY __BIT(13)
sys/arch/arm/nvidia/tegra210_carreg.h
464
#define CAR_DEV_Y_SATA_USB_UPHY __BIT(12)
sys/arch/arm/nvidia/tegra210_carreg.h
465
#define CAR_DEV_Y_MAUD __BIT(10)
sys/arch/arm/nvidia/tegra210_carreg.h
466
#define CAR_DEV_Y_MC_CCPA __BIT(9)
sys/arch/arm/nvidia/tegra210_carreg.h
467
#define CAR_DEV_Y_MC_CDPA __BIT(8)
sys/arch/arm/nvidia/tegra210_carreg.h
468
#define CAR_DEV_Y_ADSP __BIT(7)
sys/arch/arm/nvidia/tegra210_carreg.h
469
#define CAR_DEV_Y_APE __BIT(6)
sys/arch/arm/nvidia/tegra210_carreg.h
470
#define CAR_DEV_Y_DMIC3 __BIT(5)
sys/arch/arm/nvidia/tegra210_carreg.h
471
#define CAR_DEV_Y_AXIAP __BIT(4)
sys/arch/arm/nvidia/tegra210_carreg.h
472
#define CAR_DEV_Y_NVJPG __BIT(3)
sys/arch/arm/nvidia/tegra210_carreg.h
473
#define CAR_DEV_Y_NVDEC __BIT(2)
sys/arch/arm/nvidia/tegra210_carreg.h
474
#define CAR_DEV_Y_SDMMC_LEGACY_TM __BIT(1)
sys/arch/arm/nvidia/tegra210_carreg.h
475
#define CAR_DEV_Y_SPARE1 __BIT(0)
sys/arch/arm/nvidia/tegra210_carreg.h
49
#define CAR_PLLE_SS_CNTL_SSCINVERT __BIT(15)
sys/arch/arm/nvidia/tegra210_carreg.h
50
#define CAR_PLLE_SS_CNTL_SSCCENTER __BIT(14)
sys/arch/arm/nvidia/tegra210_carreg.h
504
#define CAR_CLKSRC_SATA_AUX_CLK_ENB __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
51
#define CAR_PLLE_SS_CNTL_SSCPDMBYP __BIT(13)
sys/arch/arm/nvidia/tegra210_carreg.h
515
#define CAR_UTMIP_PLL_CFG1_PLLU_POWERUP __BIT(17)
sys/arch/arm/nvidia/tegra210_carreg.h
516
#define CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN __BIT(16)
sys/arch/arm/nvidia/tegra210_carreg.h
517
#define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP __BIT(15)
sys/arch/arm/nvidia/tegra210_carreg.h
518
#define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN __BIT(14)
sys/arch/arm/nvidia/tegra210_carreg.h
52
#define CAR_PLLE_SS_CNTL_SSCBYP __BIT(12)
sys/arch/arm/nvidia/tegra210_carreg.h
522
#define CAR_UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN __BIT(30)
sys/arch/arm/nvidia/tegra210_carreg.h
523
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_D_POWERUP __BIT(25)
sys/arch/arm/nvidia/tegra210_carreg.h
524
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_D_POWERDOWN __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
527
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP __BIT(5)
sys/arch/arm/nvidia/tegra210_carreg.h
528
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN __BIT(4)
sys/arch/arm/nvidia/tegra210_carreg.h
529
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP __BIT(3)
sys/arch/arm/nvidia/tegra210_carreg.h
53
#define CAR_PLLE_SS_CNTL_INTERP_RESET __BIT(11)
sys/arch/arm/nvidia/tegra210_carreg.h
530
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN __BIT(2)
sys/arch/arm/nvidia/tegra210_carreg.h
531
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP __BIT(1)
sys/arch/arm/nvidia/tegra210_carreg.h
532
#define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN __BIT(0)
sys/arch/arm/nvidia/tegra210_carreg.h
535
#define CAR_PLLE_AUX_SS_SEQ_INCLUDE __BIT(31)
sys/arch/arm/nvidia/tegra210_carreg.h
536
#define CAR_PLLE_AUX_REF_SEL_PLLREFE __BIT(28)
sys/arch/arm/nvidia/tegra210_carreg.h
538
#define CAR_PLLE_AUX_SEQ_START_STATE __BIT(25)
sys/arch/arm/nvidia/tegra210_carreg.h
539
#define CAR_PLLE_AUX_SEQ_ENABLE __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
54
#define CAR_PLLE_SS_CNTL_BYPASS_SS __BIT(10)
sys/arch/arm/nvidia/tegra210_carreg.h
542
#define CAR_PLLE_AUX_FAST_PT __BIT(7)
sys/arch/arm/nvidia/tegra210_carreg.h
543
#define CAR_PLLE_AUX_SS_SWCTL __BIT(6)
sys/arch/arm/nvidia/tegra210_carreg.h
544
#define CAR_PLLE_AUX_CONFIG_SWCTL __BIT(5)
sys/arch/arm/nvidia/tegra210_carreg.h
545
#define CAR_PLLE_AUX_ENABLE_SWCTL __BIT(4)
sys/arch/arm/nvidia/tegra210_carreg.h
546
#define CAR_PLLE_AUX_USE_LOCKDET __BIT(3)
sys/arch/arm/nvidia/tegra210_carreg.h
547
#define CAR_PLLE_AUX_REF_SRC __BIT(2)
sys/arch/arm/nvidia/tegra210_carreg.h
548
#define CAR_PLLE_AUX_CML1_OEN __BIT(1)
sys/arch/arm/nvidia/tegra210_carreg.h
549
#define CAR_PLLE_AUX_CML0_OEN __BIT(0)
sys/arch/arm/nvidia/tegra210_carreg.h
553
#define CAR_SATA_PLL_CFG0_SEQ_START_STATE __BIT(25)
sys/arch/arm/nvidia/tegra210_carreg.h
554
#define CAR_SATA_PLL_CFG0_SEQ_ENABLE __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
555
#define CAR_SATA_PLL_CFG0_SEQ_PADPLL_SLEEP_IDDQ __BIT(13)
sys/arch/arm/nvidia/tegra210_carreg.h
556
#define CAR_SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE __BIT(7)
sys/arch/arm/nvidia/tegra210_carreg.h
557
#define CAR_SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE __BIT(6)
sys/arch/arm/nvidia/tegra210_carreg.h
558
#define CAR_SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5)
sys/arch/arm/nvidia/tegra210_carreg.h
559
#define CAR_SATA_PLL_CFG0_SEQ_IN_SWCTL __BIT(4)
sys/arch/arm/nvidia/tegra210_carreg.h
560
#define CAR_SATA_PLL_CFG0_PADPLL_USE_LOCKDET __BIT(2)
sys/arch/arm/nvidia/tegra210_carreg.h
561
#define CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE __BIT(1)
sys/arch/arm/nvidia/tegra210_carreg.h
562
#define CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL __BIT(0)
sys/arch/arm/nvidia/tegra210_carreg.h
571
#define CAR_UTMIP_PLL_CFG3_REF_SRC_SEL __BIT(26)
sys/arch/arm/nvidia/tegra210_carreg.h
572
#define CAR_UTMIP_PLL_CFG3_REF_DIS __BIT(25)
sys/arch/arm/nvidia/tegra210_carreg.h
573
#define CAR_UTMIP_PLL_CFG3_PTS __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
577
#define CAR_PLLREFE_BASE_BYPASS __BIT(31)
sys/arch/arm/nvidia/tegra210_carreg.h
578
#define CAR_PLLREFE_BASE_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra210_carreg.h
579
#define CAR_PLLREFE_BASE_REF_DIS __BIT(29)
sys/arch/arm/nvidia/tegra210_carreg.h
58
#define CAR_PLLP_BASE_BYPASS __BIT(31)
sys/arch/arm/nvidia/tegra210_carreg.h
581
#define CAR_PLLREFE_BASE_KVCO __BIT(26)
sys/arch/arm/nvidia/tegra210_carreg.h
587
#define CAR_PLLREFE_MISC_LOCK_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra210_carreg.h
588
#define CAR_PLLREFE_MISC_LOCK_OVERRIDE __BIT(29)
sys/arch/arm/nvidia/tegra210_carreg.h
589
#define CAR_PLLREFE_MISC_FREQLOCK __BIT(28)
sys/arch/arm/nvidia/tegra210_carreg.h
59
#define CAR_PLLP_BASE_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra210_carreg.h
590
#define CAR_PLLREFE_MISC_LOCK __BIT(27)
sys/arch/arm/nvidia/tegra210_carreg.h
592
#define CAR_PLLREFE_MISC_IDDQ __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
597
#define CAR_XUSBIO_PLL_CFG0_SEQ_START_STATE __BIT(25)
sys/arch/arm/nvidia/tegra210_carreg.h
598
#define CAR_XUSBIO_PLL_CFG0_SEQ_ENABLE __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
599
#define CAR_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ __BIT(13)
sys/arch/arm/nvidia/tegra210_carreg.h
60
#define CAR_PLLP_BASE_REF_DIS __BIT(29)
sys/arch/arm/nvidia/tegra210_carreg.h
600
#define CAR_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET __BIT(6)
sys/arch/arm/nvidia/tegra210_carreg.h
601
#define CAR_XUSBIO_PLL_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5)
sys/arch/arm/nvidia/tegra210_carreg.h
602
#define CAR_XUSBIO_PLL_CFG0_SEQ_IN_SWCTL __BIT(4)
sys/arch/arm/nvidia/tegra210_carreg.h
603
#define CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_OVERRIDE __BIT(3)
sys/arch/arm/nvidia/tegra210_carreg.h
604
#define CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL __BIT(2)
sys/arch/arm/nvidia/tegra210_carreg.h
605
#define CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE __BIT(1)
sys/arch/arm/nvidia/tegra210_carreg.h
606
#define CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL __BIT(0)
sys/arch/arm/nvidia/tegra210_carreg.h
609
#define CAR_UTMIPLL_HW_PWRDN_CFG0_LOCK __BIT(31)
sys/arch/arm/nvidia/tegra210_carreg.h
61
#define CAR_PLLP_BASE_OVERRIDE __BIT(28)
sys/arch/arm/nvidia/tegra210_carreg.h
611
#define CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE __BIT(25)
sys/arch/arm/nvidia/tegra210_carreg.h
612
#define CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
613
#define CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE __BIT(7)
sys/arch/arm/nvidia/tegra210_carreg.h
614
#define CAR_UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET __BIT(6)
sys/arch/arm/nvidia/tegra210_carreg.h
615
#define CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5)
sys/arch/arm/nvidia/tegra210_carreg.h
616
#define CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL __BIT(4)
sys/arch/arm/nvidia/tegra210_carreg.h
617
#define CAR_UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_OVERRIDE __BIT(3)
sys/arch/arm/nvidia/tegra210_carreg.h
618
#define CAR_UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL __BIT(2)
sys/arch/arm/nvidia/tegra210_carreg.h
619
#define CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE __BIT(1)
sys/arch/arm/nvidia/tegra210_carreg.h
62
#define CAR_PLLP_BASE_LOCK __BIT(27)
sys/arch/arm/nvidia/tegra210_carreg.h
620
#define CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL __BIT(0)
sys/arch/arm/nvidia/tegra210_carreg.h
623
#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE __BIT(28)
sys/arch/arm/nvidia/tegra210_carreg.h
625
#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_START_STATE __BIT(25)
sys/arch/arm/nvidia/tegra210_carreg.h
626
#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_ENABLE __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
627
#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT __BIT(7)
sys/arch/arm/nvidia/tegra210_carreg.h
628
#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_LOCKDET __BIT(6)
sys/arch/arm/nvidia/tegra210_carreg.h
629
#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5)
sys/arch/arm/nvidia/tegra210_carreg.h
630
#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_IN_SWCTL __BIT(4)
sys/arch/arm/nvidia/tegra210_carreg.h
631
#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_ENABLE_OVERRIDE_VALUE __BIT(3)
sys/arch/arm/nvidia/tegra210_carreg.h
632
#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL __BIT(2)
sys/arch/arm/nvidia/tegra210_carreg.h
633
#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL __BIT(0)
sys/arch/arm/nvidia/tegra210_carreg.h
655
#define CAR_CLKSRC_XUSB_SS_HS_CLK_BYPASS __BIT(25)
sys/arch/arm/nvidia/tegra210_carreg.h
656
#define CAR_CLKSRC_XUSB_SS_SS_CLK_BYPASS __BIT(24)
sys/arch/arm/nvidia/tegra210_carreg.h
69
#define CAR_PLLP_OUTA_OUT1_OVRRIDE __BIT(2)
sys/arch/arm/nvidia/tegra210_carreg.h
70
#define CAR_PLLP_OUTA_OUT1_CLKEN __BIT(1)
sys/arch/arm/nvidia/tegra210_carreg.h
71
#define CAR_PLLP_OUTA_OUT1_RSTN __BIT(0)
sys/arch/arm/nvidia/tegra210_carreg.h
74
#define CAR_PLLP_OUTB_OUT4_OVRRIDE __BIT(18)
sys/arch/arm/nvidia/tegra210_carreg.h
75
#define CAR_PLLP_OUTB_OUT4_CLKEN __BIT(17)
sys/arch/arm/nvidia/tegra210_carreg.h
76
#define CAR_PLLP_OUTB_OUT4_RSTN __BIT(16)
sys/arch/arm/nvidia/tegra210_carreg.h
78
#define CAR_PLLP_OUTB_OUT3_OVRRIDE __BIT(2)
sys/arch/arm/nvidia/tegra210_carreg.h
79
#define CAR_PLLP_OUTB_OUT3_CLKEN __BIT(1)
sys/arch/arm/nvidia/tegra210_carreg.h
80
#define CAR_PLLP_OUTB_OUT3_RSTN __BIT(0)
sys/arch/arm/nvidia/tegra210_carreg.h
83
#define CAR_PLLP_OUTC_OUT5_OVERRIDE __BIT(18)
sys/arch/arm/nvidia/tegra210_carreg.h
84
#define CAR_PLLP_OUTC_OUT5_CLKEN __BIT(17)
sys/arch/arm/nvidia/tegra210_carreg.h
85
#define CAR_PLLP_OUTC_OUT5_RSTN __BIT(16)
sys/arch/arm/nvidia/tegra210_carreg.h
89
#define CAR_PLLC_BASE_BYPASS __BIT(31)
sys/arch/arm/nvidia/tegra210_carreg.h
90
#define CAR_PLLC_BASE_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra210_carreg.h
91
#define CAR_PLLC_BASE_REF_DIS __BIT(29)
sys/arch/arm/nvidia/tegra210_carreg.h
92
#define CAR_PLLC_BASE_LOCK_OVERRIDE __BIT(27)
sys/arch/arm/nvidia/tegra210_carreg.h
93
#define CAR_PLLC_BASE_LOCK __BIT(26)
sys/arch/arm/nvidia/tegra210_carreg.h
99
#define CAR_PLLU_BASE_BYPASS __BIT(31)
sys/arch/arm/nvidia/tegra210_xusbpad.c
100
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_LOCKDET_STATUS __BIT(15)
sys/arch/arm/nvidia/tegra210_xusbpad.c
102
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_BYPASS_ENABLE __BIT(7)
sys/arch/arm/nvidia/tegra210_xusbpad.c
103
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREERUN_ENABLE __BIT(6)
sys/arch/arm/nvidia/tegra210_xusbpad.c
104
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_PWR_OVRD __BIT(4)
sys/arch/arm/nvidia/tegra210_xusbpad.c
105
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_ENABLE __BIT(3)
sys/arch/arm/nvidia/tegra210_xusbpad.c
107
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_IDDQ __BIT(0)
sys/arch/arm/nvidia/tegra210_xusbpad.c
110
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_RESET __BIT(3)
sys/arch/arm/nvidia/tegra210_xusbpad.c
111
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_OVRD __BIT(2)
sys/arch/arm/nvidia/tegra210_xusbpad.c
112
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_DONE __BIT(1)
sys/arch/arm/nvidia/tegra210_xusbpad.c
113
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_EN __BIT(0)
sys/arch/arm/nvidia/tegra210_xusbpad.c
116
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_3_LOCKDET_RESET __BIT(0)
sys/arch/arm/nvidia/tegra210_xusbpad.c
118
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TCLKOUT_EN __BIT(28)
sys/arch/arm/nvidia/tegra210_xusbpad.c
120
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TXCLKREF_EN __BIT(15)
sys/arch/arm/nvidia/tegra210_xusbpad.c
122
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REFCLKBUF_EN __BIT(8)
sys/arch/arm/nvidia/tegra210_xusbpad.c
129
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_DONE __BIT(31)
sys/arch/arm/nvidia/tegra210_xusbpad.c
130
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_OVRD __BIT(15)
sys/arch/arm/nvidia/tegra210_xusbpad.c
131
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_CLK_EN __BIT(13)
sys/arch/arm/nvidia/tegra210_xusbpad.c
132
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_EN __BIT(12)
sys/arch/arm/nvidia/tegra210_xusbpad.c
141
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_LOCKDET_STATUS __BIT(15)
sys/arch/arm/nvidia/tegra210_xusbpad.c
143
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_BYPASS_ENABLE __BIT(7)
sys/arch/arm/nvidia/tegra210_xusbpad.c
144
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREERUN_ENABLE __BIT(6)
sys/arch/arm/nvidia/tegra210_xusbpad.c
145
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_PWR_OVRD __BIT(4)
sys/arch/arm/nvidia/tegra210_xusbpad.c
146
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_ENABLE __BIT(3)
sys/arch/arm/nvidia/tegra210_xusbpad.c
148
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_IDDQ __BIT(0)
sys/arch/arm/nvidia/tegra210_xusbpad.c
151
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_RESET __BIT(3)
sys/arch/arm/nvidia/tegra210_xusbpad.c
152
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_OVRD __BIT(2)
sys/arch/arm/nvidia/tegra210_xusbpad.c
153
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_DONE __BIT(1)
sys/arch/arm/nvidia/tegra210_xusbpad.c
154
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_EN __BIT(0)
sys/arch/arm/nvidia/tegra210_xusbpad.c
157
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_3_LOCKDET_RESET __BIT(0)
sys/arch/arm/nvidia/tegra210_xusbpad.c
159
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_TCLKOUT_EN __BIT(28)
sys/arch/arm/nvidia/tegra210_xusbpad.c
161
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_TXCLKREF_EN __BIT(15)
sys/arch/arm/nvidia/tegra210_xusbpad.c
163
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REFCLKBUF_EN __BIT(8)
sys/arch/arm/nvidia/tegra210_xusbpad.c
170
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_DONE __BIT(31)
sys/arch/arm/nvidia/tegra210_xusbpad.c
171
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_OVRD __BIT(15)
sys/arch/arm/nvidia/tegra210_xusbpad.c
172
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_CLK_EN __BIT(13)
sys/arch/arm/nvidia/tegra210_xusbpad.c
173
#define XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_EN __BIT(12)
sys/arch/arm/nvidia/tegra210_xusbpad.c
50
#define XUSB_PADCTL_VBUS_OC_MAP_VBUS_ENABLE(n) __BIT((n) * 5)
sys/arch/arm/nvidia/tegra210_xusbpad.c
53
#define XUSB_PADCTL_OC_DET_OC_DETECTED_VBUS_PAD(n) __BIT(12 + (n))
sys/arch/arm/nvidia/tegra210_xusbpad.c
54
#define XUSB_PADCTL_OC_DET_OC_DETECTED(n) __BIT(8 + (n))
sys/arch/arm/nvidia/tegra210_xusbpad.c
55
#define XUSB_PADCTL_OC_DET_SET_OC_DETECTED(n) __BIT(0 + (n))
sys/arch/arm/nvidia/tegra210_xusbpad.c
58
#define XUSB_PADCTL_ELPG_PROGRAM_1_AUX_MUX_LP0_VCORE_DOWN __BIT(31)
sys/arch/arm/nvidia/tegra210_xusbpad.c
59
#define XUSB_PADCTL_ELPG_PROGRAM_1_AUX_MUX_LP0_CLAMP_EN_EARLY __BIT(30)
sys/arch/arm/nvidia/tegra210_xusbpad.c
60
#define XUSB_PADCTL_ELPG_PROGRAM_1_AUX_MUX_LP0_CLAMP_EN __BIT(29)
sys/arch/arm/nvidia/tegra210_xusbpad.c
602
XUSBPAD_LANE("hsic-0", 0, 0x04, __BIT(14), tegra210_xusbpad_hsic_func,
sys/arch/arm/nvidia/tegra210_xusbpad.c
604
XUSBPAD_LANE("hsic-1", 1, 0x04, __BIT(15), tegra210_xusbpad_hsic_func,
sys/arch/arm/nvidia/tegra210_xusbpad.c
61
#define XUSB_PADCTL_ELPG_PROGRAM_1_SSPn_ELPG_VCORE_DOWN(n) __BIT((n) * 3 + 2)
sys/arch/arm/nvidia/tegra210_xusbpad.c
62
#define XUSB_PADCTL_ELPG_PROGRAM_1_SSPn_ELPG_CLAMP_EN_EARLY(n) __BIT((n) * 3 + 1)
sys/arch/arm/nvidia/tegra210_xusbpad.c
63
#define XUSB_PADCTL_ELPG_PROGRAM_1_SSPn_ELPG_CLAMP_EN(n) __BIT((n) * 3 + 0)
sys/arch/arm/nvidia/tegra210_xusbpad.c
644
XUSBPAD_PORT("usb2-0", 0, 0x08, __BITS(1,0), __BIT(2)),
sys/arch/arm/nvidia/tegra210_xusbpad.c
645
XUSBPAD_PORT("usb2-1", 1, 0x08, __BITS(5,4), __BIT(6)),
sys/arch/arm/nvidia/tegra210_xusbpad.c
646
XUSBPAD_PORT("usb2-2", 2, 0x08, __BITS(9,8), __BIT(10)),
sys/arch/arm/nvidia/tegra210_xusbpad.c
647
XUSBPAD_PORT("usb2-3", 3, 0x08, __BITS(13,12), __BIT(14)),
sys/arch/arm/nvidia/tegra210_xusbpad.c
651
XUSBPAD_PORT("usb3-0", 0, 0x14, __BITS(3,0), __BIT(4)),
sys/arch/arm/nvidia/tegra210_xusbpad.c
652
XUSBPAD_PORT("usb3-1", 1, 0x14, __BITS(8,5), __BIT(9)),
sys/arch/arm/nvidia/tegra210_xusbpad.c
653
XUSBPAD_PORT("usb3-2", 2, 0x14, __BITS(13,10), __BIT(14)),
sys/arch/arm/nvidia/tegra210_xusbpad.c
654
XUSBPAD_PORT("usb3-3", 3, 0x14, __BITS(18,15), __BIT(19)),
sys/arch/arm/nvidia/tegra210_xusbpad.c
66
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE(n) __BIT(8 + (n))
sys/arch/arm/nvidia/tegra210_xusbpad.c
67
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE(n) __BIT(1 + (n))
sys/arch/arm/nvidia/tegra210_xusbpad.c
71
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADn_CTL_1_VREG_FIX18 __BIT(6)
sys/arch/arm/nvidia/tegra210_xusbpad.c
74
#define XUSB_PADCTL_USB2_OTG_PADn_CTL_0_PD_ZI __BIT(29)
sys/arch/arm/nvidia/tegra210_xusbpad.c
75
#define XUSB_PADCTL_USB2_OTG_PADn_CTL_0_PD2 __BIT(27)
sys/arch/arm/nvidia/tegra210_xusbpad.c
76
#define XUSB_PADCTL_USB2_OTG_PADn_CTL_0_PD __BIT(26)
sys/arch/arm/nvidia/tegra210_xusbpad.c
82
#define XUSB_PADCTL_USB2_OTG_PADn_CTL_1_PD_DR __BIT(2)
sys/arch/arm/nvidia/tegra210_xusbpad.c
83
#define XUSB_PADCTL_USB2_OTG_PADn_CTL_1_PD_DISC_OVRD __BIT(1)
sys/arch/arm/nvidia/tegra210_xusbpad.c
84
#define XUSB_PADCTL_USB2_OTG_PADn_CTL_1_PD_CHRP_OVRD __BIT(0)
sys/arch/arm/nvidia/tegra210_xusbpad.c
87
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_PD __BIT(11)
sys/arch/arm/nvidia/tegra210_xusbpad.c
92
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_PD_TRK __BIT(26)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
100
#define TEGRA_T_SATA0_INDEX_CH3 __BIT(2)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
101
#define TEGRA_T_SATA0_INDEX_CH2 __BIT(1)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
102
#define TEGRA_T_SATA0_INDEX_CH1 __BIT(0)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
35
#define TEGRA_SATA_FPCI_BAR_ACCESS_TYPE __BIT(0)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
38
#define TEGRA_SATA_CONFIGURATION_CLKEN_OVERRIDE __BIT(31)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
39
#define TEGRA_SATA_CONFIGURATION_EN_FPCI __BIT(0)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
42
#define TEGRA_SATA_INTR_MASK_IP_INT __BIT(16)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
43
#define TEGRA_SATA_INTR_MASK_MSI __BIT(8)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
44
#define TEGRA_SATA_INTR_MASK_INT __BIT(0)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
47
#define TEGRA_T_SATA0_CFG1_INTR_DISABLE __BIT(10)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
48
#define TEGRA_T_SATA0_CFG1_SERR __BIT(8)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
49
#define TEGRA_T_SATA0_CFG1_BUS_MASTER __BIT(2)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
50
#define TEGRA_T_SATA0_CFG1_MEM_SPACE __BIT(1)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
51
#define TEGRA_T_SATA0_CFG1_IO_SPACE __BIT(0)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
56
#define TEGRA_T_SATA0_CFG9_SPACE_TYPE __BIT(0)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
59
#define TEGRA_SATA_AUX_MISC_CNTL_1_AUX_OR_CORE_IDLE_STATUS_SEL __BIT(18)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
60
#define TEGRA_SATA_AUX_MISC_CNTL_1_SDS_SUPPORT __BIT(13)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
61
#define TEGRA_SATA_AUX_MISC_CNTL_1_OOB_ON_POR __BIT(7)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
64
#define TEGRA_SATA_AUX_RX_STAT_INT_SATA_RX_STAT_INT_DISABLE __BIT(2)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
72
#define TEGRA_T_SATA0_CFG_PHY_0_MASK_SQUELCH __BIT(24)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
73
#define TEGRA_T_SATA0_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD __BIT(11)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
76
#define TEGRA_T_SATA0_CFG_PHY_1_PADS_IDDQ_EN __BIT(23)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
77
#define TEGRA_T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN __BIT(22)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
83
#define TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SALP __BIT(26)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
84
#define TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM __BIT(17)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
85
#define TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP __BIT(14)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
86
#define TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP __BIT(13)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
93
#define TEGRA_T_SATA0_CFG_POWER_GATE_SSTS_RESTORED __BIT(23)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
96
#define TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN __BIT(12)
sys/arch/arm/nvidia/tegra_ahcisatareg.h
99
#define TEGRA_T_SATA0_INDEX_CH4 __BIT(3)
sys/arch/arm/nvidia/tegra_apbdma.c
235
APBDMA_WRITE(sc, APBDMA_IRQ_MASK_SET_REG, __BIT(n));
sys/arch/arm/nvidia/tegra_apbdma.c
252
APBDMA_WRITE(sc, APBDMA_IRQ_MASK_CLR_REG, __BIT(n));
sys/arch/arm/nvidia/tegra_apbdmareg.h
36
#define APBDMA_COMMAND_GEN __BIT(31)
sys/arch/arm/nvidia/tegra_apbdmareg.h
60
#define APBDMACHAN_CSR_ENB __BIT(31)
sys/arch/arm/nvidia/tegra_apbdmareg.h
61
#define APBDMACHAN_CSR_IE_EOC __BIT(30)
sys/arch/arm/nvidia/tegra_apbdmareg.h
62
#define APBDMACHAN_CSR_HOLD __BIT(29)
sys/arch/arm/nvidia/tegra_apbdmareg.h
63
#define APBDMACHAN_CSR_DIR __BIT(28)
sys/arch/arm/nvidia/tegra_apbdmareg.h
64
#define APBDMACHAN_CSR_ONCE __BIT(27)
sys/arch/arm/nvidia/tegra_apbdmareg.h
65
#define APBDMACHAN_CSR_FLOW __BIT(21)
sys/arch/arm/nvidia/tegra_apbdmareg.h
73
#define APBDMACHAN_AHB_SEQ_INTR_ENB __BIT(31)
sys/arch/arm/nvidia/tegra_apbdmareg.h
76
#define APBDMACHAN_AHB_SEQ_DATA_SWAP __BIT(27)
sys/arch/arm/nvidia/tegra_apbdmareg.h
81
#define APBDMACHAN_AHB_SEQ_DBL_BUF __BIT(19)
sys/arch/arm/nvidia/tegra_apbdmareg.h
98
#define APBDMACHAN_APB_SEQ_DATA_SWAP __BIT(27)
sys/arch/arm/nvidia/tegra_cecreg.h
33
#define CEC_SW_CONTROL_MODE __BIT(31)
sys/arch/arm/nvidia/tegra_cecreg.h
34
#define CEC_SW_CONTROL_FILTERED_RX_DATA_PIN __BIT(4)
sys/arch/arm/nvidia/tegra_cecreg.h
35
#define CEC_SW_CONTROL_RAW_INPUT_DATA_PIN __BIT(0)
sys/arch/arm/nvidia/tegra_cecreg.h
38
#define CEC_HW_CONTROL_TX_RX_MODE __BIT(31)
sys/arch/arm/nvidia/tegra_cecreg.h
39
#define CEC_HW_CONTROL_FAST_SIM_MODE __BIT(30)
sys/arch/arm/nvidia/tegra_cecreg.h
40
#define CEC_HW_CONTROL_TX_NAK_MODE __BIT(24)
sys/arch/arm/nvidia/tegra_cecreg.h
41
#define CEC_HW_CONTROL_RX_NAK_MODE __BIT(16)
sys/arch/arm/nvidia/tegra_cecreg.h
42
#define CEC_HW_CONTROL_RX_SNOOP __BIT(15)
sys/arch/arm/nvidia/tegra_cecreg.h
46
#define CEC_INPUT_FILTER_MODE __BIT(31)
sys/arch/arm/nvidia/tegra_cecreg.h
52
#define CEC_TX_REGISTER_RETRY_FRAME __BIT(17)
sys/arch/arm/nvidia/tegra_cecreg.h
53
#define CEC_TX_REGISTER_GENERATE_START_BIT __BIT(16)
sys/arch/arm/nvidia/tegra_cecreg.h
54
#define CEC_TX_REGISTER_ADDRESS_MODE __BIT(12)
sys/arch/arm/nvidia/tegra_cecreg.h
55
#define CEC_TX_REGISTER_EOM __BIT(8)
sys/arch/arm/nvidia/tegra_cecreg.h
59
#define CEC_RX_REGISTER_ACK __BIT(9)
sys/arch/arm/nvidia/tegra_cecreg.h
60
#define CEC_RX_REGISTER_EOM __BIT(8)
sys/arch/arm/nvidia/tegra_cecreg.h
72
#define CEC_INT_FILTERED_RX_DATA_PIN_TRANSITION_L2H __BIT(14)
sys/arch/arm/nvidia/tegra_cecreg.h
73
#define CEC_INT_FILTERED_RX_DATA_PIN_TRANSITION_H2L __BIT(13)
sys/arch/arm/nvidia/tegra_cecreg.h
74
#define CEC_INT_RX_BUS_ERROR_DETECTED __BIT(12)
sys/arch/arm/nvidia/tegra_cecreg.h
75
#define CEC_INT_RX_BUS_ANOMALY_DETECTED __BIT(11)
sys/arch/arm/nvidia/tegra_cecreg.h
76
#define CEC_INT_RX_START_BIT_DETECTED __BIT(10)
sys/arch/arm/nvidia/tegra_cecreg.h
77
#define CEC_INT_RX_REGISTER_OVERRUN __BIT(9)
sys/arch/arm/nvidia/tegra_cecreg.h
78
#define CEC_INT_RX_REGISTER_FULL __BIT(8)
sys/arch/arm/nvidia/tegra_cecreg.h
79
#define CEC_INT_TX_FRAME_TRANSMITTED __BIT(5)
sys/arch/arm/nvidia/tegra_cecreg.h
80
#define CEC_INT_TX_BUS_ANOMALY_DETECTED __BIT(4)
sys/arch/arm/nvidia/tegra_cecreg.h
81
#define CEC_INT_TX_ARBITRATION_FAILED __BIT(3)
sys/arch/arm/nvidia/tegra_cecreg.h
82
#define CEC_INT_TX_FRAME_OR_BLOCK_NAKD __BIT(2)
sys/arch/arm/nvidia/tegra_cecreg.h
83
#define CEC_INT_TX_REGISTER_UNDERRUN __BIT(1)
sys/arch/arm/nvidia/tegra_cecreg.h
84
#define CEC_INT_TX_REGISTER_EMPTY __BIT(0)
sys/arch/arm/nvidia/tegra_dcreg.h
100
#define DC_CMD_STATE_CONTROL_WIN_A_ACT_REQ __BIT(1)
sys/arch/arm/nvidia/tegra_dcreg.h
101
#define DC_CMD_STATE_CONTROL_GENERAL_ACT_REQ __BIT(0)
sys/arch/arm/nvidia/tegra_dcreg.h
104
#define DC_CMD_DISPLAY_WINDOW_HEADER_WINDOW_D_SELECT __BIT(7)
sys/arch/arm/nvidia/tegra_dcreg.h
105
#define DC_CMD_DISPLAY_WINDOW_HEADER_WINDOW_C_SELECT __BIT(6)
sys/arch/arm/nvidia/tegra_dcreg.h
106
#define DC_CMD_DISPLAY_WINDOW_HEADER_WINDOW_B_SELECT __BIT(5)
sys/arch/arm/nvidia/tegra_dcreg.h
107
#define DC_CMD_DISPLAY_WINDOW_HEADER_WINDOW_A_SELECT __BIT(4)
sys/arch/arm/nvidia/tegra_dcreg.h
144
#define DC_DISP_DISP_SIGNAL_OPTIONS0_M1_ENABLE __BIT(26)
sys/arch/arm/nvidia/tegra_dcreg.h
145
#define DC_DISP_DISP_SIGNAL_OPTIONS0_M0_ENABLE __BIT(24)
sys/arch/arm/nvidia/tegra_dcreg.h
146
#define DC_DISP_DISP_SIGNAL_OPTIONS0_V_PULSE3_ENABLE __BIT(20)
sys/arch/arm/nvidia/tegra_dcreg.h
147
#define DC_DISP_DISP_SIGNAL_OPTIONS0_V_PULSE2_ENABLE __BIT(19)
sys/arch/arm/nvidia/tegra_dcreg.h
148
#define DC_DISP_DISP_SIGNAL_OPTIONS0_V_PULSE1_ENABLE __BIT(18)
sys/arch/arm/nvidia/tegra_dcreg.h
149
#define DC_DISP_DISP_SIGNAL_OPTIONS0_V_PULSE0_ENABLE __BIT(16)
sys/arch/arm/nvidia/tegra_dcreg.h
150
#define DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE2_ENABLE __BIT(12)
sys/arch/arm/nvidia/tegra_dcreg.h
151
#define DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE1_ENABLE __BIT(10)
sys/arch/arm/nvidia/tegra_dcreg.h
152
#define DC_DISP_DISP_SIGNAL_OPTIONS0_H_PULSE0_ENABLE __BIT(8)
sys/arch/arm/nvidia/tegra_dcreg.h
155
#define DC_DISP_DISP_WIN_OPTIONS_HDMI_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra_dcreg.h
156
#define DC_DISP_DISP_WIN_OPTIONS_DSI_ENABLE __BIT(29)
sys/arch/arm/nvidia/tegra_dcreg.h
157
#define DC_DISP_DISP_WIN_OPTIONS_SOR_ENABLE __BIT(25)
sys/arch/arm/nvidia/tegra_dcreg.h
158
#define DC_DISP_DISP_WIN_OPTIONS_CURSOR_ENABLE __BIT(16)
sys/arch/arm/nvidia/tegra_dcreg.h
199
#define DC_DISP_H_PULSE2_CONTROL_POLARITY __BIT(4)
sys/arch/arm/nvidia/tegra_dcreg.h
200
#define DC_DISP_H_PULSE2_CONTROL_MODE __BIT(3)
sys/arch/arm/nvidia/tegra_dcreg.h
294
#define DC_DISP_BLEND_CURSOR_CONTROL_MODE_SEL __BIT(24)
sys/arch/arm/nvidia/tegra_dcreg.h
370
#define DC_WINC_A_WIN_OPTIONS_H_FILTER_MODE __BIT(31)
sys/arch/arm/nvidia/tegra_dcreg.h
371
#define DC_WINC_A_WIN_OPTIONS_WIN_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra_dcreg.h
372
#define DC_WINC_A_WIN_OPTIONS_INTERLACE_ENABLE __BIT(23)
sys/arch/arm/nvidia/tegra_dcreg.h
373
#define DC_WINC_A_WIN_OPTIONS_YUV_RANGE_EXPAND __BIT(22)
sys/arch/arm/nvidia/tegra_dcreg.h
374
#define DC_WINC_A_WIN_OPTIONS_DV_ENABLE __BIT(20)
sys/arch/arm/nvidia/tegra_dcreg.h
375
#define DC_WINC_A_WIN_OPTIONS_CSC_ENABLE __BIT(18)
sys/arch/arm/nvidia/tegra_dcreg.h
376
#define DC_WINC_A_WIN_OPTIONS_CP_ENABLE __BIT(16)
sys/arch/arm/nvidia/tegra_dcreg.h
377
#define DC_WINC_A_WIN_OPTIONS_V_FILTER_UV_ALIGN __BIT(14)
sys/arch/arm/nvidia/tegra_dcreg.h
378
#define DC_WINC_A_WIN_OPTIONS_V_FILTER_OPTIMIZE __BIT(12)
sys/arch/arm/nvidia/tegra_dcreg.h
379
#define DC_WINC_A_WIN_OPTIONS_V_FILTER_ENABLE __BIT(10)
sys/arch/arm/nvidia/tegra_dcreg.h
380
#define DC_WINC_A_WIN_OPTIONS_H_FILTER_ENABLE __BIT(8)
sys/arch/arm/nvidia/tegra_dcreg.h
381
#define DC_WINC_A_WIN_OPTIONS_COLOR_EXPAND __BIT(6)
sys/arch/arm/nvidia/tegra_dcreg.h
382
#define DC_WINC_A_WIN_OPTIONS_SCAN_COLUMN __BIT(4)
sys/arch/arm/nvidia/tegra_dcreg.h
383
#define DC_WINC_A_WIN_OPTIONS_V_DIRECTION __BIT(2)
sys/arch/arm/nvidia/tegra_dcreg.h
384
#define DC_WINC_A_WIN_OPTIONS_H_DIRECTION __BIT(0)
sys/arch/arm/nvidia/tegra_dcreg.h
58
#define DC_CMD_DISPLAY_COMMAND_RAISE __BIT(0)
sys/arch/arm/nvidia/tegra_dcreg.h
63
#define DC_CMD_DISPLAY_POWER_CONTROL_HSPI_ENABLE __BIT(25)
sys/arch/arm/nvidia/tegra_dcreg.h
64
#define DC_CMD_DISPLAY_POWER_CONTROL_SPI_ENABLE __BIT(24)
sys/arch/arm/nvidia/tegra_dcreg.h
65
#define DC_CMD_DISPLAY_POWER_CONTROL_PM1_ENABLE __BIT(18)
sys/arch/arm/nvidia/tegra_dcreg.h
66
#define DC_CMD_DISPLAY_POWER_CONTROL_PM0_ENABLE __BIT(16)
sys/arch/arm/nvidia/tegra_dcreg.h
67
#define DC_CMD_DISPLAY_POWER_CONTROL_PW4_ENABLE __BIT(8)
sys/arch/arm/nvidia/tegra_dcreg.h
68
#define DC_CMD_DISPLAY_POWER_CONTROL_PW3_ENABLE __BIT(6)
sys/arch/arm/nvidia/tegra_dcreg.h
69
#define DC_CMD_DISPLAY_POWER_CONTROL_PW2_ENABLE __BIT(4)
sys/arch/arm/nvidia/tegra_dcreg.h
70
#define DC_CMD_DISPLAY_POWER_CONTROL_PW1_ENABLE __BIT(2)
sys/arch/arm/nvidia/tegra_dcreg.h
71
#define DC_CMD_DISPLAY_POWER_CONTROL_PW0_ENABLE __BIT(0)
sys/arch/arm/nvidia/tegra_dcreg.h
76
#define DC_CMD_INT_V_BLANK __BIT(2)
sys/arch/arm/nvidia/tegra_dcreg.h
85
#define DC_CMD_STATE_ACCESS_WRITE_MUX __BIT(2)
sys/arch/arm/nvidia/tegra_dcreg.h
86
#define DC_CMD_STATE_ACCESS_READ_MUX __BIT(0)
sys/arch/arm/nvidia/tegra_dcreg.h
89
#define DC_CMD_STATE_CONTROL_NC_HOST_TRIG_ENABLE __BIT(24)
sys/arch/arm/nvidia/tegra_dcreg.h
90
#define DC_CMD_STATE_CONTROL_CURSOR_UPDATE __BIT(15)
sys/arch/arm/nvidia/tegra_dcreg.h
91
#define DC_CMD_STATE_CONTROL_WIN_D_UPDATE __BIT(12)
sys/arch/arm/nvidia/tegra_dcreg.h
92
#define DC_CMD_STATE_CONTROL_WIN_C_UPDATE __BIT(11)
sys/arch/arm/nvidia/tegra_dcreg.h
93
#define DC_CMD_STATE_CONTROL_WIN_B_UPDATE __BIT(10)
sys/arch/arm/nvidia/tegra_dcreg.h
94
#define DC_CMD_STATE_CONTROL_WIN_A_UPDATE __BIT(9)
sys/arch/arm/nvidia/tegra_dcreg.h
95
#define DC_CMD_STATE_CONTROL_GENERAL_UPDATE __BIT(8)
sys/arch/arm/nvidia/tegra_dcreg.h
96
#define DC_CMD_STATE_CONTROL_CURSOR_ACT_REQ __BIT(7)
sys/arch/arm/nvidia/tegra_dcreg.h
97
#define DC_CMD_STATE_CONTROL_WIN_D_ACT_REQ __BIT(4)
sys/arch/arm/nvidia/tegra_dcreg.h
98
#define DC_CMD_STATE_CONTROL_WIN_C_ACT_REQ __BIT(3)
sys/arch/arm/nvidia/tegra_dcreg.h
99
#define DC_CMD_STATE_CONTROL_WIN_B_ACT_REQ __BIT(2)
sys/arch/arm/nvidia/tegra_gpio.c
218
if ((cnf & __BIT(pin)) == 0)
sys/arch/arm/nvidia/tegra_gpio.c
309
if ((cnf & __BIT(pin)) == 0)
sys/arch/arm/nvidia/tegra_gpio.c
310
GPIO_WRITE(&gbank, GPIO_CNF_REG, cnf | __BIT(pin));
sys/arch/arm/nvidia/tegra_gpio.c
404
if ((cnf & __BIT(pin)) == 0)
sys/arch/arm/nvidia/tegra_gpio.c
405
GPIO_WRITE(&bank, GPIO_CNF_REG, cnf | __BIT(pin));
sys/arch/arm/nvidia/tegra_hdaudioreg.h
35
#define TEGRA_HDA_IFPS_CONFIG_FPCI_EN __BIT(0)
sys/arch/arm/nvidia/tegra_hdaudioreg.h
38
#define TEGRA_HDA_IFPS_INTR_EN __BIT(16)
sys/arch/arm/nvidia/tegra_hdaudioreg.h
41
#define TEGRA_HDA_CFG_CMD_DISABLE_INTR __BIT(10)
sys/arch/arm/nvidia/tegra_hdaudioreg.h
42
#define TEGRA_HDA_CFG_CMD_ENABLE_SERR __BIT(8)
sys/arch/arm/nvidia/tegra_hdaudioreg.h
43
#define TEGRA_HDA_CFG_CMD_BUS_MASTER __BIT(2)
sys/arch/arm/nvidia/tegra_hdaudioreg.h
44
#define TEGRA_HDA_CFG_CMD_MEM_SPACE __BIT(1)
sys/arch/arm/nvidia/tegra_hdaudioreg.h
45
#define TEGRA_HDA_CFG_CMD_IO_SPACE __BIT(0)
sys/arch/arm/nvidia/tegra_hdaudioreg.h
48
#define TEGRA_HDA_CFG_BAR0_START __BIT(6)
sys/arch/arm/nvidia/tegra_hdmireg.h
121
#define HDMI_NV_PDISP_HDMI_CTRL_ENABLE __BIT(30)
sys/arch/arm/nvidia/tegra_hdmireg.h
122
#define HDMI_NV_PDISP_HDMI_CTRL_CA_SELECT __BIT(28)
sys/arch/arm/nvidia/tegra_hdmireg.h
123
#define HDMI_NV_PDISP_HDMI_CTRL_SS_SELECT __BIT(27)
sys/arch/arm/nvidia/tegra_hdmireg.h
124
#define HDMI_NV_PDISP_HDMI_CTRL_SF_SELECT __BIT(26)
sys/arch/arm/nvidia/tegra_hdmireg.h
125
#define HDMI_NV_PDISP_HDMI_CTRL_CC_SELECT __BIT(25)
sys/arch/arm/nvidia/tegra_hdmireg.h
126
#define HDMI_NV_PDISP_HDMI_CTRL_CT_SELECT __BIT(24)
sys/arch/arm/nvidia/tegra_hdmireg.h
128
#define HDMI_NV_PDISP_HDMI_CTRL_SAMPLE_FLAT __BIT(12)
sys/arch/arm/nvidia/tegra_hdmireg.h
129
#define HDMI_NV_PDISP_HDMI_CTRL_AUDIO_LAYOUT_SELECT __BIT(10)
sys/arch/arm/nvidia/tegra_hdmireg.h
130
#define HDMI_NV_PDISP_HDMI_CTRL_AUDIO_LAYOUT __BIT(8)
sys/arch/arm/nvidia/tegra_hdmireg.h
145
#define HDMI_NV_PDISP_HDMI_SPARE_HW_CTS __BIT(0)
sys/arch/arm/nvidia/tegra_hdmireg.h
146
#define HDMI_NV_PDISP_HDMI_SPARE_FORCE_SW_CTS __BIT(1)
sys/arch/arm/nvidia/tegra_hdmireg.h
154
#define HDMI_NV_PDISP_INPUT_CONTROL_ARM_VIDEO_RANGE __BIT(1)
sys/arch/arm/nvidia/tegra_hdmireg.h
155
#define HDMI_NV_PDISP_INPUT_CONTROL_HDMI_SRC_SELECT __BIT(0)
sys/arch/arm/nvidia/tegra_hdmireg.h
188
#define HDMI_NV_PDISP_SOR_PWR_SETTING_NEW __BIT(31)
sys/arch/arm/nvidia/tegra_hdmireg.h
189
#define HDMI_NV_PDISP_SOR_PWR_MODE __BIT(28)
sys/arch/arm/nvidia/tegra_hdmireg.h
190
#define HDMI_NV_PDISP_SOR_PWR_HALT_DELAY __BIT(24)
sys/arch/arm/nvidia/tegra_hdmireg.h
191
#define HDMI_NV_PDISP_SOR_PWR_SAFE_START __BIT(17)
sys/arch/arm/nvidia/tegra_hdmireg.h
192
#define HDMI_NV_PDISP_SOR_PWR_SAFE_STATE __BIT(16)
sys/arch/arm/nvidia/tegra_hdmireg.h
193
#define HDMI_NV_PDISP_SOR_PWR_NORMAL_START __BIT(1)
sys/arch/arm/nvidia/tegra_hdmireg.h
194
#define HDMI_NV_PDISP_SOR_PWR_NORMAL_STATE __BIT(0)
sys/arch/arm/nvidia/tegra_hdmireg.h
204
#define HDMI_NV_PDISP_SOR_PLL0_PULLDOWN __BIT(5)
sys/arch/arm/nvidia/tegra_hdmireg.h
205
#define HDMI_NV_PDISP_SOR_PLL0_RESISTORSEL __BIT(4)
sys/arch/arm/nvidia/tegra_hdmireg.h
206
#define HDMI_NV_PDISP_SOR_PLL0_PDPORT __BIT(3)
sys/arch/arm/nvidia/tegra_hdmireg.h
207
#define HDMI_NV_PDISP_SOR_PLL0_VCOPD __BIT(2)
sys/arch/arm/nvidia/tegra_hdmireg.h
208
#define HDMI_NV_PDISP_SOR_PLL0_PDBG __BIT(1)
sys/arch/arm/nvidia/tegra_hdmireg.h
209
#define HDMI_NV_PDISP_SOR_PLL0_PWR __BIT(0)
sys/arch/arm/nvidia/tegra_hdmireg.h
217
#define HDMI_NV_PDISP_SOR_CSTM_PLLDIV __BIT(21)
sys/arch/arm/nvidia/tegra_hdmireg.h
218
#define HDMI_NV_PDISP_SOR_CSTM_BALANCED __BIT(19)
sys/arch/arm/nvidia/tegra_hdmireg.h
219
#define HDMI_NV_PDISP_SOR_CSTM_NEW_MODE __BIT(18)
sys/arch/arm/nvidia/tegra_hdmireg.h
220
#define HDMI_NV_PDISP_SOR_CSTM_DUP_SYNC __BIT(17)
sys/arch/arm/nvidia/tegra_hdmireg.h
221
#define HDMI_NV_PDISP_SOR_CSTM_LVDS_EN __BIT(16)
sys/arch/arm/nvidia/tegra_hdmireg.h
222
#define HDMI_NV_PDISP_SOR_CSTM_LINKACTB __BIT(15)
sys/arch/arm/nvidia/tegra_hdmireg.h
223
#define HDMI_NV_PDISP_SOR_CSTM_LINKACTA __BIT(14)
sys/arch/arm/nvidia/tegra_hdmireg.h
227
#define HDMI_NV_PDISP_SOR_CSTM_UPPER __BIT(11)
sys/arch/arm/nvidia/tegra_hdmireg.h
228
#define HDMI_NV_PDISP_SOR_CSTM_PD_TXCB __BIT(9)
sys/arch/arm/nvidia/tegra_hdmireg.h
229
#define HDMI_NV_PDISP_SOR_CSTM_PD_TXCA __BIT(8)
sys/arch/arm/nvidia/tegra_hdmireg.h
230
#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_3 __BIT(7)
sys/arch/arm/nvidia/tegra_hdmireg.h
231
#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_2 __BIT(6)
sys/arch/arm/nvidia/tegra_hdmireg.h
232
#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_1 __BIT(5)
sys/arch/arm/nvidia/tegra_hdmireg.h
233
#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDB_0 __BIT(4)
sys/arch/arm/nvidia/tegra_hdmireg.h
234
#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_3 __BIT(3)
sys/arch/arm/nvidia/tegra_hdmireg.h
235
#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_2 __BIT(2)
sys/arch/arm/nvidia/tegra_hdmireg.h
236
#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_1 __BIT(1)
sys/arch/arm/nvidia/tegra_hdmireg.h
237
#define HDMI_NV_PDISP_SOR_CSTM_PD_TXDA_0 __BIT(0)
sys/arch/arm/nvidia/tegra_hdmireg.h
244
#define HDMI_NV_PDISP_SOR_BLANK_STATUS __BIT(2)
sys/arch/arm/nvidia/tegra_hdmireg.h
245
#define HDMI_NV_PDISP_SOR_BLANK_TRANSITION __BIT(1)
sys/arch/arm/nvidia/tegra_hdmireg.h
246
#define HDMI_NV_PDISP_SOR_BLANK_OVERRIDE __BIT(0)
sys/arch/arm/nvidia/tegra_hdmireg.h
249
#define HDMI_NV_PDISP_SOR_SEQ_CTL_SWITCH __BIT(30)
sys/arch/arm/nvidia/tegra_hdmireg.h
250
#define HDMI_NV_PDISP_SOR_SEQ_CTL_STATUS __BIT(28)
sys/arch/arm/nvidia/tegra_hdmireg.h
273
#define HDMI_NV_PDISP_SOR_SEQ_INST_PLL_PULLDOWN __BIT(31)
sys/arch/arm/nvidia/tegra_hdmireg.h
274
#define HDMI_NV_PDISP_SOR_SEQ_INST_POWERDOWN_MACRO __BIT(30)
sys/arch/arm/nvidia/tegra_hdmireg.h
275
#define HDMI_NV_PDISP_SOR_SEQ_INST_ASSERT_PLL_RESETV __BIT(29)
sys/arch/arm/nvidia/tegra_hdmireg.h
276
#define HDMI_NV_PDISP_SOR_SEQ_INST_BLANK_V __BIT(28)
sys/arch/arm/nvidia/tegra_hdmireg.h
277
#define HDMI_NV_PDISP_SOR_SEQ_INST_BLANK_H __BIT(27)
sys/arch/arm/nvidia/tegra_hdmireg.h
278
#define HDMI_NV_PDISP_SOR_SEQ_INST_BLANK_DE __BIT(26)
sys/arch/arm/nvidia/tegra_hdmireg.h
279
#define HDMI_NV_PDISP_SOR_SEQ_INST_BLACK_DATA __BIT(25)
sys/arch/arm/nvidia/tegra_hdmireg.h
280
#define HDMI_NV_PDISP_SOR_SEQ_INST_TRISTATE_IOS __BIT(24)
sys/arch/arm/nvidia/tegra_hdmireg.h
281
#define HDMI_NV_PDISP_SOR_SEQ_INST_DRIVE_PWM_OUT_LO __BIT(23)
sys/arch/arm/nvidia/tegra_hdmireg.h
282
#define HDMI_NV_PDISP_SOR_SEQ_INST_PIN_B __BIT(22)
sys/arch/arm/nvidia/tegra_hdmireg.h
283
#define HDMI_NV_PDISP_SOR_SEQ_INST_PIN_A __BIT(21)
sys/arch/arm/nvidia/tegra_hdmireg.h
284
#define HDMI_NV_PDISP_SOR_SEQ_INST_HALT __BIT(15)
sys/arch/arm/nvidia/tegra_hdmireg.h
302
#define HDMI_NV_PDISP_AUDIO_N_LOOKUP __BIT(28)
sys/arch/arm/nvidia/tegra_hdmireg.h
303
#define HDMI_NV_PDISP_AUDIO_N_GENERATE __BIT(24)
sys/arch/arm/nvidia/tegra_hdmireg.h
304
#define HDMI_NV_PDISP_AUDIO_N_RESETF __BIT(20)
sys/arch/arm/nvidia/tegra_hdmireg.h
308
#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_INPUT_MODE __BIT(31)
sys/arch/arm/nvidia/tegra_hdmireg.h
309
#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_INJECT_NULLSMPL __BIT(29)
sys/arch/arm/nvidia/tegra_hdmireg.h
323
#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_AFIFO_FLUSH __BIT(12)
sys/arch/arm/nvidia/tegra_hdmireg.h
324
#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_PORT_CONNECTIVITY __BIT(0)
sys/arch/arm/nvidia/tegra_hdmireg.h
38
#define HDMI_NV_PDISP_SOR_STATE0_UPDATE __BIT(0)
sys/arch/arm/nvidia/tegra_hdmireg.h
41
#define HDMI_NV_PDISP_SOR_STATE1_ARM_SHOW_VGA __BIT(4)
sys/arch/arm/nvidia/tegra_hdmireg.h
42
#define HDMI_NV_PDISP_SOR_STATE1_ATTACHED __BIT(3)
sys/arch/arm/nvidia/tegra_hdmireg.h
43
#define HDMI_NV_PDISP_SOR_STATE1_ASY_ORMODE __BIT(2)
sys/arch/arm/nvidia/tegra_hdmireg.h
50
#define HDMI_NV_PDISP_SOR_STATE2_ASY_DEPOL __BIT(14)
sys/arch/arm/nvidia/tegra_hdmireg.h
51
#define HDMI_NV_PDISP_SOR_STATE2_ASY_VSYNCPOL __BIT(13)
sys/arch/arm/nvidia/tegra_hdmireg.h
52
#define HDMI_NV_PDISP_SOR_STATE2_ASY_HSYNCPOL __BIT(12)
sys/arch/arm/nvidia/tegra_hdmireg.h
64
#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_CHKSUM_HW __BIT(9)
sys/arch/arm/nvidia/tegra_hdmireg.h
65
#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_SINGLE __BIT(8)
sys/arch/arm/nvidia/tegra_hdmireg.h
66
#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_OTHER __BIT(4)
sys/arch/arm/nvidia/tegra_hdmireg.h
67
#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL_ENABLE __BIT(0)
sys/arch/arm/nvidia/tegra_hdmireg.h
75
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW __BIT(9)
sys/arch/arm/nvidia/tegra_hdmireg.h
76
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_SINGLE __BIT(8)
sys/arch/arm/nvidia/tegra_hdmireg.h
77
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_OTHER __BIT(4)
sys/arch/arm/nvidia/tegra_hdmireg.h
78
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL_ENABLE __BIT(0)
sys/arch/arm/nvidia/tegra_hdmireg.h
88
#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_AUDIO __BIT(16)
sys/arch/arm/nvidia/tegra_hdmireg.h
89
#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_HBLANK __BIT(12)
sys/arch/arm/nvidia/tegra_hdmireg.h
90
#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_SINGLE __BIT(8)
sys/arch/arm/nvidia/tegra_hdmireg.h
91
#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_OTHER __BIT(4)
sys/arch/arm/nvidia/tegra_hdmireg.h
92
#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL_ENABLE __BIT(0)
sys/arch/arm/nvidia/tegra_i2creg.h
100
#define I2C_FIFO_STATUS_SLV_XFER_ERR_REASON __BIT(25)
sys/arch/arm/nvidia/tegra_i2creg.h
107
#define I2C_INTERRUPT_MASK_TIMEOUT __BIT(8)
sys/arch/arm/nvidia/tegra_i2creg.h
108
#define I2C_INTERRUPT_MASK_PACKET_XFER_COMPLETE __BIT(7)
sys/arch/arm/nvidia/tegra_i2creg.h
109
#define I2C_INTERRUPT_MASK_ALL_PACKETS_XFER_COMPLETE __BIT(6)
sys/arch/arm/nvidia/tegra_i2creg.h
110
#define I2C_INTERRUPT_MASK_NOACK __BIT(3)
sys/arch/arm/nvidia/tegra_i2creg.h
111
#define I2C_INTERRUPT_MASK_ARB_LOST __BIT(2)
sys/arch/arm/nvidia/tegra_i2creg.h
112
#define I2C_INTERRUPT_MASK_TFIFO_DATA_REQ __BIT(1)
sys/arch/arm/nvidia/tegra_i2creg.h
113
#define I2C_INTERRUPT_MASK_RFIFO_DATA_REQ __BIT(0)
sys/arch/arm/nvidia/tegra_i2creg.h
116
#define I2C_INTERRUPT_STATUS_TIMEOUT __BIT(8)
sys/arch/arm/nvidia/tegra_i2creg.h
117
#define I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE __BIT(7)
sys/arch/arm/nvidia/tegra_i2creg.h
118
#define I2C_INTERRUPT_STATUS_ALL_PACKETS_XFER_COMPLETE __BIT(6)
sys/arch/arm/nvidia/tegra_i2creg.h
119
#define I2C_INTERRUPT_STATUS_NOACK __BIT(3)
sys/arch/arm/nvidia/tegra_i2creg.h
120
#define I2C_INTERRUPT_STATUS_ARB_LOST __BIT(2)
sys/arch/arm/nvidia/tegra_i2creg.h
121
#define I2C_INTERRUPT_STATUS_TFIFO_DATA_REQ __BIT(1)
sys/arch/arm/nvidia/tegra_i2creg.h
122
#define I2C_INTERRUPT_STATUS_RFIFO_DATA_REQ __BIT(0)
sys/arch/arm/nvidia/tegra_i2creg.h
137
#define I2C_BUS_CONFIG_LOAD_TIMEOUT_CONFIG_LOAD __BIT(2)
sys/arch/arm/nvidia/tegra_i2creg.h
138
#define I2C_BUS_CONFIG_LOAD_SLV_CONFIG_LOAD __BIT(1)
sys/arch/arm/nvidia/tegra_i2creg.h
139
#define I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD __BIT(0)
sys/arch/arm/nvidia/tegra_i2creg.h
167
#define I2C_IOPACKET_XMITHDR_RESP_PKT_FREQ __BIT(25)
sys/arch/arm/nvidia/tegra_i2creg.h
168
#define I2C_IOPACKET_XMITHDR_RESP_PKT_ENABLE __BIT(24)
sys/arch/arm/nvidia/tegra_i2creg.h
169
#define I2C_IOPACKET_XMITHDR_HS_MODE __BIT(22)
sys/arch/arm/nvidia/tegra_i2creg.h
170
#define I2C_IOPACKET_XMITHDR_CONTINUE_ON_NACK __BIT(21)
sys/arch/arm/nvidia/tegra_i2creg.h
171
#define I2C_IOPACKET_XMITHDR_SEND_START_BYTE __BIT(20)
sys/arch/arm/nvidia/tegra_i2creg.h
172
#define I2C_IOPACKET_XMITHDR_READ __BIT(19)
sys/arch/arm/nvidia/tegra_i2creg.h
173
#define I2C_IOPACKET_XMITHDR_ADDRESS_MODE __BIT(18)
sys/arch/arm/nvidia/tegra_i2creg.h
174
#define I2C_IOPACKET_XMITHDR_IE __BIT(17)
sys/arch/arm/nvidia/tegra_i2creg.h
175
#define I2C_IOPACKET_XMITHDR_REPEAT_STARTSTOP __BIT(16)
sys/arch/arm/nvidia/tegra_i2creg.h
176
#define I2C_IOPACKET_XMITHDR_CONTINUE_XFER __BIT(15)
sys/arch/arm/nvidia/tegra_i2creg.h
180
#define I2C_IOPACKET_RESPHDR_RFIFO_OVF __BIT(26)
sys/arch/arm/nvidia/tegra_i2creg.h
181
#define I2C_IOPACKET_RESPHDR_TFIFO_OVF __BIT(25)
sys/arch/arm/nvidia/tegra_i2creg.h
182
#define I2C_IOPACKET_RESPHDR_TRANSFER_COMPLETE __BIT(24)
sys/arch/arm/nvidia/tegra_i2creg.h
185
#define I2C_IOPACKET_RESPHDR_NOACK_FOR_ADDR __BIT(3)
sys/arch/arm/nvidia/tegra_i2creg.h
186
#define I2C_IOPACKET_RESPHDR_NOACK_FOR_DATA __BIT(2)
sys/arch/arm/nvidia/tegra_i2creg.h
187
#define I2C_IOPACKET_RESPHDR_ARB_LOST __BIT(1)
sys/arch/arm/nvidia/tegra_i2creg.h
188
#define I2C_IOPACKET_RESPHDR_CONTROLLER_BUSY __BIT(0)
sys/arch/arm/nvidia/tegra_i2creg.h
33
#define I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT __BIT(15)
sys/arch/arm/nvidia/tegra_i2creg.h
35
#define I2C_CNFG_NEW_MASTER_FSM __BIT(11)
sys/arch/arm/nvidia/tegra_i2creg.h
36
#define I2C_CNFG_PACKET_MODE_EN __BIT(10)
sys/arch/arm/nvidia/tegra_i2creg.h
37
#define I2C_CNFG_SEND __BIT(9)
sys/arch/arm/nvidia/tegra_i2creg.h
38
#define I2C_CNFG_NOACK __BIT(8)
sys/arch/arm/nvidia/tegra_i2creg.h
39
#define I2C_CNFG_CMD2 __BIT(7)
sys/arch/arm/nvidia/tegra_i2creg.h
40
#define I2C_CNFG_CMD1 __BIT(6)
sys/arch/arm/nvidia/tegra_i2creg.h
41
#define I2C_CNFG_START __BIT(5)
sys/arch/arm/nvidia/tegra_i2creg.h
42
#define I2C_CNFG_SLV2 __BIT(4)
sys/arch/arm/nvidia/tegra_i2creg.h
44
#define I2C_CNFG_A_MOD __BIT(0)
sys/arch/arm/nvidia/tegra_i2creg.h
52
#define I2C_STATUS_BUSY __BIT(8)
sys/arch/arm/nvidia/tegra_i2creg.h
57
#define I2C_SL_CNFG_FIFO_XFER_EN __BIT(20)
sys/arch/arm/nvidia/tegra_i2creg.h
59
#define I2C_SL_CNFG_ACK_LAST_BYTE_VALID __BIT(7)
sys/arch/arm/nvidia/tegra_i2creg.h
60
#define I2C_SL_CNFG_ACK_LAST_BYTE __BIT(6)
sys/arch/arm/nvidia/tegra_i2creg.h
61
#define I2C_SL_CNFG_ACK_WITHHOLD_EN __BIT(5)
sys/arch/arm/nvidia/tegra_i2creg.h
62
#define I2C_SL_CNFG_PKT_MODE_EN __BIT(4)
sys/arch/arm/nvidia/tegra_i2creg.h
63
#define I2C_SL_CNFG_ENABLE_SL __BIT(3)
sys/arch/arm/nvidia/tegra_i2creg.h
64
#define I2C_SL_CNFG_NEWSL __BIT(2)
sys/arch/arm/nvidia/tegra_i2creg.h
65
#define I2C_SL_CNFG_NACK __BIT(1)
sys/arch/arm/nvidia/tegra_i2creg.h
66
#define I2C_SL_CNFG_RESP __BIT(0)
sys/arch/arm/nvidia/tegra_i2creg.h
81
#define I2C_PACKET_TRANSFER_STATUS_TRANSFER_COMPLETE __BIT(24)
sys/arch/arm/nvidia/tegra_i2creg.h
84
#define I2C_PACKET_TRANSFER_STATUS_NOACK_FOR_ADDR __BIT(3)
sys/arch/arm/nvidia/tegra_i2creg.h
85
#define I2C_PACKET_TRANSFER_STATUS_NOACK_FOR_DATA __BIT(2)
sys/arch/arm/nvidia/tegra_i2creg.h
86
#define I2C_PACKET_TRANSFER_STATUS_ARB_LOST __BIT(1)
sys/arch/arm/nvidia/tegra_i2creg.h
87
#define I2C_PACKET_TRANSFER_STATUS_CONTROLLER_BUSY __BIT(0)
sys/arch/arm/nvidia/tegra_i2creg.h
92
#define I2C_FIFO_CONTROL_SLV_TX_FIFO_FLUSH __BIT(9)
sys/arch/arm/nvidia/tegra_i2creg.h
93
#define I2C_FIFO_CONTROL_SLV_RX_FIFO_FLUSH __BIT(8)
sys/arch/arm/nvidia/tegra_i2creg.h
96
#define I2C_FIFO_CONTROL_TX_FIFO_FLUSH __BIT(1)
sys/arch/arm/nvidia/tegra_i2creg.h
97
#define I2C_FIFO_CONTROL_RX_FIFO_FLUSH __BIT(0)
sys/arch/arm/nvidia/tegra_mcreg.h
35
#define MC_INT_DECERR_MTS __BIT(16)
sys/arch/arm/nvidia/tegra_mcreg.h
36
#define MC_INT_SECERR_SEC __BIT(13)
sys/arch/arm/nvidia/tegra_mcreg.h
37
#define MC_INT_DECERR_VPR __BIT(12)
sys/arch/arm/nvidia/tegra_mcreg.h
38
#define MC_INT_INVALID_APB_ASID_UPDATE __BIT(11)
sys/arch/arm/nvidia/tegra_mcreg.h
39
#define MC_INT_INVALID_SMMU_PAGE __BIT(10)
sys/arch/arm/nvidia/tegra_mcreg.h
40
#define MC_INT_SECURITY_VIOLATION __BIT(8)
sys/arch/arm/nvidia/tegra_mcreg.h
41
#define MC_INT_ARBITRATION_EMEM __BIT(9)
sys/arch/arm/nvidia/tegra_mcreg.h
42
#define MC_INT_DECERR_EMEM __BIT(6)
sys/arch/arm/nvidia/tegra_mcreg.h
52
#define MC_ERR_INVALID_SMMU_PAGE_READABLE __BIT(27)
sys/arch/arm/nvidia/tegra_mcreg.h
53
#define MC_ERR_INVALID_SMMU_PAGE_WRITABLE __BIT(26)
sys/arch/arm/nvidia/tegra_mcreg.h
54
#define MC_ERR_INVALID_SMMU_PAGE_NONSECURE __BIT(25)
sys/arch/arm/nvidia/tegra_mcreg.h
56
#define MC_ERR_SWAP __BIT(18)
sys/arch/arm/nvidia/tegra_mcreg.h
57
#define MC_ERR_SECURITY __BIT(17)
sys/arch/arm/nvidia/tegra_mcreg.h
58
#define MC_ERR_RW __BIT(16)
sys/arch/arm/nvidia/tegra_mcreg.h
67
#define MC_SMMU_ENABLE __BIT(0)
sys/arch/arm/nvidia/tegra_mcreg.h
78
#define MC_EMEM_CFG_0_EMEM_BOM __BIT(31)
sys/arch/arm/nvidia/tegra_mcreg.h
82
#define MC_SMMU_AFIR_ENABLE __BIT(14)
sys/arch/arm/nvidia/tegra_mcreg.h
84
#define MC_SMMU_AFIW_ENABLE __BIT(17)
sys/arch/arm/nvidia/tegra_mpioreg.h
265
#define PINMUX_AUX_RCV_SEL __BIT(9)
sys/arch/arm/nvidia/tegra_mpioreg.h
266
#define PINMUX_AUX_IO_RESET __BIT(8)
sys/arch/arm/nvidia/tegra_mpioreg.h
267
#define PINMUX_AUX_LOCK __BIT(7)
sys/arch/arm/nvidia/tegra_mpioreg.h
268
#define PINMUX_AUX_OD __BIT(6)
sys/arch/arm/nvidia/tegra_mpioreg.h
269
#define PINMUX_AUX_E_INPUT __BIT(5)
sys/arch/arm/nvidia/tegra_mpioreg.h
270
#define PINMUX_AUX_TRISTATE __BIT(4)
sys/arch/arm/nvidia/tegra_pciereg.h
65
#define AFI_INTR_MASK_MSI __BIT(8)
sys/arch/arm/nvidia/tegra_pciereg.h
66
#define AFI_INTR_MASK_INT __BIT(0)
sys/arch/arm/nvidia/tegra_pciereg.h
74
#define AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(n) __BIT(1 + (n))
sys/arch/arm/nvidia/tegra_pciereg.h
76
#define AFI_PEXn_CTRL_REFCLK_OVERRIDE_EN __BIT(4)
sys/arch/arm/nvidia/tegra_pciereg.h
77
#define AFI_PEXn_CTRL_REFCLK_EN __BIT(3)
sys/arch/arm/nvidia/tegra_pciereg.h
78
#define AFI_PEXn_CTRL_CLKREQ_EN __BIT(1)
sys/arch/arm/nvidia/tegra_pciereg.h
79
#define AFI_PEXn_CTRL_RST_L __BIT(0)
sys/arch/arm/nvidia/tegra_pciereg.h
81
#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL __BIT(9)
sys/arch/arm/nvidia/tegra_pciereg.h
82
#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN __BIT(1)
sys/arch/arm/nvidia/tegra_pciereg.h
84
#define AFI_PEXBIAS_CTRL_PWRD __BIT(0)
sys/arch/arm/nvidia/tegra_pciereg.h
87
#define AFI_MSG_PM_PME1 __BIT(20)
sys/arch/arm/nvidia/tegra_pciereg.h
89
#define AFI_MSG_PM_PME0 __BIT(4)
sys/arch/arm/nvidia/tegra_pinmux.c
51
#define PINMUX_E_SCHMT __BIT(12)
sys/arch/arm/nvidia/tegra_pinmux.c
52
#define PINMUX_E_OD __BIT(11)
sys/arch/arm/nvidia/tegra_pinmux.c
53
#define PINMUX_E_IO_HV __BIT(10)
sys/arch/arm/nvidia/tegra_pinmux.c
54
#define PINMUX_E_HSM __BIT(9)
sys/arch/arm/nvidia/tegra_pinmux.c
55
#define PINMUX_LOCK __BIT(7)
sys/arch/arm/nvidia/tegra_pinmux.c
56
#define PINMUX_E_INPUT __BIT(6)
sys/arch/arm/nvidia/tegra_pinmux.c
57
#define PINMUX_PARK __BIT(5)
sys/arch/arm/nvidia/tegra_pinmux.c
58
#define PINMUX_TRISTATE __BIT(4)
sys/arch/arm/nvidia/tegra_pmc.c
148
state = !!(status & __BIT(partid));
sys/arch/arm/nvidia/tegra_pmc.c
186
__BIT(partid));
sys/arch/arm/nvidia/tegra_pmcreg.h
35
#define PMC_CNTRL_0_CPUPWRGOOD_EN __BIT(19)
sys/arch/arm/nvidia/tegra_pmcreg.h
36
#define PMC_CNTRL_0_FUSE_OVERRIDE __BIT(18)
sys/arch/arm/nvidia/tegra_pmcreg.h
37
#define PMC_CNTRL_0_INTR_POLARITY __BIT(17)
sys/arch/arm/nvidia/tegra_pmcreg.h
38
#define PMC_CNTRL_0_CPUPWRREG_OE __BIT(16)
sys/arch/arm/nvidia/tegra_pmcreg.h
39
#define PMC_CNTRL_0_CPUPWRREG_POLARITY __BIT(15)
sys/arch/arm/nvidia/tegra_pmcreg.h
40
#define PMC_CNTRL_0_SIDE_EFFECT_LP0 __BIT(14)
sys/arch/arm/nvidia/tegra_pmcreg.h
41
#define PMC_CNTRL_0_AOINIT __BIT(13)
sys/arch/arm/nvidia/tegra_pmcreg.h
42
#define PMC_CNTRL_0_PWRGATE_DIS __BIT(12)
sys/arch/arm/nvidia/tegra_pmcreg.h
43
#define PMC_CNTRL_0_SYSCLK_OE __BIT(11)
sys/arch/arm/nvidia/tegra_pmcreg.h
44
#define PMC_CNTRL_0_SYSCLK_POLARITY __BIT(10)
sys/arch/arm/nvidia/tegra_pmcreg.h
45
#define PMC_CNTRL_0_PWRREQ_OE __BIT(9)
sys/arch/arm/nvidia/tegra_pmcreg.h
46
#define PMC_CNTRL_0_PWRREQ_POLARITY __BIT(8)
sys/arch/arm/nvidia/tegra_pmcreg.h
47
#define PMC_CNTRL_0_BLINK_EN __BIT(7)
sys/arch/arm/nvidia/tegra_pmcreg.h
48
#define PMC_CNTRL_0_GLITCHDET_DIS __BIT(6)
sys/arch/arm/nvidia/tegra_pmcreg.h
49
#define PMC_CNTRL_0_LATCHWAKE_EN __BIT(5)
sys/arch/arm/nvidia/tegra_pmcreg.h
50
#define PMC_CNTRL_0_MAIN_RST __BIT(4)
sys/arch/arm/nvidia/tegra_pmcreg.h
51
#define PMC_CNTRL_0_KBC_RST __BIT(3)
sys/arch/arm/nvidia/tegra_pmcreg.h
52
#define PMC_CNTRL_0_RTC_RST __BIT(2)
sys/arch/arm/nvidia/tegra_pmcreg.h
53
#define PMC_CNTRL_0_RTC_CLK_DIS __BIT(1)
sys/arch/arm/nvidia/tegra_pmcreg.h
54
#define PMC_CNTRL_0_KBC_CLK_DIS __BIT(0)
sys/arch/arm/nvidia/tegra_pmcreg.h
58
#define PMC_PWRGATE_TOGGLE_0_START __BIT(8)
sys/arch/arm/nvidia/tegra_pmcreg.h
91
#define PMC_IO_DPD_STATUS_HDMI __BIT(28)
sys/arch/arm/nvidia/tegra_pmcreg.h
94
#define PMC_IO_DPD2_STATUS_HV __BIT(6)
sys/arch/arm/nvidia/tegra_pmcreg.h
97
#define PMC_GPU_RG_CNTRL_RAIL_CLAMP __BIT(0)
sys/arch/arm/nvidia/tegra_rtcreg.h
48
#define RTC_BUSY_STATUS __BIT(0)
sys/arch/arm/nvidia/tegra_socthermreg.h
39
#define SOC_THERM_TSENSOR_CONFIG0_STATUS_CLR __BIT(5)
sys/arch/arm/nvidia/tegra_socthermreg.h
40
#define SOC_THERM_TSENSOR_CONFIG0_TCALC_OVERFLOW __BIT(4)
sys/arch/arm/nvidia/tegra_socthermreg.h
41
#define SOC_THERM_TSENSOR_CONFIG0_OVERFLOW __BIT(3)
sys/arch/arm/nvidia/tegra_socthermreg.h
42
#define SOC_THERM_TSENSOR_CONFIG0_CPTR_OVERFLOW __BIT(2)
sys/arch/arm/nvidia/tegra_socthermreg.h
43
#define SOC_THERM_TSENSOR_CONFIG0_RO_SEL __BIT(1)
sys/arch/arm/nvidia/tegra_socthermreg.h
44
#define SOC_THERM_TSENSOR_CONFIG0_STOP __BIT(0)
sys/arch/arm/nvidia/tegra_socthermreg.h
47
#define SOC_THERM_TSENSOR_CONFIG1_TEMP_ENABLE __BIT(31)
sys/arch/arm/nvidia/tegra_socthermreg.h
57
#define SOC_THERM_TSENSOR_STATUS0_CAPTURE_VALID __BIT(31)
sys/arch/arm/nvidia/tegra_socthermreg.h
61
#define SOC_THERM_TSENSOR_STATUS1_TEMP_VALID __BIT(31)
sys/arch/arm/nvidia/tegra_timerreg.h
56
#define TMR_PTV_EN __BIT(31)
sys/arch/arm/nvidia/tegra_timerreg.h
57
#define TMR_PTV_PER __BIT(30)
sys/arch/arm/nvidia/tegra_timerreg.h
60
#define TMR_PCR_INTR_CLR __BIT(30)
sys/arch/arm/nvidia/tegra_usbreg.h
102
#define TEGRA_EHCI_UTMIP_TX_CFG0_FS_PREAMBLE_J __BIT(19)
sys/arch/arm/nvidia/tegra_usbreg.h
105
#define TEGRA_EHCI_UTMIP_MISC_CFG0_SUSPEND_EXIT_ON_EDGE __BIT(22)
sys/arch/arm/nvidia/tegra_usbreg.h
108
#define TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN __BIT(30)
sys/arch/arm/nvidia/tegra_usbreg.h
115
#define TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_PD_CHRG __BIT(0)
sys/arch/arm/nvidia/tegra_usbreg.h
121
#define TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDR_POWERDOWN __BIT(4)
sys/arch/arm/nvidia/tegra_usbreg.h
122
#define TEGRA_EHCI_UTMIP_XCVR_CFG1_PDCHRP_POWERDOWN __BIT(2)
sys/arch/arm/nvidia/tegra_usbreg.h
123
#define TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDISC_POWERDOWN __BIT(0)
sys/arch/arm/nvidia/tegra_usbreg.h
127
#define TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_POWERDOWN __BIT(0)
sys/arch/arm/nvidia/tegra_usbreg.h
36
#define TEGRA_EHCI_ICUSB_CTRL_ENB1 __BIT(3)
sys/arch/arm/nvidia/tegra_usbreg.h
44
#define TEGRA_EHCI_HOSTPC1_DEVLC_STS __BIT(28)
sys/arch/arm/nvidia/tegra_usbreg.h
45
#define TEGRA_EHCI_HOSTPC1_DEVLC_PTW __BIT(27)
sys/arch/arm/nvidia/tegra_usbreg.h
50
#define TEGRA_EHCI_HOSTPC1_DEVLC_ALPD __BIT(24)
sys/arch/arm/nvidia/tegra_usbreg.h
51
#define TEGRA_EHCI_HOSTPC1_DEVLC_PFSC __BIT(23)
sys/arch/arm/nvidia/tegra_usbreg.h
52
#define TEGRA_EHCI_HOSTPC1_DEVLC_PHCD __BIT(22)
sys/arch/arm/nvidia/tegra_usbreg.h
56
#define TEGRA_EHCI_HOSTPC1_DEVLC_D_ASUS __BIT(17)
sys/arch/arm/nvidia/tegra_usbreg.h
57
#define TEGRA_EHCI_HOSTPC1_DEVLC_D_STL __BIT(16)
sys/arch/arm/nvidia/tegra_usbreg.h
67
#define TEGRA_EHCI_SUSP_CTRL_UHSIC_RESET __BIT(14)
sys/arch/arm/nvidia/tegra_usbreg.h
68
#define TEGRA_EHCI_SUSP_CTRL_ULPI_PHY_ENB __BIT(13)
sys/arch/arm/nvidia/tegra_usbreg.h
69
#define TEGRA_EHCI_SUSP_CTRL_UTMIP_PHY_ENB __BIT(12)
sys/arch/arm/nvidia/tegra_usbreg.h
70
#define TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET __BIT(11)
sys/arch/arm/nvidia/tegra_usbreg.h
71
#define TEGRA_EHCI_SUSP_CTRL_PHY_CLK_VALID __BIT(7)
sys/arch/arm/nvidia/tegra_usbreg.h
74
#define TEGRA_EHCI_PHY_VBUS_SENSORS_A_VBUS_VLD_STS __BIT(26)
sys/arch/arm/nvidia/tegra_usbreg.h
75
#define TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_VALUE __BIT(12)
sys/arch/arm/nvidia/tegra_usbreg.h
76
#define TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_EN __BIT(11)
sys/arch/arm/nvidia/tegra_usbreg.h
79
#define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_PU __BIT(6)
sys/arch/arm/nvidia/tegra_usbreg.h
80
#define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_DEB_SEL_B __BIT(5)
sys/arch/arm/nvidia/tegra_usbreg.h
81
#define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_SW_VALUE __BIT(4)
sys/arch/arm/nvidia/tegra_usbreg.h
82
#define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_SW_EN __BIT(3)
sys/arch/arm/nvidia/tegra_usbreg.h
83
#define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_STS __BIT(2)
sys/arch/arm/nvidia/tegra_usbreg.h
84
#define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_CHG_DET __BIT(1)
sys/arch/arm/nvidia/tegra_usbreg.h
85
#define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_INT_EN __BIT(0)
sys/arch/arm/nvidia/tegra_usbreg.h
90
#define TEGRA_EHCI_UTMIP_XCVR_CFG0_LSBIAS_SEL __BIT(21)
sys/arch/arm/nvidia/tegra_usbreg.h
92
#define TEGRA_EHCI_UTMIP_XCVR_CFG0_PDZI_POWERDOWN __BIT(18)
sys/arch/arm/nvidia/tegra_usbreg.h
93
#define TEGRA_EHCI_UTMIP_XCVR_CFG0_PD2_POWERDOWN __BIT(16)
sys/arch/arm/nvidia/tegra_usbreg.h
94
#define TEGRA_EHCI_UTMIP_XCVR_CFG0_PD_POWERDOWN __BIT(14)
sys/arch/arm/nvidia/tegra_usbreg.h
97
#define TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL_MSB __BIT(24)
sys/arch/arm/nvidia/tegra_usbreg.h
98
#define TEGRA_EHCI_UTMIP_BIAS_CFG0_BIASPD __BIT(10)
sys/arch/arm/nvidia/tegra_xusb.c
670
tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0);
sys/arch/arm/nvidia/tegra_xusbreg.h
34
#define T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN __BIT(31)
sys/arch/arm/nvidia/tegra_xusbreg.h
35
#define T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_XHCI __BIT(30)
sys/arch/arm/nvidia/tegra_xusbreg.h
36
#define T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI __BIT(29)
sys/arch/arm/nvidia/tegra_xusbreg.h
37
#define T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_PME __BIT(28)
sys/arch/arm/nvidia/tegra_xusbreg.h
38
#define T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON __BIT(27)
sys/arch/arm/nvidia/tegra_xusbreg.h
51
#define T_XUSB_CFG_ARU_SMI_INTR_EN __BIT(3)
sys/arch/arm/nvidia/tegra_xusbreg.h
52
#define T_XUSB_CFG_ARU_SMI_INTR_FW_HANG __BIT(1)
sys/arch/arm/nvidia/tegra_xusbreg.h
60
#define XUSB_CSB_FALCON_CPUCTL_STOPPED __BIT(5)
sys/arch/arm/nvidia/tegra_xusbreg.h
61
#define XUSB_CSB_FALCON_CPUCTL_HALTED __BIT(4)
sys/arch/arm/nvidia/tegra_xusbreg.h
62
#define XUSB_CSB_FALCON_CPUCTL_STARTCPU __BIT(1)
sys/arch/arm/nvidia/tegra_xusbreg.h
72
#define XUSB_CSB_MEMPOOL_APMAP_BOOTPATH __BIT(31)
sys/arch/arm/nxp/imx6_ccmreg.h
109
#define CCM_CBCMR_PERIPH2_CLK2_SEL __BIT(20)
sys/arch/arm/nxp/imx6_ccmreg.h
114
#define CCM_CBCMR_VDOAXI_CLK_SEL __BIT(11)
sys/arch/arm/nxp/imx6_ccmreg.h
115
#define CCM_CBCMR_PCIE_AXI_CLK_SEL __BIT(10)
sys/arch/arm/nxp/imx6_ccmreg.h
118
#define CCM_CBCMR_GPU3D_AXI_CLK_SEL __BIT(1)
sys/arch/arm/nxp/imx6_ccmreg.h
119
#define CCM_CBCMR_GPU2D_AXI_CLK_SEL __BIT(0)
sys/arch/arm/nxp/imx6_ccmreg.h
127
#define CCM_CSCMR1_USDHC4_CLK_SEL __BIT(19)
sys/arch/arm/nxp/imx6_ccmreg.h
128
#define CCM_CSCMR1_USDHC3_CLK_SEL __BIT(18)
sys/arch/arm/nxp/imx6_ccmreg.h
129
#define CCM_CSCMR1_USDHC2_CLK_SEL __BIT(17)
sys/arch/arm/nxp/imx6_ccmreg.h
130
#define CCM_CSCMR1_USDHC1_CLK_SEL __BIT(16)
sys/arch/arm/nxp/imx6_ccmreg.h
135
#define CCM_CSCMR1_PERCLK_SEL __BIT(6) /* 6sx */
sys/arch/arm/nxp/imx6_ccmreg.h
142
#define CCM_CSCMR2_LDB_DI1_IPU_DIV __BIT(11)
sys/arch/arm/nxp/imx6_ccmreg.h
143
#define CCM_CSCMR2_LDB_DI0_IPU_DIV __BIT(10)
sys/arch/arm/nxp/imx6_ccmreg.h
154
#define CCM_CSCDR1_UART_CLK_SEL __BIT(6) /* 6sx */
sys/arch/arm/nxp/imx6_ccmreg.h
176
#define CCM_CDCDR_HSI_TX_CLK_SEL __BIT(28)
sys/arch/arm/nxp/imx6_ccmreg.h
198
#define CCM_CSCDR2_ECSPI_SEL __BIT(18) /* 6sx */
sys/arch/arm/nxp/imx6_ccmreg.h
207
#define CCM_CDHIPR_ARM_PODF_BUSY __BIT(16)
sys/arch/arm/nxp/imx6_ccmreg.h
208
#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY __BIT(5)
sys/arch/arm/nxp/imx6_ccmreg.h
209
#define CCM_CDHIPR_MMDC_CH0_PODF_BUSY __BIT(4)
sys/arch/arm/nxp/imx6_ccmreg.h
210
#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY __BIT(3)
sys/arch/arm/nxp/imx6_ccmreg.h
211
#define CCM_CDHIPR_MMDC_CH1_PODF_BUSY __BIT(2)
sys/arch/arm/nxp/imx6_ccmreg.h
212
#define CCM_CDHIPR_AHB_PODF_BUSY __BIT(1)
sys/arch/arm/nxp/imx6_ccmreg.h
213
#define CCM_CDHIPR_AXI_PODF_BUSY __BIT(0)
sys/arch/arm/nxp/imx6_ccmreg.h
222
#define CCM_CCOSR_CLKO2_EN __BIT(24)
sys/arch/arm/nxp/imx6_ccmreg.h
225
#define CCM_CCOSR_CLK_OUT_SEL __BIT(8)
sys/arch/arm/nxp/imx6_ccmreg.h
226
#define CCM_CCOSR_CLKO1_EN __BIT(7)
sys/arch/arm/nxp/imx6_ccmreg.h
350
#define CCM_ANALOG_PLL_ARM_LOCK __BIT(31)
sys/arch/arm/nxp/imx6_ccmreg.h
351
#define CCM_ANALOG_PLL_ARM_PLL_SEL __BIT(19)
sys/arch/arm/nxp/imx6_ccmreg.h
352
#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL __BIT(18)
sys/arch/arm/nxp/imx6_ccmreg.h
353
#define CCM_ANALOG_PLL_ARM_LVDS_SEL __BIT(17)
sys/arch/arm/nxp/imx6_ccmreg.h
354
#define CCM_ANALOG_PLL_ARM_BYPASS __BIT(16)
sys/arch/arm/nxp/imx6_ccmreg.h
356
#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_6SX __BIT(14) /* 6sx */
sys/arch/arm/nxp/imx6_ccmreg.h
357
#define CCM_ANALOG_PLL_ARM_ENABLE __BIT(13)
sys/arch/arm/nxp/imx6_ccmreg.h
358
#define CCM_ANALOG_PLL_ARM_POWERDOWN __BIT(12)
sys/arch/arm/nxp/imx6_ccmreg.h
361
#define CCM_ANALOG_PLL_LOCK __BIT(31)
sys/arch/arm/nxp/imx6_ccmreg.h
362
#define CCM_ANALOG_PLL_BYPASS __BIT(16)
sys/arch/arm/nxp/imx6_ccmreg.h
364
#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_6SX __BIT(14)
sys/arch/arm/nxp/imx6_ccmreg.h
365
#define CCM_ANALOG_PLL_ENABLE __BIT(13)
sys/arch/arm/nxp/imx6_ccmreg.h
366
#define CCM_ANALOG_PLL_POWER __BIT(12)
sys/arch/arm/nxp/imx6_ccmreg.h
367
#define CCM_ANALOG_PLL_EN_USB_CLK __BIT(6)
sys/arch/arm/nxp/imx6_ccmreg.h
374
#define CCM_ANALOG_PLL_USB1_LOCK __BIT(31)
sys/arch/arm/nxp/imx6_ccmreg.h
375
#define CCM_ANALOG_PLL_USB1_RESERVED __BIT(20)
sys/arch/arm/nxp/imx6_ccmreg.h
376
#define CCM_ANALOG_PLL_USB1_BYPASS __BIT(16)
sys/arch/arm/nxp/imx6_ccmreg.h
378
#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_6SX __BIT(14)
sys/arch/arm/nxp/imx6_ccmreg.h
379
#define CCM_ANALOG_PLL_USB1_ENABLE __BIT(13)
sys/arch/arm/nxp/imx6_ccmreg.h
380
#define CCM_ANALOG_PLL_USB1_POWER __BIT(12)
sys/arch/arm/nxp/imx6_ccmreg.h
381
#define CCM_ANALOG_PLL_USB1_EN_USB_CLK __BIT(6)
sys/arch/arm/nxp/imx6_ccmreg.h
388
#define CCM_ANALOG_PLL_USB2_LOCK __BIT(31)
sys/arch/arm/nxp/imx6_ccmreg.h
389
#define CCM_ANALOG_PLL_USB2_RESERVED __BIT(20)
sys/arch/arm/nxp/imx6_ccmreg.h
390
#define CCM_ANALOG_PLL_USB2_BYPASS __BIT(16)
sys/arch/arm/nxp/imx6_ccmreg.h
392
#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_6SX __BIT(14)
sys/arch/arm/nxp/imx6_ccmreg.h
393
#define CCM_ANALOG_PLL_USB2_ENABLE __BIT(13)
sys/arch/arm/nxp/imx6_ccmreg.h
394
#define CCM_ANALOG_PLL_USB2_POWER __BIT(12)
sys/arch/arm/nxp/imx6_ccmreg.h
395
#define CCM_ANALOG_PLL_USB2_EN_USB_CLK __BIT(6)
sys/arch/arm/nxp/imx6_ccmreg.h
402
#define CCM_ANALOG_PLL_SYS_BYPASS __BIT(16)
sys/arch/arm/nxp/imx6_ccmreg.h
404
#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_6SX __BIT(14)
sys/arch/arm/nxp/imx6_ccmreg.h
405
#define CCM_ANALOG_PLL_SYS_ENABLE __BIT(13)
sys/arch/arm/nxp/imx6_ccmreg.h
406
#define CCM_ANALOG_PLL_SYS_POWERDOWN __BIT(12)
sys/arch/arm/nxp/imx6_ccmreg.h
407
#define CCM_ANALOG_PLL_SYS_DIV_SELECT __BIT(0)
sys/arch/arm/nxp/imx6_ccmreg.h
416
#define CCM_ANALOG_PLL_AUDIO_BYPASS __BIT(16)
sys/arch/arm/nxp/imx6_ccmreg.h
418
#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_6SX __BIT(14)
sys/arch/arm/nxp/imx6_ccmreg.h
419
#define CCM_ANALOG_PLL_AUDIO_ENABLE __BIT(13)
sys/arch/arm/nxp/imx6_ccmreg.h
420
#define CCM_ANALOG_PLL_AUDIO_POWERDOWN __BIT(12)
sys/arch/arm/nxp/imx6_ccmreg.h
426
#define CCM_ANALOG_PLL_VIDEO_BYPASS __BIT(16)
sys/arch/arm/nxp/imx6_ccmreg.h
428
#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_6SX __BIT(14)
sys/arch/arm/nxp/imx6_ccmreg.h
429
#define CCM_ANALOG_PLL_VIDEO_ENABLE __BIT(13)
sys/arch/arm/nxp/imx6_ccmreg.h
430
#define CCM_ANALOG_PLL_VIDEO_POWERDOWN __BIT(12)
sys/arch/arm/nxp/imx6_ccmreg.h
445
#define CCM_ANALOG_PLL_ENET_LOCK __BIT(31)
sys/arch/arm/nxp/imx6_ccmreg.h
446
#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN __BIT(21) /* iMX6UL */
sys/arch/arm/nxp/imx6_ccmreg.h
447
#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN __BIT(20) /* iMX6UL */
sys/arch/arm/nxp/imx6_ccmreg.h
448
#define CCM_ANALOG_PLL_ENET_ENABLE_100M __BIT(20) /* SATA */
sys/arch/arm/nxp/imx6_ccmreg.h
449
#define CCM_ANALOG_PLL_ENET_ENABLE_125M __BIT(19) /* PCIe */
sys/arch/arm/nxp/imx6_ccmreg.h
450
#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN __BIT(18)
sys/arch/arm/nxp/imx6_ccmreg.h
451
#define CCM_ANALOG_PLL_ENET_BYPASS __BIT(16)
sys/arch/arm/nxp/imx6_ccmreg.h
453
#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_6SX __BIT(14)
sys/arch/arm/nxp/imx6_ccmreg.h
454
#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN __BIT(13) /* iMX6UL */
sys/arch/arm/nxp/imx6_ccmreg.h
455
#define CCM_ANALOG_PLL_ENET_ENABLE __BIT(13) /* Ether */
sys/arch/arm/nxp/imx6_ccmreg.h
456
#define CCM_ANALOG_PLL_ENET_POWERDOWN __BIT(12)
sys/arch/arm/nxp/imx6_ccmreg.h
463
#define CCM_ANALOG_PFD_480_PFD3_CLKGATE __BIT(31)
sys/arch/arm/nxp/imx6_ccmreg.h
464
#define CCM_ANALOG_PFD_480_PFD3_STABLE __BIT(30)
sys/arch/arm/nxp/imx6_ccmreg.h
466
#define CCM_ANALOG_PFD_480_PFD2_CLKGATE __BIT(23)
sys/arch/arm/nxp/imx6_ccmreg.h
467
#define CCM_ANALOG_PFD_480_PFD2_STABLE __BIT(22)
sys/arch/arm/nxp/imx6_ccmreg.h
469
#define CCM_ANALOG_PFD_480_PFD1_CLKGATE __BIT(15)
sys/arch/arm/nxp/imx6_ccmreg.h
470
#define CCM_ANALOG_PFD_480_PFD1_STABLE __BIT(14)
sys/arch/arm/nxp/imx6_ccmreg.h
472
#define CCM_ANALOG_PFD_480_PFD0_CLKGATE __BIT(7)
sys/arch/arm/nxp/imx6_ccmreg.h
473
#define CCM_ANALOG_PFD_480_PFD0_STABLE __BIT(6)
sys/arch/arm/nxp/imx6_ccmreg.h
479
#define CCM_ANALOG_PFD_528_PFD2_CLKGATE __BIT(23)
sys/arch/arm/nxp/imx6_ccmreg.h
480
#define CCM_ANALOG_PFD_528_PFD2_STABLE __BIT(22)
sys/arch/arm/nxp/imx6_ccmreg.h
482
#define CCM_ANALOG_PFD_528_PFD1_CLKGATE __BIT(15)
sys/arch/arm/nxp/imx6_ccmreg.h
483
#define CCM_ANALOG_PFD_528_PFD1_STABLE __BIT(14)
sys/arch/arm/nxp/imx6_ccmreg.h
485
#define CCM_ANALOG_PFD_528_PFD0_CLKGATE __BIT(7)
sys/arch/arm/nxp/imx6_ccmreg.h
486
#define CCM_ANALOG_PFD_528_PFD0_STABLE __BIT(6)
sys/arch/arm/nxp/imx6_ccmreg.h
500
#define CCM_ANALOG_MISC1_LVDS_CLK1_OBEN __BIT(10)
sys/arch/arm/nxp/imx6_ccmreg.h
501
#define CCM_ANALOG_MISC1_LVDS_CLK2_OBEN __BIT(11)
sys/arch/arm/nxp/imx6_ccmreg.h
502
#define CCM_ANALOG_MISC1_LVDS_CLK1_IBEN __BIT(12)
sys/arch/arm/nxp/imx6_ccmreg.h
503
#define CCM_ANALOG_MISC1_LVDS_CLK2_IBEN __BIT(13)
sys/arch/arm/nxp/imx6_ccmreg.h
512
#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB __BIT(23)
sys/arch/arm/nxp/imx6_ccmreg.h
513
#define CCM_ANALOG_MISC2_REG2_OK __BIT(22)
sys/arch/arm/nxp/imx6_ccmreg.h
514
#define CCM_ANALOG_MISC2_REG2_ENABLE_BO __BIT(21)
sys/arch/arm/nxp/imx6_ccmreg.h
515
#define CCM_ANALOG_MISC2_REG2_BO_STATUS __BIT(19)
sys/arch/arm/nxp/imx6_ccmreg.h
517
#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB __BIT(15)
sys/arch/arm/nxp/imx6_ccmreg.h
518
#define CCM_ANALOG_MISC2_REG1_ENABLE_BO __BIT(13)
sys/arch/arm/nxp/imx6_ccmreg.h
519
#define CCM_ANALOG_MISC2_REG1_BO_STATUS __BIT(11)
sys/arch/arm/nxp/imx6_ccmreg.h
521
#define CCM_ANALOG_MISC2_PLL3_DISABLE __BIT(7)
sys/arch/arm/nxp/imx6_ccmreg.h
522
#define CCM_ANALOG_MISC2_REG0_ENABLE_BO __BIT(5)
sys/arch/arm/nxp/imx6_ccmreg.h
523
#define CCM_ANALOG_MISC2_REG0_BO_STATUS __BIT(3)
sys/arch/arm/nxp/imx6_ccmreg.h
527
#define CCM_TEMPMON_TEMPSENSE0_ALARM_VALUE __BIT(31, 30)
sys/arch/arm/nxp/imx6_ccmreg.h
529
#define CCM_TEMPMON_TEMPSENSE0_FINISHED __BIT(2)
sys/arch/arm/nxp/imx6_ccmreg.h
530
#define CCM_TEMPMON_TEMPSENSE0_MEASURE_TEMP __BIT(1)
sys/arch/arm/nxp/imx6_ccmreg.h
531
#define CCM_TEMPMON_TEMPSENSE0_POWER_DOWN __BIT(0)
sys/arch/arm/nxp/imx6_ccmreg.h
537
#define USB_ANALOG_USB_CHRG_DETECT_EN_B __BIT(20)
sys/arch/arm/nxp/imx6_ccmreg.h
538
#define USB_ANALOG_USB_CHRG_DETECT_CHK_CHRG_B __BIT(19)
sys/arch/arm/nxp/imx6_ccmreg.h
539
#define USB_ANALOG_USB_CHRG_DETECT_CHK_CHK_CONTACT __BIT(18)
sys/arch/arm/nxp/imx6_ccmreg.h
67
#define CCM_CCR_RBC_EN __BIT(27)
sys/arch/arm/nxp/imx6_ccmreg.h
70
#define CCM_CCR_COSC_EN __BIT(12)
sys/arch/arm/nxp/imx6_ccmreg.h
76
#define CCM_CCSR_PLL3_PFD1_DIS_MASK __BIT(15)
sys/arch/arm/nxp/imx6_ccmreg.h
77
#define CCM_CCSR_PLL3_PFD0_DIS_MASK __BIT(14)
sys/arch/arm/nxp/imx6_ccmreg.h
78
#define CCM_CCSR_PLL3_PFD3_DIS_MASK __BIT(13)
sys/arch/arm/nxp/imx6_ccmreg.h
79
#define CCM_CCSR_PLL3_PFD2_DIS_MASK __BIT(12)
sys/arch/arm/nxp/imx6_ccmreg.h
80
#define CCM_CCSR_PLL2_PFD1_594M_DIS_MASK __BIT(11)
sys/arch/arm/nxp/imx6_ccmreg.h
81
#define CCM_CCSR_PLL2_PFD0_DIS_MASK __BIT(10)
sys/arch/arm/nxp/imx6_ccmreg.h
82
#define CCM_CCSR_PLL2_PFD2_DIS_MASK __BIT(9)
sys/arch/arm/nxp/imx6_ccmreg.h
83
#define CCM_CCSR_STEP_SEL __BIT(8)
sys/arch/arm/nxp/imx6_ccmreg.h
84
#define CCM_CCSR_PLL1_SW_CLK_SEL __BIT(2)
sys/arch/arm/nxp/imx6_ccmreg.h
85
#define CCM_CCSR_PLL3_SW_CLK_SEL __BIT(0)
sys/arch/arm/nxp/imx6_ccmreg.h
92
#define CCM_CBCDR_PERIPH2_CLK_SEL __BIT(26)
sys/arch/arm/nxp/imx6_ccmreg.h
94
#define CCM_CBCDR_PERIPH_CLK_SEL __BIT(25)
sys/arch/arm/nxp/imx6_ccmreg.h
99
#define CCM_CBCDR_AXI_ALT_SEL __BIT(7)
sys/arch/arm/nxp/imx6_iomux.c
51
#define CONFIG_NO_PAD_CTL __BIT(31)
sys/arch/arm/nxp/imx6_iomux.c
52
#define CONFIG_SION __BIT(30)
sys/arch/arm/nxp/imx6_iomuxreg.h
100
#define IOMUX_GPR13_SATA_SPEED __BIT(15)
sys/arch/arm/nxp/imx6_iomuxreg.h
101
#define IOMUX_GPR13_SATA_PHY_5 __BIT(14)
sys/arch/arm/nxp/imx6_iomuxreg.h
105
#define IOMUX_GPR13_SATA_PHY_1 __BIT(1)
sys/arch/arm/nxp/imx6_iomuxreg.h
106
#define IOMUX_GPR13_SATA_PHY_0 __BIT(0)
sys/arch/arm/nxp/imx6_iomuxreg.h
1783
#define IMX6UL_IOMUX_GPR1_ARMA7_CLK_AHB_EN __BIT(26)
sys/arch/arm/nxp/imx6_iomuxreg.h
1784
#define IMX6UL_IOMUX_GPR1_ARMA7_CLK_ATB_EN __BIT(25)
sys/arch/arm/nxp/imx6_iomuxreg.h
1785
#define IMX6UL_IOMUX_GPR1_ARMA7_CLK_APB_DBG_EN __BIT(24)
sys/arch/arm/nxp/imx6_iomuxreg.h
1786
#define IMX6UL_IOMUX_GPR1_TZASC1_BOOT_LOCK __BIT(23)
sys/arch/arm/nxp/imx6_iomuxreg.h
1787
#define IMX6UL_IOMUX_GPR1_EXC_MON __BIT(22)
sys/arch/arm/nxp/imx6_iomuxreg.h
1788
#define IMX6UL_IOMUX_GPR1_SAI3_MCLK_DIR __BIT(21)
sys/arch/arm/nxp/imx6_iomuxreg.h
1789
#define IMX6UL_IOMUX_GPR1_SAI2_MCLK_DIR __BIT(20)
sys/arch/arm/nxp/imx6_iomuxreg.h
1790
#define IMX6UL_IOMUX_GPR1_SAI1_MCLK_DIR __BIT(19)
sys/arch/arm/nxp/imx6_iomuxreg.h
1791
#define IMX6UL_IOMUX_GPR1_ENET2_TX_CLK_DIR __BIT(18)
sys/arch/arm/nxp/imx6_iomuxreg.h
1792
#define IMX6UL_IOMUX_GPR1_ENET1_TX_CLK_DIR __BIT(17)
sys/arch/arm/nxp/imx6_iomuxreg.h
1793
#define IMX6UL_IOMUX_GPR1_ADD_DS __BIT(16)
sys/arch/arm/nxp/imx6_iomuxreg.h
1794
#define IMX6UL_IOMUX_GPR1_USB_EXP_MODE __BIT(15)
sys/arch/arm/nxp/imx6_iomuxreg.h
1795
#define IMX6UL_IOMUX_GPR1_ENET2_CLK_SEL __BIT(14)
sys/arch/arm/nxp/imx6_iomuxreg.h
1796
#define IMX6UL_IOMUX_GPR1_ENET1_CLK_SEL __BIT(13)
sys/arch/arm/nxp/imx6_iomuxreg.h
1797
#define IMX6UL_IOMUX_GPR1_GINT __BIT(12)
sys/arch/arm/nxp/imx6_iomuxreg.h
2227
#define IOMUX_CONFIG_SION __BIT(4)
sys/arch/arm/nxp/imx6_iomuxreg.h
2242
#define PAD_CTL_HYS __BIT(16)
sys/arch/arm/nxp/imx6_iomuxreg.h
2248
#define PAD_CTL_PUE __BIT(13)
sys/arch/arm/nxp/imx6_iomuxreg.h
2249
#define PAD_CTL_PKE __BIT(12)
sys/arch/arm/nxp/imx6_iomuxreg.h
2252
#define PAD_CTL_ODE __BIT(11)
sys/arch/arm/nxp/imx6_iomuxreg.h
2275
#define PAD_CTL_SRE __BIT(0)
sys/arch/arm/nxp/imx6_iomuxreg.h
34
#define IOMUX_GPR1_CFG_L1_CLK_REMOVAL_EN __BIT(31)
sys/arch/arm/nxp/imx6_iomuxreg.h
35
#define IOMUX_GPR1_APP_CLK_REQ_N __BIT(30)
sys/arch/arm/nxp/imx6_iomuxreg.h
36
#define IOMUX_GPR1_PCIE_SW_RST __BIT(29)
sys/arch/arm/nxp/imx6_iomuxreg.h
37
#define IOMUX_GPR1_APP_REQ_EXIT_L1 __BIT(28)
sys/arch/arm/nxp/imx6_iomuxreg.h
38
#define IOMUX_GPR1_APP_READY_ENTR_L23 __BIT(27)
sys/arch/arm/nxp/imx6_iomuxreg.h
39
#define IOMUX_GPR1_APP_REQ_ENTR_L1 __BIT(26)
sys/arch/arm/nxp/imx6_iomuxreg.h
40
#define IOMUX_GPR1_MIPI_COLOR_SW __BIT(25)
sys/arch/arm/nxp/imx6_iomuxreg.h
41
#define IOMUX_GPR1_MIPI_DPI_OFF __BIT(24)
sys/arch/arm/nxp/imx6_iomuxreg.h
42
#define IOMUX_GPR1_EXC_MON __BIT(22)
sys/arch/arm/nxp/imx6_iomuxreg.h
43
#define IOMUX_GPR1_ENET_CLK_SEL __BIT(21)
sys/arch/arm/nxp/imx6_iomuxreg.h
44
#define IOMUX_GPR1_MIPI_IPU2_MUX __BIT(20)
sys/arch/arm/nxp/imx6_iomuxreg.h
45
#define IOMUX_GPR1_MIPI_IPU1_MUX __BIT(19)
sys/arch/arm/nxp/imx6_iomuxreg.h
46
#define IOMUX_GPR1_TEST_POWERDOWN __BIT(18)
sys/arch/arm/nxp/imx6_iomuxreg.h
47
#define IOMUX_GPR1_IPU_VPU_MUX __BIT(17)
sys/arch/arm/nxp/imx6_iomuxreg.h
48
#define IOMUX_GPR1_REF_SSP_EN __BIT(16)
sys/arch/arm/nxp/imx6_iomuxreg.h
49
#define IOMUX_GPR1_USB_EXP_MODE __BIT(15)
sys/arch/arm/nxp/imx6_iomuxreg.h
50
#define IOMUX_GPR1_SYS_INT __BIT(14)
sys/arch/arm/nxp/imx6_iomuxreg.h
51
#define IOMUX_GPR1_USB_OTG_ID_SEL __BIT(13)
sys/arch/arm/nxp/imx6_iomuxreg.h
52
#define IOMUX_GPR1_GINT __BIT(12)
sys/arch/arm/nxp/imx6_iomuxreg.h
54
#define IOMUX_GPR1_ACT_CS3 __BIT(9)
sys/arch/arm/nxp/imx6_iomuxreg.h
56
#define IOMUX_GPR1_ACT_CS2 __BIT(6)
sys/arch/arm/nxp/imx6_iomuxreg.h
58
#define IOMUX_GPR1_ACT_CS1 __BIT(3)
sys/arch/arm/nxp/imx6_iomuxreg.h
60
#define IOMUX_GPR1_ACT_CS0 __BIT(0)
sys/arch/arm/nxp/imx6_iomuxreg.h
77
#define IOMUX_GPR12_ARMP_IPG_CLK_EN __BIT(27)
sys/arch/arm/nxp/imx6_iomuxreg.h
78
#define IOMUX_GPR12_ARMP_AHB_CLK_EN __BIT(26)
sys/arch/arm/nxp/imx6_iomuxreg.h
79
#define IOMUX_GPR12_ARMP_ATB_CLK_EN __BIT(25)
sys/arch/arm/nxp/imx6_iomuxreg.h
80
#define IOMUX_GPR12_ARMP_APB_CLK_EN __BIT(24)
sys/arch/arm/nxp/imx6_iomuxreg.h
83
#define IOMUX_GPR12_APPS_PM_XMT_TURNOFF __BIT(16)
sys/arch/arm/nxp/imx6_iomuxreg.h
87
#define IOMUX_GPR12_APP_INIT_RST __BIT(11)
sys/arch/arm/nxp/imx6_iomuxreg.h
88
#define IOMUX_GPR12_APP_LTSSM_ENABLE __BIT(10)
sys/arch/arm/nxp/imx6_iomuxreg.h
89
#define IOMUX_GPR12_APPS_PM_XMT_PME __BIT(9)
sys/arch/arm/nxp/imx6_iomuxreg.h
93
#define IOMUX_GPR13_SDMA_STOP_REQ __BIT(30)
sys/arch/arm/nxp/imx6_iomuxreg.h
94
#define IOMUX_GPR13_CAN2_STOP_REQ __BIT(29)
sys/arch/arm/nxp/imx6_iomuxreg.h
95
#define IOMUX_GPR13_CAN1_STOP_REQ __BIT(28)
sys/arch/arm/nxp/imx6_iomuxreg.h
96
#define IOMUX_GPR13_ENET_STOP_REQ __BIT(27)
sys/arch/arm/nxp/imx6_srcreg.h
101
#define SRC_GPR10_CORE3_ERROR_STATUS __BIT(27)
sys/arch/arm/nxp/imx6_srcreg.h
102
#define SRC_GPR10_CORE2_ERROR_STATUS __BIT(26)
sys/arch/arm/nxp/imx6_srcreg.h
103
#define SRC_GPR10_CORE1_ERROR_STATUS __BIT(25)
sys/arch/arm/nxp/imx6_srcreg.h
36
#define SRC_SCR_DBG_RST_MASK_PG __BIT(25)
sys/arch/arm/nxp/imx6_srcreg.h
38
#define SRC_SCR_COREN_ENABLE(n) __BIT(22 + ((n) - 1)) /* no core0 bit */
sys/arch/arm/nxp/imx6_srcreg.h
39
#define SRC_SCR_CORE3_ENABLE __BIT(24)
sys/arch/arm/nxp/imx6_srcreg.h
40
#define SRC_SCR_CORE2_ENABLE __BIT(23)
sys/arch/arm/nxp/imx6_srcreg.h
41
#define SRC_SCR_CORE1_ENABLE __BIT(22)
sys/arch/arm/nxp/imx6_srcreg.h
42
#define SRC_SCR_CORES_DBG_RST __BIT(21)
sys/arch/arm/nxp/imx6_srcreg.h
43
#define SRC_SCR_COREN_DBG_RST(n) __BIT(17 + (n))
sys/arch/arm/nxp/imx6_srcreg.h
44
#define SRC_SCR_CORE3_DBG_RST __BIT(20)
sys/arch/arm/nxp/imx6_srcreg.h
45
#define SRC_SCR_CORE2_DBG_RST __BIT(19)
sys/arch/arm/nxp/imx6_srcreg.h
46
#define SRC_SCR_CORE1_DBG_RST __BIT(18)
sys/arch/arm/nxp/imx6_srcreg.h
47
#define SRC_SCR_CORE0_DBG_RST __BIT(17)
sys/arch/arm/nxp/imx6_srcreg.h
48
#define SRC_SCR_COREN_RST(n) __BIT(13 + (n))
sys/arch/arm/nxp/imx6_srcreg.h
49
#define SRC_SCR_CORE3_RST __BIT(16)
sys/arch/arm/nxp/imx6_srcreg.h
50
#define SRC_SCR_CORE2_RST __BIT(15)
sys/arch/arm/nxp/imx6_srcreg.h
51
#define SRC_SCR_CORE1_RST __BIT(14)
sys/arch/arm/nxp/imx6_srcreg.h
52
#define SRC_SCR_CORE0_RST __BIT(13)
sys/arch/arm/nxp/imx6_srcreg.h
53
#define SRC_SCR_SW_IPU2_RST __BIT(12)
sys/arch/arm/nxp/imx6_srcreg.h
54
#define SRC_SCR_EIM_RST __BIT(11)
sys/arch/arm/nxp/imx6_srcreg.h
57
#define SRC_SCR_SW_OPEN_VG_RS __BIT(4)
sys/arch/arm/nxp/imx6_srcreg.h
58
#define SRC_SCR_SW_IPU1_RST __BIT(3)
sys/arch/arm/nxp/imx6_srcreg.h
59
#define SRC_SCR_SW_VPU_RST __BIT(2)
sys/arch/arm/nxp/imx6_srcreg.h
60
#define SRC_SCR_SW_GPU_RST __BIT(1)
sys/arch/arm/nxp/imx6_srcreg.h
61
#define SRC_SCR_WARM_RESET_ENABLE __BIT(0)
sys/arch/arm/nxp/imx6_srcreg.h
64
#define SRC_SRSR_WARM_BOOT __BIT(16)
sys/arch/arm/nxp/imx6_srcreg.h
66
#define SRC_SRSR_JTAG_SW_RST __BIT(6)
sys/arch/arm/nxp/imx6_srcreg.h
67
#define SRC_SRSR_JTAG_RST_B __BIT(5)
sys/arch/arm/nxp/imx6_srcreg.h
68
#define SRC_SRSR_WDOG_RST_B __BIT(4)
sys/arch/arm/nxp/imx6_srcreg.h
69
#define SRC_SRSR_IPP_USER_RESET_ __BIT(3)
sys/arch/arm/nxp/imx6_srcreg.h
70
#define SRC_SRSR_CSU_RESET_B __BIT(2)
sys/arch/arm/nxp/imx6_srcreg.h
71
#define SRC_SRSR_RESERVED1 __BIT(1)
sys/arch/arm/nxp/imx6_srcreg.h
72
#define SRC_SRSR_IPP_RESET_B __BIT(0)
sys/arch/arm/nxp/imx6_srcreg.h
74
#define SRC_SISR_CORE3_WDOG_RST_REQ __BIT(8)
sys/arch/arm/nxp/imx6_srcreg.h
75
#define SRC_SISR_CORE2_WDOG_RST_REQ __BIT(7)
sys/arch/arm/nxp/imx6_srcreg.h
76
#define SRC_SISR_CORE1_WDOG_RST_REQ __BIT(6)
sys/arch/arm/nxp/imx6_srcreg.h
77
#define SRC_SISR_CORE0_WDOG_RST_REQ __BIT(5)
sys/arch/arm/nxp/imx6_srcreg.h
78
#define SRC_SISR_IPU2_PASSED_RESET __BIT(4)
sys/arch/arm/nxp/imx6_srcreg.h
79
#define SRC_SISR_OPEN_VG_PASSED_RESET __BIT(3)
sys/arch/arm/nxp/imx6_srcreg.h
80
#define SRC_SISR_IPU1_PASSED_RESET __BIT(2)
sys/arch/arm/nxp/imx6_srcreg.h
81
#define SRC_SISR_VPU_PASSED_RESET __BIT(1)
sys/arch/arm/nxp/imx6_srcreg.h
82
#define SRC_SISR_GPU_PASSED_RESET __BIT(0)
sys/arch/arm/nxp/imx6_usbphyreg.h
54
#define USBPHY_CTRL_SFTRST __BIT(31)
sys/arch/arm/nxp/imx6_usbphyreg.h
55
#define USBPHY_CTRL_CLKGATE __BIT(30)
sys/arch/arm/nxp/imx6_usbphyreg.h
56
#define USBPHY_CTRL_ENUTMILEVEL3 __BIT(15)
sys/arch/arm/nxp/imx6_usbphyreg.h
57
#define USBPHY_CTRL_ENUTMILEVEL2 __BIT(14)
sys/arch/arm/nxp/imx6_usbreg.h
101
#define USBNC_USB_UH2_HSIC_CTRL_CLK_VLK __BIT(31)
sys/arch/arm/nxp/imx6_usbreg.h
102
#define USBNC_USB_UH2_HSIC_CTRL_HSIC_EN __BIT(12)
sys/arch/arm/nxp/imx6_usbreg.h
103
#define USBNC_USB_UH2_HSIC_CTRL_HSIC_CLK_ON __BIT(11)
sys/arch/arm/nxp/imx6_usbreg.h
105
#define USBNC_USB_UH3_HSIC_CTRL_CLK_VLK __BIT(31)
sys/arch/arm/nxp/imx6_usbreg.h
106
#define USBNC_USB_UH3_HSIC_CTRL_HSIC_EN __BIT(12)
sys/arch/arm/nxp/imx6_usbreg.h
107
#define USBNC_USB_UH3_HSIC_CTRL_HSIC_CLK_ON __BIT(11)
sys/arch/arm/nxp/imx6_usbreg.h
109
#define USBNC_USB_OTG_PHY_CTRL_0_UTMI_CLK_VLD __BIT(31)
sys/arch/arm/nxp/imx6_usbreg.h
111
#define USBNC_USB_UH1_PHY_CTRL_0_UTMI_CLK_VLD __BIT(31)
sys/arch/arm/nxp/imx6_usbreg.h
37
#define USBC_UOG_USBMODE_SDIS __BIT(4)
sys/arch/arm/nxp/imx6_usbreg.h
38
#define USBC_UOG_USBMODE_SLOM __BIT(3)
sys/arch/arm/nxp/imx6_usbreg.h
39
#define USBC_UOG_USBMODE_ES __BIT(2)
sys/arch/arm/nxp/imx6_usbreg.h
44
#define USBC_UH_PORTSC1_PE __BIT(2)
sys/arch/arm/nxp/imx6_usbreg.h
45
#define USBC_UH_PORTSC1_PTS_2 __BIT(25)
sys/arch/arm/nxp/imx6_usbreg.h
46
#define USBC_UH_PORTSC1_PTS_MASK (__BITS(31, 30) | __BIT(25))
sys/arch/arm/nxp/imx6_usbreg.h
48
#define USBC_UH_PORTSC1_PTS_ULPI __BIT(31)
sys/arch/arm/nxp/imx6_usbreg.h
49
#define USBC_UH_PORTSC1_PTS_SERIAL (__BIT(31) | __BIT(30))
sys/arch/arm/nxp/imx6_usbreg.h
50
#define USBC_UH_PORTSC1_PTS_HSIC __BIT(25)
sys/arch/arm/nxp/imx6_usbreg.h
52
#define USBC_UH_USBMODE_SDIS __BIT(4)
sys/arch/arm/nxp/imx6_usbreg.h
53
#define USBC_UH_USBMODE_SLOM __BIT(3)
sys/arch/arm/nxp/imx6_usbreg.h
54
#define USBC_UH_USBMODE_ES __BIT(2)
sys/arch/arm/nxp/imx6_usbreg.h
69
#define USBNC_USB_OTG_CTRL_WIR __BIT(31)
sys/arch/arm/nxp/imx6_usbreg.h
70
#define USBNC_USB_OTG_CTRL_WKUP_VBUS_EN __BIT(17)
sys/arch/arm/nxp/imx6_usbreg.h
71
#define USBNC_USB_OTG_CTRL_WKUP_ID_EN __BIT(16)
sys/arch/arm/nxp/imx6_usbreg.h
72
#define USBNC_USB_OTG_CTRL_WKUP_SW __BIT(15)
sys/arch/arm/nxp/imx6_usbreg.h
73
#define USBNC_USB_OTG_CTRL_WKUP_SW_EN __BIT(14)
sys/arch/arm/nxp/imx6_usbreg.h
74
#define USBNC_USB_OTG_CTRL_UTMI_ON_CLOCK __BIT(13)
sys/arch/arm/nxp/imx6_usbreg.h
75
#define USBNC_USB_OTG_CTRL_WIE __BIT(10)
sys/arch/arm/nxp/imx6_usbreg.h
76
#define USBNC_USB_OTG_CTRL_PWR_POL __BIT(9)
sys/arch/arm/nxp/imx6_usbreg.h
77
#define USBNC_USB_OTG_CTRL_OVER_CUR_POL __BIT(8)
sys/arch/arm/nxp/imx6_usbreg.h
78
#define USBNC_USB_OTG_CTRL_OVER_CUR_DIS __BIT(7)
sys/arch/arm/nxp/imx6_usbreg.h
80
#define USBNC_USB_UH1_CTRL_WIR __BIT(31)
sys/arch/arm/nxp/imx6_usbreg.h
81
#define USBNC_USB_UH1_CTRL_WKUP_VBUS_EN __BIT(17)
sys/arch/arm/nxp/imx6_usbreg.h
82
#define USBNC_USB_UH1_CTRL_WKUP_ID_EN __BIT(16)
sys/arch/arm/nxp/imx6_usbreg.h
83
#define USBNC_USB_UH1_CTRL_WKUP_SW __BIT(15)
sys/arch/arm/nxp/imx6_usbreg.h
84
#define USBNC_USB_UH1_CTRL_WKUP_SW_EN __BIT(14)
sys/arch/arm/nxp/imx6_usbreg.h
85
#define USBNC_USB_UH1_CTRL_UTMI_ON_CLOCK __BIT(13)
sys/arch/arm/nxp/imx6_usbreg.h
86
#define USBNC_USB_UH1_CTRL_WIE __BIT(10)
sys/arch/arm/nxp/imx6_usbreg.h
87
#define USBNC_USB_UH1_CTRL_PWR_POL __BIT(9)
sys/arch/arm/nxp/imx6_usbreg.h
88
#define USBNC_USB_UH1_CTRL_OVER_CUR_POL __BIT(8)
sys/arch/arm/nxp/imx6_usbreg.h
89
#define USBNC_USB_UH1_CTRL_OVER_CUR_DIS __BIT(7)
sys/arch/arm/nxp/imx6_usbreg.h
91
#define USBNC_USB_UH2_CTRL_WKUP_SW __BIT(15)
sys/arch/arm/nxp/imx6_usbreg.h
92
#define USBNC_USB_UH2_CTRL_WKUP_SW_EN __BIT(14)
sys/arch/arm/nxp/imx6_usbreg.h
93
#define USBNC_USB_UH2_CTRL_UTMI_ON_CLOCK __BIT(13)
sys/arch/arm/nxp/imx6_usbreg.h
94
#define USBNC_USB_UH2_CTRL_WIE __BIT(10)
sys/arch/arm/nxp/imx6_usbreg.h
96
#define USBNC_USB_UH3_CTRL_WKUP_SW __BIT(15)
sys/arch/arm/nxp/imx6_usbreg.h
97
#define USBNC_USB_UH3_CTRL_WKUP_SW_EN __BIT(14)
sys/arch/arm/nxp/imx6_usbreg.h
98
#define USBNC_USB_UH3_CTRL_UTMI_ON_CLOCK __BIT(13)
sys/arch/arm/nxp/imx6_usbreg.h
99
#define USBNC_USB_UH3_CTRL_WIE __BIT(10)
sys/arch/arm/nxp/imx7_gpc.c
180
val |= __BIT(bit);
sys/arch/arm/nxp/imx7_gpc.c
196
val &= ~__BIT(bit);
sys/arch/arm/nxp/imx7_gpc.c
47
#define OTG2_A53_DOMAIN __BIT(5)
sys/arch/arm/nxp/imx7_gpc.c
48
#define OTG1_A53_DOMAIN __BIT(4)
sys/arch/arm/nxp/imx7_gpc.c
51
#define USB_OTG2_SW_PUP_REQ __BIT(3)
sys/arch/arm/nxp/imx7_gpc.c
52
#define USB_OTG1_SW_PUP_REQ __BIT(2)
sys/arch/arm/nxp/imx7d_ccm.c
120
ANATOP_PLL(PLL_SYS_MAIN, "pll_sys_main", "osc", 0xb0, __BIT(0), IMX_PLL_480M_528M),
sys/arch/arm/nxp/imx7d_ccm.c
123
ANATOP_MUX(PLL_SYS_MAIN_BYPASS, "pll_sys_main_bypass", pll_sys_main_bypass_p, 0xb0, __BIT(16)),
sys/arch/arm/nxp/imx7d_ccm.c
124
ANATOP_MUX(PLL_ENET_MAIN_BYPASS, "pll_enet_main_bypass", pll_enet_main_bypass_p, 0xe0, __BIT(16)),
sys/arch/arm/nxp/imx7d_ccm.c
126
ANATOP_GATE(PLL_SYS_MAIN_CLK, "pll_sys_main_clk", "pll_sys_main_bypass", 0xb0, __BIT(13)),
sys/arch/arm/nxp/imx7d_ccm.c
130
ANATOP_GATE(PLL_SYS_MAIN_240M_CLK, "pll_sys_main_240m_clk", "pll_sys_main_240m", 0xb0, __BIT(5)),
sys/arch/arm/nxp/imx7d_ccm.c
141
ANATOP_GATE(PLL_ENET_MAIN_500M_CLK, "pll_enet_500m_clk", "pll_enet_500m", 0xe0, __BIT(12)),
sys/arch/arm/nxp/imx7d_ccm.c
142
ANATOP_GATE(PLL_ENET_MAIN_250M_CLK, "pll_enet_250m_clk", "pll_enet_250m", 0xe0, __BIT(11)),
sys/arch/arm/nxp/imx7d_ccm.c
143
ANATOP_GATE(PLL_ENET_MAIN_250M_CLK, "pll_enet_250m_clk", "pll_enet_250m", 0xe0, __BIT(11)),
sys/arch/arm/nxp/imx7d_ccm.c
144
ANATOP_GATE(PLL_ENET_MAIN_125M_CLK, "pll_enet_125m_clk", "pll_enet_125m", 0xe0, __BIT(10)),
sys/arch/arm/nxp/imx7d_ccm.c
145
ANATOP_GATE(PLL_ENET_MAIN_100M_CLK, "pll_enet_100m_clk", "pll_enet_100m", 0xe0, __BIT(9)),
sys/arch/arm/nxp/imx7d_ccm.c
146
ANATOP_GATE(PLL_ENET_MAIN_50M_CLK, "pll_enet_50m_clk", "pll_enet_50m", 0xe0, __BIT(8)),
sys/arch/arm/nxp/imx7d_ccm.c
147
ANATOP_GATE(PLL_ENET_MAIN_40M_CLK, "pll_enet_40m_clk", "pll_enet_40m", 0xe0, __BIT(7)),
sys/arch/arm/nxp/imx7d_ccm.c
148
ANATOP_GATE(PLL_ENET_MAIN_25M_CLK, "pll_enet_25m_clk", "pll_enet_25m", 0xe0, __BIT(6)),
sys/arch/arm/nxp/imx7d_ccm.c
165
IMX_GATE(UART1_ROOT_CG, "uart1_cg", "uart1_src", 0xaf80, __BIT(18)),
sys/arch/arm/nxp/imx7d_ccm.c
166
IMX_GATE(UART2_ROOT_CG, "uart2_cg", "uart2_src", 0xb000, __BIT(18)),
sys/arch/arm/nxp/imx7d_ccm.c
167
IMX_GATE(UART3_ROOT_CG, "uart3_cg", "uart3_src", 0xb080, __BIT(18)),
sys/arch/arm/nxp/imx7d_ccm.c
168
IMX_GATE(UART4_ROOT_CG, "uart4_cg", "uart4_src", 0xb100, __BIT(18)),
sys/arch/arm/nxp/imx7d_ccm.c
169
IMX_GATE(UART5_ROOT_CG, "uart5_cg", "uart5_src", 0xb180, __BIT(18)),
sys/arch/arm/nxp/imx7d_ccm.c
170
IMX_GATE(UART6_ROOT_CG, "uart6_cg", "uart6_src", 0xb200, __BIT(18)),
sys/arch/arm/nxp/imx7d_ccm.c
171
IMX_GATE(UART7_ROOT_CG, "uart7_cg", "uart7_src", 0xb280, __BIT(18)),
sys/arch/arm/nxp/imx7d_ccm.c
189
IMX_GATE(UART1_ROOT_CLK, "uart1_root_clk", "uart1_post_div", 0x4940, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
190
IMX_GATE(UART2_ROOT_CLK, "uart2_root_clk", "uart2_post_div", 0x4950, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
191
IMX_GATE(UART3_ROOT_CLK, "uart3_root_clk", "uart3_post_div", 0x4960, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
192
IMX_GATE(UART4_ROOT_CLK, "uart4_root_clk", "uart4_post_div", 0x4970, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
193
IMX_GATE(UART5_ROOT_CLK, "uart5_root_clk", "uart5_post_div", 0x4980, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
194
IMX_GATE(UART6_ROOT_CLK, "uart6_root_clk", "uart6_post_div", 0x4990, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
195
IMX_GATE(UART7_ROOT_CLK, "uart7_root_clk", "uart7_post_div", 0x49a0, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
202
IMX_GATE(I2C1_ROOT_CG, "i2c1_cg", "i2c1_src", 0xad80, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
203
IMX_GATE(I2C2_ROOT_CG, "i2c2_cg", "i2c2_src", 0xae00, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
204
IMX_GATE(I2C3_ROOT_CG, "i2c3_cg", "i2c3_src", 0xae80, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
205
IMX_GATE(I2C4_ROOT_CG, "i2c4_cg", "i2c4_src", 0xaf00, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
217
IMX_GATE(I2C1_ROOT_CLK, "i2c1_root_clk", "i2c1_post_div", 0x4880, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
218
IMX_GATE(I2C2_ROOT_CLK, "i2c2_root_clk", "i2c2_post_div", 0x4890, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
219
IMX_GATE(I2C3_ROOT_CLK, "i2c3_root_clk", "i2c3_post_div", 0x48a0, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
220
IMX_GATE(I2C4_ROOT_CLK, "i2c4_root_clk", "i2c4_post_div", 0x48b0, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
223
IMX_GATE(ENET_AXI_ROOT_CG, "enet_axi_cg", "enet_axi_src", 0x8900, __BIT(28)),
sys/arch/arm/nxp/imx7d_ccm.c
229
IMX_GATE(ENET1_TIME_ROOT_CG, "enet1_time_cg", "enet1_time_src", 0xa780, __BIT(28)),
sys/arch/arm/nxp/imx7d_ccm.c
230
IMX_GATE(ENET2_TIME_ROOT_CG, "enet2_time_cg", "enet2_time_src", 0xa880, __BIT(28)),
sys/arch/arm/nxp/imx7d_ccm.c
235
IMX_GATE(ENET1_IPG_ROOT_CLK, "enet1_ipg_root_clk", "enet_axi_post_div", 0x4700, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
236
IMX_GATE(ENET2_IPG_ROOT_CLK, "enet2_ipg_root_clk", "enet_axi_post_div", 0x4710, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
237
IMX_GATE(ENET1_TIME_ROOT_CLK, "enet1_time_root_clk", "enet1_time_post_div", 0x4700, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
238
IMX_GATE(ENET2_TIME_ROOT_CLK, "enet2_time_root_clk", "enet2_time_post_div", 0x4710, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
239
IMX_GATE(ENET_AXI_ROOT_CLK, "enet_axi_root_clk", "enet_axi_post_div", 0x4060, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
242
IMX_GATE(ENET_PHY_REF_ROOT_CG, "enet_phy_ref_cg", "enet_phy_ref_src", 0xa900, __BIT(28)),
sys/arch/arm/nxp/imx7d_ccm.c
247
IMX_GATE(AHB_CHANNEL_ROOT_CG, "ahb_cg", "ahb_src", 0x9000, __BIT(28)),
sys/arch/arm/nxp/imx7d_ccm.c
253
IMX_GATE(NAND_USDHC_BUS_ROOT_CG, "nand_usdhc_cg", "nand_usdhc_src", 0x8980, __BIT(28)),
sys/arch/arm/nxp/imx7d_ccm.c
260
IMX_GATE(USDHC1_ROOT_CG, "usdhc1_cg", "usdhc1_src", 0xab00, __BIT(28)),
sys/arch/arm/nxp/imx7d_ccm.c
261
IMX_GATE(USDHC2_ROOT_CG, "usdhc2_cg", "usdhc2_src", 0xab80, __BIT(28)),
sys/arch/arm/nxp/imx7d_ccm.c
262
IMX_GATE(USDHC3_ROOT_CG, "usdhc3_cg", "usdhc3_src", 0xac00, __BIT(28)),
sys/arch/arm/nxp/imx7d_ccm.c
269
IMX_GATE(USDHC1_ROOT_CLK, "usdhc1_root_clk", "usdhc1_post_div", 0x46c0, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
270
IMX_GATE(USDHC2_ROOT_CLK, "usdhc2_root_clk", "usdhc2_post_div", 0x46d0, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
271
IMX_GATE(USDHC3_ROOT_CLK, "usdhc3_root_clk", "usdhc3_post_div", 0x46e0, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
273
IMX_GATE(USB_CTRL_CLK, "usb_ctrl_clk", "ahb_root_clk", 0x4680, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
274
IMX_GATE(USB_PHY1_CLK, "usb_phy1_clk", "pll_usb1_main_clk", 0x46a0, __BIT(0)),
sys/arch/arm/nxp/imx7d_ccm.c
275
IMX_GATE(USB_PHY2_CLK, "usb_phy2_clk", "pll_usb_main_clk", 0x46b0, __BIT(0)),
sys/arch/arm/nxp/imx8mq_ccm.c
100
IMX_GATE(SYS1_PLL_160M_CG, "sys1_pll_160m_cg", "sys1_pll_out", 0x30, __BIT(17)),
sys/arch/arm/nxp/imx8mq_ccm.c
101
IMX_GATE(SYS1_PLL_200M_CG, "sys1_pll_200m_cg", "sys1_pll_out", 0x30, __BIT(19)),
sys/arch/arm/nxp/imx8mq_ccm.c
102
IMX_GATE(SYS1_PLL_266M_CG, "sys1_pll_266m_cg", "sys1_pll_out", 0x30, __BIT(21)),
sys/arch/arm/nxp/imx8mq_ccm.c
103
IMX_GATE(SYS1_PLL_400M_CG, "sys1_pll_400m_cg", "sys1_pll_out", 0x30, __BIT(23)),
sys/arch/arm/nxp/imx8mq_ccm.c
104
IMX_GATE(SYS1_PLL_800M_CG, "sys1_pll_800m_cg", "sys1_pll_out", 0x30, __BIT(25)),
sys/arch/arm/nxp/imx8mq_ccm.c
116
IMX_GATE(SYS2_PLL_50M_CG, "sys2_pll_50m_cg", "sys2_pll_out", 0x3c, __BIT(9)),
sys/arch/arm/nxp/imx8mq_ccm.c
117
IMX_GATE(SYS2_PLL_100M_CG, "sys2_pll_100m_cg", "sys2_pll_out", 0x3c, __BIT(11)),
sys/arch/arm/nxp/imx8mq_ccm.c
118
IMX_GATE(SYS2_PLL_125M_CG, "sys2_pll_125m_cg", "sys2_pll_out", 0x3c, __BIT(13)),
sys/arch/arm/nxp/imx8mq_ccm.c
119
IMX_GATE(SYS2_PLL_166M_CG, "sys2_pll_166m_cg", "sys2_pll_out", 0x3c, __BIT(15)),
sys/arch/arm/nxp/imx8mq_ccm.c
120
IMX_GATE(SYS2_PLL_200M_CG, "sys2_pll_200m_cg", "sys2_pll_out", 0x3c, __BIT(17)),
sys/arch/arm/nxp/imx8mq_ccm.c
121
IMX_GATE(SYS2_PLL_250M_CG, "sys2_pll_250m_cg", "sys2_pll_out", 0x3c, __BIT(19)),
sys/arch/arm/nxp/imx8mq_ccm.c
122
IMX_GATE(SYS2_PLL_333M_CG, "sys2_pll_333m_cg", "sys2_pll_out", 0x3c, __BIT(21)),
sys/arch/arm/nxp/imx8mq_ccm.c
123
IMX_GATE(SYS2_PLL_500M_CG, "sys2_pll_500m_cg", "sys2_pll_out", 0x3c, __BIT(23)),
sys/arch/arm/nxp/imx8mq_ccm.c
124
IMX_GATE(SYS2_PLL_1000M_CG, "sys2_pll_1000m_cg", "sys2_pll_out", 0x3c, __BIT(25)),
sys/arch/arm/nxp/imx8mq_ccm.c
96
IMX_GATE(SYS1_PLL_40M_CG, "sys1_pll_40m_cg", "sys1_pll_out", 0x30, __BIT(9)),
sys/arch/arm/nxp/imx8mq_ccm.c
97
IMX_GATE(SYS1_PLL_80M_CG, "sys1_pll_80m_cg", "sys1_pll_out", 0x30, __BIT(11)),
sys/arch/arm/nxp/imx8mq_ccm.c
98
IMX_GATE(SYS1_PLL_100M_CG, "sys1_pll_100m_cg", "sys1_pll_out", 0x30, __BIT(13)),
sys/arch/arm/nxp/imx8mq_ccm.c
99
IMX_GATE(SYS1_PLL_133M_CG, "sys1_pll_133m_cg", "sys1_pll_out", 0x30, __BIT(15)),
sys/arch/arm/nxp/imx8mq_usbphy.c
43
#define REF_SSP_EN __BIT(2)
sys/arch/arm/nxp/imx8mq_usbphy.c
46
#define PHY_VDATDATENB0 __BIT(20)
sys/arch/arm/nxp/imx8mq_usbphy.c
47
#define PHY_VDATSRCENB0 __BIT(19)
sys/arch/arm/nxp/imx8mq_usbphy.c
48
#define PHY_ATERESET __BIT(3)
sys/arch/arm/nxp/imx8mq_usbphy.c
49
#define PHY_COMMONONN __BIT(1)
sys/arch/arm/nxp/imx8mq_usbphy.c
50
#define PHY_RESET __BIT(0)
sys/arch/arm/nxp/imx8mq_usbphy.c
53
#define PHY_TXENABLEN0 __BIT(8)
sys/arch/arm/nxp/imx_ahcisatareg.h
33
#define SATA_CAP_SSS __BIT(27)
sys/arch/arm/nxp/imx_ahcisatareg.h
35
#define SATA_PI_PI __BIT(0)
sys/arch/arm/nxp/imx_ahcisatareg.h
51
#define SATA_P0PHYCR_CR_READ __BIT(19)
sys/arch/arm/nxp/imx_ahcisatareg.h
52
#define SATA_P0PHYCR_CR_WRITE __BIT(18)
sys/arch/arm/nxp/imx_ahcisatareg.h
53
#define SATA_P0PHYCR_CR_CAP_DATA __BIT(17)
sys/arch/arm/nxp/imx_ahcisatareg.h
54
#define SATA_P0PHYCR_CR_CAP_ADDR __BIT(16)
sys/arch/arm/nxp/imx_ahcisatareg.h
57
#define SATA_P0PHYSR_CR_ACK __BIT(18)
sys/arch/arm/nxp/imx_ahcisatareg.h
62
#define SATA_PHY_CLOCK_CTL_OVRD_MPLL_PWRON __BIT(2)
sys/arch/arm/nxp/imx_ahcisatareg.h
65
#define SATA_PHY_CLOCK_RESET_RST __BIT(0)
sys/arch/arm/nxp/imx_ahcisatareg.h
68
#define SATA_PHY_LANE0_OUT_STAT_RX_PLL_STATE __BIT(1)
sys/arch/arm/nxp/imx_ahcisatareg.h
73
#define SATA_PHY_LANE0_RX_OVRD_RX_EN __BIT(2)
sys/arch/arm/nxp/imx_ahcisatareg.h
74
#define SATA_PHY_LANE0_RX_OVRD_RX_PLL_PWRON __BIT(1)
sys/arch/arm/nxp/imx_ccm.h
152
#define IMX_PLL_ARM __BIT(0)
sys/arch/arm/nxp/imx_ccm.h
153
#define IMX_PLL_480M_528M __BIT(1)
sys/arch/arm/nxp/imx_ccm.h
154
#define IMX_PLL_ENET __BIT(2)
sys/arch/arm/nxp/imx_ccm.h
260
#define IMX_DIV_SET_RATE_PARENT __BIT(0)
sys/arch/arm/nxp/imx_ccm.h
261
#define IMX_DIV_ROUND_DOWN __BIT(1)
sys/arch/arm/nxp/imx_ccm_composite.c
42
#define TARGET_ROOT_ENABLE __BIT(28)
sys/arch/arm/nxp/imx_ccm_pll.c
41
#define PLL_POWERDOWN __BIT(12)
sys/arch/arm/nxp/imx_ccm_pll.c
42
#define PLL_POWERDOWN_ENET __BIT(5)
sys/arch/arm/nxp/imxpcie.c
527
__BIT(bit));
sys/arch/arm/nxp/imxpcie.c
528
v &= ~__BIT(bit);
sys/arch/arm/pic/pic.c
166
l->l_md.md_astpending |= __BIT(1);
sys/arch/arm/pic/pic.c
254
const uint32_t ipl_mask = __BIT(is->is_ipl);
sys/arch/arm/pic/pic.c
258
__BIT(is->is_irq & 0x1f));
sys/arch/arm/pic/pic.c
262
ci->ci_pending_pics |= __BIT(pic->pic_id);
sys/arch/arm/pic/pic.c
301
pending &= ~__BIT(n);
sys/arch/arm/pic/pic.c
302
ipl_mask |= __BIT(is->is_ipl);
sys/arch/arm/pic/pic.c
307
ci->ci_pending_pics |= __BIT(pic->pic_id);
sys/arch/arm/pic/pic.c
324
irq_mask = __BIT(irq);
sys/arch/arm/pic/pic.c
395
const uint32_t ipl_mask = __BIT(ipl);
sys/arch/arm/pic/pic.c
450
atomic_and_32(ipending, ~__BIT(irq));
sys/arch/arm/pic/pic.c
464
blocked_irqs |= __BIT(irq);
sys/arch/arm/pic/pic.c
473
ci->ci_blocked_pics |= __BIT(pic->pic_id);
sys/arch/arm/pic/pic.c
483
ci->ci_pending_pics &= ~__BIT(pic->pic_id);
sys/arch/arm/pic/pic.c
523
blocked_pics &= ~__BIT(pic_id);
sys/arch/arm/pic/pic.c
542
pending_pics &= ~__BIT(pic_id);
sys/arch/arm/pic/pic.c
550
const uint32_t ipl_mask = __BIT(ipl);
sys/arch/arm/pic/pic.c
570
while ((ci->ci_pending_ipls & ~__BIT(newipl)) > __BIT(newipl)) {
sys/arch/arm/pic/pic.c
571
KASSERT(ci->ci_pending_ipls < __BIT(NIPL));
sys/arch/arm/pic/pic.c
586
if (newipl == IPL_NONE && (l->l_md.md_astpending & __BIT(1))) {
sys/arch/arm/pic/pic.c
740
__BIT(is->is_irq & 0x1f));
sys/arch/arm/pic/pic.c
823
__BIT(is->is_irq & 0x1f));
sys/arch/arm/pic/pic.c
859
(*pic->pic_ops->pic_block_irqs)(pic, irq & ~0x1f, __BIT(irq & 0x1f));
sys/arch/arm/pic/pic.c
920
(*pic->pic_ops->pic_block_irqs)(pic, irq & ~0x1f, __BIT(irq & 0x1f));
sys/arch/arm/pic/pic.c
931
(*pic->pic_ops->pic_unblock_irqs)(pic, irq & ~0x1f, __BIT(irq & 0x1f));
sys/arch/arm/rockchip/rk3066_smp.c
118
val &= ~__BIT(cpuno);
sys/arch/arm/rockchip/rk3066_smp.c
124
} while ((val & __BIT(cpuno)) != 0);
sys/arch/arm/rockchip/rk3288_cru.c
102
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3288_cru.c
109
__BIT(4), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
115
__BIT(5), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
121
__BIT(2), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
125
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3288_cru.c
128
__BIT(0), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
134
__BIT(8), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
140
__BIT(3), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
149
__BIT(8), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
159
__BIT(10), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
169
__BIT(12), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
179
__BIT(14), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
189
__BIT(12), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
202
__BIT(0), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
209
__BIT(1), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
216
__BIT(2), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
223
__BIT(3), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
232
__BIT(5), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
240
__BIT(4), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
246
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3288_cru.c
249
__BIT(9), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
253
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3288_cru.c
256
__BIT(10), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
260
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3288_cru.c
263
__BIT(11), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
271
__BIT(7), /* gate_mask */
sys/arch/arm/rockchip/rk3288_cru.c
283
RK_MUX(0, "uart_src", mux_2plls_parents, CLKSEL_CON(15), __BIT(15)),
sys/arch/arm/rockchip/rk3288_cru.c
284
RK_MUX(RK3288_SCLK_MAC, "mac_clk", mac_parents, CLKSEL_CON(21), __BIT(4)),
sys/arch/arm/rockchip/rk3288_cru.c
84
__BIT(8), /* mode_mask */
sys/arch/arm/rockchip/rk3288_cru.c
85
__BIT(2), /* lock_mask */
sys/arch/arm/rockchip/rk3288_cru.c
90
__BIT(12), /* mode_mask */
sys/arch/arm/rockchip/rk3288_cru.c
91
__BIT(3), /* lock_mask */
sys/arch/arm/rockchip/rk3288_cru.c
96
__BIT(14), /* mode_mask */
sys/arch/arm/rockchip/rk3288_cru.c
97
__BIT(4), /* lock_mask */
sys/arch/arm/rockchip/rk3288_iomux.c
75
#define IOMUX_NOROUTE __BIT(0)
sys/arch/arm/rockchip/rk3288_iomux.c
76
#define IOMUX_4BIT __BIT(1)
sys/arch/arm/rockchip/rk3288_usb.c
44
#define GRF_UOCn_CON0_SIDDQ __BIT(13)
sys/arch/arm/rockchip/rk3328_cru.c
166
__BIT(0), /* mode_mask */
sys/arch/arm/rockchip/rk3328_cru.c
167
__BIT(4), /* lock_mask */
sys/arch/arm/rockchip/rk3328_cru.c
172
__BIT(4), /* mode_mask */
sys/arch/arm/rockchip/rk3328_cru.c
173
__BIT(3), /* lock_mask */
sys/arch/arm/rockchip/rk3328_cru.c
178
__BIT(8), /* mode_mask */
sys/arch/arm/rockchip/rk3328_cru.c
179
__BIT(2), /* lock_mask */
sys/arch/arm/rockchip/rk3328_cru.c
184
__BIT(12), /* mode_mask */
sys/arch/arm/rockchip/rk3328_cru.c
185
__BIT(1), /* lock_mask */
sys/arch/arm/rockchip/rk3328_cru.c
190
__BIT(1), /* mode_mask */
sys/arch/arm/rockchip/rk3328_cru.c
191
__BIT(0), /* lock_mask */
sys/arch/arm/rockchip/rk3328_cru.c
205
__BIT(0), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
212
__BIT(1), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
219
__BIT(2), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
223
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3328_cru.c
226
__BIT(7), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
230
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3328_cru.c
233
__BIT(8), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
246
__BIT(2), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
253
__BIT(1), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
260
__BIT(3), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
267
__BIT(4), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
274
__BIT(5), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
281
__BIT(14), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
288
__BIT(0), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
295
__BIT(2), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
302
__BIT(2), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
309
__BIT(0), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
313
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3328_cru.c
316
__BIT(1), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
320
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3328_cru.c
323
__BIT(5), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
327
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3328_cru.c
330
__BIT(9), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
334
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3328_cru.c
337
__BIT(10), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
341
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3328_cru.c
344
__BIT(11), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
348
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3328_cru.c
351
__BIT(12), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
358
__BIT(6), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
362
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3328_cru.c
365
__BIT(4), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
413
RK_MUX(RK3328_HDMIPHY, "hdmiphy", mux_hdmiphy_parents, MISC_CON, __BIT(13)),
sys/arch/arm/rockchip/rk3328_cru.c
414
RK_MUX(RK3328_USB480M, "usb480m", mux_usb480m_parents, MISC_CON, __BIT(15)),
sys/arch/arm/rockchip/rk3328_cru.c
418
RK_MUXGRF(RK3328_SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_parents, GRF_MAC_CON1, __BIT(10)),
sys/arch/arm/rockchip/rk3328_cru.c
419
RK_MUXGRF(RK3328_SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_parents, GRF_SOC_CON4, __BIT(14)),
sys/arch/arm/rockchip/rk3328_cru.c
424
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3328_cru.c
427
__BIT(1), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
431
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3328_cru.c
434
__BIT(4), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
438
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3328_cru.c
441
__BIT(8), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
445
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3328_cru.c
448
__BIT(12), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
478
__BIT(12), /* mux_mask */
sys/arch/arm/rockchip/rk3328_cru.c
481
__BIT(12), /* gate_mask */
sys/arch/arm/rockchip/rk3328_cru.c
485
__BIT(12), /* mux_mask */
sys/arch/arm/rockchip/rk3328_cru.c
488
__BIT(12), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
1005
__BIT(12), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
1011
__BIT(10), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
1015
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
1018
__BIT(7), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
1026
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
1029
__BIT(3), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
1033
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
1036
__BIT(6), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
1040
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
1043
__BIT(9), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
1066
__BIT(2), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
1069
__BIT(12), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
1075
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
1078
__BIT(11), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
1088
__BIT(8), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
1097
__BIT(0), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
220
#define PLL_LOCK __BIT(31)
sys/arch/arm/rockchip/rk3399_cru.c
228
#define PLL_DSMPD __BIT(3)
sys/arch/arm/rockchip/rk3399_cru.c
399
__BIT(8), /* mode_mask */
sys/arch/arm/rockchip/rk3399_cru.c
400
__BIT(31), /* lock_mask */
sys/arch/arm/rockchip/rk3399_cru.c
405
__BIT(8), /* mode_mask */
sys/arch/arm/rockchip/rk3399_cru.c
406
__BIT(31), /* lock_mask */
sys/arch/arm/rockchip/rk3399_cru.c
411
__BIT(8), /* mode_mask */
sys/arch/arm/rockchip/rk3399_cru.c
412
__BIT(31), /* lock_mask */
sys/arch/arm/rockchip/rk3399_cru.c
417
__BIT(8), /* mode_mask */
sys/arch/arm/rockchip/rk3399_cru.c
418
__BIT(31), /* lock_mask */
sys/arch/arm/rockchip/rk3399_cru.c
423
__BIT(8), /* mode_mask */
sys/arch/arm/rockchip/rk3399_cru.c
424
__BIT(31), /* lock_mask */
sys/arch/arm/rockchip/rk3399_cru.c
429
__BIT(8), /* mode_mask */
sys/arch/arm/rockchip/rk3399_cru.c
430
__BIT(31), /* lock_mask */
sys/arch/arm/rockchip/rk3399_cru.c
435
__BIT(8), /* mode_mask */
sys/arch/arm/rockchip/rk3399_cru.c
436
__BIT(31), /* lock_mask */
sys/arch/arm/rockchip/rk3399_cru.c
470
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
473
__BIT(2), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
479
__BIT(3), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
485
__BIT(4), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
502
__BIT(2), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
512
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
515
__BIT(2), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
521
__BIT(3), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
527
__BIT(4), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
542
__BIT(4), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
551
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
554
__BIT(12), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
562
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
565
__BIT(4), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
584
RK_MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_parents, CLKSEL_CON(33), __BIT(15)),
sys/arch/arm/rockchip/rk3399_cru.c
589
__BIT(0), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
595
__BIT(2), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
601
__BIT(4), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
607
__BIT(6), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
623
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
626
__BIT(13), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
633
__BIT(0), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
640
__BIT(1), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
653
__BIT(14), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
659
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
674
__BIT(5), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
676
RK_MUX(RK3399_SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_parents, CLKSEL_CON(19), __BIT(4)),
sys/arch/arm/rockchip/rk3399_cru.c
685
__BIT(17), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
688
__BIT(10), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
695
__BIT(11), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
716
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
719
__BIT(3), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
723
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
726
__BIT(4), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
733
__BIT(0), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
743
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
746
__BIT(4), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
753
__BIT(5), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
757
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
760
__BIT(6), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
767
__BIT(7), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
775
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
778
__BIT(0), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
782
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
785
__BIT(2), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
789
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
792
__BIT(4), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
796
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
799
__BIT(1), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
803
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
806
__BIT(3), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
810
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
813
__BIT(5), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
827
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
830
__BIT(12), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
834
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
837
__BIT(13), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
841
__BIT(7), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
844
__BIT(14), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
848
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
851
__BIT(15), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
855
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
858
__BIT(13), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
878
__BIT(2), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
884
__BIT(6), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
886
RK_MUX(RK3399_SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_parents, CLKSEL_CON(18), __BIT(10)),
sys/arch/arm/rockchip/rk3399_cru.c
892
__BIT(3), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
894
RK_MUX(RK3399_SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_parents, CLKSEL_CON(18), __BIT(7)),
sys/arch/arm/rockchip/rk3399_cru.c
902
__BIT(7), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
909
__BIT(7), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
920
__BIT(15), /* mux_mask */
sys/arch/arm/rockchip/rk3399_cru.c
923
__BIT(1), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
933
__BIT(8), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
939
__BIT(9), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
946
__BIT(12), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
953
RK_MUX(RK3399_DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_parents, CLKSEL_CON(49), __BIT(11)),
sys/arch/arm/rockchip/rk3399_cru.c
961
__BIT(10), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
967
__BIT(11), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
974
__BIT(13), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
981
RK_MUX(RK3399_DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_parents, CLKSEL_CON(50), __BIT(11)),
sys/arch/arm/rockchip/rk3399_cru.c
989
__BIT(0), /* gate_mask */
sys/arch/arm/rockchip/rk3399_cru.c
995
__BIT(1), /* gate_mask */
sys/arch/arm/rockchip/rk3399_iomux.c
469
#define GRF_SOC_CON7_FORCE_JTAG __BIT(12)
sys/arch/arm/rockchip/rk3399_pcie.c
113
#define PCIE_ATR_HDR_RID __BIT(23)
sys/arch/arm/rockchip/rk3399_pcie.c
48
#define PCBSC_PCIE_GEN_SEL __BIT(7)
sys/arch/arm/rockchip/rk3399_pcie.c
51
#define PCBSC_MODE_SELECT __BIT(6)
sys/arch/arm/rockchip/rk3399_pcie.c
56
#define PCBSC_ARI_EN SETREG(__BIT(3), 1) /* Alternate Routing ID Enable */
sys/arch/arm/rockchip/rk3399_pcie.c
57
#define PCBSC_SR_IOV_EN SETREG(__BIT(2), 1)
sys/arch/arm/rockchip/rk3399_pcie.c
58
#define PCBSC_LINK_TRAIN_EN SETREG(__BIT(1), 1)
sys/arch/arm/rockchip/rk3399_pcie.c
59
#define PCBSC_CONF_EN SETREG(__BIT(0), 1) /* Config enable */
sys/arch/arm/rockchip/rk3399_pcie.c
70
#define PCIM_INTx_MASK(x) SETREG(__BIT((x)+5), 1)
sys/arch/arm/rockchip/rk3399_pcie.c
71
#define PCIM_INTx_ENAB(x) SETREG(__BIT((x)+5), 0)
sys/arch/arm/rockchip/rk3399_pcie.c
89
#define PCIE_LM_RCBARPME __BIT(17)
sys/arch/arm/rockchip/rk3399_pcie.c
90
#define PCIE_LM_RCBARPMS __BIT(18)
sys/arch/arm/rockchip/rk3399_pcie.c
91
#define PCIE_LM_RCBARPIE __BIT(19)
sys/arch/arm/rockchip/rk3399_pcie.c
92
#define PCIE_LM_RCBARPIS __BIT(20)
sys/arch/arm/rockchip/rk3399_pmucru.c
148
#define PLL_LOCK __BIT(31)
sys/arch/arm/rockchip/rk3399_pmucru.c
156
#define PLL_DSMPD __BIT(3)
sys/arch/arm/rockchip/rk3399_pmucru.c
292
__BIT(8), /* mode_mask */
sys/arch/arm/rockchip/rk3399_pmucru.c
293
__BIT(31), /* lock_mask */
sys/arch/arm/rockchip/rk3399_pmucru.c
300
__BIT(9), /* gate_mask */
sys/arch/arm/rockchip/rk3399_pmucru.c
306
__BIT(10), /* gate_mask */
sys/arch/arm/rockchip/rk3399_pmucru.c
312
__BIT(11), /* gate_mask */
sys/arch/arm/rockchip/rk3588_cru.c
1009
CLKGATE_CON(0, 9), __BIT(7),
sys/arch/arm/rockchip/rk3588_cru.c
1016
CLKGATE_CON(0, 8), __BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
1031
CLKGATE_CON(0, 9), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
1044
CLKGATE_CON(0, 68), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
1049
CLKGATE_CON(0, 68), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
1054
CLKGATE_CON(0, 10), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
1075
CLKGATE_CON(0, 15), __BIT(4),
sys/arch/arm/rockchip/rk3588_cru.c
1084
CLKGATE_CON(0, 15), __BIT(7),
sys/arch/arm/rockchip/rk3588_cru.c
1093
CLKGATE_CON(0, 15), __BIT(10),
sys/arch/arm/rockchip/rk3588_cru.c
1104
CLKGATE_CON(0, 15), __BIT(14),
sys/arch/arm/rockchip/rk3588_cru.c
1139
CLKGATE_CON(0, 11), __BIT(9),
sys/arch/arm/rockchip/rk3588_cru.c
1146
CLKGATE_CON(0, 11), __BIT(11),
sys/arch/arm/rockchip/rk3588_cru.c
1153
CLKGATE_CON(0, 11), __BIT(13),
sys/arch/arm/rockchip/rk3588_cru.c
1162
CLKGATE_CON(0, 17), __BIT(8),
sys/arch/arm/rockchip/rk3588_cru.c
1177
CLKGATE_CON(0, 16), __BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
1184
CLKGATE_CON(0, 17), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
1191
CLKGATE_CON(0, 17), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
1198
CLKGATE_CON(0, 17), __BIT(5),
sys/arch/arm/rockchip/rk3588_cru.c
1219
CLKGATE_CON(0, 11), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
1224
CLKGATE_CON(0, 11), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
1229
CLKGATE_CON(0, 11), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
1234
CLKGATE_CON(0, 11), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
1239
CLKGATE_CON(0, 11), __BIT(4),
sys/arch/arm/rockchip/rk3588_cru.c
1244
CLKGATE_CON(0, 11), __BIT(5),
sys/arch/arm/rockchip/rk3588_cru.c
1249
CLKGATE_CON(0, 11), __BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
1254
CLKGATE_CON(0, 11), __BIT(7),
sys/arch/arm/rockchip/rk3588_cru.c
1271
CLKGATE_CON(0, 11), __BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
1286
CLKGATE_CON(0, 14), __BIT(11),
sys/arch/arm/rockchip/rk3588_cru.c
1291
CLKGATE_CON(0, 14), __BIT(12),
sys/arch/arm/rockchip/rk3588_cru.c
1296
CLKGATE_CON(0, 14), __BIT(13),
sys/arch/arm/rockchip/rk3588_cru.c
1301
CLKGATE_CON(0, 14), __BIT(14),
sys/arch/arm/rockchip/rk3588_cru.c
1306
CLKGATE_CON(0, 14), __BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
1315
CLKGATE_CON(0, 12), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
1338
CLKGATE_CON(0, 12), __BIT(11),
sys/arch/arm/rockchip/rk3588_cru.c
1351
CLKGATE_CON(0, 12), __BIT(14),
sys/arch/arm/rockchip/rk3588_cru.c
1364
CLKGATE_CON(0, 13), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
1377
CLKGATE_CON(0, 13), __BIT(4),
sys/arch/arm/rockchip/rk3588_cru.c
1390
CLKGATE_CON(0, 13), __BIT(7),
sys/arch/arm/rockchip/rk3588_cru.c
1403
CLKGATE_CON(0, 13), __BIT(10),
sys/arch/arm/rockchip/rk3588_cru.c
1416
CLKGATE_CON(0, 13), __BIT(13),
sys/arch/arm/rockchip/rk3588_cru.c
1429
CLKGATE_CON(0, 14), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
1442
CLKGATE_CON(0, 14), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
1455
CLKGATE_CON(0, 69), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
1460
CLKGATE_CON(0, 69), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
1465
CLKGATE_CON(0, 69), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
1470
CLKGATE_CON(0, 69), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
1481
CLKGATE_CON(0, 69), __BIT(8),
sys/arch/arm/rockchip/rk3588_cru.c
1486
CLKGATE_CON(0, 69), __BIT(9),
sys/arch/arm/rockchip/rk3588_cru.c
1494
CLKGATE_CON(0, 69), __BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
1505
CLKGATE_CON(0, 70), __BIT(4),
sys/arch/arm/rockchip/rk3588_cru.c
1518
CLKGATE_CON(0, 66), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
1527
CLKGATE_CON(0, 66), __BIT(7),
sys/arch/arm/rockchip/rk3588_cru.c
1536
CLKGATE_CON(0, 26), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
1541
CLKGATE_CON(0, 26), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
1546
CLKGATE_CON(0, 26), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
1557
CLKGATE_CON(0, 29), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
1562
CLKGATE_CON(0, 29), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
1567
CLKGATE_CON(0, 29), __BIT(4),
sys/arch/arm/rockchip/rk3588_cru.c
1580
CLKGATE_CON(0, 30), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
1588
CLKGATE_CON(0, 30), __BIT(5),
sys/arch/arm/rockchip/rk3588_cru.c
1607
CLKGATE_CON(0, 29), __BIT(7),
sys/arch/arm/rockchip/rk3588_cru.c
1620
CLKGATE_CON(0, 31), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
1625
CLKGATE_CON(0, 31), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
1632
CLKGATE_CON(0, 31), __BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
1637
CLKGATE_CON(0, 31), __BIT(7),
sys/arch/arm/rockchip/rk3588_cru.c
1644
CLKGATE_CON(0, 31), __BIT(9),
sys/arch/arm/rockchip/rk3588_cru.c
1649
CLKGATE_CON(0, 34), __BIT(10),
sys/arch/arm/rockchip/rk3588_cru.c
1654
CLKGATE_CON(0, 34), __BIT(11),
sys/arch/arm/rockchip/rk3588_cru.c
1659
CLKGATE_CON(0, 35), __BIT(5),
sys/arch/arm/rockchip/rk3588_cru.c
1664
CLKGATE_CON(0, 35), __BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
1669
CLKGATE_CON(0, 32), __BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
1674
CLKGATE_CON(0, 32), __BIT(7),
sys/arch/arm/rockchip/rk3588_cru.c
1679
CLKGATE_CON(0, 32), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
1771
CLKGATE_CON(0, 37), __BIT(10),
sys/arch/arm/rockchip/rk3588_cru.c
1776
CLKGATE_CON(0, 37), __BIT(11),
sys/arch/arm/rockchip/rk3588_cru.c
1781
CLKGATE_CON(0, 37), __BIT(12),
sys/arch/arm/rockchip/rk3588_cru.c
1792
CLKGATE_CON(0, 35), __BIT(10),
sys/arch/arm/rockchip/rk3588_cru.c
1809
CLKGATE_CON(0, 76), __BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
1814
CLKGATE_CON(0, 76), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
1819
CLKGATE_CON(0, 76), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
1828
CLKGATE_CON(0, 40), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
1833
CLKGATE_CON(0, 40), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
1838
CLKGATE_CON(0, 40), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
1843
CLKGATE_CON(0, 40), __BIT(7),
sys/arch/arm/rockchip/rk3588_cru.c
1848
CLKGATE_CON(0, 40), __BIT(8),
sys/arch/arm/rockchip/rk3588_cru.c
1853
CLKGATE_CON(0, 40), __BIT(9),
sys/arch/arm/rockchip/rk3588_cru.c
1858
CLKGATE_CON(0, 41), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
1863
CLKGATE_CON(0, 41), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
1868
CLKGATE_CON(0, 41), __BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
1873
CLKGATE_CON(0, 41), __BIT(7),
sys/arch/arm/rockchip/rk3588_cru.c
1878
CLKGATE_CON(0, 41), __BIT(8),
sys/arch/arm/rockchip/rk3588_cru.c
1883
CLKGATE_CON(0, 75), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
1888
CLKGATE_CON(0, 75), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
1893
CLKGATE_CON(0, 42), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
1898
CLKGATE_CON(0, 42), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
1911
CLKGATE_CON(0, 44), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
1916
CLKGATE_CON(0, 44), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
1921
CLKGATE_CON(0, 44), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
1926
CLKGATE_CON(0, 44), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
1933
CLKGATE_CON(0, 45), __BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
1956
CLKGATE_CON(0, 45), __BIT(9),
sys/arch/arm/rockchip/rk3588_cru.c
1965
CLKGATE_CON(0, 45), __BIT(12),
sys/arch/arm/rockchip/rk3588_cru.c
1972
CLKGATE_CON(0, 48), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
1977
CLKGATE_CON(0, 48), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
1982
CLKGATE_CON(0, 47), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
1987
CLKGATE_CON(0, 47), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
1996
CLKGATE_CON(0, 47), __BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
2001
CLKGATE_CON(0, 48), __BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
2006
CLKGATE_CON(0, 49), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
2011
CLKGATE_CON(0, 49), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
2016
CLKGATE_CON(0, 49), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
2021
CLKGATE_CON(0, 51), __BIT(10),
sys/arch/arm/rockchip/rk3588_cru.c
2046
CLKGATE_CON(0, 50), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
2055
CLKGATE_CON(0, 50), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
2060
CLKGATE_CON(0, 49), __BIT(9),
sys/arch/arm/rockchip/rk3588_cru.c
2075
CLKGATE_CON(0, 49), __BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
2084
CLKGATE_CON(0, 55), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
2089
CLKGATE_CON(0, 55), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
2094
CLKGATE_CON(0, 55), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
2099
CLKGATE_CON(0, 55), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
2104
CLKGATE_CON(0, 55), __BIT(4),
sys/arch/arm/rockchip/rk3588_cru.c
2131
CLKGATE_CON(0, 56), __BIT(11),
sys/arch/arm/rockchip/rk3588_cru.c
2145
CLKGATE_CON(0, 56), __BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
2159
CLKGATE_CON(0, 57), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
2174
CLKGATE_CON(0, 57), __BIT(8),
sys/arch/arm/rockchip/rk3588_cru.c
2188
CLKGATE_CON(0, 56), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
2192
CLKGATE_CON(0, 56), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
2198
CLKGATE_CON(0, 65), __BIT(9),
sys/arch/arm/rockchip/rk3588_cru.c
2203
CLKGATE_CON(0, 59), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
2208
CLKGATE_CON(0, 59), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
2213
CLKGATE_CON(0, 59), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
2218
CLKGATE_CON(0, 59), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
2223
CLKGATE_CON(0, 59), __BIT(4),
sys/arch/arm/rockchip/rk3588_cru.c
2228
CLKGATE_CON(0, 59), __BIT(5),
sys/arch/arm/rockchip/rk3588_cru.c
2233
CLKGATE_CON(0, 52), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
2238
CLKGATE_CON(0, 52), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
2243
CLKGATE_CON(0, 52), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
2248
CLKGATE_CON(0, 52), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
2253
CLKGATE_CON(0, 74), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
2258
CLKGATE_CON(0, 74), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
2270
CLKGATE_CON(0, 62), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
2279
CLKGATE_CON(0, 62), __BIT(5),
sys/arch/arm/rockchip/rk3588_cru.c
2294
CLKGATE_CON(0, 61), __BIT(12),
sys/arch/arm/rockchip/rk3588_cru.c
2307
CLKGATE_CON(0, 60), __BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
2316
CLKGATE_CON(0, 61), __BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
2335
CLKGATE_CON(0, 65), __BIT(5),
sys/arch/arm/rockchip/rk3588_cru.c
2350
CLKGATE_CON(0, 60), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
2364
CLKGATE_CON(0, 65), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
2378
CLKGATE_CON(0, 62), __BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
2392
CLKGATE_CON(0, 62), __BIT(13),
sys/arch/arm/rockchip/rk3588_cru.c
2406
CLKGATE_CON(0, 63), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
2423
CLKGATE_CON(0, 63), __BIT(5),
sys/arch/arm/rockchip/rk3588_cru.c
2436
CLKGATE_CON(0, 63), __BIT(9),
sys/arch/arm/rockchip/rk3588_cru.c
2449
CLKGATE_CON(0, 63), __BIT(13),
sys/arch/arm/rockchip/rk3588_cru.c
2454
CLKGATE_CON(0, 63), __BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
2459
CLKGATE_CON(0, 64), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
2480
CLKGATE_CON(0, 52), __BIT(10),
sys/arch/arm/rockchip/rk3588_cru.c
2485
CLKGATE_CON(0, 52), __BIT(11),
sys/arch/arm/rockchip/rk3588_cru.c
2490
CLKGATE_CON(0, 52), __BIT(12),
sys/arch/arm/rockchip/rk3588_cru.c
2495
CLKGATE_CON(0, 52), __BIT(13),
sys/arch/arm/rockchip/rk3588_cru.c
2500
CLKGATE_CON(0, 53), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
2505
CLKGATE_CON(0, 53), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
2510
CLKGATE_CON(0, 53), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
2519
CLKGATE_CON(0, 53), __BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
2524
CLKGATE_CON(0, 53), __BIT(7),
sys/arch/arm/rockchip/rk3588_cru.c
2548
CLKGATE_CON(0, 77), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
2553
CLKGATE_CON(0, 77), __BIT(4),
sys/arch/arm/rockchip/rk3588_cru.c
2558
CLKGATE_CON(0, 77), __BIT(5),
sys/arch/arm/rockchip/rk3588_cru.c
2572
CLKGATE_CON(PMU, 0), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
2577
CLKGATE_CON(PMU, 0), __BIT(4),
sys/arch/arm/rockchip/rk3588_cru.c
2582
CLKGATE_CON(PMU, 0), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
2587
CLKGATE_CON(PMU, 0), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
2592
CLKGATE_CON(PMU, 0), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
2597
CLKGATE_CON(PMU, 0), __BIT(5),
sys/arch/arm/rockchip/rk3588_cru.c
2602
CLKGATE_CON(PMU, 0), __BIT(7),
sys/arch/arm/rockchip/rk3588_cru.c
2609
CLKGATE_CON(PMU, 0), __BIT(8),
sys/arch/arm/rockchip/rk3588_cru.c
2622
CLKGATE_CON(PMU, 5), __BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
2629
CLKGATE_CON(PMU, 2), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
2636
CLKGATE_CON(PMU, 2), __BIT(8),
sys/arch/arm/rockchip/rk3588_cru.c
2650
CLKGATE_CON(PMU, 2), __BIT(11),
sys/arch/arm/rockchip/rk3588_cru.c
2675
CLKGATE_CON(PMU, 2), __BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
2685
CLKGATE_CON(PMU, 0), __BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
2694
CLKGATE_CON(PMU, 1), __BIT(13),
sys/arch/arm/rockchip/rk3588_cru.c
2703
CLKGATE_CON(PMU, 1), __BIT(9),
sys/arch/arm/rockchip/rk3588_cru.c
2711
CLKGATE_CON(PMU, 2), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
2728
CLKGATE_CON(PMU, 1), __BIT(7),
sys/arch/arm/rockchip/rk3588_cru.c
2733
CLKGATE_CON(PMU, 4), __BIT(11),
sys/arch/arm/rockchip/rk3588_cru.c
2738
CLKGATE_CON(PMU, 4), __BIT(7),
sys/arch/arm/rockchip/rk3588_cru.c
2743
CLKGATE_CON(PMU, 4), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
565
__BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
566
__BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
571
__BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
572
__BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
578
__BIT(14),
sys/arch/arm/rockchip/rk3588_cru.c
579
__BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
584
__BIT(4),
sys/arch/arm/rockchip/rk3588_cru.c
585
__BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
590
__BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
591
__BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
596
__BIT(8),
sys/arch/arm/rockchip/rk3588_cru.c
597
__BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
602
__BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
603
__BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
608
__BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
609
__BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
614
__BIT(10),
sys/arch/arm/rockchip/rk3588_cru.c
615
__BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
651
CLKGATE_CON(BIGCORE0, 0), __BIT(14),
sys/arch/arm/rockchip/rk3588_cru.c
66
#define RK3588_CLK_DSU_SEL_DF_MASK __BIT(15)
sys/arch/arm/rockchip/rk3588_cru.c
665
CLKGATE_CON(BIGCORE1, 0), __BIT(14),
sys/arch/arm/rockchip/rk3588_cru.c
679
CLKGATE_CON(0, 0), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
684
CLKGATE_CON(0, 0), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
689
CLKGATE_CON(0, 0), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
694
CLKGATE_CON(0, 0), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
699
CLKGATE_CON(0, 0), __BIT(4),
sys/arch/arm/rockchip/rk3588_cru.c
704
CLKGATE_CON(0, 0), __BIT(5),
sys/arch/arm/rockchip/rk3588_cru.c
709
CLKGATE_CON(0, 0), __BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
714
CLKGATE_CON(0, 0), __BIT(7),
sys/arch/arm/rockchip/rk3588_cru.c
720
CLKGATE_CON(0, 0), __BIT(8),
sys/arch/arm/rockchip/rk3588_cru.c
725
CLKGATE_CON(0, 0), __BIT(9),
sys/arch/arm/rockchip/rk3588_cru.c
730
CLKGATE_CON(0, 0), __BIT(10),
sys/arch/arm/rockchip/rk3588_cru.c
735
CLKGATE_CON(0, 0), __BIT(11),
sys/arch/arm/rockchip/rk3588_cru.c
740
CLKGATE_CON(0, 0), __BIT(12),
sys/arch/arm/rockchip/rk3588_cru.c
745
CLKGATE_CON(0, 0), __BIT(13),
sys/arch/arm/rockchip/rk3588_cru.c
751
CLKGATE_CON(0, 0), __BIT(14),
sys/arch/arm/rockchip/rk3588_cru.c
756
CLKGATE_CON(0, 0), __BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
761
CLKGATE_CON(0, 1), __BIT(10),
sys/arch/arm/rockchip/rk3588_cru.c
766
CLKGATE_CON(0, 1), __BIT(11),
sys/arch/arm/rockchip/rk3588_cru.c
771
CLKGATE_CON(0, 1), __BIT(12),
sys/arch/arm/rockchip/rk3588_cru.c
776
CLKGATE_CON(0, 1), __BIT(13),
sys/arch/arm/rockchip/rk3588_cru.c
781
CLKGATE_CON(0, 1), __BIT(14),
sys/arch/arm/rockchip/rk3588_cru.c
786
CLKGATE_CON(0, 1), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
791
CLKGATE_CON(0, 1), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
796
CLKGATE_CON(0, 1), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
801
CLKGATE_CON(0, 5), __BIT(9),
sys/arch/arm/rockchip/rk3588_cru.c
806
CLKGATE_CON(0, 5), __BIT(10),
sys/arch/arm/rockchip/rk3588_cru.c
811
CLKGATE_CON(0, 5), __BIT(11),
sys/arch/arm/rockchip/rk3588_cru.c
816
CLKGATE_CON(0, 5), __BIT(12),
sys/arch/arm/rockchip/rk3588_cru.c
821
CLKGATE_CON(0, 5), __BIT(13),
sys/arch/arm/rockchip/rk3588_cru.c
826
CLKGATE_CON(0, 5), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
831
CLKGATE_CON(0, 5), __BIT(4),
sys/arch/arm/rockchip/rk3588_cru.c
836
CLKGATE_CON(0, 5), __BIT(5),
sys/arch/arm/rockchip/rk3588_cru.c
841
CLKGATE_CON(0, 5), __BIT(6),
sys/arch/arm/rockchip/rk3588_cru.c
856
CLKGATE_CON(DSU, 0), __BIT(4),
sys/arch/arm/rockchip/rk3588_cru.c
860
CLKGATE_CON(DSU, 1), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
864
CLKGATE_CON(DSU, 1), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
868
CLKGATE_CON(DSU, 0), __BIT(12),
sys/arch/arm/rockchip/rk3588_cru.c
872
CLKGATE_CON(DSU, 0), __BIT(8),
sys/arch/arm/rockchip/rk3588_cru.c
876
CLKGATE_CON(DSU, 0), __BIT(9),
sys/arch/arm/rockchip/rk3588_cru.c
880
CLKGATE_CON(DSU, 0), __BIT(13),
sys/arch/arm/rockchip/rk3588_cru.c
884
CLKGATE_CON(DSU, 0), __BIT(14),
sys/arch/arm/rockchip/rk3588_cru.c
888
CLKGATE_CON(DSU, 0), __BIT(15),
sys/arch/arm/rockchip/rk3588_cru.c
893
CLKGATE_CON(DSU, 2), __BIT(2),
sys/arch/arm/rockchip/rk3588_cru.c
898
CLKGATE_CON(DSU, 1), __BIT(3),
sys/arch/arm/rockchip/rk3588_cru.c
903
CLKGATE_CON(DSU, 1), __BIT(4),
sys/arch/arm/rockchip/rk3588_cru.c
924
CLKGATE_CON(0, 7), __BIT(0),
sys/arch/arm/rockchip/rk3588_cru.c
929
CLKGATE_CON(0, 7), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
938
CLKGATE_CON(0, 7), __BIT(14),
sys/arch/arm/rockchip/rk3588_cru.c
954
CLKGATE_CON(0, 8), __BIT(1),
sys/arch/arm/rockchip/rk3588_cru.c
976
CLKGATE_CON(0, 7), __BIT(5),
sys/arch/arm/rockchip/rk3588_cru.c
990
CLKGATE_CON(0, 7), __BIT(8),
sys/arch/arm/rockchip/rk3588_iomux.c
465
{ RK3588_PMU1_IOC_REG + 0x0030, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
466
{ RK3588_PMU1_IOC_REG + 0x0030, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
467
{ RK3588_PMU1_IOC_REG + 0x0030, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
468
{ RK3588_PMU1_IOC_REG + 0x0030, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
469
{ RK3588_PMU1_IOC_REG + 0x0030, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
470
{ RK3588_PMU1_IOC_REG + 0x0030, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
471
{ RK3588_PMU1_IOC_REG + 0x0030, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
472
{ RK3588_PMU1_IOC_REG + 0x0030, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
474
{ RK3588_PMU1_IOC_REG + 0x0034, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
475
{ RK3588_PMU1_IOC_REG + 0x0034, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
476
{ RK3588_PMU1_IOC_REG + 0x0034, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
477
{ RK3588_PMU1_IOC_REG + 0x0034, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
478
{ RK3588_PMU1_IOC_REG + 0x0034, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
479
{ RK3588_PMU2_IOC_REG + 0x0040, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
480
{ RK3588_PMU2_IOC_REG + 0x0040, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
481
{ RK3588_PMU2_IOC_REG + 0x0040, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
483
{ RK3588_PMU2_IOC_REG + 0x0044, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
484
{ RK3588_PMU2_IOC_REG + 0x0044, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
485
{ RK3588_PMU2_IOC_REG + 0x0044, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
486
{ RK3588_PMU2_IOC_REG + 0x0044, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
487
{ RK3588_PMU2_IOC_REG + 0x0044, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
488
{ RK3588_PMU2_IOC_REG + 0x0044, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
489
{ RK3588_PMU2_IOC_REG + 0x0044, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
490
{ RK3588_PMU2_IOC_REG + 0x0044, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
492
{ RK3588_PMU2_IOC_REG + 0x0048, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
493
{ RK3588_PMU2_IOC_REG + 0x0048, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
494
{ RK3588_PMU2_IOC_REG + 0x0048, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
495
{ RK3588_PMU2_IOC_REG + 0x0048, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
496
{ RK3588_PMU2_IOC_REG + 0x0048, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
497
{ RK3588_PMU2_IOC_REG + 0x0048, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
498
{ RK3588_PMU2_IOC_REG + 0x0048, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
499
{ RK3588_PMU2_IOC_REG + 0x0048, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
502
{ RK3588_VCCIO1_4_IOC_REG + 0x0210, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
503
{ RK3588_VCCIO1_4_IOC_REG + 0x0210, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
504
{ RK3588_VCCIO1_4_IOC_REG + 0x0210, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
505
{ RK3588_VCCIO1_4_IOC_REG + 0x0210, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
506
{ RK3588_VCCIO1_4_IOC_REG + 0x0210, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
507
{ RK3588_VCCIO1_4_IOC_REG + 0x0210, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
508
{ RK3588_VCCIO1_4_IOC_REG + 0x0210, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
509
{ RK3588_VCCIO1_4_IOC_REG + 0x0210, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
511
{ RK3588_VCCIO1_4_IOC_REG + 0x0214, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
512
{ RK3588_VCCIO1_4_IOC_REG + 0x0214, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
513
{ RK3588_VCCIO1_4_IOC_REG + 0x0214, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
514
{ RK3588_VCCIO1_4_IOC_REG + 0x0214, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
515
{ RK3588_VCCIO1_4_IOC_REG + 0x0214, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
516
{ RK3588_VCCIO1_4_IOC_REG + 0x0214, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
517
{ RK3588_VCCIO1_4_IOC_REG + 0x0214, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
518
{ RK3588_VCCIO1_4_IOC_REG + 0x0214, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
520
{ RK3588_VCCIO1_4_IOC_REG + 0x0218, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
521
{ RK3588_VCCIO1_4_IOC_REG + 0x0218, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
522
{ RK3588_VCCIO1_4_IOC_REG + 0x0218, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
523
{ RK3588_VCCIO1_4_IOC_REG + 0x0218, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
524
{ RK3588_VCCIO1_4_IOC_REG + 0x0218, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
525
{ RK3588_VCCIO1_4_IOC_REG + 0x0218, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
526
{ RK3588_VCCIO1_4_IOC_REG + 0x0218, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
527
{ RK3588_VCCIO1_4_IOC_REG + 0x0218, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
529
{ RK3588_VCCIO1_4_IOC_REG + 0x021c, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
530
{ RK3588_VCCIO1_4_IOC_REG + 0x021c, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
531
{ RK3588_VCCIO1_4_IOC_REG + 0x021c, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
532
{ RK3588_VCCIO1_4_IOC_REG + 0x021c, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
533
{ RK3588_VCCIO1_4_IOC_REG + 0x021c, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
534
{ RK3588_VCCIO1_4_IOC_REG + 0x021c, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
535
{ RK3588_VCCIO1_4_IOC_REG + 0x021c, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
536
{ RK3588_VCCIO1_4_IOC_REG + 0x021c, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
539
{ RK3588_EMMC_IOC_REG + 0x0220, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
540
{ RK3588_EMMC_IOC_REG + 0x0220, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
541
{ RK3588_EMMC_IOC_REG + 0x0220, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
542
{ RK3588_EMMC_IOC_REG + 0x0220, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
543
{ RK3588_EMMC_IOC_REG + 0x0220, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
544
{ RK3588_EMMC_IOC_REG + 0x0220, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
545
{ RK3588_VCCIO3_5_IOC_REG + 0x0220, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
546
{ RK3588_VCCIO3_5_IOC_REG + 0x0220, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
548
{ RK3588_VCCIO3_5_IOC_REG + 0x0224, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
549
{ RK3588_VCCIO3_5_IOC_REG + 0x0224, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
550
{ RK3588_VCCIO3_5_IOC_REG + 0x0224, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
551
{ RK3588_VCCIO3_5_IOC_REG + 0x0224, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
552
{ RK3588_VCCIO3_5_IOC_REG + 0x0224, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
553
{ RK3588_VCCIO3_5_IOC_REG + 0x0224, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
554
{ RK3588_VCCIO3_5_IOC_REG + 0x0224, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
555
{ RK3588_VCCIO3_5_IOC_REG + 0x0224, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
557
{ RK3588_VCCIO3_5_IOC_REG + 0x0228, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
558
{ RK3588_VCCIO3_5_IOC_REG + 0x0228, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
559
{ RK3588_VCCIO3_5_IOC_REG + 0x0228, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
560
{ RK3588_VCCIO3_5_IOC_REG + 0x0228, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
561
{ RK3588_VCCIO3_5_IOC_REG + 0x0228, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
562
{ RK3588_VCCIO3_5_IOC_REG + 0x0228, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
563
{ RK3588_VCCIO3_5_IOC_REG + 0x0228, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
564
{ RK3588_VCCIO3_5_IOC_REG + 0x0228, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
566
{ RK3588_EMMC_IOC_REG + 0x022c, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
567
{ RK3588_EMMC_IOC_REG + 0x022c, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
568
{ RK3588_EMMC_IOC_REG + 0x022c, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
569
{ RK3588_EMMC_IOC_REG + 0x022c, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
570
{ RK3588_EMMC_IOC_REG + 0x022c, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
571
{ RK3588_EMMC_IOC_REG + 0x022c, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
572
{ RK3588_EMMC_IOC_REG + 0x022c, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
573
{ RK3588_EMMC_IOC_REG + 0x022c, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
576
{ RK3588_VCCIO3_5_IOC_REG + 0x0230, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
577
{ RK3588_VCCIO3_5_IOC_REG + 0x0230, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
578
{ RK3588_VCCIO3_5_IOC_REG + 0x0230, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
579
{ RK3588_VCCIO3_5_IOC_REG + 0x0230, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
580
{ RK3588_VCCIO3_5_IOC_REG + 0x0230, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
581
{ RK3588_VCCIO3_5_IOC_REG + 0x0230, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
582
{ RK3588_VCCIO3_5_IOC_REG + 0x0230, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
583
{ RK3588_VCCIO3_5_IOC_REG + 0x0230, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
585
{ RK3588_VCCIO3_5_IOC_REG + 0x0234, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
586
{ RK3588_VCCIO3_5_IOC_REG + 0x0234, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
587
{ RK3588_VCCIO3_5_IOC_REG + 0x0234, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
588
{ RK3588_VCCIO3_5_IOC_REG + 0x0234, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
589
{ RK3588_VCCIO3_5_IOC_REG + 0x0234, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
590
{ RK3588_VCCIO3_5_IOC_REG + 0x0234, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
591
{ RK3588_VCCIO3_5_IOC_REG + 0x0234, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
592
{ RK3588_VCCIO3_5_IOC_REG + 0x0234, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
594
{ RK3588_VCCIO3_5_IOC_REG + 0x0238, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
595
{ RK3588_VCCIO3_5_IOC_REG + 0x0238, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
596
{ RK3588_VCCIO3_5_IOC_REG + 0x0238, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
597
{ RK3588_VCCIO3_5_IOC_REG + 0x0238, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
598
{ RK3588_VCCIO3_5_IOC_REG + 0x0238, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
599
{ RK3588_VCCIO3_5_IOC_REG + 0x0238, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
600
{ RK3588_VCCIO3_5_IOC_REG + 0x0238, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
601
{ RK3588_VCCIO3_5_IOC_REG + 0x0238, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
603
{ RK3588_VCCIO3_5_IOC_REG + 0x023c, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
604
{ RK3588_VCCIO3_5_IOC_REG + 0x023c, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
605
{ RK3588_VCCIO3_5_IOC_REG + 0x023c, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
606
{ RK3588_VCCIO3_5_IOC_REG + 0x023c, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
607
{ RK3588_VCCIO3_5_IOC_REG + 0x023c, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
608
{ RK3588_VCCIO3_5_IOC_REG + 0x023c, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
609
{ RK3588_VCCIO3_5_IOC_REG + 0x023c, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
610
{ RK3588_VCCIO3_5_IOC_REG + 0x023c, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
613
{ RK3588_VCCIO6_IOC_REG + 0x0240, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
614
{ RK3588_VCCIO6_IOC_REG + 0x0240, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
615
{ RK3588_VCCIO6_IOC_REG + 0x0240, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
616
{ RK3588_VCCIO6_IOC_REG + 0x0240, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
617
{ RK3588_VCCIO6_IOC_REG + 0x0240, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
618
{ RK3588_VCCIO6_IOC_REG + 0x0240, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
619
{ RK3588_VCCIO6_IOC_REG + 0x0240, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
620
{ RK3588_VCCIO6_IOC_REG + 0x0240, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
622
{ RK3588_VCCIO6_IOC_REG + 0x0244, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
623
{ RK3588_VCCIO6_IOC_REG + 0x0244, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
624
{ RK3588_VCCIO6_IOC_REG + 0x0244, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
625
{ RK3588_VCCIO6_IOC_REG + 0x0244, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
626
{ RK3588_VCCIO6_IOC_REG + 0x0244, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
627
{ RK3588_VCCIO6_IOC_REG + 0x0244, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
628
{ RK3588_VCCIO6_IOC_REG + 0x0244, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
629
{ RK3588_VCCIO6_IOC_REG + 0x0244, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
631
{ RK3588_VCCIO6_IOC_REG + 0x0248, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
632
{ RK3588_VCCIO6_IOC_REG + 0x0248, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
633
{ RK3588_VCCIO3_5_IOC_REG + 0x0248, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
634
{ RK3588_VCCIO3_5_IOC_REG + 0x0248, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
635
{ RK3588_VCCIO3_5_IOC_REG + 0x0248, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
636
{ RK3588_VCCIO3_5_IOC_REG + 0x0248, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
637
{ RK3588_VCCIO3_5_IOC_REG + 0x0248, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
638
{ RK3588_VCCIO3_5_IOC_REG + 0x0248, __BIT(7) },
sys/arch/arm/rockchip/rk3588_iomux.c
640
{ RK3588_VCCIO2_IOC_REG + 0x024c, __BIT(0) },
sys/arch/arm/rockchip/rk3588_iomux.c
641
{ RK3588_VCCIO2_IOC_REG + 0x024c, __BIT(1) },
sys/arch/arm/rockchip/rk3588_iomux.c
642
{ RK3588_VCCIO2_IOC_REG + 0x024c, __BIT(2) },
sys/arch/arm/rockchip/rk3588_iomux.c
643
{ RK3588_VCCIO2_IOC_REG + 0x024c, __BIT(3) },
sys/arch/arm/rockchip/rk3588_iomux.c
644
{ RK3588_VCCIO2_IOC_REG + 0x024c, __BIT(4) },
sys/arch/arm/rockchip/rk3588_iomux.c
645
{ RK3588_VCCIO2_IOC_REG + 0x024c, __BIT(5) },
sys/arch/arm/rockchip/rk3588_iomux.c
646
{ RK3588_VCCIO2_IOC_REG + 0x024c, __BIT(6) },
sys/arch/arm/rockchip/rk3588_iomux.c
647
{ RK3588_VCCIO2_IOC_REG + 0x024c, __BIT(7) }
sys/arch/arm/rockchip/rk3588_iomux.c
914
val = (mask << 16) | __SHIFTIN(__BIT(3), mask);
sys/arch/arm/rockchip/rk_anxdp.c
50
#define EDP_LCDC_SEL __BIT(5)
sys/arch/arm/rockchip/rk_cru.h
363
.u.gate.mask = __BIT(_bit), \
sys/arch/arm/rockchip/rk_cru_pll.c
40
#define PLL_BYPASS __BIT(15)
sys/arch/arm/rockchip/rk_cru_pll.c
45
#define PLL_PDSEL __BIT(15)
sys/arch/arm/rockchip/rk_cru_pll.c
46
#define PLL_PD1 __BIT(14)
sys/arch/arm/rockchip/rk_cru_pll.c
47
#define PLL_PD0 __BIT(13)
sys/arch/arm/rockchip/rk_cru_pll.c
48
#define PLL_DSMPD __BIT(12)
sys/arch/arm/rockchip/rk_cru_pll.c
49
#define PLL_LOCK __BIT(10)
sys/arch/arm/rockchip/rk_cru_pll.c
54
#define PLL_FOUT4PHASEPD __BIT(27)
sys/arch/arm/rockchip/rk_cru_pll.c
55
#define PLL_FOUTVCOPD __BIT(26)
sys/arch/arm/rockchip/rk_cru_pll.c
56
#define PLL_FOUTPOSTDIVPD __BIT(25)
sys/arch/arm/rockchip/rk_cru_pll.c
57
#define PLL_DACPD __BIT(24)
sys/arch/arm/rockchip/rk_cru_pll.c
69
#define RK3288_LOCK __BIT(31)
sys/arch/arm/rockchip/rk_cru_pll.c
74
#define RK3288_BYPASS __BIT(0)
sys/arch/arm/rockchip/rk_cru_pll.c
80
#define RK3588_PLLCON1_PWRDOWN __BIT(13)
sys/arch/arm/rockchip/rk_cru_pll.c
81
#define RK3588_PLLCON6_LOCK __BIT(15)
sys/arch/arm/rockchip/rk_dwhdmi.c
50
#define HDMI_LCDC_SEL __BIT(6)
sys/arch/arm/rockchip/rk_emmcphy.c
49
#define PHYCTRL_OTAPDLYENA __BIT(11)
sys/arch/arm/rockchip/rk_emmcphy.c
51
#define PHYCTRL_ITAPCHGWIN __BIT(6)
sys/arch/arm/rockchip/rk_emmcphy.c
53
#define PHYCTRL_ITAPDLYENA __BIT(0)
sys/arch/arm/rockchip/rk_emmcphy.c
56
#define PHYCTRL_SELDLYTXCLK __BIT(5)
sys/arch/arm/rockchip/rk_emmcphy.c
57
#define PHYCTRL_SELDLYRXCLK __BIT(4)
sys/arch/arm/rockchip/rk_emmcphy.c
60
#define PHYCTRL_REN_STRB __BIT(9)
sys/arch/arm/rockchip/rk_emmcphy.c
61
#define PHYCTRL_REN_CMD __BIT(8)
sys/arch/arm/rockchip/rk_emmcphy.c
64
#define PHYCTRL_PU_STRB __BIT(9)
sys/arch/arm/rockchip/rk_emmcphy.c
65
#define PHYCTRL_PU_CMD __BIT(8)
sys/arch/arm/rockchip/rk_emmcphy.c
68
#define PHYCTRL_OD_RELEASE_CMD __BIT(9)
sys/arch/arm/rockchip/rk_emmcphy.c
69
#define PHYCTRL_OD_RELEASE_STRB __BIT(8)
sys/arch/arm/rockchip/rk_emmcphy.c
72
#define PHYCTRL_ODEN_STRB __BIT(9)
sys/arch/arm/rockchip/rk_emmcphy.c
73
#define PHYCTRL_ODEN_CMD __BIT(8)
sys/arch/arm/rockchip/rk_emmcphy.c
77
#define PHYCTRL_EN_RTRIM __BIT(8)
sys/arch/arm/rockchip/rk_emmcphy.c
78
#define PHYCTRL_RETRIM __BIT(7)
sys/arch/arm/rockchip/rk_emmcphy.c
80
#define PHYCTRL_RETENB __BIT(3)
sys/arch/arm/rockchip/rk_emmcphy.c
81
#define PHYCTRL_RETEN __BIT(2)
sys/arch/arm/rockchip/rk_emmcphy.c
82
#define PHYCTRL_ENDLL __BIT(1)
sys/arch/arm/rockchip/rk_emmcphy.c
83
#define PHYCTRL_PDB __BIT(0)
sys/arch/arm/rockchip/rk_emmcphy.c
85
#define PHYCTRL_CALDONE __BIT(6)
sys/arch/arm/rockchip/rk_emmcphy.c
86
#define PHYCTRL_DLLRDY __BIT(5)
sys/arch/arm/rockchip/rk_emmcphy.c
88
#define PHYCTRL_EXR_NINST __BIT(0)
sys/arch/arm/rockchip/rk_eqos.c
101
#define RK3588_GMAC_CLK_RMII_GATE_EN(id) __BIT(1 + (id) * 5)
sys/arch/arm/rockchip/rk_eqos.c
104
#define RK3588_GMAC_CLK_MODE(id) __BIT(0 + (id) * 5)
sys/arch/arm/rockchip/rk_eqos.c
74
#define RK3588_GMAC_RXCLK_DELAY_EN(id) __BIT(3 + 2 * (id))
sys/arch/arm/rockchip/rk_eqos.c
77
#define RK3588_GMAC_TXCLK_DELAY_EN(id) __BIT(2 + 2 * (id))
sys/arch/arm/rockchip/rk_eqos.c
91
#define RK3588_GMAC_CLK_SELECT(id) __BIT(4 + 5 * (id))
sys/arch/arm/rockchip/rk_eqos.c
94
#define RK3588_GMAC_CLK_RMII_DIV(id) __BIT(2 + 5 * (id))
sys/arch/arm/rockchip/rk_gmac.c
181
#define RK3328_GRF_MAC_CON1_MODE __BIT(9)
sys/arch/arm/rockchip/rk_gmac.c
184
#define RK3328_GRF_MAC_CON1_RXDLY_EN __BIT(1)
sys/arch/arm/rockchip/rk_gmac.c
185
#define RK3328_GRF_MAC_CON1_TXDLY_EN __BIT(0)
sys/arch/arm/rockchip/rk_gmac.c
257
#define RK3399_GRF_SOC_CON5_GMAC_FLOWCTRL __BIT(8)
sys/arch/arm/rockchip/rk_gmac.c
258
#define RK3399_GRF_SOC_CON5_GMAC_SPEED __BIT(7)
sys/arch/arm/rockchip/rk_gmac.c
259
#define RK3399_GRF_SOC_CON5_RMII_MODE __BIT(6)
sys/arch/arm/rockchip/rk_gmac.c
264
#define RK3399_GRF_SOC_CON5_RMII_CLK_SEL __BIT(3)
sys/arch/arm/rockchip/rk_gmac.c
266
#define RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA __BIT(15)
sys/arch/arm/rockchip/rk_gmac.c
268
#define RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA __BIT(7)
sys/arch/arm/rockchip/rk_gmac.c
81
#define RK3288_GRF_SOC_CON1_RMII_MODE __BIT(14)
sys/arch/arm/rockchip/rk_gmac.c
86
#define RK3288_GRF_SOC_CON1_RMII_CLK_SEL __BIT(11)
sys/arch/arm/rockchip/rk_gmac.c
89
#define RK3288_GRF_SOC_CON1_GMAC_SPEED __BIT(10)
sys/arch/arm/rockchip/rk_gmac.c
92
#define RK3288_GRF_SOC_CON1_GMAC_FLOWCTRL __BIT(9)
sys/arch/arm/rockchip/rk_gmac.c
98
#define RK3288_GRF_SOC_CON3_RXCLK_DLY_ENA_GMAC __BIT(15)
sys/arch/arm/rockchip/rk_gmac.c
99
#define RK3288_GRF_SOC_CON3_TXCLK_DLY_ENA_GMAC __BIT(14)
sys/arch/arm/rockchip/rk_gpio.c
209
const uint32_t data_mask = __BIT(pin);
sys/arch/arm/rockchip/rk_gpio.c
226
const uint32_t data_mask = __BIT(pin);
sys/arch/arm/rockchip/rk_gpio.c
249
ddr &= ~__BIT(pin);
sys/arch/arm/rockchip/rk_gpio.c
251
ddr |= __BIT(pin);
sys/arch/arm/rockchip/rk_gpio.c
265
const uint32_t data_mask = __BIT(pin);
sys/arch/arm/rockchip/rk_gpio.c
317
status &= ~__BIT(bit - 1);
sys/arch/arm/rockchip/rk_gpio.c
380
val |= __BIT(eint->eint_num);
sys/arch/arm/rockchip/rk_gpio.c
399
val &= ~__BIT(eint->eint_num);
sys/arch/arm/rockchip/rk_gpio.c
401
WR4(sc, GPIO_INT_STATUS_REG, __BIT(eint->eint_num));
sys/arch/arm/rockchip/rk_gpio.c
76
#define GPIOV2_DATA_MASK(pin) (__BIT((pin) & 0xF))
sys/arch/arm/rockchip/rk_gpio.c
77
#define GPIOV2_WRITE_MASK(pin) (__BIT(((pin) & 0xF) | 0x10))
sys/arch/arm/rockchip/rk_i2c.c
104
#define RKI2C_HAS_PCLK __BIT(0)
sys/arch/arm/rockchip/rk_i2c.c
46
#define RKI2C_CON_ACT2NAK __BIT(6)
sys/arch/arm/rockchip/rk_i2c.c
47
#define RKI2C_CON_ACK __BIT(5)
sys/arch/arm/rockchip/rk_i2c.c
48
#define RKI2C_CON_STOP __BIT(4)
sys/arch/arm/rockchip/rk_i2c.c
49
#define RKI2C_CON_START __BIT(3)
sys/arch/arm/rockchip/rk_i2c.c
55
#define RKI2C_CON_I2C_EN __BIT(0)
sys/arch/arm/rockchip/rk_i2c.c
62
#define RKI2C_MRXADDR_ADDHVLD __BIT(26)
sys/arch/arm/rockchip/rk_i2c.c
63
#define RKI2C_MRXADDR_ADDMVLD __BIT(25)
sys/arch/arm/rockchip/rk_i2c.c
64
#define RKI2C_MRXADDR_ADDLVLD __BIT(24)
sys/arch/arm/rockchip/rk_i2c.c
68
#define RKI2C_MRXRADDR_ADDHVLD __BIT(26)
sys/arch/arm/rockchip/rk_i2c.c
69
#define RKI2C_MRXRADDR_ADDMVLD __BIT(25)
sys/arch/arm/rockchip/rk_i2c.c
70
#define RKI2C_MRXRADDR_ADDLVLD __BIT(24)
sys/arch/arm/rockchip/rk_i2c.c
80
#define RKI2C_IEN_NAKRCVIEN __BIT(6)
sys/arch/arm/rockchip/rk_i2c.c
81
#define RKI2C_IEN_STOPIEN __BIT(5)
sys/arch/arm/rockchip/rk_i2c.c
82
#define RKI2C_IEN_STARTIEN __BIT(4)
sys/arch/arm/rockchip/rk_i2c.c
83
#define RKI2C_IEN_MBRFIEN __BIT(3)
sys/arch/arm/rockchip/rk_i2c.c
84
#define RKI2C_IEN_MBTFIEN __BIT(2)
sys/arch/arm/rockchip/rk_i2c.c
85
#define RKI2C_IEN_BRFIEN __BIT(1)
sys/arch/arm/rockchip/rk_i2c.c
86
#define RKI2C_IEN_BTFIEN __BIT(0)
sys/arch/arm/rockchip/rk_i2c.c
89
#define RKI2C_IPD_NAKRCVIPD __BIT(6)
sys/arch/arm/rockchip/rk_i2c.c
90
#define RKI2C_IPD_STOPIPD __BIT(5)
sys/arch/arm/rockchip/rk_i2c.c
91
#define RKI2C_IPD_STARTIPD __BIT(4)
sys/arch/arm/rockchip/rk_i2c.c
92
#define RKI2C_IPD_MBRFIPD __BIT(3)
sys/arch/arm/rockchip/rk_i2c.c
93
#define RKI2C_IPD_MBTFIPD __BIT(2)
sys/arch/arm/rockchip/rk_i2c.c
94
#define RKI2C_IPD_BRFIPD __BIT(1)
sys/arch/arm/rockchip/rk_i2c.c
95
#define RKI2C_IPD_BTFIPD __BIT(0)
sys/arch/arm/rockchip/rk_i2s.c
101
#define CLR_RXC __BIT(1)
sys/arch/arm/rockchip/rk_i2s.c
102
#define CLR_TXC __BIT(0)
sys/arch/arm/rockchip/rk_i2s.c
51
#define TXCR_HWT __BIT(14)
sys/arch/arm/rockchip/rk_i2s.c
52
#define TXCR_SJM __BIT(12)
sys/arch/arm/rockchip/rk_i2s.c
53
#define TXCR_FBM __BIT(11)
sys/arch/arm/rockchip/rk_i2s.c
56
#define TXCR_TFS __BIT(5)
sys/arch/arm/rockchip/rk_i2s.c
60
#define RXCR_HWT __BIT(14)
sys/arch/arm/rockchip/rk_i2s.c
61
#define RXCR_SJM __BIT(12)
sys/arch/arm/rockchip/rk_i2s.c
62
#define RXCR_FBM __BIT(11)
sys/arch/arm/rockchip/rk_i2s.c
65
#define RXCR_TFS __BIT(5)
sys/arch/arm/rockchip/rk_i2s.c
69
#define CKR_MSS __BIT(27)
sys/arch/arm/rockchip/rk_i2s.c
70
#define CKR_CKP __BIT(26)
sys/arch/arm/rockchip/rk_i2s.c
71
#define CKR_RLP __BIT(25)
sys/arch/arm/rockchip/rk_i2s.c
72
#define CKR_TLP __BIT(24)
sys/arch/arm/rockchip/rk_i2s.c
79
#define DMACR_RDE __BIT(24)
sys/arch/arm/rockchip/rk_i2s.c
81
#define DMACR_TDE __BIT(8)
sys/arch/arm/rockchip/rk_i2s.c
85
#define INTCR_RXOIC __BIT(18)
sys/arch/arm/rockchip/rk_i2s.c
86
#define INTCR_RXOIE __BIT(17)
sys/arch/arm/rockchip/rk_i2s.c
87
#define INTCR_RXFIE __BIT(16)
sys/arch/arm/rockchip/rk_i2s.c
89
#define INTCR_TXUIC __BIT(2)
sys/arch/arm/rockchip/rk_i2s.c
90
#define INTCR_TXUIE __BIT(1)
sys/arch/arm/rockchip/rk_i2s.c
91
#define INTCR_TXEIE __BIT(0)
sys/arch/arm/rockchip/rk_i2s.c
93
#define INTSR_RXOI __BIT(17)
sys/arch/arm/rockchip/rk_i2s.c
94
#define INTSR_RXFI __BIT(16)
sys/arch/arm/rockchip/rk_i2s.c
95
#define INTSR_TXUI __BIT(1)
sys/arch/arm/rockchip/rk_i2s.c
96
#define INTSR_TXEI __BIT(0)
sys/arch/arm/rockchip/rk_i2s.c
98
#define XFER_RXS __BIT(1)
sys/arch/arm/rockchip/rk_i2s.c
99
#define XFER_TXS __BIT(0)
sys/arch/arm/rockchip/rk_platform.c
111
#define RK3288_WDT_CR_WDT_EN __BIT(0)
sys/arch/arm/rockchip/rk_pwm.c
51
#define CTRL_CLK_SEL __BIT(9)
sys/arch/arm/rockchip/rk_pwm.c
52
#define CTRL_LP_EN __BIT(8)
sys/arch/arm/rockchip/rk_pwm.c
53
#define CTRL_OUTPUT_MODE __BIT(5)
sys/arch/arm/rockchip/rk_pwm.c
54
#define CTRL_INACTIVE_POL __BIT(4)
sys/arch/arm/rockchip/rk_pwm.c
55
#define CTRL_DUTY_POL __BIT(3)
sys/arch/arm/rockchip/rk_pwm.c
60
#define CTRL_PWM_EN __BIT(0)
sys/arch/arm/rockchip/rk_spi.c
101
#define SPI_IMR_RFFIM __BIT(4)
sys/arch/arm/rockchip/rk_spi.c
102
#define SPI_IMR_RFOIM __BIT(3)
sys/arch/arm/rockchip/rk_spi.c
103
#define SPI_IMR_RFUIM __BIT(2)
sys/arch/arm/rockchip/rk_spi.c
104
#define SPI_IMR_TFOIM __BIT(1)
sys/arch/arm/rockchip/rk_spi.c
105
#define SPI_IMR_TFEIM __BIT(0)
sys/arch/arm/rockchip/rk_spi.c
108
#define SPI_ISR_RFFIS __BIT(4)
sys/arch/arm/rockchip/rk_spi.c
109
#define SPI_ISR_RFOIS __BIT(3)
sys/arch/arm/rockchip/rk_spi.c
110
#define SPI_ISR_RFUIS __BIT(2)
sys/arch/arm/rockchip/rk_spi.c
111
#define SPI_ISR_TFOIS __BIT(1)
sys/arch/arm/rockchip/rk_spi.c
112
#define SPI_ISR_TFEIS __BIT(0)
sys/arch/arm/rockchip/rk_spi.c
115
#define SPI_RISR_RFFRIS __BIT(4)
sys/arch/arm/rockchip/rk_spi.c
116
#define SPI_RISR_RFORIS __BIT(3)
sys/arch/arm/rockchip/rk_spi.c
117
#define SPI_RISR_RFURIS __BIT(2)
sys/arch/arm/rockchip/rk_spi.c
118
#define SPI_RISR_TFORIS __BIT(1)
sys/arch/arm/rockchip/rk_spi.c
119
#define SPI_RISR_TFERIS __BIT(0)
sys/arch/arm/rockchip/rk_spi.c
122
#define SPI_ICR_CTFOI __BIT(3)
sys/arch/arm/rockchip/rk_spi.c
123
#define SPI_ICR_CRFOI __BIT(2)
sys/arch/arm/rockchip/rk_spi.c
124
#define SPI_ICR_CRFUI __BIT(1)
sys/arch/arm/rockchip/rk_spi.c
125
#define SPI_ICR_CCI __BIT(0)
sys/arch/arm/rockchip/rk_spi.c
129
#define SPI_DMACR_TDE __BIT(1)
sys/arch/arm/rockchip/rk_spi.c
130
#define SPI_DMACR_RDE __BIT(0)
sys/arch/arm/rockchip/rk_spi.c
47
#define SPI_CTRLR0_MTM __BIT(21)
sys/arch/arm/rockchip/rk_spi.c
48
#define SPI_CTRLR0_OPM __BIT(20)
sys/arch/arm/rockchip/rk_spi.c
52
#define SPI_CTRLR0_BHT __BIT(13)
sys/arch/arm/rockchip/rk_spi.c
53
#define SPI_CTRLR0_FBM __BIT(12)
sys/arch/arm/rockchip/rk_spi.c
54
#define SPI_CTRLR0_EM __BIT(11)
sys/arch/arm/rockchip/rk_spi.c
55
#define SPI_CTRLR0_RW __BIT(10)
sys/arch/arm/rockchip/rk_spi.c
57
#define SPI_CTRLR0_SCPOL __BIT(7)
sys/arch/arm/rockchip/rk_spi.c
58
#define SPI_CTRLR0_SCPH __BIT(6)
sys/arch/arm/rockchip/rk_spi.c
69
#define SPI_ENR_ENR __BIT(0)
sys/arch/arm/rockchip/rk_spi.c
72
#define SPI_SER_SER1 __BIT(1)
sys/arch/arm/rockchip/rk_spi.c
73
#define SPI_SER_SER0 __BIT(0)
sys/arch/arm/rockchip/rk_spi.c
91
#define SPI_SR_RFF __BIT(4)
sys/arch/arm/rockchip/rk_spi.c
92
#define SPI_SR_RFE __BIT(3)
sys/arch/arm/rockchip/rk_spi.c
93
#define SPI_SR_TFE __BIT(2)
sys/arch/arm/rockchip/rk_spi.c
94
#define SPI_SR_TFF __BIT(1)
sys/arch/arm/rockchip/rk_spi.c
95
#define SPI_SR_BSF __BIT(0)
sys/arch/arm/rockchip/rk_spi.c
98
#define SPI_IPR_IPR __BIT(0)
sys/arch/arm/rockchip/rk_tsadc.c
100
#define TSADC_INT_PD_HT_IRQ_SRC1 __BIT(1)
sys/arch/arm/rockchip/rk_tsadc.c
101
#define TSADC_INT_PD_HT_IRQ_SRC0 __BIT(0)
sys/arch/arm/rockchip/rk_tsadc.c
65
#define TSADC_USER_CON_ADC_STATUS __BIT(12)
sys/arch/arm/rockchip/rk_tsadc.c
67
#define TSADC_USER_CON_START __BIT(5)
sys/arch/arm/rockchip/rk_tsadc.c
68
#define TSADC_USER_CON_START_MODE __BIT(4)
sys/arch/arm/rockchip/rk_tsadc.c
69
#define TSADC_USER_CON_ADC_POWER_CTRL __BIT(3)
sys/arch/arm/rockchip/rk_tsadc.c
72
#define TSADC_AUTO_CON_LAST_TSHUT_2CRU __BIT(25)
sys/arch/arm/rockchip/rk_tsadc.c
73
#define TSADC_AUTO_CON_LAST_TSHUT_2GPIO __BIT(24)
sys/arch/arm/rockchip/rk_tsadc.c
74
#define TSADC_AUTO_CON_SAMPLE_DLY_SEL __BIT(17)
sys/arch/arm/rockchip/rk_tsadc.c
75
#define TSADC_AUTO_CON_AUTO_STATUS __BIT(16)
sys/arch/arm/rockchip/rk_tsadc.c
76
#define TSADC_AUTO_CON_SRC1_LT_EN __BIT(13)
sys/arch/arm/rockchip/rk_tsadc.c
77
#define TSADC_AUTO_CON_SRC0_LT_EN __BIT(12)
sys/arch/arm/rockchip/rk_tsadc.c
78
#define TSADC_AUTO_CON_TSHUT_POLARITY __BIT(8)
sys/arch/arm/rockchip/rk_tsadc.c
79
#define TSADC_AUTO_CON_SRC1_EN __BIT(5)
sys/arch/arm/rockchip/rk_tsadc.c
80
#define TSADC_AUTO_CON_SRC0_EN __BIT(4)
sys/arch/arm/rockchip/rk_tsadc.c
81
#define TSADC_AUTO_CON_Q_SEL __BIT(1)
sys/arch/arm/rockchip/rk_tsadc.c
82
#define TSADC_AUTO_CON_AUTO_EN __BIT(0)
sys/arch/arm/rockchip/rk_tsadc.c
84
#define TSADC_INT_EN_EOC_INT_EN __BIT(16)
sys/arch/arm/rockchip/rk_tsadc.c
85
#define TSADC_INT_EN_LT_INTEN_SRC1 __BIT(13)
sys/arch/arm/rockchip/rk_tsadc.c
86
#define TSADC_INT_EN_LT_INTEN_SRC0 __BIT(12)
sys/arch/arm/rockchip/rk_tsadc.c
87
#define TSADC_INT_EN_TSHUT_2CRU_EN_SRC1 __BIT(9)
sys/arch/arm/rockchip/rk_tsadc.c
88
#define TSADC_INT_EN_TSHUT_2CRU_EN_SRC0 __BIT(8)
sys/arch/arm/rockchip/rk_tsadc.c
89
#define TSADC_INT_EN_TSHUT_2GPIO_EN_SRC1 __BIT(5)
sys/arch/arm/rockchip/rk_tsadc.c
90
#define TSADC_INT_EN_TSHUT_2GPIO_EN_SRC0 __BIT(4)
sys/arch/arm/rockchip/rk_tsadc.c
91
#define TSADC_INT_EN_HT_INTEN_SRC1 __BIT(1)
sys/arch/arm/rockchip/rk_tsadc.c
92
#define TSADC_INT_EN_HT_INTEN_SRC0 __BIT(0)
sys/arch/arm/rockchip/rk_tsadc.c
94
#define TSADC_INT_PD_EOC_INT_PD_V3 __BIT(16)
sys/arch/arm/rockchip/rk_tsadc.c
95
#define TSADC_INT_PD_LT_IRQ_SRC1 __BIT(13)
sys/arch/arm/rockchip/rk_tsadc.c
96
#define TSADC_INT_PD_LT_IRQ_SRC0 __BIT(12)
sys/arch/arm/rockchip/rk_tsadc.c
97
#define TSADC_INT_PD_EOC_INT_PD_V2 __BIT(8)
sys/arch/arm/rockchip/rk_tsadc.c
98
#define TSADC_INT_PD_TSHUT_O_SRC1 __BIT(5)
sys/arch/arm/rockchip/rk_tsadc.c
99
#define TSADC_INT_PD_TSHUT_O_SRC0 __BIT(4)
sys/arch/arm/rockchip/rk_usb.c
52
#define RK3328_USBPHY_COMMONONN __BIT(4)
sys/arch/arm/rockchip/rk_usb.c
56
#define RK3399_USBPHY_COMMONONN __BIT(4)
sys/arch/arm/rockchip/rk_usb.c
61
#define RK3399_USBPHY_SUSPEND_N __BIT(1)
sys/arch/arm/rockchip/rk_usb.c
62
#define RK3399_USBPHY_UTMI_SEL __BIT(0)
sys/arch/arm/rockchip/rk_v1crypto.h
103
#define RK_V1CRYPTO_AES_CTRL_FIFOMODE __BIT(1)
sys/arch/arm/rockchip/rk_v1crypto.h
104
#define RK_V1CRYPTO_AES_CTRL_DIR __BIT(0)
sys/arch/arm/rockchip/rk_v1crypto.h
109
#define RK_V1CRYPTO_AES_STS_DONE __BIT(0)
sys/arch/arm/rockchip/rk_v1crypto.h
118
#define RK_V1CRYPTO_TDES_CTRL_BYTESWAP_KEY __BIT(8)
sys/arch/arm/rockchip/rk_v1crypto.h
119
#define RK_V1CRYPTO_TDES_CTRL_BYTESWAP_IV __BIT(7)
sys/arch/arm/rockchip/rk_v1crypto.h
120
#define RK_V1CRYPTO_TDES_CTRL_BYTESWAP_DO __BIT(6)
sys/arch/arm/rockchip/rk_v1crypto.h
121
#define RK_V1CRYPTO_TDES_CTRL_BYTESWAP_DI __BIT(5)
sys/arch/arm/rockchip/rk_v1crypto.h
122
#define RK_V1CRYPTO_TDES_CTRL_MODE __BIT(4)
sys/arch/arm/rockchip/rk_v1crypto.h
125
#define RK_V1CRYPTO_TDES_CTRL_KEYMODE __BIT(3)
sys/arch/arm/rockchip/rk_v1crypto.h
128
#define RK_V1CRYPTO_TDES_CTRL_SELECT __BIT(2)
sys/arch/arm/rockchip/rk_v1crypto.h
131
#define RK_V1CRYPTO_TDES_CTRL_FIFOMODE __BIT(1)
sys/arch/arm/rockchip/rk_v1crypto.h
132
#define RK_V1CRYPTO_TDES_CTRL_DIR __BIT(0)
sys/arch/arm/rockchip/rk_v1crypto.h
137
#define RK_V1CRYPTO_TDES_STS_DONE __BIT(0)
sys/arch/arm/rockchip/rk_v1crypto.h
145
#define RK_V1CRYPTO_HASH_SWAP_DO __BIT(3)
sys/arch/arm/rockchip/rk_v1crypto.h
146
#define RK_V1CRYPTO_HASH_SWAP_DI __BIT(2)
sys/arch/arm/rockchip/rk_v1crypto.h
154
#define RK_V1CRYPTO_HASH_STS_DONE __BIT(0)
sys/arch/arm/rockchip/rk_v1crypto.h
161
#define RK_V1CRYPTO_TRNG_CTRL_OSC_ENABLE __BIT(16)
sys/arch/arm/rockchip/rk_v1crypto.h
36
#define RK_V1CRYPTO_INTSTS_PKA_DONE __BIT(5)
sys/arch/arm/rockchip/rk_v1crypto.h
37
#define RK_V1CRYPTO_INTSTS_HASH_DONE __BIT(4)
sys/arch/arm/rockchip/rk_v1crypto.h
38
#define RK_V1CRYPTO_INTSTS_HRDMA_ERR __BIT(3)
sys/arch/arm/rockchip/rk_v1crypto.h
39
#define RK_V1CRYPTO_INTSTS_HRDMA_DONE __BIT(2)
sys/arch/arm/rockchip/rk_v1crypto.h
40
#define RK_V1CRYPTO_INTSTS_BCDMA_ERR __BIT(1)
sys/arch/arm/rockchip/rk_v1crypto.h
41
#define RK_V1CRYPTO_INTSTS_BCDMA_DONE __BIT(0)
sys/arch/arm/rockchip/rk_v1crypto.h
44
#define RK_V1CRYPTO_INTENA_PKA_DONE __BIT(5)
sys/arch/arm/rockchip/rk_v1crypto.h
45
#define RK_V1CRYPTO_INTENA_HASH_DONE __BIT(4)
sys/arch/arm/rockchip/rk_v1crypto.h
46
#define RK_V1CRYPTO_INTENA_HRDMA_ERR __BIT(3)
sys/arch/arm/rockchip/rk_v1crypto.h
47
#define RK_V1CRYPTO_INTENA_HRDMA_DONE __BIT(2)
sys/arch/arm/rockchip/rk_v1crypto.h
48
#define RK_V1CRYPTO_INTENA_BCDMA_ERR __BIT(1)
sys/arch/arm/rockchip/rk_v1crypto.h
49
#define RK_V1CRYPTO_INTENA_BCDMA_DONE __BIT(0)
sys/arch/arm/rockchip/rk_v1crypto.h
53
#define RK_V1CRYPTO_CTRL_TRNG_FLUSH __BIT(9)
sys/arch/arm/rockchip/rk_v1crypto.h
54
#define RK_V1CRYPTO_CTRL_TRNG_START __BIT(8)
sys/arch/arm/rockchip/rk_v1crypto.h
55
#define RK_V1CRYPTO_CTRL_PKA_FLUSH __BIT(7)
sys/arch/arm/rockchip/rk_v1crypto.h
56
#define RK_V1CRYPTO_CTRL_HASH_FLUSH __BIT(6)
sys/arch/arm/rockchip/rk_v1crypto.h
57
#define RK_V1CRYPTO_CTRL_BLOCK_FLUSH __BIT(5)
sys/arch/arm/rockchip/rk_v1crypto.h
58
#define RK_V1CRYPTO_CTRL_PKA_START __BIT(4)
sys/arch/arm/rockchip/rk_v1crypto.h
59
#define RK_V1CRYPTO_CTRL_HASH_START __BIT(3)
sys/arch/arm/rockchip/rk_v1crypto.h
60
#define RK_V1CRYPTO_CTRL_BLOCK_START __BIT(2)
sys/arch/arm/rockchip/rk_v1crypto.h
61
#define RK_V1CRYPTO_CTRL_TDES_START __BIT(1)
sys/arch/arm/rockchip/rk_v1crypto.h
62
#define RK_V1CRYPTO_CTRL_AES_START __BIT(0)
sys/arch/arm/rockchip/rk_v1crypto.h
65
#define RK_V1CRYPTO_CONF_HR_ADDR_MODE __BIT(8)
sys/arch/arm/rockchip/rk_v1crypto.h
66
#define RK_V1CRYPTO_CONF_BT_ADDR_MODE __BIT(7)
sys/arch/arm/rockchip/rk_v1crypto.h
67
#define RK_V1CRYPTO_CONF_BR_ADDR_MODE __BIT(6)
sys/arch/arm/rockchip/rk_v1crypto.h
70
#define RK_V1CRYPTO_CONF_BYTESWAP_HRFIFO __BIT(5)
sys/arch/arm/rockchip/rk_v1crypto.h
71
#define RK_V1CRYPTO_CONF_BYTESWAP_BTFIFO __BIT(4)
sys/arch/arm/rockchip/rk_v1crypto.h
72
#define RK_V1CRYPTO_CONF_BYTESWAP_BRFIFO __BIT(3)
sys/arch/arm/rockchip/rk_v1crypto.h
73
#define RK_V1CRYPTO_CONF_DESSEL __BIT(2)
sys/arch/arm/rockchip/rk_v1crypto.h
89
#define RK_V1CRYPTO_AES_CTRL_BYTESWAP_CNT __BIT(11)
sys/arch/arm/rockchip/rk_v1crypto.h
90
#define RK_V1CRYPTO_AES_CTRL_BYTESWAP_KEY __BIT(10)
sys/arch/arm/rockchip/rk_v1crypto.h
91
#define RK_V1CRYPTO_AES_CTRL_BYTESWAP_IV __BIT(9)
sys/arch/arm/rockchip/rk_v1crypto.h
92
#define RK_V1CRYPTO_AES_CTRL_BYTESWAP_DO __BIT(8)
sys/arch/arm/rockchip/rk_v1crypto.h
93
#define RK_V1CRYPTO_AES_CTRL_BYTESWAP_DI __BIT(7)
sys/arch/arm/rockchip/rk_v1crypto.h
94
#define RK_V1CRYPTO_AES_CTRL_KEYCHANGE __BIT(6)
sys/arch/arm/rockchip/rk_vop.c
112
#define VOP_INTR0_DMA_FINISH __BIT(15)
sys/arch/arm/rockchip/rk_vop.c
113
#define VOP_INTR0_MMU __BIT(14)
sys/arch/arm/rockchip/rk_vop.c
114
#define VOP_INTR0_DSP_HOLD_VALID __BIT(13)
sys/arch/arm/rockchip/rk_vop.c
115
#define VOP_INTR0_FS_FIELD __BIT(12)
sys/arch/arm/rockchip/rk_vop.c
116
#define VOP_INTR0_POST_BUF_EMPTY __BIT(11)
sys/arch/arm/rockchip/rk_vop.c
117
#define VOP_INTR0_HWC_EMPTY __BIT(10)
sys/arch/arm/rockchip/rk_vop.c
118
#define VOP_INTR0_WIN3_EMPTY __BIT(9)
sys/arch/arm/rockchip/rk_vop.c
119
#define VOP_INTR0_WIN2_EMPTY __BIT(8)
sys/arch/arm/rockchip/rk_vop.c
120
#define VOP_INTR0_WIN1_EMPTY __BIT(7)
sys/arch/arm/rockchip/rk_vop.c
121
#define VOP_INTR0_WIN0_EMPTY __BIT(6)
sys/arch/arm/rockchip/rk_vop.c
122
#define VOP_INTR0_BUS_ERROR __BIT(5)
sys/arch/arm/rockchip/rk_vop.c
123
#define VOP_INTR0_LINE_FLAG1 __BIT(4)
sys/arch/arm/rockchip/rk_vop.c
124
#define VOP_INTR0_LINE_FLAG0 __BIT(3)
sys/arch/arm/rockchip/rk_vop.c
125
#define VOP_INTR0_ADDR_SAME __BIT(2)
sys/arch/arm/rockchip/rk_vop.c
126
#define VOP_INTR0_FS_NEW __BIT(1)
sys/arch/arm/rockchip/rk_vop.c
127
#define VOP_INTR0_FS __BIT(0)
sys/arch/arm/rockchip/rk_vop.c
133
#define DSP_DCLK_POL __BIT(3)
sys/arch/arm/rockchip/rk_vop.c
134
#define DSP_DEN_POL __BIT(2)
sys/arch/arm/rockchip/rk_vop.c
135
#define DSP_VSYNC_POL __BIT(1)
sys/arch/arm/rockchip/rk_vop.c
136
#define DSP_HSYNC_POL __BIT(0)
sys/arch/arm/rockchip/rk_vop.c
220
#define RK3399_VOP_SYS_CTRL_ENABLE __BIT(11)
sys/arch/arm/rockchip/rk_vop.c
56
#define REG_LOAD_EN __BIT(0)
sys/arch/arm/rockchip/rk_vop.c
58
#define VOP_STANDBY_EN __BIT(22)
sys/arch/arm/rockchip/rk_vop.c
59
#define MIPI_OUT_EN __BIT(15)
sys/arch/arm/rockchip/rk_vop.c
60
#define EDP_OUT_EN __BIT(14)
sys/arch/arm/rockchip/rk_vop.c
61
#define HDMI_OUT_EN __BIT(13)
sys/arch/arm/rockchip/rk_vop.c
62
#define RGB_OUT_EN __BIT(12)
sys/arch/arm/rockchip/rk_vop.c
76
#define WIN0_EN __BIT(0)
sys/arch/arm/samsung/exynos4_reg.h
280
#define PHYPWR_FORCE_SUSPEND __BIT(1)
sys/arch/arm/samsung/exynos4_reg.h
281
#define PHYPWR_ANALOG_POWERDOWN __BIT(3)
sys/arch/arm/samsung/exynos4_reg.h
282
#define PHYPWR_OTG_DISABLE __BIT(4)
sys/arch/arm/samsung/exynos4_reg.h
283
#define PHYPWR_SLEEP_PHY0 __BIT(5)
sys/arch/arm/samsung/exynos4_reg.h
291
#define RSTCON_SWRST __BIT(0)
sys/arch/arm/samsung/exynos4_reg.h
292
#define RSTCON_HLINK_RWRST __BIT(1)
sys/arch/arm/samsung/exynos4_reg.h
293
#define RSTCON_DEVPHYLINK_SWRST __BIT(2)
sys/arch/arm/samsung/exynos5410_clock.c
318
CLK_MUX("mout_apll", EXYNOS5410_SRC_CPU, __BIT(0), mout_apll_p),
sys/arch/arm/samsung/exynos5410_clock.c
319
CLK_MUX("mout_cpu", EXYNOS5410_SRC_CPU, __BIT(16), mout_cpu_p),
sys/arch/arm/samsung/exynos5410_clock.c
320
CLK_MUX("mout_kpll", EXYNOS5410_SRC_KFC, __BIT(0), mout_kpll_p),
sys/arch/arm/samsung/exynos5410_clock.c
321
CLK_MUX("mout_kfc", EXYNOS5410_SRC_KFC, __BIT(16), mout_kfc_p),
sys/arch/arm/samsung/exynos5410_clock.c
323
CLK_MUX("sclk_mpll", EXYNOS5410_SRC_CPERI1, __BIT(8), mout_mpll_p),
sys/arch/arm/samsung/exynos5410_clock.c
324
CLK_MUX("sclk_mpll_muxed", EXYNOS5410_SRC_TOP2, __BIT(20), mout_mpll_user_p),
sys/arch/arm/samsung/exynos5410_clock.c
325
CLK_MUX("sclk_bpll", EXYNOS5410_SRC_CDREX, __BIT(0), mout_bpll_p),
sys/arch/arm/samsung/exynos5410_clock.c
326
CLK_MUX("sclk_bpll_muxed", EXYNOS5410_SRC_TOP2, __BIT(24), mout_bpll_user_p),
sys/arch/arm/samsung/exynos5410_clock.c
327
CLK_MUX("sclk_epll", EXYNOS5410_SRC_TOP2, __BIT(12), mout_epll_p),
sys/arch/arm/samsung/exynos5410_clock.c
328
CLK_MUX("sclk_cpll", EXYNOS5410_SRC_TOP2, __BIT(8), mout_cpll_p),
sys/arch/arm/samsung/exynos5410_clock.c
329
CLK_MUX("sclk_mpll_bpll", EXYNOS5410_SRC_TOP1, __BIT(20), mout_mpll_bpll_p),
sys/arch/arm/samsung/exynos5410_clock.c
334
CLK_MUX("mout_usbd300", EXYNOS5410_SRC_FSYS, __BIT(28), mout_sclk_mpll_bpll_p),
sys/arch/arm/samsung/exynos5410_clock.c
335
CLK_MUX("mout_usbd301", EXYNOS5410_SRC_FSYS, __BIT(29), mout_sclk_mpll_bpll_p),
sys/arch/arm/samsung/exynos5410_clock.c
341
CLK_MUX("mout_aclk200", EXYNOS5410_SRC_TOP0, __BIT(12), mout_mpll_bpll_p),
sys/arch/arm/samsung/exynos5410_clock.c
342
CLK_MUX("mout_aclk400", EXYNOS5410_SRC_TOP0, __BIT(20), mout_mpll_bpll_p),
sys/arch/arm/samsung/exynos5410_clock.c
386
CLK_GATE("sss", "aclk266", EXYNOS5410_GATE_IP_G2D, __BIT(2), 0),
sys/arch/arm/samsung/exynos5410_clock.c
388
CLK_GATE("mct", "aclk66", EXYNOS5410_GATE_IP_PERIS, __BIT(18), 0),
sys/arch/arm/samsung/exynos5410_clock.c
389
CLK_GATE("wdt", "aclk66", EXYNOS5410_GATE_IP_PERIS, __BIT(19), 0),
sys/arch/arm/samsung/exynos5410_clock.c
390
CLK_GATE("rtc", "aclk66", EXYNOS5410_GATE_IP_PERIS, __BIT(20), 0),
sys/arch/arm/samsung/exynos5410_clock.c
391
CLK_GATE("tmu", "aclk66", EXYNOS5410_GATE_IP_PERIS, __BIT(21), 0),
sys/arch/arm/samsung/exynos5410_clock.c
394
__BIT(0), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5410_clock.c
396
__BIT(4), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5410_clock.c
398
__BIT(8), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5410_clock.c
400
CLK_GATE("mmc0", "aclk200", EXYNOS5410_GATE_BUS_FSYS0, __BIT(12), 0),
sys/arch/arm/samsung/exynos5410_clock.c
401
CLK_GATE("mmc1", "aclk200", EXYNOS5410_GATE_BUS_FSYS0, __BIT(13), 0),
sys/arch/arm/samsung/exynos5410_clock.c
402
CLK_GATE("mmc2", "aclk200", EXYNOS5410_GATE_BUS_FSYS0, __BIT(14), 0),
sys/arch/arm/samsung/exynos5410_clock.c
403
CLK_GATE("pdma1", "aclk200", EXYNOS5410_GATE_BUS_FSYS0, __BIT(2), 0),
sys/arch/arm/samsung/exynos5410_clock.c
404
CLK_GATE("pdma0", "aclk200", EXYNOS5410_GATE_BUS_FSYS0, __BIT(1), 0),
sys/arch/arm/samsung/exynos5410_clock.c
407
__BIT(7), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5410_clock.c
409
__BIT(8), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5410_clock.c
411
__BIT(9), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5410_clock.c
413
__BIT(10), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5410_clock.c
416
__BIT(11), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5410_clock.c
418
CLK_GATE("uart0", "aclk66", EXYNOS5410_GATE_IP_PERIC, __BIT(0), 0),
sys/arch/arm/samsung/exynos5410_clock.c
419
CLK_GATE("uart1", "aclk66", EXYNOS5410_GATE_IP_PERIC, __BIT(1), 0),
sys/arch/arm/samsung/exynos5410_clock.c
420
CLK_GATE("uart2", "aclk66", EXYNOS5410_GATE_IP_PERIC, __BIT(2), 0),
sys/arch/arm/samsung/exynos5410_clock.c
421
CLK_GATE("uart3", "aclk66", EXYNOS5410_GATE_IP_PERIC, __BIT(3), 0),
sys/arch/arm/samsung/exynos5410_clock.c
422
CLK_GATE("i2c0", "aclk66", EXYNOS5410_GATE_IP_PERIC, __BIT(6), 0),
sys/arch/arm/samsung/exynos5410_clock.c
423
CLK_GATE("i2c1", "aclk66", EXYNOS5410_GATE_IP_PERIC, __BIT(7), 0),
sys/arch/arm/samsung/exynos5410_clock.c
424
CLK_GATE("i2c2", "aclk66", EXYNOS5410_GATE_IP_PERIC, __BIT(8), 0),
sys/arch/arm/samsung/exynos5410_clock.c
425
CLK_GATE("i2c3", "aclk66", EXYNOS5410_GATE_IP_PERIC, __BIT(9), 0),
sys/arch/arm/samsung/exynos5410_clock.c
426
CLK_GATE("usi0", "aclk66", EXYNOS5410_GATE_IP_PERIC, __BIT(10), 0),
sys/arch/arm/samsung/exynos5410_clock.c
427
CLK_GATE("usi1", "aclk66", EXYNOS5410_GATE_IP_PERIC, __BIT(11), 0),
sys/arch/arm/samsung/exynos5410_clock.c
428
CLK_GATE("usi2", "aclk66", EXYNOS5410_GATE_IP_PERIC, __BIT(12), 0),
sys/arch/arm/samsung/exynos5410_clock.c
429
CLK_GATE("usi3", "aclk66", EXYNOS5410_GATE_IP_PERIC, __BIT(13), 0),
sys/arch/arm/samsung/exynos5410_clock.c
430
CLK_GATE("pwm", "aclk66", EXYNOS5410_GATE_IP_PERIC, __BIT(24), 0),
sys/arch/arm/samsung/exynos5410_clock.c
433
__BIT(0), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5410_clock.c
435
__BIT(4), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5410_clock.c
437
__BIT(8), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5410_clock.c
439
__BIT(12), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5410_clock.c
441
CLK_GATE("usbh20", "aclk200", EXYNOS5410_GATE_IP_FSYS, __BIT(18), 0),
sys/arch/arm/samsung/exynos5410_clock.c
442
CLK_GATE("usbd301", "aclk200", EXYNOS5410_GATE_IP_FSYS, __BIT(19), 0),
sys/arch/arm/samsung/exynos5410_clock.c
443
CLK_GATE("usbd300", "aclk200", EXYNOS5410_GATE_IP_FSYS, __BIT(20), 0),
sys/arch/arm/samsung/exynos5422_clock.c
444
CLK_MUXA("sclk_cpll", "mout_cpll", EXYNOS5422_SRC_TOP6, __BIT(28),
sys/arch/arm/samsung/exynos5422_clock.c
446
CLK_MUXA("sclk_dpll", "mout_dpll", EXYNOS5422_SRC_TOP6, __BIT(24),
sys/arch/arm/samsung/exynos5422_clock.c
448
CLK_MUXA("sclk_mpll", "mout_mpll", EXYNOS5422_SRC_TOP6, __BIT(0),
sys/arch/arm/samsung/exynos5422_clock.c
450
CLK_MUXA("sclk_spll", "mout_spll", EXYNOS5422_SRC_TOP6, __BIT(8),
sys/arch/arm/samsung/exynos5422_clock.c
452
CLK_MUXA("sclk_ipll", "mout_ipll", EXYNOS5422_SRC_TOP6, __BIT(12),
sys/arch/arm/samsung/exynos5422_clock.c
454
CLK_MUXF("sclk_epll", "mout_epll", EXYNOS5422_SRC_TOP6, __BIT(20),
sys/arch/arm/samsung/exynos5422_clock.c
456
CLK_MUXF("sclk_rpll", "mout_rpll", EXYNOS5422_SRC_TOP6, __BIT(16),
sys/arch/arm/samsung/exynos5422_clock.c
459
CLK_MUX("mout_sw_aclk200_fsys", EXYNOS5422_SRC_TOP10, __BIT(24),
sys/arch/arm/samsung/exynos5422_clock.c
461
CLK_MUX("mout_sw_aclk200_fsys2", EXYNOS5422_SRC_TOP10, __BIT(12),
sys/arch/arm/samsung/exynos5422_clock.c
463
CLK_MUX("mout_user_aclk200_fsys", EXYNOS5422_SRC_TOP3, __BIT(28),
sys/arch/arm/samsung/exynos5422_clock.c
465
CLK_MUX("mout_user_aclk200_fsys2", EXYNOS5422_SRC_TOP3, __BIT(12),
sys/arch/arm/samsung/exynos5422_clock.c
474
CLK_MUX("mout_sw_aclk66", EXYNOS5422_SRC_TOP11, __BIT(8),
sys/arch/arm/samsung/exynos5422_clock.c
476
CLK_MUX("mout_user_aclk66_peric", EXYNOS5422_SRC_TOP4, __BIT(8),
sys/arch/arm/samsung/exynos5422_clock.c
519
__BIT(9), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
521
__BIT(10), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
524
__BIT(0), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
526
__BIT(1), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
528
__BIT(2), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
530
__BIT(7), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
532
__BIT(8), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
534
__BIT(9), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
536
__BIT(10), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
538
__BIT(0), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
540
__BIT(1), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
542
__BIT(2), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
544
__BIT(3), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
547
__BIT(12), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
549
__BIT(13), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
551
__BIT(14), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
553
__BIT(18), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
555
__BIT(19), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
557
__BIT(20), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
560
__BIT(0), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
562
__BIT(1), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
564
__BIT(2), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
566
__BIT(3), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
568
__BIT(6), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
570
__BIT(7), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
572
__BIT(8), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
574
__BIT(9), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
576
__BIT(14), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5422_clock.c
578
__BIT(24), CLK_SET_RATE_PARENT),
sys/arch/arm/samsung/exynos5_reg.h
377
#define HOST_CTRL0_PHY_SWRST __BIT(0)
sys/arch/arm/samsung/exynos5_reg.h
378
#define HOST_CTRL0_LINK_SWRST __BIT(1)
sys/arch/arm/samsung/exynos5_reg.h
379
#define HOST_CTRL0_UTMI_SWRST __BIT(2)
sys/arch/arm/samsung/exynos5_reg.h
380
#define HOST_CTRL0_WORDINTERFACE __BIT(3)
sys/arch/arm/samsung/exynos5_reg.h
381
#define HOST_CTRL0_FORCESUSPEND __BIT(4)
sys/arch/arm/samsung/exynos5_reg.h
382
#define HOST_CTRL0_FORCESLEEP __BIT(5)
sys/arch/arm/samsung/exynos5_reg.h
383
#define HOST_CTRL0_SIDDQ __BIT(6)
sys/arch/arm/samsung/exynos5_reg.h
384
#define HOST_CTRL0_COMMONON_N __BIT(9) /* common block configuration during suspend */
sys/arch/arm/samsung/exynos5_reg.h
385
#define HOST_CTRL0_RETENABLE __BIT(10)
sys/arch/arm/samsung/exynos5_reg.h
386
#define HOST_CTRL0_TESTBURNIN __BIT(11)
sys/arch/arm/samsung/exynos5_reg.h
392
#define HOST_CTRL0_PHY_SWRST_ALL __BIT(31)
sys/arch/arm/samsung/exynos5_reg.h
399
#define HSIC_CTRL_PHY_SWRST __BIT(0)
sys/arch/arm/samsung/exynos5_reg.h
400
#define HSIC_CTRL_UTMI_SWRST __BIT(2)
sys/arch/arm/samsung/exynos5_reg.h
401
#define HSIC_CTRL_WORDINTERFACE __BIT(3)
sys/arch/arm/samsung/exynos5_reg.h
402
#define HSIC_CTRL_FORCESUSPEND __BIT(4)
sys/arch/arm/samsung/exynos5_reg.h
403
#define HSIC_CTRL_FORCESLEEP __BIT(5)
sys/arch/arm/samsung/exynos5_reg.h
404
#define HSIC_CTRL_SIDDQ __BIT(6)
sys/arch/arm/samsung/exynos5_reg.h
415
#define HOST_EHCICTRL_ENA_INCR16 __BIT(26)
sys/arch/arm/samsung/exynos5_reg.h
416
#define HOST_EHCICTRL_ENA_INCR8 __BIT(27)
sys/arch/arm/samsung/exynos5_reg.h
417
#define HOST_EHCICTRL_ENA_INCR4 __BIT(28)
sys/arch/arm/samsung/exynos5_reg.h
418
#define HOST_EHCICTRL_ENA_INCRXALIGN __BIT(29)
sys/arch/arm/samsung/exynos5_reg.h
421
#define HOST_OHCICTRL_CLKCK_RST __BIT(0)
sys/arch/arm/samsung/exynos5_reg.h
422
#define HOST_OHCICTRL_CNTSEL __BIT(1)
sys/arch/arm/samsung/exynos5_reg.h
423
#define HOST_OHCICTRL_APPSTARTCLK __BIT(2)
sys/arch/arm/samsung/exynos5_reg.h
424
#define HOST_OHCICTRL_SUSPLGCY __BIT(3)
sys/arch/arm/samsung/exynos5_reg.h
427
#define OTG_SYS_FORCESUSPEND __BIT(0)
sys/arch/arm/samsung/exynos5_reg.h
428
#define OTG_SYS_SIDDQ_UOTG __BIT(1)
sys/arch/arm/samsung/exynos5_reg.h
429
#define OTG_SYS_OTGDISABLE __BIT(2)
sys/arch/arm/samsung/exynos5_reg.h
430
#define OTG_SYS_FORCESLEEP __BIT(3)
sys/arch/arm/samsung/exynos5_reg.h
432
#define OTG_SYS_COMMON_ON __BIT(7)
sys/arch/arm/samsung/exynos5_reg.h
433
#define OTG_SYS_IDPULLUP_UOTG __BIT(8)
sys/arch/arm/samsung/exynos5_reg.h
438
#define OTG_SYS_PHY0_SWRST __BIT(12)
sys/arch/arm/samsung/exynos5_reg.h
439
#define OTG_SYS_LINK_SWRST_UOTG __BIT(13)
sys/arch/arm/samsung/exynos5_reg.h
440
#define OTG_SYS_PHYLINK_SWRST __BIT(14)
sys/arch/arm/samsung/exynos_combiner.c
221
if (istatus & __BIT(irq)) {
sys/arch/arm/samsung/exynos_dwcmmc.c
50
#define MPS_CTRL_SECURE_WRITE __BIT(6)
sys/arch/arm/samsung/exynos_dwcmmc.c
51
#define MPS_CTRL_NON_SECURE_READ __BIT(5)
sys/arch/arm/samsung/exynos_dwcmmc.c
52
#define MPS_CTRL_NON_SECURE_WRITE __BIT(4)
sys/arch/arm/samsung/exynos_dwcmmc.c
53
#define MPS_CTRL_VALID __BIT(0)
sys/arch/arm/samsung/exynos_gpio.c
275
return __SHIFTOUT(val, __BIT(pin));
sys/arch/arm/samsung/exynos_gpio.c
287
val &= ~__BIT(pin);
sys/arch/arm/samsung/exynos_gpio.c
289
val |= __BIT(pin);
sys/arch/arm/samsung/exynos_gpio.c
525
val &= ~__BIT(gpin->pin_no);
sys/arch/arm/samsung/exynos_gpio.c
527
val |= __BIT(gpin->pin_no);
sys/arch/arm/samsung/exynos_platform.c
166
started |= __BIT(cpuindex);
sys/arch/arm/samsung/exynos_platform.c
78
#define EXYNOS5800_PMU_KFC_ETM_RESET(n) __BIT(20 + (n))
sys/arch/arm/samsung/exynos_platform.c
79
#define EXYNOS5800_PMU_KFC_CORE_RESET(n) __BIT(8 + (n))
sys/arch/arm/samsung/exynos_platform.c
89
#define EXYNOS5800_PMU_USE_L2_COMMON_UP_STATE __BIT(30)
sys/arch/arm/samsung/exynos_platform.c
90
#define EXYNOS5800_PMU_USE_ARM_CORE_DOWN_STATE __BIT(29)
sys/arch/arm/samsung/exynos_platform.c
91
#define EXYNOS5800_PMU_AUTO_CORE_DOWN __BIT(9)
sys/arch/arm/samsung/exynos_pwm.c
177
if (index >= 32 || (sc->sc_timermask & __BIT(index)) == 0)
sys/arch/arm/samsung/exynos_pwm.c
244
sc->sc_timermask |= __BIT(n);
sys/arch/arm/samsung/exynos_pwm.c
251
sc->sc_timermask |= __BIT(be32toh(data[n]));
sys/arch/arm/samsung/exynos_pwm.c
48
#define TCON_START(n) __BIT(_TCON_OFF(n) + 0)
sys/arch/arm/samsung/exynos_pwm.c
49
#define TCON_UPDATE(n) __BIT(_TCON_OFF(n) + 1)
sys/arch/arm/samsung/exynos_pwm.c
50
#define TCON_OUTINV(n) __BIT(_TCON_OFF(n) + 2)
sys/arch/arm/samsung/exynos_pwm.c
51
#define TCON_AUTO_RELOAD(n) __BIT(_TCON_OFF(n) + 3)
sys/arch/arm/samsung/exynos_pwm.c
52
#define TCON_DEADZONE_EN(n) __BIT(_TCON_OFF(n) + 4)
sys/arch/arm/samsung/exynos_reg.h
121
#define PLL_CON0_ENABLE __BIT(31)
sys/arch/arm/samsung/exynos_reg.h
122
#define PLL_CON0_LOCKED __BIT(29) /* has the PLL locked on */
sys/arch/arm/samsung/exynos_reg.h
155
#define WTCON_ENABLE __BIT(5)
sys/arch/arm/samsung/exynos_reg.h
161
#define WTCON_INT_ENABLE __BIT(2)
sys/arch/arm/samsung/exynos_reg.h
162
#define WTCON_RESET_ENABLE __BIT(0)
sys/arch/arm/samsung/exynos_usbdrdphy.c
47
#define PHY_LINK_SYSTEM_XHCI_VERCTL __BIT(27)
sys/arch/arm/samsung/exynos_usbdrdphy.c
50
#define PHY_UTMI_OTGDISABLE __BIT(6)
sys/arch/arm/samsung/exynos_usbdrdphy.c
53
#define PHY_CLK_RST_SSC_EN __BIT(20)
sys/arch/arm/samsung/exynos_usbdrdphy.c
54
#define PHY_CLK_RST_REF_SSP_EN __BIT(19)
sys/arch/arm/samsung/exynos_usbdrdphy.c
59
#define PHY_CLK_RST_RETENABLEN __BIT(4)
sys/arch/arm/samsung/exynos_usbdrdphy.c
62
#define PHY_CLK_RST_PORTRESET __BIT(1)
sys/arch/arm/samsung/exynos_usbdrdphy.c
63
#define PHY_CLK_RST_COMMONONN __BIT(0)
sys/arch/arm/samsung/exynos_usbdrdphy.c
66
#define PHY_PARAM0_REF_USE_PAD __BIT(31)
sys/arch/arm/samsung/exynos_usbdrdphy.c
71
#define PHY_TEST_POWERDOWN_SSP __BIT(3)
sys/arch/arm/samsung/exynos_usbdrdphy.c
72
#define PHY_TEST_POWERDOWN_HSP __BIT(2)
sys/arch/arm/samsung/exynos_usbdrdphy.c
74
#define PHY_BATCHG_UTMI_CLKSEL __BIT(2)
sys/arch/arm/samsung/exynos_usbdrdphy.c
81
#define USBDRD_PHY_CTRL_EN __BIT(0)
sys/arch/arm/samsung/exynos_usbphy.c
50
#define USB20PHY_CFG_HOST_LINK_EN __BIT(0)
sys/arch/arm/samsung/exynos_usbphy.c
56
#define USBHOST_PHY_CTRL_EN __BIT(0)
sys/arch/arm/samsung/mct_reg.h
39
#define G_CNT_WSTAT_L __BIT(0)
sys/arch/arm/samsung/mct_reg.h
40
#define G_CNT_WSTAT_U __BIT(1)
sys/arch/arm/samsung/mct_reg.h
46
#define G_TCON_COMP0_ENABLE __BIT(0)
sys/arch/arm/samsung/mct_reg.h
47
#define G_TCON_COMP0_AUTOINC __BIT(1)
sys/arch/arm/samsung/mct_reg.h
48
#define G_TCON_START __BIT(8)
sys/arch/arm/samsung/mct_reg.h
50
#define G_INT_CSTAT_CLEAR __BIT(0)
sys/arch/arm/samsung/mct_reg.h
52
#define G_INT_ENB_ENABLE __BIT(0)
sys/arch/arm/samsung/mct_reg.h
54
#define G_WSTAT_COMP0_L __BIT(0)
sys/arch/arm/samsung/mct_reg.h
55
#define G_WSTAT_COMP0_U __BIT(1)
sys/arch/arm/samsung/mct_reg.h
56
#define G_WSTAT_ADD_INCR __BIT(2)
sys/arch/arm/samsung/mct_reg.h
57
#define G_WSTAT_TCON __BIT(16)
sys/arch/arm/samsung/mct_reg.h
65
#define L_INCTB_UPDATE(x) (__BIT(31) | (x))
sys/arch/arm/samsung/mct_reg.h
67
#define L_TCON_TIMER_START __BIT(0)
sys/arch/arm/samsung/mct_reg.h
68
#define L_TCON_INT_START __BIT(1)
sys/arch/arm/samsung/mct_reg.h
69
#define L_TCON_INTERVAL_MODE __BIT(2)
sys/arch/arm/samsung/mct_reg.h
71
#define L_INC_CSTAT_CLEAR __BIT(0)
sys/arch/arm/samsung/mct_reg.h
73
#define L_INT_ENB_ENABLE __BIT(0)
sys/arch/arm/samsung/mct_reg.h
75
#define L_WSTAT_L_TCNTB __BIT(0)
sys/arch/arm/samsung/mct_reg.h
76
#define L_WSTAT_L_ICNTB __BIT(1)
sys/arch/arm/samsung/mct_reg.h
77
#define L_WSTAT_L_TCON __BIT(3)
sys/arch/arm/samsung/sscom_reg.h
102
#define UMCON_AFC __BIT(4)
sys/arch/arm/samsung/sscom_reg.h
103
#define UMCON_MODEMINT_ENABLE __BIT(3)
sys/arch/arm/samsung/sscom_reg.h
104
#define UMCON_RTS __BIT(0) /* Request to send */
sys/arch/arm/samsung/sscom_reg.h
109
#define UTRSTAT_S5L_RX_TIMEOUT __BIT(9) /* Apple specific */
sys/arch/arm/samsung/sscom_reg.h
110
#define UTRSTAT_S5L_TXTHRESH __BIT(5) /* Apple specific */
sys/arch/arm/samsung/sscom_reg.h
111
#define UTRSTAT_S5L_RXTHRESH __BIT(4) /* Apple specific */
sys/arch/arm/samsung/sscom_reg.h
112
#define UTRSTAT_RXTIMEOUT __BIT(3)
sys/arch/arm/samsung/sscom_reg.h
113
#define UTRSTAT_TXSHIFTER_EMPTY __BIT(2)
sys/arch/arm/samsung/sscom_reg.h
114
#define UTRSTAT_TXEMPTY __BIT(1) /* TX fifo or buffer empty */
sys/arch/arm/samsung/sscom_reg.h
115
#define UTRSTAT_RXREADY __BIT(0) /* RX fifo or buffer is not empty */
sys/arch/arm/samsung/sscom_reg.h
117
#define UERSTAT_BREAK __BIT(3) /* Break signal */
sys/arch/arm/samsung/sscom_reg.h
118
#define UERSTAT_FRAME __BIT(2) /* Frame error */
sys/arch/arm/samsung/sscom_reg.h
119
#define UERSTAT_PARITY __BIT(1) /* Parity error */
sys/arch/arm/samsung/sscom_reg.h
120
#define UERSTAT_OVERRUN __BIT(0) /* Overrun */
sys/arch/arm/samsung/sscom_reg.h
123
#define UFSTAT_TXFULL __BIT(24) /* Tx fifo full */
sys/arch/arm/samsung/sscom_reg.h
125
#define UFSTAT_RXERROR __BIT(9)
sys/arch/arm/samsung/sscom_reg.h
126
#define UFSTAT_S5L_TXFULL __BIT(9) /* Tx fifo full (Apple) */
sys/arch/arm/samsung/sscom_reg.h
127
#define UFSTAT_RXFULL __BIT(8) /* Rx fifo full */
sys/arch/arm/samsung/sscom_reg.h
128
#define UFSTAT_S5L_RXFULL __BIT(8) /* Rx fifo full (Apple) */
sys/arch/arm/samsung/sscom_reg.h
132
#define UMSTAT_DCTS __BIT(4)
sys/arch/arm/samsung/sscom_reg.h
133
#define UMSTAT_CTS __BIT(0) /* Clear to send */
sys/arch/arm/samsung/sscom_reg.h
148
#define UINT_MODEM __BIT(3)
sys/arch/arm/samsung/sscom_reg.h
149
#define UINT_TXD __BIT(2)
sys/arch/arm/samsung/sscom_reg.h
150
#define UINT_ERROR __BIT(1)
sys/arch/arm/samsung/sscom_reg.h
151
#define UINT_RXD __BIT(0)
sys/arch/arm/samsung/sscom_reg.h
44
#define ULCON_IR __BIT(6)
sys/arch/arm/samsung/sscom_reg.h
51
#define ULCON_STOP __BIT(2)
sys/arch/arm/samsung/sscom_reg.h
69
#define UCON_S5L_TXTHRESH __BIT(13) /* Apple specific */
sys/arch/arm/samsung/sscom_reg.h
70
#define UCON_S5L_RXTHRESH __BIT(12) /* Apple specific */
sys/arch/arm/samsung/sscom_reg.h
71
#define UCON_RXTO_FIFO_EMPTY __BIT(11)
sys/arch/arm/samsung/sscom_reg.h
72
#define UCON_RXTO_DMA_FSM_STOP __BIT(10)
sys/arch/arm/samsung/sscom_reg.h
73
#define UCON_TXINT_TYPE __BIT(9) /* Tx interrupt. 0=pulse,1=level */
sys/arch/arm/samsung/sscom_reg.h
76
#define UCON_S5L_RX_TIMEOUT __BIT(9) /* Apple specific */
sys/arch/arm/samsung/sscom_reg.h
77
#define UCON_RXINT_TYPE __BIT(8) /* Rx interrupt */
sys/arch/arm/samsung/sscom_reg.h
80
#define UCON_TOINT __BIT(7) /* Rx timeout interrupt */
sys/arch/arm/samsung/sscom_reg.h
81
#define UCON_ERRINT __BIT(6) /* receive error interrupt */
sys/arch/arm/samsung/sscom_reg.h
82
#define UCON_LOOP __BIT(5) /* loopback */
sys/arch/arm/samsung/sscom_reg.h
83
#define UCON_SBREAK __BIT(4) /* send break */
sys/arch/arm/samsung/sscom_reg.h
97
#define UFCON_TXFIFO_RESET __BIT(2)
sys/arch/arm/samsung/sscom_reg.h
98
#define UFCON_RXFIFO_RESET __BIT(1)
sys/arch/arm/samsung/sscom_reg.h
99
#define UFCON_FIFO_ENABLE __BIT(0)
sys/arch/arm/sunxi/sun4i_a10_ccu.c
177
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
189
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
200
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
212
__BIT(14), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
218
__BIT(24), /* sel */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
219
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
228
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
237
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
277
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
285
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
293
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
301
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
309
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
317
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
328
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
339
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
350
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
362
__BIT(15), /* div_en */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
363
__BIT(14), /* frac_sel */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
367
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
374
__BIT(15), /* div_en */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
375
__BIT(14), /* frac_sel */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
379
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
392
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
399
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
406
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
413
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
424
.u.div.enable = __BIT(31),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
441
.u.div.enable = __BIT(31),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
458
.u.div.enable = __BIT(15) | __BIT(31),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
474
.u.div.enable = __BIT(15) | __BIT(31),
sys/arch/arm/sunxi/sun4i_a10_ccu.c
486
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
496
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_ccu.c
504
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun4i_a10_codec.c
47
#define A10_DACAREN __BIT(31)
sys/arch/arm/sunxi/sun4i_a10_codec.c
48
#define A10_DACALEN __BIT(30)
sys/arch/arm/sunxi/sun4i_a10_codec.c
49
#define A10_MIXEN __BIT(29)
sys/arch/arm/sunxi/sun4i_a10_codec.c
50
#define A10_LNG __BIT(26)
sys/arch/arm/sunxi/sun4i_a10_codec.c
53
#define A10_LLNS __BIT(19)
sys/arch/arm/sunxi/sun4i_a10_codec.c
54
#define A10_RLNS __BIT(18)
sys/arch/arm/sunxi/sun4i_a10_codec.c
55
#define A10_LFMS __BIT(17)
sys/arch/arm/sunxi/sun4i_a10_codec.c
56
#define A10_RFMS __BIT(16)
sys/arch/arm/sunxi/sun4i_a10_codec.c
57
#define A10_LDACLMIXS __BIT(15)
sys/arch/arm/sunxi/sun4i_a10_codec.c
58
#define A10_RDACRMIXS __BIT(14)
sys/arch/arm/sunxi/sun4i_a10_codec.c
59
#define A10_LDACRMIXS __BIT(13)
sys/arch/arm/sunxi/sun4i_a10_codec.c
60
#define A10_MICLS __BIT(12)
sys/arch/arm/sunxi/sun4i_a10_codec.c
61
#define A10_MICRS __BIT(11)
sys/arch/arm/sunxi/sun4i_a10_codec.c
62
#define A10_DACPAS __BIT(8)
sys/arch/arm/sunxi/sun4i_a10_codec.c
63
#define A10_MIXPAS __BIT(7)
sys/arch/arm/sunxi/sun4i_a10_codec.c
64
#define A10_PAMUTE __BIT(6)
sys/arch/arm/sunxi/sun4i_a10_codec.c
68
#define A10_ADCREN __BIT(31)
sys/arch/arm/sunxi/sun4i_a10_codec.c
69
#define A10_ADCLEN __BIT(30)
sys/arch/arm/sunxi/sun4i_a10_codec.c
70
#define A10_PREG1EN __BIT(29)
sys/arch/arm/sunxi/sun4i_a10_codec.c
71
#define A10_PREG2EN __BIT(28)
sys/arch/arm/sunxi/sun4i_a10_codec.c
72
#define A10_VMICEN __BIT(27)
sys/arch/arm/sunxi/sun4i_a10_codec.c
77
#define A10_LNRDF __BIT(16)
sys/arch/arm/sunxi/sun4i_a10_codec.c
79
#define A10_MIC1NEN __BIT(12)
sys/arch/arm/sunxi/sun4i_a10_codec.c
80
#define A10_DITHER __BIT(8)
sys/arch/arm/sunxi/sun4i_a10_codec.c
81
#define A10_PA_EN __BIT(4)
sys/arch/arm/sunxi/sun4i_a10_codec.c
82
#define A10_DDE __BIT(3)
sys/arch/arm/sunxi/sun4i_a10_codec.c
83
#define A10_COMPTEN __BIT(2)
sys/arch/arm/sunxi/sun4i_dma.c
329
mask = __BIT(bit - 1);
sys/arch/arm/sunxi/sun4i_dma.c
400
ch->ch_irqmask = __BIT((type * 16) + (index * 2) + 1);
sys/arch/arm/sunxi/sun4i_dma.c
57
#define NDMA_CTRL_LOAD __BIT(31)
sys/arch/arm/sunxi/sun4i_dma.c
58
#define NDMA_CTRL_CONTI_EN __BIT(30)
sys/arch/arm/sunxi/sun4i_dma.c
62
#define NDMA_CTRL_DST_ADDR_TYPE __BIT(21)
sys/arch/arm/sunxi/sun4i_dma.c
64
#define NDMA_CTRL_BC_MODE_SEL __BIT(15)
sys/arch/arm/sunxi/sun4i_dma.c
67
#define NDMA_CTRL_SRC_ADDR_TYPE __BIT(5)
sys/arch/arm/sunxi/sun4i_dma.c
73
#define DDMA_CTRL_LOAD __BIT(31)
sys/arch/arm/sunxi/sun4i_dma.c
74
#define DDMA_CTRL_BSY_STA __BIT(30)
sys/arch/arm/sunxi/sun4i_dma.c
75
#define DDMA_CTRL_CONTI_EN __BIT(29)
sys/arch/arm/sunxi/sun4i_dma.c
80
#define DDMA_CTRL_BC_MODE_SEL __BIT(15)
sys/arch/arm/sunxi/sun4i_emac.c
100
#define EMAC_RX_CTL_START __BIT(0)
sys/arch/arm/sunxi/sun4i_emac.c
104
#define EMAC_RX_STA_PKTOK __BIT(7)
sys/arch/arm/sunxi/sun4i_emac.c
105
#define EMAC_RX_STA_ALNERR __BIT(6)
sys/arch/arm/sunxi/sun4i_emac.c
106
#define EMAC_RX_STA_LENERR __BIT(5)
sys/arch/arm/sunxi/sun4i_emac.c
107
#define EMAC_RX_STA_CRCERR __BIT(4)
sys/arch/arm/sunxi/sun4i_emac.c
112
#define EMAC_INT_RX __BIT(8)
sys/arch/arm/sunxi/sun4i_emac.c
113
#define EMAC_INT_TX1 __BIT(1)
sys/arch/arm/sunxi/sun4i_emac.c
114
#define EMAC_INT_TX0 __BIT(0)
sys/arch/arm/sunxi/sun4i_emac.c
118
#define EMAC_MAC_CTL0_SOFT_RESET __BIT(15)
sys/arch/arm/sunxi/sun4i_emac.c
119
#define EMAC_MAC_CTL0_TFC __BIT(3)
sys/arch/arm/sunxi/sun4i_emac.c
120
#define EMAC_MAC_CTL0_RFC __BIT(2)
sys/arch/arm/sunxi/sun4i_emac.c
122
#define EMAC_MAC_CTL1_ED __BIT(15)
sys/arch/arm/sunxi/sun4i_emac.c
123
#define EMAC_MAC_CTL1_NB __BIT(13)
sys/arch/arm/sunxi/sun4i_emac.c
124
#define EMAC_MAC_CTL1_BNB __BIT(12)
sys/arch/arm/sunxi/sun4i_emac.c
125
#define EMAC_MAC_CTL1_LPE __BIT(9)
sys/arch/arm/sunxi/sun4i_emac.c
126
#define EMAC_MAC_CTL1_PRE __BIT(8)
sys/arch/arm/sunxi/sun4i_emac.c
127
#define EMAC_MAC_CTL1_ADP __BIT(7)
sys/arch/arm/sunxi/sun4i_emac.c
128
#define EMAC_MAC_CTL1_VC __BIT(6)
sys/arch/arm/sunxi/sun4i_emac.c
129
#define EMAC_MAC_CTL1_PC __BIT(5)
sys/arch/arm/sunxi/sun4i_emac.c
130
#define EMAC_MAC_CTL1_CRC __BIT(4)
sys/arch/arm/sunxi/sun4i_emac.c
131
#define EMAC_MAC_CTL1_DCRC __BIT(3)
sys/arch/arm/sunxi/sun4i_emac.c
132
#define EMAC_MAC_CTL1_HF __BIT(2)
sys/arch/arm/sunxi/sun4i_emac.c
133
#define EMAC_MAC_CTL1_FLC __BIT(1)
sys/arch/arm/sunxi/sun4i_emac.c
134
#define EMAC_MAC_CTL1_FD __BIT(0)
sys/arch/arm/sunxi/sun4i_emac.c
145
#define EMAC_MAC_SUPP_100M __BIT(8)
sys/arch/arm/sunxi/sun4i_emac.c
61
#define EMAC_CTL_RX_EN __BIT(2)
sys/arch/arm/sunxi/sun4i_emac.c
62
#define EMAC_CTL_TX_EN __BIT(1)
sys/arch/arm/sunxi/sun4i_emac.c
63
#define EMAC_CTL_RST __BIT(0)
sys/arch/arm/sunxi/sun4i_emac.c
633
sc->sc_tx_active &= ~__BIT(slot);
sys/arch/arm/sunxi/sun4i_emac.c
65
#define EMAC_TX_MODE_DMA __BIT(1)
sys/arch/arm/sunxi/sun4i_emac.c
66
#define EMAC_TX_MODE_ABF_ENA __BIT(0)
sys/arch/arm/sunxi/sun4i_emac.c
71
#define EMAC_TX_CTL_START __BIT(0)
sys/arch/arm/sunxi/sun4i_emac.c
85
#define EMAC_RX_CTL_SA_IF __BIT(25)
sys/arch/arm/sunxi/sun4i_emac.c
86
#define EMAC_RX_CTL_SA __BIT(24)
sys/arch/arm/sunxi/sun4i_emac.c
87
#define EMAC_RX_CTL_BC0 __BIT(22)
sys/arch/arm/sunxi/sun4i_emac.c
88
#define EMAC_RX_CTL_MHF __BIT(21)
sys/arch/arm/sunxi/sun4i_emac.c
889
hash[crc >> 5] |= __BIT(crc & 31);
sys/arch/arm/sunxi/sun4i_emac.c
89
#define EMAC_RX_CTL_MC0 __BIT(20)
sys/arch/arm/sunxi/sun4i_emac.c
90
#define EMAC_RX_CTL_DAF __BIT(17)
sys/arch/arm/sunxi/sun4i_emac.c
91
#define EMAC_RX_CTL_UCAD __BIT(16)
sys/arch/arm/sunxi/sun4i_emac.c
92
#define EMAC_RX_CTL_POR __BIT(8)
sys/arch/arm/sunxi/sun4i_emac.c
93
#define EMAC_RX_CTL_PLE __BIT(7)
sys/arch/arm/sunxi/sun4i_emac.c
94
#define EMAC_RX_CTL_PCRCE __BIT(6)
sys/arch/arm/sunxi/sun4i_emac.c
95
#define EMAC_RX_CTL_PCF __BIT(5)
sys/arch/arm/sunxi/sun4i_emac.c
96
#define EMAC_RX_CTL_PROMISC __BIT(4)
sys/arch/arm/sunxi/sun4i_emac.c
97
#define EMAC_RX_CTL_FIFO_RESET __BIT(3)
sys/arch/arm/sunxi/sun4i_emac.c
98
#define EMAC_RX_CTL_DMA __BIT(2)
sys/arch/arm/sunxi/sun4i_emac.c
99
#define EMAC_RX_CTL_DRQ_MODE __BIT(1)
sys/arch/arm/sunxi/sun4i_spireg.h
100
#define SPI_DMACTL_TF_NF_DMA __BIT(10)
sys/arch/arm/sunxi/sun4i_spireg.h
101
#define SPI_DMACTL_TF_HE_DMA __BIT(9)
sys/arch/arm/sunxi/sun4i_spireg.h
102
#define SPI_DMACTL_TF_EMP_DMA __BIT(8)
sys/arch/arm/sunxi/sun4i_spireg.h
103
#define SPI_DMACTL_RF_FU34_DMA __BIT(4)
sys/arch/arm/sunxi/sun4i_spireg.h
104
#define SPI_DMACTL_RF_FU14_DMA __BIT(3)
sys/arch/arm/sunxi/sun4i_spireg.h
105
#define SPI_DMACTL_RF_FU_DMA __BIT(2)
sys/arch/arm/sunxi/sun4i_spireg.h
106
#define SPI_DMACTL_RF_HF_DMA __BIT(1)
sys/arch/arm/sunxi/sun4i_spireg.h
107
#define SPI_DMACTL_RF_RDY_DMA __BIT(0)
sys/arch/arm/sunxi/sun4i_spireg.h
113
#define SPI_CCTL_DRS __BIT(12)
sys/arch/arm/sunxi/sun4i_spireg.h
39
#define SPI_CTL_SDM __BIT(20)
sys/arch/arm/sunxi/sun4i_spireg.h
40
#define SPI_CTL_SDC __BIT(19)
sys/arch/arm/sunxi/sun4i_spireg.h
41
#define SPI_CTL_TP_EN __BIT(18)
sys/arch/arm/sunxi/sun4i_spireg.h
42
#define SPI_CTL_SS_LEVEL __BIT(17)
sys/arch/arm/sunxi/sun4i_spireg.h
43
#define SPI_CTL_SS_CTRL __BIT(16)
sys/arch/arm/sunxi/sun4i_spireg.h
44
#define SPI_CTL_DHB __BIT(15)
sys/arch/arm/sunxi/sun4i_spireg.h
45
#define SPI_CTL_DDB __BIT(14)
sys/arch/arm/sunxi/sun4i_spireg.h
47
#define SPI_CTL_RPSM __BIT(11)
sys/arch/arm/sunxi/sun4i_spireg.h
48
#define SPI_CTL_XCH __BIT(10)
sys/arch/arm/sunxi/sun4i_spireg.h
49
#define SPI_CTL_RF_RST __BIT(9)
sys/arch/arm/sunxi/sun4i_spireg.h
50
#define SPI_CTL_TF_RST __BIT(8)
sys/arch/arm/sunxi/sun4i_spireg.h
51
#define SPI_CTL_SSCTL __BIT(7)
sys/arch/arm/sunxi/sun4i_spireg.h
52
#define SPI_CTL_LMTF __BIT(6)
sys/arch/arm/sunxi/sun4i_spireg.h
53
#define SPI_CTL_DMAMC __BIT(5)
sys/arch/arm/sunxi/sun4i_spireg.h
54
#define SPI_CTL_SSPOL __BIT(4)
sys/arch/arm/sunxi/sun4i_spireg.h
55
#define SPI_CTL_POL __BIT(3)
sys/arch/arm/sunxi/sun4i_spireg.h
56
#define SPI_CTL_PHA __BIT(2)
sys/arch/arm/sunxi/sun4i_spireg.h
57
#define SPI_CTL_MODE __BIT(1)
sys/arch/arm/sunxi/sun4i_spireg.h
58
#define SPI_CTL_EN __BIT(0)
sys/arch/arm/sunxi/sun4i_spireg.h
61
#define SPI_INTCTL_SS_INT_EN __BIT(17)
sys/arch/arm/sunxi/sun4i_spireg.h
62
#define SPI_INTCTL_TX_INT_EN __BIT(16)
sys/arch/arm/sunxi/sun4i_spireg.h
63
#define SPI_INTCTL_TF_UR_INT_EN __BIT(14)
sys/arch/arm/sunxi/sun4i_spireg.h
64
#define SPI_INTCTL_TF_OF_INT_EN __BIT(13)
sys/arch/arm/sunxi/sun4i_spireg.h
65
#define SPI_INTCTL_TF_E34_INT_EN __BIT(12)
sys/arch/arm/sunxi/sun4i_spireg.h
66
#define SPI_INTCTL_TF_E14_INT_EN __BIT(11)
sys/arch/arm/sunxi/sun4i_spireg.h
67
#define SPI_INTCTL_TF_FL_INT_EN __BIT(10)
sys/arch/arm/sunxi/sun4i_spireg.h
68
#define SPI_INTCTL_TF_HALF_EMP_INT_EN __BIT(9)
sys/arch/arm/sunxi/sun4i_spireg.h
69
#define SPI_INTCTL_TF_EMP_INT_EN __BIT(8)
sys/arch/arm/sunxi/sun4i_spireg.h
70
#define SPI_INTCTL_RF_UR_INT_EN __BIT(6)
sys/arch/arm/sunxi/sun4i_spireg.h
71
#define SPI_INTCTL_RF_OF_INT_EN __BIT(5)
sys/arch/arm/sunxi/sun4i_spireg.h
72
#define SPI_INTCTL_RF_F34_INT_EN __BIT(4)
sys/arch/arm/sunxi/sun4i_spireg.h
73
#define SPI_INTCTL_RF_F14_INT_EN __BIT(3)
sys/arch/arm/sunxi/sun4i_spireg.h
74
#define SPI_INTCTL_RF_FU_INT_EN __BIT(2)
sys/arch/arm/sunxi/sun4i_spireg.h
75
#define SPI_INTCTL_RF_HALF_FU_INT_EN __BIT(1)
sys/arch/arm/sunxi/sun4i_spireg.h
76
#define SPI_INTCTL_RF_RDY_INT_EN __BIT(0)
sys/arch/arm/sunxi/sun4i_spireg.h
79
#define SPI_INT_STA_INT_CBF __BIT(31)
sys/arch/arm/sunxi/sun4i_spireg.h
80
#define SPI_INT_STA_SSI __BIT(17)
sys/arch/arm/sunxi/sun4i_spireg.h
81
#define SPI_INT_STA_TC __BIT(16)
sys/arch/arm/sunxi/sun4i_spireg.h
82
#define SPI_INT_STA_TU __BIT(14)
sys/arch/arm/sunxi/sun4i_spireg.h
83
#define SPI_INT_STA_TO __BIT(13)
sys/arch/arm/sunxi/sun4i_spireg.h
84
#define SPI_INT_STA_TE34 __BIT(12)
sys/arch/arm/sunxi/sun4i_spireg.h
85
#define SPI_INT_STA_TE14 __BIT(11)
sys/arch/arm/sunxi/sun4i_spireg.h
86
#define SPI_INT_STA_TF __BIT(10)
sys/arch/arm/sunxi/sun4i_spireg.h
87
#define SPI_INT_STA_THE __BIT(9)
sys/arch/arm/sunxi/sun4i_spireg.h
88
#define SPI_INT_STA_TE __BIT(8)
sys/arch/arm/sunxi/sun4i_spireg.h
89
#define SPI_INT_STA_RU __BIT(6)
sys/arch/arm/sunxi/sun4i_spireg.h
90
#define SPI_INT_STA_RO __BIT(5)
sys/arch/arm/sunxi/sun4i_spireg.h
91
#define SPI_INT_STA_RF34 __BIT(4)
sys/arch/arm/sunxi/sun4i_spireg.h
92
#define SPI_INT_STA_RF14 __BIT(3)
sys/arch/arm/sunxi/sun4i_spireg.h
93
#define SPI_INT_STA_RF __BIT(2)
sys/arch/arm/sunxi/sun4i_spireg.h
94
#define SPI_INT_STA_RHF __BIT(1)
sys/arch/arm/sunxi/sun4i_spireg.h
95
#define SPI_INT_STA_RR __BIT(0)
sys/arch/arm/sunxi/sun4i_spireg.h
98
#define SPI_DMACTL_TF_EMP34_DMA __BIT(12)
sys/arch/arm/sunxi/sun4i_spireg.h
99
#define SPI_DMACTL_TF_EMP14_DMA __BIT(11)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
129
#define A64_OUTPUT_SOURCE_LINE __BIT(0)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
130
#define A64_OUTPUT_SOURCE_HP __BIT(1)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
44
#define A64_AC_PR_RST __BIT(28)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
45
#define A64_AC_PR_RW __BIT(24)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
51
#define A64_HPPA_EN __BIT(6)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
54
#define A64_LMIXMUTE_LDAC __BIT(1)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
56
#define A64_RMIXMUTE_RDAC __BIT(1)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
58
#define A64_LINEOUT_LEFT_EN __BIT(7)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
59
#define A64_LINEOUT_RIGHT_EN __BIT(6)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
65
#define A64_MIC1AMPEN __BIT(3)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
68
#define A64_MIC2_SEL __BIT(7)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
70
#define A64_MIC2AMPEN __BIT(3)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
75
#define A64_DACAREN __BIT(7)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
76
#define A64_DACALEN __BIT(6)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
77
#define A64_RMIXEN __BIT(5)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
78
#define A64_LMIXEN __BIT(4)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
79
#define A64_RHPPAMUTE __BIT(3)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
80
#define A64_LHPPAMUTE __BIT(2)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
81
#define A64_RHPIS __BIT(1)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
82
#define A64_LHPIS __BIT(0)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
85
#define A64_ADCMIX_SRC_MIC1 __BIT(6)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
86
#define A64_ADCMIX_SRC_MIC2 __BIT(5)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
87
#define A64_ADCMIX_SRC_LINEIN __BIT(2)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
88
#define A64_ADCMIX_SRC_OMIXER __BIT(1)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
90
#define A64_ADCREN __BIT(7)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
91
#define A64_ADCLEN __BIT(6)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
94
#define A64_JACKDETEN __BIT(7)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
95
#define A64_INNERRESEN __BIT(6)
sys/arch/arm/sunxi/sun50i_a64_acodec.c
96
#define A64_AUTOPLEN __BIT(1)
sys/arch/arm/sunxi/sun50i_a64_ccu.c
257
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
258
__BIT(28), /* lock */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
268
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
278
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
288
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
289
__BIT(28), /* lock */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
303
__BIT(24), /* div_en */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
304
__BIT(25), /* frac_sel */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
308
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
318
__BIT(24), /* div_en */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
319
__BIT(25), /* frac_sel */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
323
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
331
__BIT(24), /* div_en */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
332
__BIT(25), /* frac_sel */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
336
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
344
__BIT(24), /* div_en */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
345
__BIT(25), /* frac_sel */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
349
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
360
__BIT(3), /* prediv_sel */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
368
__BIT(1), /* prediv_sel */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
392
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
399
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
406
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
414
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
421
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
428
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
440
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
450
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
456
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
462
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
470
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
478
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
485
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
492
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_ccu.c
499
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_r_ccu.c
108
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_a64_r_ccu.c
76
__BIT(2), /* prediv_sel */
sys/arch/arm/sunxi/sun50i_h6_ccu.c
230
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_h6_ccu.c
231
__BIT(28), /* lock */
sys/arch/arm/sunxi/sun50i_h6_ccu.c
239
__BIT(1), /* m */
sys/arch/arm/sunxi/sun50i_h6_ccu.c
240
__BIT(0), /* p */
sys/arch/arm/sunxi/sun50i_h6_ccu.c
241
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_h6_ccu.c
267
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_h6_ccu.c
274
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_h6_ccu.c
281
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_h6_ccu.c
360
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_h6_ccu.c
366
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_h6_r_ccu.c
114
__BIT(24), /* sel */
sys/arch/arm/sunxi/sun50i_h6_r_ccu.c
115
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_h6_r_ccu.c
122
__BIT(24), /* sel */
sys/arch/arm/sunxi/sun50i_h6_r_ccu.c
123
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun50i_h6_r_ccu.c
80
__BIT(2), /* prediv_sel */
sys/arch/arm/sunxi/sun50i_h6_r_ccu.c
96
__BIT(2), /* prediv_sel */
sys/arch/arm/sunxi/sun5i_a13_ccu.c
123
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun5i_a13_ccu.c
132
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun5i_a13_ccu.c
143
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun5i_a13_ccu.c
149
__BIT(3), /* prediv_sel */
sys/arch/arm/sunxi/sun5i_a13_ccu.c
186
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun5i_a13_ccu.c
193
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun5i_a13_ccu.c
200
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun5i_a13_ccu.c
208
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun6i_a31_ccu.c
157
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun6i_a31_ccu.c
158
__BIT(28), /* lock */
sys/arch/arm/sunxi/sun6i_a31_ccu.c
168
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun6i_a31_ccu.c
180
__BIT(3), /* prediv_sel */
sys/arch/arm/sunxi/sun6i_a31_ccu.c
194
SD0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
sys/arch/arm/sunxi/sun6i_a31_ccu.c
197
SD1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
sys/arch/arm/sunxi/sun6i_a31_ccu.c
200
SD2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
sys/arch/arm/sunxi/sun6i_a31_ccu.c
203
SD3_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
sys/arch/arm/sunxi/sun6i_a31_codec.c
101
#define PHONEOUTEN __BIT(4)
sys/arch/arm/sunxi/sun6i_a31_codec.c
102
#define PHONEOUTS0 __BIT(3)
sys/arch/arm/sunxi/sun6i_a31_codec.c
103
#define PHONEOUTS1 __BIT(2)
sys/arch/arm/sunxi/sun6i_a31_codec.c
104
#define PHONEOUTS2 __BIT(1)
sys/arch/arm/sunxi/sun6i_a31_codec.c
105
#define PHONEOUTS3 __BIT(0)
sys/arch/arm/sunxi/sun6i_a31_codec.c
108
#define ADCREN __BIT(31)
sys/arch/arm/sunxi/sun6i_a31_codec.c
109
#define ADCLEN __BIT(30)
sys/arch/arm/sunxi/sun6i_a31_codec.c
113
#define RADCMIXMUTE_MIC1 __BIT(13)
sys/arch/arm/sunxi/sun6i_a31_codec.c
114
#define RADCMIXMUTE_MIC2 __BIT(12)
sys/arch/arm/sunxi/sun6i_a31_codec.c
115
#define RADCMIXMUTE_PHONEP_PHONEN __BIT(11)
sys/arch/arm/sunxi/sun6i_a31_codec.c
116
#define RADCMIXMUTE_PHONEP __BIT(10)
sys/arch/arm/sunxi/sun6i_a31_codec.c
117
#define RADCMIXMUTE_LINEINR __BIT(9)
sys/arch/arm/sunxi/sun6i_a31_codec.c
118
#define RADCMIXMUTE_ROM __BIT(8)
sys/arch/arm/sunxi/sun6i_a31_codec.c
119
#define RADCMIXMUTE_LOM __BIT(7)
sys/arch/arm/sunxi/sun6i_a31_codec.c
121
#define LADCMIXMUTE_MIC1 __BIT(6)
sys/arch/arm/sunxi/sun6i_a31_codec.c
122
#define LADCMIXMUTE_MIC2 __BIT(5)
sys/arch/arm/sunxi/sun6i_a31_codec.c
123
#define LADCMIXMUTE_PHONEP_PHONEN __BIT(4)
sys/arch/arm/sunxi/sun6i_a31_codec.c
124
#define LADCMIXMUTE_PHONEN __BIT(3)
sys/arch/arm/sunxi/sun6i_a31_codec.c
125
#define LADCMIXMUTE_LINEINL __BIT(2)
sys/arch/arm/sunxi/sun6i_a31_codec.c
126
#define LADCMIXMUTE_LOM __BIT(1)
sys/arch/arm/sunxi/sun6i_a31_codec.c
127
#define LADCMIXMUTE_ROM __BIT(0)
sys/arch/arm/sunxi/sun6i_a31_codec.c
47
#define DACAREN __BIT(31)
sys/arch/arm/sunxi/sun6i_a31_codec.c
48
#define DACALEN __BIT(30)
sys/arch/arm/sunxi/sun6i_a31_codec.c
49
#define RMIXEN __BIT(29)
sys/arch/arm/sunxi/sun6i_a31_codec.c
50
#define LMIXEN __BIT(28)
sys/arch/arm/sunxi/sun6i_a31_codec.c
52
#define RMIXMUTE_MIC1 __BIT(23)
sys/arch/arm/sunxi/sun6i_a31_codec.c
53
#define RMIXMUTE_MIC2 __BIT(22)
sys/arch/arm/sunxi/sun6i_a31_codec.c
54
#define RMIXMUTE_PHONEP_PHONEN __BIT(21)
sys/arch/arm/sunxi/sun6i_a31_codec.c
55
#define RMIXMUTE_PHONEP __BIT(20)
sys/arch/arm/sunxi/sun6i_a31_codec.c
56
#define RMIXMUTE_LINEINR __BIT(19)
sys/arch/arm/sunxi/sun6i_a31_codec.c
57
#define RMIXMUTE_DACR __BIT(18)
sys/arch/arm/sunxi/sun6i_a31_codec.c
58
#define RMIXMUTE_DACL __BIT(17)
sys/arch/arm/sunxi/sun6i_a31_codec.c
60
#define LMIXMUTE_MIC1 __BIT(16)
sys/arch/arm/sunxi/sun6i_a31_codec.c
61
#define LMIXMUTE_MIC2 __BIT(15)
sys/arch/arm/sunxi/sun6i_a31_codec.c
62
#define LMIXMUTE_PHONEP_PHONEN __BIT(14)
sys/arch/arm/sunxi/sun6i_a31_codec.c
63
#define LMIXMUTE_PHONEN __BIT(13)
sys/arch/arm/sunxi/sun6i_a31_codec.c
64
#define LMIXMUTE_LINEINL __BIT(12)
sys/arch/arm/sunxi/sun6i_a31_codec.c
65
#define LMIXMUTE_DACL __BIT(11)
sys/arch/arm/sunxi/sun6i_a31_codec.c
66
#define LMIXMUTE_DACR __BIT(10)
sys/arch/arm/sunxi/sun6i_a31_codec.c
67
#define RHPIS __BIT(9)
sys/arch/arm/sunxi/sun6i_a31_codec.c
68
#define LHPIS __BIT(8)
sys/arch/arm/sunxi/sun6i_a31_codec.c
69
#define RHPPAMUTE __BIT(7)
sys/arch/arm/sunxi/sun6i_a31_codec.c
70
#define LHPPAMUTE __BIT(6)
sys/arch/arm/sunxi/sun6i_a31_codec.c
74
#define HPPAEN __BIT(31)
sys/arch/arm/sunxi/sun6i_a31_codec.c
76
#define COMPTEN __BIT(28)
sys/arch/arm/sunxi/sun6i_a31_codec.c
86
#define HBIASEN __BIT(31)
sys/arch/arm/sunxi/sun6i_a31_codec.c
87
#define MBIASEN __BIT(30)
sys/arch/arm/sunxi/sun6i_a31_codec.c
88
#define HBIASADCEN __BIT(29)
sys/arch/arm/sunxi/sun6i_a31_codec.c
89
#define MIC1AMPEN __BIT(28)
sys/arch/arm/sunxi/sun6i_a31_codec.c
91
#define MIC2AMPEN __BIT(24)
sys/arch/arm/sunxi/sun6i_a31_codec.c
93
#define MIC2SLT __BIT(20)
sys/arch/arm/sunxi/sun6i_a31_codec.c
94
#define LINEOUTLEN __BIT(19)
sys/arch/arm/sunxi/sun6i_a31_codec.c
95
#define LINEOUTREN __BIT(18)
sys/arch/arm/sunxi/sun6i_a31_codec.c
96
#define LINEOUTLSRC __BIT(17)
sys/arch/arm/sunxi/sun6i_a31_codec.c
97
#define LINEOUTRSRC __BIT(16)
sys/arch/arm/sunxi/sun6i_dma.c
110
#define IL2B(x) __BIT(ilog2(x))
sys/arch/arm/sunxi/sun6i_dma.c
423
mask = __BIT(bit - 1);
sys/arch/arm/sunxi/sun6i_dma.c
47
#define DMA_IRQ_EN_REG0_QUEUE_IRQ_EN(n) __BIT(n * 4 + 2)
sys/arch/arm/sunxi/sun6i_dma.c
48
#define DMA_IRQ_EN_REG0_PKG_IRQ_EN(n) __BIT(n * 4 + 1)
sys/arch/arm/sunxi/sun6i_dma.c
49
#define DMA_IRQ_EN_REG0_HLAF_IRQ_EN(n) __BIT(n * 4 + 0)
sys/arch/arm/sunxi/sun6i_dma.c
50
#define DMA_IRQ_EN_REG1_QUEUE_IRQ_EN(n) __BIT((n - 8) * 4 + 2)
sys/arch/arm/sunxi/sun6i_dma.c
51
#define DMA_IRQ_EN_REG1_PKG_IRQ_EN(n) __BIT((n - 8) * 4 + 1)
sys/arch/arm/sunxi/sun6i_dma.c
52
#define DMA_IRQ_EN_REG1_HLAF_IRQ_EN(n) __BIT((n - 8) * 4 + 0)
sys/arch/arm/sunxi/sun6i_dma.c
60
#define DMA_EN_EN __BIT(0)
sys/arch/arm/sunxi/sun6i_dma.c
62
#define DMA_PAU_PAUSE __BIT(0)
sys/arch/arm/sunxi/sun6i_dma.c
85
#define DMA_MODE_DST(m) __SHIFTIN((m), __BIT(3))
sys/arch/arm/sunxi/sun6i_dma.c
86
#define DMA_MODE_SRC(m) __SHIFTIN((m), __BIT(2))
sys/arch/arm/sunxi/sun6i_spireg.h
102
#define SPI_FSR_RB_WR __BIT(15)
sys/arch/arm/sunxi/sun6i_spireg.h
111
#define SPI_CCTL_DRS __BIT(12)
sys/arch/arm/sunxi/sun6i_spireg.h
122
#define SPI_BCC_DRM __BIT(28)
sys/arch/arm/sunxi/sun6i_spireg.h
35
#define SPI_GCR_SRST __BIT(31)
sys/arch/arm/sunxi/sun6i_spireg.h
36
#define SPI_GCR_TP_EN __BIT(7)
sys/arch/arm/sunxi/sun6i_spireg.h
37
#define SPI_GCR_MODE __BIT(1)
sys/arch/arm/sunxi/sun6i_spireg.h
40
#define SPI_GCR_EN __BIT(0)
sys/arch/arm/sunxi/sun6i_spireg.h
43
#define SPI_TCR_XCH __BIT(31)
sys/arch/arm/sunxi/sun6i_spireg.h
44
#define SPI_TCR_SDDM __BIT(14)
sys/arch/arm/sunxi/sun6i_spireg.h
45
#define SPI_TCR_SDM __BIT(13)
sys/arch/arm/sunxi/sun6i_spireg.h
46
#define SPI_TCR_FBS __BIT(12)
sys/arch/arm/sunxi/sun6i_spireg.h
47
#define SPI_TCR_SDC __BIT(11)
sys/arch/arm/sunxi/sun6i_spireg.h
48
#define SPI_TCR_RPSM __BIT(10)
sys/arch/arm/sunxi/sun6i_spireg.h
49
#define SPI_TCR_DDB __BIT(9)
sys/arch/arm/sunxi/sun6i_spireg.h
50
#define SPI_TCR_DHB __BIT(8)
sys/arch/arm/sunxi/sun6i_spireg.h
51
#define SPI_TCR_SS_LEVEL __BIT(7)
sys/arch/arm/sunxi/sun6i_spireg.h
52
#define SPI_TCR_SS_OWNER __BIT(6)
sys/arch/arm/sunxi/sun6i_spireg.h
54
#define SPI_TCR_SSCTL __BIT(3)
sys/arch/arm/sunxi/sun6i_spireg.h
55
#define SPI_TCR_SPOL __BIT(2)
sys/arch/arm/sunxi/sun6i_spireg.h
56
#define SPI_TCR_CPOL __BIT(1)
sys/arch/arm/sunxi/sun6i_spireg.h
57
#define SPI_TCR_CPHA __BIT(0)
sys/arch/arm/sunxi/sun6i_spireg.h
60
#define SPI_IER_SS_INT_EN __BIT(13)
sys/arch/arm/sunxi/sun6i_spireg.h
61
#define SPI_IER_TC_INT_EN __BIT(12)
sys/arch/arm/sunxi/sun6i_spireg.h
62
#define SPI_IER_TF_UDR_INT_EN __BIT(11)
sys/arch/arm/sunxi/sun6i_spireg.h
63
#define SPI_IER_TF_OVF_INT_EN __BIT(10)
sys/arch/arm/sunxi/sun6i_spireg.h
64
#define SPI_IER_RF_UDR_INT_EN __BIT(9)
sys/arch/arm/sunxi/sun6i_spireg.h
65
#define SPI_IER_RF_OVF_INT_EN __BIT(8)
sys/arch/arm/sunxi/sun6i_spireg.h
66
#define SPI_IER_TF_FUL_INT_EN __BIT(6)
sys/arch/arm/sunxi/sun6i_spireg.h
67
#define SPI_IER_TX_EMP_INT_EN __BIT(5)
sys/arch/arm/sunxi/sun6i_spireg.h
68
#define SPI_IER_TX_ERQ_INT_EN __BIT(4)
sys/arch/arm/sunxi/sun6i_spireg.h
69
#define SPI_IER_RF_FUL_INT_EN __BIT(2)
sys/arch/arm/sunxi/sun6i_spireg.h
70
#define SPI_IER_RX_EMP_INT_EN __BIT(1)
sys/arch/arm/sunxi/sun6i_spireg.h
71
#define SPI_IER_RF_RDY_INT_EN __BIT(0)
sys/arch/arm/sunxi/sun6i_spireg.h
74
#define SPI_ISR_SSI __BIT(13)
sys/arch/arm/sunxi/sun6i_spireg.h
75
#define SPI_ISR_TC __BIT(12)
sys/arch/arm/sunxi/sun6i_spireg.h
76
#define SPI_ISR_TF_UDF __BIT(11)
sys/arch/arm/sunxi/sun6i_spireg.h
77
#define SPI_ISR_TF_OVF __BIT(10)
sys/arch/arm/sunxi/sun6i_spireg.h
78
#define SPI_ISR_RX_UDF __BIT(9)
sys/arch/arm/sunxi/sun6i_spireg.h
79
#define SPI_ISR_RX_OVF __BIT(8)
sys/arch/arm/sunxi/sun6i_spireg.h
80
#define SPI_ISR_TX_FULL __BIT(6)
sys/arch/arm/sunxi/sun6i_spireg.h
81
#define SPI_ISR_TX_EMP __BIT(5)
sys/arch/arm/sunxi/sun6i_spireg.h
82
#define SPI_ISR_TX_READY __BIT(4)
sys/arch/arm/sunxi/sun6i_spireg.h
83
#define SPI_ISR_RX_FULL __BIT(2)
sys/arch/arm/sunxi/sun6i_spireg.h
84
#define SPI_ISR_RX_EMP __BIT(1)
sys/arch/arm/sunxi/sun6i_spireg.h
85
#define SPI_ISR_RX_RDY __BIT(0)
sys/arch/arm/sunxi/sun6i_spireg.h
88
#define SPI_FCR_TX_FIFO_RST __BIT(31)
sys/arch/arm/sunxi/sun6i_spireg.h
89
#define SPI_FCR_TF_TEST __BIT(30)
sys/arch/arm/sunxi/sun6i_spireg.h
90
#define SPI_FCR_TF_DRQ_EN __BIT(24)
sys/arch/arm/sunxi/sun6i_spireg.h
92
#define SPI_FCR_RF_RST __BIT(15)
sys/arch/arm/sunxi/sun6i_spireg.h
93
#define SPI_FCR_RF_TEST __BIT(14)
sys/arch/arm/sunxi/sun6i_spireg.h
94
#define SPI_FCR_RX_DMA_MODE __BIT(9)
sys/arch/arm/sunxi/sun6i_spireg.h
95
#define SPI_FCR_RF_DRQ_EN __BIT(8)
sys/arch/arm/sunxi/sun6i_spireg.h
99
#define SPI_FSR_TB_WR __BIT(31)
sys/arch/arm/sunxi/sun8i_a83t_ccu.c
183
.u.nkmp.p = __BIT(16),
sys/arch/arm/sunxi/sun8i_a83t_ccu.c
184
.u.nkmp.enable = __BIT(31),
sys/arch/arm/sunxi/sun8i_a83t_ccu.c
188
.u.nkmp.lock = __BIT(0), /* PLL_STABLE_STATUS_REG */
sys/arch/arm/sunxi/sun8i_a83t_ccu.c
204
.u.nkmp.p = __BIT(16),
sys/arch/arm/sunxi/sun8i_a83t_ccu.c
205
.u.nkmp.enable = __BIT(31),
sys/arch/arm/sunxi/sun8i_a83t_ccu.c
209
.u.nkmp.lock = __BIT(1), /* PLL_STABLE_STATUS_REG */
sys/arch/arm/sunxi/sun8i_a83t_ccu.c
221
__BIT(18), /* m */
sys/arch/arm/sunxi/sun8i_a83t_ccu.c
222
__BIT(16), /* p */
sys/arch/arm/sunxi/sun8i_a83t_ccu.c
223
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_a83t_ccu.c
229
__BIT(3), /* prediv_sel */
sys/arch/arm/sunxi/sun8i_a83t_ccu.c
237
__BIT(1), /* prediv_sel */
sys/arch/arm/sunxi/sun8i_a83t_ccu.c
257
SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
sys/arch/arm/sunxi/sun8i_a83t_ccu.c
260
SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
sys/arch/arm/sunxi/sun8i_a83t_ccu.c
263
SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
sys/arch/arm/sunxi/sun8i_a83t_ccu.c
49
#define Cx_CPUX_CLK_SRC_SEL(cluster) __BIT(12 + (cluster) * 16)
sys/arch/arm/sunxi/sun8i_a83t_ccu.c
59
#define SDMMC2_CLK_MODE_SELECT __BIT(30)
sys/arch/arm/sunxi/sun8i_codec.c
102
#define DAC_DIG_CTRL_ENDA __BIT(15)
sys/arch/arm/sunxi/sun8i_codec.c
46
#define AIF1CLK_ENA __BIT(11)
sys/arch/arm/sunxi/sun8i_codec.c
49
#define SYSCLK_ENA __BIT(3)
sys/arch/arm/sunxi/sun8i_codec.c
50
#define SYSCLK_SRC __BIT(0)
sys/arch/arm/sunxi/sun8i_codec.c
54
#define MOD_AIF1 __BIT(15)
sys/arch/arm/sunxi/sun8i_codec.c
55
#define MOD_ADC __BIT(3)
sys/arch/arm/sunxi/sun8i_codec.c
56
#define MOD_DAC __BIT(2)
sys/arch/arm/sunxi/sun8i_codec.c
63
#define AIF1_MSTR_MOD __BIT(15)
sys/arch/arm/sunxi/sun8i_codec.c
64
#define AIF1_BCLK_INV __BIT(14)
sys/arch/arm/sunxi/sun8i_codec.c
65
#define AIF1_LRCK_INV __BIT(13)
sys/arch/arm/sunxi/sun8i_codec.c
80
#define AIF1_DAC0L_ENA __BIT(15)
sys/arch/arm/sunxi/sun8i_codec.c
81
#define AIF1_DAC0R_ENA __BIT(14)
sys/arch/arm/sunxi/sun8i_codec.c
84
#define ADC_DIG_CTRL_ENAD __BIT(15)
sys/arch/arm/sunxi/sun8i_codec.c
88
#define HMIC_CTRL1_JACK_IN_IRQ_EN __BIT(4)
sys/arch/arm/sunxi/sun8i_codec.c
89
#define HMIC_CTRL1_JACK_OUT_IRQ_EN __BIT(3)
sys/arch/arm/sunxi/sun8i_codec.c
90
#define HMIC_CTRL1_MIC_DET_IRQ_EN __BIT(0)
sys/arch/arm/sunxi/sun8i_codec.c
96
#define HMIC_STS_MIC_PRESENT __BIT(6)
sys/arch/arm/sunxi/sun8i_codec.c
97
#define HMIC_STS_JACK_DET_OIRQ __BIT(4)
sys/arch/arm/sunxi/sun8i_codec.c
98
#define HMIC_STS_JACK_DET_IIRQ __BIT(3)
sys/arch/arm/sunxi/sun8i_codec.c
99
#define HMIC_STS_MIC_DET_ST __BIT(0)
sys/arch/arm/sunxi/sun8i_crypto.c
170
#define TASK_KEY __BIT(0)
sys/arch/arm/sunxi/sun8i_crypto.c
171
#define TASK_IV __BIT(1)
sys/arch/arm/sunxi/sun8i_crypto.c
172
#define TASK_CTR __BIT(2)
sys/arch/arm/sunxi/sun8i_crypto.c
173
#define TASK_SRC __BIT(3)
sys/arch/arm/sunxi/sun8i_crypto.c
174
#define TASK_BYTES __BIT(4) /* datalen is in bytes, not words */
sys/arch/arm/sunxi/sun8i_crypto.h
109
#define SUN8I_CRYPTO_CTR_RSA_CLK_EN __BIT(3)
sys/arch/arm/sunxi/sun8i_crypto.h
113
#define SUN8I_CRYPTO_ICR_INTR_EN_CHAN(n) (__BIT(0) << (n))
sys/arch/arm/sunxi/sun8i_crypto.h
116
#define SUN8I_CRYPTO_ISR_DONE_CHAN(n) (__BIT(0) << (n))
sys/arch/arm/sunxi/sun8i_crypto.h
118
#define SUN8I_CRYPTO_TLR_LOAD __BIT(0)
sys/arch/arm/sunxi/sun8i_crypto.h
124
#define SUN8I_CRYPTO_ESR_CHAN_ALGNOTSUP __BIT(0)
sys/arch/arm/sunxi/sun8i_crypto.h
125
#define SUN8I_CRYPTO_ESR_CHAN_DATALENERR __BIT(1)
sys/arch/arm/sunxi/sun8i_crypto.h
126
#define SUN8I_CRYPTO_ESR_CHAN_KEYSRAMERR __BIT(2)
sys/arch/arm/sunxi/sun8i_crypto.h
40
#define SUN8I_CRYPTO_TDQC_INTR_EN __BIT(31)
sys/arch/arm/sunxi/sun8i_crypto.h
41
#define SUN8I_CRYPTO_TDQC_IV_MODE __BIT(16) /* MD5/SHA-1/SHA-2 IV */
sys/arch/arm/sunxi/sun8i_crypto.h
44
#define SUN8I_CRYPTO_TDQC_HMAC_PT_LAST __BIT(15)
sys/arch/arm/sunxi/sun8i_crypto.h
45
#define SUN8I_CRYPTO_TDQC_OP_DIR __BIT(8)
sys/arch/arm/sunxi/sun8i_crypto.h
69
#define SUN8I_CRYPTO_TDQS_AES_CTS_LAST __BIT(16)
sys/arch/arm/sunxi/sun8i_h3_ccu.c
251
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
252
__BIT(28), /* lock */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
262
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
272
__BIT(24), /* div_en */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
273
__BIT(25), /* frac_sel */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
277
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
286
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
287
__BIT(28), /* lock */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
296
__BIT(24), /* div_en */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
297
__BIT(25), /* frac_sel */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
301
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
307
__BIT(3), /* prediv_sel */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
315
__BIT(1), /* prediv_sel */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
339
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
346
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
353
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
357
SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
sys/arch/arm/sunxi/sun8i_h3_ccu.c
364
SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
sys/arch/arm/sunxi/sun8i_h3_ccu.c
371
SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
sys/arch/arm/sunxi/sun8i_h3_ccu.c
383
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
390
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
400
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_h3_ccu.c
410
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_h3_codec.c
45
#define H3_AC_PR_RST __BIT(28)
sys/arch/arm/sunxi/sun8i_h3_codec.c
46
#define H3_AC_PR_RW __BIT(24)
sys/arch/arm/sunxi/sun8i_h3_codec.c
52
#define H3_LOMIXSC_LDAC __BIT(1)
sys/arch/arm/sunxi/sun8i_h3_codec.c
54
#define H3_ROMIXSC_RDAC __BIT(1)
sys/arch/arm/sunxi/sun8i_h3_codec.c
56
#define H3_DACAREN __BIT(7)
sys/arch/arm/sunxi/sun8i_h3_codec.c
57
#define H3_DACALEN __BIT(6)
sys/arch/arm/sunxi/sun8i_h3_codec.c
58
#define H3_RMIXEN __BIT(5)
sys/arch/arm/sunxi/sun8i_h3_codec.c
59
#define H3_LMIXEN __BIT(4)
sys/arch/arm/sunxi/sun8i_h3_codec.c
66
#define H3_LINEOUTEN __BIT(7)
sys/arch/arm/sunxi/sun8i_h3_codec.c
70
#define H3_LINEOUT_LSEL __BIT(3)
sys/arch/arm/sunxi/sun8i_h3_codec.c
71
#define H3_LINEOUT_RSEL __BIT(2)
sys/arch/arm/sunxi/sun8i_h3_codec.c
74
#define H3_ADCMIXSC_MIC1 __BIT(6)
sys/arch/arm/sunxi/sun8i_h3_codec.c
75
#define H3_ADCMIXSC_MIC2 __BIT(5)
sys/arch/arm/sunxi/sun8i_h3_codec.c
76
#define H3_ADCMIXSC_LINEIN __BIT(2)
sys/arch/arm/sunxi/sun8i_h3_codec.c
79
#define H3_ADCREN __BIT(7)
sys/arch/arm/sunxi/sun8i_h3_codec.c
80
#define H3_ADCLEN __BIT(6)
sys/arch/arm/sunxi/sun8i_h3_r_ccu.c
73
__BIT(2), /* prediv_sel */
sys/arch/arm/sunxi/sun8i_v3s_ccu.c
213
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_v3s_ccu.c
214
__BIT(28), /* lock */
sys/arch/arm/sunxi/sun8i_v3s_ccu.c
224
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_v3s_ccu.c
234
__BIT(24), /* div_en */
sys/arch/arm/sunxi/sun8i_v3s_ccu.c
235
__BIT(25), /* frac_sel */
sys/arch/arm/sunxi/sun8i_v3s_ccu.c
239
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_v3s_ccu.c
248
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_v3s_ccu.c
249
__BIT(28), /* lock */
sys/arch/arm/sunxi/sun8i_v3s_ccu.c
256
__BIT(3), /* prediv_sel */
sys/arch/arm/sunxi/sun8i_v3s_ccu.c
264
__BIT(1), /* prediv_sel */
sys/arch/arm/sunxi/sun8i_v3s_ccu.c
284
SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
sys/arch/arm/sunxi/sun8i_v3s_ccu.c
291
SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
sys/arch/arm/sunxi/sun8i_v3s_ccu.c
298
SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
sys/arch/arm/sunxi/sun8i_v3s_ccu.c
310
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_v3s_ccu.c
320
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun8i_v3s_codec.c
46
#define V3S_PR_RST __BIT(28)
sys/arch/arm/sunxi/sun8i_v3s_codec.c
47
#define V3S_PR_RW __BIT(24)
sys/arch/arm/sunxi/sun8i_v3s_codec.c
56
#define V3S_LMIXMUTE_LDAC __BIT(1)
sys/arch/arm/sunxi/sun8i_v3s_codec.c
58
#define V3S_RMIXMUTE_RDAC __BIT(1)
sys/arch/arm/sunxi/sun8i_v3s_codec.c
60
#define V3S_DACAREN __BIT(7)
sys/arch/arm/sunxi/sun8i_v3s_codec.c
61
#define V3S_DACALEN __BIT(6)
sys/arch/arm/sunxi/sun8i_v3s_codec.c
62
#define V3S_RMIXEN __BIT(5)
sys/arch/arm/sunxi/sun8i_v3s_codec.c
63
#define V3S_LMIXEN __BIT(4)
sys/arch/arm/sunxi/sun8i_v3s_codec.c
64
#define V3S_RHPPAMUTE __BIT(3)
sys/arch/arm/sunxi/sun8i_v3s_codec.c
65
#define V3S_LHPPAMUTE __BIT(2)
sys/arch/arm/sunxi/sun8i_v3s_codec.c
69
#define V3S_HPPAEN __BIT(7)
sys/arch/arm/sunxi/sun8i_v3s_codec.c
72
#define V3S_ADCMIXMUTE_MIC __BIT(6)
sys/arch/arm/sunxi/sun8i_v3s_codec.c
75
#define V3S_ADCREN __BIT(7)
sys/arch/arm/sunxi/sun8i_v3s_codec.c
76
#define V3S_ADCLEN __BIT(6)
sys/arch/arm/sunxi/sun9i_a80_ccu.c
185
.u.nkmp.p = __BIT(16),
sys/arch/arm/sunxi/sun9i_a80_ccu.c
186
.u.nkmp.enable = __BIT(31),
sys/arch/arm/sunxi/sun9i_a80_ccu.c
190
.u.nkmp.lock = __BIT(1), /* PLL_STABLE_STATUS_REG */
sys/arch/arm/sunxi/sun9i_a80_ccu.c
206
.u.nkmp.p = __BIT(16),
sys/arch/arm/sunxi/sun9i_a80_ccu.c
207
.u.nkmp.enable = __BIT(31),
sys/arch/arm/sunxi/sun9i_a80_ccu.c
211
.u.nkmp.lock = __BIT(1), /* PLL_STABLE_STATUS_REG */
sys/arch/arm/sunxi/sun9i_a80_ccu.c
222
__BIT(16), /* k */
sys/arch/arm/sunxi/sun9i_a80_ccu.c
224
__BIT(18), /* p */
sys/arch/arm/sunxi/sun9i_a80_ccu.c
225
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun9i_a80_ccu.c
230
__BIT(16), /* k */
sys/arch/arm/sunxi/sun9i_a80_ccu.c
232
__BIT(18), /* p */
sys/arch/arm/sunxi/sun9i_a80_ccu.c
233
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun9i_a80_ccu.c
263
__BIT(24), /* sel */
sys/arch/arm/sunxi/sun9i_a80_ccu.c
270
__BIT(24), /* sel */
sys/arch/arm/sunxi/sun9i_a80_ccu.c
279
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun9i_a80_ccu.c
290
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun9i_a80_ccu.c
301
__BIT(31), /* enable */
sys/arch/arm/sunxi/sun9i_a80_ccu.c
49
#define CPU_CLK_SRC_SELECT(cluster) __BIT((cluster) * 8)
sys/arch/arm/sunxi/sun9i_a80_usbphy.c
44
#define EHCI_HS_FORCE __BIT(20)
sys/arch/arm/sunxi/sun9i_a80_usbphy.c
45
#define HSIC_CONNECT_DET __BIT(17)
sys/arch/arm/sunxi/sun9i_a80_usbphy.c
46
#define HSIC_CONNECT_INT __BIT(16)
sys/arch/arm/sunxi/sun9i_a80_usbphy.c
47
#define AHB_INCR16 __BIT(11)
sys/arch/arm/sunxi/sun9i_a80_usbphy.c
48
#define AHB_INCR8 __BIT(10)
sys/arch/arm/sunxi/sun9i_a80_usbphy.c
49
#define AHB_INCR4 __BIT(9)
sys/arch/arm/sunxi/sun9i_a80_usbphy.c
50
#define AHB_INCRX_ALIGN __BIT(8)
sys/arch/arm/sunxi/sun9i_a80_usbphy.c
51
#define HSIC __BIT(1)
sys/arch/arm/sunxi/sun9i_a80_usbphy.c
52
#define ULPI_BYPASS __BIT(0)
sys/arch/arm/sunxi/sunxi_can.h
109
#define SUNXI_CAN_TXBUF0_EFF __BIT(7)
sys/arch/arm/sunxi/sunxi_can.h
110
#define SUNXI_CAN_TXBUF0_RTR __BIT(6)
sys/arch/arm/sunxi/sunxi_can.h
34
#define SUNXI_CAN_MODSEL_SLEEP __BIT(4)
sys/arch/arm/sunxi/sunxi_can.h
35
#define SUNXI_CAN_MODSEL_ACP_FLT_MOD __BIT(3)
sys/arch/arm/sunxi/sunxi_can.h
36
#define SUNXI_CAN_MODSEL_LB_MOD __BIT(2)
sys/arch/arm/sunxi/sunxi_can.h
37
#define SUNXI_CAN_MODSEL_LST_ONLY __BIT(1)
sys/arch/arm/sunxi/sunxi_can.h
38
#define SUNXI_CAN_MODSEL_RST __BIT(0)
sys/arch/arm/sunxi/sunxi_can.h
42
#define SUNXI_CAN_CMD_BUS_OFF __BIT(5)
sys/arch/arm/sunxi/sunxi_can.h
43
#define SUNXI_CAN_CMD_SELF_REQ __BIT(4)
sys/arch/arm/sunxi/sunxi_can.h
44
#define SUNXI_CAN_CMD_CLR_OR __BIT(3)
sys/arch/arm/sunxi/sunxi_can.h
45
#define SUNXI_CAN_CMD_REL_RX_BUF __BIT(2)
sys/arch/arm/sunxi/sunxi_can.h
46
#define SUNXI_CAN_CMD_ABT_REQ __BIT(1)
sys/arch/arm/sunxi/sunxi_can.h
47
#define SUNXI_CAN_CMD_TANS_REQ __BIT(0)
sys/arch/arm/sunxi/sunxi_can.h
59
#define SUNXI_CAN_STA_BUS __BIT(7)
sys/arch/arm/sunxi/sunxi_can.h
60
#define SUNXI_CAN_STA_ERR __BIT(6)
sys/arch/arm/sunxi/sunxi_can.h
61
#define SUNXI_CAN_STA_TX __BIT(5)
sys/arch/arm/sunxi/sunxi_can.h
62
#define SUNXI_CAN_STA_RX __BIT(4)
sys/arch/arm/sunxi/sunxi_can.h
63
#define SUNXI_CAN_STA_TX_OVER __BIT(3)
sys/arch/arm/sunxi/sunxi_can.h
64
#define SUNXI_CAN_STA_TX_RDY __BIT(2)
sys/arch/arm/sunxi/sunxi_can.h
65
#define SUNXI_CAN_STA_DATA_OR __BIT(1)
sys/arch/arm/sunxi/sunxi_can.h
66
#define SUNXI_CAN_STA_RX_RDY __BIT(0)
sys/arch/arm/sunxi/sunxi_can.h
70
#define SUNXI_CAN_INT_BERR __BIT(7)
sys/arch/arm/sunxi/sunxi_can.h
71
#define SUNXI_CAN_INT_ARB_LOST __BIT(6)
sys/arch/arm/sunxi/sunxi_can.h
72
#define SUNXI_CAN_INT_ERR_PASSIVE __BIT(5)
sys/arch/arm/sunxi/sunxi_can.h
73
#define SUNXI_CAN_INT_WAKEUP __BIT(4)
sys/arch/arm/sunxi/sunxi_can.h
74
#define SUNXI_CAN_INT_DATA_OR __BIT(3)
sys/arch/arm/sunxi/sunxi_can.h
75
#define SUNXI_CAN_INT_ERR __BIT(2)
sys/arch/arm/sunxi/sunxi_can.h
76
#define SUNXI_CAN_INT_TX_FLAG __BIT(1)
sys/arch/arm/sunxi/sunxi_can.h
77
#define SUNXI_CAN_INT_RX_FLAG __BIT(0)
sys/arch/arm/sunxi/sunxi_can.h
84
#define SUNXI_CAN_BUS_TIME_SAM __BIT(23)
sys/arch/arm/sunxi/sunxi_ccu.h
112
#define SUNXI_CCU_NKMP_DIVIDE_BY_TWO __BIT(0)
sys/arch/arm/sunxi/sunxi_ccu.h
113
#define SUNXI_CCU_NKMP_FACTOR_N_EXACT __BIT(1)
sys/arch/arm/sunxi/sunxi_ccu.h
114
#define SUNXI_CCU_NKMP_SCALE_CLOCK __BIT(2)
sys/arch/arm/sunxi/sunxi_ccu.h
115
#define SUNXI_CCU_NKMP_FACTOR_P_POW2 __BIT(3)
sys/arch/arm/sunxi/sunxi_ccu.h
116
#define SUNXI_CCU_NKMP_FACTOR_N_ZERO_IS_ONE __BIT(4)
sys/arch/arm/sunxi/sunxi_ccu.h
117
#define SUNXI_CCU_NKMP_FACTOR_P_X4 __BIT(5)
sys/arch/arm/sunxi/sunxi_ccu.h
165
#define SUNXI_CCU_NM_POWER_OF_TWO __BIT(0)
sys/arch/arm/sunxi/sunxi_ccu.h
166
#define SUNXI_CCU_NM_ROUND_DOWN __BIT(1)
sys/arch/arm/sunxi/sunxi_ccu.h
167
#define SUNXI_CCU_NM_DIVIDE_BY_TWO __BIT(2)
sys/arch/arm/sunxi/sunxi_ccu.h
210
#define SUNXI_CCU_DIV_POWER_OF_TWO __BIT(0)
sys/arch/arm/sunxi/sunxi_ccu.h
211
#define SUNXI_CCU_DIV_ZERO_IS_ONE __BIT(1)
sys/arch/arm/sunxi/sunxi_ccu.h
212
#define SUNXI_CCU_DIV_TIMES_TWO __BIT(2)
sys/arch/arm/sunxi/sunxi_ccu.h
213
#define SUNXI_CCU_DIV_SET_RATE_PARENT __BIT(3)
sys/arch/arm/sunxi/sunxi_ccu.h
274
#define SUNXI_CCU_PREDIV_POWER_OF_TWO __BIT(0)
sys/arch/arm/sunxi/sunxi_ccu.h
275
#define SUNXI_CCU_PREDIV_DIVIDE_BY_TWO __BIT(1)
sys/arch/arm/sunxi/sunxi_ccu.h
376
#define SUNXI_CCU_FRACTIONAL_PLUSONE __BIT(0)
sys/arch/arm/sunxi/sunxi_ccu.h
377
#define SUNXI_CCU_FRACTIONAL_SET_ENABLE __BIT(1)
sys/arch/arm/sunxi/sunxi_ccu.h
50
.mask = __BIT(_bit), \
sys/arch/arm/sunxi/sunxi_ccu.h
88
.u.gate.mask = __BIT(_bit), \
sys/arch/arm/sunxi/sunxi_ccu_prediv.c
83
if (prediv->prediv_sel & __BIT(sel))
sys/arch/arm/sunxi/sunxi_codec.c
70
#define DAC_FIFOC_MONO_EN __BIT(6)
sys/arch/arm/sunxi/sunxi_codec.c
71
#define DAC_FIFOC_TX_BITS __BIT(5)
sys/arch/arm/sunxi/sunxi_codec.c
72
#define DAC_FIFOC_DRQ_EN __BIT(4)
sys/arch/arm/sunxi/sunxi_codec.c
73
#define DAC_FIFOC_FIFO_FLUSH __BIT(0)
sys/arch/arm/sunxi/sunxi_codec.c
79
#define ADC_FIFOC_EN_AD __BIT(28)
sys/arch/arm/sunxi/sunxi_codec.c
80
#define ADC_FIFOC_RX_FIFO_MODE __BIT(24)
sys/arch/arm/sunxi/sunxi_codec.c
82
#define ADC_FIFOC_MONO_EN __BIT(7)
sys/arch/arm/sunxi/sunxi_codec.c
83
#define ADC_FIFOC_RX_BITS __BIT(6)
sys/arch/arm/sunxi/sunxi_codec.c
84
#define ADC_FIFOC_DRQ_EN __BIT(4)
sys/arch/arm/sunxi/sunxi_codec.c
85
#define ADC_FIFOC_FIFO_FLUSH __BIT(0)
sys/arch/arm/sunxi/sunxi_debereg.h
114
#define SUNXI_DEBE_ATTCTL1_LAY_BRSWAPEN __BIT(2)
sys/arch/arm/sunxi/sunxi_debereg.h
119
#define SUNXI_DEBE_REGBUFFCTL_REGAUTOLOAD_DIS __BIT(1)
sys/arch/arm/sunxi/sunxi_debereg.h
120
#define SUNXI_DEBE_REGBUFFCTL_REGLOADCTL __BIT(0)
sys/arch/arm/sunxi/sunxi_debereg.h
70
#define SUNXI_DEBE_MODCTL_LINE_SEL __BIT(29)
sys/arch/arm/sunxi/sunxi_debereg.h
71
#define SUNXI_DEBE_MODCTL_ITLMOD_EN __BIT(28)
sys/arch/arm/sunxi/sunxi_debereg.h
77
#define SUNXI_DEBE_MODCTL_OSCA_EN __BIT(17)
sys/arch/arm/sunxi/sunxi_debereg.h
78
#define SUNXI_DEBE_MODCTL_HWC_EN __BIT(16)
sys/arch/arm/sunxi/sunxi_debereg.h
79
#define SUNXI_DEBE_MODCTL_LAY3_EN __BIT(11)
sys/arch/arm/sunxi/sunxi_debereg.h
80
#define SUNXI_DEBE_MODCTL_LAY2_EN __BIT(10)
sys/arch/arm/sunxi/sunxi_debereg.h
81
#define SUNXI_DEBE_MODCTL_LAY1_EN __BIT(9)
sys/arch/arm/sunxi/sunxi_debereg.h
82
#define SUNXI_DEBE_MODCTL_LAY0_EN __BIT(8)
sys/arch/arm/sunxi/sunxi_debereg.h
83
#define SUNXI_DEBE_MODCTL_START_CTL __BIT(1)
sys/arch/arm/sunxi/sunxi_debereg.h
84
#define SUNXI_DEBE_MODCTL_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_debereg.h
88
#define SUNXI_DEBE_ATTCTL0_PREMUL __BIT(21,20)
sys/arch/arm/sunxi/sunxi_debereg.h
90
#define SUNXI_DEBE_ATTCTL0_LAY_PIPESEL __BIT(15)
sys/arch/arm/sunxi/sunxi_debereg.h
92
#define SUNXI_DEBE_ATTCTL0_LAY_VDOSEL __BIT(4)
sys/arch/arm/sunxi/sunxi_debereg.h
93
#define SUNXI_DEBE_ATTCTL0_LAY_YUVEN __BIT(2)
sys/arch/arm/sunxi/sunxi_debereg.h
94
#define SUNXI_DEBE_ATTCTL0_LAY_VDOEN __BIT(1)
sys/arch/arm/sunxi/sunxi_debereg.h
95
#define SUNXI_DEBE_ATTCTL0_LAY_GLBALPHAEN __BIT(0)
sys/arch/arm/sunxi/sunxi_gates.c
43
#define GATE_MASK(index) __BIT((index) % 32)
sys/arch/arm/sunxi/sunxi_gmacclk.c
42
#define GMAC_CLK_PIT __BIT(2)
sys/arch/arm/sunxi/sunxi_gpio.c
1055
GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(pin_def->eint_bank), __BIT(pin_def->eint_num));
sys/arch/arm/sunxi/sunxi_gpio.c
1056
GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(pin_def->eint_bank), __BIT(pin_def->eint_num));
sys/arch/arm/sunxi/sunxi_gpio.c
389
const uint32_t data_mask = __BIT(pin_def->pin);
sys/arch/arm/sunxi/sunxi_gpio.c
417
const uint32_t data_mask = __BIT(pin_def->pin);
sys/arch/arm/sunxi/sunxi_gpio.c
457
status &= ~__BIT(bit - 1);
sys/arch/arm/sunxi/sunxi_gpio.c
517
val |= __BIT(eint->eint_num);
sys/arch/arm/sunxi/sunxi_gpio.c
536
val &= ~__BIT(eint->eint_num);
sys/arch/arm/sunxi/sunxi_gpio.c
538
GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(eint->eint_bank), __BIT(eint->eint_num));
sys/arch/arm/sunxi/sunxi_gpio.c
77
#define SUNXI_GPIO_INT_DEBOUNCE_CLK_SEL __BIT(0)
sys/arch/arm/sunxi/sunxi_gpio.c
898
const uint32_t data_mask = __BIT(pin_def->pin);
sys/arch/arm/sunxi/sunxi_gpio.c
917
const uint32_t data_mask = __BIT(pin_def->pin);
sys/arch/arm/sunxi/sunxi_hdmiphy.c
55
#define ANA_CFG1_ENRCAL __BIT(19)
sys/arch/arm/sunxi/sunxi_hdmiphy.c
56
#define ANA_CFG1_ENCALOG __BIT(18)
sys/arch/arm/sunxi/sunxi_hdmiphy.c
57
#define ANA_CFG1_TMDSCLK_EN __BIT(16)
sys/arch/arm/sunxi/sunxi_hdmiphy.c
61
#define ANA_CFG1_CKEN __BIT(3)
sys/arch/arm/sunxi/sunxi_hdmiphy.c
62
#define ANA_CFG1_LDOEN __BIT(2)
sys/arch/arm/sunxi/sunxi_hdmiphy.c
63
#define ANA_CFG1_ENVBS __BIT(1)
sys/arch/arm/sunxi/sunxi_hdmiphy.c
64
#define ANA_CFG1_ENBI __BIT(0)
sys/arch/arm/sunxi/sunxi_hdmiphy.c
70
#define ANA_CFG3_REG_SDAEN __BIT(2)
sys/arch/arm/sunxi/sunxi_hdmiphy.c
71
#define ANA_CFG3_REG_SCLEN __BIT(0)
sys/arch/arm/sunxi/sunxi_hdmiphy.c
74
#define PLL_CFG1_REG_OD1 __BIT(31)
sys/arch/arm/sunxi/sunxi_hdmiphy.c
75
#define PLL_CFG1_REG_OD0 __BIT(30)
sys/arch/arm/sunxi/sunxi_hdmiphy.c
76
#define PLL_CFG1_CKIN_SEL __BIT(26)
sys/arch/arm/sunxi/sunxi_hdmiphy.c
77
#define PLL_CFG1_PLLEN __BIT(25)
sys/arch/arm/sunxi/sunxi_hdmiphy.c
86
#define ANA_STS_HPDO __BIT(19)
sys/arch/arm/sunxi/sunxi_hdmiphy.c
88
#define ANA_STS_RCALEND2D __BIT(7)
sys/arch/arm/sunxi/sunxi_hdmiphy.c
92
#define CEC_CONTROL_SEL __BIT(7)
sys/arch/arm/sunxi/sunxi_hdmiphy.c
93
#define CEC_INPUT_DATA __BIT(1)
sys/arch/arm/sunxi/sunxi_hdmiphy.c
94
#define CEC_OUTPUT_DATA __BIT(0)
sys/arch/arm/sunxi/sunxi_hdmireg.h
124
#define SUNXI_HDMI_VID_TIMING_4_VSYNC_ACTIVE_SEL __BIT(1)
sys/arch/arm/sunxi/sunxi_hdmireg.h
125
#define SUNXI_HDMI_VID_TIMING_4_HSYNC_ACTIVE_SEL __BIT(0)
sys/arch/arm/sunxi/sunxi_hdmireg.h
127
#define SUNXI_HDMI_PAD_CTRL0_BIAS __BIT(31)
sys/arch/arm/sunxi/sunxi_hdmireg.h
128
#define SUNXI_HDMI_PAD_CTRL0_LDOCEN __BIT(30)
sys/arch/arm/sunxi/sunxi_hdmireg.h
129
#define SUNXI_HDMI_PAD_CTRL0_LD0DEN __BIT(29)
sys/arch/arm/sunxi/sunxi_hdmireg.h
130
#define SUNXI_HDMI_PAD_CTRL0_PWENC __BIT(28)
sys/arch/arm/sunxi/sunxi_hdmireg.h
131
#define SUNXI_HDMI_PAD_CTRL0_PWEND __BIT(27)
sys/arch/arm/sunxi/sunxi_hdmireg.h
132
#define SUNXI_HDMI_PAD_CTRL0_PWENG __BIT(26)
sys/arch/arm/sunxi/sunxi_hdmireg.h
133
#define SUNXI_HDMI_PAD_CTRL0_CKEN __BIT(25)
sys/arch/arm/sunxi/sunxi_hdmireg.h
134
#define SUNXI_HDMI_PAD_CTRL0_SEN __BIT(24)
sys/arch/arm/sunxi/sunxi_hdmireg.h
135
#define SUNXI_HDMI_PAD_CTRL0_TXEN __BIT(23)
sys/arch/arm/sunxi/sunxi_hdmireg.h
136
#define SUNXI_HDMI_PAD_CTRL0_AUTOSYNC_DIS __BIT(22)
sys/arch/arm/sunxi/sunxi_hdmireg.h
137
#define SUNXI_HDMI_PAD_CTRL0_LSB_MSB __BIT(21)
sys/arch/arm/sunxi/sunxi_hdmireg.h
139
#define SUNXI_HDMI_PAD_CTRL1_AMP_OPT __BIT(23)
sys/arch/arm/sunxi/sunxi_hdmireg.h
140
#define SUNXI_HDMI_PAD_CTRL1_AMPCK_OPT __BIT(22)
sys/arch/arm/sunxi/sunxi_hdmireg.h
141
#define SUNXI_HDMI_PAD_CTRL1_DMP_OPT __BIT(21)
sys/arch/arm/sunxi/sunxi_hdmireg.h
142
#define SUNXI_HDMI_PAD_CTRL1_EMP_OPT __BIT(20)
sys/arch/arm/sunxi/sunxi_hdmireg.h
143
#define SUNXI_HDMI_PAD_CTRL1_EMPCK_OPT __BIT(19)
sys/arch/arm/sunxi/sunxi_hdmireg.h
144
#define SUNXI_HDMI_PAD_CTRL1_PWSCK __BIT(18)
sys/arch/arm/sunxi/sunxi_hdmireg.h
145
#define SUNXI_HDMI_PAD_CTRL1_PWSDT __BIT(17)
sys/arch/arm/sunxi/sunxi_hdmireg.h
146
#define SUNXI_HDMI_PAD_CTRL1_REG_CSMPS __BIT(16)
sys/arch/arm/sunxi/sunxi_hdmireg.h
147
#define SUNXI_HDMI_PAD_CTRL1_REG_DEN __BIT(15)
sys/arch/arm/sunxi/sunxi_hdmireg.h
148
#define SUNXI_HDMI_PAD_CTRL1_REG_DENCK __BIT(14)
sys/arch/arm/sunxi/sunxi_hdmireg.h
149
#define SUNXI_HDMI_PAD_CTRL1_REG_PLRCK __BIT(13)
sys/arch/arm/sunxi/sunxi_hdmireg.h
156
#define SUNXI_HDMI_PLL_CTRL_PLL_EN __BIT(31)
sys/arch/arm/sunxi/sunxi_hdmireg.h
157
#define SUNXI_HDMI_PLL_CTRL_BWS __BIT(30)
sys/arch/arm/sunxi/sunxi_hdmireg.h
158
#define SUNXI_HDMI_PLL_CTRL_HV_IS_33 __BIT(29)
sys/arch/arm/sunxi/sunxi_hdmireg.h
159
#define SUNXI_HDMI_PLL_CTRL_LDO1_EN __BIT(28)
sys/arch/arm/sunxi/sunxi_hdmireg.h
160
#define SUNXI_HDMI_PLL_CTRL_LDO2_EN __BIT(27)
sys/arch/arm/sunxi/sunxi_hdmireg.h
161
#define SUNXI_HDMI_PLL_CTRL_S6P25_7P5 __BIT(26)
sys/arch/arm/sunxi/sunxi_hdmireg.h
162
#define SUNXI_HDMI_PLL_CTRL_SDIV2 __BIT(25)
sys/arch/arm/sunxi/sunxi_hdmireg.h
163
#define SUNXI_HDMI_PLL_CTRL_SINT_FRAC __BIT(24)
sys/arch/arm/sunxi/sunxi_hdmireg.h
164
#define SUNXI_HDMI_PLL_CTRL_VCO_GAIN_EN __BIT(23)
sys/arch/arm/sunxi/sunxi_hdmireg.h
172
#define SUNXI_HDMI_AUD_CTRL_EN __BIT(31)
sys/arch/arm/sunxi/sunxi_hdmireg.h
173
#define SUNXI_HDMI_AUD_CTRL_RST __BIT(30)
sys/arch/arm/sunxi/sunxi_hdmireg.h
175
#define SUNXI_HDMI_ADMA_CTRL_SRC_DMA_MODE __BIT(31)
sys/arch/arm/sunxi/sunxi_hdmireg.h
177
#define SUNXI_HDMI_ADMA_CTRL_SRC_DMA_SAMPLE_RATE __BIT(19)
sys/arch/arm/sunxi/sunxi_hdmireg.h
178
#define SUNXI_HDMI_ADMA_CTRL_SRC_SAMPLE_LAYOUT __BIT(18)
sys/arch/arm/sunxi/sunxi_hdmireg.h
180
#define SUNXI_HDMI_ADMA_CTRL_FIFO_CLEAR __BIT(15)
sys/arch/arm/sunxi/sunxi_hdmireg.h
181
#define SUNXI_HDMI_ADMA_CTRL_DATA_SEL __BIT(0)
sys/arch/arm/sunxi/sunxi_hdmireg.h
183
#define SUNXI_HDMI_AUD_FMT_SRC_SEL __BIT(31)
sys/arch/arm/sunxi/sunxi_hdmireg.h
185
#define SUNXI_HDMI_AUD_FMT_DSD_FMT __BIT(4)
sys/arch/arm/sunxi/sunxi_hdmireg.h
186
#define SUNXI_HDMI_AUD_FMT_LAYOUT __BIT(3)
sys/arch/arm/sunxi/sunxi_hdmireg.h
204
#define SUNXI_HDMI_AUD_CH_STATUS0_CP __BIT(2)
sys/arch/arm/sunxi/sunxi_hdmireg.h
205
#define SUNXI_HDMI_AUD_CH_STATUS0_DATA_TYPE __BIT(1)
sys/arch/arm/sunxi/sunxi_hdmireg.h
206
#define SUNXI_HDMI_AUD_CH_STATUS0_APP_TYPE __BIT(0)
sys/arch/arm/sunxi/sunxi_hdmireg.h
211
#define SUNXI_HDMI_AUD_CH_STATUS1_WORD_LEN_MAX __BIT(0)
sys/arch/arm/sunxi/sunxi_hdmireg.h
213
#define SUNXI_HDMI_DDC_CTRL_EN __BIT(31)
sys/arch/arm/sunxi/sunxi_hdmireg.h
214
#define SUNXI_HDMI_DDC_CTRL_ACCESS_CMD_START __BIT(30)
sys/arch/arm/sunxi/sunxi_hdmireg.h
215
#define SUNXI_HDMI_DDC_CTRL_FIFO_DIR __BIT(8)
sys/arch/arm/sunxi/sunxi_hdmireg.h
218
#define SUNXI_HDMI_DDC_CTRL_SW_RST __BIT(0)
sys/arch/arm/sunxi/sunxi_hdmireg.h
225
#define SUNXI_HDMI_DDC_INT_STATUS_CLEAR __BIT(8)
sys/arch/arm/sunxi/sunxi_hdmireg.h
226
#define SUNXI_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OP __BIT(7)
sys/arch/arm/sunxi/sunxi_hdmireg.h
227
#define SUNXI_HDMI_DDC_INT_STATUS_RX_UNDERFLOW __BIT(6)
sys/arch/arm/sunxi/sunxi_hdmireg.h
228
#define SUNXI_HDMI_DDC_INT_STATUS_TX_OVERFLOW __BIT(5)
sys/arch/arm/sunxi/sunxi_hdmireg.h
229
#define SUNXI_HDMI_DDC_INT_STATUS_FIFO_REQ __BIT(4)
sys/arch/arm/sunxi/sunxi_hdmireg.h
230
#define SUNXI_HDMI_DDC_INT_STATUS_ARB_ERR __BIT(3)
sys/arch/arm/sunxi/sunxi_hdmireg.h
231
#define SUNXI_HDMI_DDC_INT_STATUS_ACK_ERR __BIT(2)
sys/arch/arm/sunxi/sunxi_hdmireg.h
232
#define SUNXI_HDMI_DDC_INT_STATUS_BUS_ERR __BIT(1)
sys/arch/arm/sunxi/sunxi_hdmireg.h
233
#define SUNXI_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE __BIT(0)
sys/arch/arm/sunxi/sunxi_hdmireg.h
235
#define SUNXI_HDMI_DDC_FIFO_CTRL_ADDR_CLEAR __BIT(31)
sys/arch/arm/sunxi/sunxi_hdmireg.h
236
#define SUNXI_HDMI_DDC_FIFO_CTRL_REQUEST_EN __BIT(8)
sys/arch/arm/sunxi/sunxi_hdmireg.h
240
#define SUNXI_HDMI_DDC_FIFO_STATUS_REQ_READY __BIT(7)
sys/arch/arm/sunxi/sunxi_hdmireg.h
241
#define SUNXI_HDMI_DDC_FIFO_STATUS_FULL __BIT(6)
sys/arch/arm/sunxi/sunxi_hdmireg.h
242
#define SUNXI_HDMI_DDC_FIFO_STATUS_EMPTY __BIT(5)
sys/arch/arm/sunxi/sunxi_hdmireg.h
270
#define SUNXI_A31_HDMI_DDC_CTRL_SW_RST __BIT(31)
sys/arch/arm/sunxi/sunxi_hdmireg.h
271
#define SUNXI_A31_HDMI_DDC_CTRL_ACCESS_CMD_START __BIT(27)
sys/arch/arm/sunxi/sunxi_hdmireg.h
272
#define SUNXI_A31_HDMI_DDC_CTRL_SDA_PAD_PULLDOWN __BIT(7)
sys/arch/arm/sunxi/sunxi_hdmireg.h
273
#define SUNXI_A31_HDMI_DDC_CTRL_SDA_PAD_EN __BIT(6)
sys/arch/arm/sunxi/sunxi_hdmireg.h
274
#define SUNXI_A31_HDMI_DDC_CTRL_SCL_PAD_PULLDOWN __BIT(5)
sys/arch/arm/sunxi/sunxi_hdmireg.h
275
#define SUNXI_A31_HDMI_DDC_CTRL_SCL_PAD_EN __BIT(4)
sys/arch/arm/sunxi/sunxi_hdmireg.h
276
#define SUNXI_A31_HDMI_DDC_CTRL_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_hdmireg.h
278
#define SUNXI_A31_HDMI_DDC_EXCTRL_BUS_BUSY __BIT(10)
sys/arch/arm/sunxi/sunxi_hdmireg.h
279
#define SUNXI_A31_HDMI_DDC_EXCTRL_SCL_STATUS __BIT(9)
sys/arch/arm/sunxi/sunxi_hdmireg.h
280
#define SUNXI_A31_HDMI_DDC_EXCTRL_SDA_STATUS __BIT(8)
sys/arch/arm/sunxi/sunxi_hdmireg.h
281
#define SUNXI_A31_HDMI_DDC_EXCTRL_SEGMENT_SEL __BIT(7)
sys/arch/arm/sunxi/sunxi_hdmireg.h
282
#define SUNXI_A31_HDMI_DDC_EXCTRL_SEGMENT0_DET __BIT(6)
sys/arch/arm/sunxi/sunxi_hdmireg.h
283
#define SUNXI_A31_HDMI_DDC_EXCTRL_INIT_SEQ_MODE __BIT(5)
sys/arch/arm/sunxi/sunxi_hdmireg.h
284
#define SUNXI_A31_HDMI_DDC_EXCTRL_INIT_SEQ_EN __BIT(4)
sys/arch/arm/sunxi/sunxi_hdmireg.h
285
#define SUNXI_A31_HDMI_DDC_EXCTRL_SW_SCL __BIT(3)
sys/arch/arm/sunxi/sunxi_hdmireg.h
286
#define SUNXI_A31_HDMI_DDC_EXCTRL_SW_SCL_EN __BIT(2)
sys/arch/arm/sunxi/sunxi_hdmireg.h
287
#define SUNXI_A31_HDMI_DDC_EXCTRL_SW_SDA __BIT(1)
sys/arch/arm/sunxi/sunxi_hdmireg.h
288
#define SUNXI_A31_HDMI_DDC_EXCTRL_SW_SDA_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_hdmireg.h
293
#define SUNXI_A31_HDMI_DDC_FIFO_CTRL_RST __BIT(15)
sys/arch/arm/sunxi/sunxi_hdmireg.h
83
#define SUNXI_HDMI_CTRL_MODULE_EN __BIT(31)
sys/arch/arm/sunxi/sunxi_hdmireg.h
84
#define SUNXI_HDMI_CTRL_HDCP_EN __BIT(30)
sys/arch/arm/sunxi/sunxi_hdmireg.h
85
#define SUNXI_HDMI_CTRL_CLR_AVMUTE __BIT(1)
sys/arch/arm/sunxi/sunxi_hdmireg.h
86
#define SUNXI_HDMI_CTRL_SET_AVMUTE __BIT(0)
sys/arch/arm/sunxi/sunxi_hdmireg.h
88
#define SUNXI_HDMI_HPD_HOTPLUG_DET __BIT(0)
sys/arch/arm/sunxi/sunxi_hdmireg.h
90
#define SUNXI_HDMI_VID_CTRL_VIDEO_EN __BIT(31)
sys/arch/arm/sunxi/sunxi_hdmireg.h
91
#define SUNXI_HDMI_VID_CTRL_HDMI_MODE __BIT(30)
sys/arch/arm/sunxi/sunxi_hdmireg.h
94
#define SUNXI_HDMI_VID_CTRL_SRC_SEL __BIT(5)
sys/arch/arm/sunxi/sunxi_hdmireg.h
97
#define SUNXI_HDMI_VID_CTRL_OUTPUT_FMT __BIT(4)
sys/arch/arm/sunxi/sunxi_hstimer.c
40
#define HS_TMR_IRQ_EN(n) __BIT(n)
sys/arch/arm/sunxi/sunxi_hstimer.c
42
#define HS_TMR_STAS_PEND(n) __BIT(n)
sys/arch/arm/sunxi/sunxi_hstimer.c
44
#define HS_TMR0_CTRL_MODE __BIT(7)
sys/arch/arm/sunxi/sunxi_hstimer.c
46
#define HS_TMR0_CTRL_RELOAD __BIT(1)
sys/arch/arm/sunxi/sunxi_hstimer.c
47
#define HS_TMR0_CTRL_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_hstimer.c
53
#define HS_TMR1_CTRL_MODE __BIT(7)
sys/arch/arm/sunxi/sunxi_hstimer.c
55
#define HS_TMR1_CTRL_RELOAD __BIT(1)
sys/arch/arm/sunxi/sunxi_hstimer.c
56
#define HS_TMR1_CTRL_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_hstimer.c
62
#define HS_TMR2_CTRL_MODE __BIT(7)
sys/arch/arm/sunxi/sunxi_hstimer.c
64
#define HS_TMR2_CTRL_RELOAD __BIT(1)
sys/arch/arm/sunxi/sunxi_hstimer.c
65
#define HS_TMR2_CTRL_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_hstimer.c
71
#define HS_TMR3_CTRL_MODE __BIT(7)
sys/arch/arm/sunxi/sunxi_hstimer.c
73
#define HS_TMR3_CTRL_RELOAD __BIT(1)
sys/arch/arm/sunxi/sunxi_hstimer.c
74
#define HS_TMR3_CTRL_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_i2s.c
101
#define DA_CHCFG_TX_SLOT_HIZ __BIT(9)
sys/arch/arm/sunxi/sunxi_i2s.c
102
#define DA_CHCFG_TXN_STATE __BIT(8)
sys/arch/arm/sunxi/sunxi_i2s.c
49
#define DA_CTL_BCLK_OUT __BIT(18) /* sun8i */
sys/arch/arm/sunxi/sunxi_i2s.c
50
#define DA_CLK_LRCK_OUT __BIT(17) /* sun8i */
sys/arch/arm/sunxi/sunxi_i2s.c
51
#define DA_CTL_SDO_EN __BIT(8)
sys/arch/arm/sunxi/sunxi_i2s.c
52
#define DA_CTL_MS __BIT(5) /* sun4i */
sys/arch/arm/sunxi/sunxi_i2s.c
53
#define DA_CTL_PCM __BIT(4) /* sun4i */
sys/arch/arm/sunxi/sunxi_i2s.c
58
#define DA_CTL_TXEN __BIT(2)
sys/arch/arm/sunxi/sunxi_i2s.c
59
#define DA_CTL_RXEN __BIT(1)
sys/arch/arm/sunxi/sunxi_i2s.c
60
#define DA_CTL_GEN __BIT(0)
sys/arch/arm/sunxi/sunxi_i2s.c
63
#define DA_FAT0_LRCP __BIT(7)
sys/arch/arm/sunxi/sunxi_i2s.c
66
#define DA_FAT0_BCP __BIT(6)
sys/arch/arm/sunxi/sunxi_i2s.c
79
#define DA_FCTL_HUB_EN __BIT(31)
sys/arch/arm/sunxi/sunxi_i2s.c
80
#define DA_FCTL_FTX __BIT(25)
sys/arch/arm/sunxi/sunxi_i2s.c
81
#define DA_FCTL_FRX __BIT(24)
sys/arch/arm/sunxi/sunxi_i2s.c
82
#define DA_FCTL_TXIM __BIT(2)
sys/arch/arm/sunxi/sunxi_i2s.c
86
#define DA_INT_TX_DRQ __BIT(7)
sys/arch/arm/sunxi/sunxi_i2s.c
87
#define DA_INT_RX_DRQ __BIT(3)
sys/arch/arm/sunxi/sunxi_i2s.c
90
#define DA_CLKD_MCLKO_EN_SUN8I __BIT(8)
sys/arch/arm/sunxi/sunxi_i2s.c
91
#define DA_CLKD_MCLKO_EN_SUN4I __BIT(7)
sys/arch/arm/sunxi/sunxi_intc.c
201
const uint32_t oldipl_mask = __BIT(oldipl);
sys/arch/arm/sunxi/sunxi_intc.c
54
#define INTC_PROTECT_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_lcdc.c
50
#define TCON_GCTL_TCON_EN __BIT(31)
sys/arch/arm/sunxi/sunxi_lcdc.c
51
#define TCON_GCTL_GAMMA_EN __BIT(30)
sys/arch/arm/sunxi/sunxi_lcdc.c
52
#define TCON_GCTL_IO_MAP_SEL __BIT(0)
sys/arch/arm/sunxi/sunxi_lcdc.c
54
#define TCON_GINT0_TCON0_VB_INT_EN __BIT(31)
sys/arch/arm/sunxi/sunxi_lcdc.c
55
#define TCON_GINT0_TCON1_VB_INT_EN __BIT(30)
sys/arch/arm/sunxi/sunxi_lcdc.c
56
#define TCON_GINT0_TCON0_VB_INT_FLAG __BIT(15)
sys/arch/arm/sunxi/sunxi_lcdc.c
57
#define TCON_GINT0_TCON1_VB_INT_FLAG __BIT(14)
sys/arch/arm/sunxi/sunxi_lcdc.c
62
#define TCON0_CTL_TCON0_EN __BIT(31)
sys/arch/arm/sunxi/sunxi_lcdc.c
73
#define TCON0_IO_POL_IO_OUTPUT_SEL __BIT(31)
sys/arch/arm/sunxi/sunxi_lcdc.c
75
#define TCON0_IO_POL_IO3_INV __BIT(27)
sys/arch/arm/sunxi/sunxi_lcdc.c
76
#define TCON0_IO_POL_IO2_INV __BIT(26)
sys/arch/arm/sunxi/sunxi_lcdc.c
77
#define TCON0_IO_POL_IO1_INV __BIT(25)
sys/arch/arm/sunxi/sunxi_lcdc.c
78
#define TCON0_IO_POL_IO0_INV __BIT(24)
sys/arch/arm/sunxi/sunxi_lcdc.c
83
#define TCON1_CTL_TCON1_EN __BIT(31)
sys/arch/arm/sunxi/sunxi_lcdc.c
93
#define TCON1_IO_POL_IO3_INV __BIT(27)
sys/arch/arm/sunxi/sunxi_lcdc.c
94
#define TCON1_IO_POL_IO2_INV __BIT(26)
sys/arch/arm/sunxi/sunxi_lcdc.c
95
#define TCON1_IO_POL_IO1_INV __BIT(25)
sys/arch/arm/sunxi/sunxi_lcdc.c
96
#define TCON1_IO_POL_IO0_INV __BIT(24)
sys/arch/arm/sunxi/sunxi_lradc.h
42
#define AWIN_LRADC_CTRL_HOLD_EN __BIT(6)
sys/arch/arm/sunxi/sunxi_lradc.h
53
#define AWIN_LRADC_CTRL_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_lradc.h
56
#define AWIN_LRADC_INT_KEYUP1 __BIT(12)
sys/arch/arm/sunxi/sunxi_lradc.h
57
#define AWIN_LRADC_INT_ALREADYHOLD1 __BIT(11)
sys/arch/arm/sunxi/sunxi_lradc.h
58
#define AWIN_LRADC_INT_HOLD1 __BIT(10)
sys/arch/arm/sunxi/sunxi_lradc.h
59
#define AWIN_LRADC_INT_KEY1 __BIT(9)
sys/arch/arm/sunxi/sunxi_lradc.h
60
#define AWIN_LRADC_INT_DATA1 __BIT(8)
sys/arch/arm/sunxi/sunxi_lradc.h
61
#define AWIN_LRADC_INT_KEYUP0 __BIT(4)
sys/arch/arm/sunxi/sunxi_lradc.h
62
#define AWIN_LRADC_INT_ALREADYHOLD0 __BIT(3)
sys/arch/arm/sunxi/sunxi_lradc.h
63
#define AWIN_LRADC_INT_HOLD0 __BIT(2)
sys/arch/arm/sunxi/sunxi_lradc.h
64
#define AWIN_LRADC_INT_KEY0 __BIT(1)
sys/arch/arm/sunxi/sunxi_lradc.h
65
#define AWIN_LRADC_INT_DATA0 __BIT(0)
sys/arch/arm/sunxi/sunxi_mc_smp.c
123
val &= ~__BIT(cpu);
sys/arch/arm/sunxi/sunxi_mc_smp.c
129
val &= ~__BIT(cpu);
sys/arch/arm/sunxi/sunxi_mc_smp.c
136
val &= ~__BIT(cpu);
sys/arch/arm/sunxi/sunxi_mc_smp.c
158
val &= ~__BIT(4);
sys/arch/arm/sunxi/sunxi_mc_smp.c
160
val &= ~__BIT(cpu);
sys/arch/arm/sunxi/sunxi_mc_smp.c
161
val &= ~__BIT(0); /* cluster power gate */
sys/arch/arm/sunxi/sunxi_mc_smp.c
163
val &= ~__BIT(cpu);
sys/arch/arm/sunxi/sunxi_mc_smp.c
164
val &= ~__BIT(4); /* cluster power gate */
sys/arch/arm/sunxi/sunxi_mc_smp.c
170
val |= __BIT(cpu);
sys/arch/arm/sunxi/sunxi_mc_smp.c
175
val |= __BIT(cpu);
sys/arch/arm/sunxi/sunxi_mc_smp.c
182
val |= __BIT(cpu);
sys/arch/arm/sunxi/sunxi_mc_smp.c
70
#define CPUXCFG_CL_RST_SOC_DBG_RST __BIT(24)
sys/arch/arm/sunxi/sunxi_mc_smp.c
71
#define CPUXCFG_CL_RST_ETM_RST(cpu) __BIT(20 + (cpu))
sys/arch/arm/sunxi/sunxi_mc_smp.c
72
#define CPUXCFG_CL_RST_DBG_RST(cpu) __BIT(16 + (cpu))
sys/arch/arm/sunxi/sunxi_mc_smp.c
73
#define CPUXCFG_CL_RST_H_RST __BIT(12)
sys/arch/arm/sunxi/sunxi_mc_smp.c
74
#define CPUXCFG_CL_RST_L2_RST __BIT(8)
sys/arch/arm/sunxi/sunxi_mc_smp.c
75
#define CPUXCFG_CL_RST_CX_RST(cpu) __BIT(4 + (cpu))
sys/arch/arm/sunxi/sunxi_mc_smp.c
78
#define CPUXCFG_CL_CTRL1_ACINACTM __BIT(0)
sys/arch/arm/sunxi/sunxi_mixer.c
113
#define OVL_V_ATTCTL_LAY0_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_mixer.c
143
#define OVL_UI_ATTR_CTL_LAY_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_mixer.c
156
#define VS_CTRL_COEF_SWITCH_EN __BIT(4)
sys/arch/arm/sunxi/sunxi_mixer.c
157
#define VS_CTRL_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_mixer.c
182
#define CSC_BYPASS_DISABLE __BIT(0)
sys/arch/arm/sunxi/sunxi_mixer.c
68
#define GLB_CTL_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_mixer.c
71
#define GLB_DBUFFER_DOUBLE_BUFFER_RDY __BIT(0)
sys/arch/arm/sunxi/sunxi_mixer.c
76
#define BLD_FILL_COLOR_CTL_P3_EN __BIT(11)
sys/arch/arm/sunxi/sunxi_mixer.c
77
#define BLD_FILL_COLOR_CTL_P2_EN __BIT(10)
sys/arch/arm/sunxi/sunxi_mixer.c
78
#define BLD_FILL_COLOR_CTL_P1_EN __BIT(9)
sys/arch/arm/sunxi/sunxi_mixer.c
79
#define BLD_FILL_COLOR_CTL_P0_EN __BIT(8)
sys/arch/arm/sunxi/sunxi_mixer.c
80
#define BLD_FILL_COLOR_CTL_P3_FCEN __BIT(3)
sys/arch/arm/sunxi/sunxi_mixer.c
81
#define BLD_FILL_COLOR_CTL_P2_FCEN __BIT(2)
sys/arch/arm/sunxi/sunxi_mixer.c
82
#define BLD_FILL_COLOR_CTL_P1_FCEN __BIT(1)
sys/arch/arm/sunxi/sunxi_mixer.c
83
#define BLD_FILL_COLOR_CTL_P0_FCEN __BIT(0)
sys/arch/arm/sunxi/sunxi_mixer.c
97
#define OVL_V_ATTCTL_VIDEO_UI_SEL __BIT(15)
sys/arch/arm/sunxi/sunxi_mmc.c
54
if (sunxi_mmc_debug & __BIT(device_unit(dev))) \
sys/arch/arm/sunxi/sunxi_mmc.h
100
#define SUNXI_MMC_CMD_CHECK_RSP_CRC __BIT(8)
sys/arch/arm/sunxi/sunxi_mmc.h
101
#define SUNXI_MMC_CMD_LONG_RSP __BIT(7)
sys/arch/arm/sunxi/sunxi_mmc.h
102
#define SUNXI_MMC_CMD_RSP_EXP __BIT(6)
sys/arch/arm/sunxi/sunxi_mmc.h
103
#define SUNXI_MMC_INT_CARD_REMOVE __BIT(31)
sys/arch/arm/sunxi/sunxi_mmc.h
104
#define SUNXI_MMC_INT_CARD_INSERT __BIT(30)
sys/arch/arm/sunxi/sunxi_mmc.h
105
#define SUNXI_MMC_INT_SDIO_INT __BIT(16)
sys/arch/arm/sunxi/sunxi_mmc.h
106
#define SUNXI_MMC_INT_END_BIT_ERR __BIT(15)
sys/arch/arm/sunxi/sunxi_mmc.h
107
#define SUNXI_MMC_INT_AUTO_CMD_DONE __BIT(14)
sys/arch/arm/sunxi/sunxi_mmc.h
108
#define SUNXI_MMC_INT_START_BIT_ERR __BIT(13)
sys/arch/arm/sunxi/sunxi_mmc.h
109
#define SUNXI_MMC_INT_HW_LOCKED __BIT(12)
sys/arch/arm/sunxi/sunxi_mmc.h
110
#define SUNXI_MMC_INT_FIFO_RUN_ERR __BIT(11)
sys/arch/arm/sunxi/sunxi_mmc.h
111
#define SUNXI_MMC_INT_VOL_CHG_DONE __BIT(10)
sys/arch/arm/sunxi/sunxi_mmc.h
112
#define SUNXI_MMC_INT_DATA_STARVE __BIT(10)
sys/arch/arm/sunxi/sunxi_mmc.h
113
#define SUNXI_MMC_INT_BOOT_START __BIT(9)
sys/arch/arm/sunxi/sunxi_mmc.h
114
#define SUNXI_MMC_INT_DATA_TIMEOUT __BIT(9)
sys/arch/arm/sunxi/sunxi_mmc.h
115
#define SUNXI_MMC_INT_ACK_RCV __BIT(8)
sys/arch/arm/sunxi/sunxi_mmc.h
116
#define SUNXI_MMC_INT_RESP_TIMEOUT __BIT(8)
sys/arch/arm/sunxi/sunxi_mmc.h
117
#define SUNXI_MMC_INT_DATA_CRC_ERR __BIT(7)
sys/arch/arm/sunxi/sunxi_mmc.h
118
#define SUNXI_MMC_INT_RESP_CRC_ERR __BIT(6)
sys/arch/arm/sunxi/sunxi_mmc.h
119
#define SUNXI_MMC_INT_RX_DATA_REQ __BIT(5)
sys/arch/arm/sunxi/sunxi_mmc.h
120
#define SUNXI_MMC_INT_TX_DATA_REQ __BIT(4)
sys/arch/arm/sunxi/sunxi_mmc.h
121
#define SUNXI_MMC_INT_DATA_OVER __BIT(3)
sys/arch/arm/sunxi/sunxi_mmc.h
122
#define SUNXI_MMC_INT_CMD_DONE __BIT(2)
sys/arch/arm/sunxi/sunxi_mmc.h
123
#define SUNXI_MMC_INT_RESP_ERR __BIT(1)
sys/arch/arm/sunxi/sunxi_mmc.h
129
#define SUNXI_MMC_STATUS_DMAREQ __BIT(31)
sys/arch/arm/sunxi/sunxi_mmc.h
130
#define SUNXI_MMC_STATUS_DATA_FSM_BUSY __BIT(10)
sys/arch/arm/sunxi/sunxi_mmc.h
131
#define SUNXI_MMC_STATUS_CARD_DATA_BUSY __BIT(9)
sys/arch/arm/sunxi/sunxi_mmc.h
132
#define SUNXI_MMC_STATUS_CARD_PRESENT __BIT(8)
sys/arch/arm/sunxi/sunxi_mmc.h
133
#define SUNXI_MMC_STATUS_FIFO_FULL __BIT(3)
sys/arch/arm/sunxi/sunxi_mmc.h
134
#define SUNXI_MMC_STATUS_FIFO_EMPTY __BIT(2)
sys/arch/arm/sunxi/sunxi_mmc.h
135
#define SUNXI_MMC_STATUS_TXWL_FLAG __BIT(1)
sys/arch/arm/sunxi/sunxi_mmc.h
136
#define SUNXI_MMC_STATUS_RXWL_FLAG __BIT(0)
sys/arch/arm/sunxi/sunxi_mmc.h
137
#define SUNXI_MMC_FUNCSEL_CEATA_DEV_INTEN __BIT(10)
sys/arch/arm/sunxi/sunxi_mmc.h
138
#define SUNXI_MMC_FUNCSEL_SEND_AUTO_STOP_CCSD __BIT(9)
sys/arch/arm/sunxi/sunxi_mmc.h
139
#define SUNXI_MMC_FUNCSEL_SEND_CCSD __BIT(8)
sys/arch/arm/sunxi/sunxi_mmc.h
140
#define SUNXI_MMC_FUNCSEL_ABT_RD_DATA __BIT(2)
sys/arch/arm/sunxi/sunxi_mmc.h
141
#define SUNXI_MMC_FUNCSEL_SDIO_RD_WAIT __BIT(1)
sys/arch/arm/sunxi/sunxi_mmc.h
142
#define SUNXI_MMC_FUNCSEL_SEND_IRQ_RSP __BIT(0)
sys/arch/arm/sunxi/sunxi_mmc.h
143
#define SUNXI_MMC_NTSR_MODE_SELECT __BIT(31)
sys/arch/arm/sunxi/sunxi_mmc.h
146
#define SUNXI_MMC_DMAC_REFETCH_DES __BIT(31)
sys/arch/arm/sunxi/sunxi_mmc.h
147
#define SUNXI_MMC_DMAC_IDMA_ON __BIT(7)
sys/arch/arm/sunxi/sunxi_mmc.h
148
#define SUNXI_MMC_DMAC_FIX_BURST __BIT(1)
sys/arch/arm/sunxi/sunxi_mmc.h
149
#define SUNXI_MMC_DMAC_SOFTRESET __BIT(0)
sys/arch/arm/sunxi/sunxi_mmc.h
150
#define SUNXI_MMC_IDST_HOST_ABT __BIT(10)
sys/arch/arm/sunxi/sunxi_mmc.h
151
#define SUNXI_MMC_IDST_ABNORMAL_INT_SUM __BIT(9)
sys/arch/arm/sunxi/sunxi_mmc.h
152
#define SUNXI_MMC_IDST_NORMAL_INT_SUM __BIT(8)
sys/arch/arm/sunxi/sunxi_mmc.h
153
#define SUNXI_MMC_IDST_CARD_ERR_SUM __BIT(5)
sys/arch/arm/sunxi/sunxi_mmc.h
154
#define SUNXI_MMC_IDST_DES_INVALID __BIT(4)
sys/arch/arm/sunxi/sunxi_mmc.h
155
#define SUNXI_MMC_IDST_FATAL_BUS_ERR __BIT(2)
sys/arch/arm/sunxi/sunxi_mmc.h
156
#define SUNXI_MMC_IDST_RECEIVE_INT __BIT(1)
sys/arch/arm/sunxi/sunxi_mmc.h
157
#define SUNXI_MMC_IDST_TRANSMIT_INT __BIT(0)
sys/arch/arm/sunxi/sunxi_mmc.h
163
#define SUNXI_MMC_IDMA_CONFIG_DIC __BIT(1)
sys/arch/arm/sunxi/sunxi_mmc.h
164
#define SUNXI_MMC_IDMA_CONFIG_LD __BIT(2)
sys/arch/arm/sunxi/sunxi_mmc.h
165
#define SUNXI_MMC_IDMA_CONFIG_FD __BIT(3)
sys/arch/arm/sunxi/sunxi_mmc.h
166
#define SUNXI_MMC_IDMA_CONFIG_CH __BIT(4)
sys/arch/arm/sunxi/sunxi_mmc.h
167
#define SUNXI_MMC_IDMA_CONFIG_ER __BIT(5)
sys/arch/arm/sunxi/sunxi_mmc.h
168
#define SUNXI_MMC_IDMA_CONFIG_CES __BIT(30)
sys/arch/arm/sunxi/sunxi_mmc.h
169
#define SUNXI_MMC_IDMA_CONFIG_OWN __BIT(31)
sys/arch/arm/sunxi/sunxi_mmc.h
170
#define SUNXI_MMC_SAMP_DL_SW_EN __BIT(7)
sys/arch/arm/sunxi/sunxi_mmc.h
174
#define SUNXI_MMC_IDMA_CONFIG_DIC __BIT(1)
sys/arch/arm/sunxi/sunxi_mmc.h
175
#define SUNXI_MMC_IDMA_CONFIG_LD __BIT(2)
sys/arch/arm/sunxi/sunxi_mmc.h
176
#define SUNXI_MMC_IDMA_CONFIG_FD __BIT(3)
sys/arch/arm/sunxi/sunxi_mmc.h
177
#define SUNXI_MMC_IDMA_CONFIG_CH __BIT(4)
sys/arch/arm/sunxi/sunxi_mmc.h
178
#define SUNXI_MMC_IDMA_CONFIG_ER __BIT(5)
sys/arch/arm/sunxi/sunxi_mmc.h
179
#define SUNXI_MMC_IDMA_CONFIG_CES __BIT(30)
sys/arch/arm/sunxi/sunxi_mmc.h
180
#define SUNXI_MMC_IDMA_CONFIG_OWN __BIT(31)
sys/arch/arm/sunxi/sunxi_mmc.h
64
#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB __BIT(31)
sys/arch/arm/sunxi/sunxi_mmc.h
65
#define SUNXI_MMC_GCTRL_WAIT_MEM_ACCESS_DONE __BIT(30)
sys/arch/arm/sunxi/sunxi_mmc.h
66
#define SUNXI_MMC_GCTRL_DDR_MODE __BIT(10)
sys/arch/arm/sunxi/sunxi_mmc.h
67
#define SUNXI_MMC_GCTRL_DEBOUNCEEN __BIT(8)
sys/arch/arm/sunxi/sunxi_mmc.h
68
#define SUNXI_MMC_GCTRL_DMAEN __BIT(5)
sys/arch/arm/sunxi/sunxi_mmc.h
69
#define SUNXI_MMC_GCTRL_INTEN __BIT(4)
sys/arch/arm/sunxi/sunxi_mmc.h
70
#define SUNXI_MMC_GCTRL_DMARESET __BIT(2)
sys/arch/arm/sunxi/sunxi_mmc.h
71
#define SUNXI_MMC_GCTRL_FIFORESET __BIT(1)
sys/arch/arm/sunxi/sunxi_mmc.h
72
#define SUNXI_MMC_GCTRL_SOFTRESET __BIT(0)
sys/arch/arm/sunxi/sunxi_mmc.h
76
#define SUNXI_MMC_CLKCR_MASK_DATA0 __BIT(31)
sys/arch/arm/sunxi/sunxi_mmc.h
77
#define SUNXI_MMC_CLKCR_LOWPOWERON __BIT(17)
sys/arch/arm/sunxi/sunxi_mmc.h
78
#define SUNXI_MMC_CLKCR_CARDCLKON __BIT(16)
sys/arch/arm/sunxi/sunxi_mmc.h
83
#define SUNXI_MMC_CMD_START __BIT(31)
sys/arch/arm/sunxi/sunxi_mmc.h
84
#define SUNXI_MMC_CMD_USE_HOLD_REG __BIT(29)
sys/arch/arm/sunxi/sunxi_mmc.h
85
#define SUNXI_MMC_CMD_VOL_SWITCH __BIT(28)
sys/arch/arm/sunxi/sunxi_mmc.h
86
#define SUNXI_MMC_CMD_BOOT_ABORT __BIT(27)
sys/arch/arm/sunxi/sunxi_mmc.h
87
#define SUNXI_MMC_CMD_BOOT_ACK_EXP __BIT(26)
sys/arch/arm/sunxi/sunxi_mmc.h
88
#define SUNXI_MMC_CMD_ALT_BOOT_OPT __BIT(25)
sys/arch/arm/sunxi/sunxi_mmc.h
89
#define SUNXI_MMC_CMD_ENBOOT __BIT(24)
sys/arch/arm/sunxi/sunxi_mmc.h
90
#define SUNXI_MMC_CMD_CCS_EXP __BIT(23)
sys/arch/arm/sunxi/sunxi_mmc.h
91
#define SUNXI_MMC_CMD_RD_CEATA_DEV __BIT(22)
sys/arch/arm/sunxi/sunxi_mmc.h
92
#define SUNXI_MMC_CMD_UPCLK_ONLY __BIT(21)
sys/arch/arm/sunxi/sunxi_mmc.h
93
#define SUNXI_MMC_CMD_SEND_INIT_SEQ __BIT(15)
sys/arch/arm/sunxi/sunxi_mmc.h
94
#define SUNXI_MMC_CMD_STOP_ABORT_CMD __BIT(14)
sys/arch/arm/sunxi/sunxi_mmc.h
95
#define SUNXI_MMC_CMD_WAIT_PRE_OVER __BIT(13)
sys/arch/arm/sunxi/sunxi_mmc.h
96
#define SUNXI_MMC_CMD_SEND_AUTO_STOP __BIT(12)
sys/arch/arm/sunxi/sunxi_mmc.h
97
#define SUNXI_MMC_CMD_SEQMOD __BIT(11)
sys/arch/arm/sunxi/sunxi_mmc.h
98
#define SUNXI_MMC_CMD_WRITE __BIT(10)
sys/arch/arm/sunxi/sunxi_mmc.h
99
#define SUNXI_MMC_CMD_DATA_EXP __BIT(9)
sys/arch/arm/sunxi/sunxi_nand.c
49
#define NDFC_CTL_BUS_WIDTH __BIT(2)
sys/arch/arm/sunxi/sunxi_nand.c
50
#define NDFC_CTL_RESET __BIT(1)
sys/arch/arm/sunxi/sunxi_nand.c
51
#define NDFC_CTL_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_nand.c
53
#define NDFC_ST_RB_STATE(n) __BIT(8 + (n))
sys/arch/arm/sunxi/sunxi_nand.c
54
#define NDFC_ST_CMD_FIFO_STATUS __BIT(3)
sys/arch/arm/sunxi/sunxi_nand.c
55
#define NDFC_ST_DMA_INT_FLAG __BIT(2)
sys/arch/arm/sunxi/sunxi_nand.c
56
#define NDFC_ST_CMD_INT_FLAG __BIT(1)
sys/arch/arm/sunxi/sunxi_nand.c
59
#define NDFC_INT_CMD_INT_ENABLE __BIT(1)
sys/arch/arm/sunxi/sunxi_nand.c
68
#define NDFC_CMD_DATA_METHOD __BIT(26)
sys/arch/arm/sunxi/sunxi_nand.c
69
#define NDFC_CMD_SEND_FIRST_CMD __BIT(22)
sys/arch/arm/sunxi/sunxi_nand.c
70
#define NDFC_CMD_DATA_TRANS __BIT(21)
sys/arch/arm/sunxi/sunxi_nand.c
71
#define NDFC_CMD_ACCESS_DIR __BIT(20)
sys/arch/arm/sunxi/sunxi_nand.c
72
#define NDFC_CMD_SEND_ADR __BIT(19)
sys/arch/arm/sunxi/sunxi_nmi.c
58
#define NMI_PEND_IRQ_ACK __BIT(0)
sys/arch/arm/sunxi/sunxi_nmi.c
61
#define NMI_ENABLE_IRQEN __BIT(0)
sys/arch/arm/sunxi/sunxi_platform.c
100
#define SUN9I_WDT_CFG_SYS __BIT(0)
sys/arch/arm/sunxi/sunxi_platform.c
102
#define SUN9I_WDT_MODE_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_platform.c
107
#define SUN50I_H6_WDT_CFG_SYS __BIT(0)
sys/arch/arm/sunxi/sunxi_platform.c
109
#define SUN50I_H6_WDT_MODE_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_platform.c
76
#define SUN4I_TIMER_1_CTRL_RELOAD __BIT(1)
sys/arch/arm/sunxi/sunxi_platform.c
77
#define SUN4I_TIMER_1_CTRL_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_platform.c
85
#define SUN4I_WDT_CTRL_RESTART __BIT(0)
sys/arch/arm/sunxi/sunxi_platform.c
87
#define SUN4I_WDT_MODE_RST_EN __BIT(1)
sys/arch/arm/sunxi/sunxi_platform.c
88
#define SUN4I_WDT_MODE_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_platform.c
93
#define SUN6I_WDT_CFG_SYS __BIT(0)
sys/arch/arm/sunxi/sunxi_platform.c
95
#define SUN6I_WDT_MODE_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_pwm.c
45
#define PWM0_RDY __BIT(28)
sys/arch/arm/sunxi/sunxi_pwm.c
46
#define PWM0_BYPASS __BIT(9)
sys/arch/arm/sunxi/sunxi_pwm.c
47
#define PWM_CH0_PUL_START __BIT(8)
sys/arch/arm/sunxi/sunxi_pwm.c
48
#define PWM_CHANNEL0_MODE __BIT(7)
sys/arch/arm/sunxi/sunxi_pwm.c
49
#define SCLK_CH0_GATING __BIT(6)
sys/arch/arm/sunxi/sunxi_pwm.c
50
#define PWM_CH0_ACT_STA __BIT(5)
sys/arch/arm/sunxi/sunxi_pwm.c
51
#define PWM_CH0_EN __BIT(4)
sys/arch/arm/sunxi/sunxi_resets.c
42
#define RESET_MASK(index) __BIT((index) % 32)
sys/arch/arm/sunxi/sunxi_rsb.h
33
#define RSB_CTRL_START_TRANS __BIT(7)
sys/arch/arm/sunxi/sunxi_rsb.h
34
#define RSB_CTRL_ABORT_TRANS __BIT(6)
sys/arch/arm/sunxi/sunxi_rsb.h
35
#define RSB_CTRL_GLOBAL_INT_ENB __BIT(1)
sys/arch/arm/sunxi/sunxi_rsb.h
36
#define RSB_CTRL_SOFT_RESET __BIT(0)
sys/arch/arm/sunxi/sunxi_rsb.h
41
#define RSB_INTE_LOAD_BSY_ENB __BIT(2)
sys/arch/arm/sunxi/sunxi_rsb.h
42
#define RSB_INTE_TRANS_ERR_ENB __BIT(1)
sys/arch/arm/sunxi/sunxi_rsb.h
43
#define RSB_INTE_TRANS_OVER_ENB __BIT(0)
sys/arch/arm/sunxi/sunxi_rsb.h
46
#define RSB_STAT_LOAD_BSY __BIT(2)
sys/arch/arm/sunxi/sunxi_rsb.h
47
#define RSB_STAT_TRANS_ERR __BIT(1)
sys/arch/arm/sunxi/sunxi_rsb.h
48
#define RSB_STAT_TRANS_OVER __BIT(0)
sys/arch/arm/sunxi/sunxi_rsb.h
56
#define RSB_DLEN_READ_WRITE_FLAG __BIT(4)
sys/arch/arm/sunxi/sunxi_rsb.h
61
#define RSB_LCR_SCL_STATE __BIT(5)
sys/arch/arm/sunxi/sunxi_rsb.h
62
#define RSB_LCR_SDA_STATE __BIT(4)
sys/arch/arm/sunxi/sunxi_rsb.h
63
#define RSB_LCR_SCL_CTL __BIT(3)
sys/arch/arm/sunxi/sunxi_rsb.h
64
#define RSB_LCR_SCL_CTL_EN __BIT(2)
sys/arch/arm/sunxi/sunxi_rsb.h
65
#define RSB_LCR_SDA_CTL __BIT(1)
sys/arch/arm/sunxi/sunxi_rsb.h
66
#define RSB_LCR_SDA_CTL_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_rsb.h
68
#define RSB_PMCR_PMU_INIT_SEND __BIT(31)
sys/arch/arm/sunxi/sunxi_rtc.c
109
#define SUNXI_RTC_F_HAS_VAR_PRESCALER __BIT(0)
sys/arch/arm/sunxi/sunxi_rtc.c
45
#define SUN4I_RTC_LEAP __BIT(22)
sys/arch/arm/sunxi/sunxi_rtc.c
57
#define SUN7I_RTC_LEAP __BIT(24)
sys/arch/arm/sunxi/sunxi_rtc.c
70
#define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS __BIT(15)
sys/arch/arm/sunxi/sunxi_rtc.c
71
#define SUN6I_LOSC_CTRL_ALM_DHMS_ACC __BIT(9)
sys/arch/arm/sunxi/sunxi_rtc.c
72
#define SUN6I_LOSC_CTRL_RTC_HMS_ACC __BIT(8)
sys/arch/arm/sunxi/sunxi_rtc.c
73
#define SUN6I_LOSC_CTRL_RTC_YMD_ACC __BIT(7)
sys/arch/arm/sunxi/sunxi_rtc.c
74
#define SUN6I_LOSC_CTRL_EXT_LOSC_EN __BIT(4)
sys/arch/arm/sunxi/sunxi_rtc.c
75
#define SUN6I_LOSC_CTRL_EXT_OSC __BIT(0)
sys/arch/arm/sunxi/sunxi_rtc.c
81
#define SUN6I_RTC_LEAP __BIT(22)
sys/arch/arm/sunxi/sunxi_rtc.c
93
#define SUN6I_RTC_LOSC_OUT_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_sramc.c
61
#define SUNXI_SRAMC_F_SWAP __BIT(0)
sys/arch/arm/sunxi/sunxi_sramc.c
74
.mask = __BIT(0),
sys/arch/arm/sunxi/sunxi_sramc.c
81
.mask = __BIT(24),
sys/arch/arm/sunxi/sunxi_tconreg.h
105
#define SUNXI_TCON0_LVDS_IF_EN __BIT(31)
sys/arch/arm/sunxi/sunxi_tconreg.h
106
#define SUNXI_TCON0_LVDS_IF_DUALCHAN __BIT(30)
sys/arch/arm/sunxi/sunxi_tconreg.h
107
#define SUNXI_TCON0_LVDS_IF_DIR_REV __BIT(28)
sys/arch/arm/sunxi/sunxi_tconreg.h
108
#define SUNXI_TCON0_LVDS_IF_MODE_JEIDA __BIT(27)
sys/arch/arm/sunxi/sunxi_tconreg.h
109
#define SUNXI_TCON0_LVDS_IF_18BITS __BIT(26)
sys/arch/arm/sunxi/sunxi_tconreg.h
110
#define SUNXI_TCON0_LVDS_IF_CORR_MODE1 __BIT(23)
sys/arch/arm/sunxi/sunxi_tconreg.h
112
#define SUNXI_TCON_IO_POL_IO2_INV __BIT(26)
sys/arch/arm/sunxi/sunxi_tconreg.h
113
#define SUNXI_TCON_IO_POL_PVSYNC __BIT(25)
sys/arch/arm/sunxi/sunxi_tconreg.h
114
#define SUNXI_TCON_IO_POL_PHSYNC __BIT(24)
sys/arch/arm/sunxi/sunxi_tconreg.h
116
#define SUNXI_TCON_IO_TRI_IO3 __BIT(27)
sys/arch/arm/sunxi/sunxi_tconreg.h
117
#define SUNXI_TCON_IO_TRI_IO2 __BIT(26)
sys/arch/arm/sunxi/sunxi_tconreg.h
118
#define SUNXI_TCON_IO_TRI_IO1 __BIT(25)
sys/arch/arm/sunxi/sunxi_tconreg.h
119
#define SUNXI_TCON_IO_TRI_IO0 __BIT(24)
sys/arch/arm/sunxi/sunxi_tconreg.h
75
#define SUNXI_TCON_GCTL_EN __BIT(31)
sys/arch/arm/sunxi/sunxi_tconreg.h
76
#define SUNXI_TCON_GCTL_GAMMA_EN __BIT(30)
sys/arch/arm/sunxi/sunxi_tconreg.h
77
#define SUNXI_TCON_GCTL_IO_MAP_SEL __BIT(0)
sys/arch/arm/sunxi/sunxi_tconreg.h
84
#define SUNXI_TCON0_FRM_ENABLE __BIT(31)
sys/arch/arm/sunxi/sunxi_tconreg.h
85
#define SUNXI_TCON0_FRM_R5BITS __BIT(6)
sys/arch/arm/sunxi/sunxi_tconreg.h
86
#define SUNXI_TCON0_FRM_G5BITS __BIT(5)
sys/arch/arm/sunxi/sunxi_tconreg.h
87
#define SUNXI_TCON0_FRM_B5BITS __BIT(4)
sys/arch/arm/sunxi/sunxi_tconreg.h
89
#define SUNXI_TCONx_CTL_EN __BIT(31)
sys/arch/arm/sunxi/sunxi_tconreg.h
94
#define SUNXI_TCON0_CTL_RG_SWAP __BIT(23)
sys/arch/arm/sunxi/sunxi_tconreg.h
95
#define SUNXI_TCON0_CTL_TSTV __BIT(22)
sys/arch/arm/sunxi/sunxi_tconreg.h
96
#define SUNXI_TCONx_CTL_INTERLACE_EN __BIT(20)
sys/arch/arm/sunxi/sunxi_timer.c
48
#define TMR_IRQ_EN(n) __BIT(n)
sys/arch/arm/sunxi/sunxi_timer.c
50
#define TMR_IRQ_STAS_PEND(n) __BIT(n)
sys/arch/arm/sunxi/sunxi_timer.c
52
#define TMR0_CTRL_MODE __BIT(7)
sys/arch/arm/sunxi/sunxi_timer.c
57
#define TMR0_CTRL_RELOAD __BIT(1)
sys/arch/arm/sunxi/sunxi_timer.c
58
#define TMR0_CTRL_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_timer.c
66
#define TMR2_CTRL_MODE __BIT(7)
sys/arch/arm/sunxi/sunxi_timer.c
69
#define TMR2_CTRL_RELOAD __BIT(1)
sys/arch/arm/sunxi/sunxi_timer.c
70
#define TMR2_CTRL_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_timer.c
76
#define TMR4_CTRL_RELOAD __BIT(1)
sys/arch/arm/sunxi/sunxi_timer.c
77
#define TMR4_CTRL_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_timer.c
91
#define LOSC_CTRL_OSC32K_AUTO_SWT_EN __BIT(14)
sys/arch/arm/sunxi/sunxi_timer.c
92
#define LOSC_CTRL_OSC32K_SEL __BIT(0)
sys/arch/arm/sunxi/sunxi_ts.c
53
#define TP_CTRL0_ADC_FIRST_DLY_MODE __BIT(23)
sys/arch/arm/sunxi/sunxi_ts.c
54
#define TP_CTRL0_ADC_CLK_SELECT __BIT(22)
sys/arch/arm/sunxi/sunxi_ts.c
60
#define TP_CTRL1_STYLUS_UP_DEBOUNCE_EN __BIT(9)
sys/arch/arm/sunxi/sunxi_ts.c
61
#define TP_CTRL1_TOUCH_PAN_CALI_EN __BIT(6)
sys/arch/arm/sunxi/sunxi_ts.c
62
#define TP_CTRL1_TP_DUAL_EN __BIT(5)
sys/arch/arm/sunxi/sunxi_ts.c
63
#define TP_CTRL1_TP_MODE_EN __BIT(4)
sys/arch/arm/sunxi/sunxi_ts.c
64
#define TP_CTRL1_TP_ADC_SELECT __BIT(3)
sys/arch/arm/sunxi/sunxi_ts.c
69
#define TP_CTRL2_PRE_MEA_EN __BIT(24)
sys/arch/arm/sunxi/sunxi_ts.c
72
#define TP_CTRL3_FILTER_EN __BIT(2)
sys/arch/arm/sunxi/sunxi_ts.c
75
#define TP_INT_TEMP_IRQ_EN __BIT(18)
sys/arch/arm/sunxi/sunxi_ts.c
76
#define TP_INT_OVERRUN_IRQ_EN __BIT(17)
sys/arch/arm/sunxi/sunxi_ts.c
77
#define TP_INT_DATA_IRQ_EN __BIT(16)
sys/arch/arm/sunxi/sunxi_ts.c
78
#define TP_INT_DATA_XY_CHANGE __BIT(13)
sys/arch/arm/sunxi/sunxi_ts.c
80
#define TP_INT_DATA_DRQ_EN __BIT(7)
sys/arch/arm/sunxi/sunxi_ts.c
81
#define TP_INT_FIFO_FLUSH __BIT(4)
sys/arch/arm/sunxi/sunxi_ts.c
82
#define TP_INT_UP_IRQ_EN __BIT(1)
sys/arch/arm/sunxi/sunxi_ts.c
83
#define TP_INT_DOWN_IRQ_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_ts.c
85
#define TP_FIFOCS_TEMP_IRQ_PENDING __BIT(18)
sys/arch/arm/sunxi/sunxi_ts.c
86
#define TP_FIFOCS_OVERRUN_PENDING __BIT(17)
sys/arch/arm/sunxi/sunxi_ts.c
87
#define TP_FIFOCS_DATA_PENDING __BIT(16)
sys/arch/arm/sunxi/sunxi_ts.c
89
#define TP_FIFOCS_IDLE_FLG __BIT(2)
sys/arch/arm/sunxi/sunxi_ts.c
90
#define TP_FIFOCS_UP_PENDING __BIT(1)
sys/arch/arm/sunxi/sunxi_ts.c
91
#define TP_FIFOCS_DOWN_PENDING __BIT(0)
sys/arch/arm/sunxi/sunxi_ts.c
93
#define TP_TPR_TEMP_EN __BIT(16)
sys/arch/arm/sunxi/sunxi_usb3phy.c
46
#define PCC_PIPE_CLK_OPEN __BIT(6)
sys/arch/arm/sunxi/sunxi_usb3phy.c
59
#define PEC_REF_SSP_EN __BIT(26)
sys/arch/arm/sunxi/sunxi_usb3phy.c
60
#define PEC_SSC_EN __BIT(24)
sys/arch/arm/sunxi/sunxi_usbphy.c
144
const uint32_t usbc_mask = __BIT(phy->phy_index * 2);
sys/arch/arm/sunxi/sunxi_usbphy.c
44
#define PHYCTL_ICR_ID_PULLUP __BIT(17)
sys/arch/arm/sunxi/sunxi_usbphy.c
45
#define PHYCTL_ICR_DPDM_PULLUP __BIT(16)
sys/arch/arm/sunxi/sunxi_usbphy.c
55
#define PHYCTL_DATA __BIT(7)
sys/arch/arm/sunxi/sunxi_usbphy.c
57
#define PHYCTL_OTG_ROUTE_OTG __BIT(0)
sys/arch/arm/sunxi/sunxi_usbphy.c
66
#define AHB_INCR8 __BIT(10)
sys/arch/arm/sunxi/sunxi_usbphy.c
67
#define AHB_INCR4 __BIT(9)
sys/arch/arm/sunxi/sunxi_usbphy.c
68
#define AHB_INCRX_ALIGN __BIT(8)
sys/arch/arm/sunxi/sunxi_usbphy.c
69
#define ULPI_BYPASS __BIT(0)
sys/arch/arm/sunxi/sunxi_usbphy.c
71
#define PMU_UNK_H3_CLR __BIT(1)
sys/arch/arm/sunxi/sunxi_wdt.c
49
#define SUN4I_WDT_CTRL_RSTART __BIT(0)
sys/arch/arm/sunxi/sunxi_wdt.c
52
#define SUN4I_WDT_MODE_RST_EN __BIT(1)
sys/arch/arm/sunxi/sunxi_wdt.c
53
#define SUN4I_WDT_MODE_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_wdt.c
56
#define SUN6I_WDT_IRQ_EN_EN __BIT(0)
sys/arch/arm/sunxi/sunxi_wdt.c
58
#define SUN6I_WDT_IRQ_STA_PEND __BIT(0)
sys/arch/arm/sunxi/sunxi_wdt.c
62
#define SUN6I_WDT_CTRL_RSTART __BIT(0)
sys/arch/arm/sunxi/sunxi_wdt.c
69
#define SUN6I_WDT_MODE_EN __BIT(0)
sys/arch/arm/ti/am18xx_aclk.c
69
#define AM18XX_ACLK_CFGCHIP3_ASYNC3_CLKSRC __BIT(4)
sys/arch/arm/ti/am18xx_aclk.c
70
#define AM18XX_ACLK_CFGCHIP3_ASYNC1_CLKSRC __BIT(2)
sys/arch/arm/ti/am18xx_intc.c
208
const uint32_t oldipl_mask = __BIT(old_ipl);
sys/arch/arm/ti/am18xx_pllc.c
91
#define AM18XX_PLLC_PLLCTL_PLLEN __BIT(0)
sys/arch/arm/ti/am18xx_pllc.c
92
#define AM18XX_PLLC_PLLCTL_EXTCLKSRC __BIT(9)
sys/arch/arm/ti/am18xx_usbphy.c
74
#define AM18XX_CFGCHIP2_USB11SUSPENDM __BIT(7)
sys/arch/arm/ti/am18xx_usbphy.c
75
#define AM18XX_CFGCHIP2_USB20OTGPWDN __BIT(9)
sys/arch/arm/ti/am18xx_usbphyclk.c
104
#define AM18XX_CFGCHIP2_PHYCLKGD __BIT(17)
sys/arch/arm/ti/am18xx_usbphyclk.c
105
#define AM18XX_CFGCHIP2_PHYRESET __BIT(15)
sys/arch/arm/ti/am18xx_usbphyclk.c
106
#define AM18XX_CFGCHIP2_USB11CLKMUX __BIT(12)
sys/arch/arm/ti/am18xx_usbphyclk.c
107
#define AM18XX_CFGCHIP2_USB20CLKMUX __BIT(11)
sys/arch/arm/ti/am18xx_usbphyclk.c
108
#define AM18XX_CFGCHIP2_PHYPWRDN __BIT(10)
sys/arch/arm/ti/am18xx_usbphyclk.c
109
#define AM18XX_CFGCHIP2_PHYPLLON __BIT(6)
sys/arch/arm/ti/am3_prcm.c
56
#define AM3_PRCM_CM_IDLEST_DPLL_DISP_ST_MN_BYPASS __BIT(8)
sys/arch/arm/ti/am3_prcm.c
57
#define AM3_PRCM_CM_IDLEST_DPLL_DISP_ST_DPLL_CLK __BIT(0)
sys/arch/arm/ti/if_cpsw.c
776
if ((cpsw_read_4(sc, reg) & __BIT(31)) == 0)
sys/arch/arm/ti/if_cpsw.c
799
if (v & __BIT(29)) {
sys/arch/arm/ti/if_cpsw.c
825
if ((v & __BIT(29)) == 0) {
sys/arch/arm/ti/if_cpswreg.h
128
#define __BIT32(x) ((uint32_t)__BIT(x))
sys/arch/arm/ti/omap2_gpmcreg.h
196
#define GPMC_CONFIG7_CSVALID __BIT(6)
sys/arch/arm/ti/omap2_nand.c
62
#define WAIT0 __BIT(8) /* active low */
sys/arch/arm/ti/omap2_nand.c
65
#define ECCCLEAR __BIT(8)
sys/arch/arm/ti/omap2_nand.c
69
#define ECCALGORITHM __BIT(16)
sys/arch/arm/ti/omap2_nand.c
71
#define ECC16B __BIT(7)
sys/arch/arm/ti/omap2_nand.c
72
#define ECCENABLE __BIT(0)
sys/arch/arm/ti/omap2_nand.c
83
#define NAND_WP_BIT __BIT(4)
sys/arch/arm/ti/omap3_cm.c
100
TI_PRCM_HWMOD_MASK((_name), CM_USBHOST_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))
sys/arch/arm/ti/omap3_cm.c
176
val |= __BIT(0); /* CLKSEL_GPT2 0x1: source is SYS_CLK */
sys/arch/arm/ti/omap3_cm.c
177
val |= __BIT(1); /* CLKSEL_GPT3 0x1: source is SYS_CLK */
sys/arch/arm/ti/omap3_cm.c
92
TI_PRCM_HWMOD_MASK((_name), CM_CORE1_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))
sys/arch/arm/ti/omap3_cm.c
94
TI_PRCM_HWMOD_MASK((_name), CM_CORE3_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))
sys/arch/arm/ti/omap3_cm.c
96
TI_PRCM_HWMOD_MASK((_name), CM_WKUP_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))
sys/arch/arm/ti/omap3_cm.c
98
TI_PRCM_HWMOD_MASK((_name), CM_PER_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))
sys/arch/arm/ti/omap3_platform.c
117
#define OMAP4_RST_GLOBAL_COLD __BIT(1)
sys/arch/arm/ti/omap3_platform.c
402
hatched |= __BIT(cpuindex);
sys/arch/arm/ti/omap3_platform.c
83
#define OMAP3_PRM_RSTCTRL_RST_DPLL3 __BIT(2)
sys/arch/arm/ti/ti_cpufreq.c
69
rev = __BIT(__SHIFTOUT(syscon_read_4(ti_opp_syscon, AM33XX_REV_OFFSET), AM33XX_REV_MASK));
sys/arch/arm/ti/ti_dpll_clock.c
46
#define AM3_ST_MN_BYPASS __BIT(8)
sys/arch/arm/ti/ti_dpll_clock.c
47
#define AM3_ST_DPLL_CLK __BIT(0)
sys/arch/arm/ti/ti_dpll_clock.c
53
#define OMAP3_ST_MPU_CLK __BIT(0)
sys/arch/arm/ti/ti_edma.c
267
ipr &= ~__BIT(idx);
sys/arch/arm/ti/ti_edma.c
268
if (!(ier & __BIT(idx)))
sys/arch/arm/ti/ti_edma.c
320
EDMA_WRITE(sc, EDMA_ICR_REG, __BIT(ch->ch_index));
sys/arch/arm/ti/ti_edma.c
321
EDMA_WRITE(sc, EDMA_IESR_REG, __BIT(ch->ch_index));
sys/arch/arm/ti/ti_edma.c
323
EDMA_WRITE(sc, EDMA_ICRH_REG, __BIT(ch->ch_index - 32));
sys/arch/arm/ti/ti_edma.c
324
EDMA_WRITE(sc, EDMA_IESRH_REG, __BIT(ch->ch_index - 32));
sys/arch/arm/ti/ti_edma.c
345
EDMA_WRITE(sc, EDMA_IECR_REG, __BIT(ch->ch_index));
sys/arch/arm/ti/ti_edma.c
347
EDMA_WRITE(sc, EDMA_IECRH_REG, __BIT(ch->ch_index - 32));
sys/arch/arm/ti/ti_edma.c
431
uint32_t bit = __BIT(ch->ch_index < 32 ?
sys/arch/arm/ti/ti_edma.c
457
uint32_t bit = __BIT(ch->ch_index < 32 ?
sys/arch/arm/ti/ti_edma.c
475
uint32_t bit = __BIT(ch->ch_index < 32 ?
sys/arch/arm/ti/ti_edma.h
108
#define EDMA_PARAM_OPT_PRIV __BIT(31)
sys/arch/arm/ti/ti_edma.h
110
#define EDMA_PARAM_OPT_ITCCHEN __BIT(23)
sys/arch/arm/ti/ti_edma.h
111
#define EDMA_PARAM_OPT_TCCHEN __BIT(22)
sys/arch/arm/ti/ti_edma.h
112
#define EDMA_PARAM_OPT_ITCINTEN __BIT(21)
sys/arch/arm/ti/ti_edma.h
113
#define EDMA_PARAM_OPT_TCINTEN __BIT(20)
sys/arch/arm/ti/ti_edma.h
115
#define EDMA_PARAM_OPT_TCCMODE __BIT(11)
sys/arch/arm/ti/ti_edma.h
117
#define EDMA_PARAM_OPT_STATIC __BIT(3)
sys/arch/arm/ti/ti_edma.h
118
#define EDMA_PARAM_OPT_SYNCDIM __BIT(2)
sys/arch/arm/ti/ti_edma.h
119
#define EDMA_PARAM_OPT_DAM __BIT(1)
sys/arch/arm/ti/ti_edma.h
120
#define EDMA_PARAM_OPT_SAM __BIT(0)
sys/arch/arm/ti/ti_edma.h
33
#define EDMA_CCCFG_MP_EXIST __BIT(25)
sys/arch/arm/ti/ti_edma.h
34
#define EDMA_CCCFG_CHMAP_EXIST __BIT(24)
sys/arch/arm/ti/ti_edma.h
98
#define EDMA_IEVAL_EVAL __BIT(0)
sys/arch/arm/ti/ti_gate_clock.c
173
val |= __BIT(sc->sc_shift);
sys/arch/arm/ti/ti_gate_clock.c
187
val &= ~__BIT(sc->sc_shift);
sys/arch/arm/ti/ti_gpio.c
159
oe |= __BIT(pin);
sys/arch/arm/ti/ti_gpio.c
161
oe &= ~__BIT(pin);
sys/arch/arm/ti/ti_gpio.c
225
const uint32_t data_mask = __BIT(pin->pin_nr);
sys/arch/arm/ti/ti_gpio.c
247
const uint32_t data_mask = __BIT(pin->pin_nr);
sys/arch/arm/ti/ti_gpio.c
268
const uint32_t pin_mask = __BIT(pin);
sys/arch/arm/ti/ti_gpio.c
319
const uint32_t pin_mask = __BIT(pin);
sys/arch/arm/ti/ti_gpio.c
401
const uint32_t data_mask = __BIT(pin);
sys/arch/arm/ti/ti_gpio.c
417
const uint32_t data_mask = __BIT(pin);
sys/arch/arm/ti/ti_gpio.c
467
const uint32_t pin_mask = __BIT(pin);
sys/arch/arm/ti/ti_gpio.c
579
const uint32_t pin_mask = __BIT(pin);
sys/arch/arm/ti/ti_omapintc.c
152
const uint32_t oldipl_mask = __BIT(oldipl);
sys/arch/arm/ti/ti_omapintc.c
51
#define INTC_CONTROL_NEWIRQAGR __BIT(0)
sys/arch/arm/ti/ti_omapmusb.c
52
#define OTG_SYSCONFIG_ENAWAKEUP __BIT(2)
sys/arch/arm/ti/ti_omapmusb.c
53
#define OTG_SYSCONFIG_SOFTRESET __BIT(1)
sys/arch/arm/ti/ti_omapmusb.c
54
#define OTG_SYSCONFIG_AUTOIDLE __BIT(0)
sys/arch/arm/ti/ti_omapmusb.c
57
#define OTG_SYSSTATUS_RESETDONE __BIT(0)
sys/arch/arm/ti/ti_omaptimer.c
63
#define OVF_IT_FLAG __BIT(1)
sys/arch/arm/ti/ti_omaptimer.c
66
#define MAT_EN_FLAG __BIT(0)
sys/arch/arm/ti/ti_omaptimer.c
67
#define OVF_EN_FLAG __BIT(1)
sys/arch/arm/ti/ti_omaptimer.c
68
#define TCAR_EN_FLAG __BIT(2)
sys/arch/arm/ti/ti_omaptimer.c
71
#define TCLR_ST __BIT(0)
sys/arch/arm/ti/ti_omaptimer.c
72
#define TCLR_AR __BIT(1)
sys/arch/arm/ti/ti_rngreg.h
34
#define TRNG_STATUS_READY __BIT(0)
sys/arch/arm/ti/ti_rngreg.h
36
#define TRNG_INTACK_READY __BIT(0)
sys/arch/arm/ti/ti_rngreg.h
39
#define TRNG_CONTROL_ENABLE __BIT(10)
sys/arch/arm/ti/ti_usb.c
55
#define UHH_SYSCONFIG_MIDLEMODE_SMARTSTANDBY __BIT(12)
sys/arch/arm/ti/ti_usb.c
56
#define UHH_SYSCONFIG_CLOCKACTIVITY __BIT(8)
sys/arch/arm/ti/ti_usb.c
58
#define UHH_SYSCONFIG_SIDLEMODE_SMARTIDLE __BIT(3)
sys/arch/arm/ti/ti_usb.c
59
#define UHH_SYSCONFIG_ENAWAKEUP __BIT(2)
sys/arch/arm/ti/ti_usb.c
60
#define UHH_SYSCONFIG_SOFTRESET __BIT(1)
sys/arch/arm/ti/ti_usb.c
61
#define UHH_SYSCONFIG_AUTOIDLE __BIT(0)
sys/arch/arm/ti/ti_usb.c
64
#define UHH_HOSTCONFIG_APP_START_CLK __BIT(31)
sys/arch/arm/ti/ti_usb.c
71
#define UHH_HOSTCONFIG_P3_ULPI_BYPASS __BIT(12)
sys/arch/arm/ti/ti_usb.c
72
#define UHH_HOSTCONFIG_P2_ULPI_BYPASS __BIT(11)
sys/arch/arm/ti/ti_usb.c
73
#define UHH_HOSTCONFIG_P3_CONNECT_STATUS __BIT(10)
sys/arch/arm/ti/ti_usb.c
74
#define UHH_HOSTCONFIG_P2_CONNECT_STATUS __BIT(9)
sys/arch/arm/ti/ti_usb.c
75
#define UHH_HOSTCONFIG_P1_CONNECT_STATUS __BIT(8)
sys/arch/arm/ti/ti_usb.c
76
#define UHH_HOSTCONFIG_ENA_INCR_ALIGN __BIT(5)
sys/arch/arm/ti/ti_usb.c
77
#define UHH_HOSTCONFIG_ENA_INCR16 __BIT(4)
sys/arch/arm/ti/ti_usb.c
78
#define UHH_HOSTCONFIG_ENA_INCR8 __BIT(3)
sys/arch/arm/ti/ti_usb.c
79
#define UHH_HOSTCONFIG_ENA_INCR4 __BIT(2)
sys/arch/arm/ti/ti_usb.c
80
#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN __BIT(1)
sys/arch/arm/ti/ti_usb.c
81
#define UHH_HOSTCONFIG_P1_ULPI_BYPASS __BIT(0)
sys/arch/arm/ti/ti_wdt.c
45
#define WDSC_SOFTRESET __BIT(1)
sys/arch/arm/ti/ti_wdt.c
50
#define WCLR_PRE __BIT(5)
sys/arch/arm/ti/ti_wdt.c
56
#define WWPS_W_PEND_WDLY __BIT(5)
sys/arch/arm/ti/ti_wdt.c
57
#define WWPS_W_PEND_WSPR __BIT(4)
sys/arch/arm/ti/ti_wdt.c
58
#define WWPS_W_PEND_WTGR __BIT(3)
sys/arch/arm/ti/ti_wdt.c
59
#define WWPS_W_PEND_WLDR __BIT(2)
sys/arch/arm/ti/ti_wdt.c
60
#define WWPS_W_PEND_WCRR __BIT(1)
sys/arch/arm/ti/ti_wdt.c
61
#define WWPS_W_PEND_WCLR __BIT(0)
sys/arch/arm/ti/ti_wdt.c
69
#define WIRQ_EVENT_DLY __BIT(1)
sys/arch/arm/ti/ti_wdt.c
70
#define WIRQ_EVENT_OVF __BIT(0)
sys/arch/arm/vexpress/vexpress_platform.c
74
#define SYS_CFGCTRL_START __BIT(31)
sys/arch/arm/vexpress/vexpress_platform.c
75
#define SYS_CFGCTRL_WRITE __BIT(30)
sys/arch/arm/vexpress/vexpress_platform.c
84
#define SYS_CFGSTAT_ERROR __BIT(1)
sys/arch/arm/vexpress/vexpress_platform.c
85
#define SYS_CFGSTAT_COMPLETE __BIT(0)
sys/arch/arm/vexpress/vexpress_sysreg.c
42
#define SYS_CFGCTRL_START __BIT(31)
sys/arch/arm/vexpress/vexpress_sysreg.c
43
#define SYS_CFGCTRL_WRITE __BIT(30)
sys/arch/arm/xilinx/zynq7000_clkc.c
51
#define ARM_CLK_CTRL_CPU_1XCLKACT __BIT(27)
sys/arch/arm/xilinx/zynq7000_clkc.c
52
#define ARM_CLK_CTRL_CPU_2XCLKACT __BIT(26)
sys/arch/arm/xilinx/zynq7000_clkc.c
53
#define ARM_CLK_CTRL_CPU_3OR2XCLKACT __BIT(25)
sys/arch/arm/xilinx/zynq7000_clkc.c
54
#define ARM_CLK_CTRL_CPU_6OR4XCLKACT __BIT(24)
sys/arch/arm/xilinx/zynq7000_clkc.c
57
#define UART1_CPU_1XCLKACT __BIT(21)
sys/arch/arm/xilinx/zynq7000_clkc.c
58
#define UART0_CPU_1XCLKACT __BIT(20)
sys/arch/arm/xilinx/zynq7000_clkc.c
59
#define I2C1_CPU_1XCLKACT __BIT(19)
sys/arch/arm/xilinx/zynq7000_clkc.c
60
#define I2C0_CPU_1XCLKACT __BIT(18)
sys/arch/arm/xilinx/zynq7000_clkc.c
61
#define SDI1_CPU_1XCLKACT __BIT(11)
sys/arch/arm/xilinx/zynq7000_clkc.c
62
#define SDI0_CPU_1XCLKACT __BIT(10)
sys/arch/arm/xilinx/zynq7000_clkc.c
68
#define CLK_CTRL_CLKACT1 __BIT(1)
sys/arch/arm/xilinx/zynq7000_clkc.c
69
#define CLK_CTRL_CLKACT0 __BIT(0)
sys/arch/arm/xilinx/zynq7000_clkc.c
71
#define CLK_621_TRUE_EN __BIT(0)
sys/arch/arm/xilinx/zynq_gpio.c
220
mask_data = (0xffff & ~__BIT(pin % 16)) << 16;
sys/arch/arm/xilinx/zynq_gpio.c
222
mask_data |= __BIT(pin % 16);
sys/arch/arm/xilinx/zynq_gpio.c
50
#define DATA_RO_BIT(pin) __BIT((pin) % 32)
sys/arch/arm/xilinx/zynq_gpio.c
52
#define DIRM_BIT(pin) __BIT((pin) % 32)
sys/arch/arm/xilinx/zynq_gpio.c
54
#define OEN_BIT(pin) __BIT((pin) % 32)
sys/arch/arm/xilinx/zynq_platform.c
99
#define SOFT_RST __BIT(0)
sys/arch/arm/xilinx/zynq_uart.c
174
#define ZYNQUART_HW_FLOW __BIT(0)
sys/arch/arm/xilinx/zynq_uart.c
175
#define ZYNQUART_HW_DEV_OK __BIT(1)
sys/arch/arm/xilinx/zynq_uart.c
176
#define ZYNQUART_HW_CONSOLE __BIT(2)
sys/arch/arm/xilinx/zynq_uart.c
177
#define ZYNQUART_HW_KGDB __BIT(3)
sys/arch/arm/xilinx/zynq_uart.c
184
#define ZYNQUART_RX_TTY_BLOCKED __BIT(0)
sys/arch/arm/xilinx/zynq_uart.c
185
#define ZYNQUART_RX_TTY_OVERFLOWED __BIT(1)
sys/arch/arm/xilinx/zynq_uart.c
186
#define ZYNQUART_RX_IBUF_BLOCKED __BIT(2)
sys/arch/arm/xilinx/zynq_uart.c
187
#define ZYNQUART_RX_IBUF_OVERFLOWED __BIT(3)
sys/arch/arm/xilinx/zynq_uart.c
220
#define ZYNQUART_PEND_PARAM __BIT(0)
sys/arch/arm/xilinx/zynq_uart.c
221
#define ZYNQUART_PEND_SPEED __BIT(1)
sys/arch/arm/xilinx/zynq_uartreg.h
100
#define STS_TEMPTY __BIT(3)
sys/arch/arm/xilinx/zynq_uartreg.h
101
#define STS_RFUL __BIT(2)
sys/arch/arm/xilinx/zynq_uartreg.h
102
#define STS_REMPTY __BIT(1)
sys/arch/arm/xilinx/zynq_uartreg.h
103
#define STS_RTRIG __BIT(0)
sys/arch/arm/xilinx/zynq_uartreg.h
33
#define CR_STPBRK __BIT(8)
sys/arch/arm/xilinx/zynq_uartreg.h
34
#define CR_STTBRK __BIT(7)
sys/arch/arm/xilinx/zynq_uartreg.h
35
#define CR_RSTTO __BIT(6)
sys/arch/arm/xilinx/zynq_uartreg.h
36
#define CR_TXDIS __BIT(5)
sys/arch/arm/xilinx/zynq_uartreg.h
37
#define CR_TXEN __BIT(4)
sys/arch/arm/xilinx/zynq_uartreg.h
38
#define CR_RXDIS __BIT(3)
sys/arch/arm/xilinx/zynq_uartreg.h
39
#define CR_RXEN __BIT(2)
sys/arch/arm/xilinx/zynq_uartreg.h
40
#define CR_TXRES __BIT(1)
sys/arch/arm/xilinx/zynq_uartreg.h
41
#define CR_RXRES __BIT(0)
sys/arch/arm/xilinx/zynq_uartreg.h
58
#define MR_CLKS __BIT(0)
sys/arch/arm/xilinx/zynq_uartreg.h
63
#define INT_TOVR __BIT(12)
sys/arch/arm/xilinx/zynq_uartreg.h
64
#define INT_TNFUL __BIT(11)
sys/arch/arm/xilinx/zynq_uartreg.h
65
#define INT_TTRIG __BIT(10)
sys/arch/arm/xilinx/zynq_uartreg.h
66
#define INT_DMSI __BIT(9)
sys/arch/arm/xilinx/zynq_uartreg.h
67
#define INT_TIMEOUT __BIT(8)
sys/arch/arm/xilinx/zynq_uartreg.h
68
#define INT_PARE __BIT(7)
sys/arch/arm/xilinx/zynq_uartreg.h
69
#define INT_FRAME __BIT(6)
sys/arch/arm/xilinx/zynq_uartreg.h
70
#define INT_ROVR __BIT(5)
sys/arch/arm/xilinx/zynq_uartreg.h
71
#define INT_TFUL __BIT(4)
sys/arch/arm/xilinx/zynq_uartreg.h
72
#define INT_TEMPTY __BIT(3)
sys/arch/arm/xilinx/zynq_uartreg.h
73
#define INT_RFUL __BIT(2)
sys/arch/arm/xilinx/zynq_uartreg.h
74
#define INT_REMPTY __BIT(1)
sys/arch/arm/xilinx/zynq_uartreg.h
75
#define INT_RTRIG __BIT(0)
sys/arch/arm/xilinx/zynq_uartreg.h
80
#define MODEMCR_FCM __BIT(5)
sys/arch/arm/xilinx/zynq_uartreg.h
81
#define MODEMCR_RTS __BIT(1)
sys/arch/arm/xilinx/zynq_uartreg.h
82
#define MODEMCR_DTR __BIT(0)
sys/arch/arm/xilinx/zynq_uartreg.h
84
#define MODEMSR_FCMS __BIT(8)
sys/arch/arm/xilinx/zynq_uartreg.h
85
#define MODEMSR_DCD __BIT(7)
sys/arch/arm/xilinx/zynq_uartreg.h
86
#define MODEMSR_RI __BIT(6)
sys/arch/arm/xilinx/zynq_uartreg.h
87
#define MODEMSR_DSR __BIT(5)
sys/arch/arm/xilinx/zynq_uartreg.h
88
#define MODEMSR_CTS __BIT(4)
sys/arch/arm/xilinx/zynq_uartreg.h
89
#define MODEMSR_DDCD __BIT(3)
sys/arch/arm/xilinx/zynq_uartreg.h
90
#define MODEMSR_TERI __BIT(2)
sys/arch/arm/xilinx/zynq_uartreg.h
91
#define MODEMSR_DDSR __BIT(1)
sys/arch/arm/xilinx/zynq_uartreg.h
92
#define MODEMSR_DCTS __BIT(0)
sys/arch/arm/xilinx/zynq_uartreg.h
94
#define STS_TNFUL __BIT(14)
sys/arch/arm/xilinx/zynq_uartreg.h
95
#define STS_TTRIG __BIT(13)
sys/arch/arm/xilinx/zynq_uartreg.h
96
#define STS_FDELT __BIT(12)
sys/arch/arm/xilinx/zynq_uartreg.h
97
#define STS_TAVTIVE __BIT(11)
sys/arch/arm/xilinx/zynq_uartreg.h
98
#define STS_RACTIVE __BIT(10)
sys/arch/arm/xilinx/zynq_uartreg.h
99
#define STS_TFUL __BIT(4)
sys/arch/arm/xilinx/zynq_usbreg.h
104
#define PORTSC_STS __BIT(29) /* serial transceiver select */
sys/arch/arm/xilinx/zynq_usbreg.h
105
#define PORTSC_PTW __BIT(28) /* parallel transceiver width */
sys/arch/arm/xilinx/zynq_usbreg.h
109
#define PORTSC_PFSC __BIT(24) /* port force full speed */
sys/arch/arm/xilinx/zynq_usbreg.h
110
#define PORTSC_PHCD __BIT(23) /* PHY low power suspend */
sys/arch/arm/xilinx/zynq_usbreg.h
40
#define HWHOST_HC __BIT(0)
sys/arch/arm/xilinx/zynq_usbreg.h
43
#define HWDEVICE_DC __BIT(0)
sys/arch/arm/xilinx/zynq_usbreg.h
51
#define ULPI_WU __BIT(31)
sys/arch/arm/xilinx/zynq_usbreg.h
52
#define ULPI_RUN __BIT(30)
sys/arch/arm/xilinx/zynq_usbreg.h
53
#define ULPI_RW __BIT(29)
sys/arch/arm/xilinx/zynq_usbreg.h
54
#define ULPI_SS __BIT(27)
sys/arch/arm/xilinx/zynq_usbreg.h
61
#define OTGSC_DPIE __BIT(30)
sys/arch/arm/xilinx/zynq_usbreg.h
62
#define OTGSC_1MSE __BIT(29)
sys/arch/arm/xilinx/zynq_usbreg.h
63
#define OTGSC_BSEIE __BIT(28)
sys/arch/arm/xilinx/zynq_usbreg.h
64
#define OTGSC_BSVIE __BIT(27)
sys/arch/arm/xilinx/zynq_usbreg.h
65
#define OTGSC_ASVIE __BIT(26)
sys/arch/arm/xilinx/zynq_usbreg.h
66
#define OTGSC_AVVIE __BIT(25)
sys/arch/arm/xilinx/zynq_usbreg.h
67
#define OTGSC_IDIE __BIT(24)
sys/arch/arm/xilinx/zynq_usbreg.h
68
#define OTGSC_DPIS __BIT(22)
sys/arch/arm/xilinx/zynq_usbreg.h
69
#define OTGSC_1MSS __BIT(21)
sys/arch/arm/xilinx/zynq_usbreg.h
70
#define OTGSC_BSEIS __BIT(20)
sys/arch/arm/xilinx/zynq_usbreg.h
71
#define OTGSC_BSVIS __BIT(19)
sys/arch/arm/xilinx/zynq_usbreg.h
72
#define OTGSC_ASVIS __BIT(18)
sys/arch/arm/xilinx/zynq_usbreg.h
73
#define OTGSC_AVVIS __BIT(17)
sys/arch/arm/xilinx/zynq_usbreg.h
74
#define OTGSC_IDIS __BIT(16)
sys/arch/arm/xilinx/zynq_usbreg.h
75
#define OTGSC_DPS __BIT(14)
sys/arch/arm/xilinx/zynq_usbreg.h
76
#define OTGSC_1MST __BIT(13)
sys/arch/arm/xilinx/zynq_usbreg.h
77
#define OTGSC_BSE __BIT(12)
sys/arch/arm/xilinx/zynq_usbreg.h
78
#define OTGSC_BSV __BIT(11)
sys/arch/arm/xilinx/zynq_usbreg.h
79
#define OTGSC_ASV __BIT(10)
sys/arch/arm/xilinx/zynq_usbreg.h
80
#define OTGSC_AVV __BIT( 9)
sys/arch/arm/xilinx/zynq_usbreg.h
81
#define OTGSC_ID __BIT( 8)
sys/arch/arm/xilinx/zynq_usbreg.h
82
#define OTGSC_HABA __BIT( 7)
sys/arch/arm/xilinx/zynq_usbreg.h
83
#define OTGSC_HADP __BIT( 6)
sys/arch/arm/xilinx/zynq_usbreg.h
84
#define OTGSC_IDPU __BIT( 5)
sys/arch/arm/xilinx/zynq_usbreg.h
85
#define OTGSC_DP __BIT( 4)
sys/arch/arm/xilinx/zynq_usbreg.h
86
#define OTGSC_OT __BIT( 3)
sys/arch/arm/xilinx/zynq_usbreg.h
87
#define OTGSC_HAAR __BIT( 2)
sys/arch/arm/xilinx/zynq_usbreg.h
88
#define OTGSC_VC __BIT( 1)
sys/arch/arm/xilinx/zynq_usbreg.h
89
#define OTGSC_VD __BIT( 0)
sys/arch/arm/xilinx/zynq_xadc.c
55
#define CFG_ENABLE __BIT(31)
sys/arch/arm/xilinx/zynq_xadc.c
56
#define CFG_WEDGE __BIT(13)
sys/arch/arm/xilinx/zynq_xadc.c
57
#define CFG_REDGE __BIT(12)
sys/arch/arm/xilinx/zynq_xadc.c
63
#define MSTS_CFIFOE __BIT(10)
sys/arch/arm/xilinx/zynq_xadc.c
80
#define FLAG_OT __BIT(3)
sys/arch/arm/xilinx/zynq_xadc.c
85
#define SEQ0_CALIB __BIT(0)
sys/arch/arm/xilinx/zynq_xadc.c
87
#define SEQ4_VREFN __BIT(13)
sys/arch/epoc32/epoc32/intr.c
48
const uint32_t oldipl_mask = __BIT(oldipl);
sys/arch/evbarm/rpi/vcprop.h
257
#define VCPROP_REV_ENCFLAG __BIT(23)
sys/arch/evbmips/cavium/octeon_uboot.h
110
#define CONFIG_FLAGS_PCI_HOST __BIT(0)
sys/arch/evbmips/cavium/octeon_uboot.h
111
#define CONFIG_FLAGS_PCI_TARGET __BIT(1)
sys/arch/evbmips/cavium/octeon_uboot.h
112
#define CONFIG_FLAGS_DEBUG __BIT(2)
sys/arch/evbmips/cavium/octeon_uboot.h
113
#define CONFIG_FLAGS_NO_MAGIC __BIT(3)
sys/arch/evbmips/cavium/octeon_uboot.h
114
#define CONFIG_FLAGS_OVERSIZE_TLB_MAPPING __BIT(4)
sys/arch/evbmips/cavium/octeon_uboot.h
115
#define CONFIG_FLAGS_BREAK __BIT(5)
sys/arch/evbmips/mipssim/if_mipsnetreg.h
42
#define MN_INTR_TXDONE __BIT(0) /* tx done interrupt */
sys/arch/evbmips/mipssim/if_mipsnetreg.h
43
#define MN_INTR_RXDONE __BIT(1) /* rx data available interrupt */
sys/arch/evbmips/mipssim/if_mipsnetreg.h
44
#define MN_INTR_TEST __BIT(31) /* interrupt test */
sys/arch/evbmips/rmixl/machdep.c
435
r &= ~__BIT(14); /* disable Unaligned Access */
sys/arch/evbmips/rmixl/machdep.c
445
r &= ~__BIT(7);
sys/arch/evbmips/rmixl/machdep.c
600
unsigned long end = (__BIT(40) / (1024 * 1024)) -1;
sys/arch/evbppc/include/wii.h
127
#define HW_IPCPPCCTRL_X1 __BIT(0)
sys/arch/evbppc/include/wii.h
129
#define VIDIM_E __BIT(7)
sys/arch/evbppc/include/wii.h
137
#define IOPSD1EN __BIT(24)
sys/arch/evbppc/include/wii.h
138
#define IOPSD0EN __BIT(23)
sys/arch/evbppc/include/wii.h
139
#define IOPOH1EN __BIT(22)
sys/arch/evbppc/include/wii.h
140
#define IOPOH0EN __BIT(21)
sys/arch/evbppc/include/wii.h
141
#define IOPEHCEN __BIT(20)
sys/arch/evbppc/include/wii.h
142
#define IOPAESEN __BIT(18)
sys/arch/evbppc/include/wii.h
144
#define ENAHBIOPI __BIT(0)
sys/arch/evbppc/include/wii.h
150
#define DVDVIDEO __BIT(21)
sys/arch/evbppc/include/wii.h
152
#define RSTB_IOP __BIT(23)
sys/arch/evbppc/include/wii.h
153
#define RSTB_DSP __BIT(22)
sys/arch/evbppc/include/wii.h
154
#define RSTB_IODI __BIT(17)
sys/arch/evbppc/include/wii.h
155
#define RSTBINB __BIT(0)
sys/arch/evbppc/include/wii.h
181
for (val = in32(HW_GPIOB_OUT); ; val ^= __BIT(GPIO_SLOT_LED)) {
sys/arch/evbppc/include/wii.h
195
val |= __BIT(GPIO_SLOT_LED);
sys/arch/evbppc/include/wii.h
197
val &= ~__BIT(GPIO_SLOT_LED);
sys/arch/evbppc/include/wiiu.h
82
#define PPC_COMPAT __BIT(5)
sys/arch/evbppc/mpc85xx/cadmusreg.h
52
#define CM_CSR_LED __BIT(0)
sys/arch/evbppc/mpc85xx/cadmusreg.h
54
#define CM_RST_XRSTEN __BIT(7) /* Enable the NVRAM watchdog timer to function as a general reset input */
sys/arch/evbppc/mpc85xx/cadmusreg.h
55
#define CM_RST_PHYRST __BIT(6) /* Reset the Ethernet PHY */
sys/arch/evbppc/mpc85xx/cadmusreg.h
56
#define CM_RST_ATM1RST __BIT(5) /* Reset the FCC1/ATM1 PHYS */
sys/arch/evbppc/mpc85xx/cadmusreg.h
57
#define CM_RST_ATM2RST __BIT(4) /* Reset the FCC2/ATM2 PHY */
sys/arch/evbppc/mpc85xx/cadmusreg.h
58
#define CM_RST_MEMRST __BIT(3) /* Reset the memory devices on the daughter card */
sys/arch/evbppc/mpc85xx/cadmusreg.h
59
#define CM_RST_UTRST __BIT(2) /* Reset the TCOM/ECOM boards */
sys/arch/evbppc/mpc85xx/cadmusreg.h
60
#define CM_RST_HRESET __BIT(1) /* Assert HRESET */
sys/arch/evbppc/mpc85xx/cadmusreg.h
61
#define CM_RST_SRESET __BIT(0) /* Assert SRESET */
sys/arch/evbppc/mpc85xx/cadmusreg.h
64
#define CM_PCI_M66O __BIT(7)
sys/arch/evbppc/mpc85xx/cadmusreg.h
65
#define CM_PCI_PCIXCO __BIT(6)
sys/arch/evbppc/mpc85xx/cadmusreg.h
66
#define CM_PCI_M66S __BIT(5) /* PCI V2.3 mode or earlier running at 66MHz */
sys/arch/evbppc/mpc85xx/cadmusreg.h
67
#define CM_PCI_DUAL __BIT(4) /* Daughter card has selected dual PCI-mode */
sys/arch/evbppc/mpc85xx/cadmusreg.h
71
#define CM_PCI_PCIX __BIT(1) /* the PCI edge connector is connected to a PCI-X backplace */
sys/arch/evbppc/mpc85xx/cadmusreg.h
72
#define CM_PCI_PCIEN __BIT(0) /* if 1, the PCI backplane is not present */
sys/arch/evbppc/mpc85xx/cadmusreg.h
75
#define CM_DMA_DMARQ0 __BIT(6)
sys/arch/evbppc/mpc85xx/cadmusreg.h
76
#define CM_DMA_DMACK0 __BIT(5)
sys/arch/evbppc/mpc85xx/cadmusreg.h
77
#define CM_DMA_DMADN0 __BIT(4)
sys/arch/evbppc/mpc85xx/cadmusreg.h
78
#define CM_DMA_DMARQ1 __BIT(2)
sys/arch/evbppc/mpc85xx/cadmusreg.h
79
#define CM_DMA_DMACK1 __BIT(1)
sys/arch/evbppc/mpc85xx/cadmusreg.h
80
#define CM_DMA_DMADN1 __BIT(0)
sys/arch/evbppc/mpc85xx/pixisreg.h
43
#define PX_CSR_ASLEEP __BIT(6)
sys/arch/evbppc/mpc85xx/pixisreg.h
46
#define PX_CSR_PASS __BIT(1)
sys/arch/evbppc/mpc85xx/pixisreg.h
47
#define PX_CSR_FAIL __BIT(0)
sys/arch/evbppc/mpc85xx/pixisreg.h
49
#define PX_RST_ALL __BIT(7) /* if set to 0 a full system reset is initiated */
sys/arch/evbppc/mpc85xx/pixisreg.h
50
#define PX_RST_PCIE1 __BIT(6) /* If 1: RST_PCIE1* is deasserted and the slot is out of reset. */
sys/arch/evbppc/mpc85xx/pixisreg.h
51
#define PX_RST_PCIE2 __BIT(5) /* If 1: RST_PCIE2* is deasserted and the slot is out of reset. */
sys/arch/evbppc/mpc85xx/pixisreg.h
52
#define PX_RST_PCIE3 __BIT(4) /* If 1: RST_PCIE3* is deasserted and the slot is out of reset. */
sys/arch/evbppc/mpc85xx/pixisreg.h
53
#define PX_RST_USB __BIT(3) /* If 0: RST_USB3300 is deasserted and the devices are out of reset. */
sys/arch/evbppc/mpc85xx/pixisreg.h
54
#define PX_RST_PHY __BIT(2) /* If 1: PHY_RST* is deasserted and the device is out of reset. */
sys/arch/evbppc/mpc85xx/pixisreg.h
55
#define PX_RST_LB __BIT(1) /* If 1: LB_RST* is deasserted and the device is out of reset. */
sys/arch/evbppc/mpc85xx/pixisreg.h
56
#define PX_RST_GEN __BIT(0) /* If 1: GEN_RST* is deasserted and the devices are out of reset. */
sys/arch/evbppc/mpc85xx/pixisreg.h
58
#define PX_RST2_SGMII __BIT(1) /* If 1: RST_SGMII_SLOT* is deasserted and the device is out of reset. */
sys/arch/evbppc/mpc85xx/pixisreg.h
59
#define PX_RST2_PCI __BIT(0) /* If 1: RST_PCI_SLOT* is deasserted and the devices are out of reset. */
sys/arch/evbppc/mpc85xx/pixisreg.h
76
#define PX_CSR2_MMC_8BITEN __BIT(7)
sys/arch/evbppc/mpc85xx/pixisreg.h
77
#define PX_CSR2_SDSEL_EN __BIT(6)
sys/arch/evbppc/mpc85xx/pixisreg.h
78
#define PX_CSR2_MMC_8BIT __BIT(4)
sys/arch/evbppc/mpc85xx/pixisreg.h
79
#define PX_CSR2_SDSEK __BIT(3)
sys/arch/evbppc/nintendo/dev/ahb.c
178
pic_irqmask[0] |= __BIT(irq);
sys/arch/evbppc/nintendo/dev/ahb.c
185
pic_irqmask[0] &= ~__BIT(irq);
sys/arch/evbppc/nintendo/dev/ahb.c
208
WR4(HW_PPCIRQFLAGS, __BIT(irq));
sys/arch/evbppc/nintendo/dev/ahb.c
218
val &= ~__BIT(irq);
sys/arch/evbppc/nintendo/dev/ahb.c
220
WR4(HW_ARMIRQFLAGS, __BIT(irq));
sys/arch/evbppc/nintendo/dev/ahb.c
228
pic_irqmask[irq / 32] |= __BIT(irq % 32);
sys/arch/evbppc/nintendo/dev/ahb.c
237
pic_irqmask[irq / 32] &= ~__BIT(irq % 32);
sys/arch/evbppc/nintendo/dev/ahb.c
268
WR4(reg_sts, __BIT(irq % 32));
sys/arch/evbppc/nintendo/dev/ahb.c
280
val &= ~__BIT(irq % 32);
sys/arch/evbppc/nintendo/dev/ahb.c
282
WR4(reg_sts, __BIT(irq % 32));
sys/arch/evbppc/nintendo/dev/ahcisata_ahb.c
48
#define SATA_HCCFG_INT_PORT1 __BIT(5)
sys/arch/evbppc/nintendo/dev/ahcisata_ahb.c
49
#define SATA_HCCFG_INT_PORT0 __BIT(3)
sys/arch/evbppc/nintendo/dev/bwai.c
49
#define AI_CONTROL_RATE __BIT(6)
sys/arch/evbppc/nintendo/dev/bwai.c
50
#define AI_CONTROL_SCRESET __BIT(5)
sys/arch/evbppc/nintendo/dev/bwai.c
51
#define AI_CONTROL_AIINTVLD __BIT(4)
sys/arch/evbppc/nintendo/dev/bwai.c
52
#define AI_CONTROL_AIINT __BIT(3)
sys/arch/evbppc/nintendo/dev/bwai.c
53
#define AI_CONTROL_AIINTMSK __BIT(2)
sys/arch/evbppc/nintendo/dev/bwai.c
54
#define AI_CONTROL_AFR __BIT(1)
sys/arch/evbppc/nintendo/dev/bwai.c
55
#define AI_CONTROL_PSTAT __BIT(0)
sys/arch/evbppc/nintendo/dev/bwdsp.c
53
#define DSP_DMA_CONTROL_LENGTH_CTRL __BIT(15)
sys/arch/evbppc/nintendo/dev/di.c
483
out32(HW_GPIOB_OUT, in32(HW_GPIOB_OUT) & ~__BIT(GPIO_DI_SPIN));
sys/arch/evbppc/nintendo/dev/di.c
485
out32(HW_GPIOB_OUT, in32(HW_GPIOB_OUT) | __BIT(GPIO_DI_SPIN));
sys/arch/evbppc/nintendo/dev/di.c
63
#define DISR_BRKINT __BIT(6)
sys/arch/evbppc/nintendo/dev/di.c
64
#define DISR_BRKINTMASK __BIT(5)
sys/arch/evbppc/nintendo/dev/di.c
65
#define DISR_TCINT __BIT(4)
sys/arch/evbppc/nintendo/dev/di.c
66
#define DISR_TCINTMASK __BIT(3)
sys/arch/evbppc/nintendo/dev/di.c
67
#define DISR_DEINT __BIT(2)
sys/arch/evbppc/nintendo/dev/di.c
68
#define DISR_DEINTMASK __BIT(1)
sys/arch/evbppc/nintendo/dev/di.c
69
#define DISR_BRK __BIT(0)
sys/arch/evbppc/nintendo/dev/di.c
71
#define DICVR_CVRINT __BIT(2)
sys/arch/evbppc/nintendo/dev/di.c
72
#define DICVR_CVRINTMASK __BIT(1)
sys/arch/evbppc/nintendo/dev/di.c
73
#define DICVR_CVR __BIT(0)
sys/arch/evbppc/nintendo/dev/di.c
80
#define DICR_DMA __BIT(1)
sys/arch/evbppc/nintendo/dev/di.c
81
#define DICR_TSTART __BIT(0)
sys/arch/evbppc/nintendo/dev/exi.c
211
val |= __SHIFTIN(__BIT(dev), EXI_CSR_CS);
sys/arch/evbppc/nintendo/dev/exireg.h
33
#define EXI_CSR_EXTINT __BIT(11)
sys/arch/evbppc/nintendo/dev/exireg.h
34
#define EXI_CSR_EXTINTMASK __BIT(10)
sys/arch/evbppc/nintendo/dev/exireg.h
45
#define EXI_CR_DMA __BIT(1)
sys/arch/evbppc/nintendo/dev/exireg.h
46
#define EXI_CR_TSTART __BIT(0)
sys/arch/evbppc/nintendo/dev/hwaes.c
59
#define AES_CTRL_EXEC __BIT(31)
sys/arch/evbppc/nintendo/dev/hwaes.c
60
#define AES_CTRL_IRQ __BIT(30)
sys/arch/evbppc/nintendo/dev/hwaes.c
61
#define AES_CTRL_ERR __BIT(29)
sys/arch/evbppc/nintendo/dev/hwaes.c
62
#define AES_CTRL_ENA __BIT(28)
sys/arch/evbppc/nintendo/dev/hwaes.c
63
#define AES_CTRL_DEC __BIT(27)
sys/arch/evbppc/nintendo/dev/hwaes.c
64
#define AES_CTRL_IV __BIT(12)
sys/arch/evbppc/nintendo/dev/hwgpio.c
141
return (RD4(sc, GPIOB_IN) & __BIT(pin)) != 0;
sys/arch/evbppc/nintendo/dev/hwgpio.c
153
out |= __BIT(pin);
sys/arch/evbppc/nintendo/dev/hwgpio.c
155
out &= ~__BIT(pin);
sys/arch/evbppc/nintendo/dev/hwgpio.c
170
dir |= __BIT(pin);
sys/arch/evbppc/nintendo/dev/hwgpio.c
172
dir &= ~__BIT(pin);
sys/arch/evbppc/nintendo/dev/hwgpio.c
239
const uint32_t mask = __BIT(pins[n].pin_num);
sys/arch/evbppc/nintendo/dev/resetbtn.c
46
#define RESET_SWITCH_STATE __BIT(16)
sys/arch/evbppc/nintendo/dev/si.c
108
#define SI_STATE_OPEN __BIT(0)
sys/arch/evbppc/nintendo/dev/si.c
109
#define SI_STATE_STOPPED __BIT(1)
sys/arch/evbppc/nintendo/dev/si.c
59
#define SIPOLL_EN(n) (__BIT(7 - n))
sys/arch/evbppc/nintendo/dev/si.c
61
#define SICOMCSR_TCINT __BIT(31)
sys/arch/evbppc/nintendo/dev/si.c
62
#define SICOMCSR_TCINTMSK __BIT(30)
sys/arch/evbppc/nintendo/dev/si.c
63
#define SICOMCSR_RDSTINT __BIT(28)
sys/arch/evbppc/nintendo/dev/si.c
64
#define SICOMCSR_RDSTINTMSK __BIT(27)
sys/arch/evbppc/nintendo/dev/si.c
67
#define SICOMCSR_TSTART __BIT(0)
sys/arch/evbppc/nintendo/dev/si.c
70
#define SISR_WR(n) __BIT(SISR_OFF(n) + 7)
sys/arch/evbppc/nintendo/dev/si.c
71
#define SISR_RDST(n) __BIT(SISR_OFF(n) + 5)
sys/arch/evbppc/nintendo/dev/si.c
72
#define SISR_WRST(n) __BIT(SISR_OFF(n) + 4)
sys/arch/evbppc/nintendo/dev/si.c
73
#define SISR_NOREP(n) __BIT(SISR_OFF(n) + 3)
sys/arch/evbppc/nintendo/dev/si.c
74
#define SISR_COLL(n) __BIT(SISR_OFF(n) + 2)
sys/arch/evbppc/nintendo/dev/si.c
75
#define SISR_OVRUN(n) __BIT(SISR_OFF(n) + 1)
sys/arch/evbppc/nintendo/dev/si.c
76
#define SISR_UNRUN(n) __BIT(SISR_OFF(n) + 0)
sys/arch/evbppc/nintendo/dev/vireg.h
104
#define VI_BFBL_PGOFF __BIT(28)
sys/arch/evbppc/nintendo/dev/vireg.h
125
#define VI_DI_INT __BIT(31)
sys/arch/evbppc/nintendo/dev/vireg.h
126
#define VI_DI_ENB __BIT(28)
sys/arch/evbppc/nintendo/dev/vireg.h
133
#define VI_DL_TRG __BIT(31)
sys/arch/evbppc/nintendo/dev/vireg.h
144
#define VI_HSR_HS_EN __BIT(12)
sys/arch/evbppc/nintendo/dev/vireg.h
161
#define VI_VICLK_SEL __BIT(0)
sys/arch/evbppc/nintendo/dev/vireg.h
167
#define VI_VISEL_SEL __BIT(2)
sys/arch/evbppc/nintendo/dev/vireg.h
168
#define VI_VISEL_COMPONENT_CABLE __BIT(0)
sys/arch/evbppc/nintendo/dev/vireg.h
176
#define VI_HBE_BRDR_EN __BIT(15)
sys/arch/evbppc/nintendo/dev/vireg.h
51
#define VI_DCR_DLR __BIT(3)
sys/arch/evbppc/nintendo/dev/vireg.h
52
#define VI_DCR_NIN __BIT(2)
sys/arch/evbppc/nintendo/dev/vireg.h
53
#define VI_DCR_RST __BIT(1)
sys/arch/evbppc/nintendo/dev/vireg.h
54
#define VI_DCR_ENB __BIT(0)
sys/arch/evbppc/nintendo/dev/vireg.h
94
#define VI_TFBL_PGOFF __BIT(28)
sys/arch/evbppc/nintendo/dev/wiiufb.c
70
#define DCRTC_BLANK_DATA_EN __BIT(8)
sys/arch/evbppc/nintendo/dev/wiiufb.c
72
#define DCUR_CONTROL_EN __BIT(0)
sys/arch/evbppc/nintendo/dev/wiiufb.c
86
#define DCUR_UPDATE_LOCK __BIT(16)
sys/arch/evbppc/nintendo/machdep.c
144
#define RESET_SWITCH_STATE __BIT(16)
sys/arch/evbppc/nintendo/machdep.c
618
out32(HW_GPIO_OWNER, in32(HW_GPIO_OWNER) | __BIT(GPIO_SHUTDOWN));
sys/arch/evbppc/nintendo/machdep.c
621
out32(HW_GPIO_OWNER, in32(HW_GPIO_OWNER) | __BIT(GPIO_DI_SPIN));
sys/arch/evbppc/nintendo/machdep.c
648
out32(HW_GPIOB_OUT, in32(HW_GPIOB_OUT) | __BIT(GPIO_SHUTDOWN));
sys/arch/evbppc/nintendo/machdep.c
670
if ((in32(HW_GPIOB_IN) & __BIT(WIIU_GPIO_POWER)) != 0) {
sys/arch/evbppc/nintendo/pic_pi.c
100
pic_s[cpu_num].irqmask &= ~__BIT(irq);
sys/arch/evbppc/nintendo/pic_pi.c
140
pic_s[cpu_num].actmask |= __BIT(irq);
sys/arch/evbppc/nintendo/pic_pi.c
151
pic_s[cpu_num].actmask &= ~__BIT(irq);
sys/arch/evbppc/nintendo/pic_pi.c
153
WR4(pic_s[cpu_num].intsr, __BIT(irq));
sys/arch/evbppc/nintendo/pic_pi.c
91
pic_s[cpu_num].irqmask |= __BIT(irq);
sys/arch/evbppc/stand/wii/boot.c
45
#define RESET_SWITCH_STATE __BIT(16)
sys/arch/evbppc/stand/wii/boot.c
49
#define RSTBINB __BIT(0)
sys/arch/evbppc/stand/wii/gecko.c
38
#define EXI_CSR_EXTINT __BIT(11)
sys/arch/evbppc/stand/wii/gecko.c
39
#define EXI_CSR_EXTINTMASK __BIT(10)
sys/arch/evbppc/stand/wii/gecko.c
48
#define EXI_CR_DMA __BIT(1)
sys/arch/evbppc/stand/wii/gecko.c
49
#define EXI_CR_TSTART __BIT(0)
sys/arch/evbppc/stand/wii/gpio.c
44
out32(HW_GPIOB_OUT, in32(HW_GPIOB_OUT) | __BIT(pin));
sys/arch/evbppc/stand/wii/gpio.c
50
out32(HW_GPIOB_OUT, in32(HW_GPIOB_OUT) & ~__BIT(pin));
sys/arch/evbppc/stand/wii/gpio.c
62
out32(HW_GPIO_INTLVL, in32(HW_GPIO_INTLVL) | __BIT(pin));
sys/arch/evbppc/stand/wii/gpio.c
68
out32(HW_GPIO_INTLVL, in32(HW_GPIO_INTLVL) & ~__BIT(pin));
sys/arch/evbppc/stand/wii/gpio.c
80
out32(HW_GPIO_INTFLAG, __BIT(pin));
sys/arch/evbppc/stand/wii/miniipc.c
45
#define HW_IPC_PPCCTRL_IN __BIT(2)
sys/arch/evbppc/stand/wii/miniipc.c
46
#define HW_IPC_PPCCTRL_OUT __BIT(0)
sys/arch/hp300/dev/intio.c
71
(__BIT(HP_320) | __BIT(HP_330) | __BIT(HP_340) | \
sys/arch/hp300/dev/intio.c
72
__BIT(HP_345) | __BIT(HP_345) | __BIT(HP_350) | \
sys/arch/hp300/dev/intio.c
73
__BIT(HP_360) | __BIT(HP_370) | __BIT(HP_375) | \
sys/arch/hp300/dev/intio.c
74
__BIT(HP_380) | __BIT(HP_385))
sys/arch/hp300/dev/intio.c
76
#define INTIO_362_BUILTINS __BIT(HP_362)
sys/arch/hp300/dev/intio.c
77
#define INTIO_382_BUILTINS __BIT(HP_382)
sys/arch/hp300/dev/intio.c
80
(__BIT(HP_400) | __BIT(HP_425) | __BIT(HP_433))
sys/arch/hppa/hppa/trap.c
481
#define __PABIT(x) __BIT(31 - (x))
sys/arch/hppa/include/pmap.h
88
#define PV_KENTER __BIT(0)
sys/arch/hppa/include/proc.h
55
#define MDP_OLDSPACE __BIT(0)
sys/arch/i386/pci/elan520.c
1000
pcihostmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_PCIHOSTMAP_PCI_IRQ_MAP);
sys/arch/i386/pci/elan520.c
1147
wpvmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_WPVMAP_INT_MAP);
sys/arch/i386/pci/elan520.c
1338
sc->sc_mpicmode | __BIT(ELAN_IRQ));
sys/arch/i386/pci/elan520reg.h
110
#define MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_SEL __BIT(13)
sys/arch/i386/pci/elan520reg.h
112
#define MMCR_HBMSTIRQCTL_M_TABRT_IRQ_SEL __BIT(12)
sys/arch/i386/pci/elan520reg.h
114
#define MMCR_HBMSTIRQCTL_M_MABRT_IRQ_SEL __BIT(11)
sys/arch/i386/pci/elan520reg.h
116
#define MMCR_HBMSTIRQCTL_M_SERR_IRQ_SEL __BIT(10)
sys/arch/i386/pci/elan520reg.h
118
#define MMCR_HBMSTIRQCTL_M_RPER_IRQ_SEL __BIT(9)
sys/arch/i386/pci/elan520reg.h
120
#define MMCR_HBMSTIRQCTL_M_DPER_IRQ_SEL __BIT(8)
sys/arch/i386/pci/elan520reg.h
125
#define MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB __BIT(5)
sys/arch/i386/pci/elan520reg.h
127
#define MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB __BIT(4)
sys/arch/i386/pci/elan520reg.h
129
#define MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB __BIT(3)
sys/arch/i386/pci/elan520reg.h
131
#define MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB __BIT(2)
sys/arch/i386/pci/elan520reg.h
133
#define MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB __BIT(1)
sys/arch/i386/pci/elan520reg.h
135
#define MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB __BIT(0)
sys/arch/i386/pci/elan520reg.h
147
#define MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_SEL __BIT(10)
sys/arch/i386/pci/elan520reg.h
148
#define MMCR_HBTGTIRQCTL_T_APER_IRQ_SEL __BIT(9)
sys/arch/i386/pci/elan520reg.h
149
#define MMCR_HBTGTIRQCTL_T_DPER_IRQ_SEL __BIT(8)
sys/arch/i386/pci/elan520reg.h
154
#define MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB __BIT(2)
sys/arch/i386/pci/elan520reg.h
156
#define MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB __BIT(1)
sys/arch/i386/pci/elan520reg.h
158
#define MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB __BIT(0)
sys/arch/i386/pci/elan520reg.h
169
#define MMCR_HBMSTIRQSTA_M_RTRTO_IRQ_STA __BIT(5)
sys/arch/i386/pci/elan520reg.h
170
#define MMCR_HBMSTIRQSTA_M_TABRT_IRQ_STA __BIT(4)
sys/arch/i386/pci/elan520reg.h
171
#define MMCR_HBMSTIRQSTA_M_MABRT_IRQ_STA __BIT(3)
sys/arch/i386/pci/elan520reg.h
172
#define MMCR_HBMSTIRQSTA_M_SERR_IRQ_STA __BIT(2)
sys/arch/i386/pci/elan520reg.h
173
#define MMCR_HBMSTIRQSTA_M_RPER_IRQ_STA __BIT(1)
sys/arch/i386/pci/elan520reg.h
174
#define MMCR_HBMSTIRQSTA_M_DPER_IRQ_STA __BIT(0)
sys/arch/i386/pci/elan520reg.h
192
#define MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA __BIT(2)
sys/arch/i386/pci/elan520reg.h
193
#define MMCR_HBTGTIRQSTA_T_APER_IRQ_STA __BIT(1)
sys/arch/i386/pci/elan520reg.h
194
#define MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA __BIT(0)
sys/arch/i386/pci/elan520reg.h
203
#define MMCR_PCIHOSTMAP_PCI_NMI_ENB __BIT(8)
sys/arch/i386/pci/elan520reg.h
208
#define MMCR_PICICR_NMI_DONE __BIT(7)
sys/arch/i386/pci/elan520reg.h
209
#define MMCR_PICICR_NMI_ENB __BIT(6)
sys/arch/i386/pci/elan520reg.h
211
#define MMCR_PICICR_S2_GINT_MODE __BIT(2)
sys/arch/i386/pci/elan520reg.h
212
#define MMCR_PICICR_S1_GINT_MODE __BIT(1)
sys/arch/i386/pci/elan520reg.h
213
#define MMCR_PICICR_M_GINT_MODE __BIT(0)
sys/arch/i386/pci/elan520reg.h
231
#define MMCR_ADDDECCTL_WPV_INT_ENB __BIT(7)
sys/arch/i386/pci/elan520reg.h
234
#define MMCR_WPVSTA_WPV_STA __BIT(15)
sys/arch/i386/pci/elan520reg.h
255
#define MMCR_PAR_ATTR_NOEXEC __SHIFTIN(__BIT(2), MMCR_PAR_ATTR)
sys/arch/i386/pci/elan520reg.h
256
#define MMCR_PAR_ATTR_NOCACHE __SHIFTIN(__BIT(1), MMCR_PAR_ATTR)
sys/arch/i386/pci/elan520reg.h
257
#define MMCR_PAR_ATTR_NOWRITE __SHIFTIN(__BIT(0), MMCR_PAR_ATTR)
sys/arch/i386/pci/elan520reg.h
258
#define MMCR_PAR_PG_SZ __BIT(25)
sys/arch/i386/pci/elan520reg.h
65
#define MMCR_DBCTL_RAB_ENB __BIT(4) /* enable read-ahead */
sys/arch/i386/pci/elan520reg.h
71
#define MMCR_DBCTL_WB_FLUSH __BIT(1) /* write 1 to flush wr buf */
sys/arch/i386/pci/elan520reg.h
72
#define MMCR_DBCTL_WB_ENB __BIT(0) /* enable write buffer */
sys/arch/i386/pci/elan520reg.h
74
#define MMCR_HBCTL_PCI_RST __BIT(15)
sys/arch/i386/pci/elan520reg.h
75
#define MMCR_HBCTL_T_PURGE_RD_ENB __BIT(10)
sys/arch/i386/pci/elan520reg.h
85
#define MMCR_HBCTL_M_WPOST_ENB __BIT(3)
sys/arch/i386/pci/elan520reg.h
87
#define MMCR_SYSARBCTL_CNCR_MODE_ENB __BIT(1)
sys/arch/i386/pci/elan520reg.h
88
#define MMCR_SYSARBCTL_GNT_TO_INT_ENB __BIT(0) /* 1: interrupt when the
sys/arch/i386/pci/elan520reg.h
94
#define MMCR_PCIARBSTA_GNT_TO_STA __BIT(7)
sys/arch/i386/pci/geodereg.h
101
#define SC1100_WDSTS_WDINT __BIT(1)
sys/arch/i386/pci/geodereg.h
105
#define SC1100_WDSTS_WDOVF __BIT(0)
sys/arch/i386/pci/geodereg.h
123
#define SC1100_TMSTS_OVFL __BIT(0) /* set: overflow */
sys/arch/i386/pci/geodereg.h
126
#define SC1100_TMCNFG_TM27MPD __BIT(2) /* set: power down on SUSPA# */
sys/arch/i386/pci/geodereg.h
127
#define SC1100_TMCNFG_TMCLKSEL __BIT(1) /* set: 27MHz clock, clear: 1MHz */
sys/arch/i386/pci/geodereg.h
128
#define SC1100_TMCNFG_TMEN __BIT(0) /* set: timer interrupt enabled */
sys/arch/i386/pci/geodereg.h
57
#define SC1100_WDCNFG_WD32KPD __BIT(8)
sys/arch/i386/pci/geodereg.h
89
#define SC1100_WDSTS_RESERVED __BIT(7,4) /* write as read */
sys/arch/i386/pci/geodereg.h
93
#define SC1100_WDSTS_WDRST __BIT(3)
sys/arch/i386/pci/geodereg.h
97
#define SC1100_WDSTS_WDSMI __BIT(2)
sys/arch/m68k/include/linux_bootinfo.h
137
#define BI_CPU_68020 __BIT(0)
sys/arch/m68k/include/linux_bootinfo.h
138
#define BI_CPU_68030 __BIT(1)
sys/arch/m68k/include/linux_bootinfo.h
139
#define BI_CPU_68040 __BIT(2)
sys/arch/m68k/include/linux_bootinfo.h
140
#define BI_CPU_68060 __BIT(3)
sys/arch/m68k/include/linux_bootinfo.h
141
#define BI_CPU_COLDFIRE __BIT(4)
sys/arch/m68k/include/linux_bootinfo.h
146
#define BI_FPU_68881 __BIT(0)
sys/arch/m68k/include/linux_bootinfo.h
147
#define BI_FPU_68882 __BIT(1)
sys/arch/m68k/include/linux_bootinfo.h
148
#define BI_FPU_68040 __BIT(2)
sys/arch/m68k/include/linux_bootinfo.h
149
#define BI_FPU_68060 __BIT(3)
sys/arch/m68k/include/linux_bootinfo.h
150
#define BI_FPU_SUNFPA __BIT(4)
sys/arch/m68k/include/linux_bootinfo.h
151
#define BI_FPU_COLDFIRE __BIT(5)
sys/arch/m68k/include/linux_bootinfo.h
156
#define BI_MMU_68851 __BIT(0)
sys/arch/m68k/include/linux_bootinfo.h
157
#define BI_MMU_68030 __BIT(1)
sys/arch/m68k/include/linux_bootinfo.h
158
#define BI_MMU_68040 __BIT(2)
sys/arch/m68k/include/linux_bootinfo.h
159
#define BI_MMU_68060 __BIT(3)
sys/arch/m68k/include/linux_bootinfo.h
160
#define BI_MMU_APOLLO __BIT(4)
sys/arch/m68k/include/linux_bootinfo.h
161
#define BI_MMU_SUN3 __BIT(5)
sys/arch/m68k/include/linux_bootinfo.h
162
#define BI_MMU_COLDFIRE __BIT(6)
sys/arch/m68k/include/mmu_30.h
76
#define TT30_E __BIT(15) /* Enable transparent translation */
sys/arch/m68k/include/mmu_30.h
77
#define TT30_CI __BIT(10) /* Cache Inhibit */
sys/arch/m68k/include/mmu_30.h
78
#define TT30_RW __BIT(9) /* Read(1) or Write(0) translated */
sys/arch/m68k/include/mmu_30.h
79
#define TT30_RWM __BIT(8) /* RW field used(0) or ignored(1) */
sys/arch/m68k/include/mmu_40.h
104
#define UTE40_U __BIT(3) /* Used (referenced) */
sys/arch/m68k/include/mmu_40.h
105
#define UTE40_W __BIT(2) /* Write Protected */
sys/arch/m68k/include/mmu_40.h
131
#define PTE40_UR_x __BIT(12) /* User Reserved (extra avail if 8K) */
sys/arch/m68k/include/mmu_40.h
132
#define PTE40_UR __BIT(11) /* User Reserved */
sys/arch/m68k/include/mmu_40.h
133
#define PTE40_G __BIT(10) /* Global */
sys/arch/m68k/include/mmu_40.h
134
#define PTE40_U1 __BIT(9) /* User Page Attribute 1 */
sys/arch/m68k/include/mmu_40.h
135
#define PTE40_U0 __BIT(8) /* User Page Attribute 0 */
sys/arch/m68k/include/mmu_40.h
136
#define PTE40_S __BIT(7) /* Supervisor Protected */
sys/arch/m68k/include/mmu_40.h
142
#define PTE40_M __BIT(4) /* Modified */
sys/arch/m68k/include/mmu_40.h
143
#define PTE40_U __BIT(3) /* Used (referenced) */
sys/arch/m68k/include/mmu_40.h
144
#define PTE40_W __BIT(2) /* Write Protected */
sys/arch/m68k/include/mmu_40.h
175
#define TCR40_E __BIT(15) /* enable translation */
sys/arch/m68k/include/mmu_40.h
176
#define TCR40_P __BIT(14) /* page size: 0=4K 1=8K */
sys/arch/m68k/include/mmu_40.h
186
#define TTR40_E __BIT(15) /* enable TTR */
sys/arch/m68k/include/mmu_40.h
203
#define MMUSR40_B __BIT(11) /* bus error */
sys/arch/m68k/include/mmu_40.h
211
#define MMUSR40_T __BIT(1) /* Transparent Translation hit */
sys/arch/m68k/include/mmu_40.h
78
#define LA40_L1_COUNT __BIT(LA40_L1_NBITS)
sys/arch/m68k/include/mmu_40.h
79
#define LA40_L2_COUNT __BIT(LA40_L2_NBITS)
sys/arch/m68k/include/mmu_40.h
80
#define LA40_L3_COUNT __BIT(LA40_L3_NBITS)
sys/arch/m68k/include/mmu_51.h
101
#define DTE51_SG __BIT(9) /* L: Shared Globally */
sys/arch/m68k/include/mmu_51.h
102
#define DTE51_S __BIT(8) /* L: Supervisor protected */
sys/arch/m68k/include/mmu_51.h
103
#define DTE51_U __BIT(3) /* Used */
sys/arch/m68k/include/mmu_51.h
104
#define DTE51_WP __BIT(2) /* Write Protected */
sys/arch/m68k/include/mmu_51.h
145
#define PTE51_SG __BIT(9) /* L: Shared Globally */
sys/arch/m68k/include/mmu_51.h
146
#define PTE51_S __BIT(8) /* L: Supervisor protected */
sys/arch/m68k/include/mmu_51.h
147
#define PTE51_G __BIT(7) /* Gate allowed */
sys/arch/m68k/include/mmu_51.h
148
#define PTE51_CI __BIT(6) /* Cache inhibit */
sys/arch/m68k/include/mmu_51.h
149
#define PTE51_L __BIT(5) /* Lock entry */
sys/arch/m68k/include/mmu_51.h
150
#define PTE51_M __BIT(4) /* Modified */
sys/arch/m68k/include/mmu_51.h
151
#define PTE51_U __BIT(3) /* Used */
sys/arch/m68k/include/mmu_51.h
152
#define PTE51_WP __BIT(2) /* Write Protected */
sys/arch/m68k/include/mmu_51.h
206
#define PCSR51_F __BIT(15) /* Flush(ed) */
sys/arch/m68k/include/mmu_51.h
207
#define PCSR51_LW __BIT(14) /* Lock Warning */
sys/arch/m68k/include/mmu_51.h
213
#define TCR51_E __BIT(31) /* Enable translation */
sys/arch/m68k/include/mmu_51.h
214
#define TCR51_SRE __BIT(25) /* Supervisor Root Enable */
sys/arch/m68k/include/mmu_51.h
215
#define TCR51_FCL __BIT(24) /* Function Code Lookup */
sys/arch/m68k/include/mmu_51.h
249
#define AC51_MC __BIT(7) /* Module Control */
sys/arch/m68k/include/mmu_51.h
256
#define PSR51_B __BIT(15) /* Bus Error */
sys/arch/m68k/include/mmu_51.h
257
#define PSR51_L __BIT(14) /* Limit Violation */
sys/arch/m68k/include/mmu_51.h
258
#define PSR51_S __BIT(13) /* Supervisor Violation */
sys/arch/m68k/include/mmu_51.h
259
#define PSR51_A __BIT(12) /* Access Level Violation */
sys/arch/m68k/include/mmu_51.h
260
#define PSR51_W __BIT(11) /* Write Protected */
sys/arch/m68k/include/mmu_51.h
261
#define PSR51_I __BIT(10) /* Invalid */
sys/arch/m68k/include/mmu_51.h
262
#define PSR51_M __BIT(9) /* Modified */
sys/arch/m68k/include/mmu_51.h
263
#define PSR51_G __BIT(8) /* Gate */
sys/arch/m68k/include/mmu_51.h
264
#define PSR51_C __BIT(7) /* Globally Shareable */
sys/arch/m68k/include/mmu_51.h
97
#define DTE51_LOWER __BIT(31) /* L: Index limit is lower limit */
sys/arch/m68k/include/pcr.h
37
#define PCR_ESS __BIT(0) /* enable superscalar dispatch */
sys/arch/m68k/include/pcr.h
38
#define PCR_DFP __BIT(1) /* disable floating point unit */
sys/arch/m68k/include/pcr.h
40
#define PCR_EDEBUG __BIT(7) /* enable debug features */
sys/arch/m68k/include/pmap_68k.h
132
#define PV_F_CI_VAC __BIT(0) /* mapping CI due to VAC alias */
sys/arch/m68k/include/pmap_68k.h
133
#define PV_F_CI_USR __BIT(1) /* mapping CI due to user request */
sys/arch/m68k/include/pmap_68k.h
219
#define PMBM_F_VAONLY __BIT(0)
sys/arch/m68k/include/pmap_68k.h
220
#define PMBM_F_FIXEDVA __BIT(1)
sys/arch/m68k/include/pmap_68k.h
221
#define PMBM_F_KEEPOUT __BIT(2)
sys/arch/m68k/include/pmap_68k.h
222
#define PMBM_F_CI __BIT(3) /* cache-inhibited mapping */
sys/arch/m68k/include/pmap_68k.h
223
#define PMBM_F_CWT __BIT(4) /* write-through cacheable mapping */
sys/arch/m68k/include/pmap_68k.h
224
#define PMBM_F_RO __BIT(5) /* read-only mapping */
sys/arch/m68k/include/pmap_68k.h
287
#define LA2L_L2_COUNT __BIT(LA2L_L2_NBITS) /* 2048 / 1024 */
sys/arch/m68k/include/pmap_68k.h
290
#define LA2L_L1_COUNT __BIT(LA2L_L1_NBITS) /* 256 / 1024 */
sys/arch/m68k/include/pmap_68k.h
319
#define NBSEG2L __BIT(SEGSHIFT2L)
sys/arch/m68k/include/pmap_68k.h
320
#define NBSEG3L __BIT(SEGSHIFT3L)
sys/arch/m68k/include/pmap_68k.h
321
#define NBSEG13L __BIT(SEG1SHIFT3L)
sys/arch/m68k/include/pmap_68k.h
356
#define PVH_CI __BIT(2)
sys/arch/m68k/include/pmap_motorola.h
288
#define PMBM_F_VAONLY __BIT(0)
sys/arch/m68k/include/pmap_motorola.h
289
#define PMBM_F_FIXEDVA __BIT(1)
sys/arch/m68k/include/pmap_motorola.h
290
#define PMBM_F_KEEPOUT __BIT(2)
sys/arch/m68k/include/pmap_motorola.h
291
#define PMBM_F_CI __BIT(3) /* cache-inhibited mapping */
sys/arch/m68k/include/pmap_motorola.h
292
#define PMBM_F_CWT __BIT(4) /* write-through cacheable mapping */
sys/arch/m68k/include/pmap_motorola.h
293
#define PMBM_F_RO __BIT(5) /* read-only mapping */
sys/arch/m68k/include/pte_coldfire.h
45
#define MMUTR_SG __BIT(1) // Shared Global
sys/arch/m68k/include/pte_coldfire.h
46
#define MMUTR_V __BIT(0) // Valid
sys/arch/m68k/include/pte_coldfire.h
60
#define MMUDR_SP __BIT(5) // Supervisor Protect
sys/arch/m68k/include/pte_coldfire.h
61
#define MMUDR_R __BIT(4) // Read Access
sys/arch/m68k/include/pte_coldfire.h
62
#define MMUDR_W __BIT(3) // Write Access
sys/arch/m68k/include/pte_coldfire.h
63
#define MMUDR_X __BIT(2) // Execute Access
sys/arch/m68k/include/pte_coldfire.h
64
#define MMUDR_LK __BIT(1) // Lock Entry
sys/arch/m68k/include/pte_coldfire.h
65
#define MMUDR_MBZ0 __BIT(0) // Must be zero
sys/arch/m68k/include/pte_motorola.h
106
#define PG_W __BIT(8) /* 851 unused bit XXX040 PTE40_U0 */
sys/arch/m68k/m68k/pmap_68k.c
2249
#define PRM_TFLUSH __BIT(0)
sys/arch/m68k/m68k/pmap_68k.c
2250
#define PRM_CFLUSH __BIT(1)
sys/arch/mac68k/obio/ascreg.h
102
#define DISABLEHALFIRQ __BIT(0)
sys/arch/mac68k/obio/ascreg.h
105
#define DFAC_CLOCK (__BIT(4))
sys/arch/mac68k/obio/ascreg.h
106
#define DFAC_DATA (__BIT(3))
sys/arch/mac68k/obio/ascreg.h
107
#define DFAC_LATCH (__BIT(0))
sys/arch/mac68k/obio/ascreg.h
51
#define UNDERRUN __BIT(7)
sys/arch/mac68k/obio/ascreg.h
52
#define STEREO __BIT(1)
sys/arch/mac68k/obio/ascreg.h
53
#define ANAPWM __BIT(0)
sys/arch/mac68k/obio/ascreg.h
56
#define CLEARFIFO __BIT(7)
sys/arch/mac68k/obio/ascreg.h
57
#define NONCOMP __BIT(1)
sys/arch/mac68k/obio/ascreg.h
58
#define ROMCOMP __BIT(0)
sys/arch/mac68k/obio/ascreg.h
61
#define A_HALF __BIT(0)
sys/arch/mac68k/obio/ascreg.h
62
#define A_FULL __BIT(1)
sys/arch/mac68k/obio/ascreg.h
63
#define B_HALF __BIT(2)
sys/arch/mac68k/obio/ascreg.h
64
#define B_FULL __BIT(3)
sys/arch/mac68k/obio/ascreg.h
74
#define RECORDA __BIT(0)
sys/arch/mac68k/obio/ascreg.h
75
#define REC22KHZ __BIT(1)
sys/arch/macppc/dev/ofw_i2c_machdep.c
52
#define OFW_I2C_ADDRESS_CHMASK __BIT(8)
sys/arch/mips/adm5120/adm5120_extio.c
117
{"wdc", ADM5120_BASE_EXTIO0, 0, __BIT(4), 1},
sys/arch/mips/adm5120/dev/admpci.c
107
#define ADMPCI_TAG_DEVICE_BRIDGE __BIT(11)
sys/arch/mips/adm5120/dev/if_admswreg.h
100
#define ADMSW_INTR_SLD __BIT(1)
sys/arch/mips/adm5120/dev/if_admswreg.h
101
#define ADMSW_INTR_SHD __BIT(0)
sys/arch/mips/adm5120/dev/if_admswreg.h
72
#define ADMSW_BOOT_DONE_BO __BIT(0)
sys/arch/mips/adm5120/dev/if_admswreg.h
79
#define ADMSW_INTR_CPUH __BIT(24)
sys/arch/mips/adm5120/dev/if_admswreg.h
80
#define ADMSW_INTR_SDE __BIT(23)
sys/arch/mips/adm5120/dev/if_admswreg.h
81
#define ADMSW_INTR_RDE __BIT(22)
sys/arch/mips/adm5120/dev/if_admswreg.h
82
#define ADMSW_INTR_W1TE __BIT(21)
sys/arch/mips/adm5120/dev/if_admswreg.h
83
#define ADMSW_INTR_W0TE __BIT(20)
sys/arch/mips/adm5120/dev/if_admswreg.h
84
#define ADMSW_INTR_MI __BIT(19)
sys/arch/mips/adm5120/dev/if_admswreg.h
85
#define ADMSW_INTR_PSC __BIT(18)
sys/arch/mips/adm5120/dev/if_admswreg.h
86
#define ADMSW_INTR_BCS __BIT(16)
sys/arch/mips/adm5120/dev/if_admswreg.h
87
#define ADMSW_INTR_MD __BIT(15)
sys/arch/mips/adm5120/dev/if_admswreg.h
88
#define ADMSW_INTR_GQF __BIT(14)
sys/arch/mips/adm5120/dev/if_admswreg.h
89
#define ADMSW_INTR_CPQ __BIT(13)
sys/arch/mips/adm5120/dev/if_admswreg.h
90
#define ADMSW_INTR_P5QF __BIT(11)
sys/arch/mips/adm5120/dev/if_admswreg.h
91
#define ADMSW_INTR_P4QF __BIT(10)
sys/arch/mips/adm5120/dev/if_admswreg.h
92
#define ADMSW_INTR_P3QF __BIT(9)
sys/arch/mips/adm5120/dev/if_admswreg.h
93
#define ADMSW_INTR_P2QF __BIT(8)
sys/arch/mips/adm5120/dev/if_admswreg.h
94
#define ADMSW_INTR_P1QF __BIT(7)
sys/arch/mips/adm5120/dev/if_admswreg.h
95
#define ADMSW_INTR_P0QF __BIT(6)
sys/arch/mips/adm5120/dev/if_admswreg.h
96
#define ADMSW_INTR_LDF __BIT(5)
sys/arch/mips/adm5120/dev/if_admswreg.h
97
#define ADMSW_INTR_HDF __BIT(4)
sys/arch/mips/adm5120/dev/if_admswreg.h
98
#define ADMSW_INTR_RLD __BIT(3)
sys/arch/mips/adm5120/dev/if_admswreg.h
99
#define ADMSW_INTR_RHD __BIT(2)
sys/arch/mips/adm5120/include/adm5120reg.h
137
#define ADM5120_WDOG0_WTTR __BIT(31) /* 0: do not reset,
sys/arch/mips/adm5120/include/adm5120reg.h
140
#define ADM5120_WDOG1_WDE __BIT(31) /* 0: deactivate,
sys/arch/mips/adm5120/include/adm5120reg.h
150
#define ADM5120_WDOG_RSVD __BIT(15)
sys/arch/mips/adm5120/include/adm5120reg.h
167
#define ADM5120_GPIO2_EW __BIT(6) /* 1: enable wait state pin,
sys/arch/mips/adm5120/include/adm5120reg.h
173
#define ADM5120_GPIO2_CSX1 __BIT(5) /* 1: GPIO[3:4] act as
sys/arch/mips/adm5120/include/adm5120reg.h
180
#define ADM5120_GPIO2_CSX0 __BIT(4) /* 1: GPIO[1:2] act as
sys/arch/mips/adm5120/include/adm5120reg.h
191
#define ADM5120_MPMC_CONTROL_DWB __BIT(3) /* write 1 to
sys/arch/mips/adm5120/include/adm5120reg.h
197
#define ADM5120_MPMC_CONTROL_LPM __BIT(2) /* 1: activate low-power
sys/arch/mips/adm5120/include/adm5120reg.h
201
#define ADM5120_MPMC_CONTROL_AM __BIT(1) /* 1: address mirror:
sys/arch/mips/adm5120/include/adm5120reg.h
207
#define ADM5120_MPMC_CONTROL_ME __BIT(0) /* 0: disable MPMC.
sys/arch/mips/adm5120/include/adm5120reg.h
214
#define ADM5120_MPMC_STATUS_SRA __BIT(2) /* read-only
sys/arch/mips/adm5120/include/adm5120reg.h
221
#define ADM5120_MPMC_STATUS_WBS __BIT(1) /* read-only
sys/arch/mips/adm5120/include/adm5120reg.h
226
#define ADM5120_MPMC_STATUS_BU __BIT(0) /* read-only MPMC
sys/arch/mips/adm5120/include/adm5120reg.h
242
#define ADM5120_MPMC_SC_WP __BIT(20) /* 1: write protect */
sys/arch/mips/adm5120/include/adm5120reg.h
243
#define ADM5120_MPMC_SC_BE __BIT(20) /* 1: enable write buffer */
sys/arch/mips/adm5120/include/adm5120reg.h
245
#define ADM5120_MPMC_SC_EW __BIT(8) /* 1: enable extended wait;
sys/arch/mips/adm5120/include/adm5120reg.h
247
#define ADM5120_MPMC_SC_BLS __BIT(7) /* 0: byte line state pins
sys/arch/mips/adm5120/include/adm5120reg.h
255
#define ADM5120_MPMC_SC_CCP __BIT(6) /* 0: chip select is active low,
sys/arch/mips/adm5120/include/adm5120reg.h
259
#define ADM5120_MPMC_SC_PM __BIT(3) /* 0: page mode disabled,
sys/arch/mips/adm5120/include/adm5120reg.h
263
#define ADM5120_MPMC_SC_RSVD3 __BIT(2)
sys/arch/mips/atheros/ar_intr.c
165
const uint32_t mask = misc_intmask_get() | __BIT(irq);
sys/arch/mips/atheros/ar_intr.c
185
const uint32_t mask = misc_intmask_get() & ~__BIT(ih->ih_irq);
sys/arch/mips/atheros/ar_intr.c
231
ipending *= __BIT(31) / (MIPS_INT_MASK_0 << (NINTRS-1));
sys/arch/mips/atheros/ar_intr.c
238
KASSERT(ipending & __BIT(31));
sys/arch/mips/atheros/include/ar5312reg.h
115
#define AR5312_RESET_SYSTEM __BIT(0)
sys/arch/mips/atheros/include/ar5312reg.h
116
#define AR5312_RESET_CPU __BIT(1)
sys/arch/mips/atheros/include/ar5312reg.h
117
#define AR5312_RESET_WLAN0 __BIT(2) /* mac & bb */
sys/arch/mips/atheros/include/ar5312reg.h
118
#define AR5312_RESET_PHY0 __BIT(3) /* enet phy */
sys/arch/mips/atheros/include/ar5312reg.h
119
#define AR5312_RESET_PHY1 __BIT(4) /* enet phy */
sys/arch/mips/atheros/include/ar5312reg.h
120
#define AR5312_RESET_ENET0 __BIT(5) /* mac */
sys/arch/mips/atheros/include/ar5312reg.h
121
#define AR5312_RESET_ENET1 __BIT(6) /* mac */
sys/arch/mips/atheros/include/ar5312reg.h
122
#define AR5312_RESET_UART0 __BIT(8) /* mac */
sys/arch/mips/atheros/include/ar5312reg.h
123
#define AR5312_RESET_WLAN1 __BIT(9) /* mac & bb */
sys/arch/mips/atheros/include/ar5312reg.h
124
#define AR5312_RESET_APB __BIT(10) /* bridge */
sys/arch/mips/atheros/include/ar5312reg.h
125
#define AR5312_RESET_WARM_CPU __BIT(16)
sys/arch/mips/atheros/include/ar5312reg.h
126
#define AR5312_RESET_WARM_WLAN0_MAC __BIT(17)
sys/arch/mips/atheros/include/ar5312reg.h
127
#define AR5312_RESET_WARM_WLAN0_BB __BIT(18)
sys/arch/mips/atheros/include/ar5312reg.h
128
#define AR5312_RESET_NMI __BIT(20)
sys/arch/mips/atheros/include/ar5312reg.h
129
#define AR5312_RESET_WARM_WLAN1_MAC __BIT(21)
sys/arch/mips/atheros/include/ar5312reg.h
130
#define AR5312_RESET_WARM_WLAN1_BB __BIT(22)
sys/arch/mips/atheros/include/ar5312reg.h
131
#define AR5312_RESET_LOCAL_BUS __BIT(23)
sys/arch/mips/atheros/include/ar5312reg.h
132
#define AR5312_RESET_WDOG __BIT(24)
sys/arch/mips/atheros/include/ar5312reg.h
137
#define AR5312_CLOCKCTL_DOUBLER __BIT(16)
sys/arch/mips/atheros/include/ar5312reg.h
144
#define AR5312_ENABLE_WLAN0 __BIT(0)
sys/arch/mips/atheros/include/ar5312reg.h
145
#define AR5312_ENABLE_ENET0 __BIT(1)
sys/arch/mips/atheros/include/ar5312reg.h
146
#define AR5312_ENABLE_ENET1 __BIT(2)
sys/arch/mips/atheros/include/ar5312reg.h
72
#define AR5312_FLASHCTL_RBLE __BIT(10) /* rd byte enable */
sys/arch/mips/atheros/include/ar5312reg.h
83
#define AR5312_FLASHCTL_E __BIT(19) /* enable */
sys/arch/mips/atheros/include/ar5312reg.h
84
#define AR5312_FLASHCTL_BUSERR __BIT(24) /* buserr */
sys/arch/mips/atheros/include/ar5312reg.h
85
#define AR5312_FLASHCTL_WPERR __BIT(25) /* wperr */
sys/arch/mips/atheros/include/ar5312reg.h
86
#define AR5312_FLASHCTL_WP __BIT(26) /* wp */
sys/arch/mips/atheros/include/ar5312reg.h
87
#define AR5312_FLASHCTL_BM __BIT(27) /* bm */
sys/arch/mips/atheros/include/ar9344reg.h
107
#define AR7100_CPU_PLL_PLL_BYPASS __BIT(1)
sys/arch/mips/atheros/include/ar9344reg.h
108
#define AR7100_PLL_PLL_POWER_DOWN __BIT(0)
sys/arch/mips/atheros/include/ar9344reg.h
110
#define AR9344_DDR_PLL_CONFIG_UPDATING __BIT(31)
sys/arch/mips/atheros/include/ar9344reg.h
111
#define AR9344_DDR_PLL_CONFIG_PLLPWD __BIT(30)
sys/arch/mips/atheros/include/ar9344reg.h
118
#define AR9344_CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL __BIT(24)
sys/arch/mips/atheros/include/ar9344reg.h
119
#define AR9344_CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASRT __BIT(23)
sys/arch/mips/atheros/include/ar9344reg.h
120
#define AR9344_CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT __BIT(22)
sys/arch/mips/atheros/include/ar9344reg.h
121
#define AR9344_CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL __BIT(21)
sys/arch/mips/atheros/include/ar9344reg.h
122
#define AR9344_CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL __BIT(20)
sys/arch/mips/atheros/include/ar9344reg.h
126
#define AR9344_CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS __BIT(4)
sys/arch/mips/atheros/include/ar9344reg.h
127
#define AR9344_CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS __BIT(3)
sys/arch/mips/atheros/include/ar9344reg.h
128
#define AR9344_CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS __BIT(2)
sys/arch/mips/atheros/include/ar9344reg.h
129
#define AR9344_CPU_DDR_CLOCK_CONTROL_RESET_SWITCH __BIT(1)
sys/arch/mips/atheros/include/ar9344reg.h
152
#define ARCHIP_WDOG_CTL_LAST __BIT(31)
sys/arch/mips/atheros/include/ar9344reg.h
159
#define AR9344_RESETCTL_I2S_RESET __BIT(0)
sys/arch/mips/atheros/include/ar9344reg.h
160
#define AR7100_RESETCTL_PCI_CORE_RESET __BIT(0)
sys/arch/mips/atheros/include/ar9344reg.h
161
#define AR9344_RESETCTL_MBOX_RESET __BIT(1)
sys/arch/mips/atheros/include/ar9344reg.h
162
#define AR7100_RESETCTL_PCI_BUS_RESET __BIT(1)
sys/arch/mips/atheros/include/ar9344reg.h
163
#define AR9344_RESETCTL_LUT_RESET __BIT(2)
sys/arch/mips/atheros/include/ar9344reg.h
164
#define AR9344_RESETCTL_USB_PHY_SUSPEND_OVERRIDE __BIT(3)
sys/arch/mips/atheros/include/ar9344reg.h
165
#define ARCHIP_RESETCTL_USB_PHY_RESET __BIT(4)
sys/arch/mips/atheros/include/ar9344reg.h
166
#define ARCHIP_RESETCTL_USB_HOST_RESET __BIT(5)
sys/arch/mips/atheros/include/ar9344reg.h
167
#define AR9344_RESETCTL_PCIE_RESET __BIT(6)
sys/arch/mips/atheros/include/ar9344reg.h
168
#define AR7100_RESETCTL_USB_OHCI_DLL_RESET __BIT(6)
sys/arch/mips/atheros/include/ar9344reg.h
169
#define AR9344_RESETCTL_PCIE_PHY_RESET __BIT(7)
sys/arch/mips/atheros/include/ar9344reg.h
170
#define AR9344_RESETCTL_ETH_SWITCH_RESET __BIT(8)
sys/arch/mips/atheros/include/ar9344reg.h
171
#define AR7100_RESETCTL_GMAC0_PHY_RESET __BIT(8)
sys/arch/mips/atheros/include/ar9344reg.h
172
#define ARCHIP_RESETCTL_GMAC0_MAC_RESET __BIT(9)
sys/arch/mips/atheros/include/ar9344reg.h
173
#define AR9344_RESETCTL_HOST_DMA_INT __BIT(10)
sys/arch/mips/atheros/include/ar9344reg.h
174
#define AR9344_RESETCTL_USB_PHY_ARESET __BIT(11)
sys/arch/mips/atheros/include/ar9344reg.h
175
#define AR9344_RESETCTL_ETH_SWITCH_ARESET __BIT(12)
sys/arch/mips/atheros/include/ar9344reg.h
176
#define AR7100_RESETCTL_GMAC1_PHY_RESET __BIT(12)
sys/arch/mips/atheros/include/ar9344reg.h
177
#define ARCHIP_RESETCTL_GMAC1_MAC_RESET __BIT(13)
sys/arch/mips/atheros/include/ar9344reg.h
178
#define AR9344_RESETCTL_NANDF_RESET __BIT(14)
sys/arch/mips/atheros/include/ar9344reg.h
179
#define AR9344_RESETCTL_USB_PHY_PLL_PWD_EXT __BIT(15)
sys/arch/mips/atheros/include/ar9344reg.h
180
#define ARCHIP_RESETCTL_DDR_RESET __BIT(16)
sys/arch/mips/atheros/include/ar9344reg.h
181
#define AR9344_RESETCTL_UART1_RESET __BIT(17)
sys/arch/mips/atheros/include/ar9344reg.h
182
#define AR7100_RESETCTL_I2S_RESET __BIT(17)
sys/arch/mips/atheros/include/ar9344reg.h
183
#define AR9344_RESETCTL_PCIEEP_RESET __BIT(18)
sys/arch/mips/atheros/include/ar9344reg.h
184
#define AR7100_RESETCTL_SLIC_RESET __BIT(18)
sys/arch/mips/atheros/include/ar9344reg.h
185
#define AR9344_RESETCTL_HOST_RESET_INT __BIT(19)
sys/arch/mips/atheros/include/ar9344reg.h
186
#define AR7100_RESETCTL_DMA_RESET __BIT(19)
sys/arch/mips/atheros/include/ar9344reg.h
187
#define ARCHIP_RESETCTL_CPU_COLD_RESET __BIT(20)
sys/arch/mips/atheros/include/ar9344reg.h
188
#define ARCHIP_RESETCTL_CPU_NMI __BIT(21)
sys/arch/mips/atheros/include/ar9344reg.h
189
#define AR9344_RESETCTL_RESET_GMAC0_MDIO __BIT(22)
sys/arch/mips/atheros/include/ar9344reg.h
190
#define AR9344_RESETCTL_RESET_GMAC1_MDIO __BIT(23)
sys/arch/mips/atheros/include/ar9344reg.h
191
#define ARCHIP_RESETCTL_FULL_CHIP_RESET __BIT(24)
sys/arch/mips/atheros/include/ar9344reg.h
192
#define AR9344_RESETCTL_CHKSUM_ACC_RESET __BIT(25)
sys/arch/mips/atheros/include/ar9344reg.h
193
#define AR9344_RESETCTL_PCIEEP_RST_INT __BIT(26)
sys/arch/mips/atheros/include/ar9344reg.h
194
#define AR9344_RESETCTL_RTC_RESET __BIT(27)
sys/arch/mips/atheros/include/ar9344reg.h
195
#define ARCHIP_RESETCTL_EXTERNAL_RESET __BIT(28)
sys/arch/mips/atheros/include/ar9344reg.h
196
#define AR9344_RESETCTL_HDMA_RESET __BIT(29)
sys/arch/mips/atheros/include/ar9344reg.h
197
#define AR9344_RESETCTL_SLIC_RESET __BIT(30)
sys/arch/mips/atheros/include/ar9344reg.h
198
#define AR9344_RESETCTL_HOST_RESET __BIT(31)
sys/arch/mips/atheros/include/ar9344reg.h
230
#define AR9344_BOOTSTRAP_SOFTWARE_OPTION_8 __BIT(31)
sys/arch/mips/atheros/include/ar9344reg.h
231
#define AR9344_BOOTSTRAP_SOFTWARE_OPTION_7 __BIT(30)
sys/arch/mips/atheros/include/ar9344reg.h
232
#define AR9344_BOOTSTRAP_DDR_WIDTH __BIT(29)
sys/arch/mips/atheros/include/ar9344reg.h
233
#define AR9344_BOOTSTRAP_SOFTWARE_OPTION_5 __BIT(28)
sys/arch/mips/atheros/include/ar9344reg.h
234
#define AR9344_BOOTSTRAP_SOFTWARE_OPTION_4 __BIT(27)
sys/arch/mips/atheros/include/ar9344reg.h
235
#define AR9344_BOOTSTRAP_SOFTWARE_OPTION_3 __BIT(26)
sys/arch/mips/atheros/include/ar9344reg.h
236
#define AR9344_BOOTSTRAP_SOFTWARE_OPTION_2 __BIT(25)
sys/arch/mips/atheros/include/ar9344reg.h
237
#define AR9344_BOOTSTRAP_SOFTWARE_OPTION_1 __BIT(24)
sys/arch/mips/atheros/include/ar9344reg.h
238
#define AR9344_BOOTSTRAP_USB_MODE __BIT(7)
sys/arch/mips/atheros/include/ar9344reg.h
239
#define AR9344_BOOTSTRAP_EJTAG_MODE __BIT(5)
sys/arch/mips/atheros/include/ar9344reg.h
240
#define AR9344_BOOTSTRAP_REF_CLK_40 __BIT(4)
sys/arch/mips/atheros/include/ar9344reg.h
241
#define AR9344_BOOTSTRAP_BOOT_SELECT __BIT(2)
sys/arch/mips/atheros/include/ar9344reg.h
242
#define AR9344_BOOTSTRAP_SDRAM_DISABLE __BIT(1)
sys/arch/mips/atheros/include/ar9344reg.h
243
#define AR9344_BOOTSTRAP_DDR_SELECT __BIT(0)
sys/arch/mips/atheros/include/ar9344reg.h
314
#define AR7100_PCI_ERROR_PARITY __BIT(0)
sys/arch/mips/atheros/include/ar9344reg.h
315
#define AR7100_PCI_ERROR_FATAL __BIT(1)
sys/arch/mips/atheros/include/ar9344reg.h
321
#define AR9344_SPI_FUNCTION_SLEECT_FUNCTION_SELECT __BIT(0)
sys/arch/mips/atheros/include/ar9344reg.h
324
#define AR9344_SPI_CONTROL_SPI_RELOCATE __BIT(7)
sys/arch/mips/atheros/include/ar9344reg.h
325
#define AR9344_SPI_CONTROL_REMAP_DISABLE __BIT(6)
sys/arch/mips/atheros/include/ar9344reg.h
328
#define AR9344_SPI_IO_CONTROL_IO_CS2_DISABLE __BIT(18)
sys/arch/mips/atheros/include/ar9344reg.h
329
#define AR9344_SPI_IO_CONTROL_IO_CS1_DISABLE __BIT(17)
sys/arch/mips/atheros/include/ar9344reg.h
330
#define AR9344_SPI_IO_CONTROL_IO_CS0_DISABLE __BIT(16)
sys/arch/mips/atheros/include/ar9344reg.h
331
#define AR9344_SPI_IO_CONTROL_IO_CLK __BIT(8)
sys/arch/mips/atheros/include/ar9344reg.h
332
#define AR9344_SPI_IO_CONTROL_IO_DO __BIT(0)
sys/arch/mips/atheros/include/ar9344reg.h
336
#define AR9344_SPI_SHIFT_CNT_SHIFT_EN __BIT(31)
sys/arch/mips/atheros/include/ar9344reg.h
337
#define AR9344_SPI_SHIFT_CNT_SHIFT_CHNL_2 __BIT(30)
sys/arch/mips/atheros/include/ar9344reg.h
338
#define AR9344_SPI_SHIFT_CNT_SHIFT_CHNL_1 __BIT(29)
sys/arch/mips/atheros/include/ar9344reg.h
339
#define AR9344_SPI_SHIFT_CNT_SHIFT_CHNL_0 __BIT(28)
sys/arch/mips/atheros/include/ar9344reg.h
340
#define AR9344_SPI_SHIFT_CNT_SHIFT_CLKOUT __BIT(27)
sys/arch/mips/atheros/include/ar9344reg.h
341
#define AR9344_SPI_SHIFT_CNT_TERMINATE __BIT(26)
sys/arch/mips/atheros/include/ar9344reg.h
90
#define AR9344_CPU_PLL_CONFIG_UPDATING __BIT(31)
sys/arch/mips/atheros/include/ar9344reg.h
91
#define AR9344_CPU_PLL_CONFIG_PLLPWD __BIT(30)
sys/arch/mips/atheros/include/ar9344reg.h
98
#define AR7100_CPU_PLL_SW_UPDATE __BIT(31)
sys/arch/mips/atheros/include/ar9344reg.h
99
#define AR7100_PLL_LOCKED __BIT(30)
sys/arch/mips/cavium/dev/if_cnmac.c
1290
uint64_t wqmask = __BIT(sc->sc_powgroup);
sys/arch/mips/cavium/dev/octeon_asx.c
101
CLR(asx_rx_port, __BIT(sc->sc_port));
sys/arch/mips/cavium/dev/octeon_asx.c
85
SET(asx_tx_port, __BIT(sc->sc_port));
sys/arch/mips/cavium/dev/octeon_asx.c
87
CLR(asx_tx_port, __BIT(sc->sc_port));
sys/arch/mips/cavium/dev/octeon_asx.c
99
SET(asx_rx_port, __BIT(sc->sc_port));
sys/arch/mips/cavium/dev/octeon_cib.c
197
ih->ih_mask = __BIT(bit);
sys/arch/mips/cavium/dev/octeon_cib.c
243
KASSERT(ih->ih_mask == __BIT(n - 1));
sys/arch/mips/cavium/dev/octeon_faureg.h
44
#define POW_LOAD_TAGWAIT __BIT(13)
sys/arch/mips/cavium/dev/octeon_faureg.h
58
#define POW_STORE_NOADD __BIT(13)
sys/arch/mips/cavium/dev/octeon_gmx.c
438
CLR(ovr_bp, __SHIFTIN(__BIT(index), TX_OVR_BP_EN));
sys/arch/mips/cavium/dev/octeon_gmx.c
439
SET(ovr_bp, __SHIFTIN(__BIT(index), TX_OVR_BP_BP));
sys/arch/mips/cavium/dev/octeon_gmx.c
441
SET(ovr_bp, __SHIFTIN(__BIT(index), TX_OVR_BP_IGN_FULL));
sys/arch/mips/cavium/dev/octeon_gmx.c
443
SET(ovr_bp, __SHIFTIN(__BIT(index), TX_OVR_BP_EN));
sys/arch/mips/cavium/dev/octeon_gmx.c
444
CLR(ovr_bp, __SHIFTIN(__BIT(index), TX_OVR_BP_BP));
sys/arch/mips/cavium/dev/octeon_gmx.c
446
SET(ovr_bp, __SHIFTIN(__BIT(index), TX_OVR_BP_IGN_FULL));
sys/arch/mips/cavium/dev/octeon_gmx.c
631
SET(cam_en, __BIT(multi));
sys/arch/mips/cavium/dev/octeon_ipd.c
211
CLR(sub_port_fcs, __BIT(sc->sc_port));
sys/arch/mips/cavium/dev/octeon_ipd.c
213
SET(sub_port_fcs, __BIT(sc->sc_port));
sys/arch/mips/cavium/octeon_cpunode.c
314
if (!(cpus_booted & __BIT(cpunum))) {
sys/arch/mips/cavium/octeon_cpunode.c
88
volatile uint64_t cpus_booted = __BIT(0); /* cpu0 is always booted */
sys/arch/mips/cavium/octeon_intr.c
280
cpu->cpu_ip4_enable[0] |= __BIT(CIU_INT_MBOX_15_0);
sys/arch/mips/cavium/octeon_intr.c
281
cpu->cpu_ip3_enable[0] |= __BIT(CIU_INT_MBOX_31_16);
sys/arch/mips/cavium/octeon_intr.c
371
const uint64_t irq_mask = __BIT(irq % 64);
sys/arch/mips/cavium/octeon_intr.c
434
const uint64_t irq_mask = ~__BIT(irq % 64);
sys/arch/mips/cavium/octeon_intr.c
510
hwpend[bank] &= ~__BIT(bit);
sys/arch/mips/cavium/octeon_intr.c
555
KASSERT(__SHIFTOUT(ipi_mask, mbox_mask) < __BIT(NIPIS));
sys/arch/mips/cavium/octeon_intr.c
559
if (ipi_mask & __BIT(IPI_WDOG)) {
sys/arch/mips/cavium/octeon_intr.c
561
atomic_and_64(&ci->ci_request_ipis, ~__BIT(IPI_WDOG));
sys/arch/mips/cavium/octeon_intr.c
562
ipi_mask &= ~__BIT(IPI_WDOG);
sys/arch/mips/cavium/octeon_intr.c
603
const uint32_t ipi_mask = __BIT(req + ipi_shift);
sys/arch/mips/cavium/octeonreg.h
68
#define OCTEON_ADDR_IO __BIT(48)
sys/arch/mips/cavium/octeonreg.h
93
#define MIO_FUS_PDF_IS_71XX __BIT(32)
sys/arch/mips/include/cpu.h
153
#define CPUF_PRIMARY __BIT(0) /* CPU is primary CPU */
sys/arch/mips/include/cpu.h
154
#define CPUF_PRESENT __BIT(1) /* CPU is present */
sys/arch/mips/include/cpu.h
155
#define CPUF_RUNNING __BIT(2) /* CPU is running */
sys/arch/mips/include/cpu.h
156
#define CPUF_PAUSED __BIT(3) /* CPU is paused */
sys/arch/mips/include/cpu.h
157
#define CPUF_USERPMAP __BIT(5) /* CPU has a user pmap activated */
sys/arch/mips/include/cpu.h
73
#define CPUWATCH_WRITE __BIT(0)
sys/arch/mips/include/cpu.h
74
#define CPUWATCH_READ __BIT(1)
sys/arch/mips/include/cpu.h
75
#define CPUWATCH_EXEC __BIT(2)
sys/arch/mips/include/cpu.h
76
#define CPUWATCH_MASK __BIT(3)
sys/arch/mips/include/cpu.h
77
#define CPUWATCH_ASID __BIT(4)
sys/arch/mips/include/cpuregs.h
719
#define MIPS_FCSR_FLAGS_I __BIT(2) /* inexact */
sys/arch/mips/include/cpuregs.h
720
#define MIPS_FCSR_FLAGS_U __BIT(3) /* underflow */
sys/arch/mips/include/cpuregs.h
721
#define MIPS_FCSR_FLAGS_O __BIT(4) /* overflow */
sys/arch/mips/include/cpuregs.h
722
#define MIPS_FCSR_FLAGS_Z __BIT(5) /* divide by zero */
sys/arch/mips/include/cpuregs.h
723
#define MIPS_FCSR_FLAGS_V __BIT(6) /* invalid operation */
sys/arch/mips/include/cpuregs.h
725
#define MIPS_FCSR_ENABLES_I __BIT(7) /* inexact */
sys/arch/mips/include/cpuregs.h
726
#define MIPS_FCSR_ENABLES_U __BIT(8) /* underflow */
sys/arch/mips/include/cpuregs.h
727
#define MIPS_FCSR_ENABLES_O __BIT(9) /* overflow */
sys/arch/mips/include/cpuregs.h
728
#define MIPS_FCSR_ENABLES_Z __BIT(10) /* divide by zero */
sys/arch/mips/include/cpuregs.h
729
#define MIPS_FCSR_ENABLES_V __BIT(11) /* invalid operation */
sys/arch/mips/include/cpuregs.h
731
#define MIPS_FCSR_CAUSE_I __BIT(12) /* inexact */
sys/arch/mips/include/cpuregs.h
732
#define MIPS_FCSR_CAUSE_U __BIT(13) /* underflow */
sys/arch/mips/include/cpuregs.h
733
#define MIPS_FCSR_CAUSE_O __BIT(14) /* overflow */
sys/arch/mips/include/cpuregs.h
734
#define MIPS_FCSR_CAUSE_Z __BIT(15) /* divide by zero */
sys/arch/mips/include/cpuregs.h
735
#define MIPS_FCSR_CAUSE_V __BIT(16) /* invalid operation */
sys/arch/mips/include/cpuregs.h
736
#define MIPS_FCSR_CAUSE_E __BIT(17) /* unimplemented operation */
sys/arch/mips/include/cpuregs.h
737
#define MIPS_FCSR_NAN_2008 __BIT(18)
sys/arch/mips/include/cpuregs.h
738
#define MIPS_FCSR_ABS_2008 __BIT(19)
sys/arch/mips/include/cpuregs.h
739
#define MIPS_FCSR_FCC0 __BIT(23)
sys/arch/mips/include/cpuregs.h
741
#define MIPS_FCSR_FS __BIT(24) /* r4k+ */
sys/arch/mips/include/cpuregs.h
863
#define MIPS_WATCHLO_INSN __BIT(2)
sys/arch/mips/include/cpuregs.h
864
#define MIPS_WATCHLO_DATA_READ __BIT(1)
sys/arch/mips/include/cpuregs.h
865
#define MIPS_WATCHLO_DATA_WRITE __BIT(0)
sys/arch/mips/include/cpuregs.h
867
#define MIPS_WATCHHI_M __BIT(31) /* next watch reg implemented */
sys/arch/mips/include/cpuregs.h
868
#define MIPS_WATCHHI_G __BIT(30) /* use WatchLo vaddr */
sys/arch/mips/include/cpuregs.h
890
#define MIPS_HWRENA_IMPL31 __BIT(MIPS_HWR_IMPL31)
sys/arch/mips/include/cpuregs.h
891
#define MIPS_HWRENA_IMPL30 __BIT(MIPS_HWR_IMPL30)
sys/arch/mips/include/cpuregs.h
892
#define MIPS_HWRENA_ULR __BIT(MIPS_HWR_ULR)
sys/arch/mips/include/cpuregs.h
893
#define MIPS_HWRENA_CCRES __BIT(MIPS_HWR_CCRES)
sys/arch/mips/include/cpuregs.h
894
#define MIPS_HWRENA_CC __BIT(MIPS_HWR_CC)
sys/arch/mips/include/cpuregs.h
895
#define MIPS_HWRENA_SYNCI_STEP __BIT(MIPS_HWR_SYNCI_STEP)
sys/arch/mips/include/cpuregs.h
896
#define MIPS_HWRENA_CPUNUM __BIT(MIPS_HWR_CPUNUM)
sys/arch/mips/include/locore.h
864
#define MIPS_CP0FL_USE __BIT(0) /* use these flags */
sys/arch/mips/include/locore.h
865
#define MIPS_CP0FL_ECC __BIT(1)
sys/arch/mips/include/locore.h
866
#define MIPS_CP0FL_CACHE_ERR __BIT(2)
sys/arch/mips/include/locore.h
867
#define MIPS_CP0FL_EIRR __BIT(3)
sys/arch/mips/include/locore.h
868
#define MIPS_CP0FL_EIMR __BIT(4)
sys/arch/mips/include/locore.h
869
#define MIPS_CP0FL_EBASE __BIT(5) /* XXX probeable - shouldn't be hard coded */
sys/arch/mips/include/locore.h
870
#define MIPS_CP0FL_CONFIG __BIT(6) /* XXX defined - doesn't need to be hard coded */
sys/arch/mips/include/locore.h
871
#define MIPS_CP0FL_CONFIG1 __BIT(7) /* XXX probeable - shouldn't be hard coded */
sys/arch/mips/include/locore.h
872
#define MIPS_CP0FL_CONFIG2 __BIT(8) /* XXX probeable - shouldn't be hard coded */
sys/arch/mips/include/locore.h
873
#define MIPS_CP0FL_CONFIG3 __BIT(9) /* XXX probeable - shouldn't be hard coded */
sys/arch/mips/include/locore.h
874
#define MIPS_CP0FL_CONFIG4 __BIT(10) /* XXX probeable - shouldn't be hard coded */
sys/arch/mips/include/locore.h
875
#define MIPS_CP0FL_CONFIG5 __BIT(11) /* XXX probeable - shouldn't be hard coded */
sys/arch/mips/include/locore.h
876
#define MIPS_CP0FL_CONFIG6 __BIT(12)
sys/arch/mips/include/locore.h
877
#define MIPS_CP0FL_CONFIG7 __BIT(13)
sys/arch/mips/include/mipsNN.h
306
#define MIPSNN_CFG4_M __BIT(31)
sys/arch/mips/include/mipsNN.h
312
#define MIPSNN_CFG4_AE __BIT(28)
sys/arch/mips/include/mipsNN.h
424
#define MIPSNN_CFG5_M __BIT(31)
sys/arch/mips/include/mipsNN.h
427
#define MIPSNN_CFG5_K __BIT(30)
sys/arch/mips/include/mipsNN.h
430
#define MIPSNN_CFG5_CV __BIT(29)
sys/arch/mips/include/mipsNN.h
433
#define MIPSNN_CFG5_EVA __BIT(28)
sys/arch/mips/include/mipsNN.h
436
#define MIPSNN_CFG5_MSAEn __BIT(27)
sys/arch/mips/include/mipsNN.h
439
#define MIPSNN_CFG5_XNP __BIT(13)
sys/arch/mips/include/mipsNN.h
442
#define MIPSNN_CFG5_DEC __BIT(11)
sys/arch/mips/include/mipsNN.h
445
#define MIPSNN_CFG5_L2C __BIT(10)
sys/arch/mips/include/mipsNN.h
448
#define MIPSNN_CFG5_UFE __BIT(9)
sys/arch/mips/include/mipsNN.h
451
#define MIPSNN_CFG5_FRE __BIT(8)
sys/arch/mips/include/mipsNN.h
454
#define MIPSNN_CFG5_VP __BIT(7)
sys/arch/mips/include/mipsNN.h
457
#define MIPSNN_CFG5_SBRI __BIT(6)
sys/arch/mips/include/mipsNN.h
460
#define MIPSNN_CFG5_MVH __BIT(5)
sys/arch/mips/include/mipsNN.h
463
#define MIPSNN_CFG5_LLB __BIT(4)
sys/arch/mips/include/mipsNN.h
466
#define MIPSNN_CFG5_MRP __BIT(3)
sys/arch/mips/include/mipsNN.h
469
#define MIPSNN_CFG5_UFR __BIT(2)
sys/arch/mips/include/mipsNN.h
472
#define MIPSNN_CFG5_NF_EXISTS __BIT(0)
sys/arch/mips/include/mipsNN.h
480
#define MIPSNN_PERFCTL_M __BIT(31)
sys/arch/mips/include/mipsNN.h
483
#define MIPSNN_PERFCTL_W __BIT(30)
sys/arch/mips/include/mipsNN.h
492
#define MIPSNN_PERFCTL_PCTD __BIT(15)
sys/arch/mips/include/mipsNN.h
502
#define MIPSNN_PERFCTL_IE __BIT(4)
sys/arch/mips/include/mipsNN.h
505
#define MIPSNN_PERFCTL_U __BIT(3)
sys/arch/mips/include/mipsNN.h
508
#define MIPSNN_PERFCTL_S __BIT(2)
sys/arch/mips/include/mipsNN.h
511
#define MIPSNN_PERFCTL_K __BIT(1)
sys/arch/mips/include/mipsNN.h
514
#define MIPSNN_PERFCTL_EXL __BIT(0)
sys/arch/mips/include/mipsNN.h
551
#define MIPSNN_RMIXLP_CFG7_LG_MASK __BIT(61)
sys/arch/mips/include/mipsNN.h
587
#define MIPSNN_MTI_CFG6_SPCD __BIT(14)
sys/arch/mips/include/mipsNN.h
590
#define MIPSNN_MTI_CFG6_SYND __BIT(13)
sys/arch/mips/include/mipsNN.h
593
#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_MASK __BIT(12:10)
sys/arch/mips/include/mipsNN.h
604
#define MIPSNN_MTI_CFG6_NMRUP __BIT(9) /* 1: implemented */
sys/arch/mips/include/mipsNN.h
607
#define MIPSNN_MTI_CFG6_NMRUD __BIT(8) /* 1: TLBWR is random */
sys/arch/mips/include/mipsNN.h
610
#define MIPSNN_MTI_CFG6_JRCP __BIT(1) /* 1: implemented */
sys/arch/mips/include/mipsNN.h
613
#define MIPSNN_MTI_CFG6_JRCD __BIT(0) /* 1: disabled */
sys/arch/mips/include/mipsNN.h
622
#define MIPSNN_MTI_CFG7_WII __BIT(31)
sys/arch/mips/include/mipsNN.h
625
#define MIPSNN_MTI_CFG7_FPFS __BIT(30)
sys/arch/mips/include/mipsNN.h
628
#define MIPSNN_MTI_CFG7_IHB __BIT(29)
sys/arch/mips/include/mipsNN.h
631
#define MIPSNN_MTI_CFG7_FPR1 __BIT(28) /* 1: 3:2 */
sys/arch/mips/include/mipsNN.h
634
#define MIPSNN_MTI_CFG7_SEHB __BIT(27)
sys/arch/mips/include/mipsNN.h
637
#define MIPSNN_MTI_CFG7_CP2IO __BIT(26)
sys/arch/mips/include/mipsNN.h
640
#define MIPSNN_MTI_CFG7_IAGN __BIT(25)
sys/arch/mips/include/mipsNN.h
643
#define MIPSNN_MTI_CFG7_IAGN __BIT(25)
sys/arch/mips/include/mipsNN.h
646
#define MIPSNN_MTI_CFG7_IALU __BIT(24)
sys/arch/mips/include/mipsNN.h
649
#define MIPSNN_MTI_CFG7_DGHR __BIT(23) /* 1: disable */
sys/arch/mips/include/mipsNN.h
652
#define MIPSNN_MTI_CFG7_SG __BIT(22) /* 1: no superscalar */
sys/arch/mips/include/mipsNN.h
655
#define MIPSNN_MTI_CFG7_SUI __BIT(21)
sys/arch/mips/include/mipsNN.h
658
#define MIPSNN_MTI_CFG7_NCWB __BIT(20)
sys/arch/mips/include/mipsNN.h
661
#define MIPSNN_MTI_CFG7_PCT __BIT(19)
sys/arch/mips/include/mipsNN.h
664
#define MIPSNN_MTI_CFG7_HCI __BIT(18)
sys/arch/mips/include/mipsNN.h
667
#define MIPSNN_MTI_CFG7_FPR0 __BIT(17) /* 1: half speed */
sys/arch/mips/include/mipsNN.h
677
#define MIPSNN_MTI_CFG7_AR __BIT(16) /* 1: no virt aliases */
sys/arch/mips/include/mipsNN.h
688
#define MIPSNN_MTI_CFG7_IAR __BIT(10) /* 1: no virt aliases */
sys/arch/mips/include/mipsNN.h
691
#define MIPSNN_MTI_CFG7_IVA __BIT(9) /* 1: fix disable */
sys/arch/mips/include/mipsNN.h
694
#define MIPSNN_MTI_CFG7_ES __BIT(8)
sys/arch/mips/include/mipsNN.h
697
#define MIPSNN_MTI_CFG7_BTLM __BIT(7)
sys/arch/mips/include/mipsNN.h
700
#define MIPSNN_MTI_CFG7_CPOOO __BIT(6) /* 1: disable OOO */
sys/arch/mips/include/mipsNN.h
703
#define MIPSNN_MTI_CFG7_NBLSU __BIT(5) /* 1: stalls pipeline */
sys/arch/mips/include/mipsNN.h
706
#define MIPSNN_MTI_CFG7_UBL __BIT(4) /* 1: blocking loads */
sys/arch/mips/include/mipsNN.h
709
#define MIPSNN_MTI_CFG7_BP __BIT(3) /* 1: disabled */
sys/arch/mips/include/mipsNN.h
712
#define MIPSNN_MTI_CFG7_RPS __BIT(2) /* 1: disabled */
sys/arch/mips/include/mipsNN.h
715
#define MIPSNN_MTI_CFG7_BHT __BIT(1) /* 1: disabled */
sys/arch/mips/include/mipsNN.h
718
#define MIPSNN_MTI_CFG7_SL __BIT(0) /* 1: load misses block */
sys/arch/mips/ingenic/ingenic_coreregs.h
40
#define CC_SW_RST0 __BIT(0) /* reset core 0 */
sys/arch/mips/ingenic/ingenic_coreregs.h
41
#define CC_SW_RST1 __BIT(1) /* reset core 1 */
sys/arch/mips/ingenic/ingenic_coreregs.h
42
#define CC_RPC0 __BIT(8) /* dedicated reset entry core 0 */
sys/arch/mips/ingenic/ingenic_coreregs.h
43
#define CC_RPC1 __BIT(9) /* -- || -- core 1 */
sys/arch/mips/ingenic/ingenic_coreregs.h
44
#define CC_SLEEP0M __BIT(16) /* mask sleep core 0 */
sys/arch/mips/ingenic/ingenic_coreregs.h
45
#define CC_SLEEP1M __BIT(17) /* mask sleep core 1 */
sys/arch/mips/ingenic/ingenic_coreregs.h
49
#define CS_MIRQ0_P __BIT(0) /* mailbox IRQ for 0 pending */
sys/arch/mips/ingenic/ingenic_coreregs.h
50
#define CS_MIRQ1_P __BIT(1) /* || core 1 */
sys/arch/mips/ingenic/ingenic_coreregs.h
51
#define CS_IRQ0_P __BIT(8) /* peripheral IRQ for core 0 */
sys/arch/mips/ingenic/ingenic_coreregs.h
52
#define CS_IRQ1_P __BIT(9) /* || core 1 */
sys/arch/mips/ingenic/ingenic_coreregs.h
53
#define CS_SLEEP0 __BIT(16) /* core 0 sleeping */
sys/arch/mips/ingenic/ingenic_coreregs.h
54
#define CS_SLEEP1 __BIT(17) /* core 1 sleeping */
sys/arch/mips/ingenic/ingenic_coreregs.h
58
#define REIM_MIRQ0_M __BIT(0) /* allow mailbox IRQ for core 0 */
sys/arch/mips/ingenic/ingenic_coreregs.h
59
#define REIM_MIRQ1_M __BIT(1) /* allow mailbox IRQ for core 1 */
sys/arch/mips/ingenic/ingenic_coreregs.h
60
#define REIM_IRQ0_M __BIT(8) /* allow peripheral IRQ for core 0 */
sys/arch/mips/ingenic/ingenic_coreregs.h
61
#define REIM_IRQ1_M __BIT(9) /* allow peripheral IRQ for core 1 */
sys/arch/mips/mips/cpu_subr.c
1080
if ((watchhi & __BIT(31)) == 0) /* test 'M' bit */
sys/arch/mips/mips/cpu_subr.c
1165
watchlo |= __BIT(0);
sys/arch/mips/mips/cpu_subr.c
1167
watchlo |= __BIT(1);
sys/arch/mips/mips/cpu_subr.c
1169
watchlo |= __BIT(2);
sys/arch/mips/mips/cpu_subr.c
1174
watchhi = __BIT(30); /* addr not qual. by asid (Global) */
sys/arch/mips/mips/db_disasm.c
350
(insn & __BIT(10)) ? ".hb" : "");
sys/arch/mips/mips/db_interface.c
866
mips3_sd(MIPS_PHYS_TO_XKPHYS_UNCACHED(CIU_NMI), __BIT(ci->ci_cpuid));
sys/arch/mips/mips/ipifuncs.c
123
if (ipi_mask & __BIT(IPI_NOP)) {
sys/arch/mips/mips/ipifuncs.c
127
if (ipi_mask & __BIT(IPI_AST)) {
sys/arch/mips/mips/ipifuncs.c
131
if (ipi_mask & __BIT(IPI_SHOOTDOWN)) {
sys/arch/mips/mips/ipifuncs.c
135
if (ipi_mask & __BIT(IPI_SYNCICACHE)) {
sys/arch/mips/mips/ipifuncs.c
139
if (ipi_mask & __BIT(IPI_SUSPEND)) {
sys/arch/mips/mips/ipifuncs.c
143
if (ipi_mask & __BIT(IPI_HALT)) {
sys/arch/mips/mips/ipifuncs.c
147
if (ipi_mask & __BIT(IPI_XCALL)) {
sys/arch/mips/mips/ipifuncs.c
151
if (ipi_mask & __BIT(IPI_GENERIC)) {
sys/arch/mips/mips/ipifuncs.c
156
if (ipi_mask & __BIT(IPI_KPREEMPT)) {
sys/arch/mips/mips/mips_fixup.c
300
uint32_t used = 1 | __BIT(_R_A0) | __BIT(_R_A1) | __BIT(_R_A2) | __BIT(_R_A3);
sys/arch/mips/mips/mips_fixup.c
56
|| (ebase & __BITS(31,30)) != __BIT(31)) {
sys/arch/mips/ralink/ralink_reg.h
1030
#define ISR_WDOG1_EXPIRED __BIT(29)
sys/arch/mips/ralink/ralink_reg.h
1031
#define ISR_WDOG0_EXPIRED __BIT(28)
sys/arch/mips/ralink/ralink_reg.h
1032
#define ISR_HAS_INTRUDER __BIT(27)
sys/arch/mips/ralink/ralink_reg.h
1033
#define ISR_PORT_STS_CHNG __BIT(26)
sys/arch/mips/ralink/ralink_reg.h
1034
#define ISR_BRDCAST_STORM __BIT(25)
sys/arch/mips/ralink/ralink_reg.h
1035
#define ISR_MUST_DROP_LAN __BIT(24)
sys/arch/mips/ralink/ralink_reg.h
1036
#define ISR_GLOB_QUE_FULL __BIT(23)
sys/arch/mips/ralink/ralink_reg.h
1037
#define ISR_LAN_QUE6_FULL __BIT(20)
sys/arch/mips/ralink/ralink_reg.h
1038
#define ISR_LAN_QUE5_FULL __BIT(19)
sys/arch/mips/ralink/ralink_reg.h
1039
#define ISR_LAN_QUE4_FULL __BIT(18)
sys/arch/mips/ralink/ralink_reg.h
1040
#define ISR_LAN_QUE3_FULL __BIT(17)
sys/arch/mips/ralink/ralink_reg.h
1041
#define ISR_LAN_QUE2_FULL __BIT(16)
sys/arch/mips/ralink/ralink_reg.h
1042
#define ISR_LAN_QUE1_FULL __BIT(15)
sys/arch/mips/ralink/ralink_reg.h
1043
#define ISR_LAN_QUE0_FULL __BIT(14)
sys/arch/mips/ralink/ralink_reg.h
1050
#define PCTL0_RD_CMD __BIT(14)
sys/arch/mips/ralink/ralink_reg.h
1051
#define PCTL0_WR_CMD __BIT(13)
sys/arch/mips/ralink/ralink_reg.h
1055
#define PCTL1_RD_DONE __BIT(1) /* read clear */
sys/arch/mips/ralink/ralink_reg.h
1056
#define PCTL1_WR_DONE __BIT(0) /* read clear */
sys/arch/mips/ralink/ralink_reg.h
1057
#define SGC2_WL_FC_EN __BIT(30)
sys/arch/mips/ralink/ralink_reg.h
1058
#define SGC2_PORT5_IS_LAN __BIT(29)
sys/arch/mips/ralink/ralink_reg.h
1059
#define SGC2_PORT4_IS_LAN __BIT(28)
sys/arch/mips/ralink/ralink_reg.h
1060
#define SGC2_PORT3_IS_LAN __BIT(27)
sys/arch/mips/ralink/ralink_reg.h
1061
#define SGC2_PORT2_IS_LAN __BIT(26)
sys/arch/mips/ralink/ralink_reg.h
1062
#define SGC2_PORT1_IS_LAN __BIT(25)
sys/arch/mips/ralink/ralink_reg.h
1063
#define SGC2_PORT0_IS_LAN __BIT(24)
sys/arch/mips/ralink/ralink_reg.h
1065
#define SGC2_ARBITER_LAN_EN __BIT(11)
sys/arch/mips/ralink/ralink_reg.h
1066
#define SGC2_CPU_TPID_EN __BIT(10)
sys/arch/mips/ralink/ralink_reg.h
1067
#define SGC2_DBL_TAG_EN5 __BIT(5)
sys/arch/mips/ralink/ralink_reg.h
1068
#define SGC2_DBL_TAG_EN4 __BIT(4)
sys/arch/mips/ralink/ralink_reg.h
1069
#define SGC2_DBL_TAG_EN3 __BIT(3)
sys/arch/mips/ralink/ralink_reg.h
1070
#define SGC2_DBL_TAG_EN2 __BIT(2)
sys/arch/mips/ralink/ralink_reg.h
1071
#define SGC2_DBL_TAG_EN1 __BIT(1)
sys/arch/mips/ralink/ralink_reg.h
1072
#define SGC2_DBL_TAG_EN0 __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
1086
#define PFC1_P6_Q1_EN __BIT(31)
sys/arch/mips/ralink/ralink_reg.h
1087
#define PFC1_P6_TOS_EN __BIT(30)
sys/arch/mips/ralink/ralink_reg.h
1088
#define PFC1_P5_TOS_EN __BIT(29)
sys/arch/mips/ralink/ralink_reg.h
1089
#define PFC1_P4_TOS_EN __BIT(28)
sys/arch/mips/ralink/ralink_reg.h
1090
#define PFC1_P3_TOS_EN __BIT(27)
sys/arch/mips/ralink/ralink_reg.h
1092
#define PFC1_P1_TOS_EN __BIT(25)
sys/arch/mips/ralink/ralink_reg.h
1093
#define PFC1_P0_TOS_EN __BIT(24)
sys/arch/mips/ralink/ralink_reg.h
1168
#define OTG_OTG_CNTRL_B_SESS_VALID __BIT(19)
sys/arch/mips/ralink/ralink_reg.h
1169
#define OTG_OTG_CNTRL_A_SESS_VALID __BIT(18)
sys/arch/mips/ralink/ralink_reg.h
1170
#define OTG_OTG_CNTRL_DEBOUNCE_SHORT __BIT(17)
sys/arch/mips/ralink/ralink_reg.h
1171
#define OTG_OTG_CNTRL_CONNID_STATUS __BIT(16)
sys/arch/mips/ralink/ralink_reg.h
1172
#define OTG_OTG_CNTRL_DV_HNP_EN __BIT(11)
sys/arch/mips/ralink/ralink_reg.h
1173
#define OTG_OTG_CNTRL_HC_SET_HNP_EN __BIT(10)
sys/arch/mips/ralink/ralink_reg.h
1174
#define OTG_OTG_CNTRL_HNP_REQ __BIT(9)
sys/arch/mips/ralink/ralink_reg.h
1175
#define OTG_OTG_CNTRL_HNP_SUCCESS __BIT(8)
sys/arch/mips/ralink/ralink_reg.h
1176
#define OTG_OTG_CNTRL_SESS_REQ __BIT(1)
sys/arch/mips/ralink/ralink_reg.h
1177
#define OTG_OTG_CNTRL_SESS_REQ_SUCCESS __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
1178
#define OTG_OTG_INT_DEBOUNCE_DONE __BIT(19)
sys/arch/mips/ralink/ralink_reg.h
1179
#define OTG_OTG_INT_ADEV_TIMEOUT __BIT(18)
sys/arch/mips/ralink/ralink_reg.h
1180
#define OTG_OTG_INT_HOST_NEG_DETECT __BIT(17)
sys/arch/mips/ralink/ralink_reg.h
1181
#define OTG_OTG_INT_HOST_NEG_STATUS __BIT(9)
sys/arch/mips/ralink/ralink_reg.h
1182
#define OTG_OTG_INT_SESSION_REQ_STATUS __BIT(8)
sys/arch/mips/ralink/ralink_reg.h
1183
#define OTG_OTG_INT_SESSION_END_STATUS __BIT(2)
sys/arch/mips/ralink/ralink_reg.h
1184
#define OTG_AHB_CFG_TX_PFIFO_EMPTY_INT_EN __BIT(8)
sys/arch/mips/ralink/ralink_reg.h
1185
#define OTG_AHB_CFG_TX_NPFIFO_EMPTY_INT_EN __BIT(7)
sys/arch/mips/ralink/ralink_reg.h
1186
#define OTG_AHB_CFG_DMA_EN __BIT(5)
sys/arch/mips/ralink/ralink_reg.h
1193
#define OTG_AHB_CFG_GLOBAL_INT_EN __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
1194
#define OTG_CFG_CORRUPT_TX __BIT(31)
sys/arch/mips/ralink/ralink_reg.h
1195
#define OTG_CFG_FORCE_DEVICE __BIT(30)
sys/arch/mips/ralink/ralink_reg.h
1196
#define OTG_CFG_FORCE_HOST __BIT(29)
sys/arch/mips/ralink/ralink_reg.h
1197
#define OTG_CFG_ULPI_EXT_VBUS_IND_SEL __BIT(22)
sys/arch/mips/ralink/ralink_reg.h
1198
#define OTG_CFG_ULPI_EXT_VBUS_IND __BIT(21)
sys/arch/mips/ralink/ralink_reg.h
1199
#define OTG_CFG_ULPI_EXT_VBUS_DRV __BIT(20)
sys/arch/mips/ralink/ralink_reg.h
1200
#define OTG_CFG_ULPI_CLOCK_SUSPEND __BIT(19)
sys/arch/mips/ralink/ralink_reg.h
1201
#define OTG_CFG_ULPI_AUTO_RESUME __BIT(18)
sys/arch/mips/ralink/ralink_reg.h
1202
#define OTG_CFG_ULPI_FS_LS_SEL __BIT(17)
sys/arch/mips/ralink/ralink_reg.h
1203
#define OTG_CFG_UTMI_I2C_SEL __BIT(16)
sys/arch/mips/ralink/ralink_reg.h
1205
#define OTG_CFG_HNP_CAP __BIT(9)
sys/arch/mips/ralink/ralink_reg.h
1206
#define OTG_CFG_SRP_CAP __BIT(8)
sys/arch/mips/ralink/ralink_reg.h
1207
#define OTG_CFG_ULPI_DDR_SEL __BIT(7)
sys/arch/mips/ralink/ralink_reg.h
1208
#define OTG_CFG_HS_PHY_SEL __BIT(6)
sys/arch/mips/ralink/ralink_reg.h
1209
#define OTG_CFG_FS_IF_SEL __BIT(5)
sys/arch/mips/ralink/ralink_reg.h
1210
#define OTG_CFG_ULPI_UTMI_SEL __BIT(4)
sys/arch/mips/ralink/ralink_reg.h
1211
#define OTG_CFG_PHY_IF __BIT(3)
sys/arch/mips/ralink/ralink_reg.h
1213
#define OTG_RST_AHB_IDLE __BIT(31)
sys/arch/mips/ralink/ralink_reg.h
1214
#define OTG_RST_DMA_ACTIVE __BIT(30)
sys/arch/mips/ralink/ralink_reg.h
1217
#define OTG_RST_TXQ_FLUSH __BIT(5)
sys/arch/mips/ralink/ralink_reg.h
1218
#define OTG_RST_RXQ_FLUSH __BIT(4)
sys/arch/mips/ralink/ralink_reg.h
1219
#define OTG_RST_INQ_FLUSH __BIT(3)
sys/arch/mips/ralink/ralink_reg.h
1220
#define OTG_RST_HC_FRAME __BIT(2)
sys/arch/mips/ralink/ralink_reg.h
1221
#define OTG_RST_AHB __BIT(1)
sys/arch/mips/ralink/ralink_reg.h
1222
#define OTG_RST_CORE __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
1223
#define OTG_INT_RESUME __BIT(31)
sys/arch/mips/ralink/ralink_reg.h
1224
#define OTG_INT_SESSION_REQ __BIT(30)
sys/arch/mips/ralink/ralink_reg.h
1225
#define OTG_INT_DISCONNECT __BIT(29)
sys/arch/mips/ralink/ralink_reg.h
1226
#define OTG_INT_CONNID_STATUS __BIT(28)
sys/arch/mips/ralink/ralink_reg.h
1227
#define OTG_INT_PTX_EMPTY __BIT(26)
sys/arch/mips/ralink/ralink_reg.h
1228
#define OTG_INT_HOST_CHANNEL __BIT(25)
sys/arch/mips/ralink/ralink_reg.h
1229
#define OTG_INT_PORT_STATUS __BIT(24)
sys/arch/mips/ralink/ralink_reg.h
1230
#define OTG_INT_DMA_FETCH_SUSPEND __BIT(22)
sys/arch/mips/ralink/ralink_reg.h
1231
#define OTG_INT_INCOMPLETE_PERIODIC __BIT(21)
sys/arch/mips/ralink/ralink_reg.h
1232
#define OTG_INT_INCOMPLETE_ISOC __BIT(20)
sys/arch/mips/ralink/ralink_reg.h
1233
#define OTG_INT_DV_OUT_EP __BIT(19)
sys/arch/mips/ralink/ralink_reg.h
1234
#define OTG_INT_DV_IN_EP __BIT(18)
sys/arch/mips/ralink/ralink_reg.h
1235
#define OTG_INT_DV_EP_MISMATCH __BIT(17)
sys/arch/mips/ralink/ralink_reg.h
1236
#define OTG_INT_DV_PERIODIC_END __BIT(15)
sys/arch/mips/ralink/ralink_reg.h
1237
#define OTG_INT_DV_ISOC_OUT_DROP __BIT(14)
sys/arch/mips/ralink/ralink_reg.h
1238
#define OTG_INT_DV_ENUM_COMPLETE __BIT(13)
sys/arch/mips/ralink/ralink_reg.h
1239
#define OTG_INT_DV_USB_RESET __BIT(12)
sys/arch/mips/ralink/ralink_reg.h
1240
#define OTG_INT_DV_USB_SUSPEND __BIT(11)
sys/arch/mips/ralink/ralink_reg.h
1241
#define OTG_INT_DV_USB_EARLY_SUSPEND __BIT(10)
sys/arch/mips/ralink/ralink_reg.h
1242
#define OTG_INT_I2C __BIT(9)
sys/arch/mips/ralink/ralink_reg.h
1243
#define OTG_INT_ULPI_CARKIT __BIT(8)
sys/arch/mips/ralink/ralink_reg.h
1244
#define OTG_INT_DV_OUT_NAK_EFFECTIVE __BIT(7)
sys/arch/mips/ralink/ralink_reg.h
1245
#define OTG_INT_DV_IN_NAK_EFFECTIVE __BIT(6)
sys/arch/mips/ralink/ralink_reg.h
1246
#define OTG_INT_NPTX_EMPTY __BIT(5)
sys/arch/mips/ralink/ralink_reg.h
1247
#define OTG_INT_RX_FIFO __BIT(4)
sys/arch/mips/ralink/ralink_reg.h
1248
#define OTG_INT_SOF __BIT(3)
sys/arch/mips/ralink/ralink_reg.h
1249
#define OTG_INT_OTG __BIT(2)
sys/arch/mips/ralink/ralink_reg.h
1250
#define OTG_INT_MODE_MISMATCH __BIT(1)
sys/arch/mips/ralink/ralink_reg.h
1251
#define OTG_INT_MODE __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
1253
#define OTG_HC_CFG_FORCE_NO_HS __BIT(2)
sys/arch/mips/ralink/ralink_reg.h
1273
#define USB_OTG_HC_PORT_POWER __BIT(12)
sys/arch/mips/ralink/ralink_reg.h
1277
#define USB_OTG_HC_PORT_RESET __BIT(8)
sys/arch/mips/ralink/ralink_reg.h
1278
#define USB_OTG_HC_PORT_SUSPEND __BIT(7)
sys/arch/mips/ralink/ralink_reg.h
1279
#define USB_OTG_HC_PORT_RESUME __BIT(6)
sys/arch/mips/ralink/ralink_reg.h
1280
#define USB_OTG_HC_PORT_OVCURR_CHANGE __BIT(5)
sys/arch/mips/ralink/ralink_reg.h
1281
#define USB_OTG_HC_PORT_OVCURR __BIT(4)
sys/arch/mips/ralink/ralink_reg.h
1282
#define USB_OTG_HC_PORT_ENABLE_CHANGE __BIT(3)
sys/arch/mips/ralink/ralink_reg.h
1283
#define USB_OTG_HC_PORT_ENABLE __BIT(2)
sys/arch/mips/ralink/ralink_reg.h
1284
#define USB_OTG_HC_PORT_CONNECT_CHANGE __BIT(1)
sys/arch/mips/ralink/ralink_reg.h
1285
#define USB_OTG_HC_PORT_STATUS __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
1286
#define USB_OTG_HC_CH_CFG_ENABLE __BIT(31)
sys/arch/mips/ralink/ralink_reg.h
1287
#define USB_OTG_HC_CH_CFG_DISABLE __BIT(30)
sys/arch/mips/ralink/ralink_reg.h
1288
#define USB_OTG_HC_CH_CFG_ODD_FRAME __BIT(29)
sys/arch/mips/ralink/ralink_reg.h
1296
#define USB_OTG_HC_CH_CFG_LS __BIT(17)
sys/arch/mips/ralink/ralink_reg.h
1302
#define USB_OTG_HC_CH_SPLT_EN __BIT(31)
sys/arch/mips/ralink/ralink_reg.h
1303
#define USB_OTG_HC_CH_SPLT_COMPLETE __BIT(16)
sys/arch/mips/ralink/ralink_reg.h
1312
#define USB_OTG_HC_CH_INT_TOGGLE_ERROR __BIT(10)
sys/arch/mips/ralink/ralink_reg.h
1313
#define USB_OTG_HC_CH_INT_FRAME_OVERRUN __BIT(9)
sys/arch/mips/ralink/ralink_reg.h
1314
#define USB_OTG_HC_CH_INT_BABBLE_ERROR __BIT(8)
sys/arch/mips/ralink/ralink_reg.h
1315
#define USB_OTG_HC_CH_INT_XACT_ERROR __BIT(7)
sys/arch/mips/ralink/ralink_reg.h
1316
#define USB_OTG_HC_CH_INT_NYET __BIT(6)
sys/arch/mips/ralink/ralink_reg.h
1317
#define USB_OTG_HC_CH_INT_ACK __BIT(5)
sys/arch/mips/ralink/ralink_reg.h
1318
#define USB_OTG_HC_CH_INT_NAK __BIT(4)
sys/arch/mips/ralink/ralink_reg.h
1319
#define USB_OTG_HC_CH_INT_STALL __BIT(3)
sys/arch/mips/ralink/ralink_reg.h
1320
#define USB_OTG_HC_CH_INT_DMA_ERROR __BIT(2)
sys/arch/mips/ralink/ralink_reg.h
1321
#define USB_OTG_HC_CH_INT_HALTED __BIT(1)
sys/arch/mips/ralink/ralink_reg.h
1322
#define USB_OTG_HC_CH_INT_XFER_COMPLETE __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
1323
#define USB_OTG_HC_CH_XFER_DO_PING __BIT(31)
sys/arch/mips/ralink/ralink_reg.h
1340
#define PCICFG_PSIRST __BIT(1)
sys/arch/mips/ralink/ralink_reg.h
1342
#define PCIINT_INT3 __BIT(21) /* PCIe1 interrupt */
sys/arch/mips/ralink/ralink_reg.h
1343
#define PCIINT_INT2 __BIT(20) /* PCIe0 interrupt */
sys/arch/mips/ralink/ralink_reg.h
1344
#define PCIINT_INT1 __BIT(19)
sys/arch/mips/ralink/ralink_reg.h
1345
#define PCIINT_INT0 __BIT(18)
sys/arch/mips/ralink/ralink_reg.h
1359
#define PHY0CFG_SPI_BUSY __BIT(31)
sys/arch/mips/ralink/ralink_reg.h
1360
#define PHY0CFG_SPI_WR __BIT(23)
sys/arch/mips/ralink/ralink_reg.h
1367
#define BARSETUP_BARENB __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
1375
#define PCIE_STATUS_LINK_UP __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
161
#define SYSCTL_CFG0_INIC_EE_SDRAM __BIT(29)
sys/arch/mips/ralink/ralink_reg.h
162
#define SYSCTL_CFG0_INIC_8MB_SDRAM __BIT(28)
sys/arch/mips/ralink/ralink_reg.h
164
#define SYSCTL_CFG0_BYPASS_PLL __BIT(21)
sys/arch/mips/ralink/ralink_reg.h
165
#define SYSCTL_CFG0_BE __BIT(20)
sys/arch/mips/ralink/ralink_reg.h
166
#define SYSCTL_CFG0_CPU_CLK_SEL __BIT(18)
sys/arch/mips/ralink/ralink_reg.h
170
#define SYSCTL_CFG0_SDRAM_CLK_DRV __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
172
#define SYSCTL_CFG0_BE __BIT(19)
sys/arch/mips/ralink/ralink_reg.h
184
#define SYSCTL_CFG0_DRAM_FROM_EE __BIT(8)
sys/arch/mips/ralink/ralink_reg.h
185
#define SYSCTL_CFG0_DBG_JTAG_MODE __BIT(7)
sys/arch/mips/ralink/ralink_reg.h
186
#define SYSCTL_CFG0_XTAL_FREQ_SEL __BIT(6)
sys/arch/mips/ralink/ralink_reg.h
192
#define SYSCTL_CFG0_DBG_JTAG_MODE __BIT(8)
sys/arch/mips/ralink/ralink_reg.h
193
#define SYSCTL_CFG0_TEST_MODE_1 __BIT(7)
sys/arch/mips/ralink/ralink_reg.h
194
#define SYSCTL_CFG0_XTAL_FREQ_SEL __BIT(6)
sys/arch/mips/ralink/ralink_reg.h
195
#define SYSCTL_CFG0_EXT_BG __BIT(5)
sys/arch/mips/ralink/ralink_reg.h
196
#define SYSCTL_CFG0_TEST_MODE_0 __BIT(4)
sys/arch/mips/ralink/ralink_reg.h
198
#define SYSCTL_CFG0_DRAM_TYPE __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
207
#define SYSCTL_CFG1_USB0_HOST_MODE __BIT(10)
sys/arch/mips/ralink/ralink_reg.h
208
#define SYSCTL_CFG1_PCIE_RC_MODE __BIT(8)
sys/arch/mips/ralink/ralink_reg.h
211
#define SYSCTL_CFG1_PCI_HOST_MODE __BIT(7)
sys/arch/mips/ralink/ralink_reg.h
212
#define SYSCTL_CFG1_PCI_66M_MODE __BIT(6)
sys/arch/mips/ralink/ralink_reg.h
221
#define SYSCTL_CLKCFG0_REFCLK0_IS_OUT __BIT(8)
sys/arch/mips/ralink/ralink_reg.h
228
#define SYSCTL_CLKCFG0_PERI_CLK_SEL __BIT(4)
sys/arch/mips/ralink/ralink_reg.h
231
#define SYSCTL_CLKCFG0_EPHY_USE_25M __BIT(3)
sys/arch/mips/ralink/ralink_reg.h
235
#define SYSCTL_CLKCFG1_PBUS_DIV2 __BIT(30)
sys/arch/mips/ralink/ralink_reg.h
236
#define SYSCTL_CLKCFG1_SYS_TCK_EN __BIT(29)
sys/arch/mips/ralink/ralink_reg.h
237
#define SYSCTL_CLKCFG1_FE_GDMA_PCLK_EN __BIT(22)
sys/arch/mips/ralink/ralink_reg.h
238
#define SYSCTL_CLKCFG1_PCIE_CLK_EN_3883 __BIT(21)
sys/arch/mips/ralink/ralink_reg.h
239
#define SYSCTL_CLKCFG1_UPHY1_CLK_EN __BIT(20)
sys/arch/mips/ralink/ralink_reg.h
240
#define SYSCTL_CLKCFG1_PCI_CLK_EN __BIT(19)
sys/arch/mips/ralink/ralink_reg.h
241
#define SYSCTL_CLKCFG1_UPHY0_CLK_EN_3883 __BIT(18)
sys/arch/mips/ralink/ralink_reg.h
242
#define SYSCTL_CLKCFG1_GE2_CLK_EN_3883 __BIT(17)
sys/arch/mips/ralink/ralink_reg.h
243
#define SYSCTL_CLKCFG1_GE1_CLK_EN_3883 __BIT(16)
sys/arch/mips/ralink/ralink_reg.h
246
#define SYSCTL_CLKCFG1_PWM_CLK_EN_7628 __BIT(31)
sys/arch/mips/ralink/ralink_reg.h
247
#define SYSCTL_CLKCFG1_AUX_SYS_TCK_EN_7628 __BIT(29)
sys/arch/mips/ralink/ralink_reg.h
248
#define SYSCTL_CLKCFG1_MIPSC_CLK_EN_7628 __BIT(28)
sys/arch/mips/ralink/ralink_reg.h
249
#define SYSCTL_CLKCFG1_UPHY0_CLK_EN_7628 __BIT(22)
sys/arch/mips/ralink/ralink_reg.h
250
#define SYSCTL_CLKCFG1_UART2_CLK_EN_7628 __BIT(20)
sys/arch/mips/ralink/ralink_reg.h
251
#define SYSCTL_CLKCFG1_UART1_CLK_EN_7628 __BIT(19)
sys/arch/mips/ralink/ralink_reg.h
252
#define SYSCTL_CLKCFG1_UART0_CLK_EN_7628 __BIT(12)
sys/arch/mips/ralink/ralink_reg.h
255
#define SYSCTL_CLKCFG1_AUX_SYS_TCK_EN __BIT(28)
sys/arch/mips/ralink/ralink_reg.h
256
#define SYSCTL_CLKCFG1_FE_CLK_EN __BIT(21)
sys/arch/mips/ralink/ralink_reg.h
257
#define SYSCTL_CLKCFG1_UARTL_CLK_EN __BIT(19)
sys/arch/mips/ralink/ralink_reg.h
258
#define SYSCTL_CLKCFG1_GE2_CLK_EN_7620 __BIT(7)
sys/arch/mips/ralink/ralink_reg.h
259
#define SYSCTL_CLKCFG1_GE1_CLK_EN_7620 __BIT(6)
sys/arch/mips/ralink/ralink_reg.h
260
#define SYSCTL_CLKCFG1_GE2_CLK_EN_7620 __BIT(7)
sys/arch/mips/ralink/ralink_reg.h
261
#define SYSCTL_CLKCFG1_GE1_CLK_EN_7620 __BIT(6)
sys/arch/mips/ralink/ralink_reg.h
264
#define SYSCTL_CLKCFG1_SDHC_CLK_EN __BIT(30)
sys/arch/mips/ralink/ralink_reg.h
265
#define SYSCTL_CLKCFG1_PCIE_CLK_EN_7620 __BIT(26)
sys/arch/mips/ralink/ralink_reg.h
266
#define SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620 __BIT(25)
sys/arch/mips/ralink/ralink_reg.h
267
#define SYSCTL_CLKCFG1_ESW_CLK_EN __BIT(23)
sys/arch/mips/ralink/ralink_reg.h
268
#define SYSCTL_CLKCFG1_SPI_CLK_EN __BIT(18)
sys/arch/mips/ralink/ralink_reg.h
269
#define SYSCTL_CLKCFG1_I2S_CLK_EN __BIT(17)
sys/arch/mips/ralink/ralink_reg.h
270
#define SYSCTL_CLKCFG1_I2C_CLK_EN __BIT(16)
sys/arch/mips/ralink/ralink_reg.h
271
#define SYSCTL_CLKCFG1_NAND_CLK_EN __BIT(15)
sys/arch/mips/ralink/ralink_reg.h
272
#define SYSCTL_CLKCFG1_GDMA_CLK_EN __BIT(14)
sys/arch/mips/ralink/ralink_reg.h
273
#define SYSCTL_CLKCFG1_GPIO_CLK_EN __BIT(13)
sys/arch/mips/ralink/ralink_reg.h
274
#define SYSCTL_CLKCFG1_UART_CLK_EN __BIT(12)
sys/arch/mips/ralink/ralink_reg.h
275
#define SYSCTL_CLKCFG1_PCM_CLK_EN __BIT(11)
sys/arch/mips/ralink/ralink_reg.h
276
#define SYSCTL_CLKCFG1_MC_CLK_EN __BIT(10)
sys/arch/mips/ralink/ralink_reg.h
277
#define SYSCTL_CLKCFG1_INTC_CLK_EN __BIT(9)
sys/arch/mips/ralink/ralink_reg.h
278
#define SYSCTL_CLKCFG1_TIMER_CLK_EN __BIT(8)
sys/arch/mips/ralink/ralink_reg.h
290
#define RST_PPE_7620 __BIT(31)
sys/arch/mips/ralink/ralink_reg.h
291
#define RST_PWM_7628 __BIT(31)
sys/arch/mips/ralink/ralink_reg.h
292
#define RST_SDHC_7620 __BIT(30)
sys/arch/mips/ralink/ralink_reg.h
293
#define RST_CRYPTO_7628 __BIT(29)
sys/arch/mips/ralink/ralink_reg.h
294
#define RST_MIPS_CNT_7620 __BIT(28)
sys/arch/mips/ralink/ralink_reg.h
295
#define RST_PCIPCIE_3883 __BIT(27)
sys/arch/mips/ralink/ralink_reg.h
296
#define RST_FLASH_3883 __BIT(26)
sys/arch/mips/ralink/ralink_reg.h
297
#define RST_PCIE0_7620 __BIT(26)
sys/arch/mips/ralink/ralink_reg.h
298
#define RST_UDEV_3883 __BIT(25)
sys/arch/mips/ralink/ralink_reg.h
299
#define RST_UHST0_7620 __BIT(25)
sys/arch/mips/ralink/ralink_reg.h
300
#define RST_PCI_3883 __BIT(24)
sys/arch/mips/ralink/ralink_reg.h
301
#define RST_EPHY_7620 __BIT(24)
sys/arch/mips/ralink/ralink_reg.h
302
#define RST_PCIE_3883 __BIT(23)
sys/arch/mips/ralink/ralink_reg.h
303
#define RST_ESW_7620 __BIT(23)
sys/arch/mips/ralink/ralink_reg.h
304
#define RST_UHST __BIT(22)
sys/arch/mips/ralink/ralink_reg.h
305
#define RST_FE __BIT(21)
sys/arch/mips/ralink/ralink_reg.h
306
#define RST_WLAN __BIT(20)
sys/arch/mips/ralink/ralink_reg.h
307
#define RST_UART2_7628 __BIT(20)
sys/arch/mips/ralink/ralink_reg.h
308
#define RST_UARTL __BIT(19)
sys/arch/mips/ralink/ralink_reg.h
309
#define RST_UART1_7628 __BIT(19)
sys/arch/mips/ralink/ralink_reg.h
310
#define RST_SPI __BIT(18)
sys/arch/mips/ralink/ralink_reg.h
311
#define RST_I2S __BIT(17)
sys/arch/mips/ralink/ralink_reg.h
312
#define RST_I2C __BIT(16)
sys/arch/mips/ralink/ralink_reg.h
313
#define RST_NAND __BIT(15)
sys/arch/mips/ralink/ralink_reg.h
314
#define RST_DMA __BIT(14)
sys/arch/mips/ralink/ralink_reg.h
315
#define RST_PIO __BIT(13)
sys/arch/mips/ralink/ralink_reg.h
316
#define RST_UART __BIT(12)
sys/arch/mips/ralink/ralink_reg.h
317
#define RST_UART0_7628 __BIT(12)
sys/arch/mips/ralink/ralink_reg.h
318
#define RST_PCM __BIT(11)
sys/arch/mips/ralink/ralink_reg.h
319
#define RST_MC __BIT(10)
sys/arch/mips/ralink/ralink_reg.h
320
#define RST_INTC __BIT(9)
sys/arch/mips/ralink/ralink_reg.h
321
#define RST_TIMER __BIT(8)
sys/arch/mips/ralink/ralink_reg.h
322
#define RST_GE2 __BIT(7)
sys/arch/mips/ralink/ralink_reg.h
323
#define RST_GE1 __BIT(6)
sys/arch/mips/ralink/ralink_reg.h
324
#define RST_HIF_7628 __BIT(5)
sys/arch/mips/ralink/ralink_reg.h
325
#define RST_WIFI_7628 __BIT(4)
sys/arch/mips/ralink/ralink_reg.h
326
#define RST_SPIS_7628 __BIT(3)
sys/arch/mips/ralink/ralink_reg.h
327
#define RST_SYS __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
336
#define GPIO1MODE_REFCLK __BIT(18)
sys/arch/mips/ralink/ralink_reg.h
337
#define GPIO1MODE_PERST __BIT(16)
sys/arch/mips/ralink/ralink_reg.h
338
#define GPIO1MODE_ESD __BIT(15)
sys/arch/mips/ralink/ralink_reg.h
339
#define GPIO1MODE_WDT __BIT(14)
sys/arch/mips/ralink/ralink_reg.h
340
#define GPIO1MODE_SPI __BIT(12)
sys/arch/mips/ralink/ralink_reg.h
360
#define GPIOMODE_RGMII __BIT(9)
sys/arch/mips/ralink/ralink_reg.h
361
#define GPIOMODE_SDRAM __BIT(8)
sys/arch/mips/ralink/ralink_reg.h
362
#define GPIOMODE_MDIO __BIT(7)
sys/arch/mips/ralink/ralink_reg.h
363
#define GPIOMODE_JTAG __BIT(6)
sys/arch/mips/ralink/ralink_reg.h
364
#define GPIOMODE_UARTL __BIT(5)
sys/arch/mips/ralink/ralink_reg.h
365
#define GPIOMODE_UARTF2 __BIT(4)
sys/arch/mips/ralink/ralink_reg.h
366
#define GPIOMODE_UARTF1 __BIT(3)
sys/arch/mips/ralink/ralink_reg.h
367
#define GPIOMODE_UARTF0 __BIT(2)
sys/arch/mips/ralink/ralink_reg.h
370
#define GPIOMODE_SPI __BIT(1)
sys/arch/mips/ralink/ralink_reg.h
371
#define GPIOMODE_I2C __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
385
#define TIMER_1_RESET __BIT(5)
sys/arch/mips/ralink/ralink_reg.h
386
#define TIMER_0_RESET __BIT(4)
sys/arch/mips/ralink/ralink_reg.h
387
#define TIMER_1_INT_STATUS __BIT(1)
sys/arch/mips/ralink/ralink_reg.h
388
#define TIMER_0_INT_STATUS __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
389
#define TIMER_TEST_EN __BIT(15)
sys/arch/mips/ralink/ralink_reg.h
390
#define TIMER_EN __BIT(7)
sys/arch/mips/ralink/ralink_reg.h
435
#define INT_GLOBAL_EN __BIT(INT_GLOBAL)
sys/arch/mips/ralink/ralink_reg.h
614
#define UART_IER_ELSI __BIT(2) /* RX Line Status Interrupt Enable */
sys/arch/mips/ralink/ralink_reg.h
615
#define UART_IER_ETBEI __BIT(1) /* TX Buffer Empty Interrupt Enable */
sys/arch/mips/ralink/ralink_reg.h
616
#define UART_IER_ERBFI __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
619
#define UART_IIR_FIFOES1 __BIT(7) /* FIFO Mode Enable Status */
sys/arch/mips/ralink/ralink_reg.h
620
#define UART_IIR_FIFOES0 __BIT(6) /* FIFO Mode Enable Status */
sys/arch/mips/ralink/ralink_reg.h
621
#define UART_IIR_IID3 __BIT(3) /* Interrupt Source Encoded */
sys/arch/mips/ralink/ralink_reg.h
622
#define UART_IIR_IID2 __BIT(2) /* Interrupt Source Encoded */
sys/arch/mips/ralink/ralink_reg.h
623
#define UART_IIR_IID1 __BIT(1) /* Interrupt Source Encoded */
sys/arch/mips/ralink/ralink_reg.h
624
#define UART_IIR_IP __BIT(0) /* Interrupt Pending (active low) */
sys/arch/mips/ralink/ralink_reg.h
626
#define UART_FCR_RXTRIG1 __BIT(7) /* RX Interrupt Trigger Level */
sys/arch/mips/ralink/ralink_reg.h
627
#define UART_FCR_RXTRIG0 __BIT(6) /* RX Interrupt Trigger Level */
sys/arch/mips/ralink/ralink_reg.h
628
#define UART_FCR_TXTRIG1 __BIT(5) /* TX Interrupt Trigger Level */
sys/arch/mips/ralink/ralink_reg.h
629
#define UART_FCR_TXTRIG0 __BIT(4) /* TX Interrupt Trigger Level */
sys/arch/mips/ralink/ralink_reg.h
630
#define UART_FCR_DMAMODE __BIT(3) /* Enable DMA transfers */
sys/arch/mips/ralink/ralink_reg.h
631
#define UART_FCR_TXRST __BIT(2) /* Reset Transmitter FIFO */
sys/arch/mips/ralink/ralink_reg.h
632
#define UART_FCR_RXRST __BIT(1) /* Reset Receiver FIFO */
sys/arch/mips/ralink/ralink_reg.h
633
#define UART_FCR_FIFOE __BIT(0) /* Transmit and Receive FIFO Enable */
sys/arch/mips/ralink/ralink_reg.h
635
#define UART_LCR_DLAB __BIT(7) /* Divisor Latch Access Bit */
sys/arch/mips/ralink/ralink_reg.h
636
#define UART_LCR_SB __BIT(6) /* Set Break */
sys/arch/mips/ralink/ralink_reg.h
637
#define UART_LCR_STKYP __BIT(5) /* Sticky Parity */
sys/arch/mips/ralink/ralink_reg.h
638
#define UART_LCR_EPS __BIT(4) /* Even Parity Select */
sys/arch/mips/ralink/ralink_reg.h
639
#define UART_LCR_PEN __BIT(3) /* Parity Enable */
sys/arch/mips/ralink/ralink_reg.h
640
#define UART_LCR_STB __BIT(2) /* Stop Bit */
sys/arch/mips/ralink/ralink_reg.h
641
#define UART_LCR_WLS1 __BIT(1) /* Word Length Select */
sys/arch/mips/ralink/ralink_reg.h
642
#define UART_LCR_WLS0 __BIT(0) /* Word Length Select */
sys/arch/mips/ralink/ralink_reg.h
644
#define UART_MCR_LOOP __BIT(4) /* Loop-back Mode Enable */
sys/arch/mips/ralink/ralink_reg.h
646
#define UART_MSR_DCD __BIT(7) /* Data Carrier Detect */
sys/arch/mips/ralink/ralink_reg.h
647
#define UART_MSR_RI __BIT(6) /* Ring Indicator */
sys/arch/mips/ralink/ralink_reg.h
648
#define UART_MSR_DSR __BIT(5) /* Data Set Ready */
sys/arch/mips/ralink/ralink_reg.h
649
#define UART_MSR_CTS __BIT(4) /* Clear To Send */
sys/arch/mips/ralink/ralink_reg.h
650
#define UART_MSR_DDCD __BIT(3) /* Delta Data Carrier Detect */
sys/arch/mips/ralink/ralink_reg.h
651
#define UART_MSR_TERI __BIT(2) /* Trailing Edge Ring Indicator */
sys/arch/mips/ralink/ralink_reg.h
652
#define UART_MSR_DDSR __BIT(1) /* Delta Data Set Ready */
sys/arch/mips/ralink/ralink_reg.h
653
#define UART_MSR_DCTS __BIT(0) /* Delta Clear To Send */
sys/arch/mips/ralink/ralink_reg.h
655
#define UART_LSR_FIFOE __BIT(7) /* FIFO Error Status */
sys/arch/mips/ralink/ralink_reg.h
656
#define UART_LSR_TEMT __BIT(6) /* Transmitter Empty */
sys/arch/mips/ralink/ralink_reg.h
657
#define UART_LSR_TDRQ __BIT(5) /* Transmit Data Request */
sys/arch/mips/ralink/ralink_reg.h
658
#define UART_LSR_BI __BIT(4) /* Break Interrupt */
sys/arch/mips/ralink/ralink_reg.h
659
#define UART_LSR_FE __BIT(3) /* Framing Error */
sys/arch/mips/ralink/ralink_reg.h
660
#define UART_LSR_PE __BIT(2) /* Parity Error */
sys/arch/mips/ralink/ralink_reg.h
661
#define UART_LSR_OE __BIT(1) /* Overrun Error */
sys/arch/mips/ralink/ralink_reg.h
662
#define UART_LSR_DR __BIT(0) /* Data Ready */
sys/arch/mips/ralink/ralink_reg.h
683
#define I2C_CONFIG_ADDRDIS __BIT(1)
sys/arch/mips/ralink/ralink_reg.h
684
#define I2C_CONFIG_DEVDIS __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
685
#define I2C_STATUS_STARTERR __BIT(4)
sys/arch/mips/ralink/ralink_reg.h
686
#define I2C_STATUS_ACKERR __BIT(3)
sys/arch/mips/ralink/ralink_reg.h
687
#define I2C_STATUS_DATARDY __BIT(2)
sys/arch/mips/ralink/ralink_reg.h
688
#define I2C_STATUS_SDOEMPTY __BIT(1)
sys/arch/mips/ralink/ralink_reg.h
689
#define I2C_STATUS_BUSY __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
699
#define SPI_STATUS_BUSY __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
700
#define SPI_CONFIG_MSBFIRST __BIT(8)
sys/arch/mips/ralink/ralink_reg.h
701
#define SPI_CONFIG_CLK __BIT(6)
sys/arch/mips/ralink/ralink_reg.h
702
#define SPI_CONFIG_RXCLKEDGE_FALL __BIT(5)
sys/arch/mips/ralink/ralink_reg.h
703
#define SPI_CONFIG_TXCLKEDGE_FALL __BIT(4)
sys/arch/mips/ralink/ralink_reg.h
704
#define SPI_CONFIG_TRISTATE __BIT(3)
sys/arch/mips/ralink/ralink_reg.h
714
#define SPI_CONTROL_TRISTATE __BIT(3)
sys/arch/mips/ralink/ralink_reg.h
715
#define SPI_CONTROL_STARTWR __BIT(2)
sys/arch/mips/ralink/ralink_reg.h
716
#define SPI_CONTROL_STARTRD __BIT(1)
sys/arch/mips/ralink/ralink_reg.h
718
#define SPI_CONTROL_ENABLE_HIGH __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
763
#define RA_FE_INT_RX_COHERENT __BIT(31)
sys/arch/mips/ralink/ralink_reg.h
764
#define RA_FE_INT_RX_DLY __BIT(30)
sys/arch/mips/ralink/ralink_reg.h
765
#define RA_FE_INT_TX_COHERENT __BIT(29)
sys/arch/mips/ralink/ralink_reg.h
766
#define RA_FE_INT_TX_DLY_INT __BIT(28)
sys/arch/mips/ralink/ralink_reg.h
767
#define RA_FE_INT_RX_DONE_INT1 __BIT(17)
sys/arch/mips/ralink/ralink_reg.h
768
#define RA_FE_INT_RX_DONE_INT0 __BIT(16)
sys/arch/mips/ralink/ralink_reg.h
769
#define RA_FE_INT_TX_DONE_INT3 __BIT(3)
sys/arch/mips/ralink/ralink_reg.h
770
#define RA_FE_INT_TX_DONE_INT2 __BIT(2)
sys/arch/mips/ralink/ralink_reg.h
771
#define RA_FE_INT_TX_DONE_INT1 __BIT(1)
sys/arch/mips/ralink/ralink_reg.h
772
#define RA_FE_INT_TX_DONE_INT0 __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
861
#define MDIO_ACCESS_TRG __BIT(31)
sys/arch/mips/ralink/ralink_reg.h
862
#define MDIO_ACCESS_WR __BIT(30)
sys/arch/mips/ralink/ralink_reg.h
866
#define MDIO_CFG_AUTO_POLL __BIT(29)
sys/arch/mips/ralink/ralink_reg.h
868
#define MDIO_CFG_BP_EN __BIT(16)
sys/arch/mips/ralink/ralink_reg.h
869
#define MDIO_CFG_FORCE_CFG __BIT(15)
sys/arch/mips/ralink/ralink_reg.h
874
#define MDIO_CFG_FULL_DUPLEX __BIT(12)
sys/arch/mips/ralink/ralink_reg.h
875
#define MDIO_CFG_FC_TX __BIT(11)
sys/arch/mips/ralink/ralink_reg.h
876
#define MDIO_CFG_FC_RX __BIT(10)
sys/arch/mips/ralink/ralink_reg.h
877
#define MDIO_CFG_LINK_DOWN __BIT(9)
sys/arch/mips/ralink/ralink_reg.h
878
#define MDIO_CFG_AUTO_DONE __BIT(8)
sys/arch/mips/ralink/ralink_reg.h
884
#define MDIO_CFG_TURBO_50MHZ __BIT(5)
sys/arch/mips/ralink/ralink_reg.h
885
#define MDIO_CFG_TURBO_EN __BIT(4)
sys/arch/mips/ralink/ralink_reg.h
897
#define FE_GLOBAL_RESET_PSE __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
898
#define FE_INT_PPE_COUNT_HIGH __BIT(31)
sys/arch/mips/ralink/ralink_reg.h
899
#define FE_INT_DMA_COUNT_HIGH __BIT(29)
sys/arch/mips/ralink/ralink_reg.h
900
#define FE_INT_PSE_P2_FC_ASSERT __BIT(26)
sys/arch/mips/ralink/ralink_reg.h
901
#define FE_INT_PSE_FC_DROP __BIT(24)
sys/arch/mips/ralink/ralink_reg.h
902
#define FE_INT_GDMA_DROP_OTHER __BIT(23)
sys/arch/mips/ralink/ralink_reg.h
903
#define FE_INT_PSE_P1_FC_ASSERT __BIT(22)
sys/arch/mips/ralink/ralink_reg.h
904
#define FE_INT_PSE_P0_FC_ASSERT __BIT(21)
sys/arch/mips/ralink/ralink_reg.h
905
#define FE_INT_PSE_FQ_EMPTY __BIT(20)
sys/arch/mips/ralink/ralink_reg.h
906
#define FE_INT_TX_COHERENT __BIT(17)
sys/arch/mips/ralink/ralink_reg.h
907
#define FE_INT_RX_COHERENT __BIT(16)
sys/arch/mips/ralink/ralink_reg.h
908
#define FE_INT_TX3 __BIT(11)
sys/arch/mips/ralink/ralink_reg.h
909
#define FE_INT_TX2 __BIT(10)
sys/arch/mips/ralink/ralink_reg.h
910
#define FE_INT_TX1 __BIT(9)
sys/arch/mips/ralink/ralink_reg.h
911
#define FE_INT_TX0 __BIT(8)
sys/arch/mips/ralink/ralink_reg.h
912
#define FE_INT_RX __BIT(2)
sys/arch/mips/ralink/ralink_reg.h
913
#define FE_INT_TX_DELAY __BIT(1)
sys/arch/mips/ralink/ralink_reg.h
914
#define FE_INT_RX_DELAY __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
916
#define FE_GDMA_FWD_CFG_DROP_256B __BIT(23)
sys/arch/mips/ralink/ralink_reg.h
917
#define FE_GDMA_FWD_CFG_IP4_CRC_EN __BIT(22)
sys/arch/mips/ralink/ralink_reg.h
918
#define FE_GDMA_FWD_CFG_TCP_CRC_EN __BIT(21)
sys/arch/mips/ralink/ralink_reg.h
919
#define FE_GDMA_FWD_CFG_UDP_CRC_EN __BIT(20)
sys/arch/mips/ralink/ralink_reg.h
920
#define FE_GDMA_FWD_CFG_JUMBO_EN __BIT(19)
sys/arch/mips/ralink/ralink_reg.h
921
#define FE_GDMA_FWD_CFG_DIS_TX_PAD __BIT(18)
sys/arch/mips/ralink/ralink_reg.h
922
#define FE_GDMA_FWD_CFG_DIS_TX_CRC __BIT(17)
sys/arch/mips/ralink/ralink_reg.h
923
#define FE_GDMA_FWD_CFG_STRIP_RX_CRC __BIT(16)
sys/arch/mips/ralink/ralink_reg.h
938
#define FE_CDMA_CSG_CFG_IP4_CRC_EN __BIT(2)
sys/arch/mips/ralink/ralink_reg.h
939
#define FE_CDMA_CSG_CFG_UDP_CRC_EN __BIT(1)
sys/arch/mips/ralink/ralink_reg.h
940
#define FE_CDMA_CSG_CFG_TCP_CRC_EN __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
941
#define FE_PDMA_GLOBAL_CFG_HDR_SEG_LEN __BIT(16)
sys/arch/mips/ralink/ralink_reg.h
942
#define FE_PDMA_GLOBAL_CFG_TX_WB_DDONE __BIT(6)
sys/arch/mips/ralink/ralink_reg.h
945
#define FE_PDMA_GLOBAL_CFG_BURST_SZ_8 __BIT(4)
sys/arch/mips/ralink/ralink_reg.h
947
#define FE_PDMA_GLOBAL_CFG_RX_DMA_BUSY __BIT(3)
sys/arch/mips/ralink/ralink_reg.h
948
#define FE_PDMA_GLOBAL_CFG_RX_DMA_EN __BIT(2)
sys/arch/mips/ralink/ralink_reg.h
949
#define FE_PDMA_GLOBAL_CFG_TX_DMA_BUSY __BIT(1)
sys/arch/mips/ralink/ralink_reg.h
950
#define FE_PDMA_GLOBAL_CFG_TX_DMA_EN __BIT(0)
sys/arch/mips/ralink/ralink_reg.h
951
#define PDMA_RST_RX0 __BIT(16)
sys/arch/mips/ralink/ralink_reg.h
952
#define PDMA_RST_TX3 __BIT(3)
sys/arch/mips/ralink/ralink_reg.h
953
#define PDMA_RST_TX2 __BIT(2)
sys/arch/mips/ralink/ralink_reg.h
954
#define PDMA_RST_TX1 __BIT(1)
sys/arch/mips/ralink/ralink_reg.h
955
#define PDMA_RST_TX0 __BIT(0)
sys/arch/mips/rmi/rmixl_cpu.c
110
r &= ~__BIT(7); /* DBE */
sys/arch/mips/rmi/rmixl_nand.c
278
if ((istatus & __BIT(8)) != 0)
sys/arch/mips/rmi/rmixl_obio.c
248
#define _ADDR_ERR_DEVSTAT_A1 (__BIT(8) | __BIT(1) | __BIT(0))
sys/arch/mips/rmi/rmixl_obio.c
251
#define _BITERR_INT_EN_RESV (__BITS(31,8) | __BIT(4))
sys/arch/mips/rmi/rmixl_pcie.c
116
{ RMIXL_PCIE_ECFG_UESR, (__BITS(20,12) | __BIT(4)) },
sys/arch/mips/rmi/rmixl_pcie.c
117
{ RMIXL_PCIE_ECFG_CESR, (__BITS(20,12) | __BIT(4)) },
sys/arch/mips/rmi/rmixl_pcie.c
98
(__BITS(18,17) | __BIT(31) | __BITS(5,4) | __BIT(0))
sys/arch/mips/rmi/rmixl_pcix.c
127
#define PCIX_INTR_CONTROL_MSI1_MASK __BIT(7)
sys/arch/mips/rmi/rmixl_pcix.c
128
#define PCIX_INTR_CONTROL_MSI0_MASK __BIT(6)
sys/arch/mips/rmi/rmixl_pcix.c
129
#define PCIX_INTR_CONTROL_INTD_MASK __BIT(5)
sys/arch/mips/rmi/rmixl_pcix.c
130
#define PCIX_INTR_CONTROL_INTC_MASK __BIT(4)
sys/arch/mips/rmi/rmixl_pcix.c
131
#define PCIX_INTR_CONTROL_INTB_MASK __BIT(3)
sys/arch/mips/rmi/rmixl_pcix.c
132
#define PCIX_INTR_CONTROL_INTA_MASK __BIT(2)
sys/arch/mips/rmi/rmixl_pcix.c
133
#define PCIX_INTR_CONTROL_TMSI __BIT(1) /* Trigger MSI Interrupt */
sys/arch/mips/rmi/rmixl_pcix.c
134
#define PCIX_INTR_CONTROL_DIA __BIT(0) /* Device Interrupt through INTA Pin */
sys/arch/mips/rmi/rmixl_pcix.c
144
#define PCIX_INTR_STATUS_MSI1 __BIT(5)
sys/arch/mips/rmi/rmixl_pcix.c
145
#define PCIX_INTR_STATUS_MSI0 __BIT(4)
sys/arch/mips/rmi/rmixl_pcix.c
146
#define PCIX_INTR_STATUS_INTD __BIT(3)
sys/arch/mips/rmi/rmixl_pcix.c
147
#define PCIX_INTR_STATUS_INTC __BIT(2)
sys/arch/mips/rmi/rmixl_pcix.c
148
#define PCIX_INTR_STATUS_INTB __BIT(1)
sys/arch/mips/rmi/rmixl_pcix.c
149
#define PCIX_INTR_STATUS_INTA __BIT(0)
sys/arch/mips/rmi/rmixl_pcix.c
155
#define PCIX_INTR_ERR_STATUS_SERR __BIT(4) /* System Error */
sys/arch/mips/rmi/rmixl_pcix.c
156
#define PCIX_INTR_ERR_STATUS_RESb __BIT(3)
sys/arch/mips/rmi/rmixl_pcix.c
157
#define PCIX_INTR_ERR_STATUS_TE __BIT(2) /* Target Error */
sys/arch/mips/rmi/rmixl_pcix.c
158
#define PCIX_INTR_ERR_STATUS_IE __BIT(1) /* Initiator Error */
sys/arch/mips/rmi/rmixl_pcix.c
159
#define PCIX_INTR_ERR_STATUS_RCE __BIT(0) /* Retry Count Expired */
sys/arch/mips/rmi/rmixl_pcix.c
166
#define PCIX_HOST_MODE_CTL_HDMSTAT __BIT(1) /* Host/Dev Mode status
sys/arch/mips/rmi/rmixl_pcix.c
171
#define PCIX_HOST_MODE_CTL_HOSTSWRST __BIT(0) /* Host soft reset
sys/arch/mips/rmi/rmixl_pcix.c
397
if ((mble & __BIT(40)) != 0)
sys/arch/mips/rmi/rmixl_usbi.c
133
(r & __BIT(18)) ? "OK" : "FAIL"); /* XXX USB_BIST */
sys/arch/mips/rmi/rmixlreg.h
100
#define RMIXL_MSG_STS0_SPF __BIT(1) /* Send Pending Fail */
sys/arch/mips/rmi/rmixlreg.h
1001
#define RMIXL_UG_CTRL2_PHY_RST __BIT(0) /* Resets the PHY
sys/arch/mips/rmi/rmixlreg.h
101
#define RMIXL_MSG_STS0_SMP __BIT(0) /* Send Message Pending */
sys/arch/mips/rmi/rmixlreg.h
1017
#define RMIXL_UG_CTRL3_RESb __BIT(7)
sys/arch/mips/rmi/rmixlreg.h
1019
#define RMIXL_UG_CTRL3_USB_FLUSH __BIT(0) /* Flush the USB interface */
sys/arch/mips/rmi/rmixlreg.h
1025
#define RMIXL_UB_PHY_STATUS_VBUS __BIT(0) /* USB VBUS status */
sys/arch/mips/rmi/rmixlreg.h
1031
#define RMIXL_UB_INTERRUPT_FORCE __BIT(5) /* USB force interrupt */
sys/arch/mips/rmi/rmixlreg.h
1032
#define RMIXL_UB_INTERRUPT_PHY __BIT(4) /* USB PHY interrupt */
sys/arch/mips/rmi/rmixlreg.h
1033
#define RMIXL_UB_INTERRUPT_DEV __BIT(3) /* USB Device Controller interrupt */
sys/arch/mips/rmi/rmixlreg.h
1034
#define RMIXL_UB_INTERRUPT_EHCI __BIT(2) /* USB EHCI interrupt */
sys/arch/mips/rmi/rmixlreg.h
1035
#define RMIXL_UB_INTERRUPT_OHCI_1 __BIT(1) /* USB OHCI #1 interrupt */
sys/arch/mips/rmi/rmixlreg.h
1036
#define RMIXL_UB_INTERRUPT_OHCI_0 __BIT(0) /* USB OHCI #0 interrupt */
sys/arch/mips/rmi/rmixlreg.h
109
#define RMIXL_MSG_STS1_RESV __BIT(31)
sys/arch/mips/rmi/rmixlreg.h
110
#define RMIXL_MSG_STS1_C __BIT(30) /* Credit Overrun Error */
sys/arch/mips/rmi/rmixlreg.h
115
#define RMIXL_MSG_STS1_T __BIT(15) /* Invalid Target Error */
sys/arch/mips/rmi/rmixlreg.h
116
#define RMIXL_MSG_STS1_F __BIT(14) /* Receive Queue "Write When Full" Error */
sys/arch/mips/rmi/rmixlreg.h
136
#define RMIXL_MSG_CFG0_WIE __BIT(1) /* Watermark Interrupt Enable */
sys/arch/mips/rmi/rmixlreg.h
137
#define RMIXL_MSG_CFG0_EIE __BIT(0) /* Receive Queue Not Empty Enable */
sys/arch/mips/rmi/rmixlreg.h
146
#define RMIXL_MSG_CFG1_T __BIT(2) /* Trace Mode Enable */
sys/arch/mips/rmi/rmixlreg.h
147
#define RMIXL_MSG_CFG1_C __BIT(1) /* Credit Over-run Interrupt Enable */
sys/arch/mips/rmi/rmixlreg.h
148
#define RMIXL_MSG_CFG1_M __BIT(0) /* Messaging Errors Interrupt Enable */
sys/arch/mips/rmi/rmixlreg.h
242
(RMIXL_IO_DEV_PCIX | __BIT(11)) /* PXI-X big endian */
sys/arch/mips/rmi/rmixlreg.h
366
#define RMIXL_FLASH_BAR_ENB __BIT(0) /* 1=Enable */
sys/arch/mips/rmi/rmixlreg.h
377
((((r) & RMIXL_DRAM_BAR_ADDR_MASK) + __BIT(4)) << (24 - 4))
sys/arch/mips/rmi/rmixlreg.h
379
#define RMIXL_DRAM_BAR_STATUS __BIT(0) /* 1='region enabled' */
sys/arch/mips/rmi/rmixlreg.h
401
#define RMIXL_DRAM_CFG_CHANNEL_MODE __BIT(12)
sys/arch/mips/rmi/rmixlreg.h
402
#define RMIXL_DRAM_CFG_RESb __BIT(11)
sys/arch/mips/rmi/rmixlreg.h
405
#define RMIXL_DRAM_CFG_BUS_MODE __BIT(4)
sys/arch/mips/rmi/rmixlreg.h
417
#define RMIXL_PCIX_CFG_BAR_ENB __BIT(0) /* 1=Enable */
sys/arch/mips/rmi/rmixlreg.h
418
#define RMIXL_PCIX_CFG_SIZE __BIT(25)
sys/arch/mips/rmi/rmixlreg.h
431
#define RMIXL_PCIX_MEM_BAR_ENB __BIT(0) /* 1=Enable */
sys/arch/mips/rmi/rmixlreg.h
445
#define RMIXL_PCIX_IO_BAR_ENB __BIT(0) /* 1=Enable */
sys/arch/mips/rmi/rmixlreg.h
457
#define RMIXL_PCIE_CFG_BAR_ENB __BIT(0) /* 1=Enable */
sys/arch/mips/rmi/rmixlreg.h
458
#define RMIXL_PCIE_CFG_SIZE __BIT(25)
sys/arch/mips/rmi/rmixlreg.h
471
#define RMIXL_PCIE_ECFG_BAR_ENB __BIT(0) /* 1=Enable */
sys/arch/mips/rmi/rmixlreg.h
472
#define RMIXL_PCIE_ECFG_SIZE __BIT(29)
sys/arch/mips/rmi/rmixlreg.h
485
#define RMIXL_PCIE_MEM_BAR_ENB __BIT(0) /* 1=Enable */
sys/arch/mips/rmi/rmixlreg.h
499
#define RMIXL_PCIE_IO_BAR_ENB __BIT(0) /* 1=Enable */
sys/arch/mips/rmi/rmixlreg.h
529
#define RMIXL_PIC_CONTROL_WATCHDOG_ENB __BIT(0)
sys/arch/mips/rmi/rmixlreg.h
543
#define RMIXL_PIC_IPIBASE_RESa __BIT(6) /* undocumented bit */
sys/arch/mips/rmi/rmixlreg.h
544
#define RMIXL_PIC_IPIBASE_BCAST __BIT(7)
sys/arch/mips/rmi/rmixlreg.h
545
#define RMIXL_PIC_IPIBASE_NMI __BIT(8)
sys/arch/mips/rmi/rmixlreg.h
572
#define RMIXL_PIC_IRTENTRYC1_GL __BIT(6) /* 0=Global; 1=Local */
sys/arch/mips/rmi/rmixlreg.h
573
#define RMIXL_PIC_IRTENTRYC1_NMI __BIT(7) /* 0=Maskable; 1=NMI */
sys/arch/mips/rmi/rmixlreg.h
575
#define RMIXL_PIC_IRTENTRYC1_P __BIT(29) /* 0=Rising/High; 1=Falling/Low */
sys/arch/mips/rmi/rmixlreg.h
576
#define RMIXL_PIC_IRTENTRYC1_TRG __BIT(30) /* 0=Edge; 1=Level */
sys/arch/mips/rmi/rmixlreg.h
577
#define RMIXL_PIC_IRTENTRYC1_VALID __BIT(31) /* 0=Invalid; 1=Valid IRT Entry */
sys/arch/mips/rmi/rmixlreg.h
602
#define RMIXL_GPIO_PGM_MASK (__BITS(13,0) | __BITS(22,20) | __BIT(24)) /* programmable pins */
sys/arch/mips/rmi/rmixlreg.h
611
#define RMIXL_GPIO_FLASH_RDY __BIT(17) /* Flash memory ready, input only */
sys/arch/mips/rmi/rmixlreg.h
612
#define RMIXL_GPIO_FLASH_ADV __BIT(18) /* Flash memory address valid, output only */
sys/arch/mips/rmi/rmixlreg.h
613
#define RMIXL_GPIO_FLASH_RESET_N __BIT(19) /* Flash memory reset, output only */
sys/arch/mips/rmi/rmixlreg.h
614
#define RMIXL_GPIO_THERMAL_INTRPT __BIT(23) /* Thermal interrupt, interrupt only */
sys/arch/mips/rmi/rmixlreg.h
657
#define RMIXL_GPIO_INT_STS_INT_HI_L __BIT(25) /* INT_HI_L (input) requested */
sys/arch/mips/rmi/rmixlreg.h
658
#define RMIXL_GPIO_INT_STS_INT_LO_L __BIT(26) /* INT_LO_L (input) requested */
sys/arch/mips/rmi/rmixlreg.h
673
#define RMIXL_GPIO_RESET_RESET __BIT(0)
sys/arch/mips/rmi/rmixlreg.h
705
#define RMIXL_GPIO_RESET_CFG_XAUI_PORT1_SEL __BIT(25) /* XAUI Port 1 Select:
sys/arch/mips/rmi/rmixlreg.h
709
#define RMIXL_GPIO_RESET_CFG_XAUI_PORT0_SEL __BIT(24) /* XAUI Port 0 Select:
sys/arch/mips/rmi/rmixlreg.h
713
#define RMIXL_GPIO_RESET_CFG_RESb __BIT(23)
sys/arch/mips/rmi/rmixlreg.h
714
#define RMIXL_GPIO_RESET_CFG_USB_DEV __BIT(22) /* USB Device:
sys/arch/mips/rmi/rmixlreg.h
719
#define RMIXL_GPIO_RESET_CFG_FLASH33_EN __BIT(19) /* Flash 33 MHZ Enable:
sys/arch/mips/rmi/rmixlreg.h
723
#define RMIXL_GPIO_RESET_CFG_BIST_DIAG_EN __BIT(18) /* BIST Diagnostics enable */
sys/arch/mips/rmi/rmixlreg.h
724
#define RMIXL_GPIO_RESET_CFG_BIST_RUN_EN __BIT(18) /* BIST Run enable */
sys/arch/mips/rmi/rmixlreg.h
725
#define RMIXL_GPIO_RESET_CFG_BOOT_NAND __BIT(16) /* Enable boot from NAND Flash */
sys/arch/mips/rmi/rmixlreg.h
726
#define RMIXL_GPIO_RESET_CFG_BOOT_PCMCIA __BIT(15) /* Enable boot from PCMCIA */
sys/arch/mips/rmi/rmixlreg.h
727
#define RMIXL_GPIO_RESET_CFG_FLASH_CFG __BIT(14) /* Flash 32-bit Data Configuration:
sys/arch/mips/rmi/rmixlreg.h
731
#define RMIXL_GPIO_RESET_CFG_PCMCIA_EN __BIT(13) /* PCMCIA Enable Status */
sys/arch/mips/rmi/rmixlreg.h
732
#define RMIXL_GPIO_RESET_CFG_PARITY_EN __BIT(12) /* Parity Enable Status */
sys/arch/mips/rmi/rmixlreg.h
733
#define RMIXL_GPIO_RESET_CFG_BIGEND __BIT(11) /* Big Endian Mode Enable Status */
sys/arch/mips/rmi/rmixlreg.h
741
#define RMIXL_GPIO_EXT_INT_HI_MASK __BIT(3) /* mask (input) INT_HI_L */
sys/arch/mips/rmi/rmixlreg.h
742
#define RMIXL_GPIO_EXT_INT_LO_MASK __BIT(2) /* mask (input) INT_HI_L */
sys/arch/mips/rmi/rmixlreg.h
743
#define RMIXL_GPIO_EXT_INT_HI_CTL __BIT(1) /* generate (output) INT_HI_L */
sys/arch/mips/rmi/rmixlreg.h
744
#define RMIXL_GPIO_EXT_INT_LO_CTL __BIT(0) /* generate (output) INT_LO_L */
sys/arch/mips/rmi/rmixlreg.h
753
#define RMIXL_GPIO_LOW_PWR_DIS_LP __BIT(0) /* Low Power disable */
sys/arch/mips/rmi/rmixlreg.h
754
#define RMIXL_GPIO_LOW_PWR_DIS_GMAC_QD_0 __BIT(1) /* GMAC Quad 0 (GMAC 0..3) disable */
sys/arch/mips/rmi/rmixlreg.h
755
#define RMIXL_GPIO_LOW_PWR_DIS_GMAC_QD_1 __BIT(2) /* GMAC Quad 1 (GMAC 4..7) disable */
sys/arch/mips/rmi/rmixlreg.h
756
#define RMIXL_GPIO_LOW_PWR_DIS_USB __BIT(3) /* USB disable */
sys/arch/mips/rmi/rmixlreg.h
757
#define RMIXL_GPIO_LOW_PWR_DIS_PCIE __BIT(4) /* PCIE disable */
sys/arch/mips/rmi/rmixlreg.h
758
#define RMIXL_GPIO_LOW_PWR_DIS_CDE __BIT(5) /* Compression/Decompression Engine disable */
sys/arch/mips/rmi/rmixlreg.h
759
#define RMIXL_GPIO_LOW_PWR_DIS_DMA __BIT(6) /* DMA Engine disable */
sys/arch/mips/rmi/rmixlreg.h
788
#define RMIXL_FLASH_CSDEV_BFN __BIT(15) /* Boot From Nand
sys/arch/mips/rmi/rmixlreg.h
793
#define RMIXL_FLASH_CSDEV_NANDEN __BIT(14) /* NAND Flash Enable
sys/arch/mips/rmi/rmixlreg.h
797
#define RMIXL_FLASH_CSDEV_ADVTYPE __BIT(13) /* Add Valid Sensing Type
sys/arch/mips/rmi/rmixlreg.h
801
#define RMIXL_FLASH_CSDEV_PARITY_TYPE __BIT(12) /* Parity Type
sys/arch/mips/rmi/rmixlreg.h
805
#define RMIXL_FLASH_CSDEV_PARITY_EN __BIT(11) /* Parity Enable */
sys/arch/mips/rmi/rmixlreg.h
806
#define RMIXL_FLASH_CSDEV_GENIF_EN __BIT(10) /* Generic PLD/FPGA interface mode
sys/arch/mips/rmi/rmixlreg.h
811
#define RMIXL_FLASH_CSDEV_PCMCIA_EN __BIT(9) /* PCMCIA Interface mode */
sys/arch/mips/rmi/rmixlreg.h
819
#define RMIXL_FLASH_CSDEV_MX_ADDR __BIT(6) /* Multiplexed Address
sys/arch/mips/rmi/rmixlreg.h
826
#define RMIXL_FLASH_CSDEV_WAIT_POL __BIT(5) /* WAIT polarity
sys/arch/mips/rmi/rmixlreg.h
830
#define RMIXL_FLASH_CSDEV_WAIT_EN __BIT(4) /* Enable External WAIT Ack mode */
sys/arch/mips/rmi/rmixlreg.h
89
#define RMIXL_MSG_STS0_RESV __BIT(23)
sys/arch/mips/rmi/rmixlreg.h
955
#define RMIXL_UG_CTRL1_HOST_RST __BIT(1) /* Resets the Host Controller
sys/arch/mips/rmi/rmixlreg.h
959
#define RMIXL_UG_CTRL1_DEV_RST __BIT(0) /* Resets the Device Controller
sys/arch/mips/rmi/rmixlreg.h
96
#define RMIXL_MSG_STS0_LEF __BIT(5) /* Load Empty Fail */
sys/arch/mips/rmi/rmixlreg.h
97
#define RMIXL_MSG_STS0_LPF __BIT(4) /* Load Pending Fail */
sys/arch/mips/rmi/rmixlreg.h
977
#define RMIXL_UG_CTRL2_RESb __BIT(15)
sys/arch/mips/rmi/rmixlreg.h
978
#define RMIXL_UG_CTRL2_WEAK_PDEN __BIT(14) /* 500kOhm Pull-Down Resistor on D+ and D- Enable */
sys/arch/mips/rmi/rmixlreg.h
979
#define RMIXL_UG_CTRL2_DP_PULLUP_ESD __BIT(13) /* D+ Pull-Up Resistor Enable */
sys/arch/mips/rmi/rmixlreg.h
98
#define RMIXL_MSG_STS0_LMP __BIT(3) /* Load Message Pending */
sys/arch/mips/rmi/rmixlreg.h
980
#define RMIXL_UG_CTRL2_ESD_TEST_MODE __BIT(12) /* D+ Pull-Up Resistor Control Select */
sys/arch/mips/rmi/rmixlreg.h
982
__BIT(11) /* Port_1 High-Byte Transmit Bit-Stuffing Enable */
sys/arch/mips/rmi/rmixlreg.h
984
__BIT(10) /* Port_0 High-Byte Transmit Bit-Stuffing Enable */
sys/arch/mips/rmi/rmixlreg.h
986
__BIT(9) /* Port_1 Low-Byte Transmit Bit-Stuffing Enable */
sys/arch/mips/rmi/rmixlreg.h
988
__BIT(8) /* Port_0 Low-Byte Transmit Bit-Stuffing Enable */
sys/arch/mips/rmi/rmixlreg.h
99
#define RMIXL_MSG_STS0_SCF __BIT(2) /* Send Credit Fail */
sys/arch/mips/rmi/rmixlreg.h
990
#define RMIXL_UG_CTRL2_LOOPBACK_ENB_1 __BIT(5) /* Port_1 Loopback Test Enable */
sys/arch/mips/rmi/rmixlreg.h
991
#define RMIXL_UG_CTRL2_LOOPBACK_ENB_0 __BIT(4) /* Port_0 Loopback Test Enable */
sys/arch/mips/rmi/rmixlreg.h
992
#define RMIXL_UG_CTRL2_DEVICE_VBUS __BIT(3) /* VBUS detected (Device mode only) */
sys/arch/mips/rmi/rmixlreg.h
993
#define RMIXL_UG_CTRL2_PHY_PORT_RST_1 __BIT(2) /* Resets Port_1 of the PHY
sys/arch/mips/rmi/rmixlreg.h
997
#define RMIXL_UG_CTRL2_PHY_PORT_RST_0 __BIT(1) /* Resets Port_0 of the PHY
sys/arch/or1k/include/spr.h
57
#define SR_SUMRA __BIT(16)
sys/arch/or1k/include/spr.h
58
#define SR_FO __BIT(15)
sys/arch/or1k/include/spr.h
59
#define SR_EPH __BIT(14)
sys/arch/or1k/include/spr.h
60
#define SR_DSX __BIT(13)
sys/arch/or1k/include/spr.h
61
#define SR_OVE __BIT(12)
sys/arch/or1k/include/spr.h
62
#define SR_OV __BIT(11)
sys/arch/or1k/include/spr.h
63
#define SR_CY __BIT(10)
sys/arch/or1k/include/spr.h
64
#define SR_F __BIT(9)
sys/arch/or1k/include/spr.h
65
#define SR_CE __BIT(8)
sys/arch/or1k/include/spr.h
66
#define SR_LEE __BIT(7)
sys/arch/or1k/include/spr.h
67
#define SR_IME __BIT(6)
sys/arch/or1k/include/spr.h
68
#define SR_DME __BIT(5)
sys/arch/or1k/include/spr.h
69
#define SR_ICE __BIT(4)
sys/arch/or1k/include/spr.h
70
#define SR_DCE __BIT(3)
sys/arch/or1k/include/spr.h
71
#define SR_IEE __BIT(2)
sys/arch/or1k/include/spr.h
72
#define SR_TEE __BIT(1)
sys/arch/or1k/include/spr.h
73
#define SR_SM __BIT(0)
sys/arch/or1k/include/spr.h
76
#define FPCSR_DZF __BIT(11)
sys/arch/or1k/include/spr.h
77
#define FPCSR_INF __BIT(10)
sys/arch/or1k/include/spr.h
78
#define FPCSR_IVF __BIT(9)
sys/arch/or1k/include/spr.h
79
#define FPCSR_IXF __BIT(8)
sys/arch/or1k/include/spr.h
80
#define FPCSR_ZF __BIT(7)
sys/arch/or1k/include/spr.h
81
#define FPCSR_QNF __BIT(6)
sys/arch/or1k/include/spr.h
82
#define FPCSR_SNF __BIT(5)
sys/arch/or1k/include/spr.h
83
#define FPCSR_UNF __BIT(4)
sys/arch/or1k/include/spr.h
84
#define FPCSR_OVF __BIT(3)
sys/arch/or1k/include/spr.h
90
#define FPCSR_FPEE __BIT(0)
sys/arch/powerpc/booke/dev/pq3gpio.c
222
u_int mask = __BIT(31);
sys/arch/powerpc/booke/dev/pq3gpio.c
269
uint32_t gpiomask = __BIT(31);
sys/arch/powerpc/booke/dev/pq3gpio.c
274
if (pmuxcr & __BIT(gpio2pmuxcr_map[i])) {
sys/arch/powerpc/booke/dev/pq3gpio.c
390
{ 0, __BIT(12), 0, PMUXCR_SDHC_WP },
sys/arch/powerpc/booke/dev/pq3gpio.c
391
{ __BIT(15), __BIT(8), 0, PMUXCR_USB1 },
sys/arch/powerpc/booke/dev/pq3gpio.c
392
{ __BITS(14,4)|__BIT(16)|__BITS(27,17)|__BIT(30),
sys/arch/powerpc/booke/dev/pq3gpio.c
393
__BIT(1)|__BITS(3,2), 0, PMUXCR_QE0 },
sys/arch/powerpc/booke/dev/pq3gpio.c
396
{ __BIT(29), __BITS(19,18), 0, PMUXCR_QE9 },
sys/arch/powerpc/booke/dev/pq3gpio.c
399
{ 0, __BIT(20), 0, PMUXCR_QE12 },
sys/arch/powerpc/booke/dev/pq3gpio.c
439
{ __BIT(8), PMUXCR_SDHC_CD },
sys/arch/powerpc/booke/dev/pq3gpio.c
440
{ __BIT(9), PMUXCR_SDHC_WP },
sys/arch/powerpc/booke/dev/pq3gpio.c
445
{ __BIT(10), PMUXCR_TSEC3_TS },
sys/arch/powerpc/booke/dev/pq3gpio.c
446
{ __BIT(11), PMUXCR_TSEC3_TS },
sys/arch/powerpc/booke/e500_intr.c
1246
if (info->ii_onchip_bitmap[j / 32] & __BIT(j & 31)) {
sys/arch/powerpc/booke/pci/pq3pci.c
1141
if ((slot_status & __BIT(6+16)) == 0)
sys/arch/powerpc/booke/pci/pq3pci.c
1196
uint32_t irq_mask = __BIT(irq & 31);
sys/arch/powerpc/booke/pci/pq3pci.c
617
uint32_t this_msi = __BIT(31);
sys/arch/powerpc/fpu/fpu_emu.c
311
sign = (reg & __BIT(63)) >> 32;
sys/arch/powerpc/fpu/fpu_emu.c
313
if (exp > -127 || (reg & ~__BIT(63)) == 0) {
sys/arch/powerpc/fpu/fpu_emu.c
321
word = ((reg & __BIT(62)) >> 32) |
sys/arch/powerpc/fpu/fpu_emu.c
326
frac = __SHIFTOUT(__BIT(52) | reg, __BITS(52, 29 + shift));
sys/arch/powerpc/include/booke/e500reg.h
267
#define PBFR_PAH __BIT(0)
sys/arch/powerpc/include/booke/e500reg.h
43
#define __PPCBIT(n) __BIT(31-(n))
sys/arch/powerpc/include/intr.h
116
#define PIC_VIRQ_TO_MASK(v) __BIT(HWIRQ_MAX - (v))
sys/arch/powerpc/mpc5200/bestcommreg.h
106
#define SDMA_INT_TEA __BIT(28) /* XLB bus error */
sys/arch/powerpc/mpc5200/bestcommreg.h
109
#define SDMA_INT_DBG __BIT(31) /* debug event */
sys/arch/powerpc/mpc5200/cdm.c
71
#define CDM_BIT(n) __BIT(31 - (n))
sys/arch/powerpc/mpc5200/fecreg.h
100
#define FEC_R_CNTRL_FCE __BIT(5) /* flow control enable */
sys/arch/powerpc/mpc5200/fecreg.h
101
#define FEC_R_CNTRL_PROM __BIT(3) /* promiscuous */
sys/arch/powerpc/mpc5200/fecreg.h
102
#define FEC_R_CNTRL_MII_MODE __BIT(2) /* MII (vs 7-wire) mode */
sys/arch/powerpc/mpc5200/fecreg.h
103
#define FEC_R_CNTRL_DRT __BIT(1) /* disable receive on tx */
sys/arch/powerpc/mpc5200/fecreg.h
104
#define FEC_R_CNTRL_LOOP __BIT(0) /* internal loopback */
sys/arch/powerpc/mpc5200/fecreg.h
107
#define FEC_X_CNTRL_RFC_PAUSE __BIT(4) /* (RO) paused by rx PAUSE */
sys/arch/powerpc/mpc5200/fecreg.h
108
#define FEC_X_CNTRL_TFC_PAUSE __BIT(3) /* transmit a PAUSE frame */
sys/arch/powerpc/mpc5200/fecreg.h
109
#define FEC_X_CNTRL_FDEN __BIT(2) /* full duplex enable */
sys/arch/powerpc/mpc5200/fecreg.h
110
#define FEC_X_CNTRL_HBC __BIT(1) /* heartbeat control */
sys/arch/powerpc/mpc5200/fecreg.h
111
#define FEC_X_CNTRL_GTS __BIT(0) /* graceful transmit stop */
sys/arch/powerpc/mpc5200/fecreg.h
116
#define FEC_MIB_CONTROL_MIB_DISABLE __BIT(31) /* freeze the counters */
sys/arch/powerpc/mpc5200/fecreg.h
117
#define FEC_MIB_CONTROL_MIB_IDLE __BIT(30) /* (RO) block is idle */
sys/arch/powerpc/mpc5200/fecreg.h
68
#define FEC_FIFO_CTRL_FRAME __BIT(31 - 4) /* frame mode enable */
sys/arch/powerpc/mpc5200/fecreg.h
75
#define FEC_RESET_CNTRL_FIFO_EN __BIT(31 - 7) /* RCTL[0]: enable */
sys/arch/powerpc/mpc5200/fecreg.h
76
#define FEC_RESET_CNTRL_FIFO_RST __BIT(31 - 6) /* RCTL[1]: reset FIFOs */
sys/arch/powerpc/mpc5200/fecreg.h
82
#define FEC_INT_HBERR __BIT(31) /* heartbeat error */
sys/arch/powerpc/mpc5200/fecreg.h
83
#define FEC_INT_BABR __BIT(30) /* babbling receive */
sys/arch/powerpc/mpc5200/fecreg.h
84
#define FEC_INT_BABT __BIT(29) /* babbling transmit */
sys/arch/powerpc/mpc5200/fecreg.h
85
#define FEC_INT_GRA __BIT(28) /* graceful stop complete */
sys/arch/powerpc/mpc5200/fecreg.h
86
#define FEC_INT_TFINT __BIT(27) /* transmit frame */
sys/arch/powerpc/mpc5200/fecreg.h
87
#define FEC_INT_MII __BIT(23) /* MII transfer complete */
sys/arch/powerpc/mpc5200/fecreg.h
88
#define FEC_INT_LATE_COLL __BIT(21) /* late collision */
sys/arch/powerpc/mpc5200/fecreg.h
89
#define FEC_INT_COL_RETRY_LIM __BIT(20) /* collision retry limit */
sys/arch/powerpc/mpc5200/fecreg.h
90
#define FEC_INT_XFIFO_UN __BIT(19) /* transmit FIFO underrun */
sys/arch/powerpc/mpc5200/fecreg.h
91
#define FEC_INT_XFIFO_ERROR __BIT(18) /* transmit FIFO error */
sys/arch/powerpc/mpc5200/fecreg.h
92
#define FEC_INT_RFIFO_ERROR __BIT(17) /* receive FIFO error */
sys/arch/powerpc/mpc5200/fecreg.h
95
#define FEC_ECNTRL_ETHER_EN __BIT(1) /* enable the controller */
sys/arch/powerpc/mpc5200/fecreg.h
96
#define FEC_ECNTRL_RESET __BIT(0) /* soft reset (self-clearing) */
sys/arch/powerpc/mpc5200/pscreg.h
100
#define INT_TXEMP __BIT(11)
sys/arch/powerpc/mpc5200/pscreg.h
101
#define INT_DB __BIT(10)
sys/arch/powerpc/mpc5200/pscreg.h
102
#define INT_RXRDY __BIT(9)
sys/arch/powerpc/mpc5200/pscreg.h
103
#define INT_TXRDY __BIT(8)
sys/arch/powerpc/mpc5200/pscreg.h
104
#define INT_ERROR __BIT(6)
sys/arch/powerpc/mpc5200/pscreg.h
73
#define SR_RB __BIT(15) /* received break */
sys/arch/powerpc/mpc5200/pscreg.h
74
#define SR_FE __BIT(14) /* framing error */
sys/arch/powerpc/mpc5200/pscreg.h
75
#define SR_PE __BIT(13) /* parity error */
sys/arch/powerpc/mpc5200/pscreg.h
76
#define SR_ORERR __BIT(12) /* overrun error */
sys/arch/powerpc/mpc5200/pscreg.h
77
#define SR_TXEMP __BIT(11) /* transmitter empty */
sys/arch/powerpc/mpc5200/pscreg.h
78
#define SR_TXRDY __BIT(10) /* transmitter ready */
sys/arch/powerpc/mpc5200/pscreg.h
79
#define SR_FFULL __BIT(9) /* receive FIFO full */
sys/arch/powerpc/mpc5200/pscreg.h
80
#define SR_RXRDY __BIT(8) /* receiver ready */
sys/arch/powerpc/mpc5200/pscreg.h
98
#define INT_IPC __BIT(15)
sys/arch/powerpc/mpc5200/pscreg.h
99
#define INT_ORERR __BIT(12)
sys/arch/powerpc/powerpc/fix_unaligned.c
178
#define UAF_LOAD __BIT(0)
sys/arch/powerpc/powerpc/fix_unaligned.c
179
#define UAF_HALF __BIT(1)
sys/arch/powerpc/powerpc/fix_unaligned.c
180
#define UAF_ALGEBRA __BIT(2)
sys/arch/powerpc/powerpc/fix_unaligned.c
181
#define UAF_REVERSE __BIT(3)
sys/arch/powerpc/powerpc/fix_unaligned.c
182
#define UAF_UPDATE __BIT(4)
sys/arch/riscv/dev/plic.c
153
const uint32_t mask = __BIT(irq % 32);
sys/arch/riscv/dev/plic.c
166
const uint32_t mask = __BIT(irq % 32);
sys/arch/riscv/fdt/pcihost_fdtvar.h
30
#define PHYS_HI_RELO __BIT(31)
sys/arch/riscv/fdt/pcihost_fdtvar.h
31
#define PHYS_HI_PREFETCH __BIT(30)
sys/arch/riscv/fdt/pcihost_fdtvar.h
32
#define PHYS_HI_ALIASED __BIT(29)
sys/arch/riscv/include/bus_defs.h
312
#define _BUS_DMAMAP_COHERENT __BIT(16) /* no cache flush necessary on sync */
sys/arch/riscv/include/bus_defs.h
313
#define _BUS_DMAMAP_IS_BOUNCING __BIT(17) /* is bouncing current xfer */
sys/arch/riscv/include/bus_defs.h
314
#define _BUS_DMAMAP_NOALLOC __BIT(18) /* don't alloc memory from this range */
sys/arch/riscv/include/bus_defs.h
505
#define _BUS_DMA_IS_BOUNCING __BIT(2) /* is bouncing current xfer */
sys/arch/riscv/include/bus_defs.h
506
#define _BUS_DMA_HAS_BOUNCE __BIT(1) /* has bounce buffers */
sys/arch/riscv/include/bus_defs.h
508
#define _BUS_DMA_MIGHT_NEED_BOUNCE __BIT(0) /* may need bounce buffers */
sys/arch/riscv/include/bus_defs.h
91
#define BUS_SPACE_MAP_BUS1 __BIT(8)
sys/arch/riscv/include/bus_defs.h
92
#define BUS_SPACE_MAP_BUS2 __BIT(9)
sys/arch/riscv/include/bus_defs.h
93
#define BUS_SPACE_MAP_BUS3 __BIT(10)
sys/arch/riscv/include/bus_defs.h
94
#define BUS_SPACE_MAP_BUS4 __BIT(11)
sys/arch/riscv/include/cpu.h
90
#define CPUF_PRIMARY __BIT(0) /* CPU is primary CPU */
sys/arch/riscv/include/cpu.h
91
#define CPUF_PRESENT __BIT(1) /* CPU is present */
sys/arch/riscv/include/cpu.h
92
#define CPUF_RUNNING __BIT(2) /* CPU is running */
sys/arch/riscv/include/cpu.h
93
#define CPUF_PAUSED __BIT(3) /* CPU is paused */
sys/arch/riscv/include/fenv.h
14
#define FE_INEXACT ((int)__BIT(0)) /* Result inexact */
sys/arch/riscv/include/fenv.h
15
#define FE_UNDERFLOW ((int)__BIT(1)) /* Result underflowed */
sys/arch/riscv/include/fenv.h
16
#define FE_OVERFLOW ((int)__BIT(2)) /* Result overflowed */
sys/arch/riscv/include/fenv.h
17
#define FE_DIVBYZERO ((int)__BIT(3)) /* divide-by-zero */
sys/arch/riscv/include/fenv.h
18
#define FE_INVALID ((int)__BIT(4)) /* Result invalid */
sys/arch/riscv/include/mutex.h
63
#define MTX_LOCK __BIT(8) // just one bit
sys/arch/riscv/include/pci_machdep.h
85
#define RISCV_PCI_INTR_MPSAFE __BIT(31)
sys/arch/riscv/include/pci_machdep.h
86
#define RISCV_PCI_INTR_MSIX __BIT(30)
sys/arch/riscv/include/pci_machdep.h
87
#define RISCV_PCI_INTR_MSI __BIT(29)
sys/arch/riscv/include/pmap.h
181
#define PMAP_DEV __BIT(29) /* 0x2000_0000 */
sys/arch/riscv/include/pte.h
101
#define PTE_D __BIT(7) // Dirty
sys/arch/riscv/include/pte.h
102
#define PTE_A __BIT(6) // Accessed
sys/arch/riscv/include/pte.h
103
#define PTE_G __BIT(5) // Global
sys/arch/riscv/include/pte.h
104
#define PTE_U __BIT(4) // User
sys/arch/riscv/include/pte.h
105
#define PTE_X __BIT(3) // eXecute
sys/arch/riscv/include/pte.h
106
#define PTE_W __BIT(2) // Write
sys/arch/riscv/include/pte.h
107
#define PTE_R __BIT(1) // Read
sys/arch/riscv/include/pte.h
108
#define PTE_V __BIT(0) // Valid
sys/arch/riscv/include/pte.h
61
#define PTE_N __BIT(63) // Svnapot
sys/arch/riscv/include/pte.h
78
#define PTE_XMAE_SO __BIT(63) // Strong Order
sys/arch/riscv/include/pte.h
79
#define PTE_XMAE_C __BIT(62) // Cacheable
sys/arch/riscv/include/pte.h
80
#define PTE_XMAE_B __BIT(61) // Bufferable
sys/arch/riscv/include/pte.h
81
#define PTE_XMAE_SH __BIT(60) // Shareable
sys/arch/riscv/include/pte.h
82
#define PTE_XMAE_T __BIT(59) // Trustable
sys/arch/riscv/include/pte.h
97
#define PTE_WIRED __BIT(9)
sys/arch/riscv/include/sysreg.h
169
__BIT(17) | __BITS(12, 11) | __BIT(7) | __BITS(4, 2) | \
sys/arch/riscv/include/sysreg.h
170
__BIT(0)
sys/arch/riscv/include/sysreg.h
171
#define SR_SD __BIT(63) // any of FS or VS or XS dirty
sys/arch/riscv/include/sysreg.h
180
__BIT(17) | __BITS(12, 11) | __BIT(7) | __BITS(4, 2) | \
sys/arch/riscv/include/sysreg.h
181
__BIT(0)
sys/arch/riscv/include/sysreg.h
182
#define SR_SD __BIT(31) // any of FS or VS or XS dirty
sys/arch/riscv/include/sysreg.h
187
#define SR_MXR __BIT(19) // Make eXecutable Readable
sys/arch/riscv/include/sysreg.h
188
#define SR_SUM __BIT(18) // permit Supervisor User Memory access
sys/arch/riscv/include/sysreg.h
206
#define SR_SPP __BIT(8) // Priv level before supervisor mode
sys/arch/riscv/include/sysreg.h
208
#define SR_UBE __BIT(6) // User-mode endianness
sys/arch/riscv/include/sysreg.h
209
#define SR_SPIE __BIT(5) // S-Mode interrupts enabled before trap
sys/arch/riscv/include/sysreg.h
211
#define SR_SIE __BIT(1) // Supervisor mode interrupt enable
sys/arch/riscv/include/sysreg.h
218
#define SIP_SEIP __BIT(9) // S-mode interrupt pending
sys/arch/riscv/include/sysreg.h
220
#define SIP_STIP __BIT(5) // S-mode timer interrupt pending
sys/arch/riscv/include/sysreg.h
222
#define SIP_SSIP __BIT(1) // S-mode software interrupt pending
sys/arch/riscv/include/sysreg.h
228
#define SIE_SEIE __BIT(9) // S-mode interrupt enable
sys/arch/riscv/include/sysreg.h
230
#define SIE_STIE __BIT(5) // S-mode timer interrupt enable
sys/arch/riscv/include/sysreg.h
232
#define SIE_SSIE __BIT(1) // S-mode software interrupt enable
sys/arch/riscv/include/sysreg.h
244
#define CAUSE_INTERRUPT_P(cause) ((cause) & __BIT(XLEN - 1))
sys/arch/riscv/include/sysreg.h
316
#define SATP_MODE __BIT(31) // Translation mode
sys/arch/riscv/include/sysreg.h
351
#define TX_SXSTATUS_MAEE __BIT(21)
sys/arch/riscv/include/sysreg.h
352
#define TH_SXSTATUS_THEADISAEE __BIT(22)
sys/arch/riscv/include/sysreg.h
56
#define FCSR_NV __BIT(4) // iNValid operation
sys/arch/riscv/include/sysreg.h
57
#define FCSR_DZ __BIT(3) // Divide by Zero
sys/arch/riscv/include/sysreg.h
58
#define FCSR_OF __BIT(2) // OverFlow
sys/arch/riscv/include/sysreg.h
59
#define FCSR_UF __BIT(1) // UnderFlow
sys/arch/riscv/include/sysreg.h
60
#define FCSR_NX __BIT(0) // iNeXact
sys/arch/riscv/riscv/cpu_subr.c
124
const u_long bit = __BIT(cpuindex % CPUINDEX_DIVISOR);
sys/arch/riscv/riscv/cpu_subr.c
147
return (atomic_load_acquire(&riscv_cpu_hatched[off]) & __BIT(bit)) != 0;
sys/arch/riscv/riscv/cpu_subr.c
156
const u_long bit = __BIT(cpuindex % CPUINDEX_DIVISOR);
sys/arch/riscv/riscv/cpu_subr.c
170
const u_long bit = __BIT(cpuindex % CPUINDEX_DIVISOR);
sys/arch/riscv/riscv/cpu_subr.c
94
hartmask |= __BIT(hartid);
sys/arch/riscv/riscv/interrupt.c
178
const uint32_t ipi_mask = __BIT(req);
sys/arch/riscv/riscv/interrupt.c
187
hartmask |= __BIT(hartid);
sys/arch/riscv/riscv/ipifuncs.c
103
if (ipi_mask & __BIT(IPI_NOP)) {
sys/arch/riscv/riscv/ipifuncs.c
107
if (ipi_mask & __BIT(IPI_AST)) {
sys/arch/riscv/riscv/ipifuncs.c
111
if (ipi_mask & __BIT(IPI_SUSPEND)) {
sys/arch/riscv/riscv/ipifuncs.c
115
if (ipi_mask & __BIT(IPI_HALT)) {
sys/arch/riscv/riscv/ipifuncs.c
119
if (ipi_mask & __BIT(IPI_XCALL)) {
sys/arch/riscv/riscv/ipifuncs.c
123
if (ipi_mask & __BIT(IPI_GENERIC)) {
sys/arch/riscv/riscv/ipifuncs.c
128
if (ipi_mask & __BIT(IPI_KPREEMPT)) {
sys/arch/riscv/riscv/kobj_machdep.c
342
const uint32_t immA = __SHIFTOUT(addend, __BIT(12));
sys/arch/riscv/riscv/kobj_machdep.c
345
const uint32_t immD = __SHIFTOUT(addend, __BIT(11));
sys/arch/riscv/riscv/kobj_machdep.c
347
__SHIFTIN(immA, __BIT(31)) |
sys/arch/riscv/riscv/kobj_machdep.c
350
__SHIFTIN(immD, __BIT(7));
sys/arch/riscv/riscv/kobj_machdep.c
364
const uint32_t immA = __SHIFTOUT(addend, __BIT(20));
sys/arch/riscv/riscv/kobj_machdep.c
366
const uint32_t immC = __SHIFTOUT(addend, __BIT(11));
sys/arch/riscv/riscv/kobj_machdep.c
369
__SHIFTIN(immA, __BIT(31)) |
sys/arch/riscv/riscv/kobj_machdep.c
371
__SHIFTIN(immC, __BIT(20)) |
sys/arch/riscv/riscv/kobj_machdep.c
440
const uint32_t immA = __SHIFTOUT(addend, __BIT(20));
sys/arch/riscv/riscv/kobj_machdep.c
442
const uint32_t immC = __SHIFTOUT(addend, __BIT(11));
sys/arch/riscv/riscv/kobj_machdep.c
445
__SHIFTIN(immA, __BIT(31)) |
sys/arch/riscv/riscv/kobj_machdep.c
447
__SHIFTIN(immC, __BIT(20)) |
sys/arch/riscv/riscv/kobj_machdep.c
473
const uint16_t immA = __SHIFTOUT(addend, __BIT(8));
sys/arch/riscv/riscv/kobj_machdep.c
477
const uint16_t immE = __SHIFTOUT(addend, __BIT(5));
sys/arch/riscv/riscv/kobj_machdep.c
480
__SHIFTIN(immA, __BIT(12)) |
sys/arch/riscv/riscv/kobj_machdep.c
484
__SHIFTIN(immE, __BIT(2));
sys/arch/riscv/riscv/kobj_machdep.c
497
const uint16_t immA = __SHIFTOUT(addend, __BIT(11));
sys/arch/riscv/riscv/kobj_machdep.c
498
const uint16_t immB = __SHIFTOUT(addend, __BIT(4));
sys/arch/riscv/riscv/kobj_machdep.c
500
const uint16_t immD = __SHIFTOUT(addend, __BIT(10));
sys/arch/riscv/riscv/kobj_machdep.c
501
const uint16_t immE = __SHIFTOUT(addend, __BIT(6));
sys/arch/riscv/riscv/kobj_machdep.c
502
const uint16_t immF = __SHIFTOUT(addend, __BIT(7));
sys/arch/riscv/riscv/kobj_machdep.c
504
const uint16_t immH = __SHIFTOUT(addend, __BIT(5));
sys/arch/riscv/riscv/kobj_machdep.c
507
__SHIFTIN(immA, __BIT(12)) |
sys/arch/riscv/riscv/kobj_machdep.c
508
__SHIFTIN(immB, __BIT(11)) |
sys/arch/riscv/riscv/kobj_machdep.c
510
__SHIFTIN(immD, __BIT(8)) |
sys/arch/riscv/riscv/kobj_machdep.c
511
__SHIFTIN(immE, __BIT(7)) |
sys/arch/riscv/riscv/kobj_machdep.c
512
__SHIFTIN(immF, __BIT(6)) |
sys/arch/riscv/riscv/kobj_machdep.c
514
__SHIFTIN(immH, __BIT(2));
sys/arch/riscv/riscv/kobj_machdep.c
527
const uint16_t immA = __SHIFTOUT(addend, __BIT(17));
sys/arch/riscv/riscv/kobj_machdep.c
529
const uint16_t mask = __BIT(12) | __BITS(6, 2);
sys/arch/riscv/riscv/kobj_machdep.c
531
__SHIFTIN(immA, __BIT(12)) |
sys/arch/riscv/riscv/riscv_machdep.c
980
if (va & __BIT(topbit)) {
sys/arch/riscv/riscv/riscv_tlb.c
137
hartmask |= __BIT(hartid);
sys/arch/riscv/riscv/riscv_tlb.c
98
hartmask |= __BIT(hartid);
sys/arch/riscv/riscv/trap.c
56
#define MACHINE_ECALL_TRAP_MASK (__BIT(CAUSE_MACHINE_ECALL))
sys/arch/riscv/riscv/trap.c
580
const register_t fault_mask = __BIT(code);
sys/arch/riscv/riscv/trap.c
59
(__BIT(CAUSE_SUPERVISOR_ECALL))
sys/arch/riscv/riscv/trap.c
61
#define USER_ECALL_TRAP_MASK (__BIT(CAUSE_USER_ECALL))
sys/arch/riscv/riscv/trap.c
63
#define SYSCALL_TRAP_MASK (__BIT(CAUSE_SYSCALL))
sys/arch/riscv/riscv/trap.c
65
#define BREAKPOINT_TRAP_MASK (__BIT(CAUSE_BREAKPOINT))
sys/arch/riscv/riscv/trap.c
67
#define INSTRUCTION_TRAP_MASK (__BIT(CAUSE_ILLEGAL_INSTRUCTION))
sys/arch/riscv/riscv/trap.c
69
#define FAULT_TRAP_MASK (__BIT(CAUSE_FETCH_ACCESS) \
sys/arch/riscv/riscv/trap.c
70
|__BIT(CAUSE_LOAD_ACCESS) \
sys/arch/riscv/riscv/trap.c
71
|__BIT(CAUSE_STORE_ACCESS) \
sys/arch/riscv/riscv/trap.c
72
|__BIT(CAUSE_FETCH_PAGE_FAULT) \
sys/arch/riscv/riscv/trap.c
73
|__BIT(CAUSE_LOAD_PAGE_FAULT) \
sys/arch/riscv/riscv/trap.c
74
|__BIT(CAUSE_STORE_PAGE_FAULT))
sys/arch/riscv/riscv/trap.c
76
#define MISALIGNED_TRAP_MASK (__BIT(CAUSE_FETCH_MISALIGNED) \
sys/arch/riscv/riscv/trap.c
77
|__BIT(CAUSE_LOAD_MISALIGNED) \
sys/arch/riscv/riscv/trap.c
78
|__BIT(CAUSE_STORE_MISALIGNED))
sys/arch/riscv/sifive/fu540_prci.c
53
#define PLL1_CKE __BIT(24)
sys/arch/riscv/starfive/jh7100_pinctrl.c
111
#define DT_GPIOMUX_DOUTREV_MASK __BIT(7)
sys/arch/riscv/starfive/jh7100_pinctrl.c
112
#define DT_GPIOMUX_DOENREV_MASK __BIT(6)
sys/arch/riscv/starfive/jh7100_pinctrl.c
66
#define GPO_DOUT_REVERSE __BIT(31)
sys/arch/riscv/starfive/jh7100_pinctrl.c
69
#define GPO_DOEN_REVERSE __BIT(31)
sys/arch/riscv/starfive/jh7100_pinctrl.c
85
#define PAD_BIAS_STRONG_PULLUP __BIT(8)
sys/arch/riscv/starfive/jh7100_pinctrl.c
86
#define PAD_INPUT_ENABLE __BIT(7)
sys/arch/riscv/starfive/jh7100_pinctrl.c
87
#define PAD_INPUT_SCHMITT_ENABLE __BIT(6)
sys/arch/riscv/starfive/jh7100_pinctrl.c
88
#define PAD_BIAS_DISABLE __BIT(5)
sys/arch/riscv/starfive/jh7100_pinctrl.c
89
#define PAD_BIAS_PULLDOWN __BIT(4)
sys/arch/riscv/starfive/jh7110_clkc.c
1012
WR4(sc, assert_reg, val | __BIT(bit));
sys/arch/riscv/starfive/jh7110_clkc.c
1014
WR4(sc, assert_reg, val & ~__BIT(bit));
sys/arch/riscv/starfive/jh7110_clkc.c
1020
bool asserted = (status & __BIT(bit)) == 0;
sys/arch/riscv/starfive/jh7110_pcie.c
101
#define PLDA_MISC_PHYFUNC_DISABLE __BIT(15)
sys/arch/riscv/starfive/jh7110_pcie.c
103
#define PLDA_WINROM_PREF64SUPPORT __BIT(3)
sys/arch/riscv/starfive/jh7110_pcie.c
106
#define PLDA_IMASK_INT_INTA __BIT(24)
sys/arch/riscv/starfive/jh7110_pcie.c
107
#define PLDA_IMASK_INT_INTB __BIT(25)
sys/arch/riscv/starfive/jh7110_pcie.c
108
#define PLDA_IMASK_INT_INTC __BIT(26)
sys/arch/riscv/starfive/jh7110_pcie.c
109
#define PLDA_IMASK_INT_INTD __BIT(27)
sys/arch/riscv/starfive/jh7110_pcie.c
111
#define PLDA_IMASK_INT_MSI __BIT(28)
sys/arch/riscv/starfive/jh7110_pcie.c
113
#define PLDA_ISTATUS_INT_INTA __BIT(24)
sys/arch/riscv/starfive/jh7110_pcie.c
114
#define PLDA_ISTATUS_INT_INTB __BIT(25)
sys/arch/riscv/starfive/jh7110_pcie.c
115
#define PLDA_ISTATUS_INT_INTC __BIT(26)
sys/arch/riscv/starfive/jh7110_pcie.c
116
#define PLDA_ISTATUS_INT_INTD __BIT(27)
sys/arch/riscv/starfive/jh7110_pcie.c
118
#define PLDA_ISTATUS_INT_MSI __BIT(28)
sys/arch/riscv/starfive/jh7110_pcie.c
124
#define PLDA_PMSG_LTR_SUPPORT __BIT(2)
sys/arch/riscv/starfive/jh7110_pcie.c
138
#define PLDA_ATR_IMPL __BIT(0)
sys/arch/riscv/starfive/jh7110_pcie.c
159
#define STG_SYSCON_CLKREQ __BIT(22)
sys/arch/riscv/starfive/jh7110_pcie.c
167
#define STG_SYSCON_K_RP_NEP __BIT(8)
sys/arch/riscv/starfive/jh7110_pcie.c
170
#define DATA_LINK_ACTIVE __BIT(5)
sys/arch/riscv/starfive/jh7110_pinctrl.c
108
#define JH7110_PADCFG_IE __BIT(0)
sys/arch/riscv/starfive/jh7110_pinctrl.c
114
#define JH7110_PADCFG_PU __BIT(3)
sys/arch/riscv/starfive/jh7110_pinctrl.c
115
#define JH7110_PADCFG_PD __BIT(4)
sys/arch/riscv/starfive/jh7110_pinctrl.c
117
#define JH7110_PADCFG_SLEW __BIT(5)
sys/arch/riscv/starfive/jh7110_pinctrl.c
118
#define JH7110_PADCFG_SMT __BIT(6)
sys/arch/riscv/starfive/jh7110_pinctrl.c
119
#define JH7110_PADCFG_POS __BIT(7)
sys/arch/riscv/starfive/jh7110_pinctrl.c
447
#define JH7110_PADCFG_POS __BIT(7)
sys/arch/riscv/starfive/jh7110_pinctrl.c
448
#define JH7110_PADCFG_SMT __BIT(6)
sys/arch/riscv/starfive/jh7110_pinctrl.c
449
#define JH7110_PADCFG_SLEW __BIT(5)
sys/arch/riscv/starfive/jh7110_pinctrl.c
646
const uint32_t mask = __BIT(pin_no % pins_per_bank);
sys/arch/riscv/starfive/jh7110_trng.c
123
#define JH7110_TRNG_BCONF_AUTO_RESEED_LOOPBACK __BIT(5)
sys/arch/riscv/starfive/jh7110_trng.c
124
#define JH7110_TRNG_BCONF_MODE_AFTER_RST __BIT(4)
sys/arch/riscv/starfive/jh7110_trng.c
125
#define JH7110_TRNG_BCONF_PRNG_LEN_AFTER_RST __BIT(3)
sys/arch/riscv/starfive/jh7110_trng.c
126
#define JH7110_TRNG_BCONF_MAX_PRNG_LEN __BIT(2)
sys/arch/riscv/starfive/jh7110_trng.c
76
#define JH7110_TRNG_STAT_SEEDED __BIT(9)
sys/arch/riscv/starfive/jh7110_trng.c
79
#define JH7110_TRNG_MODE_R256 __BIT(3)
sys/arch/riscv/starfive/jh7110_trng.c
82
#define JH7110_TRNG_IENABLE_GLOBAL __BIT(31)
sys/arch/riscv/starfive/jh7110_trng.c
83
#define JH7110_TRNG_IENABLE_LFSR_LOCKUP __BIT(4)
sys/arch/riscv/starfive/jh7110_trng.c
84
#define JH7110_TRNG_IENABLE_RQST_LOCKUP __BIT(3)
sys/arch/riscv/starfive/jh7110_trng.c
85
#define JH7110_TRNG_IENABLE_AGE_ALARM __BIT(2)
sys/arch/riscv/starfive/jh7110_trng.c
86
#define JH7110_TRNG_IENABLE_SEED_DONE __BIT(1)
sys/arch/riscv/starfive/jh7110_trng.c
87
#define JH7110_TRNG_IENABLE_RAND_RDY __BIT(0)
sys/arch/riscv/starfive/jh7110_trng.c
89
#define JH7110_TRNG_ISTATUS_LFSR_LOCKUP __BIT(4)
sys/arch/riscv/starfive/jh7110_trng.c
90
#define JH7110_TRNG_ISTATUS_RQST_LOCKUP __BIT(3)
sys/arch/riscv/starfive/jh7110_trng.c
91
#define JH7110_TRNG_ISTATUS_AGE_ALARM __BIT(2)
sys/arch/riscv/starfive/jh7110_trng.c
92
#define JH7110_TRNG_ISTATUS_SEED_DONE __BIT(1)
sys/arch/riscv/starfive/jh7110_trng.c
93
#define JH7110_TRNG_ISTATUS_RAND_RDY __BIT(0)
sys/arch/riscv/starfive/jh7110_trng.c
95
#define JH7110_TRNG_FEATURES_MM_RESET_STATE __BIT(3)
sys/arch/riscv/starfive/jh7110_trng.c
96
#define JH7110_TRNG_FEATURES_RAND_SEED_AVAIL __BIT(2)
sys/arch/riscv/starfive/jh71x0_clkc.h
158
#define JH71X0CLKC_DIV_GATE __BIT(0)
sys/arch/riscv/starfive/jh71x0_clkc.h
200
#define JH71X0CLKC_DIV_GATE __BIT(0)
sys/arch/riscv/starfive/jh71x0_clkc.h
235
#define JH71X0CLKC_MUX_GATE __BIT(0)
sys/arch/riscv/starfive/jh71x0_clkc.h
285
#define JH71X0CLKC_MUXDIV_GATE __BIT(0)
sys/arch/riscv/starfive/jh71x0_clkc.h
44
#define JH71X0_CLK_ENABLE __BIT(31)
sys/arch/riscv/starfive/jh71x0_clkc.h
45
#define JH71X0_CLK_INVERT __BIT(30)
sys/arch/riscv/starfive/jh71x0_temp.c
58
#define JH71X0_TEMP_RSTN __BIT(0)
sys/arch/riscv/starfive/jh71x0_temp.c
59
#define JH71X0_TEMP_PD __BIT(1)
sys/arch/riscv/starfive/jh71x0_temp.c
60
#define JH71X0_TEMP_RUN __BIT(2)
sys/arch/riscv/starfive/jh71x0_usb.c
65
#define JH7100_USB3_UTMI_IDDIG __BIT(21)
sys/arch/riscv/starfive/jh71x0_usb.c
68
#define JH7100_USB7_SSRX_SEL __BIT(18)
sys/arch/riscv/starfive/jh71x0_usb.c
69
#define JH7100_USB7_SSTX_SEL __BIT(19)
sys/arch/riscv/starfive/jh71x0_usb.c
70
#define JH7100_USB7_PLL_EN __BIT(23)
sys/arch/riscv/starfive/jh71x0_usb.c
71
#define JH7100_USB7_EQ_EN __BIT(25)
sys/arch/riscv/starfive/jh71x0_usb.c
73
#define JH7110_STRAP_HOST __BIT(17)
sys/arch/riscv/starfive/jh71x0_usb.c
74
#define JH7110_STRAP_DEVICE __BIT(18)
sys/arch/riscv/starfive/jh71x0_usb.c
77
#define JH7110_SUSPENDM_HOST __BIT(19)
sys/arch/riscv/starfive/jh71x0_usb.c
78
#define JH7110_SUSPENDM_MASK __BIT(19)
sys/arch/riscv/starfive/jh71x0_usb.c
81
#define JH7110_SUSPENDM_BYPS __BIT(20)
sys/arch/riscv/starfive/jh71x0_usb.c
82
#define JH7110_PLL_EN __BIT(22)
sys/arch/riscv/starfive/jh71x0_usb.c
83
#define JH7110_REFCLK_MODE __BIT(23)
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
234
__BIT(31), /* enable */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
235
__BIT(28), /* lock */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
243
__BIT(1), /* m */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
244
__BIT(0), /* p */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
245
__BIT(31), /* enable */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
246
__BIT(28), /* lock */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
254
__BIT(1), /* m */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
256
__BIT(31), /* enable */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
257
__BIT(28), /* lock */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
265
__BIT(1), /* m */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
267
__BIT(31), /* enable */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
268
__BIT(28), /* lock */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
278
__BIT(1), /* m */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
280
__BIT(31), /* enable */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
281
__BIT(28), /* lock */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
316
__BIT(31), /* enable */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
324
__BIT(31), /* enable */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
331
__BIT(31), /* enable */
sys/arch/riscv/sunxi/sun20i_d1_ccu.c
338
__BIT(31), /* enable */
sys/arch/sandpoint/sandpoint/com_eumb.c
109
#define COM_EUMB_FLAG_BROKEN_ETXRDY __BIT(0)
sys/arch/shark/ofw/vlpci.h
105
#define VLPCI_PCI_ARB_FAIR __BIT(7)
sys/arch/shark/ofw/vlpci.h
106
#define VLPCI_PCI_ARB_FRAME __BIT(6)
sys/arch/shark/ofw/vlpci.h
131
#define VLPCI_CFG_MISC_CTL_PCI_CFG_MECHN_2 __BIT(7)
sys/arch/shark/ofw/vlpci.h
137
#define VLPCI_CFG_MISC_CTL_TST_MODE __BIT(4)
sys/arch/shark/ofw/vlpci.h
138
#define VLPCI_CFG_MISC_CTL_SERR_NMI __BIT(3)
sys/arch/shark/ofw/vlpci.h
139
#define VLPCI_CFG_MISC_CTL_SERR_STS __BIT(2)
sys/arch/shark/ofw/vlpci.h
140
#define VLPCI_CFG_MISC_CTL_PCI_MST_BRK_TMR __BIT(1)
sys/arch/shark/ofw/vlpci.h
141
#define VLPCI_CFG_MISC_CTL_LREQI_LGNTO_PIN __BIT(0)
sys/arch/shark/ofw/vlpci.h
160
#define VLPCI_PCI_WND_ATTR_ENA __BIT(7) /* AN-025B */
sys/arch/shark/ofw/vlpci.h
161
#define VLPCI_PCI_WND_ATTR_PCI __BIT(7) /* DS */
sys/arch/shark/ofw/vlpci.h
162
#define VLPCI_PCI_WND_ATTR_WR_BUF __BIT(6)
sys/arch/shark/ofw/vlpci.h
163
#define VLPCI_PCI_WND_ATTR_IO __BIT(5) /* AN-025B */
sys/arch/shark/ofw/vlpci.h
164
#define VLPCI_PCI_WND_ATTR_VL __BIT(5) /* DS */
sys/arch/shark/ofw/vlpci.h
187
#define VLPCI_INT_CTL_ENA(int) __BIT((int) % 8 + 3)
sys/arch/shark/ofw/vlpci.h
210
#define VLPCI_ACC_ISA_CYC_A0000 __BIT(7)
sys/arch/shark/ofw/vlpci.h
211
#define VLPCI_ACC_ISA_CYC_B0000 __BIT(6)
sys/arch/shark/ofw/vlpci.h
212
#define VLPCI_ACC_ISA_CYC_C0000 __BIT(5)
sys/arch/shark/ofw/vlpci.h
213
#define VLPCI_ACC_ISA_CYC_C8000 __BIT(4)
sys/arch/shark/ofw/vlpci.h
214
#define VLPCI_ACC_ISA_CYC_D0000 __BIT(3)
sys/arch/shark/ofw/vlpci.h
215
#define VLPCI_ACC_ISA_CYC_D8000 __BIT(2)
sys/arch/shark/ofw/vlpci.h
216
#define VLPCI_ACC_ISA_CYC_E0000 __BIT(1)
sys/arch/shark/ofw/vlpci.h
217
#define VLPCI_ACC_ISA_CYC_E8000 __BIT(0)
sys/arch/shark/ofw/vlpci.h
221
#define VLPCI_MISC_CTL_HIADDR (__BITS(7, 6) | __BIT(4))
sys/arch/shark/ofw/vlpci.h
229
#define VLPCI_MISC_CTL_IOCHCK_PIN __BIT(5)
sys/arch/shark/ofw/vlpci.h
230
#define VLPCI_MISC_CTL_2ND_VL_IDE __BIT(3)
sys/arch/shark/ofw/vlpci.h
231
#define VLPCI_MISC_CTL_1ST_VL_IDE __BIT(2)
sys/arch/shark/ofw/vlpci.h
232
#define VLPCI_MISC_CTL_OBD_IO_ACC_ISA __BIT(0)
sys/arch/shark/ofw/vlpci.h
235
#define VLPCI_ACC_PCI_64K_WND_A0000 __BIT(7)
sys/arch/shark/ofw/vlpci.h
236
#define VLPCI_ACC_PCI_64K_WND_B0000 __BIT(6)
sys/arch/shark/ofw/vlpci.h
237
#define VLPCI_ACC_PCI_64K_WND_C0000 __BIT(5)
sys/arch/shark/ofw/vlpci.h
238
#define VLPCI_ACC_PCI_64K_WND_C8000 __BIT(4)
sys/arch/shark/ofw/vlpci.h
239
#define VLPCI_ACC_PCI_64K_WND_D0000 __BIT(3)
sys/arch/shark/ofw/vlpci.h
240
#define VLPCI_ACC_PCI_64K_WND_D8000 __BIT(2)
sys/arch/shark/ofw/vlpci.h
241
#define VLPCI_ACC_PCI_64K_WND_E0000 __BIT(1)
sys/arch/shark/ofw/vlpci.h
242
#define VLPCI_ACC_PCI_64K_WND_E8000 __BIT(0)
sys/arch/shark/ofw/vlpci.h
245
#define VLPCI_ACC_PCI_32K_WND_A0000 __BIT(7)
sys/arch/shark/ofw/vlpci.h
246
#define VLPCI_ACC_PCI_32K_WND_A8000 __BIT(6)
sys/arch/shark/ofw/vlpci.h
247
#define VLPCI_ACC_PCI_32K_WND_B0000 __BIT(5)
sys/arch/shark/ofw/vlpci.h
248
#define VLPCI_ACC_PCI_32K_WND_B8000 __BIT(4)
sys/arch/shark/ofw/vlpci.h
251
#define VLPCI_MISC_1_DYN_DEC_MEM_WR __BIT(7)
sys/arch/shark/ofw/vlpci.h
252
#define VLPCI_MISC_1_RTY_TMO_ACTION __BIT(6)
sys/arch/shark/ofw/vlpci.h
253
#define VLPCI_MISC_1_DYN_DEC_DIS __BIT(5)
sys/arch/shark/ofw/vlpci.h
254
#define VLPCI_MISC_1_LOCAL_PIN __BIT(4)
sys/arch/shark/ofw/vlpci.h
255
#define VLPCI_MISC_1_COMPAT_ISA_BOFF __BIT(3)
sys/arch/shark/ofw/vlpci.h
256
#define VLPCI_MISC_1_IRQ_IDLE_LOW __BIT(2)
sys/arch/shark/ofw/vlpci.h
257
#define VLPCI_MISC_1_PCI_MST_1WS_WR __BIT(1)
sys/arch/shark/ofw/vlpci.h
258
#define VLPCI_MISC_1_PCI_SLV_1WS_BST_WR __BIT(0)
sys/arch/shark/ofw/vlpci.h
272
#define VLPCI_MISC_2_BYTE_MRG __BIT(7)
sys/arch/shark/ofw/vlpci.h
273
#define VLPCI_MISC_2_ENH_BYTE_MRG __BIT(6)
sys/arch/shark/ofw/vlpci.h
274
#define VLPCI_MISC_2_DYN_PCI_BST __BIT(5)
sys/arch/shark/ofw/vlpci.h
275
#define VLPCI_MISC_2_RTY_FAIL_POP_1_DAT __BIT(4)
sys/arch/shark/ofw/vlpci.h
276
#define VLPCI_MISC_2_2WAY_DYN_DEC __BIT(3)
sys/arch/shark/ofw/vlpci.h
277
#define VLPCI_MISC_2_ISAREQ_1CLK_DLY __BIT(1)
sys/arch/shark/ofw/vlpci.h
278
#define VLPCI_MISC_2_ADS_1CLK_DLY __BIT(0)
sys/arch/shark/ofw/vlpci.h
57
#define VLPCI_DIP_SW_PCLK_CCLK __BIT(7)
sys/arch/shark/ofw/vlpci.h
58
#define VLPCI_DIP_SW_SYNC_CLK __BIT(6)
sys/arch/shark/ofw/vlpci.h
59
#define VLPCI_DIP_SW_IRQ14_15_PIN __BIT(5)
sys/arch/shark/ofw/vlpci.h
60
#define VLPCI_DIP_SW_BLAST_PIN __BIT(4)
sys/arch/shark/ofw/vlpci.h
70
#define VLPCI_BUF_CTL_CPU2PCI_WR_BUF __BIT(7)
sys/arch/shark/ofw/vlpci.h
71
#define VLPCI_BUF_CTL_PCI2CPU_WR_BUF __BIT(6)
sys/arch/shark/ofw/vlpci.h
72
#define VLPCI_BUF_CTL_CPU2PCI_PREF_BUF __BIT(5)
sys/arch/shark/ofw/vlpci.h
73
#define VLPCI_BUF_CTL_PCI2CPU_PREF_BUF __BIT(4)
sys/arch/shark/ofw/vlpci.h
74
#define VLPCI_BUF_CTL_PCI_DYN_ACC_DEC __BIT(3)
sys/arch/shark/ofw/vlpci.h
75
#define VLPCI_BUF_CTL_BST_B4_LST_BRDY __BIT(2)
sys/arch/shark/ofw/vlpci.h
76
#define VLPCI_BUF_CTL_OBD_MEM_WR_BST __BIT(1)
sys/arch/shark/ofw/vlpci.h
77
#define VLPCI_BUF_CTL_OBD_MEM_RD_BST __BIT(0)
sys/arch/shark/ofw/vlpci.h
80
#define VLPCI_VL_TIM_CPU2VL_WR_0WS __BIT(7)
sys/arch/shark/ofw/vlpci.h
81
#define VLPCI_VL_TIM_LDEV_2ND_T2 __BIT(6)
sys/arch/shark/ofw/vlpci.h
82
#define VLPCI_VL_TIM_TRDY2LRDY_BYP __BIT(5) /* AN-025B */
sys/arch/shark/ofw/vlpci.h
83
#define VLPCI_VL_TIM_TRDY2LRDY_RESYNC __BIT(5) /* DS */
sys/arch/shark/ofw/vlpci.h
84
#define VLPCI_VL_TIM_RDYRTN2TRDY_BYP __BIT(4) /* AN-025B */
sys/arch/shark/ofw/vlpci.h
85
#define VLPCI_VL_TIM_RDYRTN2TRDY_RESYNC __BIT(4) /* DS */
sys/arch/shark/ofw/vlpci.h
86
#define VLPCI_VL_TIM_OBD_MEM_1ST_DAT __BIT(3)
sys/arch/shark/ofw/vlpci.h
87
#define VLPCI_VL_TIM_CPU2PCI_WR_BST __BIT(2)
sys/arch/shark/ofw/vlpci.h
88
#define VLPCI_VL_TIM_PADS_DIS __BIT(1)
sys/arch/shark/ofw/vlpci.h
89
#define VLPCI_VL_TIM_TST_MODE __BIT(0)
sys/arch/shark/ofw/vlpci.h
92
#define VLPCI_PCI_TIM_SLV_LOCK __BIT(7)
sys/arch/shark/ofw/vlpci.h
93
#define VLPCI_PCI_TIM_RTY_CNT_64 __BIT(6)
sys/arch/shark/ofw/vlpci.h
94
#define VLPCI_PCI_TIM_RTY_DEADL_ERR_REP __BIT(5)
sys/arch/shark/ofw/vlpci.h
95
#define VLPCI_PCI_TIM_RTY_STS_OCCU __BIT(4)
sys/arch/shark/ofw/vlpci.h
96
#define VLPCI_PCI_TIM_CPU2PCI_FAST_B2B __BIT(3)
sys/arch/shark/ofw/vlpci.h
97
#define VLPCI_PCI_TIM_FAST_FRAME __BIT(2)
sys/arch/sparc64/dev/schizo.c
329
ino_bitmap = __BIT(SCZ_PCIERR_A_INO);
sys/arch/sparc64/dev/schizo.c
331
ino_bitmap = __BIT(SCZ_PCIERR_B_INO);
sys/arch/sparc64/dev/schizo.c
332
ino_bitmap |= __BIT(SCZ_UE_INO) | __BIT(SCZ_CE_INO) |
sys/arch/sparc64/dev/schizo.c
333
__BIT(SCZ_SERR_INO);
sys/arch/sparc64/dev/schizo.c
338
if (ino_bitmap & __BIT(SCZ_PCIERR_A_INO))
sys/arch/sparc64/dev/schizo.c
341
if (ino_bitmap & __BIT(SCZ_PCIERR_B_INO))
sys/arch/sparc64/dev/schizo.c
344
if (ino_bitmap & __BIT(SCZ_UE_INO))
sys/arch/sparc64/dev/schizo.c
347
if (ino_bitmap & __BIT(SCZ_CE_INO))
sys/arch/sparc64/dev/schizo.c
350
if (ino_bitmap & __BIT(SCZ_SERR_INO))
sys/arch/vax/vsa/tc_vsbus.c
104
#define KA46_BWF0_ADP __BIT(31)
sys/arch/vax/vsa/tc_vsbus.c
111
#define KA49_CFG_BA __BIT(0)
sys/arch/vax/vsa/tc_vsbus.c
125
#define KA4x_TCA_CSR_SPARE __BIT(3) /* 0x00008 RW */
sys/arch/vax/vsa/tc_vsbus.c
127
#define KA4x_TCA_CSR_RST_TC __BIT(8) /* 0x00100 RW */
sys/arch/vax/vsa/tc_vsbus.c
128
#define KA4x_TCA_CSR_EN_MAP __BIT(9) /* 0x00200 RW */
sys/arch/vax/vsa/tc_vsbus.c
129
#define KA4x_TCA_CSR_INVAL_REF __BIT(10) /* 0x00400 RW1C */
sys/arch/vax/vsa/tc_vsbus.c
130
#define KA4x_TCA_CSR_TC_TMO __BIT(11) /* 0x00800 RW */
sys/arch/vax/vsa/tc_vsbus.c
131
#define KA4x_TCA_CSR_EN_TC_IRQ __BIT(12) /* 0x01000 RW */
sys/arch/vax/vsa/tc_vsbus.c
132
#define KA4x_TCA_CSR_TC_IRQ __BIT(13) /* 0x02000 R */
sys/arch/vax/vsa/tc_vsbus.c
133
#define KA4x_TCA_CSR_ERR __BIT(14) /* 0x04000 RW1C */
sys/arch/vax/vsa/tc_vsbus.c
134
#define KA4x_TCA_CSR_ALT_CYC_ST __BIT(15) /* 0x08000 RW */
sys/arch/vax/vsa/tc_vsbus.c
135
#define KA4x_TCA_CSR_EN_PAR __BIT(16) /* 0x10000 RW */
sys/arch/vax/vsa/tc_vsbus.c
136
#define KA4x_TCA_CSR_FIFO_EMPTY __BIT(17) /* 0x20000 R */
sys/arch/virt68k/include/intr.h
159
#define INTR_F_MPSAFE __BIT(0)
sys/arch/x86/acpi/acpi_cpu_md.c
58
#define MSR_MISC_ENABLE_EST __BIT(16)
sys/arch/x86/acpi/acpi_cpu_md.c
59
#define MSR_MISC_ENABLE_TURBO __BIT(38)
sys/arch/x86/acpi/acpi_cpu_md.c
66
#define MSR_CMPHALT_SMI __BIT(27)
sys/arch/x86/acpi/acpi_cpu_md.c
67
#define MSR_CMPHALT_C1E __BIT(28)
sys/arch/x86/acpi/acpi_cpu_md.c
68
#define MSR_CMPHALT_BMSTS __BIT(29)
sys/arch/x86/acpi/acpi_cpu_md.c
831
irt = 10 * __BIT(irt);
sys/arch/x86/include/bootinfo.h
235
#define BI_EFI_32BIT __BIT(0) /* 32bit UEFI */
sys/arch/x86/include/dbregs.h
41
#define X86_DR6_DR0_BREAKPOINT_CONDITION_DETECTED __BIT(0)
sys/arch/x86/include/dbregs.h
42
#define X86_DR6_DR1_BREAKPOINT_CONDITION_DETECTED __BIT(1)
sys/arch/x86/include/dbregs.h
43
#define X86_DR6_DR2_BREAKPOINT_CONDITION_DETECTED __BIT(2)
sys/arch/x86/include/dbregs.h
44
#define X86_DR6_DR3_BREAKPOINT_CONDITION_DETECTED __BIT(3)
sys/arch/x86/include/dbregs.h
45
#define X86_DR6_DEBUG_REGISTER_ACCESS_DETECTED __BIT(13)
sys/arch/x86/include/dbregs.h
46
#define X86_DR6_SINGLE_STEP __BIT(14)
sys/arch/x86/include/dbregs.h
47
#define X86_DR6_TASK_SWITCH __BIT(15)
sys/arch/x86/include/dbregs.h
59
#define X86_DR7_LOCAL_DR0_BREAKPOINT __BIT(0)
sys/arch/x86/include/dbregs.h
60
#define X86_DR7_GLOBAL_DR0_BREAKPOINT __BIT(1)
sys/arch/x86/include/dbregs.h
61
#define X86_DR7_LOCAL_DR1_BREAKPOINT __BIT(2)
sys/arch/x86/include/dbregs.h
62
#define X86_DR7_GLOBAL_DR1_BREAKPOINT __BIT(3)
sys/arch/x86/include/dbregs.h
63
#define X86_DR7_LOCAL_DR2_BREAKPOINT __BIT(4)
sys/arch/x86/include/dbregs.h
64
#define X86_DR7_GLOBAL_DR2_BREAKPOINT __BIT(5)
sys/arch/x86/include/dbregs.h
65
#define X86_DR7_LOCAL_DR3_BREAKPOINT __BIT(6)
sys/arch/x86/include/dbregs.h
66
#define X86_DR7_GLOBAL_DR3_BREAKPOINT __BIT(7)
sys/arch/x86/include/dbregs.h
67
#define X86_DR7_LOCAL_EXACT_BREAKPOINT __BIT(8)
sys/arch/x86/include/dbregs.h
68
#define X86_DR7_GLOBAL_EXACT_BREAKPOINT __BIT(9)
sys/arch/x86/include/dbregs.h
69
#define X86_DR7_RESTRICTED_TRANSACTIONAL_MEMORY __BIT(11)
sys/arch/x86/include/dbregs.h
70
#define X86_DR7_GENERAL_DETECT_ENABLE __BIT(13)
sys/arch/x86/include/i82489reg.h
100
#define LAPIC_TRIGMODE_MASK __BIT(15)
sys/arch/x86/include/i82489reg.h
105
#define LAPIC_LVT_MASKED __BIT(16)
sys/arch/x86/include/i82489reg.h
110
# define LAPIC_DSTMODE_MASK __BIT(11)
sys/arch/x86/include/i82489reg.h
131
# define LAPIC_LVT_LINT_INP_POL __BIT(13)
sys/arch/x86/include/i82489reg.h
132
# define LAPIC_LVT_LINT_RIRR __BIT(14)
sys/arch/x86/include/i82489reg.h
155
#define LAPIC_MSIADDR_RH __BIT(3)
sys/arch/x86/include/i82489reg.h
156
#define LAPIC_MSIADDR_DM __BIT(2)
sys/arch/x86/include/i82489reg.h
166
# define LEAPIC_FR_EIDCAP __BIT(2) /* Ext. Apic ID Cap. RO */
sys/arch/x86/include/i82489reg.h
167
# define LEAPIC_FR_SEIOCAP __BIT(1) /* Specific EOI Cap. RO */
sys/arch/x86/include/i82489reg.h
168
# define LEAPIC_FR_IERCAP __BIT(0) /* Intr. Enable Reg. RO */
sys/arch/x86/include/i82489reg.h
171
# define LEAPIC_CR_EID_ENABLE __BIT(2) /* Ext. Apic ID enable */
sys/arch/x86/include/i82489reg.h
172
# define LEAPIC_CR_SEOI_ENABLE __BIT(1) /* Specific EOI enable */
sys/arch/x86/include/i82489reg.h
173
# define LEAPIC_CR_IER_ENABLE __BIT(0) /* Enable writes to IER */
sys/arch/x86/include/i82489reg.h
200
# define LEAPIC_LVTR_MASK __BIT(16) /* interrupt masked RW */
sys/arch/x86/include/i82489reg.h
201
# define LEAPIC_LVTR_DSTAT __BIT(12) /* delivery state RO */
sys/arch/x86/include/i82489reg.h
93
#define LAPIC_DLSTAT_BUSY __BIT(12) /* NA in x2APIC nor MSI */
sys/arch/x86/include/i82489reg.h
96
#define LAPIC_LEVEL_MASK __BIT(14) /* LAPIC_LVT_LINT_RIRR in LVT LINT */
sys/arch/x86/include/specialreg.h
1000
#define CPUID_CAPEX_IBPB_RET __BIT(30) /* Clear RET address predictor */
sys/arch/x86/include/specialreg.h
1027
#define CPUID_AMD_SVM_NP __BIT(0) /* Nested Paging */
sys/arch/x86/include/specialreg.h
1028
#define CPUID_AMD_SVM_LbrVirt __BIT(1) /* LBR virtualization */
sys/arch/x86/include/specialreg.h
1029
#define CPUID_AMD_SVM_SVML __BIT(2) /* SVM Lock */
sys/arch/x86/include/specialreg.h
1030
#define CPUID_AMD_SVM_NRIPS __BIT(3) /* NRIP Save on #VMEXIT */
sys/arch/x86/include/specialreg.h
1031
#define CPUID_AMD_SVM_TSCRateCtrl __BIT(4) /* MSR-based TSC rate ctrl */
sys/arch/x86/include/specialreg.h
1032
#define CPUID_AMD_SVM_VMCBCleanBits __BIT(5) /* VMCB Clean Bits support */
sys/arch/x86/include/specialreg.h
1033
#define CPUID_AMD_SVM_FlushByASID __BIT(6) /* Flush by ASID */
sys/arch/x86/include/specialreg.h
1034
#define CPUID_AMD_SVM_DecodeAssist __BIT(7) /* Decode Assists support */
sys/arch/x86/include/specialreg.h
1035
#define CPUID_AMD_SVM_PmcVirt __BIT(8) /* PMC Virtualization */
sys/arch/x86/include/specialreg.h
1036
#define CPUID_AMD_SVM_PauseFilter __BIT(10) /* PAUSE intercept filter */
sys/arch/x86/include/specialreg.h
1037
#define CPUID_AMD_SVM_PFThreshold __BIT(12) /* PAUSE filter threshold */
sys/arch/x86/include/specialreg.h
1038
#define CPUID_AMD_SVM_AVIC __BIT(13) /* Advanced Virt. Intr. Ctrl */
sys/arch/x86/include/specialreg.h
1039
#define CPUID_AMD_SVM_V_VMSAVE_VMLOAD __BIT(15) /* Virtual VM{SAVE/LOAD} */
sys/arch/x86/include/specialreg.h
1040
#define CPUID_AMD_SVM_vGIF __BIT(16) /* Virtualized GIF */
sys/arch/x86/include/specialreg.h
1041
#define CPUID_AMD_SVM_GMET __BIT(17) /* Guest Mode Execution Trap */
sys/arch/x86/include/specialreg.h
1042
#define CPUID_AMD_SVM_X2AVIC __BIT(18) /* Virt. Intr. Ctrl 4 x2APIC */
sys/arch/x86/include/specialreg.h
1043
#define CPUID_AMD_SVM_SSSCHECK __BIT(19) /* Shadow Stack restrictions */
sys/arch/x86/include/specialreg.h
1044
#define CPUID_AMD_SVM_SPEC_CTRL __BIT(20) /* SPEC_CTRL virtualization */
sys/arch/x86/include/specialreg.h
1045
#define CPUID_AMD_SVM_ROGPT __BIT(21) /* Read-Only Guest PTable */
sys/arch/x86/include/specialreg.h
1046
#define CPUID_AMD_SVM_HOST_MCE_OVERRIDE __BIT(23) /* #MC intercept */
sys/arch/x86/include/specialreg.h
1047
#define CPUID_AMD_SVM_TLBICTL __BIT(24) /* TLB Intercept Control */
sys/arch/x86/include/specialreg.h
1048
#define CPUID_AMD_SVM_VNMI __BIT(25) /* NMI Virtualization */
sys/arch/x86/include/specialreg.h
1049
#define CPUID_AMD_SVM_IBSVIRT __BIT(26) /* IBS Virtualization */
sys/arch/x86/include/specialreg.h
1050
#define CPUID_AMD_SVM_XLVTOFFFLTCHG __BIT(27) /* Ext LVToffset FLT changed */
sys/arch/x86/include/specialreg.h
1051
#define CPUID_AMD_SVM_VMCBADRCHKCHG __BIT(28) /* VMCB addr check changed */
sys/arch/x86/include/specialreg.h
1052
#define CPUID_AMD_SVM_BUSLOCKTHRESH __BIT(29) /* Bus Lock Threshold */
sys/arch/x86/include/specialreg.h
1053
#define CPUID_AMD_SVM_IDLEHLTINTERCEPT __BIT(30) /* Idle HLT Intercept */
sys/arch/x86/include/specialreg.h
1054
#define CPUID_AMD_SVM_ESHUTDOWN __BIT(31) /* Enhanced Shutdown Intr. */
sys/arch/x86/include/specialreg.h
1074
#define CPUID_IBS_FFV __BIT(0) /* Feature Flags Valid */
sys/arch/x86/include/specialreg.h
1075
#define CPUID_IBS_FETCHSUM __BIT(1) /* Fetch Sampling */
sys/arch/x86/include/specialreg.h
1076
#define CPUID_IBS_OPSAM __BIT(2) /* execution SAMpling */
sys/arch/x86/include/specialreg.h
1077
#define CPUID_IBS_RDWROPCNT __BIT(3) /* Read Write of Op Counter */
sys/arch/x86/include/specialreg.h
1078
#define CPUID_IBS_OPCNT __BIT(4) /* OP CouNTing mode */
sys/arch/x86/include/specialreg.h
1079
#define CPUID_IBS_BRNTRGT __BIT(5) /* Branch Target */
sys/arch/x86/include/specialreg.h
1080
#define CPUID_IBS_OPCNTEXT __BIT(6) /* OpCurCnt and OpMaxCnt extended */
sys/arch/x86/include/specialreg.h
1081
#define CPUID_IBS_RIPINVALIDCHK __BIT(7) /* Invalid RIP indication */
sys/arch/x86/include/specialreg.h
1082
#define CPUID_IBS_OPBRNFUSE __BIT(8) /* Fused branch micro-op indicate */
sys/arch/x86/include/specialreg.h
1083
#define CPUID_IBS_FETCHCTLEXTD __BIT(9) /* IC_IBS_EXTD_CTL MSR */
sys/arch/x86/include/specialreg.h
1084
#define CPUID_IBS_OPDATA4 __BIT(10) /* IBS op data 4 MSR */
sys/arch/x86/include/specialreg.h
1085
#define CPUID_IBS_ZEN4E __BIT(11) /* Zen4 IBS Extensions */
sys/arch/x86/include/specialreg.h
1086
#define CPUID_IBS_LOADLATFILT __BIT(12) /* Load Latency Filtering */
sys/arch/x86/include/specialreg.h
1087
#define CPUID_IBS_UPDDTLBSTAT __BIT(19) /* Updated DTLB stats */
sys/arch/x86/include/specialreg.h
1132
#define CPUID_AMD_ENCMEM_SME __BIT(0) /* Secure Memory Encryption */
sys/arch/x86/include/specialreg.h
1133
#define CPUID_AMD_ENCMEM_SEV __BIT(1) /* Secure Encrypted Virtualiz. */
sys/arch/x86/include/specialreg.h
1134
#define CPUID_AMD_ENCMEM_PGFLMSR __BIT(2) /* Page Flush MSR */
sys/arch/x86/include/specialreg.h
1135
#define CPUID_AMD_ENCMEM_SEVES __BIT(3) /* SEV Encrypted State */
sys/arch/x86/include/specialreg.h
1136
#define CPUID_AMD_ENCMEM_SEV_SNP __BIT(4) /* Secure Nested Paging */
sys/arch/x86/include/specialreg.h
1137
#define CPUID_AMD_ENCMEM_VMPL __BIT(5) /* Virtual Machine Privilege Lvl */
sys/arch/x86/include/specialreg.h
1138
#define CPUID_AMD_ENCMEM_RMPQUERY __BIT(6) /* RMPQUERY instruction */
sys/arch/x86/include/specialreg.h
1139
#define CPUID_AMD_ENCMEM_VMPLSSS __BIT(7) /* VMPL Secure Shadow Stack */
sys/arch/x86/include/specialreg.h
1140
#define CPUID_AMD_ENCMEM_SECTSC __BIT(8) /* Secure TSC */
sys/arch/x86/include/specialreg.h
1141
#define CPUID_AMD_ENCMEM_TSCAUX_V __BIT(9) /* TSC AUX Virtualization */
sys/arch/x86/include/specialreg.h
1142
#define CPUID_AMD_ENCMEM_HECC __BIT(10) /* HW Enf Cache Coh across enc dom */
sys/arch/x86/include/specialreg.h
1143
#define CPUID_AMD_ENCMEM_64BH __BIT(11) /* 64Bit Host */
sys/arch/x86/include/specialreg.h
1144
#define CPUID_AMD_ENCMEM_RSTRINJ __BIT(12) /* Restricted Injection */
sys/arch/x86/include/specialreg.h
1145
#define CPUID_AMD_ENCMEM_ALTINJ __BIT(13) /* Alternate Injection */
sys/arch/x86/include/specialreg.h
1146
#define CPUID_AMD_ENCMEM_DBGSWAP __BIT(14) /* Debug Swap */
sys/arch/x86/include/specialreg.h
1147
#define CPUID_AMD_ENCMEM_PREVHOSTIBS __BIT(15) /* Prevent Host IBS */
sys/arch/x86/include/specialreg.h
1148
#define CPUID_AMD_ENCMEM_VTE __BIT(16) /* Virtual Transparent Encryption */
sys/arch/x86/include/specialreg.h
1149
#define CPUID_AMD_ENCMEM_VMGEXITP __BIT(17) /* VMGEXIT Parameter */
sys/arch/x86/include/specialreg.h
1150
#define CPUID_AMD_ENCMEM_VIRTTOM __BIT(18) /* Virtual TOM MSR */
sys/arch/x86/include/specialreg.h
1151
#define CPUID_AMD_ENCMEM_IBSVGUEST __BIT(19) /* IBS Virt. for SEV-ES guest */
sys/arch/x86/include/specialreg.h
1152
#define CPUID_AMD_ENCMEM_PMCVGUEST __BIT(20) /* PMC Virt. for SEV-ES guest */
sys/arch/x86/include/specialreg.h
1153
#define CPUID_AMD_ENCMEM_RMPREAD __BIT(21) /* RMPREAD instruction */
sys/arch/x86/include/specialreg.h
1154
#define CPUID_AMD_ENCMEM_GUESTINTERCEPT __BIT(22) /* Guest Intercept 4SEV-ES */
sys/arch/x86/include/specialreg.h
1155
#define CPUID_AMD_ENCMEM_SEGRMP __BIT(23) /* Segmented RMP */
sys/arch/x86/include/specialreg.h
1156
#define CPUID_AMD_ENCMEM_VMSA_REGPROT __BIT(24) /* VmsaRegProt */
sys/arch/x86/include/specialreg.h
1157
#define CPUID_AMD_ENCMEM_SMTPROTECT __BIT(25) /* SMT Protection */
sys/arch/x86/include/specialreg.h
1158
#define CPUID_AMD_ENCMEM_SECAVIC __BIT(26) /* Secure AVIC */
sys/arch/x86/include/specialreg.h
1159
#define CPUID_AMD_ENCMEM_ALLOWSEV __BIT(27) /* Allowed SEV */
sys/arch/x86/include/specialreg.h
1160
#define CPUID_AMD_ENCMEM_SVSM_COMMPAGE __BIT(28) /* SVSM Communication Page */
sys/arch/x86/include/specialreg.h
1161
#define CPUID_AMD_ENCMEM_NESTED_VSMP __BIT(29) /* VIRT_{RMPUPDATE,PSMASH} */
sys/arch/x86/include/specialreg.h
1162
#define CPUID_AMD_ENCMEM_HVINUSEWR __BIT(30) /* HV In Use Write Allow */
sys/arch/x86/include/specialreg.h
1163
#define CPUID_AMD_ENCMEM_IBPBONENTRY __BIT(31) /* IBPB on Entry */
sys/arch/x86/include/specialreg.h
1183
#define CPUID_AMDEXT2_NONESTEDDBP __BIT(0) /* No nested data breakpoints */
sys/arch/x86/include/specialreg.h
1184
#define CPUID_AMDEXT2_FGKBNOSERIAL __BIT(1) /* {FS,GS,K}BASE WRMSR !serializ */
sys/arch/x86/include/specialreg.h
1185
#define CPUID_AMDEXT2_LFENCESERIAL __BIT(2) /* LFENCE always serializing */
sys/arch/x86/include/specialreg.h
1186
#define CPUID_AMDEXT2_SMMPGCFGLCK __BIT(3) /* SMM Paging configuration lock */
sys/arch/x86/include/specialreg.h
1187
#define CPUID_AMDEXT2_NULLSELCLRB __BIT(6) /* Null segment selector clr base */
sys/arch/x86/include/specialreg.h
1188
#define CPUID_AMDEXT2_UPADDRIGN __BIT(7) /* Upper Address Ignore */
sys/arch/x86/include/specialreg.h
1189
#define CPUID_AMDEXT2_AUTOIBRS __BIT(8) /* Automatic IBRS */
sys/arch/x86/include/specialreg.h
1190
#define CPUID_AMDEXT2_NOSMMCTL __BIT(9) /* SMM_CTL MSR is not supported */
sys/arch/x86/include/specialreg.h
1191
#define CPUID_AMDEXT2_FSRS __BIT(10) /* Fast Short Rep Stosb */
sys/arch/x86/include/specialreg.h
1192
#define CPUID_AMDEXT2_FSRC __BIT(11) /* Fast Short Rep Cmpsb */
sys/arch/x86/include/specialreg.h
1193
#define CPUID_AMDEXT2_PMCPRECISERETIRE __BIT(12) /* PMC Presize Retire */
sys/arch/x86/include/specialreg.h
1194
#define CPUID_AMDEXT2_PREFETCHCTL __BIT(13) /* Prefetch control MSR */
sys/arch/x86/include/specialreg.h
1195
#define CPUID_AMDEXT2_L2TLBSIZEX32 __BIT(14) /* L2TLB size encoded as x32 */
sys/arch/x86/include/specialreg.h
1196
#define CPUID_AMDEXT2_ERMSB __BIT(15) /* AMD implementation of ERMSB */
sys/arch/x86/include/specialreg.h
1197
#define CPUID_AMDEXT2_OPF17RECLAIM __BIT(16) /* Reserve opcode 0f 01/7 */
sys/arch/x86/include/specialreg.h
1198
#define CPUID_AMDEXT2_CPUIDUSRDIS __BIT(17) /* CPUID dis. for non-priv. soft */
sys/arch/x86/include/specialreg.h
1199
#define CPUID_AMDEXT2_EPSF __BIT(18) /* Enhanced Predictive Store Fwd */
sys/arch/x86/include/specialreg.h
1200
#define CPUID_AMDEXT2_0F017_RECLAIM __BIT(19) /* Opecode 0f 01/7 reserved */
sys/arch/x86/include/specialreg.h
1201
#define CPUID_AMDEXT2_PREFETCHI __BIT(20) /* IC prefetch support */
sys/arch/x86/include/specialreg.h
1202
#define CPUID_AMDEXT2_FP512_DOWNGRADE __BIT(21) /* FP512 dpath down to 256 */
sys/arch/x86/include/specialreg.h
1203
#define CPUID_AMDEXT2_WL_CLASS __BIT(22) /* wkld based heuristic feedback */
sys/arch/x86/include/specialreg.h
1204
#define CPUID_AMDEXT2_ERAPS __BIT(24) /* Enhn. Retn. Addr. Pred. Sec. */
sys/arch/x86/include/specialreg.h
1205
#define CPUID_AMDEXT2_SBPB __BIT(27) /* Selective Brnc. Pred. Barrier */
sys/arch/x86/include/specialreg.h
1206
#define CPUID_AMDEXT2_IBPB_BRTYPE __BIT(28) /* BRanch TYPE prediction flush */
sys/arch/x86/include/specialreg.h
1207
#define CPUID_AMDEXT2_SRSO_NO __BIT(29) /* Not vulnerable to SRSO */
sys/arch/x86/include/specialreg.h
1208
#define CPUID_AMDEXT2_SRSO_UK_NO __BIT(30) /* SRSO_NO at user-kern boundary */
sys/arch/x86/include/specialreg.h
1209
#define CPUID_AMDEXT2_SRSO_MSR_FIX __BIT(31) /* SRSO mitig. bit in BP_CFG[4] */
sys/arch/x86/include/specialreg.h
1231
#define CPUID_AXPERF_PERFMONV2 __BIT(0) /* Version 2 */
sys/arch/x86/include/specialreg.h
1232
#define CPUID_AXPERF_LBRSTACK __BIT(1) /* Last Branch Record Stack */
sys/arch/x86/include/specialreg.h
1233
#define CPUID_AXPERF_LBRPMCFREEZE __BIT(2) /* Freezing LBR and PMC */
sys/arch/x86/include/specialreg.h
1257
#define CPUID_VIA_HAS_AIS __BIT(0) /* Alternate Instruction Set supported */
sys/arch/x86/include/specialreg.h
1259
#define CPUID_VIA_DO_AIS __BIT(1) /* Alternate Instruction Set enabled */
sys/arch/x86/include/specialreg.h
1261
#define CPUID_VIA_HAS_RNG __BIT(2) /* Random number generator */
sys/arch/x86/include/specialreg.h
1262
#define CPUID_VIA_DO_RNG __BIT(3)
sys/arch/x86/include/specialreg.h
1263
#define CPUID_VIA_HAS_ACE __BIT(6) /* AES Encryption */
sys/arch/x86/include/specialreg.h
1264
#define CPUID_VIA_DO_ACE __BIT(7)
sys/arch/x86/include/specialreg.h
1265
#define CPUID_VIA_HAS_ACE2 __BIT(8) /* AES+CTR instructions */
sys/arch/x86/include/specialreg.h
1266
#define CPUID_VIA_DO_ACE2 __BIT(9)
sys/arch/x86/include/specialreg.h
1267
#define CPUID_VIA_HAS_PHE __BIT(10) /* SHA1+SHA256 HMAC */
sys/arch/x86/include/specialreg.h
1268
#define CPUID_VIA_DO_PHE __BIT(11)
sys/arch/x86/include/specialreg.h
1269
#define CPUID_VIA_HAS_PMM __BIT(12) /* RSA Instructions */
sys/arch/x86/include/specialreg.h
1270
#define CPUID_VIA_DO_PMM __BIT(13)
sys/arch/x86/include/specialreg.h
1322
#define IA32_TSX_CTRL_RTM_DISABLE __BIT(0)
sys/arch/x86/include/specialreg.h
1323
#define IA32_TSX_CTRL_TSX_CPUID_CLEAR __BIT(1)
sys/arch/x86/include/specialreg.h
1339
#define IA32_MISC_FAST_STR_EN __BIT(0)
sys/arch/x86/include/specialreg.h
1340
#define IA32_MISC_ATCC_EN __BIT(3)
sys/arch/x86/include/specialreg.h
1341
#define IA32_MISC_PERFMON_EN __BIT(7)
sys/arch/x86/include/specialreg.h
1342
#define IA32_MISC_BTS_UNAVAIL __BIT(11)
sys/arch/x86/include/specialreg.h
1343
#define IA32_MISC_PEBS_UNAVAIL __BIT(12)
sys/arch/x86/include/specialreg.h
1344
#define IA32_MISC_EISST_EN __BIT(16)
sys/arch/x86/include/specialreg.h
1345
#define IA32_MISC_MWAIT_EN __BIT(18)
sys/arch/x86/include/specialreg.h
1346
#define IA32_MISC_LIMIT_CPUID __BIT(22)
sys/arch/x86/include/specialreg.h
1347
#define IA32_MISC_XTPR_DIS __BIT(23)
sys/arch/x86/include/specialreg.h
1348
#define IA32_MISC_XD_DIS __BIT(34)
sys/arch/x86/include/specialreg.h
143
#define XCR0_X87 __BIT(0) /* x87 FPU/MMX state */
sys/arch/x86/include/specialreg.h
144
#define XCR0_SSE __BIT(1) /* SSE state */
sys/arch/x86/include/specialreg.h
145
#define XCR0_YMM_Hi128 __BIT(2) /* AVX-256 (ymmn registers) */
sys/arch/x86/include/specialreg.h
146
#define XCR0_BNDREGS __BIT(3) /* Memory protection ext bounds */
sys/arch/x86/include/specialreg.h
147
#define XCR0_BNDCSR __BIT(4) /* Memory protection ext state */
sys/arch/x86/include/specialreg.h
148
#define XCR0_Opmask __BIT(5) /* AVX-512 Opmask */
sys/arch/x86/include/specialreg.h
149
#define XCR0_ZMM_Hi256 __BIT(6) /* AVX-512 upper 256 bits low regs */
sys/arch/x86/include/specialreg.h
150
#define XCR0_Hi16_ZMM __BIT(7) /* AVX-512 512 bits upper registers */
sys/arch/x86/include/specialreg.h
151
#define XCR0_PT __BIT(8) /* Processor Trace state */
sys/arch/x86/include/specialreg.h
152
#define XCR0_PKRU __BIT(9) /* Protection Key state */
sys/arch/x86/include/specialreg.h
1520
#define CC6_CFG_DISABLE_BITS (__BIT(22) | __BIT(14) | __BIT(6))
sys/arch/x86/include/specialreg.h
1523
#define LS_CFG_ERRATA_1033 __BIT(4)
sys/arch/x86/include/specialreg.h
1524
#define LS_CFG_ERRATA_793 __BIT(15)
sys/arch/x86/include/specialreg.h
1525
#define LS_CFG_ERRATA_1095 __BIT(57)
sys/arch/x86/include/specialreg.h
153
#define XCR0_CET_U __BIT(11) /* User CET state */
sys/arch/x86/include/specialreg.h
1534
#define IC_CFG_ERRATA_776 __BIT(26)
sys/arch/x86/include/specialreg.h
154
#define XCR0_CET_S __BIT(12) /* Kern CET state */
sys/arch/x86/include/specialreg.h
155
#define XCR0_HDC __BIT(13) /* Hardware Duty Cycle state */
sys/arch/x86/include/specialreg.h
1550
#define FP_CFG_ERRATA_1049 __BIT(4)
sys/arch/x86/include/specialreg.h
1554
#define DE_CFG_LFENCE_SERIALIZE __BIT(1)
sys/arch/x86/include/specialreg.h
1555
#define DE_CFG_ERRATA_ZENBLEED __BIT(9)
sys/arch/x86/include/specialreg.h
1556
#define DE_CFG_ERRATA_1021 __BIT(13)
sys/arch/x86/include/specialreg.h
1559
#define BU_CFG2_CWPLUS_DIS __BIT(24)
sys/arch/x86/include/specialreg.h
156
#define XCR0_LBR __BIT(15) /* Last Branch Record */
sys/arch/x86/include/specialreg.h
1562
#define LS_CFG2_ERRATA_1091 __BIT(34)
sys/arch/x86/include/specialreg.h
157
#define XCR0_HWP __BIT(16) /* Hardware P-states */
sys/arch/x86/include/specialreg.h
158
#define XCR0_TILECFG __BIT(17) /* Intel AMX TILECFG state in XSAVE */
sys/arch/x86/include/specialreg.h
159
#define XCR0_TILEDATA __BIT(18) /* Intel AMX TILEDATA state in XSAVE */
sys/arch/x86/include/specialreg.h
160
#define XCR0_LWP __BIT(62) /* AMD Lightweight Profiling (LWP) */
sys/arch/x86/include/specialreg.h
161
#define XCR0_X __BIT(63) /* AMD: reserved for XCR0 expansion */
sys/arch/x86/include/specialreg.h
333
#define CPUID2_SSE3 __BIT(0) /* Streaming SIMD Extensions 3 */
sys/arch/x86/include/specialreg.h
334
#define CPUID2_PCLMULQDQ __BIT(1) /* PCLMULQDQ instructions */
sys/arch/x86/include/specialreg.h
335
#define CPUID2_DTES64 __BIT(2) /* 64-bit Debug Trace */
sys/arch/x86/include/specialreg.h
336
#define CPUID2_MONITOR __BIT(3) /* MONITOR/MWAIT instructions */
sys/arch/x86/include/specialreg.h
337
#define CPUID2_DS_CPL __BIT(4) /* CPL Qualified Debug Store */
sys/arch/x86/include/specialreg.h
338
#define CPUID2_VMX __BIT(5) /* Virtual Machine eXtensions */
sys/arch/x86/include/specialreg.h
339
#define CPUID2_SMX __BIT(6) /* Safer Mode eXtensions */
sys/arch/x86/include/specialreg.h
340
#define CPUID2_EST __BIT(7) /* Enhanced SpeedStep Technology */
sys/arch/x86/include/specialreg.h
341
#define CPUID2_TM2 __BIT(8) /* Thermal Monitor 2 */
sys/arch/x86/include/specialreg.h
342
#define CPUID2_SSSE3 __BIT(9) /* Supplemental SSE3 */
sys/arch/x86/include/specialreg.h
343
#define CPUID2_CNXTID __BIT(10) /* Context ID */
sys/arch/x86/include/specialreg.h
344
#define CPUID2_SDBG __BIT(11) /* Silicon Debug */
sys/arch/x86/include/specialreg.h
345
#define CPUID2_FMA __BIT(12) /* Fused Multiply Add */
sys/arch/x86/include/specialreg.h
346
#define CPUID2_CX16 __BIT(13) /* CMPXCHG16B instruction */
sys/arch/x86/include/specialreg.h
347
#define CPUID2_XTPR __BIT(14) /* Task Priority Messages disabled? */
sys/arch/x86/include/specialreg.h
348
#define CPUID2_PDCM __BIT(15) /* Perf/Debug Capability MSR */
sys/arch/x86/include/specialreg.h
350
#define CPUID2_PCID __BIT(17) /* Process Context ID */
sys/arch/x86/include/specialreg.h
351
#define CPUID2_DCA __BIT(18) /* Direct Cache Access */
sys/arch/x86/include/specialreg.h
352
#define CPUID2_SSE41 __BIT(19) /* Streaming SIMD Extensions 4.1 */
sys/arch/x86/include/specialreg.h
353
#define CPUID2_SSE42 __BIT(20) /* Streaming SIMD Extensions 4.2 */
sys/arch/x86/include/specialreg.h
354
#define CPUID2_X2APIC __BIT(21) /* xAPIC Extensions */
sys/arch/x86/include/specialreg.h
355
#define CPUID2_MOVBE __BIT(22) /* MOVBE (move after byteswap) */
sys/arch/x86/include/specialreg.h
356
#define CPUID2_POPCNT __BIT(23) /* POPCNT instruction available */
sys/arch/x86/include/specialreg.h
357
#define CPUID2_DEADLINE __BIT(24) /* APIC Timer supports TSC Deadline */
sys/arch/x86/include/specialreg.h
358
#define CPUID2_AESNI __BIT(25) /* AES instructions */
sys/arch/x86/include/specialreg.h
359
#define CPUID2_XSAVE __BIT(26) /* XSAVE instructions */
sys/arch/x86/include/specialreg.h
360
#define CPUID2_OSXSAVE __BIT(27) /* XGETBV/XSETBV instructions */
sys/arch/x86/include/specialreg.h
361
#define CPUID2_AVX __BIT(28) /* AVX instructions */
sys/arch/x86/include/specialreg.h
362
#define CPUID2_F16C __BIT(29) /* half precision conversion */
sys/arch/x86/include/specialreg.h
363
#define CPUID2_RDRAND __BIT(30) /* RDRAND (hardware random number) */
sys/arch/x86/include/specialreg.h
364
#define CPUID2_RAZ __BIT(31) /* RAZ. Indicates guest state. */
sys/arch/x86/include/specialreg.h
418
#define CPUID_DCP_SELFINITCL __BIT(8) /* Self initializing cachelvl*/
sys/arch/x86/include/specialreg.h
419
#define CPUID_DCP_FULLASSOC __BIT(9) /* Full associative */
sys/arch/x86/include/specialreg.h
431
#define CPUID_DCP_INVALIDATE __BIT(0) /* WB invalidate/invalidate */
sys/arch/x86/include/specialreg.h
432
#define CPUID_DCP_INCLUSIVE __BIT(1) /* Cache inclusiveness */
sys/arch/x86/include/specialreg.h
433
#define CPUID_DCP_COMPLEX __BIT(2) /* Complex cache indexing */
sys/arch/x86/include/specialreg.h
444
#define CPUID_MON_EMX __BIT(0) /* MONITOR/MWAIT Extensions */
sys/arch/x86/include/specialreg.h
445
#define CPUID_MON_IBE __BIT(1) /* Interrupt as Break Event */
sys/arch/x86/include/specialreg.h
458
#define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */
sys/arch/x86/include/specialreg.h
459
#define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */
sys/arch/x86/include/specialreg.h
460
#define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */
sys/arch/x86/include/specialreg.h
461
#define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */
sys/arch/x86/include/specialreg.h
462
#define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */
sys/arch/x86/include/specialreg.h
463
#define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */
sys/arch/x86/include/specialreg.h
464
#define CPUID_DSPM_HWP __BIT(7) /* HWP */
sys/arch/x86/include/specialreg.h
465
#define CPUID_DSPM_HWP_NOTIFY __BIT(8) /* HWP Notification */
sys/arch/x86/include/specialreg.h
466
#define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */
sys/arch/x86/include/specialreg.h
467
#define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */
sys/arch/x86/include/specialreg.h
468
#define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */
sys/arch/x86/include/specialreg.h
469
#define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */
sys/arch/x86/include/specialreg.h
470
#define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */
sys/arch/x86/include/specialreg.h
471
#define CPUID_DSPM_HWP_CAP __BIT(15) /* HWP Capabilities */
sys/arch/x86/include/specialreg.h
472
#define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */
sys/arch/x86/include/specialreg.h
473
#define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */
sys/arch/x86/include/specialreg.h
474
#define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */
sys/arch/x86/include/specialreg.h
475
#define CPUID_DSPM_HFI __BIT(19) /* Hardware Feedback Interface */
sys/arch/x86/include/specialreg.h
476
#define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */
sys/arch/x86/include/specialreg.h
477
#define CPUID_DSPM_TD __BIT(23) /* Thread Director */
sys/arch/x86/include/specialreg.h
478
#define CPUID_DSPM_THERMI_HFN __BIT(24) /* THERM_INTERRUPT MSR HFN bit */
sys/arch/x86/include/specialreg.h
490
#define CPUID_DSPM_HWF __BIT(0) /* MSR_APERF/MSR_MPERF available */
sys/arch/x86/include/specialreg.h
491
#define CPUID_DSPM_EPB __BIT(3) /* Energy Performance Bias */
sys/arch/x86/include/specialreg.h
512
#define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */
sys/arch/x86/include/specialreg.h
513
#define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */
sys/arch/x86/include/specialreg.h
514
#define CPUID_SEF_SGX __BIT(2) /* Software Guard Extensions */
sys/arch/x86/include/specialreg.h
515
#define CPUID_SEF_BMI1 __BIT(3) /* Advanced bit manipulation ext. 1st grp */
sys/arch/x86/include/specialreg.h
516
#define CPUID_SEF_HLE __BIT(4) /* Hardware Lock Elision */
sys/arch/x86/include/specialreg.h
517
#define CPUID_SEF_AVX2 __BIT(5) /* Advanced Vector Extensions 2 */
sys/arch/x86/include/specialreg.h
518
#define CPUID_SEF_FDPEXONLY __BIT(6) /* x87FPU Data ptr updated only on x87exp */
sys/arch/x86/include/specialreg.h
519
#define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Execution Prevention */
sys/arch/x86/include/specialreg.h
520
#define CPUID_SEF_BMI2 __BIT(8) /* Advanced bit manipulation ext. 2nd grp */
sys/arch/x86/include/specialreg.h
521
#define CPUID_SEF_ERMS __BIT(9) /* Enhanced REP MOVSB/STOSB */
sys/arch/x86/include/specialreg.h
522
#define CPUID_SEF_INVPCID __BIT(10) /* INVPCID instruction */
sys/arch/x86/include/specialreg.h
523
#define CPUID_SEF_RTM __BIT(11) /* Restricted Transactional Memory */
sys/arch/x86/include/specialreg.h
524
#define CPUID_SEF_QM __BIT(12) /* Resource Director Technology Monitoring */
sys/arch/x86/include/specialreg.h
525
#define CPUID_SEF_FPUCSDS __BIT(13) /* Deprecate FPU CS and FPU DS values */
sys/arch/x86/include/specialreg.h
526
#define CPUID_SEF_MPX __BIT(14) /* Memory Protection Extensions */
sys/arch/x86/include/specialreg.h
527
#define CPUID_SEF_PQE __BIT(15) /* Resource Director Technology Allocation */
sys/arch/x86/include/specialreg.h
528
#define CPUID_SEF_AVX512F __BIT(16) /* AVX-512 Foundation */
sys/arch/x86/include/specialreg.h
529
#define CPUID_SEF_AVX512DQ __BIT(17) /* AVX-512 Double/Quadword */
sys/arch/x86/include/specialreg.h
530
#define CPUID_SEF_RDSEED __BIT(18) /* RDSEED instruction */
sys/arch/x86/include/specialreg.h
531
#define CPUID_SEF_ADX __BIT(19) /* ADCX/ADOX instructions */
sys/arch/x86/include/specialreg.h
532
#define CPUID_SEF_SMAP __BIT(20) /* Supervisor-Mode Access Prevention */
sys/arch/x86/include/specialreg.h
533
#define CPUID_SEF_AVX512_IFMA __BIT(21) /* AVX-512 Integer Fused Multiply Add */
sys/arch/x86/include/specialreg.h
535
#define CPUID_SEF_CLFLUSHOPT __BIT(23) /* Cache Line FLUSH OPTimized */
sys/arch/x86/include/specialreg.h
536
#define CPUID_SEF_CLWB __BIT(24) /* Cache Line Write Back */
sys/arch/x86/include/specialreg.h
537
#define CPUID_SEF_PT __BIT(25) /* Processor Trace */
sys/arch/x86/include/specialreg.h
538
#define CPUID_SEF_AVX512PF __BIT(26) /* AVX-512 PreFetch */
sys/arch/x86/include/specialreg.h
539
#define CPUID_SEF_AVX512ER __BIT(27) /* AVX-512 Exponential and Reciprocal */
sys/arch/x86/include/specialreg.h
540
#define CPUID_SEF_AVX512CD __BIT(28) /* AVX-512 Conflict Detection */
sys/arch/x86/include/specialreg.h
541
#define CPUID_SEF_SHA __BIT(29) /* SHA Extensions */
sys/arch/x86/include/specialreg.h
542
#define CPUID_SEF_AVX512BW __BIT(30) /* AVX-512 Byte and Word */
sys/arch/x86/include/specialreg.h
543
#define CPUID_SEF_AVX512VL __BIT(31) /* AVX-512 Vector Length */
sys/arch/x86/include/specialreg.h
556
#define CPUID_SEF_PREFETCHWT1 __BIT(0) /* PREFETCHWT1 instruction */
sys/arch/x86/include/specialreg.h
557
#define CPUID_SEF_AVX512_VBMI __BIT(1) /* AVX-512 Vector Byte Manipulation */
sys/arch/x86/include/specialreg.h
558
#define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */
sys/arch/x86/include/specialreg.h
559
#define CPUID_SEF_PKU __BIT(3) /* Protection Keys for User-mode pages */
sys/arch/x86/include/specialreg.h
560
#define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */
sys/arch/x86/include/specialreg.h
561
#define CPUID_SEF_WAITPKG __BIT(5) /* TPAUSE,UMONITOR,UMWAIT */
sys/arch/x86/include/specialreg.h
562
#define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */
sys/arch/x86/include/specialreg.h
563
#define CPUID_SEF_CET_SS __BIT(7) /* CET Shadow Stack */
sys/arch/x86/include/specialreg.h
564
#define CPUID_SEF_GFNI __BIT(8) /* Galois Field instructions */
sys/arch/x86/include/specialreg.h
565
#define CPUID_SEF_VAES __BIT(9) /* Vector AES instruction set */
sys/arch/x86/include/specialreg.h
566
#define CPUID_SEF_VPCLMULQDQ __BIT(10) /* CLMUL instruction set */
sys/arch/x86/include/specialreg.h
567
#define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector Neural Network Instruction */
sys/arch/x86/include/specialreg.h
568
#define CPUID_SEF_AVX512_BITALG __BIT(12) /* BITALG instructions */
sys/arch/x86/include/specialreg.h
569
#define CPUID_SEF_TME_EN __BIT(13) /* Total Memory Encryption */
sys/arch/x86/include/specialreg.h
570
#define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) /* Vector Population Count D/Q */
sys/arch/x86/include/specialreg.h
571
#define CPUID_SEF_LA57 __BIT(16) /* 57bit linear addr & 5LVL paging */
sys/arch/x86/include/specialreg.h
573
#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */
sys/arch/x86/include/specialreg.h
574
#define CPUID_SEF_KL __BIT(23) /* Key Locker */
sys/arch/x86/include/specialreg.h
575
#define CPUID_SEF_BUS_LOCK_DETECT __BIT(24) /* OS bus-lock detection */
sys/arch/x86/include/specialreg.h
576
#define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */
sys/arch/x86/include/specialreg.h
577
#define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */
sys/arch/x86/include/specialreg.h
578
#define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */
sys/arch/x86/include/specialreg.h
579
#define CPUID_SEF_ENQCMD __BIT(29) /* Enqueue Stores */
sys/arch/x86/include/specialreg.h
580
#define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */
sys/arch/x86/include/specialreg.h
581
#define CPUID_SEF_PKS __BIT(31) /* Protection Keys for kern-mode pages */
sys/arch/x86/include/specialreg.h
594
#define CPUID_SEF_SGX_KEYS __BIT(1) /* Attestation support for SGX */
sys/arch/x86/include/specialreg.h
595
#define CPUID_SEF_AVX512_4VNNIW __BIT(2) /* AVX512 4-reg Neural Network ins */
sys/arch/x86/include/specialreg.h
596
#define CPUID_SEF_AVX512_4FMAPS __BIT(3) /* AVX512 4-reg Mult Accum Single precision */
sys/arch/x86/include/specialreg.h
597
#define CPUID_SEF_FSRM __BIT(4) /* Fast Short Rep Move */
sys/arch/x86/include/specialreg.h
598
#define CPUID_SEF_UINTR __BIT(5) /* User Interrupts */
sys/arch/x86/include/specialreg.h
599
#define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) /* AVX512 VP2INTERSECT */
sys/arch/x86/include/specialreg.h
600
#define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */
sys/arch/x86/include/specialreg.h
601
#define CPUID_SEF_MD_CLEAR __BIT(10) /* VERW clears CPU buffers */
sys/arch/x86/include/specialreg.h
602
#define CPUID_SEF_RTM_ALWAYS_ABORT __BIT(11) /* XBEGIN immediately abort */
sys/arch/x86/include/specialreg.h
603
#define CPUID_SEF_RTM_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */
sys/arch/x86/include/specialreg.h
604
#define CPUID_SEF_SERIALIZE __BIT(14) /* SERIALIZE instruction */
sys/arch/x86/include/specialreg.h
605
#define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */
sys/arch/x86/include/specialreg.h
606
#define CPUID_SEF_TSXLDTRK __BIT(16) /* TSX suspend load addr tracking */
sys/arch/x86/include/specialreg.h
607
#define CPUID_SEF_PCONFIG __BIT(18) /* Platform CONFIGuration */
sys/arch/x86/include/specialreg.h
608
#define CPUID_SEF_ARCH_LBR __BIT(19) /* Architectural LBR */
sys/arch/x86/include/specialreg.h
609
#define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */
sys/arch/x86/include/specialreg.h
610
#define CPUID_SEF_AMX_BF16 __BIT(22) /* AMX bfloat16 */
sys/arch/x86/include/specialreg.h
611
#define CPUID_SEF_AVX512_FP16 __BIT(23) /* AVX512 FP16 */
sys/arch/x86/include/specialreg.h
612
#define CPUID_SEF_AMX_TILE __BIT(24) /* Tile architecture */
sys/arch/x86/include/specialreg.h
613
#define CPUID_SEF_AMX_INT8 __BIT(25) /* AMX 8bit interger */
sys/arch/x86/include/specialreg.h
614
#define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */
sys/arch/x86/include/specialreg.h
615
#define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */
sys/arch/x86/include/specialreg.h
616
#define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */
sys/arch/x86/include/specialreg.h
617
#define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */
sys/arch/x86/include/specialreg.h
618
#define CPUID_SEF_CORE_CAP __BIT(30) /* IA32_CORE_CAPABILITIES */
sys/arch/x86/include/specialreg.h
619
#define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */
sys/arch/x86/include/specialreg.h
632
#define CPUID_SEF_AVXVNNI __BIT(4) /* AVX version of VNNI */
sys/arch/x86/include/specialreg.h
633
#define CPUID_SEF_AVX512_BF16 __BIT(5)
sys/arch/x86/include/specialreg.h
634
#define CPUID_SEF_FZLRMS __BIT(10) /* fast zero-length REP MOVSB */
sys/arch/x86/include/specialreg.h
635
#define CPUID_SEF_FSRSB __BIT(11) /* fast short REP STOSB */
sys/arch/x86/include/specialreg.h
636
#define CPUID_SEF_FSRCS __BIT(12) /* fast short REP CMPSB, REP SCASB */
sys/arch/x86/include/specialreg.h
637
#define CPUID_SEF_HRESET __BIT(22) /* HREST & IA32_HRESET_ENABLE MSR */
sys/arch/x86/include/specialreg.h
638
#define CPUID_SEF_LAM __BIT(26) /* Linear Address Masking */
sys/arch/x86/include/specialreg.h
647
#define CPUID_SEF_INTEL_PPIN __BIT(0) /* IA32_PPIN & IA32_PPIN_CTL MSRs */
sys/arch/x86/include/specialreg.h
653
#define CPUID_SEF_CET_SSS __BIT(18) /* CET Supervisor Shadow Stack */
sys/arch/x86/include/specialreg.h
659
#define CPUID_SEF_PSFD __BIT(0) /* Fast Forwarding Predictor Dis. */
sys/arch/x86/include/specialreg.h
660
#define CPUID_SEF_IPRED_CTRL __BIT(1) /* IPRED_DIS */
sys/arch/x86/include/specialreg.h
661
#define CPUID_SEF_RRSBA_CTRL __BIT(2) /* RRSBA for CPL3 */
sys/arch/x86/include/specialreg.h
662
#define CPUID_SEF_DDPD_U __BIT(3) /* Data Dependent Prefetcher */
sys/arch/x86/include/specialreg.h
663
#define CPUID_SEF_BHI_CTRL __BIT(4) /* BHI_DIS_S */
sys/arch/x86/include/specialreg.h
664
#define CPUID_SEF_MCDT_NO __BIT(5) /* !MXCSR Config Dependent Timing */
sys/arch/x86/include/specialreg.h
688
#define CPUID_PERF_CORECYCL __BIT(0) /* No core cycle */
sys/arch/x86/include/specialreg.h
689
#define CPUID_PERF_INSTRETRY __BIT(1) /* No instruction retried */
sys/arch/x86/include/specialreg.h
690
#define CPUID_PERF_REFCYCL __BIT(2) /* No reference cycles */
sys/arch/x86/include/specialreg.h
691
#define CPUID_PERF_LLCREF __BIT(3) /* No LLCache reference */
sys/arch/x86/include/specialreg.h
692
#define CPUID_PERF_LLCMISS __BIT(4) /* No LLCache miss */
sys/arch/x86/include/specialreg.h
693
#define CPUID_PERF_BRINSRETR __BIT(5) /* No branch inst. retried */
sys/arch/x86/include/specialreg.h
694
#define CPUID_PERF_BRMISPRRETR __BIT(6) /* No branch mispredict retry */
sys/arch/x86/include/specialreg.h
695
#define CPUID_PERF_TOPDOWNSLOT __BIT(7) /* No top-down slots */
sys/arch/x86/include/specialreg.h
709
#define CPUID_PERF_ANYTHREADDEPR __BIT(15) /* Any Thread deprecation */
sys/arch/x86/include/specialreg.h
756
#define CPUID_PES1_XSAVEOPT __BIT(0) /* xsaveopt instruction */
sys/arch/x86/include/specialreg.h
757
#define CPUID_PES1_XSAVEC __BIT(1) /* xsavec & compacted XRSTOR */
sys/arch/x86/include/specialreg.h
758
#define CPUID_PES1_XGETBV __BIT(2) /* xgetbv with ECX = 1 */
sys/arch/x86/include/specialreg.h
759
#define CPUID_PES1_XSAVES __BIT(3) /* xsaves/xrstors, IA32_XSS */
sys/arch/x86/include/specialreg.h
760
#define CPUID_PES1_XFD __BIT(4) /* eXtened Feature Disable */
sys/arch/x86/include/specialreg.h
775
#define CPUID_DATP_PGSIZE_4KB __BIT(0) /* 4KB page support */
sys/arch/x86/include/specialreg.h
776
#define CPUID_DATP_PGSIZE_2MB __BIT(1) /* 2MB page support */
sys/arch/x86/include/specialreg.h
777
#define CPUID_DATP_PGSIZE_4MB __BIT(2) /* 4MB page support */
sys/arch/x86/include/specialreg.h
778
#define CPUID_DATP_PGSIZE_1GB __BIT(3) /* 1GB page support */
sys/arch/x86/include/specialreg.h
793
#define CPUID_DATP_FULLASSOC __BIT(8) /* Full associative */
sys/arch/x86/include/specialreg.h
836
#define CPUID_SYSCALL __BIT(11) /* SYSCALL/SYSRET */
sys/arch/x86/include/specialreg.h
837
#define CPUID_XD __BIT(20) /* Execute Disable (like CPUID_NOX) */
sys/arch/x86/include/specialreg.h
838
#define CPUID_PAGE1GB __BIT(26) /* 1GB Large Page Support */
sys/arch/x86/include/specialreg.h
839
#define CPUID_RDTSCP __BIT(27) /* Read TSC Pair Instruction */
sys/arch/x86/include/specialreg.h
840
#define CPUID_EM64T __BIT(29) /* Intel EM64T */
sys/arch/x86/include/specialreg.h
847
#define CPUID_LAHF __BIT(0) /* LAHF/SAHF in IA-32e mode, 64bit sub*/
sys/arch/x86/include/specialreg.h
849
#define CPUID_PREFETCHW __BIT(8) /* PREFETCHW */
sys/arch/x86/include/specialreg.h
884
#define CPUID_CMPLEGACY __BIT(1) /* Compare Legacy */
sys/arch/x86/include/specialreg.h
885
#define CPUID_SVM __BIT(2) /* Secure Virtual Machine */
sys/arch/x86/include/specialreg.h
886
#define CPUID_EAPIC __BIT(3) /* Extended APIC space */
sys/arch/x86/include/specialreg.h
887
#define CPUID_ALTMOVCR0 __BIT(4) /* Lock Mov Cr0 */
sys/arch/x86/include/specialreg.h
888
#define CPUID_ABM __BIT(5) /* LZCNT instruction */
sys/arch/x86/include/specialreg.h
889
#define CPUID_SSE4A __BIT(6) /* SSE4A instruction set */
sys/arch/x86/include/specialreg.h
890
#define CPUID_MISALIGNSSE __BIT(7) /* Misaligned SSE */
sys/arch/x86/include/specialreg.h
891
#define CPUID_3DNOWPF __BIT(8) /* 3DNow Prefetch */
sys/arch/x86/include/specialreg.h
892
#define CPUID_OSVW __BIT(9) /* OS visible workarounds */
sys/arch/x86/include/specialreg.h
893
#define CPUID_IBS __BIT(10) /* Instruction Based Sampling */
sys/arch/x86/include/specialreg.h
894
#define CPUID_XOP __BIT(11) /* XOP instruction set */
sys/arch/x86/include/specialreg.h
895
#define CPUID_SKINIT __BIT(12) /* SKINIT */
sys/arch/x86/include/specialreg.h
896
#define CPUID_WDT __BIT(13) /* watchdog timer support */
sys/arch/x86/include/specialreg.h
897
#define CPUID_LWP __BIT(15) /* Light Weight Profiling */
sys/arch/x86/include/specialreg.h
898
#define CPUID_FMA4 __BIT(16) /* FMA4 instructions */
sys/arch/x86/include/specialreg.h
899
#define CPUID_TCE __BIT(17) /* Translation cache Extension */
sys/arch/x86/include/specialreg.h
900
#define CPUID_NODEID __BIT(19) /* NodeID MSR available */
sys/arch/x86/include/specialreg.h
901
#define CPUID_TBM __BIT(21) /* TBM instructions */
sys/arch/x86/include/specialreg.h
902
#define CPUID_TOPOEXT __BIT(22) /* cpuid Topology Extension */
sys/arch/x86/include/specialreg.h
903
#define CPUID_PCEC __BIT(23) /* Perf Ctr Ext Core */
sys/arch/x86/include/specialreg.h
904
#define CPUID_PCENB __BIT(24) /* Perf Ctr Ext NB */
sys/arch/x86/include/specialreg.h
905
#define CPUID_SPM __BIT(25) /* Stream Perf Mon */
sys/arch/x86/include/specialreg.h
906
#define CPUID_DBE __BIT(26) /* Data Breakpoint Extension */
sys/arch/x86/include/specialreg.h
907
#define CPUID_PTSC __BIT(27) /* PerfTsc */
sys/arch/x86/include/specialreg.h
908
#define CPUID_L2IPERFC __BIT(28) /* L2I performance counter Extension */
sys/arch/x86/include/specialreg.h
909
#define CPUID_MWAITX __BIT(29) /* MWAITX/MONITORX support */
sys/arch/x86/include/specialreg.h
910
#define CPUID_ADDRMASKEXT __BIT(30) /* Breakpoint Addressing Mask ext. */
sys/arch/x86/include/specialreg.h
935
#define CPUID_RAS_OVFL_RECOV __BIT(0) /* MCA Overflow Recovery */
sys/arch/x86/include/specialreg.h
936
#define CPUID_RAS_SUCCOR __BIT(1) /* Sw UnCorr. err. COntainment & Recovery */
sys/arch/x86/include/specialreg.h
937
#define CPUID_RAS_MCAX __BIT(3) /* MCA Extension */
sys/arch/x86/include/specialreg.h
943
#define CPUID_APM_TS __BIT(0) /* Temperature Sensor */
sys/arch/x86/include/specialreg.h
944
#define CPUID_APM_FID __BIT(1) /* Frequency ID control */
sys/arch/x86/include/specialreg.h
945
#define CPUID_APM_VID __BIT(2) /* Voltage ID control */
sys/arch/x86/include/specialreg.h
946
#define CPUID_APM_TTP __BIT(3) /* THERMTRIP (PCI F3xE4 register) */
sys/arch/x86/include/specialreg.h
947
#define CPUID_APM_HTC __BIT(4) /* Hardware thermal control (HTC) */
sys/arch/x86/include/specialreg.h
948
#define CPUID_APM_STC __BIT(5) /* Software thermal control (STC) */
sys/arch/x86/include/specialreg.h
949
#define CPUID_APM_100 __BIT(6) /* 100MHz multiplier control */
sys/arch/x86/include/specialreg.h
95
#define CR3_NO_TLB_FLUSH __BIT(63)
sys/arch/x86/include/specialreg.h
950
#define CPUID_APM_HWP __BIT(7) /* HW P-State control */
sys/arch/x86/include/specialreg.h
951
#define CPUID_APM_ITSC __BIT(8) /* Invariant TSC */
sys/arch/x86/include/specialreg.h
952
#define CPUID_APM_CPB __BIT(9) /* Core Performance Boost */
sys/arch/x86/include/specialreg.h
953
#define CPUID_APM_EFF __BIT(10) /* Effective Frequency (read-only) */
sys/arch/x86/include/specialreg.h
954
#define CPUID_APM_PROCFI __BIT(11) /* Processor Feedback Interface */
sys/arch/x86/include/specialreg.h
955
#define CPUID_APM_PROCPR __BIT(12) /* Processor Power Reporting */
sys/arch/x86/include/specialreg.h
956
#define CPUID_APM_CONNSTBY __BIT(13) /* Connected Standby */
sys/arch/x86/include/specialreg.h
957
#define CPUID_APM_RAPL __BIT(14) /* Running Average Power Limit */
sys/arch/x86/include/specialreg.h
975
#define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */
sys/arch/x86/include/specialreg.h
976
#define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */
sys/arch/x86/include/specialreg.h
977
#define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */
sys/arch/x86/include/specialreg.h
978
#define CPUID_CAPEX_INVLPGB __BIT(3) /* INVLPGB instruction */
sys/arch/x86/include/specialreg.h
979
#define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */
sys/arch/x86/include/specialreg.h
980
#define CPUID_CAPEX_MBE __BIT(6) /* Memory Bandwidth Enforcement */
sys/arch/x86/include/specialreg.h
981
#define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */
sys/arch/x86/include/specialreg.h
982
#define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */
sys/arch/x86/include/specialreg.h
983
#define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */
sys/arch/x86/include/specialreg.h
984
#define CPUID_CAPEX_INT_WBINVD __BIT(13) /* Interruptable WB[NO]INVD */
sys/arch/x86/include/specialreg.h
985
#define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */
sys/arch/x86/include/specialreg.h
986
#define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */
sys/arch/x86/include/specialreg.h
987
#define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */
sys/arch/x86/include/specialreg.h
988
#define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */
sys/arch/x86/include/specialreg.h
989
#define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */
sys/arch/x86/include/specialreg.h
990
#define CPUID_CAPEX_IBRS_SAMEMODE __BIT(19) /* IBRS same speculation limits */
sys/arch/x86/include/specialreg.h
991
#define CPUID_CAPEX_EFER_LSMSLE_UN __BIT(20) /* EFER.LMSLE is unsupported */
sys/arch/x86/include/specialreg.h
992
#define CPUID_CAPEX_INVLPGB_NEST __BIT(21) /* INVLPGB nested translation */
sys/arch/x86/include/specialreg.h
993
#define CPUID_CAPEX_AMD_PPIN __BIT(23) /* Protected Processor Inventory Number */
sys/arch/x86/include/specialreg.h
994
#define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */
sys/arch/x86/include/specialreg.h
995
#define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */
sys/arch/x86/include/specialreg.h
996
#define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */
sys/arch/x86/include/specialreg.h
997
#define CPUID_CAPEX_CPPC __BIT(27) /* Collaborative Processor Perf. Control */
sys/arch/x86/include/specialreg.h
998
#define CPUID_CAPEX_PSFD __BIT(28) /* Predictive Store Forward Dis */
sys/arch/x86/include/specialreg.h
999
#define CPUID_CAPEX_BTC_NO __BIT(29) /* Branch Type Confusion NO */
sys/arch/x86/pci/amdzentemp.c
98
#define AMD_17H_CUR_TMP_RANGE_SEL __BIT(19)
sys/arch/x86/pci/amdzentemp.c
99
#define AMD_17H_CCD_TMP_VALID __BIT(11)
sys/arch/x86/pci/ichlpcib.c
1010
data |= __BIT(shift);
sys/arch/x86/pci/ichlpcib.c
1012
data &= ~__BIT(shift);
sys/arch/x86/pci/ichlpcib.c
1034
data &= ~__BIT(shift);
sys/arch/x86/pci/ichlpcib.c
1037
data |= __BIT(shift);
sys/arch/x86/pci/ichlpcib.c
1047
data |= __BIT(shift);
sys/arch/x86/pci/ichlpcib.c
1049
data &= ~__BIT(shift);
sys/arch/x86/pci/ichlpcib.c
928
bit = __BIT(shift);
sys/arch/x86/pci/ichlpcib.c
992
return (__SHIFTOUT(data, __BIT(shift)) ? GPIO_PIN_HIGH : GPIO_PIN_LOW);
sys/arch/x86/pci/lpssreg.h
34
#define LPSS_RESET_DMA __BIT(2)
sys/arch/x86/pci/lpssreg.h
52
#define LPSS_TXACK_OVF __BIT(31)
sys/arch/x86/pci/lpssreg.h
56
#define LPSS_RXACK_OVF __BIT(31)
sys/arch/x86/pci/lpssreg.h
60
#define LPSS_TX_IRQ_MSK __BIT(1)
sys/arch/x86/pci/lpssreg.h
61
#define LPSS_TX_IRQ_I __BIT(0)
sys/arch/x86/pci/lpssreg.h
64
#define LPSS_TX_IRQ_CLRI __BIT(0)
sys/arch/x86/pci/lpssreg.h
81
#define LPSS_DEVIDLE_IRQ __BIT(4)
sys/arch/x86/pci/lpssreg.h
82
#define LPSS_DEVIDLE_RESTORE __BIT(3)
sys/arch/x86/pci/lpssreg.h
83
#define LPSS_DEVIDLE_IDLE __BIT(2)
sys/arch/x86/pci/lpssreg.h
84
#define LPSS_DEVIDLE_INPROG __BIT(0)
sys/arch/x86/pci/lpssreg.h
87
#define LPSS_CAP_DMA __BIT(8)
sys/arch/x86/x86/coretemp.c
101
#define MSR_THERM_INTR_TRIP2 __BIT(23)
sys/arch/x86/x86/coretemp.c
289
if ((msr & __BIT(28)) == 0)
sys/arch/x86/x86/coretemp.c
300
if ((msr & __BIT(30)) != 0)
sys/arch/x86/x86/coretemp.c
79
#define MSR_THERM_STATUS_STA __BIT(0)
sys/arch/x86/x86/coretemp.c
80
#define MSR_THERM_STATUS_LOG __BIT(1)
sys/arch/x86/x86/coretemp.c
81
#define MSR_THERM_STATUS_PROCHOT_EVT __BIT(2)
sys/arch/x86/x86/coretemp.c
82
#define MSR_THERM_STATUS_PROCHOT_LOG __BIT(3)
sys/arch/x86/x86/coretemp.c
83
#define MSR_THERM_STATUS_CRIT_STA __BIT(4)
sys/arch/x86/x86/coretemp.c
84
#define MSR_THERM_STATUS_CRIT_LOG __BIT(5)
sys/arch/x86/x86/coretemp.c
85
#define MSR_THERM_STATUS_TRIP1_STA __BIT(6)
sys/arch/x86/x86/coretemp.c
86
#define MSR_THERM_STATUS_TRIP1_LOG __BIT(7)
sys/arch/x86/x86/coretemp.c
87
#define MSR_THERM_STATUS_TRIP2_STA __BIT(8)
sys/arch/x86/x86/coretemp.c
88
#define MSR_THERM_STATUS_TRIP2_LOG __BIT(9)
sys/arch/x86/x86/coretemp.c
91
#define MSR_THERM_STATUS_VALID __BIT(31)
sys/arch/x86/x86/coretemp.c
93
#define MSR_THERM_INTR_HITEMP __BIT(0)
sys/arch/x86/x86/coretemp.c
94
#define MSR_THERM_INTR_LOTEMPT __BIT(1)
sys/arch/x86/x86/coretemp.c
95
#define MSR_THERM_INTR_PROCHOT __BIT(2)
sys/arch/x86/x86/coretemp.c
96
#define MSR_THERM_INTR_FORCPR __BIT(3)
sys/arch/x86/x86/coretemp.c
97
#define MSR_THERM_INTR_OVERHEAT __BIT(4)
sys/arch/x86/x86/coretemp.c
99
#define MSR_THERM_INTR_TRIP1 __BIT(15)
sys/arch/x86/x86/identcpu.c
864
if (x86_xsave_features & __BIT(i)) {
sys/arch/x86/x86/pmap.c
6084
#define EPT_R __BIT(0) /* read */
sys/arch/x86/x86/pmap.c
6085
#define EPT_W __BIT(1) /* write */
sys/arch/x86/x86/pmap.c
6086
#define EPT_X __BIT(2) /* execute */
sys/arch/x86/x86/pmap.c
6093
#define EPT_NOPAT __BIT(6)
sys/arch/x86/x86/pmap.c
6094
#define EPT_L __BIT(7) /* large */
sys/arch/x86/x86/pmap.c
6095
#define EPT_A __BIT(8) /* accessed */
sys/arch/x86/x86/pmap.c
6096
#define EPT_D __BIT(9) /* dirty */
sys/arch/x86/x86/pmap.c
6098
#define EPT_PVLIST __BIT(60)
sys/arch/x86/x86/pmap.c
6099
#define EPT_WIRED __BIT(61)
sys/crypto/aes/aes_ccm.c
59
#define CCM_AFLAGS_ADATA __BIT(6)
sys/dev/acpi/acpi.c
1556
sc->sc_sleepstates |= __BIT(i);
sys/dev/acpi/acpi.c
1591
if ((sc->sc_sleepstates & __BIT(state)) == 0) {
sys/dev/acpi/acpi.c
1869
((sc->sc_sleepstates & __BIT(0)) != 0) ? "S0 " : "",
sys/dev/acpi/acpi.c
1870
((sc->sc_sleepstates & __BIT(1)) != 0) ? "S1 " : "",
sys/dev/acpi/acpi.c
1871
((sc->sc_sleepstates & __BIT(2)) != 0) ? "S2 " : "",
sys/dev/acpi/acpi.c
1872
((sc->sc_sleepstates & __BIT(3)) != 0) ? "S3 " : "",
sys/dev/acpi/acpi.c
1873
((sc->sc_sleepstates & __BIT(4)) != 0) ? "S4 " : "",
sys/dev/acpi/acpi.c
1874
((sc->sc_sleepstates & __BIT(5)) != 0) ? "S5 " : "");
sys/dev/acpi/acpi_cpu.h
101
#define ACPICPU_FLAG_PIIX4 __BIT(3) /* Broken (quirk) */
sys/dev/acpi/acpi_cpu.h
103
#define ACPICPU_FLAG_C_FFH __BIT(4) /* Native C-states */
sys/dev/acpi/acpi_cpu.h
104
#define ACPICPU_FLAG_C_FADT __BIT(5) /* C-states with FADT */
sys/dev/acpi/acpi_cpu.h
105
#define ACPICPU_FLAG_C_DEP __BIT(6) /* C-state CPU coordination */
sys/dev/acpi/acpi_cpu.h
106
#define ACPICPU_FLAG_C_BM __BIT(7) /* Bus master control */
sys/dev/acpi/acpi_cpu.h
107
#define ACPICPU_FLAG_C_BM_STS __BIT(8) /* Bus master check required */
sys/dev/acpi/acpi_cpu.h
108
#define ACPICPU_FLAG_C_ARB __BIT(9) /* Bus master arbitration */
sys/dev/acpi/acpi_cpu.h
109
#define ACPICPU_FLAG_C_TSC __BIT(10) /* TSC broken, > C1, Px, Tx */
sys/dev/acpi/acpi_cpu.h
110
#define ACPICPU_FLAG_C_APIC __BIT(11) /* APIC timer broken, > C1 */
sys/dev/acpi/acpi_cpu.h
111
#define ACPICPU_FLAG_C_C1E __BIT(12) /* AMD C1E detected */
sys/dev/acpi/acpi_cpu.h
113
#define ACPICPU_FLAG_P_FFH __BIT(13) /* Native P-states */
sys/dev/acpi/acpi_cpu.h
114
#define ACPICPU_FLAG_P_DEP __BIT(14) /* P-state CPU coordination */
sys/dev/acpi/acpi_cpu.h
115
#define ACPICPU_FLAG_P_HWF __BIT(15) /* HW feedback supported */
sys/dev/acpi/acpi_cpu.h
116
#define ACPICPU_FLAG_P_XPSS __BIT(16) /* Microsoft XPSS in use */
sys/dev/acpi/acpi_cpu.h
117
#define ACPICPU_FLAG_P_TURBO __BIT(17) /* Turbo Boost / Turbo Core */
sys/dev/acpi/acpi_cpu.h
118
#define ACPICPU_FLAG_P_FIDVID __BIT(18) /* AMD "FID/VID algorithm" */
sys/dev/acpi/acpi_cpu.h
120
#define ACPICPU_FLAG_T_FFH __BIT(19) /* Native throttling */
sys/dev/acpi/acpi_cpu.h
121
#define ACPICPU_FLAG_T_FADT __BIT(20) /* Throttling with FADT */
sys/dev/acpi/acpi_cpu.h
122
#define ACPICPU_FLAG_T_DEP __BIT(21) /* T-state CPU coordination */
sys/dev/acpi/acpi_cpu.h
43
#define ACPICPU_PDC_P_FFH __BIT(0) /* SpeedStep MSRs */
sys/dev/acpi/acpi_cpu.h
44
#define ACPICPU_PDC_C_C1_HALT __BIT(1) /* C1 "I/O then halt" */
sys/dev/acpi/acpi_cpu.h
45
#define ACPICPU_PDC_T_FFH __BIT(2) /* OnDemand throttling MSRs */
sys/dev/acpi/acpi_cpu.h
46
#define ACPICPU_PDC_C_C1PT __BIT(3) /* SMP C1, Px, and Tx (same) */
sys/dev/acpi/acpi_cpu.h
47
#define ACPICPU_PDC_C_C2C3 __BIT(4) /* SMP C2 and C3 (same) */
sys/dev/acpi/acpi_cpu.h
48
#define ACPICPU_PDC_P_SW __BIT(5) /* SMP Px (different) */
sys/dev/acpi/acpi_cpu.h
49
#define ACPICPU_PDC_C_SW __BIT(6) /* SMP Cx (different) */
sys/dev/acpi/acpi_cpu.h
50
#define ACPICPU_PDC_T_SW __BIT(7) /* SMP Tx (different) */
sys/dev/acpi/acpi_cpu.h
51
#define ACPICPU_PDC_C_C1_FFH __BIT(8) /* SMP C1 native beyond halt */
sys/dev/acpi/acpi_cpu.h
52
#define ACPICPU_PDC_C_C2C3_FFH __BIT(9) /* SMP C2 and C2 native */
sys/dev/acpi/acpi_cpu.h
53
#define ACPICPU_PDC_P_HWF __BIT(11) /* Px hardware feedback */
sys/dev/acpi/acpi_cpu.h
55
#define ACPICPU_PDC_GAS_HW __BIT(0) /* HW-coordinated state */
sys/dev/acpi/acpi_cpu.h
56
#define ACPICPU_PDC_GAS_BM __BIT(1) /* Bus master check required */
sys/dev/acpi/acpi_cpu.h
97
#define ACPICPU_FLAG_C __BIT(0) /* C-states supported */
sys/dev/acpi/acpi_cpu.h
98
#define ACPICPU_FLAG_P __BIT(1) /* P-states supported */
sys/dev/acpi/acpi_cpu.h
99
#define ACPICPU_FLAG_T __BIT(2) /* T-states supported */
sys/dev/acpi/acpi_cpu_tstate.c
590
sc->sc_tstate[i].ts_control = (count - i) | __BIT(3);
sys/dev/acpi/acpi_display.c
237
#define ACPI_DISP_VGA_CAP__DOS __BIT(0)
sys/dev/acpi/acpi_display.c
238
#define ACPI_DISP_VGA_CAP__DOD __BIT(1)
sys/dev/acpi/acpi_display.c
239
#define ACPI_DISP_VGA_CAP__ROM __BIT(2)
sys/dev/acpi/acpi_display.c
240
#define ACPI_DISP_VGA_CAP__GPD __BIT(3)
sys/dev/acpi/acpi_display.c
241
#define ACPI_DISP_VGA_CAP__SPD __BIT(4)
sys/dev/acpi/acpi_display.c
242
#define ACPI_DISP_VGA_CAP__VPO __BIT(5)
sys/dev/acpi/acpi_display.c
309
#define ACPI_DISP_OUT_CAP__BCL __BIT(0)
sys/dev/acpi/acpi_display.c
310
#define ACPI_DISP_OUT_CAP__BCM __BIT(1)
sys/dev/acpi/acpi_display.c
311
#define ACPI_DISP_OUT_CAP__BQC __BIT(2)
sys/dev/acpi/acpi_display.c
312
#define ACPI_DISP_OUT_CAP__DDC __BIT(3)
sys/dev/acpi/acpi_display.c
313
#define ACPI_DISP_OUT_CAP__DCS __BIT(4)
sys/dev/acpi/acpi_display.c
314
#define ACPI_DISP_OUT_CAP__DGS __BIT(5)
sys/dev/acpi/acpi_display.c
315
#define ACPI_DISP_OUT_CAP__DSS __BIT(6)
sys/dev/acpi/acpi_ec.c
190
if (acpiec_debug & __BIT(n)) { \
sys/dev/acpi/acpi_ec.c
972
if (acpiec_debug & __BIT(ACPIEC_DEBUG_TRANSITION)) {
sys/dev/acpi/acpi_mcfg.c
54
#define PCIDEV_SET_VALID(mb, d, f) ((mb)->valid_devs[(d)] |= __BIT((f)))
sys/dev/acpi/acpi_mcfg.c
55
#define PCIDEV_SET_INVALID(mb, d, f) ((mb)->valid_devs[(d)] &= ~__BIT((f)))
sys/dev/acpi/acpi_mcfg.c
56
#define PCIDEV_IS_VALID(mb, d, f) ((mb)->valid_devs[(d)] & __BIT((f)))
sys/dev/acpi/acpi_mcfg.c
58
#define EXTCONF_SET_VALID(mb, d, f) ((mb)->valid_extconf[(d)] |= __BIT((f)))
sys/dev/acpi/acpi_mcfg.c
59
#define EXTCONF_SET_INVALID(mb, d, f) ((mb)->valid_extconf[(d)] &= ~__BIT((f)))
sys/dev/acpi/acpi_mcfg.c
60
#define EXTCONF_IS_VALID(mb, d, f) ((mb)->valid_extconf[(d)] & __BIT((f)))
sys/dev/acpi/acpi_pcc.c
54
#define PCC_STATUS_COMMAND_COMPLETE __BIT(0)
sys/dev/acpi/acpi_pcc.c
55
#define PCC_STATUS_COMMAND_ERROR __BIT(2)
sys/dev/acpi/acpi_pcc.h
32
#define PCC_READ __BIT(0)
sys/dev/acpi/acpi_pcc.h
33
#define PCC_WRITE __BIT(1)
sys/dev/acpi/acpi_pmtr.c
60
#define ACPIPMTR_FLAGS_MEASURE __BIT(0)
sys/dev/acpi/acpi_pmtr.c
61
#define ACPIPMTR_FLAGS_TRIP __BIT(1)
sys/dev/acpi/acpi_pmtr.c
62
#define ACPIPMTR_FLAGS_HWLIMIT __BIT(2)
sys/dev/acpi/acpi_pmtr.c
63
#define ACPIPMTR_FLAGS_NOTIFY __BIT(3)
sys/dev/acpi/acpi_pmtr.c
64
#define ACPIPMTR_FLAGS_DISCHARGE __BIT(8)
sys/dev/acpi/acpi_verbose.c
459
KASSERT(__BIT(acpi_fadt_flags[i].fadt_offset) ==
sys/dev/acpi/acpireg.h
51
#define ACPI_OSC_QUERY __BIT(0)
sys/dev/acpi/acpireg.h
52
#define ACPI_OSC_ERROR __BIT(1)
sys/dev/acpi/acpireg.h
53
#define ACPI_OSC_ERROR_UUID __BIT(2)
sys/dev/acpi/acpireg.h
54
#define ACPI_OSC_ERROR_REV __BIT(3)
sys/dev/acpi/acpireg.h
55
#define ACPI_OSC_ERROR_MASKED __BIT(4)
sys/dev/acpi/acpivar.h
102
#define ACPI_PCI_INFO_DEVICE __BIT(0) /* PCI device */
sys/dev/acpi/acpivar.h
103
#define ACPI_PCI_INFO_BRIDGE __BIT(1) /* PCI bridge */
sys/dev/acpi/acpivar.h
159
#define ACPI_DEVICE_POWER __BIT(0) /* Support for D-states */
sys/dev/acpi/acpivar.h
160
#define ACPI_DEVICE_WAKEUP __BIT(1) /* Support for wake-up */
sys/dev/acpi/acpivar.h
161
#define ACPI_DEVICE_EJECT __BIT(2) /* Support for "ejection" */
sys/dev/acpi/acpivar.h
162
#define ACPI_DEVICE_DOCK __BIT(3) /* Support for docking */
sys/dev/acpi/amdgpio.c
513
if ((status & __BIT(pin / 4)) == 0) {
sys/dev/acpi/apei.c
954
f & __BIT(0) ? " (event time)" : " (collect time)");
sys/dev/acpi/apei_cper.h
150
CPER_MEMORY_ERROR_VALID_ERROR_STATUS = __BIT(0),
sys/dev/acpi/apei_cper.h
151
CPER_MEMORY_ERROR_VALID_PHYSICAL_ADDRESS = __BIT(1),
sys/dev/acpi/apei_cper.h
152
CPER_MEMORY_ERROR_VALID_PHYSICAL_ADDRESS_MASK = __BIT(2),
sys/dev/acpi/apei_cper.h
153
CPER_MEMORY_ERROR_VALID_NODE = __BIT(3),
sys/dev/acpi/apei_cper.h
154
CPER_MEMORY_ERROR_VALID_CARD = __BIT(4),
sys/dev/acpi/apei_cper.h
155
CPER_MEMORY_ERROR_VALID_MODULE = __BIT(5),
sys/dev/acpi/apei_cper.h
156
CPER_MEMORY_ERROR_VALID_BANK = __BIT(6),
sys/dev/acpi/apei_cper.h
157
CPER_MEMORY_ERROR_VALID_DEVICE = __BIT(7),
sys/dev/acpi/apei_cper.h
158
CPER_MEMORY_ERROR_VALID_ROW = __BIT(8),
sys/dev/acpi/apei_cper.h
159
CPER_MEMORY_ERROR_VALID_COLUMN = __BIT(9),
sys/dev/acpi/apei_cper.h
160
CPER_MEMORY_ERROR_VALID_BIT_POSITION = __BIT(10),
sys/dev/acpi/apei_cper.h
161
CPER_MEMORY_ERROR_VALID_REQUESTOR_ID = __BIT(11),
sys/dev/acpi/apei_cper.h
162
CPER_MEMORY_ERROR_VALID_RESPONDER_ID = __BIT(12),
sys/dev/acpi/apei_cper.h
163
CPER_MEMORY_ERROR_VALID_TARGET_ID = __BIT(13),
sys/dev/acpi/apei_cper.h
164
CPER_MEMORY_ERROR_VALID_MEMORY_ERROR_TYPE = __BIT(14),
sys/dev/acpi/apei_cper.h
165
CPER_MEMORY_ERROR_VALID_RANK_NUMBER = __BIT(15),
sys/dev/acpi/apei_cper.h
166
CPER_MEMORY_ERROR_VALID_CARD_HANDLE = __BIT(16),
sys/dev/acpi/apei_cper.h
167
CPER_MEMORY_ERROR_VALID_MODULE_HANDLE = __BIT(17),
sys/dev/acpi/apei_cper.h
168
CPER_MEMORY_ERROR_VALID_EXTENDED_ROW = __BIT(18),
sys/dev/acpi/apei_cper.h
169
CPER_MEMORY_ERROR_VALID_BANK_GROUP = __BIT(19),
sys/dev/acpi/apei_cper.h
170
CPER_MEMORY_ERROR_VALID_BANK_ADDRESS = __BIT(20),
sys/dev/acpi/apei_cper.h
171
CPER_MEMORY_ERROR_VALID_CHIP_ID = __BIT(21),
sys/dev/acpi/apei_cper.h
231
CPER_MEMORY_ERROR_EXTENDED_ROWBIT16 = __BIT(0),
sys/dev/acpi/apei_cper.h
232
CPER_MEMORY_ERROR_EXTENDED_ROWBIT17 = __BIT(1),
sys/dev/acpi/apei_cper.h
270
CPER_PCIE_ERROR_VALID_PORT_TYPE = __BIT(0),
sys/dev/acpi/apei_cper.h
271
CPER_PCIE_ERROR_VALID_VERSION = __BIT(1),
sys/dev/acpi/apei_cper.h
272
CPER_PCIE_ERROR_VALID_COMMAND_STATUS = __BIT(2),
sys/dev/acpi/apei_cper.h
273
CPER_PCIE_ERROR_VALID_DEVICE_ID = __BIT(3),
sys/dev/acpi/apei_cper.h
274
CPER_PCIE_ERROR_VALID_DEVICE_SERIAL = __BIT(4),
sys/dev/acpi/apei_cper.h
275
CPER_PCIE_ERROR_VALID_BRIDGE_CONTROL_STATUS = __BIT(5),
sys/dev/acpi/apei_cper.h
276
CPER_PCIE_ERROR_VALID_CAPABILITY_STRUCTURE = __BIT(6),
sys/dev/acpi/apei_cper.h
277
CPER_PCIE_ERROR_VALID_AER_INFO = __BIT(7),
sys/dev/acpi/apei_cper.h
73
CPER_VALID_PLATFORM_ID = __BIT(0),
sys/dev/acpi/apei_cper.h
74
CPER_VALID_TIMESTAMP = __BIT(1),
sys/dev/acpi/apei_cper.h
75
CPER_VALID_PARTITION_ID = __BIT(2),
sys/dev/acpi/apei_cper.h
82
CPER_HW_ERROR_FLAG_RECOVERED = __BIT(0),
sys/dev/acpi/apei_cper.h
83
CPER_HW_ERROR_FLAG_PREVERR = __BIT(1),
sys/dev/acpi/apei_cper.h
84
CPER_HW_ERROR_FLAG_SIMULATED = __BIT(2),
sys/dev/acpi/apei_cper.h
91
CPER_SECTION_FLAG_PRIMARY = __BIT(0),
sys/dev/acpi/apei_cper.h
92
CPER_SECTION_FLAG_CONTAINMENT_WARNING = __BIT(1),
sys/dev/acpi/apei_cper.h
93
CPER_SECTION_FLAG_RESET = __BIT(2),
sys/dev/acpi/apei_cper.h
94
CPER_SECTION_FLAG_ERROR_THRESHOLD_EXCEEDED = __BIT(3),
sys/dev/acpi/apei_cper.h
95
CPER_SECTION_FLAG_RESOURCE_NOT_ACCESSIBLE = __BIT(4),
sys/dev/acpi/apei_cper.h
96
CPER_SECTION_FLAG_LATENT_ERROR = __BIT(5),
sys/dev/acpi/apei_cper.h
97
CPER_SECTION_FLAG_PROPAGATED = __BIT(6),
sys/dev/acpi/apei_cper.h
98
CPER_SECTION_FLAG_OVERFLOW = __BIT(7),
sys/dev/acpi/fujbp_acpi.c
100
#define FUJITSU_BP_HKS_BRIGHTNESS __BIT(0)
sys/dev/acpi/fujbp_acpi.c
101
#define FUJITSU_BP_HKS_POINTER __BIT(3)
sys/dev/acpi/fujbp_acpi.c
107
#define FUJITSU_BP_CAP_GHKS __BIT(0)
sys/dev/acpi/fujbp_acpi.c
108
#define FUJITSU_BP_CAP_RBLL __BIT(1)
sys/dev/acpi/fujbp_acpi.c
109
#define FUJITSU_BP_CAP_GBLL __BIT(2)
sys/dev/acpi/fujbp_acpi.c
110
#define FUJITSU_BP_CAP_SBLL __BIT(3)
sys/dev/acpi/fujbp_acpi.c
111
#define FUJITSU_BP_CAP_GMOU __BIT(4)
sys/dev/acpi/fujbp_acpi.c
112
#define FUJITSU_BP_CAP_SMOU __BIT(5)
sys/dev/acpi/fujhk_acpi.c
75
#define FUJITSU_HK_CAP_GIRB __BIT(0)
sys/dev/acpi/fujhk_acpi.c
76
#define FUJITSU_HK_CAP_FUNC __BIT(1)
sys/dev/acpi/plgpio_acpi.c
162
asc->sc_base.sc_reserved_mask |= __BIT(pin);
sys/dev/acpi/plgpio_acpi.c
172
ibe &= ~__BIT(pin);
sys/dev/acpi/plgpio_acpi.c
173
iev |= __BIT(pin);
sys/dev/acpi/plgpio_acpi.c
176
ibe &= ~__BIT(pin);
sys/dev/acpi/plgpio_acpi.c
177
iev &= ~__BIT(pin);
sys/dev/acpi/plgpio_acpi.c
180
ibe |= __BIT(pin);
sys/dev/acpi/plgpio_acpi.c
189
is |= __BIT(pin);
sys/dev/acpi/plgpio_acpi.c
192
is &= ~__BIT(pin);
sys/dev/acpi/plgpio_acpi.c
199
PLGPIO_WRITE(sc, PL061_GPIOIC_REG, __BIT(pin));
sys/dev/acpi/plgpio_acpi.c
202
ie |= __BIT(pin);
sys/dev/acpi/plgpio_acpi.c
224
mis &= ~__BIT(pin);
sys/dev/acpi/qcomgpioreg.h
26
#define TLMM_GPIO_CTL_OE __BIT(9)
sys/dev/acpi/qcomgpioreg.h
31
#define TLMM_GPIO_IN_OUT_GPIO_IN __BIT(0)
sys/dev/acpi/qcomgpioreg.h
32
#define TLMM_GPIO_IN_OUT_GPIO_OUT __BIT(1)
sys/dev/acpi/qcomgpioreg.h
37
#define TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN __BIT(4)
sys/dev/acpi/qcomgpioreg.h
43
#define TLMM_GPIO_INTR_CFG_INTR_POL_CTL __BIT(1)
sys/dev/acpi/qcomgpioreg.h
44
#define TLMM_GPIO_INTR_CFG_INTR_ENABLE __BIT(0)
sys/dev/acpi/qcomgpioreg.h
47
#define TLMM_GPIO_INTR_STATUS_INTR_STATUS __BIT(0)
sys/dev/acpi/sdhc_acpi.c
200
ISSET(funcs, __BIT(ROCKCHIP_DSM_FUNC_SET_CARD_CLOCK))) {
sys/dev/acpi/thinkpad_acpi.c
724
param[1].Integer.Value = ((__BIT(i) & mask) != 0);
sys/dev/acpi/wmi/wmi_hp.c
122
#define WMI_HP_SWITCH_MASK_WLAN_ONAIR __BIT(8)
sys/dev/acpi/wmi/wmi_hp.c
123
#define WMI_HP_SWITCH_MASK_WLAN_ENABLED __BIT(9)
sys/dev/acpi/wmi/wmi_hp.c
124
#define WMI_HP_SWITCH_MASK_WLAN_RADIO __BIT(11)
sys/dev/acpi/wmi/wmi_hp.c
125
#define WMI_HP_SWITCH_MASK_BT_ONAIR __BIT(16)
sys/dev/acpi/wmi/wmi_hp.c
126
#define WMI_HP_SWITCH_MASK_BT_ENABLED __BIT(17)
sys/dev/acpi/wmi/wmi_hp.c
127
#define WMI_HP_SWITCH_MASK_BT_RADIO __BIT(19)
sys/dev/acpi/wmi/wmi_hp.c
128
#define WMI_HP_SWITCH_MASK_WWAN_ONAIR __BIT(24)
sys/dev/acpi/wmi/wmi_hp.c
129
#define WMI_HP_SWITCH_MASK_WWAN_ENABLED __BIT(25)
sys/dev/acpi/wmi/wmi_hp.c
130
#define WMI_HP_SWITCH_MASK_WWAN_RADIO __BIT(27)
sys/dev/acpi/xhci_acpi.c
52
#define XHCI_ACPI_FLAG_URS __BIT(0)
sys/dev/ata/ata.c
1312
KASSERT((chq->active_xfers_used & __BIT(xfer->c_slot)) == 0);
sys/dev/ata/ata.c
1324
chq->active_xfers_used |= __BIT(xfer->c_slot);
sys/dev/ata/ata.c
1386
KASSERT((chq->active_xfers_used & __BIT(xfer->c_slot)) != 0);
sys/dev/ata/ata.c
1396
chq->active_xfers_used &= ~__BIT(xfer->c_slot);
sys/dev/ata/ata_subr.c
314
mask = __BIT(MIN(chq->queue_openings, drv_openings)) - 1;
sys/dev/ata/ata_subr.c
324
chq->queue_xfers_avail &= ~__BIT(*c_slot);
sys/dev/ata/ata_subr.c
326
KASSERT((chq->active_xfers_used & __BIT(*c_slot)) == 0);
sys/dev/ata/ata_subr.c
337
KASSERT((chq->active_xfers_used & __BIT(c_slot)) == 0);
sys/dev/ata/ata_subr.c
338
KASSERT((chq->queue_xfers_avail & __BIT(c_slot)) == 0);
sys/dev/ata/ata_subr.c
340
chq->queue_xfers_avail |= __BIT(c_slot);
sys/dev/ata/ata_subr.c
77
chq->queue_xfers_avail = __BIT(chq->queue_openings) - 1;
sys/dev/ata/ata_subr.c
90
KASSERTMSG((chq->active_xfers_used & __BIT(hwslot)) != 0,
sys/dev/ata/atareg.h
100
#define WDCC_LOG_NQ __BIT(7)
sys/dev/ata/atareg.h
239
#define WDSC_PRIO_HIGH __BIT(15)
sys/dev/ata/atareg.h
240
#define WDSC_PRIO_ISOCHRONOUS __BIT(14)
sys/dev/bluetooth/btmagic.c
1217
mb |= __BIT(0);
sys/dev/bluetooth/btmagic.c
1219
mb |= __BIT(2);
sys/dev/bluetooth/btmagic.c
1333
mb |= __BIT(0);
sys/dev/bluetooth/btmagic.c
1335
mb |= __BIT(2);
sys/dev/bluetooth/btmagic.c
1362
if (ISSET(sc->sc_smask, __BIT(id))) {
sys/dev/bluetooth/btmagic.c
1376
SET(sc->sc_smask, __BIT(id));
sys/dev/bluetooth/btmagic.c
1390
CLR(sc->sc_smask, __BIT(id));
sys/dev/bluetooth/btmagic.c
1410
mb = __BIT(1);
sys/dev/bluetooth/btmagic.c
1553
mb = __BIT(0);
sys/dev/bluetooth/btmagic.c
1555
mb = __BIT(2);
sys/dev/bluetooth/btmagic.c
1557
mb = __BIT(1);
sys/dev/bluetooth/btmagic.c
1581
if (ISSET(sc->sc_smask, __BIT(id))) {
sys/dev/bluetooth/btmagic.c
1608
KASSERT(!ISSET(sc->sc_smask, __BIT(id)));
sys/dev/bluetooth/btmagic.c
1609
SET(sc->sc_smask, __BIT(id));
sys/dev/bluetooth/btmagic.c
1628
if (ISSET(sc->sc_smask, __BIT(id))) {
sys/dev/bluetooth/btmagic.c
1629
CLR(sc->sc_smask, __BIT(id));
sys/dev/bluetooth/btmagic.c
1668
return __BIT(0);
sys/dev/bluetooth/btmagic.c
1681
if ((sc->sc_mb & __BIT(0)) != 0) {
sys/dev/bluetooth/btmagic.c
1682
sc->sc_mb &= ~__BIT(0);
sys/dev/bluetooth/btmagic.c
182
#define BTMAGIC_CONNECTING __BIT(0) /* we are connecting */
sys/dev/bluetooth/btmagic.c
183
#define BTMAGIC_ENABLED __BIT(1) /* touch reports enabled */
sys/dev/bluetooth/btms.c
159
#define BTMS_QUIRK_ELECOM __BIT(0)
sys/dev/cadence/cemacreg.h
100
#define GEM_DMA_CFG_AHB_ENDIAN_SWAP_MGMT_EN __BIT(6)
sys/dev/cadence/cemacreg.h
122
#define GEM_CTL_ZEROPAUSETX __BIT(12)
sys/dev/cadence/cemacreg.h
123
#define GEM_CTL_PAUSETX __BIT(11)
sys/dev/cadence/cemacreg.h
124
#define GEM_CTL_HALTTX __BIT(10)
sys/dev/cadence/cemacreg.h
125
#define GEM_CTL_STARTTX __BIT(9)
sys/dev/cadence/cemacreg.h
127
#define ETH_CTL_BP __BIT(8) /* 1 = back pressure enabled */
sys/dev/cadence/cemacreg.h
128
#define ETH_CTL_WES __BIT(7) /* 1 = statistics registers writeable */
sys/dev/cadence/cemacreg.h
129
#define ETH_CTL_ISR __BIT(6) /* 1 = increment statistics registers */
sys/dev/cadence/cemacreg.h
130
#define ETH_CTL_CSR __BIT(5) /* 1 = clear statistics registers */
sys/dev/cadence/cemacreg.h
131
#define ETH_CTL_MPE __BIT(4) /* 1 = management port enabled */
sys/dev/cadence/cemacreg.h
132
#define ETH_CTL_TE __BIT(3) /* 1 = transmit enable */
sys/dev/cadence/cemacreg.h
133
#define ETH_CTL_RE __BIT(2) /* 1 = receive enable */
sys/dev/cadence/cemacreg.h
134
#define ETH_CTL_LBL __BIT(1) /* 1 = local loopback enabled */
sys/dev/cadence/cemacreg.h
135
#define ETH_CTL_LB __BIT(0) /* 1 = loopback signal is at high level */
sys/dev/cadence/cemacreg.h
139
#define ETH_CFG_RMII __BIT(13) /* 1 = enable RMII (Reduce MII) (AT91RM9200 only) */
sys/dev/cadence/cemacreg.h
140
#define ETH_CFG_RTY __BIT(12) /* 1 = retry test enabled */
sys/dev/cadence/cemacreg.h
146
#define ETH_CFG_EAE __BIT(9) /* 1 = external address match enable */
sys/dev/cadence/cemacreg.h
147
#define ETH_CFG_BIG __BIT(8) /* 1 = receive up to 1522 bytes (VLAN) */
sys/dev/cadence/cemacreg.h
148
#define ETH_CFG_UNI __BIT(7) /* 1 = enable unicast hash */
sys/dev/cadence/cemacreg.h
149
#define ETH_CFG_MTI __BIT(6) /* 1 = enable multicast hash */
sys/dev/cadence/cemacreg.h
150
#define ETH_CFG_NBC __BIT(5) /* 1 = ignore received broadcasts */
sys/dev/cadence/cemacreg.h
151
#define ETH_CFG_CAF __BIT(4) /* 1 = receive all valid frames */
sys/dev/cadence/cemacreg.h
152
#define ETH_CFG_BR __BIT(2)
sys/dev/cadence/cemacreg.h
153
#define ETH_CFG_FD __BIT(1) /* 1 = force full duplex */
sys/dev/cadence/cemacreg.h
154
#define ETH_CFG_SPD __BIT(0) /* 1 = 100 Mbps */
sys/dev/cadence/cemacreg.h
156
#define GEM_CFG_GEN __BIT(10)
sys/dev/cadence/cemacreg.h
170
#define GEM_CFG_RXCOEN __BIT(24)
sys/dev/cadence/cemacreg.h
173
#define ETH_SR_IDLE __BIT(2) /* 1 = PHY logic is running */
sys/dev/cadence/cemacreg.h
174
#define ETH_SR_MDIO __BIT(1) /* 1 = MDIO pin set */
sys/dev/cadence/cemacreg.h
175
#define ETH_SR_LINK __BIT(0)
sys/dev/cadence/cemacreg.h
184
#define ETH_TSR_UND __BIT(6) /* 1 = transmit underrun detected */
sys/dev/cadence/cemacreg.h
185
#define ETH_TSR_COMP __BIT(5) /* 1 = transmit complete */
sys/dev/cadence/cemacreg.h
186
#define ETH_TSR_BNQ __BIT(4) /* 1 = transmit buffer not queued (at91rm9200 only) */
sys/dev/cadence/cemacreg.h
187
#define ETH_TSR_IDLE __BIT(3) /* 1 = transmitter idle */
sys/dev/cadence/cemacreg.h
188
#define ETH_TSR_RLE __BIT(2) /* 1 = retry limit exceeded */
sys/dev/cadence/cemacreg.h
189
#define ETH_TSR_COL __BIT(1) /* 1 = collision occurred */
sys/dev/cadence/cemacreg.h
190
#define ETH_TSR_OVR __BIT(0) /* 1 = transmit buffer overrun */
sys/dev/cadence/cemacreg.h
192
#define GEM_TSR_TXGO __BIT(3)
sys/dev/cadence/cemacreg.h
195
#define ETH_RSR_OVR __BIT(2) /* 1 = RX overrun */
sys/dev/cadence/cemacreg.h
196
#define ETH_RSR_REC __BIT(1) /* 1 = frame received */
sys/dev/cadence/cemacreg.h
197
#define ETH_RSR_BNA __BIT(0) /* 1 = buffer not available */
sys/dev/cadence/cemacreg.h
201
#define ETH_ISR_ABT __BIT(11) /* 1 = abort during DMA transfer */
sys/dev/cadence/cemacreg.h
202
#define ETH_ISR_ROVR __BIT(10) /* 1 = RX overrun */
sys/dev/cadence/cemacreg.h
203
#define ETH_ISR_LINK __BIT(9) /* 1 = link pin changed */
sys/dev/cadence/cemacreg.h
204
#define ETH_ISR_TIDLE __BIT(8) /* 1 = transmitter idle */
sys/dev/cadence/cemacreg.h
205
#define ETH_ISR_TCOM __BIT(7) /* 1 = transmit complete */
sys/dev/cadence/cemacreg.h
206
#define ETH_ISR_TBRE __BIT(6) /* 1 = transmit buffer register empty */
sys/dev/cadence/cemacreg.h
207
#define ETH_ISR_RTRY __BIT(5) /* 1 = retry limit exceeded */
sys/dev/cadence/cemacreg.h
208
#define ETH_ISR_TUND __BIT(4) /* 1 = transmit buffer underrun */
sys/dev/cadence/cemacreg.h
209
#define ETH_ISR_TOVR __BIT(3) /* 1 = transmit buffer overrun */
sys/dev/cadence/cemacreg.h
210
#define ETH_ISR_RBNA __BIT(2) /* 1 = receive buffer not available */
sys/dev/cadence/cemacreg.h
211
#define ETH_ISR_RCOM __BIT(1) /* 1 = receive complete */
sys/dev/cadence/cemacreg.h
212
#define ETH_ISR_DONE __BIT(0) /* 1 = management done */
sys/dev/cadence/cemacreg.h
216
#define ETH_MAN_LOW __BIT(31) /* must not be set */
sys/dev/cadence/cemacreg.h
217
#define ETH_MAN_HIGH __BIT(30) /* must be set for clause 22 */
sys/dev/cadence/cemacreg.h
246
#define ETH_RDSC_F_WRAP __BIT(1)
sys/dev/cadence/cemacreg.h
247
#define ETH_RDSC_F_USED __BIT(0)
sys/dev/cadence/cemacreg.h
250
#define ETH_RDSC_I_BCAST __BIT(31)
sys/dev/cadence/cemacreg.h
251
#define ETH_RDSC_I_MULTICAST __BIT(30)
sys/dev/cadence/cemacreg.h
252
#define ETH_RDSC_I_UNICAST __BIT(29)
sys/dev/cadence/cemacreg.h
253
#define ETH_RDSC_I_VLAN __BIT(28)
sys/dev/cadence/cemacreg.h
254
#define ETH_RDSC_I_UNKNOWN_SRC __BIT(27)
sys/dev/cadence/cemacreg.h
255
#define ETH_RDSC_I_MATCH1 __BIT(26)
sys/dev/cadence/cemacreg.h
256
#define ETH_RDSC_I_MATCH2 __BIT(25)
sys/dev/cadence/cemacreg.h
257
#define ETH_RDSC_I_MATCH3 __BIT(24)
sys/dev/cadence/cemacreg.h
258
#define ETH_RDSC_I_MATCH4 __BIT(23)
sys/dev/cadence/cemacreg.h
266
#define ETH_TDSC_I_USED __BIT(31) /* done transmitting */
sys/dev/cadence/cemacreg.h
267
#define ETH_TDSC_I_WRAP __BIT(30) /* end of descr ring */
sys/dev/cadence/cemacreg.h
268
#define ETH_TDSC_I_RETRY_ERR __BIT(29)
sys/dev/cadence/cemacreg.h
269
#define ETH_TDSC_I_AHB_ERR __BIT(27)
sys/dev/cadence/cemacreg.h
270
#define ETH_TDSC_I_LATE_COLL __BIT(26)
sys/dev/cadence/cemacreg.h
280
#define ETH_TDSC_I_NO_CRC_APPENDED __BIT(16)
sys/dev/cadence/cemacreg.h
281
#define ETH_TDSC_I_LAST_BUF __BIT(15) /* last buf in frame */
sys/dev/cadence/cemacreg.h
94
#define GEM_DMA_CFG_DISC_WHEN_NO_AHB __BIT(24)
sys/dev/cadence/cemacreg.h
96
#define GEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN __BIT(11)
sys/dev/cadence/cemacreg.h
97
#define GEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL __BIT(10)
sys/dev/cadence/cemacreg.h
99
#define GEM_DMA_CFG_AHB_ENDIAN_SWAP_PKT_EN __BIT(7)
sys/dev/cadence/if_cemacvar.h
74
#define CEMAC_FLAG_GEM __BIT(0)
sys/dev/dkvar.h
86
#define DK_DUMP_RECURSIVE __BIT(0) /* this is a virtual disk */
sys/dev/fdt/arasan_sdhc_fdt.c
50
#define RK3399_CORECFG_TIMEOUTCLKUNIT __BIT(7)
sys/dev/fdt/cdns3_fdt.c
66
#define OTG_CMD_HOST_BUS_REQ __BIT(1)
sys/dev/fdt/cdns3_fdt.c
67
#define OTG_CMD_OTG_DIS __BIT(3)
sys/dev/fdt/cdns3_fdt.c
69
#define OTG_STS_XHCI_READY __BIT(26)
sys/dev/fdt/dwc3_fdt.c
53
#define GCTL_CORESOFTRESET __BIT(11)
sys/dev/fdt/dwc3_fdt.c
56
#define GUCTL1_TX_IPGAP_LINECHECK_DIS __BIT(28)
sys/dev/fdt/dwc3_fdt.c
62
#define GUSB2PHYCFG_PHYSOFTRST __BIT(31)
sys/dev/fdt/dwc3_fdt.c
63
#define GUSB2PHYCFG_U2_FREECLK_EXISTS __BIT(30)
sys/dev/fdt/dwc3_fdt.c
65
#define GUSB2PHYCFG_SUSPHY __BIT(6)
sys/dev/fdt/dwc3_fdt.c
66
#define GUSB2PHYCFG_PHYIF __BIT(3)
sys/dev/fdt/dwc3_fdt.c
67
#define GUSB2PHYCFG_ENBLSLPM __BIT(0)
sys/dev/fdt/dwc3_fdt.c
70
#define GUSB3PIPECTL_PHYSOFTRST __BIT(31)
sys/dev/fdt/dwc3_fdt.c
71
#define GUSB3PIPECTL_UX_EXIT_PX __BIT(27)
sys/dev/fdt/dwc3_fdt.c
72
#define GUSB3PIPECTL_DEPOCHANGE __BIT(18)
sys/dev/fdt/dwc3_fdt.c
73
#define GUSB3PIPECTL_SUSPHY __BIT(17)
sys/dev/fdt/dwcmmc_fdt.c
66
.intr_cardmask = __BIT(24),
sys/dev/fdt/fdt_intr.h
35
#define FDT_INTR_MPSAFE __BIT(0)
sys/dev/fdt/fdt_intr.h
38
#define FDT_INTR_TYPE_POS_EDGE __BIT(0)
sys/dev/fdt/fdt_intr.h
39
#define FDT_INTR_TYPE_NEG_EDGE __BIT(1)
sys/dev/fdt/fdt_intr.h
42
#define FDT_INTR_TYPE_HIGH_LEVEL __BIT(2)
sys/dev/fdt/fdt_intr.h
43
#define FDT_INTR_TYPE_LOW_LEVEL __BIT(3)
sys/dev/fdt/fdtvar.h
78
#define FDT_BUS_SPACE_FLAG_NONPOSTED_MMIO __BIT(0)
sys/dev/fdt/pinctrl_single.c
40
#define PINCTRL_FLAG_PINCONF __BIT(0) /* supports generic pinconf */
sys/dev/fdt/pl061gpio_fdt.c
135
if ((cnf & __BIT(pin)) != 0)
sys/dev/fdt/pl061gpio_fdt.c
136
PLGPIO_WRITE(sc, PL061_GPIOAFSEL_REG, cnf & ~__BIT(pin));
sys/dev/hdaudio/hdafg.c
4507
#define HDAFG_ANALOG_BEEP_EN __BIT(5)
sys/dev/hdaudio/hdaudiovar.h
149
#define HDAUDIO_FLAG_32BIT __BIT(0)
sys/dev/hyperv/hvkbd.c
88
#define RESP_STATUS_ACCEPTED __BIT(0)
sys/dev/hyperv/hvkbd.c
95
#define KS_INFO_UNICODE __BIT(0)
sys/dev/hyperv/hvkbd.c
96
#define KS_INFO_BREAK __BIT(1)
sys/dev/hyperv/hvkbd.c
97
#define KS_INFO_E0 __BIT(2)
sys/dev/hyperv/hvkbd.c
98
#define KS_INFO_E1 __BIT(3)
sys/dev/hyperv/if_hvn.c
147
#define HVN_RNDIS_CMD_NORESP __BIT(0)
sys/dev/hyperv/if_hvn.c
149
#define HVN_NVS_CMD_NORESP __BIT(0)
sys/dev/hyperv/if_hvn.c
181
#define HVN_TXD_FLAG_ONAGG __BIT(0)
sys/dev/hyperv/if_hvn.c
182
#define HVN_TXD_FLAG_DMAMAP __BIT(1)
sys/dev/hyperv/if_hvn.c
205
#define HVN_TXR_FLAG_UDP_HASH __BIT(0)
sys/dev/hyperv/if_hvn.c
2137
SET(sc->sc_chim_bmap[i], __BIT(idx));
sys/dev/hyperv/if_hvn.c
2154
mask = __BIT(chim_idx % LONG_BIT);
sys/dev/hyperv/if_hvn.c
267
#define HVN_RXR_FLAG_UDP_HASH __BIT(0)
sys/dev/hyperv/if_hvn.c
304
#define HVN_LINK_EV_STATE_CHANGE __BIT(0)
sys/dev/hyperv/if_hvn.c
305
#define HVN_LINK_EV_NETWORK_CHANGE_TMOUT __BIT(1)
sys/dev/hyperv/if_hvn.c
306
#define HVN_LINK_EV_NETWORK_CHANGE __BIT(2)
sys/dev/hyperv/if_hvn.c
307
#define HVN_LINK_EV_RESUME_NETWORK __BIT(3)
sys/dev/hyperv/if_hvn.c
308
#define HVN_LINK_EV_EXIT_THREAD __BIT(4)
sys/dev/hyperv/if_hvn.c
322
#define HVN_CAPS_VLAN __BIT(0)
sys/dev/hyperv/if_hvn.c
323
#define HVN_CAPS_MTU __BIT(1)
sys/dev/hyperv/if_hvn.c
324
#define HVN_CAPS_IPCS __BIT(2)
sys/dev/hyperv/if_hvn.c
325
#define HVN_CAPS_TCP4CS __BIT(3)
sys/dev/hyperv/if_hvn.c
326
#define HVN_CAPS_TCP6CS __BIT(4)
sys/dev/hyperv/if_hvn.c
327
#define HVN_CAPS_UDP4CS __BIT(5)
sys/dev/hyperv/if_hvn.c
328
#define HVN_CAPS_UDP6CS __BIT(6)
sys/dev/hyperv/if_hvn.c
329
#define HVN_CAPS_TSO4 __BIT(7)
sys/dev/hyperv/if_hvn.c
330
#define HVN_CAPS_TSO6 __BIT(8)
sys/dev/hyperv/if_hvn.c
331
#define HVN_CAPS_HASHVAL __BIT(9)
sys/dev/hyperv/if_hvn.c
332
#define HVN_CAPS_UDPHASH __BIT(10)
sys/dev/hyperv/if_hvn.c
335
#define HVN_SCF_ATTACHED __BIT(0)
sys/dev/hyperv/if_hvn.c
336
#define HVN_SCF_RXBUF_CONNECTED __BIT(1)
sys/dev/hyperv/if_hvn.c
337
#define HVN_SCF_CHIM_CONNECTED __BIT(2)
sys/dev/hyperv/if_hvn.c
338
#define HVN_SCF_REVOKED __BIT(3)
sys/dev/hyperv/if_hvn.c
339
#define HVN_SCF_HAS_RSSKEY __BIT(4)
sys/dev/hyperv/if_hvn.c
340
#define HVN_SCF_HAS_RSSIND __BIT(5)
sys/dev/hyperv/if_hvn.c
3526
#define HVN_HANDLE_RING_DOTX __BIT(0)
sys/dev/hyperv/if_hvn.c
4085
sc->sc_rndis_agg_align = __BIT(cmp->rm_align);
sys/dev/hyperv/if_hvn.c
4702
#define HVN_RXINFO_CSUM __BIT(NDIS_PKTINFO_TYPE_CSUM)
sys/dev/hyperv/if_hvn.c
4703
#define HVN_RXINFO_VLAN __BIT(NDIS_PKTINFO_TYPE_VLAN)
sys/dev/hyperv/if_hvn.c
4704
#define HVN_RXINFO_HASHVAL __BIT(HVN_NDIS_PKTINFO_TYPE_HASHVAL)
sys/dev/hyperv/if_hvn.c
4705
#define HVN_RXINFO_HASHINFO __BIT(HVN_NDIS_PKTINFO_TYPE_HASHINF)
sys/dev/hyperv/vmbus.c
1993
__BIT(ch->ch_id % VMBUS_EVTFLAG_LEN));
sys/dev/hyperv/vmbus.c
2003
~__BIT(ch->ch_id % VMBUS_EVTFLAG_LEN));
sys/dev/hyperv/vmbusvar.h
128
#define CHF_BATCHED __BIT(0)
sys/dev/hyperv/vmbusvar.h
129
#define CHF_MONITOR __BIT(1)
sys/dev/hyperv/vmbusvar.h
130
#define CHF_REVOKED __BIT(2)
sys/dev/hyperv/vmbusvar.h
191
#define VMBUS_SCFLAG_SYNIC __BIT(0)
sys/dev/hyperv/vmbusvar.h
192
#define VMBUS_SCFLAG_CONNECTED __BIT(1)
sys/dev/hyperv/vmbusvar.h
193
#define VMBUS_SCFLAG_OFFERS_DELIVERED __BIT(2)
sys/dev/hyperv/vmbusvar.h
51
#define MSGF_NOSLEEP __BIT(0)
sys/dev/hyperv/vmbusvar.h
52
#define MSGF_NOQUEUE __BIT(1)
sys/dev/hyperv/vmbusvar.h
53
#define MSGF_ORPHANED __BIT(2)
sys/dev/i2c/ac100.c
91
#define AC100_RTC_CTRL_12H_24H_MODE __BIT(0)
sys/dev/i2c/ac100.c
93
#define AC100_RTC_UPD_TRIG_WRITE __BIT(15)
sys/dev/i2c/act8846.c
68
#define ACT_DCDC_CTRL_ON __BIT(7)
sys/dev/i2c/act8846.c
70
#define ACT_LDO_CTRL_ON __BIT(7)
sys/dev/i2c/anxedp.c
65
#define ANX_ADDR_ONLY __BIT(1)
sys/dev/i2c/anxedp.c
66
#define ANX_AUX_EN __BIT(0)
sys/dev/i2c/anxedp.c
70
#define ANX_RPLY_RECEIV __BIT(1)
sys/dev/i2c/as3722.c
107
#define AS3722_FUSE7_SD0_V_MINUS_200MV __BIT(4)
sys/dev/i2c/as3722.c
63
#define AS3722_GPIO0_CTRL_INVERT __BIT(7)
sys/dev/i2c/as3722.c
73
#define AS3722_RESET_CTRL_POWER_OFF __BIT(1)
sys/dev/i2c/as3722.c
74
#define AS3722_RESET_CTRL_FORCE_RESET __BIT(0)
sys/dev/i2c/as3722.c
78
#define AS3722_WATCHDOG_CTRL_ON __BIT(0)
sys/dev/i2c/as3722.c
85
#define AS3722_WATCHDOG_SIGNAL_SW_SIG __BIT(0)
sys/dev/i2c/as3722.c
88
#define AS3722_SDCONTROL_SD4_ENABLE __BIT(4)
sys/dev/i2c/as3722.c
93
#define AS3722_RTC_CONTROL_RTC_ON __BIT(2)
sys/dev/i2c/axp20x.c
104
#define AXP_LDO3_TRACK __BIT(7)
sys/dev/i2c/axp20x.c
109
#define AXP_SHUTDOWN_CTRL __BIT(7)
sys/dev/i2c/axp20x.c
112
#define AXP_BKUP_CTRL_ENABLE __BIT(7)
sys/dev/i2c/axp20x.c
149
#define AXP_ADC_EN1_BATTV __BIT(7)
sys/dev/i2c/axp20x.c
150
#define AXP_ADC_EN1_BATTI __BIT(6)
sys/dev/i2c/axp20x.c
151
#define AXP_ADC_EN1_ACV __BIT(5)
sys/dev/i2c/axp20x.c
152
#define AXP_ADC_EN1_ACI __BIT(4)
sys/dev/i2c/axp20x.c
153
#define AXP_ADC_EN1_VBUSV __BIT(3)
sys/dev/i2c/axp20x.c
154
#define AXP_ADC_EN1_VBUSI __BIT(2)
sys/dev/i2c/axp20x.c
155
#define AXP_ADC_EN1_APSV __BIT(1)
sys/dev/i2c/axp20x.c
156
#define AXP_ADC_EN1_TS __BIT(0)
sys/dev/i2c/axp20x.c
158
#define AXP_ADC_EN2_TEMP __BIT(7)
sys/dev/i2c/axp20x.c
51
#define AXP_INPUT_STATUS_AC_PRESENT __BIT(7)
sys/dev/i2c/axp20x.c
52
#define AXP_INPUT_STATUS_AC_OK __BIT(6)
sys/dev/i2c/axp20x.c
53
#define AXP_INPUT_STATUS_VBUS_PRESENT __BIT(5)
sys/dev/i2c/axp20x.c
54
#define AXP_INPUT_STATUS_VBUS_OK __BIT(4)
sys/dev/i2c/axp20x.c
57
#define AXP_POWER_MODE_OVERTEMP __BIT(7)
sys/dev/i2c/axp20x.c
58
#define AXP_POWER_MODE_CHARGING __BIT(6)
sys/dev/i2c/axp20x.c
59
#define AXP_POWER_MODE_BATTOK __BIT(5)
sys/dev/i2c/axp20x.c
62
#define AXP_POWEROUT_CTRL_LDO3 __BIT(6)
sys/dev/i2c/axp20x.c
63
#define AXP_POWEROUT_CTRL_DCDC2 __BIT(4)
sys/dev/i2c/axp20x.c
64
#define AXP_POWEROUT_CTRL_LDO4 __BIT(3)
sys/dev/i2c/axp20x.c
65
#define AXP_POWEROUT_CTRL_LDO2 __BIT(2)
sys/dev/i2c/axp20x.c
66
#define AXP_POWEROUT_CTRL_DCDC3 __BIT(1)
sys/dev/i2c/axp20x.c
67
#define AXP_POWEROUT_CTRL_EXTEN __BIT(0)
sys/dev/i2c/axp809.c
82
GPIO1_CTRL, __BIT(0), GPIO1LDO_CTRL, __BITS(4,0)),
sys/dev/i2c/axppmic.c
101
#define AXP_BATT_COULOMB_VALID __BIT(7)
sys/dev/i2c/axppmic.c
105
(((u_int)(_hi & ~__BIT(7)) << 8) | (_lo))
sys/dev/i2c/axppmic.c
113
#define AXP_ADDR_EXT_SLAVE __BIT(4)
sys/dev/i2c/axppmic.c
176
0x12, __BIT(3), 0x15, __BITS(4,0)),
sys/dev/i2c/axppmic.c
178
0x12, __BIT(4), 0x16, __BITS(4,0)),
sys/dev/i2c/axppmic.c
180
0x12, __BIT(5), 0x17, __BITS(4,0)),
sys/dev/i2c/axppmic.c
182
0x12, __BIT(6), 0x18, __BITS(4,0)),
sys/dev/i2c/axppmic.c
184
0x12, __BIT(0), 0x19, __BITS(4,0)),
sys/dev/i2c/axppmic.c
186
0x12, __BIT(1), 0x1a, __BITS(4,0)),
sys/dev/i2c/axppmic.c
188
0x12, __BIT(2), 0x1b, __BITS(4,0)),
sys/dev/i2c/axppmic.c
190
0x13, __BIT(2), 0x1c, __BITS(3,0)),
sys/dev/i2c/axppmic.c
192
0x13, __BIT(3), 0x1d, __BITS(3,0)),
sys/dev/i2c/axppmic.c
194
0x10, __BIT(0), 0x20, __BITS(4,0)),
sys/dev/i2c/axppmic.c
196
0x10, __BIT(1), 0x21, __BITS(6,0)),
sys/dev/i2c/axppmic.c
198
0x10, __BIT(2), 0x22, __BITS(6,0)),
sys/dev/i2c/axppmic.c
200
0x10, __BIT(3), 0x23, __BITS(6,0)),
sys/dev/i2c/axppmic.c
202
0x10, __BIT(4), 0x24, __BITS(6,0)),
sys/dev/i2c/axppmic.c
204
0x10, __BIT(5), 0x25, __BITS(6,0)),
sys/dev/i2c/axppmic.c
206
0x13, __BIT(5), 0x28, __BITS(4,0)),
sys/dev/i2c/axppmic.c
208
0x13, __BIT(6), 0x29, __BITS(4,0)),
sys/dev/i2c/axppmic.c
210
0x13, __BIT(7), 0x2a, __BITS(4,0)),
sys/dev/i2c/axppmic.c
215
0x10, __BIT(0), 0x12, __BITS(6,0)),
sys/dev/i2c/axppmic.c
217
0x10, __BIT(1), 0x13, __BITS(4,0)),
sys/dev/i2c/axppmic.c
219
0x10, __BIT(2), 0x14, __BITS(6,0)),
sys/dev/i2c/axppmic.c
221
0x10, __BIT(3), 0x15, __BITS(5,0)),
sys/dev/i2c/axppmic.c
223
0x10, __BIT(4), 0x16, __BITS(4,0)),
sys/dev/i2c/axppmic.c
225
0x10, __BIT(5), 0x17, __BITS(4,0)),
sys/dev/i2c/axppmic.c
227
0x10, __BIT(6), 0x18, __BITS(4,0)),
sys/dev/i2c/axppmic.c
229
0x10, __BIT(7), 0x19, __BITS(4,0)),
sys/dev/i2c/axppmic.c
231
0x11, __BIT(0), 0x20, __BITS(3,0)),
sys/dev/i2c/axppmic.c
233
0x11, __BIT(1), 0x21, __BITS(3,0)),
sys/dev/i2c/axppmic.c
235
0x11, __BIT(2), 0x22, __BITS(3,0)),
sys/dev/i2c/axppmic.c
237
0x11, __BIT(3), 0x23, __BITS(3,0)),
sys/dev/i2c/axppmic.c
239
0x11, __BIT(4), 0x24, __BITS(4,0)),
sys/dev/i2c/axppmic.c
241
0x11, __BIT(5), 0x25, __BITS(4,0)),
sys/dev/i2c/axppmic.c
243
0x11, __BIT(6), 0x26, __BITS(4,0)),
sys/dev/i2c/axppmic.c
248
0x10, __BIT(0), 0x1c, __BITS(2,0)),
sys/dev/i2c/axppmic.c
250
0x10, __BIT(1), 0x21, __BITS(4,0)),
sys/dev/i2c/axppmic.c
252
0x10, __BIT(2), 0x22, __BITS(5,0)),
sys/dev/i2c/axppmic.c
254
0x10, __BIT(3), 0x23, __BITS(5,0)),
sys/dev/i2c/axppmic.c
256
0x10, __BIT(4), 0x24, __BITS(5,0)),
sys/dev/i2c/axppmic.c
258
0x10, __BIT(5), 0x25, __BITS(4,0)),
sys/dev/i2c/axppmic.c
260
0x10, __BIT(6), 0x28, __BITS(4,0)),
sys/dev/i2c/axppmic.c
262
0x10, __BIT(7), 0x29, __BITS(4,0)),
sys/dev/i2c/axppmic.c
264
0x12, __BIT(0), 0x19, __BITS(4,0)),
sys/dev/i2c/axppmic.c
266
0x12, __BIT(1), 0x1a, __BITS(4,0)),
sys/dev/i2c/axppmic.c
268
0x12, __BIT(2), 0x1b, __BITS(4,0)),
sys/dev/i2c/axppmic.c
270
0x12, __BIT(3), 0x15, __BITS(4,0)),
sys/dev/i2c/axppmic.c
272
0x12, __BIT(4), 0x16, __BITS(4,0)),
sys/dev/i2c/axppmic.c
274
0x12, __BIT(5), 0x2a, __BITS(4,0)),
sys/dev/i2c/axppmic.c
276
0x12, __BIT(6)),
sys/dev/i2c/axppmic.c
279
0x12, __BIT(7), 0x21, __BITS(4,0)),
sys/dev/i2c/axppmic.c
288
0x12, __BIT(3), 0x15, __BITS(4,0)),
sys/dev/i2c/axppmic.c
290
0x12, __BIT(4), 0x16, __BITS(4,0)),
sys/dev/i2c/axppmic.c
292
0x12, __BIT(5), 0x17, __BITS(4,0)),
sys/dev/i2c/axppmic.c
294
0x12, __BIT(6), 0x18, __BITS(4,0)),
sys/dev/i2c/axppmic.c
296
0x12, __BIT(0), 0x19, __BITS(4,0)),
sys/dev/i2c/axppmic.c
298
0x12, __BIT(1), 0x1a, __BITS(4,0)),
sys/dev/i2c/axppmic.c
300
0x12, __BIT(2), 0x1b, __BITS(4,0)),
sys/dev/i2c/axppmic.c
302
0x13, __BIT(2), 0x1c, __BITS(3,0)),
sys/dev/i2c/axppmic.c
304
0x13, __BIT(3), 0x1d, __BITS(3,0)),
sys/dev/i2c/axppmic.c
306
0x10, __BIT(0), 0x20, __BITS(4,0)),
sys/dev/i2c/axppmic.c
308
0x10, __BIT(1), 0x21, __BITS(6,0)),
sys/dev/i2c/axppmic.c
310
0x10, __BIT(2), 0x22, __BITS(6,0)),
sys/dev/i2c/axppmic.c
312
0x10, __BIT(3), 0x23, __BITS(6,0)),
sys/dev/i2c/axppmic.c
314
0x10, __BIT(4), 0x24, __BITS(6,0)),
sys/dev/i2c/axppmic.c
316
0x10, __BIT(5), 0x25, __BITS(6,0)),
sys/dev/i2c/axppmic.c
318
0x10, __BIT(6), 0x26, __BITS(6,0)),
sys/dev/i2c/axppmic.c
320
0x13, __BIT(5), 0x28, __BITS(4,0)),
sys/dev/i2c/axppmic.c
322
0x13, __BIT(6), 0x29, __BITS(4,0)),
sys/dev/i2c/axppmic.c
324
0x13, __BIT(7), 0x2a, __BITS(4,0)),
sys/dev/i2c/axppmic.c
330
0x10, __BIT(0)),
sys/dev/i2c/axppmic.c
335
0x10, __BIT(1)),
sys/dev/i2c/axppmic.c
340
0x10, __BIT(2)),
sys/dev/i2c/axppmic.c
345
0x10, __BIT(3)),
sys/dev/i2c/axppmic.c
352
0x10, __BIT(4)),
sys/dev/i2c/axppmic.c
355
0x10, __BIT(5)),
sys/dev/i2c/axppmic.c
358
0x11, __BIT(0)),
sys/dev/i2c/axppmic.c
361
0x11, __BIT(1)),
sys/dev/i2c/axppmic.c
364
0x11, __BIT(2)),
sys/dev/i2c/axppmic.c
367
0x11, __BIT(3)),
sys/dev/i2c/axppmic.c
370
0x11, __BIT(4)),
sys/dev/i2c/axppmic.c
373
0x11, __BIT(5)),
sys/dev/i2c/axppmic.c
376
0x11, __BIT(6)),
sys/dev/i2c/axppmic.c
379
0x11, __BIT(7)),
sys/dev/i2c/axppmic.c
382
0x12, __BIT(0)),
sys/dev/i2c/axppmic.c
385
0x12, __BIT(1)),
sys/dev/i2c/axppmic.c
388
0x12, __BIT(2)),
sys/dev/i2c/axppmic.c
391
0x12, __BIT(3)),
sys/dev/i2c/axppmic.c
394
0x12, __BIT(4)),
sys/dev/i2c/axppmic.c
397
0x12, __BIT(5)),
sys/dev/i2c/axppmic.c
400
0x12, __BIT(6)),
sys/dev/i2c/axppmic.c
49
#define AXP_POWER_SOURCE_ACIN_PRESENT __BIT(7)
sys/dev/i2c/axppmic.c
50
#define AXP_POWER_SOURCE_VBUS_PRESENT __BIT(5)
sys/dev/i2c/axppmic.c
51
#define AXP_POWER_SOURCE_CHARGE_DIRECTION __BIT(2)
sys/dev/i2c/axppmic.c
510
.poklirq = AXPPMIC_IRQ(5, __BIT(3)),
sys/dev/i2c/axppmic.c
523
.poklirq = AXPPMIC_IRQ(2, __BIT(0)),
sys/dev/i2c/axppmic.c
532
.poklirq = AXPPMIC_IRQ(2, __BIT(0)),
sys/dev/i2c/axppmic.c
54
#define AXP_POWER_MODE_BATT_VALID __BIT(4)
sys/dev/i2c/axppmic.c
55
#define AXP_POWER_MODE_BATT_PRESENT __BIT(5)
sys/dev/i2c/axppmic.c
557
.poklirq = AXPPMIC_IRQ(5, __BIT(3)),
sys/dev/i2c/axppmic.c
56
#define AXP_POWER_MODE_BATT_CHARGING __BIT(6)
sys/dev/i2c/axppmic.c
61
#define AXP_POWER_DISABLE_CTRL __BIT(7)
sys/dev/i2c/axppmic.c
64
#define AXP_IRQ1_ACIN_RAISE __BIT(6)
sys/dev/i2c/axppmic.c
65
#define AXP_IRQ1_ACIN_LOWER __BIT(5)
sys/dev/i2c/axppmic.c
66
#define AXP_IRQ1_VBUS_RAISE __BIT(3)
sys/dev/i2c/axppmic.c
67
#define AXP_IRQ1_VBUS_LOWER __BIT(2)
sys/dev/i2c/axppmic.c
769
const uint8_t data_mask = __BIT(gpin->pin_nr);
sys/dev/i2c/axppmic.c
90
#define AXP_FUEL_GAUGE_CTRL_EN __BIT(7)
sys/dev/i2c/axppmic.c
93
#define AXP_BATT_CAP_VALID __BIT(7)
sys/dev/i2c/axppmic.c
97
#define AXP_BATT_MAX_CAP_VALID __BIT(7)
sys/dev/i2c/cwfg.c
55
#define RTT_ALRT __BIT(7)
sys/dev/i2c/cwfg.c
61
#define CONFIG_UFG __BIT(1)
sys/dev/i2c/es8316ac.c
49
#define RESET_CSM_ON __BIT(7)
sys/dev/i2c/es8316ac.c
51
#define CLKMAN1_MCLK_ON __BIT(6)
sys/dev/i2c/es8316ac.c
52
#define CLKMAN1_BCLK_ON __BIT(5)
sys/dev/i2c/es8316ac.c
53
#define CLKMAN1_CLK_CP_ON __BIT(4)
sys/dev/i2c/es8316ac.c
54
#define CLKMAN1_CLK_DAC_ON __BIT(2)
sys/dev/i2c/es8316ac.c
55
#define CLKMAN1_ANACLK_DAC_ON __BIT(0)
sys/dev/i2c/es8316ac.c
58
#define SD_CLK_MSC __BIT(7)
sys/dev/i2c/es8316ac.c
59
#define SD_CLK_BCLK_INV __BIT(5)
sys/dev/i2c/es8316ac.c
62
#define SD_FMT_LRP __BIT(5)
sys/dev/i2c/es8316ac.c
71
#define HPMIXRT_LD2LHPMIX __BIT(7)
sys/dev/i2c/es8316ac.c
72
#define HPMIXRT_RD2RHPMIX __BIT(3)
sys/dev/i2c/es8316ac.c
74
#define HPMIX_LHPMIX_MUTE __BIT(5)
sys/dev/i2c/es8316ac.c
75
#define HPMIX_PDN_LHP_MIX __BIT(4)
sys/dev/i2c/es8316ac.c
76
#define HPMIX_RHPMIX_MUTE __BIT(1)
sys/dev/i2c/es8316ac.c
77
#define HPMIX_PDN_RHP_MIX __BIT(0)
sys/dev/i2c/es8316ac.c
82
#define HPOUTEN_EN_HPL __BIT(6)
sys/dev/i2c/es8316ac.c
83
#define HPOUTEN_HPL_OUTEN __BIT(5)
sys/dev/i2c/es8316ac.c
84
#define HPOUTEN_EN_HPR __BIT(2)
sys/dev/i2c/es8316ac.c
85
#define HPOUTEN_HPR_OUTEN __BIT(1)
sys/dev/i2c/es8316ac.c
87
#define HPVOL_PDN_LICAL __BIT(7)
sys/dev/i2c/es8316ac.c
89
#define HPVOL_PDN_RICAL __BIT(3)
sys/dev/i2c/es8316ac.c
92
#define HPPWR_PDN_CPHP __BIT(2)
sys/dev/i2c/es8316ac.c
94
#define CPPWR_PDN_CP __BIT(5)
sys/dev/i2c/es8316ac.c
96
#define DACPWR_PDN_DAC_L __BIT(4)
sys/dev/i2c/es8316ac.c
97
#define DACPWR_PDN_DAC_R __BIT(0)
sys/dev/i2c/es8316ac.c
99
#define DACCTL1_MUTE __BIT(5)
sys/dev/i2c/fan53555.c
46
#define VSEL_BUCK_EN __BIT(7)
sys/dev/i2c/fan53555.c
47
#define VSEL_MODE __BIT(6)
sys/dev/i2c/fan53555.c
50
#define CONTROL_OUTPUT_DISCHARGE __BIT(7)
sys/dev/i2c/fan53555.c
52
#define CONTROL_RESET __BIT(2)
sys/dev/i2c/fan53555.c
61
#define MONITOR_PGOOD __BIT(7)
sys/dev/i2c/i2c.c
125
#define ID_F_DIRECT __BIT(0)
sys/dev/i2c/i2c.c
126
#define ID_F_BUSY __BIT(1)
sys/dev/i2c/i2c.c
127
#define ID_F_WAIT_BUSY __BIT(2)
sys/dev/i2c/i2cvar.h
48
#define I2C_F_READ __BIT(0) /* new transfer is a read */
sys/dev/i2c/i2cvar.h
49
#define I2C_F_LAST __BIT(1) /* last byte of read */
sys/dev/i2c/i2cvar.h
50
#define I2C_F_STOP __BIT(2) /* send stop after byte */
sys/dev/i2c/i2cvar.h
51
#define I2C_F_POLL __BIT(3) /* poll, don't sleep */
sys/dev/i2c/i2cvar.h
52
#define I2C_F_PEC __BIT(4) /* smbus packet error checking */
sys/dev/i2c/m41st84.c
65
#define STRTC_F_HAS_WDOG __BIT(0) /* watchdog register present */
sys/dev/i2c/m41st84.c
66
#define STRTC_F_YEAR_2000 __BIT(1) /* year epoch is 2000, not 1970 */
sys/dev/i2c/m41st84.c
67
#define STRTC_F_OSC_FAIL_OF __BIT(2) /* M41T6x: OF flag, no HT bit */
sys/dev/i2c/max77620.c
153
const bool actlo = (be32toh(gpio[2]) & __BIT(0)) != 0;
sys/dev/i2c/max77620.c
154
const bool pushpull = (be32toh(gpio[2]) & __BIT(1)) == 0;
sys/dev/i2c/max77620.c
155
const bool opendrain = (be32toh(gpio[2]) & __BIT(2)) != 0;
sys/dev/i2c/max77620.c
49
#define MAX_GPIO_OUTPUT_VAL __BIT(3)
sys/dev/i2c/max77620.c
50
#define MAX_GPIO_INPUT_VAL __BIT(2)
sys/dev/i2c/max77620.c
51
#define MAX_GPIO_DIR __BIT(1)
sys/dev/i2c/max77620.c
52
#define MAX_GPIO_DRV __BIT(0)
sys/dev/i2c/mcp980xreg.h
40
#define MCP980X_AMBIENT_TEMP_00625DEGREE __BIT(4)
sys/dev/i2c/mcp980xreg.h
41
#define MCP980X_AMBIENT_TEMP_0125DEGREE __BIT(5)
sys/dev/i2c/mcp980xreg.h
42
#define MCP980X_AMBIENT_TEMP_025DEGREE __BIT(6)
sys/dev/i2c/mcp980xreg.h
43
#define MCP980X_AMBIENT_TEMP_05DEGREE __BIT(7)
sys/dev/i2c/mcp980xreg.h
46
#define MCP980X_AMBIENT_TEMP_SIGN __BIT(15)
sys/dev/i2c/motoi2cvar.h
56
#define MOTOI2C_F_ENABLE_INV __BIT(0)
sys/dev/i2c/motoi2cvar.h
57
#define MOTOI2C_F_STATUS_W1C __BIT(1)
sys/dev/i2c/pcai2cmux.c
100
.enable_bit = __BIT(3),
sys/dev/i2c/pcai2cmux.c
80
.enable_bit = __BIT(2),
sys/dev/i2c/pcai2cmux.c
90
.enable_bit = __BIT(2),
sys/dev/i2c/rkpmic.c
102
.enable_reg = 0x23, .enable_mask = __BIT(0),
sys/dev/i2c/rkpmic.c
106
.enable_reg = 0x23, .enable_mask = __BIT(1),
sys/dev/i2c/rkpmic.c
110
.enable_reg = 0x23, .enable_mask = __BIT(2) },
sys/dev/i2c/rkpmic.c
112
.enable_reg = 0x23, .enable_mask = __BIT(3),
sys/dev/i2c/rkpmic.c
118
.enable_reg = 0x27, .enable_mask = __BIT(0),
sys/dev/i2c/rkpmic.c
122
.enable_reg = 0x27, .enable_mask = __BIT(1),
sys/dev/i2c/rkpmic.c
126
.enable_reg = 0x27, .enable_mask = __BIT(2),
sys/dev/i2c/rkpmic.c
140
.enable_reg = 0x23, .enable_mask = __BIT(0),
sys/dev/i2c/rkpmic.c
144
.enable_reg = 0x23, .enable_mask = __BIT(1),
sys/dev/i2c/rkpmic.c
148
.enable_reg = 0x23, .enable_mask = __BIT(2) },
sys/dev/i2c/rkpmic.c
150
.enable_reg = 0x23, .enable_mask = __BIT(3),
sys/dev/i2c/rkpmic.c
156
.enable_reg = 0x24, .enable_mask = __BIT(0),
sys/dev/i2c/rkpmic.c
160
.enable_reg = 0x24, .enable_mask = __BIT(1),
sys/dev/i2c/rkpmic.c
164
.enable_reg = 0x24, .enable_mask = __BIT(2),
sys/dev/i2c/rkpmic.c
168
.enable_reg = 0x24, .enable_mask = __BIT(3),
sys/dev/i2c/rkpmic.c
172
.enable_reg = 0x24, .enable_mask = __BIT(4),
sys/dev/i2c/rkpmic.c
176
.enable_reg = 0x24, .enable_mask = __BIT(5),
sys/dev/i2c/rkpmic.c
180
.enable_reg = 0x24, .enable_mask = __BIT(6),
sys/dev/i2c/rkpmic.c
184
.enable_reg = 0x24, .enable_mask = __BIT(7),
sys/dev/i2c/rkpmic.c
190
.enable_reg = 0x23, .enable_mask = __BIT(5) },
sys/dev/i2c/rkpmic.c
192
.enable_reg = 0x23, .enable_mask = __BIT(6) },
sys/dev/i2c/rkpmic.c
57
#define RTC_CTRL_READSEL __BIT(7)
sys/dev/i2c/rkpmic.c
58
#define RTC_CTRL_GET_TIME __BIT(6)
sys/dev/i2c/rkpmic.c
59
#define RTC_CTRL_SET_32_COUNTER __BIT(5)
sys/dev/i2c/rkpmic.c
60
#define RTC_CTRL_TEST_MODE __BIT(4)
sys/dev/i2c/rkpmic.c
61
#define RTC_CTRL_AMPM_MODE __BIT(3)
sys/dev/i2c/rkpmic.c
62
#define RTC_CTRL_AUTO_COMP __BIT(2)
sys/dev/i2c/rkpmic.c
63
#define RTC_CTRL_ROUND_30S __BIT(1)
sys/dev/i2c/rkpmic.c
64
#define RTC_CTRL_STOP_RTC __BIT(0)
sys/dev/i2c/rkpmic.c
73
#define CLK32OUT_CLKOUT2_EN __BIT(0)
sys/dev/i2c/rkpmic.c
76
#define DEVCTRL_DEV_OFF_RST __BIT(3)
sys/dev/i2c/sy8106a.c
45
#define SEL_GO __BIT(7)
sys/dev/i2c/sy8106a.c
50
#define COM_DISABLE __BIT(0)
sys/dev/i2c/tcagpio.c
147
const bool actlo = (be32toh(gpio[2]) & __BIT(0)) != 0;
sys/dev/i2c/tcagpio.c
46
#define PORT_BIT(pin) __BIT(pin % 8)
sys/dev/i2c/tcakp.c
59
#define CFG_AI __BIT(7)
sys/dev/i2c/tcakp.c
60
#define CFG_GPI_E_CFG __BIT(6)
sys/dev/i2c/tcakp.c
61
#define CFG_OVR_FLOW_M __BIT(5)
sys/dev/i2c/tcakp.c
62
#define CFG_INT_CFG __BIT(4)
sys/dev/i2c/tcakp.c
63
#define CFG_OVR_FLOW_IEN __BIT(3)
sys/dev/i2c/tcakp.c
64
#define CFG_K_LCK_IEN __BIT(2)
sys/dev/i2c/tcakp.c
65
#define CFG_GPI_IEN __BIT(1)
sys/dev/i2c/tcakp.c
66
#define CFG_KE_IEN __BIT(0)
sys/dev/i2c/tcakp.c
68
#define INT_STAT_CAD_INT __BIT(4)
sys/dev/i2c/tcakp.c
69
#define INT_STAT_OVR_FLOW_INT __BIT(3)
sys/dev/i2c/tcakp.c
70
#define INT_STAT_K_LCD_INT __BIT(2)
sys/dev/i2c/tcakp.c
71
#define INT_STAT_GPI_INT __BIT(1)
sys/dev/i2c/tcakp.c
72
#define INT_STAT_K_INT __BIT(0)
sys/dev/i2c/tcakp.c
74
#define KEY_LCK_EC_K_LCK_EN __BIT(6)
sys/dev/i2c/tcakp.c
75
#define KEY_LCK_EC_LCK2 __BIT(5)
sys/dev/i2c/tcakp.c
76
#define KEY_LCK_EC_LCK1 __BIT(4)
sys/dev/i2c/tcakp.c
79
#define TCA_EVENT_STATE __BIT(7)
sys/dev/i2c/tda19988.c
221
#define RXSHPDLEV_HPD __BIT(1)
sys/dev/i2c/tps65217pmicreg.h
112
#define TPS65217PMIC_DEFX_TRACKING __BIT(6)
sys/dev/i2c/tps65217pmicreg.h
113
#define TPS65217PMIC_DEFX_XADJ __BIT(7)
sys/dev/i2c/tps65217pmicreg.h
114
#define TPS65217PMIC_DEFX_LS __BIT(5)
sys/dev/i2c/tps65217pmicreg.h
117
#define TPS65217PMIC_ENABLE_LDO2 __BIT(0)
sys/dev/i2c/tps65217pmicreg.h
118
#define TPS65217PMIC_ENABLE_LDO1 __BIT(1)
sys/dev/i2c/tps65217pmicreg.h
119
#define TPS65217PMIC_ENABLE_DCDC3 __BIT(2)
sys/dev/i2c/tps65217pmicreg.h
120
#define TPS65217PMIC_ENABLE_DCDC2 __BIT(3)
sys/dev/i2c/tps65217pmicreg.h
121
#define TPS65217PMIC_ENABLE_DCDC1 __BIT(4)
sys/dev/i2c/tps65217pmicreg.h
122
#define TPS65217PMIC_ENABLE_LDO4 __BIT(5)
sys/dev/i2c/tps65217pmicreg.h
123
#define TPS65217PMIC_ENABLE_LDO3 __BIT(6)
sys/dev/i2c/tps65217pmicreg.h
59
#define TPS65217PMIC_PPATH_USB_EN __BIT(4)
sys/dev/i2c/tps65217pmicreg.h
60
#define TPS65217PMIC_PPATH_AC_EN __BIT(5)
sys/dev/i2c/tps65217pmicreg.h
63
#define TPS65217PMIC_INT_USBI __BIT(0)
sys/dev/i2c/tps65217pmicreg.h
64
#define TPS65217PMIC_INT_ACI __BIT(1)
sys/dev/i2c/tps65217pmicreg.h
65
#define TPS65217PMIC_INT_PBI __BIT(2)
sys/dev/i2c/tps65217pmicreg.h
66
#define TPS65217PMIC_INT_USBM __BIT(4)
sys/dev/i2c/tps65217pmicreg.h
67
#define TPS65217PMIC_INT_ACM __BIT(5)
sys/dev/i2c/tps65217pmicreg.h
68
#define TPS65217PMIC_INT_PBM __BIT(6)
sys/dev/i2c/tps65217pmicreg.h
76
#define TPS65217PMIC_WLEDCTRL1_ISEL __BIT(2)
sys/dev/i2c/tps65217pmicreg.h
77
#define TPS65217PMIC_WLEDCTRL1_ISINK_EN __BIT(3)
sys/dev/i2c/tps65217pmicreg.h
83
#define TPS65217PMIC_STATUS_USBPWR __BIT(2)
sys/dev/i2c/tps65217pmicreg.h
84
#define TPS65217PMIC_STATUS_ACPWR __BIT(3)
sys/dev/i2c/tps65217pmicreg.h
90
#define TPS65217PMIC_PGOOD_LDO3PG __BIT(0)
sys/dev/i2c/tps65217pmicreg.h
91
#define TPS65217PMIC_PGOOD_LDO4PG __BIT(1)
sys/dev/i2c/tps65217pmicreg.h
92
#define TPS65217PMIC_PGOOD_DC1PG __BIT(2)
sys/dev/i2c/tps65217pmicreg.h
93
#define TPS65217PMIC_PGOOD_DC2PG __BIT(3)
sys/dev/i2c/tps65217pmicreg.h
94
#define TPS65217PMIC_PGOOD_DC3PG __BIT(4)
sys/dev/i2c/tps65217pmicreg.h
95
#define TPS65217PMIC_PGOOD_LDO1PG __BIT(5)
sys/dev/i2c/tps65217pmicreg.h
96
#define TPS65217PMIC_PGOOD_LDO2PG __BIT(6)
sys/dev/i2c/tps65217pmicreg.h
99
#define TPS65217PMIC_DEFSLEW_GO __BIT(7)
sys/dev/i2c/twl4030.c
255
const bool actlo = (be32toh(gpio[2]) & __BIT(0)) != 0;
sys/dev/i2c/twl4030.c
67
#define PIN_BIT(pin) __BIT((pin) % 8)
sys/dev/i2c/twl4030.c
80
#define GET_TIME __BIT(6)
sys/dev/i2c/twl4030.c
81
#define STOP_RTC __BIT(0)
sys/dev/ic/ahcisata_core.c
620
ports &= ~__BIT(bit);
sys/dev/ic/ahcisata_core.c
729
if ((aslots & __BIT(slot)) != 0 &&
sys/dev/ic/ahcisata_core.c
730
(sact & __BIT(slot)) == 0) {
sys/dev/ic/ahcisata_core.c
746
if ((aslots & __BIT(slot)) != 0 &&
sys/dev/ic/ahcisata_core.c
747
(sact & __BIT(slot)) == 0) {
sys/dev/ic/ahcisatavar.h
58
#define AHCI_PCI_QUIRK_FORCE __BIT(0) /* force attach */
sys/dev/ic/ahcisatavar.h
59
#define AHCI_PCI_QUIRK_BAD64 __BIT(1) /* broken 64-bit DMA */
sys/dev/ic/ahcisatavar.h
60
#define AHCI_QUIRK_BADPMP __BIT(2) /* broken PMP support, ignore */
sys/dev/ic/ahcisatavar.h
61
#define AHCI_QUIRK_BADNCQ __BIT(3) /* possibly broken NCQ support, ignore */
sys/dev/ic/al2210reg.h
109
#define AL2210_RECEIVER_AGCDETENA __BIT(11)
sys/dev/ic/al2210reg.h
137
#define AL2210_CONFIG2_REGPD_MASK __BIT(19)
sys/dev/ic/al2210reg.h
139
#define AL2210_CONFIG2_XTAL_SC_MASK __BIT(10)
sys/dev/ic/al2210reg.h
144
#define AL2210_CONFIG3_AGC_DET_PATT_1MHZ __BIT(17)
sys/dev/ic/al2210reg.h
146
#define AL2210_CONFIG3_AGC_DET_PATT_100KHZ __BIT(16)
sys/dev/ic/anx_dp.c
104
#define PD_RING_OSC __BIT(6)
sys/dev/ic/anx_dp.c
106
#define TX_CUR1_2X __BIT(2)
sys/dev/ic/anx_dp.c
117
#define PLL_LOCK_CHG __BIT(6)
sys/dev/ic/anx_dp.c
122
#define INT_HPD __BIT(6)
sys/dev/ic/anx_dp.c
123
#define HW_TRAINING_FINISH __BIT(5)
sys/dev/ic/anx_dp.c
124
#define RPLY_RECEIV __BIT(1)
sys/dev/ic/anx_dp.c
125
#define AUX_ERR __BIT(0)
sys/dev/ic/anx_dp.c
127
#define DET_STA __BIT(2)
sys/dev/ic/anx_dp.c
128
#define FORCE_DET __BIT(1)
sys/dev/ic/anx_dp.c
129
#define DET_CTRL __BIT(0)
sys/dev/ic/anx_dp.c
132
#define HPD_STATUS __BIT(6)
sys/dev/ic/anx_dp.c
133
#define F_HPD __BIT(5)
sys/dev/ic/anx_dp.c
134
#define HPD_CTRL __BIT(4)
sys/dev/ic/anx_dp.c
135
#define HDCP_RDY __BIT(3)
sys/dev/ic/anx_dp.c
136
#define STRM_VALID __BIT(2)
sys/dev/ic/anx_dp.c
137
#define F_VALID __BIT(1)
sys/dev/ic/anx_dp.c
138
#define VALID_CTRL __BIT(0)
sys/dev/ic/anx_dp.c
145
#define SCRAMBLING_DISABLE __BIT(5)
sys/dev/ic/anx_dp.c
149
#define MAX_PRE_REACH __BIT(5)
sys/dev/ic/anx_dp.c
151
#define MAX_DRIVE_REACH __BIT(2)
sys/dev/ic/anx_dp.c
154
#define PLL_LOCK __BIT(4)
sys/dev/ic/anx_dp.c
155
#define F_PLL_LOCK __BIT(3)
sys/dev/ic/anx_dp.c
156
#define PLL_LOCK_CTRL __BIT(2)
sys/dev/ic/anx_dp.c
157
#define PN_INV __BIT(0)
sys/dev/ic/anx_dp.c
162
#define MACRO_RST __BIT(5)
sys/dev/ic/anx_dp.c
165
#define AUX_BUSY __BIT(4)
sys/dev/ic/anx_dp.c
169
#define DEFER_CTRL_EN __BIT(7)
sys/dev/ic/anx_dp.c
172
#define AUX_RX_COMM_I2C_DEFER __BIT(3)
sys/dev/ic/anx_dp.c
173
#define AUX_RX_COMM_AUX_DEFER __BIT(1)
sys/dev/ic/anx_dp.c
175
#define BUF_CLR __BIT(7)
sys/dev/ic/anx_dp.c
180
#define AUX_TX_COMM_DP __BIT(3)
sys/dev/ic/anx_dp.c
181
#define AUX_TX_COMM_MOT __BIT(2)
sys/dev/ic/anx_dp.c
182
#define AUX_TX_COMM_READ __BIT(0)
sys/dev/ic/anx_dp.c
190
#define ADDR_ONLY __BIT(1)
sys/dev/ic/anx_dp.c
191
#define AUX_EN __BIT(0)
sys/dev/ic/anx_dp.c
194
#define AUDIO_MODE_SPDIF_MODE __BIT(8)
sys/dev/ic/anx_dp.c
195
#define VIDEO_MODE_SLAVE_MODE __BIT(1)
sys/dev/ic/anx_dp.c
55
#define RESET_DP_TX __BIT(0)
sys/dev/ic/anx_dp.c
57
#define MASTER_VID_FUNC_EN_N __BIT(7)
sys/dev/ic/anx_dp.c
58
#define RK_VID_CAP_FUNC_EN_N __BIT(6)
sys/dev/ic/anx_dp.c
59
#define SLAVE_VID_FUNC_EN_N __BIT(5)
sys/dev/ic/anx_dp.c
60
#define RK_VID_FIFO_FUNC_EN_N __BIT(5)
sys/dev/ic/anx_dp.c
61
#define AUD_FIFO_FUNC_EN_N __BIT(4)
sys/dev/ic/anx_dp.c
62
#define AUD_FUNC_EN_N __BIT(3)
sys/dev/ic/anx_dp.c
63
#define HDCP_FUNC_EN_N __BIT(2)
sys/dev/ic/anx_dp.c
64
#define CRC_FUNC_EN_N __BIT(1)
sys/dev/ic/anx_dp.c
65
#define SW_FUNC_EN_N __BIT(0)
sys/dev/ic/anx_dp.c
67
#define SSC_FUNC_EN_N __BIT(7)
sys/dev/ic/anx_dp.c
68
#define AUX_FUNC_EN_N __BIT(2)
sys/dev/ic/anx_dp.c
69
#define SERDES_FIFO_FUNC_EN_N __BIT(1)
sys/dev/ic/anx_dp.c
70
#define LS_CLK_DOMAIN_FUNC_EN_N __BIT(0)
sys/dev/ic/anx_dp.c
72
#define VIDEO_EN __BIT(7)
sys/dev/ic/anx_dp.c
73
#define VIDEO_MUTE __BIT(6)
sys/dev/ic/anx_dp.c
79
#define F_SEL __BIT(4)
sys/dev/ic/anx_dp.c
80
#define SLAVE_I_SCAN_CFG __BIT(2)
sys/dev/ic/anx_dp.c
81
#define SLAVE_VSYNC_P_CFG __BIT(1)
sys/dev/ic/anx_dp.c
82
#define SLAVE_HSYNC_P_CFG __BIT(0)
sys/dev/ic/anx_dp.c
84
#define REF_CLK_24M __BIT(0)
sys/dev/ic/anx_dp.c
86
#define DP_INC_BG __BIT(7)
sys/dev/ic/anx_dp.c
87
#define DP_EXP_PD __BIT(6)
sys/dev/ic/anx_dp.c
88
#define DP_PHY_PD __BIT(5)
sys/dev/ic/anx_dp.c
89
#define RK_AUX_PD __BIT(5)
sys/dev/ic/anx_dp.c
90
#define AUX_PD __BIT(4)
sys/dev/ic/anx_dp.c
91
#define RK_PLL_PD __BIT(4)
sys/dev/ic/anx_dp.c
92
#define CHx_PD(x) __BIT(x) /* 0<=x<=3 */
sys/dev/ic/anx_dp.c
96
#define TX_TERMINAL_CTRL_50_OHM __BIT(4)
sys/dev/ic/anx_dp.c
98
#define SEL_24M __BIT(3)
sys/dev/ic/anx_dp.h
60
#define ANXDP_FLAG_ROCKCHIP __BIT(0)
sys/dev/ic/athnvar.h
39
#define DBG_INIT __BIT(0)
sys/dev/ic/athnvar.h
40
#define DBG_FN __BIT(1)
sys/dev/ic/athnvar.h
41
#define DBG_TX __BIT(2)
sys/dev/ic/athnvar.h
42
#define DBG_RX __BIT(3)
sys/dev/ic/athnvar.h
43
#define DBG_STM __BIT(4)
sys/dev/ic/athnvar.h
44
#define DBG_RF __BIT(5)
sys/dev/ic/athnvar.h
45
#define DBG_NODES __BIT(6)
sys/dev/ic/athnvar.h
46
#define DBG_INTR __BIT(7)
sys/dev/ic/atw.c
1893
for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) {
sys/dev/ic/atwreg.h
136
#define ATW_PAR_MWIE __BIT(24) /* memory write and invalidate
sys/dev/ic/atwreg.h
139
#define ATW_PAR_MRLE __BIT(23) /* memory read line enable */
sys/dev/ic/atwreg.h
140
#define ATW_PAR_MRME __BIT(21) /* memory read multiple
sys/dev/ic/atwreg.h
162
#define ATW_PAR_BLE __BIT(7) /* big/little endian selection */
sys/dev/ic/atwreg.h
164
#define ATW_PAR_BAR __BIT(1) /* bus arbitration */
sys/dev/ic/atwreg.h
165
#define ATW_PAR_SWR __BIT(0) /* software reset */
sys/dev/ic/atwreg.h
167
#define ATW_FRCTL_PWRMGMT __BIT(31) /* power management */
sys/dev/ic/atwreg.h
169
#define ATW_FRCTL_ORDER __BIT(28) /* order bit */
sys/dev/ic/atwreg.h
170
#define ATW_FRCTL_MAXPSP __BIT(27) /* maximum power saving */
sys/dev/ic/atwreg.h
171
#define ATW_C_FRCTL_PRSP __BIT(26) /* 1: driver sends probe
sys/dev/ic/atwreg.h
175
#define ATW_C_FRCTL_DRVBCON __BIT(25) /* 1: driver sends beacons
sys/dev/ic/atwreg.h
178
#define ATW_C_FRCTL_DRVLINKCTRL __BIT(24) /* 1: driver controls link LED
sys/dev/ic/atwreg.h
181
#define ATW_C_FRCTL_DRVLINKON __BIT(23) /* 1: turn on link LED
sys/dev/ic/atwreg.h
184
#define ATW_C_FRCTL_CTX_DATA __BIT(22) /* 0: set by CSR28
sys/dev/ic/atwreg.h
187
#define ATW_C_FRCTL_RSVFRM __BIT(21) /* 1: receive "reserved"
sys/dev/ic/atwreg.h
191
#define ATW_C_FRCTL_CFEND __BIT(19) /* write to send CF_END,
sys/dev/ic/atwreg.h
194
#define ATW_FRCTL_DOZEFRM __BIT(18) /* select pre-sleep frame */
sys/dev/ic/atwreg.h
195
#define ATW_FRCTL_PSAWAKE __BIT(17) /* MAC is awake (?) */
sys/dev/ic/atwreg.h
196
#define ATW_FRCTL_PSMODE __BIT(16) /* MAC is power-saving (?) */
sys/dev/ic/atwreg.h
199
#define ATW_INTR_PCF __BIT(31) /* started/ended CFP */
sys/dev/ic/atwreg.h
200
#define ATW_INTR_BCNTC __BIT(30) /* transmitted IBSS beacon */
sys/dev/ic/atwreg.h
201
#define ATW_INTR_GPINT __BIT(29) /* GPIO interrupt */
sys/dev/ic/atwreg.h
202
#define ATW_INTR_LINKOFF __BIT(28) /* lost ATW_WCSR_BLN beacons */
sys/dev/ic/atwreg.h
203
#define ATW_INTR_ATIMTC __BIT(27) /* transmitted ATIM */
sys/dev/ic/atwreg.h
204
#define ATW_INTR_TSFTF __BIT(26) /* TSFT out of range */
sys/dev/ic/atwreg.h
205
#define ATW_INTR_TSCZ __BIT(25) /* TSC countdown expired */
sys/dev/ic/atwreg.h
206
#define ATW_INTR_LINKON __BIT(24) /* matched SSID, BSSID */
sys/dev/ic/atwreg.h
207
#define ATW_INTR_SQL __BIT(23) /* Marvel signal quality */
sys/dev/ic/atwreg.h
208
#define ATW_INTR_WEPTD __BIT(22) /* switched WEP table */
sys/dev/ic/atwreg.h
209
#define ATW_INTR_ATIME __BIT(21) /* ended ATIM window */
sys/dev/ic/atwreg.h
210
#define ATW_INTR_TBTT __BIT(20) /* (TBTT) Target Beacon TX Time
sys/dev/ic/atwreg.h
213
#define ATW_INTR_NISS __BIT(16) /* normal interrupt status
sys/dev/ic/atwreg.h
217
#define ATW_INTR_AISS __BIT(15) /* abnormal interrupt status
sys/dev/ic/atwreg.h
222
#define ATW_INTR_TEIS __BIT(14) /* transmit early interrupt
sys/dev/ic/atwreg.h
226
#define ATW_INTR_FBE __BIT(13) /* fatal bus error */
sys/dev/ic/atwreg.h
227
#define ATW_INTR_REIS __BIT(12) /* receive early interrupt
sys/dev/ic/atwreg.h
231
#define ATW_INTR_GPTT __BIT(11) /* general purpose timer expired */
sys/dev/ic/atwreg.h
232
#define ATW_INTR_RPS __BIT(8) /* stopped receive process */
sys/dev/ic/atwreg.h
233
#define ATW_INTR_RDU __BIT(7) /* receive descriptor
sys/dev/ic/atwreg.h
236
#define ATW_INTR_RCI __BIT(6) /* completed packet reception */
sys/dev/ic/atwreg.h
237
#define ATW_INTR_TUF __BIT(5) /* transmit underflow */
sys/dev/ic/atwreg.h
238
#define ATW_INTR_TRT __BIT(4) /* transmit retry count
sys/dev/ic/atwreg.h
241
#define ATW_INTR_TLT __BIT(3) /* transmit lifetime exceeded */
sys/dev/ic/atwreg.h
242
#define ATW_INTR_TDU __BIT(2) /* transmit descriptor
sys/dev/ic/atwreg.h
245
#define ATW_INTR_TPS __BIT(1) /* stopped transmit process */
sys/dev/ic/atwreg.h
246
#define ATW_INTR_TCI __BIT(0) /* completed transmit */
sys/dev/ic/atwreg.h
247
#define ATW_NAR_TXCF __BIT(31) /* stop process on TX failure */
sys/dev/ic/atwreg.h
248
#define ATW_NAR_HF __BIT(30) /* flush TX FIFO to host (?) */
sys/dev/ic/atwreg.h
249
#define ATW_NAR_UTR __BIT(29) /* select retry count source */
sys/dev/ic/atwreg.h
250
#define ATW_NAR_PCF __BIT(28) /* use one/both transmit
sys/dev/ic/atwreg.h
253
#define ATW_NAR_CFP __BIT(27) /* indicate more TX data to
sys/dev/ic/atwreg.h
256
#define ATW_C_NAR_APSTA __BIT(26) /* 0: STA mode
sys/dev/ic/atwreg.h
259
#define ATW_C_NAR_TDBBE __BIT(25) /* 0: disable TDBB
sys/dev/ic/atwreg.h
262
#define ATW_C_NAR_TDBHE __BIT(24) /* 0: disable TDBH
sys/dev/ic/atwreg.h
265
#define ATW_C_NAR_TDBHT __BIT(23) /* write 1 to make ASIC
sys/dev/ic/atwreg.h
268
#define ATW_NAR_SF __BIT(21) /* store and forward: ignore
sys/dev/ic/atwreg.h
278
#define ATW_NAR_ST __BIT(13) /* start/stop transmit */
sys/dev/ic/atwreg.h
282
#define ATW_NAR_MM __BIT(7) /* RX any multicast */
sys/dev/ic/atwreg.h
283
#define ATW_NAR_PR __BIT(6) /* promiscuous mode */
sys/dev/ic/atwreg.h
284
#define ATW_NAR_EA __BIT(5) /* match ad hoc packets (?) */
sys/dev/ic/atwreg.h
285
#define ATW_NAR_DISPCF __BIT(4) /* 1: PCF *not* supported
sys/dev/ic/atwreg.h
288
#define ATW_NAR_PB __BIT(3) /* pass bad packets */
sys/dev/ic/atwreg.h
289
#define ATW_NAR_STPDMA __BIT(2) /* stop DMA, abort packet */
sys/dev/ic/atwreg.h
290
#define ATW_NAR_SR __BIT(1) /* start/stop receive */
sys/dev/ic/atwreg.h
291
#define ATW_NAR_CTX __BIT(0) /* continuous TX mode */
sys/dev/ic/atwreg.h
295
#define ATW_IER_NIE __BIT(16) /* normal interrupt enable */
sys/dev/ic/atwreg.h
296
#define ATW_IER_AIE __BIT(15) /* abnormal interrupt enable */
sys/dev/ic/atwreg.h
298
#define ATW_IER_PCFIE __BIT(31) /* STA entered CFP */
sys/dev/ic/atwreg.h
299
#define ATW_IER_BCNTCIE __BIT(30) /* STA TX'd beacon */
sys/dev/ic/atwreg.h
300
#define ATW_IER_ATIMTCIE __BIT(27) /* transmitted ATIM */
sys/dev/ic/atwreg.h
301
#define ATW_IER_LINKONIE __BIT(24) /* matched beacon */
sys/dev/ic/atwreg.h
302
#define ATW_IER_ATIMIE __BIT(21) /* ended ATIM window */
sys/dev/ic/atwreg.h
303
#define ATW_IER_TBTTIE __BIT(20) /* TBTT */
sys/dev/ic/atwreg.h
304
#define ATW_IER_TEIE __BIT(14) /* moved TX packet to FIFO */
sys/dev/ic/atwreg.h
305
#define ATW_IER_REIE __BIT(12) /* RX packet filled its first
sys/dev/ic/atwreg.h
308
#define ATW_IER_RCIE __BIT(6) /* completed RX */
sys/dev/ic/atwreg.h
309
#define ATW_IER_TDUIE __BIT(2) /* transmit descriptor
sys/dev/ic/atwreg.h
312
#define ATW_IER_TCIE __BIT(0) /* completed TX */
sys/dev/ic/atwreg.h
314
#define ATW_IER_GPIE __BIT(29) /* GPIO interrupt */
sys/dev/ic/atwreg.h
315
#define ATW_IER_LINKOFFIE __BIT(28) /* lost beacon */
sys/dev/ic/atwreg.h
316
#define ATW_IER_TSFTFIE __BIT(26) /* TSFT out of range */
sys/dev/ic/atwreg.h
317
#define ATW_IER_TSCIE __BIT(25) /* TSC countdown expired */
sys/dev/ic/atwreg.h
318
#define ATW_IER_SQLIE __BIT(23) /* signal quality */
sys/dev/ic/atwreg.h
319
#define ATW_IER_WEPIE __BIT(22) /* finished WEP table switch */
sys/dev/ic/atwreg.h
320
#define ATW_IER_FBEIE __BIT(13) /* fatal bus error */
sys/dev/ic/atwreg.h
321
#define ATW_IER_GPTIE __BIT(11) /* general purpose timer expired */
sys/dev/ic/atwreg.h
322
#define ATW_IER_RPSIE __BIT(8) /* stopped receive process */
sys/dev/ic/atwreg.h
323
#define ATW_IER_RUIE __BIT(7) /* receive descriptor unavailable */
sys/dev/ic/atwreg.h
324
#define ATW_IER_TUIE __BIT(5) /* transmit underflow */
sys/dev/ic/atwreg.h
325
#define ATW_IER_TRTIE __BIT(4) /* exceeded transmit retry count */
sys/dev/ic/atwreg.h
326
#define ATW_IER_TLTTIE __BIT(3) /* transmit lifetime exceeded */
sys/dev/ic/atwreg.h
327
#define ATW_IER_TPSIE __BIT(1) /* stopped transmit process */
sys/dev/ic/atwreg.h
330
#define ATW_LPC_LPCO __BIT(16) /* lost packet counter overflow */
sys/dev/ic/atwreg.h
335
#define ATW_TEST1_RXPKT1IN __BIT(1)
sys/dev/ic/atwreg.h
337
#define ATW_TEST1_CONTROL __BIT(31) /* "0: read from dxfer_control,
sys/dev/ic/atwreg.h
363
#define ATW_SPR_SRS __BIT(11) /* activate SEEPROM access */
sys/dev/ic/atwreg.h
364
#define ATW_SPR_SDO __BIT(3) /* data out of SEEPROM */
sys/dev/ic/atwreg.h
365
#define ATW_SPR_SDI __BIT(2) /* data into SEEPROM */
sys/dev/ic/atwreg.h
366
#define ATW_SPR_SCLK __BIT(1) /* SEEPROM clock */
sys/dev/ic/atwreg.h
367
#define ATW_SPR_SCS __BIT(0) /* SEEPROM chip select */
sys/dev/ic/atwreg.h
416
#define ATW_TEST0_EPNE __BIT(18) /* SEEPROM not detected */
sys/dev/ic/atwreg.h
417
#define ATW_TEST0_EPSNM __BIT(17) /* SEEPROM bad signature */
sys/dev/ic/atwreg.h
418
#define ATW_TEST0_EPTYP_MASK __BIT(16) /* SEEPROM type
sys/dev/ic/atwreg.h
424
#define ATW_TEST0_EPRLD __BIT(15) /* recall SEEPROM (write 1) */
sys/dev/ic/atwreg.h
426
#define ATW_WCSR_CRCT __BIT(30) /* CRC-16 type */
sys/dev/ic/atwreg.h
427
#define ATW_WCSR_WP1E __BIT(29) /* match wake-up pattern 1 */
sys/dev/ic/atwreg.h
428
#define ATW_WCSR_WP2E __BIT(28) /* match wake-up pattern 2 */
sys/dev/ic/atwreg.h
429
#define ATW_WCSR_WP3E __BIT(27) /* match wake-up pattern 3 */
sys/dev/ic/atwreg.h
430
#define ATW_WCSR_WP4E __BIT(26) /* match wake-up pattern 4 */
sys/dev/ic/atwreg.h
431
#define ATW_WCSR_WP5E __BIT(25) /* match wake-up pattern 5 */
sys/dev/ic/atwreg.h
435
#define ATW_WCSR_TSFTWE __BIT(20) /* wake up on TSFT out of
sys/dev/ic/atwreg.h
438
#define ATW_WCSR_TIMWE __BIT(19) /* wake up on TIM */
sys/dev/ic/atwreg.h
439
#define ATW_WCSR_ATIMWE __BIT(18) /* wake up on ATIM */
sys/dev/ic/atwreg.h
440
#define ATW_WCSR_KEYWE __BIT(17) /* wake up on key update */
sys/dev/ic/atwreg.h
441
#define ATW_WCSR_WFRE __BIT(10) /* wake up on wake-up frame */
sys/dev/ic/atwreg.h
442
#define ATW_WCSR_MPRE __BIT(9) /* wake up on magic packet */
sys/dev/ic/atwreg.h
443
#define ATW_WCSR_LSOE __BIT(8) /* wake up on link loss */
sys/dev/ic/atwreg.h
445
#define ATW_WCSR_KEYUP __BIT(6) /* */
sys/dev/ic/atwreg.h
446
#define ATW_WCSR_TSFTW __BIT(5) /* */
sys/dev/ic/atwreg.h
447
#define ATW_WCSR_TIMW __BIT(4) /* */
sys/dev/ic/atwreg.h
448
#define ATW_WCSR_ATIMW __BIT(3) /* */
sys/dev/ic/atwreg.h
449
#define ATW_WCSR_WFR __BIT(2) /* */
sys/dev/ic/atwreg.h
450
#define ATW_WCSR_MPR __BIT(1) /* */
sys/dev/ic/atwreg.h
451
#define ATW_WCSR_LSO __BIT(0) /* */
sys/dev/ic/atwreg.h
453
#define ATW_GPTMR_COM_MASK __BIT(16) /* continuous operation mode */
sys/dev/ic/atwreg.h
464
#define ATW_BBPCTL_TWI __BIT(31)
sys/dev/ic/atwreg.h
468
#define ATW_BBPCTL_NEGEDGE_DO __BIT(23)
sys/dev/ic/atwreg.h
470
#define ATW_BBPCTL_NEGEDGE_DI __BIT(22)
sys/dev/ic/atwreg.h
471
#define ATW_BBPCTL_CCA_ACTLO __BIT(21) /* 1: CCA signal is low
sys/dev/ic/atwreg.h
483
#define ATW_BBPCTL_WR __BIT(17)
sys/dev/ic/atwreg.h
484
#define ATW_BBPCTL_RD __BIT(16) /* start read; reset on
sys/dev/ic/atwreg.h
490
#define ATW_SYNCTL_WR __BIT(31) /* start write; reset on
sys/dev/ic/atwreg.h
493
#define ATW_SYNCTL_RD __BIT(30) /* start read; reset on
sys/dev/ic/atwreg.h
496
#define ATW_SYNCTL_CS0 __BIT(29) /* chip select */
sys/dev/ic/atwreg.h
497
#define ATW_SYNCTL_CS1 __BIT(28)
sys/dev/ic/atwreg.h
498
#define ATW_SYNCTL_CAL __BIT(27) /* generate RF CAL pulse after
sys/dev/ic/atwreg.h
501
#define ATW_SYNCTL_SELCAL __BIT(26) /* RF CAL source, 0: CAL bit,
sys/dev/ic/atwreg.h
505
#define ATW_C_SYNCTL_MMICE __BIT(25) /* ADM8211C/CR define this
sys/dev/ic/atwreg.h
522
#define ATW_PLCPHD_PMBL __BIT(15) /* 0: long preamble, 1: short */
sys/dev/ic/atwreg.h
576
#define ATW_MMIRADDR2_PROREXT __BIT(15) /* Probe Response
sys/dev/ic/atwreg.h
585
#define ATW_TXBR_ALCUPDATE_MASK __BIT(31)
sys/dev/ic/atwreg.h
590
#define ATW_ALCSTAT_MCOV_MASK __BIT(27) /* MPDU count overflow */
sys/dev/ic/atwreg.h
591
#define ATW_ALCSTAT_ESOV_MASK __BIT(26) /* error sum overflow */
sys/dev/ic/atwreg.h
627
#define ATW_CMDR_PM __BIT(19) /* enables power mgmt
sys/dev/ic/atwreg.h
630
#define ATW_CMDR_APM __BIT(18) /* APM mode, effective when
sys/dev/ic/atwreg.h
633
#define ATW_CMDR_RTE __BIT(4) /* enable Rx FIFO threshold */
sys/dev/ic/atwreg.h
643
#define ATW_CMDR_SINT_MASK __BIT(1) /* software interrupt---huh? */
sys/dev/ic/atwreg.h
701
#define ATW_C_BCNT_EXTEN1 __BIT(31) /* 11M beacon len. extension */
sys/dev/ic/atwreg.h
704
#define ATW_C_BCNT_EXTEN0 __BIT(15) /* 11M beacon len. extension */
sys/dev/ic/atwreg.h
705
#define ATW_C_BCNT_BEANLEN0 __BIT(14,0) /* beacon length in us */
sys/dev/ic/atwreg.h
711
#define ATW_C_TSC_TIMTABSEL __BIT(4) /* select TIM table 0 or 1 */
sys/dev/ic/atwreg.h
716
#define ATW_SYNRF_SELSYN __BIT(31) /* 0: MAC controls SYN IF pins,
sys/dev/ic/atwreg.h
721
#define ATW_SYNRF_SELRF __BIT(30) /* 0: MAC controls RF IF pins,
sys/dev/ic/atwreg.h
725
#define ATW_SYNRF_LERF __BIT(29) /* if SELSYN = 1, direct control
sys/dev/ic/atwreg.h
728
#define ATW_SYNRF_LEIF __BIT(28) /* if SELSYN = 1, direct control
sys/dev/ic/atwreg.h
731
#define ATW_SYNRF_SYNCLK __BIT(27) /* if SELSYN = 1, direct control
sys/dev/ic/atwreg.h
734
#define ATW_SYNRF_SYNDATA __BIT(26) /* if SELSYN = 1, direct control
sys/dev/ic/atwreg.h
737
#define ATW_SYNRF_PE1 __BIT(25) /* if SELRF = 1, direct control
sys/dev/ic/atwreg.h
740
#define ATW_SYNRF_PE2 __BIT(24) /* if SELRF = 1, direct control
sys/dev/ic/atwreg.h
743
#define ATW_SYNRF_PAPE __BIT(23) /* if SELRF = 1, direct control
sys/dev/ic/atwreg.h
746
#define ATW_C_SYNRF_TRSW __BIT(22) /* if SELRF = 1, direct control
sys/dev/ic/atwreg.h
749
#define ATW_C_SYNRF_TRSWN __BIT(21) /* if SELRF = 1, direct control
sys/dev/ic/atwreg.h
752
#define ATW_SYNRF_INTERSIL_EN __BIT(20) /* if SELRF = 1, enables
sys/dev/ic/atwreg.h
757
#define ATW_SYNRF_PHYRST __BIT(18) /* if SELRF = 1, direct control
sys/dev/ic/atwreg.h
779
#define ATW_CAP0_RCVDTIM __BIT(4) /* receive every DTIM */
sys/dev/ic/atwreg.h
785
#define ATW_RMD_ATIMST __BIT(31) /* ATIM frame TX status */
sys/dev/ic/atwreg.h
786
#define ATW_RMD_CFP __BIT(30) /* CFP indicator */
sys/dev/ic/atwreg.h
829
#define ATW_WEPCTL_WEPENABLE __BIT(31) /* enable WEP engine */
sys/dev/ic/atwreg.h
830
#define ATW_WEPCTL_AUTOSWITCH __BIT(30) /* auto-switch enable (huh?) */
sys/dev/ic/atwreg.h
831
#define ATW_WEPCTL_CURTBL __BIT(29) /* current table in use */
sys/dev/ic/atwreg.h
832
#define ATW_WEPCTL_WR __BIT(28) /* */
sys/dev/ic/atwreg.h
833
#define ATW_WEPCTL_RD __BIT(27) /* */
sys/dev/ic/atwreg.h
834
#define ATW_WEPCTL_WEPRXBYP __BIT(25) /* bypass WEP on RX */
sys/dev/ic/atwreg.h
835
#define ATW_WEPCTL_SHKEY __BIT(24) /* 1: pass to host if tbl
sys/dev/ic/atwreg.h
839
#define ATW_WEPCTL_UNKNOWN0 __BIT(23) /* has something to do with
sys/dev/ic/atwreg.h
849
#define ATW_WEP_ENABLED __BIT(7)
sys/dev/ic/atwreg.h
850
#define ATW_WEP_104BIT __BIT(6)
sys/dev/ic/atwreg.h
855
#define ATW_MACTEST_FORCE_IV __BIT(23)
sys/dev/ic/atwreg.h
856
#define ATW_MACTEST_FORCE_KEYID __BIT(22)
sys/dev/ic/atwreg.h
858
#define ATW_MACTEST_MMI_USETXCLK __BIT(11)
sys/dev/ic/atwreg.h
863
#define ATW_FER_INTR __BIT(15)
sys/dev/ic/atwreg.h
865
#define ATW_FER_GWAKE __BIT(4)
sys/dev/ic/atwreg.h
867
#define ATW_FEMR_INTR_EN __BIT(15) /* enable INTA# */
sys/dev/ic/atwreg.h
868
#define ATW_FEMR_WAKEUP_EN __BIT(14) /* enable wake-up */
sys/dev/ic/atwreg.h
869
#define ATW_FEMR_GWAKE_EN __BIT(4) /* enable general wake-up */
sys/dev/ic/atwreg.h
871
#define ATW_FPSR_INTR_STATUS __BIT(15) /* interrupt status */
sys/dev/ic/atwreg.h
872
#define ATW_FPSR_WAKEUP_STATUS __BIT(4) /* CSTSCHG state */
sys/dev/ic/atwreg.h
874
#define ATW_FFER_INTA_FORCE __BIT(15)
sys/dev/ic/atwreg.h
876
#define ATW_FFER_GWAKE_FORCE __BIT(4)
sys/dev/ic/atwreg.h
934
#define ATW_TXCTL_OWN __BIT(31) /* 1: ready to transmit */
sys/dev/ic/atwreg.h
935
#define ATW_TXCTL_DONE __BIT(30) /* 0: not processed */
sys/dev/ic/atwreg.h
941
#define ATW_TXSTAT_ES __BIT(29) /* 0: TX successful */
sys/dev/ic/atwreg.h
942
#define ATW_TXSTAT_TLT __BIT(28) /* TX lifetime expired */
sys/dev/ic/atwreg.h
943
#define ATW_TXSTAT_TRT __BIT(27) /* TX retry limit expired */
sys/dev/ic/atwreg.h
944
#define ATW_TXSTAT_TUF __BIT(26) /* TX under-run error */
sys/dev/ic/atwreg.h
945
#define ATW_TXSTAT_TRO __BIT(25) /* TX over-run error */
sys/dev/ic/atwreg.h
946
#define ATW_TXSTAT_SOFBR __BIT(24) /* packet size != buffer size
sys/dev/ic/atwreg.h
957
#define ATW_TXFLAG_IC __BIT(31) /* interrupt on completion */
sys/dev/ic/atwreg.h
958
#define ATW_TXFLAG_LS __BIT(30) /* packet's last descriptor */
sys/dev/ic/atwreg.h
959
#define ATW_TXFLAG_FS __BIT(29) /* packet's first descriptor */
sys/dev/ic/atwreg.h
960
#define ATW_TXFLAG_TER __BIT(25) /* end of ring */
sys/dev/ic/atwreg.h
961
#define ATW_TXFLAG_TCH __BIT(24) /* at_buf2 is 2nd chain */
sys/dev/ic/atwreg.h
973
#define ATW_RXCTL_RER __BIT(25) /* end of ring */
sys/dev/ic/atwreg.h
974
#define ATW_RXCTL_RCH __BIT(24) /* ar_buf2 is 2nd chain */
sys/dev/ic/atwreg.h
978
#define ATW_RXSTAT_OWN __BIT(31) /* 1: NIC may fill descriptor */
sys/dev/ic/atwreg.h
979
#define ATW_RXSTAT_ES __BIT(30) /* error summary, 0 on
sys/dev/ic/atwreg.h
982
#define ATW_RXSTAT_SQL __BIT(29) /* has signal quality (?) */
sys/dev/ic/atwreg.h
983
#define ATW_RXSTAT_DE __BIT(28) /* descriptor error---packet is
sys/dev/ic/atwreg.h
987
#define ATW_RXSTAT_FS __BIT(27) /* packet's first descriptor */
sys/dev/ic/atwreg.h
988
#define ATW_RXSTAT_LS __BIT(26) /* packet's last descriptor */
sys/dev/ic/atwreg.h
989
#define ATW_RXSTAT_PCF __BIT(25) /* received during CFP */
sys/dev/ic/atwreg.h
990
#define ATW_RXSTAT_SFDE __BIT(24) /* PLCP SFD error */
sys/dev/ic/atwreg.h
991
#define ATW_RXSTAT_SIGE __BIT(23) /* PLCP signal error */
sys/dev/ic/atwreg.h
992
#define ATW_RXSTAT_CRC16E __BIT(22) /* PLCP CRC16 error */
sys/dev/ic/atwreg.h
993
#define ATW_RXSTAT_RXTOE __BIT(21) /* RX time-out, last descriptor
sys/dev/ic/atwreg.h
996
#define ATW_RXSTAT_CRC32E __BIT(20) /* CRC32 error */
sys/dev/ic/atwreg.h
997
#define ATW_RXSTAT_ICVE __BIT(19) /* WEP ICV error */
sys/dev/ic/atwreg.h
998
#define ATW_RXSTAT_DA1 __BIT(17) /* DA bit 1, admin'd address */
sys/dev/ic/atwreg.h
999
#define ATW_RXSTAT_DA0 __BIT(16) /* DA bit 0, group address */
sys/dev/ic/atwvar.h
345
#define ATW_HDRCTL_SHORT_PREAMBLE __BIT(0) /* use short preamble */
sys/dev/ic/atwvar.h
346
#define ATW_HDRCTL_MORE_FRAG __BIT(1) /* ??? from Linux */
sys/dev/ic/atwvar.h
347
#define ATW_HDRCTL_MORE_DATA __BIT(2) /* ??? from Linux */
sys/dev/ic/atwvar.h
348
#define ATW_HDRCTL_FRAG_NUM __BIT(3) /* ??? from Linux */
sys/dev/ic/atwvar.h
349
#define ATW_HDRCTL_RTSCTS __BIT(4) /* send RTS */
sys/dev/ic/atwvar.h
350
#define ATW_HDRCTL_WEP __BIT(5)
sys/dev/ic/atwvar.h
352
#define ATW_HDRCTL_UNKNOWN1 __BIT(15)
sys/dev/ic/atwvar.h
353
#define ATW_HDRCTL_UNKNOWN2 __BIT(8)
sys/dev/ic/bcmgenet.c
496
WR4(sc, GENET_TX_DMA_RING_CFG, __BIT(qid)); /* enable */
sys/dev/ic/bcmgenet.c
534
WR4(sc, GENET_RX_DMA_RING_CFG, __BIT(qid)); /* enable */
sys/dev/ic/bcmgenetreg.h
139
#define GENET_RX_DESC_STATUS_OWN __BIT(15)
sys/dev/ic/bcmgenetreg.h
140
#define GENET_RX_DESC_STATUS_EOP __BIT(14)
sys/dev/ic/bcmgenetreg.h
141
#define GENET_RX_DESC_STATUS_SOP __BIT(13)
sys/dev/ic/bcmgenetreg.h
143
#define GENET_RX_DESC_STATUS_LEN_ERR __BIT(4)
sys/dev/ic/bcmgenetreg.h
144
#define GENET_RX_DESC_STATUS_FRAME_ERR __BIT(3)
sys/dev/ic/bcmgenetreg.h
145
#define GENET_RX_DESC_STATUS_RX_ERR __BIT(2)
sys/dev/ic/bcmgenetreg.h
146
#define GENET_RX_DESC_STATUS_CRC_ERR __BIT(1)
sys/dev/ic/bcmgenetreg.h
147
#define GENET_RX_DESC_STATUS_OVRUN_ERR __BIT(0)
sys/dev/ic/bcmgenetreg.h
153
#define GENET_TX_DESC_STATUS_OWN __BIT(15)
sys/dev/ic/bcmgenetreg.h
154
#define GENET_TX_DESC_STATUS_EOP __BIT(14)
sys/dev/ic/bcmgenetreg.h
155
#define GENET_TX_DESC_STATUS_SOP __BIT(13)
sys/dev/ic/bcmgenetreg.h
157
#define GENET_TX_DESC_STATUS_CRC __BIT(6)
sys/dev/ic/bcmgenetreg.h
163
#define GENET_RX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1)
sys/dev/ic/bcmgenetreg.h
164
#define GENET_RX_DMA_CTRL_EN __BIT(0)
sys/dev/ic/bcmgenetreg.h
170
#define GENET_TX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1)
sys/dev/ic/bcmgenetreg.h
171
#define GENET_TX_DMA_CTRL_EN __BIT(0)
sys/dev/ic/bcmgenetreg.h
42
#define GENET_SYS_RBUF_FLUSH_RESET __BIT(1)
sys/dev/ic/bcmgenetreg.h
45
#define GENET_EXT_RGMII_OOB_ID_MODE_DISABLE __BIT(16)
sys/dev/ic/bcmgenetreg.h
46
#define GENET_EXT_RGMII_OOB_RGMII_MODE_EN __BIT(6)
sys/dev/ic/bcmgenetreg.h
47
#define GENET_EXT_RGMII_OOB_OOB_DISABLE __BIT(5)
sys/dev/ic/bcmgenetreg.h
48
#define GENET_EXT_RGMII_OOB_RGMII_LINK __BIT(4)
sys/dev/ic/bcmgenetreg.h
54
#define GENET_IRQ_MDIO_ERROR __BIT(24)
sys/dev/ic/bcmgenetreg.h
55
#define GENET_IRQ_MDIO_DONE __BIT(23)
sys/dev/ic/bcmgenetreg.h
56
#define GENET_IRQ_TXDMA_DONE __BIT(16)
sys/dev/ic/bcmgenetreg.h
57
#define GENET_IRQ_RXDMA_DONE __BIT(13)
sys/dev/ic/bcmgenetreg.h
59
#define GENET_RBUF_BAD_DIS __BIT(2)
sys/dev/ic/bcmgenetreg.h
60
#define GENET_RBUF_ALIGN_2B __BIT(1)
sys/dev/ic/bcmgenetreg.h
61
#define GENET_RBUF_64B_EN __BIT(0)
sys/dev/ic/bcmgenetreg.h
64
#define GENET_UMAC_CMD_LCL_LOOP_EN __BIT(15)
sys/dev/ic/bcmgenetreg.h
65
#define GENET_UMAC_CMD_SW_RESET __BIT(13)
sys/dev/ic/bcmgenetreg.h
66
#define GENET_UMAC_CMD_PROMISC __BIT(4)
sys/dev/ic/bcmgenetreg.h
71
#define GENET_UMAC_CMD_RXEN __BIT(1)
sys/dev/ic/bcmgenetreg.h
72
#define GENET_UMAC_CMD_TXEN __BIT(0)
sys/dev/ic/bcmgenetreg.h
78
#define GENET_UMAC_MIB_RESET_TX __BIT(2)
sys/dev/ic/bcmgenetreg.h
79
#define GENET_UMAC_MIB_RESET_RUNT __BIT(1)
sys/dev/ic/bcmgenetreg.h
80
#define GENET_UMAC_MIB_RESET_RX __BIT(0)
sys/dev/ic/bcmgenetreg.h
82
#define GENET_MDIO_START_BUSY __BIT(29)
sys/dev/ic/bcmgenetreg.h
83
#define GENET_MDIO_READ __BIT(27)
sys/dev/ic/bcmgenetreg.h
84
#define GENET_MDIO_WRITE __BIT(26)
sys/dev/ic/bwfm.c
260
fwp->fwsel_revmask & __BIT(ctx->ctx_chiprev))
sys/dev/ic/bwfmvar.h
118
#define BWFM_FWREQ(x) __BIT(x)
sys/dev/ic/bwfmvar.h
119
#define BWFM_FWOPT(x) __BIT((x)+16)
sys/dev/ic/bwfmvar.h
99
#define BWFM_FWSEL_REV_EQ(x) __BIT(x)
sys/dev/ic/cdnsiic.c
59
#define CR_CLR_FIFO __BIT(6)
sys/dev/ic/cdnsiic.c
60
#define CR_HOLD __BIT(4)
sys/dev/ic/cdnsiic.c
61
#define CR_ACKEN __BIT(3)
sys/dev/ic/cdnsiic.c
62
#define CR_NEA __BIT(2)
sys/dev/ic/cdnsiic.c
63
#define CR_MS __BIT(1)
sys/dev/ic/cdnsiic.c
64
#define CR_RD_WR __BIT(0)
sys/dev/ic/cdnsiic.c
66
#define SR_TXDV __BIT(6)
sys/dev/ic/cdnsiic.c
67
#define SR_RXDV __BIT(5)
sys/dev/ic/cdnsiic.c
71
#define ISR_ARB_LOST __BIT(9)
sys/dev/ic/cdnsiic.c
72
#define ISR_RX_UNF __BIT(7)
sys/dev/ic/cdnsiic.c
73
#define ISR_TX_OVR __BIT(6)
sys/dev/ic/cdnsiic.c
74
#define ISR_RX_OVR __BIT(5)
sys/dev/ic/cdnsiic.c
75
#define ISR_SLV_RDY __BIT(4)
sys/dev/ic/cdnsiic.c
76
#define ISR_TO __BIT(3)
sys/dev/ic/cdnsiic.c
77
#define ISR_NACK __BIT(2)
sys/dev/ic/cdnsiic.c
78
#define ISR_DATA __BIT(1)
sys/dev/ic/cdnsiic.c
79
#define ISR_COMP __BIT(0)
sys/dev/ic/dw_hdmi.c
100
#define HDMI_VP_CONF_BYPASS_SELECT __BIT(2)
sys/dev/ic/dw_hdmi.c
109
#define HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY __BIT(6)
sys/dev/ic/dw_hdmi.c
110
#define HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY __BIT(5)
sys/dev/ic/dw_hdmi.c
111
#define HDMI_FC_INVIDCONF_DE_IN_POLARITY __BIT(4)
sys/dev/ic/dw_hdmi.c
112
#define HDMI_FC_INVIDCONF_DVI_MODE __BIT(3)
sys/dev/ic/dw_hdmi.c
113
#define HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC __BIT(1)
sys/dev/ic/dw_hdmi.c
114
#define HDMI_FC_INVIDCONF_IN_I_P __BIT(0)
sys/dev/ic/dw_hdmi.c
146
#define HDMI_PHY_CONF0_PDZ __BIT(7)
sys/dev/ic/dw_hdmi.c
147
#define HDMI_PHY_CONF0_ENTMDS __BIT(6)
sys/dev/ic/dw_hdmi.c
148
#define HDMI_PHY_CONF0_SVSRET __BIT(5)
sys/dev/ic/dw_hdmi.c
149
#define HDMI_PHY_CONF0_PDDQ __BIT(4)
sys/dev/ic/dw_hdmi.c
150
#define HDMI_PHY_CONF0_TXPWRON __BIT(3)
sys/dev/ic/dw_hdmi.c
151
#define HDMI_PHY_CONF0_ENHPDRXSENSE __BIT(2)
sys/dev/ic/dw_hdmi.c
152
#define HDMI_PHY_CONF0_SELDATAENPOL __BIT(1)
sys/dev/ic/dw_hdmi.c
153
#define HDMI_PHY_CONF0_SELDIPIF __BIT(0)
sys/dev/ic/dw_hdmi.c
155
#define HDMI_PHY_STAT0_RX_SENSE_3 __BIT(7)
sys/dev/ic/dw_hdmi.c
156
#define HDMI_PHY_STAT0_RX_SENSE_2 __BIT(6)
sys/dev/ic/dw_hdmi.c
157
#define HDMI_PHY_STAT0_RX_SENSE_1 __BIT(5)
sys/dev/ic/dw_hdmi.c
158
#define HDMI_PHY_STAT0_RX_SENSE_0 __BIT(4)
sys/dev/ic/dw_hdmi.c
159
#define HDMI_PHY_STAT0_HPD __BIT(1)
sys/dev/ic/dw_hdmi.c
160
#define HDMI_PHY_STAT0_TX_PHY_LOCK __BIT(0)
sys/dev/ic/dw_hdmi.c
163
#define HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST __BIT(7)
sys/dev/ic/dw_hdmi.c
164
#define HDMI_AUD_CONF0_I2S_SELECT __BIT(5)
sys/dev/ic/dw_hdmi.c
170
#define HDMI_AUD_CONF2_INSERT_PCUV __BIT(2)
sys/dev/ic/dw_hdmi.c
171
#define HDMI_AUD_CONF2_NLPCM __BIT(1)
sys/dev/ic/dw_hdmi.c
172
#define HDMI_AUD_CONF2_HBR __BIT(0)
sys/dev/ic/dw_hdmi.c
185
#define HDMI_MC_CLKDIS_HDCPCLK_DISABLE __BIT(6)
sys/dev/ic/dw_hdmi.c
186
#define HDMI_MC_CLKDIS_CECCLK_DISABLE __BIT(5)
sys/dev/ic/dw_hdmi.c
187
#define HDMI_MC_CLKDIS_CSCCLK_DISABLE __BIT(4)
sys/dev/ic/dw_hdmi.c
188
#define HDMI_MC_CLKDIS_AUDCLK_DISABLE __BIT(3)
sys/dev/ic/dw_hdmi.c
189
#define HDMI_MC_CLKDIS_PREPCLK_DISABLE __BIT(2)
sys/dev/ic/dw_hdmi.c
190
#define HDMI_MC_CLKDIS_TMDSCLK_DISABLE __BIT(1)
sys/dev/ic/dw_hdmi.c
191
#define HDMI_MC_CLKDIS_PIXELCLK_DISABLE __BIT(0)
sys/dev/ic/dw_hdmi.c
193
#define HDMI_MC_SWRSTZREQ_CECSWRST_REQ __BIT(6)
sys/dev/ic/dw_hdmi.c
194
#define HDMI_MC_SWRSTZREQ_PREPSWRST_REQ __BIT(2)
sys/dev/ic/dw_hdmi.c
195
#define HDMI_MC_SWRSTZREQ_TMDSSWRST_REQ __BIT(1)
sys/dev/ic/dw_hdmi.c
196
#define HDMI_MC_SWRSTZREQ_PIXELSWRST_REQ __BIT(0)
sys/dev/ic/dw_hdmi.c
199
#define HDMI_MC_PHYRSTZ_ASSERT __BIT(0)
sys/dev/ic/dw_hdmi.c
209
#define HDMI_I2CM_OPERATION_WR __BIT(4)
sys/dev/ic/dw_hdmi.c
210
#define HDMI_I2CM_OPERATION_RD_EXT __BIT(1)
sys/dev/ic/dw_hdmi.c
211
#define HDMI_I2CM_OPERATION_RD __BIT(0)
sys/dev/ic/dw_hdmi.c
213
#define HDMI_I2CM_INT_DONE_POL __BIT(3)
sys/dev/ic/dw_hdmi.c
214
#define HDMI_I2CM_INT_DONE_MASK __BIT(2)
sys/dev/ic/dw_hdmi.c
215
#define HDMI_I2CM_INT_DONE_INTERRUPT __BIT(1)
sys/dev/ic/dw_hdmi.c
216
#define HDMI_I2CM_INT_DONE_STATUS __BIT(0)
sys/dev/ic/dw_hdmi.c
222
#define HDMI_I2CM_CTLINT_NACK_POL __BIT(7)
sys/dev/ic/dw_hdmi.c
223
#define HDMI_I2CM_CTLINT_NACK_MASK __BIT(6)
sys/dev/ic/dw_hdmi.c
224
#define HDMI_I2CM_CTLINT_NACK_INTERRUPT __BIT(5)
sys/dev/ic/dw_hdmi.c
225
#define HDMI_I2CM_CTLINT_NACK_STATUS __BIT(4)
sys/dev/ic/dw_hdmi.c
226
#define HDMI_I2CM_CTLINT_ARB_POL __BIT(3)
sys/dev/ic/dw_hdmi.c
227
#define HDMI_I2CM_CTLINT_ARB_MASK __BIT(2)
sys/dev/ic/dw_hdmi.c
228
#define HDMI_I2CM_CTLINT_ARB_INTERRUPT __BIT(1)
sys/dev/ic/dw_hdmi.c
229
#define HDMI_I2CM_CTLINT_ARB_STATUS __BIT(0)
sys/dev/ic/dw_hdmi.c
238
#define HDMI_I2CM_DIV_FAST_STD_MODE __BIT(3)
sys/dev/ic/dw_hdmi.c
242
#define HDMI_I2CM_SOFTRSTZ_I2C_SOFTRST __BIT(0)
sys/dev/ic/dw_hdmi.c
60
#define HDMI_CONFIG0_ID_AUDI2S __BIT(4)
sys/dev/ic/dw_hdmi.c
64
#define HDMI_IH_I2CM_STAT0_DONE __BIT(1)
sys/dev/ic/dw_hdmi.c
65
#define HDMI_IH_I2CM_STAT0_ERROR __BIT(0)
sys/dev/ic/dw_hdmi.c
67
#define HDMI_IH_MUTE_WAKEUP_INTERRUPT __BIT(1)
sys/dev/ic/dw_hdmi.c
68
#define HDMI_IH_MUTE_ALL_INTERRUPT __BIT(0)
sys/dev/ic/dw_hdmi.c
74
#define HDMI_TX_INSTUFFING_BCBDATA_STUFFING __BIT(2)
sys/dev/ic/dw_hdmi.c
75
#define HDMI_TX_INSTUFFING_RCRDATA_STUFFING __BIT(1)
sys/dev/ic/dw_hdmi.c
76
#define HDMI_TX_INSTUFFING_GYDATA_STUFFING __BIT(0)
sys/dev/ic/dw_hdmi.c
91
#define HDMI_VP_STUFF_IDEFAULT_PHASE __BIT(5)
sys/dev/ic/dw_hdmi.c
92
#define HDMI_VP_STUFF_YCC422_STUFFING __BIT(2)
sys/dev/ic/dw_hdmi.c
93
#define HDMI_VP_STUFF_PP_STUFFING __BIT(1)
sys/dev/ic/dw_hdmi.c
94
#define HDMI_VP_STUFF_PR_STUFFING __BIT(0)
sys/dev/ic/dw_hdmi.c
99
#define HDMI_VP_CONF_BYPASS_EN __BIT(6)
sys/dev/ic/dw_hdmi.h
72
#define DWHDMI_USE_INTERNAL_PHY __BIT(0)
sys/dev/ic/dwc_eqos_reg.h
149
#define GMAC_MAC_ADDRESS_HIGH_AE __BIT(31)
sys/dev/ic/dwc_eqos_reg.h
150
#define GMAC_MAC_ADDRESS_HIGH_SE __BIT(30)
sys/dev/ic/dwc_eqos_reg.h
152
#define GMAC_MAC_ADDRESS_HIGH_DCS __BIT(16)
sys/dev/ic/dwc_gmac_reg.h
119
#define GMAC_MMC_CTRL_FHP __BIT(5) /* Full-Half preset */
sys/dev/ic/dwc_gmac_reg.h
120
#define GMAC_MMC_CTRL_CP __BIT(4) /* Counters preset */
sys/dev/ic/dwc_gmac_reg.h
121
#define GMAC_MMC_CTRL_MCF __BIT(3) /* MMC counter freeze */
sys/dev/ic/dwc_gmac_reg.h
122
#define GMAC_MMC_CTRL_ROR __BIT(2) /* reset on read */
sys/dev/ic/dwc_gmac_reg.h
123
#define GMAC_MMC_CTRL_CSR __BIT(1) /* Counter stop rollover */
sys/dev/ic/dwc_gmac_reg.h
124
#define GMAC_MMC_CTRL_CR __BIT(0) /* Counters reset */
sys/dev/ic/dwc_gmac_reg.h
144
#define GMAC_MII_BUSY __BIT(0)
sys/dev/ic/dwc_gmac_reg.h
145
#define GMAC_MII_WRITE __BIT(1)
sys/dev/ic/dwc_gmac_reg.h
162
#define GMAC_BUSMODE_AAL __BIT(25)
sys/dev/ic/dwc_gmac_reg.h
163
#define GMAC_BUSMODE_4PBL __BIT(24)
sys/dev/ic/dwc_gmac_reg.h
164
#define GMAC_BUSMODE_USP __BIT(23)
sys/dev/ic/dwc_gmac_reg.h
166
#define GMAC_BUSMODE_FIXEDBURST __BIT(16)
sys/dev/ic/dwc_gmac_reg.h
175
#define GMAC_BUSMODE_RESET __BIT(0)
sys/dev/ic/dwc_gmac_reg.h
177
#define AWIN_GMAC_MRCOIS __BIT(7) /* MMC RX csum offload intr */
sys/dev/ic/dwc_gmac_reg.h
178
#define AWIN_GMAC_MTIS __BIT(6) /* MMC TX interrupt */
sys/dev/ic/dwc_gmac_reg.h
179
#define AWIN_GMAC_MRIS __BIT(3) /* MMC RX interrupt */
sys/dev/ic/dwc_gmac_reg.h
180
#define AWIN_GMAC_MIS __BIT(4) /* MMC interrupt */
sys/dev/ic/dwc_gmac_reg.h
181
#define AWIN_GMAC_PIS __BIT(3) /* PMT interrupt */
sys/dev/ic/dwc_gmac_reg.h
182
#define AWIN_GMAC_MII_IRQ __BIT(0) /* RGMII interrupt */
sys/dev/ic/dwc_gmac_reg.h
185
#define GMAC_DMA_OP_DISABLECSDROP __BIT(26) /* disable dropping of
sys/dev/ic/dwc_gmac_reg.h
188
#define GMAC_DMA_OP_RXSTOREFORWARD __BIT(25) /* start RX when a
sys/dev/ic/dwc_gmac_reg.h
190
#define GMAC_DMA_OP_DISABLERXFLUSH __BIT(24) /* Do not drop frames
sys/dev/ic/dwc_gmac_reg.h
192
#define GMAC_DMA_OP_TXSTOREFORWARD __BIT(21) /* start TX when a
sys/dev/ic/dwc_gmac_reg.h
194
#define GMAC_DMA_OP_FLUSHTX __BIT(20) /* flush TX fifo */
sys/dev/ic/dwc_gmac_reg.h
196
#define GMAC_DMA_OP_TXSTART __BIT(13) /* start TX DMA engine */
sys/dev/ic/dwc_gmac_reg.h
199
#define GMAC_DMA_OP_EFC __BIT(8) /* enable flow control */
sys/dev/ic/dwc_gmac_reg.h
200
#define GMAC_DMA_OP_FEF __BIT(7) /* forward error frames */
sys/dev/ic/dwc_gmac_reg.h
201
#define GMAC_DMA_OP_FUF __BIT(6) /* forward undersize frames */
sys/dev/ic/dwc_gmac_reg.h
203
#define GMAC_DMA_OP_OSF __BIT(2) /* operate on 2nd frame */
sys/dev/ic/dwc_gmac_reg.h
204
#define GMAC_DMA_OP_RXSTART __BIT(1) /* start RX DMA engine */
sys/dev/ic/dwc_gmac_reg.h
206
#define GMAC_DMA_INT_MMC __BIT(27) /* MMC interrupt */
sys/dev/ic/dwc_gmac_reg.h
207
#define GMAC_DMA_INT_GLI __BIT(26) /* PHY interrupt */
sys/dev/ic/dwc_gmac_reg.h
208
#define GMAC_DMA_INT_NIE __BIT(16) /* Normal/Summary */
sys/dev/ic/dwc_gmac_reg.h
209
#define GMAC_DMA_INT_AIE __BIT(15) /* Abnormal/Summary */
sys/dev/ic/dwc_gmac_reg.h
210
#define GMAC_DMA_INT_ERE __BIT(14) /* Early receive */
sys/dev/ic/dwc_gmac_reg.h
211
#define GMAC_DMA_INT_FBE __BIT(13) /* Fatal bus error */
sys/dev/ic/dwc_gmac_reg.h
212
#define GMAC_DMA_INT_ETE __BIT(10) /* Early transmit */
sys/dev/ic/dwc_gmac_reg.h
213
#define GMAC_DMA_INT_RWE __BIT(9) /* Receive watchdog */
sys/dev/ic/dwc_gmac_reg.h
214
#define GMAC_DMA_INT_RSE __BIT(8) /* Receive stopped */
sys/dev/ic/dwc_gmac_reg.h
215
#define GMAC_DMA_INT_RUE __BIT(7) /* Receive buffer unavail. */
sys/dev/ic/dwc_gmac_reg.h
216
#define GMAC_DMA_INT_RIE __BIT(6) /* Receive interrupt */
sys/dev/ic/dwc_gmac_reg.h
217
#define GMAC_DMA_INT_UNE __BIT(5) /* Tx underflow */
sys/dev/ic/dwc_gmac_reg.h
218
#define GMAC_DMA_INT_OVE __BIT(4) /* Receive overflow */
sys/dev/ic/dwc_gmac_reg.h
219
#define GMAC_DMA_INT_TJE __BIT(3) /* Transmit jabber */
sys/dev/ic/dwc_gmac_reg.h
220
#define GMAC_DMA_INT_TUE __BIT(2) /* Transmit buffer unavail. */
sys/dev/ic/dwc_gmac_reg.h
221
#define GMAC_DMA_INT_TSE __BIT(1) /* Transmit stopped */
sys/dev/ic/dwc_gmac_reg.h
222
#define GMAC_DMA_INT_TIE __BIT(0) /* Transmit interrupt */
sys/dev/ic/dwc_gmac_reg.h
226
#define GMAC_DMA_FEAT_ENHANCED_DESC __BIT(24)
sys/dev/ic/dwc_gmac_reg.h
227
#define GMAC_DMA_FEAT_COE_RX_2 __BIT(18) /* RX cksum offload type 2 */
sys/dev/ic/dwc_gmac_reg.h
228
#define GMAC_DMA_FEAT_COE_RX_1 __BIT(17) /* RX cksum offload type 1 */
sys/dev/ic/dwc_gmac_reg.h
229
#define GMAC_DMA_FEAT_COE_TX __BIT(16) /* TX checksum offload */
sys/dev/ic/dwc_gmac_reg.h
230
#define GMAC_DMA_FEAT_RMON __BIT(11) /* MMC */
sys/dev/ic/dwc_gmac_reg.h
235
#define DDESC_STATUS_OWNEDBYDEV __BIT(31)
sys/dev/ic/dwc_gmac_reg.h
238
#define DDESC_STATUS_DAFILTERFAIL __BIT(30)
sys/dev/ic/dwc_gmac_reg.h
240
#define DDESC_STATUS_RXERROR __BIT(15)
sys/dev/ic/dwc_gmac_reg.h
241
#define DDESC_STATUS_RXTRUNCATED __BIT(14)
sys/dev/ic/dwc_gmac_reg.h
242
#define DDESC_STATUS_SAFILTERFAIL __BIT(13)
sys/dev/ic/dwc_gmac_reg.h
243
#define DDESC_STATUS_RXIPC_GIANTFRAME __BIT(12)
sys/dev/ic/dwc_gmac_reg.h
244
#define DDESC_STATUS_RXDAMAGED __BIT(11)
sys/dev/ic/dwc_gmac_reg.h
245
#define DDESC_STATUS_RXVLANTAG __BIT(10)
sys/dev/ic/dwc_gmac_reg.h
246
#define DDESC_STATUS_RXFIRST __BIT(9)
sys/dev/ic/dwc_gmac_reg.h
247
#define DDESC_STATUS_RXLAST __BIT(8)
sys/dev/ic/dwc_gmac_reg.h
248
#define DDESC_STATUS_RXIPC_GIANT __BIT(7)
sys/dev/ic/dwc_gmac_reg.h
249
#define DDESC_STATUS_RXCOLLISION __BIT(6)
sys/dev/ic/dwc_gmac_reg.h
250
#define DDESC_STATUS_RXFRAMEETHER __BIT(5)
sys/dev/ic/dwc_gmac_reg.h
251
#define DDESC_STATUS_RXWATCHDOG __BIT(4)
sys/dev/ic/dwc_gmac_reg.h
252
#define DDESC_STATUS_RXMIIERROR __BIT(3)
sys/dev/ic/dwc_gmac_reg.h
253
#define DDESC_STATUS_RXDRIBBLING __BIT(2)
sys/dev/ic/dwc_gmac_reg.h
254
#define DDESC_STATUS_RXCRC __BIT(1)
sys/dev/ic/dwc_gmac_reg.h
255
#define DDESC_STATUS_RXPCE __BIT(0)
sys/dev/ic/dwc_gmac_reg.h
260
#define DDESC_CNTL_TXINT __BIT(31)
sys/dev/ic/dwc_gmac_reg.h
261
#define DDESC_CNTL_TXLAST __BIT(30)
sys/dev/ic/dwc_gmac_reg.h
262
#define DDESC_CNTL_TXFIRST __BIT(29)
sys/dev/ic/dwc_gmac_reg.h
270
#define DDESC_CNTL_TXCRCDIS __BIT(26)
sys/dev/ic/dwc_gmac_reg.h
271
#define DDESC_CNTL_TXRINGEND __BIT(25)
sys/dev/ic/dwc_gmac_reg.h
272
#define DDESC_CNTL_TXCHAIN __BIT(24)
sys/dev/ic/dwc_gmac_reg.h
273
#define DDESC_CNTL_TXDISPAD __BIT(23)
sys/dev/ic/dwc_gmac_reg.h
276
#define DDESC_CNTL_RXINTDIS __BIT(31)
sys/dev/ic/dwc_gmac_reg.h
277
#define DDESC_CNTL_RXRINGEND __BIT(25)
sys/dev/ic/dwc_gmac_reg.h
278
#define DDESC_CNTL_RXCHAIN __BIT(24)
sys/dev/ic/dwc_gmac_reg.h
292
#define DDESC_DES0_OWN __BIT(31)
sys/dev/ic/dwc_gmac_reg.h
299
#define DDESC_TDES0_IC __BIT(30)
sys/dev/ic/dwc_gmac_reg.h
300
#define DDESC_TDES0_LS __BIT(29)
sys/dev/ic/dwc_gmac_reg.h
301
#define DDESC_TDES0_FS __BIT(28)
sys/dev/ic/dwc_gmac_reg.h
303
#define DDESC_TDES0_TER __BIT(21)
sys/dev/ic/dwc_gmac_reg.h
304
#define DDESC_TDES0_TCH __BIT(20)
sys/dev/ic/dwc_gmac_reg.h
309
#define DDESC_RDES0_ES __BIT(15)
sys/dev/ic/dwc_gmac_reg.h
310
#define DDESC_RDES0_LE __BIT(12)
sys/dev/ic/dwc_gmac_reg.h
312
#define DDESC_RDES1_RCH __BIT(14)
sys/dev/ic/dwc_gmac_reg.h
49
#define AWIN_GMAC_MAC_CONF_DISABLEJABBER __BIT(22) /* jabber disable */
sys/dev/ic/dwc_gmac_reg.h
50
#define AWIN_GMAC_MAC_CONF_FRAMEBURST __BIT(21) /* allow TX frameburst when
sys/dev/ic/dwc_gmac_reg.h
52
#define AWIN_GMAC_MAC_CONF_MIISEL __BIT(15) /* select MII phy */
sys/dev/ic/dwc_gmac_reg.h
53
#define AWIN_GMAC_MAC_CONF_FES100 __BIT(14) /* 100 mbit mode */
sys/dev/ic/dwc_gmac_reg.h
54
#define AWIN_GMAC_MAC_CONF_DISABLERXOWN __BIT(13) /* do not receive our own
sys/dev/ic/dwc_gmac_reg.h
57
#define AWIN_GMAC_MAC_CONF_FULLDPLX __BIT(11) /* select full duplex */
sys/dev/ic/dwc_gmac_reg.h
58
#define AWIN_GMAC_MAC_CONF_IPC __BIT(10) /* IP checksum offload (RX) */
sys/dev/ic/dwc_gmac_reg.h
59
#define AWIN_GMAC_MAC_CONF_ACS __BIT(7) /* auto pad/CRC stripping */
sys/dev/ic/dwc_gmac_reg.h
60
#define AWIN_GMAC_MAC_CONF_TXENABLE __BIT(3) /* enable TX dma engine */
sys/dev/ic/dwc_gmac_reg.h
61
#define AWIN_GMAC_MAC_CONF_RXENABLE __BIT(2) /* enable RX dma engine */
sys/dev/ic/dwc_gmac_reg.h
63
#define AWIN_GMAC_MAC_FFILT_RA __BIT(31) /* receive all mode */
sys/dev/ic/dwc_gmac_reg.h
64
#define AWIN_GMAC_MAC_FFILT_HPF __BIT(10) /* hash or perfect filter */
sys/dev/ic/dwc_gmac_reg.h
65
#define AWIN_GMAC_MAC_FFILT_SAF __BIT(9) /* source address filter */
sys/dev/ic/dwc_gmac_reg.h
66
#define AWIN_GMAC_MAC_FFILT_SAIF __BIT(8) /* inverse filtering */
sys/dev/ic/dwc_gmac_reg.h
67
#define AWIN_GMAC_MAC_FFILT_DBF __BIT(5) /* disable broadcast frames */
sys/dev/ic/dwc_gmac_reg.h
68
#define AWIN_GMAC_MAC_FFILT_PM __BIT(4) /* promiscuous multicast */
sys/dev/ic/dwc_gmac_reg.h
69
#define AWIN_GMAC_MAC_FFILT_DAIF __BIT(3) /* DA inverse filtering */
sys/dev/ic/dwc_gmac_reg.h
70
#define AWIN_GMAC_MAC_FFILT_HMC __BIT(2) /* multicast hash compare */
sys/dev/ic/dwc_gmac_reg.h
71
#define AWIN_GMAC_MAC_FFILT_HUC __BIT(1) /* unicast hash compare */
sys/dev/ic/dwc_gmac_reg.h
72
#define AWIN_GMAC_MAC_FFILT_PR __BIT(0) /* promiscuous mode */
sys/dev/ic/dwc_gmac_reg.h
74
#define AWIN_GMAC_MAC_INT_LPI __BIT(10)
sys/dev/ic/dwc_gmac_reg.h
75
#define AWIN_GMAC_MAC_INT_TSI __BIT(9)
sys/dev/ic/dwc_gmac_reg.h
76
#define AWIN_GMAC_MAC_INT_ANEG __BIT(2)
sys/dev/ic/dwc_gmac_reg.h
77
#define AWIN_GMAC_MAC_INT_LINKCHG __BIT(1)
sys/dev/ic/dwc_gmac_reg.h
78
#define AWIN_GMAC_MAC_INT_RGSMII __BIT(0)
sys/dev/ic/dwc_gmac_reg.h
81
#define AWIN_GMAC_MAC_FLOWCTRL_UPE __BIT(3)
sys/dev/ic/dwc_gmac_reg.h
82
#define AWIN_GMAC_MAC_FLOWCTRL_RFE __BIT(2)
sys/dev/ic/dwc_gmac_reg.h
83
#define AWIN_GMAC_MAC_FLOWCTRL_TFE __BIT(1)
sys/dev/ic/dwc_gmac_reg.h
84
#define AWIN_GMAC_MAC_FLOWCTRL_BUSY __BIT(0)
sys/dev/ic/dwc_gmac_var.h
100
#define DWC_GMAC_FIXED_BURST __BIT(1)/* fixed burst bus mode */
sys/dev/ic/dwc_gmac_var.h
99
#define DWC_GMAC_FORCE_THRESH_DMA_MODE __BIT(0)/* force DMA to use threshold mode */
sys/dev/ic/dwc_mmc_reg.h
100
#define DWC_MMC_CMD_WAIT_PRE_OVER __BIT(13)
sys/dev/ic/dwc_mmc_reg.h
101
#define DWC_MMC_CMD_SEND_AUTO_STOP __BIT(12)
sys/dev/ic/dwc_mmc_reg.h
102
#define DWC_MMC_CMD_SEQMOD __BIT(11)
sys/dev/ic/dwc_mmc_reg.h
103
#define DWC_MMC_CMD_WRITE __BIT(10)
sys/dev/ic/dwc_mmc_reg.h
104
#define DWC_MMC_CMD_DATA_EXP __BIT(9)
sys/dev/ic/dwc_mmc_reg.h
105
#define DWC_MMC_CMD_CHECK_RSP_CRC __BIT(8)
sys/dev/ic/dwc_mmc_reg.h
106
#define DWC_MMC_CMD_LONG_RSP __BIT(7)
sys/dev/ic/dwc_mmc_reg.h
107
#define DWC_MMC_CMD_RSP_EXP __BIT(6)
sys/dev/ic/dwc_mmc_reg.h
109
#define DWC_MMC_INT_CARD_REMOVE __BIT(31)
sys/dev/ic/dwc_mmc_reg.h
110
#define DWC_MMC_INT_CARD_INSERT __BIT(30)
sys/dev/ic/dwc_mmc_reg.h
111
#define DWC_MMC_INT_SDIO_INT(n) __BIT(16 + (n))
sys/dev/ic/dwc_mmc_reg.h
112
#define DWC_MMC_INT_END_BIT_ERR __BIT(15)
sys/dev/ic/dwc_mmc_reg.h
113
#define DWC_MMC_INT_AUTO_CMD_DONE __BIT(14)
sys/dev/ic/dwc_mmc_reg.h
114
#define DWC_MMC_INT_START_BIT_ERR __BIT(13)
sys/dev/ic/dwc_mmc_reg.h
115
#define DWC_MMC_INT_HW_LOCKED __BIT(12)
sys/dev/ic/dwc_mmc_reg.h
116
#define DWC_MMC_INT_FIFO_RUN_ERR __BIT(11)
sys/dev/ic/dwc_mmc_reg.h
117
#define DWC_MMC_INT_VOL_CHG_DONE __BIT(10)
sys/dev/ic/dwc_mmc_reg.h
118
#define DWC_MMC_INT_DATA_STARVE __BIT(10)
sys/dev/ic/dwc_mmc_reg.h
119
#define DWC_MMC_INT_BOOT_START __BIT(9)
sys/dev/ic/dwc_mmc_reg.h
120
#define DWC_MMC_INT_DATA_TIMEOUT __BIT(9)
sys/dev/ic/dwc_mmc_reg.h
121
#define DWC_MMC_INT_ACK_RCV __BIT(8)
sys/dev/ic/dwc_mmc_reg.h
122
#define DWC_MMC_INT_RESP_TIMEOUT __BIT(8)
sys/dev/ic/dwc_mmc_reg.h
123
#define DWC_MMC_INT_DATA_CRC_ERR __BIT(7)
sys/dev/ic/dwc_mmc_reg.h
124
#define DWC_MMC_INT_RESP_CRC_ERR __BIT(6)
sys/dev/ic/dwc_mmc_reg.h
125
#define DWC_MMC_INT_RX_DATA_REQ __BIT(5)
sys/dev/ic/dwc_mmc_reg.h
126
#define DWC_MMC_INT_TX_DATA_REQ __BIT(4)
sys/dev/ic/dwc_mmc_reg.h
127
#define DWC_MMC_INT_DATA_OVER __BIT(3)
sys/dev/ic/dwc_mmc_reg.h
128
#define DWC_MMC_INT_CMD_DONE __BIT(2)
sys/dev/ic/dwc_mmc_reg.h
129
#define DWC_MMC_INT_RESP_ERR __BIT(1)
sys/dev/ic/dwc_mmc_reg.h
136
#define DWC_MMC_STATUS_DMAREQ __BIT(31)
sys/dev/ic/dwc_mmc_reg.h
137
#define DWC_MMC_STATUS_DATA_FSM_BUSY __BIT(10)
sys/dev/ic/dwc_mmc_reg.h
138
#define DWC_MMC_STATUS_CARD_DATA_BUSY __BIT(9)
sys/dev/ic/dwc_mmc_reg.h
139
#define DWC_MMC_STATUS_CARD_PRESENT __BIT(8)
sys/dev/ic/dwc_mmc_reg.h
140
#define DWC_MMC_STATUS_FIFO_FULL __BIT(3)
sys/dev/ic/dwc_mmc_reg.h
141
#define DWC_MMC_STATUS_FIFO_EMPTY __BIT(2)
sys/dev/ic/dwc_mmc_reg.h
142
#define DWC_MMC_STATUS_TXWL_FLAG __BIT(1)
sys/dev/ic/dwc_mmc_reg.h
143
#define DWC_MMC_STATUS_RXWL_FLAG __BIT(0)
sys/dev/ic/dwc_mmc_reg.h
150
#define DWC_MMC_CDETECT_CARD_DETECT_N __BIT(0)
sys/dev/ic/dwc_mmc_reg.h
152
#define DWC_MMC_DMAC_IDMA_ON __BIT(7)
sys/dev/ic/dwc_mmc_reg.h
153
#define DWC_MMC_DMAC_FIX_BURST __BIT(1)
sys/dev/ic/dwc_mmc_reg.h
154
#define DWC_MMC_DMAC_SOFTRESET __BIT(0)
sys/dev/ic/dwc_mmc_reg.h
160
#define DWC_MMC_IDST_HOST_ABT __BIT(10)
sys/dev/ic/dwc_mmc_reg.h
161
#define DWC_MMC_IDST_ABNORMAL_INT_SUM __BIT(9)
sys/dev/ic/dwc_mmc_reg.h
162
#define DWC_MMC_IDST_NORMAL_INT_SUM __BIT(8)
sys/dev/ic/dwc_mmc_reg.h
163
#define DWC_MMC_IDST_CARD_ERR_SUM __BIT(5)
sys/dev/ic/dwc_mmc_reg.h
164
#define DWC_MMC_IDST_DES_INVALID __BIT(4)
sys/dev/ic/dwc_mmc_reg.h
165
#define DWC_MMC_IDST_FATAL_BUS_ERR __BIT(2)
sys/dev/ic/dwc_mmc_reg.h
166
#define DWC_MMC_IDST_RECEIVE_INT __BIT(1)
sys/dev/ic/dwc_mmc_reg.h
167
#define DWC_MMC_IDST_TRANSMIT_INT __BIT(0)
sys/dev/ic/dwc_mmc_reg.h
175
#define DWC_MMC_CARDTHRCTL_RDTHREN __BIT(0)
sys/dev/ic/dwc_mmc_reg.h
179
#define DWC_MMC_IDMA_CONFIG_DIC __BIT(1)
sys/dev/ic/dwc_mmc_reg.h
180
#define DWC_MMC_IDMA_CONFIG_LD __BIT(2)
sys/dev/ic/dwc_mmc_reg.h
181
#define DWC_MMC_IDMA_CONFIG_FD __BIT(3)
sys/dev/ic/dwc_mmc_reg.h
182
#define DWC_MMC_IDMA_CONFIG_CH __BIT(4)
sys/dev/ic/dwc_mmc_reg.h
183
#define DWC_MMC_IDMA_CONFIG_ER __BIT(5)
sys/dev/ic/dwc_mmc_reg.h
184
#define DWC_MMC_IDMA_CONFIG_CES __BIT(30)
sys/dev/ic/dwc_mmc_reg.h
185
#define DWC_MMC_IDMA_CONFIG_OWN __BIT(31)
sys/dev/ic/dwc_mmc_reg.h
72
#define DWC_MMC_GCTRL_USE_INTERNAL_DMAC __BIT(25)
sys/dev/ic/dwc_mmc_reg.h
73
#define DWC_MMC_GCTRL_SEND_AUTO_STOP_CCSD __BIT(10)
sys/dev/ic/dwc_mmc_reg.h
74
#define DWC_MMC_GCTRL_DMAEN __BIT(5)
sys/dev/ic/dwc_mmc_reg.h
75
#define DWC_MMC_GCTRL_INTEN __BIT(4)
sys/dev/ic/dwc_mmc_reg.h
76
#define DWC_MMC_GCTRL_DMARESET __BIT(2)
sys/dev/ic/dwc_mmc_reg.h
77
#define DWC_MMC_GCTRL_FIFORESET __BIT(1)
sys/dev/ic/dwc_mmc_reg.h
78
#define DWC_MMC_GCTRL_SOFTRESET __BIT(0)
sys/dev/ic/dwc_mmc_reg.h
83
#define DWC_MMC_CLKENA_LOWPOWERON __BIT(16)
sys/dev/ic/dwc_mmc_reg.h
84
#define DWC_MMC_CLKENA_CARDCLKON __BIT(0)
sys/dev/ic/dwc_mmc_reg.h
90
#define DWC_MMC_CMD_START __BIT(31)
sys/dev/ic/dwc_mmc_reg.h
91
#define DWC_MMC_CMD_USE_HOLD_REG __BIT(29)
sys/dev/ic/dwc_mmc_reg.h
92
#define DWC_MMC_CMD_VOL_SWITCH __BIT(28)
sys/dev/ic/dwc_mmc_reg.h
93
#define DWC_MMC_CMD_BOOT_MODE __BIT(27)
sys/dev/ic/dwc_mmc_reg.h
94
#define DWC_MMC_CMD_DISABLE_BOOT __BIT(26)
sys/dev/ic/dwc_mmc_reg.h
95
#define DWC_MMC_CMD_EXPECT_BOOT_ACT __BIT(25)
sys/dev/ic/dwc_mmc_reg.h
96
#define DWC_MMC_CMD_ENABLE_BOOT __BIT(24)
sys/dev/ic/dwc_mmc_reg.h
97
#define DWC_MMC_CMD_UPCLK_ONLY __BIT(21)
sys/dev/ic/dwc_mmc_reg.h
98
#define DWC_MMC_CMD_SEND_INIT_SEQ __BIT(15)
sys/dev/ic/dwc_mmc_reg.h
99
#define DWC_MMC_CMD_STOP_ABORT_CMD __BIT(14)
sys/dev/ic/dwc_mmc_var.h
40
#define DWC_MMC_F_DMA __BIT(0)
sys/dev/ic/dwc_mmc_var.h
41
#define DWC_MMC_F_USE_HOLD_REG __BIT(1)
sys/dev/ic/dwc_mmc_var.h
42
#define DWC_MMC_F_PWREN_INV __BIT(2)
sys/dev/ic/dwc_mmc_var.h
43
#define DWC_MMC_F_BROKEN_CD __BIT(3)
sys/dev/ic/dwc_mmc_var.h
44
#define DWC_MMC_F_NON_REMOVABLE __BIT(4)
sys/dev/ic/dwc_wdt.c
45
#define WDT_CR_RESP_MODE __BIT(1)
sys/dev/ic/dwc_wdt.c
46
#define WDT_CR_WDT_EN __BIT(0)
sys/dev/ic/dwc_wdt.c
58
#define WDT_STAT_WDT_STATUS __BIT(0)
sys/dev/ic/dwc_wdt.c
61
#define WDT_EOI_WDT_INT_CLR __BIT(0)
sys/dev/ic/hfa3861areg.h
38
#define HFA3861A_CR5_SHORTPRE __BIT(3) /* 0: long preamble,
sys/dev/ic/hfa3861areg.h
41
#define HFA3861A_CR5_RSVD1 __BIT(2) /* reserved, set to 0 */
sys/dev/ic/hfa3861areg.h
56
#define HFA3861A_CR49_SEL __BIT(7) /* 0: read-only register set 'b'
sys/dev/ic/hfa3861areg.h
75
#define HFA3861A_CR63_SFD __BIT(5) /* SFD found, sets 'a' & 'b' */
sys/dev/ic/hfa3861areg.h
76
#define HFA3861A_CR63_SHORTPRE __BIT(4) /* short preamble detected,
sys/dev/ic/hfa3861areg.h
79
#define HFA3861A_CR63_SIGNAL_OK __BIT(3) /* valid signal field,
sys/dev/ic/hfa3861areg.h
82
#define HFA3861A_CR63_CRC16_OK __BIT(2) /* valid CRC 16,
sys/dev/ic/hfa3861areg.h
85
#define HFA3861A_CR63_ANTENNA __BIT(1) /* antenna used,
sys/dev/ic/hfa3861areg.h
88
#define HFA3861A_CR63_RSVD __BIT(0) /* reserved, sets 'a' & 'b' */
sys/dev/ic/i82801lpcreg.h
176
#define SMB_TCOBASE_IOS __BIT(0) /* I/O Space */
sys/dev/ic/i82801lpcreg.h
178
#define SMB_TCOCTL_TCO_BASE_EN __BIT(8) /* TCO Base Enable */
sys/dev/ic/i82801lpcreg.h
315
#define P2SB_P2SBC_HIDE __BIT(8) /* Hide Device */
sys/dev/ic/i82801lpcreg.h
329
#define SB_SMBUS_TCOCFG_IE __BIT(7) /* TCO IRQ Enable */
sys/dev/ic/i82801lpcreg.h
339
#define SB_SMBUS_GC_NR __BIT(1) /* No Reboot */
sys/dev/ic/i82801lpcreg.h
340
#define SB_SMBUS_GC_FD __BIT(0) /* Function Disable */
sys/dev/ic/i82801lpcreg.h
342
#define SB_SMBUS_PCE_SE __BIT(3) /* Sleep Enable */
sys/dev/ic/i82801lpcreg.h
343
#define SB_SMBUS_PCE_D3HE __BIT(2) /* D3-Hot Enable */
sys/dev/ic/i82801lpcreg.h
344
#define SB_SMBUS_PCE_I3E __BIT(1) /* I3 Enable */
sys/dev/ic/i82801lpcreg.h
345
#define SB_SMBUS_PCE_PMCRE __BIT(0) /* PMC Request Enable */
sys/dev/ic/igpio.c
151
if (!(__BIT(b) & unknown_bits & val))
sys/dev/ic/igpioreg.h
44
#define IGPIO_PADCFG0_PREGFRXSEL __BIT(24)
sys/dev/ic/igpioreg.h
45
#define IGPIO_PADCFG0_RXINV __BIT(23)
sys/dev/ic/igpioreg.h
46
#define IGPIO_PADCFG0_GPIROUTIOXAPIC __BIT(20)
sys/dev/ic/igpioreg.h
47
#define IGPIO_PADCFG0_GPIROUTSCI __BIT(19)
sys/dev/ic/igpioreg.h
48
#define IGPIO_PADCFG0_GPIROUTSMI __BIT(18)
sys/dev/ic/igpioreg.h
49
#define IGPIO_PADCFG0_GPIROUTNMI __BIT(17)
sys/dev/ic/igpioreg.h
53
#define IGPIO_PADCFG0_GPIORXDIS __BIT(9)
sys/dev/ic/igpioreg.h
54
#define IGPIO_PADCFG0_GPIOTXDIS __BIT(8)
sys/dev/ic/igpioreg.h
55
#define IGPIO_PADCFG0_GPIORXSTATE __BIT(1)
sys/dev/ic/igpioreg.h
56
#define IGPIO_PADCFG0_GPIOTXSTATE __BIT(0)
sys/dev/ic/igpioreg.h
59
#define IGPIO_PADCFG1_TERM_UP __BIT(13)
sys/dev/ic/igpioreg.h
62
#define IGPIO_PADCFG1_TERM_20K __BIT(2)
sys/dev/ic/igpioreg.h
63
#define IGPIO_PADCFG1_TERM_5K __BIT(1)
sys/dev/ic/igpioreg.h
64
#define IGPIO_PADCFG1_TERM_1K __BIT(0)
sys/dev/ic/igpioreg.h
65
#define IGPIO_PADCFG1_TERM_833 (__BIT(1) | BIT(0))
sys/dev/ic/max2820reg.h
101
#define MAX2820_ENABLE_RSVD0 __BIT(0) /* reserved */
sys/dev/ic/max2820reg.h
107
#define MAX2820_SYNTH_ICP __BIT(6) /* Charge-Pump Current Select
sys/dev/ic/max2820reg.h
143
#define MAX2820_RECEIVE_SF __BIT(3) /* Special Function Select
sys/dev/ic/max2820reg.h
49
#define MAX2820_ENABLE_RSVD1 __BIT(11) /* reserved */
sys/dev/ic/max2820reg.h
50
#define MAX2820_ENABLE_PAB __BIT(10) /* Transmit Baseband Filters
sys/dev/ic/max2820reg.h
56
#define MAX2820_ENABLE_TXFLT __BIT(9) /* Transmit Baseband Filters
sys/dev/ic/max2820reg.h
62
#define MAX2820_ENABLE_TXUVD __BIT(8) /* Tx Upconverter, VGA, and
sys/dev/ic/max2820reg.h
68
#define MAX2820_ENABLE_DET __BIT(7) /* Receive Detector Enable
sys/dev/ic/max2820reg.h
73
#define MAX2820_ENABLE_RXDFA __BIT(6) /* Rx Downconverter, Filters,
sys/dev/ic/max2820reg.h
79
#define MAX2820_ENABLE_RXLNA __BIT(5) /* Receive LNA Enable
sys/dev/ic/max2820reg.h
84
#define MAX2820_ENABLE_AT __BIT(4) /* Auto-tuner Enable
sys/dev/ic/max2820reg.h
89
#define MAX2820_ENABLE_CP __BIT(3) /* PLL Charge-Pump Enable
sys/dev/ic/max2820reg.h
93
#define MAX2820_ENABLE_PLL __BIT(2) /* PLL Enable
sys/dev/ic/max2820reg.h
97
#define MAX2820_ENABLE_VCO __BIT(1) /* VCO Enable
sys/dev/ic/mcp23xxxgpio.c
195
val = data & __BIT(epin) ? GPIO_PIN_HIGH : GPIO_PIN_LOW;
sys/dev/ic/mcp23xxxgpio.c
220
data |= __BIT(epin);
sys/dev/ic/mcp23xxxgpio.c
222
data &= ~__BIT(epin);
sys/dev/ic/mcp23xxxgpio.c
241
const uint8_t bit = __BIT(epin);
sys/dev/ic/mcp23xxxgpioreg.h
110
#define IOCON_BANK __BIT(7) /* select address layout (23x1x only) */
sys/dev/ic/mcp23xxxgpioreg.h
111
#define IOCON_MIRROR __BIT(6) /* mirror INTA/INTB outputs (23x1x only) */
sys/dev/ic/mcp23xxxgpioreg.h
112
#define IOCON_SEQOP __BIT(5) /* sequential address operation */
sys/dev/ic/mcp23xxxgpioreg.h
113
#define IOCON_DISLW __BIT(4) /* slew rate SDA output */
sys/dev/ic/mcp23xxxgpioreg.h
114
#define IOCON_HAEN __BIT(3) /* hardware address enable bit (SPI only) */
sys/dev/ic/mcp23xxxgpioreg.h
115
#define IOCON_ODR __BIT(2) /* configure INT pin as open drain */
sys/dev/ic/mcp23xxxgpioreg.h
116
#define IOCON_INTPOL __BIT(1) /* INT pin polarity (unless ODR is set) */
sys/dev/ic/mpc106reg.h
100
#define MPC106_PICR2_L2_UPD_EN __BIT(31) /* Service L2 cache misses */
sys/dev/ic/mpc106reg.h
101
#define MPC106_PICR2_L2_EN __BIT(30) /* L2 cache internal enable */
sys/dev/ic/mpc106reg.h
103
#define MPC106_PICR2_NOSERCFG __BIT(29) /* serialized config writes */
sys/dev/ic/mpc106reg.h
104
#define MPC106_PICR2_FLUSH_L2 __BIT(28) /* 0->1: flush L2 cache */
sys/dev/ic/mpc106reg.h
105
#define MPC106_PICR2_NOSNOOP_EN __BIT(27) /* snoop transactions */
sys/dev/ic/mpc106reg.h
106
#define MPC106_PICR2_CF_FF0_LOC __BIT(26) /* ROM remapping enable */
sys/dev/ic/mpc106reg.h
107
#define MPC106_PICR2_FLASH_LOCK __BIT(25) /* Flash write lockout */
sys/dev/ic/mpc106reg.h
108
#define MPC106_PICR2_FAST_L2_MODE __BIT(24) /* Fast L2 mode timing */
sys/dev/ic/mpc106reg.h
124
#define MPC106_PICR2_MOD_HIGH __BIT(17) /* Cache modified polarity */
sys/dev/ic/mpc106reg.h
125
#define MPC106_PICR2_HIT_HIGH __BIT(16) /* Cache hit polarity */
sys/dev/ic/mpc106reg.h
126
#define MPC106_PICR2_RSVD2 __BIT(15)
sys/dev/ic/mpc106reg.h
127
#define MPC106_PICR2_ADDR_ONLY_DISABLE __BIT(14) /* L2 ignores CLEAN/
sys/dev/ic/mpc106reg.h
129
#define MPC106_PICR2_HOLD __BIT(13) /* L2 tag address hold */
sys/dev/ic/mpc106reg.h
130
#define MPC106_PICR2_INV_MODE __BIT(12) /* L2 invalidate mode enable */
sys/dev/ic/mpc106reg.h
131
#define MPC106_PICR2_RWITM __BIT(11) /* read with intent to modify
sys/dev/ic/mpc106reg.h
138
#define MPC106_PICR2_BANKS __BIT(8) /* L2: nrof banks */
sys/dev/ic/mpc106reg.h
139
#define MPC106_PICR2_FAST_CASTOUT __BIT(7) /* L2 Fast castout timing */
sys/dev/ic/mpc106reg.h
140
#define MPC106_PICR2_TOE_WIDTH __BIT(6) /* TOE 0:2, 1:3 clock cycles */
sys/dev/ic/mpc106reg.h
151
#define MPC106_PICR2_DOE __BIT(1) /* L2 first data read timing */
sys/dev/ic/mpc106reg.h
152
#define MPC106_PICR2_WDATA __BIT(0) /* L2 first data write timing*/
sys/dev/ic/mpc106reg.h
171
#define MPC106_MCCR1_501_MODE __BIT(22) /* 501 mode conf signal */
sys/dev/ic/mpc106reg.h
172
#define MPC106_MCCR1_8N64 __BIT(21)
sys/dev/ic/mpc106reg.h
173
#define MPC106_MCCR1_BURST __BIT(20)
sys/dev/ic/mpc106reg.h
174
#define MPC106_MCCR1_MEMGO __BIT(19)
sys/dev/ic/mpc106reg.h
175
#define MPC106_MCCR1_SREN __BIT(18)
sys/dev/ic/mpc106reg.h
176
#define MPC106_MCCR1_RAMTYPE __BIT(17) /* 0:SDRAM 1:DRAM/EDO */
sys/dev/ic/mpc106reg.h
177
#define MPC106_MCCR1_PCKEN __BIT(16) /* dis/enable parity */
sys/dev/ic/mpc106reg.h
182
#define MPC106_MCRR2_BSTOPRE0 __BIT(21)
sys/dev/ic/mpc106reg.h
183
#define MPC106_MCRR2_BSTOPRE1 __BIT(20)
sys/dev/ic/mpc106reg.h
184
#define MPC106_MCRR2_EXT_ECM_PAR_EN __BIT(19) /* ext. ECM parity check */
sys/dev/ic/mpc106reg.h
185
#define MPC106_MCRR2_EXT_ECM_ECC_EN __BIT(18) /* ext. ECM ECC enable */
sys/dev/ic/mpc106reg.h
186
#define MPC106_MCRR2_ECC_EN __BIT(17) /* ECC enable */
sys/dev/ic/mpc106reg.h
187
#define MPC106_MCRR2_EDO __BIT(16) /* EDO enable */
sys/dev/ic/mpc106reg.h
189
#define MPC106_MCRR2_BUFMODE __BIT(1) /* buffer mode */
sys/dev/ic/mpc106reg.h
190
#define MPC106_MCRR2_RMW_PAR __BIT(0) /* RMW parity enable */
sys/dev/ic/mpc106reg.h
62
#define MPC106_PICR1_CACHE_1G __BIT(21) /* Cache 0-1G only */
sys/dev/ic/mpc106reg.h
63
#define MPC106_PICR1_RCS0 __BIT(20) /* ROM on 0:PCI, 1:60x bus */
sys/dev/ic/mpc106reg.h
64
#define MPC106_PICR1_XIO_MODE __BIT(19) /* 0:Contig, 1:Discontig mode */
sys/dev/ic/mpc106reg.h
70
#define MPC106_PICR1_XATS __BIT(16) /* Address map 0:B, 1:A */
sys/dev/ic/mpc106reg.h
73
#define MPC106_PICR1_LBA_EN __BIT(13) /* Local bus slave enable */
sys/dev/ic/mpc106reg.h
74
#define MPC106_PICR1_FLASHWR_EN __BIT(12) /* Flash writes enable */
sys/dev/ic/mpc106reg.h
75
#define MPC106_PICR1_MCP_EN __BIT(11) /* Machine check enable */
sys/dev/ic/mpc106reg.h
76
#define MPC106_PICR1_TEA_EN __BIT(10) /* Transfer error enable */
sys/dev/ic/mpc106reg.h
77
#define MPC106_PICR1_DPARK __BIT(9) /* Data bus park */
sys/dev/ic/mpc106reg.h
78
#define MPC106_PICR1_EXT_L2_EN __BIT(8) /* external l2 enable */
sys/dev/ic/mpc106reg.h
79
#define MPC106_PICR1_NO_PORT_REGS __BIT(7) /* Implement ext. conf regs */
sys/dev/ic/mpc106reg.h
80
#define MPC106_PICR1_ST_GATH_EN __BIT(6) /* Store gathering enable */
sys/dev/ic/mpc106reg.h
81
#define MPC106_PICR1_LE_MODE __BIT(5) /* 0:Big, 1:Little endian */
sys/dev/ic/mpc106reg.h
82
#define MPC106_PICR1_LOOP_SNOOP __BIT(4) /* Snoop looping enable */
sys/dev/ic/mpc106reg.h
83
#define MPC106_PICR1_APARK __BIT(3) /* Address bus park */
sys/dev/ic/mpc106reg.h
84
#define MPC106_PICR1_SPECREADS __BIT(2) /* Speculative read enable */
sys/dev/ic/msm6242breg.h
43
#define MSM6242B_PMAM_BIT __BIT(2)
sys/dev/ic/msm6242breg.h
54
#define MSM6242B_CONTROL_D_HOLD __BIT(0)
sys/dev/ic/msm6242breg.h
55
#define MSM6242B_CONTROL_D_BUSY __BIT(1)
sys/dev/ic/msm6242breg.h
56
#define MSM6242B_CONTROL_D_IRQF __BIT(2)
sys/dev/ic/msm6242breg.h
57
#define MSM6242B_CONTROL_D_30SECADJ __BIT(3)
sys/dev/ic/msm6242breg.h
62
#define MSM6242B_CONTROL_F_24H __BIT(2)
sys/dev/ic/mvsata.c
2786
if ((aslots & __BIT(quetag)) == 0) {
sys/dev/ic/mvsata.c
2877
if ((aslots & __BIT(i)) == 0)
sys/dev/ic/nvmereg.h
169
#define NVM_SQE_CQ_IEN __BIT(1)
sys/dev/ic/nvmereg.h
170
#define NVM_SQE_Q_PC __BIT(0)
sys/dev/ic/nvmereg.h
198
#define NVM_SQE_IO_LR __BIT(15) /* Limited Retry */
sys/dev/ic/nvmereg.h
199
#define NVM_SQE_IO_FUA __BIT(14) /* Force Unit Access (bypass cache) */
sys/dev/ic/nvmereg.h
202
#define NVM_SQE_IO_INCOMP __BIT(7) /* Incompressible */
sys/dev/ic/nvmereg.h
203
#define NVM_SQE_IO_SEQ __BIT(6) /* Sequential request */
sys/dev/ic/nvmereg.h
206
#define NVM_SQE_IO_LAT_IDLE __BIT(4) /* Latency: idle */
sys/dev/ic/nvmereg.h
207
#define NVM_SQE_IO_LAT_NORMAL __BIT(5) /* Latency: normal */
sys/dev/ic/nvmereg.h
241
#define NVME_CQE_DNR __BIT(15)
sys/dev/ic/nvmereg.h
242
#define NVME_CQE_M __BIT(14)
sys/dev/ic/nvmereg.h
302
#define NVME_CQE_PHASE __BIT(0)
sys/dev/ic/nvmereg.h
31
#define NVME_CAP_CSS_NVM __BIT(0)
sys/dev/ic/nvmereg.h
32
#define NVME_CAP_NSSRS(_r) ISSET((_r), __BIT(36))
sys/dev/ic/nvmereg.h
33
#define NVME_CAP_DSTRD(_r) __BIT(2 + (((_r) >> 32) & 0xf)) /* bytes */
sys/dev/ic/nvmereg.h
36
#define NVME_CAP_AMS_WRR __BIT(0)
sys/dev/ic/nvmereg.h
37
#define NVME_CAP_AMS_VENDOR __BIT(1)
sys/dev/ic/nvmereg.h
371
#define NVM_SET_FEATURES_SV __BIT(31) /* Persist */
sys/dev/ic/nvmereg.h
373
#define NVM_VOLATILE_WRITE_CACHE_WCE __BIT(0) /* Write Cache Enable */
sys/dev/ic/nvmereg.h
38
#define NVME_CAP_CQR(_r) ISSET((_r), __BIT(16))
sys/dev/ic/nvmereg.h
380
#define NVME_PSD_NOPS __BIT(1)
sys/dev/ic/nvmereg.h
381
#define NVME_PSD_MPS __BIT(0)
sys/dev/ic/nvmereg.h
444
#define NVME_ID_CTRLR_OACS_DOORBELL_BC __BIT(8)
sys/dev/ic/nvmereg.h
445
#define NVME_ID_CTRLR_OACS_VIRT_MGMT __BIT(7)
sys/dev/ic/nvmereg.h
446
#define NVME_ID_CTRLR_OACS_NVME_MI __BIT(6)
sys/dev/ic/nvmereg.h
447
#define NVME_ID_CTRLR_OACS_DIRECTIVES __BIT(5)
sys/dev/ic/nvmereg.h
448
#define NVME_ID_CTRLR_OACS_DEV_SELFTEST __BIT(4)
sys/dev/ic/nvmereg.h
449
#define NVME_ID_CTRLR_OACS_NS __BIT(3)
sys/dev/ic/nvmereg.h
450
#define NVME_ID_CTRLR_OACS_FW __BIT(2)
sys/dev/ic/nvmereg.h
451
#define NVME_ID_CTRLR_OACS_FORMAT __BIT(1)
sys/dev/ic/nvmereg.h
452
#define NVME_ID_CTRLR_OACS_SECURITY __BIT(0)
sys/dev/ic/nvmereg.h
457
#define NVME_ID_CTRLR_FRMW_NOREQ_RESET __BIT(4)
sys/dev/ic/nvmereg.h
459
#define NVME_ID_CTRLR_FRMW_SLOT1_RO __BIT(0)
sys/dev/ic/nvmereg.h
461
#define NVME_ID_CTRLR_LPA_CMD_EFFECT __BIT(1)
sys/dev/ic/nvmereg.h
462
#define NVME_ID_CTRLR_LPA_NS_SMART __BIT(0)
sys/dev/ic/nvmereg.h
470
#define NVME_ID_CTRLR_APSTA_PRESENT __BIT(0)
sys/dev/ic/nvmereg.h
521
#define NVME_ID_CTRLR_ONCS_TIMESTAMP __BIT(6)
sys/dev/ic/nvmereg.h
522
#define NVME_ID_CTRLR_ONCS_RESERVATION __BIT(5)
sys/dev/ic/nvmereg.h
523
#define NVME_ID_CTRLR_ONCS_SET_FEATURES __BIT(4)
sys/dev/ic/nvmereg.h
524
#define NVME_ID_CTRLR_ONCS_WRITE_ZERO __BIT(3)
sys/dev/ic/nvmereg.h
525
#define NVME_ID_CTRLR_ONCS_DSM __BIT(2)
sys/dev/ic/nvmereg.h
526
#define NVME_ID_CTRLR_ONCS_WRITE_UNC __BIT(1)
sys/dev/ic/nvmereg.h
527
#define NVME_ID_CTRLR_ONCS_COMPARE __BIT(0)
sys/dev/ic/nvmereg.h
531
#define NVME_ID_CTRLR_FNA_CRYPTO_ERASE __BIT(2)
sys/dev/ic/nvmereg.h
532
#define NVME_ID_CTRLR_FNA_ERASE_ALL __BIT(1)
sys/dev/ic/nvmereg.h
533
#define NVME_ID_CTRLR_FNA_FORMAT_ALL __BIT(0)
sys/dev/ic/nvmereg.h
535
#define NVME_ID_CTRLR_VWC_PRESENT __BIT(0)
sys/dev/ic/nvmereg.h
576
#define NVME_ID_NS_NSFEAT_LOGICAL_BLK_ERR __BIT(2)
sys/dev/ic/nvmereg.h
577
#define NVME_ID_NS_NSFEAT_NS __BIT(1)
sys/dev/ic/nvmereg.h
578
#define NVME_ID_NS_NSFEAT_THIN_PROV __BIT(0)
sys/dev/ic/nvmereg.h
588
#define NVME_ID_NS_DPS_MD_START __BIT(3)
sys/dev/ic/nvmereg.h
74
#define NVME_CC_EN __BIT(0)
sys/dev/ic/nvmereg.h
80
#define NVME_CSTS_CFS __BIT(1)
sys/dev/ic/nvmereg.h
81
#define NVME_CSTS_RDY __BIT(0)
sys/dev/ic/nvmereg.h
86
#define NVME_AQA_ACQS_R(_v) ((_v >> 16) & (__BIT(12) - 1))
sys/dev/ic/nvmereg.h
89
#define NVME_AQA_ASQS_R(_v) (_v & (__BIT(12) - 1))
sys/dev/ic/nvmevar.h
105
#define NVME_NS_F_OPEN __BIT(0)
sys/dev/ic/nvmevar.h
164
#define NVME_F_ATTACHED __BIT(0)
sys/dev/ic/nvmevar.h
165
#define NVME_F_OPEN __BIT(1)
sys/dev/ic/nvmevar.h
168
#define NVME_QUIRK_DELAY_B4_CHK_RDY __BIT(0)
sys/dev/ic/nvmevar.h
169
#define NVME_QUIRK_NOMSI __BIT(1)
sys/dev/ic/nvmevar.h
66
#define NVME_NS_CTX_F_READ __BIT(0)
sys/dev/ic/nvmevar.h
67
#define NVME_NS_CTX_F_POLL __BIT(1)
sys/dev/ic/nvmevar.h
68
#define NVME_NS_CTX_F_FUA __BIT(2)
sys/dev/ic/pl031.c
45
#define RTCCR_START __BIT(0)
sys/dev/ic/pl041.c
48
#define AACITXCR_TXFEN __BIT(16)
sys/dev/ic/pl041.c
49
#define AACITXCR_TXCM __BIT(15)
sys/dev/ic/pl041.c
52
#define AACITXCR_TX(n) __BIT(n)
sys/dev/ic/pl041.c
53
#define AACITXCR_TXEN __BIT(0)
sys/dev/ic/pl041.c
55
#define AACISR_TXFF __BIT(5)
sys/dev/ic/pl041.c
56
#define AACISR_TXHE __BIT(3)
sys/dev/ic/pl041.c
58
#define AACIISR_URINTR __BIT(5)
sys/dev/ic/pl041.c
59
#define AACIISR_TXINTR __BIT(2)
sys/dev/ic/pl041.c
61
#define AACIIE_TXUIE __BIT(5)
sys/dev/ic/pl041.c
62
#define AACIIE_TXIE __BIT(2)
sys/dev/ic/pl050.c
43
#define KMIRXINTREN __BIT(4)
sys/dev/ic/pl050.c
44
#define KMIEN __BIT(2)
sys/dev/ic/pl050.c
46
#define TXEMPTY __BIT(6)
sys/dev/ic/pl050.c
47
#define RXFULL __BIT(4)
sys/dev/ic/pl050.c
51
#define KMIRXINTR __BIT(0)
sys/dev/ic/pl061.c
64
if ((cnf & __BIT(pin)) != 0)
sys/dev/ic/pl181reg.h
100
#define MMCI_INT_DATA_END __BIT(8)
sys/dev/ic/pl181reg.h
101
#define MMCI_INT_DATA_BLOCK_END __BIT(10)
sys/dev/ic/pl181reg.h
102
#define MMCI_INT_CMD_ACTIVE __BIT(11)
sys/dev/ic/pl181reg.h
103
#define MMCI_INT_TX_ACTIVE __BIT(12)
sys/dev/ic/pl181reg.h
104
#define MMCI_INT_RX_ACTIVE __BIT(13)
sys/dev/ic/pl181reg.h
105
#define MMCI_INT_TX_FIFO_HALF_EMPTY __BIT(14)
sys/dev/ic/pl181reg.h
106
#define MMCI_INT_RX_FIFO_HALF_FULL __BIT(15)
sys/dev/ic/pl181reg.h
107
#define MMCI_INT_TX_FIFO_FULL __BIT(16)
sys/dev/ic/pl181reg.h
108
#define MMCI_INT_RX_FIFO_FULL __BIT(17)
sys/dev/ic/pl181reg.h
109
#define MMCI_INT_TX_FIFO_EMPTY __BIT(18)
sys/dev/ic/pl181reg.h
110
#define MMCI_INT_RX_FIFO_EMPTY __BIT(19)
sys/dev/ic/pl181reg.h
111
#define MMCI_INT_TX_DATA_AVAIL __BIT(20)
sys/dev/ic/pl181reg.h
112
#define MMCI_INT_RX_DATA_AVAIL __BIT(21)
sys/dev/ic/pl181reg.h
65
#define MMCI_POWER_OD __BIT(6)
sys/dev/ic/pl181reg.h
66
#define MMCI_POWER_ROD __BIT(7)
sys/dev/ic/pl181reg.h
69
#define MMCI_CLOCK_ENABLE __BIT(8)
sys/dev/ic/pl181reg.h
70
#define MMCI_CLOCK_PWRSAVE __BIT(9)
sys/dev/ic/pl181reg.h
71
#define MMCI_CLOCK_BYPASS __BIT(10)
sys/dev/ic/pl181reg.h
74
#define MMCI_COMMAND_RESPONSE __BIT(6)
sys/dev/ic/pl181reg.h
75
#define MMCI_COMMAND_LONGRSP __BIT(7)
sys/dev/ic/pl181reg.h
76
#define MMCI_COMMAND_INTERRUPT __BIT(8)
sys/dev/ic/pl181reg.h
77
#define MMCI_COMMAND_PENDING __BIT(9)
sys/dev/ic/pl181reg.h
78
#define MMCI_COMMAND_ENABLE __BIT(10)
sys/dev/ic/pl181reg.h
84
#define MMCI_DATA_CTRL_ENABLE __BIT(0)
sys/dev/ic/pl181reg.h
85
#define MMCI_DATA_CTRL_DIRECTION __BIT(1)
sys/dev/ic/pl181reg.h
86
#define MMCI_DATA_CTRL_MODE __BIT(2)
sys/dev/ic/pl181reg.h
87
#define MMCI_DATA_CTRL_DMAENABLE __BIT(3)
sys/dev/ic/pl181reg.h
92
#define MMCI_INT_CMD_CRC_FAIL __BIT(0)
sys/dev/ic/pl181reg.h
93
#define MMCI_INT_DATA_CRC_FAIL __BIT(1)
sys/dev/ic/pl181reg.h
94
#define MMCI_INT_CMD_TIMEOUT __BIT(2)
sys/dev/ic/pl181reg.h
95
#define MMCI_INT_DATA_TIMEOUT __BIT(3)
sys/dev/ic/pl181reg.h
96
#define MMCI_INT_TX_UNDERRUN __BIT(4)
sys/dev/ic/pl181reg.h
97
#define MMCI_INT_RX_OVERRUN __BIT(5)
sys/dev/ic/pl181reg.h
98
#define MMCI_INT_CMD_RESP_END __BIT(6)
sys/dev/ic/pl181reg.h
99
#define MMCI_INT_CMD_SENT __BIT(7)
sys/dev/ic/rf3000reg.h
107
#define RF3000_OPTIONS2_LNAGS_DELAY __BIT(7)
sys/dev/ic/rf3000reg.h
110
#define RF3000_OPTIONS2_RTG_THRESH __BIT(2)
sys/dev/ic/rf3000reg.h
60
#define RF3000_RXSTAT_SHORTPRE __BIT(3)/* 1: short preamble */
sys/dev/ic/rf3000reg.h
61
#define RF3000_RXSTAT_ACQ __BIT(2)/* 1: acquired */
sys/dev/ic/rf3000reg.h
62
#define RF3000_RXSTAT_SFD __BIT(1)/* 1: SFD detected */
sys/dev/ic/rf3000reg.h
63
#define RF3000_RXSTAT_CRC __BIT(0)/* 1: CRC invalid */
sys/dev/ic/rf3000reg.h
73
#define RF3000_DIVCTL_ENABLE __BIT(7)/* enable diversity */
sys/dev/ic/rf3000reg.h
74
#define RF3000_DIVCTL_ANTSEL __BIT(6)/* if ENABLE = 0, set
sys/dev/ic/rf3000reg.h
81
#define RF3000_GAINCTL_SCRAMBLER __BIT(1)
sys/dev/ic/rf3000reg.h
86
#define RF3000_HIGAINCAL_DSSSPAD __BIT(6)/* 6dB gain pad for DSSS
sys/dev/ic/rf3000reg.h
93
#define RF3000_OPTIONS1_SAT_THRESH_SIGN __BIT(7)
sys/dev/ic/rf3000reg.h
95
#define RF3000_OPTIONS1_ALTAGC __BIT(4)/* 1: retrigger AGC
sys/dev/ic/rf3000reg.h
99
#define RF3000_OPTIONS1_ALTBUS __BIT(3)/* 1: enable alternate
sys/dev/ic/rng200reg.h
42
#define RNG200_RBG_ENABLE __BIT(1)
sys/dev/ic/rng200reg.h
48
#define RNG200_MASTER_FAIL __BIT(31)
sys/dev/ic/rng200reg.h
49
#define RNG200_NIST_FAIL __BIT(5)
sys/dev/ic/rtl81x9.c
563
hashes[0] |= __BIT(h);
sys/dev/ic/rtl81x9.c
565
hashes[1] |= __BIT(h - 32);
sys/dev/ic/rtl81x9reg.h
236
#define RTK_MISC_TXPLA_RST __BIT(29)
sys/dev/ic/rtl81x9reg.h
237
#define RTK_MISC_DISABLE_LAN_EN __BIT(23) /* Enable GPIO pin */
sys/dev/ic/rtl81x9reg.h
238
#define RTK_MISC_PWM_EN __BIT(22)
sys/dev/ic/rtl81x9reg.h
239
#define RTK_MISC_RXDV_GATED_EN __BIT(19)
sys/dev/ic/rtl81x9reg.h
240
#define RTK_MISC_EARLY_TALLY_EN __BIT(16)
sys/dev/ic/rtsxvar.h
54
#define RTSX_F_CARD_PRESENT __BIT(0)
sys/dev/ic/rtsxvar.h
55
#define RTSX_F_SDIO_SUPPORT __BIT(1)
sys/dev/ic/rtsxvar.h
56
#define RTSX_F_5209 __BIT(2)
sys/dev/ic/rtsxvar.h
57
#define RTSX_F_5227 __BIT(3)
sys/dev/ic/rtsxvar.h
58
#define RTSX_F_5229 __BIT(4)
sys/dev/ic/rtsxvar.h
59
#define RTSX_F_5229_TYPE_C __BIT(5)
sys/dev/ic/rtsxvar.h
60
#define RTSX_F_525A __BIT(6)
sys/dev/ic/rtsxvar.h
61
#define RTSX_F_8402 __BIT(7)
sys/dev/ic/rtsxvar.h
62
#define RTSX_F_8411 __BIT(8)
sys/dev/ic/rtsxvar.h
63
#define RTSX_F_8411B __BIT(9)
sys/dev/ic/rtsxvar.h
64
#define RTSX_F_8411B_QFN48 __BIT(10)
sys/dev/ic/rtwnreg.h
943
#define R92C_RD_CTRL_DIS_EDCA_CNT_DWN __BIT(11)
sys/dev/ic/rtwnreg.h
946
#define R92C_RATE_SHORTGI __BIT(6)
sys/dev/ic/rtwreg.h
100
#define RTW_CR_MULRW __BIT(0)/* PCI Multiple Read/Write enable: 1 enables,
sys/dev/ic/rtwreg.h
107
#define RTW_INTR_TXFOVW __BIT(15) /* Tx FIFO underflow */
sys/dev/ic/rtwreg.h
108
#define RTW_INTR_TIMEOUT __BIT(14) /* Time Out: 1 indicates
sys/dev/ic/rtwreg.h
115
#define RTW_INTR_BCNINT __BIT(13)
sys/dev/ic/rtwreg.h
120
#define RTW_INTR_ATIMINT __BIT(12)
sys/dev/ic/rtwreg.h
122
#define RTW_INTR_TBDER __BIT(11)
sys/dev/ic/rtwreg.h
123
#define RTW_INTR_TBDOK __BIT(10) /* Tx Beacon Descriptor OK */
sys/dev/ic/rtwreg.h
124
#define RTW_INTR_THPDER __BIT(9)/* Tx High Priority Descriptor Error:
sys/dev/ic/rtwreg.h
127
#define RTW_INTR_THPDOK __BIT(8)/* Tx High Priority Descriptor OK */
sys/dev/ic/rtwreg.h
128
#define RTW_INTR_TNPDER __BIT(7)/* Tx Normal Priority Descriptor Error:
sys/dev/ic/rtwreg.h
131
#define RTW_INTR_TNPDOK __BIT(6)/* Tx Normal Priority Descriptor OK */
sys/dev/ic/rtwreg.h
132
#define RTW_INTR_RXFOVW __BIT(5)/* Rx FIFO Overflow: either RDU (see below)
sys/dev/ic/rtwreg.h
135
#define RTW_INTR_RDU __BIT(4)/* Rx Descriptor Unavailable */
sys/dev/ic/rtwreg.h
136
#define RTW_INTR_TLPDER __BIT(3)/* Tx Normal Priority Descriptor Error
sys/dev/ic/rtwreg.h
139
#define RTW_INTR_TLPDOK __BIT(2)/* Tx Normal Priority Descriptor OK */
sys/dev/ic/rtwreg.h
140
#define RTW_INTR_RER __BIT(1)/* Rx Error: CRC32 or ICV error */
sys/dev/ic/rtwreg.h
141
#define RTW_INTR_ROK __BIT(0)/* Rx OK */
sys/dev/ic/rtwreg.h
152
#define RTW_TCR_CWMIN __BIT(31)/* 1: CWmin = 8, 0: CWmin = 32. */
sys/dev/ic/rtwreg.h
153
#define RTW_TCR_SWSEQ __BIT(30)/* 1: host assigns 802.11 sequence number,
sys/dev/ic/rtwreg.h
166
#define RTW_TCR_SAT __BIT(24)
sys/dev/ic/rtwreg.h
179
#define RTW_TCR_DISCW __BIT(20)
sys/dev/ic/rtwreg.h
182
#define RTW_TCR_ICV __BIT(19)
sys/dev/ic/rtwreg.h
191
#define RTW_TCR_CRC __BIT(16) /* 0: RTL8180 appends CRC32
sys/dev/ic/rtwreg.h
204
#define RTW_RCR_ONLYERLPKT __BIT(31)
sys/dev/ic/rtwreg.h
206
#define RTW_RCR_ENCS2 __BIT(30)
sys/dev/ic/rtwreg.h
208
#define RTW_RCR_ENCS1 __BIT(29)
sys/dev/ic/rtwreg.h
209
#define RTW_RCR_ENMARP __BIT(28) /* enable MAC auto-reset PHY */
sys/dev/ic/rtwreg.h
214
#define RTW_RCR_CBSSID __BIT(23)
sys/dev/ic/rtwreg.h
216
#define RTW_RCR_APWRMGT __BIT(22)
sys/dev/ic/rtwreg.h
220
#define RTW_RCR_ADD3 __BIT(21)
sys/dev/ic/rtwreg.h
221
#define RTW_RCR_AMF __BIT(20) /* accept management frames */
sys/dev/ic/rtwreg.h
222
#define RTW_RCR_ACF __BIT(19) /* accept control frames */
sys/dev/ic/rtwreg.h
223
#define RTW_RCR_ADF __BIT(18) /* accept data frames */
sys/dev/ic/rtwreg.h
235
#define RTW_RCR_AICV __BIT(12)/* accept frames w/ ICV errors */
sys/dev/ic/rtwreg.h
249
#define RTW_RCR_9356SEL __BIT(6)
sys/dev/ic/rtwreg.h
251
#define RTW_RCR_ACRC32 __BIT(5)/* accept frames w/ CRC32 errors */
sys/dev/ic/rtwreg.h
252
#define RTW_RCR_AB __BIT(3)/* accept broadcast frames */
sys/dev/ic/rtwreg.h
253
#define RTW_RCR_AM __BIT(2)/* accept multicast frames */
sys/dev/ic/rtwreg.h
255
#define RTW_RCR_APM __BIT(1)
sys/dev/ic/rtwreg.h
256
#define RTW_RCR_AAP __BIT(0)/* accept frames w/ destination */
sys/dev/ic/rtwreg.h
312
#define RTW_9346CR_EECS __BIT(3)
sys/dev/ic/rtwreg.h
313
#define RTW_9346CR_EESK __BIT(2)
sys/dev/ic/rtwreg.h
314
#define RTW_9346CR_EEDI __BIT(1)
sys/dev/ic/rtwreg.h
315
#define RTW_9346CR_EEDO __BIT(0) /* read-only */
sys/dev/ic/rtwreg.h
318
#define RTW_CONFIG0_WEP40 __BIT(7)/* implements 40-bit WEP,
sys/dev/ic/rtwreg.h
321
#define RTW_CONFIG0_WEP104 __BIT(6)/* implements 104-bit WEP,
sys/dev/ic/rtwreg.h
325
#define RTW_CONFIG0_LEDGPOEN __BIT(4)/* 1: RTW_PSR_LEDGPO[01] control
sys/dev/ic/rtwreg.h
332
#define RTW_CONFIG0_AUXPWR __BIT(3)
sys/dev/ic/rtwreg.h
368
#define RTW_CONFIG1_LWACT __BIT(4)
sys/dev/ic/rtwreg.h
370
#define RTW_CONFIG1_MEMMAP __BIT(3)/* using PCI memory space, read-only */
sys/dev/ic/rtwreg.h
371
#define RTW_CONFIG1_IOMAP __BIT(2)/* using PCI I/O space, read-only */
sys/dev/ic/rtwreg.h
372
#define RTW_CONFIG1_VPD __BIT(1)/* if set, VPD from offsets
sys/dev/ic/rtwreg.h
377
#define RTW_CONFIG1_PMEN __BIT(0)/* Power Management Enable: TBD */
sys/dev/ic/rtwreg.h
380
#define RTW_CONFIG2_LCK __BIT(7)/* clocks are locked, read-only:
sys/dev/ic/rtwreg.h
384
#define RTW_CONFIG2_ANT __BIT(6) /* diversity enabled, read-only */
sys/dev/ic/rtwreg.h
385
#define RTW_CONFIG2_DPS __BIT(3) /* Descriptor Polling State: enable
sys/dev/ic/rtwreg.h
388
#define RTW_CONFIG2_PAPESIGN __BIT(2) /* TBD, from EEPROM */
sys/dev/ic/rtwreg.h
401
#define RTW_ANAPARM_TXDACOFF __BIT(27) /* 1: disable Tx DAC,
sys/dev/ic/rtwreg.h
470
#define RTW_CONFIG3_GNTSEL __BIT(7) /* Grant Select, read-only */
sys/dev/ic/rtwreg.h
471
#define RTW_CONFIG3_PARMEN __BIT(6) /* Set RTW_CONFIG3_PARMEN and
sys/dev/ic/rtwreg.h
475
#define RTW_CONFIG3_MAGIC __BIT(5)/* Valid when RTW_CONFIG1_PMEN is
sys/dev/ic/rtwreg.h
479
#define RTW_CONFIG3_CARDBEN __BIT(3)/* Cardbus-related registers
sys/dev/ic/rtwreg.h
483
#define RTW_CONFIG3_CLKRUNEN __BIT(2)/* CLKRUN enabled, read-only.
sys/dev/ic/rtwreg.h
486
#define RTW_CONFIG3_FUNCREGEN __BIT(1)/* Function Registers Enabled,
sys/dev/ic/rtwreg.h
489
#define RTW_CONFIG3_FBTBEN __BIT(0)/* Fast back-to-back enabled,
sys/dev/ic/rtwreg.h
493
#define RTW_CONFIG4_VCOPDN __BIT(7)/* VCO Power Down
sys/dev/ic/rtwreg.h
499
#define RTW_CONFIG4_PWROFF __BIT(6)/* Power Off
sys/dev/ic/rtwreg.h
508
#define RTW_CONFIG4_PWRMGT __BIT(5)/* Power Management
sys/dev/ic/rtwreg.h
513
#define RTW_CONFIG4_LWPME __BIT(4)/* LANWAKE vs. PMEB: Cardbus-only
sys/dev/ic/rtwreg.h
521
#define RTW_CONFIG4_LWPTN __BIT(2)/* see RTW_CONFIG1_LWACT
sys/dev/ic/rtwreg.h
533
#define RTW_PSR_GPO __BIT(7)/* Control/status of pin 52. */
sys/dev/ic/rtwreg.h
534
#define RTW_PSR_GPI __BIT(6)/* Status of pin 64. */
sys/dev/ic/rtwreg.h
535
#define RTW_PSR_LEDGPO1 __BIT(5)/* Status/control of LED1 pin if
sys/dev/ic/rtwreg.h
538
#define RTW_PSR_LEDGPO0 __BIT(4)/* Status/control of LED0 pin if
sys/dev/ic/rtwreg.h
541
#define RTW_PSR_UWF __BIT(1)/* Enable Unicast Wakeup Frame */
sys/dev/ic/rtwreg.h
542
#define RTW_PSR_PSEN __BIT(0)/* 1: page 1, 0: page 0 */
sys/dev/ic/rtwreg.h
548
#define RTW_SCR_TXSECON __BIT(1)/* Enable Tx WEP. Invalid if
sys/dev/ic/rtwreg.h
552
#define RTW_SCR_RXSECON __BIT(0)/* Enable Rx WEP. Invalid if
sys/dev/ic/rtwreg.h
579
#define RTW_PHYDELAY_REVC_MAGIC __BIT(3) /* Rev. C magic from reference
sys/dev/ic/rtwreg.h
59
#define RTW_BRSR_BPLCP __BIT(8)/* 1: use short PLCP header for CTS/ACK packet,
sys/dev/ic/rtwreg.h
594
#define RTW_BB_WREN __BIT(7) /* write enable */
sys/dev/ic/rtwreg.h
602
#define RTW_PHYCFG_MAC_POLL __BIT(31) /* if !RTW_PHYCFG_HST,
sys/dev/ic/rtwreg.h
606
#define RTW_PHYCFG_HST __BIT(30) /* 1: host bangs bits
sys/dev/ic/rtwreg.h
619
#define RTW_PHYCFG_HST_EN __BIT(2)
sys/dev/ic/rtwreg.h
620
#define RTW_PHYCFG_HST_CLK __BIT(1)
sys/dev/ic/rtwreg.h
621
#define RTW_PHYCFG_HST_DATA __BIT(0)
sys/dev/ic/rtwreg.h
675
#define RTW_CONFIG5_TXFIFOOK __BIT(7)/* Tx FIFO self-test pass, read-only */
sys/dev/ic/rtwreg.h
676
#define RTW_CONFIG5_RXFIFOOK __BIT(6)/* Rx FIFO self-test pass, read-only */
sys/dev/ic/rtwreg.h
677
#define RTW_CONFIG5_CALON __BIT(5)/* 1: start calibration cycle
sys/dev/ic/rtwreg.h
681
#define RTW_CONFIG5_EACPI __BIT(2)/* Enable ACPI Wake up, default 0 */
sys/dev/ic/rtwreg.h
682
#define RTW_CONFIG5_LANWAKE __BIT(1)/* Enable LAN Wake signal,
sys/dev/ic/rtwreg.h
685
#define RTW_CONFIG5_PMESTS __BIT(0)/* 1: both software & PCI Reset
sys/dev/ic/rtwreg.h
69
#define RTW_BRSR_MBR8181_1MBPS __BIT(0)
sys/dev/ic/rtwreg.h
695
#define RTW_TPPOLL_BQ __BIT(7)/* RTL8180 clears to notify host of a beacon
sys/dev/ic/rtwreg.h
698
#define RTW_TPPOLL_HPQ __BIT(6)/* Host writes 1 to notify RTL8180 of
sys/dev/ic/rtwreg.h
70
#define RTW_BRSR_MBR8181_2MBPS __BIT(1)
sys/dev/ic/rtwreg.h
702
#define RTW_TPPOLL_NPQ __BIT(5)/* If RTW_CONFIG2_DPS is set,
sys/dev/ic/rtwreg.h
71
#define RTW_BRSR_MBR8181_5MBPS __BIT(2)
sys/dev/ic/rtwreg.h
711
#define RTW_TPPOLL_LPQ __BIT(4)/* Host writes 1 to notify RTL8180 of
sys/dev/ic/rtwreg.h
715
#define RTW_TPPOLL_SBQ __BIT(3)/* Host writes 1 to tell RTL8180 to
sys/dev/ic/rtwreg.h
719
#define RTW_TPPOLL_SHPQ __BIT(2)/* Host writes 1 to tell RTL8180 to
sys/dev/ic/rtwreg.h
72
#define RTW_BRSR_MBR8181_11MBPS __BIT(3)
sys/dev/ic/rtwreg.h
722
#define RTW_TPPOLL_SNPQ __BIT(1)/* Host writes 1 to tell RTL8180 to
sys/dev/ic/rtwreg.h
726
#define RTW_TPPOLL_SLPQ __BIT(0)/* Host writes 1 to tell RTL8180 to
sys/dev/ic/rtwreg.h
756
#define RTW_FER_INTR __BIT(15) /* set when RTW_FFER_INTR is set */
sys/dev/ic/rtwreg.h
757
#define RTW_FER_GWAKE __BIT(4) /* General Wakeup */
sys/dev/ic/rtwreg.h
762
#define RTW_FEMR_INTR __BIT(15) /* set when RTW_FFER_INTR is set */
sys/dev/ic/rtwreg.h
763
#define RTW_FEMR_WKUP __BIT(14) /* Wakeup Mask */
sys/dev/ic/rtwreg.h
764
#define RTW_FEMR_GWAKE __BIT(4) /* General Wakeup */
sys/dev/ic/rtwreg.h
770
#define RTW_FPSR_INTR __BIT(15) /* TBD */
sys/dev/ic/rtwreg.h
771
#define RTW_FPSR_GWAKE __BIT(4) /* General Wakeup: TBD */
sys/dev/ic/rtwreg.h
777
#define RTW_FFER_INTR __BIT(15) /* TBD */
sys/dev/ic/rtwreg.h
778
#define RTW_FFER_GWAKE __BIT(4) /* General Wakeup: TBD */
sys/dev/ic/rtwreg.h
818
#define RTW_SR_RFPARM_DIGPHY __BIT(0) /* 1: digital PHY */
sys/dev/ic/rtwreg.h
819
#define RTW_SR_RFPARM_DFLANTB __BIT(1) /* 1: antenna B is default */
sys/dev/ic/rtwreg.h
845
#define RTW_TXCTL0_OWN __BIT(31) /* 1: ready to Tx */
sys/dev/ic/rtwreg.h
846
#define RTW_TXCTL0_RSVD0 __BIT(30) /* reserved */
sys/dev/ic/rtwreg.h
847
#define RTW_TXCTL0_FS __BIT(29) /* first segment */
sys/dev/ic/rtwreg.h
848
#define RTW_TXCTL0_LS __BIT(28) /* last segment */
sys/dev/ic/rtwreg.h
856
#define RTW_TXCTL0_RTSEN __BIT(23) /* RTS Enable */
sys/dev/ic/rtwreg.h
86
#define RTW_CR_RST __BIT(4)/* Reset: host sets to 1 to disable
sys/dev/ic/rtwreg.h
864
#define RTW_TXCTL0_BEACON __BIT(18) /* packet is a beacon */
sys/dev/ic/rtwreg.h
865
#define RTW_TXCTL0_MOREFRAG __BIT(17) /* another fragment
sys/dev/ic/rtwreg.h
869
#define RTW_TXCTL0_SPLCP __BIT(16)
sys/dev/ic/rtwreg.h
881
#define RTW_TXSTAT_TOK __BIT(15)
sys/dev/ic/rtwreg.h
885
#define RTW_TXCTL1_LENGEXT __BIT(31) /* supplements _LENGTH
sys/dev/ic/rtwreg.h
90
#define RTW_CR_RE __BIT(3)/* Receiver Enable: host enables receiver
sys/dev/ic/rtwreg.h
909
#define RTW_RXCTL_OWN __BIT(31) /* 1: owned by NIC */
sys/dev/ic/rtwreg.h
910
#define RTW_RXCTL_EOR __BIT(30) /* end of ring */
sys/dev/ic/rtwreg.h
911
#define RTW_RXCTL_FS __BIT(29) /* first segment */
sys/dev/ic/rtwreg.h
912
#define RTW_RXCTL_LS __BIT(28) /* last segment */
sys/dev/ic/rtwreg.h
920
#define RTW_RXSTAT_DMAFAIL __BIT(27) /* DMA failure on this pkt */
sys/dev/ic/rtwreg.h
921
#define RTW_RXSTAT_BOVF __BIT(26) /* buffer overflow XXX means
sys/dev/ic/rtwreg.h
924
#define RTW_RXSTAT_SPLCP __BIT(25) /* Rx'd with short preamble
sys/dev/ic/rtwreg.h
927
#define RTW_RXSTAT_RSVD1 __BIT(24) /* reserved */
sys/dev/ic/rtwreg.h
933
#define RTW_RXSTAT_MIC __BIT(19) /* XXX from reference driver */
sys/dev/ic/rtwreg.h
934
#define RTW_RXSTAT_MAR __BIT(18) /* is multicast */
sys/dev/ic/rtwreg.h
935
#define RTW_RXSTAT_PAR __BIT(17) /* matches RTL8180's MAC */
sys/dev/ic/rtwreg.h
936
#define RTW_RXSTAT_BAR __BIT(16) /* is broadcast */
sys/dev/ic/rtwreg.h
937
#define RTW_RXSTAT_RES __BIT(15) /* error summary. valid when
sys/dev/ic/rtwreg.h
942
#define RTW_RXSTAT_PWRMGT __BIT(14) /* 802.11 PWRMGMT bit is set */
sys/dev/ic/rtwreg.h
943
#define RTW_RXSTAT_CRC16 __BIT(14) /* XXX CRC16 error, from
sys/dev/ic/rtwreg.h
946
#define RTW_RXSTAT_CRC32 __BIT(13) /* CRC32 error */
sys/dev/ic/rtwreg.h
947
#define RTW_RXSTAT_ICV __BIT(12) /* ICV error */
sys/dev/ic/rtwreg.h
95
#define RTW_CR_TE __BIT(2)/* Transmitter Enable: host enables transmitter
sys/dev/ic/rtwreg.h
967
#define RTW_RXRSSI_IMR_LNA __BIT(8) /* 1: LNA activated */
sys/dev/ic/sa2400reg.h
107
#define SA2400_OPMODE_ADC __BIT(19)
sys/dev/ic/sa2400reg.h
109
#define SA2400_OPMODE_FTERR __BIT(18)
sys/dev/ic/sa2400reg.h
116
#define SA2400_OPMODE_V2P5 __BIT(14)
sys/dev/ic/sa2400reg.h
118
#define SA2400_OPMODE_I1M __BIT(13)
sys/dev/ic/sa2400reg.h
120
#define SA2400_OPMODE_I0P3 __BIT(12)
sys/dev/ic/sa2400reg.h
121
#define SA2400_OPMODE_IN22 __BIT(10) /* xtal input frequency,
sys/dev/ic/sa2400reg.h
125
#define SA2400_OPMODE_CLK __BIT(9) /* reference clock output on */
sys/dev/ic/sa2400reg.h
126
#define SA2400_OPMODE_XO __BIT(8) /* xtal oscillator on */
sys/dev/ic/sa2400reg.h
127
#define SA2400_OPMODE_DIGIN __BIT(7) /* use digital Tx inputs
sys/dev/ic/sa2400reg.h
130
#define SA2400_OPMODE_RXLV __BIT(6) /* Rx output common mode
sys/dev/ic/sa2400reg.h
135
#define SA2400_OPMODE_VEO __BIT(5) /* make internal vco
sys/dev/ic/sa2400reg.h
139
#define SA2400_OPMODE_VEI __BIT(4) /* use external vco input
sys/dev/ic/sa2400reg.h
159
#define SA2400_AGC_TARGETSIGN __BIT(23) /* fine-tune AGC target:
sys/dev/ic/sa2400reg.h
187
#define SA2400_MANRX_AHSN __BIT(23) /* 1: AGC w/ high S/N---switch
sys/dev/ic/sa2400reg.h
199
#define SA2400_MANRX_RXOSQON __BIT(22) /* Rx Q-channel correction. */
sys/dev/ic/sa2400reg.h
200
#define SA2400_MANRX_RXOSQSIGN __BIT(21)
sys/dev/ic/sa2400reg.h
203
#define SA2400_MANRX_RXOSION __BIT(17) /* Rx I-channel correction. */
sys/dev/ic/sa2400reg.h
204
#define SA2400_MANRX_RXOSISIGN __BIT(16)
sys/dev/ic/sa2400reg.h
206
#define SA2400_MANRX_TEN __BIT(12) /* use 10MHz offset cancellation
sys/dev/ic/sa2400reg.h
228
#define SA2400_TX_TXOSQON __BIT(19)
sys/dev/ic/sa2400reg.h
229
#define SA2400_TX_TXOSQSIGN __BIT(18)
sys/dev/ic/sa2400reg.h
231
#define SA2400_TX_TXOSION __BIT(14)
sys/dev/ic/sa2400reg.h
232
#define SA2400_TX_TXOSISIGN __BIT(13)
sys/dev/ic/sa2400reg.h
252
#define SA2400_VCO_VCERR __BIT(4)/* VCO calibration error flag---no
sys/dev/ic/sa2400reg.h
38
#define SA2400_TWI_WREN __BIT(7) /* enable write */
sys/dev/ic/sa2400reg.h
45
#define SA2400_SYNA_FM __BIT(21) /* fractional modulus select,
sys/dev/ic/sa2400reg.h
66
#define SA2400_SYNB_ON __BIT(9) /* power on/off,
sys/dev/ic/sa2400reg.h
71
#define SA2400_SYNB_ONE __BIT(8) /* always 1 */
sys/dev/ic/sa2400reg.h
90
#define SA2400_SYNC_ZERO __BIT(2) /* always 0 */
sys/dev/ic/sa2400reg.h
94
#define SA2400_SYND_TPHPSU __BIT(16) /* T[phpsu], 1: disable
sys/dev/ic/sa2400reg.h
98
#define SA2400_SYND_TPSU __BIT(15) /* T[spu], 1: speedup on,
sys/dev/ic/si4136reg.h
57
#define SI4126_MAIN_XINDIV2 __BIT(6)
sys/dev/ic/si4136reg.h
58
#define SI4126_MAIN_LPWR __BIT(5) /* 1: low-power mode */
sys/dev/ic/si4136reg.h
59
#define SI4126_MAIN_AUTOPDB __BIT(3) /* 1: equivalent to
sys/dev/ic/si4136reg.h
74
#define SI4126_POWER_PDIB __BIT(1) /* 1: IF synthesizer on */
sys/dev/ic/si4136reg.h
75
#define SI4126_POWER_PDRB __BIT(0) /* 1: RF synthesizer on */
sys/dev/ic/si470x_reg.h
32
#define __BIT16(x) ((uint16_t)__BIT(x))
sys/dev/ic/siisata.c
608
if ((aslots & __BIT(slot)) != 0 &&
sys/dev/ic/siisatareg.h
135
#define GR_GC_GLBLRST __BIT(31)
sys/dev/ic/siisatareg.h
136
#define GR_GC_MSIACK __BIT(30)
sys/dev/ic/siisatareg.h
137
#define GR_GC_I2CINTEN __BIT(29)
sys/dev/ic/siisatareg.h
138
#define GR_GC_PERRRPTDSBL __BIT(28)
sys/dev/ic/siisatareg.h
139
#define GR_GC_3GBPS __BIT(24)
sys/dev/ic/siisatareg.h
140
#define GR_GC_REQ64 __BIT(20)
sys/dev/ic/siisatareg.h
141
#define GR_GC_DEVSEL __BIT(19)
sys/dev/ic/siisatareg.h
142
#define GR_GC_STOP __BIT(18)
sys/dev/ic/siisatareg.h
143
#define GR_GC_TRDY __BIT(17)
sys/dev/ic/siisatareg.h
144
#define GR_GC_M66EN __BIT(16)
sys/dev/ic/siisatareg.h
146
#define GR_GC_PXIE(n) __SHIFTIN(__BIT(n), GR_GC_PXIE_MASK)
sys/dev/ic/siisatareg.h
149
#define GR_GIS_I2C __BIT(29)
sys/dev/ic/siisatareg.h
151
#define GR_GIS_PXIS(n) __SHIFTIN(__BIT(n), GR_GIS_PXIS_MASK)
sys/dev/ic/siisatareg.h
225
#define PR_PIS_CMDCMPL __BIT(0) /* command completion */
sys/dev/ic/siisatareg.h
226
#define PR_PIS_CMDERRR __BIT(1) /* command error */
sys/dev/ic/siisatareg.h
227
#define PR_PIS_PRTRDY __BIT(2) /* port ready */
sys/dev/ic/siisatareg.h
228
#define PR_PIS_PMCHNG __BIT(3) /* power management state change */
sys/dev/ic/siisatareg.h
229
#define PR_PIS_PHYRDYCHG __BIT(4)
sys/dev/ic/siisatareg.h
230
#define PR_PIS_COMWAKE __BIT(5)
sys/dev/ic/siisatareg.h
231
#define PR_PIS_UNRECFIS __BIT(6)
sys/dev/ic/siisatareg.h
232
#define PR_PIS_DEVEXCHG __BIT(7)
sys/dev/ic/siisatareg.h
233
#define PR_PIS_8B10BDET __BIT(8)
sys/dev/ic/siisatareg.h
234
#define PR_PIS_CRCET __BIT(9)
sys/dev/ic/siisatareg.h
235
#define PR_PIS_HET __BIT(10)
sys/dev/ic/siisatareg.h
236
#define PR_PIS_SDBN __BIT(11)
sys/dev/ic/siisatareg.h
238
#define PR_PC_PORT_RESET __BIT(0)
sys/dev/ic/siisatareg.h
239
#define PR_PC_DEVICE_RESET __BIT(1)
sys/dev/ic/siisatareg.h
240
#define PR_PC_PORT_INITIALIZE __BIT(2)
sys/dev/ic/siisatareg.h
241
#define PR_PC_INCOR __BIT(3)
sys/dev/ic/siisatareg.h
242
#define PR_PC_LED_DISABLE __BIT(4)
sys/dev/ic/siisatareg.h
243
#define PR_PC_PACKET_LENGTH __BIT(5)
sys/dev/ic/siisatareg.h
244
#define PR_PC_RESUME __BIT(6)
sys/dev/ic/siisatareg.h
245
#define PR_PC_TXBIST __BIT(7)
sys/dev/ic/siisatareg.h
246
#define PR_PC_CONT_DISABLE __BIT(8)
sys/dev/ic/siisatareg.h
247
#define PR_PC_SCRAMBLER_DISABLE __BIT(9)
sys/dev/ic/siisatareg.h
248
#define PR_PC_32BA __BIT(10)
sys/dev/ic/siisatareg.h
249
#define PR_PC_INTERLOCK_REJECT __BIT(11)
sys/dev/ic/siisatareg.h
250
#define PR_PC_INTERLOCK_ACCEPT __BIT(12)
sys/dev/ic/siisatareg.h
251
#define PR_PC_PMP_ENABLE __BIT(13)
sys/dev/ic/siisatareg.h
252
#define PR_PC_AIA __BIT(14)
sys/dev/ic/siisatareg.h
253
#define PR_PC_LED_ON __BIT(15)
sys/dev/ic/siisatareg.h
256
#define PR_PC_OOB_BYPASS __BIT(25)
sys/dev/ic/siisatareg.h
257
#define PR_PS_PORT_READY __BIT(31)
sys/dev/ic/siisatareg.h
259
#define PR_PSS_ATTENTION __BIT(31)
sys/dev/ic/siisatareg.h
261
#define PR_PXSS(n) __SHIFTIN(__BIT(n), PR_PSS_SLOT_MASK)
sys/dev/ic/siisatareg.h
53
#define SGE_FLAG_TRM __BIT(31)
sys/dev/ic/siisatareg.h
54
#define SGE_FLAG_LNK __BIT(30)
sys/dev/ic/siisatareg.h
55
#define SGE_FLAG_DRD __BIT(29)
sys/dev/ic/siisatareg.h
56
#define SGE_FLAG_XCF __BIT(28)
sys/dev/ic/siisatareg.h
68
#define PRB_CF_PROTOCOL_OVERRIDE __BIT(0)
sys/dev/ic/siisatareg.h
69
#define PRB_CF_RETRANSMIT __BIT(1)
sys/dev/ic/siisatareg.h
70
#define PRB_CF_EXTERNAL_COMMAND __BIT(2)
sys/dev/ic/siisatareg.h
71
#define PRB_CF_RECEIVE __BIT(3)
sys/dev/ic/siisatareg.h
72
#define PRB_CF_PACKET_READ __BIT(4)
sys/dev/ic/siisatareg.h
73
#define PRB_CF_PACKET_WRITE __BIT(5)
sys/dev/ic/siisatareg.h
74
#define PRB_CF_INTERRUPT_MASK __BIT(6)
sys/dev/ic/siisatareg.h
75
#define PRB_CF_SOFT_RESET __BIT(7)
sys/dev/ic/siisatareg.h
77
#define PRB_PO_PACKET __BIT(0)
sys/dev/ic/siisatareg.h
78
#define PRB_PO_LCQ __BIT(1)
sys/dev/ic/siisatareg.h
79
#define PRB_PO_NCQ __BIT(2)
sys/dev/ic/siisatareg.h
80
#define PRB_PO_READ __BIT(3)
sys/dev/ic/siisatareg.h
81
#define PRB_PO_WRITE __BIT(4)
sys/dev/ic/siisatareg.h
82
#define PRB_PO_TRANSPARENT __BIT(5)
sys/dev/ic/ssdfbvar.h
169
#define SSD1322_FUNCTION_SELECTION_INTERNAL_VDD __BIT(0)
sys/dev/ic/ssdfbvar.h
185
#define SSD1322_GPIO0_TRISTATE __BIT(0)
sys/dev/ic/ssdfbvar.h
186
#define SSD1322_GPIO0_LOW __BIT(1)
sys/dev/ic/ssdfbvar.h
189
#define SSD1322_GPIO1_TRISTATE __BIT(2)
sys/dev/ic/ssdfbvar.h
190
#define SSD1322_GPIO1_LOW __BIT(3)
sys/dev/ic/ssdfbvar.h
239
#define SSD1353_REMAP_NO_INCREMENT __BIT(0)
sys/dev/ic/ssdfbvar.h
240
#define SSD1353_REMAP_SEG_DIRECTION __BIT(1)
sys/dev/ic/ssdfbvar.h
241
#define SSD1353_REMAP_RGB __BIT(2)
sys/dev/ic/ssdfbvar.h
242
#define SSD1353_REMAP_LR __BIT(3)
sys/dev/ic/ssdfbvar.h
243
#define SSD1353_REMAP_COM_DIRECTION __BIT(4)
sys/dev/ic/ssdfbvar.h
244
#define SSD1353_REMAP_SPLIT_ODD_EVEN __BIT(5)
sys/dev/ic/ssdfbvar.h
304
#define SSDFB_I2C_CTRL_BYTE_CONTINUATION_MASK __BIT(7)
sys/dev/ic/ssdfbvar.h
305
#define SSDFB_I2C_CTRL_BYTE_DATA_MASK __BIT(6)
sys/dev/ic/tpmreg.h
137
#define TPM_ACCESS_VALID __BIT(7)
sys/dev/ic/tpmreg.h
138
#define TPM_ACCESS_ACTIVE_LOCALITY __BIT(5)
sys/dev/ic/tpmreg.h
139
#define TPM_ACCESS_BEEN_SEIZED __BIT(4)
sys/dev/ic/tpmreg.h
140
#define TPM_ACCESS_SEIZE __BIT(3)
sys/dev/ic/tpmreg.h
141
#define TPM_ACCESS_PENDING_REQUEST __BIT(2)
sys/dev/ic/tpmreg.h
142
#define TPM_ACCESS_REQUEST_USE __BIT(1)
sys/dev/ic/tpmreg.h
143
#define TPM_ACCESS_ESTABLISHMENT __BIT(0)
sys/dev/ic/tpmreg.h
146
#define TPM_GLOBAL_INT_ENABLE __BIT(31)
sys/dev/ic/tpmreg.h
147
#define TPM_CMD_READY_INT __BIT(7)
sys/dev/ic/tpmreg.h
153
#define TPM_LOCALITY_CHANGE_INT __BIT(2)
sys/dev/ic/tpmreg.h
154
#define TPM_STS_VALID_INT __BIT(1)
sys/dev/ic/tpmreg.h
155
#define TPM_DATA_AVAIL_INT __BIT(0)
sys/dev/ic/tpmreg.h
161
#define TPM_INTF_BURST_COUNT_STATIC __BIT(8)
sys/dev/ic/tpmreg.h
162
#define TPM_INTF_CMD_READY_INT __BIT(7)
sys/dev/ic/tpmreg.h
163
#define TPM_INTF_INT_EDGE_FALLING __BIT(6)
sys/dev/ic/tpmreg.h
164
#define TPM_INTF_INT_EDGE_RISING __BIT(5)
sys/dev/ic/tpmreg.h
165
#define TPM_INTF_INT_LEVEL_LOW __BIT(4)
sys/dev/ic/tpmreg.h
166
#define TPM_INTF_INT_LEVEL_HIGH __BIT(3)
sys/dev/ic/tpmreg.h
167
#define TPM_INTF_LOCALITY_CHANGE_INT __BIT(2)
sys/dev/ic/tpmreg.h
168
#define TPM_INTF_STS_VALID_INT __BIT(1)
sys/dev/ic/tpmreg.h
169
#define TPM_INTF_DATA_AVAIL_INT __BIT(0)
sys/dev/ic/tpmreg.h
176
#define TPM_STS_VALID __BIT(7)
sys/dev/ic/tpmreg.h
177
#define TPM_STS_CMD_READY __BIT(6)
sys/dev/ic/tpmreg.h
178
#define TPM_STS_GO __BIT(5)
sys/dev/ic/tpmreg.h
179
#define TPM_STS_DATA_AVAIL __BIT(4)
sys/dev/ic/tpmreg.h
180
#define TPM_STS_DATA_EXPECT __BIT(3)
sys/dev/ic/tpmreg.h
181
#define TPM_STS_SELFTEST_DONE __BIT(2)
sys/dev/ic/tpmreg.h
182
#define TPM_STS_RESP_RETRY __BIT(1)
sys/dev/ic/tulip.c
2937
mchash[hash >> 5] |= __BIT(hash & 0x1f);
sys/dev/ipmivar.h
150
#define IPMI_WDOG_USE_NOLOG __BIT(7)
sys/dev/ipmivar.h
151
#define IPMI_WDOG_USE_NOSTOP __BIT(6)
sys/dev/ipmivar.h
161
#define IPMI_WDOG_ACT_PRE_RSVD1 __BIT(7)
sys/dev/ipmivar.h
167
#define IPMI_WDOG_ACT_PRE_RSVD0 __BIT(3)
sys/dev/ipmivar.h
175
#define IPMI_WDOG_FLAGS_OEM __BIT(5)
sys/dev/ipmivar.h
176
#define IPMI_WDOG_FLAGS_OS __BIT(4)
sys/dev/ipmivar.h
177
#define IPMI_WDOG_FLAGS_OSLOAD __BIT(3)
sys/dev/ipmivar.h
178
#define IPMI_WDOG_FLAGS_POST __BIT(2)
sys/dev/ipmivar.h
179
#define IPMI_WDOG_FLAGS_FRB2 __BIT(1)
sys/dev/ipmivar.h
180
#define IPMI_WDOG_FLAGS_RSVD0 __BIT(0)
sys/dev/isa/isv.c
51
#define ISV_CONTROL_MODE_MASK __BIT(0)
sys/dev/isa/isv.c
54
#define ISV_CONTROL_COUNTER_MASK __BIT(1)
sys/dev/isa/isv.c
61
#define ISV_STATUS_VIDEO_MASK __BIT(15)
sys/dev/isa/wbsioreg.h
117
#define WBSIO_GPIO0_WDT1 __BIT(0)
sys/dev/isa/wbsioreg.h
118
#define WBSIO_GPIO0_ENABLE __BIT(1)
sys/dev/isa/wbsioreg.h
121
#define WBSIO_GPIO_BASEADDR __BIT(3) /* Base address mode */
sys/dev/isa/wbsioreg.h
122
#define WBSIO_GPIO1_ENABLE __BIT(1)
sys/dev/isa/wbsioreg.h
123
#define WBSIO_GPIO2_ENABLE __BIT(2)
sys/dev/isa/wbsioreg.h
124
#define WBSIO_GPIO3_ENABLE __BIT(3)
sys/dev/isa/wbsioreg.h
125
#define WBSIO_GPIO4_ENABLE __BIT(4)
sys/dev/isa/wbsioreg.h
126
#define WBSIO_GPIO5_ENABLE __BIT(5)
sys/dev/isa/wbsioreg.h
127
#define WBSIO_GPIO6_ENABLE __BIT(6)
sys/dev/isa/wbsioreg.h
128
#define WBSIO_GPIO7_ENABLE __BIT(7)
sys/dev/isa/wbsioreg.h
129
#define WBSIO_GPIO8_ENABLE __BIT(0)
sys/dev/isa/wbsioreg.h
141
#define WBSIO_WDT_MODE_LEVEL __BIT(0)
sys/dev/isa/wbsioreg.h
143
#define WBSIO_WDT_MODE_KBCRST __BIT(2)
sys/dev/isa/wbsioreg.h
144
#define WBSIO_WDT_MODE_MINUTES __BIT(3)
sys/dev/isa/wbsioreg.h
145
#define WBSIO_WDT_MODE_FASTER __BIT(4)
sys/dev/isa/wbsioreg.h
150
#define WBSIO_WDT_STAT_TIMEOUT __BIT(4)
sys/dev/isa/wbsioreg.h
151
#define WBSIO_WDT_STAT_EVENT __BIT(5)
sys/dev/isa/wbsioreg.h
155
#define WBSIO_NCT6779D_MFS2_GP00 __BIT(0)
sys/dev/isa/wbsioreg.h
156
#define WBSIO_NCT6779D_MFS2_GP01 __BIT(1)
sys/dev/isa/wbsioreg.h
157
#define WBSIO_NCT6779D_MFS2_GP02 __BIT(2)
sys/dev/isa/wbsioreg.h
158
#define WBSIO_NCT6779D_MFS2_GP03_MASK (__BIT(3)|__BIT(4))
sys/dev/isa/wbsioreg.h
159
#define WBSIO_NCT6779D_MFS2_GP04 __BIT(5)
sys/dev/isa/wbsioreg.h
160
#define WBSIO_NCT6779D_MFS2_GP05 __BIT(6)
sys/dev/isa/wbsioreg.h
161
#define WBSIO_NCT6779D_MFS2_GP06 __BIT(7)
sys/dev/isa/wbsioreg.h
162
#define WBSIO_NCT6779D_MFS3_GP07_MASK __BIT(0)
sys/dev/isa/wbsioreg.h
163
#define WBSIO_NCT6779D_MFS4_GP10_GP17 __BIT(6)
sys/dev/isa/wbsioreg.h
164
#define WBSIO_NCT6779D_MFS4_GP20_GP21 __BIT(0)
sys/dev/isa/wbsioreg.h
165
#define WBSIO_NCT6779D_MFS4_GP22_GP23 __BIT(1)
sys/dev/isa/wbsioreg.h
166
#define WBSIO_NCT6779D_MFS1_GP24_MASK __BIT(4)
sys/dev/isa/wbsioreg.h
167
#define WBSIO_NCT6779D_GOPT2_GP24_MASK __BIT(3)
sys/dev/isa/wbsioreg.h
168
#define WBSIO_NCT6779D_MFS4_GP25_MASK __BIT(3)
sys/dev/isa/wbsioreg.h
169
#define WBSIO_NCT6779D_GOPT2_GP25_MASK __BIT(3)
sys/dev/isa/wbsioreg.h
170
#define WBSIO_NCT6779D_MFS6_GP26 __BIT(0)
sys/dev/isa/wbsioreg.h
171
#define WBSIO_NCT6779D_MFS6_GP27_MASK (__BIT(3)|__BIT(4))
sys/dev/isa/wbsioreg.h
172
#define WBSIO_NCT6779D_MFS0_GP30 __BIT(6)
sys/dev/isa/wbsioreg.h
173
#define WBSIO_NCT6779D_MFS0_GP30_MASK __BIT(7)
sys/dev/isa/wbsioreg.h
174
#define WBSIO_NCT6779D_MFS0_GP31 __BIT(5)
sys/dev/isa/wbsioreg.h
175
#define WBSIO_NCT6779D_MFS1_GP31_MASK __BIT(0)
sys/dev/isa/wbsioreg.h
176
#define WBSIO_NCT6779D_MFS0_GP32 __BIT(4)
sys/dev/isa/wbsioreg.h
177
#define WBSIO_NCT6779D_MFS1_GP32_MASK __BIT(0)
sys/dev/isa/wbsioreg.h
178
#define WBSIO_NCT6779D_MFS6_GP33 __BIT(7)
sys/dev/isa/wbsioreg.h
179
#define WBSIO_NCT6779D_MFS6_GP33_MASK __BIT(6)
sys/dev/isa/wbsioreg.h
180
#define WBSIO_NCT6779D_MFS1_GP40 __BIT(3)
sys/dev/isa/wbsioreg.h
181
#define WBSIO_NCT6779D_MFS0_GP41 __BIT(3)
sys/dev/isa/wbsioreg.h
182
#define WBSIO_NCT6779D_MFS0_GP41_MASK __BIT(2)
sys/dev/isa/wbsioreg.h
183
#define WBSIO_NCT6779D_MFS1_GP42 (__BIT(1)|__BIT(2))
sys/dev/isa/wbsioreg.h
184
#define WBSIO_NCT6779D_GOPT2_GP43 __BIT(4)
sys/dev/isa/wbsioreg.h
185
#define WBSIO_NCT6779D_MFS1_GP44_GP45_MASK __BIT(6)
sys/dev/isa/wbsioreg.h
186
#define WBSIO_NCT6779D_GOPT2_GP46_MASK __BIT(5)
sys/dev/isa/wbsioreg.h
187
#define WBSIO_NCT6779D_MFS1_GP47 __BIT(7)
sys/dev/isa/wbsioreg.h
188
#define WBSIO_NCT6779D_HM_GP50_MASK __BIT(2)
sys/dev/isa/wbsioreg.h
189
#define WBSIO_NCT6779D_HM_GP52_MASK __BIT(1)
sys/dev/isa/wbsioreg.h
190
#define WBSIO_NCT6779D_HM_GP55_MASK __BIT(3)
sys/dev/isa/wbsioreg.h
191
#define WBSIO_NCT6779D_MFS5_GP74 __BIT(5)
sys/dev/isa/wbsioreg.h
192
#define WBSIO_NCT6779D_MFS5_GP75 __BIT(6)
sys/dev/isa/wbsioreg.h
193
#define WBSIO_NCT6779D_MFS5_GP76 __BIT(7)
sys/dev/isa/wbsioreg.h
194
#define WBSIO_NCT6779D_GPIO4_WDTO __BIT(4)
sys/dev/marvell/gtbrgreg.h
68
#define BRG_BCR_EN __BIT(16) /* Enable BRG */
sys/dev/marvell/gtbrgreg.h
69
#define BRG_BCR_RST __BIT(17) /* Reset BRG */
sys/dev/marvell/gtbrgreg.h
87
#define BRG_INTR_BTR0 __BIT(0) /* Baud Tuning 0 irpt. */
sys/dev/marvell/gtbrgreg.h
88
#define BRG_INTR_BTR1 __BIT(1) /* Baud Tuning 1 irpt. */
sys/dev/marvell/gtbrgreg.h
89
#define BRG_INTR_BTR2 __BIT(2) /* Baud Tuning 2 irpt. */
sys/dev/marvell/gtmpscreg.h
110
#define GTMPSC_MMCR_LO_TTX __BIT(3) /* Transparent TX */
sys/dev/marvell/gtmpscreg.h
111
#define GTMPSC_MMCR_LO_TRX __BIT(4) /* Transparent RX */
sys/dev/marvell/gtmpscreg.h
112
#define GTMPSC_MMCR_LO_RESa __BIT(5)
sys/dev/marvell/gtmpscreg.h
113
#define GTMPSC_MMCR_LO_ET __BIT(6) /* Enable TX */
sys/dev/marvell/gtmpscreg.h
114
#define GTMPSC_MMCR_LO_ER __BIT(7) /* Enable RX */
sys/dev/marvell/gtmpscreg.h
120
#define GTMPSC_MMCR_LO_NLM __BIT(10) /* Null Modem */
sys/dev/marvell/gtmpscreg.h
121
#define GTMPSC_MMCR_LO_RESb __BIT(11)
sys/dev/marvell/gtmpscreg.h
122
#define GTMPSC_MMCR_LO_TSYN __BIT(12) /* Transmitter sync to Rcvr. */
sys/dev/marvell/gtmpscreg.h
123
#define GTMPSC_MMCR_LO_RESc __BIT(13)
sys/dev/marvell/gtmpscreg.h
126
#define GTMPSC_MMCR_LO_TIDL __BIT(16) /* TX Idles */
sys/dev/marvell/gtmpscreg.h
127
#define GTMPSC_MMCR_LO_RTSM __BIT(17) /* RTS Mode */
sys/dev/marvell/gtmpscreg.h
128
#define GTMPSC_MMCR_LO_RESd __BIT(18)
sys/dev/marvell/gtmpscreg.h
129
#define GTMPSC_MMCR_LO_CTSS __BIT(19) /* CTS Sampling mode */
sys/dev/marvell/gtmpscreg.h
130
#define GTMPSC_MMCR_LO_CDS __BIT(20) /* CD Sampling mode */
sys/dev/marvell/gtmpscreg.h
131
#define GTMPSC_MMCR_LO_CTSM __BIT(21) /* CTS operating Mode */
sys/dev/marvell/gtmpscreg.h
132
#define GTMPSC_MMCR_LO_CDM __BIT(22) /* CD operating Mode */
sys/dev/marvell/gtmpscreg.h
136
#define GTMPSC_MMCR_LO_TRVD __BIT(28) /* Transmit Reverse Data */
sys/dev/marvell/gtmpscreg.h
137
#define GTMPSC_MMCR_LO_RRVD __BIT(29) /* Receive Reverse Data */
sys/dev/marvell/gtmpscreg.h
138
#define GTMPSC_MMCR_LO_RESf __BIT(30)
sys/dev/marvell/gtmpscreg.h
139
#define GTMPSC_MMCR_LO_GDE __BIT(31) /* Glitch Detect Enable */
sys/dev/marvell/gtmpscreg.h
146
#define GTMPSC_MMCR_HI_TCI __BIT(0) /* TX Clock Invert */
sys/dev/marvell/gtmpscreg.h
147
#define GTMPSC_MMCR_HI_TINV __BIT(1) /* TX Bitstream Inversion */
sys/dev/marvell/gtmpscreg.h
166
#define GTMPSC_MMCR_HI_RINV __BIT(16) /* RX Bitstream Inversion */
sys/dev/marvell/gtmpscreg.h
168
#define GTMPSC_MMCR_HI_RESb __BIT(21)
sys/dev/marvell/gtmpscreg.h
169
#define GTMPSC_MMCR_HI_RDW __BIT(22) /* Receive Data Width */
sys/dev/marvell/gtmpscreg.h
197
#define SDMA_CSR_RX_PE __BIT(0) /* Parity Error */
sys/dev/marvell/gtmpscreg.h
198
#define SDMA_CSR_RX_CDL __BIT(1) /* Carrier Detect Loss */
sys/dev/marvell/gtmpscreg.h
199
#define SDMA_CSR_RX_RESa __BIT(2)
sys/dev/marvell/gtmpscreg.h
200
#define SDMA_CSR_RX_FR __BIT(3) /* Framing Error */
sys/dev/marvell/gtmpscreg.h
202
#define SDMA_CSR_RX_OR __BIT(6) /* Data Overrun */
sys/dev/marvell/gtmpscreg.h
204
#define SDMA_CSR_RX_BR __BIT(9) /* Break Received */
sys/dev/marvell/gtmpscreg.h
205
#define SDMA_CSR_RX_MI __BIT(10) /* Max Idle */
sys/dev/marvell/gtmpscreg.h
206
#define SDMA_CSR_RX_ADDR __BIT(11) /* Address */
sys/dev/marvell/gtmpscreg.h
207
#define SDMA_CSR_RX_AMATCH __BIT(12) /* Address match */
sys/dev/marvell/gtmpscreg.h
208
#define SDMA_CSR_RX_CT __BIT(13) /* Transparency Control char */
sys/dev/marvell/gtmpscreg.h
209
#define SDMA_CSR_RX_C __BIT(14) /* Control char */
sys/dev/marvell/gtmpscreg.h
210
#define SDMA_CSR_RX_ES __BIT(15) /* Error Summary */
sys/dev/marvell/gtmpscreg.h
211
#define SDMA_CSR_RX_L __BIT(16) /* Last */
sys/dev/marvell/gtmpscreg.h
212
#define SDMA_CSR_RX_F __BIT(17) /* First */
sys/dev/marvell/gtmpscreg.h
214
#define SDMA_CSR_RX_EI __BIT(23) /* Enable Interrupt */
sys/dev/marvell/gtmpscreg.h
216
#define SDMA_CSR_RX_AUTO __BIT(30) /* Auto Mode */
sys/dev/marvell/gtmpscreg.h
217
#define SDMA_CSR_RX_OWN __BIT(31) /* Owner */
sys/dev/marvell/gtmpscreg.h
223
#define SDMA_CSR_TX_RESa __BIT(0)
sys/dev/marvell/gtmpscreg.h
224
#define SDMA_CSR_TX_CTSL __BIT(1) /* CTS Loss */
sys/dev/marvell/gtmpscreg.h
226
#define SDMA_CSR_TX_ES __BIT(15) /* Error Summary */
sys/dev/marvell/gtmpscreg.h
227
#define SDMA_CSR_TX_L __BIT(16) /* Last */
sys/dev/marvell/gtmpscreg.h
228
#define SDMA_CSR_TX_F __BIT(17) /* First */
sys/dev/marvell/gtmpscreg.h
229
#define SDMA_CSR_TX_P __BIT(18) /* Preamble */
sys/dev/marvell/gtmpscreg.h
230
#define SDMA_CSR_TX_ADDR __BIT(19) /* Address */
sys/dev/marvell/gtmpscreg.h
231
#define SDMA_CSR_TX_NS __BIT(20) /* No Stop Bit */
sys/dev/marvell/gtmpscreg.h
233
#define SDMA_CSR_TX_EI __BIT(23) /* Enable Interrupt */
sys/dev/marvell/gtmpscreg.h
235
#define SDMA_CSR_TX_AUTO __BIT(30) /* Auto Mode */
sys/dev/marvell/gtmpscreg.h
236
#define SDMA_CSR_TX_OWN __BIT(31) /* Owner */
sys/dev/marvell/gtmpscreg.h
243
#define GTMPSC_MPCR_DRT __BIT(6) /* Disable Rx on Tx */
sys/dev/marvell/gtmpscreg.h
244
#define GTMPSC_MPCR_ISO __BIT(7) /* Isochronous Mode */
sys/dev/marvell/gtmpscreg.h
245
#define GTMPSC_MPCR_RZS __BIT(8) /* Rx Zero Stop Bit(s) */
sys/dev/marvell/gtmpscreg.h
246
#define GTMPSC_MPCR_FRZ __BIT(9) /* Freeze Tx */
sys/dev/marvell/gtmpscreg.h
259
#define GTMPSC_MPCR_FLC_ASYNC __BIT(15) /* Asynchronous Flow Ctl mode */
sys/dev/marvell/gtmpscreg.h
271
#define GTMPSC_CHR2_RESa __BIT(0)
sys/dev/marvell/gtmpscreg.h
272
#define GTMPSC_CHR2_TEV __BIT(1) /* Tx Enb. Vert. Redundancy */
sys/dev/marvell/gtmpscreg.h
279
#define GTMPSC_CHR2_TXABORT __BIT(7) /* Tx Abort */
sys/dev/marvell/gtmpscreg.h
280
#define GTMPSC_CHR2_RESc __BIT(8)
sys/dev/marvell/gtmpscreg.h
281
#define GTMPSC_CHR2_TCS __BIT(9) /* Tx TCS Char */
sys/dev/marvell/gtmpscreg.h
283
#define GTMPSC_CHR2_REC __BIT(17) /* Rx Enb. Vert. Redundancy */
sys/dev/marvell/gtmpscreg.h
290
#define GTMPSC_CHR2_RXABORT __BIT(23) /* Rx Abort */
sys/dev/marvell/gtmpscreg.h
291
#define GTMPSC_CHR2_RESf __BIT(24)
sys/dev/marvell/gtmpscreg.h
292
#define GTMPSC_CHR2_CRD __BIT(25) /* Close RX Descriptor */
sys/dev/marvell/gtmpscreg.h
294
#define GTMPSC_CHR2_EH __BIT(31) /* Enter Hunt */
sys/dev/marvell/gtmpscreg.h
317
#define GTMPSC_CHRCC_INT __BIT(12) /* Interrupt */
sys/dev/marvell/gtmpscreg.h
318
#define GTMPSC_CHRCC_CO __BIT(13) /* ISO 3309 Control Octet */
sys/dev/marvell/gtmpscreg.h
319
#define GTMPSC_CHRCC_R __BIT(14) /* Reject */
sys/dev/marvell/gtmpscreg.h
320
#define GTMPSC_CHRCC_V __BIT(15) /* Valid */
sys/dev/marvell/gtmpscreg.h
326
#define GTMPSC_CHR9_MODE1 __BIT(15) /* mode #1 */
sys/dev/marvell/gtmpscreg.h
329
#define GTMPSC_CHR9_MODE2 __BIT(31) /* mode #2 */
sys/dev/marvell/gtmpscreg.h
334
#define GTMPSC_CHR10_CTS __BIT(0) /* Clear To Send */
sys/dev/marvell/gtmpscreg.h
335
#define GTMPSC_CHR10_CD __BIT(1) /* Carrier Detect */
sys/dev/marvell/gtmpscreg.h
336
#define GTMPSC_CHR10_RESa __BIT(2)
sys/dev/marvell/gtmpscreg.h
337
#define GTMPSC_CHR10_TIDLE __BIT(3) /* Tx in Idle State */
sys/dev/marvell/gtmpscreg.h
338
#define GTMPSC_CHR10_RESb __BIT(4)
sys/dev/marvell/gtmpscreg.h
339
#define GTMPSC_CHR10_RHS __BIT(5) /* Rx in HUNT State */
sys/dev/marvell/gtmpscreg.h
340
#define GTMPSC_CHR10_RESc __BIT(6)
sys/dev/marvell/gtmpscreg.h
341
#define GTMPSC_CHR10_RLS __BIT(7) /* Rx Line STatus */
sys/dev/marvell/gtmpscreg.h
343
#define GTMPSC_CHR10_RLIDL __BIT(11) /* Rx IDLE Line */
sys/dev/marvell/gtmpscreg.h
86
#define GTMPSC_MRRE_DSC __BIT(31) /* "Don't Stop Clock" */
sys/dev/marvell/gtsdmareg.h
100
#define SDMA_SDCM_AT __BIT(31) /* Abort TX */
sys/dev/marvell/gtsdmareg.h
107
#define SDMA_INTR_RXBUF(u) U__(__BIT(0),u) /* SDMA #0 Rx Buffer Return */
sys/dev/marvell/gtsdmareg.h
108
#define SDMA_INTR_RXERR(u) U__(__BIT(1),u) /* SDMA #0 Rx Error */
sys/dev/marvell/gtsdmareg.h
109
#define SDMA_INTR_TXBUF(u) U__(__BIT(2),u) /* SDMA #0 Tx Buffer Return */
sys/dev/marvell/gtsdmareg.h
110
#define SDMA_INTR_TXEND(u) U__(__BIT(3),u) /* SDMA #0 Tx End */
sys/dev/marvell/gtsdmareg.h
73
#define SDMA_SDC_RFT __BIT(0) /* RX FIFO Threshold */
sys/dev/marvell/gtsdmareg.h
74
#define SDMA_SDC_SFM __BIT(1) /* Single Frame Mode */
sys/dev/marvell/gtsdmareg.h
77
#define SDMA_SDC_BLMR __BIT(6) /* RX Big=0 Lil=1 Endian mode */
sys/dev/marvell/gtsdmareg.h
78
#define SDMA_SDC_BLMT __BIT(7) /* TX Big=0 Lil=1 Endian mode */
sys/dev/marvell/gtsdmareg.h
79
#define SDMA_SDC_POVR __BIT(8) /* PCI Override */
sys/dev/marvell/gtsdmareg.h
80
#define SDMA_SDC_RIFB __BIT(9) /* RX Intr on Frame boundaries */
sys/dev/marvell/gtsdmareg.h
93
#define SDMA_SDCM_ERD __BIT(7) /* Enable RX DMA */
sys/dev/marvell/gtsdmareg.h
95
#define SDMA_SDCM_AR __BIT(15) /* Abort Receive */
sys/dev/marvell/gtsdmareg.h
96
#define SDMA_SDCM_STD __BIT(16) /* Stop TX */
sys/dev/marvell/gtsdmareg.h
98
#define SDMA_SDCM_TXD __BIT(23) /* TX Demand */
sys/dev/marvell/mvgbereg.h
361
#define MVGBE_SDC_IPGINTRX_V2_MASK (__BIT(25) | __BITS(21, 7))
sys/dev/marvell/mvxpsecreg.h
122
#define MV_ACC_CRYPTO_MAC_96 __BIT(7)
sys/dev/marvell/mvxpsecreg.h
123
#define MV_ACC_CRYPTO_DECRYPT __BIT(12)
sys/dev/marvell/mvxpsecreg.h
124
#define MV_ACC_CRYPTO_CBC __BIT(16)
sys/dev/marvell/mvxpsecreg.h
125
#define MV_ACC_CRYPTO_3DES_EDE __BIT(20)
sys/dev/marvell/mvxpsecreg.h
169
#define MVXPSEC_INT_AUTH __BIT(0)
sys/dev/marvell/mvxpsecreg.h
170
#define MVXPSEC_INT_DES __BIT(1)
sys/dev/marvell/mvxpsecreg.h
171
#define MVXPSEC_INT_AES_ENC __BIT(2)
sys/dev/marvell/mvxpsecreg.h
172
#define MVXPSEC_INT_AES_DEC __BIT(3)
sys/dev/marvell/mvxpsecreg.h
173
#define MVXPSEC_INT_ENC __BIT(4)
sys/dev/marvell/mvxpsecreg.h
179
#define MVXPSEC_INT_SA __BIT(5)
sys/dev/marvell/mvxpsecreg.h
180
#define MVXPSEC_INT_ACCTDMA __BIT(7)
sys/dev/marvell/mvxpsecreg.h
181
#define MVXPSEC_INT_ACCTDMA_CONT __BIT(11)
sys/dev/marvell/mvxpsecreg.h
182
#define MVXPSEC_INT_COAL __BIT(14)
sys/dev/marvell/mvxpsecreg.h
185
#define MVXPSEC_INT_TDMA_COMP __BIT(9)
sys/dev/marvell/mvxpsecreg.h
186
#define MVXPSEC_INT_TDMA_OWN __BIT(10)
sys/dev/marvell/mvxpsecreg.h
208
#define MV_TDMA_ATTR_ENABLE __BIT(0)
sys/dev/marvell/mvxpsecreg.h
224
#define MV_TDMA_CONTROL_OUTS_EN __BIT(4)
sys/dev/marvell/mvxpsecreg.h
230
#define MV_TDMA_CONTROL_CHAIN_DIS __BIT(9)
sys/dev/marvell/mvxpsecreg.h
231
#define MV_TDMA_CONTROL_BSWAP_DIS __BIT(11)
sys/dev/marvell/mvxpsecreg.h
232
#define MV_TDMA_CONTROL_ENABLE __BIT(12)
sys/dev/marvell/mvxpsecreg.h
233
#define MV_TDMA_CONTROL_FETCH __BIT(13)
sys/dev/marvell/mvxpsecreg.h
234
#define MV_TDMA_CONTROL_ACT __BIT(14)
sys/dev/marvell/mvxpsecvar.h
483
#define MVXPSEC_DEBUG_DMA __BIT(0)
sys/dev/marvell/mvxpsecvar.h
484
#define MVXPSEC_DEBUG_IOCTL __BIT(1)
sys/dev/marvell/mvxpsecvar.h
485
#define MVXPSEC_DEBUG_INTR __BIT(2)
sys/dev/marvell/mvxpsecvar.h
486
#define MVXPSEC_DEBUG_SRAM __BIT(3)
sys/dev/marvell/mvxpsecvar.h
487
#define MVXPSEC_DEBUG_OPENCRYPTO __BIT(4)
sys/dev/marvell/mvxpsecvar.h
488
#define MVXPSEC_DEBUG_PAYLOAD __BIT(5)
sys/dev/marvell/mvxpsecvar.h
489
#define MVXPSEC_DEBUG_HASH_IV __BIT(6)
sys/dev/marvell/mvxpsecvar.h
490
#define MVXPSEC_DEBUG_HASH_VAL __BIT(7)
sys/dev/marvell/mvxpsecvar.h
491
#define MVXPSEC_DEBUG_DESC __BIT(8) /* descriptors and registers */
sys/dev/marvell/mvxpsecvar.h
492
#define MVXPSEC_DEBUG_INPUT __BIT(9)
sys/dev/marvell/mvxpsecvar.h
493
#define MVXPSEC_DEBUG_ENC_IV __BIT(10)
sys/dev/marvell/mvxpsecvar.h
494
#define MVXPSEC_DEBUG_QUEUE __BIT(11)
sys/dev/mii/atphy.c
79
#define ATPHY_RGMII_RX_CLK_DLY __BIT(15)
sys/dev/mii/atphy.c
80
#define ATPHY_RGMII_TX_CLK_DLY __BIT(8)
sys/dev/mii/inbmphyreg.h
142
#define CV_SMB_CTRL_FORCE_SMBUS __BIT(0)
sys/dev/mii/inbmphyreg.h
145
#define BM_RATE_ADAPTATION_CTRL_RX_RXDV_PRE __BIT(8)
sys/dev/mii/inbmphyreg.h
146
#define BM_RATE_ADAPTATION_CTRL_RX_CRS_PRE __BIT(7)
sys/dev/mii/inbmphyreg.h
154
#define HV_PM_CTRL_K1_CLK_REQ __BIT(9)
sys/dev/mii/inbmphyreg.h
155
#define HV_PM_CTRL_K1_ENA __BIT(14)
sys/dev/mii/inbmphyreg.h
165
#define I217_LPI_GPIO_CTRL_AUTO_EN_LPI __BIT(11)
sys/dev/mii/inbmphyreg.h
169
#define I82579_LPI_CTRL_EN_100 __BIT(13)
sys/dev/mii/inbmphyreg.h
170
#define I82579_LPI_CTRL_EN_1000 __BIT(14)
sys/dev/mii/inbmphyreg.h
189
#define I218_ULP_CONFIG1_START __BIT(0)
sys/dev/mii/inbmphyreg.h
190
#define I218_ULP_CONFIG1_IND __BIT(2)
sys/dev/mii/inbmphyreg.h
191
#define I218_ULP_CONFIG1_STICKY_ULP __BIT(4)
sys/dev/mii/inbmphyreg.h
192
#define I218_ULP_CONFIG1_INBAND_EXIT __BIT(5)
sys/dev/mii/inbmphyreg.h
193
#define I218_ULP_CONFIG1_WOL_HOST __BIT(6)
sys/dev/mii/inbmphyreg.h
194
#define I218_ULP_CONFIG1_RESET_TO_SMBUS __BIT(8)
sys/dev/mii/inbmphyreg.h
195
#define I218_ULP_CONFIG1_EN_ULP_LANPHYPC __BIT(10)
sys/dev/mii/inbmphyreg.h
196
#define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST __BIT(11)
sys/dev/mii/inbmphyreg.h
197
#define I218_ULP_CONFIG1_DIS_SMB_PERST __BIT(12)
sys/dev/mii/inbmphyreg.h
93
#define I82579_LPI_PLL_SHUT_100 __BIT(2) /* 100M LPI PLL Shut Enable */
sys/dev/mii/makphyvar.h
40
#define MAKPHY_F_I210 __BIT(0) /* Identify I210 (mii_model == 0) */
sys/dev/mii/makphyvar.h
41
#define MAKPHY_F_FICO_AUTOSEL __BIT(1) /* Fiber/Copper autoselect mode */
sys/dev/mii/makphyvar.h
42
#define MAKPHY_QUIRK_PSSR_LINK __BIT(2) /*
sys/dev/mii/mcommphy.c
105
#define YT8531_RGMII_RXD_DS_HIBITS __BIT(2)
sys/dev/mii/mcommphy.c
116
#define YT8531_EN_SYNC_E __BIT(6)
sys/dev/mii/mcommphy.c
117
#define YT8531_CLK_FRE_SEL_125M __BIT(4)
sys/dev/mii/mcommphy.c
64
#define YT8511_RX_CLK_DELAY_EN __BIT(0)
sys/dev/mii/mcommphy.c
70
#define YT8521_RX_CLK_EN __BIT(12)
sys/dev/mii/mcommphy.c
73
#define YT8511_PLLON_IN_SLP __BIT(14)
sys/dev/mii/mcommphy.c
76
#define YT8521_PLLON_IN_SLP __BIT(14)
sys/dev/mii/mcommphy.c
79
#define YT8521_RXC_DLY_EN __BIT(8)
sys/dev/mii/mcommphy.c
88
#define YT8521_TX_CLK_SEL_INV __BIT(14)
sys/dev/mii/mcommphy.c
99
#define YT8531_RGMII_RXD_DS_HIMASK __BIT(12)
sys/dev/mii/rgephyreg.h
66
#define RGEPHY_PHYCR1_MDI_MMCE __BIT(9)
sys/dev/mii/rgephyreg.h
67
#define RGEPHY_PHYCR1_ALDPS_EN __BIT(2)
sys/dev/mii/rgephyreg.h
70
#define RGEPHY_PHYSR_ALDPS __BIT(14)
sys/dev/mii/rgephyreg.h
71
#define RGEPHY_PHYSR_MDI_PLUG __BIT(13)
sys/dev/mii/rgephyreg.h
72
#define RGEPHY_PHYSR_NWAY_EN __BIT(12)
sys/dev/mii/rgephyreg.h
73
#define RGEPHY_PHYSR_MASTER __BIT(11)
sys/dev/mii/rgephyreg.h
74
#define RGEPHY_PHYSR_EEE __BIT(8)
sys/dev/mii/rgephyreg.h
75
#define RGEPHY_PHYSR_RXFLOW_EN __BIT(7)
sys/dev/mii/rgephyreg.h
76
#define RGEPHY_PHYSR_TXFLOW_EN __BIT(6)
sys/dev/mii/rgephyreg.h
81
#define RGEPHY_PHYSR_DUPLEX __BIT(3)
sys/dev/mii/rgephyreg.h
82
#define RGEPHY_PHYSR_LINK __BIT(2)
sys/dev/mii/rgephyreg.h
83
#define RGEPHY_PHYSR_MDI_XOVER __BIT(1)
sys/dev/mii/rgephyreg.h
84
#define RGEPHY_PHYSR_JABBER __BIT(0)
sys/dev/nand/nand_micron.c
54
#define MT29FxG_PARAM_WIDTH(p) (((p) >> 1) & __BIT(0))
sys/dev/nor/cfi_0002.c
517
uint8_t r0 = bus_space_read_1(bst, bsh, 0) & __BIT(7);
sys/dev/nor/cfi_0002.c
518
uint8_t r1 = bus_space_read_1(bst, bsh, 0) & __BIT(7);
sys/dev/nor/cfi_0002.c
574
return ((r & __BIT(7)) == 0):
sys/dev/nvmm/x86/nvmm_x86.c
516
if ((xcr0 & __BIT(i)) == 0)
sys/dev/nvmm/x86/nvmm_x86.h
133
#define NVMM_CAP_ARCH_VCPU_CONF_CPUID __BIT(0)
sys/dev/nvmm/x86/nvmm_x86.h
134
#define NVMM_CAP_ARCH_VCPU_CONF_TPR __BIT(1)
sys/dev/nvmm/x86/nvmm_x86.h
135
#define NVMM_CAP_ARCH_VCPU_CONF_XCR0_MASK __BIT(2)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1007
if ((cpudata->xcr0_mask & __BIT(ecx)) == 0) {
sys/dev/nvmm/x86/nvmm_x86_svm.c
1184
#define SVM_EXIT_IO_A64 __BIT(9)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1185
#define SVM_EXIT_IO_A32 __BIT(8)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1186
#define SVM_EXIT_IO_A16 __BIT(7)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1187
#define SVM_EXIT_IO_SZ32 __BIT(6)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1188
#define SVM_EXIT_IO_SZ16 __BIT(5)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1189
#define SVM_EXIT_IO_SZ8 __BIT(4)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1190
#define SVM_EXIT_IO_REP __BIT(3)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1191
#define SVM_EXIT_IO_STR __BIT(2)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1192
#define SVM_EXIT_IO_IN __BIT(0)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1912
#define SVM_MSRBM_READ __BIT(0)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1913
#define SVM_MSRBM_WRITE __BIT(1)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1945
#define SVM_SEG_ATTRIB_S __BIT(4)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1947
#define SVM_SEG_ATTRIB_P __BIT(7)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1948
#define SVM_SEG_ATTRIB_AVL __BIT(8)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1949
#define SVM_SEG_ATTRIB_L __BIT(9)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1950
#define SVM_SEG_ATTRIB_DEF __BIT(10)
sys/dev/nvmm/x86/nvmm_x86_svm.c
1951
#define SVM_SEG_ATTRIB_G __BIT(11)
sys/dev/nvmm/x86/nvmm_x86_svm.c
2299
if (svm_asidmap[oct] & __BIT(bit)) {
sys/dev/nvmm/x86/nvmm_x86_svm.c
2303
svm_asidmap[oct] |= __BIT(bit);
sys/dev/nvmm/x86/nvmm_x86_svm.c
2333
svm_asidmap[oct] &= ~__BIT(bit);
sys/dev/nvmm/x86/nvmm_x86_svm.c
251
#define VMCB_CTRL_INTERCEPT_RCR(x) __BIT( 0 + x)
sys/dev/nvmm/x86/nvmm_x86_svm.c
252
#define VMCB_CTRL_INTERCEPT_WCR(x) __BIT(16 + x)
sys/dev/nvmm/x86/nvmm_x86_svm.c
255
#define VMCB_CTRL_INTERCEPT_RDR(x) __BIT( 0 + x)
sys/dev/nvmm/x86/nvmm_x86_svm.c
256
#define VMCB_CTRL_INTERCEPT_WDR(x) __BIT(16 + x)
sys/dev/nvmm/x86/nvmm_x86_svm.c
259
#define VMCB_CTRL_INTERCEPT_VEC(x) __BIT(x)
sys/dev/nvmm/x86/nvmm_x86_svm.c
262
#define VMCB_CTRL_INTERCEPT_INTR __BIT(0)
sys/dev/nvmm/x86/nvmm_x86_svm.c
263
#define VMCB_CTRL_INTERCEPT_NMI __BIT(1)
sys/dev/nvmm/x86/nvmm_x86_svm.c
264
#define VMCB_CTRL_INTERCEPT_SMI __BIT(2)
sys/dev/nvmm/x86/nvmm_x86_svm.c
265
#define VMCB_CTRL_INTERCEPT_INIT __BIT(3)
sys/dev/nvmm/x86/nvmm_x86_svm.c
266
#define VMCB_CTRL_INTERCEPT_VINTR __BIT(4)
sys/dev/nvmm/x86/nvmm_x86_svm.c
267
#define VMCB_CTRL_INTERCEPT_CR0_SPEC __BIT(5)
sys/dev/nvmm/x86/nvmm_x86_svm.c
268
#define VMCB_CTRL_INTERCEPT_RIDTR __BIT(6)
sys/dev/nvmm/x86/nvmm_x86_svm.c
269
#define VMCB_CTRL_INTERCEPT_RGDTR __BIT(7)
sys/dev/nvmm/x86/nvmm_x86_svm.c
270
#define VMCB_CTRL_INTERCEPT_RLDTR __BIT(8)
sys/dev/nvmm/x86/nvmm_x86_svm.c
271
#define VMCB_CTRL_INTERCEPT_RTR __BIT(9)
sys/dev/nvmm/x86/nvmm_x86_svm.c
272
#define VMCB_CTRL_INTERCEPT_WIDTR __BIT(10)
sys/dev/nvmm/x86/nvmm_x86_svm.c
273
#define VMCB_CTRL_INTERCEPT_WGDTR __BIT(11)
sys/dev/nvmm/x86/nvmm_x86_svm.c
274
#define VMCB_CTRL_INTERCEPT_WLDTR __BIT(12)
sys/dev/nvmm/x86/nvmm_x86_svm.c
275
#define VMCB_CTRL_INTERCEPT_WTR __BIT(13)
sys/dev/nvmm/x86/nvmm_x86_svm.c
276
#define VMCB_CTRL_INTERCEPT_RDTSC __BIT(14)
sys/dev/nvmm/x86/nvmm_x86_svm.c
277
#define VMCB_CTRL_INTERCEPT_RDPMC __BIT(15)
sys/dev/nvmm/x86/nvmm_x86_svm.c
278
#define VMCB_CTRL_INTERCEPT_PUSHF __BIT(16)
sys/dev/nvmm/x86/nvmm_x86_svm.c
2785
svm_asidmap[0] |= __BIT(0);
sys/dev/nvmm/x86/nvmm_x86_svm.c
279
#define VMCB_CTRL_INTERCEPT_POPF __BIT(17)
sys/dev/nvmm/x86/nvmm_x86_svm.c
2790
svm_asidmap[i] |= __BIT(j);
sys/dev/nvmm/x86/nvmm_x86_svm.c
280
#define VMCB_CTRL_INTERCEPT_CPUID __BIT(18)
sys/dev/nvmm/x86/nvmm_x86_svm.c
281
#define VMCB_CTRL_INTERCEPT_RSM __BIT(19)
sys/dev/nvmm/x86/nvmm_x86_svm.c
282
#define VMCB_CTRL_INTERCEPT_IRET __BIT(20)
sys/dev/nvmm/x86/nvmm_x86_svm.c
283
#define VMCB_CTRL_INTERCEPT_INTN __BIT(21)
sys/dev/nvmm/x86/nvmm_x86_svm.c
284
#define VMCB_CTRL_INTERCEPT_INVD __BIT(22)
sys/dev/nvmm/x86/nvmm_x86_svm.c
285
#define VMCB_CTRL_INTERCEPT_PAUSE __BIT(23)
sys/dev/nvmm/x86/nvmm_x86_svm.c
286
#define VMCB_CTRL_INTERCEPT_HLT __BIT(24)
sys/dev/nvmm/x86/nvmm_x86_svm.c
287
#define VMCB_CTRL_INTERCEPT_INVLPG __BIT(25)
sys/dev/nvmm/x86/nvmm_x86_svm.c
288
#define VMCB_CTRL_INTERCEPT_INVLPGA __BIT(26)
sys/dev/nvmm/x86/nvmm_x86_svm.c
289
#define VMCB_CTRL_INTERCEPT_IOIO_PROT __BIT(27)
sys/dev/nvmm/x86/nvmm_x86_svm.c
290
#define VMCB_CTRL_INTERCEPT_MSR_PROT __BIT(28)
sys/dev/nvmm/x86/nvmm_x86_svm.c
291
#define VMCB_CTRL_INTERCEPT_TASKSW __BIT(29)
sys/dev/nvmm/x86/nvmm_x86_svm.c
292
#define VMCB_CTRL_INTERCEPT_FERR_FREEZE __BIT(30)
sys/dev/nvmm/x86/nvmm_x86_svm.c
293
#define VMCB_CTRL_INTERCEPT_SHUTDOWN __BIT(31)
sys/dev/nvmm/x86/nvmm_x86_svm.c
296
#define VMCB_CTRL_INTERCEPT_VMRUN __BIT(0)
sys/dev/nvmm/x86/nvmm_x86_svm.c
297
#define VMCB_CTRL_INTERCEPT_VMMCALL __BIT(1)
sys/dev/nvmm/x86/nvmm_x86_svm.c
298
#define VMCB_CTRL_INTERCEPT_VMLOAD __BIT(2)
sys/dev/nvmm/x86/nvmm_x86_svm.c
299
#define VMCB_CTRL_INTERCEPT_VMSAVE __BIT(3)
sys/dev/nvmm/x86/nvmm_x86_svm.c
300
#define VMCB_CTRL_INTERCEPT_STGI __BIT(4)
sys/dev/nvmm/x86/nvmm_x86_svm.c
301
#define VMCB_CTRL_INTERCEPT_CLGI __BIT(5)
sys/dev/nvmm/x86/nvmm_x86_svm.c
302
#define VMCB_CTRL_INTERCEPT_SKINIT __BIT(6)
sys/dev/nvmm/x86/nvmm_x86_svm.c
303
#define VMCB_CTRL_INTERCEPT_RDTSCP __BIT(7)
sys/dev/nvmm/x86/nvmm_x86_svm.c
304
#define VMCB_CTRL_INTERCEPT_ICEBP __BIT(8)
sys/dev/nvmm/x86/nvmm_x86_svm.c
305
#define VMCB_CTRL_INTERCEPT_WBINVD __BIT(9)
sys/dev/nvmm/x86/nvmm_x86_svm.c
306
#define VMCB_CTRL_INTERCEPT_MONITOR __BIT(10)
sys/dev/nvmm/x86/nvmm_x86_svm.c
307
#define VMCB_CTRL_INTERCEPT_MWAIT __BIT(11)
sys/dev/nvmm/x86/nvmm_x86_svm.c
308
#define VMCB_CTRL_INTERCEPT_MWAIT_ARMED __BIT(12)
sys/dev/nvmm/x86/nvmm_x86_svm.c
309
#define VMCB_CTRL_INTERCEPT_XSETBV __BIT(13)
sys/dev/nvmm/x86/nvmm_x86_svm.c
310
#define VMCB_CTRL_INTERCEPT_RDPRU __BIT(14)
sys/dev/nvmm/x86/nvmm_x86_svm.c
311
#define VMCB_CTRL_INTERCEPT_EFER_SPEC __BIT(15)
sys/dev/nvmm/x86/nvmm_x86_svm.c
312
#define VMCB_CTRL_INTERCEPT_WCR_SPEC(x) __BIT(16 + x)
sys/dev/nvmm/x86/nvmm_x86_svm.c
315
#define VMCB_CTRL_INTERCEPT_INVLPGB_ALL __BIT(0)
sys/dev/nvmm/x86/nvmm_x86_svm.c
316
#define VMCB_CTRL_INTERCEPT_INVLPGB_ILL __BIT(1)
sys/dev/nvmm/x86/nvmm_x86_svm.c
317
#define VMCB_CTRL_INTERCEPT_PCID __BIT(2)
sys/dev/nvmm/x86/nvmm_x86_svm.c
318
#define VMCB_CTRL_INTERCEPT_MCOMMIT __BIT(3)
sys/dev/nvmm/x86/nvmm_x86_svm.c
319
#define VMCB_CTRL_INTERCEPT_TLBSYNC __BIT(4)
sys/dev/nvmm/x86/nvmm_x86_svm.c
336
#define VMCB_CTRL_V_IRQ __BIT(8)
sys/dev/nvmm/x86/nvmm_x86_svm.c
337
#define VMCB_CTRL_V_VGIF __BIT(9)
sys/dev/nvmm/x86/nvmm_x86_svm.c
339
#define VMCB_CTRL_V_IGN_TPR __BIT(20)
sys/dev/nvmm/x86/nvmm_x86_svm.c
340
#define VMCB_CTRL_V_INTR_MASKING __BIT(24)
sys/dev/nvmm/x86/nvmm_x86_svm.c
341
#define VMCB_CTRL_V_GUEST_VGIF __BIT(25)
sys/dev/nvmm/x86/nvmm_x86_svm.c
342
#define VMCB_CTRL_V_AVIC_EN __BIT(31)
sys/dev/nvmm/x86/nvmm_x86_svm.c
346
#define VMCB_CTRL_INTR_SHADOW __BIT(0)
sys/dev/nvmm/x86/nvmm_x86_svm.c
347
#define VMCB_CTRL_INTR_MASK __BIT(1)
sys/dev/nvmm/x86/nvmm_x86_svm.c
356
#define VMCB_CTRL_EXITINTINFO_EV __BIT(11)
sys/dev/nvmm/x86/nvmm_x86_svm.c
357
#define VMCB_CTRL_EXITINTINFO_V __BIT(31)
sys/dev/nvmm/x86/nvmm_x86_svm.c
361
#define VMCB_CTRL_ENABLE_NP __BIT(0)
sys/dev/nvmm/x86/nvmm_x86_svm.c
362
#define VMCB_CTRL_ENABLE_SEV __BIT(1)
sys/dev/nvmm/x86/nvmm_x86_svm.c
363
#define VMCB_CTRL_ENABLE_ES_SEV __BIT(2)
sys/dev/nvmm/x86/nvmm_x86_svm.c
364
#define VMCB_CTRL_ENABLE_GMET __BIT(3)
sys/dev/nvmm/x86/nvmm_x86_svm.c
365
#define VMCB_CTRL_ENABLE_VTE __BIT(5)
sys/dev/nvmm/x86/nvmm_x86_svm.c
375
#define VMCB_CTRL_EVENTINJ_EV __BIT(11)
sys/dev/nvmm/x86/nvmm_x86_svm.c
376
#define VMCB_CTRL_EVENTINJ_V __BIT(31)
sys/dev/nvmm/x86/nvmm_x86_svm.c
382
#define VMCB_CTRL_ENABLE_LBR __BIT(0)
sys/dev/nvmm/x86/nvmm_x86_svm.c
383
#define VMCB_CTRL_ENABLE_VVMSAVE __BIT(1)
sys/dev/nvmm/x86/nvmm_x86_svm.c
386
#define VMCB_CTRL_VMCB_CLEAN_I __BIT(0)
sys/dev/nvmm/x86/nvmm_x86_svm.c
387
#define VMCB_CTRL_VMCB_CLEAN_IOPM __BIT(1)
sys/dev/nvmm/x86/nvmm_x86_svm.c
388
#define VMCB_CTRL_VMCB_CLEAN_ASID __BIT(2)
sys/dev/nvmm/x86/nvmm_x86_svm.c
389
#define VMCB_CTRL_VMCB_CLEAN_TPR __BIT(3)
sys/dev/nvmm/x86/nvmm_x86_svm.c
390
#define VMCB_CTRL_VMCB_CLEAN_NP __BIT(4)
sys/dev/nvmm/x86/nvmm_x86_svm.c
391
#define VMCB_CTRL_VMCB_CLEAN_CR __BIT(5)
sys/dev/nvmm/x86/nvmm_x86_svm.c
392
#define VMCB_CTRL_VMCB_CLEAN_DR __BIT(6)
sys/dev/nvmm/x86/nvmm_x86_svm.c
393
#define VMCB_CTRL_VMCB_CLEAN_DT __BIT(7)
sys/dev/nvmm/x86/nvmm_x86_svm.c
394
#define VMCB_CTRL_VMCB_CLEAN_SEG __BIT(8)
sys/dev/nvmm/x86/nvmm_x86_svm.c
395
#define VMCB_CTRL_VMCB_CLEAN_CR2 __BIT(9)
sys/dev/nvmm/x86/nvmm_x86_svm.c
396
#define VMCB_CTRL_VMCB_CLEAN_LBR __BIT(10)
sys/dev/nvmm/x86/nvmm_x86_svm.c
397
#define VMCB_CTRL_VMCB_CLEAN_AVIC __BIT(11)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
1454
if ((cpudata->xcr0_mask & __BIT(ecx)) == 0) {
sys/dev/nvmm/x86/nvmm_x86_vmx.c
1622
#define VMX_QUAL_CR_LMSW_OPMEM __BIT(6)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
1624
#define VMX_QUAL_CR_LMSW_SRC __BIT(31,16)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
1824
#define VMX_QUAL_IO_IN __BIT(3)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
1825
#define VMX_QUAL_IO_STR __BIT(4)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
1826
#define VMX_QUAL_IO_REP __BIT(5)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
1827
#define VMX_QUAL_IO_DX __BIT(6)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
193
#define IA32_FEATURE_CONTROL_LOCK __BIT(0)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
194
#define IA32_FEATURE_CONTROL_IN_SMX __BIT(1)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
195
#define IA32_FEATURE_CONTROL_OUT_SMX __BIT(2)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
200
#define IA32_VMX_BASIC_MEM_WIDTH __BIT(48)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
201
#define IA32_VMX_BASIC_DUAL __BIT(49)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
205
#define IA32_VMX_BASIC_IO_REPORT __BIT(54)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
2054
#define VMX_EPT_VIOLATION_READ __BIT(0)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
2055
#define VMX_EPT_VIOLATION_WRITE __BIT(1)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
2056
#define VMX_EPT_VIOLATION_EXECUTE __BIT(2)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
206
#define IA32_VMX_BASIC_TRUE_CTLS __BIT(55)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
225
#define IA32_VMX_EPT_VPID_XO __BIT(0)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
226
#define IA32_VMX_EPT_VPID_WALKLENGTH_4 __BIT(6)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
227
#define IA32_VMX_EPT_VPID_UC __BIT(8)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
228
#define IA32_VMX_EPT_VPID_WB __BIT(14)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
229
#define IA32_VMX_EPT_VPID_2MB __BIT(16)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
230
#define IA32_VMX_EPT_VPID_1GB __BIT(17)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
231
#define IA32_VMX_EPT_VPID_INVEPT __BIT(20)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
232
#define IA32_VMX_EPT_VPID_FLAGS_AD __BIT(21)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
233
#define IA32_VMX_EPT_VPID_ADVANCED_VMEXIT_INFO __BIT(22)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
234
#define IA32_VMX_EPT_VPID_SHSTK __BIT(23)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
235
#define IA32_VMX_EPT_VPID_INVEPT_CONTEXT __BIT(25)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
236
#define IA32_VMX_EPT_VPID_INVEPT_ALL __BIT(26)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
237
#define IA32_VMX_EPT_VPID_INVVPID __BIT(32)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
238
#define IA32_VMX_EPT_VPID_INVVPID_ADDR __BIT(40)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
239
#define IA32_VMX_EPT_VPID_INVVPID_CONTEXT __BIT(41)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
240
#define IA32_VMX_EPT_VPID_INVVPID_ALL __BIT(42)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
241
#define IA32_VMX_EPT_VPID_INVVPID_CONTEXT_NOG __BIT(43)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
2648
bitmap[byte] &= ~__BIT(bitoff);
sys/dev/nvmm/x86/nvmm_x86_vmx.c
2651
bitmap[2048 + byte] &= ~__BIT(bitoff);
sys/dev/nvmm/x86/nvmm_x86_vmx.c
2656
#define VMX_SEG_ATTRIB_S __BIT(4)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
2658
#define VMX_SEG_ATTRIB_P __BIT(7)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
2659
#define VMX_SEG_ATTRIB_AVL __BIT(12)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
2660
#define VMX_SEG_ATTRIB_L __BIT(13)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
2661
#define VMX_SEG_ATTRIB_DEF __BIT(14)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
2662
#define VMX_SEG_ATTRIB_G __BIT(15)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
2663
#define VMX_SEG_ATTRIB_UNUSABLE __BIT(16)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
287
#define EPTP_FLAGS_AD __BIT(6)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
288
#define EPTP_SSS __BIT(7)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3043
if (vmx_asidmap[oct] & __BIT(bit)) {
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3049
vmx_asidmap[oct] |= __BIT(bit);
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3072
vmx_asidmap[oct] &= ~__BIT(bit);
sys/dev/nvmm/x86/nvmm_x86_vmx.c
325
#define PIN_CTLS_INT_EXITING __BIT(0)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
326
#define PIN_CTLS_NMI_EXITING __BIT(3)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
327
#define PIN_CTLS_VIRTUAL_NMIS __BIT(5)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
328
#define PIN_CTLS_ACTIVATE_PREEMPT_TIMER __BIT(6)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
329
#define PIN_CTLS_PROCESS_POSTED_INTS __BIT(7)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
331
#define PROC_CTLS_INT_WINDOW_EXITING __BIT(2)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
332
#define PROC_CTLS_USE_TSC_OFFSETTING __BIT(3)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
333
#define PROC_CTLS_HLT_EXITING __BIT(7)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
334
#define PROC_CTLS_INVLPG_EXITING __BIT(9)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
335
#define PROC_CTLS_MWAIT_EXITING __BIT(10)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
336
#define PROC_CTLS_RDPMC_EXITING __BIT(11)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
337
#define PROC_CTLS_RDTSC_EXITING __BIT(12)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
338
#define PROC_CTLS_RCR3_EXITING __BIT(15)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
339
#define PROC_CTLS_LCR3_EXITING __BIT(16)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
340
#define PROC_CTLS_RCR8_EXITING __BIT(19)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
341
#define PROC_CTLS_LCR8_EXITING __BIT(20)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
342
#define PROC_CTLS_USE_TPR_SHADOW __BIT(21)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
343
#define PROC_CTLS_NMI_WINDOW_EXITING __BIT(22)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
344
#define PROC_CTLS_DR_EXITING __BIT(23)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
345
#define PROC_CTLS_UNCOND_IO_EXITING __BIT(24)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
346
#define PROC_CTLS_USE_IO_BITMAPS __BIT(25)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
347
#define PROC_CTLS_MONITOR_TRAP_FLAG __BIT(27)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
348
#define PROC_CTLS_USE_MSR_BITMAPS __BIT(28)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
349
#define PROC_CTLS_MONITOR_EXITING __BIT(29)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
350
#define PROC_CTLS_PAUSE_EXITING __BIT(30)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3507
((msrval & __BIT(32 + bitoff)) != 0)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3509
((msrval & __BIT(bitoff)) == 0)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
351
#define PROC_CTLS_ACTIVATE_CTLS2 __BIT(31)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3529
if (!(set_one & __BIT(i))) {
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3563
if (set_one & __BIT(i))
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3565
*res &= ~__BIT(i);
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3567
if (set_zero & __BIT(i))
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3569
*res |= __BIT(i);
sys/dev/nvmm/x86/nvmm_x86_vmx.c
357
#define EXIT_CTLS_SAVE_DEBUG_CONTROLS __BIT(2)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3571
if (set_zero & __BIT(i)) {
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3572
*res &= ~__BIT(i);
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3573
} else if (set_one & __BIT(i)) {
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3574
*res |= __BIT(i);
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3576
*res &= ~__BIT(i);
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3578
*res &= ~__BIT(i);
sys/dev/nvmm/x86/nvmm_x86_vmx.c
358
#define EXIT_CTLS_HOST_LONG_MODE __BIT(9)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3580
*res |= __BIT(i);
sys/dev/nvmm/x86/nvmm_x86_vmx.c
359
#define EXIT_CTLS_LOAD_PERFGLOBALCTRL __BIT(12)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
360
#define EXIT_CTLS_ACK_INTERRUPT __BIT(15)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
361
#define EXIT_CTLS_SAVE_PAT __BIT(18)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
362
#define EXIT_CTLS_LOAD_PAT __BIT(19)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
363
#define EXIT_CTLS_SAVE_EFER __BIT(20)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
364
#define EXIT_CTLS_LOAD_EFER __BIT(21)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
365
#define EXIT_CTLS_SAVE_PREEMPT_TIMER __BIT(22)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
366
#define EXIT_CTLS_CLEAR_BNDCFGS __BIT(23)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
367
#define EXIT_CTLS_CONCEAL_PT __BIT(24)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
368
#define EXIT_CTLS_CLEAR_RTIT_CTL __BIT(25)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
369
#define EXIT_CTLS_LOAD_CET __BIT(28)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
370
#define EXIT_CTLS_LOAD_PKRS __BIT(29)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
3720
vmx_asidmap[0] |= __BIT(0);
sys/dev/nvmm/x86/nvmm_x86_vmx.c
374
#define ENTRY_CTLS_LOAD_DEBUG_CONTROLS __BIT(2)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
375
#define ENTRY_CTLS_LONG_MODE __BIT(9)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
376
#define ENTRY_CTLS_SMM __BIT(10)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
377
#define ENTRY_CTLS_DISABLE_DUAL __BIT(11)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
378
#define ENTRY_CTLS_LOAD_PERFGLOBALCTRL __BIT(13)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
379
#define ENTRY_CTLS_LOAD_PAT __BIT(14)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
380
#define ENTRY_CTLS_LOAD_EFER __BIT(15)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
381
#define ENTRY_CTLS_LOAD_BNDCFGS __BIT(16)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
382
#define ENTRY_CTLS_CONCEAL_PT __BIT(17)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
383
#define ENTRY_CTLS_LOAD_RTIT_CTL __BIT(18)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
384
#define ENTRY_CTLS_LOAD_CET __BIT(20)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
385
#define ENTRY_CTLS_LOAD_PKRS __BIT(22)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
397
#define INTR_INFO_ERROR __BIT(11)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
398
#define INTR_INFO_VALID __BIT(31)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
403
#define PROC_CTLS2_VIRT_APIC_ACCESSES __BIT(0)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
404
#define PROC_CTLS2_ENABLE_EPT __BIT(1)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
405
#define PROC_CTLS2_DESC_TABLE_EXITING __BIT(2)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
406
#define PROC_CTLS2_ENABLE_RDTSCP __BIT(3)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
407
#define PROC_CTLS2_VIRT_X2APIC __BIT(4)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
408
#define PROC_CTLS2_ENABLE_VPID __BIT(5)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
409
#define PROC_CTLS2_WBINVD_EXITING __BIT(6)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
410
#define PROC_CTLS2_UNRESTRICTED_GUEST __BIT(7)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
411
#define PROC_CTLS2_APIC_REG_VIRT __BIT(8)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
412
#define PROC_CTLS2_VIRT_INT_DELIVERY __BIT(9)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
413
#define PROC_CTLS2_PAUSE_LOOP_EXITING __BIT(10)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
414
#define PROC_CTLS2_RDRAND_EXITING __BIT(11)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
415
#define PROC_CTLS2_INVPCID_ENABLE __BIT(12)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
416
#define PROC_CTLS2_VMFUNC_ENABLE __BIT(13)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
417
#define PROC_CTLS2_VMCS_SHADOWING __BIT(14)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
418
#define PROC_CTLS2_ENCLS_EXITING __BIT(15)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
419
#define PROC_CTLS2_RDSEED_EXITING __BIT(16)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
420
#define PROC_CTLS2_PML_ENABLE __BIT(17)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
421
#define PROC_CTLS2_EPT_VIOLATION __BIT(18)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
422
#define PROC_CTLS2_CONCEAL_VMX_FROM_PT __BIT(19)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
423
#define PROC_CTLS2_XSAVES_ENABLE __BIT(20)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
424
#define PROC_CTLS2_MODE_BASED_EXEC_EPT __BIT(22)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
425
#define PROC_CTLS2_SUBPAGE_PERMISSIONS __BIT(23)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
426
#define PROC_CTLS2_PT_USES_GPA __BIT(24)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
427
#define PROC_CTLS2_USE_TSC_SCALING __BIT(25)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
428
#define PROC_CTLS2_WAIT_PAUSE_ENABLE __BIT(26)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
429
#define PROC_CTLS2_ENCLV_EXITING __BIT(28)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
461
#define INT_STATE_STI __BIT(0)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
462
#define INT_STATE_MOVSS __BIT(1)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
463
#define INT_STATE_SMI __BIT(2)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
464
#define INT_STATE_NMI __BIT(3)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
465
#define INT_STATE_ENCLAVE __BIT(4)
sys/dev/nvmm/x86/nvmm_x86_vmx.c
631
#define VMCS_IDENT_SHADOW __BIT(31)
sys/dev/ofw/ofw_isa.h
59
#define OFW_ISA_PHYS_HI_IO __BIT(0)
sys/dev/ofw/ofw_isa.h
60
#define OFW_ISA_PHYS_HI_10BIT __BIT(1)
sys/dev/ofw/ofw_isa.h
61
#define OFW_ISA_PHYS_HI_11BIT __BIT(2)
sys/dev/pci/agp_i810.c
219
WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31));
sys/dev/pci/agp_i810.c
220
while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) {
sys/dev/pci/coram.c
358
if (val & __BIT(2))
sys/dev/pci/coram.c
361
if (val & ~__BIT(2))
sys/dev/pci/coram.c
817
v & __BIT(2));
sys/dev/pci/coram.c
903
v |= __BIT(5); /* Enable RISC controller */
sys/dev/pci/cx23885reg.h
116
#define CMDS_IQS_ISRP __BIT(31)
sys/dev/pci/cxdtvreg.h
105
#define CXDTV_TS_RISC_EN __BIT(4)
sys/dev/pci/cxdtvreg.h
106
#define CXDTV_TS_FIFO_EN __BIT(0)
sys/dev/pci/cxdtvreg.h
109
#define CXDTV_TS_RISCI2 __BIT(4)
sys/dev/pci/cxdtvreg.h
110
#define CXDTV_TS_RISCI1 __BIT(0)
sys/dev/pci/cxdtvreg.h
116
#define MPEG_IN_SYNC __BIT(0)
sys/dev/pci/cxdtvreg.h
117
#define IPB_MCLK_POL __BIT(1)
sys/dev/pci/cxdtvreg.h
118
#define IPB_PUNC_CLK __BIT(2)
sys/dev/pci/cxdtvreg.h
119
#define IPB_SMODE __BIT(3)
sys/dev/pci/cxdtvreg.h
120
#define IPB_BIT_RVRS __BIT(4)
sys/dev/pci/cxdtvreg.h
121
#define IPB_ERR_ACK __BIT(5)
sys/dev/pci/cxdtvreg.h
122
#define IPB_SW_RST __BIT(6)
sys/dev/pci/cxdtvreg.h
123
#define IPB_STAT_CLR __BIT(7)
sys/dev/pci/cxdtvreg.h
127
#define IPB_SOP_SYNC_CHK __BIT(12)
sys/dev/pci/cxdtvreg.h
128
#define IPB_SOP_BYTEWIDE __BIT(13)
sys/dev/pci/cxdtvreg.h
130
#define IPB_TSSOP_POL __BIT(16)
sys/dev/pci/cxdtvreg.h
167
#define CX_CMDS_IQS_ISRP __BIT(31)
sys/dev/pci/cxdtvreg.h
71
#define CXT_PI_VID_INT __BIT(0)
sys/dev/pci/cxdtvreg.h
72
#define CXT_PI_AUD_INT __BIT(1)
sys/dev/pci/cxdtvreg.h
73
#define CXT_PI_TS_INT __BIT(2)
sys/dev/pci/cxdtvreg.h
74
#define CXT_PI_VIP_INT __BIT(3)
sys/dev/pci/cxdtvreg.h
75
#define CXT_PI_HST_INT __BIT(4)
sys/dev/pci/cxdtvreg.h
77
#define CXDTV_DEV_CNTRL2_RUN_RISC __BIT(5)
sys/dev/pci/cxdtvreg.h
80
#define MPEG_PAR_EN __BIT(7)
sys/dev/pci/ehci_pci.c
101
#define EHCI_SBx00_WORKAROUND_ENABLE __BIT(27)
sys/dev/pci/hdaudio_pci.h
46
#define HDAUDIO_INTEL_PCH_CGCTL_MISCBDCGE __BIT(6)
sys/dev/pci/hdaudio_pci.h
48
#define HDAUDIO_INTEL_PCH_DEVC_NSNPEN __BIT(11)
sys/dev/pci/if_aq.c
1102
AQ_LINK_10G = __BIT(0),
sys/dev/pci/if_aq.c
1103
AQ_LINK_5G = __BIT(1),
sys/dev/pci/if_aq.c
1104
AQ_LINK_2G5 = __BIT(2),
sys/dev/pci/if_aq.c
1105
AQ_LINK_1G = __BIT(3),
sys/dev/pci/if_aq.c
1106
AQ_LINK_100M = __BIT(4),
sys/dev/pci/if_aq.c
1107
AQ_LINK_10M = __BIT(5)
sys/dev/pci/if_aq.c
1115
AQ_FC_RX = __BIT(0),
sys/dev/pci/if_aq.c
1116
AQ_FC_TX = __BIT(1),
sys/dev/pci/if_aq.c
1164
#define RXDESC_TYPE_PKTTYPE_VLAN __BIT(9)
sys/dev/pci/if_aq.c
1165
#define RXDESC_TYPE_PKTTYPE_VLAN_DOUBLE __BIT(10)
sys/dev/pci/if_aq.c
1166
#define RXDESC_TYPE_MAC_DMA_ERR __BIT(12)
sys/dev/pci/if_aq.c
1168
#define RXDESC_TYPE_IPV4_CSUM_CHECKED __BIT(19) /* PKTTYPE_ETHER_IPV4 */
sys/dev/pci/if_aq.c
1169
#define RXDESC_TYPE_TCPUDP_CSUM_CHECKED __BIT(20)
sys/dev/pci/if_aq.c
1170
#define RXDESC_TYPE_SPH __BIT(21)
sys/dev/pci/if_aq.c
1174
#define RXDESC_STATUS_DD __BIT(0)
sys/dev/pci/if_aq.c
1175
#define RXDESC_STATUS_EOP __BIT(1)
sys/dev/pci/if_aq.c
1176
#define RXDESC_STATUS_MACERR __BIT(2)
sys/dev/pci/if_aq.c
1177
#define RXDESC_STATUS_IPV4_CSUM_NG __BIT(3)
sys/dev/pci/if_aq.c
1178
#define RXDESC_STATUS_TCPUDP_CSUM_ERROR __BIT(4)
sys/dev/pci/if_aq.c
1179
#define RXDESC_STATUS_TCPUDP_CSUM_OK __BIT(5)
sys/dev/pci/if_aq.c
1201
#define AQ_TXDESC_CTL1_DD __BIT(20) /* TXD */
sys/dev/pci/if_aq.c
1202
#define AQ_TXDESC_CTL1_EOP __BIT(21) /* TXD */
sys/dev/pci/if_aq.c
1203
#define AQ_TXDESC_CTL1_CMD_VLAN __BIT(22) /* TXD */
sys/dev/pci/if_aq.c
1204
#define AQ_TXDESC_CTL1_CMD_FCS __BIT(23) /* TXD */
sys/dev/pci/if_aq.c
1205
#define AQ_TXDESC_CTL1_CMD_IP4CSUM __BIT(24) /* TXD */
sys/dev/pci/if_aq.c
1206
#define AQ_TXDESC_CTL1_CMD_L4CSUM __BIT(25) /* TXD */
sys/dev/pci/if_aq.c
1207
#define AQ_TXDESC_CTL1_CMD_LSO __BIT(26) /* TXD */
sys/dev/pci/if_aq.c
1208
#define AQ_TXDESC_CTL1_CMD_WB __BIT(27) /* TXD */
sys/dev/pci/if_aq.c
1209
#define AQ_TXDESC_CTL1_CMD_VXLAN __BIT(28) /* TXD */
sys/dev/pci/if_aq.c
1211
#define AQ_TXDESC_CTL1_LSO_IPV6 __BIT(21) /* TXC */
sys/dev/pci/if_aq.c
1212
#define AQ_TXDESC_CTL1_LSO_TCP __BIT(22) /* TXC */
sys/dev/pci/if_aq.c
1215
#define AQ_TXDESC_CTL2_CTX_EN __BIT(13)
sys/dev/pci/if_aq.c
1216
#define AQ_TXDESC_CTL2_CTX_IDX __BIT(12)
sys/dev/pci/if_aq.c
144
#define AQ_FW_SOFTRESET_RESET __BIT(15) /* soft reset bit */
sys/dev/pci/if_aq.c
145
#define AQ_FW_SOFTRESET_DIS __BIT(14) /* reset disable */
sys/dev/pci/if_aq.c
200
#define AQ_FW_GLB_CTL2_MCP_UP_FORCE_INTERRUPT __BIT(1)
sys/dev/pci/if_aq.c
220
#define AQ_INTR_IRQ_MAP_TX_EN(i) (__BIT(31) >> (((i) & 1)*8))
sys/dev/pci/if_aq.c
223
#define AQ_INTR_IRQ_MAP_RX_EN(i) (__BIT(15) >> (((i) & 1)*8))
sys/dev/pci/if_aq.c
234
#define AQ_INTR_CTRL_MULTIVEC __BIT(2)
sys/dev/pci/if_aq.c
235
#define AQ_INTR_CTRL_AUTO_MASK __BIT(5)
sys/dev/pci/if_aq.c
236
#define AQ_INTR_CTRL_CLR_ON_READ __BIT(7)
sys/dev/pci/if_aq.c
237
#define AQ_INTR_CTRL_RESET_DIS __BIT(29)
sys/dev/pci/if_aq.c
238
#define AQ_INTR_CTRL_RESET_IRQ __BIT(31)
sys/dev/pci/if_aq.c
243
#define FW_MPI_RESETCTRL_RESET_DIS __BIT(29)
sys/dev/pci/if_aq.c
246
#define RX_SYSCONTROL_RPF_TPO_SYS_LOOPBACK __BIT(8)
sys/dev/pci/if_aq.c
247
#define RX_SYSCONTROL_RPB_DMA_SYS_LOOPBACK __BIT(6)
sys/dev/pci/if_aq.c
248
#define RX_SYSCONTROL_RPB_DMA_NET_LOOPBACK __BIT(4)
sys/dev/pci/if_aq.c
249
#define RX_SYSCONTROL_RESET_DIS __BIT(29)
sys/dev/pci/if_aq.c
263
#define RPF_L2BC_EN __BIT(0)
sys/dev/pci/if_aq.c
264
#define RPF_L2BC_PROMISC __BIT(3)
sys/dev/pci/if_aq.c
274
#define RPF_L2UC_MSW_EN __BIT(31)
sys/dev/pci/if_aq.c
284
#define RPF_MCAST_FILTER_EN __BIT(31)
sys/dev/pci/if_aq.c
286
#define RPF_MCAST_FILTER_MASK_ALLMULTI __BIT(14)
sys/dev/pci/if_aq.c
289
#define RPF_VLAN_MODE_PROMISC __BIT(1)
sys/dev/pci/if_aq.c
290
#define RPF_VLAN_MODE_ACCEPT_UNTAGGED __BIT(2)
sys/dev/pci/if_aq.c
300
#define RPF_VLAN_FILTER_EN __BIT(31)
sys/dev/pci/if_aq.c
301
#define RPF_VLAN_FILTER_RXQ_EN __BIT(28)
sys/dev/pci/if_aq.c
309
#define RPF_ETHERTYPE_FILTER_EN __BIT(31)
sys/dev/pci/if_aq.c
310
#define RPF_ETHERTYPE_FILTER_PRIO_EN __BIT(30)
sys/dev/pci/if_aq.c
311
#define RPF_ETHERTYPE_FILTER_RXQF_EN __BIT(29)
sys/dev/pci/if_aq.c
314
#define RPF_ETHERTYPE_FILTER_MNG_RXQF __BIT(19)
sys/dev/pci/if_aq.c
320
#define RPF_L3_FILTER_L4_EN __BIT(31)
sys/dev/pci/if_aq.c
321
#define RPF_L3_FILTER_IPV6_EN __BIT(30)
sys/dev/pci/if_aq.c
322
#define RPF_L3_FILTER_SRCADDR_EN __BIT(29)
sys/dev/pci/if_aq.c
323
#define RPF_L3_FILTER_DSTADDR_EN __BIT(28)
sys/dev/pci/if_aq.c
324
#define RPF_L3_FILTER_L4_SRCPORT_EN __BIT(27)
sys/dev/pci/if_aq.c
325
#define RPF_L3_FILTER_L4_DSTPORT_EN __BIT(26)
sys/dev/pci/if_aq.c
326
#define RPF_L3_FILTER_L4_PROTO_EN __BIT(25)
sys/dev/pci/if_aq.c
327
#define RPF_L3_FILTER_ARP_EN __BIT(24)
sys/dev/pci/if_aq.c
328
#define RPF_L3_FILTER_L4_RXQUEUE_EN __BIT(23)
sys/dev/pci/if_aq.c
329
#define RPF_L3_FILTER_L4_RXQUEUE_MANAGEMENT_EN __BIT(22)
sys/dev/pci/if_aq.c
344
#define RX_FLR_RSS_CONTROL1_EN __BIT(31)
sys/dev/pci/if_aq.c
351
#define RPF_RSS_KEY_WR_EN __BIT(5)
sys/dev/pci/if_aq.c
357
#define RPF_RSS_REDIR_WR_EN __BIT(4)
sys/dev/pci/if_aq.c
363
#define RPO_HWCSUM_IP4CSUM_EN __BIT(1)
sys/dev/pci/if_aq.c
364
#define RPO_HWCSUM_L4CSUM_EN __BIT(0) /* TCP/UDP/SCTP */
sys/dev/pci/if_aq.c
371
#define RPO_LRO_CONF_PATCHOPTIMIZATION_EN __BIT(15)
sys/dev/pci/if_aq.c
386
#define RPB_RPF_RX_TC_MODE __BIT(8)
sys/dev/pci/if_aq.c
388
#define RPB_RPF_RX_BUF_EN __BIT(0)
sys/dev/pci/if_aq.c
394
#define RPB_RXB_XOFF_EN __BIT(31)
sys/dev/pci/if_aq.c
399
#define RX_DMA_DESC_CACHE_INIT __BIT(0)
sys/dev/pci/if_aq.c
402
#define RX_DMA_INT_DESC_WRWB_EN __BIT(2)
sys/dev/pci/if_aq.c
403
#define RX_DMA_INT_DESC_MODERATE_EN __BIT(3)
sys/dev/pci/if_aq.c
407
#define RX_INTR_MODERATION_CTL_EN __BIT(1)
sys/dev/pci/if_aq.c
416
#define RX_DMA_DESC_RESET __BIT(25)
sys/dev/pci/if_aq.c
417
#define RX_DMA_DESC_HEADER_SPLIT __BIT(28)
sys/dev/pci/if_aq.c
418
#define RX_DMA_DESC_VLAN_STRIP __BIT(29)
sys/dev/pci/if_aq.c
419
#define RX_DMA_DESC_EN __BIT(31)
sys/dev/pci/if_aq.c
430
#define RX_DMA_DCAD_PAYLOAD_EN __BIT(29)
sys/dev/pci/if_aq.c
431
#define RX_DMA_DCAD_HEADER_EN __BIT(30)
sys/dev/pci/if_aq.c
432
#define RX_DMA_DCAD_DESC_EN __BIT(31)
sys/dev/pci/if_aq.c
435
#define RX_DMA_DCA_EN __BIT(31)
sys/dev/pci/if_aq.c
445
#define TX_SYSCONTROL_TPO_PKT_SYS_LOOPBACK __BIT(7)
sys/dev/pci/if_aq.c
446
#define TX_SYSCONTROL_TPB_DMA_SYS_LOOPBACK __BIT(6)
sys/dev/pci/if_aq.c
447
#define TX_SYSCONTROL_TPB_DMA_NET_LOOPBACK __BIT(4)
sys/dev/pci/if_aq.c
448
#define TX_SYSCONTROL_RESET_DIS __BIT(29)
sys/dev/pci/if_aq.c
4487
__BIT(7) | sc->sc_linkstat_irq);
sys/dev/pci/if_aq.c
451
#define TX_TPO2_EN __BIT(16)
sys/dev/pci/if_aq.c
454
#define TPS_DESC_VM_ARB_MODE __BIT(0)
sys/dev/pci/if_aq.c
456
#define TPS_DESC_RATE_TA_RST __BIT(31)
sys/dev/pci/if_aq.c
461
#define TPS_DATA_TC_ARB_MODE __BIT(0)
sys/dev/pci/if_aq.c
478
#define TPO_HWCSUM_IP4CSUM_EN __BIT(1)
sys/dev/pci/if_aq.c
479
#define TPO_HWCSUM_L4CSUM_EN __BIT(0) /* TCP/UDP/SCTP */
sys/dev/pci/if_aq.c
490
#define TPB_TX_BUF_EN __BIT(0)
sys/dev/pci/if_aq.c
491
#define TPB_TX_BUF_SCP_INS_EN __BIT(2)
sys/dev/pci/if_aq.c
492
#define TPB_TX_BUF_CLK_GATE_EN __BIT(5)
sys/dev/pci/if_aq.c
493
#define TPB_TX_BUF_TC_MODE __BIT(8)
sys/dev/pci/if_aq.c
494
#define TPB_TX_BUF_TC_Q_RAND_MAP_EN __BIT(9) /* AQ2 */
sys/dev/pci/if_aq.c
505
#define TX_DMA_INT_DESC_WRWB_EN __BIT(1)
sys/dev/pci/if_aq.c
506
#define TX_DMA_INT_DESC_MODERATE_EN __BIT(4)
sys/dev/pci/if_aq.c
5061
imask |= __BIT(sc->sc_tx_irq[i]);
sys/dev/pci/if_aq.c
5062
imask |= __BIT(sc->sc_rx_irq[i]);
sys/dev/pci/if_aq.c
5067
imask |= __BIT(sc->sc_linkstat_irq);
sys/dev/pci/if_aq.c
5083
if (status & __BIT(sc->sc_linkstat_irq)) {
sys/dev/pci/if_aq.c
5091
if (status & __BIT(sc->sc_rx_irq[0])) {
sys/dev/pci/if_aq.c
5095
if (status & __BIT(sc->sc_tx_irq[0])) {
sys/dev/pci/if_aq.c
5119
if ((status & (__BIT(txirq) | __BIT(rxirq))) == 0) {
sys/dev/pci/if_aq.c
513
#define TX_DMA_DESC_EN __BIT(31)
sys/dev/pci/if_aq.c
5138
if (status & __BIT(sc->sc_linkstat_irq)) {
sys/dev/pci/if_aq.c
5144
__BIT(sc->sc_linkstat_irq));
sys/dev/pci/if_aq.c
523
#define TDM_DCAD_CPUID_EN __BIT(31)
sys/dev/pci/if_aq.c
526
#define TDM_DCA_EN __BIT(31)
sys/dev/pci/if_aq.c
531
#define TX_INTR_MODERATION_CTL_EN __BIT(1)
sys/dev/pci/if_aq.c
540
#define AQ2_MIF_HOST_FINISHED_STATUS_ACK __BIT(0)
sys/dev/pci/if_aq.c
543
#define AQ2_MCP_HOST_REQ_INT_READY __BIT(0)
sys/dev/pci/if_aq.c
5462
AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, __BIT(sc->sc_tx_irq[ringidx]));
sys/dev/pci/if_aq.c
548
#define AQ2_PHI_EXT_TAG_ENABLE __BIT(5)
sys/dev/pci/if_aq.c
551
#define AQ2_MIF_BOOT_HOST_DATA_LOADED __BIT(16)
sys/dev/pci/if_aq.c
552
#define AQ2_MIF_BOOT_BOOT_STARTED __BIT(24)
sys/dev/pci/if_aq.c
553
#define AQ2_MIF_BOOT_CRASH_INIT __BIT(27)
sys/dev/pci/if_aq.c
554
#define AQ2_MIF_BOOT_BOOT_CODE_FAILED __BIT(28)
sys/dev/pci/if_aq.c
555
#define AQ2_MIF_BOOT_FW_INIT_FAILED __BIT(29)
sys/dev/pci/if_aq.c
556
#define AQ2_MIF_BOOT_FW_INIT_COMP_SUCCESS __BIT(31)
sys/dev/pci/if_aq.c
560
#define AQ2_ART_ACTION_RSS_MASK __BIT(7)
sys/dev/pci/if_aq.c
562
#define AQ2_ART_ACTION_ENABLE_MASK __BIT(0)
sys/dev/pci/if_aq.c
5682
AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, __BIT(sc->sc_rx_irq[ringidx]));
sys/dev/pci/if_aq.c
579
#define AQ2_RPF_TAG_UNTAG_MASK __BIT(14)
sys/dev/pci/if_aq.c
582
#define AQ2_RPF_TAG_ALLMC_MASK __BIT(6)
sys/dev/pci/if_aq.c
597
#define AQ2_RPF_NEW_CTRL_ENABLE __BIT(11)
sys/dev/pci/if_aq.c
603
#define AQ2_RPF_REDIR2_INDEX __BIT(12)
sys/dev/pci/if_aq.c
606
#define AQ2_RPF_REDIR2_HASHTYPE_IP __BIT(0)
sys/dev/pci/if_aq.c
607
#define AQ2_RPF_REDIR2_HASHTYPE_TCP4 __BIT(1)
sys/dev/pci/if_aq.c
608
#define AQ2_RPF_REDIR2_HASHTYPE_UDP4 __BIT(2)
sys/dev/pci/if_aq.c
609
#define AQ2_RPF_REDIR2_HASHTYPE_IP6 __BIT(3)
sys/dev/pci/if_aq.c
610
#define AQ2_RPF_REDIR2_HASHTYPE_TCP6 __BIT(4)
sys/dev/pci/if_aq.c
611
#define AQ2_RPF_REDIR2_HASHTYPE_UDP6 __BIT(5)
sys/dev/pci/if_aq.c
612
#define AQ2_RPF_REDIR2_HASHTYPE_IP6EX __BIT(6)
sys/dev/pci/if_aq.c
613
#define AQ2_RPF_REDIR2_HASHTYPE_TCP6EX __BIT(7)
sys/dev/pci/if_aq.c
614
#define AQ2_RPF_REDIR2_HASHTYPE_UDP6EX __BIT(8)
sys/dev/pci/if_aq.c
627
#define AQ2_RPF_L3_V6_V4_SELECT_EN __BIT(23)
sys/dev/pci/if_aq.c
642
#define AQ2_TX_INTR_MODERATION_CTL_EN __BIT(1)
sys/dev/pci/if_aq.c
650
#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_PROMISCUOUS_MODE __BIT(13)
sys/dev/pci/if_aq.c
651
#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_FRAME_PADDING_REMOVAL_RX __BIT(12)
sys/dev/pci/if_aq.c
652
#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_CRC_FORWARDING __BIT(11)
sys/dev/pci/if_aq.c
653
#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_TX_PADDING __BIT(10)
sys/dev/pci/if_aq.c
654
#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_CONTROL_FRAME __BIT(9)
sys/dev/pci/if_aq.c
655
#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_DISCARD_ERROR_FRAME __BIT(8)
sys/dev/pci/if_aq.c
656
#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_DISABLE_LENGTH_CHECK __BIT(7)
sys/dev/pci/if_aq.c
657
#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_FLOW_CONTROL_MODE __BIT(6)
sys/dev/pci/if_aq.c
658
#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_DISCARD_SHORT_FRAMES __BIT(5)
sys/dev/pci/if_aq.c
659
#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_DISABLE_CRC_CORRUPTION __BIT(4)
sys/dev/pci/if_aq.c
669
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_DOWNSHIFT __BIT(27)
sys/dev/pci/if_aq.c
670
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_TX __BIT(25)
sys/dev/pci/if_aq.c
671
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_RX __BIT(24)
sys/dev/pci/if_aq.c
672
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_10G __BIT(20)
sys/dev/pci/if_aq.c
673
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_5G __BIT(19)
sys/dev/pci/if_aq.c
674
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_2G5 __BIT(18)
sys/dev/pci/if_aq.c
675
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_1G __BIT(17)
sys/dev/pci/if_aq.c
676
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_100M __BIT(16)
sys/dev/pci/if_aq.c
677
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10G __BIT(15)
sys/dev/pci/if_aq.c
678
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N5G __BIT(14)
sys/dev/pci/if_aq.c
679
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_5G __BIT(13)
sys/dev/pci/if_aq.c
680
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N2G5 __BIT(12)
sys/dev/pci/if_aq.c
681
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_2G5 __BIT(11)
sys/dev/pci/if_aq.c
682
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G __BIT(10)
sys/dev/pci/if_aq.c
683
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M __BIT(9)
sys/dev/pci/if_aq.c
684
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M __BIT(8)
sys/dev/pci/if_aq.c
685
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G_HD __BIT(7)
sys/dev/pci/if_aq.c
686
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M_HD __BIT(6)
sys/dev/pci/if_aq.c
687
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M_HD __BIT(5)
sys/dev/pci/if_aq.c
688
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EXTERNAL_LOOPBACK __BIT(4)
sys/dev/pci/if_aq.c
689
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_INTERNAL_LOOPBACK __BIT(3)
sys/dev/pci/if_aq.c
690
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_MINIMAL_LINK_SPEED __BIT(2)
sys/dev/pci/if_aq.c
691
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_LINK_RENEGOTIATE __BIT(1)
sys/dev/pci/if_aq.c
692
#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_LINK_UP __BIT(0)
sys/dev/pci/if_aq.c
698
#define AQ2_FW_INTERFACE_IN_THERMAL_SHUTDOWN_WARNING_ENABLE __BIT(1)
sys/dev/pci/if_aq.c
699
#define AQ2_FW_INTERFACE_IN_THERMAL_SHUTDOWN_ENABLE __BIT(0)
sys/dev/pci/if_aq.c
708
#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_QUEUE_OR_TC __BIT(23)
sys/dev/pci/if_aq.c
710
#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_ACCEPT __BIT(16)
sys/dev/pci/if_aq.c
711
#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_QUEUE_OR_TC __BIT(15)
sys/dev/pci/if_aq.c
713
#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_ACCEPT __BIT(8)
sys/dev/pci/if_aq.c
714
#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_QUEUE_OR_TC __BIT(7)
sys/dev/pci/if_aq.c
716
#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_MCAST __BIT(1)
sys/dev/pci/if_aq.c
717
#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_ALL __BIT(0)
sys/dev/pci/if_aq.c
734
#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_DUPLEX __BIT(11)
sys/dev/pci/if_aq.c
735
#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_EEE __BIT(10)
sys/dev/pci/if_aq.c
736
#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_PAUSE_RX __BIT(9)
sys/dev/pci/if_aq.c
737
#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_PAUSE_TX __BIT(8)
sys/dev/pci/if_aq.c
753
#define HEALTH_MONITOR_DATA1_READY __BIT(0)
sys/dev/pci/if_aq.c
754
#define HEALTH_MONITOR_DATA1_FAULT __BIT(1)
sys/dev/pci/if_aq.c
755
#define HEALTH_MONITOR_DATA1_FLASHLESS_FINISHED __BIT(2)
sys/dev/pci/if_aq.c
756
#define HEALTH_MONITOR_DATA1_HOT_WARNING __BIT(2)
sys/dev/pci/if_aq.c
771
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_PAUSE_TX __BIT(25)
sys/dev/pci/if_aq.c
772
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_PAUSE_RX __BIT(24)
sys/dev/pci/if_aq.c
773
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_EEE_10G __BIT(23)
sys/dev/pci/if_aq.c
774
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_EEE_5G __BIT(21)
sys/dev/pci/if_aq.c
775
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_EEE_2G5 __BIT(19)
sys/dev/pci/if_aq.c
776
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_EEE_1G __BIT(18)
sys/dev/pci/if_aq.c
777
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_EEE_100M __BIT(17)
sys/dev/pci/if_aq.c
778
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_10G __BIT(15)
sys/dev/pci/if_aq.c
779
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_N5G __BIT(14)
sys/dev/pci/if_aq.c
780
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_5G __BIT(13)
sys/dev/pci/if_aq.c
781
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_N2G5 __BIT(12)
sys/dev/pci/if_aq.c
782
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_2G5 __BIT(11)
sys/dev/pci/if_aq.c
783
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_1G __BIT(10)
sys/dev/pci/if_aq.c
784
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_100M __BIT(9)
sys/dev/pci/if_aq.c
785
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_10M __BIT(8)
sys/dev/pci/if_aq.c
786
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_1G_HD __BIT(7)
sys/dev/pci/if_aq.c
787
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_100M_HD __BIT(6)
sys/dev/pci/if_aq.c
788
#define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_10M_HD __BIT(5)
sys/dev/pci/if_aq.c
874
#define FW1X_CTRL_10G __BIT(0)
sys/dev/pci/if_aq.c
875
#define FW1X_CTRL_5G __BIT(1)
sys/dev/pci/if_aq.c
876
#define FW1X_CTRL_5GSR __BIT(2)
sys/dev/pci/if_aq.c
877
#define FW1X_CTRL_2G5 __BIT(3)
sys/dev/pci/if_aq.c
878
#define FW1X_CTRL_1G __BIT(4)
sys/dev/pci/if_aq.c
879
#define FW1X_CTRL_100M __BIT(5)
sys/dev/pci/if_aq.c
881
#define FW2X_CTRL_10BASET_HD __BIT(0)
sys/dev/pci/if_aq.c
882
#define FW2X_CTRL_10BASET_FD __BIT(1)
sys/dev/pci/if_aq.c
883
#define FW2X_CTRL_100BASETX_HD __BIT(2)
sys/dev/pci/if_aq.c
884
#define FW2X_CTRL_100BASET4_HD __BIT(3)
sys/dev/pci/if_aq.c
885
#define FW2X_CTRL_100BASET2_HD __BIT(4)
sys/dev/pci/if_aq.c
886
#define FW2X_CTRL_100BASETX_FD __BIT(5)
sys/dev/pci/if_aq.c
887
#define FW2X_CTRL_100BASET2_FD __BIT(6)
sys/dev/pci/if_aq.c
888
#define FW2X_CTRL_1000BASET_HD __BIT(7)
sys/dev/pci/if_aq.c
889
#define FW2X_CTRL_1000BASET_FD __BIT(8)
sys/dev/pci/if_aq.c
890
#define FW2X_CTRL_2P5GBASET_FD __BIT(9)
sys/dev/pci/if_aq.c
891
#define FW2X_CTRL_5GBASET_FD __BIT(10)
sys/dev/pci/if_aq.c
892
#define FW2X_CTRL_10GBASET_FD __BIT(11)
sys/dev/pci/if_aq.c
893
#define FW2X_CTRL_RESERVED1 __BIT(32)
sys/dev/pci/if_aq.c
894
#define FW2X_CTRL_10BASET_EEE __BIT(33)
sys/dev/pci/if_aq.c
895
#define FW2X_CTRL_RESERVED2 __BIT(34)
sys/dev/pci/if_aq.c
896
#define FW2X_CTRL_PAUSE __BIT(35)
sys/dev/pci/if_aq.c
897
#define FW2X_CTRL_ASYMMETRIC_PAUSE __BIT(36)
sys/dev/pci/if_aq.c
898
#define FW2X_CTRL_100BASETX_EEE __BIT(37)
sys/dev/pci/if_aq.c
899
#define FW2X_CTRL_RESERVED3 __BIT(38)
sys/dev/pci/if_aq.c
900
#define FW2X_CTRL_RESERVED4 __BIT(39)
sys/dev/pci/if_aq.c
901
#define FW2X_CTRL_1000BASET_FD_EEE __BIT(40)
sys/dev/pci/if_aq.c
902
#define FW2X_CTRL_2P5GBASET_FD_EEE __BIT(41)
sys/dev/pci/if_aq.c
903
#define FW2X_CTRL_5GBASET_FD_EEE __BIT(42)
sys/dev/pci/if_aq.c
904
#define FW2X_CTRL_10GBASET_FD_EEE __BIT(43)
sys/dev/pci/if_aq.c
905
#define FW2X_CTRL_RESERVED5 __BIT(44)
sys/dev/pci/if_aq.c
906
#define FW2X_CTRL_RESERVED6 __BIT(45)
sys/dev/pci/if_aq.c
907
#define FW2X_CTRL_RESERVED7 __BIT(46)
sys/dev/pci/if_aq.c
908
#define FW2X_CTRL_RESERVED8 __BIT(47)
sys/dev/pci/if_aq.c
909
#define FW2X_CTRL_RESERVED9 __BIT(48)
sys/dev/pci/if_aq.c
910
#define FW2X_CTRL_CABLE_DIAG __BIT(49)
sys/dev/pci/if_aq.c
911
#define FW2X_CTRL_TEMPERATURE __BIT(50)
sys/dev/pci/if_aq.c
912
#define FW2X_CTRL_DOWNSHIFT __BIT(51)
sys/dev/pci/if_aq.c
913
#define FW2X_CTRL_PTP_AVB_EN __BIT(52)
sys/dev/pci/if_aq.c
914
#define FW2X_CTRL_MEDIA_DETECT __BIT(53)
sys/dev/pci/if_aq.c
915
#define FW2X_CTRL_LINK_DROP __BIT(54)
sys/dev/pci/if_aq.c
916
#define FW2X_CTRL_SLEEP_PROXY __BIT(55)
sys/dev/pci/if_aq.c
917
#define FW2X_CTRL_WOL __BIT(56)
sys/dev/pci/if_aq.c
918
#define FW2X_CTRL_MAC_STOP __BIT(57)
sys/dev/pci/if_aq.c
919
#define FW2X_CTRL_EXT_LOOPBACK __BIT(58)
sys/dev/pci/if_aq.c
920
#define FW2X_CTRL_INT_LOOPBACK __BIT(59)
sys/dev/pci/if_aq.c
921
#define FW2X_CTRL_EFUSE_AGENT __BIT(60)
sys/dev/pci/if_aq.c
922
#define FW2X_CTRL_WOL_TIMER __BIT(61)
sys/dev/pci/if_aq.c
923
#define FW2X_CTRL_STATISTICS __BIT(62)
sys/dev/pci/if_aq.c
924
#define FW2X_CTRL_TRANSACTION_ID __BIT(63)
sys/dev/pci/if_bgevar.h
307
#define BGE_MFW_ON_RXCPU __BIT(0)
sys/dev/pci/if_bgevar.h
308
#define BGE_MFW_ON_APE __BIT(1)
sys/dev/pci/if_bgevar.h
309
#define BGE_MFW_TYPE_NCSI __BIT(2)
sys/dev/pci/if_bgevar.h
310
#define BGE_MFW_TYPE_DASH __BIT(3)
sys/dev/pci/if_bgevar.h
337
#define BGE_STS_LINK __BIT(0) /* MAC link status */
sys/dev/pci/if_bgevar.h
338
#define BGE_STS_LINK_EVT __BIT(1) /* pending link event */
sys/dev/pci/if_bgevar.h
339
#define BGE_STS_AUTOPOLL __BIT(2) /* PHY auto-polling */
sys/dev/pci/if_bnx.c
5630
hashes[(h & 0xE0) >> 5] |= __BIT(h & 0x1F);
sys/dev/pci/if_enavar.h
167
#define ENA_FLAG_BITMASK(bit) (~(uint32_t)__BIT(bit))
sys/dev/pci/if_enavar.h
169
#define ENA_FLAG_ISSET(bit, adapter) ((adapter)->flags & __BIT(bit))
sys/dev/pci/if_enavar.h
171
atomic_or_32(&(adapter)->flags, __BIT(bit))
sys/dev/pci/if_etreg.h
239
#define ET_MAC_CFG1_SOFT_RST __BIT(31)
sys/dev/pci/if_iavf.c
4662
vec[num_vec].rxq_map = htole16(__BIT(rxr->rxr_qid));
sys/dev/pci/if_iavf.c
4663
vec[num_vec].txq_map = htole16(__BIT(txr->txr_qid));
sys/dev/pci/if_iwm.c
3175
CTASSERT(__BIT(IWM_BLOCK_2_EXP_SIZE) == IWM_PAGING_BLOCK_SIZE);
sys/dev/pci/if_iwm.c
936
if (!ISSET(bits, __BIT(i)))
sys/dev/pci/if_iwm.c
959
if (!ISSET(bits, __BIT(i)))
sys/dev/pci/if_iwmvar.h
301
#define IWM_FLAG_USE_ICT __BIT(0)
sys/dev/pci/if_iwmvar.h
302
#define IWM_FLAG_HW_INITED __BIT(1)
sys/dev/pci/if_iwmvar.h
303
#define IWM_FLAG_STOPPED __BIT(2)
sys/dev/pci/if_iwmvar.h
304
#define IWM_FLAG_RFKILL __BIT(3)
sys/dev/pci/if_iwmvar.h
305
#define IWM_FLAG_SCANNING __BIT(4)
sys/dev/pci/if_iwmvar.h
306
#define IWM_FLAG_ATTACHED __BIT(5)
sys/dev/pci/if_iwmvar.h
307
#define IWM_FLAG_FW_LOADED __BIT(6)
sys/dev/pci/if_iwmvar.h
308
#define IWM_FLAG_TE_ACTIVE __BIT(7)
sys/dev/pci/if_iwmvar.h
309
#define IWM_FLAG_MAC_ACTIVE __BIT(8)
sys/dev/pci/if_iwmvar.h
310
#define IWM_FLAG_BINDING_ACTIVE __BIT(9)
sys/dev/pci/if_iwmvar.h
311
#define IWM_FLAG_STA_ACTIVE __BIT(10)
sys/dev/pci/if_iwmvar.h
312
#define IWM_FLAG_BGSCAN __BIT(11)
sys/dev/pci/if_iwmvar.h
313
#define IWM_FLAG_TXFLUSH __BIT(12)
sys/dev/pci/if_ixl.c
635
#define IXL_SC_AQ_FLAG_RXCTL __BIT(0)
sys/dev/pci/if_ixl.c
636
#define IXL_SC_AQ_FLAG_NVMLOCK __BIT(1)
sys/dev/pci/if_ixl.c
637
#define IXL_SC_AQ_FLAG_NVMREAD __BIT(2)
sys/dev/pci/if_ixl.c
638
#define IXL_SC_AQ_FLAG_RSS __BIT(3)
sys/dev/pci/if_ixl.c
7013
__BIT(I40E_GLNVM_SRCTL_START_SHIFT);
sys/dev/pci/if_ixl.c
721
IXL_LINK_FLAG_WAITDONE = __BIT(0),
sys/dev/pci/if_rtwnreg.h
170
#define RTWN_FLAG_FW_LOADED __BIT(0)
sys/dev/pci/if_rtwnreg.h
171
#define RTWN_FLAG_CCK_HIPWR __BIT(1)
sys/dev/pci/if_rtwnreg.h
174
#define RTWN_CHIP_88C __BIT(0)
sys/dev/pci/if_rtwnreg.h
175
#define RTWN_CHIP_92C __BIT(1)
sys/dev/pci/if_rtwnreg.h
176
#define RTWN_CHIP_92C_1T2R __BIT(2)
sys/dev/pci/if_rtwnreg.h
177
#define RTWN_CHIP_UMC __BIT(3)
sys/dev/pci/if_rtwnreg.h
178
#define RTWN_CHIP_UMC_A_CUT __BIT(4)
sys/dev/pci/if_rtwnreg.h
179
#define RTWN_CHIP_UMC_B_CUT __BIT(5)
sys/dev/pci/if_skreg.h
1293
#define SK_Y2_ASF_HCU_CSSR_ARB_RST __BIT(9)
sys/dev/pci/if_skreg.h
1294
#define SK_Y2_ASF_HCU_CSSR_CPU_RST_MODE __BIT(8)
sys/dev/pci/if_skreg.h
1562
#define SK_Y2_REG4_FORCE_ASPM_REQUEST __BIT(15)
sys/dev/pci/if_skreg.h
1563
#define SK_Y2_REG4_ASPM_GPHY_LINK_DOWN __BIT(14)
sys/dev/pci/if_skreg.h
1564
#define SK_Y2_REG4_ASPM_INT_FIFO_EMPTY __BIT(13)
sys/dev/pci/if_skreg.h
1565
#define SK_Y2_REG4_ASPM_CLKRUN_REQUEST __BIT(12)
sys/dev/pci/if_skreg.h
1566
#define SK_Y2_REG4_ASPM_FORCE_CLKREQ_ENA __BIT(4)
sys/dev/pci/if_skreg.h
1567
#define SK_Y2_REG4_ASPM_CLKREQ_PAD __BIT(3)
sys/dev/pci/if_skreg.h
1568
#define SK_Y2_REG4_ASPM_A1_MODE_SELECT __BIT(2)
sys/dev/pci/if_skreg.h
1569
#define SK_Y2_REG4_CLK_GATE_PEX_UNIT_ENA __BIT(1)
sys/dev/pci/if_skreg.h
1570
#define SK_Y2_REG4_CLK_GATE_ROOT_COR_ENA __BIT(0)
sys/dev/pci/if_skreg.h
207
#define SK_CSR_WOL_OFF __BIT(14)
sys/dev/pci/if_skreg.h
208
#define SK_CSR_WOL_ON __BIT(15)
sys/dev/pci/if_vioif.c
100
#define VIRTIO_NET_F_CTRL_RX_EXTRA __BIT(20)
sys/dev/pci/if_vioif.c
101
#define VIRTIO_NET_F_GUEST_ANNOUNCE __BIT(21)
sys/dev/pci/if_vioif.c
102
#define VIRTIO_NET_F_MQ __BIT(22)
sys/dev/pci/if_vioif.c
103
#define VIRTIO_NET_F_CTRL_MAC_ADDR __BIT(23)
sys/dev/pci/if_vioif.c
83
#define VIRTIO_NET_F_CSUM __BIT(0)
sys/dev/pci/if_vioif.c
84
#define VIRTIO_NET_F_GUEST_CSUM __BIT(1)
sys/dev/pci/if_vioif.c
85
#define VIRTIO_NET_F_MAC __BIT(5)
sys/dev/pci/if_vioif.c
86
#define VIRTIO_NET_F_GSO __BIT(6)
sys/dev/pci/if_vioif.c
87
#define VIRTIO_NET_F_GUEST_TSO4 __BIT(7)
sys/dev/pci/if_vioif.c
88
#define VIRTIO_NET_F_GUEST_TSO6 __BIT(8)
sys/dev/pci/if_vioif.c
89
#define VIRTIO_NET_F_GUEST_ECN __BIT(9)
sys/dev/pci/if_vioif.c
90
#define VIRTIO_NET_F_GUEST_UFO __BIT(10)
sys/dev/pci/if_vioif.c
91
#define VIRTIO_NET_F_HOST_TSO4 __BIT(11)
sys/dev/pci/if_vioif.c
92
#define VIRTIO_NET_F_HOST_TSO6 __BIT(12)
sys/dev/pci/if_vioif.c
93
#define VIRTIO_NET_F_HOST_ECN __BIT(13)
sys/dev/pci/if_vioif.c
94
#define VIRTIO_NET_F_HOST_UFO __BIT(14)
sys/dev/pci/if_vioif.c
95
#define VIRTIO_NET_F_MRG_RXBUF __BIT(15)
sys/dev/pci/if_vioif.c
96
#define VIRTIO_NET_F_STATUS __BIT(16)
sys/dev/pci/if_vioif.c
97
#define VIRTIO_NET_F_CTRL_VQ __BIT(17)
sys/dev/pci/if_vioif.c
98
#define VIRTIO_NET_F_CTRL_RX __BIT(18)
sys/dev/pci/if_vioif.c
99
#define VIRTIO_NET_F_CTRL_VLAN __BIT(19)
sys/dev/pci/if_wm.c
12045
for (i = __BIT(nbits - 1); i != 0; i >>= 1) {
sys/dev/pci/if_wm.c
151
#define WM_DEBUG_LINK __BIT(0)
sys/dev/pci/if_wm.c
152
#define WM_DEBUG_TX __BIT(1)
sys/dev/pci/if_wm.c
153
#define WM_DEBUG_RX __BIT(2)
sys/dev/pci/if_wm.c
154
#define WM_DEBUG_GMII __BIT(3)
sys/dev/pci/if_wm.c
155
#define WM_DEBUG_MANAGE __BIT(4)
sys/dev/pci/if_wm.c
156
#define WM_DEBUG_NVM __BIT(5)
sys/dev/pci/if_wm.c
157
#define WM_DEBUG_INIT __BIT(6)
sys/dev/pci/if_wm.c
158
#define WM_DEBUG_LOCK __BIT(7)
sys/dev/pci/if_wm.c
18092
value = howmany(value, __BIT(5));
sys/dev/pci/if_wm.c
3891
*hang |= __BIT(wmq->wmq_id);
sys/dev/pci/if_wm.c
5136
tarc1 |= __BIT(22); /* TARC1 bits 22 */
sys/dev/pci/if_wm.c
5140
tarc1 &= ~__BIT(28);
sys/dev/pci/if_wm.c
5142
tarc1 |= __BIT(28);
sys/dev/pci/if_wm.c
5158
tarc0 |= __BIT(26); /* TARC0 bit 26 */
sys/dev/pci/if_wm.c
5162
reg &= ~__BIT(23); /* Clear bit 23 */
sys/dev/pci/if_wm.c
5163
reg |= __BIT(22); /* Set bit 22 */
sys/dev/pci/if_wm.c
5167
sc->sc_ctrl &= ~__BIT(29); /* Clear bit 29 */
sys/dev/pci/if_wm.c
5189
reg |= __BIT(22);
sys/dev/pci/if_wm.c
5201
reg |= __BIT(0);
sys/dev/pci/if_wm.c
5209
tarc0 &= ~__BIT(20); /* Clear bits 20 */
sys/dev/pci/if_wm.c
5214
tarc1 &= ~__BIT(28);
sys/dev/pci/if_wm.c
5216
tarc1 |= __BIT(28);
sys/dev/pci/if_wm.c
5233
tarc0 |= __BIT(29);
sys/dev/pci/if_wm.c
5240
tarc0 &= ~__BIT(28);
sys/dev/pci/if_wm.c
5247
reg |= __BIT(22); /* Set bit 22 */
sys/dev/pci/if_wm.c
5260
tarc1 &= ~__BIT(28);
sys/dev/pci/if_wm.c
5262
tarc1 |= __BIT(28);
sys/dev/pci/if_wm.c
5263
tarc1 |= __BIT(24) | __BIT(26) | __BIT(30);
sys/dev/pci/if_wm.c
5269
reg &= ~__BIT(31);
sys/dev/pci/if_wmreg.h
104
#define WRX_ST_DD __BIT(0) /* descriptor done */
sys/dev/pci/if_wmreg.h
105
#define WRX_ST_EOP __BIT(1) /* end of packet */
sys/dev/pci/if_wmreg.h
106
#define WRX_ST_IXSM __BIT(2) /* ignore checksum indication */
sys/dev/pci/if_wmreg.h
107
#define WRX_ST_VP __BIT(3) /* VLAN packet */
sys/dev/pci/if_wmreg.h
1078
#define GPIE_NSICR __BIT(0) /* Non Selective Interrupt Clear */
sys/dev/pci/if_wmreg.h
1079
#define GPIE_MULTI_MSIX __BIT(4) /* Multiple MSIX */
sys/dev/pci/if_wmreg.h
108
#define WRX_ST_BPDU __BIT(4) /* ??? */
sys/dev/pci/if_wmreg.h
1080
#define GPIE_EIAME __BIT(30) /* Extended Interrupt Auto Mask Ena. */
sys/dev/pci/if_wmreg.h
1081
#define GPIE_PBA __BIT(31) /* PBA support */
sys/dev/pci/if_wmreg.h
109
#define WRX_ST_TCPCS __BIT(5) /* TCP checksum performed */
sys/dev/pci/if_wmreg.h
1093
#define EITR_RX_QUEUE(x) __BIT(0+(x)) /* Rx Queue x Interrupt x=[0-3] */
sys/dev/pci/if_wmreg.h
1094
#define EITR_TX_QUEUE(x) __BIT(8+(x)) /* Tx Queue x Interrupt x=[0-3] */
sys/dev/pci/if_wmreg.h
110
#define WRX_ST_IPCS __BIT(6) /* IP checksum performed */
sys/dev/pci/if_wmreg.h
1101
#define EITR_CNT_INGR __BIT(31) /* does not overwrite counter */
sys/dev/pci/if_wmreg.h
111
#define WRX_ST_PIF __BIT(7) /* passed in-exact filter */
sys/dev/pci/if_wmreg.h
1116
#define TXDMAC_DPP __BIT(0) /* disable packet prefetch */
sys/dev/pci/if_wmreg.h
1133
#define TXDCTL_COUNT_DESC __BIT(22) /* Enable the counting of desc.
sys/dev/pci/if_wmreg.h
114
#define WRX_ER_CE __BIT(0) /* CRC error */
sys/dev/pci/if_wmreg.h
115
#define WRX_ER_SE __BIT(1) /* symbol error */
sys/dev/pci/if_wmreg.h
116
#define WRX_ER_SEQ __BIT(2) /* sequence error */
sys/dev/pci/if_wmreg.h
117
#define WRX_ER_ICE __BIT(3) /* ??? */
sys/dev/pci/if_wmreg.h
118
#define WRX_ER_CXE __BIT(4) /* carrier extension error */
sys/dev/pci/if_wmreg.h
119
#define WRX_ER_TCPE __BIT(5) /* TCP checksum error */
sys/dev/pci/if_wmreg.h
120
#define WRX_ER_IPE __BIT(6) /* IP checksum error */
sys/dev/pci/if_wmreg.h
121
#define WRX_ER_RXE __BIT(7) /* Rx data error */
sys/dev/pci/if_wmreg.h
125
#define WRX_VLAN_CFI __BIT(12) /* Canonical Form Indicator */
sys/dev/pci/if_wmreg.h
1250
#define PCS_CFG_PCS_EN __BIT(3)
sys/dev/pci/if_wmreg.h
1253
#define PCS_LCTL_FLV_LINK_UP __BIT(0) /* Forced Link Value */
sys/dev/pci/if_wmreg.h
1256
#define PCS_LCTL_FSV_100 __BIT(1) /* 100Mbps */
sys/dev/pci/if_wmreg.h
1257
#define PCS_LCTL_FSV_1000 __BIT(2) /* 1Gpbs */
sys/dev/pci/if_wmreg.h
1258
#define PCS_LCTL_FDV_FULL __BIT(3) /* Force Duplex Value */
sys/dev/pci/if_wmreg.h
1259
#define PCS_LCTL_FSD __BIT(4) /* Force Speed and Duplex */
sys/dev/pci/if_wmreg.h
1260
#define PCS_LCTL_FORCE_LINK __BIT(5) /* Force Link */
sys/dev/pci/if_wmreg.h
1261
#define PCS_LCTL_LINK_LATCH_LOW __BIT(6) /* Link Latch Low */
sys/dev/pci/if_wmreg.h
1262
#define PCS_LCTL_FORCE_FC __BIT(7) /* Force Flow Control */
sys/dev/pci/if_wmreg.h
1263
#define PCS_LCTL_AN_ENABLE __BIT(16) /* AN enable */
sys/dev/pci/if_wmreg.h
1264
#define PCS_LCTL_AN_RESTART __BIT(17) /* AN restart */
sys/dev/pci/if_wmreg.h
1265
#define PCS_LCTL_AN_TIMEOUT __BIT(18) /* AN Timeout Enable */
sys/dev/pci/if_wmreg.h
1266
#define PCS_LCTL_AN_SGMII_BYP __BIT(19) /* AN SGMII Bypass */
sys/dev/pci/if_wmreg.h
1267
#define PCS_LCTL_AN_SGMII_TRIG __BIT(20) /* AN SGMII Trigger */
sys/dev/pci/if_wmreg.h
1268
#define PCS_LCTL_FAST_LINKTIMER __BIT(24) /* Fast Link Timer */
sys/dev/pci/if_wmreg.h
1269
#define PCS_LCTL_LINK_OK_FIX_EN __BIT(25) /* Link OK Fix Enable */
sys/dev/pci/if_wmreg.h
1272
#define PCS_LSTS_LINKOK __BIT(0)
sys/dev/pci/if_wmreg.h
1277
#define PCS_LSTS_FDX __BIT(3)
sys/dev/pci/if_wmreg.h
1278
#define PCS_LSTS_AN_COMP __BIT(16)
sys/dev/pci/if_wmreg.h
1287
#define RXCSUM_IPOFL __BIT(8) /* IP checksum offload */
sys/dev/pci/if_wmreg.h
1288
#define RXCSUM_TUOFL __BIT(9) /* TCP/UDP checksum offload */
sys/dev/pci/if_wmreg.h
1289
#define RXCSUM_IPV6OFL __BIT(10) /* IPv6 checksum offload */
sys/dev/pci/if_wmreg.h
1290
#define RXCSUM_CRCOFL __BIT(11) /* SCTP CRC32 checksum offload */
sys/dev/pci/if_wmreg.h
1291
#define RXCSUM_IPPCSE __BIT(12) /* IP payload checksum enable */
sys/dev/pci/if_wmreg.h
1292
#define RXCSUM_PCSD __BIT(13) /* packet checksum disabled */
sys/dev/pci/if_wmreg.h
1297
#define WMREG_RFCTL_NFSWDIS __BIT(6) /* NFS Write Disable */
sys/dev/pci/if_wmreg.h
1298
#define WMREG_RFCTL_NFSRDIS __BIT(7) /* NFS Read Disable */
sys/dev/pci/if_wmreg.h
1299
#define WMREG_RFCTL_ACKDIS __BIT(12) /* ACK Accelerate Disable */
sys/dev/pci/if_wmreg.h
1300
#define WMREG_RFCTL_ACKD_DIS __BIT(13) /* ACK data Disable */
sys/dev/pci/if_wmreg.h
1301
#define WMREG_RFCTL_EXSTEN __BIT(15) /* Extended status Enable. 82574 only. */
sys/dev/pci/if_wmreg.h
1302
#define WMREG_RFCTL_IPV6EXDIS __BIT(16) /* IPv6 Extension Header Disable */
sys/dev/pci/if_wmreg.h
1303
#define WMREG_RFCTL_NEWIPV6EXDIS __BIT(17) /* New IPv6 Extension Header */
sys/dev/pci/if_wmreg.h
1313
#define WUFC_LNKC __BIT(0) /* Link Status Change Wakeup Enable */
sys/dev/pci/if_wmreg.h
1314
#define WUFC_MAG __BIT(1) /* Magic Packet Wakeup Enable */
sys/dev/pci/if_wmreg.h
1315
#define WUFC_EX __BIT(2) /* Directed Exact Wakeup Enable */
sys/dev/pci/if_wmreg.h
1316
#define WUFC_MC __BIT(3) /* Directed Multicast Wakeup En */
sys/dev/pci/if_wmreg.h
1317
#define WUFC_BC __BIT(4) /* Broadcast Wakeup Enable */
sys/dev/pci/if_wmreg.h
1318
#define WUFC_ARPDIR __BIT(5) /* ARP Request Packet Wakeup En */
sys/dev/pci/if_wmreg.h
1319
#define WUFC_IPV4 __BIT(6) /* Directed IPv4 Packet Wakeup En */
sys/dev/pci/if_wmreg.h
1320
#define WUFC_IPV6 __BIT(7) /* Directed IPv6 Packet Wakeup En */
sys/dev/pci/if_wmreg.h
1321
#define WUFC_NS __BIT(9) /* NS Wakeup En */
sys/dev/pci/if_wmreg.h
1322
#define WUFC_NSDIR __BIT(10) /* NS Directed En */
sys/dev/pci/if_wmreg.h
1323
#define WUFC_ARP __BIT(11) /* ARP request En */
sys/dev/pci/if_wmreg.h
1324
#define WUFC_FLEX_HQ __BIT(14) /* Flex Filters Host Queueing En */
sys/dev/pci/if_wmreg.h
1325
#define WUFC_NOTCO __BIT(15) /* ? */
sys/dev/pci/if_wmreg.h
1328
#define WUFC_FW_RST_WK __BIT(31) /* Wake on Firmware Reset Assert En */
sys/dev/pci/if_wmreg.h
1332
#define WUS_MNG __BIT(8) /* Manageability event */
sys/dev/pci/if_wmreg.h
1343
#define MRQC_ENABLE_RSS_MQ_82574 __BIT(0) /* enable RSS for 82574 */
sys/dev/pci/if_wmreg.h
1344
#define MRQC_ENABLE_RSS_MQ __BIT(1) /* enable hardware max RSS without VMDq */
sys/dev/pci/if_wmreg.h
1352
#define MRQC_DEFQ_NOT_RSS_FLT __SHFTIN(__BIT(1), MRQC_DEFQ_MASK)
sys/dev/pci/if_wmreg.h
1364
#define MRQC_DEFQ_IGNORED1 __SHFTIN(__BIT(2), MRQC_DEFQ_MASK)
sys/dev/pci/if_wmreg.h
1366
#define MRQC_DEFQ_IGNORED2 __SHFTIN(__BIT(2)|__BIT(0), MRQC_DEFQ_MASK)
sys/dev/pci/if_wmreg.h
1370
#define MRQC_RSS_FIELD_IPV4_TCP __BIT(16)
sys/dev/pci/if_wmreg.h
1371
#define MRQC_RSS_FIELD_IPV4 __BIT(17)
sys/dev/pci/if_wmreg.h
1372
#define MRQC_RSS_FIELD_IPV6_TCP_EX __BIT(18)
sys/dev/pci/if_wmreg.h
1373
#define MRQC_RSS_FIELD_IPV6_EX __BIT(19)
sys/dev/pci/if_wmreg.h
1374
#define MRQC_RSS_FIELD_IPV6 __BIT(20)
sys/dev/pci/if_wmreg.h
1375
#define MRQC_RSS_FIELD_IPV6_TCP __BIT(21)
sys/dev/pci/if_wmreg.h
1376
#define MRQC_RSS_FIELD_IPV4_UDP __BIT(22)
sys/dev/pci/if_wmreg.h
1377
#define MRQC_RSS_FIELD_IPV6_UDP __BIT(23)
sys/dev/pci/if_wmreg.h
1378
#define MRQC_RSS_FIELD_IPV6_UDP_EX __BIT(24)
sys/dev/pci/if_wmreg.h
1386
#define RETA_ENT_QINDEX_MASK_82574 __BIT(7) /*queue index for 82574 */
sys/dev/pci/if_wmreg.h
1392
#define MANC_SMBUS_EN __BIT(0)
sys/dev/pci/if_wmreg.h
1393
#define MANC_ASF_EN __BIT(1)
sys/dev/pci/if_wmreg.h
1394
#define MANC_ARP_EN __BIT(13)
sys/dev/pci/if_wmreg.h
1395
#define MANC_RECV_TCO_RESET __BIT(16)
sys/dev/pci/if_wmreg.h
1396
#define MANC_RECV_TCO_EN __BIT(17)
sys/dev/pci/if_wmreg.h
1397
#define MANC_BLK_PHY_RST_ON_IDE __BIT(18)
sys/dev/pci/if_wmreg.h
1398
#define MANC_RECV_ALL __BIT(19)
sys/dev/pci/if_wmreg.h
1399
#define MANC_EN_MAC_ADDR_FILTER __BIT(20)
sys/dev/pci/if_wmreg.h
1400
#define MANC_EN_MNG2HOST __BIT(21)
sys/dev/pci/if_wmreg.h
1401
#define MANC_EN_BMC2OS __BIT(28)
sys/dev/pci/if_wmreg.h
1441
#define H2ME_ULP __BIT(11)
sys/dev/pci/if_wmreg.h
1442
#define H2ME_ENFORCE_SETTINGS __BIT(12)
sys/dev/pci/if_wmreg.h
1448
#define FWSM_RSPCIPHY __BIT(6) /* Reset PHY on PCI reset */
sys/dev/pci/if_wmreg.h
1450
#define FWSM_ULP_CFG_DONE __BIT(10)
sys/dev/pci/if_wmreg.h
1451
#define FWSM_FW_VALID __BIT(15) /* FW established a valid mode */
sys/dev/pci/if_wmreg.h
1468
#define FEXTNVM9_IOSFSB_CLKGATE_DIS __BIT(11)
sys/dev/pci/if_wmreg.h
1469
#define FEXTNVM9_IOSFSB_CLKREQ_DIS __BIT(12)
sys/dev/pci/if_wmreg.h
147
#define EXTRXD_DD_MASK __BIT(0)
sys/dev/pci/if_wmreg.h
1471
#define FEXTNVM11_DIS_MULRFIX __BIT(13) /* Disable MULR fix */
sys/dev/pci/if_wmreg.h
1484
#define EEC_FLASH_DETECTED __BIT(19) /* FLASH */
sys/dev/pci/if_wmreg.h
1485
#define EEC_FLUPD __BIT(23) /* Update FLASH */
sys/dev/pci/if_wmreg.h
1541
#define NVM_CFG1_LVDID __BIT(0)
sys/dev/pci/if_wmreg.h
1542
#define NVM_CFG1_LSSID __BIT(1)
sys/dev/pci/if_wmreg.h
1543
#define NVM_CFG1_PME_CLOCK __BIT(2)
sys/dev/pci/if_wmreg.h
1544
#define NVM_CFG1_PM __BIT(3)
sys/dev/pci/if_wmreg.h
1545
#define NVM_CFG1_ILOS __BIT(4) /* Invert loss of signal */
sys/dev/pci/if_wmreg.h
1548
#define NVM_CFG1_IPS1 __BIT(8)
sys/dev/pci/if_wmreg.h
1549
#define NVM_CFG1_LRST __BIT(9)
sys/dev/pci/if_wmreg.h
1550
#define NVM_CFG1_FD __BIT(10)
sys/dev/pci/if_wmreg.h
1551
#define NVM_CFG1_FRCSPD __BIT(11)
sys/dev/pci/if_wmreg.h
1552
#define NVM_CFG1_IPS0 __BIT(12)
sys/dev/pci/if_wmreg.h
1553
#define NVM_CFG1_64_32_BAR __BIT(13)
sys/dev/pci/if_wmreg.h
1555
#define NVM_CFG2_CSR_RD_SPLIT __BIT(1)
sys/dev/pci/if_wmreg.h
1556
#define NVM_CFG2_82544_APM_EN __BIT(2)
sys/dev/pci/if_wmreg.h
1557
#define NVM_CFG2_64_BIT __BIT(3)
sys/dev/pci/if_wmreg.h
1558
#define NVM_CFG2_MAX_READ __BIT(4)
sys/dev/pci/if_wmreg.h
1559
#define NVM_CFG2_DMCR_MAP __BIT(5)
sys/dev/pci/if_wmreg.h
1560
#define NVM_CFG2_133_CAP __BIT(6)
sys/dev/pci/if_wmreg.h
1561
#define NVM_CFG2_MSI_DIS __BIT(7)
sys/dev/pci/if_wmreg.h
1562
#define NVM_CFG2_FLASH_DIS __BIT(8)
sys/dev/pci/if_wmreg.h
1564
#define NVM_CFG2_APM_EN __BIT(10)
sys/dev/pci/if_wmreg.h
1565
#define NVM_CFG2_ANE __BIT(11)
sys/dev/pci/if_wmreg.h
1567
#define NVM_CFG2_ASDE __BIT(14)
sys/dev/pci/if_wmreg.h
1568
#define NVM_CFG2_APM_PME __BIT(15)
sys/dev/pci/if_wmreg.h
1577
#define NVM_COMPAT_MAS_EN(x) __BIT(x) /* Media Auto Sense Enable */
sys/dev/pci/if_wmreg.h
1578
#define NVM_COMPAT_SERDES_FORCE_MODE __BIT(14) /* Don't use autonego */
sys/dev/pci/if_wmreg.h
1590
#define NVM_CFG3_PORTA_EXT_MDIO __BIT(2) /* External MDIO Interface */
sys/dev/pci/if_wmreg.h
1591
#define NVM_CFG3_PORTA_COM_MDIO __BIT(3) /* MDIO Interface is shared */
sys/dev/pci/if_wmreg.h
1592
#define NVM_CFG3_APME __BIT(10) /* APM Enable */
sys/dev/pci/if_wmreg.h
1593
#define NVM_CFG3_ILOS __BIT(13) /* Invert loss of signal */
sys/dev/pci/if_wmreg.h
1750
#define NQTX_CMD_EOP __BIT(24) /* end of packet */
sys/dev/pci/if_wmreg.h
1751
#define NQTX_CMD_IFCS __BIT(25) /* insert FCS */
sys/dev/pci/if_wmreg.h
1752
#define NQTX_CMD_RS __BIT(27) /* report status */
sys/dev/pci/if_wmreg.h
1753
#define NQTX_CMD_DEXT __BIT(29) /* descriptor extension */
sys/dev/pci/if_wmreg.h
1754
#define NQTX_CMD_VLE __BIT(30) /* VLAN enable */
sys/dev/pci/if_wmreg.h
1755
#define NQTX_CMD_TSE __BIT(31) /* TCP segmentation enable */
sys/dev/pci/if_wmreg.h
1766
#define NQTXD_FIELDS_IXSM __BIT(8) /* do IP checksum */
sys/dev/pci/if_wmreg.h
1767
#define NQTXD_FIELDS_TUXSM __BIT(9) /* do TCP/UDP checksum */
sys/dev/pci/if_wmreg.h
1778
#define NQTXC_CMD_SNAP __BIT(9)
sys/dev/pci/if_wmreg.h
1779
#define NQTXC_CMD_IPV_MASK __BIT(10)
sys/dev/pci/if_wmreg.h
1782
#define NQTXC_CMD_TP_MASK __BIT(11)
sys/dev/pci/if_wmreg.h
186
#define EXTRXC_ERROR_CE __BIT(4) /* The same as WRX_ER_CE. */
sys/dev/pci/if_wmreg.h
187
#define EXTRXC_ERROR_SE __BIT(5) /* The same as WRX_ER_SE. */
sys/dev/pci/if_wmreg.h
188
#define EXTRXC_ERROR_SEQ __BIT(6) /* The same as WRX_ER_SEQ. */
sys/dev/pci/if_wmreg.h
190
#define EXTRXC_ERROR_CXE __BIT(8) /* The same as WRX_ER_CXE. */
sys/dev/pci/if_wmreg.h
191
#define EXTRXC_ERROR_TCPE __BIT(9) /* The same as WRX_ER_TCPE. */
sys/dev/pci/if_wmreg.h
192
#define EXTRXC_ERROR_IPE __BIT(10) /* The same as WRX_ER_IPE. */
sys/dev/pci/if_wmreg.h
193
#define EXTRXC_ERROR_RXE __BIT(11) /* The same as WRX_ER_RXE. */
sys/dev/pci/if_wmreg.h
195
#define EXTRXC_STATUS_DD __BIT(0) /* The same as WRX_ST_DD. */
sys/dev/pci/if_wmreg.h
196
#define EXTRXC_STATUS_EOP __BIT(1) /* The same as WRX_ST_EOP. */
sys/dev/pci/if_wmreg.h
198
#define EXTRXC_STATUS_VP __BIT(3) /* The same as WRX_ST_VP. */
sys/dev/pci/if_wmreg.h
199
#define EXTRXC_STATUS_UDPCS __BIT(4) /* UDP checksum calculated on packet. */
sys/dev/pci/if_wmreg.h
200
#define EXTRXC_STATUS_TCPCS __BIT(5) /* The same as WRX_ST_TCPCS. */
sys/dev/pci/if_wmreg.h
201
#define EXTRXC_STATUS_IPCS __BIT(6) /* The same as WRX_ST_IPCS. */
sys/dev/pci/if_wmreg.h
203
#define EXTRXC_STATUS_TST __BIT(8) /* Time stamp taken. */
sys/dev/pci/if_wmreg.h
204
#define EXTRXC_STATUS_IPIDV __BIT(9) /* IP identification valid. */
sys/dev/pci/if_wmreg.h
205
#define EXTRXC_STATUS_UDPV __BIT(10) /* Valid UDP XSUM. */
sys/dev/pci/if_wmreg.h
207
#define EXTRXC_STATUS_ACK __BIT(15) /* ACK packet indication. */
sys/dev/pci/if_wmreg.h
231
#define NQRXD_A0_MASK __BIT(0)
sys/dev/pci/if_wmreg.h
232
#define NQRXD_NSE_MASK __BIT(0)
sys/dev/pci/if_wmreg.h
235
#define NQRXD_DD_MASK __BIT(0)
sys/dev/pci/if_wmreg.h
256
#define NQRXC_PKT_TYPE_ETQF_VALID_MASK __BIT(15)
sys/dev/pci/if_wmreg.h
257
#define NQRXC_PKT_TYPE_VLAN_MASK __BIT(16)
sys/dev/pci/if_wmreg.h
262
#define NQRXC_SPH_MASK __BIT(31)
sys/dev/pci/if_wmreg.h
288
#define NQRXC_PKT_TYPE_IPV4 __BIT(0)
sys/dev/pci/if_wmreg.h
289
#define NQRXC_PKT_TYPE_IPV4E __BIT(1)
sys/dev/pci/if_wmreg.h
290
#define NQRXC_PKT_TYPE_IPV6 __BIT(2)
sys/dev/pci/if_wmreg.h
291
#define NQRXC_PKT_TYPE_IPV6E __BIT(3)
sys/dev/pci/if_wmreg.h
292
#define NQRXC_PKT_TYPE_TCP __BIT(4)
sys/dev/pci/if_wmreg.h
293
#define NQRXC_PKT_TYPE_UDP __BIT(5)
sys/dev/pci/if_wmreg.h
294
#define NQRXC_PKT_TYPE_SCTP __BIT(6)
sys/dev/pci/if_wmreg.h
295
#define NQRXC_PKT_TYPE_NFS __BIT(7)
sys/dev/pci/if_wmreg.h
303
#define NQRXC_ERROR_HB0 __BIT(3) /* Header Buffer Overflow. */
sys/dev/pci/if_wmreg.h
306
#define NQRXC_ERROR_L4E __BIT(9) /* L4 error indication. */
sys/dev/pci/if_wmreg.h
307
#define NQRXC_ERROR_IPE __BIT(10) /* The same as WRX_ER_IPE. */
sys/dev/pci/if_wmreg.h
308
#define NQRXC_ERROR_RXE __BIT(11) /* The same as WRX_ER_RXE. */
sys/dev/pci/if_wmreg.h
311
#define NQRXC_STATUS_DD __BIT(0) /* The same as WRX_ST_DD. */
sys/dev/pci/if_wmreg.h
312
#define NQRXC_STATUS_EOP __BIT(1) /* The same as WRX_ST_EOP. */
sys/dev/pci/if_wmreg.h
314
#define NQRXC_STATUS_VP __BIT(3) /* The same as WRX_ST_VP. */
sys/dev/pci/if_wmreg.h
315
#define NQRXC_STATUS_UDPCS __BIT(4) /* UDP checksum or IP payload checksum. */
sys/dev/pci/if_wmreg.h
317
#define NQRXC_STATUS_L4I __BIT(5) /* L4 integrity check was done. */
sys/dev/pci/if_wmreg.h
318
#define NQRXC_STATUS_IPCS __BIT(6) /* The same as WRX_ST_IPCS. */
sys/dev/pci/if_wmreg.h
319
#define NQRXC_STATUS_PIF __BIT(7) /* The same as WRX_ST_PIF. */
sys/dev/pci/if_wmreg.h
321
#define NQRXC_STATUS_VEXT __BIT(9) /* First VLAN is found on a bouble VLAN packet. */
sys/dev/pci/if_wmreg.h
322
#define NQRXC_STATUS_UDPV __BIT(10) /* The packet contains a valid checksum field in a first fragment UDP IPv4 packet. */
sys/dev/pci/if_wmreg.h
323
#define NQRXC_STATUS_LLINT __BIT(11) /* The packet caused an immediate interrupt. */
sys/dev/pci/if_wmreg.h
324
#define NQRXC_STATUS_STRIPCRC __BIT(12) /* Ethernet CRC is stripped. */
sys/dev/pci/if_wmreg.h
326
#define NQRXC_STATUS_TSIP __BIT(15) /* Timestamp in packet. */
sys/dev/pci/if_wmreg.h
327
#define NQRXC_STATUS_TS __BIT(16) /* Time stamped packet. */
sys/dev/pci/if_wmreg.h
329
#define NQRXC_STATUS_LB __BIT(18) /* Sent by a local virtual machine (VM to VM switch indication). */
sys/dev/pci/if_wmreg.h
330
#define NQRXC_STATUS_MC __BIT(19) /* Packet received from Manageability Controller */
sys/dev/pci/if_wmreg.h
351
#define WTX_CMD_EOP __BIT(24) /* end of packet */
sys/dev/pci/if_wmreg.h
352
#define WTX_CMD_IFCS __BIT(25) /* insert FCS */
sys/dev/pci/if_wmreg.h
353
#define WTX_CMD_RS __BIT(27) /* report status */
sys/dev/pci/if_wmreg.h
354
#define WTX_CMD_RPS __BIT(28) /* report packet sent */
sys/dev/pci/if_wmreg.h
355
#define WTX_CMD_DEXT __BIT(29) /* descriptor extension */
sys/dev/pci/if_wmreg.h
356
#define WTX_CMD_VLE __BIT(30) /* VLAN enable */
sys/dev/pci/if_wmreg.h
357
#define WTX_CMD_IDE __BIT(31) /* interrupt delay enable */
sys/dev/pci/if_wmreg.h
360
#define WTX_DTYP_MASK __BIT(20)
sys/dev/pci/if_wmreg.h
365
#define WTX_ST_DD __BIT(0) /* descriptor done */
sys/dev/pci/if_wmreg.h
366
#define WTX_ST_EC __BIT(1) /* excessive collisions */
sys/dev/pci/if_wmreg.h
367
#define WTX_ST_LC __BIT(2) /* late collision */
sys/dev/pci/if_wmreg.h
368
#define WTX_ST_TU __BIT(3) /* transmit underrun */
sys/dev/pci/if_wmreg.h
371
#define WTX_IXSM __BIT(0) /* IP checksum offload */
sys/dev/pci/if_wmreg.h
372
#define WTX_TXSM __BIT(1) /* TCP/UDP checksum offload */
sys/dev/pci/if_wmreg.h
388
#define WTX_TCPIP_CMD_TCP __BIT(24) /* 1 = TCP, 0 = UDP */
sys/dev/pci/if_wmreg.h
389
#define WTX_TCPIP_CMD_IP __BIT(25) /* 1 = IPv4, 0 = IPv6 */
sys/dev/pci/if_wmreg.h
390
#define WTX_TCPIP_CMD_TSE __BIT(26) /* segmentation context valid */
sys/dev/pci/if_wmreg.h
415
#define DESCRING_STATUS_FLUSH_REQ __BIT(8)
sys/dev/pci/if_wmreg.h
421
#define CTRL_FD __BIT(0) /* full duplex */
sys/dev/pci/if_wmreg.h
422
#define CTRL_BEM __BIT(1) /* big-endian mode */
sys/dev/pci/if_wmreg.h
423
#define CTRL_PRIOR __BIT(2) /* 0 = receive, 1 = fair */
sys/dev/pci/if_wmreg.h
424
#define CTRL_GIO_M_DIS __BIT(2) /* disabl PCI master access */
sys/dev/pci/if_wmreg.h
425
#define CTRL_LRST __BIT(3) /* link reset */
sys/dev/pci/if_wmreg.h
426
#define CTRL_ASDE __BIT(5) /* auto speed detect enable */
sys/dev/pci/if_wmreg.h
427
#define CTRL_SLU __BIT(6) /* set link up */
sys/dev/pci/if_wmreg.h
428
#define CTRL_ILOS __BIT(7) /* invert loss of signal */
sys/dev/pci/if_wmreg.h
434
#define CTRL_FRCSPD __BIT(11) /* force speed (Livengood) */
sys/dev/pci/if_wmreg.h
435
#define CTRL_FRCFDX __BIT(12) /* force full-duplex (Livengood) */
sys/dev/pci/if_wmreg.h
436
#define CTRL_D_UD_EN __BIT(13) /* Dock/Undock enable */
sys/dev/pci/if_wmreg.h
437
#define CTRL_D_UD_POL __BIT(14) /* Defined polarity of Dock/Undock indication in SDP[0] */
sys/dev/pci/if_wmreg.h
438
#define CTRL_F_PHY_R __BIT(15) /* Reset both PHY ports, through PHYRST_N pin */
sys/dev/pci/if_wmreg.h
439
#define CTRL_EXTLINK_EN __BIT(16) /* enable link status from external LINK_0 and LINK_1 pins */
sys/dev/pci/if_wmreg.h
440
#define CTRL_LANPHYPC_OVERRIDE __BIT(16) /* SW control of LANPHYPC */
sys/dev/pci/if_wmreg.h
441
#define CTRL_LANPHYPC_VALUE __BIT(17) /* SW value of LANPHYPC */
sys/dev/pci/if_wmreg.h
448
#define CTRL_MEHE __BIT(19) /* Memory Error Handling Enable(I217)*/
sys/dev/pci/if_wmreg.h
449
#define CTRL_RST __BIT(26) /* device reset */
sys/dev/pci/if_wmreg.h
450
#define CTRL_RFCE __BIT(27) /* Rx flow control enable */
sys/dev/pci/if_wmreg.h
451
#define CTRL_TFCE __BIT(28) /* Tx flow control enable */
sys/dev/pci/if_wmreg.h
452
#define CTRL_VME __BIT(30) /* VLAN Mode Enable */
sys/dev/pci/if_wmreg.h
453
#define CTRL_PHY_RESET __BIT(31) /* PHY reset (Cordova) */
sys/dev/pci/if_wmreg.h
458
#define STATUS_FD __BIT(0) /* full duplex */
sys/dev/pci/if_wmreg.h
459
#define STATUS_LU __BIT(1) /* link up */
sys/dev/pci/if_wmreg.h
460
#define STATUS_TCKOK __BIT(2) /* Tx clock running */
sys/dev/pci/if_wmreg.h
461
#define STATUS_RBCOK __BIT(3) /* Rx clock running */
sys/dev/pci/if_wmreg.h
464
#define STATUS_TXOFF __BIT(4) /* Tx paused */
sys/dev/pci/if_wmreg.h
465
#define STATUS_TBIMODE __BIT(5) /* fiber mode (Livengood) */
sys/dev/pci/if_wmreg.h
471
#define STATUS_LAN_INIT_DONE __BIT(9) /* Lan Init Completion by NVM */
sys/dev/pci/if_wmreg.h
472
#define STATUS_MTXCKOK __BIT(10) /* MTXD clock running */
sys/dev/pci/if_wmreg.h
473
#define STATUS_PHYRA __BIT(10) /* PHY Reset Asserted (PCH) */
sys/dev/pci/if_wmreg.h
474
#define STATUS_PCI66 __BIT(11) /* 66MHz bus (Livengood) */
sys/dev/pci/if_wmreg.h
475
#define STATUS_BUS64 __BIT(12) /* 64-bit bus (Livengood) */
sys/dev/pci/if_wmreg.h
476
#define STATUS_2P5_SKU __BIT(12) /* Value of the 2.5GBE SKU strap */
sys/dev/pci/if_wmreg.h
477
#define STATUS_PCIX_MODE __BIT(13) /* PCIX mode (Cordova) */
sys/dev/pci/if_wmreg.h
478
#define STATUS_2P5_SKU_OVER __BIT(13) /* Value of the 2.5GBE SKU override */
sys/dev/pci/if_wmreg.h
484
#define STATUS_GIO_M_ENA __BIT(19) /* GIO master enable */
sys/dev/pci/if_wmreg.h
485
#define STATUS_DEV_RST_SET __BIT(20) /* Device Reset Set */
sys/dev/pci/if_wmreg.h
494
#define EECD_SK __BIT(0) /* clock */
sys/dev/pci/if_wmreg.h
495
#define EECD_CS __BIT(1) /* chip select */
sys/dev/pci/if_wmreg.h
496
#define EECD_DI __BIT(2) /* data in */
sys/dev/pci/if_wmreg.h
497
#define EECD_DO __BIT(3) /* data out */
sys/dev/pci/if_wmreg.h
501
#define EECD_EE_REQ __BIT(6) /* (shared) EEPROM request */
sys/dev/pci/if_wmreg.h
502
#define EECD_EE_GNT __BIT(7) /* (shared) EEPROM grant */
sys/dev/pci/if_wmreg.h
503
#define EECD_EE_PRES __BIT(8) /* EEPROM present */
sys/dev/pci/if_wmreg.h
504
#define EECD_EE_SIZE __BIT(9) /* EEPROM size
sys/dev/pci/if_wmreg.h
506
#define EECD_EE_AUTORD __BIT(9) /* auto read done */
sys/dev/pci/if_wmreg.h
507
#define EECD_EE_ABITS __BIT(10) /* EEPROM address bits
sys/dev/pci/if_wmreg.h
510
#define EECD_EE_TYPE __BIT(13) /* EEPROM type
sys/dev/pci/if_wmreg.h
512
#define EECD_SEC1VAL __BIT(22) /* Sector One Valid */
sys/dev/pci/if_wmreg.h
516
#define FEXTNVM6_REQ_PLL_CLK __BIT(8)
sys/dev/pci/if_wmreg.h
517
#define FEXTNVM6_ENABLE_K1_ENTRY_CONDITION __BIT(9)
sys/dev/pci/if_wmreg.h
518
#define FEXTNVM6_K1_OFF_ENABLE __BIT(31)
sys/dev/pci/if_wmreg.h
527
#define CTRL_EXT_NSICR __BIT(0) /* Non Interrupt clear on read */
sys/dev/pci/if_wmreg.h
530
#define CTRL_EXT_LPCD __BIT(2) /* LCD Power Cycle Done */
sys/dev/pci/if_wmreg.h
540
#define CTRL_EXT_FORCE_SMBUS __BIT(11) /* Force SMBus mode */
sys/dev/pci/if_wmreg.h
541
#define CTRL_EXT_ASDCHK __BIT(12) /* ASD check */
sys/dev/pci/if_wmreg.h
542
#define CTRL_EXT_EE_RST __BIT(13) /* EEPROM reset */
sys/dev/pci/if_wmreg.h
543
#define CTRL_EXT_IPS __BIT(14) /* invert power state bit 0 */
sys/dev/pci/if_wmreg.h
544
#define CTRL_EXT_SPD_BYPS __BIT(15) /* speed select bypass */
sys/dev/pci/if_wmreg.h
545
#define CTRL_EXT_IPS1 __BIT(16) /* invert power state bit 1 */
sys/dev/pci/if_wmreg.h
546
#define CTRL_EXT_RO_DIS __BIT(17) /* relaxed ordering disabled */
sys/dev/pci/if_wmreg.h
547
#define CTRL_EXT_SDLPE __BIT(18) /* SerDes Low Power Enable */
sys/dev/pci/if_wmreg.h
548
#define CTRL_EXT_DMA_DYN_CLK __BIT(19) /* DMA Dynamic Gating Enable */
sys/dev/pci/if_wmreg.h
549
#define CTRL_EXT_PHYPDEN __BIT(20)
sys/dev/pci/if_wmreg.h
558
#define CTRL_EXT_EIAME __BIT(24) /* Extended Interrupt Auto Mask En */
sys/dev/pci/if_wmreg.h
561
#define CTRL_EXT_PBA __BIT(31) /* PBA Support */
sys/dev/pci/if_wmreg.h
573
#define MDIC_READY __BIT(28)
sys/dev/pci/if_wmreg.h
574
#define MDIC_I __BIT(29) /* interrupt on MDI complete */
sys/dev/pci/if_wmreg.h
575
#define MDIC_E __BIT(30) /* MDI error */
sys/dev/pci/if_wmreg.h
576
#define MDIC_DEST __BIT(31) /* Destination */
sys/dev/pci/if_wmreg.h
583
#define SCTL_CTL_READY __BIT(31)
sys/dev/pci/if_wmreg.h
598
#define FEXTNVM_SW_CONFIG __BIT(0) /* SW PHY Config En (ICH8 B0) */
sys/dev/pci/if_wmreg.h
599
#define FEXTNVM_SW_CONFIG_ICH8M __BIT(27) /* SW PHY Config En (>= ICH8 B1) */
sys/dev/pci/if_wmreg.h
646
#define CONNSW_AUTOSENSE_EN __BIT(0) /* Auto Sense Enable */
sys/dev/pci/if_wmreg.h
647
#define CONNSW_AUTOSENSE_CONF __BIT(1) /* Auto Sense Config Mode */
sys/dev/pci/if_wmreg.h
648
#define CONNSW_ENRGSRC __BIT(2) /* SerDes Energy Detect Src */
sys/dev/pci/if_wmreg.h
649
#define CONNSW_SERDESD __BIT(9) /* SerDes Signal Detect Ind. */
sys/dev/pci/if_wmreg.h
650
#define CONNSW_PHYSD __BIT(10) /* PHY Signal Detect Ind. */
sys/dev/pci/if_wmreg.h
651
#define CONNSW_PHY_PDN __BIT(11) /* Internal PHY in powerdown */
sys/dev/pci/if_wmreg.h
658
#define FEXTNVM3_PHY_CFG_COUNTER_50MS __BIT(27)
sys/dev/pci/if_wmreg.h
679
#define RAL_RDR1 __BIT(30) /* put packet in alt. rx ring */
sys/dev/pci/if_wmreg.h
680
#define RAL_AV __BIT(31) /* entry is valid */
sys/dev/pci/if_wmreg.h
691
#define ICR_TXDW __BIT(0) /* Tx desc written back */
sys/dev/pci/if_wmreg.h
692
#define ICR_TXQE __BIT(1) /* Tx queue empty */
sys/dev/pci/if_wmreg.h
693
#define ICR_LSC __BIT(2) /* link status change */
sys/dev/pci/if_wmreg.h
694
#define ICR_RXSEQ __BIT(3) /* receive sequence error */
sys/dev/pci/if_wmreg.h
695
#define ICR_RXDMT0 __BIT(4) /* Rx ring 0 nearly empty */
sys/dev/pci/if_wmreg.h
696
#define ICR_RXO __BIT(6) /* Rx overrun */
sys/dev/pci/if_wmreg.h
697
#define ICR_RXT0 __BIT(7) /* Rx ring 0 timer */
sys/dev/pci/if_wmreg.h
698
#define ICR_MDAC __BIT(9) /* MDIO access complete */
sys/dev/pci/if_wmreg.h
699
#define ICR_RXCFG __BIT(10) /* Receiving /C/ */
sys/dev/pci/if_wmreg.h
700
#define ICR_GPI(x) __BIT(11+(x)) /* general purpose interrupts */
sys/dev/pci/if_wmreg.h
701
#define ICR_RXQ(x) __BIT(20+(x)) /* 82574: Rx queue x interrupt x=0,1 */
sys/dev/pci/if_wmreg.h
702
#define ICR_TXQ(x) __BIT(22+(x)) /* 82574: Tx queue x interrupt x=0,1 */
sys/dev/pci/if_wmreg.h
703
#define ICR_OTHER __BIT(24) /* 82574: Other interrupt */
sys/dev/pci/if_wmreg.h
704
#define ICR_INT __BIT(31) /* device generated an interrupt */
sys/dev/pci/if_wmreg.h
724
#define FEXTNVM7_SIDE_CLK_UNGATE __BIT(2)
sys/dev/pci/if_wmreg.h
725
#define FEXTNVM7_DIS_SMB_PERST __BIT(5)
sys/dev/pci/if_wmreg.h
726
#define FEXTNVM7_DIS_PB_READ __BIT(18)
sys/dev/pci/if_wmreg.h
731
#define IVAR_VALID __BIT(7)
sys/dev/pci/if_wmreg.h
742
#define IVAR_VALID_82574 __BIT(3)
sys/dev/pci/if_wmreg.h
746
#define IVAR_INT_ON_ALL_WB __BIT(31)
sys/dev/pci/if_wmreg.h
753
#define SVCR_OFF_EN __BIT(0)
sys/dev/pci/if_wmreg.h
754
#define SVCR_OFF_MASKINT __BIT(12)
sys/dev/pci/if_wmreg.h
763
#define LTRV_SNOOP_REQ __BIT(15)
sys/dev/pci/if_wmreg.h
764
#define LTRV_SEND __BIT(30)
sys/dev/pci/if_wmreg.h
766
#define LTRV_NONSNOOP_REQ __BIT(31)
sys/dev/pci/if_wmreg.h
769
#define RCTL_EN __BIT(1) /* receiver enable */
sys/dev/pci/if_wmreg.h
770
#define RCTL_SBP __BIT(2) /* store bad packets */
sys/dev/pci/if_wmreg.h
771
#define RCTL_UPE __BIT(3) /* unicast promisc. enable */
sys/dev/pci/if_wmreg.h
772
#define RCTL_MPE __BIT(4) /* multicast promisc. enable */
sys/dev/pci/if_wmreg.h
773
#define RCTL_LPE __BIT(5) /* large packet enable */
sys/dev/pci/if_wmreg.h
788
#define RCTL_BAM __BIT(15) /* broadcast accept mode */
sys/dev/pci/if_wmreg.h
789
#define RCTL_RDMTS_HEX __BIT(16)
sys/dev/pci/if_wmreg.h
797
#define RCTL_DPF __BIT(22) /* discard pause frames */
sys/dev/pci/if_wmreg.h
798
#define RCTL_PMCF __BIT(23) /* pass MAC control frames */
sys/dev/pci/if_wmreg.h
799
#define RCTL_BSEX __BIT(25) /* buffer size extension (Livengood) */
sys/dev/pci/if_wmreg.h
800
#define RCTL_SECRC __BIT(26) /* strip Ethernet CRC */
sys/dev/pci/if_wmreg.h
804
#define RDTR_FPD __BIT(31) /* flush partial descriptor */
sys/dev/pci/if_wmreg.h
855
#define RXDCTL_GRAN __BIT(24) /* 0 = cacheline, 1 = descriptor */
sys/dev/pci/if_wmreg.h
883
#define TXCW_FD __BIT(5) /* Full Duplex */
sys/dev/pci/if_wmreg.h
884
#define TXCW_HD __BIT(6) /* Half Duplex */
sys/dev/pci/if_wmreg.h
885
#define TXCW_SYM_PAUSE __BIT(7) /* sym pause request */
sys/dev/pci/if_wmreg.h
886
#define TXCW_ASYM_PAUSE __BIT(8) /* asym pause request */
sys/dev/pci/if_wmreg.h
887
#define TXCW_TxConfig __BIT(30) /* Tx Config */
sys/dev/pci/if_wmreg.h
888
#define TXCW_ANE __BIT(31) /* Autonegotiate */
sys/dev/pci/if_wmreg.h
892
#define RXCW_NC __BIT(26) /* no carrier */
sys/dev/pci/if_wmreg.h
893
#define RXCW_IV __BIT(27) /* config invalid */
sys/dev/pci/if_wmreg.h
894
#define RXCW_CC __BIT(28) /* config change */
sys/dev/pci/if_wmreg.h
895
#define RXCW_C __BIT(29) /* /C/ reception */
sys/dev/pci/if_wmreg.h
896
#define RXCW_SYNCH __BIT(30) /* synchronized */
sys/dev/pci/if_wmreg.h
897
#define RXCW_ANC __BIT(31) /* autonegotiation complete */
sys/dev/pci/if_wmreg.h
903
#define TCTL_EN __BIT(1) /* transmitter enable */
sys/dev/pci/if_wmreg.h
904
#define TCTL_PSP __BIT(3) /* pad short packets */
sys/dev/pci/if_wmreg.h
907
#define TCTL_SWXOFF __BIT(22) /* software XOFF */
sys/dev/pci/if_wmreg.h
908
#define TCTL_RTLC __BIT(24) /* retransmit on late collision */
sys/dev/pci/if_wmreg.h
909
#define TCTL_NRTU __BIT(25) /* no retransmit on underrun */
sys/dev/pci/if_wmreg.h
910
#define TCTL_MULR __BIT(28) /* multiple request */
sys/dev/pci/if_wmreg.h
973
#define MDICNFG_COM_MDIO __BIT(30)
sys/dev/pci/if_wmreg.h
974
#define MDICNFG_DEST __BIT(31)
sys/dev/pci/if_wmreg.h
981
#define PHPM_SPD_EN __BIT(0) /* Smart Power Down */
sys/dev/pci/if_wmreg.h
982
#define PHPM_D0A_LPLU __BIT(1) /* D0 Low Power Link Up */
sys/dev/pci/if_wmreg.h
983
#define PHPM_NOND0A_LPLU __BIT(2) /* Non-D0a LPLU */
sys/dev/pci/if_wmreg.h
984
#define PHPM_NOND0A_GBE_DIS __BIT(3) /* Disable 1G in non-D0a */
sys/dev/pci/if_wmreg.h
985
#define PHPM_GO_LINK_D __BIT(5) /* Go Link Disconnect */
sys/dev/pci/ixgbe/ixgbe_type.h
4546
#define IXGBE_QUIRK_MOD_ABS_INVERT __BIT(0)
sys/dev/pci/ixgbe/ixv.c
2450
IXGBE_EVC_ADD(&count, current + __BIT(36) - (last)); \
sys/dev/pci/pccbbreg.h
133
#define PCI1420_SYSCTRL_MRBURSTDN __BIT(15)
sys/dev/pci/pccbbreg.h
135
#define PCI1420_SYSCTRL_MRBURSTUP __BIT(14)
sys/dev/pci/pci_resource.c
1002
enabled |= __BIT(PCI_MAPREG_TYPE_MEM);
sys/dev/pci/pci_resource.c
1005
enabled |= __BIT(PCI_MAPREG_TYPE_IO);
sys/dev/pci/pci_resource.c
1011
if ((enabled & __BIT(pi->pi_type)) != 0) {
sys/dev/pci/pci_resource.c
756
enabled |= __BIT(PCI_MAPREG_TYPE_MEM);
sys/dev/pci/pci_resource.c
759
enabled |= __BIT(PCI_MAPREG_TYPE_IO);
sys/dev/pci/pci_resource.c
765
required |= __BIT(pi->pi_type);
sys/dev/pci/pci_resource.c
772
if ((enabled & __BIT(pi->pi_type)) == 0) {
sys/dev/pci/pci_subr.c
3544
if (reg & __BIT(i)) {
sys/dev/pci/pci_subr.c
4693
onoff("66 MHz capable", rval, __BIT(5));
sys/dev/pci/pci_subr.c
4694
onoff("User Definable Features (UDF) support", rval, __BIT(6));
sys/dev/pci/pci_subr.c
4695
onoff("Fast back-to-back capable", rval, __BIT(7));
sys/dev/pci/pci_subr.c
4696
onoff("Data parity error detected", rval, __BIT(8));
sys/dev/pci/pci_subr.c
4716
onoff("Signalled target abort", rval, __BIT(11));
sys/dev/pci/pci_subr.c
4717
onoff("Received target abort", rval, __BIT(12));
sys/dev/pci/pci_subr.c
4718
onoff("Received master abort", rval, __BIT(13));
sys/dev/pci/pci_subr.c
4719
onoff("Received system error", rval, __BIT(14));
sys/dev/pci/pci_subr.c
4720
onoff("Detected parity error", rval, __BIT(15));
sys/dev/pci/pci_subr.c
5092
onoff("Parity error response", rval, __BIT(0));
sys/dev/pci/pci_subr.c
5093
onoff("SERR# enable", rval, __BIT(1));
sys/dev/pci/pci_subr.c
5094
onoff("ISA enable", rval, __BIT(2));
sys/dev/pci/pci_subr.c
5095
onoff("VGA enable", rval, __BIT(3));
sys/dev/pci/pci_subr.c
5096
onoff("Master abort mode", rval, __BIT(5));
sys/dev/pci/pci_subr.c
5097
onoff("Secondary (CardBus) bus reset", rval, __BIT(6));
sys/dev/pci/pci_subr.c
5099
__BIT(7));
sys/dev/pci/pci_subr.c
5100
onoff("Memory window 0 prefetchable", rval, __BIT(8));
sys/dev/pci/pci_subr.c
5101
onoff("Memory window 1 prefetchable", rval, __BIT(9));
sys/dev/pci/pci_subr.c
5102
onoff("Write posting enable", rval, __BIT(10));
sys/dev/pci/pcireg.h
1003
#define PCIE_DCAP_EXT_TAG_FIELD __BIT(5) /* Extended Tag Field Support */
sys/dev/pci/pcireg.h
1006
#define PCIE_DCAP_ATTN_BUTTON __BIT(12) /* Attention Indicator Button */
sys/dev/pci/pcireg.h
1007
#define PCIE_DCAP_ATTN_IND __BIT(13) /* Attention Indicator Present*/
sys/dev/pci/pcireg.h
1008
#define PCIE_DCAP_PWR_IND __BIT(14) /* Power Indicator Present */
sys/dev/pci/pcireg.h
1009
#define PCIE_DCAP_ROLE_ERR_RPT __BIT(15) /* Role-Based Error Reporting */
sys/dev/pci/pcireg.h
1012
#define PCIE_DCAP_FLR __BIT(28) /* Function-Level Reset Cap. */
sys/dev/pci/pcireg.h
1014
#define PCIE_DCSR_ENA_COR_ERR __BIT(0) /* Correctable Error Report En*/
sys/dev/pci/pcireg.h
1015
#define PCIE_DCSR_ENA_NFER __BIT(1) /* Non-Fatal Error Report En. */
sys/dev/pci/pcireg.h
1016
#define PCIE_DCSR_ENA_FER __BIT(2) /* Fatal Error Reporting Enabl*/
sys/dev/pci/pcireg.h
1017
#define PCIE_DCSR_ENA_URR __BIT(3) /* Unsupported Request Rpt En */
sys/dev/pci/pcireg.h
1018
#define PCIE_DCSR_ENA_RELAX_ORD __BIT(4) /* Enable Relaxed Ordering */
sys/dev/pci/pcireg.h
1020
#define PCIE_DCSR_EXT_TAG_FIELD __BIT(8) /* Extended Tag Field Enable */
sys/dev/pci/pcireg.h
1021
#define PCIE_DCSR_PHANTOM_FUNCS __BIT(9) /* Phantom Functions Enable */
sys/dev/pci/pcireg.h
1022
#define PCIE_DCSR_AUX_POWER_PM __BIT(10) /* Aux Power PM Enable */
sys/dev/pci/pcireg.h
1023
#define PCIE_DCSR_ENA_NO_SNOOP __BIT(11) /* Enable No Snoop */
sys/dev/pci/pcireg.h
1025
#define PCIE_DCSR_BRDG_CFG_RETRY __BIT(15) /* Bridge Config Retry Enable */
sys/dev/pci/pcireg.h
1026
#define PCIE_DCSR_INITIATE_FLR __BIT(15) /* Initiate Function-Level Rst*/
sys/dev/pci/pcireg.h
1027
#define PCIE_DCSR_CED __BIT(0 + 16) /* Correctable Error Detected */
sys/dev/pci/pcireg.h
1028
#define PCIE_DCSR_NFED __BIT(1 + 16) /* Non-Fatal Error Detected */
sys/dev/pci/pcireg.h
1029
#define PCIE_DCSR_FED __BIT(2 + 16) /* Fatal Error Detected */
sys/dev/pci/pcireg.h
1030
#define PCIE_DCSR_URD __BIT(3 + 16) /* Unsupported Req. Detected */
sys/dev/pci/pcireg.h
1031
#define PCIE_DCSR_AUX_PWR __BIT(4 + 16) /* Aux Power Detected */
sys/dev/pci/pcireg.h
1032
#define PCIE_DCSR_TRANSACTION_PND __BIT(5 + 16) /* Transaction Pending */
sys/dev/pci/pcireg.h
1033
#define PCIE_DCSR_EMGPWRREDD __BIT(6 + 16) /* Emg. Pwr. Reduct. Detected */
sys/dev/pci/pcireg.h
1046
#define PCIE_LCAP_CLOCK_PM __BIT(18) /* Clock Power Management */
sys/dev/pci/pcireg.h
1047
#define PCIE_LCAP_SURPRISE_DOWN __BIT(19) /* Surprise Down Err Rpt Cap. */
sys/dev/pci/pcireg.h
1048
#define PCIE_LCAP_DL_ACTIVE __BIT(20) /* Data Link Layer Link Active*/
sys/dev/pci/pcireg.h
1049
#define PCIE_LCAP_LINK_BW_NOTIFY __BIT(21) /* Link BW Notification Capabl*/
sys/dev/pci/pcireg.h
1050
#define PCIE_LCAP_ASPM_COMPLIANCE __BIT(22) /* ASPM Optionally Compliance */
sys/dev/pci/pcireg.h
1053
#define PCIE_LCSR_ASPM_L0S __BIT(0) /* Active State PM Control L0s*/
sys/dev/pci/pcireg.h
1054
#define PCIE_LCSR_ASPM_L1 __BIT(1) /* Active State PM Control L1 */
sys/dev/pci/pcireg.h
1055
#define PCIE_LCSR_RCB __BIT(3) /* Read Completion Boundary Ctl*/
sys/dev/pci/pcireg.h
1056
#define PCIE_LCSR_LINK_DIS __BIT(4) /* Link Disable */
sys/dev/pci/pcireg.h
1057
#define PCIE_LCSR_RETRAIN __BIT(5) /* Retrain Link */
sys/dev/pci/pcireg.h
1058
#define PCIE_LCSR_COMCLKCFG __BIT(6) /* Common Clock Configuration */
sys/dev/pci/pcireg.h
1059
#define PCIE_LCSR_EXTNDSYNC __BIT(7) /* Extended Synch */
sys/dev/pci/pcireg.h
1060
#define PCIE_LCSR_ENCLKPM __BIT(8) /* Enable Clock Power Managmt */
sys/dev/pci/pcireg.h
1061
#define PCIE_LCSR_HAWD __BIT(9) /* HW Autonomous Width Disable*/
sys/dev/pci/pcireg.h
1062
#define PCIE_LCSR_LBMIE __BIT(10) /* Link BW Management Intr En */
sys/dev/pci/pcireg.h
1063
#define PCIE_LCSR_LABIE __BIT(11) /* Link Autonomous BW Intr En */
sys/dev/pci/pcireg.h
1073
#define PCIE_LCSR_NLW_X1 __BIT(20) /* Negotiated x1 */
sys/dev/pci/pcireg.h
1074
#define PCIE_LCSR_NLW_X2 __BIT(21) /* Negotiated x2 */
sys/dev/pci/pcireg.h
1075
#define PCIE_LCSR_NLW_X4 __BIT(22) /* Negotiated x4 */
sys/dev/pci/pcireg.h
1076
#define PCIE_LCSR_NLW_X8 __BIT(23) /* Negotiated x8 */
sys/dev/pci/pcireg.h
1078
#define PCIE_LCSR_NLW_X16 __BIT(24) /* Negotiated x16 */
sys/dev/pci/pcireg.h
1079
#define PCIE_LCSR_NLW_X32 __BIT(25) /* Negotiated x32 */
sys/dev/pci/pcireg.h
1080
#define PCIE_LCSR_LINKTRAIN_ERR __BIT(10 + 16) /* Link Training Error */
sys/dev/pci/pcireg.h
1081
#define PCIE_LCSR_LINKTRAIN __BIT(11 + 16) /* Link Training */
sys/dev/pci/pcireg.h
1082
#define PCIE_LCSR_SLOTCLKCFG __BIT(12 + 16) /* Slot Clock Configuration */
sys/dev/pci/pcireg.h
1083
#define PCIE_LCSR_DLACTIVE __BIT(13 + 16) /* Data Link Layer Link Active*/
sys/dev/pci/pcireg.h
1084
#define PCIE_LCSR_LINK_BW_MGMT __BIT(14 + 16) /* Link BW Management Status */
sys/dev/pci/pcireg.h
1085
#define PCIE_LCSR_LINK_AUTO_BW __BIT(15 + 16) /* Link Autonomous BW Status */
sys/dev/pci/pcireg.h
1087
#define PCIE_SLCAP_ABP __BIT(0) /* Attention Button Present */
sys/dev/pci/pcireg.h
1088
#define PCIE_SLCAP_PCP __BIT(1) /* Power Controller Present */
sys/dev/pci/pcireg.h
1089
#define PCIE_SLCAP_MSP __BIT(2) /* MRL Sensor Present */
sys/dev/pci/pcireg.h
1090
#define PCIE_SLCAP_AIP __BIT(3) /* Attention Indicator Present*/
sys/dev/pci/pcireg.h
1091
#define PCIE_SLCAP_PIP __BIT(4) /* Power Indicator Present */
sys/dev/pci/pcireg.h
1092
#define PCIE_SLCAP_HPS __BIT(5) /* Hot-Plug Surprise */
sys/dev/pci/pcireg.h
1093
#define PCIE_SLCAP_HPC __BIT(6) /* Hot-Plug Capable */
sys/dev/pci/pcireg.h
1096
#define PCIE_SLCAP_EIP __BIT(17) /* Electromechanical Interlock*/
sys/dev/pci/pcireg.h
1097
#define PCIE_SLCAP_NCCS __BIT(18) /* No Command Completed Supp. */
sys/dev/pci/pcireg.h
110
#define PCI_STATUS_IMMD_READNESS __BIT(0+16)
sys/dev/pci/pcireg.h
1100
#define PCIE_SLCSR_ABE __BIT(0) /* Attention Button Pressed En*/
sys/dev/pci/pcireg.h
1101
#define PCIE_SLCSR_PFE __BIT(1) /* Power Button Pressed Enable*/
sys/dev/pci/pcireg.h
1102
#define PCIE_SLCSR_MSE __BIT(2) /* MRL Sensor Changed Enable */
sys/dev/pci/pcireg.h
1103
#define PCIE_SLCSR_PDE __BIT(3) /* Presence Detect Changed Ena*/
sys/dev/pci/pcireg.h
1104
#define PCIE_SLCSR_CCE __BIT(4) /* Command Completed Intr. En */
sys/dev/pci/pcireg.h
1105
#define PCIE_SLCSR_HPE __BIT(5) /* Hot Plug Interrupt Enable */
sys/dev/pci/pcireg.h
1111
#define PCIE_SLCSR_PCC __BIT(10) /*
sys/dev/pci/pcireg.h
1115
#define PCIE_SLCSR_EIC __BIT(11) /* Electromechanical Interlock*/
sys/dev/pci/pcireg.h
1116
#define PCIE_SLCSR_DLLSCE __BIT(12) /* DataLinkLayer State Changed*/
sys/dev/pci/pcireg.h
1117
#define PCIE_SLCSR_AUTOSPLDIS __BIT(13) /* Auto Slot Power Limit Dis. */
sys/dev/pci/pcireg.h
1118
#define PCIE_SLCSR_ABP __BIT(0 + 16) /* Attention Button Pressed */
sys/dev/pci/pcireg.h
1119
#define PCIE_SLCSR_PFD __BIT(1 + 16) /* Power Fault Detected */
sys/dev/pci/pcireg.h
1120
#define PCIE_SLCSR_MSC __BIT(2 + 16) /* MRL Sensor Changed */
sys/dev/pci/pcireg.h
1121
#define PCIE_SLCSR_PDC __BIT(3 + 16) /* Presence Detect Changed */
sys/dev/pci/pcireg.h
1122
#define PCIE_SLCSR_CC __BIT(4 + 16) /* Command Completed */
sys/dev/pci/pcireg.h
1123
#define PCIE_SLCSR_MS __BIT(5 + 16) /* MRL Sensor State */
sys/dev/pci/pcireg.h
1124
#define PCIE_SLCSR_PDS __BIT(6 + 16) /* Presence Detect State */
sys/dev/pci/pcireg.h
1125
#define PCIE_SLCSR_EIS __BIT(7 + 16) /* Electromechanical Interlock*/
sys/dev/pci/pcireg.h
1126
#define PCIE_SLCSR_LACS __BIT(8 + 16) /* Data Link Layer State Chg. */
sys/dev/pci/pcireg.h
1128
#define PCIE_RCR_SERR_CER __BIT(0) /* SERR on Correctable Err. En*/
sys/dev/pci/pcireg.h
1129
#define PCIE_RCR_SERR_NFER __BIT(1) /* SERR on Non-Fatal Error En */
sys/dev/pci/pcireg.h
1130
#define PCIE_RCR_SERR_FER __BIT(2) /* SERR on Fatal Error Enable */
sys/dev/pci/pcireg.h
1131
#define PCIE_RCR_PME_IE __BIT(3) /* PME Interrupt Enable */
sys/dev/pci/pcireg.h
1132
#define PCIE_RCR_CRS_SVE __BIT(4) /* CRS Software Visibility En */
sys/dev/pci/pcireg.h
1133
#define PCIE_RCR_CRS_SV __BIT(16) /* CRS Software Visibility */
sys/dev/pci/pcireg.h
1136
#define PCIE_RSR_PME_STAT __BIT(16) /* PME Status */
sys/dev/pci/pcireg.h
1137
#define PCIE_RSR_PME_PEND __BIT(17) /* PME Pending */
sys/dev/pci/pcireg.h
1140
#define PCIE_DCAP2_COMPT_DIS __BIT(4) /* Compl. Timeout Disable Supp*/
sys/dev/pci/pcireg.h
1141
#define PCIE_DCAP2_ARI_FWD __BIT(5) /* ARI Forward Supported */
sys/dev/pci/pcireg.h
1142
#define PCIE_DCAP2_ATOM_ROUT __BIT(6) /* AtomicOp Routing Supported */
sys/dev/pci/pcireg.h
1143
#define PCIE_DCAP2_32ATOM __BIT(7) /* 32bit AtomicOp Compl. Supp */
sys/dev/pci/pcireg.h
1144
#define PCIE_DCAP2_64ATOM __BIT(8) /* 64bit AtomicOp Compl. Supp */
sys/dev/pci/pcireg.h
1145
#define PCIE_DCAP2_128CAS __BIT(9) /* 128bit Cas Completer Supp. */
sys/dev/pci/pcireg.h
1146
#define PCIE_DCAP2_NO_ROPR_PASS __BIT(10) /* No RO-enabled PR-PR Passng */
sys/dev/pci/pcireg.h
1147
#define PCIE_DCAP2_LTR_MEC __BIT(11) /* LTR Mechanism Supported */
sys/dev/pci/pcireg.h
1150
#define PCIE_DCAP2_TBT_COMP __BIT(16) /* 10-bit Tag Completer Supp. */
sys/dev/pci/pcireg.h
1151
#define PCIE_DCAP2_TBT_REQ __BIT(17) /* 10-bit Tag Requester Supp. */
sys/dev/pci/pcireg.h
1153
#define PCIE_DCAP2_EXTFMT_FLD __BIT(20) /* Extended Fmt Field Support */
sys/dev/pci/pcireg.h
1154
#define PCIE_DCAP2_EETLP_PREF __BIT(21) /* End-End TLP Prefix Support */
sys/dev/pci/pcireg.h
1157
#define PCIE_DCAP2_EMGPWRRED_INI __BIT(26) /* Emrg. Pwr. Reduc. Ini. Req */
sys/dev/pci/pcireg.h
1158
#define PCIE_DCAP2_FRS __BIT(31) /* FRS Supported */
sys/dev/pci/pcireg.h
1161
#define PCIE_DCSR2_COMPT_DIS __BIT(4) /* Completion Timeout Disable */
sys/dev/pci/pcireg.h
1162
#define PCIE_DCSR2_ARI_FWD __BIT(5) /* ARI Forwarding Enable */
sys/dev/pci/pcireg.h
1163
#define PCIE_DCSR2_ATOM_REQ __BIT(6) /* AtomicOp Requester Enable */
sys/dev/pci/pcireg.h
1164
#define PCIE_DCSR2_ATOM_EBLK __BIT(7) /* AtomicOp Egress Blocking */
sys/dev/pci/pcireg.h
1165
#define PCIE_DCSR2_IDO_REQ __BIT(8) /* IDO Request Enable */
sys/dev/pci/pcireg.h
1166
#define PCIE_DCSR2_IDO_COMP __BIT(9) /* IDO Completion Enable */
sys/dev/pci/pcireg.h
1167
#define PCIE_DCSR2_LTR_MEC __BIT(10) /* LTR Mechanism Enable */
sys/dev/pci/pcireg.h
1168
#define PCIE_DCSR2_EMGPWRRED_REQ __BIT(11) /* Emergency Power Reduc. Req */
sys/dev/pci/pcireg.h
1169
#define PCIE_DCSR2_TBT_REQ __BIT(12) /* 10-bit Tag Requester Ena. */
sys/dev/pci/pcireg.h
1171
#define PCIE_DCSR2_EETLP __BIT(15) /* End-End TLP Prefix Blcking */
sys/dev/pci/pcireg.h
1174
#define PCIE_LCAP2_SUP_LNKS2 __BIT(1) /* Supported Speed 2.5GT/ */
sys/dev/pci/pcireg.h
1175
#define PCIE_LCAP2_SUP_LNKS5 __BIT(2) /* Supported Speed 5GT/ */
sys/dev/pci/pcireg.h
1176
#define PCIE_LCAP2_SUP_LNKS8 __BIT(3) /* Supported Speed 8GT/ */
sys/dev/pci/pcireg.h
1177
#define PCIE_LCAP2_SUP_LNKS16 __BIT(4) /* Supported Speed 16GT/ */
sys/dev/pci/pcireg.h
1178
#define PCIE_LCAP2_SUP_LNKS32 __BIT(5) /* Supported Speed 32GT/ */
sys/dev/pci/pcireg.h
1179
#define PCIE_LCAP2_SUP_LNKS64 __BIT(6) /* Supported Speed 64GT/ */
sys/dev/pci/pcireg.h
1180
#define PCIE_LCAP2_CROSSLNK __BIT(8) /* Crosslink Supported */
sys/dev/pci/pcireg.h
1185
#define PCIE_LCAP2_RETIMERPD __BIT(23) /* Retimer Presence Detect */
sys/dev/pci/pcireg.h
1186
#define PCIE_LCAP2_DRS __BIT(31) /* DRS Supported */
sys/dev/pci/pcireg.h
1192
#define PCIE_LCSR2_ENT_COMPL __BIT(4) /* Enter Compliance */
sys/dev/pci/pcireg.h
1193
#define PCIE_LCSR2_HW_AS_DIS __BIT(5) /* HW Autonomous Speed Disabl */
sys/dev/pci/pcireg.h
1194
#define PCIE_LCSR2_SEL_DEEMP __BIT(6) /* Selectable De-emphasis */
sys/dev/pci/pcireg.h
1196
#define PCIE_LCSR2_EN_MCOMP __BIT(10) /* Enter Modified Compliance */
sys/dev/pci/pcireg.h
1197
#define PCIE_LCSR2_COMP_SOS __BIT(11) /* Compliance SOS */
sys/dev/pci/pcireg.h
1199
#define PCIE_LCSR2_DEEMP_LVL __BIT(0 + 16) /* Current De-emphasis Level */
sys/dev/pci/pcireg.h
1200
#define PCIE_LCSR2_EQ_COMPL __BIT(1 + 16) /* Equalization Complete */
sys/dev/pci/pcireg.h
1201
#define PCIE_LCSR2_EQP1_SUC __BIT(2 + 16) /* Equaliz Phase 1 Successful */
sys/dev/pci/pcireg.h
1202
#define PCIE_LCSR2_EQP2_SUC __BIT(3 + 16) /* Equaliz Phase 2 Successful */
sys/dev/pci/pcireg.h
1203
#define PCIE_LCSR2_EQP3_SUC __BIT(4 + 16) /* Equaliz Phase 3 Successful */
sys/dev/pci/pcireg.h
1204
#define PCIE_LCSR2_LNKEQ_REQ __BIT(5 + 16) /* Link Equalization Request */
sys/dev/pci/pcireg.h
1205
#define PCIE_LCSR2_RETIMERPD __BIT(6 + 16) /* Retimer Presence Detected */
sys/dev/pci/pcireg.h
1213
#define PCIE_LCSR2_DRSRCV __BIT(15 + 16) /* DRS Message Received */
sys/dev/pci/pcireg.h
1266
#define PCI_MSIX_VECTCTL_MASK __BIT(0)
sys/dev/pci/pcireg.h
1293
#define PCI_AF_TP_CAP __BIT(24) /* Transaction Pending */
sys/dev/pci/pcireg.h
1294
#define PCI_AF_FLR_CAP __BIT(25) /* Function Level Reset */
sys/dev/pci/pcireg.h
1296
#define PCI_AFCR_INITIATE_FLR __BIT(0) /* Initiate Function LVL RST */
sys/dev/pci/pcireg.h
1297
#define PCI_AFSR_TP __BIT(8) /* Transaction Pending */
sys/dev/pci/pcireg.h
1422
#define PCI_BRIDGE_CONTROL_PERE __BIT(16)
sys/dev/pci/pcireg.h
1423
#define PCI_BRIDGE_CONTROL_SERR __BIT(17)
sys/dev/pci/pcireg.h
1424
#define PCI_BRIDGE_CONTROL_ISA __BIT(18)
sys/dev/pci/pcireg.h
1425
#define PCI_BRIDGE_CONTROL_VGA __BIT(19)
sys/dev/pci/pcireg.h
1426
#define PCI_BRIDGE_CONTROL_VGA16 __BIT(20)
sys/dev/pci/pcireg.h
1427
#define PCI_BRIDGE_CONTROL_MABRT __BIT(21)
sys/dev/pci/pcireg.h
1428
#define PCI_BRIDGE_CONTROL_SECBR __BIT(22)
sys/dev/pci/pcireg.h
1429
#define PCI_BRIDGE_CONTROL_SECFASTB2B __BIT(23)
sys/dev/pci/pcireg.h
1430
#define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER __BIT(24)
sys/dev/pci/pcireg.h
1431
#define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER __BIT(25)
sys/dev/pci/pcireg.h
1432
#define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT __BIT(26)
sys/dev/pci/pcireg.h
1433
#define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR __BIT(27)
sys/dev/pci/pcireg.h
1604
#define PCI_AER_UC_UNDEFINED __BIT(0)
sys/dev/pci/pcireg.h
1605
#define PCI_AER_UC_DL_PROTOCOL_ERROR __BIT(4)
sys/dev/pci/pcireg.h
1606
#define PCI_AER_UC_SURPRISE_DOWN_ERROR __BIT(5)
sys/dev/pci/pcireg.h
1607
#define PCI_AER_UC_POISONED_TLP __BIT(12)
sys/dev/pci/pcireg.h
1608
#define PCI_AER_UC_FC_PROTOCOL_ERROR __BIT(13)
sys/dev/pci/pcireg.h
1609
#define PCI_AER_UC_COMPLETION_TIMEOUT __BIT(14)
sys/dev/pci/pcireg.h
1610
#define PCI_AER_UC_COMPLETER_ABORT __BIT(15)
sys/dev/pci/pcireg.h
1611
#define PCI_AER_UC_UNEXPECTED_COMPLETION __BIT(16)
sys/dev/pci/pcireg.h
1612
#define PCI_AER_UC_RECEIVER_OVERFLOW __BIT(17)
sys/dev/pci/pcireg.h
1613
#define PCI_AER_UC_MALFORMED_TLP __BIT(18)
sys/dev/pci/pcireg.h
1614
#define PCI_AER_UC_ECRC_ERROR __BIT(19)
sys/dev/pci/pcireg.h
1615
#define PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR __BIT(20)
sys/dev/pci/pcireg.h
1616
#define PCI_AER_UC_ACS_VIOLATION __BIT(21)
sys/dev/pci/pcireg.h
1617
#define PCI_AER_UC_INTERNAL_ERROR __BIT(22)
sys/dev/pci/pcireg.h
1618
#define PCI_AER_UC_MC_BLOCKED_TLP __BIT(23)
sys/dev/pci/pcireg.h
1619
#define PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED __BIT(24)
sys/dev/pci/pcireg.h
1620
#define PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR __BIT(25)
sys/dev/pci/pcireg.h
1621
#define PCI_AER_UC_POISONTLP_EGRESS_BLOCKED __BIT(26)
sys/dev/pci/pcireg.h
1627
#define PCI_AER_COR_RECEIVER_ERROR __BIT(0)
sys/dev/pci/pcireg.h
1628
#define PCI_AER_COR_BAD_TLP __BIT(6)
sys/dev/pci/pcireg.h
1629
#define PCI_AER_COR_BAD_DLLP __BIT(7)
sys/dev/pci/pcireg.h
1630
#define PCI_AER_COR_REPLAY_NUM_ROLLOVER __BIT(8)
sys/dev/pci/pcireg.h
1631
#define PCI_AER_COR_REPLAY_TIMER_TIMEOUT __BIT(12)
sys/dev/pci/pcireg.h
1632
#define PCI_AER_COR_ADVISORY_NF_ERROR __BIT(13)
sys/dev/pci/pcireg.h
1633
#define PCI_AER_COR_INTERNAL_ERROR __BIT(14)
sys/dev/pci/pcireg.h
1634
#define PCI_AER_COR_HEADER_LOG_OVERFLOW __BIT(15)
sys/dev/pci/pcireg.h
1639
#define PCI_AER_ECRC_GEN_CAPABLE __BIT(5)
sys/dev/pci/pcireg.h
1640
#define PCI_AER_ECRC_GEN_ENABLE __BIT(6)
sys/dev/pci/pcireg.h
1641
#define PCI_AER_ECRC_CHECK_CAPABLE __BIT(7)
sys/dev/pci/pcireg.h
1642
#define PCI_AER_ECRC_CHECK_ENABLE __BIT(8)
sys/dev/pci/pcireg.h
1643
#define PCI_AER_MULT_HDR_CAPABLE __BIT(9)
sys/dev/pci/pcireg.h
1644
#define PCI_AER_MULT_HDR_ENABLE __BIT(10)
sys/dev/pci/pcireg.h
1645
#define PCI_AER_TLP_PREFIX_LOG_PRESENT __BIT(11)
sys/dev/pci/pcireg.h
1646
#define PCI_AER_COMPTOUTPRFXHDRLOG_CAP __BIT(12)
sys/dev/pci/pcireg.h
1650
#define PCI_AER_ROOTERR_COR_ENABLE __BIT(0)
sys/dev/pci/pcireg.h
1651
#define PCI_AER_ROOTERR_NF_ENABLE __BIT(1)
sys/dev/pci/pcireg.h
1652
#define PCI_AER_ROOTERR_F_ENABLE __BIT(2)
sys/dev/pci/pcireg.h
1655
#define PCI_AER_ROOTERR_COR_ERR __BIT(0)
sys/dev/pci/pcireg.h
1656
#define PCI_AER_ROOTERR_MULTI_COR_ERR __BIT(1)
sys/dev/pci/pcireg.h
1657
#define PCI_AER_ROOTERR_UC_ERR __BIT(2)
sys/dev/pci/pcireg.h
1658
#define PCI_AER_ROOTERR_MULTI_UC_ERR __BIT(3)
sys/dev/pci/pcireg.h
1659
#define PCI_AER_ROOTERR_FIRST_UC_FATAL __BIT(4)
sys/dev/pci/pcireg.h
1660
#define PCI_AER_ROOTERR_NF_ERR __BIT(5)
sys/dev/pci/pcireg.h
1661
#define PCI_AER_ROOTERR_F_ERR __BIT(6)
sys/dev/pci/pcireg.h
1681
#define PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME __BIT(0)
sys/dev/pci/pcireg.h
1682
#define PCI_VC_CAP2_ARB_CAP_WRR_32 __BIT(1)
sys/dev/pci/pcireg.h
1683
#define PCI_VC_CAP2_ARB_CAP_WRR_64 __BIT(2)
sys/dev/pci/pcireg.h
1684
#define PCI_VC_CAP2_ARB_CAP_WRR_128 __BIT(3)
sys/dev/pci/pcireg.h
1687
#define PCI_VC_CONTROL_LOAD_VC_ARB_TABLE __BIT(0)
sys/dev/pci/pcireg.h
1690
#define PCI_VC_STATUS_LOAD_VC_ARB_TABLE __BIT(0)
sys/dev/pci/pcireg.h
1692
#define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME __BIT(0)
sys/dev/pci/pcireg.h
1693
#define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32 __BIT(1)
sys/dev/pci/pcireg.h
1694
#define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64 __BIT(2)
sys/dev/pci/pcireg.h
1695
#define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128 __BIT(3)
sys/dev/pci/pcireg.h
1696
#define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128 __BIT(4)
sys/dev/pci/pcireg.h
1697
#define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256 __BIT(5)
sys/dev/pci/pcireg.h
1698
#define PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH __BIT(14)
sys/dev/pci/pcireg.h
1699
#define PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS __BIT(15)
sys/dev/pci/pcireg.h
1704
#define PCI_VC_RESOURCE_CTL_LOAD_PORT_ARB_TABLE __BIT(16)
sys/dev/pci/pcireg.h
1707
#define PCI_VC_RESOURCE_CTL_VC_ENABLE __BIT(31)
sys/dev/pci/pcireg.h
1709
#define PCI_VC_RESOURCE_STA_PORT_ARB_TABLE __BIT(0)
sys/dev/pci/pcireg.h
1710
#define PCI_VC_RESOURCE_STA_VC_NEG_PENDING __BIT(1)
sys/dev/pci/pcireg.h
1732
#define PCI_PWRBDGT_CAP_SYSALLOC __BIT(0) /* System Allocated */
sys/dev/pci/pcireg.h
1746
#define PCI_RCLINK_DCL_LINKDESC_LVALID __BIT(0) /* Link Valid */
sys/dev/pci/pcireg.h
1747
#define PCI_RCLINK_DCL_LINKDESC_LTYPE __BIT(1) /* Link Type */
sys/dev/pci/pcireg.h
1748
#define PCI_RCLINK_DCL_LINKDESC_ARCRBH __BIT(2) /* Associate RCRB Header */
sys/dev/pci/pcireg.h
1809
#define PCI_ACS_CAP_V __BIT(0) /* Source Validation */
sys/dev/pci/pcireg.h
1810
#define PCI_ACS_CAP_B __BIT(1) /* Transaction Blocking */
sys/dev/pci/pcireg.h
1811
#define PCI_ACS_CAP_R __BIT(2) /* P2P Request Redirect */
sys/dev/pci/pcireg.h
1812
#define PCI_ACS_CAP_C __BIT(3) /* P2P Completion Redirect */
sys/dev/pci/pcireg.h
1813
#define PCI_ACS_CAP_U __BIT(4) /* Upstream Forwarding */
sys/dev/pci/pcireg.h
1814
#define PCI_ACS_CAP_E __BIT(5) /* Egress Control */
sys/dev/pci/pcireg.h
1815
#define PCI_ACS_CAP_T __BIT(6) /* Direct Translated P2P */
sys/dev/pci/pcireg.h
1818
#define PCI_ACS_CTL_V __BIT(0 + 16) /* Source Validation Enable */
sys/dev/pci/pcireg.h
1819
#define PCI_ACS_CTL_B __BIT(1 + 16) /* Transaction Blocking Enable */
sys/dev/pci/pcireg.h
1820
#define PCI_ACS_CTL_R __BIT(2 + 16) /* P2P Request Redirect Enable */
sys/dev/pci/pcireg.h
1821
#define PCI_ACS_CTL_C __BIT(3 + 16) /* P2P Completion Redirect Enable */
sys/dev/pci/pcireg.h
1822
#define PCI_ACS_CTL_U __BIT(4 + 16) /* Upstream Forwarding Enable */
sys/dev/pci/pcireg.h
1823
#define PCI_ACS_CTL_E __BIT(5 + 16) /* Egress Control Enable */
sys/dev/pci/pcireg.h
1824
#define PCI_ACS_CTL_T __BIT(6 + 16) /* Direct Translated P2P Enable */
sys/dev/pci/pcireg.h
1832
#define PCI_ARI_CAP_M __BIT(0) /* MFVC Function Groups Cap. */
sys/dev/pci/pcireg.h
1833
#define PCI_ARI_CAP_A __BIT(1) /* ACS Function Groups Cap. */
sys/dev/pci/pcireg.h
1836
#define PCI_ARI_CTL_M __BIT(16) /* MFVC Function Groups Ena. */
sys/dev/pci/pcireg.h
1837
#define PCI_ARI_CTL_A __BIT(17) /* ACS Function Groups Ena. */
sys/dev/pci/pcireg.h
1846
#define PCI_ATS_CAP_PALIGNREQ __BIT(5) /* Page Aligned Request */
sys/dev/pci/pcireg.h
1847
#define PCI_ATS_CAP_GLOBALINVL __BIT(6) /* Global Invalidate Support */
sys/dev/pci/pcireg.h
1848
#define PCI_ATS_CAP_RELAXORD __BIT(7) /* Relaxed Ordering */
sys/dev/pci/pcireg.h
1851
#define PCI_ATS_CTL_EN __BIT(31) /* Enable */
sys/dev/pci/pcireg.h
1858
#define PCI_SRIOV_CAP_VF_MIGRATION __BIT(0)
sys/dev/pci/pcireg.h
1859
#define PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED __BIT(1)
sys/dev/pci/pcireg.h
1862
#define PCI_SRIOV_CTL_VF_ENABLE __BIT(0)
sys/dev/pci/pcireg.h
1863
#define PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT __BIT(1)
sys/dev/pci/pcireg.h
1864
#define PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE __BIT(2)
sys/dev/pci/pcireg.h
1865
#define PCI_SRIOV_CTL_VF_MSE __BIT(3)
sys/dev/pci/pcireg.h
1866
#define PCI_SRIOV_CTL_ARI_CAP_HIER __BIT(4)
sys/dev/pci/pcireg.h
1868
#define PCI_SRIOV_STA_VF_MIGRATION __BIT(0)
sys/dev/pci/pcireg.h
1897
#define PCI_MCAST_CAP_ECRCREGEN __BIT(15) /* ECRC Regen. Supported */
sys/dev/pci/pcireg.h
1900
#define PCI_MCAST_CTL_ENA __BIT(15+16) /* Enable */
sys/dev/pci/pcireg.h
1921
#define PCI_PAGE_REQ_CTL_E __BIT(0) /* Enable */
sys/dev/pci/pcireg.h
1922
#define PCI_PAGE_REQ_CTL_R __BIT(1) /* Reset */
sys/dev/pci/pcireg.h
1924
#define PCI_PAGE_REQ_STA_RF __BIT(0+16) /* Response Failure */
sys/dev/pci/pcireg.h
1925
#define PCI_PAGE_REQ_STA_UPRGI __BIT(1+16) /* Unexpected Page Req Grp Idx */
sys/dev/pci/pcireg.h
1926
#define PCI_PAGE_REQ_STA_S __BIT(8+16) /* Stopped */
sys/dev/pci/pcireg.h
1927
#define PCI_PAGE_REQ_STA_PASIDR __BIT(15+16) /* PRG Response PASID Required */
sys/dev/pci/pcireg.h
1974
#define PCI_EA_W __BIT(30) /* Writable */
sys/dev/pci/pcireg.h
1975
#define PCI_EA_E __BIT(31) /* Enable for this entry */
sys/dev/pci/pcireg.h
1978
#define PCI_EA_BASEMAXOFFSET_S __BIT(1) /* Field Size */
sys/dev/pci/pcireg.h
1979
#define PCI_EA_BASEMAXOFFSET_64BIT __BIT(1) /* 64bit */
sys/dev/pci/pcireg.h
2008
#define PCI_DPA_CS_SUBSTCTLEN __BIT(8) /* Substate Control Enabled */
sys/dev/pci/pcireg.h
2018
#define PCI_TPH_REQ_CAP_NOST __BIT(0) /* No ST Mode Supported */
sys/dev/pci/pcireg.h
2019
#define PCI_TPH_REQ_CAP_INTVEC __BIT(1) /* Intr Vec Mode Supported */
sys/dev/pci/pcireg.h
2020
#define PCI_TPH_REQ_CAP_DEVSPEC __BIT(2) /* Device Specific Mode Supported */
sys/dev/pci/pcireg.h
2021
#define PCI_TPH_REQ_CAP_XTPHREQ __BIT(8) /* Extend TPH Requester Supported */
sys/dev/pci/pcireg.h
2056
#define PCI_SECPCIE_LCTL3_PERFEQ __BIT(0) /* Perform Equalization */
sys/dev/pci/pcireg.h
2057
#define PCI_SECPCIE_LCTL3_LINKEQREQ_IE __BIT(1) /* Link Eq. Req. Int. Ena. */
sys/dev/pci/pcireg.h
2077
#define PCI_PASID_CAP_XPERM __BIT(1) /* Execute Permission Supported */
sys/dev/pci/pcireg.h
2078
#define PCI_PASID_CAP_PRIVMODE __BIT(2) /* Privileged Mode Supported */
sys/dev/pci/pcireg.h
2081
#define PCI_PASID_CTL_PASID_EN __BIT(0+16) /* PASID Enable */
sys/dev/pci/pcireg.h
2082
#define PCI_PASID_CTL_XPERM_EN __BIT(1+16) /* Execute Permission Enable */
sys/dev/pci/pcireg.h
2083
#define PCI_PASID_CTL_PRIVMODE_EN __BIT(2+16) /* Privileged Mode Enable */
sys/dev/pci/pcireg.h
2090
#define PCI_LNR_CAP_64 __BIT(0) /* LNR-64 Supported */
sys/dev/pci/pcireg.h
2091
#define PCI_LNR_CAP_128 __BIT(1) /* LNR-128 Supported */
sys/dev/pci/pcireg.h
2094
#define PCI_LNR_CTL_EN __BIT(0+16) /* LNR Enable */
sys/dev/pci/pcireg.h
2095
#define PCI_LNR_CTL_CLS __BIT(1+16) /* LNR CLS */
sys/dev/pci/pcireg.h
2105
#define PCI_DPCCAP_RPEXT __BIT(5) /* RP Extensions for DPC */
sys/dev/pci/pcireg.h
2106
#define PCI_DPCCAP_POISONTLPEB __BIT(6) /* Poisoned TLP Egress Blckng.*/
sys/dev/pci/pcireg.h
2107
#define PCI_DPCCAP_SWTRIG __BIT(7) /* DPC Software Triggering */
sys/dev/pci/pcireg.h
2109
#define PCI_DPCCAP_DLACTECORS __BIT(12) /* DL_Active ERR_COR Signaling*/
sys/dev/pci/pcireg.h
2111
#define PCI_DPCCTL_COMPCTL __BIT(18) /* DPC Completion Control */
sys/dev/pci/pcireg.h
2112
#define PCI_DPCCTL_IE __BIT(19) /* DPC Interrupt Enable */
sys/dev/pci/pcireg.h
2113
#define PCI_DPCCTL_ERRCOREN __BIT(20) /* DPC ERR_COR enable */
sys/dev/pci/pcireg.h
2114
#define PCI_DPCCTL_POISONTLPEB __BIT(21) /* Poisoned TLP Egress Blckng.*/
sys/dev/pci/pcireg.h
2115
#define PCI_DPCCTL_SWTRIG __BIT(22) /* DPC Software Trigger */
sys/dev/pci/pcireg.h
2116
#define PCI_DPCCTL_DLACTECOR __BIT(23) /* DL_Active ERR_COR Enable */
sys/dev/pci/pcireg.h
2119
#define PCI_DPCSTAT_TSTAT __BIT(0) /* DPC Trigger Status */
sys/dev/pci/pcireg.h
2121
#define PCI_DPCSTAT_ISTAT __BIT(3) /* DPC Interrupt Status */
sys/dev/pci/pcireg.h
2122
#define PCI_DPCSTAT_RPBUSY __BIT(4) /* DPC RP Busy */
sys/dev/pci/pcireg.h
2128
#define PCI_DPC_RPPIO_CFGUR_CPL __BIT(0) /* CfgReq received UR Complt. */
sys/dev/pci/pcireg.h
2129
#define PCI_DPC_RPPIO_CFGCA_CPL __BIT(1) /* CfgReq received CA Complt. */
sys/dev/pci/pcireg.h
2130
#define PCI_DPC_RPPIO_CFG_CTO __BIT(2) /* CfgReq Completion Timeout */
sys/dev/pci/pcireg.h
2131
#define PCI_DPC_RPPIO_IOUR_CPL __BIT(8) /* I/OReq received UR Complt. */
sys/dev/pci/pcireg.h
2132
#define PCI_DPC_RPPIO_IOCA_CPL __BIT(9) /* I/OReq received CA Complt. */
sys/dev/pci/pcireg.h
2133
#define PCI_DPC_RPPIO_IO_CTO __BIT(10) /* I/OReq Completion Timeout */
sys/dev/pci/pcireg.h
2134
#define PCI_DPC_RPPIO_MEMUR_CPL __BIT(16) /* MemReq received UR Complt. */
sys/dev/pci/pcireg.h
2135
#define PCI_DPC_RPPIO_MEMCA_CPL __BIT(17) /* MemReq received CA Complt. */
sys/dev/pci/pcireg.h
2136
#define PCI_DPC_RPPIO_MEM_CTO __BIT(18) /* MemReq Completion Timeout */
sys/dev/pci/pcireg.h
2155
#define PCI_L1PM_CAP_PCIPM12 __BIT(0) /* PCI-PM L1.2 Supported */
sys/dev/pci/pcireg.h
2156
#define PCI_L1PM_CAP_PCIPM11 __BIT(1) /* PCI-PM L1.1 Supported */
sys/dev/pci/pcireg.h
2157
#define PCI_L1PM_CAP_ASPM12 __BIT(2) /* ASPM L1.2 Supported */
sys/dev/pci/pcireg.h
2158
#define PCI_L1PM_CAP_ASPM11 __BIT(3) /* ASPM L1.1 Supported */
sys/dev/pci/pcireg.h
2159
#define PCI_L1PM_CAP_L1PM __BIT(4) /* L1 PM Substates Supported */
sys/dev/pci/pcireg.h
2160
#define PCI_L1PM_CAP_LA __BIT(5) /* Link Activation Supported */
sys/dev/pci/pcireg.h
2165
#define PCI_L1PM_CTL1_PCIPM12_EN __BIT(0) /* PCI-PM L1.2 Enable */
sys/dev/pci/pcireg.h
2166
#define PCI_L1PM_CTL1_PCIPM11_EN __BIT(1) /* PCI-PM L1.1 Enable */
sys/dev/pci/pcireg.h
2167
#define PCI_L1PM_CTL1_ASPM12_EN __BIT(2) /* ASPM L1.2 Enable */
sys/dev/pci/pcireg.h
2168
#define PCI_L1PM_CTL1_ASPM11_EN __BIT(3) /* ASPM L1.1 Enable */
sys/dev/pci/pcireg.h
2169
#define PCI_L1PM_CTL1_LAIE __BIT(4) /* Link Activation Int. En. */
sys/dev/pci/pcireg.h
2170
#define PCI_L1PM_CTL1_LA __BIT(5) /* Link Activation Control */
sys/dev/pci/pcireg.h
2178
#define PCI_L1PM_STAT_LA __BIT(0) /* Link Activation Status */
sys/dev/pci/pcireg.h
2185
#define PCI_PTM_CAP_REQ __BIT(0) /* PTM Requester Capable */
sys/dev/pci/pcireg.h
2186
#define PCI_PTM_CAP_RESP __BIT(1) /* PTM Responder Capable */
sys/dev/pci/pcireg.h
2187
#define PCI_PTM_CAP_ROOT __BIT(2) /* PTM Root Capable */
sys/dev/pci/pcireg.h
2190
#define PCI_PTM_CTL_EN __BIT(0) /* PTM Enable */
sys/dev/pci/pcireg.h
2191
#define PCI_PTM_CTL_ROOTSEL __BIT(1) /* Root Select */
sys/dev/pci/pcireg.h
2225
#define PCI_DLF_LFEAT_SCLFCTL __BIT(0) /* Scaled Flow Control */
sys/dev/pci/pcireg.h
2226
#define PCI_DLF_CAP_XCHG __BIT(31) /* DLF Exchange enable */
sys/dev/pci/pcireg.h
2229
#define PCI_DLF_STAT_RMTVALID __BIT(31) /* Remote DLF supported Valid */
sys/dev/pci/pcireg.h
2238
#define PCI_PL16G_STAT_EQ_COMPL __BIT(0) /* Equalization 16.0 GT/s Complete */
sys/dev/pci/pcireg.h
2239
#define PCI_PL16G_STAT_EQ_P1S __BIT(1) /* Eq. 16.0 GT/s Phase 1 Successful */
sys/dev/pci/pcireg.h
2240
#define PCI_PL16G_STAT_EQ_P2S __BIT(2) /* Eq. 16.0 GT/s Phase 2 Successful */
sys/dev/pci/pcireg.h
2241
#define PCI_PL16G_STAT_EQ_P3S __BIT(3) /* Eq. 16.0 GT/s Phase 3 Successful */
sys/dev/pci/pcireg.h
2242
#define PCI_PL16G_STAT_LEQR __BIT(4) /* Link Eq. Request 16.0 GT/s */
sys/dev/pci/pcireg.h
2254
#define PCI_LMR_PCAP_MUDS __BIT(0) /* Margining uses Driver Software */
sys/dev/pci/pcireg.h
2255
#define PCI_LMR_PSTAT_MR __BIT(16) /* Margining Ready */
sys/dev/pci/pcireg.h
2256
#define PCI_LMR_PSTAT_MSR __BIT(17) /* Margining Software Ready */
sys/dev/pci/pcireg.h
2260
#define PCI_LMR_LCTL_UMODEL __BIT(6) /* Usage Model */
sys/dev/pci/pcireg.h
2264
#define PCI_LMR_LSTAT_UMODEL __BIT(22) /* Usage Model */
sys/dev/pci/pcireg.h
655
#define AGP_MODE_SBA __BIT(9)
sys/dev/pci/pcireg.h
656
#define AGP_MODE_AGP __BIT(8)
sys/dev/pci/pcireg.h
657
#define AGP_MODE_HTRANS __BIT(6)
sys/dev/pci/pcireg.h
658
#define AGP_MODE_4G __BIT(5)
sys/dev/pci/pcireg.h
659
#define AGP_MODE_FW __BIT(4)
sys/dev/pci/pcireg.h
660
#define AGP_MODE_MODE_3 __BIT(3)
sys/dev/pci/pcireg.h
713
#define PCI_MSI_CTL_EXTMDATA_EN __SHIFTIN(__BIT(10), PCI_MSI_CTL_MASK)
sys/dev/pci/pcireg.h
714
#define PCI_MSI_CTL_EXTMDATA_CAP __SHIFTIN(__BIT(9), PCI_MSI_CTL_MASK)
sys/dev/pci/pcireg.h
715
#define PCI_MSI_CTL_PERVEC_MASK __SHIFTIN(__BIT(8), PCI_MSI_CTL_MASK)
sys/dev/pci/pcireg.h
716
#define PCI_MSI_CTL_64BIT_ADDR __SHIFTIN(__BIT(7), PCI_MSI_CTL_MASK)
sys/dev/pci/pcireg.h
721
#define PCI_MSI_CTL_MSI_ENABLE __SHIFTIN(__BIT(0), PCI_MSI_CTL_MASK)
sys/dev/pci/pcireg.h
73
#define PCI_CONF_TYPE0_IDSEL(d) __BIT((d) + 11)
sys/dev/pci/pcireg.h
888
#define PCI_HT_MSI_ENABLED __BIT(16)
sys/dev/pci/pcireg.h
889
#define PCI_HT_MSI_FIXED __BIT(17)
sys/dev/pci/pcireg.h
949
#define PCI_SECURE_CAP_IOTLBSUP __BIT(24) /* IOTLB */
sys/dev/pci/pcireg.h
950
#define PCI_SECURE_CAP_HTTUNNEL __BIT(25) /* HT tunnel translation */
sys/dev/pci/pcireg.h
951
#define PCI_SECURE_CAP_NPCACHE __BIT(26) /* Not present table entries cached */
sys/dev/pci/pcireg.h
952
#define PCI_SECURE_CAP_EFRSUP __BIT(27) /* IOMMU Ext-Feature Reg */
sys/dev/pci/pcireg.h
953
#define PCI_SECURE_CAP_EXT __BIT(28) /* IOMMU Misc Info Reg 1 */
sys/dev/pci/pcireg.h
955
#define PCI_SECURE_IOMMU_BAL_EN __BIT(0) /* Enable */
sys/dev/pci/pcireg.h
961
#define PCI_SECURE_IOMMU_RANGE_RNGVALID __BIT(7) /* Range valid */
sys/dev/pci/pcireg.h
971
#define PCI_SECURE_IOMMU_MISC0_ATSRESV __BIT(22) /* ATS resp addr range rsvd */
sys/dev/pci/pcireg.h
998
#define PCIE_XCAP_SI __SHIFTIN(__BIT(8), PCIE_XCAP_MASK) /* Slot Implemented */
sys/dev/pci/pcivar.h
219
#define PCI_QUIRK_MULTIFUNCTION __BIT(0)
sys/dev/pci/pcivar.h
220
#define PCI_QUIRK_MONOFUNCTION __BIT(1)
sys/dev/pci/pcivar.h
230
#define PCI_QUIRK_HASEXTCNF __BIT(10)
sys/dev/pci/pcivar.h
231
#define PCI_QUIRK_NOEXTCNF __BIT(11)
sys/dev/pci/pcivar.h
64
PCI_OVERRIDE_CONF_READ = __BIT(0)
sys/dev/pci/pcivar.h
65
, PCI_OVERRIDE_CONF_WRITE = __BIT(1)
sys/dev/pci/pcivar.h
66
, PCI_OVERRIDE_INTR_MAP = __BIT(2)
sys/dev/pci/pcivar.h
67
, PCI_OVERRIDE_INTR_STRING = __BIT(3)
sys/dev/pci/pcivar.h
68
, PCI_OVERRIDE_INTR_EVCNT = __BIT(4)
sys/dev/pci/pcivar.h
69
, PCI_OVERRIDE_INTR_ESTABLISH = __BIT(5)
sys/dev/pci/pcivar.h
70
, PCI_OVERRIDE_INTR_DISESTABLISH = __BIT(6)
sys/dev/pci/pcivar.h
71
, PCI_OVERRIDE_MAKE_TAG = __BIT(7)
sys/dev/pci/pcivar.h
72
, PCI_OVERRIDE_DECOMPOSE_TAG = __BIT(8)
sys/dev/pci/piixpmreg.h
128
#define SB800_PM_SMBUS0EN_ENABLE __BIT(0) /* Function enable */
sys/dev/pci/piixpmreg.h
135
#define SB800_PM_USE_SMBUS0SEL __BIT(0) /*
sys/dev/pci/qat/qat_c3xxxreg.h
103
#define ERRMSK0_CERR_C3XXX (__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
sys/dev/pci/qat/qat_c3xxxreg.h
104
#define ERRMSK1_CERR_C3XXX (__BIT(8) | __BIT(0))
sys/dev/pci/qat/qat_c3xxxreg.h
108
#define ERRMSK0_UERR_C3XXX (__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
sys/dev/pci/qat/qat_c3xxxreg.h
109
#define ERRMSK1_UERR_C3XXX (__BIT(9) | __BIT(1))
sys/dev/pci/qat/qat_c3xxxreg.h
110
#define ERRMSK3_UERR_C3XXX (__BIT(6) | __BIT(5) | __BIT(4) | __BIT(3) | \
sys/dev/pci/qat/qat_c3xxxreg.h
111
__BIT(2) | __BIT(0))
sys/dev/pci/qat/qat_c3xxxreg.h
112
#define ERRMSK5_UERR_C3XXX (__BIT(16))
sys/dev/pci/qat/qat_c3xxxreg.h
121
#define RICPP_EN_C3XXX (__BIT(2) | __BIT(1) | __BIT(0))
sys/dev/pci/qat/qat_c3xxxreg.h
132
(__BIT(3) | __BIT(2) | __BIT(1) | __BIT(0))
sys/dev/pci/qat/qat_c3xxxreg.h
140
#define CPP_CFC_UE_C3XXX (__BIT(1) | __BIT(0))
sys/dev/pci/qat/qat_c3xxxreg.h
145
(__BIT(20) | __BIT(19) | __BIT(18) | __BIT(17) | __BIT(16))
sys/dev/pci/qat/qat_c3xxxreg.h
151
(__BIT(11) | __BIT(9) | __BIT(7) | __BIT(5) | __BIT(3) | __BIT(1))
sys/dev/pci/qat/qat_c3xxxreg.h
155
#define CERRSSMMMP_EN_C3XXX (__BIT(3))
sys/dev/pci/qat/qat_c3xxxreg.h
158
#define UERRSSMMMP_EN_C3XXX (__BIT(3))
sys/dev/pci/qat/qat_c3xxxreg.h
76
#define SOFTSTRAP_SS_POWERGATE_CY_C3XXX __BIT(23)
sys/dev/pci/qat/qat_c3xxxreg.h
77
#define SOFTSTRAP_SS_POWERGATE_PKE_C3XXX __BIT(24)
sys/dev/pci/qat/qat_c3xxxreg.h
91
#define ENABLE_AE_ECC_ERR_C3XXX __BIT(28)
sys/dev/pci/qat/qat_c3xxxreg.h
92
#define ENABLE_AE_ECC_PARITY_CORR_C3XXX (__BIT(24) | __BIT(12))
sys/dev/pci/qat/qat_c3xxxreg.h
93
#define ERRSSMSH_EN_C3XXX __BIT(3)
sys/dev/pci/qat/qat_c3xxxreg.h
95
#define PPERR_EN_C3XXX (__BIT(2))
sys/dev/pci/qat/qat_c62xreg.h
103
#define ERRMSK0_CERR_C62X (__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
sys/dev/pci/qat/qat_c62xreg.h
104
#define ERRMSK1_CERR_C62X (__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
sys/dev/pci/qat/qat_c62xreg.h
105
#define ERRMSK3_CERR_C62X (__BIT(7))
sys/dev/pci/qat/qat_c62xreg.h
106
#define ERRMSK4_CERR_C62X (__BIT(8) | __BIT(0))
sys/dev/pci/qat/qat_c62xreg.h
110
#define ERRMSK0_UERR_C62X (__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
sys/dev/pci/qat/qat_c62xreg.h
111
#define ERRMSK1_UERR_C62X (__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
sys/dev/pci/qat/qat_c62xreg.h
112
#define ERRMSK3_UERR_C62X (__BIT(8) | __BIT(6) | __BIT(5) | __BIT(4) | \
sys/dev/pci/qat/qat_c62xreg.h
113
__BIT(3) | __BIT(2) | __BIT(0))
sys/dev/pci/qat/qat_c62xreg.h
114
#define ERRMSK4_UERR_C62X (__BIT(9) | __BIT(1))
sys/dev/pci/qat/qat_c62xreg.h
115
#define ERRMSK5_UERR_C62X (__BIT(18) | __BIT(17) | __BIT(16))
sys/dev/pci/qat/qat_c62xreg.h
124
#define RICPP_EN_C62X (__BIT(2) | __BIT(1) | __BIT(0))
sys/dev/pci/qat/qat_c62xreg.h
135
(__BIT(4) | __BIT(3) | __BIT(2) | __BIT(1) | __BIT(0))
sys/dev/pci/qat/qat_c62xreg.h
143
#define CPP_CFC_UE_C62X (__BIT(1) | __BIT(0))
sys/dev/pci/qat/qat_c62xreg.h
148
#define SECRAM_CERR_C62X (__BIT(3))
sys/dev/pci/qat/qat_c62xreg.h
155
#define SECRAM_UERR_C62X (__BIT(17) | __BIT(3))
sys/dev/pci/qat/qat_c62xreg.h
162
#define TGT_UERR_C62X (__BIT(3) | __BIT(2))
sys/dev/pci/qat/qat_c62xreg.h
168
(__BIT(20) | __BIT(19) | __BIT(18) | __BIT(17) | __BIT(16))
sys/dev/pci/qat/qat_c62xreg.h
174
(__BIT(11) | __BIT(9) | __BIT(7) | __BIT(5) | __BIT(3) | __BIT(1))
sys/dev/pci/qat/qat_c62xreg.h
178
#define CERRSSMMMP_EN_C62X (__BIT(3))
sys/dev/pci/qat/qat_c62xreg.h
181
#define UERRSSMMMP_EN_C62X (__BIT(3))
sys/dev/pci/qat/qat_c62xreg.h
76
#define SOFTSTRAP_SS_POWERGATE_CY_C62X __BIT(23)
sys/dev/pci/qat/qat_c62xreg.h
77
#define SOFTSTRAP_SS_POWERGATE_PKE_C62X __BIT(24)
sys/dev/pci/qat/qat_c62xreg.h
91
#define ENABLE_AE_ECC_ERR_C62X __BIT(28)
sys/dev/pci/qat/qat_c62xreg.h
92
#define ENABLE_AE_ECC_PARITY_CORR_C62X (__BIT(24) | __BIT(12))
sys/dev/pci/qat/qat_c62xreg.h
93
#define ERRSSMSH_EN_C62X __BIT(3)
sys/dev/pci/qat/qat_c62xreg.h
95
#define PPERR_EN_C62X (__BIT(2))
sys/dev/pci/qat/qat_d15xxreg.h
103
#define ERRMSK0_CERR_D15XX (__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
sys/dev/pci/qat/qat_d15xxreg.h
104
#define ERRMSK1_CERR_D15XX (__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
sys/dev/pci/qat/qat_d15xxreg.h
105
#define ERRMSK3_CERR_D15XX (__BIT(7))
sys/dev/pci/qat/qat_d15xxreg.h
106
#define ERRMSK4_CERR_D15XX (__BIT(8) | __BIT(0))
sys/dev/pci/qat/qat_d15xxreg.h
110
#define ERRMSK0_UERR_D15XX (__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
sys/dev/pci/qat/qat_d15xxreg.h
111
#define ERRMSK1_UERR_D15XX (__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
sys/dev/pci/qat/qat_d15xxreg.h
112
#define ERRMSK3_UERR_D15XX (__BIT(8) | __BIT(6) | __BIT(5) | __BIT(4) | \
sys/dev/pci/qat/qat_d15xxreg.h
113
__BIT(3) | __BIT(2) | __BIT(0))
sys/dev/pci/qat/qat_d15xxreg.h
114
#define ERRMSK4_UERR_D15XX (__BIT(9) | __BIT(1))
sys/dev/pci/qat/qat_d15xxreg.h
115
#define ERRMSK5_UERR_D15XX (__BIT(18) | __BIT(17) | __BIT(16))
sys/dev/pci/qat/qat_d15xxreg.h
124
#define RICPP_EN_D15XX (__BIT(2) | __BIT(1) | __BIT(0))
sys/dev/pci/qat/qat_d15xxreg.h
135
(__BIT(4) | __BIT(3) | __BIT(2) | __BIT(1) | __BIT(0))
sys/dev/pci/qat/qat_d15xxreg.h
143
#define CPP_CFC_UE_D15XX (__BIT(1) | __BIT(0))
sys/dev/pci/qat/qat_d15xxreg.h
148
#define SECRAM_CERR_D15XX (__BIT(3))
sys/dev/pci/qat/qat_d15xxreg.h
155
#define SECRAM_UERR_D15XX (__BIT(17) | __BIT(3))
sys/dev/pci/qat/qat_d15xxreg.h
162
#define TGT_UERR_D15XX (__BIT(3) | __BIT(2))
sys/dev/pci/qat/qat_d15xxreg.h
168
(__BIT(20) | __BIT(19) | __BIT(18) | __BIT(17) | __BIT(16))
sys/dev/pci/qat/qat_d15xxreg.h
174
(__BIT(11) | __BIT(9) | __BIT(7) | __BIT(5) | __BIT(3) | __BIT(1))
sys/dev/pci/qat/qat_d15xxreg.h
178
#define CERRSSMMMP_EN_D15XX (__BIT(3))
sys/dev/pci/qat/qat_d15xxreg.h
181
#define UERRSSMMMP_EN_D15XX (__BIT(3))
sys/dev/pci/qat/qat_d15xxreg.h
76
#define SOFTSTRAP_SS_POWERGATE_CY_D15XX __BIT(23)
sys/dev/pci/qat/qat_d15xxreg.h
77
#define SOFTSTRAP_SS_POWERGATE_PKE_D15XX __BIT(24)
sys/dev/pci/qat/qat_d15xxreg.h
91
#define ENABLE_AE_ECC_ERR_D15XX __BIT(28)
sys/dev/pci/qat/qat_d15xxreg.h
92
#define ENABLE_AE_ECC_PARITY_CORR_D15XX (__BIT(24) | __BIT(12))
sys/dev/pci/qat/qat_d15xxreg.h
93
#define ERRSSMSH_EN_D15XX __BIT(3)
sys/dev/pci/qat/qat_d15xxreg.h
95
#define PPERR_EN_D15XX (__BIT(2))
sys/dev/pci/qat/qat_hw15reg.h
406
#define COMN_RESP_CRYPTO_STATUS __BIT(7)
sys/dev/pci/qat/qat_hw15reg.h
407
#define COMN_RESP_PKE_STATUS __BIT(6)
sys/dev/pci/qat/qat_hw15reg.h
408
#define COMN_RESP_CMP_STATUS __BIT(5)
sys/dev/pci/qat/qat_hw15reg.h
409
#define COMN_RESP_XLAT_STATUS __BIT(4)
sys/dev/pci/qat/qat_hw15reg.h
410
#define COMN_RESP_PM_STATUS __BIT(3)
sys/dev/pci/qat/qat_hw15reg.h
411
#define COMN_RESP_INIT_ADMIN_STATUS __BIT(2)
sys/dev/pci/qat/qat_hw15reg.h
536
#define LA_FLAGS_GCM_IV_LEN_FLAG __BIT(9)
sys/dev/pci/qat/qat_hw15reg.h
542
#define LA_FLAGS_DIGEST_IN_BUFFER __BIT(5)
sys/dev/pci/qat/qat_hw15reg.h
543
#define LA_FLAGS_CMP_AUTH_RES __BIT(4)
sys/dev/pci/qat/qat_hw15reg.h
544
#define LA_FLAGS_RET_AUTH_RES __BIT(3)
sys/dev/pci/qat/qat_hw15reg.h
545
#define LA_FLAGS_UPDATE_STATE __BIT(2)
sys/dev/pci/qat/qat_hw15reg.h
73
#define ARCH_IF_FLAGS_VALID_FLAG __BIT(7)
sys/dev/pci/qat/qat_hw17reg.h
1216
#define FW_LA_ZUC_3G_PROTO __BIT(12)
sys/dev/pci/qat/qat_hw17reg.h
1220
#define FW_LA_GCM_IV_LEN_12_OCTETS __BIT(11)
sys/dev/pci/qat/qat_hw17reg.h
1224
#define FW_LA_DIGEST_IN_BUFFER __BIT(10)
sys/dev/pci/qat/qat_hw17reg.h
1238
#define FW_LA_CMP_AUTH_RES __BIT(6)
sys/dev/pci/qat/qat_hw17reg.h
1242
#define FW_LA_RET_AUTH_RES __BIT(5)
sys/dev/pci/qat/qat_hw17reg.h
1246
#define FW_LA_UPDATE_STATE __BIT(4)
sys/dev/pci/qat/qat_hw17reg.h
1250
#define FW_CIPH_AUTH_CFG_OFFSET_IN_SHRAM_CP __BIT(3)
sys/dev/pci/qat/qat_hw17reg.h
1257
#define FW_CIPH_IV_16BYTE_DATA __BIT(2)
sys/dev/pci/qat/qat_hw17reg.h
556
#define FW_COMN_VALID __BIT(7)
sys/dev/pci/qat/qatreg.h
100
#define FUSECTL_MASK __BIT(31)
sys/dev/pci/qat/qatreg.h
103
#define LEGFUSE_ACCEL_MASK_CIPHER_SLICE __BIT(0)
sys/dev/pci/qat/qatreg.h
104
#define LEGFUSE_ACCEL_MASK_AUTH_SLICE __BIT(1)
sys/dev/pci/qat/qatreg.h
105
#define LEGFUSE_ACCEL_MASK_PKE_SLICE __BIT(2)
sys/dev/pci/qat/qatreg.h
106
#define LEGFUSE_ACCEL_MASK_COMPRESS_SLICE __BIT(3)
sys/dev/pci/qat/qatreg.h
107
#define LEGFUSE_ACCEL_MASK_LZS_SLICE __BIT(4)
sys/dev/pci/qat/qatreg.h
108
#define LEGFUSE_ACCEL_MASK_EIA3_SLICE __BIT(5)
sys/dev/pci/qat/qatreg.h
109
#define LEGFUSE_ACCEL_MASK_SHA3_SLICE __BIT(6)
sys/dev/pci/qat/qatreg.h
1352
#define HW_AUTH_CONFIG_SHA3_PADDING __BIT(16)
sys/dev/pci/qat/qatreg.h
1461
#define CIPHER_CONFIG_CONVERT __BIT(9)
sys/dev/pci/qat/qatreg.h
1462
#define CIPHER_CONFIG_DIR __BIT(8)
sys/dev/pci/qat/qatreg.h
153
#define ETR_RING_CONFIG_LATE_HEAD_POINTER_MODE __BIT(31)
sys/dev/pci/qat/qatreg.h
226
#define ETR_INT_COL_CTL_ENABLE __BIT(31)
sys/dev/pci/qat/qatreg.h
232
#define ETR_AP_DEST_ENABLE __BIT(7)
sys/dev/pci/qat/qatreg.h
281
#define FCU_STATUS_AUTHFWLD __BIT(8)
sys/dev/pci/qat/qatreg.h
282
#define FCU_STATUS_DONE __BIT(9)
sys/dev/pci/qat/qatreg.h
297
#define CAP_GLOBAL_CTL_MISC_TIMESTAMP_EN __BIT(7)
sys/dev/pci/qat/qatreg.h
317
#define USTORE_ADDRESS_ECS __BIT(31)
sys/dev/pci/qat/qatreg.h
341
#define CTX_ENABLES_INUSE_CONTEXTS __BIT(31)
sys/dev/pci/qat/qatreg.h
342
#define CTX_ENABLES_CNTL_STORE_PARITY_ERROR __BIT(29)
sys/dev/pci/qat/qatreg.h
343
#define CTX_ENABLES_CNTL_STORE_PARITY_ENABLE __BIT(28)
sys/dev/pci/qat/qatreg.h
344
#define CTX_ENABLES_BREAKPOINT __BIT(27)
sys/dev/pci/qat/qatreg.h
345
#define CTX_ENABLES_PAR_ERR __BIT(25)
sys/dev/pci/qat/qatreg.h
346
#define CTX_ENABLES_NN_MODE __BIT(20)
sys/dev/pci/qat/qatreg.h
347
#define CTX_ENABLES_NN_RING_EMPTY __BIT(18)
sys/dev/pci/qat/qatreg.h
348
#define CTX_ENABLES_LMADDR_1_GLOBAL __BIT(17)
sys/dev/pci/qat/qatreg.h
349
#define CTX_ENABLES_LMADDR_0_GLOBAL __BIT(16)
sys/dev/pci/qat/qatreg.h
375
#define ACTIVE_CTX_STATUS_ABO __BIT(31)
sys/dev/pci/qat/qatreg.h
445
#define AE_MISC_CONTROL_PARITY_ENABLE __BIT(24)
sys/dev/pci/qat/qatreg.h
446
#define AE_MISC_CONTROL_FORCE_BAD_PARITY __BIT(23)
sys/dev/pci/qat/qatreg.h
447
#define AE_MISC_CONTROL_ONE_CTX_RELOAD __BIT(22)
sys/dev/pci/qat/qatreg.h
449
#define AE_MISC_CONTROL_SHARE_CS __BIT(2)
sys/dev/pci/qat/qatreg.h
469
#define INTSTATSSM_SHANGERR __BIT(13)
sys/dev/pci/qat/qatreg.h
476
#define SLICE_HANG_AUTH0_MASK __BIT(0)
sys/dev/pci/qat/qatreg.h
477
#define SLICE_HANG_AUTH1_MASK __BIT(1)
sys/dev/pci/qat/qatreg.h
478
#define SLICE_HANG_CPHR0_MASK __BIT(4)
sys/dev/pci/qat/qatreg.h
479
#define SLICE_HANG_CPHR1_MASK __BIT(5)
sys/dev/pci/qat/qatreg.h
480
#define SLICE_HANG_CMP0_MASK __BIT(8)
sys/dev/pci/qat/qatreg.h
481
#define SLICE_HANG_CMP1_MASK __BIT(9)
sys/dev/pci/qat/qatreg.h
482
#define SLICE_HANG_XLT0_MASK __BIT(12)
sys/dev/pci/qat/qatreg.h
483
#define SLICE_HANG_XLT1_MASK __BIT(13)
sys/dev/pci/qat/qatreg.h
484
#define SLICE_HANG_MMP0_MASK __BIT(16)
sys/dev/pci/qat/qatreg.h
485
#define SLICE_HANG_MMP1_MASK __BIT(17)
sys/dev/pci/qat/qatreg.h
486
#define SLICE_HANG_MMP2_MASK __BIT(18)
sys/dev/pci/qat/qatreg.h
487
#define SLICE_HANG_MMP3_MASK __BIT(19)
sys/dev/pci/qat/qatreg.h
488
#define SLICE_HANG_MMP4_MASK __BIT(20)
sys/dev/pci/qat/qatreg.h
513
#define EMSK3_CPM0_MASK __BIT(2)
sys/dev/pci/qat/qatreg.h
514
#define EMSK3_CPM1_MASK __BIT(3)
sys/dev/pci/qat/qatreg.h
515
#define EMSK5_CPM2_MASK __BIT(16)
sys/dev/pci/qat/qatreg.h
516
#define EMSK5_CPM3_MASK __BIT(17)
sys/dev/pci/qat/qatreg.h
517
#define EMSK5_CPM4_MASK __BIT(18)
sys/dev/pci/qat/qatreg.h
968
#define AE_MODE_RELOAD_CTX_SHARED __BIT(12)
sys/dev/pci/qat/qatreg.h
969
#define AE_MODE_SHARED_USTORE __BIT(11)
sys/dev/pci/qat/qatreg.h
970
#define AE_MODE_LMEM1 __BIT(9)
sys/dev/pci/qat/qatreg.h
971
#define AE_MODE_LMEM0 __BIT(8)
sys/dev/pci/qat/qatvar.h
867
#define QAT_DUMP_DESC __BIT(0)
sys/dev/pci/qat/qatvar.h
868
#define QAT_DUMP_RING __BIT(1)
sys/dev/pci/qat/qatvar.h
869
#define QAT_DUMP_RING_MSG __BIT(2)
sys/dev/pci/qat/qatvar.h
870
#define QAT_DUMP_PCI __BIT(3)
sys/dev/pci/qat/qatvar.h
871
#define QAT_DUMP_AEFW __BIT(4)
sys/dev/pci/sdhc_pci.c
84
#define SDHC_PCI_QUIRK_FORCE_DMA __BIT(0)
sys/dev/pci/sdhc_pci.c
85
#define SDHC_PCI_QUIRK_TI_HACK __BIT(1)
sys/dev/pci/sdhc_pci.c
86
#define SDHC_PCI_QUIRK_NO_PWR0 __BIT(2)
sys/dev/pci/sdhc_pci.c
87
#define SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK __BIT(3)
sys/dev/pci/sdhc_pci.c
88
#define SDHC_PCI_QUIRK_RICOH_SLOW_SDR50_HACK __BIT(4)
sys/dev/pci/sdhc_pci.c
89
#define SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET __BIT(5)
sys/dev/pci/sdhc_pci.c
90
#define SDHC_PCI_QUIRK_SINGLE_POWER_WRITE __BIT(6)
sys/dev/pci/sdhc_pci.c
91
#define SDHC_PCI_QUIRK_BROKEN_ADMA __BIT(7)
sys/dev/pci/tdvfbreg.h
105
#define TDV_FBIINIT2_FAST_RAS __BIT(5)
sys/dev/pci/tdvfbreg.h
106
#define TDV_FBIINIT2_DRAM_OE __BIT(6)
sys/dev/pci/tdvfbreg.h
108
#define TDV_FBIINIT2_FIFO_RDA __BIT(21)
sys/dev/pci/tdvfbreg.h
109
#define TDV_FBIINIT2_DRAM_REFR __BIT(22)
sys/dev/pci/tdvfbreg.h
114
#define TDV_FBIINIT3_TREX_DIS __BIT(6)
sys/dev/pci/tdvfbreg.h
117
#define TDV_FBIINIT4_PCIWAIT __BIT(0)
sys/dev/pci/tdvfbreg.h
118
#define TDV_FBIINIT4_LFB_RDA __BIT(1)
sys/dev/pci/tdvfbreg.h
126
#define TDV_DAC_DATA_READ __BIT(11)
sys/dev/pci/tdvfbreg.h
130
#define TDV_FBIINIT5_PHSYNC __BIT(23)
sys/dev/pci/tdvfbreg.h
131
#define TDV_FBIINIT5_PVSYNC __BIT(24)
sys/dev/pci/tdvfbreg.h
155
#define TDV_BLTCMD_LAUNCH __BIT(31)
sys/dev/pci/tdvfbreg.h
157
#define TDV_BLTCMD_CLIPRECT __BIT(16)
sys/dev/pci/tdvfbreg.h
158
#define TDV_BLTCMD_DSTTILED __BIT(15)
sys/dev/pci/tdvfbreg.h
184
#define TDV_GENDAC_CMD_PWDOWN __BIT(0)
sys/dev/pci/tdvfbreg.h
191
#define TDV_GENDAC_PLL_VIDCLK __BIT(5)
sys/dev/pci/tdvfbreg.h
43
#define TDV_INITENABLE_EN_INIT __BIT(0)
sys/dev/pci/tdvfbreg.h
44
#define TDV_INITENABLE_EN_FIFO __BIT(1)
sys/dev/pci/tdvfbreg.h
45
#define TDV_INITENABLE_REMAPDAC __BIT(2)
sys/dev/pci/tdvfbreg.h
56
#define TDV_STATUS_FBI_BUSY __BIT(7) /* FBI == CVG Bruce */
sys/dev/pci/tdvfbreg.h
57
#define TDV_STATUS_TREX_BUSY __BIT(8) /* TREX == CVG Chuck */
sys/dev/pci/tdvfbreg.h
58
#define TDV_STATUS_GFX_BUSY __BIT(9)
sys/dev/pci/tdvfbreg.h
63
#define TDV_FBZMODE_CLIPPING __BIT(0)
sys/dev/pci/tdvfbreg.h
64
#define TDV_FBZMODE_RGB_WR __BIT(9)
sys/dev/pci/tdvfbreg.h
65
#define TDV_FBZMODE_ALPHA_WR __BIT(10)
sys/dev/pci/tdvfbreg.h
66
#define TDV_FBZMODE_INVERT_Y __BIT(17)
sys/dev/pci/tdvfbreg.h
71
#define TDV_LFBMODE_PIXPIPE __BIT(8)
sys/dev/pci/tdvfbreg.h
72
#define TDV_LFBMODE_WSW_WR __BIT(11)
sys/dev/pci/tdvfbreg.h
73
#define TDV_LFBMODE_BSW_WR __BIT(12)
sys/dev/pci/tdvfbreg.h
74
#define TDV_LFBMODE_WSW_RD __BIT(15)
sys/dev/pci/tdvfbreg.h
75
#define TDV_LFBMODE_BSW_RD __BIT(16)
sys/dev/pci/tdvfbreg.h
83
#define TDV_FBIINIT0_VGA_PASS __BIT(0)
sys/dev/pci/tdvfbreg.h
84
#define TDV_FBIINIT0_FBI_RST __BIT(1)
sys/dev/pci/tdvfbreg.h
85
#define TDV_FBIINIT0_FIFO_RST __BIT(2)
sys/dev/pci/tdvfbreg.h
88
#define TDV_FBIINIT1_PCIWAIT __BIT(1)
sys/dev/pci/tdvfbreg.h
89
#define TDV_FBIINIT1_LFB_EN __BIT(3)
sys/dev/pci/tdvfbreg.h
91
#define TDV_FBIINIT1_VIDEO_RST __BIT(8)
sys/dev/pci/tdvfbreg.h
92
#define TDV_FBIINIT1_BLANKING __BIT(12)
sys/dev/pci/tdvfbreg.h
93
#define TDV_FBIINIT1_DR_DATA __BIT(13)
sys/dev/pci/tdvfbreg.h
94
#define TDV_FBIINIT1_DR_BLANKING __BIT(14)
sys/dev/pci/tdvfbreg.h
95
#define TDV_FBIINIT1_DR_HVSYNC __BIT(15)
sys/dev/pci/tdvfbreg.h
96
#define TDV_FBIINIT1_DR_DCLK __BIT(16)
sys/dev/pci/vio9p.c
99
#define VIO9P_INUSE __BIT(0)
sys/dev/pci/virtioreg.h
83
#define VIRTIO_F_NOTIFY_ON_EMPTY __BIT(24)
sys/dev/pci/virtioreg.h
84
#define VIRTIO_F_RING_INDIRECT_DESC __BIT(28)
sys/dev/pci/virtioreg.h
85
#define VIRTIO_F_RING_EVENT_IDX __BIT(29)
sys/dev/pci/virtioreg.h
86
#define VIRTIO_F_BAD_FEATURE __BIT(30)
sys/dev/pci/virtioreg.h
87
#define VIRTIO_F_VERSION_1 __BIT(32)
sys/dev/pci/virtioreg.h
88
#define VIRTIO_F_ACCESS_PLATFORM __BIT(33)
sys/dev/pci/virtioreg.h
89
#define VIRTIO_F_RING_PACKED __BIT(34)
sys/dev/pci/virtioreg.h
90
#define VIRTIO_F_ORDER_PLATFORM __BIT(36)
sys/dev/pci/virtioreg.h
91
#define VIRTIO_F_SR_IOV __BIT(37)
sys/dev/pckbport/alps.c
677
val = val | __BIT(1);
sys/dev/pckbport/alps.c
922
cur_y2 &= ~__BIT(5); /* Clear duplicate locations */
sys/dev/pckbport/alps.c
923
cur_y2 |= (psc->packet[4] & __BIT(1)) << 4; /* Set another */
sys/dev/pckbport/synapticsreg.h
80
#define SYN_CCAP_COVERED_PAD __BIT(15)
sys/dev/pckbport/synapticsreg.h
82
#define SYN_CCAP_CLICKPAD_BIT_0 __BIT(12) /* one-button clickpad */
sys/dev/pckbport/synapticsreg.h
83
#define SYN_CCAP_HAS_ADV_GESTURE_MODE __BIT(11)
sys/dev/pckbport/synapticsreg.h
84
#define SYN_CCAP_CLEARPAD __BIT(10)
sys/dev/pckbport/synapticsreg.h
85
#define SYN_CCAP_REPORT_MAX __BIT(9)
sys/dev/pckbport/synapticsreg.h
86
#define SYN_CCAP_ADJ_THRESHOLD __BIT(8)
sys/dev/pckbport/synapticsreg.h
87
#define SYN_CCAP_REPORT_MIN __BIT(5)
sys/dev/pckbport/synapticsreg.h
88
#define SYN_CCAP_UNIFORM_CLICKPAD __BIT(4)
sys/dev/pckbport/synapticsreg.h
89
#define SYN_CCAP_IMAGE_SENSOR __BIT(3) /* reports V */
sys/dev/pckbport/synapticsreg.h
90
#define SYN_CCAP_REDUCED_FILTERING __BIT(2)
sys/dev/pckbport/synapticsreg.h
91
#define SYN_CCAP_DELUX_LED_CONTROLS __BIT(1)
sys/dev/pckbport/synapticsreg.h
92
#define SYN_CCAP_CLICKPAD_BIT_1 __BIT(0) /* two-button clickpad */
sys/dev/scsipi/cd.c
1383
int pmask = __BIT(part);
sys/dev/scsipi/sd.c
978
int pmask = __BIT(part);
sys/dev/sdmmc/sdmmcreg.h
409
#define SSR_PERFORMANCE_ENHANCE_CARD_MAINT __BIT(0)
sys/dev/sdmmc/sdmmcreg.h
410
#define SSR_PERFORMANCE_ENHANCE_HOST_MAINT __BIT(1)
sys/dev/sdmmc/sdmmcreg.h
411
#define SSR_PERFORMANCE_ENHANCE_CACHE __BIT(2)
sys/dev/sdmmc/sdmmcreg.h
466
return dst & (__BIT(len) - 1);
sys/dev/sdmmc/sdmmcvar.h
257
#define SMC_CAPS_AUTO_STOP __BIT(0) /* send CMD12 automagically by host */
sys/dev/sdmmc/sdmmcvar.h
258
#define SMC_CAPS_4BIT_MODE __BIT(1) /* 4-bits data bus width */
sys/dev/sdmmc/sdmmcvar.h
259
#define SMC_CAPS_DMA __BIT(2) /* DMA transfer */
sys/dev/sdmmc/sdmmcvar.h
260
#define SMC_CAPS_SPI_MODE __BIT(3) /* SPI mode */
sys/dev/sdmmc/sdmmcvar.h
261
#define SMC_CAPS_POLL_CARD_DET __BIT(4) /* Polling card detect */
sys/dev/sdmmc/sdmmcvar.h
262
#define SMC_CAPS_SINGLE_ONLY __BIT(5) /* only single read/write */
sys/dev/sdmmc/sdmmcvar.h
263
#define SMC_CAPS_8BIT_MODE __BIT(6) /* 8-bits data bus width */
sys/dev/sdmmc/sdmmcvar.h
264
#define SMC_CAPS_MULTI_SEG_DMA __BIT(7) /* multiple segment DMA transfer */
sys/dev/sdmmc/sdmmcvar.h
265
#define SMC_CAPS_SD_HIGHSPEED __BIT(8) /* SD high-speed timing */
sys/dev/sdmmc/sdmmcvar.h
266
#define SMC_CAPS_MMC_HIGHSPEED __BIT(9) /* MMC high-speed timing */
sys/dev/sdmmc/sdmmcvar.h
267
#define SMC_CAPS_MMC_DDR52 __BIT(10) /* MMC HS DDR52 timing */
sys/dev/sdmmc/sdmmcvar.h
269
#define SMC_CAPS_UHS_SDR50 __BIT(12) /* UHS SDR50 timing */
sys/dev/sdmmc/sdmmcvar.h
270
#define SMC_CAPS_UHS_SDR104 __BIT(13) /* UHS SDR104 timing */
sys/dev/sdmmc/sdmmcvar.h
271
#define SMC_CAPS_UHS_DDR50 __BIT(14) /* UHS DDR50 timing */
sys/dev/sdmmc/sdmmcvar.h
275
#define SMC_CAPS_MMC_HS200 __BIT(15) /* eMMC HS200 timing */
sys/dev/sdmmc/sdmmcvar.h
276
#define SMC_CAPS_POLLING __BIT(30) /* driver supports cmd polling */
sys/dev/spi/mcp23xxxgpio_spi.c
299
spi_present_mask = __BIT(device_cfdata(self)->cf_flags & 0x7);
sys/dev/spi/mcp23xxxgpio_spi.c
308
spi_present_mask >= __BIT(4)) ||
sys/dev/spi/mcp23xxxgpio_spi.c
310
spi_present_mask >= __BIT(8))) {
sys/dev/spi/mcp23xxxgpio_spi.c
322
for (bank = 0; spi_present_mask != 0; spi_present_mask &= ~__BIT(ha)) {
sys/dev/spi/mcp48x1.c
54
#define MCP48X1DAC_WRITE __BIT(15) /* active low */
sys/dev/spi/mcp48x1.c
55
#define MCP48X1DAC_GAIN __BIT(13) /* active low */
sys/dev/spi/mcp48x1.c
56
#define MCP48X1DAC_SHDN __BIT(12) /* active low */
sys/dev/spi/oj6sh.c
294
return (motion & __BIT(7) ? true : false);
sys/dev/spi/spi.c
119
#define SPIH_ATTACHED __BIT(0)
sys/dev/spi/spi.c
120
#define SPIH_DIRECT __BIT(1)
sys/dev/spi/spivar.h
62
#define SPI_MODE_CPHA __BIT(0)
sys/dev/spi/spivar.h
63
#define SPI_MODE_CPOL __BIT(1)
sys/dev/spi/spivar.h
81
#define SPI_F_3WIRE __BIT(0) /* requires 3-wire mode */
sys/dev/spi/spivar.h
82
#define SPI_F_CS_HIGH __BIT(1) /* chip select is active-high */
sys/dev/spi/spivar.h
83
#define SPI_F_LSB __BIT(2) /* transfer LSB first */
sys/dev/tc/tc.c
133
sc->sc_slots_used |= __BIT(builtin->tcb_slot);
sys/dev/tc/tc.c
152
if (sc->sc_slots_used & __BIT(i))
sys/dev/tc/tc.c
178
sc->sc_slots_used |= __BIT(i);
sys/dev/tc/tcu.c
56
#define TCU_CFG_RUN __BIT(7) /* write-only */
sys/dev/tc/tcu.c
57
#define TCU_CFG_S1_1 __BIT(3) /* read-only */
sys/dev/tc/tcu.c
58
#define TCU_CFG_S1_2 __BIT(2) /* read-only */
sys/dev/tc/tcu.c
59
#define TCU_CFG_S1_3 __BIT(1) /* read-only */
sys/dev/tc/tcu.c
60
#define TCU_CFG_S1_4 __BIT(0) /* read-only */
sys/dev/tprof/tprof.c
511
tprof_stop(__BIT(c));
sys/dev/tprof/tprof.c
583
SET(tb->tb_softc.sc_ctr_configured_mask, __BIT(c));
sys/dev/tprof/tprof.c
584
CLR(tb->tb_softc.sc_ctr_prof_mask, __BIT(c));
sys/dev/tprof/tprof.c
585
CLR(tb->tb_softc.sc_ctr_ovf_mask, __BIT(c));
sys/dev/tprof/tprof.c
588
SET(tb->tb_softc.sc_ctr_prof_mask, __BIT(c));
sys/dev/tprof/tprof.c
589
SET(tb->tb_softc.sc_ctr_ovf_mask, __BIT(c));
sys/dev/tprof/tprof.c
593
SET(tb->tb_softc.sc_ctr_ovf_mask, __BIT(c));
sys/dev/tprof/tprof.c
614
if (ISSET(configmask, __BIT(c))) {
sys/dev/tprof/tprof_armv7.c
170
armreg_pmcntenclr_write(__BIT(counter) & PMCNTEN_P);
sys/dev/tprof/tprof_armv7.c
173
armreg_pmintenclr_write(__BIT(counter) & PMINTEN_P);
sys/dev/tprof/tprof_armv7.c
188
armreg_pmintenset_write(__BIT(counter) & PMINTEN_P);
sys/dev/tprof/tprof_armv7.c
191
armreg_pmovsr_write(__BIT(counter) & PMOVS_P);
sys/dev/tprof/tprof_armv7.c
235
CLR(mask, __BIT(bit));
sys/dev/tprof/tprof_armv7.c
237
if (ISSET(sc->sc_ctr_prof_mask, __BIT(bit))) {
sys/dev/tprof/tprof_armv7.c
251
} else if (ISSET(sc->sc_ctr_ovf_mask, __BIT(bit))) {
sys/dev/tprof/tprof_armv7.c
253
counters_offset[bit] += __BIT(32);
sys/dev/tprof/tprof_armv7.c
88
if (eid[idx] & __BIT(bit)) {
sys/dev/tprof/tprof_armv8.c
143
reg_pmcntenclr_el0_write(__BIT(counter) & PMCNTEN_P);
sys/dev/tprof/tprof_armv8.c
146
reg_pmintenclr_el1_write(__BIT(counter) & PMINTEN_P);
sys/dev/tprof/tprof_armv8.c
159
reg_pmintenset_el1_write(__BIT(counter) & PMINTEN_P);
sys/dev/tprof/tprof_armv8.c
163
reg_pmovsclr_el0_write(__BIT(counter) & PMOVS_P);
sys/dev/tprof/tprof_armv8.c
207
CLR(mask, __BIT(bit));
sys/dev/tprof/tprof_armv8.c
209
if (ISSET(sc->sc_ctr_prof_mask, __BIT(bit))) {
sys/dev/tprof/tprof_armv8.c
223
} else if (ISSET(sc->sc_ctr_ovf_mask, __BIT(bit))) {
sys/dev/tprof/tprof_armv8.c
225
counters_offset[bit] += __BIT(32);
sys/dev/tprof/tprof_armv8.c
67
if (eid[idx] & __BIT(bit))
sys/dev/tprof/tprof_x86_amd.c
101
#define PESR_GO __BIT(40)
sys/dev/tprof/tprof_x86_amd.c
102
#define PESR_HO __BIT(41)
sys/dev/tprof/tprof_x86_amd.c
168
CLR(runmask, __BIT(bit));
sys/dev/tprof/tprof_x86_amd.c
180
CLR(stopmask, __BIT(bit));
sys/dev/tprof/tprof_x86_amd.c
197
CLR(mask, __BIT(bit));
sys/dev/tprof/tprof_x86_amd.c
201
if ((ctr & __BIT(COUNTER_BITWIDTH - 1)) != 0)
sys/dev/tprof/tprof_x86_amd.c
204
if (ISSET(sc->sc_ctr_prof_mask, __BIT(bit))) {
sys/dev/tprof/tprof_x86_amd.c
222
counters_offset[bit] += __BIT(COUNTER_BITWIDTH);
sys/dev/tprof/tprof_x86_amd.c
90
#define PESR_USR __BIT(16)
sys/dev/tprof/tprof_x86_amd.c
91
#define PESR_OS __BIT(17)
sys/dev/tprof/tprof_x86_amd.c
92
#define PESR_E __BIT(18)
sys/dev/tprof/tprof_x86_amd.c
93
#define PESR_PC __BIT(19)
sys/dev/tprof/tprof_x86_amd.c
94
#define PESR_INT __BIT(20)
sys/dev/tprof/tprof_x86_amd.c
96
#define PESR_EN __BIT(22)
sys/dev/tprof/tprof_x86_amd.c
97
#define PESR_INV __BIT(23)
sys/dev/tprof/tprof_x86_intel.c
159
CLR(runmask, __BIT(bit));
sys/dev/tprof/tprof_x86_intel.c
171
CLR(stopmask, __BIT(bit));
sys/dev/tprof/tprof_x86_intel.c
190
CLR(mask, __BIT(bit));
sys/dev/tprof/tprof_x86_intel.c
194
if ((ctr & __BIT(counter_bitwidth - 1)) != 0)
sys/dev/tprof/tprof_x86_intel.c
197
if (ISSET(sc->sc_ctr_prof_mask, __BIT(bit))) {
sys/dev/tprof/tprof_x86_intel.c
215
counters_offset[bit] += __BIT(counter_bitwidth);
sys/dev/tprof/tprof_x86_intel.c
89
#define PERFEVTSEL_USR __BIT(16)
sys/dev/tprof/tprof_x86_intel.c
90
#define PERFEVTSEL_OS __BIT(17)
sys/dev/tprof/tprof_x86_intel.c
91
#define PERFEVTSEL_E __BIT(18)
sys/dev/tprof/tprof_x86_intel.c
92
#define PERFEVTSEL_PC __BIT(19)
sys/dev/tprof/tprof_x86_intel.c
93
#define PERFEVTSEL_INT __BIT(20)
sys/dev/tprof/tprof_x86_intel.c
94
#define PERFEVTSEL_EN __BIT(22)
sys/dev/tprof/tprof_x86_intel.c
95
#define PERFEVTSEL_INV __BIT(23)
sys/dev/usb/ehci.c
2057
EHCI_QH_SET_SMASK(__BIT(1)) /* Start Split Y1 */
sys/dev/usb/ehcireg.h
192
#define EHCI_LINK_TERMINATE __BIT(0)
sys/dev/usb/ehcireg.h
215
#define EHCI_ITD_ACTIVE __BIT(31)
sys/dev/usb/ehcireg.h
216
#define EHCI_ITD_BUF_ERR __BIT(30)
sys/dev/usb/ehcireg.h
217
#define EHCI_ITD_BABBLE __BIT(29)
sys/dev/usb/ehcireg.h
218
#define EHCI_ITD_ERROR __BIT(28)
sys/dev/usb/ehcireg.h
222
#define EHCI_ITD_IOC __BIT(15)
sys/dev/usb/ehcireg.h
241
#define EHCI_ITD_DIR_MASK __BIT(11)
sys/dev/usb/ehcireg.h
261
#define EHCI_SITD_DIR_MASK __BIT(31)
sys/dev/usb/ehcireg.h
277
#define EHCI_SITD_IOC __BIT(31)
sys/dev/usb/ehcireg.h
278
#define EHCI_SITD_P __BIT(30)
sys/dev/usb/ehcireg.h
338
#define EHCI_QTD_IOC __BIT(15)
sys/dev/usb/ehcireg.h
343
#define EHCI_QTD_TOGGLE_MASK __BIT(31)
sys/dev/usb/ehcireg.h
361
#define EHCI_QH_INACT __BIT(7) /* inactivate on next */
sys/dev/usb/ehcireg.h
372
#define EHCI_QH_DTC __BIT(14) /* data toggle control */
sys/dev/usb/ehcireg.h
374
#define EHCI_QH_HRECL __BIT(15) /* head of reclamation */
sys/dev/usb/ehcireg.h
379
#define EHCI_QH_CTL __BIT(27) /* control endpoint */
sys/dev/usb/ehcireg.h
421
#define EHCI_DSC_WRITE __BIT(4)
sys/dev/usb/ehcireg.h
422
#define EHCI_DSC_GO __BIT(5)
sys/dev/usb/ehcireg.h
423
#define EHCI_DSC_ERROR __BIT(6)
sys/dev/usb/ehcireg.h
428
#define EHCI_DSC_IN_USE __BIT(10)
sys/dev/usb/ehcireg.h
429
#define EHCI_DSC_DONE __BIT(16)
sys/dev/usb/ehcireg.h
430
#define EHCI_DSC_ENABLED __BIT(28)
sys/dev/usb/ehcireg.h
431
#define EHCI_DSC_OWNER __BIT(30)
sys/dev/usb/ehcireg.h
90
#define EHCI_HCC_IST_FULLFRAME __BIT(7)
sys/dev/usb/if_axe.c
112
#define AX178 __BIT(0) /* AX88178 */
sys/dev/usb/if_axe.c
113
#define AX772 __BIT(1) /* AX88772 */
sys/dev/usb/if_axe.c
114
#define AX772A __BIT(2) /* AX88772A */
sys/dev/usb/if_axe.c
115
#define AX772B __BIT(3) /* AX88772B */
sys/dev/usb/if_axe.c
116
#define AXSTD_FRAME __BIT(12)
sys/dev/usb/if_axe.c
117
#define AXCSUM_FRAME __BIT(13)
sys/dev/usb/if_axereg.h
218
#define AXE_SW_RESET_IPOSC __BIT(7)
sys/dev/usb/if_axereg.h
223
#define AXE_SW_RESET_IPCOPS __BIT(10)
sys/dev/usb/if_axereg.h
224
#define AXE_SW_RESET_IPCOPSC __BIT(11)
sys/dev/usb/if_axereg.h
225
#define AXE_SW_RESET_AD __BIT(12)
sys/dev/usb/if_axereg.h
226
#define AXE_SW_RESET_IPFPS __BIT(13)
sys/dev/usb/if_axereg.h
227
#define AXE_SW_RESET_WOLLP __BIT(14)
sys/dev/usb/if_muevar.h
40
#define MUE_RX_CMD_A_IPV __BIT(29)
sys/dev/usb/if_muevar.h
41
#define MUE_RX_CMD_A_TCE __BIT(30)
sys/dev/usb/if_muevar.h
42
#define MUE_RX_CMD_A_ICE __BIT(31)
sys/dev/usb/if_otus.c
76
#define DBG_INIT __BIT(0)
sys/dev/usb/if_otus.c
77
#define DBG_FN __BIT(1)
sys/dev/usb/if_otus.c
78
#define DBG_TX __BIT(2)
sys/dev/usb/if_otus.c
79
#define DBG_RX __BIT(3)
sys/dev/usb/if_otus.c
80
#define DBG_STM __BIT(4)
sys/dev/usb/if_otus.c
81
#define DBG_CHAN __BIT(5)
sys/dev/usb/if_otus.c
82
#define DBG_REG __BIT(6)
sys/dev/usb/if_otus.c
83
#define DBG_CMD __BIT(7)
sys/dev/usb/if_urevar.h
47
#define URE_RXPKT_IPV4_CS __BIT(19)
sys/dev/usb/if_urevar.h
48
#define URE_RXPKT_IPV6_CS __BIT(20)
sys/dev/usb/if_urevar.h
49
#define URE_RXPKT_TCP_CS __BIT(22)
sys/dev/usb/if_urevar.h
50
#define URE_RXPKT_UDP_CS __BIT(23)
sys/dev/usb/if_urevar.h
52
#define URE_RXPKT_RX_VLAN_TAG __BIT(16)
sys/dev/usb/if_urevar.h
53
#define URE_RXPKT_TCP_F __BIT(21)
sys/dev/usb/if_urevar.h
54
#define URE_RXPKT_UDP_F __BIT(22)
sys/dev/usb/if_urevar.h
55
#define URE_RXPKT_IP_F __BIT(23)
sys/dev/usb/if_urevar.h
63
#define URE_TXPKT_TX_FS __BIT(31)
sys/dev/usb/if_urevar.h
64
#define URE_TXPKT_TX_LS __BIT(30)
sys/dev/usb/if_urevar.h
69
#define URE_TXPKT_IPV6_CS __BIT(28)
sys/dev/usb/if_urevar.h
70
#define URE_TXPKT_IPV4_CS __BIT(29)
sys/dev/usb/if_urevar.h
71
#define URE_TXPKT_TCP_CS __BIT(30)
sys/dev/usb/if_urevar.h
72
#define URE_TXPKT_UDP_CS __BIT(31)
sys/dev/usb/if_urtwn.c
136
#define FLAG_RTL8188E __BIT(0)
sys/dev/usb/if_urtwn.c
137
#define FLAG_RTL8192E __BIT(1)
sys/dev/usb/if_urtwn.c
5021
urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13));
sys/dev/usb/if_urtwn.c
90
#define DBG_INIT __BIT(0)
sys/dev/usb/if_urtwn.c
91
#define DBG_FN __BIT(1)
sys/dev/usb/if_urtwn.c
92
#define DBG_TX __BIT(2)
sys/dev/usb/if_urtwn.c
93
#define DBG_RX __BIT(3)
sys/dev/usb/if_urtwn.c
94
#define DBG_STM __BIT(4)
sys/dev/usb/if_urtwn.c
95
#define DBG_RF __BIT(5)
sys/dev/usb/if_urtwn.c
96
#define DBG_REG __BIT(6)
sys/dev/usb/if_urtwnreg.h
49
#define R92E_AUTO_LLT_EN __BIT(16)
sys/dev/usb/if_urtwnreg.h
54
#define R92E_SPSLDO_SEL __BIT(24)
sys/dev/usb/if_urtwnvar.h
122
#define URTWN_FLAG_CCK_HIPWR __BIT(0)
sys/dev/usb/if_urtwnvar.h
123
#define URTWN_FLAG_ATTACHED __BIT(1)
sys/dev/usb/if_urtwnvar.h
124
#define URTWN_FLAG_FWREADY __BIT(2)
sys/dev/usb/ohcireg.h
106
#define OHCI_FM_FIT __BIT(31)
sys/dev/usb/ohcireg.h
114
#define OHCI_RHD_PSM __BIT(8) /* Power Switching Mode */
sys/dev/usb/ohcireg.h
115
#define OHCI_RHD_NPS __BIT(9) /* No Power Switching */
sys/dev/usb/ohcireg.h
116
#define OHCI_RHD_DT __BIT(10) /* Device Type */
sys/dev/usb/ohcireg.h
117
#define OHCI_RHD_OCPM __BIT(11) /* Overcurrent Protection Mode */
sys/dev/usb/ohcireg.h
118
#define OHCI_RHD_NOCP __BIT(12) /* No Overcurrent Protection */
sys/dev/usb/ohcireg.h
124
#define OHCI_RHS_LPS __BIT(0) /* Local Power Status */
sys/dev/usb/ohcireg.h
125
#define OHCI_RHS_OCI __BIT(1) /* OverCurrent Indicator */
sys/dev/usb/ohcireg.h
126
#define OHCI_RHS_DRWE __BIT(15) /* Device Remote Wakeup Enable */
sys/dev/usb/ohcireg.h
127
#define OHCI_RHS_LPSC __BIT(16) /* Local Power Status Change */
sys/dev/usb/ohcireg.h
128
#define OHCI_RHS_CCIC __BIT(17) /* OverCurrent Indicator Change */
sys/dev/usb/ohcireg.h
129
#define OHCI_RHS_CRWE __BIT(31) /* Clear Remote Wakeup Enable */
sys/dev/usb/ohcireg.h
170
#define OHCI_ED_SPEED __BIT(13)
sys/dev/usb/ohcireg.h
171
#define OHCI_ED_SKIP __BIT(14)
sys/dev/usb/ohcireg.h
172
#define OHCI_ED_FORMAT_MASK __BIT(15)
sys/dev/usb/ohcireg.h
182
#define OHCI_HALTED __BIT(0)
sys/dev/usb/ohcireg.h
183
#define OHCI_TOGGLECARRY __BIT(1)
sys/dev/usb/ohcireg.h
196
#define OHCI_TD_R __BIT(18) /* Buffer Rounding */
sys/dev/usb/ohcireg.h
253
#define OHCI_ITD_PAGE_SELECT __BIT(12)
sys/dev/usb/ohcireg.h
50
#define OHCI_REV_LEGACY_MASK __BIT(8)
sys/dev/usb/ohcireg.h
60
#define OHCI_PLE __BIT(2) /* Periodic List Enable */
sys/dev/usb/ohcireg.h
61
#define OHCI_IE __BIT(3) /* Isochronous Enable */
sys/dev/usb/ohcireg.h
62
#define OHCI_CLE __BIT(4) /* Control List Enable */
sys/dev/usb/ohcireg.h
63
#define OHCI_BLE __BIT(5) /* Bulk List Enable */
sys/dev/usb/ohcireg.h
71
#define OHCI_IR __BIT(8) /* Interrupt Routing */
sys/dev/usb/ohcireg.h
72
#define OHCI_RWC __BIT(9) /* Remote Wakeup Connected */
sys/dev/usb/ohcireg.h
73
#define OHCI_RWE __BIT(10) /* Remote Wakeup Enabled */
sys/dev/usb/ohcireg.h
75
#define OHCI_HCR __BIT(0) /* Host Controller Reset */
sys/dev/usb/ohcireg.h
76
#define OHCI_CLF __BIT(1) /* Control List Filled */
sys/dev/usb/ohcireg.h
77
#define OHCI_BLF __BIT(2) /* Bulk List Filled */
sys/dev/usb/ohcireg.h
78
#define OHCI_OCR __BIT(3) /* Ownership Change Request */
sys/dev/usb/ohcireg.h
81
#define OHCI_SO __BIT(0) /* Scheduling Overrun */
sys/dev/usb/ohcireg.h
82
#define OHCI_WDH __BIT(1) /* Writeback Done Head */
sys/dev/usb/ohcireg.h
83
#define OHCI_SF __BIT(2) /* Start of Frame */
sys/dev/usb/ohcireg.h
84
#define OHCI_RD __BIT(3) /* Resume Detected */
sys/dev/usb/ohcireg.h
85
#define OHCI_UE __BIT(4) /* Unrecoverable Error */
sys/dev/usb/ohcireg.h
86
#define OHCI_FNO __BIT(5) /* Frame Number Overflow */
sys/dev/usb/ohcireg.h
87
#define OHCI_RHSC __BIT(6) /* Root Hub Status Change */
sys/dev/usb/ohcireg.h
88
#define OHCI_OC __BIT(30) /* Ownership Change */
sys/dev/usb/ohcireg.h
89
#define OHCI_MIE __BIT(31) /* Master Interrupt Enable */
sys/dev/usb/uatp.c
187
#define UATP_DEBUG_ATTACH __BIT(0)
sys/dev/usb/uatp.c
188
#define UATP_DEBUG_MISC __BIT(1)
sys/dev/usb/uatp.c
189
#define UATP_DEBUG_WSMOUSE __BIT(2)
sys/dev/usb/uatp.c
190
#define UATP_DEBUG_IOCTL __BIT(3)
sys/dev/usb/uatp.c
191
#define UATP_DEBUG_RESET __BIT(4)
sys/dev/usb/uatp.c
192
#define UATP_DEBUG_INTR __BIT(5)
sys/dev/usb/uatp.c
193
#define UATP_DEBUG_PARSE __BIT(6)
sys/dev/usb/uatp.c
194
#define UATP_DEBUG_TAP __BIT(7)
sys/dev/usb/uatp.c
195
#define UATP_DEBUG_EMUL_BUTTON __BIT(8)
sys/dev/usb/uatp.c
196
#define UATP_DEBUG_ACCUMULATE __BIT(9)
sys/dev/usb/uatp.c
197
#define UATP_DEBUG_STATUS __BIT(10)
sys/dev/usb/uatp.c
198
#define UATP_DEBUG_SPURINTR __BIT(11)
sys/dev/usb/uatp.c
199
#define UATP_DEBUG_MOVE __BIT(12)
sys/dev/usb/uatp.c
200
#define UATP_DEBUG_ACCEL __BIT(13)
sys/dev/usb/uatp.c
201
#define UATP_DEBUG_TRACK_DIST __BIT(14)
sys/dev/usb/uatp.c
202
#define UATP_DEBUG_PALM __BIT(15)
sys/dev/usb/uatp.c
249
#define UATP_STATUS_BUTTON __BIT(0) /* Button pressed */
sys/dev/usb/uatp.c
250
#define UATP_STATUS_BASE __BIT(2) /* Base sensor data */
sys/dev/usb/uatp.c
251
#define UATP_STATUS_POST_RESET __BIT(4) /* Post-reset */
sys/dev/usb/uatp.c
520
#define UATP_ENABLED __BIT(0) /* . Is the wsmouse enabled? */
sys/dev/usb/uatp.c
521
#define UATP_DYING __BIT(1) /* . Have we been deactivated? */
sys/dev/usb/uatp.c
522
#define UATP_VALID __BIT(2) /* . Do we have valid sensor data? */
sys/dev/usb/uhcireg.h
100
#define UHCI_PORTSC_CCS __BIT(0)
sys/dev/usb/uhcireg.h
101
#define UHCI_PORTSC_CSC __BIT(1)
sys/dev/usb/uhcireg.h
102
#define UHCI_PORTSC_PE __BIT(2)
sys/dev/usb/uhcireg.h
103
#define UHCI_PORTSC_POEDC __BIT(3)
sys/dev/usb/uhcireg.h
106
#define UHCI_PORTSC_RD __BIT(6)
sys/dev/usb/uhcireg.h
107
#define UHCI_PORTSC_LSDA __BIT(8)
sys/dev/usb/uhcireg.h
108
#define UHCI_PORTSC_PR __BIT(9)
sys/dev/usb/uhcireg.h
109
#define UHCI_PORTSC_OCI __BIT(10)
sys/dev/usb/uhcireg.h
110
#define UHCI_PORTSC_OCIC __BIT(11)
sys/dev/usb/uhcireg.h
111
#define UHCI_PORTSC_SUSP __BIT(12)
sys/dev/usb/uhcireg.h
123
#define UHCI_PTR_T __BIT(0)
sys/dev/usb/uhcireg.h
125
#define UHCI_PTR_QH __BIT(1)
sys/dev/usb/uhcireg.h
126
#define UHCI_PTR_VF __BIT(2)
sys/dev/usb/uhcireg.h
153
#define UHCI_TD_BITSTUFF __BIT(17)
sys/dev/usb/uhcireg.h
154
#define UHCI_TD_CRCTO __BIT(18)
sys/dev/usb/uhcireg.h
155
#define UHCI_TD_NAK __BIT(19)
sys/dev/usb/uhcireg.h
156
#define UHCI_TD_BABBLE __BIT(20)
sys/dev/usb/uhcireg.h
157
#define UHCI_TD_DBUFFER __BIT(21)
sys/dev/usb/uhcireg.h
158
#define UHCI_TD_STALLED __BIT(22)
sys/dev/usb/uhcireg.h
159
#define UHCI_TD_ACTIVE __BIT(23)
sys/dev/usb/uhcireg.h
161
#define UHCI_TD_IOC __BIT(24)
sys/dev/usb/uhcireg.h
162
#define UHCI_TD_IOS __BIT(25)
sys/dev/usb/uhcireg.h
163
#define UHCI_TD_LS __BIT(26)
sys/dev/usb/uhcireg.h
167
#define UHCI_TD_SPD __BIT(29)
sys/dev/usb/uhcireg.h
181
#define UHCI_TD_DT_MASK __BIT(19)
sys/dev/usb/uhcireg.h
46
#define PCI_LEGSUP_A20PTS __BIT(15) /* End of A20GATE passthru status */
sys/dev/usb/uhcireg.h
47
#define PCI_LEGSUP_USBPIRQDEN __BIT(13) /* USB PIRQ D Enable */
sys/dev/usb/uhcireg.h
48
#define PCI_LEGSUP_USBIRQS __BIT(12) /* USB IRQ status */
sys/dev/usb/uhcireg.h
49
#define PCI_LEGSUP_TBY64W __BIT(11) /* Trap by 64h write status */
sys/dev/usb/uhcireg.h
50
#define PCI_LEGSUP_TBY64R __BIT(10) /* Trap by 64h read status */
sys/dev/usb/uhcireg.h
51
#define PCI_LEGSUP_TBY60W __BIT(9) /* Trap by 60h write status */
sys/dev/usb/uhcireg.h
52
#define PCI_LEGSUP_TBY60R __BIT(8) /* Trap by 60h read status */
sys/dev/usb/uhcireg.h
53
#define PCI_LEGSUP_SMIEPTE __BIT(7) /* SMI at end of passthru enable */
sys/dev/usb/uhcireg.h
54
#define PCI_LEGSUP_PSS __BIT(6) /* Passthru status */
sys/dev/usb/uhcireg.h
55
#define PCI_LEGSUP_A20PTEN __BIT(5) /* A20GATE passthru enable */
sys/dev/usb/uhcireg.h
56
#define PCI_LEGSUP_USBSMIEN __BIT(4) /* Enable SMI# generation */
sys/dev/usb/uhcireg.h
65
#define UHCI_CMD_RS __BIT(0)
sys/dev/usb/uhcireg.h
66
#define UHCI_CMD_HCRESET __BIT(1)
sys/dev/usb/uhcireg.h
67
#define UHCI_CMD_GRESET __BIT(2)
sys/dev/usb/uhcireg.h
68
#define UHCI_CMD_EGSM __BIT(3)
sys/dev/usb/uhcireg.h
69
#define UHCI_CMD_FGR __BIT(4)
sys/dev/usb/uhcireg.h
70
#define UHCI_CMD_SWDBG __BIT(5)
sys/dev/usb/uhcireg.h
71
#define UHCI_CMD_CF __BIT(6)
sys/dev/usb/uhcireg.h
72
#define UHCI_CMD_MAXP __BIT(7)
sys/dev/usb/uhcireg.h
75
#define UHCI_STS_USBINT __BIT(0)
sys/dev/usb/uhcireg.h
76
#define UHCI_STS_USBEI __BIT(1)
sys/dev/usb/uhcireg.h
77
#define UHCI_STS_RD __BIT(2)
sys/dev/usb/uhcireg.h
78
#define UHCI_STS_HSE __BIT(3)
sys/dev/usb/uhcireg.h
79
#define UHCI_STS_HCPE __BIT(4)
sys/dev/usb/uhcireg.h
80
#define UHCI_STS_HCH __BIT(5)
sys/dev/usb/uhcireg.h
84
#define UHCI_INTR_TOCRCIE __BIT(0)
sys/dev/usb/uhcireg.h
85
#define UHCI_INTR_RIE __BIT(1)
sys/dev/usb/uhcireg.h
86
#define UHCI_INTR_IOCE __BIT(2)
sys/dev/usb/uhcireg.h
87
#define UHCI_INTR_SPIE __BIT(3)
sys/dev/usb/uhso.c
1012
if (!ISSET(buf[0], __BIT(i)))
sys/dev/usb/uhso.c
322
#define UHSO_PORT_MUXPIPE __BIT(0) /* duplicate ipipe/ibuf references */
sys/dev/usb/uhso.c
323
#define UHSO_PORT_MUXREADY __BIT(1) /* input is ready */
sys/dev/usb/uhso.c
324
#define UHSO_PORT_MUXBUSY __BIT(2) /* read in progress */
sys/dev/usb/uhso.c
792
if (ISSET(mux, __BIT(i))) {
sys/dev/usb/ulpireg.h
51
#define FUNCTION_CONTROL_TERMSELECT __BIT(2)
sys/dev/usb/ulpireg.h
53
#define FUNCTION_CONTROL_RESET __BIT(5)
sys/dev/usb/ulpireg.h
54
#define FUNCTION_CONTROL_SUSPENDM __BIT(6)
sys/dev/usb/ulpireg.h
57
#define OTG_CONTROL_IDPULLUP __BIT(0) /* ID pull up */
sys/dev/usb/ulpireg.h
58
#define OTG_CONTROL_DPPULLDOWN __BIT(1) /* D+ pull down */
sys/dev/usb/ulpireg.h
59
#define OTG_CONTROL_DMPULLDOWN __BIT(2) /* D- pull down */
sys/dev/usb/ulpireg.h
60
#define OTG_CONTROL_DISCHRGVBUS __BIT(3) /* discharge Vbus */
sys/dev/usb/ulpireg.h
61
#define OTG_CONTROL_CHRGVBUS __BIT(4) /* charge Vbus */
sys/dev/usb/ulpireg.h
62
#define OTG_CONTROL_DRVVBUS __BIT(5) /* drive 5V on Vbus */
sys/dev/usb/ulpireg.h
63
#define OTG_CONTROL_DRVVBUSEXT __BIT(6) /* drive Vbus external */
sys/dev/usb/ulpireg.h
64
#define OTG_CONTROL_USEEXTVBUSIND __BIT(7) /* use external Vbus over-current
sys/dev/usb/usb.h
322
#define UE_GET_SS_ISO_SSP_MASK __BIT(7)
sys/dev/usb/usb.h
367
#define USB_DEVCAP_V2EXT_LPM __BIT(1)
sys/dev/usb/usb.h
368
#define USB_DEVCAP_V2EXT_BESL_SUPPORTED __BIT(2)
sys/dev/usb/usb.h
369
#define USB_DEVCAP_V2EXT_BESL_BASELINE_VALID __BIT(3)
sys/dev/usb/usb.h
370
#define USB_DEVCAP_V2EXT_BESL_DEEP_VALID __BIT(4)
sys/dev/usb/usb.h
384
#define USB_DEVCAP_SS_LTM __BIT(1)
sys/dev/usb/usb.h
386
#define USB_DEVCAP_SS_SPEED_LS __BIT(0)
sys/dev/usb/usb.h
387
#define USB_DEVCAP_SS_SPEED_FS __BIT(1)
sys/dev/usb/usb.h
388
#define USB_DEVCAP_SS_SPEED_HS __BIT(2)
sys/dev/usb/usb.h
389
#define USB_DEVCAP_SS_SPEED_SS __BIT(3)
sys/dev/usb/usb_mem.h
54
#define USB_DMA_FULLBLOCK __BIT(0)
sys/dev/usb/usb_mem.h
55
#define USB_DMA_COHERENT __BIT(1)
sys/dev/usb/usb_mem.h
60
#define USBMALLOC_MULTISEG __BIT(0)
sys/dev/usb/usb_mem.h
61
#define USBMALLOC_COHERENT __BIT(1)
sys/dev/usb/usb_mem.h
62
#define USBMALLOC_ZERO __BIT(2)
sys/dev/usb/uslsareg.h
103
#define SLSA_RV_SET_MHS_DTR __BIT(0)
sys/dev/usb/uslsareg.h
104
#define SLSA_RV_SET_MHS_RTS __BIT(1)
sys/dev/usb/uslsareg.h
106
#define SLSA_RV_SET_MHS_DTR_MASK __BIT(8)
sys/dev/usb/uslsareg.h
107
#define SLSA_RV_SET_MHS_RTS_MASK __BIT(9)
sys/dev/usb/uslsareg.h
112
#define SLSA_MDMSTS_DTR __BIT(0)
sys/dev/usb/uslsareg.h
113
#define SLSA_MDMSTS_RTS __BIT(1)
sys/dev/usb/uslsareg.h
114
#define SLSA_MDMSTS_CTS __BIT(4)
sys/dev/usb/uslsareg.h
115
#define SLSA_MDMSTS_DSR __BIT(5)
sys/dev/usb/uslsareg.h
116
#define SLSA_MDMSTS_RI __BIT(6)
sys/dev/usb/uslsareg.h
117
#define SLSA_MDMSTS_DCD __BIT(7)
sys/dev/usb/uslsareg.h
123
#define SLSA_EVENT_TERI __BIT(0) /* RI trailing edge */
sys/dev/usb/uslsareg.h
124
#define SLSA_EVENT_RB80 __BIT(2) /* Rx buf 80% full */
sys/dev/usb/uslsareg.h
125
#define SLSA_EVENT_CR __BIT(8) /* char received */
sys/dev/usb/uslsareg.h
126
#define SLSA_EVENT_SCR __BIT(9) /* special char received */
sys/dev/usb/uslsareg.h
127
#define SLSA_EVENT_TQE __BIT(10) /* Tx queue empty */
sys/dev/usb/uslsareg.h
128
#define SLSA_EVENT_DCTS __BIT(11) /* CTS changed */
sys/dev/usb/uslsareg.h
129
#define SLSA_EVENT_DDSR __BIT(12) /* DSR changed */
sys/dev/usb/uslsareg.h
130
#define SLSA_EVENT_DDCD __BIT(13) /* DCD changed */
sys/dev/usb/uslsareg.h
131
#define SLSA_EVENT_BI __BIT(14) /* line break received */
sys/dev/usb/uslsareg.h
132
#define SLSA_EVENT_LSE __BIT(15) /* line status error */
sys/dev/usb/uslsareg.h
144
#define SLSA_RV_PURGE_TX __BIT(0)
sys/dev/usb/uslsareg.h
145
#define SLSA_RV_PURGE_RX __BIT(1)
sys/dev/usb/uslsareg.h
146
#define SLSA_RV_PURGE_TX1 __BIT(2) /* what's the second set for? */
sys/dev/usb/uslsareg.h
147
#define SLSA_RV_PURGE_RX1 __BIT(3)
sys/dev/usb/uslsareg.h
196
#define SERIAL_CTS_HANDSHAKE __BIT(3)
sys/dev/usb/uslsareg.h
197
#define SERIAL_DSR_HANDSHAKE __BIT(4)
sys/dev/usb/uslsareg.h
198
#define SERIAL_DCD_HANDSHAKE __BIT(5)
sys/dev/usb/uslsareg.h
199
#define SERIAL_DSR_SENSITIVITY __BIT(6)
sys/dev/usb/uslsareg.h
201
#define SERIAL_AUTO_TRANSMIT __BIT(0)
sys/dev/usb/uslsareg.h
202
#define SERIAL_AUTO_RECEIVE __BIT(1)
sys/dev/usb/uslsareg.h
203
#define SERIAL_ERROR_CHAR __BIT(2)
sys/dev/usb/uslsareg.h
204
#define SERIAL_NULL_STRIPPING __BIT(3)
sys/dev/usb/uslsareg.h
205
#define SERIAL_BREAK_CHAR __BIT(4)
sys/dev/usb/uslsareg.h
207
#define SERIAL_XOFF_CONTINUE __BIT(31)
sys/dev/usb/vhci.c
814
p[0] = __BIT(vfd->port); /* TODO-bitmap */
sys/dev/usb/vhci.c
901
p[0] = __BIT(vfd->port); /* TODO-bitmap */
sys/dev/usb/xhci.c
1275
bus == 0 ? 0 : __BIT(cp % NBBY);
sys/dev/usb/xhci.c
591
const uint8_t bit = __BIT(port % NBBY);
sys/dev/usb/xhcireg.h
104
#define XHCI_HCC2_U3C(x) __SHIFTOUT((x), __BIT(0)) /* U3 Entry capable */
sys/dev/usb/xhcireg.h
105
#define XHCI_HCC2_CMC(x) __SHIFTOUT((x), __BIT(1)) /* CEC MaxExLatTooLg */
sys/dev/usb/xhcireg.h
106
#define XHCI_HCC2_FSC(x) __SHIFTOUT((x), __BIT(2)) /* Force Save Context */
sys/dev/usb/xhcireg.h
107
#define XHCI_HCC2_CTC(x) __SHIFTOUT((x), __BIT(3)) /* Compliance Transc */
sys/dev/usb/xhcireg.h
108
#define XHCI_HCC2_LEC(x) __SHIFTOUT((x), __BIT(4)) /* Large ESIT Payload */
sys/dev/usb/xhcireg.h
109
#define XHCI_HCC2_CIC(x) __SHIFTOUT((x), __BIT(5)) /* Configuration Inf */
sys/dev/usb/xhcireg.h
110
#define XHCI_HCC2_ETC(x) __SHIFTOUT((x), __BIT(6)) /* Extended TBC */
sys/dev/usb/xhcireg.h
111
#define XHCI_HCC2_ETC_TSC(x) __SHIFTOUT((x), __BIT(7)) /* ExtTBC TRB Status */
sys/dev/usb/xhcireg.h
112
#define XHCI_HCC2_GSC(x) __SHIFTOUT((x), __BIT(8)) /* Get/Set Extended Property */
sys/dev/usb/xhcireg.h
113
#define XHCI_HCC2_VTC(x) __SHIFTOUT((x), __BIT(9)) /* Virt. Based Trust */
sys/dev/usb/xhcireg.h
119
#define XHCI_CMD_RS __BIT(0) /* RW Run/Stop */
sys/dev/usb/xhcireg.h
120
#define XHCI_CMD_HCRST __BIT(1) /* RW Host Controller Reset */
sys/dev/usb/xhcireg.h
121
#define XHCI_CMD_INTE __BIT(2) /* RW Interrupter Enable */
sys/dev/usb/xhcireg.h
122
#define XHCI_CMD_HSEE __BIT(3) /* RW Host System Error Enable */
sys/dev/usb/xhcireg.h
123
#define XHCI_CMD_LHCRST __BIT(7) /* RO/RW Light Host Controller Reset */
sys/dev/usb/xhcireg.h
124
#define XHCI_CMD_CSS __BIT(8) /* RW Controller Save State */
sys/dev/usb/xhcireg.h
125
#define XHCI_CMD_CRS __BIT(9) /* RW Controller Restore State */
sys/dev/usb/xhcireg.h
126
#define XHCI_CMD_EWE __BIT(10) /* RW Enable Wrap Event */
sys/dev/usb/xhcireg.h
127
#define XHCI_CMD_EU3S __BIT(11) /* RW Enable U3 MFINDEX Stop */
sys/dev/usb/xhcireg.h
128
#define XHCI_CMD_CME __BIT(13) /* RW CEM Enable */
sys/dev/usb/xhcireg.h
129
#define XHCI_CMD_ETE __BIT(14) /* RW Extended TBC Enable */
sys/dev/usb/xhcireg.h
130
#define XHCI_CMD_TSC_EN __BIT(15) /* RW Extended TBC TRB Status Enable */
sys/dev/usb/xhcireg.h
131
#define XHCI_CMD_VTIOE __BIT(16) /* RW VTIO Enable */
sys/dev/usb/xhcireg.h
141
#define XHCI_STS_HCH __BIT(0) /* RO - Host Controller Halted */
sys/dev/usb/xhcireg.h
142
#define XHCI_STS_RSVDZ0 __BIT(1) /* RsvdZ - 1:1 */
sys/dev/usb/xhcireg.h
143
#define XHCI_STS_HSE __BIT(2) /* RW - Host System Error */
sys/dev/usb/xhcireg.h
144
#define XHCI_STS_EINT __BIT(3) /* RW - Event Interrupt */
sys/dev/usb/xhcireg.h
145
#define XHCI_STS_PCD __BIT(4) /* RW - Port Change Detect */
sys/dev/usb/xhcireg.h
147
#define XHCI_STS_SSS __BIT(8) /* RO - Save State Status */
sys/dev/usb/xhcireg.h
148
#define XHCI_STS_RSS __BIT(9) /* RO - Restore State Status */
sys/dev/usb/xhcireg.h
149
#define XHCI_STS_SRE __BIT(10) /* RW - Save/Restore Error */
sys/dev/usb/xhcireg.h
150
#define XHCI_STS_CNR __BIT(11) /* RO - Controller Not Ready */
sys/dev/usb/xhcireg.h
151
#define XHCI_STS_HCE __BIT(12) /* RO - Host Controller Error */
sys/dev/usb/xhcireg.h
155
#define XHCI_PAGESIZE_4K __BIT(0) /* 4K Page Size */
sys/dev/usb/xhcireg.h
156
#define XHCI_PAGESIZE_8K __BIT(1) /* 8K Page Size */
sys/dev/usb/xhcireg.h
157
#define XHCI_PAGESIZE_16K __BIT(2) /* 16K Page Size */
sys/dev/usb/xhcireg.h
158
#define XHCI_PAGESIZE_32K __BIT(3) /* 32K Page Size */
sys/dev/usb/xhcireg.h
159
#define XHCI_PAGESIZE_64K __BIT(4) /* 64K Page Size */
sys/dev/usb/xhcireg.h
160
#define XHCI_PAGESIZE_128K __BIT(5) /* 128K Page Size */
sys/dev/usb/xhcireg.h
161
#define XHCI_PAGESIZE_256K __BIT(6) /* 256K Page Size */
sys/dev/usb/xhcireg.h
162
#define XHCI_PAGESIZE_512K __BIT(7) /* 512K Page Size */
sys/dev/usb/xhcireg.h
163
#define XHCI_PAGESIZE_1M __BIT(8) /* 1M Page Size */
sys/dev/usb/xhcireg.h
164
#define XHCI_PAGESIZE_2M __BIT(9) /* 2M Page Size */
sys/dev/usb/xhcireg.h
168
#define XHCI_DNCTRL_MASK(n) __BIT((n))
sys/dev/usb/xhcireg.h
172
#define XHCI_CRCR_LO_RCS __BIT(0) /* RW - consumer cycle state */
sys/dev/usb/xhcireg.h
173
#define XHCI_CRCR_LO_CS __BIT(1) /* RW - command stop */
sys/dev/usb/xhcireg.h
174
#define XHCI_CRCR_LO_CA __BIT(2) /* RW - command abort */
sys/dev/usb/xhcireg.h
175
#define XHCI_CRCR_LO_CRR __BIT(3) /* RW - command ring running */
sys/dev/usb/xhcireg.h
187
#define XHCI_CONFIG_U3E __BIT(8) /* RW - U3 Entry Enable */
sys/dev/usb/xhcireg.h
188
#define XHCI_CONFIG_CIE __BIT(9) /* RW - Configuration Information Enable */
sys/dev/usb/xhcireg.h
192
#define XHCI_PS_CCS __BIT(0) /* RO - current connect status */
sys/dev/usb/xhcireg.h
193
#define XHCI_PS_PED __BIT(1) /* RW - port enabled / disabled */
sys/dev/usb/xhcireg.h
194
#define XHCI_PS_OCA __BIT(3) /* RO - over current active */
sys/dev/usb/xhcireg.h
195
#define XHCI_PS_PR __BIT(4) /* RW - port reset */
sys/dev/usb/xhcireg.h
221
#define XHCI_PS_PP __BIT(9) /* RW - port power */
sys/dev/usb/xhcireg.h
231
#define XHCI_PS_LWS __BIT(16) /* RW - port link state write strobe */
sys/dev/usb/xhcireg.h
232
#define XHCI_PS_CSC __BIT(17) /* RW - connect status change */
sys/dev/usb/xhcireg.h
233
#define XHCI_PS_PEC __BIT(18) /* RW - port enable/disable change */
sys/dev/usb/xhcireg.h
234
#define XHCI_PS_WRC __BIT(19) /* RW - warm port reset change */
sys/dev/usb/xhcireg.h
235
#define XHCI_PS_OCC __BIT(20) /* RW - over-current change */
sys/dev/usb/xhcireg.h
236
#define XHCI_PS_PRC __BIT(21) /* RW - port reset change */
sys/dev/usb/xhcireg.h
237
#define XHCI_PS_PLC __BIT(22) /* RW - port link state change */
sys/dev/usb/xhcireg.h
238
#define XHCI_PS_CEC __BIT(23) /* RW - config error change */
sys/dev/usb/xhcireg.h
239
#define XHCI_PS_CAS __BIT(24) /* RO - cold attach status */
sys/dev/usb/xhcireg.h
240
#define XHCI_PS_WCE __BIT(25) /* RW - wake on connect enable */
sys/dev/usb/xhcireg.h
241
#define XHCI_PS_WDE __BIT(26) /* RW - wake on disconnect enable */
sys/dev/usb/xhcireg.h
242
#define XHCI_PS_WOE __BIT(27) /* RW - wake on over-current enable */
sys/dev/usb/xhcireg.h
243
#define XHCI_PS_DR __BIT(30) /* RO - device removable */
sys/dev/usb/xhcireg.h
244
#define XHCI_PS_WPR __BIT(31) /* RW - warm port reset */
sys/dev/usb/xhcireg.h
256
#define XHCI_PM3_FLA __BIT(16) /* RW - Force Link PM Accept */
sys/dev/usb/xhcireg.h
261
#define XHCI_PM2_RWE __BIT(3) /* RW - remote wakeup enable */
sys/dev/usb/xhcireg.h
268
#define XHCI_PM2_HLE __BIT(16) /* RW - hardware LPM enable */
sys/dev/usb/xhcireg.h
298
#define XHCI_IMAN_INTR_PEND __BIT(0) /* RW - interrupt pending */
sys/dev/usb/xhcireg.h
299
#define XHCI_IMAN_INTR_ENA __BIT(1) /* RW - interrupt enable */
sys/dev/usb/xhcireg.h
321
#define XHCI_ERSTBA_MASK __BIT(31,6) /* RW - segment base address (low) */
sys/dev/usb/xhcireg.h
328
#define XHCI_ERDP_BUSY __BIT(3) /* RW - event handler busy */
sys/dev/usb/xhcireg.h
329
#define XHCI_ERDP_PTRLO_MASK __BIT(31,4) /* RW - dequeue pointer (low) */
sys/dev/usb/xhcireg.h
427
#define XHCI_TRB_3_CYCLE_BIT __BIT(0)
sys/dev/usb/xhcireg.h
428
#define XHCI_TRB_3_TC_BIT __BIT(1) /* command ring only */
sys/dev/usb/xhcireg.h
429
#define XHCI_TRB_3_ENT_BIT __BIT(1) /* transfer ring only */
sys/dev/usb/xhcireg.h
430
#define XHCI_TRB_3_ISP_BIT __BIT(2)
sys/dev/usb/xhcireg.h
431
#define XHCI_TRB_3_NSNOOP_BIT __BIT(3)
sys/dev/usb/xhcireg.h
432
#define XHCI_TRB_3_CHAIN_BIT __BIT(4)
sys/dev/usb/xhcireg.h
433
#define XHCI_TRB_3_IOC_BIT __BIT(5)
sys/dev/usb/xhcireg.h
434
#define XHCI_TRB_3_IDT_BIT __BIT(6)
sys/dev/usb/xhcireg.h
438
#define XHCI_TRB_3_BEI_BIT __BIT(9)
sys/dev/usb/xhcireg.h
439
#define XHCI_TRB_3_DCEP_BIT __BIT(9)
sys/dev/usb/xhcireg.h
440
#define XHCI_TRB_3_PRSV_BIT __BIT(9)
sys/dev/usb/xhcireg.h
441
#define XHCI_TRB_3_BSR_BIT __BIT(9)
sys/dev/usb/xhcireg.h
447
#define XHCI_TRB_3_DIR_IN __BIT(16)
sys/dev/usb/xhcireg.h
457
#define XHCI_TRB_3_ISO_SIA_BIT __BIT(31)
sys/dev/usb/xhcireg.h
458
#define XHCI_TRB_3_SUSP_EP_BIT __BIT(23)
sys/dev/usb/xhcireg.h
551
#define XHCI_SCTX_0_MTT_MASK __BIT(25)
sys/dev/usb/xhcireg.h
554
#define XHCI_SCTX_0_HUB_MASK __BIT(26)
sys/dev/usb/xhcireg.h
613
#define XHCI_EPCTX_0_LSA_MASK __BIT(15)
sys/dev/usb/xhcireg.h
629
#define XHCI_EPCTX_1_HID_MASK __BIT(7)
sys/dev/usb/xhcireg.h
640
#define XHCI_EPCTX_2_DCS_MASK __BIT(0)
sys/dev/usb/xhcireg.h
662
#define XHCI_INCTX_0_DROP_MASK(n) __BIT((n))
sys/dev/usb/xhcireg.h
664
#define XHCI_INCTX_1_ADD_MASK(n) __BIT((n))
sys/dev/usb/xhcireg.h
70
#define XHCI_HCS2_SPR_MASK __BIT(26)
sys/dev/usb/xhcireg.h
84
#define XHCI_HCC_AC64(x) __SHIFTOUT((x), __BIT(0)) /* 64-bit capable */
sys/dev/usb/xhcireg.h
85
#define XHCI_HCC_BNC(x) __SHIFTOUT((x), __BIT(1)) /* BW negotiation */
sys/dev/usb/xhcireg.h
86
#define XHCI_HCC_CSZ(x) __SHIFTOUT((x), __BIT(2)) /* context size */
sys/dev/usb/xhcireg.h
87
#define XHCI_HCC_PPC(x) __SHIFTOUT((x), __BIT(3)) /* port power control */
sys/dev/usb/xhcireg.h
88
#define XHCI_HCC_PIND(x) __SHIFTOUT((x), __BIT(4)) /* port indicators */
sys/dev/usb/xhcireg.h
89
#define XHCI_HCC_LHRC(x) __SHIFTOUT((x), __BIT(5)) /* light HC reset */
sys/dev/usb/xhcireg.h
90
#define XHCI_HCC_LTC(x) __SHIFTOUT((x), __BIT(6)) /* latency tolerance msg */
sys/dev/usb/xhcireg.h
91
#define XHCI_HCC_NSS(x) __SHIFTOUT((x), __BIT(7)) /* no secondary sid */
sys/dev/usb/xhcireg.h
92
#define XHCI_HCC_PAE(x) __SHIFTOUT((x), __BIT(8)) /* Parse All Event Data */
sys/dev/usb/xhcireg.h
93
#define XHCI_HCC_SPC(x) __SHIFTOUT((x), __BIT(9)) /* Short packet */
sys/dev/usb/xhcireg.h
94
#define XHCI_HCC_SEC(x) __SHIFTOUT((x), __BIT(10)) /* Stopped EDTLA */
sys/dev/usb/xhcireg.h
95
#define XHCI_HCC_CFC(x) __SHIFTOUT((x), __BIT(11)) /* Contiguous Frame ID */
sys/dev/usb/xhcivar.h
151
#define XHCI_QUIRK_INTEL __BIT(0) /* Intel xhci chip */
sys/dev/usb/xhcivar.h
152
#define XHCI_DEFERRED_START __BIT(1)
sys/dev/usb/xhcivar.h
153
#define XHCI_32BIT_ACCESS __BIT(2)
sys/dev/vmt/vmtreg.h
64
#define VCPUINFO_LEGACY_X2APIC __BIT(3)
sys/dev/vmt/vmtreg.h
65
#define VCPUINFO_VCPU_RESERVED __BIT(31)
sys/dev/vmt/vmtvar.h
148
#define X86_IO_W7_DIR __BIT(2)
sys/dev/vmt/vmtvar.h
149
#define X86_IO_W7_WITH __BIT(3)
sys/dev/vmt/vmtvar.h
150
#define X86_IO_W7_STR __BIT(4)
sys/dev/vmt/vmtvar.h
151
#define X86_IO_W7_DF __BIT(5)
sys/dev/wsfont/wsfont.c
480
#define BIT_FROM_LEFT(x) __BIT(7 - ((x) % 8))
sys/dev/wsfont/wsfont.c
481
#define BIT_FROM_RIGHT(x) __BIT((x) % 8)
sys/kern/kern_proc.c
151
#define PT_F_FREE ((uintptr_t)__BIT(0))
sys/kern/kern_proc.c
153
#define PT_F_PROC ((uintptr_t)__BIT(1))
sys/kern/subr_device.c
858
#define S8_BIT __BIT(7)
sys/kern/subr_device.c
860
#define S16_BIT __BIT(15)
sys/kern/subr_device.c
862
#define S32_BIT __BIT(31)
sys/kern/subr_kcpuset.c
363
kcp->bits[j] |= __BIT(i & KC_MASK);
sys/kern/subr_kcpuset.c
374
kcp->bits[j] &= ~(__BIT(i & KC_MASK));
sys/kern/subr_kcpuset.c
387
return ((__BIT(i & KC_MASK)) & kcp->bits[j]) != 0;
sys/kern/subr_kcpuset.c
394
const uint32_t mask = ~(__BIT(i & KC_MASK));
sys/kern/subr_kcpuset.c
506
atomic_or_32(&kcp->bits[j], __BIT(i & KC_MASK));
sys/kern/subr_kcpuset.c
515
atomic_and_32(&kcp->bits[j], ~(__BIT(i & KC_MASK)));
sys/kern/sys_futex.c
1441
return arg - 0x1000*__SHIFTOUT(arg, __BIT(11));
sys/kern/sys_select.c
1011
sc->sc_mask = __BIT(index);
sys/kern/sys_select.c
931
mask ^= __BIT(index);
sys/net/if.h
483
#define IFEF_MPSAFE __BIT(0) /* handlers can run in parallel (see below) */
sys/net/if_ether.h
248
#define ETHER_F_ALLMULTI __BIT(0)
sys/net/if_sppp.h
183
#define SPPP_LCP_OPT_MRU __BIT(1)
sys/net/if_sppp.h
184
#define SPPP_LCP_OPT_ASYNC_MAP __BIT(2)
sys/net/if_sppp.h
185
#define SPPP_LCP_OPT_AUTH_PROTO __BIT(3)
sys/net/if_sppp.h
186
#define SPPP_LCP_OPT_QUAL_PROTO __BIT(4)
sys/net/if_sppp.h
187
#define SPPP_LCP_OPT_MAGIC __BIT(5)
sys/net/if_sppp.h
188
#define SPPP_LCP_OPT_RESERVED __BIT(6)
sys/net/if_sppp.h
189
#define SPPP_LCP_OPT_PROTO_COMP __BIT(7)
sys/net/if_sppp.h
190
#define SPPP_LCP_OPT_ADDR_COMP __BIT(8)
sys/net/if_sppp.h
191
#define SPPP_LCP_OPT_FCS_ALTS __BIT(9)
sys/net/if_sppp.h
192
#define SPPP_LCP_OPT_SELF_DESC_PAD __BIT(10)
sys/net/if_sppp.h
193
#define SPPP_LCP_OPT_CALL_BACK __BIT(13)
sys/net/if_sppp.h
194
#define SPPP_LCP_OPT_COMPOUND_FRMS __BIT(15)
sys/net/if_sppp.h
195
#define SPPP_LCP_OPT_MP_MRRU __BIT(17)
sys/net/if_sppp.h
196
#define SPPP_LCP_OPT_MP_SSNHF __BIT(18)
sys/net/if_sppp.h
197
#define SPPP_LCP_OPT_MP_EID __BIT(19)
sys/net/if_sppp.h
200
#define SPPP_IPCP_OPT_COMPRESSION __BIT(1)
sys/net/if_sppp.h
201
#define SPPP_IPCP_OPT_ADDRESS __BIT(2)
sys/net/if_sppp.h
202
#define SPPP_IPCP_OPT_PRIMDNS __BIT(3)
sys/net/if_sppp.h
203
#define SPPP_IPCP_OPT_SECDNS __BIT(4)
sys/net/if_sppp.h
205
#define SPPP_IPV6CP_OPT_IFID __BIT(1)
sys/net/if_sppp.h
206
#define SPPP_IPV6CP_OPT_COMPRESSION __BIT(2)
sys/net/if_sppp.h
238
#define SPPP_NCP_IPCP __BIT(0)
sys/net/if_sppp.h
239
#define SPPP_NCP_IPV6CP __BIT(1)
sys/net/if_spppsubr.c
297
SPPP_AUTH_SERV = __BIT(0),
sys/net/if_spppsubr.c
298
SPPP_AUTH_PEER = __BIT(1),
sys/net/if_spppvar.h
144
#define PP_DEVF_KEEPALIVE __BIT(0) /* use keepalive protocol */
sys/net/if_spppvar.h
145
#define PP_DEVF_NOFRAMING __BIT(1) /* do not add/expect encapsulation
sys/net/if_wg.c
673
#define WGP_TASK_SEND_INIT_MESSAGE __BIT(0)
sys/net/if_wg.c
674
#define WGP_TASK_RETRY_HANDSHAKE __BIT(1)
sys/net/if_wg.c
675
#define WGP_TASK_ESTABLISH_SESSION __BIT(2)
sys/net/if_wg.c
676
#define WGP_TASK_ENDPOINT_CHANGED __BIT(3)
sys/net/if_wg.c
677
#define WGP_TASK_SEND_KEEPALIVE_MESSAGE __BIT(4)
sys/net/if_wg.c
678
#define WGP_TASK_DESTROY_PREV_SESSION __BIT(5)
sys/net/if_wg.c
705
#define WG_UPCALL_INET __BIT(0)
sys/net/if_wg.c
706
#define WG_UPCALL_INET6 __BIT(1)
sys/net/if_wg.h
38
#define WG_IOCTL_SET_PRIVATE_KEY __BIT(0)
sys/net/if_wg.h
39
#define WG_IOCTL_SET_LISTEN_PORT __BIT(1)
sys/net/if_wg.h
40
#define WG_IOCTL_ADD_PEER __BIT(2)
sys/net/if_wg.h
41
#define WG_IOCTL_DELETE_PEER __BIT(3)
sys/net/lagg/if_lagg.h
116
#define LAGGREQFAIL_RXALL __BIT(0)
sys/net/lagg/if_lagg.h
133
#define LAGG_PORT_MASTER __BIT(0)
sys/net/lagg/if_lagg.h
134
#define LAGG_PORT_STACK __BIT(1)
sys/net/lagg/if_lagg.h
135
#define LAGG_PORT_ACTIVE __BIT(2)
sys/net/lagg/if_lagg.h
136
#define LAGG_PORT_COLLECTING __BIT(3)
sys/net/lagg/if_lagg.h
137
#define LAGG_PORT_DISTRIBUTING __BIT(4)
sys/net/lagg/if_lagg.h
138
#define LAGG_PORT_STANDBY __BIT(5)
sys/net/lagg/if_lagg.h
59
#define LACP_STATE_ACTIVITY __BIT(0)
sys/net/lagg/if_lagg.h
60
#define LACP_STATE_TIMEOUT __BIT(1)
sys/net/lagg/if_lagg.h
61
#define LACP_STATE_AGGREGATION __BIT(2)
sys/net/lagg/if_lagg.h
62
#define LACP_STATE_SYNC __BIT(3)
sys/net/lagg/if_lagg.h
63
#define LACP_STATE_COLLECTING __BIT(4)
sys/net/lagg/if_lagg.h
64
#define LACP_STATE_DISTRIBUTING __BIT(5)
sys/net/lagg/if_lagg.h
65
#define LACP_STATE_DEFAULTED __BIT(6)
sys/net/lagg/if_lagg.h
66
#define LACP_STATE_EXPIRED __BIT(7)
sys/net/lagg/if_lagg.h
87
#define LAGGREQLACP_OPTIMISTIC __BIT(0)
sys/net/lagg/if_lagg.h
88
#define LAGGREQLACP_DUMPDU __BIT(1)
sys/net/lagg/if_lagg.h
89
#define LAGGREQLACP_STOPDU __BIT(2)
sys/net/lagg/if_lagg.h
90
#define LAGGREQLACP_MULTILS __BIT(3)
sys/net/lagg/if_lagg_lacp.c
138
#define LACP_PORT_NTT __BIT(0)
sys/net/lagg/if_lagg_lacp.c
139
#define LACP_PORT_MARK __BIT(1)
sys/net/rss_config.h
34
#define RSS_TOEPLITZ_USE_TCP_PORT __BIT(0)
sys/net/rss_config.h
35
#define RSS_TOEPLITZ_USE_UDP_PORT __BIT(1)
sys/net/toeplitz.c
293
if (data & __BIT(x)) \
sys/net/toeplitz.c
296
if (key & __BIT(x)) \
sys/netinet/ip_encap.h
100
#define IP_ENCAP_ADDR_ENABLE __BIT(0)
sys/sys/bus.h
67
BUS_SPACE_OVERRIDE_MAP = __BIT(0)
sys/sys/bus.h
68
, BUS_SPACE_OVERRIDE_UNMAP = __BIT(1)
sys/sys/bus.h
69
, BUS_SPACE_OVERRIDE_ALLOC = __BIT(2)
sys/sys/bus.h
70
, BUS_SPACE_OVERRIDE_FREE = __BIT(3)
sys/sys/bus.h
71
, BUS_SPACE_OVERRIDE_RESERVE = __BIT(4)
sys/sys/bus.h
72
, BUS_SPACE_OVERRIDE_RELEASE = __BIT(5)
sys/sys/bus.h
73
, BUS_SPACE_OVERRIDE_RESERVATION_MAP = __BIT(6)
sys/sys/bus.h
74
, BUS_SPACE_OVERRIDE_RESERVATION_UNMAP = __BIT(7)
sys/sys/bus.h
75
, BUS_SPACE_OVERRIDE_RESERVE_SUBREGION = __BIT(8)
sys/sys/bus.h
77
, BUS_SPACE_OVERRIDE_EXTEND = __BIT(9)
sys/sys/bus.h
78
, BUS_SPACE_OVERRIDE_TRIM = __BIT(10)
sys/sys/bus.h
83
BUS_DMAMAP_OVERRIDE_CREATE = __BIT(0)
sys/sys/bus.h
84
, BUS_DMAMAP_OVERRIDE_DESTROY = __BIT(1)
sys/sys/bus.h
85
, BUS_DMAMAP_OVERRIDE_LOAD = __BIT(2)
sys/sys/bus.h
86
, BUS_DMAMAP_OVERRIDE_LOAD_MBUF = __BIT(3)
sys/sys/bus.h
87
, BUS_DMAMAP_OVERRIDE_LOAD_UIO = __BIT(4)
sys/sys/bus.h
88
, BUS_DMAMAP_OVERRIDE_LOAD_RAW = __BIT(5)
sys/sys/bus.h
89
, BUS_DMAMAP_OVERRIDE_UNLOAD = __BIT(6)
sys/sys/bus.h
90
, BUS_DMAMAP_OVERRIDE_SYNC = __BIT(7)
sys/sys/bus.h
91
, BUS_DMAMEM_OVERRIDE_ALLOC = __BIT(8)
sys/sys/bus.h
92
, BUS_DMAMEM_OVERRIDE_FREE = __BIT(9)
sys/sys/bus.h
93
, BUS_DMAMEM_OVERRIDE_MAP = __BIT(10)
sys/sys/bus.h
94
, BUS_DMAMEM_OVERRIDE_UNMAP = __BIT(11)
sys/sys/bus.h
95
, BUS_DMAMEM_OVERRIDE_MMAP = __BIT(12)
sys/sys/bus.h
96
, BUS_DMATAG_OVERRIDE_SUBREGION = __BIT(13)
sys/sys/bus.h
97
, BUS_DMATAG_OVERRIDE_DESTROY = __BIT(14)
sys/sys/cdefs.h
663
#define __MASK(__n) (__BIT(__n) - 1)
sys/sys/cdefs.h
671
((__BIT(__MAX((__m), (__n)) + 1) - 1) ^ (__BIT(__MIN((__m), (__n))) - 1))
sys/sys/event.h
240
#define FILTEROP_ISFD __BIT(0) /* ident == file descriptor */
sys/sys/event.h
241
#define FILTEROP_MPSAFE __BIT(1) /* does not require KERNEL_LOCK */
sys/sys/eventvar.h
57
#define KQ_RESTART __BIT(31) /* force ERESTART */
sys/sys/eventvar.h
58
#define KQ_CLOSING __BIT(30) /* kqueue is closing for good */
sys/sys/extent.h
74
#define EXF_FIXED __BIT(0) /* extent uses fixed storage */
sys/sys/extent.h
75
#define EXF_NOCOALESCE __BIT(1) /* coalescing of regions not allowed */
sys/sys/extent.h
76
#define EXF_EARLY __BIT(2) /* no need to lock */
sys/sys/extent.h
82
#define EX_WAITOK __BIT(0) /* safe to sleep */
sys/sys/extent.h
83
#define EX_FAST __BIT(1) /* take first fit in extent_alloc() */
sys/sys/extent.h
84
#define EX_CATCH __BIT(2) /* catch signals while sleeping */
sys/sys/extent.h
85
#define EX_NOCOALESCE __BIT(3) /* create a non-coalescing extent */
sys/sys/extent.h
86
#define EX_MALLOCOK __BIT(4) /* safe to call kmem_alloc() */
sys/sys/extent.h
87
#define EX_WAITSPACE __BIT(5) /* wait for space to become free */
sys/sys/extent.h
88
#define EX_BOUNDZERO __BIT(6) /* boundary lines start at 0 */
sys/sys/extent.h
89
#define EX_EARLY __BIT(7) /* safe for early kernel bootstrap */
sys/sys/futex.h
127
#define FUTEX_WAITERS ((int)__BIT(31))
sys/sys/futex.h
128
#define FUTEX_OWNER_DIED ((int)__BIT(30))
sys/sys/futex.h
129
#define FUTEX_SYNCOBJ_1 ((int)__BIT(29))
sys/sys/futex.h
130
#define FUTEX_SYNCOBJ_0 ((int)__BIT(28))
sys/sys/futex.h
159
#define _FUTEX_ROBUST_ENTRY_PI __BIT(0)
sys/sys/futex.h
89
#define FUTEX_PRIVATE_FLAG __BIT(7)
sys/sys/futex.h
90
#define FUTEX_CLOCK_REALTIME __BIT(8)
sys/sys/kernhist.h
117
#define KERNHIST_UVMMAPHIST __BIT(0) /* maphist */
sys/sys/kernhist.h
118
#define KERNHIST_UVMPDHIST __BIT(1) /* pdhist */
sys/sys/kernhist.h
119
#define KERNHIST_UVMUBCHIST __BIT(2) /* ubchist */
sys/sys/kernhist.h
120
#define KERNHIST_UVMLOANHIST __BIT(3) /* loanhist */
sys/sys/kernhist.h
121
#define KERNHIST_USBHIST __BIT(4) /* usbhist */
sys/sys/kernhist.h
122
#define KERNHIST_SCDEBUGHIST __BIT(5) /* scdebughist */
sys/sys/kernhist.h
123
#define KERNHIST_BIOHIST __BIT(6) /* biohist */
sys/uvm/pmap/pmap.c
2182
colors |= __BIT(atop(pv->pv_va) & colormask);
sys/uvm/pmap/pmap.h
227
#define PMAP_DEFERRED_ACTIVATE __BIT(0)
sys/uvm/pmap/vmpagemd.h
63
#define PV_KENTER __BIT(0)
sys/uvm/pmap/vmpagemd.h
70
#define VM_PAGEMD_VMPAGE __BIT(0) /* page is vm managed */
sys/uvm/pmap/vmpagemd.h
71
#define VM_PAGEMD_REFERENCED __BIT(1) /* page has been referenced */
sys/uvm/pmap/vmpagemd.h
72
#define VM_PAGEMD_MODIFIED __BIT(2) /* page has been modified */
sys/uvm/pmap/vmpagemd.h
73
#define VM_PAGEMD_POOLPAGE __BIT(3) /* page is used as a poolpage */
sys/uvm/pmap/vmpagemd.h
74
#define VM_PAGEMD_EXECPAGE __BIT(4) /* page is exec mapped */
sys/uvm/pmap/vmpagemd.h
76
#define VM_PAGEMD_UNCACHED __BIT(5) /* page is mapped uncached */
tests/include/t_paths.c
46
#define PATH_DEV __BIT(0) /* A device node */
tests/include/t_paths.c
47
#define PATH_DIR __BIT(1) /* A directory */
tests/include/t_paths.c
48
#define PATH_FILE __BIT(2) /* A file */
tests/include/t_paths.c
49
#define PATH_ROOT __BIT(3) /* Access for root only */
tests/include/t_paths.c
50
#define PATH_OPT __BIT(3) /* Optional, ENODEV if not supported */
tests/kernel/arch/hppa/execregs.c
64
| __BIT(58) /* C bit (comparison) set */
tests/kernel/arch/hppa/execregs.c
67
| __SHIFTIN(0, __BIT(38)) /* no delayed trap */
tests/kernel/arch/hppa/execregs.c
68
| __SHIFTIN(1, __BIT(37)) /* Denormalized As Zero */
tests/kernel/arch/x86/sig_fpu.c
111
return cpuid(0x00000001, 0).edx & __BIT(0);
tests/kernel/arch/x86/sig_fpu.c
253
#define MXCSR_MISALIGNEDEXC __BIT(17) /* misaligned exc fault */
tests/kernel/arch/x86/sig_fpu.c
254
#define MXCSR_FTZ __BIT(15) /* flush to zero */
tests/kernel/arch/x86/sig_fpu.c
257
#define MXCSR_DAZ __BIT(6) /* denormals are zero */
tests/kernel/arch/x86/sig_fpu.c
273
return cpuid(0x00000001, 0).edx & __BIT(25);
tests/kernel/arch/x86/sig_fpu.c
427
return cpuid(0x00000001, 0).ecx & __BIT(28);
tests/kernel/arch/x86/sig_fpu.c
565
return cpuid(0x00000007, 0).ebx & __BIT(16);
tests/lib/libc/gen/t_fpclassify.c
100
# define DBL_SNANBIT (SNANBIT*__BIT(DBL_MANT_DIG - 2))
tests/lib/libc/gen/t_fpclassify.c
126
(QNANBIT*__BIT(LDBL_MANT_DIG - 2 - EXT_FRACLBITS))
tests/lib/libc/gen/t_fpclassify.c
128
(SNANBIT*__BIT(LDBL_MANT_DIG - 2 - EXT_FRACLBITS))
tests/lib/libc/gen/t_fpclassify.c
77
# define FLT_QNANBIT (QNANBIT*__BIT(FLT_MANT_DIG - 2))
tests/lib/libc/gen/t_fpclassify.c
78
# define FLT_SNANBIT (SNANBIT*__BIT(FLT_MANT_DIG - 2))
tests/lib/libc/gen/t_fpclassify.c
99
# define DBL_QNANBIT (QNANBIT*__BIT(DBL_MANT_DIG - 2))
tests/lib/libc/sys/t_futex_ops.c
664
lwp_data[i].bitset = __BIT(i);
tests/lib/libc/sys/t_wait_noproc.c
161
if (pos & __BIT(n))
tests/lib/libc/sys/t_wait_noproc.c
208
if (pos & __BIT(n))
usr.sbin/bta2dpd/bta2dpd/sbc_encode.c
187
while (!(x & __BIT(30))) {
usr.sbin/bta2dpd/bta2dpd/sbc_encode.c
194
while (!(y & __BIT(30))) {
usr.sbin/bta2dpd/bta2dpd/sbc_encode.c
233
while (!(x & __BIT(30))) {
usr.sbin/btconfig/btconfig.c
1035
if (class & __BIT(13)) tag("<Limited Discoverable>");
usr.sbin/btconfig/btconfig.c
1036
if (class & __BIT(16)) tag("<Positioning>");
usr.sbin/btconfig/btconfig.c
1037
if (class & __BIT(17)) tag("<Networking>");
usr.sbin/btconfig/btconfig.c
1038
if (class & __BIT(18)) tag("<Rendering>");
usr.sbin/btconfig/btconfig.c
1039
if (class & __BIT(19)) tag("<Capturing>");
usr.sbin/btconfig/btconfig.c
1040
if (class & __BIT(20)) tag("<Object Transfer>");
usr.sbin/btconfig/btconfig.c
1041
if (class & __BIT(21)) tag("<Audio>");
usr.sbin/btconfig/btconfig.c
1042
if (class & __BIT(22)) tag("<Telephony>");
usr.sbin/btconfig/btconfig.c
1043
if (class & __BIT(23)) tag("<Information>");
usr.sbin/btconfig/btconfig.c
984
if (class & __BIT(6)) tag("Keyboard");
usr.sbin/btconfig/btconfig.c
985
if (class & __BIT(7)) tag("Mouse");
usr.sbin/btconfig/btconfig.c
989
if (class & __BIT(4)) tag("Display");
usr.sbin/btconfig/btconfig.c
990
if (class & __BIT(5)) tag("Camera");
usr.sbin/btconfig/btconfig.c
991
if (class & __BIT(6)) tag("Scanner");
usr.sbin/btconfig/btconfig.c
992
if (class & __BIT(7)) tag("Printer");
usr.sbin/tprof/arch/tprof_x86.c
1094
{ "ExRetMmxFpInstr@X87", 0xcb, __BIT(0), true },
usr.sbin/tprof/arch/tprof_x86.c
1095
{ "ExRetMmxFpInstr@Mmx", 0xcb, __BIT(1), true },
usr.sbin/tprof/arch/tprof_x86.c
1096
{ "ExRetMmxFpInstr@Sse", 0xcb, __BIT(2), true },
usr.sbin/tprof/arch/tprof_x86.c
1136
{ "LsBadStatus2", 0x24, __BIT(1), true },
usr.sbin/tprof/arch/tprof_x86.c
1137
{ "LsLocks", 0x25, __BIT(0), true },
usr.sbin/tprof/arch/tprof_x86.c
1144
{ "LsStCommitCancel2", 0x37, __BIT(0), true },
usr.sbin/tprof/arch/tprof_x86.c
1154
{ "LsMisalLoads-MA64", 0x47, __BIT(0), true },
usr.sbin/tprof/arch/tprof_x86.c
1155
{ "LsMisalLoads-MA4K", 0x47, __BIT(1), true },
usr.sbin/tprof/arch/tprof_x86.c
1171
{ "LsNotHaltedP0Cyc", 0x120, __BIT(0), true },
usr.sbin/tprof/arch/tprof_x86.c
1176
{ "BpL1TlbMissL2TlbMiss-IF4K", 0x85, __BIT(0), true },
usr.sbin/tprof/arch/tprof_x86.c
1177
{ "BpL1TlbMissL2TlbMiss-IF2M", 0x85, __BIT(1), true },
usr.sbin/tprof/arch/tprof_x86.c
1178
{ "BpL1TlbMissL2TlbMiss-IF1G", 0x85, __BIT(2), true },
usr.sbin/tprof/arch/tprof_x86.c
1179
{ "BpL1TlbMissL2TlbMiss-Coalesced4K", 0x85, __BIT(3), true },
usr.sbin/tprof/arch/tprof_x86.c
1185
{ "BpL1TlbFetchHit-IF4K", 0x94, __BIT(0), true },
usr.sbin/tprof/arch/tprof_x86.c
1186
{ "BpL1TlbFetchHit-IF2M", 0x94, __BIT(1), true },
usr.sbin/tprof/arch/tprof_x86.c
1187
{ "BpL1TlbFetchHit-IF1G", 0x94, __BIT(2), true },
usr.sbin/tprof/arch/tprof_x86.c
1233
{ "ExRetMmxFpInstr@X87", 0xcb, __BIT(0), true },
usr.sbin/tprof/arch/tprof_x86.c
1234
{ "ExRetMmxFpInstr@Mmx", 0xcb, __BIT(1), true },
usr.sbin/tprof/arch/tprof_x86.c
1235
{ "ExRetMmxFpInstr@Sse", 0xcb, __BIT(2), true },
usr.sbin/tprof/arch/tprof_x86.c
1270
{ "L3LookupState-L3Miss", 0x04, __BIT(0), true },
