arch/arc/include/asm/io.h
205
#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
arch/arm/common/sa1111.c
1007
writel_relaxed(val | SKCR_SLEEP, sachip->base + SA1111_SKCR);
arch/arm/common/sa1111.c
1068
writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN0);
arch/arm/common/sa1111.c
1069
writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN1);
arch/arm/common/sa1111.c
1072
writel_relaxed(save->skcr, base + SA1111_SKCR);
arch/arm/common/sa1111.c
1073
writel_relaxed(save->skpcr, base + SA1111_SKPCR);
arch/arm/common/sa1111.c
1074
writel_relaxed(save->skcdr, base + SA1111_SKCDR);
arch/arm/common/sa1111.c
1075
writel_relaxed(save->skaud, base + SA1111_SKAUD);
arch/arm/common/sa1111.c
1076
writel_relaxed(save->skpwm0, base + SA1111_SKPWM0);
arch/arm/common/sa1111.c
1077
writel_relaxed(save->skpwm1, base + SA1111_SKPWM1);
arch/arm/common/sa1111.c
1080
writel_relaxed(save->intpol0, base + SA1111_INTPOL0);
arch/arm/common/sa1111.c
1081
writel_relaxed(save->intpol1, base + SA1111_INTPOL1);
arch/arm/common/sa1111.c
1082
writel_relaxed(save->inten0, base + SA1111_INTEN0);
arch/arm/common/sa1111.c
1083
writel_relaxed(save->inten1, base + SA1111_INTEN1);
arch/arm/common/sa1111.c
1084
writel_relaxed(save->wakepol0, base + SA1111_WAKEPOL0);
arch/arm/common/sa1111.c
1085
writel_relaxed(save->wakepol1, base + SA1111_WAKEPOL1);
arch/arm/common/sa1111.c
1086
writel_relaxed(save->wakeen0, base + SA1111_WAKEEN0);
arch/arm/common/sa1111.c
1087
writel_relaxed(save->wakeen1, base + SA1111_WAKEEN1);
arch/arm/common/sa1111.c
1234
writel_relaxed(val, sachip->base + SA1111_SKCR);
arch/arm/common/sa1111.c
1259
writel_relaxed(div - 1, sachip->base + SA1111_SKAUD);
arch/arm/common/sa1111.c
1304
writel_relaxed(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
arch/arm/common/sa1111.c
1323
writel_relaxed(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
arch/arm/common/sa1111.c
217
writel_relaxed(stat0, mapbase + SA1111_INTSTATCLR0);
arch/arm/common/sa1111.c
221
writel_relaxed(stat1, mapbase + SA1111_INTSTATCLR1);
arch/arm/common/sa1111.c
275
writel_relaxed(ie, mapbase + SA1111_INTEN0);
arch/arm/common/sa1111.c
294
writel_relaxed(ip ^ mask, mapbase + SA1111_INTPOL0);
arch/arm/common/sa1111.c
295
writel_relaxed(ip, mapbase + SA1111_INTPOL0);
arch/arm/common/sa1111.c
326
writel_relaxed(ip, mapbase + SA1111_INTPOL0);
arch/arm/common/sa1111.c
327
writel_relaxed(ip, mapbase + SA1111_WAKEPOL0);
arch/arm/common/sa1111.c
343
writel_relaxed(we, mapbase + SA1111_WAKEEN0);
arch/arm/common/sa1111.c
401
writel_relaxed(0, irqbase + SA1111_INTEN0);
arch/arm/common/sa1111.c
402
writel_relaxed(0, irqbase + SA1111_INTEN1);
arch/arm/common/sa1111.c
403
writel_relaxed(0, irqbase + SA1111_WAKEEN0);
arch/arm/common/sa1111.c
404
writel_relaxed(0, irqbase + SA1111_WAKEEN1);
arch/arm/common/sa1111.c
410
writel_relaxed(0, irqbase + SA1111_INTPOL0);
arch/arm/common/sa1111.c
411
writel_relaxed(BIT(IRQ_S0_READY_NINT & 31) |
arch/arm/common/sa1111.c
416
writel_relaxed(~0, irqbase + SA1111_INTSTATCLR0);
arch/arm/common/sa1111.c
417
writel_relaxed(~0, irqbase + SA1111_INTSTATCLR1);
arch/arm/common/sa1111.c
455
writel_relaxed(0, irqbase + SA1111_INTEN0);
arch/arm/common/sa1111.c
456
writel_relaxed(0, irqbase + SA1111_INTEN1);
arch/arm/common/sa1111.c
457
writel_relaxed(0, irqbase + SA1111_WAKEEN0);
arch/arm/common/sa1111.c
458
writel_relaxed(0, irqbase + SA1111_WAKEEN1);
arch/arm/common/sa1111.c
512
writel_relaxed(val, reg);
arch/arm/common/sa1111.c
656
writel_relaxed(r, sachip->base + SA1111_SKCR);
arch/arm/common/sa1111.c
658
writel_relaxed(r, sachip->base + SA1111_SKCR);
arch/arm/common/sa1111.c
670
writel_relaxed(r, sachip->base + SA1111_SKCR);
arch/arm/common/sa1111.c
681
writel_relaxed(0, sachip->base + SA1111_SKPCR);
arch/arm/common/sa1111.c
711
writel_relaxed(smcr, sachip->base + SA1111_SMCR);
arch/arm/common/sa1111.c
886
writel_relaxed(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR);
arch/arm/common/sa1111.c
990
writel_relaxed(0, sachip->base + SA1111_SKPWM0);
arch/arm/common/sa1111.c
991
writel_relaxed(0, sachip->base + SA1111_SKPWM1);
arch/arm/include/asm/arch_gicv3.h
146
writel_relaxed((u32)val, addr);
arch/arm/include/asm/arch_gicv3.h
147
writel_relaxed((u32)(val >> 32), addr + 4);
arch/arm/include/asm/arch_gicv3.h
191
#define gic_write_lpir(v, c) writel_relaxed(lower_32_bits(v), c)
arch/arm/include/asm/arch_gicv3.h
226
writel_relaxed(tmp, addr + 4);
arch/arm/include/asm/io.h
290
#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
arch/arm/kernel/io.c
23
writel_relaxed(value, reg);
arch/arm/kernel/smp_scu.c
47
writel_relaxed(scu_ctrl | 0x1, scu_base + 0x30);
arch/arm/kernel/smp_scu.c
63
writel_relaxed(scu_ctrl, scu_base + SCU_CTRL);
arch/arm/kernel/smp_twd.c
162
writel_relaxed(0x1, twd_base + TWD_TIMER_CONTROL);
arch/arm/kernel/smp_twd.c
165
writel_relaxed(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
arch/arm/kernel/smp_twd.c
228
writel_relaxed(0, twd_base + TWD_TIMER_CONTROL);
arch/arm/kernel/smp_twd.c
241
writel_relaxed(0, twd_base + TWD_TIMER_CONTROL);
arch/arm/kernel/smp_twd.c
39
writel_relaxed(0, twd_base + TWD_TIMER_CONTROL);
arch/arm/kernel/smp_twd.c
46
writel_relaxed(TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT,
arch/arm/kernel/smp_twd.c
57
writel_relaxed(DIV_ROUND_CLOSEST(twd_timer_rate, HZ),
arch/arm/kernel/smp_twd.c
59
writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL);
arch/arm/kernel/smp_twd.c
70
writel_relaxed(evt, twd_base + TWD_TIMER_COUNTER);
arch/arm/kernel/smp_twd.c
71
writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL);
arch/arm/kernel/smp_twd.c
85
writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
arch/arm/mach-aspeed/platsmp.c
25
writel_relaxed(0, base + BOOT_ADDR);
arch/arm/mach-aspeed/platsmp.c
26
writel_relaxed(__pa_symbol(secondary_startup_arm), base + BOOT_ADDR);
arch/arm/mach-aspeed/platsmp.c
27
writel_relaxed((0xABBAAB00 | (cpu & 0xff)), base + BOOT_SIG);
arch/arm/mach-axxia/platsmp.c
25
writel_relaxed(__pa_symbol(secondary_startup), virt);
arch/arm/mach-bcm/bcm63xx_smp.c
138
writel_relaxed(val, bootlut_base + BOOTLUT_RESET_VECT);
arch/arm/mach-bcm/bcm_kona_smc.c
127
writel_relaxed(data->arg0, args++);
arch/arm/mach-bcm/bcm_kona_smc.c
128
writel_relaxed(data->arg1, args++);
arch/arm/mach-bcm/bcm_kona_smc.c
129
writel_relaxed(data->arg2, args++);
arch/arm/mach-bcm/platsmp-brcmstb.c
127
writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
arch/arm/mach-bcm/platsmp-brcmstb.c
133
writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
arch/arm/mach-bcm/platsmp-brcmstb.c
134
writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
arch/arm/mach-bcm/platsmp.c
118
writel_relaxed(secondary_startup_phy, sku_rom_lut);
arch/arm/mach-bcm/platsmp.c
194
writel_relaxed(boot_val, boot_reg);
arch/arm/mach-bcm/platsmp.c
256
writel_relaxed(CDC_CMD, cdc_base + CDC_CMD_REG(cpu));
arch/arm/mach-exynos/common.h
165
writel_relaxed(val, pmu_base_addr + offset);
arch/arm/mach-exynos/firmware.c
251
writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
arch/arm/mach-exynos/firmware.c
260
writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
arch/arm/mach-exynos/firmware.c
40
writel_relaxed(__pa_symbol(exynos_cpu_resume_ns),
arch/arm/mach-exynos/firmware.c
42
writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
arch/arm/mach-exynos/firmware.c
99
writel_relaxed(boot_addr, boot_reg);
arch/arm/mach-exynos/platsmp.c
285
writel_relaxed(boot_addr, boot_reg);
arch/arm/mach-exynos/pm.c
129
writel_relaxed(__pa_symbol(exynos_cpu_resume),
arch/arm/mach-exynos/pm.c
131
writel_relaxed(flags, exynos_boot_vector_flag());
arch/arm/mach-exynos/suspend.c
345
writel_relaxed(0x0, pm_state.sysram_base + EXYNOS5420_CPU_STATE);
arch/arm/mach-exynos/suspend.c
486
writel_relaxed(pm_state.cpu_state,
arch/arm/mach-highbank/sysregs.h
33
writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
arch/arm/mach-highbank/sysregs.h
42
writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu));
arch/arm/mach-hisi/hotplug.c
106
writel_relaxed(val, ctrl_base + SCPERCTRL0);
arch/arm/mach-hisi/hotplug.c
111
writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
arch/arm/mach-hisi/hotplug.c
116
writel_relaxed(val, ctrl_base + SCPERCTRL0);
arch/arm/mach-hisi/hotplug.c
119
writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS);
arch/arm/mach-hisi/hotplug.c
123
writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
arch/arm/mach-hisi/hotplug.c
131
writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
arch/arm/mach-hisi/hotplug.c
135
writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
arch/arm/mach-hisi/hotplug.c
203
writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
arch/arm/mach-hisi/hotplug.c
207
writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
arch/arm/mach-hisi/hotplug.c
213
writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
arch/arm/mach-hisi/hotplug.c
218
writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
arch/arm/mach-hisi/hotplug.c
239
writel_relaxed(temp, ctrl_base + HIP01_PERI9);
arch/arm/mach-hisi/hotplug.c
246
writel_relaxed(temp, ctrl_base + HIP01_PERI9);
arch/arm/mach-hisi/hotplug.c
82
writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
arch/arm/mach-hisi/hotplug.c
87
writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN);
arch/arm/mach-hisi/hotplug.c
92
writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
arch/arm/mach-hisi/hotplug.c
95
writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
arch/arm/mach-hisi/hotplug.c
99
writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
arch/arm/mach-hisi/platmcpm.c
122
writel_relaxed(data, sys_dreq);
arch/arm/mach-hisi/platmcpm.c
132
writel_relaxed(data, sys_dreq);
arch/arm/mach-hisi/platmcpm.c
220
writel_relaxed(data, sysctrl + SC_CPU_RESET_REQ(cluster));
arch/arm/mach-hisi/platmcpm.c
327
writel_relaxed(hip04_boot_method[0], relocation);
arch/arm/mach-hisi/platmcpm.c
328
writel_relaxed(0xa5a5a5a5, relocation + 4); /* magic number */
arch/arm/mach-hisi/platmcpm.c
329
writel_relaxed(__pa_symbol(secondary_startup), relocation + 8);
arch/arm/mach-hisi/platmcpm.c
330
writel_relaxed(0, relocation + 12);
arch/arm/mach-hisi/platmcpm.c
92
writel_relaxed(data, fabric + FAB_SF_MODE);
arch/arm/mach-hisi/platsmp.c
112
writel_relaxed(0xe51ff004, virt); /* ldr pc, [pc, #-4] */
arch/arm/mach-hisi/platsmp.c
113
writel_relaxed(jump_addr, virt + 4); /* pc jump phy address */
arch/arm/mach-hisi/platsmp.c
148
writel_relaxed(0xe51ff004, virt);
arch/arm/mach-hisi/platsmp.c
149
writel_relaxed(jump_addr, virt + 4);
arch/arm/mach-hisi/platsmp.c
173
writel_relaxed(remap_reg_value, ctrl_base + REG_SC_CTRL);
arch/arm/mach-hisi/platsmp.c
28
writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2));
arch/arm/mach-imx/cpu-imx5.c
154
writel_relaxed(gpc, tigerp_base + ARM_GPC);
arch/arm/mach-imx/gpc.c
112
writel_relaxed(~0, reg_imr1 + i * 4);
arch/arm/mach-imx/gpc.c
122
writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
arch/arm/mach-imx/gpc.c
133
writel_relaxed(val, reg);
arch/arm/mach-imx/gpc.c
144
writel_relaxed(val, reg);
arch/arm/mach-imx/gpc.c
257
writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
arch/arm/mach-imx/gpc.c
36
writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
arch/arm/mach-imx/gpc.c
42
writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
arch/arm/mach-imx/gpc.c
48
writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
arch/arm/mach-imx/gpc.c
59
writel_relaxed(val, gpc_base + GPC_CNTR);
arch/arm/mach-imx/gpc.c
73
writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
arch/arm/mach-imx/gpc.c
86
writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
arch/arm/mach-imx/mach-imx51.c
63
writel_relaxed(0x00000203, m4if_base + 0x40);
arch/arm/mach-imx/mach-imx51.c
64
writel_relaxed(0x00000000, m4if_base + 0x44);
arch/arm/mach-imx/mach-imx51.c
65
writel_relaxed(0x00120125, m4if_base + 0x9c);
arch/arm/mach-imx/mach-imx51.c
66
writel_relaxed(0x001901A3, m4if_base + 0x48);
arch/arm/mach-imx/mmdc.c
576
writel_relaxed(val, reg);
arch/arm/mach-imx/mxc.h
84
#define imx_writel writel_relaxed
arch/arm/mach-imx/platsmp.c
142
writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
arch/arm/mach-imx/pm-imx6.c
241
writel_relaxed(val, ccm_base + CGPR);
arch/arm/mach-imx/pm-imx6.c
258
writel_relaxed(val, ccm_base + CCR);
arch/arm/mach-imx/pm-imx6.c
285
writel_relaxed(val, ccm_base + CLPCR);
arch/arm/mach-imx/pm-imx6.c
291
writel_relaxed(val, ccm_base + CCR);
arch/arm/mach-imx/pm-imx6.c
356
writel_relaxed(val, ccm_base + CLPCR);
arch/arm/mach-imx/pm-imx6.c
660
writel_relaxed(val, ccm_base + CLPCR);
arch/arm/mach-imx/pm-imx7ulp.c
54
writel_relaxed(val, smc1_base + SMC_PMCTRL);
arch/arm/mach-imx/src.c
108
writel_relaxed(val, gpc_base + reg);
arch/arm/mach-imx/src.c
116
writel_relaxed(val, gpc_base + reg);
arch/arm/mach-imx/src.c
135
writel_relaxed(val, src_base + SRC_A7RCR1);
arch/arm/mach-imx/src.c
141
writel_relaxed(val, src_base + SRC_SCR);
arch/arm/mach-imx/src.c
149
writel_relaxed(__pa_symbol(jump_addr),
arch/arm/mach-imx/src.c
162
writel_relaxed(arg, src_base + SRC_GPR1(gpr_v2) + cpu * 8 + 4);
arch/arm/mach-imx/src.c
183
writel_relaxed(val, src_base + SRC_SCR);
arch/arm/mach-imx/src.c
68
writel_relaxed(val, src_base + SRC_SCR);
arch/arm/mach-imx/src.c
87
writel_relaxed(enable, gpc_base + offset);
arch/arm/mach-imx/system.c
111
writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
arch/arm/mach-mediatek/platsmp.c
127
writel_relaxed(__pa_symbol(secondary_startup_arm),
arch/arm/mach-mediatek/platsmp.c
77
writel_relaxed(mtk_smp_info->core_keys[cpu-1],
arch/arm/mach-mstar/mstarv7.c
64
writel_relaxed(0, l3bridge + MSTARV7_L3BRIDGE_FLUSH);
arch/arm/mach-mstar/mstarv7.c
65
writel_relaxed(MSTARV7_L3BRIDGE_FLUSH_TRIGGER, l3bridge
arch/arm/mach-mvebu/kirkwood-pm.c
25
writel_relaxed(~0, memory_pm_ctrl);
arch/arm/mach-mvebu/kirkwood-pm.c
28
writel_relaxed(0x7, ddr_operation_base);
arch/arm/mach-mvebu/kirkwood-pm.c
37
writel_relaxed(mem_pm_ctrl, memory_pm_ctrl);
arch/arm/mach-omap1/irq.c
75
writel_relaxed(value, irq_banks[bank].va + offset);
arch/arm/mach-omap1/irq.c
81
writel_relaxed(0x1, irq_banks[1].va + IRQ_CONTROL_REG_OFFSET);
arch/arm/mach-omap1/irq.c
83
writel_relaxed(0x1, irq_banks[0].va + IRQ_CONTROL_REG_OFFSET);
arch/arm/mach-omap2/cm2xxx_3xxx.h
57
writel_relaxed(val, cm_base.va + module + idx);
arch/arm/mach-omap2/cm33xx.c
54
writel_relaxed(val, cm_base.va + inst + idx);
arch/arm/mach-omap2/cminst44xx.c
127
writel_relaxed(val, _cm_bases[part].va + inst + idx);
arch/arm/mach-omap2/control.c
195
writel_relaxed(val, omap2_ctrl_base + offset);
arch/arm/mach-omap2/control.c
224
writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
arch/arm/mach-omap2/omap-hotplug.c
39
writel_relaxed(0, base + OMAP_AUX_CORE_BOOT_0);
arch/arm/mach-omap2/omap-mpuss-lowpower.c
123
writel_relaxed(addr, pm_info->wkup_sar_addr);
arch/arm/mach-omap2/omap-mpuss-lowpower.c
149
writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
arch/arm/mach-omap2/omap-mpuss-lowpower.c
188
writel_relaxed(save_state, pm_info->l2x0_sar_addr);
arch/arm/mach-omap2/omap-mpuss-lowpower.c
201
writel_relaxed(l2x0_saved_regs.aux_ctrl,
arch/arm/mach-omap2/omap-mpuss-lowpower.c
203
writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
arch/arm/mach-omap2/omap-mpuss-lowpower.c
434
writel_relaxed((omap_type() != OMAP2_DEVICE_TYPE_GP) ? 1 : 0,
arch/arm/mach-omap2/omap-mpuss-lowpower.c
496
writel_relaxed(startup_pa, sar_base +
arch/arm/mach-omap2/omap-mpuss-lowpower.c
499
writel_relaxed(startup_pa, sar_base +
arch/arm/mach-omap2/omap-smp.c
189
writel_relaxed(AUX_CORE_BOOT0_GP_RELEASE,
arch/arm/mach-omap2/omap-smp.c
350
writel_relaxed(1, c->cpu1_rstctrl_va);
arch/arm/mach-omap2/omap-smp.c
352
writel_relaxed(0, c->cpu1_rstctrl_va);
arch/arm/mach-omap2/omap-smp.c
404
writel_relaxed(__pa_symbol(cfg.startup_addr),
arch/arm/mach-omap2/omap-wakeupgen.c
265
writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);
arch/arm/mach-omap2/omap-wakeupgen.c
267
writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);
arch/arm/mach-omap2/omap-wakeupgen.c
271
writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
arch/arm/mach-omap2/omap-wakeupgen.c
273
writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);
arch/arm/mach-omap2/omap-wakeupgen.c
278
writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
arch/arm/mach-omap2/omap-wakeupgen.c
298
writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
arch/arm/mach-omap2/omap-wakeupgen.c
300
writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
arch/arm/mach-omap2/omap-wakeupgen.c
305
writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
arch/arm/mach-omap2/omap-wakeupgen.c
353
writel_relaxed(val, sar_base + offset);
arch/arm/mach-omap2/omap-wakeupgen.c
83
writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
arch/arm/mach-omap2/omap-wakeupgen.c
89
writel_relaxed(val, sar_base + offset + (idx * 4));
arch/arm/mach-omap2/omap4-common.c
118
writel_relaxed(readl_relaxed(dram_sync), dram_sync);
arch/arm/mach-omap2/omap4-common.c
119
writel_relaxed(readl_relaxed(sram_sync), sram_sync);
arch/arm/mach-omap2/omap4-common.c
177
writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
arch/arm/mach-omap2/omap4-common.c
183
writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
arch/arm/mach-omap2/omap4-common.c
203
writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
arch/arm/mach-omap2/omap4-common.c
205
writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
arch/arm/mach-omap2/omap4-common.c
207
writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
arch/arm/mach-omap2/omap4-common.c
83
writel_relaxed(0, dram_sync);
arch/arm/mach-omap2/omap_hwmod.c
2902
writel_relaxed(v, oh->_mpu_rt_va + reg_offs);
arch/arm/mach-omap2/omap_phy_internal.c
47
writel_relaxed(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
arch/arm/mach-omap2/pm33xx-core.c
284
writel_relaxed(0x0, AM33XX_L4_WK_IO_ADDRESS(0x44df2e14));
arch/arm/mach-omap2/prcm_mpu44xx.c
35
writel_relaxed(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
arch/arm/mach-omap2/prm2xxx_3xxx.h
60
writel_relaxed(val, prm_base.va + module + idx);
arch/arm/mach-omap2/prm33xx.c
28
writel_relaxed(val, prm_base.va + inst + idx);
arch/arm/mach-omap2/prm44xx.c
104
writel_relaxed(val, prm_base.va + inst + reg);
arch/arm/mach-omap2/prminst44xx.c
72
writel_relaxed(val, _prm_bases[part].va + inst + idx);
arch/arm/mach-omap2/sdrc.h
31
writel_relaxed(val, OMAP_SDRC_REGADDR(reg));
arch/arm/mach-omap2/sdrc.h
43
writel_relaxed(val, OMAP_SMS_REGADDR(reg));
arch/arm/mach-omap2/sdrc2xxx.c
101
writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP);
arch/arm/mach-omap2/sdrc2xxx.c
103
writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP);
arch/arm/mach-omap2/sram.c
124
writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
arch/arm/mach-omap2/sram.c
125
writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
arch/arm/mach-omap2/sram.c
126
writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
arch/arm/mach-omap2/sram.c
129
writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
arch/arm/mach-omap2/sram.c
130
writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
arch/arm/mach-omap2/sram.c
131
writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
arch/arm/mach-omap2/sram.c
132
writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
arch/arm/mach-omap2/sram.c
133
writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
arch/arm/mach-omap2/timer.c
148
writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
arch/arm/mach-omap2/timer.c
153
writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
arch/arm/mach-omap2/vc.c
584
writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME);
arch/arm/mach-omap2/vc.c
716
writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
arch/arm/mach-omap2/wd_timer.c
48
writel_relaxed(0xAAAA, base + OMAP_WDT_SPR);
arch/arm/mach-omap2/wd_timer.c
52
writel_relaxed(0x5555, base + OMAP_WDT_SPR);
arch/arm/mach-pxa/reset.c
75
writel_relaxed(OWER_WME, OWER);
arch/arm/mach-pxa/reset.c
76
writel_relaxed(OSSR_M3, OSSR);
arch/arm/mach-pxa/reset.c
78
writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3);
arch/arm/mach-pxa/reset.c
84
writel_relaxed(MDREFR_SLFRSH, MDREFR);
arch/arm/mach-qcom/platsmp.c
171
writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL);
arch/arm/mach-qcom/platsmp.c
177
writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
arch/arm/mach-qcom/platsmp.c
179
writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
arch/arm/mach-qcom/platsmp.c
184
writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
arch/arm/mach-qcom/platsmp.c
189
writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
arch/arm/mach-qcom/platsmp.c
194
writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
arch/arm/mach-qcom/platsmp.c
199
writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
arch/arm/mach-qcom/platsmp.c
258
writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
arch/arm/mach-qcom/platsmp.c
265
writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
arch/arm/mach-qcom/platsmp.c
272
writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
arch/arm/mach-qcom/platsmp.c
275
writel_relaxed(0x10003, l2_saw_base + APCS_SAW2_2_VCTL);
arch/arm/mach-qcom/platsmp.c
280
writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
arch/arm/mach-qcom/platsmp.c
285
writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
arch/arm/mach-qcom/platsmp.c
290
writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
arch/arm/mach-qcom/platsmp.c
294
writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
arch/arm/mach-qcom/platsmp.c
70
writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
arch/arm/mach-qcom/platsmp.c
71
writel_relaxed(0, base + SCSS_CPU1CORE_RESET);
arch/arm/mach-qcom/platsmp.c
72
writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP);
arch/arm/mach-s3c/cpu.c
26
writel_relaxed(0x0, S3C_VA_SYS + 0xA1C);
arch/arm/mach-s3c/pm-common.c
52
writel_relaxed(ptr->val, ptr->reg);
arch/arm/mach-s3c/pm-common.c
72
writel_relaxed(ptr->val, ptr->reg);
arch/arm/mach-s5pv210/pm.c
63
writel_relaxed(ptr->val, ptr->reg);
arch/arm/mach-sa1100/assabet.c
91
writel_relaxed(def_val, reg);
arch/arm/mach-shmobile/platsmp-apmu.c
50
writel_relaxed(BIT(bit), p + WUPCR_OFFS);
arch/arm/mach-shmobile/platsmp-apmu.c
62
writel_relaxed(3, p + CPUNCR_OFFS(bit));
arch/arm/mach-shmobile/pm-rcar-gen2.c
110
writel_relaxed(bar, p + CA15BAR);
arch/arm/mach-shmobile/pm-rcar-gen2.c
111
writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
arch/arm/mach-shmobile/pm-rcar-gen2.c
114
writel_relaxed((readl_relaxed(p + CA15RESCNT) &
arch/arm/mach-shmobile/pm-rcar-gen2.c
119
writel_relaxed(bar, p + CA7BAR);
arch/arm/mach-shmobile/pm-rcar-gen2.c
120
writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
arch/arm/mach-shmobile/pm-rcar-gen2.c
123
writel_relaxed((readl_relaxed(p + CA7RESCNT) &
arch/arm/mach-spear/restart.c
26
writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES);
arch/arm/mach-spear/spear13xx.c
39
writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL);
arch/arm/mach-spear/spear13xx.c
45
writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL);
arch/arm/mach-spear/spear13xx.c
46
writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL);
arch/arm/mach-tegra/irq.c
51
writel_relaxed(0x1E0, tegra_gic_cpu_base + GIC_CPU_CTRL);
arch/arm/mach-ux500/cpu-db8500.c
49
writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
arch/arm/mach-ux500/cpu-db8500.c
51
writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
arch/arm/mach-versatile/spc.c
136
writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
arch/arm/mach-versatile/spc.c
169
writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
arch/arm/mach-versatile/spc.c
191
writel_relaxed(addr, baseaddr);
arch/arm/mach-versatile/spc.c
212
writel_relaxed(enable, info->baseaddr + pwdrn_reg);
arch/arm/mm/cache-l2x0-pmu.c
66
writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT0_CFG - 4 * idx);
arch/arm/mm/cache-l2x0-pmu.c
76
writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT0_VAL - 4 * idx);
arch/arm/mm/cache-l2x0-pmu.c
83
writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT_CTRL);
arch/arm/mm/cache-l2x0-pmu.c
90
writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT_CTRL);
arch/arm/mm/cache-l2x0.c
126
writel_relaxed(0, base + sync_reg_offset);
arch/arm/mm/cache-l2x0.c
1396
writel_relaxed(start, base + AURORA_RANGE_BASE_ADDR_REG);
arch/arm/mm/cache-l2x0.c
1397
writel_relaxed(range_end - CACHE_LINE_SIZE, base + offset);
arch/arm/mm/cache-l2x0.c
1400
writel_relaxed(0, base + AURORA_SYNC_REG);
arch/arm/mm/cache-l2x0.c
1437
writel_relaxed(0, base + AURORA_SYNC_REG);
arch/arm/mm/cache-l2x0.c
1442
writel_relaxed(0, l2x0_base + AURORA_SYNC_REG);
arch/arm/mm/cache-l2x0.c
1452
writel_relaxed(0, base + AURORA_SYNC_REG);
arch/arm/mm/cache-l2x0.c
1728
writel_relaxed(l2x0_saved_regs.aux2_ctrl,
arch/arm/mm/cache-l2x0.c
1730
writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
arch/arm/mm/cache-l2x0.c
176
writel_relaxed(0, base + sync_reg_offset);
arch/arm/mm/cache-l2x0.c
183
writel_relaxed(start, reg);
arch/arm/mm/cache-l2x0.c
194
writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA);
arch/arm/mm/cache-l2x0.c
200
writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA);
arch/arm/mm/cache-l2x0.c
271
writel_relaxed(0, base + L2X0_CACHE_SYNC);
arch/arm/mm/cache-l2x0.c
295
writel_relaxed(start, reg);
arch/arm/mm/cache-l2x0.c
317
writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA);
arch/arm/mm/cache-l2x0.c
324
writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA);
arch/arm/mm/cache-l2x0.c
481
writel_relaxed(start, base + L2X0_CLEAN_LINE_PA);
arch/arm/mm/cache-l2x0.c
482
writel_relaxed(start, base + L2X0_INV_LINE_PA);
arch/arm/mm/cache-l2x0.c
488
writel_relaxed(end, base + L2X0_CLEAN_LINE_PA);
arch/arm/mm/cache-l2x0.c
489
writel_relaxed(end, base + L2X0_INV_LINE_PA);
arch/arm/mm/cache-l2x0.c
512
writel_relaxed(start, base + L2X0_CLEAN_LINE_PA);
arch/arm/mm/cache-l2x0.c
513
writel_relaxed(start, base + L2X0_INV_LINE_PA);
arch/arm/mm/cache-l2x0.c
73
writel_relaxed(val, base + reg);
arch/arm/mm/cache-l2x0.c
88
writel_relaxed(l2x0_way_mask, reg);
arch/arm/mm/cache-l2x0.c
97
writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE +
arch/arm/mm/cache-l2x0.c
99
writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE +
arch/arm/mm/cache-uniphier.c
100
writel_relaxed(UNIPHIER_SSCOPE_CM_SYNC,
arch/arm/mm/cache-uniphier.c
147
writel_relaxed(UNIPHIER_SSCOLPQS_EF, data->op_base + UNIPHIER_SSCOLPQS);
arch/arm/mm/cache-uniphier.c
151
writel_relaxed(UNIPHIER_SSCOQM_CE | operation,
arch/arm/mm/cache-uniphier.c
156
writel_relaxed(start, data->op_base + UNIPHIER_SSCOQAD);
arch/arm/mm/cache-uniphier.c
157
writel_relaxed(size, data->op_base + UNIPHIER_SSCOQSZ);
arch/arm/mm/cache-uniphier.c
226
writel_relaxed(val, data->ctrl_base + UNIPHIER_SSCC);
arch/arm/mm/cache-uniphier.c
235
writel_relaxed(data->way_mask, data->way_ctrl_base + 4 * cpu);
arch/arm/mm/pmsa-v7.c
105
writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv7_RNR);
arch/arm/mm/pmsa-v7.c
115
writel_relaxed((v << 16) | rsr, BASEADDR_V7M_SCB + PMSAv7_RASR);
arch/arm/mm/pmsa-v7.c
123
writel_relaxed(v | racr, BASEADDR_V7M_SCB + PMSAv7_RASR);
arch/arm/mm/pmsa-v7.c
129
writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv7_RBAR);
arch/arm/mm/pmsa-v8.c
63
writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RNR);
arch/arm/mm/pmsa-v8.c
68
writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RBAR);
arch/arm/mm/pmsa-v8.c
73
writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RLAR);
arch/arm64/kernel/acpi_parking_protocol.c
104
writel_relaxed(cpu_entry->gic_cpu_id, &mailbox->cpu_id);
arch/arm64/kvm/hyp/vgic-v2-cpuif-proxy.c
80
writel_relaxed(data, addr);
arch/arm64/kvm/vgic/vgic-v2.c
142
writel_relaxed(FIELD_GET(GICH_LR_PHYSID_CPUID, lr),
arch/arm64/kvm/vgic/vgic-v2.c
19
writel_relaxed(val, base + GICH_LR0 + (lr * 4));
arch/arm64/kvm/vgic/vgic-v2.c
205
writel_relaxed(FIELD_GET(GICH_LR_PHYSID_CPUID, lr),
arch/arm64/kvm/vgic/vgic-v2.c
563
writel_relaxed(0, base + GICH_LR0 + (i * 4));
arch/arm64/kvm/vgic/vgic-v2.c
588
writel_relaxed(0, base + GICH_HCR);
arch/arm64/kvm/vgic/vgic-v2.c
601
writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR);
arch/arm64/kvm/vgic/vgic-v2.c
604
writel_relaxed(cpu_if->vgic_lr[i], base + GICH_LR0 + (i * 4));
arch/arm64/kvm/vgic/vgic-v2.c
611
writel_relaxed(cpu_if->vgic_vmcr,
arch/arm64/kvm/vgic/vgic-v2.c
613
writel_relaxed(cpu_if->vgic_apr,
arch/csky/include/asm/io.h
27
#define writel(v,c) ({ wmb(); writel_relaxed((v),(c)); })
arch/csky/include/asm/io.h
31
#define writel(v,c) ({ wmb(); writel_relaxed((v),(c)); mb(); })
arch/mips/loongson64/smp.c
124
writel_relaxed(action, ipi_clear0_regs[cpu_logical_map(cpu)]);
arch/mips/loongson64/smp.c
132
writel_relaxed((u32)action, ipi_set0_regs[cpu]);
arch/mips/loongson64/smp.c
138
writel_relaxed(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]);
arch/sh/include/asm/io.h
55
#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
drivers/accel/ethosu/ethosu_drv.c
218
writel_relaxed(RESET_PENDING_CSL, ethosudev->regs + NPU_REG_RESET);
drivers/accel/ethosu/ethosu_drv.c
234
writel_relaxed(0x0000aa8a, ethosudev->regs + NPU_REG_REGIONCFG);
drivers/accel/ethosu/ethosu_drv.c
236
writel_relaxed(U65_SRAM_AXI_LIMIT_CFG, ethosudev->regs + NPU_REG_AXILIMIT0);
drivers/accel/ethosu/ethosu_drv.c
237
writel_relaxed(U65_DRAM_AXI_LIMIT_CFG, ethosudev->regs + NPU_REG_AXILIMIT2);
drivers/accel/ethosu/ethosu_drv.c
239
writel_relaxed(U85_AXI_SRAM_CFG, ethosudev->regs + NPU_REG_AXI_SRAM);
drivers/accel/ethosu/ethosu_drv.c
240
writel_relaxed(U85_AXI_EXT_CFG, ethosudev->regs + NPU_REG_AXI_EXT);
drivers/accel/ethosu/ethosu_drv.c
241
writel_relaxed(U85_MEM_ATTR0_CFG, ethosudev->regs + NPU_REG_MEM_ATTR0); // SRAM
drivers/accel/ethosu/ethosu_drv.c
242
writel_relaxed(U85_MEM_ATTR2_CFG, ethosudev->regs + NPU_REG_MEM_ATTR2); // DRAM
drivers/accel/ethosu/ethosu_job.c
240
writel_relaxed(CMD_CLEAR_IRQ, dev->regs + NPU_REG_CMD);
drivers/accel/ethosu/ethosu_job.c
55
writel_relaxed(lower_32_bits(bo->dma_addr), dev->regs + NPU_REG_BASEP(region));
drivers/accel/ethosu/ethosu_job.c
56
writel_relaxed(upper_32_bits(bo->dma_addr), dev->regs + NPU_REG_BASEP_HI(region));
drivers/accel/ethosu/ethosu_job.c
61
writel_relaxed(lower_32_bits(dev->sramphys),
drivers/accel/ethosu/ethosu_job.c
63
writel_relaxed(upper_32_bits(dev->sramphys),
drivers/accel/ethosu/ethosu_job.c
69
writel_relaxed(lower_32_bits(cmd_bo->dma_addr), dev->regs + NPU_REG_QBASE);
drivers/accel/ethosu/ethosu_job.c
70
writel_relaxed(upper_32_bits(cmd_bo->dma_addr), dev->regs + NPU_REG_QBASE_HI);
drivers/accel/ethosu/ethosu_job.c
71
writel_relaxed(cmd_info->cmd_size, dev->regs + NPU_REG_QSIZE);
drivers/accel/qaic/mhi_controller.c
776
writel_relaxed(val, addr);
drivers/acpi/cppc_acpi.c
1158
writel_relaxed(val, vaddr);
drivers/ata/ahci_brcm.c
115
writel_relaxed(val, addr);
drivers/ata/sata_dwc_460ex.c
41
#define sata_dwc_writel(a, v) writel_relaxed(v, a)
drivers/base/regmap/regmap-mmio.c
129
writel_relaxed(val, ctx->regs + reg);
drivers/bus/arm-cci.c
237
writel_relaxed(enable ? CCI_ENABLE_REQ : 0, base + CCI_PORT_CTRL);
drivers/bus/hisi_lpc.c
123
writel_relaxed(opcnt, lpcdev->membase + LPC_REG_OP_LEN);
drivers/bus/hisi_lpc.c
124
writel_relaxed(cmd_word, lpcdev->membase + LPC_REG_CMD);
drivers/bus/hisi_lpc.c
125
writel_relaxed(addr, lpcdev->membase + LPC_REG_ADDR);
drivers/bus/hisi_lpc.c
176
writel_relaxed(opcnt, lpcdev->membase + LPC_REG_OP_LEN);
drivers/bus/hisi_lpc.c
177
writel_relaxed(cmd_word, lpcdev->membase + LPC_REG_CMD);
drivers/bus/hisi_lpc.c
178
writel_relaxed(addr, lpcdev->membase + LPC_REG_ADDR);
drivers/bus/omap-ocp2scp.c
63
writel_relaxed(reg, regs + OCP2SCP_TIMING);
drivers/bus/omap_l3_noc.c
143
writel_relaxed(clear, l3_targ_stderr);
drivers/bus/omap_l3_noc.c
207
writel_relaxed(mask_val, mask_reg);
drivers/bus/omap_l3_noc.c
325
writel_relaxed(mask_val, mask_regx);
drivers/bus/omap_l3_noc.c
331
writel_relaxed(mask_val, mask_regx);
drivers/bus/ti-sysc.c
191
writel_relaxed(value, ddata->module_va + offset);
drivers/cache/sifive_ccache.c
158
writel_relaxed(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32);
drivers/char/agp/intel-gtt.c
1160
writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
drivers/char/agp/intel-gtt.c
337
writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
drivers/char/agp/intel-gtt.c
755
writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
drivers/char/hw_random/exynos-trng.c
151
writel_relaxed(val, trng->mem + EXYNOS_TRNG_CLKDIV);
drivers/char/hw_random/exynos-trng.c
155
writel_relaxed(val, trng->mem + EXYNOS_TRNG_CTRL);
drivers/char/hw_random/exynos-trng.c
161
writel_relaxed(0, trng->mem + EXYNOS_TRNG_POST_CTRL);
drivers/char/hw_random/exynos-trng.c
89
writel_relaxed(max * 8, trng->mem + EXYNOS_TRNG_FIFO_CTRL);
drivers/char/hw_random/hisi-rng.c
43
writel_relaxed(seed, hrng->base + RNG_SEED);
drivers/char/hw_random/hisi-rng.c
53
writel_relaxed(val, hrng->base + RNG_CTRL);
drivers/char/hw_random/hisi-rng.c
61
writel_relaxed(0, hrng->base + RNG_CTRL);
drivers/char/hw_random/histb-rng.c
57
writel_relaxed(val, base + RNG_CTRL);
drivers/char/hw_random/meson-rng.c
67
writel_relaxed(readl_relaxed(cfg_addr) | SEED_READY_STS_BIT, cfg_addr);
drivers/char/hw_random/stm32-rng.c
112
writel_relaxed(cr | RNG_CR_CONDRST, priv->base + RNG_CR);
drivers/char/hw_random/stm32-rng.c
113
writel_relaxed(cr & ~RNG_CR_CONDRST, priv->base + RNG_CR);
drivers/char/hw_random/stm32-rng.c
116
writel_relaxed(sr & ~RNG_SR_SEIS, priv->base + RNG_SR);
drivers/char/hw_random/stm32-rng.c
162
writel_relaxed(sr & ~RNG_SR_SEIS, priv->base + RNG_SR);
drivers/char/hw_random/stm32-rng.c
234
writel_relaxed(0, priv->base + RNG_SR);
drivers/char/hw_random/stm32-rng.c
297
writel_relaxed(0, priv->base + RNG_SR);
drivers/char/hw_random/stm32-rng.c
315
writel_relaxed(reg, priv->base + RNG_CR);
drivers/char/hw_random/stm32-rng.c
318
writel_relaxed(priv->data->htcr, priv->base + RNG_HTCR);
drivers/char/hw_random/stm32-rng.c
319
writel_relaxed(priv->data->nscr & RNG_NSCR_MASK, priv->base + RNG_NSCR);
drivers/char/hw_random/stm32-rng.c
326
writel_relaxed(reg, priv->base + RNG_CR);
drivers/char/hw_random/stm32-rng.c
346
writel_relaxed(reg, priv->base + RNG_CR);
drivers/char/hw_random/stm32-rng.c
353
writel_relaxed(reg, priv->base + RNG_CR);
drivers/char/hw_random/stm32-rng.c
383
writel_relaxed(reg, priv->base + RNG_CR);
drivers/char/hw_random/stm32-rng.c
407
writel_relaxed(priv->pm_conf.cr, priv->base + RNG_CR);
drivers/char/hw_random/stm32-rng.c
425
writel_relaxed(0, priv->base + RNG_SR);
drivers/char/hw_random/stm32-rng.c
429
writel_relaxed(reg, priv->base + RNG_CR);
drivers/char/hw_random/stm32-rng.c
445
writel_relaxed(0, priv->base + RNG_SR);
drivers/char/hw_random/stm32-rng.c
454
writel_relaxed(priv->pm_conf.cr | RNG_CR_CONDRST, priv->base + RNG_CR);
drivers/char/hw_random/stm32-rng.c
456
writel_relaxed(priv->pm_conf.nscr, priv->base + RNG_NSCR);
drivers/char/hw_random/stm32-rng.c
457
writel_relaxed(priv->pm_conf.htcr, priv->base + RNG_HTCR);
drivers/char/hw_random/stm32-rng.c
462
writel_relaxed(reg, priv->base + RNG_CR);
drivers/char/hw_random/stm32-rng.c
475
writel_relaxed(reg, priv->base + RNG_CR);
drivers/clk/axs10x/i2s_pll_clock.c
67
writel_relaxed(val, clk->base + reg);
drivers/clk/berlin/berlin2-avpll.c
135
writel_relaxed(reg, vco->base + VCO_CTRL0);
drivers/clk/berlin/berlin2-avpll.c
150
writel_relaxed(reg, vco->base + VCO_CTRL0);
drivers/clk/berlin/berlin2-avpll.c
233
writel_relaxed(reg, ch->base + VCO_CTRL10);
drivers/clk/berlin/berlin2-avpll.c
245
writel_relaxed(reg, ch->base + VCO_CTRL10);
drivers/clk/berlin/berlin2-div.c
113
writel_relaxed(reg, div->base + map->gate_offs);
drivers/clk/berlin/berlin2-div.c
134
writel_relaxed(reg, div->base + map->pll_switch_offs);
drivers/clk/berlin/berlin2-div.c
141
writel_relaxed(reg, div->base + map->pll_select_offs);
drivers/clk/berlin/berlin2-div.c
94
writel_relaxed(reg, div->base + map->gate_offs);
drivers/clk/clk-apple-nco.c
175
writel_relaxed(div, chan->base + REG_DIV);
drivers/clk/clk-apple-nco.c
176
writel_relaxed(inc1, chan->base + REG_INC1);
drivers/clk/clk-apple-nco.c
177
writel_relaxed(inc2, chan->base + REG_INC2);
drivers/clk/clk-apple-nco.c
180
writel_relaxed(1 << 31, chan->base + REG_ACCINIT);
drivers/clk/clk-apple-nco.c
83
writel_relaxed(val | CTRL_ENABLE, chan->base + REG_CTRL);
drivers/clk/clk-apple-nco.c
92
writel_relaxed(val & ~CTRL_ENABLE, chan->base + REG_CTRL);
drivers/clk/clk-xgene.c
39
writel_relaxed(data, csr);
drivers/clk/hisilicon/clk-hi3559a.c
393
writel_relaxed(val, clk->ctrl_reg1);
drivers/clk/hisilicon/clk-hi3559a.c
401
writel_relaxed(val, clk->ctrl_reg2);
drivers/clk/hisilicon/clk-hi3559a.c
683
writel_relaxed(val, crg_base + 0x20);
drivers/clk/hisilicon/clk-hi3559a.c
688
writel_relaxed(val, crg_base + 0x1C);
drivers/clk/hisilicon/clk-hi3620.c
361
writel_relaxed(val, mclk->clken_reg);
drivers/clk/hisilicon/clk-hi3620.c
365
writel_relaxed(val, mclk->sam_reg);
drivers/clk/hisilicon/clk-hi3620.c
369
writel_relaxed(val, mclk->drv_reg);
drivers/clk/hisilicon/clk-hi3620.c
373
writel_relaxed(val, mclk->div_reg);
drivers/clk/hisilicon/clk-hi3620.c
377
writel_relaxed(val, mclk->clken_reg);
drivers/clk/hisilicon/clk-hix5hd2.c
176
writel_relaxed(val, clk->ctrl_reg);
drivers/clk/hisilicon/clk-hix5hd2.c
178
writel_relaxed(val, clk->ctrl_reg);
drivers/clk/hisilicon/clk-hix5hd2.c
183
writel_relaxed(val, clk->phy_reg);
drivers/clk/hisilicon/clk-hix5hd2.c
188
writel_relaxed(val, clk->phy_reg);
drivers/clk/hisilicon/clk-hix5hd2.c
193
writel_relaxed(val, clk->phy_reg);
drivers/clk/hisilicon/clk-hix5hd2.c
205
writel_relaxed(val, clk->ctrl_reg);
drivers/clk/hisilicon/clk-hix5hd2.c
221
writel_relaxed(val, clk->ctrl_reg);
drivers/clk/hisilicon/clk-hix5hd2.c
226
writel_relaxed(val, clk->phy_reg);
drivers/clk/hisilicon/clk-hix5hd2.c
239
writel_relaxed(val, clk->ctrl_reg);
drivers/clk/hisilicon/clk-hix5hd2.c
244
writel_relaxed(val, clk->phy_reg);
drivers/clk/hisilicon/clkdivider-hi6220.c
86
writel_relaxed(data, dclk->reg);
drivers/clk/hisilicon/clkgate-separated.c
42
writel_relaxed(reg, sclk->enable);
drivers/clk/hisilicon/clkgate-separated.c
59
writel_relaxed(reg, sclk->enable + CLKGATE_SEPARATED_DISABLE);
drivers/clk/imx/clk-composite-7ulp.c
153
writel_relaxed(val, reg);
drivers/clk/imx/clk-frac-pll.c
177
writel_relaxed(val, pll->base + PLL_CFG1);
drivers/clk/imx/clk-frac-pll.c
181
writel_relaxed(val, pll->base + PLL_CFG0);
drivers/clk/imx/clk-frac-pll.c
186
writel_relaxed(val, pll->base + PLL_CFG0);
drivers/clk/imx/clk-frac-pll.c
193
writel_relaxed(val, pll->base + PLL_CFG0);
drivers/clk/imx/clk-frac-pll.c
72
writel_relaxed(val, pll->base + PLL_CFG0);
drivers/clk/imx/clk-frac-pll.c
84
writel_relaxed(val, pll->base + PLL_CFG0);
drivers/clk/imx/clk-fracn-gppll.c
246
writel_relaxed(tmp, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
251
writel_relaxed(tmp, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
255
writel_relaxed(tmp, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
259
writel_relaxed(tmp, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
263
writel_relaxed(pll_div, pll->base + PLL_DIV);
drivers/clk/imx/clk-fracn-gppll.c
266
writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR);
drivers/clk/imx/clk-fracn-gppll.c
267
writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR);
drivers/clk/imx/clk-fracn-gppll.c
276
writel_relaxed(tmp, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
286
writel_relaxed(tmp, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
307
writel_relaxed(readl_relaxed(pll->base + PLL_NUMERATOR),
drivers/clk/imx/clk-fracn-gppll.c
311
writel_relaxed(val, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
314
writel_relaxed(val, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
322
writel_relaxed(val, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
325
writel_relaxed(val, pll->base + PLL_CTRL);
drivers/clk/imx/clk-fracn-gppll.c
347
writel_relaxed(val, pll->base + PLL_CTRL);
drivers/clk/imx/clk-imx6q.c
281
writel_relaxed(reg, ccm_base + CCM_CCSR);
drivers/clk/imx/clk-imx6q.c
291
writel_relaxed(reg, ccm_base + CCM_CCSR);
drivers/clk/imx/clk-imx6q.c
379
writel_relaxed(reg, ccm_base + CCM_CS2CDR);
drivers/clk/imx/clk-imx6q.c
408
writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_528);
drivers/clk/imx/clk-imx6q.c
413
writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_480);
drivers/clk/imx/clk-imx6q.c
418
writel_relaxed(reg, anatop_base + CCM_ANALOG_PLL_VIDEO);
drivers/clk/imx/clk-imx6sl.c
149
writel_relaxed(val, anatop_base + PLL_ARM);
drivers/clk/imx/clk-imx6sl.c
153
writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM);
drivers/clk/imx/clk-imx6sl.c
171
writel_relaxed(arm_div_for_wait, ccm_base + CACRR);
drivers/clk/imx/clk-imx6sl.c
173
writel_relaxed(saved_arm_div, ccm_base + CACRR);
drivers/clk/imx/clk-imx6sll.c
106
writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x0));
drivers/clk/imx/clk-imx6sll.c
107
writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x10));
drivers/clk/imx/clk-imx6sll.c
108
writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x20));
drivers/clk/imx/clk-imx6sll.c
109
writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x30));
drivers/clk/imx/clk-imx6sll.c
110
writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x70));
drivers/clk/imx/clk-imx6sll.c
111
writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xa0));
drivers/clk/imx/clk-imx6sll.c
112
writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xe0));
drivers/clk/imx/clk-imx8-acm.c
472
writel_relaxed(priv->regs[i], priv->reg + sels[i].reg);
drivers/clk/imx/clk-pfd.c
102
writel_relaxed(0x3f << (pfd->idx * 8), pfd->reg + CLR);
drivers/clk/imx/clk-pfd.c
103
writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET);
drivers/clk/imx/clk-pfd.c
40
writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR);
drivers/clk/imx/clk-pfd.c
49
writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET);
drivers/clk/imx/clk-pfdv2.c
188
writel_relaxed(val, pfd->reg);
drivers/clk/imx/clk-pfdv2.c
60
writel_relaxed(val, pfd->reg);
drivers/clk/imx/clk-pfdv2.c
75
writel_relaxed(val, pfd->reg);
drivers/clk/imx/clk-pll14xx.c
313
writel_relaxed(tmp, pll->base + DIV_CTL0);
drivers/clk/imx/clk-pll14xx.c
321
writel_relaxed(tmp, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
325
writel_relaxed(tmp, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
333
writel_relaxed(div_val, pll->base + DIV_CTL0);
drivers/clk/imx/clk-pll14xx.c
345
writel_relaxed(tmp, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
354
writel_relaxed(tmp, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
375
writel_relaxed(div_ctl0, pll->base + DIV_CTL0);
drivers/clk/imx/clk-pll14xx.c
377
writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv),
drivers/clk/imx/clk-pll14xx.c
386
writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
390
writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
395
writel_relaxed(div_ctl0, pll->base + DIV_CTL0);
drivers/clk/imx/clk-pll14xx.c
397
writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1);
drivers/clk/imx/clk-pll14xx.c
409
writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
418
writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
437
writel_relaxed(val, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
439
writel_relaxed(val, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
446
writel_relaxed(val, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
472
writel_relaxed(val, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pll14xx.c
540
writel_relaxed(val, pll->base + GNRL_CTL);
drivers/clk/imx/clk-pllv3.c
146
writel_relaxed(val, pll->base);
drivers/clk/imx/clk-pllv3.c
203
writel_relaxed(val, pll->base);
drivers/clk/imx/clk-pllv3.c
292
writel_relaxed(val, pll->base);
drivers/clk/imx/clk-pllv3.c
293
writel_relaxed(mfn, pll->base + pll->num_offset);
drivers/clk/imx/clk-pllv3.c
294
writel_relaxed(mfd, pll->base + pll->denom_offset);
drivers/clk/imx/clk-pllv3.c
387
writel_relaxed(val, pll->base);
drivers/clk/imx/clk-pllv3.c
389
writel_relaxed(mf.mfn, pll->base + pll->num_offset);
drivers/clk/imx/clk-pllv3.c
390
writel_relaxed(mf.mfd, pll->base + pll->denom_offset);
drivers/clk/imx/clk-pllv3.c
83
writel_relaxed(val, pll->base);
drivers/clk/imx/clk-pllv3.c
98
writel_relaxed(val, pll->base);
drivers/clk/imx/clk-pllv4.c
207
writel_relaxed(val, pll->base + pll->cfg_offset);
drivers/clk/imx/clk-pllv4.c
209
writel_relaxed(mfn, pll->base + pll->num_offset);
drivers/clk/imx/clk-pllv4.c
210
writel_relaxed(mfd, pll->base + pll->denom_offset);
drivers/clk/imx/clk-pllv4.c
222
writel_relaxed(val, pll->base);
drivers/clk/imx/clk-pllv4.c
234
writel_relaxed(val, pll->base);
drivers/clk/imx/clk-sscg-pll.c
312
writel_relaxed(val, pll->base + PLL_CFG0);
drivers/clk/imx/clk-sscg-pll.c
324
writel_relaxed(val, pll->base + PLL_CFG0);
drivers/clk/imx/clk-sscg-pll.c
379
writel_relaxed(val, pll->base + PLL_CFG2);
drivers/clk/imx/clk-vf610.c
163
writel_relaxed(cscmr1, CCM_CSCMR1);
drivers/clk/imx/clk-vf610.c
164
writel_relaxed(cscmr2, CCM_CSCMR2);
drivers/clk/imx/clk-vf610.c
166
writel_relaxed(cscdr1, CCM_CSCDR1);
drivers/clk/imx/clk-vf610.c
167
writel_relaxed(cscdr2, CCM_CSCDR2);
drivers/clk/imx/clk-vf610.c
168
writel_relaxed(cscdr3, CCM_CSCDR3);
drivers/clk/imx/clk-vf610.c
171
writel_relaxed(ccgr[i], CCM_CCGRx(i));
drivers/clk/imx/clk.c
39
writel_relaxed(reg, ccm_base + CCM_CCDR);
drivers/clk/mmp/clk-apbc.c
108
writel_relaxed(data, apbc->base);
drivers/clk/mmp/clk-apbc.c
49
writel_relaxed(data, apbc->base);
drivers/clk/mmp/clk-apbc.c
61
writel_relaxed(data, apbc->base);
drivers/clk/mmp/clk-apbc.c
74
writel_relaxed(data, apbc->base);
drivers/clk/mmp/clk-apbc.c
96
writel_relaxed(data, apbc->base);
drivers/clk/mmp/clk-apmu.c
36
writel_relaxed(data, apmu->base);
drivers/clk/mmp/clk-apmu.c
54
writel_relaxed(data, apmu->base);
drivers/clk/mmp/clk-frac.c
110
writel_relaxed(val, factor->base);
drivers/clk/mvebu/dove-divider.c
42
writel_relaxed(v, base + DIV_CTRL1);
drivers/clk/mvebu/dove-divider.c
45
writel_relaxed(v, base + DIV_CTRL0);
drivers/clk/mvebu/dove-divider.c
46
writel_relaxed(v | load, base + DIV_CTRL0);
drivers/clk/mvebu/dove-divider.c
48
writel_relaxed(v, base + DIV_CTRL0);
drivers/clk/mxs/clk-frac.c
99
writel_relaxed(val, frac->reg);
drivers/clk/mxs/clk-imx23.c
49
writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
drivers/clk/mxs/clk-imx23.c
52
writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR);
drivers/clk/mxs/clk-imx23.c
57
writel_relaxed(val, SAIF);
drivers/clk/mxs/clk-imx23.c
63
writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR);
drivers/clk/mxs/clk-imx23.c
69
writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR);
drivers/clk/mxs/clk-imx23.c
70
writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET);
drivers/clk/mxs/clk-imx28.c
104
writel_relaxed(val, ENET);
drivers/clk/mxs/clk-imx28.c
110
writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR);
drivers/clk/mxs/clk-imx28.c
119
writel_relaxed(val, FRAC0);
drivers/clk/mxs/clk-imx28.c
73
writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR);
drivers/clk/mxs/clk-imx28.c
74
writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET);
drivers/clk/mxs/clk-imx28.c
84
writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
drivers/clk/mxs/clk-imx28.c
87
writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET);
drivers/clk/mxs/clk-imx28.c
90
writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR);
drivers/clk/mxs/clk-imx28.c
95
writel_relaxed(val, SAIF0);
drivers/clk/mxs/clk-imx28.c
99
writel_relaxed(val, SAIF1);
drivers/clk/mxs/clk-pll.c
36
writel_relaxed(1 << pll->power, pll->base + SET);
drivers/clk/mxs/clk-pll.c
47
writel_relaxed(1 << pll->power, pll->base + CLR);
drivers/clk/mxs/clk-pll.c
54
writel_relaxed(1 << 31, pll->base + CLR);
drivers/clk/mxs/clk-pll.c
63
writel_relaxed(1 << 31, pll->base + SET);
drivers/clk/mxs/clk-ref.c
35
writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + CLR);
drivers/clk/mxs/clk-ref.c
44
writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET);
drivers/clk/mxs/clk-ref.c
98
writel_relaxed(val, ref->reg);
drivers/clk/nuvoton/clk-ma35d1-divider.c
67
writel_relaxed(data, dclk->reg);
drivers/clk/nuvoton/clk-ma35d1-pll.c
215
writel_relaxed(reg_ctl[0], pll->ctl0_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
216
writel_relaxed(reg_ctl[1], pll->ctl1_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
217
writel_relaxed(reg_ctl[2], pll->ctl2_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
302
writel_relaxed(val, pll->ctl1_base);
drivers/clk/nuvoton/clk-ma35d1-pll.c
313
writel_relaxed(val, pll->ctl1_base);
drivers/clk/renesas/clk-emev2.c
31
writel_relaxed(value, smu_base + offs);
drivers/clk/renesas/clk-vbattb.c
172
writel_relaxed(val, vbclk->base + VBATTB_XOSCCR);
drivers/clk/rockchip/clk-pll.c
221
writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
drivers/clk/rockchip/clk-pll.c
227
writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,
drivers/clk/rockchip/clk-pll.c
239
writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
drivers/clk/rockchip/clk-pll.c
464
writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
drivers/clk/rockchip/clk-pll.c
467
writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK,
drivers/clk/rockchip/clk-pll.c
703
writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
drivers/clk/rockchip/clk-pll.c
707
writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK,
drivers/clk/rockchip/clk-pll.c
719
writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2));
drivers/clk/rockchip/clk-pll.c
721
writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK,
drivers/clk/rockchip/clk-pll.c
960
writel_relaxed(HIWORD_UPDATE(rate->m, RK3588_PLLCON0_M_MASK, RK3588_PLLCON0_M_SHIFT),
drivers/clk/rockchip/clk-pll.c
963
writel_relaxed(HIWORD_UPDATE(rate->p, RK3588_PLLCON1_P_MASK, RK3588_PLLCON1_P_SHIFT) |
drivers/clk/rockchip/clk-pll.c
967
writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, RK3588_PLLCON2_K_SHIFT),
drivers/clk/rockchip/clk-rk3036.c
457
writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10),
drivers/clk/rockchip/clk-rk3288.c
890
writel_relaxed(1 << (12 + 16),
drivers/clk/rockchip/clk-rk3288.c
904
writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
drivers/clk/rockchip/clk-rk3288.c
916
writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000,
drivers/clk/rockchip/clk-rk3288.c
923
writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
drivers/clk/rockchip/clk-rk3506.c
825
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RK3506_CLKSEL_CON(15));
drivers/clk/rockchip/clk-rv1126b.c
1069
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_CORECLKSEL_CON(0));
drivers/clk/rockchip/clk-rv1126b.c
1070
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_NPUCLKSEL_CON(0));
drivers/clk/rockchip/clk-rv1126b.c
1071
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VICLKSEL_CON(0));
drivers/clk/rockchip/clk-rv1126b.c
1072
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VEPUCLKSEL_CON(0));
drivers/clk/rockchip/clk-rv1126b.c
1073
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VCPCLKSEL_CON(0));
drivers/clk/samsung/clk-exynos4.c
1189
writel_relaxed(tmp, reg_base + PWR_CTRL1);
drivers/clk/samsung/clk-exynos4.c
1194
writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2);
drivers/clk/samsung/clk-pll.c
1056
writel_relaxed(tmp, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1062
writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
107
writel_relaxed(tmp, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1071
writel_relaxed(tmp, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1149
writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
1159
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1163
writel_relaxed(con1, pll->con_reg + 4);
drivers/clk/samsung/clk-pll.c
119
writel_relaxed(tmp, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1253
writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
1255
writel_relaxed(pll_con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1256
writel_relaxed(pll_con2, pll->con_reg + 8);
drivers/clk/samsung/clk-pll.c
1387
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1393
writel_relaxed(rate->pdiv * PLL1031X_LOCK_FACTOR, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
1414
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
1415
writel_relaxed(con3, pll->con_reg + 0xc);
drivers/clk/samsung/clk-pll.c
254
writel_relaxed(tmp, pll->con_reg);
drivers/clk/samsung/clk-pll.c
261
writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
drivers/clk/samsung/clk-pll.c
264
writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
drivers/clk/samsung/clk-pll.c
274
writel_relaxed(tmp, pll->con_reg);
drivers/clk/samsung/clk-pll.c
368
writel_relaxed(pll_con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
374
writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
383
writel_relaxed(pll_con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
387
writel_relaxed(pll_con1, pll->con_reg + 4);
drivers/clk/samsung/clk-pll.c
486
writel_relaxed(rate->pdiv * PLL0822X_LOCK_FACTOR,
drivers/clk/samsung/clk-pll.c
490
writel_relaxed(pll_con3, pll->con_reg);
drivers/clk/samsung/clk-pll.c
583
writel_relaxed(rate->pdiv * PLL0831X_LOCK_FACTOR, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
586
writel_relaxed(pll_con3, pll->con_reg);
drivers/clk/samsung/clk-pll.c
587
writel_relaxed(pll_con5, pll->con_reg + 8);
drivers/clk/samsung/clk-pll.c
682
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
703
writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
706
writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
713
writel_relaxed(con1, pll->con_reg + 0x4);
drivers/clk/samsung/clk-pll.c
714
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
819
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
857
writel_relaxed(lock, pll->lock_reg);
drivers/clk/samsung/clk-pll.c
858
writel_relaxed(con0, pll->con_reg);
drivers/clk/samsung/clk-pll.c
859
writel_relaxed(con1, pll->con_reg + 0x4);
drivers/clk/sifive/sifive-prci.c
39
writel_relaxed(v, pd->va + offs);
drivers/clk/spear/clk-aux-synth.c
122
writel_relaxed(val, aux->reg);
drivers/clk/spear/clk-frac-synth.c
110
writel_relaxed(val, frac->reg);
drivers/clk/spear/clk-gpt-synth.c
99
writel_relaxed(val, gpt->reg);
drivers/clk/spear/clk-vco-pll.c
160
writel_relaxed(val, pll->vco->cfg_reg);
drivers/clk/spear/clk-vco-pll.c
249
writel_relaxed(val, vco->mode_reg);
drivers/clk/spear/clk-vco-pll.c
263
writel_relaxed(val, vco->cfg_reg);
drivers/clk/starfive/clk-starfive-jh71x0.c
41
writel_relaxed(value, reg);
drivers/clk/stm32/clk-stm32mp1.c
1001
writel_relaxed(1, tim_ker->timpre);
drivers/clk/stm32/clk-stm32mp1.c
473
writel_relaxed(BIT(gate->bit_idx), gate->reg + RCC_CLR);
drivers/clk/stm32/clk-stm32mp1.c
793
writel_relaxed(reg, clk_elem->reg);
drivers/clk/stm32/clk-stm32mp1.c
824
writel_relaxed(reg, clk_elem->reg);
drivers/clk/stm32/clk-stm32mp1.c
998
writel_relaxed(0, tim_ker->timpre);
drivers/clk/tegra/clk-divider.c
117
writel_relaxed(val, divider->reg);
drivers/clk/tegra/clk-periph-gate.c
22
writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
drivers/clk/tegra/clk-periph-gate.c
24
writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
drivers/clk/tegra/clk-periph-gate.c
29
writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
drivers/clk/tegra/clk-periph-gate.c
59
writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
drivers/clk/tegra/clk-periph-gate.c
60
writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
drivers/clk/tegra/clk-periph-gate.c
62
writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
drivers/clk/tegra/clk-pll-out.c
43
writel_relaxed(val, pll_out->reg);
drivers/clk/tegra/clk-pll-out.c
65
writel_relaxed(val, pll_out->reg);
drivers/clk/tegra/clk-pll.c
1177
writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
drivers/clk/tegra/clk-pll.c
1189
writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
drivers/clk/tegra/clk-pll.c
1303
writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
drivers/clk/tegra/clk-pll.c
1805
writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
drivers/clk/tegra/clk-pll.c
1818
writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
drivers/clk/tegra/clk-pll.c
1825
writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
drivers/clk/tegra/clk-pll.c
1830
writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
drivers/clk/tegra/clk-pll.c
1841
writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
drivers/clk/tegra/clk-pll.c
1848
writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
drivers/clk/tegra/clk-pll.c
2099
writel_relaxed(val_iddq,
drivers/clk/tegra/clk-pll.c
237
#define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
drivers/clk/tegra/clk-pll.c
2404
writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
drivers/clk/tegra/clk-pll.c
385
writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
drivers/clk/tegra/clk-pll.c
403
writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
drivers/clk/tegra/clk-super.c
112
writel_relaxed(val, mux->reg);
drivers/clk/tegra/clk-super.c
97
writel_relaxed(val, mux->reg);
drivers/clk/tegra/clk-tegra-audio.c
221
writel_relaxed(1, clk_base + dmic_clks[i].offset);
drivers/clk/tegra/clk-tegra-fixed.c
116
writel_relaxed(val, clk_base + OSC_CTRL);
drivers/clk/tegra/clk-tegra-super-cclk.c
198
writel_relaxed(val, reg + 4);
drivers/clk/tegra/clk-tegra114.c
1212
writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
drivers/clk/tegra/clk-tegra114.c
1239
writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
drivers/clk/tegra/clk-tegra114.c
1261
writel_relaxed(r, clk_base + CPU_FINETRIM_R);
drivers/clk/tegra/clk-tegra114.c
1270
writel_relaxed(dr, clk_base + CPU_FINETRIM_DR);
drivers/clk/tegra/clk-tegra114.c
1287
writel_relaxed(v, clk_base + RST_DFLL_DVCO);
drivers/clk/tegra/clk-tegra114.c
1303
writel_relaxed(v, clk_base + RST_DFLL_DVCO);
drivers/clk/tegra/clk-tegra124.c
1394
writel_relaxed(v, clk_base + RST_DFLL_DVCO);
drivers/clk/tegra/clk-tegra124.c
1410
writel_relaxed(v, clk_base + RST_DFLL_DVCO);
drivers/clk/tegra/clk-tegra20-emc.c
126
writel_relaxed(val, emc->reg);
drivers/clk/tegra/clk-tegra20-emc.c
161
writel_relaxed(val, emc->reg);
drivers/clk/tegra/clk-tegra20-emc.c
94
writel_relaxed(val, emc->reg);
drivers/clk/tegra/clk-tegra210.c
1006
writel_relaxed(val, clk_base + plldss->params->base_reg);
drivers/clk/tegra/clk-tegra210.c
1010
writel_relaxed(misc0_val, clk_base +
drivers/clk/tegra/clk-tegra210.c
1016
writel_relaxed(misc0_val, clk_base +
drivers/clk/tegra/clk-tegra210.c
1019
writel_relaxed(misc1_val & (~PLLDSS_MISC1_CFG_EN_SSC),
drivers/clk/tegra/clk-tegra210.c
1021
writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]);
drivers/clk/tegra/clk-tegra210.c
1022
writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]);
drivers/clk/tegra/clk-tegra210.c
1091
writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);
drivers/clk/tegra/clk-tegra210.c
1103
writel_relaxed(val, clk_base + pllre->params->base_reg);
drivers/clk/tegra/clk-tegra210.c
1104
writel_relaxed(PLLRE_MISC0_DEFAULT_VALUE,
drivers/clk/tegra/clk-tegra210.c
1199
writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
drivers/clk/tegra/clk-tegra210.c
1205
writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]);
drivers/clk/tegra/clk-tegra210.c
1212
writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base +
drivers/clk/tegra/clk-tegra210.c
1216
writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base +
drivers/clk/tegra/clk-tegra210.c
1220
writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
drivers/clk/tegra/clk-tegra210.c
1223
writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base +
drivers/clk/tegra/clk-tegra210.c
1227
writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base +
drivers/clk/tegra/clk-tegra210.c
1229
writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base +
drivers/clk/tegra/clk-tegra210.c
1258
writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);
drivers/clk/tegra/clk-tegra210.c
1265
writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE,
drivers/clk/tegra/clk-tegra210.c
1317
writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]);
drivers/clk/tegra/clk-tegra210.c
1324
writel_relaxed(PLLP_MISC0_DEFAULT_VALUE,
drivers/clk/tegra/clk-tegra210.c
1332
writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]);
drivers/clk/tegra/clk-tegra210.c
1379
writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]);
drivers/clk/tegra/clk-tegra210.c
1384
writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]);
drivers/clk/tegra/clk-tegra210.c
1391
writel_relaxed(PLLU_MISC0_DEFAULT_VALUE,
drivers/clk/tegra/clk-tegra210.c
1393
writel_relaxed(PLLU_MISC1_DEFAULT_VALUE,
drivers/clk/tegra/clk-tegra210.c
1441
writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
drivers/clk/tegra/clk-tegra210.c
1446
writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
drivers/clk/tegra/clk-tegra210.c
1455
writel_relaxed(base, clk_base + pllx->params->base_reg);
drivers/clk/tegra/clk-tegra210.c
1459
writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
drivers/clk/tegra/clk-tegra210.c
2787
writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
drivers/clk/tegra/clk-tegra210.c
2797
writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
drivers/clk/tegra/clk-tegra210.c
2819
writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
drivers/clk/tegra/clk-tegra210.c
2833
writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
drivers/clk/tegra/clk-tegra210.c
2847
writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
drivers/clk/tegra/clk-tegra210.c
2853
writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
drivers/clk/tegra/clk-tegra210.c
2865
writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
drivers/clk/tegra/clk-tegra210.c
2871
writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
drivers/clk/tegra/clk-tegra210.c
2876
writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
drivers/clk/tegra/clk-tegra210.c
2882
writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
drivers/clk/tegra/clk-tegra210.c
2889
writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
drivers/clk/tegra/clk-tegra210.c
2913
writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);
drivers/clk/tegra/clk-tegra210.c
2968
writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
drivers/clk/tegra/clk-tegra210.c
2972
writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
drivers/clk/tegra/clk-tegra210.c
2977
writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
drivers/clk/tegra/clk-tegra210.c
2982
writel_relaxed(reg, clk_base + PLLU_BASE);
drivers/clk/tegra/clk-tegra210.c
3442
writel_relaxed(_val, clk_base + (_base) + ((_off) * 4))
drivers/clk/tegra/clk-tegra210.c
3478
writel_relaxed(spare_reg_ctx, clk_base + SPARE_REG0);
drivers/clk/tegra/clk-tegra210.c
3479
writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB);
drivers/clk/tegra/clk-tegra210.c
3480
writel_relaxed(clk_msk_arm_ctx, clk_base + CLK_MASK_ARM);
drivers/clk/tegra/clk-tegra210.c
3492
writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_L, clk_base + CLK_OUT_ENB_L);
drivers/clk/tegra/clk-tegra210.c
3493
writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_H, clk_base + CLK_OUT_ENB_H);
drivers/clk/tegra/clk-tegra210.c
3494
writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_U, clk_base + CLK_OUT_ENB_U);
drivers/clk/tegra/clk-tegra210.c
3495
writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_V, clk_base + CLK_OUT_ENB_V);
drivers/clk/tegra/clk-tegra210.c
3496
writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_W, clk_base + CLK_OUT_ENB_W);
drivers/clk/tegra/clk-tegra210.c
3497
writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_X, clk_base + CLK_OUT_ENB_X);
drivers/clk/tegra/clk-tegra210.c
3498
writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_Y, clk_base + CLK_OUT_ENB_Y);
drivers/clk/tegra/clk-tegra210.c
3644
writel_relaxed(v, clk_base + RST_DFLL_DVCO);
drivers/clk/tegra/clk-tegra210.c
3660
writel_relaxed(v, clk_base + RST_DFLL_DVCO);
drivers/clk/tegra/clk-tegra210.c
525
writel_relaxed(value, clk_base + PLLE_MISC0);
drivers/clk/tegra/clk-tegra210.c
530
writel_relaxed(value, clk_base + PLLE_AUX);
drivers/clk/tegra/clk-tegra210.c
535
writel_relaxed(value, clk_base + PLLE_AUX);
drivers/clk/tegra/clk-tegra210.c
552
writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
drivers/clk/tegra/clk-tegra210.c
562
writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
drivers/clk/tegra/clk-tegra210.c
574
writel_relaxed(val, clk_base + SATA_PLL_CFG0);
drivers/clk/tegra/clk-tegra210.c
584
writel_relaxed(val, clk_base + SATA_PLL_CFG0);
drivers/clk/tegra/clk-tegra210.c
604
writel_relaxed(val, clk_base + SATA_PLL_CFG0);
drivers/clk/tegra/clk-tegra210.c
613
writel_relaxed(CLK_OUT_ENB_X_CLK_ENB_EMC_DLL, clk_base + offset);
drivers/clk/tegra/clk-tegra210.c
619
writel_relaxed(emc_dll_src_value, clk_base + CLK_SOURCE_EMC_DLL);
drivers/clk/tegra/clk-tegra210.c
625
writel_relaxed(emc_src_value, clk_base + CLK_SOURCE_EMC);
drivers/clk/tegra/clk-tegra210.c
634
writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset);
drivers/clk/tegra/clk-tegra210.c
636
writel_relaxed(val, clk_base + mbist->lvl2_offset);
drivers/clk/tegra/clk-tegra210.c
648
writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE);
drivers/clk/tegra/clk-tegra210.c
652
writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA);
drivers/clk/tegra/clk-tegra210.c
654
writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE);
drivers/clk/tegra/clk-tegra210.c
657
writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
drivers/clk/tegra/clk-tegra210.c
658
writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
drivers/clk/tegra/clk-tegra210.c
659
writel_relaxed(csi_src, clk_base + PLLD_BASE);
drivers/clk/tegra/clk-tegra210.c
670
writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA);
drivers/clk/tegra/clk-tegra210.c
674
writel_relaxed(dsc_top_ctrl | BIT(2), dispa_base + DC_COM_DSC_TOP_CTL);
drivers/clk/tegra/clk-tegra210.c
676
writel_relaxed(dsc_top_ctrl, dispa_base + DC_COM_DSC_TOP_CTL);
drivers/clk/tegra/clk-tegra210.c
679
writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
drivers/clk/tegra/clk-tegra210.c
688
writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE);
drivers/clk/tegra/clk-tegra210.c
692
writel_relaxed(val | BIT(0) | GENMASK(7, 2) | BIT(24),
drivers/clk/tegra/clk-tegra210.c
696
writel_relaxed(val, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
drivers/clk/tegra/clk-tegra210.c
699
writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
drivers/clk/tegra/clk-tegra210.c
711
writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC);
drivers/clk/tegra/clk-tegra210.c
712
writel_relaxed(ovre | BIT(10) | BIT(11),
drivers/clk/tegra/clk-tegra210.c
722
writel_relaxed(i2s_ctrl | BIT(10),
drivers/clk/tegra/clk-tegra210.c
724
writel_relaxed(0, i2s_base + TEGRA210_I2S_CG);
drivers/clk/tegra/clk-tegra210.c
726
writel_relaxed(1, i2s_base + TEGRA210_I2S_CG);
drivers/clk/tegra/clk-tegra210.c
727
writel_relaxed(i2s_ctrl, i2s_base + TEGRA210_I2S_CTRL);
drivers/clk/tegra/clk-tegra210.c
733
writel_relaxed(ovrc, clk_base + LVL2_CLK_GATE_OVRC);
drivers/clk/tegra/clk-tegra210.c
734
writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
drivers/clk/tegra/clk-tegra210.c
795
writel_relaxed(PLLCX_MISC0_DEFAULT_VALUE,
drivers/clk/tegra/clk-tegra210.c
797
writel_relaxed(PLLCX_MISC1_DEFAULT_VALUE,
drivers/clk/tegra/clk-tegra210.c
799
writel_relaxed(PLLCX_MISC2_DEFAULT_VALUE,
drivers/clk/tegra/clk-tegra210.c
801
writel_relaxed(PLLCX_MISC3_DEFAULT_VALUE,
drivers/clk/tegra/clk-tegra210.c
863
writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]);
drivers/clk/tegra/clk-tegra210.c
871
writel_relaxed(val, clk_base + plla->params->base_reg);
drivers/clk/tegra/clk-tegra210.c
872
writel_relaxed(PLLA_MISC0_DEFAULT_VALUE,
drivers/clk/tegra/clk-tegra210.c
874
writel_relaxed(PLLA_MISC2_DEFAULT_VALUE,
drivers/clk/tegra/clk-tegra210.c
916
writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
drivers/clk/tegra/clk-tegra210.c
926
writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
drivers/clk/tegra/clk-tegra210.c
927
writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base +
drivers/clk/tegra/clk-tegra210.c
990
writel_relaxed(val, clk_base +
drivers/clk/tegra/clk-tegra210.c
997
writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]);
drivers/clk/tegra/clk.c
114
writel_relaxed(BIT(id % 32),
drivers/clk/tegra/clk.c
128
writel_relaxed(BIT(id % 32),
drivers/clk/tegra/clk.c
174
writel_relaxed(val, clk_base + CLK_OUT_ENB_Y);
drivers/clk/tegra/clk.c
197
writel_relaxed(periph_state_ctx[idx],
drivers/clk/tegra/clk.c
207
writel_relaxed(periph_state_ctx[idx],
drivers/clk/ti/adpll.c
355
writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
drivers/clk/ti/adpll.c
367
writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
drivers/clk/ti/adpll.c
784
writel_relaxed(ADPLL_PLLSS_MMR_UNLOCK_MAGIC, reg);
drivers/clk/ti/clk.c
48
writel_relaxed(val, reg->ptr);
drivers/clk/ti/clk.c
52
writel_relaxed(val, io->mem + reg->offset);
drivers/clk/ti/clk.c
62
writel_relaxed(v, ptr);
drivers/clk/ti/fapll.c
108
writel_relaxed(v, fd->base);
drivers/clk/ti/fapll.c
137
writel_relaxed(v, fd->base);
drivers/clk/ti/fapll.c
149
writel_relaxed(v, fd->base);
drivers/clk/ti/fapll.c
260
writel_relaxed(v, fd->base);
drivers/clk/ti/fapll.c
284
writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
drivers/clk/ti/fapll.c
295
writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
drivers/clk/ti/fapll.c
400
writel_relaxed(v, synth->freq);
drivers/clk/ti/fapll.c
476
writel_relaxed(v, synth->div);
drivers/clk/ti/fapll.c
97
writel_relaxed(v, fd->base);
drivers/clocksource/arm_arch_timer_mmio.c
223
writel_relaxed(cntacr, cntctlbase + CNTACR(i));
drivers/clocksource/arm_arch_timer_mmio.c
65
writel_relaxed((u32)val, timer->base + CNTP_CTL);
drivers/clocksource/arm_arch_timer_mmio.c
79
writel_relaxed((u32)val, timer->base + CNTV_CTL);
drivers/clocksource/arm_global_timer.c
108
writel_relaxed(ctrl, gt_base + GT_CONTROL);
drivers/clocksource/arm_global_timer.c
109
writel_relaxed(lower_32_bits(counter), gt_base + GT_COMP0);
drivers/clocksource/arm_global_timer.c
110
writel_relaxed(upper_32_bits(counter), gt_base + GT_COMP1);
drivers/clocksource/arm_global_timer.c
113
writel_relaxed(delta, gt_base + GT_AUTO_INC);
drivers/clocksource/arm_global_timer.c
118
writel_relaxed(ctrl, gt_base + GT_CONTROL);
drivers/clocksource/arm_global_timer.c
167
writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
drivers/clocksource/armv7m_systick.c
57
writel_relaxed(SYSTICK_LOAD_RELOAD_MASK, base + SYST_RVR);
drivers/clocksource/armv7m_systick.c
58
writel_relaxed(SYST_CSR_ENABLE, base + SYST_CSR);
drivers/clocksource/asm9260_timer.c
113
writel_relaxed(delta, priv.base + HW_MR0);
drivers/clocksource/asm9260_timer.c
115
writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
drivers/clocksource/asm9260_timer.c
122
writel_relaxed(BM_C0_EN, priv.base + HW_TCR + CLR_REG);
drivers/clocksource/asm9260_timer.c
136
writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0),
drivers/clocksource/asm9260_timer.c
146
writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0),
drivers/clocksource/asm9260_timer.c
149
writel_relaxed(priv.ticks_per_jiffy, priv.base + HW_MR0);
drivers/clocksource/asm9260_timer.c
151
writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
drivers/clocksource/asm9260_timer.c
173
writel_relaxed(BM_IR_MR0, priv.base + HW_IR);
drivers/clocksource/asm9260_timer.c
218
writel_relaxed(BM_DIR_DEFAULT, priv.base + HW_DIR);
drivers/clocksource/asm9260_timer.c
220
writel_relaxed(BM_PR_DISABLE, priv.base + HW_PR);
drivers/clocksource/asm9260_timer.c
222
writel_relaxed(BM_CTCR_DEFAULT, priv.base + HW_CTCR);
drivers/clocksource/asm9260_timer.c
224
writel_relaxed(BM_MCR_INT_EN(0) , priv.base + HW_MCR);
drivers/clocksource/asm9260_timer.c
232
writel_relaxed(0xffffffff, priv.base + HW_MR1);
drivers/clocksource/asm9260_timer.c
234
writel_relaxed(BM_C1_EN, priv.base + HW_TCR + SET_REG);
drivers/clocksource/bcm2835_timer.c
48
writel_relaxed(readl_relaxed(system_clock) + event,
drivers/clocksource/bcm2835_timer.c
58
writel_relaxed(timer->match_mask, timer->control);
drivers/clocksource/clksrc_st_lpc.c
32
writel_relaxed(0, ddata.base + LPC_LPT_START_OFF);
drivers/clocksource/clksrc_st_lpc.c
33
writel_relaxed(0, ddata.base + LPC_LPT_MSB_OFF);
drivers/clocksource/clksrc_st_lpc.c
34
writel_relaxed(0, ddata.base + LPC_LPT_LSB_OFF);
drivers/clocksource/clksrc_st_lpc.c
35
writel_relaxed(1, ddata.base + LPC_LPT_START_OFF);
drivers/clocksource/dw_apb_timer.c
68
writel_relaxed(val, timer->base + offs);
drivers/clocksource/exynos_mct.c
149
writel_relaxed(mask, reg_base + stat_addr);
drivers/clocksource/exynos_mct.c
98
writel_relaxed(value, reg_base + offset);
drivers/clocksource/mps2-timer.c
158
writel_relaxed(0, base + TIMER_CTRL);
drivers/clocksource/mps2-timer.c
217
writel_relaxed(0, base + TIMER_CTRL);
drivers/clocksource/mps2-timer.c
220
writel_relaxed(0xffffffff, base + TIMER_VALUE);
drivers/clocksource/mps2-timer.c
221
writel_relaxed(0xffffffff, base + TIMER_RELOAD);
drivers/clocksource/mps2-timer.c
223
writel_relaxed(TIMER_CTRL_ENABLE, base + TIMER_CTRL);
drivers/clocksource/mps2-timer.c
51
writel_relaxed(val, to_mps2_clkevt(c)->reg + offset);
drivers/clocksource/mps2-timer.c
91
writel_relaxed(1, ce->reg + TIMER_INT);
drivers/clocksource/samsung_pwm_timer.c
131
writel_relaxed(tcon, pwm.base + REG_TCON);
drivers/clocksource/samsung_pwm_timer.c
152
writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel));
drivers/clocksource/samsung_pwm_timer.c
153
writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel));
drivers/clocksource/samsung_pwm_timer.c
154
writel_relaxed(tcon, pwm.base + REG_TCON);
drivers/clocksource/samsung_pwm_timer.c
179
writel_relaxed(tcon, pwm.base + REG_TCON);
drivers/clocksource/timer-atmel-pit.c
66
writel_relaxed(value, base + reg_offset);
drivers/clocksource/timer-atmel-tcb.c
221
writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC));
drivers/clocksource/timer-atmel-tcb.c
224
writel_relaxed(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
drivers/clocksource/timer-cadence-ttc.c
118
writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
drivers/clocksource/timer-cadence-ttc.c
120
writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
drivers/clocksource/timer-cadence-ttc.c
128
writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
drivers/clocksource/timer-cadence-ttc.c
205
writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
drivers/clocksource/timer-cadence-ttc.c
233
writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
drivers/clocksource/timer-cadence-ttc.c
301
writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
drivers/clocksource/timer-cadence-ttc.c
311
writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
drivers/clocksource/timer-cadence-ttc.c
321
writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
drivers/clocksource/timer-cadence-ttc.c
372
writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
drivers/clocksource/timer-cadence-ttc.c
373
writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
drivers/clocksource/timer-cadence-ttc.c
375
writel_relaxed(CNT_CNTRL_RESET,
drivers/clocksource/timer-cadence-ttc.c
460
writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
drivers/clocksource/timer-cadence-ttc.c
461
writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
drivers/clocksource/timer-cadence-ttc.c
463
writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
drivers/clocksource/timer-davinci.c
112
writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
drivers/clocksource/timer-davinci.c
205
writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34);
drivers/clocksource/timer-davinci.c
206
writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD34);
drivers/clocksource/timer-davinci.c
207
writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
drivers/clocksource/timer-davinci.c
222
writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12);
drivers/clocksource/timer-davinci.c
223
writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD12);
drivers/clocksource/timer-davinci.c
224
writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
drivers/clocksource/timer-davinci.c
230
writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TCR);
drivers/clocksource/timer-davinci.c
235
writel_relaxed(DAVINCI_TIMER_TGCR_DEFAULT,
drivers/clocksource/timer-davinci.c
238
writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12);
drivers/clocksource/timer-davinci.c
239
writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34);
drivers/clocksource/timer-davinci.c
82
writel_relaxed(val, clockevent->base + reg);
drivers/clocksource/timer-davinci.c
99
writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
drivers/clocksource/timer-gx6605s.c
105
writel_relaxed(0, base + TIMER_DIV);
drivers/clocksource/timer-gx6605s.c
106
writel_relaxed(0, base + TIMER_CONFIG);
drivers/clocksource/timer-gx6605s.c
114
writel_relaxed(0, base + TIMER_DIV);
drivers/clocksource/timer-gx6605s.c
115
writel_relaxed(0, base + TIMER_INI);
drivers/clocksource/timer-gx6605s.c
117
writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
drivers/clocksource/timer-gx6605s.c
119
writel_relaxed(GX6605S_CONFIG_EN, base + TIMER_CONFIG);
drivers/clocksource/timer-gx6605s.c
121
writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
drivers/clocksource/timer-gx6605s.c
30
writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS);
drivers/clocksource/timer-gx6605s.c
31
writel_relaxed(0, base + TIMER_INI);
drivers/clocksource/timer-gx6605s.c
43
writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
drivers/clocksource/timer-gx6605s.c
46
writel_relaxed(GX6605S_CONFIG_EN | GX6605S_CONFIG_IRQ_EN,
drivers/clocksource/timer-gx6605s.c
58
writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
drivers/clocksource/timer-gx6605s.c
61
writel_relaxed(ULONG_MAX - delta, base + TIMER_INI);
drivers/clocksource/timer-gx6605s.c
62
writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
drivers/clocksource/timer-gx6605s.c
71
writel_relaxed(0, base + TIMER_CONTRL);
drivers/clocksource/timer-gx6605s.c
72
writel_relaxed(0, base + TIMER_CONFIG);
drivers/clocksource/timer-gxp.c
52
writel_relaxed(event, timer->counter);
drivers/clocksource/timer-imx-gpt.c
104
writel_relaxed(0, imxtm->base + V2_IR);
drivers/clocksource/timer-imx-gpt.c
112
writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
drivers/clocksource/timer-imx-gpt.c
117
writel_relaxed(1<<0, imxtm->base + V2_IR);
drivers/clocksource/timer-imx-gpt.c
122
writel_relaxed(0, imxtm->base + MX1_2_TSTAT);
drivers/clocksource/timer-imx-gpt.c
127
writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
drivers/clocksource/timer-imx-gpt.c
133
writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);
drivers/clocksource/timer-imx-gpt.c
180
writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);
drivers/clocksource/timer-imx-gpt.c
194
writel_relaxed(tcmp, imxtm->base + V2_TCMP);
drivers/clocksource/timer-imx-gpt.c
211
writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
drivers/clocksource/timer-imx-gpt.c
233
writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
drivers/clocksource/timer-imx-gpt.c
296
writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
drivers/clocksource/timer-imx-gpt.c
309
writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
drivers/clocksource/timer-imx-gpt.c
320
writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
drivers/clocksource/timer-imx-gpt.c
326
writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
drivers/clocksource/timer-imx-gpt.c
408
writel_relaxed(0, imxtm->base + MXC_TCTL);
drivers/clocksource/timer-imx-gpt.c
409
writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */
drivers/clocksource/timer-imx-gpt.c
99
writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
drivers/clocksource/timer-imx-sysctr.c
85
writel_relaxed(cmp_hi, base + CMPCV_HI);
drivers/clocksource/timer-imx-sysctr.c
86
writel_relaxed(cmp_lo, base + CMPCV_LO);
drivers/clocksource/timer-keystone.c
55
writel_relaxed(val, timer.base + rg);
drivers/clocksource/timer-lpc32xx.c
102
writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR);
drivers/clocksource/timer-lpc32xx.c
105
writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R |
drivers/clocksource/timer-lpc32xx.c
116
writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R,
drivers/clocksource/timer-lpc32xx.c
123
writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR);
drivers/clocksource/timer-lpc32xx.c
124
writel_relaxed(ddata->ticks_per_jiffy, ddata->base + LPC32XX_TIMER_MR0);
drivers/clocksource/timer-lpc32xx.c
125
writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR);
drivers/clocksource/timer-lpc32xx.c
135
writel_relaxed(LPC32XX_TIMER_IR_MR0INT, ddata->base + LPC32XX_TIMER_IR);
drivers/clocksource/timer-lpc32xx.c
186
writel_relaxed(LPC32XX_TIMER_TCR_CRST, base + LPC32XX_TIMER_TCR);
drivers/clocksource/timer-lpc32xx.c
187
writel_relaxed(0, base + LPC32XX_TIMER_PR);
drivers/clocksource/timer-lpc32xx.c
188
writel_relaxed(0, base + LPC32XX_TIMER_MCR);
drivers/clocksource/timer-lpc32xx.c
189
writel_relaxed(0, base + LPC32XX_TIMER_CTCR);
drivers/clocksource/timer-lpc32xx.c
190
writel_relaxed(LPC32XX_TIMER_TCR_CEN, base + LPC32XX_TIMER_TCR);
drivers/clocksource/timer-lpc32xx.c
253
writel_relaxed(0, base + LPC32XX_TIMER_TCR);
drivers/clocksource/timer-lpc32xx.c
254
writel_relaxed(0, base + LPC32XX_TIMER_PR);
drivers/clocksource/timer-lpc32xx.c
255
writel_relaxed(0, base + LPC32XX_TIMER_CTCR);
drivers/clocksource/timer-lpc32xx.c
256
writel_relaxed(LPC32XX_TIMER_IR_MR0INT, base + LPC32XX_TIMER_IR);
drivers/clocksource/timer-lpc32xx.c
75
writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR);
drivers/clocksource/timer-lpc32xx.c
76
writel_relaxed(delta, ddata->base + LPC32XX_TIMER_MR0);
drivers/clocksource/timer-lpc32xx.c
77
writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR);
drivers/clocksource/timer-lpc32xx.c
88
writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR);
drivers/clocksource/timer-microchip-pit64b.c
127
writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
drivers/clocksource/timer-microchip-pit64b.c
128
writel_relaxed(mode | timer->mode, timer->base + MCHP_PIT64B_MR);
drivers/clocksource/timer-microchip-pit64b.c
129
writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR);
drivers/clocksource/timer-microchip-pit64b.c
130
writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR);
drivers/clocksource/timer-microchip-pit64b.c
131
writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER);
drivers/clocksource/timer-microchip-pit64b.c
132
writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);
drivers/clocksource/timer-microchip-pit64b.c
137
writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
drivers/clocksource/timer-milbeaut.c
129
writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
drivers/clocksource/timer-milbeaut.c
130
writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS);
drivers/clocksource/timer-milbeaut.c
131
writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS);
drivers/clocksource/timer-milbeaut.c
133
writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
drivers/clocksource/timer-milbeaut.c
139
writel_relaxed(0, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
drivers/clocksource/timer-milbeaut.c
57
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
drivers/clocksource/timer-milbeaut.c
71
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
drivers/clocksource/timer-milbeaut.c
79
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
drivers/clocksource/timer-milbeaut.c
84
writel_relaxed(cnt, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
drivers/clocksource/timer-pxa.c
53
#define timer_writel(val, reg) writel_relaxed((val), timer_base + (reg))
drivers/clocksource/timer-qcom.c
185
writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
drivers/clocksource/timer-qcom.c
244
writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
drivers/clocksource/timer-qcom.c
44
writel_relaxed(ctrl, event_base + TIMER_ENABLE);
drivers/clocksource/timer-qcom.c
56
writel_relaxed(ctrl, event_base + TIMER_ENABLE);
drivers/clocksource/timer-qcom.c
58
writel_relaxed(ctrl, event_base + TIMER_CLEAR);
drivers/clocksource/timer-qcom.c
59
writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
drivers/clocksource/timer-qcom.c
65
writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
drivers/clocksource/timer-qcom.c
75
writel_relaxed(ctrl, event_base + TIMER_ENABLE);
drivers/clocksource/timer-rda.c
121
writel_relaxed(RDA_TIMER_IRQ_CLR_OSTIMER,
drivers/clocksource/timer-rda.c
47
writel_relaxed(RDA_TIMER_IRQ_MASK_OSTIMER,
drivers/clocksource/timer-rda.c
51
writel_relaxed(load_l, base + RDA_OSTIMER_LOADVAL_L);
drivers/clocksource/timer-rda.c
52
writel_relaxed(ctrl, base + RDA_OSTIMER_CTRL);
drivers/clocksource/timer-rda.c
60
writel_relaxed(RDA_TIMER_IRQ_MASK_OSTIMER,
drivers/clocksource/timer-rda.c
63
writel_relaxed(0, base + RDA_OSTIMER_CTRL);
drivers/clocksource/timer-rockchip.c
57
writel_relaxed(TIMER_DISABLE, timer->ctrl);
drivers/clocksource/timer-rockchip.c
62
writel_relaxed(TIMER_ENABLE | flags, timer->ctrl);
drivers/clocksource/timer-rockchip.c
68
writel_relaxed(cycles, timer->base + TIMER_LOAD_COUNT0);
drivers/clocksource/timer-rockchip.c
69
writel_relaxed(0, timer->base + TIMER_LOAD_COUNT1);
drivers/clocksource/timer-rockchip.c
74
writel_relaxed(1, timer->base + TIMER_INT_STATUS);
drivers/clocksource/timer-sprd.c
180
writel_relaxed(TIMER_VALUE_LO_MASK,
drivers/clocksource/timer-sprd.c
182
writel_relaxed(TIMER_VALUE_HI_MASK,
drivers/clocksource/timer-sprd.c
50
writel_relaxed(val, base + TIMER_CTL);
drivers/clocksource/timer-sprd.c
58
writel_relaxed(val, base + TIMER_CTL);
drivers/clocksource/timer-sprd.c
63
writel_relaxed(cycles & TIMER_VALUE_LO_MASK, base + TIMER_LOAD_LO);
drivers/clocksource/timer-sprd.c
64
writel_relaxed(0, base + TIMER_LOAD_HI);
drivers/clocksource/timer-sprd.c
69
writel_relaxed(TIMER_INT_EN, base + TIMER_INT);
drivers/clocksource/timer-sprd.c
77
writel_relaxed(val, base + TIMER_INT);
drivers/clocksource/timer-stm32.c
101
writel_relaxed(0, timer_of_base(to) + TIM_DIER);
drivers/clocksource/timer-stm32.c
114
writel_relaxed(TIM_CR1_UDIS | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1);
drivers/clocksource/timer-stm32.c
133
writel_relaxed(next, timer_of_base(to) + TIM_CCR1);
drivers/clocksource/timer-stm32.c
139
writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER);
drivers/clocksource/timer-stm32.c
167
writel_relaxed(0, timer_of_base(to) + TIM_SR);
drivers/clocksource/timer-stm32.c
192
writel_relaxed(UINT_MAX, timer_of_base(to) + TIM_ARR);
drivers/clocksource/timer-stm32.c
222
writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC);
drivers/clocksource/timer-stm32.c
223
writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR);
drivers/clocksource/timer-stm32.c
224
writel_relaxed(0, timer_of_base(to) + TIM_SR);
drivers/clocksource/timer-tegra.c
108
writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
drivers/clocksource/timer-tegra.c
113
writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
drivers/clocksource/timer-tegra.c
136
writel_relaxed(0, timer_of_base(to) + TIMER_PTV);
drivers/clocksource/timer-tegra.c
137
writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR);
drivers/clocksource/timer-tegra.c
298
writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
drivers/clocksource/timer-tegra.c
68
writel_relaxed(TIMER_PTV_EN | (cycles - 1), reg_base + TIMER_PTV);
drivers/clocksource/timer-tegra.c
77
writel_relaxed(0, reg_base + TIMER_PTV);
drivers/clocksource/timer-tegra.c
87
writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1),
drivers/clocksource/timer-tegra.c
98
writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
drivers/clocksource/timer-tegra186.c
100
writel_relaxed(value, tmr->regs + offset);
drivers/clocksource/timer-tegra186.c
105
writel_relaxed(value, wdt->regs + offset);
drivers/clocksource/timer-ti-32k.c
120
writel_relaxed(0, sysc);
drivers/clocksource/timer-ti-dm-systimer.c
100
writel_relaxed(BIT(1) | BIT(2), t->base + t->ifctrl);
drivers/clocksource/timer-ti-dm-systimer.c
116
writel_relaxed(l, sysc);
drivers/clocksource/timer-ti-dm-systimer.c
439
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);
drivers/clocksource/timer-ti-dm-systimer.c
454
writel_relaxed(0xffffffff - cycles, t->base + t->counter);
drivers/clocksource/timer-ti-dm-systimer.c
458
writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl);
drivers/clocksource/timer-ti-dm-systimer.c
473
writel_relaxed(l, ctrl);
drivers/clocksource/timer-ti-dm-systimer.c
479
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);
drivers/clocksource/timer-ti-dm-systimer.c
495
writel_relaxed(clkevt->period, t->base + t->load);
drivers/clocksource/timer-ti-dm-systimer.c
499
writel_relaxed(clkevt->period, t->base + t->counter);
drivers/clocksource/timer-ti-dm-systimer.c
503
writel_relaxed(OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
drivers/clocksource/timer-ti-dm-systimer.c
529
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);
drivers/clocksource/timer-ti-dm-systimer.c
530
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
drivers/clocksource/timer-ti-dm-systimer.c
576
writel_relaxed(OMAP_TIMER_CTRL_POSTED, t->base + t->ifctrl);
drivers/clocksource/timer-ti-dm-systimer.c
583
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);
drivers/clocksource/timer-ti-dm-systimer.c
584
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
drivers/clocksource/timer-ti-dm-systimer.c
748
writel_relaxed(clksrc->loadval, t->base + t->counter);
drivers/clocksource/timer-ti-dm-systimer.c
749
writel_relaxed(OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
drivers/clocksource/timer-ti-dm-systimer.c
783
writel_relaxed(0, t->base + t->counter);
drivers/clocksource/timer-ti-dm-systimer.c
784
writel_relaxed(OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
drivers/clocksource/timer-ti-dm-systimer.c
82
writel_relaxed(val, t->base + t->sysc);
drivers/clocksource/timer-ti-dm-systimer.c
90
writel_relaxed(DMTIMER_TYPE1_DISABLE, t->base + t->sysc);
drivers/clocksource/timer-ti-dm.c
204
writel_relaxed(val, timer->func_base + offset);
drivers/cpufreq/kirkwood-cpufreq.c
61
writel_relaxed(reg, priv.base);
drivers/cpufreq/kirkwood-cpufreq.c
78
writel_relaxed(reg, priv.base);
drivers/cpufreq/mediatek-cpufreq-hw.c
132
writel_relaxed(target_freq, priv->fdvfs + cpu * 4);
drivers/cpufreq/mediatek-cpufreq-hw.c
146
writel_relaxed(index, data->reg_bases[REG_FREQ_PERF_STATE]);
drivers/cpufreq/mediatek-cpufreq-hw.c
181
writel_relaxed(index, data->reg_bases[REG_FREQ_PERF_STATE]);
drivers/cpufreq/mediatek-cpufreq-hw.c
318
writel_relaxed(0x1, data->reg_bases[REG_FREQ_ENABLE]);
drivers/cpufreq/mediatek-cpufreq-hw.c
341
writel_relaxed(0x0, data->reg_bases[REG_FREQ_ENABLE]);
drivers/cpufreq/qcom-cpufreq-hw.c
121
writel_relaxed(index, data->base + soc_data->reg_perf_state);
drivers/cpufreq/qcom-cpufreq-hw.c
125
writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4);
drivers/cpufreq/qcom-cpufreq-hw.c
193
writel_relaxed(index, data->base + soc_data->reg_perf_state);
drivers/cpufreq/qcom-cpufreq-hw.c
197
writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4);
drivers/cpufreq/qcom-cpufreq-hw.c
394
writel_relaxed(GT_IRQ_STATUS,
drivers/cpufreq/s5pv210-cpufreq.c
220
writel_relaxed(tmp1, reg);
drivers/cpufreq/s5pv210-cpufreq.c
300
writel_relaxed(reg, S5P_CLK_DIV2);
drivers/cpufreq/s5pv210-cpufreq.c
315
writel_relaxed(reg, S5P_CLK_SRC2);
drivers/cpufreq/s5pv210-cpufreq.c
333
writel_relaxed(reg, S5P_CLK_SRC0);
drivers/cpufreq/s5pv210-cpufreq.c
358
writel_relaxed(reg, S5P_CLK_DIV0);
drivers/cpufreq/s5pv210-cpufreq.c
372
writel_relaxed(reg, S5P_ARM_MCS_CON);
drivers/cpufreq/s5pv210-cpufreq.c
376
writel_relaxed(0x2cf, S5P_APLL_LOCK);
drivers/cpufreq/s5pv210-cpufreq.c
384
writel_relaxed(APLL_VAL_1000, S5P_APLL_CON);
drivers/cpufreq/s5pv210-cpufreq.c
386
writel_relaxed(APLL_VAL_800, S5P_APLL_CON);
drivers/cpufreq/s5pv210-cpufreq.c
401
writel_relaxed(reg, S5P_CLK_SRC2);
drivers/cpufreq/s5pv210-cpufreq.c
415
writel_relaxed(reg, S5P_CLK_DIV2);
drivers/cpufreq/s5pv210-cpufreq.c
426
writel_relaxed(reg, S5P_CLK_SRC0);
drivers/cpufreq/s5pv210-cpufreq.c
449
writel_relaxed(reg, S5P_CLK_DIV6);
drivers/cpufreq/virtual-cpufreq.c
109
writel_relaxed(idx, base + cpu * PER_CPU_OFFSET +
drivers/cpufreq/virtual-cpufreq.c
95
writel_relaxed(target_freq,
drivers/crypto/amlogic/amlogic-gxl-core.c
35
writel_relaxed(0xF, mc->base + ((0x4 + flow) << 2));
drivers/crypto/atmel-aes.c
363
writel_relaxed(value, dd->io_base + offset);
drivers/crypto/atmel-sha.c
281
writel_relaxed(value, dd->io_base + offset);
drivers/crypto/atmel-tdes.c
179
writel_relaxed(value, dd->io_base + offset);
drivers/crypto/axis/artpec6_crypto.c
2531
writel_relaxed(out, base + PDMA_OUT_BUF_CFG);
drivers/crypto/axis/artpec6_crypto.c
2532
writel_relaxed(PDMA_OUT_CFG_EN, base + PDMA_OUT_CFG);
drivers/crypto/axis/artpec6_crypto.c
2535
writel_relaxed(in, base + A6_PDMA_IN_BUF_CFG);
drivers/crypto/axis/artpec6_crypto.c
2536
writel_relaxed(PDMA_IN_CFG_EN, base + A6_PDMA_IN_CFG);
drivers/crypto/axis/artpec6_crypto.c
2537
writel_relaxed(A6_PDMA_INTR_MASK_IN_DATA |
drivers/crypto/axis/artpec6_crypto.c
2541
writel_relaxed(in, base + A7_PDMA_IN_BUF_CFG);
drivers/crypto/axis/artpec6_crypto.c
2542
writel_relaxed(PDMA_IN_CFG_EN, base + A7_PDMA_IN_CFG);
drivers/crypto/axis/artpec6_crypto.c
2543
writel_relaxed(A7_PDMA_INTR_MASK_IN_DATA |
drivers/crypto/axis/artpec6_crypto.c
2557
writel_relaxed(A6_PDMA_IN_CMD_STOP, base + A6_PDMA_IN_CMD);
drivers/crypto/axis/artpec6_crypto.c
2558
writel_relaxed(0, base + A6_PDMA_IN_CFG);
drivers/crypto/axis/artpec6_crypto.c
2559
writel_relaxed(A6_PDMA_OUT_CMD_STOP, base + PDMA_OUT_CMD);
drivers/crypto/axis/artpec6_crypto.c
2561
writel_relaxed(A7_PDMA_IN_CMD_STOP, base + A7_PDMA_IN_CMD);
drivers/crypto/axis/artpec6_crypto.c
2562
writel_relaxed(0, base + A7_PDMA_IN_CFG);
drivers/crypto/axis/artpec6_crypto.c
2563
writel_relaxed(A7_PDMA_OUT_CMD_STOP, base + PDMA_OUT_CMD);
drivers/crypto/axis/artpec6_crypto.c
2566
writel_relaxed(0, base + PDMA_OUT_CFG);
drivers/crypto/axis/artpec6_crypto.c
2610
writel_relaxed(in_cmd_flush_stat, base + in_cmd_reg);
drivers/crypto/axis/artpec6_crypto.c
2612
writel_relaxed(ack, base + ack_intr_reg);
drivers/crypto/axis/artpec6_crypto.c
500
writel_relaxed(ind, base + A6_PDMA_IN_DESCRQ_PUSH);
drivers/crypto/axis/artpec6_crypto.c
501
writel_relaxed(statd, base + A6_PDMA_IN_STATQ_PUSH);
drivers/crypto/axis/artpec6_crypto.c
502
writel_relaxed(PDMA_IN_CMD_START, base + A6_PDMA_IN_CMD);
drivers/crypto/axis/artpec6_crypto.c
504
writel_relaxed(ind, base + A7_PDMA_IN_DESCRQ_PUSH);
drivers/crypto/axis/artpec6_crypto.c
505
writel_relaxed(statd, base + A7_PDMA_IN_STATQ_PUSH);
drivers/crypto/axis/artpec6_crypto.c
506
writel_relaxed(PDMA_IN_CMD_START, base + A7_PDMA_IN_CMD);
drivers/crypto/axis/artpec6_crypto.c
509
writel_relaxed(outd, base + PDMA_OUT_DESCRQ_PUSH);
drivers/crypto/axis/artpec6_crypto.c
510
writel_relaxed(PDMA_OUT_CMD_START, base + PDMA_OUT_CMD);
drivers/crypto/ccree/cc_request_mgr.c
198
writel_relaxed(seq[i].word[w], reg);
drivers/crypto/exynos-rng.c
94
writel_relaxed(val, rng->mem + offset);
drivers/crypto/hisilicon/hpre/hpre_main.c
518
writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG);
drivers/crypto/hisilicon/hpre/hpre_main.c
519
writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG);
drivers/crypto/hisilicon/hpre/hpre_main.c
726
writel_relaxed(HPRE_QM_AXI_CFG_MASK, qm->io_base + QM_AXI_M_CFG);
drivers/crypto/hisilicon/sec/sec_drv.c
262
writel_relaxed(regval, addr);
drivers/crypto/hisilicon/sec/sec_drv.c
274
writel_relaxed(regval, addr);
drivers/crypto/hisilicon/sec/sec_drv.c
284
writel_relaxed(0x7, base + SEC_ALGSUB_CLK_EN_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
301
writel_relaxed(0x7, base + SEC_ALGSUB_CLK_DIS_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
319
writel_relaxed(1, base + SEC_ALGSUB_RST_REQ_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
320
writel_relaxed(1, base + SEC_ALGSUB_BUILD_RST_REQ_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
337
writel_relaxed(1, base + SEC_ALGSUB_RST_DREQ_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
338
writel_relaxed(1, base + SEC_ALGSUB_BUILD_RST_DREQ_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
365
writel_relaxed(regval, addr);
drivers/crypto/hisilicon/sec/sec_drv.c
380
writel_relaxed(0x44cf9e, addr);
drivers/crypto/hisilicon/sec/sec_drv.c
382
writel_relaxed(0x4cfd9, addr);
drivers/crypto/hisilicon/sec/sec_drv.c
394
writel_relaxed(regval, addr);
drivers/crypto/hisilicon/sec/sec_drv.c
406
writel_relaxed(regval, addr);
drivers/crypto/hisilicon/sec/sec_drv.c
419
writel_relaxed(regval, addr);
drivers/crypto/hisilicon/sec/sec_drv.c
432
writel_relaxed(regval, addr);
drivers/crypto/hisilicon/sec/sec_drv.c
445
writel_relaxed(regval, addr);
drivers/crypto/hisilicon/sec/sec_drv.c
454
writel_relaxed(hash_mask[0],
drivers/crypto/hisilicon/sec/sec_drv.c
465
writel_relaxed(hash_mask,
drivers/crypto/hisilicon/sec/sec_drv.c
485
writel_relaxed(regval, addr);
drivers/crypto/hisilicon/sec/sec_drv.c
499
writel_relaxed(regval, addr);
drivers/crypto/hisilicon/sec/sec_drv.c
505
writel_relaxed(saa_int_mask,
drivers/crypto/hisilicon/sec/sec_drv.c
515
writel_relaxed((SEC_VMID | ((SEC_SID & 0xffff) << 8)),
drivers/crypto/hisilicon/sec/sec_drv.c
533
writel_relaxed(regval, addr);
drivers/crypto/hisilicon/sec/sec_drv.c
550
writel_relaxed(regval, addr);
drivers/crypto/hisilicon/sec/sec_drv.c
563
writel_relaxed(regval, base + SEC_Q_CFG_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
575
writel_relaxed(regval, addr);
drivers/crypto/hisilicon/sec/sec_drv.c
580
writel_relaxed(upper_32_bits(addr), queue->regs + SEC_Q_BASE_HADDR_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
581
writel_relaxed(lower_32_bits(addr), queue->regs + SEC_Q_BASE_LADDR_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
586
writel_relaxed(upper_32_bits(addr),
drivers/crypto/hisilicon/sec/sec_drv.c
588
writel_relaxed(lower_32_bits(addr),
drivers/crypto/hisilicon/sec/sec_drv.c
594
writel_relaxed(upper_32_bits(addr),
drivers/crypto/hisilicon/sec/sec_drv.c
596
writel_relaxed(lower_32_bits(addr),
drivers/crypto/hisilicon/sec/sec_drv.c
602
writel_relaxed((u32)~0, queue->regs + SEC_Q_FLOW_INT_MKS_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
607
writel_relaxed(0, queue->regs + SEC_Q_FLOW_INT_MKS_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
612
writel_relaxed((u32)~0, queue->regs + SEC_Q_FAIL_INT_MSK_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
619
writel_relaxed(0x0, queue->regs + SEC_QUEUE_ENB_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
627
writel_relaxed(SEC_Q_INIT_AND_STAT_CLEAR, queue->regs + SEC_Q_INIT_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
628
writel_relaxed(0x1, queue->regs + SEC_QUEUE_ENB_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
903
writel_relaxed(1, queue->regs + SEC_Q_PROC_NUM_CFG_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
913
writel_relaxed(0x100, queue->regs + SEC_Q_OT_TH_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
917
writel_relaxed(SEC_Q_INIT_AND_STAT_CLEAR, queue->regs + SEC_Q_INIT_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
940
writel_relaxed(GENMASK(info->num_saas - 1, 0),
drivers/crypto/hisilicon/sec/sec_drv.c
961
writel_relaxed((u32)~0, info->regs[SEC_SAA] + SEC_FSM_MAX_CNT_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
978
writel_relaxed(0x3f,
drivers/crypto/hisilicon/sec2/sec_main.c
487
writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
573
writel_relaxed(reg, qm->io_base +
drivers/crypto/hisilicon/sec2/sec_main.c
580
writel_relaxed(reg, qm->io_base +
drivers/crypto/hisilicon/sec2/sec_main.c
586
writel_relaxed(reg, qm->io_base +
drivers/crypto/hisilicon/sec2/sec_main.c
595
writel_relaxed(reg, qm->io_base +
drivers/crypto/hisilicon/sec2/sec_main.c
610
writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
628
writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
639
writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
651
writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
663
writel_relaxed(SEC_BD_ERR_CHK_EN0,
drivers/crypto/hisilicon/sec2/sec_main.c
667
writel_relaxed(SEC_BD_ERR_CHK_EN1,
drivers/crypto/hisilicon/sec2/sec_main.c
669
writel_relaxed(SEC_BD_ERR_CHK_EN3,
drivers/crypto/img-hash.c
157
writel_relaxed(value, hdev->io_base + offset);
drivers/crypto/img-hash.c
205
writel_relaxed(buffer[count], hdev->cpu_addr);
drivers/crypto/marvell/cesa/cesa.h
718
writel_relaxed(int_mask, engine->regs + CESA_SA_INT_MSK);
drivers/crypto/marvell/cesa/cipher.c
120
writel_relaxed(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG);
drivers/crypto/marvell/cesa/hash.c
184
writel_relaxed(creq->state[i],
drivers/crypto/marvell/cesa/hash.c
281
writel_relaxed(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG);
drivers/crypto/marvell/cesa/hash.c
326
writel_relaxed(creq->state[i], engine->regs +
drivers/crypto/marvell/cesa/tdma.c
50
writel_relaxed(0, engine->regs + CESA_SA_CFG);
drivers/crypto/marvell/cesa/tdma.c
53
writel_relaxed(CESA_TDMA_DST_BURST_128B | CESA_TDMA_SRC_BURST_128B |
drivers/crypto/marvell/cesa/tdma.c
57
writel_relaxed(CESA_SA_CFG_ACT_CH0_IDMA | CESA_SA_CFG_MULTI_PKT |
drivers/crypto/marvell/cesa/tdma.c
60
writel_relaxed(dreq->chain.first->cur_dma,
drivers/crypto/rockchip/rk3288_crypto.h
186
writel_relaxed((val), ((dev)->reg + (offset)))
drivers/crypto/sa2ul.c
2411
writel_relaxed(val, saul_base + SA_ENGINE_ENABLE_CONTROL);
drivers/crypto/stm32/stm32-cryp.c
301
writel_relaxed(val, cryp->regs + ofst);
drivers/crypto/stm32/stm32-cryp.c
314
writel_relaxed(readl_relaxed(cryp->regs + cryp->caps->cr) | CR_CRYPEN,
drivers/crypto/stm32/stm32-cryp.c
344
writel_relaxed(readl_relaxed(cryp->regs + cryp->caps->cr) | CR_KEYRDEN,
drivers/crypto/stm32/stm32-cryp.c
350
writel_relaxed(readl_relaxed(cryp->regs + cryp->caps->cr) & ~CR_KEYRDEN,
drivers/crypto/stm32/stm32-hash.c
237
writel_relaxed(value, hdev->io_base + offset);
drivers/crypto/ti/dthev2-aes.c
188
writel_relaxed(ctx->key[0], aes_base_reg + DTHE_P_AES_KEY1_0);
drivers/crypto/ti/dthev2-aes.c
189
writel_relaxed(ctx->key[1], aes_base_reg + DTHE_P_AES_KEY1_1);
drivers/crypto/ti/dthev2-aes.c
190
writel_relaxed(ctx->key[2], aes_base_reg + DTHE_P_AES_KEY1_2);
drivers/crypto/ti/dthev2-aes.c
191
writel_relaxed(ctx->key[3], aes_base_reg + DTHE_P_AES_KEY1_3);
drivers/crypto/ti/dthev2-aes.c
194
writel_relaxed(ctx->key[4], aes_base_reg + DTHE_P_AES_KEY1_4);
drivers/crypto/ti/dthev2-aes.c
195
writel_relaxed(ctx->key[5], aes_base_reg + DTHE_P_AES_KEY1_5);
drivers/crypto/ti/dthev2-aes.c
198
writel_relaxed(ctx->key[6], aes_base_reg + DTHE_P_AES_KEY1_6);
drivers/crypto/ti/dthev2-aes.c
199
writel_relaxed(ctx->key[7], aes_base_reg + DTHE_P_AES_KEY1_7);
drivers/crypto/ti/dthev2-aes.c
205
writel_relaxed(ctx->key[key2_offset + 0], aes_base_reg + DTHE_P_AES_KEY2_0);
drivers/crypto/ti/dthev2-aes.c
206
writel_relaxed(ctx->key[key2_offset + 1], aes_base_reg + DTHE_P_AES_KEY2_1);
drivers/crypto/ti/dthev2-aes.c
207
writel_relaxed(ctx->key[key2_offset + 2], aes_base_reg + DTHE_P_AES_KEY2_2);
drivers/crypto/ti/dthev2-aes.c
208
writel_relaxed(ctx->key[key2_offset + 3], aes_base_reg + DTHE_P_AES_KEY2_3);
drivers/crypto/ti/dthev2-aes.c
211
writel_relaxed(ctx->key[key2_offset + 4], aes_base_reg + DTHE_P_AES_KEY2_4);
drivers/crypto/ti/dthev2-aes.c
212
writel_relaxed(ctx->key[key2_offset + 5], aes_base_reg + DTHE_P_AES_KEY2_5);
drivers/crypto/ti/dthev2-aes.c
215
writel_relaxed(ctx->key[key2_offset + 6], aes_base_reg + DTHE_P_AES_KEY2_6);
drivers/crypto/ti/dthev2-aes.c
216
writel_relaxed(ctx->key[key2_offset + 7], aes_base_reg + DTHE_P_AES_KEY2_7);
drivers/crypto/ti/dthev2-aes.c
247
writel_relaxed(iv_in[i],
drivers/crypto/ti/dthev2-aes.c
251
writel_relaxed(ctrl_val, aes_base_reg + DTHE_P_AES_CTRL);
drivers/crypto/ti/dthev2-aes.c
293
writel_relaxed(aes_sysconfig_val, aes_base_reg + DTHE_P_AES_SYSCONFIG);
drivers/crypto/ti/dthev2-aes.c
296
writel_relaxed(aes_irqenable_val, aes_base_reg + DTHE_P_AES_IRQENABLE);
drivers/crypto/ti/dthev2-aes.c
356
writel_relaxed(lower_32_bits(req->cryptlen), aes_base_reg + DTHE_P_AES_C_LENGTH_0);
drivers/crypto/ti/dthev2-aes.c
357
writel_relaxed(upper_32_bits(req->cryptlen), aes_base_reg + DTHE_P_AES_C_LENGTH_1);
drivers/devfreq/event/rockchip-dfi.c
197
writel_relaxed(FIELD_PREP_WM16(DDRMON_CTRL_TIMER_CNT_EN, 0) |
drivers/devfreq/event/rockchip-dfi.c
202
writel_relaxed(ctrl, dfi_regs + i * dfi->ddrmon_stride +
drivers/devfreq/event/rockchip-dfi.c
206
writel_relaxed(FIELD_PREP_WM16(DDRMON_CTRL_SOFTWARE_EN, 1),
drivers/devfreq/event/rockchip-dfi.c
236
writel_relaxed(FIELD_PREP_WM16(DDRMON_CTRL_SOFTWARE_EN, 0),
drivers/devfreq/sun8i-a33-mbus.c
116
writel_relaxed(pmu_cfg,
drivers/devfreq/sun8i-a33-mbus.c
118
writel_relaxed(pmu_cfg | MBUS_PMU_CFG_ENABLE,
drivers/devfreq/sun8i-a33-mbus.c
154
writel_relaxed(pwrctl, priv->reg_dram + DRAM_PWRCTL);
drivers/devfreq/sun8i-a33-mbus.c
156
writel_relaxed(vtfcr & ~DRAM_VTFCR_VTF_ENABLE,
drivers/devfreq/sun8i-a33-mbus.c
202
writel_relaxed(vtfcr, priv->reg_dram + DRAM_VTFCR);
drivers/devfreq/sun8i-a33-mbus.c
207
writel_relaxed(pwrctl, priv->reg_dram + DRAM_PWRCTL);
drivers/devfreq/sun8i-a33-mbus.c
303
writel_relaxed(MBUS_TMR_PERIOD(mbus_freq_mhz),
drivers/devfreq/sun8i-a33-mbus.c
307
writel_relaxed(0xffffffff, priv->reg_mbus + MBUS_MDFSMRMR);
drivers/devfreq/tegra30-devfreq.c
225
writel_relaxed(val, tegra->regs + offset);
drivers/devfreq/tegra30-devfreq.c
236
writel_relaxed(val, dev->regs + offset);
drivers/dma/amba-pl08x.c
408
writel_relaxed(lli[PL080_LLI_SRC], phychan->reg_src);
drivers/dma/amba-pl08x.c
409
writel_relaxed(lli[PL080_LLI_DST], phychan->reg_dst);
drivers/dma/amba-pl08x.c
410
writel_relaxed(lli[PL080_LLI_LLI], phychan->reg_lli);
drivers/dma/amba-pl08x.c
423
writel_relaxed(llictl & FTDMAC020_LLI_TRANSFER_SIZE_MASK,
drivers/dma/amba-pl08x.c
507
writel_relaxed(val, phychan->reg_control);
drivers/dma/amba-pl08x.c
510
writel_relaxed(lli[PL080_LLI_CCTL], phychan->reg_control);
drivers/dma/amba-pl08x.c
515
writel_relaxed(lli[PL080S_LLI_CCTL2],
drivers/dma/apple-admac.c
211
writel_relaxed((curr & ~mask) | (val & mask), addr);
drivers/dma/apple-admac.c
300
writel_relaxed(lower_32_bits(addr), ad->base + REG_DESC_WRITE(channo));
drivers/dma/apple-admac.c
301
writel_relaxed(upper_32_bits(addr), ad->base + REG_DESC_WRITE(channo));
drivers/dma/apple-admac.c
302
writel_relaxed(tx->period_len, ad->base + REG_DESC_WRITE(channo));
drivers/dma/apple-admac.c
303
writel_relaxed(FLAG_DESC_NOTIFY, ad->base + REG_DESC_WRITE(channo));
drivers/dma/apple-admac.c
416
writel_relaxed(STATUS_DESC_DONE | STATUS_ERR,
drivers/dma/apple-admac.c
418
writel_relaxed(STATUS_DESC_DONE | STATUS_ERR,
drivers/dma/apple-admac.c
423
writel_relaxed(startbit, ad->base + REG_TX_START);
drivers/dma/apple-admac.c
426
writel_relaxed(startbit, ad->base + REG_RX_START);
drivers/dma/apple-admac.c
441
writel_relaxed(stopbit, ad->base + REG_TX_STOP);
drivers/dma/apple-admac.c
444
writel_relaxed(stopbit, ad->base + REG_RX_STOP);
drivers/dma/apple-admac.c
456
writel_relaxed(REG_CHAN_CTL_RST_RINGS,
drivers/dma/apple-admac.c
458
writel_relaxed(0, ad->base + REG_CHAN_CTL(adchan->no));
drivers/dma/apple-admac.c
467
writel_relaxed(0, ad->base + REG_CHAN_CTL(ch));
drivers/dma/apple-admac.c
566
writel_relaxed(adchan->carveout,
drivers/dma/apple-admac.c
627
writel_relaxed(RING_ERR, ad->base + REG_DESC_RING(channo));
drivers/dma/apple-admac.c
633
writel_relaxed(RING_ERR, ad->base + REG_REPORT_RING(channo));
drivers/dma/apple-admac.c
651
writel_relaxed(STATUS_DESC_DONE,
drivers/dma/apple-admac.c
709
writel_relaxed(~(u32) 0, ad->base + REG_GLOBAL_INTSTATE(ad->irq_index));
drivers/dma/apple-admac.c
787
writel_relaxed(bus_width, ad->base + REG_BUS_WIDTH(adchan->no));
drivers/dma/apple-admac.c
796
writel_relaxed(FIELD_PREP(CHAN_FIFOCTL_LIMIT, 0x30 * wordsize)
drivers/dma/arm-dma350.c
296
writel_relaxed(CH_CMD_PAUSE, dch->base + CH_CMD);
drivers/dma/arm-dma350.c
311
writel_relaxed(CH_CMD_RESUME, dch->base + CH_CMD);
drivers/dma/arm-dma350.c
344
writel_relaxed(CH_CMD_STOP, dch->base + CH_CMD);
drivers/dma/arm-dma350.c
416
writel_relaxed(*reg++, dch->base + CH_INTREN);
drivers/dma/arm-dma350.c
418
writel_relaxed(*reg++, dch->base + CH_CTRL);
drivers/dma/arm-dma350.c
420
writel_relaxed(*reg++, dch->base + CH_SRCADDR);
drivers/dma/arm-dma350.c
422
writel_relaxed(*reg++, dch->base + CH_SRCADDRHI);
drivers/dma/arm-dma350.c
424
writel_relaxed(*reg++, dch->base + CH_DESADDR);
drivers/dma/arm-dma350.c
426
writel_relaxed(*reg++, dch->base + CH_DESADDRHI);
drivers/dma/arm-dma350.c
428
writel_relaxed(*reg++, dch->base + CH_XSIZE);
drivers/dma/arm-dma350.c
430
writel_relaxed(*reg++, dch->base + CH_XSIZEHI);
drivers/dma/arm-dma350.c
432
writel_relaxed(*reg++, dch->base + CH_SRCTRANSCFG);
drivers/dma/arm-dma350.c
434
writel_relaxed(*reg++, dch->base + CH_DESTRANSCFG);
drivers/dma/arm-dma350.c
436
writel_relaxed(*reg++, dch->base + CH_XADDRINC);
drivers/dma/arm-dma350.c
438
writel_relaxed(*reg++, dch->base + CH_FILLVAL);
drivers/dma/arm-dma350.c
440
writel_relaxed(*reg++, dch->base + CH_SRCTRIGINCFG);
drivers/dma/arm-dma350.c
442
writel_relaxed(*reg++, dch->base + CH_DESTRIGINCFG);
drivers/dma/arm-dma350.c
444
writel_relaxed(*reg++, dch->base + CH_AUTOCFG);
drivers/dma/arm-dma350.c
446
writel_relaxed(*reg++, dch->base + CH_LINKADDR);
drivers/dma/arm-dma350.c
448
writel_relaxed(*reg++, dch->base + CH_LINKADDRHI);
drivers/dma/arm-dma350.c
489
writel_relaxed(ch_status, dch->base + CH_STATUS);
drivers/dma/arm-dma350.c
512
writel_relaxed(CH_INTREN_DONE | CH_INTREN_ERR, dch->base + CH_INTREN);
drivers/dma/arm-dma350.c
521
writel_relaxed(0, dch->base + CH_INTREN);
drivers/dma/arm-dma350.c
591
writel_relaxed(CH_CMD_CLEAR, dch->base + CH_CMD);
drivers/dma/arm-dma350.c
615
writel_relaxed(reg, dch->base + CH_LINKATTR);
drivers/dma/at_xdmac.c
317
writel_relaxed((value), (atxdmac)->regs + (reg))
drivers/dma/at_xdmac.c
320
#define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg))
drivers/dma/hisi_dma.c
333
writel_relaxed(val, base + reg + index * HISI_DMA_Q_OFFSET);
drivers/dma/hisi_dma.c
342
writel_relaxed(tmp, addr);
drivers/dma/hisi_dma.c
677
writel_relaxed(tmp, addr);
drivers/dma/hisi_dma.c
804
writel_relaxed(mode == RC ? 1 : 0,
drivers/dma/imx-sdma.c
1181
writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
drivers/dma/imx-sdma.c
1379
writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
drivers/dma/imx-sdma.c
2133
writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
drivers/dma/imx-sdma.c
2156
writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
drivers/dma/imx-sdma.c
2160
writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
drivers/dma/imx-sdma.c
2169
writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
drivers/dma/imx-sdma.c
2173
writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG);
drivers/dma/imx-sdma.c
2175
writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
drivers/dma/imx-sdma.c
2177
writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
drivers/dma/imx-sdma.c
728
writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
drivers/dma/imx-sdma.c
729
writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
drivers/dma/imx-sdma.c
730
writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
drivers/dma/imx-sdma.c
764
writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG);
drivers/dma/imx-sdma.c
811
writel_relaxed(val, sdma->regs + chnenbl);
drivers/dma/imx-sdma.c
818
writel_relaxed(val, sdma->regs + SDMA_DONE0_CONFIG);
drivers/dma/imx-sdma.c
831
writel_relaxed(val, sdma->regs + chnenbl);
drivers/dma/imx-sdma.c
951
writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
drivers/dma/k3dma.c
140
writel_relaxed(val, phy->base + CX_CFG);
drivers/dma/k3dma.c
144
writel_relaxed(val, phy->base + CX_CFG);
drivers/dma/k3dma.c
155
writel_relaxed(val, d->base + INT_TC1_RAW);
drivers/dma/k3dma.c
156
writel_relaxed(val, d->base + INT_TC2_RAW);
drivers/dma/k3dma.c
157
writel_relaxed(val, d->base + INT_ERR1_RAW);
drivers/dma/k3dma.c
158
writel_relaxed(val, d->base + INT_ERR2_RAW);
drivers/dma/k3dma.c
163
writel_relaxed(hw->lli, phy->base + CX_LLI);
drivers/dma/k3dma.c
164
writel_relaxed(hw->count, phy->base + CX_CNT0);
drivers/dma/k3dma.c
165
writel_relaxed(hw->saddr, phy->base + CX_SRC);
drivers/dma/k3dma.c
166
writel_relaxed(hw->daddr, phy->base + CX_DST);
drivers/dma/k3dma.c
167
writel_relaxed(hw->config, phy->base + CX_CFG);
drivers/dma/k3dma.c
193
writel_relaxed(0x0, d->base + CH_PRI);
drivers/dma/k3dma.c
196
writel_relaxed(0xffff, d->base + INT_TC1_MASK);
drivers/dma/k3dma.c
197
writel_relaxed(0xffff, d->base + INT_TC2_MASK);
drivers/dma/k3dma.c
198
writel_relaxed(0xffff, d->base + INT_ERR1_MASK);
drivers/dma/k3dma.c
199
writel_relaxed(0xffff, d->base + INT_ERR2_MASK);
drivers/dma/k3dma.c
202
writel_relaxed(0x0, d->base + INT_TC1_MASK);
drivers/dma/k3dma.c
203
writel_relaxed(0x0, d->base + INT_TC2_MASK);
drivers/dma/k3dma.c
204
writel_relaxed(0x0, d->base + INT_ERR1_MASK);
drivers/dma/k3dma.c
205
writel_relaxed(0x0, d->base + INT_ERR2_MASK);
drivers/dma/k3dma.c
249
writel_relaxed(irq_chan, d->base + INT_TC1_RAW);
drivers/dma/k3dma.c
250
writel_relaxed(irq_chan, d->base + INT_TC2_RAW);
drivers/dma/k3dma.c
251
writel_relaxed(err1, d->base + INT_ERR1_RAW);
drivers/dma/k3dma.c
252
writel_relaxed(err2, d->base + INT_ERR2_RAW);
drivers/dma/mediatek/mtk-cqdma.c
175
writel_relaxed(val, pc->base + reg);
drivers/dma/milbeaut-hdmac.c
142
writel_relaxed(MLB_HDMAC_DE, mc->mdev->reg_base + MLB_HDMAC_DMACR);
drivers/dma/milbeaut-hdmac.c
143
writel_relaxed(src_addr, mc->reg_ch_base + MLB_HDMAC_DMACSA);
drivers/dma/milbeaut-hdmac.c
144
writel_relaxed(dest_addr, mc->reg_ch_base + MLB_HDMAC_DMACDA);
drivers/dma/milbeaut-hdmac.c
145
writel_relaxed(cb, mc->reg_ch_base + MLB_HDMAC_DMACB);
drivers/dma/milbeaut-hdmac.c
156
writel_relaxed(ca, mc->reg_ch_base + MLB_HDMAC_DMACA);
drivers/dma/milbeaut-hdmac.c
158
writel_relaxed(ca, mc->reg_ch_base + MLB_HDMAC_DMACA);
drivers/dma/milbeaut-hdmac.c
182
writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACB);
drivers/dma/milbeaut-hdmac.c
185
writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACB);
drivers/dma/milbeaut-hdmac.c
234
writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACA);
drivers/dma/milbeaut-hdmac.c
249
writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACA);
drivers/dma/milbeaut-hdmac.c
300
writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACA);
drivers/dma/milbeaut-xdmac.c
119
writel_relaxed(val, mc->reg_ch_base + M10V_XDTBC);
drivers/dma/milbeaut-xdmac.c
122
writel_relaxed(val, mc->reg_ch_base + M10V_XDSSA);
drivers/dma/milbeaut-xdmac.c
125
writel_relaxed(val, mc->reg_ch_base + M10V_XDDSA);
drivers/dma/milbeaut-xdmac.c
131
writel_relaxed(val, mc->reg_ch_base + M10V_XDSAC);
drivers/dma/milbeaut-xdmac.c
137
writel_relaxed(val, mc->reg_ch_base + M10V_XDDAC);
drivers/dma/milbeaut-xdmac.c
146
writel_relaxed(val, mc->reg_ch_base + M10V_XDDES);
drivers/dma/milbeaut-xdmac.c
169
writel_relaxed(val, mc->reg_ch_base + M10V_XDDSD);
drivers/dma/mv_xor.c
106
writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan));
drivers/dma/mv_xor.c
113
writel_relaxed(val, XOR_INTR_MASK(chan));
drivers/dma/mv_xor.c
1280
writel_relaxed(mv_chan->saved_config_reg,
drivers/dma/mv_xor.c
1282
writel_relaxed(mv_chan->saved_int_mask_reg,
drivers/dma/mv_xor.c
130
writel_relaxed(val, XOR_INTR_CAUSE(chan));
drivers/dma/mv_xor.c
136
writel_relaxed(val, XOR_INTR_CAUSE(chan));
drivers/dma/mv_xor.c
153
writel_relaxed(config, XOR_CONFIG(chan));
drivers/dma/pxa_dma.c
166
writel_relaxed((val), (phy)->base + _reg((phy)->idx)); \
drivers/dma/pxa_dma.c
420
writel_relaxed(0, chan->phy->base + reg);
drivers/dma/pxa_dma.c
464
writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg);
drivers/dma/qcom/bam_dma.c
1086
writel_relaxed(bchan->tail * sizeof(struct bam_desc_hw),
drivers/dma/qcom/bam_dma.c
1380
writel_relaxed(0, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
drivers/dma/qcom/bam_dma.c
433
writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
drivers/dma/qcom/bam_dma.c
435
writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
drivers/dma/qcom/bam_dma.c
442
writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
drivers/dma/qcom/bam_dma.c
445
writel_relaxed(DEFAULT_CNT_THRSHLD,
drivers/dma/qcom/bam_dma.c
449
writel_relaxed(BAM_CNFG_BITS_DEFAULT, bam_addr(bdev, 0, BAM_CNFG_BITS));
drivers/dma/qcom/bam_dma.c
452
writel_relaxed(BAM_ERROR_EN | BAM_HRESP_ERR_EN,
drivers/dma/qcom/bam_dma.c
456
writel_relaxed(BAM_IRQ_MSK, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
drivers/dma/qcom/bam_dma.c
472
writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_RST));
drivers/dma/qcom/bam_dma.c
473
writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_RST));
drivers/dma/qcom/bam_dma.c
502
writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)),
drivers/dma/qcom/bam_dma.c
504
writel_relaxed(BAM_FIFO_SIZE,
drivers/dma/qcom/bam_dma.c
508
writel_relaxed(P_DEFAULT_IRQS_EN,
drivers/dma/qcom/bam_dma.c
514
writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
drivers/dma/qcom/bam_dma.c
524
writel_relaxed(val, bam_addr(bdev, bchan->id, BAM_P_CTRL));
drivers/dma/qcom/bam_dma.c
597
writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
drivers/dma/qcom/bam_dma.c
600
writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_IRQ_EN));
drivers/dma/qcom/bam_dma.c
606
writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
drivers/dma/qcom/bam_dma.c
774
writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_HALT));
drivers/dma/qcom/bam_dma.c
799
writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_HALT));
drivers/dma/qcom/bam_dma.c
835
writel_relaxed(pipe_stts, bam_addr(bdev, i, BAM_P_IRQ_CLR));
drivers/dma/qcom/bam_dma.c
913
writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR));
drivers/dma/qcom/bam_dma.c
988
writel_relaxed(maxburst,
drivers/dma/qcom/gpi.c
569
writel_relaxed(val, addr);
drivers/dma/qcom/hidma_ll.c
408
writel_relaxed(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
drivers/dma/qcom/qcom_adm.c
484
writel_relaxed(0x0,
drivers/dma/sa11x0-dma.c
1058
writel_relaxed(txd->ddar, p->base + DMA_DDAR);
drivers/dma/sa11x0-dma.c
1060
writel_relaxed(p->dbs[0], p->base + DMA_DBSA);
drivers/dma/sa11x0-dma.c
1061
writel_relaxed(p->dbt[0], p->base + DMA_DBTA);
drivers/dma/sa11x0-dma.c
1062
writel_relaxed(p->dbs[1], p->base + DMA_DBSB);
drivers/dma/sa11x0-dma.c
1063
writel_relaxed(p->dbt[1], p->base + DMA_DBTB);
drivers/dma/sa11x0-dma.c
1064
writel_relaxed(p->dcsr, p->base + DMA_DCSR_S);
drivers/dma/sa11x0-dma.c
212
writel_relaxed(sg->addr, base + dbsx);
drivers/dma/sa11x0-dma.c
213
writel_relaxed(sg->len, base + dbtx);
drivers/dma/sa11x0-dma.c
260
writel_relaxed(dcsr & (DCSR_ERROR | DCSR_DONEA | DCSR_DONEB),
drivers/dma/sa11x0-dma.c
316
writel_relaxed(DCSR_RUN | DCSR_STRTA | DCSR_STRTB,
drivers/dma/sa11x0-dma.c
318
writel_relaxed(txd->ddar, p->base + DMA_DDAR);
drivers/dma/sa11x0-dma.c
937
writel_relaxed(DCSR_RUN | DCSR_IE | DCSR_ERROR |
drivers/dma/sa11x0-dma.c
940
writel_relaxed(0, p->base + DMA_DDAR);
drivers/dma/ste_dma40.c
2958
writel_relaxed(backup[i], addr);
drivers/dma/ste_dma40.c
3004
writel_relaxed(base->gcc_pwr_off_mask,
drivers/dma/ste_dma40.c
3016
writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
drivers/dma/ste_dma40.c
3612
writel_relaxed(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
drivers/dma/ste_dma40_ll.c
343
writel_relaxed(lli_src->lcsp02, &lcpa[0].lcsp0);
drivers/dma/ste_dma40_ll.c
344
writel_relaxed(lli_src->lcsp13, &lcpa[0].lcsp1);
drivers/dma/ste_dma40_ll.c
345
writel_relaxed(lli_dst->lcsp02, &lcpa[0].lcsp2);
drivers/dma/ste_dma40_ll.c
346
writel_relaxed(lli_dst->lcsp13, &lcpa[0].lcsp3);
drivers/dma/ste_dma40_ll.c
356
writel_relaxed(lli_src->lcsp02, &lcla[0].lcsp02);
drivers/dma/ste_dma40_ll.c
357
writel_relaxed(lli_src->lcsp13, &lcla[0].lcsp13);
drivers/dma/ste_dma40_ll.c
358
writel_relaxed(lli_dst->lcsp02, &lcla[1].lcsp02);
drivers/dma/ste_dma40_ll.c
359
writel_relaxed(lli_dst->lcsp13, &lcla[1].lcsp13);
drivers/dma/stm32/stm32-dma.c
263
writel_relaxed(val, dmadev->base + reg);
drivers/dma/stm32/stm32-dma3.c
1065
writel_relaxed(csr, ddata->base + STM32_DMA3_CFCR(chan->id));
drivers/dma/stm32/stm32-dma3.c
1080
writel_relaxed(CSEMCR_SEM_MUTEX, ddata->base + STM32_DMA3_CSEMCR(chan->id));
drivers/dma/stm32/stm32-dma3.c
1106
writel_relaxed(0, ddata->base + STM32_DMA3_CSEMCR(chan->id));
drivers/dma/stm32/stm32-dma3.c
432
writel_relaxed(swdesc->lli[0].hwdesc_addr & CLBAR_LBA,
drivers/dma/stm32/stm32-dma3.c
790
writel_relaxed(chan->swdesc->ccr, ddata->base + STM32_DMA3_CCR(id));
drivers/dma/stm32/stm32-dma3.c
791
writel_relaxed(hwdesc->ctr1, ddata->base + STM32_DMA3_CTR1(id));
drivers/dma/stm32/stm32-dma3.c
792
writel_relaxed(hwdesc->ctr2, ddata->base + STM32_DMA3_CTR2(id));
drivers/dma/stm32/stm32-dma3.c
793
writel_relaxed(hwdesc->cbr1, ddata->base + STM32_DMA3_CBR1(id));
drivers/dma/stm32/stm32-dma3.c
794
writel_relaxed(hwdesc->csar, ddata->base + STM32_DMA3_CSAR(id));
drivers/dma/stm32/stm32-dma3.c
795
writel_relaxed(hwdesc->cdar, ddata->base + STM32_DMA3_CDAR(id));
drivers/dma/stm32/stm32-dma3.c
796
writel_relaxed(hwdesc->cllr, ddata->base + STM32_DMA3_CLLR(id));
drivers/dma/stm32/stm32-dma3.c
801
writel_relaxed(csr, ddata->base + STM32_DMA3_CFCR(id));
drivers/dma/stm32/stm32-dma3.c
806
writel_relaxed(ccr | CCR_EN, ddata->base + STM32_DMA3_CCR(id));
drivers/dma/stm32/stm32-dma3.c
824
writel_relaxed(ccr, ddata->base + STM32_DMA3_CCR(chan->id));
drivers/dma/stm32/stm32-dma3.c
830
writel_relaxed(CFCR_SUSPF, ddata->base + STM32_DMA3_CFCR(chan->id));
drivers/dma/stm32/stm32-dma3.c
843
writel_relaxed(ccr |= CCR_RESET, ddata->base + STM32_DMA3_CCR(chan->id));
drivers/dma/stm32/stm32-dma3.c
883
writel_relaxed(swdesc->ccr | CCR_SUSP, ddata->base + STM32_DMA3_CCR(chan->id));
drivers/dma/stm32/stm32-dma3.c
888
writel_relaxed(CFCR_SUSPF, ddata->base + STM32_DMA3_CFCR(chan->id));
drivers/dma/stm32/stm32-dma3.c
889
writel_relaxed(swdesc->ccr, ddata->base + STM32_DMA3_CCR(chan->id));
drivers/dma/stm32/stm32-dma3.c
913
writel_relaxed(CFCR_SUSPF, ddata->base + STM32_DMA3_CFCR(chan->id));
drivers/dma/stm32/stm32-dma3.c
914
writel_relaxed(swdesc->ccr, ddata->base + STM32_DMA3_CCR(chan->id));
drivers/dma/stm32/stm32-dma3.c
984
writel_relaxed(ccr & ~(CCR_ALLIE | CCR_EN), ddata->base + STM32_DMA3_CCR(chan->id));
drivers/dma/stm32/stm32-dmamux.c
61
writel_relaxed(val, iomem + reg);
drivers/dma/stm32/stm32-mdma.c
296
writel_relaxed(val, dmadev->base + reg);
drivers/dma/stm32/stm32-mdma.c
304
writel_relaxed(readl_relaxed(addr) | mask, addr);
drivers/dma/stm32/stm32-mdma.c
312
writel_relaxed(readl_relaxed(addr) & ~mask, addr);
drivers/dma/sun4i-dma.c
1195
writel_relaxed(irqs & ~disableirqs,
drivers/dma/sun4i-dma.c
1200
writel_relaxed(pendirq, priv->base + SUN4I_DMA_IRQ_PENDING_STATUS_REG);
drivers/dma/sun4i-dma.c
361
writel_relaxed(d->src, pchan->base + SUN4I_DDMA_SRC_ADDR_REG);
drivers/dma/sun4i-dma.c
362
writel_relaxed(d->dst, pchan->base + SUN4I_DDMA_DST_ADDR_REG);
drivers/dma/sun4i-dma.c
363
writel_relaxed(d->len, pchan->base + SUN4I_DDMA_BYTE_COUNT_REG);
drivers/dma/sun4i-dma.c
364
writel_relaxed(d->para, pchan->base + SUN4I_DDMA_PARA_REG);
drivers/dma/sun4i-dma.c
365
writel_relaxed(d->cfg, pchan->base + SUN4I_DDMA_CFG_REG);
drivers/dma/sun4i-dma.c
367
writel_relaxed(d->src, pchan->base + SUN4I_NDMA_SRC_ADDR_REG);
drivers/dma/sun4i-dma.c
368
writel_relaxed(d->dst, pchan->base + SUN4I_NDMA_DST_ADDR_REG);
drivers/dma/sun4i-dma.c
369
writel_relaxed(d->len, pchan->base + SUN4I_NDMA_BYTE_COUNT_REG);
drivers/dma/sun4i-dma.c
370
writel_relaxed(d->cfg, pchan->base + SUN4I_NDMA_CFG_REG);
drivers/dma/sun4i-dma.c
396
writel_relaxed(reg, priv->base + SUN4I_DMA_IRQ_ENABLE_REG);
drivers/dma/tegra186-gpc-dma.c
264
writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
drivers/dma/ti/omap-dma.c
321
writel_relaxed(val, addr);
drivers/edac/al_mc_edac.c
139
writel_relaxed(AL_MC_ECC_CLEAR_UE_COUNT | AL_MC_ECC_CLEAR_UE_ERR,
drivers/edac/al_mc_edac.c
94
writel_relaxed(AL_MC_ECC_CLEAR_CE_COUNT | AL_MC_ECC_CLEAR_CE_ERR,
drivers/edac/ti_edac.c
89
writel_relaxed(val, edac->reg + offset);
drivers/fsi/fsi-master-aspeed.c
108
writel_relaxed(CMD_WRITE, base + OPB0_RW);
drivers/fsi/fsi-master-aspeed.c
109
writel_relaxed(transfer_size, base + OPB0_XFER_SIZE);
drivers/fsi/fsi-master-aspeed.c
110
writel_relaxed(addr, base + OPB0_FSI_ADDR);
drivers/fsi/fsi-master-aspeed.c
111
writel_relaxed(val, base + OPB0_FSI_DATA_W);
drivers/fsi/fsi-master-aspeed.c
112
writel_relaxed(0x1, base + OPB_IRQ_CLEAR);
drivers/fsi/fsi-master-aspeed.c
160
writel_relaxed(CMD_READ, base + OPB0_RW);
drivers/fsi/fsi-master-aspeed.c
161
writel_relaxed(transfer_size, base + OPB0_XFER_SIZE);
drivers/fsi/fsi-master-aspeed.c
162
writel_relaxed(addr, base + OPB0_FSI_ADDR);
drivers/fsi/fsi-master-aspeed.c
163
writel_relaxed(0x1, base + OPB_IRQ_CLEAR);
drivers/gpio/gpio-amd-fch.c
113
writel_relaxed(mask, ptr);
drivers/gpio/gpio-amd-fch.c
56
writel_relaxed(readl_relaxed(ptr) & ~AMD_FCH_GPIO_FLAG_DIRECTION, ptr);
drivers/gpio/gpio-amd-fch.c
78
writel_relaxed(val | AMD_FCH_GPIO_FLAG_DIRECTION, ptr);
drivers/gpio/gpio-blzp1600.c
61
writel_relaxed(val, chip->base + offset);
drivers/gpio/gpio-blzp1600.c
73
writel_relaxed(val, reg);
drivers/gpio/gpio-davinci.c
159
writel_relaxed(__gpio_mask(offset),
drivers/gpio/gpio-davinci.c
272
writel_relaxed(mask, &g->clr_falling);
drivers/gpio/gpio-davinci.c
273
writel_relaxed(mask, &g->clr_rising);
drivers/gpio/gpio-davinci.c
293
writel_relaxed(mask, &g->set_falling);
drivers/gpio/gpio-davinci.c
295
writel_relaxed(mask, &g->set_rising);
drivers/gpio/gpio-davinci.c
343
writel_relaxed(status, &g->intstat);
drivers/gpio/gpio-davinci.c
406
writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
drivers/gpio/gpio-davinci.c
408
writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
drivers/gpio/gpio-davinci.c
535
writel_relaxed(~0, &g->set_falling);
drivers/gpio/gpio-davinci.c
536
writel_relaxed(~0, &g->set_rising);
drivers/gpio/gpio-davinci.c
559
writel_relaxed(~0, &g->clr_falling);
drivers/gpio/gpio-davinci.c
560
writel_relaxed(~0, &g->clr_rising);
drivers/gpio/gpio-davinci.c
589
writel_relaxed(binten, gpio_base + BINTEN);
drivers/gpio/gpio-davinci.c
615
writel_relaxed(GENMASK(31, 0), &g->intstat);
drivers/gpio/gpio-davinci.c
629
writel_relaxed(chips->binten_context, base + BINTEN);
drivers/gpio/gpio-davinci.c
635
writel_relaxed(context->dir, &g->dir);
drivers/gpio/gpio-davinci.c
637
writel_relaxed(context->set_data, &g->set_data);
drivers/gpio/gpio-davinci.c
639
writel_relaxed(context->set_rising, &g->set_rising);
drivers/gpio/gpio-davinci.c
641
writel_relaxed(context->set_falling, &g->set_falling);
drivers/gpio/gpio-davinci.c
92
writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
drivers/gpio/gpio-davinci.c
96
writel_relaxed(temp, &g->dir);
drivers/gpio/gpio-eic-sprd.c
160
writel_relaxed(tmp, base + reg);
drivers/gpio/gpio-eic-sprd.c
222
writel_relaxed(value, base + reg);
drivers/gpio/gpio-lpc18xx.c
65
writel_relaxed(val, ic->base + LPC18XX_GPIO_PIN_IC_ISEL);
drivers/gpio/gpio-lpc18xx.c
71
writel_relaxed(BIT(pin), ic->base + reg);
drivers/gpio/gpio-omap.c
1015
writel_relaxed(l, bank->base + bank->regs->irqenable);
drivers/gpio/gpio-omap.c
1024
writel_relaxed(0, base + bank->regs->debounce_en);
drivers/gpio/gpio-omap.c
1030
writel_relaxed(0, base + bank->regs->ctrl);
drivers/gpio/gpio-omap.c
104
writel_relaxed(val, reg);
drivers/gpio/gpio-omap.c
1121
writel_relaxed(bank->context.sysconfig, base + regs->sysconfig);
drivers/gpio/gpio-omap.c
1122
writel_relaxed(bank->context.wake_en, base + regs->wkup_en);
drivers/gpio/gpio-omap.c
1123
writel_relaxed(bank->context.ctrl, base + regs->ctrl);
drivers/gpio/gpio-omap.c
1124
writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0);
drivers/gpio/gpio-omap.c
1125
writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1);
drivers/gpio/gpio-omap.c
1126
writel_relaxed(bank->context.risingdetect, base + regs->risingdetect);
drivers/gpio/gpio-omap.c
1127
writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect);
drivers/gpio/gpio-omap.c
1128
writel_relaxed(bank->context.dataout, base + regs->dataout);
drivers/gpio/gpio-omap.c
1129
writel_relaxed(bank->context.oe, base + regs->direction);
drivers/gpio/gpio-omap.c
1132
writel_relaxed(bank->context.debounce, base + regs->debounce);
drivers/gpio/gpio-omap.c
1133
writel_relaxed(bank->context.debounce_en,
drivers/gpio/gpio-omap.c
1137
writel_relaxed(bank->context.irqenable1, base + regs->irqenable);
drivers/gpio/gpio-omap.c
1138
writel_relaxed(bank->context.irqenable2, base + regs->irqenable2);
drivers/gpio/gpio-omap.c
1222
writel_relaxed(bank->context.fallingdetect,
drivers/gpio/gpio-omap.c
1224
writel_relaxed(bank->context.risingdetect,
drivers/gpio/gpio-omap.c
1262
writel_relaxed(old0 | gen, bank->base +
drivers/gpio/gpio-omap.c
1264
writel_relaxed(old1 | gen, bank->base +
drivers/gpio/gpio-omap.c
1269
writel_relaxed(old0 | l, bank->base +
drivers/gpio/gpio-omap.c
1271
writel_relaxed(old1 | l, bank->base +
drivers/gpio/gpio-omap.c
1274
writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
drivers/gpio/gpio-omap.c
1275
writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
drivers/gpio/gpio-omap.c
132
writel_relaxed(l, reg);
drivers/gpio/gpio-omap.c
149
writel_relaxed(bank->dbck_enable_mask,
drivers/gpio/gpio-omap.c
162
writel_relaxed(0, bank->base + bank->regs->debounce_en);
drivers/gpio/gpio-omap.c
200
writel_relaxed(debounce, bank->base + bank->regs->debounce);
drivers/gpio/gpio-omap.c
245
writel_relaxed(bank->context.debounce_en,
drivers/gpio/gpio-omap.c
250
writel_relaxed(bank->context.debounce, bank->base +
drivers/gpio/gpio-omap.c
330
writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg);
drivers/gpio/gpio-omap.c
355
writel_relaxed(l, reg);
drivers/gpio/gpio-omap.c
369
writel_relaxed(l, reg);
drivers/gpio/gpio-omap.c
380
writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
drivers/gpio/gpio-omap.c
390
writel_relaxed(ctrl, reg);
drivers/gpio/gpio-omap.c
404
writel_relaxed(ctrl, reg);
drivers/gpio/gpio-omap.c
475
writel_relaxed(gpio_mask, reg);
drivers/gpio/gpio-omap.c
480
writel_relaxed(gpio_mask, reg);
drivers/gpio/gpio-omap.c
521
writel_relaxed(gpio_mask, reg);
drivers/gpio/gpio-omap.c
758
writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
drivers/gpio/gpio-omap.c
772
writel_relaxed(bank->context.wake_en, mask_reg);
drivers/gpio/gpio-omap.c
982
writel_relaxed(l, reg);
drivers/gpio/gpio-pxa.c
275
writel_relaxed(value, base + GPDR_OFFSET);
drivers/gpio/gpio-pxa.c
289
writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
drivers/gpio/gpio-pxa.c
304
writel_relaxed(tmp, base + GPDR_OFFSET);
drivers/gpio/gpio-pxa.c
322
writel_relaxed(GPIO_bit(offset),
drivers/gpio/gpio-pxa.c
388
writel_relaxed(grer, c->regbase + GRER_OFFSET);
drivers/gpio/gpio-pxa.c
389
writel_relaxed(gfer, c->regbase + GFER_OFFSET);
drivers/gpio/gpio-pxa.c
415
writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
drivers/gpio/gpio-pxa.c
417
writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
drivers/gpio/gpio-pxa.c
449
writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
drivers/gpio/gpio-pxa.c
485
writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET);
drivers/gpio/gpio-pxa.c
500
writel_relaxed(grer, base + GRER_OFFSET);
drivers/gpio/gpio-pxa.c
501
writel_relaxed(gfer, base + GFER_OFFSET);
drivers/gpio/gpio-pxa.c
674
writel_relaxed(0, c->regbase + GFER_OFFSET);
drivers/gpio/gpio-pxa.c
675
writel_relaxed(0, c->regbase + GRER_OFFSET);
drivers/gpio/gpio-pxa.c
676
writel_relaxed(~0, c->regbase + GEDR_OFFSET);
drivers/gpio/gpio-pxa.c
679
writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
drivers/gpio/gpio-pxa.c
766
writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
drivers/gpio/gpio-pxa.c
782
writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);
drivers/gpio/gpio-pxa.c
783
writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
drivers/gpio/gpio-pxa.c
785
writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
drivers/gpio/gpio-pxa.c
786
writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
drivers/gpio/gpio-pxa.c
787
writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
drivers/gpio/gpio-rda.c
103
writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
drivers/gpio/gpio-rda.c
109
writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
drivers/gpio/gpio-rda.c
113
writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
drivers/gpio/gpio-rda.c
120
writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
drivers/gpio/gpio-rda.c
124
writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
drivers/gpio/gpio-rda.c
133
writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
drivers/gpio/gpio-rda.c
142
writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
drivers/gpio/gpio-rda.c
61
writel_relaxed(tmp, base + reg);
drivers/gpio/gpio-rda.c
76
writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
drivers/gpio/gpio-rda.c
99
writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
drivers/gpio/gpio-reg.c
105
writel_relaxed(r->out, r->reg);
drivers/gpio/gpio-reg.c
191
writel_relaxed(r->out, r->reg);
drivers/gpio/gpio-reg.c
73
writel_relaxed(val, r->reg);
drivers/gpio/gpio-rtd.c
255
writel_relaxed(val, data->base + reg_offset);
drivers/gpio/gpio-rtd.c
294
writel_relaxed(val, data->base + dato_reg_offset);
drivers/gpio/gpio-rtd.c
347
writel_relaxed(val, data->base + reg_offset);
drivers/gpio/gpio-rtd.c
405
writel_relaxed(status, data->irq_base + reg_offset);
drivers/gpio/gpio-rtd.c
446
writel_relaxed(clr_mask, data->irq_base + gpa_reg_offset);
drivers/gpio/gpio-rtd.c
447
writel_relaxed(clr_mask, data->irq_base + gpda_reg_offset);
drivers/gpio/gpio-rtd.c
451
writel_relaxed(val, data->base + ie_reg_offset);
drivers/gpio/gpio-rtd.c
468
writel_relaxed(val, data->base + ie_reg_offset);
drivers/gpio/gpio-rtd.c
509
writel_relaxed(val, data->base + dp_reg_offset);
drivers/gpio/gpio-sa1100.c
125
writel_relaxed(grer, base + R_GRER);
drivers/gpio/gpio-sa1100.c
126
writel_relaxed(gfer, base + R_GFER);
drivers/gpio/gpio-sa1100.c
161
writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR);
drivers/gpio/gpio-sa1100.c
245
writel_relaxed(mask, gedr);
drivers/gpio/gpio-sa1100.c
266
writel_relaxed(sgc->irqwake & sgc->irqrising, sgc->membase + R_GRER);
drivers/gpio/gpio-sa1100.c
267
writel_relaxed(sgc->irqwake & sgc->irqfalling, sgc->membase + R_GFER);
drivers/gpio/gpio-sa1100.c
272
writel_relaxed(readl_relaxed(sgc->membase + R_GEDR),
drivers/gpio/gpio-sa1100.c
323
writel_relaxed(0, sgc->membase + R_GFER);
drivers/gpio/gpio-sa1100.c
324
writel_relaxed(0, sgc->membase + R_GRER);
drivers/gpio/gpio-sa1100.c
325
writel_relaxed(-1, sgc->membase + R_GEDR);
drivers/gpio/gpio-sa1100.c
51
writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg);
drivers/gpio/gpio-sa1100.c
72
writel_relaxed(readl_relaxed(gpdr) & ~BIT(offset), gpdr);
drivers/gpio/gpio-sa1100.c
85
writel_relaxed(readl_relaxed(gpdr) | BIT(offset), gpdr);
drivers/gpio/gpio-spear-spics.c
105
writel_relaxed(tmp, spics->base + spics->perip_cfg);
drivers/gpio/gpio-spear-spics.c
71
writel_relaxed(tmp, spics->base + spics->perip_cfg);
drivers/gpio/gpio-spear-spics.c
91
writel_relaxed(tmp, spics->base + spics->perip_cfg);
drivers/gpio/gpio-sprd.c
65
writel_relaxed(tmp, base + reg);
drivers/gpio/gpio-tegra.c
106
writel_relaxed(val, tgi->regs + reg);
drivers/gpio/gpio-vf610.c
89
writel_relaxed(val, reg);
drivers/gpio/gpio-xgs-iproc.c
107
writel_relaxed(event_mask,
drivers/gpio/gpio-xgs-iproc.c
111
writel_relaxed(int_mask,
drivers/gpio/gpio-xgs-iproc.c
133
writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE);
drivers/gpio/gpio-xgs-iproc.c
138
writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE);
drivers/gpio/gpio-xgs-iproc.c
143
writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL);
drivers/gpio/gpio-xgs-iproc.c
148
writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL);
drivers/gpio/gpio-xgs-iproc.c
266
writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK);
drivers/gpio/gpio-xgs-iproc.c
307
writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK);
drivers/gpio/gpio-xgs-iproc.c
58
writel_relaxed(event_status,
drivers/gpio/gpio-xgs-iproc.c
81
writel_relaxed(event_mask,
drivers/gpio/gpio-xgs-iproc.c
85
writel_relaxed(int_mask,
drivers/gpio/gpio-zynq.c
292
writel_relaxed(state, gpio->base_addr + reg_offset);
drivers/gpio/gpio-zynq.c
328
writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
drivers/gpio/gpio-zynq.c
360
writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
drivers/gpio/gpio-zynq.c
365
writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
drivers/gpio/gpio-zynq.c
417
writel_relaxed(BIT(bank_pin_num),
drivers/gpio/gpio-zynq.c
441
writel_relaxed(BIT(bank_pin_num),
drivers/gpio/gpio-zynq.c
461
writel_relaxed(BIT(bank_pin_num),
drivers/gpio/gpio-zynq.c
551
writel_relaxed(int_type,
drivers/gpio/gpio-zynq.c
553
writel_relaxed(int_pol,
drivers/gpio/gpio-zynq.c
555
writel_relaxed(int_any,
drivers/gpio/gpio-zynq.c
710
writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
drivers/gpio/gpio-zynq.c
712
writel_relaxed(gpio->context.datalsw[bank_num],
drivers/gpio/gpio-zynq.c
715
writel_relaxed(gpio->context.datamsw[bank_num],
drivers/gpio/gpio-zynq.c
718
writel_relaxed(gpio->context.dirm[bank_num],
drivers/gpio/gpio-zynq.c
721
writel_relaxed(gpio->context.int_type[bank_num],
drivers/gpio/gpio-zynq.c
724
writel_relaxed(gpio->context.int_polarity[bank_num],
drivers/gpio/gpio-zynq.c
727
writel_relaxed(gpio->context.int_any[bank_num],
drivers/gpio/gpio-zynq.c
730
writel_relaxed(~(gpio->context.int_en[bank_num]),
drivers/gpio/gpio-zynq.c
956
writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
drivers/gpu/drm/armada/armada_510.c
73
writel_relaxed(ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,
drivers/gpu/drm/armada/armada_crtc.c
148
writel_relaxed(drm_color_lut_extract(lut[i].red, 8),
drivers/gpu/drm/armada/armada_crtc.c
150
writel_relaxed(i | SRAM_WRITE | SRAM_GAMMA_YR,
drivers/gpu/drm/armada/armada_crtc.c
153
writel_relaxed(drm_color_lut_extract(lut[i].green, 8),
drivers/gpu/drm/armada/armada_crtc.c
155
writel_relaxed(i | SRAM_WRITE | SRAM_GAMMA_UG,
drivers/gpu/drm/armada/armada_crtc.c
158
writel_relaxed(drm_color_lut_extract(lut[i].blue, 8),
drivers/gpu/drm/armada/armada_crtc.c
160
writel_relaxed(i | SRAM_WRITE | SRAM_GAMMA_VB,
drivers/gpu/drm/armada/armada_crtc.c
265
writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
drivers/gpu/drm/armada/armada_crtc.c
266
writel_relaxed(dcrtc->v[i].spu_v_h_total,
drivers/gpu/drm/armada/armada_crtc.c
272
writel_relaxed(val, base + LCD_SPU_ADV_REG);
drivers/gpu/drm/armada/armada_crtc.c
281
writel_relaxed(dcrtc->cursor_hw_pos,
drivers/gpu/drm/armada/armada_crtc.c
283
writel_relaxed(dcrtc->cursor_hw_sz,
drivers/gpu/drm/armada/armada_crtc.c
316
writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
drivers/gpu/drm/armada/armada_crtc.c
577
writel_relaxed(val,
drivers/gpu/drm/armada/armada_crtc.c
579
writel_relaxed(addr | SRAM_WRITE,
drivers/gpu/drm/armada/armada_crtc.c
597
writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
drivers/gpu/drm/armada/armada_crtc.c
598
writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
drivers/gpu/drm/armada/armada_crtc.c
782
writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
drivers/gpu/drm/armada/armada_crtc.c
92
writel_relaxed(val | regs->val, reg);
drivers/gpu/drm/armada/armada_crtc.c
942
writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
drivers/gpu/drm/armada/armada_crtc.c
943
writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
drivers/gpu/drm/armada/armada_crtc.c
944
writel_relaxed(dcrtc->spu_iopad_ctrl,
drivers/gpu/drm/armada/armada_crtc.c
946
writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
drivers/gpu/drm/armada/armada_crtc.c
947
writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
drivers/gpu/drm/armada/armada_crtc.c
950
writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
drivers/gpu/drm/armada/armada_crtc.c
951
writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
drivers/gpu/drm/armada/armada_crtc.c
953
writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
drivers/gpu/drm/armada/armada_drm.h
30
writel_relaxed(v, ptr);
drivers/gpu/drm/bridge/inno-hdmi.c
481
writel_relaxed(val, hdmi->regs + (offset) * 0x04);
drivers/gpu/drm/bridge/microchip-lvds.c
76
writel_relaxed(val, lvds->regs + offset);
drivers/gpu/drm/exynos/exynos_drm_g2d.c
807
writel_relaxed(node->dma_addr, g2d->regs + G2D_DMA_SFR_BASE_ADDR);
drivers/gpu/drm/exynos/exynos_drm_g2d.c
808
writel_relaxed(G2D_DMA_START, g2d->regs + G2D_DMA_COMMAND);
drivers/gpu/drm/exynos/exynos_drm_g2d.c
940
writel_relaxed(pending, g2d->regs + G2D_INTC_PEND);
drivers/gpu/drm/exynos/exynos_drm_g2d.c
950
writel_relaxed(0, g2d->regs + G2D_DMA_HOLD_CMD);
drivers/gpu/drm/exynos/exynos_drm_g2d.c
952
writel_relaxed(G2D_DMA_CONTINUE,
drivers/gpu/drm/mediatek/mtk_ddp_comp.c
178
writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
drivers/gpu/drm/mediatek/mtk_ddp_comp.c
217
writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
drivers/gpu/drm/mediatek/mtk_ddp_comp.c
261
writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
drivers/gpu/drm/mediatek/mtk_ddp_comp.c
92
writel_relaxed(value, regs + offset);
drivers/gpu/drm/mediatek/mtk_disp_aal.c
148
writel_relaxed(0x0, aal->regs + DISP_AAL_EN);
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
80
writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
drivers/gpu/drm/mediatek/mtk_disp_gamma.c
236
writel_relaxed(0x0, gamma->regs + DISP_GAMMA_EN);
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
208
writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN);
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
215
writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
269
writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
271
writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
278
writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
284
writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
drivers/gpu/drm/meson/meson_crtc.c
107
writel_relaxed(0 << 16 |
drivers/gpu/drm/meson/meson_crtc.c
110
writel_relaxed(0 << 16 |
drivers/gpu/drm/meson/meson_crtc.c
113
writel_relaxed(crtc_state->mode.hdisplay << 16 |
drivers/gpu/drm/meson/meson_crtc.c
251
writel_relaxed(priv->viu.osd1_blk2_cfg4,
drivers/gpu/drm/meson/meson_crtc.c
257
writel_relaxed(priv->viu.osd1_blk1_cfg4,
drivers/gpu/drm/meson/meson_crtc.c
271
writel_relaxed(priv->viu.osd_blend_din0_scope_h,
drivers/gpu/drm/meson/meson_crtc.c
274
writel_relaxed(priv->viu.osd_blend_din0_scope_v,
drivers/gpu/drm/meson/meson_crtc.c
277
writel_relaxed(priv->viu.osb_blend0_size,
drivers/gpu/drm/meson/meson_crtc.c
280
writel_relaxed(priv->viu.osb_blend1_size,
drivers/gpu/drm/meson/meson_crtc.c
302
writel_relaxed(VD_BLEND_PREBLD_SRC_VD1 |
drivers/gpu/drm/meson/meson_crtc.c
308
writel_relaxed(priv->viu.vd1_afbc ?
drivers/gpu/drm/meson/meson_crtc.c
320
writel_relaxed(priv->viu.osd1_ctrl_stat,
drivers/gpu/drm/meson/meson_crtc.c
322
writel_relaxed(priv->viu.osd1_ctrl_stat2,
drivers/gpu/drm/meson/meson_crtc.c
324
writel_relaxed(priv->viu.osd1_blk0_cfg[0],
drivers/gpu/drm/meson/meson_crtc.c
326
writel_relaxed(priv->viu.osd1_blk0_cfg[1],
drivers/gpu/drm/meson/meson_crtc.c
328
writel_relaxed(priv->viu.osd1_blk0_cfg[2],
drivers/gpu/drm/meson/meson_crtc.c
330
writel_relaxed(priv->viu.osd1_blk0_cfg[3],
drivers/gpu/drm/meson/meson_crtc.c
332
writel_relaxed(priv->viu.osd1_blk0_cfg[4],
drivers/gpu/drm/meson/meson_crtc.c
348
writel_relaxed(priv->viu.osd_sc_ctrl0,
drivers/gpu/drm/meson/meson_crtc.c
350
writel_relaxed(priv->viu.osd_sc_i_wh_m1,
drivers/gpu/drm/meson/meson_crtc.c
352
writel_relaxed(priv->viu.osd_sc_o_h_start_end,
drivers/gpu/drm/meson/meson_crtc.c
354
writel_relaxed(priv->viu.osd_sc_o_v_start_end,
drivers/gpu/drm/meson/meson_crtc.c
356
writel_relaxed(priv->viu.osd_sc_v_ini_phase,
drivers/gpu/drm/meson/meson_crtc.c
358
writel_relaxed(priv->viu.osd_sc_v_phase_step,
drivers/gpu/drm/meson/meson_crtc.c
360
writel_relaxed(priv->viu.osd_sc_h_ini_phase,
drivers/gpu/drm/meson/meson_crtc.c
362
writel_relaxed(priv->viu.osd_sc_h_phase_step,
drivers/gpu/drm/meson/meson_crtc.c
364
writel_relaxed(priv->viu.osd_sc_h_ctrl0,
drivers/gpu/drm/meson/meson_crtc.c
366
writel_relaxed(priv->viu.osd_sc_v_ctrl0,
drivers/gpu/drm/meson/meson_crtc.c
395
writel_relaxed(priv->viu.vd1_afbc_head_addr,
drivers/gpu/drm/meson/meson_crtc.c
398
writel_relaxed(priv->viu.vd1_afbc_body_addr,
drivers/gpu/drm/meson/meson_crtc.c
401
writel_relaxed(priv->viu.vd1_afbc_en,
drivers/gpu/drm/meson/meson_crtc.c
404
writel_relaxed(priv->viu.vd1_afbc_mode,
drivers/gpu/drm/meson/meson_crtc.c
407
writel_relaxed(priv->viu.vd1_afbc_size_in,
drivers/gpu/drm/meson/meson_crtc.c
410
writel_relaxed(priv->viu.vd1_afbc_dec_def_color,
drivers/gpu/drm/meson/meson_crtc.c
413
writel_relaxed(priv->viu.vd1_afbc_conv_ctrl,
drivers/gpu/drm/meson/meson_crtc.c
416
writel_relaxed(priv->viu.vd1_afbc_size_out,
drivers/gpu/drm/meson/meson_crtc.c
419
writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_ctrl,
drivers/gpu/drm/meson/meson_crtc.c
422
writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_w,
drivers/gpu/drm/meson/meson_crtc.c
425
writel_relaxed(priv->viu.vd1_afbc_mif_hor_scope,
drivers/gpu/drm/meson/meson_crtc.c
428
writel_relaxed(priv->viu.vd1_afbc_mif_ver_scope,
drivers/gpu/drm/meson/meson_crtc.c
431
writel_relaxed(priv->viu.vd1_afbc_pixel_hor_scope,
drivers/gpu/drm/meson/meson_crtc.c
434
writel_relaxed(priv->viu.vd1_afbc_pixel_ver_scope,
drivers/gpu/drm/meson/meson_crtc.c
437
writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_h,
drivers/gpu/drm/meson/meson_crtc.c
473
writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE));
drivers/gpu/drm/meson/meson_crtc.c
476
writel_relaxed(priv->viu.vd1_if0_gen_reg,
drivers/gpu/drm/meson/meson_crtc.c
479
writel_relaxed(priv->viu.vd1_if0_gen_reg,
drivers/gpu/drm/meson/meson_crtc.c
482
writel_relaxed(priv->viu.vd1_if0_gen_reg2,
drivers/gpu/drm/meson/meson_crtc.c
485
writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
drivers/gpu/drm/meson/meson_crtc.c
488
writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
drivers/gpu/drm/meson/meson_crtc.c
491
writel_relaxed(priv->viu.viu_vd1_fmt_w,
drivers/gpu/drm/meson/meson_crtc.c
494
writel_relaxed(priv->viu.viu_vd1_fmt_w,
drivers/gpu/drm/meson/meson_crtc.c
497
writel_relaxed(priv->viu.vd1_if0_canvas0,
drivers/gpu/drm/meson/meson_crtc.c
500
writel_relaxed(priv->viu.vd1_if0_canvas0,
drivers/gpu/drm/meson/meson_crtc.c
503
writel_relaxed(priv->viu.vd1_if0_canvas0,
drivers/gpu/drm/meson/meson_crtc.c
506
writel_relaxed(priv->viu.vd1_if0_canvas0,
drivers/gpu/drm/meson/meson_crtc.c
509
writel_relaxed(priv->viu.vd1_if0_luma_x0,
drivers/gpu/drm/meson/meson_crtc.c
512
writel_relaxed(priv->viu.vd1_if0_luma_x0,
drivers/gpu/drm/meson/meson_crtc.c
515
writel_relaxed(priv->viu.vd1_if0_luma_x0,
drivers/gpu/drm/meson/meson_crtc.c
518
writel_relaxed(priv->viu.vd1_if0_luma_x0,
drivers/gpu/drm/meson/meson_crtc.c
521
writel_relaxed(priv->viu.vd1_if0_luma_y0,
drivers/gpu/drm/meson/meson_crtc.c
524
writel_relaxed(priv->viu.vd1_if0_luma_y0,
drivers/gpu/drm/meson/meson_crtc.c
527
writel_relaxed(priv->viu.vd1_if0_luma_y0,
drivers/gpu/drm/meson/meson_crtc.c
530
writel_relaxed(priv->viu.vd1_if0_luma_y0,
drivers/gpu/drm/meson/meson_crtc.c
533
writel_relaxed(priv->viu.vd1_if0_chroma_x0,
drivers/gpu/drm/meson/meson_crtc.c
536
writel_relaxed(priv->viu.vd1_if0_chroma_x0,
drivers/gpu/drm/meson/meson_crtc.c
539
writel_relaxed(priv->viu.vd1_if0_chroma_x0,
drivers/gpu/drm/meson/meson_crtc.c
542
writel_relaxed(priv->viu.vd1_if0_chroma_x0,
drivers/gpu/drm/meson/meson_crtc.c
545
writel_relaxed(priv->viu.vd1_if0_chroma_y0,
drivers/gpu/drm/meson/meson_crtc.c
548
writel_relaxed(priv->viu.vd1_if0_chroma_y0,
drivers/gpu/drm/meson/meson_crtc.c
551
writel_relaxed(priv->viu.vd1_if0_chroma_y0,
drivers/gpu/drm/meson/meson_crtc.c
554
writel_relaxed(priv->viu.vd1_if0_chroma_y0,
drivers/gpu/drm/meson/meson_crtc.c
557
writel_relaxed(priv->viu.vd1_if0_repeat_loop,
drivers/gpu/drm/meson/meson_crtc.c
560
writel_relaxed(priv->viu.vd1_if0_repeat_loop,
drivers/gpu/drm/meson/meson_crtc.c
563
writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
drivers/gpu/drm/meson/meson_crtc.c
566
writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
drivers/gpu/drm/meson/meson_crtc.c
569
writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
drivers/gpu/drm/meson/meson_crtc.c
572
writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
drivers/gpu/drm/meson/meson_crtc.c
575
writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
drivers/gpu/drm/meson/meson_crtc.c
578
writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
drivers/gpu/drm/meson/meson_crtc.c
581
writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
drivers/gpu/drm/meson/meson_crtc.c
584
writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
drivers/gpu/drm/meson/meson_crtc.c
587
writel_relaxed(0, priv->io_base + meson_crtc->viu_offset +
drivers/gpu/drm/meson/meson_crtc.c
589
writel_relaxed(0, priv->io_base + meson_crtc->viu_offset +
drivers/gpu/drm/meson/meson_crtc.c
591
writel_relaxed(0, priv->io_base + meson_crtc->viu_offset +
drivers/gpu/drm/meson/meson_crtc.c
593
writel_relaxed(0, priv->io_base + meson_crtc->viu_offset +
drivers/gpu/drm/meson/meson_crtc.c
595
writel_relaxed(priv->viu.vd1_range_map_y,
drivers/gpu/drm/meson/meson_crtc.c
598
writel_relaxed(priv->viu.vd1_range_map_cb,
drivers/gpu/drm/meson/meson_crtc.c
601
writel_relaxed(priv->viu.vd1_range_map_cr,
drivers/gpu/drm/meson/meson_crtc.c
604
writel_relaxed(VPP_VSC_BANK_LENGTH(4) |
drivers/gpu/drm/meson/meson_crtc.c
611
writel_relaxed(priv->viu.vpp_pic_in_height,
drivers/gpu/drm/meson/meson_crtc.c
613
writel_relaxed(priv->viu.vpp_postblend_vd1_h_start_end,
drivers/gpu/drm/meson/meson_crtc.c
615
writel_relaxed(priv->viu.vpp_blend_vd2_h_start_end,
drivers/gpu/drm/meson/meson_crtc.c
617
writel_relaxed(priv->viu.vpp_postblend_vd1_v_start_end,
drivers/gpu/drm/meson/meson_crtc.c
619
writel_relaxed(priv->viu.vpp_blend_vd2_v_start_end,
drivers/gpu/drm/meson/meson_crtc.c
621
writel_relaxed(priv->viu.vpp_hsc_region12_startp,
drivers/gpu/drm/meson/meson_crtc.c
623
writel_relaxed(priv->viu.vpp_hsc_region34_startp,
drivers/gpu/drm/meson/meson_crtc.c
625
writel_relaxed(priv->viu.vpp_hsc_region4_endp,
drivers/gpu/drm/meson/meson_crtc.c
627
writel_relaxed(priv->viu.vpp_hsc_start_phase_step,
drivers/gpu/drm/meson/meson_crtc.c
629
writel_relaxed(priv->viu.vpp_hsc_region1_phase_slope,
drivers/gpu/drm/meson/meson_crtc.c
631
writel_relaxed(priv->viu.vpp_hsc_region3_phase_slope,
drivers/gpu/drm/meson/meson_crtc.c
633
writel_relaxed(priv->viu.vpp_line_in_length,
drivers/gpu/drm/meson/meson_crtc.c
635
writel_relaxed(priv->viu.vpp_preblend_h_size,
drivers/gpu/drm/meson/meson_crtc.c
637
writel_relaxed(priv->viu.vpp_vsc_region12_startp,
drivers/gpu/drm/meson/meson_crtc.c
639
writel_relaxed(priv->viu.vpp_vsc_region34_startp,
drivers/gpu/drm/meson/meson_crtc.c
641
writel_relaxed(priv->viu.vpp_vsc_region4_endp,
drivers/gpu/drm/meson/meson_crtc.c
643
writel_relaxed(priv->viu.vpp_vsc_start_phase_step,
drivers/gpu/drm/meson/meson_crtc.c
645
writel_relaxed(priv->viu.vpp_vsc_ini_phase,
drivers/gpu/drm/meson/meson_crtc.c
647
writel_relaxed(priv->viu.vpp_vsc_phase_ctrl,
drivers/gpu/drm/meson/meson_crtc.c
649
writel_relaxed(priv->viu.vpp_hsc_phase_ctrl,
drivers/gpu/drm/meson/meson_crtc.c
651
writel_relaxed(0x42, priv->io_base + _REG(VPP_SCALE_COEF_IDX));
drivers/gpu/drm/meson/meson_drv.c
147
writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
drivers/gpu/drm/meson/meson_drv.c
151
writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
drivers/gpu/drm/meson/meson_drv.c
156
writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
drivers/gpu/drm/meson/meson_drv.c
160
writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
drivers/gpu/drm/meson/meson_dw_hdmi.c
412
writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
drivers/gpu/drm/meson/meson_dw_hdmi.c
414
writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
drivers/gpu/drm/meson/meson_dw_hdmi.c
424
writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
drivers/gpu/drm/meson/meson_dw_hdmi.c
426
writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
128
writel_relaxed(FIELD_PREP(MIPI_DSI_TOP_DPI_COLOR_MODE, dpi_data_format) |
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
72
writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD);
drivers/gpu/drm/meson/meson_encoder_dsi.c
70
writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
drivers/gpu/drm/meson/meson_encoder_dsi.c
74
writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN));
drivers/gpu/drm/meson/meson_encoder_dsi.c
78
writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN));
drivers/gpu/drm/meson/meson_encoder_dsi.c
88
writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
drivers/gpu/drm/meson/meson_encoder_hdmi.c
236
writel_relaxed(2 | (2 << 2),
drivers/gpu/drm/meson/meson_encoder_hdmi.c
240
writel_relaxed(1 | (2 << 2),
drivers/gpu/drm/meson/meson_encoder_hdmi.c
244
writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
drivers/gpu/drm/meson/meson_encoder_hdmi.c
249
writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
drivers/gpu/drm/meson/meson_encoder_hdmi.c
251
writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
drivers/gpu/drm/meson/meson_encoder_hdmi.c
263
writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
drivers/gpu/drm/meson/meson_encoder_hdmi.c
264
writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
drivers/gpu/drm/meson/meson_osd_afbcd.c
103
writel_relaxed(FIELD_PREP(OSD1_AFBCD_ID_FIFO_THRD, 0x40) |
drivers/gpu/drm/meson/meson_osd_afbcd.c
133
writel_relaxed(mode, priv->io_base + _REG(OSD1_AFBCD_MODE));
drivers/gpu/drm/meson/meson_osd_afbcd.c
135
writel_relaxed(FIELD_PREP(OSD1_AFBCD_HREG_VSIZE_IN,
drivers/gpu/drm/meson/meson_osd_afbcd.c
141
writel_relaxed(priv->viu.osd1_addr >> 4,
drivers/gpu/drm/meson/meson_osd_afbcd.c
143
writel_relaxed(priv->viu.osd1_addr >> 4,
drivers/gpu/drm/meson/meson_osd_afbcd.c
146
writel_relaxed((0xe4 << 24) | (priv->viu.osd1_addr & 0xffffff),
drivers/gpu/drm/meson/meson_osd_afbcd.c
162
writel_relaxed(conv_lbuf_len,
drivers/gpu/drm/meson/meson_osd_afbcd.c
165
writel_relaxed(FIELD_PREP(OSD1_AFBCD_DEC_PIXEL_BGN_H, 0) |
drivers/gpu/drm/meson/meson_osd_afbcd.c
170
writel_relaxed(FIELD_PREP(OSD1_AFBCD_DEC_PIXEL_BGN_V, 0) |
drivers/gpu/drm/meson/meson_osd_afbcd.c
84
writel_relaxed(VIU_SW_RESET_OSD1_AFBCD,
drivers/gpu/drm/meson/meson_osd_afbcd.c
86
writel_relaxed(0, priv->io_base + _REG(VIU_SW_RESET));
drivers/gpu/drm/meson/meson_overlay.c
738
writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
drivers/gpu/drm/meson/meson_overlay.c
739
writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL));
drivers/gpu/drm/meson/meson_overlay.c
740
writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0));
drivers/gpu/drm/meson/meson_overlay.c
741
writel_relaxed(0, priv->io_base + _REG(VD2_IF0_GEN_REG + 0x17b0));
drivers/gpu/drm/meson/meson_rdma.c
113
writel_relaxed(val, priv->io_base + _REG(reg));
drivers/gpu/drm/meson/meson_rdma.c
38
writel_relaxed(RDMA_CTRL_SW_RESET,
drivers/gpu/drm/meson/meson_rdma.c
40
writel_relaxed(RDMA_DEFAULT_CONFIG |
drivers/gpu/drm/meson/meson_registers.h
15
writel_relaxed((readl_relaxed(addr) & ~(mask)) | ((val) & (mask)), addr)
drivers/gpu/drm/meson/meson_venc.c
1048
writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
drivers/gpu/drm/meson/meson_venc.c
1049
writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
drivers/gpu/drm/meson/meson_venc.c
1056
writel_relaxed(ENCI_CFILT_CMPT_SEL_HIGH | 0x10,
drivers/gpu/drm/meson/meson_venc.c
1058
writel_relaxed(ENCI_CFILT_CMPT_CR_DLY(2) |
drivers/gpu/drm/meson/meson_venc.c
1063
writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
drivers/gpu/drm/meson/meson_venc.c
1066
writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
drivers/gpu/drm/meson/meson_venc.c
1067
writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
drivers/gpu/drm/meson/meson_venc.c
1070
writel_relaxed(vmode->enci.hso_begin,
drivers/gpu/drm/meson/meson_venc.c
1072
writel_relaxed(vmode->enci.hso_end,
drivers/gpu/drm/meson/meson_venc.c
1076
writel_relaxed(vmode->enci.vso_even,
drivers/gpu/drm/meson/meson_venc.c
1078
writel_relaxed(vmode->enci.vso_odd,
drivers/gpu/drm/meson/meson_venc.c
1082
writel_relaxed(ENCI_MACV_MAX_AMP_ENABLE_CHANGE |
drivers/gpu/drm/meson/meson_venc.c
1087
writel_relaxed(vmode->enci.video_prog_mode,
drivers/gpu/drm/meson/meson_venc.c
1089
writel_relaxed(vmode->enci.video_mode,
drivers/gpu/drm/meson/meson_venc.c
1101
writel_relaxed(ENCI_VIDEO_MODE_ADV_DMXMD(2) |
drivers/gpu/drm/meson/meson_venc.c
1110
writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
drivers/gpu/drm/meson/meson_venc.c
1113
writel_relaxed(vmode->enci.yc_delay,
drivers/gpu/drm/meson/meson_venc.c
1118
writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
drivers/gpu/drm/meson/meson_venc.c
1128
writel_relaxed(ENCI_VFIFO2VD_CTL_ENABLE |
drivers/gpu/drm/meson/meson_venc.c
1133
writel_relaxed(vmode->enci.pixel_start,
drivers/gpu/drm/meson/meson_venc.c
1135
writel_relaxed(vmode->enci.pixel_end,
drivers/gpu/drm/meson/meson_venc.c
1138
writel_relaxed(vmode->enci.top_field_line_start,
drivers/gpu/drm/meson/meson_venc.c
1140
writel_relaxed(vmode->enci.top_field_line_end,
drivers/gpu/drm/meson/meson_venc.c
1143
writel_relaxed(vmode->enci.bottom_field_line_start,
drivers/gpu/drm/meson/meson_venc.c
1145
writel_relaxed(vmode->enci.bottom_field_line_end,
drivers/gpu/drm/meson/meson_venc.c
1152
writel_relaxed(ENCI_VIDEO_EN_ENABLE,
drivers/gpu/drm/meson/meson_venc.c
1165
writel_relaxed(de_h_begin,
drivers/gpu/drm/meson/meson_venc.c
1167
writel_relaxed(de_h_end,
drivers/gpu/drm/meson/meson_venc.c
1177
writel_relaxed(de_v_begin_even,
drivers/gpu/drm/meson/meson_venc.c
1179
writel_relaxed(de_v_end_even,
drivers/gpu/drm/meson/meson_venc.c
1181
writel_relaxed(de_v_begin_odd,
drivers/gpu/drm/meson/meson_venc.c
1183
writel_relaxed(de_v_end_odd,
drivers/gpu/drm/meson/meson_venc.c
1198
writel_relaxed(hs_begin,
drivers/gpu/drm/meson/meson_venc.c
1200
writel_relaxed(hs_end,
drivers/gpu/drm/meson/meson_venc.c
1211
writel_relaxed(vs_bline_evn,
drivers/gpu/drm/meson/meson_venc.c
1214
writel_relaxed(vs_eline_evn,
drivers/gpu/drm/meson/meson_venc.c
1217
writel_relaxed(hs_begin,
drivers/gpu/drm/meson/meson_venc.c
1219
writel_relaxed(hs_begin,
drivers/gpu/drm/meson/meson_venc.c
1226
writel_relaxed(vs_bline_odd,
drivers/gpu/drm/meson/meson_venc.c
1229
writel_relaxed(hs_begin,
drivers/gpu/drm/meson/meson_venc.c
1237
writel_relaxed(vs_eline_evn, priv->io_base
drivers/gpu/drm/meson/meson_venc.c
1240
writel_relaxed(hs_begin, priv->io_base
drivers/gpu/drm/meson/meson_venc.c
1246
writel_relaxed(vs_eline_odd, priv->io_base
drivers/gpu/drm/meson/meson_venc.c
1249
writel_relaxed(hs_begin, priv->io_base
drivers/gpu/drm/meson/meson_venc.c
1261
writel_relaxed(vs_bline_odd,
drivers/gpu/drm/meson/meson_venc.c
1264
writel_relaxed(vs_eline_odd,
drivers/gpu/drm/meson/meson_venc.c
1271
writel_relaxed(vso_begin_odd,
drivers/gpu/drm/meson/meson_venc.c
1273
writel_relaxed(vso_begin_odd,
drivers/gpu/drm/meson/meson_venc.c
1279
writel_relaxed(vs_bline_evn,
drivers/gpu/drm/meson/meson_venc.c
1286
writel_relaxed(vso_begin_evn, priv->io_base
drivers/gpu/drm/meson/meson_venc.c
1294
writel_relaxed(vs_eline_odd, priv->io_base
drivers/gpu/drm/meson/meson_venc.c
1297
writel_relaxed(vso_begin_evn, priv->io_base
drivers/gpu/drm/meson/meson_venc.c
1302
writel_relaxed(vs_eline_evn, priv->io_base
drivers/gpu/drm/meson/meson_venc.c
1305
writel_relaxed(vso_begin_evn, priv->io_base
drivers/gpu/drm/meson/meson_venc.c
1310
writel_relaxed(vmode->encp.dvi_settings,
drivers/gpu/drm/meson/meson_venc.c
1312
writel_relaxed(vmode->encp.video_mode,
drivers/gpu/drm/meson/meson_venc.c
1314
writel_relaxed(vmode->encp.video_mode_adv,
drivers/gpu/drm/meson/meson_venc.c
1317
writel_relaxed(vmode->encp.video_prog_mode,
drivers/gpu/drm/meson/meson_venc.c
1320
writel_relaxed(vmode->encp.video_sync_mode,
drivers/gpu/drm/meson/meson_venc.c
1323
writel_relaxed(vmode->encp.video_yc_dly,
drivers/gpu/drm/meson/meson_venc.c
1326
writel_relaxed(vmode->encp.video_rgb_ctrl,
drivers/gpu/drm/meson/meson_venc.c
1329
writel_relaxed(vmode->encp.video_filt_ctrl,
drivers/gpu/drm/meson/meson_venc.c
1332
writel_relaxed(vmode->encp.video_ofld_voav_ofst,
drivers/gpu/drm/meson/meson_venc.c
1335
writel_relaxed(vmode->encp.yfp1_htime,
drivers/gpu/drm/meson/meson_venc.c
1337
writel_relaxed(vmode->encp.yfp2_htime,
drivers/gpu/drm/meson/meson_venc.c
1339
writel_relaxed(vmode->encp.max_pxcnt,
drivers/gpu/drm/meson/meson_venc.c
1341
writel_relaxed(vmode->encp.hspuls_begin,
drivers/gpu/drm/meson/meson_venc.c
1343
writel_relaxed(vmode->encp.hspuls_end,
drivers/gpu/drm/meson/meson_venc.c
1345
writel_relaxed(vmode->encp.hspuls_switch,
drivers/gpu/drm/meson/meson_venc.c
1347
writel_relaxed(vmode->encp.vspuls_begin,
drivers/gpu/drm/meson/meson_venc.c
1349
writel_relaxed(vmode->encp.vspuls_end,
drivers/gpu/drm/meson/meson_venc.c
1351
writel_relaxed(vmode->encp.vspuls_bline,
drivers/gpu/drm/meson/meson_venc.c
1353
writel_relaxed(vmode->encp.vspuls_eline,
drivers/gpu/drm/meson/meson_venc.c
1356
writel_relaxed(vmode->encp.eqpuls_begin,
drivers/gpu/drm/meson/meson_venc.c
1359
writel_relaxed(vmode->encp.eqpuls_end,
drivers/gpu/drm/meson/meson_venc.c
1362
writel_relaxed(vmode->encp.eqpuls_bline,
drivers/gpu/drm/meson/meson_venc.c
1365
writel_relaxed(vmode->encp.eqpuls_eline,
drivers/gpu/drm/meson/meson_venc.c
1367
writel_relaxed(vmode->encp.havon_begin,
drivers/gpu/drm/meson/meson_venc.c
1369
writel_relaxed(vmode->encp.havon_end,
drivers/gpu/drm/meson/meson_venc.c
1371
writel_relaxed(vmode->encp.vavon_bline,
drivers/gpu/drm/meson/meson_venc.c
1373
writel_relaxed(vmode->encp.vavon_eline,
drivers/gpu/drm/meson/meson_venc.c
1375
writel_relaxed(vmode->encp.hso_begin,
drivers/gpu/drm/meson/meson_venc.c
1377
writel_relaxed(vmode->encp.hso_end,
drivers/gpu/drm/meson/meson_venc.c
1379
writel_relaxed(vmode->encp.vso_begin,
drivers/gpu/drm/meson/meson_venc.c
1381
writel_relaxed(vmode->encp.vso_end,
drivers/gpu/drm/meson/meson_venc.c
1383
writel_relaxed(vmode->encp.vso_bline,
drivers/gpu/drm/meson/meson_venc.c
1386
writel_relaxed(vmode->encp.vso_eline,
drivers/gpu/drm/meson/meson_venc.c
1389
writel_relaxed(vmode->encp.sy_val,
drivers/gpu/drm/meson/meson_venc.c
1392
writel_relaxed(vmode->encp.sy2_val,
drivers/gpu/drm/meson/meson_venc.c
1394
writel_relaxed(vmode->encp.max_lncnt,
drivers/gpu/drm/meson/meson_venc.c
1397
writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
drivers/gpu/drm/meson/meson_venc.c
1412
writel_relaxed(de_h_begin,
drivers/gpu/drm/meson/meson_venc.c
1414
writel_relaxed(de_h_end,
drivers/gpu/drm/meson/meson_venc.c
1426
writel_relaxed(de_v_begin_even,
drivers/gpu/drm/meson/meson_venc.c
1428
writel_relaxed(de_v_end_even,
drivers/gpu/drm/meson/meson_venc.c
1441
writel_relaxed(de_v_begin_odd,
drivers/gpu/drm/meson/meson_venc.c
1443
writel_relaxed(de_v_end_odd,
drivers/gpu/drm/meson/meson_venc.c
1462
writel_relaxed(hs_begin,
drivers/gpu/drm/meson/meson_venc.c
1464
writel_relaxed(hs_end,
drivers/gpu/drm/meson/meson_venc.c
1484
writel_relaxed(vs_bline_evn,
drivers/gpu/drm/meson/meson_venc.c
1486
writel_relaxed(vs_eline_evn,
drivers/gpu/drm/meson/meson_venc.c
1490
writel_relaxed(vso_begin_evn,
drivers/gpu/drm/meson/meson_venc.c
1492
writel_relaxed(vso_begin_evn,
drivers/gpu/drm/meson/meson_venc.c
1506
writel_relaxed(vs_bline_odd,
drivers/gpu/drm/meson/meson_venc.c
1508
writel_relaxed(vs_eline_odd,
drivers/gpu/drm/meson/meson_venc.c
1510
writel_relaxed(vso_begin_odd,
drivers/gpu/drm/meson/meson_venc.c
1512
writel_relaxed(vso_begin_odd,
drivers/gpu/drm/meson/meson_venc.c
1552
writel_relaxed(reg, priv->io_base + _REG(VPU_HDMI_SETTING));
drivers/gpu/drm/meson/meson_venc.c
1595
writel_relaxed(L_GAMMA_ADDR_PORT_AUTO_INC | rgb_mask |
drivers/gpu/drm/meson/meson_venc.c
1606
writel_relaxed(data[i], priv->io_base + _REG(L_GAMMA_DATA_PORT));
drivers/gpu/drm/meson/meson_venc.c
1614
writel_relaxed(L_GAMMA_ADDR_PORT_AUTO_INC | rgb_mask |
drivers/gpu/drm/meson/meson_venc.c
1660
writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
drivers/gpu/drm/meson/meson_venc.c
1662
writel_relaxed(ENCL_PX_LN_CNT_SHADOW_EN, priv->io_base + _REG(ENCL_VIDEO_MODE));
drivers/gpu/drm/meson/meson_venc.c
1663
writel_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN |
drivers/gpu/drm/meson/meson_venc.c
1667
writel_relaxed(ENCL_VIDEO_FILT_CTRL_BYPASS_FILTER,
drivers/gpu/drm/meson/meson_venc.c
1669
writel_relaxed(max_pxcnt, priv->io_base + _REG(ENCL_VIDEO_MAX_PXCNT));
drivers/gpu/drm/meson/meson_venc.c
1670
writel_relaxed(max_lncnt, priv->io_base + _REG(ENCL_VIDEO_MAX_LNCNT));
drivers/gpu/drm/meson/meson_venc.c
1671
writel_relaxed(havon_begin, priv->io_base + _REG(ENCL_VIDEO_HAVON_BEGIN));
drivers/gpu/drm/meson/meson_venc.c
1672
writel_relaxed(havon_end, priv->io_base + _REG(ENCL_VIDEO_HAVON_END));
drivers/gpu/drm/meson/meson_venc.c
1673
writel_relaxed(vavon_bline, priv->io_base + _REG(ENCL_VIDEO_VAVON_BLINE));
drivers/gpu/drm/meson/meson_venc.c
1674
writel_relaxed(vavon_eline, priv->io_base + _REG(ENCL_VIDEO_VAVON_ELINE));
drivers/gpu/drm/meson/meson_venc.c
1676
writel_relaxed(hso_begin, priv->io_base + _REG(ENCL_VIDEO_HSO_BEGIN));
drivers/gpu/drm/meson/meson_venc.c
1677
writel_relaxed(hso_end, priv->io_base + _REG(ENCL_VIDEO_HSO_END));
drivers/gpu/drm/meson/meson_venc.c
1678
writel_relaxed(vso_begin, priv->io_base + _REG(ENCL_VIDEO_VSO_BEGIN));
drivers/gpu/drm/meson/meson_venc.c
1679
writel_relaxed(vso_end, priv->io_base + _REG(ENCL_VIDEO_VSO_END));
drivers/gpu/drm/meson/meson_venc.c
1680
writel_relaxed(vso_bline, priv->io_base + _REG(ENCL_VIDEO_VSO_BLINE));
drivers/gpu/drm/meson/meson_venc.c
1681
writel_relaxed(vso_eline, priv->io_base + _REG(ENCL_VIDEO_VSO_ELINE));
drivers/gpu/drm/meson/meson_venc.c
1682
writel_relaxed(ENCL_VIDEO_RGBIN_RGB | ENCL_VIDEO_RGBIN_ZBLK,
drivers/gpu/drm/meson/meson_venc.c
1686
writel_relaxed(0, priv->io_base + _REG(ENCL_TST_MDSEL));
drivers/gpu/drm/meson/meson_venc.c
1687
writel_relaxed(0, priv->io_base + _REG(ENCL_TST_Y));
drivers/gpu/drm/meson/meson_venc.c
1688
writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CB));
drivers/gpu/drm/meson/meson_venc.c
1689
writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CR));
drivers/gpu/drm/meson/meson_venc.c
1690
writel_relaxed(1, priv->io_base + _REG(ENCL_TST_EN));
drivers/gpu/drm/meson/meson_venc.c
1694
writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN));
drivers/gpu/drm/meson/meson_venc.c
1696
writel_relaxed(0, priv->io_base + _REG(L_RGB_BASE_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1697
writel_relaxed(0x400, priv->io_base + _REG(L_RGB_COEFF_ADDR)); /* Magic value */
drivers/gpu/drm/meson/meson_venc.c
1699
writel_relaxed(L_DITH_CNTL_DITH10_EN, priv->io_base + _REG(L_DITH_CNTL_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1702
writel_relaxed(havon_begin, priv->io_base + _REG(L_OEH_HS_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1703
writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEH_HE_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1704
writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEH_VS_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1705
writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEH_VE_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1708
writel_relaxed(havon_begin, priv->io_base + _REG(L_OEV1_HS_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1709
writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEV1_HE_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1710
writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEV1_VS_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1711
writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEV1_VE_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1715
writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HS_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1716
writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HE_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1718
writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HS_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1719
writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HE_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1721
writel_relaxed(0, priv->io_base + _REG(L_STH1_VS_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1722
writel_relaxed(max_lncnt, priv->io_base + _REG(L_STH1_VE_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1725
writel_relaxed(vso_begin, priv->io_base + _REG(L_STV1_HS_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1726
writel_relaxed(vso_end, priv->io_base + _REG(L_STV1_HE_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1728
writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VS_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1729
writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VE_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1731
writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VS_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1732
writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VE_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1736
writel_relaxed(havon_begin, priv->io_base + _REG(L_DE_HS_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1737
writel_relaxed(havon_end + 1, priv->io_base + _REG(L_DE_HE_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1738
writel_relaxed(vavon_bline, priv->io_base + _REG(L_DE_VS_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1739
writel_relaxed(vavon_eline, priv->io_base + _REG(L_DE_VE_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1742
writel_relaxed(hso_begin, priv->io_base + _REG(L_HSYNC_HS_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1743
writel_relaxed(hso_end, priv->io_base + _REG(L_HSYNC_HE_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1744
writel_relaxed(0, priv->io_base + _REG(L_HSYNC_VS_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1745
writel_relaxed(max_lncnt, priv->io_base + _REG(L_HSYNC_VE_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1748
writel_relaxed(vso_begin, priv->io_base + _REG(L_VSYNC_HS_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1749
writel_relaxed(vso_end, priv->io_base + _REG(L_VSYNC_HE_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1750
writel_relaxed(vso_bline, priv->io_base + _REG(L_VSYNC_VS_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1751
writel_relaxed(vso_eline, priv->io_base + _REG(L_VSYNC_VE_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1753
writel_relaxed(0, priv->io_base + _REG(L_INV_CNT_ADDR));
drivers/gpu/drm/meson/meson_venc.c
1754
writel_relaxed(L_TCON_MISC_SEL_STV1 | L_TCON_MISC_SEL_STV2,
drivers/gpu/drm/meson/meson_venc.c
1770
writel_relaxed(ENCI_CFILT_CMPT_SEL_HIGH | 0x10,
drivers/gpu/drm/meson/meson_venc.c
1772
writel_relaxed(ENCI_CFILT_CMPT_CR_DLY(2) |
drivers/gpu/drm/meson/meson_venc.c
1777
writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
drivers/gpu/drm/meson/meson_venc.c
1780
writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
drivers/gpu/drm/meson/meson_venc.c
1781
writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
drivers/gpu/drm/meson/meson_venc.c
1784
writel_relaxed(mode->hso_begin,
drivers/gpu/drm/meson/meson_venc.c
1786
writel_relaxed(mode->hso_end,
drivers/gpu/drm/meson/meson_venc.c
1790
writel_relaxed(mode->vso_even,
drivers/gpu/drm/meson/meson_venc.c
1792
writel_relaxed(mode->vso_odd,
drivers/gpu/drm/meson/meson_venc.c
1796
writel_relaxed(ENCI_MACV_MAX_AMP_ENABLE_CHANGE |
drivers/gpu/drm/meson/meson_venc.c
1801
writel_relaxed(mode->video_prog_mode,
drivers/gpu/drm/meson/meson_venc.c
1803
writel_relaxed(mode->video_mode,
drivers/gpu/drm/meson/meson_venc.c
1815
writel_relaxed(ENCI_VIDEO_MODE_ADV_DMXMD(2) |
drivers/gpu/drm/meson/meson_venc.c
1823
writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
drivers/gpu/drm/meson/meson_venc.c
1826
writel_relaxed(mode->yc_delay, priv->io_base + _REG(ENCI_YC_DELAY));
drivers/gpu/drm/meson/meson_venc.c
1829
writel_relaxed(mode->pixel_start,
drivers/gpu/drm/meson/meson_venc.c
1831
writel_relaxed(mode->pixel_end,
drivers/gpu/drm/meson/meson_venc.c
1834
writel_relaxed(mode->top_field_line_start,
drivers/gpu/drm/meson/meson_venc.c
1836
writel_relaxed(mode->top_field_line_end,
drivers/gpu/drm/meson/meson_venc.c
1839
writel_relaxed(mode->bottom_field_line_start,
drivers/gpu/drm/meson/meson_venc.c
1841
writel_relaxed(mode->bottom_field_line_end,
drivers/gpu/drm/meson/meson_venc.c
1845
writel_relaxed(0, priv->io_base + _REG(VENC_SYNC_ROUTE));
drivers/gpu/drm/meson/meson_venc.c
1848
writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
drivers/gpu/drm/meson/meson_venc.c
1858
writel_relaxed(ENCI_VFIFO2VD_CTL_ENABLE |
drivers/gpu/drm/meson/meson_venc.c
1863
writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_SETTING));
drivers/gpu/drm/meson/meson_venc.c
1878
writel_relaxed(VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA | reg,
drivers/gpu/drm/meson/meson_venc.c
1885
writel_relaxed(VENC_UPSAMPLE_CTRL_INTERLACE_PB | reg,
drivers/gpu/drm/meson/meson_venc.c
1892
writel_relaxed(VENC_UPSAMPLE_CTRL_INTERLACE_PR | reg,
drivers/gpu/drm/meson/meson_venc.c
1896
writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL0));
drivers/gpu/drm/meson/meson_venc.c
1897
writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL1));
drivers/gpu/drm/meson/meson_venc.c
1898
writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL2));
drivers/gpu/drm/meson/meson_venc.c
1899
writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL3));
drivers/gpu/drm/meson/meson_venc.c
1900
writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL4));
drivers/gpu/drm/meson/meson_venc.c
1901
writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL5));
drivers/gpu/drm/meson/meson_venc.c
1907
writel_relaxed(VENC_VDAC_FIFO_EN_ENCI_ENABLE,
drivers/gpu/drm/meson/meson_venc.c
1911
writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_0));
drivers/gpu/drm/meson/meson_venc.c
1912
writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_1));
drivers/gpu/drm/meson/meson_venc.c
1915
writel_relaxed(ENCI_VIDEO_EN_ENABLE,
drivers/gpu/drm/meson/meson_venc.c
1919
writel_relaxed(mode->video_saturation,
drivers/gpu/drm/meson/meson_venc.c
1921
writel_relaxed(mode->video_contrast,
drivers/gpu/drm/meson/meson_venc.c
1923
writel_relaxed(mode->video_brightness,
drivers/gpu/drm/meson/meson_venc.c
1925
writel_relaxed(mode->video_hue,
drivers/gpu/drm/meson/meson_venc.c
1929
writel_relaxed(VENC_VDAC_DAC0_FILT_CTRL0_EN,
drivers/gpu/drm/meson/meson_venc.c
1931
writel_relaxed(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1));
drivers/gpu/drm/meson/meson_venc.c
1934
writel_relaxed(0, priv->io_base + _REG(ENCI_MACV_N0));
drivers/gpu/drm/meson/meson_venc.c
1937
writel_relaxed(mode->analog_sync_adj,
drivers/gpu/drm/meson/meson_venc.c
1953
writel_relaxed(VENC_INTCTRL_ENCP_LNRST_INT_EN,
drivers/gpu/drm/meson/meson_venc.c
1957
writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN,
drivers/gpu/drm/meson/meson_venc.c
1966
writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL));
drivers/gpu/drm/meson/meson_venc.c
1981
writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));
drivers/gpu/drm/meson/meson_venc.c
1992
writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
drivers/gpu/drm/meson/meson_venc.c
1993
writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
drivers/gpu/drm/meson/meson_venc.c
1994
writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
drivers/gpu/drm/meson/meson_viu.c
332
writel_relaxed(osd1_fifo_ctrl_stat,
drivers/gpu/drm/meson/meson_viu.c
334
writel_relaxed(osd1_ctrl_stat2,
drivers/gpu/drm/meson/meson_viu.c
448
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
drivers/gpu/drm/meson/meson_viu.c
449
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
drivers/gpu/drm/meson/meson_viu.c
463
writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE));
drivers/gpu/drm/meson/meson_viu.c
465
writel_relaxed(0x00FF00C0,
drivers/gpu/drm/meson/meson_viu.c
467
writel_relaxed(0x00FF00C0,
drivers/gpu/drm/meson/meson_viu.c
481
writel_relaxed(val, priv->io_base + _REG(VIU_OSD_BLEND_CTRL));
drivers/gpu/drm/meson/meson_viu.c
483
writel_relaxed(OSD_BLEND_PATH_SEL_ENABLE,
drivers/gpu/drm/meson/meson_viu.c
485
writel_relaxed(OSD_BLEND_PATH_SEL_ENABLE,
drivers/gpu/drm/meson/meson_viu.c
487
writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
drivers/gpu/drm/meson/meson_viu.c
488
writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL));
drivers/gpu/drm/meson/meson_viu.c
489
writel_relaxed(0,
drivers/gpu/drm/meson/meson_viu.c
491
writel_relaxed(0,
drivers/gpu/drm/meson/meson_vpp.c
101
writel_relaxed(0x1020080,
drivers/gpu/drm/meson/meson_vpp.c
103
writel_relaxed(0x42020,
drivers/gpu/drm/meson/meson_vpp.c
106
writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL));
drivers/gpu/drm/meson/meson_vpp.c
110
writel_relaxed(VPP_OFIFO_SIZE_DEFAULT,
drivers/gpu/drm/meson/meson_vpp.c
115
writel_relaxed(VPP_POSTBLEND_HOLD_LINES(4) | VPP_PREBLEND_HOLD_LINES(4),
drivers/gpu/drm/meson/meson_vpp.c
134
writel_relaxed(4096,
drivers/gpu/drm/meson/meson_vpp.c
136
writel_relaxed(4096,
drivers/gpu/drm/meson/meson_vpp.c
141
writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
drivers/gpu/drm/meson/meson_vpp.c
142
writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
drivers/gpu/drm/meson/meson_vpp.c
143
writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
drivers/gpu/drm/meson/meson_vpp.c
146
writel_relaxed(VPP_VSC_BANK_LENGTH(4) | VPP_HSC_BANK_LENGTH(4) |
drivers/gpu/drm/meson/meson_vpp.c
151
writel_relaxed(VPP_MINUS_BLACK_LVL_VADJ1_ENABLE,
drivers/gpu/drm/meson/meson_vpp.c
59
writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0,
drivers/gpu/drm/meson/meson_vpp.c
62
writel_relaxed(coefs[i],
drivers/gpu/drm/meson/meson_vpp.c
84
writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0,
drivers/gpu/drm/meson/meson_vpp.c
87
writel_relaxed(coefs[i],
drivers/gpu/drm/meson/meson_vpp.c
95
writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1));
drivers/gpu/drm/meson/meson_vpp.c
99
writel_relaxed(VPP_PPS_DUMMY_DATA_MODE,
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
106
writel_relaxed(val, c->blk_addr + reg_off);
drivers/gpu/drm/msm/msm_mdss.c
181
writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
drivers/gpu/drm/msm/msm_mdss.c
199
writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
drivers/gpu/drm/msm/msm_mdss.c
214
writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
drivers/gpu/drm/msm/msm_mdss.c
217
writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
drivers/gpu/drm/msm/msm_mdss.c
218
writel_relaxed(0, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);
drivers/gpu/drm/msm/msm_mdss.c
221
writel_relaxed(3, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
drivers/gpu/drm/msm/msm_mdss.c
223
writel_relaxed(2, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
drivers/gpu/drm/msm/msm_mdss.c
224
writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);
drivers/gpu/drm/msm/msm_mdss.c
240
writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
drivers/gpu/drm/msm/msm_mdss.c
243
writel_relaxed(5, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
drivers/gpu/drm/msm/msm_mdss.c
245
writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
drivers/gpu/drm/msm/msm_mdss.c
247
writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);
drivers/gpu/drm/omapdrm/dss/pll.c
415
writel_relaxed(l, base + PLL_CONFIGURATION1);
drivers/gpu/drm/omapdrm/dss/pll.c
424
writel_relaxed(l, base + PLL_CONFIGURATION3);
drivers/gpu/drm/omapdrm/dss/pll.c
449
writel_relaxed(l, base + PLL_CONFIGURATION2);
drivers/gpu/drm/omapdrm/dss/pll.c
463
writel_relaxed(1, base + PLL_GO); /* PLL_GO */
drivers/gpu/drm/omapdrm/dss/pll.c
486
writel_relaxed(1, base + PLL_GO); /* PLL_GO */
drivers/gpu/drm/omapdrm/dss/pll.c
508
writel_relaxed(l, base + PLL_CONFIGURATION2);
drivers/gpu/drm/omapdrm/dss/pll.c
534
writel_relaxed(l, base + PLL_CONFIGURATION1);
drivers/gpu/drm/omapdrm/dss/pll.c
548
writel_relaxed(l, base + PLL_CONFIGURATION2);
drivers/gpu/drm/omapdrm/dss/pll.c
552
writel_relaxed(l, base + PLL_CONFIGURATION3);
drivers/gpu/drm/omapdrm/dss/pll.c
557
writel_relaxed(l, base + PLL_CONFIGURATION4);
drivers/gpu/drm/omapdrm/dss/pll.c
559
writel_relaxed(1, base + PLL_GO); /* PLL_GO */
drivers/gpu/drm/omapdrm/dss/video-pll.c
26
writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg)
drivers/gpu/drm/rockchip/rk3066_hdmi.c
76
writel_relaxed(val, hdmi->regs + offset);
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
227
writel_relaxed(v, vop->regs + offset);
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
654
writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
drivers/gpu/drm/rockchip/rockchip_lvds.c
79
writel_relaxed(val, lvds->regs + offset);
drivers/gpu/drm/rockchip/rockchip_lvds.c
82
writel_relaxed(val, lvds->regs + offset + RK3288_LVDS_CH1_OFFSET);
drivers/gpu/drm/stm/ltdc.c
747
writel_relaxed(ldev->irq_status, ldev->regs + LTDC_ICR);
drivers/hsi/controllers/omap_ssi_core.c
150
writel_relaxed(SSI_WAKE(0),
drivers/hsi/controllers/omap_ssi_core.c
153
writel_relaxed(SSI_WAKE(0),
drivers/hsi/controllers/omap_ssi_core.c
174
writel_relaxed(val, omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG);
drivers/hsi/controllers/omap_ssi_core.c
204
writel_relaxed(val, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0));
drivers/hsi/controllers/omap_ssi_core.c
232
writel_relaxed(status_reg, sys + SSI_GDD_MPU_IRQ_STATUS_REG);
drivers/hsi/controllers/omap_ssi_core.c
426
writel_relaxed(SSI_SWRESET, omap_ssi->gdd + SSI_GDD_GRST_REG);
drivers/hsi/controllers/omap_ssi_core.c
431
writel_relaxed(SSI_CLK_AUTOGATING_ON, omap_ssi->sys + SSI_GDD_GCR_REG);
drivers/hsi/controllers/omap_ssi_core.c
583
writel_relaxed(omap_ssi->gdd_gcr, omap_ssi->gdd + SSI_GDD_GCR_REG);
drivers/hsi/controllers/omap_ssi_port.c
1247
writel_relaxed(omap_port->sst.divisor,
drivers/hsi/controllers/omap_ssi_port.c
1282
writel_relaxed(omap_port->sys_mpu_enable,
drivers/hsi/controllers/omap_ssi_port.c
1287
writel_relaxed(omap_port->sst.frame_size, base + SSI_SST_FRAMESIZE_REG);
drivers/hsi/controllers/omap_ssi_port.c
1288
writel_relaxed(omap_port->sst.channels, base + SSI_SST_CHANNELS_REG);
drivers/hsi/controllers/omap_ssi_port.c
1289
writel_relaxed(omap_port->sst.arb_mode, base + SSI_SST_ARBMODE_REG);
drivers/hsi/controllers/omap_ssi_port.c
1293
writel_relaxed(omap_port->ssr.frame_size, base + SSI_SSR_FRAMESIZE_REG);
drivers/hsi/controllers/omap_ssi_port.c
1294
writel_relaxed(omap_port->ssr.channels, base + SSI_SSR_CHANNELS_REG);
drivers/hsi/controllers/omap_ssi_port.c
1295
writel_relaxed(omap_port->ssr.timeout, base + SSI_SSR_TIMEOUT_REG);
drivers/hsi/controllers/omap_ssi_port.c
1304
writel_relaxed(omap_port->sst.mode,
drivers/hsi/controllers/omap_ssi_port.c
1306
writel_relaxed(omap_port->ssr.mode,
drivers/hsi/controllers/omap_ssi_port.c
264
writel_relaxed(d_addr, gdd + SSI_GDD_CDSA_REG(lch));
drivers/hsi/controllers/omap_ssi_port.c
265
writel_relaxed(s_addr, gdd + SSI_GDD_CSSA_REG(lch));
drivers/hsi/controllers/omap_ssi_port.c
272
writel_relaxed(tmp, omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG);
drivers/hsi/controllers/omap_ssi_port.c
470
writel_relaxed(SSI_MODE_SLEEP, sst + SSI_SST_MODE_REG);
drivers/hsi/controllers/omap_ssi_port.c
471
writel_relaxed(SSI_MODE_SLEEP, ssr + SSI_SSR_MODE_REG);
drivers/hsi/controllers/omap_ssi_port.c
475
writel_relaxed(31, sst + SSI_SST_FRAMESIZE_REG);
drivers/hsi/controllers/omap_ssi_port.c
476
writel_relaxed(div, sst + SSI_SST_DIVISOR_REG);
drivers/hsi/controllers/omap_ssi_port.c
477
writel_relaxed(cl->tx_cfg.num_hw_channels, sst + SSI_SST_CHANNELS_REG);
drivers/hsi/controllers/omap_ssi_port.c
478
writel_relaxed(cl->tx_cfg.arb_mode, sst + SSI_SST_ARBMODE_REG);
drivers/hsi/controllers/omap_ssi_port.c
479
writel_relaxed(cl->tx_cfg.mode, sst + SSI_SST_MODE_REG);
drivers/hsi/controllers/omap_ssi_port.c
481
writel_relaxed(31, ssr + SSI_SSR_FRAMESIZE_REG);
drivers/hsi/controllers/omap_ssi_port.c
482
writel_relaxed(cl->rx_cfg.num_hw_channels, ssr + SSI_SSR_CHANNELS_REG);
drivers/hsi/controllers/omap_ssi_port.c
483
writel_relaxed(0, ssr + SSI_SSR_TIMEOUT_REG);
drivers/hsi/controllers/omap_ssi_port.c
488
writel_relaxed(cl->rx_cfg.mode, ssr + SSI_SSR_MODE_REG);
drivers/hsi/controllers/omap_ssi_port.c
540
writel_relaxed(0, sst + SSI_SST_BUFSTATE_REG);
drivers/hsi/controllers/omap_ssi_port.c
541
writel_relaxed(0, sst + SSI_SST_TXSTATE_REG);
drivers/hsi/controllers/omap_ssi_port.c
543
writel_relaxed(0, ssr + SSI_SSR_RXSTATE_REG);
drivers/hsi/controllers/omap_ssi_port.c
544
writel_relaxed(0, ssr + SSI_SSR_BUFSTATE_REG);
drivers/hsi/controllers/omap_ssi_port.c
547
writel_relaxed(err, ssr + SSI_SSR_ERRORACK_REG);
drivers/hsi/controllers/omap_ssi_port.c
549
writel_relaxed(0, ssr + SSI_SSR_BREAK_REG);
drivers/hsi/controllers/omap_ssi_port.c
551
writel_relaxed(0, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0));
drivers/hsi/controllers/omap_ssi_port.c
552
writel_relaxed(0xffffff00,
drivers/hsi/controllers/omap_ssi_port.c
554
writel_relaxed(0, omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG);
drivers/hsi/controllers/omap_ssi_port.c
701
writel_relaxed(tmp, omap_port->sst_base + SSI_SST_BUFSTATE_REG);
drivers/hsi/controllers/omap_ssi_port.c
705
writel_relaxed(tmp, omap_port->ssr_base + SSI_SSR_BUFSTATE_REG);
drivers/hsi/controllers/omap_ssi_port.c
709
writel_relaxed(tmp, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0));
drivers/hsi/controllers/omap_ssi_port.c
710
writel_relaxed(status, omap_ssi->sys +
drivers/hsi/controllers/omap_ssi_port.c
741
writel_relaxed(tmp, omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG);
drivers/hsi/controllers/omap_ssi_port.c
821
writel_relaxed(tmp, omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG);
drivers/hsi/controllers/omap_ssi_port.c
827
writel_relaxed(tmp, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0));
drivers/hsi/controllers/omap_ssi_port.c
829
writel_relaxed(err, omap_port->ssr_base + SSI_SSR_ERRORACK_REG);
drivers/hsi/controllers/omap_ssi_port.c
830
writel_relaxed(SSI_ERROROCCURED,
drivers/hsi/controllers/omap_ssi_port.c
863
writel_relaxed(val, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0));
drivers/hsi/controllers/omap_ssi_port.c
864
writel_relaxed(0, omap_port->ssr_base + SSI_SSR_BREAK_REG);
drivers/hsi/controllers/omap_ssi_port.c
934
writel_relaxed(reg, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0));
drivers/hsi/controllers/omap_ssi_port.c
935
writel_relaxed(val, omap_ssi->sys + SSI_MPU_STATUS_REG(port->num, 0));
drivers/hwmon/as370-hwmon.c
38
writel_relaxed(val, addr);
drivers/hwmon/as370-hwmon.c
40
writel_relaxed(val, addr);
drivers/hwmon/as370-hwmon.c
42
writel_relaxed(val, addr);
drivers/hwmon/as370-hwmon.c
44
writel_relaxed(val, addr);
drivers/hwtracing/coresight/coresight-cpu-debug.c
118
writel_relaxed(0x0, drvdata->base + EDOSLAR);
drivers/hwtracing/coresight/coresight-cpu-debug.c
162
writel_relaxed(edprcr, drvdata->base + EDPRCR);
drivers/hwtracing/coresight/coresight-cpu-debug.c
185
writel_relaxed(edprcr, drvdata->base + EDPRCR);
drivers/hwtracing/coresight/coresight-cpu-debug.c
243
writel_relaxed(save_edprcr, drvdata->base + EDPRCR);
drivers/hwtracing/coresight/coresight-cti-core.c
175
writel_relaxed(0, drvdata->base + CTICONTROL);
drivers/hwtracing/coresight/coresight-cti-core.c
192
writel_relaxed(value, drvdata->base + offset);
drivers/hwtracing/coresight/coresight-cti-core.c
69
writel_relaxed(0, drvdata->base + CTICONTROL);
drivers/hwtracing/coresight/coresight-cti-core.c
73
writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i));
drivers/hwtracing/coresight/coresight-cti-core.c
74
writel_relaxed(config->ctiouten[i],
drivers/hwtracing/coresight/coresight-cti-core.c
79
writel_relaxed(config->ctigate, drvdata->base + CTIGATE);
drivers/hwtracing/coresight/coresight-cti-core.c
80
writel_relaxed(config->asicctl, drvdata->base + ASICCTL);
drivers/hwtracing/coresight/coresight-cti-core.c
81
writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET);
drivers/hwtracing/coresight/coresight-cti-core.c
84
writel_relaxed(1, drvdata->base + CTICONTROL);
drivers/hwtracing/coresight/coresight-etb10.c
112
writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
drivers/hwtracing/coresight/coresight-etb10.c
115
writel_relaxed(0x0, drvdata->base + ETB_RWD_REG);
drivers/hwtracing/coresight/coresight-etb10.c
118
writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
drivers/hwtracing/coresight/coresight-etb10.c
120
writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
drivers/hwtracing/coresight/coresight-etb10.c
122
writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG);
drivers/hwtracing/coresight/coresight-etb10.c
123
writel_relaxed(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER,
drivers/hwtracing/coresight/coresight-etb10.c
126
writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG);
drivers/hwtracing/coresight/coresight-etb10.c
261
writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
drivers/hwtracing/coresight/coresight-etb10.c
264
writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
drivers/hwtracing/coresight/coresight-etb10.c
272
writel_relaxed(0x0, drvdata->base + ETB_CTL_REG);
drivers/hwtracing/coresight/coresight-etb10.c
310
writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
drivers/hwtracing/coresight/coresight-etb10.c
312
writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER);
drivers/hwtracing/coresight/coresight-etb10.c
338
writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
drivers/hwtracing/coresight/coresight-etb10.c
527
writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
drivers/hwtracing/coresight/coresight-etb10.c
555
writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
drivers/hwtracing/coresight/coresight-etb10.c
556
writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
drivers/hwtracing/coresight/coresight-etm.h
263
writel_relaxed(val, drvdata->csa.base + off);
drivers/hwtracing/coresight/coresight-etm3x-core.c
107
writel_relaxed(etmpdcr, drvdata->csa.base + ETMPDCR);
drivers/hwtracing/coresight/coresight-etm3x-core.c
92
writel_relaxed(etmpdcr, drvdata->csa.base + ETMPDCR);
drivers/hwtracing/coresight/coresight-etm4x.h
585
writel_relaxed((val), (csa)->base + (offset)); \
drivers/hwtracing/coresight/coresight-funnel.c
115
writel_relaxed(functl, drvdata->base + FUNNEL_FUNCTL);
drivers/hwtracing/coresight/coresight-funnel.c
72
writel_relaxed(functl, drvdata->base + FUNNEL_FUNCTL);
drivers/hwtracing/coresight/coresight-funnel.c
73
writel_relaxed(drvdata->priority, drvdata->base + FUNNEL_PRICTL);
drivers/hwtracing/coresight/coresight-priv.h
124
writel_relaxed(0x0, addr + CORESIGHT_LAR);
drivers/hwtracing/coresight/coresight-priv.h
131
writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
drivers/hwtracing/coresight/coresight-replicator.c
110
writel_relaxed(id0val, drvdata->base + REPLICATOR_IDFILTER0);
drivers/hwtracing/coresight/coresight-replicator.c
111
writel_relaxed(id1val, drvdata->base + REPLICATOR_IDFILTER1);
drivers/hwtracing/coresight/coresight-replicator.c
166
writel_relaxed(0xff, drvdata->base + reg);
drivers/hwtracing/coresight/coresight-replicator.c
55
writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
drivers/hwtracing/coresight/coresight-replicator.c
56
writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
drivers/hwtracing/coresight/coresight-stm.c
155
writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR);
drivers/hwtracing/coresight/coresight-stm.c
156
writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER);
drivers/hwtracing/coresight/coresight-stm.c
157
writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER);
drivers/hwtracing/coresight/coresight-stm.c
158
writel_relaxed(0x01 | /* Enable HW event tracing */
drivers/hwtracing/coresight/coresight-stm.c
169
writel_relaxed(0x10,
drivers/hwtracing/coresight/coresight-stm.c
171
writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
drivers/hwtracing/coresight/coresight-stm.c
172
writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
drivers/hwtracing/coresight/coresight-stm.c
187
writel_relaxed(0xFFF, drvdata->base + STMSYNCR);
drivers/hwtracing/coresight/coresight-stm.c
188
writel_relaxed((drvdata->traceid << 16 | /* trace id */
drivers/hwtracing/coresight/coresight-stm.c
224
writel_relaxed(0x0, drvdata->base + STMHEMCR);
drivers/hwtracing/coresight/coresight-stm.c
225
writel_relaxed(0x0, drvdata->base + STMHEER);
drivers/hwtracing/coresight/coresight-stm.c
226
writel_relaxed(0x0, drvdata->base + STMHETER);
drivers/hwtracing/coresight/coresight-stm.c
235
writel_relaxed(0x0, drvdata->base + STMSPER);
drivers/hwtracing/coresight/coresight-stm.c
236
writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR);
drivers/hwtracing/coresight/coresight-stm.c
249
writel_relaxed(val, drvdata->base + STMTCSR);
drivers/hwtracing/coresight/coresight-stm.c
327
writel_relaxed(*(u32 *)data, addr);
drivers/hwtracing/coresight/coresight-stm.c
559
writel_relaxed(0x0, drvdata->base + STMSPER);
drivers/hwtracing/coresight/coresight-stm.c
560
writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
drivers/hwtracing/coresight/coresight-stm.c
561
writel_relaxed(stmsper, drvdata->base + STMSPER);
drivers/hwtracing/coresight/coresight-stm.c
604
writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
drivers/hwtracing/coresight/coresight-tmc-core.c
61
writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
drivers/hwtracing/coresight/coresight-tmc-core.c
63
writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
drivers/hwtracing/coresight/coresight-tmc-core.c
75
writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
drivers/hwtracing/coresight/coresight-tmc-core.c
80
writel_relaxed(0x0, drvdata->base + TMC_CTL);
drivers/hwtracing/coresight/coresight-tmc-etf.c
123
writel_relaxed(TMC_MODE_HARDWARE_FIFO, drvdata->base + TMC_MODE);
drivers/hwtracing/coresight/coresight-tmc-etf.c
124
writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI,
drivers/hwtracing/coresight/coresight-tmc-etf.c
126
writel_relaxed(0x0, drvdata->base + TMC_BUFWM);
drivers/hwtracing/coresight/coresight-tmc-etf.c
35
writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
drivers/hwtracing/coresight/coresight-tmc-etf.c
41
writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
drivers/hwtracing/coresight/coresight-tmc-etf.c
43
writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
drivers/hwtracing/coresight/coresight-tmc-etr.c
1074
writel_relaxed(etr_buf->size / 4, drvdata->base + TMC_RSZ);
drivers/hwtracing/coresight/coresight-tmc-etr.c
1075
writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
drivers/hwtracing/coresight/coresight-tmc-etr.c
1091
writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
drivers/hwtracing/coresight/coresight-tmc-etr.c
1102
writel_relaxed(sts, drvdata->base + TMC_STS);
drivers/hwtracing/coresight/coresight-tmc-etr.c
1109
writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
drivers/hwtracing/coresight/coresight-tmc-etr.c
1111
writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
drivers/hwtracing/coresight/coresight-tnoc.c
63
writel_relaxed(drvdata->atid, drvdata->base + TRACE_NOC_XLD);
drivers/hwtracing/coresight/coresight-tnoc.c
66
writel_relaxed(TRACE_NOC_SYNC_INTERVAL, drvdata->base + TRACE_NOC_SYNCR);
drivers/hwtracing/coresight/coresight-tpda.c
158
writel_relaxed(val, drvdata->base + TPDA_CR);
drivers/hwtracing/coresight/coresight-tpda.c
165
writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR);
drivers/hwtracing/coresight/coresight-tpda.c
179
writel_relaxed(val, drvdata->base + TPDA_SYNCR);
drivers/hwtracing/coresight/coresight-tpda.c
194
writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port));
drivers/hwtracing/coresight/coresight-tpda.c
254
writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port));
drivers/hwtracing/coresight/coresight-tpda.c
395
writel_relaxed(val, drvdata->base + TPDA_CR);
drivers/hwtracing/coresight/coresight-tpda.c
508
writel_relaxed(val, drvdata->base + TPDA_FLUSH_CR);
drivers/hwtracing/coresight/coresight-tpdm.c
328
writel_relaxed(val, drvdata->base + TPDM_DSB_TIER);
drivers/hwtracing/coresight/coresight-tpdm.c
336
writel_relaxed(drvdata->dsb->msr[i],
drivers/hwtracing/coresight/coresight-tpdm.c
348
writel_relaxed(drvdata->dsb->edge_ctrl[i],
drivers/hwtracing/coresight/coresight-tpdm.c
351
writel_relaxed(drvdata->dsb->edge_ctrl_mask[i],
drivers/hwtracing/coresight/coresight-tpdm.c
354
writel_relaxed(drvdata->dsb->patt_val[i],
drivers/hwtracing/coresight/coresight-tpdm.c
356
writel_relaxed(drvdata->dsb->patt_mask[i],
drivers/hwtracing/coresight/coresight-tpdm.c
358
writel_relaxed(drvdata->dsb->trig_patt[i],
drivers/hwtracing/coresight/coresight-tpdm.c
360
writel_relaxed(drvdata->dsb->trig_patt_mask[i],
drivers/hwtracing/coresight/coresight-tpdm.c
377
writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
drivers/hwtracing/coresight/coresight-tpdm.c
402
writel_relaxed(val, drvdata->base + TPDM_CMB_TIER);
drivers/hwtracing/coresight/coresight-tpdm.c
410
writel_relaxed(drvdata->cmb->msr[i],
drivers/hwtracing/coresight/coresight-tpdm.c
423
writel_relaxed(drvdata->cmb->patt_val[i],
drivers/hwtracing/coresight/coresight-tpdm.c
425
writel_relaxed(drvdata->cmb->patt_mask[i],
drivers/hwtracing/coresight/coresight-tpdm.c
427
writel_relaxed(drvdata->cmb->trig_patt[i],
drivers/hwtracing/coresight/coresight-tpdm.c
429
writel_relaxed(drvdata->cmb->trig_patt_mask[i],
drivers/hwtracing/coresight/coresight-tpdm.c
460
writel_relaxed(val, drvdata->base + TPDM_CMB_CR);
drivers/hwtracing/coresight/coresight-tpdm.c
519
writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
drivers/hwtracing/coresight/coresight-tpdm.c
532
writel_relaxed(val, drvdata->base + TPDM_CMB_CR);
drivers/hwtracing/coresight/coresight-tpdm.c
677
writel_relaxed(0x1, drvdata->base + TPDM_ITCNTRL);
drivers/hwtracing/coresight/coresight-tpdm.c
680
writel_relaxed(val, drvdata->base + TPDM_ITATBCNTRL);
drivers/hwtracing/coresight/coresight-tpdm.c
682
writel_relaxed(0, drvdata->base + TPDM_ITCNTRL);
drivers/hwtracing/intel_th/sth.c
49
writel_relaxed(*(u32 *)payload, dest);
drivers/i2c/busses/i2c-at91-core.c
35
writel_relaxed(val, dev->base + reg);
drivers/i2c/busses/i2c-cadence.c
136
#define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
drivers/i2c/busses/i2c-hisi.c
116
writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK);
drivers/i2c/busses/i2c-hisi.c
121
writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK);
drivers/i2c/busses/i2c-hisi.c
126
writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR);
drivers/i2c/busses/i2c-hisi.c
131
writel_relaxed(mask, ctlr->iobase + HISI_I2C_TX_INT_CLR);
drivers/i2c/busses/i2c-hix5hd2.c
106
writel_relaxed(I2C_CLEAR_ALL, priv->regs + HIX5I2C_ICR);
drivers/i2c/busses/i2c-hix5hd2.c
111
writel_relaxed(0, priv->regs + HIX5I2C_CTRL);
drivers/i2c/busses/i2c-hix5hd2.c
116
writel_relaxed(I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL,
drivers/i2c/busses/i2c-hix5hd2.c
127
writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL);
drivers/i2c/busses/i2c-hix5hd2.c
132
writel_relaxed(scl, priv->regs + HIX5I2C_SCL_H);
drivers/i2c/busses/i2c-hix5hd2.c
133
writel_relaxed(scl, priv->regs + HIX5I2C_SCL_L);
drivers/i2c/busses/i2c-hix5hd2.c
136
writel_relaxed(val, priv->regs + HIX5I2C_CTRL);
drivers/i2c/busses/i2c-hix5hd2.c
191
writel_relaxed(I2C_STOP, priv->regs + HIX5I2C_COM);
drivers/i2c/busses/i2c-hix5hd2.c
201
writel_relaxed(I2C_READ | I2C_NO_ACK, priv->regs + HIX5I2C_COM);
drivers/i2c/busses/i2c-hix5hd2.c
204
writel_relaxed(I2C_READ, priv->regs + HIX5I2C_COM);
drivers/i2c/busses/i2c-hix5hd2.c
216
writel_relaxed(data, priv->regs + HIX5I2C_TXR);
drivers/i2c/busses/i2c-hix5hd2.c
217
writel_relaxed(I2C_WRITE, priv->regs + HIX5I2C_COM);
drivers/i2c/busses/i2c-hix5hd2.c
307
writel_relaxed(i2c_8bit_addr_from_msg(priv->msg),
drivers/i2c/busses/i2c-hix5hd2.c
310
writel_relaxed(I2C_WRITE | I2C_START, priv->regs + HIX5I2C_COM);
drivers/i2c/busses/i2c-hix5hd2.c
99
writel_relaxed(val, priv->regs + HIX5I2C_ICR);
drivers/i2c/busses/i2c-qcom-geni.c
211
writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
drivers/i2c/busses/i2c-qcom-geni.c
214
writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG);
drivers/i2c/busses/i2c-qcom-geni.c
219
writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
drivers/i2c/busses/i2c-qcom-geni.c
308
writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
drivers/i2c/busses/i2c-qcom-geni.c
339
writel_relaxed(val, base + SE_GENI_TX_FIFOn);
drivers/i2c/busses/i2c-qcom-geni.c
342
writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
drivers/i2c/busses/i2c-qcom-geni.c
349
writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR);
drivers/i2c/busses/i2c-qcom-geni.c
352
writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR);
drivers/i2c/busses/i2c-qcom-geni.c
354
writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR);
drivers/i2c/busses/i2c-qcom-geni.c
392
writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST);
drivers/i2c/busses/i2c-qcom-geni.c
407
writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST);
drivers/i2c/busses/i2c-qcom-geni.c
457
writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN);
drivers/i2c/busses/i2c-qcom-geni.c
496
writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN);
drivers/i2c/busses/i2c-qcom-geni.c
510
writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG);
drivers/i2c/busses/i2c-st.c
201
writel_relaxed(readl_relaxed(reg) | mask, reg);
drivers/i2c/busses/i2c-st.c
206
writel_relaxed(readl_relaxed(reg) & ~mask, reg);
drivers/i2c/busses/i2c-st.c
282
writel_relaxed(val, i2c_dev->base + SSC_CLR);
drivers/i2c/busses/i2c-st.c
286
writel_relaxed(val, i2c_dev->base + SSC_CTL);
drivers/i2c/busses/i2c-st.c
293
writel_relaxed(val, i2c_dev->base + SSC_BRG);
drivers/i2c/busses/i2c-st.c
296
writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG);
drivers/i2c/busses/i2c-st.c
299
writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C);
drivers/i2c/busses/i2c-st.c
303
writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD);
drivers/i2c/busses/i2c-st.c
307
writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP);
drivers/i2c/busses/i2c-st.c
311
writel_relaxed(val, i2c_dev->base + SSC_START_HOLD);
drivers/i2c/busses/i2c-st.c
315
writel_relaxed(val, i2c_dev->base + SSC_DATA_SETUP);
drivers/i2c/busses/i2c-st.c
319
writel_relaxed(val, i2c_dev->base + SSC_STOP_SETUP);
drivers/i2c/busses/i2c-st.c
323
writel_relaxed(val, i2c_dev->base + SSC_BUS_FREE);
drivers/i2c/busses/i2c-st.c
327
writel_relaxed(val, i2c_dev->base + SSC_PRSCALER);
drivers/i2c/busses/i2c-st.c
328
writel_relaxed(val, i2c_dev->base + SSC_PRSCALER_DATAOUT);
drivers/i2c/busses/i2c-st.c
332
writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH);
drivers/i2c/busses/i2c-st.c
336
writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH_DATAOUT);
drivers/i2c/busses/i2c-st.c
354
writel_relaxed(0, i2c_dev->base + SSC_IEN);
drivers/i2c/busses/i2c-st.c
364
writel_relaxed(0, i2c_dev->base + SSC_TBUF);
drivers/i2c/busses/i2c-st.c
404
writel_relaxed(tbuf | 1, i2c_dev->base + SSC_TBUF);
drivers/i2c/busses/i2c-st.c
546
writel_relaxed(ien, i2c_dev->base + SSC_IEN);
drivers/i2c/busses/i2c-st.c
587
writel_relaxed(0, i2c_dev->base + SSC_IEN);
drivers/i2c/busses/i2c-st.c
592
writel_relaxed(SSC_CLR_NACK, i2c_dev->base + SSC_CLR);
drivers/i2c/busses/i2c-st.c
601
writel_relaxed(it, i2c_dev->base + SSC_IEN);
drivers/i2c/busses/i2c-st.c
608
writel_relaxed(SSC_CLR_SSCARBL, i2c_dev->base + SSC_CLR);
drivers/i2c/busses/i2c-st.c
611
writel_relaxed(it, i2c_dev->base + SSC_IEN);
drivers/i2c/busses/i2c-st.c
672
writel_relaxed(it, i2c_dev->base + SSC_IEN);
drivers/i2c/busses/i2c-st.c
692
writel_relaxed(SSC_CLR_SSCSTOP | SSC_CLR_REPSTRT,
drivers/i2c/busses/i2c-stm32f4.c
136
writel_relaxed(readl_relaxed(reg) | mask, reg);
drivers/i2c/busses/i2c-stm32f4.c
141
writel_relaxed(readl_relaxed(reg) & ~mask, reg);
drivers/i2c/busses/i2c-stm32f4.c
186
writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2);
drivers/i2c/busses/i2c-stm32f4.c
221
writel_relaxed(STM32F4_I2C_TRISE_VALUE(trise),
drivers/i2c/busses/i2c-stm32f4.c
273
writel_relaxed(ccr, i2c_dev->base + STM32F4_I2C_CCR);
drivers/i2c/busses/i2c-stm32f4.c
293
writel_relaxed(STM32F4_I2C_CR1_PE, i2c_dev->base + STM32F4_I2C_CR1);
drivers/i2c/busses/i2c-stm32f4.c
322
writel_relaxed(byte, i2c_dev->base + STM32F4_I2C_DR);
drivers/i2c/busses/i2c-stm32f4.c
508
writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
drivers/i2c/busses/i2c-stm32f4.c
516
writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
drivers/i2c/busses/i2c-stm32f4.c
529
writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
drivers/i2c/busses/i2c-stm32f4.c
544
writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
drivers/i2c/busses/i2c-stm32f4.c
595
writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2);
drivers/i2c/busses/i2c-stm32f4.c
640
writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
drivers/i2c/busses/i2c-stm32f4.c
654
writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
drivers/i2c/busses/i2c-stm32f4.c
661
writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
drivers/i2c/busses/i2c-stm32f7.c
1145
writel_relaxed(cr1, base + STM32F7_I2C_CR1);
drivers/i2c/busses/i2c-stm32f7.c
1146
writel_relaxed(cr2, base + STM32F7_I2C_CR2);
drivers/i2c/busses/i2c-stm32f7.c
1231
writel_relaxed(cr1, base + STM32F7_I2C_CR1);
drivers/i2c/busses/i2c-stm32f7.c
1232
writel_relaxed(cr2, base + STM32F7_I2C_CR2);
drivers/i2c/busses/i2c-stm32f7.c
1323
writel_relaxed(value, base + STM32F7_I2C_TXDR);
drivers/i2c/busses/i2c-stm32f7.c
1364
writel_relaxed(mask, base + STM32F7_I2C_ICR);
drivers/i2c/busses/i2c-stm32f7.c
1460
writel_relaxed(val, base + STM32F7_I2C_TXDR);
drivers/i2c/busses/i2c-stm32f7.c
1476
writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
drivers/i2c/busses/i2c-stm32f7.c
1486
writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
drivers/i2c/busses/i2c-stm32f7.c
1504
writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
drivers/i2c/busses/i2c-stm32f7.c
1529
writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
drivers/i2c/busses/i2c-stm32f7.c
1537
writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
drivers/i2c/busses/i2c-stm32f7.c
1543
writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
drivers/i2c/busses/i2c-stm32f7.c
1549
writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);
drivers/i2c/busses/i2c-stm32f7.c
1629
writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
drivers/i2c/busses/i2c-stm32f7.c
1675
writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
drivers/i2c/busses/i2c-stm32f7.c
1749
writel_relaxed(STM32F7_I2C_ISR_TXE,
drivers/i2c/busses/i2c-stm32f7.c
1828
writel_relaxed(STM32F7_I2C_ISR_TXE,
drivers/i2c/busses/i2c-stm32f7.c
1941
writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
drivers/i2c/busses/i2c-stm32f7.c
1956
writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
drivers/i2c/busses/i2c-stm32f7.c
2455
writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
drivers/i2c/busses/i2c-stm32f7.c
2456
writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
drivers/i2c/busses/i2c-stm32f7.c
2461
writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
drivers/i2c/busses/i2c-stm32f7.c
2462
writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
drivers/i2c/busses/i2c-stm32f7.c
2463
writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
drivers/i2c/busses/i2c-stm32f7.c
436
writel_relaxed(readl_relaxed(reg) | mask, reg);
drivers/i2c/busses/i2c-stm32f7.c
441
writel_relaxed(readl_relaxed(reg) & ~mask, reg);
drivers/i2c/busses/i2c-stm32f7.c
767
writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
drivers/i2c/busses/i2c-stm32f7.c
830
writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
drivers/i2c/busses/i2c-stm32f7.c
853
writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
drivers/i2c/busses/i2c-stm32f7.c
978
writel_relaxed(cr1, base + STM32F7_I2C_CR1);
drivers/i2c/busses/i2c-stm32f7.c
979
writel_relaxed(cr2, base + STM32F7_I2C_CR2);
drivers/i2c/busses/i2c-tegra.c
334
writel_relaxed(val, i2c_dev->base + reg);
drivers/i2c/busses/i2c-tegra.c
358
writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
drivers/iio/adc/at91-sama5d2_adc.c
446
writel_relaxed(val, (st)->base + (st)->soc_info.platform->layout->reg)
drivers/iio/adc/at91_adc.c
141
(writel_relaxed(val, st->reg_base + reg))
drivers/iio/adc/ep93xx_adc.c
97
writel_relaxed(0xAA, priv->base + EP93XX_ADC_SW_LOCK);
drivers/iio/adc/ep93xx_adc.c
98
writel_relaxed(channel->address,
drivers/iio/adc/rockchip_saradc.c
102
writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC);
drivers/iio/adc/rockchip_saradc.c
103
writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC);
drivers/iio/adc/rockchip_saradc.c
106
writel_relaxed(val, info->regs + SARADC2_END_INT_EN);
drivers/iio/adc/rockchip_saradc.c
129
writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST);
drivers/iio/adc/rockchip_saradc.c
143
writel_relaxed(0, info->regs + SARADC_CTRL);
drivers/iio/adc/rockchip_saradc.c
89
writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
drivers/iio/adc/stm32-adc-core.c
169
writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
drivers/iio/adc/stm32-adc-core.c
301
writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
drivers/iio/adc/stm32-adc-core.c
570
writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr);
drivers/iio/adc/stm32-adc.c
619
writel_relaxed(val, adc->common->base + adc->offset + reg);
drivers/iio/adc/stm32-adc.c
634
writel_relaxed(readl_relaxed(adc->common->base + reg) | bits,
drivers/iio/adc/stm32-adc.c
651
writel_relaxed(readl_relaxed(adc->common->base + reg) & ~bits,
drivers/infiniband/hw/mlx4/qp.c
3831
writel_relaxed(qp->doorbell_qpn,
drivers/input/keyboard/spear-keyboard.c
119
writel_relaxed(val, kbd->io_base + MODE_CTL_REG);
drivers/input/keyboard/spear-keyboard.c
120
writel_relaxed(1, kbd->io_base + STATUS_REG);
drivers/input/keyboard/spear-keyboard.c
125
writel_relaxed(val, kbd->io_base + MODE_CTL_REG);
drivers/input/keyboard/spear-keyboard.c
138
writel_relaxed(val, kbd->io_base + MODE_CTL_REG);
drivers/input/keyboard/spear-keyboard.c
259
writel_relaxed(val, kbd->io_base + MODE_CTL_REG);
drivers/input/keyboard/spear-keyboard.c
263
writel_relaxed(mode_ctl_reg & ~MODE_CTL_START_SCAN,
drivers/input/keyboard/spear-keyboard.c
299
writel_relaxed(kbd->mode_ctl_reg, kbd->io_base + MODE_CTL_REG);
drivers/input/keyboard/spear-keyboard.c
95
writel_relaxed(0, kbd->io_base + STATUS_REG);
drivers/input/serio/sa1111ps2.c
102
writel_relaxed(ps2if->buf[ps2if->tail], ps2if->base + PS2DATA);
drivers/input/serio/sa1111ps2.c
124
writel_relaxed(val, ps2if->base + PS2DATA);
drivers/input/serio/sa1111ps2.c
170
writel_relaxed(PS2CR_ENA, ps2if->base + PS2CR);
drivers/input/serio/sa1111ps2.c
178
writel_relaxed(0, ps2if->base + PS2CR);
drivers/input/serio/sa1111ps2.c
208
writel_relaxed(PS2CR_ENA | mask, ps2if->base + PS2CR);
drivers/input/serio/sa1111ps2.c
243
writel_relaxed(0, ps2if->base + PS2CR);
drivers/input/serio/sa1111ps2.c
308
writel_relaxed(0, ps2if->base + PS2CLKDIV);
drivers/input/serio/sa1111ps2.c
309
writel_relaxed(127, ps2if->base + PS2PRECNT);
drivers/input/serio/sa1111ps2.c
69
writel_relaxed(PS2STAT_STP, ps2if->base + PS2STAT);
drivers/interconnect/qcom/osm-l3.c
131
writel_relaxed(index, qp->base + qp->reg_perf_state);
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
168
writel_relaxed(q->llq.cons, q->cons_reg);
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
3967
writel_relaxed(val, smmu->base + reg_off);
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
3985
writel_relaxed(reg | GBPA_UPDATE, gbpa);
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
4012
writel_relaxed(msg->data, smmu->base + cfg[1]);
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
4013
writel_relaxed(ARM_SMMU_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]);
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
4172
writel_relaxed(reg, smmu->base + ARM_SMMU_STRTAB_BASE_CFG);
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
4199
writel_relaxed(reg, smmu->base + ARM_SMMU_CR1);
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
4207
writel_relaxed(reg, smmu->base + ARM_SMMU_CR2);
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
4214
writel_relaxed(smmu->cmdq.q.llq.prod, smmu->base + ARM_SMMU_CMDQ_PROD);
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
4215
writel_relaxed(smmu->cmdq.q.llq.cons, smmu->base + ARM_SMMU_CMDQ_CONS);
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
4240
writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD);
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
4241
writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS);
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
4255
writel_relaxed(smmu->priq.q.llq.prod,
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
4257
writel_relaxed(smmu->priq.q.llq.cons,
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
885
writel_relaxed(prod, cmdq->q.prod_reg);
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
457
writel_relaxed(0, REG_VCMDQ_PAGE0(vcmdq, PROD));
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
458
writel_relaxed(0, REG_VCMDQ_PAGE0(vcmdq, CONS));
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
605
writel_relaxed(regval,
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
41
writel_relaxed(val, arm_smmu_page(smmu, page) + offset);
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
144
writel_relaxed(val, reg);
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
171
writel_relaxed(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
214
writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR);
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
72
writel_relaxed(val, reg);
drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
141
writel_relaxed(val, tbu->base + DEBUG_SID_HALT_REG);
drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
169
writel_relaxed(val, tbu->base + DEBUG_SID_HALT_REG);
drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
196
writel_relaxed(val, tbu->base + DEBUG_SID_HALT_REG);
drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
258
writel_relaxed(val, tbu->base + DEBUG_SID_HALT_REG);
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
212
writel_relaxed(lower_32_bits(page_addr),
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
214
writel_relaxed(upper_32_bits(page_addr),
drivers/iommu/arm/arm-smmu/arm-smmu.h
497
writel_relaxed(val, arm_smmu_page(smmu, page) + offset);
drivers/iommu/arm/arm-smmu/qcom_iommu.c
863
writel_relaxed(0xffffffff, qcom_iommu->local_base + SMMU_INTR_SEL_NS);
drivers/iommu/arm/arm-smmu/qcom_iommu.c
93
writel_relaxed(val, ctx->base + reg);
drivers/iommu/mtk_iommu.c
1095
writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG);
drivers/iommu/mtk_iommu.c
1104
writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG);
drivers/iommu/mtk_iommu.c
1107
writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS);
drivers/iommu/mtk_iommu.c
1109
writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS);
drivers/iommu/mtk_iommu.c
1115
writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL);
drivers/iommu/mtk_iommu.c
1128
writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL);
drivers/iommu/mtk_iommu.c
1137
writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0);
drivers/iommu/mtk_iommu.c
1146
writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL);
drivers/iommu/mtk_iommu.c
1153
writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR);
drivers/iommu/mtk_iommu.c
1157
writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR);
drivers/iommu/mtk_iommu.c
1536
writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);
drivers/iommu/mtk_iommu.c
1537
writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
drivers/iommu/mtk_iommu.c
1538
writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
drivers/iommu/mtk_iommu.c
1539
writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
drivers/iommu/mtk_iommu.c
1540
writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
drivers/iommu/mtk_iommu.c
1546
writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0);
drivers/iommu/mtk_iommu.c
1547
writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL);
drivers/iommu/mtk_iommu.c
1548
writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
drivers/iommu/mtk_iommu.c
398
writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg);
drivers/iommu/mtk_iommu.c
399
writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE);
drivers/iommu/mtk_iommu.c
443
writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
drivers/iommu/mtk_iommu.c
446
writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A);
drivers/iommu/mtk_iommu.c
447
writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1),
drivers/iommu/mtk_iommu.c
449
writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE);
drivers/iommu/mtk_iommu.c
456
writel_relaxed(0, base + REG_MMU_CPE_DONE);
drivers/iommu/mtk_iommu.c
534
writel_relaxed(regval, base + REG_MMU_INT_CONTROL0);
drivers/iommu/mtk_iommu_v1.c
173
writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
drivers/iommu/mtk_iommu_v1.c
175
writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
drivers/iommu/mtk_iommu_v1.c
185
writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
drivers/iommu/mtk_iommu_v1.c
187
writel_relaxed(iova & F_MMU_FAULT_VA_MSK,
drivers/iommu/mtk_iommu_v1.c
189
writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK,
drivers/iommu/mtk_iommu_v1.c
191
writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
drivers/iommu/mtk_iommu_v1.c
201
writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
drivers/iommu/mtk_iommu_v1.c
235
writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
drivers/iommu/mtk_iommu_v1.c
552
writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
drivers/iommu/mtk_iommu_v1.c
562
writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
drivers/iommu/mtk_iommu_v1.c
565
writel_relaxed(data->protect_base,
drivers/iommu/mtk_iommu_v1.c
568
writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM);
drivers/iommu/mtk_iommu_v1.c
572
writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
drivers/iommu/mtk_iommu_v1.c
754
writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR);
drivers/iommu/mtk_iommu_v1.c
755
writel_relaxed(reg->standard_axi_mode,
drivers/iommu/mtk_iommu_v1.c
757
writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM);
drivers/iommu/mtk_iommu_v1.c
758
writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
drivers/iommu/mtk_iommu_v1.c
759
writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL);
drivers/iommu/mtk_iommu_v1.c
760
writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR);
drivers/iommu/riscv/iommu.h
76
writel_relaxed((val), (iommu)->reg + (addr))
drivers/iommu/sprd-iommu.c
94
writel_relaxed(val, sdev->base + reg);
drivers/irqchip/exynos-combiner.c
133
writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
drivers/irqchip/exynos-combiner.c
233
writel_relaxed(combiner_data[i].irq_mask,
drivers/irqchip/exynos-combiner.c
235
writel_relaxed(combiner_data[i].pm_save,
drivers/irqchip/exynos-combiner.c
55
writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
drivers/irqchip/exynos-combiner.c
62
writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_SET);
drivers/irqchip/irq-aclint-sswi.c
29
writel_relaxed(0x0, this_cpu_read(sswi_cpu_regs));
drivers/irqchip/irq-al-fic.c
123
writel_relaxed(BIT(data->hwirq), fic->base + AL_FIC_SET_CAUSE);
drivers/irqchip/irq-al-fic.c
206
writel_relaxed(0xFFFFFFFF, fic->base + AL_FIC_MASK);
drivers/irqchip/irq-al-fic.c
209
writel_relaxed(0, fic->base + AL_FIC_CAUSE);
drivers/irqchip/irq-al-fic.c
211
writel_relaxed(control, fic->base + AL_FIC_CONTROL);
drivers/irqchip/irq-al-fic.c
60
writel_relaxed(control, fic->base + AL_FIC_CONTROL);
drivers/irqchip/irq-apple-aic.c
345
writel_relaxed(val, ic->base + reg);
drivers/irqchip/irq-bcm2835.c
167
writel_relaxed(reg, intc.disable[b]);
drivers/irqchip/irq-bcm2835.c
175
writel_relaxed(0, base + REG_FIQ_CONTROL);
drivers/irqchip/irq-bcm2835.c
94
writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
drivers/irqchip/irq-bcm2835.c
99
writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
drivers/irqchip/irq-bcm2836.c
177
writel_relaxed(BIT(d->hwirq),
drivers/irqchip/irq-bcm2836.c
194
writel_relaxed(BIT(d->hwirq), mailbox0_base + 16 * cpu);
drivers/irqchip/irq-clps711x.c
106
writel_relaxed(tmp, intmr);
drivers/irqchip/irq-clps711x.c
117
writel_relaxed(tmp, intmr);
drivers/irqchip/irq-clps711x.c
145
writel_relaxed(0, clps711x_intc->base + clps711x_irqs[hw].eoi);
drivers/irqchip/irq-clps711x.c
176
writel_relaxed(0, clps711x_intc->intmr[0]);
drivers/irqchip/irq-clps711x.c
177
writel_relaxed(0, clps711x_intc->intmr[1]);
drivers/irqchip/irq-clps711x.c
178
writel_relaxed(0, clps711x_intc->intmr[2]);
drivers/irqchip/irq-clps711x.c
95
writel_relaxed(0, clps711x_intc->base + clps711x_irqs[hwirq].eoi);
drivers/irqchip/irq-csky-mpintc.c
101
writel_relaxed(d->hwirq, reg_base + INTCL_CACR);
drivers/irqchip/irq-csky-mpintc.c
156
writel_relaxed(cpu, INTCG_base + INTCG_CIDSTR + offset);
drivers/irqchip/irq-csky-mpintc.c
221
writel_relaxed((*cpumask_bits(mask)) << 8 | IPI_IRQ,
drivers/irqchip/irq-csky-mpintc.c
255
writel_relaxed(BIT(0), INTCG_base + INTCG_ICTLR);
drivers/irqchip/irq-csky-mpintc.c
266
writel_relaxed(BIT(0), per_cpu(intcl_reg, cpu) + INTCL_PICTLR);
drivers/irqchip/irq-csky-mpintc.c
68
writel_relaxed(tmp | TRIG_VAL(trigger, irq), TRIG_BASE(irq));
drivers/irqchip/irq-csky-mpintc.c
87
writel_relaxed(d->hwirq, reg_base + INTCL_SENR);
drivers/irqchip/irq-csky-mpintc.c
94
writel_relaxed(d->hwirq, reg_base + INTCL_CENR);
drivers/irqchip/irq-davinci-cp-intc.c
51
writel_relaxed(value, davinci_cp_intc_base + offset);
drivers/irqchip/irq-dw-apb-ictl.c
105
writel_relaxed(~0, gc->reg_base + ct->regs.enable);
drivers/irqchip/irq-dw-apb-ictl.c
106
writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask);
drivers/irqchip/irq-dw-apb-ictl.c
164
writel_relaxed(~0, iobase + APB_INT_MASK_L);
drivers/irqchip/irq-dw-apb-ictl.c
165
writel_relaxed(~0, iobase + APB_INT_MASK_H);
drivers/irqchip/irq-dw-apb-ictl.c
166
writel_relaxed(~0, iobase + APB_INT_ENABLE_L);
drivers/irqchip/irq-dw-apb-ictl.c
167
writel_relaxed(~0, iobase + APB_INT_ENABLE_H);
drivers/irqchip/irq-gic-common.c
106
writel_relaxed(REPEAT_BYTE_U32(priority),
drivers/irqchip/irq-gic-common.c
114
writel_relaxed(GICD_INT_EN_CLR_X32,
drivers/irqchip/irq-gic-common.c
116
writel_relaxed(GICD_INT_EN_CLR_X32,
drivers/irqchip/irq-gic-common.c
130
writel_relaxed(GICD_INT_EN_CLR_X32,
drivers/irqchip/irq-gic-common.c
132
writel_relaxed(GICD_INT_EN_CLR_X32,
drivers/irqchip/irq-gic-common.c
140
writel_relaxed(REPEAT_BYTE_U32(priority),
drivers/irqchip/irq-gic-common.c
82
writel_relaxed(val, base + confoff);
drivers/irqchip/irq-gic-common.c
99
writel_relaxed(GICD_INT_ACTLOW_LVLTRIG,
drivers/irqchip/irq-gic-v3-its.c
1149
writel_relaxed(wr, its->base + GITS_CWRITER);
drivers/irqchip/irq-gic-v3-its.c
3240
writel_relaxed(val, rbase + GICR_CTLR);
drivers/irqchip/irq-gic-v3-its.c
4433
writel_relaxed(vpe->vpe_id, base + GICR_VSGIR);
drivers/irqchip/irq-gic-v3-its.c
4765
writel_relaxed(val, base + GITS_CTLR);
drivers/irqchip/irq-gic-v3-its.c
5013
writel_relaxed(its->ctlr_save, base + GITS_CTLR);
drivers/irqchip/irq-gic-v3-its.c
5026
writel_relaxed(its->ctlr_save, base + GITS_CTLR);
drivers/irqchip/irq-gic-v3-its.c
5080
writel_relaxed(its->ctlr_save, base + GITS_CTLR);
drivers/irqchip/irq-gic-v3-its.c
5219
writel_relaxed(ctlr, its->base + GITS_CTLR);
drivers/irqchip/irq-gic-v3-its.c
5325
writel_relaxed(ctlr, its->base + GITS_CTLR);
drivers/irqchip/irq-gic-v3-its.c
5389
writel_relaxed(val, rbase + GICR_CTLR);
drivers/irqchip/irq-gic-v3.c
1294
writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8);
drivers/irqchip/irq-gic-v3.c
181
writel_relaxed(val, gic_data.dist_base + GICD_CTLR);
drivers/irqchip/irq-gic-v3.c
384
writel_relaxed(val, rbase + GICR_WAKER);
drivers/irqchip/irq-gic-v3.c
483
writel_relaxed(mask, base + offset + (index / 32) * 4);
drivers/irqchip/irq-gic-v3.c
931
writel_relaxed(0, base + GICD_CTLR);
drivers/irqchip/irq-gic-v3.c
941
writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
drivers/irqchip/irq-gic-v3.c
945
writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8);
drivers/irqchip/irq-gic-v3.c
946
writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8);
drivers/irqchip/irq-gic-v3.c
950
writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8);
drivers/irqchip/irq-gic-v3.c
953
writel_relaxed(0, base + GICD_ICFGRnE + i / 4);
drivers/irqchip/irq-gic-v3.c
956
writel_relaxed(REPEAT_BYTE_U32(dist_prio_irq),
drivers/irqchip/irq-gic-v3.c
969
writel_relaxed(val, base + GICD_CTLR);
drivers/irqchip/irq-gic-v5-irs.c
38
writel_relaxed(val, irs_data->irs_base + reg_offset);
drivers/irqchip/irq-gic-v5-its.c
55
writel_relaxed(val, its_node->its_base + reg_offset);
drivers/irqchip/irq-gic-v5-iwb.c
31
writel_relaxed(val, iwb_node->iwb_base + reg_offset);
drivers/irqchip/irq-gic.c
1014
writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
drivers/irqchip/irq-gic.c
1017
writel_relaxed((1 << (new_cpu_id + 16)) | j,
drivers/irqchip/irq-gic.c
183
writel_relaxed(mask, gic_dist_base(d) + offset + (irqd_to_hwirq(d) / 32) * 4);
drivers/irqchip/irq-gic.c
225
writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_EOI);
drivers/irqchip/irq-gic.c
239
writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
drivers/irqchip/irq-gic.c
348
writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
drivers/irqchip/irq-gic.c
452
writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4);
drivers/irqchip/irq-gic.c
460
writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
drivers/irqchip/irq-gic.c
471
writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
drivers/irqchip/irq-gic.c
480
writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
drivers/irqchip/irq-gic.c
484
writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
drivers/irqchip/irq-gic.c
521
writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
drivers/irqchip/irq-gic.c
538
writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
drivers/irqchip/irq-gic.c
604
writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
drivers/irqchip/irq-gic.c
607
writel_relaxed(gic->saved_spi_conf[i],
drivers/irqchip/irq-gic.c
611
writel_relaxed(REPEAT_BYTE_U32(GICD_INT_DEF_PRI),
drivers/irqchip/irq-gic.c
615
writel_relaxed(gic->saved_spi_target[i],
drivers/irqchip/irq-gic.c
619
writel_relaxed(GICD_INT_EN_CLR_X32,
drivers/irqchip/irq-gic.c
621
writel_relaxed(gic->saved_spi_enable[i],
drivers/irqchip/irq-gic.c
626
writel_relaxed(GICD_INT_EN_CLR_X32,
drivers/irqchip/irq-gic.c
628
writel_relaxed(gic->saved_spi_active[i],
drivers/irqchip/irq-gic.c
632
writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
drivers/irqchip/irq-gic.c
683
writel_relaxed(GICD_INT_EN_CLR_X32,
drivers/irqchip/irq-gic.c
685
writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
drivers/irqchip/irq-gic.c
690
writel_relaxed(GICD_INT_EN_CLR_X32,
drivers/irqchip/irq-gic.c
692
writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
drivers/irqchip/irq-gic.c
697
writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
drivers/irqchip/irq-gic.c
700
writel_relaxed(REPEAT_BYTE_U32(GICD_INT_DEF_PRI),
drivers/irqchip/irq-gic.c
703
writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
drivers/irqchip/irq-gic.c
788
writel_relaxed(val, addr);
drivers/irqchip/irq-gic.c
827
writel_relaxed(2 << 24 | d->hwirq,
drivers/irqchip/irq-gic.c
845
writel_relaxed(map << 16 | d->hwirq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
drivers/irqchip/irq-gic.c
925
writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
drivers/irqchip/irq-gic.c
993
writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
drivers/irqchip/irq-hip04.c
106
writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_SET +
drivers/irqchip/irq-hip04.c
113
writel_relaxed(hip04_irq(d), hip04_cpu_base(d) + GIC_CPU_EOI);
drivers/irqchip/irq-hip04.c
167
writel_relaxed(val | bit, reg);
drivers/irqchip/irq-hip04.c
193
writel_relaxed(map << 8 | d->hwirq, hip04_data.dist_base + GIC_DIST_SOFTINT);
drivers/irqchip/irq-hip04.c
253
writel_relaxed(0, base + GIC_DIST_CTRL);
drivers/irqchip/irq-hip04.c
261
writel_relaxed(cpumask, base + GIC_DIST_TARGET + ((i * 2) & ~3));
drivers/irqchip/irq-hip04.c
265
writel_relaxed(1, base + GIC_DIST_CTRL);
drivers/irqchip/irq-hip04.c
292
writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
drivers/irqchip/irq-hip04.c
293
writel_relaxed(1, base + GIC_CPU_CTRL);
drivers/irqchip/irq-hip04.c
96
writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_CLEAR +
drivers/irqchip/irq-imx-gpcv2.c
109
writel_relaxed(val, reg);
drivers/irqchip/irq-imx-gpcv2.c
125
writel_relaxed(val, reg);
drivers/irqchip/irq-imx-gpcv2.c
262
writel_relaxed(~0, reg + GPC_IMR1_CORE2);
drivers/irqchip/irq-imx-gpcv2.c
263
writel_relaxed(~0, reg + GPC_IMR1_CORE3);
drivers/irqchip/irq-imx-gpcv2.c
266
writel_relaxed(~0, reg + GPC_IMR1_CORE0);
drivers/irqchip/irq-imx-gpcv2.c
267
writel_relaxed(~0, reg + GPC_IMR1_CORE1);
drivers/irqchip/irq-imx-gpcv2.c
280
writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup);
drivers/irqchip/irq-imx-gpcv2.c
49
writel_relaxed(cd->wakeup_sources[i], reg);
drivers/irqchip/irq-imx-gpcv2.c
65
writel_relaxed(cd->saved_irq_mask[i], gpcv2_idx_to_reg(cd, i));
drivers/irqchip/irq-imx-intmux.c
113
writel_relaxed(val, reg);
drivers/irqchip/irq-imx-intmux.c
268
writel_relaxed(0, data->regs + CHANIER(i));
drivers/irqchip/irq-imx-intmux.c
296
writel_relaxed(0, data->regs + CHANIER(i));
drivers/irqchip/irq-imx-intmux.c
338
writel_relaxed(irqchip_data->saved_reg, data->regs + CHANIER(i));
drivers/irqchip/irq-imx-intmux.c
94
writel_relaxed(val, reg);
drivers/irqchip/irq-imx-irqsteer.c
213
writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
drivers/irqchip/irq-imx-irqsteer.c
282
writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
drivers/irqchip/irq-imx-irqsteer.c
284
writel_relaxed(data->saved_reg[i],
drivers/irqchip/irq-imx-irqsteer.c
58
writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
drivers/irqchip/irq-imx-irqsteer.c
72
writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
drivers/irqchip/irq-loongson-htvec.c
157
writel_relaxed(0x0, priv->base + HTVEC_EN_OFF + 4 * idx);
drivers/irqchip/irq-loongson-htvec.c
158
writel_relaxed(0xFFFFFFFF, priv->base + 4 * idx);
drivers/irqchip/irq-loongson-pch-pic.c
271
writel_relaxed(0xFFFFFFFF, priv->base + PCH_PIC_MASK + 4 * i);
drivers/irqchip/irq-loongson-pch-pic.c
272
writel_relaxed(0xFFFFFFFF, priv->base + PCH_PIC_CLR + 4 * i);
drivers/irqchip/irq-loongson-pch-pic.c
274
writel_relaxed(0, priv->base + PCH_PIC_AUTO0 + 4 * i);
drivers/irqchip/irq-loongson-pch-pic.c
275
writel_relaxed(0, priv->base + PCH_PIC_AUTO1 + 4 * i);
drivers/irqchip/irq-loongson-pch-pic.c
277
writel_relaxed(0xFFFFFFFF, priv->base + PCH_PIC_HTMSI_EN + 4 * i);
drivers/irqchip/irq-lpc32xx.c
43
writel_relaxed(val, ic->base + reg);
drivers/irqchip/irq-mbigen.c
123
writel_relaxed(mask, base + addr);
drivers/irqchip/irq-mbigen.c
145
writel_relaxed(val, base + addr);
drivers/irqchip/irq-mbigen.c
167
writel_relaxed(val, base);
drivers/irqchip/irq-mchp-eic.c
134
writel_relaxed(eic->scfg[hwirq], eic->base +
drivers/irqchip/irq-mchp-eic.c
242
writel_relaxed(0UL, eic->base + MCHP_EIC_SCFG(i));
drivers/irqchip/irq-mchp-eic.c
53
writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq));
drivers/irqchip/irq-mchp-eic.c
64
writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq));
drivers/irqchip/irq-mchp-eic.c
96
writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq));
drivers/irqchip/irq-meson-gpio.c
233
writel_relaxed(tmp, ctl->base + reg);
drivers/irqchip/irq-mmp.c
103
writel_relaxed(r, mmp_icu_base + (hwirq << 2));
drivers/irqchip/irq-mmp.c
112
writel_relaxed(r, mmp_icu2_base + (hwirq << 2));
drivers/irqchip/irq-mmp.c
116
writel_relaxed(r, data->reg_mask);
drivers/irqchip/irq-mmp.c
132
writel_relaxed(r, mmp_icu_base + (hwirq << 2));
drivers/irqchip/irq-mmp.c
135
writel_relaxed(r, data->reg_mask);
drivers/irqchip/irq-mmp.c
79
writel_relaxed(r, mmp_icu_base + (hwirq << 2));
drivers/irqchip/irq-mmp.c
87
writel_relaxed(r, data->reg_mask);
drivers/irqchip/irq-mtk-cirq.c
247
writel_relaxed(mask, reg);
drivers/irqchip/irq-mtk-cirq.c
255
writel_relaxed(value, reg);
drivers/irqchip/irq-mtk-cirq.c
267
writel_relaxed(value | CIRQ_FLUSH, reg);
drivers/irqchip/irq-mtk-cirq.c
272
writel_relaxed(value, reg);
drivers/irqchip/irq-mtk-cirq.c
87
writel_relaxed(mask, mtk_cirq_irq_reg(chip_data, idx, cirq_num));
drivers/irqchip/irq-mtk-sysirq.c
52
writel_relaxed(value, base + reg_index * 4);
drivers/irqchip/irq-mvebu-icu.c
122
writel_relaxed(msg[0].address_hi, icu->base + subset->offset_set_ah);
drivers/irqchip/irq-mvebu-icu.c
123
writel_relaxed(msg[0].address_lo, icu->base + subset->offset_set_al);
drivers/irqchip/irq-mvebu-icu.c
129
writel_relaxed(msg[1].address_hi, icu->base + subset->offset_clr_ah);
drivers/irqchip/irq-mvebu-icu.c
130
writel_relaxed(msg[1].address_lo, icu->base + subset->offset_clr_al);
drivers/irqchip/irq-mvebu-icu.c
169
writel_relaxed(icu_int, icu->base + ICU_INT_CFG(d->hwirq));
drivers/irqchip/irq-mvebu-icu.c
181
writel_relaxed(icu_int, icu->base + ICU_INT_CFG(ICU_SATA0_ICU_ID));
drivers/irqchip/irq-mvebu-icu.c
182
writel_relaxed(icu_int, icu->base + ICU_INT_CFG(ICU_SATA1_ICU_ID));
drivers/irqchip/irq-mvebu-icu.c
346
writel_relaxed(0x0, icu->base + ICU_INT_CFG(i));
drivers/irqchip/irq-mvebu-sei.c
346
writel_relaxed(0xFFFFFFFF, sei->base + GICP_SECR(reg_idx));
drivers/irqchip/irq-mvebu-sei.c
347
writel_relaxed(0xFFFFFFFF, sei->base + GICP_SEMR(reg_idx));
drivers/irqchip/irq-mvebu-sei.c
63
writel_relaxed(BIT(SEI_IRQ_REG_BIT(d->hwirq)),
drivers/irqchip/irq-mvebu-sei.c
77
writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx));
drivers/irqchip/irq-mvebu-sei.c
91
writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx));
drivers/irqchip/irq-mxs.c
226
writel_relaxed(ASM9260_BM_CTRL_IRQ_ENABLE,
drivers/irqchip/irq-nvic.c
127
writel_relaxed(~0, gc->reg_base + NVIC_ICER);
drivers/irqchip/irq-nvic.c
132
writel_relaxed(0, nvic_base + NVIC_IPR + i);
drivers/irqchip/irq-omap-intc.c
74
writel_relaxed(val, omap_irq_base + reg);
drivers/irqchip/irq-owl-sirq.c
116
writel_relaxed(extctl, data->base + data->params->reg_offset[index]);
drivers/irqchip/irq-pruss-intc.c
134
writel_relaxed(val, intc->base + reg);
drivers/irqchip/irq-qcom-mpm.c
103
writel_relaxed(val, priv->base + offset);
drivers/irqchip/irq-rda-intc.c
32
writel_relaxed(BIT(d->hwirq), rda_intc_base + RDA_INTC_MASK_CLR);
drivers/irqchip/irq-rda-intc.c
37
writel_relaxed(BIT(d->hwirq), rda_intc_base + RDA_INTC_MASK_SET);
drivers/irqchip/irq-rda-intc.c
92
writel_relaxed(RDA_IRQ_MASK_ALL, rda_intc_base + RDA_INTC_MASK_CLR);
drivers/irqchip/irq-renesas-rzg2l.c
106
writel_relaxed(iscr & ~bit, priv->base + ISCR);
drivers/irqchip/irq-renesas-rzg2l.c
122
writel_relaxed(reg & ~bit, priv->base + TSCR);
drivers/irqchip/irq-renesas-rzg2l.c
150
writel_relaxed(readl_relaxed(priv->base + IMSK) | bit, priv->base + IMSK);
drivers/irqchip/irq-renesas-rzg2l.c
158
writel_relaxed(readl_relaxed(priv->base + IMSK) & ~bit, priv->base + IMSK);
drivers/irqchip/irq-renesas-rzg2l.c
166
writel_relaxed(readl_relaxed(priv->base + TMSK) | bit, priv->base + TMSK);
drivers/irqchip/irq-renesas-rzg2l.c
174
writel_relaxed(readl_relaxed(priv->base + TMSK) & ~bit, priv->base + TMSK);
drivers/irqchip/irq-renesas-rzg2l.c
226
writel_relaxed(reg, priv->base + TSSR(tssr_index));
drivers/irqchip/irq-renesas-rzg2l.c
267
writel_relaxed(reg, priv->base + TSSR(tssr_index));
drivers/irqchip/irq-renesas-rzg2l.c
322
writel_relaxed(tmp, priv->base + IITSR);
drivers/irqchip/irq-renesas-rzg2l.c
338
writel_relaxed(reg, priv->base + TSSR(tssr_index));
drivers/irqchip/irq-renesas-rzg2l.c
378
writel_relaxed(reg, priv->base + TITSR(index));
drivers/irqchip/irq-renesas-rzg2l.c
380
writel_relaxed(tssr, priv->base + TSSR(tssr_index));
drivers/irqchip/irq-renesas-rzg2l.c
424
writel_relaxed(cache->titsr[i], base + TITSR(i));
drivers/irqchip/irq-renesas-rzg2l.c
425
writel_relaxed(cache->iitsr, base + IITSR);
drivers/irqchip/irq-renesas-rzt2h.c
145
writel_relaxed(val, base + RZT2H_ICU_PORTNF_MD);
drivers/irqchip/irq-renesas-rzv2h.c
182
writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR);
drivers/irqchip/irq-renesas-rzv2h.c
187
writel_relaxed(bit, priv->base + ICU_ISCLR);
drivers/irqchip/irq-renesas-rzv2h.c
189
writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR);
drivers/irqchip/irq-renesas-rzv2h.c
217
writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k));
drivers/irqchip/irq-renesas-rzv2h.c
225
writel_relaxed(BIT(tint_nr), priv->base + priv->info->t_offs + ICU_TSCLR);
drivers/irqchip/irq-renesas-rzv2h.c
258
writel_relaxed(sense, priv->base + ICU_NITSR);
drivers/irqchip/irq-renesas-rzv2h.c
279
writel_relaxed(bit, priv->base + ICU_ISCLR);
drivers/irqchip/irq-renesas-rzv2h.c
315
writel_relaxed(iitsr, priv->base + ICU_IITSR);
drivers/irqchip/irq-renesas-rzv2h.c
338
writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR);
drivers/irqchip/irq-renesas-rzv2h.c
405
writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
drivers/irqchip/irq-renesas-rzv2h.c
410
writel_relaxed(titsr, priv->base + priv->info->t_offs + ICU_TITSR(titsr_k));
drivers/irqchip/irq-renesas-rzv2h.c
414
writel_relaxed(tssr | tien, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
drivers/irqchip/irq-renesas-rzv2h.c
461
writel_relaxed(cache->titsr[i], base + rzv2h_icu_data->info->t_offs + ICU_TITSR(i));
drivers/irqchip/irq-renesas-rzv2h.c
462
writel_relaxed(cache->iitsr, base + ICU_IITSR);
drivers/irqchip/irq-renesas-rzv2h.c
463
writel_relaxed(cache->nitsr, base + ICU_NITSR);
drivers/irqchip/irq-riscv-imsic-platform.c
63
writel_relaxed(vec->local_id, local->msi_va);
drivers/irqchip/irq-riscv-imsic-state.c
187
writel_relaxed(tvec->local_id, tlocal->msi_va);
drivers/irqchip/irq-riscv-imsic-state.c
191
writel_relaxed(mvec->local_id, mlocal->msi_va);
drivers/irqchip/irq-riscv-imsic-state.c
196
writel_relaxed(mvec->local_id, mlocal->msi_va);
drivers/irqchip/irq-sa11x0.c
100
writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR);
drivers/irqchip/irq-sa11x0.c
110
writel_relaxed(st->iccr, iobase + ICCR);
drivers/irqchip/irq-sa11x0.c
111
writel_relaxed(st->iclr, iobase + ICLR);
drivers/irqchip/irq-sa11x0.c
113
writel_relaxed(st->icmr, iobase + ICMR);
drivers/irqchip/irq-sa11x0.c
158
writel_relaxed(0, iobase + ICMR);
drivers/irqchip/irq-sa11x0.c
161
writel_relaxed(0, iobase + ICLR);
drivers/irqchip/irq-sa11x0.c
167
writel_relaxed(1, iobase + ICCR);
drivers/irqchip/irq-sa11x0.c
40
writel_relaxed(reg, iobase + ICMR);
drivers/irqchip/irq-sa11x0.c
49
writel_relaxed(reg, iobase + ICMR);
drivers/irqchip/irq-sifive-plic.c
434
writel_relaxed(new_mask, enable + j);
drivers/irqchip/irq-sifive-plic.c
469
writel_relaxed(stored, enable + i);
drivers/irqchip/irq-sni-exiu.c
106
writel_relaxed(val, data->base + EILVL);
drivers/irqchip/irq-sni-exiu.c
116
writel_relaxed(val, data->base + EIEDG);
drivers/irqchip/irq-sni-exiu.c
118
writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR);
drivers/irqchip/irq-sni-exiu.c
219
writel_relaxed(0xFFFFFFFF, data->base + EIREQCLR);
drivers/irqchip/irq-sni-exiu.c
220
writel_relaxed(0xFFFFFFFF, data->base + EIMASK);
drivers/irqchip/irq-sni-exiu.c
69
writel_relaxed(val, data->base + EIMASK);
drivers/irqchip/irq-sni-exiu.c
79
writel_relaxed(val, data->base + EIMASK);
drivers/irqchip/irq-sni-exiu.c
89
writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR);
drivers/irqchip/irq-sni-exiu.c
92
writel_relaxed(val, data->base + EIMASK);
drivers/irqchip/irq-sp7021-intc.c
248
writel_relaxed(0, REG_INTR_MASK + i * 4);
drivers/irqchip/irq-sp7021-intc.c
250
writel_relaxed(~0, REG_INTR_TYPE + i * 4);
drivers/irqchip/irq-sp7021-intc.c
252
writel_relaxed(0, REG_INTR_POLARITY + i * 4);
drivers/irqchip/irq-sp7021-intc.c
254
writel_relaxed(~0, REG_INTR_PRIORITY + i * 4);
drivers/irqchip/irq-sp7021-intc.c
256
writel_relaxed(~0, REG_INTR_CLEAR + i * 4);
drivers/irqchip/irq-sp7021-intc.c
96
writel_relaxed(mask, reg);
drivers/irqchip/irq-stm32-exti.c
196
writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
drivers/irqchip/irq-stm32-exti.c
206
writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
drivers/irqchip/irq-stm32-exti.c
207
writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
drivers/irqchip/irq-stm32-exti.c
209
writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
drivers/irqchip/irq-stm32-exti.c
316
writel_relaxed(0, base + stm32_bank->imr_ofst);
drivers/irqchip/irq-stm32-exti.c
317
writel_relaxed(0, base + stm32_bank->emr_ofst);
drivers/irqchip/irq-stm32mp-exti.c
275
writel_relaxed(wake_active, base + bank->imr_ofst);
drivers/irqchip/irq-stm32mp-exti.c
284
writel_relaxed(chip_data->rtsr_cache, base + bank->rtsr_ofst);
drivers/irqchip/irq-stm32mp-exti.c
285
writel_relaxed(chip_data->ftsr_cache, base + bank->ftsr_ofst);
drivers/irqchip/irq-stm32mp-exti.c
287
writel_relaxed(mask_cache, base + bank->imr_ofst);
drivers/irqchip/irq-stm32mp-exti.c
297
writel_relaxed(val, base + reg);
drivers/irqchip/irq-stm32mp-exti.c
308
writel_relaxed(val, base + reg);
drivers/irqchip/irq-stm32mp-exti.c
321
writel_relaxed(val, base + reg);
drivers/irqchip/irq-stm32mp-exti.c
392
writel_relaxed(rtsr, base + bank->rtsr_ofst);
drivers/irqchip/irq-stm32mp-exti.c
393
writel_relaxed(ftsr, base + bank->ftsr_ofst);
drivers/irqchip/irq-stm32mp-exti.c
463
writel_relaxed(mask, base + bank->swier_ofst);
drivers/irqchip/irq-stm32mp-exti.c
578
writel_relaxed(0, base + bank->imr_ofst);
drivers/irqchip/irq-sun6i-r.c
139
writel_relaxed(nmi_src_type, base + SUN6I_NMI_CTRL);
drivers/irqchip/irq-sun6i-r.c
279
writel_relaxed(buf[i], base + SUN6I_IRQ_ENABLE(i));
drivers/irqchip/irq-sun6i-r.c
282
writel_relaxed(buf[i], base + SUN6I_MUX_ENABLE(i));
drivers/irqchip/irq-sun6i-r.c
292
writel_relaxed(SUN6I_NMI_BIT, base + SUN6I_IRQ_ENABLE(0));
drivers/irqchip/irq-sun6i-r.c
294
writel_relaxed(0, base + SUN6I_IRQ_ENABLE(i));
drivers/irqchip/irq-sun6i-r.c
86
writel_relaxed(SUN6I_NMI_BIT, base + SUN6I_IRQ_PENDING(0));
drivers/irqchip/irq-tegra.c
151
writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);
drivers/irqchip/irq-tegra.c
154
writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);
drivers/irqchip/irq-tegra.c
157
writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
drivers/irqchip/irq-tegra.c
173
writel_relaxed(lic->cpu_iep[i],
drivers/irqchip/irq-tegra.c
175
writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);
drivers/irqchip/irq-tegra.c
176
writel_relaxed(lic->cpu_ier[i],
drivers/irqchip/irq-tegra.c
178
writel_relaxed(lic->cop_iep[i],
drivers/irqchip/irq-tegra.c
180
writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);
drivers/irqchip/irq-tegra.c
181
writel_relaxed(lic->cop_ier[i],
drivers/irqchip/irq-tegra.c
319
writel_relaxed(GENMASK(31, 0), base + ICTLR_CPU_IER_CLR);
drivers/irqchip/irq-tegra.c
321
writel_relaxed(0, base + ICTLR_CPU_IEP_CLASS);
drivers/irqchip/irq-tegra.c
88
writel_relaxed(mask, base + reg);
drivers/irqchip/irq-uniphier-aidet.c
219
writel_relaxed(priv->saved_vals[i],
drivers/irqchip/irq-uniphier-aidet.c
40
writel_relaxed(tmp, priv->reg_base + reg);
drivers/irqchip/qcom-pdc.c
59
writel_relaxed(val, base + reg + i * sizeof(u32));
drivers/mailbox/arm_mhu.c
53
writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
drivers/mailbox/arm_mhu.c
71
writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
drivers/mailbox/arm_mhu.c
83
writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
drivers/mailbox/arm_mhu_db.c
154
writel_relaxed(BIT(chan_info->doorbell), base + INTR_SET_OFS);
drivers/mailbox/arm_mhu_db.c
80
writel_relaxed(BIT(chan_info->doorbell), base + INTR_CLR_OFS);
drivers/mailbox/arm_mhuv2.c
1001
writel_relaxed(0x0, &mhu->send->ch_wn[i].int_en);
drivers/mailbox/arm_mhuv2.c
1013
writel_relaxed(0x1, &mhu->send->access_request);
drivers/mailbox/arm_mhuv2.c
1049
writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_set);
drivers/mailbox/arm_mhuv2.c
1107
writel_relaxed(0x0, &mhu->send->access_request);
drivers/mailbox/arm_mhuv2.c
255
writel_relaxed(_regval, _regptr); \
drivers/mailbox/arm_mhuv2.c
265
writel_relaxed(BIT(priv->doorbell),
drivers/mailbox/arm_mhuv2.c
275
writel_relaxed(BIT(priv->doorbell),
drivers/mailbox/arm_mhuv2.c
283
writel_relaxed(BIT(priv->doorbell),
drivers/mailbox/arm_mhuv2.c
306
writel_relaxed(BIT(priv->doorbell),
drivers/mailbox/arm_mhuv2.c
335
writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_clear);
drivers/mailbox/arm_mhuv2.c
345
writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_set);
drivers/mailbox/arm_mhuv2.c
379
writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[idx].stat_clear);
drivers/mailbox/arm_mhuv2.c
393
writel_relaxed(0x1, &mhu->send->ch_wn[i].int_clr);
drivers/mailbox/arm_mhuv2.c
394
writel_relaxed(0x1, &mhu->send->ch_wn[i].int_en);
drivers/mailbox/arm_mhuv2.c
405
writel_relaxed(0x0, &mhu->send->ch_wn[i].int_en);
drivers/mailbox/arm_mhuv2.c
477
writel_relaxed(word, &mhu->send->ch_wn[priv->ch_wn_idx + windows - 1 - i].stat_set);
drivers/mailbox/arm_mhuv2.c
557
writel_relaxed(1, &mhu->send->ch_wn[priv->ch_wn_idx + i].int_clr);
drivers/mailbox/arm_mhuv2.c
570
writel_relaxed(1, &mhu->send->ch_wn[priv->ch_wn_idx].int_clr);
drivers/mailbox/arm_mhuv2.c
921
writel_relaxed(0x1, &mhu->send->ch_wn[priv->ch_wn_idx].int_en);
drivers/mailbox/arm_mhuv3.c
221
writel_relaxed(_rval, _rptr); \
drivers/mailbox/arm_mhuv3.c
399
writel_relaxed(BIT(priv->doorbell), &mhu->mbx->dbcw[priv->ch_idx].msk_clr);
drivers/mailbox/arm_mhuv3.c
410
writel_relaxed(BIT(priv->doorbell), &mhu->mbx->dbcw[priv->ch_idx].msk_set);
drivers/mailbox/arm_mhuv3.c
418
writel_relaxed(BIT(priv->doorbell), &mhu->mbx->dbcw[priv->ch_idx].clr);
drivers/mailbox/arm_mhuv3.c
456
writel_relaxed(BIT(priv->doorbell), &mhu->pbx->dbcw[priv->ch_idx].set);
drivers/mailbox/arm_mhuv3.c
588
writel_relaxed(0xFFFFFFFF, &dbcw[i].clr);
drivers/mailbox/arm_mhuv3.c
589
writel_relaxed(0xFFFFFFFF, &dbcw[i].msk_set);
drivers/mailbox/bcm-flexrm-mailbox.c
1289
writel_relaxed(0x0, ring->regs + RING_CONTROL);
drivers/mailbox/bcm-flexrm-mailbox.c
1293
writel_relaxed(val, ring->regs + RING_BD_START_ADDR);
drivers/mailbox/bcm-flexrm-mailbox.c
1302
writel_relaxed(val, ring->regs + RING_CMPL_START_ADDR);
drivers/mailbox/bcm-flexrm-mailbox.c
1321
writel_relaxed(val, ring->regs + RING_MSI_CONTROL);
drivers/mailbox/bcm-flexrm-mailbox.c
1325
writel_relaxed(val, ring->regs + RING_CONTROL);
drivers/mailbox/bcm-flexrm-mailbox.c
1356
writel_relaxed(0x0, ring->regs + RING_CONTROL);
drivers/mailbox/bcm-flexrm-mailbox.c
1360
writel_relaxed(BIT(CONTROL_FLUSH_SHIFT),
drivers/mailbox/bcm-flexrm-mailbox.c
1374
writel_relaxed(0x0, ring->regs + RING_CONTROL);
drivers/mailbox/bcm-flexrm-mailbox.c
1469
writel_relaxed(msg->address_lo, ring->regs + RING_MSI_ADDR_LS);
drivers/mailbox/bcm-flexrm-mailbox.c
1470
writel_relaxed(msg->address_hi, ring->regs + RING_MSI_ADDR_MS);
drivers/mailbox/bcm-flexrm-mailbox.c
1471
writel_relaxed(msg->data, ring->regs + RING_MSI_DATA_VALUE);
drivers/mailbox/bcm74110-mailbox.c
118
writel_relaxed(val, mbox->base + offset_base + off); \
drivers/mailbox/hi3660-mailbox.c
189
writel_relaxed(~BIT(mchan->dst_irq), base + MBOX_IMASK_REG);
drivers/mailbox/hi3660-mailbox.c
192
writel_relaxed(BIT(mchan->dst_irq), base + MBOX_DST_REG);
drivers/mailbox/hi3660-mailbox.c
195
writel_relaxed(MBOX_AUTOMATIC_ACK, base + MBOX_MODE_REG);
drivers/mailbox/hi3660-mailbox.c
199
writel_relaxed(buf[i], base + MBOX_DATA_REG + i * 4);
drivers/mailbox/mailbox-altera.c
107
writel_relaxed(MBOX_MAGIC, mbox->mbox_base + MAILBOX_PTR_REG);
drivers/mailbox/mailbox-altera.c
111
writel_relaxed(0, mbox->mbox_base + MAILBOX_PTR_REG);
drivers/mailbox/mailbox-altera.c
227
writel_relaxed(udata[MBOX_PTR], mbox->mbox_base + MAILBOX_PTR_REG);
drivers/mailbox/mailbox-altera.c
228
writel_relaxed(udata[MBOX_CMD], mbox->mbox_base + MAILBOX_CMD_REG);
drivers/mailbox/mailbox-altera.c
270
writel_relaxed(~0, mbox->mbox_base + MAILBOX_INTMASK_REG);
drivers/mailbox/mailbox-altera.c
85
writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG);
drivers/mailbox/mailbox-altera.c
97
writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG);
drivers/mailbox/mailbox-mpfs.c
135
writel_relaxed(word_buf[index],
drivers/mailbox/mailbox-mpfs.c
149
writel_relaxed(val, mbox->mbox_base + msg->mbox_offset + index * 0x4);
drivers/mailbox/mailbox-mpfs.c
161
writel_relaxed(tx_trigger, mbox->ctrl_base + SERVICES_CR_OFFSET);
drivers/mailbox/mailbox-mpfs.c
207
writel_relaxed(0, mbox->int_reg);
drivers/mailbox/mailbox-sti.c
130
writel_relaxed(BIT(channel), base + STI_ENA_SET_OFFSET);
drivers/mailbox/mailbox-sti.c
145
writel_relaxed(BIT(channel), base + STI_ENA_CLR_OFFSET);
drivers/mailbox/mailbox-sti.c
157
writel_relaxed(BIT(channel), base + STI_IRQ_CLR_OFFSET);
drivers/mailbox/mailbox-sti.c
283
writel_relaxed(BIT(channel), base + STI_IRQ_SET_OFFSET);
drivers/mailbox/pl320-ipc.c
100
writel_relaxed(2, ipc_base + IPCMxSEND(IPC_RX_MBOX));
drivers/mailbox/pl320-ipc.c
126
writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
drivers/mailbox/pl320-ipc.c
134
writel_relaxed(CHAN_MASK(A9_SOURCE),
drivers/mailbox/pl320-ipc.c
136
writel_relaxed(CHAN_MASK(M3_SOURCE),
drivers/mailbox/pl320-ipc.c
138
writel_relaxed(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
drivers/mailbox/pl320-ipc.c
142
writel_relaxed(CHAN_MASK(M3_SOURCE),
drivers/mailbox/pl320-ipc.c
144
writel_relaxed(CHAN_MASK(A9_SOURCE),
drivers/mailbox/pl320-ipc.c
146
writel_relaxed(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
drivers/mailbox/pl320-ipc.c
52
writel_relaxed(data[i], ipc_base + IPCMxDR(mbox, i));
drivers/mailbox/pl320-ipc.c
53
writel_relaxed(0x1, ipc_base + IPCMxSEND(mbox));
drivers/mailbox/pl320-ipc.c
94
writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
drivers/mailbox/platform_mhu.c
59
writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
drivers/mailbox/platform_mhu.c
77
writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
drivers/mailbox/platform_mhu.c
89
writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
drivers/mailbox/rockchip-mailbox.c
116
writel_relaxed(1 << idx,
drivers/mailbox/rockchip-mailbox.c
72
writel_relaxed(msg->cmd, mb->mbox_base + MAILBOX_A2B_CMD(chans->idx));
drivers/mailbox/rockchip-mailbox.c
73
writel_relaxed(msg->rx_size, mb->mbox_base +
drivers/mailbox/rockchip-mailbox.c
84
writel_relaxed((1 << mb->mbox.num_chans) - 1,
drivers/mailbox/rockchip-mailbox.c
96
writel_relaxed(0, mb->mbox_base + MAILBOX_B2A_INTEN);
drivers/mailbox/stm32-ipcc.c
359
writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR);
drivers/mailbox/stm32-ipcc.c
360
writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR);
drivers/mailbox/stm32-ipcc.c
68
writel_relaxed(readl_relaxed(reg) | mask, reg);
drivers/mailbox/stm32-ipcc.c
78
writel_relaxed(readl_relaxed(reg) & ~mask, reg);
drivers/media/cec/platform/meson/ao-cec.c
229
writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
drivers/media/cec/platform/meson/ao-cec.c
260
writel_relaxed(reg, ao_cec->base + CEC_RW_REG);
drivers/media/cec/platform/meson/ao-cec.c
295
writel_relaxed(reg, ao_cec->base + CEC_RW_REG);
drivers/media/cec/platform/meson/ao-cec.c
412
writel_relaxed(CEC_INTR_TX, ao_cec->base + CEC_INTR_CLR_REG);
drivers/media/cec/platform/meson/ao-cec.c
460
writel_relaxed(CEC_INTR_RX, ao_cec->base + CEC_INTR_CLR_REG);
drivers/media/cec/platform/meson/ao-cec.c
680
writel_relaxed(CEC_GEN_CNTL_RESET,
drivers/media/platform/microchip/microchip-csi2dc.c
96
#define csi2dc_writel(st, reg, val) writel_relaxed((val), \
drivers/media/platform/nvidia/tegra-vde/vde.c
35
writel_relaxed(value, base + offset);
drivers/media/platform/qcom/camss/camss-csid-340.c
111
writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
drivers/media/platform/qcom/camss/camss-csid-340.c
132
writel_relaxed(CSID_IRQ_MASK_RST_DONE, csid->base + CSID_IRQ_MASK);
drivers/media/platform/qcom/camss/camss-csid-340.c
133
writel_relaxed(CSID_IRQ_MASK_RST_DONE, csid->base + CSID_IRQ_CLEAR);
drivers/media/platform/qcom/camss/camss-csid-340.c
134
writel_relaxed(CSID_IRQ_CMD_CLEAR, csid->base + CSID_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-csid-340.c
160
writel_relaxed(val, csid->base + CSID_IRQ_CLEAR);
drivers/media/platform/qcom/camss/camss-csid-340.c
161
writel_relaxed(CSID_IRQ_CMD_CLEAR, csid->base + CSID_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-csid-340.c
66
writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0);
drivers/media/platform/qcom/camss/camss-csid-340.c
69
writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1);
drivers/media/platform/qcom/camss/camss-csid-340.c
74
writel_relaxed(!!enable, csid->base + CSID_RDI_CTRL(rdi));
drivers/media/platform/qcom/camss/camss-csid-4-1.c
104
writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_1);
drivers/media/platform/qcom/camss/camss-csid-4-1.c
113
writel_relaxed(val, csid->base + CAMSS_CSID_CID_LUT_VC_n(vc));
drivers/media/platform/qcom/camss/camss-csid-4-1.c
119
writel_relaxed(val, csid->base + CAMSS_CSID_CID_n_CFG(cid));
drivers/media/platform/qcom/camss/camss-csid-4-1.c
123
writel_relaxed(val, csid->base + CAMSS_CSID_TG_CTRL);
drivers/media/platform/qcom/camss/camss-csid-4-1.c
128
writel_relaxed(val, csid->base + CAMSS_CSID_TG_CTRL);
drivers/media/platform/qcom/camss/camss-csid-4-1.c
147
writel_relaxed(value, csid->base + CAMSS_CSID_IRQ_CLEAR_CMD);
drivers/media/platform/qcom/camss/camss-csid-4-1.c
161
writel_relaxed(0x7fff, csid->base + CAMSS_CSID_RST_CMD);
drivers/media/platform/qcom/camss/camss-csid-4-1.c
74
writel_relaxed(val, csid->base + CAMSS_CSID_TG_VC_CFG);
drivers/media/platform/qcom/camss/camss-csid-4-1.c
79
writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_0(0));
drivers/media/platform/qcom/camss/camss-csid-4-1.c
83
writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_1(0));
drivers/media/platform/qcom/camss/camss-csid-4-1.c
87
writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_2(0));
drivers/media/platform/qcom/camss/camss-csid-4-1.c
99
writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_0);
drivers/media/platform/qcom/camss/camss-csid-4-7.c
100
writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_0);
drivers/media/platform/qcom/camss/camss-csid-4-7.c
105
writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_1);
drivers/media/platform/qcom/camss/camss-csid-4-7.c
115
writel_relaxed(val, csid->base + CAMSS_CSID_CID_LUT_VC_n(vc));
drivers/media/platform/qcom/camss/camss-csid-4-7.c
131
writel_relaxed(val, csid->base + CAMSS_CSID_CID_n_CFG(cid));
drivers/media/platform/qcom/camss/camss-csid-4-7.c
135
writel_relaxed(val, csid->base + CAMSS_CSID_TG_CTRL);
drivers/media/platform/qcom/camss/camss-csid-4-7.c
140
writel_relaxed(val, csid->base + CAMSS_CSID_TG_CTRL);
drivers/media/platform/qcom/camss/camss-csid-4-7.c
166
writel_relaxed(value, csid->base + CAMSS_CSID_IRQ_CLEAR_CMD);
drivers/media/platform/qcom/camss/camss-csid-4-7.c
186
writel_relaxed(0x7fff, csid->base + CAMSS_CSID_RST_CMD);
drivers/media/platform/qcom/camss/camss-csid-4-7.c
75
writel_relaxed(val, csid->base + CAMSS_CSID_TG_VC_CFG);
drivers/media/platform/qcom/camss/camss-csid-4-7.c
80
writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_0(0));
drivers/media/platform/qcom/camss/camss-csid-4-7.c
84
writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_1(0));
drivers/media/platform/qcom/camss/camss-csid-4-7.c
88
writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_2(0));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
186
writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0);
drivers/media/platform/qcom/camss/camss-csid-gen2.c
192
writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1);
drivers/media/platform/qcom/camss/camss-csid-gen2.c
203
writel_relaxed(val, csid->base + CSID_RDI_CTRL(rdi));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
223
writel_relaxed(val, csid->base + CSID_TPG_VC_CFG0);
drivers/media/platform/qcom/camss/camss-csid-gen2.c
227
writel_relaxed(val, csid->base + CSID_TPG_VC_CFG1);
drivers/media/platform/qcom/camss/camss-csid-gen2.c
229
writel_relaxed(0x12345678, csid->base + CSID_TPG_LFSR_SEED);
drivers/media/platform/qcom/camss/camss-csid-gen2.c
233
writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_0(0));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
236
writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_1(0));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
241
writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_2(0));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
243
writel_relaxed(0, csid->base + CSID_TPG_COLOR_BARS_CFG);
drivers/media/platform/qcom/camss/camss-csid-gen2.c
245
writel_relaxed(0, csid->base + CSID_TPG_COLOR_BOX_CFG);
drivers/media/platform/qcom/camss/camss-csid-gen2.c
253
writel_relaxed(val, csid->base + CSID_TPG_CTRL);
drivers/media/platform/qcom/camss/camss-csid-gen2.c
287
writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
291
writel_relaxed(val, csid->base + CSID_RDI_CFG1(vc));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
294
writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PERIOD(vc));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
297
writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PATTERN(vc));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
300
writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(vc));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
303
writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(vc));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
306
writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PERIOD(vc));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
309
writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PATTERN(vc));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
312
writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PERIOD(vc));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
315
writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PATTERN(vc));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
318
writel_relaxed(val, csid->base + CSID_RDI_CTRL(vc));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
322
writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
364
writel_relaxed(val, csid->base + CSID_TOP_IRQ_CLEAR);
drivers/media/platform/qcom/camss/camss-csid-gen2.c
368
writel_relaxed(val, csid->base + CSID_CSI2_RX_IRQ_CLEAR);
drivers/media/platform/qcom/camss/camss-csid-gen2.c
374
writel_relaxed(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));
drivers/media/platform/qcom/camss/camss-csid-gen2.c
378
writel_relaxed(val, csid->base + CSID_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-csid-gen2.c
399
writel_relaxed(1, csid->base + CSID_TOP_IRQ_CLEAR);
drivers/media/platform/qcom/camss/camss-csid-gen2.c
400
writel_relaxed(1, csid->base + CSID_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-csid-gen2.c
401
writel_relaxed(1, csid->base + CSID_TOP_IRQ_MASK);
drivers/media/platform/qcom/camss/camss-csid-gen2.c
402
writel_relaxed(1, csid->base + CSID_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-csid-gen2.c
406
writel_relaxed(val, csid->base + CSID_RST_STROBES);
drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
108
writel_relaxed(0x1, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
110
writel_relaxed(0x1, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
115
writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG);
drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
118
writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
126
writel_relaxed(0x10, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
128
writel_relaxed(settle_cnt, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
130
writel_relaxed(0x3f, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
132
writel_relaxed(0x3f, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
150
writel_relaxed(0x0, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
154
writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG);
drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
172
writel_relaxed(val, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
174
writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
175
writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
176
writel_relaxed(0x0, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
58
writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c
60
writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
1046
writel_relaxed(val, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
1050
writel_relaxed(val, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
1054
writel_relaxed(val, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
1058
writel_relaxed(val, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
1068
writel_relaxed(0, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
1078
writel_relaxed(0, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
1081
writel_relaxed(0, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
837
writel_relaxed(0x1, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
840
writel_relaxed(0x0, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
856
writel_relaxed(val, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
860
writel_relaxed(0x1, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
862
writel_relaxed(0x0, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
866
writel_relaxed(0x0, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
921
writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l));
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
924
writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG2(l));
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
927
writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG3(l));
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
931
writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG5(l));
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
934
writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG6(l));
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
937
writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG7(l));
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
941
writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG8(l));
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
944
writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG9(l));
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
947
writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_TEST_IMP(l));
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
950
writel_relaxed(val, csiphy->base +
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
955
writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l));
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
961
writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG4(l));
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
964
writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_MISC1(l));
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
988
writel_relaxed(val, csiphy->base + r->reg_addr);
drivers/media/platform/qcom/camss/camss-csiphy.c
292
writel_relaxed(val, csiphy->base_clk_mux);
drivers/media/platform/qcom/camss/camss-ispif.c
174
writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
drivers/media/platform/qcom/camss/camss-ispif.c
175
writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
drivers/media/platform/qcom/camss/camss-ispif.c
176
writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
drivers/media/platform/qcom/camss/camss-ispif.c
177
writel_relaxed(value3, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(1));
drivers/media/platform/qcom/camss/camss-ispif.c
178
writel_relaxed(value4, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(1));
drivers/media/platform/qcom/camss/camss-ispif.c
179
writel_relaxed(value5, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(1));
drivers/media/platform/qcom/camss/camss-ispif.c
239
writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
drivers/media/platform/qcom/camss/camss-ispif.c
240
writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
drivers/media/platform/qcom/camss/camss-ispif.c
241
writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
drivers/media/platform/qcom/camss/camss-ispif.c
300
writel_relaxed(val, ispif->base + ISPIF_RST_CMD_1);
drivers/media/platform/qcom/camss/camss-ispif.c
302
writel_relaxed(val, ispif->base + ISPIF_RST_CMD_0);
drivers/media/platform/qcom/camss/camss-ispif.c
434
writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
drivers/media/platform/qcom/camss/camss-ispif.c
442
writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
drivers/media/platform/qcom/camss/camss-ispif.c
450
writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
drivers/media/platform/qcom/camss/camss-ispif.c
458
writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
drivers/media/platform/qcom/camss/camss-ispif.c
466
writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
drivers/media/platform/qcom/camss/camss-ispif.c
669
writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
drivers/media/platform/qcom/camss/camss-ispif.c
670
writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE,
drivers/media/platform/qcom/camss/camss-ispif.c
678
writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
drivers/media/platform/qcom/camss/camss-ispif.c
679
writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE,
drivers/media/platform/qcom/camss/camss-ispif.c
687
writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
drivers/media/platform/qcom/camss/camss-ispif.c
688
writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE,
drivers/media/platform/qcom/camss/camss-ispif.c
696
writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
drivers/media/platform/qcom/camss/camss-ispif.c
697
writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE,
drivers/media/platform/qcom/camss/camss-ispif.c
705
writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
drivers/media/platform/qcom/camss/camss-ispif.c
706
writel_relaxed(ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE,
drivers/media/platform/qcom/camss/camss-ispif.c
760
writel_relaxed(val, ispif->base + addr);
drivers/media/platform/qcom/camss/camss-ispif.c
781
writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe));
drivers/media/platform/qcom/camss/camss-ispif.c
788
writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe));
drivers/media/platform/qcom/camss/camss-vfe-17x.c
181
writel_relaxed(bits | set_bits, vfe->base + reg);
drivers/media/platform/qcom/camss/camss-vfe-17x.c
199
writel_relaxed(BIT(31), vfe->base + VFE_IRQ_MASK_0);
drivers/media/platform/qcom/camss/camss-vfe-17x.c
204
writel_relaxed(reset_bits, vfe->base + VFE_GLOBAL_RESET_CMD);
drivers/media/platform/qcom/camss/camss-vfe-17x.c
214
writel_relaxed(val, vfe->base + VFE_BUS_WM_DEBUG_STATUS_CFG);
drivers/media/platform/qcom/camss/camss-vfe-17x.c
217
writel_relaxed(0, vfe->base + VFE_BUS_WM_ADDR_SYNC_FRAME_HEADER);
drivers/media/platform/qcom/camss/camss-vfe-17x.c
221
writel_relaxed(val, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
drivers/media/platform/qcom/camss/camss-vfe-17x.c
223
writel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
drivers/media/platform/qcom/camss/camss-vfe-17x.c
227
writel_relaxed(val, vfe->base + VFE_BUS_WM_ADDR_SYNC_NO_SYNC);
drivers/media/platform/qcom/camss/camss-vfe-17x.c
229
writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm));
drivers/media/platform/qcom/camss/camss-vfe-17x.c
232
writel_relaxed(val, vfe->base + VFE_BUS_WM_BUFFER_WIDTH_CFG(wm));
drivers/media/platform/qcom/camss/camss-vfe-17x.c
235
writel_relaxed(val, vfe->base + VFE_BUS_WM_BUFFER_HEIGHT_CFG(wm));
drivers/media/platform/qcom/camss/camss-vfe-17x.c
238
writel_relaxed(val, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); // XXX 1 for PLAIN8?
drivers/media/platform/qcom/camss/camss-vfe-17x.c
242
writel_relaxed(val, vfe->base + VFE_BUS_WM_STRIDE(wm));
drivers/media/platform/qcom/camss/camss-vfe-17x.c
247
writel_relaxed(val, vfe->base + VFE_BUS_WM_CFG(wm));
drivers/media/platform/qcom/camss/camss-vfe-17x.c
253
writel_relaxed(0, vfe->base + VFE_BUS_WM_CFG(wm));
drivers/media/platform/qcom/camss/camss-vfe-17x.c
263
writel_relaxed(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
drivers/media/platform/qcom/camss/camss-vfe-17x.c
264
writel_relaxed(stride * pix->height, vfe->base + VFE_BUS_WM_FRAME_INC(wm));
drivers/media/platform/qcom/camss/camss-vfe-17x.c
274
writel_relaxed(vfe->reg_update, vfe->base + VFE_REG_UPDATE_CMD);
drivers/media/platform/qcom/camss/camss-vfe-17x.c
291
writel_relaxed(~0u, vfe->base + VFE_BUS_IRQ_MASK(0));
drivers/media/platform/qcom/camss/camss-vfe-17x.c
292
writel_relaxed(~0u, vfe->base + VFE_BUS_IRQ_MASK(1));
drivers/media/platform/qcom/camss/camss-vfe-17x.c
293
writel_relaxed(~0u, vfe->base + VFE_BUS_IRQ_MASK(2));
drivers/media/platform/qcom/camss/camss-vfe-17x.c
306
writel_relaxed(*status0, vfe->base + VFE_IRQ_CLEAR_0);
drivers/media/platform/qcom/camss/camss-vfe-17x.c
307
writel_relaxed(*status1, vfe->base + VFE_IRQ_CLEAR_1);
drivers/media/platform/qcom/camss/camss-vfe-17x.c
311
writel_relaxed(CMD_GLOBAL_CLEAR, vfe->base + VFE_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-vfe-17x.c
337
writel_relaxed(status0, vfe->base + VFE_IRQ_CLEAR_0);
drivers/media/platform/qcom/camss/camss-vfe-17x.c
338
writel_relaxed(status1, vfe->base + VFE_IRQ_CLEAR_1);
drivers/media/platform/qcom/camss/camss-vfe-17x.c
342
writel_relaxed(vfe_bus_status[i], vfe->base + VFE_BUS_IRQ_CLEAR(i));
drivers/media/platform/qcom/camss/camss-vfe-17x.c
348
writel_relaxed(CMD_GLOBAL_CLEAR, vfe->base + VFE_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-vfe-17x.c
349
writel_relaxed(1, vfe->base + VFE_BUS_IRQ_CLEAR_GLOBAL);
drivers/media/platform/qcom/camss/camss-vfe-340.c
172
writel_relaxed(status, vfe->base + TFE_IRQ_CLEAR_0);
drivers/media/platform/qcom/camss/camss-vfe-340.c
173
writel_relaxed(TFE_IRQ_CMD_CLEAR, vfe->base + TFE_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-vfe-340.c
183
writel_relaxed(bus_status, vfe->base + TFE_BUS_IRQ_CLEAR_0);
drivers/media/platform/qcom/camss/camss-vfe-340.c
184
writel_relaxed(TFE_BUS_IRQ_CMD_CLEAR, vfe->base + TFE_BUS_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-vfe-340.c
211
writel_relaxed(status, vfe->base + TFE_BUS_STATUS_CLEAR);
drivers/media/platform/qcom/camss/camss-vfe-340.c
243
writel_relaxed(addr, vfe->base + TFE_BUS_IMAGE_ADDR(wm));
drivers/media/platform/qcom/camss/camss-vfe-340.c
253
writel_relaxed(TFE_BUS_IMAGE_CFG_0_DEFAULT, vfe->base + TFE_BUS_IMAGE_CFG_0(wm));
drivers/media/platform/qcom/camss/camss-vfe-340.c
254
writel_relaxed(0u, vfe->base + TFE_BUS_IMAGE_CFG_1(wm));
drivers/media/platform/qcom/camss/camss-vfe-340.c
255
writel_relaxed(TFE_BUS_IMAGE_CFG_2_DEFAULT, vfe->base + TFE_BUS_IMAGE_CFG_2(wm));
drivers/media/platform/qcom/camss/camss-vfe-340.c
256
writel_relaxed(stride * pix->height, vfe->base + TFE_BUS_FRAME_INCR(wm));
drivers/media/platform/qcom/camss/camss-vfe-340.c
257
writel_relaxed(TFE_BUS_PACKER_CFG_FMT_PLAIN64, vfe->base + TFE_BUS_PACKER_CFG(wm));
drivers/media/platform/qcom/camss/camss-vfe-340.c
260
writel_relaxed(0, vfe->base + TFE_BUS_FRAMEDROP_CFG_0(wm));
drivers/media/platform/qcom/camss/camss-vfe-340.c
261
writel_relaxed(1, vfe->base + TFE_BUS_FRAMEDROP_CFG_1(wm));
drivers/media/platform/qcom/camss/camss-vfe-340.c
262
writel_relaxed(0, vfe->base + TFE_BUS_IRQ_SUBSAMPLE_CFG_0(wm));
drivers/media/platform/qcom/camss/camss-vfe-340.c
263
writel_relaxed(1, vfe->base + TFE_BUS_IRQ_SUBSAMPLE_CFG_1(wm));
drivers/media/platform/qcom/camss/camss-vfe-340.c
296
writel_relaxed(vfe->reg_update, vfe->base + TFE_REG_UPDATE_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
226
writel_relaxed(bits & ~clr_bits, vfe->base + reg);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
233
writel_relaxed(bits | set_bits, vfe->base + reg);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
248
writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
253
writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ,
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
259
writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
311
writel_relaxed(reg, vfe->base +
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
320
writel_relaxed(reg, vfe->base +
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
323
writel_relaxed(0, vfe->base +
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
325
writel_relaxed(0, vfe->base +
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
342
writel_relaxed(reg,
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
349
writel_relaxed(pattern,
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
360
writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm));
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
366
writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
372
writel_relaxed(addr,
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
378
writel_relaxed(addr,
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
394
writel_relaxed(0x10000009, vfe->base + VFE_0_BUS_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
396
writel_relaxed(0, vfe->base + VFE_0_BUS_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
437
writel_relaxed(VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF,
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
528
writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
600
writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
603
writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
606
writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
628
writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
629
writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
640
writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
645
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
650
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
655
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
660
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
662
writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
667
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
672
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
679
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
684
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
696
writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
701
writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
706
writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
715
writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
724
writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
730
writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
739
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
740
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
741
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
742
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
743
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
744
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
745
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
746
writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
796
writel_relaxed(val, vfe->base + VFE_0_CORE_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
800
writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
803
writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
806
writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
809
writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG_0);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
812
writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
818
writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
826
writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
834
writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
845
writel_relaxed(val, vfe->base + VFE_0_MODULE_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
847
writel_relaxed(0x0, vfe->base + VFE_0_MODULE_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
871
writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
872
writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1);
drivers/media/platform/qcom/camss/camss-vfe-4-1.c
875
writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
1087
writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
1088
writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
1092
writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
269
writel_relaxed(bits & ~clr_bits, vfe->base + reg);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
276
writel_relaxed(bits | set_bits, vfe->base + reg);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
292
writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
296
writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
301
writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ,
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
307
writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
401
writel_relaxed(reg, vfe->base +
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
410
writel_relaxed(reg, vfe->base +
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
413
writel_relaxed(0, vfe->base +
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
415
writel_relaxed(0, vfe->base +
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
432
writel_relaxed(reg,
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
439
writel_relaxed(pattern,
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
450
writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm));
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
458
writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
466
writel_relaxed(addr,
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
472
writel_relaxed(addr,
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
488
writel_relaxed(0x101, vfe->base + VFE_0_BUS_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
490
writel_relaxed(0, vfe->base + VFE_0_BUS_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
530
writel_relaxed(VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF,
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
659
writel_relaxed(val, vfe->base + VFE_0_REALIGN_BUF_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
677
writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
751
writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
754
writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
757
writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
779
writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
780
writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
791
writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
796
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
801
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
806
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
811
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
813
writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
818
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
823
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
830
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
835
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
847
writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
852
writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
857
writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
866
writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
875
writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
881
writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
889
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
890
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
891
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
892
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
893
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
894
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
895
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
896
writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
904
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_0);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
905
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_1);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
906
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_2);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
907
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_3);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
908
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_4);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
909
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_5);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
910
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_6);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
911
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_7);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
912
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_8);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
913
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_9);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
914
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_10);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
915
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_11);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
916
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_12);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
917
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_13);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
918
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_14);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
919
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_15);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
920
writel_relaxed(val16, vfe->base + VFE_0_BUS_BDG_DS_CFG_16);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
949
writel_relaxed(val, vfe->base + VFE_0_CORE_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
953
writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
956
writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
959
writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
962
writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
965
writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
968
writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
974
writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
982
writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-7.c
992
writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1021
writel_relaxed(2 << VFE_0_BUS_IMAGE_MASTER_n_SHIFT(wm),
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1024
writel_relaxed(1 << VFE_0_BUS_IMAGE_MASTER_n_SHIFT(wm),
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1038
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1039
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1040
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1041
writel_relaxed(val3, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1042
writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1043
writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1044
writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1045
writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1053
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_0);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1054
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_1);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1055
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_2);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1056
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_3);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1057
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_4);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1058
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_5);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1059
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_6);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1060
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_7);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1061
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_8);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1062
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_9);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1063
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_10);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1064
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_11);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1065
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_12);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1066
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_13);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1067
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_14);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1068
writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_15);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1069
writel_relaxed(val16, vfe->base + VFE_0_BUS_BDG_DS_CFG_16);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1077
writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1078
writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
1082
writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
252
writel_relaxed(bits & ~clr_bits, vfe->base + reg);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
259
writel_relaxed(bits | set_bits, vfe->base + reg);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
275
writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
279
writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
284
writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ,
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
290
writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
374
writel_relaxed(reg, vfe->base +
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
383
writel_relaxed(reg, vfe->base +
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
386
writel_relaxed(0, vfe->base +
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
388
writel_relaxed(0, vfe->base +
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
405
writel_relaxed(reg,
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
412
writel_relaxed(pattern, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm));
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
422
writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm));
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
430
writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
438
writel_relaxed(addr,
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
444
writel_relaxed(addr,
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
460
writel_relaxed(0x101, vfe->base + VFE_0_BUS_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
462
writel_relaxed(0, vfe->base + VFE_0_BUS_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
502
writel_relaxed(VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF,
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
630
writel_relaxed(val, vfe->base + VFE_0_REALIGN_BUF_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
649
writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
722
writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
725
writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
728
writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
750
writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
751
writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
762
writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
767
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
772
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
777
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
782
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
784
writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
789
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
794
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
801
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
806
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
818
writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
823
writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
828
writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
837
writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
846
writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
852
writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
881
writel_relaxed(val, vfe->base + VFE_0_CORE_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
885
writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
888
writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
891
writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
894
writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
897
writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
900
writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
906
writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
914
writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD);
drivers/media/platform/qcom/camss/camss-vfe-4-8.c
924
writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD);
drivers/media/platform/qcom/camss/camss-vfe-480.c
107
writel_relaxed(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
drivers/media/platform/qcom/camss/camss-vfe-480.c
109
writel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
drivers/media/platform/qcom/camss/camss-vfe-480.c
111
writel_relaxed(pix->plane_fmt[0].bytesperline * pix->height,
drivers/media/platform/qcom/camss/camss-vfe-480.c
113
writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm));
drivers/media/platform/qcom/camss/camss-vfe-480.c
114
writel_relaxed(WM_IMAGE_CFG_0_DEFAULT_WIDTH,
drivers/media/platform/qcom/camss/camss-vfe-480.c
116
writel_relaxed(pix->plane_fmt[0].bytesperline,
drivers/media/platform/qcom/camss/camss-vfe-480.c
118
writel_relaxed(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
drivers/media/platform/qcom/camss/camss-vfe-480.c
121
writel_relaxed(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));
drivers/media/platform/qcom/camss/camss-vfe-480.c
122
writel_relaxed(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));
drivers/media/platform/qcom/camss/camss-vfe-480.c
123
writel_relaxed(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm));
drivers/media/platform/qcom/camss/camss-vfe-480.c
124
writel_relaxed(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm));
drivers/media/platform/qcom/camss/camss-vfe-480.c
126
writel_relaxed(1 << WM_CFG_EN | MODE_MIPI_RAW << WM_CFG_MODE,
drivers/media/platform/qcom/camss/camss-vfe-480.c
133
writel_relaxed(0, vfe->base + VFE_BUS_WM_CFG(wm));
drivers/media/platform/qcom/camss/camss-vfe-480.c
140
writel_relaxed(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
drivers/media/platform/qcom/camss/camss-vfe-480.c
146
writel_relaxed(vfe->reg_update, vfe->base + VFE_REG_UPDATE_CMD);
drivers/media/platform/qcom/camss/camss-vfe-480.c
193
writel_relaxed(status, vfe->base + VFE_IRQ_CLEAR(0));
drivers/media/platform/qcom/camss/camss-vfe-480.c
194
writel_relaxed(IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-vfe-480.c
202
writel_relaxed(status, vfe->base + VFE_BUS_IRQ_CLEAR(0));
drivers/media/platform/qcom/camss/camss-vfe-480.c
203
writel_relaxed(1, vfe->base + VFE_BUS_IRQ_CLEAR_GLOBAL);
drivers/media/platform/qcom/camss/camss-vfe-480.c
95
writel_relaxed(IRQ_MASK_0_RESET_ACK, vfe->base + VFE_IRQ_MASK(0));
drivers/media/platform/qcom/camss/camss-vfe-480.c
96
writel_relaxed(GLOBAL_RESET_HW_AND_REG, vfe->base + VFE_GLOBAL_RESET_CMD);
drivers/media/platform/qcom/camss/camss-vfe-vbif.c
22
writel_relaxed(val, vfe->vbif_base + reg);
drivers/media/platform/raspberrypi/rp1-cfe/pisp-fe.c
160
writel_relaxed(val, fe->base + offset);
drivers/media/platform/st/sti/hva/hva-hw.c
110
writel_relaxed(0x1, hva->regs + HVA_HIF_REG_IT_ACK);
drivers/media/platform/st/sti/hva/hva-hw.c
214
writel_relaxed(0x1, hva->regs + HVA_HIF_REG_IT_ACK);
drivers/media/platform/st/sti/hva/hva-hw.c
489
writel_relaxed(reg, hva->regs + HVA_HIF_REG_CLK_GATING);
drivers/media/platform/st/sti/hva/hva-hw.c
495
writel_relaxed(BSM_CFG_VAL1, hva->regs + HVA_HIF_REG_BSM);
drivers/media/platform/st/sti/hva/hva-hw.c
498
writel_relaxed(MIF_CFG_VAL3, hva->regs + HVA_HIF_REG_MIF_CFG);
drivers/media/platform/st/sti/hva/hva-hw.c
499
writel_relaxed(HEC_MIF_CFG_VAL, hva->regs + HVA_HIF_REG_HEC_MIF_CFG);
drivers/media/platform/st/sti/hva/hva-hw.c
509
writel_relaxed(cmd + (client_id << 8), hva->regs + HVA_HIF_FIFO_CMD);
drivers/media/platform/st/sti/hva/hva-hw.c
510
writel_relaxed(task->paddr, hva->regs + HVA_HIF_FIFO_CMD);
drivers/media/platform/st/sti/hva/hva-hw.c
533
writel_relaxed(reg, hva->regs + HVA_HIF_REG_CLK_GATING);
drivers/media/platform/st/stm32/dma2d/dma2d-hw.c
26
writel_relaxed(val, base + reg);
drivers/media/platform/st/stm32/stm32-csi.c
372
writel_relaxed(lmcfgr, csidev->base + STM32_CSI_LMCFGR);
drivers/media/platform/st/stm32/stm32-csi.c
383
writel_relaxed(STM32_CSI_PTCR1_TWM, csidev->base + STM32_CSI_PTCR1);
drivers/media/platform/st/stm32/stm32-csi.c
386
writel_relaxed(STM32_CSI_PTCR0_TCKEN, csidev->base + STM32_CSI_PTCR0);
drivers/media/platform/st/stm32/stm32-csi.c
389
writel_relaxed(STM32_CSI_PTCR1_TWM, csidev->base + STM32_CSI_PTCR1);
drivers/media/platform/st/stm32/stm32-csi.c
395
writel_relaxed(0, csidev->base + STM32_CSI_PTCR0);
drivers/media/platform/st/stm32/stm32-csi.c
398
writel_relaxed(0, csidev->base + STM32_CSI_PTCR1);
drivers/media/platform/st/stm32/stm32-csi.c
401
writel_relaxed(((addr >> 8) & STM32_CSI_PTCR1_TDI_MASK) << STM32_CSI_PTCR1_TDI_SHIFT,
drivers/media/platform/st/stm32/stm32-csi.c
405
writel_relaxed(STM32_CSI_PTCR0_TCKEN, csidev->base + STM32_CSI_PTCR0);
drivers/media/platform/st/stm32/stm32-csi.c
409
writel_relaxed(0, csidev->base + STM32_CSI_PTCR0);
drivers/media/platform/st/stm32/stm32-csi.c
412
writel_relaxed(STM32_CSI_PTCR1_TWM, csidev->base + STM32_CSI_PTCR1);
drivers/media/platform/st/stm32/stm32-csi.c
415
writel_relaxed(STM32_CSI_PTCR0_TCKEN, csidev->base + STM32_CSI_PTCR0);
drivers/media/platform/st/stm32/stm32-csi.c
418
writel_relaxed((addr & STM32_CSI_PTCR1_TDI_MASK) <<
drivers/media/platform/st/stm32/stm32-csi.c
426
writel_relaxed(0, csidev->base + STM32_CSI_PTCR0);
drivers/media/platform/st/stm32/stm32-csi.c
429
writel_relaxed(0, csidev->base + STM32_CSI_PTCR1);
drivers/media/platform/st/stm32/stm32-csi.c
433
writel_relaxed((val & STM32_CSI_PTCR1_TDI_MASK) << STM32_CSI_PTCR1_TDI_SHIFT,
drivers/media/platform/st/stm32/stm32-csi.c
437
writel_relaxed(STM32_CSI_PTCR0_TCKEN, csidev->base + STM32_CSI_PTCR0);
drivers/media/platform/st/stm32/stm32-csi.c
440
writel_relaxed(0, csidev->base + STM32_CSI_PTCR0);
drivers/media/platform/st/stm32/stm32-csi.c
519
writel_relaxed(STM32_CSI_CR_CSIEN, csidev->base + STM32_CSI_CR);
drivers/media/platform/st/stm32/stm32-csi.c
522
writel_relaxed(STM32_CSI_SR0_ERRORS, csidev->base + STM32_CSI_IER0);
drivers/media/platform/st/stm32/stm32-csi.c
525
writel_relaxed(lanes_ie, csidev->base + STM32_CSI_IER1);
drivers/media/platform/st/stm32/stm32-csi.c
529
writel_relaxed(0, csidev->base + STM32_CSI_PRCR);
drivers/media/platform/st/stm32/stm32-csi.c
532
writel_relaxed(0, csidev->base + STM32_CSI_PCR);
drivers/media/platform/st/stm32/stm32-csi.c
535
writel_relaxed(STM32_CSI_PTCR0_TCKEN, csidev->base + STM32_CSI_PTCR0);
drivers/media/platform/st/stm32/stm32-csi.c
537
writel_relaxed(0, csidev->base + STM32_CSI_PTCR0);
drivers/media/platform/st/stm32/stm32-csi.c
542
writel_relaxed((ccfr << STM32_CSI_PFCR_CCFR_SHIFT) |
drivers/media/platform/st/stm32/stm32-csi.c
558
writel_relaxed(STM32_CSI_PFCR_DLD | readl_relaxed(csidev->base + STM32_CSI_PFCR),
drivers/media/platform/st/stm32/stm32-csi.c
562
writel_relaxed(lanes_en | STM32_CSI_PCR_CLEN, csidev->base + STM32_CSI_PCR);
drivers/media/platform/st/stm32/stm32-csi.c
563
writel_relaxed(lanes_en | STM32_CSI_PCR_CLEN | STM32_CSI_PCR_PWRDOWN,
drivers/media/platform/st/stm32/stm32-csi.c
566
writel_relaxed(STM32_CSI_PRCR_PEN, csidev->base + STM32_CSI_PRCR);
drivers/media/platform/st/stm32/stm32-csi.c
569
writel_relaxed(0, csidev->base + STM32_CSI_PMCR);
drivers/media/platform/st/stm32/stm32-csi.c
583
writel_relaxed(0, csidev->base + STM32_CSI_PCR);
drivers/media/platform/st/stm32/stm32-csi.c
586
writel_relaxed(0, csidev->base + STM32_CSI_IER0);
drivers/media/platform/st/stm32/stm32-csi.c
587
writel_relaxed(0, csidev->base + STM32_CSI_IER1);
drivers/media/platform/st/stm32/stm32-csi.c
590
writel_relaxed(0, csidev->base + STM32_CSI_CR);
drivers/media/platform/st/stm32/stm32-csi.c
619
writel_relaxed(cfgr1, csidev->base + STM32_CSI_VCXCFGR1(vc));
drivers/media/platform/st/stm32/stm32-csi.c
622
writel_relaxed(STM32_CSI_CR_VCXSTART(vc) | STM32_CSI_CR_CSIEN,
drivers/media/platform/st/stm32/stm32-csi.c
643
writel_relaxed(STM32_CSI_CR_VCXSTOP(vc) | STM32_CSI_CR_CSIEN,
drivers/media/platform/st/stm32/stm32-csi.c
656
writel_relaxed(0, csidev->base + STM32_CSI_VCXCFGR1(vc));
drivers/media/platform/st/stm32/stm32-csi.c
657
writel_relaxed(0, csidev->base + STM32_CSI_VCXCFGR2(vc));
drivers/media/platform/st/stm32/stm32-csi.c
861
writel_relaxed(sr0 & STM32_CSI_SR0_ERRORS,
drivers/media/platform/st/stm32/stm32-csi.c
863
writel_relaxed(sr1 & STM32_CSI_SR1_ERRORS,
drivers/media/platform/st/stm32/stm32-dcmi.c
186
writel_relaxed(val, base + reg);
drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-common.h
184
writel_relaxed(val, base + reg);
drivers/media/platform/verisilicon/hantro.h
397
writel_relaxed(val, vpu->enc_base + reg);
drivers/media/platform/verisilicon/hantro.h
418
writel_relaxed(val, vpu->dec_base + reg);
drivers/media/rc/ir-hix5hd2.c
126
writel_relaxed(val, priv->base + IR_ENABLE);
drivers/media/rc/ir-hix5hd2.c
153
writel_relaxed(val, priv->base + IR_CONFIG);
drivers/media/rc/ir-hix5hd2.c
155
writel_relaxed(0x00, priv->base + IR_INTM);
drivers/media/rc/ir-hix5hd2.c
157
writel_relaxed(0x01, priv->base + IR_START);
drivers/media/rc/ir-hix5hd2.c
204
writel_relaxed(INT_CLR_OVERFLOW, priv->base + IR_INTC);
drivers/media/rc/ir-hix5hd2.c
233
writel_relaxed(INT_CLR_RCV, priv->base + IR_INTC);
drivers/media/rc/ir-hix5hd2.c
235
writel_relaxed(INT_CLR_TIMEOUT, priv->base + IR_INTC);
drivers/media/rc/ir-hix5hd2.c
379
writel_relaxed(0x00, priv->base + IR_INTM);
drivers/media/rc/ir-hix5hd2.c
380
writel_relaxed(0xff, priv->base + IR_INTC);
drivers/media/rc/ir-hix5hd2.c
381
writel_relaxed(0x01, priv->base + IR_START);
drivers/memory/brcmstb_dpfe.c
341
writel_relaxed(val, priv->regs + REG_DCPU_RESET);
drivers/memory/brcmstb_dpfe.c
354
writel_relaxed(0, regs + REG_TO_DCPU_MBOX);
drivers/memory/brcmstb_dpfe.c
355
writel_relaxed(0, regs + REG_TO_HOST_MBOX);
drivers/memory/brcmstb_dpfe.c
360
writel_relaxed(val, regs + REG_DCPU_RESET);
drivers/memory/brcmstb_dpfe.c
365
writel_relaxed(val, regs + REG_DCPU_RESET);
drivers/memory/brcmstb_dpfe.c
430
writel_relaxed(0, priv->regs + release_mbox);
drivers/memory/brcmstb_dpfe.c
468
writel_relaxed(chksum, regs + DCPU_MSG_RAM(i));
drivers/memory/brcmstb_dpfe.c
470
writel_relaxed(msg[i], regs + DCPU_MSG_RAM(i));
drivers/memory/brcmstb_dpfe.c
474
writel_relaxed(1, regs + REG_TO_DCPU_MBOX);
drivers/memory/brcmstb_dpfe.c
605
writel_relaxed(0, mem + i);
drivers/memory/brcmstb_dpfe.c
610
writel_relaxed(be32_to_cpu(fw[i]), mem + i);
drivers/memory/brcmstb_dpfe.c
613
writel_relaxed(le32_to_cpu(fw[i]), mem + i);
drivers/memory/brcmstb_dpfe.c
790
writel_relaxed(val, info + DRAM_INFO_INTERVAL);
drivers/memory/brcmstb_memc.c
212
writel_relaxed(val, cfg);
drivers/memory/brcmstb_memc.c
63
writel_relaxed(val, cfg);
drivers/memory/mtk-smi.c
254
writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON);
drivers/memory/mtk-smi.c
258
writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG);
drivers/memory/mtk-smi.c
261
writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i));
drivers/memory/mtk-smi.c
570
writel_relaxed(SLP_PROT_EN, larb->base + SMI_LARB_SLP_CON);
drivers/memory/mtk-smi.c
582
writel_relaxed(0, larb->base + SMI_LARB_SLP_CON);
drivers/memory/mtk-smi.c
943
writel_relaxed(init[i].value, common->base + init[i].offset);
drivers/memory/omap-gpmc.c
270
writel_relaxed(val, gpmc_base + idx);
drivers/memory/omap-gpmc.c
283
writel_relaxed(val, reg_addr);
drivers/memory/samsung/exynos-srom.c
92
writel_relaxed(bw, srom->reg_base + EXYNOS_SROM_BW);
drivers/memory/samsung/exynos-srom.c
94
writel_relaxed(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) |
drivers/memory/stm32_omm.c
275
writel_relaxed(omm->cr, omm->io_base + OMM_CR);
drivers/memory/stm32_omm.c
440
writel_relaxed(omm->cr, omm->io_base + OMM_CR);
drivers/memory/tegra/mc.h
131
writel_relaxed(value, mc->bcast_ch_regs + offset);
drivers/memory/tegra/mc.h
133
writel_relaxed(value, mc->ch_regs[ch] + offset);
drivers/memory/tegra/mc.h
144
writel_relaxed(value, mc->regs + offset);
drivers/memory/tegra/tegra20-emc.c
1123
writel_relaxed(EMC_PWR_GATHER_DISABLE, emc->regs + EMC_STAT_CONTROL);
drivers/memory/tegra/tegra20-emc.c
1134
writel_relaxed(EMC_PWR_GATHER_CLEAR, emc->regs + EMC_STAT_CONTROL);
drivers/memory/tegra/tegra20-emc.c
1135
writel_relaxed(EMC_PWR_GATHER_ENABLE, emc->regs + EMC_STAT_CONTROL);
drivers/memory/tegra/tegra20-emc.c
1164
writel_relaxed(0x00000000, emc->regs + EMC_STAT_CONTROL);
drivers/memory/tegra/tegra20-emc.c
1165
writel_relaxed(0x00000000, emc->regs + EMC_STAT_LLMC_CONTROL);
drivers/memory/tegra/tegra20-emc.c
1166
writel_relaxed(0xffffffff, emc->regs + EMC_STAT_PWR_CLOCK_LIMIT);
drivers/memory/tegra/tegra20-emc.c
251
writel_relaxed(status, emc->regs + EMC_INTSTATUS);
drivers/memory/tegra/tegra20-emc.c
290
writel_relaxed(timing->data[i],
drivers/memory/tegra/tegra20-emc.c
308
writel_relaxed(EMC_TIMING_UPDATE,
drivers/memory/tegra/tegra20-emc.c
545
writel_relaxed(EMC_MRR_DIVLD_INT, emc->regs + EMC_INTSTATUS);
drivers/memory/tegra/tegra20-emc.c
551
writel_relaxed(val, emc->regs + EMC_MRR);
drivers/memory/tegra/tegra20-emc.c
617
writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
drivers/memory/tegra/tegra20-emc.c
620
writel_relaxed(intmask, emc->regs + EMC_INTMASK);
drivers/memory/tegra/tegra20-emc.c
621
writel_relaxed(intmask, emc->regs + EMC_INTSTATUS);
drivers/memory/tegra/tegra20-emc.c
629
writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
drivers/memory/tegra/tegra210-emc.h
946
writel_relaxed(value, emc->regs + offset);
drivers/memory/tegra/tegra210-emc.h
958
writel_relaxed(value, emc->channel[channel] + offset);
drivers/memory/tegra/tegra210-emc.h
970
writel_relaxed(value, emc->regs + EMC_CCFIFO_DATA);
drivers/memory/tegra/tegra210-emc.h
974
writel_relaxed(value, emc->regs + EMC_CCFIFO_ADDR);
drivers/memory/tegra/tegra30-emc.c
1066
writel_relaxed(EMC_MRR_DIVLD_INT, emc->regs + EMC_INTSTATUS);
drivers/memory/tegra/tegra30-emc.c
1072
writel_relaxed(val, emc->regs + EMC_MRR);
drivers/memory/tegra/tegra30-emc.c
1145
writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
drivers/memory/tegra/tegra30-emc.c
1148
writel_relaxed(intmask, emc->regs + EMC_INTMASK);
drivers/memory/tegra/tegra30-emc.c
1149
writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS);
drivers/memory/tegra/tegra30-emc.c
1157
writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
drivers/memory/tegra/tegra30-emc.c
403
writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL);
drivers/memory/tegra/tegra30-emc.c
432
writel_relaxed(status, emc->regs + EMC_INTSTATUS);
drivers/memory/tegra/tegra30-emc.c
469
writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL2);
drivers/memory/tegra/tegra30-emc.c
480
writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL3);
drivers/memory/tegra/tegra30-emc.c
491
writel_relaxed(val, emc->regs + EMC_XM2QUSEPADCTRL);
drivers/memory/tegra/tegra30-emc.c
579
writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
drivers/memory/tegra/tegra30-emc.c
620
writel_relaxed(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
drivers/memory/tegra/tegra30-emc.c
639
writel_relaxed(timing->data[i],
drivers/memory/tegra/tegra30-emc.c
662
writel_relaxed(val, emc->regs + EMC_MRS_WAIT_CNT);
drivers/memory/tegra/tegra30-emc.c
685
writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE);
drivers/memory/tegra/tegra30-emc.c
689
writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE,
drivers/memory/tegra/tegra30-emc.c
691
writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST,
drivers/memory/tegra/tegra30-emc.c
693
writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
drivers/memory/tegra/tegra30-emc.c
697
writel_relaxed(EMC_REFCTRL_DISABLE_ALL(dram_num),
drivers/memory/tegra/tegra30-emc.c
703
writel_relaxed(timing->emc_mode_1,
drivers/memory/tegra/tegra30-emc.c
706
writel_relaxed(DRAM_BROADCAST(dram_num) |
drivers/memory/tegra/tegra30-emc.c
712
writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
drivers/memory/tegra/tegra30-emc.c
715
writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG);
drivers/memory/tegra/tegra30-emc.c
716
writel_relaxed(timing->data[73], emc->regs + EMC_XM2CLKPADCTRL);
drivers/memory/tegra/tegra30-emc.c
726
writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
drivers/memory/tegra/tegra30-emc.c
728
writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
drivers/memory/tegra/tegra30-emc.c
732
writel_relaxed(DRAM_BROADCAST(dram_num),
drivers/memory/tegra/tegra30-emc.c
738
writel_relaxed(timing->emc_mode_1,
drivers/memory/tegra/tegra30-emc.c
742
writel_relaxed(timing->emc_mode_2,
drivers/memory/tegra/tegra30-emc.c
754
writel_relaxed(val, emc->regs + EMC_MRS);
drivers/memory/tegra/tegra30-emc.c
758
writel_relaxed(timing->emc_mode_2,
drivers/memory/tegra/tegra30-emc.c
762
writel_relaxed(timing->emc_mode_1,
drivers/memory/tegra/tegra30-emc.c
772
writel_relaxed(EMC_ZQ_CAL_LONG_CMD_DEV0,
drivers/memory/tegra/tegra30-emc.c
776
writel_relaxed(EMC_ZQ_CAL_LONG_CMD_DEV1,
drivers/memory/tegra/tegra30-emc.c
781
writel_relaxed(0x1, emc->regs + EMC_UNSTALL_RW_AFTER_CLKCHANGE);
drivers/memory/tegra/tegra30-emc.c
810
writel_relaxed(EMC_REFCTRL_ENABLE_ALL(dram_num),
drivers/memory/tegra/tegra30-emc.c
815
writel_relaxed(timing->emc_auto_cal_interval,
drivers/memory/tegra/tegra30-emc.c
821
writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
drivers/memory/tegra/tegra30-emc.c
826
writel_relaxed(timing->emc_zcal_cnt_long,
drivers/mfd/mcp-sa11x0.c
108
writel_relaxed(reg << 17 | MCDR2_Rd, MCDR2(m));
drivers/mfd/mcp-sa11x0.c
130
writel_relaxed(m->mccr0, MCCR0(m));
drivers/mfd/mcp-sa11x0.c
138
writel_relaxed(m->mccr0, MCCR0(m));
drivers/mfd/mcp-sa11x0.c
208
writel_relaxed(-1, MCSR(m));
drivers/mfd/mcp-sa11x0.c
209
writel_relaxed(m->mccr1, MCCR1(m));
drivers/mfd/mcp-sa11x0.c
210
writel_relaxed(m->mccr0, MCCR0(m));
drivers/mfd/mcp-sa11x0.c
272
writel_relaxed(m->mccr1, MCCR1(m));
drivers/mfd/mcp-sa11x0.c
273
writel_relaxed(m->mccr0, MCCR0(m));
drivers/mfd/mcp-sa11x0.c
53
writel_relaxed(m->mccr0, MCCR0(m));
drivers/mfd/mcp-sa11x0.c
65
writel_relaxed(m->mccr0, MCCR0(m));
drivers/mfd/mcp-sa11x0.c
81
writel_relaxed(reg << 17 | MCDR2_Wr | (val & 0xffff), MCDR2(m));
drivers/mfd/omap-usb-host.c
112
writel_relaxed(val, base + reg);
drivers/mfd/omap-usb-tll.c
115
writel_relaxed(val, base + reg);
drivers/mfd/qcom_rpm.c
469
writel_relaxed(buf[i], RPM_REQ_REG(rpm, res->target_id + i));
drivers/mfd/qcom_rpm.c
473
writel_relaxed(sel_mask[i],
drivers/mfd/qcom_rpm.c
477
writel_relaxed(BIT(state), RPM_CTRL_REG(rpm, rpm->data->req_ctx_off));
drivers/mfd/qcom_rpm.c
502
writel_relaxed(0,
drivers/misc/pci_endpoint_test.c
367
writel_relaxed(bar_test_pattern_with_offset(barno, j),
drivers/misc/vcpu_stall_detector.c
51
writel_relaxed((value), \
drivers/mmc/host/cqhci.h
305
writel_relaxed(val, host->mmio + reg);
drivers/mmc/host/dw_mmc.h
506
writel_relaxed((value), (dev)->regs + SDMMC_##reg)
drivers/mmc/host/mmci.c
1363
writel_relaxed(clks, host->base + MMCIDATATIMER);
drivers/mmc/host/mmci.c
1775
writel_relaxed(mask | MCI_ST_SDIOITMASK, base + MMCIMASK0);
drivers/mmc/host/mmci.c
1777
writel_relaxed(mask & ~MCI_ST_SDIOITMASK, base + MMCIMASK0);
drivers/mmc/host/mmci_qcom_dml.c
141
writel_relaxed(1, base + DML_SW_RESET);
drivers/mmc/host/mmci_qcom_dml.c
162
writel_relaxed(config, base + DML_CONFIG);
drivers/mmc/host/mmci_qcom_dml.c
168
writel_relaxed(PRODUCER_PIPE_LOGICAL_SIZE,
drivers/mmc/host/mmci_qcom_dml.c
170
writel_relaxed(CONSUMER_PIPE_LOGICAL_SIZE,
drivers/mmc/host/mmci_qcom_dml.c
174
writel_relaxed(producer_id | (consumer_id << CONSUMER_PIPE_ID_SHFT),
drivers/mmc/host/mmci_qcom_dml.c
64
writel_relaxed(config, base + DML_CONFIG);
drivers/mmc/host/mmci_qcom_dml.c
67
writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE);
drivers/mmc/host/mmci_qcom_dml.c
70
writel_relaxed(data->blocks * data->blksz,
drivers/mmc/host/mmci_qcom_dml.c
75
writel_relaxed(config, base + DML_CONFIG);
drivers/mmc/host/mmci_qcom_dml.c
77
writel_relaxed(1, base + DML_PRODUCER_START);
drivers/mmc/host/mmci_qcom_dml.c
84
writel_relaxed(config, base + DML_CONFIG);
drivers/mmc/host/mmci_qcom_dml.c
88
writel_relaxed(config, base + DML_CONFIG);
drivers/mmc/host/mmci_qcom_dml.c
90
writel_relaxed(1, base + DML_CONSUMER_START);
drivers/mmc/host/mmci_stm32_sdmmc.c
240
writel_relaxed(dma_addr,
drivers/mmc/host/mmci_stm32_sdmmc.c
242
writel_relaxed(MMCI_STM32_IDMAEN,
drivers/mmc/host/mmci_stm32_sdmmc.c
259
writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR);
drivers/mmc/host/mmci_stm32_sdmmc.c
260
writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR);
drivers/mmc/host/mmci_stm32_sdmmc.c
261
writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R);
drivers/mmc/host/mmci_stm32_sdmmc.c
262
writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER);
drivers/mmc/host/mmci_stm32_sdmmc.c
263
writel_relaxed(MMCI_STM32_IDMAEN | MMCI_STM32_IDMALLIEN,
drivers/mmc/host/mmci_stm32_sdmmc.c
277
writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
drivers/mmc/host/mmci_stm32_sdmmc.c
291
writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
drivers/mmc/host/mmci_stm32_sdmmc.c
357
writel_relaxed(0, dlyb->base + DLYB_CR);
drivers/mmc/host/mmci_stm32_sdmmc.c
424
writel_relaxed(thr, host->base + MMCI_STM32_FIFOTHRR);
drivers/mmc/host/mmci_stm32_sdmmc.c
460
writel_relaxed(mask | host->variant->busy_detect_mask,
drivers/mmc/host/mmci_stm32_sdmmc.c
470
writel_relaxed(mask & ~host->variant->busy_detect_mask,
drivers/mmc/host/mmci_stm32_sdmmc.c
475
writel_relaxed(host->variant->busy_detect_mask, base + MMCICLEAR);
drivers/mmc/host/mmci_stm32_sdmmc.c
482
writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR);
drivers/mmc/host/mmci_stm32_sdmmc.c
492
writel_relaxed(DLYB_CR_SEN | DLYB_CR_DEN, dlyb->base + DLYB_CR);
drivers/mmc/host/mmci_stm32_sdmmc.c
496
writel_relaxed(cfgr, dlyb->base + DLYB_CFGR);
drivers/mmc/host/mmci_stm32_sdmmc.c
499
writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR);
drivers/mmc/host/mmci_stm32_sdmmc.c
544
writel_relaxed(cr, dlyb->base + SYSCFG_DLYBSD_CR);
drivers/mmc/host/mmci_stm32_sdmmc.c
561
writel_relaxed(cr, dlyb->base + SYSCFG_DLYBSD_CR);
drivers/mmc/host/mmci_stm32_sdmmc.c
660
writel_relaxed(MCI_STM32_VSWENDC, host->base + MMCICLEAR);
drivers/mmc/host/mmci_stm32_sdmmc.c
684
writel_relaxed(MCI_STM32_VSWENDC | MCI_STM32_CKSTOPC,
drivers/mmc/host/mtk-sd.c
839
writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
drivers/mmc/host/sdhci-msm.c
1009
writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
drivers/mmc/host/sdhci-msm.c
1039
writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset);
drivers/mmc/host/sdhci-msm.c
1045
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
1051
writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
drivers/mmc/host/sdhci-msm.c
1077
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
1121
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
1197
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
1234
writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
drivers/mmc/host/sdhci-msm.c
1395
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
1401
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
1796
writel_relaxed(new_config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
2310
writel_relaxed(config,
drivers/mmc/host/sdhci-msm.c
2670
writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
drivers/mmc/host/sdhci-msm.c
2714
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
338
writel_relaxed(val, msm_host->core_mem + offset);
drivers/mmc/host/sdhci-msm.c
344
writel_relaxed(val, host->ioaddr + offset);
drivers/mmc/host/sdhci-msm.c
454
writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
drivers/mmc/host/sdhci-msm.c
468
writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
drivers/mmc/host/sdhci-msm.c
472
writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
drivers/mmc/host/sdhci-msm.c
482
writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
drivers/mmc/host/sdhci-msm.c
632
writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
drivers/mmc/host/sdhci-msm.c
659
writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
drivers/mmc/host/sdhci-msm.c
662
writel_relaxed(msm_host->dll_config,
drivers/mmc/host/sdhci-msm.c
669
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
675
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
682
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
688
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
713
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
722
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
728
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
737
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
748
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
758
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
765
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
771
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
803
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
810
writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
drivers/mmc/host/sdhci-msm.c
822
writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
drivers/mmc/host/sdhci-msm.c
846
writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
drivers/mmc/host/sdhci-msm.c
857
writel_relaxed(config, host->ioaddr +
drivers/mmc/host/sdhci-msm.c
939
writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
drivers/mmc/host/sdhci-msm.c
943
writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
drivers/mmc/host/sdhci-msm.c
947
writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
drivers/mmc/host/sdhci-msm.c
951
writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
drivers/mmc/host/sdhci-msm.c
955
writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
drivers/mmc/host/sdhci-msm.c
959
writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
drivers/mmc/host/sdhci-msm.c
960
writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
drivers/mmc/host/sdhci-msm.c
961
writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
drivers/mmc/host/sdhci-msm.c
962
writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
drivers/mmc/host/sdhci-msm.c
963
writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
drivers/mmc/host/sdhci-msm.c
964
writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
drivers/mmc/host/sdhci-msm.c
965
writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
drivers/mmc/host/sdhci-msm.c
966
writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
drivers/mmc/host/sdhci-msm.c
967
writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
drivers/mmc/host/sdhci-msm.c
973
writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
drivers/mmc/host/sdhci-msm.c
977
writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
drivers/mmc/host/sdhci-msm.c
981
writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
drivers/mmc/host/sdhci-msm.c
985
writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
drivers/mmc/host/sdhci-sprd.c
145
writel_relaxed(val, host->ioaddr + reg);
drivers/mmc/host/sdhci-st.c
128
writel_relaxed(0x0, ioaddr + ST_TOP_MMC_DLY_CTRL);
drivers/mmc/host/sdhci-st.c
129
writel_relaxed(ST_TOP_MMC_DLY_MAX,
drivers/mmc/host/sdhci-st.c
156
writel_relaxed(ST_MMC_CCONFIG_1_DEFAULT,
drivers/mmc/host/sdhci-st.c
176
writel_relaxed(cconf2, host->ioaddr + ST_MMC_CCONFIG_REG_2);
drivers/mmc/host/sdhci-st.c
182
writel_relaxed(ST_MMC_GP_OUTPUT_CD,
drivers/mmc/host/sdhci-st.c
209
writel_relaxed(cconf3, host->ioaddr + ST_MMC_CCONFIG_REG_3);
drivers/mmc/host/sdhci-st.c
210
writel_relaxed(cconf4, host->ioaddr + ST_MMC_CCONFIG_REG_4);
drivers/mmc/host/sdhci-st.c
211
writel_relaxed(cconf5, host->ioaddr + ST_MMC_CCONFIG_REG_5);
drivers/mmc/host/sdhci-st.c
219
writel_relaxed(ST_TOP_MMC_DYN_DLY_CONF, ioaddr + ST_TOP_MMC_DLY_CTRL);
drivers/mmc/host/sdhci-st.c
220
writel_relaxed(ST_TOP_MMC_TX_DLL_STEP_DLY_VALID,
drivers/mtd/lpddr/lpddr2_nvm.c
140
writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18,
drivers/mtd/lpddr/lpddr2_nvm.c
142
writel_relaxed(0x01, pcm_data->ctl_regs + LPDDR2_MODE_REG_DATA);
drivers/mtd/lpddr/lpddr2_nvm.c
155
writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18,
drivers/mtd/lpddr/lpddr2_nvm.c
157
writel_relaxed(0x02, pcm_data->ctl_regs + LPDDR2_MODE_REG_DATA);
drivers/mtd/nand/raw/arasan-nand-controller.c
1387
writel_relaxed(0, nfc->base + INTR_SIG_EN_REG);
drivers/mtd/nand/raw/arasan-nand-controller.c
1390
writel_relaxed(EVENT_MASK, nfc->base + INTR_STS_EN_REG);
drivers/mtd/nand/raw/arasan-nand-controller.c
247
writel_relaxed(event, nfc->base + INTR_STS_REG);
drivers/mtd/nand/raw/arasan-nand-controller.c
274
writel_relaxed(nfc_op->pkt_reg, nfc->base + PKT_REG);
drivers/mtd/nand/raw/arasan-nand-controller.c
275
writel_relaxed(nfc_op->addr1_reg, nfc->base + MEM_ADDR1_REG);
drivers/mtd/nand/raw/arasan-nand-controller.c
276
writel_relaxed(nfc_op->addr2_reg, nfc->base + MEM_ADDR2_REG);
drivers/mtd/nand/raw/arasan-nand-controller.c
277
writel_relaxed(nfc_op->cmd_reg, nfc->base + CMD_REG);
drivers/mtd/nand/raw/arasan-nand-controller.c
278
writel_relaxed(nfc_op->prog_reg, nfc->base + PROG_REG);
drivers/mtd/nand/raw/arasan-nand-controller.c
345
writel_relaxed(anand->data_iface, nfc->base + DATA_INTERFACE_REG);
drivers/mtd/nand/raw/arasan-nand-controller.c
346
writel_relaxed(anand->timings, nfc->base + TIMING_REG);
drivers/mtd/nand/raw/arasan-nand-controller.c
429
writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG);
drivers/mtd/nand/raw/arasan-nand-controller.c
430
writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG);
drivers/mtd/nand/raw/arasan-nand-controller.c
542
writel_relaxed(anand->ecc_conf, nfc->base + ECC_CONF_REG);
drivers/mtd/nand/raw/arasan-nand-controller.c
543
writel_relaxed(ECC_SP_CMD1(NAND_CMD_RNDIN) |
drivers/mtd/nand/raw/arasan-nand-controller.c
553
writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG);
drivers/mtd/nand/raw/arasan-nand-controller.c
554
writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG);
drivers/mtd/nand/raw/arasan-nand-controller.c
716
writel_relaxed(remainder, nfc->base + DATA_PORT_REG);
drivers/mtd/nand/raw/atmel/pmecc.c
648
writel_relaxed(smu[(strength + 1) * num + i],
drivers/mtd/nand/raw/brcmnand/brcmnand.h
73
writel_relaxed(val, addr);
drivers/mtd/nand/raw/cadence-nand-controller.c
1054
writel_relaxed((u32)cdns_ctrl->dma_cdma_desc,
drivers/mtd/nand/raw/cadence-nand-controller.c
1056
writel_relaxed(0, cdns_ctrl->reg + CMD_REG3);
drivers/mtd/nand/raw/cadence-nand-controller.c
1063
writel_relaxed(reg, cdns_ctrl->reg + CMD_REG0);
drivers/mtd/nand/raw/cadence-nand-controller.c
1227
writel_relaxed(0, cdns_ctrl->reg + MULTIPLANE_CFG);
drivers/mtd/nand/raw/cadence-nand-controller.c
1228
writel_relaxed(0, cdns_ctrl->reg + CACHE_CFG);
drivers/mtd/nand/raw/cadence-nand-controller.c
1231
writel_relaxed(0xFFFFFFFF, cdns_ctrl->reg + INTR_STATUS);
drivers/mtd/nand/raw/cadence-nand-controller.c
1300
writel_relaxed(reg, cdns_ctrl->reg + TRAN_CFG_0);
drivers/mtd/nand/raw/cadence-nand-controller.c
1305
writel_relaxed(reg, cdns_ctrl->reg + TRAN_CFG_1);
drivers/mtd/nand/raw/cadence-nand-controller.c
1311
writel_relaxed(reg, cdns_ctrl->reg + CONTROL_DATA_CTRL);
drivers/mtd/nand/raw/cadence-nand-controller.c
1372
writel_relaxed(t->async_toggle_timings,
drivers/mtd/nand/raw/cadence-nand-controller.c
1374
writel_relaxed(t->timings0, cdns_ctrl->reg + TIMINGS0);
drivers/mtd/nand/raw/cadence-nand-controller.c
1375
writel_relaxed(t->timings1, cdns_ctrl->reg + TIMINGS1);
drivers/mtd/nand/raw/cadence-nand-controller.c
1376
writel_relaxed(t->timings2, cdns_ctrl->reg + TIMINGS2);
drivers/mtd/nand/raw/cadence-nand-controller.c
1379
writel_relaxed(t->dll_phy_ctrl, cdns_ctrl->reg + DLL_PHY_CTRL);
drivers/mtd/nand/raw/cadence-nand-controller.c
1381
writel_relaxed(t->phy_ctrl, cdns_ctrl->reg + PHY_CTRL);
drivers/mtd/nand/raw/cadence-nand-controller.c
1384
writel_relaxed(0, cdns_ctrl->reg + PHY_TSEL);
drivers/mtd/nand/raw/cadence-nand-controller.c
1385
writel_relaxed(2, cdns_ctrl->reg + PHY_DQ_TIMING);
drivers/mtd/nand/raw/cadence-nand-controller.c
1386
writel_relaxed(t->phy_dqs_timing,
drivers/mtd/nand/raw/cadence-nand-controller.c
1388
writel_relaxed(t->phy_gate_lpbk_ctrl,
drivers/mtd/nand/raw/cadence-nand-controller.c
1390
writel_relaxed(PHY_DLL_MASTER_CTRL_BYPASS_MODE,
drivers/mtd/nand/raw/cadence-nand-controller.c
1392
writel_relaxed(0, cdns_ctrl->reg + PHY_DLL_SLAVE_CTRL);
drivers/mtd/nand/raw/cadence-nand-controller.c
2839
writel_relaxed(reg, cdns_ctrl->reg + DLL_PHY_CTRL);
drivers/mtd/nand/raw/cadence-nand-controller.c
2840
writel_relaxed(OPR_MODE_NVDDR, cdns_ctrl->reg + COMMON_SET);
drivers/mtd/nand/raw/cadence-nand-controller.c
2841
writel_relaxed(NVDDR_TOGGLE_TIMINGS_0,
drivers/mtd/nand/raw/cadence-nand-controller.c
2843
writel_relaxed(NVDDR_TOGGLE_TIMINGS_1,
drivers/mtd/nand/raw/cadence-nand-controller.c
2845
writel_relaxed(NVDDR_ASYNC_TOGGLE_TIMINGS,
drivers/mtd/nand/raw/cadence-nand-controller.c
2847
writel_relaxed(t->sync_timings, cdns_ctrl->reg + SYNC_TIMINGS);
drivers/mtd/nand/raw/cadence-nand-controller.c
2848
writel_relaxed(t->timings0, cdns_ctrl->reg + TIMINGS0);
drivers/mtd/nand/raw/cadence-nand-controller.c
2849
writel_relaxed(t->timings1, cdns_ctrl->reg + TIMINGS1);
drivers/mtd/nand/raw/cadence-nand-controller.c
2850
writel_relaxed(t->timings2, cdns_ctrl->reg + TIMINGS2);
drivers/mtd/nand/raw/cadence-nand-controller.c
2851
writel_relaxed(t->dll_phy_ctrl, cdns_ctrl->reg + DLL_PHY_CTRL);
drivers/mtd/nand/raw/cadence-nand-controller.c
2852
writel_relaxed(t->phy_ctrl, cdns_ctrl->reg + PHY_CTRL);
drivers/mtd/nand/raw/cadence-nand-controller.c
2853
writel_relaxed(NVDDR_PHY_TSEL, cdns_ctrl->reg + PHY_TSEL);
drivers/mtd/nand/raw/cadence-nand-controller.c
2854
writel_relaxed(t->phy_dq_timing, cdns_ctrl->reg + PHY_DQ_TIMING);
drivers/mtd/nand/raw/cadence-nand-controller.c
2855
writel_relaxed(t->phy_dqs_timing, cdns_ctrl->reg + PHY_DQS_TIMING);
drivers/mtd/nand/raw/cadence-nand-controller.c
2856
writel_relaxed(t->phy_gate_lpbk_ctrl,
drivers/mtd/nand/raw/cadence-nand-controller.c
2858
writel_relaxed(NVDDR_PHY_DLL_MASTER_CTRL,
drivers/mtd/nand/raw/cadence-nand-controller.c
2860
writel_relaxed(NVDDR_PHY_DLL_SLAVE_CTRL,
drivers/mtd/nand/raw/cadence-nand-controller.c
2862
writel_relaxed(t->phy_ie_timing, cdns_ctrl->reg + PHY_IE_TIMING);
drivers/mtd/nand/raw/cadence-nand-controller.c
2863
writel_relaxed((reg | DLL_PHY_CTRL_DLL_RST_N),
drivers/mtd/nand/raw/cadence-nand-controller.c
3123
writel_relaxed(INTR_ENABLE_INTR_EN, cdns_ctrl->reg + INTR_ENABLE);
drivers/mtd/nand/raw/cadence-nand-controller.c
647
writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0);
drivers/mtd/nand/raw/cadence-nand-controller.c
663
writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0);
drivers/mtd/nand/raw/cadence-nand-controller.c
698
writel_relaxed(reg, cdns_ctrl->reg + SKIP_BYTES_CONF);
drivers/mtd/nand/raw/cadence-nand-controller.c
727
writel_relaxed(reg, cdns_ctrl->reg + SKIP_BYTES_CONF);
drivers/mtd/nand/raw/cadence-nand-controller.c
728
writel_relaxed(skip_bytes_offset, cdns_ctrl->reg + SKIP_BYTES_OFFSET);
drivers/mtd/nand/raw/cadence-nand-controller.c
747
writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0);
drivers/mtd/nand/raw/cadence-nand-controller.c
748
writel_relaxed(bitflips_threshold, cdns_ctrl->reg + ECC_CONFIG_1);
drivers/mtd/nand/raw/cadence-nand-controller.c
767
writel_relaxed(reg, cdns_ctrl->reg + COMMON_SET);
drivers/mtd/nand/raw/cadence-nand-controller.c
776
writel_relaxed(irq_status->status, cdns_ctrl->reg + INTR_STATUS);
drivers/mtd/nand/raw/cadence-nand-controller.c
777
writel_relaxed(irq_status->trd_status,
drivers/mtd/nand/raw/cadence-nand-controller.c
779
writel_relaxed(irq_status->trd_error,
drivers/mtd/nand/raw/cadence-nand-controller.c
846
writel_relaxed(INTR_ENABLE_INTR_EN | irq_mask->status,
drivers/mtd/nand/raw/cadence-nand-controller.c
849
writel_relaxed(irq_mask->trd_error,
drivers/mtd/nand/raw/cadence-nand-controller.c
897
writel_relaxed(mini_ctrl_cmd_l, cdns_ctrl->reg + CMD_REG2);
drivers/mtd/nand/raw/cadence-nand-controller.c
898
writel_relaxed(mini_ctrl_cmd_h, cdns_ctrl->reg + CMD_REG3);
drivers/mtd/nand/raw/cadence-nand-controller.c
906
writel_relaxed(reg, cdns_ctrl->reg + CMD_REG0);
drivers/mtd/nand/raw/fsmc_nand.c
278
writel_relaxed(value | tclr | tar, host->regs_va + FSMC_PC);
drivers/mtd/nand/raw/fsmc_nand.c
279
writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM);
drivers/mtd/nand/raw/fsmc_nand.c
280
writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB);
drivers/mtd/nand/raw/fsmc_nand.c
378
writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256,
drivers/mtd/nand/raw/fsmc_nand.c
380
writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCEN,
drivers/mtd/nand/raw/fsmc_nand.c
382
writel_relaxed(readl(host->regs_va + FSMC_PC) | FSMC_ECCEN,
drivers/mtd/nand/raw/fsmc_nand.c
572
writel_relaxed(p[i], host->data_va);
drivers/mtd/nand/raw/marvell_nand.c
1007
writel_relaxed(ndsr, nfc->regs + NDSR);
drivers/mtd/nand/raw/marvell_nand.c
1021
writel_relaxed(ndsr, nfc->regs + NDSR);
drivers/mtd/nand/raw/marvell_nand.c
1890
writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
drivers/mtd/nand/raw/marvell_nand.c
1962
writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
drivers/mtd/nand/raw/marvell_nand.c
2890
writel_relaxed(NDCR_ALL_INT | NDCR_ND_ARB_EN | NDCR_SPARE_EN |
drivers/mtd/nand/raw/marvell_nand.c
2892
writel_relaxed(0xFFFFFFFF, nfc->regs + NDSR);
drivers/mtd/nand/raw/marvell_nand.c
2893
writel_relaxed(0, nfc->regs + NDECCCTRL);
drivers/mtd/nand/raw/marvell_nand.c
525
writel_relaxed(reg | int_mask, nfc->regs + NDCR);
drivers/mtd/nand/raw/marvell_nand.c
534
writel_relaxed(reg & ~int_mask, nfc->regs + NDCR);
drivers/mtd/nand/raw/marvell_nand.c
542
writel_relaxed(int_mask, nfc->regs + NDSR);
drivers/mtd/nand/raw/marvell_nand.c
569
writel_relaxed(ndcr, nfc->regs + NDCR);
drivers/mtd/nand/raw/marvell_nand.c
587
writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
drivers/mtd/nand/raw/marvell_nand.c
624
writel_relaxed(readl(nfc->regs + NDSR), nfc->regs + NDSR);
drivers/mtd/nand/raw/marvell_nand.c
627
writel_relaxed(ndcr | NDCR_ND_RUN, nfc->regs + NDCR);
drivers/mtd/nand/raw/marvell_nand.c
637
writel_relaxed(NDSR_WRCMDREQ, nfc->regs + NDSR);
drivers/mtd/nand/raw/marvell_nand.c
653
writel_relaxed(to_nand_sel(marvell_nand)->ndcb0_csel | nfc_op->ndcb[0],
drivers/mtd/nand/raw/marvell_nand.c
655
writel_relaxed(nfc_op->ndcb[1], nfc->regs + NDCB0);
drivers/mtd/nand/raw/marvell_nand.c
695
writel_relaxed(flag, nfc->regs + NDSR);
drivers/mtd/nand/raw/marvell_nand.c
779
writel_relaxed(ndcr_generic | marvell_nand->ndcr, nfc->regs + NDCR);
drivers/mtd/nand/raw/marvell_nand.c
787
writel_relaxed(marvell_nand->ndtr0, nfc->regs + NDTR0);
drivers/mtd/nand/raw/marvell_nand.c
788
writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1);
drivers/mtd/nand/raw/marvell_nand.c
825
writel_relaxed(ndcr | NDCR_ECC_EN, nfc->regs + NDCR);
drivers/mtd/nand/raw/marvell_nand.c
832
writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL);
drivers/mtd/nand/raw/marvell_nand.c
842
writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR);
drivers/mtd/nand/raw/marvell_nand.c
844
writel_relaxed(0, nfc->regs + NDECCCTRL);
drivers/mtd/nand/raw/marvell_nand.c
854
writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR);
drivers/mtd/nand/raw/marvell_nand.c
862
writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR);
drivers/mtd/nand/raw/meson_nand.c
731
writel_relaxed(nfc->cmdfifo.cmd[i],
drivers/mtd/nand/raw/renesas-nand-controller.c
265
writel_relaxed(control, rnandc->regs + CONTROL_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
274
writel_relaxed(control, rnandc->regs + CONTROL_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
279
writel_relaxed(0, rnandc->regs + INT_STATUS_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
280
writel_relaxed(0, rnandc->regs + ECC_STAT_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
281
writel_relaxed(0, rnandc->regs + ECC_CNT_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
286
writel_relaxed(0, rnandc->regs + INT_MASK_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
292
writel_relaxed(val, rnandc->regs + INT_MASK_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
297
writel_relaxed(FIFO_INIT, rnandc->regs + FIFO_INIT_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
310
writel_relaxed(MEM_CTRL_CS(cs) | MEM_CTRL_DIS_WP(cs), rnandc->regs + MEM_CTRL_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
311
writel_relaxed(rnand->control, rnandc->regs + CONTROL_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
312
writel_relaxed(rnand->ecc_ctrl, rnandc->regs + ECC_CTRL_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
313
writel_relaxed(rnand->timings_asyn, rnandc->regs + TIMINGS_ASYN_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
314
writel_relaxed(rnand->tim_seq0, rnandc->regs + TIM_SEQ0_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
315
writel_relaxed(rnand->tim_seq1, rnandc->regs + TIM_SEQ1_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
316
writel_relaxed(rnand->tim_gen_seq0, rnandc->regs + TIM_GEN_SEQ0_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
317
writel_relaxed(rnand->tim_gen_seq1, rnandc->regs + TIM_GEN_SEQ1_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
318
writel_relaxed(rnand->tim_gen_seq2, rnandc->regs + TIM_GEN_SEQ2_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
319
writel_relaxed(rnand->tim_gen_seq3, rnandc->regs + TIM_GEN_SEQ3_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
327
writel_relaxed(rop->addr0_col, rnandc->regs + ADDR0_COL_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
328
writel_relaxed(rop->addr0_row, rnandc->regs + ADDR0_ROW_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
329
writel_relaxed(rop->addr1_col, rnandc->regs + ADDR1_COL_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
330
writel_relaxed(rop->addr1_row, rnandc->regs + ADDR1_ROW_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
331
writel_relaxed(rop->ecc_offset, rnandc->regs + ECC_OFFSET_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
332
writel_relaxed(rop->gen_seq_ctrl, rnandc->regs + GEN_SEQ_CTRL_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
333
writel_relaxed(DATA_SIZE(rop->len), rnandc->regs + DATA_SIZE_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
334
writel_relaxed(rop->command, rnandc->regs + COMMAND_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
339
writel_relaxed(DMA_CTRL_INCREMENT_BURST_4 |
drivers/mtd/nand/raw/renesas-nand-controller.c
881
writel_relaxed(last_bytes, rnandc->regs + FIFO_DATA_REG);
drivers/mtd/nand/raw/stm32_fmc2_nand.c
1270
writel_relaxed(*(u32 *)buf, io_addr_w);
drivers/mtd/nand/raw/tegra_nand.c
1056
writel_relaxed(nand->config, ctrl->regs + CONFIG);
drivers/mtd/nand/raw/tegra_nand.c
1192
writel_relaxed(HWSTATUS_CMD_DEFAULT, ctrl->regs + HWSTATUS_CMD);
drivers/mtd/nand/raw/tegra_nand.c
1193
writel_relaxed(HWSTATUS_MASK_DEFAULT, ctrl->regs + HWSTATUS_MASK);
drivers/mtd/nand/raw/tegra_nand.c
1194
writel_relaxed(INT_MASK, ctrl->regs + IER);
drivers/mtd/nand/raw/tegra_nand.c
1211
writel_relaxed(DMA_MST_CTRL_IS_DONE, ctrl->regs + DMA_MST_CTRL);
drivers/mtd/nand/raw/tegra_nand.c
282
writel_relaxed(dma, ctrl->regs + DMA_MST_CTRL);
drivers/mtd/nand/raw/tegra_nand.c
287
writel_relaxed(isr, ctrl->regs + ISR);
drivers/mtd/nand/raw/tegra_nand.c
335
writel_relaxed(0, ctrl->regs + DMA_MST_CTRL);
drivers/mtd/nand/raw/tegra_nand.c
336
writel_relaxed(0, ctrl->regs + COMMAND);
drivers/mtd/nand/raw/tegra_nand.c
340
writel_relaxed(isr, ctrl->regs + ISR);
drivers/mtd/nand/raw/tegra_nand.c
342
writel_relaxed(dma, ctrl->regs + DMA_MST_CTRL);
drivers/mtd/nand/raw/tegra_nand.c
372
writel_relaxed(instr->ctx.cmd.opcode,
drivers/mtd/nand/raw/tegra_nand.c
376
writel_relaxed(instr->ctx.cmd.opcode,
drivers/mtd/nand/raw/tegra_nand.c
394
writel_relaxed(addr1, ctrl->regs + ADDR_REG1);
drivers/mtd/nand/raw/tegra_nand.c
395
writel_relaxed(addr2, ctrl->regs + ADDR_REG2);
drivers/mtd/nand/raw/tegra_nand.c
416
writel_relaxed(reg, ctrl->regs + RESP);
drivers/mtd/nand/raw/tegra_nand.c
426
writel_relaxed(cmd, ctrl->regs + COMMAND);
drivers/mtd/nand/raw/tegra_nand.c
486
writel_relaxed(nand->bch_config, ctrl->regs + BCH_CONFIG);
drivers/mtd/nand/raw/tegra_nand.c
488
writel_relaxed(0, ctrl->regs + BCH_CONFIG);
drivers/mtd/nand/raw/tegra_nand.c
491
writel_relaxed(nand->config_ecc, ctrl->regs + CONFIG);
drivers/mtd/nand/raw/tegra_nand.c
493
writel_relaxed(nand->config, ctrl->regs + CONFIG);
drivers/mtd/nand/raw/tegra_nand.c
509
writel_relaxed(NAND_CMD_READ0, ctrl->regs + CMD_REG1);
drivers/mtd/nand/raw/tegra_nand.c
510
writel_relaxed(NAND_CMD_READSTART, ctrl->regs + CMD_REG2);
drivers/mtd/nand/raw/tegra_nand.c
512
writel_relaxed(NAND_CMD_SEQIN, ctrl->regs + CMD_REG1);
drivers/mtd/nand/raw/tegra_nand.c
513
writel_relaxed(NAND_CMD_PAGEPROG, ctrl->regs + CMD_REG2);
drivers/mtd/nand/raw/tegra_nand.c
522
writel_relaxed(addr1, ctrl->regs + ADDR_REG1);
drivers/mtd/nand/raw/tegra_nand.c
525
writel_relaxed(page >> 16, ctrl->regs + ADDR_REG2);
drivers/mtd/nand/raw/tegra_nand.c
539
writel_relaxed(mtd->writesize - 1, ctrl->regs + DMA_CFG_A);
drivers/mtd/nand/raw/tegra_nand.c
540
writel_relaxed(dma_addr, ctrl->regs + DATA_PTR);
drivers/mtd/nand/raw/tegra_nand.c
553
writel_relaxed(oob_len - 1, ctrl->regs + DMA_CFG_B);
drivers/mtd/nand/raw/tegra_nand.c
554
writel_relaxed(dma_addr_oob, ctrl->regs + TAG_PTR);
drivers/mtd/nand/raw/tegra_nand.c
571
writel_relaxed(dma_ctrl, ctrl->regs + DMA_MST_CTRL);
drivers/mtd/nand/raw/tegra_nand.c
586
writel_relaxed(cmd, ctrl->regs + COMMAND);
drivers/mtd/nand/raw/tegra_nand.c
811
writel_relaxed(reg, ctrl->regs + TIMING_1);
drivers/mtd/nand/raw/tegra_nand.c
816
writel_relaxed(reg, ctrl->regs + TIMING_2);
drivers/net/can/at91_can.c
293
writel_relaxed(value, priv->reg_base + reg);
drivers/net/dsa/bcm_sf2.h
141
writel_relaxed(val, priv->name + off); \
drivers/net/dsa/bcm_sf2.h
191
writel_relaxed(val, priv->core + tmp);
drivers/net/dsa/bcm_sf2.h
201
writel_relaxed(val, priv->reg + priv->reg_offsets[off]);
drivers/net/dsa/bcm_sf2.h
220
writel_relaxed(val, priv->reg + priv->reg_offsets[off] + reg);
drivers/net/ethernet/amazon/ena/ena_com.c
2347
writel_relaxed((u32)aenq->head, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
drivers/net/ethernet/broadcom/asp2/bcmasp.h
410
writel_relaxed(val, intf->m + off); \
drivers/net/ethernet/broadcom/asp2/bcmasp.h
484
writel_relaxed(val, priv->base + (offset) + off); \
drivers/net/ethernet/broadcom/asp2/bcmasp.h
507
writel_relaxed(val, priv->base + priv->name##_offset + \
drivers/net/ethernet/broadcom/bcmsysport.c
44
writel_relaxed(val, priv->base + SYS_PORT_RDMA_OFFSET + off);
drivers/net/ethernet/broadcom/bcmsysport.c
88
writel_relaxed(upper_32_bits(addr) & DESC_ADDR_HI_MASK,
drivers/net/ethernet/broadcom/bcmsysport.c
91
writel_relaxed(lower_32_bits(addr), d + DESC_ADDR_LO);
drivers/net/ethernet/broadcom/bcmsysport.h
787
writel_relaxed(val, priv->base + (offset) + off); \
drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
176
writel_relaxed((u32)val, REG_ADDR(bp, offset))
drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
774
writel_relaxed((u32)(val), (bp)->doorbells + ((bp)->db_size * (cid)))
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2871
writel_relaxed(db_val, db->doorbell);
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2873
writel_relaxed(db_val, db->doorbell);
drivers/net/ethernet/broadcom/genet/bcmgenet.c
76
writel_relaxed(value, offset);
drivers/net/ethernet/broadcom/genet/bcmgenet.h
713
writel_relaxed(val, priv->base + offset + off); \
drivers/net/ethernet/cadence/macb_main.c
212
writel_relaxed(value, bp->regs + offset);
drivers/net/ethernet/hisilicon/hip04_eth.c
284
writel_relaxed(val, priv->base + GE_PORT_MODE);
drivers/net/ethernet/hisilicon/hip04_eth.c
287
writel_relaxed(val, priv->base + GE_DUPLEX_TYPE);
drivers/net/ethernet/hisilicon/hip04_eth.c
290
writel_relaxed(val, priv->base + GE_MODE_CHANGE_REG);
drivers/net/ethernet/hisilicon/hip04_eth.c
296
writel_relaxed(RESET_DREQ_ALL, priv->sysctrl_base + SC_PPE_RESET_DREQ);
drivers/net/ethernet/hisilicon/hip04_eth.c
318
writel_relaxed(val, priv->base + PPE_CFG_STS_MODE);
drivers/net/ethernet/hisilicon/hip04_eth.c
325
writel_relaxed(val, priv->base + PPE_CFG_QOS_VMID_GEN);
drivers/net/ethernet/hisilicon/hip04_eth.c
336
writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG);
drivers/net/ethernet/hisilicon/hip04_eth.c
339
writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG);
drivers/net/ethernet/hisilicon/hip04_eth.c
342
writel_relaxed(val, priv->base + PPE_CFG_BUS_CTRL_REG);
drivers/net/ethernet/hisilicon/hip04_eth.c
345
writel_relaxed(val, priv->base + PPE_CFG_MAX_FRAME_LEN_REG);
drivers/net/ethernet/hisilicon/hip04_eth.c
348
writel_relaxed(val, priv->base + GE_MAX_FRM_SIZE_REG);
drivers/net/ethernet/hisilicon/hip04_eth.c
351
writel_relaxed(val, priv->base + GE_SHORT_RUNTS_THR_REG);
drivers/net/ethernet/hisilicon/hip04_eth.c
355
writel_relaxed(val, priv->base + GE_TRANSMIT_CONTROL_REG);
drivers/net/ethernet/hisilicon/hip04_eth.c
358
writel_relaxed(val, priv->base + GE_CF_CRC_STRIP_REG);
drivers/net/ethernet/hisilicon/hip04_eth.c
362
writel_relaxed(val, priv->base + GE_RECV_CONTROL_REG);
drivers/net/ethernet/hisilicon/hip04_eth.c
366
writel_relaxed(val, priv->base + GE_TX_LOCAL_PAGE_REG);
drivers/net/ethernet/hisilicon/hip04_eth.c
378
writel_relaxed(val, priv->base + GE_PORT_EN);
drivers/net/ethernet/hisilicon/hip04_eth.c
382
writel_relaxed(val, priv->base + PPE_RINT);
drivers/net/ethernet/hisilicon/hip04_eth.c
386
writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_INT);
drivers/net/ethernet/hisilicon/hip04_eth.c
390
writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
drivers/net/ethernet/hisilicon/hip04_eth.c
400
writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
drivers/net/ethernet/hisilicon/hip04_eth.c
405
writel_relaxed(val, priv->base + GE_PORT_EN);
drivers/net/ethernet/hisilicon/hip04_eth.c
433
writel_relaxed(((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1])),
drivers/net/ethernet/hisilicon/hip04_eth.c
435
writel_relaxed(((ndev->dev_addr[2] << 24) | (ndev->dev_addr[3] << 16) |
drivers/net/ethernet/hisilicon/hip04_eth.c
561
writel_relaxed(DEF_INT_MASK & ~RCV_INT,
drivers/net/ethernet/hisilicon/hip04_eth.c
650
writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
drivers/net/ethernet/hisilicon/hip04_eth.c
671
writel_relaxed(DEF_INT_MASK, priv->base + PPE_RINT);
drivers/net/ethernet/hisilicon/hip04_eth.c
688
writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
drivers/net/ethernet/hisilicon/hip04_eth.c
705
writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
316
writel_relaxed(val, priv->ctrl_base);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
319
writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
326
writel_relaxed(val, priv->base + PORT_MODE);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
327
writel_relaxed(0, priv->base + MODE_CHANGE_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
328
writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
333
writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
334
writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
335
writel_relaxed(0, priv->base + RX_FQ_REG_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
337
writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
338
writel_relaxed(rx << 3, priv->base + RX_BQ_DEPTH);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
339
writel_relaxed(0, priv->base + RX_BQ_REG_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
341
writel_relaxed(BITS_TX_BQ_DEPTH_EN, priv->base + TX_BQ_REG_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
342
writel_relaxed(tx << 3, priv->base + TX_BQ_DEPTH);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
343
writel_relaxed(0, priv->base + TX_BQ_REG_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
345
writel_relaxed(BITS_TX_RQ_DEPTH_EN, priv->base + TX_RQ_REG_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
346
writel_relaxed(tx << 3, priv->base + TX_RQ_DEPTH);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
347
writel_relaxed(0, priv->base + TX_RQ_REG_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
352
writel_relaxed(BITS_RX_FQ_START_ADDR_EN, priv->base + RX_FQ_REG_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
353
writel_relaxed(phy_addr, priv->base + RX_FQ_START_ADDR);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
354
writel_relaxed(0, priv->base + RX_FQ_REG_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
359
writel_relaxed(BITS_RX_BQ_START_ADDR_EN, priv->base + RX_BQ_REG_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
360
writel_relaxed(phy_addr, priv->base + RX_BQ_START_ADDR);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
361
writel_relaxed(0, priv->base + RX_BQ_REG_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
366
writel_relaxed(BITS_TX_BQ_START_ADDR_EN, priv->base + TX_BQ_REG_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
367
writel_relaxed(phy_addr, priv->base + TX_BQ_START_ADDR);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
368
writel_relaxed(0, priv->base + TX_BQ_REG_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
373
writel_relaxed(BITS_TX_RQ_START_ADDR_EN, priv->base + TX_RQ_REG_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
374
writel_relaxed(phy_addr, priv->base + TX_RQ_START_ADDR);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
375
writel_relaxed(0, priv->base + TX_RQ_REG_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
391
writel_relaxed(0, priv->base + ENA_PMU_INT);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
392
writel_relaxed(~0, priv->base + RAW_PMU_INT);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
394
writel_relaxed(BIT_CRC_ERR_PASS, priv->base + REC_FILT_CONTROL);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
395
writel_relaxed(MAC_MAX_FRAME_SIZE, priv->base + CONTROL_WORD);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
396
writel_relaxed(0, priv->base + COL_SLOT_TIME);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
399
writel_relaxed(val, priv->base + IN_QUEUE_TH);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
401
writel_relaxed(RX_BQ_IN_TIMEOUT, priv->base + RX_BQ_IN_TIMEOUT_TH);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
402
writel_relaxed(TX_RQ_IN_TIMEOUT, priv->base + TX_RQ_IN_TIMEOUT_TH);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
410
writel_relaxed(DEF_INT_MASK, priv->base + ENA_PMU_INT);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
415
writel_relaxed(0, priv->base + ENA_PMU_INT);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
420
writel_relaxed(0xf, priv->base + DESC_WR_RD_ENA);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
421
writel_relaxed(BITS_RX_EN | BITS_TX_EN, priv->base + PORT_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
426
writel_relaxed(~(u32)(BITS_RX_EN | BITS_TX_EN), priv->base + PORT_EN);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
427
writel_relaxed(0, priv->base + DESC_WR_RD_ENA);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
437
writel_relaxed(val, priv->base + STATION_ADDR_HIGH);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
440
writel_relaxed(val, priv->base + STATION_ADDR_LOW);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
506
writel_relaxed(dma_byte(pos), priv->base + RX_FQ_WR_ADDR);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
560
writel_relaxed(dma_byte(pos), priv->base + RX_BQ_RD_ADDR);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
630
writel_relaxed(dma_byte(pos), priv->base + TX_RQ_RD_ADDR);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
658
writel_relaxed(ints, priv->base + RAW_PMU_INT);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
675
writel_relaxed(ints, priv->base + RAW_PMU_INT);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
784
writel_relaxed(dma_byte(pos), priv->base + TX_BQ_WR_ADDR);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
943
writel_relaxed(MDIO_READ | phy << 8 | reg, base + MDIO_SINGLE_CMD);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
971
writel_relaxed(val, base + MDIO_SINGLE_DATA);
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
972
writel_relaxed(MDIO_WRITE | phy << 8 | reg, base + MDIO_SINGLE_CMD);
drivers/net/ethernet/hisilicon/hns/hnae.h
579
#define hnae_queue_xmit(q, buf_num) writel_relaxed(buf_num, \
drivers/net/ethernet/hisilicon/hns/hns_enet.c
712
writel_relaxed(i, ring->io_base + RCB_REG_HEAD);
drivers/net/ethernet/hisilicon/hns_mdio.c
97
writel_relaxed(value, base + reg);
drivers/net/ethernet/intel/i40e/i40e_txrx.c
2317
writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail);
drivers/net/ethernet/intel/ice/ice_ethtool.c
1215
writel_relaxed(tx_ring->next_to_use, tx_ring->tail);
drivers/net/ethernet/intel/ice/ice_txrx.c
1556
writel_relaxed(j, tstamp_ring->tail);
drivers/net/ethernet/intel/ice/ice_txrx.c
1558
writel_relaxed(i, tx_ring->tail);
drivers/net/ethernet/intel/ice/ice_txrx_lib.h
106
writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail);
drivers/net/ethernet/intel/idpf/xdp.h
75
writel_relaxed(xdpsq->next_to_use, xdpsq->tail);
drivers/net/ethernet/marvell/mvneta_bm.h
152
writel_relaxed(buf_phys_addr, priv->bppi_virt_addr +
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
173
writel_relaxed(data, priv->swth_base[thread] + offset);
drivers/net/ethernet/marvell/mvpp2/mvpp2_tai.c
77
writel_relaxed(val & 0xffff, reg);
drivers/net/ethernet/marvell/prestera/prestera_pci.c
602
writel_relaxed(*(u32 *)(buf + i), prestera_ldr_wr_ptr(fw));
drivers/net/ethernet/marvell/pxa168_eth.c
280
writel_relaxed(data, pep->base + offset);
drivers/net/ethernet/qlogic/qla3xxx.c
1858
writel_relaxed(qdev->small_buf_q_producer_index,
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
480
writel_relaxed(0, adapter->isr_int_vec);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
558
writel_relaxed(csr1, adpt->csr + EMAC_EMAC_WRAPPER_CSR1);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
560
writel_relaxed(mac, adpt->base + EMAC_MAC_CTRL);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
566
writel_relaxed(adpt->irq_mod, adpt->base + EMAC_IRQ_MOD_TIM_INIT);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
567
writel_relaxed(INT_RD_CLR_EN | LPW_MODE | IRQ_MODERATOR_EN |
drivers/net/ethernet/qualcomm/emac/emac-sgmii.c
110
writel_relaxed(irq_bits, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR);
drivers/net/ethernet/qualcomm/emac/emac-sgmii.c
111
writel_relaxed(IRQ_GLOBAL_CLEAR, phy->base + EMAC_SGMII_PHY_IRQ_CMD);
drivers/net/ethernet/qualcomm/emac/emac-sgmii.c
129
writel_relaxed(0, phy->base + EMAC_SGMII_PHY_IRQ_CMD);
drivers/net/ethernet/qualcomm/emac/emac-sgmii.c
130
writel_relaxed(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR);
drivers/net/ethernet/ti/cpsw.c
723
writel_relaxed(CPDMA_TX_PRIORITY_MAP,
drivers/net/ethernet/ti/cpsw.c
725
writel_relaxed(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
drivers/net/ethernet/ti/cpsw.c
826
writel_relaxed(0, &cpsw->regs->ptype);
drivers/net/ethernet/ti/cpsw.c
829
writel_relaxed(0x7, &cpsw->regs->stat_port_en);
drivers/net/ethernet/ti/cpsw_ale.c
1154
writel_relaxed(tmp, ale->params.ale_regs + offset);
drivers/net/ethernet/ti/cpsw_ale.c
1651
writel_relaxed(idx, ale->params.ale_regs + ALE_POLICER_TBL_CTL);
drivers/net/ethernet/ti/cpsw_ale.c
1659
writel_relaxed(idx, ale->params.ale_regs + ALE_POLICER_TBL_CTL);
drivers/net/ethernet/ti/cpsw_ale.c
348
writel_relaxed(idx, ale->params.ale_regs + ALE_TABLE_CONTROL);
drivers/net/ethernet/ti/cpsw_ale.c
364
writel_relaxed(ale_entry[i], ale->params.ale_regs +
drivers/net/ethernet/ti/cpsw_ale.c
367
writel_relaxed(idx | ALE_TABLE_WRITE, ale->params.ale_regs +
drivers/net/ethernet/ti/cpsw_new.c
587
writel_relaxed(CPDMA_TX_PRIORITY_MAP,
drivers/net/ethernet/ti/cpsw_new.c
589
writel_relaxed(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
drivers/net/ethernet/ti/cpsw_new.c
592
writel_relaxed(0, &cpsw->regs->ptype);
drivers/net/ethernet/ti/cpsw_new.c
595
writel_relaxed(0x7, &cpsw->regs->stat_port_en);
drivers/net/ethernet/ti/cpsw_priv.c
282
writel_relaxed(1, reg);
drivers/net/ethernet/ti/cpsw_priv.c
38
writel_relaxed(0xFF, &cpsw->wr_regs->tx_en);
drivers/net/ethernet/ti/cpsw_priv.c
39
writel_relaxed(0xFF, &cpsw->wr_regs->rx_en);
drivers/net/ethernet/ti/cpsw_priv.c
46
writel_relaxed(0, &cpsw->wr_regs->tx_en);
drivers/net/ethernet/ti/cpsw_priv.c
47
writel_relaxed(0, &cpsw->wr_regs->rx_en);
drivers/net/ethernet/ti/cpsw_priv.c
613
writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype);
drivers/net/ethernet/ti/cpsw_priv.c
614
writel_relaxed(ETH_P_8021Q, &cpsw->regs->vlan_ltype);
drivers/net/ethernet/ti/cpsw_priv.c
799
writel_relaxed(val, &cpsw->regs->ptype);
drivers/net/ethernet/ti/cpsw_priv.h
323
writel_relaxed(val, slave->regs + offset);
drivers/net/ethernet/ti/cpts.c
33
#define cpts_write32(c, v, r) writel_relaxed(v, &c->reg->r)
drivers/net/ethernet/ti/davinci_cpdma.c
1060
writel_relaxed(0, &desc->hw_next);
drivers/net/ethernet/ti/davinci_cpdma.c
1061
writel_relaxed(buffer, &desc->hw_buffer);
drivers/net/ethernet/ti/davinci_cpdma.c
1062
writel_relaxed(len, &desc->hw_len);
drivers/net/ethernet/ti/davinci_cpdma.c
1063
writel_relaxed(mode | len, &desc->hw_mode);
drivers/net/ethernet/ti/davinci_cpdma.c
1064
writel_relaxed((uintptr_t)si->token, &desc->sw_token);
drivers/net/ethernet/ti/davinci_cpdma.c
1065
writel_relaxed(buffer, &desc->sw_buffer);
drivers/net/ethernet/ti/davinci_cpdma.c
1066
writel_relaxed(si->data_dma ? len | CPDMA_DMA_EXT_MAP : len,
drivers/net/ethernet/ti/icssm/icssm_prueth.c
47
writel_relaxed(val, prueth->mem[region].va + reg);
drivers/net/fddi/defza.c
82
#define writel_o writel_relaxed
drivers/net/fddi/defza.c
92
#define writel_u writel_relaxed
drivers/net/mdio/mdio-bcm-unimac.c
64
writel_relaxed(val, priv->base + offset);
drivers/net/mdio/mdio-mux-meson-g12a.c
189
writel_relaxed(0x0, priv->regs + ETH_PHY_CNTL2);
drivers/net/wireless/ath/wil6210/debugfs.c
385
writel_relaxed(val, (void __iomem *)d->offset);
drivers/nvmem/microchip-otpc.c
181
writel_relaxed(0UL, otpc->base + MCHP_OTPC_AR);
drivers/nvmem/microchip-otpc.c
82
writel_relaxed(tmp, otpc->base + MCHP_OTPC_MR);
drivers/nvmem/microchip-otpc.c
87
writel_relaxed(tmp, otpc->base + MCHP_OTPC_CR);
drivers/pci/controller/dwc/pcie-al.c
150
writel_relaxed(val, pcie->controller_base + offset);
drivers/pci/controller/dwc/pcie-amd-mdb.c
111
writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC);
drivers/pci/controller/dwc/pcie-amd-mdb.c
186
writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC);
drivers/pci/controller/dwc/pcie-amd-mdb.c
200
writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC);
drivers/pci/controller/dwc/pcie-amd-mdb.c
235
writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC);
drivers/pci/controller/dwc/pcie-amd-mdb.c
258
writel_relaxed(AMD_MDB_PCIE_IMR_ALL_MASK,
drivers/pci/controller/dwc/pcie-amd-mdb.c
264
writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC);
drivers/pci/controller/dwc/pcie-amd-mdb.c
267
writel_relaxed(AMD_MDB_PCIE_IMR_ALL_MASK,
drivers/pci/controller/dwc/pcie-amd-mdb.c
91
writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC);
drivers/pci/controller/dwc/pcie-dw-rockchip.c
116
writel_relaxed(val, rockchip->apb_base + reg);
drivers/pci/controller/dwc/pcie-fu740.c
137
writel_relaxed(addr, phy_cr_para_addr);
drivers/pci/controller/dwc/pcie-fu740.c
138
writel_relaxed(wrdata, phy_cr_para_wr_data);
drivers/pci/controller/dwc/pcie-fu740.c
139
writel_relaxed(1, phy_cr_para_wr_en);
drivers/pci/controller/dwc/pcie-fu740.c
147
writel_relaxed(0, phy_cr_para_wr_en);
drivers/pci/controller/dwc/pcie-fu740.c
158
writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_SEL);
drivers/pci/controller/dwc/pcie-fu740.c
159
writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_SEL);
drivers/pci/controller/dwc/pcie-fu740.c
203
writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE);
drivers/pci/controller/dwc/pcie-fu740.c
258
writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
drivers/pci/controller/dwc/pcie-fu740.c
272
writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
drivers/pci/controller/dwc/pcie-fu740.c
276
writel_relaxed(0x4, afp->mgmt_base + PCIEX8MGMT_DEVICE_TYPE);
drivers/pci/controller/dwc/pcie-fu740.c
85
writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_PERST_N);
drivers/pci/controller/dwc/pcie-fu740.c
91
writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PERST_N);
drivers/pci/controller/dwc/pcie-qcom-ep.c
435
writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG);
drivers/pci/controller/dwc/pcie-qcom-ep.c
442
writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN);
drivers/pci/controller/dwc/pcie-qcom-ep.c
445
writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE);
drivers/pci/controller/dwc/pcie-qcom-ep.c
450
writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
drivers/pci/controller/dwc/pcie-qcom-ep.c
455
writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
drivers/pci/controller/dwc/pcie-qcom-ep.c
460
writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
drivers/pci/controller/dwc/pcie-qcom-ep.c
465
writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH);
drivers/pci/controller/dwc/pcie-qcom-ep.c
478
writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL);
drivers/pci/controller/dwc/pcie-qcom-ep.c
485
writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL);
drivers/pci/controller/dwc/pcie-qcom-ep.c
490
writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS);
drivers/pci/controller/dwc/pcie-qcom-ep.c
510
writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK);
drivers/pci/controller/dwc/pcie-qcom-ep.c
514
writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK);
drivers/pci/controller/dwc/pcie-qcom-ep.c
519
writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_5_MASK);
drivers/pci/controller/dwc/pcie-qcom-ep.c
524
writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_3_MASK);
drivers/pci/controller/dwc/pcie-qcom-ep.c
541
writel_relaxed(pcie_ep->mmio_res->start,
drivers/pci/controller/dwc/pcie-qcom-ep.c
543
writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
drivers/pci/controller/dwc/pcie-qcom-ep.c
548
writel_relaxed(val, pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
drivers/pci/controller/dwc/pcie-qcom-ep.c
555
writel_relaxed(val, pcie_ep->parf + PARF_LTSSM);
drivers/pci/controller/dwc/pcie-qcom-ep.c
558
writel_relaxed(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
drivers/pci/controller/dwc/pcie-qcom-ep.c
696
writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR);
drivers/pci/controller/dwc/pcie-qcom-ep.c
711
writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
drivers/pci/controller/dwc/pcie-qcom-ep.c
719
writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
drivers/pci/controller/dwc/pcie-sophgo.c
41
writel_relaxed(val, sophgo->app_base + reg);
drivers/pci/controller/dwc/pcie-spacemit-k1.c
223
writel_relaxed(MSI_CTRL_INT, k1->link + INTR_ENABLE);
drivers/pci/controller/dwc/pcie-spacemit-k1.c
228
writel_relaxed(val, k1->link + K1_PHY_AHB_IRQ_EN);
drivers/pci/controller/dwc/pcie-spacemit-k1.c
241
writel_relaxed(val, k1->link + K1_PHY_AHB_IRQ_EN);
drivers/pci/controller/dwc/pcie-spacemit-k1.c
243
writel_relaxed(0, k1->link + INTR_ENABLE);
drivers/pci/controller/dwc/pcie-tegra194.c
295
writel_relaxed(value, pcie->appl_base + reg);
drivers/pci/controller/dwc/pcie-visconti.c
110
writel_relaxed(val, pcie->smu_base + reg);
drivers/pci/controller/dwc/pcie-visconti.c
116
writel_relaxed(val, pcie->mpu_base + reg);
drivers/pci/controller/dwc/pcie-visconti.c
99
writel_relaxed(val, pcie->ulreg_base + reg);
drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
208
writel_relaxed(lower_32_bits(msg_addr),
drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
210
writel_relaxed(upper_32_bits(msg_addr),
drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
212
writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
213
writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
drivers/pci/controller/pcie-altera-msi.c
44
writel_relaxed(value, msi->csr_base + reg);
drivers/pci/controller/pcie-altera.c
151
writel_relaxed(value, pcie->cra_base + reg);
drivers/pci/controller/pcie-altera.c
523
writel_relaxed(value, addr);
drivers/pci/controller/pcie-apple.c
210
writel_relaxed(readl_relaxed(addr) | set, addr);
drivers/pci/controller/pcie-apple.c
215
writel_relaxed(readl_relaxed(addr) & ~clr, addr);
drivers/pci/controller/pcie-apple.c
311
writel_relaxed(BIT(data->hwirq), port->base + PORT_INTSTAT);
drivers/pci/controller/pcie-apple.c
419
writel_relaxed(~0, port->base + PORT_INTMSK);
drivers/pci/controller/pcie-apple.c
420
writel_relaxed(~0, port->base + PORT_INTSTAT);
drivers/pci/controller/pcie-apple.c
421
writel_relaxed(~0, port->base + PORT_LINKCMDSTS);
drivers/pci/controller/pcie-apple.c
427
writel_relaxed(lower_32_bits(DOORBELL_ADDR),
drivers/pci/controller/pcie-apple.c
430
writel_relaxed(0, port->base + pcie->hw->port_msiaddr_hi);
drivers/pci/controller/pcie-apple.c
435
writel_relaxed(FIELD_PREP(PORT_MSIMAP_TARGET, i) |
drivers/pci/controller/pcie-apple.c
439
writel_relaxed(0, port->base + PORT_MSIBASE);
drivers/pci/controller/pcie-apple.c
443
writel_relaxed(val | PORT_MSICFG_EN, port->base + PORT_MSICFG);
drivers/pci/controller/pcie-apple.c
548
writel_relaxed(val, port_rid2sid_addr(port, idx));
drivers/pci/controller/pcie-apple.c
661
writel_relaxed(PORT_LTSSMCTL_START, port->base + PORT_LTSSMCTL);
drivers/pci/controller/pcie-brcmstb.c
1109
writel_relaxed(tmp, base + reg_offset);
drivers/pci/controller/pcie-brcmstb.c
1111
writel_relaxed(upper_32_bits(pci_offset), base + reg_offset + 4);
drivers/pci/controller/pcie-brcmstb.c
1124
writel_relaxed(tmp, base + reg_offset);
drivers/pci/controller/pcie-brcmstb.c
1126
writel_relaxed(tmp, base + reg_offset + 4);
drivers/pci/controller/pcie-iproc-msi.c
142
writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]);
drivers/pci/controller/pcie-mediatek-gen3.c
1008
writel_relaxed(val, pcie->base + PCIE_EQ_PRESET_01_REG);
drivers/pci/controller/pcie-mediatek-gen3.c
1014
writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG);
drivers/pci/controller/pcie-mediatek-gen3.c
1255
writel_relaxed(pcie->saved_irq_state, pcie->base + PCIE_INT_ENABLE_REG);
drivers/pci/controller/pcie-mediatek-gen3.c
1260
writel_relaxed(msi_set->saved_irq_state,
drivers/pci/controller/pcie-mediatek-gen3.c
1273
writel_relaxed(val, pcie->base + PCIE_ICMD_PM_REG);
drivers/pci/controller/pcie-mediatek-gen3.c
1299
writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
drivers/pci/controller/pcie-mediatek-gen3.c
278
writel_relaxed(val, pcie->base + PCIE_CFGNUM_REG);
drivers/pci/controller/pcie-mediatek-gen3.c
344
writel_relaxed(lower_32_bits(cpu_addr) | PCIE_ATR_SIZE(fls(table_size) - 1), table);
drivers/pci/controller/pcie-mediatek-gen3.c
345
writel_relaxed(upper_32_bits(cpu_addr), table + PCIE_ATR_SRC_ADDR_MSB_OFFSET);
drivers/pci/controller/pcie-mediatek-gen3.c
346
writel_relaxed(lower_32_bits(pci_addr), table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET);
drivers/pci/controller/pcie-mediatek-gen3.c
347
writel_relaxed(upper_32_bits(pci_addr), table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET);
drivers/pci/controller/pcie-mediatek-gen3.c
357
writel_relaxed(val, table + PCIE_ATR_TRSL_PARAM_OFFSET);
drivers/pci/controller/pcie-mediatek-gen3.c
391
writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base);
drivers/pci/controller/pcie-mediatek-gen3.c
392
writel_relaxed(upper_32_bits(msi_set->msg_addr),
drivers/pci/controller/pcie-mediatek-gen3.c
399
writel_relaxed(val, pcie->base + PCIE_MSI_SET_ENABLE_REG);
drivers/pci/controller/pcie-mediatek-gen3.c
403
writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
drivers/pci/controller/pcie-mediatek-gen3.c
433
writel_relaxed(val, pcie->base + PCIE_SETTING_REG);
drivers/pci/controller/pcie-mediatek-gen3.c
440
writel_relaxed(val, pcie->base + PCIE_CONF_LINK2_CTL_STS);
drivers/pci/controller/pcie-mediatek-gen3.c
448
writel_relaxed(val, pcie->base + PCIE_RESOURCE_CTRL_REG);
drivers/pci/controller/pcie-mediatek-gen3.c
455
writel_relaxed(val, pcie->base + PCIE_PCI_IDS_1);
drivers/pci/controller/pcie-mediatek-gen3.c
460
writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
drivers/pci/controller/pcie-mediatek-gen3.c
465
writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG);
drivers/pci/controller/pcie-mediatek-gen3.c
479
writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
drivers/pci/controller/pcie-mediatek-gen3.c
492
writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
drivers/pci/controller/pcie-mediatek-gen3.c
581
writel_relaxed(BIT(hwirq), msi_set->base + PCIE_MSI_SET_STATUS_OFFSET);
drivers/pci/controller/pcie-mediatek-gen3.c
596
writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
drivers/pci/controller/pcie-mediatek-gen3.c
612
writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
drivers/pci/controller/pcie-mediatek-gen3.c
683
writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
drivers/pci/controller/pcie-mediatek-gen3.c
696
writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
drivers/pci/controller/pcie-mediatek-gen3.c
714
writel_relaxed(BIT(hwirq), pcie->base + PCIE_INT_STATUS_REG);
drivers/pci/controller/pcie-mediatek-gen3.c
842
writel_relaxed(BIT(irq_bit), pcie->base + PCIE_INT_STATUS_REG);
drivers/pci/controller/pcie-mt7621.c
112
writel_relaxed(val, pcie->base + reg);
drivers/pci/controller/pcie-mt7621.c
123
writel_relaxed(val, port->base + reg);
drivers/pci/controller/pcie-mt7621.c
133
writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
drivers/pci/controller/pcie-rzg3s-host.c
1041
writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
drivers/pci/controller/pcie-rzg3s-host.c
1045
writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L);
drivers/pci/controller/pcie-rzg3s-host.c
1046
writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U);
drivers/pci/controller/pcie-rzg3s-host.c
1049
writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
drivers/pci/controller/pcie-rzg3s-host.c
1069
writel_relaxed(RZG3S_PCI_PEIS0_DL_UPDOWN |
drivers/pci/controller/pcie-rzg3s-host.c
1074
writel_relaxed(0, host->axi + RZG3S_PCI_PEIE0);
drivers/pci/controller/pcie-rzg3s-host.c
1077
writel_relaxed(~0U, host->axi + RZG3S_PCI_PEIS1);
drivers/pci/controller/pcie-rzg3s-host.c
1080
writel_relaxed(0, host->axi + RZG3S_PCI_PEIE1);
drivers/pci/controller/pcie-rzg3s-host.c
1083
writel_relaxed(~0U, host->axi + RZG3S_PCI_AMEIS);
drivers/pci/controller/pcie-rzg3s-host.c
1086
writel_relaxed(~0U, host->axi + RZG3S_PCI_ASEIS1);
drivers/pci/controller/pcie-rzg3s-host.c
1089
writel_relaxed(~0U, host->axi + RZG3S_PCI_MSGRCVIS);
drivers/pci/controller/pcie-rzg3s-host.c
1172
writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
drivers/pci/controller/pcie-rzg3s-host.c
1180
writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
drivers/pci/controller/pcie-rzg3s-host.c
1251
writel_relaxed(upper_32_bits(cpu_addr),
drivers/pci/controller/pcie-rzg3s-host.c
1253
writel_relaxed(lower_32_bits(cpu_addr),
drivers/pci/controller/pcie-rzg3s-host.c
1257
writel_relaxed(upper_32_bits(size), host->axi + RZG3S_PCI_AWMASKU(id));
drivers/pci/controller/pcie-rzg3s-host.c
1258
writel_relaxed(lower_32_bits(size), host->axi + RZG3S_PCI_AWMASKL(id));
drivers/pci/controller/pcie-rzg3s-host.c
1261
writel_relaxed(upper_32_bits(pci_addr),
drivers/pci/controller/pcie-rzg3s-host.c
1263
writel_relaxed(lower_32_bits(pci_addr) | RZG3S_PCI_AWBASEL_WIN_ENA,
drivers/pci/controller/pcie-rzg3s-host.c
1363
writel_relaxed(upper_32_bits(res_start),
drivers/pci/controller/pcie-rzg3s-host.c
1365
writel_relaxed(lower_32_bits(res_start),
drivers/pci/controller/pcie-rzg3s-host.c
1369
writel_relaxed(upper_32_bits(size), host->axi + RZG3S_PCI_PWMASKU(id));
drivers/pci/controller/pcie-rzg3s-host.c
1370
writel_relaxed(lower_32_bits(size), host->axi + RZG3S_PCI_PWMASKL(id));
drivers/pci/controller/pcie-rzg3s-host.c
1373
writel_relaxed(upper_32_bits(res_start),
drivers/pci/controller/pcie-rzg3s-host.c
1375
writel_relaxed(lower_32_bits(res_start) | RZG3S_PCI_PWBASEL_ENA,
drivers/pci/controller/pcie-rzg3s-host.c
1435
writel_relaxed(RZG3S_PCI_PERM_PIPE_PHY_REG_EN,
drivers/pci/controller/pcie-rzg3s-host.c
1439
writel_relaxed(xcfgd_settings[i],
drivers/pci/controller/pcie-rzg3s-host.c
1444
writel_relaxed(xcfga_cmn_settings[i],
drivers/pci/controller/pcie-rzg3s-host.c
1449
writel_relaxed(xcfga_rx_settings[i],
drivers/pci/controller/pcie-rzg3s-host.c
1453
writel_relaxed(0x107, host->axi + RZG3S_PCI_PHY_XCFGA_TX);
drivers/pci/controller/pcie-rzg3s-host.c
1456
writel_relaxed(RZG3S_PCI_PHY_XCFG_CTRL_PHYREG_SEL,
drivers/pci/controller/pcie-rzg3s-host.c
1463
writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
drivers/pci/controller/pcie-rzg3s-host.c
271
writel_relaxed(tmp, base + offset);
drivers/pci/controller/pcie-rzg3s-host.c
303
writel_relaxed(FIELD_PREP(RZG3S_PCI_REQADR1_BUS, bus->number) |
drivers/pci/controller/pcie-rzg3s-host.c
310
writel_relaxed(RZG3S_PCI_REQBE_BYTE_EN, host->axi + RZG3S_PCI_REQBE);
drivers/pci/controller/pcie-rzg3s-host.c
323
writel_relaxed(type0 ? RZG3S_PCI_REQISS_TR_TP0_RD :
drivers/pci/controller/pcie-rzg3s-host.c
365
writel_relaxed(0, host->axi + RZG3S_PCI_REQDATA(0));
drivers/pci/controller/pcie-rzg3s-host.c
366
writel_relaxed(0, host->axi + RZG3S_PCI_REQDATA(1));
drivers/pci/controller/pcie-rzg3s-host.c
367
writel_relaxed(data, host->axi + RZG3S_PCI_REQDATA(2));
drivers/pci/controller/pcie-rzg3s-host.c
370
writel_relaxed(type0 ? RZG3S_PCI_REQISS_TR_TP0_WR :
drivers/pci/controller/pcie-rzg3s-host.c
498
writel_relaxed(BIT(reg_bit),
drivers/pci/controller/pcie-rzg3s-host.c
513
writel_relaxed(BIT(reg_bit), host->axi + RZG3S_PCI_MSIRS(reg_id));
drivers/pci/controller/pcie-rzg3s-host.c
657
writel_relaxed(FIELD_PREP(RZG3S_PCI_MSIRCVWMSKL_MASK,
drivers/pci/controller/pcie-rzg3s-host.c
662
writel_relaxed(upper_32_bits(msi->window_base),
drivers/pci/controller/pcie-rzg3s-host.c
664
writel_relaxed(lower_32_bits(msi->window_base) |
drivers/pci/controller/pcie-rzg3s-host.c
671
writel_relaxed(RZG3S_PCI_MSIRE_ENA,
drivers/pci/controller/pcie-rzg3s-host.c
676
writel_relaxed(RZG3S_PCI_MSGRCVIE_MSG_RCV,
drivers/pci/controller/pcie-rzg3s-host.c
770
writel_relaxed(0, host->axi + RZG3S_PCI_MSIRE(reg_id));
drivers/pci/controller/pcie-rzg3s-host.c
773
writel_relaxed(0, host->axi + RZG3S_PCI_MSIRCVWADRL);
drivers/pci/controller/pcie-xilinx-cpm.c
138
writel_relaxed(val, port->reg_base + reg);
drivers/pci/controller/pcie-xilinx-cpm.c
297
writel_relaxed(val, port->cpm_base +
drivers/pci/controller/pcie-xilinx-cpm.c
307
writel_relaxed(val,
drivers/pci/controller/plda/pcie-microchip-host.c
316
writel_relaxed(lower_32_bits(msi->vector_phy),
drivers/pci/controller/plda/pcie-microchip-host.c
318
writel_relaxed(upper_32_bits(msi->vector_phy),
drivers/pci/controller/plda/pcie-microchip-host.c
421
writel_relaxed(mask, addr);
drivers/pci/controller/plda/pcie-microchip-host.c
455
writel_relaxed(val, addr);
drivers/pci/controller/plda/pcie-microchip-host.c
491
writel_relaxed(val, addr);
drivers/pci/controller/plda/pcie-microchip-host.c
566
writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT,
drivers/pci/controller/plda/pcie-microchip-host.c
568
writel_relaxed(0, port->ctrl_base_addr + SEC_ERROR_EVENT_CNT);
drivers/pci/controller/plda/pcie-microchip-host.c
573
writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT,
drivers/pci/controller/plda/pcie-microchip-host.c
575
writel_relaxed(0, port->ctrl_base_addr + DED_ERROR_EVENT_CNT);
drivers/pci/controller/plda/pcie-microchip-host.c
587
writel_relaxed(val, port->ctrl_base_addr + ECC_CONTROL);
drivers/pci/controller/plda/pcie-microchip-host.c
590
writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT,
drivers/pci/controller/plda/pcie-microchip-host.c
595
writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT,
drivers/pci/controller/plda/pcie-microchip-host.c
600
writel_relaxed(0, port->bridge_base_addr + IMASK_LOCAL);
drivers/pci/controller/plda/pcie-microchip-host.c
601
writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_LOCAL);
drivers/pci/controller/plda/pcie-microchip-host.c
602
writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_MSI);
drivers/pci/controller/plda/pcie-microchip-host.c
611
writel_relaxed(val, port->ctrl_base_addr + PCIE_EVENT_INT);
drivers/pci/controller/plda/pcie-microchip-host.c
614
writel_relaxed(0, port->bridge_base_addr + IMASK_HOST);
drivers/pci/controller/plda/pcie-microchip-host.c
615
writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_HOST);
drivers/pci/controller/plda/pcie-plda-host.c
209
writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL);
drivers/pci/controller/plda/pcie-plda-host.c
223
writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
drivers/pci/controller/plda/pcie-plda-host.c
238
writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
drivers/pci/controller/plda/pcie-plda-host.c
324
writel_relaxed(plda_hwirq_to_mask(data->hwirq),
drivers/pci/controller/plda/pcie-plda-host.c
338
writel_relaxed(val, port->bridge_addr + IMASK_LOCAL);
drivers/pci/controller/plda/pcie-plda-host.c
352
writel_relaxed(val, port->bridge_addr + IMASK_LOCAL);
drivers/pci/controller/plda/pcie-plda-host.c
47
writel_relaxed(status & PM_MSI_INT_MSI_MASK,
drivers/pci/controller/plda/pcie-plda-host.c
67
writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI);
drivers/pci/controller/plda/pcie-plda.h
226
writel_relaxed(value, plda->bridge_addr + GEN_SETTINGS);
drivers/pci/controller/plda/pcie-plda.h
237
writel_relaxed(value, plda->bridge_addr + PCIE_PCI_IDS_DW1);
drivers/pci/controller/plda/pcie-plda.h
246
writel_relaxed(value, plda->bridge_addr + PCIE_WINROM);
drivers/pci/controller/plda/pcie-plda.h
255
writel_relaxed(value, plda->bridge_addr + PMSG_SUPPORT_RX);
drivers/pci/controller/plda/pcie-plda.h
264
writel_relaxed(value, plda->bridge_addr + PCI_MISC);
drivers/pci/controller/plda/pcie-plda.h
271
writel_relaxed(lower_32_bits(val), addr + PCI_BASE_ADDRESS_0);
drivers/pci/controller/plda/pcie-plda.h
272
writel_relaxed(upper_32_bits(val), addr + PCI_BASE_ADDRESS_1);
drivers/pcmcia/sa1111_generic.c
130
writel_relaxed(val, s->dev->mapbase + PCCR);
drivers/pcmcia/sa1111_generic.c
211
writel_relaxed(PCSSR_S0_SLEEP | PCSSR_S1_SLEEP, base + PCSSR);
drivers/pcmcia/sa1111_generic.c
212
writel_relaxed(PCCR_S0_FLT | PCCR_S1_FLT, base + PCCR);
drivers/perf/arm-cci.c
713
writel_relaxed(value, cci_pmu->base +
drivers/perf/arm-cmn.c
1425
writel_relaxed(0, CMN_DT_PMCR(&cmn->dtc[0]));
drivers/perf/arm-cmn.c
1433
writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN,
drivers/perf/arm-cmn.c
1481
writel_relaxed(CMN_COUNTER_INIT, pmevcnt);
drivers/perf/arm-cmn.c
1492
writel_relaxed(CMN_COUNTER_INIT, CMN_DT_PMEVCNT(&cmn->dtc[i], idx));
drivers/perf/arm-cmn.c
1546
writel_relaxed(reg >> 32, dn->pmu_base + CMN_PMU_EVENT_SEL + 4);
drivers/perf/arm-cmn.c
1562
writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL);
drivers/perf/arm-cmn.c
1577
writel_relaxed(CMN_DT_DTC_CTL_DT_EN | CMN_DT_DTC_CTL_CG_DISABLE,
drivers/perf/arm-cmn.c
1612
writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL);
drivers/perf/arm-cmn.c
1862
writel_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG);
drivers/perf/arm-cmn.c
1936
writel_relaxed(cfg, dtm->base + CMN_DTM_WPn_CONFIG(wp_idx));
drivers/perf/arm-cmn.c
2082
writel_relaxed(status, CMN_DT_PMOVSR_CLR(dtc));
drivers/perf/arm-cmn.c
2142
writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL);
drivers/perf/arm-cmn.c
2143
writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, CMN_DT_PMCR(dtc));
drivers/perf/arm-cmn.c
2145
writel_relaxed(0x1ff, CMN_DT_PMOVSR_CLR(dtc));
drivers/perf/arm-cmn.c
2644
writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL);
drivers/perf/arm-ni.c
280
writel_relaxed(NI_PMCR_ENABLE, pmu_to_cd(pmu)->pmu_base + NI_PMCR);
drivers/perf/arm-ni.c
285
writel_relaxed(0, pmu_to_cd(pmu)->pmu_base + NI_PMCR);
drivers/perf/arm-ni.c
399
writel_relaxed(1U << event->hw.idx, cd->pmu_base + NI_PMCNTENSET);
drivers/perf/arm-ni.c
406
writel_relaxed(1U << event->hw.idx, cd->pmu_base + NI_PMCNTENCLR);
drivers/perf/arm-ni.c
420
writel_relaxed(S32_MIN, (void __iomem *)hw->event_base);
drivers/perf/arm-ni.c
455
writel_relaxed(reg, cd->pmu_base + NI_PMEVTYPER(hw->idx));
drivers/perf/arm-ni.c
499
writel_relaxed(reg, cd->pmu_base + NI_PMOVSCLR);
drivers/perf/arm-ni.c
565
writel_relaxed(1, unit->pmusela);
drivers/perf/arm-ni.c
589
writel_relaxed(NI_PMCR_RESET_CCNT | NI_PMCR_RESET_EVCNT,
drivers/perf/arm-ni.c
591
writel_relaxed(U32_MAX, cd->pmu_base + NI_PMCNTENCLR);
drivers/perf/arm-ni.c
592
writel_relaxed(U32_MAX, cd->pmu_base + NI_PMOVSCLR);
drivers/perf/arm-ni.c
626
writel_relaxed(0, cd->pmu_base + NI_PMCR);
drivers/perf/arm-ni.c
627
writel_relaxed(U32_MAX, cd->pmu_base + NI_PMINTENCLR);
drivers/perf/arm-ni.c
662
writel_relaxed(U32_MAX, cd->pmu_base + NI_PMINTENSET);
drivers/perf/arm_smmuv3_pmu.c
735
writel_relaxed(msg->data, pmu->reg_base + SMMU_PMCG_IRQ_CFG1);
drivers/perf/arm_smmuv3_pmu.c
736
writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE,
drivers/perf/fsl_imx9_ddr_perf.c
484
writel_relaxed(pmcfg1, pmu->base + PMCFG1);
drivers/perf/fsl_imx9_ddr_perf.c
489
writel_relaxed(pmcfg2, pmu->base + PMCFG2);
drivers/perf/fsl_imx9_ddr_perf.c
531
writel_relaxed(pmcfg1, pmu->base + PMCFG1);
drivers/perf/fsl_imx9_ddr_perf.c
539
writel_relaxed(pmcfg, pmu->base + offset);
drivers/perf/hisilicon/hisi_pcie_pmu.c
207
writel_relaxed(val, pcie_pmu->base + offset);
drivers/perf/qcom_l3_pmu.c
203
writel_relaxed(gang, l3pmu->regs + L3_M_BC_GANG);
drivers/perf/qcom_l3_pmu.c
207
writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx + 1));
drivers/perf/qcom_l3_pmu.c
208
writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx));
drivers/perf/qcom_l3_pmu.c
214
writel_relaxed(EVSEL(0), l3pmu->regs + L3_HML3_PM_EVTYPE(idx + 1));
drivers/perf/qcom_l3_pmu.c
215
writel_relaxed(EVSEL(evsel), l3pmu->regs + L3_HML3_PM_EVTYPE(idx));
drivers/perf/qcom_l3_pmu.c
218
writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx + 1));
drivers/perf/qcom_l3_pmu.c
219
writel_relaxed(PMCNTENSET(idx + 1), l3pmu->regs + L3_M_BC_CNTENSET);
drivers/perf/qcom_l3_pmu.c
220
writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx));
drivers/perf/qcom_l3_pmu.c
221
writel_relaxed(PMCNTENSET(idx), l3pmu->regs + L3_M_BC_CNTENSET);
drivers/perf/qcom_l3_pmu.c
232
writel_relaxed(PMCNTENCLR(idx), l3pmu->regs + L3_M_BC_CNTENCLR);
drivers/perf/qcom_l3_pmu.c
233
writel_relaxed(PMCNTENCLR(idx + 1), l3pmu->regs + L3_M_BC_CNTENCLR);
drivers/perf/qcom_l3_pmu.c
236
writel_relaxed(gang & ~GANG_EN(idx + 1), l3pmu->regs + L3_M_BC_GANG);
drivers/perf/qcom_l3_pmu.c
282
writel_relaxed(irqctl | PMIRQONMSBEN(idx), l3pmu->regs + L3_M_BC_IRQCTL);
drivers/perf/qcom_l3_pmu.c
286
writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx));
drivers/perf/qcom_l3_pmu.c
289
writel_relaxed(EVSEL(evsel), l3pmu->regs + L3_HML3_PM_EVTYPE(idx));
drivers/perf/qcom_l3_pmu.c
292
writel_relaxed(PMINTENSET(idx), l3pmu->regs + L3_M_BC_INTENSET);
drivers/perf/qcom_l3_pmu.c
295
writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx));
drivers/perf/qcom_l3_pmu.c
296
writel_relaxed(PMCNTENSET(idx), l3pmu->regs + L3_M_BC_CNTENSET);
drivers/perf/qcom_l3_pmu.c
307
writel_relaxed(PMCNTENCLR(idx), l3pmu->regs + L3_M_BC_CNTENCLR);
drivers/perf/qcom_l3_pmu.c
310
writel_relaxed(PMINTENCLR(idx), l3pmu->regs + L3_M_BC_INTENCLR);
drivers/perf/qcom_l3_pmu.c
313
writel_relaxed(irqctl & ~PMIRQONMSBEN(idx), l3pmu->regs + L3_M_BC_IRQCTL);
drivers/perf/qcom_l3_pmu.c
354
writel_relaxed(BC_RESET, l3pmu->regs + L3_M_BC_CR);
drivers/perf/qcom_l3_pmu.c
362
writel_relaxed(BC_CNTENCLR_RESET, l3pmu->regs + L3_M_BC_CNTENCLR);
drivers/perf/qcom_l3_pmu.c
363
writel_relaxed(BC_INTENCLR_RESET, l3pmu->regs + L3_M_BC_INTENCLR);
drivers/perf/qcom_l3_pmu.c
364
writel_relaxed(PMOVSRCLR_RESET, l3pmu->regs + L3_M_BC_OVSR);
drivers/perf/qcom_l3_pmu.c
365
writel_relaxed(BC_GANG_RESET, l3pmu->regs + L3_M_BC_GANG);
drivers/perf/qcom_l3_pmu.c
366
writel_relaxed(BC_IRQCTL_RESET, l3pmu->regs + L3_M_BC_IRQCTL);
drivers/perf/qcom_l3_pmu.c
367
writel_relaxed(PM_CR_RESET, l3pmu->regs + L3_HML3_PM_CR);
drivers/perf/qcom_l3_pmu.c
370
writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(i));
drivers/perf/qcom_l3_pmu.c
371
writel_relaxed(EVSEL(0), l3pmu->regs + L3_HML3_PM_EVTYPE(i));
drivers/perf/qcom_l3_pmu.c
374
writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRA);
drivers/perf/qcom_l3_pmu.c
375
writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRAM);
drivers/perf/qcom_l3_pmu.c
376
writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRB);
drivers/perf/qcom_l3_pmu.c
377
writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRBM);
drivers/perf/qcom_l3_pmu.c
378
writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRC);
drivers/perf/qcom_l3_pmu.c
379
writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRCM);
drivers/perf/qcom_l3_pmu.c
399
writel_relaxed(status, l3pmu->regs + L3_M_BC_OVSR);
drivers/perf/qcom_l3_pmu.c
434
writel_relaxed(BC_ENABLE, l3pmu->regs + L3_M_BC_CR);
drivers/perf/qcom_l3_pmu.c
441
writel_relaxed(0, l3pmu->regs + L3_M_BC_CR);
drivers/phy/broadcom/phy-brcm-usb-init.h
103
writel_relaxed(val, addr);
drivers/phy/hisilicon/phy-hix5hd2-sata.c
103
writel_relaxed(val, priv->base + SATA_PORT_PHYCTL2);
drivers/phy/hisilicon/phy-hix5hd2-sata.c
111
writel_relaxed(val, priv->base + SATA_PORT_PHYCTL);
drivers/phy/hisilicon/phy-hix5hd2-sata.c
118
writel_relaxed(val, priv->base + SATA_PORT_PHYCTL);
drivers/phy/hisilicon/phy-hix5hd2-sata.c
124
writel_relaxed(val, priv->base + SATA_PORT_PHYCTL);
drivers/phy/hisilicon/phy-hix5hd2-sata.c
86
writel_relaxed(val, priv->base + SATA_PHY0_CTLL);
drivers/phy/hisilicon/phy-hix5hd2-sata.c
89
writel_relaxed(val, priv->base + SATA_PHY0_CTLL);
drivers/phy/hisilicon/phy-hix5hd2-sata.c
96
writel_relaxed(val, priv->base + SATA_PORT_PHYCTL1);
drivers/phy/marvell/phy-mmp3-hsic.c
25
writel_relaxed(hsic_ctrl, base + HSIC_CTRL);
drivers/phy/marvell/phy-mmp3-usb.c
126
writel_relaxed(reg, base + offset);
drivers/phy/marvell/phy-mmp3-usb.c
137
writel_relaxed(reg, base + offset);
drivers/phy/marvell/phy-pxa-usb.c
137
writel_relaxed(reg, base + offset);
drivers/phy/marvell/phy-pxa-usb.c
148
writel_relaxed(reg, base + offset);
drivers/phy/marvell/phy-pxa-usb.c
155
writel_relaxed(value, base + offset);
drivers/phy/phy-snps-eusb2.c
197
writel_relaxed(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
100
writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
101
writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
104
writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
105
writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
107
writel_relaxed(0x0A, base + UNIPHY_PLL_CAL_CFG0);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
108
writel_relaxed(0xF3, base + UNIPHY_PLL_CAL_CFG8);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
109
writel_relaxed(0x01, base + UNIPHY_PLL_CAL_CFG9);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
110
writel_relaxed(0xED, base + UNIPHY_PLL_CAL_CFG10);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
111
writel_relaxed(0x02, base + UNIPHY_PLL_CAL_CFG11);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
113
writel_relaxed(0x36, base + UNIPHY_PLL_SDM_CFG0);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
114
writel_relaxed(0x0D, base + UNIPHY_PLL_SDM_CFG1);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
115
writel_relaxed(0xA3, base + UNIPHY_PLL_SDM_CFG2);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
116
writel_relaxed(0xF0, base + UNIPHY_PLL_SDM_CFG3);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
117
writel_relaxed(0x00, base + UNIPHY_PLL_SDM_CFG4);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
119
writel_relaxed(0x19, base + UNIPHY_PLL_SSC_CFG0);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
120
writel_relaxed(0xE1, base + UNIPHY_PLL_SSC_CFG1);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
121
writel_relaxed(0x00, base + UNIPHY_PLL_SSC_CFG2);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
122
writel_relaxed(0x11, base + UNIPHY_PLL_SSC_CFG3);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
124
writel_relaxed(0x04, base + UNIPHY_PLL_LKDET_CFG0);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
125
writel_relaxed(0xFF, base + UNIPHY_PLL_LKDET_CFG1);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
127
writel_relaxed(0x02, base + UNIPHY_PLL_GLB_CFG);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
131
writel_relaxed(0x03, base + UNIPHY_PLL_GLB_CFG);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
132
writel_relaxed(0x05, base + UNIPHY_PLL_LKDET_CFG2);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
156
writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
157
writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
158
writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
160
writel_relaxed(0x00, base + SATA_PHY_POW_DWN_CTRL1);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
161
writel_relaxed(0x59, base + SATA_PHY_CDR_CTRL0);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
162
writel_relaxed(0x04, base + SATA_PHY_CDR_CTRL1);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
163
writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL2);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
164
writel_relaxed(0x00, base + SATA_PHY_PI_CTRL0);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
165
writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL3);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
166
writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
168
writel_relaxed(0x11, base + SATA_PHY_TX_DATA_CTRL);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
169
writel_relaxed(0x43, base + SATA_PHY_ALIGNP);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
170
writel_relaxed(0x04, base + SATA_PHY_OOB_TERM);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
172
writel_relaxed(0x01, base + SATA_PHY_EQUAL);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
173
writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL0);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
174
writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL1);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
185
writel_relaxed(0xF8, base + SATA_PHY_POW_DWN_CTRL0);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
186
writel_relaxed(0xFE, base + SATA_PHY_POW_DWN_CTRL1);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
189
writel_relaxed(0x00, base + UNIPHY_PLL_GLB_CFG);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
91
writel_relaxed(0x01, base + SATA_PHY_SER_CTRL);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
92
writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
97
writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
98
writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
99
writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c
103
writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c
116
writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c
61
writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3);
drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c
68
writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0);
drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c
77
writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1);
drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c
82
writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2);
drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c
87
writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c
92
writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
drivers/phy/qualcomm/phy-qcom-m31.c
257
writel_relaxed(POWER_DOWN, qphy->base + USB2PHY_PORT_POWERDOWN);
drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
177
writel_relaxed(reg, base + offset);
drivers/phy/st/phy-stm32-combophy.c
310
writel_relaxed(val, combophy->base + COMBOPHY_SUP_ANA_MPLL_LOOP_CTL);
drivers/phy/st/phy-stm32-usbphyc.c
161
writel_relaxed(readl_relaxed(reg) | bits, reg);
drivers/phy/st/phy-stm32-usbphyc.c
166
writel_relaxed(readl_relaxed(reg) & ~bits, reg);
drivers/phy/st/phy-stm32-usbphyc.c
254
writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
drivers/phy/st/phy-stm32-usbphyc.c
350
writel_relaxed(monsel, usbphyc->base + reg_mon);
drivers/phy/st/phy-stm32-usbphyc.c
561
writel_relaxed(usbphyc_phy->tune, usbphyc->base + reg);
drivers/phy/st/phy-stm32-usbphyc.c
799
writel_relaxed(usbphyc_phy->tune, usbphyc->base + STM32_USBPHYC_TUNE(port));
drivers/phy/tegra/phy-tegra194-p2u.c
47
writel_relaxed(value, phy->base + reg);
drivers/pinctrl/actions/pinctrl-owl.c
531
writel_relaxed(val, base);
drivers/pinctrl/actions/pinctrl-owl.c
66
writel_relaxed(reg_val, base);
drivers/pinctrl/actions/pinctrl-owl.c
718
writel_relaxed(value, gpio_base + port->intc_type + offset);
drivers/pinctrl/actions/pinctrl-owl.c
779
writel_relaxed(value, gpio_base + port->intc_ctl);
drivers/pinctrl/mediatek/mtk-eint.c
258
writel_relaxed(~buf[inst][port], reg + eint->regs->mask_set);
drivers/pinctrl/mediatek/mtk-eint.c
259
writel_relaxed(buf[inst][port], reg + eint->regs->mask_clr);
drivers/pinctrl/mediatek/mtk-eint.c
384
writel_relaxed(mask, reg);
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
50
writel_relaxed(val, pctl->base[i] + reg);
drivers/pinctrl/nomadik/pinctrl-nomadik.c
268
writel_relaxed(nmk_chip->lowemi,
drivers/pinctrl/nomadik/pinctrl-nomadik.c
322
writel_relaxed(nmk_chip->rimsc,
drivers/pinctrl/nomadik/pinctrl-nomadik.c
328
writel_relaxed(nmk_chip->fimsc,
drivers/pinctrl/pinctrl-artpec6.c
720
writel_relaxed(val, pmx->base + reg);
drivers/pinctrl/pinctrl-artpec6.c
932
writel_relaxed(val, base + artpec6_pmx_reg_offset(i));
drivers/pinctrl/pinctrl-at91-pio4.c
172
writel_relaxed(val, atmel_pioctrl->reg_base
drivers/pinctrl/pinctrl-at91-pio4.c
461
writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
drivers/pinctrl/pinctrl-at91-pio4.c
477
writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
drivers/pinctrl/pinctrl-at91-pio4.c
480
writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
drivers/pinctrl/pinctrl-at91-pio4.c
872
writel_relaxed(mask, atmel_pioctrl->reg_base +
drivers/pinctrl/pinctrl-at91-pio4.c
876
writel_relaxed(mask, atmel_pioctrl->reg_base +
drivers/pinctrl/pinctrl-at91.c
1437
writel_relaxed(mask, pio + PIO_ODR);
drivers/pinctrl/pinctrl-at91.c
1458
writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
drivers/pinctrl/pinctrl-at91.c
1474
writel_relaxed(set_mask, pio + PIO_SODR);
drivers/pinctrl/pinctrl-at91.c
1475
writel_relaxed(clear_mask, pio + PIO_CODR);
drivers/pinctrl/pinctrl-at91.c
1487
writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
drivers/pinctrl/pinctrl-at91.c
1488
writel_relaxed(mask, pio + PIO_OER);
drivers/pinctrl/pinctrl-at91.c
1564
writel_relaxed(mask, pio + PIO_IDR);
drivers/pinctrl/pinctrl-at91.c
1577
writel_relaxed(mask, pio + PIO_IER);
drivers/pinctrl/pinctrl-at91.c
1601
writel_relaxed(mask, pio + PIO_ESR);
drivers/pinctrl/pinctrl-at91.c
1602
writel_relaxed(mask, pio + PIO_REHLSR);
drivers/pinctrl/pinctrl-at91.c
1606
writel_relaxed(mask, pio + PIO_ESR);
drivers/pinctrl/pinctrl-at91.c
1607
writel_relaxed(mask, pio + PIO_FELLSR);
drivers/pinctrl/pinctrl-at91.c
1611
writel_relaxed(mask, pio + PIO_LSR);
drivers/pinctrl/pinctrl-at91.c
1612
writel_relaxed(mask, pio + PIO_FELLSR);
drivers/pinctrl/pinctrl-at91.c
1616
writel_relaxed(mask, pio + PIO_LSR);
drivers/pinctrl/pinctrl-at91.c
1617
writel_relaxed(mask, pio + PIO_REHLSR);
drivers/pinctrl/pinctrl-at91.c
1625
writel_relaxed(mask, pio + PIO_AIMDR);
drivers/pinctrl/pinctrl-at91.c
1634
writel_relaxed(mask, pio + PIO_AIMER);
drivers/pinctrl/pinctrl-at91.c
1665
writel_relaxed(at91_chip->backups, pio + PIO_IDR);
drivers/pinctrl/pinctrl-at91.c
1666
writel_relaxed(at91_chip->wakeups, pio + PIO_IER);
drivers/pinctrl/pinctrl-at91.c
1685
writel_relaxed(at91_chip->wakeups, pio + PIO_IDR);
drivers/pinctrl/pinctrl-at91.c
1686
writel_relaxed(at91_chip->backups, pio + PIO_IER);
drivers/pinctrl/pinctrl-at91.c
1752
writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
drivers/pinctrl/pinctrl-at91.c
405
writel_relaxed(mask, pio + PIO_IDR);
drivers/pinctrl/pinctrl-at91.c
416
writel_relaxed(mask, pio + PIO_PPDDR);
drivers/pinctrl/pinctrl-at91.c
418
writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
drivers/pinctrl/pinctrl-at91.c
430
writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
drivers/pinctrl/pinctrl-at91.c
431
writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
drivers/pinctrl/pinctrl-at91.c
441
writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
drivers/pinctrl/pinctrl-at91.c
446
writel_relaxed(mask, pio + PIO_ASR);
drivers/pinctrl/pinctrl-at91.c
451
writel_relaxed(mask, pio + PIO_BSR);
drivers/pinctrl/pinctrl-at91.c
457
writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
drivers/pinctrl/pinctrl-at91.c
459
writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
drivers/pinctrl/pinctrl-at91.c
465
writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
drivers/pinctrl/pinctrl-at91.c
467
writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
drivers/pinctrl/pinctrl-at91.c
473
writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
drivers/pinctrl/pinctrl-at91.c
474
writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
drivers/pinctrl/pinctrl-at91.c
479
writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
drivers/pinctrl/pinctrl-at91.c
480
writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
drivers/pinctrl/pinctrl-at91.c
515
writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
drivers/pinctrl/pinctrl-at91.c
529
writel_relaxed(mask, pio + PIO_IFSCDR);
drivers/pinctrl/pinctrl-at91.c
545
writel_relaxed(mask, pio + PIO_IFSCER);
drivers/pinctrl/pinctrl-at91.c
546
writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
drivers/pinctrl/pinctrl-at91.c
547
writel_relaxed(mask, pio + PIO_IFER);
drivers/pinctrl/pinctrl-at91.c
549
writel_relaxed(mask, pio + PIO_IFSCDR);
drivers/pinctrl/pinctrl-at91.c
560
writel_relaxed(mask, pio + PIO_PUDR);
drivers/pinctrl/pinctrl-at91.c
562
writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
drivers/pinctrl/pinctrl-at91.c
567
writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
drivers/pinctrl/pinctrl-at91.c
640
writel_relaxed(tmp, reg);
drivers/pinctrl/pinctrl-at91.c
687
writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
drivers/pinctrl/pinctrl-at91.c
705
writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR);
drivers/pinctrl/pinctrl-at91.c
833
writel_relaxed(mask, pio + PIO_PDR);
drivers/pinctrl/pinctrl-at91.c
838
writel_relaxed(mask, pio + PIO_PER);
drivers/pinctrl/pinctrl-at91.c
839
writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
drivers/pinctrl/pinctrl-at91.c
957
writel_relaxed(mask, at91_chip->regbase + PIO_PER);
drivers/pinctrl/pinctrl-bm1880.c
1002
writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset);
drivers/pinctrl/pinctrl-bm1880.c
1262
writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset);
drivers/pinctrl/pinctrl-eic7700.c
431
writel_relaxed(value, pc->base + EIC7700_PIN_REG(pin));
drivers/pinctrl/pinctrl-eic7700.c
508
writel_relaxed(value, pc->base + EIC7700_PIN_REG(group_selector));
drivers/pinctrl/pinctrl-eic7700.c
537
writel_relaxed(value, pc->base + EIC7700_PIN_REG(offset));
drivers/pinctrl/pinctrl-eic7700.c
663
writel_relaxed(rgmii0_mode, pc->base + EIC7700_RGMII0_SEL_MODE);
drivers/pinctrl/pinctrl-eic7700.c
664
writel_relaxed(rgmii1_mode, pc->base + EIC7700_RGMII1_SEL_MODE);
drivers/pinctrl/pinctrl-th1520.c
588
writel_relaxed(tmp, padcfg);
drivers/pinctrl/pinctrl-th1520.c
796
writel_relaxed(tmp, muxcfg);
drivers/pinctrl/pxa/pinctrl-pxa2xx.c
101
writel_relaxed(val, gpdr);
drivers/pinctrl/pxa/pinctrl-pxa2xx.c
164
writel_relaxed(val, gafr);
drivers/pinctrl/pxa/pinctrl-pxa2xx.c
168
writel_relaxed(val, gpdr);
drivers/pinctrl/pxa/pinctrl-pxa2xx.c
232
writel_relaxed(val, pgsr);
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
220
writel_relaxed(mux, reg_mux);
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
222
writel_relaxed(mux2, reg_mux2);
drivers/pinctrl/spacemit/pinctrl-k1.c
477
writel_relaxed(val, pctrl->regs + IO_PWR_DOMAIN_OFFSET + offset);
drivers/pinctrl/spacemit/pinctrl-k1.c
627
writel_relaxed(mux | value, reg);
drivers/pinctrl/spacemit/pinctrl-k1.c
643
writel_relaxed(spin->gpiofunc, reg);
drivers/pinctrl/spacemit/pinctrl-k1.c
805
writel_relaxed(mux | value, reg);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
1054
writel_relaxed(mask, ic);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
1069
writel_relaxed(value, ie);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
1087
writel_relaxed(value, ie);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
1088
writel_relaxed(mask, ic);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
1105
writel_relaxed(value, ie);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
1155
writel_relaxed(irq_type, base + GPIOIS);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
1157
writel_relaxed(edge_both, base + GPIOIBE);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
1159
writel_relaxed(polarity, base + GPIOIEV);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
674
writel_relaxed(dout, reg_dout);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
675
writel_relaxed(doen, reg_doen);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
677
writel_relaxed(gpio + 2, reg_din);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
715
writel_relaxed(value, reg);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
938
writel_relaxed(GPO_DISABLE, doen);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
952
writel_relaxed(value, dout);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
953
writel_relaxed(GPO_ENABLE, doen);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
980
writel_relaxed(value, dout);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c
117
writel_relaxed(0, sfp->base + JH7110_AON_GPIOIE);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c
119
writel_relaxed(0, sfp->base + JH7110_AON_GPIOIC);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c
120
writel_relaxed(0x0f, sfp->base + JH7110_AON_GPIOIC);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c
122
writel_relaxed(1, sfp->base + JH7110_AON_GPIOEN);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c
306
writel_relaxed(func, reg);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c
328
writel_relaxed(grp, reg);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
283
writel_relaxed(dout, reg_dout);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
285
writel_relaxed(doen, reg_doen);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
288
writel_relaxed(ival, reg_din);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
369
writel_relaxed(value, reg);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
625
writel_relaxed(dout, reg_dout);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
702
writel_relaxed(value, ic);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
703
writel_relaxed(value | mask, ic);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
720
writel_relaxed(value, ie);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
741
writel_relaxed(value, ie);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
744
writel_relaxed(value, ic);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
745
writel_relaxed(value | mask, ic);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
764
writel_relaxed(value, ie);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
815
writel_relaxed(irq_type, base + irq_reg->is_reg_base);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
818
writel_relaxed(edge_both, base + irq_reg->ibe_reg_base);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
821
writel_relaxed(polarity, base + irq_reg->iev_reg_base);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
994
writel_relaxed(sfp->saved_regs[i], sfp->base + 4 * i);
drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
565
writel_relaxed(mux, hdp->base + HDP_MUX);
drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
662
writel_relaxed(HDP_CTRL_ENABLE, hdp->base + HDP_CTRL);
drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
674
writel_relaxed(HDP_CTRL_DISABLE, hdp->base + HDP_CTRL);
drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
701
writel_relaxed(HDP_CTRL_ENABLE, hdp->base + HDP_CTRL);
drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
702
writel_relaxed(hdp->gposet_conf, hdp->base + HDP_GPOSET);
drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
703
writel_relaxed(hdp->mux_conf, hdp->base + HDP_MUX);
drivers/pinctrl/stm32/pinctrl-stm32.c
1102
writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
drivers/pinctrl/stm32/pinctrl-stm32.c
1148
writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
drivers/pinctrl/stm32/pinctrl-stm32.c
1194
writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
drivers/pinctrl/stm32/pinctrl-stm32.c
1228
writel_relaxed(val, bank->base + advcfgr_offset);
drivers/pinctrl/stm32/pinctrl-stm32.c
1333
writel_relaxed(val, bank->base + delay_offset);
drivers/pinctrl/stm32/pinctrl-stm32.c
316
writel_relaxed(STM32_GPIO_SEMCR_SEM_MUTEX, bank->base + STM32_GPIO_SEMCR(gpio_nr));
drivers/pinctrl/stm32/pinctrl-stm32.c
336
writel_relaxed(0, bank->base + STM32_GPIO_SEMCR(gpio_nr));
drivers/pinctrl/stm32/pinctrl-stm32.c
349
writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
drivers/pinctrl/stm32/pinctrl-stm32.c
959
writel_relaxed(val, bank->base + alt_offset);
drivers/pinctrl/stm32/pinctrl-stm32.c
964
writel_relaxed(val, bank->base + STM32_GPIO_MODER);
drivers/pinctrl/tegra/pinctrl-tegra.c
37
writel_relaxed(val, pmx->regs[bank] + reg);
drivers/pinctrl/tegra/pinctrl-tegra.c
797
writel_relaxed(*backup_regs++, regs++);
drivers/pinctrl/vt8500/pinctrl-wmt.c
33
writel_relaxed(val, data->base + reg);
drivers/pinctrl/vt8500/pinctrl-wmt.c
43
writel_relaxed(val, data->base + reg);
drivers/pmdomain/qcom/cpr.c
259
writel_relaxed(value, drv->base + offset);
drivers/pmdomain/qcom/cpr.c
275
writel_relaxed(val, drv->base + offset);
drivers/pmdomain/samsung/exynos-pm-domains.c
47
writel_relaxed(pwr, base);
drivers/pmdomain/ti/omap_prm.c
544
writel_relaxed((v & ~PRM_POWERSTATE_MASK) | mode,
drivers/pmdomain/ti/omap_prm.c
591
writel_relaxed(v, prmd->prm->base + prmd->pwrstctrl);
drivers/pmdomain/ti/omap_prm.c
791
writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl);
drivers/pmdomain/ti/omap_prm.c
820
writel_relaxed(v, reset->prm->base + reset->prm->data->rstst);
drivers/pmdomain/ti/omap_prm.c
830
writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl);
drivers/pmdomain/ti/omap_prm.c
936
writel_relaxed(reset->mask, reset->prm->base +
drivers/power/reset/at91-reset.c
269
writel_relaxed(val, reset->dev_base);
drivers/power/reset/hisi-reboot.c
27
writel_relaxed(0xdeadbeef, base + reboot_offset);
drivers/pwm/pwm-atmel.c
110
writel_relaxed(val, chip->base + offset);
drivers/pwm/pwm-berlin.c
72
writel_relaxed(value, bpc->base + channel * 0x10 + offset);
drivers/pwm/pwm-brcmstb.c
74
writel_relaxed(value, p->base + offset);
drivers/pwm/pwm-imx27.c
325
writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);
drivers/pwm/pwm-imx27.c
326
writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);
drivers/pwm/pwm-imx27.c
335
writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);
drivers/pwm/pwm-imx27.c
338
writel_relaxed(duty_cycles, imx->mmio_base + MX3_PWMSAR);
drivers/pwm/pwm-microchip-core.c
178
writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
drivers/pwm/pwm-microchip-core.c
179
writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
drivers/pwm/pwm-microchip-core.c
346
writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
drivers/pwm/pwm-microchip-core.c
347
writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
drivers/pwm/pwm-microchip-core.c
469
writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD);
drivers/pwm/pwm-microchip-core.c
86
writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset);
drivers/pwm/pwm-rockchip.c
138
writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
drivers/pwm/pwm-rockchip.c
185
writel_relaxed(val, pc->base + pc->data->regs.ctrl);
drivers/pwm/pwm-spear.c
228
writel_relaxed(val, pc->mmio_base + PWMMCR);
drivers/pwm/pwm-spear.c
72
writel_relaxed(val, chip->mmio_base + (num << 4) + offset);
drivers/pwm/pwm-sprd.c
68
writel_relaxed(val, spc->base + offset);
drivers/regulator/stm32-pwr.c
73
writel_relaxed(val, priv->base + REG_PWR_CR3);
drivers/regulator/stm32-pwr.c
92
writel_relaxed(val, priv->base + REG_PWR_CR3);
drivers/regulator/stm32-vrefbuf.c
123
writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
drivers/regulator/stm32-vrefbuf.c
53
writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
drivers/regulator/stm32-vrefbuf.c
67
writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
drivers/regulator/stm32-vrefbuf.c
87
writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
drivers/remoteproc/mtk_scp_ipi.c
106
writel_relaxed(val, dst + len - remain);
drivers/remoteproc/mtk_scp_ipi.c
97
writel_relaxed(val, ptr);
drivers/remoteproc/pru_rproc.c
143
writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg);
drivers/resctrl/mpam_devices.c
178
writel_relaxed(val, msc->mapped_hwpage + reg);
drivers/reset/reset-brcmstb.c
46
writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_SET);
drivers/reset/reset-brcmstb.c
57
writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_CLEAR);
drivers/reset/reset-ma35d1.c
134
writel_relaxed(BIT(ma35d1_reset_map[id].bit),
drivers/reset/reset-ma35d1.c
154
writel_relaxed(reg, data->base + ma35d1_reset_map[id].reg_ofs);
drivers/rtc/rtc-at91rm9200.c
89
writel_relaxed((val), at91_rtc_regs + field)
drivers/rtc/rtc-brcmstb-waketimer.c
117
writel_relaxed(WKTMR_ALARM_EVENT,
drivers/rtc/rtc-brcmstb-waketimer.c
122
writel_relaxed(WKTMR_ALARM_EVENT,
drivers/rtc/rtc-brcmstb-waketimer.c
207
writel_relaxed(sec, timer->base + BRCMSTB_WKTMR_COUNTER);
drivers/rtc/rtc-brcmstb-waketimer.c
64
writel_relaxed(reg - 1, timer->base + BRCMSTB_WKTMR_ALARM);
drivers/rtc/rtc-brcmstb-waketimer.c
65
writel_relaxed(WKTMR_ALARM_EVENT, timer->base + BRCMSTB_WKTMR_EVENT);
drivers/rtc/rtc-brcmstb-waketimer.c
82
writel_relaxed(timer->rate, timer->base + BRCMSTB_WKTMR_PRESCALER);
drivers/rtc/rtc-brcmstb-waketimer.c
84
writel_relaxed(secs, timer->base + BRCMSTB_WKTMR_ALARM);
drivers/rtc/rtc-brcmstb-waketimer.c
90
writel_relaxed(secs, timer->base + BRCMSTB_WKTMR_ALARM);
drivers/rtc/rtc-digicolor.c
142
writel_relaxed(alarm_time - reference, rtc->regs + DC_RTC_ALARM);
drivers/rtc/rtc-digicolor.c
87
writel_relaxed(val, rtc->regs + DC_RTC_REFERENCE);
drivers/rtc/rtc-meson-vrtc.c
34
writel_relaxed(time, vrtc->io_alarm);
drivers/rtc/rtc-mt7622.c
110
writel_relaxed(val, rtc->base + reg);
drivers/rtc/rtc-rtd119x.c
145
writel_relaxed((tm->tm_sec << 1) & RTD_RTCSEC_RTCSEC_MASK, data->base + RTD_RTCSEC);
drivers/rtc/rtc-rtd119x.c
146
writel_relaxed(tm->tm_min & RTD_RTCMIN_RTCMIN_MASK, data->base + RTD_RTCMIN);
drivers/rtc/rtc-rtd119x.c
147
writel_relaxed(tm->tm_hour & RTD_RTCHR_RTCHR_MASK, data->base + RTD_RTCHR);
drivers/rtc/rtc-rtd119x.c
148
writel_relaxed(day & RTD_RTCDATE1_RTCDATE1_MASK, data->base + RTD_RTCDATE1);
drivers/rtc/rtc-rtd119x.c
149
writel_relaxed((day >> 8) & RTD_RTCDATE2_RTCDATE2_MASK, data->base + RTD_RTCDATE2);
drivers/rtc/rtc-rtd119x.c
195
writel_relaxed(RTD_RTCACR_RTCPWR, data->base + RTD_RTCACR);
drivers/rtc/rtc-rtd119x.c
199
writel_relaxed(0, data->base + RTD_RTCMIN);
drivers/rtc/rtc-rtd119x.c
200
writel_relaxed(0, data->base + RTD_RTCHR);
drivers/rtc/rtc-rtd119x.c
201
writel_relaxed(0, data->base + RTD_RTCDATE1);
drivers/rtc/rtc-rtd119x.c
202
writel_relaxed(0, data->base + RTD_RTCDATE2);
drivers/rtc/rtc-rtd119x.c
61
writel_relaxed(val, data->base + RTD_RTCCR);
drivers/rtc/rtc-rtd119x.c
76
writel_relaxed(0x5a, data->base + RTD_RTCEN);
drivers/rtc/rtc-rtd119x.c
78
writel_relaxed(0, data->base + RTD_RTCEN);
drivers/rtc/rtc-sa1100.c
103
writel_relaxed(rtsr, info->rtsr);
drivers/rtc/rtc-sa1100.c
120
writel_relaxed(rtc_tm_to_time64(tm), info->rcnr);
drivers/rtc/rtc-sa1100.c
141
writel_relaxed(readl_relaxed(info->rtsr) &
drivers/rtc/rtc-sa1100.c
143
writel_relaxed(rtc_tm_to_time64(&alrm->time), info->rtar);
drivers/rtc/rtc-sa1100.c
145
writel_relaxed(readl_relaxed(info->rtsr) | RTSR_ALE, info->rtsr);
drivers/rtc/rtc-sa1100.c
147
writel_relaxed(readl_relaxed(info->rtsr) & ~RTSR_ALE, info->rtsr);
drivers/rtc/rtc-sa1100.c
195
writel_relaxed(RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16), info->rttr);
drivers/rtc/rtc-sa1100.c
199
writel_relaxed(0, info->rcnr);
drivers/rtc/rtc-sa1100.c
233
writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr);
drivers/rtc/rtc-sa1100.c
303
writel_relaxed(0, info->rtsr);
drivers/rtc/rtc-sa1100.c
55
writel_relaxed(0, info->rtsr);
drivers/rtc/rtc-sa1100.c
62
writel_relaxed((RTSR_AL | RTSR_HZ) & (rtsr >> 2), info->rtsr);
drivers/rtc/rtc-sa1100.c
71
writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr);
drivers/rtc/rtc-sa1100.c
77
writel_relaxed(rtsr & (RTSR_ALE | RTSR_HZE), info->rtsr);
drivers/rtc/rtc-st-lpc.c
114
writel_relaxed(lpt >> 32, rtc->ioaddr + LPC_LPT_MSB_OFF);
drivers/rtc/rtc-st-lpc.c
115
writel_relaxed(lpt, rtc->ioaddr + LPC_LPT_LSB_OFF);
drivers/rtc/rtc-st-lpc.c
116
writel_relaxed(1, rtc->ioaddr + LPC_LPT_START_OFF);
drivers/rtc/rtc-st-lpc.c
264
writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF);
drivers/rtc/rtc-st-lpc.c
265
writel_relaxed(0, rtc->ioaddr + LPC_LPA_START_OFF);
drivers/rtc/rtc-st-lpc.c
266
writel_relaxed(0, rtc->ioaddr + LPC_WDT_OFF);
drivers/rtc/rtc-st-lpc.c
283
writel_relaxed(0, rtc->ioaddr + LPC_LPA_MSB_OFF);
drivers/rtc/rtc-st-lpc.c
284
writel_relaxed(0, rtc->ioaddr + LPC_LPA_LSB_OFF);
drivers/rtc/rtc-st-lpc.c
285
writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF);
drivers/rtc/rtc-st-lpc.c
286
writel_relaxed(1, rtc->ioaddr + LPC_LPA_START_OFF);
drivers/rtc/rtc-st-lpc.c
287
writel_relaxed(0, rtc->ioaddr + LPC_WDT_OFF);
drivers/rtc/rtc-st-lpc.c
59
writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF);
drivers/rtc/rtc-st-lpc.c
61
writel_relaxed(msb, rtc->ioaddr + LPC_LPA_MSB_OFF);
drivers/rtc/rtc-st-lpc.c
62
writel_relaxed(lsb, rtc->ioaddr + LPC_LPA_LSB_OFF);
drivers/rtc/rtc-st-lpc.c
63
writel_relaxed(1, rtc->ioaddr + LPC_LPA_START_OFF);
drivers/rtc/rtc-st-lpc.c
65
writel_relaxed(0, rtc->ioaddr + LPC_WDT_OFF);
drivers/rtc/rtc-stm32.c
1041
writel_relaxed(pred_s, rtc->base + regs->prer);
drivers/rtc/rtc-stm32.c
1042
writel_relaxed(pred_a | pred_s, rtc->base + regs->prer);
drivers/rtc/rtc-stm32.c
1046
writel_relaxed(cr, rtc->base + regs->cr);
drivers/rtc/rtc-stm32.c
1227
writel_relaxed(cr, rtc->base + regs->cr);
drivers/rtc/rtc-stm32.c
191
writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr);
drivers/rtc/rtc-stm32.c
192
writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr);
drivers/rtc/rtc-stm32.c
199
writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr);
drivers/rtc/rtc-stm32.c
285
writel_relaxed(cr, rtc->base + regs.cr);
drivers/rtc/rtc-stm32.c
286
writel_relaxed(cfgr, rtc->base + regs.cfgr);
drivers/rtc/rtc-stm32.c
412
writel_relaxed(isr, rtc->base + regs->isr);
drivers/rtc/rtc-stm32.c
434
writel_relaxed(isr, rtc->base + regs->isr);
drivers/rtc/rtc-stm32.c
443
writel_relaxed(isr, rtc->base + regs->isr);
drivers/rtc/rtc-stm32.c
580
writel_relaxed(tr, rtc->base + regs->tr);
drivers/rtc/rtc-stm32.c
581
writel_relaxed(dr, rtc->base + regs->dr);
drivers/rtc/rtc-stm32.c
676
writel_relaxed(cr, rtc->base + regs->cr);
drivers/rtc/rtc-stm32.c
761
writel_relaxed(cr, rtc->base + regs->cr);
drivers/rtc/rtc-stm32.c
778
writel_relaxed(alrmar, rtc->base + regs->alrmar);
drivers/rtc/rtc-stm32.c
801
writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags,
drivers/rtc/rtc-stm32.c
863
writel_relaxed(flags, rtc->base + regs.scr);
drivers/rtc/rtc-stm32.c
939
writel_relaxed(cr, rtc->base + regs.cr);
drivers/rtc/rtc-stm32.c
947
writel_relaxed(cfgr, rtc->base + regs.cfgr);
drivers/slimbus/qcom-ngd-ctrl.c
1165
writel_relaxed(cfg, ctrl->ngd->base);
drivers/slimbus/qcom-ngd-ctrl.c
1216
writel_relaxed(DEF_NGD_INT_MASK, ngd->base + NGD_INT_EN);
drivers/slimbus/qcom-ngd-ctrl.c
1219
writel_relaxed(rx_msgq|SLIM_RX_MSGQ_TIMEOUT_VAL,
drivers/soc/amlogic/meson-canvas.c
44
writel_relaxed(val, canvas->reg_base + reg);
drivers/soc/apple/mailbox.c
137
writel_relaxed(mbox->hw->irq_bit_send_empty,
drivers/soc/apple/mailbox.c
212
writel_relaxed(mbox->hw->irq_bit_recv_not_empty,
drivers/soc/apple/mailbox.c
263
writel_relaxed(mbox->hw->irq_bit_recv_not_empty |
drivers/soc/dove/pmu.c
158
writel_relaxed(val, pmu_base + PMU_ISO);
drivers/soc/dove/pmu.c
165
writel_relaxed(val, pmc_base + PMC_SW_RST);
drivers/soc/dove/pmu.c
170
writel_relaxed(val, pmu_base + PMU_PWR);
drivers/soc/dove/pmu.c
190
writel_relaxed(val, pmu_base + PMU_PWR);
drivers/soc/dove/pmu.c
196
writel_relaxed(val, pmc_base + PMC_SW_RST);
drivers/soc/dove/pmu.c
203
writel_relaxed(val, pmu_base + PMU_ISO);
drivers/soc/dove/pmu.c
262
writel_relaxed(done, base + PMC_IRQ_CAUSE);
drivers/soc/dove/pmu.c
56
writel_relaxed(val & ~BIT(id), pmu->pmc_base + PMC_SW_RST);
drivers/soc/dove/pmu.c
57
writel_relaxed(val | BIT(id), pmu->pmc_base + PMC_SW_RST);
drivers/soc/dove/pmu.c
71
writel_relaxed(val, pmu->pmc_base + PMC_SW_RST);
drivers/soc/dove/pmu.c
85
writel_relaxed(val, pmu->pmc_base + PMC_SW_RST);
drivers/soc/fsl/dpio/qbman-portal.c
184
writel_relaxed(value, p->addr_cinh + offset);
drivers/soc/mediatek/mtk-mmsys.c
180
writel_relaxed(tmp, mmsys->regs + offset);
drivers/soc/mediatek/mtk-mutex.c
1066
writel_relaxed(reg, mtx->regs + offset);
drivers/soc/mediatek/mtk-mutex.c
1086
writel_relaxed(idx, mtx->regs +
drivers/soc/mediatek/mtk-mutex.c
931
writel_relaxed(reg, mtx->regs + offset);
drivers/soc/mediatek/mtk-mutex.c
935
writel_relaxed(mtx->data->mutex_sof[sof_id],
drivers/soc/mediatek/mtk-mutex.c
961
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
drivers/soc/mediatek/mtk-mutex.c
971
writel_relaxed(reg, mtx->regs + offset);
drivers/soc/mediatek/mtk-svs.c
566
writel_relaxed(val, svsp->base + svsp->regs[rg_i]);
drivers/soc/qcom/qcom-geni-se.c
1276
writel_relaxed(0x1, se->base + GENI_FORCE_DEFAULT_REG);
drivers/soc/qcom/qcom-geni-se.c
304
writel_relaxed(val, base + SE_IRQ_EN);
drivers/soc/qcom/qcom-geni-se.c
308
writel_relaxed(val, base + SE_GENI_DMA_MODE_EN);
drivers/soc/qcom/qcom-geni-se.c
310
writel_relaxed(0, base + SE_GSI_EVENT_EN);
drivers/soc/qcom/qcom-geni-se.c
319
writel_relaxed(val, base + SE_GENI_CGC_CTRL);
drivers/soc/qcom/qcom-geni-se.c
324
writel_relaxed(val, base + SE_DMA_GENERAL_CFG);
drivers/soc/qcom/qcom-geni-se.c
326
writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL);
drivers/soc/qcom/qcom-geni-se.c
327
writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG);
drivers/soc/qcom/qcom-geni-se.c
332
writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
drivers/soc/qcom/qcom-geni-se.c
333
writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
drivers/soc/qcom/qcom-geni-se.c
334
writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);
drivers/soc/qcom/qcom-geni-se.c
335
writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);
drivers/soc/qcom/qcom-geni-se.c
336
writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);
drivers/soc/qcom/qcom-geni-se.c
337
writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);
drivers/soc/qcom/qcom-geni-se.c
357
writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG);
drivers/soc/qcom/qcom-geni-se.c
358
writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG);
drivers/soc/qcom/qcom-geni-se.c
362
writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
drivers/soc/qcom/qcom-geni-se.c
366
writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
drivers/soc/qcom/qcom-geni-se.c
384
writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
drivers/soc/qcom/qcom-geni-se.c
390
writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
drivers/soc/qcom/qcom-geni-se.c
407
writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
drivers/soc/qcom/qcom-geni-se.c
413
writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
drivers/soc/qcom/qcom-geni-se.c
559
writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0);
drivers/soc/qcom/qcom-geni-se.c
560
writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1);
drivers/soc/qcom/qcom-geni-se.c
563
writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0);
drivers/soc/qcom/qcom-geni-se.c
564
writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1);
drivers/soc/qcom/qcom-geni-se.c
575
writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN);
drivers/soc/qcom/qcom-geni-se.c
778
writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET);
drivers/soc/qcom/qcom-geni-se.c
779
writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_TX_PTR_L);
drivers/soc/qcom/qcom-geni-se.c
780
writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_TX_PTR_H);
drivers/soc/qcom/qcom-geni-se.c
781
writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR);
drivers/soc/qcom/qcom-geni-se.c
829
writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET);
drivers/soc/qcom/qcom-geni-se.c
830
writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_RX_PTR_L);
drivers/soc/qcom/qcom-geni-se.c
831
writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_RX_PTR_H);
drivers/soc/qcom/qcom-geni-se.c
833
writel_relaxed(0, se->base + SE_DMA_RX_ATTR);
drivers/soc/qcom/qcom_gsbi.c
185
writel_relaxed((gsbi->mode << GSBI_PROTOCOL_SHIFT) | gsbi->crci,
drivers/soc/qcom/rpmh-rsc.c
1115
writel_relaxed(drv->tcs[ACTIVE_TCS].mask,
drivers/soc/qcom/rpmh-rsc.c
221
writel_relaxed(data, tcs_cmd_addr(drv, reg, tcs_id, cmd_id));
drivers/soc/qcom/rpmh-rsc.c
227
writel_relaxed(data, tcs_reg_addr(drv, reg, tcs_id));
drivers/soc/qcom/rpmh-rsc.c
427
writel_relaxed(data, drv->tcs_base + reg);
drivers/soc/qcom/rpmh-rsc.c
463
writel_relaxed(BIT(i), drv->tcs_base + drv->regs[RSC_DRV_IRQ_CLEAR]);
drivers/soc/qcom/rpmh-rsc.c
831
writel_relaxed(lo, drv->base + RSC_DRV_CTL_TCS_DATA_LO);
drivers/soc/qcom/rpmh-rsc.c
832
writel_relaxed(hi, drv->base + RSC_DRV_CTL_TCS_DATA_HI);
drivers/soc/qcom/spm.c
260
writel_relaxed(val, drv->reg_base +
drivers/soc/qcom/spm.c
274
writel_relaxed(val, drv->reg_base +
drivers/soc/samsung/exynos-pmu.c
50
writel_relaxed(val, pmu_base_addr + offset);
drivers/soc/tegra/fuse/tegra-apbmisc.c
119
writel_relaxed(ERD_MASK_INBAND_ERR,
drivers/soc/ti/knav_dma.c
155
writel_relaxed(v, &chan->reg_chan->mode);
drivers/soc/ti/knav_dma.c
156
writel_relaxed(DMA_ENABLE, &chan->reg_chan->control);
drivers/soc/ti/knav_dma.c
160
writel_relaxed(cfg->u.tx.priority, &chan->reg_tx_sched->prio);
drivers/soc/ti/knav_dma.c
178
writel_relaxed(v, &chan->reg_rx_flow->control);
drivers/soc/ti/knav_dma.c
179
writel_relaxed(0, &chan->reg_rx_flow->tags);
drivers/soc/ti/knav_dma.c
180
writel_relaxed(0, &chan->reg_rx_flow->tag_sel);
drivers/soc/ti/knav_dma.c
184
writel_relaxed(v, &chan->reg_rx_flow->fdq_sel[0]);
drivers/soc/ti/knav_dma.c
188
writel_relaxed(v, &chan->reg_rx_flow->fdq_sel[1]);
drivers/soc/ti/knav_dma.c
190
writel_relaxed(0, &chan->reg_rx_flow->thresh[0]);
drivers/soc/ti/knav_dma.c
191
writel_relaxed(0, &chan->reg_rx_flow->thresh[1]);
drivers/soc/ti/knav_dma.c
192
writel_relaxed(0, &chan->reg_rx_flow->thresh[2]);
drivers/soc/ti/knav_dma.c
210
writel_relaxed(DMA_TEARDOWN, &chan->reg_chan->control);
drivers/soc/ti/knav_dma.c
233
writel_relaxed(0, &chan->reg_rx_flow->fdq_sel[0]);
drivers/soc/ti/knav_dma.c
234
writel_relaxed(0, &chan->reg_rx_flow->fdq_sel[1]);
drivers/soc/ti/knav_dma.c
235
writel_relaxed(0, &chan->reg_rx_flow->thresh[0]);
drivers/soc/ti/knav_dma.c
236
writel_relaxed(0, &chan->reg_rx_flow->thresh[1]);
drivers/soc/ti/knav_dma.c
237
writel_relaxed(0, &chan->reg_rx_flow->thresh[2]);
drivers/soc/ti/knav_dma.c
245
writel_relaxed(0, &chan->reg_rx_flow->control);
drivers/soc/ti/knav_dma.c
246
writel_relaxed(0, &chan->reg_rx_flow->tags);
drivers/soc/ti/knav_dma.c
247
writel_relaxed(0, &chan->reg_rx_flow->tag_sel);
drivers/soc/ti/knav_dma.c
261
writel_relaxed(0, &dma->reg_tx_chan[i].mode);
drivers/soc/ti/knav_dma.c
262
writel_relaxed(DMA_ENABLE, &dma->reg_tx_chan[i].control);
drivers/soc/ti/knav_dma.c
274
writel_relaxed(v, &dma->reg_global->emulation_control);
drivers/soc/ti/knav_dma.c
278
writel_relaxed(v, &dma->reg_global->perf_control);
drivers/soc/ti/knav_dma.c
283
writel_relaxed(v, &dma->reg_global->priority_control);
drivers/soc/ti/knav_dma.c
287
writel_relaxed(DMA_ENABLE, &dma->reg_rx_chan[i].control);
drivers/soc/ti/knav_dma.c
290
writel_relaxed(dma->qm_base_address[i],
drivers/soc/ti/knav_dma.c
304
writel_relaxed(v, &dma->reg_rx_chan[i].control);
drivers/soc/ti/knav_dma.c
307
writel_relaxed(v, &dma->reg_tx_chan[i].control);
drivers/soc/ti/knav_qmss_acc.c
113
writel_relaxed(1, pdsp->intd + ACC_INTD_OFFSET_COUNT(channel));
drivers/soc/ti/knav_qmss_acc.c
115
writel_relaxed(ACC_CHANNEL_INT_BASE + channel,
drivers/soc/ti/knav_qmss_acc.c
186
writel_relaxed(1, pdsp->intd + ACC_INTD_OFFSET_COUNT(channel));
drivers/soc/ti/knav_qmss_acc.c
189
writel_relaxed(ACC_CHANNEL_INT_BASE + channel,
drivers/soc/ti/knav_qmss_acc.c
286
writel_relaxed(cmd->timer_config, &pdsp->acc_command->timer_config);
drivers/soc/ti/knav_qmss_acc.c
287
writel_relaxed(cmd->queue_num, &pdsp->acc_command->queue_num);
drivers/soc/ti/knav_qmss_acc.c
288
writel_relaxed(cmd->list_dma, &pdsp->acc_command->list_dma);
drivers/soc/ti/knav_qmss_acc.c
289
writel_relaxed(cmd->queue_mask, &pdsp->acc_command->queue_mask);
drivers/soc/ti/knav_qmss_acc.c
290
writel_relaxed(cmd->command, &pdsp->acc_command->command);
drivers/soc/ti/knav_qmss_acc.c
73
writel_relaxed(mask, pdsp->intd + offset);
drivers/soc/ti/knav_qmss_queue.c
1047
writel_relaxed((u32)region->dma_start, ®s->base);
drivers/soc/ti/knav_qmss_queue.c
1048
writel_relaxed(region->link_index, ®s->start_index);
drivers/soc/ti/knav_qmss_queue.c
1049
writel_relaxed(hw_desc_size << 16 | hw_num_desc,
drivers/soc/ti/knav_qmss_queue.c
1185
writel_relaxed((u32)block->dma, &qmgr->reg_config->link_ram_base0);
drivers/soc/ti/knav_qmss_queue.c
1187
writel_relaxed(block->size,
drivers/soc/ti/knav_qmss_queue.c
1190
writel_relaxed(block->size - 1,
drivers/soc/ti/knav_qmss_queue.c
1198
writel_relaxed(block->dma, &qmgr->reg_config->link_ram_base1);
drivers/soc/ti/knav_qmss_queue.c
1282
writel_relaxed(THRESH_GTE | 1,
drivers/soc/ti/knav_qmss_queue.c
1284
writel_relaxed(0,
drivers/soc/ti/knav_qmss_queue.c
1549
writel_relaxed(val, &pdsp->regs->control);
drivers/soc/ti/knav_qmss_queue.c
1589
writel_relaxed(pdsp->id + 1, pdsp->command + 0x18);
drivers/soc/ti/knav_qmss_queue.c
1594
writel_relaxed(be32_to_cpu(fwdata[i]), pdsp->iram + i);
drivers/soc/ti/knav_qmss_queue.c
1607
writel_relaxed(0xffffffff, pdsp->command);
drivers/soc/ti/knav_qmss_queue.c
1614
writel_relaxed(val, &pdsp->regs->control);
drivers/soc/ti/knav_qmss_queue.c
1618
writel_relaxed(val, &pdsp->regs->control);
drivers/soc/ti/knav_qmss_queue.c
508
writel_relaxed(0, &inst->qmgr->reg_push[id].ptr_size_thresh);
drivers/soc/ti/knav_qmss_queue.c
640
writel_relaxed(val, &qh->reg_push[0].ptr_size_thresh);
drivers/soc/ti/pm33xx.c
322
writel_relaxed(1 << (retrigger_irq & 31),
drivers/spi/atmel-quadspi.c
418
writel_relaxed(value, aq->regs + offset);
drivers/spi/spi-apple.c
131
writel_relaxed(value, spi->regs + offset);
drivers/spi/spi-at91-usart.c
71
writel_relaxed((value), (port)->regs + US_##reg)
drivers/spi/spi-atmel.c
228
writel_relaxed((value), (port)->regs + SPI_##reg)
drivers/spi/spi-axi-spi-engine.c
1006
writel_relaxed(SPI_ENGINE_CMD_SYNC(0),
drivers/spi/spi-axi-spi-engine.c
1009
writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CONFIG,
drivers/spi/spi-axi-spi-engine.c
1014
writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_XFER_BITS,
drivers/spi/spi-axi-spi-engine.c
1019
writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK,
drivers/spi/spi-axi-spi-engine.c
1022
writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK,
drivers/spi/spi-axi-spi-engine.c
1027
writel_relaxed(SPI_ENGINE_CMD_SYNC(1),
drivers/spi/spi-axi-spi-engine.c
1038
writel_relaxed(reg, spi_engine->base +
drivers/spi/spi-axi-spi-engine.c
1052
writel_relaxed(reg, spi_engine->base +
drivers/spi/spi-axi-spi-engine.c
1057
writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK,
drivers/spi/spi-axi-spi-engine.c
1060
writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK,
drivers/spi/spi-axi-spi-engine.c
1099
writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
drivers/spi/spi-axi-spi-engine.c
1100
writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
drivers/spi/spi-axi-spi-engine.c
1101
writel_relaxed(0x01, spi_engine->base + SPI_ENGINE_REG_RESET);
drivers/spi/spi-axi-spi-engine.c
1203
writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_RESET);
drivers/spi/spi-axi-spi-engine.c
1204
writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
drivers/spi/spi-axi-spi-engine.c
1205
writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
drivers/spi/spi-axi-spi-engine.c
565
writel_relaxed(buf[i], addr);
drivers/spi/spi-axi-spi-engine.c
588
writel_relaxed(buf[i], addr);
drivers/spi/spi-axi-spi-engine.c
596
writel_relaxed(buf[i], addr);
drivers/spi/spi-axi-spi-engine.c
604
writel_relaxed(buf[i], addr);
drivers/spi/spi-axi-spi-engine.c
670
writel_relaxed(SPI_ENGINE_INT_SYNC,
drivers/spi/spi-axi-spi-engine.c
704
writel_relaxed(spi_engine->int_enable,
drivers/spi/spi-axi-spi-engine.c
771
writel_relaxed(buf[i], sdo_addr);
drivers/spi/spi-axi-spi-engine.c
776
writel_relaxed(buf[i], sdo_addr);
drivers/spi/spi-axi-spi-engine.c
781
writel_relaxed(buf[i], sdo_addr);
drivers/spi/spi-axi-spi-engine.c
786
writel_relaxed(p->instructions[i], cmd_addr);
drivers/spi/spi-axi-spi-engine.c
796
writel_relaxed(1, spi_engine->base +
drivers/spi/spi-axi-spi-engine.c
798
writel_relaxed(0, spi_engine->base +
drivers/spi/spi-axi-spi-engine.c
896
writel_relaxed(SPI_ENGINE_CMD_SYNC(0),
drivers/spi/spi-axi-spi-engine.c
899
writel_relaxed(SPI_ENGINE_CMD_CS_INV(spi_engine->cs_inv),
drivers/spi/spi-axi-spi-engine.c
907
writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK,
drivers/spi/spi-axi-spi-engine.c
910
writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK,
drivers/spi/spi-axi-spi-engine.c
919
writel_relaxed(SPI_ENGINE_CMD_ASSERT(0, 0xff),
drivers/spi/spi-axi-spi-engine.c
922
writel_relaxed(SPI_ENGINE_CMD_SYNC(1),
drivers/spi/spi-axi-spi-engine.c
974
writel_relaxed(int_enable,
drivers/spi/spi-axiado.c
44
writel_relaxed(val, xspi->regs + offset);
drivers/spi/spi-bcm-qspi.h
77
writel_relaxed(data, addr);
drivers/spi/spi-cadence.c
150
writel_relaxed(val, xspi->regs + offset);
drivers/spi/spi-dw.h
234
writel_relaxed(val, dws->regs + offset);
drivers/spi/spi-meson-spicc.c
1013
writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER,
drivers/spi/spi-meson-spicc.c
1017
writel_relaxed(0, spicc->base + SPICC_INTREG);
drivers/spi/spi-meson-spicc.c
167
writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
drivers/spi/spi-meson-spicc.c
230
writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);
drivers/spi/spi-meson-spicc.c
314
writel_relaxed(spicc->tx_dma, spicc->base + SPICC_DRADDR);
drivers/spi/spi-meson-spicc.c
315
writel_relaxed(spicc->rx_dma, spicc->base + SPICC_DWADDR);
drivers/spi/spi-meson-spicc.c
346
writel_relaxed(count_en, spicc->base + SPICC_LD_CNTL0);
drivers/spi/spi-meson-spicc.c
347
writel_relaxed(ld_ctr1, spicc->base + SPICC_LD_CNTL1);
drivers/spi/spi-meson-spicc.c
348
writel_relaxed(SPICC_DMA_ENABLE
drivers/spi/spi-meson-spicc.c
366
writel_relaxed(0, spicc->base + SPICC_INTREG);
drivers/spi/spi-meson-spicc.c
367
writel_relaxed(0, spicc->base + SPICC_DMAREG);
drivers/spi/spi-meson-spicc.c
434
writel_relaxed(meson_spicc_pull_data(spicc),
drivers/spi/spi-meson-spicc.c
530
writel_relaxed(conf, spicc->base + SPICC_TESTREG);
drivers/spi/spi-meson-spicc.c
548
writel_relaxed(conf, spicc->base + SPICC_CONREG);
drivers/spi/spi-meson-spicc.c
554
writel_relaxed(0, spicc->base + SPICC_DMAREG);
drivers/spi/spi-meson-spicc.c
632
writel_relaxed(SPICC_TE_EN, spicc->base + SPICC_INTREG);
drivers/spi/spi-meson-spicc.c
643
writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG);
drivers/spi/spi-meson-spicc.c
707
writel_relaxed(conf, spicc->base + SPICC_CONREG);
drivers/spi/spi-meson-spicc.c
710
writel_relaxed(0, spicc->base + SPICC_PERIODREG);
drivers/spi/spi-meson-spicc.c
730
writel_relaxed(conf, spicc->base + SPICC_CONREG);
drivers/spi/spi-microchip-core-qspi.c
156
writel_relaxed(control, qspi->regs + REG_CONTROL);
drivers/spi/spi-microchip-core-qspi.c
175
writel_relaxed(control, qspi->regs + REG_CONTROL);
drivers/spi/spi-microchip-core-qspi.c
187
writel_relaxed(control, qspi->regs + REG_CONTROL);
drivers/spi/spi-microchip-core-qspi.c
203
writel_relaxed(control, qspi->regs + REG_CONTROL);
drivers/spi/spi-microchip-core-qspi.c
211
writel_relaxed(data, qspi->regs + REG_X4_TX_DATA);
drivers/spi/spi-microchip-core-qspi.c
215
writel_relaxed(control, qspi->regs + REG_CONTROL);
drivers/spi/spi-microchip-core-qspi.c
221
writel_relaxed(data, qspi->regs + REG_TX_DATA);
drivers/spi/spi-microchip-core-qspi.c
233
writel_relaxed(control, qspi->regs + REG_CONTROL);
drivers/spi/spi-microchip-core-qspi.c
243
writel_relaxed(data, qspi->regs + REG_X4_TX_DATA);
drivers/spi/spi-microchip-core-qspi.c
288
writel_relaxed(control, qspi->regs + REG_CONTROL);
drivers/spi/spi-microchip-core-qspi.c
295
writel_relaxed(data, qspi->regs + REG_TX_DATA);
drivers/spi/spi-microchip-core-qspi.c
312
writel_relaxed(mask, qspi->regs + REG_IEN);
drivers/spi/spi-microchip-core-qspi.c
317
writel_relaxed(0, qspi->regs + REG_IEN);
drivers/spi/spi-microchip-core-qspi.c
330
writel_relaxed(IEN_TXDONE, qspi->regs + REG_STATUS);
drivers/spi/spi-microchip-core-qspi.c
335
writel_relaxed(IEN_RXAVAILABLE, qspi->regs + REG_STATUS);
drivers/spi/spi-microchip-core-qspi.c
341
writel_relaxed(IEN_RXDONE, qspi->regs + REG_STATUS);
drivers/spi/spi-microchip-core-qspi.c
370
writel_relaxed(control, qspi->regs + REG_CONTROL);
drivers/spi/spi-microchip-core-qspi.c
378
writel_relaxed(control, qspi->regs + REG_CONTROL);
drivers/spi/spi-microchip-core-qspi.c
391
writel_relaxed(control, qspi->regs + REG_CONTROL);
drivers/spi/spi-microchip-core-qspi.c
434
writel_relaxed(frames, qspi->regs + REG_FRAMESUP);
drivers/spi/spi-microchip-core-qspi.c
448
writel_relaxed(frames, qspi->regs + REG_FRAMES);
drivers/spi/spi-microchip-core-qspi.c
619
writel_relaxed(control, qspi->regs + REG_CONTROL);
drivers/spi/spi-microchip-core-qspi.c
644
writel_relaxed(control, qspi->regs + REG_CONTROL);
drivers/spi/spi-microchip-core-qspi.c
647
writel_relaxed(frames, qspi->regs + REG_FRAMESUP);
drivers/spi/spi-microchip-core-qspi.c
656
writel_relaxed(frames, qspi->regs + REG_FRAMES);
drivers/spi/spi-microchip-core-qspi.c
750
writel_relaxed(control, qspi->regs + REG_CONTROL);
drivers/spi/spi-omap2-mcspi.c
1220
writel_relaxed(0, cs->base
drivers/spi/spi-omap2-mcspi.c
1325
writel_relaxed(cs->chconf0,
drivers/spi/spi-omap2-mcspi.c
1424
writel_relaxed(cs->chconf0,
drivers/spi/spi-omap2-mcspi.c
1427
writel_relaxed(cs->chconf0,
drivers/spi/spi-omap2-mcspi.c
1430
writel_relaxed(cs->chconf0,
drivers/spi/spi-omap2-mcspi.c
155
writel_relaxed(val, mcspi->base + idx);
drivers/spi/spi-omap2-mcspi.c
170
writel_relaxed(val, cs->base + idx);
drivers/spi/spi-omap2-mcspi.c
745
writel_relaxed(*tx++, tx_reg);
drivers/spi/spi-omap2-mcspi.c
794
writel_relaxed(*tx++, tx_reg);
drivers/spi/spi-omap2-mcspi.c
843
writel_relaxed(*tx++, tx_reg);
drivers/spi/spi-qup.c
1019
writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL);
drivers/spi/spi-qup.c
1160
writel_relaxed(1, base + QUP_SW_RESET);
drivers/spi/spi-qup.c
1168
writel_relaxed(0, base + QUP_OPERATIONAL);
drivers/spi/spi-qup.c
1169
writel_relaxed(0, base + QUP_IO_M_MODES);
drivers/spi/spi-qup.c
1172
writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
drivers/spi/spi-qup.c
1174
writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN,
drivers/spi/spi-qup.c
1179
writel_relaxed(QUP_ERROR_OUTPUT_OVER_RUN |
drivers/spi/spi-qup.c
1183
writel_relaxed(0, base + SPI_CONFIG);
drivers/spi/spi-qup.c
1184
writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
drivers/spi/spi-qup.c
1224
writel_relaxed(config, controller->base + QUP_CONFIG);
drivers/spi/spi-qup.c
1253
writel_relaxed(config, controller->base + QUP_CONFIG);
drivers/spi/spi-qup.c
233
writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
drivers/spi/spi-qup.c
234
writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
drivers/spi/spi-qup.c
238
writel_relaxed(cur_state, controller->base + QUP_STATE);
drivers/spi/spi-qup.c
297
writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
drivers/spi/spi-qup.c
336
writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
drivers/spi/spi-qup.c
361
writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
drivers/spi/spi-qup.c
383
writel_relaxed(QUP_OP_OUT_SERVICE_FLAG,
drivers/spi/spi-qup.c
632
writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
drivers/spi/spi-qup.c
633
writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
drivers/spi/spi-qup.c
663
writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
drivers/spi/spi-qup.c
743
writel_relaxed(controller->n_words,
drivers/spi/spi-qup.c
745
writel_relaxed(controller->n_words,
drivers/spi/spi-qup.c
748
writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
drivers/spi/spi-qup.c
749
writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
drivers/spi/spi-qup.c
752
writel_relaxed(controller->n_words,
drivers/spi/spi-qup.c
754
writel_relaxed(controller->n_words,
drivers/spi/spi-qup.c
757
writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
drivers/spi/spi-qup.c
758
writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
drivers/spi/spi-qup.c
771
writel_relaxed(0, input_cnt);
drivers/spi/spi-qup.c
773
writel_relaxed(controller->n_words, input_cnt);
drivers/spi/spi-qup.c
775
writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
drivers/spi/spi-qup.c
780
writel_relaxed(controller->n_words,
drivers/spi/spi-qup.c
782
writel_relaxed(controller->n_words,
drivers/spi/spi-qup.c
785
writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
drivers/spi/spi-qup.c
786
writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
drivers/spi/spi-qup.c
806
writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
drivers/spi/spi-qup.c
815
writel_relaxed(control, controller->base + SPI_IO_CONTROL);
drivers/spi/spi-qup.c
838
writel_relaxed(config, controller->base + SPI_CONFIG);
drivers/spi/spi-qup.c
852
writel_relaxed(config, controller->base + QUP_CONFIG);
drivers/spi/spi-qup.c
866
writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
drivers/spi/spi-rockchip-sfc.c
195
writel_relaxed(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR);
drivers/spi/spi-rockchip-sfc.c
204
writel_relaxed(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
drivers/spi/spi-rockchip-sfc.c
599
writel_relaxed(reg, sfc->regbase + SFC_ICLR);
drivers/spi/spi-rockchip.c
203
writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
drivers/spi/spi-rockchip.c
21
writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
drivers/spi/spi-rockchip.c
23
writel_relaxed(readl_relaxed(reg) | (bits), reg)
drivers/spi/spi-rockchip.c
291
writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
drivers/spi/spi-rockchip.c
292
writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
drivers/spi/spi-rockchip.c
315
writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
drivers/spi/spi-rockchip.c
362
writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
drivers/spi/spi-rockchip.c
363
writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
drivers/spi/spi-rockchip.c
374
writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
drivers/spi/spi-rockchip.c
375
writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
drivers/spi/spi-rockchip.c
391
writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
drivers/spi/spi-rockchip.c
399
writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
drivers/spi/spi-rockchip.c
401
writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
drivers/spi/spi-rockchip.c
417
writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
drivers/spi/spi-rockchip.c
517
writel_relaxed(INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
drivers/spi/spi-rockchip.c
590
writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
drivers/spi/spi-rockchip.c
591
writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
drivers/spi/spi-rockchip.c
598
writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
drivers/spi/spi-rockchip.c
600
writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
drivers/spi/spi-rockchip.c
602
writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
drivers/spi/spi-rockchip.c
603
writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1,
drivers/spi/spi-rockchip.c
605
writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
drivers/spi/spi-rockchip.c
611
writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
drivers/spi/spi-rockchip.c
750
writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
drivers/spi/spi-sprd-adi.c
242
writel_relaxed(reg, sadi->base + REG_ADI_RD_CMD);
drivers/spi/spi-sprd-adi.c
315
writel_relaxed(val, (void __iomem *)(sadi->slave_vbase + reg));
drivers/spi/spi-sprd-adi.c
467
writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
drivers/spi/spi-sprd-adi.c
468
writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);
drivers/spi/spi-sprd-adi.c
473
writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);
drivers/spi/spi-sprd-adi.c
492
writel_relaxed(chn_config, sadi->base +
drivers/spi/spi-sprd-adi.c
498
writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
drivers/spi/spi-sprd-adi.c
502
writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
drivers/spi/spi-sprd.c
213
writel_relaxed(SPRD_SPI_TX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR);
drivers/spi/spi-sprd.c
231
writel_relaxed(SPRD_SPI_RX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR);
drivers/spi/spi-sprd.c
238
writel_relaxed(SPRD_SPI_SW_TX_REQ, ss->base + SPRD_SPI_CTL12);
drivers/spi/spi-sprd.c
243
writel_relaxed(SPRD_SPI_SW_RX_REQ, ss->base + SPRD_SPI_CTL12);
drivers/spi/spi-sprd.c
251
writel_relaxed(val, ss->base + SPRD_SPI_CTL1);
drivers/spi/spi-sprd.c
261
writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
drivers/spi/spi-sprd.c
271
writel_relaxed(val, ss->base + SPRD_SPI_CTL8);
drivers/spi/spi-sprd.c
274
writel_relaxed(val, ss->base + SPRD_SPI_CTL9);
drivers/spi/spi-sprd.c
284
writel_relaxed(val, ss->base + SPRD_SPI_CTL10);
drivers/spi/spi-sprd.c
287
writel_relaxed(val, ss->base + SPRD_SPI_CTL11);
drivers/spi/spi-sprd.c
300
writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
drivers/spi/spi-sprd.c
303
writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
drivers/spi/spi-sprd.c
314
writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
drivers/spi/spi-sprd.c
319
writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
drivers/spi/spi-sprd.c
324
writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
drivers/spi/spi-sprd.c
359
writel_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);
drivers/spi/spi-sprd.c
461
writel_relaxed(SPRD_SPI_TX_END_CLR | SPRD_SPI_RX_END_CLR,
drivers/spi/spi-sprd.c
465
writel_relaxed(val | SPRD_SPI_TX_END_INT_EN |
drivers/spi/spi-sprd.c
472
writel_relaxed(0, ss->base + SPRD_SPI_INT_EN);
drivers/spi/spi-sprd.c
484
writel_relaxed(val, ss->base + SPRD_SPI_CTL2);
drivers/spi/spi-sprd.c
661
writel_relaxed(clk_div, ss->base + SPRD_SPI_CLKD);
drivers/spi/spi-sprd.c
678
writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
drivers/spi/spi-sprd.c
689
writel_relaxed(interval, ss->base + SPRD_SPI_CTL5);
drivers/spi/spi-sprd.c
692
writel_relaxed(1, ss->base + SPRD_SPI_FIFO_RST);
drivers/spi/spi-sprd.c
693
writel_relaxed(0, ss->base + SPRD_SPI_FIFO_RST);
drivers/spi/spi-sprd.c
709
writel_relaxed(val, ss->base + SPRD_SPI_CTL7);
drivers/spi/spi-sprd.c
774
writel_relaxed(val | mode, ss->base + SPRD_SPI_CTL1);
drivers/spi/spi-sprd.c
820
writel_relaxed(SPRD_SPI_TX_END_CLR, ss->base + SPRD_SPI_INT_CLR);
drivers/spi/spi-sprd.c
828
writel_relaxed(SPRD_SPI_RX_END_CLR, ss->base + SPRD_SPI_INT_CLR);
drivers/spi/spi-st-ssc4.c
146
writel_relaxed((ctl | 0xf), spi_st->base + SSC_CTL);
drivers/spi/spi-st-ssc4.c
159
writel_relaxed(SSC_IEN_TEEN, spi_st->base + SSC_IEN);
drivers/spi/spi-st-ssc4.c
166
writel_relaxed(ctl, spi_st->base + SSC_CTL);
drivers/spi/spi-st-ssc4.c
205
writel_relaxed(sscbrg, spi_st->base + SSC_BRG);
drivers/spi/spi-st-ssc4.c
241
writel_relaxed(var, spi_st->base + SSC_CTL);
drivers/spi/spi-st-ssc4.c
262
writel_relaxed(0x0, spi_st->base + SSC_IEN);
drivers/spi/spi-st-ssc4.c
317
writel_relaxed(0x0, spi_st->base + SSC_I2C);
drivers/spi/spi-st-ssc4.c
320
writel_relaxed(var, spi_st->base + SSC_CTL);
drivers/spi/spi-st-ssc4.c
325
writel_relaxed(var, spi_st->base + SSC_CTL);
drivers/spi/spi-st-ssc4.c
330
writel_relaxed(var, spi_st->base + SSC_CTL);
drivers/spi/spi-st-ssc4.c
386
writel_relaxed(0, spi_st->base + SSC_IEN);
drivers/spi/spi-st-ssc4.c
88
writel_relaxed(word, spi_st->base + SSC_TBUF);
drivers/spi/spi-stm32-ospi.c
1000
writel_relaxed(0, ospi->regs_base + OSPI_CR);
drivers/spi/spi-stm32-ospi.c
1047
writel_relaxed(ospi->cr_reg, regs_base + OSPI_CR);
drivers/spi/spi-stm32-ospi.c
1048
writel_relaxed(ospi->dcr_reg, regs_base + OSPI_DCR1);
drivers/spi/spi-stm32-ospi.c
160
writel_relaxed(*((u32 *)val), addr);
drivers/spi/spi-stm32-ospi.c
177
writel_relaxed(cr, regs_base + OSPI_CR);
drivers/spi/spi-stm32-ospi.c
258
writel_relaxed(FCR_CTCF | FCR_CTEF, regs_base + OSPI_FCR);
drivers/spi/spi-stm32-ospi.c
285
writel_relaxed(cr, regs_base + OSPI_CR);
drivers/spi/spi-stm32-ospi.c
386
writel_relaxed(cr | CR_DMAEN, regs_base + OSPI_CR);
drivers/spi/spi-stm32-ospi.c
397
writel_relaxed(cr & ~CR_DMAEN, regs_base + OSPI_CR);
drivers/spi/spi-stm32-ospi.c
436
writel_relaxed(cr | CR_SMIE, regs_base + OSPI_CR);
drivers/spi/spi-stm32-ospi.c
447
writel_relaxed(FCR_CSMF, regs_base + OSPI_FCR);
drivers/spi/spi-stm32-ospi.c
482
writel_relaxed(cr, regs_base + OSPI_CR);
drivers/spi/spi-stm32-ospi.c
485
writel_relaxed(op->data.nbytes - 1, regs_base + OSPI_DLR);
drivers/spi/spi-stm32-ospi.c
490
writel_relaxed(dcr2, regs_base + OSPI_DCR2);
drivers/spi/spi-stm32-ospi.c
505
writel_relaxed(tcr, regs_base + OSPI_TCR);
drivers/spi/spi-stm32-ospi.c
512
writel_relaxed(ccr, regs_base + OSPI_CCR);
drivers/spi/spi-stm32-ospi.c
515
writel_relaxed(op->cmd.opcode, regs_base + OSPI_IR);
drivers/spi/spi-stm32-ospi.c
518
writel_relaxed(op->addr.val, regs_base + OSPI_AR);
drivers/spi/spi-stm32-ospi.c
544
writel_relaxed(FCR_CTCF | FCR_CSMF, regs_base + OSPI_FCR);
drivers/spi/spi-stm32-ospi.c
570
writel_relaxed(mask, regs_base + OSPI_PSMKR);
drivers/spi/spi-stm32-ospi.c
571
writel_relaxed(match, regs_base + OSPI_PSMAR);
drivers/spi/spi-stm32-ospi.c
769
writel_relaxed(ospi->cr_reg, regs_base + OSPI_CR);
drivers/spi/spi-stm32-ospi.c
773
writel_relaxed(ospi->dcr_reg, regs_base + OSPI_DCR1);
drivers/spi/spi-stm32-ospi.c
967
writel_relaxed(0, ospi->regs_base + OSPI_CR);
drivers/spi/spi-stm32-qspi.c
138
writel_relaxed(cr, qspi->io_base + QSPI_CR);
drivers/spi/spi-stm32-qspi.c
163
writel_relaxed(*((u32 *)val), addr);
drivers/spi/spi-stm32-qspi.c
277
writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR);
drivers/spi/spi-stm32-qspi.c
288
writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR);
drivers/spi/spi-stm32-qspi.c
337
writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR);
drivers/spi/spi-stm32-qspi.c
350
writel_relaxed(cr | CR_SMIE, qspi->io_base + QSPI_CR);
drivers/spi/spi-stm32-qspi.c
356
writel_relaxed(FCR_CSMF, qspi->io_base + QSPI_FCR);
drivers/spi/spi-stm32-qspi.c
380
writel_relaxed(cr, qspi->io_base + QSPI_CR);
drivers/spi/spi-stm32-qspi.c
383
writel_relaxed(op->data.nbytes - 1,
drivers/spi/spi-stm32-qspi.c
406
writel_relaxed(ccr, qspi->io_base + QSPI_CCR);
drivers/spi/spi-stm32-qspi.c
409
writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
drivers/spi/spi-stm32-qspi.c
435
writel_relaxed(cr, qspi->io_base + QSPI_CR);
drivers/spi/spi-stm32-qspi.c
442
writel_relaxed(FCR_CTCF | FCR_CSMF, qspi->io_base + QSPI_FCR);
drivers/spi/spi-stm32-qspi.c
469
writel_relaxed(mask, qspi->io_base + QSPI_PSMKR);
drivers/spi/spi-stm32-qspi.c
470
writel_relaxed(match, qspi->io_base + QSPI_PSMAR);
drivers/spi/spi-stm32-qspi.c
687
writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
drivers/spi/spi-stm32-qspi.c
691
writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
drivers/spi/spi-stm32-qspi.c
881
writel_relaxed(0, qspi->io_base + QSPI_CR);
drivers/spi/spi-stm32-qspi.c
902
writel_relaxed(0, qspi->io_base + QSPI_CR);
drivers/spi/spi-stm32-qspi.c
950
writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
drivers/spi/spi-stm32-qspi.c
951
writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
drivers/spi/spi-stm32.c
1141
writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
drivers/spi/spi-stm32.c
1228
writel_relaxed(
drivers/spi/spi-stm32.c
1402
writel_relaxed(sr & STM32H7_SPI_SR_SUSP, spi->base + STM32H7_SPI_IFCR);
drivers/spi/spi-stm32.c
1449
writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
drivers/spi/spi-stm32.c
1796
writel_relaxed(
drivers/spi/spi-stm32.c
1822
writel_relaxed(
drivers/spi/spi-stm32.c
1840
writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
drivers/spi/spi-stm32.c
1931
writel_relaxed(
drivers/spi/spi-stm32.c
1979
writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
drivers/spi/spi-stm32.c
1992
writel_relaxed(FIELD_PREP(STM32H7_SPI_CR2_TSIZE, nb_words),
drivers/spi/spi-stm32.c
2026
writel_relaxed(readl_relaxed(spi->base + spi->cfg->regs->rdy_en.reg) &
drivers/spi/spi-stm32.c
449
writel_relaxed(readl_relaxed(spi->base + offset) | bits,
drivers/spi/spi-stm32.c
456
writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
drivers/spi/spi-stm32.c
686
writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
drivers/spi/spi-stm32.c
919
writel_relaxed(0, spi->base + STM32H7_SPI_IER);
drivers/spi/spi-stm32.c
920
writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
drivers/spi/spi-zynq-qspi.c
157
writel_relaxed(val, xqspi->regs + offset);
drivers/spi/spi-zynq-qspi.c
438
writel_relaxed(0, xqspi->regs +
drivers/spi/spi-zynqmp-gqspi.c
233
writel_relaxed(val, (xqspi->regs + offset));
drivers/spmi/spmi-pmic-arb.c
269
writel_relaxed(val, pmic_arb->wr_base + offset);
drivers/spmi/spmi-pmic-arb.c
275
writel_relaxed(val, pmic_arb->rd_base + offset);
drivers/spmi/spmi-pmic-arb.c
669
writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(bus, apid));
drivers/spmi/spmi-pmic-arb.c
779
writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(bus, apid));
drivers/spmi/spmi-pmic-arb.c
802
writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT,
drivers/staging/media/meson/vdec/vdec_helpers.c
25
writel_relaxed(val, core->dos_base + reg);
drivers/staging/media/meson/vdec/vdec_helpers.c
49
writel_relaxed(val, core->esparser_base + reg);
drivers/staging/media/tegra-video/tegra210.c
150
writel_relaxed(val, chan->vi->iomem + addr);
drivers/staging/media/tegra-video/tegra210.c
166
writel_relaxed(val, vi_csi_base + addr);
drivers/staging/media/tegra-video/tegra210.c
837
writel_relaxed(val, csi_pp_base + addr);
drivers/staging/media/tegra-video/tegra210.c
849
writel_relaxed(val, csi_pp_base + offset + addr);
drivers/staging/media/tegra-video/tegra210.c
873
writel_relaxed(val, csi_cil_base + offset + addr);
drivers/staging/media/tegra-video/tegra210.c
899
writel_relaxed(val, csi_pp_base + offset + addr);
drivers/staging/nvec/nvec.c
583
writel_relaxed(val, reg);
drivers/thermal/imx8mm_thermal.c
161
writel_relaxed(val, tmu->base + TER);
drivers/thermal/imx8mm_thermal.c
170
writel_relaxed(val, tmu->base + TPS);
drivers/thermal/imx91_thermal.c
127
writel_relaxed(IMX91_TMU_CTRL0_THR1_IE, tmu->base + IMX91_TMU_CTRL0 + REG_CLR);
drivers/thermal/imx91_thermal.c
130
writel_relaxed(IMX91_TMU_THR_CTRL01_THR1_MASK, tmu->base + IMX91_TMU_THR_CTRL01 + REG_CLR);
drivers/thermal/imx91_thermal.c
133
writel_relaxed(val, tmu->base + IMX91_TMU_THR_CTRL01 + REG_SET);
drivers/thermal/imx91_thermal.c
135
writel_relaxed(IMX91_TMU_STAT0_THR1_IF, tmu->base + IMX91_TMU_STAT0 + REG_CLR);
drivers/thermal/imx91_thermal.c
137
writel_relaxed(IMX91_TMU_CTRL0_THR1_IE, tmu->base + IMX91_TMU_CTRL0 + REG_SET);
drivers/thermal/imx91_thermal.c
159
writel_relaxed(trim1, tmu->base + IMX91_TMU_TRIM1);
drivers/thermal/imx91_thermal.c
160
writel_relaxed(trim2, tmu->base + IMX91_TMU_TRIM2);
drivers/thermal/imx91_thermal.c
184
writel_relaxed(IMX91_TMU_CTRL0_THR1_IE, tmu->base + IMX91_TMU_CTRL0 + REG_CLR);
drivers/thermal/imx91_thermal.c
211
writel_relaxed(IMX91_TMU_CTRL0_THR1_IE | IMX91_TMU_CTRL0_THR1_MASK,
drivers/thermal/imx91_thermal.c
214
writel_relaxed(FIELD_PREP(IMX91_TMU_CTRL0_THR1_MASK, IMX91_TMU_THR_MODE_GE),
drivers/thermal/imx91_thermal.c
218
writel_relaxed(IMX91_TMU_CTRL0_THR1_IE, tmu->base + IMX91_TMU_CTRL0 + REG_CLR);
drivers/thermal/imx91_thermal.c
264
writel_relaxed(IMX91_TMU_DEFAULT_TRIM1_CONFIG, tmu->base + IMX91_TMU_TRIM1);
drivers/thermal/imx91_thermal.c
265
writel_relaxed(IMX91_TMU_DEFAULT_TRIM2_CONFIG, tmu->base + IMX91_TMU_TRIM2);
drivers/thermal/imx91_thermal.c
275
writel_relaxed(IMX91_TMU_DIV_EN | FIELD_PREP(IMX91_TMU_DIV_MASK, div),
drivers/thermal/imx91_thermal.c
279
writel_relaxed(FIELD_PREP(IMX91_TMU_PUDL_MASK, 100U), tmu->base + IMX91_TMU_PUD_ST_CTRL);
drivers/thermal/imx91_thermal.c
288
writel_relaxed(FIELD_PREP(IMX91_TMU_CTRL1_RES_MASK, 0x3),
drivers/thermal/imx91_thermal.c
290
writel_relaxed(FIELD_PREP(IMX91_TMU_CTRL1_RES_MASK, 0x1),
drivers/thermal/imx91_thermal.c
293
writel_relaxed(IMX91_TMU_CTRL1_MEAS_MODE_MASK, tmu->base + IMX91_TMU_CTRL1 + REG_CLR);
drivers/thermal/imx91_thermal.c
294
writel_relaxed(FIELD_PREP(IMX91_TMU_CTRL1_MEAS_MODE_MASK,
drivers/thermal/imx91_thermal.c
302
writel_relaxed(FIELD_PREP(IMX91_TMU_PERIOD_CTRL_MEAS_MASK, 4 * HZ_PER_MHZ / 25),
drivers/thermal/imx91_thermal.c
85
writel_relaxed(val, tmu->base + IMX91_TMU_CTRL1 + REG_SET);
drivers/thermal/imx91_thermal.c
94
writel_relaxed(IMX91_TMU_CTRL1_EN, tmu->base + reg);
drivers/thermal/rockchip_thermal.c
1006
writel_relaxed(TSADCV2_INT_SRC_EN_MASK(chn),
drivers/thermal/rockchip_thermal.c
1014
writel_relaxed(alarm_value & table->data_mask,
drivers/thermal/rockchip_thermal.c
1016
writel_relaxed(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn),
drivers/thermal/rockchip_thermal.c
1031
writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
drivers/thermal/rockchip_thermal.c
1035
writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
drivers/thermal/rockchip_thermal.c
1050
writel_relaxed(tshut_value, regs + TSADCV3_COMP_SHUT(chn));
drivers/thermal/rockchip_thermal.c
1053
writel_relaxed(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn),
drivers/thermal/rockchip_thermal.c
1073
writel_relaxed(val, regs + TSADCV2_INT_EN);
drivers/thermal/rockchip_thermal.c
1088
writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN);
drivers/thermal/rockchip_thermal.c
1089
writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN);
drivers/thermal/rockchip_thermal.c
716
writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
drivers/thermal/rockchip_thermal.c
719
writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
drivers/thermal/rockchip_thermal.c
722
writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
drivers/thermal/rockchip_thermal.c
723
writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
drivers/thermal/rockchip_thermal.c
725
writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
drivers/thermal/rockchip_thermal.c
727
writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
drivers/thermal/rockchip_thermal.c
757
writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs +
drivers/thermal/rockchip_thermal.c
760
writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
drivers/thermal/rockchip_thermal.c
762
writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
drivers/thermal/rockchip_thermal.c
764
writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
drivers/thermal/rockchip_thermal.c
766
writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
drivers/thermal/rockchip_thermal.c
779
writel_relaxed(TSADCV3_AUTO_PERIOD_TIME,
drivers/thermal/rockchip_thermal.c
781
writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
drivers/thermal/rockchip_thermal.c
783
writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME,
drivers/thermal/rockchip_thermal.c
785
writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
drivers/thermal/rockchip_thermal.c
790
writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
drivers/thermal/rockchip_thermal.c
793
writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
drivers/thermal/rockchip_thermal.c
807
writel_relaxed(TSADCV5_USER_INTER_PD_SOC, regs + TSADCV2_USER_CON);
drivers/thermal/rockchip_thermal.c
808
writel_relaxed(TSADCV5_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
drivers/thermal/rockchip_thermal.c
809
writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
drivers/thermal/rockchip_thermal.c
811
writel_relaxed(TSADCV5_AUTO_PERIOD_HT_TIME,
drivers/thermal/rockchip_thermal.c
813
writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
drivers/thermal/rockchip_thermal.c
817
writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
drivers/thermal/rockchip_thermal.c
820
writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
drivers/thermal/rockchip_thermal.c
850
writel_relaxed(TSADCV6_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
drivers/thermal/rockchip_thermal.c
851
writel_relaxed(TSADCV6_AUTO_PERIOD_HT_TIME,
drivers/thermal/rockchip_thermal.c
853
writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
drivers/thermal/rockchip_thermal.c
855
writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
drivers/thermal/rockchip_thermal.c
858
writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
drivers/thermal/rockchip_thermal.c
862
writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
drivers/thermal/rockchip_thermal.c
871
writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
drivers/thermal/rockchip_thermal.c
879
writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
drivers/thermal/rockchip_thermal.c
887
writel_relaxed(val & TSADCV4_INT_PD_CLEAR_MASK, regs + TSADCV3_INT_PD);
drivers/thermal/rockchip_thermal.c
889
writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK,
drivers/thermal/rockchip_thermal.c
903
writel_relaxed(val, regs + TSADCV2_AUTO_CON);
drivers/thermal/rockchip_thermal.c
925
writel_relaxed(val, regs + TSADCV2_AUTO_CON);
drivers/thermal/rockchip_thermal.c
937
writel_relaxed(val, regs + TSADCV2_AUTO_CON);
drivers/thermal/rockchip_thermal.c
975
writel_relaxed(int_clr, regs + TSADCV2_INT_EN);
drivers/thermal/rockchip_thermal.c
984
writel_relaxed(alarm_value & table->data_mask,
drivers/thermal/rockchip_thermal.c
989
writel_relaxed(int_en, regs + TSADCV2_INT_EN);
drivers/thermal/spear_thermal.c
123
writel_relaxed(stdev->flags, stdev->thermal_base);
drivers/thermal/spear_thermal.c
163
writel_relaxed(actual_mask & ~stdev->flags, stdev->thermal_base);
drivers/thermal/spear_thermal.c
56
writel_relaxed(actual_mask & ~stdev->flags, stdev->thermal_base);
drivers/thermal/spear_thermal.c
79
writel_relaxed(actual_mask | stdev->flags, stdev->thermal_base);
drivers/thermal/st/stm_thermal.c
117
writel_relaxed(value, sensor->base + DTS_ITENR_OFFSET);
drivers/thermal/st/stm_thermal.c
134
writel_relaxed(ICIFR_MASK, sensor->base + DTS_ICIFR_OFFSET);
drivers/thermal/st/stm_thermal.c
147
writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET);
drivers/thermal/st/stm_thermal.c
164
writel_relaxed(value, sensor->base +
drivers/thermal/st/stm_thermal.c
181
writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET);
drivers/thermal/st/stm_thermal.c
189
writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET);
drivers/thermal/st/stm_thermal.c
235
writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET);
drivers/thermal/st/stm_thermal.c
297
writel_relaxed(value, sensor->base + DTS_ITENR_OFFSET);
drivers/thermal/st/stm_thermal.c
344
writel_relaxed(itr1, sensor->base + DTS_ITR1_OFFSET);
drivers/thermal/st/stm_thermal.c
520
writel_relaxed(ICIFR_MASK, sensor->base + DTS_ICIFR_OFFSET);
drivers/thermal/tegra/tegra30-tsensor.c
128
writel_relaxed(val, ts->regs + 0x40 + TSENSOR_SENSOR0_CONFIG0);
drivers/thermal/tegra/tegra30-tsensor.c
129
writel_relaxed(val, ts->regs + 0x80 + TSENSOR_SENSOR0_CONFIG0);
drivers/thermal/tegra/tegra30-tsensor.c
237
writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1);
drivers/thermal/tegra/tegra30-tsensor.c
255
writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_STATUS0);
drivers/thermal/tegra/tegra30-tsensor.c
301
writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
drivers/thermal/tegra/tegra30-tsensor.c
360
writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
drivers/thermal/tegra/tegra30-tsensor.c
377
writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1);
drivers/thermal/tegra/tegra30-tsensor.c
383
writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG2);
drivers/thermal/tegra/tegra30-tsensor.c
407
writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
drivers/tty/serial/amba-pl011.c
310
writel_relaxed(val, addr);
drivers/tty/serial/imx_earlycon.c
24
writel_relaxed(ch, port->membase + URTX0);
drivers/tty/serial/ma35d1_serial.c
175
writel_relaxed(value, p->port.membase + offset);
drivers/tty/serial/mps2-uart.c
101
writel_relaxed(val, mps_port->port.membase + off);
drivers/tty/serial/msm_serial.c
198
writel_relaxed(val, port->membase + off);
drivers/tty/serial/mxs-auart.c
492
writel_relaxed(val, addr);
drivers/tty/serial/mxs-auart.c
500
writel_relaxed(val, addr + SET_REG);
drivers/tty/serial/mxs-auart.c
508
writel_relaxed(val, addr + CLR_REG);
drivers/tty/serial/samsung_tty.c
191
writel_relaxed(val, portaddr(port, reg));
drivers/tty/serial/samsung_tty.c
198
#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
drivers/tty/serial/sifive.c
193
writel_relaxed(v, port->membase + offs);
drivers/tty/serial/sprd_serial.c
168
writel_relaxed(value, port->membase + offset);
drivers/tty/serial/st-asc.c
162
#ifdef writel_relaxed
drivers/tty/serial/st-asc.c
163
writel_relaxed(value, port->membase + offset);
drivers/tty/serial/stm32-usart.c
1079
writel_relaxed(val, port->membase + ofs->cr2);
drivers/tty/serial/stm32-usart.c
1085
writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr);
drivers/tty/serial/stm32-usart.c
1141
writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
drivers/tty/serial/stm32-usart.c
1185
writel_relaxed(0, port->membase + ofs->cr1);
drivers/tty/serial/stm32-usart.c
1189
writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
drivers/tty/serial/stm32-usart.c
1252
writel_relaxed(bits, port->membase + ofs->rtor);
drivers/tty/serial/stm32-usart.c
126
writel_relaxed(val, port->membase + reg);
drivers/tty/serial/stm32-usart.c
1300
writel_relaxed(presc, port->membase + ofs->presc);
drivers/tty/serial/stm32-usart.c
1314
writel_relaxed(brr, port->membase + ofs->brr);
drivers/tty/serial/stm32-usart.c
135
writel_relaxed(val, port->membase + reg);
drivers/tty/serial/stm32-usart.c
1380
writel_relaxed(cr3, port->membase + ofs->cr3);
drivers/tty/serial/stm32-usart.c
1381
writel_relaxed(cr2, port->membase + ofs->cr2);
drivers/tty/serial/stm32-usart.c
1382
writel_relaxed(cr1, port->membase + ofs->cr1);
drivers/tty/serial/stm32-usart.c
1898
writel_relaxed(cr3, port->membase + ofs->cr3);
drivers/tty/serial/stm32-usart.c
1922
writel_relaxed(ch, port->membase + ofs->tdr);
drivers/tty/serial/stm32-usart.c
1946
writel_relaxed(new_cr1, port->membase + ofs->cr1);
drivers/tty/serial/stm32-usart.c
1951
writel_relaxed(old_cr1, port->membase + ofs->cr1);
drivers/tty/serial/stm32-usart.c
2009
writel_relaxed(ch, port->membase + info->ofs.tdr);
drivers/tty/serial/stm32-usart.c
255
writel_relaxed(cr3, port->membase + ofs->cr3);
drivers/tty/serial/stm32-usart.c
256
writel_relaxed(cr1, port->membase + ofs->cr1);
drivers/tty/serial/stm32-usart.c
405
writel_relaxed(sr & USART_SR_ERR_MASK,
drivers/tty/serial/stm32-usart.c
711
writel_relaxed(ch, port->membase + ofs->tdr);
drivers/tty/serial/stm32-usart.c
808
writel_relaxed(port->x_char, port->membase + ofs->tdr);
drivers/tty/serial/stm32-usart.c
825
writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
drivers/tty/serial/stm32-usart.c
865
writel_relaxed(USART_ICR_RTOCF,
drivers/tty/serial/stm32-usart.c
872
writel_relaxed(USART_ICR_WUCF,
drivers/tty/serial/tegra-utc.c
85
writel_relaxed(val, addr);
drivers/tty/serial/tegra-utc.c
99
writel_relaxed(val, addr);
drivers/ufs/host/ufs-qcom.c
877
writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
drivers/usb/chipidea/ci_hdrc_msm.c
166
writel_relaxed(val, ci->base + HS_PHY_SEC_CTRL);
drivers/usb/chipidea/ci_hdrc_msm.c
93
writel_relaxed(val, msm_ci->base + HS_PHY_SEC_CTRL);
drivers/usb/dwc3/dwc3-st.c
106
writel_relaxed(value, base + offset);
drivers/usb/gadget/udc/atmel_usba_udc.h
191
writel_relaxed((value), (udc)->regs + USBA_##reg)
drivers/usb/gadget/udc/atmel_usba_udc.h
195
writel_relaxed((value), (ep)->ep_regs + USBA_EPT_##reg)
drivers/usb/gadget/udc/atmel_usba_udc.h
199
writel_relaxed((value), (ep)->dma_regs + USBA_DMA_##reg)
drivers/usb/host/ehci-orion.c
24
#define wrl(off, val) writel_relaxed((val), hcd->regs + (off))
drivers/usb/host/ohci-sa1111.c
135
writel_relaxed(usb_rst | USB_RESET_FORCEIFRESET | USB_RESET_FORCEHCRESET,
drivers/usb/host/ohci-sa1111.c
145
writel_relaxed(usb_rst, dev->mapbase + USB_RESET);
drivers/usb/host/ohci-sa1111.c
161
writel_relaxed(usb_rst | USB_RESET_FORCEIFRESET | USB_RESET_FORCEHCRESET,
drivers/usb/isp1760/isp1760-hcd.c
425
writel_relaxed(*src, dst);
drivers/usb/isp1760/isp1760-hcd.c
446
writel_relaxed(*src, dst);
drivers/usb/phy/phy-mxs-usb.c
405
writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
drivers/usb/phy/phy-mxs-usb.c
423
writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
drivers/usb/phy/phy-mxs-usb.c
580
writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET);
drivers/usb/phy/phy-mxs-usb.c
582
writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR);
drivers/usb/phy/phy-mxs-usb.c
741
writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
drivers/usb/phy/phy-mxs-usb.c
751
writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
drivers/usb/phy/phy-tegra-usb.c
1002
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
1008
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
1111
writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
drivers/usb/phy/phy-tegra-usb.c
1129
writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
drivers/usb/phy/phy-tegra-usb.c
1151
writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
drivers/usb/phy/phy-tegra-usb.c
297
writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
drivers/usb/phy/phy-tegra-usb.c
303
writel_relaxed(val, base + TEGRA_USB_PORTSC1);
drivers/usb/phy/phy-tegra-usb.c
318
writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
drivers/usb/phy/phy-tegra-usb.c
325
writel_relaxed(val, base + TEGRA_USB_PORTSC1);
drivers/usb/phy/phy-tegra-usb.c
419
writel_relaxed(val, base + UTMIP_BIAS_CFG0);
drivers/usb/phy/phy-tegra-usb.c
466
writel_relaxed(val, base + UTMIP_BIAS_CFG0);
drivers/usb/phy/phy-tegra-usb.c
500
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
506
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
533
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
539
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
559
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
564
writel_relaxed(val, base + USB1_LEGACY_CTRL);
drivers/usb/phy/phy-tegra-usb.c
569
writel_relaxed(val, base + UTMIP_TX_CFG0);
drivers/usb/phy/phy-tegra-usb.c
575
writel_relaxed(val, base + UTMIP_HSRX_CFG0);
drivers/usb/phy/phy-tegra-usb.c
580
writel_relaxed(val, base + UTMIP_HSRX_CFG1);
drivers/usb/phy/phy-tegra-usb.c
585
writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0);
drivers/usb/phy/phy-tegra-usb.c
589
writel_relaxed(val, base + UTMIP_MISC_CFG0);
drivers/usb/phy/phy-tegra-usb.c
597
writel_relaxed(val, base + UTMIP_MISC_CFG1);
drivers/usb/phy/phy-tegra-usb.c
604
writel_relaxed(val, base + UTMIP_PLL_CFG1);
drivers/usb/phy/phy-tegra-usb.c
609
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
614
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
619
writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
drivers/usb/phy/phy-tegra-usb.c
624
writel_relaxed(val, base + USB_PHY_VBUS_SENSORS);
drivers/usb/phy/phy-tegra-usb.c
628
writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
drivers/usb/phy/phy-tegra-usb.c
632
writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
drivers/usb/phy/phy-tegra-usb.c
657
writel_relaxed(val, base + UTMIP_XCVR_CFG0);
drivers/usb/phy/phy-tegra-usb.c
663
writel_relaxed(val, base + UTMIP_XCVR_CFG1);
drivers/usb/phy/phy-tegra-usb.c
668
writel_relaxed(val, base + UTMIP_BIAS_CFG1);
drivers/usb/phy/phy-tegra-usb.c
675
writel_relaxed(val, base + UTMIP_SPARE_CFG0);
drivers/usb/phy/phy-tegra-usb.c
680
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
685
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
691
writel_relaxed(val, base + USB1_LEGACY_CTRL);
drivers/usb/phy/phy-tegra-usb.c
695
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
707
writel_relaxed(val, base + USB_USBMODE);
drivers/usb/phy/phy-tegra-usb.c
736
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
741
writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
drivers/usb/phy/phy-tegra-usb.c
747
writel_relaxed(val, base + UTMIP_XCVR_CFG0);
drivers/usb/phy/phy-tegra-usb.c
753
writel_relaxed(val, base + UTMIP_XCVR_CFG1);
drivers/usb/phy/phy-tegra-usb.c
760
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
770
writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
drivers/usb/phy/phy-tegra-usb.c
774
writel_relaxed(val, base + USB_PHY_VBUS_SENSORS);
drivers/usb/phy/phy-tegra-usb.c
801
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
805
writel_relaxed(val, base + ULPI_TIMING_CTRL_0);
drivers/usb/phy/phy-tegra-usb.c
809
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
812
writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
drivers/usb/phy/phy-tegra-usb.c
817
writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
drivers/usb/phy/phy-tegra-usb.c
823
writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
drivers/usb/phy/phy-tegra-usb.c
840
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
845
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
886
writel_relaxed(value, base + shift + reg);
drivers/usb/phy/phy-tegra-usb.c
906
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
912
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
946
writel_relaxed(val, base + USB_SUSP_CTRL);
drivers/usb/phy/phy-tegra-usb.c
957
writel_relaxed(val, base + USB_USBMODE);
drivers/usb/phy/phy-tegra-usb.c
965
writel_relaxed(val, base + USB_TXFILLTUNING);
drivers/usb/phy/phy-tegra-usb.c
971
writel_relaxed(val, base + phy->soc_config->portsc1_offset);
drivers/vfio/platform/reset/vfio_platform_bcmflexrm.c
40
writel_relaxed(0x0, ring + RING_CONTROL);
drivers/vfio/platform/reset/vfio_platform_bcmflexrm.c
44
writel_relaxed(BIT(CONTROL_FLUSH_SHIFT), ring + RING_CONTROL);
drivers/vfio/platform/reset/vfio_platform_bcmflexrm.c
56
writel_relaxed(0x0, ring + RING_CONTROL);
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
126
writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
139
writel_relaxed(win->pitch[0],
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
141
writel_relaxed(win->pitch[2] << 16 | win->pitch[1],
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
144
writel_relaxed((win->ysrc << 16) | win->xsrc,
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
146
writel_relaxed((win->ydst << 16) | win->xdst,
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
148
writel_relaxed(win->ypos << 16 | win->xpos,
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
151
writel_relaxed(win->pitch[0], (void __iomem *)®s->g_pitch);
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
153
writel_relaxed((win->ysrc << 16) | win->xsrc,
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
155
writel_relaxed((win->ydst << 16) | win->xdst,
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
157
writel_relaxed(win->ypos << 16 | win->xpos,
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
190
writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
243
writel_relaxed(addr->phys[0], (void __iomem *)®s->v_y0);
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
244
writel_relaxed(addr->phys[1], (void __iomem *)®s->v_u0);
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
245
writel_relaxed(addr->phys[2], (void __iomem *)®s->v_v0);
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
247
writel_relaxed(addr->phys[0], (void __iomem *)®s->g_0);
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
270
writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id));
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
276
writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id));
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
278
writel_relaxed((mode->yres << 16) | mode->xres,
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
280
writel_relaxed((mode->left_margin << 16) | mode->right_margin,
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
282
writel_relaxed((mode->upper_margin << 16) | mode->lower_margin,
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
288
writel_relaxed((total_y << 16) | total_x,
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
297
writel_relaxed(vsync_ctrl, (void __iomem *)®s->vsync_ctrl);
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
311
writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
333
writel_relaxed(tmp, ctrl->reg_base + LCD_TOP_CTRL);
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
342
writel_relaxed(tmp, ctrl->reg_base + SPU_IRQ_ENA);
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
358
writel_relaxed(tmp, ctrl_regs(path) + SPU_IOPAD_CONTROL);
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
365
writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
375
writel_relaxed(dma_ctrl1, ctrl_regs(path) + dma_ctrl(1, path->id));
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
378
writel_relaxed(0x00000000, (void __iomem *)®s->blank_color);
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
379
writel_relaxed(0x00000000, (void __iomem *)®s->g_1);
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
380
writel_relaxed(0x00000000, (void __iomem *)®s->g_start);
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
392
writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
42
writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR);
drivers/video/fbdev/mmp/hw/mmp_spi.c
100
writel_relaxed(IOPAD_DUMB18SPI |
drivers/video/fbdev/mmp/hw/mmp_spi.c
38
writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR);
drivers/video/fbdev/mmp/hw/mmp_spi.c
42
writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA);
drivers/video/fbdev/mmp/hw/mmp_spi.c
45
writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA);
drivers/video/fbdev/mmp/hw/mmp_spi.c
48
writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA);
drivers/video/fbdev/mmp/hw/mmp_spi.c
74
writel_relaxed(tmp, reg_base + LCD_SPU_SPI_CTRL);
drivers/video/fbdev/mmp/hw/mmp_spi.c
76
writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
257
writel_relaxed(l, base + PLL_CONFIGURATION1);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
266
writel_relaxed(l, base + PLL_CONFIGURATION3);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
291
writel_relaxed(l, base + PLL_CONFIGURATION2);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
293
writel_relaxed(1, base + PLL_GO); /* PLL_GO */
drivers/video/fbdev/omap2/omapfb/dss/pll.c
314
writel_relaxed(l, base + PLL_CONFIGURATION2);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
340
writel_relaxed(l, base + PLL_CONFIGURATION1);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
354
writel_relaxed(l, base + PLL_CONFIGURATION2);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
358
writel_relaxed(l, base + PLL_CONFIGURATION3);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
363
writel_relaxed(l, base + PLL_CONFIGURATION4);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
365
writel_relaxed(1, base + PLL_GO); /* PLL_GO */
drivers/video/fbdev/omap2/omapfb/dss/video-pll.c
28
writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg)
drivers/video/fbdev/sa1100fb.c
794
writel_relaxed(fbi->reg_lccr3, fbi->base + LCCR3);
drivers/video/fbdev/sa1100fb.c
795
writel_relaxed(fbi->reg_lccr2, fbi->base + LCCR2);
drivers/video/fbdev/sa1100fb.c
796
writel_relaxed(fbi->reg_lccr1, fbi->base + LCCR1);
drivers/video/fbdev/sa1100fb.c
797
writel_relaxed(fbi->reg_lccr0 & ~LCCR0_LEN, fbi->base + LCCR0);
drivers/video/fbdev/sa1100fb.c
798
writel_relaxed(fbi->dbar1, fbi->base + DBAR1);
drivers/video/fbdev/sa1100fb.c
799
writel_relaxed(fbi->dbar2, fbi->base + DBAR2);
drivers/video/fbdev/sa1100fb.c
800
writel_relaxed(fbi->reg_lccr0 | LCCR0_LEN, fbi->base + LCCR0);
drivers/video/fbdev/sa1100fb.c
827
writel_relaxed(~0, fbi->base + LCSR);
drivers/video/fbdev/sa1100fb.c
831
writel_relaxed(lccr0, fbi->base + LCCR0);
drivers/video/fbdev/sa1100fb.c
833
writel_relaxed(lccr0, fbi->base + LCCR0);
drivers/video/fbdev/sa1100fb.c
852
writel_relaxed(lccr0, fbi->base + LCCR0);
drivers/video/fbdev/sa1100fb.c
856
writel_relaxed(lcsr, fbi->base + LCSR);
drivers/watchdog/apple_wdt.c
100
writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
drivers/watchdog/apple_wdt.c
103
writel_relaxed(wdt->clk_rate * actual, wdt->regs + APPLE_WDT_WD1_BITE_TIME);
drivers/watchdog/apple_wdt.c
126
writel_relaxed(APPLE_WDT_CTRL_RESET_EN, wdt->regs + APPLE_WDT_WD1_CTRL);
drivers/watchdog/apple_wdt.c
127
writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_BITE_TIME);
drivers/watchdog/apple_wdt.c
128
writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
drivers/watchdog/apple_wdt.c
71
writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
drivers/watchdog/apple_wdt.c
72
writel_relaxed(APPLE_WDT_CTRL_RESET_EN, wdt->regs + APPLE_WDT_WD1_CTRL);
drivers/watchdog/apple_wdt.c
81
writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CTRL);
drivers/watchdog/apple_wdt.c
90
writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
drivers/watchdog/at91sam9_wdt.c
43
writel_relaxed((val), (wdt)->base + (field))
drivers/watchdog/bcm2835_wdt.c
106
writel_relaxed(10 | PM_PASSWORD, wdt->base + PM_WDOG);
drivers/watchdog/bcm2835_wdt.c
110
writel_relaxed(val, wdt->base + PM_RSTC);
drivers/watchdog/bcm2835_wdt.c
165
writel_relaxed(val, wdt->base + PM_RSTS);
drivers/watchdog/bcm2835_wdt.c
74
writel_relaxed(PM_PASSWORD | (SECS_TO_WDOG_TICKS(wdog->timeout) &
drivers/watchdog/bcm2835_wdt.c
77
writel_relaxed(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) |
drivers/watchdog/bcm2835_wdt.c
89
writel_relaxed(PM_PASSWORD | PM_RSTC_RESET, wdt->base + PM_RSTC);
drivers/watchdog/bcm7038_wdt.c
46
writel_relaxed(value, addr);
drivers/watchdog/bcm_kona_wdt.c
182
writel_relaxed(val, wdt->base + SECWDOG_CTRL_REG);
drivers/watchdog/cadence_wdt.c
87
writel_relaxed(val, wdt->regs + offset);
drivers/watchdog/digicolor_wdt.c
40
writel_relaxed(0, wdt->base + TIMER_A_CONTROL);
drivers/watchdog/digicolor_wdt.c
41
writel_relaxed(ticks, wdt->base + TIMER_A_COUNT);
drivers/watchdog/digicolor_wdt.c
42
writel_relaxed(TIMER_A_ENABLE_COUNT | TIMER_A_ENABLE_WATCHDOG,
drivers/watchdog/digicolor_wdt.c
73
writel_relaxed(0, wdt->base + TIMER_A_CONTROL);
drivers/watchdog/imx7ulp_wdt.c
256
writel_relaxed(UNLOCK_SEQ0, wdt->base + WDOG_CNT);
drivers/watchdog/imx7ulp_wdt.c
257
writel_relaxed(UNLOCK_SEQ1, wdt->base + WDOG_CNT);
drivers/watchdog/omap_wdt.c
107
writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
drivers/watchdog/omap_wdt.c
111
writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
drivers/watchdog/omap_wdt.c
126
writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
drivers/watchdog/omap_wdt.c
153
writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
drivers/watchdog/omap_wdt.c
80
writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
drivers/watchdog/omap_wdt.c
93
writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
drivers/watchdog/omap_wdt.c
97
writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
drivers/watchdog/renesas_wdt.c
64
writel_relaxed(val, priv->base + reg);
drivers/watchdog/rtd119x_wdt.c
125
writel_relaxed(RTD119X_TCWTR_WDCLR, data->base + RTD119X_TCWTR);
drivers/watchdog/rtd119x_wdt.c
63
writel_relaxed(RTD119X_TCWTR_WDCLR, data->base + RTD119X_TCWTR);
drivers/watchdog/rti_wdt.c
105
writel_relaxed(RTIWWDRX_NMI, wdt->base + RTIWWDRXCTRL);
drivers/watchdog/rti_wdt.c
108
writel_relaxed(RTIWWDSIZE_50P, wdt->base + RTIWWDSIZECTRL);
drivers/watchdog/rti_wdt.c
113
writel_relaxed(WDENABLE_KEY, wdt->base + RTIDWDCTRL);
drivers/watchdog/rti_wdt.c
122
writel_relaxed(WDKEY_SEQ0, wdt->base + RTIWDKEY);
drivers/watchdog/rti_wdt.c
124
writel_relaxed(WDKEY_SEQ1, wdt->base + RTIWDKEY);
drivers/watchdog/rti_wdt.c
93
writel_relaxed(timer_margin, wdt->base + RTIDWDPRLD);
drivers/watchdog/rzg2l_wdt.c
80
writel_relaxed(val, priv->base + reg);
drivers/watchdog/sa1100_wdt.c
63
writel_relaxed(val, reg_base + offset);
drivers/watchdog/sama5d4_wdt.c
100
writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IDR);
drivers/watchdog/sama5d4_wdt.c
68
writel_relaxed(val, wdt->reg_base + field);
drivers/watchdog/sama5d4_wdt.c
76
writel_relaxed(val, wdt->reg_base + field);
drivers/watchdog/sama5d4_wdt.c
85
writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IER);
drivers/watchdog/sp805_wdt.c
141
writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
drivers/watchdog/sp805_wdt.c
142
writel_relaxed(0, wdt->base + WDTCONTROL);
drivers/watchdog/sp805_wdt.c
143
writel_relaxed(0, wdt->base + WDTLOAD);
drivers/watchdog/sp805_wdt.c
144
writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL);
drivers/watchdog/sp805_wdt.c
168
writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
drivers/watchdog/sp805_wdt.c
169
writel_relaxed(wdt->load_val, wdt->base + WDTLOAD);
drivers/watchdog/sp805_wdt.c
170
writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
drivers/watchdog/sp805_wdt.c
173
writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base +
drivers/watchdog/sp805_wdt.c
176
writel_relaxed(LOCK, wdt->base + WDTLOCK);
drivers/watchdog/sp805_wdt.c
203
writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
drivers/watchdog/sp805_wdt.c
204
writel_relaxed(0, wdt->base + WDTCONTROL);
drivers/watchdog/sp805_wdt.c
205
writel_relaxed(LOCK, wdt->base + WDTLOCK);
drivers/watchdog/sprd_wdt.c
130
writel_relaxed((tmr_step >> SPRD_WDT_CNT_HIGH_SHIFT) &
drivers/watchdog/sprd_wdt.c
132
writel_relaxed((tmr_step & SPRD_WDT_LOW_VALUE_MASK),
drivers/watchdog/sprd_wdt.c
134
writel_relaxed((prtmr_step >> SPRD_WDT_CNT_HIGH_SHIFT) &
drivers/watchdog/sprd_wdt.c
137
writel_relaxed(prtmr_step & SPRD_WDT_LOW_VALUE_MASK,
drivers/watchdog/sprd_wdt.c
161
writel_relaxed(val, wdt->base + SPRD_WDT_CTRL);
drivers/watchdog/sprd_wdt.c
171
writel_relaxed(0x0, wdt->base + SPRD_WDT_CTRL);
drivers/watchdog/sprd_wdt.c
191
writel_relaxed(val, wdt->base + SPRD_WDT_CTRL);
drivers/watchdog/sprd_wdt.c
207
writel_relaxed(val, wdt->base + SPRD_WDT_CTRL);
drivers/watchdog/sprd_wdt.c
74
writel_relaxed(0x0, addr + SPRD_WDT_LOCK);
drivers/watchdog/sprd_wdt.c
79
writel_relaxed(SPRD_WDT_UNLOCK_KEY, addr + SPRD_WDT_LOCK);
drivers/watchdog/sprd_wdt.c
87
writel_relaxed(SPRD_WDT_INT_CLEAR_BIT, wdt->base + SPRD_WDT_INT_CLR);
drivers/watchdog/st_lpc_wdt.c
101
writel_relaxed(0, st_wdog->base + LPC_WDT_OFF);
drivers/watchdog/st_lpc_wdt.c
84
writel_relaxed(timeout * clkrate, st_wdog->base + LPC_LPA_LSB_OFF);
drivers/watchdog/st_lpc_wdt.c
85
writel_relaxed(1, st_wdog->base + LPC_LPA_START_OFF);
drivers/watchdog/st_lpc_wdt.c
92
writel_relaxed(1, st_wdog->base + LPC_WDT_OFF);
drivers/watchdog/stm32_iwdg.c
94
writel_relaxed(val, base + reg);
include/asm-generic/io.h
405
#ifndef writel_relaxed
include/asm-generic/io.h
406
#define writel_relaxed writel_relaxed
include/linux/coresight.h
503
writel_relaxed((u32)val, csa->base + lo_offset);
include/linux/coresight.h
504
writel_relaxed((u32)(val >> 32), csa->base + hi_offset);
include/linux/coresight.h
523
writel_relaxed(val, csa->base + offset);
include/linux/io-64-nonatomic-hi-lo.h
38
writel_relaxed(val >> 32, addr + 4);
include/linux/io-64-nonatomic-hi-lo.h
39
writel_relaxed(val, addr);
include/linux/io-64-nonatomic-lo-hi.h
38
writel_relaxed(val, addr);
include/linux/io-64-nonatomic-lo-hi.h
39
writel_relaxed(val >> 32, addr + 4);
include/linux/soc/qcom/geni-se.h
382
writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG);
include/linux/soc/qcom/geni-se.h
395
writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG);
include/linux/soc/qcom/geni-se.h
407
writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG);
include/linux/soc/qcom/geni-se.h
420
writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG);
include/ufs/ufshcd.h
1271
writel_relaxed((val), (hba)->mcq_base + (reg))
rust/helpers/io.c
100
writel_relaxed(value, addr);
sound/soc/apple/mca.c
173
writel_relaxed(newval, ptr);
sound/soc/apple/mca.c
287
writel_relaxed(cl->no + 1, cl->base + REG_SYNCGEN_MCLK_SEL);
sound/soc/apple/mca.c
441
writel_relaxed(0xffffffff,
sound/soc/apple/mca.c
443
writel_relaxed(~((u32)mca_crop_mask(mask, nchans)),
sound/soc/apple/mca.c
445
writel_relaxed(0xffffffff,
sound/soc/apple/mca.c
447
writel_relaxed(~((u32)mask),
sound/soc/apple/mca.c
450
writel_relaxed(0xffffffff,
sound/soc/apple/mca.c
452
writel_relaxed(~((u32)mca_crop_mask(mask, nchans)),
sound/soc/apple/mca.c
454
writel_relaxed(1 << port,
sound/soc/apple/mca.c
548
writel_relaxed(bitstart,
sound/soc/apple/mca.c
550
writel_relaxed(bitstart,
sound/soc/apple/mca.c
672
writel_relaxed(regval, mca->switch_base + REG_DMA_ADAPTER_A(cl->no));
sound/soc/apple/mca.c
675
writel_relaxed(regval,
sound/soc/apple/mca.c
678
writel_relaxed(regval,
sound/soc/apple/mca.c
686
writel_relaxed((bclk_ratio / 2) - 1,
sound/soc/apple/mca.c
688
writel_relaxed(((bclk_ratio + 1) / 2) - 1,
sound/soc/apple/mca.c
690
writel_relaxed(FIELD_PREP(MCLK_CONF_DIV, 0x1),
sound/soc/apple/mca.c
762
writel_relaxed(PORT_ENABLES_CLOCKS | PORT_ENABLES_TX_DATA,
sound/soc/apple/mca.c
764
writel_relaxed(FIELD_PREP(PORT_CLOCK_SEL, fe_cl->no + 1),
sound/soc/apple/mca.c
766
writel_relaxed(PORT_DATA_SEL_TXA(fe_cl->no),
sound/soc/apple/mca.c
789
writel_relaxed(0, cl->base + REG_PORT_ENABLES);
sound/soc/apple/mca.c
790
writel_relaxed(0, cl->base + REG_PORT_DATA_SEL);
sound/soc/fsl/fsl_xcvr.c
1427
writel_relaxed(0, reg_ctrl);
sound/soc/sprd/sprd-mcdt.c
125
writel_relaxed(tmp, mcdt->base + reg);
sound/soc/sprd/sprd-mcdt.c
187
writel_relaxed(val, mcdt->base + reg);
sound/soc/starfive/jh7110_tdm.c
144
writel_relaxed(val, tdm->tdm_base + reg);
sound/soc/sti/uniperif.h
1031
writel_relaxed(value, ip->base + UNIPERIF_STATUS_1_OFFSET(ip))
sound/soc/sti/uniperif.h
105
writel_relaxed(value, ip->base + UNIPERIF_CHANNEL_STA_REG5_OFFSET(ip))
sound/soc/sti/uniperif.h
1056
writel_relaxed(value, ip->base + \
sound/soc/sti/uniperif.h
1067
writel_relaxed(value, ip->base + UNIPERIF_USER_VALIDITY_OFFSET(ip))
sound/soc/sti/uniperif.h
1110
writel_relaxed(value, ip->base + UNIPERIF_TDM_ENABLE_OFFSET(ip))
sound/soc/sti/uniperif.h
1138
writel_relaxed(value, ip->base + \
sound/soc/sti/uniperif.h
1185
writel_relaxed(value, ip->base + \
sound/soc/sti/uniperif.h
1213
writel_relaxed(value, ip->base + \
sound/soc/sti/uniperif.h
160
writel_relaxed(value, ip->base + UNIPERIF_ITS_BCLR_OFFSET(ip))
sound/soc/sti/uniperif.h
196
writel_relaxed(value, ip->base + UNIPERIF_ITM_BCLR_OFFSET(ip))
sound/soc/sti/uniperif.h
22
writel_relaxed(((readl_relaxed(ip->base + offset) & \
sound/soc/sti/uniperif.h
221
writel_relaxed(value, ip->base + UNIPERIF_ITM_BSET_OFFSET(ip))
sound/soc/sti/uniperif.h
25
writel_relaxed((((value) & mask) << shift), ip->base + offset)
sound/soc/sti/uniperif.h
276
writel_relaxed(value, ip->base + UNIPERIF_CONFIG_OFFSET(ip))
sound/soc/sti/uniperif.h
36
writel_relaxed(value, ip->base + UNIPERIF_SOFT_RST_OFFSET(ip))
sound/soc/sti/uniperif.h
548
writel_relaxed(value, ip->base + UNIPERIF_CTRL_OFFSET(ip))
sound/soc/sti/uniperif.h
58
writel_relaxed(value, ip->base + UNIPERIF_FIFO_DATA_OFFSET(ip))
sound/soc/sti/uniperif.h
68
writel_relaxed(value, ip->base + \
sound/soc/sti/uniperif.h
75
writel_relaxed(value, ip->base + UNIPERIF_CHANNEL_STA_REG0_OFFSET(ip))
sound/soc/sti/uniperif.h
794
writel_relaxed(value, ip->base + UNIPERIF_I2S_FMT_OFFSET(ip))
sound/soc/sti/uniperif.h
81
writel_relaxed(value, ip->base + UNIPERIF_CHANNEL_STA_REG1_OFFSET(ip))
sound/soc/sti/uniperif.h
87
writel_relaxed(value, ip->base + UNIPERIF_CHANNEL_STA_REG2_OFFSET(ip))
sound/soc/sti/uniperif.h
93
writel_relaxed(value, ip->base + UNIPERIF_CHANNEL_STA_REG3_OFFSET(ip))
sound/soc/sti/uniperif.h
99
writel_relaxed(value, ip->base + UNIPERIF_CHANNEL_STA_REG4_OFFSET(ip))
sound/soc/sti/uniperif.h
993
writel_relaxed(value, ip->base + UNIPERIF_BIT_CONTROL_OFFSET(ip))
sound/soc/stm/stm32_sai.c
123
writel_relaxed(FIELD_PREP(SAI_GCR_SYNCOUT_MASK, synco), sai->base);
sound/soc/stm/stm32_sai.c
290
writel_relaxed(sai->gcr, sai->base);
sound/soc/stm/stm32_sai.c
93
writel_relaxed(FIELD_PREP(SAI_GCR_SYNCIN_MASK, (synci - 1)), sai->base);
sound/soc/ti/omap-dmic.c
53
writel_relaxed(val, dmic->io_base + reg);
sound/soc/ti/omap-mcbsp-priv.h
291
writel_relaxed(val, addr);
sound/soc/ti/omap-mcbsp-st.c
66
writel_relaxed(val, mcbsp->st_data->io_base_st + reg);
sound/soc/ti/omap-mcpdm.c
69
writel_relaxed(val, mcpdm->io_base + reg);
tools/include/asm-generic/io.h
334
#ifndef writel_relaxed
tools/include/asm-generic/io.h
335
#define writel_relaxed writel_relaxed
tools/testing/selftests/kvm/include/arm64/processor.h
246
#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c));})
tools/testing/selftests/kvm/lib/arm64/gic_v3.c
448
writel_relaxed(ctlr, rdist_base + GICR_CTLR);
tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c
37
writel_relaxed(val, GITS_BASE_GVA + offset);
