/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
 */

#ifndef _CORESIGHT_PRIV_H
#define _CORESIGHT_PRIV_H

#include <linux/amba/bus.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/coresight.h>
#include <linux/pm_runtime.h>

extern struct mutex coresight_mutex;
extern const struct device_type coresight_dev_type[];

/*
 * Coresight management registers (0xf00-0xfcc)
 * 0xfa0 - 0xfa4: Management    registers in PFTv1.0
 *                Trace         registers in PFTv1.1
 */
#define CORESIGHT_ITCTRL        0xf00
#define CORESIGHT_CLAIMSET      0xfa0
#define CORESIGHT_CLAIMCLR      0xfa4
#define CORESIGHT_LAR           0xfb0
#define CORESIGHT_LSR           0xfb4
#define CORESIGHT_DEVARCH       0xfbc
#define CORESIGHT_AUTHSTATUS    0xfb8
#define CORESIGHT_DEVID         0xfc8
#define CORESIGHT_DEVTYPE       0xfcc


/*
 * Coresight device CLAIM protocol.
 * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.
 */
#define CORESIGHT_CLAIM_MASK            GENMASK(1, 0)
#define CORESIGHT_CLAIM_FREE            0
#define CORESIGHT_CLAIM_EXTERNAL        1
#define CORESIGHT_CLAIM_SELF_HOSTED     2
#define CORESIGHT_CLAIM_INVALID         3

#define TIMEOUT_US              100
#define BMVAL(val, lsb, msb)    ((val & GENMASK(msb, lsb)) >> lsb)

#define ETM_MODE_EXCL_KERN      BIT(30)
#define ETM_MODE_EXCL_USER      BIT(31)
#define ETM_MODE_EXCL_HOST      BIT(32)
#define ETM_MODE_EXCL_GUEST     BIT(33)

struct cs_pair_attribute {
        struct device_attribute attr;
        u32 lo_off;
        u32 hi_off;
};

struct cs_off_attribute {
        struct device_attribute attr;
        u32 off;
};

ssize_t coresight_simple_show32(struct device *_dev, struct device_attribute *attr, char *buf);
ssize_t coresight_simple_show_pair(struct device *_dev, struct device_attribute *attr, char *buf);

#define coresight_simple_reg32(name, offset)                            \
        (&((struct cs_off_attribute[]) {                                \
           {                                                            \
                __ATTR(name, 0444, coresight_simple_show32, NULL),      \
                offset                                                  \
           }                                                            \
        })[0].attr.attr)

#define coresight_simple_reg64(name, lo_off, hi_off)                    \
        (&((struct cs_pair_attribute[]) {                               \
           {                                                            \
                __ATTR(name, 0444, coresight_simple_show_pair, NULL),   \
                lo_off, hi_off                                          \
           }                                                            \
        })[0].attr.attr)

extern const u32 coresight_barrier_pkt[4];
#define CORESIGHT_BARRIER_PKT_SIZE (sizeof(coresight_barrier_pkt))

enum etm_addr_type {
        ETM_ADDR_TYPE_NONE,
        ETM_ADDR_TYPE_SINGLE,
        ETM_ADDR_TYPE_RANGE,
        ETM_ADDR_TYPE_START,
        ETM_ADDR_TYPE_STOP,
};

/**
 * struct cs_buffer - keep track of a recording session' specifics
 * @cur:        index of the current buffer
 * @nr_pages:   max number of pages granted to us
 * @pid:        PID this cs_buffer belongs to
 * @offset:     offset within the current buffer
 * @data_size:  how much we collected in this run
 * @snapshot:   is this run in snapshot mode
 * @data_pages: a handle the ring buffer
 */
struct cs_buffers {
        unsigned int            cur;
        unsigned int            nr_pages;
        pid_t                   pid;
        unsigned long           offset;
        local_t                 data_size;
        bool                    snapshot;
        void                    **data_pages;
};

static inline void coresight_insert_barrier_packet(void *buf)
{
        if (buf)
                memcpy(buf, coresight_barrier_pkt, CORESIGHT_BARRIER_PKT_SIZE);
}

static inline void CS_LOCK(void __iomem *addr)
{
        do {
                /* Wait for things to settle */
                mb();
                writel_relaxed(0x0, addr + CORESIGHT_LAR);
        } while (0);
}

static inline void CS_UNLOCK(void __iomem *addr)
{
        do {
                writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
                /* Make sure everyone has seen this */
                mb();
        } while (0);
}

void coresight_disable_path(struct coresight_path *path);
int coresight_enable_path(struct coresight_path *path, enum cs_mode mode);
struct coresight_device *coresight_get_sink(struct coresight_path *path);
struct coresight_device *coresight_get_sink_by_id(u32 id);
struct coresight_device *
coresight_find_default_sink(struct coresight_device *csdev);
struct coresight_path *coresight_build_path(struct coresight_device *csdev,
                                            struct coresight_device *sink);
void coresight_release_path(struct coresight_path *path);
int coresight_add_sysfs_link(struct coresight_sysfs_link *info);
void coresight_remove_sysfs_link(struct coresight_sysfs_link *info);
int coresight_create_conns_sysfs_group(struct coresight_device *csdev);
void coresight_remove_conns_sysfs_group(struct coresight_device *csdev);
int coresight_make_links(struct coresight_device *orig,
                         struct coresight_connection *conn,
                         struct coresight_device *target);
void coresight_remove_links(struct coresight_device *orig,
                            struct coresight_connection *conn);
u32 coresight_get_sink_id(struct coresight_device *csdev);
void coresight_path_assign_trace_id(struct coresight_path *path,
                                   enum cs_mode mode);

#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X)
int etm_readl_cp14(u32 off, unsigned int *val);
int etm_writel_cp14(u32 off, u32 val);
#else
static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
#endif

struct cti_assoc_op {
        void (*add)(struct coresight_device *csdev);
        void (*remove)(struct coresight_device *csdev);
};

void coresight_set_cti_ops(const struct cti_assoc_op *cti_op);
void coresight_remove_cti_ops(void);

/*
 * Macros and inline functions to handle CoreSight UCI data and driver
 * private data in AMBA ID table entries, and extract data values.
 */

/* coresight AMBA ID, no UCI, no driver data: id table entry */
#define CS_AMBA_ID(pid)                 \
        {                               \
                .id     = pid,          \
                .mask   = 0x000fffff,   \
        }

/* coresight AMBA ID, UCI with driver data only: id table entry. */
#define CS_AMBA_ID_DATA(pid, dval)                              \
        {                                                       \
                .id     = pid,                                  \
                .mask   = 0x000fffff,                           \
                .data   =  (void *)&(struct amba_cs_uci_id)     \
                        {                               \
                                .data = (void *)dval,   \
                        }                               \
        }

/* coresight AMBA ID, full UCI structure: id table entry. */
#define __CS_AMBA_UCI_ID(pid, m, uci_ptr)       \
        {                                       \
                .id     = pid,                  \
                .mask   = m,                    \
                .data   = (void *)uci_ptr       \
        }
#define CS_AMBA_UCI_ID(pid, uci)        __CS_AMBA_UCI_ID(pid, 0x000fffff, uci)
/*
 * PIDR2[JEDEC], BIT(3) must be 1 (Read As One) to indicate that rest of the
 * PIDR1, PIDR2 DES_* fields follow JEDEC encoding for the designer. Use that
 * as a match value for blanket matching all devices in the given CoreSight
 * device type and architecture.
 */
#define PIDR2_JEDEC                     BIT(3)
#define PID_PIDR2_JEDEC                 (PIDR2_JEDEC << 16)
/*
 * Match all PIDs in a given CoreSight device type and architecture, defined
 * by the uci.
 */
#define CS_AMBA_MATCH_ALL_UCI(uci)                                      \
        __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci)

/* extract the data value from a UCI structure given amba_id pointer. */
static inline void *coresight_get_uci_data(const struct amba_id *id)
{
        struct amba_cs_uci_id *uci_id = id->data;

        if (!uci_id)
                return NULL;

        return uci_id->data;
}

static inline void *coresight_get_uci_data_from_amba(const struct amba_id *table, u32 pid)
{
        while (table->mask) {
                if ((pid & table->mask) == table->id)
                        return coresight_get_uci_data(table);
                table++;
        };
        return NULL;
}

void coresight_release_platform_data(struct coresight_device *csdev,
                                     struct device *dev,
                                     struct coresight_platform_data *pdata);
struct coresight_device *
coresight_find_csdev_by_fwnode(struct fwnode_handle *r_fwnode);
void coresight_add_helper(struct coresight_device *csdev,
                          struct coresight_device *helper);

void coresight_set_percpu_sink(int cpu, struct coresight_device *csdev);
struct coresight_device *coresight_get_percpu_sink(int cpu);
void coresight_disable_source(struct coresight_device *csdev, void *data);
void coresight_pause_source(struct coresight_device *csdev);
int coresight_resume_source(struct coresight_device *csdev);

#endif