bin/pkill/pkill.c

143

regex_t reg;

bin/pkill/pkill.c

372

if ((rv = regcomp(&reg, *argv, cflags)) != 0) {

bin/pkill/pkill.c

373

regerror(rv, &reg, buf, bufsz);

bin/pkill/pkill.c

401

rv = regexec(&reg, mstr, 1, &regmatch, 0);

bin/pkill/pkill.c

411

regerror(rv, &reg, buf, bufsz);

bin/pkill/pkill.c

425

regfree(&reg);

crypto/krb5/src/kadmin/dbutil/dump.c

225

regex_t reg;

crypto/krb5/src/kadmin/dbutil/dump.c

235

st = regcomp(&reg, args->names[i], REG_EXTENDED);

crypto/krb5/src/kadmin/dbutil/dump.c

237

regerror(st, &reg, errmsg, sizeof(errmsg));

crypto/krb5/src/kadmin/dbutil/dump.c

243

st = regexec(&reg, name, 1, &rmatch, 0);

crypto/krb5/src/kadmin/dbutil/dump.c

249

regerror(st, &reg, errmsg, sizeof(errmsg));

crypto/krb5/src/kadmin/dbutil/dump.c

254

regfree(&reg);

crypto/krb5/src/plugins/preauth/spake/edwards25519.c

1749

.reg = &spake_iana_edwards25519,

crypto/krb5/src/plugins/preauth/spake/groups.c

106

if (groupdefs[i]->reg->id == group)

crypto/krb5/src/plugins/preauth/spake/groups.c

120

if (strcasecmp(name, groupdefs[i]->reg->name) == 0)

crypto/krb5/src/plugins/preauth/spake/groups.c

121

return groupdefs[i]->reg->id;

crypto/krb5/src/plugins/preauth/spake/groups.c

328

*len_out = gdef->reg->mult_len;

crypto/krb5/src/plugins/preauth/spake/groups.c

344

if (gdef == NULL || wbytes->length != gdef->reg->mult_len)

crypto/krb5/src/plugins/preauth/spake/groups.c

350

priv = k5alloc(gdef->reg->mult_len, &ret);

crypto/krb5/src/plugins/preauth/spake/groups.c

353

pub = k5alloc(gdef->reg->elem_len, &ret);

crypto/krb5/src/plugins/preauth/spake/groups.c

362

*priv_out = make_data(priv, gdef->reg->mult_len);

crypto/krb5/src/plugins/preauth/spake/groups.c

363

*pub_out = make_data(pub, gdef->reg->elem_len);

crypto/krb5/src/plugins/preauth/spake/groups.c

368

zapfree(priv, gdef->reg->mult_len);

crypto/krb5/src/plugins/preauth/spake/groups.c

385

if (gdef == NULL || wbytes->length != gdef->reg->mult_len)

crypto/krb5/src/plugins/preauth/spake/groups.c

387

if (ourpriv->length != gdef->reg->mult_len ||

crypto/krb5/src/plugins/preauth/spake/groups.c

388

theirpub->length != gdef->reg->elem_len)

crypto/krb5/src/plugins/preauth/spake/groups.c

394

spakeresult = k5alloc(gdef->reg->elem_len, &ret);

crypto/krb5/src/plugins/preauth/spake/groups.c

405

*spakeresult_out = make_data(spakeresult, gdef->reg->elem_len);

crypto/krb5/src/plugins/preauth/spake/groups.c

410

zapfree(spakeresult, gdef->reg->elem_len);

crypto/krb5/src/plugins/preauth/spake/groups.c

423

*len_out = gdef->reg->hash_len;

crypto/krb5/src/plugins/preauth/spake/groups.h

44

const spake_iana *reg;

crypto/krb5/src/plugins/preauth/spake/openssl.c

122

if (!EC_POINT_oct2point(gd->group, gd->M, reg->m, reg->elem_len, gd->ctx))

crypto/krb5/src/plugins/preauth/spake/openssl.c

128

if (!EC_POINT_oct2point(gd->group, gd->N, reg->n, reg->elem_len, gd->ctx))

crypto/krb5/src/plugins/preauth/spake/openssl.c

146

const spake_iana *reg = gdata->gdef->reg;

crypto/krb5/src/plugins/preauth/spake/openssl.c

155

if (BN_bin2bn(wbytes, reg->mult_len, w) &&

crypto/krb5/src/plugins/preauth/spake/openssl.c

167

const spake_iana *reg = gdata->gdef->reg;

crypto/krb5/src/plugins/preauth/spake/openssl.c

194

memset(priv_out, 0, reg->mult_len);

crypto/krb5/src/plugins/preauth/spake/openssl.c

195

BN_bn2bin(priv, &priv_out[reg->mult_len - BN_num_bytes(priv)]);

crypto/krb5/src/plugins/preauth/spake/openssl.c

199

pub_out, reg->elem_len, gdata->ctx);

crypto/krb5/src/plugins/preauth/spake/openssl.c

200

if (len != reg->elem_len)

crypto/krb5/src/plugins/preauth/spake/openssl.c

217

const spake_iana *reg = gdata->gdef->reg;

crypto/krb5/src/plugins/preauth/spake/openssl.c

228

priv = BN_bin2bn(ourpriv, reg->mult_len, NULL);

crypto/krb5/src/plugins/preauth/spake/openssl.c

235

if (!EC_POINT_oct2point(gdata->group, pub, theirpub, reg->elem_len,

crypto/krb5/src/plugins/preauth/spake/openssl.c

257

elem_out, reg->elem_len, gdata->ctx);

crypto/krb5/src/plugins/preauth/spake/openssl.c

258

if (len != reg->elem_len)

crypto/krb5/src/plugins/preauth/spake/openssl.c

291

.reg = &spake_iana_p256,

crypto/krb5/src/plugins/preauth/spake/openssl.c

300

.reg = &spake_iana_p384,

crypto/krb5/src/plugins/preauth/spake/openssl.c

309

.reg = &spake_iana_p521,

crypto/krb5/src/plugins/preauth/spake/openssl.c

78

const spake_iana *reg = gdef->reg;

crypto/krb5/src/plugins/preauth/spake/openssl.c

83

switch (reg->id) {

crypto/openssl/include/crypto/sparc_arch.h

105

#define SPARC_LOAD_ADDRESS_LEAF(SYM, reg, tmp) SPARC_LOAD_ADDRESS(SYM, reg)

crypto/openssl/include/crypto/sparc_arch.h

113

# define SPARC_LOAD_ADDRESS(SYM, reg) \

crypto/openssl/include/crypto/sparc_arch.h

114

SPARC_SETUP_GOT_REG(reg); \

crypto/openssl/include/crypto/sparc_arch.h

117

LDPTR [reg + %o7], reg;

crypto/openssl/include/crypto/sparc_arch.h

121

# define SPARC_LOAD_ADDRESS_LEAF(SYM, reg, tmp) \

crypto/openssl/include/crypto/sparc_arch.h

123

SPARC_LOAD_ADDRESS(SYM, reg) \

crypto/openssl/include/crypto/sparc_arch.h

58

# define SPARC_PIC_THUNK(reg) \

crypto/openssl/include/crypto/sparc_arch.h

62

add %o7, reg, reg;

crypto/openssl/include/crypto/sparc_arch.h

64

# define SPARC_PIC_THUNK_CALL(reg) \

crypto/openssl/include/crypto/sparc_arch.h

65

sethi %hi(_GLOBAL_OFFSET_TABLE_-4), reg; \

crypto/openssl/include/crypto/sparc_arch.h

67

or reg, %lo(_GLOBAL_OFFSET_TABLE_+4), reg;

crypto/openssl/include/crypto/sparc_arch.h

70

# define SPARC_SETUP_GOT_REG(reg) SPARC_PIC_THUNK_CALL(reg)

crypto/openssl/include/crypto/sparc_arch.h

72

# define SPARC_SETUP_GOT_REG(reg) \

crypto/openssl/include/crypto/sparc_arch.h

73

sethi %hi(_GLOBAL_OFFSET_TABLE_-4), reg; \

crypto/openssl/include/crypto/sparc_arch.h

75

or reg,%lo(_GLOBAL_OFFSET_TABLE_+4), reg; \

crypto/openssl/include/crypto/sparc_arch.h

76

add %o7, reg, reg

crypto/openssl/include/crypto/sparc_arch.h

83

#define SPARC_LOAD_ADDRESS(SYM, reg) \

crypto/openssl/include/crypto/sparc_arch.h

84

setx SYM, %o7, reg;

crypto/openssl/include/crypto/sparc_arch.h

96

#define SPARC_LOAD_ADDRESS(SYM, reg) \

crypto/openssl/include/crypto/sparc_arch.h

97

set SYM, reg;

lib/clang/liblldb/LLDBWrapLua.cpp

1433

SWIGINTERN void SWIG_Lua_namespace_register(lua_State *L, swig_lua_namespace *ns, int reg)

lib/clang/liblldb/LLDBWrapLua.cpp

1476

if (reg) {

lib/libc/arm/aeabi/aeabi_vfp.h

63

#define LOAD_SREG(vreg, reg) vmov vreg, reg

lib/libc/arm/aeabi/aeabi_vfp.h

64

#define UNLOAD_SREG(reg, vreg) vmov reg, vreg

lib/libc/net/nsdispatch.c

462

#define NSS_BACKEND(name, reg) \

lib/libc/net/nsdispatch.c

463

ns_mtab *reg(unsigned int *, nss_module_unregister_fn *);

lib/libc/net/nsdispatch.c

470

#define NSS_BACKEND(name, reg) nss_load_module(#name, reg);

lib/libnetmap/libnetmap.h

178

struct nmreq_register reg;

lib/libnetmap/libnetmap.h

525

int nmreq_register_decode(const char **pmode, struct nmreq_register *reg,

lib/libnetmap/nmport.c

398

if (d->reg.nr_mem_id && d->reg.nr_mem_id != mem_id) {

lib/libnetmap/nmport.c

400

mem_id, d->reg.nr_mem_id);

lib/libnetmap/nmport.c

404

d->reg.nr_mem_id = mem_id;

lib/libnetmap/nmport.c

456

d->reg.nr_tx_rings = nr_rings;

lib/libnetmap/nmport.c

457

d->reg.nr_rx_rings = nr_rings;

lib/libnetmap/nmport.c

461

d->reg.nr_host_tx_rings = nr_rings;

lib/libnetmap/nmport.c

462

d->reg.nr_host_rx_rings = nr_rings;

lib/libnetmap/nmport.c

466

d->reg.nr_tx_slots = nr_slots;

lib/libnetmap/nmport.c

467

d->reg.nr_rx_slots = nr_slots;

lib/libnetmap/nmport.c

470

d->reg.nr_tx_rings = atoi(nmport_key(p, conf, tx_rings));

lib/libnetmap/nmport.c

473

d->reg.nr_rx_rings = atoi(nmport_key(p, conf, rx_rings));

lib/libnetmap/nmport.c

476

d->reg.nr_host_tx_rings = atoi(nmport_key(p, conf, host_tx_rings));

lib/libnetmap/nmport.c

479

d->reg.nr_host_rx_rings = atoi(nmport_key(p, conf, host_rx_rings));

lib/libnetmap/nmport.c

482

d->reg.nr_tx_slots = atoi(nmport_key(p, conf, tx_slots));

lib/libnetmap/nmport.c

485

d->reg.nr_rx_slots = atoi(nmport_key(p, conf, rx_slots));

lib/libnetmap/nmport.c

545

if (nmreq_register_decode(&scan, &d->reg, d->ctx) < 0) {

lib/libnetmap/nmport.c

564

memset(&d->reg, 0, sizeof(d->reg));

lib/libnetmap/nmport.c

678

if (m->mem_id == d->reg.nr_mem_id)

lib/libnetmap/nmport.c

693

m->mem = mmap(NULL, d->reg.nr_memsize, PROT_READ|PROT_WRITE,

lib/libnetmap/nmport.c

699

m->size = d->reg.nr_memsize;

lib/libnetmap/nmport.c

701

m->mem_id = d->reg.nr_mem_id;

lib/libnetmap/nmport.c

713

d->nifp = NETMAP_IF(m->mem, d->reg.nr_offset);

lib/libnetmap/nmport.c

715

num_tx = d->reg.nr_tx_rings + d->nifp->ni_host_tx_rings;

lib/libnetmap/nmport.c

723

num_rx = d->reg.nr_rx_rings + d->nifp->ni_host_rx_rings;

lib/libnetmap/nmport.c

850

c->hdr.nr_body = (uintptr_t)&c->reg;

lib/libnetmap/nmport.c

853

c->reg = d->reg; /* this also copies the mem_id */

lib/libnetmap/nmport.c

89

nmreq_header_init(&d->hdr, NETMAP_REQ_REGISTER, &d->reg);

lib/libnetmap/nmreq.c

675

printf(" nr_mem_id: %"PRIu16"\n", d->reg.nr_mem_id);

lib/libnetmap/nmreq.c

676

printf(" nr_ringid: %"PRIu16"\n", d->reg.nr_ringid);

lib/libnetmap/nmreq.c

677

printf(" nr_mode: %lx\n", (unsigned long)d->reg.nr_mode);

lib/libnetmap/nmreq.c

678

printf(" nr_flags: %lx\n", (unsigned long)d->reg.nr_flags);

lib/libproc/proc_regs.c

105

switch (reg) {

lib/libproc/proc_regs.c

137

DPRINTFX("ERROR: no support for reg number %d", reg);

lib/libproc/proc_regs.c

42

proc_regget(struct proc_handle *phdl, proc_reg_t reg, unsigned long *regvalue)

lib/libproc/proc_regs.c

44

struct reg regs;

lib/libproc/proc_regs.c

54

switch (reg) {

lib/libproc/proc_regs.c

86

DPRINTFX("ERROR: no support for reg number %d", reg);

lib/libproc/proc_regs.c

94

proc_regset(struct proc_handle *phdl, proc_reg_t reg, unsigned long regvalue)

lib/libproc/proc_regs.c

96

struct reg regs;

lib/libsys/aarch64/__vdso_gettc.c

40

uint64_t reg;

lib/libsys/aarch64/__vdso_gettc.c

42

__asm __volatile("mrs %0, cntvct_el0" : "=r" (reg));

lib/libsys/aarch64/__vdso_gettc.c

43

return (reg);

lib/libsys/aarch64/__vdso_gettc.c

49

uint64_t reg;

lib/libsys/aarch64/__vdso_gettc.c

51

__asm __volatile("mrs %0, cntpct_el0" : "=r" (reg));

lib/libsys/aarch64/__vdso_gettc.c

52

return (reg);

lib/libsys/arm/__vdso_gettc.c

43

uint64_t reg;

lib/libsys/arm/__vdso_gettc.c

45

__asm __volatile("mrrc\tp15, 1, %Q0, %R0, c14" : "=r" (reg));

lib/libsys/arm/__vdso_gettc.c

46

return (reg);

lib/libsys/arm/__vdso_gettc.c

52

uint64_t reg;

lib/libsys/arm/__vdso_gettc.c

54

__asm __volatile("mrrc\tp15, 0, %Q0, %R0, c14" : "=r" (reg));

lib/libsys/arm/__vdso_gettc.c

55

return (reg);

lib/libthread_db/arch/aarch64/libpthread_md.c

38

pt_reg_to_ucontext(const struct reg *r, ucontext_t *uc)

lib/libthread_db/arch/aarch64/libpthread_md.c

50

pt_ucontext_to_reg(const ucontext_t *uc, struct reg *r)

lib/libthread_db/arch/aarch64/libpthread_md.c

88

pt_reg_sstep(struct reg *reg __unused, int step __unused)

lib/libthread_db/arch/amd64/libpthread_md.c

114

pt_reg_sstep(struct reg *reg, int step)

lib/libthread_db/arch/amd64/libpthread_md.c

118

old = reg->r_rflags;

lib/libthread_db/arch/amd64/libpthread_md.c

120

reg->r_rflags |= 0x0100;

lib/libthread_db/arch/amd64/libpthread_md.c

122

reg->r_rflags &= ~0x0100;

lib/libthread_db/arch/amd64/libpthread_md.c

123

return (old != reg->r_rflags); /* changed ? */

lib/libthread_db/arch/amd64/libpthread_md.c

39

pt_reg_to_ucontext(const struct reg *r, ucontext_t *uc)

lib/libthread_db/arch/amd64/libpthread_md.c

66

pt_ucontext_to_reg(const ucontext_t *uc, struct reg *r)

lib/libthread_db/arch/arm/libpthread_md.c

114

pt_reg_sstep(struct reg *reg __unused, int step __unused)

lib/libthread_db/arch/arm/libpthread_md.c

36

pt_reg_to_ucontext(const struct reg *r, ucontext_t *uc)

lib/libthread_db/arch/arm/libpthread_md.c

61

pt_ucontext_to_reg(const ucontext_t *uc, struct reg *r)

lib/libthread_db/arch/i386/libpthread_md.c

106

pt_reg_sstep(struct reg *reg, int step)

lib/libthread_db/arch/i386/libpthread_md.c

110

old = reg->r_eflags;

lib/libthread_db/arch/i386/libpthread_md.c

112

reg->r_eflags |= 0x0100;

lib/libthread_db/arch/i386/libpthread_md.c

114

reg->r_eflags &= ~0x0100;

lib/libthread_db/arch/i386/libpthread_md.c

115

return (old != reg->r_eflags); /* changed ? */

lib/libthread_db/arch/i386/libpthread_md.c

39

pt_reg_to_ucontext(const struct reg *r, ucontext_t *uc)

lib/libthread_db/arch/i386/libpthread_md.c

46

pt_ucontext_to_reg(const ucontext_t *uc, struct reg *r)

lib/libthread_db/arch/powerpc/libpthread_md.c

36

pt_reg_to_ucontext(const struct reg *r, ucontext_t *uc)

lib/libthread_db/arch/powerpc/libpthread_md.c

44

pt_ucontext_to_reg(const ucontext_t *uc, struct reg *r)

lib/libthread_db/arch/powerpc/libpthread_md.c

77

pt_reg_sstep(struct reg *reg __unused, int step __unused)

lib/libthread_db/arch/riscv/libpthread_md.c

103

pt_reg_sstep(struct reg *reg __unused, int step __unused)

lib/libthread_db/arch/riscv/libpthread_md.c

42

pt_reg_to_ucontext(const struct reg *r, ucontext_t *uc)

lib/libthread_db/arch/riscv/libpthread_md.c

60

pt_ucontext_to_reg(const ucontext_t *uc, struct reg *r)

lib/libthread_db/libpthread_db.c

981

struct reg regs;

lib/libthread_db/libpthread_db.h

84

void pt_reg_to_ucontext(const struct reg *, ucontext_t *);

lib/libthread_db/libpthread_db.h

85

void pt_ucontext_to_reg(const ucontext_t *, struct reg *);

lib/libthread_db/libpthread_db.h

92

int pt_reg_sstep(struct reg *reg, int step);

lib/libvmmapi/amd64/vmmapi_machdep.c

104

vmsegdesc.regnum = reg;

lib/libvmmapi/amd64/vmmapi_machdep.c

114

vm_get_desc(struct vcpu *vcpu, int reg, uint64_t *base, uint32_t *limit,

lib/libvmmapi/amd64/vmmapi_machdep.c

121

vmsegdesc.regnum = reg;

lib/libvmmapi/amd64/vmmapi_machdep.c

133

vm_get_seg_desc(struct vcpu *vcpu, int reg, struct seg_desc *seg_desc)

lib/libvmmapi/amd64/vmmapi_machdep.c

137

error = vm_get_desc(vcpu, reg, &seg_desc->base, &seg_desc->limit,

lib/libvmmapi/amd64/vmmapi_machdep.c

97

vm_set_desc(struct vcpu *vcpu, int reg,

lib/libvmmapi/vmmapi.c

748

vm_set_register(struct vcpu *vcpu, int reg, uint64_t val)

lib/libvmmapi/vmmapi.c

754

vmreg.regnum = reg;

lib/libvmmapi/vmmapi.c

762

vm_get_register(struct vcpu *vcpu, int reg, uint64_t *ret_val)

lib/libvmmapi/vmmapi.c

768

vmreg.regnum = reg;

lib/libvmmapi/vmmapi.h

149

int vm_set_desc(struct vcpu *vcpu, int reg,

lib/libvmmapi/vmmapi.h

151

int vm_get_desc(struct vcpu *vcpu, int reg,

lib/libvmmapi/vmmapi.h

153

int vm_get_seg_desc(struct vcpu *vcpu, int reg, struct seg_desc *seg_desc);

lib/libvmmapi/vmmapi.h

155

int vm_set_register(struct vcpu *vcpu, int reg, uint64_t val);

lib/libvmmapi/vmmapi.h

156

int vm_get_register(struct vcpu *vcpu, int reg, uint64_t *retval);

libexec/rtld-elf/rtld.c

3207

void (*reg)(void (*)(void));

libexec/rtld-elf/rtld.c

3236

reg = NULL;

libexec/rtld-elf/rtld.c

3238

reg = (void (*)(void (*)(void)))

libexec/rtld-elf/rtld.c

3242

if (reg != NULL) {

libexec/rtld-elf/rtld.c

3243

reg(rtld_exit);

sbin/etherswitchcfg/etherswitchcfg.c

125

er.reg = r;

sbin/etherswitchcfg/etherswitchcfg.c

136

er.reg = r;

sbin/etherswitchcfg/etherswitchcfg.c

143

read_phyregister(struct cfg *cfg, int phy, int reg)

sbin/etherswitchcfg/etherswitchcfg.c

148

er.reg = reg;

sbin/etherswitchcfg/etherswitchcfg.c

155

write_phyregister(struct cfg *cfg, int phy, int reg, int val)

sbin/etherswitchcfg/etherswitchcfg.c

160

er.reg = reg;

sbin/etherswitchcfg/etherswitchcfg.c

415

int phy, reg, val;

sbin/etherswitchcfg/etherswitchcfg.c

424

reg = strtol(d, &c, 0);

sbin/etherswitchcfg/etherswitchcfg.c

429

write_phyregister(cfg, phy, reg, val);

sbin/etherswitchcfg/etherswitchcfg.c

431

printf("\treg %d.0x%02x=0x%04x\n", phy, reg, read_phyregister(cfg, phy, reg));

sbin/ifconfig/ifieee80211.c

2148

const struct ieee80211_regdomain *reg,

sbin/ifconfig/ifieee80211.c

2266

if ((flags & REQ_ECM) && !reg->ecm) {

sbin/ifconfig/ifieee80211.c

2271

if ((flags & REQ_INDOOR) && reg->location == 'O') {

sbin/ifconfig/ifieee80211.c

2277

if ((flags & REQ_OUTDOOR) && reg->location == 'I') {

sbin/ifconfig/ifieee80211.c

2325

const struct ieee80211_regdomain *reg = &req->rd;

sbin/ifconfig/ifieee80211.c

2337

if (reg->regdomain == 0) {

sbin/ifconfig/ifieee80211.c

2338

cc = lib80211_country_findbycc(rdp, reg->country);

sbin/ifconfig/ifieee80211.c

2341

reg->country);

sbin/ifconfig/ifieee80211.c

2344

rd = lib80211_regdomain_findbysku(rdp, reg->regdomain);

sbin/ifconfig/ifieee80211.c

2347

reg->regdomain);

sbin/ifconfig/ifieee80211.c

2358

regdomain_addchans(ctx, ci, &rd->bands_11b, reg,

sbin/ifconfig/ifieee80211.c

2361

regdomain_addchans(ctx, ci, &rd->bands_11g, reg,

sbin/ifconfig/ifieee80211.c

2364

regdomain_addchans(ctx, ci, &rd->bands_11a, reg,

sbin/ifconfig/ifieee80211.c

2367

regdomain_addchans(ctx, ci, &rd->bands_11na, reg,

sbin/ifconfig/ifieee80211.c

2371

regdomain_addchans(ctx, ci, &rd->bands_11na, reg,

sbin/ifconfig/ifieee80211.c

2374

regdomain_addchans(ctx, ci, &rd->bands_11na, reg,

sbin/ifconfig/ifieee80211.c

2380

regdomain_addchans(ctx, ci, &rd->bands_11ac, reg,

sbin/ifconfig/ifieee80211.c

2387

regdomain_addchans(ctx, ci, &rd->bands_11ac, reg,

sbin/ifconfig/ifieee80211.c

2391

regdomain_addchans(ctx, ci, &rd->bands_11ac, reg,

sbin/ifconfig/ifieee80211.c

2399

regdomain_addchans(ctx, ci, &rd->bands_11ac, reg,

sbin/ifconfig/ifieee80211.c

2403

regdomain_addchans(ctx, ci, &rd->bands_11ac, reg,

sbin/ifconfig/ifieee80211.c

2412

regdomain_addchans(ctx, ci, &rd->bands_11ac, reg,

sbin/ifconfig/ifieee80211.c

2416

regdomain_addchans(ctx, ci, &rd->bands_11ac, reg,

sbin/ifconfig/ifieee80211.c

2425

regdomain_addchans(ctx, ci, &rd->bands_11ac, reg,

sbin/ifconfig/ifieee80211.c

2429

regdomain_addchans(ctx, ci, &rd->bands_11ac, reg,

sbin/ifconfig/ifieee80211.c

2437

regdomain_addchans(ctx, ci, &rd->bands_11ng, reg,

sbin/ifconfig/ifieee80211.c

2441

regdomain_addchans(ctx, ci, &rd->bands_11ng, reg,

sbin/ifconfig/ifieee80211.c

2444

regdomain_addchans(ctx, ci, &rd->bands_11ng, reg,

sbin/ifconfig/ifieee80211.c

4835

print_regdomain(const struct ieee80211_regdomain *reg, int verb)

sbin/ifconfig/ifieee80211.c

4837

if ((reg->regdomain != 0 &&

sbin/ifconfig/ifieee80211.c

4838

reg->regdomain != reg->country) || verb) {

sbin/ifconfig/ifieee80211.c

4840

lib80211_regdomain_findbysku(getregdata(), reg->regdomain);

sbin/ifconfig/ifieee80211.c

4842

LINE_CHECK("regdomain %d", reg->regdomain);

sbin/ifconfig/ifieee80211.c

4846

if (reg->country != 0 || verb) {

sbin/ifconfig/ifieee80211.c

4848

lib80211_country_findbycc(getregdata(), reg->country);

sbin/ifconfig/ifieee80211.c

4850

LINE_CHECK("country %d", reg->country);

sbin/ifconfig/ifieee80211.c

4854

if (reg->location == 'I')

sbin/ifconfig/ifieee80211.c

4856

else if (reg->location == 'O')

sbin/ifconfig/ifieee80211.c

4860

if (reg->ecm)

stand/fdt/fdt_loader_cmd.c

709

fdt_reg_valid(uint32_t *reg, int len, int addr_cells, int size_cells)

stand/fdt/fdt_loader_cmd.c

722

cur_start = fdt64_to_cpu(reg[i * cells_in_tuple]);

stand/fdt/fdt_loader_cmd.c

724

cur_start = fdt32_to_cpu(reg[i * cells_in_tuple]);

stand/fdt/fdt_loader_cmd.c

727

cur_size = fdt64_to_cpu(reg[i * cells_in_tuple + 2]);

stand/fdt/fdt_loader_cmd.c

729

cur_size = fdt32_to_cpu(reg[i * cells_in_tuple + 1]);

stand/i386/libi386/vbe.c

155

vga_get_reg(int reg, int index)

stand/i386/libi386/vbe.c

157

return (inb(reg + index));

stand/i386/libi386/vbe.c

161

vga_get_atr(int reg, int i)

stand/i386/libi386/vbe.c

165

(void) inb(reg + VGA_GEN_INPUT_STAT_1);

stand/i386/libi386/vbe.c

166

outb(reg + VGA_AC_WRITE, i);

stand/i386/libi386/vbe.c

167

ret = inb(reg + VGA_AC_READ);

stand/i386/libi386/vbe.c

169

(void) inb(reg + VGA_GEN_INPUT_STAT_1);

stand/i386/libi386/vbe.c

175

vga_set_atr(int reg, int i, int v)

stand/i386/libi386/vbe.c

177

(void) inb(reg + VGA_GEN_INPUT_STAT_1);

stand/i386/libi386/vbe.c

178

outb(reg + VGA_AC_WRITE, i);

stand/i386/libi386/vbe.c

179

outb(reg + VGA_AC_WRITE, v);

stand/i386/libi386/vbe.c

181

(void) inb(reg + VGA_GEN_INPUT_STAT_1);

stand/i386/libi386/vbe.c

185

vga_set_indexed(int reg, int indexreg, int datareg, uint8_t index, uint8_t val)

stand/i386/libi386/vbe.c

187

outb(reg + indexreg, index);

stand/i386/libi386/vbe.c

188

outb(reg + datareg, val);

stand/i386/libi386/vbe.c

192

vga_get_indexed(int reg, int indexreg, int datareg, uint8_t index)

stand/i386/libi386/vbe.c

194

outb(reg + indexreg, index);

stand/i386/libi386/vbe.c

195

return (inb(reg + datareg));

stand/i386/libi386/vbe.c

199

vga_get_crtc(int reg, int i)

stand/i386/libi386/vbe.c

201

return (vga_get_indexed(reg, VGA_CRTC_ADDRESS, VGA_CRTC_DATA, i));

stand/i386/libi386/vbe.c

205

vga_set_crtc(int reg, int i, int v)

stand/i386/libi386/vbe.c

207

vga_set_indexed(reg, VGA_CRTC_ADDRESS, VGA_CRTC_DATA, i, v);

stand/i386/libi386/vbe.c

211

vga_get_seq(int reg, int i)

stand/i386/libi386/vbe.c

213

return (vga_get_indexed(reg, VGA_SEQ_ADDRESS, VGA_SEQ_DATA, i));

stand/i386/libi386/vbe.c

217

vga_set_seq(int reg, int i, int v)

stand/i386/libi386/vbe.c

219

vga_set_indexed(reg, VGA_SEQ_ADDRESS, VGA_SEQ_DATA, i, v);

stand/i386/libi386/vbe.c

223

vga_get_grc(int reg, int i)

stand/i386/libi386/vbe.c

225

return (vga_get_indexed(reg, VGA_GC_ADDRESS, VGA_GC_DATA, i));

stand/i386/libi386/vbe.c

229

vga_set_grc(int reg, int i, int v)

stand/i386/libi386/vbe.c

231

vga_set_indexed(reg, VGA_GC_ADDRESS, VGA_GC_DATA, i, v);

stand/i386/libi386/vbe.c

417

biosvbe_palette_data(int mode, int reg, struct paletteentry *pe)

stand/i386/libi386/vbe.c

423

v86.edx = reg;

stand/i386/libi386/vidconsole.c

784

uint8_t reg[7];

stand/i386/libi386/vidconsole.c

802

reg[0] = vga_get_seq(VGA_REG_BASE, VGA_SEQ_MAP_MASK);

stand/i386/libi386/vidconsole.c

803

reg[1] = vga_get_seq(VGA_REG_BASE, VGA_SEQ_CLOCKING_MODE);

stand/i386/libi386/vidconsole.c

804

reg[2] = vga_get_seq(VGA_REG_BASE, VGA_SEQ_MEMORY_MODE);

stand/i386/libi386/vidconsole.c

805

reg[3] = vga_get_grc(VGA_REG_BASE, VGA_GC_READ_MAP_SELECT);

stand/i386/libi386/vidconsole.c

806

reg[4] = vga_get_grc(VGA_REG_BASE, VGA_GC_MODE);

stand/i386/libi386/vidconsole.c

807

reg[5] = vga_get_grc(VGA_REG_BASE, VGA_GC_MISCELLANEOUS);

stand/i386/libi386/vidconsole.c

808

reg[6] = vga_get_atr(VGA_REG_BASE, VGA_AC_MODE_CONTROL);

stand/i386/libi386/vidconsole.c

812

reg[1] | VGA_SEQ_CM_SO);

stand/i386/libi386/vidconsole.c

859

vga_set_atr(VGA_REG_BASE, VGA_AC_MODE_CONTROL, reg[6]);

stand/i386/libi386/vidconsole.c

863

vga_set_seq(VGA_REG_BASE, VGA_SEQ_MAP_MASK, reg[0]);

stand/i386/libi386/vidconsole.c

864

vga_set_seq(VGA_REG_BASE, VGA_SEQ_MEMORY_MODE, reg[2]);

stand/i386/libi386/vidconsole.c

870

vga_set_grc(VGA_REG_BASE, VGA_GC_READ_MAP_SELECT, reg[3]);

stand/i386/libi386/vidconsole.c

871

vga_set_grc(VGA_REG_BASE, VGA_GC_MODE, reg[4]);

stand/i386/libi386/vidconsole.c

872

vga_set_grc(VGA_REG_BASE, VGA_GC_MISCELLANEOUS, (reg[5] & 0x03) | 0x0c);

stand/i386/libi386/vidconsole.c

875

vga_set_seq(VGA_REG_BASE, VGA_SEQ_CLOCKING_MODE, reg[1] & 0xdf);

stand/powerpc/ofw/main.c

85

cell_t reg[24];

stand/powerpc/ofw/main.c

92

sz = OF_getencprop(memoryp, "reg", &reg[0], sizeof(reg));

stand/powerpc/ofw/main.c

93

sz /= sizeof(reg[0]);

stand/powerpc/ofw/main.c

97

memsz += (uint64_t)reg[i + acells] << 32;

stand/powerpc/ofw/main.c

98

memsz += reg[i + acells + scells - 1];

stand/userboot/userboot.h

220

int (*vm_set_register)(void *arg, int vcpu, int reg, uint64_t val);

stand/userboot/userboot.h

221

int (*vm_set_desc)(void *arg, int vcpu, int reg, uint64_t base,

sys/amd64/amd64/db_trace.c

105

long *reg;

sys/amd64/amd64/db_trace.c

110

reg = (long *)((uintptr_t)kdb_frame + (db_expr_t)vp->valuep);

sys/amd64/amd64/db_trace.c

112

*valuep = *reg;

sys/amd64/amd64/db_trace.c

114

*reg = *valuep;

sys/amd64/amd64/db_trace.c

89

uint16_t *reg;

sys/amd64/amd64/db_trace.c

94

reg = (uint16_t *)((uintptr_t)kdb_frame + (db_expr_t)vp->valuep);

sys/amd64/amd64/db_trace.c

96

*valuep = *reg;

sys/amd64/amd64/db_trace.c

98

*reg = *valuep;

sys/amd64/amd64/exec_machdep.c

455

fill_regs(struct thread *td, struct reg *regs)

sys/amd64/amd64/exec_machdep.c

464

fill_frame_regs(struct trapframe *tp, struct reg *regs)

sys/amd64/amd64/exec_machdep.c

504

set_regs(struct thread *td, struct reg *regs)

sys/amd64/amd64/ptrace_machdep.c

106

struct segbasereg32 *reg;

sys/amd64/amd64/ptrace_machdep.c

110

KASSERT(*sizep == sizeof(*reg), ("%s: invalid size", __func__));

sys/amd64/amd64/ptrace_machdep.c

111

reg = buf;

sys/amd64/amd64/ptrace_machdep.c

114

reg->r_fsbase = (uint32_t)pcb->pcb_fsbase;

sys/amd64/amd64/ptrace_machdep.c

115

reg->r_gsbase = (uint32_t)pcb->pcb_gsbase;

sys/amd64/amd64/ptrace_machdep.c

117

*sizep = sizeof(*reg);

sys/amd64/amd64/ptrace_machdep.c

125

struct segbasereg32 *reg;

sys/amd64/amd64/ptrace_machdep.c

128

KASSERT(size == sizeof(*reg), ("%s: invalid size", __func__));

sys/amd64/amd64/ptrace_machdep.c

129

reg = buf;

sys/amd64/amd64/ptrace_machdep.c

133

pcb->pcb_fsbase = reg->r_fsbase;

sys/amd64/amd64/ptrace_machdep.c

135

pcb->pcb_gsbase = reg->r_gsbase;

sys/amd64/amd64/ptrace_machdep.c

58

struct segbasereg *reg;

sys/amd64/amd64/ptrace_machdep.c

62

KASSERT(*sizep == sizeof(*reg), ("%s: invalid size", __func__));

sys/amd64/amd64/ptrace_machdep.c

63

reg = buf;

sys/amd64/amd64/ptrace_machdep.c

66

reg->r_fsbase = pcb->pcb_fsbase;

sys/amd64/amd64/ptrace_machdep.c

67

reg->r_gsbase = pcb->pcb_gsbase;

sys/amd64/amd64/ptrace_machdep.c

69

*sizep = sizeof(*reg);

sys/amd64/amd64/ptrace_machdep.c

77

struct segbasereg *reg;

sys/amd64/amd64/ptrace_machdep.c

80

KASSERT(size == sizeof(*reg), ("%s: invalid size", __func__));

sys/amd64/amd64/ptrace_machdep.c

81

reg = buf;

sys/amd64/amd64/ptrace_machdep.c

85

pcb->pcb_fsbase = reg->r_fsbase;

sys/amd64/amd64/ptrace_machdep.c

87

pcb->pcb_gsbase = reg->r_gsbase;

sys/amd64/amd64/trap.c

1095

int reg, regcnt, error;

sys/amd64/amd64/trap.c

1099

reg = 0;

sys/amd64/amd64/trap.c

1104

reg++;

sys/amd64/amd64/trap.c

1116

argp += reg;

sys/amd64/ia32/ia32_reg.c

270

struct segbasereg32 *reg;

sys/amd64/ia32/ia32_reg.c

274

KASSERT(*sizep == sizeof(*reg), ("%s: invalid size", __func__));

sys/amd64/ia32/ia32_reg.c

275

reg = buf;

sys/amd64/ia32/ia32_reg.c

280

reg->r_fsbase = pcb->pcb_fsbase;

sys/amd64/ia32/ia32_reg.c

281

reg->r_gsbase = pcb->pcb_gsbase;

sys/amd64/ia32/ia32_reg.c

283

*sizep = sizeof(*reg);

sys/amd64/ia32/ia32_reg.c

291

struct segbasereg32 *reg;

sys/amd64/ia32/ia32_reg.c

294

KASSERT(size == sizeof(*reg), ("%s: invalid size", __func__));

sys/amd64/ia32/ia32_reg.c

295

reg = buf;

sys/amd64/ia32/ia32_reg.c

299

pcb->pcb_fsbase = reg->r_fsbase;

sys/amd64/ia32/ia32_reg.c

301

pcb->pcb_gsbase = reg->r_gsbase;

sys/amd64/include/asmacros.h

84

#define PCPU_ADDR(member, reg) \

sys/amd64/include/asmacros.h

85

movq %gs:PC_PRVSPACE, reg ; \

sys/amd64/include/asmacros.h

86

addq $PC_ ## member, reg

sys/amd64/include/cpufunc.h

440

rxcr(u_int reg)

sys/amd64/include/cpufunc.h

444

__asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));

sys/amd64/include/cpufunc.h

449

load_xcr(u_int reg, u_long val)

sys/amd64/include/cpufunc.h

455

__asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));

sys/amd64/include/vmm.h

236

int vm_get_register(struct vcpu *vcpu, int reg, uint64_t *retval);

sys/amd64/include/vmm.h

237

int vm_set_register(struct vcpu *vcpu, int reg, uint64_t val);

sys/amd64/include/vmm.h

238

int vm_get_seg_desc(struct vcpu *vcpu, int reg,

sys/amd64/include/vmm.h

240

int vm_set_seg_desc(struct vcpu *vcpu, int reg,

sys/amd64/include/vmm.h

470

reg:4,

sys/amd64/include/vmm_instruction_emul.h

83

int vie_update_register(struct vcpu *vcpu, enum vm_reg_name reg,

sys/amd64/include/xen/hypercall.h

237

unsigned int reg, unsigned long value)

sys/amd64/include/xen/hypercall.h

239

return _hypercall2(int, set_debugreg, reg, value);

sys/amd64/include/xen/hypercall.h

244

unsigned int reg)

sys/amd64/include/xen/hypercall.h

246

return _hypercall1(unsigned long, get_debugreg, reg);

sys/amd64/include/xen/hypercall.h

336

int reg, unsigned long value)

sys/amd64/include/xen/hypercall.h

338

return _hypercall2(int, set_segment_base, reg, value);

sys/amd64/linux/linux.h

239

struct reg;

sys/amd64/linux/linux.h

242

void bsd_to_linux_regset(const struct reg *b_reg,

sys/amd64/linux/linux.h

244

void linux_to_bsd_regset(struct reg *b_reg,

sys/amd64/linux/linux.h

246

void linux_ptrace_get_syscall_info_machdep(const struct reg *reg,

sys/amd64/linux/linux_machdep.c

221

bsd_to_linux_regset(const struct reg *b_reg, struct linux_pt_regset *l_regset)

sys/amd64/linux/linux_machdep.c

254

linux_to_bsd_regset(struct reg *b_reg, const struct linux_pt_regset *l_regset)

sys/amd64/linux/linux_machdep.c

285

linux_ptrace_get_syscall_info_machdep(const struct reg *reg,

sys/amd64/linux/linux_machdep.c

290

si->instruction_pointer = reg->r_rip;

sys/amd64/linux/linux_machdep.c

291

si->stack_pointer = reg->r_rsp;

sys/amd64/linux/linux_machdep.c

331

struct linux_pt_regset reg;

sys/amd64/linux/linux_machdep.c

332

struct reg b_reg;

sys/amd64/linux/linux_machdep.c

350

bsd_to_linux_regset(&b_reg, &reg);

sys/amd64/linux/linux_machdep.c

351

val = *(&reg.r15 + ((uintptr_t)addr / sizeof(reg.r15)));

sys/amd64/linux/linux_machdep.c

363

uintptr_t reg;

sys/amd64/linux/linux_machdep.c

369

.reg = offsetof(struct linux_pt_regset, gs),

sys/amd64/linux/linux_machdep.c

373

.reg = offsetof(struct linux_pt_regset, fs),

sys/amd64/linux/linux_machdep.c

377

.reg = offsetof(struct linux_pt_regset, ds),

sys/amd64/linux/linux_machdep.c

381

.reg = offsetof(struct linux_pt_regset, es),

sys/amd64/linux/linux_machdep.c

385

.reg = offsetof(struct linux_pt_regset, cs),

sys/amd64/linux/linux_machdep.c

389

.reg = offsetof(struct linux_pt_regset, ss),

sys/amd64/linux/linux_machdep.c

397

struct linux_pt_regset reg;

sys/amd64/linux/linux_machdep.c

398

struct reg b_reg, b_reg1;

sys/amd64/linux/linux_machdep.c

414

if ((uintptr_t)addr == linux_segregs_off[i].reg) {

sys/amd64/linux/linux_machdep.c

423

bsd_to_linux_regset(&b_reg, &reg);

sys/amd64/linux/linux_machdep.c

424

*(&reg.r15 + ((uintptr_t)addr / sizeof(reg.r15))) = (uint64_t)data;

sys/amd64/linux/linux_machdep.c

425

linux_to_bsd_regset(&b_reg1, &reg);

sys/amd64/pci/pci_cfgreg.c

101

pci_docfgregread(int domain, int bus, int slot, int func, int reg, int bytes)

sys/amd64/pci/pci_cfgreg.c

104

return (pcireg_cfgread(bus, slot, func, reg, bytes));

sys/amd64/pci/pci_cfgreg.c

111

return (pciereg_cfgread(region, bus, slot, func, reg,

sys/amd64/pci/pci_cfgreg.c

116

return (pcireg_cfgread(bus, slot, func, reg, bytes));

sys/amd64/pci/pci_cfgreg.c

125

pci_cfgregread(int domain, int bus, int slot, int func, int reg, int bytes)

sys/amd64/pci/pci_cfgreg.c

137

if (reg == PCIR_INTLINE && bytes == 1) {

sys/amd64/pci/pci_cfgreg.c

144

return (pci_docfgregread(domain, bus, slot, func, reg, bytes));

sys/amd64/pci/pci_cfgreg.c

151

pci_cfgregwrite(int domain, int bus, int slot, int func, int reg, uint32_t data,

sys/amd64/pci/pci_cfgreg.c

155

pcireg_cfgwrite(bus, slot, func, reg, data, bytes);

sys/amd64/pci/pci_cfgreg.c

164

pciereg_cfgwrite(region, bus, slot, func, reg, data,

sys/amd64/pci/pci_cfgreg.c

171

pcireg_cfgwrite(bus, slot, func, reg, data, bytes);

sys/amd64/pci/pci_cfgreg.c

180

pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)

sys/amd64/pci/pci_cfgreg.c

185

(unsigned)reg <= PCI_REGMAX && bytes != 3 &&

sys/amd64/pci/pci_cfgreg.c

186

(unsigned)bytes <= 4 && (reg & (bytes - 1)) == 0) {

sys/amd64/pci/pci_cfgreg.c

188

| (func << 8) | (reg & ~0x03));

sys/amd64/pci/pci_cfgreg.c

189

dataport = CONF1_DATA_PORT + (reg & 0x03);

sys/amd64/pci/pci_cfgreg.c

206

pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)

sys/amd64/pci/pci_cfgreg.c

212

port = pci_cfgenable(bus, slot, func, reg, bytes);

sys/amd64/pci/pci_cfgreg.c

232

pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)

sys/amd64/pci/pci_cfgreg.c

237

port = pci_cfgenable(bus, slot, func, reg, bytes);

sys/amd64/pci/pci_cfgreg.c

313

#define PCIE_VADDR(base, reg, bus, slot, func) \

sys/amd64/pci/pci_cfgreg.c

318

((reg) & 0xfff)))

sys/amd64/pci/pci_cfgreg.c

330

unsigned func, unsigned reg, unsigned bytes)

sys/amd64/pci/pci_cfgreg.c

337

if (slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)

sys/amd64/pci/pci_cfgreg.c

340

va = PCIE_VADDR(region->base, reg, bus - region->minbus, slot, func);

sys/amd64/pci/pci_cfgreg.c

362

unsigned func, unsigned reg, int data, unsigned bytes)

sys/amd64/pci/pci_cfgreg.c

368

if (slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)

sys/amd64/pci/pci_cfgreg.c

371

va = PCIE_VADDR(region->base, reg, bus - region->minbus, slot, func);

sys/amd64/pci/pci_cfgreg.c

53

int reg, int bytes);

sys/amd64/pci/pci_cfgreg.c

56

unsigned slot, unsigned func, unsigned reg, unsigned bytes);

sys/amd64/pci/pci_cfgreg.c

58

unsigned slot, unsigned func, unsigned reg, int data,

sys/amd64/pci/pci_cfgreg.c

60

static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);

sys/amd64/pci/pci_cfgreg.c

61

static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);

sys/amd64/pt/pt.c

191

uint64_t reg;

sys/amd64/pt/pt.c

195

reg = rdmsr(MSR_IA32_RTIT_OUTPUT_MASK_PTRS);

sys/amd64/pt/pt.c

196

offset = ((reg & PT_TOPA_PAGE_MASK) >> PT_TOPA_PAGE_SHIFT) * PAGE_SIZE;

sys/amd64/pt/pt.c

197

offset += (reg >> 32);

sys/amd64/pt/pt.c

772

uint64_t reg;

sys/amd64/pt/pt.c

774

reg = rdmsr(MSR_IA_GLOBAL_STATUS_RESET);

sys/amd64/pt/pt.c

775

reg &= ~GLOBAL_STATUS_FLAG_TRACETOPAPMI;

sys/amd64/pt/pt.c

776

reg |= GLOBAL_STATUS_FLAG_TRACETOPAPMI;

sys/amd64/pt/pt.c

777

wrmsr(MSR_IA_GLOBAL_STATUS_RESET, reg);

sys/amd64/pt/pt.c

793

uint64_t reg;

sys/amd64/pt/pt.c

796

reg = rdmsr(MSR_IA_GLOBAL_STATUS);

sys/amd64/pt/pt.c

797

if ((reg & GLOBAL_STATUS_FLAG_TRACETOPAPMI) == 0) {

sys/amd64/vmm/amd/svm.c

135

static int svm_getdesc(void *vcpui, int reg, struct seg_desc *desc);

sys/amd64/vmm/amd/svm.c

2293

swctx_regptr(struct svm_regctx *regctx, int reg)

sys/amd64/vmm/amd/svm.c

2296

switch (reg) {

sys/amd64/vmm/amd/svm.c

2342

register_t *reg;

sys/amd64/vmm/amd/svm.c

2354

reg = swctx_regptr(svm_get_guest_regctx(vcpu), ident);

sys/amd64/vmm/amd/svm.c

2356

if (reg != NULL) {

sys/amd64/vmm/amd/svm.c

2357

*val = *reg;

sys/amd64/vmm/amd/svm.c

2369

register_t *reg;

sys/amd64/vmm/amd/svm.c

2384

reg = swctx_regptr(svm_get_guest_regctx(vcpu), ident);

sys/amd64/vmm/amd/svm.c

2386

if (reg != NULL) {

sys/amd64/vmm/amd/svm.c

2387

*reg = val;

sys/amd64/vmm/amd/svm.c

2407

svm_getdesc(void *vcpui, int reg, struct seg_desc *desc)

sys/amd64/vmm/amd/svm.c

2409

return (vmcb_getdesc(vcpui, reg, desc));

sys/amd64/vmm/amd/svm.c

2413

svm_setdesc(void *vcpui, int reg, struct seg_desc *desc)

sys/amd64/vmm/amd/svm.c

2415

return (vmcb_setdesc(vcpui, reg, desc));

sys/amd64/vmm/amd/vmcb.c

381

vmcb_setdesc(struct svm_vcpu *vcpu, int reg, struct seg_desc *desc)

sys/amd64/vmm/amd/vmcb.c

389

seg = vmcb_segptr(vmcb, reg);

sys/amd64/vmm/amd/vmcb.c

391

__func__, reg));

sys/amd64/vmm/amd/vmcb.c

395

if (reg != VM_REG_GUEST_GDTR && reg != VM_REG_GUEST_IDTR) {

sys/amd64/vmm/amd/vmcb.c

410

"attrib (%#x)", reg, seg->base, seg->limit, seg->attrib);

sys/amd64/vmm/amd/vmcb.c

412

switch (reg) {

sys/amd64/vmm/amd/vmcb.c

431

vmcb_getdesc(struct svm_vcpu *vcpu, int reg, struct seg_desc *desc)

sys/amd64/vmm/amd/vmcb.c

437

seg = vmcb_segptr(vmcb, reg);

sys/amd64/vmm/amd/vmcb.c

439

__func__, reg));

sys/amd64/vmm/amd/vmcb.c

445

if (reg != VM_REG_GUEST_GDTR && reg != VM_REG_GUEST_IDTR) {

sys/amd64/vmm/amd/vmcb.c

460

if (reg != VM_REG_GUEST_CS && reg != VM_REG_GUEST_TR) {

sys/amd64/vmm/amd/vmcb.c

503

vmcb_snapshot_desc(struct svm_vcpu *vcpu, int reg,

sys/amd64/vmm/amd/vmcb.c

510

ret = vmcb_getdesc(vcpu, reg, &desc);

sys/amd64/vmm/amd/vmcb.c

522

ret = vmcb_setdesc(vcpu, reg, &desc);

sys/amd64/vmm/amd/vmcb.h

363

int vmcb_snapshot_desc(struct svm_vcpu *vcpu, int reg,

sys/amd64/vmm/intel/vmx.c

2016

enum vm_reg_name reg;

sys/amd64/vmm/intel/vmx.c

2018

reg = in ? VM_REG_GUEST_RDI : VM_REG_GUEST_RSI;

sys/amd64/vmm/intel/vmx.c

2019

error = vmx_getreg(vcpu, reg, &val);

sys/amd64/vmm/intel/vmx.c

316

static int vmx_getdesc(void *vcpui, int reg, struct seg_desc *desc);

sys/amd64/vmm/intel/vmx.c

317

static int vmx_getreg(void *vcpui, int reg, uint64_t *retval);

sys/amd64/vmm/intel/vmx.c

318

static int vmxctx_setreg(struct vmxctx *vmxctx, int reg, uint64_t val);

sys/amd64/vmm/intel/vmx.c

3271

vmxctx_regptr(struct vmxctx *vmxctx, int reg)

sys/amd64/vmm/intel/vmx.c

3274

switch (reg) {

sys/amd64/vmm/intel/vmx.c

3324

vmxctx_getreg(struct vmxctx *vmxctx, int reg, uint64_t *retval)

sys/amd64/vmm/intel/vmx.c

3328

if ((regp = vmxctx_regptr(vmxctx, reg)) != NULL) {

sys/amd64/vmm/intel/vmx.c

3336

vmxctx_setreg(struct vmxctx *vmxctx, int reg, uint64_t val)

sys/amd64/vmm/intel/vmx.c

3340

if ((regp = vmxctx_regptr(vmxctx, reg)) != NULL) {

sys/amd64/vmm/intel/vmx.c

3388

vmx_shadow_reg(int reg)

sys/amd64/vmm/intel/vmx.c

3394

switch (reg) {

sys/amd64/vmm/intel/vmx.c

3409

vmx_getreg(void *vcpui, int reg, uint64_t *retval)

sys/amd64/vmm/intel/vmx.c

3420

switch (reg) {

sys/amd64/vmm/intel/vmx.c

3431

if (vmxctx_getreg(&vcpu->ctx, reg, retval) == 0)

sys/amd64/vmm/intel/vmx.c

3434

return (vmcs_getreg(vcpu->vmcs, running, reg, retval));

sys/amd64/vmm/intel/vmx.c

3438

vmx_setreg(void *vcpui, int reg, uint64_t val)

sys/amd64/vmm/intel/vmx.c

3451

if (reg == VM_REG_GUEST_INTR_SHADOW)

sys/amd64/vmm/intel/vmx.c

3454

if (vmxctx_setreg(&vcpu->ctx, reg, val) == 0)

sys/amd64/vmm/intel/vmx.c

3458

if (reg < 0)

sys/amd64/vmm/intel/vmx.c

3461

error = vmcs_setreg(vcpu->vmcs, running, reg, val);

sys/amd64/vmm/intel/vmx.c

3470

(reg == VM_REG_GUEST_EFER)) {

sys/amd64/vmm/intel/vmx.c

3481

shadow = vmx_shadow_reg(reg);

sys/amd64/vmm/intel/vmx.c

3490

if (reg == VM_REG_GUEST_CR3) {

sys/amd64/vmm/intel/vmx.c

3507

vmx_getdesc(void *vcpui, int reg, struct seg_desc *desc)

sys/amd64/vmm/intel/vmx.c

3518

return (vmcs_getdesc(vcpu->vmcs, running, reg, desc));

sys/amd64/vmm/intel/vmx.c

3522

vmx_setdesc(void *vcpui, int reg, struct seg_desc *desc)

sys/amd64/vmm/intel/vmx.c

3533

return (vmcs_setdesc(vcpu->vmcs, running, reg, desc));

sys/amd64/vmm/intel/vmx.c

3600

int reg;

sys/amd64/vmm/intel/vmx.c

3613

reg = VMCS_PRI_PROC_BASED_CTLS;

sys/amd64/vmm/intel/vmx.c

3622

reg = VMCS_PRI_PROC_BASED_CTLS;

sys/amd64/vmm/intel/vmx.c

3631

reg = VMCS_PRI_PROC_BASED_CTLS;

sys/amd64/vmm/intel/vmx.c

3651

reg = VMCS_SEC_PROC_BASED_CTLS;

sys/amd64/vmm/intel/vmx.c

3660

reg = VMCS_SEC_PROC_BASED_CTLS;

sys/amd64/vmm/intel/vmx.c

3671

reg = VMCS_EXCEPTION_BITMAP;

sys/amd64/vmm/intel/vmx.c

3697

error = vmwrite(reg, baseval);

sys/amd64/vmm/intel/vmx.h

103

uint32_t reg[PAGE_SIZE / 4];

sys/amd64/vmm/intel/vmx_cpufunc.h

118

vmwrite(uint64_t reg, uint64_t val)

sys/amd64/vmm/intel/vmx_cpufunc.h

125

: [val] "r" (val), [reg] "r" (reg)

sys/amd64/vmm/io/vioapic.c

112

low = vioapic->rtbl[pin].reg;

sys/amd64/vmm/io/vioapic.c

113

high = vioapic->rtbl[pin].reg >> 32;

sys/amd64/vmm/io/vioapic.c

129

vioapic->rtbl[pin].reg |= IOART_REM_IRR;

sys/amd64/vmm/io/vioapic.c

264

low = vioapic->rtbl[pin].reg;

sys/amd64/vmm/io/vioapic.c

265

high = vioapic->rtbl[pin].reg >> 32;

sys/amd64/vmm/io/vioapic.c

315

return (vioapic->rtbl[pin].reg >> rshift);

sys/amd64/vmm/io/vioapic.c

352

last = vioapic->rtbl[pin].reg;

sys/amd64/vmm/io/vioapic.c

356

vioapic->rtbl[pin].reg &= ~mask64 | RTBL_RO_BITS;

sys/amd64/vmm/io/vioapic.c

357

vioapic->rtbl[pin].reg |= data64 & ~RTBL_RO_BITS;

sys/amd64/vmm/io/vioapic.c

365

if ((vioapic->rtbl[pin].reg & IOART_TRGRMOD) == IOART_TRGREDG &&

sys/amd64/vmm/io/vioapic.c

366

(vioapic->rtbl[pin].reg & IOART_REM_IRR) != 0)

sys/amd64/vmm/io/vioapic.c

367

vioapic->rtbl[pin].reg &= ~IOART_REM_IRR;

sys/amd64/vmm/io/vioapic.c

370

pin, vioapic->rtbl[pin].reg);

sys/amd64/vmm/io/vioapic.c

377

changed = last ^ vioapic->rtbl[pin].reg;

sys/amd64/vmm/io/vioapic.c

393

if ((vioapic->rtbl[pin].reg & IOART_TRGRMOD) == IOART_TRGRLVL &&

sys/amd64/vmm/io/vioapic.c

482

if ((vioapic->rtbl[pin].reg & IOART_REM_IRR) == 0)

sys/amd64/vmm/io/vioapic.c

484

if ((vioapic->rtbl[pin].reg & IOART_INTVEC) != vector)

sys/amd64/vmm/io/vioapic.c

486

vioapic->rtbl[pin].reg &= ~IOART_REM_IRR;

sys/amd64/vmm/io/vioapic.c

509

vioapic->rtbl[i].reg = 0x0001000000010000UL;

sys/amd64/vmm/io/vioapic.c

539

SNAPSHOT_VAR_OR_LEAVE(vioapic->rtbl[i].reg, meta, ret, done);

sys/amd64/vmm/io/vioapic.c

64

uint64_t reg;

sys/amd64/vmm/io/vlapic.c

1339

uint32_t *reg;

sys/amd64/vmm/io/vlapic.c

1397

reg = &lapic->isr0;

sys/amd64/vmm/io/vlapic.c

1398

*data = *(reg + i);

sys/amd64/vmm/io/vlapic.c

1402

reg = &lapic->tmr0;

sys/amd64/vmm/io/vlapic.c

1403

*data = *(reg + i);

sys/amd64/vmm/io/vlapic.c

1407

reg = &lapic->irr0;

sys/amd64/vmm/io/vlapic.c

1408

*data = atomic_load_acq_int(reg + i);

sys/amd64/vmm/io/vlapic.c

1425

reg = vlapic_get_lvtptr(vlapic, offset);

sys/amd64/vmm/io/vlapic.c

1426

KASSERT(*data == *reg, ("inconsistent lvt value at "

sys/amd64/vmm/io/vlapic.c

1427

"offset %#lx: %#lx/%#x", offset, *data, *reg));

sys/amd64/vmm/io/vlapic.c

443

uint32_t mode, reg, vec;

sys/amd64/vmm/io/vlapic.c

445

reg = atomic_load_acq_32(&vlapic->lvt_last[lvt]);

sys/amd64/vmm/io/vlapic.c

447

if (reg & APIC_LVT_M)

sys/amd64/vmm/io/vlapic.c

449

vec = reg & APIC_LVT_VECTOR;

sys/amd64/vmm/io/vlapic.c

450

mode = reg & APIC_LVT_DM;

sys/amd64/vmm/vmm.c

595

vm_get_register(struct vcpu *vcpu, int reg, uint64_t *retval)

sys/amd64/vmm/vmm.c

598

if (reg >= VM_REG_LAST)

sys/amd64/vmm/vmm.c

601

return (vmmops_getreg(vcpu->cookie, reg, retval));

sys/amd64/vmm/vmm.c

605

vm_set_register(struct vcpu *vcpu, int reg, uint64_t val)

sys/amd64/vmm/vmm.c

610

if (reg >= VM_REG_LAST)

sys/amd64/vmm/vmm.c

613

error = vmmops_setreg(vcpu->cookie, reg, val);

sys/amd64/vmm/vmm.c

614

if (error || reg != VM_REG_GUEST_RIP)

sys/amd64/vmm/vmm.c

624

is_descriptor_table(int reg)

sys/amd64/vmm/vmm.c

627

switch (reg) {

sys/amd64/vmm/vmm.c

637

is_segment_register(int reg)

sys/amd64/vmm/vmm.c

640

switch (reg) {

sys/amd64/vmm/vmm.c

656

vm_get_seg_desc(struct vcpu *vcpu, int reg, struct seg_desc *desc)

sys/amd64/vmm/vmm.c

659

if (!is_segment_register(reg) && !is_descriptor_table(reg))

sys/amd64/vmm/vmm.c

662

return (vmmops_getdesc(vcpu->cookie, reg, desc));

sys/amd64/vmm/vmm.c

666

vm_set_seg_desc(struct vcpu *vcpu, int reg, struct seg_desc *desc)

sys/amd64/vmm/vmm.c

669

if (!is_segment_register(reg) && !is_descriptor_table(reg))

sys/amd64/vmm/vmm.c

672

return (vmmops_setdesc(vcpu->cookie, reg, desc));

sys/amd64/vmm/vmm_instruction_emul.c

1005

enum vm_reg_name reg;

sys/amd64/vmm/vmm_instruction_emul.c

1023

reg = gpr_map[vie->reg];

sys/amd64/vmm/vmm_instruction_emul.c

1024

error = vie_read_register(vcpu, reg, &val1);

sys/amd64/vmm/vmm_instruction_emul.c

1035

error = vie_update_register(vcpu, reg, result, size);

sys/amd64/vmm/vmm_instruction_emul.c

1093

enum vm_reg_name reg;

sys/amd64/vmm/vmm_instruction_emul.c

1111

reg = gpr_map[vie->reg];

sys/amd64/vmm/vmm_instruction_emul.c

1112

error = vie_read_register(vcpu, reg, &val1);

sys/amd64/vmm/vmm_instruction_emul.c

1123

error = vie_update_register(vcpu, reg, result, size);

sys/amd64/vmm/vmm_instruction_emul.c

1182

enum vm_reg_name reg;

sys/amd64/vmm/vmm_instruction_emul.c

1204

reg = gpr_map[vie->reg];

sys/amd64/vmm/vmm_instruction_emul.c

1205

error = vie_read_register(vcpu, reg, &regop);

sys/amd64/vmm/vmm_instruction_emul.c

1296

if ((vie->reg & 7) != 0)

sys/amd64/vmm/vmm_instruction_emul.c

1384

error = vie_update_register(vcpu, gpr_map[vie->reg], dst, size);

sys/amd64/vmm/vmm_instruction_emul.c

1406

enum vm_reg_name reg;

sys/amd64/vmm/vmm_instruction_emul.c

1422

reg = gpr_map[vie->reg];

sys/amd64/vmm/vmm_instruction_emul.c

1423

error = vie_read_register(vcpu, reg, &val1);

sys/amd64/vmm/vmm_instruction_emul.c

1434

error = vie_update_register(vcpu, reg, nval, size);

sys/amd64/vmm/vmm_instruction_emul.c

1462

enum vm_reg_name reg;

sys/amd64/vmm/vmm_instruction_emul.c

1478

reg = gpr_map[vie->reg];

sys/amd64/vmm/vmm_instruction_emul.c

1479

error = vie_read_register(vcpu, reg, &val1);

sys/amd64/vmm/vmm_instruction_emul.c

1490

error = vie_update_register(vcpu, reg, nval, size);

sys/amd64/vmm/vmm_instruction_emul.c

1627

if ((vie->reg & 7) != 6)

sys/amd64/vmm/vmm_instruction_emul.c

1648

if ((vie->reg & 7) != 0)

sys/amd64/vmm/vmm_instruction_emul.c

1663

switch (vie->reg & 7) {

sys/amd64/vmm/vmm_instruction_emul.c

1698

if ((vie->reg & 7) != 4)

sys/amd64/vmm/vmm_instruction_emul.c

1735

switch (vie->reg & 7) {

sys/amd64/vmm/vmm_instruction_emul.c

2555

vie->reg = (x >> 3) & 0x7;

sys/amd64/vmm/vmm_instruction_emul.c

2583

vie->reg |= (vie->rex_r << 3);

sys/amd64/vmm/vmm_instruction_emul.c

283

vie_read_register(struct vcpu *vcpu, enum vm_reg_name reg, uint64_t *rval)

sys/amd64/vmm/vmm_instruction_emul.c

287

error = vm_get_register(vcpu, reg, rval);

sys/amd64/vmm/vmm_instruction_emul.c

293

vie_calc_bytereg(struct vie *vie, enum vm_reg_name *reg, int *lhbr)

sys/amd64/vmm/vmm_instruction_emul.c

296

*reg = gpr_map[vie->reg];

sys/amd64/vmm/vmm_instruction_emul.c

311

if (vie->reg & 0x4) {

sys/amd64/vmm/vmm_instruction_emul.c

313

*reg = gpr_map[vie->reg & 0x3];

sys/amd64/vmm/vmm_instruction_emul.c

323

enum vm_reg_name reg;

sys/amd64/vmm/vmm_instruction_emul.c

325

vie_calc_bytereg(vie, &reg, &lhbr);

sys/amd64/vmm/vmm_instruction_emul.c

326

error = vm_get_register(vcpu, reg, &val);

sys/amd64/vmm/vmm_instruction_emul.c

344

enum vm_reg_name reg;

sys/amd64/vmm/vmm_instruction_emul.c

346

vie_calc_bytereg(vie, &reg, &lhbr);

sys/amd64/vmm/vmm_instruction_emul.c

347

error = vm_get_register(vcpu, reg, &origval);

sys/amd64/vmm/vmm_instruction_emul.c

360

error = vm_set_register(vcpu, reg, val);

sys/amd64/vmm/vmm_instruction_emul.c

366

vie_update_register(struct vcpu *vcpu, enum vm_reg_name reg,

sys/amd64/vmm/vmm_instruction_emul.c

375

error = vie_read_register(vcpu, reg, &origval);

sys/amd64/vmm/vmm_instruction_emul.c

390

error = vm_set_register(vcpu, reg, val);

sys/amd64/vmm/vmm_instruction_emul.c

506

enum vm_reg_name reg;

sys/amd64/vmm/vmm_instruction_emul.c

532

reg = gpr_map[vie->reg];

sys/amd64/vmm/vmm_instruction_emul.c

533

error = vie_read_register(vcpu, reg, &val);

sys/amd64/vmm/vmm_instruction_emul.c

559

reg = gpr_map[vie->reg];

sys/amd64/vmm/vmm_instruction_emul.c

560

error = vie_update_register(vcpu, reg, val, size);

sys/amd64/vmm/vmm_instruction_emul.c

572

reg = VM_REG_GUEST_RAX;

sys/amd64/vmm/vmm_instruction_emul.c

573

error = vie_update_register(vcpu, reg, val, size);

sys/amd64/vmm/vmm_instruction_emul.c

620

enum vm_reg_name reg;

sys/amd64/vmm/vmm_instruction_emul.c

643

reg = gpr_map[vie->reg];

sys/amd64/vmm/vmm_instruction_emul.c

649

error = vie_update_register(vcpu, reg, val, size);

sys/amd64/vmm/vmm_instruction_emul.c

663

reg = gpr_map[vie->reg];

sys/amd64/vmm/vmm_instruction_emul.c

668

error = vie_update_register(vcpu, reg, val, size);

sys/amd64/vmm/vmm_instruction_emul.c

686

reg = gpr_map[vie->reg];

sys/amd64/vmm/vmm_instruction_emul.c

692

error = vie_update_register(vcpu, reg, val, size);

sys/arm/allwinner/a10/a10_intc.c

108

#define aintc_read_4(sc, reg) \

sys/arm/allwinner/a10/a10_intc.c

109

bus_space_read_4(sc->aintc_bst, sc->aintc_bsh, reg)

sys/arm/allwinner/a10/a10_intc.c

110

#define aintc_write_4(sc, reg, val) \

sys/arm/allwinner/a10/a10_intc.c

111

bus_space_write_4(sc->aintc_bst, sc->aintc_bsh, reg, val)

sys/arm/allwinner/a10_ahci.c

267

uint32_t reg;

sys/arm/allwinner/a10_ahci.c

273

reg = ATA_INL(ch->r_mem, AHCI_P0DMACR);

sys/arm/allwinner/a10_ahci.c

274

reg &= ~0xff00;

sys/arm/allwinner/a10_ahci.c

275

reg |= 0x4400;

sys/arm/allwinner/a10_ahci.c

276

ATA_OUTL(ch->r_mem, AHCI_P0DMACR, reg);

sys/arm/allwinner/a10_codec.c

178

#define CODEC_ANALOG_READ(sc, reg) bus_read_4((sc)->res[1], (reg))

sys/arm/allwinner/a10_codec.c

179

#define CODEC_ANALOG_WRITE(sc, reg, val) bus_write_4((sc)->res[1], (reg), (val))

sys/arm/allwinner/a10_codec.c

181

#define CODEC_READ(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/arm/allwinner/a10_codec.c

182

#define CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/arm/allwinner/a10_codec.c

243

unsigned reg;

sys/arm/allwinner/a10_codec.c

266

val = CODEC_READ(sc, a10_mixers[dev].reg);

sys/arm/allwinner/a10_codec.c

269

CODEC_WRITE(sc, a10_mixers[dev].reg, val);

sys/arm/allwinner/a10_codec.c

481

pcell_t reg[2];

sys/arm/allwinner/a10_codec.c

491

reg, sizeof(reg)) <= 0) {

sys/arm/allwinner/a10_codec.c

495

sc->res[1] = bus_alloc_resource(sc->dev, SYS_RES_MEMORY, &rid, reg[0],

sys/arm/allwinner/a10_codec.c

496

reg[0]+reg[1], reg[1], RF_ACTIVE );

sys/arm/allwinner/a10_codec.c

518

unsigned reg;

sys/arm/allwinner/a10_codec.c

544

h3_pr_set_clear(sc, h3_mixers[dev].reg,

sys/arm/allwinner/a10_dmac.c

86

#define DMA_READ(sc, reg) bus_read_4((sc)->sc_res[0], (reg))

sys/arm/allwinner/a10_dmac.c

87

#define DMA_WRITE(sc, reg, val) bus_write_4((sc)->sc_res[0], (reg), (val))

sys/arm/allwinner/a10_dmac.c

88

#define DMACH_READ(ch, reg) \

sys/arm/allwinner/a10_dmac.c

89

DMA_READ((ch)->ch_sc, (reg) + (ch)->ch_regoff)

sys/arm/allwinner/a10_dmac.c

90

#define DMACH_WRITE(ch, reg, val) \

sys/arm/allwinner/a10_dmac.c

91

DMA_WRITE((ch)->ch_sc, (reg) + (ch)->ch_regoff, (val))

sys/arm/allwinner/a10_sramc.c

61

#define sramc_read_4(sc, reg) \

sys/arm/allwinner/a10_sramc.c

62

bus_space_read_4((sc)->bst, (sc)->bsh, (reg))

sys/arm/allwinner/a10_sramc.c

63

#define sramc_write_4(sc, reg, val) \

sys/arm/allwinner/a10_sramc.c

64

bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val))

sys/arm/allwinner/a20/a20_cpu_cfg.c

61

#define cpu_cfg_read_4(sc, reg) \

sys/arm/allwinner/a20/a20_cpu_cfg.c

62

bus_space_read_4((sc)->bst, (sc)->bsh, (reg))

sys/arm/allwinner/a20/a20_cpu_cfg.c

63

#define cpu_cfg_write_4(sc, reg, val) \

sys/arm/allwinner/a20/a20_cpu_cfg.c

64

bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val))

sys/arm/allwinner/a31_dmac.c

160

#define DMA_READ(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/arm/allwinner/a31_dmac.c

161

#define DMA_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/arm/allwinner/a33_codec.c

154

#define CODEC_READ(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/arm/allwinner/a33_codec.c

155

#define CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/arm/allwinner/a64/sun50i_a64_acodec.c

133

#define A64CODEC_READ(sc, reg) bus_read_4((sc)->res, (reg))

sys/arm/allwinner/a64/sun50i_a64_acodec.c

134

#define A64CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/arm/allwinner/a64/sun50i_a64_acodec.c

226

regulator_t reg;

sys/arm/allwinner/a64/sun50i_a64_acodec.c

241

if (regulator_get_by_ofw_property(dev, 0, "cpvdd-supply", &reg) == 0) {

sys/arm/allwinner/a64/sun50i_a64_acodec.c

242

error = regulator_enable(reg);

sys/arm/allwinner/aw_gmacclk.c

230

sc->reg = paddr;

sys/arm/allwinner/aw_gmacclk.c

81

bus_addr_t reg;

sys/arm/allwinner/aw_gmacclk.c

87

#define GMACCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val))

sys/arm/allwinner/aw_gmacclk.c

88

#define GMACCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val))

sys/arm/allwinner/aw_gpio.c

1240

uint32_t reg;

sys/arm/allwinner/aw_gpio.c

1250

reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_STA(sc->gpio_pic_irqsrc[irq].bank));

sys/arm/allwinner/aw_gpio.c

1251

if (!(reg & (1 << sc->gpio_pic_irqsrc[irq].intnum)))

sys/arm/allwinner/aw_gpio.c

1317

uint32_t reg;

sys/arm/allwinner/aw_gpio.c

1321

reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank));

sys/arm/allwinner/aw_gpio.c

1322

reg &= ~(1 << sc->gpio_pic_irqsrc[irq].intnum);

sys/arm/allwinner/aw_gpio.c

1323

AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank), reg);

sys/arm/allwinner/aw_gpio.c

1345

uint32_t reg;

sys/arm/allwinner/aw_gpio.c

1350

reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank));

sys/arm/allwinner/aw_gpio.c

1351

reg |= 1 << sc->gpio_pic_irqsrc[irq].intnum;

sys/arm/allwinner/aw_gpio.c

1352

AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank), reg);

sys/arm/allwinner/aw_gpio.c

1425

uint32_t pinidx, reg;

sys/arm/allwinner/aw_gpio.c

1472

reg = AW_GPIO_READ(sc,

sys/arm/allwinner/aw_gpio.c

1475

reg &= ~(0xF << pinidx);

sys/arm/allwinner/aw_gpio.c

1476

reg |= irqcfg;

sys/arm/allwinner/aw_gpio.c

1480

reg);

sys/arm/allwinner/aw_i2s.c

237

#define I2S_READ(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/arm/allwinner/aw_i2s.c

238

#define I2S_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/arm/allwinner/aw_mmc.c

1249

uint32_t reg;

sys/arm/allwinner/aw_mmc.c

1252

reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);

sys/arm/allwinner/aw_mmc.c

1253

reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER |

sys/arm/allwinner/aw_mmc.c

1257

reg |= AW_MMC_CKCR_ENB;

sys/arm/allwinner/aw_mmc.c

1259

reg |= AW_MMC_CKCR_MASK_DATA0;

sys/arm/allwinner/aw_mmc.c

1261

AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);

sys/arm/allwinner/aw_mmc.c

1263

reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK |

sys/arm/allwinner/aw_mmc.c

1265

AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg);

sys/arm/allwinner/aw_mmc.c

1268

while (reg & AW_MMC_CMDR_LOAD && --retry > 0) {

sys/arm/allwinner/aw_mmc.c

1269

reg = AW_MMC_READ_4(sc, AW_MMC_CMDR);

sys/arm/allwinner/aw_mmc.c

1274

if (reg & AW_MMC_CMDR_LOAD) {

sys/arm/allwinner/aw_mmc.c

1280

reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);

sys/arm/allwinner/aw_mmc.c

1281

reg &= ~AW_MMC_CKCR_MASK_DATA0;

sys/arm/allwinner/aw_mmc.c

1282

AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);

sys/arm/allwinner/aw_mmc.c

1331

uint32_t reg, div = 1;

sys/arm/allwinner/aw_mmc.c

1397

reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);

sys/arm/allwinner/aw_mmc.c

1400

reg |= AW_MMC_GCTL_DDR_MOD_SEL;

sys/arm/allwinner/aw_mmc.c

1402

reg &= ~AW_MMC_GCTL_DDR_MOD_SEL;

sys/arm/allwinner/aw_mmc.c

1403

AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);

sys/arm/allwinner/aw_mmc.c

1421

reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);

sys/arm/allwinner/aw_mmc.c

1422

reg &= ~AW_MMC_CKCR_DIV;

sys/arm/allwinner/aw_mmc.c

1423

reg |= div - 1;

sys/arm/allwinner/aw_mmc.c

1424

AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);

sys/arm/allwinner/aw_mmc.c

1428

reg = AW_MMC_READ_4(sc, AW_MMC_NTSR);

sys/arm/allwinner/aw_mmc.c

1429

reg |= AW_MMC_NTSR_MODE_SELECT;

sys/arm/allwinner/aw_mmc.c

1430

AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg);

sys/arm/allwinner/aw_mmc.c

726

uint32_t reg;

sys/arm/allwinner/aw_mmc.c

729

reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);

sys/arm/allwinner/aw_mmc.c

730

reg |= AW_MMC_GCTL_RESET;

sys/arm/allwinner/aw_mmc.c

731

AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);

sys/arm/allwinner/aw_mmc.c

754

uint32_t reg;

sys/arm/allwinner/aw_mmc.c

781

reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);

sys/arm/allwinner/aw_mmc.c

782

reg |= AW_MMC_GCTL_INT_ENB;

sys/arm/allwinner/aw_mmc.c

783

reg &= ~AW_MMC_GCTL_FIFO_AC_MOD;

sys/arm/allwinner/aw_mmc.c

784

reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS;

sys/arm/allwinner/aw_mmc.c

785

AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);

sys/arm/allwinner/aw_mp.c

100

ncpu = CPUV7_L2CTLR_NPROC(reg);

sys/arm/allwinner/aw_mp.c

94

uint32_t reg;

sys/arm/allwinner/aw_mp.c

99

reg = cp15_l2ctlr_get();

sys/arm/allwinner/aw_reset.c

66

#define RESET_READ(sc, reg) bus_read_4((sc)->res, (reg))

sys/arm/allwinner/aw_reset.c

67

#define RESET_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/arm/allwinner/aw_rsb.c

152

#define RSB_READ(sc, reg) bus_read_4((sc)->res, (reg))

sys/arm/allwinner/aw_rsb.c

153

#define RSB_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/arm/allwinner/aw_rtc.c

92

#define RTC_READ(sc, reg) bus_read_4((sc)->res, (reg))

sys/arm/allwinner/aw_rtc.c

93

#define RTC_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/arm/allwinner/aw_sid.c

285

#define RD1(sc, reg) bus_read_1((sc)->res, (reg))

sys/arm/allwinner/aw_sid.c

286

#define RD4(sc, reg) bus_read_4((sc)->res, (reg))

sys/arm/allwinner/aw_sid.c

287

#define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/arm/allwinner/aw_thermal.c

374

#define RD4(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/arm/allwinner/aw_thermal.c

375

#define WR4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/arm/allwinner/aw_timer.c

104

#define timer_read_4(sc, reg) \

sys/arm/allwinner/aw_timer.c

105

bus_read_4(sc->res[AW_TIMER_MEMRES], reg)

sys/arm/allwinner/aw_timer.c

106

#define timer_write_4(sc, reg, val) \

sys/arm/allwinner/aw_timer.c

107

bus_write_4(sc->res[AW_TIMER_MEMRES], reg, val)

sys/arm/allwinner/aw_usb3phy.c

158

if (sc->reg)

sys/arm/allwinner/aw_usb3phy.c

159

error = regulator_enable(sc->reg);

sys/arm/allwinner/aw_usb3phy.c

161

if (sc->reg)

sys/arm/allwinner/aw_usb3phy.c

162

error = regulator_disable(sc->reg);

sys/arm/allwinner/aw_usb3phy.c

259

regulator_get_by_ofw_property(dev, node, "phy-supply", &sc->reg);

sys/arm/allwinner/aw_usb3phy.c

88

regulator_t reg;

sys/arm/allwinner/aw_usbphy.c

157

regulator_t * reg;

sys/arm/allwinner/aw_usbphy.c

234

regulator_t reg;

sys/arm/allwinner/aw_usbphy.c

285

sc->reg = malloc(sizeof(*(sc->reg)) * sc->phy_conf->num_phys, M_DEVBUF,

sys/arm/allwinner/aw_usbphy.c

292

if (regulator_get_by_ofw_property(dev, 0, pname, &reg) == 0)

sys/arm/allwinner/aw_usbphy.c

293

sc->reg[off] = reg;

sys/arm/allwinner/aw_usbphy.c

356

regulator_t reg;

sys/arm/allwinner/aw_usbphy.c

370

reg = sc->reg[phy];

sys/arm/allwinner/aw_usbphy.c

371

if (reg == NULL)

sys/arm/allwinner/aw_usbphy.c

390

error = regulator_enable(reg);

sys/arm/allwinner/aw_usbphy.c

392

error = regulator_disable(reg);

sys/arm/allwinner/axp209.c

1205

uint8_t reg, data;

sys/arm/allwinner/axp209.c

1254

if (axp2xx_read(dev, sc->sensors[i].enable_reg, &reg, 1) == -1) {

sys/arm/allwinner/axp209.c

1259

reg |= sc->sensors[i].enable_mask;

sys/arm/allwinner/axp209.c

1260

if (axp2xx_write(dev, sc->sensors[i].enable_reg, reg) == -1) {

sys/arm/allwinner/axp209.c

1307

struct axp2xx_reg_sc *reg;

sys/arm/allwinner/axp209.c

1363

reg = axp2xx_reg_attach(dev, child, &regdefs[i]);

sys/arm/allwinner/axp209.c

1364

if (reg == NULL) {

sys/arm/allwinner/axp209.c

1370

sc->regs[i] = reg;

sys/arm/allwinner/axp209.c

636

axp2xx_read(device_t dev, uint8_t reg, uint8_t *data, uint8_t size)

sys/arm/allwinner/axp209.c

639

return (iicdev_readfrom(dev, reg, data, size, IIC_INTRWAIT));

sys/arm/allwinner/axp209.c

643

axp2xx_write(device_t dev, uint8_t reg, uint8_t data)

sys/arm/allwinner/axp209.c

646

return (iicdev_writeto(dev, reg, &data, sizeof(data), IIC_INTRWAIT));

sys/arm/allwinner/axp209.c

830

uint8_t reg;

sys/arm/allwinner/axp209.c

834

axp2xx_read(sc->dev, AXP2XX_IRQ1_STATUS, &reg, 1);

sys/arm/allwinner/axp209.c

835

if (reg) {

sys/arm/allwinner/axp209.c

836

if (reg & AXP2XX_IRQ1_AC_OVERVOLT)

sys/arm/allwinner/axp209.c

838

if (reg & AXP2XX_IRQ1_VBUS_OVERVOLT)

sys/arm/allwinner/axp209.c

840

if (reg & AXP2XX_IRQ1_VBUS_LOW)

sys/arm/allwinner/axp209.c

842

if (reg & AXP2XX_IRQ1_AC_CONN)

sys/arm/allwinner/axp209.c

844

if (reg & AXP2XX_IRQ1_AC_DISCONN)

sys/arm/allwinner/axp209.c

846

if (reg & AXP2XX_IRQ1_VBUS_CONN)

sys/arm/allwinner/axp209.c

848

if (reg & AXP2XX_IRQ1_VBUS_DISCONN)

sys/arm/allwinner/axp209.c

853

axp2xx_read(sc->dev, AXP2XX_IRQ2_STATUS, &reg, 1);

sys/arm/allwinner/axp209.c

854

if (reg) {

sys/arm/allwinner/axp209.c

855

if (reg & AXP2XX_IRQ2_BATT_CHARGED)

sys/arm/allwinner/axp209.c

857

if (reg & AXP2XX_IRQ2_BATT_CHARGING)

sys/arm/allwinner/axp209.c

859

if (reg & AXP2XX_IRQ2_BATT_CONN)

sys/arm/allwinner/axp209.c

861

if (reg & AXP2XX_IRQ2_BATT_DISCONN)

sys/arm/allwinner/axp209.c

863

if (reg & AXP2XX_IRQ2_BATT_TEMP_LOW)

sys/arm/allwinner/axp209.c

865

if (reg & AXP2XX_IRQ2_BATT_TEMP_OVER)

sys/arm/allwinner/axp209.c

870

axp2xx_read(sc->dev, AXP2XX_IRQ3_STATUS, &reg, 1);

sys/arm/allwinner/axp209.c

871

if (reg) {

sys/arm/allwinner/axp209.c

872

if (reg & AXP2XX_IRQ3_PEK_SHORT)

sys/arm/allwinner/axp209.c

877

axp2xx_read(sc->dev, AXP2XX_IRQ4_STATUS, &reg, 1);

sys/arm/allwinner/axp209.c

878

if (reg) {

sys/arm/allwinner/axp209.c

882

axp2xx_read(sc->dev, AXP2XX_IRQ5_STATUS, &reg, 1);

sys/arm/allwinner/axp209.c

883

if (reg) {

sys/arm/allwinner/axp81x.c

1466

struct axp8xx_reg_sc *reg;

sys/arm/allwinner/axp81x.c

1533

reg = axp8xx_reg_attach(dev, child,

sys/arm/allwinner/axp81x.c

1535

if (reg == NULL) {

sys/arm/allwinner/axp81x.c

1541

sc->regs[i] = reg;

sys/arm/allwinner/axp81x.c

712

axp8xx_read(device_t dev, uint8_t reg, uint8_t *data, uint8_t size)

sys/arm/allwinner/axp81x.c

722

msg[0].buf = ®

sys/arm/allwinner/axp81x.c

733

axp8xx_write(device_t dev, uint8_t reg, uint8_t val)

sys/arm/allwinner/axp81x.c

743

msg[0].buf = ®

sys/arm/allwinner/if_awg.c

1493

uint32_t reg, tx_delay, rx_delay;

sys/arm/allwinner/if_awg.c

1519

reg = syscon_read_emac_clk_reg(dev);

sys/arm/allwinner/if_awg.c

1520

reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN);

sys/arm/allwinner/if_awg.c

1522

reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII;

sys/arm/allwinner/if_awg.c

1524

reg |= EMAC_CLK_RMII_EN;

sys/arm/allwinner/if_awg.c

1526

reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII;

sys/arm/allwinner/if_awg.c

1539

reg &= ~(EMAC_CLK_ETXDC | EMAC_CLK_ERXDC);

sys/arm/allwinner/if_awg.c

1541

reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT);

sys/arm/allwinner/if_awg.c

1543

reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT);

sys/arm/allwinner/if_awg.c

1547

reg |= EMAC_CLK_EPHY_SELECT;

sys/arm/allwinner/if_awg.c

1548

reg &= ~EMAC_CLK_EPHY_SHUTDOWN;

sys/arm/allwinner/if_awg.c

1551

reg |= EMAC_CLK_EPHY_LED_POL;

sys/arm/allwinner/if_awg.c

1553

reg &= ~EMAC_CLK_EPHY_LED_POL;

sys/arm/allwinner/if_awg.c

1556

reg &= ~EMAC_CLK_EPHY_ADDR;

sys/arm/allwinner/if_awg.c

1557

reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT);

sys/arm/allwinner/if_awg.c

1559

reg &= ~EMAC_CLK_EPHY_SELECT;

sys/arm/allwinner/if_awg.c

1564

device_printf(dev, "EMAC clock: 0x%08x\n", reg);

sys/arm/allwinner/if_awg.c

1565

syscon_write_emac_clk_reg(dev, reg);

sys/arm/allwinner/if_awg.c

1616

regulator_t reg;

sys/arm/allwinner/if_awg.c

1623

reg = NULL;

sys/arm/allwinner/if_awg.c

1702

if (regulator_get_by_ofw_property(dev, 0, "phy-supply", &reg) == 0) {

sys/arm/allwinner/if_awg.c

1703

error = regulator_enable(reg);

sys/arm/allwinner/if_awg.c

1738

if (reg != NULL)

sys/arm/allwinner/if_awg.c

1739

regulator_release(reg);

sys/arm/allwinner/if_awg.c

1757

u_int reg;

sys/arm/allwinner/if_awg.c

1791

RD4(sc, regs[n].reg));

sys/arm/allwinner/if_awg.c

235

awg_miibus_readreg(device_t dev, int phy, int reg)

sys/arm/allwinner/if_awg.c

246

(reg << PHY_REG_ADDR_SHIFT) |

sys/arm/allwinner/if_awg.c

258

phy, reg);

sys/arm/allwinner/if_awg.c

264

awg_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/arm/allwinner/if_awg.c

275

(reg << PHY_REG_ADDR_SHIFT) |

sys/arm/allwinner/if_awg.c

285

phy, reg);

sys/arm/allwinner/if_awg.c

71

#define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg))

sys/arm/allwinner/if_awg.c

72

#define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val))

sys/arm/allwinner/if_emac.c

1007

EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);

sys/arm/allwinner/if_emac.c

1023

emac_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/arm/allwinner/if_emac.c

1030

EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);

sys/arm/allwinner/if_emac.c

135

#define EMAC_READ_REG(sc, reg) \

sys/arm/allwinner/if_emac.c

136

bus_space_read_4(sc->emac_tag, sc->emac_handle, reg)

sys/arm/allwinner/if_emac.c

137

#define EMAC_WRITE_REG(sc, reg, val) \

sys/arm/allwinner/if_emac.c

138

bus_space_write_4(sc->emac_tag, sc->emac_handle, reg, val)

sys/arm/allwinner/if_emac.c

615

uint32_t fifo, reg;

sys/arm/allwinner/if_emac.c

657

reg = (fifo == 0) ? EMAC_TX_PL0 : EMAC_TX_PL1;

sys/arm/allwinner/if_emac.c

658

EMAC_WRITE_REG(sc, reg, m->m_len);

sys/arm/allwinner/if_emac.c

661

reg = (fifo == 0) ? EMAC_TX_CTL0 : EMAC_TX_CTL1;

sys/arm/allwinner/if_emac.c

662

EMAC_WRITE_REG(sc, reg, EMAC_READ_REG(sc, reg) | 1);

sys/arm/allwinner/if_emac.c

999

emac_miibus_readreg(device_t dev, int phy, int reg)

sys/arm/annapurna/alpine/alpine_machdep_mp.c

100

reg = cp15_l2ctlr_get();

sys/arm/annapurna/alpine/alpine_machdep_mp.c

101

ncores = CPUV7_L2CTLR_NPROC(reg);

sys/arm/annapurna/alpine/alpine_machdep_mp.c

84

alpine_validate_cpu(u_int id, phandle_t child, u_int addr_cell, pcell_t *reg)

sys/arm/annapurna/alpine/alpine_machdep_mp.c

94

uint32_t reg;

sys/arm/arm/cpuinfo.c

350

uint32_t reg, newreg;

sys/arm/arm/cpuinfo.c

352

reg = cp15_actlr_get();

sys/arm/arm/cpuinfo.c

353

newreg = reg;

sys/arm/arm/cpuinfo.c

356

if (reg == newreg)

sys/arm/arm/cpuinfo.c

360

reg = cp15_actlr_get();

sys/arm/arm/cpuinfo.c

361

if (reg == newreg)

sys/arm/arm/cpuinfo.c

80

uint32_t reg;

sys/arm/arm/cpuinfo.c

82

reg = cp15_actlr_get();

sys/arm/arm/cpuinfo.c

83

return (SYSCTL_OUT(req, &reg, sizeof(reg)));

sys/arm/arm/db_interface.c

136

int *reg;

sys/arm/arm/db_interface.c

141

reg = (int *)((uintptr_t)kdb_frame + (db_expr_t)vp->valuep);

sys/arm/arm/db_interface.c

143

*valp = *reg;

sys/arm/arm/db_interface.c

145

*reg = *valp;

sys/arm/arm/db_interface.c

249

db_fetch_reg(int reg)

sys/arm/arm/db_interface.c

252

switch (reg) {

sys/arm/arm/db_interface.c

302

db_branch_taken_fetch_reg(void *cookie __unused, int reg)

sys/arm/arm/db_interface.c

305

return (db_fetch_reg(reg));

sys/arm/arm/db_trace.c

61

u_int reg, i;

sys/arm/arm/db_trace.c

91

for (i = 0, reg = 0; upd_mask != 0; upd_mask >>= 1, reg++) {

sys/arm/arm/db_trace.c

94

(reg < 10) ? " " : "", reg,

sys/arm/arm/db_trace.c

95

state->registers[reg]);

sys/arm/arm/debug_monitor.c

100

((((reg) & DBGDIDR_BRPS_MASK) >> DBGDIDR_BRPS_SHIFT) + 1)

sys/arm/arm/debug_monitor.c

208

dbg_wb_read_reg(int reg, int n)

sys/arm/arm/debug_monitor.c

214

switch (reg + n) {

sys/arm/arm/debug_monitor.c

222

reg >> OP2_SHIFT);

sys/arm/arm/debug_monitor.c

229

dbg_wb_write_reg(int reg, int n, uint32_t val)

sys/arm/arm/debug_monitor.c

232

switch (reg + n) {

sys/arm/arm/debug_monitor.c

240

reg >> OP2_SHIFT);

sys/arm/arm/debug_monitor.c

94

#define DBGDIDR_WRPS_NUM(reg) \

sys/arm/arm/debug_monitor.c

95

((((reg) & DBGDIDR_WRPS_MASK) >> DBGDIDR_WRPS_SHIFT) + 1)

sys/arm/arm/debug_monitor.c

99

#define DBGDIDR_BRPS_NUM(reg) \

sys/arm/arm/exec_machdep.c

113

memcpy(vfp->mcv_reg, pcb->pcb_vfpstate.reg,

sys/arm/arm/exec_machdep.c

135

memcpy(pcb->pcb_vfpstate.reg, vfp->mcv_reg,

sys/arm/arm/exec_machdep.c

136

sizeof(pcb->pcb_vfpstate.reg));

sys/arm/arm/generic_timer.c

315

int reg;

sys/arm/arm/generic_timer.c

326

reg = ISS_MSR_Rt(esr);

sys/arm/arm/generic_timer.c

328

if (reg < nitems(frame->tf_x)) {

sys/arm/arm/generic_timer.c

329

frame->tf_x[reg] = val;

sys/arm/arm/generic_timer.c

330

} else if (reg == 30) {

sys/arm/arm/gic.c

637

uint32_t reg;

sys/arm/arm/gic.c

645

reg = gic_d_read_4(sc, GICD_ICFGR(irq));

sys/arm/arm/gic.c

646

mask = (reg >> 2*(irq % 16)) & 0x3;

sys/arm/arm/gic.c

665

reg = reg & ~(0x3 << 2*(irq % 16));

sys/arm/arm/gic.c

666

reg = reg | (mask << 2*(irq % 16));

sys/arm/arm/gic.c

667

gic_d_write_4(sc, GICD_ICFGR(irq), reg);

sys/arm/arm/machdep_kdb.c

120

memcpy(regs->fpr_r, pcb->pcb_vfpstate.reg,

sys/arm/arm/machdep_kdb.c

130

set_regs(struct thread *td, struct reg *regs)

sys/arm/arm/machdep_kdb.c

152

memcpy(pcb->pcb_vfpstate.reg, regs->fpr_r, sizeof(regs->fpr_r));

sys/arm/arm/machdep_kdb.c

46

u_int reg;

sys/arm/arm/machdep_kdb.c

48

reg = cp15_midr_get();

sys/arm/arm/machdep_kdb.c

49

db_printf("Cpu ID: 0x%08x\n", reg);

sys/arm/arm/machdep_kdb.c

50

reg = cp15_ctr_get();

sys/arm/arm/machdep_kdb.c

51

db_printf("Current Cache Lvl ID: 0x%08x\n",reg);

sys/arm/arm/machdep_kdb.c

53

reg = cp15_sctlr_get();

sys/arm/arm/machdep_kdb.c

54

db_printf("Ctrl: 0x%08x\n",reg);

sys/arm/arm/machdep_kdb.c

55

reg = cp15_actlr_get();

sys/arm/arm/machdep_kdb.c

56

db_printf("Aux Ctrl: 0x%08x\n",reg);

sys/arm/arm/machdep_kdb.c

58

reg = cp15_id_pfr0_get();

sys/arm/arm/machdep_kdb.c

59

db_printf("Processor Feat 0: 0x%08x\n", reg);

sys/arm/arm/machdep_kdb.c

60

reg = cp15_id_pfr1_get();

sys/arm/arm/machdep_kdb.c

61

db_printf("Processor Feat 1: 0x%08x\n", reg);

sys/arm/arm/machdep_kdb.c

62

reg = cp15_id_dfr0_get();

sys/arm/arm/machdep_kdb.c

63

db_printf("Debug Feat 0: 0x%08x\n", reg);

sys/arm/arm/machdep_kdb.c

64

reg = cp15_id_afr0_get();

sys/arm/arm/machdep_kdb.c

65

db_printf("Auxiliary Feat 0: 0x%08x\n", reg);

sys/arm/arm/machdep_kdb.c

66

reg = cp15_id_mmfr0_get();

sys/arm/arm/machdep_kdb.c

67

db_printf("Memory Model Feat 0: 0x%08x\n", reg);

sys/arm/arm/machdep_kdb.c

68

reg = cp15_id_mmfr1_get();

sys/arm/arm/machdep_kdb.c

69

db_printf("Memory Model Feat 1: 0x%08x\n", reg);

sys/arm/arm/machdep_kdb.c

70

reg = cp15_id_mmfr2_get();

sys/arm/arm/machdep_kdb.c

71

db_printf("Memory Model Feat 2: 0x%08x\n", reg);

sys/arm/arm/machdep_kdb.c

72

reg = cp15_id_mmfr3_get();

sys/arm/arm/machdep_kdb.c

73

db_printf("Memory Model Feat 3: 0x%08x\n", reg);

sys/arm/arm/machdep_kdb.c

74

reg = cp15_ttbr_get();

sys/arm/arm/machdep_kdb.c

75

db_printf("TTB0: 0x%08x\n", reg);

sys/arm/arm/machdep_kdb.c

80

u_int reg;

sys/arm/arm/machdep_kdb.c

84

reg = cp15_par_get();

sys/arm/arm/machdep_kdb.c

85

db_printf("Physical address reg: 0x%08x\n",reg);

sys/arm/arm/machdep_kdb.c

92

fill_regs(struct thread *td, struct reg *regs)

sys/arm/arm/machdep_ptrace.c

57

ptrace_get_usr_reg(void *cookie, int reg)

sys/arm/arm/machdep_ptrace.c

62

KASSERT(((reg >= 0) && (reg <= ARM_REG_NUM_PC)),

sys/arm/arm/machdep_ptrace.c

65

switch(reg) {

sys/arm/arm/machdep_ptrace.c

76

ret = *((register_t*)&td->td_frame->tf_r0 + reg);

sys/arm/arm/mpcore_timer.c

114

#define tmr_prv_read_4(sc, reg) bus_read_4((sc)->prv_mem, reg)

sys/arm/arm/mpcore_timer.c

115

#define tmr_prv_write_4(sc, reg, val) bus_write_4((sc)->prv_mem, reg, val)

sys/arm/arm/mpcore_timer.c

116

#define tmr_gbl_read_4(sc, reg) bus_read_4((sc)->gbl_mem, reg)

sys/arm/arm/mpcore_timer.c

117

#define tmr_gbl_write_4(sc, reg, val) bus_write_4((sc)->gbl_mem, reg, val)

sys/arm/arm/pmap-v6.c

430

uint32_t inner, outer, nos, reg;

sys/arm/arm/pmap-v6.c

439

reg = nos << 5;

sys/arm/arm/pmap-v6.c

440

reg |= outer << 3;

sys/arm/arm/pmap-v6.c

442

reg |= (inner & 0x1) << 6;

sys/arm/arm/pmap-v6.c

443

reg |= (inner & 0x2) >> 1;

sys/arm/arm/pmap-v6.c

446

reg |= 1 << 1,

sys/arm/arm/pmap-v6.c

449

return reg;

sys/arm/arm/sp804.c

106

#define sp804_timer_tc_read_4(reg) \

sys/arm/arm/sp804.c

107

bus_space_read_4(sc->bst, sc->bsh, reg)

sys/arm/arm/sp804.c

109

#define sp804_timer_tc_write_4(reg, val) \

sys/arm/arm/sp804.c

110

bus_space_write_4(sc->bst, sc->bsh, reg, val)

sys/arm/arm/sp804.c

126

uint32_t count, reg;

sys/arm/arm/sp804.c

134

reg = TIMER_CONTROL_32BIT | TIMER_CONTROL_INTREN |

sys/arm/arm/sp804.c

137

sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg);

sys/arm/arm/sp804.c

153

uint32_t reg;

sys/arm/arm/sp804.c

156

reg = sp804_timer_tc_read_4(SP804_TIMER2_CONTROL);

sys/arm/arm/sp804.c

157

reg &= ~(TIMER_CONTROL_EN);

sys/arm/arm/sp804.c

158

sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg);

sys/arm/arm/sp804.c

201

uint32_t id, reg;

sys/arm/arm/sp804.c

254

reg = TIMER_CONTROL_PERIODIC | TIMER_CONTROL_32BIT;

sys/arm/arm/sp804.c

255

sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg);

sys/arm/arm/sp804.c

256

reg |= TIMER_CONTROL_EN;

sys/arm/arm/sp804.c

257

sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg);

sys/arm/arm/unwind.c

388

unsigned int mask, reg;

sys/arm/arm/unwind.c

405

for (reg = 4; mask && reg < 16; mask >>= 1, reg++) {

sys/arm/arm/unwind.c

411

state->registers[reg] = *vsp++;

sys/arm/arm/unwind.c

412

state->update_mask |= 1 << reg;

sys/arm/arm/unwind.c

415

if (reg == SP)

sys/arm/arm/unwind.c

428

unsigned int count, reg;

sys/arm/arm/unwind.c

443

for (reg = 4; reg <= 4 + count; reg++) {

sys/arm/arm/unwind.c

444

state->registers[reg] = *vsp++;

sys/arm/arm/unwind.c

445

state->update_mask |= 1 << reg;

sys/arm/arm/unwind.c

460

unsigned int mask, reg;

sys/arm/arm/unwind.c

473

for (reg = 0; mask && reg < 4; mask >>= 1, reg++) {

sys/arm/arm/unwind.c

478

state->registers[reg] = *vsp++;

sys/arm/arm/unwind.c

479

state->update_mask |= 1 << reg;

sys/arm/arm/vfp.c

84

#define fmxr(reg, val) \

sys/arm/arm/vfp.c

86

" vmsr " __STRING(reg) ", %0" :: "r"(val));

sys/arm/arm/vfp.c

88

#define fmrx(reg) \

sys/arm/arm/vfp.c

91

" vmrs %0, " __STRING(reg) : "=r"(val)); \

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

128

uint32_t reg;

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

131

reg = BCM_BSC_READ(sc, off);

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

132

reg &= ~mask;

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

133

reg |= value;

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

134

BCM_BSC_WRITE(sc, off, reg);

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

183

uint32_t clk, reg;

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

189

reg = BCM_BSC_READ(sc, BCM_BSC_DELAY);

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

191

reg >>= 16;

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

192

error = sysctl_handle_int(oidp, &reg, sizeof(reg), req);

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

199

if (reg > clk / 2)

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

200

reg = clk / 2 - 1;

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

201

bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16);

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

211

uint32_t clk, reg;

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

217

reg = BCM_BSC_READ(sc, BCM_BSC_DELAY);

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

219

reg &= 0xffff;

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

220

error = sysctl_handle_int(oidp, &reg, sizeof(reg), req);

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

227

if (reg > clk / 2)

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

228

reg = clk / 2 - 1;

sys/arm/broadcom/bcm2835/bcm2835_bsc.c

229

bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg);

sys/arm/broadcom/bcm2835/bcm2835_dma.c

220

uint32_t reg;

sys/arm/broadcom/bcm2835/bcm2835_dma.c

240

reg = bus_read_4(sc->sc_mem, BCM_DMA_ENABLE);

sys/arm/broadcom/bcm2835/bcm2835_dma.c

241

if ((reg & bcm_dma_channel_mask) != bcm_dma_channel_mask)

sys/arm/broadcom/bcm2835/bcm2835_dma.c

243

reg = bus_read_4(sc->sc_mem, BCM_DMA_INT_STATUS);

sys/arm/broadcom/bcm2835/bcm2835_dma.c

244

if ((reg & bcm_dma_channel_mask) != 0)

sys/arm/broadcom/bcm2835/bcm2835_dma.c

535

uint32_t reg;

sys/arm/broadcom/bcm2835/bcm2835_dma.c

545

reg = bus_read_4(sc->sc_mem, BCM_DMA_CH(ch) + i*4);

sys/arm/broadcom/bcm2835/bcm2835_dma.c

546

printf("%8.8x ", reg);

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

309

uint32_t reg;

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

323

reg = BCM_GPIO_READ(sc, BCM2711_GPIO_GPPUD(regid));

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

324

reg &= ~(BCM2711_GPIO_MASK << shift);

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

325

reg |= (state << shift);

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

326

BCM_GPIO_WRITE(sc, BCM2711_GPIO_GPPUD(regid), reg);

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

510

uint32_t bank, reg;

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

525

reg = BCM_GPIO_GPSET(bank);

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

527

reg = BCM_GPIO_GPCLR(bank);

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

528

BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin));

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

560

uint32_t bank, data, reg;

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

576

reg = BCM_GPIO_GPCLR(bank);

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

578

reg = BCM_GPIO_GPSET(bank);

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

579

BCM_GPIO_WRITE(sc, reg, BCM_GPIO_MASK(pin));

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

866

bcm_gpio_modify(struct bcm_gpio_softc *sc, uint32_t reg, uint32_t mask,

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

871

BCM_GPIO_SET_BITS(sc, reg, mask);

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

873

BCM_GPIO_CLEAR_BITS(sc, reg, mask);

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

955

uint32_t reg;

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

958

reg = BCM_GPIO_READ(sc, BCM_GPIO_GPEDS(bank));

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

959

while (reg != 0) {

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

960

irq = BCM_GPIO_PINS_PER_BANK * bank + ffs(reg) - 1;

sys/arm/broadcom/bcm2835/bcm2835_gpio.c

972

reg &= ~bgi->bgi_mask;

sys/arm/broadcom/bcm2835/bcm2835_intr.c

142

#define intc_read_4(_sc, reg) \

sys/arm/broadcom/bcm2835/bcm2835_intr.c

143

bus_space_read_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg))

sys/arm/broadcom/bcm2835/bcm2835_intr.c

144

#define intc_write_4(_sc, reg, val) \

sys/arm/broadcom/bcm2835/bcm2835_intr.c

145

bus_space_write_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg), (val))

sys/arm/broadcom/bcm2835/bcm2835_mbox.c

399

uint32_t reg;

sys/arm/broadcom/bcm2835/bcm2835_mbox.c

425

MBOX_READ(mbox, BCM2835_MBOX_CHAN_PROP, &reg);

sys/arm/broadcom/bcm2835/bcm2835_mbox.c

432

err = bcm2835_mbox_err(mbox, msg_phys, reg,

sys/arm/broadcom/bcm2835/bcm2835_mbox.c

90

#define mbox_read_4(sc, reg) \

sys/arm/broadcom/bcm2835/bcm2835_mbox.c

91

bus_space_read_4((sc)->bst, (sc)->bsh, reg)

sys/arm/broadcom/bcm2835/bcm2835_mbox.c

92

#define mbox_write_4(sc, reg, val) \

sys/arm/broadcom/bcm2835/bcm2835_mbox.c

93

bus_space_write_4((sc)->bst, (sc)->bsh, reg, val)

sys/arm/broadcom/bcm2835/bcm2835_pwm.c

334

uint32_t reg;

sys/arm/broadcom/bcm2835/bcm2835_pwm.c

338

reg = BCM_PWM_MEM_READ(sc, arg2 & 0xff);

sys/arm/broadcom/bcm2835/bcm2835_pwm.c

340

error = sysctl_handle_int(oidp, &reg, sizeof(reg), req);

sys/arm/broadcom/bcm2835/bcm2835_pwm.c

344

BCM_PWM_MEM_WRITE(sc, arg2, reg);

sys/arm/broadcom/bcm2835/bcm2835_sdhci.c

671

uint32_t reg;

sys/arm/broadcom/bcm2835/bcm2835_sdhci.c

694

reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS) &

sys/arm/broadcom/bcm2835/bcm2835_sdhci.c

696

if ((reg & DATA_PENDING_MASK) != 0 &&

sys/arm/broadcom/bcm2835/bcm2835_sdhci.c

709

} else if ((reg & SDHCI_INT_DATA_END) != 0) {

sys/arm/broadcom/bcm2835/bcm2835_sdhci.c

712

reg);

sys/arm/broadcom/bcm2835/bcm2835_spi.c

103

uint32_t reg;

sys/arm/broadcom/bcm2835/bcm2835_spi.c

106

reg = BCM_SPI_READ(sc, off);

sys/arm/broadcom/bcm2835/bcm2835_spi.c

107

reg &= ~mask;

sys/arm/broadcom/bcm2835/bcm2835_spi.c

108

reg |= value;

sys/arm/broadcom/bcm2835/bcm2835_spi.c

109

BCM_SPI_WRITE(sc, off, reg);

sys/arm/broadcom/bcm2835/bcm2835_spi.c

140

uint32_t reg;

sys/arm/broadcom/bcm2835/bcm2835_spi.c

145

reg = BCM_SPI_READ(sc, SPI_CS);

sys/arm/broadcom/bcm2835/bcm2835_spi.c

147

reg = (reg & bit) ? 1 : 0;

sys/arm/broadcom/bcm2835/bcm2835_spi.c

149

error = sysctl_handle_int(oidp, &reg, sizeof(reg), req);

sys/arm/broadcom/bcm2835/bcm2835_spi.c

70

uint32_t reg;

sys/arm/broadcom/bcm2835/bcm2835_spi.c

73

reg = BCM_SPI_READ(sc, SPI_CS);

sys/arm/broadcom/bcm2835/bcm2835_spi.c

74

device_printf(dev, "CS=%b\n", reg,

sys/arm/broadcom/bcm2835/bcm2835_spi.c

79

reg = BCM_SPI_READ(sc, SPI_CLK) & SPI_CLK_MASK;

sys/arm/broadcom/bcm2835/bcm2835_spi.c

80

if (reg % 2)

sys/arm/broadcom/bcm2835/bcm2835_spi.c

81

reg--;

sys/arm/broadcom/bcm2835/bcm2835_spi.c

82

if (reg == 0)

sys/arm/broadcom/bcm2835/bcm2835_spi.c

83

reg = 65536;

sys/arm/broadcom/bcm2835/bcm2835_spi.c

85

SPI_CORE_CLK / 1000000, reg, SPI_CORE_CLK / reg);

sys/arm/broadcom/bcm2835/bcm2835_spi.c

86

reg = BCM_SPI_READ(sc, SPI_DLEN) & SPI_DLEN_MASK;

sys/arm/broadcom/bcm2835/bcm2835_spi.c

87

device_printf(dev, "DLEN=%d\n", reg);

sys/arm/broadcom/bcm2835/bcm2835_spi.c

88

reg = BCM_SPI_READ(sc, SPI_LTOH) & SPI_LTOH_MASK;

sys/arm/broadcom/bcm2835/bcm2835_spi.c

89

device_printf(dev, "LTOH=%d\n", reg);

sys/arm/broadcom/bcm2835/bcm2835_spi.c

90

reg = BCM_SPI_READ(sc, SPI_DC);

sys/arm/broadcom/bcm2835/bcm2835_spi.c

92

(reg & SPI_DC_RPANIC_MASK) >> SPI_DC_RPANIC_SHIFT,

sys/arm/broadcom/bcm2835/bcm2835_spi.c

93

(reg & SPI_DC_RDREQ_MASK) >> SPI_DC_RDREQ_SHIFT,

sys/arm/broadcom/bcm2835/bcm2835_spi.c

94

(reg & SPI_DC_TPANIC_MASK) >> SPI_DC_TPANIC_SHIFT,

sys/arm/broadcom/bcm2835/bcm2835_spi.c

95

(reg & SPI_DC_TDREQ_MASK) >> SPI_DC_TDREQ_SHIFT);

sys/arm/broadcom/bcm2835/bcm2835_wdog.c

164

uint32_t ticks, reg;

sys/arm/broadcom/bcm2835/bcm2835_wdog.c

189

reg = (BCM2835_PASSWORD << BCM2835_PASSWORD_SHIFT) | ticks;

sys/arm/broadcom/bcm2835/bcm2835_wdog.c

190

WRITE(sc, BCM2835_WDOG_REG, reg);

sys/arm/broadcom/bcm2835/bcm2835_wdog.c

192

reg = READ(sc, BCM2835_RSTC_REG);

sys/arm/broadcom/bcm2835/bcm2835_wdog.c

193

reg &= BCM2835_RSTC_WRCFG_CLR;

sys/arm/broadcom/bcm2835/bcm2835_wdog.c

194

reg |= BCM2835_RSTC_WRCFG_FULL_RESET;

sys/arm/broadcom/bcm2835/bcm2835_wdog.c

195

reg |= (BCM2835_PASSWORD << BCM2835_PASSWORD_SHIFT);

sys/arm/broadcom/bcm2835/bcm2835_wdog.c

196

WRITE(sc, BCM2835_RSTC_REG, reg);

sys/arm/broadcom/bcm2835/bcm2836.c

171

#define bcm_lintc_read_4(sc, reg) \

sys/arm/broadcom/bcm2835/bcm2836.c

172

bus_space_read_4((sc)->bls_bst, (sc)->bls_bsh, (reg))

sys/arm/broadcom/bcm2835/bcm2836.c

173

#define bcm_lintc_write_4(sc, reg, val) \

sys/arm/broadcom/bcm2835/bcm2836.c

174

bus_space_write_4((sc)->bls_bst, (sc)->bls_bsh, (reg), (val))

sys/arm/broadcom/bcm2835/bcm2836.c

177

bcm_lintc_rwreg_clr(struct bcm_lintc_softc *sc, uint32_t reg,

sys/arm/broadcom/bcm2835/bcm2836.c

181

bcm_lintc_write_4(sc, reg, bcm_lintc_read_4(sc, reg) & ~mask);

sys/arm/broadcom/bcm2835/bcm2836.c

185

bcm_lintc_rwreg_set(struct bcm_lintc_softc *sc, uint32_t reg,

sys/arm/broadcom/bcm2835/bcm2836.c

189

bcm_lintc_write_4(sc, reg, bcm_lintc_read_4(sc, reg) | mask);

sys/arm/broadcom/bcm2835/bcm2836.c

391

uint32_t num, reg;

sys/arm/broadcom/bcm2835/bcm2836.c

399

reg = bcm_lintc_read_4(sc, BCM_LINTC_PENDING_REG(cpu));

sys/arm/broadcom/bcm2835/bcm2836.c

400

if ((reg & BCM_LINTC_PENDING_MASK) == 0)

sys/arm/broadcom/bcm2835/bcm2836.c

403

if (reg & BCM_LINTC_MBOX0_IRQ_MASK)

sys/arm/broadcom/bcm2835/bcm2836.c

406

if (reg & BCM_LINTC_TIMER0_IRQ_MASK)

sys/arm/broadcom/bcm2835/bcm2836.c

408

if (reg & BCM_LINTC_TIMER1_IRQ_MASK)

sys/arm/broadcom/bcm2835/bcm2836.c

410

if (reg & BCM_LINTC_TIMER2_IRQ_MASK)

sys/arm/broadcom/bcm2835/bcm2836.c

412

if (reg & BCM_LINTC_TIMER3_IRQ_MASK)

sys/arm/broadcom/bcm2835/bcm2836.c

414

if (reg & BCM_LINTC_GPU_IRQ_MASK)

sys/arm/broadcom/bcm2835/bcm2836.c

416

if (reg & BCM_LINTC_PMU_IRQ_MASK)

sys/arm/broadcom/bcm2835/bcm2836.c

421

reg &= ~BCM_LINTC_PENDING_MASK;

sys/arm/broadcom/bcm2835/bcm2836.c

422

if (reg != 0)

sys/arm/broadcom/bcm2835/bcm2836.c

423

device_printf(sc->bls_dev, "Unknown interrupt(s) %x\n", reg);

sys/arm/broadcom/bcm2835/bcm2836.c

521

uint32_t reg, uint32_t mask)

sys/arm/broadcom/bcm2835/bcm2836.c

525

bcm_lintc_rwreg_set(sc, reg, mask);

sys/arm/broadcom/bcm2835/bcm2838_pci.c

166

bcm_pcib_set_reg(struct bcm_pcib_softc *sc, uint32_t reg, uint32_t val)

sys/arm/broadcom/bcm2835/bcm2838_pci.c

169

bus_write_4(sc->base.base.res, reg, htole32(val));

sys/arm/broadcom/bcm2835/bcm2838_pci.c

173

bcm_pcib_read_reg(struct bcm_pcib_softc *sc, uint32_t reg)

sys/arm/broadcom/bcm2835/bcm2838_pci.c

176

return (le32toh(bus_read_4(sc->base.base.res, reg)));

sys/arm/broadcom/bcm2835/bcm2838_pci.c

267

u_int slot, u_int func, u_int reg)

sys/arm/broadcom/bcm2835/bcm2838_pci.c

281

return (reg);

sys/arm/broadcom/bcm2835/bcm2838_pci.c

287

return (REG_EP_CONFIG_DATA + reg);

sys/arm/broadcom/bcm2835/bcm2838_pci.c

292

u_int func, u_int reg)

sys/arm/broadcom/bcm2835/bcm2838_pci.c

297

if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))

sys/arm/broadcom/bcm2835/bcm2838_pci.c

313

bcm_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,

sys/arm/broadcom/bcm2835/bcm2838_pci.c

321

if (!bcm_pcib_is_valid_quad(sc, bus, slot, func, reg))

sys/arm/broadcom/bcm2835/bcm2838_pci.c

325

offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg);

sys/arm/broadcom/bcm2835/bcm2838_pci.c

348

u_int func, u_int reg, uint32_t val, int bytes)

sys/arm/broadcom/bcm2835/bcm2838_pci.c

354

if (!bcm_pcib_is_valid_quad(sc, bus, slot, func, reg))

sys/arm/broadcom/bcm2835/bcm2838_pci.c

358

offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg);

sys/arm/freescale/imx/imx6_anatop.c

749

int reg;

sys/arm/freescale/imx/imx6_anatop.c

756

reg = (IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE);

sys/arm/freescale/imx/imx6_anatop.c

757

reg &= ~(IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK << \

sys/arm/freescale/imx/imx6_anatop.c

759

reg |= (mfi << IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT);

sys/arm/freescale/imx/imx6_anatop.c

760

imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO, reg);

sys/arm/freescale/imx/imx6_audmux.c

101

uint32_t reg;

sys/arm/freescale/imx/imx6_audmux.c

104

reg = (PTCR_TFS_DIR | PTCR_TCLKDIR | PTCR_SYN);

sys/arm/freescale/imx/imx6_audmux.c

105

WRITE4(sc, AUDMUX_PTCR(audmux_port), reg);

sys/arm/freescale/imx/imx6_audmux.c

108

reg = (PDCR_RXDSEL_PORT(ssi_port) << PDCR_RXDSEL_S);

sys/arm/freescale/imx/imx6_audmux.c

109

WRITE4(sc, AUDMUX_PDCR(audmux_port), reg);

sys/arm/freescale/imx/imx6_ccm.c

100

WR4(sc, CCM_CCGR1, reg);

sys/arm/freescale/imx/imx6_ccm.c

103

reg = CCGR2_I2C1 | CCGR2_I2C2 | CCGR2_I2C3 | CCGR2_IIM |

sys/arm/freescale/imx/imx6_ccm.c

107

WR4(sc, CCM_CCGR2, reg);

sys/arm/freescale/imx/imx6_ccm.c

110

reg = CCGR3_OCRAM | CCGR3_MMDC_CORE_IPG |

sys/arm/freescale/imx/imx6_ccm.c

112

WR4(sc, CCM_CCGR3, reg);

sys/arm/freescale/imx/imx6_ccm.c

115

reg = CCGR4_PL301_MX6QFAST1_S133 |

sys/arm/freescale/imx/imx6_ccm.c

117

WR4(sc, CCM_CCGR4, reg);

sys/arm/freescale/imx/imx6_ccm.c

120

reg = CCGR5_SDMA | CCGR5_SSI1 | CCGR5_SSI2 | CCGR5_SSI3 |

sys/arm/freescale/imx/imx6_ccm.c

122

WR4(sc, CCM_CCGR5, reg);

sys/arm/freescale/imx/imx6_ccm.c

125

reg = CCGR6_USBOH3 | CCGR6_USDHC1 | CCGR6_USDHC2 |

sys/arm/freescale/imx/imx6_ccm.c

127

WR4(sc, CCM_CCGR6, reg);

sys/arm/freescale/imx/imx6_ccm.c

148

uint32_t reg;

sys/arm/freescale/imx/imx6_ccm.c

177

reg = RD4(sc, CCM_CGPR);

sys/arm/freescale/imx/imx6_ccm.c

178

reg |= CCM_CGPR_INT_MEM_CLK_LPM;

sys/arm/freescale/imx/imx6_ccm.c

179

WR4(sc, CCM_CGPR, reg);

sys/arm/freescale/imx/imx6_ccm.c

180

reg = RD4(sc, CCM_CLPCR);

sys/arm/freescale/imx/imx6_ccm.c

181

reg = (reg & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM_RUN;

sys/arm/freescale/imx/imx6_ccm.c

182

WR4(sc, CCM_CLPCR, reg);

sys/arm/freescale/imx/imx6_ccm.c

215

uint32_t reg;

sys/arm/freescale/imx/imx6_ccm.c

224

reg = RD4(sc, CCM_CSCMR1);

sys/arm/freescale/imx/imx6_ccm.c

225

reg &= ~(SSI_CLK_SEL_M << SSI1_CLK_SEL_S);

sys/arm/freescale/imx/imx6_ccm.c

226

reg |= (SSI_CLK_SEL_PLL4 << SSI1_CLK_SEL_S);

sys/arm/freescale/imx/imx6_ccm.c

227

reg &= ~(SSI_CLK_SEL_M << SSI2_CLK_SEL_S);

sys/arm/freescale/imx/imx6_ccm.c

228

reg |= (SSI_CLK_SEL_PLL4 << SSI2_CLK_SEL_S);

sys/arm/freescale/imx/imx6_ccm.c

229

reg &= ~(SSI_CLK_SEL_M << SSI3_CLK_SEL_S);

sys/arm/freescale/imx/imx6_ccm.c

230

reg |= (SSI_CLK_SEL_PLL4 << SSI3_CLK_SEL_S);

sys/arm/freescale/imx/imx6_ccm.c

231

WR4(sc, CCM_CSCMR1, reg);

sys/arm/freescale/imx/imx6_ccm.c

239

reg = RD4(sc, CCM_CS1CDR);

sys/arm/freescale/imx/imx6_ccm.c

241

reg &= ~(SSI_CLK_PODF_MASK << SSI1_CLK_PODF_SHIFT);

sys/arm/freescale/imx/imx6_ccm.c

242

reg &= ~(SSI_CLK_PODF_MASK << SSI3_CLK_PODF_SHIFT);

sys/arm/freescale/imx/imx6_ccm.c

243

reg |= (0x1 << SSI1_CLK_PODF_SHIFT);

sys/arm/freescale/imx/imx6_ccm.c

244

reg |= (0x1 << SSI3_CLK_PODF_SHIFT);

sys/arm/freescale/imx/imx6_ccm.c

246

reg &= ~(SSI_CLK_PRED_MASK << SSI1_CLK_PRED_SHIFT);

sys/arm/freescale/imx/imx6_ccm.c

247

reg &= ~(SSI_CLK_PRED_MASK << SSI3_CLK_PRED_SHIFT);

sys/arm/freescale/imx/imx6_ccm.c

248

reg |= (0x3 << SSI1_CLK_PRED_SHIFT);

sys/arm/freescale/imx/imx6_ccm.c

249

reg |= (0x3 << SSI3_CLK_PRED_SHIFT);

sys/arm/freescale/imx/imx6_ccm.c

250

WR4(sc, CCM_CS1CDR, reg);

sys/arm/freescale/imx/imx6_ccm.c

253

reg = RD4(sc, CCM_CS2CDR);

sys/arm/freescale/imx/imx6_ccm.c

255

reg &= ~(SSI_CLK_PODF_MASK << SSI2_CLK_PODF_SHIFT);

sys/arm/freescale/imx/imx6_ccm.c

256

reg |= (0x1 << SSI2_CLK_PODF_SHIFT);

sys/arm/freescale/imx/imx6_ccm.c

258

reg &= ~(SSI_CLK_PRED_MASK << SSI2_CLK_PRED_SHIFT);

sys/arm/freescale/imx/imx6_ccm.c

259

reg |= (0x3 << SSI2_CLK_PRED_SHIFT);

sys/arm/freescale/imx/imx6_ccm.c

260

WR4(sc, CCM_CS2CDR, reg);

sys/arm/freescale/imx/imx6_ccm.c

397

uint32_t reg;

sys/arm/freescale/imx/imx6_ccm.c

401

reg = RD4(ccm_sc, CCM_ANALOG_PLL_VIDEO);

sys/arm/freescale/imx/imx6_ccm.c

402

reg &= ~CCM_ANALOG_PLL_VIDEO_POWERDOWN;

sys/arm/freescale/imx/imx6_ccm.c

403

WR4(ccm_sc, CCM_ANALOG_PLL_VIDEO, reg);

sys/arm/freescale/imx/imx6_ccm.c

409

reg &= ~CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK;

sys/arm/freescale/imx/imx6_ccm.c

410

reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_2;

sys/arm/freescale/imx/imx6_ccm.c

411

reg &= ~CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK;

sys/arm/freescale/imx/imx6_ccm.c

412

reg |= 37 << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT;

sys/arm/freescale/imx/imx6_ccm.c

413

WR4(ccm_sc, CCM_ANALOG_PLL_VIDEO, reg);

sys/arm/freescale/imx/imx6_ccm.c

419

reg = RD4(ccm_sc, CCM_ANALOG_PLL_VIDEO);

sys/arm/freescale/imx/imx6_ccm.c

420

reg &= ~CCM_ANALOG_PLL_VIDEO_POWERDOWN;

sys/arm/freescale/imx/imx6_ccm.c

421

WR4(ccm_sc, CCM_ANALOG_PLL_VIDEO, reg);

sys/arm/freescale/imx/imx6_ccm.c

434

reg |= CCM_ANALOG_PLL_VIDEO_ENABLE;

sys/arm/freescale/imx/imx6_ccm.c

435

reg &= ~CCM_ANALOG_PLL_VIDEO_BYPASS;

sys/arm/freescale/imx/imx6_ccm.c

436

WR4(ccm_sc, CCM_ANALOG_PLL_VIDEO, reg);

sys/arm/freescale/imx/imx6_ccm.c

445

uint32_t reg;

sys/arm/freescale/imx/imx6_ccm.c

448

reg = RD4(sc, CCM_CCGR3);

sys/arm/freescale/imx/imx6_ccm.c

450

reg |= CCGR3_IPU1_IPU | CCGR3_IPU1_DI0;

sys/arm/freescale/imx/imx6_ccm.c

452

reg |= CCGR3_IPU2_IPU | CCGR3_IPU2_DI0;

sys/arm/freescale/imx/imx6_ccm.c

453

WR4(sc, CCM_CCGR3, reg);

sys/arm/freescale/imx/imx6_ccm.c

456

reg = RD4(sc, CCM_CHSCCDR);

sys/arm/freescale/imx/imx6_ccm.c

457

reg &= ~(CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |

sys/arm/freescale/imx/imx6_ccm.c

459

reg |= (CHSCCDR_PODF_DIVIDE_BY_3 << CHSCCDR_IPU1_DI0_PODF_SHIFT);

sys/arm/freescale/imx/imx6_ccm.c

460

reg |= (CHSCCDR_IPU_PRE_CLK_PLL5 << CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT);

sys/arm/freescale/imx/imx6_ccm.c

461

WR4(sc, CCM_CHSCCDR, reg);

sys/arm/freescale/imx/imx6_ccm.c

463

reg |= (CHSCCDR_CLK_SEL_PREMUXED << CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT);

sys/arm/freescale/imx/imx6_ccm.c

464

WR4(sc, CCM_CHSCCDR, reg);

sys/arm/freescale/imx/imx6_ccm.c

478

uint32_t reg;

sys/arm/freescale/imx/imx6_ccm.c

481

reg = RD4(sc, CCM_CCGR2);

sys/arm/freescale/imx/imx6_ccm.c

482

reg |= CCGR2_HDMI_TX | CCGR2_HDMI_TX_ISFR;

sys/arm/freescale/imx/imx6_ccm.c

483

WR4(sc, CCM_CCGR2, reg);

sys/arm/freescale/imx/imx6_ccm.c

91

uint32_t reg;

sys/arm/freescale/imx/imx6_ccm.c

94

reg = CCGR0_AIPS_TZ1 | CCGR0_AIPS_TZ2 | CCGR0_ABPHDMA;

sys/arm/freescale/imx/imx6_ccm.c

95

WR4(sc, CCM_CCGR0, reg);

sys/arm/freescale/imx/imx6_ccm.c

98

reg = CCGR1_ENET | CCGR1_EPIT1 | CCGR1_GPT | CCGR1_ECSPI1 |

sys/arm/freescale/imx/imx6_ipu.c

1023

reg = IPU_READ4(sc, IPU_CONF);

sys/arm/freescale/imx/imx6_ipu.c

1024

reg |= IPU_CONF_DMFC_EN | IPU_CONF_DC_EN | IPU_CONF_DP_EN;

sys/arm/freescale/imx/imx6_ipu.c

1025

IPU_WRITE4(sc, IPU_CONF, reg);

sys/arm/freescale/imx/imx6_ipu.c

1033

reg = IPU_READ4(sc, off);

sys/arm/freescale/imx/imx6_ipu.c

1034

reg |= (1 << (DMA_CHANNEL & 0x1f));

sys/arm/freescale/imx/imx6_ipu.c

1035

IPU_WRITE4(sc, off, reg);

sys/arm/freescale/imx/imx6_ipu.c

509

uint32_t flag, reg;

sys/arm/freescale/imx/imx6_ipu.c

512

reg = IPU_READ4(sc, IPU_DISP_GEN);

sys/arm/freescale/imx/imx6_ipu.c

513

reg |= flag;

sys/arm/freescale/imx/imx6_ipu.c

514

IPU_WRITE4(sc, IPU_DISP_GEN, reg);

sys/arm/freescale/imx/imx6_ipu.c

522

uint32_t addr, reg;

sys/arm/freescale/imx/imx6_ipu.c

526

reg = DI_RUN_VALUE_M1(run_value) |

sys/arm/freescale/imx/imx6_ipu.c

529

IPU_WRITE4(sc, addr, reg);

sys/arm/freescale/imx/imx6_ipu.c

540

uint32_t addr, reg;

sys/arm/freescale/imx/imx6_ipu.c

544

reg = DI_CNT_POLARITY_GEN_EN(cnt_polarity_gen_en) |

sys/arm/freescale/imx/imx6_ipu.c

548

reg |= DI_CNT_DOWN(cnt_down) | cnt_up;

sys/arm/freescale/imx/imx6_ipu.c

550

reg |= DI_CNT_AUTO_RELOAD;

sys/arm/freescale/imx/imx6_ipu.c

551

IPU_WRITE4(sc, addr, reg);

sys/arm/freescale/imx/imx6_ipu.c

555

reg = IPU_READ4(sc, addr);

sys/arm/freescale/imx/imx6_ipu.c

557

reg &= ~(0xffff);

sys/arm/freescale/imx/imx6_ipu.c

558

reg |= repeat_count;

sys/arm/freescale/imx/imx6_ipu.c

561

reg &= ~(0xffff << 16);

sys/arm/freescale/imx/imx6_ipu.c

562

reg |= (repeat_count << 16);

sys/arm/freescale/imx/imx6_ipu.c

564

IPU_WRITE4(sc, addr, reg);

sys/arm/freescale/imx/imx6_ipu.c

571

uint32_t addr, reg;

sys/arm/freescale/imx/imx6_ipu.c

583

reg = IPU_READ4(sc, addr);

sys/arm/freescale/imx/imx6_ipu.c

585

reg &= ~(0xffff);

sys/arm/freescale/imx/imx6_ipu.c

587

reg &= ~(0xffff << 16);

sys/arm/freescale/imx/imx6_ipu.c

588

IPU_WRITE4(sc, addr, reg);

sys/arm/freescale/imx/imx6_ipu.c

777

uint32_t reg;

sys/arm/freescale/imx/imx6_ipu.c

788

reg = IPU_READ4(sc, offset);

sys/arm/freescale/imx/imx6_ipu.c

789

reg &= ~(0xFFFF << shift);

sys/arm/freescale/imx/imx6_ipu.c

790

reg |= ((addr << 8) | priority) << shift;

sys/arm/freescale/imx/imx6_ipu.c

791

IPU_WRITE4(sc, offset, reg);

sys/arm/freescale/imx/imx6_ipu.c

798

uint32_t reg, shift, ptr;

sys/arm/freescale/imx/imx6_ipu.c

802

reg = IPU_READ4(sc, DC_MAP_CONF_VAL(ptr));

sys/arm/freescale/imx/imx6_ipu.c

807

reg &= ~(0xffff << shift);

sys/arm/freescale/imx/imx6_ipu.c

808

reg |= ((offset << 8) | mask) << shift;

sys/arm/freescale/imx/imx6_ipu.c

809

IPU_WRITE4(sc, DC_MAP_CONF_VAL(ptr), reg);

sys/arm/freescale/imx/imx6_ipu.c

811

reg = IPU_READ4(sc, DC_MAP_CONF_PTR(map));

sys/arm/freescale/imx/imx6_ipu.c

816

reg &= ~(MAP_CONF_PTR_MASK << shift);

sys/arm/freescale/imx/imx6_ipu.c

817

reg |= (ptr) << shift;

sys/arm/freescale/imx/imx6_ipu.c

818

IPU_WRITE4(sc, DC_MAP_CONF_PTR(map), reg);

sys/arm/freescale/imx/imx6_ipu.c

824

uint32_t reg, shift;

sys/arm/freescale/imx/imx6_ipu.c

826

reg = IPU_READ4(sc, DC_MAP_CONF_VAL(map));

sys/arm/freescale/imx/imx6_ipu.c

83

#define IPU_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, (reg))

sys/arm/freescale/imx/imx6_ipu.c

831

reg &= ~(MAP_CONF_VAL_MASK << shift);

sys/arm/freescale/imx/imx6_ipu.c

832

IPU_WRITE4(sc, DC_MAP_CONF_VAL(map), reg);

sys/arm/freescale/imx/imx6_ipu.c

84

#define IPU_WRITE4(_sc, reg, value) \

sys/arm/freescale/imx/imx6_ipu.c

85

bus_write_4((_sc)->sc_mem_res, (reg), (value))

sys/arm/freescale/imx/imx6_ipu.c

870

uint32_t reg, db_mode_sel, cur_buf;

sys/arm/freescale/imx/imx6_ipu.c

935

reg = IPU_READ4(sc, DMFC_GENERAL_1);

sys/arm/freescale/imx/imx6_ipu.c

936

reg &= ~(DMFC_GENERAL_1_WAIT4EOT_5B);

sys/arm/freescale/imx/imx6_ipu.c

937

IPU_WRITE4(sc, DMFC_GENERAL_1, reg);

sys/arm/freescale/imx/imx6_ipu.c

950

reg = IPU_READ4(sc, db_mode_sel);

sys/arm/freescale/imx/imx6_ipu.c

951

reg |= (1UL << (DMA_CHANNEL & 0x1f));

sys/arm/freescale/imx/imx6_ipu.c

952

IPU_WRITE4(sc, db_mode_sel, reg);

sys/arm/freescale/imx/imx6_ipu.c

960

uint32_t reg, off;

sys/arm/freescale/imx/imx6_pl310.c

52

uint32_t reg;

sys/arm/freescale/imx/imx6_pl310.c

59

reg = pl310_read4(sc, PL310_POWER_CTRL);

sys/arm/freescale/imx/imx6_pl310.c

60

reg |= POWER_CTRL_ENABLE_GATING | POWER_CTRL_ENABLE_STANDBY;

sys/arm/freescale/imx/imx6_pl310.c

61

pl310_write4(sc, PL310_POWER_CTRL, reg);

sys/arm/freescale/imx/imx6_sdma.c

211

int reg;

sys/arm/freescale/imx/imx6_sdma.c

214

reg = READ4(sc, SDMAARM_EVTOVR);

sys/arm/freescale/imx/imx6_sdma.c

216

reg |= (1 << chn);

sys/arm/freescale/imx/imx6_sdma.c

218

reg &= ~(1 << chn);

sys/arm/freescale/imx/imx6_sdma.c

219

WRITE4(sc, SDMAARM_EVTOVR, reg);

sys/arm/freescale/imx/imx6_sdma.c

222

reg = READ4(sc, SDMAARM_HOSTOVR);

sys/arm/freescale/imx/imx6_sdma.c

224

reg |= (1 << chn);

sys/arm/freescale/imx/imx6_sdma.c

226

reg &= ~(1 << chn);

sys/arm/freescale/imx/imx6_sdma.c

227

WRITE4(sc, SDMAARM_HOSTOVR, reg);

sys/arm/freescale/imx/imx6_sdma.c

230

reg = READ4(sc, SDMAARM_DSPOVR);

sys/arm/freescale/imx/imx6_sdma.c

232

reg |= (1 << chn);

sys/arm/freescale/imx/imx6_sdma.c

234

reg &= ~(1 << chn);

sys/arm/freescale/imx/imx6_sdma.c

235

WRITE4(sc, SDMAARM_DSPOVR, reg);

sys/arm/freescale/imx/imx6_src.c

73

uint32_t reg;

sys/arm/freescale/imx/imx6_src.c

79

reg = RD4(src_sc, SRC_SCR);

sys/arm/freescale/imx/imx6_src.c

80

reg |= SW_IPU1_RST;

sys/arm/freescale/imx/imx6_src.c

81

WR4(src_sc, SRC_SCR, reg);

sys/arm/freescale/imx/imx6_src.c

84

reg = RD4(src_sc, SRC_SCR);

sys/arm/freescale/imx/imx6_src.c

85

if (reg & SW_IPU1_RST)

sys/arm/freescale/imx/imx6_ssi.c

520

int reg;

sys/arm/freescale/imx/imx6_ssi.c

530

reg = (SIER_TDMAE);

sys/arm/freescale/imx/imx6_ssi.c

531

WRITE4(sc, SSI_SIER, reg);

sys/arm/freescale/imx/imx6_ssi.c

542

int reg;

sys/arm/freescale/imx/imx6_ssi.c

546

reg = READ4(sc, SSI_SIER);

sys/arm/freescale/imx/imx6_ssi.c

547

reg &= ~(SIER_TDMAE);

sys/arm/freescale/imx/imx6_ssi.c

548

WRITE4(sc, SSI_SIER, reg);

sys/arm/freescale/imx/imx6_ssi.c

674

int reg;

sys/arm/freescale/imx/imx6_ssi.c

676

reg = READ4(sc, SSI_STCCR);

sys/arm/freescale/imx/imx6_ssi.c

677

reg &= ~(WL3_WL0_M << WL3_WL0_S);

sys/arm/freescale/imx/imx6_ssi.c

678

reg |= (0xb << WL3_WL0_S); /* 24 bit */

sys/arm/freescale/imx/imx6_ssi.c

679

reg &= ~(DC4_DC0_M << DC4_DC0_S);

sys/arm/freescale/imx/imx6_ssi.c

680

reg |= (1 << DC4_DC0_S); /* 2 words per frame */

sys/arm/freescale/imx/imx6_ssi.c

681

reg &= ~(STCCR_DIV2); /* Divide by 1 */

sys/arm/freescale/imx/imx6_ssi.c

682

reg &= ~(STCCR_PSR); /* Divide by 1 */

sys/arm/freescale/imx/imx6_ssi.c

683

reg &= ~(PM7_PM0_M << PM7_PM0_S);

sys/arm/freescale/imx/imx6_ssi.c

684

reg |= (1 << PM7_PM0_S); /* Divide by 2 */

sys/arm/freescale/imx/imx6_ssi.c

685

WRITE4(sc, SSI_STCCR, reg);

sys/arm/freescale/imx/imx6_ssi.c

687

reg = READ4(sc, SSI_SFCSR);

sys/arm/freescale/imx/imx6_ssi.c

688

reg &= ~(SFCSR_TFWM0_M << SFCSR_TFWM0_S);

sys/arm/freescale/imx/imx6_ssi.c

689

reg |= (8 << SFCSR_TFWM0_S); /* empty slots */

sys/arm/freescale/imx/imx6_ssi.c

690

WRITE4(sc, SSI_SFCSR, reg);

sys/arm/freescale/imx/imx6_ssi.c

692

reg = READ4(sc, SSI_STCR);

sys/arm/freescale/imx/imx6_ssi.c

693

reg |= (STCR_TFEN0);

sys/arm/freescale/imx/imx6_ssi.c

694

reg &= ~(STCR_TFEN1);

sys/arm/freescale/imx/imx6_ssi.c

695

reg &= ~(STCR_TSHFD); /* MSB */

sys/arm/freescale/imx/imx6_ssi.c

696

reg |= (STCR_TXBIT0);

sys/arm/freescale/imx/imx6_ssi.c

697

reg |= (STCR_TXDIR | STCR_TFDIR);

sys/arm/freescale/imx/imx6_ssi.c

698

reg |= (STCR_TSCKP); /* falling edge */

sys/arm/freescale/imx/imx6_ssi.c

699

reg |= (STCR_TFSI);

sys/arm/freescale/imx/imx6_ssi.c

700

reg &= ~(STCR_TFSI); /* active high frame sync */

sys/arm/freescale/imx/imx6_ssi.c

701

reg &= ~(STCR_TFSL);

sys/arm/freescale/imx/imx6_ssi.c

702

reg |= STCR_TEFS;

sys/arm/freescale/imx/imx6_ssi.c

703

WRITE4(sc, SSI_STCR, reg);

sys/arm/freescale/imx/imx6_ssi.c

705

reg = READ4(sc, SSI_SCR);

sys/arm/freescale/imx/imx6_ssi.c

706

reg &= ~(SCR_I2S_MODE_M << SCR_I2S_MODE_S); /* Not master */

sys/arm/freescale/imx/imx6_ssi.c

707

reg |= (SCR_SSIEN | SCR_TE);

sys/arm/freescale/imx/imx6_ssi.c

708

reg |= (SCR_NET);

sys/arm/freescale/imx/imx6_ssi.c

709

reg |= (SCR_SYN);

sys/arm/freescale/imx/imx6_ssi.c

710

WRITE4(sc, SSI_SCR, reg);

sys/arm/freescale/imx/imx_gpio.c

324

u_int icfg, irq, reg, shift, wrk;

sys/arm/freescale/imx/imx_gpio.c

374

reg = IMX_GPIO_ICR1_REG;

sys/arm/freescale/imx/imx_gpio.c

377

reg = IMX_GPIO_ICR2_REG;

sys/arm/freescale/imx/imx_gpio.c

380

wrk = READ4(sc, reg);

sys/arm/freescale/imx/imx_gpio.c

383

WRITE4(sc, reg, wrk);

sys/arm/freescale/imx/imx_i2c.c

659

int error, reg;

sys/arm/freescale/imx/imx_i2c.c

695

reg = i2c_read_reg(sc, I2C_DATA_REG);

sys/arm/freescale/imx/imx_i2c.c

696

DEBUGF(sc, 1, "0x%02x ", reg);

sys/arm/freescale/imx/imx_i2c.c

697

*buf++ = reg;

sys/arm/freescale/imx/imx_iomux.c

119

iomux_configure_input(struct iomux_softc *sc, uint32_t reg, uint32_t val)

sys/arm/freescale/imx/imx_iomux.c

124

if (reg == 0 && val == 0)

sys/arm/freescale/imx/imx_iomux.c

139

val = (RD4(sc, reg) & ~mask) | (select << shift);

sys/arm/freescale/imx/imx_iomux.c

141

WR4(sc, reg, val);

sys/arm/freescale/imx/imx_spi.c

231

uint32_t reg;

sys/arm/freescale/imx/imx_spi.c

247

reg = 0;

sys/arm/freescale/imx/imx_spi.c

249

reg |= 1u << CFGREG_SSPOL_SHIFT;

sys/arm/freescale/imx/imx_spi.c

251

reg |= 1u << CFGREG_SCLKPHA_SHIFT;

sys/arm/freescale/imx/imx_spi.c

253

reg |= 1u << CFGREG_SCLKPOL_SHIFT;

sys/arm/freescale/imx/imx_spi.c

254

reg |= 1u << CFGREG_SCLKCTL_SHIFT;

sys/arm/freescale/imx/imx_spi.c

256

WR4(sc, ECSPI_CFGREG, reg);

sys/arm/freescale/imx/imx_spi.c

261

reg = (FIFO_RXTHRESH << DMA_RX_THRESH_SHIFT);

sys/arm/freescale/imx/imx_spi.c

262

reg |= (FIFO_TXTHRESH << DMA_TX_THRESH_SHIFT);

sys/arm/freescale/imx/imx_spi.c

263

WR4(sc, ECSPI_DMAREG, reg);

sys/arm/freescale/imx/imx_wdog.c

103

uint16_t reg;

sys/arm/freescale/imx/imx_wdog.c

111

reg = RD2(sc, WDOG_CR_REG);

sys/arm/freescale/imx/imx_wdog.c

112

reg &= ~WDOG_CR_WT_MASK;

sys/arm/freescale/imx/imx_wdog.c

113

reg |= ((2 * timeout - 1) << WDOG_CR_WT_SHIFT);

sys/arm/freescale/imx/imx_wdog.c

114

WR2(sc, WDOG_CR_REG, reg | WDOG_CR_WDE);

sys/arm/freescale/imx/imx_wdog.c

122

reg = RD2(sc, WDOG_MCR_REG);

sys/arm/freescale/imx/imx_wdog.c

123

WR2(sc, WDOG_MCR_REG, reg & ~WDOG_MCR_PDE);

sys/arm/freescale/vybrid/vf_adc.c

162

int reg;

sys/arm/freescale/vybrid/vf_adc.c

168

reg = READ4(sc, ADC_HC0);

sys/arm/freescale/vybrid/vf_adc.c

169

reg &= ~(HC_ADCH_M << HC_ADCH_S);

sys/arm/freescale/vybrid/vf_adc.c

170

reg |= (channel << HC_ADCH_S);

sys/arm/freescale/vybrid/vf_adc.c

171

WRITE4(sc, ADC_HC0, reg);

sys/arm/freescale/vybrid/vf_adc.c

181

int reg;

sys/arm/freescale/vybrid/vf_adc.c

205

reg = READ4(sc, ADC_CFG);

sys/arm/freescale/vybrid/vf_adc.c

206

reg &= ~(CFG_MODE_M << CFG_MODE_S);

sys/arm/freescale/vybrid/vf_adc.c

207

reg |= (CFG_MODE_12 << CFG_MODE_S); /* 12bit */

sys/arm/freescale/vybrid/vf_adc.c

208

WRITE4(sc, ADC_CFG, reg);

sys/arm/freescale/vybrid/vf_adc.c

211

reg = READ4(sc, ADC_GC);

sys/arm/freescale/vybrid/vf_adc.c

212

reg |= (GC_ADCO | GC_AVGE);

sys/arm/freescale/vybrid/vf_adc.c

213

WRITE4(sc, ADC_GC, reg);

sys/arm/freescale/vybrid/vf_adc.c

216

reg = READ4(sc, ADC_HC0);

sys/arm/freescale/vybrid/vf_adc.c

217

reg &= HC_AIEN;

sys/arm/freescale/vybrid/vf_adc.c

218

WRITE4(sc, ADC_HC0, reg);

sys/arm/freescale/vybrid/vf_anadig.c

132

int reg;

sys/arm/freescale/vybrid/vf_anadig.c

134

reg = READ4(sc, pll_ctrl);

sys/arm/freescale/vybrid/vf_anadig.c

135

reg &= ~(CTRL_BYPASS | CTRL_PWR);

sys/arm/freescale/vybrid/vf_anadig.c

138

reg |= (CTRL_PWR | EN_USB_CLKS);

sys/arm/freescale/vybrid/vf_anadig.c

140

WRITE4(sc, pll_ctrl, reg);

sys/arm/freescale/vybrid/vf_anadig.c

146

reg = READ4(sc, pll_ctrl);

sys/arm/freescale/vybrid/vf_anadig.c

147

reg |= (CTRL_PLL_EN);

sys/arm/freescale/vybrid/vf_anadig.c

148

WRITE4(sc, pll_ctrl, reg);

sys/arm/freescale/vybrid/vf_anadig.c

157

int reg;

sys/arm/freescale/vybrid/vf_anadig.c

165

reg = READ4(sc, ANADIG_PLL4_CTRL);

sys/arm/freescale/vybrid/vf_anadig.c

166

reg &= ~(PLL4_CTRL_DIV_SEL_M << PLL4_CTRL_DIV_SEL_S);

sys/arm/freescale/vybrid/vf_anadig.c

167

reg |= (mfi << PLL4_CTRL_DIV_SEL_S);

sys/arm/freescale/vybrid/vf_anadig.c

168

WRITE4(sc, ANADIG_PLL4_CTRL, reg);

sys/arm/freescale/vybrid/vf_anadig.c

179

int reg;

sys/arm/freescale/vybrid/vf_anadig.c

206

reg = READ4(sc, ANADIG_REG_3P0);

sys/arm/freescale/vybrid/vf_anadig.c

207

reg |= (ENABLE_LINREG);

sys/arm/freescale/vybrid/vf_anadig.c

208

WRITE4(sc, ANADIG_REG_3P0, reg);

sys/arm/freescale/vybrid/vf_anadig.c

211

reg = READ4(sc, USB_MISC(0));

sys/arm/freescale/vybrid/vf_anadig.c

212

reg |= (EN_CLK_TO_UTMI);

sys/arm/freescale/vybrid/vf_anadig.c

213

WRITE4(sc, USB_MISC(0), reg);

sys/arm/freescale/vybrid/vf_anadig.c

215

reg = READ4(sc, USB_MISC(1));

sys/arm/freescale/vybrid/vf_anadig.c

216

reg |= (EN_CLK_TO_UTMI);

sys/arm/freescale/vybrid/vf_anadig.c

217

WRITE4(sc, USB_MISC(1), reg);

sys/arm/freescale/vybrid/vf_ccm.c

154

uint32_t reg;

sys/arm/freescale/vybrid/vf_ccm.c

166

.reg = CCM_CACRR,

sys/arm/freescale/vybrid/vf_ccm.c

190

.reg = CCM_CACRR,

sys/arm/freescale/vybrid/vf_ccm.c

202

.reg = CCM_CSCDR1,

sys/arm/freescale/vybrid/vf_ccm.c

214

.reg = CCM_CCOSR,

sys/arm/freescale/vybrid/vf_ccm.c

226

.reg = CCM_CSCDR2,

sys/arm/freescale/vybrid/vf_ccm.c

238

.reg = CCM_CSCDR2,

sys/arm/freescale/vybrid/vf_ccm.c

250

.reg = CCM_CSCDR3,

sys/arm/freescale/vybrid/vf_ccm.c

262

.reg = CCM_CSCDR3,

sys/arm/freescale/vybrid/vf_ccm.c

274

.reg = CCM_CSCDR1,

sys/arm/freescale/vybrid/vf_ccm.c

286

.reg = CCM_CSCDR2,

sys/arm/freescale/vybrid/vf_ccm.c

306

.reg = CCM_CSCDR2,

sys/arm/freescale/vybrid/vf_ccm.c

367

int reg;

sys/arm/freescale/vybrid/vf_ccm.c

377

reg = READ4(sc, clk->sel_reg);

sys/arm/freescale/vybrid/vf_ccm.c

378

reg &= ~(clk->sel_mask << clk->sel_shift);

sys/arm/freescale/vybrid/vf_ccm.c

379

reg |= (clk->sel_val << clk->sel_shift);

sys/arm/freescale/vybrid/vf_ccm.c

380

WRITE4(sc, clk->sel_reg, reg);

sys/arm/freescale/vybrid/vf_ccm.c

383

reg = READ4(sc, clk->reg);

sys/arm/freescale/vybrid/vf_ccm.c

384

reg |= clk->enable_reg;

sys/arm/freescale/vybrid/vf_ccm.c

385

reg &= ~(clk->div_mask << clk->div_shift);

sys/arm/freescale/vybrid/vf_ccm.c

386

reg |= (clk->div_val << clk->div_shift);

sys/arm/freescale/vybrid/vf_ccm.c

387

WRITE4(sc, clk->reg, reg);

sys/arm/freescale/vybrid/vf_ccm.c

443

int reg;

sys/arm/freescale/vybrid/vf_ccm.c

459

reg = READ4(sc, CCM_CCR);

sys/arm/freescale/vybrid/vf_ccm.c

460

reg |= (FIRC_EN | FXOSC_EN);

sys/arm/freescale/vybrid/vf_ccm.c

461

WRITE4(sc, CCM_CCR, reg);

sys/arm/freescale/vybrid/vf_dcu4.c

223

int reg;

sys/arm/freescale/vybrid/vf_dcu4.c

228

reg = READ4(sc, DCU_INT_STATUS);

sys/arm/freescale/vybrid/vf_dcu4.c

229

WRITE4(sc, DCU_INT_STATUS, reg);

sys/arm/freescale/vybrid/vf_dcu4.c

286

int reg;

sys/arm/freescale/vybrid/vf_dcu4.c

292

reg = ((sc->sc_info.fb_height) << DELTA_Y_S);

sys/arm/freescale/vybrid/vf_dcu4.c

293

reg |= (sc->sc_info.fb_width / 16);

sys/arm/freescale/vybrid/vf_dcu4.c

294

WRITE4(sc, DCU_DISP_SIZE, reg);

sys/arm/freescale/vybrid/vf_dcu4.c

296

reg = (panel->h_back_porch << BP_H_SHIFT);

sys/arm/freescale/vybrid/vf_dcu4.c

297

reg |= (panel->h_pulse_width << PW_H_SHIFT);

sys/arm/freescale/vybrid/vf_dcu4.c

298

reg |= (panel->h_front_porch << FP_H_SHIFT);

sys/arm/freescale/vybrid/vf_dcu4.c

299

WRITE4(sc, DCU_HSYN_PARA, reg);

sys/arm/freescale/vybrid/vf_dcu4.c

301

reg = (panel->v_back_porch << BP_V_SHIFT);

sys/arm/freescale/vybrid/vf_dcu4.c

302

reg |= (panel->v_pulse_width << PW_V_SHIFT);

sys/arm/freescale/vybrid/vf_dcu4.c

303

reg |= (panel->v_front_porch << FP_V_SHIFT);

sys/arm/freescale/vybrid/vf_dcu4.c

304

WRITE4(sc, DCU_VSYN_PARA, reg);

sys/arm/freescale/vybrid/vf_dcu4.c

309

reg = (INV_VS | INV_HS);

sys/arm/freescale/vybrid/vf_dcu4.c

310

WRITE4(sc, DCU_SYNPOL, reg);

sys/arm/freescale/vybrid/vf_dcu4.c

313

reg = (0x3 << LS_BF_VS_SHIFT);

sys/arm/freescale/vybrid/vf_dcu4.c

314

reg |= (0x78 << OUT_BUF_HIGH_SHIFT);

sys/arm/freescale/vybrid/vf_dcu4.c

315

reg |= (0 << OUT_BUF_LOW_SHIFT);

sys/arm/freescale/vybrid/vf_dcu4.c

316

WRITE4(sc, DCU_THRESHOLD, reg);

sys/arm/freescale/vybrid/vf_dcu4.c

335

reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 16));

sys/arm/freescale/vybrid/vf_dcu4.c

336

WRITE4(sc, DCU_CTRLDESCLn_1(0), reg);

sys/arm/freescale/vybrid/vf_dcu4.c

339

reg = (BPP24 << BPP_SHIFT);

sys/arm/freescale/vybrid/vf_dcu4.c

340

reg |= EN_LAYER;

sys/arm/freescale/vybrid/vf_dcu4.c

341

reg |= (0xFF << TRANS_SHIFT); /* completely opaque */

sys/arm/freescale/vybrid/vf_dcu4.c

342

WRITE4(sc, DCU_CTRLDESCLn_4(0), reg);

sys/arm/freescale/vybrid/vf_dcu4.c

350

reg = READ4(sc, DCU_DCU_MODE);

sys/arm/freescale/vybrid/vf_dcu4.c

351

reg &= ~(DCU_MODE_M << DCU_MODE_S);

sys/arm/freescale/vybrid/vf_dcu4.c

352

reg |= (DCU_MODE_NORMAL << DCU_MODE_S);

sys/arm/freescale/vybrid/vf_dcu4.c

353

reg |= (RASTER_EN);

sys/arm/freescale/vybrid/vf_dcu4.c

354

WRITE4(sc, DCU_DCU_MODE, reg);

sys/arm/freescale/vybrid/vf_dmamux.c

102

reg = 0;

sys/arm/freescale/vybrid/vf_dmamux.c

104

reg |= (CHCFG_ENBL);

sys/arm/freescale/vybrid/vf_dmamux.c

106

reg &= ~(CHCFG_SOURCE_MASK << CHCFG_SOURCE_SHIFT);

sys/arm/freescale/vybrid/vf_dmamux.c

107

reg |= (source << CHCFG_SOURCE_SHIFT);

sys/arm/freescale/vybrid/vf_dmamux.c

109

MUX_WRITE1(sc, mux, DMAMUX_CHCFG(channel), reg);

sys/arm/freescale/vybrid/vf_dmamux.c

96

int reg;

sys/arm/freescale/vybrid/vf_edma.c

120

int reg;

sys/arm/freescale/vybrid/vf_edma.c

129

reg, READ4(sc, DMA_ES));

sys/arm/freescale/vybrid/vf_edma.c

196

int reg;

sys/arm/freescale/vybrid/vf_edma.c

198

reg = READ4(sc, DMA_ERQ);

sys/arm/freescale/vybrid/vf_edma.c

199

reg &= ~(0x1 << chnum);

sys/arm/freescale/vybrid/vf_edma.c

200

WRITE4(sc, DMA_ERQ, reg);

sys/arm/freescale/vybrid/vf_edma.c

210

int reg;

sys/arm/freescale/vybrid/vf_edma.c

221

reg = (tcd->smod << TCD_ATTR_SMOD_SHIFT);

sys/arm/freescale/vybrid/vf_edma.c

222

reg |= (tcd->dmod << TCD_ATTR_DMOD_SHIFT);

sys/arm/freescale/vybrid/vf_edma.c

223

reg |= (tcd->ssize << TCD_ATTR_SSIZE_SHIFT);

sys/arm/freescale/vybrid/vf_edma.c

224

reg |= (tcd->dsize << TCD_ATTR_DSIZE_SHIFT);

sys/arm/freescale/vybrid/vf_edma.c

225

TCD_WRITE2(sc, DMA_TCDn_ATTR(chnum), reg);

sys/arm/freescale/vybrid/vf_edma.c

233

reg = tcd->nmajor; /* Current Major Iteration Count */

sys/arm/freescale/vybrid/vf_edma.c

234

TCD_WRITE2(sc, DMA_TCDn_CITER_ELINKNO(chnum), reg);

sys/arm/freescale/vybrid/vf_edma.c

235

TCD_WRITE2(sc, DMA_TCDn_BITER_ELINKNO(chnum), reg);

sys/arm/freescale/vybrid/vf_edma.c

237

reg = (TCD_CSR_INTMAJOR);

sys/arm/freescale/vybrid/vf_edma.c

239

reg |= TCD_CSR_MAJORELINK;

sys/arm/freescale/vybrid/vf_edma.c

240

reg |= (tcd->majorelinkch << TCD_CSR_MAJORELINKCH_SHIFT);

sys/arm/freescale/vybrid/vf_edma.c

242

TCD_WRITE2(sc, DMA_TCDn_CSR(chnum), reg);

sys/arm/freescale/vybrid/vf_edma.c

245

reg = READ4(sc, DMA_ERQ);

sys/arm/freescale/vybrid/vf_edma.c

246

reg |= (0x1 << chnum);

sys/arm/freescale/vybrid/vf_edma.c

247

WRITE4(sc, DMA_ERQ, reg);

sys/arm/freescale/vybrid/vf_edma.c

250

reg = READ4(sc, DMA_EEI);

sys/arm/freescale/vybrid/vf_edma.c

251

reg |= (0x1 << chnum);

sys/arm/freescale/vybrid/vf_edma.c

252

WRITE4(sc, DMA_EEI, reg);

sys/arm/freescale/vybrid/vf_edma.c

260

int reg;

sys/arm/freescale/vybrid/vf_edma.c

263

reg = TCD_READ2(sc, DMA_TCDn_CSR(chnum));

sys/arm/freescale/vybrid/vf_edma.c

264

reg |= TCD_CSR_START;

sys/arm/freescale/vybrid/vf_edma.c

265

TCD_WRITE2(sc, DMA_TCDn_CSR(chnum), reg);

sys/arm/freescale/vybrid/vf_ehci.c

200

int reg;

sys/arm/freescale/vybrid/vf_ehci.c

203

reg = PHY_READ4(esc, USBPHY_CTRL);

sys/arm/freescale/vybrid/vf_ehci.c

204

reg |= (USBPHY_CTRL_SFTRST);

sys/arm/freescale/vybrid/vf_ehci.c

205

PHY_WRITE4(esc, USBPHY_CTRL, reg);

sys/arm/freescale/vybrid/vf_ehci.c

210

reg &= ~(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE);

sys/arm/freescale/vybrid/vf_ehci.c

211

PHY_WRITE4(esc, USBPHY_CTRL, reg);

sys/arm/freescale/vybrid/vf_ehci.c

213

reg = (ENUTMILEVEL2 | ENUTMILEVEL3);

sys/arm/freescale/vybrid/vf_ehci.c

214

PHY_WRITE4(esc, USBPHY_CTRL_SET, reg);

sys/arm/freescale/vybrid/vf_ehci.c

231

reg = PHY_READ4(esc, USBPHY_DEBUG);

sys/arm/freescale/vybrid/vf_ehci.c

232

reg &= ~(USBPHY_DEBUG_CLKGATE);

sys/arm/freescale/vybrid/vf_ehci.c

233

PHY_WRITE4(esc, USBPHY_DEBUG, reg);

sys/arm/freescale/vybrid/vf_ehci.c

260

int reg;

sys/arm/freescale/vybrid/vf_ehci.c

349

reg = bus_space_read_4(sc->sc_io_tag, sc->sc_io_hdl, 0xA8);

sys/arm/freescale/vybrid/vf_ehci.c

350

reg |= 0x3;

sys/arm/freescale/vybrid/vf_ehci.c

351

bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, 0xA8, reg);

sys/arm/freescale/vybrid/vf_port.c

110

int reg;

sys/arm/freescale/vybrid/vf_port.c

116

reg = READ4(sc, PORT_PCR(i));

sys/arm/freescale/vybrid/vf_port.c

117

if (reg & PCR_ISF) {

sys/arm/freescale/vybrid/vf_port.c

119

WRITE4(sc, PORT_PCR(i), reg);

sys/arm/freescale/vybrid/vf_port.c

139

int reg;

sys/arm/freescale/vybrid/vf_port.c

173

reg = READ4(sc, PORT_PCR(pnum));

sys/arm/freescale/vybrid/vf_port.c

174

reg &= ~(PCR_IRQC_M << PCR_IRQC_S);

sys/arm/freescale/vybrid/vf_port.c

175

reg |= (val << PCR_IRQC_S);

sys/arm/freescale/vybrid/vf_port.c

176

WRITE4(sc, PORT_PCR(pnum), reg);

sys/arm/freescale/vybrid/vf_sai.c

344

int reg;

sys/arm/freescale/vybrid/vf_sai.c

355

reg = READ4(sc, I2S_TCR2);

sys/arm/freescale/vybrid/vf_sai.c

356

reg &= ~(0xff << 0);

sys/arm/freescale/vybrid/vf_sai.c

357

reg |= (sr->div << 0);

sys/arm/freescale/vybrid/vf_sai.c

358

WRITE4(sc, I2S_TCR2, reg);

sys/arm/freescale/vybrid/vf_sai.c

615

int reg;

sys/arm/freescale/vybrid/vf_sai.c

621

reg = READ4(sc, I2S_TCSR);

sys/arm/freescale/vybrid/vf_sai.c

622

reg &= ~(TCSR_BCE | TCSR_TE | TCSR_FRDE);

sys/arm/freescale/vybrid/vf_sai.c

623

WRITE4(sc, I2S_TCSR, reg);

sys/arm/freescale/vybrid/vf_sai.c

625

reg = READ4(sc, I2S_TCR3);

sys/arm/freescale/vybrid/vf_sai.c

626

reg &= ~(TCR3_TCE);

sys/arm/freescale/vybrid/vf_sai.c

627

WRITE4(sc, I2S_TCR3, reg);

sys/arm/freescale/vybrid/vf_sai.c

629

reg = (64 << TCR1_TFW_S);

sys/arm/freescale/vybrid/vf_sai.c

630

WRITE4(sc, I2S_TCR1, reg);

sys/arm/freescale/vybrid/vf_sai.c

632

reg = READ4(sc, I2S_TCR2);

sys/arm/freescale/vybrid/vf_sai.c

633

reg &= ~(TCR2_MSEL_M << TCR2_MSEL_S);

sys/arm/freescale/vybrid/vf_sai.c

634

reg |= (1 << TCR2_MSEL_S);

sys/arm/freescale/vybrid/vf_sai.c

635

reg |= (TCR2_BCP | TCR2_BCD);

sys/arm/freescale/vybrid/vf_sai.c

636

WRITE4(sc, I2S_TCR2, reg);

sys/arm/freescale/vybrid/vf_sai.c

640

reg = READ4(sc, I2S_TCR3);

sys/arm/freescale/vybrid/vf_sai.c

641

reg |= (TCR3_TCE);

sys/arm/freescale/vybrid/vf_sai.c

642

WRITE4(sc, I2S_TCR3, reg);

sys/arm/freescale/vybrid/vf_sai.c

645

reg = READ4(sc, I2S_TCR4);

sys/arm/freescale/vybrid/vf_sai.c

646

reg &= ~(TCR4_FRSZ_M << TCR4_FRSZ_S);

sys/arm/freescale/vybrid/vf_sai.c

647

reg |= (1 << TCR4_FRSZ_S); /* 2 words per frame */

sys/arm/freescale/vybrid/vf_sai.c

648

reg &= ~(TCR4_SYWD_M << TCR4_SYWD_S);

sys/arm/freescale/vybrid/vf_sai.c

649

reg |= (23 << TCR4_SYWD_S);

sys/arm/freescale/vybrid/vf_sai.c

650

reg |= (TCR4_MF | TCR4_FSE | TCR4_FSP | TCR4_FSD);

sys/arm/freescale/vybrid/vf_sai.c

651

WRITE4(sc, I2S_TCR4, reg);

sys/arm/freescale/vybrid/vf_sai.c

653

reg = READ4(sc, I2S_TCR5);

sys/arm/freescale/vybrid/vf_sai.c

654

reg &= ~(TCR5_W0W_M << TCR5_W0W_S);

sys/arm/freescale/vybrid/vf_sai.c

655

reg |= (23 << TCR5_W0W_S);

sys/arm/freescale/vybrid/vf_sai.c

656

reg &= ~(TCR5_WNW_M << TCR5_WNW_S);

sys/arm/freescale/vybrid/vf_sai.c

657

reg |= (23 << TCR5_WNW_S);

sys/arm/freescale/vybrid/vf_sai.c

658

reg &= ~(TCR5_FBT_M << TCR5_FBT_S);

sys/arm/freescale/vybrid/vf_sai.c

659

reg |= (31 << TCR5_FBT_S);

sys/arm/freescale/vybrid/vf_sai.c

660

WRITE4(sc, I2S_TCR5, reg);

sys/arm/freescale/vybrid/vf_sai.c

663

reg = READ4(sc, I2S_TCSR);

sys/arm/freescale/vybrid/vf_sai.c

664

reg |= (TCSR_BCE | TCSR_TE | TCSR_FRDE);

sys/arm/freescale/vybrid/vf_sai.c

665

reg |= (1 << 10); /* FEIE */

sys/arm/freescale/vybrid/vf_sai.c

666

WRITE4(sc, I2S_TCSR, reg);

sys/arm/freescale/vybrid/vf_spi.c

147

uint32_t reg;

sys/arm/freescale/vybrid/vf_spi.c

160

reg = READ4(sc, SPI_MCR);

sys/arm/freescale/vybrid/vf_spi.c

161

reg |= MCR_MSTR;

sys/arm/freescale/vybrid/vf_spi.c

162

reg &= ~(MCR_CONT_SCKE | MCR_MDIS | MCR_FRZ);

sys/arm/freescale/vybrid/vf_spi.c

163

reg &= ~(MCR_PCSIS_M << MCR_PCSIS_S);

sys/arm/freescale/vybrid/vf_spi.c

164

reg |= (MCR_PCSIS_M << MCR_PCSIS_S); /* PCS Active low */

sys/arm/freescale/vybrid/vf_spi.c

165

reg |= (MCR_CLR_TXF | MCR_CLR_RXF);

sys/arm/freescale/vybrid/vf_spi.c

166

WRITE4(sc, SPI_MCR, reg);

sys/arm/freescale/vybrid/vf_spi.c

168

reg = READ4(sc, SPI_RSER);

sys/arm/freescale/vybrid/vf_spi.c

169

reg |= RSER_EOQF_RE;

sys/arm/freescale/vybrid/vf_spi.c

170

WRITE4(sc, SPI_RSER, reg);

sys/arm/freescale/vybrid/vf_spi.c

172

reg = READ4(sc, SPI_MCR);

sys/arm/freescale/vybrid/vf_spi.c

173

reg &= ~MCR_HALT;

sys/arm/freescale/vybrid/vf_spi.c

174

WRITE4(sc, SPI_MCR, reg);

sys/arm/freescale/vybrid/vf_spi.c

176

reg = READ4(sc, SPI_CTAR0);

sys/arm/freescale/vybrid/vf_spi.c

177

reg &= ~(CTAR_FMSZ_M << CTAR_FMSZ_S);

sys/arm/freescale/vybrid/vf_spi.c

178

reg |= (CTAR_FMSZ_8 << CTAR_FMSZ_S);

sys/arm/freescale/vybrid/vf_spi.c

185

reg &= ~CTAR_CPOL; /* Polarity */

sys/arm/freescale/vybrid/vf_spi.c

186

reg |= CTAR_CPHA;

sys/arm/freescale/vybrid/vf_spi.c

191

reg |= CTAR_LSBFE;

sys/arm/freescale/vybrid/vf_spi.c

192

WRITE4(sc, SPI_CTAR0, reg);

sys/arm/freescale/vybrid/vf_spi.c

194

reg = READ4(sc, SPI_CTAR0);

sys/arm/freescale/vybrid/vf_spi.c

195

reg &= ~(CTAR_PBR_M << CTAR_PBR_S);

sys/arm/freescale/vybrid/vf_spi.c

196

reg |= (CTAR_PBR_7 << CTAR_PBR_S);

sys/arm/freescale/vybrid/vf_spi.c

197

WRITE4(sc, SPI_CTAR0, reg);

sys/arm/freescale/vybrid/vf_spi.c

208

uint32_t reg, wreg;

sys/arm/freescale/vybrid/vf_spi.c

232

reg = READ4(sc, SPI_SR);

sys/arm/freescale/vybrid/vf_spi.c

233

reg |= (SR_TCF | SR_EOQF);

sys/arm/freescale/vybrid/vf_spi.c

234

WRITE4(sc, SPI_SR, reg);

sys/arm/freescale/vybrid/vf_uart.c

204

int reg;

sys/arm/freescale/vybrid/vf_uart.c

218

reg = uart_getreg(bas, UART_C2);

sys/arm/freescale/vybrid/vf_uart.c

219

reg &= ~(UART_C2_RE | UART_C2_TE);

sys/arm/freescale/vybrid/vf_uart.c

227

reg = uart_getreg(bas, UART_BDH);

sys/arm/freescale/vybrid/vf_uart.c

228

reg &= ~UART_BDH_SBR;

sys/arm/freescale/vybrid/vf_uart.c

229

reg |= ((sbr & 0x1f00) >> 8);

sys/arm/freescale/vybrid/vf_uart.c

230

uart_setreg(bas, UART_BDH, reg);

sys/arm/freescale/vybrid/vf_uart.c

232

reg = sbr & 0x00ff;

sys/arm/freescale/vybrid/vf_uart.c

233

uart_setreg(bas, UART_BDL, reg);

sys/arm/freescale/vybrid/vf_uart.c

235

reg = uart_getreg(bas, UART_C4);

sys/arm/freescale/vybrid/vf_uart.c

236

reg &= ~UART_C4_BRFA;

sys/arm/freescale/vybrid/vf_uart.c

237

reg |= (brfa & UART_C4_BRFA);

sys/arm/freescale/vybrid/vf_uart.c

238

uart_setreg(bas, UART_C4, reg);

sys/arm/freescale/vybrid/vf_uart.c

240

reg = uart_getreg(bas, UART_C2);

sys/arm/freescale/vybrid/vf_uart.c

241

reg |= (UART_C2_RE | UART_C2_TE);

sys/arm/freescale/vybrid/vf_uart.c

242

uart_setreg(bas, UART_C2, reg);

sys/arm/freescale/vybrid/vf_uart.c

293

int reg;

sys/arm/freescale/vybrid/vf_uart.c

302

reg = uart_getreg(bas, UART_C2);

sys/arm/freescale/vybrid/vf_uart.c

304

reg &= ~UART_C2_RIE;

sys/arm/freescale/vybrid/vf_uart.c

306

reg |= UART_C2_RIE;

sys/arm/freescale/vybrid/vf_uart.c

308

uart_setreg(bas, UART_C2, reg);

sys/arm/freescale/vybrid/vf_uart.c

367

int reg;

sys/arm/freescale/vybrid/vf_uart.c

382

reg = uart_getreg(bas, UART_C2);

sys/arm/freescale/vybrid/vf_uart.c

383

reg &= ~(UART_C2_TIE);

sys/arm/freescale/vybrid/vf_uart.c

384

uart_setreg(bas, UART_C2, reg);

sys/arm/freescale/vybrid/vf_uart.c

392

reg = uart_getreg(bas, UART_C2);

sys/arm/freescale/vybrid/vf_uart.c

393

reg &= ~(UART_C2_RIE);

sys/arm/freescale/vybrid/vf_uart.c

394

uart_setreg(bas, UART_C2, reg);

sys/arm/freescale/vybrid/vf_uart.c

440

int reg;

sys/arm/freescale/vybrid/vf_uart.c

459

reg = uart_getreg(bas, UART_C2);

sys/arm/freescale/vybrid/vf_uart.c

460

reg |= (UART_C2_RIE);

sys/arm/freescale/vybrid/vf_uart.c

461

uart_setreg(bas, UART_C2, reg);

sys/arm/freescale/vybrid/vf_uart.c

471

int reg;

sys/arm/freescale/vybrid/vf_uart.c

479

reg = uart_getreg(bas, UART_C2);

sys/arm/freescale/vybrid/vf_uart.c

480

reg |= (UART_C2_RIE);

sys/arm/freescale/vybrid/vf_uart.c

481

uart_setreg(bas, UART_C2, reg);

sys/arm/freescale/vybrid/vf_uart.c

492

int reg;

sys/arm/freescale/vybrid/vf_uart.c

506

reg = uart_getreg(bas, UART_C2);

sys/arm/freescale/vybrid/vf_uart.c

507

reg |= (UART_C2_TIE);

sys/arm/freescale/vybrid/vf_uart.c

508

uart_setreg(bas, UART_C2, reg);

sys/arm/include/armreg.h

372

#define CPU_CLIDR_CTYPE(reg,x) (((reg) >> ((x) * 3)) & 0x7)

sys/arm/include/armreg.h

373

#define CPU_CLIDR_LOUIS(reg) (((reg) >> 21) & 0x7)

sys/arm/include/armreg.h

374

#define CPU_CLIDR_LOC(reg) (((reg) >> 24) & 0x7)

sys/arm/include/armreg.h

375

#define CPU_CLIDR_LOUU(reg) (((reg) >> 27) & 0x7)

sys/arm/include/cpu.h

100

uint32_t reg; \

sys/arm/include/cpu.h

101

__asm __volatile("mrc\t" _FX(aname): "=r" (reg)); \

sys/arm/include/cpu.h

102

return(reg); \

sys/arm/include/cpu.h

109

uint64_t reg; \

sys/arm/include/cpu.h

110

__asm __volatile("mrrc\t" _FX(aname): "=r" (reg)); \

sys/arm/include/cpu.h

111

return(reg); \

sys/arm/include/cpu.h

123

fname(uint32_t reg) \

sys/arm/include/cpu.h

125

__asm __volatile("mcr\t" _FX(aname):: "r" (reg)); \

sys/arm/include/cpu.h

130

fname(uint64_t reg) \

sys/arm/include/cpu.h

132

__asm __volatile("mcrr\t" _FX(aname):: "r" (reg)); \

sys/arm/include/cpu.h

601

cp15_ttbr_set(uint32_t reg)

sys/arm/include/cpu.h

604

_CP15_TTB_SET(reg);

sys/arm/include/vfp.h

148

uint64_t reg[32];

sys/arm/mv/a37x0_gpio.c

140

uint32_t reg;

sys/arm/mv/a37x0_gpio.c

145

reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));

sys/arm/mv/a37x0_gpio.c

146

if ((reg & A37X0_GPIO_BIT(pin)) != 0)

sys/arm/mv/a37x0_gpio.c

158

uint32_t reg;

sys/arm/mv/a37x0_gpio.c

164

reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));

sys/arm/mv/a37x0_gpio.c

166

reg |= A37X0_GPIO_BIT(pin);

sys/arm/mv/a37x0_gpio.c

168

reg &= ~A37X0_GPIO_BIT(pin);

sys/arm/mv/a37x0_gpio.c

169

A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUT_EN(pin), reg);

sys/arm/mv/a37x0_gpio.c

178

uint32_t reg;

sys/arm/mv/a37x0_gpio.c

184

reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));

sys/arm/mv/a37x0_gpio.c

185

if ((reg & A37X0_GPIO_BIT(pin)) != 0)

sys/arm/mv/a37x0_gpio.c

186

reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin));

sys/arm/mv/a37x0_gpio.c

188

reg = A37X0_GPIO_READ(sc, A37X0_GPIO_INPUT(pin));

sys/arm/mv/a37x0_gpio.c

189

*val = ((reg & A37X0_GPIO_BIT(pin)) != 0) ? 1 : 0;

sys/arm/mv/a37x0_gpio.c

198

uint32_t reg;

sys/arm/mv/a37x0_gpio.c

204

reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin));

sys/arm/mv/a37x0_gpio.c

206

reg |= A37X0_GPIO_BIT(pin);

sys/arm/mv/a37x0_gpio.c

208

reg &= ~A37X0_GPIO_BIT(pin);

sys/arm/mv/a37x0_gpio.c

209

A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg);

sys/arm/mv/a37x0_gpio.c

218

uint32_t reg;

sys/arm/mv/a37x0_gpio.c

224

reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));

sys/arm/mv/a37x0_gpio.c

225

if ((reg & A37X0_GPIO_BIT(pin)) == 0)

sys/arm/mv/a37x0_gpio.c

227

reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin));

sys/arm/mv/a37x0_gpio.c

228

reg ^= A37X0_GPIO_BIT(pin);

sys/arm/mv/a37x0_gpio.c

229

A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg);

sys/arm/mv/a37x0_iic.c

147

uint32_t mode, reg;

sys/arm/mv/a37x0_iic.c

152

reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);

sys/arm/mv/a37x0_iic.c

153

mode = reg & ICR_MODE_MASK;

sys/arm/mv/a37x0_iic.c

154

A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg & ~ICR_IUE);

sys/arm/mv/a37x0_iic.c

155

A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_UR);

sys/arm/mv/a37x0_iic.c

157

A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg & ~ICR_IUE);

sys/arm/mv/a37x0_iic.c

160

reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);

sys/arm/mv/a37x0_iic.c

161

reg |= mode | ICR_IUE | ICR_GCD | ICR_SCLE;

sys/arm/mv/a37x0_iic.c

162

A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg);

sys/arm/mv/a37x0_iic.c

286

uint32_t reg;

sys/arm/mv/a37x0_iic.c

291

reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);

sys/arm/mv/a37x0_iic.c

292

if (reg & (ICR_ACKNAK | ICR_STOP)) {

sys/arm/mv/a37x0_iic.c

293

reg &= ~(ICR_START | ICR_ACKNAK | ICR_STOP);

sys/arm/mv/a37x0_iic.c

294

A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg);

sys/arm/mv/a37x0_iic.c

297

reg = A37X0_IIC_READ(sc, A37X0_IIC_ISR);

sys/arm/mv/a37x0_iic.c

298

A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, reg);

sys/arm/mv/a37x0_iic.c

309

uint32_t reg, status;

sys/arm/mv/a37x0_iic.c

324

reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);

sys/arm/mv/a37x0_iic.c

325

reg &= ~(ICR_STOP | ICR_ACKNAK);

sys/arm/mv/a37x0_iic.c

326

A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_START | ICR_TB);

sys/arm/mv/a37x0_iic.c

370

uint32_t reg, status;

sys/arm/mv/a37x0_iic.c

374

reg = A37X0_IIC_READ(sc, A37X0_IIC_ISR);

sys/arm/mv/a37x0_iic.c

375

if ((reg & (ISR_UB | ISR_IBB)) != ISR_UB) {

sys/arm/mv/a37x0_iic.c

383

reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);

sys/arm/mv/a37x0_iic.c

384

reg &= ~(ICR_START | ICR_STOP | ICR_ACKNAK);

sys/arm/mv/a37x0_iic.c

386

reg |= ICR_ACKNAK | ICR_STOP;

sys/arm/mv/a37x0_iic.c

387

A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_TB);

sys/arm/mv/a37x0_iic.c

407

uint32_t reg, status;

sys/arm/mv/a37x0_iic.c

411

reg = A37X0_IIC_READ(sc, A37X0_IIC_ISR);

sys/arm/mv/a37x0_iic.c

412

if ((reg & (ISR_UB | ISR_IBB)) != ISR_UB) {

sys/arm/mv/a37x0_iic.c

421

reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);

sys/arm/mv/a37x0_iic.c

422

reg &= ~(ICR_START | ICR_STOP | ICR_ACKNAK);

sys/arm/mv/a37x0_iic.c

424

reg |= ICR_STOP;

sys/arm/mv/a37x0_iic.c

425

A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_TB);

sys/arm/mv/a37x0_iic.c

87

uint32_t reg;

sys/arm/mv/a37x0_iic.c

90

reg = A37X0_IIC_READ(sc, off);

sys/arm/mv/a37x0_iic.c

91

reg &= ~mask;

sys/arm/mv/a37x0_iic.c

92

reg |= value;

sys/arm/mv/a37x0_iic.c

93

A37X0_IIC_WRITE(sc, off, reg);

sys/arm/mv/a37x0_spi.c

114

a37x0_spi_wait(struct a37x0_spi_softc *sc, int timeout, uint32_t reg,

sys/arm/mv/a37x0_spi.c

120

if ((A37X0_SPI_READ(sc, reg) & mask) == 0)

sys/arm/mv/a37x0_spi.c

147

uint32_t reg;

sys/arm/mv/a37x0_spi.c

173

reg = A37X0_SPI_READ(sc, A37X0_SPI_CONTROL);

sys/arm/mv/a37x0_spi.c

174

A37X0_SPI_WRITE(sc, A37X0_SPI_CONTROL, reg & ~A37X0_SPI_CS_MASK);

sys/arm/mv/a37x0_spi.c

177

reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF);

sys/arm/mv/a37x0_spi.c

178

A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg | A37X0_SPI_FIFO_FLUSH);

sys/arm/mv/a37x0_spi.c

188

reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF);

sys/arm/mv/a37x0_spi.c

189

A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg | A37X0_SPI_SRST);

sys/arm/mv/a37x0_spi.c

192

reg &= ~(A37X0_SPI_FIFO_MODE | A37X0_SPI_BYTE_LEN);

sys/arm/mv/a37x0_spi.c

193

A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg);

sys/arm/mv/a37x0_spi.c

197

reg = A37X0_SPI_READ(sc, A37X0_SPI_INTR_STAT);

sys/arm/mv/a37x0_spi.c

198

A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_STAT, reg);

sys/arm/mv/a37x0_spi.c

285

uint32_t psc, reg;

sys/arm/mv/a37x0_spi.c

292

reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF);

sys/arm/mv/a37x0_spi.c

293

reg &= ~A37X0_SPI_PSC_MASK;

sys/arm/mv/a37x0_spi.c

294

reg |= psc & A37X0_SPI_PSC_MASK;

sys/arm/mv/a37x0_spi.c

295

A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg);

sys/arm/mv/a37x0_spi.c

301

uint32_t reg;

sys/arm/mv/a37x0_spi.c

304

reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF);

sys/arm/mv/a37x0_spi.c

305

reg &= ~(A37X0_SPI_DATA_PIN_MASK << A37X0_SPI_DATA_PIN_SHIFT);

sys/arm/mv/a37x0_spi.c

306

reg |= (npins / 2) << A37X0_SPI_DATA_PIN_SHIFT;

sys/arm/mv/a37x0_spi.c

307

reg |= A37X0_SPI_INSTR_PIN | A37X0_SPI_ADDR_PIN;

sys/arm/mv/a37x0_spi.c

308

A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg);

sys/arm/mv/a37x0_spi.c

314

uint32_t reg;

sys/arm/mv/a37x0_spi.c

316

reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF);

sys/arm/mv/a37x0_spi.c

319

reg &= ~(A37X0_SPI_CLK_PHASE | A37X0_SPI_CLK_POL);

sys/arm/mv/a37x0_spi.c

322

reg &= ~A37X0_SPI_CLK_POL;

sys/arm/mv/a37x0_spi.c

323

reg |= A37X0_SPI_CLK_PHASE;

sys/arm/mv/a37x0_spi.c

326

reg &= ~A37X0_SPI_CLK_PHASE;

sys/arm/mv/a37x0_spi.c

327

reg |= A37X0_SPI_CLK_POL;

sys/arm/mv/a37x0_spi.c

330

reg |= (A37X0_SPI_CLK_PHASE | A37X0_SPI_CLK_POL);

sys/arm/mv/a37x0_spi.c

333

A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg);

sys/arm/mv/a37x0_spi.c

372

uint32_t clock, cs, mode, reg;

sys/arm/mv/a37x0_spi.c

428

reg = A37X0_SPI_READ(sc, A37X0_SPI_INTR_STAT);

sys/arm/mv/a37x0_spi.c

429

A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_STAT, reg);

sys/arm/mv/a37x0_spi.c

439

reg = A37X0_SPI_READ(sc, A37X0_SPI_CONTROL);

sys/arm/mv/a37x0_spi.c

440

if (reg & A37X0_SPI_XFER_DONE)

sys/arm/mv/a37x0_spi.c

450

reg = A37X0_SPI_READ(sc, A37X0_SPI_CONTROL);

sys/arm/mv/a37x0_spi.c

451

A37X0_SPI_WRITE(sc, A37X0_SPI_CONTROL, reg & ~A37X0_SPI_CS_MASK);

sys/arm/mv/armada/thermal.c

259

uint32_t reg;

sys/arm/mv/armada/thermal.c

268

reg = bus_read_4(sc->stat_res, 0);

sys/arm/mv/armada/thermal.c

269

reg = (reg >> tdata->temp_shift) & tdata->temp_mask;

sys/arm/mv/armada/thermal.c

277

tmp = ((m * reg) - b) / div;

sys/arm/mv/armada/thermal.c

279

tmp = (b - (m * reg)) / div;

sys/arm/mv/armada38x/armada38x_mp.c

53

uint32_t reg;

sys/arm/mv/armada38x/armada38x_mp.c

62

reg = bus_space_read_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1));

sys/arm/mv/armada38x/armada38x_mp.c

63

reg &= ~CPU_RESET_ASSERT;

sys/arm/mv/armada38x/armada38x_mp.c

65

bus_space_write_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1), reg);

sys/arm/mv/armada38x/armada38x_pl310.c

50

uint32_t reg;

sys/arm/mv/armada38x/armada38x_pl310.c

56

reg = pl310_read4(sc, PL310_POWER_CTRL);

sys/arm/mv/armada38x/armada38x_pl310.c

57

reg |= POWER_CTRL_ENABLE_GATING;

sys/arm/mv/armada38x/armada38x_pl310.c

58

pl310_write4(sc, PL310_POWER_CTRL, reg);

sys/arm/mv/armadaxp/armadaxp.c

116

read_coher_fabric(uint32_t reg)

sys/arm/mv/armadaxp/armadaxp.c

119

return (bus_space_read_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg));

sys/arm/mv/armadaxp/armadaxp.c

123

write_coher_fabric(uint32_t reg, uint32_t val)

sys/arm/mv/armadaxp/armadaxp.c

126

bus_space_write_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg, val);

sys/arm/mv/armadaxp/armadaxp.c

160

read_l2_cache(uint32_t reg)

sys/arm/mv/armadaxp/armadaxp.c

163

return (bus_space_read_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg));

sys/arm/mv/armadaxp/armadaxp.c

167

write_l2_cache(uint32_t reg, uint32_t val)

sys/arm/mv/armadaxp/armadaxp.c

170

bus_space_write_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg, val);

sys/arm/mv/armadaxp/armadaxp.c

182

u_int32_t reg;

sys/arm/mv/armadaxp/armadaxp.c

185

reg = read_l2_cache(ARMADAXP_L2_AUX_CTRL);

sys/arm/mv/armadaxp/armadaxp.c

186

reg &= ~(L2_WBWT_MODE_MASK);

sys/arm/mv/armadaxp/armadaxp.c

187

reg &= ~(L2_REP_STRAT_MASK);

sys/arm/mv/armadaxp/armadaxp.c

188

reg |= L2_REP_STRAT_SEMIPLRU;

sys/arm/mv/armadaxp/armadaxp.c

189

reg |= L2_WBWT_MODE_WT;

sys/arm/mv/armadaxp/armadaxp.c

190

write_l2_cache(ARMADAXP_L2_AUX_CTRL, reg);

sys/arm/mv/armadaxp/armadaxp.c

199

reg = read_l2_cache(ARMADAXP_L2_CTRL);

sys/arm/mv/armadaxp/armadaxp.c

200

write_l2_cache(ARMADAXP_L2_CTRL, reg | L2_ENABLE);

sys/arm/mv/armadaxp/armadaxp.c

214

reg = read_coher_fabric(COHER_FABRIC_CFU);

sys/arm/mv/armadaxp/armadaxp.c

215

reg |= (1 << 17) | (1 << 18);

sys/arm/mv/armadaxp/armadaxp.c

216

write_coher_fabric(COHER_FABRIC_CFU, reg);

sys/arm/mv/armadaxp/armadaxp.c

219

reg = read_coher_fabric(COHER_FABRIC_CIB_CTRL);

sys/arm/mv/armadaxp/armadaxp.c

220

reg &= ~(7 << 16);

sys/arm/mv/armadaxp/armadaxp.c

221

reg |= (7 << 16);

sys/arm/mv/armadaxp/armadaxp.c

222

write_coher_fabric(COHER_FABRIC_CIB_CTRL, reg);

sys/arm/mv/armadaxp/armadaxp_mp.c

103

uint32_t reg, *src, *dst, cpu_num, div_val, cputype;

sys/arm/mv/armadaxp/armadaxp_mp.c

130

reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);

sys/arm/mv/armadaxp/armadaxp_mp.c

131

reg &= CPU_DIVCLK_MASK(cpu_num);

sys/arm/mv/armadaxp/armadaxp_mp.c

132

reg |= div_val << (cpu_num * 8);

sys/arm/mv/armadaxp/armadaxp_mp.c

133

write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg);

sys/arm/mv/armadaxp/armadaxp_mp.c

140

reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0);

sys/arm/mv/armadaxp/armadaxp_mp.c

141

reg &= CPU_DIVCLK_MASK(3);

sys/arm/mv/armadaxp/armadaxp_mp.c

142

reg |= div_val << 24;

sys/arm/mv/armadaxp/armadaxp_mp.c

143

write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0, reg);

sys/arm/mv/armadaxp/armadaxp_mp.c

147

reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);

sys/arm/mv/armadaxp/armadaxp_mp.c

148

reg &= CPU_DIVCLK_MASK(cpu_num);

sys/arm/mv/armadaxp/armadaxp_mp.c

149

reg |= div_val << (cpu_num * 8);

sys/arm/mv/armadaxp/armadaxp_mp.c

150

write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg);

sys/arm/mv/armadaxp/armadaxp_mp.c

154

reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0);

sys/arm/mv/armadaxp/armadaxp_mp.c

155

reg |= ((0x1 << (mp_ncpus - 1)) - 1) << 21;

sys/arm/mv/armadaxp/armadaxp_mp.c

156

write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);

sys/arm/mv/armadaxp/armadaxp_mp.c

157

reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0);

sys/arm/mv/armadaxp/armadaxp_mp.c

158

reg |= 0x01000000;

sys/arm/mv/armadaxp/armadaxp_mp.c

159

write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);

sys/arm/mv/armadaxp/armadaxp_mp.c

162

reg &= ~(0xf << 21);

sys/arm/mv/armadaxp/armadaxp_mp.c

163

write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);

sys/arm/mv/armadaxp/armadaxp_mp.c

75

read_cpu_clkdiv(uint32_t reg)

sys/arm/mv/armadaxp/armadaxp_mp.c

78

return (bus_space_read_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg));

sys/arm/mv/armadaxp/armadaxp_mp.c

82

write_cpu_clkdiv(uint32_t reg, uint32_t val)

sys/arm/mv/armadaxp/armadaxp_mp.c

85

bus_space_write_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg, val);

sys/arm/mv/clk/a37x0_xtal.c

100

reg = SYSCON_READ_4(syscon, NB_GPIO1_PIN_LT_L);

sys/arm/mv/clk/a37x0_xtal.c

101

if (reg & NB_GPIO1_MPP1_9)

sys/arm/mv/clk/a37x0_xtal.c

83

uint32_t reg;

sys/arm/mv/clk/armada38x_gateclk.c

262

uint32_t reg;

sys/arm/mv/clk/armada38x_gateclk.c

267

reg = RD4(sc, addr);

sys/arm/mv/clk/armada38x_gateclk.c

268

reg &= ~clr;

sys/arm/mv/clk/armada38x_gateclk.c

269

reg |= set;

sys/arm/mv/clk/armada38x_gateclk.c

270

WR4(sc, addr, reg);

sys/arm/mv/clk/armada38x_gen.c

57

uint32_t reg;

sys/arm/mv/clk/armada38x_gen.c

60

RD4(clk, 0, &reg);

sys/arm/mv/clk/armada38x_gen.c

63

reg = (reg & SAR_A38X_TCLK_FREQ_MASK) >> SAR_A38X_TCLK_FREQ_SHIFT;

sys/arm/mv/clk/armada38x_gen.c

64

*freq = reg ? TCLK_200MHZ : TCLK_250MHZ;

sys/arm/mv/gpio.c

1007

reg = GPIO_INT_CAUSE;

sys/arm/mv/gpio.c

1009

mv_gpio_reg_clear(s->dev, reg, pin);

sys/arm/mv/gpio.c

1015

uint32_t reg, polar_reg, reg_val, polar_reg_val;

sys/arm/mv/gpio.c

1022

reg = GPIO_DATA_IN;

sys/arm/mv/gpio.c

1025

reg_val = mv_gpio_reg_read(dev, reg);

sys/arm/mv/gpio.c

1037

uint32_t reg;

sys/arm/mv/gpio.c

1046

reg = GPIO_DATA_OUT;

sys/arm/mv/gpio.c

1049

mv_gpio_reg_set(dev, reg, pin);

sys/arm/mv/gpio.c

1051

mv_gpio_reg_clear(dev, reg, pin);

sys/arm/mv/gpio.c

863

mv_gpio_reg_read(device_t dev, uint32_t reg)

sys/arm/mv/gpio.c

868

return (bus_space_read_4(sc->bst, sc->bsh, sc->offset + reg));

sys/arm/mv/gpio.c

872

mv_gpio_reg_write(device_t dev, uint32_t reg, uint32_t val)

sys/arm/mv/gpio.c

877

bus_space_write_4(sc->bst, sc->bsh, sc->offset + reg, val);

sys/arm/mv/gpio.c

881

mv_gpio_reg_set(device_t dev, uint32_t reg, uint32_t pin)

sys/arm/mv/gpio.c

885

reg_val = mv_gpio_reg_read(dev, reg);

sys/arm/mv/gpio.c

887

mv_gpio_reg_write(dev, reg, reg_val);

sys/arm/mv/gpio.c

891

mv_gpio_reg_clear(device_t dev, uint32_t reg, uint32_t pin)

sys/arm/mv/gpio.c

895

reg_val = mv_gpio_reg_read(dev, reg);

sys/arm/mv/gpio.c

897

mv_gpio_reg_write(dev, reg, reg_val);

sys/arm/mv/gpio.c

903

uint32_t reg;

sys/arm/mv/gpio.c

910

reg = GPIO_DATA_OUT_EN_CTRL;

sys/arm/mv/gpio.c

913

mv_gpio_reg_clear(dev, reg, pin);

sys/arm/mv/gpio.c

915

mv_gpio_reg_set(dev, reg, pin);

sys/arm/mv/gpio.c

921

uint32_t reg;

sys/arm/mv/gpio.c

928

reg = GPIO_BLINK_EN;

sys/arm/mv/gpio.c

931

mv_gpio_reg_set(dev, reg, pin);

sys/arm/mv/gpio.c

933

mv_gpio_reg_clear(dev, reg, pin);

sys/arm/mv/gpio.c

939

uint32_t reg, reg_val;

sys/arm/mv/gpio.c

946

reg = GPIO_DATA_IN_POLAR;

sys/arm/mv/gpio.c

949

reg_val = mv_gpio_reg_read(dev, reg) & GPIO(pin);

sys/arm/mv/gpio.c

951

mv_gpio_reg_clear(dev, reg, pin);

sys/arm/mv/gpio.c

953

mv_gpio_reg_set(dev, reg, pin);

sys/arm/mv/gpio.c

955

mv_gpio_reg_set(dev, reg, pin);

sys/arm/mv/gpio.c

957

mv_gpio_reg_clear(dev, reg, pin);

sys/arm/mv/gpio.c

963

uint32_t reg;

sys/arm/mv/gpio.c

970

reg = GPIO_INT_LEV_MASK;

sys/arm/mv/gpio.c

973

mv_gpio_reg_set(dev, reg, pin);

sys/arm/mv/gpio.c

975

mv_gpio_reg_clear(dev, reg, pin);

sys/arm/mv/gpio.c

981

uint32_t reg;

sys/arm/mv/gpio.c

988

reg = GPIO_INT_EDGE_MASK;

sys/arm/mv/gpio.c

991

mv_gpio_reg_set(dev, reg, pin);

sys/arm/mv/gpio.c

993

mv_gpio_reg_clear(dev, reg, pin);

sys/arm/mv/gpio.c

999

uint32_t reg, pin;

sys/arm/mv/mpic.c

156

#define MPIC_WRITE(softc, reg, val) \

sys/arm/mv/mpic.c

157

bus_space_write_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg), (val))

sys/arm/mv/mpic.c

158

#define MPIC_READ(softc, reg) \

sys/arm/mv/mpic.c

159

bus_space_read_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg))

sys/arm/mv/mpic.c

161

#define MPIC_CPU_WRITE(softc, reg, val) \

sys/arm/mv/mpic.c

162

bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val))

sys/arm/mv/mpic.c

163

#define MPIC_CPU_READ(softc, reg) \

sys/arm/mv/mpic.c

164

bus_space_read_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg))

sys/arm/mv/mpic.c

166

#define MPIC_DRBL_WRITE(softc, reg, val) \

sys/arm/mv/mpic.c

167

bus_space_write_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg), (val))

sys/arm/mv/mpic.c

168

#define MPIC_DRBL_READ(softc, reg) \

sys/arm/mv/mpic.c

169

bus_space_read_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg))

sys/arm/mv/mv_ap806_clock.c

100

#define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg))

sys/arm/mv/mv_ap806_clock.c

101

#define WR4(sc, reg, val) SYSCON_WRITE_4((sc)->syscon, (reg), (val))

sys/arm/mv/mv_ap806_clock.c

123

uint32_t reg;

sys/arm/mv/mv_ap806_clock.c

134

reg = RD4(sc, 0x400);

sys/arm/mv/mv_ap806_clock.c

135

switch (reg & 0x1f) {

sys/arm/mv/mv_ap806_clock.c

181

reg & 0x1f);

sys/arm/mv/mv_ap806_gicp.c

78

#define RD4(sc, reg) bus_read_4((sc)->res, (reg))

sys/arm/mv/mv_ap806_gicp.c

79

#define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/arm/mv/mv_ap806_sei.c

102

#define RD4(sc, reg) bus_read_4((sc)->mem_res, (reg))

sys/arm/mv/mv_ap806_sei.c

103

#define WR4(sc, reg, val) bus_write_4((sc)->mem_res, (reg), (val))

sys/arm/mv/mv_armv7_machdep.c

159

pcell_t reg[4];

sys/arm/mv/mv_armv7_machdep.c

198

len = OF_getprop(node, "reg", reg, sizeof(reg));

sys/arm/mv/mv_armv7_machdep.c

202

rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells,

sys/arm/mv/mv_common.c

1829

pcell_t reg[8];

sys/arm/mv/mv_common.c

1836

if ((sizeof(pcell_t) * (addr_cells + size_cells)) > sizeof(reg))

sys/arm/mv/mv_common.c

1838

if (OF_getprop(child, mimo_reg_source, &reg, sizeof(reg)) <= 0)

sys/arm/mv/mv_common.c

1842

base = fdt_data_get(&reg[0], addr_cells);

sys/arm/mv/mv_common.c

1844

base = fdt_data_get(&reg[addr_cells - 2], 2);

sys/arm/mv/mv_common.c

1845

fdt_data_get(&reg[addr_cells], size_cells);

sys/arm/mv/mv_common.c

1959

pcell_t ranges[3], reg[2], *rangesptr;

sys/arm/mv/mv_common.c

1992

len = OF_getprop(node, "reg", reg, sizeof(reg));

sys/arm/mv/mv_common.c

1998

base = fdt_data_get((void *)&reg[0], par_addr_cells);

sys/arm/mv/mv_common.c

2001

reg[0] = cpu_to_fdt32(base);

sys/arm/mv/mv_common.c

2002

if (OF_setprop(node, "reg", (void *)&reg[0],

sys/arm/mv/mv_common.c

2003

sizeof(reg)) < 0)

sys/arm/mv/mv_common.c

370

uint32_t reg;

sys/arm/mv/mv_common.c

372

reg = CPU_PM_CTRL_ALL;

sys/arm/mv/mv_common.c

373

reg &= ~mask;

sys/arm/mv/mv_common.c

374

soc_power_ctrl_set(reg);

sys/arm/mv/mv_common.c

427

read_cpu_ctrl(uint32_t reg)

sys/arm/mv/mv_common.c

431

return (soc_decode_win_spec->read_cpu_ctrl(reg));

sys/arm/mv/mv_common.c

436

read_cpu_ctrl_armv7(uint32_t reg)

sys/arm/mv/mv_common.c

439

return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE_ARMV7, reg));

sys/arm/mv/mv_common.c

443

write_cpu_ctrl(uint32_t reg, uint32_t val)

sys/arm/mv/mv_common.c

447

soc_decode_win_spec->write_cpu_ctrl(reg, val);

sys/arm/mv/mv_common.c

451

write_cpu_ctrl_armv7(uint32_t reg, uint32_t val)

sys/arm/mv/mv_common.c

454

bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE_ARMV7, reg, val);

sys/arm/mv/mv_common.c

458

read_cpu_mp_clocks(uint32_t reg)

sys/arm/mv/mv_common.c

461

return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg));

sys/arm/mv/mv_common.c

465

write_cpu_mp_clocks(uint32_t reg, uint32_t val)

sys/arm/mv/mv_common.c

468

bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val);

sys/arm/mv/mv_common.c

472

read_cpu_misc(uint32_t reg)

sys/arm/mv/mv_common.c

475

return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg));

sys/arm/mv/mv_common.c

479

write_cpu_misc(uint32_t reg, uint32_t val)

sys/arm/mv/mv_common.c

482

bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val);

sys/arm/mv/mv_common.c

82

uint32_t read_cpu_ctrl_armv7(uint32_t reg);

sys/arm/mv/mv_common.c

84

void write_cpu_ctrl_armv7(uint32_t reg, uint32_t val);

sys/arm/mv/mv_cp110_clock.c

134

#define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg))

sys/arm/mv/mv_cp110_clock.c

135

#define WR4(sc, reg, val) SYSCON_WRITE_4((sc)->syscon, (reg), (val))

sys/arm/mv/mv_cp110_clock.c

310

uint32_t reg;

sys/arm/mv/mv_cp110_clock.c

314

reg = RD4(sc, addr);

sys/arm/mv/mv_cp110_clock.c

315

reg &= ~clr;

sys/arm/mv/mv_cp110_clock.c

316

reg |= set;

sys/arm/mv/mv_cp110_clock.c

317

WR4(sc, addr, reg);

sys/arm/mv/mv_cp110_icu.c

100

#define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/arm/mv/mv_cp110_icu.c

121

uint32_t reg, icu_grp;

sys/arm/mv/mv_cp110_icu.c

157

reg = RD4(sc, ICU_INT_CFG(i));

sys/arm/mv/mv_cp110_icu.c

158

icu_grp = reg >> ICU_INT_GROUP_SHIFT;

sys/arm/mv/mv_cp110_icu.c

175

uint32_t reg, irq_no, irq_type;

sys/arm/mv/mv_cp110_icu.c

191

reg = RD4(sc, ICU_INT_CFG(irq_no));

sys/arm/mv/mv_cp110_icu.c

195

sc->parent_map_data->cells[0] = reg & ICU_INT_MASK;

sys/arm/mv/mv_cp110_icu.c

99

#define RD4(sc, reg) bus_read_4((sc)->res, (reg))

sys/arm/mv/mv_pci.c

1106

u_int func, u_int reg, int bytes)

sys/arm/mv/mv_pci.c

1115

PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);

sys/arm/mv/mv_pci.c

1124

cd + (reg & 3));

sys/arm/mv/mv_pci.c

1128

cd + (reg & 2)));

sys/arm/mv/mv_pci.c

1141

u_int func, u_int reg, uint32_t data, int bytes)

sys/arm/mv/mv_pci.c

1150

PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);

sys/arm/mv/mv_pci.c

1158

cd + (reg & 3), data);

sys/arm/mv/mv_pci.c

1162

cd + (reg & 2), htole16(data));

sys/arm/mv/mv_pci.c

1200

u_int reg, int bytes)

sys/arm/mv/mv_pci.c

1209

return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes));

sys/arm/mv/mv_pci.c

1214

u_int reg, uint32_t val, int bytes)

sys/arm/mv/mv_pci.c

1223

mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes);

sys/arm/mv/mv_pci.c

1230

struct ofw_pci_register reg;

sys/arm/mv/mv_pci.c

1239

bzero(&reg, sizeof(reg));

sys/arm/mv/mv_pci.c

1240

reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |

sys/arm/mv/mv_pci.c

1245

&reg, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr),

sys/arm/mv/mv_pci.c

262

#define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc)

sys/arm/mv/mv_pci.c

737

int reg, width;

sys/arm/mv/mv_pci.c

739

reg = PCIR_BAR(barno);

sys/arm/mv/mv_pci.c

745

mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);

sys/arm/mv/mv_pci.c

746

bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);

sys/arm/mv/mv_pci.c

759

bus, slot, func, reg, bar, addr);

sys/arm/mv/mv_pci.c

761

mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);

sys/arm/mv/mv_pci.c

763

mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,

sys/arm/mv/mv_spi.c

123

uint32_t reg;

sys/arm/mv/mv_spi.c

149

reg = MV_SPI_READ(sc, MV_SPI_CONTROL);

sys/arm/mv/mv_spi.c

150

MV_SPI_WRITE(sc, MV_SPI_CONTROL, reg & ~MV_SPI_CTRL_CS_ACTIVE);

sys/arm/mv/mv_spi.c

153

reg = MV_SPI_READ(sc, MV_SPI_CONF);

sys/arm/mv/mv_spi.c

154

MV_SPI_WRITE(sc, MV_SPI_CONF, reg & ~MV_SPI_CONF_BYTELEN);

sys/arm/mv/mv_spi.c

279

uint32_t clock, cs, mode, reg, spr, sppr;

sys/arm/mv/mv_spi.c

322

reg = MV_SPI_READ(sc, MV_SPI_CONF);

sys/arm/mv/mv_spi.c

323

reg &= ~(MV_SPI_CONF_MODE_MASK | MV_SPI_CONF_CLOCK_MASK);

sys/arm/mv/mv_spi.c

324

reg |= mode << MV_SPI_CONF_MODE_SHIFT;

sys/arm/mv/mv_spi.c

325

reg |= spr & MV_SPI_CONF_CLOCK_SPR_MASK;

sys/arm/mv/mv_spi.c

326

reg |= (sppr & MV_SPI_CONF_CLOCK_SPPR_MASK) <<

sys/arm/mv/mv_spi.c

328

reg |= (sppr & MV_SPI_CONF_CLOCK_SPPRHI_MASK) <<

sys/arm/mv/mv_spi.c

330

MV_SPI_WRITE(sc, MV_SPI_CONTROL, reg);

sys/arm/mv/mv_spi.c

333

reg = (cs & MV_SPI_CTRL_CS_MASK) << MV_SPI_CTRL_CS_SHIFT;

sys/arm/mv/mv_spi.c

334

MV_SPI_WRITE(sc, MV_SPI_CONTROL, reg);

sys/arm/mv/mv_spi.c

335

reg = MV_SPI_READ(sc, MV_SPI_CONTROL);

sys/arm/mv/mv_spi.c

336

MV_SPI_WRITE(sc, MV_SPI_CONTROL, reg | MV_SPI_CTRL_CS_ACTIVE);

sys/arm/mv/mv_spi.c

348

reg = MV_SPI_READ(sc, MV_SPI_CONTROL);

sys/arm/mv/mv_spi.c

349

if (reg & MV_SPI_CTRL_SMEMREADY)

sys/arm/mv/mv_spi.c

359

reg = MV_SPI_READ(sc, MV_SPI_CONTROL);

sys/arm/mv/mv_spi.c

360

MV_SPI_WRITE(sc, MV_SPI_CONTROL, reg & ~MV_SPI_CTRL_CS_ACTIVE);

sys/arm/mv/mv_thermal.c

121

#define RD4(sc, reg) \

sys/arm/mv/mv_thermal.c

122

SYSCON_READ_4((sc)->syscon, sc->config->regs[reg])

sys/arm/mv/mv_thermal.c

123

#define WR4(sc, reg, val) \

sys/arm/mv/mv_thermal.c

124

SYSCON_WRITE_4((sc)->syscon, sc->config->regs[reg], (val))

sys/arm/mv/mv_thermal.c

137

uint32_t reg;

sys/arm/mv/mv_thermal.c

142

reg = RD4(sc, STATUS);

sys/arm/mv/mv_thermal.c

143

if ((reg & sc->config->valid_mask) == sc->config->valid_mask)

sys/arm/mv/mv_thermal.c

157

uint32_t reg;

sys/arm/mv/mv_thermal.c

163

reg = RD4(sc, CONTROL0);

sys/arm/mv/mv_thermal.c

164

reg &= ~(CONTROL0_TSEN_START | CONTROL0_TSEN_EN);

sys/arm/mv/mv_thermal.c

165

WR4(sc, CONTROL0, reg);

sys/arm/mv/mv_thermal.c

174

reg &= ~(CONTROL0_MODE_MASK << CONTROL0_MODE_SHIFT);

sys/arm/mv/mv_thermal.c

177

reg |= CONTROL0_MODE_EXTERNAL << CONTROL0_MODE_SHIFT;

sys/arm/mv/mv_thermal.c

178

reg &= ~(CONTROL0_CHANNEL_MASK << CONTROL0_CHANNEL_SHIFT);

sys/arm/mv/mv_thermal.c

179

reg |= (sensor - 1) << CONTROL0_CHANNEL_SHIFT;

sys/arm/mv/mv_thermal.c

181

WR4(sc, CONTROL0, reg);

sys/arm/mv/mv_thermal.c

185

reg = RD4(sc, CONTROL0);

sys/arm/mv/mv_thermal.c

186

reg |= CONTROL0_TSEN_START | CONTROL0_TSEN_EN;

sys/arm/mv/mv_thermal.c

187

WR4(sc, CONTROL0, reg);

sys/arm/mv/mv_thermal.c

195

uint32_t reg;

sys/arm/mv/mv_thermal.c

202

reg = RD4(sc, STATUS) & STATUS_TEMP_MASK;

sys/arm/mv/mv_thermal.c

205

sample = sign_extend(reg, fls(STATUS_TEMP_MASK) - 1);

sys/arm/mv/mv_thermal.c

207

sample = reg;

sys/arm/mv/mv_thermal.c

218

uint32_t reg;

sys/arm/mv/mv_thermal.c

221

reg = RD4(sc, CONTROL0);

sys/arm/mv/mv_thermal.c

222

reg &= ~CONTROL0_TSEN_RESET;

sys/arm/mv/mv_thermal.c

223

reg |= CONTROL0_TSEN_START | CONTROL0_TSEN_EN;

sys/arm/mv/mv_thermal.c

226

reg |= CONTROL0_OSR_MAX << CONTROL0_OSR_SHIFT;

sys/arm/mv/mv_thermal.c

228

WR4(sc, CONTROL0, reg);

sys/arm/mv/mv_thermal.c

239

uint32_t reg;

sys/arm/mv/mv_thermal.c

241

reg = RD4(sc, CONTROL1);

sys/arm/mv/mv_thermal.c

242

reg &= (1 << 7);

sys/arm/mv/mv_thermal.c

243

reg |= (1 << 8);

sys/arm/mv/mv_thermal.c

244

WR4(sc, CONTROL1, reg);

sys/arm/mv/mv_thermal.c

247

reg = RD4(sc, CONTROL0);

sys/arm/mv/mv_thermal.c

248

reg |= CONTROL0_OSR_MAX << CONTROL0_OSR_SHIFT;

sys/arm/mv/mv_thermal.c

249

WR4(sc, CONTROL0, reg);

sys/arm/mv/mvebu_gpio.c

122

gpio_write(struct mvebu_gpio_softc *sc, bus_size_t reg,

sys/arm/mv/mvebu_gpio.c

128

SYSCON_WRITE_4(sc->syscon, sc->offset + GPIO_REGNUM(pin->gp_pin) + reg,

sys/arm/mv/mvebu_gpio.c

133

gpio_read(struct mvebu_gpio_softc *sc, bus_size_t reg, struct gpio_pin *pin)

sys/arm/mv/mvebu_gpio.c

140

sc->offset + GPIO_REGNUM(pin->gp_pin) + reg);

sys/arm/mv/mvebu_gpio.c

146

gpio_modify(struct mvebu_gpio_softc *sc, bus_size_t reg,

sys/arm/mv/mvebu_gpio.c

152

SYSCON_MODIFY_4(sc->syscon, sc->offset + GPIO_REGNUM(pin->gp_pin) + reg,

sys/arm/mv/mvebu_gpio.c

311

intr_modify(struct mvebu_gpio_softc *sc, bus_addr_t reg,

sys/arm/mv/mvebu_gpio.c

318

sc->offset + GPIO_REGNUM(mgi->irq) + reg, 1 << bit,

sys/arm/mv/mvebu_pinctrl.c

106

#define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg))

sys/arm/mv/mvebu_pinctrl.c

107

#define WR4(sc, reg, val) SYSCON_WRITE_4((sc)->syscon, (reg), (val))

sys/arm/mv/mvebu_pinctrl.c

113

uint32_t offset, shift, reg;

sys/arm/mv/mvebu_pinctrl.c

117

reg = RD4(sc, offset);

sys/arm/mv/mvebu_pinctrl.c

118

reg &= ~(PINS_MASK << shift);

sys/arm/mv/mvebu_pinctrl.c

119

reg |= function << shift;

sys/arm/mv/mvebu_pinctrl.c

120

WR4(sc, offset, reg);

sys/arm/mv/mvvar.h

108

uint32_t read_cpu_mp_clocks(uint32_t reg);

sys/arm/mv/mvvar.h

109

void write_cpu_mp_clocks(uint32_t reg, uint32_t val);

sys/arm/mv/mvvar.h

110

uint32_t read_cpu_misc(uint32_t reg);

sys/arm/mv/mvvar.h

111

void write_cpu_misc(uint32_t reg, uint32_t val);

sys/arm/mv/mvwin.h

279

#define WIN_REG_IDX_RD(pre,reg,off,base) \

sys/arm/mv/mvwin.h

281

pre ## _ ## reg ## _read(int i) \

sys/arm/mv/mvwin.h

286

#define WIN_REG_IDX_RD2(pre,reg,off,base) \

sys/arm/mv/mvwin.h

288

pre ## _ ## reg ## _read(int i, int j) \

sys/arm/mv/mvwin.h

293

#define WIN_REG_BASE_IDX_RD(pre,reg,off) \

sys/arm/mv/mvwin.h

295

pre ## _ ## reg ## _read(uint32_t base, int i) \

sys/arm/mv/mvwin.h

300

#define WIN_REG_BASE_IDX_RD2(pre,reg,off) \

sys/arm/mv/mvwin.h

302

pre ## _ ## reg ## _read(uint32_t base, int i, int j) \

sys/arm/mv/mvwin.h

307

#define WIN_REG_IDX_WR(pre,reg,off,base) \

sys/arm/mv/mvwin.h

309

pre ## _ ## reg ## _write(int i, uint32_t val) \

sys/arm/mv/mvwin.h

314

#define WIN_REG_IDX_WR2(pre,reg,off,base) \

sys/arm/mv/mvwin.h

316

pre ## _ ## reg ## _write(int i, int j, uint32_t val) \

sys/arm/mv/mvwin.h

321

#define WIN_REG_BASE_IDX_WR(pre,reg,off) \

sys/arm/mv/mvwin.h

323

pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \

sys/arm/mv/mvwin.h

328

#define WIN_REG_BASE_IDX_WR2(pre,reg,off) \

sys/arm/mv/mvwin.h

330

pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val) \

sys/arm/mv/mvwin.h

335

#define WIN_REG_RD(pre,reg,off,base) \

sys/arm/mv/mvwin.h

337

pre ## _ ## reg ## _read(void) \

sys/arm/mv/mvwin.h

342

#define WIN_REG_BASE_RD(pre,reg,off) \

sys/arm/mv/mvwin.h

344

pre ## _ ## reg ## _read(uint32_t base) \

sys/arm/mv/mvwin.h

349

#define WIN_REG_WR(pre,reg,off,base) \

sys/arm/mv/mvwin.h

351

pre ## _ ## reg ## _write(uint32_t val) \

sys/arm/mv/mvwin.h

356

#define WIN_REG_BASE_WR(pre,reg,off) \

sys/arm/mv/mvwin.h

358

pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \

sys/arm/nvidia/as3722.c

100

int as3722_read_buf(struct as3722_softc *sc, uint8_t reg, uint8_t *buf,

sys/arm/nvidia/as3722.c

112

addr = reg;

sys/arm/nvidia/as3722.c

117

"Error when reading reg 0x%02X, rv: %d\n", reg, rv);

sys/arm/nvidia/as3722.c

125

as3722_write(struct as3722_softc *sc, uint8_t reg, uint8_t val)

sys/arm/nvidia/as3722.c

135

data[0] = reg;

sys/arm/nvidia/as3722.c

141

"Error when writing reg 0x%02X, rv: %d\n", reg, rv);

sys/arm/nvidia/as3722.c

147

int as3722_write_buf(struct as3722_softc *sc, uint8_t reg, uint8_t *buf,

sys/arm/nvidia/as3722.c

159

data[0] = reg;

sys/arm/nvidia/as3722.c

164

"Error when writing reg 0x%02X, rv: %d\n", reg, rv);

sys/arm/nvidia/as3722.c

171

as3722_modify(struct as3722_softc *sc, uint8_t reg, uint8_t clear, uint8_t set)

sys/arm/nvidia/as3722.c

176

rv = as3722_read(sc, reg, &val);

sys/arm/nvidia/as3722.c

183

rv = as3722_write(sc, reg, val);

sys/arm/nvidia/as3722.c

193

uint8_t reg;

sys/arm/nvidia/as3722.c

197

rv = RD1(sc, AS3722_ASIC_ID1, &reg);

sys/arm/nvidia/as3722.c

201

if (reg != AS3722_DEVICE_ID) {

sys/arm/nvidia/as3722.c

202

device_printf(sc->dev, "Invalid chip ID is 0x%x\n", reg);

sys/arm/nvidia/as3722.c

218

uint32_t reg;

sys/arm/nvidia/as3722.c

221

reg = 0;

sys/arm/nvidia/as3722.c

223

reg |= AS3722_INT_PULL_UP;

sys/arm/nvidia/as3722.c

225

reg |= AS3722_I2C_PULL_UP;

sys/arm/nvidia/as3722.c

228

AS3722_INT_PULL_UP | AS3722_I2C_PULL_UP, reg);

sys/arm/nvidia/as3722.c

77

as3722_read(struct as3722_softc *sc, uint8_t reg, uint8_t *val)

sys/arm/nvidia/as3722.c

88

addr = reg;

sys/arm/nvidia/as3722.c

93

"Error when reading reg 0x%02X, rv: %d\n", reg, rv);

sys/arm/nvidia/as3722.h

283

#define RD1(sc, reg, val) as3722_read(sc, reg, val)

sys/arm/nvidia/as3722.h

284

#define WR1(sc, reg, val) as3722_write(sc, reg, val)

sys/arm/nvidia/as3722.h

285

#define RM1(sc, reg, clr, set) as3722_modify(sc, reg, clr, set)

sys/arm/nvidia/as3722.h

287

int as3722_read(struct as3722_softc *sc, uint8_t reg, uint8_t *val);

sys/arm/nvidia/as3722.h

288

int as3722_write(struct as3722_softc *sc, uint8_t reg, uint8_t val);

sys/arm/nvidia/as3722.h

289

int as3722_modify(struct as3722_softc *sc, uint8_t reg, uint8_t clear,

sys/arm/nvidia/as3722.h

291

int as3722_read_buf(struct as3722_softc *sc, uint8_t reg, uint8_t *buf,

sys/arm/nvidia/as3722.h

293

int as3722_write_buf(struct as3722_softc *sc, uint8_t reg, uint8_t *buf,

sys/arm/nvidia/as3722_regulators.c

601

struct as3722_reg_sc *reg;

sys/arm/nvidia/as3722_regulators.c

625

reg = as3722_attach(sc, child, as3722s_def + i);

sys/arm/nvidia/as3722_regulators.c

626

if (reg == NULL) {

sys/arm/nvidia/as3722_regulators.c

631

sc->regs[i] = reg;

sys/arm/nvidia/drm2/tegra_hdmi.c

424

const struct audio_reg *reg;

sys/arm/nvidia/drm2/tegra_hdmi.c

427

reg = audio_regs + i;

sys/arm/nvidia/drm2/tegra_hdmi.c

428

if (reg->audio_clk == freq) {

sys/arm/nvidia/drm2/tegra_hdmi.c

430

*acr_reg = reg->acr_reg;

sys/arm/nvidia/drm2/tegra_hdmi.c

432

*nval_reg = reg->nval_reg;

sys/arm/nvidia/drm2/tegra_hdmi.c

434

*aval_reg = reg->aval_reg;

sys/arm/nvidia/tegra124/tegra124_car.c

486

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_car.c

489

reg = bus_read_4(sc->mem_res, addr);

sys/arm/nvidia/tegra124/tegra124_car.c

490

reg &= ~clear_mask;

sys/arm/nvidia/tegra124/tegra124_car.c

491

reg |= set_mask;

sys/arm/nvidia/tegra124/tegra124_car.c

492

bus_write_4(sc->mem_res, addr, reg);

sys/arm/nvidia/tegra124/tegra124_car.h

32

#define RD4(sc, reg, val) CLKDEV_READ_4((sc)->clkdev, reg, val)

sys/arm/nvidia/tegra124/tegra124_car.h

33

#define WR4(sc, reg, val) CLKDEV_WRITE_4((sc)->clkdev, reg, val)

sys/arm/nvidia/tegra124/tegra124_car.h

34

#define MD4(sc, reg, mask, set) CLKDEV_MODIFY_4((sc)->clkdev, reg, mask, set)

sys/arm/nvidia/tegra124/tegra124_clk_per.c

549

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_clk_per.c

556

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_per.c

561

sc->mux = (reg >> PERLCK_MUX_SHIFT) & PERLCK_MUX_MASK;

sys/arm/nvidia/tegra124/tegra124_clk_per.c

565

sc->divider = (reg & sc->div_mask) + 2;

sys/arm/nvidia/tegra124/tegra124_clk_per.c

569

if (!(reg & PERLCK_UDIV_DIS))

sys/arm/nvidia/tegra124/tegra124_clk_per.c

575

if (!(reg & PERLCK_AMUX_DIS) && (sc->mux == 7)) {

sys/arm/nvidia/tegra124/tegra124_clk_per.c

577

((reg >> PERLCK_AMUX_SHIFT) & PERLCK_MUX_MASK);

sys/arm/nvidia/tegra124/tegra124_clk_per.c

588

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_clk_per.c

596

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_per.c

597

reg &= ~(PERLCK_MUX_MASK << PERLCK_MUX_SHIFT);

sys/arm/nvidia/tegra124/tegra124_clk_per.c

599

reg &= ~PERLCK_AMUX_DIS;

sys/arm/nvidia/tegra124/tegra124_clk_per.c

600

reg &= ~(PERLCK_MUX_MASK << PERLCK_AMUX_SHIFT);

sys/arm/nvidia/tegra124/tegra124_clk_per.c

603

reg |= idx << PERLCK_MUX_SHIFT;

sys/arm/nvidia/tegra124/tegra124_clk_per.c

605

reg |= 7 << PERLCK_MUX_SHIFT;

sys/arm/nvidia/tegra124/tegra124_clk_per.c

606

reg |= (idx - 8) << PERLCK_AMUX_SHIFT;

sys/arm/nvidia/tegra124/tegra124_clk_per.c

609

reg |= idx << PERLCK_MUX_SHIFT;

sys/arm/nvidia/tegra124/tegra124_clk_per.c

611

WR4(sc, sc->base_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_per.c

621

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_clk_per.c

627

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_per.c

757

uint32_t reg, mask, base_reg;

sys/arm/nvidia/tegra124/tegra124_clk_per.c

766

RD4(sc, base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_per.c

777

uint32_t reg, mask, base_reg;

sys/arm/nvidia/tegra124/tegra124_clk_per.c

784

RD4(sc, base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_per.c

786

*enabled = reg & mask ? true: false;

sys/arm/nvidia/tegra124/tegra124_clk_per.c

793

uint32_t reg, mask, reset_reg;

sys/arm/nvidia/tegra124/tegra124_clk_per.c

800

CLKDEV_READ_4(sc->dev, reset_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1000

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1005

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1006

if (reg & PLL_BASE_ENABLE) {

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1007

RD4(sc, sc->misc_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1008

reg |= sc->lock_enable;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1009

WR4(sc, sc->misc_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1012

RD4(sc, sc->misc_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1013

reg &= ~(1 << 29); /* Diasble lock override */

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1014

WR4(sc, sc->misc_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1026

uint32_t reg, misc_reg;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1030

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1041

clknode_get_name(clk), reg, misc_reg, m, n, p, pr,

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1042

(reg >> 30) & 1, (reg >> 29) & 1, (reg >> 28) & 1,

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1081

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1090

CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1091

reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1092

reg |= UTMIP_PLL_CFG2_STABLE_COUNT(STABLE_COUNT);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1093

reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1094

reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(ACTIVE_DELAY_COUNT);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1095

reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1096

reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1097

reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1098

CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1100

CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1101

reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1102

reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(ENABLE_DELAY_COUNT);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1103

reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1104

reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(XTAL_FREQ_COUNT);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1105

reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1106

reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1107

reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1108

reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1109

CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1112

CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1113

reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1114

reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1115

reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1116

CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1119

CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1120

reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1121

reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1122

CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1126

CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1127

reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1128

reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1129

CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1133

CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1134

reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1135

CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

415

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

417

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

419

reg &= ~PLL_BASE_BYPASS;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

420

reg |= PLL_BASE_ENABLE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

421

WR4(sc, sc->base_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

428

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

430

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

432

reg |= PLL_BASE_BYPASS;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

433

reg &= ~PLL_BASE_ENABLE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

434

WR4(sc, sc->base_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

456

reg_to_pdiv(struct pll_sc *sc, uint32_t reg)

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

462

return (1 << reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

465

if (reg == tbl->value)

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

517

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

521

RD4(sc, sc->misc_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

522

reg &= PLLRE_MISC_LOCK;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

526

RD4(sc, sc->misc_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

527

reg &= PLLE_MISC_LOCK;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

531

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

532

reg &= PLL_BASE_LOCK;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

535

return (reg != 0);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

558

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

566

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

567

reg &= ~PLLE_BASE_LOCK_OVERRIDE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

568

WR4(sc, sc->base_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

570

RD4(sc, PLLE_AUX, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

571

reg |= PLLE_AUX_ENABLE_SWCTL;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

572

reg &= ~PLLE_AUX_SEQ_ENABLE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

573

WR4(sc, PLLE_AUX, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

576

RD4(sc, sc->misc_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

577

reg |= PLLE_MISC_LOCK_ENABLE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

578

reg |= PLLE_MISC_IDDQ_SWCTL;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

579

reg &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

580

reg |= PLLE_MISC_PTS;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

581

reg |= PLLE_MISC_VREG_BG_CTRL_MASK;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

582

reg |= PLLE_MISC_VREG_CTRL_MASK;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

583

WR4(sc, sc->misc_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

586

RD4(sc, PLLE_SS_CNTL, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

587

reg |= PLLE_SS_CNTL_DISABLE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

588

WR4(sc, PLLE_SS_CNTL, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

590

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

591

reg = set_divisors(sc, reg, pll_m, pll_n, pll_p);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

592

reg &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

593

reg |= pll_cml << PLLE_BASE_DIVCML_SHIFT;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

594

WR4(sc, sc->base_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

602

RD4(sc, PLLE_SS_CNTL, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

603

reg &= ~PLLE_SS_CNTL_SSCCENTER;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

604

reg &= ~PLLE_SS_CNTL_SSCINVERT;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

605

reg &= ~PLLE_SS_CNTL_COEFFICIENTS_MASK;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

606

reg |= PLLE_SS_CNTL_COEFFICIENTS_VAL;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

607

WR4(sc, PLLE_SS_CNTL, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

608

reg &= ~PLLE_SS_CNTL_SSCBYP;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

609

reg &= ~PLLE_SS_CNTL_BYPASS_SS;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

610

WR4(sc, PLLE_SS_CNTL, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

613

reg &= ~PLLE_SS_CNTL_INTERP_RESET;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

614

WR4(sc, PLLE_SS_CNTL, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

618

RD4(sc, sc->misc_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

619

reg &= ~PLLE_MISC_IDDQ_SWCTL;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

620

WR4(sc, sc->misc_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

622

RD4(sc, PLLE_AUX, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

623

reg |= PLLE_AUX_USE_LOCKDET;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

624

reg |= PLLE_AUX_SEQ_START_STATE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

625

reg &= ~PLLE_AUX_ENABLE_SWCTL;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

626

reg &= ~PLLE_AUX_SS_SWCTL;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

627

WR4(sc, PLLE_AUX, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

628

reg |= PLLE_AUX_SEQ_START_STATE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

630

reg |= PLLE_AUX_SEQ_ENABLE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

631

WR4(sc, PLLE_AUX, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

633

RD4(sc, XUSBIO_PLL_CFG0, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

634

reg |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

635

reg |= XUSBIO_PLL_CFG0_SEQ_START_STATE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

636

reg &= ~XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

637

reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

638

WR4(sc, XUSBIO_PLL_CFG0, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

641

reg |= XUSBIO_PLL_CFG0_SEQ_ENABLE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

642

WR4(sc, XUSBIO_PLL_CFG0, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

645

RD4(sc, SATA_PLL_CFG0, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

646

reg &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

647

reg &= ~SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

648

reg |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

649

reg &= ~SATA_PLL_CFG0_SEQ_IN_SWCTL;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

650

reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

651

reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

652

reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

653

reg &= ~SATA_PLL_CFG0_SEQ_ENABLE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

654

reg |= SATA_PLL_CFG0_SEQ_START_STATE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

655

WR4(sc, SATA_PLL_CFG0, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

657

reg |= SATA_PLL_CFG0_SEQ_ENABLE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

658

WR4(sc, SATA_PLL_CFG0, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

661

RD4(sc, PCIE_PLL_CFG0, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

662

reg |= PCIE_PLL_CFG0_SEQ_ENABLE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

663

WR4(sc, PCIE_PLL_CFG0, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

690

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

694

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

695

*enabled = reg & PLL_BASE_ENABLE ? true: false;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

696

WR4(sc, sc->base_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

704

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

732

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

733

reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

734

reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

735

reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

737

WR4(sc, sc->base_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

740

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

741

reg |= PLL_BASE_ENABLE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

742

WR4(sc, sc->base_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

745

RD4(sc, sc->misc_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

746

reg |= sc->lock_enable;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

747

WR4(sc, sc->misc_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

752

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

753

reg &= ~PLL_BASE_ENABLE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

754

WR4(sc, sc->base_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

757

RD4(sc, sc->misc_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

886

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

914

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

915

reg &= ~PLL_BASE_ENABLE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

916

WR4(sc, sc->base_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

919

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

920

reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

921

reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

922

reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

924

WR4(sc, sc->base_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

925

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

929

RD4(sc, sc->misc_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

930

reg |= sc->lock_enable;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

931

WR4(sc, sc->misc_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

934

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

935

reg |= PLL_BASE_ENABLE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

936

WR4(sc, sc->base_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

941

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

942

reg &= ~PLL_BASE_ENABLE;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

943

WR4(sc, sc->base_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

946

RD4(sc, sc->misc_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_super.c

135

super_mux_get_state(uint32_t reg)

sys/arm/nvidia/tegra124/tegra124_clk_super.c

137

reg = (reg >> SUPER_MUX_STATE_BIT_SHIFT) & SUPER_MUX_STATE_BIT_MASK;

sys/arm/nvidia/tegra124/tegra124_clk_super.c

138

if (reg & SUPER_MUX_STATE_BIT_FIQ)

sys/arm/nvidia/tegra124/tegra124_clk_super.c

140

if (reg & SUPER_MUX_STATE_BIT_IRQ)

sys/arm/nvidia/tegra124/tegra124_clk_super.c

142

if (reg & SUPER_MUX_STATE_BIT_RUN)

sys/arm/nvidia/tegra124/tegra124_clk_super.c

144

if (reg & SUPER_MUX_STATE_BIT_IDLE)

sys/arm/nvidia/tegra124/tegra124_clk_super.c

153

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_clk_super.c

159

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_super.c

161

state = super_mux_get_state(reg);

sys/arm/nvidia/tegra124/tegra124_clk_super.c

170

sc->mux = (reg >> shift) & ((1 << SUPER_MUX_MUX_WIDTH) - 1);

sys/arm/nvidia/tegra124/tegra124_clk_super.c

177

if (((reg & SUPER_MUX_LP_DIV2_BYPASS) == 0) &&

sys/arm/nvidia/tegra124/tegra124_clk_super.c

192

uint32_t reg, dummy;

sys/arm/nvidia/tegra124/tegra124_clk_super.c

197

RD4(sc, sc->base_reg, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_super.c

198

state = super_mux_get_state(reg);

sys/arm/nvidia/tegra124/tegra124_clk_super.c

209

reg &= ~SUPER_MUX_LP_DIV2_BYPASS;

sys/arm/nvidia/tegra124/tegra124_clk_super.c

210

WR4(sc, sc->base_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_super.c

213

reg = SUPER_MUX_LP_DIV2_BYPASS;

sys/arm/nvidia/tegra124/tegra124_clk_super.c

214

WR4(sc, sc->base_reg, reg);

sys/arm/nvidia/tegra124/tegra124_clk_super.c

218

reg &= ~(((1 << SUPER_MUX_MUX_WIDTH) - 1) << shift);

sys/arm/nvidia/tegra124/tegra124_clk_super.c

219

reg |= idx << shift;

sys/arm/nvidia/tegra124/tegra124_clk_super.c

221

WR4(sc, sc->base_reg, reg);

sys/arm/nvidia/tegra124/tegra124_machdep.c

100

reg = bus_space_read_4(fdtbus_bs_tag, pmc, PMC_SCRATCH0);

sys/arm/nvidia/tegra124/tegra124_machdep.c

101

reg &= PMC_SCRATCH0_MODE_MASK;

sys/arm/nvidia/tegra124/tegra124_machdep.c

103

reg | PMC_SCRATCH0_MODE_BOOTLOADER); /* boot to bootloader */

sys/arm/nvidia/tegra124/tegra124_machdep.c

106

reg = bus_space_read_4(fdtbus_bs_tag, pmc, PMC_CONTROL_REG);

sys/arm/nvidia/tegra124/tegra124_machdep.c

109

bus_space_write_4(fdtbus_bs_tag, pmc, PMC_CONTROL_REG, reg | 0x10);

sys/arm/nvidia/tegra124/tegra124_machdep.c

95

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_pmc.c

186

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_pmc.c

191

reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id);

sys/arm/nvidia/tegra124/tegra124_pmc.c

192

if (((reg != 0) && ena) || ((reg == 0) && !ena)) {

sys/arm/nvidia/tegra124/tegra124_pmc.c

198

reg = RD4(sc, PMC_PWRGATE_TOGGLE);

sys/arm/nvidia/tegra124/tegra124_pmc.c

199

if ((reg & PMC_PWRGATE_TOGGLE_START) == 0)

sys/arm/nvidia/tegra124/tegra124_pmc.c

211

reg = RD4(sc, PMC_PWRGATE_TOGGLE);

sys/arm/nvidia/tegra124/tegra124_pmc.c

212

if ((reg & PMC_PWRGATE_TOGGLE_START) == 0)

sys/arm/nvidia/tegra124/tegra124_pmc.c

227

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_pmc.c

238

reg = RD4(sc, PMC_PWRGATE_STATUS);

sys/arm/nvidia/tegra124/tegra124_pmc.c

239

if ((reg & PMC_PWRGATE_STATUS_PARTID(id)) == 0)

sys/arm/nvidia/tegra124/tegra124_pmc.c

251

reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD);

sys/arm/nvidia/tegra124/tegra124_pmc.c

252

if ((reg & PMC_REMOVE_CLAMPING_CMD_PARTID(swid)) == 0)

sys/arm/nvidia/tegra124/tegra124_pmc.c

259

reg = RD4(sc, PMC_CLAMP_STATUS);

sys/arm/nvidia/tegra124/tegra124_pmc.c

260

if ((reg & PMC_CLAMP_STATUS_PARTID(id)) != 0)

sys/arm/nvidia/tegra124/tegra124_pmc.c

270

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_pmc.c

274

reg = RD4(sc, PMC_PWRGATE_STATUS);

sys/arm/nvidia/tegra124/tegra124_pmc.c

275

return ((reg & PMC_PWRGATE_STATUS_PARTID(id)) ? 1 : 0);

sys/arm/nvidia/tegra124/tegra124_pmc.c

482

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_pmc.c

512

reg = RD4(sc, PMC_CNTRL);

sys/arm/nvidia/tegra124/tegra124_pmc.c

513

reg |= PMC_CNTRL_CPU_PWRREQ_OE;

sys/arm/nvidia/tegra124/tegra124_pmc.c

514

WR4(sc, PMC_CNTRL, reg);

sys/arm/nvidia/tegra124/tegra124_pmc.c

517

reg = RD4(sc, PMC_CNTRL);

sys/arm/nvidia/tegra124/tegra124_pmc.c

519

reg &= ~PMC_CNTRL_SYSCLK_POLARITY;

sys/arm/nvidia/tegra124/tegra124_pmc.c

521

reg |= PMC_CNTRL_SYSCLK_POLARITY;

sys/arm/nvidia/tegra124/tegra124_pmc.c

522

WR4(sc, PMC_CNTRL, reg);

sys/arm/nvidia/tegra124/tegra124_pmc.c

525

reg = RD4(sc, PMC_CNTRL);

sys/arm/nvidia/tegra124/tegra124_pmc.c

526

reg |= PMC_CNTRL_SYSCLK_OE;

sys/arm/nvidia/tegra124/tegra124_pmc.c

527

WR4(sc, PMC_CNTRL, reg);

sys/arm/nvidia/tegra124/tegra124_pmc.c

533

reg = RD4(sc, PMC_IO_DPD_STATUS);

sys/arm/nvidia/tegra124/tegra124_pmc.c

534

reg &= ~ PMC_IO_DPD_STATUS_HDMI;

sys/arm/nvidia/tegra124/tegra124_pmc.c

535

WR4(sc, PMC_IO_DPD_STATUS, reg);

sys/arm/nvidia/tegra124/tegra124_pmc.c

537

reg = RD4(sc, PMC_IO_DPD2_STATUS);

sys/arm/nvidia/tegra124/tegra124_pmc.c

538

reg &= ~ PMC_IO_DPD2_STATUS_HV;

sys/arm/nvidia/tegra124/tegra124_pmc.c

539

WR4(sc, PMC_IO_DPD2_STATUS, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

1099

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

1102

reg = tegra_fuse_read_4(FUSE_XUSB_CALIB);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

1103

sc->hs_curr_level_0 = FUSE_XUSB_CALIB_HS_CURR_LEVEL_0(reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

1104

sc->hs_curr_level_123 = FUSE_XUSB_CALIB_HS_CURR_LEVEL_123(reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

1105

sc->hs_iref_cap = FUSE_XUSB_CALIB_HS_IREF_CAP(reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

1106

sc->hs_squelch_level = FUSE_XUSB_CALIB_HS_SQUELCH_LEVEL(reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

1107

sc->hs_term_range_adj = FUSE_XUSB_CALIB_HS_TERM_RANGE_ADJ(reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

291

bus_size_t reg;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

307

.reg = r, \

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

366

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

368

reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

370

reg &= ~SS_PORT_MAP_PORT_INTERNAL(port->idx);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

372

reg |= SS_PORT_MAP_PORT_INTERNAL(port->idx);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

373

reg &= ~SS_PORT_MAP_PORT_MAP(port->idx, ~0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

374

reg |= SS_PORT_MAP_PORT_MAP(port->idx, port->companion);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

375

WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

377

reg = RD4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx));

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

378

reg &= ~IOPHY_USB3_PAD_CTL2_CDR_CNTL(~0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

379

reg &= ~IOPHY_USB3_PAD_CTL2_RX_EQ(~0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

380

reg &= ~IOPHY_USB3_PAD_CTL2_RX_WANDER(~0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

381

reg |= IOPHY_USB3_PAD_CTL2_CDR_CNTL(0x24);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

382

reg |= IOPHY_USB3_PAD_CTL2_RX_EQ(0xF070);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

383

reg |= IOPHY_USB3_PAD_CTL2_RX_WANDER(0xF);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

384

WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx), reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

389

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

390

reg &= ~ELPG_PROGRAM_SSP_ELPG_VCORE_DOWN(port->idx);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

391

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

394

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

395

reg &= ~ELPG_PROGRAM_SSP_ELPG_CLAMP_EN_EARLY(port->idx);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

396

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

399

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

400

reg &= ~ELPG_PROGRAM_SSP_ELPG_CLAMP_EN(port->idx);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

401

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

410

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

413

reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

414

reg &= ~IOPHY_PLL_P0_CTL1_REFCLK_SEL(~0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

415

WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

418

reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

419

reg |= IOPHY_PLL_P0_CTL2_REFCLKBUF_EN;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

420

reg |= IOPHY_PLL_P0_CTL2_TXCLKREF_EN;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

421

reg |= IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

422

WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

425

reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

426

reg |= IOPHY_PLL_P0_CTL1_PLL_RST;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

427

WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

431

reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

432

if (reg & IOPHY_PLL_P0_CTL1_PLL0_LOCKDET)

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

440

reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

441

reg |= USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

442

WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

450

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

452

reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

453

reg &= ~USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

454

WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

456

reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

457

reg &= ~IOPHY_PLL_P0_CTL1_PLL_RST;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

458

WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

468

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

471

reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

472

reg &= ~IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

473

reg &= ~IOPHY_MISC_PAD_S0_CTL1_IDDQ;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

474

WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

476

reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

477

reg &= ~IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

478

reg &= ~IOPHY_PLL_S0_CTL1_PLL_IDDQ;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

479

WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

481

reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

482

reg |= IOPHY_PLL_S0_CTL1_PLL1_MODE;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

483

WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

485

reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

486

reg |= IOPHY_PLL_S0_CTL1_PLL_RST_L;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

487

WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

490

reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

491

if (reg & IOPHY_PLL_S0_CTL1_PLL1_LOCKDET)

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

499

reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

500

reg |= IOPHY_PLL_S0_CTL1_PLL_RST_L;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

501

WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

503

reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

504

reg |= USB3_PAD_MUX_SATA_IDDQ_DISABLE;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

505

WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

513

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

515

reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

516

reg &= ~USB3_PAD_MUX_SATA_IDDQ_DISABLE;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

517

WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

519

reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

520

reg &= ~IOPHY_PLL_S0_CTL1_PLL_RST_L;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

521

WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

524

reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

525

reg &= ~IOPHY_PLL_S0_CTL1_PLL1_MODE;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

526

WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

529

reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

530

reg |= IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

531

reg |= IOPHY_PLL_S0_CTL1_PLL_IDDQ;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

532

WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

535

reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

536

reg |= IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

537

reg |= IOPHY_MISC_PAD_S0_CTL1_IDDQ;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

538

WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

547

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

556

reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

557

reg &= ~USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(~0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

558

reg &= ~USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(~0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

559

reg |= USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(sc->hs_squelch_level);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

560

reg |= USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(5);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

561

WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

563

reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

564

reg &= ~USB2_PORT_CAP_PORT_CAP(lane->idx, ~0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

565

reg |= USB2_PORT_CAP_PORT_CAP(lane->idx, USB2_PORT_CAP_PORT_CAP_HOST);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

566

WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

568

reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx));

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

569

reg &= ~USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(~0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

570

reg &= ~USB2_OTG_PAD_CTL0_HS_SLEW(~0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

571

reg &= ~USB2_OTG_PAD_CTL0_LS_RSLEW(~0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

572

reg &= ~USB2_OTG_PAD_CTL0_PD;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

573

reg &= ~USB2_OTG_PAD_CTL0_PD2;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

574

reg &= ~USB2_OTG_PAD_CTL0_PD_ZI;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

576

reg |= USB2_OTG_PAD_CTL0_HS_SLEW(14);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

578

reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level_0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

579

reg |= USB2_OTG_PAD_CTL0_LS_RSLEW(3);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

581

reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level_123);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

582

reg |= USB2_OTG_PAD_CTL0_LS_RSLEW(0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

584

WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

586

reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx));

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

587

reg &= ~USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(~0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

588

reg &= ~USB2_OTG_PAD_CTL1_HS_IREF_CAP(~0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

589

reg &= ~USB2_OTG_PAD_CTL1_PD_DR;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

590

reg &= ~USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

591

reg &= ~USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

593

reg |= USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(sc->hs_term_range_adj);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

594

reg |= USB2_OTG_PAD_CTL1_HS_IREF_CAP(sc->hs_iref_cap);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

595

WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

605

reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

606

reg &= ~USB2_BIAS_PAD_CTL0_PD;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

607

WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

615

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

624

reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

625

reg |= USB2_BIAS_PAD_CTL0_PD;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

626

WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

642

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

644

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

645

reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

646

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

649

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

650

reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

651

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

654

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

655

reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

656

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

665

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

667

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

668

reg |= ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

669

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

672

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

673

reg |= ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

674

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

677

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

678

reg |= ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

679

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

847

uint32_t reg;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

849

reg = RD4(sc, lane->reg);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

850

reg &= ~(lane->mask << lane->shift);

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

851

reg |= (lane->mux_idx & lane->mask) << lane->shift;

sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c

852

WR4(sc, lane->reg, reg);

sys/arm/nvidia/tegra_ahci.c

614

uint32_t reg;

sys/arm/nvidia/tegra_ahci.c

623

reg = AHCI_RD4(sc, T_AHCI_HBA_CAP_BKDR);

sys/arm/nvidia/tegra_ahci.c

624

reg &= ~T_AHCI_HBA_CAP_BKDR_NUM_PORTS(~0);

sys/arm/nvidia/tegra_ahci.c

625

reg |= T_AHCI_HBA_CAP_BKDR_NUM_PORTS(0);

sys/arm/nvidia/tegra_ahci.c

626

reg |= T_AHCI_HBA_CAP_BKDR_EXT_SATA;

sys/arm/nvidia/tegra_ahci.c

627

reg |= T_AHCI_HBA_CAP_BKDR_CMD_CMPL_COALESING;

sys/arm/nvidia/tegra_ahci.c

628

reg |= T_AHCI_HBA_CAP_BKDR_FIS_SWITCHING;

sys/arm/nvidia/tegra_ahci.c

629

reg |= T_AHCI_HBA_CAP_BKDR_SUPP_PM;

sys/arm/nvidia/tegra_ahci.c

630

reg |= T_AHCI_HBA_CAP_BKDR_SUPP_CLO;

sys/arm/nvidia/tegra_ahci.c

631

reg |= T_AHCI_HBA_CAP_BKDR_SUPP_STG_SPUP;

sys/arm/nvidia/tegra_ahci.c

632

AHCI_WR4(sc, T_AHCI_HBA_CAP_BKDR, reg);

sys/arm/nvidia/tegra_ahci.c

635

reg = AHCI_RD4(sc, T_AHCI_PORT_BKDR);

sys/arm/nvidia/tegra_ahci.c

636

reg |= T_AHCI_PORT_BKDR_COLD_PRSN_DET;

sys/arm/nvidia/tegra_ahci.c

637

reg |= T_AHCI_PORT_BKDR_HOTPLUG_CAP;

sys/arm/nvidia/tegra_ahci.c

638

reg |= T_AHCI_PORT_BKDR_EXT_SATA_SUPP;

sys/arm/nvidia/tegra_ahci.c

639

AHCI_WR4(sc, T_AHCI_PORT_BKDR, reg);

sys/arm/nvidia/tegra_efuse.c

278

uint32_t reg;

sys/arm/nvidia/tegra_efuse.c

284

reg = RD4(sc, TEGRA210_FUSE_SPARE + 2 * 4);

sys/arm/nvidia/tegra_efuse.c

285

val |= (reg & 1) << 0;

sys/arm/nvidia/tegra_efuse.c

286

reg = RD4(sc, TEGRA210_FUSE_SPARE + 3 * 4);

sys/arm/nvidia/tegra_efuse.c

287

val |= (reg & 1) << 1;

sys/arm/nvidia/tegra_efuse.c

288

reg = RD4(sc, TEGRA210_FUSE_SPARE + 4 * 4);

sys/arm/nvidia/tegra_efuse.c

289

val |= (reg & 1) << 2;

sys/arm/nvidia/tegra_gpio.c

148

gpio_write_masked(struct tegra_gpio_softc *sc, bus_size_t reg,

sys/arm/nvidia/tegra_gpio.c

157

bus_write_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin), tmp);

sys/arm/nvidia/tegra_gpio.c

161

gpio_read(struct tegra_gpio_softc *sc, bus_size_t reg, struct gpio_pin *pin)

sys/arm/nvidia/tegra_gpio.c

167

val = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin));

sys/arm/nvidia/tegra_gpio.c

340

intr_write_masked(struct tegra_gpio_softc *sc, bus_addr_t reg,

sys/arm/nvidia/tegra_gpio.c

349

bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp);

sys/arm/nvidia/tegra_gpio.c

353

intr_write_modify(struct tegra_gpio_softc *sc, bus_addr_t reg,

sys/arm/nvidia/tegra_gpio.c

361

tmp = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq));

sys/arm/nvidia/tegra_gpio.c

364

bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp);

sys/arm/nvidia/tegra_gpio.c

497

uint32_t reg;

sys/arm/nvidia/tegra_gpio.c

517

reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH;

sys/arm/nvidia/tegra_gpio.c

519

reg = GPIO_INT_LVL_EDGE;

sys/arm/nvidia/tegra_gpio.c

521

reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_DELTA;

sys/arm/nvidia/tegra_gpio.c

523

reg = GPIO_INT_LVL_HIGH;

sys/arm/nvidia/tegra_gpio.c

525

reg = 0;

sys/arm/nvidia/tegra_gpio.c

531

*regp = reg;

sys/arm/nvidia/tegra_gpio.c

540

uint32_t reg;

sys/arm/nvidia/tegra_gpio.c

547

reg = 0;

sys/arm/nvidia/tegra_gpio.c

550

reg = GPIO_INT_LVL_HIGH;

sys/arm/nvidia/tegra_gpio.c

553

reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH;

sys/arm/nvidia/tegra_gpio.c

556

reg = GPIO_INT_LVL_EDGE;

sys/arm/nvidia/tegra_gpio.c

559

reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_DELTA;

sys/arm/nvidia/tegra_gpio.c

566

*regp = reg;

sys/arm/nvidia/tegra_i2c.c

240

uint32_t reg;

sys/arm/nvidia/tegra_i2c.c

242

reg = RD4(sc, I2C_FIFO_CONTROL);

sys/arm/nvidia/tegra_i2c.c

243

reg |= I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH;

sys/arm/nvidia/tegra_i2c.c

244

WR4(sc, I2C_FIFO_CONTROL, reg);

sys/arm/nvidia/tegra_i2c.c

248

reg = RD4(sc, I2C_FIFO_CONTROL);

sys/arm/nvidia/tegra_i2c.c

249

reg &= I2C_FIFO_CONTROL_TX_FIFO_FLUSH |

sys/arm/nvidia/tegra_i2c.c

251

if (reg == 0)

sys/arm/nvidia/tegra_i2c.c

281

uint32_t reg, status;

sys/arm/nvidia/tegra_i2c.c

296

reg = RD4(sc, I2C_BUS_CLEAR_CONFIG);

sys/arm/nvidia/tegra_i2c.c

297

reg |= I2C_BUS_CLEAR_CONFIG_BC_ENABLE;

sys/arm/nvidia/tegra_i2c.c

298

WR4(sc, I2C_BUS_CLEAR_CONFIG,reg);

sys/arm/nvidia/tegra_i2c.c

358

uint32_t reg;

sys/arm/nvidia/tegra_i2c.c

365

reg = RD4(sc, I2C_FIFO_STATUS);

sys/arm/nvidia/tegra_i2c.c

366

if (I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT(reg) == 0)

sys/arm/nvidia/tegra_i2c.c

369

reg = 0;

sys/arm/nvidia/tegra_i2c.c

371

reg |= sc->msg->buf[sc->msg_idx] << (i * 8);

sys/arm/nvidia/tegra_i2c.c

374

WR4(sc, I2C_TX_PACKET_FIFO, reg);

sys/arm/nvidia/tegra_i2c.c

384

uint32_t reg;

sys/arm/nvidia/tegra_i2c.c

391

reg = RD4(sc, I2C_FIFO_STATUS);

sys/arm/nvidia/tegra_i2c.c

392

if (I2C_FIFO_STATUS_RX_FIFO_FULL_CNT(reg) == 0)

sys/arm/nvidia/tegra_i2c.c

395

reg = RD4(sc, I2C_RX_FIFO);

sys/arm/nvidia/tegra_i2c.c

397

sc->msg->buf[sc->msg_idx] = (reg >> (i * 8)) & 0xFF;

sys/arm/nvidia/tegra_i2c.c

411

uint32_t status, reg;

sys/arm/nvidia/tegra_i2c.c

420

reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER);

sys/arm/nvidia/tegra_i2c.c

421

reg &= ~I2C_INT_TFIFO_DATA_REQ;

sys/arm/nvidia/tegra_i2c.c

422

reg &= ~I2C_INT_RFIFO_DATA_REQ;

sys/arm/nvidia/tegra_i2c.c

442

reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER);

sys/arm/nvidia/tegra_i2c.c

443

reg &= ~I2C_INT_RFIFO_DATA_REQ;

sys/arm/nvidia/tegra_i2c.c

444

WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg);

sys/arm/nvidia/tegra_i2c.c

450

reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER);

sys/arm/nvidia/tegra_i2c.c

451

reg &= ~I2C_INT_TFIFO_DATA_REQ;

sys/arm/nvidia/tegra_i2c.c

452

WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg);

sys/arm/nvidia/tegra_i2c.c

458

reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER);

sys/arm/nvidia/tegra_i2c.c

459

reg &= ~I2C_INT_TFIFO_DATA_REQ;

sys/arm/nvidia/tegra_i2c.c

460

reg &= ~I2C_INT_RFIFO_DATA_REQ;

sys/arm/nvidia/tegra_i2c.c

461

WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg);

sys/arm/nvidia/tegra_pcie.c

1122

uint32_t reg;

sys/arm/nvidia/tegra_pcie.c

1126

reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,

sys/arm/nvidia/tegra_pcie.c

1128

reg &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;

sys/arm/nvidia/tegra_pcie.c

1129

reg |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;

sys/arm/nvidia/tegra_pcie.c

1131

RP_PRIV_MISC, reg, 4);

sys/arm/nvidia/tegra_pcie.c

1134

reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,

sys/arm/nvidia/tegra_pcie.c

1136

if (reg & RP_VEND_XP_DL_UP)

sys/arm/nvidia/tegra_pcie.c

1144

reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,

sys/arm/nvidia/tegra_pcie.c

1146

if (reg & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)

sys/arm/nvidia/tegra_pcie.c

1160

uint32_t reg;

sys/arm/nvidia/tegra_pcie.c

1166

reg = AFI_RD4(sc, port->afi_pex_ctrl);

sys/arm/nvidia/tegra_pcie.c

1167

reg &= ~AFI_PEX_CTRL_RST_L;

sys/arm/nvidia/tegra_pcie.c

1168

AFI_WR4(sc, port->afi_pex_ctrl, reg);

sys/arm/nvidia/tegra_pcie.c

1173

reg |= AFI_PEX_CTRL_REFCLK_EN;

sys/arm/nvidia/tegra_pcie.c

1174

reg |= AFI_PEX_CTRL_CLKREQ_EN;

sys/arm/nvidia/tegra_pcie.c

1175

reg |= AFI_PEX_CTRL_OVERRIDE_EN;

sys/arm/nvidia/tegra_pcie.c

1176

AFI_WR4(sc, port->afi_pex_ctrl, reg);

sys/arm/nvidia/tegra_pcie.c

1181

reg |= AFI_PEX_CTRL_RST_L;

sys/arm/nvidia/tegra_pcie.c

1182

AFI_WR4(sc, port->afi_pex_ctrl, reg);

sys/arm/nvidia/tegra_pcie.c

1185

reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,

sys/arm/nvidia/tegra_pcie.c

1187

reg |= RP_VEND_CTL2_PCA_ENABLE;

sys/arm/nvidia/tegra_pcie.c

1189

RP_VEND_CTL2, reg, 4);

sys/arm/nvidia/tegra_pcie.c

1204

uint32_t reg;

sys/arm/nvidia/tegra_pcie.c

1209

reg = AFI_RD4(sc, port->afi_pex_ctrl);

sys/arm/nvidia/tegra_pcie.c

1210

reg &= ~AFI_PEX_CTRL_RST_L;

sys/arm/nvidia/tegra_pcie.c

1211

AFI_WR4(sc, port->afi_pex_ctrl, reg);

sys/arm/nvidia/tegra_pcie.c

1216

reg &= ~AFI_PEX_CTRL_CLKREQ_EN;

sys/arm/nvidia/tegra_pcie.c

1217

reg &= ~AFI_PEX_CTRL_REFCLK_EN;

sys/arm/nvidia/tegra_pcie.c

1218

AFI_WR4(sc, port->afi_pex_ctrl, reg);

sys/arm/nvidia/tegra_pcie.c

1248

uint32_t reg;

sys/arm/nvidia/tegra_pcie.c

1257

reg = AFI_RD4(sc, AFI_PLLE_CONTROL);

sys/arm/nvidia/tegra_pcie.c

1258

reg &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;

sys/arm/nvidia/tegra_pcie.c

1259

reg |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;

sys/arm/nvidia/tegra_pcie.c

1260

AFI_WR4(sc, AFI_PLLE_CONTROL, reg);

sys/arm/nvidia/tegra_pcie.c

1266

reg = AFI_RD4(sc, AFI_PCIE_CONFIG);

sys/arm/nvidia/tegra_pcie.c

1267

reg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;

sys/arm/nvidia/tegra_pcie.c

1272

reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1;

sys/arm/nvidia/tegra_pcie.c

1277

reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1;

sys/arm/nvidia/tegra_pcie.c

1282

reg |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL;

sys/arm/nvidia/tegra_pcie.c

1285

reg &=

sys/arm/nvidia/tegra_pcie.c

1288

AFI_WR4(sc, AFI_PCIE_CONFIG, reg);

sys/arm/nvidia/tegra_pcie.c

1291

reg = AFI_RD4(sc, AFI_FUSE);

sys/arm/nvidia/tegra_pcie.c

1292

reg &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;

sys/arm/nvidia/tegra_pcie.c

1293

AFI_WR4(sc, AFI_FUSE, reg);

sys/arm/nvidia/tegra_pcie.c

1319

reg = AFI_RD4(sc, AFI_CONFIGURATION);

sys/arm/nvidia/tegra_pcie.c

1320

reg |= AFI_CONFIGURATION_EN_FPCI;

sys/arm/nvidia/tegra_pcie.c

1321

AFI_WR4(sc, AFI_CONFIGURATION, reg);

sys/arm/nvidia/tegra_pcie.c

1324

reg = 0;

sys/arm/nvidia/tegra_pcie.c

1325

reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_SLVERR);

sys/arm/nvidia/tegra_pcie.c

1326

reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_DECERR);

sys/arm/nvidia/tegra_pcie.c

1327

reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_SLVERR);

sys/arm/nvidia/tegra_pcie.c

1328

reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_DECERR);

sys/arm/nvidia/tegra_pcie.c

1329

reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_WRERR);

sys/arm/nvidia/tegra_pcie.c

1330

reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_SM_MSG);

sys/arm/nvidia/tegra_pcie.c

1331

reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_DFPCI_DECERR);

sys/arm/nvidia/tegra_pcie.c

1332

reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_AXI_DECERR);

sys/arm/nvidia/tegra_pcie.c

1333

reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT);

sys/arm/nvidia/tegra_pcie.c

1334

reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE);

sys/arm/nvidia/tegra_pcie.c

1335

reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE);

sys/arm/nvidia/tegra_pcie.c

1336

reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE);

sys/arm/nvidia/tegra_pcie.c

1337

reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE);

sys/arm/nvidia/tegra_pcie.c

1338

reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_P2P_ERROR);

sys/arm/nvidia/tegra_pcie.c

1339

AFI_WR4(sc, AFI_AFI_INTR_ENABLE, reg);

sys/arm/nvidia/tegra_pcie.c

1382

uint32_t reg;

sys/arm/nvidia/tegra_pcie.c

1414

reg = AFI_RD4(sc, AFI_INTR_MASK);

sys/arm/nvidia/tegra_pcie.c

1415

reg |= AFI_INTR_MASK_MSI_MASK;

sys/arm/nvidia/tegra_pcie.c

1416

AFI_WR4(sc, AFI_INTR_MASK, reg);

sys/arm/nvidia/tegra_pcie.c

226

#define PCI_CFG_EXT_REG(reg) ((((reg) >> 8) & 0x0f) << 24)

sys/arm/nvidia/tegra_pcie.c

230

#define PCI_CFG_BASE_REG(reg) ((reg) & 0xff)

sys/arm/nvidia/tegra_pcie.c

389

u_int func, u_int reg)

sys/arm/nvidia/tegra_pcie.c

396

PCI_CFG_EXT_REG(reg);

sys/arm/nvidia/tegra_pcie.c

417

u_int reg, int bytes)

sys/arm/nvidia/tegra_pcie.c

433

off = reg & 0xFFF;

sys/arm/nvidia/tegra_pcie.c

440

rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg);

sys/arm/nvidia/tegra_pcie.c

444

off = PCI_CFG_BASE_REG(reg);

sys/arm/nvidia/tegra_pcie.c

466

u_int reg, uint32_t val, int bytes)

sys/arm/nvidia/tegra_pcie.c

482

off = reg & 0xFFF;

sys/arm/nvidia/tegra_pcie.c

489

rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg);

sys/arm/nvidia/tegra_pcie.c

493

off = PCI_CFG_BASE_REG(reg);

sys/arm/nvidia/tegra_pcie.c

588

uint32_t reg;

sys/arm/nvidia/tegra_pcie.c

596

reg = AFI_RD4(sc, AFI_MSI_EN_VEC(offs));

sys/arm/nvidia/tegra_pcie.c

598

reg |= bit;

sys/arm/nvidia/tegra_pcie.c

600

reg &= ~bit;

sys/arm/nvidia/tegra_pcie.c

601

AFI_WR4(sc, AFI_MSI_EN_VEC(offs), reg);

sys/arm/nvidia/tegra_pcie.c

607

u_int irq, i, bit, reg;

sys/arm/nvidia/tegra_pcie.c

616

reg = AFI_RD4(sc, AFI_MSI_VEC(i));

sys/arm/nvidia/tegra_pcie.c

618

while (reg != 0) {

sys/arm/nvidia/tegra_pcie.c

619

bit = ffs(reg) - 1;

sys/arm/nvidia/tegra_pcie.c

630

reg = AFI_RD4(sc, AFI_MSI_VEC(i));

sys/arm/nvidia/tegra_pinmux.c

167

bus_size_t reg;

sys/arm/nvidia/tegra_pinmux.c

175

.reg = r, \

sys/arm/nvidia/tegra_pinmux.c

183

.reg = r, \

sys/arm/nvidia/tegra_pinmux.c

384

bus_size_t reg;

sys/arm/nvidia/tegra_pinmux.c

394

.reg = r - 0x868, \

sys/arm/nvidia/tegra_pinmux.c

486

uint32_t reg;

sys/arm/nvidia/tegra_pinmux.c

488

reg = bus_read_4(sc->mux_mem_res, mux->reg);

sys/arm/nvidia/tegra_pinmux.c

498

reg &= ~(TEGRA_MUX_FUNCTION_MASK << TEGRA_MUX_FUNCTION_SHIFT);

sys/arm/nvidia/tegra_pinmux.c

499

reg |= (tmp & TEGRA_MUX_FUNCTION_MASK) <<

sys/arm/nvidia/tegra_pinmux.c

503

reg &= ~(TEGRA_MUX_PUPD_MASK << TEGRA_MUX_PUPD_SHIFT);

sys/arm/nvidia/tegra_pinmux.c

504

reg |= (cfg->params[PROP_ID_PULL] & TEGRA_MUX_PUPD_MASK) <<

sys/arm/nvidia/tegra_pinmux.c

508

reg &= ~(1 << TEGRA_MUX_TRISTATE_SHIFT);

sys/arm/nvidia/tegra_pinmux.c

509

reg |= (cfg->params[PROP_ID_TRISTATE] & 1) <<

sys/arm/nvidia/tegra_pinmux.c

513

reg &= ~(1 << TEGRA_MUX_ENABLE_INPUT_SHIFT);

sys/arm/nvidia/tegra_pinmux.c

514

reg |= (cfg->params[TEGRA_MUX_ENABLE_INPUT_SHIFT] & 1) <<

sys/arm/nvidia/tegra_pinmux.c

518

reg &= ~(1 << TEGRA_MUX_ENABLE_INPUT_SHIFT);

sys/arm/nvidia/tegra_pinmux.c

519

reg |= (cfg->params[PROP_ID_ENABLE_INPUT] & 1) <<

sys/arm/nvidia/tegra_pinmux.c

523

reg &= ~(1 << TEGRA_MUX_ENABLE_INPUT_SHIFT);

sys/arm/nvidia/tegra_pinmux.c

524

reg |= (cfg->params[PROP_ID_OPEN_DRAIN] & 1) <<

sys/arm/nvidia/tegra_pinmux.c

528

reg &= ~(1 << TEGRA_MUX_LOCK_SHIFT);

sys/arm/nvidia/tegra_pinmux.c

529

reg |= (cfg->params[PROP_ID_LOCK] & 1) <<

sys/arm/nvidia/tegra_pinmux.c

533

reg &= ~(1 << TEGRA_MUX_IORESET_SHIFT);

sys/arm/nvidia/tegra_pinmux.c

534

reg |= (cfg->params[PROP_ID_IORESET] & 1) <<

sys/arm/nvidia/tegra_pinmux.c

538

reg &= ~(1 << TEGRA_MUX_RCV_SEL_SHIFT);

sys/arm/nvidia/tegra_pinmux.c

539

reg |= (cfg->params[PROP_ID_RCV_SEL] & 1) <<

sys/arm/nvidia/tegra_pinmux.c

542

bus_write_4(sc->mux_mem_res, mux->reg, reg);

sys/arm/nvidia/tegra_pinmux.c

550

uint32_t reg;

sys/arm/nvidia/tegra_pinmux.c

552

reg = bus_read_4(sc->pad_mem_res, grp->reg);

sys/arm/nvidia/tegra_pinmux.c

555

reg &= ~(1 << TEGRA_GRP_HSM_SHIFT);

sys/arm/nvidia/tegra_pinmux.c

556

reg |= (cfg->params[PROP_ID_HIGH_SPEED_MODE] & 1) <<

sys/arm/nvidia/tegra_pinmux.c

560

reg &= ~(1 << TEGRA_GRP_SCHMT_SHIFT);

sys/arm/nvidia/tegra_pinmux.c

561

reg |= (cfg->params[PROP_ID_SCHMITT] & 1) <<

sys/arm/nvidia/tegra_pinmux.c

565

reg &= ~(TEGRA_GRP_DRV_TYPE_MASK << TEGRA_GRP_DRV_TYPE_SHIFT);

sys/arm/nvidia/tegra_pinmux.c

566

reg |= (cfg->params[PROP_ID_DRIVE_TYPE] &

sys/arm/nvidia/tegra_pinmux.c

570

reg &= ~(TEGRA_GRP_DRV_DRVDN_SLWR_MASK <<

sys/arm/nvidia/tegra_pinmux.c

572

reg |= (cfg->params[PROP_ID_SLEW_RATE_RISING] &

sys/arm/nvidia/tegra_pinmux.c

577

reg &= ~(TEGRA_GRP_DRV_DRVUP_SLWF_MASK <<

sys/arm/nvidia/tegra_pinmux.c

579

reg |= (cfg->params[PROP_ID_SLEW_RATE_FALLING] &

sys/arm/nvidia/tegra_pinmux.c

585

reg &= ~(grp->drvdn_shift << grp->drvdn_mask);

sys/arm/nvidia/tegra_pinmux.c

586

reg |= (cfg->params[PROP_ID_DRIVE_DOWN_STRENGTH] &

sys/arm/nvidia/tegra_pinmux.c

591

reg &= ~(grp->drvup_shift << grp->drvup_mask);

sys/arm/nvidia/tegra_pinmux.c

592

reg |= (cfg->params[PROP_ID_DRIVE_UP_STRENGTH] &

sys/arm/nvidia/tegra_pinmux.c

595

bus_write_4(sc->pad_mem_res, grp->reg, reg);

sys/arm/nvidia/tegra_pinmux.c

604

uint32_t reg;

sys/arm/nvidia/tegra_pinmux.c

613

reg = bus_read_4(sc->mipi_mem_res, 0); /* register 0x820 */

sys/arm/nvidia/tegra_pinmux.c

615

reg &= ~(1 << 1);

sys/arm/nvidia/tegra_pinmux.c

617

reg |= (1 << 1);

sys/arm/nvidia/tegra_pinmux.c

618

bus_write_4(sc->mipi_mem_res, 0, reg); /* register 0x820 */

sys/arm/nvidia/tegra_soctherm.c

376

extract_signed(uint32_t reg, int shift, int bits)

sys/arm/nvidia/tegra_soctherm.c

382

val = ((reg >> shift) & mask) << (32 - bits);

sys/arm/nvidia/tegra_usbphy.c

313

reg_wait(struct usbphy_softc *sc, uint32_t reg, uint32_t mask, uint32_t val)

sys/arm/nvidia/tegra_usbphy.c

318

if ((RD4(sc, reg) & mask) == val)

sys/arm/nvidia/tegra_xhci.c

578

uint32_t reg;

sys/arm/nvidia/tegra_xhci.c

580

reg = ARU_MAILBOX_DATA_IN_TYPE(cmd) | ARU_MAILBOX_DATA_IN_DATA(data);

sys/arm/nvidia/tegra_xhci.c

581

FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_IN, reg);

sys/arm/nvidia/tegra_xhci.c

583

reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD);

sys/arm/nvidia/tegra_xhci.c

584

reg |= ARU_MAILBOX_CMD_DEST_FALC | ARU_MAILBOX_CMD_INT_EN;

sys/arm/nvidia/tegra_xhci.c

585

FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg);

sys/arm/nvidia/tegra_xhci.c

592

uint32_t reg;

sys/arm/nvidia/tegra_xhci.c

595

reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER);

sys/arm/nvidia/tegra_xhci.c

596

if (reg != ARU_MAILBOX_OWNER_NONE) {

sys/arm/nvidia/tegra_xhci.c

598

"CPU mailbox is busy: 0x%08X\n", reg);

sys/arm/nvidia/tegra_xhci.c

603

reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER);

sys/arm/nvidia/tegra_xhci.c

604

if (reg != ARU_MAILBOX_OWNER_SW) {

sys/arm/nvidia/tegra_xhci.c

606

"Cannot acquire CPU mailbox: 0x%08X\n", reg);

sys/arm/nvidia/tegra_xhci.c

609

reg = ARU_MAILBOX_DATA_IN_TYPE(cmd) | ARU_MAILBOX_DATA_IN_DATA(data);

sys/arm/nvidia/tegra_xhci.c

610

FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_IN, reg);

sys/arm/nvidia/tegra_xhci.c

612

reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD);

sys/arm/nvidia/tegra_xhci.c

613

reg |= ARU_MAILBOX_CMD_DEST_FALC | ARU_MAILBOX_CMD_INT_EN;

sys/arm/nvidia/tegra_xhci.c

614

FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg);

sys/arm/nvidia/tegra_xhci.c

617

reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER);

sys/arm/nvidia/tegra_xhci.c

618

if (reg == ARU_MAILBOX_OWNER_NONE)

sys/arm/nvidia/tegra_xhci.c

624

"Command response timeout: 0x%08X\n", reg);

sys/arm/nvidia/tegra_xhci.c

710

uint32_t reg, msg, resp_cmd, resp_data;

sys/arm/nvidia/tegra_xhci.c

715

reg = FPCI_RD4(sc, XUSB_CFG_ARU_SMI_INTR);

sys/arm/nvidia/tegra_xhci.c

716

FPCI_WR4(sc, XUSB_CFG_ARU_SMI_INTR, reg);

sys/arm/nvidia/tegra_xhci.c

717

if (reg & ARU_SMI_INTR_FW_HANG) {

sys/arm/nvidia/tegra_xhci.c

733

reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD);

sys/arm/nvidia/tegra_xhci.c

734

reg &= ~ARU_MAILBOX_CMD_DEST_SMI;

sys/arm/nvidia/tegra_xhci.c

735

FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg);

sys/arm/nvidia/tegra_xhci.c

861

uint32_t reg;

sys/arm/nvidia/tegra_xhci.c

867

reg = IPFS_RD4(sc, XUSB_HOST_CONFIGURATION);

sys/arm/nvidia/tegra_xhci.c

868

reg |= CONFIGURATION_EN_FPCI;

sys/arm/nvidia/tegra_xhci.c

869

IPFS_WR4(sc, XUSB_HOST_CONFIGURATION, reg);

sys/arm/nvidia/tegra_xhci.c

873

reg = FPCI_RD4(sc, T_XUSB_CFG_4);

sys/arm/nvidia/tegra_xhci.c

874

reg &= ~CFG_4_BASE_ADDRESS(~0);

sys/arm/nvidia/tegra_xhci.c

875

reg |= CFG_4_BASE_ADDRESS((uint32_t)base_addr >> 15);

sys/arm/nvidia/tegra_xhci.c

876

FPCI_WR4(sc, T_XUSB_CFG_4, reg);

sys/arm/nvidia/tegra_xhci.c

880

reg = FPCI_RD4(sc, T_XUSB_CFG_1);

sys/arm/nvidia/tegra_xhci.c

881

reg |= CFG_1_IO_SPACE;

sys/arm/nvidia/tegra_xhci.c

882

reg |= CFG_1_MEMORY_SPACE;

sys/arm/nvidia/tegra_xhci.c

883

reg |= CFG_1_BUS_MASTER;

sys/arm/nvidia/tegra_xhci.c

884

FPCI_WR4(sc, T_XUSB_CFG_1, reg);

sys/arm/nvidia/tegra_xhci.c

887

reg = IPFS_RD4(sc, XUSB_HOST_INTR_MASK);

sys/arm/nvidia/tegra_xhci.c

888

reg |= INTR_IP_INT_MASK;

sys/arm/nvidia/tegra_xhci.c

889

IPFS_WR4(sc, XUSB_HOST_INTR_MASK, reg);

sys/arm/qemu/virt_mp.c

50

virt_start_ap(u_int id, phandle_t node, u_int addr_cells, pcell_t *reg)

sys/arm/qemu/virt_mp.c

58

err = psci_cpu_on(*reg, pmap_kextract((vm_offset_t)mpentry), id);

sys/arm/rockchip/rk32xx_mp.c

120

rk32xx_start_ap(u_int id, phandle_t node, u_int addr_cells, pcell_t *reg)

sys/arm/rockchip/rk32xx_mp.c

137

mask = 1 << (*reg & 0x0f);

sys/arm/rockchip/rk32xx_mp.c

142

*reg, id);

sys/arm/rockchip/rk32xx_mp.c

147

rv = psci_cpu_on(*reg, pmap_kextract((vm_offset_t)mpentry), id);

sys/arm/ti/aintc.c

86

#define aintc_read_4(_sc, reg) \

sys/arm/ti/aintc.c

87

bus_space_read_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg))

sys/arm/ti/aintc.c

88

#define aintc_write_4(_sc, reg, val) \

sys/arm/ti/aintc.c

89

bus_space_write_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg), (val))

sys/arm/ti/am335x/am3359_cppi41.c

125

uint32_t reg, reset_bit, timeout=10;

sys/arm/ti/am335x/am3359_cppi41.c

155

reg = ti_am3359_cppi41_read_4(dev, sysc_address);

sys/arm/ti/am335x/am3359_cppi41.c

156

if ((reg & reset_bit) && timeout--) {

sys/arm/ti/am335x/am3359_cppi41.c

159

reg = ti_am3359_cppi41_read_4(dev, sysc_address);

sys/arm/ti/am335x/am335x_dmtimer.c

88

#define DMTIMER_READ4(sc, reg) bus_read_4((sc)->tmr_mem_res, (reg))

sys/arm/ti/am335x/am335x_dmtimer.c

89

#define DMTIMER_WRITE4(sc, reg, val) bus_write_4((sc)->tmr_mem_res, (reg), (val))

sys/arm/ti/am335x/am335x_dmtpps.c

145

#define DMTIMER_READ4(sc, reg) bus_read_4((sc)->mem_res, (reg))

sys/arm/ti/am335x/am335x_dmtpps.c

146

#define DMTIMER_WRITE4(sc, reg, val) bus_write_4((sc)->mem_res, (reg), (val))

sys/arm/ti/am335x/am335x_ecap.c

110

uint16_t reg;

sys/arm/ti/am335x/am335x_ecap.c

125

reg = ECAP_READ2(sc, ECAP_ECCTL2);

sys/arm/ti/am335x/am335x_ecap.c

126

reg |= ECCTL2_MODE_APWM | ECCTL2_TSCTRSTOP_FREERUN | ECCTL2_SYNCO_SEL;

sys/arm/ti/am335x/am335x_ecap.c

127

ECAP_WRITE2(sc, ECAP_ECCTL2, reg);

sys/arm/ti/am335x/am335x_ecap.c

57

#define ECAP_READ2(_sc, reg) bus_read_2((_sc)->sc_mem_res, reg);

sys/arm/ti/am335x/am335x_ecap.c

58

#define ECAP_WRITE2(_sc, reg, value) \

sys/arm/ti/am335x/am335x_ecap.c

59

bus_write_2((_sc)->sc_mem_res, reg, value);

sys/arm/ti/am335x/am335x_ecap.c

60

#define ECAP_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg);

sys/arm/ti/am335x/am335x_ecap.c

61

#define ECAP_WRITE4(_sc, reg, value) \

sys/arm/ti/am335x/am335x_ecap.c

62

bus_write_4((_sc)->sc_mem_res, reg, value);

sys/arm/ti/am335x/am335x_ehrpwm.c

458

uint16_t reg;

sys/arm/ti/am335x/am335x_ehrpwm.c

473

reg = EPWM_READ2(sc, EPWM_TBCTL);

sys/arm/ti/am335x/am335x_ehrpwm.c

474

reg &= ~(TBCTL_CLKDIV_MASK | TBCTL_HSPCLKDIV_MASK);

sys/arm/ti/am335x/am335x_ehrpwm.c

475

EPWM_WRITE2(sc, EPWM_TBCTL, reg);

sys/arm/ti/am335x/am335x_ehrpwm.c

486

reg = EPWM_READ2(sc, EPWM_DBCTL);

sys/arm/ti/am335x/am335x_ehrpwm.c

487

reg &= ~DBCTL_MASK;

sys/arm/ti/am335x/am335x_ehrpwm.c

488

reg |= DBCTL_BYPASS;

sys/arm/ti/am335x/am335x_ehrpwm.c

489

EPWM_WRITE2(sc, EPWM_DBCTL, reg);

sys/arm/ti/am335x/am335x_ehrpwm.c

495

reg = EPWM_READ2(sc, EPWM_PCCTL);

sys/arm/ti/am335x/am335x_ehrpwm.c

496

reg &= ~PCCTL_CHPEN_MASK;

sys/arm/ti/am335x/am335x_ehrpwm.c

497

reg |= PCCTL_CHPEN_DISABLE;

sys/arm/ti/am335x/am335x_ehrpwm.c

508

reg = EPWM_READ2(sc, EPWM_TZFLG);

sys/arm/ti/am335x/am335x_ehrpwm.c

511

reg &= ~TBCTL_CTRMODE_MASK;

sys/arm/ti/am335x/am335x_ehrpwm.c

512

reg |= TBCTL_CTRMODE_UP | TBCTL_FREERUN;

sys/arm/ti/am335x/am335x_ehrpwm.c

513

EPWM_WRITE2(sc, EPWM_TBCTL, reg);

sys/arm/ti/am335x/am335x_ehrpwm.c

69

#define EPWM_READ2(_sc, reg) bus_read_2((_sc)->sc_mem_res, reg)

sys/arm/ti/am335x/am335x_ehrpwm.c

70

#define EPWM_WRITE2(_sc, reg, value) \

sys/arm/ti/am335x/am335x_ehrpwm.c

71

bus_write_2((_sc)->sc_mem_res, reg, value)

sys/arm/ti/am335x/am335x_lcd.c

182

#define LCD_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg);

sys/arm/ti/am335x/am335x_lcd.c

183

#define LCD_WRITE4(_sc, reg, value) \

sys/arm/ti/am335x/am335x_lcd.c

184

bus_write_4((_sc)->sc_mem_res, reg, value);

sys/arm/ti/am335x/am335x_lcd.c

522

uint32_t reg;

sys/arm/ti/am335x/am335x_lcd.c

524

reg = LCD_READ4(sc, LCD_IRQSTATUS);

sys/arm/ti/am335x/am335x_lcd.c

525

LCD_WRITE4(sc, LCD_IRQSTATUS, reg);

sys/arm/ti/am335x/am335x_lcd.c

527

reg = LCD_READ4(sc, LCD_IRQSTATUS);

sys/arm/ti/am335x/am335x_lcd.c

529

if (reg & IRQ_SYNC_LOST) {

sys/arm/ti/am335x/am335x_lcd.c

530

reg = LCD_READ4(sc, LCD_RASTER_CTRL);

sys/arm/ti/am335x/am335x_lcd.c

531

reg &= ~RASTER_CTRL_LCDEN;

sys/arm/ti/am335x/am335x_lcd.c

532

LCD_WRITE4(sc, LCD_RASTER_CTRL, reg);

sys/arm/ti/am335x/am335x_lcd.c

534

reg = LCD_READ4(sc, LCD_RASTER_CTRL);

sys/arm/ti/am335x/am335x_lcd.c

535

reg |= RASTER_CTRL_LCDEN;

sys/arm/ti/am335x/am335x_lcd.c

536

LCD_WRITE4(sc, LCD_RASTER_CTRL, reg);

sys/arm/ti/am335x/am335x_lcd.c

540

if (reg & IRQ_PL) {

sys/arm/ti/am335x/am335x_lcd.c

541

reg = LCD_READ4(sc, LCD_RASTER_CTRL);

sys/arm/ti/am335x/am335x_lcd.c

542

reg &= ~RASTER_CTRL_LCDEN;

sys/arm/ti/am335x/am335x_lcd.c

543

LCD_WRITE4(sc, LCD_RASTER_CTRL, reg);

sys/arm/ti/am335x/am335x_lcd.c

545

reg = LCD_READ4(sc, LCD_RASTER_CTRL);

sys/arm/ti/am335x/am335x_lcd.c

546

reg |= RASTER_CTRL_LCDEN;

sys/arm/ti/am335x/am335x_lcd.c

547

LCD_WRITE4(sc, LCD_RASTER_CTRL, reg);

sys/arm/ti/am335x/am335x_lcd.c

551

if (reg & IRQ_EOF0) {

sys/arm/ti/am335x/am335x_lcd.c

554

reg &= ~IRQ_EOF0;

sys/arm/ti/am335x/am335x_lcd.c

557

if (reg & IRQ_EOF1) {

sys/arm/ti/am335x/am335x_lcd.c

560

reg &= ~IRQ_EOF1;

sys/arm/ti/am335x/am335x_lcd.c

563

if (reg & IRQ_FUF) {

sys/arm/ti/am335x/am335x_lcd.c

567

if (reg & IRQ_ACB) {

sys/arm/ti/am335x/am335x_lcd.c

574

reg = LCD_READ4(sc, LCD_END_OF_INT_IND);

sys/arm/ti/am335x/am335x_lcd.c

615

uint32_t reg, timing0, timing1, timing2;

sys/arm/ti/am335x/am335x_lcd.c

684

reg = CTRL_RASTER_MODE;

sys/arm/ti/am335x/am335x_lcd.c

686

reg |= (div << CTRL_DIV_SHIFT);

sys/arm/ti/am335x/am335x_lcd.c

687

LCD_WRITE4(sc, LCD_CTRL, reg);

sys/arm/ti/am335x/am335x_lcd.c

753

reg = LCDDMA_CTRL_FB0_FB1;

sys/arm/ti/am335x/am335x_lcd.c

773

reg |= (burst_log << LCDDMA_CTRL_BURST_SIZE_SHIFT);

sys/arm/ti/am335x/am335x_lcd.c

775

reg |= (0 << LCDDMA_CTRL_TH_FIFO_RDY_SHIFT);

sys/arm/ti/am335x/am335x_lcd.c

776

LCD_WRITE4(sc, LCD_LCDDMA_CTRL, reg);

sys/arm/ti/am335x/am335x_lcd.c

784

reg = RASTER_CTRL_LCDTFT;

sys/arm/ti/am335x/am335x_lcd.c

785

reg |= (sc->sc_panel.fdd << RASTER_CTRL_REQDLY_SHIFT);

sys/arm/ti/am335x/am335x_lcd.c

786

reg |= (PALETTE_DATA_ONLY << RASTER_CTRL_PALMODE_SHIFT);

sys/arm/ti/am335x/am335x_lcd.c

788

reg |= RASTER_CTRL_TFT24;

sys/arm/ti/am335x/am335x_lcd.c

790

reg |= RASTER_CTRL_TFT24_UNPACKED;

sys/arm/ti/am335x/am335x_lcd.c

791

LCD_WRITE4(sc, LCD_RASTER_CTRL, reg);

sys/arm/ti/am335x/am335x_lcd.c

800

reg = IRQ_EOF1 | IRQ_EOF0 | IRQ_FUF | IRQ_PL |

sys/arm/ti/am335x/am335x_lcd.c

803

LCD_WRITE4(sc, LCD_IRQENABLE_SET, reg);

sys/arm/ti/am335x/am335x_lcd.c

805

reg = LCD_READ4(sc, LCD_RASTER_CTRL);

sys/arm/ti/am335x/am335x_lcd.c

806

reg |= RASTER_CTRL_LCDEN;

sys/arm/ti/am335x/am335x_lcd.c

807

LCD_WRITE4(sc, LCD_RASTER_CTRL, reg);

sys/arm/ti/am335x/am335x_musb.c

102

#define USB_READ4(sc, idx, reg) bus_read_4((sc)->sc_mem_res[idx], (reg))

sys/arm/ti/am335x/am335x_musb.c

104

#define USBCTRL_WRITE4(sc, reg, val) \

sys/arm/ti/am335x/am335x_musb.c

105

USB_WRITE4((sc), RES_USBCTRL, (reg), (val))

sys/arm/ti/am335x/am335x_musb.c

106

#define USBCTRL_READ4(sc, reg) \

sys/arm/ti/am335x/am335x_musb.c

107

USB_READ4((sc), RES_USBCTRL, (reg))

sys/arm/ti/am335x/am335x_musb.c

160

uint32_t reg;

sys/arm/ti/am335x/am335x_musb.c

165

reg = SYSCON_READ_4(ssc->syscon, USB_CTRL[sc->sc_id]);

sys/arm/ti/am335x/am335x_musb.c

166

reg &= ~3; /* Enable power */

sys/arm/ti/am335x/am335x_musb.c

167

reg |= 1 << 19; /* VBUS detect enable */

sys/arm/ti/am335x/am335x_musb.c

168

reg |= 1 << 20; /* Session end enable */

sys/arm/ti/am335x/am335x_musb.c

170

SYSCON_WRITE_4(ssc->syscon, USB_CTRL[sc->sc_id], reg);

sys/arm/ti/am335x/am335x_musb.c

178

uint32_t reg;

sys/arm/ti/am335x/am335x_musb.c

184

reg = SYSCON_READ_4(ssc->syscon, USB_CTRL[sc->sc_id]);

sys/arm/ti/am335x/am335x_musb.c

185

SYSCON_WRITE_4(ssc->syscon, USB_CTRL[sc->sc_id], reg | 3);

sys/arm/ti/am335x/am335x_musb.c

247

uint32_t reg;

sys/arm/ti/am335x/am335x_musb.c

369

reg = USBCTRL_READ4(sc, USBCTRL_MODE);

sys/arm/ti/am335x/am335x_musb.c

370

reg |= USBCTRL_MODE_IDDIGMUX;

sys/arm/ti/am335x/am335x_musb.c

371

reg &= ~USBCTRL_MODE_IDDIG;

sys/arm/ti/am335x/am335x_musb.c

372

USBCTRL_WRITE4(sc, USBCTRL_MODE, reg);

sys/arm/ti/am335x/am335x_musb.c

376

reg = USBCTRL_READ4(sc, USBCTRL_MODE);

sys/arm/ti/am335x/am335x_musb.c

377

reg |= USBCTRL_MODE_IDDIGMUX;

sys/arm/ti/am335x/am335x_musb.c

378

reg |= USBCTRL_MODE_IDDIG;

sys/arm/ti/am335x/am335x_musb.c

379

USBCTRL_WRITE4(sc, USBCTRL_MODE, reg);

sys/arm/ti/am335x/am335x_musb.c

382

reg = USBCTRL_INTEN_USB_ALL & ~USBCTRL_INTEN_USB_SOF;

sys/arm/ti/am335x/am335x_musb.c

383

USBCTRL_WRITE4(sc, USBCTRL_INTEN_SET1, reg);

sys/arm/ti/am335x/am335x_musb.c

98

#define USB_WRITE4(sc, idx, reg, val) do { \

sys/arm/ti/am335x/am335x_musb.c

99

bus_write_4((sc)->sc_mem_res[idx], (reg), (val)); \

sys/arm/ti/am335x/am335x_pmic.c

206

uint8_t reg, vo;

sys/arm/ti/am335x/am335x_pmic.c

266

reg = 0;

sys/arm/ti/am335x/am335x_pmic.c

267

am335x_pmic_write(dev, TPS65217_INT_REG, &reg, 1);

sys/arm/ti/am335x/am335x_pmic.c

268

am335x_pmic_read(dev, TPS65217_INT_REG, &reg, 1);

sys/arm/ti/am335x/am335x_pwmss.c

102

uint32_t reg, id;

sys/arm/ti/am335x/am335x_pwmss.c

139

reg = SYSCON_READ_4(sc->syscon, SCM_PWMSS_CTRL);

sys/arm/ti/am335x/am335x_pwmss.c

140

reg |= (1 << id);

sys/arm/ti/am335x/am335x_pwmss.c

141

SYSCON_WRITE_4(sc->syscon, SCM_PWMSS_CTRL, reg);

sys/arm/ti/am335x/am335x_rtc.c

51

#define RTC_READ4(_sc, reg) \

sys/arm/ti/am335x/am335x_rtc.c

52

bus_read_4((_sc)->sc_mem_res, reg)

sys/arm/ti/am335x/am335x_rtc.c

53

#define RTC_WRITE4(_sc, reg, value) \

sys/arm/ti/am335x/am335x_rtc.c

54

bus_write_4((_sc)->sc_mem_res, reg, value)

sys/arm/ti/am335x/am335x_scm.c

115

uint32_t reg;

sys/arm/ti/am335x/am335x_scm.c

139

reg = SYSCON_READ_4(sc->syscon, SCM_BGAP_CTRL);

sys/arm/ti/am335x/am335x_scm.c

143

reg = SYSCON_READ_4(sc->syscon, SCM_BGAP_CTRL);

sys/arm/ti/am335x/am335x_scm.c

146

reg = SCM_BGAP_CLRZ | SCM_BGAP_CONTCONV | SCM_BGAP_SOC;

sys/arm/ti/am335x/am335x_scm.c

147

SYSCON_WRITE_4(sc->syscon, SCM_BGAP_CTRL, reg);

sys/arm/ti/am335x/am335x_scm.c

57

uint32_t reg;

sys/arm/ti/am335x/am335x_scm.c

64

reg = SYSCON_READ_4(sc->syscon, SCM_BGAP_CTRL);

sys/arm/ti/am335x/am335x_scm.c

65

if ((reg & SCM_BGAP_EOCZ) == 0)

sys/arm/ti/am335x/am335x_scm.c

69

if ((reg & SCM_BGAP_EOCZ) == 0) {

sys/arm/ti/am335x/am335x_scm.c

71

(reg >> SCM_BGAP_TEMP_SHIFT) & SCM_BGAP_TEMP_MASK;

sys/arm/ti/am335x/tda19988.c

308

uint8_t reg;

sys/arm/ti/am335x/tda19988.c

311

{ sc->sc_addr, IIC_M_WR, 1, &reg },

sys/arm/ti/am335x/tda19988.c

315

reg = REGADDR(addr);

sys/arm/ti/am335x/tda19988.c

329

uint8_t reg;

sys/arm/ti/am335x/tda19988.c

332

{ sc->sc_addr, IIC_M_WR, 1, &reg },

sys/arm/ti/am335x/tda19988.c

336

reg = REGADDR(addr);

sys/arm/ti/am335x/tda19988.c

434

uint8_t reg, div;

sys/arm/ti/am335x/tda19988.c

519

reg = VIP_CNTRL_3_SYNC_HS;

sys/arm/ti/am335x/tda19988.c

521

reg |= VIP_CNTRL_3_H_TGL;

sys/arm/ti/am335x/tda19988.c

523

reg |= VIP_CNTRL_3_V_TGL;

sys/arm/ti/am335x/tda19988.c

524

tda19988_reg_write(sc, TDA_VIP_CNTRL_3, reg);

sys/arm/ti/am335x/tda19988.c

526

reg = TBG_CNTRL_1_TGL_EN;

sys/arm/ti/am335x/tda19988.c

528

reg |= TBG_CNTRL_1_H_TGL;

sys/arm/ti/am335x/tda19988.c

530

reg |= TBG_CNTRL_1_V_TGL;

sys/arm/ti/am335x/tda19988.c

531

tda19988_reg_write(sc, TDA_TBG_CNTRL_1, reg);

sys/arm/ti/am335x/tda19988.c

59

#define REGPAGE(reg) (((reg) >> 8) & 0xff)

sys/arm/ti/am335x/tda19988.c

60

#define REGADDR(reg) ((reg) & 0xff)

sys/arm/ti/clk/ti_clkctrl.c

115

cell_t *reg;

sys/arm/ti/clk/ti_clkctrl.c

149

reg = malloc(numbytes_reg, M_DEVBUF, M_WAITOK);

sys/arm/ti/clk/ti_clkctrl.c

150

OF_getencprop(node, "reg", reg, numbytes_reg);

sys/arm/ti/clk/ti_clkctrl.c

155

free(reg, M_DEVBUF);

sys/arm/ti/clk/ti_clkctrl.c

187

for (reg_offset = 0; reg_offset < reg[index+1]; reg_offset += sizeof(cell_t)) {

sys/arm/ti/clk/ti_clkctrl.c

188

err = create_clkctrl(sc, reg, index, reg_offset, parent_offset,

sys/arm/ti/clk/ti_clkctrl.c

198

reg_address = reg[index] + reg_offset-reg[0];

sys/arm/ti/clk/ti_clkctrl.c

203

err = create_clkctrl(sc, reg, index, reg_offset,

sys/arm/ti/clk/ti_clkctrl.c

210

reg_address = reg[index] + reg_offset - reg[0];

sys/arm/ti/clk/ti_clkctrl.c

213

err = create_clkctrl(sc, reg, index, reg_offset,

sys/arm/ti/clk/ti_clkctrl.c

233

free(reg, M_DEVBUF);

sys/arm/ti/clk/ti_clkctrl.c

275

create_clkctrl(struct ti_clkctrl_softc *sc, cell_t *reg, uint32_t index, uint32_t reg_offset,

sys/arm/ti/clk/ti_clkctrl.c

293

def.clkdef.id = reg[index] + reg_offset - reg[0] + special_gdbclk_reg;

sys/arm/ti/clk/ti_clkctrl.c

294

def.register_offset = parent_offset + reg[index] + reg_offset;

sys/arm/ti/clk/ti_clkctrl.c

93

create_clkctrl(struct ti_clkctrl_softc *sc, cell_t *reg, uint32_t index, uint32_t reg_offset,

sys/arm/ti/cpsw/if_cpsw.c

1054

reg = SYSCON_READ_4(syscon, SCM_MAC_ID0_HI + sc->unit * 8);

sys/arm/ti/cpsw/if_cpsw.c

1055

mac_addr[0] = reg & 0xFF;

sys/arm/ti/cpsw/if_cpsw.c

1056

mac_addr[1] = (reg >> 8) & 0xFF;

sys/arm/ti/cpsw/if_cpsw.c

1057

mac_addr[2] = (reg >> 16) & 0xFF;

sys/arm/ti/cpsw/if_cpsw.c

1058

mac_addr[3] = (reg >> 24) & 0xFF;

sys/arm/ti/cpsw/if_cpsw.c

1061

reg = SYSCON_READ_4(syscon, SCM_MAC_ID0_LO + sc->unit * 8);

sys/arm/ti/cpsw/if_cpsw.c

1062

mac_addr[4] = reg & 0xFF;

sys/arm/ti/cpsw/if_cpsw.c

1063

mac_addr[5] = (reg >> 8) & 0xFF;

sys/arm/ti/cpsw/if_cpsw.c

1153

uint32_t reg;

sys/arm/ti/cpsw/if_cpsw.c

1177

reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit));

sys/arm/ti/cpsw/if_cpsw.c

1178

reg |= CPSW_SL_MACTL_GMII_ENABLE;

sys/arm/ti/cpsw/if_cpsw.c

1179

cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg);

sys/arm/ti/cpsw/if_cpsw.c

120

static int cpswp_miibus_readreg(device_t, int phy, int reg);

sys/arm/ti/cpsw/if_cpsw.c

121

static int cpswp_miibus_writereg(device_t, int phy, int reg, int value);

sys/arm/ti/cpsw/if_cpsw.c

1284

uint32_t reg;

sys/arm/ti/cpsw/if_cpsw.c

1307

reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit));

sys/arm/ti/cpsw/if_cpsw.c

1308

reg &= ~CPSW_SL_MACTL_GMII_ENABLE;

sys/arm/ti/cpsw/if_cpsw.c

1309

cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg);

sys/arm/ti/cpsw/if_cpsw.c

1365

uint32_t reg;

sys/arm/ti/cpsw/if_cpsw.c

1374

reg = cpsw_read_4(sc->swsc, CPSW_ALE_CONTROL);

sys/arm/ti/cpsw/if_cpsw.c

1375

reg &= ~CPSW_ALE_CTL_BYPASS;

sys/arm/ti/cpsw/if_cpsw.c

1377

reg |= CPSW_ALE_CTL_BYPASS;

sys/arm/ti/cpsw/if_cpsw.c

1378

cpsw_write_4(sc->swsc, CPSW_ALE_CONTROL, reg);

sys/arm/ti/cpsw/if_cpsw.c

1464

cpswp_miibus_ready(struct cpsw_softc *sc, uint32_t reg)

sys/arm/ti/cpsw/if_cpsw.c

1469

r = cpsw_read_4(sc, reg);

sys/arm/ti/cpsw/if_cpsw.c

1479

cpswp_miibus_readreg(device_t dev, int phy, int reg)

sys/arm/ti/cpsw/if_cpsw.c

1491

cmd = MDIO_PHYACCESS_GO | (reg & 0x1F) << 21 | (phy & 0x1F) << 16;

sys/arm/ti/cpsw/if_cpsw.c

1508

cpswp_miibus_writereg(device_t dev, int phy, int reg, int value)

sys/arm/ti/cpsw/if_cpsw.c

1521

(reg & 0x1F) << 21 | (phy & 0x1F) << 16 | (value & 0xFFFF);

sys/arm/ti/cpsw/if_cpsw.c

1536

uint32_t mac_control, reg;

sys/arm/ti/cpsw/if_cpsw.c

1541

reg = CPSW_SL_MACCONTROL(sc->unit);

sys/arm/ti/cpsw/if_cpsw.c

1542

mac_control = cpsw_read_4(sc->swsc, reg);

sys/arm/ti/cpsw/if_cpsw.c

1561

cpsw_write_4(sc->swsc, reg, mac_control);

sys/arm/ti/cpsw/if_cpsw.c

2551

cpsw_stat_sysctls[i].reg);

sys/arm/ti/cpsw/if_cpsw.c

2569

cpsw_stat_sysctls[i].reg);

sys/arm/ti/cpsw/if_cpsw.c

2571

cpsw_write_4(sc, CPSW_STATS_OFFSET + cpsw_stat_sysctls[i].reg,

sys/arm/ti/cpsw/if_cpsw.c

2586

result += cpsw_read_4(sc, CPSW_STATS_OFFSET + stat->reg);

sys/arm/ti/cpsw/if_cpsw.c

267

int reg;

sys/arm/ti/cpsw/if_cpsw.c

2809

uint32_t reg;

sys/arm/ti/cpsw/if_cpsw.c

2829

reg = cpsw_read_4(sc, CPSW_PORT_P_VLAN(p->es_port));

sys/arm/ti/cpsw/if_cpsw.c

2830

p->es_pvid = reg & ETHERSWITCH_VID_MASK;

sys/arm/ti/cpsw/if_cpsw.c

2832

reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port));

sys/arm/ti/cpsw/if_cpsw.c

2833

if (reg & ALE_PORTCTL_DROP_UNTAGGED)

sys/arm/ti/cpsw/if_cpsw.c

2835

if (reg & ALE_PORTCTL_INGRESS)

sys/arm/ti/cpsw/if_cpsw.c

2847

uint32_t reg;

sys/arm/ti/cpsw/if_cpsw.c

2858

reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port));

sys/arm/ti/cpsw/if_cpsw.c

2860

reg |= ALE_PORTCTL_DROP_UNTAGGED;

sys/arm/ti/cpsw/if_cpsw.c

2862

reg &= ~ALE_PORTCTL_DROP_UNTAGGED;

sys/arm/ti/cpsw/if_cpsw.c

2864

reg |= ALE_PORTCTL_INGRESS;

sys/arm/ti/cpsw/if_cpsw.c

2866

reg &= ~ALE_PORTCTL_INGRESS;

sys/arm/ti/cpsw/if_cpsw.c

2867

cpsw_write_4(sc, CPSW_ALE_PORTCTL(p->es_port), reg);

sys/arm/ti/cpsw/if_cpsw.c

2998

cpsw_readphy(device_t dev, int phy, int reg)

sys/arm/ti/cpsw/if_cpsw.c

3006

cpsw_writephy(device_t dev, int phy, int reg, int data)

sys/arm/ti/cpsw/if_cpsw.c

400

uint32_t reg = queue->hdp_offset;

sys/arm/ti/cpsw/if_cpsw.c

402

CPSW_DEBUGF(("HDP <=== 0x%08x (was 0x%08x)", v, cpsw_read_4(sc, reg)));

sys/arm/ti/cpsw/if_cpsw.c

403

cpsw_write_4(sc, reg, v);

sys/arm/ti/cpsw/if_cpsw.c

601

uint32_t reg;

sys/arm/ti/cpsw/if_cpsw.c

604

reg = cpsw_read_4(sc, CPSW_WR_INT_CONTROL);

sys/arm/ti/cpsw/if_cpsw.c

605

reg &= ~(CPSW_WR_INT_PACE_EN | CPSW_WR_INT_PRESCALE_MASK);

sys/arm/ti/cpsw/if_cpsw.c

606

cpsw_write_4(sc, CPSW_WR_INT_CONTROL, reg);

sys/arm/ti/cpsw/if_cpsw.c

612

reg = CPSW_ALE_CTL_ENABLE;

sys/arm/ti/cpsw/if_cpsw.c

614

reg |= CPSW_ALE_CTL_VLAN_AWARE;

sys/arm/ti/cpsw/if_cpsw.c

615

cpsw_write_4(sc, CPSW_ALE_CONTROL, reg);

sys/arm/ti/cpsw/if_cpsw.c

793

uint32_t reg;

sys/arm/ti/cpsw/if_cpsw.c

843

reg = cpsw_read_4(sc, CPSW_SS_IDVER);

sys/arm/ti/cpsw/if_cpsw.c

844

device_printf(dev, "CPSW SS Version %d.%d (%d)\n", (reg >> 8 & 0x7),

sys/arm/ti/cpsw/if_cpsw.c

845

reg & 0xFF, (reg >> 11) & 0x1F);

sys/arm/ti/cpsw/if_cpsw.c

993

uint32_t reg;

sys/arm/ti/ti_adc.c

104

uint32_t reg;

sys/arm/ti/ti_adc.c

115

reg = ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID;

sys/arm/ti/ti_adc.c

117

reg |= ADC_CTRL_TSC_ENABLE;

sys/arm/ti/ti_adc.c

120

reg |= ADC_CTRL_TSC_4WIRE;

sys/arm/ti/ti_adc.c

123

reg |= ADC_CTRL_TSC_5WIRE;

sys/arm/ti/ti_adc.c

126

reg |= ADC_CTRL_TSC_8WIRE;

sys/arm/ti/ti_adc.c

132

reg |= ADC_CTRL_ENABLE;

sys/arm/ti/ti_adc.c

134

ADC_WRITE4(sc, ADC_CTRL, reg);

sys/arm/ti/ti_adc.c

210

uint32_t reg, val;

sys/arm/ti/ti_adc.c

215

reg = input->stepconfig;

sys/arm/ti/ti_adc.c

216

val = ADC_READ4(sc, reg);

sys/arm/ti/ti_adc.c

238

ADC_WRITE4(sc, reg, val);

sys/arm/ti/ti_adc.c

258

int error, reg;

sys/arm/ti/ti_adc.c

264

reg = (int)ADC_READ4(sc, ADC_CLKDIV) + 1;

sys/arm/ti/ti_adc.c

267

error = sysctl_handle_int(oidp, &reg, sizeof(reg), req);

sys/arm/ti/ti_adc.c

276

reg--;

sys/arm/ti/ti_adc.c

277

if (reg < 9)

sys/arm/ti/ti_adc.c

278

reg = 9;

sys/arm/ti/ti_adc.c

279

if (reg > USHRT_MAX)

sys/arm/ti/ti_adc.c

280

reg = USHRT_MAX;

sys/arm/ti/ti_adc.c

286

ADC_WRITE4(sc, ADC_CLKDIV, reg);

sys/arm/ti/ti_adc.c

330

int error, reg;

sys/arm/ti/ti_adc.c

338

reg = (int)ADC_READ4(sc, input->stepdelay) & ADC_STEP_OPEN_DELAY;

sys/arm/ti/ti_adc.c

341

error = sysctl_handle_int(oidp, &reg, sizeof(reg), req);

sys/arm/ti/ti_adc.c

345

if (reg < 0)

sys/arm/ti/ti_adc.c

346

reg = 0;

sys/arm/ti/ti_adc.c

349

ADC_WRITE4(sc, input->stepdelay, reg & ADC_STEP_OPEN_DELAY);

sys/arm/ti/ti_adc.c

749

uint32_t rev, reg;

sys/arm/ti/ti_adc.c

855

reg = ADC_READ4(sc, ADC_CTRL);

sys/arm/ti/ti_adc.c

856

ADC_WRITE4(sc, ADC_CTRL, reg | ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID);

sys/arm/ti/ti_adcvar.h

32

#define ADC_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg)

sys/arm/ti/ti_adcvar.h

33

#define ADC_WRITE4(_sc, reg, value) \

sys/arm/ti/ti_adcvar.h

34

bus_write_4((_sc)->sc_mem_res, reg, value)

sys/arm/ti/ti_edma3.c

123

#define ti_edma3_cc_rd_4(reg) bus_read_4(ti_edma3_sc->mem_res[0], reg)

sys/arm/ti/ti_edma3.c

124

#define ti_edma3_cc_wr_4(reg, val) bus_write_4(ti_edma3_sc->mem_res[0], reg, val)

sys/arm/ti/ti_edma3.c

157

uint32_t reg;

sys/arm/ti/ti_edma3.c

186

reg = ti_edma3_cc_rd_4(TI_EDMA3CC_PID);

sys/arm/ti/ti_edma3.c

188

device_printf(dev, "EDMA revision %08x\n", reg);

sys/arm/ti/ti_edma3.c

241

uint32_t reg;

sys/arm/ti/ti_edma3.c

262

reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(i>>3));

sys/arm/ti/ti_edma3.c

263

reg &= TI_EDMA3CC_DMAQNUM_CLR(i);

sys/arm/ti/ti_edma3.c

264

reg |= TI_EDMA3CC_DMAQNUM_SET(i, eqn);

sys/arm/ti/ti_edma3.c

265

ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(i>>3), reg);

sys/arm/ti/ti_edma3.c

273

reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM);

sys/arm/ti/ti_edma3.c

274

reg &= TI_EDMA3CC_QDMAQNUM_CLR(i);

sys/arm/ti/ti_edma3.c

275

reg |= TI_EDMA3CC_QDMAQNUM_SET(i, eqn);

sys/arm/ti/ti_edma3.c

276

ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg);

sys/arm/ti/ti_edma3.c

284

uint32_t reg;

sys/arm/ti/ti_edma3.c

301

uint32_t reg;

sys/arm/ti/ti_edma3.c

308

reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAE(0));

sys/arm/ti/ti_edma3.c

309

reg |= (0x01 << ch);

sys/arm/ti/ti_edma3.c

310

ti_edma3_cc_wr_4(TI_EDMA3CC_DRAE(0), reg);

sys/arm/ti/ti_edma3.c

312

reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAEH(0));

sys/arm/ti/ti_edma3.c

313

reg |= (0x01 << (ch - 32));

sys/arm/ti/ti_edma3.c

314

ti_edma3_cc_wr_4(TI_EDMA3CC_DRAEH(0), reg);

sys/arm/ti/ti_edma3.c

318

reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(ch >> 3));

sys/arm/ti/ti_edma3.c

319

reg &= TI_EDMA3CC_DMAQNUM_CLR(ch);

sys/arm/ti/ti_edma3.c

320

reg |= TI_EDMA3CC_DMAQNUM_SET((ch), eqn);

sys/arm/ti/ti_edma3.c

321

ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(ch >> 3), reg);

sys/arm/ti/ti_edma3.c

324

reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch));

sys/arm/ti/ti_edma3.c

325

reg &= TI_EDMA3CC_OPT_TCC_CLR;

sys/arm/ti/ti_edma3.c

326

reg |= TI_EDMA3CC_OPT_TCC_SET(ch);

sys/arm/ti/ti_edma3.c

327

ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg);

sys/arm/ti/ti_edma3.c

335

uint32_t reg;

sys/arm/ti/ti_edma3.c

341

reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QRAE(0));

sys/arm/ti/ti_edma3.c

342

reg |= (0x01 << ch);

sys/arm/ti/ti_edma3.c

343

ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), reg);

sys/arm/ti/ti_edma3.c

346

reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM);

sys/arm/ti/ti_edma3.c

347

reg |= TI_EDMA3CC_QDMAQNUM_SET(ch, eqn);

sys/arm/ti/ti_edma3.c

348

ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg);

sys/arm/ti/ti_edma3.c

351

reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch));

sys/arm/ti/ti_edma3.c

352

reg &= TI_EDMA3CC_OPT_TCC_CLR;

sys/arm/ti/ti_edma3.c

353

reg |= TI_EDMA3CC_OPT_TCC_SET(ch);

sys/arm/ti/ti_edma3.c

354

ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg);

sys/arm/ti/ti_gpio.c

212

uint32_t reg;

sys/arm/ti/ti_gpio.c

215

reg = ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_0);

sys/arm/ti/ti_gpio.c

216

reg |= ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_1);

sys/arm/ti/ti_gpio.c

218

return (reg);

sys/arm/ti/ti_gpio.c

433

uint32_t reg;

sys/arm/ti/ti_gpio.c

441

reg = TI_GPIO_CLEARDATAOUT;

sys/arm/ti/ti_gpio.c

443

reg = TI_GPIO_SETDATAOUT;

sys/arm/ti/ti_gpio.c

444

ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin));

sys/arm/ti/ti_gpio.c

469

uint32_t oe, reg, val;

sys/arm/ti/ti_gpio.c

482

reg = TI_GPIO_DATAIN;

sys/arm/ti/ti_gpio.c

484

reg = TI_GPIO_DATAOUT;

sys/arm/ti/ti_gpio.c

485

val = ti_gpio_read_4(sc, reg);

sys/arm/ti/ti_gpio.c

508

uint32_t reg, val;

sys/arm/ti/ti_gpio.c

518

reg = TI_GPIO_CLEARDATAOUT;

sys/arm/ti/ti_gpio.c

520

reg = TI_GPIO_SETDATAOUT;

sys/arm/ti/ti_gpio.c

521

ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin));

sys/arm/ti/ti_gpio.c

731

ti_gpio_rwreg_modify(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask,

sys/arm/ti/ti_gpio.c

736

value = ti_gpio_read_4(sc, reg);

sys/arm/ti/ti_gpio.c

737

ti_gpio_write_4(sc, reg, set_bits ? value | mask : value & ~mask);

sys/arm/ti/ti_gpio.c

776

uint32_t reg;

sys/arm/ti/ti_gpio.c

784

reg = ti_gpio_intr_status(sc);

sys/arm/ti/ti_gpio.c

787

if ((reg & tgi->tgi_mask) == 0)

sys/arm/ti/ti_i2c.c

357

uint16_t reg;

sys/arm/ti/ti_i2c.c

411

reg = ti_i2c_read_2(sc, I2C_REG_BUF);

sys/arm/ti/ti_i2c.c

412

reg |= I2C_BUF_RXFIFO_CLR | I2C_BUF_TXFIFO_CLR;

sys/arm/ti/ti_i2c.c

413

ti_i2c_write_2(sc, I2C_REG_BUF, reg);

sys/arm/ti/ti_i2c.c

415

reg = sc->sc_con_reg | I2C_CON_STT;

sys/arm/ti/ti_i2c.c

417

reg |= I2C_CON_STP;

sys/arm/ti/ti_i2c.c

419

reg |= I2C_CON_TRX;

sys/arm/ti/ti_i2c.c

420

ti_i2c_write_2(sc, I2C_REG_CON, reg);

sys/arm/ti/ti_i2c.c

460

uint16_t fifo_trsh, reg, scll, sclh;

sys/arm/ti/ti_i2c.c

585

reg = fifo_trsh | (fifo_trsh << I2C_BUF_RXTRSH_SHIFT);

sys/arm/ti/ti_i2c.c

586

ti_i2c_write_2(sc, I2C_REG_BUF, reg);

sys/arm/ti/ti_i2c.c

615

reg = I2C_IE_XDR | /* Transmit draining interrupt. */

sys/arm/ti/ti_i2c.c

624

ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, reg);

sys/arm/ti/ti_mbox.c

104

ti_mbox_reg_read(struct ti_mbox_softc *sc, uint16_t reg)

sys/arm/ti/ti_mbox.c

106

return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));

sys/arm/ti/ti_mbox.c

110

ti_mbox_reg_write(struct ti_mbox_softc *sc, uint16_t reg, uint32_t val)

sys/arm/ti/ti_mbox.c

112

bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);

sys/arm/ti/ti_pinmux.c

352

name, cfg->reg, cfg->conf);

sys/arm/ti/ti_pinmux.c

356

ti_pinmux_write_2(sc, cfg->reg, cfg->conf);

sys/arm/ti/ti_pinmux.c

60

uint32_t reg;

sys/arm/ti/ti_pinmux.c

71

#define ti_pinmux_read_2(sc, reg) \

sys/arm/ti/ti_pinmux.c

72

bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arm/ti/ti_pinmux.c

73

#define ti_pinmux_write_2(sc, reg, val) \

sys/arm/ti/ti_pinmux.c

74

bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arm/ti/ti_pinmux.c

75

#define ti_pinmux_read_4(sc, reg) \

sys/arm/ti/ti_pinmux.c

76

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arm/ti/ti_pinmux.c

77

#define ti_pinmux_write_4(sc, reg, val) \

sys/arm/ti/ti_pinmux.c

78

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arm/ti/ti_pinmux.h

53

uint16_t reg;

sys/arm/ti/ti_prcm.c

219

uint32_t reg;

sys/arm/ti/ti_prcm.c

223

reg = bus_space_read_4(sc->bst, sc->bsh, addr);

sys/arm/ti/ti_prcm.c

224

reg &= ~clr;

sys/arm/ti/ti_prcm.c

225

reg |= set;

sys/arm/ti/ti_prcm.c

226

bus_space_write_4(sc->bst, sc->bsh, addr, reg);

sys/arm/ti/ti_prcm.c

227

DPRINTF(sc->dev, "offset=%lx reg: %x (clr %x set %x)\n", addr, reg, clr, set);

sys/arm/ti/ti_pruss.c

286

ti_pruss_reg_read(struct ti_pruss_softc *sc, uint32_t reg)

sys/arm/ti/ti_pruss.c

288

return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));

sys/arm/ti/ti_pruss.c

292

ti_pruss_reg_write(struct ti_pruss_softc *sc, uint32_t reg, uint32_t val)

sys/arm/ti/ti_pruss.c

294

bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);

sys/arm/ti/ti_pruss.c

337

uint32_t reg = enable ? PRUSS_INTC_HIEISR : PRUSS_INTC_HIDISR;

sys/arm/ti/ti_pruss.c

338

ti_pruss_reg_write(sc, reg, sc->sc_irq_devs[irq].channel);

sys/arm/ti/ti_pruss.c

340

reg = enable ? PRUSS_INTC_EISR : PRUSS_INTC_EICR;

sys/arm/ti/ti_pruss.c

341

ti_pruss_reg_write(sc, reg, sc->sc_irq_devs[irq].event );

sys/arm/ti/ti_scm.h

52

int ti_scm_reg_read_4(uint32_t reg, uint32_t *val);

sys/arm/ti/ti_scm.h

53

int ti_scm_reg_write_4(uint32_t reg, uint32_t val);

sys/arm/ti/ti_scm_syscon.c

115

uint32_t reg;

sys/arm/ti/ti_scm_syscon.c

120

reg = bus_space_read_4(sc->bst, sc->bsh, offset);

sys/arm/ti/ti_scm_syscon.c

121

reg &= ~clr;

sys/arm/ti/ti_scm_syscon.c

122

reg |= set;

sys/arm/ti/ti_scm_syscon.c

123

bus_space_write_4(sc->bst, sc->bsh, offset, reg);

sys/arm/ti/ti_scm_syscon.c

125

DPRINTF(sc->dev, "offset=%lx reg: %x (clr %x set %x)\n", offset, reg, clr, set);

sys/arm/ti/ti_scm_syscon.c

238

uint32_t reg;

sys/arm/ti/ti_scm_syscon.c

242

reg = bus_space_read_4(sc->bst, sc->bsh, addr);

sys/arm/ti/ti_scm_syscon.c

243

reg &= ~clr;

sys/arm/ti/ti_scm_syscon.c

244

reg |= set;

sys/arm/ti/ti_scm_syscon.c

245

bus_space_write_4(sc->bst, sc->bsh, addr, reg);

sys/arm/ti/ti_scm_syscon.c

246

DPRINTF(sc->dev, "offset=%lx reg: %x (clr %x set %x)\n", addr, reg, clr, set);

sys/arm/ti/ti_spi.c

109

reg = TI_SPI_READ(sc, MCSPI_STAT_CH(i));

sys/arm/ti/ti_spi.c

110

device_printf(dev, "CH%dSTAT: 0x%b\n", i, reg, STATBITS);

sys/arm/ti/ti_spi.c

113

reg = TI_SPI_READ(sc, MCSPI_XFERLEVEL);

sys/arm/ti/ti_spi.c

114

device_printf(dev, "XFERLEVEL: %#x\n", reg);

sys/arm/ti/ti_spi.c

121

uint32_t clkdiv, conf, div, extclk, reg;

sys/arm/ti/ti_spi.c

139

reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(ch));

sys/arm/ti/ti_spi.c

140

reg &= ~(MCSPI_CTRL_EXTCLK_MSK << MCSPI_CTRL_EXTCLK_SHIFT);

sys/arm/ti/ti_spi.c

141

reg |= extclk << MCSPI_CTRL_EXTCLK_SHIFT;

sys/arm/ti/ti_spi.c

142

TI_SPI_WRITE(sc, MCSPI_CTRL_CH(ch), reg);

sys/arm/ti/ti_spi.c

144

reg = TI_SPI_READ(sc, MCSPI_CONF_CH(ch));

sys/arm/ti/ti_spi.c

145

reg &= ~(MCSPI_CONF_CLKG | MCSPI_CONF_CLK_MSK << MCSPI_CONF_CLK_SHIFT);

sys/arm/ti/ti_spi.c

146

TI_SPI_WRITE(sc, MCSPI_CONF_CH(ch), reg | conf);

sys/arm/ti/ti_spi.c

433

uint32_t clockhz, cs, mode, reg;

sys/arm/ti/ti_spi.c

490

reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs));

sys/arm/ti/ti_spi.c

491

reg &= ~(MCSPI_CONF_FFER | MCSPI_CONF_FFEW | MCSPI_CONF_SBPOL |

sys/arm/ti/ti_spi.c

495

reg |= MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | MCSPI_CONF_WL8BITS;

sys/arm/ti/ti_spi.c

496

reg |= mode; /* POL and PHA are the low bits, we can just OR-in mode */

sys/arm/ti/ti_spi.c

497

TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);

sys/arm/ti/ti_spi.c

501

reg = TI_SPI_READ(sc, MCSPI_IRQENABLE);

sys/arm/ti/ti_spi.c

502

reg |= 0xf;

sys/arm/ti/ti_spi.c

503

TI_SPI_WRITE(sc, MCSPI_IRQENABLE, reg);

sys/arm/ti/ti_spi.c

507

reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs));

sys/arm/ti/ti_spi.c

508

TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg | MCSPI_CTRL_ENABLE);

sys/arm/ti/ti_spi.c

511

reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs));

sys/arm/ti/ti_spi.c

512

TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg |= MCSPI_CONF_FORCE);

sys/arm/ti/ti_spi.c

519

reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs));

sys/arm/ti/ti_spi.c

520

reg &= ~MCSPI_CONF_FORCE;

sys/arm/ti/ti_spi.c

521

TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);

sys/arm/ti/ti_spi.c

524

reg = TI_SPI_READ(sc, MCSPI_IRQENABLE);

sys/arm/ti/ti_spi.c

525

reg &= ~0xf;

sys/arm/ti/ti_spi.c

526

TI_SPI_WRITE(sc, MCSPI_IRQENABLE, reg);

sys/arm/ti/ti_spi.c

530

reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs));

sys/arm/ti/ti_spi.c

531

reg &= ~MCSPI_CTRL_ENABLE;

sys/arm/ti/ti_spi.c

532

TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg);

sys/arm/ti/ti_spi.c

535

reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs));

sys/arm/ti/ti_spi.c

536

reg &= ~(MCSPI_CONF_FFER | MCSPI_CONF_FFEW);

sys/arm/ti/ti_spi.c

537

TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);

sys/arm/ti/ti_spi.c

80

uint32_t reg;

sys/arm/ti/ti_spi.c

83

reg = TI_SPI_READ(sc, MCSPI_SYSCONFIG);

sys/arm/ti/ti_spi.c

84

device_printf(dev, "SYSCONFIG: %#x\n", reg);

sys/arm/ti/ti_spi.c

85

reg = TI_SPI_READ(sc, MCSPI_SYSSTATUS);

sys/arm/ti/ti_spi.c

86

device_printf(dev, "SYSSTATUS: %#x\n", reg);

sys/arm/ti/ti_spi.c

87

reg = TI_SPI_READ(sc, MCSPI_IRQSTATUS);

sys/arm/ti/ti_spi.c

88

device_printf(dev, "IRQSTATUS: 0x%b\n", reg, IRQSTATUSBITS);

sys/arm/ti/ti_spi.c

89

reg = TI_SPI_READ(sc, MCSPI_IRQENABLE);

sys/arm/ti/ti_spi.c

90

device_printf(dev, "IRQENABLE: 0x%b\n", reg, IRQSTATUSBITS);

sys/arm/ti/ti_spi.c

91

reg = TI_SPI_READ(sc, MCSPI_MODULCTRL);

sys/arm/ti/ti_spi.c

92

device_printf(dev, "MODULCTRL: 0x%b\n", reg, MODULCTRLBITS);

sys/arm/ti/ti_sysc.c

138

struct sysc_reg reg[REG_MAX];

sys/arm/ti/ti_sysc.c

165

return (sc->reg[REG_REV].address);

sys/arm/ti/ti_sysc.c

179

return (sc->reg[REG_SYSC].address);

sys/arm/ti/ti_sysc.c

193

return (sc->reg[REG_SYSS].address);

sys/arm/ti/ti_sysc.c

275

cell_t *reg;

sys/arm/ti/ti_sysc.c

307

reg = malloc(nreg, M_DEVBUF, M_WAITOK);

sys/arm/ti/ti_sysc.c

308

OF_getencprop(node, "reg", reg, nreg);

sys/arm/ti/ti_sysc.c

312

sc->reg[idx].address = 0;

sys/arm/ti/ti_sysc.c

313

sc->reg[idx].size = 0;

sys/arm/ti/ti_sysc.c

326

sc->reg[prop_idx].address <<= 32;

sys/arm/ti/ti_sysc.c

327

sc->reg[prop_idx].address |= reg[reg_i++];

sys/arm/ti/ti_sysc.c

331

sc->reg[prop_idx].size <<= 32;

sys/arm/ti/ti_sysc.c

332

sc->reg[prop_idx].size |= reg[reg_i++];

sys/arm/ti/ti_sysc.c

336

sc->offset_reg[prop_idx] = sc->reg[prop_idx].address;

sys/arm/ti/ti_sysc.c

338

sc->offset_reg[prop_idx] = sc->reg[prop_idx].address -

sys/arm/ti/ti_sysc.c

343

sc->reg[prop_idx].address,

sys/arm/ti/ti_sysc.c

344

sc->reg[prop_idx].size);

sys/arm/ti/ti_sysc.c

346

free(reg, M_DEVBUF);

sys/arm/ti/ti_wdt.c

101

ti_wdt_reg_write(struct ti_wdt_softc *sc, uint32_t reg, uint32_t val)

sys/arm/ti/ti_wdt.c

104

bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);

sys/arm/ti/ti_wdt.c

94

ti_wdt_reg_read(struct ti_wdt_softc *sc, uint32_t reg)

sys/arm/ti/ti_wdt.c

97

return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));

sys/arm/xilinx/uart_dev_cdnc.c

54

#define RD4(bas, reg) \

sys/arm/xilinx/uart_dev_cdnc.c

55

bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs((bas), (reg)))

sys/arm/xilinx/uart_dev_cdnc.c

56

#define WR4(bas, reg, value) \

sys/arm/xilinx/uart_dev_cdnc.c

57

bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs((bas), (reg)), \

sys/arm/xilinx/zy7_slcr.c

260

uint32_t reg;

sys/arm/xilinx/zy7_slcr.c

271

reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));

sys/arm/xilinx/zy7_slcr.c

272

reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK);

sys/arm/xilinx/zy7_slcr.c

273

reg |= (source << ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT);

sys/arm/xilinx/zy7_slcr.c

274

WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg);

sys/arm/xilinx/zy7_slcr.c

288

uint32_t reg;

sys/arm/xilinx/zy7_slcr.c

297

reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));

sys/arm/xilinx/zy7_slcr.c

298

source = (reg & ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK) >>

sys/arm/xilinx/zy7_slcr.c

316

uint32_t reg;

sys/arm/xilinx/zy7_slcr.c

361

reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));

sys/arm/xilinx/zy7_slcr.c

362

reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK |

sys/arm/xilinx/zy7_slcr.c

364

reg |= (div1 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT) |

sys/arm/xilinx/zy7_slcr.c

366

WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg);

sys/arm/xilinx/zy7_slcr.c

383

uint32_t reg;

sys/arm/xilinx/zy7_slcr.c

410

reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));

sys/arm/xilinx/zy7_slcr.c

411

div1 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK) >>

sys/arm/xilinx/zy7_slcr.c

413

div0 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK) >>

sys/arm/xilinx/zy7_slcr.c

484

uint32_t reg;

sys/arm/xilinx/zy7_slcr.c

490

reg = RD4(sc, ZY7_SLCR_FPGA_THR_CNT(unit));

sys/arm/xilinx/zy7_slcr.c

493

return !(reg & 1);

sys/arm/xilinx/zy7_slcr.c

501

uint32_t reg;

sys/arm/xilinx/zy7_slcr.c

507

reg = RD4(sc, ZY7_SLCR_LVL_SHFTR_EN);

sys/arm/xilinx/zy7_slcr.c

510

return (reg == ZY7_SLCR_LVL_SHFTR_EN_ALL);

sys/arm64/acpica/pci_cfgreg.c

43

pci_cfgregread(int domain, int bus, int slot, int func, int reg, int bytes)

sys/arm64/acpica/pci_cfgreg.c

55

pci_cfgregwrite(int domain, int bus, int slot, int func, int reg, uint32_t data,

sys/arm64/apple/apple_aic.c

628

uint64_t reg;

sys/arm64/apple/apple_aic.c

635

reg = READ_SPECIALREG(AIC_FIQ_VM_TIMER);

sys/arm64/apple/apple_aic.c

636

if ((reg & AIC_FIQ_VM_TIMER_PEN) != 0) {

sys/arm64/apple/apple_aic.c

640

if ((reg & AIC_FIQ_VM_TIMER_VEN) != 0) {

sys/arm64/apple/apple_pinctrl.c

199

uint32_t reg;

sys/arm64/apple/apple_pinctrl.c

205

reg = HREAD4(sc, GPIO_PIN(pin));

sys/arm64/apple/apple_pinctrl.c

206

reg &= ~GPIO_PIN_FUNC_MASK;

sys/arm64/apple/apple_pinctrl.c

207

reg &= ~GPIO_PIN_MODE_MASK;

sys/arm64/apple/apple_pinctrl.c

210

reg &= ~GPIO_PIN_DATA;

sys/arm64/apple/apple_pinctrl.c

212

reg |= GPIO_PIN_DATA;

sys/arm64/apple/apple_pinctrl.c

215

reg |= GPIO_PIN_MODE_INPUT;

sys/arm64/apple/apple_pinctrl.c

217

reg |= GPIO_PIN_MODE_OUTPUT;

sys/arm64/apple/apple_pinctrl.c

219

HWRITE4(sc, GPIO_PIN(pin), reg);

sys/arm64/apple/apple_pinctrl.c

260

uint32_t reg;

sys/arm64/apple/apple_pinctrl.c

270

reg = HREAD4(sc, GPIO_PIN(pin));

sys/arm64/apple/apple_pinctrl.c

271

if ((reg & GPIO_PIN_MODE_INPUT) != 0)

sys/arm64/apple/apple_pinctrl.c

273

else if ((reg & GPIO_PIN_MODE_OUTPUT) != 0)

sys/arm64/apple/apple_pinctrl.c

309

uint32_t reg;

sys/arm64/apple/apple_pinctrl.c

316

reg = HREAD4(sc, GPIO_PIN(pin));

sys/arm64/apple/apple_pinctrl.c

317

*val = !!(reg & GPIO_PIN_DATA);

sys/arm64/apple/apple_pinctrl.c

348

uint32_t reg;

sys/arm64/apple/apple_pinctrl.c

355

reg = HREAD4(sc, GPIO_PIN(pin));

sys/arm64/apple/apple_pinctrl.c

356

if ((reg & GPIO_PIN_DATA) == 0)

sys/arm64/apple/apple_pinctrl.c

357

reg |= GPIO_PIN_DATA;

sys/arm64/apple/apple_pinctrl.c

359

reg &= ~GPIO_PIN_DATA;

sys/arm64/apple/apple_pinctrl.c

360

HWRITE4(sc, GPIO_PIN(pin), reg);

sys/arm64/apple/apple_pinctrl.c

410

uint32_t reg;

sys/arm64/apple/apple_pinctrl.c

425

reg = HREAD4(sc, GPIO_PIN(pin));

sys/arm64/apple/apple_pinctrl.c

426

reg &= ~GPIO_PIN_FUNC_MASK;

sys/arm64/apple/apple_pinctrl.c

427

reg |= (func << GPIO_PIN_FUNC_SHIFT) & GPIO_PIN_FUNC_MASK;

sys/arm64/apple/apple_pinctrl.c

428

HWRITE4(sc, GPIO_PIN(pin), reg);

sys/arm64/apple/apple_pinctrl.c

63

#define HREAD4(sc, reg) \

sys/arm64/apple/apple_pinctrl.c

64

bus_read_4((sc)->sc_res[APPLE_PINCTRL_MEMRES], reg)

sys/arm64/apple/apple_pinctrl.c

65

#define HWRITE4(sc, reg, val) \

sys/arm64/apple/apple_pinctrl.c

66

bus_write_4((sc)->sc_res[APPLE_PINCTRL_MEMRES], reg, val)

sys/arm64/apple/apple_pinctrl.c

67

#define HSET4(sc, reg, bits) \

sys/arm64/apple/apple_pinctrl.c

68

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arm64/apple/apple_pinctrl.c

69

#define HCLR4(sc, reg, bits) \

sys/arm64/apple/apple_pinctrl.c

70

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arm64/apple/exynos_uart.c

406

int reg;

sys/arm64/apple/exynos_uart.c

421

reg = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh,

sys/arm64/apple/exynos_uart.c

423

reg &= ~(1 << 2);

sys/arm64/apple/exynos_uart.c

425

reg);

sys/arm64/apple/exynos_uart.c

514

int reg;

sys/arm64/apple/exynos_uart.c

527

reg = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh,

sys/arm64/apple/exynos_uart.c

529

reg |= UINTM_TXINTR;

sys/arm64/apple/exynos_uart.c

531

SSCOM_UINTM, reg);

sys/arm64/arm64/cmn600.c

185

cmn600_node_read8(struct cmn600_node *nd, uint32_t reg)

sys/arm64/arm64/cmn600.c

188

return (RD8(nd->sc, nd->nd_offset + reg));

sys/arm64/arm64/cmn600.c

192

cmn600_node_write8(struct cmn600_node *nd, uint32_t reg, uint64_t val)

sys/arm64/arm64/cmn600.c

195

WR8(nd->sc, nd->nd_offset + reg, val);

sys/arm64/arm64/cmn600.c

199

cmn600_node_read4(struct cmn600_node *nd, uint32_t reg)

sys/arm64/arm64/cmn600.c

202

return (RD4(nd->sc, nd->nd_offset + reg));

sys/arm64/arm64/cmn600.c

206

cmn600_node_write4(struct cmn600_node *nd, uint32_t reg, uint32_t val)

sys/arm64/arm64/cmn600.c

209

WR4(nd->sc, nd->nd_offset + reg, val);

sys/arm64/arm64/cmn600.c

542

pmu_cmn600_rd4(void *arg, int nodeid, int node_type, off_t reg)

sys/arm64/arm64/cmn600.c

552

return (cmn600_node_read4(node, reg));

sys/arm64/arm64/cmn600.c

556

pmu_cmn600_wr4(void *arg, int nodeid, int node_type, off_t reg, uint32_t val)

sys/arm64/arm64/cmn600.c

566

cmn600_node_write4(node, reg, val);

sys/arm64/arm64/cmn600.c

571

pmu_cmn600_rd8(void *arg, int nodeid, int node_type, off_t reg)

sys/arm64/arm64/cmn600.c

581

return (cmn600_node_read8(node, reg));

sys/arm64/arm64/cmn600.c

585

pmu_cmn600_wr8(void *arg, int nodeid, int node_type, off_t reg, uint64_t val)

sys/arm64/arm64/cmn600.c

595

cmn600_node_write8(node, reg, val);

sys/arm64/arm64/cmn600.c

600

pmu_cmn600_set8(void *arg, int nodeid, int node_type, off_t reg, uint64_t val)

sys/arm64/arm64/cmn600.c

610

cmn600_node_write8(node, reg, cmn600_node_read8(node, reg) | val);

sys/arm64/arm64/cmn600.c

615

pmu_cmn600_clr8(void *arg, int nodeid, int node_type, off_t reg, uint64_t val)

sys/arm64/arm64/cmn600.c

625

cmn600_node_write8(node, reg, cmn600_node_read8(node, reg) & ~val);

sys/arm64/arm64/cmn600.c

630

pmu_cmn600_md8(void *arg, int nodeid, int node_type, off_t reg, uint64_t mask,

sys/arm64/arm64/cmn600.c

641

cmn600_node_write8(node, reg, (cmn600_node_read8(node, reg) & ~mask) |

sys/arm64/arm64/db_interface.c

50

long *reg;

sys/arm64/arm64/db_interface.c

55

reg = (long *)((uintptr_t)kdb_frame + (db_expr_t)vp->valuep);

sys/arm64/arm64/db_interface.c

57

*valuep = *reg;

sys/arm64/arm64/db_interface.c

59

*reg = *valuep;

sys/arm64/arm64/debug_monitor.c

107

#define DBG_WB_READ(reg, num, val) do { \

sys/arm64/arm64/debug_monitor.c

108

__asm __volatile("mrs %0, dbg" reg #num "_el1" : "=r" (val)); \

sys/arm64/arm64/debug_monitor.c

111

#define DBG_WB_WRITE(reg, num, val) do { \

sys/arm64/arm64/debug_monitor.c

112

__asm __volatile("msr dbg" reg #num "_el1, %0" :: "r" (val)); \

sys/arm64/arm64/debug_monitor.c

115

#define READ_WB_REG_CASE(reg, num, offset, val) \

sys/arm64/arm64/debug_monitor.c

117

DBG_WB_READ(reg, num, val); \

sys/arm64/arm64/debug_monitor.c

120

#define WRITE_WB_REG_CASE(reg, num, offset, val) \

sys/arm64/arm64/debug_monitor.c

122

DBG_WB_WRITE(reg, num, val); \

sys/arm64/arm64/debug_monitor.c

125

#define SWITCH_CASES_READ_WB_REG(reg, offset, val) \

sys/arm64/arm64/debug_monitor.c

126

READ_WB_REG_CASE(reg, 0, offset, val); \

sys/arm64/arm64/debug_monitor.c

127

READ_WB_REG_CASE(reg, 1, offset, val); \

sys/arm64/arm64/debug_monitor.c

128

READ_WB_REG_CASE(reg, 2, offset, val); \

sys/arm64/arm64/debug_monitor.c

129

READ_WB_REG_CASE(reg, 3, offset, val); \

sys/arm64/arm64/debug_monitor.c

130

READ_WB_REG_CASE(reg, 4, offset, val); \

sys/arm64/arm64/debug_monitor.c

131

READ_WB_REG_CASE(reg, 5, offset, val); \

sys/arm64/arm64/debug_monitor.c

132

READ_WB_REG_CASE(reg, 6, offset, val); \

sys/arm64/arm64/debug_monitor.c

133

READ_WB_REG_CASE(reg, 7, offset, val); \

sys/arm64/arm64/debug_monitor.c

134

READ_WB_REG_CASE(reg, 8, offset, val); \

sys/arm64/arm64/debug_monitor.c

135

READ_WB_REG_CASE(reg, 9, offset, val); \

sys/arm64/arm64/debug_monitor.c

136

READ_WB_REG_CASE(reg, 10, offset, val); \

sys/arm64/arm64/debug_monitor.c

137

READ_WB_REG_CASE(reg, 11, offset, val); \

sys/arm64/arm64/debug_monitor.c

138

READ_WB_REG_CASE(reg, 12, offset, val); \

sys/arm64/arm64/debug_monitor.c

139

READ_WB_REG_CASE(reg, 13, offset, val); \

sys/arm64/arm64/debug_monitor.c

140

READ_WB_REG_CASE(reg, 14, offset, val); \

sys/arm64/arm64/debug_monitor.c

141

READ_WB_REG_CASE(reg, 15, offset, val)

sys/arm64/arm64/debug_monitor.c

143

#define SWITCH_CASES_WRITE_WB_REG(reg, offset, val) \

sys/arm64/arm64/debug_monitor.c

144

WRITE_WB_REG_CASE(reg, 0, offset, val); \

sys/arm64/arm64/debug_monitor.c

145

WRITE_WB_REG_CASE(reg, 1, offset, val); \

sys/arm64/arm64/debug_monitor.c

146

WRITE_WB_REG_CASE(reg, 2, offset, val); \

sys/arm64/arm64/debug_monitor.c

147

WRITE_WB_REG_CASE(reg, 3, offset, val); \

sys/arm64/arm64/debug_monitor.c

148

WRITE_WB_REG_CASE(reg, 4, offset, val); \

sys/arm64/arm64/debug_monitor.c

149

WRITE_WB_REG_CASE(reg, 5, offset, val); \

sys/arm64/arm64/debug_monitor.c

150

WRITE_WB_REG_CASE(reg, 6, offset, val); \

sys/arm64/arm64/debug_monitor.c

151

WRITE_WB_REG_CASE(reg, 7, offset, val); \

sys/arm64/arm64/debug_monitor.c

152

WRITE_WB_REG_CASE(reg, 8, offset, val); \

sys/arm64/arm64/debug_monitor.c

153

WRITE_WB_REG_CASE(reg, 9, offset, val); \

sys/arm64/arm64/debug_monitor.c

154

WRITE_WB_REG_CASE(reg, 10, offset, val); \

sys/arm64/arm64/debug_monitor.c

155

WRITE_WB_REG_CASE(reg, 11, offset, val); \

sys/arm64/arm64/debug_monitor.c

156

WRITE_WB_REG_CASE(reg, 12, offset, val); \

sys/arm64/arm64/debug_monitor.c

157

WRITE_WB_REG_CASE(reg, 13, offset, val); \

sys/arm64/arm64/debug_monitor.c

158

WRITE_WB_REG_CASE(reg, 14, offset, val); \

sys/arm64/arm64/debug_monitor.c

159

WRITE_WB_REG_CASE(reg, 15, offset, val)

sys/arm64/arm64/debug_monitor.c

163

dbg_wb_read_reg(int reg, int n)

sys/arm64/arm64/debug_monitor.c

167

switch (reg + n) {

sys/arm64/arm64/debug_monitor.c

181

dbg_wb_write_reg(int reg, int n, uint64_t val)

sys/arm64/arm64/debug_monitor.c

183

switch (reg + n) {

sys/arm64/arm64/debug_monitor.c

387

uint64_t *reg;

sys/arm64/arm64/debug_monitor.c

393

reg = monitor->dbg_bcr;

sys/arm64/arm64/debug_monitor.c

397

reg = monitor->dbg_wcr;

sys/arm64/arm64/debug_monitor.c

405

if ((reg[i] & DBG_WB_CTRL_E) == 0)

sys/arm64/arm64/disassem.c

481

arm64_disasm_reg_width(int option, int reg)

sys/arm64/arm64/disassem.c

484

return (arm64_x_reg(reg, 0));

sys/arm64/arm64/disassem.c

485

return (arm64_w_reg(reg, 0));

sys/arm64/arm64/exec_machdep.c

101

set_regs(struct thread *td, struct reg *regs)

sys/arm64/arm64/exec_machdep.c

479

sizeof((struct reg *)0)->x);

sys/arm64/arm64/exec_machdep.c

75

fill_regs(struct thread *td, struct reg *regs)

sys/arm64/arm64/gic_v3.c

859

uint32_t reg;

sys/arm64/arm64/gic_v3.c

875

reg = gic_r_read(sc, 4,

sys/arm64/arm64/gic_v3.c

878

reg = gic_d_read(sc, 4, GICD_ICFGR(irq));

sys/arm64/arm64/gic_v3.c

880

reg &= ~(2 << ((irq % 16) * 2));

sys/arm64/arm64/gic_v3.c

882

reg |= 2 << ((irq % 16) * 2);

sys/arm64/arm64/gic_v3.c

886

GICR_SGI_BASE_SIZE + GICD_ICFGR(irq), reg);

sys/arm64/arm64/gic_v3.c

889

gic_d_write(sc, 4, GICD_ICFGR(irq), reg);

sys/arm64/arm64/gic_v3_reg.h

362

#define GITS_CMD_OFFSET(reg) ((reg) & 0xfffe0ul)

sys/arm64/arm64/gic_v3_reg.h

503

#define gic_icc_write(reg, val) \

sys/arm64/arm64/gic_v3_reg.h

505

WRITE_SPECIALREG(icc_ ##reg ##_el1, val); \

sys/arm64/arm64/gic_v3_reg.h

509

#define gic_icc_read(reg) \

sys/arm64/arm64/gic_v3_reg.h

513

val = READ_SPECIALREG(icc_ ##reg ##_el1); \

sys/arm64/arm64/gic_v3_reg.h

517

#define gic_icc_set(reg, mask) \

sys/arm64/arm64/gic_v3_reg.h

520

val = gic_icc_read(reg); \

sys/arm64/arm64/gic_v3_reg.h

522

gic_icc_write(reg, val); \

sys/arm64/arm64/gic_v3_reg.h

525

#define gic_icc_clear(reg, mask) \

sys/arm64/arm64/gic_v3_reg.h

528

val = gic_icc_read(reg); \

sys/arm64/arm64/gic_v3_reg.h

530

gic_icc_write(reg, val); \

sys/arm64/arm64/gic_v3_var.h

136

#define gic_d_read(sc, len, reg) \

sys/arm64/arm64/gic_v3_var.h

138

bus_read_##len(sc->gic_dist, reg); \

sys/arm64/arm64/gic_v3_var.h

141

#define gic_d_write(sc, len, reg, val) \

sys/arm64/arm64/gic_v3_var.h

143

bus_write_##len(sc->gic_dist, reg, val);\

sys/arm64/arm64/gic_v3_var.h

147

#define gic_r_read(sc, len, reg) \

sys/arm64/arm64/gic_v3_var.h

153

(sc)->gic_redists.pcpu[cpu].offset + (reg)); \

sys/arm64/arm64/gic_v3_var.h

156

#define gic_r_write(sc, len, reg, val) \

sys/arm64/arm64/gic_v3_var.h

162

(sc)->gic_redists.pcpu[cpu].offset + (reg), \

sys/arm64/arm64/gicv3_its.c

336

#define gic_its_read_4(sc, reg) \

sys/arm64/arm64/gicv3_its.c

337

bus_read_4((sc)->sc_its_res, (reg))

sys/arm64/arm64/gicv3_its.c

338

#define gic_its_read_8(sc, reg) \

sys/arm64/arm64/gicv3_its.c

339

bus_read_8((sc)->sc_its_res, (reg))

sys/arm64/arm64/gicv3_its.c

341

#define gic_its_write_4(sc, reg, val) \

sys/arm64/arm64/gicv3_its.c

342

bus_write_4((sc)->sc_its_res, (reg), (val))

sys/arm64/arm64/gicv3_its.c

343

#define gic_its_write_8(sc, reg, val) \

sys/arm64/arm64/gicv3_its.c

344

bus_write_8((sc)->sc_its_res, (reg), (val))

sys/arm64/arm64/gicv3_its.c

423

uint64_t reg, tmp;

sys/arm64/arm64/gicv3_its.c

435

reg = GITS_CBASER_VALID |

sys/arm64/arm64/gicv3_its.c

439

reg |= GITS_CBASER_SHARE_NS << GITS_CBASER_SHARE_SHIFT;

sys/arm64/arm64/gicv3_its.c

441

reg |= GITS_CBASER_SHARE_IS << GITS_CBASER_SHARE_SHIFT;

sys/arm64/arm64/gicv3_its.c

442

gic_its_write_8(sc, GITS_CBASER, reg);

sys/arm64/arm64/gicv3_its.c

453

reg &= ~GITS_CBASER_CACHE_MASK;

sys/arm64/arm64/gicv3_its.c

454

reg &= ~GITS_CBASER_SHARE_MASK;

sys/arm64/arm64/gicv3_its.c

456

reg |= GITS_CBASER_CACHE_NIN << GITS_CBASER_CACHE_SHIFT;

sys/arm64/arm64/gicv3_its.c

457

reg |= GITS_CBASER_SHARE_NS << GITS_CBASER_SHARE_SHIFT;

sys/arm64/arm64/gicv3_its.c

459

gic_its_write_8(sc, GITS_CBASER, reg);

sys/arm64/arm64/gicv3_its.c

473

uint64_t reg, tmp;

sys/arm64/arm64/gicv3_its.c

477

reg = gic_its_read_8(sc, GITS_BASER(table));

sys/arm64/arm64/gicv3_its.c

480

reg &= ~GITS_BASER_PSZ_MASK;

sys/arm64/arm64/gicv3_its.c

483

reg |= GITS_BASER_PSZ_4K << GITS_BASER_PSZ_SHIFT;

sys/arm64/arm64/gicv3_its.c

486

reg |= GITS_BASER_PSZ_16K << GITS_BASER_PSZ_SHIFT;

sys/arm64/arm64/gicv3_its.c

489

reg |= GITS_BASER_PSZ_64K << GITS_BASER_PSZ_SHIFT;

sys/arm64/arm64/gicv3_its.c

494

gic_its_write_8(sc, GITS_BASER(table), reg);

sys/arm64/arm64/gicv3_its.c

500

if ((tmp & GITS_BASER_PSZ_MASK) == (reg & GITS_BASER_PSZ_MASK))

sys/arm64/arm64/gicv3_its.c

519

uint64_t reg;

sys/arm64/arm64/gicv3_its.c

521

reg = gic_its_read_8(sc, GITS_BASER(table));

sys/arm64/arm64/gicv3_its.c

524

reg |= GITS_BASER_INDIRECT;

sys/arm64/arm64/gicv3_its.c

525

gic_its_write_8(sc, GITS_BASER(table), reg);

sys/arm64/arm64/gicv3_its.c

528

reg = gic_its_read_8(sc, GITS_BASER(table));

sys/arm64/arm64/gicv3_its.c

529

return ((reg & GITS_BASER_INDIRECT) != 0);

sys/arm64/arm64/gicv3_its.c

538

uint64_t cache, reg, share, tmp, type;

sys/arm64/arm64/gicv3_its.c

581

reg = gic_its_read_8(sc, GITS_BASER(i));

sys/arm64/arm64/gicv3_its.c

583

type = GITS_BASER_TYPE(reg);

sys/arm64/arm64/gicv3_its.c

588

l1_esize = GITS_BASER_ESIZE(reg);

sys/arm64/arm64/gicv3_its.c

672

reg &= ~(GITS_BASER_VALID | GITS_BASER_INDIRECT |

sys/arm64/arm64/gicv3_its.c

678

reg |= GITS_BASER_VALID |

sys/arm64/arm64/gicv3_its.c

687

reg |=

sys/arm64/arm64/gicv3_its.c

691

reg |=

sys/arm64/arm64/gicv3_its.c

695

reg |=

sys/arm64/arm64/gicv3_its.c

700

gic_its_write_8(sc, GITS_BASER(i), reg);

sys/arm64/arm64/gicv3_its.c

707

(reg & GITS_BASER_SHARE_MASK)) {

sys/arm64/arm64/gicv3_its.c

713

if (tmp != reg) {

sys/arm64/arm64/gicv3_its.c

716

i, reg, tmp);

sys/arm64/arm64/identcpu.c

2369

int reg;

sys/arm64/arm64/identcpu.c

2392

reg = ISS_MSR_Rt(esr);

sys/arm64/arm64/identcpu.c

2394

if (reg == 31)

sys/arm64/arm64/identcpu.c

2397

if (reg < nitems(frame->tf_x))

sys/arm64/arm64/identcpu.c

2398

frame->tf_x[reg] = value;

sys/arm64/arm64/identcpu.c

2399

else if (reg == 30)

sys/arm64/arm64/identcpu.c

2409

int reg;

sys/arm64/arm64/identcpu.c

2470

reg = ISS_MSR_Rt(esr);

sys/arm64/arm64/identcpu.c

2472

if (reg == 31)

sys/arm64/arm64/identcpu.c

2475

if (reg < nitems(frame->tf_x))

sys/arm64/arm64/identcpu.c

2476

frame->tf_x[reg] = value;

sys/arm64/arm64/identcpu.c

2477

else if (reg == 30)

sys/arm64/arm64/identcpu.c

2767

uint64_t min, reg;

sys/arm64/arm64/identcpu.c

2775

reg = CPU_DESC_FIELD(*cpu_desc, i);

sys/arm64/arm64/identcpu.c

2796

if (mrs_field_cmp(reg, min, fields[j].shift,

sys/arm64/arm64/identcpu.c

2965

print_register(struct sbuf *sb, const char *reg_name, uint64_t reg,

sys/arm64/arm64/identcpu.c

2972

print_fields(sb, reg, arg);

sys/arm64/arm64/identcpu.c

2980

print_id_fields(struct sbuf *sb, uint64_t reg, const void *arg)

sys/arm64/arm64/identcpu.c

2994

field = (reg & fields[i].mask) >> fields[i].shift;

sys/arm64/arm64/identcpu.c

3008

reg &= ~(((1ul << fields[i].width) - 1) << fields[i].shift);

sys/arm64/arm64/identcpu.c

3011

if (reg != 0)

sys/arm64/arm64/identcpu.c

3012

sbuf_printf(sb, "%s%#lx", SEP_STR, reg);

sys/arm64/arm64/identcpu.c

3017

print_id_register(struct sbuf *sb, const char *reg_name, uint64_t reg,

sys/arm64/arm64/identcpu.c

3021

print_register(sb, reg_name, reg, print_id_fields, fields);

sys/arm64/arm64/kexec_support.c

139

register_t reg;

sys/arm64/arm64/kexec_support.c

149

reg = pmap_kextract((vm_offset_t)pagetable_l0_ttbr0_bootstrap);

sys/arm64/arm64/kexec_support.c

150

set_ttbr0(reg);

sys/arm64/arm64/machdep.c

981

#define PRINT_REG(reg) \

sys/arm64/arm64/machdep.c

982

db_printf(__STRING(reg) " = %#016lx\n", READ_SPECIALREG(reg))

sys/arm64/arm64/mp_machdep.c

677

start_cpu_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)

sys/arm64/arm64/mp_machdep.c

685

target_cpu = reg[0];

sys/arm64/arm64/mp_machdep.c

688

target_cpu |= reg[1];

sys/arm64/arm64/pl031_rtc.c

109

bus_release_resource(dev, SYS_RES_MEMORY, sc->reg_rid, sc->reg);

sys/arm64/arm64/pl031_rtc.c

120

ts->tv_sec = bus_read_4(sc->reg, RTCDR);

sys/arm64/arm64/pl031_rtc.c

132

bus_write_4(sc->reg, RTCLR, ts->tv_sec);

sys/arm64/arm64/pl031_rtc.c

59

struct resource *reg;

sys/arm64/arm64/pl031_rtc.c

91

sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->reg_rid,

sys/arm64/arm64/pl031_rtc.c

93

if (sc->reg == 0)

sys/arm64/arm64/pmap.c

9149

uint64_t reg;

sys/arm64/arm64/pmap.c

9151

get_kernel_reg(ID_AA64PFR1_EL1, &reg);

sys/arm64/arm64/pmap.c

9152

if (ID_AA64PFR1_BT_VAL(reg) != ID_AA64PFR1_BT_NONE) {

sys/arm64/arm64/pmap.c

9171

uint64_t reg;

sys/arm64/arm64/pmap.c

9174

get_kernel_reg(ID_AA64MMFR2_EL1, &reg);

sys/arm64/arm64/pmap.c

9175

if (ID_AA64MMFR2_CnP_VAL(reg) != ID_AA64MMFR2_CnP_NONE) {

sys/arm64/arm64/ptrauth.c

218

#define LOAD_KEY(space, name, reg) \

sys/arm64/arm64/ptrauth.c

220

"msr "__XSTRING(MRS_REG_ALT_NAME(reg ## KeyLo_EL1))", %0 \n" \

sys/arm64/arm64/ptrauth.c

221

"msr "__XSTRING(MRS_REG_ALT_NAME(reg ## KeyHi_EL1))", %1 \n" \

sys/arm64/arm64/trap.c

449

u_int reg;

sys/arm64/arm64/trap.c

451

for (reg = 0; reg < nitems(frame->tf_x); reg++) {

sys/arm64/arm64/trap.c

452

snprintf(name, sizeof(name), "%sx%d", (reg < 10) ? " " : "",

sys/arm64/arm64/trap.c

453

reg);

sys/arm64/arm64/trap.c

454

print_gp_register(name, frame->tf_x[reg]);

sys/arm64/arm64/vfp.c

895

uint64_t reg;

sys/arm64/arm64/vfp.c

898

get_kernel_reg(ID_AA64PFR0_EL1, &reg);

sys/arm64/arm64/vfp.c

899

if (ID_AA64PFR0_SVE_VAL(reg) == ID_AA64PFR0_SVE_NONE)

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

197

uint16_t phyid, uint32_t reg, uint32_t val, uint32_t op)

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

211

if (reg & MII_ADDR_C45)

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

216

bus_write_4(sc->reg_base, MDIO_ADDR_OFFSET, reg);

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

257

brcm_iproc_mdio_write_mux(device_t dev, int bus, int phy, int reg, int val)

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

268

return (brcm_iproc_mdio_op(sc, phy, reg, val, MDIO_CTRL_WRITE_OP));

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

272

brcm_iproc_mdio_read_mux(device_t dev, int bus, int phy, int reg)

sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c

283

return (brcm_iproc_mdio_op(sc, phy, reg, 0, MDIO_CTRL_READ_OP));

sys/arm64/broadcom/brcmmdio/mdio_nexus_iproc.c

107

brcm_mdionexus_mdio_readreg(device_t dev, int phy, int reg)

sys/arm64/broadcom/brcmmdio/mdio_nexus_iproc.c

114

sc->mux_id, phy, reg));

sys/arm64/broadcom/brcmmdio/mdio_nexus_iproc.c

118

brcm_mdionexus_mdio_writereg(device_t dev, int phy, int reg, int val)

sys/arm64/broadcom/brcmmdio/mdio_nexus_iproc.c

125

sc->mux_id, phy, reg, val));

sys/arm64/broadcom/genet/if_genet.c

1672

gen_miibus_readreg(device_t dev, int phy, int reg)

sys/arm64/broadcom/genet/if_genet.c

1681

(phy << GENET_MDIO_ADDR_SHIFT) | (reg << GENET_MDIO_REG_SHIFT));

sys/arm64/broadcom/genet/if_genet.c

1697

phy, reg);

sys/arm64/broadcom/genet/if_genet.c

1703

gen_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/arm64/broadcom/genet/if_genet.c

1711

(phy << GENET_MDIO_ADDR_SHIFT) | (reg << GENET_MDIO_REG_SHIFT) |

sys/arm64/broadcom/genet/if_genet.c

1723

phy, reg);

sys/arm64/broadcom/genet/if_genet.c

80

#define RD4(sc, reg) bus_read_4((sc)->res[_RES_MAC], (reg))

sys/arm64/broadcom/genet/if_genet.c

81

#define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_MAC], (reg), (val))

sys/arm64/cavium/thunder_pcie_pem.c

459

start = rman_get_start(sc->reg);

sys/arm64/cavium/thunder_pcie_pem.c

551

thunder_pem_config_reg_read(struct thunder_pem_softc *sc, int reg)

sys/arm64/cavium/thunder_pcie_pem.c

557

PEM_CFG_RD_REG_ALIGN(reg));

sys/arm64/cavium/thunder_pcie_pem.c

569

u_int func, u_int reg, int bytes)

sys/arm64/cavium/thunder_pcie_pem.c

578

(func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))

sys/arm64/cavium/thunder_pcie_pem.c

594

data = bus_space_read_1(t, h, reg);

sys/arm64/cavium/thunder_pcie_pem.c

597

data = le16toh(bus_space_read_2(t, h, reg));

sys/arm64/cavium/thunder_pcie_pem.c

600

data = le32toh(bus_space_read_4(t, h, reg));

sys/arm64/cavium/thunder_pcie_pem.c

614

u_int func, u_int reg, uint32_t val, int bytes)

sys/arm64/cavium/thunder_pcie_pem.c

622

(func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))

sys/arm64/cavium/thunder_pcie_pem.c

638

bus_space_write_1(t, h, reg, val);

sys/arm64/cavium/thunder_pcie_pem.c

641

bus_space_write_2(t, h, reg, htole16(val));

sys/arm64/cavium/thunder_pcie_pem.c

644

bus_space_write_4(t, h, reg, htole32(val));

sys/arm64/cavium/thunder_pcie_pem.c

74

#define PCIERC_CFG006_SEC_BUS(reg) (((reg) >> 8) & 0xFF)

sys/arm64/cavium/thunder_pcie_pem.c

75

#define PEM_CFG_RD_REG_ALIGN(reg) ((reg) & ~0x3)

sys/arm64/cavium/thunder_pcie_pem.c

783

sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,

sys/arm64/cavium/thunder_pcie_pem.c

785

if (sc->reg == NULL) {

sys/arm64/cavium/thunder_pcie_pem.c

791

error = bus_map_resource(dev, SYS_RES_MEMORY, sc->reg, &req, &map);

sys/arm64/cavium/thunder_pcie_pem.c

796

rman_set_mapping(sc->reg, &map);

sys/arm64/cavium/thunder_pcie_pem.c

798

sc->reg_bst = rman_get_bustag(sc->reg);

sys/arm64/cavium/thunder_pcie_pem.c

799

sc->reg_bsh = rman_get_bushandle(sc->reg);

sys/arm64/cavium/thunder_pcie_pem.c

918

bus_free_resource(dev, SYS_RES_MEMORY, sc->reg);

sys/arm64/cavium/thunder_pcie_pem.c

932

if (sc->reg != NULL)

sys/arm64/cavium/thunder_pcie_pem.c

933

bus_free_resource(dev, SYS_RES_MEMORY, sc->reg);

sys/arm64/cavium/thunder_pcie_pem.h

37

struct resource *reg;

sys/arm64/coresight/coresight.h

91

int reg;

sys/arm64/coresight/coresight_cpu_debug.c

78

uint32_t reg;

sys/arm64/coresight/coresight_cpu_debug.c

89

reg = bus_read_4(sc->res, EDPRCR);

sys/arm64/coresight/coresight_cpu_debug.c

90

if (reg & EDPRCR_CORENPDRQ)

sys/arm64/coresight/coresight_cpu_debug.c

94

reg |= EDPRCR_COREPURQ;

sys/arm64/coresight/coresight_cpu_debug.c

95

bus_write_4(sc->res, EDPRCR, reg);

sys/arm64/coresight/coresight_cpu_debug.c

98

reg = bus_read_4(sc->res, EDPRSR);

sys/arm64/coresight/coresight_cpu_debug.c

99

} while ((reg & EDPRCR_CORENPDRQ) == 0);

sys/arm64/coresight/coresight_etm4x.c

112

reg = TRCVICTLR_SSSTATUS;

sys/arm64/coresight/coresight_etm4x.c

115

reg |= (1 << EVENT_SEL_S);

sys/arm64/coresight/coresight_etm4x.c

120

reg |= TRCVICTLR_EXLEVEL_NS_M;

sys/arm64/coresight/coresight_etm4x.c

121

reg &= ~TRCVICTLR_EXLEVEL_NS(event->excp_level);

sys/arm64/coresight/coresight_etm4x.c

122

reg |= TRCVICTLR_EXLEVEL_S_M;

sys/arm64/coresight/coresight_etm4x.c

123

reg &= ~TRCVICTLR_EXLEVEL_S(event->excp_level);

sys/arm64/coresight/coresight_etm4x.c

124

bus_write_4(sc->res, TRCVICTLR, reg);

sys/arm64/coresight/coresight_etm4x.c

131

reg = 0;

sys/arm64/coresight/coresight_etm4x.c

133

reg |= TRCACATR_EXLEVEL_S_M;

sys/arm64/coresight/coresight_etm4x.c

134

reg &= ~TRCACATR_EXLEVEL_S(event->excp_level);

sys/arm64/coresight/coresight_etm4x.c

136

reg |= TRCACATR_EXLEVEL_NS_M;

sys/arm64/coresight/coresight_etm4x.c

137

reg &= ~TRCACATR_EXLEVEL_NS(event->excp_level);

sys/arm64/coresight/coresight_etm4x.c

138

bus_write_4(sc->res, TRCACATR(i), reg);

sys/arm64/coresight/coresight_etm4x.c

141

reg = bus_read_4(sc->res, TRCVIIECTLR);

sys/arm64/coresight/coresight_etm4x.c

142

reg |= (1 << (TRCVIIECTLR_INCLUDE_S + i / 2));

sys/arm64/coresight/coresight_etm4x.c

143

bus_write_4(sc->res, TRCVIIECTLR, reg);

sys/arm64/coresight/coresight_etm4x.c

173

uint32_t reg __unused;

sys/arm64/coresight/coresight_etm4x.c

183

reg = bus_read_4(sc->res, TRCIDR(1));

sys/arm64/coresight/coresight_etm4x.c

185

(reg & TRCIDR1_TRCARCHMAJ_M) >> TRCIDR1_TRCARCHMAJ_S,

sys/arm64/coresight/coresight_etm4x.c

186

(reg & TRCIDR1_TRCARCHMIN_M) >> TRCIDR1_TRCARCHMIN_S);

sys/arm64/coresight/coresight_etm4x.c

196

uint32_t reg;

sys/arm64/coresight/coresight_etm4x.c

207

reg = bus_read_4(sc->res, TRCSTATR);

sys/arm64/coresight/coresight_etm4x.c

208

} while ((reg & TRCSTATR_IDLE) == 1);

sys/arm64/coresight/coresight_etm4x.c

221

uint32_t reg;

sys/arm64/coresight/coresight_etm4x.c

230

reg = bus_read_4(sc->res, TRCSTATR);

sys/arm64/coresight/coresight_etm4x.c

231

} while ((reg & TRCSTATR_IDLE) == 0);

sys/arm64/coresight/coresight_etm4x.c

72

uint32_t reg;

sys/arm64/coresight/coresight_etm4x.c

83

reg = TRCCONFIGR_RS | TRCCONFIGR_TS;

sys/arm64/coresight/coresight_etm4x.c

84

reg |= TRCCONFIGR_CID | TRCCONFIGR_VMID;

sys/arm64/coresight/coresight_etm4x.c

85

reg |= TRCCONFIGR_INSTP0_LDRSTR;

sys/arm64/coresight/coresight_etm4x.c

86

reg |= TRCCONFIGR_COND_ALL;

sys/arm64/coresight/coresight_etm4x.c

87

bus_write_4(sc->res, TRCCONFIGR, reg);

sys/arm64/coresight/coresight_fdt.c

88

endp->reg = port_reg;

sys/arm64/coresight/coresight_funnel.c

100

uint32_t reg;

sys/arm64/coresight/coresight_funnel.c

106

reg = bus_read_4(sc->res, FUNNEL_FUNCTL);

sys/arm64/coresight/coresight_funnel.c

107

reg &= ~(1 << endp->reg);

sys/arm64/coresight/coresight_funnel.c

108

bus_write_4(sc->res, FUNNEL_FUNCTL, reg);

sys/arm64/coresight/coresight_funnel.c

80

uint32_t reg;

sys/arm64/coresight/coresight_funnel.c

86

reg = bus_read_4(sc->res, FUNNEL_FUNCTL);

sys/arm64/coresight/coresight_funnel.c

87

reg &= ~(FUNCTL_HOLDTIME_MASK);

sys/arm64/coresight/coresight_funnel.c

88

reg |= (7 << FUNCTL_HOLDTIME_SHIFT);

sys/arm64/coresight/coresight_funnel.c

89

reg |= (1 << endp->reg);

sys/arm64/coresight/coresight_funnel.c

90

bus_write_4(sc->res, FUNNEL_FUNCTL, reg);

sys/arm64/coresight/coresight_replicator.c

72

if (endp->reg == 0) {

sys/arm64/coresight/coresight_tmc.c

107

uint32_t reg;

sys/arm64/coresight/coresight_tmc.c

112

reg = bus_read_4(sc->res, TMC_STS);

sys/arm64/coresight/coresight_tmc.c

113

} while ((reg & STS_TMCREADY) == 0);

sys/arm64/coresight/coresight_tmc.c

138

uint32_t reg;

sys/arm64/coresight/coresight_tmc.c

145

reg = bus_read_4(sc->res, TMC_STS);

sys/arm64/coresight/coresight_tmc.c

146

} while ((reg & STS_TMCREADY) == 0);

sys/arm64/coresight/coresight_tmc.c

151

reg = AXICTL_PROT_CTRL_BIT1;

sys/arm64/coresight/coresight_tmc.c

152

reg |= AXICTL_WRBURSTLEN_16;

sys/arm64/coresight/coresight_tmc.c

159

reg |= AXICTL_AXCACHE_OS;

sys/arm64/coresight/coresight_tmc.c

160

bus_write_4(sc->res, TMC_AXICTL, reg);

sys/arm64/coresight/coresight_tmc.c

162

reg = FFCR_EN_FMT | FFCR_EN_TI | FFCR_FON_FLIN |

sys/arm64/coresight/coresight_tmc.c

164

bus_write_4(sc->res, TMC_FFCR, reg);

sys/arm64/coresight/coresight_tmc.c

175

reg = bus_read_4(sc->res, TMC_STS);

sys/arm64/coresight/coresight_tmc.c

176

reg &= ~STS_FULL;

sys/arm64/coresight/coresight_tmc.c

177

bus_write_4(sc->res, TMC_STS, reg);

sys/arm64/coresight/coresight_tmc.c

188

uint32_t reg;

sys/arm64/coresight/coresight_tmc.c

198

reg = bus_read_4(sc->res, TMC_DEVID);

sys/arm64/coresight/coresight_tmc.c

199

reg &= DEVID_CONFIGTYPE_M;

sys/arm64/coresight/coresight_tmc.c

200

switch (reg) {

sys/arm64/coresight/coresight_tmc.c

62

uint32_t reg;

sys/arm64/coresight/coresight_tmc.c

75

reg = bus_read_4(sc->res, TMC_STS);

sys/arm64/coresight/coresight_tmc.c

76

} while ((reg & STS_TMCREADY) == 1);

sys/arm64/coresight/coresight_tmc.c

88

uint32_t reg;

sys/arm64/coresight/coresight_tmc.c

92

reg = bus_read_4(sc->res, TMC_CTL);

sys/arm64/coresight/coresight_tmc.c

93

reg &= ~CTL_TRACECAPTEN;

sys/arm64/coresight/coresight_tmc.c

94

bus_write_4(sc->res, TMC_CTL, reg);

sys/arm64/coresight/coresight_tmc.c

97

reg = bus_read_4(sc->res, TMC_STS);

sys/arm64/coresight/coresight_tmc.c

98

} while ((reg & STS_TMCREADY) == 1);

sys/arm64/freescale/imx/clk/imx_clk_composite.c

136

uint32_t reg, pre_div, post_div;

sys/arm64/freescale/imx/clk/imx_clk_composite.c

141

READ4(clk, sc->offset, &reg);

sys/arm64/freescale/imx/clk/imx_clk_composite.c

144

pre_div = ((reg & TARGET_ROOT_PRE_PODF_MASK)

sys/arm64/freescale/imx/clk/imx_clk_composite.c

146

post_div = ((reg & TARGET_ROOT_POST_PODF_MASK)

sys/arm64/freescale/imx/clk/imx_clk_gate.c

79

uint32_t reg;

sys/arm64/freescale/imx/clk/imx_clk_gate.c

91

RD4(clk, sc->offset, &reg);

sys/arm64/freescale/imx/clk/imx_clk_mux.c

109

RD4(clk, sc->offset, &reg);

sys/arm64/freescale/imx/clk/imx_clk_mux.c

76

uint32_t reg;

sys/arm64/freescale/imx/clk/imx_clk_mux.c

83

rv = RD4(clk, sc->offset, &reg);

sys/arm64/freescale/imx/clk/imx_clk_mux.c

88

reg = (reg >> sc->shift) & sc->mask;

sys/arm64/freescale/imx/clk/imx_clk_mux.c

89

clknode_init_parent_idx(clk, reg);

sys/arm64/freescale/imx/clk/imx_clk_mux.c

96

uint32_t reg;

sys/arm64/freescale/imx/imx_ccm.c

195

uint32_t reg;

sys/arm64/freescale/imx/imx_ccm.c

199

reg = CCU_READ4(sc, addr);

sys/arm64/freescale/imx/imx_ccm.c

200

reg &= ~clr;

sys/arm64/freescale/imx/imx_ccm.c

201

reg |= set;

sys/arm64/freescale/imx/imx_ccm.c

202

CCU_WRITE4(sc, addr, reg);

sys/arm64/include/_armreg.h

43

#define MRS_REG_ALT_NAME(reg) \

sys/arm64/include/_armreg.h

44

_MRS_REG_ALT_NAME(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2)

sys/arm64/include/_armreg.h

47

#define READ_SPECIALREG(reg) \

sys/arm64/include/_armreg.h

49

__asm __volatile("mrs %0, " __STRING(reg) : "=&r" (_val)); \

sys/arm64/include/_armreg.h

52

#define WRITE_SPECIALREG(reg, _val) \

sys/arm64/include/_armreg.h

53

__asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val))

sys/arm64/include/armreg.h

359

#define CTR_TminLine_VAL(reg) ((reg) & CTR_TminLine_MASK)

sys/arm64/include/armreg.h

363

#define CTR_DIC_VAL(reg) ((reg) & CTR_DIC_MASK)

sys/arm64/include/armreg.h

369

#define CTR_IDC_VAL(reg) ((reg) & CTR_IDC_MASK)

sys/arm64/include/armreg.h

375

#define CTR_CWG_VAL(reg) ((reg) & CTR_CWG_MASK)

sys/arm64/include/armreg.h

376

#define CTR_CWG_SIZE(reg) (4 << (CTR_CWG_VAL(reg) >> CTR_CWG_SHIFT))

sys/arm64/include/armreg.h

380

#define CTR_ERG_VAL(reg) ((reg) & CTR_ERG_MASK)

sys/arm64/include/armreg.h

381

#define CTR_ERG_SIZE(reg) (4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT))

sys/arm64/include/armreg.h

385

#define CTR_DLINE_VAL(reg) ((reg) & CTR_DLINE_MASK)

sys/arm64/include/armreg.h

386

#define CTR_DLINE_SIZE(reg) (4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT))

sys/arm64/include/armreg.h

390

#define CTR_L1IP_VAL(reg) ((reg) & CTR_L1IP_MASK)

sys/arm64/include/armreg.h

396

#define CTR_ILINE_VAL(reg) ((reg) & CTR_ILINE_MASK)

sys/arm64/include/armreg.h

397

#define CTR_ILINE_SIZE(reg) (4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT))

sys/arm64/include/armreg.h

482

#define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT)

sys/arm64/include/armreg.h

592

#define ISS_MSR_REG(reg) \

sys/arm64/include/armreg.h

593

__ISS_MSR_REG(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2)

sys/arm64/include/asm.h

100

cbz reg, 997f; /* If no PAN skip */ \

sys/arm64/include/asm.h

106

#define EXIT_USER_ACCESS(reg) \

sys/arm64/include/asm.h

107

cbz reg, 998f; /* If no PAN skip */ \

sys/arm64/include/asm.h

113

#define EXIT_USER_ACCESS_CHECK(reg, tmp) \

sys/arm64/include/asm.h

115

ldr reg, [tmp]; /* Read it */ \

sys/arm64/include/asm.h

116

cbz reg, 999f; /* If no PAN skip */ \

sys/arm64/include/asm.h

97

#define ENTER_USER_ACCESS(reg, tmp) \

sys/arm64/include/asm.h

99

ldr reg, [tmp]; /* Read it */ \

sys/arm64/include/cmn600_reg.h

54

uint32_t pmu_cmn600_rd4(void *arg, int nodeid, int node_type, off_t reg);

sys/arm64/include/cmn600_reg.h

55

int pmu_cmn600_wr4(void *arg, int nodeid, int node_type, off_t reg,

sys/arm64/include/cmn600_reg.h

57

uint64_t pmu_cmn600_rd8(void *arg, int nodeid, int node_type, off_t reg);

sys/arm64/include/cmn600_reg.h

58

int pmu_cmn600_wr8(void *arg, int nodeid, int node_type, off_t reg,

sys/arm64/include/cmn600_reg.h

60

int pmu_cmn600_set8(void *arg, int nodeid, int node_type, off_t reg,

sys/arm64/include/cmn600_reg.h

62

int pmu_cmn600_clr8(void *arg, int nodeid, int node_type, off_t reg,

sys/arm64/include/cmn600_reg.h

64

int pmu_cmn600_md8(void *arg, int nodeid, int node_type, off_t reg,

sys/arm64/include/cpu.h

283

#define update_special_reg(reg, clear, set) \

sys/arm64/include/cpu.h

284

update_special_reg_iss(reg ## _ISS, clear, set)

sys/arm64/include/cpu.h

286

#define get_kernel_reg(reg, valp) \

sys/arm64/include/cpu.h

287

get_kernel_reg_iss(reg ## _ISS, valp)

sys/arm64/include/cpu.h

289

#define get_kernel_reg_masked(reg, valp, mask) \

sys/arm64/include/cpu.h

290

get_kernel_reg_iss_masked(reg ## _ISS, valp, mask)

sys/arm64/include/cpu.h

292

#define get_user_reg(reg, valp, fbsd) \

sys/arm64/include/cpu.h

293

get_user_reg_iss(reg ## _ISS, valp, fbsd)

sys/arm64/include/vmm.h

179

int vm_get_register(struct vcpu *vcpu, int reg, uint64_t *retval);

sys/arm64/include/vmm.h

180

int vm_set_register(struct vcpu *vcpu, int reg, uint64_t val);

sys/arm64/include/vmm.h

223

enum vm_reg_name reg;

sys/arm64/include/vmm.h

229

enum vm_reg_name reg;

sys/arm64/iommu/smmu.c

1060

uint32_t reg;

sys/arm64/iommu/smmu.c

1064

reg = bus_read_4(sc->res[0], SMMU_CR0);

sys/arm64/iommu/smmu.c

1065

reg &= ~CR0_SMMUEN;

sys/arm64/iommu/smmu.c

1066

error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg);

sys/arm64/iommu/smmu.c

1116

uint32_t reg;

sys/arm64/iommu/smmu.c

1142

reg = IRQ_CTRL_EVENTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN;

sys/arm64/iommu/smmu.c

1144

reg |= IRQ_CTRL_PRIQ_IRQEN;

sys/arm64/iommu/smmu.c

1146

error = smmu_write_ack(sc, SMMU_IRQ_CTRL, SMMU_IRQ_CTRLACK, reg);

sys/arm64/iommu/smmu.c

1215

int reg;

sys/arm64/iommu/smmu.c

1217

reg = bus_read_4(sc->res[0], SMMU_CR0);

sys/arm64/iommu/smmu.c

1219

if (reg & CR0_SMMUEN)

sys/arm64/iommu/smmu.c

1233

reg = CR1_TABLE_SH_IS |

sys/arm64/iommu/smmu.c

1239

bus_write_4(sc->res[0], SMMU_CR1, reg);

sys/arm64/iommu/smmu.c

1241

reg = CR2_PTM | CR2_RECINVSID | CR2_E2H;

sys/arm64/iommu/smmu.c

1242

bus_write_4(sc->res[0], SMMU_CR2, reg);

sys/arm64/iommu/smmu.c

1254

reg = CR0_CMDQEN;

sys/arm64/iommu/smmu.c

1255

error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg);

sys/arm64/iommu/smmu.c

1277

reg |= CR0_EVENTQEN;

sys/arm64/iommu/smmu.c

1278

error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg);

sys/arm64/iommu/smmu.c

1290

reg |= CR0_PRIQEN;

sys/arm64/iommu/smmu.c

1291

error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg);

sys/arm64/iommu/smmu.c

1299

reg |= CR0_ATSCHK;

sys/arm64/iommu/smmu.c

1300

error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg);

sys/arm64/iommu/smmu.c

1307

reg |= CR0_SMMUEN;

sys/arm64/iommu/smmu.c

1308

error = smmu_write_ack(sc, SMMU_CR0, SMMU_CR0ACK, reg);

sys/arm64/iommu/smmu.c

1320

uint32_t reg;

sys/arm64/iommu/smmu.c

1325

reg = bus_read_4(sc->res[0], SMMU_IDR0);

sys/arm64/iommu/smmu.c

1327

if (reg & IDR0_ST_LVL_2) {

sys/arm64/iommu/smmu.c

1334

if (reg & IDR0_CD2L) {

sys/arm64/iommu/smmu.c

1341

switch (reg & IDR0_TTENDIAN_M) {

sys/arm64/iommu/smmu.c

1364

if (reg & IDR0_SEV)

sys/arm64/iommu/smmu.c

1367

if (reg & IDR0_MSI) {

sys/arm64/iommu/smmu.c

1373

if (reg & IDR0_HYP) {

sys/arm64/iommu/smmu.c

1379

if (reg & IDR0_ATS)

sys/arm64/iommu/smmu.c

1382

if (reg & IDR0_PRI)

sys/arm64/iommu/smmu.c

1385

switch (reg & IDR0_STALL_MODEL_M) {

sys/arm64/iommu/smmu.c

1396

if (reg & IDR0_S1P) {

sys/arm64/iommu/smmu.c

1402

if (reg & IDR0_S2P) {

sys/arm64/iommu/smmu.c

1409

switch (reg & IDR0_TTF_M) {

sys/arm64/iommu/smmu.c

1419

if (reg & IDR0_ASID16)

sys/arm64/iommu/smmu.c

1427

if (reg & IDR0_VMID16)

sys/arm64/iommu/smmu.c

1432

reg = bus_read_4(sc->res[0], SMMU_IDR1);

sys/arm64/iommu/smmu.c

1434

if (reg & (IDR1_TABLES_PRESET | IDR1_QUEUES_PRESET | IDR1_REL)) {

sys/arm64/iommu/smmu.c

1440

val = (reg & IDR1_CMDQS_M) >> IDR1_CMDQS_S;

sys/arm64/iommu/smmu.c

1445

val = (reg & IDR1_EVENTQS_M) >> IDR1_EVENTQS_S;

sys/arm64/iommu/smmu.c

1451

val = (reg & IDR1_PRIQS_M) >> IDR1_PRIQS_S;

sys/arm64/iommu/smmu.c

1457

sc->ssid_bits = (reg & IDR1_SSIDSIZE_M) >> IDR1_SSIDSIZE_S;

sys/arm64/iommu/smmu.c

1458

sc->sid_bits = (reg & IDR1_SIDSIZE_M) >> IDR1_SIDSIZE_S;

sys/arm64/iommu/smmu.c

1469

reg = bus_read_4(sc->res[0], SMMU_IDR3);

sys/arm64/iommu/smmu.c

1470

if (reg & IDR3_RIL)

sys/arm64/iommu/smmu.c

1474

reg = bus_read_4(sc->res[0], SMMU_IDR5);

sys/arm64/iommu/smmu.c

1476

switch (reg & IDR5_OAS_M) {

sys/arm64/iommu/smmu.c

1501

if (reg & IDR5_GRAN64K)

sys/arm64/iommu/smmu.c

1503

if (reg & IDR5_GRAN16K)

sys/arm64/iommu/smmu.c

1505

if (reg & IDR5_GRAN4K)

sys/arm64/iommu/smmu.c

1508

if ((reg & IDR5_VAX_M) == IDR5_VAX_52)

sys/arm64/iommu/smmu.c

288

smmu_write_ack(struct smmu_softc *sc, uint32_t reg,

sys/arm64/iommu/smmu.c

296

bus_write_4(sc->res[0], reg, val);

sys/arm64/iommu/smmu.c

887

uint64_t reg;

sys/arm64/iommu/smmu.c

910

reg = STRTAB_BASE_CFG_FMT_LINEAR;

sys/arm64/iommu/smmu.c

911

reg |= sc->sid_bits << STRTAB_BASE_CFG_LOG2SIZE_S;

sys/arm64/iommu/smmu.c

912

strtab->base_cfg = (uint32_t)reg;

sys/arm64/iommu/smmu.c

916

reg = base & STRTAB_BASE_ADDR_M;

sys/arm64/iommu/smmu.c

917

KASSERT(reg == base, ("bad allocation 2"));

sys/arm64/iommu/smmu.c

918

reg |= STRTAB_BASE_RA;

sys/arm64/iommu/smmu.c

919

strtab->base = reg;

sys/arm64/iommu/smmu.c

932

uint32_t reg;

sys/arm64/iommu/smmu.c

964

reg = STRTAB_BASE_CFG_FMT_2LVL;

sys/arm64/iommu/smmu.c

965

reg |= size << STRTAB_BASE_CFG_LOG2SIZE_S;

sys/arm64/iommu/smmu.c

966

reg |= STRTAB_SPLIT << STRTAB_BASE_CFG_SPLIT_S;

sys/arm64/iommu/smmu.c

967

strtab->base_cfg = (uint32_t)reg;

sys/arm64/linux/linux.h

193

struct reg;

sys/arm64/linux/linux.h

196

void bsd_to_linux_regset(const struct reg *b_reg,

sys/arm64/linux/linux.h

198

void linux_to_bsd_regset(struct reg *b_reg,

sys/arm64/linux/linux.h

200

void linux_ptrace_get_syscall_info_machdep(const struct reg *reg,

sys/arm64/linux/linux_machdep.c

103

si->instruction_pointer = reg->lr;

sys/arm64/linux/linux_machdep.c

104

si->stack_pointer = reg->sp;

sys/arm64/linux/linux_machdep.c

71

bsd_to_linux_regset(const struct reg *b_reg, struct linux_pt_regset *l_regset)

sys/arm64/linux/linux_machdep.c

85

linux_to_bsd_regset(struct reg *b_reg, const struct linux_pt_regset *l_regset)

sys/arm64/linux/linux_machdep.c

98

linux_ptrace_get_syscall_info_machdep(const struct reg *reg,

sys/arm64/linux/linux_vdso_gtod.c

122

uint64_t reg;

sys/arm64/linux/linux_vdso_gtod.c

124

__asm __volatile("mrs %0, cntvct_el0" : "=r" (reg));

sys/arm64/linux/linux_vdso_gtod.c

125

return (reg);

sys/arm64/linux/linux_vdso_gtod.c

131

uint64_t reg;

sys/arm64/linux/linux_vdso_gtod.c

133

__asm __volatile("mrs %0, cntpct_el0" : "=r" (reg));

sys/arm64/linux/linux_vdso_gtod.c

134

return (reg);

sys/arm64/nvidia/tegra210/max77620.c

111

addr = reg;

sys/arm64/nvidia/tegra210/max77620.c

116

"Error when reading reg 0x%02X, rv: %d\n", reg, rv);

sys/arm64/nvidia/tegra210/max77620.c

124

max77620_write(struct max77620_softc *sc, uint8_t reg, uint8_t val)

sys/arm64/nvidia/tegra210/max77620.c

134

data[0] = reg;

sys/arm64/nvidia/tegra210/max77620.c

140

"Error when writing reg 0x%02X, rv: %d\n", reg, rv);

sys/arm64/nvidia/tegra210/max77620.c

147

max77620_write_buf(struct max77620_softc *sc, uint8_t reg, uint8_t *buf,

sys/arm64/nvidia/tegra210/max77620.c

159

data[0] = reg;

sys/arm64/nvidia/tegra210/max77620.c

164

"Error when writing reg 0x%02X, rv: %d\n", reg, rv);

sys/arm64/nvidia/tegra210/max77620.c

171

max77620_modify(struct max77620_softc *sc, uint8_t reg, uint8_t clear,

sys/arm64/nvidia/tegra210/max77620.c

177

rv = max77620_read(sc, reg, &val);

sys/arm64/nvidia/tegra210/max77620.c

184

rv = max77620_write(sc, reg, val);

sys/arm64/nvidia/tegra210/max77620.c

76

max77620_read(struct max77620_softc *sc, uint8_t reg, uint8_t *val)

sys/arm64/nvidia/tegra210/max77620.c

87

addr = reg;

sys/arm64/nvidia/tegra210/max77620.c

92

"Error when reading reg 0x%02X, rv: %d\n", reg, rv);

sys/arm64/nvidia/tegra210/max77620.c

99

int max77620_read_buf(struct max77620_softc *sc, uint8_t reg, uint8_t *buf,

sys/arm64/nvidia/tegra210/max77620.h

224

#define RD1(sc, reg, val) max77620_read(sc, reg, val)

sys/arm64/nvidia/tegra210/max77620.h

225

#define WR1(sc, reg, val) max77620_write(sc, reg, val)

sys/arm64/nvidia/tegra210/max77620.h

226

#define RM1(sc, reg, clr, set) max77620_modify(sc, reg, clr, set)

sys/arm64/nvidia/tegra210/max77620.h

228

int max77620_read(struct max77620_softc *sc, uint8_t reg, uint8_t *val);

sys/arm64/nvidia/tegra210/max77620.h

229

int max77620_write(struct max77620_softc *sc, uint8_t reg, uint8_t val);

sys/arm64/nvidia/tegra210/max77620.h

230

int max77620_modify(struct max77620_softc *sc, uint8_t reg, uint8_t clear,

sys/arm64/nvidia/tegra210/max77620.h

232

int max77620_read_buf(struct max77620_softc *sc, uint8_t reg, uint8_t *buf,

sys/arm64/nvidia/tegra210/max77620.h

234

int max77620_write_buf(struct max77620_softc *sc, uint8_t reg, uint8_t *buf,

sys/arm64/nvidia/tegra210/max77620_gpio.c

101

uint8_t reg;

sys/arm64/nvidia/tegra210/max77620_gpio.c

194

uint8_t reg;

sys/arm64/nvidia/tegra210/max77620_gpio.c

211

rv = RD1(sc, pin->reg, &reg);

sys/arm64/nvidia/tegra210/max77620_gpio.c

250

reg &= ~MAX77620_REG_GPIO_DRV(~0);

sys/arm64/nvidia/tegra210/max77620_gpio.c

251

reg |= MAX77620_REG_GPIO_DRV(MAX77620_REG_GPIO_DRV_OPENDRAIN);

sys/arm64/nvidia/tegra210/max77620_gpio.c

255

reg &= ~MAX77620_REG_GPIO_DRV(~0);

sys/arm64/nvidia/tegra210/max77620_gpio.c

256

reg |= MAX77620_REG_GPIO_DRV(MAX77620_REG_GPIO_DRV_PUSHPULL);

sys/arm64/nvidia/tegra210/max77620_gpio.c

259

rv = WR1(sc, pin->reg, reg);

sys/arm64/nvidia/tegra210/max77620_gpio.c

440

uint8_t reg;

sys/arm64/nvidia/tegra210/max77620_gpio.c

446

rv = RD1(sc, pin->reg, &reg);

sys/arm64/nvidia/tegra210/max77620_gpio.c

462

if (MAX77620_REG_GPIO_DRV_GET(reg) == MAX77620_REG_GPIO_DRV_PUSHPULL)

sys/arm64/nvidia/tegra210/max77620_gpio.c

468

if (MAX77620_REG_GPIO_DRV_GET(reg) == MAX77620_REG_GPIO_DRV_PUSHPULL)

sys/arm64/nvidia/tegra210/max77620_gpio.c

504

uint8_t reg;

sys/arm64/nvidia/tegra210/max77620_gpio.c

527

rv = RD1(sc, pin->reg, &reg);

sys/arm64/nvidia/tegra210/max77620_gpio.c

545

reg &= ~MAX77620_REG_GPIO_DRV(~0);

sys/arm64/nvidia/tegra210/max77620_gpio.c

546

reg |= MAX77620_REG_GPIO_DRV(MAX77620_REG_GPIO_DRV_OPENDRAIN);

sys/arm64/nvidia/tegra210/max77620_gpio.c

547

reg &= ~MAX77620_REG_GPIO_OUTPUT_VAL(~0);

sys/arm64/nvidia/tegra210/max77620_gpio.c

548

reg |= MAX77620_REG_GPIO_OUTPUT_VAL(1);

sys/arm64/nvidia/tegra210/max77620_gpio.c

553

reg &= ~MAX77620_REG_GPIO_DRV(~0);

sys/arm64/nvidia/tegra210/max77620_gpio.c

554

reg |= MAX77620_REG_GPIO_DRV(MAX77620_REG_GPIO_DRV_PUSHPULL);

sys/arm64/nvidia/tegra210/max77620_gpio.c

556

reg &= ~MAX77620_REG_GPIO_DRV(~0);

sys/arm64/nvidia/tegra210/max77620_gpio.c

557

reg |= MAX77620_REG_GPIO_DRV(MAX77620_REG_GPIO_DRV_OPENDRAIN);

sys/arm64/nvidia/tegra210/max77620_gpio.c

560

rv = WR1(sc, pin->reg, reg);

sys/arm64/nvidia/tegra210/max77620_gpio.c

600

rv = RM1(sc, sc->gpio_pins[pin]->reg, MAX77620_REG_GPIO_OUTPUT_VAL(~0),

sys/arm64/nvidia/tegra210/max77620_gpio.c

618

rv = RD1(sc, sc->gpio_pins[pin]->reg, &tmp);

sys/arm64/nvidia/tegra210/max77620_gpio.c

643

rv = RD1(sc, sc->gpio_pins[pin]->reg, &tmp);

sys/arm64/nvidia/tegra210/max77620_gpio.c

649

rv = RM1(sc, sc->gpio_pins[pin]->reg, MAX77620_REG_GPIO_OUTPUT_VAL(~0),

sys/arm64/nvidia/tegra210/max77620_gpio.c

708

pin->reg = MAX77620_REG_GPIO0 + i;

sys/arm64/nvidia/tegra210/max77620_regulators.c

760

struct max77620_reg_sc *reg;

sys/arm64/nvidia/tegra210/max77620_regulators.c

787

reg = max77620_attach(sc, child, max77620s_def + i);

sys/arm64/nvidia/tegra210/max77620_regulators.c

788

if (reg == NULL) {

sys/arm64/nvidia/tegra210/max77620_regulators.c

793

sc->regs[i] = reg;

sys/arm64/nvidia/tegra210/max77620_rtc.c

100

max77620_rtc_read(struct max77620_rtc_softc *sc, uint8_t reg, uint8_t *val)

sys/arm64/nvidia/tegra210/max77620_rtc.c

111

addr = reg;

sys/arm64/nvidia/tegra210/max77620_rtc.c

116

"Error when reading reg 0x%02X, rv: %d\n", reg, rv);

sys/arm64/nvidia/tegra210/max77620_rtc.c

124

max77620_rtc_read_buf(struct max77620_rtc_softc *sc, uint8_t reg,

sys/arm64/nvidia/tegra210/max77620_rtc.c

136

addr = reg;

sys/arm64/nvidia/tegra210/max77620_rtc.c

141

"Error when reading reg 0x%02X, rv: %d\n", reg, rv);

sys/arm64/nvidia/tegra210/max77620_rtc.c

149

max77620_rtc_write(struct max77620_rtc_softc *sc, uint8_t reg, uint8_t val)

sys/arm64/nvidia/tegra210/max77620_rtc.c

159

data[0] = reg;

sys/arm64/nvidia/tegra210/max77620_rtc.c

165

"Error when writing reg 0x%02X, rv: %d\n", reg, rv);

sys/arm64/nvidia/tegra210/max77620_rtc.c

172

max77620_rtc_write_buf(struct max77620_rtc_softc *sc, uint8_t reg, uint8_t *buf,

sys/arm64/nvidia/tegra210/max77620_rtc.c

184

data[0] = reg;

sys/arm64/nvidia/tegra210/max77620_rtc.c

189

"Error when writing reg 0x%02X, rv: %d\n", reg, rv);

sys/arm64/nvidia/tegra210/max77620_rtc.c

196

max77620_rtc_modify(struct max77620_rtc_softc *sc, uint8_t reg, uint8_t clear,

sys/arm64/nvidia/tegra210/max77620_rtc.c

202

rv = max77620_rtc_read(sc, reg, &val);

sys/arm64/nvidia/tegra210/max77620_rtc.c

209

rv = max77620_rtc_write(sc, reg, val);

sys/arm64/nvidia/tegra210/max77620_rtc.c

219

uint8_t reg;

sys/arm64/nvidia/tegra210/max77620_rtc.c

222

reg = for_read ? RTC_UPDATE0_RTC_RBUDR: RTC_UPDATE0_RTC_UDR;

sys/arm64/nvidia/tegra210/max77620_rtc.c

223

rv = max77620_rtc_modify(sc, MAX77620_RTC_UPDATE0, reg, reg);

sys/arm64/nvidia/tegra210/max77620_rtc.c

329

uint8_t reg;

sys/arm64/nvidia/tegra210/max77620_rtc.c

338

reg = RTC_CONTROL_MODE_24 | RTC_CONTROL_BCD_EN;

sys/arm64/nvidia/tegra210/max77620_rtc.c

339

rv = max77620_rtc_modify(sc, MAX77620_RTC_CONTROLM, reg, reg);

sys/arm64/nvidia/tegra210/max77620_rtc.c

345

rv = max77620_rtc_modify(sc, MAX77620_RTC_CONTROL, reg, reg);

sys/arm64/nvidia/tegra210/tegra210_car.c

484

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_car.c

487

reg = bus_read_4(sc->mem_res, addr);

sys/arm64/nvidia/tegra210/tegra210_car.c

488

reg &= ~clear_mask;

sys/arm64/nvidia/tegra210/tegra210_car.c

489

reg |= set_mask;

sys/arm64/nvidia/tegra210/tegra210_car.c

490

bus_write_4(sc->mem_res, addr, reg);

sys/arm64/nvidia/tegra210/tegra210_car.h

33

#define RD4(sc, reg, val) CLKDEV_READ_4((sc)->clkdev, reg, val)

sys/arm64/nvidia/tegra210/tegra210_car.h

34

#define WR4(sc, reg, val) CLKDEV_WRITE_4((sc)->clkdev, reg, val)

sys/arm64/nvidia/tegra210/tegra210_car.h

35

#define MD4(sc, reg, mask, set) CLKDEV_MODIFY_4((sc)->clkdev, reg, mask, set)

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

662

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

669

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

674

sc->mux = (reg >> PERLCK_MUX_SHIFT) & PERLCK_MUX_MASK;

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

678

sc->divider = (reg & sc->div_mask) + 2;

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

682

if (!(reg & PERLCK_UDIV_DIS))

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

688

if (!(reg & PERLCK_AMUX_DIS) && (sc->mux == 7)) {

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

690

((reg >> PERLCK_AMUX_SHIFT) & PERLCK_MUX_MASK);

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

701

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

710

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

711

reg &= ~(PERLCK_MUX_MASK << PERLCK_MUX_SHIFT);

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

713

reg &= ~PERLCK_AMUX_DIS;

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

714

reg &= ~(PERLCK_MUX_MASK << PERLCK_AMUX_SHIFT);

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

717

reg |= idx << PERLCK_MUX_SHIFT;

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

719

reg |= 7 << PERLCK_MUX_SHIFT;

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

720

reg |= (idx - 8) << PERLCK_AMUX_SHIFT;

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

723

reg |= idx << PERLCK_MUX_SHIFT;

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

725

WR4(sc, sc->base_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

735

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

741

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

871

uint32_t reg, mask, base_reg;

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

880

RD4(sc, base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

891

uint32_t reg, mask, base_reg;

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

898

RD4(sc, base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

900

*enabled = reg & mask ? true: false;

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

908

uint32_t reg, mask, reset_reg;

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

914

CLKDEV_READ_4(sc->dev, DFLL_BASE, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

920

CLKDEV_READ_4(sc->dev, reset_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

926

CLKDEV_READ_4(sc->dev, reset_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1117

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1153

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1154

reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1156

WR4(sc, sc->base_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1162

RD4(sc, PLLX_MISC_2, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1163

reg &= ~PLLX_MISC_2_EN_DYNRAMP;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1164

WR4(sc, PLLX_MISC_2, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1167

RD4(sc, PLLX_MISC_2, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1168

reg &= ~PLLX_MISC_2_NDIV_NEW(~0);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1169

reg |= PLLX_MISC_2_NDIV_NEW(n);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1170

WR4(sc, PLLX_MISC_2, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1173

RD4(sc, PLLX_MISC_2, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1174

reg |= PLLX_MISC_2_EN_DYNRAMP;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1175

WR4(sc, PLLX_MISC_2, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1179

RD4(sc, PLLX_MISC_2, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1180

if (reg & PLLX_MISC_2_DYNRAMP_DONE)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1190

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1191

reg = set_masked(reg, n, mnp_bits->n_shift,

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1193

WR4(sc, sc->base_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1196

RD4(sc, PLLX_MISC_2, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1197

reg &= ~PLLX_MISC_2_EN_DYNRAMP;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1198

WR4(sc, PLLX_MISC_2, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1208

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1209

reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1211

WR4(sc, sc->base_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1224

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1226

RD4(sc, PLLX_MISC, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1227

reg = PLLX_MISC_LOCK_ENABLE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1228

WR4(sc, PLLX_MISC, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1231

reg = 0;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1232

reg |= PLLX_MISC_2_DYNRAMP_STEPA(PLLX_STEP_A);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1233

reg |= PLLX_MISC_2_DYNRAMP_STEPB(PLLX_STEP_B);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1234

WR4(sc, PLLX_MISC_2, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1237

reg = 0;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1238

WR4(sc, PLLX_MISC_4, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1239

WR4(sc, PLLX_MISC_5, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1305

uint32_t reg, rv;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1316

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1317

if (reg & PLL_BASE_ENABLE) {

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1318

RD4(sc, sc->misc_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1319

reg |= sc->lock_enable;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1320

WR4(sc, sc->misc_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1323

RD4(sc, sc->misc_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1324

reg &= ~(1 << 29); /* Disable lock override */

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1325

WR4(sc, sc->misc_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1336

uint32_t reg, misc_reg;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1341

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1356

clknode_get_name(clk), reg, misc_reg, m, n, p, pr,

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1357

(reg >> 30) & 1, (reg >> 29) & 1, (reg >> 28) & 1,

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1399

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1408

CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1409

reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1410

CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1412

CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1413

reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1414

reg |= UTMIP_PLL_CFG2_STABLE_COUNT(STABLE_COUNT);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1415

reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1416

reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(ACTIVE_DELAY_COUNT);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1417

CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1419

CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1420

reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1421

reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(ENABLE_DELAY_COUNT);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1422

reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1423

reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(XTAL_FREQ_COUNT);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1424

reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1425

CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1427

reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1428

reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1429

CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1433

CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1434

reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1435

reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1436

reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1437

reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1438

reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1439

reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1440

CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1443

CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1444

reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1445

reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1446

CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1450

CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1451

reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1452

reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1453

CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1456

CLKDEV_READ_4(sc->dev, XUSB_PLL_CFG0, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1457

reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1458

CLKDEV_WRITE_4(sc->dev, XUSB_PLL_CFG0, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1462

CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1463

reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1464

CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

600

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

603

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

605

reg &= ~PLL_BASE_BYPASS;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

606

reg |= PLL_BASE_ENABLE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

607

WR4(sc, sc->base_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

614

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

616

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

618

reg |= PLL_BASE_BYPASS;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

619

reg &= ~PLL_BASE_ENABLE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

620

WR4(sc, sc->base_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

646

reg_to_pdiv(struct pll_sc *sc, uint32_t reg)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

653

return (1 << reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

655

return (reg == 0 ? 1: reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

658

if (reg == tbl->value)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

710

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

714

RD4(sc, sc->misc_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

715

reg &= PLLREFE_MISC_LOCK;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

719

RD4(sc, sc->misc_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

720

reg &= PLLE_MISC_LOCK;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

724

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

725

reg &= PLL_BASE_LOCK;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

728

return (reg != 0);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

751

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

758

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

759

reg &= ~PLLE_BASE_LOCK_OVERRIDE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

760

WR4(sc, sc->base_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

763

RD4(sc, PLLE_AUX, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

764

reg |= PLLE_AUX_ENABLE_SWCTL;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

765

reg &= ~PLLE_AUX_SEQ_ENABLE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

766

WR4(sc, PLLE_AUX, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

769

RD4(sc, sc->misc_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

770

reg |= PLLE_MISC_LOCK_ENABLE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

771

reg |= PLLE_MISC_IDDQ_SWCTL;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

772

reg &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

773

reg |= PLLE_MISC_PTS;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

774

reg &= ~PLLE_MISC_VREG_BG_CTRL(~0);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

775

reg &= ~PLLE_MISC_VREG_CTRL(~0);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

776

WR4(sc, sc->misc_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

779

RD4(sc, PLLE_SS_CNTL, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

780

reg |= PLLE_SS_CNTL_DISABLE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

781

WR4(sc, PLLE_SS_CNTL, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

783

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

784

reg = set_divisors(sc, reg, pll_m, pll_n, pll_cml);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

785

WR4(sc, sc->base_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

793

RD4(sc, PLLE_SS_CNTL, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

794

reg &= ~PLLE_SS_CNTL_SSCINCINTRV(~0);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

795

reg &= ~PLLE_SS_CNTL_SSCINC(~0);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

796

reg &= ~PLLE_SS_CNTL_SSCINVERT;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

797

reg &= ~PLLE_SS_CNTL_SSCCENTER;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

798

reg &= ~PLLE_SS_CNTL_SSCMAX(~0);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

799

reg |= PLLE_SS_CNTL_SSCINCINTRV(0x23);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

800

reg |= PLLE_SS_CNTL_SSCINC(0x1);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

801

reg |= PLLE_SS_CNTL_SSCMAX(0x21);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

802

WR4(sc, PLLE_SS_CNTL, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

803

reg &= ~PLLE_SS_CNTL_SSCBYP;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

804

reg &= ~PLLE_SS_CNTL_BYPASS_SS;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

805

WR4(sc, PLLE_SS_CNTL, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

808

reg &= ~PLLE_SS_CNTL_INTERP_RESET;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

809

WR4(sc, PLLE_SS_CNTL, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

813

RD4(sc, sc->misc_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

814

reg &= ~PLLE_MISC_IDDQ_SWCTL;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

815

WR4(sc, sc->misc_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

817

RD4(sc, PLLE_AUX, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

818

reg |= PLLE_AUX_USE_LOCKDET;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

819

reg |= PLLE_AUX_SS_SEQ_INCLUDE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

820

reg &= ~PLLE_AUX_ENABLE_SWCTL;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

821

reg &= ~PLLE_AUX_SS_SWCTL;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

822

WR4(sc, PLLE_AUX, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

823

reg |= PLLE_AUX_SEQ_START_STATE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

825

reg |= PLLE_AUX_SEQ_ENABLE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

826

WR4(sc, PLLE_AUX, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

829

RD4(sc, XUSBIO_PLL_CFG0, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

830

reg &= ~XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

831

reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

832

reg |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

833

reg |= XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

834

reg &= ~XUSBIO_PLL_CFG0_SEQ_ENABLE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

835

WR4(sc, XUSBIO_PLL_CFG0, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

838

reg |= XUSBIO_PLL_CFG0_SEQ_ENABLE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

839

WR4(sc, XUSBIO_PLL_CFG0, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

843

RD4(sc, SATA_PLL_CFG0, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

844

reg &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

845

reg &= ~SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

846

reg |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

847

reg |= SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

848

reg &= ~SATA_PLL_CFG0_SEQ_IN_SWCTL;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

849

reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

850

reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

851

reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

852

reg &= ~SATA_PLL_CFG0_SEQ_ENABLE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

853

WR4(sc, SATA_PLL_CFG0, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

855

reg |= SATA_PLL_CFG0_SEQ_ENABLE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

856

WR4(sc, SATA_PLL_CFG0, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

859

RD4(sc, PCIE_PLL_CFG, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

860

reg |= PCIE_PLL_CFG_SEQ_ENABLE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

861

WR4(sc, PCIE_PLL_CFG, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

888

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

892

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

893

*enabled = reg & PLL_BASE_ENABLE ? true: false;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

894

WR4(sc, sc->base_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

902

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

930

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

931

reg = set_masked(reg, m, mnp_bits->m_shift, mnp_bits->m_width);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

932

reg = set_masked(reg, n, mnp_bits->n_shift, mnp_bits->n_width);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

933

reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

935

WR4(sc, sc->base_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

938

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

939

reg |= PLL_BASE_ENABLE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

940

WR4(sc, sc->base_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

943

RD4(sc, sc->misc_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

944

reg |= sc->lock_enable;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

945

WR4(sc, sc->misc_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

950

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

951

reg &= ~PLL_BASE_ENABLE;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

952

WR4(sc, sc->base_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

955

RD4(sc, sc->misc_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

125

super_mux_get_state(uint32_t reg)

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

127

reg = (reg >> SUPER_MUX_STATE_BIT_SHIFT) & SUPER_MUX_STATE_BIT_MASK;

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

128

if (reg & SUPER_MUX_STATE_BIT_FIQ)

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

130

if (reg & SUPER_MUX_STATE_BIT_IRQ)

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

132

if (reg & SUPER_MUX_STATE_BIT_RUN)

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

134

if (reg & SUPER_MUX_STATE_BIT_IDLE)

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

143

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

149

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

151

state = super_mux_get_state(reg);

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

159

sc->mux = (reg >> shift) & ((1 << SUPER_MUX_MUX_WIDTH) - 1);

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

172

uint32_t reg, dummy;

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

177

RD4(sc, sc->base_reg, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

178

state = super_mux_get_state(reg);

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

187

reg &= ~(((1 << SUPER_MUX_MUX_WIDTH) - 1) << shift);

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

188

reg |= idx << shift;

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

190

WR4(sc, sc->base_reg, reg);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

167

bus_size_t reg;

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

177

.reg = r - 0x8D4, \

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

216

bus_size_t reg;

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

225

.reg = r, \

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

229

.grp.reg = gr - 0x8D4, \

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

239

.reg = r, \

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

243

.grp.reg = gr - 0x8D4, \

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

457

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

459

reg = bus_read_4(sc->mux_mem_res, mux->reg);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

469

reg &= ~(TEGRA_MUX_FUNCTION_MASK << TEGRA_MUX_FUNCTION_SHIFT);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

470

reg |= (tmp & TEGRA_MUX_FUNCTION_MASK) <<

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

474

reg &= ~(TEGRA_MUX_PUPD_MASK << TEGRA_MUX_PUPD_SHIFT);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

475

reg |= (cfg->params[PROP_ID_PULL] & TEGRA_MUX_PUPD_MASK) <<

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

479

reg &= ~(1 << TEGRA_MUX_TRISTATE_SHIFT);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

480

reg |= (cfg->params[PROP_ID_TRISTATE] & 1) <<

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

484

reg &= ~(1 << TEGRA_MUX_ENABLE_INPUT_SHIFT);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

485

reg |= (cfg->params[TEGRA_MUX_ENABLE_INPUT_SHIFT] & 1) <<

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

489

reg &= ~(1 << TEGRA_MUX_ENABLE_INPUT_SHIFT);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

490

reg |= (cfg->params[PROP_ID_ENABLE_INPUT] & 1) <<

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

494

reg &= ~(1 << TEGRA_MUX_ENABLE_INPUT_SHIFT);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

495

reg |= (cfg->params[PROP_ID_OPEN_DRAIN] & 1) <<

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

499

reg &= ~(1 << TEGRA_MUX_LOCK_SHIFT);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

500

reg |= (cfg->params[PROP_ID_LOCK] & 1) <<

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

504

reg &= ~(1 << TEGRA_MUX_IORESET_SHIFT);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

505

reg |= (cfg->params[PROP_ID_IORESET] & 1) <<

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

509

reg &= ~(1 << TEGRA_MUX_RCV_SEL_SHIFT);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

510

reg |= (cfg->params[PROP_ID_RCV_SEL] & 1) <<

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

513

bus_write_4(sc->mux_mem_res, mux->reg, reg);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

521

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

523

reg = bus_read_4(sc->pad_mem_res, grp->reg);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

526

reg &= ~(1 << TEGRA_GRP_HSM_SHIFT);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

527

reg |= (cfg->params[PROP_ID_HIGH_SPEED_MODE] & 1) <<

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

531

reg &= ~(1 << TEGRA_GRP_SCHMT_SHIFT);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

532

reg |= (cfg->params[PROP_ID_SCHMITT] & 1) <<

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

536

reg &= ~(TEGRA_GRP_DRV_TYPE_MASK << TEGRA_GRP_DRV_TYPE_SHIFT);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

537

reg |= (cfg->params[PROP_ID_DRIVE_TYPE] &

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

541

reg &= ~(TEGRA_GRP_DRV_DRVDN_SLWR_MASK <<

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

543

reg |= (cfg->params[PROP_ID_SLEW_RATE_RISING] &

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

548

reg &= ~(TEGRA_GRP_DRV_DRVUP_SLWF_MASK <<

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

550

reg |= (cfg->params[PROP_ID_SLEW_RATE_FALLING] &

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

556

reg &= ~(grp->drvdn_shift << grp->drvdn_mask);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

557

reg |= (cfg->params[PROP_ID_DRIVE_DOWN_STRENGTH] &

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

562

reg &= ~(grp->drvup_shift << grp->drvup_mask);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

563

reg |= (cfg->params[PROP_ID_DRIVE_UP_STRENGTH] &

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

566

bus_write_4(sc->pad_mem_res, grp->reg, reg);

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

588

if (mux->grp.reg <= 0) {

sys/arm64/nvidia/tegra210/tegra210_pmc.c

222

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_pmc.c

227

reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

228

if (((reg != 0) && ena) || ((reg == 0) && !ena)) {

sys/arm64/nvidia/tegra210/tegra210_pmc.c

234

reg = RD4(sc, PMC_PWRGATE_TOGGLE);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

235

if ((reg & PMC_PWRGATE_TOGGLE_START) == 0)

sys/arm64/nvidia/tegra210/tegra210_pmc.c

247

reg = RD4(sc, PMC_PWRGATE_TOGGLE);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

248

if ((reg & PMC_PWRGATE_TOGGLE_START) == 0)

sys/arm64/nvidia/tegra210/tegra210_pmc.c

263

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_pmc.c

274

reg = RD4(sc, PMC_PWRGATE_STATUS);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

275

if ((reg & PMC_PWRGATE_STATUS_PARTID(id)) == 0)

sys/arm64/nvidia/tegra210/tegra210_pmc.c

287

reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

288

if ((reg & PMC_REMOVE_CLAMPING_CMD_PARTID(swid)) == 0)

sys/arm64/nvidia/tegra210/tegra210_pmc.c

295

reg = RD4(sc, PMC_CLAMP_STATUS);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

296

if ((reg & PMC_CLAMP_STATUS_PARTID(id)) != 0)

sys/arm64/nvidia/tegra210/tegra210_pmc.c

306

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_pmc.c

310

reg = RD4(sc, PMC_PWRGATE_STATUS);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

311

return ((reg & PMC_PWRGATE_STATUS_PARTID(id)) ? 1 : 0);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

546

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_pmc.c

577

reg = RD4(sc, PMC_CNTRL);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

578

reg |= PMC_CNTRL_CPU_PWRREQ_OE;

sys/arm64/nvidia/tegra210/tegra210_pmc.c

579

WR4(sc, PMC_CNTRL, reg);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

582

reg = RD4(sc, PMC_CNTRL);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

584

reg &= ~PMC_CNTRL_SYSCLK_POLARITY;

sys/arm64/nvidia/tegra210/tegra210_pmc.c

586

reg |= PMC_CNTRL_SYSCLK_POLARITY;

sys/arm64/nvidia/tegra210/tegra210_pmc.c

587

WR4(sc, PMC_CNTRL, reg);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

590

reg = RD4(sc, PMC_CNTRL);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

591

reg |= PMC_CNTRL_SYSCLK_OE;

sys/arm64/nvidia/tegra210/tegra210_pmc.c

592

WR4(sc, PMC_CNTRL, reg);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

598

reg = RD4(sc, PMC_IO_DPD_STATUS);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

599

reg &= ~ PMC_IO_DPD_STATUS_HDMI;

sys/arm64/nvidia/tegra210/tegra210_pmc.c

600

WR4(sc, PMC_IO_DPD_STATUS, reg);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

602

reg = RD4(sc, PMC_IO_DPD2_STATUS);

sys/arm64/nvidia/tegra210/tegra210_pmc.c

603

reg &= ~ PMC_IO_DPD2_STATUS_HV;

sys/arm64/nvidia/tegra210/tegra210_pmc.c

604

WR4(sc, PMC_IO_DPD2_STATUS, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1002

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1007

reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1009

reg &= ~SS_PORT_MAP_PORT_INTERNAL(port->idx);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1011

reg |= SS_PORT_MAP_PORT_INTERNAL(port->idx);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1012

reg &= ~SS_PORT_MAP_PORT_MAP(port->idx, ~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1013

reg |= SS_PORT_MAP_PORT_MAP(port->idx, port->companion);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1014

WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1025

reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(port->idx));

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1026

reg &= ~UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1027

reg |= UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL(2);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1028

WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(port->idx), reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1030

reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(port->idx));

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1031

reg &= ~UPHY_USB3_PAD_ECTL2_RX_CTLE(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1032

reg |= UPHY_USB3_PAD_ECTL2_RX_CTLE(0x00fc);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1033

WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(port->idx), reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1037

reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(port->idx));

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1038

reg &= ~UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1039

reg |= UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL(0x01c7);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1040

WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(port->idx), reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1051

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1052

reg &= ~ELPG_PROGRAM1_SSP_ELPG_VCORE_DOWN(port->idx);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1053

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1056

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1057

reg &= ~ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN_EARLY(port->idx);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1058

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1061

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1062

reg &= ~ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN(port->idx);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1063

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1072

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1079

reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1080

reg |= USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1081

WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1089

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1091

reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1092

reg &= ~USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1093

WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1104

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1111

reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1112

reg |= USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->idx);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1113

WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1121

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1123

reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1124

reg &= ~USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->idx);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1125

WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1135

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1158

reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx));

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1159

reg &= ~HSIC_PAD_CTL1_TX_RTUNEP(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1160

reg |= HSIC_PAD_CTL1_TX_RTUNEP(sc->tx_rtune_p);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1161

WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1163

reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL2(lane->idx));

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1164

reg &= ~HSIC_PAD_CTL2_RX_STROBE_TRIM(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1165

reg &= ~HSIC_PAD_CTL2_RX_DATA1_TRIM(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1166

reg &= ~HSIC_PAD_CTL2_RX_DATA0_TRIM(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1167

reg |= HSIC_PAD_CTL2_RX_STROBE_TRIM(sc->rx_strobe_trim);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1168

reg |= HSIC_PAD_CTL2_RX_DATA1_TRIM(sc->rx_data1_trim);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1169

reg |= HSIC_PAD_CTL2_RX_DATA0_TRIM(sc->rx_data0_trim);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1170

WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL2(lane->idx), reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1172

reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx));

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1173

reg &= ~HSIC_PAD_CTL0_RPU_DATA0;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1174

reg &= ~HSIC_PAD_CTL0_RPU_DATA1;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1175

reg &= ~HSIC_PAD_CTL0_RPU_STROBE;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1176

reg &= ~HSIC_PAD_CTL0_PD_RX_DATA0;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1177

reg &= ~HSIC_PAD_CTL0_PD_RX_DATA1;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1178

reg &= ~HSIC_PAD_CTL0_PD_RX_STROBE;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1179

reg &= ~HSIC_PAD_CTL0_PD_ZI_DATA0;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1180

reg &= ~HSIC_PAD_CTL0_PD_ZI_DATA1;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1181

reg &= ~HSIC_PAD_CTL0_PD_ZI_STROBE;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1182

reg &= ~HSIC_PAD_CTL0_PD_TX_DATA0;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1183

reg &= ~HSIC_PAD_CTL0_PD_TX_DATA1;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1184

reg &= ~HSIC_PAD_CTL0_PD_TX_STROBE;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1185

reg |= HSIC_PAD_CTL0_RPD_DATA0;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1186

reg |= HSIC_PAD_CTL0_RPD_DATA1;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1187

reg |= HSIC_PAD_CTL0_RPD_STROBE;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1188

WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx), reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1199

reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1200

reg &= ~HSIC_PAD_TRK_CTL_TRK_START_TIMER(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1201

reg &= ~HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1202

reg |= HSIC_PAD_TRK_CTL_TRK_START_TIMER(0x1e);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1203

reg |= HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER(0x0a);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1204

WR4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1208

reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1209

reg &= ~HSIC_PAD_TRK_CTL_PD_TRK;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1210

WR4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1220

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1230

reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx));

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1231

reg |= HSIC_PAD_CTL0_PD_RX_DATA0;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1232

reg |= HSIC_PAD_CTL0_PD_RX_DATA1;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1233

reg |= HSIC_PAD_CTL0_PD_RX_STROBE;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1234

reg |= HSIC_PAD_CTL0_PD_ZI_DATA0;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1235

reg |= HSIC_PAD_CTL0_PD_ZI_DATA1;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1236

reg |= HSIC_PAD_CTL0_PD_ZI_STROBE;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1237

reg |= HSIC_PAD_CTL0_PD_TX_DATA0;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1238

reg |= HSIC_PAD_CTL0_PD_TX_DATA1;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1239

reg |= HSIC_PAD_CTL0_PD_TX_STROBE;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1240

WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1257

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1269

reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1270

reg &= ~USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1271

reg &= ~USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1272

reg |= USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(0x7);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1273

WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1275

reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1276

reg &= ~USB2_PORT_CAP_PORT_CAP(lane->idx, ~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1277

reg |= USB2_PORT_CAP_PORT_CAP(lane->idx, USB2_PORT_CAP_PORT_CAP_HOST);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1278

WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1280

reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx));

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1281

reg &= ~USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1282

reg &= ~USB2_OTG_PAD_CTL0_HS_SLEW(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1283

reg &= ~USB2_OTG_PAD_CTL0_PD;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1284

reg &= ~USB2_OTG_PAD_CTL0_PD2;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1285

reg &= ~USB2_OTG_PAD_CTL0_PD_ZI;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1286

reg |= USB2_OTG_PAD_CTL0_HS_SLEW(14);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1287

reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level[lane->idx] +

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1289

WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1291

reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx));

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1292

reg &= ~USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1293

reg &= ~USB2_OTG_PAD_CTL1_RPD_CTRL(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1294

reg &= ~USB2_OTG_PAD_CTL1_PD_DR;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1295

reg &= ~USB2_OTG_PAD_CTL1_PD_CHRP_OVRD;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1296

reg &= ~USB2_OTG_PAD_CTL1_PD_DISC_OVRD;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1297

reg |= USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(sc->hs_term_range_adj);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1298

reg |= USB2_OTG_PAD_CTL1_RPD_CTRL(sc->rpd_ctrl);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1299

WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1301

reg = RD4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(lane->idx));

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1302

reg &= ~USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1303

reg |= USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1304

WR4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(lane->idx), reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1322

reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1323

reg &= ~USB2_BIAS_PAD_CTL1_TRK_START_TIMER(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1324

reg &= ~USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1325

reg |= USB2_BIAS_PAD_CTL1_TRK_START_TIMER(0x1e);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1326

reg |= USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER(0x0a);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1327

WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1329

reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1330

reg &= ~USB2_BIAS_PAD_CTL0_PD;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1331

WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1338

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1350

reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1351

reg |= USB2_BIAS_PAD_CTL0_PD;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1352

WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1377

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1379

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1380

reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1381

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1384

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1385

reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1386

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1389

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1390

reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1391

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1400

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1402

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1403

reg |= ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1404

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1407

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1408

reg |= ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1409

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1412

reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1413

reg |= ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1414

WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1584

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1586

reg = RD4(sc, lane->reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1587

reg &= ~(lane->mask << lane->shift);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1588

reg |= (lane->mux_idx & lane->mask) << lane->shift;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1589

WR4(sc, lane->reg, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1851

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1854

reg = tegra_fuse_read_4(FUSE_SKU_CALIB_0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1855

sc->hs_curr_level[0] = FUSE_SKU_CALIB_0_HS_CURR_LEVEL_0(reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1858

FUSE_SKU_CALIB_0_HS_CURR_LEVEL_123(reg, i);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1860

sc->hs_term_range_adj = FUSE_SKU_CALIB_0_HS_TERM_RANGE_ADJ(reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1863

sc->rpd_ctrl = FUSE_USB_CALIB_EXT_0_RPD_CTRL(reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

459

bus_size_t reg;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

476

.reg = r, \

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

545

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

570

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

571

reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

572

reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(0x136);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

573

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

575

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

576

reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

577

reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

578

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

580

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

581

reg |= UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

582

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

584

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

585

reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

586

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

588

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

589

reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

590

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

596

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

597

reg &= ~UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

598

reg &= ~UPHY_PLL_P0_CTL4_PLL0_REFCLK_SEL(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

599

reg |= UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL(0x2);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

600

reg |= UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

601

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

603

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

604

reg &= ~UPHY_PLL_P0_CTL1_PLL0_FREQ_MDIV(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

605

reg &= ~UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

606

reg |= UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(0x19);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

607

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

609

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

610

reg &= ~UPHY_PLL_P0_CTL1_PLL0_IDDQ;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

611

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

613

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

614

reg &= ~UPHY_PLL_P0_CTL1_PLL0_SLEEP(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

615

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

621

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

622

reg |= UPHY_PLL_P0_CTL4_PLL0_REFCLKBUF_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

623

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

626

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

627

reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

628

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

630

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

631

if (reg & UPHY_PLL_P0_CTL2_PLL0_CAL_DONE)

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

637

"for pad '%s' (0x%08X).\n", pad->name, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

642

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

643

reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

644

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

646

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

647

if ((reg & UPHY_PLL_P0_CTL2_PLL0_CAL_DONE) == 0)

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

659

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

660

reg |= UPHY_PLL_P0_CTL1_PLL0_ENABLE;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

661

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

663

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

664

if (reg & UPHY_PLL_P0_CTL1_PLL0_LOCKDET_STATUS)

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

676

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

677

reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

678

reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

679

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

682

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

683

if (reg & UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE)

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

694

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

695

reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

696

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

699

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

700

if (!(reg & UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE))

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

712

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

713

reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

714

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

719

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

720

reg &= ~UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

721

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

723

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

724

reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

725

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

727

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

728

reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

729

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

769

uint32_t reg;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

793

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

794

reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

795

reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(0x136);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

796

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

798

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

799

reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

800

reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

801

WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

803

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

804

reg |= UPHY_PLL_S0_CTL1_PLL0_PWR_OVRD;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

805

WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

807

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

808

reg |= UPHY_PLL_S0_CTL2_PLL0_CAL_OVRD;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

809

WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

811

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

812

reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_OVRD;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

813

WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

819

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

820

reg &= ~UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

821

reg &= ~UPHY_PLL_S0_CTL4_PLL0_REFCLK_SEL(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

822

reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

825

reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(0x2);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

827

reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(0x0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

835

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

836

reg &= ~UPHY_PLL_S0_CTL1_PLL0_FREQ_MDIV(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

837

reg &= ~UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

839

reg |= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x19);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

841

reg |= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x1e);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

842

WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

844

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

845

reg &= ~UPHY_PLL_S0_CTL1_PLL0_IDDQ;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

846

WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

848

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

849

reg &= ~UPHY_PLL_S0_CTL1_PLL0_SLEEP(~0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

850

WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

856

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

857

reg |= UPHY_PLL_S0_CTL4_PLL0_REFCLKBUF_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

858

WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

861

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

862

reg |= UPHY_PLL_S0_CTL2_PLL0_CAL_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

863

WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

865

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

866

if (reg & UPHY_PLL_S0_CTL2_PLL0_CAL_DONE)

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

877

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

878

reg &= ~UPHY_PLL_S0_CTL2_PLL0_CAL_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

879

WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

881

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

882

if ((reg & UPHY_PLL_S0_CTL2_PLL0_CAL_DONE) == 0)

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

894

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

895

reg |= UPHY_PLL_S0_CTL1_PLL0_ENABLE;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

896

WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

898

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

899

if (reg & UPHY_PLL_S0_CTL1_PLL0_LOCKDET_STATUS)

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

911

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

912

reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

913

reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_CLK_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

914

WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

916

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

917

if (reg & UPHY_PLL_S0_CTL8_PLL0_RCAL_DONE)

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

928

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

929

reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

930

WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

932

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

933

if (!(reg & UPHY_PLL_S0_CTL8_PLL0_RCAL_DONE))

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

944

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

945

reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_CLK_EN;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

946

WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

951

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

952

reg &= ~UPHY_PLL_S0_CTL1_PLL0_PWR_OVRD;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

953

WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

955

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

956

reg &= ~UPHY_PLL_S0_CTL2_PLL0_CAL_OVRD;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

957

WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

959

reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

960

reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_OVRD;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

961

WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);

sys/arm64/qoriq/clk/qoriq_clkgen.c

122

uint32_t reg;

sys/arm64/qoriq/clk/qoriq_clkgen.c

127

reg = le32toh(bus_read_4(sc->res, addr));

sys/arm64/qoriq/clk/qoriq_clkgen.c

129

reg = be32toh(bus_read_4(sc->res, addr));

sys/arm64/qoriq/clk/qoriq_clkgen.c

131

reg &= ~clr;

sys/arm64/qoriq/clk/qoriq_clkgen.c

132

reg |= set;

sys/arm64/qoriq/clk/qoriq_clkgen.c

135

bus_write_4(sc->res, addr, htole32(reg));

sys/arm64/qoriq/clk/qoriq_clkgen.c

137

bus_write_4(sc->res, addr, htobe32(reg));

sys/arm64/qoriq/qoriq_dw_pci.c

112

uint32_t reg;

sys/arm64/qoriq/qoriq_dw_pci.c

114

reg = pci_dw_dbi_rd4(sc->dev, DW_MISC_CONTROL_1);

sys/arm64/qoriq/qoriq_dw_pci.c

116

reg &= ~DBI_RO_WR_EN;

sys/arm64/qoriq/qoriq_dw_pci.c

118

reg |= DBI_RO_WR_EN;

sys/arm64/qoriq/qoriq_dw_pci.c

119

pci_dw_dbi_wr4(sc->dev, DW_MISC_CONTROL_1, reg);

sys/arm64/qoriq/qoriq_dw_pci.c

142

uint32_t reg;

sys/arm64/qoriq/qoriq_dw_pci.c

145

reg = pci_dw_dbi_rd4(sc->dev, sc->soc_cfg->pex_pf0_dgb);

sys/arm64/qoriq/qoriq_dw_pci.c

146

reg >>= sc->soc_cfg->ltssm_bit;

sys/arm64/qoriq/qoriq_dw_pci.c

147

reg &= 0x3F;

sys/arm64/qoriq/qoriq_dw_pci.c

148

*status = (reg == 0x11) ? true : false;

sys/arm64/qoriq/qoriq_gpio_pic.c

231

uint32_t reg;

sys/arm64/qoriq/qoriq_gpio_pic.c

248

reg = RD4(sc, GPIO_GPICR);

sys/arm64/qoriq/qoriq_gpio_pic.c

250

reg |= BIT(31 - qisrc->pin);

sys/arm64/qoriq/qoriq_gpio_pic.c

252

reg &= ~BIT(31 - qisrc->pin);

sys/arm64/qoriq/qoriq_gpio_pic.c

253

WR4(sc, GPIO_GPICR, reg);

sys/arm64/qoriq/qoriq_gpio_pic.c

77

uint32_t reg;

sys/arm64/qoriq/qoriq_gpio_pic.c

79

reg = RD4(sc, GPIO_GPIMR);

sys/arm64/qoriq/qoriq_gpio_pic.c

81

reg |= BIT(31 - pin);

sys/arm64/qoriq/qoriq_gpio_pic.c

83

reg &= ~BIT(31 - pin);

sys/arm64/qoriq/qoriq_gpio_pic.c

84

WR4(sc, GPIO_GPIMR, reg);

sys/arm64/qoriq/qoriq_gpio_pic.c

90

uint32_t reg;

sys/arm64/qoriq/qoriq_gpio_pic.c

92

reg = BIT(31 - pin);

sys/arm64/qoriq/qoriq_gpio_pic.c

93

WR4(sc, GPIO_GPIER, reg);

sys/arm64/rockchip/rk3328_codec.c

159

#define RKCODEC_READ(sc, reg) bus_read_4((sc)->res, (reg))

sys/arm64/rockchip/rk3328_codec.c

160

#define RKCODEC_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/arm64/rockchip/rk_gpio.c

144

rk_gpio_read_bit(struct rk_gpio_softc *sc, int reg, int bit)

sys/arm64/rockchip/rk_gpio.c

146

struct rk_gpio_reg *rk_reg = &sc->regs[reg];

sys/arm64/rockchip/rk_gpio.c

161

rk_gpio_write_bit(struct rk_gpio_softc *sc, int reg, int bit, int data)

sys/arm64/rockchip/rk_gpio.c

163

struct rk_gpio_reg *rk_reg = &sc->regs[reg];

sys/arm64/rockchip/rk_gpio.c

185

rk_gpio_read_4(struct rk_gpio_softc *sc, int reg)

sys/arm64/rockchip/rk_gpio.c

187

struct rk_gpio_reg *rk_reg = &sc->regs[reg];

sys/arm64/rockchip/rk_gpio.c

199

rk_gpio_write_4(struct rk_gpio_softc *sc, int reg, uint32_t value)

sys/arm64/rockchip/rk_gpio.c

201

struct rk_gpio_reg *rk_reg = &sc->regs[reg];

sys/arm64/rockchip/rk_gpio.c

591

uint32_t reg;

sys/arm64/rockchip/rk_gpio.c

596

reg = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DR);

sys/arm64/rockchip/rk_gpio.c

598

*orig_pins = reg;

sys/arm64/rockchip/rk_gpio.c

599

sc->swporta = reg;

sys/arm64/rockchip/rk_gpio.c

602

reg = (reg & ~clear_pins) ^ change_pins;

sys/arm64/rockchip/rk_gpio.c

603

rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, reg);

sys/arm64/rockchip/rk_gpio.c

615

uint32_t reg, set, mask, flags;

sys/arm64/rockchip/rk_gpio.c

636

reg = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DDR);

sys/arm64/rockchip/rk_gpio.c

637

reg &= ~mask;

sys/arm64/rockchip/rk_gpio.c

638

reg |= set;

sys/arm64/rockchip/rk_gpio.c

639

rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DDR, reg);

sys/arm64/rockchip/rk_gpio.c

640

sc->swporta_ddr = reg;

sys/arm64/rockchip/rk_grf_gpio.c

102

uint32_t reg;

sys/arm64/rockchip/rk_grf_gpio.c

109

reg = SYSCON_READ_4(sc->sc_grf, GRF_SOC_CON10);

sys/arm64/rockchip/rk_grf_gpio.c

110

if (reg & SOC_CON10_GPIOMUT)

sys/arm64/rockchip/rk_i2s.c

163

#define RK_I2S_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/arm64/rockchip/rk_i2s.c

164

#define RK_I2S_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/arm64/rockchip/rk_iodomain.c

164

uint32_t reg = 0;

sys/arm64/rockchip/rk_iodomain.c

193

reg |= (1 << sc->conf->supply[i].bit);

sys/arm64/rockchip/rk_iodomain.c

240

SYSCON_WRITE_4(sc->grf, sc->conf->grf_reg, reg | mask);

sys/arm64/rockchip/rk_pcie.c

166

#define PRIV_CFG_RD4(sc, reg) \

sys/arm64/rockchip/rk_pcie.c

167

(uint32_t)rk_pcie_local_cfg_read(sc, true, reg, 4)

sys/arm64/rockchip/rk_pcie.c

168

#define PRIV_CFG_RD2(sc, reg) \

sys/arm64/rockchip/rk_pcie.c

169

(uint16_t)rk_pcie_local_cfg_read(sc, true, reg, 2)

sys/arm64/rockchip/rk_pcie.c

170

#define PRIV_CFG_RD1(sc, reg) \

sys/arm64/rockchip/rk_pcie.c

171

(uint8_t)rk_pcie_local_cfg_read(sc, true, reg, 1)

sys/arm64/rockchip/rk_pcie.c

172

#define PRIV_CFG_WR4(sc, reg, val) \

sys/arm64/rockchip/rk_pcie.c

173

rk_pcie_local_cfg_write(sc, true, reg, val, 4)

sys/arm64/rockchip/rk_pcie.c

174

#define PRIV_CFG_WR2(sc, reg, val) \

sys/arm64/rockchip/rk_pcie.c

175

rk_pcie_local_cfg_write(sc, true, reg, val, 2)

sys/arm64/rockchip/rk_pcie.c

176

#define PRIV_CFG_WR1(sc, reg, val) \

sys/arm64/rockchip/rk_pcie.c

177

rk_pcie_local_cfg_write(sc, true, reg, val, 1)

sys/arm64/rockchip/rk_pcie.c

245

rk_pcie_local_cfg_read(struct rk_pcie_softc *sc, bool priv, u_int reg,

sys/arm64/rockchip/rk_pcie.c

258

val = bus_read_4(sc->apb_mem_res, base + reg);

sys/arm64/rockchip/rk_pcie.c

261

val = bus_read_2(sc->apb_mem_res, base + reg);

sys/arm64/rockchip/rk_pcie.c

264

val = bus_read_1(sc->apb_mem_res, base + reg);

sys/arm64/rockchip/rk_pcie.c

273

rk_pcie_local_cfg_write(struct rk_pcie_softc *sc, bool priv, u_int reg,

sys/arm64/rockchip/rk_pcie.c

286

bus_write_4(sc->apb_mem_res, base + reg, val);

sys/arm64/rockchip/rk_pcie.c

289

val2 = bus_read_4(sc->apb_mem_res, base + (reg & ~3));

sys/arm64/rockchip/rk_pcie.c

290

val2 &= ~(0xffff << ((reg & 3) << 3));

sys/arm64/rockchip/rk_pcie.c

291

val2 |= ((val & 0xffff) << ((reg & 3) << 3));

sys/arm64/rockchip/rk_pcie.c

292

bus_write_4(sc->apb_mem_res, base + (reg & ~3), val2);

sys/arm64/rockchip/rk_pcie.c

295

val2 = bus_read_4(sc->apb_mem_res, base + (reg & ~3));

sys/arm64/rockchip/rk_pcie.c

296

val2 &= ~(0xff << ((reg & 3) << 3));

sys/arm64/rockchip/rk_pcie.c

297

val2 |= ((val & 0xff) << ((reg & 3) << 3));

sys/arm64/rockchip/rk_pcie.c

298

bus_write_4(sc->apb_mem_res, base + (reg & ~3), val2);

sys/arm64/rockchip/rk_pcie.c

305

u_int reg)

sys/arm64/rockchip/rk_pcie.c

310

func > PCI_FUNCMAX || reg > PCIE_REGMAX)

sys/arm64/rockchip/rk_pcie.c

449

u_int func, u_int reg, int bytes)

sys/arm64/rockchip/rk_pcie.c

460

if (!rk_pcie_check_dev(sc, bus, slot, func, reg))

sys/arm64/rockchip/rk_pcie.c

463

return (rk_pcie_local_cfg_read(sc, false, reg, bytes));

sys/arm64/rockchip/rk_pcie.c

466

ATU_CFG_REG(reg);

sys/arm64/rockchip/rk_pcie.c

492

u_int func, u_int reg, uint32_t val, int bytes)

sys/arm64/rockchip/rk_pcie.c

500

if (!rk_pcie_check_dev(sc, bus, slot, func, reg))

sys/arm64/rockchip/rk_pcie.c

504

return (rk_pcie_local_cfg_write(sc, false, reg, val, bytes));

sys/arm64/rockchip/rk_pcie.c

507

ATU_CFG_REG(reg);

sys/arm64/rockchip/rk_pcie_phy.c

104

cfg_write(struct rk_pcie_phy_softc *sc, uint32_t reg, uint32_t data)

sys/arm64/rockchip/rk_pcie_phy.c

108

(reg & 0x3F) << 1 | (data & 0x0F) << 7);

sys/arm64/rockchip/rk_pcie_phy.c

122

cfg_read(struct rk_pcie_phy_softc *sc, uint32_t reg)

sys/arm64/rockchip/rk_pcie_phy.c

126

WR4(sc, GRF_SOC_CON8, 0x3FF, reg << 1);

sys/arm64/rockchip/rk_pcie_phy.c

97

#define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg))

sys/arm64/rockchip/rk_pcie_phy.c

98

#define WR4(sc, reg, mask, val) \

sys/arm64/rockchip/rk_pcie_phy.c

99

SYSCON_WRITE_4((sc)->syscon, (reg), ((mask) << GRF_HIWORD_SHIFT) | (val))

sys/arm64/rockchip/rk_pinctrl.c

1039

uint32_t *reg, uint32_t *mask, uint32_t *bit)

sys/arm64/rockchip/rk_pinctrl.c

1046

*reg = sc->conf->pin_fixup[i].reg;

sys/arm64/rockchip/rk_pinctrl.c

1145

uint32_t bit, mask, reg, drive;

sys/arm64/rockchip/rk_pinctrl.c

1174

reg = sc->conf->get_pd_offset(sc, bank);

sys/arm64/rockchip/rk_pinctrl.c

1175

reg += bank * 0x10 + ((pin / 8) * 0x4);

sys/arm64/rockchip/rk_pinctrl.c

1178

SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16));

sys/arm64/rockchip/rk_pinctrl.c

1188

reg = 0x01c0 + (bank * 0x40) + (pin / 2 * 4);

sys/arm64/rockchip/rk_pinctrl.c

1190

reg = 0x0070 + (pin / 2 * 4);

sys/arm64/rockchip/rk_pinctrl.c

1196

SYSCON_WRITE_4(syscon, reg, drive | (mask << 16));

sys/arm64/rockchip/rk_pinctrl.c

1200

&reg);

sys/arm64/rockchip/rk_pinctrl.c

1204

SYSCON_MODIFY_4(syscon, reg, mask,

sys/arm64/rockchip/rk_pinctrl.c

1210

reg = sc->conf->iomux_conf[i].offset;

sys/arm64/rockchip/rk_pinctrl.c

1214

reg += 0x4;

sys/arm64/rockchip/rk_pinctrl.c

1220

reg += 4;

sys/arm64/rockchip/rk_pinctrl.c

1234

rk_pinctrl_get_fixup(sc, bank, pin, &reg, &mask, &bit);

sys/arm64/rockchip/rk_pinctrl.c

1242

SYSCON_MODIFY_4(syscon, reg, mask, function << bit | (mask << 16));

sys/arm64/rockchip/rk_pinctrl.c

1282

uint32_t subbank, bit, mask, reg;

sys/arm64/rockchip/rk_pinctrl.c

130

.reg = _reg, \

sys/arm64/rockchip/rk_pinctrl.c

1305

reg = sc->conf->iomux_conf[i].offset;

sys/arm64/rockchip/rk_pinctrl.c

1309

reg += 0x4;

sys/arm64/rockchip/rk_pinctrl.c

1315

reg += 4;

sys/arm64/rockchip/rk_pinctrl.c

1329

rk_pinctrl_get_fixup(sc, bank, pin, &reg, &mask, &bit);

sys/arm64/rockchip/rk_pinctrl.c

1331

reg = SYSCON_READ_4(syscon, reg);

sys/arm64/rockchip/rk_pinctrl.c

1332

pinfunc = (reg & mask) >> bit;

sys/arm64/rockchip/rk_pinctrl.c

1386

uint32_t reg, bit;

sys/arm64/rockchip/rk_pinctrl.c

1407

reg = sc->conf->get_pd_offset(sc, bank);

sys/arm64/rockchip/rk_pinctrl.c

1408

reg += bank * 0x10 + ((pin / 8) * 0x4);

sys/arm64/rockchip/rk_pinctrl.c

1410

reg = SYSCON_READ_4(syscon, reg);

sys/arm64/rockchip/rk_pinctrl.c

1411

reg = (reg >> bit) & 0x3;

sys/arm64/rockchip/rk_pinctrl.c

1412

bias = sc->conf->resolv_bias_value(bank, reg);

sys/arm64/rockchip/rk_pinctrl.c

1426

uint32_t bit, mask, reg;

sys/arm64/rockchip/rk_pinctrl.c

1447

reg = sc->conf->get_pd_offset(sc, bank);

sys/arm64/rockchip/rk_pinctrl.c

1448

reg += bank * 0x10 + ((pin / 8) * 0x4);

sys/arm64/rockchip/rk_pinctrl.c

1452

SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16));

sys/arm64/rockchip/rk_pinctrl.c

76

uint32_t reg;

sys/arm64/rockchip/rk_typec_phy.c

134

#define RK_TYPEC_PHY_READ(sc, reg) bus_read_4(sc->res, (reg))

sys/arm64/rockchip/rk_typec_phy.c

135

#define RK_TYPEC_PHY_WRITE(sc, reg, val) bus_write_4(sc->res, (reg), (val))

sys/arm64/rockchip/rk_typec_phy.c

161

uint32_t reg;

sys/arm64/rockchip/rk_typec_phy.c

164

reg = SYSCON_READ_4(sc->grf, GRF_USB3PHY_CON0(sc->phy_ctrl_id));

sys/arm64/rockchip/rk_typec_phy.c

166

reg |= USB3PHY_CON0_USB2_ONLY;

sys/arm64/rockchip/rk_typec_phy.c

168

reg &= ~USB3PHY_CON0_USB2_ONLY;

sys/arm64/rockchip/rk_typec_phy.c

170

reg |= (USB3PHY_CON0_USB2_ONLY) << 16;

sys/arm64/rockchip/rk_typec_phy.c

171

SYSCON_WRITE_4(sc->grf, GRF_USB3PHY_CON0(sc->phy_ctrl_id), reg);

sys/arm64/rockchip/rk_typec_phy.c

174

reg = SYSCON_READ_4(sc->grf, GRF_USB3OTG_CON1(sc->phy_ctrl_id));

sys/arm64/rockchip/rk_typec_phy.c

176

reg |= USB3OTG_CON1_U3_DIS;

sys/arm64/rockchip/rk_typec_phy.c

178

reg &= ~USB3OTG_CON1_U3_DIS;

sys/arm64/rockchip/rk_typec_phy.c

180

reg |= (USB3OTG_CON1_U3_DIS) << 16;

sys/arm64/rockchip/rk_typec_phy.c

181

SYSCON_WRITE_4(sc->grf, GRF_USB3OTG_CON1(sc->phy_ctrl_id), reg);

sys/arm64/rockchip/rk_typec_phy.c

190

uint32_t reg;

sys/arm64/rockchip/rk_typec_phy.c

225

reg = RK_TYPEC_PHY_READ(sc, CMN_DIAG_HSCLK_SEL);

sys/arm64/rockchip/rk_typec_phy.c

226

reg &= ~CMN_DIAG_HSCLK_SEL_PLL_MASK;

sys/arm64/rockchip/rk_typec_phy.c

227

reg |= CMN_DIAG_HSCLK_SEL_PLL_CONFIG;

sys/arm64/rockchip/rk_typec_phy.c

228

RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_HSCLK_SEL, reg);

sys/arm64/rockchip/rk_typec_phy.c

272

reg = RK_TYPEC_PHY_READ(sc, PMA_CMN_CTRL1);

sys/arm64/rockchip/rk_typec_phy.c

273

if (reg & PMA_CMN_CTRL1_READY)

sys/arm64/vmm/io/vgic_v3.c

1012

dist_ctlr_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,

sys/arm64/vmm/io/vgic_v3.c

1041

dist_typer_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,

sys/arm64/vmm/io/vgic_v3.c

1056

dist_iidr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)

sys/arm64/vmm/io/vgic_v3.c

1063

dist_setclrspi_nsr_write(struct hypctx *hypctx, u_int reg, u_int offset,

sys/arm64/vmm/io/vgic_v3.c

1072

reg == GICD_SETSPI_NSR);

sys/arm64/vmm/io/vgic_v3.c

1077

dist_isenabler_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)

sys/arm64/vmm/io/vgic_v3.c

1081

n = (reg - GICD_ISENABLER(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1088

dist_isenabler_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,

sys/arm64/vmm/io/vgic_v3.c

1095

n = (reg - GICD_ISENABLER(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1103

dist_icenabler_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)

sys/arm64/vmm/io/vgic_v3.c

1107

n = (reg - GICD_ICENABLER(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1114

dist_icenabler_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,

sys/arm64/vmm/io/vgic_v3.c

1121

n = (reg - GICD_ISENABLER(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1129

dist_ispendr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)

sys/arm64/vmm/io/vgic_v3.c

1133

n = (reg - GICD_ISPENDR(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1140

dist_ispendr_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,

sys/arm64/vmm/io/vgic_v3.c

1147

n = (reg - GICD_ISPENDR(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1155

dist_icpendr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)

sys/arm64/vmm/io/vgic_v3.c

1159

n = (reg - GICD_ICPENDR(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1166

dist_icpendr_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,

sys/arm64/vmm/io/vgic_v3.c

1173

n = (reg - GICD_ICPENDR(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1182

dist_isactiver_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)

sys/arm64/vmm/io/vgic_v3.c

1186

n = (reg - GICD_ISACTIVER(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1193

dist_isactiver_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,

sys/arm64/vmm/io/vgic_v3.c

1200

n = (reg - GICD_ISACTIVER(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1208

dist_icactiver_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,

sys/arm64/vmm/io/vgic_v3.c

1213

n = (reg - GICD_ICACTIVER(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1220

dist_icactiver_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,

sys/arm64/vmm/io/vgic_v3.c

1227

n = (reg - GICD_ICACTIVER(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1236

dist_ipriorityr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,

sys/arm64/vmm/io/vgic_v3.c

1241

n = (reg - GICD_IPRIORITYR(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1248

dist_ipriorityr_write(struct hypctx *hypctx, u_int reg, u_int offset,

sys/arm64/vmm/io/vgic_v3.c

1253

irq_base = (reg - GICD_IPRIORITYR(0)) + offset;

sys/arm64/vmm/io/vgic_v3.c

1261

dist_icfgr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)

sys/arm64/vmm/io/vgic_v3.c

1265

n = (reg - GICD_ICFGR(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1272

dist_icfgr_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,

sys/arm64/vmm/io/vgic_v3.c

1279

n = (reg - GICD_ICFGR(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1287

dist_irouter_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)

sys/arm64/vmm/io/vgic_v3.c

1291

n = (reg - GICD_IROUTER(0)) / 8;

sys/arm64/vmm/io/vgic_v3.c

1298

dist_irouter_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,

sys/arm64/vmm/io/vgic_v3.c

1303

n = (reg - GICD_IROUTER(0)) / 8;

sys/arm64/vmm/io/vgic_v3.c

1311

u_int reg_list_size, u_int reg, u_int size, uint64_t *rval, void *arg)

sys/arm64/vmm/io/vgic_v3.c

1316

if (reg_list[i].start <= reg && reg_list[i].end >= reg + size) {

sys/arm64/vmm/io/vgic_v3.c

1317

offset = reg & (reg_list[i].size - 1);

sys/arm64/vmm/io/vgic_v3.c

1318

reg -= offset;

sys/arm64/vmm/io/vgic_v3.c

1320

reg_list[i].read(hypctx, reg, rval, NULL);

sys/arm64/vmm/io/vgic_v3.c

1346

u_int reg_list_size, u_int reg, u_int size, uint64_t wval, void *arg)

sys/arm64/vmm/io/vgic_v3.c

1351

if (reg_list[i].start <= reg && reg_list[i].end >= reg + size) {

sys/arm64/vmm/io/vgic_v3.c

1352

offset = reg & (reg_list[i].size - 1);

sys/arm64/vmm/io/vgic_v3.c

1353

reg -= offset;

sys/arm64/vmm/io/vgic_v3.c

1355

reg_list[i].write(hypctx, reg, offset,

sys/arm64/vmm/io/vgic_v3.c

1377

uint64_t reg;

sys/arm64/vmm/io/vgic_v3.c

1388

reg = fault_ipa - vgic->dist_start;

sys/arm64/vmm/io/vgic_v3.c

1393

if ((reg & (size - 1)) != 0) {

sys/arm64/vmm/io/vgic_v3.c

1399

reg, size, rval, NULL))

sys/arm64/vmm/io/vgic_v3.c

1415

uint64_t reg;

sys/arm64/vmm/io/vgic_v3.c

1426

reg = fault_ipa - vgic->dist_start;

sys/arm64/vmm/io/vgic_v3.c

1431

if ((reg & (size - 1)) != 0)

sys/arm64/vmm/io/vgic_v3.c

1435

reg, size, wval, NULL))

sys/arm64/vmm/io/vgic_v3.c

1449

redist_ctlr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)

sys/arm64/vmm/io/vgic_v3.c

1457

redist_iidr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)

sys/arm64/vmm/io/vgic_v3.c

1464

redist_typer_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)

sys/arm64/vmm/io/vgic_v3.c

1501

redist_ienabler0_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,

sys/arm64/vmm/io/vgic_v3.c

1508

redist_isenabler0_write(struct hypctx *hypctx, u_int reg, u_int offset,

sys/arm64/vmm/io/vgic_v3.c

1518

redist_icenabler0_write(struct hypctx *hypctx, u_int reg, u_int offset,

sys/arm64/vmm/io/vgic_v3.c

1528

redist_ipendr0_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,

sys/arm64/vmm/io/vgic_v3.c

1535

redist_ispendr0_write(struct hypctx *hypctx, u_int reg, u_int offset,

sys/arm64/vmm/io/vgic_v3.c

1545

redist_icpendr0_write(struct hypctx *hypctx, u_int reg, u_int offset,

sys/arm64/vmm/io/vgic_v3.c

1555

redist_iactiver0_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,

sys/arm64/vmm/io/vgic_v3.c

1562

redist_isactiver0_write(struct hypctx *hypctx, u_int reg, u_int offset,

sys/arm64/vmm/io/vgic_v3.c

1570

redist_icactiver0_write(struct hypctx *hypctx, u_int reg, u_int offset,

sys/arm64/vmm/io/vgic_v3.c

1578

redist_ipriorityr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,

sys/arm64/vmm/io/vgic_v3.c

1583

n = (reg - GICR_IPRIORITYR(0)) / 4;

sys/arm64/vmm/io/vgic_v3.c

1588

redist_ipriorityr_write(struct hypctx *hypctx, u_int reg, u_int offset,

sys/arm64/vmm/io/vgic_v3.c

1593

irq_base = (reg - GICR_IPRIORITYR(0)) + offset;

sys/arm64/vmm/io/vgic_v3.c

1599

redist_icfgr1_read(struct hypctx *hypctx, u_int reg, uint64_t *rval, void *arg)

sys/arm64/vmm/io/vgic_v3.c

1605

redist_icfgr1_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,

sys/arm64/vmm/io/vgic_v3.c

1620

uint64_t reg;

sys/arm64/vmm/io/vgic_v3.c

1663

reg = (fault_ipa - vgic->redist_start) %

sys/arm64/vmm/io/vgic_v3.c

1670

if ((reg & (size - 1)) != 0) {

sys/arm64/vmm/io/vgic_v3.c

1675

if (reg < GICR_RD_BASE_SIZE) {

sys/arm64/vmm/io/vgic_v3.c

1677

nitems(redist_rd_registers), reg, size, rval, NULL))

sys/arm64/vmm/io/vgic_v3.c

1679

} else if (reg < (GICR_SGI_BASE + GICR_SGI_BASE_SIZE)) {

sys/arm64/vmm/io/vgic_v3.c

1681

nitems(redist_sgi_registers), reg - GICR_SGI_BASE, size,

sys/arm64/vmm/io/vgic_v3.c

1698

uint64_t reg;

sys/arm64/vmm/io/vgic_v3.c

1740

reg = (fault_ipa - vgic->redist_start) %

sys/arm64/vmm/io/vgic_v3.c

1747

if ((reg & (size - 1)) != 0)

sys/arm64/vmm/io/vgic_v3.c

1750

if (reg < GICR_RD_BASE_SIZE) {

sys/arm64/vmm/io/vgic_v3.c

1752

nitems(redist_rd_registers), reg, size, wval, NULL))

sys/arm64/vmm/io/vgic_v3.c

1754

} else if (reg < (GICR_SGI_BASE + GICR_SGI_BASE_SIZE)) {

sys/arm64/vmm/io/vgic_v3.c

1756

nitems(redist_sgi_registers), reg - GICR_SGI_BASE, size,

sys/arm64/vmm/io/vgic_v3.c

2087

uint64_t reg;

sys/arm64/vmm/io/vgic_v3.c

2096

reg = addr - vgic->dist_start;

sys/arm64/vmm/io/vgic_v3.c

2097

if (reg != GICD_SETSPI_NSR)

sys/arm64/vmm/io/vgic_v3.c

638

gic_pidr2_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,

sys/arm64/vmm/io/vgic_v3.c

646

gic_zero_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,

sys/arm64/vmm/io/vgic_v3.c

653

gic_ignore_write(struct hypctx *hypctx, u_int reg, u_int offset, u_int size,

sys/arm64/vmm/io/vgic_v3.c

994

dist_ctlr_read(struct hypctx *hypctx, u_int reg, uint64_t *rval,

sys/arm64/vmm/vmm.c

155

#define _FETCH_KERN_REG(reg, field) do { \

sys/arm64/vmm/vmm.c

157

get_kernel_reg_iss_masked(reg ## _ISS, &regs->field, \

sys/arm64/vmm/vmm.c

795

vm_get_register(struct vcpu *vcpu, int reg, uint64_t *retval)

sys/arm64/vmm/vmm.c

797

if (reg < 0 || reg >= VM_REG_LAST)

sys/arm64/vmm/vmm.c

800

return (vmmops_getreg(vcpu->cookie, reg, retval));

sys/arm64/vmm/vmm.c

804

vm_set_register(struct vcpu *vcpu, int reg, uint64_t val)

sys/arm64/vmm/vmm.c

808

if (reg < 0 || reg >= VM_REG_LAST)

sys/arm64/vmm/vmm.c

810

error = vmmops_setreg(vcpu->cookie, reg, val);

sys/arm64/vmm/vmm.c

811

if (error || reg != VM_REG_GUEST_PC)

sys/arm64/vmm/vmm_arm64.c

1246

hypctx_regptr(struct hypctx *hypctx, int reg)

sys/arm64/vmm/vmm_arm64.c

1248

switch (reg) {

sys/arm64/vmm/vmm_arm64.c

1250

return (&hypctx->tf.tf_x[reg]);

sys/arm64/vmm/vmm_arm64.c

1278

vmmops_getreg(void *vcpui, int reg, uint64_t *retval)

sys/arm64/vmm/vmm_arm64.c

1289

regp = hypctx_regptr(hypctx, reg);

sys/arm64/vmm/vmm_arm64.c

1298

vmmops_setreg(void *vcpui, int reg, uint64_t val)

sys/arm64/vmm/vmm_arm64.c

1309

regp = hypctx_regptr(hypctx, reg);

sys/arm64/vmm/vmm_arm64.c

637

vie->reg = reg_num;

sys/arm64/vmm/vmm_arm64.c

662

vre->reg = reg_num;

sys/arm64/vmm/vmm_handlers.c

38

vmm_nvhe_read_reg(uint64_t reg)

sys/arm64/vmm/vmm_handlers.c

40

return (vmm_call_hyp(HYP_READ_REGISTER, reg));

sys/arm64/vmm/vmm_handlers.c

43

DEFINE_IFUNC(, uint64_t, vmm_read_reg, (uint64_t reg))

sys/arm64/vmm/vmm_hyp.c

683

VMM_HYP_FUNC(read_reg)(uint64_t reg)

sys/arm64/vmm/vmm_hyp.c

685

switch (reg) {

sys/arm64/vmm/vmm_instruction_emul.c

66

error = vm_set_register(vcpu, vie->reg, val);

sys/arm64/vmm/vmm_instruction_emul.c

68

error = vm_get_register(vcpu, vie->reg, &val);

sys/arm64/vmm/vmm_instruction_emul.c

92

error = vm_set_register(vcpu, vre->reg, val);

sys/arm64/vmm/vmm_instruction_emul.c

94

error = vm_get_register(vcpu, vre->reg, &val);

sys/arm64/vmm/vmm_nvhe.c

36

#define EL1_REG(reg) MRS_REG_ALT_NAME(reg ## _EL1)

sys/arm64/vmm/vmm_nvhe.c

37

#define EL0_REG(reg) MRS_REG_ALT_NAME(reg ## _EL0)

sys/arm64/vmm/vmm_reset.c

47

#define set_arch_unknown(reg) (memset(&(reg), ARCH_UNKNOWN, sizeof(reg)))

sys/arm64/vmm/vmm_vhe.c

36

#define EL1_REG(reg) MRS_REG_ALT_NAME(reg ## _EL12)

sys/arm64/vmm/vmm_vhe.c

37

#define EL0_REG(reg) MRS_REG_ALT_NAME(reg ## _EL02)

sys/cam/ata/ata_all.c

705

ata_pm_read_cmd(struct ccb_ataio *ataio, int reg, int port)

sys/cam/ata/ata_all.c

710

ataio->cmd.features = reg;

sys/cam/ata/ata_all.c

715

ata_pm_write_cmd(struct ccb_ataio *ataio, int reg, int port, uint32_t val)

sys/cam/ata/ata_all.c

720

ataio->cmd.features = reg;

sys/cam/ata/ata_all.h

128

void ata_pm_read_cmd(struct ccb_ataio *ataio, int reg, int port);

sys/cam/ata/ata_all.h

129

void ata_pm_write_cmd(struct ccb_ataio *ataio, int reg, int port, uint32_t val);

sys/cddl/dev/dtrace/aarch64/dtrace_isa.c

317

dtrace_getreg(struct trapframe *frame, uint_t reg)

sys/cddl/dev/dtrace/aarch64/dtrace_isa.c

319

switch (reg) {

sys/cddl/dev/dtrace/aarch64/dtrace_isa.c

321

return (frame->tf_x[reg]);

sys/cddl/dev/dtrace/aarch64/dtrace_subr.c

240

dtrace_load64(uint64_t *addr, struct trapframe *frame, u_int reg)

sys/cddl/dev/dtrace/aarch64/dtrace_subr.c

243

KASSERT(reg <= 31, ("dtrace_load64: Invalid register %u", reg));

sys/cddl/dev/dtrace/aarch64/dtrace_subr.c

244

if (reg < nitems(frame->tf_x))

sys/cddl/dev/dtrace/aarch64/dtrace_subr.c

245

frame->tf_x[reg] = *addr;

sys/cddl/dev/dtrace/aarch64/dtrace_subr.c

246

else if (reg == 30) /* lr */

sys/cddl/dev/dtrace/aarch64/dtrace_subr.c

252

dtrace_store64(uint64_t *addr, struct trapframe *frame, u_int reg)

sys/cddl/dev/dtrace/aarch64/dtrace_subr.c

255

KASSERT(reg <= 31, ("dtrace_store64: Invalid register %u", reg));

sys/cddl/dev/dtrace/aarch64/dtrace_subr.c

256

if (reg < nitems(frame->tf_x))

sys/cddl/dev/dtrace/aarch64/dtrace_subr.c

257

*addr = frame->tf_x[reg];

sys/cddl/dev/dtrace/aarch64/dtrace_subr.c

258

else if (reg == 30) /* lr */

sys/cddl/dev/dtrace/aarch64/dtrace_subr.c

260

else if (reg == 31) /* xzr */

sys/cddl/dev/dtrace/amd64/dtrace_isa.c

474

dtrace_getreg(struct trapframe *frame, uint_t reg)

sys/cddl/dev/dtrace/amd64/dtrace_isa.c

499

if (reg <= GS) {

sys/cddl/dev/dtrace/amd64/dtrace_isa.c

500

if (reg >= sizeof (regmap) / sizeof (int)) {

sys/cddl/dev/dtrace/amd64/dtrace_isa.c

505

reg = regmap[reg];

sys/cddl/dev/dtrace/amd64/dtrace_isa.c

508

reg -= GS + 1;

sys/cddl/dev/dtrace/amd64/dtrace_isa.c

511

switch (reg) {

sys/cddl/dev/dtrace/arm/dtrace_isa.c

159

dtrace_getreg(struct trapframe *frame, uint_t reg)

sys/cddl/dev/dtrace/arm/dtrace_subr.c

225

int data, invop, reg, update_sp;

sys/cddl/dev/dtrace/arm/dtrace_subr.c

252

for (reg = 12; reg >= 0; reg--) {

sys/cddl/dev/dtrace/arm/dtrace_subr.c

253

if (data & (1 << reg)) {

sys/cddl/dev/dtrace/arm/dtrace_subr.c

255

*sp = r0[reg];

sys/cddl/dev/dtrace/arm/dtrace_subr.c

269

for (reg = 0; reg <= 12; reg++) {

sys/cddl/dev/dtrace/arm/dtrace_subr.c

270

if (data & (1 << reg)) {

sys/cddl/dev/dtrace/arm/dtrace_subr.c

271

r0[reg] = *sp;

sys/cddl/dev/dtrace/i386/dtrace_isa.c

500

dtrace_getreg(struct trapframe *frame, uint_t reg)

sys/cddl/dev/dtrace/i386/dtrace_isa.c

525

if (reg > SS) {

sys/cddl/dev/dtrace/i386/dtrace_isa.c

530

if (reg >= sizeof (regmap) / sizeof (int)) {

sys/cddl/dev/dtrace/i386/dtrace_isa.c

535

reg = regmap[reg];

sys/cddl/dev/dtrace/i386/dtrace_isa.c

537

switch(reg) {

sys/cddl/dev/dtrace/powerpc/dtrace_isa.c

459

struct reg *rp = (struct reg *)((uintptr_t)fp[0] + 48);

sys/cddl/dev/dtrace/powerpc/dtrace_isa.c

461

struct reg *rp = (struct reg *)((uintptr_t)fp[0] + 8);

sys/cddl/dev/dtrace/powerpc/dtrace_isa.c

533

dtrace_getreg(struct trapframe *frame, uint_t reg)

sys/cddl/dev/dtrace/powerpc/dtrace_isa.c

535

if (reg < 32)

sys/cddl/dev/dtrace/powerpc/dtrace_isa.c

536

return (frame->fixreg[reg]);

sys/cddl/dev/dtrace/powerpc/dtrace_isa.c

538

switch (reg) {

sys/cddl/dev/dtrace/riscv/dtrace_isa.c

319

dtrace_getreg(struct trapframe *frame, uint_t reg)

sys/cddl/dev/dtrace/riscv/dtrace_isa.c

321

switch (reg) {

sys/cddl/dev/dtrace/riscv/dtrace_isa.c

333

return (frame->tf_t[reg - REG_T0]);

sys/cddl/dev/dtrace/riscv/dtrace_isa.c

335

return (frame->tf_s[reg - REG_S0]);

sys/cddl/dev/dtrace/riscv/dtrace_isa.c

337

return (frame->tf_a[reg - REG_A0]);

sys/cddl/dev/dtrace/riscv/dtrace_isa.c

339

return (frame->tf_s[reg - REG_S2 + 2]);

sys/cddl/dev/dtrace/riscv/dtrace_isa.c

341

return (frame->tf_t[reg - REG_T3 + 3]);

sys/cddl/dev/dtrace/x86/dis_tables.c

3032

dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m)

sys/cddl/dev/dtrace/x86/dis_tables.c

3037

dtrace_get_SIB(x, mode, reg, r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

3047

dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m)

sys/cddl/dev/dtrace/x86/dis_tables.c

3049

if (reg != NULL && r_m == NULL) {

sys/cddl/dev/dtrace/x86/dis_tables.c

3051

*reg += 8;

sys/cddl/dev/dtrace/x86/dis_tables.c

3053

if (reg != NULL && (REX_R & rex_prefix) != 0)

sys/cddl/dev/dtrace/x86/dis_tables.c

3054

*reg += 8;

sys/cddl/dev/dtrace/x86/dis_tables.c

3066

dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m)

sys/cddl/dev/dtrace/x86/dis_tables.c

3068

if (reg != NULL && r_m == NULL) {

sys/cddl/dev/dtrace/x86/dis_tables.c

3070

*reg += 8;

sys/cddl/dev/dtrace/x86/dis_tables.c

3072

if (reg != NULL && ((VEX_R & vex_byte1) == 0))

sys/cddl/dev/dtrace/x86/dis_tables.c

3073

*reg += 8;

sys/cddl/dev/dtrace/x86/dis_tables.c

3128

dtrace_evex_adjust_reg(uint_t evex_byte1, uint_t *reg)

sys/cddl/dev/dtrace/x86/dis_tables.c

3130

if (reg != NULL) {

sys/cddl/dev/dtrace/x86/dis_tables.c

3132

*reg += 8;

sys/cddl/dev/dtrace/x86/dis_tables.c

3135

*reg += 16;

sys/cddl/dev/dtrace/x86/dis_tables.c

3564

#define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \

sys/cddl/dev/dtrace/x86/dis_tables.c

3565

dtrace_get_modrm(x, &mode, &reg, &r_m); \

sys/cddl/dev/dtrace/x86/dis_tables.c

3566

dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m); \

sys/cddl/dev/dtrace/x86/dis_tables.c

3568

dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \

sys/cddl/dev/dtrace/x86/dis_tables.c

3577

#define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \

sys/cddl/dev/dtrace/x86/dis_tables.c

3578

dtrace_get_modrm(x, &mode, &reg, &r_m); \

sys/cddl/dev/dtrace/x86/dis_tables.c

3579

dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m); \

sys/cddl/dev/dtrace/x86/dis_tables.c

3581

dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \

sys/cddl/dev/dtrace/x86/dis_tables.c

3590

#define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \

sys/cddl/dev/dtrace/x86/dis_tables.c

3591

dtrace_get_modrm(x, &mode, &reg, &r_m); \

sys/cddl/dev/dtrace/x86/dis_tables.c

3592

dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m); \

sys/cddl/dev/dtrace/x86/dis_tables.c

3594

dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \

sys/cddl/dev/dtrace/x86/dis_tables.c

3601

#define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \

sys/cddl/dev/dtrace/x86/dis_tables.c

3602

dtrace_get_modrm(x, &mode, &reg, &r_m); \

sys/cddl/dev/dtrace/x86/dis_tables.c

3603

dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m); \

sys/cddl/dev/dtrace/x86/dis_tables.c

3605

dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \

sys/cddl/dev/dtrace/x86/dis_tables.c

3613

#define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \

sys/cddl/dev/dtrace/x86/dis_tables.c

3614

dtrace_get_modrm(x, &mode, &reg, &r_m); \

sys/cddl/dev/dtrace/x86/dis_tables.c

3615

dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m); \

sys/cddl/dev/dtrace/x86/dis_tables.c

3648

uint_t reg; /* reg value from ModRM byte */

sys/cddl/dev/dtrace/x86/dis_tables.c

3825

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

3832

opcode3 = (((mode << 3) | reg)>>1) & 0x0F;

sys/cddl/dev/dtrace/x86/dis_tables.c

3833

opcode4 = ((reg << 3) | r_m) & 0x0F;

sys/cddl/dev/dtrace/x86/dis_tables.c

3862

reg = (b >> 3) & 0x7;

sys/cddl/dev/dtrace/x86/dis_tables.c

4305

reg = opcode3;

sys/cddl/dev/dtrace/x86/dis_tables.c

4441

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

4461

} else if (reg == 4 || reg == 5) {

sys/cddl/dev/dtrace/x86/dis_tables.c

4465

dp = (instable_t *)&dis_op0FC7[reg];

sys/cddl/dev/dtrace/x86/dis_tables.c

4651

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

4652

dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

4654

dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

4671

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

4672

dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

4673

dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

4684

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

4685

dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

4686

dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

4698

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

4699

dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

4705

dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

4709

dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

4720

THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND,

sys/cddl/dev/dtrace/x86/dis_tables.c

4728

STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

4738

STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

4744

STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

4755

MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

4760

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

4764

MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

4770

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

4771

dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

4773

dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

4782

STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

4800

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

4811

reg = REGNO(opcode2);

sys/cddl/dev/dtrace/x86/dis_tables.c

4812

dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);

sys/cddl/dev/dtrace/x86/dis_tables.c

4814

r_m = reg;

sys/cddl/dev/dtrace/x86/dis_tables.c

4829

reg = REGNO(opcode7);

sys/cddl/dev/dtrace/x86/dis_tables.c

4830

dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);

sys/cddl/dev/dtrace/x86/dis_tables.c

4831

dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

4859

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

4862

dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit);

sys/cddl/dev/dtrace/x86/dis_tables.c

4905

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5085

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5118

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5119

dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5120

dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit);

sys/cddl/dev/dtrace/x86/dis_tables.c

5131

reg = REGNO(opcode5);

sys/cddl/dev/dtrace/x86/dis_tables.c

5133

reg = REGNO(opcode2);

sys/cddl/dev/dtrace/x86/dis_tables.c

5134

dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);

sys/cddl/dev/dtrace/x86/dis_tables.c

5135

dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

5145

reg = REGNO(opcode2);

sys/cddl/dev/dtrace/x86/dis_tables.c

5146

dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);

sys/cddl/dev/dtrace/x86/dis_tables.c

5147

dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

5157

reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3;

sys/cddl/dev/dtrace/x86/dis_tables.c

5158

dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

5168

reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7;

sys/cddl/dev/dtrace/x86/dis_tables.c

5169

dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

5177

STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

5185

STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

5196

MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

5205

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5209

dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5211

dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

5222

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5226

THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1,

sys/cddl/dev/dtrace/x86/dis_tables.c

5232

THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND,

sys/cddl/dev/dtrace/x86/dis_tables.c

5246

THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

5258

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5262

MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

5272

STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

5299

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5308

MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

5316

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5325

MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

5331

MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

5336

MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

5344

MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

5352

MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

5359

MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

5365

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5368

dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5370

dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

5380

THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1,

sys/cddl/dev/dtrace/x86/dis_tables.c

5451

FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND,

sys/cddl/dev/dtrace/x86/dis_tables.c

5457

ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

5700

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5718

dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5735

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5759

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5773

if (reg == 5) {

sys/cddl/dev/dtrace/x86/dis_tables.c

5775

} else if (reg == 6) {

sys/cddl/dev/dtrace/x86/dis_tables.c

5789

dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5823

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5825

if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3))

sys/cddl/dev/dtrace/x86/dis_tables.c

5828

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5835

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5836

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5867

dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);

sys/cddl/dev/dtrace/x86/dis_tables.c

5898

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5899

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5901

dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);

sys/cddl/dev/dtrace/x86/dis_tables.c

5929

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5930

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5932

dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2);

sys/cddl/dev/dtrace/x86/dis_tables.c

5946

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5947

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5961

dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

5968

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5969

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

5970

dtrace_get_operand(x, REG_ONLY, reg, wbit, 3);

sys/cddl/dev/dtrace/x86/dis_tables.c

6017

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6018

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6027

dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

6042

dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

6050

dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

6053

dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

6063

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6064

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6066

dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);

sys/cddl/dev/dtrace/x86/dis_tables.c

6077

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6079

(void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg],

sys/cddl/dev/dtrace/x86/dis_tables.c

6082

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6102

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6103

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6104

dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit);

sys/cddl/dev/dtrace/x86/dis_tables.c

6115

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6116

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6118

dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

6124

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6125

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6126

dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

6137

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6138

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6139

dtrace_get_operand(x, mode, reg, wbit, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

6147

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6148

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6149

dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

6160

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6161

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6164

dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

6173

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6174

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6176

dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

6183

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6184

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6196

dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

6203

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6204

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6214

dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

6223

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6224

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6227

dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

6237

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6238

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6241

dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

6248

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6249

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6253

dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

6261

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6262

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6266

dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

6273

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6274

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6275

dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);

sys/cddl/dev/dtrace/x86/dis_tables.c

6297

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6298

dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6300

switch (reg) {

sys/cddl/dev/dtrace/x86/dis_tables.c

6332

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6334

dtrace_evex_adjust_reg(evex_byte1, &reg);

sys/cddl/dev/dtrace/x86/dis_tables.c

6337

dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);

sys/cddl/dev/dtrace/x86/dis_tables.c

6346

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6348

dtrace_evex_adjust_reg(evex_byte1, &reg);

sys/cddl/dev/dtrace/x86/dis_tables.c

6354

dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);

sys/cddl/dev/dtrace/x86/dis_tables.c

6360

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6362

dtrace_evex_adjust_reg(evex_byte1, &reg);

sys/cddl/dev/dtrace/x86/dis_tables.c

6365

dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);

sys/cddl/dev/dtrace/x86/dis_tables.c

6381

dtrace_get_modrm(x, &mode, &reg, &r_m);

sys/cddl/dev/dtrace/x86/dis_tables.c

6383

dtrace_evex_adjust_reg(evex_byte1, &reg);

sys/cddl/dev/dtrace/x86/dis_tables.c

6386

dtrace_get_operand(x, REG_ONLY, reg, wbit, 3);

sys/cddl/dev/kinst/aarch64/kinst_isa.c

105

reg = instr & 0x1f;

sys/cddl/dev/kinst/aarch64/kinst_isa.c

109

if (cond == 1 && frame->tf_x[reg] != 0)

sys/cddl/dev/kinst/aarch64/kinst_isa.c

112

else if (cond == 0 && frame->tf_x[reg] == 0)

sys/cddl/dev/kinst/aarch64/kinst_isa.c

120

reg = instr & 0x1f;

sys/cddl/dev/kinst/aarch64/kinst_isa.c

126

if (cond == 1 && (frame->tf_x[reg] & (1 << bitpos)) != 0)

sys/cddl/dev/kinst/aarch64/kinst_isa.c

129

else if (cond == 0 && (frame->tf_x[reg] & (1 << bitpos)) == 0)

sys/cddl/dev/kinst/aarch64/kinst_isa.c

26

uint8_t cond, reg, bitpos;

sys/cddl/dev/kinst/aarch64/kinst_isa.c

31

reg = instr & 0x1f;

sys/cddl/dev/kinst/aarch64/kinst_isa.c

38

frame->tf_x[reg] = frame->tf_elr + imm;

sys/cddl/dev/kinst/aarch64/kinst_isa.c

44

frame->tf_x[reg] = (frame->tf_elr & ~0xfff) + imm;

sys/cddl/dev/kinst/amd64/kinst_isa.c

228

register_t reg;

sys/cddl/dev/kinst/amd64/kinst_isa.c

231

reg = intr_disable();

sys/cddl/dev/kinst/amd64/kinst_isa.c

235

intr_restore(reg);

sys/cddl/dev/kinst/amd64/kinst_isa.c

59

kinst_regoff(int reg)

sys/cddl/dev/kinst/amd64/kinst_isa.c

61

#define _MATCH_REG(i, reg) \

sys/cddl/dev/kinst/amd64/kinst_isa.c

63

return (offsetof(struct trapframe, tf_ ## reg) / \

sys/cddl/dev/kinst/amd64/kinst_isa.c

65

switch (reg) {

sys/cddl/dev/kinst/amd64/kinst_isa.c

84

panic("%s: unhandled register index %d", __func__, reg);

sys/cddl/dev/kinst/amd64/kinst_isa.c

91

kinst_regval(struct trapframe *frame, int reg)

sys/cddl/dev/kinst/amd64/kinst_isa.c

93

if (reg == -1)

sys/cddl/dev/kinst/amd64/kinst_isa.c

95

return (((register_t *)frame)[kinst_regoff(reg)]);

sys/cddl/dev/kinst/riscv/kinst_isa.c

19

#define _MATCH_REG(reg) \

sys/cddl/dev/kinst/riscv/kinst_isa.c

20

(offsetof(struct trapframe, tf_ ## reg) / sizeof(register_t))

sys/compat/freebsd32/freebsd32_misc.c

1023

struct reg32 reg;

sys/compat/freebsd32/freebsd32_misc.c

1072

bzero(&r.reg, sizeof(r.reg));

sys/compat/freebsd32/freebsd32_misc.c

1081

error = copyin(uap->addr, &r.reg, sizeof(r.reg));

sys/compat/freebsd32/freebsd32_misc.c

1193

error = copyout(&r.reg, uap->addr, sizeof(r.reg));

sys/compat/linsysfs/linsysfs.c

163

uint32_t reg;

sys/compat/linsysfs/linsysfs.c

167

reg = pci_get_vendor(dev);

sys/compat/linsysfs/linsysfs.c

168

config[0] = reg;

sys/compat/linsysfs/linsysfs.c

169

config[1] = reg >> 8;

sys/compat/linsysfs/linsysfs.c

170

reg = pci_get_device(dev);

sys/compat/linsysfs/linsysfs.c

171

config[2] = reg;

sys/compat/linsysfs/linsysfs.c

172

config[3] = reg >> 8;

sys/compat/linsysfs/linsysfs.c

173

reg = pci_get_revid(dev);

sys/compat/linsysfs/linsysfs.c

174

config[8] = reg;

sys/compat/linsysfs/linsysfs.c

175

reg = pci_get_subvendor(dev);

sys/compat/linsysfs/linsysfs.c

176

config[44] = reg;

sys/compat/linsysfs/linsysfs.c

177

config[45] = reg >> 8;

sys/compat/linsysfs/linsysfs.c

178

reg = pci_get_subdevice(dev);

sys/compat/linsysfs/linsysfs.c

179

config[46] = reg;

sys/compat/linsysfs/linsysfs.c

180

config[47] = reg >> 8;

sys/compat/linux/linux_elf.c

223

struct reg pr_reg;

sys/compat/linux/linux_ptrace.c

265

struct reg b_reg;

sys/compat/linux/linux_ptrace.c

285

struct reg b_reg;

sys/compat/linux/linux_ptrace.c

300

struct reg b_reg;

sys/compat/linux/linux_ptrace.c

374

struct reg b_reg;

sys/compat/linuxkpi/common/include/linux/pci.h

641

int reg;

sys/compat/linuxkpi/common/include/linux/pci.h

643

if (pci_find_cap(pdev->dev.bsddev, capid, &reg))

sys/compat/linuxkpi/common/include/linux/pci.h

645

return (reg);

sys/compat/linuxkpi/common/include/linux/pci.h

656

int reg;

sys/compat/linuxkpi/common/include/linux/pci.h

658

if (pci_find_extcap(pdev->dev.bsddev, capid, &reg))

sys/compat/linuxkpi/common/include/linux/pci.h

660

return (reg);

sys/compat/linuxkpi/common/src/linux_page.c

685

lkpi_arch_phys_wc_del(int reg)

sys/compat/linuxkpi/common/src/linux_page.c

692

if (reg < __MTRR_ID_BASE)

sys/compat/linuxkpi/common/src/linux_page.c

695

mrdesc = idr_find(&mtrr_idr, reg - __MTRR_ID_BASE);

sys/compat/linuxkpi/common/src/linux_page.c

697

idr_remove(&mtrr_idr, reg - __MTRR_ID_BASE);

sys/crypto/armv8/armv8_crypto.c

114

uint64_t reg;

sys/crypto/armv8/armv8_crypto.c

118

reg = READ_SPECIALREG(id_aa64isar0_el1);

sys/crypto/armv8/armv8_crypto.c

120

if (ID_AA64ISAR0_AES_VAL(reg) == ID_AA64ISAR0_AES_PMULL)

sys/crypto/armv8/armv8_crypto.c

84

uint64_t reg;

sys/crypto/armv8/armv8_crypto.c

87

reg = READ_SPECIALREG(id_aa64isar0_el1);

sys/crypto/armv8/armv8_crypto.c

89

switch (ID_AA64ISAR0_AES_VAL(reg)) {

sys/dev/aac/aacvar.h

273

#define AAC_MEM0_SETREG4(sc, reg, val) bus_space_write_4(sc->aac_btag0, \

sys/dev/aac/aacvar.h

274

sc->aac_bhandle0, reg, val)

sys/dev/aac/aacvar.h

275

#define AAC_MEM0_GETREG4(sc, reg) bus_space_read_4(sc->aac_btag0, \

sys/dev/aac/aacvar.h

276

sc->aac_bhandle0, reg)

sys/dev/aac/aacvar.h

277

#define AAC_MEM0_SETREG2(sc, reg, val) bus_space_write_2(sc->aac_btag0, \

sys/dev/aac/aacvar.h

278

sc->aac_bhandle0, reg, val)

sys/dev/aac/aacvar.h

279

#define AAC_MEM0_GETREG2(sc, reg) bus_space_read_2(sc->aac_btag0, \

sys/dev/aac/aacvar.h

280

sc->aac_bhandle0, reg)

sys/dev/aac/aacvar.h

281

#define AAC_MEM0_SETREG1(sc, reg, val) bus_space_write_1(sc->aac_btag0, \

sys/dev/aac/aacvar.h

282

sc->aac_bhandle0, reg, val)

sys/dev/aac/aacvar.h

283

#define AAC_MEM0_GETREG1(sc, reg) bus_space_read_1(sc->aac_btag0, \

sys/dev/aac/aacvar.h

284

sc->aac_bhandle0, reg)

sys/dev/aac/aacvar.h

286

#define AAC_MEM1_SETREG4(sc, reg, val) bus_space_write_4(sc->aac_btag1, \

sys/dev/aac/aacvar.h

287

sc->aac_bhandle1, reg, val)

sys/dev/aac/aacvar.h

288

#define AAC_MEM1_GETREG4(sc, reg) bus_space_read_4(sc->aac_btag1, \

sys/dev/aac/aacvar.h

289

sc->aac_bhandle1, reg)

sys/dev/aac/aacvar.h

290

#define AAC_MEM1_SETREG2(sc, reg, val) bus_space_write_2(sc->aac_btag1, \

sys/dev/aac/aacvar.h

291

sc->aac_bhandle1, reg, val)

sys/dev/aac/aacvar.h

292

#define AAC_MEM1_GETREG2(sc, reg) bus_space_read_2(sc->aac_btag1, \

sys/dev/aac/aacvar.h

293

sc->aac_bhandle1, reg)

sys/dev/aac/aacvar.h

294

#define AAC_MEM1_SETREG1(sc, reg, val) bus_space_write_1(sc->aac_btag1, \

sys/dev/aac/aacvar.h

295

sc->aac_bhandle1, reg, val)

sys/dev/aac/aacvar.h

296

#define AAC_MEM1_GETREG1(sc, reg) bus_space_read_1(sc->aac_btag1, \

sys/dev/aac/aacvar.h

297

sc->aac_bhandle1, reg)

sys/dev/aacraid/aacraid_var.h

281

#define AAC_MEM0_SETREG4(sc, reg, val) bus_space_write_4(sc->aac_btag0, \

sys/dev/aacraid/aacraid_var.h

282

sc->aac_bhandle0, reg, val)

sys/dev/aacraid/aacraid_var.h

283

#define AAC_MEM0_GETREG4(sc, reg) bus_space_read_4(sc->aac_btag0, \

sys/dev/aacraid/aacraid_var.h

284

sc->aac_bhandle0, reg)

sys/dev/aacraid/aacraid_var.h

285

#define AAC_MEM0_SETREG2(sc, reg, val) bus_space_write_2(sc->aac_btag0, \

sys/dev/aacraid/aacraid_var.h

286

sc->aac_bhandle0, reg, val)

sys/dev/aacraid/aacraid_var.h

287

#define AAC_MEM0_GETREG2(sc, reg) bus_space_read_2(sc->aac_btag0, \

sys/dev/aacraid/aacraid_var.h

288

sc->aac_bhandle0, reg)

sys/dev/aacraid/aacraid_var.h

289

#define AAC_MEM0_SETREG1(sc, reg, val) bus_space_write_1(sc->aac_btag0, \

sys/dev/aacraid/aacraid_var.h

290

sc->aac_bhandle0, reg, val)

sys/dev/aacraid/aacraid_var.h

291

#define AAC_MEM0_GETREG1(sc, reg) bus_space_read_1(sc->aac_btag0, \

sys/dev/aacraid/aacraid_var.h

292

sc->aac_bhandle0, reg)

sys/dev/aacraid/aacraid_var.h

294

#define AAC_MEM1_SETREG4(sc, reg, val) bus_space_write_4(sc->aac_btag1, \

sys/dev/aacraid/aacraid_var.h

295

sc->aac_bhandle1, reg, val)

sys/dev/aacraid/aacraid_var.h

296

#define AAC_MEM1_GETREG4(sc, reg) bus_space_read_4(sc->aac_btag1, \

sys/dev/aacraid/aacraid_var.h

297

sc->aac_bhandle1, reg)

sys/dev/aacraid/aacraid_var.h

298

#define AAC_MEM1_SETREG2(sc, reg, val) bus_space_write_2(sc->aac_btag1, \

sys/dev/aacraid/aacraid_var.h

299

sc->aac_bhandle1, reg, val)

sys/dev/aacraid/aacraid_var.h

300

#define AAC_MEM1_GETREG2(sc, reg) bus_space_read_2(sc->aac_btag1, \

sys/dev/aacraid/aacraid_var.h

301

sc->aac_bhandle1, reg)

sys/dev/aacraid/aacraid_var.h

302

#define AAC_MEM1_SETREG1(sc, reg, val) bus_space_write_1(sc->aac_btag1, \

sys/dev/aacraid/aacraid_var.h

303

sc->aac_bhandle1, reg, val)

sys/dev/aacraid/aacraid_var.h

304

#define AAC_MEM1_GETREG1(sc, reg) bus_space_read_1(sc->aac_btag1, \

sys/dev/aacraid/aacraid_var.h

305

sc->aac_bhandle1, reg)

sys/dev/acpi_support/acpi_panasonic.c

341

int reg;

sys/dev/acpi_support/acpi_panasonic.c

344

reg = (power_profile_get_state() == POWER_PROFILE_PERFORMANCE) ?

sys/dev/acpi_support/acpi_panasonic.c

352

*val = acpi_panasonic_sinf(h, reg);

sys/dev/acpi_support/acpi_panasonic.c

362

int reg;

sys/dev/acpi_support/acpi_panasonic.c

365

reg = (power_profile_get_state() == POWER_PROFILE_PERFORMANCE) ?

sys/dev/acpi_support/acpi_panasonic.c

373

*val = acpi_panasonic_sinf(h, reg);

sys/dev/acpi_support/acpi_panasonic.c

383

int reg;

sys/dev/acpi_support/acpi_panasonic.c

386

reg = (power_profile_get_state() == POWER_PROFILE_PERFORMANCE) ?

sys/dev/acpi_support/acpi_panasonic.c

396

acpi_panasonic_sset(h, reg, *val);

sys/dev/acpi_support/acpi_panasonic.c

399

*val = acpi_panasonic_sinf(h, reg);

sys/dev/acpica/acpi_cpu.c

109

#define CPU_GET_REG(reg, width) \

sys/dev/acpica/acpi_cpu.c

110

(bus_space_read_ ## width(rman_get_bustag((reg)), \

sys/dev/acpica/acpi_cpu.c

111

rman_get_bushandle((reg)), 0))

sys/dev/acpica/acpi_cpu.c

112

#define CPU_SET_REG(reg, width, val) \

sys/dev/acpica/acpi_cpu.c

113

(bus_space_write_ ## width(rman_get_bustag((reg)), \

sys/dev/acpica/acpi_cpu.c

114

rman_get_bushandle((reg)), 0, (val)))

sys/dev/acpica/acpi_pcib_acpi.c

539

u_int reg, int bytes)

sys/dev/acpica/acpi_pcib_acpi.c

543

return (pci_cfgregread(sc->ap_segment, bus, slot, func, reg, bytes));

sys/dev/acpica/acpi_pcib_acpi.c

548

u_int reg, uint32_t data, int bytes)

sys/dev/acpica/acpi_pcib_acpi.c

552

pci_cfgregwrite(sc->ap_segment, bus, slot, func, reg, data, bytes);

sys/dev/acpica/acpi_pcib_acpi.c

80

u_int slot, u_int func, u_int reg, int bytes);

sys/dev/acpica/acpi_pcib_acpi.c

82

u_int slot, u_int func, u_int reg, uint32_t data,

sys/dev/acpica/acpi_perf.c

86

#define PX_GET_REG(reg) \

sys/dev/acpica/acpi_perf.c

87

(bus_space_read_4(rman_get_bustag((reg)), \

sys/dev/acpica/acpi_perf.c

88

rman_get_bushandle((reg)), 0))

sys/dev/acpica/acpi_perf.c

89

#define PX_SET_REG(reg, val) \

sys/dev/acpica/acpi_perf.c

90

(bus_space_write_4(rman_get_bustag((reg)), \

sys/dev/acpica/acpi_perf.c

91

rman_get_bushandle((reg)), 0, (val)))

sys/dev/acpica/acpi_throttle.c

65

#define THR_GET_REG(reg) \

sys/dev/acpica/acpi_throttle.c

66

(bus_space_read_4(rman_get_bustag((reg)), \

sys/dev/acpica/acpi_throttle.c

67

rman_get_bushandle((reg)), 0))

sys/dev/acpica/acpi_throttle.c

68

#define THR_SET_REG(reg, val) \

sys/dev/acpica/acpi_throttle.c

69

(bus_space_write_4(rman_get_bustag((reg)), \

sys/dev/acpica/acpi_throttle.c

70

rman_get_bushandle((reg)), 0, (val)))

sys/dev/adb/adb.h

59

u_int adb_send_packet(device_t dev, u_char command, u_char reg, int len,

sys/dev/adb/adb.h

71

size_t adb_read_register(device_t dev, u_char reg, void *data);

sys/dev/adb/adb.h

72

size_t adb_write_register(device_t dev, u_char reg, size_t len, void *data);

sys/dev/adb/adb_bus.c

245

adb_send_packet(device_t dev, u_char command, u_char reg, int len, u_char *data)

sys/dev/adb/adb_bus.c

256

command_byte |= reg;

sys/dev/adb/adb_bus.c

306

uint8_t reg, int len, u_char *data, u_char *reply)

sys/dev/adb/adb_bus.c

317

command_byte |= reg;

sys/dev/adb/adb_bus.c

380

adb_read_register(device_t dev, u_char reg, void *data)

sys/dev/adb/adb_bus.c

390

ADB_COMMAND_TALK, reg, 0, NULL, data);

sys/dev/adb/adb_bus.c

396

adb_write_register(device_t dev, u_char reg, size_t len, void *data)

sys/dev/adb/adb_bus.c

406

ADB_COMMAND_LISTEN, reg, len, (u_char *)data, NULL);

sys/dev/adb/adb_bus.c

409

ADB_COMMAND_TALK, reg, 0, NULL, NULL);

sys/dev/adb/adb_bus.c

49

static int adb_send_raw_packet_sync(device_t dev, uint8_t to, uint8_t command, uint8_t reg, int len, u_char *data, u_char *reply);

sys/dev/adb/adb_buttons.c

110

u_char command, u_char reg, int len, u_char *data)

sys/dev/adb/adb_buttons.c

58

u_char command, u_char reg, int len, u_char *data);

sys/dev/adb/adb_kbd.c

410

u_char command, u_char reg, int len, u_char *data)

sys/dev/adb/adb_kbd.c

419

if (reg != 0 || len != 2)

sys/dev/adb/adb_kbd.c

65

u_char command, u_char reg, int len, u_char *data);

sys/dev/adb/adb_mouse.c

334

u_char reg, int len, u_char *data)

sys/dev/adb/adb_mouse.c

343

if (command != ADB_COMMAND_TALK || reg != 0 || len < 2)

sys/dev/adb/adb_mouse.c

66

u_char command, u_char reg, int len, u_char *data);

sys/dev/ae/if_ae.c

111

static int ae_miibus_readreg(device_t dev, int phy, int reg);

sys/dev/ae/if_ae.c

112

static int ae_miibus_writereg(device_t dev, int phy, int reg, int val);

sys/dev/ae/if_ae.c

146

static int ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word);

sys/dev/ae/if_ae.c

188

#define AE_READ_4(sc, reg) \

sys/dev/ae/if_ae.c

189

bus_read_4((sc)->mem[0], (reg))

sys/dev/ae/if_ae.c

190

#define AE_READ_2(sc, reg) \

sys/dev/ae/if_ae.c

191

bus_read_2((sc)->mem[0], (reg))

sys/dev/ae/if_ae.c

192

#define AE_READ_1(sc, reg) \

sys/dev/ae/if_ae.c

193

bus_read_1((sc)->mem[0], (reg))

sys/dev/ae/if_ae.c

194

#define AE_WRITE_4(sc, reg, val) \

sys/dev/ae/if_ae.c

195

bus_write_4((sc)->mem[0], (reg), (val))

sys/dev/ae/if_ae.c

196

#define AE_WRITE_2(sc, reg, val) \

sys/dev/ae/if_ae.c

197

bus_write_2((sc)->mem[0], (reg), (val))

sys/dev/ae/if_ae.c

198

#define AE_WRITE_1(sc, reg, val) \

sys/dev/ae/if_ae.c

199

bus_write_1((sc)->mem[0], (reg), (val))

sys/dev/ae/if_ae.c

200

#define AE_PHY_READ(sc, reg) \

sys/dev/ae/if_ae.c

201

ae_miibus_readreg(sc->dev, 0, reg)

sys/dev/ae/if_ae.c

202

#define AE_PHY_WRITE(sc, reg, val) \

sys/dev/ae/if_ae.c

203

ae_miibus_writereg(sc->dev, 0, reg, val)

sys/dev/ae/if_ae.c

786

ae_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/ae/if_ae.c

799

val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) |

sys/dev/ae/if_ae.c

814

device_printf(sc->dev, "phy read timeout: %d.\n", reg);

sys/dev/ae/if_ae.c

821

ae_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/ae/if_ae.c

834

aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) |

sys/dev/ae/if_ae.c

850

device_printf(sc->dev, "phy write timeout: %d.\n", reg);

sys/dev/ae/if_ae.c

923

ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word)

sys/dev/ae/if_ae.c

933

val = 0x100 + reg * 4;

sys/dev/ae/if_ae.c

944

reg);

sys/dev/ae/if_ae.c

954

uint32_t word, reg, val;

sys/dev/ae/if_ae.c

985

reg = word >> AE_VPD_REG_SHIFT;

sys/dev/ae/if_ae.c

988

if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG)

sys/dev/ae/if_ae.c

994

if (reg == AE_EADDR0_REG)

sys/dev/age/if_age.c

1304

uint32_t reg, pmcs;

sys/dev/age/if_age.c

1404

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/age/if_age.c

1405

reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC);

sys/dev/age/if_age.c

1406

reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST);

sys/dev/age/if_age.c

1408

reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;

sys/dev/age/if_age.c

1410

reg |= MAC_CFG_RX_ENB;

sys/dev/age/if_age.c

1411

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/age/if_age.c

1795

uint32_t reg;

sys/dev/age/if_age.c

1859

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/age/if_age.c

1860

reg &= ~MAC_CFG_RXCSUM_ENB;

sys/dev/age/if_age.c

1862

reg |= MAC_CFG_RXCSUM_ENB;

sys/dev/age/if_age.c

1863

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/age/if_age.c

1908

uint32_t reg;

sys/dev/age/if_age.c

1913

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/age/if_age.c

1914

reg &= ~MAC_CFG_FULL_DUPLEX;

sys/dev/age/if_age.c

1915

reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC);

sys/dev/age/if_age.c

1916

reg &= ~MAC_CFG_SPEED_MASK;

sys/dev/age/if_age.c

1921

reg |= MAC_CFG_SPEED_10_100;

sys/dev/age/if_age.c

1924

reg |= MAC_CFG_SPEED_1000;

sys/dev/age/if_age.c

1928

reg |= MAC_CFG_FULL_DUPLEX;

sys/dev/age/if_age.c

1931

reg |= MAC_CFG_TX_FC;

sys/dev/age/if_age.c

1933

reg |= MAC_CFG_RX_FC;

sys/dev/age/if_age.c

1937

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/age/if_age.c

1946

uint32_t reg;

sys/dev/age/if_age.c

1979

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/age/if_age.c

1983

reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;

sys/dev/age/if_age.c

1984

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/age/if_age.c

207

age_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/age/if_age.c

216

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/age/if_age.c

225

device_printf(sc->age_dev, "phy read timeout : %d\n", reg);

sys/dev/age/if_age.c

236

age_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/age/if_age.c

246

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/age/if_age.c

2508

uint32_t reg;

sys/dev/age/if_age.c

2515

if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)

sys/dev/age/if_age.c

2521

device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg);

sys/dev/age/if_age.c

2545

uint32_t reg, fsize;

sys/dev/age/if_age.c

255

device_printf(sc->age_dev, "phy write timeout : %d\n", reg);

sys/dev/age/if_age.c

2643

reg = CSR_READ_4(sc, AGE_MASTER_CFG);

sys/dev/age/if_age.c

2644

reg &= ~MASTER_MTIMER_ENB;

sys/dev/age/if_age.c

2646

reg &= ~MASTER_ITIMER_ENB;

sys/dev/age/if_age.c

2648

reg |= MASTER_ITIMER_ENB;

sys/dev/age/if_age.c

2649

CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);

sys/dev/age/if_age.c

2704

reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);

sys/dev/age/if_age.c

2705

rxf_lo = reg / 16;

sys/dev/age/if_age.c

2708

rxf_hi = (reg * 7) / 8;

sys/dev/age/if_age.c

2711

reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);

sys/dev/age/if_age.c

2712

rrd_lo = reg / 8;

sys/dev/age/if_age.c

2713

rrd_hi = (reg * 7) / 8;

sys/dev/age/if_age.c

2799

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/age/if_age.c

2801

reg |= MAC_CFG_RXCSUM_ENB;

sys/dev/age/if_age.c

2808

CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);

sys/dev/age/if_age.c

2826

uint32_t reg;

sys/dev/age/if_age.c

2858

if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)

sys/dev/age/if_age.c

2864

"stopping Rx/Tx MACs timed out(0x%08x)!\n", reg);

sys/dev/age/if_age.c

2900

uint32_t reg;

sys/dev/age/if_age.c

2905

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/age/if_age.c

2906

if ((reg & MAC_CFG_TX_ENB) != 0) {

sys/dev/age/if_age.c

2907

reg &= ~MAC_CFG_TX_ENB;

sys/dev/age/if_age.c

2908

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/age/if_age.c

2911

reg = CSR_READ_4(sc, AGE_DMA_CFG);

sys/dev/age/if_age.c

2912

if ((reg & DMA_CFG_RD_ENB) != 0) {

sys/dev/age/if_age.c

2913

reg &= ~DMA_CFG_RD_ENB;

sys/dev/age/if_age.c

2914

CSR_WRITE_4(sc, AGE_DMA_CFG, reg);

sys/dev/age/if_age.c

2929

uint32_t reg;

sys/dev/age/if_age.c

2934

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/age/if_age.c

2935

if ((reg & MAC_CFG_RX_ENB) != 0) {

sys/dev/age/if_age.c

2936

reg &= ~MAC_CFG_RX_ENB;

sys/dev/age/if_age.c

2937

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/age/if_age.c

2940

reg = CSR_READ_4(sc, AGE_DMA_CFG);

sys/dev/age/if_age.c

2941

if ((reg & DMA_CFG_WR_ENB) != 0) {

sys/dev/age/if_age.c

2942

reg &= ~DMA_CFG_WR_ENB;

sys/dev/age/if_age.c

2943

CSR_WRITE_4(sc, AGE_DMA_CFG, reg);

sys/dev/age/if_age.c

3102

uint32_t reg;

sys/dev/age/if_age.c

3107

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/age/if_age.c

3108

reg &= ~MAC_CFG_VLAN_TAG_STRIP;

sys/dev/age/if_age.c

3110

reg |= MAC_CFG_VLAN_TAG_STRIP;

sys/dev/age/if_age.c

3111

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/age/if_age.c

337

uint32_t ea[2], reg;

sys/dev/age/if_age.c

340

reg = CSR_READ_4(sc, AGE_SPI_CTRL);

sys/dev/age/if_age.c

341

if ((reg & SPI_VPD_ENB) != 0) {

sys/dev/age/if_age.c

343

reg &= ~SPI_VPD_ENB;

sys/dev/age/if_age.c

344

CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);

sys/dev/age/if_age.c

356

reg = CSR_READ_4(sc, AGE_TWSI_CTRL);

sys/dev/age/if_age.c

357

if ((reg & TWSI_CTRL_SW_LD_START) == 0)

sys/dev/age/if_age.c

382

uint16_t reg, pn;

sys/dev/age/if_age.c

410

reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,

sys/dev/age/if_age.c

412

if ((reg & PHY_CDTC_ENB) == 0)

sys/dev/age/if_age.c

416

reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,

sys/dev/age/if_age.c

418

if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) {

sys/dev/age/if_age.c

432

reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,

sys/dev/age/if_age.c

435

ATPHY_DBG_DATA, reg | 0x03);

sys/dev/age/if_agevar.h

236

#define CSR_WRITE_4(_sc, reg, val) \

sys/dev/age/if_agevar.h

237

bus_write_4((_sc)->age_res[0], (reg), (val))

sys/dev/age/if_agevar.h

238

#define CSR_WRITE_2(_sc, reg, val) \

sys/dev/age/if_agevar.h

239

bus_write_2((_sc)->age_res[0], (reg), (val))

sys/dev/age/if_agevar.h

240

#define CSR_READ_2(_sc, reg) \

sys/dev/age/if_agevar.h

241

bus_read_2((_sc)->age_res[0], (reg))

sys/dev/age/if_agevar.h

242

#define CSR_READ_4(_sc, reg) \

sys/dev/age/if_agevar.h

243

bus_read_4((_sc)->age_res[0], (reg))

sys/dev/agp/agp_intel.c

261

u_int32_t reg;

sys/dev/agp/agp_intel.c

271

reg = pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) & ~(1 << 1);

sys/dev/agp/agp_intel.c

272

printf("%s: set RDCR to %02x\n", __func__, reg & 0xff);

sys/dev/agp/agp_intel.c

273

pci_write_config(dev, AGP_INTEL_I820_RDCR, reg, 1);

sys/dev/agp/agp_intel.c

281

reg = pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) & ~(1 << 1);

sys/dev/agp/agp_intel.c

282

printf("%s: set AGPM to %02x\n", __func__, reg & 0xff);

sys/dev/agp/agp_intel.c

283

pci_write_config(dev, AGP_INTEL_I845_AGPM, reg, 1);

sys/dev/agp/agp_intel.c

290

reg = pci_read_config(dev, AGP_INTEL_MCHCFG, 2) & ~(1 << 9);

sys/dev/agp/agp_intel.c

291

printf("%s: set MCHCFG to %x04\n", __func__, reg & 0xffff);

sys/dev/agp/agp_intel.c

292

pci_write_config(dev, AGP_INTEL_MCHCFG, reg, 2);

sys/dev/agp/agp_intel.c

295

reg = pci_read_config(dev, AGP_INTEL_NBXCFG, 4) & ~(1 << 9);

sys/dev/agp/agp_intel.c

296

printf("%s: set NBXCFG to %08x\n", __func__, reg);

sys/dev/agp/agp_intel.c

297

pci_write_config(dev, AGP_INTEL_NBXCFG, reg, 4);

sys/dev/aic7xxx/aic79xx_pci.c

830

u_int reg;

sys/dev/aic7xxx/aic79xx_pci.c

844

for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {

sys/dev/aic7xxx/aic79xx_pci.c

847

pci_status[i] = ahd_inb(ahd, reg);

sys/dev/aic7xxx/aic79xx_pci.c

849

ahd_outb(ahd, reg, pci_status[i]);

sys/dev/aic7xxx/aic_osm_lib.h

348

int reg, int width);

sys/dev/aic7xxx/aic_osm_lib.h

350

int reg, uint32_t value,

sys/dev/aic7xxx/aic_osm_lib.h

357

aic_pci_read_config(aic_dev_softc_t pci, int reg, int width)

sys/dev/aic7xxx/aic_osm_lib.h

359

return (pci_read_config(pci, reg, width));

sys/dev/aic7xxx/aic_osm_lib.h

363

aic_pci_write_config(aic_dev_softc_t pci, int reg, uint32_t value, int width)

sys/dev/aic7xxx/aic_osm_lib.h

365

pci_write_config(pci, reg, value, width);

sys/dev/al_eth/al_eth.c

1905

uint32_t reg;

sys/dev/al_eth/al_eth.c

1907

reg = al_udma_iofic_read_cause(regs_base, AL_UDMA_IOFIC_LEVEL_PRIMARY,

sys/dev/al_eth/al_eth.c

1909

if (likely(reg))

sys/dev/al_eth/al_eth.c

1911

__func__, reg);

sys/dev/al_eth/al_eth.c

1913

if (unlikely(reg & AL_INT_GROUP_A_GROUP_D_SUM)) {

sys/dev/al_eth/al_eth.c

1936

if ((reg & AL_INT_GROUP_A_GROUP_B_SUM) != 0 ) {

sys/dev/al_eth/al_eth.c

1952

if ((reg & AL_INT_GROUP_A_GROUP_C_SUM) != 0) {

sys/dev/al_eth/al_eth.c

3420

al_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/al_eth/al_eth.c

3429

-1, reg, &value);

sys/dev/al_eth/al_eth.c

3448

al_miibus_writereg(device_t dev, int phy, int reg, int value)

sys/dev/al_eth/al_eth.c

3456

-1, reg, value);

sys/dev/al_eth/al_init_eth_lm.c

734

uint8_t reg;

sys/dev/al_eth/al_init_eth_lm.c

741

&reg);

sys/dev/al_eth/al_init_eth_lm.c

746

reg &= ~(reg_mask);

sys/dev/al_eth/al_init_eth_lm.c

747

reg |= reg_value;

sys/dev/al_eth/al_init_eth_lm.c

753

reg);

sys/dev/al_eth/al_init_eth_lm.c

853

uint8_t reg;

sys/dev/al_eth/al_init_eth_lm.c

863

&reg);

sys/dev/al_eth/al_init_eth_lm.c

868

if (reg & LM_DS25_SIGNAL_DETECT_MASK)

sys/dev/al_eth/al_init_eth_lm.c

883

uint8_t reg;

sys/dev/al_eth/al_init_eth_lm.c

893

&reg);

sys/dev/al_eth/al_init_eth_lm.c

898

if (reg & LM_DS25_CDR_LOCK_MASK)

sys/dev/alc/if_alc.c

2531

uint32_t reg, pmcs;

sys/dev/alc/if_alc.c

2540

reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);

sys/dev/alc/if_alc.c

2541

reg |= PCIE_PHYMISC_FORCE_RCV_DET;

sys/dev/alc/if_alc.c

2542

CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);

sys/dev/alc/if_alc.c

2561

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/alc/if_alc.c

2562

reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |

sys/dev/alc/if_alc.c

2565

reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;

sys/dev/alc/if_alc.c

2567

reg |= MAC_CFG_RX_ENB;

sys/dev/alc/if_alc.c

2568

CSR_WRITE_4(sc, ALC_MAC_CFG, reg);

sys/dev/alc/if_alc.c

2570

reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);

sys/dev/alc/if_alc.c

2571

reg |= PCIE_PHYMISC_FORCE_RCV_DET;

sys/dev/alc/if_alc.c

2572

CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);

sys/dev/alc/if_alc.c

2588

uint32_t gphy, mac, master, pmcs, reg;

sys/dev/alc/if_alc.c

2625

reg = CSR_READ_4(sc, ALC_MISC);

sys/dev/alc/if_alc.c

2626

reg &= ~MISC_INTNLOSC_OPEN;

sys/dev/alc/if_alc.c

2627

CSR_WRITE_4(sc, ALC_MISC, reg);

sys/dev/alc/if_alc.c

2628

reg |= MISC_INTNLOSC_OPEN;

sys/dev/alc/if_alc.c

2629

CSR_WRITE_4(sc, ALC_MISC, reg);

sys/dev/alc/if_alc.c

2633

reg = CSR_READ_4(sc, ALC_PDLL_TRNS1);

sys/dev/alc/if_alc.c

2634

reg |= PDLL_TRNS1_D3PLLOFF_ENB;

sys/dev/alc/if_alc.c

2635

CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg);

sys/dev/alc/if_alc.c

274

alc_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/alc/if_alc.c

281

v = alc_mii_readreg_816x(sc, phy, reg);

sys/dev/alc/if_alc.c

283

v = alc_mii_readreg_813x(sc, phy, reg);

sys/dev/alc/if_alc.c

288

alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg)

sys/dev/alc/if_alc.c

300

reg == MII_EXTSR)

sys/dev/alc/if_alc.c

304

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/alc/if_alc.c

313

device_printf(sc->alc_dev, "phy read timeout : %d\n", reg);

sys/dev/alc/if_alc.c

3134

uint32_t reg;

sys/dev/alc/if_alc.c

3139

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/alc/if_alc.c

3140

reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |

sys/dev/alc/if_alc.c

3146

reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;

sys/dev/alc/if_alc.c

3151

reg |= MAC_CFG_SPEED_10_100;

sys/dev/alc/if_alc.c

3154

reg |= MAC_CFG_SPEED_1000;

sys/dev/alc/if_alc.c

3158

reg |= MAC_CFG_FULL_DUPLEX;

sys/dev/alc/if_alc.c

3160

reg |= MAC_CFG_TX_FC;

sys/dev/alc/if_alc.c

3162

reg |= MAC_CFG_RX_FC;

sys/dev/alc/if_alc.c

3164

CSR_WRITE_4(sc, ALC_MAC_CFG, reg);

sys/dev/alc/if_alc.c

3171

uint32_t *reg;

sys/dev/alc/if_alc.c

3185

for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;

sys/dev/alc/if_alc.c

3186

reg++) {

sys/dev/alc/if_alc.c

3191

for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;

sys/dev/alc/if_alc.c

3192

reg++) {

sys/dev/alc/if_alc.c

3205

uint32_t *reg;

sys/dev/alc/if_alc.c

321

alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg)

sys/dev/alc/if_alc.c

3222

for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;

sys/dev/alc/if_alc.c

3223

reg++) {

sys/dev/alc/if_alc.c

3224

*reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);

sys/dev/alc/if_alc.c

3228

for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;

sys/dev/alc/if_alc.c

3229

reg++) {

sys/dev/alc/if_alc.c

3230

*reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);

sys/dev/alc/if_alc.c

331

MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg));

sys/dev/alc/if_alc.c

340

device_printf(sc->alc_dev, "phy read timeout : %d\n", reg);

sys/dev/alc/if_alc.c

348

alc_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/alc/if_alc.c

355

v = alc_mii_writereg_816x(sc, phy, reg, val);

sys/dev/alc/if_alc.c

357

v = alc_mii_writereg_813x(sc, phy, reg, val);

sys/dev/alc/if_alc.c

362

alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val)

sys/dev/alc/if_alc.c

369

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/alc/if_alc.c

3774

uint32_t reg;

sys/dev/alc/if_alc.c

3776

reg = CSR_READ_4(sc, ALC_MISC3);

sys/dev/alc/if_alc.c

3777

reg &= ~MISC3_25M_BY_SW;

sys/dev/alc/if_alc.c

3778

reg |= MISC3_25M_NOTO_INTNL;

sys/dev/alc/if_alc.c

3779

CSR_WRITE_4(sc, ALC_MISC3, reg);

sys/dev/alc/if_alc.c

378

device_printf(sc->alc_dev, "phy write timeout : %d\n", reg);

sys/dev/alc/if_alc.c

3781

reg = CSR_READ_4(sc, ALC_MISC);

sys/dev/alc/if_alc.c

3787

reg &= ~MISC_PSW_OCP_MASK;

sys/dev/alc/if_alc.c

3788

reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT);

sys/dev/alc/if_alc.c

3789

reg &= ~MISC_INTNLOSC_OPEN;

sys/dev/alc/if_alc.c

3790

CSR_WRITE_4(sc, ALC_MISC, reg);

sys/dev/alc/if_alc.c

3791

CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);

sys/dev/alc/if_alc.c

3792

reg = CSR_READ_4(sc, ALC_MISC2);

sys/dev/alc/if_alc.c

3793

reg &= ~MISC2_CALB_START;

sys/dev/alc/if_alc.c

3794

CSR_WRITE_4(sc, ALC_MISC2, reg);

sys/dev/alc/if_alc.c

3795

CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START);

sys/dev/alc/if_alc.c

3798

reg &= ~MISC_INTNLOSC_OPEN;

sys/dev/alc/if_alc.c

3801

reg &= ~MISC_ISO_ENB;

sys/dev/alc/if_alc.c

3802

CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);

sys/dev/alc/if_alc.c

3803

CSR_WRITE_4(sc, ALC_MISC, reg);

sys/dev/alc/if_alc.c

3812

uint32_t pmcfg, reg;

sys/dev/alc/if_alc.c

3831

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/alc/if_alc.c

3832

reg |= MASTER_OOB_DIS_OFF | MASTER_RESET;

sys/dev/alc/if_alc.c

3833

CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);

sys/dev/alc/if_alc.c

384

alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val)

sys/dev/alc/if_alc.c

3853

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/alc/if_alc.c

3854

if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC |

sys/dev/alc/if_alc.c

3860

device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg);

sys/dev/alc/if_alc.c

3865

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/alc/if_alc.c

3866

reg |= MASTER_CLK_SEL_DIS;

sys/dev/alc/if_alc.c

3867

CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);

sys/dev/alc/if_alc.c

3875

reg = CSR_READ_4(sc, ALC_MISC3);

sys/dev/alc/if_alc.c

3876

reg &= ~MISC3_25M_BY_SW;

sys/dev/alc/if_alc.c

3877

reg |= MISC3_25M_NOTO_INTNL;

sys/dev/alc/if_alc.c

3878

CSR_WRITE_4(sc, ALC_MISC3, reg);

sys/dev/alc/if_alc.c

3879

reg = CSR_READ_4(sc, ALC_MISC);

sys/dev/alc/if_alc.c

3880

reg &= ~MISC_INTNLOSC_OPEN;

sys/dev/alc/if_alc.c

3882

reg &= ~MISC_ISO_ENB;

sys/dev/alc/if_alc.c

3883

CSR_WRITE_4(sc, ALC_MISC, reg);

sys/dev/alc/if_alc.c

3911

uint32_t reg, rxf_hi, rxf_lo;

sys/dev/alc/if_alc.c

394

((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) |

sys/dev/alc/if_alc.c

4036

reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;

sys/dev/alc/if_alc.c

4038

reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;

sys/dev/alc/if_alc.c

4039

CSR_WRITE_4(sc, ALC_IM_TIMER, reg);

sys/dev/alc/if_alc.c

404

device_printf(sc->alc_dev, "phy write timeout : %d\n", reg);

sys/dev/alc/if_alc.c

4044

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/alc/if_alc.c

4045

reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);

sys/dev/alc/if_alc.c

4046

reg |= MASTER_SA_TIMER_ENB;

sys/dev/alc/if_alc.c

4048

reg |= MASTER_IM_RX_TIMER_ENB;

sys/dev/alc/if_alc.c

4051

reg |= MASTER_IM_TX_TIMER_ENB;

sys/dev/alc/if_alc.c

4052

CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);

sys/dev/alc/if_alc.c

4127

reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &

sys/dev/alc/if_alc.c

4130

reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB;

sys/dev/alc/if_alc.c

4131

CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg);

sys/dev/alc/if_alc.c

4133

reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<

sys/dev/alc/if_alc.c

4137

reg >>= 1;

sys/dev/alc/if_alc.c

4138

reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &

sys/dev/alc/if_alc.c

4140

reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB;

sys/dev/alc/if_alc.c

4141

CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);

sys/dev/alc/if_alc.c

4143

reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT |

sys/dev/alc/if_alc.c

4147

CSR_WRITE_4(sc, ALC_HQTD_CFG, reg);

sys/dev/alc/if_alc.c

4148

reg = WRR_PRI_RESTRICT_NONE;

sys/dev/alc/if_alc.c

4149

reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT |

sys/dev/alc/if_alc.c

415

uint32_t reg;

sys/dev/alc/if_alc.c

4153

CSR_WRITE_4(sc, ALC_WRR, reg);

sys/dev/alc/if_alc.c

4169

reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);

sys/dev/alc/if_alc.c

4170

reg &= SRAM_RX_FIFO_LEN_MASK;

sys/dev/alc/if_alc.c

4171

reg *= 8;

sys/dev/alc/if_alc.c

4172

if (reg > 8 * 1024)

sys/dev/alc/if_alc.c

4173

reg -= RX_FIFO_PAUSE_816X_RSVD;

sys/dev/alc/if_alc.c

4175

reg -= RX_BUF_SIZE_MAX;

sys/dev/alc/if_alc.c

4176

reg /= 8;

sys/dev/alc/if_alc.c

4178

((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &

sys/dev/alc/if_alc.c

4185

reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);

sys/dev/alc/if_alc.c

4186

rxf_hi = (reg * 8) / 10;

sys/dev/alc/if_alc.c

4187

rxf_lo = (reg * 3) / 10;

sys/dev/alc/if_alc.c

4202

reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &

sys/dev/alc/if_alc.c

4204

reg |= RXQ_CFG_RSS_MODE_DIS;

sys/dev/alc/if_alc.c

4206

reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT <<

sys/dev/alc/if_alc.c

4210

reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;

sys/dev/alc/if_alc.c

4214

reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;

sys/dev/alc/if_alc.c

4216

CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);

sys/dev/alc/if_alc.c

4219

reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;

sys/dev/alc/if_alc.c

4220

reg |= sc->alc_rcb;

sys/dev/alc/if_alc.c

4222

reg |= DMA_CFG_CMB_ENB;

sys/dev/alc/if_alc.c

4224

reg |= DMA_CFG_SMB_ENB;

sys/dev/alc/if_alc.c

4226

reg |= DMA_CFG_SMB_DIS;

sys/dev/alc/if_alc.c

4227

reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) <<

sys/dev/alc/if_alc.c

4229

reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) <<

sys/dev/alc/if_alc.c

4231

reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &

sys/dev/alc/if_alc.c

4233

reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &

sys/dev/alc/if_alc.c

4239

reg |= DMA_CFG_RD_CHNL_SEL_2;

sys/dev/alc/if_alc.c

4244

reg |= DMA_CFG_RD_CHNL_SEL_4;

sys/dev/alc/if_alc.c

4248

CSR_WRITE_4(sc, ALC_DMA_CFG, reg);

sys/dev/alc/if_alc.c

4263

reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |

sys/dev/alc/if_alc.c

4270

reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;

sys/dev/alc/if_alc.c

4272

reg |= MAC_CFG_SPEED_10_100;

sys/dev/alc/if_alc.c

4274

reg |= MAC_CFG_SPEED_1000;

sys/dev/alc/if_alc.c

4275

CSR_WRITE_4(sc, ALC_MAC_CFG, reg);

sys/dev/alc/if_alc.c

4302

uint32_t reg;

sys/dev/alc/if_alc.c

4319

reg = CSR_READ_4(sc, ALC_DMA_CFG);

sys/dev/alc/if_alc.c

4320

reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB);

sys/dev/alc/if_alc.c

4321

reg |= DMA_CFG_SMB_DIS;

sys/dev/alc/if_alc.c

4322

CSR_WRITE_4(sc, ALC_DMA_CFG, reg);

sys/dev/alc/if_alc.c

4364

uint32_t reg;

sys/dev/alc/if_alc.c

4369

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/alc/if_alc.c

4370

if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {

sys/dev/alc/if_alc.c

4371

reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);

sys/dev/alc/if_alc.c

4372

CSR_WRITE_4(sc, ALC_MAC_CFG, reg);

sys/dev/alc/if_alc.c

4375

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/alc/if_alc.c

4376

if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0)

sys/dev/alc/if_alc.c

4382

"could not disable Rx/Tx MAC(0x%08x)!\n", reg);

sys/dev/alc/if_alc.c

4416

uint32_t reg;

sys/dev/alc/if_alc.c

4420

reg = CSR_READ_4(sc, ALC_RXQ_CFG);

sys/dev/alc/if_alc.c

4422

if ((reg & RXQ_CFG_ENB) != 0) {

sys/dev/alc/if_alc.c

4423

reg &= ~RXQ_CFG_ENB;

sys/dev/alc/if_alc.c

4424

CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);

sys/dev/alc/if_alc.c

4427

if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) {

sys/dev/alc/if_alc.c

4428

reg &= ~RXQ_CFG_QUEUE0_ENB;

sys/dev/alc/if_alc.c

4429

CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);

sys/dev/alc/if_alc.c

4433

reg = CSR_READ_4(sc, ALC_TXQ_CFG);

sys/dev/alc/if_alc.c

4434

if ((reg & TXQ_CFG_ENB) != 0) {

sys/dev/alc/if_alc.c

4435

reg &= ~TXQ_CFG_ENB;

sys/dev/alc/if_alc.c

4436

CSR_WRITE_4(sc, ALC_TXQ_CFG, reg);

sys/dev/alc/if_alc.c

4440

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/alc/if_alc.c

4441

if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)

sys/dev/alc/if_alc.c

4447

"could not disable RxQ/TxQ (0x%08x)!\n", reg);

sys/dev/alc/if_alc.c

449

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/alc/if_alc.c

450

reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;

sys/dev/alc/if_alc.c

451

CSR_WRITE_4(sc, ALC_MAC_CFG, reg);

sys/dev/alc/if_alc.c

4555

uint32_t reg;

sys/dev/alc/if_alc.c

4560

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/alc/if_alc.c

4562

reg |= MAC_CFG_VLAN_TAG_STRIP;

sys/dev/alc/if_alc.c

4564

reg &= ~MAC_CFG_VLAN_TAG_STRIP;

sys/dev/alc/if_alc.c

4565

CSR_WRITE_4(sc, ALC_MAC_CFG, reg);

sys/dev/alc/if_alc.c

458

alc_miidbg_readreg(struct alc_softc *sc, int reg)

sys/dev/alc/if_alc.c

462

reg);

sys/dev/alc/if_alc.c

468

alc_miidbg_writereg(struct alc_softc *sc, int reg, int val)

sys/dev/alc/if_alc.c

472

reg);

sys/dev/alc/if_alc.c

478

alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg)

sys/dev/alc/if_alc.c

483

CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |

sys/dev/alc/if_alc.c

500

devaddr, reg);

sys/dev/alc/if_alc.c

508

alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val)

sys/dev/alc/if_alc.c

513

CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |

sys/dev/alc/if_alc.c

531

devaddr, reg);

sys/dev/alc/if_alc.c

803

uint32_t reg;

sys/dev/alc/if_alc.c

809

reg = CSR_READ_4(sc, ALC_SLD);

sys/dev/alc/if_alc.c

810

if ((reg & (SLD_PROGRESS | SLD_START)) == 0)

sys/dev/alc/if_alc.c

815

CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START);

sys/dev/alc/if_alc.c

818

reg = CSR_READ_4(sc, ALC_SLD);

sys/dev/alc/if_alc.c

819

if ((reg & SLD_START) == 0)

sys/dev/alc/if_alc.c

831

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/alc/if_alc.c

832

if ((reg & (EEPROM_LD_EEPROM_EXIST |

sys/dev/alc/if_alc.c

835

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/alc/if_alc.c

836

if ((reg & (EEPROM_LD_PROGRESS |

sys/dev/alc/if_alc.c

842

CSR_WRITE_4(sc, ALC_EEPROM_LD, reg |

sys/dev/alc/if_alc.c

846

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/alc/if_alc.c

847

if ((reg & EEPROM_LD_START) == 0)

sys/dev/alc/if_alcvar.h

259

#define CSR_WRITE_4(_sc, reg, val) \

sys/dev/alc/if_alcvar.h

260

bus_write_4((_sc)->alc_res[0], (reg), (val))

sys/dev/alc/if_alcvar.h

261

#define CSR_WRITE_2(_sc, reg, val) \

sys/dev/alc/if_alcvar.h

262

bus_write_2((_sc)->alc_res[0], (reg), (val))

sys/dev/alc/if_alcvar.h

263

#define CSR_WRITE_1(_sc, reg, val) \

sys/dev/alc/if_alcvar.h

264

bus_write_1((_sc)->alc_res[0], (reg), (val))

sys/dev/alc/if_alcvar.h

265

#define CSR_READ_2(_sc, reg) \

sys/dev/alc/if_alcvar.h

266

bus_read_2((_sc)->alc_res[0], (reg))

sys/dev/alc/if_alcvar.h

267

#define CSR_READ_4(_sc, reg) \

sys/dev/alc/if_alcvar.h

268

bus_read_4((_sc)->alc_res[0], (reg))

sys/dev/ale/if_ale.c

1468

uint32_t reg, pmcs;

sys/dev/ale/if_ale.c

1475

reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);

sys/dev/ale/if_ale.c

1476

reg |= PCIE_PHYMISC_FORCE_RCV_DET;

sys/dev/ale/if_ale.c

1477

CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);

sys/dev/ale/if_ale.c

1497

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/ale/if_ale.c

1498

reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |

sys/dev/ale/if_ale.c

1501

reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;

sys/dev/ale/if_ale.c

1503

reg |= MAC_CFG_RX_ENB;

sys/dev/ale/if_ale.c

1504

CSR_WRITE_4(sc, ALE_MAC_CFG, reg);

sys/dev/ale/if_ale.c

1508

reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);

sys/dev/ale/if_ale.c

1509

reg |= PCIE_PHYMISC_FORCE_RCV_DET;

sys/dev/ale/if_ale.c

1510

CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);

sys/dev/ale/if_ale.c

201

ale_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/ale/if_ale.c

2036

uint32_t reg;

sys/dev/ale/if_ale.c

2041

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/ale/if_ale.c

2042

reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |

sys/dev/ale/if_ale.c

2048

reg |= MAC_CFG_SPEED_10_100;

sys/dev/ale/if_ale.c

2051

reg |= MAC_CFG_SPEED_1000;

sys/dev/ale/if_ale.c

2055

reg |= MAC_CFG_FULL_DUPLEX;

sys/dev/ale/if_ale.c

2057

reg |= MAC_CFG_TX_FC;

sys/dev/ale/if_ale.c

2059

reg |= MAC_CFG_RX_FC;

sys/dev/ale/if_ale.c

2061

CSR_WRITE_4(sc, ALE_MAC_CFG, reg);

sys/dev/ale/if_ale.c

2068

uint32_t *reg;

sys/dev/ale/if_ale.c

2071

for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {

sys/dev/ale/if_ale.c

2076

for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {

sys/dev/ale/if_ale.c

2088

uint32_t *reg;

sys/dev/ale/if_ale.c

2098

for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {

sys/dev/ale/if_ale.c

2099

*reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);

sys/dev/ale/if_ale.c

210

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/ale/if_ale.c

2103

for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {

sys/dev/ale/if_ale.c

2104

*reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);

sys/dev/ale/if_ale.c

219

device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);

sys/dev/ale/if_ale.c

227

ale_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/ale/if_ale.c

237

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/ale/if_ale.c

246

device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);

sys/dev/ale/if_ale.c

2549

uint32_t reg;

sys/dev/ale/if_ale.c

2565

if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)

sys/dev/ale/if_ale.c

257

uint32_t reg;

sys/dev/ale/if_ale.c

2571

device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);

sys/dev/ale/if_ale.c

2592

uint32_t reg, rxf_hi, rxf_lo;

sys/dev/ale/if_ale.c

2671

reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;

sys/dev/ale/if_ale.c

2672

reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;

sys/dev/ale/if_ale.c

2673

CSR_WRITE_4(sc, ALE_IM_TIMER, reg);

sys/dev/ale/if_ale.c

2674

reg = CSR_READ_4(sc, ALE_MASTER_CFG);

sys/dev/ale/if_ale.c

2675

reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);

sys/dev/ale/if_ale.c

2676

reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);

sys/dev/ale/if_ale.c

2678

reg |= MASTER_IM_RX_TIMER_ENB;

sys/dev/ale/if_ale.c

2680

reg |= MASTER_IM_TX_TIMER_ENB;

sys/dev/ale/if_ale.c

2681

CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);

sys/dev/ale/if_ale.c

2712

reg = sc->ale_max_frame_size;

sys/dev/ale/if_ale.c

2714

reg = (sc->ale_max_frame_size * 2) / 3;

sys/dev/ale/if_ale.c

2716

reg = sc->ale_max_frame_size / 2;

sys/dev/ale/if_ale.c

2718

roundup(reg, TX_JUMBO_THRESH_UNIT) >>

sys/dev/ale/if_ale.c

2722

reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))

sys/dev/ale/if_ale.c

2724

reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &

sys/dev/ale/if_ale.c

2726

CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);

sys/dev/ale/if_ale.c

2730

reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);

sys/dev/ale/if_ale.c

2732

(((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<

sys/dev/ale/if_ale.c

2736

reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);

sys/dev/ale/if_ale.c

2737

rxf_hi = (reg * 7) / 10;

sys/dev/ale/if_ale.c

2738

rxf_lo = (reg * 3)/ 10;

sys/dev/ale/if_ale.c

2755

reg = 0;

sys/dev/ale/if_ale.c

2757

reg |= DMA_CFG_TXCMB_ENB;

sys/dev/ale/if_ale.c

2760

sc->ale_dma_rd_burst | reg |

sys/dev/ale/if_ale.c

2788

reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |

sys/dev/ale/if_ale.c

2792

reg |= MAC_CFG_SPEED_10_100;

sys/dev/ale/if_ale.c

2794

reg |= MAC_CFG_SPEED_1000;

sys/dev/ale/if_ale.c

2795

CSR_WRITE_4(sc, ALE_MAC_CFG, reg);

sys/dev/ale/if_ale.c

2821

uint32_t reg;

sys/dev/ale/if_ale.c

2838

reg = CSR_READ_4(sc, ALE_TXQ_CFG);

sys/dev/ale/if_ale.c

2839

reg &= ~TXQ_CFG_ENB;

sys/dev/ale/if_ale.c

2840

CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);

sys/dev/ale/if_ale.c

2841

reg = CSR_READ_4(sc, ALE_RXQ_CFG);

sys/dev/ale/if_ale.c

2842

reg &= ~RXQ_CFG_ENB;

sys/dev/ale/if_ale.c

2843

CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);

sys/dev/ale/if_ale.c

2844

reg = CSR_READ_4(sc, ALE_DMA_CFG);

sys/dev/ale/if_ale.c

2845

reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);

sys/dev/ale/if_ale.c

2846

CSR_WRITE_4(sc, ALE_DMA_CFG, reg);

sys/dev/ale/if_ale.c

2872

uint32_t reg;

sys/dev/ale/if_ale.c

2877

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/ale/if_ale.c

2878

if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {

sys/dev/ale/if_ale.c

2879

reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);

sys/dev/ale/if_ale.c

2880

CSR_WRITE_4(sc, ALE_MAC_CFG, reg);

sys/dev/ale/if_ale.c

2884

reg = CSR_READ_4(sc, ALE_IDLE_STATUS);

sys/dev/ale/if_ale.c

2885

if (reg == 0)

sys/dev/ale/if_ale.c

2891

"could not disable Tx/Rx MAC(0x%08x)!\n", reg);

sys/dev/ale/if_ale.c

290

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/ale/if_ale.c

291

reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;

sys/dev/ale/if_ale.c

292

CSR_WRITE_4(sc, ALE_MAC_CFG, reg);

sys/dev/ale/if_ale.c

2950

uint32_t reg;

sys/dev/ale/if_ale.c

2955

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/ale/if_ale.c

2956

reg &= ~MAC_CFG_VLAN_TAG_STRIP;

sys/dev/ale/if_ale.c

2958

reg |= MAC_CFG_VLAN_TAG_STRIP;

sys/dev/ale/if_ale.c

2959

CSR_WRITE_4(sc, ALE_MAC_CFG, reg);

sys/dev/ale/if_ale.c

360

uint32_t ea[2], reg;

sys/dev/ale/if_ale.c

363

reg = CSR_READ_4(sc, ALE_SPI_CTRL);

sys/dev/ale/if_ale.c

364

if ((reg & SPI_VPD_ENB) != 0) {

sys/dev/ale/if_ale.c

365

reg &= ~SPI_VPD_ENB;

sys/dev/ale/if_ale.c

366

CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);

sys/dev/ale/if_ale.c

378

reg = CSR_READ_4(sc, ALE_TWSI_CTRL);

sys/dev/ale/if_ale.c

379

if ((reg & TWSI_CTRL_SW_LD_START) == 0)

sys/dev/ale/if_alevar.h

228

#define CSR_WRITE_4(_sc, reg, val) \

sys/dev/ale/if_alevar.h

229

bus_write_4((_sc)->ale_res[0], (reg), (val))

sys/dev/ale/if_alevar.h

230

#define CSR_WRITE_2(_sc, reg, val) \

sys/dev/ale/if_alevar.h

231

bus_write_2((_sc)->ale_res[0], (reg), (val))

sys/dev/ale/if_alevar.h

232

#define CSR_WRITE_1(_sc, reg, val) \

sys/dev/ale/if_alevar.h

233

bus_write_1((_sc)->ale_res[0], (reg), (val))

sys/dev/ale/if_alevar.h

234

#define CSR_READ_2(_sc, reg) \

sys/dev/ale/if_alevar.h

235

bus_read_2((_sc)->ale_res[0], (reg))

sys/dev/ale/if_alevar.h

236

#define CSR_READ_4(_sc, reg) \

sys/dev/ale/if_alevar.h

237

bus_read_4((_sc)->ale_res[0], (reg))

sys/dev/amdgpio/amdgpio.c

203

uint32_t reg, val;

sys/dev/amdgpio/amdgpio.c

229

reg = AMDGPIO_PIN_REGISTER(pin);

sys/dev/amdgpio/amdgpio.c

230

val = amdgpio_read_4(sc, reg);

sys/dev/amdgpio/amdgpio.c

244

amdgpio_write_4(sc, reg, val);

sys/dev/amdgpio/amdgpio.c

259

uint32_t reg, val;

sys/dev/amdgpio/amdgpio.c

271

reg = AMDGPIO_PIN_REGISTER(pin);

sys/dev/amdgpio/amdgpio.c

272

val = amdgpio_read_4(sc, reg);

sys/dev/amdgpio/amdgpio.c

297

uint32_t reg, val;

sys/dev/amdgpio/amdgpio.c

310

reg = AMDGPIO_PIN_REGISTER(pin);

sys/dev/amdgpio/amdgpio.c

311

val = amdgpio_read_4(sc, reg);

sys/dev/amdgpio/amdgpio.c

318

amdgpio_write_4(sc, reg, val);

sys/dev/amdgpio/amdgpio.c

331

uint32_t reg, val;

sys/dev/amdgpio/amdgpio.c

345

reg = AMDGPIO_PIN_REGISTER(pin);

sys/dev/amdgpio/amdgpio.c

346

val = amdgpio_read_4(sc, reg);

sys/dev/amdgpio/amdgpio.c

350

amdgpio_write_4(sc, reg, val);

sys/dev/amdgpio/amdgpio.c

395

uint32_t reg;

sys/dev/amdgpio/amdgpio.c

410

reg = amdgpio_read_4(sc, off);

sys/dev/amdgpio/amdgpio.c

411

if ((reg & UNSERVICED_INTERRUPT_MASK) == 0)

sys/dev/amdgpio/amdgpio.c

417

amdgpio_write_4(sc, off, reg);

sys/dev/amdgpio/amdgpio.c

437

int i, pin, bank, reg;

sys/dev/amdgpio/amdgpio.c

495

reg = AMDGPIO_PIN_REGISTER(pin);

sys/dev/amdgpio/amdgpio.c

496

flags = amdgpio_read_4(sc, reg);

sys/dev/amdgpio/amdgpio.c

499

amdgpio_write_4(sc, reg, flags);

sys/dev/amdgpio/amdgpio.c

82

uint32_t reg, val;

sys/dev/amdgpio/amdgpio.c

88

reg = AMDGPIO_PIN_REGISTER(pin);

sys/dev/amdgpio/amdgpio.c

89

val = amdgpio_read_4(sc, reg);

sys/dev/amdsbwd/amdsbwd.c

133

pmio_read(struct resource *res, uint8_t reg)

sys/dev/amdsbwd/amdsbwd.c

135

bus_write_1(res, 0, reg); /* Index */

sys/dev/amdsbwd/amdsbwd.c

140

pmio_write(struct resource *res, uint8_t reg, uint8_t val)

sys/dev/amdsbwd/amdsbwd.c

142

bus_write_1(res, 0, reg); /* Index */

sys/dev/amdsmu/amdsmu.h

102

amdsmu_read4(const struct amdsmu_softc *sc, bus_size_t reg)

sys/dev/amdsmu/amdsmu.h

104

return (bus_space_read_4(sc->bus_tag, sc->reg_space, reg));

sys/dev/amdsmu/amdsmu.h

108

amdsmu_write4(const struct amdsmu_softc *sc, bus_size_t reg, uint32_t val)

sys/dev/amdsmu/amdsmu.h

110

bus_space_write_4(sc->bus_tag, sc->reg_space, reg, val);

sys/dev/aq/aq_hw.h

45

#define AQ_WRITE_REG(hw, reg, value) writel(((hw)->hw_addr + (reg)), htole32(value))

sys/dev/aq/aq_hw.h

47

#define AQ_READ_REG(hw, reg) le32toh(readl((hw)->hw_addr + reg))

sys/dev/aq/aq_hw.h

50

#define AQ_WRITE_REG_BIT(hw, reg, msk, shift, value) do { \

sys/dev/aq/aq_hw.h

53

reg_old = AQ_READ_REG(hw, reg); \

sys/dev/aq/aq_hw.h

56

AQ_WRITE_REG(hw, reg, reg_new); \

sys/dev/aq/aq_hw.h

58

AQ_WRITE_REG(hw, reg, value); \

sys/dev/aq/aq_hw.h

63

#define AQ_READ_REG_BIT(a, reg, msk, shift) ( \

sys/dev/aq/aq_hw.h

64

((AQ_READ_REG(a, reg) & msk) >> shift))

sys/dev/ata/ata-all.h

372

int (*pm_read)(device_t dev, int port, int reg, u_int32_t *result);

sys/dev/ata/ata-all.h

373

int (*pm_write)(device_t dev, int port, int reg, u_int32_t value);

sys/dev/ata/ata-all.h

488

int ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val);

sys/dev/ata/ata-all.h

489

int ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val);

sys/dev/ata/ata-pci.c

204

ata_pci_read_config(device_t dev, device_t child, int reg, int width)

sys/dev/ata/ata-pci.c

207

return (pci_read_config(dev, reg, width));

sys/dev/ata/ata-pci.c

211

ata_pci_write_config(device_t dev, device_t child, int reg,

sys/dev/ata/ata-pci.c

215

pci_write_config(dev, reg, val, width);

sys/dev/ata/ata-pci.h

535

uint32_t ata_pci_read_config(device_t dev, device_t child, int reg, int width);

sys/dev/ata/ata-pci.h

536

void ata_pci_write_config(device_t dev, device_t child, int reg,

sys/dev/ata/ata-sata.c

100

if (ch->r_io[reg].res) {

sys/dev/ata/ata-sata.c

101

ATA_IDX_OUTL(ch, reg, val);

sys/dev/ata/ata-sata.c

82

ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val)

sys/dev/ata/ata-sata.c

86

return (ch->hw.pm_read(ch->dev, port, reg, val));

sys/dev/ata/ata-sata.c

87

if (ch->r_io[reg].res) {

sys/dev/ata/ata-sata.c

88

*val = ATA_IDX_INL(ch, reg);

sys/dev/ata/ata-sata.c

95

ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val)

sys/dev/ata/ata-sata.c

99

return (ch->hw.pm_write(ch->dev, port, reg, val));

sys/dev/ata/chipsets/ata-amd.c

118

int reg = 0x53 - devno;

sys/dev/ata/chipsets/ata-amd.c

130

pci_write_config(parent, reg, modes[mode & ATA_MODE_MASK], 1);

sys/dev/ata/chipsets/ata-amd.c

133

pci_write_config(parent, reg, 0x8b, 1);

sys/dev/ata/chipsets/ata-amd.c

137

pci_write_config(parent, reg - 0x08, timings[ata_mode2idx(piomode)], 1);

sys/dev/ata/chipsets/ata-highpoint.c

200

u_int8_t reg, val, res;

sys/dev/ata/chipsets/ata-highpoint.c

203

reg = ch->unit ? 0x57 : 0x53;

sys/dev/ata/chipsets/ata-highpoint.c

204

val = pci_read_config(parent, reg, 1);

sys/dev/ata/chipsets/ata-highpoint.c

205

pci_write_config(parent, reg, val | 0x80, 1);

sys/dev/ata/chipsets/ata-highpoint.c

208

reg = 0x5b;

sys/dev/ata/chipsets/ata-highpoint.c

209

val = pci_read_config(parent, reg, 1);

sys/dev/ata/chipsets/ata-highpoint.c

210

pci_write_config(parent, reg, val & 0xfe, 1);

sys/dev/ata/chipsets/ata-highpoint.c

213

pci_write_config(parent, reg, val, 1);

sys/dev/ata/chipsets/ata-intel.c

600

ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result)

sys/dev/ata/chipsets/ata-intel.c

614

switch (reg) {

sys/dev/ata/chipsets/ata-intel.c

616

reg = 0x28;

sys/dev/ata/chipsets/ata-intel.c

619

reg = 0x2c;

sys/dev/ata/chipsets/ata-intel.c

622

reg = 0x30;

sys/dev/ata/chipsets/ata-intel.c

627

*result = ATA_INL(ctlr->r_res2, offset + reg);

sys/dev/ata/chipsets/ata-intel.c

63

int reg, u_int32_t *result);

sys/dev/ata/chipsets/ata-intel.c

632

ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result)

sys/dev/ata/chipsets/ata-intel.c

644

switch (reg) {

sys/dev/ata/chipsets/ata-intel.c

646

reg = 0;

sys/dev/ata/chipsets/ata-intel.c

649

reg = 1;

sys/dev/ata/chipsets/ata-intel.c

65

int reg, u_int32_t *result);

sys/dev/ata/chipsets/ata-intel.c

652

reg = 2;

sys/dev/ata/chipsets/ata-intel.c

659

0x50 + smap[port] * 0x10 + reg * 4, 4);

sys/dev/ata/chipsets/ata-intel.c

666

ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result)

sys/dev/ata/chipsets/ata-intel.c

67

int reg, u_int32_t *result);

sys/dev/ata/chipsets/ata-intel.c

676

switch (reg) {

sys/dev/ata/chipsets/ata-intel.c

678

reg = 0;

sys/dev/ata/chipsets/ata-intel.c

681

reg = 1;

sys/dev/ata/chipsets/ata-intel.c

684

reg = 2;

sys/dev/ata/chipsets/ata-intel.c

69

int reg, u_int32_t result);

sys/dev/ata/chipsets/ata-intel.c

690

ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg);

sys/dev/ata/chipsets/ata-intel.c

697

ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value)

sys/dev/ata/chipsets/ata-intel.c

71

int reg, u_int32_t result);

sys/dev/ata/chipsets/ata-intel.c

711

switch (reg) {

sys/dev/ata/chipsets/ata-intel.c

713

reg = 0x28;

sys/dev/ata/chipsets/ata-intel.c

716

reg = 0x2c;

sys/dev/ata/chipsets/ata-intel.c

719

reg = 0x30;

sys/dev/ata/chipsets/ata-intel.c

724

ATA_OUTL(ctlr->r_res2, offset + reg, value);

sys/dev/ata/chipsets/ata-intel.c

729

ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value)

sys/dev/ata/chipsets/ata-intel.c

73

int reg, u_int32_t result);

sys/dev/ata/chipsets/ata-intel.c

741

switch (reg) {

sys/dev/ata/chipsets/ata-intel.c

743

reg = 0;

sys/dev/ata/chipsets/ata-intel.c

746

reg = 1;

sys/dev/ata/chipsets/ata-intel.c

749

reg = 2;

sys/dev/ata/chipsets/ata-intel.c

756

0x50 + smap[port] * 0x10 + reg * 4, 4);

sys/dev/ata/chipsets/ata-intel.c

763

ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value)

sys/dev/ata/chipsets/ata-intel.c

773

switch (reg) {

sys/dev/ata/chipsets/ata-intel.c

775

reg = 0;

sys/dev/ata/chipsets/ata-intel.c

778

reg = 1;

sys/dev/ata/chipsets/ata-intel.c

781

reg = 2;

sys/dev/ata/chipsets/ata-intel.c

787

ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg);

sys/dev/ata/chipsets/ata-nvidia.c

332

int reg = 0x63 - devno;

sys/dev/ata/chipsets/ata-nvidia.c

337

pci_write_config(parent, reg, modes[mode & ATA_MODE_MASK], 1);

sys/dev/ata/chipsets/ata-nvidia.c

340

pci_write_config(parent, reg, 0x8b, 1);

sys/dev/ata/chipsets/ata-nvidia.c

343

pci_write_config(parent, reg - 0x08, timings[ata_mode2idx(piomode)], 1);

sys/dev/ata/chipsets/ata-promise.c

68

static int ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result);

sys/dev/ata/chipsets/ata-promise.c

69

static int ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t result);

sys/dev/ata/chipsets/ata-promise.c

822

ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result)

sys/dev/ata/chipsets/ata-promise.c

829

*result = ATA_IDX_INL(ch, reg);

sys/dev/ata/chipsets/ata-promise.c

833

switch (reg) {

sys/dev/ata/chipsets/ata-promise.c

835

reg = 0;

sys/dev/ata/chipsets/ata-promise.c

838

reg = 1;

sys/dev/ata/chipsets/ata-promise.c

841

reg = 2;

sys/dev/ata/chipsets/ata-promise.c

850

ATA_IDX_OUTB(ch, ATA_FEATURE, reg);

sys/dev/ata/chipsets/ata-promise.c

873

ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t value)

sys/dev/ata/chipsets/ata-promise.c

880

ATA_IDX_OUTL(ch, reg, value);

sys/dev/ata/chipsets/ata-promise.c

884

switch (reg) {

sys/dev/ata/chipsets/ata-promise.c

886

reg = 0;

sys/dev/ata/chipsets/ata-promise.c

889

reg = 1;

sys/dev/ata/chipsets/ata-promise.c

892

reg = 2;

sys/dev/ata/chipsets/ata-promise.c

901

ATA_IDX_OUTB(ch, ATA_FEATURE, reg);

sys/dev/ata/chipsets/ata-sis.c

266

u_int32_t reg;

sys/dev/ata/chipsets/ata-sis.c

268

reg = (pci_read_config(parent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);

sys/dev/ata/chipsets/ata-sis.c

269

pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4);

sys/dev/ata/chipsets/ata-sis.c

277

u_int16_t reg = 0x40 + (devno << 1);

sys/dev/ata/chipsets/ata-sis.c

279

pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);

sys/dev/ata/chipsets/ata-sis.c

286

u_int16_t reg = 0x40 + (devno << 1);

sys/dev/ata/chipsets/ata-sis.c

288

pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);

sys/dev/ata/chipsets/ata-sis.c

297

u_int16_t reg = 0x40 + (devno << 1);

sys/dev/ata/chipsets/ata-sis.c

299

pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);

sys/dev/ata/chipsets/ata-via.c

348

int reg = 0x53 - devno;

sys/dev/ata/chipsets/ata-via.c

361

pci_write_config(parent, reg,

sys/dev/ata/chipsets/ata-via.c

365

pci_write_config(parent, reg, 0x8b, 1);

sys/dev/ata/chipsets/ata-via.c

369

pci_write_config(parent, reg - 0x08,timings[ata_mode2idx(piomode)], 1);

sys/dev/ata/chipsets/ata-via.c

481

ata_via_sata_scr_read(device_t dev, int port, int reg, u_int32_t *result)

sys/dev/ata/chipsets/ata-via.c

488

switch (reg) {

sys/dev/ata/chipsets/ata-via.c

527

ata_via_sata_scr_write(device_t dev, int port, int reg, u_int32_t value)

sys/dev/ata/chipsets/ata-via.c

534

switch (reg) {

sys/dev/ata/chipsets/ata-via.c

65

static int ata_via_sata_scr_read(device_t dev, int port, int reg,

sys/dev/ata/chipsets/ata-via.c

67

static int ata_via_sata_scr_write(device_t dev, int port, int reg,

sys/dev/ath/ah_osdep.c

147

ath_hal_reg_whilst_asleep(struct ath_hal *ah, uint32_t reg)

sys/dev/ath/ah_osdep.c

150

if (reg >= 0x4000 && reg < 0x5000)

sys/dev/ath/ah_osdep.c

152

if (reg >= 0x6000 && reg < 0x7000)

sys/dev/ath/ah_osdep.c

154

if (reg >= 0x7000 && reg < 0x8000)

sys/dev/ath/ah_osdep.c

257

r->reg = 0;

sys/dev/ath/ah_osdep.c

271

ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)

sys/dev/ath/ah_osdep.c

278

if (! ath_hal_reg_whilst_asleep(ah, reg) &&

sys/dev/ath/ah_osdep.c

281

__func__, reg, val, ah->ah_powerMode);

sys/dev/ath/ah_osdep.c

291

r->reg = reg;

sys/dev/ath/ah_osdep.c

298

bus_space_write_4(tag, h, reg, val);

sys/dev/ath/ah_osdep.c

299

OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_WRITE);

sys/dev/ath/ah_osdep.c

305

ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)

sys/dev/ath/ah_osdep.c

313

if (! ath_hal_reg_whilst_asleep(ah, reg) &&

sys/dev/ath/ah_osdep.c

316

__func__, reg, ah->ah_powerMode);

sys/dev/ath/ah_osdep.c

322

OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_READ);

sys/dev/ath/ah_osdep.c

323

val = bus_space_read_4(tag, h, reg);

sys/dev/ath/ah_osdep.c

332

r->reg = reg;

sys/dev/ath/ah_osdep.c

349

r->reg = id;

sys/dev/ath/ah_osdep.c

369

ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)

sys/dev/ath/ah_osdep.c

376

if (! ath_hal_reg_whilst_asleep(ah, reg) &&

sys/dev/ath/ah_osdep.c

379

__func__, reg, val, ah->ah_powerMode);

sys/dev/ath/ah_osdep.c

385

bus_space_write_4(tag, h, reg, val);

sys/dev/ath/ah_osdep.c

386

OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_WRITE);

sys/dev/ath/ah_osdep.c

392

ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)

sys/dev/ath/ah_osdep.c

400

if (! ath_hal_reg_whilst_asleep(ah, reg) &&

sys/dev/ath/ah_osdep.c

403

__func__, reg, ah->ah_powerMode);

sys/dev/ath/ah_osdep.c

409

OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_READ);

sys/dev/ath/ah_osdep.c

410

val = bus_space_read_4(tag, h, reg);

sys/dev/ath/ah_osdep.h

140

extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);

sys/dev/ath/ah_osdep.h

141

extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);

sys/dev/ath/ath_hal/ah.c

303

ath_hal_wait(struct ath_hal *ah, u_int reg, uint32_t mask, uint32_t val)

sys/dev/ath/ath_hal/ah.c

306

return ath_hal_waitfor(ah, reg, mask, val, AH_TIMEOUT);

sys/dev/ath/ath_hal/ah.c

311

ath_hal_waitfor(struct ath_hal *ah, u_int reg, uint32_t mask, uint32_t val, uint32_t timeout)

sys/dev/ath/ath_hal/ah.c

316

if ((OS_REG_READ(ah, reg) & mask) == val)

sys/dev/ath/ath_hal/ah.c

322

__func__, reg, OS_REG_READ(ah, reg), mask, val);

sys/dev/ath/ath_hal/ah_decode.h

34

reg : 24;

sys/dev/ath/ath_hal/ah_internal.h

615

extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,

sys/dev/ath/ath_hal/ah_internal.h

617

extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg,

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

193

uint32_t reg;

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

197

reg = OS_REG_READ(ah, AR_GPIODO);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

198

reg &= ~(1 << gpio);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

199

reg |= (val&1) << gpio;

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

201

OS_REG_WRITE(ah, AR_GPIODO, reg);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

718

uint32_t reg;

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

720

reg = OS_REG_READ(ah, AR_NAV);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

721

return (reg);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

209

uint32_t reg = ar5k0007_init[i].Offset;

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

211

if (!(bChannelChange && (0x8000 <= reg && reg < 0x9000)))

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

212

OS_REG_WRITE(ah, reg, ar5k0007_init[i].Value);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

197

uint32_t reg;

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

201

reg = OS_REG_READ(ah, AR_GPIOCR);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

202

reg &= ~(AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT));

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

203

reg |= AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

205

OS_REG_WRITE(ah, AR_GPIOCR, reg);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

215

uint32_t reg;

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

219

reg = OS_REG_READ(ah, AR_GPIOCR);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

220

reg &= ~(AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT));

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

221

reg |= AR_GPIOCR_0_CR_N << (gpio * AR_GPIOCR_CR_SHIFT);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

223

OS_REG_WRITE(ah, AR_GPIOCR, reg);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

233

uint32_t reg;

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

237

reg = OS_REG_READ(ah, AR_GPIODO);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

238

reg &= ~(1 << gpio);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

239

reg |= (val&1) << gpio;

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

241

OS_REG_WRITE(ah, AR_GPIODO, reg);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

741

uint32_t reg;

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

743

reg = OS_REG_READ(ah, AR_NAV);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

744

return (reg);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

331

uint32_t reg = ar5211Common[i][0];

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

333

if (!(bChannelChange && (0x8000 <= reg && reg < 0x9000)))

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

334

OS_REG_WRITE(ah, reg, ar5211Common[i][1]);

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

74

uint32_t reg;

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

78

reg = OS_REG_READ(ah, AR_GPIODO);

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

79

reg &= ~(1 << gpio);

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

80

reg |= (val&1) << gpio;

sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c

82

OS_REG_WRITE(ah, AR_GPIODO, reg);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1468

uint32_t reg;

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1470

reg = OS_REG_READ(ah, AR_NAV);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1472

if (reg == 0xdeadbeef)

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

1474

return (reg);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

302

uint32_t reg;

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

319

reg = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

321

OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

323

OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2741

uint32_t reg = AR_RATE_DURATION(rt->info[i].rateCode);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2746

OS_REG_WRITE(ah, reg,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2753

reg += rt->info[i].shortPreamble << 2;

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

2754

OS_REG_WRITE(ah, reg,

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

83

uint32_t reg = V(r, 0);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

86

if (!(bChannelChange && IS_NO_RESET_TIMER_ADDR(reg))) {

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

87

OS_REG_WRITE(ah, reg, V(r, 1));

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

74

uint32_t reg;

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

79

reg = OS_REG_READ(ah, gpioOffset+AR5312_GPIODO);

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

80

reg &= ~(1 << gpio);

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

81

reg |= (val&1) << gpio;

sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c

83

OS_REG_WRITE(ah, gpioOffset+AR5312_GPIODO, reg);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

67

uint32_t reg = V(i, 0);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

70

if (!(bChannelChange && IS_NO_RESET_TIMER_ADDR(reg))) {

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

71

OS_REG_WRITE(ah, reg, V(i, 1));

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

771

uint32_t reg;

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

794

reg = OS_REG_READ(ah,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

799

reg |= resetBB; /* Cold and warm reset the baseband bits */

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

805

reg &= regMask;

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

806

reg |= (resetBits | resetBB) ;

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

810

reg);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

817

reg &= regMask;

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

823

reg);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

849

reg = OS_REG_READ(ah,

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

854

reg |= resetBB; /* Cold and warm reset the baseband bits */

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

860

reg &= regMask;

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

861

reg |= (resetBits | resetBB) ;

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

865

reg);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

872

reg &= regMask;

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

878

reg);

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

74

uint32_t reg;

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

79

reg = OS_REG_READ(ah, gpioOffset+AR5315_GPIODO);

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

80

reg &= ~(1 << gpio);

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

81

reg |= (val&1) << gpio;

sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c

83

OS_REG_WRITE(ah, gpioOffset+AR5315_GPIODO, reg);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

124

reg = OS_REG_READ(ah, AR_GPIO_OE_OUT);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

125

reg &= ~(AR_GPIO_OE_OUT_DRV << gpio_shift);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

126

reg |= AR_GPIO_OE_OUT_DRV_ALL << gpio_shift;

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

127

OS_REG_WRITE(ah, AR_GPIO_OE_OUT, reg);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

139

uint32_t gpio_shift, reg;

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

149

reg = OS_REG_READ(ah, AR_GPIO_OE_OUT);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

150

reg &= ~(AR_GPIO_OE_OUT_DRV << gpio_shift);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

151

reg |= AR_GPIO_OE_OUT_DRV_ALL << gpio_shift;

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

152

OS_REG_WRITE(ah, AR_GPIO_OE_OUT, reg);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

163

uint32_t reg;

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

169

reg = OS_REG_READ(ah, AR_GPIO_IN_OUT);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

171

reg |= AR_GPIO_BIT(gpio);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

173

reg &= ~AR_GPIO_BIT(gpio);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

174

OS_REG_WRITE(ah, AR_GPIO_IN_OUT, reg);

sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c

86

uint32_t gpio_shift, reg;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

462

unsigned int reg;

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

463

reg = (OS_REG_READ(ah, AR_STA_ID1) | (1<<22));

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

464

OS_REG_WRITE(ah,AR_STA_ID1, reg);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

465

ath_hal_printf(ah, "MBSSID Set bit 22 of AR_STA_ID 0x%x\n", reg);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

534

uint32_t reg = HAL_INI_VAL(ia, i, 0);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

537

if (reg == AR_AN_TOP2 && AH5416(ah)->ah_need_an_top2_fixup)

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

540

OS_REG_WRITE(ah, reg, val);

sys/dev/ath/ath_hal/ar9002/ar9280_attach.c

543

if (reg >= 0x7800 && reg < 0x7900)

sys/dev/ath/if_ath.c

6355

ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg,

sys/dev/ath/if_ath.c

6364

__func__, reg->regdomain, reg->country, reg->location,

sys/dev/ath/if_ath.c

6365

reg->ecm ? " ecm" : "");

sys/dev/ath/if_ath.c

6368

reg->country, reg->regdomain);

sys/dev/atkbdc/psm.c

7101

elantech_read_1(KBDC kbdc, int hwversion, int reg, int *val)

sys/dev/atkbdc/psm.c

7112

res |= send_aux_command(kbdc, reg) != PSM_ACK;

sys/dev/atkbdc/psm.c

7122

elantech_write_1(KBDC kbdc, int hwversion, int reg, int val)

sys/dev/atkbdc/psm.c

7131

res |= send_aux_command(kbdc, reg) != PSM_ACK;

sys/dev/axgbe/if_axgbe_pci.c

317

axgbe_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/axgbe/if_axgbe_pci.c

323

axgbe_printf(3, "%s: phy %d reg %d\n", __func__, phy, reg);

sys/dev/axgbe/if_axgbe_pci.c

325

val = xgbe_phy_mii_read(pdata, phy, reg);

sys/dev/axgbe/if_axgbe_pci.c

332

axgbe_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/axgbe/if_axgbe_pci.c

337

axgbe_printf(3, "%s: phy %d reg %d val 0x%x\n", __func__, phy, reg, val);

sys/dev/axgbe/if_axgbe_pci.c

339

xgbe_phy_mii_write(pdata, phy, reg, val);

sys/dev/axgbe/if_axgbe_pci.c

402

unsigned int reg;

sys/dev/axgbe/if_axgbe_pci.c

461

reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);

sys/dev/axgbe/if_axgbe_pci.c

462

pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);

sys/dev/axgbe/if_axgbe_pci.c

464

pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);

sys/dev/axgbe/xgbe-dev.c

1003

unsigned int reg;

sys/dev/axgbe/xgbe-dev.c

1008

reg = XGMAC_IOREAD(pdata, MAC_GPIOSR);

sys/dev/axgbe/xgbe-dev.c

1010

reg |= (1 << (gpio + 16));

sys/dev/axgbe/xgbe-dev.c

1011

XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg);

sys/dev/axgbe/xgbe-dev.c

1164

xgbe_create_mdio_sca(int port, int reg)

sys/dev/axgbe/xgbe-dev.c

1168

da = (reg & MII_ADDR_C45) ? reg >> 16 : 0;

sys/dev/axgbe/xgbe-dev.c

1171

XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg);

sys/dev/axgbe/xgbe-dev.c

1179

xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, int reg,

sys/dev/axgbe/xgbe-dev.c

1186

mdio_sca = xgbe_create_mdio_sca(addr, reg);

sys/dev/axgbe/xgbe-dev.c

1207

xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, int reg)

sys/dev/axgbe/xgbe-dev.c

1213

mdio_sca = xgbe_create_mdio_sca(addr, reg);

sys/dev/axgbe/xgbe-dev.c

1956

unsigned int i, j, reg, reg_val;

sys/dev/axgbe/xgbe-dev.c

1985

reg = MAC_RQC2R;

sys/dev/axgbe/xgbe-dev.c

2006

XGMAC_IOWRITE(pdata, reg, reg_val);

sys/dev/axgbe/xgbe-dev.c

2007

reg += MAC_RQC2_INC;

sys/dev/axgbe/xgbe-dev.c

2012

reg = MTL_RQDCM0R;

sys/dev/axgbe/xgbe-dev.c

2020

XGMAC_IOWRITE(pdata, reg, reg_val);

sys/dev/axgbe/xgbe-dev.c

2022

reg += MTL_RQDCM_INC;

sys/dev/axgbe/xgbe-dev.c

491

unsigned int reg, reg_val;

sys/dev/axgbe/xgbe-dev.c

501

reg = MAC_Q0TFCR;

sys/dev/axgbe/xgbe-dev.c

503

reg_val = XGMAC_IOREAD(pdata, reg);

sys/dev/axgbe/xgbe-dev.c

505

XGMAC_IOWRITE(pdata, reg, reg_val);

sys/dev/axgbe/xgbe-dev.c

507

reg += MAC_QTFCR_INC;

sys/dev/axgbe/xgbe-dev.c

517

unsigned int reg, reg_val;

sys/dev/axgbe/xgbe-dev.c

539

reg = MAC_Q0TFCR;

sys/dev/axgbe/xgbe-dev.c

541

reg_val = XGMAC_IOREAD(pdata, reg);

sys/dev/axgbe/xgbe-dev.c

549

XGMAC_IOWRITE(pdata, reg, reg_val);

sys/dev/axgbe/xgbe-dev.c

551

reg += MAC_QTFCR_INC;

sys/dev/axgbe/xgbe-dev.c

987

unsigned int reg;

sys/dev/axgbe/xgbe-dev.c

992

reg = XGMAC_IOREAD(pdata, MAC_GPIOSR);

sys/dev/axgbe/xgbe-dev.c

994

reg &= ~(1 << (gpio + 16));

sys/dev/axgbe/xgbe-dev.c

995

XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg);

sys/dev/axgbe/xgbe-i2c.c

339

unsigned int reg;

sys/dev/axgbe/xgbe-i2c.c

341

reg = XI2C_IOREAD(pdata, IC_CON);

sys/dev/axgbe/xgbe-i2c.c

342

XI2C_SET_BITS(reg, IC_CON, MASTER_MODE, 1);

sys/dev/axgbe/xgbe-i2c.c

343

XI2C_SET_BITS(reg, IC_CON, SLAVE_DISABLE, 1);

sys/dev/axgbe/xgbe-i2c.c

344

XI2C_SET_BITS(reg, IC_CON, RESTART_EN, 1);

sys/dev/axgbe/xgbe-i2c.c

345

XI2C_SET_BITS(reg, IC_CON, SPEED, XGBE_STD_SPEED);

sys/dev/axgbe/xgbe-i2c.c

346

XI2C_SET_BITS(reg, IC_CON, RX_FIFO_FULL_HOLD, 1);

sys/dev/axgbe/xgbe-i2c.c

347

XI2C_IOWRITE(pdata, IC_CON, reg);

sys/dev/axgbe/xgbe-i2c.c

354

unsigned int reg;

sys/dev/axgbe/xgbe-i2c.c

356

reg = XI2C_IOREAD(pdata, IC_COMP_PARAM_1);

sys/dev/axgbe/xgbe-i2c.c

357

i2c->max_speed_mode = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,

sys/dev/axgbe/xgbe-i2c.c

359

i2c->rx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,

sys/dev/axgbe/xgbe-i2c.c

361

i2c->tx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,

sys/dev/axgbe/xgbe-mdio.c

1001

reg &= ~0x400;

sys/dev/axgbe/xgbe-mdio.c

1004

reg |= 0x800;

sys/dev/axgbe/xgbe-mdio.c

1006

reg &= ~0x800;

sys/dev/axgbe/xgbe-mdio.c

1009

reg &= ~XGBE_XNP_NP_EXCHANGE;

sys/dev/axgbe/xgbe-mdio.c

1011

XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);

sys/dev/axgbe/xgbe-mdio.c

1182

unsigned int reg = 0;

sys/dev/axgbe/xgbe-mdio.c

1209

reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK);

sys/dev/axgbe/xgbe-mdio.c

1211

set_mode, reg);

sys/dev/axgbe/xgbe-mdio.c

123

int reg;

sys/dev/axgbe/xgbe-mdio.c

125

reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);

sys/dev/axgbe/xgbe-mdio.c

1253

reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK);

sys/dev/axgbe/xgbe-mdio.c

126

reg &= ~XGBE_AN_CL37_INT_MASK;

sys/dev/axgbe/xgbe-mdio.c

1264

__func__, set_mode, reg, ret);

sys/dev/axgbe/xgbe-mdio.c

127

XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);

sys/dev/axgbe/xgbe-mdio.c

133

int reg;

sys/dev/axgbe/xgbe-mdio.c

135

reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);

sys/dev/axgbe/xgbe-mdio.c

136

reg &= ~XGBE_AN_CL37_INT_MASK;

sys/dev/axgbe/xgbe-mdio.c

137

XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);

sys/dev/axgbe/xgbe-mdio.c

139

reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);

sys/dev/axgbe/xgbe-mdio.c

140

reg &= ~XGBE_PCS_CL37_BP;

sys/dev/axgbe/xgbe-mdio.c

141

XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);

sys/dev/axgbe/xgbe-mdio.c

147

int reg;

sys/dev/axgbe/xgbe-mdio.c

149

reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);

sys/dev/axgbe/xgbe-mdio.c

150

reg |= XGBE_PCS_CL37_BP;

sys/dev/axgbe/xgbe-mdio.c

151

XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);

sys/dev/axgbe/xgbe-mdio.c

153

reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);

sys/dev/axgbe/xgbe-mdio.c

154

reg |= XGBE_AN_CL37_INT_MASK;

sys/dev/axgbe/xgbe-mdio.c

155

XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);

sys/dev/axgbe/xgbe-mdio.c

344

unsigned int reg;

sys/dev/axgbe/xgbe-mdio.c

346

reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1);

sys/dev/axgbe/xgbe-mdio.c

347

reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE;

sys/dev/axgbe/xgbe-mdio.c

350

reg |= MDIO_VEND2_CTRL1_AN_ENABLE;

sys/dev/axgbe/xgbe-mdio.c

353

reg |= MDIO_VEND2_CTRL1_AN_RESTART;

sys/dev/axgbe/xgbe-mdio.c

355

XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);

sys/dev/axgbe/xgbe-mdio.c

375

unsigned int reg;

sys/dev/axgbe/xgbe-mdio.c

378

reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);

sys/dev/axgbe/xgbe-mdio.c

379

reg &= ~XGBE_KR_TRAINING_ENABLE;

sys/dev/axgbe/xgbe-mdio.c

380

XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);

sys/dev/axgbe/xgbe-mdio.c

383

reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);

sys/dev/axgbe/xgbe-mdio.c

384

reg &= ~MDIO_AN_CTRL1_ENABLE;

sys/dev/axgbe/xgbe-mdio.c

387

reg |= MDIO_AN_CTRL1_ENABLE;

sys/dev/axgbe/xgbe-mdio.c

390

reg |= MDIO_AN_CTRL1_RESTART;

sys/dev/axgbe/xgbe-mdio.c

392

XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);

sys/dev/axgbe/xgbe-mdio.c

461

unsigned int ad_reg, lp_reg, reg;

sys/dev/axgbe/xgbe-mdio.c

473

reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);

sys/dev/axgbe/xgbe-mdio.c

474

reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE);

sys/dev/axgbe/xgbe-mdio.c

476

reg |= pdata->fec_ability;

sys/dev/axgbe/xgbe-mdio.c

478

XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);

sys/dev/axgbe/xgbe-mdio.c

485

reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);

sys/dev/axgbe/xgbe-mdio.c

486

reg |= XGBE_KR_TRAINING_ENABLE;

sys/dev/axgbe/xgbe-mdio.c

487

reg |= XGBE_KR_TRAINING_START;

sys/dev/axgbe/xgbe-mdio.c

488

XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);

sys/dev/axgbe/xgbe-mdio.c

517

unsigned int reg, ad_reg, lp_reg;

sys/dev/axgbe/xgbe-mdio.c

520

reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);

sys/dev/axgbe/xgbe-mdio.c

524

if (!(reg & link_support))

sys/dev/axgbe/xgbe-mdio.c

628

unsigned int reg;

sys/dev/axgbe/xgbe-mdio.c

634

reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);

sys/dev/axgbe/xgbe-mdio.c

635

pdata->an_int = reg & XGBE_AN_CL37_INT_MASK;

sys/dev/axgbe/xgbe-mdio.c

636

pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK;

sys/dev/axgbe/xgbe-mdio.c

640

reg &= ~XGBE_AN_CL37_INT_MASK;

sys/dev/axgbe/xgbe-mdio.c

641

XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);

sys/dev/axgbe/xgbe-mdio.c

909

unsigned int reg;

sys/dev/axgbe/xgbe-mdio.c

916

reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);

sys/dev/axgbe/xgbe-mdio.c

918

reg |= 0x100;

sys/dev/axgbe/xgbe-mdio.c

920

reg &= ~0x100;

sys/dev/axgbe/xgbe-mdio.c

923

reg |= 0x80;

sys/dev/axgbe/xgbe-mdio.c

925

reg &= ~0x80;

sys/dev/axgbe/xgbe-mdio.c

928

reg |= XGBE_AN_CL37_FD_MASK;

sys/dev/axgbe/xgbe-mdio.c

929

reg &= ~XGBE_AN_CL37_HD_MASK;

sys/dev/axgbe/xgbe-mdio.c

931

axgbe_printf(2, "%s: Writing reg: 0x%x\n", __func__, reg);

sys/dev/axgbe/xgbe-mdio.c

932

XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg);

sys/dev/axgbe/xgbe-mdio.c

935

reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);

sys/dev/axgbe/xgbe-mdio.c

937

reg, pdata->an_mode);

sys/dev/axgbe/xgbe-mdio.c

938

reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK;

sys/dev/axgbe/xgbe-mdio.c

939

reg &= ~XGBE_AN_CL37_PCS_MODE_MASK;

sys/dev/axgbe/xgbe-mdio.c

943

reg |= XGBE_AN_CL37_PCS_MODE_BASEX;

sys/dev/axgbe/xgbe-mdio.c

946

reg |= XGBE_AN_CL37_PCS_MODE_SGMII;

sys/dev/axgbe/xgbe-mdio.c

952

reg |= XGBE_AN_CL37_MII_CTRL_8BIT;

sys/dev/axgbe/xgbe-mdio.c

953

axgbe_printf(2, "%s: Writing reg: 0x%x\n", __func__, reg);

sys/dev/axgbe/xgbe-mdio.c

954

XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);

sys/dev/axgbe/xgbe-mdio.c

968

unsigned int reg;

sys/dev/axgbe/xgbe-mdio.c

973

reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);

sys/dev/axgbe/xgbe-mdio.c

975

reg |= 0xc000;

sys/dev/axgbe/xgbe-mdio.c

977

reg &= ~0xc000;

sys/dev/axgbe/xgbe-mdio.c

979

XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);

sys/dev/axgbe/xgbe-mdio.c

982

reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);

sys/dev/axgbe/xgbe-mdio.c

984

reg |= 0x80;

sys/dev/axgbe/xgbe-mdio.c

986

reg &= ~0x80;

sys/dev/axgbe/xgbe-mdio.c

990

reg |= 0x20;

sys/dev/axgbe/xgbe-mdio.c

992

reg &= ~0x20;

sys/dev/axgbe/xgbe-mdio.c

994

XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);

sys/dev/axgbe/xgbe-mdio.c

997

reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);

sys/dev/axgbe/xgbe-mdio.c

999

reg |= 0x400;

sys/dev/axgbe/xgbe-phy-v1.c

249

unsigned int reg;

sys/dev/axgbe/xgbe-phy-v1.c

251

reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);

sys/dev/axgbe/xgbe-phy-v1.c

253

reg |= MDIO_CTRL1_LPOWER;

sys/dev/axgbe/xgbe-phy-v1.c

254

XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);

sys/dev/axgbe/xgbe-phy-v1.c

258

reg &= ~MDIO_CTRL1_LPOWER;

sys/dev/axgbe/xgbe-phy-v1.c

259

XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);

sys/dev/axgbe/xgbe-phy-v1.c

301

unsigned int reg;

sys/dev/axgbe/xgbe-phy-v1.c

304

reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);

sys/dev/axgbe/xgbe-phy-v1.c

305

reg &= ~MDIO_PCS_CTRL2_TYPE;

sys/dev/axgbe/xgbe-phy-v1.c

306

reg |= MDIO_PCS_CTRL2_10GBR;

sys/dev/axgbe/xgbe-phy-v1.c

307

XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);

sys/dev/axgbe/xgbe-phy-v1.c

309

reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);

sys/dev/axgbe/xgbe-phy-v1.c

310

reg &= ~MDIO_CTRL1_SPEEDSEL;

sys/dev/axgbe/xgbe-phy-v1.c

311

reg |= MDIO_CTRL1_SPEED10G;

sys/dev/axgbe/xgbe-phy-v1.c

312

XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);

sys/dev/axgbe/xgbe-phy-v1.c

345

unsigned int reg;

sys/dev/axgbe/xgbe-phy-v1.c

348

reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);

sys/dev/axgbe/xgbe-phy-v1.c

349

reg &= ~MDIO_PCS_CTRL2_TYPE;

sys/dev/axgbe/xgbe-phy-v1.c

350

reg |= MDIO_PCS_CTRL2_10GBX;

sys/dev/axgbe/xgbe-phy-v1.c

351

XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);

sys/dev/axgbe/xgbe-phy-v1.c

353

reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);

sys/dev/axgbe/xgbe-phy-v1.c

354

reg &= ~MDIO_CTRL1_SPEEDSEL;

sys/dev/axgbe/xgbe-phy-v1.c

355

reg |= MDIO_CTRL1_SPEED1G;

sys/dev/axgbe/xgbe-phy-v1.c

356

XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);

sys/dev/axgbe/xgbe-phy-v1.c

389

unsigned int reg;

sys/dev/axgbe/xgbe-phy-v1.c

392

reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);

sys/dev/axgbe/xgbe-phy-v1.c

393

reg &= ~MDIO_PCS_CTRL2_TYPE;

sys/dev/axgbe/xgbe-phy-v1.c

394

reg |= MDIO_PCS_CTRL2_10GBX;

sys/dev/axgbe/xgbe-phy-v1.c

395

XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);

sys/dev/axgbe/xgbe-phy-v1.c

397

reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);

sys/dev/axgbe/xgbe-phy-v1.c

398

reg &= ~MDIO_CTRL1_SPEEDSEL;

sys/dev/axgbe/xgbe-phy-v1.c

399

reg |= MDIO_CTRL1_SPEED1G;

sys/dev/axgbe/xgbe-phy-v1.c

400

XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);

sys/dev/axgbe/xgbe-phy-v1.c

434

unsigned int reg;

sys/dev/axgbe/xgbe-phy-v1.c

436

reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);

sys/dev/axgbe/xgbe-phy-v1.c

437

reg &= MDIO_PCS_CTRL2_TYPE;

sys/dev/axgbe/xgbe-phy-v1.c

439

if (reg == MDIO_PCS_CTRL2_10GBR) {

sys/dev/axgbe/xgbe-phy-v1.c

587

unsigned int reg;

sys/dev/axgbe/xgbe-phy-v1.c

594

reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);

sys/dev/axgbe/xgbe-phy-v1.c

595

reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);

sys/dev/axgbe/xgbe-phy-v1.c

597

return ((reg & MDIO_STAT1_LSTATUS) ? 1 : 0);

sys/dev/axgbe/xgbe-phy-v1.c

616

unsigned int reg, count;

sys/dev/axgbe/xgbe-phy-v1.c

619

reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);

sys/dev/axgbe/xgbe-phy-v1.c

620

reg |= MDIO_CTRL1_RESET;

sys/dev/axgbe/xgbe-phy-v1.c

621

XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);

sys/dev/axgbe/xgbe-phy-v1.c

626

reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);

sys/dev/axgbe/xgbe-phy-v1.c

627

} while ((reg & MDIO_CTRL1_RESET) && --count);

sys/dev/axgbe/xgbe-phy-v1.c

629

if (reg & MDIO_CTRL1_RESET)

sys/dev/axgbe/xgbe-phy-v2.c

1001

reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);

sys/dev/axgbe/xgbe-phy-v2.c

1002

reg &= 0x03ff;

sys/dev/axgbe/xgbe-phy-v2.c

1003

reg &= ~0x0001;

sys/dev/axgbe/xgbe-phy-v2.c

1005

reg | 0x0001);

sys/dev/axgbe/xgbe-phy-v2.c

1008

reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);

sys/dev/axgbe/xgbe-phy-v2.c

1009

xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg | 0x00800);

sys/dev/axgbe/xgbe-phy-v2.c

1013

reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);

sys/dev/axgbe/xgbe-phy-v2.c

1014

reg &= 0x03ff;

sys/dev/axgbe/xgbe-phy-v2.c

1015

reg &= ~0x0006;

sys/dev/axgbe/xgbe-phy-v2.c

1017

reg | 0x0004);

sys/dev/axgbe/xgbe-phy-v2.c

1020

reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);

sys/dev/axgbe/xgbe-phy-v2.c

1021

xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800);

sys/dev/axgbe/xgbe-phy-v2.c

1025

reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);

sys/dev/axgbe/xgbe-phy-v2.c

1026

reg &= 0x03ff;

sys/dev/axgbe/xgbe-phy-v2.c

1027

reg &= ~0x0001;

sys/dev/axgbe/xgbe-phy-v2.c

1029

reg);

sys/dev/axgbe/xgbe-phy-v2.c

1032

reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);

sys/dev/axgbe/xgbe-phy-v2.c

1033

xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800);

sys/dev/axgbe/xgbe-phy-v2.c

2249

int reg;

sys/dev/axgbe/xgbe-phy-v2.c

2251

reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,

sys/dev/axgbe/xgbe-phy-v2.c

2254

if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {

sys/dev/axgbe/xgbe-phy-v2.c

2950

int reg;

sys/dev/axgbe/xgbe-phy-v2.c

2953

reg = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR);

sys/dev/axgbe/xgbe-phy-v2.c

2954

reg = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR);

sys/dev/axgbe/xgbe-phy-v2.c

2955

if (reg < 0)

sys/dev/axgbe/xgbe-phy-v2.c

2956

return (reg);

sys/dev/axgbe/xgbe-phy-v2.c

2958

if ((reg & BMSR_LINK) == 0)

sys/dev/axgbe/xgbe-phy-v2.c

2963

axgbe_printf(2, "Link: %d updated reg %#x\n", pdata->phy.link, reg);

sys/dev/axgbe/xgbe-phy-v2.c

3104

unsigned int reg;

sys/dev/axgbe/xgbe-phy-v2.c

3168

reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);

sys/dev/axgbe/xgbe-phy-v2.c

3169

reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);

sys/dev/axgbe/xgbe-phy-v2.c

3170

axgbe_printf(1, "%s: link_status reg: 0x%x\n", __func__, reg);

sys/dev/axgbe/xgbe-phy-v2.c

3171

if (reg & MDIO_STAT1_LSTATUS)

sys/dev/axgbe/xgbe-phy-v2.c

433

xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,

sys/dev/axgbe/xgbe-phy-v2.c

444

redrv_data[0] = ((reg >> 8) & 0xff) << 1;

sys/dev/axgbe/xgbe-phy-v2.c

445

redrv_data[1] = reg & 0xff;

sys/dev/axgbe/xgbe-phy-v2.c

516

xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, void *reg,

sys/dev/axgbe/xgbe-phy-v2.c

530

i2c_op.buf = reg;

sys/dev/axgbe/xgbe-phy-v2.c

647

xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr, int reg,

sys/dev/axgbe/xgbe-phy-v2.c

652

if (reg & MII_ADDR_C45) {

sys/dev/axgbe/xgbe-phy-v2.c

660

return (pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val));

sys/dev/axgbe/xgbe-phy-v2.c

664

xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, uint16_t val)

sys/dev/axgbe/xgbe-phy-v2.c

674

mii_data[0] = reg & 0xff;

sys/dev/axgbe/xgbe-phy-v2.c

687

xgbe_phy_mii_write(struct xgbe_prv_data *pdata, int addr, int reg, uint16_t val)

sys/dev/axgbe/xgbe-phy-v2.c

692

axgbe_printf(3, "%s: addr %d reg %d val %#x\n", __func__, addr, reg, val);

sys/dev/axgbe/xgbe-phy-v2.c

698

ret = xgbe_phy_i2c_mii_write(pdata, reg, val);

sys/dev/axgbe/xgbe-phy-v2.c

700

ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);

sys/dev/axgbe/xgbe-phy-v2.c

710

xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr, int reg)

sys/dev/axgbe/xgbe-phy-v2.c

714

if (reg & MII_ADDR_C45) {

sys/dev/axgbe/xgbe-phy-v2.c

722

return (pdata->hw_if.read_ext_mii_regs(pdata, addr, reg));

sys/dev/axgbe/xgbe-phy-v2.c

726

xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)

sys/dev/axgbe/xgbe-phy-v2.c

736

mii_reg = reg;

sys/dev/axgbe/xgbe-phy-v2.c

749

xgbe_phy_mii_read(struct xgbe_prv_data *pdata, int addr, int reg)

sys/dev/axgbe/xgbe-phy-v2.c

754

axgbe_printf(3, "%s: addr %d reg %d\n", __func__, addr, reg);

sys/dev/axgbe/xgbe-phy-v2.c

760

ret = xgbe_phy_i2c_mii_read(pdata, reg);

sys/dev/axgbe/xgbe-phy-v2.c

762

ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);

sys/dev/axgbe/xgbe-phy-v2.c

975

int reg;

sys/dev/axgbe/xgbe-phy-v2.c

996

reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x18);

sys/dev/axgbe/xgbe-phy-v2.c

997

xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, reg & ~0x0080);

sys/dev/axgbe/xgbe-sysctl.c

1234

unsigned int reg;

sys/dev/axgbe/xgbe-sysctl.c

1255

sscanf(buf, "%x", &reg);

sys/dev/axgbe/xgbe-sysctl.c

1256

axgbe_printf(2, "WRITE: %s: mmd_reg: 0x%x\n", __func__, reg);

sys/dev/axgbe/xgbe-sysctl.c

1257

pdata->sysctl_xpcs_mmd = reg;

sys/dev/axgbe/xgbe-sysctl.c

1271

unsigned int reg;

sys/dev/axgbe/xgbe-sysctl.c

1292

sscanf(buf, "%x", &reg);

sys/dev/axgbe/xgbe-sysctl.c

1293

axgbe_printf(2, "WRITE: %s: reg: 0x%x\n", __func__, reg);

sys/dev/axgbe/xgbe-sysctl.c

1294

pdata->sysctl_xpcs_reg = reg;

sys/dev/axgbe/xgbe-sysctl.c

1346

unsigned int reg;

sys/dev/axgbe/xgbe-sysctl.c

1367

sscanf(buf, "%x", &reg);

sys/dev/axgbe/xgbe-sysctl.c

1368

axgbe_printf(2, "WRITE: %s: reg: 0x%x\n", __func__, reg);

sys/dev/axgbe/xgbe-sysctl.c

1369

pdata->sysctl_xprop_reg = reg;

sys/dev/axgbe/xgbe-sysctl.c

1419

unsigned int reg;

sys/dev/axgbe/xgbe-sysctl.c

1440

sscanf(buf, "%x", &reg);

sys/dev/axgbe/xgbe-sysctl.c

1441

axgbe_printf(2, "WRITE: %s: reg: 0x%x\n", __func__, reg);

sys/dev/axgbe/xgbe-sysctl.c

1442

pdata->sysctl_xi2c_reg = reg;

sys/dev/axgbe/xgbe-sysctl.c

493

unsigned int reg;

sys/dev/axgbe/xgbe-sysctl.c

514

sscanf(buf, "%x", &reg);

sys/dev/axgbe/xgbe-sysctl.c

515

axgbe_printf(2, "WRITE: %s: reg: 0x%x\n", __func__, reg);

sys/dev/axgbe/xgbe-sysctl.c

516

pdata->sysctl_xgmac_reg = reg;

sys/dev/axgbe/xgbe.h

1332

int xgbe_phy_mii_write(struct xgbe_prv_data *pdata, int addr, int reg,

sys/dev/axgbe/xgbe.h

1334

int xgbe_phy_mii_read(struct xgbe_prv_data *pdata, int addr, int reg);

sys/dev/bce/if_bce.c

1823

bce_miibus_read_reg(device_t dev, int phy, int reg)

sys/dev/bce/if_bce.c

1837

if (reg >= MII_BMCR && reg <= MII_ANLPRNP)

sys/dev/bce/if_bce.c

1838

reg += 0x10;

sys/dev/bce/if_bce.c

1851

val = BCE_MIPHY(phy) | BCE_MIREG(reg) |

sys/dev/bce/if_bce.c

1872

"reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);

sys/dev/bce/if_bce.c

1888

DB_PRINT_PHY_REG(reg, val);

sys/dev/bce/if_bce.c

1901

bce_miibus_write_reg(device_t dev, int phy, int reg, int val)

sys/dev/bce/if_bce.c

1909

DB_PRINT_PHY_REG(reg, val);

sys/dev/bce/if_bce.c

1917

if (reg >= MII_BMCR && reg <= MII_ANLPRNP)

sys/dev/bce/if_bce.c

1918

reg += 0x10;

sys/dev/bce/if_bce.c

1931

val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |

sys/dev/bce/if_bce.c

5084

u32 reg, val;

sys/dev/bce/if_bce.c

5183

reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);

sys/dev/bce/if_bce.c

5188

reg = 0);

sys/dev/bce/if_bce.c

5190

if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=

sys/dev/bce/if_bce.c

5194

(reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK),

sys/dev/bce/if_bce.c

810

u32 reg;

sys/dev/bce/if_bce.c

815

if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0) {

sys/dev/bce/if_bce.c

816

if (reg != 0)

sys/dev/bce/if_bce.c

821

if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {

sys/dev/bce/if_bce.c

822

if (reg != 0) {

sys/dev/bce/if_bce.c

823

u16 link_status = pci_read_config(dev, reg + 0x12, 2);

sys/dev/bce/if_bce.c

834

if (pci_find_cap(dev, PCIY_MSI, &reg) == 0) {

sys/dev/bce/if_bce.c

835

if (reg != 0)

sys/dev/bce/if_bce.c

840

if (pci_find_cap(dev, PCIY_MSIX, &reg) == 0) {

sys/dev/bce/if_bce.c

841

if (reg != 0)

sys/dev/bce/if_bcereg.h

1070

#define BCE_SETBIT(sc, reg, x) \

sys/dev/bce/if_bcereg.h

1071

REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))

sys/dev/bce/if_bcereg.h

1072

#define BCE_CLRBIT(sc, reg, x) \

sys/dev/bce/if_bcereg.h

1073

REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))

sys/dev/bce/if_bcereg.h

1074

#define PCI_SETBIT(dev, reg, x, s) \

sys/dev/bce/if_bcereg.h

1075

pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)

sys/dev/bce/if_bcereg.h

1076

#define PCI_CLRBIT(dev, reg, x, s) \

sys/dev/bce/if_bcereg.h

1077

pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)

sys/dev/bce/if_bcereg.h

429

#define DB_PRINT_PHY_REG(reg, val) \

sys/dev/bce/if_bcereg.h

430

switch(reg) { \

sys/dev/bce/if_bcereg.h

433

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \

sys/dev/bce/if_bcereg.h

437

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \

sys/dev/bce/if_bcereg.h

441

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \

sys/dev/bce/if_bcereg.h

445

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \

sys/dev/bce/if_bcereg.h

449

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \

sys/dev/bce/if_bcereg.h

453

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \

sys/dev/bce/if_bcereg.h

457

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \

sys/dev/bce/if_bcereg.h

461

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \

sys/dev/bce/if_bcereg.h

465

__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff); \

sys/dev/bce/if_bcereg.h

486

#define DB_PRINT_PHY_REG(reg, val)

sys/dev/bfe/if_bfe.c

1157

bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,

sys/dev/bfe/if_bfe.c

1163

u_int32_t val = CSR_READ_4(sc, reg);

sys/dev/bfe/if_bfe.c

1174

"%x to %s.\n", bit, reg, (clear ? "clear" : "set"));

sys/dev/bfe/if_bfe.c

1181

bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)

sys/dev/bfe/if_bfe.c

1190

(reg << BFE_MDIO_RA_SHIFT) |

sys/dev/bfe/if_bfe.c

1199

bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val)

sys/dev/bfe/if_bfe.c

1207

(reg << BFE_MDIO_RA_SHIFT) |

sys/dev/bfe/if_bfe.c

1242

uint32_t reg, *val;

sys/dev/bfe/if_bfe.c

1248

for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)

sys/dev/bfe/if_bfe.c

1249

*val++ = CSR_READ_4(sc, reg);

sys/dev/bfe/if_bfe.c

1250

for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)

sys/dev/bfe/if_bfe.c

1251

*val++ = CSR_READ_4(sc, reg);

sys/dev/bfe/if_bfe.c

615

bfe_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/bfe/if_bfe.c

621

bfe_readphy(sc, reg, &ret);

sys/dev/bfe/if_bfe.c

627

bfe_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/bfe/if_bfe.c

632

bfe_writephy(sc, reg, val);

sys/dev/bfe/if_bfe.c

873

uint32_t reg;

sys/dev/bfe/if_bfe.c

878

for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)

sys/dev/bfe/if_bfe.c

879

CSR_READ_4(sc, reg);

sys/dev/bfe/if_bfe.c

880

for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)

sys/dev/bfe/if_bfe.c

881

CSR_READ_4(sc, reg);

sys/dev/bfe/if_bfereg.h

426

#define PCI_SETBIT(dev, reg, x, s) \

sys/dev/bfe/if_bfereg.h

427

pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)

sys/dev/bfe/if_bfereg.h

428

#define PCI_CLRBIT(dev, reg, x, s) \

sys/dev/bfe/if_bfereg.h

429

pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)

sys/dev/bfe/if_bfereg.h

444

#define CSR_READ_4(sc, reg) bus_read_4(sc->bfe_res, reg)

sys/dev/bfe/if_bfereg.h

446

#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->bfe_res, reg, val)

sys/dev/bge/if_bge.c

1094

bge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/bge/if_bge.c

1113

BGE_MIPHY(phy) | BGE_MIREG(reg));

sys/dev/bge/if_bge.c

1129

phy, reg, val);

sys/dev/bge/if_bge.c

1148

bge_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/bge/if_bge.c

1156

(reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))

sys/dev/bge/if_bge.c

1170

BGE_MIPHY(phy) | BGE_MIREG(reg) | val);

sys/dev/bge/if_bge.c

1192

phy, reg, val);

sys/dev/bge/if_bge.c

3295

int capmask, error, reg, rid, trys;

sys/dev/bge/if_bge.c

3564

if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {

sys/dev/bge/if_bge.c

3570

sc->bge_expcap = reg;

sys/dev/bge/if_bge.c

3586

if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0)

sys/dev/bge/if_bge.c

3587

sc->bge_pcixcap = reg;

sys/dev/bge/if_bge.c

3616

if (pci_find_cap(sc->bge_dev, PCIY_MSI, &reg) == 0) {

sys/dev/bge/if_bge.c

3617

sc->bge_msicap = reg;

sys/dev/bge/if_bge.c

3618

reg = 1;

sys/dev/bge/if_bge.c

3619

if (bge_can_use_msi(sc) && pci_alloc_msi(dev, &reg) == 0) {

sys/dev/bge/if_bge.c

5945

bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)

sys/dev/bge/if_bge.c

5949

BGE_CLRBIT(sc, reg, bit);

sys/dev/bge/if_bge.c

5952

if ((CSR_READ_4(sc, reg) & bit) == 0)

sys/dev/bge/if_bgereg.h

2803

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/bge/if_bgereg.h

2804

bus_write_4(sc->bge_res, reg, val)

sys/dev/bge/if_bgereg.h

2806

#define CSR_READ_4(sc, reg) \

sys/dev/bge/if_bgereg.h

2807

bus_read_4(sc->bge_res, reg)

sys/dev/bge/if_bgereg.h

2809

#define BGE_SETBIT(sc, reg, x) \

sys/dev/bge/if_bgereg.h

2810

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))

sys/dev/bge/if_bgereg.h

2811

#define BGE_CLRBIT(sc, reg, x) \

sys/dev/bge/if_bgereg.h

2812

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))

sys/dev/bge/if_bgereg.h

2815

#define APE_WRITE_4(sc, reg, val) \

sys/dev/bge/if_bgereg.h

2816

bus_write_4(sc->bge_res2, reg, val)

sys/dev/bge/if_bgereg.h

2818

#define APE_READ_4(sc, reg) \

sys/dev/bge/if_bgereg.h

2819

bus_read_4(sc->bge_res2, reg)

sys/dev/bge/if_bgereg.h

2821

#define APE_SETBIT(sc, reg, x) \

sys/dev/bge/if_bgereg.h

2822

APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x)))

sys/dev/bge/if_bgereg.h

2823

#define APE_CLRBIT(sc, reg, x) \

sys/dev/bge/if_bgereg.h

2824

APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x)))

sys/dev/bge/if_bgereg.h

2826

#define PCI_SETBIT(dev, reg, x, s) \

sys/dev/bge/if_bgereg.h

2827

pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)

sys/dev/bge/if_bgereg.h

2828

#define PCI_CLRBIT(dev, reg, x, s) \

sys/dev/bge/if_bgereg.h

2829

pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)

sys/dev/bge/if_bgereg.h

2934

int reg;

sys/dev/bhnd/bhndb/bhndb_pci.c

1022

int reg;

sys/dev/bhnd/bhndb/bhndb_pci.c

1024

if (pci_find_cap(device_get_parent(dev), PCIY_EXPRESS, &reg) == 0)

sys/dev/bhnd/bhndb/bhndb_pci.c

900

int reg;

sys/dev/bhnd/bhndb/bhndb_pci.c

905

reg = rw->d.dyn.cfg_offset;

sys/dev/bhnd/bhndb/bhndb_pci.c

910

if (pci_read_config(pci_dev, reg, 4) == addr)

sys/dev/bhnd/bhndb/bhndb_subr.c

1070

struct bhndb_region *reg;

sys/dev/bhnd/bhndb/bhndb_subr.c

1073

reg = malloc(sizeof(*reg), M_BHND, M_NOWAIT);

sys/dev/bhnd/bhndb/bhndb_subr.c

1074

if (reg == NULL)

sys/dev/bhnd/bhndb/bhndb_subr.c

1077

*reg = (struct bhndb_region) {

sys/dev/bhnd/bhndb/bhndb_subr.c

1085

STAILQ_INSERT_HEAD(&br->bus_regions, reg, link);

sys/dev/bhnd/cores/chipc/chipc_gpio.c

581

struct chipc_gpio_reg *reg)

sys/dev/bhnd/cores/chipc/chipc_gpio.c

587

if (reg->mask == 0)

sys/dev/bhnd/cores/chipc/chipc_gpio.c

591

value &= ~reg->mask;

sys/dev/bhnd/cores/chipc/chipc_gpio.c

592

value |= reg->value;

sys/dev/bhnd/cores/chipc/chipc_spi.h

83

#define SPI_WRITE(sc, reg, val) bus_write_4(sc->sc_res, (reg), (val));

sys/dev/bhnd/cores/chipc/chipc_spi.h

85

#define SPI_READ(sc, reg) bus_read_4(sc->sc_res, (reg))

sys/dev/bhnd/cores/chipc/chipc_spi.h

87

#define SPI_SET_BITS(sc, reg, bits) \

sys/dev/bhnd/cores/chipc/chipc_spi.h

88

SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits))

sys/dev/bhnd/cores/chipc/chipc_spi.h

90

#define SPI_CLEAR_BITS(sc, reg, bits) \

sys/dev/bhnd/cores/chipc/chipc_spi.h

91

SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits))

sys/dev/bhnd/cores/pci/bhnd_pci.c

371

bhnd_pcie_mdio_read(struct bhnd_pci_softc *sc, int phy, int reg)

sys/dev/bhnd/cores/pci/bhnd_pci.c

382

cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg);

sys/dev/bhnd/cores/pci/bhnd_pci.c

396

bhnd_pcie_mdio_write(struct bhnd_pci_softc *sc, int phy, int reg, int val)

sys/dev/bhnd/cores/pci/bhnd_pci.c

406

cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg) | (val & BHND_PCIE_MDIODATA_DATA_MASK);

sys/dev/bhnd/cores/pci/bhnd_pci.c

418

int reg)

sys/dev/bhnd/cores/pci/bhnd_pci.c

425

return (bhnd_pcie_mdio_read(sc, phy, reg));

sys/dev/bhnd/cores/pci/bhnd_pci.c

445

cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg);

sys/dev/bhnd/cores/pci/bhnd_pci.c

460

int reg, int val)

sys/dev/bhnd/cores/pci/bhnd_pci.c

466

return (bhnd_pcie_mdio_write(sc, phy, reg, val));

sys/dev/bhnd/cores/pci/bhnd_pci.c

486

cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg) |

sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c

506

bus_size_t reg;

sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c

510

reg = BHND_PCIE_SPROM_SHADOW + BHND_PCIE_SRSH_ASPM_OFFSET;

sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c

511

cfg = BHND_PCI_READ_2(sc, reg);

sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c

518

BHND_PCI_WRITE_2(sc, reg, cfg);

sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c

533

reg = BHND_PCIE_SPROM_SHADOW + BHND_PCIE_SRSH_CLKREQ_OFFSET_R5;

sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c

534

cfg = BHND_PCI_READ_2(sc, reg);

sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c

541

BHND_PCI_WRITE_2(sc, reg, cfg);

sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c

546

bus_size_t reg;

sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c

550

reg = BHND_PCIE_SPROM_SHADOW + BHND_PCIE_SRSH_PCIE_MISC_CONFIG;

sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c

551

cfg = BHND_PCI_READ_2(sc, reg);

sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c

556

BHND_PCI_WRITE_2(sc, reg, cfg);

sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c

563

bus_size_t reg;

sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c

574

reg = BHND_PCIE_SPROM_SHADOW + BHND_PCIE_SRSH_BD_OFFSET;

sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c

575

BHND_PCI_WRITE_2(sc, reg, 0);

sys/dev/bhnd/cores/pci/bhnd_pcivar.h

57

int reg);

sys/dev/bhnd/cores/pci/bhnd_pcivar.h

59

int reg, int val);

sys/dev/bhnd/cores/pci/bhnd_pcivar.h

61

int devaddr, int reg);

sys/dev/bhnd/cores/pci/bhnd_pcivar.h

63

int devaddr, int reg, int val);

sys/dev/bhnd/cores/pcie2/bhnd_pcie2.c

222

bhnd_pcie2_mdio_read(struct bhnd_pcie2_softc *sc, int phy, int reg)

sys/dev/bhnd/cores/pcie2/bhnd_pcie2.c

229

bhnd_pcie2_mdio_write(struct bhnd_pcie2_softc *sc, int phy, int reg, int val)

sys/dev/bhnd/cores/pcie2/bhnd_pcie2.c

237

int reg)

sys/dev/bhnd/cores/pcie2/bhnd_pcie2.c

245

int reg, int val)

sys/dev/bhnd/cores/pcie2/bhnd_pcie2_var.h

57

int reg);

sys/dev/bhnd/cores/pcie2/bhnd_pcie2_var.h

59

int reg, int val);

sys/dev/bhnd/cores/pcie2/bhnd_pcie2_var.h

61

int devaddr, int reg);

sys/dev/bhnd/cores/pcie2/bhnd_pcie2_var.h

63

int phy, int devaddr, int reg, int val);

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

317

bhnd_pmu_read_chipctrl_method(device_t dev, uint32_t reg)

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

325

rval = BHND_PMU_CCTRL_READ(sc, reg);

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

335

bhnd_pmu_write_chipctrl_method(device_t dev, uint32_t reg, uint32_t value,

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

341

BHND_PMU_CCTRL_WRITE(sc, reg, value, mask);

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

349

bhnd_pmu_read_regctrl_method(device_t dev, uint32_t reg)

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

357

rval = BHND_PMU_REGCTRL_READ(sc, reg);

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

367

bhnd_pmu_write_regctrl_method(device_t dev, uint32_t reg, uint32_t value,

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

373

BHND_PMU_REGCTRL_WRITE(sc, reg, value, mask);

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

381

bhnd_pmu_read_pllctrl_method(device_t dev, uint32_t reg)

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

389

rval = BHND_PMU_PLL_READ(sc, reg);

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

399

bhnd_pmu_write_pllctrl_method(device_t dev, uint32_t reg, uint32_t value,

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

405

BHND_PMU_PLL_WRITE(sc, reg, value, mask);

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

577

bhnd_pmu_read_4(bus_size_t reg, void *ctx)

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

580

return (bhnd_bus_read_4(sc->res, reg));

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

585

bhnd_pmu_write_4(bus_size_t reg, uint32_t val, void *ctx)

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

588

return (bhnd_bus_write_4(sc->res, reg, val));

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

75

static uint32_t bhnd_pmu_read_4(bus_size_t reg, void *ctx);

sys/dev/bhnd/cores/pmu/bhnd_pmu.c

76

static void bhnd_pmu_write_4(bus_size_t reg, uint32_t val, void *ctx);

sys/dev/bhnd/cores/pmu/bhnd_pmu.h

111

bhnd_pmu_write_regctrl(device_t dev, uint32_t reg, uint32_t value,

sys/dev/bhnd/cores/pmu/bhnd_pmu.h

114

return (BHND_PMU_WRITE_REGCTRL(dev, reg, value, mask));

sys/dev/bhnd/cores/pmu/bhnd_pmu.h

129

bhnd_pmu_read_pllctrl(device_t dev, uint32_t reg)

sys/dev/bhnd/cores/pmu/bhnd_pmu.h

131

return (BHND_PMU_READ_PLLCTRL(dev, reg));

sys/dev/bhnd/cores/pmu/bhnd_pmu.h

146

bhnd_pmu_write_pllctrl(device_t dev, uint32_t reg, uint32_t value,

sys/dev/bhnd/cores/pmu/bhnd_pmu.h

149

return (BHND_PMU_WRITE_PLLCTRL(dev, reg, value, mask));

sys/dev/bhnd/cores/pmu/bhnd_pmu.h

59

bhnd_pmu_read_chipctrl(device_t dev, uint32_t reg)

sys/dev/bhnd/cores/pmu/bhnd_pmu.h

61

return (BHND_PMU_READ_CHIPCTRL(dev, reg));

sys/dev/bhnd/cores/pmu/bhnd_pmu.h

76

bhnd_pmu_write_chipctrl(device_t dev, uint32_t reg, uint32_t value,

sys/dev/bhnd/cores/pmu/bhnd_pmu.h

79

return (BHND_PMU_WRITE_CHIPCTRL(dev, reg, value, mask));

sys/dev/bhnd/cores/pmu/bhnd_pmu.h

94

bhnd_pmu_read_regctrl(device_t dev, uint32_t reg)

sys/dev/bhnd/cores/pmu/bhnd_pmu.h

96

return (BHND_PMU_READ_REGCTRL(dev, reg));

sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h

95

bus_size_t addr, bus_size_t data, uint32_t reg);

sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h

97

bus_size_t addr, bus_size_t data, uint32_t reg,

sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c

149

bus_size_t data, uint32_t reg)

sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c

151

io->wr4(addr, reg, io_ctx);

sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c

166

bus_size_t data, uint32_t reg, uint32_t val, uint32_t mask)

sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c

170

io->wr4(addr, reg, io_ctx);

sys/dev/bhnd/cores/pmu/bhnd_pmuvar.h

85

uint32_t (*rd4)(bus_size_t reg, void *ctx);

sys/dev/bhnd/cores/pmu/bhnd_pmuvar.h

88

void (*wr4)(bus_size_t reg, uint32_t val, void *ctx);

sys/dev/bhnd/siba/siba_subr.c

668

bus_size_t reg, uint32_t value, uint32_t mask)

sys/dev/bhnd/siba/siba_subr.c

677

KASSERT(reg <= SIBA_CFG_SIZE-4, ("%s invalid CFG0 register offset %#jx",

sys/dev/bhnd/siba/siba_subr.c

678

device_get_nameunit(dev), (uintmax_t)reg));

sys/dev/bhnd/siba/siba_subr.c

680

rval = bhnd_bus_read_4(r, reg);

sys/dev/bhnd/siba/siba_subr.c

684

bhnd_bus_write_4(r, reg, rval);

sys/dev/bhnd/siba/siba_subr.c

685

bhnd_bus_read_4(r, reg); /* read-back */

sys/dev/bhnd/siba/siba_subr.c

707

siba_wait_target_state(device_t dev, struct siba_devinfo *dinfo, bus_size_t reg,

sys/dev/bhnd/siba/siba_subr.c

718

rval = bhnd_bus_read_4(r, reg);

sys/dev/bhnd/siba/sibavar.h

115

struct siba_devinfo *dinfo, bus_size_t reg,

sys/dev/bhnd/siba/sibavar.h

118

struct siba_devinfo *dinfo, bus_size_t reg,

sys/dev/bnxt/bnxt_en/bnxt.h

973

#define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)

sys/dev/bnxt/bnxt_en/bnxt.h

974

#define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)

sys/dev/bnxt/bnxt_en/bnxt.h

979

#define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \

sys/dev/bnxt/bnxt_en/bnxt.h

980

((reg) & BNXT_GRC_OFFSET_MASK))

sys/dev/bnxt/bnxt_en/if_bnxt.c

1668

u32 reg = fw_health->regs[reg_idx];

sys/dev/bnxt/bnxt_en/if_bnxt.c

1671

reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);

sys/dev/bnxt/bnxt_en/if_bnxt.c

1672

reg_off = BNXT_FW_HEALTH_REG_OFF(reg);

sys/dev/bnxt/bnxt_en/if_bnxt.c

1790

u32 reg = fw_health->fw_reset_seq_regs[reg_idx];

sys/dev/bnxt/bnxt_en/if_bnxt.c

1795

reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);

sys/dev/bnxt/bnxt_en/if_bnxt.c

1796

reg_off = BNXT_FW_HEALTH_REG_OFF(reg);

sys/dev/bnxt/bnxt_en/if_bnxt.c

1878

static inline void __bnxt_map_fw_health_reg(struct bnxt_softc *bp, u32 reg)

sys/dev/bnxt/bnxt_en/if_bnxt.c

1880

writel_fbsd(bp, BNXT_GRCPF_REG_WINDOW_BASE_OUT + BNXT_FW_HEALTH_WIN_MAP_OFF, 0, reg & BNXT_GRC_BASE_MASK);

sys/dev/bnxt/bnxt_en/if_bnxt.c

1893

u32 reg = fw_health->regs[i];

sys/dev/bnxt/bnxt_en/if_bnxt.c

1895

if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC)

sys/dev/bnxt/bnxt_en/if_bnxt.c

1898

reg_base = reg & BNXT_GRC_BASE_MASK;

sys/dev/bnxt/bnxt_en/if_bnxt.c

1899

if ((reg & BNXT_GRC_BASE_MASK) != reg_base)

sys/dev/bnxt/bnxt_en/if_bnxt.c

1901

fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_OFF(reg);

sys/dev/bnxt/bnxt_re/qplib_fp.c

484

nq->nq_db.reg.bar_reg = NULL;

sys/dev/bnxt/bnxt_re/qplib_fp.c

529

nq_db->reg.bar_id = dbreg->bar_id;

sys/dev/bnxt/bnxt_re/qplib_fp.c

530

nq_db->reg.bar_base = dbreg->bar_base;

sys/dev/bnxt/bnxt_re/qplib_fp.c

531

nq_db->reg.bar_reg = dbreg->bar_reg + reg_offt;

sys/dev/bnxt/bnxt_re/qplib_fp.c

532

nq_db->reg.len = _is_chip_gen_p5_p7(res->cctx) ? sizeof(u64) :

sys/dev/bnxt/bnxt_re/qplib_fp.c

535

nq_db->dbinfo.db = nq_db->reg.bar_reg;

sys/dev/bnxt/bnxt_re/qplib_fp.h

509

struct bnxt_qplib_reg_desc reg;

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1149

creq->creq_db.reg.bar_reg = NULL;

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1152

if (cmdq->cmdq_mbox.reg.bar_reg) {

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1153

iounmap(cmdq->cmdq_mbox.reg.bar_reg);

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1154

cmdq->cmdq_mbox.reg.bar_reg = NULL;

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1216

mbox->reg.bar_id = RCFW_COMM_PCI_BAR_REGION;

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1217

mbox->reg.len = RCFW_COMM_SIZE;

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1218

mbox->reg.bar_base = pci_resource_start(pdev, mbox->reg.bar_id);

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1219

if (!mbox->reg.bar_base) {

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1222

mbox->reg.bar_id);

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1226

bar_reg = mbox->reg.bar_base + RCFW_COMM_BASE_OFFSET;

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1227

mbox->reg.len = RCFW_COMM_SIZE;

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1228

mbox->reg.bar_reg = ioremap(bar_reg, mbox->reg.len);

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1229

if (!mbox->reg.bar_reg) {

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1232

mbox->reg.bar_id);

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1236

mbox->prod = (void __iomem *)((char *)mbox->reg.bar_reg +

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1238

mbox->db = (void __iomem *)((char *)mbox->reg.bar_reg +

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1253

creq_db->reg.bar_id = dbreg->bar_id;

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1254

creq_db->reg.bar_base = dbreg->bar_base;

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1255

creq_db->reg.bar_reg = dbreg->bar_reg + reg_offt;

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1256

creq_db->reg.len = _is_chip_gen_p5_p7(res->cctx) ? sizeof(u64) :

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1259

creq_db->dbinfo.db = creq_db->reg.bar_reg;

sys/dev/bnxt/bnxt_re/qplib_rcfw.c

1290

__iowrite32_copy(mbox->reg.bar_reg, &init, sizeof(init) / 4);

sys/dev/bnxt/bnxt_re/qplib_rcfw.h

232

struct bnxt_qplib_reg_desc reg;

sys/dev/bnxt/bnxt_re/qplib_rcfw.h

247

struct bnxt_qplib_reg_desc reg;

sys/dev/bnxt/bnxt_re/qplib_res.c

1115

struct bnxt_qplib_reg_desc *reg;

sys/dev/bnxt/bnxt_re/qplib_res.c

1117

reg = &res->dpi_tbl.ucreg;

sys/dev/bnxt/bnxt_re/qplib_res.c

1118

if (reg->bar_reg)

sys/dev/bnxt/bnxt_re/qplib_res.c

1119

pci_iounmap(res->pdev, reg->bar_reg);

sys/dev/bnxt/bnxt_re/qplib_res.c

1120

reg->bar_reg = NULL;

sys/dev/bnxt/bnxt_re/qplib_res.c

1121

reg->bar_base = 0;

sys/dev/bnxt/bnxt_re/qplib_res.c

1122

reg->len = 0;

sys/dev/bnxt/bnxt_re/qplib_res.c

1123

reg->bar_id = 0; /* Zero? or ff */

sys/dev/bnxt/bnxt_re/qplib_res.c

851

struct bnxt_qplib_reg_desc *reg;

sys/dev/bnxt/bnxt_re/qplib_res.c

856

reg = &dpit->wcreg;

sys/dev/bnxt/bnxt_re/qplib_res.c

872

dpi->dpi = bit_num + (reg->offset - dpit->ucreg.offset) / PAGE_SIZE;

sys/dev/bnxt/bnxt_re/qplib_res.c

874

umaddr = reg->bar_base + reg->offset + bit_num * PAGE_SIZE;

sys/dev/bnxt/bnxt_re/qplib_res.c

954

struct bnxt_qplib_reg_desc *reg;

sys/dev/bnxt/bnxt_re/qplib_res.c

960

reg = &dpit->wcreg;

sys/dev/bnxt/bnxt_re/qplib_res.c

969

bar_len = pci_resource_len(res->pdev, reg->bar_id);

sys/dev/bnxt/bnxt_re/qplib_res.c

970

dpit->max = (bar_len - reg->offset) / PAGE_SIZE;

sys/dev/bnxt/bnxt_re/qplib_res.h

640

#define BNXT_DBR_PACING_WIN_OFF(reg) (BNXT_DBR_PACING_WIN_BASE + \

sys/dev/bwi/if_bwivar.h

76

#define CSR_READ_4(sc, reg) \

sys/dev/bwi/if_bwivar.h

77

bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))

sys/dev/bwi/if_bwivar.h

78

#define CSR_READ_2(sc, reg) \

sys/dev/bwi/if_bwivar.h

79

bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))

sys/dev/bwi/if_bwivar.h

81

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/bwi/if_bwivar.h

82

bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))

sys/dev/bwi/if_bwivar.h

83

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/bwi/if_bwivar.h

84

bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))

sys/dev/bwi/if_bwivar.h

86

#define CSR_SETBITS_4(sc, reg, bits) \

sys/dev/bwi/if_bwivar.h

87

CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))

sys/dev/bwi/if_bwivar.h

88

#define CSR_SETBITS_2(sc, reg, bits) \

sys/dev/bwi/if_bwivar.h

89

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))

sys/dev/bwi/if_bwivar.h

91

#define CSR_FILT_SETBITS_4(sc, reg, filt, bits) \

sys/dev/bwi/if_bwivar.h

92

CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))

sys/dev/bwi/if_bwivar.h

93

#define CSR_FILT_SETBITS_2(sc, reg, filt, bits) \

sys/dev/bwi/if_bwivar.h

94

CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))

sys/dev/bwi/if_bwivar.h

96

#define CSR_CLRBITS_4(sc, reg, bits) \

sys/dev/bwi/if_bwivar.h

97

CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))

sys/dev/bwi/if_bwivar.h

98

#define CSR_CLRBITS_2(sc, reg, bits) \

sys/dev/bwi/if_bwivar.h

99

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))

sys/dev/bwn/if_bwn.c

6946

uint16_t reg;

sys/dev/bwn/if_bwn.c

6949

reg = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG);

sys/dev/bwn/if_bwn.c

6950

if (reg) {

sys/dev/bwn/if_bwn_phy_g.c

1206

radio0, radio1, radio2, reg0, reg1, reg2, radio78, reg, index;

sys/dev/bwn/if_bwn_phy_g.c

1274

reg = BWN_RF_READ(mac, 0x60);

sys/dev/bwn/if_bwn_phy_g.c

1275

index = (reg & 0x001e) >> 1;

sys/dev/bwn/if_bwn_phy_g.c

1276

rcc = (((rcc_table[index] << 1) | (reg & 0x0001)) | 0x0020);

sys/dev/bwn/if_bwn_phy_g.c

1976

uint16_t reg, v, padmix;

sys/dev/bwn/if_bwn_phy_g.c

1981

reg = 0x43;

sys/dev/bwn/if_bwn_phy_g.c

1984

reg = 0x52;

sys/dev/bwn/if_bwn_phy_g.c

1989

reg = 0x43;

sys/dev/bwn/if_bwn_phy_g.c

1993

reg = 0x52;

sys/dev/bwn/if_bwn_phy_g.c

2003

return (reg);

sys/dev/bwn/if_bwn_phy_g.c

2012

uint16_t reg, mask;

sys/dev/bwn/if_bwn_phy_g.c

2064

reg = bwn_lo_txctl_regtable(mac, &mask, NULL);

sys/dev/bwn/if_bwn_phy_g.c

2066

BWN_RF_MASK(mac, reg, mask);

sys/dev/bwn/if_bwn_phy_g.c

2509

uint16_t pad, reg, value;

sys/dev/bwn/if_bwn_phy_g.c

2515

reg = bwn_lo_txctl_regtable(mac, &value, &pad);

sys/dev/bwn/if_bwn_phy_g.c

2517

BWN_RF_SETMASK(mac, reg, ~value, (rfatt->padmix ? value :0));

sys/dev/bwn/if_bwn_phy_g.c

3368

bwn_rf_2050_rfoverval(struct bwn_mac *mac, uint16_t reg, uint32_t lpd)

sys/dev/bwn/if_bwn_phy_g.c

3405

if (reg == BWN_PHY_RFOVER) {

sys/dev/bwn/if_bwn_phy_g.c

3407

} else if (reg == BWN_PHY_RFOVERVAL) {

sys/dev/bwn/if_bwn_phy_g.c

3423

if (reg == BWN_PHY_RFOVER)

sys/dev/bwn/if_bwn_phy_g.c

3425

if (reg == BWN_PHY_RFOVERVAL) {

sys/dev/bwn/if_bwn_phy_g.c

3449

if (reg == BWN_PHY_RFOVER) {

sys/dev/bwn/if_bwn_phy_g.c

3451

} else if (reg == BWN_PHY_RFOVERVAL) {

sys/dev/bwn/if_bwn_phy_g.c

3467

if (reg == BWN_PHY_RFOVER) {

sys/dev/bwn/if_bwn_phy_g.c

3469

} else if (reg == BWN_PHY_RFOVERVAL) {

sys/dev/bwn/if_bwn_phy_g.c

479

bwn_phy_g_read(struct bwn_mac *mac, uint16_t reg)

sys/dev/bwn/if_bwn_phy_g.c

482

BWN_WRITE_2(mac, BWN_PHYCTL, reg);

sys/dev/bwn/if_bwn_phy_g.c

487

bwn_phy_g_write(struct bwn_mac *mac, uint16_t reg, uint16_t value)

sys/dev/bwn/if_bwn_phy_g.c

490

BWN_WRITE_2(mac, BWN_PHYCTL, reg);

sys/dev/bwn/if_bwn_phy_g.c

495

bwn_phy_g_rf_read(struct bwn_mac *mac, uint16_t reg)

sys/dev/bwn/if_bwn_phy_g.c

498

KASSERT(reg != 1, ("%s:%d: fail", __func__, __LINE__));

sys/dev/bwn/if_bwn_phy_g.c

499

BWN_WRITE_2(mac, BWN_RFCTL, reg | 0x80);

sys/dev/bwn/if_bwn_phy_g.c

504

bwn_phy_g_rf_write(struct bwn_mac *mac, uint16_t reg, uint16_t value)

sys/dev/bwn/if_bwn_phy_g.c

507

KASSERT(reg != 1, ("%s:%d: fail", __func__, __LINE__));

sys/dev/bwn/if_bwn_phy_g.c

508

BWN_WRITE_2(mac, BWN_RFCTL, reg);

sys/dev/bwn/if_bwn_phy_g.h

39

extern uint16_t bwn_phy_g_read(struct bwn_mac *mac, uint16_t reg);

sys/dev/bwn/if_bwn_phy_g.h

40

extern void bwn_phy_g_write(struct bwn_mac *mac, uint16_t reg, uint16_t value);

sys/dev/bwn/if_bwn_phy_g.h

41

extern uint16_t bwn_phy_g_rf_read(struct bwn_mac *mac, uint16_t reg);

sys/dev/bwn/if_bwn_phy_g.h

42

extern void bwn_phy_g_rf_write(struct bwn_mac *mac, uint16_t reg, uint16_t value);

sys/dev/bwn/if_bwn_phy_lp.c

1309

uint16_t reg;

sys/dev/bwn/if_bwn_phy_lp.c

1358

BWN_PHY_WRITE(mac, v1[i].reg, v1[i].value);

sys/dev/bwn/if_bwn_phy_lp.c

1669

BWN_RF_WRITE(mac, v1[i].reg, v1[i].value);

sys/dev/bwn/if_bwn_phy_lp.c

1775

BWN_RF_WRITE(mac, v1[i].reg, v1[i].value);

sys/dev/bwn/if_bwn_phy_lp.c

1778

BWN_RF_WRITE(mac, v1[i].reg, v1[i].value);

sys/dev/bwn/if_bwn_phy_lp.c

1791

BWN_RF_WRITE(mac, v2[i].reg, v2[i].value);

sys/dev/bwn/if_bwn_phy_lp.c

477

bwn_phy_lp_read(struct bwn_mac *mac, uint16_t reg)

sys/dev/bwn/if_bwn_phy_lp.c

480

BWN_WRITE_2(mac, BWN_PHYCTL, reg);

sys/dev/bwn/if_bwn_phy_lp.c

485

bwn_phy_lp_write(struct bwn_mac *mac, uint16_t reg, uint16_t value)

sys/dev/bwn/if_bwn_phy_lp.c

488

BWN_WRITE_2(mac, BWN_PHYCTL, reg);

sys/dev/bwn/if_bwn_phy_lp.c

493

bwn_phy_lp_maskset(struct bwn_mac *mac, uint16_t reg, uint16_t mask,

sys/dev/bwn/if_bwn_phy_lp.c

497

BWN_WRITE_2(mac, BWN_PHYCTL, reg);

sys/dev/bwn/if_bwn_phy_lp.c

503

bwn_phy_lp_rf_read(struct bwn_mac *mac, uint16_t reg)

sys/dev/bwn/if_bwn_phy_lp.c

506

KASSERT(reg != 1, ("unaccessible register %d", reg));

sys/dev/bwn/if_bwn_phy_lp.c

507

if (mac->mac_phy.rev < 2 && reg != 0x4001)

sys/dev/bwn/if_bwn_phy_lp.c

508

reg |= 0x100;

sys/dev/bwn/if_bwn_phy_lp.c

510

reg |= 0x200;

sys/dev/bwn/if_bwn_phy_lp.c

511

BWN_WRITE_2(mac, BWN_RFCTL, reg);

sys/dev/bwn/if_bwn_phy_lp.c

516

bwn_phy_lp_rf_write(struct bwn_mac *mac, uint16_t reg, uint16_t value)

sys/dev/bwn/if_bwn_phy_lp.c

519

KASSERT(reg != 1, ("unaccessible register %d", reg));

sys/dev/bwn/if_bwn_phy_lp.c

520

BWN_WRITE_2(mac, BWN_RFCTL, reg);

sys/dev/bwn/if_bwn_phy_n.c

151

bwn_phy_n_read(struct bwn_mac *mac, uint16_t reg)

sys/dev/bwn/if_bwn_phy_n.c

154

BWN_WRITE_2(mac, BWN_PHYCTL, reg);

sys/dev/bwn/if_bwn_phy_n.c

159

bwn_phy_n_write(struct bwn_mac *mac, uint16_t reg, uint16_t value)

sys/dev/bwn/if_bwn_phy_n.c

162

BWN_WRITE_2(mac, BWN_PHYCTL, reg);

sys/dev/bwn/if_bwn_phy_n.c

167

bwn_phy_n_rf_read(struct bwn_mac *mac, uint16_t reg)

sys/dev/bwn/if_bwn_phy_n.c

171

if (mac->mac_phy.rev < 7 && reg == 1) {

sys/dev/bwn/if_bwn_phy_n.c

176

reg |= 0x200; /* radio 0x2057 */

sys/dev/bwn/if_bwn_phy_n.c

178

reg |= 0x100;

sys/dev/bwn/if_bwn_phy_n.c

180

BWN_WRITE_2(mac, BWN_RFCTL, reg);

sys/dev/bwn/if_bwn_phy_n.c

185

bwn_phy_n_rf_write(struct bwn_mac *mac, uint16_t reg, uint16_t value)

sys/dev/bwn/if_bwn_phy_n.c

189

if (mac->mac_phy.rev < 7 && reg == 1) {

sys/dev/bwn/if_bwn_phy_n.c

193

BWN_WRITE_2(mac, BWN_RFCTL, reg);

sys/dev/bwn/if_bwn_phy_n.h

39

extern uint16_t bwn_phy_n_read(struct bwn_mac *mac, uint16_t reg);

sys/dev/bwn/if_bwn_phy_n.h

40

extern void bwn_phy_n_write(struct bwn_mac *mac, uint16_t reg, uint16_t value);

sys/dev/bwn/if_bwn_phy_n.h

41

extern uint16_t bwn_phy_n_rf_read(struct bwn_mac *mac, uint16_t reg);

sys/dev/bwn/if_bwn_phy_n.h

42

extern void bwn_phy_n_rf_write(struct bwn_mac *mac, uint16_t reg, uint16_t value);

sys/dev/bwn/if_bwnreg.h

419

#define BWN_PHY_CCK(reg) ((reg) | BWN_PHYROUTE_BASE)

sys/dev/bwn/if_bwnreg.h

420

#define BWN_PHY_N(reg) ((reg) | BWN_PHYROUTE_BASE) /* PHY-N */

sys/dev/bwn/if_bwnreg.h

421

#define BWN_PHY_N_BMODE(reg) ((reg) | BWN_PHYROUTE_N_BMODE)

sys/dev/bwn/if_bwnreg.h

422

#define BWN_PHY_OFDM(reg) ((reg) | BWN_PHYROUTE_OFDM_GPHY)

sys/dev/bwn/if_bwnreg.h

423

#define BWN_PHY_EXTG(reg) ((reg) | BWN_PHYROUTE_EXT_GPHY)

sys/dev/bxe/bxe.c

13156

int reg,

sys/dev/bxe/bxe.c

13165

return (pci_read_config(sc->dev, (pcie_reg + reg), width));

sys/dev/bxe/bxe.c

13190

int reg;

sys/dev/bxe/bxe.c

13193

if (pci_find_cap(sc->dev, PCIY_PMG, &reg) == 0) {

sys/dev/bxe/bxe.c

13194

if (reg != 0) {

sys/dev/bxe/bxe.c

13195

BLOGD(sc, DBG_LOAD, "Found PM capability at 0x%04x\n", reg);

sys/dev/bxe/bxe.c

13198

sc->devinfo.pcie_pm_cap_reg = (uint16_t)reg;

sys/dev/bxe/bxe.c

13228

sc->devinfo.pcie_pcie_cap_reg = (uint16_t)reg;

sys/dev/bxe/bxe.c

13231

if (pci_find_cap(sc->dev, PCIY_MSI, &reg) == 0) {

sys/dev/bxe/bxe.c

13232

if (reg != 0) {

sys/dev/bxe/bxe.c

13233

BLOGD(sc, DBG_LOAD, "Found MSI capability at 0x%04x\n", reg);

sys/dev/bxe/bxe.c

13236

sc->devinfo.pcie_msi_cap_reg = (uint16_t)reg;

sys/dev/bxe/bxe.c

13241

if (pci_find_cap(sc->dev, PCIY_MSIX, &reg) == 0) {

sys/dev/bxe/bxe.c

13242

if (reg != 0) {

sys/dev/bxe/bxe.c

13243

BLOGD(sc, DBG_LOAD, "Found MSI-X capability at 0x%04x\n", reg);

sys/dev/bxe/bxe.c

13246

sc->devinfo.pcie_msix_cap_reg = (uint16_t)reg;

sys/dev/bxe/bxe.c

17712

uint32_t reg,

sys/dev/bxe/bxe.c

17719

while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {

sys/dev/bxe/bxe.c

17728

uint32_t reg,

sys/dev/bxe/bxe.c

17732

uint32_t val = bxe_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);

sys/dev/bxe/bxe.c

18425

int reg;

sys/dev/bxe/bxe.c

18429

reg = PXP2_REG_RQ_ONCHIP_AT + index*8;

sys/dev/bxe/bxe.c

18431

reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;

sys/dev/bxe/bxe.c

18436

REG_WR_DMAE(sc, reg, wb_write, 2);

sys/dev/bxe/bxe.h

2269

uint32_t reg,

sys/dev/bxe/bxe.h

2277

val = REG_RD(sc, reg);

sys/dev/bxe/bxe_elink.c

10577

reg_set[i].reg, reg_set[i].val);

sys/dev/bxe/bxe_elink.c

10647

elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,

sys/dev/bxe/bxe_elink.c

3414

uint16_t reg, uint16_t val)

sys/dev/bxe/bxe_elink.c

3425

tmp = ((phy->addr << 21) | (reg << 16) | val |

sys/dev/bxe/bxe_elink.c

3449

uint16_t reg, uint16_t *ret_val)

sys/dev/bxe/bxe_elink.c

3461

val = ((phy->addr << 21) | (reg << 16) |

sys/dev/bxe/bxe_elink.c

3490

uint8_t devad, uint16_t reg, uint16_t *ret_val)

sys/dev/bxe/bxe_elink.c

3506

val = ((phy->addr << 21) | (devad << 16) | reg |

sys/dev/bxe/bxe_elink.c

3567

uint8_t devad, uint16_t reg, uint16_t val)

sys/dev/bxe/bxe_elink.c

3584

tmp = ((phy->addr << 21) | (devad << 16) | reg |

sys/dev/bxe/bxe_elink.c

3993

uint8_t devad, uint16_t reg, uint16_t or_val)

sys/dev/bxe/bxe_elink.c

3996

elink_cl45_read(sc, phy, devad, reg, &val);

sys/dev/bxe/bxe_elink.c

3997

elink_cl45_write(sc, phy, devad, reg, val | or_val);

sys/dev/bxe/bxe_elink.c

4002

uint8_t devad, uint16_t reg, uint16_t and_val)

sys/dev/bxe/bxe_elink.c

4005

elink_cl45_read(sc, phy, devad, reg, &val);

sys/dev/bxe/bxe_elink.c

4006

elink_cl45_write(sc, phy, devad, reg, val & and_val);

sys/dev/bxe/bxe_elink.c

4010

uint8_t devad, uint16_t reg, uint16_t *ret_val)

sys/dev/bxe/bxe_elink.c

4020

reg, ret_val);

sys/dev/bxe/bxe_elink.c

4027

uint8_t devad, uint16_t reg, uint16_t val)

sys/dev/bxe/bxe_elink.c

4037

reg, val);

sys/dev/bxe/bxe_elink.c

4492

elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,

sys/dev/bxe/bxe_elink.c

4527

elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,

sys/dev/bxe/bxe_elink.c

4581

elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,

sys/dev/bxe/bxe_elink.c

4734

elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,

sys/dev/bxe/bxe_elink.c

5153

elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,

sys/dev/bxe/bxe_elink.c

951

static uint32_t elink_bits_en(struct bxe_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/bxe/bxe_elink.c

953

uint32_t val = REG_RD(sc, reg);

sys/dev/bxe/bxe_elink.c

956

REG_WR(sc, reg, val);

sys/dev/bxe/bxe_elink.c

960

static uint32_t elink_bits_dis(struct bxe_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/bxe/bxe_elink.c

962

uint32_t val = REG_RD(sc, reg);

sys/dev/bxe/bxe_elink.c

965

REG_WR(sc, reg, val);

sys/dev/bxe/bxe_elink.c

9825

uint16_t reg;

sys/dev/bxe/bxe_elink.c

9827

reg = MDIO_XS_8706_REG_BANK_RX0 +

sys/dev/bxe/bxe_elink.c

9830

elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);

sys/dev/bxe/bxe_elink.c

9836

" reg 0x%x <-- val 0x%x\n", reg, val);

sys/dev/bxe/bxe_elink.c

9837

elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);

sys/dev/bxe/bxe_elink.h

258

uint16_t reg;

sys/dev/bxe/bxe_elink.h

531

uint8_t devad, uint16_t reg, uint16_t *ret_val);

sys/dev/bxe/bxe_elink.h

534

uint8_t devad, uint16_t reg, uint16_t val);

sys/dev/bxe/ecore_init_ops.h

216

static void ecore_wr_64(struct bxe_softc *sc, uint32_t reg, uint32_t val_lo,

sys/dev/bxe/ecore_init_ops.h

223

REG_WR_DMAE_LEN(sc, reg, wb_write, 2);

sys/dev/bxe/ecore_init_ops.h

708

uint32_t reg;

sys/dev/bxe/ecore_init_ops.h

711

reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx*8;

sys/dev/bxe/ecore_init_ops.h

713

reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;

sys/dev/bxe/ecore_init_ops.h

715

ecore_wr_64(sc, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));

sys/dev/bxe/ecore_init_ops.h

904

uint32_t base_reg, uint32_t reg)

sys/dev/bxe/ecore_init_ops.h

911

ecore_init_wr_wb(sc, reg + i*8,

sys/dev/cadence/if_cgem.c

1373

cgem_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/cadence/if_cgem.c

1381

(reg << CGEM_PHY_MAINT_REG_ADDR_SHIFT));

sys/dev/cadence/if_cgem.c

1388

device_printf(dev, "phy read timeout: %d\n", reg);

sys/dev/cadence/if_cgem.c

1395

if (reg == MII_EXTSR)

sys/dev/cadence/if_cgem.c

1406

cgem_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/cadence/if_cgem.c

1414

(reg << CGEM_PHY_MAINT_REG_ADDR_SHIFT) |

sys/dev/cadence/if_cgem.c

1422

device_printf(dev, "phy write timeout: %d\n", reg);

sys/dev/cardbus/cardbus_cis.c

291

uint8_t reg;

sys/dev/cardbus/cardbus_cis.c

299

reg = *tupledata;

sys/dev/cardbus/cardbus_cis.c

301

if (reg & TPL_BAR_REG_AS)

sys/dev/cardbus/cardbus_cis.c

306

bar = reg & TPL_BAR_REG_ASI_MASK;

sys/dev/cardbus/cardbus_cis.c

319

if (reg & TPL_BAR_REG_PREFETCHABLE)

sys/dev/cardbus/cardbus_cis.c

340

if (reg & TPL_BAR_REG_BELOW1MB)

sys/dev/cas/if_cas.c

148

static int cas_mii_readreg(device_t dev, int phy, int reg);

sys/dev/cas/if_cas.c

150

static int cas_mii_writereg(device_t dev, int phy, int reg, int val);

sys/dev/cas/if_cas.c

2135

cas_mii_readreg(device_t dev, int phy, int reg)

sys/dev/cas/if_cas.c

2142

printf("%s: phy %d reg %d\n", __func__, phy, reg);

sys/dev/cas/if_cas.c

2147

switch (reg) {

sys/dev/cas/if_cas.c

2149

reg = CAS_PCS_CTRL;

sys/dev/cas/if_cas.c

2152

reg = CAS_PCS_STATUS;

sys/dev/cas/if_cas.c

2158

reg = CAS_PCS_ANAR;

sys/dev/cas/if_cas.c

2161

reg = CAS_PCS_ANLPAR;

sys/dev/cas/if_cas.c

2167

"%s: unhandled register %d\n", __func__, reg);

sys/dev/cas/if_cas.c

2170

return (CAS_READ_4(sc, reg));

sys/dev/cas/if_cas.c

2176

(reg << CAS_MIF_FRAME_REG_SHFT);

sys/dev/cas/if_cas.c

2193

cas_mii_writereg(device_t dev, int phy, int reg, int val)

sys/dev/cas/if_cas.c

2200

printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__);

sys/dev/cas/if_cas.c

2205

switch (reg) {

sys/dev/cas/if_cas.c

2207

reg = CAS_PCS_STATUS;

sys/dev/cas/if_cas.c

2210

reg = CAS_PCS_CTRL;

sys/dev/cas/if_cas.c

2238

reg = CAS_PCS_ANLPAR;

sys/dev/cas/if_cas.c

2242

"%s: unhandled register %d\n", __func__, reg);

sys/dev/cas/if_cas.c

2245

CAS_WRITE_4(sc, reg, val);

sys/dev/cas/if_cas.c

2246

CAS_BARRIER(sc, reg, 4,

sys/dev/cas/if_cas.c

2254

(reg << CAS_MIF_FRAME_REG_SHFT) |

sys/dev/cas/if_cas.c

673

uint32_t reg;

sys/dev/cas/if_cas.c

676

reg = CAS_READ_4(sc, r);

sys/dev/cas/if_cas.c

677

if ((reg & clr) == 0 && (reg & set) == set)

sys/dev/cas/if_casreg.h

1011

#define CAS_GET(reg, bits) (((reg) & (bits ## _MASK)) >> (bits ## _SHFT))

sys/dev/cesa/cesa.h

91

#define CESA_REG_READ(sc, reg) \

sys/dev/cesa/cesa.h

92

bus_read_4((sc)->sc_res[RES_CESA_REGS], (reg))

sys/dev/cesa/cesa.h

93

#define CESA_REG_WRITE(sc, reg, val) \

sys/dev/cesa/cesa.h

94

bus_write_4((sc)->sc_res[RES_CESA_REGS], (reg), (val))

sys/dev/cesa/cesa.h

96

#define CESA_TDMA_READ(sc, reg) \

sys/dev/cesa/cesa.h

97

bus_read_4((sc)->sc_res[RES_TDMA_REGS], (reg))

sys/dev/cesa/cesa.h

98

#define CESA_TDMA_WRITE(sc, reg, val) \

sys/dev/cesa/cesa.h

99

bus_write_4((sc)->sc_res[RES_TDMA_REGS], (reg), (val))

sys/dev/clk/allwinner/aw_ccu.c

102

bus_size_t reg;

sys/dev/clk/allwinner/aw_ccu.c

106

if (aw_ccu_check_addr(sc, addr, &bsh, &reg) != 0)

sys/dev/clk/allwinner/aw_ccu.c

110

*val = bus_space_read_4(sc->bst, bsh, reg);

sys/dev/clk/allwinner/aw_ccu.c

120

bus_size_t reg;

sys/dev/clk/allwinner/aw_ccu.c

125

if (aw_ccu_check_addr(sc, addr, &bsh, &reg) != 0)

sys/dev/clk/allwinner/aw_ccu.c

129

val = bus_space_read_4(sc->bst, bsh, reg);

sys/dev/clk/allwinner/aw_ccu.c

132

bus_space_write_4(sc->bst, bsh, reg, val);

sys/dev/clk/allwinner/aw_ccu.c

84

bus_size_t reg;

sys/dev/clk/allwinner/aw_ccu.c

88

if (aw_ccu_check_addr(sc, addr, &bsh, &reg) != 0)

sys/dev/clk/allwinner/aw_ccu.c

92

bus_space_write_4(sc->bst, bsh, reg, val);

sys/dev/clk/allwinner/aw_ccung.c

103

uint32_t reg;

sys/dev/clk/allwinner/aw_ccung.c

108

reg = CCU_READ4(sc, addr);

sys/dev/clk/allwinner/aw_ccung.c

109

reg &= ~clr;

sys/dev/clk/allwinner/aw_ccung.c

110

reg |= set;

sys/dev/clk/allwinner/aw_ccung.c

111

CCU_WRITE4(sc, addr, reg);

sys/dev/clk/allwinner/aw_ccung.c

73

#define CCU_READ4(sc, reg) bus_read_4((sc)->res, (reg))

sys/dev/clk/allwinner/aw_ccung.c

74

#define CCU_WRITE4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/dev/clk/clk_div.c

116

uint32_t reg;

sys/dev/clk/clk_div.c

124

rv = RD4(clk, sc->offset, &reg);

sys/dev/clk/clk_div.c

129

i_div = (reg >> sc->i_shift) & sc->i_mask;

sys/dev/clk/clk_div.c

133

f_div = (reg >> sc->f_shift) & sc->f_mask;

sys/dev/clk/clk_div.c

166

uint32_t reg, i_div, f_div, hw_i_div;

sys/dev/clk/clk_div.c

229

RD4(clk, sc->offset, &reg);

sys/dev/clk/clk_gate.c

103

uint32_t reg;

sys/dev/clk/clk_gate.c

109

rv = RD4(clk, sc->offset, &reg);

sys/dev/clk/clk_gate.c

113

reg = (reg >> sc->shift) & sc->mask;

sys/dev/clk/clk_gate.c

114

*enabled = reg == sc->on_value;

sys/dev/clk/clk_gate.c

83

uint32_t reg;

sys/dev/clk/clk_gate.c

95

RD4(clk, sc->offset, &reg);

sys/dev/clk/clk_mux.c

106

RD4(clk, sc->offset, &reg);

sys/dev/clk/clk_mux.c

73

uint32_t reg;

sys/dev/clk/clk_mux.c

80

rv = RD4(clk, sc->offset, &reg);

sys/dev/clk/clk_mux.c

85

reg = (reg >> sc->shift) & sc->mask;

sys/dev/clk/clk_mux.c

86

clknode_init_parent_idx(clk, reg);

sys/dev/clk/clk_mux.c

93

uint32_t reg;

sys/dev/clk/rockchip/rk_clk_armclk.c

121

uint32_t reg, div;

sys/dev/clk/rockchip/rk_clk_armclk.c

127

READ4(clk, sc->muxdiv_offset, &reg);

sys/dev/clk/rockchip/rk_clk_armclk.c

128

dprintf("Read: muxdiv_offset=%x, val=%x\n", sc->muxdiv_offset, reg);

sys/dev/clk/rockchip/rk_clk_armclk.c

132

div = ((reg & sc->div_mask) >> sc->div_shift) + 1;

sys/dev/clk/rockchip/rk_clk_composite.c

170

uint32_t reg, div;

sys/dev/clk/rockchip/rk_clk_composite.c

176

READ4(clk, sc->muxdiv_offset, &reg);

sys/dev/clk/rockchip/rk_clk_composite.c

177

dprintf("Read: muxdiv_offset=%x, val=%x\n", sc->muxdiv_offset, reg);

sys/dev/clk/rockchip/rk_clk_composite.c

181

div = ((reg & sc->div_mask) >> sc->div_shift);

sys/dev/clk/rockchip/rk_clk_composite.c

194

uint64_t freq, uint32_t *reg)

sys/dev/clk/rockchip/rk_clk_composite.c

218

*reg = best_div_reg;

sys/dev/clk/rockchip/rk_clk_fract.c

140

uint32_t reg;

sys/dev/clk/rockchip/rk_clk_fract.c

145

RD4(clk, sc->offset, &reg);

sys/dev/clk/rockchip/rk_clk_fract.c

148

sc->numerator = (reg >> 16) & 0xFFFF;

sys/dev/clk/rockchip/rk_clk_fract.c

149

sc->denominator = reg & 0xFFFF;

sys/dev/clk/rockchip/rk_clk_gate.c

107

RD4(clk, sc->offset, &reg);

sys/dev/clk/rockchip/rk_clk_gate.c

74

uint32_t reg;

sys/dev/clk/rockchip/rk_clk_gate.c

80

rv = RD4(clk, sc->offset, &reg);

sys/dev/clk/rockchip/rk_clk_gate.c

84

reg = (reg >> sc->shift) & sc->mask;

sys/dev/clk/rockchip/rk_clk_gate.c

85

sc->ungated = reg == sc->on_value ? 1 : 0;

sys/dev/clk/rockchip/rk_clk_gate.c

93

uint32_t reg;

sys/dev/clk/rockchip/rk_clk_mux.c

109

uint32_t reg;

sys/dev/clk/rockchip/rk_clk_mux.c

124

reg = SYSCON_READ_4(sc->grf, sc->offset);

sys/dev/clk/rockchip/rk_clk_mux.c

127

rv = RD4(clk, sc->offset, &reg);

sys/dev/clk/rockchip/rk_clk_mux.c

132

reg = (reg >> sc->shift) & sc->mask;

sys/dev/clk/rockchip/rk_clk_mux.c

133

clknode_init_parent_idx(clk, reg);

sys/dev/clk/rockchip/rk_clk_mux.c

140

uint32_t reg;

sys/dev/clk/rockchip/rk_clk_mux.c

158

RD4(clk, sc->offset, &reg);

sys/dev/clk/rockchip/rk_clk_pll.c

123

uint32_t reg;

sys/dev/clk/rockchip/rk_clk_pll.c

128

READ4(clk, sc->mode_reg, &reg);

sys/dev/clk/rockchip/rk_clk_pll.c

131

reg = (reg >> sc->mode_shift) & RK3066_CLK_PLL_MODE_MASK;

sys/dev/clk/rockchip/rk_clk_pll.c

132

clknode_init_parent_idx(clk, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

140

uint32_t reg;

sys/dev/clk/rockchip/rk_clk_pll.c

145

reg = (idx & RK3066_CLK_PLL_MODE_MASK) << sc->mode_shift;

sys/dev/clk/rockchip/rk_clk_pll.c

146

reg |= (RK3066_CLK_PLL_MODE_MASK << sc->mode_shift) <<

sys/dev/clk/rockchip/rk_clk_pll.c

150

WRITE4(clk, sc->mode_reg, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

161

uint32_t raw0, raw1, raw2, reg;

sys/dev/clk/rockchip/rk_clk_pll.c

170

READ4(clk, sc->mode_reg, &reg);

sys/dev/clk/rockchip/rk_clk_pll.c

174

reg = (reg >> sc->mode_shift) & RK3066_CLK_PLL_MODE_MASK;

sys/dev/clk/rockchip/rk_clk_pll.c

176

if (reg != RK3066_CLK_PLL_MODE_NORMAL)

sys/dev/clk/rockchip/rk_clk_pll.c

208

uint32_t reg;

sys/dev/clk/rockchip/rk_clk_pll.c

228

reg = (RK3066_CLK_PLL_MODE_MASK << sc->mode_shift) <<

sys/dev/clk/rockchip/rk_clk_pll.c

230

dprintf("Set PLL_MODEREG to %x\n", reg);

sys/dev/clk/rockchip/rk_clk_pll.c

231

WRITE4(clk, sc->mode_reg, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

238

reg = 0;

sys/dev/clk/rockchip/rk_clk_pll.c

239

reg |= RK3066_CLK_PLL_POSTDIV_MASK << 16;

sys/dev/clk/rockchip/rk_clk_pll.c

240

reg |= (rates->postdiv1 - 1) << RK3066_CLK_PLL_POSTDIV_SHIFT;

sys/dev/clk/rockchip/rk_clk_pll.c

242

reg |= RK3066_CLK_PLL_REFDIV_MASK << 16;

sys/dev/clk/rockchip/rk_clk_pll.c

243

reg |= (rates->refdiv - 1)<< RK3066_CLK_PLL_REFDIV_SHIFT;

sys/dev/clk/rockchip/rk_clk_pll.c

245

dprintf("Set PLL_CON0 to %x\n", reg);

sys/dev/clk/rockchip/rk_clk_pll.c

246

WRITE4(clk, sc->base_offset, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

250

READ4(clk, sc->base_offset + 4, &reg);

sys/dev/clk/rockchip/rk_clk_pll.c

251

reg &= ~RK3066_CLK_PLL_FBDIV_MASK;

sys/dev/clk/rockchip/rk_clk_pll.c

252

reg |= RK3066_CLK_PLL_FBDIV_MASK << 16;

sys/dev/clk/rockchip/rk_clk_pll.c

253

reg = (rates->fbdiv - 1) << RK3066_CLK_PLL_FBDIV_SHIFT;

sys/dev/clk/rockchip/rk_clk_pll.c

255

dprintf("Set PLL_CON1 to %x\n", reg);

sys/dev/clk/rockchip/rk_clk_pll.c

256

WRITE4(clk, sc->base_offset + 0x4, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

259

reg = rates->bwadj - 1;

sys/dev/clk/rockchip/rk_clk_pll.c

260

dprintf("Set PLL_CON2 to %x (%x)\n", reg, rates->bwadj);

sys/dev/clk/rockchip/rk_clk_pll.c

261

WRITE4(clk, sc->base_offset + 0x8, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

270

READ4(clk, sc->base_offset + 0x4, &reg);

sys/dev/clk/rockchip/rk_clk_pll.c

271

if ((reg & RK3066_CLK_PLL_LOCK_MASK) != 0)

sys/dev/clk/rockchip/rk_clk_pll.c

281

dprintf("PLL_CON1: %x\n", reg);

sys/dev/clk/rockchip/rk_clk_pll.c

286

reg = (RK3066_CLK_PLL_MODE_NORMAL << sc->mode_shift);

sys/dev/clk/rockchip/rk_clk_pll.c

287

reg |= (RK3066_CLK_PLL_MODE_MASK << sc->mode_shift) <<

sys/dev/clk/rockchip/rk_clk_pll.c

289

dprintf("Set PLL_MODEREG to %x\n", reg);

sys/dev/clk/rockchip/rk_clk_pll.c

290

WRITE4(clk, sc->mode_reg, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

427

uint32_t reg;

sys/dev/clk/rockchip/rk_clk_pll.c

451

reg = (RK3328_CLK_PLL_MODE_MASK << sc->mode_shift) <<

sys/dev/clk/rockchip/rk_clk_pll.c

453

dprintf("Set PLL_MODEREG to %x\n", reg);

sys/dev/clk/rockchip/rk_clk_pll.c

454

WRITE4(clk, sc->mode_reg, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

457

reg = (rates->postdiv1 << RK3328_CLK_PLL_POSTDIV1_SHIFT) |

sys/dev/clk/rockchip/rk_clk_pll.c

459

reg |= (RK3328_CLK_PLL_POSTDIV1_MASK | RK3328_CLK_PLL_FBDIV_MASK) << 16;

sys/dev/clk/rockchip/rk_clk_pll.c

460

dprintf("Set PLL_CON0 to %x\n", reg);

sys/dev/clk/rockchip/rk_clk_pll.c

461

WRITE4(clk, sc->base_offset, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

464

reg = (rates->dsmpd << RK3328_CLK_PLL_DSMPD_SHIFT) |

sys/dev/clk/rockchip/rk_clk_pll.c

467

reg |= (RK3328_CLK_PLL_DSMPD_MASK |

sys/dev/clk/rockchip/rk_clk_pll.c

470

dprintf("Set PLL_CON1 to %x\n", reg);

sys/dev/clk/rockchip/rk_clk_pll.c

471

WRITE4(clk, sc->base_offset + 0x4, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

474

READ4(clk, sc->base_offset + 0x8, &reg);

sys/dev/clk/rockchip/rk_clk_pll.c

475

reg &= ~RK3328_CLK_PLL_FRAC_MASK;

sys/dev/clk/rockchip/rk_clk_pll.c

476

reg |= rates->frac << RK3328_CLK_PLL_FRAC_SHIFT;

sys/dev/clk/rockchip/rk_clk_pll.c

477

dprintf("Set PLL_CON2 to %x\n", reg);

sys/dev/clk/rockchip/rk_clk_pll.c

478

WRITE4(clk, sc->base_offset + 0x8, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

482

READ4(clk, sc->base_offset + 0x4, &reg);

sys/dev/clk/rockchip/rk_clk_pll.c

483

if ((reg & RK3328_CLK_PLL_LOCK_MASK) == 0)

sys/dev/clk/rockchip/rk_clk_pll.c

489

reg = (RK3328_CLK_PLL_MODE_NORMAL << sc->mode_shift);

sys/dev/clk/rockchip/rk_clk_pll.c

490

reg |= (RK3328_CLK_PLL_MODE_MASK << sc->mode_shift) <<

sys/dev/clk/rockchip/rk_clk_pll.c

492

dprintf("Set PLL_MODEREG to %x\n", reg);

sys/dev/clk/rockchip/rk_clk_pll.c

493

WRITE4(clk, sc->mode_reg, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

668

uint32_t reg;

sys/dev/clk/rockchip/rk_clk_pll.c

692

reg = RK3399_CLK_PLL_MODE_SLOW << RK3399_CLK_PLL_MODE_SHIFT;

sys/dev/clk/rockchip/rk_clk_pll.c

693

reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT;

sys/dev/clk/rockchip/rk_clk_pll.c

694

WRITE4(clk, sc->base_offset + 0xC, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

697

reg = rates->fbdiv << RK3399_CLK_PLL_FBDIV_SHIFT;

sys/dev/clk/rockchip/rk_clk_pll.c

698

reg |= RK3399_CLK_PLL_FBDIV_MASK << RK_CLK_PLL_MASK_SHIFT;

sys/dev/clk/rockchip/rk_clk_pll.c

699

WRITE4(clk, sc->base_offset, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

702

reg = rates->postdiv1 << RK3399_CLK_PLL_POSTDIV1_SHIFT;

sys/dev/clk/rockchip/rk_clk_pll.c

703

reg |= rates->postdiv2 << RK3399_CLK_PLL_POSTDIV2_SHIFT;

sys/dev/clk/rockchip/rk_clk_pll.c

704

reg |= rates->refdiv << RK3399_CLK_PLL_REFDIV_SHIFT;

sys/dev/clk/rockchip/rk_clk_pll.c

705

reg |= (RK3399_CLK_PLL_POSTDIV1_MASK | RK3399_CLK_PLL_POSTDIV2_MASK |

sys/dev/clk/rockchip/rk_clk_pll.c

707

WRITE4(clk, sc->base_offset + 0x4, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

710

READ4(clk, sc->base_offset + 0x8, &reg);

sys/dev/clk/rockchip/rk_clk_pll.c

711

reg &= ~RK3399_CLK_PLL_FRAC_MASK;

sys/dev/clk/rockchip/rk_clk_pll.c

712

reg |= rates->frac << RK3399_CLK_PLL_FRAC_SHIFT;

sys/dev/clk/rockchip/rk_clk_pll.c

713

WRITE4(clk, sc->base_offset + 0x8, reg | RK3399_CLK_PLL_WRITE_MASK);

sys/dev/clk/rockchip/rk_clk_pll.c

716

reg = rates->dsmpd << RK3399_CLK_PLL_DSMPD_SHIFT;

sys/dev/clk/rockchip/rk_clk_pll.c

717

reg |= RK3399_CLK_PLL_DSMPD_MASK << RK_CLK_PLL_MASK_SHIFT;

sys/dev/clk/rockchip/rk_clk_pll.c

718

WRITE4(clk, sc->base_offset + 0xC, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

722

READ4(clk, sc->base_offset + RK3399_CLK_PLL_LOCK_OFFSET, &reg);

sys/dev/clk/rockchip/rk_clk_pll.c

723

if ((reg & RK3399_CLK_PLL_LOCK_MASK) == 0)

sys/dev/clk/rockchip/rk_clk_pll.c

729

reg = RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT;

sys/dev/clk/rockchip/rk_clk_pll.c

730

reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT;

sys/dev/clk/rockchip/rk_clk_pll.c

731

WRITE4(clk, sc->base_offset + 0xC, reg);

sys/dev/clk/rockchip/rk_cru.c

101

reg = CCU_READ4(sc, addr);

sys/dev/clk/rockchip/rk_cru.c

102

reg &= ~clr;

sys/dev/clk/rockchip/rk_cru.c

103

reg |= set;

sys/dev/clk/rockchip/rk_cru.c

104

CCU_WRITE4(sc, addr, reg);

sys/dev/clk/rockchip/rk_cru.c

113

uint32_t reg;

sys/dev/clk/rockchip/rk_cru.c

122

reg = sc->reset_offset + id / 16 * 4;

sys/dev/clk/rockchip/rk_cru.c

129

CCU_WRITE4(sc, reg, val | ((1 << bit) << 16));

sys/dev/clk/rockchip/rk_cru.c

139

uint32_t reg;

sys/dev/clk/rockchip/rk_cru.c

147

reg = sc->reset_offset + id / 16 * 4;

sys/dev/clk/rockchip/rk_cru.c

151

val = CCU_READ4(sc, reg);

sys/dev/clk/rockchip/rk_cru.c

67

#define CCU_READ4(sc, reg) bus_read_4((sc)->res, (reg))

sys/dev/clk/rockchip/rk_cru.c

68

#define CCU_WRITE4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/dev/clk/rockchip/rk_cru.c

97

uint32_t reg;

sys/dev/clk/starfive/jh7110_clk.c

109

uint32_t reg;

sys/dev/clk/starfive/jh7110_clk.c

117

reg = READ4(sc, sc_clk->offset);

sys/dev/clk/starfive/jh7110_clk.c

119

idx = (reg & JH7110_MUX_MASK) >> JH7110_MUX_SHIFT;

sys/dev/clk/starfive/jh7110_clk.c

132

uint32_t reg;

sys/dev/clk/starfive/jh7110_clk.c

142

reg = READ4(sc, sc_clk->offset);

sys/dev/clk/starfive/jh7110_clk.c

144

reg |= (1 << JH7110_ENABLE_SHIFT);

sys/dev/clk/starfive/jh7110_clk.c

146

reg &= ~(1 << JH7110_ENABLE_SHIFT);

sys/dev/clk/starfive/jh7110_clk.c

147

WRITE4(sc, sc_clk->offset, reg);

sys/dev/clk/starfive/jh7110_clk.c

159

uint32_t reg;

sys/dev/clk/starfive/jh7110_clk.c

173

reg = READ4(sc, sc_clk->offset) & ~JH7110_MUX_MASK;

sys/dev/clk/starfive/jh7110_clk.c

174

reg |= idx << JH7110_MUX_SHIFT;

sys/dev/clk/starfive/jh7110_clk.c

175

WRITE4(sc, sc_clk->offset, reg);

sys/dev/cpuctl/cpuctl.c

254

uint64_t reg;

sys/dev/cpuctl/cpuctl.c

282

ret = rdmsr_safe(data->msr, &reg);

sys/dev/cpuctl/cpuctl.c

284

ret = wrmsr_safe(data->msr, reg | data->data);

sys/dev/cpuctl/cpuctl.c

288

ret = rdmsr_safe(data->msr, &reg);

sys/dev/cpuctl/cpuctl.c

290

ret = wrmsr_safe(data->msr, reg & ~data->data);

sys/dev/cpufreq/cpufreq_dt.c

193

error = regulator_get_voltage(sc->reg, &uvolt);

sys/dev/cpufreq/cpufreq_dt.c

225

error = regulator_set_voltage(sc->reg,

sys/dev/cpufreq/cpufreq_dt.c

240

error = regulator_set_voltage(sc->reg,

sys/dev/cpufreq/cpufreq_dt.c

249

error = regulator_set_voltage(sc->reg,

sys/dev/cpufreq/cpufreq_dt.c

487

sc->reg = NULL;

sys/dev/cpufreq/cpufreq_dt.c

502

&sc->reg) == 0)

sys/dev/cpufreq/cpufreq_dt.c

505

&sc->reg) == 0)

sys/dev/cpufreq/cpufreq_dt.c

601

regulator_release(sc->reg);

sys/dev/cpufreq/cpufreq_dt.c

71

#define CPUFREQ_DT_HAVE_REGULATOR(sc) ((sc)->reg != NULL)

sys/dev/cpufreq/cpufreq_dt.c

76

regulator_t reg;

sys/dev/cpufreq/ichss.c

86

#define ICH_GET_REG(reg) \

sys/dev/cpufreq/ichss.c

87

(bus_space_read_1(rman_get_bustag((reg)), \

sys/dev/cpufreq/ichss.c

88

rman_get_bushandle((reg)), 0))

sys/dev/cpufreq/ichss.c

89

#define ICH_SET_REG(reg, val) \

sys/dev/cpufreq/ichss.c

90

(bus_space_write_1(rman_get_bustag((reg)), \

sys/dev/cpufreq/ichss.c

91

rman_get_bushandle((reg)), 0, (val)))

sys/dev/cxgb/common/cxgb_aq100x.c

118

int reg;

sys/dev/cxgb/common/cxgb_aq100x.c

136

int reg;

sys/dev/cxgb/common/cxgb_aq100x.c

154

int reg;

sys/dev/cxgb/common/cxgb_aq100x.c

69

(void) mdio_write(phy, regs[i].mmd, regs[i].reg, regs[i].val); \

sys/dev/cxgb/common/cxgb_aq100x.c

75

(void) mdio_read(phy, regs[i].mmd, regs[i].reg, &v); \

sys/dev/cxgb/common/cxgb_common.h

590

static inline int mdio_read(struct cphy *phy, int mmd, int reg,

sys/dev/cxgb/common/cxgb_common.h

593

return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp);

sys/dev/cxgb/common/cxgb_common.h

596

static inline int mdio_write(struct cphy *phy, int mmd, int reg,

sys/dev/cxgb/common/cxgb_common.h

599

return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);

sys/dev/cxgb/common/cxgb_common.h

679

int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity,

sys/dev/cxgb/common/cxgb_common.h

682

static inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask,

sys/dev/cxgb/common/cxgb_common.h

685

return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,

sys/dev/cxgb/common/cxgb_common.h

689

int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,

sys/dev/cxgb/common/cxgb_t3_hw.c

1744

static int t3_handle_intr_status(adapter_t *adapter, unsigned int reg,

sys/dev/cxgb/common/cxgb_t3_hw.c

1750

unsigned int status = t3_read_reg(adapter, reg) & mask;

sys/dev/cxgb/common/cxgb_t3_hw.c

1766

t3_write_reg(adapter, reg, status);

sys/dev/cxgb/common/cxgb_t3_hw.c

3094

#define mem_region(adap, start, size, reg) \

sys/dev/cxgb/common/cxgb_t3_hw.c

3095

t3_write_reg((adap), A_ ## reg, (start)); \

sys/dev/cxgb/common/cxgb_t3_hw.c

369

int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,

sys/dev/cxgb/common/cxgb_t3_hw.c

375

ret = mdio_read(phy, mmd, reg, &val);

sys/dev/cxgb/common/cxgb_t3_hw.c

378

ret = mdio_write(phy, mmd, reg, val | set);

sys/dev/cxgb/common/cxgb_t3_hw.c

52

int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity,

sys/dev/cxgb/common/cxgb_t3_hw.c

56

u32 val = t3_read_reg(adapter, reg);

sys/dev/cxgb/common/cxgb_vsc7323.c

282

#define ELMR_STAT(port, reg) (ELMR_STATS + port * 0x40 + reg)

sys/dev/cxgb/common/cxgb_vsc7323.c

48

#define VSC_REG(block, subblock, reg) \

sys/dev/cxgb/common/cxgb_vsc7323.c

49

((reg) | ((subblock) << 8) | ((block) << 12))

sys/dev/cxgb/common/cxgb_xgmac.c

367

unsigned int i, reg = mac->offset + A_XGM_RX_EXACT_MATCH_LOW_1;

sys/dev/cxgb/common/cxgb_xgmac.c

369

for (i = 0; i < EXACT_ADDR_FILTERS; i++, reg += 8) {

sys/dev/cxgb/common/cxgb_xgmac.c

370

u32 v = t3_read_reg(mac->adapter, reg);

sys/dev/cxgb/common/cxgb_xgmac.c

371

t3_write_reg(mac->adapter, reg, v);

sys/dev/cxgb/common/cxgb_xgmac.c

378

unsigned int i, reg = mac->offset + A_XGM_RX_EXACT_MATCH_HIGH_1;

sys/dev/cxgb/common/cxgb_xgmac.c

380

for (i = 0; i < EXACT_ADDR_FILTERS; i++, reg += 8) {

sys/dev/cxgb/common/cxgb_xgmac.c

381

u32 v = t3_read_reg(mac->adapter, reg);

sys/dev/cxgb/common/cxgb_xgmac.c

382

t3_write_reg(mac->adapter, reg, v);

sys/dev/cxgb/common/cxgb_xgmac.c

477

unsigned int thres, v, reg;

sys/dev/cxgb/common/cxgb_xgmac.c

509

reg = adap->params.rev == T3_REV_B2 ?

sys/dev/cxgb/common/cxgb_xgmac.c

513

if (t3_wait_op_done(adap, reg + mac->offset,

sys/dev/cxgb/common/cxgb_xgmac.c

801

#define RMON_UPDATE(mac, name, reg) \

sys/dev/cxgb/common/cxgb_xgmac.c

802

(mac)->stats.name += (u64)RMON_READ(mac, A_XGM_STAT_##reg)

sys/dev/cxgb/cxgb_adapter.h

441

t3_os_pci_read_config_4(adapter_t *adapter, int reg, uint32_t *val)

sys/dev/cxgb/cxgb_adapter.h

443

*val = pci_read_config(adapter->dev, reg, 4);

sys/dev/cxgb/cxgb_adapter.h

447

t3_os_pci_write_config_4(adapter_t *adapter, int reg, uint32_t val)

sys/dev/cxgb/cxgb_adapter.h

449

pci_write_config(adapter->dev, reg, val, 4);

sys/dev/cxgb/cxgb_adapter.h

453

t3_os_pci_read_config_2(adapter_t *adapter, int reg, uint16_t *val)

sys/dev/cxgb/cxgb_adapter.h

455

*val = pci_read_config(adapter->dev, reg, 2);

sys/dev/cxgb/cxgb_adapter.h

459

t3_os_pci_write_config_2(adapter_t *adapter, int reg, uint16_t val)

sys/dev/cxgb/cxgb_adapter.h

461

pci_write_config(adapter->dev, reg, val, 2);

sys/dev/cxgb/cxgb_main.c

1139

int rc, reg = 0;

sys/dev/cxgb/cxgb_main.c

1141

rc = pci_find_cap(sc->dev, cap, &reg);

sys/dev/cxgb/cxgb_main.c

1142

return (rc == 0 ? reg : 0);

sys/dev/cxgb/cxgb_main.c

446

int msi_needed, reg;

sys/dev/cxgb/cxgb_main.c

473

if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {

sys/dev/cxgb/cxgb_main.c

476

lnk = pci_read_config(dev, reg + PCIER_LINK_STA, 2);

sys/dev/cxgbe/adapter.h

1273

t4_read_reg(struct adapter *sc, uint32_t reg)

sys/dev/cxgbe/adapter.h

1277

return bus_read_4(sc->regs_res, reg);

sys/dev/cxgbe/adapter.h

1281

t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)

sys/dev/cxgbe/adapter.h

1285

bus_write_4(sc->regs_res, reg, val);

sys/dev/cxgbe/adapter.h

1289

t4_read_reg64(struct adapter *sc, uint32_t reg)

sys/dev/cxgbe/adapter.h

1294

return bus_read_8(sc->regs_res, reg);

sys/dev/cxgbe/adapter.h

1296

return (uint64_t)bus_read_4(sc->regs_res, reg) +

sys/dev/cxgbe/adapter.h

1297

((uint64_t)bus_read_4(sc->regs_res, reg + 4) << 32);

sys/dev/cxgbe/adapter.h

1303

t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)

sys/dev/cxgbe/adapter.h

1308

bus_write_8(sc->regs_res, reg, val);

sys/dev/cxgbe/adapter.h

1310

bus_write_4(sc->regs_res, reg, val);

sys/dev/cxgbe/adapter.h

1311

bus_write_4(sc->regs_res, reg + 4, val>> 32);

sys/dev/cxgbe/adapter.h

1316

t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)

sys/dev/cxgbe/adapter.h

1320

*val = pci_read_config(sc->dev, reg, 1);

sys/dev/cxgbe/adapter.h

1324

t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)

sys/dev/cxgbe/adapter.h

1328

pci_write_config(sc->dev, reg, val, 1);

sys/dev/cxgbe/adapter.h

1332

t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)

sys/dev/cxgbe/adapter.h

1337

*val = pci_read_config(sc->dev, reg, 2);

sys/dev/cxgbe/adapter.h

1341

t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)

sys/dev/cxgbe/adapter.h

1345

pci_write_config(sc->dev, reg, val, 2);

sys/dev/cxgbe/adapter.h

1349

t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)

sys/dev/cxgbe/adapter.h

1353

*val = pci_read_config(sc->dev, reg, 4);

sys/dev/cxgbe/adapter.h

1357

t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)

sys/dev/cxgbe/adapter.h

1361

pci_write_config(sc->dev, reg, val, 4);

sys/dev/cxgbe/adapter.h

1398

CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg,

sys/dev/cxgbe/adapter.h

1418

(long long)t4_read_reg64(sc, reg),

sys/dev/cxgbe/adapter.h

1419

(long long)t4_read_reg64(sc, reg + 8),

sys/dev/cxgbe/adapter.h

1420

(long long)t4_read_reg64(sc, reg + 16),

sys/dev/cxgbe/adapter.h

1421

(long long)t4_read_reg64(sc, reg + 24),

sys/dev/cxgbe/adapter.h

1422

(long long)t4_read_reg64(sc, reg + 32),

sys/dev/cxgbe/adapter.h

1423

(long long)t4_read_reg64(sc, reg + 40),

sys/dev/cxgbe/adapter.h

1424

(long long)t4_read_reg64(sc, reg + 48),

sys/dev/cxgbe/adapter.h

1425

(long long)t4_read_reg64(sc, reg + 56));

sys/dev/cxgbe/common/common.h

683

u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg);

sys/dev/cxgbe/common/common.h

819

u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach);

sys/dev/cxgbe/common/common.h

836

u32 t4_port_reg(struct adapter *adap, u8 port, u32 reg);

sys/dev/cxgbe/common/common.h

962

unsigned int mmd, unsigned int reg, unsigned int *valp);

sys/dev/cxgbe/common/common.h

964

unsigned int mmd, unsigned int reg, unsigned int val);

sys/dev/cxgbe/common/t4_hw.c

101

static int t7_wait_sram_done(struct adapter *adap, int reg, int result_reg,

sys/dev/cxgbe/common/t4_hw.c

105

u32 val = t4_read_reg(adap, reg);

sys/dev/cxgbe/common/t4_hw.c

196

u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg)

sys/dev/cxgbe/common/t4_hw.c

198

u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg);

sys/dev/cxgbe/common/t4_hw.c

281

t4_port_reg(struct adapter *adap, u8 port, u32 reg)

sys/dev/cxgbe/common/t4_hw.c

284

return T7_PORT_REG(port, reg);

sys/dev/cxgbe/common/t4_hw.c

286

return T5_PORT_REG(port, reg);

sys/dev/cxgbe/common/t4_hw.c

287

return PORT_REG(port, reg);

sys/dev/cxgbe/common/t4_hw.c

3379

unsigned int reg = reg_ranges[range];

sys/dev/cxgbe/common/t4_hw.c

3381

u32 *bufp = (u32 *)(buf + reg);

sys/dev/cxgbe/common/t4_hw.c

3387

while (reg <= last_reg && bufp < buf_end) {

sys/dev/cxgbe/common/t4_hw.c

3388

*bufp++ = t4_read_reg(adap, reg);

sys/dev/cxgbe/common/t4_hw.c

3389

reg += sizeof(u32);

sys/dev/cxgbe/common/t4_hw.c

62

static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,

sys/dev/cxgbe/common/t4_hw.c

6536

t7_tlstx_reg(u8 instance, u8 channel, u32 reg)

sys/dev/cxgbe/common/t4_hw.c

6541

TLS_TX_CH_REG(reg, channel));

sys/dev/cxgbe/common/t4_hw.c

66

u32 val = t4_read_reg(adapter, reg);

sys/dev/cxgbe/common/t4_hw.c

772

u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach)

sys/dev/cxgbe/common/t4_hw.c

793

ldst_cmd.u.pcie.r = reg;

sys/dev/cxgbe/common/t4_hw.c

80

static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,

sys/dev/cxgbe/common/t4_hw.c

806

reg, -ret);

sys/dev/cxgbe/common/t4_hw.c

813

return t4_hw_pci_read_cfg4(adap, reg);

sys/dev/cxgbe/common/t4_hw.c

83

return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,

sys/dev/cxgbe/common/t4_hw.c

9024

unsigned int mmd, unsigned int reg, unsigned int *valp)

sys/dev/cxgbe/common/t4_hw.c

9038

c.u.mdio.raddr = cpu_to_be16(reg);

sys/dev/cxgbe/common/t4_hw.c

9058

unsigned int mmd, unsigned int reg, unsigned int val)

sys/dev/cxgbe/common/t4_hw.c

9071

c.u.mdio.raddr = cpu_to_be16(reg);

sys/dev/cxgbe/common/t4_regs.h

286

#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))

sys/dev/cxgbe/common/t4_regs.h

515

#define T7_PORT_REG(idx, reg) (T7_PORT_BASE(idx) + (reg))

sys/dev/cxgbe/common/t4_regs.h

65

#define PF_REG(idx, reg) (PF_BASE(idx) + (reg))

sys/dev/cxgbe/common/t4_regs.h

656

#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)

sys/dev/cxgbe/common/t4_regs.h

659

#define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx)

sys/dev/cxgbe/common/t4_regs.h

662

#define MC_REG(reg, idx) (reg + MC_STRIDE * idx)

sys/dev/cxgbe/common/t4_regs.h

665

#define MC_T7_REG(reg, idx) (reg + MC_T7_STRIDE * idx)

sys/dev/cxgbe/common/t4_regs.h

99

#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))

sys/dev/cxgbe/cudbg/cudbg_lib.c

963

#define ulp_region(reg) \

sys/dev/cxgbe/cudbg/cudbg_lib.c

965

md->base = t4_read_reg(padap, A_ULP_ ## reg ## _LLIMIT);\

sys/dev/cxgbe/cudbg/cudbg_lib.c

966

(md++)->limit = t4_read_reg(padap, A_ULP_ ## reg ## _ULIMIT);\

sys/dev/cxgbe/t4_iov.c

145

t4iov_read_reg(struct t4iov_softc *sc, uint32_t reg)

sys/dev/cxgbe/t4_iov.c

148

return bus_read_4(sc->regs_res, reg);

sys/dev/cxgbe/t4_main.c

10634

#define ulp_region(reg) do {\

sys/dev/cxgbe/t4_main.c

10636

md->base = (uint64_t)t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT) << shift; \

sys/dev/cxgbe/t4_main.c

10637

md->limit = (uint64_t)t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) << shift; \

sys/dev/cxgbe/t4_main.c

12369

int rc, reg = arg2;

sys/dev/cxgbe/t4_main.c

12374

MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||

sys/dev/cxgbe/t4_main.c

12375

reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||

sys/dev/cxgbe/t4_main.c

12376

reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||

sys/dev/cxgbe/t4_main.c

12377

reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);

sys/dev/cxgbe/t4_main.c

12386

if (reg == A_TP_INIT_SRTT)

sys/dev/cxgbe/t4_main.c

12387

v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));

sys/dev/cxgbe/t4_main.c

12389

v = tp_tick_us * t4_read_reg(sc, reg);

sys/dev/cxgbe/t4_main.c

13856

uint32_t base, j, off, pf, reg, save, win_pos;

sys/dev/cxgbe/t4_main.c

13858

reg = chip_id(sc) > CHELSIO_T6 ?

sys/dev/cxgbe/t4_main.c

13861

save = t4_read_reg(sc, reg);

sys/dev/cxgbe/t4_main.c

13874

t4_write_reg(sc, reg, win_pos | pf);

sys/dev/cxgbe/t4_main.c

13875

t4_read_reg(sc, reg);

sys/dev/cxgbe/t4_main.c

13891

t4_write_reg(sc, reg, save);

sys/dev/cxgbe/t4_main.c

13892

t4_read_reg(sc, reg);

sys/dev/cxgbe/t4_main.c

4108

uint32_t bar0, reg;

sys/dev/cxgbe/t4_main.c

4136

reg = chip_id(sc) > CHELSIO_T6 ?

sys/dev/cxgbe/t4_main.c

4139

t4_write_reg(sc, reg, (mw->mw_base + bar0) | V_BIR(0) |

sys/dev/cxgbe/t4_main.c

4147

t4_read_reg(sc, reg);

sys/dev/cxgbe/t4_main.c

4160

uint32_t pf, reg, val;

sys/dev/cxgbe/t4_main.c

4174

reg = PCIE_MEM_ACCESS_T7_REG(A_PCIE_MEM_ACCESS_OFFSET0, idx);

sys/dev/cxgbe/t4_main.c

4177

reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);

sys/dev/cxgbe/t4_main.c

4180

t4_write_reg(sc, reg, val);

sys/dev/cxgbe/t4_main.c

4181

t4_read_reg(sc, reg); /* flush */

sys/dev/cxgbe/t4_main.c

7559

read_vf_stat(struct adapter *sc, u_int vin, int reg)

sys/dev/cxgbe/t4_main.c

7564

stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));

sys/dev/cxgbe/t4_main.c

7565

stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));

sys/dev/cxgbe/t4_main.c

7569

V_PL_VFID(vin) | V_PL_ADDR(VF_MPS_REG(reg)));

sys/dev/cxgbe/t4_main.c

7610

int reg;

sys/dev/cxgbe/t4_main.c

7614

for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;

sys/dev/cxgbe/t4_main.c

7615

reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)

sys/dev/cxgbe/t4_main.c

9223

int rc, reg = arg2;

sys/dev/cxgbe/t4_main.c

9231

val = t4_read_reg64(sc, reg);

sys/dev/cxgbe/t4_main.c

9244

int rc, i, reg = arg2;

sys/dev/cxgbe/t4_main.c

9254

t4_port_reg(sc, pi->tx_chan + i, reg));

sys/dev/cxgbe/t4_sge.c

743

int i, reg;

sys/dev/cxgbe/t4_sge.c

780

reg = A_SGE_FL_BUFFER_SIZE2;

sys/dev/cxgbe/t4_sge.c

782

MPASS(reg <= A_SGE_FL_BUFFER_SIZE15);

sys/dev/cxgbe/t4_sge.c

783

t4_write_reg(sc, reg, sw_buf_sizes[i]);

sys/dev/cxgbe/t4_sge.c

784

reg += 4;

sys/dev/cxgbe/t4_sge.c

785

MPASS(reg <= A_SGE_FL_BUFFER_SIZE15);

sys/dev/cxgbe/t4_sge.c

786

t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE);

sys/dev/cxgbe/t4_sge.c

787

reg += 4;

sys/dev/cxgbe/t4_vf.c

825

int reg;

sys/dev/cxgbe/t4_vf.c

827

for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;

sys/dev/cxgbe/t4_vf.c

828

reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)

sys/dev/cxgbe/t4_vf.c

829

t4_write_reg(sc, VF_MPS_REG(reg), 0);

sys/dev/cyapa/cyapa.c

285

cyapa_read_bytes(device_t dev, uint8_t reg, uint8_t *val, int cnt)

sys/dev/cyapa/cyapa.c

289

{ addr, IIC_M_WR | IIC_M_NOSTOP, 1, &reg },

sys/dev/cyapa/cyapa.c

297

cyapa_write_bytes(device_t dev, uint8_t reg, const uint8_t *val, int cnt)

sys/dev/cyapa/cyapa.c

301

{ addr, IIC_M_WR | IIC_M_NOSTOP, 1, &reg },

sys/dev/dc/dcphy.c

189

int reg;

sys/dev/dc/dcphy.c

261

reg = CSR_READ_4(dc_sc, DC_10BTSTAT);

sys/dev/dc/dcphy.c

262

if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))

sys/dev/dc/dcphy.c

73

#define DC_SETBIT(sc, reg, x) \

sys/dev/dc/dcphy.c

74

CSR_WRITE_4(sc, reg, \

sys/dev/dc/dcphy.c

75

CSR_READ_4(sc, reg) | x)

sys/dev/dc/dcphy.c

77

#define DC_CLRBIT(sc, reg, x) \

sys/dev/dc/dcphy.c

78

CSR_WRITE_4(sc, reg, \

sys/dev/dc/dcphy.c

79

CSR_READ_4(sc, reg) & ~x)

sys/dev/dc/if_dc.c

1605

uint32_t reg;

sys/dev/dc/if_dc.c

1619

reg = (p[0] | (p[1] << 8)) << 16;

sys/dev/dc/if_dc.c

1620

CSR_WRITE_4(sc, DC_WATCHDOG, reg);

sys/dev/dc/if_dc.c

1624

reg = (p[0] | (p[1] << 8)) << 16;

sys/dev/dc/if_dc.c

1625

CSR_WRITE_4(sc, DC_WATCHDOG, reg);

sys/dev/dc/if_dc.c

2031

uint32_t reg, revision;

sys/dev/dc/if_dc.c

2293

reg = CSR_READ_4(sc, DC_AL_PAR0);

sys/dev/dc/if_dc.c

2295

mac[0] = (reg >> 0) & 0xff;

sys/dev/dc/if_dc.c

2296

mac[1] = (reg >> 8) & 0xff;

sys/dev/dc/if_dc.c

2297

mac[2] = (reg >> 16) & 0xff;

sys/dev/dc/if_dc.c

2298

mac[3] = (reg >> 24) & 0xff;

sys/dev/dc/if_dc.c

2299

reg = CSR_READ_4(sc, DC_AL_PAR1);

sys/dev/dc/if_dc.c

2300

mac[4] = (reg >> 0) & 0xff;

sys/dev/dc/if_dc.c

2301

mac[5] = (reg >> 8) & 0xff;

sys/dev/dc/if_dc.c

356

#define DC_SETBIT(sc, reg, x) \

sys/dev/dc/if_dc.c

357

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/dc/if_dc.c

359

#define DC_CLRBIT(sc, reg, x) \

sys/dev/dc/if_dc.c

360

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/dc/if_dc.c

652

dc_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/dc/if_dc.c

661

switch (reg) {

sys/dev/dc/if_dc.c

685

(phy << 23) | (reg << 18));

sys/dev/dc/if_dc.c

700

((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) |

sys/dev/dc/if_dc.c

715

switch (reg) {

sys/dev/dc/if_dc.c

739

reg);

sys/dev/dc/if_dc.c

753

rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg);

sys/dev/dc/if_dc.c

761

dc_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/dc/if_dc.c

770

(phy << 23) | (reg << 10) | data);

sys/dev/dc/if_dc.c

781

((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) |

sys/dev/dc/if_dc.c

789

switch (reg) {

sys/dev/dc/if_dc.c

813

reg);

sys/dev/dc/if_dc.c

826

mii_bitbang_writereg(dev, &dc_mii_bitbang_ops, phy, reg, data);

sys/dev/dc/if_dcreg.h

805

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/dc/if_dcreg.h

806

bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val)

sys/dev/dc/if_dcreg.h

808

#define CSR_READ_4(sc, reg) \

sys/dev/dc/if_dcreg.h

809

bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg)

sys/dev/dc/if_dcreg.h

811

#define CSR_BARRIER_4(sc, reg, flags) \

sys/dev/dc/if_dcreg.h

812

bus_space_barrier(sc->dc_btag, sc->dc_bhandle, reg, 4, flags)

sys/dev/dc/pnphy.c

199

int reg;

sys/dev/dc/pnphy.c

207

reg = CSR_READ_4(dc_sc, DC_ISR);

sys/dev/dc/pnphy.c

208

if (!(reg & DC_ISR_LINKFAIL))

sys/dev/dc/pnphy.c

210

reg = CSR_READ_4(dc_sc, DC_NETCFG);

sys/dev/dc/pnphy.c

211

if (reg & DC_NETCFG_SPEEDSEL)

sys/dev/dc/pnphy.c

215

if (reg & DC_NETCFG_FULLDUPLEX)

sys/dev/dialog/da9063/da9063_iic.c

157

uint8_t reg;

sys/dev/dialog/da9063/da9063_iic.c

168

error = iicdev_readfrom(dev, DA9063_IIC_PAGE_OFF(addr), &reg, 1,

sys/dev/dialog/da9063/da9063_iic.c

175

reg &= ~clear_mask;

sys/dev/dialog/da9063/da9063_iic.c

176

reg |= set_mask;

sys/dev/dialog/da9063/da9063_iic.c

178

error = iicdev_writeto(dev, DA9063_IIC_PAGE_OFF(addr), &reg, 1,

sys/dev/dialog/da9063/da9063_iic.c

207

uint8_t reg;

sys/dev/dialog/da9063/da9063_iic.c

214

error = iicdev_readfrom(dev, DA9063_PAGE_CON, &reg, 1, IIC_WAIT);

sys/dev/dialog/da9063/da9063_iic.c

218

sc->page = ((reg >> DA9063_PAGE_CON_REG_PAGE_SHIFT) &

sys/dev/dialog/da9063/da9063_iic.c

76

uint8_t reg;

sys/dev/dialog/da9063/da9063_iic.c

84

error = iicdev_readfrom(sc->dev, DA9063_PAGE_CON, &reg, 1, IIC_WAIT);

sys/dev/dialog/da9063/da9063_iic.c

88

reg &= ~(DA9063_PAGE_CON_REG_PAGE_MASK <<

sys/dev/dialog/da9063/da9063_iic.c

90

reg |= (page << DA9063_IIC_PAGE_CON_REG_PAGE_SHIFT) <<

sys/dev/dialog/da9063/da9063_iic.c

93

error = iicdev_writeto(sc->dev, DA9063_PAGE_CON, &reg, 1, IIC_WAIT);

sys/dev/dpaa/fman_mdio.c

155

pqmdio_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/dpaa/fman_mdio.c

164

MDIO_WRITE4(sc, MDIO_MIIMADD, (phy << 8) | reg);

sys/dev/dpaa/fman_mdio.c

182

pqmdio_miibus_writereg(device_t dev, int phy, int reg, int value)

sys/dev/dpaa/fman_mdio.c

193

MDIO_WRITE4(sc, MDIO_MIIMADD, (phy << 8) | reg);

sys/dev/dpaa/fman_mdio.c

74

static int pqmdio_miibus_readreg(device_t dev, int phy, int reg);

sys/dev/dpaa/fman_mdio.c

75

static int pqmdio_miibus_writereg(device_t dev, int phy, int reg, int value);

sys/dev/dpaa/if_dtsec.c

822

dtsec_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/dpaa/if_dtsec.c

828

return (MIIBUS_READREG(sc->sc_mdio, phy, reg));

sys/dev/dpaa/if_dtsec.c

832

dtsec_miibus_writereg(device_t dev, int phy, int reg, int value)

sys/dev/dpaa/if_dtsec.c

839

return (MIIBUS_WRITEREG(sc->sc_mdio, phy, reg, value));

sys/dev/dpaa/if_dtsec.h

148

int dtsec_miibus_readreg(device_t dev, int phy, int reg);

sys/dev/dpaa/if_dtsec.h

149

int dtsec_miibus_writereg(device_t dev, int phy, int reg,

sys/dev/dpaa2/dpaa2_mc_acpi.c

105

s = device_get_property(dev, "reg", &sc->reg, sizeof(sc->reg),

sys/dev/dpaa2/dpaa2_mc_acpi.c

124

sc->uid, sc->reg, sc->managed[0] != '\0' ? sc->managed : "",

sys/dev/dpaa2/dpaa2_mc_acpi.c

65

uint64_t reg;

sys/dev/dpaa2/dpaa2_mc_acpi.c

75

uint64_t reg;

sys/dev/dpaa2/dpaa2_mc_acpi.c

78

s = device_get_property(dev, "reg", &reg, sizeof(reg),

sys/dev/dpaa2/dpaa2_mc_fdt.c

105

s = device_get_property(dev, "reg", &reg, sizeof(reg),

sys/dev/dpaa2/dpaa2_mc_fdt.c

127

s = device_get_property(dev, "reg", &sc->reg, sizeof(sc->reg),

sys/dev/dpaa2/dpaa2_mc_fdt.c

151

sc->reg, sc->sfp, sc->pcs_handle, sc->phy_handle,

sys/dev/dpaa2/dpaa2_mc_fdt.c

166

if (sc->reg == id)

sys/dev/dpaa2/dpaa2_mc_fdt.c

62

uint32_t reg;

sys/dev/dpaa2/dpaa2_mc_fdt.c

74

reg = <0x1>;

sys/dev/dpaa2/dpaa2_mc_fdt.c

83

reg = <0x3>;

sys/dev/dpaa2/dpaa2_mc_fdt.c

95

uint64_t reg;

sys/dev/dpaa2/dpaa2_rc.c

2295

uint8_t phy, uint16_t reg, uint16_t *val)

sys/dev/dpaa2/dpaa2_rc.c

2300

uint16_t reg;

sys/dev/dpaa2/dpaa2_rc.c

2312

args->reg = reg;

sys/dev/dpaa2/dpaa2_rc.c

2324

uint8_t phy, uint16_t reg, uint16_t val)

sys/dev/dpaa2/dpaa2_rc.c

2329

uint16_t reg;

sys/dev/dpaa2/dpaa2_rc.c

2341

args->reg = reg;

sys/dev/dpaa2/dpaa2_rc.c

2990

struct dpaa2_rc_obj_region reg;

sys/dev/dpaa2/dpaa2_rc.c

3071

i, obj->type, &reg);

sys/dev/dpaa2/dpaa2_rc.c

3078

count = reg.size;

sys/dev/dpaa2/dpaa2_rc.c

3079

start = reg.base_paddr + reg.base_offset;

sys/dev/dpaa2/dpaa2_rc.c

3080

end = reg.base_paddr + reg.base_offset + reg.size - 1;

sys/dev/dpaa2/dpaa2_rc.c

881

struct dpaa2_rc_obj_region *reg)

sys/dev/dpaa2/dpaa2_rc.c

906

if (portal == NULL || cmd == NULL || reg == NULL)

sys/dev/dpaa2/dpaa2_rc.c

949

reg->base_paddr = resp->base_paddr;

sys/dev/dpaa2/dpaa2_rc.c

950

reg->base_offset = resp->base_offset;

sys/dev/dpaa2/dpaa2_rc.c

951

reg->size = resp->size;

sys/dev/dpaa2/dpaa2_rc.c

952

reg->flags = resp->flags;

sys/dev/dpaa2/dpaa2_rc.c

953

reg->type = resp->type & 0xFu;

sys/dev/dpaa2/dpaa2_swp.c

186

uint32_t reg, mask_size, eqcr_pi; /* EQCR producer index */

sys/dev/dpaa2/dpaa2_swp.c

235

reg = dpaa2_swp_set_cfg(

sys/dev/dpaa2/dpaa2_swp.c

249

reg &= ~(1 << DPAA2_SWP_CFG_CPBS_SHIFT); /* QMan-backed mode */

sys/dev/dpaa2/dpaa2_swp.c

254

reg = dpaa2_swp_set_cfg(

sys/dev/dpaa2/dpaa2_swp.c

269

reg &= ~(1 << DPAA2_SWP_CFG_CPBS_SHIFT); /* QMan-backed mode */

sys/dev/dpaa2/dpaa2_swp.c

271

dpaa2_swp_write_reg(p, DPAA2_SWP_CINH_CFG, reg);

sys/dev/dpaa2/dpaa2_swp.c

272

reg = dpaa2_swp_read_reg(p, DPAA2_SWP_CINH_CFG);

sys/dev/dpaa2/dpaa2_swp.c

273

if (!reg) {

sys/dev/dpaa2/memac_mdio_acpi.c

168

memac_acpi_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/dpaa2/memac_mdio_acpi.c

173

return (memac_miibus_readreg(&sc->scc, phy, reg));

sys/dev/dpaa2/memac_mdio_acpi.c

177

memac_acpi_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/dpaa2/memac_mdio_acpi.c

182

return (memac_miibus_writereg(&sc->scc, phy, reg, data));

sys/dev/dpaa2/memac_mdio_common.c

146

memac_read_4(struct memac_mdio_softc_common *sc, uint32_t reg)

sys/dev/dpaa2/memac_mdio_common.c

150

v = bus_read_4(sc->mem_res, reg);

sys/dev/dpaa2/memac_mdio_common.c

160

memac_write_4(struct memac_mdio_softc_common *sc, uint32_t reg, uint32_t val)

sys/dev/dpaa2/memac_mdio_common.c

168

bus_write_4(sc->mem_res, reg, v);

sys/dev/dpaa2/memac_mdio_common.c

190

memac_miibus_readreg(struct memac_mdio_softc_common *sc, int phy, int reg)

sys/dev/dpaa2/memac_mdio_common.c

205

ctl = MDIO_CTL_PORT_ADDR(phy) | MDIO_CTL_DEV_ADDR(reg);

sys/dev/dpaa2/memac_mdio_common.c

221

device_printf(sc->dev, "phy read %d:%d = %#06x\n", phy, reg, val);

sys/dev/dpaa2/memac_mdio_common.c

228

memac_miibus_writereg(struct memac_mdio_softc_common *sc, int phy, int reg, int data)

sys/dev/dpaa2/memac_mdio_common.c

233

device_printf(sc->dev, "phy write %d:%d\n", phy, reg);

sys/dev/dpaa2/memac_mdio_common.c

247

ctl = MDIO_CTL_PORT_ADDR(phy) | MDIO_CTL_DEV_ADDR(reg);

sys/dev/dpaa2/memac_mdio_common.c

53

memacphy_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/dpaa2/memac_mdio_common.c

56

return (MIIBUS_READREG(device_get_parent(dev), phy, reg));

sys/dev/dpaa2/memac_mdio_common.c

60

memacphy_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/dpaa2/memac_mdio_common.c

63

return (MIIBUS_WRITEREG(device_get_parent(dev), phy, reg, data));

sys/dev/dpaa2/memac_mdio_fdt.c

114

s = device_get_property(dev, "reg", &sc->reg, sizeof(sc->reg),

sys/dev/dpaa2/memac_mdio_fdt.c

117

sc->scc.phy = sc->reg;

sys/dev/dpaa2/memac_mdio_fdt.c

128

node, ofw_bus_get_name(dev), sc->reg, sc->xref, sc->scc.phy);

sys/dev/dpaa2/memac_mdio_fdt.c

173

memac_fdt_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/dpaa2/memac_mdio_fdt.c

178

return (memac_miibus_readreg(&sc->scc, phy, reg));

sys/dev/dpaa2/memac_mdio_fdt.c

182

memac_fdt_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/dpaa2/memac_mdio_fdt.c

187

return (memac_miibus_writereg(&sc->scc, phy, reg, data));

sys/dev/dpaa2/memac_mdio_fdt.c

60

uint32_t reg;

sys/dev/dwc/dwc1000_core.c

117

dwc1000_miibus_write_reg(device_t dev, int phy, int reg, int val)

sys/dev/dwc/dwc1000_core.c

126

| ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT)

sys/dev/dwc/dwc1000_core.c

148

uint32_t reg;

sys/dev/dwc/dwc1000_core.c

166

reg = READ4(sc, MAC_CONFIGURATION);

sys/dev/dwc/dwc1000_core.c

170

reg &= ~(CONF_FES | CONF_PS);

sys/dev/dwc/dwc1000_core.c

173

reg |= (CONF_FES | CONF_PS);

sys/dev/dwc/dwc1000_core.c

176

reg &= ~(CONF_FES);

sys/dev/dwc/dwc1000_core.c

177

reg |= (CONF_PS);

sys/dev/dwc/dwc1000_core.c

189

reg |= (CONF_DM);

sys/dev/dwc/dwc1000_core.c

191

reg &= ~(CONF_DM);

sys/dev/dwc/dwc1000_core.c

192

WRITE4(sc, MAC_CONFIGURATION, reg);

sys/dev/dwc/dwc1000_core.c

194

reg = FLOW_CONTROL_UP;

sys/dev/dwc/dwc1000_core.c

196

reg |= FLOW_CONTROL_TX;

sys/dev/dwc/dwc1000_core.c

198

reg |= FLOW_CONTROL_RX;

sys/dev/dwc/dwc1000_core.c

200

reg |= dwc_pause_time << FLOW_CONTROL_PT_SHIFT;

sys/dev/dwc/dwc1000_core.c

201

WRITE4(sc, FLOW_CONTROL, reg);

sys/dev/dwc/dwc1000_core.c

210

uint32_t reg;

sys/dev/dwc/dwc1000_core.c

215

reg = READ4(sc, MAC_CONFIGURATION);

sys/dev/dwc/dwc1000_core.c

216

reg |= (CONF_JD | CONF_ACS | CONF_BE);

sys/dev/dwc/dwc1000_core.c

217

WRITE4(sc, MAC_CONFIGURATION, reg);

sys/dev/dwc/dwc1000_core.c

223

uint32_t reg;

sys/dev/dwc/dwc1000_core.c

226

reg = READ4(sc, MAC_CONFIGURATION);

sys/dev/dwc/dwc1000_core.c

228

reg |= CONF_TE | CONF_RE;

sys/dev/dwc/dwc1000_core.c

230

reg &= ~(CONF_TE | CONF_RE);

sys/dev/dwc/dwc1000_core.c

231

WRITE4(sc, MAC_CONFIGURATION, reg);

sys/dev/dwc/dwc1000_core.c

237

uint32_t reg;

sys/dev/dwc/dwc1000_core.c

240

reg = READ4(sc, MAC_CONFIGURATION);

sys/dev/dwc/dwc1000_core.c

242

reg |= CONF_IPC;

sys/dev/dwc/dwc1000_core.c

244

reg &= ~CONF_IPC;

sys/dev/dwc/dwc1000_core.c

245

WRITE4(sc, MAC_CONFIGURATION, reg);

sys/dev/dwc/dwc1000_core.c

395

uint32_t reg;

sys/dev/dwc/dwc1000_core.c

397

reg = READ4(sc, MMC_CONTROL);

sys/dev/dwc/dwc1000_core.c

398

reg |= (MMC_CONTROL_CNTRST);

sys/dev/dwc/dwc1000_core.c

399

WRITE4(sc, MMC_CONTROL, reg);

sys/dev/dwc/dwc1000_core.c

433

uint32_t reg;

sys/dev/dwc/dwc1000_core.c

437

reg = READ4(sc, INTERRUPT_STATUS);

sys/dev/dwc/dwc1000_core.c

438

if (reg)

sys/dev/dwc/dwc1000_core.c

89

dwc1000_miibus_read_reg(device_t dev, int phy, int reg)

sys/dev/dwc/dwc1000_core.c

99

| ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT)

sys/dev/dwc/dwc1000_core.h

33

int dwc1000_miibus_read_reg(device_t dev, int phy, int reg);

sys/dev/dwc/dwc1000_core.h

34

int dwc1000_miibus_write_reg(device_t dev, int phy, int reg, int val);

sys/dev/dwc/dwc1000_dma.c

540

uint32_t reg;

sys/dev/dwc/dwc1000_dma.c

545

reg = READ4(sc, OPERATION_MODE);

sys/dev/dwc/dwc1000_dma.c

546

reg |= (MODE_TSF | MODE_OSF | MODE_FUF);

sys/dev/dwc/dwc1000_dma.c

547

reg &= ~(MODE_RSF);

sys/dev/dwc/dwc1000_dma.c

548

reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT);

sys/dev/dwc/dwc1000_dma.c

549

WRITE4(sc, OPERATION_MODE, reg);

sys/dev/dwc/dwc1000_dma.c

554

reg = READ4(sc, OPERATION_MODE);

sys/dev/dwc/dwc1000_dma.c

555

reg |= (MODE_ST | MODE_SR);

sys/dev/dwc/dwc1000_dma.c

556

WRITE4(sc, OPERATION_MODE, reg);

sys/dev/dwc/dwc1000_dma.c

565

uint32_t reg;

sys/dev/dwc/dwc1000_dma.c

570

reg = READ4(sc, OPERATION_MODE);

sys/dev/dwc/dwc1000_dma.c

571

reg &= ~(MODE_ST);

sys/dev/dwc/dwc1000_dma.c

572

WRITE4(sc, OPERATION_MODE, reg);

sys/dev/dwc/dwc1000_dma.c

575

reg = READ4(sc, OPERATION_MODE);

sys/dev/dwc/dwc1000_dma.c

576

reg |= (MODE_FTF);

sys/dev/dwc/dwc1000_dma.c

577

WRITE4(sc, OPERATION_MODE, reg);

sys/dev/dwc/dwc1000_dma.c

580

reg = READ4(sc, OPERATION_MODE);

sys/dev/dwc/dwc1000_dma.c

581

reg &= ~(MODE_SR);

sys/dev/dwc/dwc1000_dma.c

582

WRITE4(sc, OPERATION_MODE, reg);

sys/dev/dwc/dwc1000_dma.c

588

uint32_t reg;

sys/dev/dwc/dwc1000_dma.c

591

reg = READ4(sc, BUS_MODE);

sys/dev/dwc/dwc1000_dma.c

592

reg |= (BUS_MODE_SWR);

sys/dev/dwc/dwc1000_dma.c

593

WRITE4(sc, BUS_MODE, reg);

sys/dev/dwc/dwc1000_dma.c

614

uint32_t reg;

sys/dev/dwc/dwc1000_dma.c

619

reg = BUS_MODE_USP;

sys/dev/dwc/dwc1000_dma.c

621

reg |= BUS_MODE_EIGHTXPBL;

sys/dev/dwc/dwc1000_dma.c

622

reg |= (sc->txpbl << BUS_MODE_PBL_SHIFT);

sys/dev/dwc/dwc1000_dma.c

623

reg |= (sc->rxpbl << BUS_MODE_RPBL_SHIFT);

sys/dev/dwc/dwc1000_dma.c

625

reg |= BUS_MODE_FIXEDBURST;

sys/dev/dwc/dwc1000_dma.c

627

reg |= BUS_MODE_MIXEDBURST;

sys/dev/dwc/dwc1000_dma.c

629

reg |= BUS_MODE_AAL;

sys/dev/dwc/dwc1000_dma.c

631

WRITE4(sc, BUS_MODE, reg);

sys/dev/dwc/dwc1000_dma.c

633

reg = READ4(sc, HW_FEATURE);

sys/dev/dwc/dwc1000_dma.c

634

if (reg & HW_FEATURE_EXT_DESCRIPTOR)

sys/dev/dwc/dwc1000_dma.c

640

reg = READ4(sc, OPERATION_MODE);

sys/dev/dwc/dwc1000_dma.c

641

reg &= ~(MODE_ST | MODE_SR);

sys/dev/dwc/dwc1000_dma.c

642

WRITE4(sc, OPERATION_MODE, reg);

sys/dev/dwc/dwc1000_dma.c

856

uint32_t reg;

sys/dev/dwc/dwc1000_dma.c

862

reg = READ4(sc, DMA_STATUS);

sys/dev/dwc/dwc1000_dma.c

863

if (reg & DMA_STATUS_NIS) {

sys/dev/dwc/dwc1000_dma.c

864

if (reg & DMA_STATUS_RI)

sys/dev/dwc/dwc1000_dma.c

867

if (reg & DMA_STATUS_TI) {

sys/dev/dwc/dwc1000_dma.c

873

if (reg & DMA_STATUS_AIS) {

sys/dev/dwc/dwc1000_dma.c

874

if (reg & DMA_STATUS_FBI) {

sys/dev/dwc/dwc1000_dma.c

880

WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK);

sys/dev/dwc/if_dwc_aw.c

114

if (regulator_get_by_ofw_property(dev, 0, "phy-supply", &reg) == 0) {

sys/dev/dwc/if_dwc_aw.c

115

error = regulator_enable(reg);

sys/dev/dwc/if_dwc_aw.c

74

regulator_t reg;

sys/dev/dwc/if_dwc_rk.c

176

uint32_t reg;

sys/dev/dwc/if_dwc_rk.c

182

reg = SYSCON_READ_4(sc->grf, RK3328_GRF_MAC_CON0);

sys/dev/dwc/if_dwc_rk.c

183

tx = ((reg >> MAC_CON0_GMAC2IO_TX_DL_CFG_SHIFT) & MAC_CON0_GMAC2IO_TX_DL_CFG_MASK);

sys/dev/dwc/if_dwc_rk.c

184

rx = ((reg >> MAC_CON0_GMAC2IO_RX_DL_CFG_SHIFT) & MAC_CON0_GMAC2IO_RX_DL_CFG_MASK);

sys/dev/dwc/if_dwc_rk.c

186

reg = SYSCON_READ_4(sc->grf, RK3328_GRF_MAC_CON1);

sys/dev/dwc/if_dwc_rk.c

189

tx, ((reg & MAC_CON1_GMAC2IO_GMAC_TXCLK_DLY_ENA) ? "enabled" : "disabled"),

sys/dev/dwc/if_dwc_rk.c

190

rx, ((reg & MAC_CON1_GMAC2IO_GMAC_RXCLK_DLY_ENA) ? "enabled" : "disabled"));

sys/dev/dwc/if_dwc_rk.c

196

reg = (MAC_CON1_GMAC2IO_GMAC_TXCLK_DLY_ENA | MAC_CON1_GMAC2IO_GMAC_RXCLK_DLY_ENA) << 16;

sys/dev/dwc/if_dwc_rk.c

197

reg |= (MAC_CON1_GMAC2IO_GMAC_TXCLK_DLY_ENA | MAC_CON1_GMAC2IO_GMAC_RXCLK_DLY_ENA);

sys/dev/dwc/if_dwc_rk.c

198

SYSCON_WRITE_4(sc->grf, RK3328_GRF_MAC_CON1, reg);

sys/dev/dwc/if_dwc_rk.c

200

reg = 0xffff << 16;

sys/dev/dwc/if_dwc_rk.c

201

reg |= ((sc->tx_delay & MAC_CON0_GMAC2IO_TX_DL_CFG_MASK) <<

sys/dev/dwc/if_dwc_rk.c

203

reg |= ((sc->rx_delay & MAC_CON0_GMAC2IO_TX_DL_CFG_MASK) <<

sys/dev/dwc/if_dwc_rk.c

205

SYSCON_WRITE_4(sc->grf, RK3328_GRF_MAC_CON0, reg);

sys/dev/dwc/if_dwc_rk.c

211

uint32_t reg;

sys/dev/dwc/if_dwc_rk.c

221

reg = MAC_CON1_GMAC2IO_GMII_CLK_SEL_125;

sys/dev/dwc/if_dwc_rk.c

224

reg = MAC_CON1_GMAC2IO_GMII_CLK_SEL_25;

sys/dev/dwc/if_dwc_rk.c

227

reg = MAC_CON1_GMAC2IO_GMII_CLK_SEL_2_5;

sys/dev/dwc/if_dwc_rk.c

235

((MAC_CON1_GMAC2IO_GMII_CLK_SEL_MASK << 16) | reg));

sys/dev/dwc/if_dwc_rk.c

240

reg = MAC_CON1_GMAC2IO_RMII_CLK_SEL_25 |

sys/dev/dwc/if_dwc_rk.c

244

reg = MAC_CON1_GMAC2IO_RMII_CLK_SEL_2_5 |

sys/dev/dwc/if_dwc_rk.c

254

reg |

sys/dev/dwc/if_dwc_rk.c

294

uint32_t reg, tx, rx;

sys/dev/dwc/if_dwc_rk.c

299

reg = SYSCON_READ_4(sc->grf, RK3399_GRF_SOC_CON6);

sys/dev/dwc/if_dwc_rk.c

300

tx = ((reg >> SOC_CON6_TX_DL_CFG_SHIFT) & SOC_CON6_TX_DL_CFG_MASK);

sys/dev/dwc/if_dwc_rk.c

301

rx = ((reg >> SOC_CON6_RX_DL_CFG_SHIFT) & SOC_CON6_RX_DL_CFG_MASK);

sys/dev/dwc/if_dwc_rk.c

305

tx, ((reg & SOC_CON6_GMAC_TXCLK_DLY_ENA) ? "enabled" : "disabled"),

sys/dev/dwc/if_dwc_rk.c

306

rx, ((reg & SOC_CON6_GMAC_RXCLK_DLY_ENA) ? "enabled" : "disabled"));

sys/dev/dwc/if_dwc_rk.c

312

reg = 0xFFFF << 16;

sys/dev/dwc/if_dwc_rk.c

313

reg |= ((sc->tx_delay & SOC_CON6_TX_DL_CFG_MASK) <<

sys/dev/dwc/if_dwc_rk.c

315

reg |= ((sc->rx_delay & SOC_CON6_RX_DL_CFG_MASK) <<

sys/dev/dwc/if_dwc_rk.c

317

reg |= SOC_CON6_GMAC_TXCLK_DLY_ENA | SOC_CON6_GMAC_RXCLK_DLY_ENA;

sys/dev/dwc/if_dwc_rk.c

319

SYSCON_WRITE_4(sc->grf, RK3399_GRF_SOC_CON6, reg);

sys/dev/dwc/if_dwc_rk.c

325

uint32_t reg;

sys/dev/dwc/if_dwc_rk.c

330

reg = SOC_CON5_GMAC_CLK_SEL_125;

sys/dev/dwc/if_dwc_rk.c

333

reg = SOC_CON5_GMAC_CLK_SEL_25;

sys/dev/dwc/if_dwc_rk.c

336

reg = SOC_CON5_GMAC_CLK_SEL_2_5;

sys/dev/dwc/if_dwc_rk.c

344

((SOC_CON5_GMAC_CLK_SEL_MASK << 16) | reg));

sys/dev/dwwdt/dwwdt.c

61

#define DWWDT_READ4(sc, reg) bus_read_4((sc)->sc_mem_res, (reg))

sys/dev/dwwdt/dwwdt.c

62

#define DWWDT_WRITE4(sc, reg, val) \

sys/dev/dwwdt/dwwdt.c

63

bus_write_4((sc)->sc_mem_res, (reg), (val))

sys/dev/e1000/e1000_80003es2lan.c

1037

reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;

sys/dev/e1000/e1000_80003es2lan.c

1040

ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);

sys/dev/e1000/e1000_80003es2lan.c

1044

reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;

sys/dev/e1000/e1000_80003es2lan.c

1045

ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);

sys/dev/e1000/e1000_80003es2lan.c

1049

ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);

sys/dev/e1000/e1000_80003es2lan.c

1062

reg = E1000_READ_REG(hw, E1000_CTRL_EXT);

sys/dev/e1000/e1000_80003es2lan.c

1063

reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;

sys/dev/e1000/e1000_80003es2lan.c

1064

E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);

sys/dev/e1000/e1000_80003es2lan.c

923

u32 reg;

sys/dev/e1000/e1000_80003es2lan.c

928

reg = E1000_READ_REG(hw, E1000_TXDCTL(0));

sys/dev/e1000/e1000_80003es2lan.c

929

reg |= (1 << 22);

sys/dev/e1000/e1000_80003es2lan.c

930

E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);

sys/dev/e1000/e1000_80003es2lan.c

933

reg = E1000_READ_REG(hw, E1000_TXDCTL(1));

sys/dev/e1000/e1000_80003es2lan.c

934

reg |= (1 << 22);

sys/dev/e1000/e1000_80003es2lan.c

935

E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);

sys/dev/e1000/e1000_80003es2lan.c

938

reg = E1000_READ_REG(hw, E1000_TARC(0));

sys/dev/e1000/e1000_80003es2lan.c

939

reg &= ~(0xF << 27); /* 30:27 */

sys/dev/e1000/e1000_80003es2lan.c

941

reg &= ~(1 << 20);

sys/dev/e1000/e1000_80003es2lan.c

942

E1000_WRITE_REG(hw, E1000_TARC(0), reg);

sys/dev/e1000/e1000_80003es2lan.c

945

reg = E1000_READ_REG(hw, E1000_TARC(1));

sys/dev/e1000/e1000_80003es2lan.c

947

reg &= ~(1 << 28);

sys/dev/e1000/e1000_80003es2lan.c

949

reg |= (1 << 28);

sys/dev/e1000/e1000_80003es2lan.c

950

E1000_WRITE_REG(hw, E1000_TARC(1), reg);

sys/dev/e1000/e1000_80003es2lan.c

955

reg = E1000_READ_REG(hw, E1000_RFCTL);

sys/dev/e1000/e1000_80003es2lan.c

956

reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);

sys/dev/e1000/e1000_80003es2lan.c

957

E1000_WRITE_REG(hw, E1000_RFCTL, reg);

sys/dev/e1000/e1000_80003es2lan.c

972

u32 reg;

sys/dev/e1000/e1000_82542.c

448

u32 e1000_translate_register_82542(u32 reg)

sys/dev/e1000/e1000_82542.c

456

switch (reg) {

sys/dev/e1000/e1000_82542.c

458

reg = 0x00040;

sys/dev/e1000/e1000_82542.c

461

reg = 0x00108;

sys/dev/e1000/e1000_82542.c

464

reg = 0x00110;

sys/dev/e1000/e1000_82542.c

467

reg = 0x00114;

sys/dev/e1000/e1000_82542.c

470

reg = 0x00118;

sys/dev/e1000/e1000_82542.c

473

reg = 0x00120;

sys/dev/e1000/e1000_82542.c

476

reg = 0x00128;

sys/dev/e1000/e1000_82542.c

479

reg = 0x00138;

sys/dev/e1000/e1000_82542.c

482

reg = 0x0013C;

sys/dev/e1000/e1000_82542.c

485

reg = 0x00140;

sys/dev/e1000/e1000_82542.c

488

reg = 0x00148;

sys/dev/e1000/e1000_82542.c

491

reg = 0x00150;

sys/dev/e1000/e1000_82542.c

494

reg = 0x00160;

sys/dev/e1000/e1000_82542.c

497

reg = 0x00168;

sys/dev/e1000/e1000_82542.c

500

reg = 0x00200;

sys/dev/e1000/e1000_82542.c

503

reg = 0x00420;

sys/dev/e1000/e1000_82542.c

506

reg = 0x00424;

sys/dev/e1000/e1000_82542.c

509

reg = 0x00428;

sys/dev/e1000/e1000_82542.c

512

reg = 0x00430;

sys/dev/e1000/e1000_82542.c

515

reg = 0x00438;

sys/dev/e1000/e1000_82542.c

518

reg = 0x00440;

sys/dev/e1000/e1000_82542.c

521

reg = 0x00600;

sys/dev/e1000/e1000_82542.c

524

reg = 0x08010;

sys/dev/e1000/e1000_82542.c

527

reg = 0x08018;

sys/dev/e1000/e1000_82542.c

533

return reg;

sys/dev/e1000/e1000_82571.c

1152

u32 reg;

sys/dev/e1000/e1000_82571.c

1157

reg = E1000_READ_REG(hw, E1000_TXDCTL(0));

sys/dev/e1000/e1000_82571.c

1158

reg |= (1 << 22);

sys/dev/e1000/e1000_82571.c

1159

E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);

sys/dev/e1000/e1000_82571.c

1162

reg = E1000_READ_REG(hw, E1000_TXDCTL(1));

sys/dev/e1000/e1000_82571.c

1163

reg |= (1 << 22);

sys/dev/e1000/e1000_82571.c

1164

E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);

sys/dev/e1000/e1000_82571.c

1167

reg = E1000_READ_REG(hw, E1000_TARC(0));

sys/dev/e1000/e1000_82571.c

1168

reg &= ~(0xF << 27); /* 30:27 */

sys/dev/e1000/e1000_82571.c

1172

reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);

sys/dev/e1000/e1000_82571.c

1176

reg |= (1 << 26);

sys/dev/e1000/e1000_82571.c

1181

E1000_WRITE_REG(hw, E1000_TARC(0), reg);

sys/dev/e1000/e1000_82571.c

1184

reg = E1000_READ_REG(hw, E1000_TARC(1));

sys/dev/e1000/e1000_82571.c

1188

reg &= ~((1 << 29) | (1 << 30));

sys/dev/e1000/e1000_82571.c

1189

reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);

sys/dev/e1000/e1000_82571.c

1191

reg &= ~(1 << 28);

sys/dev/e1000/e1000_82571.c

1193

reg |= (1 << 28);

sys/dev/e1000/e1000_82571.c

1194

E1000_WRITE_REG(hw, E1000_TARC(1), reg);

sys/dev/e1000/e1000_82571.c

1205

reg = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_82571.c

1206

reg &= ~(1 << 29);

sys/dev/e1000/e1000_82571.c

1207

E1000_WRITE_REG(hw, E1000_CTRL, reg);

sys/dev/e1000/e1000_82571.c

1218

reg = E1000_READ_REG(hw, E1000_CTRL_EXT);

sys/dev/e1000/e1000_82571.c

1219

reg &= ~(1 << 23);

sys/dev/e1000/e1000_82571.c

1220

reg |= (1 << 22);

sys/dev/e1000/e1000_82571.c

1221

E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);

sys/dev/e1000/e1000_82571.c

1228

reg = E1000_READ_REG(hw, E1000_PBA_ECC);

sys/dev/e1000/e1000_82571.c

1229

reg |= E1000_PBA_ECC_CORR_EN;

sys/dev/e1000/e1000_82571.c

1230

E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);

sys/dev/e1000/e1000_82571.c

1238

reg = E1000_READ_REG(hw, E1000_CTRL_EXT);

sys/dev/e1000/e1000_82571.c

1239

reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;

sys/dev/e1000/e1000_82571.c

1240

E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);

sys/dev/e1000/e1000_82571.c

1247

reg = E1000_READ_REG(hw, E1000_RFCTL);

sys/dev/e1000/e1000_82571.c

1248

reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);

sys/dev/e1000/e1000_82571.c

1249

E1000_WRITE_REG(hw, E1000_RFCTL, reg);

sys/dev/e1000/e1000_82571.c

1256

reg = E1000_READ_REG(hw, E1000_GCR);

sys/dev/e1000/e1000_82571.c

1257

reg |= (1 << 22);

sys/dev/e1000/e1000_82571.c

1258

E1000_WRITE_REG(hw, E1000_GCR, reg);

sys/dev/e1000/e1000_82571.c

1266

reg = E1000_READ_REG(hw, E1000_GCR2);

sys/dev/e1000/e1000_82571.c

1267

reg |= 1;

sys/dev/e1000/e1000_82571.c

1268

E1000_WRITE_REG(hw, E1000_GCR2, reg);

sys/dev/e1000/e1000_82575.c

1167

u32 reg;

sys/dev/e1000/e1000_82575.c

1176

reg = E1000_READ_REG(hw, E1000_PCS_CFG0);

sys/dev/e1000/e1000_82575.c

1177

reg |= E1000_PCS_CFG_PCS_EN;

sys/dev/e1000/e1000_82575.c

1178

E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);

sys/dev/e1000/e1000_82575.c

1181

reg = E1000_READ_REG(hw, E1000_CTRL_EXT);

sys/dev/e1000/e1000_82575.c

1182

reg &= ~E1000_CTRL_EXT_SDP3_DATA;

sys/dev/e1000/e1000_82575.c

1183

E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);

sys/dev/e1000/e1000_82575.c

1265

u32 reg;

sys/dev/e1000/e1000_82575.c

1275

reg = E1000_READ_REG(hw, E1000_PCS_CFG0);

sys/dev/e1000/e1000_82575.c

1276

reg &= ~E1000_PCS_CFG_PCS_EN;

sys/dev/e1000/e1000_82575.c

1277

E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);

sys/dev/e1000/e1000_82575.c

1280

reg = E1000_READ_REG(hw, E1000_CTRL_EXT);

sys/dev/e1000/e1000_82575.c

1281

reg |= E1000_CTRL_EXT_SDP3_DATA;

sys/dev/e1000/e1000_82575.c

1282

E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);

sys/dev/e1000/e1000_82575.c

129

u32 reg = 0;

sys/dev/e1000/e1000_82575.c

137

reg = E1000_READ_REG(hw, E1000_MDIC);

sys/dev/e1000/e1000_82575.c

138

ext_mdio = !!(reg & E1000_MDIC_DEST);

sys/dev/e1000/e1000_82575.c

145

reg = E1000_READ_REG(hw, E1000_MDICNFG);

sys/dev/e1000/e1000_82575.c

146

ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);

sys/dev/e1000/e1000_82575.c

1496

u32 ctrl_ext, ctrl_reg, reg, anadv_reg;

sys/dev/e1000/e1000_82575.c

1527

reg = E1000_READ_REG(hw, E1000_PCS_LCTL);

sys/dev/e1000/e1000_82575.c

1537

reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);

sys/dev/e1000/e1000_82575.c

1565

reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;

sys/dev/e1000/e1000_82575.c

1577

reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |

sys/dev/e1000/e1000_82575.c

1582

reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */

sys/dev/e1000/e1000_82575.c

1586

reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;

sys/dev/e1000/e1000_82575.c

1607

DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);

sys/dev/e1000/e1000_82575.c

1610

reg |= E1000_PCS_LCTL_FSD; /* Force Speed */

sys/dev/e1000/e1000_82575.c

1613

reg |= E1000_PCS_LCTL_FORCE_FCTRL;

sys/dev/e1000/e1000_82575.c

1615

DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);

sys/dev/e1000/e1000_82575.c

1618

E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);

sys/dev/e1000/e1000_api.c

1394

s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,

sys/dev/e1000/e1000_api.c

1397

return e1000_write_8bit_ctrl_reg_generic(hw, reg, offset, data);

sys/dev/e1000/e1000_api.h

119

u32 e1000_translate_register_82542(u32 reg);

sys/dev/e1000/e1000_api.h

88

s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,

sys/dev/e1000/e1000_defines.h

1386

#define GG82563_REG(page, reg) \

sys/dev/e1000/e1000_defines.h

1387

(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))

sys/dev/e1000/e1000_hw.h

1083

s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);

sys/dev/e1000/e1000_hw.h

1084

s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);

sys/dev/e1000/e1000_hw.h

1085

void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);

sys/dev/e1000/e1000_hw.h

1086

void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);

sys/dev/e1000/e1000_i210.c

605

u32 i, reg;

sys/dev/e1000/e1000_i210.c

610

reg = E1000_READ_REG(hw, E1000_EECD);

sys/dev/e1000/e1000_i210.c

611

if (reg & E1000_EECD_FLUDONE_I210) {

sys/dev/e1000/e1000_ich8lan.c

1026

u16 reg;

sys/dev/e1000/e1000_ich8lan.c

1035

&reg);

sys/dev/e1000/e1000_ich8lan.c

1042

reg &

sys/dev/e1000/e1000_ich8lan.c

1055

reg);

sys/dev/e1000/e1000_ich8lan.c

1067

ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);

sys/dev/e1000/e1000_ich8lan.c

1072

reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;

sys/dev/e1000/e1000_ich8lan.c

1076

reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;

sys/dev/e1000/e1000_ich8lan.c

1082

reg |= 50 <<

sys/dev/e1000/e1000_ich8lan.c

1089

ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);

sys/dev/e1000/e1000_ich8lan.c

1132

u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |

sys/dev/e1000/e1000_ich8lan.c

1210

reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);

sys/dev/e1000/e1000_ich8lan.c

1211

E1000_WRITE_REG(hw, E1000_LTRV, reg);

sys/dev/e1000/e1000_ich8lan.c

1214

reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;

sys/dev/e1000/e1000_ich8lan.c

1215

reg |= obff_hwm;

sys/dev/e1000/e1000_ich8lan.c

1216

E1000_WRITE_REG(hw, E1000_SVT, reg);

sys/dev/e1000/e1000_ich8lan.c

1219

reg = E1000_READ_REG(hw, E1000_SVCR);

sys/dev/e1000/e1000_ich8lan.c

1220

reg |= E1000_SVCR_OFF_EN;

sys/dev/e1000/e1000_ich8lan.c

1225

reg |= E1000_SVCR_OFF_MASKINT;

sys/dev/e1000/e1000_ich8lan.c

1226

E1000_WRITE_REG(hw, E1000_SVCR, reg);

sys/dev/e1000/e1000_ich8lan.c

2500

u32 reg = 0;

sys/dev/e1000/e1000_ich8lan.c

2524

reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);

sys/dev/e1000/e1000_ich8lan.c

2525

reg |= E1000_CTRL_FRCSPD;

sys/dev/e1000/e1000_ich8lan.c

2526

E1000_WRITE_REG(hw, E1000_CTRL, reg);

sys/dev/e1000/e1000_ich8lan.c

3106

u16 reg;

sys/dev/e1000/e1000_ich8lan.c

3134

hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);

sys/dev/e1000/e1000_ich8lan.c

3135

reg &= ~BM_WUC_HOST_WU_BIT;

sys/dev/e1000/e1000_ich8lan.c

3136

hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);

sys/dev/e1000/e1000_ich8lan.c

4979

u32 ctrl, reg;

sys/dev/e1000/e1000_ich8lan.c

5066

reg = E1000_READ_REG(hw, E1000_FEXTNVM3);

sys/dev/e1000/e1000_ich8lan.c

5067

reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;

sys/dev/e1000/e1000_ich8lan.c

5068

reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;

sys/dev/e1000/e1000_ich8lan.c

5069

E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);

sys/dev/e1000/e1000_ich8lan.c

5093

reg = E1000_READ_REG(hw, E1000_KABGTXD);

sys/dev/e1000/e1000_ich8lan.c

5094

reg |= E1000_KABGTXD_BGSQLBIAS;

sys/dev/e1000/e1000_ich8lan.c

5095

E1000_WRITE_REG(hw, E1000_KABGTXD, reg);

sys/dev/e1000/e1000_ich8lan.c

5206

u32 reg;

sys/dev/e1000/e1000_ich8lan.c

5211

reg = E1000_READ_REG(hw, E1000_CTRL_EXT);

sys/dev/e1000/e1000_ich8lan.c

5212

reg |= (1 << 22);

sys/dev/e1000/e1000_ich8lan.c

5215

reg |= E1000_CTRL_EXT_PHYPDEN;

sys/dev/e1000/e1000_ich8lan.c

5216

E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);

sys/dev/e1000/e1000_ich8lan.c

5219

reg = E1000_READ_REG(hw, E1000_TXDCTL(0));

sys/dev/e1000/e1000_ich8lan.c

5220

reg |= (1 << 22);

sys/dev/e1000/e1000_ich8lan.c

5221

E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);

sys/dev/e1000/e1000_ich8lan.c

5224

reg = E1000_READ_REG(hw, E1000_TXDCTL(1));

sys/dev/e1000/e1000_ich8lan.c

5225

reg |= (1 << 22);

sys/dev/e1000/e1000_ich8lan.c

5226

E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);

sys/dev/e1000/e1000_ich8lan.c

5229

reg = E1000_READ_REG(hw, E1000_TARC(0));

sys/dev/e1000/e1000_ich8lan.c

5231

reg |= (1 << 28) | (1 << 29);

sys/dev/e1000/e1000_ich8lan.c

5232

reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);

sys/dev/e1000/e1000_ich8lan.c

5233

E1000_WRITE_REG(hw, E1000_TARC(0), reg);

sys/dev/e1000/e1000_ich8lan.c

5236

reg = E1000_READ_REG(hw, E1000_TARC(1));

sys/dev/e1000/e1000_ich8lan.c

5238

reg &= ~(1 << 28);

sys/dev/e1000/e1000_ich8lan.c

5240

reg |= (1 << 28);

sys/dev/e1000/e1000_ich8lan.c

5241

reg |= (1 << 24) | (1 << 26) | (1 << 30);

sys/dev/e1000/e1000_ich8lan.c

5242

E1000_WRITE_REG(hw, E1000_TARC(1), reg);

sys/dev/e1000/e1000_ich8lan.c

5246

reg = E1000_READ_REG(hw, E1000_STATUS);

sys/dev/e1000/e1000_ich8lan.c

5247

reg &= ~(1U << 31);

sys/dev/e1000/e1000_ich8lan.c

5248

E1000_WRITE_REG(hw, E1000_STATUS, reg);

sys/dev/e1000/e1000_ich8lan.c

5254

reg = E1000_READ_REG(hw, E1000_RFCTL);

sys/dev/e1000/e1000_ich8lan.c

5255

reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);

sys/dev/e1000/e1000_ich8lan.c

5261

reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);

sys/dev/e1000/e1000_ich8lan.c

5262

E1000_WRITE_REG(hw, E1000_RFCTL, reg);

sys/dev/e1000/e1000_ich8lan.c

5266

reg = E1000_READ_REG(hw, E1000_PBECCSTS);

sys/dev/e1000/e1000_ich8lan.c

5267

reg |= E1000_PBECCSTS_ECC_ENABLE;

sys/dev/e1000/e1000_ich8lan.c

5268

E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);

sys/dev/e1000/e1000_ich8lan.c

5270

reg = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_ich8lan.c

5271

reg |= E1000_CTRL_MEHE;

sys/dev/e1000/e1000_ich8lan.c

5272

E1000_WRITE_REG(hw, E1000_CTRL, reg);

sys/dev/e1000/e1000_ich8lan.c

5587

u32 reg;

sys/dev/e1000/e1000_ich8lan.c

5599

reg = E1000_READ_REG(hw, E1000_PHY_CTRL);

sys/dev/e1000/e1000_ich8lan.c

5600

reg |= (E1000_PHY_CTRL_GBE_DISABLE |

sys/dev/e1000/e1000_ich8lan.c

5602

E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);

sys/dev/e1000/e1000_ich8lan.c

5623

reg = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/e1000_ich8lan.c

5624

E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);

sys/dev/e1000/e1000_ich8lan.h

136

#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \

sys/dev/e1000/e1000_ich8lan.h

137

((reg) & MAX_PHY_REG_ADDRESS))

sys/dev/e1000/e1000_mac.c

2166

s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,

sys/dev/e1000/e1000_mac.c

2175

E1000_WRITE_REG(hw, reg, regvalue);

sys/dev/e1000/e1000_mac.c

2180

regvalue = E1000_READ_REG(hw, reg);

sys/dev/e1000/e1000_mac.c

2185

DEBUGOUT1("Reg %08x did not indicate ready\n", reg);

sys/dev/e1000/e1000_mac.c

288

u32 reg;

sys/dev/e1000/e1000_mac.c

293

reg = E1000_READ_REG(hw, E1000_STATUS);

sys/dev/e1000/e1000_mac.c

294

bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;

sys/dev/e1000/e1000_mac.h

79

s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,

sys/dev/e1000/e1000_nvm.c

241

u32 i, reg = 0;

sys/dev/e1000/e1000_nvm.c

247

reg = E1000_READ_REG(hw, E1000_EERD);

sys/dev/e1000/e1000_nvm.c

249

reg = E1000_READ_REG(hw, E1000_EEWR);

sys/dev/e1000/e1000_nvm.c

251

if (reg & E1000_NVM_RW_REG_DONE)

sys/dev/e1000/e1000_osdep.c

103

pci_write_config(dev, offset + reg, *value, 2);

sys/dev/e1000/e1000_osdep.c

54

e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)

sys/dev/e1000/e1000_osdep.c

56

pci_write_config(((struct e1000_osdep *)hw->back)->dev, reg, *value, 2);

sys/dev/e1000/e1000_osdep.c

60

e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)

sys/dev/e1000/e1000_osdep.c

62

*value = pci_read_config(((struct e1000_osdep *)hw->back)->dev, reg, 2);

sys/dev/e1000/e1000_osdep.c

83

e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)

sys/dev/e1000/e1000_osdep.c

89

*value = pci_read_config(dev, offset + reg, 2);

sys/dev/e1000/e1000_osdep.c

97

e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)

sys/dev/e1000/e1000_osdep.h

166

#define E1000_REGISTER(hw, reg) (((hw)->mac.type >= e1000_82543) \

sys/dev/e1000/e1000_osdep.h

167

? reg : e1000_translate_register_82542(reg))

sys/dev/e1000/e1000_osdep.h

182

e1000_rd32(struct e1000_osdep *osdep, uint32_t reg)

sys/dev/e1000/e1000_osdep.h

185

KASSERT(reg < osdep->mem_bus_space_size,

sys/dev/e1000/e1000_osdep.h

187

(uintmax_t)reg, (uintmax_t)osdep->mem_bus_space_size));

sys/dev/e1000/e1000_osdep.h

190

osdep->mem_bus_space_handle, reg));

sys/dev/e1000/e1000_osdep.h

195

e1000_wr32(struct e1000_osdep *osdep, uint32_t reg, uint32_t value)

sys/dev/e1000/e1000_osdep.h

198

KASSERT(reg < osdep->mem_bus_space_size,

sys/dev/e1000/e1000_osdep.h

200

(uintmax_t)reg, (uintmax_t)osdep->mem_bus_space_size));

sys/dev/e1000/e1000_osdep.h

203

osdep->mem_bus_space_handle, reg, value);

sys/dev/e1000/e1000_osdep.h

208

#define E1000_READ_REG(hw, reg) \

sys/dev/e1000/e1000_osdep.h

209

e1000_rd32((hw)->back, E1000_REGISTER(hw, reg))

sys/dev/e1000/e1000_osdep.h

211

#define E1000_WRITE_REG(hw, reg, value) \

sys/dev/e1000/e1000_osdep.h

212

e1000_wr32((hw)->back, E1000_REGISTER(hw, reg), value)

sys/dev/e1000/e1000_osdep.h

214

#define E1000_READ_REG_ARRAY(hw, reg, index) \

sys/dev/e1000/e1000_osdep.h

215

e1000_rd32((hw)->back, E1000_REGISTER(hw, reg) + ((index) << 2))

sys/dev/e1000/e1000_osdep.h

217

#define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \

sys/dev/e1000/e1000_osdep.h

218

e1000_wr32((hw)->back, E1000_REGISTER(hw, reg) + ((index) << 2), value)

sys/dev/e1000/e1000_osdep.h

223

#define E1000_READ_REG_ARRAY_BYTE(hw, reg, index) \

sys/dev/e1000/e1000_osdep.h

226

E1000_REGISTER(hw, reg) + index)

sys/dev/e1000/e1000_osdep.h

228

#define E1000_WRITE_REG_ARRAY_BYTE(hw, reg, index, value) \

sys/dev/e1000/e1000_osdep.h

231

E1000_REGISTER(hw, reg) + index, value)

sys/dev/e1000/e1000_osdep.h

233

#define E1000_WRITE_REG_ARRAY_WORD(hw, reg, index, value) \

sys/dev/e1000/e1000_osdep.h

236

E1000_REGISTER(hw, reg) + (index << 1), value)

sys/dev/e1000/e1000_osdep.h

238

#define E1000_WRITE_REG_IO(hw, reg, value) do {\

sys/dev/e1000/e1000_osdep.h

241

(hw)->io_base, reg); \

sys/dev/e1000/e1000_osdep.h

246

#define E1000_READ_FLASH_REG(hw, reg) \

sys/dev/e1000/e1000_osdep.h

248

((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg)

sys/dev/e1000/e1000_osdep.h

250

#define E1000_READ_FLASH_REG16(hw, reg) \

sys/dev/e1000/e1000_osdep.h

252

((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg)

sys/dev/e1000/e1000_osdep.h

254

#define E1000_WRITE_FLASH_REG(hw, reg, value) \

sys/dev/e1000/e1000_osdep.h

256

((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value)

sys/dev/e1000/e1000_osdep.h

258

#define E1000_WRITE_FLASH_REG16(hw, reg, value) \

sys/dev/e1000/e1000_osdep.h

260

((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value)

sys/dev/e1000/e1000_phy.c

3104

static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)

sys/dev/e1000/e1000_phy.c

3108

if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))

sys/dev/e1000/e1000_phy.c

3444

u16 reg = BM_PHY_REG_NUM(offset);

sys/dev/e1000/e1000_phy.c

3465

DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);

sys/dev/e1000/e1000_phy.c

3468

ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);

sys/dev/e1000/e1000_phy.c

3485

DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);

sys/dev/e1000/e1000_phy.c

3549

u16 reg = BM_PHY_REG_NUM(offset);

sys/dev/e1000/e1000_phy.c

3576

if (reg > MAX_PHY_MULTI_PAGE_REG) {

sys/dev/e1000/e1000_phy.c

3589

page << IGP_PAGE_SHIFT, reg);

sys/dev/e1000/e1000_phy.c

3591

ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,

sys/dev/e1000/e1000_phy.c

3659

u16 reg = BM_PHY_REG_NUM(offset);

sys/dev/e1000/e1000_phy.c

3692

!(MAX_PHY_REG_ADDRESS & reg) &&

sys/dev/e1000/e1000_phy.c

3702

if (reg > MAX_PHY_MULTI_PAGE_REG) {

sys/dev/e1000/e1000_phy.c

3715

page << IGP_PAGE_SHIFT, reg);

sys/dev/e1000/e1000_phy.c

3717

ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,

sys/dev/e1000/e1000_phy.h

165

#define BM_PHY_REG(page, reg) \

sys/dev/e1000/e1000_phy.h

166

(((reg) & MAX_PHY_REG_ADDRESS) |\

sys/dev/e1000/e1000_phy.h

168

(((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))

sys/dev/e1000/e1000_vf.h

292

s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);

sys/dev/e1000/if_em.c

2821

u32 dmac, reg = ~E1000_DMACR_DMAC_EN;

sys/dev/e1000/if_em.c

2832

E1000_WRITE_REG(hw, E1000_DMACR, reg);

sys/dev/e1000/if_em.c

2843

reg = E1000_READ_REG(hw, E1000_FCRTC);

sys/dev/e1000/if_em.c

2844

reg &= ~E1000_FCRTC_RTH_COAL_MASK;

sys/dev/e1000/if_em.c

2845

reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)

sys/dev/e1000/if_em.c

2847

E1000_WRITE_REG(hw, E1000_FCRTC, reg);

sys/dev/e1000/if_em.c

2853

reg = E1000_READ_REG(hw, E1000_DMACR);

sys/dev/e1000/if_em.c

2854

reg &= ~E1000_DMACR_DMACTHR_MASK;

sys/dev/e1000/if_em.c

2855

reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)

sys/dev/e1000/if_em.c

2859

reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);

sys/dev/e1000/if_em.c

2871

reg |= ((sc->dmac * 5) >> 6);

sys/dev/e1000/if_em.c

2873

reg |= (sc->dmac >> 5);

sys/dev/e1000/if_em.c

2875

reg |= (sc->dmac >> 5);

sys/dev/e1000/if_em.c

2878

E1000_WRITE_REG(hw, E1000_DMACR, reg);

sys/dev/e1000/if_em.c

2883

reg = E1000_READ_REG(hw, E1000_DMCTLX);

sys/dev/e1000/if_em.c

2885

reg |= IGB_DMCTLX_DCFLUSH_DIS;

sys/dev/e1000/if_em.c

2894

reg |= 0xA;

sys/dev/e1000/if_em.c

2896

reg |= 0x4;

sys/dev/e1000/if_em.c

2898

reg |= 0x4;

sys/dev/e1000/if_em.c

2901

E1000_WRITE_REG(hw, E1000_DMCTLX, reg);

sys/dev/e1000/if_em.c

2908

reg = E1000_READ_REG(hw, E1000_PCIEMISC);

sys/dev/e1000/if_em.c

2909

reg &= ~E1000_PCIEMISC_LX_DECISION;

sys/dev/e1000/if_em.c

2910

E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);

sys/dev/e1000/if_em.c

2913

u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);

sys/dev/e1000/if_em.c

2915

reg & ~E1000_PCIEMISC_LX_DECISION);

sys/dev/e1000/if_em.c

3739

u32 reg;

sys/dev/e1000/if_em.c

3740

reg = E1000_READ_REG(hw, E1000_IOSFPC);

sys/dev/e1000/if_em.c

3741

reg |= E1000_RCTL_RDMTS_HEX;

sys/dev/e1000/if_em.c

3742

E1000_WRITE_REG(hw, E1000_IOSFPC, reg);

sys/dev/e1000/if_em.c

3744

reg = E1000_READ_REG(hw, E1000_TARC(0));

sys/dev/e1000/if_em.c

3745

reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;

sys/dev/e1000/if_em.c

3746

reg |= E1000_TARC0_CB_MULTIQ_2_REQ;

sys/dev/e1000/if_em.c

3747

E1000_WRITE_REG(hw, E1000_TARC(0), reg);

sys/dev/e1000/if_em.c

4084

u32 reg;

sys/dev/e1000/if_em.c

4086

reg = E1000_READ_REG(hw, E1000_RCTL);

sys/dev/e1000/if_em.c

4087

reg &= ~E1000_RCTL_CFIEN;

sys/dev/e1000/if_em.c

4088

reg |= E1000_RCTL_VFE;

sys/dev/e1000/if_em.c

4089

E1000_WRITE_REG(hw, E1000_RCTL, reg);

sys/dev/e1000/if_em.c

4096

u32 reg;

sys/dev/e1000/if_em.c

4098

reg = E1000_READ_REG(hw, E1000_RCTL);

sys/dev/e1000/if_em.c

4099

reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);

sys/dev/e1000/if_em.c

4100

E1000_WRITE_REG(hw, E1000_RCTL, reg);

sys/dev/e1000/if_em.c

4129

u32 reg;

sys/dev/e1000/if_em.c

4141

reg = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/if_em.c

4142

reg |= E1000_CTRL_VME;

sys/dev/e1000/if_em.c

4143

E1000_WRITE_REG(hw, E1000_CTRL, reg);

sys/dev/e1000/if_em.c

4145

reg = E1000_READ_REG(hw, E1000_CTRL);

sys/dev/e1000/if_em.c

4146

reg &= ~E1000_CTRL_VME;

sys/dev/e1000/if_em.c

4147

E1000_WRITE_REG(hw, E1000_CTRL, reg);

sys/dev/e1000/if_em.c

4662

int base, reg;

sys/dev/e1000/if_em.c

4676

reg = base + PCIER_LINK_CAP;

sys/dev/e1000/if_em.c

4677

link_cap = pci_read_config(dev, reg, 2);

sys/dev/e1000/if_em.c

4680

reg = base + PCIER_LINK_CTL;

sys/dev/e1000/if_em.c

4681

link_ctrl = pci_read_config(dev, reg, 2);

sys/dev/e1000/if_em.c

4683

pci_write_config(dev, reg, link_ctrl, 2);

sys/dev/e1000/if_em.c

4908

u32 reg, usec, rate;

sys/dev/e1000/if_em.c

4916

reg = E1000_READ_REG(hw, E1000_EITR(tque->me));

sys/dev/e1000/if_em.c

4918

reg = E1000_READ_REG(hw, E1000_EITR_82574(tque->me));

sys/dev/e1000/if_em.c

4920

reg = E1000_READ_REG(hw, E1000_ITR);

sys/dev/e1000/if_em.c

4925

reg = E1000_READ_REG(hw, E1000_EITR(rque->msix));

sys/dev/e1000/if_em.c

4927

reg = E1000_READ_REG(hw,

sys/dev/e1000/if_em.c

4930

reg = E1000_READ_REG(hw, E1000_ITR);

sys/dev/e1000/if_em.c

4934

if (reg > 0)

sys/dev/e1000/if_em.c

4935

rate = EM_INTS_TO_ITR(reg);

sys/dev/e1000/if_em.c

4939

usec = (reg & IGB_QVECTOR_MASK);

sys/dev/e1000/if_em.c

5502

u32 reg, val, shift;

sys/dev/e1000/if_em.c

5508

reg = E1000_DTXTCPFLGL;

sys/dev/e1000/if_em.c

5512

reg = E1000_DTXTCPFLGL;

sys/dev/e1000/if_em.c

5516

reg = E1000_DTXTCPFLGH;

sys/dev/e1000/if_em.c

5523

val = E1000_READ_REG(&sc->hw, reg);

sys/dev/e1000/if_em.c

5531

E1000_WRITE_REG(&sc->hw, reg, val);

sys/dev/e1000/if_em.h

374

#define UPDATE_VF_REG(reg, last, cur) \

sys/dev/e1000/if_em.h

376

u32 new = E1000_READ_REG(&sc->hw, reg); \

sys/dev/enetc/enetc.h

103

#define ENETC_RD4(sc, reg) \

sys/dev/enetc/enetc.h

104

bus_read_4((sc)->regs, reg)

sys/dev/enetc/enetc.h

105

#define ENETC_WR4(sc, reg, value) \

sys/dev/enetc/enetc.h

106

bus_write_4((sc)->regs, reg, value)

sys/dev/enetc/enetc.h

108

#define ENETC_PORT_RD8(sc, reg) \

sys/dev/enetc/enetc.h

109

bus_read_8((sc)->regs, ENETC_PORT_BASE + (reg))

sys/dev/enetc/enetc.h

110

#define ENETC_PORT_RD4(sc, reg) \

sys/dev/enetc/enetc.h

111

bus_read_4((sc)->regs, ENETC_PORT_BASE + (reg))

sys/dev/enetc/enetc.h

112

#define ENETC_PORT_WR4(sc, reg, value) \

sys/dev/enetc/enetc.h

113

bus_write_4((sc)->regs, ENETC_PORT_BASE + (reg), value)

sys/dev/enetc/enetc.h

114

#define ENETC_PORT_RD2(sc, reg) \

sys/dev/enetc/enetc.h

115

bus_read_2((sc)->regs, ENETC_PORT_BASE + (reg))

sys/dev/enetc/enetc.h

116

#define ENETC_PORT_WR2(sc, reg, value) \

sys/dev/enetc/enetc.h

117

bus_write_2((sc)->regs, ENETC_PORT_BASE + (reg), value)

sys/dev/enetc/enetc.h

119

#define ENETC_TXQ_RD4(sc, q, reg) \

sys/dev/enetc/enetc.h

120

ENETC_RD4((sc), ENETC_BDR(TX, q, reg))

sys/dev/enetc/enetc.h

121

#define ENETC_TXQ_WR4(sc, q, reg, value) \

sys/dev/enetc/enetc.h

122

ENETC_WR4((sc), ENETC_BDR(TX, q, reg), value)

sys/dev/enetc/enetc.h

123

#define ENETC_RXQ_RD4(sc, q, reg) \

sys/dev/enetc/enetc.h

124

ENETC_RD4((sc), ENETC_BDR(RX, q, reg))

sys/dev/enetc/enetc.h

125

#define ENETC_RXQ_WR4(sc, q, reg, value) \

sys/dev/enetc/enetc.h

126

ENETC_WR4((sc), ENETC_BDR(RX, q, reg), value)

sys/dev/enetc/enetc_mdio.c

111

enetc_mdio_write(struct resource *regs, int mdio_base, int phy, int reg,

sys/dev/enetc/enetc_mdio.c

118

if (reg & MII_ADDR_C45) {

sys/dev/enetc/enetc_mdio.c

120

dev_addr = (reg >> 16) & 0x1f;

sys/dev/enetc/enetc_mdio.c

124

dev_addr = reg & 0x1f;

sys/dev/enetc/enetc_mdio.c

138

if (reg & MII_ADDR_C45) {

sys/dev/enetc/enetc_mdio.c

139

ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_ADDR, reg & 0xffff);

sys/dev/enetc/enetc_mdio.c

64

enetc_mdio_read(struct resource *regs, int mdio_base, int phy, int reg)

sys/dev/enetc/enetc_mdio.c

70

if (reg & MII_ADDR_C45) {

sys/dev/enetc/enetc_mdio.c

72

dev_addr = (reg >> 16) & 0x1f;

sys/dev/enetc/enetc_mdio.c

76

dev_addr = reg & 0x1f;

sys/dev/enetc/enetc_mdio.c

90

if (reg & MII_ADDR_C45) {

sys/dev/enetc/enetc_mdio.c

91

ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_ADDR, reg & 0xffff);

sys/dev/enetc/if_enetc.c

1376

uint32_t reg = 0;

sys/dev/enetc/if_enetc.c

1381

reg = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);

sys/dev/enetc/if_enetc.c

1383

reg = ENETC_PSIPMR_SET_MP(0);

sys/dev/enetc/if_enetc.c

1385

ENETC_PORT_WR4(sc, ENETC_PSIPMR, reg);

sys/dev/enetc/if_enetc.c

1426

enetc_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/enetc/if_enetc.c

1435

phy, reg);

sys/dev/enetc/if_enetc.c

1442

enetc_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/enetc/if_enetc.c

1451

phy, reg, data);

sys/dev/enetc/if_enetc.c

603

uint32_t reg;

sys/dev/enetc/if_enetc.c

605

reg = ENETC_RD4(sc, ENETC_SIPCAPR0);

sys/dev/enetc/if_enetc.c

606

if (reg & ENETC_SIPCAPR0_RSS) {

sys/dev/enetc/if_enetc.c

607

reg = ENETC_RD4(sc, ENETC_SIRSSCAPR);

sys/dev/enetc/if_enetc.c

608

buckets_num = ENETC_SIRSSCAPR_GET_NUM_RSS(reg);

sys/dev/enetc/if_enetc.c

614

arc4rand((uint8_t *)&reg, sizeof(reg), 0);

sys/dev/enetc/if_enetc.c

615

ENETC_PORT_WR4(sc, ENETC_PRSSK(i), reg);

sys/dev/eqos/if_eqos.c

111

eqos_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/eqos/if_eqos.c

119

(reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) |

sys/dev/eqos/if_eqos.c

136

phy, reg);

sys/dev/eqos/if_eqos.c

143

eqos_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/eqos/if_eqos.c

153

(reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) |

sys/dev/eqos/if_eqos.c

168

phy, reg);

sys/dev/eqos/if_eqos.c

179

uint32_t reg;

sys/dev/eqos/if_eqos.c

188

reg = RD4(sc, GMAC_MAC_CONFIGURATION);

sys/dev/eqos/if_eqos.c

192

reg |= GMAC_MAC_CONFIGURATION_PS;

sys/dev/eqos/if_eqos.c

193

reg &= ~GMAC_MAC_CONFIGURATION_FES;

sys/dev/eqos/if_eqos.c

196

reg |= GMAC_MAC_CONFIGURATION_PS;

sys/dev/eqos/if_eqos.c

197

reg |= GMAC_MAC_CONFIGURATION_FES;

sys/dev/eqos/if_eqos.c

201

reg &= ~GMAC_MAC_CONFIGURATION_PS;

sys/dev/eqos/if_eqos.c

202

reg &= ~GMAC_MAC_CONFIGURATION_FES;

sys/dev/eqos/if_eqos.c

206

reg &= ~GMAC_MAC_CONFIGURATION_PS;

sys/dev/eqos/if_eqos.c

207

reg |= GMAC_MAC_CONFIGURATION_FES;

sys/dev/eqos/if_eqos.c

215

reg |= GMAC_MAC_CONFIGURATION_DM;

sys/dev/eqos/if_eqos.c

217

reg &= ~GMAC_MAC_CONFIGURATION_DM;

sys/dev/eqos/if_eqos.c

219

WR4(sc, GMAC_MAC_CONFIGURATION, reg);

sys/dev/et/if_et.c

409

et_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/et/if_et.c

420

val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK;

sys/dev/et/if_et.c

436

"read phy %d, reg %d timed out\n", phy, reg);

sys/dev/et/if_et.c

453

et_miibus_writereg(device_t dev, int phy, int reg, int val0)

sys/dev/et/if_et.c

464

val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK;

sys/dev/et/if_et.c

481

"write phy %d, reg %d timed out\n", phy, reg);

sys/dev/et/if_et.c

482

et_miibus_readreg(dev, phy, reg);

sys/dev/et/if_etvar.h

68

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/et/if_etvar.h

69

bus_write_4((sc)->sc_mem_res, (reg), (val))

sys/dev/et/if_etvar.h

70

#define CSR_READ_4(sc, reg) \

sys/dev/et/if_etvar.h

71

bus_read_4((sc)->sc_mem_res, (reg))

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

113

uint32_t reg;

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

118

reg = AR40XX_FWD_CTRL0_CPU_PORT_EN

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

120

AR40XX_REG_WRITE(sc, AR40XX_REG_FWD_CTRL0, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

123

reg = (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_UC_FLOOD_S)

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

126

AR40XX_REG_WRITE(sc, AR40XX_REG_FWD_CTRL1, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

129

reg = AR40XX_REG_READ(sc, AR40XX_REG_MAX_FRAME_SIZE);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

130

reg &= ~AR40XX_MAX_FRAME_SIZE_MTU;

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

131

reg |= 9018 + 8 + 2;

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

132

AR40XX_REG_WRITE(sc, AR40XX_REG_MAX_FRAME_SIZE, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

135

reg = AR40XX_REG_READ(sc, AR40XX_REG_MODULE_EN);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

136

reg |= AR40XX_MODULE_EN_MIB;

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

137

AR40XX_REG_WRITE(sc, AR40XX_REG_MODULE_EN, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

143

reg = (AR40XX_PORT0_FC_THRESH_ON_DFLT << 16)

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

145

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

277

ar40xx_hw_wait_bit(struct ar40xx_softc *sc, int reg, uint32_t mask,

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

285

t = AR40XX_REG_READ(sc, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw.c

297

(unsigned int)reg, t, mask, val);

sys/dev/etherswitch/ar40xx/ar40xx_hw.h

34

extern int ar40xx_hw_wait_bit(struct ar40xx_softc *sc, int reg,

sys/dev/etherswitch/ar40xx/ar40xx_hw_mib.c

126

uint32_t reg;

sys/dev/etherswitch/ar40xx/ar40xx_hw_mib.c

133

reg = AR40XX_REG_READ(sc, AR40XX_REG_MIB_FUNC);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mib.c

134

reg &= ~AR40XX_MIB_FUNC;

sys/dev/etherswitch/ar40xx/ar40xx_hw_mib.c

135

reg |= (op << AR40XX_MIB_FUNC_S);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mib.c

136

AR40XX_REG_WRITE(sc, AR40XX_REG_MIB_FUNC, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mib.c

173

uint32_t base, reg;

sys/dev/etherswitch/ar40xx/ar40xx_hw_mib.c

186

reg = AR40XX_REG_READ(sc, base + ar40xx_mibs[i].offset + 4);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mib.c

187

val |= ((uint64_t) reg << 32);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

105

reg = AR40XX_REG_READ(sc, AR40XX_REG_FWD_CTRL0);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

106

reg &= ~AR40XX_FWD_CTRL0_MIRROR_PORT;

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

107

reg |=

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

109

AR40XX_REG_WRITE(sc, AR40XX_REG_FWD_CTRL0, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

112

reg = AR40XX_REG_READ(sc,

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

114

reg |= AR40XX_PORT_LOOKUP_ING_MIRROR_EN;

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

117

reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

122

reg = AR40XX_REG_READ(sc,

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

124

reg |= AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN;

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

127

reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

76

uint32_t reg;

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

80

reg = AR40XX_REG_READ(sc, AR40XX_REG_FWD_CTRL0);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

81

reg &= ~(AR40XX_FWD_CTRL0_MIRROR_PORT);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

82

reg |= (0xF << AR40XX_FWD_CTRL0_MIRROR_PORT_S);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

83

AR40XX_REG_WRITE(sc, AR40XX_REG_FWD_CTRL0, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

87

reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_LOOKUP(port));

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

88

reg &= ~AR40XX_PORT_LOOKUP_ING_MIRROR_EN;

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

89

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

91

reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_HOL_CTRL1(port));

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

92

reg &= ~AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN;

sys/dev/etherswitch/ar40xx/ar40xx_hw_mirror.c

93

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_HOL_CTRL1(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

113

reg = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

115

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN1(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

117

reg = AR40XX_PORT_LOOKUP_LEARN;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

118

reg |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

119

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

151

uint32_t reg;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

158

reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_STATUS(port));

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

159

reg |= AR40XX_PORT_AUTO_LINK_EN;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

160

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

173

uint32_t reg;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

178

reg = AR40XX_PORT_STATUS_TXFLOW

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

183

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(0), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

186

reg |= AR40XX_PORT_TX_EN | AR40XX_PORT_RX_EN;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

187

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(0), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

203

uint32_t reg;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

208

reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_VLAN0(port));

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

210

reg = reg >> AR40XX_PORT_VLAN0_DEF_CVID_S;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

211

reg = reg & 0x0fff; /* XXX */

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

213

*pvid = reg;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

226

uint32_t reg;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

232

reg = pvid << AR40XX_PORT_VLAN0_DEF_SVID_S;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

233

reg |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

234

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN0(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

257

uint32_t egress, ingress, reg;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

269

reg = pvid << AR40XX_PORT_VLAN0_DEF_SVID_S;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

270

reg |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

271

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN0(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

274

reg = AR40XX_PORT_VLAN1_PORT_VLAN_PROP;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

275

reg |= egress << AR40XX_PORT_VLAN1_OUT_MODE_S;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

276

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN1(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

279

reg = members;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

280

reg |= AR40XX_PORT_LOOKUP_LEARN;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

281

reg |= ingress << AR40XX_PORT_LOOKUP_IN_MODE_S;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

282

reg |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

283

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(port), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_port.c

76

uint32_t reg;

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

322

uint32_t i, phy, reg;

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

350

reg = AR40XX_REG_READ(sc,

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

352

reg |= AR40XX_PORT_LOOKUP_LOOPBACK;

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

354

AR40XX_REG_PORT_LOOKUP(phy + 1), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

389

uint32_t reg;

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

400

reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_LOOKUP(phy + 1));

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

401

reg &= ~AR40XX_PORT_LOOKUP_LOOPBACK;

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

402

AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(phy + 1), reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

418

uint32_t reg;

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

428

reg = ar40xx_hw_psgmii_reg_read(sc, 0x78c);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

430

"%s: PSGMIIPHY_PLL_VCO_RELATED_CTRL=0x%08x\n", __func__, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

432

reg = ar40xx_hw_psgmii_reg_read(sc, 0x09c);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

434

"%s: PSGMIIPHY_VCO_CALIBRATION_CTRL=0x%08x\n", __func__, reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

82

ar40xx_hw_psgmii_reg_write(struct ar40xx_softc *sc, uint32_t reg,

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

86

reg, val);

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

92

ar40xx_hw_psgmii_reg_read(struct ar40xx_softc *sc, uint32_t reg)

sys/dev/etherswitch/ar40xx/ar40xx_hw_psgmii.c

99

reg);

sys/dev/etherswitch/ar40xx/ar40xx_hw_vtu.c

162

uint32_t op, reg, val;

sys/dev/etherswitch/ar40xx/ar40xx_hw_vtu.c

179

reg = AR40XX_REG_READ(sc, AR40XX_REG_VTU_FUNC0);

sys/dev/etherswitch/ar40xx/ar40xx_hw_vtu.c

183

val = reg >> AR40XX_VTU_FUNC0_EG_MODE_S(i);

sys/dev/etherswitch/ar40xx/ar40xx_main.c

115

ar40xx_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/ar40xx/ar40xx_main.c

119

return MDIO_READREG(sc->sc_mdio_dev, phy, reg);

sys/dev/etherswitch/ar40xx/ar40xx_main.c

123

ar40xx_writephy(device_t dev, int phy, int reg, int val)

sys/dev/etherswitch/ar40xx/ar40xx_main.c

127

return MDIO_WRITEREG(sc->sc_mdio_dev, phy, reg, val);

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

103

if (((reg & AR40XX_PORT_STATUS_LINK_UP) != 0) &&

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

110

if (((reg & AR40XX_PORT_STATUS_LINK_UP) == 0) &&

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

83

uint32_t reg;

sys/dev/etherswitch/ar40xx/ar40xx_phy.c

95

reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_STATUS(phy + 1));

sys/dev/etherswitch/ar40xx/ar40xx_var.h

37

#define AR40XX_REG_WRITE(sc, reg, val) do { \

sys/dev/etherswitch/ar40xx/ar40xx_var.h

38

bus_write_4(sc->sc_ess_mem_res, (reg), (val)); \

sys/dev/etherswitch/ar40xx/ar40xx_var.h

41

#define AR40XX_REG_READ(sc, reg) bus_read_4(sc->sc_ess_mem_res, (reg))

sys/dev/etherswitch/arswitch/arswitch.c

1001

AR8X16_PORT_CTRL_DOUBLE_TAG, reg);

sys/dev/etherswitch/arswitch/arswitch.c

1068

ar8327_led_mapping[phy][led].reg,

sys/dev/etherswitch/arswitch/arswitch.c

1249

arswitch_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/arswitch/arswitch.c

1253

return (sc->hal.arswitch_phy_read(dev, phy, reg));

sys/dev/etherswitch/arswitch/arswitch.c

1257

arswitch_writephy(device_t dev, int phy, int reg, int val)

sys/dev/etherswitch/arswitch/arswitch.c

1261

return (sc->hal.arswitch_phy_write(dev, phy, reg, val));

sys/dev/etherswitch/arswitch/arswitch.c

868

uint32_t reg;

sys/dev/etherswitch/arswitch/arswitch.c

876

reg = arswitch_readreg(sc->sc_dev, AR8X16_REG_PORT_CTRL(p->es_port));

sys/dev/etherswitch/arswitch/arswitch.c

877

if (reg & AR8X16_PORT_CTRL_DOUBLE_TAG)

sys/dev/etherswitch/arswitch/arswitch.c

879

reg >>= AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT;

sys/dev/etherswitch/arswitch/arswitch.c

880

if ((reg & 0x3) == AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_ADD)

sys/dev/etherswitch/arswitch/arswitch.c

882

if ((reg & 0x3) == AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP)

sys/dev/etherswitch/arswitch/arswitch.c

947

ar8327_led_mapping[p->es_port-1][led].reg);

sys/dev/etherswitch/arswitch/arswitch.c

972

uint32_t reg;

sys/dev/etherswitch/arswitch/arswitch.c

988

reg = 0;

sys/dev/etherswitch/arswitch/arswitch.c

990

reg |= AR8X16_PORT_CTRL_DOUBLE_TAG;

sys/dev/etherswitch/arswitch/arswitch.c

992

reg |= AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_ADD <<

sys/dev/etherswitch/arswitch/arswitch.c

995

reg |= AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP <<

sys/dev/etherswitch/arswitch/arswitch_8327.c

1014

uint32_t reg;

sys/dev/etherswitch/arswitch/arswitch_8327.c

1022

reg = arswitch_readreg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port));

sys/dev/etherswitch/arswitch/arswitch_8327.c

1023

reg = reg >> AR8327_PORT_VLAN0_DEF_CVID_S;

sys/dev/etherswitch/arswitch/arswitch_8327.c

1024

reg = reg & 0xfff;

sys/dev/etherswitch/arswitch/arswitch_8327.c

1026

*pvid = reg;

sys/dev/etherswitch/arswitch/arswitch_8327.c

1192

uint32_t op, reg, val;

sys/dev/etherswitch/arswitch/arswitch_8327.c

1205

reg = arswitch_readreg(sc->sc_dev, AR8327_REG_VTU_FUNC0);

sys/dev/etherswitch/arswitch/arswitch_8327.c

1206

DPRINTF(sc, ARSWITCH_DBG_REGIO, "%s: %d: reg=0x%08x\n", __func__, vid, reg);

sys/dev/etherswitch/arswitch/arswitch_8327.c

1214

val = reg >> AR8327_VTU_FUNC0_EG_MODE_S(i);

sys/dev/etherswitch/arswitch/arswitch_8327.c

967

uint32_t reg;

sys/dev/etherswitch/arswitch/arswitch_8327.c

973

reg = arswitch_readreg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port));

sys/dev/etherswitch/arswitch/arswitch_8327.c

974

*ports = reg & 0x7f;

sys/dev/etherswitch/arswitch/arswitch_8327.h

89

int reg;

sys/dev/etherswitch/arswitch/arswitch_phy.c

100

__func__, phy, reg, data);

sys/dev/etherswitch/arswitch/arswitch_phy.c

111

arswitch_readphy_internal(device_t dev, int phy, int reg)

sys/dev/etherswitch/arswitch/arswitch_phy.c

123

if (reg < 0 || reg >= 32)

sys/dev/etherswitch/arswitch/arswitch_phy.c

136

(reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT));

sys/dev/etherswitch/arswitch/arswitch_phy.c

137

DEVERR(dev, err, "arswitch_readphy()=%d: phy=%d.%02x\n", phy, reg);

sys/dev/etherswitch/arswitch/arswitch_phy.c

148

phy, reg, timeout);

sys/dev/etherswitch/arswitch/arswitch_phy.c

157

__func__, phy, reg, data);

sys/dev/etherswitch/arswitch/arswitch_phy.c

166

__func__, phy, reg, err);

sys/dev/etherswitch/arswitch/arswitch_phy.c

172

arswitch_writephy_internal(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/arswitch/arswitch_phy.c

182

if (reg < 0 || reg >= 32)

sys/dev/etherswitch/arswitch/arswitch_phy.c

196

(reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT) |

sys/dev/etherswitch/arswitch/arswitch_phy.c

210

__func__, phy, reg, data, err);

sys/dev/etherswitch/arswitch/arswitch_phy.c

213

DEVERR(dev, err, "arswitch_writephy()=%d: phy=%d.%02x\n", phy, reg);

sys/dev/etherswitch/arswitch/arswitch_phy.c

71

arswitch_readphy_external(device_t dev, int phy, int reg)

sys/dev/etherswitch/arswitch/arswitch_phy.c

79

ret = (MDIO_READREG(device_get_parent(dev), phy, reg));

sys/dev/etherswitch/arswitch/arswitch_phy.c

82

__func__, phy, reg, ret);

sys/dev/etherswitch/arswitch/arswitch_phy.c

89

arswitch_writephy_external(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/arswitch/arswitch_phy.c

97

reg, data);

sys/dev/etherswitch/arswitch/arswitch_phy.h

31

extern int arswitch_readphy_external(device_t dev, int phy, int reg);

sys/dev/etherswitch/arswitch/arswitch_phy.h

32

extern int arswitch_writephy_external(device_t dev, int phy, int reg, int data);

sys/dev/etherswitch/arswitch/arswitch_phy.h

34

extern int arswitch_readphy_internal(device_t dev, int phy, int reg);

sys/dev/etherswitch/arswitch/arswitch_phy.h

35

extern int arswitch_writephy_internal(device_t dev, int phy, int reg, int data);

sys/dev/etherswitch/arswitch/arswitch_reg.c

102

uint16_t phy, reg;

sys/dev/etherswitch/arswitch/arswitch_reg.c

104

arswitch_split_setpage(dev, addr, &phy, &reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

105

return (MDIO_WRITEREG(device_get_parent(dev), 0x10 | phy, reg, data));

sys/dev/etherswitch/arswitch/arswitch_reg.c

129

arswitch_reg_read32(device_t dev, int phy, int reg)

sys/dev/etherswitch/arswitch/arswitch_reg.c

132

lo = MDIO_READREG(device_get_parent(dev), phy, reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

133

hi = MDIO_READREG(device_get_parent(dev), phy, reg + 1);

sys/dev/etherswitch/arswitch/arswitch_reg.c

139

arswitch_reg_write32(device_t dev, int phy, int reg, uint32_t value)

sys/dev/etherswitch/arswitch/arswitch_reg.c

151

phy, reg, lo);

sys/dev/etherswitch/arswitch/arswitch_reg.c

153

phy, reg + 1, hi);

sys/dev/etherswitch/arswitch/arswitch_reg.c

156

phy, reg + 1, hi);

sys/dev/etherswitch/arswitch/arswitch_reg.c

158

phy, reg, lo);

sys/dev/etherswitch/arswitch/arswitch_reg.c

167

uint16_t phy, reg;

sys/dev/etherswitch/arswitch/arswitch_reg.c

169

arswitch_split_setpage(dev, addr, &phy, &reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

170

return arswitch_reg_read32(dev, 0x10 | phy, reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

176

uint16_t phy, reg;

sys/dev/etherswitch/arswitch/arswitch_reg.c

178

arswitch_split_setpage(dev, addr, &phy, &reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

179

return (arswitch_reg_write32(dev, 0x10 | phy, reg, value));

sys/dev/etherswitch/arswitch/arswitch_reg.c

221

uint16_t phy, reg;

sys/dev/etherswitch/arswitch/arswitch_reg.c

226

arswitch_split_setpage(dev, addr, &phy, &reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

228

value = arswitch_reg_read32(dev, 0x10 | phy, reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

231

return (arswitch_reg_write32(dev, 0x10 | phy, reg, value));

sys/dev/etherswitch/arswitch/arswitch_reg.c

239

uint16_t phy, reg;

sys/dev/etherswitch/arswitch/arswitch_reg.c

243

arswitch_split_setpage(dev, addr, &phy, &reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

247

v = arswitch_reg_read32(dev, 0x10 | phy, reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

66

uint16_t *reg)

sys/dev/etherswitch/arswitch/arswitch_reg.c

73

*reg = (addr >> 1) & 0x1f;

sys/dev/etherswitch/arswitch/arswitch_reg.c

90

uint16_t phy, reg;

sys/dev/etherswitch/arswitch/arswitch_reg.c

92

arswitch_split_setpage(dev, addr, &phy, &reg);

sys/dev/etherswitch/arswitch/arswitch_reg.c

93

return (MDIO_READREG(device_get_parent(dev), 0x10 | phy, reg));

sys/dev/etherswitch/arswitch/arswitch_vlans.c

108

uint32_t reg;

sys/dev/etherswitch/arswitch/arswitch_vlans.c

116

reg = arswitch_readreg(sc->sc_dev, AR8X16_REG_VLAN_DATA);

sys/dev/etherswitch/arswitch/arswitch_vlans.c

117

if ((reg & AR8X16_VLAN_VALID) == 0) {

sys/dev/etherswitch/arswitch/arswitch_vlans.c

121

reg &= ((1 << (sc->numphys + 1)) - 1);

sys/dev/etherswitch/arswitch/arswitch_vlans.c

122

*ports = reg;

sys/dev/etherswitch/arswitch/arswitch_vlans.c

123

*untagged_ports = reg;

sys/dev/etherswitch/arswitch/arswitch_vlans.c

144

uint32_t reg;

sys/dev/etherswitch/arswitch/arswitch_vlans.c

149

reg = arswitch_readreg(sc->sc_dev, AR8X16_REG_PORT_VLAN(port));

sys/dev/etherswitch/arswitch/arswitch_vlans.c

150

*ports = (reg >> AR8X16_PORT_VLAN_DEST_PORTS_SHIFT);

sys/dev/etherswitch/arswitch/arswitch_vlans.c

369

uint32_t reg;

sys/dev/etherswitch/arswitch/arswitch_vlans.c

372

reg = arswitch_readreg(sc->sc_dev, AR8X16_REG_PORT_VLAN(port));

sys/dev/etherswitch/arswitch/arswitch_vlans.c

373

*pvid = reg & 0xfff;

sys/dev/etherswitch/e6000sw/e6000sw.c

1014

uint32_t reg;

sys/dev/etherswitch/e6000sw/e6000sw.c

1027

reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2);

sys/dev/etherswitch/e6000sw/e6000sw.c

1029

reg |= PORT_CONTROL2_DISC_TAGGED;

sys/dev/etherswitch/e6000sw/e6000sw.c

1031

reg &= ~PORT_CONTROL2_DISC_TAGGED;

sys/dev/etherswitch/e6000sw/e6000sw.c

1033

reg |= PORT_CONTROL2_DISC_UNTAGGED;

sys/dev/etherswitch/e6000sw/e6000sw.c

1035

reg &= ~PORT_CONTROL2_DISC_UNTAGGED;

sys/dev/etherswitch/e6000sw/e6000sw.c

1036

e6000sw_writereg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2, reg);

sys/dev/etherswitch/e6000sw/e6000sw.c

1055

uint32_t reg;

sys/dev/etherswitch/e6000sw/e6000sw.c

1057

reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP);

sys/dev/etherswitch/e6000sw/e6000sw.c

1058

reg &= ~(PORT_MASK(sc) | PORT_VLAN_MAP_FID_MASK);

sys/dev/etherswitch/e6000sw/e6000sw.c

1059

reg |= members & PORT_MASK(sc) & ~(1 << port);

sys/dev/etherswitch/e6000sw/e6000sw.c

1060

reg |= (fid << PORT_VLAN_MAP_FID) & PORT_VLAN_MAP_FID_MASK;

sys/dev/etherswitch/e6000sw/e6000sw.c

1061

e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VLAN_MAP, reg);

sys/dev/etherswitch/e6000sw/e6000sw.c

1062

reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1);

sys/dev/etherswitch/e6000sw/e6000sw.c

1063

reg &= ~PORT_CONTROL1_FID_MASK;

sys/dev/etherswitch/e6000sw/e6000sw.c

1064

reg |= (fid >> 4) & PORT_CONTROL1_FID_MASK;

sys/dev/etherswitch/e6000sw/e6000sw.c

1065

e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL1, reg);

sys/dev/etherswitch/e6000sw/e6000sw.c

1315

uint32_t port, reg;

sys/dev/etherswitch/e6000sw/e6000sw.c

1326

reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP);

sys/dev/etherswitch/e6000sw/e6000sw.c

1327

vg->es_untagged_ports = vg->es_member_ports = reg & PORT_MASK(sc);

sys/dev/etherswitch/e6000sw/e6000sw.c

1329

vg->es_fid = (reg & PORT_VLAN_MAP_FID_MASK) >> PORT_VLAN_MAP_FID;

sys/dev/etherswitch/e6000sw/e6000sw.c

1330

reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1);

sys/dev/etherswitch/e6000sw/e6000sw.c

1331

vg->es_fid |= (reg & PORT_CONTROL1_FID_MASK) << 4;

sys/dev/etherswitch/e6000sw/e6000sw.c

1340

uint32_t reg;

sys/dev/etherswitch/e6000sw/e6000sw.c

1355

reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_OPERATION);

sys/dev/etherswitch/e6000sw/e6000sw.c

1356

reg &= ~VTU_OP_MASK;

sys/dev/etherswitch/e6000sw/e6000sw.c

1357

reg |= VTU_GET_NEXT | VTU_BUSY;

sys/dev/etherswitch/e6000sw/e6000sw.c

1358

e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, reg);

sys/dev/etherswitch/e6000sw/e6000sw.c

1364

reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_VID);

sys/dev/etherswitch/e6000sw/e6000sw.c

1365

if (reg == VTU_VID_MASK || (reg & VTU_VID_VALID) == 0)

sys/dev/etherswitch/e6000sw/e6000sw.c

1367

if ((reg & VTU_VID_MASK) != vg->es_vid)

sys/dev/etherswitch/e6000sw/e6000sw.c

1371

reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_DATA);

sys/dev/etherswitch/e6000sw/e6000sw.c

1374

reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_DATA2);

sys/dev/etherswitch/e6000sw/e6000sw.c

1375

port = (reg >> VTU_PORT(sc, i)) & VTU_PORT_MASK;

sys/dev/etherswitch/e6000sw/e6000sw.c

1465

e6000sw_readreg(e6000sw_softc_t *sc, int addr, int reg)

sys/dev/etherswitch/e6000sw/e6000sw.c

1471

return (MDIO_READ(sc->dev, addr, reg) & 0xffff);

sys/dev/etherswitch/e6000sw/e6000sw.c

1478

SMI_CMD_OP_C22_READ | (reg & SMI_CMD_REG_ADDR_MASK) |

sys/dev/etherswitch/e6000sw/e6000sw.c

1489

e6000sw_writereg(e6000sw_softc_t *sc, int addr, int reg, int val)

sys/dev/etherswitch/e6000sw/e6000sw.c

1495

MDIO_WRITE(sc->dev, addr, reg, val);

sys/dev/etherswitch/e6000sw/e6000sw.c

1505

SMI_CMD_OP_C22_WRITE | (reg & SMI_CMD_REG_ADDR_MASK) |

sys/dev/etherswitch/e6000sw/e6000sw.c

1549

uint32_t reg;

sys/dev/etherswitch/e6000sw/e6000sw.c

1551

reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID);

sys/dev/etherswitch/e6000sw/e6000sw.c

1552

reg &= ~PORT_VID_DEF_VID_MASK;

sys/dev/etherswitch/e6000sw/e6000sw.c

1553

reg |= (pvid & PORT_VID_DEF_VID_MASK);

sys/dev/etherswitch/e6000sw/e6000sw.c

1554

e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VID, reg);

sys/dev/etherswitch/e6000sw/e6000sw.c

1752

uint32_t reg;

sys/dev/etherswitch/e6000sw/e6000sw.c

1761

reg = e6000sw_readreg(sc, REG_GLOBAL, ATU_OPERATION);

sys/dev/etherswitch/e6000sw/e6000sw.c

1763

(reg | ATU_UNIT_BUSY | flag));

sys/dev/etherswitch/e6000sw/e6000sw.c

504

uint32_t reg;

sys/dev/etherswitch/e6000sw/e6000sw.c

507

reg = e6000sw_read_xmdio(dev, port, E6000SW_SERDES_DEV,

sys/dev/etherswitch/e6000sw/e6000sw.c

510

reg &= ~E6000SW_SERDES_PDOWN;

sys/dev/etherswitch/e6000sw/e6000sw.c

512

reg |= E6000SW_SERDES_PDOWN;

sys/dev/etherswitch/e6000sw/e6000sw.c

514

E6000SW_SERDES_SGMII_CTL, reg);

sys/dev/etherswitch/e6000sw/e6000sw.c

517

reg = e6000sw_read_xmdio(dev, port, E6000SW_SERDES_DEV,

sys/dev/etherswitch/e6000sw/e6000sw.c

520

reg |= E6000SW_SERDES_PDOWN;

sys/dev/etherswitch/e6000sw/e6000sw.c

522

reg &= ~E6000SW_SERDES_PDOWN;

sys/dev/etherswitch/e6000sw/e6000sw.c

524

E6000SW_SERDES_PCS_CTL1, reg);

sys/dev/etherswitch/e6000sw/e6000sw.c

536

uint32_t reg;

sys/dev/etherswitch/e6000sw/e6000sw.c

597

reg = e6000sw_readreg(sc, REG_PORT(sc, port),

sys/dev/etherswitch/e6000sw/e6000sw.c

599

reg &= ~PSC_CONTROL_LINK_UP;

sys/dev/etherswitch/e6000sw/e6000sw.c

600

reg |= PSC_CONTROL_FORCED_LINK;

sys/dev/etherswitch/e6000sw/e6000sw.c

602

reg);

sys/dev/etherswitch/e6000sw/e6000sw.c

608

reg &= ~(PSC_CONTROL_SPD2500 | PSC_CONTROL_ALT_SPD |

sys/dev/etherswitch/e6000sw/e6000sw.c

612

reg |= PSC_CONTROL_SPD2500;

sys/dev/etherswitch/e6000sw/e6000sw.c

614

reg |= PSC_CONTROL_SPD1000;

sys/dev/etherswitch/e6000sw/e6000sw.c

618

reg |= PSC_CONTROL_ALT_SPD;

sys/dev/etherswitch/e6000sw/e6000sw.c

619

reg |= PSC_CONTROL_FORCED_DPX | PSC_CONTROL_FULLDPX |

sys/dev/etherswitch/e6000sw/e6000sw.c

624

reg |= PSC_CONTROL_FORCED_FC | PSC_CONTROL_FC_ON;

sys/dev/etherswitch/e6000sw/e6000sw.c

629

reg |= PSC_CONTROL_FORCED_EEE;

sys/dev/etherswitch/e6000sw/e6000sw.c

631

reg);

sys/dev/etherswitch/e6000sw/e6000sw.c

660

reg = e6000sw_readreg(sc, REG_GLOBAL, SWITCH_GLOBAL_STATUS);

sys/dev/etherswitch/e6000sw/e6000sw.c

661

if (reg & SWITCH_GLOBAL_STATUS_IR)

sys/dev/etherswitch/e6000sw/e6000sw.c

680

e6000sw_waitready(e6000sw_softc_t *sc, uint32_t phy, uint32_t reg,

sys/dev/etherswitch/e6000sw/e6000sw.c

686

if ((e6000sw_readreg(sc, phy, reg) & busybit) == 0)

sys/dev/etherswitch/e6000sw/e6000sw.c

699

uint32_t reg;

sys/dev/etherswitch/e6000sw/e6000sw.c

708

reg = devaddr & SMI_CMD_REG_ADDR_MASK;

sys/dev/etherswitch/e6000sw/e6000sw.c

709

reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK;

sys/dev/etherswitch/e6000sw/e6000sw.c

714

reg | SMI_CMD_OP_C45_ADDR);

sys/dev/etherswitch/e6000sw/e6000sw.c

722

reg | SMI_CMD_OP_C45_READ);

sys/dev/etherswitch/e6000sw/e6000sw.c

729

reg = e6000sw_readreg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG);

sys/dev/etherswitch/e6000sw/e6000sw.c

731

return (reg & PHY_DATA_MASK);

sys/dev/etherswitch/e6000sw/e6000sw.c

738

uint32_t reg;

sys/dev/etherswitch/e6000sw/e6000sw.c

74

#define MDIO_READ(dev, addr, reg) \

sys/dev/etherswitch/e6000sw/e6000sw.c

747

reg = devaddr & SMI_CMD_REG_ADDR_MASK;

sys/dev/etherswitch/e6000sw/e6000sw.c

748

reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK;

sys/dev/etherswitch/e6000sw/e6000sw.c

75

MDIO_READREG(device_get_parent(dev), (addr), (reg))

sys/dev/etherswitch/e6000sw/e6000sw.c

753

reg | SMI_CMD_OP_C45_ADDR);

sys/dev/etherswitch/e6000sw/e6000sw.c

76

#define MDIO_WRITE(dev, addr, reg, val) \

sys/dev/etherswitch/e6000sw/e6000sw.c

762

reg | SMI_CMD_OP_C45_WRITE);

sys/dev/etherswitch/e6000sw/e6000sw.c

768

e6000sw_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/e6000sw/e6000sw.c

77

MDIO_WRITEREG(device_get_parent(dev), (addr), (reg), (val))

sys/dev/etherswitch/e6000sw/e6000sw.c

778

ret = e6000sw_readphy_locked(dev, phy, reg);

sys/dev/etherswitch/e6000sw/e6000sw.c

790

e6000sw_readphy_locked(device_t dev, int phy, int reg)

sys/dev/etherswitch/e6000sw/e6000sw.c

798

if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) {

sys/dev/etherswitch/e6000sw/e6000sw.c

809

SMI_CMD_OP_C22_READ | (reg & SMI_CMD_REG_ADDR_MASK) |

sys/dev/etherswitch/e6000sw/e6000sw.c

822

e6000sw_writephy(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/e6000sw/e6000sw.c

832

ret = e6000sw_writephy_locked(dev, phy, reg, data);

sys/dev/etherswitch/e6000sw/e6000sw.c

840

e6000sw_writephy_locked(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/e6000sw/e6000sw.c

847

if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) {

sys/dev/etherswitch/e6000sw/e6000sw.c

860

SMI_CMD_OP_C22_WRITE | (reg & SMI_CMD_REG_ADDR_MASK) |

sys/dev/etherswitch/e6000sw/e6000sw.c

964

uint32_t reg;

sys/dev/etherswitch/e6000sw/e6000sw.c

978

reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2);

sys/dev/etherswitch/e6000sw/e6000sw.c

979

if (reg & PORT_CONTROL2_DISC_TAGGED)

sys/dev/etherswitch/e6000sw/e6000sw.c

981

if (reg & PORT_CONTROL2_DISC_UNTAGGED)

sys/dev/etherswitch/e6000sw/e6060sw.c

909

e6060sw_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/e6000sw/e6060sw.c

919

if (reg < 0 || reg >= 32)

sys/dev/etherswitch/e6000sw/e6060sw.c

923

data = MDIO_READREG(device_get_parent(dev), phy, reg);

sys/dev/etherswitch/e6000sw/e6060sw.c

930

e6060sw_writephy(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/e6000sw/e6060sw.c

940

if (reg < 0 || reg >= 32)

sys/dev/etherswitch/e6000sw/e6060sw.c

944

err = MDIO_WRITEREG(device_get_parent(dev), phy, reg, data);

sys/dev/etherswitch/etherswitch.c

141

etherswitch_reg_t *reg;

sys/dev/etherswitch/etherswitch.c

153

reg = (etherswitch_reg_t *)data;

sys/dev/etherswitch/etherswitch.c

155

reg->val = ETHERSWITCH_READREG(etherswitch, reg->reg);

sys/dev/etherswitch/etherswitch.c

160

reg = (etherswitch_reg_t *)data;

sys/dev/etherswitch/etherswitch.c

162

error = ETHERSWITCH_WRITEREG(etherswitch, reg->reg, reg->val);

sys/dev/etherswitch/etherswitch.c

184

phyreg->val = ETHERSWITCH_READPHYREG(etherswitch, phyreg->phy, phyreg->reg);

sys/dev/etherswitch/etherswitch.c

189

error = ETHERSWITCH_WRITEPHYREG(etherswitch, phyreg->phy, phyreg->reg, phyreg->val);

sys/dev/etherswitch/etherswitch.h

15

uint32_t reg;

sys/dev/etherswitch/etherswitch.h

22

uint16_t reg;

sys/dev/etherswitch/felix/felix.c

286

uint32_t reg;

sys/dev/etherswitch/felix/felix.c

293

reg = FELIX_RD4(sc, FELIX_DEVCPU_GCB_RST);

sys/dev/etherswitch/felix/felix.c

294

if ((reg & FELIX_DEVCPU_GCB_RST_EN) == 0)

sys/dev/etherswitch/felix/felix.c

307

reg = FELIX_RD4(sc, FELIX_SYS_RAM_CTRL);

sys/dev/etherswitch/felix/felix.c

308

if ((reg & FELIX_SYS_RAM_CTRL_INIT) == 0)

sys/dev/etherswitch/felix/felix.c

544

uint32_t reg;

sys/dev/etherswitch/felix/felix.c

551

reg = FELIX_RD4(sc, FELIX_ANA_VT);

sys/dev/etherswitch/felix/felix.c

552

if ((reg & FELIX_ANA_VT_STS) == FELIX_ANA_VT_IDLE)

sys/dev/etherswitch/felix/felix.c

572

reg = FELIX_ANA_PORT_RD4(sc, i, FELIX_ANA_PORT_VLAN_CFG);

sys/dev/etherswitch/felix/felix.c

573

if ((reg & FELIX_ANA_PORT_VLAN_CFG_VID_MASK) != 0)

sys/dev/etherswitch/felix/felix.c

576

reg |= FELIX_ANA_PORT_VLAN_CFG_VID_AWARE;

sys/dev/etherswitch/felix/felix.c

577

FELIX_ANA_PORT_WR4(sc, i, FELIX_ANA_PORT_VLAN_CFG, reg);

sys/dev/etherswitch/felix/felix.c

630

uint32_t reg;

sys/dev/etherswitch/felix/felix.c

634

reg = FELIX_ANA_PORT_RD4(sc, p->es_port, FELIX_ANA_PORT_DROP_CFG);

sys/dev/etherswitch/felix/felix.c

635

if (reg & FELIX_ANA_PORT_DROP_CFG_TAGGED)

sys/dev/etherswitch/felix/felix.c

638

if (reg & FELIX_ANA_PORT_DROP_CFG_UNTAGGED)

sys/dev/etherswitch/felix/felix.c

641

reg = FELIX_DEVGMII_PORT_RD4(sc, p->es_port, FELIX_DEVGMII_VLAN_CFG);

sys/dev/etherswitch/felix/felix.c

642

if (reg & FELIX_DEVGMII_VLAN_CFG_DOUBLE_ENA)

sys/dev/etherswitch/felix/felix.c

645

reg = FELIX_REW_PORT_RD4(sc, p->es_port, FELIX_REW_PORT_TAG_CFG);

sys/dev/etherswitch/felix/felix.c

646

if (reg & FELIX_REW_PORT_TAG_CFG_ALL)

sys/dev/etherswitch/felix/felix.c

649

reg = FELIX_ANA_PORT_RD4(sc, p->es_port, FELIX_ANA_PORT_VLAN_CFG);

sys/dev/etherswitch/felix/felix.c

650

if (reg & FELIX_ANA_PORT_VLAN_CFG_POP)

sys/dev/etherswitch/felix/felix.c

653

p->es_pvid = reg & FELIX_ANA_PORT_VLAN_CFG_VID_MASK;

sys/dev/etherswitch/felix/felix.c

692

uint32_t reg;

sys/dev/etherswitch/felix/felix.c

694

reg = FELIX_ANA_PORT_RD4(sc, p->es_port, FELIX_ANA_PORT_DROP_CFG);

sys/dev/etherswitch/felix/felix.c

696

reg |= FELIX_ANA_PORT_DROP_CFG_TAGGED;

sys/dev/etherswitch/felix/felix.c

698

reg &= ~FELIX_ANA_PORT_DROP_CFG_TAGGED;

sys/dev/etherswitch/felix/felix.c

701

reg |= FELIX_ANA_PORT_DROP_CFG_UNTAGGED;

sys/dev/etherswitch/felix/felix.c

703

reg &= ~FELIX_ANA_PORT_DROP_CFG_UNTAGGED;

sys/dev/etherswitch/felix/felix.c

705

FELIX_ANA_PORT_WR4(sc, p->es_port, FELIX_ANA_PORT_DROP_CFG, reg);

sys/dev/etherswitch/felix/felix.c

707

reg = FELIX_REW_PORT_RD4(sc, p->es_port, FELIX_REW_PORT_TAG_CFG);

sys/dev/etherswitch/felix/felix.c

709

reg |= FELIX_REW_PORT_TAG_CFG_ALL;

sys/dev/etherswitch/felix/felix.c

711

reg &= ~FELIX_REW_PORT_TAG_CFG_ALL;

sys/dev/etherswitch/felix/felix.c

713

FELIX_REW_PORT_WR4(sc, p->es_port, FELIX_REW_PORT_TAG_CFG, reg);

sys/dev/etherswitch/felix/felix.c

715

reg = FELIX_ANA_PORT_RD4(sc, p->es_port, FELIX_ANA_PORT_VLAN_CFG);

sys/dev/etherswitch/felix/felix.c

717

reg |= FELIX_ANA_PORT_VLAN_CFG_POP;

sys/dev/etherswitch/felix/felix.c

719

reg &= ~FELIX_ANA_PORT_VLAN_CFG_POP;

sys/dev/etherswitch/felix/felix.c

721

reg &= ~FELIX_ANA_PORT_VLAN_CFG_VID_MASK;

sys/dev/etherswitch/felix/felix.c

722

reg |= p->es_pvid & FELIX_ANA_PORT_VLAN_CFG_VID_MASK;

sys/dev/etherswitch/felix/felix.c

730

reg &= ~FELIX_ANA_PORT_VLAN_CFG_VID_AWARE;

sys/dev/etherswitch/felix/felix.c

732

reg |= FELIX_ANA_PORT_VLAN_CFG_VID_AWARE;

sys/dev/etherswitch/felix/felix.c

734

FELIX_ANA_PORT_WR4(sc, p->es_port, FELIX_ANA_PORT_VLAN_CFG, reg);

sys/dev/etherswitch/felix/felix.c

789

felix_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/felix/felix.c

795

return (enetc_mdio_read(sc->mdio, FELIX_MDIO_BASE, phy, reg));

sys/dev/etherswitch/felix/felix.c

799

felix_writephy(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/felix/felix.c

805

return (enetc_mdio_write(sc->mdio, FELIX_MDIO_BASE, phy, reg, data));

sys/dev/etherswitch/felix/felix.c

811

uint32_t reg;

sys/dev/etherswitch/felix/felix.c

845

reg = vg->es_member_ports & FELIX_ANA_VT_PORTMASK_MASK;

sys/dev/etherswitch/felix/felix.c

846

reg <<= FELIX_ANA_VT_PORTMASK_SHIFT;

sys/dev/etherswitch/felix/felix.c

847

reg |= FELIX_ANA_VT_WRITE;

sys/dev/etherswitch/felix/felix.c

850

FELIX_WR4(sc, FELIX_ANA_VT, reg);

sys/dev/etherswitch/felix/felix.c

859

reg = FELIX_RD4(sc, FELIX_ANA_VT);

sys/dev/etherswitch/felix/felix.c

860

if ((reg & FELIX_ANA_VT_STS) != FELIX_ANA_VT_IDLE)

sys/dev/etherswitch/felix/felix.c

887

uint32_t reg;

sys/dev/etherswitch/felix/felix.c

905

reg = FELIX_RD4(sc, FELIX_ANA_VT);

sys/dev/etherswitch/felix/felix.c

906

if ((reg & FELIX_ANA_VT_STS) != FELIX_ANA_VT_IDLE)

sys/dev/etherswitch/felix/felix.c

909

reg >>= FELIX_ANA_VT_PORTMASK_SHIFT;

sys/dev/etherswitch/felix/felix.c

910

reg &= FELIX_ANA_VT_PORTMASK_MASK;

sys/dev/etherswitch/felix/felix.c

912

vg->es_untagged_ports = vg->es_member_ports = reg;

sys/dev/etherswitch/felix/felix_var.h

48

#define FELIX_RD4(sc, reg) bus_read_4((sc)->regs, reg)

sys/dev/etherswitch/felix/felix_var.h

49

#define FELIX_WR4(sc, reg, value) bus_write_4((sc)->regs, reg, value)

sys/dev/etherswitch/felix/felix_var.h

51

#define FELIX_DEVGMII_PORT_RD4(sc, port, reg) \

sys/dev/etherswitch/felix/felix_var.h

53

FELIX_DEVGMII_BASE + (FELIX_DEVGMII_PORT_OFFSET * (port)) + reg)

sys/dev/etherswitch/felix/felix_var.h

54

#define FELIX_DEVGMII_PORT_WR4(sc, port, reg, value) \

sys/dev/etherswitch/felix/felix_var.h

56

FELIX_DEVGMII_BASE + (FELIX_DEVGMII_PORT_OFFSET * (port)) + reg, \

sys/dev/etherswitch/felix/felix_var.h

59

#define FELIX_ANA_PORT_RD4(sc, port, reg) \

sys/dev/etherswitch/felix/felix_var.h

61

FELIX_ANA_PORT_BASE + (FELIX_ANA_PORT_OFFSET * (port)) + reg)

sys/dev/etherswitch/felix/felix_var.h

62

#define FELIX_ANA_PORT_WR4(sc, port, reg, value) \

sys/dev/etherswitch/felix/felix_var.h

64

FELIX_ANA_PORT_BASE + (FELIX_ANA_PORT_OFFSET * (port)) + reg, \

sys/dev/etherswitch/felix/felix_var.h

67

#define FELIX_REW_PORT_RD4(sc, port, reg) \

sys/dev/etherswitch/felix/felix_var.h

69

FELIX_REW_PORT_BASE + (FELIX_REW_PORT_OFFSET * (port)) + reg)

sys/dev/etherswitch/felix/felix_var.h

70

#define FELIX_REW_PORT_WR4(sc, port, reg, value) \

sys/dev/etherswitch/felix/felix_var.h

72

FELIX_REW_PORT_BASE + (FELIX_REW_PORT_OFFSET * (port)) + reg, \

sys/dev/etherswitch/infineon/adm6996fc.c

735

adm6996fc_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/infineon/adm6996fc.c

745

if (reg < 0 || reg >= 32)

sys/dev/etherswitch/infineon/adm6996fc.c

750

(ADM6996FC_PHY_C0 + ADM6996FC_PHY_SIZE * phy) + reg);

sys/dev/etherswitch/infineon/adm6996fc.c

757

adm6996fc_writephy(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/infineon/adm6996fc.c

767

if (reg < 0 || reg >= 32)

sys/dev/etherswitch/infineon/adm6996fc.c

772

(ADM6996FC_PHY_C0 + ADM6996FC_PHY_SIZE * phy) + reg, data);

sys/dev/etherswitch/ip17x/ip175c.c

106

memset(reg, 0, sizeof(reg));

sys/dev/etherswitch/ip17x/ip175c.c

108

reg[i] = ports[i * 2] << 8 | ports[i * 2 + 1];

sys/dev/etherswitch/ip17x/ip175c.c

111

err = ip17x_writephy(sc->sc_dev, 29, 19, reg[0]);

sys/dev/etherswitch/ip17x/ip175c.c

113

err = ip17x_writephy(sc->sc_dev, 29, 20, reg[1]);

sys/dev/etherswitch/ip17x/ip175c.c

115

err = ip17x_updatephy(sc->sc_dev, 29, 21, 0xff00, reg[2]);

sys/dev/etherswitch/ip17x/ip175c.c

117

err = ip17x_updatephy(sc->sc_dev, 30, 18, 0x00ff, reg[2]);

sys/dev/etherswitch/ip17x/ip175c.c

83

uint32_t ports[IP175X_NUM_PORTS], reg[IP175X_NUM_PORTS/2];

sys/dev/etherswitch/ip17x/ip17x_phy.c

100

val = ip17x_readphy(dev, phy, reg);

sys/dev/etherswitch/ip17x/ip17x_phy.c

103

return (ip17x_writephy(dev, phy, reg, val));

sys/dev/etherswitch/ip17x/ip17x_phy.c

54

ip17x_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/ip17x/ip17x_phy.c

64

if (reg < 0 || reg >= 32)

sys/dev/etherswitch/ip17x/ip17x_phy.c

68

data = MDIO_READREG(device_get_parent(dev), phy, reg);

sys/dev/etherswitch/ip17x/ip17x_phy.c

75

ip17x_writephy(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/ip17x/ip17x_phy.c

85

if (reg < 0 || reg >= 32)

sys/dev/etherswitch/ip17x/ip17x_phy.c

89

err = MDIO_WRITEREG(device_get_parent(dev), phy, reg, data);

sys/dev/etherswitch/ip17x/ip17x_phy.c

96

ip17x_updatephy(device_t dev, int phy, int reg, int mask, int value)

sys/dev/etherswitch/micrel/ksz8995ma.c

273

int err, reg;

sys/dev/etherswitch/micrel/ksz8995ma.c

321

reg = ksz8995ma_readreg(dev, KSZ8995MA_GC3);

sys/dev/etherswitch/micrel/ksz8995ma.c

323

reg & ~KSZ8995MA_VLAN_ENABLE);

sys/dev/etherswitch/micrel/ksz8995ma.c

714

int reg;

sys/dev/etherswitch/micrel/ksz8995ma.c

724

reg = ksz8995ma_readreg(dev, KSZ8995MA_GC3);

sys/dev/etherswitch/micrel/ksz8995ma.c

726

reg & ~KSZ8995MA_VLAN_ENABLE);

sys/dev/etherswitch/micrel/ksz8995ma.c

730

reg = ksz8995ma_readreg(dev, KSZ8995MA_GC3);

sys/dev/etherswitch/micrel/ksz8995ma.c

732

reg | KSZ8995MA_VLAN_ENABLE);

sys/dev/etherswitch/micrel/ksz8995ma.c

735

reg = ksz8995ma_readreg(dev, KSZ8995MA_GC3);

sys/dev/etherswitch/micrel/ksz8995ma.c

737

reg & ~KSZ8995MA_VLAN_ENABLE);

sys/dev/etherswitch/micrel/ksz8995ma.c

785

ksz8995ma_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/micrel/ksz8995ma.c

793

if (reg == MII_BMSR) {

sys/dev/etherswitch/micrel/ksz8995ma.c

799

} else if (reg == MII_PHYIDR1) {

sys/dev/etherswitch/micrel/ksz8995ma.c

801

} else if (reg == MII_PHYIDR2) {

sys/dev/etherswitch/micrel/ksz8995ma.c

803

} else if (reg == MII_ANAR) {

sys/dev/etherswitch/micrel/ksz8995ma.c

807

} else if (reg == MII_ANLPAR) {

sys/dev/etherswitch/micrel/ksz8995ma.c

817

ksz8995ma_writephy(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/micrel/ksz8995ma.c

825

if (reg == MII_BMCR) {

sys/dev/etherswitch/micrel/ksz8995ma.c

838

} else if (reg == MII_ANAR) {

sys/dev/etherswitch/miiproxy.c

282

miiproxy_readreg(device_t dev, int phy, int reg)

sys/dev/etherswitch/miiproxy.c

287

return (MDIO_READREG(sc->mdio, phy, reg));

sys/dev/etherswitch/miiproxy.c

292

miiproxy_writereg(device_t dev, int phy, int reg, int val)

sys/dev/etherswitch/miiproxy.c

297

return (MDIO_WRITEREG(sc->mdio, phy, reg, val));

sys/dev/etherswitch/mtkswitch/mtkswitch.c

587

mtkswitch_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/mtkswitch/mtkswitch.c

591

return (sc->hal.mtkswitch_phy_read(dev, phy, reg));

sys/dev/etherswitch/mtkswitch/mtkswitch.c

595

mtkswitch_writephy(device_t dev, int phy, int reg, int val)

sys/dev/etherswitch/mtkswitch/mtkswitch.c

599

return (sc->hal.mtkswitch_phy_write(dev, phy, reg, val));

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

100

mtkswitch_phy_write(device_t dev, int phy, int reg, int val)

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

105

if ((phy < 0 || phy >= 32) || (reg < 0 || reg >= 32))

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

110

res = mtkswitch_phy_write_locked(sc, phy, reg, val);

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

117

mtkswitch_reg_read32(struct mtkswitch_softc *sc, int reg)

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

120

return (MTKSWITCH_READ(sc, reg));

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

124

mtkswitch_reg_write32(struct mtkswitch_softc *sc, int reg, uint32_t val)

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

127

MTKSWITCH_WRITE(sc, reg, val);

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

132

mtkswitch_reg_read32_mt7621(struct mtkswitch_softc *sc, int reg)

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

137

MTKSWITCH_GLOBAL_REG, MTKSWITCH_REG_ADDR(reg));

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

139

MTKSWITCH_REG_LO(reg));

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

141

MTKSWITCH_REG_HI(reg));

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

146

mtkswitch_reg_write32_mt7621(struct mtkswitch_softc *sc, int reg, uint32_t val)

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

150

MTKSWITCH_GLOBAL_REG, MTKSWITCH_REG_ADDR(reg));

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

152

MTKSWITCH_REG_LO(reg), MTKSWITCH_VAL_LO(val));

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

154

MTKSWITCH_REG_HI(reg), MTKSWITCH_VAL_HI(val));

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

159

mtkswitch_reg_read(device_t dev, int reg)

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

164

val = sc->hal.mtkswitch_read(sc, MTKSWITCH_REG32(reg));

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

165

if (MTKSWITCH_IS_HI16(reg))

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

171

mtkswitch_reg_write(device_t dev, int reg, int val)

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

176

tmp = sc->hal.mtkswitch_read(sc, MTKSWITCH_REG32(reg));

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

177

if (MTKSWITCH_IS_HI16(reg)) {

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

184

sc->hal.mtkswitch_write(sc, MTKSWITCH_REG32(reg), tmp);

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

57

mtkswitch_phy_read_locked(struct mtkswitch_softc *sc, int phy, int reg)

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

62

(reg << PIAC_MDIO_REG_ADDR_OFF) | (phy << PIAC_MDIO_PHY_ADDR_OFF) |

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

70

mtkswitch_phy_read(device_t dev, int phy, int reg)

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

75

if ((phy < 0 || phy >= 32) || (reg < 0 || reg >= 32))

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

80

data = mtkswitch_phy_read_locked(sc, phy, reg);

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

87

mtkswitch_phy_write_locked(struct mtkswitch_softc *sc, int phy, int reg,

sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c

92

(reg << PIAC_MDIO_REG_ADDR_OFF) | (phy << PIAC_MDIO_PHY_ADDR_OFF) |

sys/dev/etherswitch/mtkswitch/mtkswitch_rt3050.c

108

mtkswitch_phy_write(device_t dev, int phy, int reg, int val)

sys/dev/etherswitch/mtkswitch/mtkswitch_rt3050.c

115

MTKSWITCH_WRITE(sc, MTKSWITCH_PCR0, PCR0_WRITE | PCR0_REG(reg) |

sys/dev/etherswitch/mtkswitch/mtkswitch_rt3050.c

57

mtkswitch_reg_read(device_t dev, int reg)

sys/dev/etherswitch/mtkswitch/mtkswitch_rt3050.c

63

val = MTKSWITCH_READ(sc, MTKSWITCH_REG32(reg));

sys/dev/etherswitch/mtkswitch/mtkswitch_rt3050.c

64

if (MTKSWITCH_IS_HI16(reg))

sys/dev/etherswitch/mtkswitch/mtkswitch_rt3050.c

70

mtkswitch_reg_write(device_t dev, int reg, int val)

sys/dev/etherswitch/mtkswitch/mtkswitch_rt3050.c

76

tmp = MTKSWITCH_READ(sc, MTKSWITCH_REG32(reg));

sys/dev/etherswitch/mtkswitch/mtkswitch_rt3050.c

77

if (MTKSWITCH_IS_HI16(reg)) {

sys/dev/etherswitch/mtkswitch/mtkswitch_rt3050.c

84

MTKSWITCH_WRITE(sc, MTKSWITCH_REG32(reg), tmp);

sys/dev/etherswitch/mtkswitch/mtkswitch_rt3050.c

90

mtkswitch_phy_read(device_t dev, int phy, int reg)

sys/dev/etherswitch/mtkswitch/mtkswitch_rt3050.c

98

MTKSWITCH_WRITE(sc, MTKSWITCH_PCR0, PCR0_READ | PCR0_REG(reg) |

sys/dev/etherswitch/rtl8366/rtl8366rb.c

631

rtl_readreg(device_t dev, int reg)

sys/dev/etherswitch/rtl8366/rtl8366rb.c

637

smi_read(dev, reg, &data, RTL_WAITOK);

sys/dev/etherswitch/rtl8366/rtl8366rb.c

642

rtl_writereg(device_t dev, int reg, int value)

sys/dev/etherswitch/rtl8366/rtl8366rb.c

644

return (smi_write(dev, reg, value, RTL_WAITOK));

sys/dev/etherswitch/rtl8366/rtl8366rb.c

821

rtl_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/rtl8366/rtl8366rb.c

833

if (reg < 0 || reg >= RTL8366_NUM_PHY_REG)

sys/dev/etherswitch/rtl8366/rtl8366rb.c

842

err = smi_write_locked(sc, RTL8366_PHYREG(phy, 0, reg), 0, sleep);

sys/dev/etherswitch/rtl8366/rtl8366rb.c

852

DEVERR(dev, err, "rtl_readphy()=%d: phy=%d.%02x\n", phy, reg);

sys/dev/etherswitch/rtl8366/rtl8366rb.c

857

rtl_writephy(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/rtl8366/rtl8366rb.c

866

if (reg < 0 || reg >= RTL8366_NUM_PHY_REG)

sys/dev/etherswitch/rtl8366/rtl8366rb.c

875

err = smi_write_locked(sc, RTL8366_PHYREG(phy, 0, reg), data, sleep);

sys/dev/etherswitch/rtl8366/rtl8366rb.c

884

DEVERR(dev, err, "rtl_writephy()=%d: phy=%d.%02x\n", phy, reg);

sys/dev/etherswitch/rtl8366/rtl8366rbvar.h

175

#define RTL8366_PHYREG(phy, page, reg) \

sys/dev/etherswitch/rtl8366/rtl8366rbvar.h

176

(0x8000 | (1 << (((phy) & 0x1f) + 9)) | (((page) & (sc->chip_type == 0 ? 0xf : 0x7)) << 5) | ((reg) & 0x1f))

sys/dev/etherswitch/ukswitch/ukswitch.c

466

ukswitch_readphy(device_t dev, int phy, int reg)

sys/dev/etherswitch/ukswitch/ukswitch.c

476

if (reg < 0 || reg >= 32)

sys/dev/etherswitch/ukswitch/ukswitch.c

480

data = MDIO_READREG(device_get_parent(dev), phy, reg);

sys/dev/etherswitch/ukswitch/ukswitch.c

487

ukswitch_writephy(device_t dev, int phy, int reg, int data)

sys/dev/etherswitch/ukswitch/ukswitch.c

497

if (reg < 0 || reg >= 32)

sys/dev/etherswitch/ukswitch/ukswitch.c

501

err = MDIO_WRITEREG(device_get_parent(dev), phy, reg, data);

sys/dev/exca/exca.c

144

exca_mem_getb(struct exca_softc *sc, int reg)

sys/dev/exca/exca.c

146

return (bus_space_read_1(sc->bst, sc->bsh, sc->offset + reg));

sys/dev/exca/exca.c

150

exca_mem_putb(struct exca_softc *sc, int reg, uint8_t val)

sys/dev/exca/exca.c

152

bus_space_write_1(sc->bst, sc->bsh, sc->offset + reg, val);

sys/dev/exca/exca.c

156

exca_io_getb(struct exca_softc *sc, int reg)

sys/dev/exca/exca.c

158

bus_space_write_1(sc->bst, sc->bsh, EXCA_REG_INDEX, reg + sc->offset);

sys/dev/exca/exca.c

163

exca_io_putb(struct exca_softc *sc, int reg, uint8_t val)

sys/dev/exca/exca.c

165

bus_space_write_1(sc->bst, sc->bsh, EXCA_REG_INDEX, reg + sc->offset);

sys/dev/exca/excavar.h

130

exca_getb(struct exca_softc *sc, int reg)

sys/dev/exca/excavar.h

132

return (sc->getb(sc, reg));

sys/dev/exca/excavar.h

136

exca_putb(struct exca_softc *sc, int reg, uint8_t val)

sys/dev/exca/excavar.h

138

sc->putb(sc, reg, val);

sys/dev/exca/excavar.h

142

exca_setb(struct exca_softc *sc, int reg, uint8_t mask)

sys/dev/exca/excavar.h

144

exca_putb(sc, reg, exca_getb(sc, reg) | mask);

sys/dev/exca/excavar.h

148

exca_clrb(struct exca_softc *sc, int reg, uint8_t mask)

sys/dev/exca/excavar.h

150

exca_putb(sc, reg, exca_getb(sc, reg) & ~mask);

sys/dev/fdc/fdc.c

319

fdregwr(struct fdc_data *fdc, int reg, uint8_t v)

sys/dev/fdc/fdc.c

322

bus_space_write_1(fdc->iot, fdc->ioh[reg], fdc->ioff[reg], v);

sys/dev/fdc/fdc.c

326

fdregrd(struct fdc_data *fdc, int reg)

sys/dev/fdc/fdc.c

329

return bus_space_read_1(fdc->iot, fdc->ioh[reg], fdc->ioff[reg]);

sys/dev/fdt/fdt_arm_platform.c

74

fdt_platform_maxid(u_int id, phandle_t node, u_int addr_cells, pcell_t *reg)

sys/dev/fdt/fdt_common.c

323

pcell_t reg[4];

sys/dev/fdt/fdt_common.c

329

if ((sizeof(pcell_t) * (addr_cells + size_cells)) > sizeof(reg))

sys/dev/fdt/fdt_common.c

332

len = OF_getprop(node, "reg", &reg, sizeof(reg));

sys/dev/fdt/fdt_common.c

336

*base = fdt_data_get(&reg[0], addr_cells);

sys/dev/fdt/fdt_common.c

337

*size = fdt_data_get(&reg[addr_cells], size_cells);

sys/dev/fdt/fdt_common.c

461

pcell_t reg[FDT_REG_CELLS];

sys/dev/fdt/fdt_common.c

481

rv = OF_getprop(child, "reg", reg, sizeof(reg));

sys/dev/fdt/fdt_common.c

487

fdt_data_to_res(reg, addr_cells, size_cells,

sys/dev/fdt/fdt_common.c

500

pcell_t reg[FDT_REG_CELLS * FDT_MEM_REGIONS];

sys/dev/fdt/fdt_common.c

519

if (reg_len <= 0 || reg_len > sizeof(reg))

sys/dev/fdt/fdt_common.c

522

if (OF_getprop(memory, "reg", reg, reg_len) <= 0)

sys/dev/fdt/fdt_common.c

526

regp = (pcell_t *)®

sys/dev/ffec/if_ffec.c

318

ffec_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/ffec/if_ffec.c

330

((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK));

sys/dev/ffec/if_ffec.c

343

ffec_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/ffec/if_ffec.c

354

((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) |

sys/dev/firewire/firewire.c

1465

struct csrreg *reg;

sys/dev/firewire/firewire.c

1474

reg = (struct csrreg *)&fwdev->csrrom[offset / sizeof(uint32_t)];

sys/dev/firewire/firewire.c

1476

(uint32_t *)reg, dir->crc_len);

sys/dev/firewire/firewire.c

1490

if ((reg[i].key & CSRTYPE_MASK) == CSRTYPE_D)

sys/dev/firewire/firewire.c

1492

else if ((reg[i].key & CSRTYPE_MASK) == CSRTYPE_L)

sys/dev/firewire/firewire.c

1497

off = offset + reg[i].val * sizeof(uint32_t);

sys/dev/firewire/fwcrom.c

105

struct csrreg *reg;

sys/dev/firewire/fwcrom.c

109

reg = crom_get(cc);

sys/dev/firewire/fwcrom.c

110

if ((reg->key & CSRTYPE_MASK) == CSRTYPE_D) {

sys/dev/firewire/fwcrom.c

118

ptr->dir = (struct csrdirectory *) (reg + reg->val);

sys/dev/firewire/fwcrom.c

145

struct csrreg *reg;

sys/dev/firewire/fwcrom.c

148

reg = crom_get(cc);

sys/dev/firewire/fwcrom.c

149

if (reg->key == key)

sys/dev/firewire/fwcrom.c

150

return reg;

sys/dev/firewire/fwcrom.c

159

struct csrreg *reg;

sys/dev/firewire/fwcrom.c

166

reg = crom_get(cc);

sys/dev/firewire/fwcrom.c

168

if (reg->key == CSRKEY_SPEC && reg->val == spec)

sys/dev/firewire/fwcrom.c

173

if (reg->key == CSRKEY_VER && reg->val == ver)

sys/dev/firewire/fwcrom.c

186

struct csrreg *reg;

sys/dev/firewire/fwcrom.c

195

reg = crom_get(cc);

sys/dev/firewire/fwcrom.c

196

if (reg->key != CROM_TEXTLEAF ||

sys/dev/firewire/fwcrom.c

197

(vm_offset_t)(reg + reg->val) > CROM_END(cc)) {

sys/dev/firewire/fwcrom.c

201

textleaf = (struct csrtext *)(reg + reg->val);

sys/dev/firewire/fwcrom.c

297

struct csrreg *reg;

sys/dev/firewire/fwcrom.c

302

reg = crom_get(cc);

sys/dev/firewire/fwcrom.c

303

switch (reg->key & CSRTYPE_MASK) {

sys/dev/firewire/fwcrom.c

306

len -= snprintf(buf, len, "%d", reg->val);

sys/dev/firewire/fwcrom.c

314

reg->val, reg->val);

sys/dev/firewire/fwcrom.c

320

dir = (struct csrdirectory *)(reg + reg->val);

sys/dev/firewire/fwcrom.c

327

switch (reg->key) {

sys/dev/firewire/fwcrom.c

342

crom_desc_specver(0, reg->val, buf, len);

sys/dev/firewire/fwcrom.c

410

struct csrreg reg;

sys/dev/firewire/fwcrom.c

414

foo.reg.key = key;

sys/dev/firewire/fwcrom.c

415

foo.reg.val = val;

sys/dev/firewire/fwcrom.c

500

struct csrreg *reg;

sys/dev/firewire/fwcrom.c

501

reg = (struct csrreg *)

sys/dev/firewire/fwcrom.c

503

reg->val = offset -

sys/dev/firewire/fwohci.c

357

struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data;

sys/dev/firewire/fwohci.c

372

if (reg->addr <= OHCI_MAX_REG) {

sys/dev/firewire/fwohci.c

373

OWRITE(fc, reg->addr, reg->data);

sys/dev/firewire/fwohci.c

374

reg->data = OREAD(fc, reg->addr);

sys/dev/firewire/fwohci.c

380

if (reg->addr <= OHCI_MAX_REG) {

sys/dev/firewire/fwohci.c

381

reg->data = OREAD(fc, reg->addr);

sys/dev/firewire/fwohci.c

398

if (reg->addr <= OHCI_MAX_PHY_REG)

sys/dev/firewire/fwohci.c

399

reg->data = fwphy_rddata(fc, reg->addr);

sys/dev/firewire/fwohci.c

404

if (reg->addr <= OHCI_MAX_PHY_REG)

sys/dev/firewire/fwohci.c

405

reg->data = fwphy_wrdata(fc, reg->addr, reg->data);

sys/dev/firewire/fwohci.c

419

uint32_t reg, reg2;

sys/dev/firewire/fwohci.c

432

reg = fwphy_rddata(sc, FW_PHY_SPD_REG);

sys/dev/firewire/fwohci.c

434

if ((reg >> 5) != 7) {

sys/dev/firewire/fwohci.c

436

sc->fc.nport = reg & FW_PHY_NP;

sys/dev/firewire/fwohci.c

437

sc->fc.speed = reg & FW_PHY_SPD >> 6;

sys/dev/firewire/fwohci.c

449

sc->fc.nport = reg & FW_PHY_NP;

sys/dev/firewire/fwohci.c

482

reg = fwphy_rddata(sc, FW_PHY_SPD_REG);

sys/dev/firewire/fwohci.c

483

if ((reg >> 5) == 7) {

sys/dev/firewire/fwohci.c

484

reg = fwphy_rddata(sc, 4);

sys/dev/firewire/fwohci.c

485

reg |= 1 << 6;

sys/dev/firewire/fwohci.c

486

fwphy_wrdata(sc, 4, reg);

sys/dev/firewire/fwohci.c

487

reg = fwphy_rddata(sc, 4);

sys/dev/firewire/fwohci.c

497

uint32_t reg, reg2;

sys/dev/firewire/fwohci.c

531

reg = OREAD(sc, OHCI_BUS_OPT);

sys/dev/firewire/fwohci.c

532

reg2 = reg | OHCI_BUSFNC;

sys/dev/firewire/fwohci.c

533

max_rec = (reg & 0x0000f000) >> 12;

sys/dev/firewire/fwohci.c

534

speed = (reg & 0x00000007);

sys/dev/firewire/fwohci.c

545

device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);

sys/dev/firewire/fwohci.c

603

uint32_t reg;

sys/dev/firewire/fwohci.c

607

reg = OREAD(sc, OHCI_VERSION);

sys/dev/firewire/fwohci.c

608

mver = (reg >> 16) & 0xff;

sys/dev/firewire/fwohci.c

610

mver, reg & 0xff, (reg >> 24) & 1);

sys/dev/firewire/fwohci.c

619

reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);

sys/dev/firewire/fwohci.c

623

if ((reg & (1 << i)) == 0)

sys/dev/firewire/sbp.c

418

struct csrreg *reg;

sys/dev/firewire/sbp.c

428

reg = crom_search_key(&cc, CROM_LUN);

sys/dev/firewire/sbp.c

429

if (reg == NULL)

sys/dev/firewire/sbp.c

431

lun = reg->val & 0xffff;

sys/dev/firewire/sbp.c

490

reg = crom_search_key(&cc, CROM_LUN);

sys/dev/firewire/sbp.c

491

if (reg == NULL)

sys/dev/firewire/sbp.c

493

lun = reg->val & 0xffff;

sys/dev/firewire/sbp.c

520

sdev->type = (reg->val & 0xff0000) >> 16;

sys/dev/firewire/sbp.c

580

struct csrreg *reg;

sys/dev/firewire/sbp.c

597

reg = crom_search_key(&cc, CROM_MGM);

sys/dev/firewire/sbp.c

598

if (reg == NULL || reg->val == 0) {

sys/dev/firewire/sbp.c

604

target->mgm_lo = 0xf0000000 | (reg->val << 2);

sys/dev/firewire/sbp.c

625

struct csrreg *reg;

sys/dev/firewire/sbp.c

637

while ((reg = crom_search_key(cc, CSRKEY_VER)) != NULL) {

sys/dev/firewire/sbp.c

638

if (reg->val == CSRVAL_T10SBP2)

sys/dev/firewire/sbp.c

643

reg = crom_search_key(cc, CSRKEY_FIRM_VER);

sys/dev/firewire/sbp.c

644

if (reg != NULL)

sys/dev/firewire/sbp.c

646

"%06x", reg->val);

sys/dev/firewire/sbp_targ.c

1800

int reg)

sys/dev/firewire/sbp_targ.c

1819

switch (reg) {

sys/dev/firewire/sbp_targ.c

1867

__func__, reg, login_id);

sys/dev/firmware/arm/scmi_clk.c

348

uint32_t reg;

sys/dev/firmware/arm/scmi_clk.c

353

error = OF_getencprop(node, "reg", &reg, sizeof(uint32_t));

sys/dev/firmware/arm/scmi_clk.c

357

if (reg != SCMI_PROTOCOL_ID_CLOCK)

sys/dev/firmware/arm/scmi_shmem.c

101

OF_getencprop(node, "reg", &reg, sizeof(reg));

sys/dev/firmware/arm/scmi_shmem.c

103

sc->reg = reg;

sys/dev/firmware/arm/scmi_shmem.c

130

addr[i] = MMIO_SRAM_READ_1(sc->parent, sc->reg + offset + i);

sys/dev/firmware/arm/scmi_shmem.c

146

MMIO_SRAM_WRITE_1(sc->parent, sc->reg + offset + i, addr[i]);

sys/dev/firmware/arm/scmi_shmem.c

57

int reg;

sys/dev/firmware/arm/scmi_shmem.c

91

int reg;

sys/dev/flash/cqspi.c

255

uint32_t reg;

sys/dev/flash/cqspi.c

261

reg = (cmd << FLASHCMD_CMDOPCODE_S);

sys/dev/flash/cqspi.c

262

reg |= (FLASHCMD_ENCMDADDR);

sys/dev/flash/cqspi.c

263

reg |= ((len - 1) << FLASHCMD_NUMADDRBYTES_S);

sys/dev/flash/cqspi.c

264

WRITE4(sc, CQSPI_FLASHCMD, reg);

sys/dev/flash/cqspi.c

266

reg |= FLASHCMD_EXECCMD;

sys/dev/flash/cqspi.c

267

WRITE4(sc, CQSPI_FLASHCMD, reg);

sys/dev/flash/cqspi.c

278

uint32_t reg;

sys/dev/flash/cqspi.c

281

reg = (cmd << FLASHCMD_CMDOPCODE_S);

sys/dev/flash/cqspi.c

282

WRITE4(sc, CQSPI_FLASHCMD, reg);

sys/dev/flash/cqspi.c

283

reg |= FLASHCMD_EXECCMD;

sys/dev/flash/cqspi.c

284

WRITE4(sc, CQSPI_FLASHCMD, reg);

sys/dev/flash/cqspi.c

296

uint32_t reg;

sys/dev/flash/cqspi.c

310

reg = (cmd << FLASHCMD_CMDOPCODE_S);

sys/dev/flash/cqspi.c

311

reg |= ((len - 1) << FLASHCMD_NUMRDDATABYTES_S);

sys/dev/flash/cqspi.c

312

reg |= FLASHCMD_ENRDDATA;

sys/dev/flash/cqspi.c

313

WRITE4(sc, CQSPI_FLASHCMD, reg);

sys/dev/flash/cqspi.c

315

reg |= FLASHCMD_EXECCMD;

sys/dev/flash/cqspi.c

316

WRITE4(sc, CQSPI_FLASHCMD, reg);

sys/dev/flash/cqspi.c

376

uint32_t reg;

sys/dev/flash/cqspi.c

379

reg = READ4(sc, CQSPI_CFG);

sys/dev/flash/cqspi.c

380

if (reg & CFG_IDLE) {

sys/dev/flash/cqspi.c

413

uint32_t reg;

sys/dev/flash/cqspi.c

427

reg = DMAPER_NUMSGLREQBYTES_4;

sys/dev/flash/cqspi.c

428

reg |= DMAPER_NUMBURSTREQBYTES_4;

sys/dev/flash/cqspi.c

429

WRITE4(sc, CQSPI_DMAPER, reg);

sys/dev/flash/cqspi.c

438

reg = (0 << DEVWR_DUMMYWRCLKS_S);

sys/dev/flash/cqspi.c

439

reg |= DEVWR_DATA_WIDTH_QUAD;

sys/dev/flash/cqspi.c

440

reg |= DEVWR_ADDR_WIDTH_SINGLE;

sys/dev/flash/cqspi.c

441

reg |= (CMD_QUAD_PAGE_PROGRAM << DEVWR_WROPCODE_S);

sys/dev/flash/cqspi.c

442

WRITE4(sc, CQSPI_DEVWR, reg);

sys/dev/flash/cqspi.c

444

reg = DEVRD_DATA_WIDTH_QUAD;

sys/dev/flash/cqspi.c

445

reg |= DEVRD_ADDR_WIDTH_SINGLE;

sys/dev/flash/cqspi.c

446

reg |= DEVRD_INST_WIDTH_SINGLE;

sys/dev/flash/cqspi.c

447

WRITE4(sc, CQSPI_DEVRD, reg);

sys/dev/flash/cqspi.c

470

uint32_t reg;

sys/dev/flash/cqspi.c

479

reg = DMAPER_NUMSGLREQBYTES_4;

sys/dev/flash/cqspi.c

480

reg |= DMAPER_NUMBURSTREQBYTES_4;

sys/dev/flash/cqspi.c

481

WRITE4(sc, CQSPI_DMAPER, reg);

sys/dev/flash/cqspi.c

490

reg = (0 << DEVRD_DUMMYRDCLKS_S);

sys/dev/flash/cqspi.c

491

reg |= DEVRD_DATA_WIDTH_QUAD;

sys/dev/flash/cqspi.c

492

reg |= DEVRD_ADDR_WIDTH_SINGLE;

sys/dev/flash/cqspi.c

493

reg |= DEVRD_INST_WIDTH_SINGLE;

sys/dev/flash/cqspi.c

494

reg |= DEVRD_ENMODEBITS;

sys/dev/flash/cqspi.c

495

reg |= (CMD_READ_4B_QUAD_OUTPUT << DEVRD_RDOPCODE_S);

sys/dev/flash/cqspi.c

496

WRITE4(sc, CQSPI_DEVRD, reg);

sys/dev/flash/cqspi.c

522

uint32_t reg;

sys/dev/flash/cqspi.c

551

reg = READ4(sc, CQSPI_CFG);

sys/dev/flash/cqspi.c

552

reg &= ~(CFG_EN);

sys/dev/flash/cqspi.c

553

WRITE4(sc, CQSPI_CFG, reg);

sys/dev/flash/cqspi.c

555

reg = READ4(sc, CQSPI_DEVSZ);

sys/dev/flash/cqspi.c

556

reg &= ~(DEVSZ_NUMADDRBYTES_M);

sys/dev/flash/cqspi.c

557

reg |= ((4 - 1) - DEVSZ_NUMADDRBYTES_S);

sys/dev/flash/cqspi.c

558

WRITE4(sc, CQSPI_DEVSZ, reg);

sys/dev/flash/cqspi.c

564

reg = READ4(sc, CQSPI_CFG);

sys/dev/flash/cqspi.c

566

reg &= ~(CFG_BAUD_M);

sys/dev/flash/cqspi.c

567

reg |= CFG_BAUD12;

sys/dev/flash/cqspi.c

568

reg |= CFG_ENDMA;

sys/dev/flash/cqspi.c

569

WRITE4(sc, CQSPI_CFG, reg);

sys/dev/flash/cqspi.c

571

reg = (3 << DELAY_NSS_S);

sys/dev/flash/cqspi.c

572

reg |= (3 << DELAY_BTWN_S);

sys/dev/flash/cqspi.c

573

reg |= (1 << DELAY_AFTER_S);

sys/dev/flash/cqspi.c

574

reg |= (1 << DELAY_INIT_S);

sys/dev/flash/cqspi.c

575

WRITE4(sc, CQSPI_DELAY, reg);

sys/dev/flash/cqspi.c

578

reg &= ~(RDDATACAP_DELAY_M);

sys/dev/flash/cqspi.c

579

reg |= (1 << RDDATACAP_DELAY_S);

sys/dev/flash/cqspi.c

580

WRITE4(sc, CQSPI_RDDATACAP, reg);

sys/dev/flash/cqspi.c

583

reg = READ4(sc, CQSPI_CFG);

sys/dev/flash/cqspi.c

584

reg |= (CFG_EN);

sys/dev/flash/cqspi.c

585

WRITE4(sc, CQSPI_CFG, reg);

sys/dev/flash/flexspi/flex_spi.c

150

uint32_t reg;

sys/dev/flash/flexspi/flex_spi.c

154

reg = read_reg(sc, offset);

sys/dev/flash/flexspi/flex_spi.c

156

condition = ((reg & mask) == 0);

sys/dev/flash/flexspi/flex_spi.c

158

condition = ((reg & mask) != 0);

sys/dev/flash/flexspi/flex_spi.c

289

int i, ret, reg;

sys/dev/flash/flexspi/flex_spi.c

306

reg = read_reg(sc, FSPI_RFDR);

sys/dev/flash/flexspi/flex_spi.c

308

reg = read_reg(sc, FSPI_RFDR + 4);

sys/dev/flash/flexspi/flex_spi.c

311

*(uint32_t *)(buf + i) = reg;

sys/dev/flash/flexspi/flex_spi.c

313

memcpy(buf + i, &reg, size - i);

sys/dev/flash/flexspi/flex_spi.c

329

int i, ret, reg;

sys/dev/flash/flexspi/flex_spi.c

349

reg = *(uint32_t *)(buf + i);

sys/dev/flash/flexspi/flex_spi.c

351

reg = 0;

sys/dev/flash/flexspi/flex_spi.c

352

memcpy(&reg, buf + i, size - i);

sys/dev/flash/flexspi/flex_spi.c

356

write_reg(sc, FSPI_TFDR, reg);

sys/dev/flash/flexspi/flex_spi.c

358

write_reg(sc, FSPI_TFDR + 4, reg);

sys/dev/flash/flexspi/flex_spi.c

374

uint32_t cnt = 1000, reg;

sys/dev/flash/flexspi/flex_spi.c

376

reg = read_reg(sc, FSPI_IPRXFCR);

sys/dev/flash/flexspi/flex_spi.c

378

reg &= ~FSPI_IPRXFCR_DMA_EN;

sys/dev/flash/flexspi/flex_spi.c

379

reg |= FSPI_IPRXFCR_CLR;

sys/dev/flash/flexspi/flex_spi.c

380

write_reg(sc, FSPI_IPRXFCR, reg);

sys/dev/flash/flexspi/flex_spi.c

403

reg = read_reg(sc, FSPI_INTR);

sys/dev/flash/flexspi/flex_spi.c

404

if (reg & FSPI_INTR_IPCMDDONE) {

sys/dev/flash/flexspi/flex_spi.c

629

uint32_t reg;

sys/dev/flash/flexspi/flex_spi.c

638

reg = read_reg(sc, FSPI_MCR0);

sys/dev/flash/flexspi/flex_spi.c

639

reg |= FSPI_MCR0_SWRST;

sys/dev/flash/flexspi/flex_spi.c

640

write_reg(sc, FSPI_MCR0, reg);

sys/dev/flash/flexspi/flex_spi.c

662

reg = read_reg(sc, FSPI_MCR2);

sys/dev/flash/flexspi/flex_spi.c

663

reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);

sys/dev/flash/flexspi/flex_spi.c

664

write_reg(sc, FSPI_MCR2, reg);

sys/dev/flash/flexspi/flex_spi.c

713

uint32_t reg;

sys/dev/flash/flexspi/flex_spi.c

759

reg = read_reg(sc, FSPI_INTR);

sys/dev/flash/flexspi/flex_spi.c

760

if (reg)

sys/dev/flash/flexspi/flex_spi.c

761

write_reg(sc, FSPI_INTR, reg);

sys/dev/flash/w25n.c

113

w25n_read_status_register(struct w25n_softc *sc, uint8_t reg,

sys/dev/flash/w25n.c

123

txBuf[1] = reg;

sys/dev/ftgpio/ftgpio.c

118

ftgpio_group_get_ioreg(struct ftgpio_softc *sc, uint8_t reg, unsigned group)

sys/dev/ftgpio/ftgpio.c

122

KASSERT((group == 0 && REG_OUTPUT_DATA <= reg && reg <= REG_INTERRUPT_STATUS) || \

sys/dev/ftgpio/ftgpio.c

123

(group >= 1 && reg <= REG_DRIVE_ENABLE),

sys/dev/ftgpio/ftgpio.c

124

("%s: invalid register %u for group %u", __func__, reg, group));

sys/dev/ftgpio/ftgpio.c

125

ioreg = (((0xf - group) << 4) + reg);

sys/dev/fxp/if_fxp.c

1111

uint16_t reg;

sys/dev/fxp/if_fxp.c

1119

reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;

sys/dev/fxp/if_fxp.c

1121

reg = FXP_EEPROM_EECS;

sys/dev/fxp/if_fxp.c

1122

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/fxp/if_fxp.c

1124

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);

sys/dev/fxp/if_fxp.c

1126

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/fxp/if_fxp.c

1141

uint16_t reg, data;

sys/dev/fxp/if_fxp.c

1155

reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;

sys/dev/fxp/if_fxp.c

1157

reg = FXP_EEPROM_EECS;

sys/dev/fxp/if_fxp.c

1158

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/fxp/if_fxp.c

1160

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);

sys/dev/fxp/if_fxp.c

1162

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/fxp/if_fxp.c

1164

reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;

sys/dev/fxp/if_fxp.c

1166

if (autosize && reg == 0) {

sys/dev/fxp/if_fxp.c

1175

reg = FXP_EEPROM_EECS;

sys/dev/fxp/if_fxp.c

1177

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);

sys/dev/fxp/if_fxp.c

1181

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/fxp/if_fxp.c

264

static int fxp_miibus_readreg(device_t dev, int phy, int reg);

sys/dev/fxp/if_fxp.c

265

static int fxp_miibus_writereg(device_t dev, int phy, int reg,

sys/dev/fxp/if_fxp.c

2735

fxp_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/fxp/if_fxp.c

2742

(FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));

sys/dev/fxp/if_fxp.c

2755

fxp_miibus_writereg(device_t dev, int phy, int reg, int value)

sys/dev/fxp/if_fxp.c

2761

(FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |

sys/dev/fxp/if_fxpvar.h

244

#define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg)

sys/dev/fxp/if_fxpvar.h

245

#define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg)

sys/dev/fxp/if_fxpvar.h

246

#define CSR_READ_4(sc, reg) bus_read_4(sc->fxp_res[0], reg)

sys/dev/fxp/if_fxpvar.h

247

#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val)

sys/dev/fxp/if_fxpvar.h

248

#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val)

sys/dev/fxp/if_fxpvar.h

249

#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->fxp_res[0], reg, val)

sys/dev/gem/if_gem.c

1832

gem_mii_readreg(device_t dev, int phy, int reg)

sys/dev/gem/if_gem.c

1839

printf("%s: phy %d reg %d\n", __func__, phy, reg);

sys/dev/gem/if_gem.c

1844

switch (reg) {

sys/dev/gem/if_gem.c

1846

reg = GEM_MII_CONTROL;

sys/dev/gem/if_gem.c

1849

reg = GEM_MII_STATUS;

sys/dev/gem/if_gem.c

1855

reg = GEM_MII_ANAR;

sys/dev/gem/if_gem.c

1858

reg = GEM_MII_ANLPAR;

sys/dev/gem/if_gem.c

1864

"%s: unhandled register %d\n", __func__, reg);

sys/dev/gem/if_gem.c

1867

return (GEM_READ_4(sc, reg));

sys/dev/gem/if_gem.c

1873

(reg << GEM_MIF_REG_SHIFT);

sys/dev/gem/if_gem.c

1890

gem_mii_writereg(device_t dev, int phy, int reg, int val)

sys/dev/gem/if_gem.c

1897

printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__);

sys/dev/gem/if_gem.c

1902

switch (reg) {

sys/dev/gem/if_gem.c

1904

reg = GEM_MII_STATUS;

sys/dev/gem/if_gem.c

1907

reg = GEM_MII_CONTROL;

sys/dev/gem/if_gem.c

1935

reg = GEM_MII_ANLPAR;

sys/dev/gem/if_gem.c

1939

"%s: unhandled register %d\n", __func__, reg);

sys/dev/gem/if_gem.c

1942

GEM_WRITE_4(sc, reg, val);

sys/dev/gem/if_gem.c

1943

GEM_BARRIER(sc, reg, 4,

sys/dev/gem/if_gem.c

1951

(reg << GEM_MIF_REG_SHIFT) |

sys/dev/gem/if_gem.c

586

uint32_t reg;

sys/dev/gem/if_gem.c

589

reg = GEM_READ_4(sc, r);

sys/dev/gem/if_gem.c

590

if ((reg & clr) == 0 && (reg & set) == set)

sys/dev/gem/if_gemvar.h

258

int gem_mii_readreg(device_t dev, int phy, int reg);

sys/dev/gem/if_gemvar.h

260

int gem_mii_writereg(device_t dev, int phy, int reg, int val);

sys/dev/gpio/bytgpio.c

285

#define BYGPIO_PIN_REGISTER(sc, pin, r) ((sc)->sc_pinpad_map[(pin)].reg * 16 + (r))

sys/dev/gpio/bytgpio.c

372

uint32_t reg, val;

sys/dev/gpio/bytgpio.c

384

reg = BYGPIO_PIN_REGISTER(sc, pin, BYTGPIO_PAD_VAL);

sys/dev/gpio/bytgpio.c

385

val = bytgpio_read_4(sc, reg);

sys/dev/gpio/bytgpio.c

403

uint32_t reg, val;

sys/dev/gpio/bytgpio.c

429

reg = BYGPIO_PIN_REGISTER(sc, pin, BYTGPIO_PAD_VAL);

sys/dev/gpio/bytgpio.c

430

val = bytgpio_read_4(sc, reg);

sys/dev/gpio/bytgpio.c

436

bytgpio_write_4(sc, reg, val);

sys/dev/gpio/bytgpio.c

462

uint32_t reg, val;

sys/dev/gpio/bytgpio.c

472

reg = BYGPIO_PIN_REGISTER(sc, pin, BYTGPIO_PAD_VAL);

sys/dev/gpio/bytgpio.c

473

val = bytgpio_read_4(sc, reg);

sys/dev/gpio/bytgpio.c

478

bytgpio_write_4(sc, reg, val);

sys/dev/gpio/bytgpio.c

488

uint32_t reg, val;

sys/dev/gpio/bytgpio.c

502

reg = BYGPIO_PIN_REGISTER(sc, pin, BYTGPIO_PAD_VAL);

sys/dev/gpio/bytgpio.c

506

val = bytgpio_read_4(sc, reg);

sys/dev/gpio/bytgpio.c

520

uint32_t reg, val;

sys/dev/gpio/bytgpio.c

531

reg = BYGPIO_PIN_REGISTER(sc, pin, BYTGPIO_PAD_VAL);

sys/dev/gpio/bytgpio.c

532

val = bytgpio_read_4(sc, reg);

sys/dev/gpio/bytgpio.c

534

bytgpio_write_4(sc, reg, val);

sys/dev/gpio/bytgpio.c

560

uint32_t reg, val;

sys/dev/gpio/bytgpio.c

606

reg = BYGPIO_PIN_REGISTER(sc, pin, BYTGPIO_PCONF0);

sys/dev/gpio/bytgpio.c

607

val = bytgpio_read_4(sc, reg);

sys/dev/gpio/bytgpio.c

62

int reg;

sys/dev/gpio/bytgpio.c

69

#define GPIO_PIN_MAP(r, f) { .reg = (r), .pad_func = (f) }

sys/dev/gpio/chvgpio.c

462

uint32_t reg;

sys/dev/gpio/chvgpio.c

465

reg = bus_read_4(sc->sc_mem_res, CHVGPIO_INTERRUPT_STATUS);

sys/dev/gpio/chvgpio.c

467

if ((reg & (1 << line)) == 0)

sys/dev/gpio/dwgpio/dwgpio.c

294

int reg;

sys/dev/gpio/dwgpio/dwgpio.c

307

reg = READ4(sc, GPIO_SWPORT_DR(sc->port));

sys/dev/gpio/dwgpio/dwgpio.c

308

if (reg & (1 << i))

sys/dev/gpio/dwgpio/dwgpio.c

309

reg &= ~(1 << i);

sys/dev/gpio/dwgpio/dwgpio.c

311

reg |= (1 << i);

sys/dev/gpio/dwgpio/dwgpio.c

312

WRITE4(sc, GPIO_SWPORT_DR(sc->port), reg);

sys/dev/gpio/dwgpio/dwgpio.c

323

int reg;

sys/dev/gpio/dwgpio/dwgpio.c

331

reg = READ4(sc, GPIO_SWPORT_DDR(sc->port));

sys/dev/gpio/dwgpio/dwgpio.c

336

reg |= (1 << pin->gp_pin);

sys/dev/gpio/dwgpio/dwgpio.c

339

reg &= ~(1 << pin->gp_pin);

sys/dev/gpio/dwgpio/dwgpio.c

343

WRITE4(sc, GPIO_SWPORT_DDR(sc->port), reg);

sys/dev/gpio/dwgpio/dwgpio.c

372

int reg;

sys/dev/gpio/dwgpio/dwgpio.c

386

reg = READ4(sc, GPIO_SWPORT_DR(sc->port));

sys/dev/gpio/dwgpio/dwgpio.c

388

reg |= (1 << i);

sys/dev/gpio/dwgpio/dwgpio.c

390

reg &= ~(1 << i);

sys/dev/gpio/dwgpio/dwgpio.c

391

WRITE4(sc, GPIO_SWPORT_DR(sc->port), reg);

sys/dev/gpio/gpiomdio.c

185

gpiomdio_readreg(device_t dev, int phy, int reg)

sys/dev/gpio/gpiomdio.c

191

return (mii_bitbang_readreg(dev, &sc->miibb_ops, phy, reg));

sys/dev/gpio/gpiomdio.c

195

gpiomdio_writereg(device_t dev, int phy, int reg, int val)

sys/dev/gpio/gpiomdio.c

200

mii_bitbang_writereg(dev, &sc->miibb_ops, phy, reg, val);

sys/dev/gpio/qoriq_gpio.c

105

uint32_t reg;

sys/dev/gpio/qoriq_gpio.c

114

reg = bus_read_4(sc->sc_mem, GPIO_GPDIR);

sys/dev/gpio/qoriq_gpio.c

115

reg &= ~(1 << (31 - pin));

sys/dev/gpio/qoriq_gpio.c

116

bus_write_4(sc->sc_mem, GPIO_GPDIR, reg);

sys/dev/gpio/qoriq_gpio.c

119

reg = bus_read_4(sc->sc_mem, GPIO_GPDIR);

sys/dev/gpio/qoriq_gpio.c

120

reg |= (1 << (31 - pin));

sys/dev/gpio/qoriq_gpio.c

121

bus_write_4(sc->sc_mem, GPIO_GPDIR, reg);

sys/dev/gpio/qoriq_gpio.c

122

reg = bus_read_4(sc->sc_mem, GPIO_GPODR);

sys/dev/gpio/qoriq_gpio.c

124

reg |= (1 << (31 - pin));

sys/dev/gpio/qoriq_gpio.c

126

reg &= ~(1 << (31 - pin));

sys/dev/gpio/qoriq_gpio.c

127

bus_write_4(sc->sc_mem, GPIO_GPODR, reg);

sys/dev/gpio/qoriq_gpio.c

277

uint32_t dir, odr, mask, reg;

sys/dev/gpio/qoriq_gpio.c

312

reg = (bus_read_4(sc->sc_mem, GPIO_GPDIR) & ~mask) | dir;

sys/dev/gpio/qoriq_gpio.c

313

bus_write_4(sc->sc_mem, GPIO_GPDIR, reg);

sys/dev/gpio/qoriq_gpio.c

315

reg = (bus_read_4(sc->sc_mem, GPIO_GPODR) & ~mask) | odr;

sys/dev/gpio/qoriq_gpio.c

316

bus_write_4(sc->sc_mem, GPIO_GPODR, reg);

sys/dev/hdmi/dwc_hdmi.c

184

uint8_t reg;

sys/dev/hdmi/dwc_hdmi.c

186

reg = RD1(sc, HDMI_PHY_CONF0);

sys/dev/hdmi/dwc_hdmi.c

187

reg &= ~HDMI_PHY_CONF0_PDZ_MASK;

sys/dev/hdmi/dwc_hdmi.c

188

reg |= (enable << HDMI_PHY_CONF0_PDZ_OFFSET);

sys/dev/hdmi/dwc_hdmi.c

189

WR1(sc, HDMI_PHY_CONF0, reg);

sys/dev/hdmi/dwc_hdmi.c

195

uint8_t reg;

sys/dev/hdmi/dwc_hdmi.c

197

reg = RD1(sc, HDMI_PHY_CONF0);

sys/dev/hdmi/dwc_hdmi.c

198

reg &= ~HDMI_PHY_CONF0_ENTMDS_MASK;

sys/dev/hdmi/dwc_hdmi.c

199

reg |= (enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);

sys/dev/hdmi/dwc_hdmi.c

200

WR1(sc, HDMI_PHY_CONF0, reg);

sys/dev/hdmi/dwc_hdmi.c

206

uint8_t reg;

sys/dev/hdmi/dwc_hdmi.c

208

reg = RD1(sc, HDMI_PHY_CONF0);

sys/dev/hdmi/dwc_hdmi.c

209

reg &= ~HDMI_PHY_CONF0_GEN2_PDDQ_MASK;

sys/dev/hdmi/dwc_hdmi.c

210

reg |= (enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);

sys/dev/hdmi/dwc_hdmi.c

211

WR1(sc, HDMI_PHY_CONF0, reg);

sys/dev/hdmi/dwc_hdmi.c

217

uint8_t reg;

sys/dev/hdmi/dwc_hdmi.c

219

reg = RD1(sc, HDMI_PHY_CONF0);

sys/dev/hdmi/dwc_hdmi.c

220

reg &= ~HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;

sys/dev/hdmi/dwc_hdmi.c

221

reg |= (enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);

sys/dev/hdmi/dwc_hdmi.c

222

WR1(sc, HDMI_PHY_CONF0, reg);

sys/dev/hdmi/dwc_hdmi.c

228

uint8_t reg;

sys/dev/hdmi/dwc_hdmi.c

230

reg = RD1(sc, HDMI_PHY_CONF0);

sys/dev/hdmi/dwc_hdmi.c

231

reg &= ~HDMI_PHY_CONF0_SELDATAENPOL_MASK;

sys/dev/hdmi/dwc_hdmi.c

232

reg |= (enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);

sys/dev/hdmi/dwc_hdmi.c

233

WR1(sc, HDMI_PHY_CONF0, reg);

sys/dev/hdmi/dwc_hdmi.c

239

uint8_t reg;

sys/dev/hdmi/dwc_hdmi.c

241

reg = RD1(sc, HDMI_PHY_CONF0);

sys/dev/hdmi/dwc_hdmi.c

242

reg &= ~HDMI_PHY_CONF0_SELDIPIF_MASK;

sys/dev/hdmi/dwc_hdmi.c

243

reg |= (enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);

sys/dev/hdmi/dwc_hdmi.c

244

WR1(sc, HDMI_PHY_CONF0, reg);

sys/dev/hid/ietp.c

452

static const uint16_t reg = IETP_PATTERN;

sys/dev/hid/ietp.c

455

uint8_t cmd[2] = { reg & 0xff, (reg >> 8) & 0xff };

sys/dev/hid/ietp.c

469

DPRINTF("Read reg 0x%04x with size %zu\n", reg, sizeof(resp));

sys/dev/hid/ietp.c

509

uint16_t buf, reg;

sys/dev/hid/ietp.c

528

reg = pattern >= 0x01 ? IETP_IC_TYPE : IETP_OSM_VERSION;

sys/dev/hid/ietp.c

529

if (ietp_iic_read_reg(dev, reg, sizeof(buf), &buf) != 0) {

sys/dev/hid/ietp.c

655

ietp_iic_read_reg(device_t dev, uint16_t reg, size_t len, void *val)

sys/dev/hid/ietp.c

659

uint8_t cmd[2] = { reg & 0xff, (reg >> 8) & 0xff };

sys/dev/hid/ietp.c

667

DPRINTF("Read reg 0x%04x with size %zu\n", reg, len);

sys/dev/hid/ietp.c

679

ietp_iic_write_reg(device_t dev, uint16_t reg, uint16_t val)

sys/dev/hid/ietp.c

683

uint8_t cmd[4] = { reg & 0xff, (reg >> 8) & 0xff,

sys/dev/hid/ietp.c

690

DPRINTF("Write reg 0x%04x with value 0x%04x\n", reg, val);

sys/dev/hpt27xx/hpt27xx_os_bsd.c

101

pci_cfgregwrite(0, bus, dev, func, reg, v, 1);

sys/dev/hpt27xx/hpt27xx_os_bsd.c

103

void pcicfg_write_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U32 v)

sys/dev/hpt27xx/hpt27xx_os_bsd.c

105

pci_cfgregwrite(0, bus, dev, func, reg, v, 4);

sys/dev/hpt27xx/hpt27xx_os_bsd.c

91

HPT_U8 pcicfg_read_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg)

sys/dev/hpt27xx/hpt27xx_os_bsd.c

93

return (HPT_U8)pci_cfgregread(0, bus, dev, func, reg, 1);

sys/dev/hpt27xx/hpt27xx_os_bsd.c

95

HPT_U32 pcicfg_read_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg)

sys/dev/hpt27xx/hpt27xx_os_bsd.c

97

return (HPT_U32)pci_cfgregread(0, bus, dev, func, reg, 4);

sys/dev/hpt27xx/hpt27xx_os_bsd.c

99

void pcicfg_write_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U8 v)

sys/dev/hpt27xx/osm.h

158

HPT_U8 pcicfg_read_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg);

sys/dev/hpt27xx/osm.h

159

HPT_U32 pcicfg_read_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg);

sys/dev/hpt27xx/osm.h

160

void pcicfg_write_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U8 v);

sys/dev/hpt27xx/osm.h

161

void pcicfg_write_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U32 v);

sys/dev/hptnr/hptnr_os_bsd.c

89

HPT_U32 pcicfg_read_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg)

sys/dev/hptnr/hptnr_os_bsd.c

91

return (HPT_U32)pci_cfgregread(0, bus, dev, func, reg, 4);

sys/dev/hptnr/osm.h

156

HPT_U8 pcicfg_read_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg);

sys/dev/hptnr/osm.h

157

HPT_U32 pcicfg_read_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg);

sys/dev/hptnr/osm.h

158

void pcicfg_write_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U8 v);

sys/dev/hptnr/osm.h

159

void pcicfg_write_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U32 v);

sys/dev/hptrr/osm.h

126

#define pcicfg_read_dword(bus, dev, fn, reg) 0xffff

sys/dev/hwpmc/hwpmc_arm64.c

106

uint32_t reg;

sys/dev/hwpmc/hwpmc_arm64.c

108

reg = (1 << pmc);

sys/dev/hwpmc/hwpmc_arm64.c

109

WRITE_SPECIALREG(pmcntenclr_el0, reg);

sys/dev/hwpmc/hwpmc_arm64.c

120

uint32_t reg;

sys/dev/hwpmc/hwpmc_arm64.c

122

reg = READ_SPECIALREG(pmcr_el0);

sys/dev/hwpmc/hwpmc_arm64.c

124

return (reg);

sys/dev/hwpmc/hwpmc_arm64.c

128

arm64_pmcr_write(uint64_t reg)

sys/dev/hwpmc/hwpmc_arm64.c

131

WRITE_SPECIALREG(pmcr_el0, reg);

sys/dev/hwpmc/hwpmc_arm64.c

153

arm64_pmcn_write(unsigned int pmc, uint64_t reg)

sys/dev/hwpmc/hwpmc_arm64.c

159

WRITE_SPECIALREG(pmxevcntr_el0, reg);

sys/dev/hwpmc/hwpmc_arm64.c

230

int reg;

sys/dev/hwpmc/hwpmc_arm64.c

242

reg = (1 << ri);

sys/dev/hwpmc/hwpmc_arm64.c

243

if ((READ_SPECIALREG(pmovsclr_el0) & reg) != 0) {

sys/dev/hwpmc/hwpmc_arm64.c

245

WRITE_SPECIALREG(pmovsclr_el0, reg);

sys/dev/hwpmc/hwpmc_arm64.c

384

int reg, cpu;

sys/dev/hwpmc/hwpmc_arm64.c

400

reg = (1 << ri);

sys/dev/hwpmc/hwpmc_arm64.c

401

if ((READ_SPECIALREG(pmovsclr_el0) & reg) == 0)

sys/dev/hwpmc/hwpmc_arm64.c

404

WRITE_SPECIALREG(pmovsclr_el0, reg);

sys/dev/hwpmc/hwpmc_arm64.c

64

uint32_t reg;

sys/dev/hwpmc/hwpmc_arm64.c

66

reg = (1 << pmc);

sys/dev/hwpmc/hwpmc_arm64.c

67

WRITE_SPECIALREG(pmintenset_el1, reg);

sys/dev/hwpmc/hwpmc_arm64.c

78

uint32_t reg;

sys/dev/hwpmc/hwpmc_arm64.c

80

reg = (1 << pmc);

sys/dev/hwpmc/hwpmc_arm64.c

81

WRITE_SPECIALREG(pmintenclr_el1, reg);

sys/dev/hwpmc/hwpmc_arm64.c

92

uint32_t reg;

sys/dev/hwpmc/hwpmc_arm64.c

94

reg = (1 << pmc);

sys/dev/hwpmc/hwpmc_arm64.c

95

WRITE_SPECIALREG(pmcntenset_el0, reg);

sys/dev/hwpmc/hwpmc_armv7.c

101

reg = (1 << pmc);

sys/dev/hwpmc/hwpmc_armv7.c

102

cp15_pmcnten_clr(reg);

sys/dev/hwpmc/hwpmc_armv7.c

123

armv7_pmcn_write(unsigned int pmc, uint32_t reg)

sys/dev/hwpmc/hwpmc_armv7.c

129

cp15_pmxevcntr_set(reg);

sys/dev/hwpmc/hwpmc_armv7.c

131

return (reg);

sys/dev/hwpmc/hwpmc_armv7.c

164

u_int reg;

sys/dev/hwpmc/hwpmc_armv7.c

176

reg = (1u << 31);

sys/dev/hwpmc/hwpmc_armv7.c

178

reg = (1u << ri);

sys/dev/hwpmc/hwpmc_armv7.c

180

if ((cp15_pmovsr_get() & reg) != 0) {

sys/dev/hwpmc/hwpmc_armv7.c

182

cp15_pmovsr_set(reg);

sys/dev/hwpmc/hwpmc_armv7.c

320

int reg, cpu;

sys/dev/hwpmc/hwpmc_armv7.c

335

reg = (1u << 31);

sys/dev/hwpmc/hwpmc_armv7.c

337

reg = (1u << ri);

sys/dev/hwpmc/hwpmc_armv7.c

339

if ((cp15_pmovsr_get() & reg) == 0) {

sys/dev/hwpmc/hwpmc_armv7.c

344

cp15_pmovsr_set(reg);

sys/dev/hwpmc/hwpmc_armv7.c

474

int reg;

sys/dev/hwpmc/hwpmc_armv7.c

476

reg = cp15_pmcr_get();

sys/dev/hwpmc/hwpmc_armv7.c

477

armv7_npmcs = (reg >> ARMV7_PMNC_N_SHIFT) & \

sys/dev/hwpmc/hwpmc_armv7.c

479

idcode = (reg & ARMV7_IDCODE_MASK) >> ARMV7_IDCODE_SHIFT;

sys/dev/hwpmc/hwpmc_armv7.c

63

uint32_t reg;

sys/dev/hwpmc/hwpmc_armv7.c

65

reg = (1 << pmc);

sys/dev/hwpmc/hwpmc_armv7.c

66

cp15_pminten_set(reg);

sys/dev/hwpmc/hwpmc_armv7.c

75

uint32_t reg;

sys/dev/hwpmc/hwpmc_armv7.c

77

reg = (1 << pmc);

sys/dev/hwpmc/hwpmc_armv7.c

78

cp15_pminten_clr(reg);

sys/dev/hwpmc/hwpmc_armv7.c

87

uint32_t reg;

sys/dev/hwpmc/hwpmc_armv7.c

89

reg = (1 << pmc);

sys/dev/hwpmc/hwpmc_armv7.c

90

cp15_pmcnten_set(reg);

sys/dev/hwpmc/hwpmc_armv7.c

99

uint32_t reg;

sys/dev/hwpmc/pmu_dmc620.c

79

pmu_dmc620_rd4(void *arg, u_int cntr, off_t reg)

sys/dev/hwpmc/pmu_dmc620.c

87

val = RD4(sc, DMC620_REG(cntr, reg));

sys/dev/hwpmc/pmu_dmc620.c

92

pmu_dmc620_wr4(void *arg, u_int cntr, off_t reg, uint32_t val)

sys/dev/hwpmc/pmu_dmc620.c

99

WR4(sc, DMC620_REG(cntr, reg), val);

sys/dev/hwpmc/pmu_dmc620_reg.h

76

uint32_t pmu_dmc620_rd4(void *arg, u_int cntr, off_t reg);

sys/dev/hwpmc/pmu_dmc620_reg.h

77

void pmu_dmc620_wr4(void *arg, u_int cntr, off_t reg, uint32_t val);

sys/dev/hyperv/pcib/vmbus_pcib.c

1772

u_int reg, int bytes)

sys/dev/hyperv/pcib/vmbus_pcib.c

1785

_hv_pcifront_read_config(hpdev, reg, bytes, &data);

sys/dev/hyperv/pcib/vmbus_pcib.c

1792

u_int reg, uint32_t data, int bytes)

sys/dev/hyperv/pcib/vmbus_pcib.c

1804

_hv_pcifront_write_config(hpdev, reg, bytes, data);

sys/dev/iavf/iavf_adminq.c

286

u32 reg = 0;

sys/dev/iavf/iavf_adminq.c

299

reg = rd32(hw, hw->aq.asq.bal);

sys/dev/iavf/iavf_adminq.c

300

if (reg != IAVF_LO_DWORD(hw->aq.asq.desc_buf.pa))

sys/dev/iavf/iavf_adminq.c

315

u32 reg = 0;

sys/dev/iavf/iavf_adminq.c

331

reg = rd32(hw, hw->aq.arq.bal);

sys/dev/iavf/iavf_adminq.c

332

if (reg != IAVF_LO_DWORD(hw->aq.arq.desc_buf.pa))

sys/dev/iavf/iavf_lib.c

201

u32 reg;

sys/dev/iavf/iavf_lib.c

205

reg = rd32(hw, IAVF_VFGEN_RSTAT) &

sys/dev/iavf/iavf_lib.c

208

if ((reg == VIRTCHNL_VFR_VFACTIVE) ||

sys/dev/iavf/iavf_lib.c

209

(reg == VIRTCHNL_VFR_COMPLETED))

sys/dev/iavf/iavf_osdep.c

293

iavf_read_pci_cfg(struct iavf_hw *hw, u32 reg)

sys/dev/iavf/iavf_osdep.c

298

reg, 2);

sys/dev/iavf/iavf_osdep.c

313

iavf_write_pci_cfg(struct iavf_hw *hw, u32 reg, u16 value)

sys/dev/iavf/iavf_osdep.c

316

reg, value, 2);

sys/dev/iavf/iavf_osdep.c

331

iavf_rd32(struct iavf_hw *hw, uint32_t reg)

sys/dev/iavf/iavf_osdep.c

335

KASSERT(reg < osdep->mem_bus_space_size,

sys/dev/iavf/iavf_osdep.c

337

(uintmax_t)reg, (uintmax_t)osdep->mem_bus_space_size));

sys/dev/iavf/iavf_osdep.c

340

osdep->mem_bus_space_handle, reg));

sys/dev/iavf/iavf_osdep.c

352

iavf_wr32(struct iavf_hw *hw, uint32_t reg, uint32_t val)

sys/dev/iavf/iavf_osdep.c

356

KASSERT(reg < osdep->mem_bus_space_size,

sys/dev/iavf/iavf_osdep.c

358

(uintmax_t)reg, (uintmax_t)osdep->mem_bus_space_size));

sys/dev/iavf/iavf_osdep.c

361

osdep->mem_bus_space_handle, reg, val);

sys/dev/iavf/iavf_osdep.h

243

uint32_t iavf_rd32(struct iavf_hw *hw, uint32_t reg);

sys/dev/iavf/iavf_osdep.h

244

void iavf_wr32(struct iavf_hw *hw, uint32_t reg, uint32_t val);

sys/dev/iavf/iavf_osdep.h

246

#define rd32(hw, reg) iavf_rd32(hw, reg)

sys/dev/iavf/iavf_osdep.h

247

#define wr32(hw, reg, val) iavf_wr32(hw, reg, val)

sys/dev/iavf/if_iavf_iflib.c

1130

u32 reg, oldreg;

sys/dev/iavf/if_iavf_iflib.c

1133

oldreg = reg = rd32(hw, hw->aq.arq.len);

sys/dev/iavf/if_iavf_iflib.c

1136

if (reg == 0xdeadbeef || reg == 0xffffffff) {

sys/dev/iavf/if_iavf_iflib.c

1142

if (reg & IAVF_VF_ARQLEN1_ARQVFE_MASK) {

sys/dev/iavf/if_iavf_iflib.c

1144

reg &= ~IAVF_VF_ARQLEN1_ARQVFE_MASK;

sys/dev/iavf/if_iavf_iflib.c

1147

if (reg & IAVF_VF_ARQLEN1_ARQOVFL_MASK) {

sys/dev/iavf/if_iavf_iflib.c

1149

reg &= ~IAVF_VF_ARQLEN1_ARQOVFL_MASK;

sys/dev/iavf/if_iavf_iflib.c

1152

if (reg & IAVF_VF_ARQLEN1_ARQCRIT_MASK) {

sys/dev/iavf/if_iavf_iflib.c

1154

reg &= ~IAVF_VF_ARQLEN1_ARQCRIT_MASK;

sys/dev/iavf/if_iavf_iflib.c

1157

if (oldreg != reg)

sys/dev/iavf/if_iavf_iflib.c

1158

wr32(hw, hw->aq.arq.len, reg);

sys/dev/iavf/if_iavf_iflib.c

1160

oldreg = reg = rd32(hw, hw->aq.asq.len);

sys/dev/iavf/if_iavf_iflib.c

1161

if (reg & IAVF_VF_ATQLEN1_ATQVFE_MASK) {

sys/dev/iavf/if_iavf_iflib.c

1163

reg &= ~IAVF_VF_ATQLEN1_ATQVFE_MASK;

sys/dev/iavf/if_iavf_iflib.c

1166

if (reg & IAVF_VF_ATQLEN1_ATQOVFL_MASK) {

sys/dev/iavf/if_iavf_iflib.c

1168

reg &= ~IAVF_VF_ATQLEN1_ATQOVFL_MASK;

sys/dev/iavf/if_iavf_iflib.c

1171

if (reg & IAVF_VF_ATQLEN1_ATQCRIT_MASK) {

sys/dev/iavf/if_iavf_iflib.c

1173

reg &= ~IAVF_VF_ATQLEN1_ATQCRIT_MASK;

sys/dev/iavf/if_iavf_iflib.c

1176

if (oldreg != reg)

sys/dev/iavf/if_iavf_iflib.c

1177

wr32(hw, hw->aq.asq.len, reg);

sys/dev/iavf/if_iavf_iflib.c

1200

u32 reg;

sys/dev/iavf/if_iavf_iflib.c

1236

reg = rd32(hw, IAVF_VFINT_ICR0_ENA1);

sys/dev/iavf/if_iavf_iflib.c

1237

reg |= IAVF_VFINT_ICR0_ENA1_ADMINQ_MASK;

sys/dev/iavf/if_iavf_iflib.c

1238

wr32(hw, IAVF_VFINT_ICR0_ENA1, reg);

sys/dev/iavf/if_iavf_iflib.c

1589

u32 reg, mask;

sys/dev/iavf/if_iavf_iflib.c

1596

reg = rd32(hw, IAVF_VFINT_ICR01);

sys/dev/iavf/if_iavf_iflib.c

1604

if (reg & IAVF_VFINT_ICR01_ADMINQ_MASK) {

sys/dev/iavf/if_iavf_iflib.c

1662

u32 reg;

sys/dev/iavf/if_iavf_iflib.c

1664

reg = IAVF_VFINT_DYN_CTLN1_INTENA_MASK |

sys/dev/iavf/if_iavf_iflib.c

1667

wr32(hw, IAVF_VFINT_DYN_CTLN1(id), reg);

sys/dev/ice/ice_common.c

1225

u32 cnt, reg = 0, grst_timeout, uld_mask, reset_wait_cnt;

sys/dev/ice/ice_common.c

1236

reg = rd32(hw, GLGEN_RSTAT);

sys/dev/ice/ice_common.c

1237

if (!(reg & GLGEN_RSTAT_DEVSTATE_M))

sys/dev/ice/ice_common.c

1261

reg = rd32(hw, GLNVM_ULD) & uld_mask;

sys/dev/ice/ice_common.c

1262

if (reg == uld_mask) {

sys/dev/ice/ice_common.c

1271

reg);

sys/dev/ice/ice_common.c

1287

u32 cnt, reg, reset_wait_cnt, cfg_lock_timeout;

sys/dev/ice/ice_common.c

1304

reg = rd32(hw, PFGEN_CTRL);

sys/dev/ice/ice_common.c

1306

wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));

sys/dev/ice/ice_common.c

1316

reg = rd32(hw, PFGEN_CTRL);

sys/dev/ice/ice_common.c

1317

if (!(reg & PFGEN_CTRL_PFSWR_M))

sys/dev/ice/ice_common.c

5903

ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,

sys/dev/ice/ice_common.c

5906

u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);

sys/dev/ice/ice_common.c

5940

ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,

sys/dev/ice/ice_common.c

5945

new_data = rd32(hw, reg);

sys/dev/ice/ice_common.h

320

ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,

sys/dev/ice/ice_common.h

323

ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,

sys/dev/ice/ice_dcb.c

278

u32 reg;

sys/dev/ice/ice_dcb.c

280

reg = rd32(hw, PRTDCB_GENS);

sys/dev/ice/ice_dcb.c

281

return (u8)((reg & PRTDCB_GENS_DCBX_STATUS_M) >>

sys/dev/ice/ice_ddp_common.c

2411

u32 reg = 0;

sys/dev/ice/ice_ddp_common.c

2528

reg = rd32(hw, GLGEN_RSTAT);

sys/dev/ice/ice_ddp_common.c

2529

if (reg & GLGEN_RSTAT_DEVSTATE_M) {

sys/dev/ice/ice_fwlog.c

309

static int ice_aq_fwlog_register(struct ice_hw *hw, bool reg)

sys/dev/ice/ice_fwlog.c

315

if (reg)

sys/dev/ice/ice_iov.c

484

u32 reg, reg_idx, bit_idx;

sys/dev/ice/ice_iov.c

491

reg = rd32(hw, GLGEN_VFLRSTAT(reg_idx));

sys/dev/ice/ice_iov.c

492

if (reg & BIT(bit_idx))

sys/dev/ice/ice_iov.c

510

u32 reg;

sys/dev/ice/ice_iov.c

513

reg = rd32(hw, VPGEN_VFRTRIG(vf->vf_num));

sys/dev/ice/ice_iov.c

514

reg &= ~VPGEN_VFRTRIG_VFSWR_M;

sys/dev/ice/ice_iov.c

515

wr32(hw, VPGEN_VFRTRIG(vf->vf_num), reg);

sys/dev/ice/ice_iov.c

546

u32 reg;

sys/dev/ice/ice_iov.c

552

reg = rd32(hw, VPGEN_VFRTRIG(vf->vf_num));

sys/dev/ice/ice_iov.c

553

reg |= VPGEN_VFRTRIG_VFSWR_M;

sys/dev/ice/ice_iov.c

554

wr32(hw, VPGEN_VFRTRIG(vf->vf_num), reg);

sys/dev/ice/ice_iov.c

568

reg = rd32(hw, PF_PCI_CIAD);

sys/dev/ice/ice_iov.c

569

if (!(reg & PCIEM_STA_TRANSACTION_PND))

sys/dev/ice/ice_iov.c

589

reg = rd32(hw, VPGEN_VFRSTAT(vf->vf_num));

sys/dev/ice/ice_iov.c

590

if ((reg & VPGEN_VFRSTAT_VFRD_M))

sys/dev/ice/ice_lib.c

1485

u32 reg, val;

sys/dev/ice/ice_lib.c

1488

reg = vsi->rx_qmap[rxq->me];

sys/dev/ice/ice_lib.c

1489

val = rd32(hw, QINT_RQCTL(reg));

sys/dev/ice/ice_lib.c

1491

wr32(hw, QINT_RQCTL(reg), val);

sys/dev/ice/ice_lib.c

1522

u32 reg, val;

sys/dev/ice/ice_lib.c

1525

reg = vsi->tx_qmap[txq->me];

sys/dev/ice/ice_lib.c

1526

val = rd32(hw, QINT_TQCTL(reg));

sys/dev/ice/ice_lib.c

1528

wr32(hw, QINT_TQCTL(reg), val);

sys/dev/ice/ice_lib.c

1836

ice_is_rxq_ready(struct ice_hw *hw, int pf_q, u32 *reg)

sys/dev/ice/ice_lib.c

1850

*reg = qrx_ctrl;

sys/dev/ice/ice_lib.c

75

static int ice_is_rxq_ready(struct ice_hw *hw, int pf_q, u32 *reg);

sys/dev/ice/ice_lib.c

8240

u16 reg;

sys/dev/ice/ice_lib.c

8244

reg = (link_status & PCIEM_LINK_STA_WIDTH) >> 4;

sys/dev/ice/ice_lib.c

8246

switch (reg) {

sys/dev/ice/ice_lib.c

8254

hw->bus.width = (enum ice_pcie_link_width)reg;

sys/dev/ice/ice_lib.c

8261

reg = (link_status & PCIEM_LINK_STA_SPEED) + 0x13;

sys/dev/ice/ice_lib.c

8263

switch (reg) {

sys/dev/ice/ice_lib.c

8269

hw->bus.speed = (enum ice_pcie_bus_speed)reg;

sys/dev/ice/ice_lib.c

8337

u32 reg;

sys/dev/ice/ice_lib.c

8342

reg = rd32(hw, GL_MDET_TX_TCLAN);

sys/dev/ice/ice_lib.c

8343

if (reg & GL_MDET_TX_TCLAN_VALID_M) {

sys/dev/ice/ice_lib.c

8344

u8 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >> GL_MDET_TX_TCLAN_PF_NUM_S;

sys/dev/ice/ice_lib.c

8345

u16 vf_num = (reg & GL_MDET_TX_TCLAN_VF_NUM_M) >> GL_MDET_TX_TCLAN_VF_NUM_S;

sys/dev/ice/ice_lib.c

8346

u8 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >> GL_MDET_TX_TCLAN_MAL_TYPE_S;

sys/dev/ice/ice_lib.c

8347

u16 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >> GL_MDET_TX_TCLAN_QNUM_S;

sys/dev/ice/ice_lib.c

8362

reg = rd32(hw, GL_MDET_TX_PQM);

sys/dev/ice/ice_lib.c

8363

if (reg & GL_MDET_TX_PQM_VALID_M) {

sys/dev/ice/ice_lib.c

8364

u8 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >> GL_MDET_TX_PQM_PF_NUM_S;

sys/dev/ice/ice_lib.c

8365

u16 vf_num = (reg & GL_MDET_TX_PQM_VF_NUM_M) >> GL_MDET_TX_PQM_VF_NUM_S;

sys/dev/ice/ice_lib.c

8366

u8 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >> GL_MDET_TX_PQM_MAL_TYPE_S;

sys/dev/ice/ice_lib.c

8367

u16 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >> GL_MDET_TX_PQM_QNUM_S;

sys/dev/ice/ice_lib.c

8381

reg = rd32(hw, GL_MDET_RX);

sys/dev/ice/ice_lib.c

8382

if (reg & GL_MDET_RX_VALID_M) {

sys/dev/ice/ice_lib.c

8383

u8 pf_num = (reg & GL_MDET_RX_PF_NUM_M) >> GL_MDET_RX_PF_NUM_S;

sys/dev/ice/ice_lib.c

8384

u16 vf_num = (reg & GL_MDET_RX_VF_NUM_M) >> GL_MDET_RX_VF_NUM_S;

sys/dev/ice/ice_lib.c

8385

u8 event = (reg & GL_MDET_RX_MAL_TYPE_M) >> GL_MDET_RX_MAL_TYPE_S;

sys/dev/ice/ice_lib.c

8386

u16 queue = (reg & GL_MDET_RX_QNUM_M) >> GL_MDET_RX_QNUM_S;

sys/dev/ice/ice_lib.c

8404

reg = rd32(hw, PF_MDET_TX_TCLAN);

sys/dev/ice/ice_lib.c

8405

if (reg & PF_MDET_TX_TCLAN_VALID_M) {

sys/dev/ice/ice_lib.c

8411

reg = rd32(hw, PF_MDET_TX_PQM);

sys/dev/ice/ice_lib.c

8412

if (reg & PF_MDET_TX_PQM_VALID_M) {

sys/dev/ice/ice_lib.c

8418

reg = rd32(hw, PF_MDET_RX);

sys/dev/ice/ice_lib.c

8419

if (reg & PF_MDET_RX_VALID_M) {

sys/dev/ice/ice_osdep.c

191

rd32(struct ice_hw *hw, uint32_t reg)

sys/dev/ice/ice_osdep.c

195

return bus_space_read_4(sc->bar0.tag, sc->bar0.handle, reg);

sys/dev/ice/ice_osdep.c

209

rd64(struct ice_hw *hw, uint32_t reg)

sys/dev/ice/ice_osdep.c

215

data = bus_space_read_8(sc->bar0.tag, sc->bar0.handle, reg);

sys/dev/ice/ice_osdep.c

221

data = bus_space_read_4(sc->bar0.tag, sc->bar0.handle, reg);

sys/dev/ice/ice_osdep.c

222

data |= ((uint64_t)bus_space_read_4(sc->bar0.tag, sc->bar0.handle, reg + 4)) << 32;

sys/dev/ice/ice_osdep.c

237

wr32(struct ice_hw *hw, uint32_t reg, uint32_t val)

sys/dev/ice/ice_osdep.c

241

bus_space_write_4(sc->bar0.tag, sc->bar0.handle, reg, val);

sys/dev/ice/ice_osdep.c

256

wr64(struct ice_hw *hw, uint32_t reg, uint64_t val)

sys/dev/ice/ice_osdep.c

261

bus_space_write_8(sc->bar0.tag, sc->bar0.handle, reg, val);

sys/dev/ice/ice_osdep.c

271

bus_space_write_4(sc->bar0.tag, sc->bar0.handle, reg, lo_val);

sys/dev/ice/ice_osdep.c

272

bus_space_write_4(sc->bar0.tag, sc->bar0.handle, reg + 4, hi_val);

sys/dev/ice/ice_osdep.h

85

uint32_t rd32(struct ice_hw *hw, uint32_t reg);

sys/dev/ice/ice_osdep.h

86

uint64_t rd64(struct ice_hw *hw, uint32_t reg);

sys/dev/ice/ice_osdep.h

87

void wr32(struct ice_hw *hw, uint32_t reg, uint32_t val);

sys/dev/ice/ice_osdep.h

88

void wr64(struct ice_hw *hw, uint32_t reg, uint64_t val);

sys/dev/ice/ice_vf_mbx.c

299

u32 reg = rd32(hw, E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT(vf_id));

sys/dev/ice/ice_vf_mbx.c

301

wr32(hw, E830_MBX_VF_DEC_TRIG(vf_id), reg);

sys/dev/ichiic/ig4_iic.c

1164

#define REGDUMP(sc, reg) \

sys/dev/ichiic/ig4_iic.c

1165

device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg))

sys/dev/ichiic/ig4_iic.c

160

reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value)

sys/dev/ichiic/ig4_iic.c

162

bus_write_4(sc->regs_res, reg, value);

sys/dev/ichiic/ig4_iic.c

163

bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE);

sys/dev/ichiic/ig4_iic.c

167

reg_read(ig4iic_softc_t *sc, uint32_t reg)

sys/dev/ichiic/ig4_iic.c

171

bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_READ);

sys/dev/ichiic/ig4_iic.c

172

value = bus_read_4(sc->regs_res, reg);

sys/dev/ichwd/ichwd.h

321

#define PCR_REG_OFF(pid, reg) (((pid) << PCR_PORTID_SHIFT) | (reg))

sys/dev/igc/if_igc.c

1710

u32 dmac, reg = ~IGC_DMACR_DMAC_EN;

sys/dev/igc/if_igc.c

1718

IGC_WRITE_REG(hw, IGC_DMACR, reg);

sys/dev/igc/if_igc.c

1729

reg = IGC_READ_REG(hw, IGC_FCRTC);

sys/dev/igc/if_igc.c

1730

reg &= ~IGC_FCRTC_RTH_COAL_MASK;

sys/dev/igc/if_igc.c

1731

reg |= ((hwm << IGC_FCRTC_RTH_COAL_SHIFT)

sys/dev/igc/if_igc.c

1733

IGC_WRITE_REG(hw, IGC_FCRTC, reg);

sys/dev/igc/if_igc.c

1738

reg = IGC_READ_REG(hw, IGC_DMACR);

sys/dev/igc/if_igc.c

1739

reg &= ~IGC_DMACR_DMACTHR_MASK;

sys/dev/igc/if_igc.c

1740

reg |= ((dmac << IGC_DMACR_DMACTHR_SHIFT)

sys/dev/igc/if_igc.c

1744

reg |= (IGC_DMACR_DMAC_EN | IGC_DMACR_DMAC_LX_MASK);

sys/dev/igc/if_igc.c

1755

reg |= ((sc->dmac * 5) >> 6);

sys/dev/igc/if_igc.c

1757

reg |= (sc->dmac >> 5);

sys/dev/igc/if_igc.c

1759

IGC_WRITE_REG(hw, IGC_DMACR, reg);

sys/dev/igc/if_igc.c

1764

reg = IGC_READ_REG(hw, IGC_DMCTLX);

sys/dev/igc/if_igc.c

1765

reg |= IGC_DMCTLX_DCFLUSH_DIS;

sys/dev/igc/if_igc.c

1774

reg |= 0xA;

sys/dev/igc/if_igc.c

1776

reg |= 0x4;

sys/dev/igc/if_igc.c

1778

IGC_WRITE_REG(hw, IGC_DMCTLX, reg);

sys/dev/igc/if_igc.c

1785

reg = IGC_READ_REG(hw, IGC_PCIEMISC);

sys/dev/igc/if_igc.c

1786

reg &= ~IGC_PCIEMISC_LX_DECISION;

sys/dev/igc/if_igc.c

1787

IGC_WRITE_REG(hw, IGC_PCIEMISC, reg);

sys/dev/igc/if_igc.c

2328

u32 reg;

sys/dev/igc/if_igc.c

2334

reg = IGC_READ_REG(hw, IGC_CTRL);

sys/dev/igc/if_igc.c

2335

reg |= IGC_CTRL_VME;

sys/dev/igc/if_igc.c

2336

IGC_WRITE_REG(hw, IGC_CTRL, reg);

sys/dev/igc/if_igc.c

2338

reg = IGC_READ_REG(hw, IGC_CTRL);

sys/dev/igc/if_igc.c

2339

reg &= ~IGC_CTRL_VME;

sys/dev/igc/if_igc.c

2340

IGC_WRITE_REG(hw, IGC_CTRL, reg);

sys/dev/igc/if_igc.c

2642

u32 reg, usec, rate;

sys/dev/igc/if_igc.c

2649

reg = IGC_READ_REG(hw, IGC_EITR(tque->me));

sys/dev/igc/if_igc.c

2653

reg = IGC_READ_REG(hw, IGC_EITR(rque->msix));

sys/dev/igc/if_igc.c

2656

usec = (reg & IGC_QVECTOR_MASK);

sys/dev/igc/if_igc.c

3081

u32 reg, val, shift;

sys/dev/igc/if_igc.c

3087

reg = IGC_DTXTCPFLGL;

sys/dev/igc/if_igc.c

3091

reg = IGC_DTXTCPFLGL;

sys/dev/igc/if_igc.c

3095

reg = IGC_DTXTCPFLGH;

sys/dev/igc/if_igc.c

3102

val = IGC_READ_REG(&sc->hw, reg);

sys/dev/igc/if_igc.c

3110

IGC_WRITE_REG(&sc->hw, reg, val);

sys/dev/igc/igc_defines.h

1174

#define GG82563_REG(page, reg) \

sys/dev/igc/igc_defines.h

1175

(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))

sys/dev/igc/igc_hw.h

541

s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);

sys/dev/igc/igc_hw.h

542

s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);

sys/dev/igc/igc_hw.h

543

void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);

sys/dev/igc/igc_hw.h

544

void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);

sys/dev/igc/igc_i225.c

863

u32 i, reg;

sys/dev/igc/igc_i225.c

868

reg = IGC_READ_REG(hw, IGC_EECD);

sys/dev/igc/igc_i225.c

869

if (reg & IGC_EECD_FLUDONE_I225) {

sys/dev/igc/igc_nvm.c

198

u32 i, reg = 0;

sys/dev/igc/igc_nvm.c

204

reg = IGC_READ_REG(hw, IGC_EERD);

sys/dev/igc/igc_nvm.c

206

reg = IGC_READ_REG(hw, IGC_EEWR);

sys/dev/igc/igc_nvm.c

208

if (reg & IGC_NVM_RW_REG_DONE)

sys/dev/igc/igc_osdep.h

101

IGC_REGISTER(hw, reg), value)

sys/dev/igc/igc_osdep.h

103

#define IGC_READ_REG_ARRAY(hw, reg, index) \

sys/dev/igc/igc_osdep.h

106

IGC_REGISTER(hw, reg) + ((index)<< 2))

sys/dev/igc/igc_osdep.h

108

#define IGC_WRITE_REG_ARRAY(hw, reg, index, value) \

sys/dev/igc/igc_osdep.h

111

IGC_REGISTER(hw, reg) + ((index)<< 2), value)

sys/dev/igc/igc_osdep.h

116

#define IGC_READ_REG_ARRAY_BYTE(hw, reg, index) \

sys/dev/igc/igc_osdep.h

119

IGC_REGISTER(hw, reg) + index)

sys/dev/igc/igc_osdep.h

121

#define IGC_WRITE_REG_ARRAY_BYTE(hw, reg, index, value) \

sys/dev/igc/igc_osdep.h

124

IGC_REGISTER(hw, reg) + index, value)

sys/dev/igc/igc_osdep.h

126

#define IGC_WRITE_REG_ARRAY_WORD(hw, reg, index, value) \

sys/dev/igc/igc_osdep.h

129

IGC_REGISTER(hw, reg) + (index << 1), value)

sys/dev/igc/igc_osdep.h

77

#define IGC_REGISTER(hw, reg) reg

sys/dev/igc/igc_osdep.h

93

#define IGC_READ_REG(hw, reg) \

sys/dev/igc/igc_osdep.h

96

IGC_REGISTER(hw, reg))

sys/dev/igc/igc_osdep.h

98

#define IGC_WRITE_REG(hw, reg, value) \

sys/dev/iicbus/adc/ad7417.c

125

ad7417_write(device_t dev, uint32_t addr, uint8_t reg, uint8_t *buff, int len)

sys/dev/iicbus/adc/ad7417.c

135

buf[0] = reg;

sys/dev/iicbus/adc/ad7417.c

152

ad7417_read_1(device_t dev, uint32_t addr, uint8_t reg, uint8_t *data)

sys/dev/iicbus/adc/ad7417.c

158

{ addr, IIC_M_WR | IIC_M_NOSTOP, 1, &reg },

sys/dev/iicbus/adc/ad7417.c

180

ad7417_read_2(device_t dev, uint32_t addr, uint8_t reg, uint16_t *data)

sys/dev/iicbus/adc/ad7417.c

186

{ addr, IIC_M_WR | IIC_M_NOSTOP, 1, &reg },

sys/dev/iicbus/adc/ad7417.c

217

{ addr, IIC_M_WR | IIC_M_NOSTOP, 1, &in->reg },

sys/dev/iicbus/adc/ad7417.c

222

buf[0] = out.reg;

sys/dev/iicbus/adc/ad7417.c

504

config.reg = AD7417_CONFIG;

sys/dev/iicbus/adc/ad7417.c

505

data.reg = AD7417_ADC;

sys/dev/iicbus/adc/ad7417.c

73

uint8_t reg;

sys/dev/iicbus/adc/ad7417.c

78

uint8_t reg;

sys/dev/iicbus/adc/ad7417.c

88

static int ad7417_write(device_t dev, uint32_t addr, uint8_t reg,

sys/dev/iicbus/adc/ad7417.c

90

static int ad7417_read_1(device_t dev, uint32_t addr, uint8_t reg,

sys/dev/iicbus/adc/ad7417.c

92

static int ad7417_read_2(device_t dev, uint32_t addr, uint8_t reg,

sys/dev/iicbus/adc/ad7418.c

135

ad7418_read_1(device_t dev, int reg)

sys/dev/iicbus/adc/ad7418.c

137

uint8_t addr = reg;

sys/dev/iicbus/adc/ad7418.c

147

ad7418_write_1(device_t dev, int reg, int v)

sys/dev/iicbus/adc/ad7418.c

154

data[0] = reg;

sys/dev/iicbus/adc/ad7418.c

179

ad7418_read_2(device_t dev, int reg)

sys/dev/iicbus/adc/ad7418.c

181

uint8_t addr = reg;

sys/dev/iicbus/adc/ad7418.c

69

static int ad7418_read_1(device_t dev, int reg);

sys/dev/iicbus/adc/ad7418.c

70

static int ad7418_write_1(device_t dev, int reg, int v);

sys/dev/iicbus/adc/ads111x.c

168

ads111x_write_2(struct ads111x_softc *sc, int reg, int val)

sys/dev/iicbus/adc/ads111x.c

176

data[0] = reg;

sys/dev/iicbus/adc/ads111x.c

188

ads111x_read_2(struct ads111x_softc *sc, int reg, int *val)

sys/dev/iicbus/adc/ads111x.c

193

err = iic2errno(iicdev_readfrom(sc->dev, reg, data, 2, IIC_WAIT));

sys/dev/iicbus/controller/opencores/iicoc.c

51

iicoc_dev_write(device_t dev, int reg, int value)

sys/dev/iicbus/controller/opencores/iicoc.c

56

bus_write_1(sc->mem_res, reg<<sc->reg_shift, value);

sys/dev/iicbus/controller/opencores/iicoc.c

60

iicoc_dev_read(device_t dev, int reg)

sys/dev/iicbus/controller/opencores/iicoc.c

66

val = bus_read_1(sc->mem_res, reg<<sc->reg_shift);

sys/dev/iicbus/controller/qcom/geni_iic.c

125

#define RD(sc, reg) bus_read_4((sc)->regs_res, reg)

sys/dev/iicbus/controller/qcom/geni_iic.c

126

#define WR(sc, reg, val) bus_write_4((sc)->regs_res, reg, val)

sys/dev/iicbus/controller/rockchip/rk_i2c.c

162

#define RK_I2C_READ(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/dev/iicbus/controller/rockchip/rk_i2c.c

163

#define RK_I2C_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/dev/iicbus/controller/rockchip/rk_i2c.c

282

uint32_t reg;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

289

reg = RK_I2C_READ(sc, RK_I2C_CON);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

290

reg |= RK_I2C_CON_STOP;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

291

RK_I2C_WRITE(sc, RK_I2C_CON, reg);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

300

reg = RK_I2C_READ(sc, RK_I2C_CON);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

301

reg &= ~RK_I2C_CON_CTRL_MASK;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

302

RK_I2C_WRITE(sc, RK_I2C_CON, reg);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

309

uint32_t reg;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

334

reg = RK_I2C_READ(sc, RK_I2C_CON);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

335

reg &= ~RK_I2C_CON_START;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

336

RK_I2C_WRITE(sc, RK_I2C_CON, reg);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

348

reg = RK_I2C_READ(sc, RK_I2C_CON);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

349

reg |= RK_I2C_CON_LASTACK;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

350

RK_I2C_WRITE(sc, RK_I2C_CON, reg);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

370

reg = RK_I2C_READ(sc, RK_I2C_CON) & \

sys/dev/iicbus/controller/rockchip/rk_i2c.c

372

reg |= sc->mode << RK_I2C_CON_MODE_SHIFT;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

373

reg |= RK_I2C_CON_EN;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

379

reg |= RK_I2C_CON_LASTACK;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

382

RK_I2C_WRITE(sc, RK_I2C_CON, reg);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

399

reg = RK_I2C_READ(sc, RK_I2C_CON);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

400

reg &= ~RK_I2C_CON_STOP;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

401

RK_I2C_WRITE(sc, RK_I2C_CON, reg);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

429

uint32_t reg;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

439

reg = RK_I2C_READ(sc, RK_I2C_CON) & ~RK_I2C_CON_CTRL_MASK;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

446

reg |= RK_I2C_CON_START;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

454

reg |= RK_I2C_CON_LASTACK;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

469

reg |= RK_I2C_CON_NAKSTOP;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

470

reg |= sc->mode << RK_I2C_CON_MODE_SHIFT;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

471

reg |= RK_I2C_CON_EN;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

472

RK_I2C_WRITE(sc, RK_I2C_CON, reg);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

479

uint32_t reg;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

533

reg = msgs[i].slave & ~LSB;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

534

reg |= RK_I2C_MRXADDR_VALID(0);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

535

RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

538

reg = 0;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

540

reg |= (uint32_t)msgs[i].buf[j] << (j * 8);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

541

reg |= RK_I2C_MRXADDR_VALID(j);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

543

RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, reg);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

552

reg = msgs[i].slave & ~LSB;

sys/dev/iicbus/controller/rockchip/rk_i2c.c

553

reg |= RK_I2C_MRXADDR_VALID(0);

sys/dev/iicbus/controller/rockchip/rk_i2c.c

554

RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg);

sys/dev/iicbus/controller/vybrid/vf_i2c.c

292

int reg;

sys/dev/iicbus/controller/vybrid/vf_i2c.c

306

reg = READ1(sc, I2C_IBCR);

sys/dev/iicbus/controller/vybrid/vf_i2c.c

307

reg |= (IBCR_RSTA | IBCR_IBIE);

sys/dev/iicbus/controller/vybrid/vf_i2c.c

308

WRITE1(sc, I2C_IBCR, reg);

sys/dev/iicbus/controller/vybrid/vf_i2c.c

334

int reg;

sys/dev/iicbus/controller/vybrid/vf_i2c.c

359

reg = (IBCR_MSSL | IBCR_NOACK | IBCR_IBIE | IBCR_TXRX);

sys/dev/iicbus/controller/vybrid/vf_i2c.c

360

WRITE1(sc, I2C_IBCR, reg);

sys/dev/iicbus/gpio/tca64xx.c

164

tca64xx_read(device_t dev, uint8_t reg, uint8_t *data)

sys/dev/iicbus/gpio/tca64xx.c

177

msgs[0].buf = ®

sys/dev/iicbus/gpio/tca64xx.c

189

tca64xx_write(device_t dev, uint8_t reg, uint8_t val)

sys/dev/iicbus/gpio/tca64xx.c

194

uint8_t buffer[2] = {reg, val};

sys/dev/iicbus/gpio/tca64xx.c

622

uint8_t reg, regval;

sys/dev/iicbus/gpio/tca64xx.c

625

reg = (uint8_t)arg2;

sys/dev/iicbus/gpio/tca64xx.c

627

error = tca64xx_read(dev, reg, &regval);

sys/dev/iicbus/iichid.c

1060

int error, reg;

sys/dev/iicbus/iichid.c

1081

reg = acpi_is_iichid(handle);

sys/dev/iicbus/iichid.c

1082

if (reg == IICHID_REG_NONE)

sys/dev/iicbus/iichid.c

1085

if (reg == IICHID_REG_ACPI) {

sys/dev/iicbus/iichid.c

1089

config_reg = (uint16_t)reg;

sys/dev/iicbus/iichid.c

140

int reg;

sys/dev/iicbus/iichid.c

218

int reg;

sys/dev/iicbus/iichid.c

222

reg = ids->reg;

sys/dev/iicbus/iichid.c

235

return (reg);

sys/dev/iicbus/pmic/act8846.c

107

addr = reg;

sys/dev/iicbus/pmic/act8846.c

112

"Error when reading reg 0x%02X, rv: %d\n", reg, rv);

sys/dev/iicbus/pmic/act8846.c

120

act8846_write(struct act8846_softc *sc, uint8_t reg, uint8_t val)

sys/dev/iicbus/pmic/act8846.c

130

data[0] = reg;

sys/dev/iicbus/pmic/act8846.c

136

"Error when writing reg 0x%02X, rv: %d\n", reg, rv);

sys/dev/iicbus/pmic/act8846.c

142

int act8846_write_buf(struct act8846_softc *sc, uint8_t reg, uint8_t *buf,

sys/dev/iicbus/pmic/act8846.c

154

data[0] = reg;

sys/dev/iicbus/pmic/act8846.c

159

"Error when writing reg 0x%02X, rv: %d\n", reg, rv);

sys/dev/iicbus/pmic/act8846.c

166

act8846_modify(struct act8846_softc *sc, uint8_t reg, uint8_t clear, uint8_t set)

sys/dev/iicbus/pmic/act8846.c

171

rv = act8846_read(sc, reg, &val);

sys/dev/iicbus/pmic/act8846.c

178

rv = act8846_write(sc, reg, val);

sys/dev/iicbus/pmic/act8846.c

72

act8846_read(struct act8846_softc *sc, uint8_t reg, uint8_t *val)

sys/dev/iicbus/pmic/act8846.c

83

addr = reg;

sys/dev/iicbus/pmic/act8846.c

88

"Error when reading reg 0x%02X, rv: %d\n", reg, rv);

sys/dev/iicbus/pmic/act8846.c

95

int act8846_read_buf(struct act8846_softc *sc, uint8_t reg, uint8_t *buf,

sys/dev/iicbus/pmic/act8846.h

47

#define RD1(sc, reg, val) act8846_read(sc, reg, val)

sys/dev/iicbus/pmic/act8846.h

48

#define WR1(sc, reg, val) act8846_write(sc, reg, val)

sys/dev/iicbus/pmic/act8846.h

49

#define RM1(sc, reg, clr, set) act8846_modify(sc, reg, clr, set)

sys/dev/iicbus/pmic/act8846.h

51

int act8846_read(struct act8846_softc *sc, uint8_t reg, uint8_t *val);

sys/dev/iicbus/pmic/act8846.h

52

int act8846_write(struct act8846_softc *sc, uint8_t reg, uint8_t val);

sys/dev/iicbus/pmic/act8846.h

53

int act8846_modify(struct act8846_softc *sc, uint8_t reg, uint8_t clear,

sys/dev/iicbus/pmic/act8846.h

55

int act8846_read_buf(struct act8846_softc *sc, uint8_t reg, uint8_t *buf,

sys/dev/iicbus/pmic/act8846.h

57

int act8846_write_buf(struct act8846_softc *sc, uint8_t reg, uint8_t *buf,

sys/dev/iicbus/pmic/act8846_regulator.c

449

struct act8846_reg_sc *reg;

sys/dev/iicbus/pmic/act8846_regulator.c

475

reg = act8846_attach(sc, node, child, act8846_regdefs + i);

sys/dev/iicbus/pmic/act8846_regulator.c

476

if (reg == NULL) {

sys/dev/iicbus/pmic/act8846_regulator.c

481

sc->regs[i] = reg;

sys/dev/iicbus/pmic/fan53555.c

119

fan53555_read(device_t dev, uint8_t reg, uint8_t *val)

sys/dev/iicbus/pmic/fan53555.c

130

addr = reg;

sys/dev/iicbus/pmic/fan53555.c

135

reg, rv);

sys/dev/iicbus/pmic/fan53555.c

143

fan53555_write(device_t dev, uint8_t reg, uint8_t val)

sys/dev/iicbus/pmic/fan53555.c

153

data[0] = reg;

sys/dev/iicbus/pmic/fan53555.c

159

"Error when writing reg 0x%02X, rv: %d\n", reg, rv);

sys/dev/iicbus/pmic/fan53555.c

181

uint8_t reg;

sys/dev/iicbus/pmic/fan53555.c

183

rv = fan53555_read(sc->base_dev, sc->live_reg, &reg);

sys/dev/iicbus/pmic/fan53555.c

186

reg &= ~FAN53555_VSEL_MASK;

sys/dev/iicbus/pmic/fan53555.c

187

reg |= sel;

sys/dev/iicbus/pmic/fan53555.c

189

rv = fan53555_write(sc->base_dev, sc->live_reg, reg);

sys/dev/iicbus/pmic/rockchip/rk8xx.c

55

rk8xx_read(device_t dev, uint8_t reg, uint8_t *data, uint8_t size)

sys/dev/iicbus/pmic/rockchip/rk8xx.c

59

err = iicdev_readfrom(dev, reg, data, size, IIC_INTRWAIT);

sys/dev/iicbus/pmic/rockchip/rk8xx.c

64

rk8xx_write(device_t dev, uint8_t reg, uint8_t *data, uint8_t size)

sys/dev/iicbus/pmic/rockchip/rk8xx.c

67

return (iicdev_writeto(dev, reg, data, size, IIC_INTRWAIT));

sys/dev/iicbus/pmic/rockchip/rk8xx.h

115

int rk8xx_read(device_t dev, uint8_t reg, uint8_t *data, uint8_t size);

sys/dev/iicbus/pmic/rockchip/rk8xx.h

116

int rk8xx_write(device_t dev, uint8_t reg, uint8_t *data, uint8_t size);

sys/dev/iicbus/pmic/rockchip/rk8xx.h

69

struct rk8xx_reg_sc *reg;

sys/dev/iicbus/pmic/rockchip/rk8xx_regulators.c

317

struct rk8xx_reg_sc *reg;

sys/dev/iicbus/pmic/rockchip/rk8xx_regulators.c

333

reg = rk8xx_reg_attach(sc->dev, child, &sc->regdefs[i]);

sys/dev/iicbus/pmic/rockchip/rk8xx_regulators.c

334

if (reg == NULL) {

sys/dev/iicbus/pmic/rockchip/rk8xx_regulators.c

341

regp->reg = reg;

sys/dev/iicbus/pmic/rockchip/rk8xx_regulators.c

360

if (regp->reg->xref == xref) {

sys/dev/iicbus/pmic/rockchip/rk8xx_regulators.c

361

*id = regp->reg->def->id;

sys/dev/iicbus/pmic/silergy/sy8106a.c

107

buffer[0] = reg;

sys/dev/iicbus/pmic/silergy/sy8106a.c

232

if (sc->reg->xref != xref)

sys/dev/iicbus/pmic/silergy/sy8106a.c

265

sc->reg = sy8106a_reg_attach(dev, node);

sys/dev/iicbus/pmic/silergy/sy8106a.c

266

if (sc->reg == NULL) {

sys/dev/iicbus/pmic/silergy/sy8106a.c

74

struct sy8106a_reg_sc *reg;

sys/dev/iicbus/pmic/silergy/sy8106a.c

78

sy8106a_read(device_t dev, uint8_t reg, uint8_t *data, uint8_t size)

sys/dev/iicbus/pmic/silergy/sy8106a.c

88

msg[0].buf = ®

sys/dev/iicbus/pmic/silergy/sy8106a.c

99

sy8106a_write(device_t dev, uint8_t reg, uint8_t val)

sys/dev/iicbus/pmic/silergy/syr827.c

230

if (sc->reg->xref != xref)

sys/dev/iicbus/pmic/silergy/syr827.c

291

sc->reg = syr827_reg_attach(dev, node);

sys/dev/iicbus/pmic/silergy/syr827.c

292

if (sc->reg == NULL) {

sys/dev/iicbus/pmic/silergy/syr827.c

84

struct syr827_reg_sc *reg;

sys/dev/iicbus/pmic/silergy/syr827.c

88

syr827_read(device_t dev, uint8_t reg, uint8_t *data, uint8_t size)

sys/dev/iicbus/pmic/silergy/syr827.c

90

return (iicdev_readfrom(dev, reg, data, size, IIC_INTRWAIT));

sys/dev/iicbus/pmic/silergy/syr827.c

94

syr827_write(device_t dev, uint8_t reg, uint8_t val)

sys/dev/iicbus/pmic/silergy/syr827.c

96

return (iicdev_writeto(dev, reg, &val, 1, IIC_INTRWAIT));

sys/dev/iicbus/pwm/adm1030.c

68

static int adm1030_write_byte(device_t dev, uint32_t addr, uint8_t reg, uint8_t buf);

sys/dev/iicbus/pwm/adm1030.c

88

adm1030_write_byte(device_t dev, uint32_t addr, uint8_t reg, uint8_t byte)

sys/dev/iicbus/pwm/adm1030.c

98

buf[0] = reg;

sys/dev/iicbus/pwm/adt746x.c

125

static int adt746x_write(device_t dev, uint32_t addr, uint8_t reg,

sys/dev/iicbus/pwm/adt746x.c

127

static int adt746x_read(device_t dev, uint32_t addr, uint8_t reg,

sys/dev/iicbus/pwm/adt746x.c

150

adt746x_write(device_t dev, uint32_t addr, uint8_t reg, uint8_t *buff)

sys/dev/iicbus/pwm/adt746x.c

160

buf[0] = reg;

sys/dev/iicbus/pwm/adt746x.c

177

adt746x_read(device_t dev, uint32_t addr, uint8_t reg, uint8_t *data)

sys/dev/iicbus/pwm/adt746x.c

183

{addr, IIC_M_WR | IIC_M_NOSTOP, 1, &reg},

sys/dev/iicbus/pwm/adt746x.c

296

uint8_t reg = 0, manual, mode = 0;

sys/dev/iicbus/pwm/adt746x.c

306

reg = fan->pwm_reg;

sys/dev/iicbus/pwm/adt746x.c

322

adt746x_write(sc->sc_dev, sc->sc_addr, reg, &buf);

sys/dev/iicbus/pwm/adt746x.c

330

uint8_t buf, reg;

sys/dev/iicbus/pwm/adt746x.c

336

reg = fan->pwm_reg;

sys/dev/iicbus/pwm/adt746x.c

338

adt746x_read(sc->sc_dev, sc->sc_addr, reg, &buf);

sys/dev/iicbus/pwm/adt746x.c

402

int i = 0, reg, sensid;

sys/dev/iicbus/pwm/adt746x.c

420

OF_getprop(node, "reg", &reg, sizeof(reg));

sys/dev/iicbus/pwm/adt746x.c

424

sc->sc_sensors[i].reg = reg;

sys/dev/iicbus/pwm/adt746x.c

544

if (adt746x_read(sc->sc_dev, sc->sc_addr, sens->reg,

sys/dev/iicbus/pwm/adt746x.c

552

if (adt746x_read(sc->sc_dev, sc->sc_addr, sens->reg,

sys/dev/iicbus/pwm/adt746x.c

555

if (adt746x_read(sc->sc_dev, sc->sc_addr, sens->reg + 1,

sys/dev/iicbus/pwm/adt746x.c

654

sc->sc_sensors[i].reg);

sys/dev/iicbus/pwm/adt746x.c

85

cell_t reg;

sys/dev/iicbus/rtc/ds1307.c

85

ds1307_read1(device_t dev, uint8_t reg, uint8_t *data)

sys/dev/iicbus/rtc/ds1307.c

88

return (iicdev_readfrom(dev, reg, data, 1, IIC_INTRWAIT));

sys/dev/iicbus/rtc/ds1307.c

92

ds1307_write1(device_t dev, uint8_t reg, uint8_t data)

sys/dev/iicbus/rtc/ds1307.c

95

return (iicdev_writeto(dev, reg, &data, 1, IIC_INTRWAIT));

sys/dev/iicbus/rtc/ds13rtc.c

204

read_reg(struct ds13rtc_softc *sc, uint8_t reg, uint8_t *val)

sys/dev/iicbus/rtc/ds13rtc.c

207

return (iicdev_readfrom(sc->dev, reg, val, sizeof(*val), IIC_WAIT));

sys/dev/iicbus/rtc/ds13rtc.c

211

write_reg(struct ds13rtc_softc *sc, uint8_t reg, uint8_t val)

sys/dev/iicbus/rtc/ds13rtc.c

214

return (iicdev_writeto(sc->dev, reg, &val, sizeof(val), IIC_WAIT));

sys/dev/iicbus/rtc/ds3231.c

69

ds3231_read1(device_t dev, uint8_t reg, uint8_t *data)

sys/dev/iicbus/rtc/ds3231.c

72

return (iicdev_readfrom(dev, reg, data, 1, IIC_INTRWAIT));

sys/dev/iicbus/rtc/ds3231.c

76

ds3231_write1(device_t dev, uint8_t reg, uint8_t data)

sys/dev/iicbus/rtc/ds3231.c

79

return (iicdev_writeto(dev, reg, &data, 1, IIC_INTRWAIT));

sys/dev/iicbus/rtc/hym8563.c

107

hym8563_read_buf(device_t dev, uint8_t reg, uint8_t *buf, uint16_t buflen)

sys/dev/iicbus/rtc/hym8563.c

110

return (iicdev_readfrom(dev, reg, buf, buflen, IIC_WAIT));

sys/dev/iicbus/rtc/hym8563.c

114

hym8563_write_buf(device_t dev, uint8_t reg, uint8_t *buf, uint16_t buflen)

sys/dev/iicbus/rtc/hym8563.c

117

return (iicdev_writeto(dev, reg, buf, buflen, IIC_WAIT));

sys/dev/iicbus/rtc/hym8563.c

121

hym8563_read_1(device_t dev, uint8_t reg, uint8_t *data)

sys/dev/iicbus/rtc/hym8563.c

124

return (iicdev_readfrom(dev, reg, data, 1, IIC_WAIT));

sys/dev/iicbus/rtc/hym8563.c

128

hym8563_write_1(device_t dev, uint8_t reg, uint8_t val)

sys/dev/iicbus/rtc/hym8563.c

131

return (iicdev_writeto(dev, reg, &val, 1, IIC_WAIT));

sys/dev/iicbus/rtc/hym8563.c

393

uint8_t reg;

sys/dev/iicbus/rtc/hym8563.c

407

rv = hym8563_read_1(sc->dev, HYM8563_CTRL2, &reg);

sys/dev/iicbus/rtc/isl12xx.c

150

isl12xx_read1(struct isl12xx_softc *sc, uint8_t reg, uint8_t *data)

sys/dev/iicbus/rtc/isl12xx.c

153

return (iicdev_readfrom(sc->dev, reg, data, 1, WAITFLAGS));

sys/dev/iicbus/rtc/isl12xx.c

157

isl12xx_write1(struct isl12xx_softc *sc, uint8_t reg, uint8_t val)

sys/dev/iicbus/rtc/isl12xx.c

160

return (iicdev_writeto(sc->dev, reg, &val, 1, WAITFLAGS));

sys/dev/iicbus/rtc/nxprtc.c

291

read_reg(struct nxprtc_softc *sc, uint8_t reg, uint8_t *val)

sys/dev/iicbus/rtc/nxprtc.c

294

return (nxprtc_readfrom(sc->dev, reg, val, sizeof(*val), WAITFLAGS));

sys/dev/iicbus/rtc/nxprtc.c

298

write_reg(struct nxprtc_softc *sc, uint8_t reg, uint8_t val)

sys/dev/iicbus/rtc/nxprtc.c

301

return (iicdev_writeto(sc->dev, reg, &val, sizeof(val), WAITFLAGS));

sys/dev/iicbus/rtc/rtc8583.c

115

rtc8583_read1(struct rtc8583_softc *sc, uint8_t reg, uint8_t *data)

sys/dev/iicbus/rtc/rtc8583.c

118

return (iicdev_readfrom(sc->dev, reg, data, 1, IIC_WAIT));

sys/dev/iicbus/rtc/rtc8583.c

122

rtc8583_write1(struct rtc8583_softc *sc, uint8_t reg, uint8_t val)

sys/dev/iicbus/rtc/rtc8583.c

125

return (rtc8583_writeto(sc->dev, reg, &val, 1, IIC_WAIT));

sys/dev/iicbus/rtc/rv3032.c

174

rv3032_update_register(struct rv3032_softc *sc, uint8_t reg, uint8_t value, uint8_t mask)

sys/dev/iicbus/rtc/rv3032.c

179

if ((rv = iicdev_readfrom(sc->dev, reg, &data, 1, IIC_WAIT)) != 0)

sys/dev/iicbus/rtc/rv3032.c

183

if ((rv = iicdev_writeto(sc->dev, reg, &data, 1, IIC_WAIT)) != 0)

sys/dev/iicbus/rtc/rx8803.c

142

uint8_t reg;

sys/dev/iicbus/rtc/rx8803.c

161

rc = iicdev_readfrom(dev, RX8803_CTRL, &reg, sizeof(uint8_t), IIC_WAIT);

sys/dev/iicbus/rtc/rx8803.c

165

reg |= RX8803_CTRL_DISABLE;

sys/dev/iicbus/rtc/rx8803.c

167

rc = iicdev_writeto(dev, RX8803_CTRL, &reg, sizeof(uint8_t), IIC_WAIT);

sys/dev/iicbus/rtc/rx8803.c

180

reg &= ~RX8803_CTRL_DISABLE;

sys/dev/iicbus/rtc/rx8803.c

181

rc = iicdev_writeto(dev, RX8803_CTRL, &reg, sizeof(uint8_t), IIC_WAIT);

sys/dev/iicbus/rtc/rx8803.c

186

rc = iicdev_readfrom(dev, RX8803_FLAGS, &reg, sizeof(uint8_t), IIC_WAIT);

sys/dev/iicbus/rtc/rx8803.c

190

reg &= ~(RX8803_FLAGS_V1F | RX8803_FLAGS_V2F);

sys/dev/iicbus/rtc/rx8803.c

191

rc = iicdev_writeto(dev, RX8803_FLAGS, &reg, sizeof(uint8_t), IIC_WAIT);

sys/dev/iicbus/rtc/s35390a.c

156

s390rtc_read(device_t dev, uint8_t reg, uint8_t *buf, size_t len)

sys/dev/iicbus/rtc/s35390a.c

161

.slave = sc->sc_addr | reg,

sys/dev/iicbus/rtc/s35390a.c

182

s390rtc_write(device_t dev, uint8_t reg, uint8_t *buf, size_t len)

sys/dev/iicbus/rtc/s35390a.c

187

.slave = sc->sc_addr | reg,

sys/dev/iicbus/rtc/s35390a.c

230

uint8_t reg;

sys/dev/iicbus/rtc/s35390a.c

236

error = s390rtc_read(dev, S390_STATUS1, &reg, 1);

sys/dev/iicbus/rtc/s35390a.c

242

if (reg & (S390_ST1_POC | S390_ST1_BLD)) {

sys/dev/iicbus/rtc/s35390a.c

243

reg |= S390_ST1_24H | S390_ST1_RESET;

sys/dev/iicbus/rtc/s35390a.c

244

error = s390rtc_write(dev, S390_STATUS1, &reg, 1);

sys/dev/iicbus/rtc/s35390a.c

253

error = s390rtc_read(dev, S390_STATUS2, &reg, 1);

sys/dev/iicbus/rtc/s35390a.c

259

if (reg & S390_ST2_TEST) {

sys/dev/iicbus/rtc/s35390a.c

260

reg &= ~S390_ST2_TEST;

sys/dev/iicbus/rtc/s35390a.c

261

error = s390rtc_write(dev, S390_STATUS2, &reg, 1);

sys/dev/iicbus/sensor/ds1631.c

116

ds1631_write(device_t dev, uint32_t addr, uint8_t reg, uint8_t *buff, int len)

sys/dev/iicbus/sensor/ds1631.c

127

buf[0] = reg;

sys/dev/iicbus/sensor/ds1631.c

143

ds1631_read_1(device_t dev, uint32_t addr, uint8_t reg, uint8_t *data)

sys/dev/iicbus/sensor/ds1631.c

149

{ addr, IIC_M_WR, 1, &reg },

sys/dev/iicbus/sensor/ds1631.c

171

ds1631_read_2(device_t dev, uint32_t addr, uint8_t reg, uint16_t *data)

sys/dev/iicbus/sensor/ds1631.c

177

{ addr, IIC_M_WR, 1, &reg },

sys/dev/iicbus/sensor/ds1631.c

80

uint8_t reg;

sys/dev/iicbus/sensor/ds1631.c

85

uint8_t reg;

sys/dev/iicbus/sensor/ds1631.c

93

static int ds1631_read_1(device_t dev, uint32_t addr, uint8_t reg,

sys/dev/iicbus/sensor/ds1631.c

95

static int ds1631_read_2(device_t dev, uint32_t addr, uint8_t reg,

sys/dev/iicbus/sensor/ds1631.c

97

static int ds1631_write(device_t dev, uint32_t addr, uint8_t reg,

sys/dev/iicbus/sensor/ds1775.c

70

static int ds1775_read_2(device_t dev, uint32_t addr, uint8_t reg,

sys/dev/iicbus/sensor/ds1775.c

89

ds1775_read_2(device_t dev, uint32_t addr, uint8_t reg, uint16_t *data)

sys/dev/iicbus/sensor/ds1775.c

95

{ addr, IIC_M_WR | IIC_M_NOSTOP, 1, &reg },

sys/dev/iicbus/sensor/lm75.c

130

lm75_read(device_t dev, uint32_t addr, uint8_t reg, uint8_t *data, size_t len)

sys/dev/iicbus/sensor/lm75.c

133

{ addr, IIC_M_WR | IIC_M_NOSTOP, 1, &reg },

sys/dev/iicbus/sensor/lm75.c

378

lm75_temp_read(struct lm75_softc *sc, uint8_t reg, int32_t *temp)

sys/dev/iicbus/sensor/lm75.c

385

if (lm75_read(sc->sc_dev, sc->sc_addr, reg, buf8, sizeof(buf8)) < 0)

sys/dev/iicbus/sensor/lm75.c

397

lm75_temp_write(struct lm75_softc *sc, uint8_t reg, int32_t temp)

sys/dev/iicbus/sensor/lm75.c

411

buf8[0] = reg;

sys/dev/iicbus/sensor/lm75.c

462

uint8_t reg;

sys/dev/iicbus/sensor/lm75.c

465

reg = (uint8_t)arg2;

sys/dev/iicbus/sensor/lm75.c

468

if (lm75_temp_read(sc, reg, &temp) != 0)

sys/dev/iicbus/sensor/lm75.c

475

if (lm75_temp_write(sc, reg, temp) != 0)

sys/dev/iicbus/sensor/max6690.c

103

max6690_read(device_t dev, uint32_t addr, uint8_t reg, uint8_t *data)

sys/dev/iicbus/sensor/max6690.c

115

{ addr, IIC_M_WR | IIC_M_NOSTOP, 1, &reg },

sys/dev/iicbus/sensor/max6690.c

76

static int max6690_read(device_t dev, uint32_t addr, uint8_t reg,

sys/dev/iicbus/sensor/tmp461.c

203

tmp461_read_1(device_t dev, uint8_t reg, uint8_t *data)

sys/dev/iicbus/sensor/tmp461.c

207

error = iicdev_readfrom(dev, reg, (void *) data, 1, IIC_DONTWAIT);

sys/dev/iicbus/sensor/tmp461.c

215

tmp461_write_1(device_t dev, uint8_t reg, uint8_t data)

sys/dev/iicbus/sensor/tmp461.c

219

error = iicdev_writeto(dev, reg, (void *) &data, 1, IIC_DONTWAIT);

sys/dev/iicbus/sensor/tmp461.c

229

uint8_t data, offset, reg;

sys/dev/iicbus/sensor/tmp461.c

257

reg = remote_measure ?

sys/dev/iicbus/sensor/tmp461.c

261

error = tmp461_read_1(dev, reg, &data);

sys/dev/iicbus/sensor/tmp461.c

77

static int tmp461_read_1(device_t dev, uint8_t reg, uint8_t *data);

sys/dev/iicbus/sensor/tmp461.c

78

static int tmp461_write_1(device_t dev, uint8_t reg, uint8_t data);

sys/dev/intel/spi.c

270

uint32_t reg;

sys/dev/intel/spi.c

281

reg = INTELSPI_READ(sc, INTELSPI_SSPREG_SSSR);

sys/dev/intel/spi.c

282

if (reg == 0xffffffffU) {

sys/dev/intel/spi.c

290

reg = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR1);

sys/dev/intel/spi.c

291

reg &= ~(SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE);

sys/dev/intel/spi.c

292

INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR1, reg);

sys/dev/intel/spi.c

302

uint32_t reg;

sys/dev/intel/spi.c

307

reg = INTELSPI_READ(sc, SPI_CS_CTRL(sc));

sys/dev/intel/spi.c

308

reg &= ~(SPI_CS_CTRL_CS_MASK);

sys/dev/intel/spi.c

309

reg |= (SPI_CS_CTRL_SW_MODE | SPI_CS_CTRL_CS_HIGH);

sys/dev/intel/spi.c

310

INTELSPI_WRITE(sc, SPI_CS_CTRL(sc), reg);

sys/dev/intel/spi.c

313

reg = SSCR1_TFT(TX_FIFO_THRESHOLD) | SSCR1_RFT(RX_FIFO_THRESHOLD);

sys/dev/intel/spi.c

314

INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR1, reg);

sys/dev/intel/spi.c

316

reg = SSCR0_SCR(CLOCK_DIV_10MHZ);

sys/dev/intel/spi.c

318

reg |= SSCR0_FRF_SPI;

sys/dev/intel/spi.c

320

reg |= SSCR0_DSS(DATA_SIZE_8BITS);

sys/dev/intel/spi.c

322

reg |= SSCR0_SSE;

sys/dev/intel/spi.c

323

INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR0, reg);

sys/dev/intel/spi.c

329

uint32_t reg;

sys/dev/intel/spi.c

331

reg = INTELSPI_READ(sc, SPI_CS_CTRL(sc));

sys/dev/intel/spi.c

332

reg &= ~(SPI_CS_CTRL_CS_MASK);

sys/dev/intel/spi.c

333

reg |= SPI_CS_CTRL_SW_MODE;

sys/dev/intel/spi.c

336

reg |= SPI_CS_CTRL_CS_HIGH;

sys/dev/intel/spi.c

338

INTELSPI_WRITE(sc, SPI_CS_CTRL(sc), reg);

sys/dev/intpm/intpm.c

125

amd_pmio_read(struct resource *res, uint8_t reg)

sys/dev/intpm/intpm.c

127

bus_write_1(res, 0, reg); /* Index */

sys/dev/ipw/if_ipwreg.h

326

#define CSR_READ_1(sc, reg) \

sys/dev/ipw/if_ipwreg.h

327

bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/ipw/if_ipwreg.h

329

#define CSR_READ_2(sc, reg) \

sys/dev/ipw/if_ipwreg.h

330

bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/ipw/if_ipwreg.h

332

#define CSR_READ_4(sc, reg) \

sys/dev/ipw/if_ipwreg.h

333

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/ipw/if_ipwreg.h

335

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/ipw/if_ipwreg.h

336

bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/ipw/if_ipwreg.h

338

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/ipw/if_ipwreg.h

339

bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/ipw/if_ipwreg.h

341

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/ipw/if_ipwreg.h

342

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/ipw/if_ipwreg.h

344

#define CSR_WRITE_MULTI_1(sc, reg, buf, len) \

sys/dev/ipw/if_ipwreg.h

345

bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \

sys/dev/irdma/fbsd_kcompat.c

55

irdma_rd32(struct irdma_dev_ctx *dev_ctx, u32 reg){

sys/dev/irdma/fbsd_kcompat.c

57

KASSERT(reg < dev_ctx->mem_bus_space_size,

sys/dev/irdma/fbsd_kcompat.c

59

(uintmax_t)reg, (uintmax_t)dev_ctx->mem_bus_space_size));

sys/dev/irdma/fbsd_kcompat.c

62

dev_ctx->mem_bus_space_handle, reg));

sys/dev/irdma/fbsd_kcompat.c

66

irdma_wr32(struct irdma_dev_ctx *dev_ctx, u32 reg, u32 value)

sys/dev/irdma/fbsd_kcompat.c

69

KASSERT(reg < dev_ctx->mem_bus_space_size,

sys/dev/irdma/fbsd_kcompat.c

71

(uintmax_t)reg, (uintmax_t)dev_ctx->mem_bus_space_size));

sys/dev/irdma/fbsd_kcompat.c

74

dev_ctx->mem_bus_space_handle, reg, value);

sys/dev/irdma/fbsd_kcompat.c

78

irdma_rd64(struct irdma_dev_ctx *dev_ctx, u32 reg){

sys/dev/irdma/fbsd_kcompat.c

80

KASSERT(reg < dev_ctx->mem_bus_space_size,

sys/dev/irdma/fbsd_kcompat.c

82

(uintmax_t)reg, (uintmax_t)dev_ctx->mem_bus_space_size));

sys/dev/irdma/fbsd_kcompat.c

85

dev_ctx->mem_bus_space_handle, reg));

sys/dev/irdma/fbsd_kcompat.c

89

irdma_wr64(struct irdma_dev_ctx *dev_ctx, u32 reg, u64 value)

sys/dev/irdma/fbsd_kcompat.c

92

KASSERT(reg < dev_ctx->mem_bus_space_size,

sys/dev/irdma/fbsd_kcompat.c

94

(uintmax_t)reg, (uintmax_t)dev_ctx->mem_bus_space_size));

sys/dev/irdma/fbsd_kcompat.c

97

dev_ctx->mem_bus_space_handle, reg, value);

sys/dev/irdma/osdep.h

188

#define rd32(a, reg) irdma_rd32((a)->dev_context, (reg))

sys/dev/irdma/osdep.h

189

#define wr32(a, reg, value) irdma_wr32((a)->dev_context, (reg), (value))

sys/dev/irdma/osdep.h

191

#define rd64(a, reg) irdma_rd64((a)->dev_context, (reg))

sys/dev/irdma/osdep.h

192

#define wr64(a, reg, value) irdma_wr64((a)->dev_context, (reg), (value))

sys/dev/irdma/osdep.h

218

u32 irdma_rd32(struct irdma_dev_ctx *dev_ctx, u32 reg);

sys/dev/irdma/osdep.h

219

void irdma_wr32(struct irdma_dev_ctx *dev_ctx, u32 reg, u32 value);

sys/dev/irdma/osdep.h

220

u64 irdma_rd64(struct irdma_dev_ctx *dev_ctx, u32 reg);

sys/dev/irdma/osdep.h

221

void irdma_wr64(struct irdma_dev_ctx *dev_ctx, u32 reg, u64 value);

sys/dev/isci/scil/scic_sds_controller.h

506

#define smu_register_write(controller, reg, value) \

sys/dev/isci/scil/scic_sds_controller.h

507

scic_sds_pci_write_smu_dword((controller), &(reg), (value))

sys/dev/isci/scil/scic_sds_controller.h

512

#define smu_register_read(controller, reg) \

sys/dev/isci/scil/scic_sds_controller.h

513

scic_sds_pci_read_smu_dword((controller), &(reg))

sys/dev/isci/scil/scic_sds_controller.h

518

#define scu_register_write(controller, reg, value) \

sys/dev/isci/scil/scic_sds_controller.h

519

scic_sds_pci_write_scu_dword((controller), &(reg), (value))

sys/dev/isci/scil/scic_sds_controller.h

524

#define scu_register_read(controller, reg) \

sys/dev/isci/scil/scic_sds_controller.h

525

scic_sds_pci_read_scu_dword((controller), &(reg))

sys/dev/isci/scil/scic_sds_controller.h

531

#define lex_register_write(controller, reg, value) \

sys/dev/isci/scil/scic_sds_controller.h

532

scic_cb_pci_write_dword((controller), (reg), (value))

sys/dev/isci/scil/scic_sds_controller.h

537

#define lex_register_read(controller, reg) \

sys/dev/isci/scil/scic_sds_controller.h

538

scic_cb_pci_read_dword((controller), (reg))

sys/dev/isci/scil/scic_sds_controller_registers.h

100

#define scu_afe_register_read(controller, reg) \

sys/dev/isci/scil/scic_sds_controller_registers.h

103

(controller)->scu_registers->afe.reg \

sys/dev/isci/scil/scic_sds_controller_registers.h

111

#define scu_sgpio_peg0_register_read(controller, reg) \

sys/dev/isci/scil/scic_sds_controller_registers.h

114

(controller)->scu_registers->peg0.sgpio.reg \

sys/dev/isci/scil/scic_sds_controller_registers.h

117

#define scu_sgpio_peg0_register_write(controller, reg, value) \

sys/dev/isci/scil/scic_sds_controller_registers.h

120

(controller)->scu_registers->peg0.sgpio.reg, \

sys/dev/isci/scil/scic_sds_controller_registers.h

129

#define scu_controller_viit_register_write(controller, index, reg, value) \

sys/dev/isci/scil/scic_sds_controller_registers.h

132

(controller)->scu_registers->peg0.viit[index].reg, \

sys/dev/isci/scil/scic_sds_controller_registers.h

345

#define scic_sds_controller_scu_register_read(controller, reg) \

sys/dev/isci/scil/scic_sds_controller_registers.h

348

(controller)->scu_registers->reg \

sys/dev/isci/scil/scic_sds_controller_registers.h

351

#define scic_sds_controller_scu_register_write(controller, reg, value) \

sys/dev/isci/scil/scic_sds_controller_registers.h

354

(controller)->scu_registers->reg, \

sys/dev/isci/scil/scic_sds_controller_registers.h

368

#define scu_sdma_register_read(controller, reg) \

sys/dev/isci/scil/scic_sds_controller_registers.h

371

(controller)->scu_registers->sdma.reg \

sys/dev/isci/scil/scic_sds_controller_registers.h

374

#define scu_sdma_register_write(controller, reg, value) \

sys/dev/isci/scil/scic_sds_controller_registers.h

377

(controller)->scu_registers->sdma.reg, \

sys/dev/isci/scil/scic_sds_controller_registers.h

481

#define scu_cram_register_read(controller, reg) \

sys/dev/isci/scil/scic_sds_controller_registers.h

484

(controller)->scu_registers->cram.reg \

sys/dev/isci/scil/scic_sds_controller_registers.h

487

#define scu_cram_register_write(controller, reg, value) \

sys/dev/isci/scil/scic_sds_controller_registers.h

490

(controller)->scu_registers->cram.reg, \

sys/dev/isci/scil/scic_sds_controller_registers.h

499

#define scu_fbram_register_read(controller, reg) \

sys/dev/isci/scil/scic_sds_controller_registers.h

502

(controller)->scu_registers->fbram.reg \

sys/dev/isci/scil/scic_sds_controller_registers.h

505

#define scu_fbram_register_write(controller, reg, value) \

sys/dev/isci/scil/scic_sds_controller_registers.h

508

(controller)->scu_registers->fbram.reg, \

sys/dev/isci/scil/scic_sds_controller_registers.h

556

#define scu_ptsg_register_read(controller, reg) \

sys/dev/isci/scil/scic_sds_controller_registers.h

559

(controller)->scu_registers->peg0.ptsg.reg \

sys/dev/isci/scil/scic_sds_controller_registers.h

562

#define scu_ptsg_register_write(controller, reg, value) \

sys/dev/isci/scil/scic_sds_controller_registers.h

565

(controller)->scu_registers->peg0.ptsg.reg, \

sys/dev/isci/scil/scic_sds_controller_registers.h

75

#define scic_sds_controller_smu_register_read(controller, reg) \

sys/dev/isci/scil/scic_sds_controller_registers.h

78

(controller)->smu_registers->reg \

sys/dev/isci/scil/scic_sds_controller_registers.h

81

#define scic_sds_controller_smu_register_write(controller, reg, value) \

sys/dev/isci/scil/scic_sds_controller_registers.h

84

(controller)->smu_registers->reg, \

sys/dev/isci/scil/scic_sds_controller_registers.h

93

#define scu_afe_register_write(controller, reg, value) \

sys/dev/isci/scil/scic_sds_controller_registers.h

96

(controller)->scu_registers->afe.reg, \

sys/dev/isci/scil/scic_sds_phy_registers.h

143

#define scu_link_layer_register_read(phy, reg) \

sys/dev/isci/scil/scic_sds_phy_registers.h

146

(phy)->link_layer_registers->reg \

sys/dev/isci/scil/scic_sds_phy_registers.h

153

#define scu_link_layer_register_write(phy, reg, value) \

sys/dev/isci/scil/scic_sds_phy_registers.h

156

(phy)->link_layer_registers->reg, \

sys/dev/isci/scil/scic_sds_phy_registers.h

78

#define scu_transport_layer_read(phy, reg) \

sys/dev/isci/scil/scic_sds_phy_registers.h

81

(phy)->transport_layer_registers->reg \

sys/dev/isci/scil/scic_sds_phy_registers.h

88

#define scu_transport_layer_write(phy, reg, value) \

sys/dev/isci/scil/scic_sds_phy_registers.h

91

(phy)->transport_layer_registers->reg, \

sys/dev/isci/scil/scic_sds_port_registers.h

72

#define scu_port_task_scheduler_read(port, reg) \

sys/dev/isci/scil/scic_sds_port_registers.h

75

(port)->port_task_scheduler_registers->reg \

sys/dev/isci/scil/scic_sds_port_registers.h

82

#define scu_port_task_scheduler_write(port, reg, value) \

sys/dev/isci/scil/scic_sds_port_registers.h

85

(port)->port_task_scheduler_registers->reg, \

sys/dev/isci/scil/scic_sds_port_registers.h

89

#define scu_port_viit_register_write(port, reg, value) \

sys/dev/isci/scil/scic_sds_port_registers.h

92

(port)->viit_registers->reg, \

sys/dev/iser/iser_memory.c

110

struct iser_mem_reg *reg)

sys/dev/iser/iser_memory.c

114

reg->sge.lkey = device->mr->lkey;

sys/dev/iser/iser_memory.c

115

reg->rkey = device->mr->rkey;

sys/dev/iser/iser_memory.c

116

reg->sge.length = ib_sg_dma_len(device->ib_device, &sg[0]);

sys/dev/iser/iser_memory.c

117

reg->sge.addr = ib_sg_dma_address(device->ib_device, &sg[0]);

sys/dev/iser/iser_memory.c

154

struct iser_mem_reg *reg)

sys/dev/iser/iser_memory.c

167

return iser_reg_dma(device, mem, reg);

sys/dev/iser/iser_memory.c

202

reg->sge.lkey = mr->lkey;

sys/dev/iser/iser_memory.c

203

reg->rkey = mr->rkey;

sys/dev/iser/iser_memory.c

204

reg->sge.addr = mr->iova;

sys/dev/iser/iser_memory.c

205

reg->sge.length = mr->length;

sys/dev/iser/iser_memory.c

257

struct iser_mem_reg *reg = &iser_pdu->rdma_reg[cmd_dir];

sys/dev/iser/iser_memory.c

259

if (!reg->mem_h)

sys/dev/iser/iser_memory.c

263

reg->mem_h);

sys/dev/iser/iser_memory.c

264

reg->mem_h = NULL;

sys/dev/isl/isl.c

77

isl_read_byte(device_t dev, uint8_t reg, uint8_t *val)

sys/dev/isl/isl.c

81

{ addr, IIC_M_WR | IIC_M_NOSTOP, 1, &reg },

sys/dev/isl/isl.c

89

isl_write_byte(device_t dev, uint8_t reg, uint8_t val)

sys/dev/isl/isl.c

92

uint8_t bytes[] = { reg, val };

sys/dev/isp/ispvar.h

107

#define ISP_SETBITS(isp, reg, val) \

sys/dev/isp/ispvar.h

108

(*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), ISP_READ((isp), (reg)) | (val))

sys/dev/isp/ispvar.h

110

#define ISP_CLRBITS(isp, reg, val) \

sys/dev/isp/ispvar.h

111

(*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), ISP_READ((isp), (reg)) & ~(val))

sys/dev/isp/ispvar.h

90

#define ISP_READ(isp, reg) \

sys/dev/isp/ispvar.h

91

(*(isp)->isp_mdvec->dv_rd_reg)((isp), (reg))

sys/dev/isp/ispvar.h

93

#define ISP_WRITE(isp, reg, val) \

sys/dev/isp/ispvar.h

94

(*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), (val))

sys/dev/iwi/if_iwi.c

1249

CSR_WRITE_4(sc, data->reg, data->physaddr);

sys/dev/iwi/if_iwi.c

3144

CSR_WRITE_4(sc, data->reg, data->physaddr);

sys/dev/iwi/if_iwi.c

789

data->reg = IWI_CSR_RX_BASE + i * 4;

sys/dev/iwi/if_iwireg.h

572

#define CSR_READ_1(sc, reg) \

sys/dev/iwi/if_iwireg.h

573

bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/iwi/if_iwireg.h

575

#define CSR_READ_2(sc, reg) \

sys/dev/iwi/if_iwireg.h

576

bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/iwi/if_iwireg.h

578

#define CSR_READ_4(sc, reg) \

sys/dev/iwi/if_iwireg.h

579

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/iwi/if_iwireg.h

585

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/iwi/if_iwireg.h

586

bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/iwi/if_iwireg.h

588

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/iwi/if_iwireg.h

589

bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/iwi/if_iwireg.h

591

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/iwi/if_iwireg.h

592

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/iwi/if_iwivar.h

97

uint32_t reg;

sys/dev/iwm/if_iwm.c

5910

uint16_t reg;

sys/dev/iwm/if_iwm.c

5920

reg = pci_read_config(dev, PCIR_STATUS, sizeof(reg));

sys/dev/iwm/if_iwm.c

5922

if (reg & PCIM_STATUS_INTxSTATE) {

sys/dev/iwm/if_iwm.c

5923

reg &= ~PCIM_STATUS_INTxSTATE;

sys/dev/iwm/if_iwm.c

5925

pci_write_config(dev, PCIR_STATUS, reg, sizeof(reg));

sys/dev/iwm/if_iwm_pcie_trans.c

257

iwm_poll_bit(struct iwm_softc *sc, int reg,

sys/dev/iwm/if_iwm_pcie_trans.c

261

if ((IWM_READ(sc, reg) & mask) == (bits & mask)) {

sys/dev/iwm/if_iwm_pcie_trans.c

313

uint32_t reg, uint32_t bits, uint32_t mask)

sys/dev/iwm/if_iwm_pcie_trans.c

319

val = iwm_read_prph(sc, reg) & mask;

sys/dev/iwm/if_iwm_pcie_trans.c

321

iwm_write_prph(sc, reg, val);

sys/dev/iwm/if_iwm_pcie_trans.c

327

iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/iwm/if_iwm_pcie_trans.c

329

iwm_set_bits_mask_prph(sc, reg, bits, ~0);

sys/dev/iwm/if_iwm_pcie_trans.c

333

iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/iwm/if_iwm_pcie_trans.c

335

iwm_set_bits_mask_prph(sc, reg, 0, ~bits);

sys/dev/iwm/if_iwm_pcie_trans.h

116

extern int iwm_poll_bit(struct iwm_softc *sc, int reg,

sys/dev/iwm/if_iwm_pcie_trans.h

121

uint32_t reg, uint32_t bits, uint32_t mask);

sys/dev/iwm/if_iwm_pcie_trans.h

122

extern void iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits);

sys/dev/iwm/if_iwm_pcie_trans.h

123

extern void iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits);

sys/dev/iwm/if_iwmreg.h

6958

#define IWM_READ(sc, reg) \

sys/dev/iwm/if_iwmreg.h

6959

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/iwm/if_iwmreg.h

6961

#define IWM_WRITE(sc, reg, val) \

sys/dev/iwm/if_iwmreg.h

6962

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/iwm/if_iwmreg.h

6964

#define IWM_WRITE_1(sc, reg, val) \

sys/dev/iwm/if_iwmreg.h

6965

bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/iwm/if_iwmreg.h

6967

#define IWM_SETBITS(sc, reg, mask) \

sys/dev/iwm/if_iwmreg.h

6968

IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask))

sys/dev/iwm/if_iwmreg.h

6970

#define IWM_CLRBITS(sc, reg, mask) \

sys/dev/iwm/if_iwmreg.h

6971

IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))

sys/dev/iwn/if_iwn.c

6471

uint32_t reg;

sys/dev/iwn/if_iwn.c

6495

reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4);

sys/dev/iwn/if_iwn.c

6496

if (!(reg & PCIEM_LINK_CTL_ASPMC_L0S)) /* L0s Entry disabled. */

sys/dev/iwn/if_iwn.c

8557

uint32_t reg;

sys/dev/iwn/if_iwn.c

8574

reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4);

sys/dev/iwn/if_iwn.c

8576

if (reg & PCIEM_LINK_CTL_ASPMC_L1) /* L1 Entry enabled. */

sys/dev/iwn/if_iwnreg.h

2334

#define IWN_READ(sc, reg) \

sys/dev/iwn/if_iwnreg.h

2335

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/iwn/if_iwnreg.h

2337

#define IWN_WRITE(sc, reg, val) \

sys/dev/iwn/if_iwnreg.h

2338

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/iwn/if_iwnreg.h

2340

#define IWN_WRITE_1(sc, reg, val) \

sys/dev/iwn/if_iwnreg.h

2341

bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/iwn/if_iwnreg.h

2343

#define IWN_SETBITS(sc, reg, mask) \

sys/dev/iwn/if_iwnreg.h

2344

IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask))

sys/dev/iwn/if_iwnreg.h

2346

#define IWN_CLRBITS(sc, reg, mask) \

sys/dev/iwn/if_iwnreg.h

2347

IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask))

sys/dev/iwx/if_iwx.c

1834

iwx_poll_bit(struct iwx_softc *sc, int reg, uint32_t bits, uint32_t mask,

sys/dev/iwx/if_iwx.c

1838

if ((IWX_READ(sc, reg) & mask) == (bits & mask)) {

sys/dev/iwx/if_iwx.c

1894

iwx_set_bits_mask_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits,

sys/dev/iwx/if_iwx.c

1900

val = iwx_read_prph(sc, reg) & mask;

sys/dev/iwx/if_iwx.c

1902

iwx_write_prph(sc, reg, val);

sys/dev/iwx/if_iwx.c

1910

iwx_set_bits_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/iwx/if_iwx.c

1912

return iwx_set_bits_mask_prph(sc, reg, bits, ~0);

sys/dev/iwx/if_iwx.c

1916

iwx_clear_bits_prph(struct iwx_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/iwx/if_iwx.c

1918

return iwx_set_bits_mask_prph(sc, reg, 0, ~bits);

sys/dev/iwx/if_iwxreg.h

7905

#define IWX_READ(sc, reg) \

sys/dev/iwx/if_iwxreg.h

7906

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/iwx/if_iwxreg.h

7908

#define IWX_WRITE(sc, reg, val) \

sys/dev/iwx/if_iwxreg.h

7909

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/iwx/if_iwxreg.h

7911

#define IWX_WRITE_1(sc, reg, val) \

sys/dev/iwx/if_iwxreg.h

7912

bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/iwx/if_iwxreg.h

7914

#define IWX_SETBITS(sc, reg, mask) { \

sys/dev/iwx/if_iwxreg.h

7915

IWX_WRITE(sc, reg, IWX_READ(sc, reg) | (mask)); }

sys/dev/iwx/if_iwxreg.h

7917

#define IWX_CLRBITS(sc, reg, mask) \

sys/dev/iwx/if_iwxreg.h

7918

IWX_WRITE(sc, reg, IWX_READ(sc, reg) & ~(mask))

sys/dev/ixgbe/if_ix.c

3122

unsigned int reg, usec, rate;

sys/dev/ixgbe/if_ix.c

3127

reg = IXGBE_READ_REG(&que->sc->hw, IXGBE_EITR(que->msix));

sys/dev/ixgbe/if_ix.c

3128

usec = ((reg & 0x0FF8) >> 3);

sys/dev/ixgbe/if_ix.c

3136

reg &= ~0xfff; /* default, no limitation */

sys/dev/ixgbe/if_ix.c

3142

reg |= ((4000000/rate) & 0xff8);

sys/dev/ixgbe/if_ix.c

3144

IXGBE_WRITE_REG(&que->sc->hw, IXGBE_EITR(que->msix), reg);

sys/dev/ixgbe/if_ix.c

5456

u32 reg;

sys/dev/ixgbe/if_ix.c

5484

reg = IXGBE_READ_REG(hw, IXGBE_RETA(i));

sys/dev/ixgbe/if_ix.c

5485

sbuf_printf(buf, "RETA(%2d): 0x%08x\n", i, reg);

sys/dev/ixgbe/if_ix.c

5487

reg = IXGBE_READ_REG(hw, IXGBE_ERETA(i - 32));

sys/dev/ixgbe/if_ix.c

5488

sbuf_printf(buf, "ERETA(%2d): 0x%08x\n", i - 32, reg);

sys/dev/ixgbe/if_ix.c

5514

u16 reg;

sys/dev/ixgbe/if_ix.c

5526

IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &reg)) {

sys/dev/ixgbe/if_ix.c

5534

reg = reg >> 8;

sys/dev/ixgbe/if_ix.c

5536

return (sysctl_handle_16(oidp, NULL, reg, req));

sys/dev/ixgbe/if_ix.c

5550

u16 reg;

sys/dev/ixgbe/if_ix.c

5562

IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &reg)) {

sys/dev/ixgbe/if_ix.c

5569

reg = !!(reg & 0x4000);

sys/dev/ixgbe/if_ix.c

5571

return (sysctl_handle_16(oidp, 0, reg, req));

sys/dev/ixgbe/if_ix.c

5648

u32 reg, val, shift;

sys/dev/ixgbe/if_ix.c

5654

reg = IXGBE_DTXTCPFLGL;

sys/dev/ixgbe/if_ix.c

5658

reg = IXGBE_DTXTCPFLGL;

sys/dev/ixgbe/if_ix.c

5662

reg = IXGBE_DTXTCPFLGH;

sys/dev/ixgbe/if_ix.c

5669

val = IXGBE_READ_REG(&sc->hw, reg);

sys/dev/ixgbe/if_ix.c

5677

IXGBE_WRITE_REG(&sc->hw, reg, val);

sys/dev/ixgbe/if_ix.c

5810

ixgbe_check_fan_failure(struct ixgbe_softc *sc, u32 reg, bool in_interrupt)

sys/dev/ixgbe/if_ix.c

5817

if (reg & mask)

sys/dev/ixgbe/if_ixv.c

1433

u32 reg, rxdctl;

sys/dev/ixgbe/if_ixv.c

1460

reg = IXGBE_READ_REG(hw, IXGBE_VFSRRCTL(j));

sys/dev/ixgbe/if_ixv.c

1461

reg &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;

sys/dev/ixgbe/if_ixv.c

1462

reg &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;

sys/dev/ixgbe/if_ixv.c

1463

reg |= bufsz;

sys/dev/ixgbe/if_ixv.c

1464

reg |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;

sys/dev/ixgbe/if_ixv.c

1465

IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(j), reg);

sys/dev/ixgbe/if_ixv.c

1780

#define UPDATE_STAT_32(reg, last, count) \

sys/dev/ixgbe/if_ixv.c

1782

u32 current = IXGBE_READ_REG(hw, reg); \

sys/dev/ixgbe/if_ixv.c

728

u32 reg;

sys/dev/ixgbe/if_ixv.c

733

reg = IXGBE_READ_REG(hw, IXGBE_VTEICS);

sys/dev/ixgbe/if_ixv.c

735

IXGBE_WRITE_REG(hw, IXGBE_VTEICR, reg);

sys/dev/ixgbe/if_ixv.c

738

if (reg & IXGBE_EICR_LSC)

sys/dev/ixgbe/ixgbe_82598.c

1079

s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)

sys/dev/ixgbe/ixgbe_82598.c

1086

IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));

sys/dev/ixgbe/ixgbe_82598.c

1103

s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)

sys/dev/ixgbe/ixgbe_82598.c

1109

atlas_ctl = (reg << 8) | val;

sys/dev/ixgbe/ixgbe_82598.c

413

u32 reg;

sys/dev/ixgbe/ixgbe_82598.c

538

reg = hw->fc.pause_time * 0x00010001;

sys/dev/ixgbe/ixgbe_82598.c

540

IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);

sys/dev/ixgbe/ixgbe_82598.h

45

s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);

sys/dev/ixgbe/ixgbe_82598.h

46

s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);

sys/dev/ixgbe/ixgbe_82599.c

1715

#define IXGBE_WRITE_REG_BE32(a, reg, value) \

sys/dev/ixgbe/ixgbe_82599.c

1716

IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))

sys/dev/ixgbe/ixgbe_82599.c

2103

s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)

sys/dev/ixgbe/ixgbe_82599.c

2110

(reg << 8));

sys/dev/ixgbe/ixgbe_82599.c

2127

s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)

sys/dev/ixgbe/ixgbe_82599.c

2133

core_ctl = (reg << 8) | val;

sys/dev/ixgbe/ixgbe_82599.h

56

s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);

sys/dev/ixgbe/ixgbe_82599.h

57

s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);

sys/dev/ixgbe/ixgbe_api.c

1504

s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)

sys/dev/ixgbe/ixgbe_api.c

1506

return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,

sys/dev/ixgbe/ixgbe_api.c

1518

s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)

sys/dev/ixgbe/ixgbe_api.c

1520

return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg,

sys/dev/ixgbe/ixgbe_api.c

1579

s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)

sys/dev/ixgbe/ixgbe_api.c

1582

reg, val), IXGBE_NOT_IMPLEMENTED);

sys/dev/ixgbe/ixgbe_api.c

1594

s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)

sys/dev/ixgbe/ixgbe_api.c

1597

(hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);

sys/dev/ixgbe/ixgbe_api.c

1644

s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)

sys/dev/ixgbe/ixgbe_api.c

1647

(hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);

sys/dev/ixgbe/ixgbe_api.c

1659

s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)

sys/dev/ixgbe/ixgbe_api.c

1662

(hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);

sys/dev/ixgbe/ixgbe_api.h

145

s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);

sys/dev/ixgbe/ixgbe_api.h

146

s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);

sys/dev/ixgbe/ixgbe_api.h

184

s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);

sys/dev/ixgbe/ixgbe_api.h

185

s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);

sys/dev/ixgbe/ixgbe_api.h

191

s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);

sys/dev/ixgbe/ixgbe_api.h

192

s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);

sys/dev/ixgbe/ixgbe_common.c

1089

u32 reg;

sys/dev/ixgbe/ixgbe_common.c

1094

reg = IXGBE_READ_REG(hw, IXGBE_STATUS);

sys/dev/ixgbe/ixgbe_common.c

1095

bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;

sys/dev/ixgbe/ixgbe_common.c

1099

reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));

sys/dev/ixgbe/ixgbe_common.c

1100

if (reg & IXGBE_FACTPS_LFS)

sys/dev/ixgbe/ixgbe_common.c

1795

u32 reg;

sys/dev/ixgbe/ixgbe_common.c

1802

reg = IXGBE_READ_REG(hw, IXGBE_EERD);

sys/dev/ixgbe/ixgbe_common.c

1804

reg = IXGBE_READ_REG(hw, IXGBE_EEWR);

sys/dev/ixgbe/ixgbe_common.c

1806

if (reg & IXGBE_EEPROM_RW_REG_DONE) {

sys/dev/ixgbe/ixgbe_common.c

242

u32 reg = 0, reg_bp = 0;

sys/dev/ixgbe/ixgbe_common.c

275

reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);

sys/dev/ixgbe/ixgbe_common.c

280

reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);

sys/dev/ixgbe/ixgbe_common.c

2823

u32 reg;

sys/dev/ixgbe/ixgbe_common.c

2935

reg = hw->fc.pause_time * 0x00010001;

sys/dev/ixgbe/ixgbe_common.c

2937

IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);

sys/dev/ixgbe/ixgbe_common.c

304

reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);

sys/dev/ixgbe/ixgbe_common.c

316

reg |= IXGBE_PCS1GANA_ASM_PAUSE;

sys/dev/ixgbe/ixgbe_common.c

317

reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;

sys/dev/ixgbe/ixgbe_common.c

338

reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;

sys/dev/ixgbe/ixgbe_common.c

358

IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);

sys/dev/ixgbe/ixgbe_common.c

359

reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);

sys/dev/ixgbe/ixgbe_common.c

363

reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;

sys/dev/ixgbe/ixgbe_common.c

365

IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);

sys/dev/ixgbe/ixgbe_common.c

366

DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);

sys/dev/ixgbe/ixgbe_common.c

385

DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);

sys/dev/ixgbe/ixgbe_common.c

4163

u32 offset, reg;

sys/dev/ixgbe/ixgbe_common.c

4172

reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);

sys/dev/ixgbe/ixgbe_common.c

4173

switch (reg & IXGBE_GCR_EXT_VT_MODE_MASK) {

sys/dev/ixgbe/ixgbe_common.c

4193

reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));

sys/dev/ixgbe/ixgbe_common.c

4194

reg |= IXGBE_TXDCTL_ENABLE;

sys/dev/ixgbe/ixgbe_common.c

4195

IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);

sys/dev/ixgbe/ixgbe_common.c

4199

reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));

sys/dev/ixgbe/ixgbe_common.c

4200

reg &= ~IXGBE_TXDCTL_ENABLE;

sys/dev/ixgbe/ixgbe_common.c

4201

IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);

sys/dev/ixgbe/ixgbe_common.c

5574

u32 reg, i;

sys/dev/ixgbe/ixgbe_common.c

5576

reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);

sys/dev/ixgbe/ixgbe_common.c

5579

(reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));

sys/dev/ixgbe/ixgbe_common.h

39

#define IXGBE_WRITE_REG64(hw, reg, value) \

sys/dev/ixgbe/ixgbe_common.h

41

IXGBE_WRITE_REG(hw, reg, (u32) value); \

sys/dev/ixgbe/ixgbe_common.h

42

IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \

sys/dev/ixgbe/ixgbe_dcb_82598.c

115

u32 reg = 0;

sys/dev/ixgbe/ixgbe_dcb_82598.c

120

reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;

sys/dev/ixgbe/ixgbe_dcb_82598.c

121

IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);

sys/dev/ixgbe/ixgbe_dcb_82598.c

123

reg = IXGBE_READ_REG(hw, IXGBE_RMCS);

sys/dev/ixgbe/ixgbe_dcb_82598.c

125

reg &= ~IXGBE_RMCS_ARBDIS;

sys/dev/ixgbe/ixgbe_dcb_82598.c

127

reg |= IXGBE_RMCS_RRM;

sys/dev/ixgbe/ixgbe_dcb_82598.c

129

reg |= IXGBE_RMCS_DFP;

sys/dev/ixgbe/ixgbe_dcb_82598.c

131

IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);

sys/dev/ixgbe/ixgbe_dcb_82598.c

138

reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);

sys/dev/ixgbe/ixgbe_dcb_82598.c

141

reg |= IXGBE_RT2CR_LSP;

sys/dev/ixgbe/ixgbe_dcb_82598.c

143

IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);

sys/dev/ixgbe/ixgbe_dcb_82598.c

146

reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);

sys/dev/ixgbe/ixgbe_dcb_82598.c

147

reg |= IXGBE_RDRXCTL_RDMTS_1_2;

sys/dev/ixgbe/ixgbe_dcb_82598.c

148

reg |= IXGBE_RDRXCTL_MPBEN;

sys/dev/ixgbe/ixgbe_dcb_82598.c

149

reg |= IXGBE_RDRXCTL_MCEN;

sys/dev/ixgbe/ixgbe_dcb_82598.c

150

IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);

sys/dev/ixgbe/ixgbe_dcb_82598.c

152

reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);

sys/dev/ixgbe/ixgbe_dcb_82598.c

154

reg &= ~IXGBE_RXCTRL_DMBYPS;

sys/dev/ixgbe/ixgbe_dcb_82598.c

155

IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);

sys/dev/ixgbe/ixgbe_dcb_82598.c

174

u32 reg, max_credits;

sys/dev/ixgbe/ixgbe_dcb_82598.c

177

reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);

sys/dev/ixgbe/ixgbe_dcb_82598.c

180

reg &= ~IXGBE_DPMCS_ARBDIS;

sys/dev/ixgbe/ixgbe_dcb_82598.c

181

reg |= IXGBE_DPMCS_TSOEF;

sys/dev/ixgbe/ixgbe_dcb_82598.c

184

reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);

sys/dev/ixgbe/ixgbe_dcb_82598.c

186

IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);

sys/dev/ixgbe/ixgbe_dcb_82598.c

191

reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;

sys/dev/ixgbe/ixgbe_dcb_82598.c

192

reg |= (u32)(refill[i]);

sys/dev/ixgbe/ixgbe_dcb_82598.c

193

reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;

sys/dev/ixgbe/ixgbe_dcb_82598.c

196

reg |= IXGBE_TDTQ2TCCR_GSP;

sys/dev/ixgbe/ixgbe_dcb_82598.c

199

reg |= IXGBE_TDTQ2TCCR_LSP;

sys/dev/ixgbe/ixgbe_dcb_82598.c

201

IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);

sys/dev/ixgbe/ixgbe_dcb_82598.c

221

u32 reg;

sys/dev/ixgbe/ixgbe_dcb_82598.c

224

reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);

sys/dev/ixgbe/ixgbe_dcb_82598.c

226

reg &= ~IXGBE_PDPMCS_ARBDIS;

sys/dev/ixgbe/ixgbe_dcb_82598.c

228

reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);

sys/dev/ixgbe/ixgbe_dcb_82598.c

230

IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);

sys/dev/ixgbe/ixgbe_dcb_82598.c

234

reg = refill[i];

sys/dev/ixgbe/ixgbe_dcb_82598.c

235

reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;

sys/dev/ixgbe/ixgbe_dcb_82598.c

236

reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;

sys/dev/ixgbe/ixgbe_dcb_82598.c

239

reg |= IXGBE_TDPT2TCCR_GSP;

sys/dev/ixgbe/ixgbe_dcb_82598.c

242

reg |= IXGBE_TDPT2TCCR_LSP;

sys/dev/ixgbe/ixgbe_dcb_82598.c

244

IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);

sys/dev/ixgbe/ixgbe_dcb_82598.c

248

reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);

sys/dev/ixgbe/ixgbe_dcb_82598.c

249

reg |= IXGBE_DTXCTL_ENDBUBD;

sys/dev/ixgbe/ixgbe_dcb_82598.c

250

IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);

sys/dev/ixgbe/ixgbe_dcb_82598.c

264

u32 fcrtl, reg;

sys/dev/ixgbe/ixgbe_dcb_82598.c

268

reg = IXGBE_READ_REG(hw, IXGBE_RMCS);

sys/dev/ixgbe/ixgbe_dcb_82598.c

269

reg &= ~IXGBE_RMCS_TFCE_802_3X;

sys/dev/ixgbe/ixgbe_dcb_82598.c

270

reg |= IXGBE_RMCS_TFCE_PRIORITY;

sys/dev/ixgbe/ixgbe_dcb_82598.c

271

IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);

sys/dev/ixgbe/ixgbe_dcb_82598.c

274

reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);

sys/dev/ixgbe/ixgbe_dcb_82598.c

275

reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);

sys/dev/ixgbe/ixgbe_dcb_82598.c

278

reg |= IXGBE_FCTRL_RPFCE;

sys/dev/ixgbe/ixgbe_dcb_82598.c

280

IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);

sys/dev/ixgbe/ixgbe_dcb_82598.c

291

reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;

sys/dev/ixgbe/ixgbe_dcb_82598.c

293

IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);

sys/dev/ixgbe/ixgbe_dcb_82598.c

297

reg = hw->fc.pause_time | (hw->fc.pause_time << 16);

sys/dev/ixgbe/ixgbe_dcb_82598.c

299

IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);

sys/dev/ixgbe/ixgbe_dcb_82598.c

316

u32 reg = 0;

sys/dev/ixgbe/ixgbe_dcb_82598.c

322

reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));

sys/dev/ixgbe/ixgbe_dcb_82598.c

323

reg |= ((0x1010101) * j);

sys/dev/ixgbe/ixgbe_dcb_82598.c

324

IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);

sys/dev/ixgbe/ixgbe_dcb_82598.c

325

reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));

sys/dev/ixgbe/ixgbe_dcb_82598.c

326

reg |= ((0x1010101) * j);

sys/dev/ixgbe/ixgbe_dcb_82598.c

327

IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);

sys/dev/ixgbe/ixgbe_dcb_82598.c

331

reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));

sys/dev/ixgbe/ixgbe_dcb_82598.c

332

reg |= ((0x1010101) * i);

sys/dev/ixgbe/ixgbe_dcb_82598.c

333

IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

125

u32 reg = 0;

sys/dev/ixgbe/ixgbe_dcb_82599.c

134

reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;

sys/dev/ixgbe/ixgbe_dcb_82599.c

135

IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

143

reg = 0;

sys/dev/ixgbe/ixgbe_dcb_82599.c

145

reg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));

sys/dev/ixgbe/ixgbe_dcb_82599.c

147

IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

153

reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);

sys/dev/ixgbe/ixgbe_dcb_82599.c

155

reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;

sys/dev/ixgbe/ixgbe_dcb_82599.c

158

reg |= IXGBE_RTRPT4C_LSP;

sys/dev/ixgbe/ixgbe_dcb_82599.c

160

IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

167

reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;

sys/dev/ixgbe/ixgbe_dcb_82599.c

168

IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

186

u32 reg, max_credits;

sys/dev/ixgbe/ixgbe_dcb_82599.c

198

reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;

sys/dev/ixgbe/ixgbe_dcb_82599.c

199

reg |= (u32)(refill[i]);

sys/dev/ixgbe/ixgbe_dcb_82599.c

200

reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;

sys/dev/ixgbe/ixgbe_dcb_82599.c

203

reg |= IXGBE_RTTDT2C_GSP;

sys/dev/ixgbe/ixgbe_dcb_82599.c

206

reg |= IXGBE_RTTDT2C_LSP;

sys/dev/ixgbe/ixgbe_dcb_82599.c

208

IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

215

reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;

sys/dev/ixgbe/ixgbe_dcb_82599.c

216

IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

236

u32 reg;

sys/dev/ixgbe/ixgbe_dcb_82599.c

243

reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |

sys/dev/ixgbe/ixgbe_dcb_82599.c

246

IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

254

reg = 0;

sys/dev/ixgbe/ixgbe_dcb_82599.c

256

reg |= (map[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));

sys/dev/ixgbe/ixgbe_dcb_82599.c

258

IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

262

reg = refill[i];

sys/dev/ixgbe/ixgbe_dcb_82599.c

263

reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;

sys/dev/ixgbe/ixgbe_dcb_82599.c

264

reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;

sys/dev/ixgbe/ixgbe_dcb_82599.c

267

reg |= IXGBE_RTTPT2C_GSP;

sys/dev/ixgbe/ixgbe_dcb_82599.c

270

reg |= IXGBE_RTTPT2C_LSP;

sys/dev/ixgbe/ixgbe_dcb_82599.c

272

IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

279

reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |

sys/dev/ixgbe/ixgbe_dcb_82599.c

281

IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

296

u32 i, j, fcrtl, reg;

sys/dev/ixgbe/ixgbe_dcb_82599.c

303

reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);

sys/dev/ixgbe/ixgbe_dcb_82599.c

304

reg |= IXGBE_MFLCN_DPF;

sys/dev/ixgbe/ixgbe_dcb_82599.c

311

reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);

sys/dev/ixgbe/ixgbe_dcb_82599.c

314

reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;

sys/dev/ixgbe/ixgbe_dcb_82599.c

317

reg |= IXGBE_MFLCN_RPFCE;

sys/dev/ixgbe/ixgbe_dcb_82599.c

319

IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

339

reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;

sys/dev/ixgbe/ixgbe_dcb_82599.c

350

reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;

sys/dev/ixgbe/ixgbe_dcb_82599.c

354

IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

363

reg = hw->fc.pause_time | (hw->fc.pause_time << 16);

sys/dev/ixgbe/ixgbe_dcb_82599.c

365

IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

384

u32 reg = 0;

sys/dev/ixgbe/ixgbe_dcb_82599.c

406

reg = 0x01010101 * (i / 4);

sys/dev/ixgbe/ixgbe_dcb_82599.c

407

IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

420

reg = 0x00000000;

sys/dev/ixgbe/ixgbe_dcb_82599.c

422

reg = 0x01010101;

sys/dev/ixgbe/ixgbe_dcb_82599.c

424

reg = 0x02020202;

sys/dev/ixgbe/ixgbe_dcb_82599.c

426

reg = 0x03030303;

sys/dev/ixgbe/ixgbe_dcb_82599.c

428

reg = 0x04040404;

sys/dev/ixgbe/ixgbe_dcb_82599.c

430

reg = 0x05050505;

sys/dev/ixgbe/ixgbe_dcb_82599.c

432

reg = 0x06060606;

sys/dev/ixgbe/ixgbe_dcb_82599.c

434

reg = 0x07070707;

sys/dev/ixgbe/ixgbe_dcb_82599.c

435

IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

451

reg = 0x01010101 * (i / 8);

sys/dev/ixgbe/ixgbe_dcb_82599.c

452

IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

465

reg = 0x00000000;

sys/dev/ixgbe/ixgbe_dcb_82599.c

467

reg = 0x01010101;

sys/dev/ixgbe/ixgbe_dcb_82599.c

469

reg = 0x02020202;

sys/dev/ixgbe/ixgbe_dcb_82599.c

471

reg = 0x03030303;

sys/dev/ixgbe/ixgbe_dcb_82599.c

472

IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

510

u32 reg;

sys/dev/ixgbe/ixgbe_dcb_82599.c

514

reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);

sys/dev/ixgbe/ixgbe_dcb_82599.c

515

reg |= IXGBE_RTTDCS_ARBDIS;

sys/dev/ixgbe/ixgbe_dcb_82599.c

516

IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

518

reg = IXGBE_READ_REG(hw, IXGBE_MRQC);

sys/dev/ixgbe/ixgbe_dcb_82599.c

521

switch (reg & IXGBE_MRQC_MRQE_MASK) {

sys/dev/ixgbe/ixgbe_dcb_82599.c

525

reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |

sys/dev/ixgbe/ixgbe_dcb_82599.c

531

reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |

sys/dev/ixgbe/ixgbe_dcb_82599.c

540

reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |

sys/dev/ixgbe/ixgbe_dcb_82599.c

547

reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |

sys/dev/ixgbe/ixgbe_dcb_82599.c

550

reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |

sys/dev/ixgbe/ixgbe_dcb_82599.c

553

IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

557

reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;

sys/dev/ixgbe/ixgbe_dcb_82599.c

560

reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;

sys/dev/ixgbe/ixgbe_dcb_82599.c

562

reg |= IXGBE_MTQC_VT_ENA;

sys/dev/ixgbe/ixgbe_dcb_82599.c

564

IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

572

reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);

sys/dev/ixgbe/ixgbe_dcb_82599.c

573

reg &= ~IXGBE_RTTDCS_ARBDIS;

sys/dev/ixgbe/ixgbe_dcb_82599.c

574

IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);

sys/dev/ixgbe/ixgbe_dcb_82599.c

577

reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);

sys/dev/ixgbe/ixgbe_dcb_82599.c

578

reg |= IXGBE_SECTX_DCB;

sys/dev/ixgbe/ixgbe_dcb_82599.c

579

IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);

sys/dev/ixgbe/ixgbe_e610.c

4121

static s32 ixgbe_aci_fwlog_register(struct ixgbe_hw *hw, bool reg)

sys/dev/ixgbe/ixgbe_e610.c

4127

if (reg)

sys/dev/ixgbe/ixgbe_osdep.c

43

ixgbe_read_pci_cfg(struct ixgbe_hw *hw, u32 reg)

sys/dev/ixgbe/ixgbe_osdep.c

45

return pci_read_config(((struct ixgbe_softc *)hw->back)->dev, reg, 2);

sys/dev/ixgbe/ixgbe_osdep.c

49

ixgbe_write_pci_cfg(struct ixgbe_hw *hw, u32 reg, u16 value)

sys/dev/ixgbe/ixgbe_osdep.c

51

pci_write_config(((struct ixgbe_softc *)hw->back)->dev, reg, value, 2);

sys/dev/ixgbe/ixgbe_osdep.c

55

ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)

sys/dev/ixgbe/ixgbe_osdep.c

58

((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle, reg);

sys/dev/ixgbe/ixgbe_osdep.c

62

ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 val)

sys/dev/ixgbe/ixgbe_osdep.c

66

reg, val);

sys/dev/ixgbe/ixgbe_osdep.c

70

ixgbe_read_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset)

sys/dev/ixgbe/ixgbe_osdep.c

74

reg + (offset << 2));

sys/dev/ixgbe/ixgbe_osdep.c

78

ixgbe_write_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset, u32 val)

sys/dev/ixgbe/ixgbe_osdep.c

82

reg + (offset << 2), val);

sys/dev/ixgbe/ixgbe_osdep.h

220

#define IXGBE_READ_REG(a, reg) ixgbe_read_reg(a, reg)

sys/dev/ixgbe/ixgbe_osdep.h

223

#define IXGBE_WRITE_REG(a, reg, val) ixgbe_write_reg(a, reg, val)

sys/dev/ixgbe/ixgbe_osdep.h

226

#define IXGBE_READ_REG_ARRAY(a, reg, offset) \

sys/dev/ixgbe/ixgbe_osdep.h

227

ixgbe_read_reg_array(a, reg, offset)

sys/dev/ixgbe/ixgbe_osdep.h

230

#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, val) \

sys/dev/ixgbe/ixgbe_osdep.h

231

ixgbe_write_reg_array(a, reg, offset, val)

sys/dev/ixgbe/ixgbe_phy.c

109

s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,

sys/dev/ixgbe/ixgbe_phy.c

121

reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */

sys/dev/ixgbe/ixgbe_phy.c

122

csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);

sys/dev/ixgbe/ixgbe_phy.c

135

if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))

sys/dev/ixgbe/ixgbe_phy.c

186

s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,

sys/dev/ixgbe/ixgbe_phy.c

195

reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */

sys/dev/ixgbe/ixgbe_phy.c

196

csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);

sys/dev/ixgbe/ixgbe_phy.c

211

if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))

sys/dev/ixgbe/ixgbe_phy.c

2695

u16 reg;

sys/dev/ixgbe/ixgbe_phy.c

2702

&reg);

sys/dev/ixgbe/ixgbe_phy.c

2707

reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;

sys/dev/ixgbe/ixgbe_phy.c

2711

reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;

sys/dev/ixgbe/ixgbe_phy.c

2716

reg);

sys/dev/ixgbe/ixgbe_phy.h

216

s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,

sys/dev/ixgbe/ixgbe_phy.h

218

s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,

sys/dev/ixgbe/ixgbe_type.h

4180

s32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);

sys/dev/ixgbe/ixgbe_type.h

4181

s32 (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,

sys/dev/ixgbe/ixgbe_type.h

4183

s32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);

sys/dev/ixgbe/ixgbe_type.h

4184

s32 (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,

sys/dev/ixgbe/ixgbe_x540.c

739

u32 reg;

sys/dev/ixgbe/ixgbe_x540.c

745

reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));

sys/dev/ixgbe/ixgbe_x540.c

746

if (reg & IXGBE_EEC_FLUDONE) {

sys/dev/ixgbe/ixgbe_x550.c

1000

IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);

sys/dev/ixgbe/ixgbe_x550.c

113

static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)

sys/dev/ixgbe/ixgbe_x550.c

115

return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);

sys/dev/ixgbe/ixgbe_x550.c

126

static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)

sys/dev/ixgbe/ixgbe_x550.c

128

return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);

sys/dev/ixgbe/ixgbe_x550.c

1291

u32 reg;

sys/dev/ixgbe/ixgbe_x550.c

1296

reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);

sys/dev/ixgbe/ixgbe_x550.c

1297

reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);

sys/dev/ixgbe/ixgbe_x550.c

1298

IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);

sys/dev/ixgbe/ixgbe_x550.c

1301

reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);

sys/dev/ixgbe/ixgbe_x550.c

1302

reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);

sys/dev/ixgbe/ixgbe_x550.c

1303

IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);

sys/dev/ixgbe/ixgbe_x550.c

1314

u32 reg;

sys/dev/ixgbe/ixgbe_x550.c

1319

reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);

sys/dev/ixgbe/ixgbe_x550.c

1320

reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);

sys/dev/ixgbe/ixgbe_x550.c

1321

IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);

sys/dev/ixgbe/ixgbe_x550.c

1324

reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);

sys/dev/ixgbe/ixgbe_x550.c

1325

reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);

sys/dev/ixgbe/ixgbe_x550.c

1326

IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);

sys/dev/ixgbe/ixgbe_x550.c

1338

u32 idx, reg, num_qs, start_q, bitmask;

sys/dev/ixgbe/ixgbe_x550.c

1343

reg = IXGBE_READ_REG(hw, IXGBE_MRQC);

sys/dev/ixgbe/ixgbe_x550.c

1344

switch (reg & IXGBE_MRQC_MRQE_MASK) {

sys/dev/ixgbe/ixgbe_x550.c

1363

reg = 0;

sys/dev/ixgbe/ixgbe_x550.c

1364

reg |= (bitmask << (start_q % 32));

sys/dev/ixgbe/ixgbe_x550.c

1365

IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);

sys/dev/ixgbe/ixgbe_x550.c

1366

IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);

sys/dev/ixgbe/ixgbe_x550.c

1379

u32 i, j, reg, q, shift, vf, idx;

sys/dev/ixgbe/ixgbe_x550.c

1384

reg = IXGBE_READ_REG(hw, IXGBE_MRQC);

sys/dev/ixgbe/ixgbe_x550.c

1385

switch (reg & IXGBE_MRQC_MRQE_MASK) {

sys/dev/ixgbe/ixgbe_x550.c

139

static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)

sys/dev/ixgbe/ixgbe_x550.c

143

status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);

sys/dev/ixgbe/ixgbe_x550.c

158

static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)

sys/dev/ixgbe/ixgbe_x550.c

162

status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);

sys/dev/ixgbe/ixgbe_x550.c

181

u8 reg;

sys/dev/ixgbe/ixgbe_x550.c

184

status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);

sys/dev/ixgbe/ixgbe_x550.c

187

reg |= IXGBE_PE_BIT1;

sys/dev/ixgbe/ixgbe_x550.c

188

status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);

sys/dev/ixgbe/ixgbe_x550.c

1903

u16 reg;

sys/dev/ixgbe/ixgbe_x550.c

1910

&reg);

sys/dev/ixgbe/ixgbe_x550.c

1913

!(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))

sys/dev/ixgbe/ixgbe_x550.c

1919

&reg);

sys/dev/ixgbe/ixgbe_x550.c

192

status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);

sys/dev/ixgbe/ixgbe_x550.c

1922

!(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |

sys/dev/ixgbe/ixgbe_x550.c

1929

&reg);

sys/dev/ixgbe/ixgbe_x550.c

1935

if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {

sys/dev/ixgbe/ixgbe_x550.c

1939

} else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {

sys/dev/ixgbe/ixgbe_x550.c

1943

&reg);

sys/dev/ixgbe/ixgbe_x550.c

1949

if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {

sys/dev/ixgbe/ixgbe_x550.c

195

reg &= ~IXGBE_PE_BIT1;

sys/dev/ixgbe/ixgbe_x550.c

1958

IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);

sys/dev/ixgbe/ixgbe_x550.c

196

status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);

sys/dev/ixgbe/ixgbe_x550.c

1961

!(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))

sys/dev/ixgbe/ixgbe_x550.c

1966

IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);

sys/dev/ixgbe/ixgbe_x550.c

1972

if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)

sys/dev/ixgbe/ixgbe_x550.c

1990

u16 reg;

sys/dev/ixgbe/ixgbe_x550.c

200

status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);

sys/dev/ixgbe/ixgbe_x550.c

2009

IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);

sys/dev/ixgbe/ixgbe_x550.c

2014

reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;

sys/dev/ixgbe/ixgbe_x550.c

2018

IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);

sys/dev/ixgbe/ixgbe_x550.c

2027

&reg);

sys/dev/ixgbe/ixgbe_x550.c

203

reg &= ~IXGBE_PE_BIT1;

sys/dev/ixgbe/ixgbe_x550.c

2032

reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |

sys/dev/ixgbe/ixgbe_x550.c

2037

reg);

sys/dev/ixgbe/ixgbe_x550.c

204

status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);

sys/dev/ixgbe/ixgbe_x550.c

2045

&reg);

sys/dev/ixgbe/ixgbe_x550.c

2050

reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |

sys/dev/ixgbe/ixgbe_x550.c

2055

reg);

sys/dev/ixgbe/ixgbe_x550.c

2063

&reg);

sys/dev/ixgbe/ixgbe_x550.c

2068

reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;

sys/dev/ixgbe/ixgbe_x550.c

2072

reg);

sys/dev/ixgbe/ixgbe_x550.c

210

status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);

sys/dev/ixgbe/ixgbe_x550.c

213

reg |= IXGBE_PE_BIT1;

sys/dev/ixgbe/ixgbe_x550.c

214

status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);

sys/dev/ixgbe/ixgbe_x550.c

2503

u16 reg;

sys/dev/ixgbe/ixgbe_x550.c

2508

&reg);

sys/dev/ixgbe/ixgbe_x550.c

2516

if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {

sys/dev/ixgbe/ixgbe_x550.c

2520

&reg);

sys/dev/ixgbe/ixgbe_x550.c

2525

reg &= ~IXGBE_MDIO_POWER_UP_STALL;

sys/dev/ixgbe/ixgbe_x550.c

2530

reg);

sys/dev/ixgbe/ixgbe_x550.c

3150

u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +

sys/dev/ixgbe/ixgbe_x550.c

3152

u32 value = IXGBE_READ_REG(hw, reg);

sys/dev/ixgbe/ixgbe_x550.c

544

u16 reg, u16 *val)

sys/dev/ixgbe/ixgbe_x550.c

546

return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);

sys/dev/ixgbe/ixgbe_x550.c

560

u16 reg, u16 *val)

sys/dev/ixgbe/ixgbe_x550.c

562

return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);

sys/dev/ixgbe/ixgbe_x550.c

575

u8 addr, u16 reg, u16 val)

sys/dev/ixgbe/ixgbe_x550.c

577

return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);

sys/dev/ixgbe/ixgbe_x550.c

591

u8 addr, u16 reg, u16 val)

sys/dev/ixgbe/ixgbe_x550.c

593

return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);

sys/dev/ixgbe/ixgbe_x550.c

883

u32 reg, high_pri_tc;

sys/dev/ixgbe/ixgbe_x550.c

888

reg = IXGBE_READ_REG(hw, IXGBE_DMACR);

sys/dev/ixgbe/ixgbe_x550.c

889

reg &= ~IXGBE_DMACR_DMAC_EN;

sys/dev/ixgbe/ixgbe_x550.c

890

IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);

sys/dev/ixgbe/ixgbe_x550.c

899

reg = IXGBE_READ_REG(hw, IXGBE_DMACR);

sys/dev/ixgbe/ixgbe_x550.c

902

reg &= ~IXGBE_DMACR_DMACWT_MASK;

sys/dev/ixgbe/ixgbe_x550.c

903

reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;

sys/dev/ixgbe/ixgbe_x550.c

905

reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;

sys/dev/ixgbe/ixgbe_x550.c

909

reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &

sys/dev/ixgbe/ixgbe_x550.c

912

reg |= IXGBE_DMACR_EN_MNG_IND;

sys/dev/ixgbe/ixgbe_x550.c

915

reg |= IXGBE_DMACR_DMAC_EN;

sys/dev/ixgbe/ixgbe_x550.c

916

IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);

sys/dev/ixgbe/ixgbe_x550.c

931

u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;

sys/dev/ixgbe/ixgbe_x550.c

954

reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));

sys/dev/ixgbe/ixgbe_x550.c

955

reg &= ~IXGBE_DMCTH_DMACRXT_MASK;

sys/dev/ixgbe/ixgbe_x550.c

970

reg |= (rx_pb_size > maxframe_size_kb) ?

sys/dev/ixgbe/ixgbe_x550.c

973

IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);

sys/dev/ixgbe/ixgbe_x550.c

986

u32 reg;

sys/dev/ixgbe/ixgbe_x550.c

991

reg = IXGBE_READ_REG(hw, IXGBE_DMACR);

sys/dev/ixgbe/ixgbe_x550.c

992

reg &= ~IXGBE_DMACR_DMAC_EN;

sys/dev/ixgbe/ixgbe_x550.c

993

IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);

sys/dev/ixgbe/ixgbe_x550.c

998

reg = IXGBE_READ_REG(hw, IXGBE_DMACR);

sys/dev/ixgbe/ixgbe_x550.c

999

reg |= IXGBE_DMACR_DMAC_EN;

sys/dev/ixl/i40e_adminq.c

301

u32 reg = 0;

sys/dev/ixl/i40e_adminq.c

318

reg = rd32(hw, hw->aq.asq.bal);

sys/dev/ixl/i40e_adminq.c

319

if (reg != I40E_LO_DWORD(hw->aq.asq.desc_buf.pa))

sys/dev/ixl/i40e_adminq.c

334

u32 reg = 0;

sys/dev/ixl/i40e_adminq.c

354

reg = rd32(hw, hw->aq.arq.bal);

sys/dev/ixl/i40e_adminq.c

355

if (reg != I40E_LO_DWORD(hw->aq.arq.desc_buf.pa))

sys/dev/ixl/i40e_common.c

1304

u32 cnt, reg = 0;

sys/dev/ixl/i40e_common.c

1307

reg = rd32(hw, I40E_GLGEN_RSTAT);

sys/dev/ixl/i40e_common.c

1308

if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))

sys/dev/ixl/i40e_common.c

1314

DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);

sys/dev/ixl/i40e_common.c

1331

u32 reg = 0;

sys/dev/ixl/i40e_common.c

1345

reg = rd32(hw, I40E_GLGEN_RSTAT);

sys/dev/ixl/i40e_common.c

1346

if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))

sys/dev/ixl/i40e_common.c

1350

if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {

sys/dev/ixl/i40e_common.c

1357

reg = rd32(hw, I40E_GLNVM_ULD);

sys/dev/ixl/i40e_common.c

1358

reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |

sys/dev/ixl/i40e_common.c

1360

if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |

sys/dev/ixl/i40e_common.c

1367

if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |

sys/dev/ixl/i40e_common.c

1370

DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);

sys/dev/ixl/i40e_common.c

1380

reg = rd32(hw, I40E_PFGEN_CTRL);

sys/dev/ixl/i40e_common.c

1382

(reg | I40E_PFGEN_CTRL_PFSWR_MASK));

sys/dev/ixl/i40e_common.c

1384

reg = rd32(hw, I40E_PFGEN_CTRL);

sys/dev/ixl/i40e_common.c

1385

if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))

sys/dev/ixl/i40e_common.c

1395

} else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {

sys/dev/ixl/i40e_common.c

6433

u16 reg, u8 phy_addr, u16 *value)

sys/dev/ixl/i40e_common.c

6440

command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |

sys/dev/ixl/i40e_common.c

6478

u16 reg, u8 phy_addr, u16 value)

sys/dev/ixl/i40e_common.c

6488

command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |

sys/dev/ixl/i40e_common.c

6519

u8 page, u16 reg, u8 phy_addr, u16 *value)

sys/dev/ixl/i40e_common.c

6526

command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |

sys/dev/ixl/i40e_common.c

6593

u8 page, u16 reg, u8 phy_addr, u16 value)

sys/dev/ixl/i40e_common.c

6600

command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |

sys/dev/ixl/i40e_common.c

6660

u8 page, u16 reg, u8 phy_addr, u16 value)

sys/dev/ixl/i40e_common.c

6667

reg, phy_addr, value);

sys/dev/ixl/i40e_common.c

6678

page, reg, phy_addr, value);

sys/dev/ixl/i40e_common.c

6699

u8 page, u16 reg, u8 phy_addr, u16 *value)

sys/dev/ixl/i40e_common.c

6705

status = i40e_read_phy_register_clause22(hw, reg, phy_addr,

sys/dev/ixl/i40e_common.c

6716

status = i40e_read_phy_register_clause45(hw, page, reg,

sys/dev/ixl/i40e_dcb.c

47

u32 reg;

sys/dev/ixl/i40e_dcb.c

52

reg = rd32(hw, I40E_PRTDCB_GENS);

sys/dev/ixl/i40e_dcb.c

53

*status = (u16)((reg & I40E_PRTDCB_GENS_DCBX_STATUS_MASK) >>

sys/dev/ixl/i40e_osdep.c

246

i40e_read_pci_cfg(struct i40e_hw *hw, u32 reg)

sys/dev/ixl/i40e_osdep.c

251

reg, 2);

sys/dev/ixl/i40e_osdep.c

257

i40e_write_pci_cfg(struct i40e_hw *hw, u32 reg, u16 value)

sys/dev/ixl/i40e_osdep.c

260

reg, value, 2);

sys/dev/ixl/i40e_osdep.h

194

rd32_osdep(struct i40e_osdep *osdep, uint32_t reg)

sys/dev/ixl/i40e_osdep.h

197

KASSERT(reg < osdep->mem_bus_space_size,

sys/dev/ixl/i40e_osdep.h

199

(uintmax_t)reg, (uintmax_t)osdep->mem_bus_space_size));

sys/dev/ixl/i40e_osdep.h

202

osdep->mem_bus_space_handle, reg));

sys/dev/ixl/i40e_osdep.h

206

wr32_osdep(struct i40e_osdep *osdep, uint32_t reg, uint32_t value)

sys/dev/ixl/i40e_osdep.h

209

KASSERT(reg < osdep->mem_bus_space_size,

sys/dev/ixl/i40e_osdep.h

211

(uintmax_t)reg, (uintmax_t)osdep->mem_bus_space_size));

sys/dev/ixl/i40e_osdep.h

214

osdep->mem_bus_space_handle, reg, value);

sys/dev/ixl/i40e_osdep.h

223

#define rd32(a, reg) rd32_osdep((a)->back, (reg))

sys/dev/ixl/i40e_osdep.h

224

#define wr32(a, reg, value) wr32_osdep((a)->back, (reg), (value))

sys/dev/ixl/i40e_osdep.h

226

#define rd64(a, reg) (\

sys/dev/ixl/i40e_osdep.h

229

reg))

sys/dev/ixl/i40e_osdep.h

231

#define wr64(a, reg, value) (\

sys/dev/ixl/i40e_osdep.h

234

reg, value))

sys/dev/ixl/i40e_prototype.h

625

u16 reg, u8 phy_addr, u16 *value);

sys/dev/ixl/i40e_prototype.h

627

u16 reg, u8 phy_addr, u16 value);

sys/dev/ixl/i40e_prototype.h

629

u8 page, u16 reg, u8 phy_addr, u16 *value);

sys/dev/ixl/i40e_prototype.h

631

u8 page, u16 reg, u8 phy_addr, u16 value);

sys/dev/ixl/i40e_prototype.h

633

u8 page, u16 reg, u8 phy_addr, u16 *value);

sys/dev/ixl/i40e_prototype.h

635

u8 page, u16 reg, u8 phy_addr, u16 value);

sys/dev/ixl/if_ixl.c

1394

u32 loop = 0, reg;

sys/dev/ixl/if_ixl.c

1436

reg = rd32(hw, I40E_PFINT_ICR0_ENA);

sys/dev/ixl/if_ixl.c

1437

reg |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;

sys/dev/ixl/if_ixl.c

1438

wr32(hw, I40E_PFINT_ICR0_ENA, reg);

sys/dev/ixl/ixl_iw.c

328

u32 reg;

sys/dev/ixl/ixl_iw.c

339

reg = I40E_PFINT_AEQCTL_CAUSE_ENA_MASK |

sys/dev/ixl/ixl_iw.c

342

wr32(hw, I40E_PFINT_AEQCTL, reg);

sys/dev/ixl/ixl_iw.c

350

reg = I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK;

sys/dev/ixl/ixl_iw.c

351

wr32(hw, I40E_PFINT_LNKLSTN(vec - 1), reg);

sys/dev/ixl/ixl_iw.c

353

reg = (i & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) |

sys/dev/ixl/ixl_iw.c

356

wr32(hw, I40E_PFINT_LNKLSTN(vec - 1), reg);

sys/dev/ixl/ixl_iw.c

358

reg = I40E_PFINT_CEQCTL_CAUSE_ENA_MASK |

sys/dev/ixl/ixl_iw.c

364

wr32(hw, I40E_PFINT_CEQCTL(i), reg);

sys/dev/ixl/ixl_iw.c

54

u32 reg;

sys/dev/ixl/ixl_iw.c

58

reg = I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK;

sys/dev/ixl/ixl_iw.c

59

wr32(hw, I40E_PFINT_LNKLSTN(vec - 1), reg);

sys/dev/ixl/ixl_pf_i2c.c

615

u32 reg = 0;

sys/dev/ixl/ixl_pf_i2c.c

619

reg |= (byte_offset << I40E_GLGEN_I2CCMD_REGADD_SHIFT);

sys/dev/ixl/ixl_pf_i2c.c

620

reg |= (((dev_addr >> 1) & 0x7) << I40E_GLGEN_I2CCMD_PHYADD_SHIFT);

sys/dev/ixl/ixl_pf_i2c.c

621

reg |= I40E_GLGEN_I2CCMD_OP_MASK;

sys/dev/ixl/ixl_pf_i2c.c

622

wr32(hw, I40E_GLGEN_I2CCMD(hw->func_caps.mdio_port_num), reg);

sys/dev/ixl/ixl_pf_i2c.c

627

reg = rd32(hw, I40E_GLGEN_I2CCMD(hw->func_caps.mdio_port_num));

sys/dev/ixl/ixl_pf_i2c.c

630

*data = (u8)(reg & 0xff);

sys/dev/ixl/ixl_pf_i2c.c

646

u32 reg = 0;

sys/dev/ixl/ixl_pf_i2c.c

652

reg = rd32(hw, I40E_GLGEN_I2CCMD(hw->func_caps.mdio_port_num));

sys/dev/ixl/ixl_pf_i2c.c

655

reg &= ~I40E_GLGEN_I2CCMD_PHYADD_MASK;

sys/dev/ixl/ixl_pf_i2c.c

656

reg |= (((dev_addr >> 1) & 0x7) << I40E_GLGEN_I2CCMD_PHYADD_SHIFT);

sys/dev/ixl/ixl_pf_i2c.c

657

reg &= ~I40E_GLGEN_I2CCMD_REGADD_MASK;

sys/dev/ixl/ixl_pf_i2c.c

658

reg |= (byte_offset << I40E_GLGEN_I2CCMD_REGADD_SHIFT);

sys/dev/ixl/ixl_pf_i2c.c

659

reg &= ~I40E_GLGEN_I2CCMD_DATA_MASK;

sys/dev/ixl/ixl_pf_i2c.c

660

reg |= (datai2c << I40E_GLGEN_I2CCMD_DATA_SHIFT);

sys/dev/ixl/ixl_pf_i2c.c

661

reg &= ~I40E_GLGEN_I2CCMD_OP_MASK;

sys/dev/ixl/ixl_pf_i2c.c

664

wr32(hw, I40E_GLGEN_I2CCMD(hw->func_caps.mdio_port_num), reg);

sys/dev/ixl/ixl_pf_i2c.c

681

u32 reg;

sys/dev/ixl/ixl_pf_i2c.c

683

reg = rd32(hw, I40E_GLGEN_I2CCMD(portnum));

sys/dev/ixl/ixl_pf_i2c.c

684

if ((reg & I40E_GLGEN_I2CCMD_R_MASK) != 0)

sys/dev/ixl/ixl_pf_i2c.c

704

u32 reg;

sys/dev/ixl/ixl_pf_i2c.c

710

&reg, NULL);

sys/dev/ixl/ixl_pf_i2c.c

716

*data = (u8)reg;

sys/dev/ixl/ixl_pf_iflib.c

138

u32 reg, mask, rstat_reg;

sys/dev/ixl/ixl_pf_iflib.c

145

reg = rd32(hw, I40E_PFINT_ICR0);

sys/dev/ixl/ixl_pf_iflib.c

153

if (reg & I40E_PFINT_ICR0_ADMINQ_MASK) {

sys/dev/ixl/ixl_pf_iflib.c

158

if (reg & I40E_PFINT_ICR0_MAL_DETECT_MASK) {

sys/dev/ixl/ixl_pf_iflib.c

164

if (reg & I40E_PFINT_ICR0_GRST_MASK) {

sys/dev/ixl/ixl_pf_iflib.c

195

if (reg & I40E_PFINT_ICR0_ECC_ERR_MASK)

sys/dev/ixl/ixl_pf_iflib.c

197

if (reg & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)

sys/dev/ixl/ixl_pf_iflib.c

199

if (reg & I40E_PFINT_ICR0_PE_CRITERR_MASK)

sys/dev/ixl/ixl_pf_iflib.c

202

if (reg & IXL_ICR0_CRIT_ERR_MASK) {

sys/dev/ixl/ixl_pf_iflib.c

209

if (reg & I40E_PFINT_ICR0_HMC_ERR_MASK) {

sys/dev/ixl/ixl_pf_iflib.c

210

reg = rd32(hw, I40E_PFHMC_ERRORINFO);

sys/dev/ixl/ixl_pf_iflib.c

211

if (reg & I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK) {

sys/dev/ixl/ixl_pf_iflib.c

213

device_printf(dev, "INFO 0x%08x\n", reg);

sys/dev/ixl/ixl_pf_iflib.c

214

reg = rd32(hw, I40E_PFHMC_ERRORDATA);

sys/dev/ixl/ixl_pf_iflib.c

215

device_printf(dev, "DATA 0x%08x\n", reg);

sys/dev/ixl/ixl_pf_iflib.c

221

if (reg & I40E_PFINT_ICR0_VFLR_MASK) {

sys/dev/ixl/ixl_pf_iflib.c

246

u32 reg;

sys/dev/ixl/ixl_pf_iflib.c

254

reg = ((i << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT)

sys/dev/ixl/ixl_pf_iflib.c

258

wr32(hw, I40E_PFINT_LNKLSTN(i), reg);

sys/dev/ixl/ixl_pf_iflib.c

260

reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK |

sys/dev/ixl/ixl_pf_iflib.c

265

wr32(hw, I40E_QINT_RQCTL(i), reg);

sys/dev/ixl/ixl_pf_iflib.c

267

reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK |

sys/dev/ixl/ixl_pf_iflib.c

272

wr32(hw, I40E_QINT_TQCTL(i), reg);

sys/dev/ixl/ixl_pf_iflib.c

284

u32 reg;

sys/dev/ixl/ixl_pf_iflib.c

289

reg = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK

sys/dev/ixl/ixl_pf_iflib.c

298

wr32(hw, I40E_PFINT_ICR0_ENA, reg);

sys/dev/ixl/ixl_pf_iflib.c

308

reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK

sys/dev/ixl/ixl_pf_iflib.c

311

wr32(hw, I40E_QINT_RQCTL(0), reg);

sys/dev/ixl/ixl_pf_iflib.c

313

reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK

sys/dev/ixl/ixl_pf_iflib.c

316

wr32(hw, I40E_QINT_TQCTL(0), reg);

sys/dev/ixl/ixl_pf_main.c

1673

u32 reg;

sys/dev/ixl/ixl_pf_main.c

1684

reg = rd32(hw, I40E_QTX_ENA(pf_qidx));

sys/dev/ixl/ixl_pf_main.c

1685

reg |= I40E_QTX_ENA_QENA_REQ_MASK |

sys/dev/ixl/ixl_pf_main.c

1687

wr32(hw, I40E_QTX_ENA(pf_qidx), reg);

sys/dev/ixl/ixl_pf_main.c

1690

reg = rd32(hw, I40E_QTX_ENA(pf_qidx));

sys/dev/ixl/ixl_pf_main.c

1691

if (reg & I40E_QTX_ENA_QENA_STAT_MASK)

sys/dev/ixl/ixl_pf_main.c

1695

if ((reg & I40E_QTX_ENA_QENA_STAT_MASK) == 0) {

sys/dev/ixl/ixl_pf_main.c

1709

u32 reg;

sys/dev/ixl/ixl_pf_main.c

1718

reg = rd32(hw, I40E_QRX_ENA(pf_qidx));

sys/dev/ixl/ixl_pf_main.c

1719

reg |= I40E_QRX_ENA_QENA_REQ_MASK |

sys/dev/ixl/ixl_pf_main.c

1721

wr32(hw, I40E_QRX_ENA(pf_qidx), reg);

sys/dev/ixl/ixl_pf_main.c

1724

reg = rd32(hw, I40E_QRX_ENA(pf_qidx));

sys/dev/ixl/ixl_pf_main.c

1725

if (reg & I40E_QRX_ENA_QENA_STAT_MASK)

sys/dev/ixl/ixl_pf_main.c

1729

if ((reg & I40E_QRX_ENA_QENA_STAT_MASK) == 0) {

sys/dev/ixl/ixl_pf_main.c

1759

u32 reg;

sys/dev/ixl/ixl_pf_main.c

1771

reg = rd32(hw, I40E_QTX_ENA(pf_qidx));

sys/dev/ixl/ixl_pf_main.c

1772

reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;

sys/dev/ixl/ixl_pf_main.c

1773

wr32(hw, I40E_QTX_ENA(pf_qidx), reg);

sys/dev/ixl/ixl_pf_main.c

1776

reg = rd32(hw, I40E_QTX_ENA(pf_qidx));

sys/dev/ixl/ixl_pf_main.c

1777

if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))

sys/dev/ixl/ixl_pf_main.c

1781

if (reg & I40E_QTX_ENA_QENA_STAT_MASK) {

sys/dev/ixl/ixl_pf_main.c

1798

u32 reg;

sys/dev/ixl/ixl_pf_main.c

1807

reg = rd32(hw, I40E_QRX_ENA(pf_qidx));

sys/dev/ixl/ixl_pf_main.c

1808

reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;

sys/dev/ixl/ixl_pf_main.c

1809

wr32(hw, I40E_QRX_ENA(pf_qidx), reg);

sys/dev/ixl/ixl_pf_main.c

1812

reg = rd32(hw, I40E_QRX_ENA(pf_qidx));

sys/dev/ixl/ixl_pf_main.c

1813

if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))

sys/dev/ixl/ixl_pf_main.c

1817

if (reg & I40E_QRX_ENA_QENA_STAT_MASK) {

sys/dev/ixl/ixl_pf_main.c

1851

u32 reg;

sys/dev/ixl/ixl_pf_main.c

1854

reg = rd32(hw, I40E_GL_MDET_TX);

sys/dev/ixl/ixl_pf_main.c

1855

if (reg & I40E_GL_MDET_TX_VALID_MASK) {

sys/dev/ixl/ixl_pf_main.c

1856

pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>

sys/dev/ixl/ixl_pf_main.c

1858

vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>

sys/dev/ixl/ixl_pf_main.c

1860

event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>

sys/dev/ixl/ixl_pf_main.c

1862

queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >>

sys/dev/ixl/ixl_pf_main.c

1871

reg = rd32(hw, I40E_PF_MDET_TX);

sys/dev/ixl/ixl_pf_main.c

1872

if (reg & I40E_PF_MDET_TX_VALID_MASK) {

sys/dev/ixl/ixl_pf_main.c

1881

reg = rd32(hw, I40E_VP_MDET_TX(i));

sys/dev/ixl/ixl_pf_main.c

1882

if (reg & I40E_VP_MDET_TX_VALID_MASK) {

sys/dev/ixl/ixl_pf_main.c

1924

u32 reg;

sys/dev/ixl/ixl_pf_main.c

1930

reg = rd32(hw, I40E_GL_MDET_RX);

sys/dev/ixl/ixl_pf_main.c

1931

if (reg & I40E_GL_MDET_RX_VALID_MASK) {

sys/dev/ixl/ixl_pf_main.c

1932

pf_num = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>

sys/dev/ixl/ixl_pf_main.c

1934

event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>

sys/dev/ixl/ixl_pf_main.c

1936

queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >>

sys/dev/ixl/ixl_pf_main.c

1945

reg = rd32(hw, I40E_PF_MDET_RX);

sys/dev/ixl/ixl_pf_main.c

1946

if (reg & I40E_PF_MDET_RX_VALID_MASK) {

sys/dev/ixl/ixl_pf_main.c

1955

reg = rd32(hw, I40E_VP_MDET_RX(i));

sys/dev/ixl/ixl_pf_main.c

1956

if (reg & I40E_VP_MDET_RX_VALID_MASK) {

sys/dev/ixl/ixl_pf_main.c

1996

u32 reg;

sys/dev/ixl/ixl_pf_main.c

2008

reg = rd32(hw, I40E_PFINT_ICR0_ENA);

sys/dev/ixl/ixl_pf_main.c

2009

reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;

sys/dev/ixl/ixl_pf_main.c

2010

wr32(hw, I40E_PFINT_ICR0_ENA, reg);

sys/dev/ixl/ixl_pf_main.c

2017

u32 reg;

sys/dev/ixl/ixl_pf_main.c

2020

reg = I40E_PFINT_DYN_CTL0_INTENA_MASK |

sys/dev/ixl/ixl_pf_main.c

2023

wr32(hw, I40E_PFINT_DYN_CTL0, reg);

sys/dev/ixl/ixl_pf_main.c

2029

u32 reg;

sys/dev/ixl/ixl_pf_main.c

2031

reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT;

sys/dev/ixl/ixl_pf_main.c

2032

wr32(hw, I40E_PFINT_DYN_CTL0, reg);

sys/dev/ixl/ixl_pf_main.c

2039

u32 reg;

sys/dev/ixl/ixl_pf_main.c

2041

reg = I40E_PFINT_DYN_CTLN_INTENA_MASK |

sys/dev/ixl/ixl_pf_main.c

2044

wr32(hw, I40E_PFINT_DYN_CTLN(id), reg);

sys/dev/ixl/ixl_pf_main.c

2050

u32 reg;

sys/dev/ixl/ixl_pf_main.c

2052

reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;

sys/dev/ixl/ixl_pf_main.c

2053

wr32(hw, I40E_PFINT_DYN_CTLN(id), reg);

sys/dev/ixl/ixl_pf_main.c

2401

_ixl_stat_update_helper(struct i40e_hw *hw, u32 reg,

sys/dev/ixl/ixl_pf_main.c

2404

u64 new_data = rd64(hw, reg);

sys/dev/ixl/ixl_pf_main.c

2419

ixl_stat_update48(struct i40e_hw *hw, u32 reg,

sys/dev/ixl/ixl_pf_main.c

2423

reg,

sys/dev/ixl/ixl_pf_main.c

2434

ixl_stat_update64(struct i40e_hw *hw, u32 reg,

sys/dev/ixl/ixl_pf_main.c

2438

reg,

sys/dev/ixl/ixl_pf_main.c

2449

ixl_stat_update32(struct i40e_hw *hw, u32 reg,

sys/dev/ixl/ixl_pf_main.c

2454

new_data = rd32(hw, reg);

sys/dev/ixl/ixl_pf_main.c

3273

u32 reg;

sys/dev/ixl/ixl_pf_main.c

3276

reg = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(i));

sys/dev/ixl/ixl_pf_main.c

3277

i2c_en = (reg & I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK);

sys/dev/ixl/ixl_pf_main.c

3278

port_matched = ((reg & I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_MASK)

sys/dev/ixl/ixl_pf_main.c

4065

u32 reg;

sys/dev/ixl/ixl_pf_main.c

4085

reg = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));

sys/dev/ixl/ixl_pf_main.c

4086

bcopy(&reg, ((caddr_t)&key_data) + (i << 2), 4);

sys/dev/ixl/ixl_pf_main.c

4156

u32 reg;

sys/dev/ixl/ixl_pf_main.c

4173

reg = rd32(hw, I40E_PFQF_HLUT(i));

sys/dev/ixl/ixl_pf_main.c

4174

bcopy(&reg, &hlut[i << 2], 4);

sys/dev/ixl/ixl_pf_main.c

783

u32 reg;

sys/dev/ixl/ixl_pf_main.c

789

reg = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |

sys/dev/ixl/ixl_pf_main.c

797

wr32(hw, I40E_PFINT_ICR0_ENA, reg);

sys/dev/jedec_dimm/jedec_dimm.c

1053

jedec_dimm_readw_be(struct jedec_dimm_softc *sc, uint8_t reg, uint16_t *val)

sys/dev/jedec_dimm/jedec_dimm.c

1057

rc = smbus_readw(sc->smbus, sc->tsod_addr, reg, val);

sys/dev/jedec_dimm/jedec_dimm.c

165

static int jedec_dimm_readw_be(struct jedec_dimm_softc *sc, uint8_t reg,

sys/dev/jme/if_jme.c

1941

uint32_t reg;

sys/dev/jme/if_jme.c

2025

reg = CSR_READ_4(sc, JME_RXMAC);

sys/dev/jme/if_jme.c

2026

reg &= ~RXMAC_CSUM_ENB;

sys/dev/jme/if_jme.c

2028

reg |= RXMAC_CSUM_ENB;

sys/dev/jme/if_jme.c

2029

CSR_WRITE_4(sc, JME_RXMAC, reg);

sys/dev/jme/if_jme.c

212

jme_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/jme/if_jme.c

225

SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));

sys/dev/jme/if_jme.c

233

device_printf(sc->jme_dev, "phy read timeout : %d\n", reg);

sys/dev/jme/if_jme.c

244

jme_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/jme/if_jme.c

257

SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));

sys/dev/jme/if_jme.c

265

device_printf(sc->jme_dev, "phy write timeout : %d\n", reg);

sys/dev/jme/if_jme.c

2731

uint32_t reg;

sys/dev/jme/if_jme.c

2790

reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;

sys/dev/jme/if_jme.c

2791

reg |= TXMAC_THRESH_1_PKT;

sys/dev/jme/if_jme.c

2792

reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;

sys/dev/jme/if_jme.c

2793

CSR_WRITE_4(sc, JME_TXMAC, reg);

sys/dev/jme/if_jme.c

2848

reg = CSR_READ_4(sc, JME_PMCS);

sys/dev/jme/if_jme.c

2849

reg &= ~PMCS_WOL_ENB_MASK;

sys/dev/jme/if_jme.c

2850

CSR_WRITE_4(sc, JME_PMCS, reg);

sys/dev/jme/if_jme.c

2852

reg = CSR_READ_4(sc, JME_RXMAC);

sys/dev/jme/if_jme.c

2858

reg |= RXMAC_PAD_10BYTES;

sys/dev/jme/if_jme.c

2860

reg |= RXMAC_CSUM_ENB;

sys/dev/jme/if_jme.c

2861

CSR_WRITE_4(sc, JME_RXMAC, reg);

sys/dev/jme/if_jme.c

2864

reg = CSR_READ_4(sc, JME_GPREG0);

sys/dev/jme/if_jme.c

2865

reg &= ~GPREG0_PCC_UNIT_MASK;

sys/dev/jme/if_jme.c

2867

reg |= GPREG0_PCC_UNIT_US;

sys/dev/jme/if_jme.c

2875

reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |

sys/dev/jme/if_jme.c

2880

reg &= ~GPREG0_POST_DW0_ENB;

sys/dev/jme/if_jme.c

2882

reg &= ~GPREG0_PME_ENB;

sys/dev/jme/if_jme.c

2884

reg &= ~GPREG0_PHY_ADDR_MASK;

sys/dev/jme/if_jme.c

2885

reg |= sc->jme_phyaddr;

sys/dev/jme/if_jme.c

2886

CSR_WRITE_4(sc, JME_GPREG0, reg);

sys/dev/jme/if_jme.c

2889

reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &

sys/dev/jme/if_jme.c

2891

reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &

sys/dev/jme/if_jme.c

2893

reg |= PCCTX_COAL_TXQ0;

sys/dev/jme/if_jme.c

2894

CSR_WRITE_4(sc, JME_PCCTX, reg);

sys/dev/jme/if_jme.c

2897

reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &

sys/dev/jme/if_jme.c

2899

reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &

sys/dev/jme/if_jme.c

2901

CSR_WRITE_4(sc, JME_PCCRX0, reg);

sys/dev/jme/if_jme.c

2919

reg = sc->jme_rx_pcd_to << PCDRX0_TO_THROTTLE_SHIFT;

sys/dev/jme/if_jme.c

2920

reg |= sc->jme_rx_pcd_to << PCDRX0_TO_SHIFT;

sys/dev/jme/if_jme.c

2921

CSR_WRITE_4(sc, PCDRX_REG(0), reg);

sys/dev/jme/if_jme.c

2922

reg = sc->jme_tx_pcd_to << PCDTX_TO_THROTTLE_SHIFT;

sys/dev/jme/if_jme.c

2923

reg |= sc->jme_tx_pcd_to << PCDTX_TO_SHIFT;

sys/dev/jme/if_jme.c

2924

CSR_WRITE_4(sc, JME_PCDTX, reg);

sys/dev/jme/if_jme.c

3036

uint32_t reg;

sys/dev/jme/if_jme.c

3039

reg = CSR_READ_4(sc, JME_TXCSR);

sys/dev/jme/if_jme.c

3040

if ((reg & TXCSR_TX_ENB) == 0)

sys/dev/jme/if_jme.c

3042

reg &= ~TXCSR_TX_ENB;

sys/dev/jme/if_jme.c

3043

CSR_WRITE_4(sc, JME_TXCSR, reg);

sys/dev/jme/if_jme.c

3056

uint32_t reg;

sys/dev/jme/if_jme.c

3059

reg = CSR_READ_4(sc, JME_RXCSR);

sys/dev/jme/if_jme.c

3060

if ((reg & RXCSR_RX_ENB) == 0)

sys/dev/jme/if_jme.c

3062

reg &= ~RXCSR_RX_ENB;

sys/dev/jme/if_jme.c

3063

CSR_WRITE_4(sc, JME_RXCSR, reg);

sys/dev/jme/if_jme.c

3189

uint32_t reg;

sys/dev/jme/if_jme.c

3194

reg = CSR_READ_4(sc, JME_RXMAC);

sys/dev/jme/if_jme.c

3195

reg &= ~RXMAC_VLAN_ENB;

sys/dev/jme/if_jme.c

3197

reg |= RXMAC_VLAN_ENB;

sys/dev/jme/if_jme.c

3198

CSR_WRITE_4(sc, JME_RXMAC, reg);

sys/dev/jme/if_jme.c

3297

uint32_t reg;

sys/dev/jme/if_jme.c

3307

reg = CSR_READ_4(sc, JME_STAT_CRCMII);

sys/dev/jme/if_jme.c

3308

stat->rx_crc_errs = (reg & STAT_RX_CRC_ERR_MASK) >>

sys/dev/jme/if_jme.c

3310

stat->rx_mii_errs = (reg & STAT_RX_MII_ERR_MASK) >>

sys/dev/jme/if_jme.c

3312

reg = CSR_READ_4(sc, JME_STAT_RXERR);

sys/dev/jme/if_jme.c

3313

stat->rx_fifo_oflows = (reg & STAT_RXERR_OFLOW_MASK) >>

sys/dev/jme/if_jme.c

3315

stat->rx_desc_empty = (reg & STAT_RXERR_MPTY_MASK) >>

sys/dev/jme/if_jme.c

3317

reg = CSR_READ_4(sc, JME_STAT_FAIL);

sys/dev/jme/if_jme.c

3318

stat->rx_bad_frames = (reg & STAT_FAIL_RX_MASK) >> STAT_FAIL_RX_SHIFT;

sys/dev/jme/if_jme.c

3319

stat->tx_bad_frames = (reg & STAT_FAIL_TX_MASK) >> STAT_FAIL_TX_SHIFT;

sys/dev/jme/if_jme.c

3335

uint32_t reg;

sys/dev/jme/if_jme.c

3339

reg = CSR_READ_4(sc, JME_PHYPOWDN);

sys/dev/jme/if_jme.c

3340

reg |= 0x0000000F;

sys/dev/jme/if_jme.c

3341

CSR_WRITE_4(sc, JME_PHYPOWDN, reg);

sys/dev/jme/if_jme.c

3342

reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4);

sys/dev/jme/if_jme.c

3343

reg &= ~PE1_GIGA_PDOWN_MASK;

sys/dev/jme/if_jme.c

3344

reg |= PE1_GIGA_PDOWN_D3;

sys/dev/jme/if_jme.c

3345

pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4);

sys/dev/jme/if_jme.c

3352

uint32_t reg;

sys/dev/jme/if_jme.c

3359

reg = CSR_READ_4(sc, JME_PHYPOWDN);

sys/dev/jme/if_jme.c

3360

reg &= ~0x0000000F;

sys/dev/jme/if_jme.c

3361

CSR_WRITE_4(sc, JME_PHYPOWDN, reg);

sys/dev/jme/if_jme.c

3362

reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4);

sys/dev/jme/if_jme.c

3363

reg &= ~PE1_GIGA_PDOWN_MASK;

sys/dev/jme/if_jme.c

3364

reg |= PE1_GIGA_PDOWN_DIS;

sys/dev/jme/if_jme.c

3365

pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4);

sys/dev/jme/if_jme.c

351

uint32_t reg;

sys/dev/jme/if_jme.c

356

reg = CSR_READ_4(sc, JME_SMBCSR);

sys/dev/jme/if_jme.c

357

if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)

sys/dev/jme/if_jme.c

367

reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;

sys/dev/jme/if_jme.c

368

CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);

sys/dev/jme/if_jme.c

371

reg = CSR_READ_4(sc, JME_SMBINTF);

sys/dev/jme/if_jme.c

372

if ((reg & SMBINTF_CMD_TRIGGER) == 0)

sys/dev/jme/if_jme.c

381

reg = CSR_READ_4(sc, JME_SMBINTF);

sys/dev/jme/if_jme.c

382

*val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;

sys/dev/jme/if_jme.c

391

uint8_t fup, reg, val;

sys/dev/jme/if_jme.c

408

if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)

sys/dev/jme/if_jme.c

410

if (reg >= JME_PAR0 &&

sys/dev/jme/if_jme.c

411

reg < JME_PAR0 + ETHER_ADDR_LEN) {

sys/dev/jme/if_jme.c

415

eaddr[reg - JME_PAR0] = val;

sys/dev/jme/if_jme.c

437

uint32_t reg;

sys/dev/jme/if_jme.c

440

reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);

sys/dev/jme/if_jme.c

441

if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR | EFUSE_CTL1_AUTOLAOD_DONE)) !=

sys/dev/jme/if_jme.c

445

reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4);

sys/dev/jme/if_jme.c

446

reg |= EFUSE_CTL2_RESET;

sys/dev/jme/if_jme.c

447

pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4);

sys/dev/jme/if_jme.c

448

reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4);

sys/dev/jme/if_jme.c

449

reg &= ~EFUSE_CTL2_RESET;

sys/dev/jme/if_jme.c

450

pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4);

sys/dev/jme/if_jme.c

453

reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);

sys/dev/jme/if_jme.c

454

reg &= ~EFUSE_CTL1_CMD_MASK;

sys/dev/jme/if_jme.c

455

reg |= EFUSE_CTL1_CMD_AUTOLOAD | EFUSE_CTL1_EXECUTE;

sys/dev/jme/if_jme.c

456

pci_write_config(sc->jme_dev, JME_EFUSE_CTL1, reg, 4);

sys/dev/jme/if_jme.c

464

reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);

sys/dev/jme/if_jme.c

465

if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR |

sys/dev/jme/if_jme.c

470

if ((reg & EFUSE_CTL1_EXECUTE) == 0)

sys/dev/jme/if_jme.c

626

uint32_t reg;

sys/dev/jme/if_jme.c

708

reg = CSR_READ_4(sc, JME_CHIPMODE);

sys/dev/jme/if_jme.c

709

sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT;

sys/dev/jme/if_jme.c

710

if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=

sys/dev/jme/if_jme.c

720

(reg & CHIPMODE_FPGA_REV_MASK) >>

sys/dev/jme/if_jme.c

751

reg = CSR_READ_4(sc, JME_SMBCSR);

sys/dev/jme/if_jme.c

752

if ((reg & SMBCSR_EEPROM_PRESENT) != 0)

sys/dev/jme/if_jmevar.h

229

#define CSR_WRITE_4(_sc, reg, val) \

sys/dev/jme/if_jmevar.h

230

bus_write_4((_sc)->jme_res[0], (reg), (val))

sys/dev/jme/if_jmevar.h

231

#define CSR_READ_4(_sc, reg) \

sys/dev/jme/if_jmevar.h

232

bus_read_4((_sc)->jme_res[0], (reg))

sys/dev/lge/if_lge.c

194

#define LGE_SETBIT(sc, reg, x) \

sys/dev/lge/if_lge.c

195

CSR_WRITE_4(sc, reg, \

sys/dev/lge/if_lge.c

196

CSR_READ_4(sc, reg) | (x))

sys/dev/lge/if_lge.c

198

#define LGE_CLRBIT(sc, reg, x) \

sys/dev/lge/if_lge.c

199

CSR_WRITE_4(sc, reg, \

sys/dev/lge/if_lge.c

200

CSR_READ_4(sc, reg) & ~(x))

sys/dev/lge/if_lge.c

261

lge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/lge/if_lge.c

276

CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);

sys/dev/lge/if_lge.c

291

lge_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/lge/if_lge.c

299

(data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);

sys/dev/lge/if_lgereg.h

532

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/lge/if_lgereg.h

533

bus_space_write_4(sc->lge_btag, sc->lge_bhandle, reg, val)

sys/dev/lge/if_lgereg.h

535

#define CSR_READ_2(sc, reg) \

sys/dev/lge/if_lgereg.h

536

bus_space_read_2(sc->lge_btag, sc->lge_bhandle, reg)

sys/dev/lge/if_lgereg.h

538

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/lge/if_lgereg.h

539

bus_space_write_2(sc->lge_btag, sc->lge_bhandle, reg, val)

sys/dev/lge/if_lgereg.h

541

#define CSR_READ_4(sc, reg) \

sys/dev/lge/if_lgereg.h

542

bus_space_read_4(sc->lge_btag, sc->lge_bhandle, reg)

sys/dev/lge/if_lgereg.h

544

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/lge/if_lgereg.h

545

bus_space_write_1(sc->lge_btag, sc->lge_bhandle, reg, val)

sys/dev/lge/if_lgereg.h

547

#define CSR_READ_1(sc, reg) \

sys/dev/lge/if_lgereg.h

548

bus_space_read_1(sc->lge_btag, sc->lge_bhandle, reg)

sys/dev/liquidio/base/lio_device.h

810

lio_read_pci_cfg(struct octeon_device *oct, uint32_t reg)

sys/dev/liquidio/base/lio_device.h

813

return (pci_read_config(oct->device, reg, 4));

sys/dev/liquidio/base/lio_device.h

817

lio_write_pci_cfg(struct octeon_device *oct, uint32_t reg, uint32_t value)

sys/dev/liquidio/base/lio_device.h

820

pci_write_config(oct->device, reg, value, 4);

sys/dev/liquidio/base/lio_device.h

824

lio_read_csr8(struct octeon_device *oct, uint32_t reg)

sys/dev/liquidio/base/lio_device.h

828

oct->mem_bus_space[0].handle, reg));

sys/dev/liquidio/base/lio_device.h

832

lio_write_csr8(struct octeon_device *oct, uint32_t reg, uint8_t val)

sys/dev/liquidio/base/lio_device.h

836

oct->mem_bus_space[0].handle, reg, val);

sys/dev/liquidio/base/lio_device.h

840

lio_read_csr16(struct octeon_device *oct, uint32_t reg)

sys/dev/liquidio/base/lio_device.h

844

oct->mem_bus_space[0].handle, reg));

sys/dev/liquidio/base/lio_device.h

848

lio_write_csr16(struct octeon_device *oct, uint32_t reg, uint16_t val)

sys/dev/liquidio/base/lio_device.h

852

oct->mem_bus_space[0].handle, reg, val);

sys/dev/liquidio/base/lio_device.h

856

lio_read_csr32(struct octeon_device *oct, uint32_t reg)

sys/dev/liquidio/base/lio_device.h

860

oct->mem_bus_space[0].handle, reg));

sys/dev/liquidio/base/lio_device.h

864

lio_write_csr32(struct octeon_device *oct, uint32_t reg, uint32_t val)

sys/dev/liquidio/base/lio_device.h

868

oct->mem_bus_space[0].handle, reg, val);

sys/dev/liquidio/base/lio_device.h

872

lio_read_csr64(struct octeon_device *oct, uint32_t reg)

sys/dev/liquidio/base/lio_device.h

876

return (lio_read_csr32(oct, reg) |

sys/dev/liquidio/base/lio_device.h

877

((uint64_t)lio_read_csr32(oct, reg + 4) << 32));

sys/dev/liquidio/base/lio_device.h

880

oct->mem_bus_space[0].handle, reg));

sys/dev/liquidio/base/lio_device.h

885

lio_write_csr64(struct octeon_device *oct, uint32_t reg, uint64_t val)

sys/dev/liquidio/base/lio_device.h

889

lio_write_csr32(oct, reg, (uint32_t)val);

sys/dev/liquidio/base/lio_device.h

890

lio_write_csr32(oct, reg + 4, val >> 32);

sys/dev/liquidio/base/lio_device.h

893

oct->mem_bus_space[0].handle, reg, val);

sys/dev/liquidio/base/lio_mem_ops.c

103

lio_write_bar1_mem32(oct, reg, (uint32_t)val);

sys/dev/liquidio/base/lio_mem_ops.c

104

lio_write_bar1_mem32(oct, reg + 4, val >> 32);

sys/dev/liquidio/base/lio_mem_ops.c

107

oct->mem_bus_space[1].handle, reg, val);

sys/dev/liquidio/base/lio_mem_ops.c

137

lio_read_bar1_mem8(struct octeon_device *oct, uint32_t reg)

sys/dev/liquidio/base/lio_mem_ops.c

141

oct->mem_bus_space[1].handle, reg));

sys/dev/liquidio/base/lio_mem_ops.c

60

lio_write_bar1_mem8(struct octeon_device *oct, uint32_t reg, uint64_t val)

sys/dev/liquidio/base/lio_mem_ops.c

64

oct->mem_bus_space[1].handle, reg, val);

sys/dev/liquidio/base/lio_mem_ops.c

69

lio_read_bar1_mem32(struct octeon_device *oct, uint32_t reg)

sys/dev/liquidio/base/lio_mem_ops.c

73

oct->mem_bus_space[1].handle, reg));

sys/dev/liquidio/base/lio_mem_ops.c

77

lio_write_bar1_mem32(struct octeon_device *oct, uint32_t reg, uint32_t val)

sys/dev/liquidio/base/lio_mem_ops.c

81

oct->mem_bus_space[1].handle, reg, val);

sys/dev/liquidio/base/lio_mem_ops.c

86

lio_read_bar1_mem64(struct octeon_device *oct, uint32_t reg)

sys/dev/liquidio/base/lio_mem_ops.c

90

return (lio_read_bar1_mem32(oct, reg) |

sys/dev/liquidio/base/lio_mem_ops.c

91

((uint64_t)lio_read_bar1_mem32(oct, reg + 4) << 32));

sys/dev/liquidio/base/lio_mem_ops.c

94

oct->mem_bus_space[1].handle, reg));

sys/dev/liquidio/base/lio_mem_ops.c

99

lio_write_bar1_mem64(struct octeon_device *oct, uint32_t reg, uint64_t val)

sys/dev/liquidio/lio_sysctl.c

765

uint32_t reg;

sys/dev/liquidio/lio_sysctl.c

774

reg = LIO_CN23XX_SLI_PKT_MAC_RINFO64(oct->pcie_port, oct->pf_num);

sys/dev/liquidio/lio_sysctl.c

776

reg, oct->pcie_port, oct->pf_num,

sys/dev/liquidio/lio_sysctl.c

777

LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

780

reg = LIO_CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num);

sys/dev/liquidio/lio_sysctl.c

782

reg, oct->pcie_port, oct->pf_num,

sys/dev/liquidio/lio_sysctl.c

783

LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

786

reg = LIO_CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num);

sys/dev/liquidio/lio_sysctl.c

788

reg, oct->pcie_port, oct->pf_num,

sys/dev/liquidio/lio_sysctl.c

789

LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

792

reg = 0x29120;

sys/dev/liquidio/lio_sysctl.c

793

len += sprintf(s + len, "[%08x] (SLI_PKT_MEM_CTL): %016llx\n", reg,

sys/dev/liquidio/lio_sysctl.c

794

LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

797

reg = 0x27300 + oct->pcie_port * LIO_CN23XX_MAC_INT_OFFSET +

sys/dev/liquidio/lio_sysctl.c

800

reg, oct->pcie_port, oct->pf_num,

sys/dev/liquidio/lio_sysctl.c

801

LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

804

reg = 0x27200 + oct->pcie_port * LIO_CN23XX_MAC_INT_OFFSET +

sys/dev/liquidio/lio_sysctl.c

807

reg, oct->pcie_port, oct->pf_num,

sys/dev/liquidio/lio_sysctl.c

808

LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

811

reg = LIO_CN23XX_SLI_PKT_CNT_INT;

sys/dev/liquidio/lio_sysctl.c

812

len += sprintf(s + len, "[%08x] (SLI_PKT_CNT_INT): %016llx\n", reg,

sys/dev/liquidio/lio_sysctl.c

813

LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

816

reg = LIO_CN23XX_SLI_PKT_TIME_INT;

sys/dev/liquidio/lio_sysctl.c

817

len += sprintf(s + len, "[%08x] (SLI_PKT_TIME_INT): %016llx\n", reg,

sys/dev/liquidio/lio_sysctl.c

818

LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

821

reg = 0x29160;

sys/dev/liquidio/lio_sysctl.c

822

len += sprintf(s + len, "[%08x] (SLI_PKT_INT): %016llx\n", reg,

sys/dev/liquidio/lio_sysctl.c

823

LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

826

reg = LIO_CN23XX_SLI_OQ_WMARK;

sys/dev/liquidio/lio_sysctl.c

828

reg, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

831

reg = LIO_CN23XX_SLI_PKT_IOQ_RING_RST;

sys/dev/liquidio/lio_sysctl.c

832

len += sprintf(s + len, "[%08x] (SLI_PKT_RING_RST): %016llx\n", reg,

sys/dev/liquidio/lio_sysctl.c

833

LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

836

reg = LIO_CN23XX_SLI_GBL_CONTROL;

sys/dev/liquidio/lio_sysctl.c

837

len += sprintf(s + len, "[%08x] (SLI_PKT_GBL_CONTROL): %016llx\n", reg,

sys/dev/liquidio/lio_sysctl.c

838

LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

841

reg = 0x29220;

sys/dev/liquidio/lio_sysctl.c

843

reg, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

848

reg = LIO_CN23XX_SLI_OUT_BP_EN_W1S;

sys/dev/liquidio/lio_sysctl.c

850

reg, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

853

reg = LIO_CN23XX_SLI_OUT_BP_EN2_W1S;

sys/dev/liquidio/lio_sysctl.c

855

reg, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

859

reg = LIO_CN23XX_SLI_OQ_BUFF_INFO_SIZE(i);

sys/dev/liquidio/lio_sysctl.c

861

reg, i, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

866

reg = LIO_CN23XX_SLI_IQ_INSTR_COUNT64(i);

sys/dev/liquidio/lio_sysctl.c

868

reg, i, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

873

reg = LIO_CN23XX_SLI_OQ_PKTS_CREDIT(i);

sys/dev/liquidio/lio_sysctl.c

875

reg, i, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

880

reg = LIO_CN23XX_SLI_OQ_SIZE(i);

sys/dev/liquidio/lio_sysctl.c

882

reg, i, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

887

reg = LIO_CN23XX_SLI_OQ_PKT_CONTROL(i);

sys/dev/liquidio/lio_sysctl.c

889

reg, i, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

894

reg = LIO_CN23XX_SLI_OQ_BASE_ADDR64(i);

sys/dev/liquidio/lio_sysctl.c

896

reg, i, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

901

reg = LIO_CN23XX_SLI_OQ_PKT_INT_LEVELS(i);

sys/dev/liquidio/lio_sysctl.c

903

reg, i, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

908

reg = LIO_CN23XX_SLI_OQ_PKTS_SENT(i);

sys/dev/liquidio/lio_sysctl.c

910

reg, i, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

915

reg = 0x100c0 + i * LIO_CN23XX_OQ_OFFSET;

sys/dev/liquidio/lio_sysctl.c

917

reg, i, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

922

reg = LIO_CN23XX_SLI_IQ_PKT_CONTROL64(i);

sys/dev/liquidio/lio_sysctl.c

924

reg, i, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

929

reg = LIO_CN23XX_SLI_IQ_BASE_ADDR64(i);

sys/dev/liquidio/lio_sysctl.c

931

reg, i, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

936

reg = LIO_CN23XX_SLI_IQ_DOORBELL(i);

sys/dev/liquidio/lio_sysctl.c

938

reg, i, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

943

reg = LIO_CN23XX_SLI_IQ_SIZE(i);

sys/dev/liquidio/lio_sysctl.c

945

reg, i, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/liquidio/lio_sysctl.c

950

reg = LIO_CN23XX_SLI_IQ_INSTR_COUNT64(i);

sys/dev/liquidio/lio_sysctl.c

952

reg, i, LIO_CAST64(lio_read_csr64(oct, reg)));

sys/dev/mailbox/arm/arm_doorbell.c

101

uint32_t reg;

sys/dev/mailbox/arm/arm_doorbell.c

106

reg = bus_read_4(sc->res[0], MHU_CHAN_RX_HP + MHU_INTR_STAT);

sys/dev/mailbox/arm/arm_doorbell.c

108

if (reg & (1 << i)) {

sys/dev/mailbox/arm/arm_doorbell.c

295

uint32_t reg;

sys/dev/mailbox/arm/arm_doorbell.c

313

reg = bus_read_4(sc->res[0], offset + MHU_INTR_STAT);

sys/dev/mailbox/arm/arm_doorbell.c

314

if (reg & (1 << db->db)) {

sys/dev/mailbox/arm/arm_doorbell.c

79

uint32_t reg;

sys/dev/mailbox/arm/arm_doorbell.c

84

reg = bus_read_4(sc->res[0], MHU_CHAN_RX_LP + MHU_INTR_STAT);

sys/dev/mailbox/arm/arm_doorbell.c

86

if (reg & (1 << i)) {

sys/dev/malo/if_malo_pci.c

152

int error = ENXIO, i, msic, reg;

sys/dev/malo/if_malo_pci.c

175

if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {

sys/dev/mdio/mdio.c

64

mdio_readreg(device_t dev, int phy, int reg)

sys/dev/mdio/mdio.c

67

return (MDIO_READREG(device_get_parent(dev), phy, reg));

sys/dev/mdio/mdio.c

71

mdio_writereg(device_t dev, int phy, int reg, int val)

sys/dev/mdio/mdio.c

74

return (MDIO_WRITEREG(device_get_parent(dev), phy, reg, val));

sys/dev/mdio/mdio.c

78

mdio_readextreg(device_t dev, int phy, int devad, int reg)

sys/dev/mdio/mdio.c

81

return (MDIO_READEXTREG(device_get_parent(dev), phy, devad, reg));

sys/dev/mdio/mdio.c

85

mdio_writeextreg(device_t dev, int phy, int devad, int reg,

sys/dev/mdio/mdio.c

89

return (MDIO_WRITEEXTREG(device_get_parent(dev), phy, devad, reg, val));

sys/dev/mfi/mfivar.h

594

#define MFI_WRITE4(sc, reg, val) bus_space_write_4((sc)->mfi_btag, \

sys/dev/mfi/mfivar.h

595

sc->mfi_bhandle, (reg), (val))

sys/dev/mfi/mfivar.h

596

#define MFI_READ4(sc, reg) bus_space_read_4((sc)->mfi_btag, \

sys/dev/mfi/mfivar.h

597

(sc)->mfi_bhandle, (reg))

sys/dev/mfi/mfivar.h

598

#define MFI_WRITE2(sc, reg, val) bus_space_write_2((sc)->mfi_btag, \

sys/dev/mfi/mfivar.h

599

sc->mfi_bhandle, (reg), (val))

sys/dev/mfi/mfivar.h

600

#define MFI_READ2(sc, reg) bus_space_read_2((sc)->mfi_btag, \

sys/dev/mfi/mfivar.h

601

(sc)->mfi_bhandle, (reg))

sys/dev/mfi/mfivar.h

602

#define MFI_WRITE1(sc, reg, val) bus_space_write_1((sc)->mfi_btag, \

sys/dev/mfi/mfivar.h

603

sc->mfi_bhandle, (reg), (val))

sys/dev/mfi/mfivar.h

604

#define MFI_READ1(sc, reg) bus_space_read_1((sc)->mfi_btag, \

sys/dev/mfi/mfivar.h

605

(sc)->mfi_bhandle, (reg))

sys/dev/mgb/if_mgb.c

1414

mgb_fct_control(struct mgb_softc *sc, int reg, int channel,

sys/dev/mgb/if_mgb.c

1420

CSR_WRITE_REG(sc, reg, MGB_FCT_RESET(channel));

sys/dev/mgb/if_mgb.c

1421

return (mgb_wait_for_bits(sc, reg, 0, MGB_FCT_RESET(channel)));

sys/dev/mgb/if_mgb.c

1423

CSR_WRITE_REG(sc, reg, MGB_FCT_ENBL(channel));

sys/dev/mgb/if_mgb.c

1426

CSR_WRITE_REG(sc, reg, MGB_FCT_DSBL(channel));

sys/dev/mgb/if_mgb.c

1427

return (mgb_wait_for_bits(sc, reg, 0, MGB_FCT_ENBL(channel)));

sys/dev/mgb/if_mgb.c

1512

mgb_wait_for_bits(struct mgb_softc *sc, int reg, int set_bits, int clear_bits)

sys/dev/mgb/if_mgb.c

1523

val = CSR_READ_REG(sc, reg);

sys/dev/mgb/if_mgb.c

1540

mgb_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/mgb/if_mgb.c

1551

mii_access |= (reg & MGB_MII_REG_ADDR_MASK) << MGB_MII_REG_ADDR_SHIFT;

sys/dev/mgb/if_mgb.c

1561

mgb_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/mgb/if_mgb.c

1572

mii_access |= (reg & MGB_MII_REG_ADDR_MASK) << MGB_MII_REG_ADDR_SHIFT;

sys/dev/mgb/if_mgb.h

134

#define MGB_DMA_REG(reg, _channel) ((reg) | ((_channel) << 6))

sys/dev/mgb/if_mgb.h

221

#define CSR_READ_BYTE(sc, reg) \

sys/dev/mgb/if_mgb.h

222

bus_read_1((sc)->regs, reg)

sys/dev/mgb/if_mgb.h

224

#define CSR_WRITE_BYTE(sc, reg, val) \

sys/dev/mgb/if_mgb.h

225

bus_write_1((sc)->regs, reg, val)

sys/dev/mgb/if_mgb.h

227

#define CSR_UPDATE_BYTE(sc, reg, val) \

sys/dev/mgb/if_mgb.h

228

CSR_WRITE_BYTE(sc, reg, CSR_READ_BYTE(sc, reg) | (val))

sys/dev/mgb/if_mgb.h

230

#define CSR_READ_REG(sc, reg) \

sys/dev/mgb/if_mgb.h

231

bus_read_4((sc)->regs, reg)

sys/dev/mgb/if_mgb.h

233

#define CSR_WRITE_REG(sc, reg, val) \

sys/dev/mgb/if_mgb.h

234

bus_write_4((sc)->regs, reg, val)

sys/dev/mgb/if_mgb.h

236

#define CSR_CLEAR_REG(sc, reg, bits) \

sys/dev/mgb/if_mgb.h

237

CSR_WRITE_REG(sc, reg, CSR_READ_REG(sc, reg) & ~(bits))

sys/dev/mgb/if_mgb.h

239

#define CSR_UPDATE_REG(sc, reg, val) \

sys/dev/mgb/if_mgb.h

240

CSR_WRITE_REG(sc, reg, CSR_READ_REG(sc, reg) | (val))

sys/dev/mgb/if_mgb.h

242

#define CSR_READ_2_BYTES(sc, reg) \

sys/dev/mgb/if_mgb.h

243

bus_read_2((sc)->regs, reg)

sys/dev/mgb/if_mgb.h

245

#define CSR_READ_REG_BYTES(sc, reg, dest, cnt) \

sys/dev/mgb/if_mgb.h

246

bus_read_region_1((sc)->regs, reg, dest, cnt)

sys/dev/mge/if_mge.c

1553

mge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/mge/if_mge.c

1558

return (mv_read_ext_phy(dev, phy, reg));

sys/dev/mge/if_mge.c

1562

mge_miibus_writereg(device_t dev, int phy, int reg, int value)

sys/dev/mge/if_mge.c

1567

mv_write_ext_phy(dev, phy, reg, value);

sys/dev/mge/if_mge.c

2049

uint32_t reg;

sys/dev/mge/if_mge.c

2054

reg = MGE_READ(sc, MGE_SDMA_CONFIG);

sys/dev/mge/if_mge.c

2055

reg &= ~mge_rx_ipg(sc->mge_rx_ipg_max, sc->mge_ver);

sys/dev/mge/if_mge.c

2056

reg |= mge_rx_ipg(sc->rx_ic_time, sc->mge_ver);

sys/dev/mge/if_mge.c

2057

MGE_WRITE(sc, MGE_SDMA_CONFIG, reg);

sys/dev/mge/if_mge.c

2063

uint32_t reg;

sys/dev/mge/if_mge.c

2068

reg = MGE_READ(sc, MGE_TX_FIFO_URGENT_TRSH);

sys/dev/mge/if_mge.c

2069

reg &= ~mge_tfut_ipg(sc->mge_tfut_ipg_max, sc->mge_ver);

sys/dev/mge/if_mge.c

207

mv_read_ge_smi(device_t dev, int phy, int reg)

sys/dev/mge/if_mge.c

2070

reg |= mge_tfut_ipg(sc->tx_ic_time, sc->mge_ver);

sys/dev/mge/if_mge.c

2071

MGE_WRITE(sc, MGE_TX_FIFO_URGENT_TRSH, reg);

sys/dev/mge/if_mge.c

2121

mge_mdio_writereg(device_t dev, int phy, int reg, int value)

sys/dev/mge/if_mge.c

2124

mv_write_ge_smi(dev, phy, reg, value);

sys/dev/mge/if_mge.c

2131

mge_mdio_readreg(device_t dev, int phy, int reg)

sys/dev/mge/if_mge.c

2135

ret = mv_read_ge_smi(dev, phy, reg);

sys/dev/mge/if_mge.c

229

(MGE_SMI_READ | (reg << 21) | (phy << 16)));

sys/dev/mge/if_mge.c

254

mv_write_ge_smi(device_t dev, int phy, int reg, uint32_t value)

sys/dev/mge/if_mge.c

274

(MGE_SMI_WRITE | (reg << 21) | (phy << 16) |

sys/dev/mge/if_mge.c

282

mv_read_ext_phy(device_t dev, int phy, int reg)

sys/dev/mge/if_mge.c

292

(MGE_SMI_READ | (reg << 21) | (phy << 16)));

sys/dev/mge/if_mge.c

309

mv_write_ext_phy(device_t dev, int phy, int reg, int value)

sys/dev/mge/if_mge.c

318

(MGE_SMI_WRITE | (reg << 21) | (phy << 16) |

sys/dev/mge/if_mge.c

94

static int mge_miibus_readreg(device_t dev, int phy, int reg);

sys/dev/mge/if_mge.c

95

static int mge_miibus_writereg(device_t dev, int phy, int reg, int value);

sys/dev/mge/if_mge.c

97

static int mge_mdio_readreg(device_t dev, int phy, int reg);

sys/dev/mge/if_mge.c

98

static int mge_mdio_writereg(device_t dev, int phy, int reg, int value);

sys/dev/mge/if_mgevar.h

119

#define MGE_READ(sc,reg) bus_read_4((sc)->res[0], (reg))

sys/dev/mge/if_mgevar.h

120

#define MGE_WRITE(sc,reg,val) bus_write_4((sc)->res[0], (reg), (val))

sys/dev/mge/if_mgevar.h

180

#define SW_SMI_READ_CMD(phy, reg) ((1 << 15) | (1 << 12) | (1 << 11) | (phy << 5) | reg)

sys/dev/mge/if_mgevar.h

181

#define SW_SMI_WRITE_CMD(phy, reg) ((1 << 15) | (1 << 12) | (1 << 10) | (phy << 5) | reg)

sys/dev/mii/acphy.c

160

int reg;

sys/dev/mii/acphy.c

168

reg = PHY_READ(sc, MII_BMCR);

sys/dev/mii/acphy.c

169

if (reg & (BMCR_ISO | BMCR_PDOWN))

sys/dev/mii/acphy.c

170

PHY_WRITE(sc, MII_BMCR, reg & ~(BMCR_ISO | BMCR_PDOWN));

sys/dev/mii/atphy.c

275

uint32_t reg;

sys/dev/mii/atphy.c

282

reg = PHY_READ(sc, ATPHY_SCR);

sys/dev/mii/atphy.c

284

reg |= ATPHY_SCR_AUTO_X_MODE;

sys/dev/mii/atphy.c

286

reg &= ~ATPHY_SCR_MAC_PDOWN;

sys/dev/mii/atphy.c

288

reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;

sys/dev/mii/atphy.c

290

reg |= ATPHY_SCR_POLARITY_REVERSAL;

sys/dev/mii/atphy.c

291

PHY_WRITE(sc, ATPHY_SCR, reg);

sys/dev/mii/brgphy.c

672

int reg;

sys/dev/mii/brgphy.c

690

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/mii/brgphy.c

691

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/mii/brgphy.c

699

int reg;

sys/dev/mii/brgphy.c

709

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/mii/brgphy.c

710

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/mii/brgphy.c

717

int reg;

sys/dev/mii/brgphy.c

726

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/mii/brgphy.c

727

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/mii/brgphy.c

735

int reg;

sys/dev/mii/brgphy.c

744

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/mii/brgphy.c

745

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/mii/brgphy.c

752

int reg;

sys/dev/mii/brgphy.c

762

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/mii/brgphy.c

763

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/mii/brgphy.c

770

int reg;

sys/dev/mii/brgphy.c

782

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/mii/brgphy.c

783

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/mii/brgphy.c

790

int reg;

sys/dev/mii/brgphy.c

805

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/mii/brgphy.c

806

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/mii/brgphy.c

813

int reg;

sys/dev/mii/brgphy.c

824

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/mii/brgphy.c

825

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/mii/brgphy.c

832

int reg;

sys/dev/mii/brgphy.c

843

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/mii/brgphy.c

844

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/mii/ciphy.c

125

int reg, speed, gig;

sys/dev/mii/ciphy.c

192

reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);

sys/dev/mii/ciphy.c

193

if (reg & BMSR_LINK)

sys/dev/mii/e1000phy.c

186

uint16_t reg, page;

sys/dev/mii/e1000phy.c

189

reg = PHY_READ(sc, E1000_CR);

sys/dev/mii/e1000phy.c

190

reg &= ~(E1000_CR_ISOLATE | E1000_CR_POWER_DOWN);

sys/dev/mii/e1000phy.c

191

PHY_WRITE(sc, E1000_CR, reg);

sys/dev/mii/e1000phy.c

193

reg = PHY_READ(sc, E1000_SCR);

sys/dev/mii/e1000phy.c

195

reg &= ~E1000_SCR_AUTO_X_MODE;

sys/dev/mii/e1000phy.c

196

PHY_WRITE(sc, E1000_SCR, reg);

sys/dev/mii/e1000phy.c

201

reg = PHY_READ(sc, E1000_SCR);

sys/dev/mii/e1000phy.c

202

reg &= ~E1000_SCR_MODE_MASK;

sys/dev/mii/e1000phy.c

203

reg |= E1000_SCR_MODE_1000BX;

sys/dev/mii/e1000phy.c

204

PHY_WRITE(sc, E1000_SCR, reg);

sys/dev/mii/e1000phy.c

208

reg = PHY_READ(sc, E1000_SCR);

sys/dev/mii/e1000phy.c

209

reg |= E1000_SCR_FIB_SIGDET_POLARITY;

sys/dev/mii/e1000phy.c

210

PHY_WRITE(sc, E1000_SCR, reg);

sys/dev/mii/e1000phy.c

225

reg &= ~E1000_SCR_EN_DETECT_MASK;

sys/dev/mii/e1000phy.c

226

reg |= E1000_SCR_AUTO_X_MODE;

sys/dev/mii/e1000phy.c

229

reg &= ~E1000_SCR_POWER_DOWN;

sys/dev/mii/e1000phy.c

230

reg |= E1000_SCR_ASSERT_CRS_ON_TX;

sys/dev/mii/e1000phy.c

233

reg |= (E1000_SCR_AUTO_X_MODE >> 1);

sys/dev/mii/e1000phy.c

234

reg |= E1000_SCR_ASSERT_CRS_ON_TX;

sys/dev/mii/e1000phy.c

237

reg |= E1000_SCR_AUTO_MDIX;

sys/dev/mii/e1000phy.c

238

reg &= ~(E1000_SCR_EN_DETECT |

sys/dev/mii/e1000phy.c

240

reg |= E1000_SCR_LPNP;

sys/dev/mii/e1000phy.c

245

reg &= ~E1000_SCR_AUTO_X_MODE;

sys/dev/mii/e1000phy.c

246

reg |= E1000_SCR_ASSERT_CRS_ON_TX;

sys/dev/mii/e1000phy.c

251

reg &= ~E1000_SCR_POLARITY_REVERSAL;

sys/dev/mii/e1000phy.c

253

PHY_WRITE(sc, E1000_SCR, reg);

sys/dev/mii/e1000phy.c

260

reg = PHY_READ(sc, E1000_SCR);

sys/dev/mii/e1000phy.c

261

reg |= E1000_SCR_RGMII_POWER_UP;

sys/dev/mii/e1000phy.c

262

PHY_WRITE(sc, E1000_SCR, reg);

sys/dev/mii/e1000phy.c

296

reg = PHY_READ(sc, E1000_ESCR);

sys/dev/mii/e1000phy.c

297

reg |= E1000_ESCR_TX_CLK_25;

sys/dev/mii/e1000phy.c

298

PHY_WRITE(sc, E1000_ESCR, reg);

sys/dev/mii/e1000phy.c

303

reg = PHY_READ(sc, E1000_CR);

sys/dev/mii/e1000phy.c

304

reg |= E1000_CR_RESET;

sys/dev/mii/e1000phy.c

305

PHY_WRITE(sc, E1000_CR, reg);

sys/dev/mii/e1000phy.c

313

int reg;

sys/dev/mii/e1000phy.c

345

reg = PHY_READ(sc, E1000_CR);

sys/dev/mii/e1000phy.c

347

reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN);

sys/dev/mii/e1000phy.c

359

reg = PHY_READ(sc, E1000_CR);

sys/dev/mii/e1000phy.c

360

reg &= ~E1000_CR_AUTO_NEG_ENABLE;

sys/dev/mii/e1000phy.c

362

reg &= ~(E1000_CR_ISOLATE | E1000_CR_POWER_DOWN);

sys/dev/mii/e1000phy.c

363

PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET);

sys/dev/mii/e1000phy.c

389

reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);

sys/dev/mii/e1000phy.c

390

if (reg & BMSR_LINK) {

sys/dev/mii/e1000phy.c

481

uint16_t reg;

sys/dev/mii/e1000phy.c

484

reg = PHY_READ(sc, E1000_AR);

sys/dev/mii/e1000phy.c

485

reg &= ~(E1000_AR_PAUSE | E1000_AR_ASM_DIR);

sys/dev/mii/e1000phy.c

486

reg |= E1000_AR_10T | E1000_AR_10T_FD |

sys/dev/mii/e1000phy.c

490

reg |= E1000_AR_PAUSE | E1000_AR_ASM_DIR;

sys/dev/mii/e1000phy.c

491

PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD);

sys/dev/mii/e1000phy.c

495

reg = 0;

sys/dev/mii/e1000phy.c

497

reg |= E1000_1GCR_1000T_FD;

sys/dev/mii/e1000phy.c

499

reg |= E1000_1GCR_1000T;

sys/dev/mii/e1000phy.c

500

PHY_WRITE(sc, E1000_1GCR, reg);

sys/dev/mii/ip1000phy.c

123

uint32_t gig, reg, speed;

sys/dev/mii/ip1000phy.c

187

reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);

sys/dev/mii/ip1000phy.c

188

if (reg & BMSR_LINK) {

sys/dev/mii/ip1000phy.c

300

uint32_t reg;

sys/dev/mii/ip1000phy.c

302

reg = 0;

sys/dev/mii/ip1000phy.c

304

reg = PHY_READ(sc, IP1000PHY_MII_ANAR);

sys/dev/mii/ip1000phy.c

305

reg &= ~(IP1000PHY_ANAR_PAUSE | IP1000PHY_ANAR_APAUSE);

sys/dev/mii/ip1000phy.c

306

reg |= IP1000PHY_ANAR_NP;

sys/dev/mii/ip1000phy.c

308

reg |= IP1000PHY_ANAR_10T | IP1000PHY_ANAR_10T_FDX |

sys/dev/mii/ip1000phy.c

311

reg |= IP1000PHY_ANAR_PAUSE | IP1000PHY_ANAR_APAUSE;

sys/dev/mii/ip1000phy.c

312

PHY_WRITE(sc, IP1000PHY_MII_ANAR, reg | IP1000PHY_ANAR_CSMA);

sys/dev/mii/ip1000phy.c

314

reg = IP1000PHY_1000CR_1000T | IP1000PHY_1000CR_1000T_FDX;

sys/dev/mii/ip1000phy.c

316

reg |= IP1000PHY_1000CR_MASTER;

sys/dev/mii/ip1000phy.c

317

PHY_WRITE(sc, IP1000PHY_MII_1000CR, reg);

sys/dev/mii/ip1000phy.c

342

uint32_t reg;

sys/dev/mii/ip1000phy.c

347

reg = PHY_READ(sc, IP1000PHY_MII_BMCR);

sys/dev/mii/ip1000phy.c

348

reg &= ~(IP1000PHY_BMCR_AUTOEN | IP1000PHY_BMCR_FDX);

sys/dev/mii/ip1000phy.c

349

PHY_WRITE(sc, MII_BMCR, reg);

sys/dev/mii/mcommphy.c

219

uint16_t reg, oldaddr;

sys/dev/mii/mcommphy.c

236

reg = PHY_READ(sc, EXT_REG_DATA);

sys/dev/mii/mcommphy.c

238

reg |= TX_CLK_SEL;

sys/dev/mii/mcommphy.c

240

reg &= ~TX_CLK_SEL;

sys/dev/mii/mcommphy.c

241

PHY_WRITE(sc, EXT_REG_DATA, reg);

sys/dev/mii/mcommphy.c

251

uint16_t reg, oldaddr;

sys/dev/mii/mcommphy.c

271

reg = PHY_READ(sc, EXT_REG_DATA);

sys/dev/mii/mcommphy.c

273

reg &= ~(RXC_DLY_EN);

sys/dev/mii/mcommphy.c

274

PHY_WRITE(sc, EXT_REG_DATA, reg);

sys/dev/mii/mcommphy.c

278

reg = PHY_READ(sc, EXT_REG_DATA);

sys/dev/mii/mcommphy.c

279

reg &= ~(RX_DELAY_SEL_MASK << RX_DELAY_SEL_SHIFT);

sys/dev/mii/mcommphy.c

280

reg |= rx_delay << RX_DELAY_SEL_SHIFT;

sys/dev/mii/mcommphy.c

281

reg &= ~(TX_DELAY_SEL_MASK << TX_DELAY_SEL_SHIFT);

sys/dev/mii/mcommphy.c

282

reg |= tx_delay << TX_DELAY_SEL_SHIFT;

sys/dev/mii/mcommphy.c

283

PHY_WRITE(sc, EXT_REG_DATA, reg);

sys/dev/mii/mcommphy.c

294

uint16_t reg, oldaddr;

sys/dev/mii/mcommphy.c

300

reg = PHY_READ(sc, EXT_REG_DATA);

sys/dev/mii/mcommphy.c

301

reg &= ~(PAD_RXC_MASK << PAD_RXC_SHIFT);

sys/dev/mii/mcommphy.c

302

reg |= (JH7110_RGMII_RXC_STRENGTH << PAD_RXC_SHIFT);

sys/dev/mii/mcommphy.c

303

PHY_WRITE(sc, EXT_REG_DATA, reg);

sys/dev/mii/mcommphy.c

307

reg = PHY_READ(sc, EXT_REG_DATA);

sys/dev/mii/mcommphy.c

308

reg &= ~(EN_SYNC_E);

sys/dev/mii/mcommphy.c

309

PHY_WRITE(sc, EXT_REG_DATA, reg);

sys/dev/mii/micphy.c

118

ksz9031_read(struct mii_softc *sc, uint32_t devaddr, uint32_t reg)

sys/dev/mii/micphy.c

122

PHY_WRITE(sc, MII_KSZ9031_MMD_ACCESS_DATA, reg);

sys/dev/mii/micphy.c

132

ksz9031_write(struct mii_softc *sc, uint32_t devaddr, uint32_t reg,

sys/dev/mii/micphy.c

138

PHY_WRITE(sc, MII_KSZ9031_MMD_ACCESS_DATA, reg);

sys/dev/mii/micphy.c

147

ksz9021_read(struct mii_softc *sc, uint32_t reg)

sys/dev/mii/micphy.c

150

PHY_WRITE(sc, MII_KSZPHY_EXTREG, reg);

sys/dev/mii/micphy.c

156

ksz9021_write(struct mii_softc *sc, uint32_t reg, uint32_t val)

sys/dev/mii/micphy.c

159

PHY_WRITE(sc, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | reg);

sys/dev/mii/micphy.c

165

uint32_t dev, uint32_t reg, char *field1, uint32_t f1mask, int f1off,

sys/dev/mii/micphy.c

174

val = ksz9031_read(sc, dev, reg);

sys/dev/mii/micphy.c

176

val = ksz9021_read(sc, reg);

sys/dev/mii/micphy.c

203

ksz9031_write(sc, dev, reg, val);

sys/dev/mii/micphy.c

205

ksz9021_write(sc, reg, val);

sys/dev/mii/micphy.c

287

int reg;

sys/dev/mii/micphy.c

296

reg = PHY_READ(sc, MII_KSZ8081_PHYCTL2);

sys/dev/mii/micphy.c

299

PHY_WRITE(sc, MII_KSZ8081_PHYCTL2, reg);

sys/dev/mii/mii.c

291

miibus_readreg(device_t dev, int phy, int reg)

sys/dev/mii/mii.c

296

return (MIIBUS_READREG(parent, phy, reg));

sys/dev/mii/mii.c

300

miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/mii/mii.c

305

return (MIIBUS_WRITEREG(parent, phy, reg, data));

sys/dev/mii/mii_bitbang.c

117

mii_bitbang_readreg(device_t dev, mii_bitbang_ops_t ops, int phy, int reg)

sys/dev/mii/mii_bitbang.c

126

mii_bitbang_sendbits(dev, ops, reg, 5);

sys/dev/mii/mii_bitbang.c

165

mii_bitbang_writereg(device_t dev, mii_bitbang_ops_t ops, int phy, int reg,

sys/dev/mii/mii_bitbang.c

174

mii_bitbang_sendbits(dev, ops, reg, 5);

sys/dev/mii/mii_bitbang.h

51

int phy, int reg);

sys/dev/mii/mii_bitbang.h

54

int phy, int reg, int val);

sys/dev/mii/mii_fdt.c

104

int reg;

sys/dev/mii/mii_fdt.c

131

if (OF_getencprop(phynode, "reg", &reg, sizeof(reg)) <= 0)

sys/dev/mii/mii_fdt.c

134

if (reg == addr)

sys/dev/mii/mii_physubr.c

292

int reg;

sys/dev/mii/mii_physubr.c

306

reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);

sys/dev/mii/mii_physubr.c

307

if ((reg & BMSR_LINK) != 0) {

sys/dev/mii/mii_physubr.c

335

int i, reg;

sys/dev/mii/mii_physubr.c

338

reg = BMCR_RESET;

sys/dev/mii/mii_physubr.c

340

reg = BMCR_RESET | BMCR_ISO;

sys/dev/mii/mii_physubr.c

341

PHY_WRITE(sc, MII_BMCR, reg);

sys/dev/mii/mii_physubr.c

345

reg = PHY_READ(sc, MII_BMCR);

sys/dev/mii/mii_physubr.c

346

if ((reg & BMCR_RESET) == 0)

sys/dev/mii/mii_physubr.c

352

reg &= ~(BMCR_PDOWN | BMCR_ISO);

sys/dev/mii/mii_physubr.c

356

reg |= BMCR_ISO;

sys/dev/mii/mii_physubr.c

357

if (PHY_READ(sc, MII_BMCR) != reg)

sys/dev/mii/mii_physubr.c

358

PHY_WRITE(sc, MII_BMCR, reg);

sys/dev/mii/mv88e151x.c

183

uint32_t reg;

sys/dev/mii/mv88e151x.c

191

reg = PHY_READ(phy, MV88E151X_FIBER_STATUS);

sys/dev/mii/mv88e151x.c

193

if (reg & MV88E151X_STATUS_LINK)

sys/dev/mii/mv88e151x.c

224

else if (reg & MV88E151X_STATUS_LINK &&

sys/dev/mii/mv88e151x.c

225

reg & MV88E151X_STATUS_SYNC &&

sys/dev/mii/mv88e151x.c

226

(reg & MV88E151X_STATUS_ENERGY) == 0) {

sys/dev/mii/mv88e151x.c

227

if (((reg & MV88E151X_STATUS_SPEED_MASK) >>

sys/dev/mii/mv88e151x.c

231

else if (((reg & MV88E151X_STATUS_SPEED_MASK) >>

sys/dev/mii/mv88e151x.c

237

if ((reg & MV88E151X_STATUS_SPEED_MASK) != 0 &&

sys/dev/mii/mv88e151x.c

238

(reg & MV88E151X_STATUS_FDX))

sys/dev/mii/nsphy.c

138

int reg;

sys/dev/mii/nsphy.c

145

reg = PHY_READ(sc, MII_NSPHY_PCR);

sys/dev/mii/nsphy.c

151

reg |= PCR_LED4MODE;

sys/dev/mii/nsphy.c

158

reg |= PCR_CIMDIS;

sys/dev/mii/nsphy.c

164

reg |= PCR_FLINK100;

sys/dev/mii/nsphy.c

176

reg |= 0x0100 | 0x0400;

sys/dev/mii/nsphy.c

179

PHY_WRITE(sc, MII_NSPHY_PCR, reg);

sys/dev/mii/nsphy.c

279

int reg, i;

sys/dev/mii/nsphy.c

282

reg = BMCR_RESET;

sys/dev/mii/nsphy.c

284

reg = BMCR_RESET | BMCR_ISO;

sys/dev/mii/nsphy.c

285

PHY_WRITE(sc, MII_BMCR, reg);

sys/dev/mii/nsphy.c

305

reg = PHY_READ(sc, MII_BMCR);

sys/dev/mii/nsphy.c

306

if (reg != 0 && (reg & BMCR_RESET) == 0)

sys/dev/mii/nsphy.c

314

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/nsphyter.c

221

int reg, i;

sys/dev/mii/nsphyter.c

224

reg = BMCR_RESET;

sys/dev/mii/nsphyter.c

226

reg = BMCR_RESET | BMCR_ISO;

sys/dev/mii/nsphyter.c

227

PHY_WRITE(sc, MII_BMCR, reg);

sys/dev/mii/nsphyter.c

249

reg = PHY_READ(sc, MII_BMCR);

sys/dev/mii/nsphyter.c

250

if (reg != 0 && (reg & BMCR_RESET) == 0)

sys/dev/mii/nsphyter.c

258

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/rgephy.c

282

uint16_t reg;

sys/dev/mii/rgephy.c

288

reg = PHY_READ(sc, RGEPHY_F_MII_SSR);

sys/dev/mii/rgephy.c

289

if (reg & RGEPHY_F_SSR_LINK)

sys/dev/mii/rgephy.c

292

reg = PHY_READ(sc, RGEPHY_MII_SSR);

sys/dev/mii/rgephy.c

293

if (reg & RGEPHY_SSR_LINK)

sys/dev/mii/rgephy.c

298

reg = PHY_READ(sc, URE_GMEDIASTAT);

sys/dev/mii/rgephy.c

300

reg = PHY_READ(sc, RL_GMEDIASTAT);

sys/dev/mii/rgephy.c

301

if (reg & RL_GMEDIASTAT_LINK)

sys/dev/mii/rlswitch.c

381

int phy, reg, val;

sys/dev/mii/rlswitch.c

388

for (reg = 0; reg <= 31; reg++) {

sys/dev/mii/rlswitch.c

389

val = MIIBUS_READREG(sc->mii_dev, phy, reg);

sys/dev/mii/smcphy.c

126

int reg;

sys/dev/mii/smcphy.c

153

reg = PHY_READ(sc, MII_BMCR);

sys/dev/mii/smcphy.c

154

if (reg & BMCR_ISO) {

sys/dev/mii/smcphy.c

155

PHY_WRITE(sc, MII_BMCR, reg & ~BMCR_ISO);

sys/dev/mii/smcphy.c

158

reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);

sys/dev/mii/smcphy.c

159

if (reg & BMSR_LINK) {

sys/dev/mii/smscphy.c

113

int reg;

sys/dev/mii/smscphy.c

140

reg = PHY_READ(sc, MII_BMCR);

sys/dev/mii/smscphy.c

141

if (reg & BMCR_ISO) {

sys/dev/mii/smscphy.c

142

PHY_WRITE(sc, MII_BMCR, reg & ~BMCR_ISO);

sys/dev/mii/smscphy.c

145

reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);

sys/dev/mii/smscphy.c

146

if (reg & BMSR_LINK) {

sys/dev/mii/vscphy.c

138

vscphy_read(struct vscphy_softc *sc, u_int reg)

sys/dev/mii/vscphy.c

142

val = PHY_READ(&sc->mii_sc, reg);

sys/dev/mii/vscphy.c

147

vscphy_write(struct vscphy_softc *sc, u_int reg, u_int val)

sys/dev/mii/vscphy.c

150

PHY_WRITE(&sc->mii_sc, reg, val);

sys/dev/mii/vscphy.c

156

int reg;

sys/dev/mii/vscphy.c

160

reg = vscphy_read(vsc, VSC8501_RGMII_CTRL_REG);

sys/dev/mii/vscphy.c

161

reg &= ~VSC8501_RGMII_RXCLOCK_DISABLE;

sys/dev/mii/vscphy.c

162

reg &= ~VSC8501_RGMII_LANESWAP;

sys/dev/mii/vscphy.c

163

reg &= ~(VSC8501_RGMII_DELAY_MASK << VSC8501_RGMII_DELAY_TXSHIFT);

sys/dev/mii/vscphy.c

164

reg &= ~(VSC8501_RGMII_DELAY_MASK << VSC8501_RGMII_DELAY_RXSHIFT);

sys/dev/mii/vscphy.c

166

reg |= VSC8501_RGMII_LANESWAP;

sys/dev/mii/vscphy.c

169

reg |= vsc->txdelay << VSC8501_RGMII_DELAY_TXSHIFT;

sys/dev/mii/vscphy.c

173

reg |= vsc->rxdelay << VSC8501_RGMII_DELAY_RXSHIFT;

sys/dev/mii/vscphy.c

175

vscphy_write(vsc, VSC8501_RGMII_CTRL_REG, reg);

sys/dev/mii/vscphy.c

183

int reg;

sys/dev/mii/vscphy.c

189

reg = vscphy_read(vsc, VSC8501_EXTCTL1_REG);

sys/dev/mii/vscphy.c

191

reg |= VSC8501_EXTCTL1_RGMII_MODE;

sys/dev/mii/vscphy.c

193

reg &= ~VSC8501_EXTCTL1_RGMII_MODE;

sys/dev/mii/vscphy.c

194

vscphy_write(vsc, VSC8501_EXTCTL1_REG, reg);

sys/dev/mii/xmphy.c

141

int reg;

sys/dev/mii/xmphy.c

186

reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);

sys/dev/mii/xmphy.c

187

if (reg & BMSR_LINK)

sys/dev/mlx4/device.h

727

void __iomem *reg;

sys/dev/mlx4/mlx4_core/mlx4_pd.c

224

bf->reg = uar->bf_map + idx * dev->caps.bf_reg_size;

sys/dev/mlx4/mlx4_core/mlx4_pd.c

255

idx = (bf->reg - bf->uar->bf_map) / dev->caps.bf_reg_size;

sys/dev/mlx4/mlx4_en/mlx4_en_tx.c

906

mlx4_bf_copy(((u8 *)ring->bf.reg) + ring->bf.offset,

sys/dev/mlx5/device.h

1234

#define MLX5_CAP_PCAM_REG(mdev, reg) \

sys/dev/mlx5/device.h

1235

MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)

sys/dev/mlx5/device.h

1240

#define MLX5_CAP_MCAM_REG(mdev, reg) \

sys/dev/mlx5/device.h

1241

MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)

sys/dev/mlx5/port.h

174

#define MLX5_GET_ETH_PROTO(reg, out, ext, field) \

sys/dev/mlx5/port.h

175

((ext) ? MLX5_GET(reg, out, ext_##field) : \

sys/dev/mlx5/port.h

176

MLX5_GET(reg, out, field))

sys/dev/mmc/host/dwmmc.c

1000

reg |= (SDMMC_BMOD_DE | SDMMC_BMOD_FB);

sys/dev/mmc/host/dwmmc.c

1001

WRITE4(sc, SDMMC_BMOD, reg);

sys/dev/mmc/host/dwmmc.c

1013

int reg;

sys/dev/mmc/host/dwmmc.c

1018

reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S);

sys/dev/mmc/host/dwmmc.c

1019

reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S;

sys/dev/mmc/host/dwmmc.c

1020

reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S;

sys/dev/mmc/host/dwmmc.c

1022

WRITE4(sc, SDMMC_FIFOTH, reg);

sys/dev/mmc/host/dwmmc.c

211

int reg;

sys/dev/mmc/host/dwmmc.c

214

reg = READ4(sc, SDMMC_CTRL);

sys/dev/mmc/host/dwmmc.c

215

reg |= (reset_bits);

sys/dev/mmc/host/dwmmc.c

216

WRITE4(sc, SDMMC_CTRL, reg);

sys/dev/mmc/host/dwmmc.c

372

uint32_t reg;

sys/dev/mmc/host/dwmmc.c

382

reg = READ4(sc, SDMMC_MINTSTS);

sys/dev/mmc/host/dwmmc.c

383

if (reg) {

sys/dev/mmc/host/dwmmc.c

384

dprintf("%s 0x%08x\n", __func__, reg);

sys/dev/mmc/host/dwmmc.c

386

if (reg & DWMMC_CMD_ERR_FLAGS) {

sys/dev/mmc/host/dwmmc.c

388

reg, cmd->opcode);

sys/dev/mmc/host/dwmmc.c

392

if (reg & DWMMC_DATA_ERR_FLAGS) {

sys/dev/mmc/host/dwmmc.c

394

reg, cmd->opcode);

sys/dev/mmc/host/dwmmc.c

402

if (reg & SDMMC_INTMASK_CMD_DONE) {

sys/dev/mmc/host/dwmmc.c

407

if (reg & SDMMC_INTMASK_ACD)

sys/dev/mmc/host/dwmmc.c

410

if (reg & SDMMC_INTMASK_DTO)

sys/dev/mmc/host/dwmmc.c

413

if (reg & SDMMC_INTMASK_CD) {

sys/dev/mmc/host/dwmmc.c

420

WRITE4(sc, SDMMC_RINTSTS, reg);

sys/dev/mmc/host/dwmmc.c

423

if (reg & (SDMMC_INTMASK_RXDR|SDMMC_INTMASK_DTO)) {

sys/dev/mmc/host/dwmmc.c

426

if (reg & (SDMMC_INTMASK_TXDR|SDMMC_INTMASK_DTO)) {

sys/dev/mmc/host/dwmmc.c

431

reg = READ4(sc, SDMMC_IDSTS);

sys/dev/mmc/host/dwmmc.c

432

if (reg) {

sys/dev/mmc/host/dwmmc.c

433

dprintf("dma intr 0x%08x\n", reg);

sys/dev/mmc/host/dwmmc.c

434

if (reg & (SDMMC_IDINTEN_TI | SDMMC_IDINTEN_RI)) {

sys/dev/mmc/host/dwmmc.c

865

uint32_t reg;

sys/dev/mmc/host/dwmmc.c

900

reg = READ4(sc, SDMMC_UHS_REG);

sys/dev/mmc/host/dwmmc.c

904

reg |= (SDMMC_UHS_REG_DDR);

sys/dev/mmc/host/dwmmc.c

906

reg &= ~(SDMMC_UHS_REG_DDR);

sys/dev/mmc/host/dwmmc.c

907

WRITE4(sc, SDMMC_UHS_REG, reg);

sys/dev/mmc/host/dwmmc.c

942

int reg;

sys/dev/mmc/host/dwmmc.c

944

reg = READ4(sc, SDMMC_CTRL);

sys/dev/mmc/host/dwmmc.c

945

reg &= ~(SDMMC_CTRL_USE_IDMAC);

sys/dev/mmc/host/dwmmc.c

946

reg |= (SDMMC_CTRL_DMA_RESET);

sys/dev/mmc/host/dwmmc.c

947

WRITE4(sc, SDMMC_CTRL, reg);

sys/dev/mmc/host/dwmmc.c

949

reg = READ4(sc, SDMMC_BMOD);

sys/dev/mmc/host/dwmmc.c

950

reg &= ~(SDMMC_BMOD_DE | SDMMC_BMOD_FB);

sys/dev/mmc/host/dwmmc.c

951

reg |= (SDMMC_BMOD_SWR);

sys/dev/mmc/host/dwmmc.c

952

WRITE4(sc, SDMMC_BMOD, reg);

sys/dev/mmc/host/dwmmc.c

962

int reg;

sys/dev/mmc/host/dwmmc.c

966

reg = READ4(sc, SDMMC_INTMASK);

sys/dev/mmc/host/dwmmc.c

967

reg &= ~(SDMMC_INTMASK_TXDR | SDMMC_INTMASK_RXDR);

sys/dev/mmc/host/dwmmc.c

968

WRITE4(sc, SDMMC_INTMASK, reg);

sys/dev/mmc/host/dwmmc.c

987

reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S);

sys/dev/mmc/host/dwmmc.c

988

reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S;

sys/dev/mmc/host/dwmmc.c

989

reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S;

sys/dev/mmc/host/dwmmc.c

991

WRITE4(sc, SDMMC_FIFOTH, reg);

sys/dev/mmc/host/dwmmc.c

994

reg = READ4(sc, SDMMC_CTRL);

sys/dev/mmc/host/dwmmc.c

995

reg |= (SDMMC_CTRL_USE_IDMAC | SDMMC_CTRL_DMA_ENABLE);

sys/dev/mmc/host/dwmmc.c

996

WRITE4(sc, SDMMC_CTRL, reg);

sys/dev/mmc/host/dwmmc.c

999

reg = READ4(sc, SDMMC_BMOD);

sys/dev/mpr/mpr.c

153

uint32_t reg;

sys/dev/mpr/mpr.c

186

reg = mpr_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET);

sys/dev/mpr/mpr.c

187

if (reg & MPI2_DIAG_DIAG_WRITE_ENABLE) {

sys/dev/mpr/mpr.c

199

reg |= MPI2_DIAG_RESET_ADAPTER;

sys/dev/mpr/mpr.c

201

reg);

sys/dev/mpr/mpr.c

202

mpr_regwrite(sc, MPI2_HOST_DIAGNOSTIC_OFFSET, reg);

sys/dev/mpr/mpr.c

228

reg = mpr_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET);

sys/dev/mpr/mpr.c

229

if (reg & MPI2_DIAG_RESET_ADAPTER) {

sys/dev/mpr/mpr.c

232

reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET);

sys/dev/mpr/mpr.c

233

if ((reg & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_RESET) {

sys/dev/mpr/mpr.c

277

uint32_t reg, state;

sys/dev/mpr/mpr.c

292

reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET);

sys/dev/mpr/mpr.c

293

mpr_dprint(sc, MPR_INIT, " Doorbell= 0x%x\n", reg);

sys/dev/mpr/mpr.c

299

if (reg & MPI2_DOORBELL_USED) {

sys/dev/mpr/mpr.c

308

if ((reg & MPI2_DOORBELL_WHO_INIT_MASK) ==

sys/dev/mpr/mpr.c

317

state = reg & MPI2_IOC_STATE_MASK;

sys/dev/mpr/mpr.c

355

uint32_t reg, state;

sys/dev/mpr/mpr.c

361

reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET);

sys/dev/mpr/mpr.c

362

mpr_dprint(sc, MPR_INIT, "%s entered, Doorbell= 0x%x\n", __func__, reg);

sys/dev/mpr/mpr.c

364

state = reg & MPI2_IOC_STATE_MASK;

sys/dev/mps/mps.c

150

uint32_t reg;

sys/dev/mps/mps.c

183

reg = mps_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET);

sys/dev/mps/mps.c

184

if (reg & MPI2_DIAG_DIAG_WRITE_ENABLE) {

sys/dev/mps/mps.c

196

reg |= MPI2_DIAG_RESET_ADAPTER;

sys/dev/mps/mps.c

198

reg);

sys/dev/mps/mps.c

199

mps_regwrite(sc, MPI2_HOST_DIAGNOSTIC_OFFSET, reg);

sys/dev/mps/mps.c

225

reg = mps_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET);

sys/dev/mps/mps.c

226

if (reg & MPI2_DIAG_RESET_ADAPTER) {

sys/dev/mps/mps.c

229

reg = mps_regread(sc, MPI2_DOORBELL_OFFSET);

sys/dev/mps/mps.c

230

if ((reg & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_RESET) {

sys/dev/mps/mps.c

274

uint32_t reg, state;

sys/dev/mps/mps.c

288

reg = mps_regread(sc, MPI2_DOORBELL_OFFSET);

sys/dev/mps/mps.c

289

mps_dprint(sc, MPS_INIT, " Doorbell= 0x%x\n", reg);

sys/dev/mps/mps.c

295

if (reg & MPI2_DOORBELL_USED) {

sys/dev/mps/mps.c

304

if ((reg & MPI2_DOORBELL_WHO_INIT_MASK) ==

sys/dev/mps/mps.c

313

state = reg & MPI2_IOC_STATE_MASK;

sys/dev/mps/mps.c

352

uint32_t reg, state;

sys/dev/mps/mps.c

358

reg = mps_regread(sc, MPI2_DOORBELL_OFFSET);

sys/dev/mps/mps.c

359

mps_dprint(sc, MPS_INIT, "%s entered, Doorbell= 0x%x\n", __func__, reg);

sys/dev/mps/mps.c

361

state = reg & MPI2_IOC_STATE_MASK;

sys/dev/mpt/mpt_pci.c

750

#define MPT_CHECK(reg, offset, size) \

sys/dev/mpt/mpt_pci.c

752

if (mpt->pci_cfg.reg != val) { \

sys/dev/mpt/mpt_pci.c

754

"Restoring " #reg " to 0x%X from 0x%X\n", \

sys/dev/mpt/mpt_pci.c

755

mpt->pci_cfg.reg, val); \

sys/dev/mrsas/mrsas.c

2757

init_frame->driver_operations.reg = htole32(init_frame->driver_operations.reg);

sys/dev/mrsas/mrsas.h

2533

u_int32_t reg;

sys/dev/msk/if_msk.c

1735

int error, msic, msir, reg;

sys/dev/msk/if_msk.c

1823

if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, &reg) == 0) {

sys/dev/msk/if_msk.c

1825

sc->msk_expcap = reg;

sys/dev/msk/if_msk.c

1826

} else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, &reg) == 0) {

sys/dev/msk/if_msk.c

1828

sc->msk_pcixcap = reg;

sys/dev/msk/if_msk.c

3768

uint32_t reg;

sys/dev/msk/if_msk.c

3861

reg = GMF_OPER_ON | GMF_RX_F_FL_ON;

sys/dev/msk/if_msk.c

3864

reg |= GMF_RX_OVER_ON;

sys/dev/msk/if_msk.c

3865

CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg);

sys/dev/msk/if_msk.c

3883

reg = RX_GMF_FL_THR_DEF + 1;

sys/dev/msk/if_msk.c

3887

reg = 0x178;

sys/dev/msk/if_msk.c

3888

CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg);

sys/dev/msk/if_msk.c

3911

reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA));

sys/dev/msk/if_msk.c

3912

reg &= ~0x03;

sys/dev/msk/if_msk.c

3913

CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg);

sys/dev/msk/if_msk.c

397

msk_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/msk/if_msk.c

3971

reg = BMU_DIS_RX_RSS_HASH;

sys/dev/msk/if_msk.c

3974

reg |= BMU_ENA_RX_CHKSUM;

sys/dev/msk/if_msk.c

3976

reg |= BMU_DIS_RX_CHKSUM;

sys/dev/msk/if_msk.c

3977

CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg);

sys/dev/msk/if_msk.c

403

return (msk_phy_readreg(sc_if, phy, reg));

sys/dev/msk/if_msk.c

407

msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg)

sys/dev/msk/if_msk.c

415

GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);

sys/dev/msk/if_msk.c

435

msk_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/msk/if_msk.c

441

return (msk_phy_writereg(sc_if, phy, reg, val));

sys/dev/msk/if_msk.c

445

msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val)

sys/dev/msk/if_msk.c

454

GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg));

sys/dev/msk/if_mskreg.h

2124

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/msk/if_mskreg.h

2125

bus_write_4((sc)->msk_res[0], (reg), (val))

sys/dev/msk/if_mskreg.h

2126

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/msk/if_mskreg.h

2127

bus_write_2((sc)->msk_res[0], (reg), (val))

sys/dev/msk/if_mskreg.h

2128

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/msk/if_mskreg.h

2129

bus_write_1((sc)->msk_res[0], (reg), (val))

sys/dev/msk/if_mskreg.h

2131

#define CSR_READ_4(sc, reg) \

sys/dev/msk/if_mskreg.h

2132

bus_read_4((sc)->msk_res[0], (reg))

sys/dev/msk/if_mskreg.h

2133

#define CSR_READ_2(sc, reg) \

sys/dev/msk/if_mskreg.h

2134

bus_read_2((sc)->msk_res[0], (reg))

sys/dev/msk/if_mskreg.h

2135

#define CSR_READ_1(sc, reg) \

sys/dev/msk/if_mskreg.h

2136

bus_read_1((sc)->msk_res[0], (reg))

sys/dev/msk/if_mskreg.h

2138

#define CSR_PCI_WRITE_4(sc, reg, val) \

sys/dev/msk/if_mskreg.h

2139

bus_write_4((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))

sys/dev/msk/if_mskreg.h

2140

#define CSR_PCI_WRITE_2(sc, reg, val) \

sys/dev/msk/if_mskreg.h

2141

bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))

sys/dev/msk/if_mskreg.h

2142

#define CSR_PCI_WRITE_1(sc, reg, val) \

sys/dev/msk/if_mskreg.h

2143

bus_write_1((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))

sys/dev/msk/if_mskreg.h

2145

#define CSR_PCI_READ_4(sc, reg) \

sys/dev/msk/if_mskreg.h

2146

bus_read_4((sc)->msk_res[0], Y2_CFG_SPC + (reg))

sys/dev/msk/if_mskreg.h

2147

#define CSR_PCI_READ_2(sc, reg) \

sys/dev/msk/if_mskreg.h

2148

bus_read_2((sc)->msk_res[0], Y2_CFG_SPC + (reg))

sys/dev/msk/if_mskreg.h

2149

#define CSR_PCI_READ_1(sc, reg) \

sys/dev/msk/if_mskreg.h

2150

bus_read_1((sc)->msk_res[0], Y2_CFG_SPC + (reg))

sys/dev/msk/if_mskreg.h

2152

#define MSK_IF_READ_4(sc_if, reg) \

sys/dev/msk/if_mskreg.h

2153

CSR_READ_4((sc_if)->msk_softc, (reg))

sys/dev/msk/if_mskreg.h

2154

#define MSK_IF_READ_2(sc_if, reg) \

sys/dev/msk/if_mskreg.h

2155

CSR_READ_2((sc_if)->msk_softc, (reg))

sys/dev/msk/if_mskreg.h

2156

#define MSK_IF_READ_1(sc_if, reg) \

sys/dev/msk/if_mskreg.h

2157

CSR_READ_1((sc_if)->msk_softc, (reg))

sys/dev/msk/if_mskreg.h

2159

#define MSK_IF_WRITE_4(sc_if, reg, val) \

sys/dev/msk/if_mskreg.h

2160

CSR_WRITE_4((sc_if)->msk_softc, (reg), (val))

sys/dev/msk/if_mskreg.h

2161

#define MSK_IF_WRITE_2(sc_if, reg, val) \

sys/dev/msk/if_mskreg.h

2162

CSR_WRITE_2((sc_if)->msk_softc, (reg), (val))

sys/dev/msk/if_mskreg.h

2163

#define MSK_IF_WRITE_1(sc_if, reg, val) \

sys/dev/msk/if_mskreg.h

2164

CSR_WRITE_1((sc_if)->msk_softc, (reg), (val))

sys/dev/msk/if_mskreg.h

2166

#define GMAC_REG(port, reg) \

sys/dev/msk/if_mskreg.h

2167

((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg))

sys/dev/msk/if_mskreg.h

2168

#define GMAC_WRITE_2(sc, port, reg, val) \

sys/dev/msk/if_mskreg.h

2169

CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val))

sys/dev/msk/if_mskreg.h

2170

#define GMAC_READ_2(sc, port, reg) \

sys/dev/msk/if_mskreg.h

2171

CSR_READ_2((sc), GMAC_REG((port), (reg)))

sys/dev/mvs/mvs.c

252

uint32_t reg;

sys/dev/mvs/mvs.c

261

reg = ATA_INL(ch->r_mem, SATA_FISC);

sys/dev/mvs/mvs.c

262

reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1;

sys/dev/mvs/mvs.c

263

ATA_OUTL(ch->r_mem, SATA_FISC, reg);

sys/dev/mvs/mvs.c

264

reg = ATA_INL(ch->r_mem, SATA_FISIM);

sys/dev/mvs/mvs.c

265

reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1;

sys/dev/mvs/mvs.c

266

ATA_OUTL(ch->r_mem, SATA_FISC, reg);

sys/dev/mwl/mwlhal.c

2233

getRFReg(struct mwl_hal_priv *mh, int flag, uint32_t reg, uint32_t *val)

sys/dev/mwl/mwlhal.c

2240

pCmd->Offset = htole16(reg);

sys/dev/mwl/mwlhal.c

2252

getBBReg(struct mwl_hal_priv *mh, int flag, uint32_t reg, uint32_t *val)

sys/dev/mwl/mwlhal.c

2259

pCmd->Offset = htole16(reg);

sys/dev/mxge/if_mxge.c

3642

int reg;

sys/dev/mxge/if_mxge.c

3646

if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {

sys/dev/mxge/if_mxge.c

3647

lnk = pci_read_config(dev, reg + 0x12, 2);

sys/dev/mxge/if_mxge.c

3651

pectl = pci_read_config(dev, reg + 0x8, 2);

sys/dev/mxge/if_mxge.c

3653

pci_write_config(dev, reg + 0x8, pectl, 2);

sys/dev/mxge/if_mxge.c

3657

pci_write_config(dev, reg + 0x8, sc->pectl, 2);

sys/dev/mxge/if_mxge.c

547

int reg, status;

sys/dev/mxge/if_mxge.c

555

if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {

sys/dev/mxge/if_mxge.c

556

pectl = pci_read_config(dev, reg + 0x8, 2);

sys/dev/my/if_my.c

140

#define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/my/if_my.c

141

#define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/my/if_my.c

218

my_phy_readreg(struct my_softc * sc, int reg)

sys/dev/my/if_my.c

226

data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);

sys/dev/my/if_my.c

228

miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);

sys/dev/my/if_my.c

261

my_phy_writereg(struct my_softc * sc, int reg, int data)

sys/dev/my/if_my.c

269

CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);

sys/dev/my/if_my.c

271

miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);

sys/dev/my/if_myreg.h

388

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/my/if_myreg.h

389

bus_space_write_4(sc->my_btag, sc->my_bhandle, reg, val)

sys/dev/my/if_myreg.h

390

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/my/if_myreg.h

391

bus_space_write_2(sc->my_btag, sc->my_bhandle, reg, val)

sys/dev/my/if_myreg.h

392

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/my/if_myreg.h

393

bus_space_write_1(sc->my_btag, sc->my_bhandle, reg, val)

sys/dev/my/if_myreg.h

395

#define CSR_READ_4(sc, reg) \

sys/dev/my/if_myreg.h

396

bus_space_read_4(sc->my_btag, sc->my_bhandle, reg)

sys/dev/my/if_myreg.h

397

#define CSR_READ_2(sc, reg) \

sys/dev/my/if_myreg.h

398

bus_space_read_2(sc->my_btag, sc->my_bhandle, reg)

sys/dev/my/if_myreg.h

399

#define CSR_READ_1(sc, reg) \

sys/dev/my/if_myreg.h

400

bus_space_read_1(sc->my_btag, sc->my_bhandle, reg)

sys/dev/nctgpio/nctgpio.c

1057

uint8_t reg;

sys/dev/nctgpio/nctgpio.c

1060

reg = nct_ppod_reg(sc, pin_num);

sys/dev/nctgpio/nctgpio.c

1061

outcfg = superio_ldn_read(sc->dev, NCT_PPOD_LDN, reg);

sys/dev/nctgpio/nctgpio.c

1063

superio_ldn_write(sc->dev, 0xf, reg, outcfg);

sys/dev/nctgpio/nctgpio.c

1069

uint8_t reg;

sys/dev/nctgpio/nctgpio.c

1072

reg = nct_ppod_reg(sc, pin_num);

sys/dev/nctgpio/nctgpio.c

1073

outcfg = superio_ldn_read(sc->dev, NCT_PPOD_LDN, reg);

sys/dev/nctgpio/nctgpio.c

1075

superio_ldn_write(sc->dev, 0xf, reg, outcfg);

sys/dev/nctgpio/nctgpio.c

1081

uint8_t reg;

sys/dev/nctgpio/nctgpio.c

1084

reg = nct_ppod_reg(sc, pin_num);

sys/dev/nctgpio/nctgpio.c

1085

outcfg = superio_ldn_read(sc->dev, NCT_PPOD_LDN, reg);

sys/dev/nctgpio/nctgpio.c

780

nct_io_read(struct nct_softc *sc, uint8_t grpnum, uint8_t reg)

sys/dev/nctgpio/nctgpio.c

786

val = bus_read_1(sc->iores, reg);

sys/dev/nctgpio/nctgpio.c

788

io2str(reg), val, reg);

sys/dev/nctgpio/nctgpio.c

793

nct_io_write(struct nct_softc *sc, uint8_t grpnum, uint8_t reg, uint8_t val)

sys/dev/nctgpio/nctgpio.c

798

io2str(reg), val, reg);

sys/dev/nctgpio/nctgpio.c

799

bus_write_1(sc->iores, reg, val);

sys/dev/nctgpio/nctgpio.c

803

nct_get_ioreg(struct nct_softc *sc, reg_t reg, uint8_t grpnum)

sys/dev/nctgpio/nctgpio.c

811

return (iobase + reg);

sys/dev/nctgpio/nctgpio.c

815

reg2str(reg_t reg)

sys/dev/nctgpio/nctgpio.c

817

switch (reg) {

sys/dev/nctgpio/nctgpio.c

826

nct_read_reg(struct nct_softc *sc, reg_t reg, uint8_t grpnum)

sys/dev/nctgpio/nctgpio.c

832

ioreg = nct_get_ioreg(sc, reg, grpnum);

sys/dev/nctgpio/nctgpio.c

840

reg2str(reg), val, grpnum, ioreg);

sys/dev/nctgpio/nctgpio.c

861

nct_write_reg(struct nct_softc *sc, reg_t reg, uint8_t grpnum, uint8_t val)

sys/dev/nctgpio/nctgpio.c

866

ioreg = nct_get_ioreg(sc, reg, grpnum);

sys/dev/nctgpio/nctgpio.c

877

reg2str(reg), val, grpnum, ioreg);

sys/dev/nctgpio/nctgpio.c

881

nct_set_pin_reg(struct nct_softc *sc, reg_t reg, uint32_t pin_num, bool val)

sys/dev/nctgpio/nctgpio.c

891

KASSERT(reg == REG_IOR || reg == REG_INV,

sys/dev/nctgpio/nctgpio.c

892

("%s: unsupported register %d", __func__, reg));

sys/dev/nctgpio/nctgpio.c

899

if (reg == REG_IOR)

sys/dev/nctgpio/nctgpio.c

907

nct_write_reg(sc, reg, group, *cache);

sys/dev/nctgpio/nctgpio.c

974

nct_get_pin_reg(struct nct_softc *sc, reg_t reg, uint32_t pin_num)

sys/dev/nctgpio/nctgpio.c

986

val = nct_read_reg(sc, reg, group);

sys/dev/ncthwm/ncthwm.c

119

ncthwm_write(struct ncthwm_softc *sc, uint8_t reg, uint8_t val)

sys/dev/ncthwm/ncthwm.c

121

bus_write_1(sc->iores, 0, reg);

sys/dev/ncthwm/ncthwm.c

126

ncthwm_read(struct ncthwm_softc *sc, uint8_t reg)

sys/dev/ncthwm/ncthwm.c

128

bus_write_1(sc->iores, 0, reg);

sys/dev/neta/if_mvneta.c

1013

uint32_t reg;

sys/dev/neta/if_mvneta.c

1030

reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK;

sys/dev/neta/if_mvneta.c

1031

reg = MVNETA_RQC_DIS(reg);

sys/dev/neta/if_mvneta.c

1032

MVNETA_WRITE(sc, MVNETA_RQC, reg);

sys/dev/neta/if_mvneta.c

1037

"timeout for RX stopped. rqc 0x%x\n", reg);

sys/dev/neta/if_mvneta.c

1041

reg = MVNETA_READ(sc, MVNETA_RQC);

sys/dev/neta/if_mvneta.c

1042

} while ((reg & MVNETA_RQC_EN_MASK) != 0);

sys/dev/neta/if_mvneta.c

1045

reg = MVNETA_READ(sc, MVNETA_PIE);

sys/dev/neta/if_mvneta.c

1046

reg &= ~MVNETA_PIE_TXPKTINTRPTENB_MASK;

sys/dev/neta/if_mvneta.c

1047

MVNETA_WRITE(sc, MVNETA_PIE, reg);

sys/dev/neta/if_mvneta.c

1049

reg = MVNETA_READ(sc, MVNETA_PRXTXTIM);

sys/dev/neta/if_mvneta.c

1050

reg &= ~MVNETA_PRXTXTI_TBTCQ_MASK;

sys/dev/neta/if_mvneta.c

1051

MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg);

sys/dev/neta/if_mvneta.c

1053

reg = MVNETA_READ(sc, MVNETA_TQC) & MVNETA_TQC_EN_MASK;

sys/dev/neta/if_mvneta.c

1054

reg = MVNETA_TQC_DIS(reg);

sys/dev/neta/if_mvneta.c

1055

MVNETA_WRITE(sc, MVNETA_TQC, reg);

sys/dev/neta/if_mvneta.c

1060

"timeout for TX stopped. tqc 0x%x\n", reg);

sys/dev/neta/if_mvneta.c

1064

reg = MVNETA_READ(sc, MVNETA_TQC);

sys/dev/neta/if_mvneta.c

1065

} while ((reg & MVNETA_TQC_EN_MASK) != 0);

sys/dev/neta/if_mvneta.c

1072

"timeout for TX FIFO drained. ps0 0x%x\n", reg);

sys/dev/neta/if_mvneta.c

1076

reg = MVNETA_READ(sc, MVNETA_PS0);

sys/dev/neta/if_mvneta.c

1077

} while (((reg & MVNETA_PS0_TXFIFOEMP) == 0) &&

sys/dev/neta/if_mvneta.c

1078

((reg & MVNETA_PS0_TXINPROG) != 0));

sys/dev/neta/if_mvneta.c

1091

uint32_t reg;

sys/dev/neta/if_mvneta.c

1130

reg = MVNETA_READ(sc, MVNETA_EUC);

sys/dev/neta/if_mvneta.c

1131

reg &= ~MVNETA_EUC_POLLING;

sys/dev/neta/if_mvneta.c

1132

MVNETA_WRITE(sc, MVNETA_EUC, reg);

sys/dev/neta/if_mvneta.c

1135

reg = MVNETA_LPIC0_LILIMIT(MVNETA_LPI_LI);

sys/dev/neta/if_mvneta.c

1136

reg |= MVNETA_LPIC0_TSLIMIT(MVNETA_LPI_TS);

sys/dev/neta/if_mvneta.c

1137

MVNETA_WRITE(sc, MVNETA_LPIC0, reg);

sys/dev/neta/if_mvneta.c

1139

reg = MVNETA_LPIC1_TWLIMIT(MVNETA_LPI_TW);

sys/dev/neta/if_mvneta.c

1140

MVNETA_WRITE(sc, MVNETA_LPIC1, reg);

sys/dev/neta/if_mvneta.c

1142

reg = MVNETA_LPIC2_MUSTSET;

sys/dev/neta/if_mvneta.c

1143

MVNETA_WRITE(sc, MVNETA_LPIC2, reg);

sys/dev/neta/if_mvneta.c

1146

reg = MVNETA_PMACC0_MUSTSET; /* must write 0x1 */

sys/dev/neta/if_mvneta.c

1147

reg &= ~MVNETA_PMACC0_PORTEN; /* port is still disabled */

sys/dev/neta/if_mvneta.c

1148

reg |= MVNETA_PMACC0_FRAMESIZELIMIT(if_getmtu(ifp) + MVNETA_ETHER_SIZE);

sys/dev/neta/if_mvneta.c

1149

MVNETA_WRITE(sc, MVNETA_PMACC0, reg);

sys/dev/neta/if_mvneta.c

1152

reg = MVNETA_READ(sc, MVNETA_PMACC2);

sys/dev/neta/if_mvneta.c

1155

reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN);

sys/dev/neta/if_mvneta.c

1159

reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN);

sys/dev/neta/if_mvneta.c

1164

reg |= MVNETA_PMACC2_RGMIIEN;

sys/dev/neta/if_mvneta.c

1167

reg |= MVNETA_PMACC2_MUSTSET;

sys/dev/neta/if_mvneta.c

1168

reg &= ~MVNETA_PMACC2_PORTMACRESET;

sys/dev/neta/if_mvneta.c

1169

MVNETA_WRITE(sc, MVNETA_PMACC2, reg);

sys/dev/neta/if_mvneta.c

1172

reg = MVNETA_READ(sc, MVNETA_PXCX);

sys/dev/neta/if_mvneta.c

1173

reg &= ~MVNETA_PXCX_TXCRCDIS;

sys/dev/neta/if_mvneta.c

1174

MVNETA_WRITE(sc, MVNETA_PXCX, reg);

sys/dev/neta/if_mvneta.c

1182

reg = MVNETA_SDC_RXBSZ_16_64BITWORDS;

sys/dev/neta/if_mvneta.c

1183

reg |= MVNETA_SDC_TXBSZ_16_64BITWORDS;

sys/dev/neta/if_mvneta.c

1184

reg |= MVNETA_SDC_BLMR;

sys/dev/neta/if_mvneta.c

1185

reg |= MVNETA_SDC_BLMT;

sys/dev/neta/if_mvneta.c

1186

MVNETA_WRITE(sc, MVNETA_SDC, reg);

sys/dev/neta/if_mvneta.c

1493

uint32_t reg;

sys/dev/neta/if_mvneta.c

1504

reg = MVNETA_PRXDQS_BUFFERSIZE(sc->rx_frame_size >> 3);

sys/dev/neta/if_mvneta.c

1505

reg |= MVNETA_PRXDQS_DESCRIPTORSQUEUESIZE(MVNETA_RX_RING_CNT);

sys/dev/neta/if_mvneta.c

1506

MVNETA_WRITE(sc, MVNETA_PRXDQS(q), reg);

sys/dev/neta/if_mvneta.c

1512

reg = MVNETA_PRXC_PACKETOFFSET(MVNETA_PACKET_OFFSET >> 3);

sys/dev/neta/if_mvneta.c

1513

MVNETA_WRITE(sc, MVNETA_PRXC(q), reg);

sys/dev/neta/if_mvneta.c

1529

uint32_t reg;

sys/dev/neta/if_mvneta.c

1540

reg = MVNETA_PTXDQS_DQS(MVNETA_TX_RING_CNT);

sys/dev/neta/if_mvneta.c

1541

MVNETA_WRITE(sc, MVNETA_PTXDQS(q), reg);

sys/dev/neta/if_mvneta.c

1553

uint32_t reg;

sys/dev/neta/if_mvneta.c

1560

reg = MVNETA_PRXDQTH_ODT(rx->queue_th_received);

sys/dev/neta/if_mvneta.c

1561

MVNETA_WRITE(sc, MVNETA_PRXDQTH(q), reg);

sys/dev/neta/if_mvneta.c

1563

reg = MVNETA_PRXITTH_RITT(rx->queue_th_time);

sys/dev/neta/if_mvneta.c

1564

MVNETA_WRITE(sc, MVNETA_PRXITTH(q), reg);

sys/dev/neta/if_mvneta.c

1567

reg = MVNETA_READ(sc, MVNETA_PRXTXTIM);

sys/dev/neta/if_mvneta.c

1568

reg |= MVNETA_PRXTXTI_RBICTAPQ(q); /* Rx Buffer Interrupt Coalese */

sys/dev/neta/if_mvneta.c

1569

MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg);

sys/dev/neta/if_mvneta.c

1572

reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK;

sys/dev/neta/if_mvneta.c

1573

reg |= MVNETA_RQC_ENQ(q);

sys/dev/neta/if_mvneta.c

1574

MVNETA_WRITE(sc, MVNETA_RQC, reg);

sys/dev/neta/if_mvneta.c

1664

uint32_t reg;

sys/dev/neta/if_mvneta.c

1667

reg = MVNETA_READ(sc, MVNETA_PRXTXTIM);

sys/dev/neta/if_mvneta.c

1668

reg |= MVNETA_PRXTXTI_PMISCICSUMMARY;

sys/dev/neta/if_mvneta.c

1669

MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg);

sys/dev/neta/if_mvneta.c

1678

reg = MVNETA_READ(sc, MVNETA_PIE);

sys/dev/neta/if_mvneta.c

1679

reg |= MVNETA_PIE_RXPKTINTRPTENB_MASK;

sys/dev/neta/if_mvneta.c

1680

reg |= MVNETA_PIE_TXPKTINTRPTENB_MASK;

sys/dev/neta/if_mvneta.c

1681

MVNETA_WRITE(sc, MVNETA_PIE, reg);

sys/dev/neta/if_mvneta.c

2190

uint32_t reg;

sys/dev/neta/if_mvneta.c

2214

reg = MVNETA_READ(sc, MVNETA_PMACC0);

sys/dev/neta/if_mvneta.c

2215

reg |= MVNETA_PMACC0_PORTEN;

sys/dev/neta/if_mvneta.c

2216

reg &= ~MVNETA_PMACC0_FRAMESIZELIMIT_MASK;

sys/dev/neta/if_mvneta.c

2217

reg |= MVNETA_PMACC0_FRAMESIZELIMIT(if_getmtu(ifp) + MVNETA_ETHER_SIZE);

sys/dev/neta/if_mvneta.c

2218

MVNETA_WRITE(sc, MVNETA_PMACC0, reg);

sys/dev/neta/if_mvneta.c

2261

uint32_t reg;

sys/dev/neta/if_mvneta.c

2279

reg = MVNETA_READ(sc, MVNETA_PMACC0);

sys/dev/neta/if_mvneta.c

2280

reg &= ~MVNETA_PMACC0_PORTEN;

sys/dev/neta/if_mvneta.c

2281

MVNETA_WRITE(sc, MVNETA_PMACC0, reg);

sys/dev/neta/if_mvneta.c

2402

int reg;

sys/dev/neta/if_mvneta.c

2405

reg = MVNETA_READ(sc, MVNETA_PANC);

sys/dev/neta/if_mvneta.c

2406

reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS |

sys/dev/neta/if_mvneta.c

2408

reg |= MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN |

sys/dev/neta/if_mvneta.c

2410

MVNETA_WRITE(sc, MVNETA_PANC, reg);

sys/dev/neta/if_mvneta.c

2412

reg = MVNETA_READ(sc, MVNETA_PMACC2);

sys/dev/neta/if_mvneta.c

2413

reg |= MVNETA_PMACC2_INBANDANMODE;

sys/dev/neta/if_mvneta.c

2414

MVNETA_WRITE(sc, MVNETA_PMACC2, reg);

sys/dev/neta/if_mvneta.c

2416

reg = MVNETA_READ(sc, MVNETA_PSOMSCD);

sys/dev/neta/if_mvneta.c

2417

reg |= MVNETA_PSOMSCD_ENABLE;

sys/dev/neta/if_mvneta.c

2418

MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg);

sys/dev/neta/if_mvneta.c

2420

reg = MVNETA_READ(sc, MVNETA_PANC);

sys/dev/neta/if_mvneta.c

2421

reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS |

sys/dev/neta/if_mvneta.c

2424

MVNETA_WRITE(sc, MVNETA_PANC, reg);

sys/dev/neta/if_mvneta.c

2426

reg = MVNETA_READ(sc, MVNETA_PMACC2);

sys/dev/neta/if_mvneta.c

2427

reg &= ~MVNETA_PMACC2_INBANDANMODE;

sys/dev/neta/if_mvneta.c

2428

MVNETA_WRITE(sc, MVNETA_PMACC2, reg);

sys/dev/neta/if_mvneta.c

2430

reg = MVNETA_READ(sc, MVNETA_PSOMSCD);

sys/dev/neta/if_mvneta.c

2431

reg &= ~MVNETA_PSOMSCD_ENABLE;

sys/dev/neta/if_mvneta.c

2432

MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg);

sys/dev/neta/if_mvneta.c

2439

int reg, err;

sys/dev/neta/if_mvneta.c

2461

reg = MVNETA_READ(sc, MVNETA_PANC);

sys/dev/neta/if_mvneta.c

2462

reg &= ~(MVNETA_PANC_SETGMIISPEED |

sys/dev/neta/if_mvneta.c

2476

reg |= MVNETA_PANC_SETGMIISPEED;

sys/dev/neta/if_mvneta.c

2478

reg |= MVNETA_PANC_SETMIISPEED;

sys/dev/neta/if_mvneta.c

2481

reg |= MVNETA_PANC_SETFULLDX;

sys/dev/neta/if_mvneta.c

2483

MVNETA_WRITE(sc, MVNETA_PANC, reg);

sys/dev/neta/if_mvneta.c

2496

int reg;

sys/dev/neta/if_mvneta.c

2517

reg = MVNETA_READ(sc, MVNETA_PANC);

sys/dev/neta/if_mvneta.c

2518

reg &= ~(MVNETA_PANC_SETGMIISPEED |

sys/dev/neta/if_mvneta.c

2523

reg |= MVNETA_PANC_SETGMIISPEED;

sys/dev/neta/if_mvneta.c

2525

reg |= MVNETA_PANC_SETMIISPEED;

sys/dev/neta/if_mvneta.c

2528

reg |= MVNETA_PANC_SETFULLDX;

sys/dev/neta/if_mvneta.c

2530

MVNETA_WRITE(sc, MVNETA_PANC, reg);

sys/dev/neta/if_mvneta.c

2576

uint32_t reg;

sys/dev/neta/if_mvneta.c

2581

reg = MVNETA_READ(sc, MVNETA_LPIC1);

sys/dev/neta/if_mvneta.c

2583

reg |= MVNETA_LPIC1_LPIRE;

sys/dev/neta/if_mvneta.c

2585

reg &= ~MVNETA_LPIC1_LPIRE;

sys/dev/neta/if_mvneta.c

2586

MVNETA_WRITE(sc, MVNETA_LPIC1, reg);

sys/dev/neta/if_mvneta.c

2592

uint32_t reg;

sys/dev/neta/if_mvneta.c

2596

reg = MVNETA_READ(sc, MVNETA_PANC);

sys/dev/neta/if_mvneta.c

2599

reg |= MVNETA_PANC_PAUSEADV;

sys/dev/neta/if_mvneta.c

2600

reg |= MVNETA_PANC_ANFCEN;

sys/dev/neta/if_mvneta.c

2603

reg &= ~MVNETA_PANC_PAUSEADV;

sys/dev/neta/if_mvneta.c

2604

reg &= ~MVNETA_PANC_ANFCEN;

sys/dev/neta/if_mvneta.c

2607

MVNETA_WRITE(sc, MVNETA_PANC, reg);

sys/dev/neta/if_mvneta.c

2613

uint32_t reg;

sys/dev/neta/if_mvneta.c

2618

reg = MVNETA_READ(sc, MVNETA_PANC);

sys/dev/neta/if_mvneta.c

2619

reg |= MVNETA_PANC_FORCELINKPASS;

sys/dev/neta/if_mvneta.c

2620

reg &= ~MVNETA_PANC_FORCELINKFAIL;

sys/dev/neta/if_mvneta.c

2621

MVNETA_WRITE(sc, MVNETA_PANC, reg);

sys/dev/neta/if_mvneta.c

2633

uint32_t reg;

sys/dev/neta/if_mvneta.c

2638

reg = MVNETA_READ(sc, MVNETA_PANC);

sys/dev/neta/if_mvneta.c

2639

reg &= ~MVNETA_PANC_FORCELINKPASS;

sys/dev/neta/if_mvneta.c

2640

reg |= MVNETA_PANC_FORCELINKFAIL;

sys/dev/neta/if_mvneta.c

2641

MVNETA_WRITE(sc, MVNETA_PANC, reg);

sys/dev/neta/if_mvneta.c

3361

uint32_t reg, time_mvtclk;

sys/dev/neta/if_mvneta.c

3401

reg = MVNETA_PRXITTH_RITT(rx->queue_th_time);

sys/dev/neta/if_mvneta.c

3402

MVNETA_WRITE(sc, MVNETA_PRXITTH(arg->queue), reg);

sys/dev/neta/if_mvneta.c

3543

uint32_t reg;

sys/dev/neta/if_mvneta.c

3585

reg = MVNETA_READ(sc, MVNETA_PDFC);

sys/dev/neta/if_mvneta.c

3586

sc->counter_pdfc += reg;

sys/dev/neta/if_mvneta.c

3587

if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg);

sys/dev/neta/if_mvneta.c

3588

reg = MVNETA_READ(sc, MVNETA_POFC);

sys/dev/neta/if_mvneta.c

3589

sc->counter_pofc += reg;

sys/dev/neta/if_mvneta.c

3590

if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg);

sys/dev/neta/if_mvneta.c

529

uint32_t reg;

sys/dev/neta/if_mvneta.c

585

reg = MVNETA_READ(sc, MVNETA_PSNPCFG);

sys/dev/neta/if_mvneta.c

586

reg &= ~MVNETA_PSNPCFG_DESCSNP_MASK;

sys/dev/neta/if_mvneta.c

587

reg &= ~MVNETA_PSNPCFG_BUFSNP_MASK;

sys/dev/neta/if_mvneta.c

588

MVNETA_WRITE(sc, MVNETA_PSNPCFG, reg);

sys/dev/neta/if_mvneta.c

875

mvneta_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/neta/if_mvneta.c

899

MVNETA_SMI_REGAD(reg) | MVNETA_SMI_OPCODE_READ;

sys/dev/neta/if_mvneta.c

937

reg, val);

sys/dev/neta/if_mvneta.c

943

mvneta_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/neta/if_mvneta.c

954

phy, reg, val);

sys/dev/neta/if_mvneta.c

970

smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg) |

sys/dev/neta/if_mvnetareg.h

347

#define MVNETA_PHYADDR_GET_PHYAD(reg) ((reg) & 0x1f)

sys/dev/neta/if_mvnetareg.h

352

#define MVNETA_SMI_REGAD(reg) (((reg) & 0x1f) << 21)

sys/dev/neta/if_mvnetareg.h

417

#define MVNETA_PV_GET_VERSION(reg) ((reg) & 0xff)

sys/dev/neta/if_mvnetareg.h

475

#define MVNETA_PRXS_GET_ODC(reg) (((reg) >> 0) & 0x3fff)

sys/dev/neta/if_mvnetareg.h

476

#define MVNETA_PRXS_GET_NODC(reg) (((reg) >> 16) & 0x3fff)

sys/dev/neta/if_mvnetareg.h

511

#define MVNETA_PTXS_GET_TBC(reg) (((reg) >> 16) & 0x3fff)

sys/dev/neta/if_mvnetareg.h

739

#define MVNETA_PRXTXTI_GET_TBTCQ(reg) (((reg) >> 0) & 0xff)

sys/dev/neta/if_mvnetareg.h

743

#define MVNETA_PRXTXTI_GET_RBICTAPQ(reg) (((reg) >> 8) & 0xff)

sys/dev/neta/if_mvnetareg.h

747

#define MVNETA_PRXTXTI_GET_RDTAQ(reg) (((reg) >> 16) & 0xff)

sys/dev/neta/if_mvnetareg.h

756

#define MVNETA_PRXTXI_GET_TBRQ(reg) (((reg) >> 0) & 0xff)

sys/dev/neta/if_mvnetareg.h

759

#define MVNETA_PRXTXI_GET_RPQ(reg) (((reg) >> 8) & 0xff)

sys/dev/neta/if_mvnetareg.h

762

#define MVNETA_PRXTXI_GET_RREQ(reg) (((reg) >> 16) & 0xff)

sys/dev/neta/if_mvnetareg.h

792

#define MVNETA_PEUIAE_GET_ADDR(reg) ((reg) & 0x3fff)

sys/dev/neta/if_mvnetavar.h

60

#define MVNETA_READ(sc, reg) \

sys/dev/neta/if_mvnetavar.h

61

bus_read_4((sc)->res[0], (reg))

sys/dev/neta/if_mvnetavar.h

62

#define MVNETA_WRITE(sc, reg, val) \

sys/dev/neta/if_mvnetavar.h

63

bus_write_4((sc)->res[0], (reg), (val))

sys/dev/neta/if_mvnetavar.h

65

#define MVNETA_READ_REGION(sc, reg, val, c) \

sys/dev/neta/if_mvnetavar.h

66

bus_read_region_4((sc)->res[0], (reg), (val), (c))

sys/dev/neta/if_mvnetavar.h

67

#define MVNETA_WRITE_REGION(sc, reg, val, c) \

sys/dev/neta/if_mvnetavar.h

68

bus_write_region_4((sc)->res[0], (reg), (val), (c))

sys/dev/neta/if_mvnetavar.h

70

#define MVNETA_READ_MIB(sc, reg) \

sys/dev/neta/if_mvnetavar.h

71

bus_read_4((sc)->res[0], MVNETA_PORTMIB_BASE + (reg))

sys/dev/netmap/netmap.c

1891

struct nmreq_register *reg = (struct nmreq_register *)hdr->nr_body;

sys/dev/netmap/netmap.c

1895

u_int nr_flags = reg->nr_flags, nr_mode = reg->nr_mode,

sys/dev/netmap/netmap.c

1896

nr_ringid = reg->nr_ringid;

sys/dev/netmap/netmap.c

1993

struct nmreq_register *reg = (struct nmreq_register *)hdr->nr_body;

sys/dev/netmap/netmap.c

2002

priv->np_txpoll = (reg->nr_flags & NR_NO_TX_POLL) ? 0 : 1;

sys/dev/netmap/netmap_bdg.c

1671

if (req->reg.nr_ringid != 0 ||

sys/dev/netmap/netmap_bdg.c

1672

(req->reg.nr_mode != NR_REG_ALL_NIC &&

sys/dev/netmap/netmap_bdg.c

1673

req->reg.nr_mode != NR_REG_NIC_SW)) {

sys/dev/netmap/netmap_bdg.c

508

if (areq->reg.nr_mode != NR_REG_NIC_SW) {

sys/dev/netmap/netmap_bdg.c

562

if (req->reg.nr_mem_id) {

sys/dev/netmap/netmap_bdg.c

563

nmd = netmap_mem_find(req->reg.nr_mem_id);

sys/dev/netmap/netmap_freebsd.c

841

nm_os_pt_memdev_ioread(struct ptnetmap_memdev *ptn_dev, unsigned int reg)

sys/dev/netmap/netmap_freebsd.c

843

return bus_read_4(ptn_dev->pci_io, reg);

sys/dev/netmap/netmap_legacy.c

160

if (nmreq_register_from_legacy(nmr, hdr, &req->reg)) {

sys/dev/netmap/netmap_legacy.c

165

req->reg.nr_mode = NR_REG_NIC_SW;

sys/dev/netmap/netmap_legacy.c

167

req->reg.nr_mode = NR_REG_ALL_NIC;

sys/dev/netmap/netmap_legacy.c

318

nmreq_register_to_legacy(&req->reg, nmr);

sys/dev/nfe/if_nfe.c

1006

nfe_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/nfe/if_nfe.c

1019

NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);

sys/dev/nfe/if_nfe.c

1040

DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);

sys/dev/nfe/if_nfe.c

1046

nfe_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/nfe/if_nfe.c

1060

ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;

sys/dev/nfe/if_nfe.c

364

int error = 0, i, msic, phyloc, reg, rid;

sys/dev/nfe/if_nfe.c

384

if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {

sys/dev/nfe/if_nfe.c

387

v = pci_read_config(dev, reg + 0x08, 2);

sys/dev/nfe/if_nfe.c

391

pci_write_config(dev, reg + 0x08, v, 2);

sys/dev/nfe/if_nfe.c

393

v = pci_read_config(dev, reg + 0x0c, 2);

sys/dev/nfe/if_nfe.c

396

width = pci_read_config(dev, reg + 0x12, 2);

sys/dev/nfe/if_nfereg.h

288

#define NFE_READ(sc, reg) \

sys/dev/nfe/if_nfereg.h

289

bus_read_4((sc)->nfe_res[0], (reg))

sys/dev/nfe/if_nfereg.h

291

#define NFE_WRITE(sc, reg, val) \

sys/dev/nfe/if_nfereg.h

292

bus_write_4((sc)->nfe_res[0], (reg), (val))

sys/dev/nge/if_nge.c

2051

uint32_t reg;

sys/dev/nge/if_nge.c

2183

reg = CSR_READ_4(sc, NGE_MIBCTL);

sys/dev/nge/if_nge.c

2184

reg &= ~NGE_MIBCTL_FREEZE_CNT;

sys/dev/nge/if_nge.c

2185

reg |= NGE_MIBCTL_CLEAR_CNT;

sys/dev/nge/if_nge.c

2186

CSR_WRITE_4(sc, NGE_MIBCTL, reg);

sys/dev/nge/if_nge.c

2420

uint32_t reg;

sys/dev/nge/if_nge.c

2425

reg = CSR_READ_4(sc, NGE_CSR);

sys/dev/nge/if_nge.c

2426

if ((reg & (NGE_CSR_TX_ENABLE | NGE_CSR_RX_ENABLE)) != 0) {

sys/dev/nge/if_nge.c

2427

reg &= ~(NGE_CSR_TX_ENABLE | NGE_CSR_RX_ENABLE);

sys/dev/nge/if_nge.c

2428

reg |= NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE;

sys/dev/nge/if_nge.c

2429

CSR_WRITE_4(sc, NGE_CSR, reg);

sys/dev/nge/if_nge.c

244

#define NGE_SETBIT(sc, reg, x) \

sys/dev/nge/if_nge.c

245

CSR_WRITE_4(sc, reg, \

sys/dev/nge/if_nge.c

246

CSR_READ_4(sc, reg) | (x))

sys/dev/nge/if_nge.c

248

#define NGE_CLRBIT(sc, reg, x) \

sys/dev/nge/if_nge.c

249

CSR_WRITE_4(sc, reg, \

sys/dev/nge/if_nge.c

250

CSR_READ_4(sc, reg) & ~(x))

sys/dev/nge/if_nge.c

2512

uint32_t reg;

sys/dev/nge/if_nge.c

2541

reg = 0;

sys/dev/nge/if_nge.c

2543

reg |= NGE_WOLCSR_WAKE_ON_UNICAST;

sys/dev/nge/if_nge.c

2545

reg |= NGE_WOLCSR_WAKE_ON_MULTICAST;

sys/dev/nge/if_nge.c

2547

reg |= NGE_WOLCSR_WAKE_ON_MAGICPKT;

sys/dev/nge/if_nge.c

2548

CSR_WRITE_4(sc, NGE_WOLCSR, reg);

sys/dev/nge/if_nge.c

2551

reg = CSR_READ_4(sc, NGE_CLKRUN);

sys/dev/nge/if_nge.c

2552

reg |= NGE_CLKRUN_PMEENB | NGE_CLNRUN_CLKRUN_ENB;

sys/dev/nge/if_nge.c

2553

CSR_WRITE_4(sc, NGE_CLKRUN, reg);

sys/dev/nge/if_nge.c

411

nge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/nge/if_nge.c

421

switch (reg) {

sys/dev/nge/if_nge.c

423

reg = NGE_TBI_BMCR;

sys/dev/nge/if_nge.c

428

reg = CSR_READ_4(sc, NGE_TBI_BMSR);

sys/dev/nge/if_nge.c

429

if ((reg & NGE_TBIBMSR_ANEG_DONE) != 0)

sys/dev/nge/if_nge.c

431

if ((reg & NGE_TBIBMSR_LINKSTAT) != 0)

sys/dev/nge/if_nge.c

435

reg = NGE_TBI_ANAR;

sys/dev/nge/if_nge.c

438

reg = NGE_TBI_ANLPAR;

sys/dev/nge/if_nge.c

441

reg = NGE_TBI_ANER;

sys/dev/nge/if_nge.c

444

reg = NGE_TBI_ESR;

sys/dev/nge/if_nge.c

451

"bad phy register read : %d\n", reg);

sys/dev/nge/if_nge.c

454

return (CSR_READ_4(sc, reg));

sys/dev/nge/if_nge.c

457

return (mii_bitbang_readreg(dev, &nge_mii_bitbang_ops, phy, reg));

sys/dev/nge/if_nge.c

461

nge_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/nge/if_nge.c

470

switch (reg) {

sys/dev/nge/if_nge.c

472

reg = NGE_TBI_BMCR;

sys/dev/nge/if_nge.c

477

reg = NGE_TBI_ANAR;

sys/dev/nge/if_nge.c

480

reg = NGE_TBI_ANLPAR;

sys/dev/nge/if_nge.c

483

reg = NGE_TBI_ANER;

sys/dev/nge/if_nge.c

486

reg = NGE_TBI_ESR;

sys/dev/nge/if_nge.c

493

"bad phy register write : %d\n", reg);

sys/dev/nge/if_nge.c

496

CSR_WRITE_4(sc, reg, data);

sys/dev/nge/if_nge.c

500

mii_bitbang_writereg(dev, &nge_mii_bitbang_ops, phy, reg, data);

sys/dev/nge/if_nge.c

515

uint32_t done, reg, status;

sys/dev/nge/if_nge.c

588

reg = CSR_READ_4(sc, NGE_CFG);

sys/dev/nge/if_nge.c

594

reg |= NGE_CFG_MODE_1000;

sys/dev/nge/if_nge.c

597

reg &= ~NGE_CFG_MODE_1000;

sys/dev/nge/if_nge.c

600

CSR_WRITE_4(sc, NGE_CFG, reg);

sys/dev/nge/if_nge.c

603

reg = CSR_READ_4(sc, NGE_CSR);

sys/dev/nge/if_nge.c

604

reg |= NGE_CSR_TX_RESET | NGE_CSR_RX_RESET;

sys/dev/nge/if_nge.c

605

CSR_WRITE_4(sc, NGE_CSR, reg);

sys/dev/nge/if_nge.c

641

reg = CSR_READ_4(sc, NGE_CSR);

sys/dev/nge/if_nge.c

642

reg |= NGE_CSR_RX_ENABLE;

sys/dev/nge/if_nge.c

643

CSR_WRITE_4(sc, NGE_CSR, reg);

sys/dev/nge/if_nge.c

819

uint16_t ea[ETHER_ADDR_LEN/2], ea_temp, reg;

sys/dev/nge/if_nge.c

877

reg = pci_read_config(dev, PCIR_COMMAND, 2);

sys/dev/nge/if_nge.c

878

reg |= PCIM_CMD_MWRICEN;

sys/dev/nge/if_nge.c

879

pci_write_config(dev, PCIR_COMMAND, reg, 2);

sys/dev/nge/if_ngereg.h

673

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/nge/if_ngereg.h

674

bus_write_4((sc)->nge_res, reg, val)

sys/dev/nge/if_ngereg.h

676

#define CSR_BARRIER_4(sc, reg, flags) \

sys/dev/nge/if_ngereg.h

677

bus_barrier((sc)->nge_res, reg, 4, flags)

sys/dev/nge/if_ngereg.h

679

#define CSR_READ_4(sc, reg) \

sys/dev/nge/if_ngereg.h

680

bus_read_4((sc)->nge_res, reg)

sys/dev/ntb/ntb_hw/ntb_hw_amd.c

767

uint32_t fullreg, reg, stat;

sys/dev/ntb/ntb_hw/ntb_hw_amd.c

770

reg = fullreg & NTB_LIN_STA_ACTIVE_BIT;

sys/dev/ntb/ntb_hw/ntb_hw_amd.c

772

if (reg == ntb->cntl_sta)

sys/dev/ntb/ntb_hw/ntb_hw_amd.c

778

ntb->cntl_sta = reg;

sys/dev/ntb/ntb_hw/ntb_hw_amd.c

834

unsigned int reg;

sys/dev/ntb/ntb_hw/ntb_hw_amd.c

836

reg = amd_ntb_reg_read(4, AMD_SIDEINFO_OFFSET);

sys/dev/ntb/ntb_hw/ntb_hw_amd.c

837

if (!(reg & AMD_SIDE_READY)) {

sys/dev/ntb/ntb_hw/ntb_hw_amd.c

838

reg |= AMD_SIDE_READY;

sys/dev/ntb/ntb_hw/ntb_hw_amd.c

839

amd_ntb_reg_write(4, AMD_SIDEINFO_OFFSET, reg);

sys/dev/ntb/ntb_hw/ntb_hw_amd.c

841

reg = amd_ntb_reg_read(4, AMD_SIDEINFO_OFFSET);

sys/dev/ntb/ntb_hw/ntb_hw_amd.c

847

unsigned int reg;

sys/dev/ntb/ntb_hw/ntb_hw_amd.c

849

reg = amd_ntb_reg_read(4, AMD_SIDEINFO_OFFSET);

sys/dev/ntb/ntb_hw/ntb_hw_amd.c

850

if (reg & AMD_SIDE_READY) {

sys/dev/ntb/ntb_hw/ntb_hw_amd.c

851

reg &= ~AMD_SIDE_READY;

sys/dev/ntb/ntb_hw/ntb_hw_amd.c

852

amd_ntb_reg_write(4, AMD_SIDEINFO_OFFSET, reg);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

1179

uint64_t i, reg;

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

1190

reg = intel_ntb_reg_read(8, XEON_GEN3_REG_IMINT_STATUS);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

1191

intel_ntb_reg_write(8, XEON_GEN3_REG_IMINT_STATUS, reg);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

1236

uint64_t i, reg;

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

1247

reg = intel_ntb_reg_read(8, XEON_GEN4_REG_IMINT_STATUS);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

1248

intel_ntb_reg_write(8, XEON_GEN4_REG_IMINT_STATUS, reg);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

1688

if (ntb->reg != NULL)

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

1934

ntb->reg = &xeon_reg;

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2018

ntb->reg = &xeon_gen3_reg;

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2052

ntb->reg = &xeon_gen4_reg;

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2084

ntb->reg = &atom_reg;

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2364

uint64_t reg;

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2400

reg = intel_ntb_reg_read(8, XEON_GEN3_REG_EMBAR1XBASE);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2401

reg += ntb->bar_info[NTB_B2B_BAR_1].size;

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2402

intel_ntb_reg_write(8, XEON_GEN3_REG_EMBAR1XLIMIT, reg);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2404

reg = intel_ntb_reg_read(8, XEON_GEN3_REG_EMBAR2XBASE);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2405

reg += ntb->bar_info[NTB_B2B_BAR_2].size;

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2406

intel_ntb_reg_write(8, XEON_GEN3_REG_EMBAR2XLIMIT, reg);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2626

intel_ntb_reg_write(4, ntb->reg->ntb_ctl, cntl);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2668

cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2674

intel_ntb_reg_write(4, ntb->reg->ntb_ctl, cntl);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2686

cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2689

intel_ntb_reg_write(4, ntb->reg->ntb_ctl, cntl);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

269

const struct ntb_reg *reg;

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2718

cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2724

intel_ntb_reg_write(4, ntb->reg->ntb_ctl, cntl);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2747

cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2772

status32 = intel_ntb_reg_read(4, ntb->reg->ntb_ctl);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2776

status32 = intel_ntb_reg_read(4, ntb->reg->lnk_sta);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2803

ntb_cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2808

ntb->lnk_sta = intel_ntb_reg_read(4, ntb->reg->lnk_sta);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2821

reg_val = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2854

reg_val = intel_ntb_reg_read(2, ntb->reg->lnk_sta);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

2992

NTB_REG_32 | ntb->reg->ntb_ctl, sysctl_handle_register, "IU",

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

3293

uint32_t reg;

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

3298

reg = arg2 & ~NTB_REGFLAGS_MASK;

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

3307

umv = db_ioread(ntb, reg);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

3313

umv = pci_read_config(ntb->device, reg, 8);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

3315

umv = intel_ntb_reg_read(8, reg);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

3320

umv = pci_read_config(ntb->device, reg, 4);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

3322

umv = intel_ntb_reg_read(4, reg);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

3327

umv = pci_read_config(ntb->device, reg, 2);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

3329

umv = intel_ntb_reg_read(2, reg);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

3334

umv = pci_read_config(ntb->device, reg, 1);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

3336

umv = intel_ntb_reg_read(1, reg);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

3444

ntb->lnk_sta = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2);

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

3810

*db_size = ntb->reg->db_size;

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

824

KASSERT(ntb->reg->mw_bar[mw] != 0, ("invalid mw"));

sys/dev/ntb/ntb_hw/ntb_hw_intel.c

826

return (ntb->reg->mw_bar[mw]);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

120

#define NTX_READ(sc, reg) \

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

121

bus_read_4((sc)->conf_res, PLX_NTX_OUR_BASE(sc) + (reg))

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

122

#define NTX_WRITE(sc, reg, val) \

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

123

bus_write_4((sc)->conf_res, PLX_NTX_OUR_BASE(sc) + (reg), (val))

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

126

#define PNTX_READ(sc, reg) \

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

127

bus_read_4((sc)->conf_res, PLX_NTX_PEER_BASE(sc) + (reg))

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

128

#define PNTX_WRITE(sc, reg, val) \

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

129

bus_write_4((sc)->conf_res, PLX_NTX_PEER_BASE(sc) + (reg), (val))

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

132

#define BNTX_READ(sc, reg) \

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

134

PLX_NTX_BASE(sc) + (reg))

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

135

#define BNTX_WRITE(sc, reg, val) \

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

137

PLX_NTX_BASE(sc) + (reg), (val))

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

557

uint32_t reg, val;

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

565

reg = PLX_PORT_CONTROL(sc);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

566

val = bus_read_4(sc->conf_res, reg);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

573

bus_write_4(sc->conf_res, reg, val);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

581

uint32_t reg, val;

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

587

reg = PLX_PORT_CONTROL(sc);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

588

val = bus_read_4(sc->conf_res, reg);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

590

bus_write_4(sc->conf_res, reg, val);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

598

uint32_t reg, val;

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

604

reg = PLX_PORT_CONTROL(sc);

sys/dev/ntb/ntb_hw/ntb_hw_plx.c

605

val = bus_read_4(sc->conf_res, reg);

sys/dev/nvme/nvme_private.h

325

#define nvme_mmio_offsetof(reg) \

sys/dev/nvme/nvme_private.h

326

offsetof(struct nvme_registers, reg)

sys/dev/nvme/nvme_private.h

328

#define nvme_mmio_read_4(sc, reg) \

sys/dev/nvme/nvme_private.h

329

bus_read_4((sc)->resource, nvme_mmio_offsetof(reg))

sys/dev/nvme/nvme_private.h

331

#define nvme_mmio_write_4(sc, reg, val) \

sys/dev/nvme/nvme_private.h

332

bus_write_4((sc)->resource, nvme_mmio_offsetof(reg), val)

sys/dev/nvme/nvme_private.h

334

#define nvme_mmio_write_8(sc, reg, val) \

sys/dev/nvme/nvme_private.h

336

bus_write_4((sc)->resource, nvme_mmio_offsetof(reg), \

sys/dev/nvme/nvme_private.h

338

bus_write_4((sc)->resource, nvme_mmio_offsetof(reg) + 4, \

sys/dev/nvmem/nvmem.c

107

if (OF_getencprop(cell_node, "reg", reg, sizeof(reg)) != sizeof(reg)) {

sys/dev/nvmem/nvmem.c

114

if (buflen != reg[1])

sys/dev/nvmem/nvmem.c

124

rv = NVMEM_READ(provider, reg[0], reg[1], cell);

sys/dev/nvmem/nvmem.c

149

uint32_t reg[2];

sys/dev/nvmem/nvmem.c

161

if (OF_getencprop(cell_node, "reg", reg, sizeof(reg)) != sizeof(reg)) {

sys/dev/nvmem/nvmem.c

168

if (buflen != reg[1])

sys/dev/nvmem/nvmem.c

178

rv = NVMEM_WRITE(provider, reg[0], reg[1], cell);

sys/dev/nvmem/nvmem.c

73

uint32_t reg[2];

sys/dev/nvmem/nvmem.c

84

if (OF_getencprop(cell_node, "reg", reg, sizeof(reg)) != sizeof(reg)) {

sys/dev/nvmem/nvmem.c

91

return (reg[1]);

sys/dev/nvmem/nvmem.c

99

uint32_t reg[2];

sys/dev/oce/oce_hw.c

506

uint32_t reg;

sys/dev/oce/oce_hw.c

508

reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);

sys/dev/oce/oce_hw.c

509

reg |= HOSTINTR_MASK;

sys/dev/oce/oce_hw.c

510

OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg);

sys/dev/oce/oce_hw.c

521

uint32_t reg;

sys/dev/oce/oce_hw.c

523

reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);

sys/dev/oce/oce_hw.c

524

reg &= ~HOSTINTR_MASK;

sys/dev/oce/oce_hw.c

525

OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg);

sys/dev/ocs_fc/ocs.h

102

ocs_pci_reg_t reg[PCI_MAX_BAR];

sys/dev/ocs_fc/ocs_ioctl.c

298

if (ocs->reg[req->bar].res == NULL) {

sys/dev/ocs_fc/ocs_os.c

101

ocs_pci_reg_t *reg = NULL;

sys/dev/ocs_fc/ocs_os.c

103

reg = &ocs->reg[rset];

sys/dev/ocs_fc/ocs_os.c

105

return bus_space_read_4(reg->btag, reg->bhandle, off);

sys/dev/ocs_fc/ocs_os.c

125

ocs_pci_reg_t *reg = NULL;

sys/dev/ocs_fc/ocs_os.c

127

reg = &ocs->reg[rset];

sys/dev/ocs_fc/ocs_os.c

129

return bus_space_read_2(reg->btag, reg->bhandle, off);

sys/dev/ocs_fc/ocs_os.c

149

ocs_pci_reg_t *reg = NULL;

sys/dev/ocs_fc/ocs_os.c

151

reg = &ocs->reg[rset];

sys/dev/ocs_fc/ocs_os.c

153

return bus_space_read_1(reg->btag, reg->bhandle, off);

sys/dev/ocs_fc/ocs_os.c

174

ocs_pci_reg_t *reg = NULL;

sys/dev/ocs_fc/ocs_os.c

176

reg = &ocs->reg[rset];

sys/dev/ocs_fc/ocs_os.c

178

return bus_space_write_4(reg->btag, reg->bhandle, off, val);

sys/dev/ocs_fc/ocs_os.c

199

ocs_pci_reg_t *reg = NULL;

sys/dev/ocs_fc/ocs_os.c

201

reg = &ocs->reg[rset];

sys/dev/ocs_fc/ocs_os.c

203

return bus_space_write_2(reg->btag, reg->bhandle, off, val);

sys/dev/ocs_fc/ocs_os.c

224

ocs_pci_reg_t *reg = NULL;

sys/dev/ocs_fc/ocs_os.c

226

reg = &ocs->reg[rset];

sys/dev/ocs_fc/ocs_os.c

228

return bus_space_write_1(reg->btag, reg->bhandle, off, val);

sys/dev/ocs_fc/ocs_os.c

49

ocs_config_read32(ocs_os_handle_t os, uint32_t reg)

sys/dev/ocs_fc/ocs_os.c

51

return pci_read_config(os->dev, reg, 4);

sys/dev/ocs_fc/ocs_os.c

55

ocs_config_read16(ocs_os_handle_t os, uint32_t reg)

sys/dev/ocs_fc/ocs_os.c

57

return pci_read_config(os->dev, reg, 2);

sys/dev/ocs_fc/ocs_os.c

61

ocs_config_read8(ocs_os_handle_t os, uint32_t reg)

sys/dev/ocs_fc/ocs_os.c

63

return pci_read_config(os->dev, reg, 1);

sys/dev/ocs_fc/ocs_os.c

67

ocs_config_write8(ocs_os_handle_t os, uint32_t reg, uint8_t val)

sys/dev/ocs_fc/ocs_os.c

69

return pci_write_config(os->dev, reg, val, 1);

sys/dev/ocs_fc/ocs_os.c

73

ocs_config_write16(ocs_os_handle_t os, uint32_t reg, uint16_t val)

sys/dev/ocs_fc/ocs_os.c

75

return pci_write_config(os->dev, reg, val, 2);

sys/dev/ocs_fc/ocs_os.c

79

ocs_config_write32(ocs_os_handle_t os, uint32_t reg, uint32_t val)

sys/dev/ocs_fc/ocs_os.c

81

return pci_write_config(os->dev, reg, val, 4);

sys/dev/ocs_fc/ocs_os.h

1069

extern uint32_t ocs_config_read32(ocs_os_handle_t os, uint32_t reg);

sys/dev/ocs_fc/ocs_os.h

1081

extern uint16_t ocs_config_read16(ocs_os_handle_t os, uint32_t reg);

sys/dev/ocs_fc/ocs_os.h

1093

extern uint8_t ocs_config_read8(ocs_os_handle_t os, uint32_t reg);

sys/dev/ocs_fc/ocs_os.h

1106

extern void ocs_config_write8(ocs_os_handle_t os, uint32_t reg, uint8_t val);

sys/dev/ocs_fc/ocs_os.h

1119

extern void ocs_config_write16(ocs_os_handle_t os, uint32_t reg, uint16_t val);

sys/dev/ocs_fc/ocs_os.h

1132

extern void ocs_config_write32(ocs_os_handle_t os, uint32_t reg, uint32_t val);

sys/dev/ocs_fc/ocs_pci.c

130

ocs->reg[r].rid = PCIR_BAR(i);

sys/dev/ocs_fc/ocs_pci.c

131

ocs->reg[r].res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,

sys/dev/ocs_fc/ocs_pci.c

132

&ocs->reg[r].rid, RF_ACTIVE);

sys/dev/ocs_fc/ocs_pci.c

133

if (ocs->reg[r].res) {

sys/dev/ocs_fc/ocs_pci.c

134

ocs->reg[r].btag = rman_get_bustag(ocs->reg[r].res);

sys/dev/ocs_fc/ocs_pci.c

135

ocs->reg[r].bhandle = rman_get_bushandle(ocs->reg[r].res);

sys/dev/ocs_fc/ocs_pci.c

139

ocs->reg[r].rid);

sys/dev/ocs_fc/ocs_pci.c

164

ocs->reg[0].rid = PCIR_BAR(PCI_64BIT_BAR0);

sys/dev/ocs_fc/ocs_pci.c

165

ocs->reg[0].res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,

sys/dev/ocs_fc/ocs_pci.c

166

&ocs->reg[0].rid, RF_ACTIVE);

sys/dev/ocs_fc/ocs_pci.c

168

if (ocs->reg[0].res == NULL) {

sys/dev/ocs_fc/ocs_pci.c

170

ocs->reg[0].rid);

sys/dev/ocs_fc/ocs_pci.c

174

ocs->reg[0].btag = rman_get_bustag(ocs->reg[0].res);

sys/dev/ocs_fc/ocs_pci.c

175

ocs->reg[0].bhandle = rman_get_bushandle(ocs->reg[0].res);

sys/dev/ocs_fc/ocs_pci.c

756

if (ocs->reg[i].res) {

sys/dev/ocs_fc/ocs_pci.c

758

ocs->reg[i].rid,

sys/dev/ocs_fc/ocs_pci.c

759

ocs->reg[i].res);

sys/dev/ocs_fc/sli4.c

258

sli_reg_read(sli4_t *sli, sli4_regname_e reg)

sys/dev/ocs_fc/sli4.c

260

const sli4_reg_t *r = &(regmap[reg][sli->if_type]);

sys/dev/ocs_fc/sli4.c

263

ocs_log_err(sli->os, "regname %d not defined for if_type %d\n", reg, sli->if_type);

sys/dev/ocs_fc/sli4.c

280

sli_reg_write(sli4_t *sli, sli4_regname_e reg, uint32_t val)

sys/dev/ocs_fc/sli4.c

282

const sli4_reg_t *r = &(regmap[reg][sli->if_type]);

sys/dev/ocs_fc/sli4.c

285

ocs_log_err(sli->os, "regname %d not defined for if_type %d\n", reg, sli->if_type);

sys/dev/ocs_fc/sli4.h

209

uint32_t reg = 0;

sys/dev/ocs_fc/sli4.h

220

} * eq_doorbell = (void *)®

sys/dev/ocs_fc/sli4.h

232

return reg;

sys/dev/ocs_fc/sli4.h

237

uint32_t reg = 0;

sys/dev/ocs_fc/sli4.h

247

} * cq_doorbell = (void *)®

sys/dev/ocs_fc/sli4.h

258

return reg;

sys/dev/ocs_fc/sli4.h

263

uint32_t reg = 0;

sys/dev/ocs_fc/sli4.h

272

} * eq_doorbell = (void *)®

sys/dev/ocs_fc/sli4.h

281

return reg;

sys/dev/ocs_fc/sli4.h

286

uint32_t reg = 0;

sys/dev/ocs_fc/sli4.h

294

} * cq_doorbell = (void *)®

sys/dev/ocs_fc/sli4.h

303

return reg;

sys/dev/ofw/ofw_bus_subr.c

362

ofw_bus_lookup_imap(phandle_t node, struct ofw_bus_iinfo *ii, void *reg,

sys/dev/ofw/ofw_bus_subr.c

375

rv = OF_getencprop(node, "reg", reg, regsz);

sys/dev/ofw/ofw_bus_subr.c

379

return (ofw_bus_search_intrmap(pintr, pintrsz, reg, ii->opi_addrc,

sys/dev/ofw/ofw_bus_subr.c

565

uint32_t *reg;

sys/dev/ofw/ofw_bus_subr.c

576

ret = OF_getencprop_alloc_multi(node, reg_source, sizeof(*reg),

sys/dev/ofw/ofw_bus_subr.c

577

(void **)&reg);

sys/dev/ofw/ofw_bus_subr.c

591

phys |= reg[i + j];

sys/dev/ofw/ofw_bus_subr.c

595

size |= reg[i + acells + j];

sys/dev/ofw/ofw_bus_subr.c

603

free(reg, M_OFWPROP);

sys/dev/ofw/ofw_bus_subr.c

670

void *reg;

sys/dev/ofw/ofw_bus_subr.c

692

reg = NULL;

sys/dev/ofw/ofw_bus_subr.c

694

reg = malloc(ii.opi_addrc, M_OFWPROP, M_WAITOK);

sys/dev/ofw/ofw_bus_subr.c

696

rv = ofw_bus_lookup_imap(node, &ii, reg, ii.opi_addrc, intrp,

sys/dev/ofw/ofw_bus_subr.c

699

free(reg, M_OFWPROP);

sys/dev/ofw/ofw_cpu.c

411

pcell_t addr_cells, reg[2];

sys/dev/ofw/ofw_cpu.c

454

rv = OF_getencprop(child, "reg", reg,

sys/dev/ofw/ofw_cpu.c

459

if (callback == NULL || callback(id, child, addr_cells, reg))

sys/dev/ofw/ofw_graph.c

110

uint32_t reg;

sys/dev/ofw/ofw_graph.c

119

if (OF_getencprop(child, "reg", &reg, sizeof(uint32_t)) <= 0 ||

sys/dev/ofw/ofw_graph.c

120

reg != idx)

sys/dev/ofw/ofw_graph.c

50

uint32_t reg;

sys/dev/ofw/ofw_graph.c

73

if (OF_getencprop(child, "reg", &reg, sizeof(uint32_t)) <= 0 ||

sys/dev/ofw/ofw_graph.c

74

reg != idx)

sys/dev/ofw/ofw_pcib.c

321

struct ofw_pci_register reg;

sys/dev/ofw/ofw_pcib.c

330

bzero(&reg, sizeof(reg));

sys/dev/ofw/ofw_pcib.c

331

reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |

sys/dev/ofw/ofw_pcib.c

336

&sc->sc_pci_iinfo, &reg, sizeof(reg), &pintr, sizeof(pintr),

sys/dev/otus/if_otus.c

1304

otus_write(struct otus_softc *sc, uint32_t reg, uint32_t val)

sys/dev/otus/if_otus.c

1309

sc->write_buf[sc->write_idx].reg = htole32(reg);

sys/dev/otus/if_otus.c

1347

uint32_t regs[8], reg;

sys/dev/otus/if_otus.c

1355

reg = AR_EEPROM_OFFSET;

sys/dev/otus/if_otus.c

1357

for (j = 0; j < 8; j++, reg += 4)

sys/dev/otus/if_otus.c

1358

regs[j] = htole32(reg);

sys/dev/otus/if_otus.c

2606

otus_phy_get_def(struct otus_softc *sc, uint32_t reg)

sys/dev/otus/if_otus.c

2611

if (AR_PHY(ar5416_phy_regs[i]) == reg)

sys/dev/otus/if_otusreg.h

1054

uint32_t reg;

sys/dev/otus/if_otusreg.h

123

#define AR_PHY(reg) (AR_PHY_BASE + (reg) * 4)

sys/dev/p2sb/lewisburg_gpiocm.c

54

#define LBGGPIOCM_READ(sc, reg) p2sb_port_read_4(sc->p2sb, sc->port, reg)

sys/dev/p2sb/lewisburg_gpiocm.c

55

#define LBGGPIOCM_WRITE(sc, reg, val) \

sys/dev/p2sb/lewisburg_gpiocm.c

56

p2sb_port_write_4(sc->p2sb, sc->port, reg, val)

sys/dev/p2sb/p2sb.c

83

p2sb_port_read_4(device_t dev, uint8_t port, uint32_t reg)

sys/dev/p2sb/p2sb.c

87

KASSERT(reg < (1<<P2SB_PORT2ADDRESS_SHIFT), ("register out of port"));

sys/dev/p2sb/p2sb.c

89

return (bus_read_4(sc->res, P2SB_PORT_ADDRESS(port) + reg));

sys/dev/p2sb/p2sb.c

93

p2sb_port_write_4(device_t dev, uint8_t port, uint32_t reg, uint32_t val)

sys/dev/p2sb/p2sb.c

97

KASSERT(reg < (1<<P2SB_PORT2ADDRESS_SHIFT), ("register out of port"));

sys/dev/p2sb/p2sb.c

99

bus_write_4(sc->res, P2SB_PORT_ADDRESS(port) + reg, val);

sys/dev/p2sb/p2sb.h

7

uint32_t p2sb_port_read_4(device_t dev, uint8_t port, uint32_t reg);

sys/dev/p2sb/p2sb.h

8

void p2sb_port_write_4(device_t dev, uint8_t port, uint32_t reg, uint32_t val);

sys/dev/pccbb/pccbb.c

1070

uint32_t reg;

sys/dev/pccbb/pccbb.c

1123

reg = pci_read_config(sc->dev, CBBR_BRIDGECTRL, 2);

sys/dev/pccbb/pccbb.c

1124

reg &= ~(CBBM_BRIDGECTRL_PREFETCH_0 |

sys/dev/pccbb/pccbb.c

1127

reg |= CBBM_BRIDGECTRL_PREFETCH_1;

sys/dev/pccbb/pccbb.c

1128

pci_write_config(sc->dev, CBBR_BRIDGECTRL, reg, 2);

sys/dev/pccbb/pccbb.c

247

uint8_t reg;

sys/dev/pccbb/pccbb.c

249

reg = (exca_getb(&sc->exca, EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) |

sys/dev/pccbb/pccbb.c

251

exca_putb(&sc->exca, EXCA_INTR, reg);

sys/dev/pccbb/pccbb.c

265

uint8_t reg;

sys/dev/pccbb/pccbb.c

267

reg = (exca_getb(&sc->exca, EXCA_INTR) & ~EXCA_INTR_IRQ_MASK) |

sys/dev/pccbb/pccbb.c

271

exca_putb(&sc->exca, EXCA_INTR, reg);

sys/dev/pccbb/pccbb.c

633

uint8_t reg;

sys/dev/pccbb/pccbb.c

664

reg = exca_getb(&sc->exca, EXCA_INTR);

sys/dev/pccbb/pccbb.c

665

exca_putb(&sc->exca, EXCA_INTR, (reg & 0xf0) | 1);

sys/dev/pccbb/pccbb.c

666

return (reg);

sys/dev/pccbb/pccbb.c

675

cbb_o2micro_power_hack2(struct cbb_softc *sc, uint8_t reg)

sys/dev/pccbb/pccbb.c

677

exca_putb(&sc->exca, EXCA_INTR, reg);

sys/dev/pccbb/pccbb.c

688

uint8_t reg = 0;

sys/dev/pccbb/pccbb.c

724

reg = cbb_o2micro_power_hack(sc);

sys/dev/pccbb/pccbb.c

833

cbb_o2micro_power_hack2(sc, reg);

sys/dev/pccbb/pccbb_pci.c

409

uint32_t mux, sysctrl, reg;

sys/dev/pccbb/pccbb_pci.c

534

reg = exca_getb(&sc->exca, EXCA_O2MICRO_CTRL_C);

sys/dev/pccbb/pccbb_pci.c

535

reg = (reg & 0x0f) |

sys/dev/pccbb/pccbb_pci.c

537

exca_putb(&sc->exca, EXCA_O2MICRO_CTRL_C, reg);

sys/dev/pccbb/pccbb_pci.c

811

cbb_read_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, int width)

sys/dev/pccbb/pccbb_pci.c

817

b, s, f, reg, width));

sys/dev/pccbb/pccbb_pci.c

821

cbb_write_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, uint32_t val,

sys/dev/pccbb/pccbb_pci.c

828

b, s, f, reg, val, width);

sys/dev/pccbb/pccbbvar.h

145

cbb_set(struct cbb_softc *sc, uint32_t reg, uint32_t val)

sys/dev/pccbb/pccbbvar.h

147

bus_space_write_4(sc->bst, sc->bsh, reg, val);

sys/dev/pccbb/pccbbvar.h

151

cbb_get(struct cbb_softc *sc, uint32_t reg)

sys/dev/pccbb/pccbbvar.h

153

return (bus_space_read_4(sc->bst, sc->bsh, reg));

sys/dev/pccbb/pccbbvar.h

157

cbb_setb(struct cbb_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pccbb/pccbbvar.h

159

cbb_set(sc, reg, cbb_get(sc, reg) | bits);

sys/dev/pccbb/pccbbvar.h

163

cbb_clrb(struct cbb_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pccbb/pccbbvar.h

165

cbb_set(sc, reg, cbb_get(sc, reg) & ~bits);

sys/dev/pci/controller/pci_n1sdp.c

231

n1sdp_get_bus_space(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,

sys/dev/pci/controller/pci_n1sdp.c

251

reg);

sys/dev/pci/controller/pci_n1sdp.c

258

u_int func, u_int reg, int bytes)

sys/dev/pci/controller/pci_n1sdp.c

275

(reg > PCIE_REGMAX))

sys/dev/pci/controller/pci_n1sdp.c

278

if (n1sdp_get_bus_space(dev, bus, slot, func, reg, &t, &h, &offset) !=0)

sys/dev/pci/controller/pci_n1sdp.c

304

u_int func, u_int reg, uint32_t val, int bytes)

sys/dev/pci/controller/pci_n1sdp.c

321

(reg > PCIE_REGMAX))

sys/dev/pci/controller/pci_n1sdp.c

324

if (n1sdp_get_bus_space(dev, bus, slot, func, reg, &t, &h, &offset) !=0)

sys/dev/pci/hostb_pci.c

118

pci_hostb_read_config(device_t dev, device_t child, int reg, int width)

sys/dev/pci/hostb_pci.c

121

return (pci_read_config(dev, reg, width));

sys/dev/pci/hostb_pci.c

125

pci_hostb_write_config(device_t dev, device_t child, int reg,

sys/dev/pci/hostb_pci.c

129

pci_write_config(dev, reg, val, width);

sys/dev/pci/pci.c

1048

pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)

sys/dev/pci/pci.c

1052

KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));

sys/dev/pci/pci.c

1054

WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);

sys/dev/pci/pci.c

1068

pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)

sys/dev/pci/pci.c

1072

KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));

sys/dev/pci/pci.c

1075

WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);

sys/dev/pci/pci.c

1101

uint32_t reg;

sys/dev/pci/pci.c

1105

if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, &reg))

sys/dev/pci/pci.c

1107

vrs->val = le32toh(reg);

sys/dev/pci/pci.c

114

static int pci_add_map(device_t bus, device_t dev, int reg,

sys/dev/pci/pci.c

125

int reg, uint32_t *data);

sys/dev/pci/pci.c

128

int reg, uint32_t data);

sys/dev/pci/pci.c

2323

pcie_read_config(device_t dev, int reg, int width)

sys/dev/pci/pci.c

2335

return (pci_read_config(dev, cap + reg, width));

sys/dev/pci/pci.c

2339

pcie_write_config(device_t dev, int reg, uint32_t value, int width)

sys/dev/pci/pci.c

2347

pci_write_config(dev, cap + reg, value, width);

sys/dev/pci/pci.c

2358

pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value,

sys/dev/pci/pci.c

2372

old = pci_read_config(dev, cap + reg, width);

sys/dev/pci/pci.c

2375

pci_write_config(dev, cap + reg, new, width);

sys/dev/pci/pci.c

3154

pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp,

sys/dev/pci/pci.c

3168

if (PCIR_IS_BIOS(&dinfo->cfg, reg)) {

sys/dev/pci/pci.c

3169

map = pci_read_config(dev, reg, 4);

sys/dev/pci/pci.c

3170

pci_write_config(dev, reg, 0xfffffffe, 4);

sys/dev/pci/pci.c

3171

testval = pci_read_config(dev, reg, 4);

sys/dev/pci/pci.c

3172

pci_write_config(dev, reg, map, 4);

sys/dev/pci/pci.c

3180

map = pci_read_config(dev, reg, 4);

sys/dev/pci/pci.c

3183

map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;

sys/dev/pci/pci.c

3207

pci_write_config(dev, reg, 0xffffffff, 4);

sys/dev/pci/pci.c

3209

pci_write_config(dev, reg + 4, 0xffffffff, 4);

sys/dev/pci/pci.c

3210

testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;

sys/dev/pci/pci.c

3212

testval |= pci_read_config(dev, reg, 4);

sys/dev/pci/pci.c

3219

pci_write_config(dev, reg, map, 4);

sys/dev/pci/pci.c

3221

pci_write_config(dev, reg + 4, map >> 32, 4);

sys/dev/pci/pci.c

3252

pci_find_bar(device_t dev, int reg)

sys/dev/pci/pci.c

3259

if (pm->pm_reg == reg)

sys/dev/pci/pci.c

3308

pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size)

sys/dev/pci/pci.c

3315

pm->pm_reg = reg;

sys/dev/pci/pci.c

3320

reg));

sys/dev/pci/pci.c

3357

pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,

sys/dev/pci/pci.c

3371

pm = pci_find_bar(dev, reg);

sys/dev/pci/pci.c

3378

pci_read_bar(dev, reg, &map, &testval, NULL);

sys/dev/pci/pci.c

3409

pm = pci_add_bar(dev, reg, map, mapsize);

sys/dev/pci/pci.c

3412

reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);

sys/dev/pci/pci.c

3438

pci_get_function(dev), reg);

sys/dev/pci/pci.c

3479

resource_list_add(rl, type, reg, start, end, count);

sys/dev/pci/pci.c

3487

res = resource_list_reserve(rl, bus, dev, type, reg, start, end, count,

sys/dev/pci/pci.c

3498

resource_list_delete(rl, type, reg);

sys/dev/pci/pci.c

3499

resource_list_add(rl, type, reg, 0, ~0, count);

sys/dev/pci/pci.c

3500

res = resource_list_reserve(rl, bus, dev, type, reg, 0, ~0,

sys/dev/pci/pci.c

3512

resource_list_delete(rl, type, reg);

sys/dev/pci/pci.c

3518

pci_get_slot(dev), pci_get_function(dev), reg);

sys/dev/pci/pci.c

6055

pci_read_config_method(device_t dev, device_t child, int reg, int width)

sys/dev/pci/pci.c

6066

if (reg == PCIR_VENDOR) {

sys/dev/pci/pci.c

6077

} else if (reg == PCIR_DEVICE) {

sys/dev/pci/pci.c

6092

cfg->bus, cfg->slot, cfg->func, reg, width));

sys/dev/pci/pci.c

6096

pci_write_config_method(device_t dev, device_t child, int reg,

sys/dev/pci/pci.c

6103

cfg->bus, cfg->slot, cfg->func, reg, val, width);

sys/dev/pci/pci.c

87

#define PCIR_IS_BIOS(cfg, reg) \

sys/dev/pci/pci.c

88

(((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \

sys/dev/pci/pci.c

89

((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))

sys/dev/pci/pci_dw.c

100

return (bus_read_2(sc->dbi_res, reg));

sys/dev/pci/pci_dw.c

102

return (bus_read_1(sc->dbi_res, reg));

sys/dev/pci/pci_dw.c

110

pci_dw_dbi_write(device_t dev, u_int reg, uint32_t val, int width)

sys/dev/pci/pci_dw.c

117

reg, val, width);

sys/dev/pci/pci_dw.c

121

bus_write_4(sc->dbi_res, reg, val);

sys/dev/pci/pci_dw.c

124

bus_write_2(sc->dbi_res, reg, val);

sys/dev/pci/pci_dw.c

127

bus_write_1(sc->dbi_res, reg, val);

sys/dev/pci/pci_dw.c

138

uint32_t reg;

sys/dev/pci/pci_dw.c

140

reg = DBI_RD4(sc, DW_MISC_CONTROL_1);

sys/dev/pci/pci_dw.c

142

reg &= ~DBI_RO_WR_EN;

sys/dev/pci/pci_dw.c

144

reg |= DBI_RO_WR_EN;

sys/dev/pci/pci_dw.c

145

DBI_WR4(sc, DW_MISC_CONTROL_1, reg);

sys/dev/pci/pci_dw.c

150

u_int reg)

sys/dev/pci/pci_dw.c

156

func > PCI_FUNCMAX || reg > PCIE_REGMAX)

sys/dev/pci/pci_dw.c

183

uint32_t reg;

sys/dev/pci/pci_dw.c

190

reg = IATU_UR_RD4(sc, DW_IATU_UR_REG(i, LWR_TARGET_ADDR));

sys/dev/pci/pci_dw.c

191

if (reg != 0x12340000)

sys/dev/pci/pci_dw.c

204

uint32_t reg;

sys/dev/pci/pci_dw.c

208

reg = DBI_RD4(sc, DW_IATU_VIEWPORT);

sys/dev/pci/pci_dw.c

209

if (reg > IATU_REGION_INDEX(~0U)) {

sys/dev/pci/pci_dw.c

212

reg);

sys/dev/pci/pci_dw.c

216

num_viewports = reg + 1;

sys/dev/pci/pci_dw.c

225

reg = DBI_RD4(sc, DW_IATU_LWR_TARGET_ADDR);

sys/dev/pci/pci_dw.c

226

if (reg != 0x12340000)

sys/dev/pci/pci_dw.c

248

uint32_t reg;

sys/dev/pci/pci_dw.c

271

reg = IATU_UR_RD4(sc, DW_IATU_UR_REG(idx, CTRL2));

sys/dev/pci/pci_dw.c

272

if (reg & IATU_CTRL2_REGION_EN)

sys/dev/pci/pci_dw.c

286

uint32_t reg;

sys/dev/pci/pci_dw.c

303

reg = DBI_RD4(sc, DW_IATU_CTRL2);

sys/dev/pci/pci_dw.c

304

if (reg & IATU_CTRL2_REGION_EN)

sys/dev/pci/pci_dw.c

330

uint32_t reg;

sys/dev/pci/pci_dw.c

370

reg = DBI_RD4(sc, DW_PORT_LINK_CTRL);

sys/dev/pci/pci_dw.c

371

reg &= ~PORT_LINK_CAPABLE(~0);

sys/dev/pci/pci_dw.c

374

reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_1);

sys/dev/pci/pci_dw.c

377

reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_2);

sys/dev/pci/pci_dw.c

380

reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_4);

sys/dev/pci/pci_dw.c

383

reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_8);

sys/dev/pci/pci_dw.c

386

reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_16);

sys/dev/pci/pci_dw.c

389

reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_32);

sys/dev/pci/pci_dw.c

397

DBI_WR4(sc, DW_PORT_LINK_CTRL, reg);

sys/dev/pci/pci_dw.c

400

reg = DBI_RD4(sc, DW_GEN2_CTRL);

sys/dev/pci/pci_dw.c

401

reg &= ~GEN2_CTRL_NUM_OF_LANES(~0);

sys/dev/pci/pci_dw.c

404

reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_1);

sys/dev/pci/pci_dw.c

407

reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_2);

sys/dev/pci/pci_dw.c

410

reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_4);

sys/dev/pci/pci_dw.c

413

reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_8);

sys/dev/pci/pci_dw.c

416

reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_16);

sys/dev/pci/pci_dw.c

419

reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_32);

sys/dev/pci/pci_dw.c

422

DBI_WR4(sc, DW_GEN2_CTRL, reg);

sys/dev/pci/pci_dw.c

424

reg = DBI_RD4(sc, DW_GEN2_CTRL);

sys/dev/pci/pci_dw.c

425

reg |= DIRECT_SPEED_CHANGE;

sys/dev/pci/pci_dw.c

426

DBI_WR4(sc, DW_GEN2_CTRL, reg);

sys/dev/pci/pci_dw.c

519

u_int func, u_int reg, int bytes)

sys/dev/pci/pci_dw.c

529

if (!pci_dw_check_dev(sc, bus, slot, func, reg))

sys/dev/pci/pci_dw.c

550

data = bus_read_1(res, reg);

sys/dev/pci/pci_dw.c

553

data = bus_read_2(res, reg);

sys/dev/pci/pci_dw.c

556

data = bus_read_4(res, reg);

sys/dev/pci/pci_dw.c

568

u_int func, u_int reg, uint32_t val, int bytes)

sys/dev/pci/pci_dw.c

576

if (!pci_dw_check_dev(sc, bus, slot, func, reg))

sys/dev/pci/pci_dw.c

597

bus_write_1(res, reg, val);

sys/dev/pci/pci_dw.c

600

bus_write_2(res, reg, val);

sys/dev/pci/pci_dw.c

603

bus_write_4(res, reg, val);

sys/dev/pci/pci_dw.c

64

#define DBI_WR1(sc, reg, val) pci_dw_dbi_wr1((sc)->dev, reg, val)

sys/dev/pci/pci_dw.c

65

#define DBI_WR2(sc, reg, val) pci_dw_dbi_wr2((sc)->dev, reg, val)

sys/dev/pci/pci_dw.c

66

#define DBI_WR4(sc, reg, val) pci_dw_dbi_wr4((sc)->dev, reg, val)

sys/dev/pci/pci_dw.c

67

#define DBI_RD1(sc, reg) pci_dw_dbi_rd1((sc)->dev, reg)

sys/dev/pci/pci_dw.c

68

#define DBI_RD2(sc, reg) pci_dw_dbi_rd2((sc)->dev, reg)

sys/dev/pci/pci_dw.c

69

#define DBI_RD4(sc, reg) pci_dw_dbi_rd4((sc)->dev, reg)

sys/dev/pci/pci_dw.c

71

#define IATU_UR_WR4(sc, reg, val) \

sys/dev/pci/pci_dw.c

72

bus_write_4((sc)->iatu_ur_res, (sc)->iatu_ur_offset + (reg), (val))

sys/dev/pci/pci_dw.c

73

#define IATU_UR_RD4(sc, reg) \

sys/dev/pci/pci_dw.c

74

bus_read_4((sc)->iatu_ur_res, (sc)->iatu_ur_offset + (reg))

sys/dev/pci/pci_dw.c

89

pci_dw_dbi_read(device_t dev, u_int reg, int width)

sys/dev/pci/pci_dw.c

95

dprintf("%s: reg: 0x%04X, width: %d\n", __func__, reg, width);

sys/dev/pci/pci_dw.c

98

return (bus_read_4(sc->dbi_res, reg));

sys/dev/pci/pci_dw.h

135

pci_dw_dbi_wr4(device_t dev, u_int reg, uint32_t val)

sys/dev/pci/pci_dw.h

137

PCI_DW_DBI_WRITE(dev, reg, val, 4);

sys/dev/pci/pci_dw.h

141

pci_dw_dbi_wr2(device_t dev, u_int reg, uint16_t val)

sys/dev/pci/pci_dw.h

143

PCI_DW_DBI_WRITE(dev, reg, val, 2);

sys/dev/pci/pci_dw.h

147

pci_dw_dbi_wr1(device_t dev, u_int reg, uint8_t val)

sys/dev/pci/pci_dw.h

149

PCI_DW_DBI_WRITE(dev, reg, val, 1);

sys/dev/pci/pci_dw.h

153

pci_dw_dbi_rd4(device_t dev, u_int reg)

sys/dev/pci/pci_dw.h

155

return (PCI_DW_DBI_READ(dev, reg, 4));

sys/dev/pci/pci_dw.h

159

pci_dw_dbi_rd2(device_t dev, u_int reg)

sys/dev/pci/pci_dw.h

161

return ((uint16_t)PCI_DW_DBI_READ(dev, reg, 2));

sys/dev/pci/pci_dw.h

165

pci_dw_dbi_rd1(device_t dev, u_int reg)

sys/dev/pci/pci_dw.h

167

return ((uint8_t)PCI_DW_DBI_READ(dev, reg, 1));

sys/dev/pci/pci_dw_mv.c

141

uint32_t reg;

sys/dev/pci/pci_dw_mv.c

144

reg = pci_dw_dbi_rd4(sc->dev, MV_GLOBAL_CONTROL_REG);

sys/dev/pci/pci_dw_mv.c

145

reg &= ~0x000000F0;

sys/dev/pci/pci_dw_mv.c

146

reg |= 0x000000040;

sys/dev/pci/pci_dw_mv.c

147

pci_dw_dbi_wr4(sc->dev, MV_GLOBAL_CONTROL_REG, reg);

sys/dev/pci/pci_dw_mv.c

158

reg = pci_dw_dbi_rd4(sc->dev, MV_INT_MASK1);

sys/dev/pci/pci_dw_mv.c

159

reg |= INT_A_ASSERT_MASK | INT_B_ASSERT_MASK |

sys/dev/pci/pci_dw_mv.c

161

pci_dw_dbi_wr4(sc->dev, MV_INT_MASK1, reg);

sys/dev/pci/pci_dw_mv.c

191

uint32_t reg;

sys/dev/pci/pci_dw_mv.c

193

reg = pci_dw_dbi_rd4(dev, MV_GLOBAL_STATUS_REG);

sys/dev/pci/pci_dw_mv.c

194

if ((reg & (MV_STATUS_RDLH_LINK_UP | MV_STATUS_PHY_LINK_UP)) ==

sys/dev/pci/pci_host_generic.c

298

u_int func, u_int reg, int bytes)

sys/dev/pci/pci_host_generic.c

308

(reg > PCIE_REGMAX))

sys/dev/pci/pci_host_generic.c

313

offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);

sys/dev/pci/pci_host_generic.c

334

u_int func, u_int reg, uint32_t val, int bytes)

sys/dev/pci/pci_host_generic.c

343

(reg > PCIE_REGMAX))

sys/dev/pci/pci_host_generic.c

346

offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);

sys/dev/pci/pci_host_generic.c

72

u_int func, u_int reg, int bytes);

sys/dev/pci/pci_host_generic.c

74

u_int func, u_int reg, uint32_t val, int bytes);

sys/dev/pci/pci_host_generic.h

46

#define PCIE_ADDR_OFFSET(bus, slot, func, reg) \

sys/dev/pci/pci_host_generic.h

50

((reg) & PCIE_REG_MASK))

sys/dev/pci/pci_host_generic_acpi.c

76

#define PCIE_ADDR_OFFSET(bus, slot, func, reg) \

sys/dev/pci/pci_host_generic_acpi.c

80

((reg) & PCIE_REG_MASK))

sys/dev/pci/pci_host_generic_den0115.c

203

u_int func, u_int reg, int bytes)

sys/dev/pci/pci_host_generic_den0115.c

214

(reg > PCIE_REGMAX))

sys/dev/pci/pci_host_generic_den0115.c

218

if (arm_smccc_invoke(SMCCC_PCI_READ, addr, reg, bytes, &result) < 0) {

sys/dev/pci/pci_host_generic_den0115.c

227

u_int func, u_int reg, uint32_t val, int bytes)

sys/dev/pci/pci_host_generic_den0115.c

238

(reg > PCIE_REGMAX))

sys/dev/pci/pci_host_generic_den0115.c

242

arm_smccc_invoke(SMCCC_PCI_WRITE, addr, reg, bytes, val, &result);

sys/dev/pci/pci_host_generic_fdt.c

251

struct ofw_pci_register reg;

sys/dev/pci/pci_host_generic_fdt.c

259

bzero(&reg, sizeof(reg));

sys/dev/pci/pci_host_generic_fdt.c

260

reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |

sys/dev/pci/pci_host_generic_fdt.c

265

&sc->pci_iinfo, &reg, sizeof(reg), &pintr, sizeof(pintr),

sys/dev/pci/pci_host_generic_fdt.c

442

pcell_t reg[5];

sys/dev/pci/pci_host_generic_fdt.c

452

len = OF_getencprop(node, "reg", reg, sizeof(reg));

sys/dev/pci/pci_host_generic_fdt.c

462

di->func = OFW_PCI_PHYS_HI_FUNCTION(reg[0]);

sys/dev/pci/pci_host_generic_fdt.c

463

di->slot = OFW_PCI_PHYS_HI_DEVICE(reg[0]);

sys/dev/pci/pci_host_generic_fdt.c

464

di->bus = OFW_PCI_PHYS_HI_BUS(reg[0]);

sys/dev/pci/pci_pci.c

1774

rid = w->reg;

sys/dev/pci/pci_pci.c

2442

pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)

sys/dev/pci/pci_pci.c

2461

f, reg, width));

sys/dev/pci/pci_pci.c

2465

pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width)

sys/dev/pci/pci_pci.c

2476

reg, val, width);

sys/dev/pci/pci_pci.c

372

rid = w->reg;

sys/dev/pci/pci_pci.c

404

sc->io.reg, as.res[i]);

sys/dev/pci/pci_pci.c

466

rid = w->reg;

sys/dev/pci/pci_pci.c

517

sc->io.reg = PCIR_IOBASEL_1;

sys/dev/pci/pci_pci.c

539

sc->mem.reg = PCIR_MEMBASE_1;

sys/dev/pci/pci_pci.c

566

sc->pmem.reg = PCIR_PMBASEL_1;

sys/dev/pci/pci_pci.c

78

u_int f, u_int reg, int width);

sys/dev/pci/pci_pci.c

80

u_int f, u_int reg, uint32_t val, int width);

sys/dev/pci/pci_private.h

144

void pci_read_bar(device_t dev, int reg, pci_addr_t *mapp,

sys/dev/pci/pci_private.h

146

struct pci_map *pci_add_bar(device_t dev, int reg, pci_addr_t value,

sys/dev/pci/pcib_private.h

136

typedef uint32_t pci_read_config_fn(int d, int b, int s, int f, int reg,

sys/dev/pci/pcib_private.h

77

int reg; /* resource id from parent */

sys/dev/pci/pcireg.h

671

#define PCIM_EA_SEC_NR(reg) ((reg) & 0xff)

sys/dev/pci/pcireg.h

672

#define PCIM_EA_SUB_NR(reg) (((reg) >> 8) & 0xff)

sys/dev/pci/pcivar.h

400

pci_read_config(device_t dev, int reg, int width)

sys/dev/pci/pcivar.h

402

return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);

sys/dev/pci/pcivar.h

406

pci_write_config(device_t dev, int reg, uint32_t val, int width)

sys/dev/pci/pcivar.h

408

PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);

sys/dev/pci/pcivar.h

705

uint32_t pcie_read_config(device_t dev, int reg, int width);

sys/dev/pci/pcivar.h

706

void pcie_write_config(device_t dev, int reg, uint32_t value, int width);

sys/dev/pci/pcivar.h

707

uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask,

sys/dev/pci/pcivar.h

732

struct pci_map *pci_find_bar(device_t dev, int reg);

sys/dev/pci/vga_pci.c

491

vga_pci_read_config(device_t dev, device_t child, int reg, int width)

sys/dev/pci/vga_pci.c

494

return (pci_read_config(dev, reg, width));

sys/dev/pci/vga_pci.c

498

vga_pci_write_config(device_t dev, device_t child, int reg,

sys/dev/pci/vga_pci.c

502

pci_write_config(dev, reg, val, width);

sys/dev/pms/freebsd/driver/common/lxcommon.h

224

U16 reg; /* pci memory bar number */

sys/dev/powermac_nvram/powermac_nvram.c

133

u_int32_t reg[3];

sys/dev/powermac_nvram/powermac_nvram.c

139

if ((i = OF_getprop(node, "reg", reg, sizeof(reg))) < 8)

sys/dev/powermac_nvram/powermac_nvram.c

157

sc->sc_bank0 = pmap_mapdev(reg[i], NVRAM_SIZE * 2);

sys/dev/ppbus/ppb_msq.h

109

#define MS_RSET(reg,assert,clear) { MS_OP_RSET, {{ (reg) }, { (assert) }, { (clear) }}}

sys/dev/ppbus/ppb_msq.h

110

#define MS_RASSERT(reg,byte) { MS_OP_RASSERT, { { (reg) }, { (byte) }}}

sys/dev/ppbus/ppb_msq.h

111

#define MS_RCLR(reg,clear) { MS_OP_RSET, {{ (reg) }, { MS_ASSERT_NONE }, { (clear) }}}

sys/dev/ppbus/ppb_msq.h

112

#define MS_RFETCH(reg,mask,ptr) { MS_OP_RFETCH, {{ (reg) }, { (mask) }, { (ptr) }}}

sys/dev/ppbus/ppb_msq.h

115

#define MS_TRIG(reg,len,array) { MS_OP_TRIG, {{ (reg) }, { (len) }, { (array) }}}

sys/dev/ppbus/ppb_msq.h

118

#define MS_RASSERT_P(n,reg) { MS_OP_RASSERT_P, {{ (n) }, { (reg) }}}

sys/dev/ppbus/ppb_msq.h

119

#define MS_RFETCH_P(n,reg,mask) { MS_OP_RFETCH_P, {{ (n) }, { (reg) }, { (mask) }}}

sys/dev/ppc/ppc.c

1320

int reg;

sys/dev/ppc/ppc.c

1329

#define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg))

sys/dev/ppc/ppc.c

1330

#define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte))

sys/dev/ppc/ppc.c

1347

reg = mi->arg[1].i;

sys/dev/ppc/ppc.c

1353

w_reg(reg, ppc, *ptr++);

sys/dev/ppc/ppc.c

1357

w_reg(reg, ppc, *ptr++);

sys/dev/ppc/ppc.c

1364

reg = mi->arg[1].i;

sys/dev/ppc/ppc.c

1371

*ptr++ = r_reg(reg, ppc) & mask;

sys/dev/ppc/ppc.c

1375

*ptr++ = r_reg(reg, ppc) & mask;

sys/dev/ppc/ppc.c

1412

reg = mi->arg[0].i;

sys/dev/ppc/ppc.c

1418

w_reg(reg, ppc, *p++);

sys/dev/pst/pst-iop.c

162

sc->reg->oqueue_intr_mask = 0x0;

sys/dev/pst/pst-iop.c

175

if ((mfa = sc->reg->oqueue) == 0xffffffff)

sys/dev/pst/pst-iop.c

176

if ((mfa = sc->reg->oqueue) == 0xffffffff)

sys/dev/pst/pst-iop.c

221

sc->reg->iqueue = mfa;

sys/dev/pst/pst-iop.c

228

while ((mfa = sc->reg->iqueue) == 0xffffffff && --timeout)

sys/dev/pst/pst-iop.c

270

sc->reg->iqueue = mfa;

sys/dev/pst/pst-iop.c

284

sc->reg->oqueue = sc->phys_obase + (i * I2O_IOP_OUTBOUND_FRAME_SIZE);

sys/dev/pst/pst-iop.c

390

while ((mfa = sc->reg->iqueue) == 0xffffffff && timeout) {

sys/dev/pst/pst-iop.c

411

sc->reg->iqueue = mfa;

sys/dev/pst/pst-iop.c

434

if ((sc->reg->oqueue_intr_mask & I2O_OUT_INTR_QUEUE) == 0) {

sys/dev/pst/pst-iop.c

437

sc->reg->iqueue = mfa;

sys/dev/pst/pst-iop.c

445

sc->reg->oqueue = request.mfa;

sys/dev/pst/pst-iop.c

448

sc->reg->iqueue = mfa;

sys/dev/pst/pst-iop.c

449

while (--timeout && ((out_mfa = sc->reg->oqueue) == 0xffffffff))

sys/dev/pst/pst-iop.c

459

sc->reg->oqueue = out_mfa;

sys/dev/pst/pst-iop.c

64

while ((mfa = sc->reg->iqueue) == 0xffffffff && --timeout)

sys/dev/pst/pst-iop.c

72

sc->reg->oqueue_intr_mask = 0xffffffff;

sys/dev/pst/pst-iop.h

47

struct i2o_registers *reg;

sys/dev/pst/pst-pci.c

91

sc->reg = (struct i2o_registers *)sc->ibase;

sys/dev/pst/pst-raid.c

188

psc->iop->reg->oqueue_intr_mask = 0xffffffff;

sys/dev/pst/pst-raid.c

261

psc->iop->reg->oqueue = mfa;

sys/dev/pst/pst-raid.c

307

request->psc->iop->reg->iqueue = request->mfa;

sys/dev/pwm/controller/allwinner/aw_pwm.c

109

#define AW_PWM_READ(sc, reg) bus_read_4((sc)->res, (reg))

sys/dev/pwm/controller/allwinner/aw_pwm.c

110

#define AW_PWM_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/dev/pwm/controller/allwinner/aw_pwm.c

134

uint32_t reg;

sys/dev/pwm/controller/allwinner/aw_pwm.c

165

reg = AW_PWM_READ(sc, AW_PWM_CTRL);

sys/dev/pwm/controller/allwinner/aw_pwm.c

166

if (reg & (AW_PWM_CTRL_GATE | AW_PWM_CTRL_EN))

sys/dev/pwm/controller/allwinner/aw_pwm.c

169

reg = AW_PWM_READ(sc, AW_PWM_CTRL);

sys/dev/pwm/controller/allwinner/aw_pwm.c

170

reg &= AW_PWM_CTRL_PRESCALE_MASK;

sys/dev/pwm/controller/allwinner/aw_pwm.c

171

if (reg > nitems(aw_pwm_clk_prescaler)) {

sys/dev/pwm/controller/allwinner/aw_pwm.c

172

device_printf(dev, "Bad prescaler %x, cannot guess current settings\n", reg);

sys/dev/pwm/controller/allwinner/aw_pwm.c

175

clk_freq = sc->clk_freq / aw_pwm_clk_prescaler[reg];

sys/dev/pwm/controller/allwinner/aw_pwm.c

177

reg = AW_PWM_READ(sc, AW_PWM_PERIOD);

sys/dev/pwm/controller/allwinner/aw_pwm.c

179

(clk_freq / ((reg >> AW_PWM_PERIOD_TOTAL_SHIFT) & AW_PWM_PERIOD_TOTAL_MASK));

sys/dev/pwm/controller/allwinner/aw_pwm.c

181

(clk_freq / ((reg >> AW_PWM_PERIOD_ACTIVE_SHIFT) & AW_PWM_PERIOD_ACTIVE_MASK));

sys/dev/pwm/controller/allwinner/aw_pwm.c

246

uint32_t reg;

sys/dev/pwm/controller/allwinner/aw_pwm.c

295

reg = AW_PWM_READ(sc, AW_PWM_CTRL);

sys/dev/pwm/controller/allwinner/aw_pwm.c

298

reg &= ~AW_PWM_CTRL_PRESCALE_MASK;

sys/dev/pwm/controller/allwinner/aw_pwm.c

299

reg |= prescaler;

sys/dev/pwm/controller/allwinner/aw_pwm.c

301

reg &= ~AW_PWM_CTRL_MODE_MASK;

sys/dev/pwm/controller/allwinner/aw_pwm.c

302

reg |= AW_PWM_CTRL_CYCLE_MODE;

sys/dev/pwm/controller/allwinner/aw_pwm.c

304

reg &= ~AW_PWM_CTRL_PULSE_START;

sys/dev/pwm/controller/allwinner/aw_pwm.c

305

reg &= ~AW_PWM_CTRL_CLK_BYPASS;

sys/dev/pwm/controller/allwinner/aw_pwm.c

307

AW_PWM_WRITE(sc, AW_PWM_CTRL, reg);

sys/dev/pwm/controller/allwinner/aw_pwm.c

310

reg = ((clk_rate / period_freq - 1) << AW_PWM_PERIOD_TOTAL_SHIFT) |

sys/dev/pwm/controller/allwinner/aw_pwm.c

312

AW_PWM_WRITE(sc, AW_PWM_PERIOD, reg);

sys/dev/pwm/controller/allwinner/aw_pwm.c

337

uint32_t reg;

sys/dev/pwm/controller/allwinner/aw_pwm.c

344

reg = AW_PWM_READ(sc, AW_PWM_CTRL);

sys/dev/pwm/controller/allwinner/aw_pwm.c

346

reg |= AW_PWM_CTRL_GATE | AW_PWM_CTRL_EN;

sys/dev/pwm/controller/allwinner/aw_pwm.c

348

reg &= ~(AW_PWM_CTRL_GATE | AW_PWM_CTRL_EN);

sys/dev/pwm/controller/allwinner/aw_pwm.c

350

AW_PWM_WRITE(sc, AW_PWM_CTRL, reg);

sys/dev/pwm/controller/rockchip/rk_pwm.c

123

#define RK_PWM_READ(sc, reg) bus_read_4((sc)->res, (reg))

sys/dev/pwm/controller/rockchip/rk_pwm.c

124

#define RK_PWM_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/dev/pwm/controller/rockchip/rk_pwm.c

149

uint32_t reg;

sys/dev/pwm/controller/rockchip/rk_pwm.c

178

reg = RK_PWM_READ(sc, RK_PWM_CTRL);

sys/dev/pwm/controller/rockchip/rk_pwm.c

179

if ((reg & RK_PWM_CTRL_ENABLE_MASK) == RK_PWM_CTRL_ENABLED)

sys/dev/pwm/controller/rockchip/rk_pwm.c

182

reg = RK_PWM_READ(sc, RK_PWM_CTRL);

sys/dev/pwm/controller/rockchip/rk_pwm.c

183

reg &= RK_PWM_CTRL_PRESCALE_MASK;

sys/dev/pwm/controller/rockchip/rk_pwm.c

184

sc->prescaler = reg >> RK_PWM_CTRL_PRESCALE_SHIFT;

sys/dev/pwm/controller/rockchip/rk_pwm.c

186

reg = RK_PWM_READ(sc, RK_PWM_CTRL);

sys/dev/pwm/controller/rockchip/rk_pwm.c

187

reg &= RK_PWM_CTRL_SCALE_MASK;

sys/dev/pwm/controller/rockchip/rk_pwm.c

188

sc->scaler = reg >> RK_PWM_CTRL_SCALE_SHIFT;

sys/dev/pwm/controller/rockchip/rk_pwm.c

190

reg = RK_PWM_READ(sc, RK_PWM_CTRL);

sys/dev/pwm/controller/rockchip/rk_pwm.c

191

if ((reg & RK_PWM_CTRL_CLOCKSRC_MASK) == RK_PWM_CTRL_CLOCKSRC_SCALED)

sys/dev/pwm/controller/rockchip/rk_pwm.c

205

reg = RK_PWM_READ(sc, RK_PWM_PERIOD);

sys/dev/pwm/controller/rockchip/rk_pwm.c

207

(clk_freq / reg);

sys/dev/pwm/controller/rockchip/rk_pwm.c

208

reg = RK_PWM_READ(sc, RK_PWM_DUTY);

sys/dev/pwm/controller/rockchip/rk_pwm.c

210

(clk_freq / reg);

sys/dev/pwm/controller/rockchip/rk_pwm.c

269

uint32_t reg;

sys/dev/pwm/controller/rockchip/rk_pwm.c

298

reg = RK_PWM_READ(sc, RK_PWM_CTRL);

sys/dev/pwm/controller/rockchip/rk_pwm.c

300

if ((reg & RK_PWM_CTRL_MODE_MASK) != RK_PWM_CTRL_MODE_CONTINUOUS) {

sys/dev/pwm/controller/rockchip/rk_pwm.c

302

SET(reg, RK_PWM_CTRL_ENABLE_MASK, RK_PWM_CTRL_DISABLED);

sys/dev/pwm/controller/rockchip/rk_pwm.c

303

RK_PWM_WRITE(sc, RK_PWM_CTRL, reg);

sys/dev/pwm/controller/rockchip/rk_pwm.c

309

SET(reg, RK_PWM_CTRL_ENABLE_MASK, RK_PWM_CTRL_ENABLED);

sys/dev/pwm/controller/rockchip/rk_pwm.c

310

SET(reg, RK_PWM_CTRL_MODE_MASK, RK_PWM_CTRL_MODE_CONTINUOUS);

sys/dev/pwm/controller/rockchip/rk_pwm.c

311

SET(reg, RK_PWM_CTRL_ALIGN_MASK, RK_PWM_CTRL_ALIGN_LEFT);

sys/dev/pwm/controller/rockchip/rk_pwm.c

312

SET(reg, RK_PWM_CTRL_CLOCKSRC_MASK, using_scaler);

sys/dev/pwm/controller/rockchip/rk_pwm.c

313

SET(reg, RK_PWM_CTRL_PRESCALE_MASK,

sys/dev/pwm/controller/rockchip/rk_pwm.c

315

SET(reg, RK_PWM_CTRL_SCALE_MASK,

sys/dev/pwm/controller/rockchip/rk_pwm.c

318

RK_PWM_WRITE(sc, RK_PWM_CTRL, reg);

sys/dev/pwm/controller/rockchip/rk_pwm.c

343

uint32_t reg;

sys/dev/pwm/controller/rockchip/rk_pwm.c

350

reg = RK_PWM_READ(sc, RK_PWM_CTRL);

sys/dev/pwm/controller/rockchip/rk_pwm.c

351

SET(reg, RK_PWM_CTRL_ENABLE_MASK, enable);

sys/dev/pwm/controller/rockchip/rk_pwm.c

353

RK_PWM_WRITE(sc, RK_PWM_CTRL, reg);

sys/dev/pwm/controller/rockchip/rk_pwm.c

51

#define SET(reg,mask,val) reg = ((reg & ~mask) | val)

sys/dev/qat/include/common/icp_qat_hal.h

199

#define AE_XFER_ADDR(handle, ae, reg) \

sys/dev/qat/include/common/icp_qat_hal.h

200

(AE_XFER(handle, ae) + (((reg)&0xff) << 2))

sys/dev/qat/include/common/icp_qat_hal.h

201

#define SET_AE_XFER(handle, ae, reg, val) \

sys/dev/qat/include/common/icp_qat_hal.h

202

ADF_CSR_WR(handle->hal_misc_addr_v, AE_XFER_ADDR(handle, ae, reg), val)

sys/dev/qat/qat_common/qat_hal.c

1842

unsigned short reg;

sys/dev/qat/qat_common/qat_hal.c

1852

handle, ae, reg_num, &reg, &ctx);

sys/dev/qat/qat_common/qat_hal.c

1855

reg = reg_num;

sys/dev/qat/qat_common/qat_hal.c

1860

stat = qat_hal_wr_rel_reg(handle, ae, ctx, type, reg, regdata);

sys/dev/qat/qat_common/qat_hal.c

1879

unsigned short reg;

sys/dev/qat/qat_common/qat_hal.c

1889

handle, ae, reg_num, &reg, &ctx);

sys/dev/qat/qat_common/qat_hal.c

1892

reg = reg_num;

sys/dev/qat/qat_common/qat_hal.c

1898

handle, ae, ctx, type, reg, regdata);

sys/dev/qat/qat_common/qat_hal.c

1917

unsigned short reg;

sys/dev/qat/qat_common/qat_hal.c

1927

handle, ae, reg_num, &reg, &ctx);

sys/dev/qat/qat_common/qat_hal.c

1930

reg = reg_num;

sys/dev/qat/qat_common/qat_hal.c

1936

handle, ae, ctx, type, reg, regdata);

sys/dev/qat/qat_common/qat_hal.c

877

unsigned short reg;

sys/dev/qat/qat_common/qat_hal.c

882

for (reg = 0; reg < ICP_QAT_UCLO_MAX_GPR_REG; reg++) {

sys/dev/qat/qat_common/qat_hal.c

884

handle, ae, 0, ICP_SR_RD_ABS, reg, 0);

sys/dev/qat/qat_common/qat_hal.c

886

handle, ae, 0, ICP_DR_RD_ABS, reg, 0);

sys/dev/qat/qat_common/qat_uclo.c

540

qat_uclo_calc_checksum(unsigned int reg, int ch)

sys/dev/qat/qat_common/qat_uclo.c

544

unsigned int inbyte = (unsigned int)((reg >> 0x18) ^ ch);

sys/dev/qat/qat_common/qat_uclo.c

546

reg ^= inbyte << 0x8;

sys/dev/qat/qat_common/qat_uclo.c

548

if (reg & topbit)

sys/dev/qat/qat_common/qat_uclo.c

549

reg = (reg << 1) ^ 0x1021;

sys/dev/qat/qat_common/qat_uclo.c

551

reg <<= 1;

sys/dev/qat/qat_common/qat_uclo.c

553

return reg & 0xFFFF;

sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c

2100

u32 reg = 0x0;

sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c

2107

reg = ADF_CSR_RD(addr + ADF_C4XXX_AE2FUNC_MAP_OFFSET,

sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c

2110

reg |= ADF_C4XXX_AE2FUNC_MAP_VALID;

sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c

2112

reg &= ~ADF_C4XXX_AE2FUNC_MAP_VALID;

sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c

2115

reg);

sys/dev/qat_c2xxx/qat_ae.c

1035

uint32_t times, reset, clock, reg, mask;

sys/dev/qat_c2xxx/qat_ae.c

1048

reg = qat_cap_global_read_4(sc, CAP_GLOBAL_CTL_RESET);

sys/dev/qat_c2xxx/qat_ae.c

1051

& reg);

sys/dev/qat_c2xxx/qat_ae.c

1183

u_int mask, reg;

sys/dev/qat_c2xxx/qat_ae.c

1190

for (reg = 0; reg < MAX_GPR_REG; reg++) {

sys/dev/qat_c2xxx/qat_ae.c

1192

reg, 0);

sys/dev/qat_c2xxx/qat_ae.c

1194

reg, 0);

sys/dev/qat_c2xxx/qat_ae.c

1781

qat_aefw_csum_calc(u_int reg, int ch)

sys/dev/qat_c2xxx/qat_ae.c

1785

u_int inbyte = (u_int)((reg >> 0x18) ^ ch);

sys/dev/qat_c2xxx/qat_ae.c

1787

reg ^= inbyte << (CRC_WIDTH - 0x8);

sys/dev/qat_c2xxx/qat_ae.c

1789

if (reg & topbit)

sys/dev/qat_c2xxx/qat_ae.c

1790

reg = (reg << 1) ^ CRC_POLY;

sys/dev/qat_c2xxx/qat_ae.c

1792

reg <<= 1;

sys/dev/qat_c2xxx/qat_ae.c

1795

return (reg & CRC_WIDTHMASK(CRC_WIDTH));

sys/dev/qat_c2xxx/qat_ae.c

303

qat_aereg_get_10bit_addr(enum aereg_type regtype, u_short reg)

sys/dev/qat_c2xxx/qat_ae.c

310

addr = (reg & 0x7f) | 0x80;

sys/dev/qat_c2xxx/qat_ae.c

314

addr = reg & 0x1f;

sys/dev/qat_c2xxx/qat_ae.c

319

addr = 0x180 | (reg & 0x1f);

sys/dev/qat_c2xxx/qat_ae.c

322

addr = 0x140 | ((reg & 0x3) << 1);

sys/dev/qat_c2xxx/qat_ae.c

327

addr = 0x1c0 | (reg & 0x1f);

sys/dev/qat_c2xxx/qat_ae.c

330

addr = 0x100 | ((reg & 0x3) << 1);

sys/dev/qat_c2xxx/qat_ae.c

333

addr = 0x241 | ((reg & 0x3) << 1);

sys/dev/qat_c2xxx/qat_ae.c

336

addr = 0x280 | (reg & 0x1f);

sys/dev/qat_c2xxx/qat_ae.c

345

addr = 0x300 | (reg & 0xff);

sys/dev/qat_c2xxx/qatvar.h

877

uint32_t reg;

sys/dev/qat_c2xxx/qatvar.h

879

reg = qat_misc_read_4(sc, offset);

sys/dev/qat_c2xxx/qatvar.h

880

reg |= value;

sys/dev/qat_c2xxx/qatvar.h

881

qat_misc_write_4(sc, offset, reg);

sys/dev/qat_c2xxx/qatvar.h

888

uint32_t reg;

sys/dev/qat_c2xxx/qatvar.h

890

reg = qat_misc_read_4(sc, offset);

sys/dev/qat_c2xxx/qatvar.h

891

reg &= mask;

sys/dev/qat_c2xxx/qatvar.h

892

qat_misc_write_4(sc, offset, reg);

sys/dev/qcom_clk/qcom_clk_apssdiv.c

100

cdiv = (reg >> sc->div_shift) & ((1U << sc->div_width) - 1);

sys/dev/qcom_clk/qcom_clk_apssdiv.c

116

uint32_t reg;

sys/dev/qcom_clk/qcom_clk_apssdiv.c

122

&reg);

sys/dev/qcom_clk/qcom_clk_apssdiv.c

124

return (!! (reg & (1U << sc->enable_shift)));

sys/dev/qcom_clk/qcom_clk_apssdiv.c

149

uint32_t reg;

sys/dev/qcom_clk/qcom_clk_apssdiv.c

162

&reg);

sys/dev/qcom_clk/qcom_clk_apssdiv.c

164

reg |= (1U << sc->enable_shift);

sys/dev/qcom_clk/qcom_clk_apssdiv.c

166

reg &= ~(1U << sc->enable_shift);

sys/dev/qcom_clk/qcom_clk_apssdiv.c

169

reg);

sys/dev/qcom_clk/qcom_clk_apssdiv.c

191

uint32_t reg;

sys/dev/qcom_clk/qcom_clk_apssdiv.c

226

CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->div_offset, &reg);

sys/dev/qcom_clk/qcom_clk_apssdiv.c

227

reg &= ~(((1U << sc->div_width) - 1) << sc->div_shift);

sys/dev/qcom_clk/qcom_clk_apssdiv.c

228

reg |= (f->pre_div << sc->div_shift);

sys/dev/qcom_clk/qcom_clk_apssdiv.c

229

CLKDEV_WRITE_4(clknode_get_device(sc->clknode), sc->div_offset, reg);

sys/dev/qcom_clk/qcom_clk_apssdiv.c

88

uint32_t reg, cdiv;

sys/dev/qcom_clk/qcom_clk_apssdiv.c

98

CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->div_offset, &reg);

sys/dev/qcom_clk/qcom_clk_branch2.c

101

&reg);

sys/dev/qcom_clk/qcom_clk_branch2.c

103

return (!! (reg & (1U << sc->hwcg_bit)));

sys/dev/qcom_clk/qcom_clk_branch2.c

109

uint32_t reg;

sys/dev/qcom_clk/qcom_clk_branch2.c

111

CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->halt_reg, &reg);

sys/dev/qcom_clk/qcom_clk_branch2.c

125

return !! ((reg & QCOM_CLK_BRANCH2_CLK_OFF) == 0);

sys/dev/qcom_clk/qcom_clk_branch2.c

127

return !! (reg & QCOM_CLK_BRANCH2_CLK_OFF);

sys/dev/qcom_clk/qcom_clk_branch2.c

184

uint32_t reg;

sys/dev/qcom_clk/qcom_clk_branch2.c

201

&reg);

sys/dev/qcom_clk/qcom_clk_branch2.c

203

reg |= (1U << sc->enable_shift);

sys/dev/qcom_clk/qcom_clk_branch2.c

205

reg &= ~(1U << sc->enable_shift);

sys/dev/qcom_clk/qcom_clk_branch2.c

208

reg);

sys/dev/qcom_clk/qcom_clk_branch2.c

70

uint32_t reg;

sys/dev/qcom_clk/qcom_clk_branch2.c

73

&reg);

sys/dev/qcom_clk/qcom_clk_branch2.c

77

sc->enable_offset, reg);

sys/dev/qcom_clk/qcom_clk_branch2.c

79

return (!! (reg & (1U << sc->enable_shift)));

sys/dev/qcom_clk/qcom_clk_branch2.c

95

uint32_t reg;

sys/dev/qcom_clk/qcom_clk_fepll.c

74

uint32_t reg, fdbkdiv, refclkdiv;

sys/dev/qcom_clk/qcom_clk_fepll.c

88

CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->offset, &reg);

sys/dev/qcom_clk/qcom_clk_fepll.c

91

fdbkdiv = (reg >> sc->fdbkdiv_shift) &

sys/dev/qcom_clk/qcom_clk_fepll.c

93

refclkdiv = (reg >> sc->refclkdiv_shift) &

sys/dev/qcom_clk/qcom_clk_rcg2.c

100

QCOM_CLK_RCG2_CMD_REGISTER(sc), &reg);

sys/dev/qcom_clk/qcom_clk_rcg2.c

101

if ((reg & QCOM_CLK_RCG2_CMD_UPDATE) == 0) {

sys/dev/qcom_clk/qcom_clk_rcg2.c

109

QCOM_CLK_RCG2_CMD_REGISTER(sc), &reg);

sys/dev/qcom_clk/qcom_clk_rcg2.c

111

__func__, reg);

sys/dev/qcom_clk/qcom_clk_rcg2.c

203

uint32_t mask, reg;

sys/dev/qcom_clk/qcom_clk_rcg2.c

210

QCOM_CLK_RCG2_M_OFFSET(sc), &reg);

sys/dev/qcom_clk/qcom_clk_rcg2.c

211

reg &= ~mask;

sys/dev/qcom_clk/qcom_clk_rcg2.c

212

reg |= (f->m & mask);

sys/dev/qcom_clk/qcom_clk_rcg2.c

214

QCOM_CLK_RCG2_M_OFFSET(sc), reg);

sys/dev/qcom_clk/qcom_clk_rcg2.c

217

QCOM_CLK_RCG2_N_OFFSET(sc), &reg);

sys/dev/qcom_clk/qcom_clk_rcg2.c

218

reg &= ~mask;

sys/dev/qcom_clk/qcom_clk_rcg2.c

219

reg |= ((~(f->n - f->m)) & mask);

sys/dev/qcom_clk/qcom_clk_rcg2.c

221

QCOM_CLK_RCG2_N_OFFSET(sc), reg);

sys/dev/qcom_clk/qcom_clk_rcg2.c

224

QCOM_CLK_RCG2_D_OFFSET(sc), &reg);

sys/dev/qcom_clk/qcom_clk_rcg2.c

225

reg &= ~mask;

sys/dev/qcom_clk/qcom_clk_rcg2.c

226

reg |= ((~f->n) & mask);

sys/dev/qcom_clk/qcom_clk_rcg2.c

228

QCOM_CLK_RCG2_D_OFFSET(sc), reg);

sys/dev/qcom_clk/qcom_clk_rcg2.c

241

QCOM_CLK_RCG2_CFG_OFFSET(sc), &reg);

sys/dev/qcom_clk/qcom_clk_rcg2.c

242

reg &= ~mask;

sys/dev/qcom_clk/qcom_clk_rcg2.c

245

reg = reg | ((f->pre_div) << QCOM_CLK_RCG2_CFG_SRC_DIV_SHIFT);

sys/dev/qcom_clk/qcom_clk_rcg2.c

248

reg = reg | (((parent_idx << QCOM_CLK_RCG2_CFG_SRC_SEL_SHIFT)

sys/dev/qcom_clk/qcom_clk_rcg2.c

253

reg |= QCOM_CLK_RCG2_CFG_MODE_DUAL_EDGE;

sys/dev/qcom_clk/qcom_clk_rcg2.c

256

QCOM_CLK_RCG2_CFG_OFFSET(sc), reg);

sys/dev/qcom_clk/qcom_clk_rcg2.c

263

uint32_t reg;

sys/dev/qcom_clk/qcom_clk_rcg2.c

277

QCOM_CLK_RCG2_CMD_REGISTER(sc), &reg);

sys/dev/qcom_clk/qcom_clk_rcg2.c

278

if (reg & QCOM_CLK_RCG2_CMD_ROOT_OFF)

sys/dev/qcom_clk/qcom_clk_rcg2.c

285

QCOM_CLK_RCG2_CFG_OFFSET(sc), &reg);

sys/dev/qcom_clk/qcom_clk_rcg2.c

288

idx = (reg & QCOM_CLK_RCG2_CFG_SRC_SEL_MASK)

sys/dev/qcom_clk/qcom_clk_rcg2.c

327

uint32_t reg;

sys/dev/qcom_clk/qcom_clk_rcg2.c

330

QCOM_CLK_RCG2_CFG_OFFSET(sc), &reg);

sys/dev/qcom_clk/qcom_clk_rcg2.c

331

reg = reg & ~QCOM_CLK_RCG2_CFG_SRC_SEL_MASK;

sys/dev/qcom_clk/qcom_clk_rcg2.c

332

reg = reg | (((index << QCOM_CLK_RCG2_CFG_SRC_SEL_SHIFT)

sys/dev/qcom_clk/qcom_clk_rcg2.c

336

reg);

sys/dev/qcom_clk/qcom_clk_rcg2.c

83

uint32_t reg, count;

sys/dev/qcom_clk/qcom_clk_rcg2.c

89

QCOM_CLK_RCG2_CMD_REGISTER(sc), &reg);

sys/dev/qcom_clk/qcom_clk_rcg2.c

90

reg |= QCOM_CLK_RCG2_CMD_UPDATE;

sys/dev/qcom_clk/qcom_clk_rcg2.c

92

QCOM_CLK_RCG2_CMD_REGISTER(sc), reg);

sys/dev/qcom_clk/qcom_clk_ro_div.c

69

uint32_t reg, idx, div = 1;

sys/dev/qcom_clk/qcom_clk_ro_div.c

80

CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->offset, &reg);

sys/dev/qcom_clk/qcom_clk_ro_div.c

83

idx = (reg >> sc->shift) & ((1U << sc->width) - 1);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

114

uint32_t reg;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

119

reg = EDMA_REG_READ(sc, EDMA_REG_IRQ_MODRT_TIMER_INIT);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

120

reg = reg >> EDMA_IRQ_MODRT_TX_TIMER_SHIFT;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

121

reg &= EDMA_IRQ_MODRT_TIMER_MASK;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

123

*usec = reg * 2;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

138

uint32_t reg;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

145

reg = EDMA_REG_READ(sc, EDMA_REG_IRQ_MODRT_TIMER_INIT);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

146

reg &= ~(EDMA_IRQ_MODRT_TIMER_MASK << EDMA_IRQ_MODRT_TX_TIMER_SHIFT);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

147

reg |= (usec & EDMA_IRQ_MODRT_TIMER_MASK)

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

149

EDMA_REG_WRITE(sc, EDMA_REG_IRQ_MODRT_TIMER_INIT, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

164

uint32_t reg;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

169

reg = EDMA_REG_READ(sc, EDMA_REG_IRQ_MODRT_TIMER_INIT);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

170

reg &= ~(EDMA_IRQ_MODRT_TIMER_MASK << EDMA_IRQ_MODRT_RX_TIMER_SHIFT);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

171

reg |= (usec & EDMA_IRQ_MODRT_TIMER_MASK)

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

173

EDMA_REG_WRITE(sc, EDMA_REG_IRQ_MODRT_TIMER_INIT, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

381

uint32_t reg;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

384

reg = EDMA_REG_READ(sc, EDMA_REG_RXQ_CTRL);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

385

reg &= ~EDMA_RXQ_CTRL_EN;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

386

EDMA_REG_WRITE(sc, EDMA_REG_RXQ_CTRL, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

390

reg = EDMA_REG_READ(sc, EDMA_REG_TXQ_CTRL);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

391

reg &= ~EDMA_TXQ_CTRL_TXQ_EN;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

392

EDMA_REG_WRITE(sc, EDMA_REG_TXQ_CTRL, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

445

uint32_t reg;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

454

reg = EDMA_REG_READ(sc, EDMA_REG_RFD_IDX_Q(queue));

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

456

"%s: q=%d reg was 0x%08x\n", __func__, queue, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

457

reg &= ~EDMA_RFD_PROD_IDX_BITS;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

458

reg |= idx;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

459

EDMA_REG_WRITE(sc, EDMA_REG_RFD_IDX_Q(queue), reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

461

"%s: q=%d reg now 0x%08x\n", __func__, queue, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

478

uint32_t reg;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

481

reg = EDMA_REG_READ(sc, EDMA_REG_RFD_IDX_Q(queue));

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

482

return (reg >> EDMA_RFD_CONS_IDX_SHIFT) & EDMA_RFD_CONS_IDX_MASK;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

511

uint32_t reg;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

516

reg = EDMA_REG_READ(sc, EDMA_REG_INTR_CTRL);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

517

reg &= ~(1 << EDMA_INTR_SW_IDX_W_TYP_SHIFT);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

518

reg |= sc->sc_state.intr_sw_idx_w << EDMA_INTR_SW_IDX_W_TYP_SHIFT;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

519

EDMA_REG_WRITE(sc, EDMA_REG_INTR_CTRL, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

526

reg = (EDMA_TX_IMT << EDMA_IRQ_MODRT_TX_TIMER_SHIFT);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

527

reg |= (EDMA_RX_IMT << EDMA_IRQ_MODRT_RX_TIMER_SHIFT);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

528

EDMA_REG_WRITE(sc, EDMA_REG_IRQ_MODRT_TIMER_INIT, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

541

uint32_t reg;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

545

reg = (EDMA_TPD_BURST << EDMA_TXQ_NUM_TPD_BURST_SHIFT);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

546

reg |= EDMA_TXQ_CTRL_TPD_BURST_EN;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

547

reg |= (EDMA_TXF_BURST << EDMA_TXQ_TXF_BURST_NUM_SHIFT);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

548

EDMA_REG_WRITE(sc, EDMA_REG_TXQ_CTRL, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

562

uint32_t reg;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

570

reg = (EDMA_RFD_BURST << EDMA_RXQ_RFD_BURST_NUM_SHIFT);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

572

reg |= (EDMA_RFD_THR << EDMA_RXQ_RFD_PF_THRESH_SHIFT);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

574

reg |= (EDMA_RFD_LTHR << EDMA_RXQ_RFD_LOW_THRESH_SHIFT);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

575

EDMA_REG_WRITE(sc, EDMA_REG_RX_DESC1, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

578

reg = EDMA_FIFO_THRESH_128_BYTE;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

580

reg |= EDMA_RXQ_CTRL_RMV_VLAN;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

581

EDMA_REG_WRITE(sc, EDMA_REG_RXQ_CTRL, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

595

uint32_t reg, i, idx;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

613

reg = EDMA_REG_READ(sc, EDMA_REG_TPD_IDX_Q(i));

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

614

idx = (reg >> EDMA_TPD_CONS_IDX_SHIFT) & 0xffff;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

620

reg &= ~(EDMA_TPD_PROD_IDX_MASK << EDMA_TPD_PROD_IDX_SHIFT);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

621

reg |= idx;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

622

EDMA_REG_WRITE(sc, EDMA_REG_TPD_IDX_Q(i), reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

645

reg = (len & EDMA_RX_BUF_SIZE_MASK)

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

648

reg |= (sc->sc_config.rx_ring_count & EDMA_RFD_RING_SIZE_MASK)

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

650

EDMA_REG_WRITE(sc, EDMA_REG_RX_DESC0, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

659

reg = EDMA_REG_READ(sc, EDMA_REG_TX_SRAM_PART);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

660

reg |= 1 << EDMA_LOAD_PTR_SHIFT;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

661

EDMA_REG_WRITE(sc, EDMA_REG_TX_SRAM_PART, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

673

uint32_t reg;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

678

reg = EDMA_REG_READ(sc, EDMA_REG_TXQ_CTRL);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

679

reg |= EDMA_TXQ_CTRL_TXQ_EN;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

680

EDMA_REG_WRITE(sc, EDMA_REG_TXQ_CTRL, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

693

uint32_t reg;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

696

reg = EDMA_REG_READ(sc, EDMA_REG_RXQ_CTRL);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

697

reg |= EDMA_RXQ_CTRL_EN;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

698

EDMA_REG_WRITE(sc, EDMA_REG_RXQ_CTRL, reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

711

uint32_t reg;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

714

reg = EDMA_REG_READ(sc, EDMA_REG_TPD_IDX_Q(queue_id));

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

715

*idx = (reg >> EDMA_TPD_CONS_IDX_SHIFT) & EDMA_TPD_CONS_IDX_MASK;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

727

uint32_t reg;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

730

reg = EDMA_REG_READ(sc, EDMA_REG_TPD_IDX_Q(queue_id));

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

731

reg &= ~EDMA_TPD_PROD_IDX_BITS;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

732

reg |= (idx & EDMA_TPD_PROD_IDX_MASK) << EDMA_TPD_PROD_IDX_SHIFT;

sys/dev/qcom_ess_edma/qcom_ess_edma_hw.c

733

EDMA_REG_WRITE(sc, EDMA_REG_TPD_IDX_Q(queue_id), reg);

sys/dev/qcom_ess_edma/qcom_ess_edma_var.h

46

#define EDMA_REG_WRITE(sc, reg, val) do { \

sys/dev/qcom_ess_edma/qcom_ess_edma_var.h

47

bus_write_4(sc->sc_mem_res, (reg), (val)); \

sys/dev/qcom_ess_edma/qcom_ess_edma_var.h

50

#define EDMA_REG_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg))

sys/dev/qcom_ess_edma/qcom_ess_edma_var.h

52

#define EDMA_REG_SET_BITS(sc, reg, bits) \

sys/dev/qcom_ess_edma/qcom_ess_edma_var.h

53

EDMA_REG_WRITE(sc, reg, EDMA_REG_READ(sc, (reg)) | (bits))

sys/dev/qcom_ess_edma/qcom_ess_edma_var.h

55

#define EDMA_REG_CLEAR_BITS(sc, reg, bits) \

sys/dev/qcom_ess_edma/qcom_ess_edma_var.h

56

EDMA_REG_WRITE(sc, reg, EDMA_REG_READ(sc, (reg)) & ~(bits))

sys/dev/qcom_gcc/qcom_gcc_clock.c

54

*val = bus_read_4(sc->reg, addr);

sys/dev/qcom_gcc/qcom_gcc_clock.c

64

bus_write_4(sc->reg, addr, val);

sys/dev/qcom_gcc/qcom_gcc_clock.c

73

uint32_t reg;

sys/dev/qcom_gcc/qcom_gcc_clock.c

76

reg = bus_read_4(sc->reg, addr);

sys/dev/qcom_gcc/qcom_gcc_clock.c

77

reg &= clear_mask;

sys/dev/qcom_gcc/qcom_gcc_clock.c

78

reg |= set_mask;

sys/dev/qcom_gcc/qcom_gcc_clock.c

79

bus_write_4(sc->reg, addr, reg);

sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c

135

uint32_t reg;

sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c

146

reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg);

sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c

148

reg |= (1U << gcc_ipq4019_reset_list[id].bit);

sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c

150

reg &= ~(1U << gcc_ipq4019_reset_list[id].bit);

sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c

151

bus_write_4(sc->reg, gcc_ipq4019_reset_list[id].reg, reg);

sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c

160

uint32_t reg;

sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c

170

reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg);

sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c

171

if (reg & ((1U << gcc_ipq4019_reset_list[id].bit)))

sys/dev/qcom_gcc/qcom_gcc_main.c

154

sc->reg = bus_alloc_resource_anywhere(dev, SYS_RES_MEMORY,

sys/dev/qcom_gcc/qcom_gcc_main.c

157

sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,

sys/dev/qcom_gcc/qcom_gcc_main.c

160

if (sc->reg == NULL) {

sys/dev/qcom_gcc/qcom_gcc_main.c

201

if (sc->reg != NULL) {

sys/dev/qcom_gcc/qcom_gcc_main.c

203

sc->reg_rid, sc->reg);

sys/dev/qcom_gcc/qcom_gcc_msm8916_clock.c

65

bus_write_4(sc->reg, GCC_QDSS_BCR, GCC_QDSS_BCR_BLK_ARES);

sys/dev/qcom_gcc/qcom_gcc_msm8916_clock.c

68

bus_write_4(sc->reg, GCC_QDSS_CFG_AHB_CBCR, AHB_CBCR_CLK_ENABLE);

sys/dev/qcom_gcc/qcom_gcc_msm8916_clock.c

71

bus_write_4(sc->reg, GCC_QDSS_DAP_CBCR, DAP_CBCR_CLK_ENABLE);

sys/dev/qcom_gcc/qcom_gcc_msm8916_clock.c

74

bus_write_4(sc->reg, GCC_QDSS_ETR_USB_CBCR, ETR_USB_CBCR_CLK_ENABLE);

sys/dev/qcom_gcc/qcom_gcc_msm8916_clock.c

77

bus_write_4(sc->reg, GCC_QDSS_BCR, 0);

sys/dev/qcom_gcc/qcom_gcc_var.h

38

uint32_t reg;

sys/dev/qcom_gcc/qcom_gcc_var.h

53

struct resource *reg;

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

161

uint32_t reg;

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

168

reg = MDIO_READ(sc, QCOM_IPQ4018_MDIO_REG_CMD);

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

169

if ((reg & QCOM_IPQ4018_MDIO_REG_CMD_ACCESS_BUSY) == 0)

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

180

int phy, int reg)

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

186

((phy & 0xff) << 8) | (reg & 0xff));

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

191

qcom_mdio_ipq4018_readreg(device_t dev, int phy, int reg)

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

198

__func__, phy, reg);

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

207

qcom_mdio_ipq4018_set_phy_reg_addr(sc, phy, reg);

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

233

qcom_mdio_ipq4018_writereg(device_t dev, int phy, int reg, int value)

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

239

__func__, phy, reg, value);

sys/dev/qcom_mdio/qcom_mdio_ipq4018.c

248

qcom_mdio_ipq4018_set_phy_reg_addr(sc, phy, reg);

sys/dev/qcom_mdio/qcom_mdio_ipq4018_var.h

39

#define MDIO_WRITE(sc, reg, val) do { \

sys/dev/qcom_mdio/qcom_mdio_ipq4018_var.h

40

bus_write_4(sc->sc_mem_res, (reg), (val)); \

sys/dev/qcom_mdio/qcom_mdio_ipq4018_var.h

43

#define MDIO_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg))

sys/dev/qcom_mdio/qcom_mdio_ipq4018_var.h

53

#define MDIO_SET_BITS(sc, reg, bits) \

sys/dev/qcom_mdio/qcom_mdio_ipq4018_var.h

54

GPIO_WRITE(sc, reg, MDIO_READ(sc, (reg)) | (bits))

sys/dev/qcom_mdio/qcom_mdio_ipq4018_var.h

56

#define MDIO_CLEAR_BITS(sc, reg, bits) \

sys/dev/qcom_mdio/qcom_mdio_ipq4018_var.h

57

GPIO_WRITE(sc, reg, MDIO_READ(sc, (reg)) & ~(bits))

sys/dev/qcom_qup/qcom_spi_hw.c

108

uint32_t reg;

sys/dev/qcom_qup/qcom_spi_hw.c

112

reg = QCOM_SPI_READ_4(sc, QUP_STATE);

sys/dev/qcom_qup/qcom_spi_hw.c

115

return !! (reg & QUP_STATE_VALID);

sys/dev/qcom_qup/qcom_spi_hw.c

284

uint32_t reg;

sys/dev/qcom_qup/qcom_spi_hw.c

292

reg = QCOM_SPI_READ_4(sc, SPI_IO_CONTROL);

sys/dev/qcom_qup/qcom_spi_hw.c

294

reg |= SPI_IO_C_FORCE_CS;

sys/dev/qcom_qup/qcom_spi_hw.c

296

reg &= ~SPI_IO_C_FORCE_CS;

sys/dev/qcom_qup/qcom_spi_hw.c

297

reg &= ~SPI_IO_C_CS_SELECT_MASK;

sys/dev/qcom_qup/qcom_spi_hw.c

298

reg |= SPI_IO_C_CS_SELECT(cs);

sys/dev/qcom_qup/qcom_spi_hw.c

299

QCOM_SPI_WRITE_4(sc, SPI_IO_CONTROL, reg);

sys/dev/qcom_qup/qcom_spi_hw.c

544

uint32_t reg;

sys/dev/qcom_qup/qcom_spi_hw.c

548

reg = QCOM_SPI_READ_4(sc, QUP_IO_M_MODES);

sys/dev/qcom_qup/qcom_spi_hw.c

550

reg &= ~((QUP_IO_M_INPUT_MODE_MASK << QUP_IO_M_INPUT_MODE_SHIFT)

sys/dev/qcom_qup/qcom_spi_hw.c

562

reg |= (QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);

sys/dev/qcom_qup/qcom_spi_hw.c

564

reg &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);

sys/dev/qcom_qup/qcom_spi_hw.c

567

reg |= ((sc->state.transfer_mode & QUP_IO_M_INPUT_MODE_MASK)

sys/dev/qcom_qup/qcom_spi_hw.c

569

reg |= ((sc->state.transfer_mode & QUP_IO_M_OUTPUT_MODE_MASK)

sys/dev/qcom_qup/qcom_spi_hw.c

573

"%s: QUP_IO_M_MODES=0x%08x\n", __func__, reg);

sys/dev/qcom_qup/qcom_spi_hw.c

575

QCOM_SPI_WRITE_4(sc, QUP_IO_M_MODES, reg);

sys/dev/qcom_qup/qcom_spi_hw.c

585

uint32_t reg;

sys/dev/qcom_qup/qcom_spi_hw.c

589

reg = QCOM_SPI_READ_4(sc, SPI_IO_CONTROL);

sys/dev/qcom_qup/qcom_spi_hw.c

592

reg |= SPI_IO_C_CLK_IDLE_HIGH;

sys/dev/qcom_qup/qcom_spi_hw.c

594

reg &= ~SPI_IO_C_CLK_IDLE_HIGH;

sys/dev/qcom_qup/qcom_spi_hw.c

597

"%s: SPI_IO_CONTROL=0x%08x\n", __func__, reg);

sys/dev/qcom_qup/qcom_spi_hw.c

599

QCOM_SPI_WRITE_4(sc, SPI_IO_CONTROL, reg);

sys/dev/qcom_qup/qcom_spi_hw.c

609

uint32_t reg;

sys/dev/qcom_qup/qcom_spi_hw.c

619

reg = QCOM_SPI_READ_4(sc, SPI_CONFIG);

sys/dev/qcom_qup/qcom_spi_hw.c

620

reg &= ~SPI_CONFIG_LOOPBACK;

sys/dev/qcom_qup/qcom_spi_hw.c

623

reg &= ~SPI_CONFIG_INPUT_FIRST;

sys/dev/qcom_qup/qcom_spi_hw.c

625

reg |= SPI_CONFIG_INPUT_FIRST;

sys/dev/qcom_qup/qcom_spi_hw.c

634

reg |= SPI_CONFIG_HS_MODE;

sys/dev/qcom_qup/qcom_spi_hw.c

636

reg &= ~SPI_CONFIG_HS_MODE;

sys/dev/qcom_qup/qcom_spi_hw.c

639

"%s: SPI_CONFIG=0x%08x\n", __func__, reg);

sys/dev/qcom_qup/qcom_spi_hw.c

641

QCOM_SPI_WRITE_4(sc, SPI_CONFIG, reg);

sys/dev/qcom_qup/qcom_spi_hw.c

650

uint32_t reg;

sys/dev/qcom_qup/qcom_spi_hw.c

654

reg = QCOM_SPI_READ_4(sc, QUP_CONFIG);

sys/dev/qcom_qup/qcom_spi_hw.c

655

reg &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);

sys/dev/qcom_qup/qcom_spi_hw.c

658

reg |= QUP_CONFIG_SPI_MODE;

sys/dev/qcom_qup/qcom_spi_hw.c

661

reg |= ((sc->state.transfer_word_size * 8) - 1) & QUP_CONFIG_N;

sys/dev/qcom_qup/qcom_spi_hw.c

67

uint32_t reg, val;

sys/dev/qcom_qup/qcom_spi_hw.c

670

reg |= QUP_CONFIG_NO_INPUT;

sys/dev/qcom_qup/qcom_spi_hw.c

672

reg |= QUP_CONFIG_NO_OUTPUT;

sys/dev/qcom_qup/qcom_spi_hw.c

676

"%s: QUP_CONFIG=0x%08x\n", __func__, reg);

sys/dev/qcom_qup/qcom_spi_hw.c

678

QCOM_SPI_WRITE_4(sc, QUP_CONFIG, reg);

sys/dev/qcom_qup/qcom_spi_hw.c

69

reg = QCOM_SPI_READ_4(sc, QUP_IO_M_MODES);

sys/dev/qcom_qup/qcom_spi_hw.c

72

"%s: QUP_IO_M_MODES=0x%08x\n", __func__, reg);

sys/dev/qcom_qup/qcom_spi_hw.c

75

val = (reg >> QUP_IO_M_INPUT_BLOCK_SIZE_SHIFT)

sys/dev/qcom_qup/qcom_spi_hw.c

776

uint32_t reg;

sys/dev/qcom_qup/qcom_spi_hw.c

797

reg = 0;

sys/dev/qcom_qup/qcom_spi_hw.c

799

if (qcom_spi_hw_write_from_tx_buf(sc, 24, &reg))

sys/dev/qcom_qup/qcom_spi_hw.c

802

if (qcom_spi_hw_write_from_tx_buf(sc, 24, &reg))

sys/dev/qcom_qup/qcom_spi_hw.c

804

if (qcom_spi_hw_write_from_tx_buf(sc, 16, &reg))

sys/dev/qcom_qup/qcom_spi_hw.c

807

if (qcom_spi_hw_write_from_tx_buf(sc, 24, &reg))

sys/dev/qcom_qup/qcom_spi_hw.c

809

if (qcom_spi_hw_write_from_tx_buf(sc, 16, &reg))

sys/dev/qcom_qup/qcom_spi_hw.c

811

if (qcom_spi_hw_write_from_tx_buf(sc, 8, &reg))

sys/dev/qcom_qup/qcom_spi_hw.c

813

if (qcom_spi_hw_write_from_tx_buf(sc, 0, &reg))

sys/dev/qcom_qup/qcom_spi_hw.c

822

QCOM_SPI_WRITE_4(sc, QUP_OUTPUT_FIFO, reg);

sys/dev/qcom_qup/qcom_spi_hw.c

83

val = (reg >> QUP_IO_M_OUTPUT_BLOCK_SIZE_SHIFT)

sys/dev/qcom_qup/qcom_spi_hw.c

872

uint32_t reg;

sys/dev/qcom_qup/qcom_spi_hw.c

883

reg = QCOM_SPI_READ_4(sc, QUP_OPERATIONAL);

sys/dev/qcom_qup/qcom_spi_hw.c

884

if ((reg & QUP_OP_IN_FIFO_NOT_EMPTY) == 0) {

sys/dev/qcom_qup/qcom_spi_hw.c

894

reg = QCOM_SPI_READ_4(sc, QUP_INPUT_FIFO);

sys/dev/qcom_qup/qcom_spi_hw.c

901

if (qcom_spi_hw_read_into_rx_buf(sc, reg & 0xff))

sys/dev/qcom_qup/qcom_spi_hw.c

904

if (qcom_spi_hw_read_into_rx_buf(sc, (reg >> 8) & 0xff))

sys/dev/qcom_qup/qcom_spi_hw.c

906

if (qcom_spi_hw_read_into_rx_buf(sc, reg & 0xff))

sys/dev/qcom_qup/qcom_spi_hw.c

909

if (qcom_spi_hw_read_into_rx_buf(sc, (reg >> 24) & 0xff))

sys/dev/qcom_qup/qcom_spi_hw.c

91

val = (reg >> QUP_IO_M_INPUT_FIFO_SIZE_SHIFT)

sys/dev/qcom_qup/qcom_spi_hw.c

911

if (qcom_spi_hw_read_into_rx_buf(sc, (reg >> 16) & 0xff))

sys/dev/qcom_qup/qcom_spi_hw.c

913

if (qcom_spi_hw_read_into_rx_buf(sc, (reg >> 8) & 0xff))

sys/dev/qcom_qup/qcom_spi_hw.c

915

if (qcom_spi_hw_read_into_rx_buf(sc, reg & 0xff))

sys/dev/qcom_qup/qcom_spi_hw.c

930

reg = QCOM_SPI_READ_4(sc, QUP_OPERATIONAL);

sys/dev/qcom_qup/qcom_spi_hw.c

931

if (reg & QUP_OP_MAX_INPUT_DONE_FLAG) {

sys/dev/qcom_qup/qcom_spi_hw.c

97

val = (reg >> QUP_IO_M_OUTPUT_FIFO_SIZE_SHIFT)

sys/dev/qcom_qup/qcom_spi_var.h

116

#define QCOM_SPI_READ_4(sc, reg) bus_read_4((sc)->sc_mem_res, (reg))

sys/dev/qcom_qup/qcom_spi_var.h

117

#define QCOM_SPI_WRITE_4(sc, reg, val) bus_write_4((sc)->sc_mem_res, \

sys/dev/qcom_qup/qcom_spi_var.h

118

(reg), (val))

sys/dev/qcom_rnd/qcom_rnd.c

113

uint32_t reg;

sys/dev/qcom_rnd/qcom_rnd.c

129

sc->reg = bus_alloc_resource_anywhere(dev, SYS_RES_MEMORY,

sys/dev/qcom_rnd/qcom_rnd.c

131

if (sc->reg == NULL) {

sys/dev/qcom_rnd/qcom_rnd.c

141

bus_barrier(sc->reg, 0, 0x120, BUS_SPACE_BARRIER_READ);

sys/dev/qcom_rnd/qcom_rnd.c

142

reg = bus_read_4(sc->reg, QCOM_RND_PRNG_CONFIG);

sys/dev/qcom_rnd/qcom_rnd.c

143

if (reg & QCOM_RND_PRNG_CONFIG_HW_ENABLE) {

sys/dev/qcom_rnd/qcom_rnd.c

149

reg = bus_read_4(sc->reg, QCOM_RND_PRNG_LFSR_CFG);

sys/dev/qcom_rnd/qcom_rnd.c

150

reg &= QCOM_RND_PRNG_LFSR_CFG_MASK;

sys/dev/qcom_rnd/qcom_rnd.c

151

reg |= QCOM_RND_PRNG_LFSR_CFG_CLOCKS;

sys/dev/qcom_rnd/qcom_rnd.c

152

bus_write_4(sc->reg, QCOM_RND_PRNG_LFSR_CFG, reg);

sys/dev/qcom_rnd/qcom_rnd.c

153

bus_barrier(sc->reg, 0, 0x120, BUS_SPACE_BARRIER_WRITE);

sys/dev/qcom_rnd/qcom_rnd.c

155

reg = bus_read_4(sc->reg, QCOM_RND_PRNG_CONFIG);

sys/dev/qcom_rnd/qcom_rnd.c

156

reg |= QCOM_RND_PRNG_CONFIG_HW_ENABLE;

sys/dev/qcom_rnd/qcom_rnd.c

157

bus_write_4(sc->reg, QCOM_RND_PRNG_CONFIG, reg);

sys/dev/qcom_rnd/qcom_rnd.c

158

bus_barrier(sc->reg, 0, 0x120, BUS_SPACE_BARRIER_WRITE);

sys/dev/qcom_rnd/qcom_rnd.c

177

if (sc->reg != NULL) {

sys/dev/qcom_rnd/qcom_rnd.c

178

bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->reg_rid, sc->reg);

sys/dev/qcom_rnd/qcom_rnd.c

196

uint32_t reg;

sys/dev/qcom_rnd/qcom_rnd.c

199

bus_barrier(sc->reg, 0, 0x120, BUS_SPACE_BARRIER_READ);

sys/dev/qcom_rnd/qcom_rnd.c

200

reg = bus_read_4(sc->reg, QCOM_RND_PRNG_STATUS);

sys/dev/qcom_rnd/qcom_rnd.c

201

if ((reg & QCOM_RND_PRNG_STATUS_DATA_AVAIL) == 0)

sys/dev/qcom_rnd/qcom_rnd.c

203

reg = bus_read_4(sc->reg, QCOM_RND_PRNG_DATA_OUT);

sys/dev/qcom_rnd/qcom_rnd.c

204

memcpy(((char *) buf) + rz, &reg, sizeof(uint32_t));

sys/dev/qcom_rnd/qcom_rnd.c

54

struct resource *reg;

sys/dev/qcom_tcsr/qcom_tcsr.c

153

uint32_t reg;

sys/dev/qcom_tcsr/qcom_tcsr.c

159

reg = QCOM_TCSR_READ_4(sc, QCOM_TCSR_ESS_INTERFACE_SEL_OFFSET);

sys/dev/qcom_tcsr/qcom_tcsr.c

160

reg &= ~QCOM_TCSR_ESS_INTERFACE_SEL_MASK;

sys/dev/qcom_tcsr/qcom_tcsr.c

161

reg |= (val & QCOM_TCSR_ESS_INTERFACE_SEL_MASK);

sys/dev/qcom_tcsr/qcom_tcsr.c

162

QCOM_TCSR_WRITE_4(sc, QCOM_TCSR_ESS_INTERFACE_SEL_OFFSET, reg);

sys/dev/qcom_tcsr/qcom_tcsr_var.h

31

#define QCOM_TCSR_READ_4(sc, reg) bus_read_4((sc)->sc_mem_res, (reg))

sys/dev/qcom_tcsr/qcom_tcsr_var.h

32

#define QCOM_TCSR_WRITE_4(sc, reg, val) bus_write_4((sc)->sc_mem_res, \

sys/dev/qcom_tcsr/qcom_tcsr_var.h

33

(reg), (val))

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

107

reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

109

reg = reg >> QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_SHIFT;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

110

reg &= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

111

*function = reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

124

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

131

reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

133

reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OE_ENABLE;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

136

reg);

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

149

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

156

reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

158

reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OE_ENABLE;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

160

QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

173

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

180

reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

182

*is_output = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OE_ENABLE);

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

195

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

202

reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

205

reg |= QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

207

reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

209

QCOM_TLMM_IPQ4018_REG_PIN_IO), reg);

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

221

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

228

reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

231

*val = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_IO_INPUT_STATUS);

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

244

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

251

reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

254

*val = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_IO_INPUT_STATUS);

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

266

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

273

reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

275

if ((reg & QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN) == 0)

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

276

reg |= QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

278

reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

280

QCOM_TLMM_IPQ4018_REG_PIN_IO), reg);

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

295

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

302

reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

305

reg &= ~(QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_MASK

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

310

reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_DISABLE

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

314

reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLDOWN

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

318

reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLUP

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

322

reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_BUSHOLD

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

328

QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

341

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

348

reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

351

reg >>= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

352

reg &= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_MASK;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

354

switch (reg) {

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

379

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

391

reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

394

reg &= ~(QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_SHIFT

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

396

reg |= (drv & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_MASK)

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

400

QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

412

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

419

reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

422

*drv = (reg >> QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_SHIFT)

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

438

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

445

reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

448

reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_VM_ENABLE;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

450

reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_VM_ENABLE;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

453

QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

465

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

472

reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

475

*enable = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_VM_ENABLE);

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

487

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

494

reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

497

reg &= ~QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OD_ENABLE;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

499

reg |= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OD_ENABLE;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

502

QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

514

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

521

reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

524

*enable = !! (reg & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OD_ENABLE);

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

71

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

78

reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin,

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

80

reg &= ~(QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

82

reg |= (function & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK)

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

85

QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg);

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_hw.c

99

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_reg.h

79

#define QCOM_TLMM_IPQ4018_REG_PIN(p, reg) \

sys/dev/qcom_tlmm/qcom_tlmm_ipq4018_reg.h

81

QCOM_TLMM_IPQ4018_REG_CONFIG_PIN_BASE + (reg))

sys/dev/qcom_tlmm/qcom_tlmm_var.h

131

.reg = r, \

sys/dev/qcom_tlmm/qcom_tlmm_var.h

139

uint32_t reg;

sys/dev/qcom_tlmm/qcom_tlmm_var.h

40

#define GPIO_WRITE(sc, reg, val) do { \

sys/dev/qcom_tlmm/qcom_tlmm_var.h

41

bus_write_4(sc->gpio_mem_res, (reg), (val)); \

sys/dev/qcom_tlmm/qcom_tlmm_var.h

44

#define GPIO_READ(sc, reg) bus_read_4(sc->gpio_mem_res, (reg))

sys/dev/qcom_tlmm/qcom_tlmm_var.h

46

#define GPIO_SET_BITS(sc, reg, bits) \

sys/dev/qcom_tlmm/qcom_tlmm_var.h

47

GPIO_WRITE(sc, reg, GPIO_READ(sc, (reg)) | (bits))

sys/dev/qcom_tlmm/qcom_tlmm_var.h

49

#define GPIO_CLEAR_BITS(sc, reg, bits) \

sys/dev/qcom_tlmm/qcom_tlmm_var.h

50

GPIO_WRITE(sc, reg, GPIO_READ(sc, (reg)) & ~(bits))

sys/dev/qlnx/qlnxe/bcm_osal.h

337

#define OSAL_PCI_READ_CONFIG_BYTE(dev, reg, value) \

sys/dev/qlnx/qlnxe/bcm_osal.h

338

qlnx_pci_read_config_byte(dev, reg, value);

sys/dev/qlnx/qlnxe/bcm_osal.h

339

#define OSAL_PCI_READ_CONFIG_WORD(dev, reg, value) \

sys/dev/qlnx/qlnxe/bcm_osal.h

340

qlnx_pci_read_config_word(dev, reg, value);

sys/dev/qlnx/qlnxe/bcm_osal.h

341

#define OSAL_PCI_READ_CONFIG_DWORD(dev, reg, value) \

sys/dev/qlnx/qlnxe/bcm_osal.h

342

qlnx_pci_read_config_dword(dev, reg, value);

sys/dev/qlnx/qlnxe/bcm_osal.h

344

#define OSAL_PCI_WRITE_CONFIG_BYTE(dev, reg, value) \

sys/dev/qlnx/qlnxe/bcm_osal.h

345

qlnx_pci_write_config_byte(dev, reg, value);

sys/dev/qlnx/qlnxe/bcm_osal.h

346

#define OSAL_PCI_WRITE_CONFIG_WORD(dev, reg, value) \

sys/dev/qlnx/qlnxe/bcm_osal.h

347

qlnx_pci_write_config_word(dev, reg, value);

sys/dev/qlnx/qlnxe/bcm_osal.h

348

#define OSAL_PCI_WRITE_CONFIG_DWORD(dev, reg, value) \

sys/dev/qlnx/qlnxe/bcm_osal.h

349

qlnx_pci_write_config_dword(dev, reg, value);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1298

clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1299

clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1300

clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1302

clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1303

clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1304

clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1306

clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1307

clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1308

clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1310

clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1311

clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1312

clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1314

clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1315

clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1316

clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1318

clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1319

clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1320

clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);

sys/dev/qlnx/qlnxe/ecore_cxt.c

153

u32 reg;

sys/dev/qlnx/qlnxe/ecore_cxt.c

1688

ilt_clients[i].first.reg,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1691

ilt_clients[i].last.reg,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1694

ilt_clients[i].p_size.reg,

sys/dev/qlnx/qlnxe/ecore_cxt.c

74

#define ILT_CFG_REG(cli, reg) PSWRQ2_REG_##cli##_##reg##_RT_OFFSET

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

3119

const struct dbg_dump_reg *reg = (const struct dbg_dump_reg *)&input_regs_arr.ptr[input_offset];

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

3122

GET_FIELD(reg->data, DBG_DUMP_REG_ADDRESS),

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

3123

GET_FIELD(reg->data, DBG_DUMP_REG_LENGTH),

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

3124

GET_FIELD(reg->data, DBG_DUMP_REG_WIDE_BUS));

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4215

const struct dbg_idle_chk_cond_reg *reg = &cond_regs[reg_id];

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4222

offset += IDLE_CHK_RESULT_REG_HDR_DWORDS + reg->entry_size;

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4228

reg_hdr->start_entry = reg->start_entry;

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4229

reg_hdr->size = reg->entry_size;

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4230

SET_FIELD(reg_hdr->data, DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM, reg->num_entries > 1 || reg->start_entry > 0 ? 1 : 0);

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4240

const struct dbg_idle_chk_info_reg *reg = &info_regs[reg_id];

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4245

offset += IDLE_CHK_RESULT_REG_HDR_DWORDS + reg->size;

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4249

block_id = GET_FIELD(reg->data, DBG_IDLE_CHK_INFO_REG_BLOCK_ID);

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4264

eval_mode = GET_FIELD(reg->mode.data, DBG_MODE_HDR_EVAL_MODE) > 0;

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4266

modes_buf_offset = GET_FIELD(reg->mode.data, DBG_MODE_HDR_MODES_BUF_OFFSET);

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4273

addr = GET_FIELD(reg->data, DBG_IDLE_CHK_INFO_REG_ADDRESS);

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4274

wide_bus = GET_FIELD(reg->data, DBG_IDLE_CHK_INFO_REG_WIDE_BUS);

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4280

reg_hdr->size = reg->size;

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4284

offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, dump_buf + offset, dump, addr, reg->size, wide_bus);

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4357

const struct dbg_idle_chk_cond_reg *reg = &cond_regs[reg_id];

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4364

addr = GET_FIELD(reg->data, DBG_IDLE_CHK_COND_REG_ADDRESS);

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4365

wide_bus = GET_FIELD(reg->data, DBG_IDLE_CHK_COND_REG_WIDE_BUS);

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4366

if (reg->num_entries > 1 || reg->start_entry > 0) {

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4367

padded_entry_size = reg->entry_size > 1 ? OSAL_ROUNDUP_POW_OF_TWO(reg->entry_size) : 1;

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4368

addr += (reg->start_entry + entry_id) * padded_entry_size;

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4372

if (next_reg_offset + reg->entry_size >= IDLE_CHK_MAX_ENTRIES_SIZE) {

sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c

4377

next_reg_offset += ecore_grc_dump_addr_range(p_hwfn, p_ptt, cond_reg_values + next_reg_offset, dump, addr, reg->entry_size, wide_bus);

sys/dev/qlnx/qlnxe/ecore_hsi_common.h

2588

__le32 reg;

sys/dev/qlnx/qlnxe/ecore_hsi_common.h

2610

__le32 reg;

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

173

#define QM_INIT_TX_PQ_MAP(p_hwfn, map, chip, pq_id, rl_valid, vp_pq_id, rl_id, ext_voq, wrr) OSAL_MEMSET(&map, 0, sizeof(map)); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_PQ_VALID, 1); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_RL_VALID, rl_valid); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_VP_PQ_ID, vp_pq_id); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_RL_ID, rl_id); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_VOQ, ext_voq); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_WRR_WEIGHT_GROUP, wrr); STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + pq_id, *((u32 *)&map))

sys/dev/qlnx/qlnxe/ecore_vf.c

522

u32 reg;

sys/dev/qlnx/qlnxe/ecore_vf.c

531

reg = PXP_VF_BAR0_ME_OPAQUE_ADDRESS;

sys/dev/qlnx/qlnxe/ecore_vf.c

532

p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, reg);

sys/dev/qlnx/qlnxe/ecore_vf.c

534

reg = PXP_VF_BAR0_ME_CONCRETE_ADDRESS;

sys/dev/qlnx/qlnxe/ecore_vf.c

535

p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, reg);

sys/dev/qlnx/qlnxe/qlnx_ioctl.c

465

pci_cfg_rd_wr->reg,

sys/dev/qlnx/qlnxe/qlnx_ioctl.c

470

pci_write_config(ha->pci_dev, pci_cfg_rd_wr->reg,

sys/dev/qlnx/qlnxe/qlnx_ioctl.h

167

uint32_t reg;

sys/dev/qlnx/qlnxe/qlnx_os.c

5113

int reg;

sys/dev/qlnx/qlnxe/qlnx_os.c

5118

if (pci_find_cap(ha->pci_dev, PCIY_EXPRESS, &reg) == 0)

sys/dev/qlnx/qlnxe/qlnx_os.c

5119

return reg;

sys/dev/qlnx/qlnxe/qlnx_os.c

5129

int reg;

sys/dev/qlnx/qlnxe/qlnx_os.c

5134

if (pci_find_extcap(ha->pci_dev, ext_cap, &reg) == 0)

sys/dev/qlnx/qlnxe/qlnx_os.c

5135

return reg;

sys/dev/qlnx/qlnxe/qlnx_os.c

7274

uint32_t reg;

sys/dev/qlnx/qlnxe/qlnx_os.c

7298

reg = XSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7300

s_stats->xstorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7302

reg = XSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7304

s_stats->xstorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7306

reg = XSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7308

s_stats->xstorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7310

reg = XSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7312

s_stats->xstorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7315

reg = YSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7317

s_stats->ystorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7319

reg = YSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7321

s_stats->ystorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7323

reg = YSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7325

s_stats->ystorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7327

reg = YSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7329

s_stats->ystorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7332

reg = PSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7334

s_stats->pstorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7336

reg = PSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7338

s_stats->pstorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7340

reg = PSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7342

s_stats->pstorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7344

reg = PSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7346

s_stats->pstorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7349

reg = TSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7351

s_stats->tstorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7353

reg = TSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7355

s_stats->tstorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7357

reg = TSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7359

s_stats->tstorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7361

reg = TSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7363

s_stats->tstorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7366

reg = MSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7368

s_stats->mstorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7370

reg = MSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7372

s_stats->mstorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7374

reg = MSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7376

s_stats->mstorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7378

reg = MSEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7380

s_stats->mstorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7383

reg = USEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7385

s_stats->ustorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7387

reg = USEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7389

s_stats->ustorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7391

reg = USEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7393

s_stats->ustorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlnx/qlnxe/qlnx_os.c

7395

reg = USEM_REG_FAST_MEMORY +

sys/dev/qlnx/qlnxe/qlnx_os.c

7397

s_stats->ustorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);

sys/dev/qlxgb/qla_ioctl.c

101

rv->val = READ_OFFSET32(ha, rv->reg);

sys/dev/qlxgb/qla_ioctl.c

103

WRITE_OFFSET32(ha, rv->reg, rv->val);

sys/dev/qlxgb/qla_ioctl.c

106

if ((rval = qla_rdwr_indreg32(ha, rv->reg, &rv->val,

sys/dev/qlxgb/qla_ioctl.h

42

uint32_t reg;

sys/dev/qlxgb/qla_reg.h

228

#define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)

sys/dev/qlxgb/qla_reg.h

231

#define WRITE_REG32(ha, reg, val) \

sys/dev/qlxgb/qla_reg.h

233

bus_write_4((ha->pci_reg), reg, val);\

sys/dev/qlxgb/qla_reg.h

234

bus_read_4((ha->pci_reg), reg);\

sys/dev/qlxgb/qla_reg.h

237

#define WRITE_REG32_MB(ha, reg, val) \

sys/dev/qlxgb/qla_reg.h

240

bus_write_4((ha->pci_reg), reg, val);\

sys/dev/qlxgbe/ql_hw.h

203

#define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)

sys/dev/qlxgbe/ql_hw.h

205

#define WRITE_REG32(ha, reg, val) \

sys/dev/qlxgbe/ql_hw.h

207

bus_write_4((ha->pci_reg), reg, val);\

sys/dev/qlxgbe/ql_hw.h

208

bus_read_4((ha->pci_reg), reg);\

sys/dev/qlxgbe/ql_ioctl.c

116

u.rv->val = READ_REG32(ha, u.rv->reg);

sys/dev/qlxgbe/ql_ioctl.c

118

WRITE_REG32(ha, u.rv->reg, u.rv->val);

sys/dev/qlxgbe/ql_ioctl.c

121

if ((rval = ql_rdwr_indreg32(ha, u.rv->reg, &u.rv->val,

sys/dev/qlxgbe/ql_ioctl.h

42

uint32_t reg;

sys/dev/qlxge/qls_dump.c

1575

uint32_t reg, reg_val;

sys/dev/qlxge/qls_dump.c

1907

reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (i << Q81_FUNCTION_SHIFT) |

sys/dev/qlxge/qls_dump.c

1910

ret = qls_mpi_risc_rd_reg(ha, reg, &reg_val);

sys/dev/qlxge/qls_dump.c

374

qls_wait_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit, uint32_t err_bit)

sys/dev/qlxge/qls_dump.c

380

data = READ_REG32(ha, reg);

sys/dev/qlxge/qls_dump.c

394

qls_rd_mpi_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)

sys/dev/qlxge/qls_dump.c

404

WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg | Q81_CTL_PROC_ADDR_READ);

sys/dev/qlxge/qls_dump.c

419

qls_wr_mpi_reg(qla_host_t *ha, uint32_t reg, uint32_t data)

sys/dev/qlxge/qls_dump.c

430

WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg);

sys/dev/qlxge/qls_dump.c

479

qls_rd_ofunc_reg(qla_host_t *ha, uint32_t reg)

sys/dev/qlxge/qls_dump.c

490

reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (ofunc << Q81_FUNCTION_SHIFT) | reg;

sys/dev/qlxge/qls_dump.c

492

ret = qls_rd_mpi_reg(ha, reg, &data);

sys/dev/qlxge/qls_dump.c

501

qls_wr_ofunc_reg(qla_host_t *ha, uint32_t reg, uint32_t value)

sys/dev/qlxge/qls_dump.c

510

reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (ofunc << Q81_FUNCTION_SHIFT) | reg;

sys/dev/qlxge/qls_dump.c

512

qls_wr_mpi_reg(ha, reg, value);

sys/dev/qlxge/qls_dump.c

518

qls_wait_ofunc_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit,

sys/dev/qlxge/qls_dump.c

525

data = qls_rd_ofunc_reg(ha, reg);

sys/dev/qlxge/qls_dump.c

542

qls_rd_ofunc_serdes_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)

sys/dev/qlxge/qls_dump.c

554

(reg | Q81_XG_SERDES_ADDR_READ));

sys/dev/qlxge/qls_dump.c

574

qls_rd_ofunc_xgmac_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)

sys/dev/qlxge/qls_dump.c

585

(reg | Q81_XGMAC_ADDR_R));

sys/dev/qlxge/qls_dump.c

599

qls_rd_serdes_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)

sys/dev/qlxge/qls_dump.c

610

(reg | Q81_XG_SERDES_ADDR_READ));

sys/dev/qlxge/qls_dump.c

856

qls_rd_xgmac_reg(qla_host_t *ha, uint32_t reg, uint32_t*data)

sys/dev/qlxge/qls_dump.c

865

WRITE_REG32(ha, Q81_CTL_XGMAC_ADDR, (reg | Q81_XGMAC_ADDR_R));

sys/dev/qlxge/qls_glbl.h

86

extern int qls_mbx_rd_reg(qla_host_t *ha, uint32_t reg, uint32_t *data);

sys/dev/qlxge/qls_glbl.h

87

extern int qls_mbx_wr_reg(qla_host_t *ha, uint32_t reg, uint32_t data);

sys/dev/qlxge/qls_glbl.h

88

extern int qls_mpi_risc_rd_reg(qla_host_t *ha, uint32_t reg, uint32_t *data);

sys/dev/qlxge/qls_glbl.h

89

extern int qls_mpi_risc_wr_reg(qla_host_t *ha, uint32_t reg, uint32_t data);

sys/dev/qlxge/qls_hw.c

1933

qls_proc_addr_rd_reg(qla_host_t *ha, uint32_t addr_module, uint32_t reg,

sys/dev/qlxge/qls_hw.c

1944

value = addr_module | reg | Q81_CTL_PROC_ADDR_READ;

sys/dev/qlxge/qls_hw.c

1960

qls_proc_addr_wr_reg(qla_host_t *ha, uint32_t addr_module, uint32_t reg,

sys/dev/qlxge/qls_hw.c

1973

value = addr_module | reg;

sys/dev/qlxge/qls_hw.c

2081

qls_mpi_risc_rd_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)

sys/dev/qlxge/qls_hw.c

2086

reg, data);

sys/dev/qlxge/qls_hw.c

2091

qls_mpi_risc_wr_reg(qla_host_t *ha, uint32_t reg, uint32_t data)

sys/dev/qlxge/qls_hw.c

2096

reg, data);

sys/dev/qlxge/qls_hw.c

2101

qls_mbx_rd_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)

sys/dev/qlxge/qls_hw.c

2106

reg += Q81_FUNC0_MBX_OUT_REG0;

sys/dev/qlxge/qls_hw.c

2108

reg += Q81_FUNC1_MBX_OUT_REG0;

sys/dev/qlxge/qls_hw.c

2110

ret = qls_mpi_risc_rd_reg(ha, reg, data);

sys/dev/qlxge/qls_hw.c

2116

qls_mbx_wr_reg(qla_host_t *ha, uint32_t reg, uint32_t data)

sys/dev/qlxge/qls_hw.c

2121

reg += Q81_FUNC0_MBX_IN_REG0;

sys/dev/qlxge/qls_hw.c

2123

reg += Q81_FUNC1_MBX_IN_REG0;

sys/dev/qlxge/qls_hw.c

2125

ret = qls_mpi_risc_wr_reg(ha, reg, data);

sys/dev/qlxge/qls_hw.c

77

uint32_t reg, uint32_t *data);

sys/dev/qlxge/qls_hw.c

79

uint32_t reg, uint32_t data);

sys/dev/qlxge/qls_hw.h

898

#define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)

sys/dev/qlxge/qls_hw.h

899

#define READ_REG64(ha, reg) bus_read_8((ha->pci_reg), reg)

sys/dev/qlxge/qls_hw.h

901

#define WRITE_REG32_ONLY(ha, reg, val) bus_write_4((ha->pci_reg), reg, val)

sys/dev/qlxge/qls_hw.h

903

#define WRITE_REG32(ha, reg, val) bus_write_4((ha->pci_reg), reg, val)

sys/dev/ral/rt2560.c

167

uint32_t reg;

sys/dev/ral/rt2560.c

174

uint8_t reg;

sys/dev/ral/rt2560.c

1949

rt2560_bbp_write(struct rt2560_softc *sc, uint8_t reg, uint8_t val)

sys/dev/ral/rt2560.c

1964

tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val;

sys/dev/ral/rt2560.c

1967

DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val);

sys/dev/ral/rt2560.c

1971

rt2560_bbp_read(struct rt2560_softc *sc, uint8_t reg)

sys/dev/ral/rt2560.c

1986

val = RT2560_BBP_BUSY | reg << 8;

sys/dev/ral/rt2560.c

2001

rt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val)

sys/dev/ral/rt2560.c

2017

(reg & 0x3);

sys/dev/ral/rt2560.c

2021

sc->rf_regs[reg] = val;

sys/dev/ral/rt2560.c

2023

DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff);

sys/dev/ral/rt2560.c

2429

sc->bbp_prom[i].reg = val >> 8;

sys/dev/ral/rt2560.c

2492

rt2560_bbp_write(sc, rt2560_def_bbp[i].reg,

sys/dev/ral/rt2560.c

2498

if (sc->bbp_prom[i].reg == 0 && sc->bbp_prom[i].val == 0)

sys/dev/ral/rt2560.c

2500

rt2560_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);

sys/dev/ral/rt2560.c

2587

RAL_WRITE(sc, rt2560_def_mac[i].reg, rt2560_def_mac[i].val);

sys/dev/ral/rt2560reg.h

307

#define RAL_READ(sc, reg) \

sys/dev/ral/rt2560reg.h

308

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/ral/rt2560reg.h

310

#define RAL_WRITE(sc, reg, val) \

sys/dev/ral/rt2560reg.h

311

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/ral/rt2560var.h

138

uint8_t reg;

sys/dev/ral/rt2661.c

1685

rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val)

sys/dev/ral/rt2661.c

1700

tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;

sys/dev/ral/rt2661.c

1703

DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val);

sys/dev/ral/rt2661.c

1707

rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg)

sys/dev/ral/rt2661.c

1722

val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8;

sys/dev/ral/rt2661.c

173

uint32_t reg;

sys/dev/ral/rt2661.c

1737

rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)

sys/dev/ral/rt2661.c

1753

(reg & 3);

sys/dev/ral/rt2661.c

1757

sc->rf_regs[reg] = val;

sys/dev/ral/rt2661.c

1759

DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff);

sys/dev/ral/rt2661.c

180

uint8_t reg;

sys/dev/ral/rt2661.c

2178

sc->bbp_prom[i].reg = val >> 8;

sys/dev/ral/rt2661.c

2180

DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg,

sys/dev/ral/rt2661.c

2205

rt2661_bbp_write(sc, rt2661_def_bbp[i].reg,

sys/dev/ral/rt2661.c

2211

if (sc->bbp_prom[i].reg == 0)

sys/dev/ral/rt2661.c

2213

rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);

sys/dev/ral/rt2661.c

2283

RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);

sys/dev/ral/rt2661reg.h

317

#define RAL_READ(sc, reg) \

sys/dev/ral/rt2661reg.h

318

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/ral/rt2661reg.h

324

#define RAL_WRITE(sc, reg, val) \

sys/dev/ral/rt2661reg.h

325

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/ral/rt2661var.h

137

uint8_t reg;

sys/dev/ral/rt2860.c

190

uint32_t reg;

sys/dev/ral/rt2860.c

197

uint8_t reg;

sys/dev/ral/rt2860.c

2024

rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)

sys/dev/ral/rt2860.c

2040

RT2860_BBP_CSR_KICK | reg << 8 | val);

sys/dev/ral/rt2860.c

2048

rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg)

sys/dev/ral/rt2860.c

2065

RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8);

sys/dev/ral/rt2860.c

2086

rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val)

sys/dev/ral/rt2860.c

2103

(val & 0x3fffff) << 2 | (reg & 3);

sys/dev/ral/rt2860.c

2108

rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg)

sys/dev/ral/rt2860.c

2122

tmp = RT3070_RF_KICK | reg << 8;

sys/dev/ral/rt2860.c

2139

rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)

sys/dev/ral/rt2860.c

2154

tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;

sys/dev/ral/rt2860.c

219

uint8_t reg;

sys/dev/ral/rt2860.c

2656

rt3090_rf_write(sc, rt3090_def_rf[i].reg,

sys/dev/ral/rt2860.c

2752

rt3090_rf_write(sc, rt5392_def_rf[i].reg,

sys/dev/ral/rt2860.c

2757

rt3090_rf_write(sc, rt5390_def_rf[i].reg,

sys/dev/ral/rt2860.c

2998

if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff)

sys/dev/ral/rt2860.c

3000

rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);

sys/dev/ral/rt2860.c

3390

sc->bbp[i].reg = val >> 8;

sys/dev/ral/rt2860.c

3391

DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val));

sys/dev/ral/rt2860.c

3398

sc->rf[i].reg = val >> 8;

sys/dev/ral/rt2860.c

3399

DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg,

sys/dev/ral/rt2860.c

3529

uint32_t reg;

sys/dev/ral/rt2860.c

3532

reg = val;

sys/dev/ral/rt2860.c

3534

reg |= (uint32_t)val << 16;

sys/dev/ral/rt2860.c

3536

sc->txpow20mhz[ridx] = reg;

sys/dev/ral/rt2860.c

3537

sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);

sys/dev/ral/rt2860.c

3538

sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);

sys/dev/ral/rt2860.c

3674

rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg,

sys/dev/ral/rt2860.c

3712

rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg,

sys/dev/ral/rt2860.c

3879

RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val);

sys/dev/ral/rt2860.c

3971

if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)

sys/dev/ral/rt2860.c

3973

rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);

sys/dev/ral/rt2860.c

964

uint16_t reg;

sys/dev/ral/rt2860.c

992

reg = RT3070_EFUSE_DATA3 - (addr & 0xc);

sys/dev/ral/rt2860.c

993

tmp = RAL_READ(sc, reg);

sys/dev/ral/rt2860reg.h

1000

#define RAL_WRITE(sc, reg, val) \

sys/dev/ral/rt2860reg.h

1001

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/ral/rt2860reg.h

997

#define RAL_READ(sc, reg) \

sys/dev/ral/rt2860reg.h

998

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/ral/rt2860var.h

187

uint8_t reg;

sys/dev/random/armv8rng.c

101

get_kernel_reg(ID_AA64ISAR0_EL1, &reg);

sys/dev/random/armv8rng.c

102

if (ID_AA64ISAR0_RNDR_VAL(reg) != ID_AA64ISAR0_RNDR_NONE) {

sys/dev/random/armv8rng.c

95

uint64_t reg;

sys/dev/rccgpio/rccgpio.c

87

rcc_gpio_modify_bits(struct rcc_gpio_softc *sc, uint32_t reg, uint32_t mask,

sys/dev/rccgpio/rccgpio.c

93

value = RCC_READ(sc, reg);

sys/dev/rccgpio/rccgpio.c

96

RCC_WRITE(sc, reg, value);

sys/dev/re/if_re.c

1223

phy, reg, rid;

sys/dev/re/if_re.c

1277

if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {

sys/dev/re/if_re.c

1279

sc->rl_expcap = reg;

sys/dev/re/if_re.c

3094

uint32_t reg;

sys/dev/re/if_re.c

3171

reg = 0x000fff00;

sys/dev/re/if_re.c

3173

reg |= 0x000000ff;

sys/dev/re/if_re.c

3175

reg |= 0x00f00000;

sys/dev/re/if_re.c

3176

CSR_WRITE_4(sc, 0x7c, reg);

sys/dev/re/if_re.c

449

re_gmii_readreg(device_t dev, int phy, int reg)

sys/dev/re/if_re.c

459

if (reg == RL_GMEDIASTAT) {

sys/dev/re/if_re.c

464

CSR_WRITE_4(sc, RL_PHYAR, reg << 16);

sys/dev/re/if_re.c

487

re_gmii_writereg(device_t dev, int phy, int reg, int data)

sys/dev/re/if_re.c

495

CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |

sys/dev/re/if_re.c

519

re_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/re/if_re.c

528

rval = re_gmii_readreg(dev, phy, reg);

sys/dev/re/if_re.c

532

switch (reg) {

sys/dev/re/if_re.c

573

re_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/re/if_re.c

582

rval = re_gmii_writereg(dev, phy, reg, data);

sys/dev/re/if_re.c

586

switch (reg) {

sys/dev/regulator/regulator.c

1004

regnode = reg->regnode;

sys/dev/regulator/regulator.c

1015

regulator_set_voltage(regulator_t reg, int min_uvolt, int max_uvolt)

sys/dev/regulator/regulator.c

1020

regnode = reg->regnode;

sys/dev/regulator/regulator.c

1026

rv = regnode_set_voltage_checked(regnode, reg, min_uvolt, max_uvolt);

sys/dev/regulator/regulator.c

1028

reg->min_uvolt = min_uvolt;

sys/dev/regulator/regulator.c

1029

reg->max_uvolt = max_uvolt;

sys/dev/regulator/regulator.c

1036

regulator_check_voltage(regulator_t reg, int uvolt)

sys/dev/regulator/regulator.c

1041

regnode = reg->regnode;

sys/dev/regulator/regulator.c

1052

regulator_get_name(regulator_t reg)

sys/dev/regulator/regulator.c

1056

regnode = reg->regnode;

sys/dev/regulator/regulator.c

1063

regulator_get_by_name(device_t cdev, const char *name, regulator_t *reg)

sys/dev/regulator/regulator.c

1073

*reg = regulator_create(regnode, cdev);

sys/dev/regulator/regulator.c

1079

regulator_get_by_id(device_t cdev, device_t pdev, intptr_t id, regulator_t *reg)

sys/dev/regulator/regulator.c

1090

*reg = regulator_create(regnode, cdev);

sys/dev/regulator/regulator.c

1097

regulator_release(regulator_t reg)

sys/dev/regulator/regulator.c

1101

regnode = reg->regnode;

sys/dev/regulator/regulator.c

1105

while (reg->enable_cnt > 0) {

sys/dev/regulator/regulator.c

1107

reg->enable_cnt--;

sys/dev/regulator/regulator.c

1110

TAILQ_REMOVE(&regnode->consumers_list, reg, link);

sys/dev/regulator/regulator.c

1115

free(reg, M_REGULATOR);

sys/dev/regulator/regulator.c

1204

regulator_t *reg)

sys/dev/regulator/regulator.c

1211

*reg = NULL;

sys/dev/regulator/regulator.c

1239

return (regulator_get_by_id(cdev, regdev, id, reg));

sys/dev/regulator/regulator.c

784

regnode_set_voltage_checked(struct regnode *regnode, struct regulator *reg,

sys/dev/regulator/regulator.c

808

if (tmp == reg)

sys/dev/regulator/regulator.c

903

struct regulator *reg;

sys/dev/regulator/regulator.c

907

reg = malloc(sizeof(struct regulator), M_REGULATOR,

sys/dev/regulator/regulator.c

909

reg->cdev = cdev;

sys/dev/regulator/regulator.c

910

reg->regnode = regnode;

sys/dev/regulator/regulator.c

911

reg->enable_cnt = 0;

sys/dev/regulator/regulator.c

915

TAILQ_INSERT_TAIL(&regnode->consumers_list, reg, link);

sys/dev/regulator/regulator.c

916

reg ->min_uvolt = regnode->std_param.min_uvolt;

sys/dev/regulator/regulator.c

917

reg ->max_uvolt = regnode->std_param.max_uvolt;

sys/dev/regulator/regulator.c

920

return (reg);

sys/dev/regulator/regulator.c

924

regulator_enable(regulator_t reg)

sys/dev/regulator/regulator.c

929

regnode = reg->regnode;

sys/dev/regulator/regulator.c

935

reg->enable_cnt++;

sys/dev/regulator/regulator.c

941

regulator_disable(regulator_t reg)

sys/dev/regulator/regulator.c

946

regnode = reg->regnode;

sys/dev/regulator/regulator.c

949

KASSERT(reg->enable_cnt > 0,

sys/dev/regulator/regulator.c

955

reg->enable_cnt--;

sys/dev/regulator/regulator.c

961

regulator_stop(regulator_t reg)

sys/dev/regulator/regulator.c

966

regnode = reg->regnode;

sys/dev/regulator/regulator.c

969

KASSERT(reg->enable_cnt == 0,

sys/dev/regulator/regulator.c

979

regulator_status(regulator_t reg, int *status)

sys/dev/regulator/regulator.c

984

regnode = reg->regnode;

sys/dev/regulator/regulator.c

988

if (reg->enable_cnt == 0) {

sys/dev/regulator/regulator.c

999

regulator_get_voltage(regulator_t reg, int *uvolt)

sys/dev/regulator/regulator.h

134

int regulator_enable(regulator_t reg);

sys/dev/regulator/regulator.h

135

int regulator_disable(regulator_t reg);

sys/dev/regulator/regulator.h

136

int regulator_stop(regulator_t reg);

sys/dev/regulator/regulator.h

137

int regulator_status(regulator_t reg, int *status);

sys/dev/regulator/regulator.h

138

int regulator_get_voltage(regulator_t reg, int *uvolt);

sys/dev/regulator/regulator.h

139

int regulator_set_voltage(regulator_t reg, int min_uvolt, int max_uvolt);

sys/dev/regulator/regulator.h

140

int regulator_check_voltage(regulator_t reg, int uvolt);

sys/dev/regulator/regulator.h

144

regulator_t *reg);

sys/dev/rge/if_rge.c

190

uint32_t hwrev, reg;

sys/dev/rge/if_rge.c

242

if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {

sys/dev/rge/if_rge.c

244

sc->sc_expcap = reg;

sys/dev/rge/if_rge.c

457

reg = pci_conf_read(pa->pa_pc, pa->pa_tag,

sys/dev/rge/if_rge.c

459

reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1 |

sys/dev/rge/if_rge.c

462

reg);

sys/dev/rge/if_rge_hw.c

1670

mac_r25_mcu[i].reg, mac_r25_mcu[i].val);

sys/dev/rge/if_rge_hw.c

1682

mac_r25b_mcu[i].reg, mac_r25b_mcu[i].val);

sys/dev/rge/if_rge_hw.c

1686

mac_r25d_1_mcu[i].reg,

sys/dev/rge/if_rge_hw.c

1693

mac_r25d_1_mcu[i].reg,

sys/dev/rge/if_rge_hw.c

1700

mac_r25d_1_mcu[i].reg,

sys/dev/rge/if_rge_hw.c

1705

mac_r25d_2_mcu[i].reg,

sys/dev/rge/if_rge_hw.c

1712

mac_r25d_2_mcu[i].reg,

sys/dev/rge/if_rge_hw.c

1717

mac_r26_1_mcu[i].reg, mac_r26_1_mcu[i].val);

sys/dev/rge/if_rge_hw.c

1723

mac_r26_1_mcu[i].reg, mac_r26_1_mcu[i].val);

sys/dev/rge/if_rge_hw.c

1727

mac_r26_2_mcu[i].reg, mac_r26_2_mcu[i].val);

sys/dev/rge/if_rge_hw.c

1731

mac_r27_mcu[i].reg, mac_r27_mcu[i].val);

sys/dev/rge/if_rge_hw.c

1737

mac_r27_mcu[i].reg, mac_r27_mcu[i].val);

sys/dev/rge/if_rge_hw.c

1791

uint16_t reg;

sys/dev/rge/if_rge_hw.c

1804

for (reg = 0xfc28; reg < 0xfc48; reg += 2)

sys/dev/rge/if_rge_hw.c

1805

rge_write_mac_ocp(sc, reg, 0);

sys/dev/rge/if_rge_hw.c

192

uint16_t reg;

sys/dev/rge/if_rge_hw.c

201

rtl8125_mac_bps[i].reg,

sys/dev/rge/if_rge_hw.c

2012

rge_write_csi(struct rge_softc *sc, uint32_t reg, uint32_t val)

sys/dev/rge/if_rge_hw.c

2017

RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |

sys/dev/rge/if_rge_hw.c

2030

rge_read_csi(struct rge_softc *sc, uint32_t reg)

sys/dev/rge/if_rge_hw.c

2034

RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |

sys/dev/rge/if_rge_hw.c

2049

rge_write_mac_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val)

sys/dev/rge/if_rge_hw.c

205

rtl8125_mac_bps[i].reg, 0);

sys/dev/rge/if_rge_hw.c

2053

tmp = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT;

sys/dev/rge/if_rge_hw.c

2060

rge_read_mac_ocp(struct rge_softc *sc, uint16_t reg)

sys/dev/rge/if_rge_hw.c

2064

val = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT;

sys/dev/rge/if_rge_hw.c

207

if (rtl8125_mac_bps[i].reg < 0xf9f8)

sys/dev/rge/if_rge_hw.c

2071

rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val)

sys/dev/rge/if_rge_hw.c

2076

tmp = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT;

sys/dev/rge/if_rge_hw.c

209

rtl8125_mac_bps[i].reg, 0);

sys/dev/rge/if_rge_hw.c

2090

rge_read_ephy(struct rge_softc *sc, uint16_t reg)

sys/dev/rge/if_rge_hw.c

2095

val = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT;

sys/dev/rge/if_rge_hw.c

2111

rge_check_ephy_ext_add(struct rge_softc *sc, uint16_t reg)

sys/dev/rge/if_rge_hw.c

2115

val = (reg >> 12);

sys/dev/rge/if_rge_hw.c

2118

return reg & 0x0fff;

sys/dev/rge/if_rge_hw.c

2122

rge_r27_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val)

sys/dev/rge/if_rge_hw.c

2124

rge_write_ephy(sc, rge_check_ephy_ext_add(sc, reg), val);

sys/dev/rge/if_rge_hw.c

2128

rge_write_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg, uint16_t val)

sys/dev/rge/if_rge_hw.c

2132

phyaddr = addr ? addr : RGE_PHYBASE + (reg / 8);

sys/dev/rge/if_rge_hw.c

2135

off = addr ? reg : 0x10 + (reg % 8);

sys/dev/rge/if_rge_hw.c

2143

rge_read_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg)

sys/dev/rge/if_rge_hw.c

2147

phyaddr = addr ? addr : RGE_PHYBASE + (reg / 8);

sys/dev/rge/if_rge_hw.c

2150

off = addr ? reg : 0x10 + (reg % 8);

sys/dev/rge/if_rge_hw.c

2158

rge_write_phy_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val)

sys/dev/rge/if_rge_hw.c

2163

tmp = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT;

sys/dev/rge/if_rge_hw.c

2175

rge_read_phy_ocp(struct rge_softc *sc, uint16_t reg)

sys/dev/rge/if_rge_hw.c

2180

val = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT;

sys/dev/rge/if_rge_hw.c

231

rge_write_mac_ocp(sc, rtl8125b_mac_bps[i].reg,

sys/dev/rge/if_rge_hw.c

257

for (reg = 0xf812; reg <= 0xf9f6; reg += 2)

sys/dev/rge/if_rge_hw.c

258

rge_write_mac_ocp(sc, reg, 0);

sys/dev/rge/if_rge_hw.c

279

rtl8125d_2_mac_bps[i].reg,

sys/dev/rge/if_rge_hw.c

283

rtl8125d_2_mac_bps[i].reg, 0);

sys/dev/rge/if_rge_hw.c

286

for (reg = 0xf884; reg <= 0xf9f6; reg += 2)

sys/dev/rge/if_rge_hw.c

287

rge_write_mac_ocp(sc, reg, 0);

sys/dev/rge/if_rge_hw.c

450

rge_write_ephy(sc, mac_r25_ephy[i].reg, mac_r25_ephy[i].val);

sys/dev/rge/if_rge_hw.c

474

rge_write_ephy(sc, mac_r25b_ephy[i].reg, mac_r25b_ephy[i].val);

sys/dev/rge/if_rge_hw.c

483

rge_r27_write_ephy(sc, mac_r27_ephy[i].reg,

sys/dev/rge/if_rge_hw.c

92

static void rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val);

sys/dev/rge/if_rge_hw.c

93

static uint16_t rge_read_ephy(struct rge_softc *sc, uint16_t reg);

sys/dev/rge/if_rge_hw.c

94

static uint16_t rge_check_ephy_ext_add(struct rge_softc *sc, uint16_t reg);

sys/dev/rge/if_rge_hw.c

95

static void rge_r27_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val);

sys/dev/rge/if_rge_hw.h

38

extern uint16_t rge_read_phy_ocp(struct rge_softc *sc, uint16_t reg);

sys/dev/rge/if_rge_microcode.h

10245

uint16_t reg;

sys/dev/rge/if_rge_microcode.h

27

uint16_t reg;

sys/dev/rge/if_rge_stats.c

112

reg = RGE_READ_4(sc, RGE_DTCCR_LO);

sys/dev/rge/if_rge_stats.c

113

if ((reg & RGE_DTCCR_CMD) == 0)

sys/dev/rge/if_rge_stats.c

123

if ((reg & RGE_DTCCR_CMD) != 0)

sys/dev/rge/if_rge_stats.c

80

uint32_t reg;

sys/dev/rge/if_rgevar.h

217

#define RGE_WRITE_4(sc, reg, val) \

sys/dev/rge/if_rgevar.h

218

bus_space_write_4(sc->rge_btag, sc->rge_bhandle, reg, val)

sys/dev/rge/if_rgevar.h

219

#define RGE_WRITE_2(sc, reg, val) \

sys/dev/rge/if_rgevar.h

220

bus_space_write_2(sc->rge_btag, sc->rge_bhandle, reg, val)

sys/dev/rge/if_rgevar.h

221

#define RGE_WRITE_1(sc, reg, val) \

sys/dev/rge/if_rgevar.h

222

bus_space_write_1(sc->rge_btag, sc->rge_bhandle, reg, val)

sys/dev/rge/if_rgevar.h

224

#define RGE_WRITE_BARRIER_4(sc, reg) \

sys/dev/rge/if_rgevar.h

225

bus_space_barrier(sc->rge_btag, sc->rge_bhandle, reg, 4, \

sys/dev/rge/if_rgevar.h

227

#define RGE_READ_BARRIER_4(sc, reg) \

sys/dev/rge/if_rgevar.h

228

bus_space_barrier(sc->rge_btag, sc->rge_bhandle, reg, 4, \

sys/dev/rge/if_rgevar.h

232

#define RGE_READ_4(sc, reg) \

sys/dev/rge/if_rgevar.h

233

bus_space_read_4(sc->rge_btag, sc->rge_bhandle, reg)

sys/dev/rge/if_rgevar.h

234

#define RGE_READ_2(sc, reg) \

sys/dev/rge/if_rgevar.h

235

bus_space_read_2(sc->rge_btag, sc->rge_bhandle, reg)

sys/dev/rge/if_rgevar.h

236

#define RGE_READ_1(sc, reg) \

sys/dev/rge/if_rgevar.h

237

bus_space_read_1(sc->rge_btag, sc->rge_bhandle, reg)

sys/dev/rge/if_rgevar.h

239

#define RGE_SETBIT_4(sc, reg, val) \

sys/dev/rge/if_rgevar.h

240

RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) | (val))

sys/dev/rge/if_rgevar.h

241

#define RGE_SETBIT_2(sc, reg, val) \

sys/dev/rge/if_rgevar.h

242

RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) | (val))

sys/dev/rge/if_rgevar.h

243

#define RGE_SETBIT_1(sc, reg, val) \

sys/dev/rge/if_rgevar.h

244

RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) | (val))

sys/dev/rge/if_rgevar.h

246

#define RGE_CLRBIT_4(sc, reg, val) \

sys/dev/rge/if_rgevar.h

247

RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) & ~(val))

sys/dev/rge/if_rgevar.h

248

#define RGE_CLRBIT_2(sc, reg, val) \

sys/dev/rge/if_rgevar.h

249

RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) & ~(val))

sys/dev/rge/if_rgevar.h

250

#define RGE_CLRBIT_1(sc, reg, val) \

sys/dev/rge/if_rgevar.h

251

RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) & ~(val))

sys/dev/rge/if_rgevar.h

253

#define RGE_EPHY_SETBIT(sc, reg, val) \

sys/dev/rge/if_rgevar.h

254

rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) | (val))

sys/dev/rge/if_rgevar.h

256

#define RGE_EPHY_CLRBIT(sc, reg, val) \

sys/dev/rge/if_rgevar.h

257

rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) & ~(val))

sys/dev/rge/if_rgevar.h

259

#define RGE_PHY_SETBIT(sc, reg, val) \

sys/dev/rge/if_rgevar.h

260

rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) | (val))

sys/dev/rge/if_rgevar.h

262

#define RGE_PHY_CLRBIT(sc, reg, val) \

sys/dev/rge/if_rgevar.h

263

rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) & ~(val))

sys/dev/rge/if_rgevar.h

265

#define RGE_MAC_SETBIT(sc, reg, val) \

sys/dev/rge/if_rgevar.h

266

rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) | (val))

sys/dev/rge/if_rgevar.h

268

#define RGE_MAC_CLRBIT(sc, reg, val) \

sys/dev/rge/if_rgevar.h

269

rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) & ~(val))

sys/dev/rl/if_rl.c

388

rl_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/rl/if_rl.c

396

switch (reg) {

sys/dev/rl/if_rl.c

430

return (mii_bitbang_readreg(dev, &rl_mii_bitbang_ops, phy, reg));

sys/dev/rl/if_rl.c

434

rl_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/rl/if_rl.c

442

switch (reg) {

sys/dev/rl/if_rl.c

470

mii_bitbang_writereg(dev, &rl_mii_bitbang_ops, phy, reg, data);

sys/dev/rl/if_rlreg.h

945

#define CSR_WRITE_STREAM_4(sc, reg, val) \

sys/dev/rl/if_rlreg.h

946

bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)

sys/dev/rl/if_rlreg.h

947

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/rl/if_rlreg.h

948

bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)

sys/dev/rl/if_rlreg.h

949

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/rl/if_rlreg.h

950

bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)

sys/dev/rl/if_rlreg.h

951

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/rl/if_rlreg.h

952

bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)

sys/dev/rl/if_rlreg.h

954

#define CSR_READ_4(sc, reg) \

sys/dev/rl/if_rlreg.h

955

bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)

sys/dev/rl/if_rlreg.h

956

#define CSR_READ_2(sc, reg) \

sys/dev/rl/if_rlreg.h

957

bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)

sys/dev/rl/if_rlreg.h

958

#define CSR_READ_1(sc, reg) \

sys/dev/rl/if_rlreg.h

959

bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)

sys/dev/rl/if_rlreg.h

961

#define CSR_BARRIER(sc, reg, length, flags) \

sys/dev/rl/if_rlreg.h

962

bus_space_barrier(sc->rl_btag, sc->rl_bhandle, reg, length, flags)

sys/dev/rtsx/rtsx.c

1338

uint32_t reg;

sys/dev/rtsx/rtsx.c

1344

reg = READ4(sc, RTSX_HAIMR);

sys/dev/rtsx/rtsx.c

1345

if (!(reg & RTSX_HAIMR_BUSY))

sys/dev/rtsx/rtsx.c

1348

*val = (reg & 0xff);

sys/dev/rtsx/rtsx.c

1392

uint32_t reg;

sys/dev/rtsx/rtsx.c

1400

reg = READ4(sc, RTSX_HAIMR);

sys/dev/rtsx/rtsx.c

1401

if (!(reg & RTSX_HAIMR_BUSY)) {

sys/dev/rtsx/rtsx.c

1402

if (val != (reg & 0xff)) {

sys/dev/rtsx/rtsx.c

1403

device_printf(sc->rtsx_dev, "rtsx_write(0x%x) error reg=0x%x\n", arg, reg);

sys/dev/rtsx/rtsx.c

2228

rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg,

sys/dev/rtsx/rtsx.c

2237

((uint32_t)(reg & 0x3fff) << 16) |

sys/dev/rtsx/rtsx.c

2358

uint16_t reg;

sys/dev/rtsx/rtsx.c

2390

for (reg = RTSX_PPBUF_BASE2; reg < RTSX_PPBUF_BASE2 + 16; reg++)

sys/dev/rtsx/rtsx.c

2391

rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0);

sys/dev/rtsx/rtsx.c

2394

for (reg = RTSX_SD_CMD0; reg <= RTSX_SD_CMD4; reg++)

sys/dev/rtsx/rtsx.c

2395

rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0);

sys/dev/rtsx/rtsx.c

242

static void rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg,

sys/dev/rtsx/rtsx.c

2553

uint16_t reg = RTSX_PPBUF_BASE2;

sys/dev/rtsx/rtsx.c

2562

rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0);

sys/dev/rtsx/rtsx.c

2597

uint16_t reg = RTSX_PPBUF_BASE2 + RTSX_HOSTCMD_MAX;

sys/dev/rtsx/rtsx.c

2602

rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0);

sys/dev/rtsx/rtsx.c

2661

uint16_t reg = RTSX_PPBUF_BASE2;

sys/dev/rtsx/rtsx.c

2674

rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr);

sys/dev/rtsx/rtsx.c

2696

uint16_t reg = RTSX_PPBUF_BASE2 + RTSX_HOSTCMD_MAX;

sys/dev/rtsx/rtsx.c

2708

rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr);

sys/dev/rtsx/rtsx.c

318

#define READ4(sc, reg) \

sys/dev/rtsx/rtsx.c

319

(bus_space_read_4((sc)->rtsx_mem_btag, (sc)->rtsx_mem_bhandle, (reg)))

sys/dev/rtsx/rtsx.c

320

#define WRITE4(sc, reg, val) \

sys/dev/rtsx/rtsx.c

321

(bus_space_write_4((sc)->rtsx_mem_btag, (sc)->rtsx_mem_bhandle, (reg), (val)))

sys/dev/rtsx/rtsx.c

323

#define RTSX_READ(sc, reg, val) \

sys/dev/rtsx/rtsx.c

325

int err = rtsx_read((sc), (reg), (val)); \

sys/dev/rtsx/rtsx.c

330

#define RTSX_WRITE(sc, reg, val) \

sys/dev/rtsx/rtsx.c

332

int err = rtsx_write((sc), (reg), 0xff, (val)); \

sys/dev/rtsx/rtsx.c

336

#define RTSX_CLR(sc, reg, bits) \

sys/dev/rtsx/rtsx.c

338

int err = rtsx_write((sc), (reg), (bits), 0); \

sys/dev/rtsx/rtsx.c

343

#define RTSX_SET(sc, reg, bits) \

sys/dev/rtsx/rtsx.c

345

int err = rtsx_write((sc), (reg), (bits), 0xff);\

sys/dev/rtsx/rtsx.c

350

#define RTSX_BITOP(sc, reg, mask, bits) \

sys/dev/rtsx/rtsx.c

352

int err = rtsx_write((sc), (reg), (mask), (bits)); \

sys/dev/rtsx/rtsx.c

778

uint32_t reg;

sys/dev/rtsx/rtsx.c

784

reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4);

sys/dev/rtsx/rtsx.c

785

if (!(reg & 0x80)) {

sys/dev/rtsx/rtsx.c

786

sc->rtsx_card_drive_sel = (reg >> 8) & 0x3F;

sys/dev/rtsx/rtsx.c

787

sc->rtsx_sd30_drive_sel_3v3 = reg & 0x07;

sys/dev/rtsx/rtsx.c

789

device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);

sys/dev/rtsx/rtsx.c

798

reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);

sys/dev/rtsx/rtsx.c

799

if (!(reg & 0x1000000)) {

sys/dev/rtsx/rtsx.c

801

sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6;

sys/dev/rtsx/rtsx.c

802

reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4);

sys/dev/rtsx/rtsx.c

803

sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03;

sys/dev/rtsx/rtsx.c

804

if (reg & 0x4000)

sys/dev/rtsx/rtsx.c

807

device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);

sys/dev/rtsx/rtsx.c

817

reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);

sys/dev/rtsx/rtsx.c

818

if (!(reg & 0x1000000)) {

sys/dev/rtsx/rtsx.c

820

sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6;

sys/dev/rtsx/rtsx.c

821

reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4);

sys/dev/rtsx/rtsx.c

822

sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive((reg >> 5) & 0x03);

sys/dev/rtsx/rtsx.c

824

device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);

sys/dev/rtsx/rtsx.c

834

reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);

sys/dev/rtsx/rtsx.c

835

if ((reg & 0x1000000)) {

sys/dev/rtsx/rtsx.c

837

sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6;

sys/dev/rtsx/rtsx.c

838

reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4);

sys/dev/rtsx/rtsx.c

839

sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03;

sys/dev/rtsx/rtsx.c

840

if (reg & 0x4000)

sys/dev/rtsx/rtsx.c

843

device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);

sys/dev/rtsx/rtsx.c

872

reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);

sys/dev/rtsx/rtsx.c

873

if (!(reg & 0x1000000)) {

sys/dev/rtsx/rtsx.c

874

sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive(reg & 0x03);

sys/dev/rtsx/rtsx.c

876

device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);

sys/dev/rtwn/if_rtwn.c

1062

uint32_t reg;

sys/dev/rtwn/if_rtwn.c

1064

reg = rtwn_read_4(sc, R92C_WMAC_TRXPTCL_CTL);

sys/dev/rtwn/if_rtwn.c

1066

reg |= R92C_WMAC_TRXPTCL_SHPRE;

sys/dev/rtwn/if_rtwn.c

1068

reg &= ~R92C_WMAC_TRXPTCL_SHPRE;

sys/dev/rtwn/if_rtwn.c

1069

rtwn_write_4(sc, R92C_WMAC_TRXPTCL_CTL, reg);

sys/dev/rtwn/if_rtwn.c

1514

uint16_t reg;

sys/dev/rtwn/if_rtwn.c

1556

reg = rtwn_get_qmap(sc);

sys/dev/rtwn/if_rtwn.c

1558

R92C_TRXDMA_CTRL_QMAP_M, reg));

sys/dev/rtwn/if_rtwn.c

1580

error = rtwn_write_1(sc, sc->mac_prog[i].reg,

sys/dev/rtwn/if_rtwn.c

725

uint32_t reg;

sys/dev/rtwn/if_rtwn.c

727

reg = rtwn_read_4(sc, R92C_SYS_CFG);

sys/dev/rtwn/if_rtwn.c

728

if (reg & R92C_SYS_CFG_TRP_VAUX_EN) /* test chip */

sys/dev/rtwn/if_rtwn.c

731

rtwn_read_chipid_vendor(sc, reg);

sys/dev/rtwn/if_rtwn_beacon.c

65

uint16_t reg;

sys/dev/rtwn/if_rtwn_beacon.c

71

reg = sc->bcn_status_reg[id];

sys/dev/rtwn/if_rtwn_beacon.c

73

if (rtwn_read_4(sc, reg) & R92C_TDECTRL_BCN_VALID) {

sys/dev/rtwn/if_rtwn_efuse.c

100

if (reg & R92C_EFUSE_CTRL_VALID)

sys/dev/rtwn/if_rtwn_efuse.c

111

*val = MS(reg, R92C_EFUSE_CTRL_DATA);

sys/dev/rtwn/if_rtwn_efuse.c

121

uint8_t reg;

sys/dev/rtwn/if_rtwn_efuse.c

132

error = rtwn_efuse_read_next(sc, &reg);

sys/dev/rtwn/if_rtwn_efuse.c

136

addr, reg);

sys/dev/rtwn/if_rtwn_efuse.c

137

rom[addr] = reg;

sys/dev/rtwn/if_rtwn_efuse.c

139

error = rtwn_efuse_read_next(sc, &reg);

sys/dev/rtwn/if_rtwn_efuse.c

143

addr + 1, reg);

sys/dev/rtwn/if_rtwn_efuse.c

144

rom[addr + 1] = reg;

sys/dev/rtwn/if_rtwn_efuse.c

177

uint8_t msk, off, reg;

sys/dev/rtwn/if_rtwn_efuse.c

184

RTWN_CHK(rtwn_efuse_read_next(sc, &reg));

sys/dev/rtwn/if_rtwn_efuse.c

185

while (reg != 0xff) {

sys/dev/rtwn/if_rtwn_efuse.c

188

(reg & 0x1f) == 0x0f) {

sys/dev/rtwn/if_rtwn_efuse.c

189

off = reg >> 5;

sys/dev/rtwn/if_rtwn_efuse.c

190

RTWN_CHK(rtwn_efuse_read_next(sc, &reg));

sys/dev/rtwn/if_rtwn_efuse.c

192

if ((reg & 0x0f) != 0x0f)

sys/dev/rtwn/if_rtwn_efuse.c

193

off = ((reg & 0xf0) >> 1) | off;

sys/dev/rtwn/if_rtwn_efuse.c

197

off = reg >> 4;

sys/dev/rtwn/if_rtwn_efuse.c

198

msk = reg & 0xf;

sys/dev/rtwn/if_rtwn_efuse.c

201

RTWN_CHK(rtwn_efuse_read_next(sc, &reg));

sys/dev/rtwn/if_rtwn_efuse.c

55

uint32_t reg;

sys/dev/rtwn/if_rtwn_efuse.c

62

reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN);

sys/dev/rtwn/if_rtwn_efuse.c

63

if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {

sys/dev/rtwn/if_rtwn_efuse.c

65

reg | R92C_SYS_FUNC_EN_ELDR);

sys/dev/rtwn/if_rtwn_efuse.c

69

reg = rtwn_read_2(sc, R92C_SYS_CLKR);

sys/dev/rtwn/if_rtwn_efuse.c

70

if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=

sys/dev/rtwn/if_rtwn_efuse.c

73

reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);

sys/dev/rtwn/if_rtwn_efuse.c

84

uint32_t reg;

sys/dev/rtwn/if_rtwn_efuse.c

90

reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);

sys/dev/rtwn/if_rtwn_efuse.c

91

reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->next_rom_addr);

sys/dev/rtwn/if_rtwn_efuse.c

92

reg &= ~R92C_EFUSE_CTRL_VALID;

sys/dev/rtwn/if_rtwn_efuse.c

94

error = rtwn_write_4(sc, R92C_EFUSE_CTRL, reg);

sys/dev/rtwn/if_rtwn_efuse.c

99

reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);

sys/dev/rtwn/if_rtwn_fw.c

59

uint32_t reg;

sys/dev/rtwn/if_rtwn_fw.c

63

reg = rtwn_read_4(sc, R92C_MCUFWDL);

sys/dev/rtwn/if_rtwn_fw.c

64

reg = RW(reg, R92C_MCUFWDL_PAGE, page);

sys/dev/rtwn/if_rtwn_fw.c

65

rtwn_write_4(sc, R92C_MCUFWDL, reg);

sys/dev/rtwn/if_rtwn_nop.h

43

rtwn_nop_softc_uint32(struct rtwn_softc *sc, uint32_t reg)

sys/dev/rtwn/if_rtwnreg.h

122

uint16_t reg;

sys/dev/rtwn/if_rtwnreg.h

131

const uint16_t *reg;

sys/dev/rtwn/if_rtwnreg.h

149

const uint8_t *reg;

sys/dev/rtwn/pci/rtwn_pci_attach.c

491

uint16_t reg, int mlen)

sys/dev/rtwn/pci/rtwn_pci_attach.c

496

rtwn_pci_write_1(sc, reg++, buf[i]);

sys/dev/rtwn/rtl8188e/pci/r88ee_init.c

160

uint8_t reg;

sys/dev/rtwn/rtl8188e/pci/r88ee_init.c

244

reg = rtwn_read_1(sc, R92C_RSV_CTRL + 1);

sys/dev/rtwn/rtl8188e/pci/r88ee_init.c

245

rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08);

sys/dev/rtwn/rtl8188e/pci/r88ee_init.c

246

rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08);

sys/dev/rtwn/rtl8188e/r88e_calib.c

312

uint32_t reg, val, x;

sys/dev/rtwn/rtl8188e/r88e_calib.c

318

reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(0));

sys/dev/rtwn/rtl8188e/r88e_calib.c

319

val = ((reg >> 22) & 0x3ff);

sys/dev/rtwn/rtl8188e/r88e_calib.c

323

reg = (((x * val) >> 8) & 0x3ff);

sys/dev/rtwn/rtl8188e/r88e_calib.c

324

rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(0), 0x3ff, reg);

sys/dev/rtwn/rtl8188e/r88e_fw.c

105

uint16_t reg;

sys/dev/rtwn/rtl8188e/r88e_fw.c

107

reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN);

sys/dev/rtwn/rtl8188e/r88e_fw.c

108

rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);

sys/dev/rtwn/rtl8188e/r88e_fw.c

112

reg | R92C_SYS_FUNC_EN_CPUEN);

sys/dev/rtwn/rtl8188e/r88e_fw.c

137

uint32_t reg;

sys/dev/rtwn/rtl8188e/r88e_fw.c

139

reg = R88E_MACID_NO_LINK;

sys/dev/rtwn/rtl8188e/r88e_fw.c

141

reg += 4;

sys/dev/rtwn/rtl8188e/r88e_fw.c

144

rtwn_setbits_4(sc, reg, 1 << (id % 32), 0);

sys/dev/rtwn/rtl8188e/r88e_fw.c

146

rtwn_setbits_4(sc, reg, 0, 1 << (id % 32));

sys/dev/rtwn/rtl8188e/r88e_init.c

60

uint32_t reg;

sys/dev/rtwn/rtl8188e/r88e_init.c

64

reg = rtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);

sys/dev/rtwn/rtl8188e/r88e_init.c

66

RW(reg, R92C_AFE_XTAL_CTRL_ADDR, val | val << 6));

sys/dev/rtwn/rtl8188e/usb/r88eu_init.c

138

uint8_t reg;

sys/dev/rtwn/rtl8188e/usb/r88eu_init.c

238

reg = rtwn_read_1(sc, R92C_RSV_CTRL + 1);

sys/dev/rtwn/rtl8188e/usb/r88eu_init.c

239

rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08);

sys/dev/rtwn/rtl8188e/usb/r88eu_init.c

240

rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08);

sys/dev/rtwn/rtl8192c/pci/r92ce_calib.c

314

uint32_t reg, val, x;

sys/dev/rtwn/rtl8192c/pci/r92ce_calib.c

320

reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain));

sys/dev/rtwn/rtl8192c/pci/r92ce_calib.c

321

val = ((reg >> 22) & 0x3ff);

sys/dev/rtwn/rtl8192c/pci/r92ce_calib.c

325

reg = (((x * val) >> 8) & 0x3ff);

sys/dev/rtwn/rtl8192c/pci/r92ce_calib.c

326

rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x3ff, reg);

sys/dev/rtwn/rtl8192c/pci/r92ce_init.c

111

uint32_t reg;

sys/dev/rtwn/rtl8192c/pci/r92ce_init.c

193

reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL);

sys/dev/rtwn/rtl8192c/pci/r92ce_init.c

194

if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) {

sys/dev/rtwn/rtl8192c/r92c_calib.c

333

uint32_t reg, val, x;

sys/dev/rtwn/rtl8192c/r92c_calib.c

339

reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain));

sys/dev/rtwn/rtl8192c/r92c_calib.c

340

val = ((reg >> 22) & 0x3ff);

sys/dev/rtwn/rtl8192c/r92c_calib.c

344

reg = (((x * val) >> 8) & 0x3ff);

sys/dev/rtwn/rtl8192c/r92c_calib.c

345

rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x3ff, reg);

sys/dev/rtwn/rtl8192c/r92c_chan.c

219

uint32_t reg;

sys/dev/rtwn/rtl8192c/r92c_chan.c

223

reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);

sys/dev/rtwn/rtl8192c/r92c_chan.c

224

reg = RW(reg, R92C_TXAGC_A_CCK1, power[RTWN_RIDX_CCK1]);

sys/dev/rtwn/rtl8192c/r92c_chan.c

225

rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);

sys/dev/rtwn/rtl8192c/r92c_chan.c

226

reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);

sys/dev/rtwn/rtl8192c/r92c_chan.c

227

reg = RW(reg, R92C_TXAGC_A_CCK2, power[RTWN_RIDX_CCK2]);

sys/dev/rtwn/rtl8192c/r92c_chan.c

228

reg = RW(reg, R92C_TXAGC_A_CCK55, power[RTWN_RIDX_CCK55]);

sys/dev/rtwn/rtl8192c/r92c_chan.c

229

reg = RW(reg, R92C_TXAGC_A_CCK11, power[RTWN_RIDX_CCK11]);

sys/dev/rtwn/rtl8192c/r92c_chan.c

230

rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);

sys/dev/rtwn/rtl8192c/r92c_chan.c

232

reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);

sys/dev/rtwn/rtl8192c/r92c_chan.c

233

reg = RW(reg, R92C_TXAGC_B_CCK1, power[RTWN_RIDX_CCK1]);

sys/dev/rtwn/rtl8192c/r92c_chan.c

234

reg = RW(reg, R92C_TXAGC_B_CCK2, power[RTWN_RIDX_CCK2]);

sys/dev/rtwn/rtl8192c/r92c_chan.c

235

reg = RW(reg, R92C_TXAGC_B_CCK55, power[RTWN_RIDX_CCK55]);

sys/dev/rtwn/rtl8192c/r92c_chan.c

236

rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);

sys/dev/rtwn/rtl8192c/r92c_chan.c

237

reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);

sys/dev/rtwn/rtl8192c/r92c_chan.c

238

reg = RW(reg, R92C_TXAGC_B_CCK11, power[RTWN_RIDX_CCK11]);

sys/dev/rtwn/rtl8192c/r92c_chan.c

239

rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);

sys/dev/rtwn/rtl8192c/r92c_init.c

142

bb_prog->reg[j], bb_prog->val[j]);

sys/dev/rtwn/rtl8192c/r92c_init.c

144

rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]);

sys/dev/rtwn/rtl8192c/r92c_init.c

199

for (i = 0; rf_prog[i].reg != NULL; i++) {

sys/dev/rtwn/rtl8192c/r92c_init.c

212

prog->reg[j], prog->val[j]);

sys/dev/rtwn/rtl8192c/r92c_init.c

219

if (prog->reg[j] > 0xf8) {

sys/dev/rtwn/rtl8192c/r92c_init.c

224

rtwn_rf_write(sc, chain, prog->reg[j], prog->val[j]);

sys/dev/rtwn/rtl8192c/r92c_init.c

236

uint32_t reg, type;

sys/dev/rtwn/rtl8192c/r92c_init.c

243

reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));

sys/dev/rtwn/rtl8192c/r92c_init.c

244

type = (reg >> off) & 0x10;

sys/dev/rtwn/rtl8192c/r92c_init.c

313

uint32_t reg;

sys/dev/rtwn/rtl8192c/r92c_init.c

320

reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));

sys/dev/rtwn/rtl8192c/r92c_init.c

321

sc->sc_ant = MS(reg, R92C_FPGA0_RFIFACEOE0_ANT); /* XXX */

sys/dev/rtwn/rtl8192c/r92c_rf.c

57

uint32_t reg[R92C_MAX_CHAINS], val;

sys/dev/rtwn/rtl8192c/r92c_rf.c

59

reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0));

sys/dev/rtwn/rtl8192c/r92c_rf.c

61

reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));

sys/dev/rtwn/rtl8192c/r92c_rf.c

64

reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);

sys/dev/rtwn/rtl8192c/r92c_rf.c

68

RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |

sys/dev/rtwn/rtl8192c/r92c_rf.c

73

reg[0] | R92C_HSSI_PARAM2_READ_EDGE);

sys/dev/rtwn/rtl8192c/usb/r92cu_init.c

111

reg = rtwn_read_1(sc, R92C_LDOV12D_CTRL);

sys/dev/rtwn/rtl8192c/usb/r92cu_init.c

112

if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) {

sys/dev/rtwn/rtl8192c/usb/r92cu_init.c

114

reg | R92C_LDOV12D_CTRL_LDV12_EN));

sys/dev/rtwn/rtl8192c/usb/r92cu_init.c

183

uint32_t reg;

sys/dev/rtwn/rtl8192c/usb/r92cu_init.c

264

reg = rtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00;

sys/dev/rtwn/rtl8192c/usb/r92cu_init.c

265

reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000;

sys/dev/rtwn/rtl8192c/usb/r92cu_init.c

266

rtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg);

sys/dev/rtwn/rtl8192c/usb/r92cu_init.c

271

reg = rtwn_read_2(sc, R92C_GPIO_IO_SEL) & ~0x00f0;

sys/dev/rtwn/rtl8192c/usb/r92cu_init.c

272

reg |= (((reg & 0x000f) << 4) | 0x0780);

sys/dev/rtwn/rtl8192c/usb/r92cu_init.c

273

rtwn_write_2(sc, R92C_GPIO_IO_SEL, reg);

sys/dev/rtwn/rtl8192c/usb/r92cu_init.c

329

uint32_t reg;

sys/dev/rtwn/rtl8192c/usb/r92cu_init.c

331

reg = rtwn_read_4(sc, R92C_TDECTRL);

sys/dev/rtwn/rtl8192c/usb/r92cu_init.c

332

reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, uc->tx_agg_desc_num);

sys/dev/rtwn/rtl8192c/usb/r92cu_init.c

333

rtwn_write_4(sc, R92C_TDECTRL, reg);

sys/dev/rtwn/rtl8192c/usb/r92cu_init.c

87

uint32_t reg;

sys/dev/rtwn/rtl8192c/usb/r92cu_led.c

54

uint8_t reg;

sys/dev/rtwn/rtl8192c/usb/r92cu_led.c

57

reg = rtwn_read_1(sc, R92C_LEDCFG0) & 0x70;

sys/dev/rtwn/rtl8192c/usb/r92cu_led.c

59

reg |= R92C_LEDCFG0_DIS;

sys/dev/rtwn/rtl8192c/usb/r92cu_led.c

60

rtwn_write_1(sc, R92C_LEDCFG0, reg);

sys/dev/rtwn/rtl8192e/r92e_init.c

124

bb_prog->reg[j], bb_prog->val[j]);

sys/dev/rtwn/rtl8192e/r92e_init.c

126

rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]);

sys/dev/rtwn/rtl8192e/r92e_init.c

167

uint32_t reg, type;

sys/dev/rtwn/rtl8192e/r92e_init.c

174

reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));

sys/dev/rtwn/rtl8192e/r92e_init.c

175

type = (reg >> off) & 0x10;

sys/dev/rtwn/rtl8192e/r92e_init.c

197

reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));

sys/dev/rtwn/rtl8192e/r92e_init.c

198

reg &= ~(0x10 << off) | (type << off);

sys/dev/rtwn/rtl8192e/r92e_init.c

199

rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg);

sys/dev/rtwn/rtl8192e/r92e_init.c

83

uint32_t reg;

sys/dev/rtwn/rtl8192e/r92e_init.c

87

reg = rtwn_bb_read(sc, R92E_AFE_XTAL_CTRL);

sys/dev/rtwn/rtl8192e/r92e_init.c

89

RW(reg, R92E_AFE_XTAL_CTRL_ADDR, val | val << 6));

sys/dev/rtwn/rtl8812a/r12a_init.c

162

bb_prog->reg[j], bb_prog->val[j]);

sys/dev/rtwn/rtl8812a/r12a_init.c

164

rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]);

sys/dev/rtwn/rtl8812a/r12a_init.c

219

uint32_t reg;

sys/dev/rtwn/rtl8812a/r12a_init.c

223

reg = rtwn_bb_read(sc, R92C_MAC_PHY_CTRL);

sys/dev/rtwn/rtl8812a/r12a_init.c

224

reg = RW(reg, R12A_MAC_PHY_CRYSTALCAP, val | (val << 6));

sys/dev/rtwn/rtl8812a/r12a_init.c

225

rtwn_bb_write(sc, R92C_MAC_PHY_CTRL, reg);

sys/dev/rtwn/rtl8812a/r12a_init.c

477

uint32_t reg;

sys/dev/rtwn/rtl8812a/r12a_init.c

481

reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));

sys/dev/rtwn/rtl8812a/r12a_init.c

482

sc->sc_ant = MS(reg, R92C_FPGA0_RFIFACEOE0_ANT);

sys/dev/rtwn/rtl8821a/r21a_init.c

322

uint32_t reg;

sys/dev/rtwn/rtl8821a/r21a_init.c

326

reg = rtwn_bb_read(sc, R92C_MAC_PHY_CTRL);

sys/dev/rtwn/rtl8821a/r21a_init.c

327

reg = RW(reg, R21A_MAC_PHY_CRYSTALCAP, val | (val << 6));

sys/dev/rtwn/rtl8821a/r21a_init.c

328

rtwn_bb_write(sc, R92C_MAC_PHY_CTRL, reg);

sys/dev/rtwn/usb/rtwn_usb_attach.c

313

uint16_t reg, int mlen)

sys/dev/rtwn/usb/rtwn_usb_attach.c

318

error = rtwn_usb_write_region_1(sc, reg, __DECONST(uint8_t *, buf),

sys/dev/safe/safe.c

169

#define WRITE_REG(sc,reg,val) \

sys/dev/safe/safe.c

170

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)

sys/dev/safexcel/safexcel.c

304

uint32_t i, mask, pemask, reg;

sys/dev/safexcel/safexcel.c

316

reg = SAFEXCEL_READ(sc, SAFEXCEL_HIA_AIC_R(sc) +

sys/dev/safexcel/safexcel.c

318

if (SAFEXCEL_REG_LO16(reg) != EIP201_VERSION_LE)

sys/dev/safexcel/safexcel.c

325

reg = SAFEXCEL_READ(sc, SAFEXCEL_HIA_AIC_G(sc) + SAFEXCEL_HIA_OPTIONS);

sys/dev/safexcel/safexcel.c

327

if ((reg & SAFEXCEL_OPT_ADDR_64) == 0)

sys/dev/safexcel/safexcel.c

330

if (((reg & SAFEXCEL_OPT_TGT_ALIGN_MASK) >>

sys/dev/safexcel/safexcel.c

335

(reg & SAFEXCEL_xDR_HDW_MASK) >> SAFEXCEL_xDR_HDW_OFFSET;

sys/dev/safexcel/safexcel.c

338

sc->sc_config.rings = reg & SAFEXCEL_N_RINGS_MASK;

sys/dev/safexcel/safexcel.c

342

sc->sc_config.pes = (reg & pemask) >> SAFEXCEL_N_PES_OFFSET;

sys/dev/sbni/if_sbni.c

134

sbni_inb(struct sbni_softc *sc, enum sbni_reg reg)

sys/dev/sbni/if_sbni.c

139

sc->io_off + reg);

sys/dev/sbni/if_sbni.c

143

sbni_outb(struct sbni_softc *sc, enum sbni_reg reg, u_char value)

sys/dev/sbni/if_sbni.c

148

sc->io_off + reg, value);

sys/dev/scc/scc_bfe.h

48

#define scc_regofs(bas, reg) ((reg) << (bas)->regshft)

sys/dev/scc/scc_bfe.h

50

#define scc_getreg(bas, reg) \

sys/dev/scc/scc_bfe.h

51

bus_space_read_1((bas)->bst, (bas)->bsh, scc_regofs(bas, reg))

sys/dev/scc/scc_bfe.h

52

#define scc_setreg(bas, reg, value) \

sys/dev/scc/scc_bfe.h

53

bus_space_write_1((bas)->bst, (bas)->bsh, scc_regofs(bas, reg), value)

sys/dev/scc/scc_dev_quicc.c

46

#define quicc_read2(bas, reg) \

sys/dev/scc/scc_dev_quicc.c

47

bus_space_read_2((bas)->bst, (bas)->bsh, reg)

sys/dev/scc/scc_dev_quicc.c

48

#define quicc_read4(bas, reg) \

sys/dev/scc/scc_dev_quicc.c

49

bus_space_read_4((bas)->bst, (bas)->bsh, reg)

sys/dev/scc/scc_dev_quicc.c

51

#define quicc_write2(bas, reg, val) \

sys/dev/scc/scc_dev_quicc.c

52

bus_space_write_2((bas)->bst, (bas)->bsh, reg, val)

sys/dev/scc/scc_dev_quicc.c

53

#define quicc_write4(bas, reg, val) \

sys/dev/scc/scc_dev_quicc.c

54

bus_space_write_4((bas)->bst, (bas)->bsh, reg, val)

sys/dev/scc/scc_dev_z8530.c

93

scc_getmreg(struct scc_bas *bas, int ch, int reg)

sys/dev/scc/scc_dev_z8530.c

96

scc_setreg(bas, ch + REG_CTRL, reg);

sys/dev/sdhci/sdhci_fdt_cvitek.c

118

reg = bus_read_4(res, CVI_CV181X_SDHCI_EMMC_CTRL);

sys/dev/sdhci/sdhci_fdt_cvitek.c

119

reg |= EMMC_CTRL_RESET_MASK;

sys/dev/sdhci/sdhci_fdt_cvitek.c

120

bus_write_4(res, CVI_CV181X_SDHCI_EMMC_CTRL, reg);

sys/dev/sdhci/sdhci_fdt_cvitek.c

97

uint32_t reg;

sys/dev/sdhci/sdhci_fsl_fdt.c

1127

uint32_t reg;

sys/dev/sdhci/sdhci_fsl_fdt.c

1131

reg = RD4(sc, SDHCI_FSL_TBCTL);

sys/dev/sdhci/sdhci_fsl_fdt.c

1134

reg |= SDHCI_FSL_TBCTL_TBEN;

sys/dev/sdhci/sdhci_fsl_fdt.c

1136

reg &= ~SDHCI_FSL_TBCTL_TBEN;

sys/dev/sdhci/sdhci_fsl_fdt.c

1138

WR4(sc, SDHCI_FSL_TBCTL, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1145

uint32_t reg;

sys/dev/sdhci/sdhci_fsl_fdt.c

1157

reg = RD4(sc, SDHCI_FSL_TBPTR);

sys/dev/sdhci/sdhci_fsl_fdt.c

1158

reg &= ~SDHCI_FSL_TBPTR_WND_MASK;

sys/dev/sdhci/sdhci_fsl_fdt.c

1159

reg &= ~(SDHCI_FSL_TBPTR_WND_MASK << SDHCI_FSL_TBPTR_WND_START_SHIFT);

sys/dev/sdhci/sdhci_fsl_fdt.c

1160

reg |= wnd_start << SDHCI_FSL_TBPTR_WND_START_SHIFT;

sys/dev/sdhci/sdhci_fsl_fdt.c

1161

reg |= wnd_end;

sys/dev/sdhci/sdhci_fsl_fdt.c

1162

WR4(sc, SDHCI_FSL_TBPTR, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1168

reg = RD4(sc, SDHCI_FSL_AUTOCERR);

sys/dev/sdhci/sdhci_fsl_fdt.c

1169

reg |= SDHCI_FSL_AUTOCERR_EXTN;

sys/dev/sdhci/sdhci_fsl_fdt.c

1170

WR4(sc, SDHCI_FSL_AUTOCERR, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1172

reg |= SDHCI_FSL_AUTOCERR_SMPCLKSEL;

sys/dev/sdhci/sdhci_fsl_fdt.c

1173

WR4(sc, SDHCI_FSL_AUTOCERR, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1175

reg = RD4(sc, SDHCI_FSL_TBCTL);

sys/dev/sdhci/sdhci_fsl_fdt.c

1176

reg &= ~SDHCI_FSL_TBCTL_TB_MODE_MASK;

sys/dev/sdhci/sdhci_fsl_fdt.c

1177

reg |= SDHCI_FSL_TBCTL_MODE_SW;

sys/dev/sdhci/sdhci_fsl_fdt.c

1178

WR4(sc, SDHCI_FSL_TBCTL, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1194

uint32_t clk_divider, reg;

sys/dev/sdhci/sdhci_fsl_fdt.c

1229

reg = RD4(sc, SDHCI_FSL_ESDHC_CTRL);

sys/dev/sdhci/sdhci_fsl_fdt.c

1230

reg |= SDHCI_FSL_ESDHC_CTRL_FAF;

sys/dev/sdhci/sdhci_fsl_fdt.c

1231

WR4(sc, SDHCI_FSL_ESDHC_CTRL, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1247

reg = RD4(sc, SDHCI_FSL_TBCTL);

sys/dev/sdhci/sdhci_fsl_fdt.c

1248

reg &= ~SDHCI_FSL_TBCTL_TB_MODE_MASK;

sys/dev/sdhci/sdhci_fsl_fdt.c

1249

reg |= SDHCI_FSL_TBCTL_TBEN | SDHCI_FSL_TBCTL_MODE_3;

sys/dev/sdhci/sdhci_fsl_fdt.c

1250

WR4(sc, SDHCI_FSL_TBCTL, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1265

reg = RD4(sc, SDHCI_FSL_TBPTR);

sys/dev/sdhci/sdhci_fsl_fdt.c

1266

wnd_start = reg >> SDHCI_FSL_TBPTR_WND_START_SHIFT;

sys/dev/sdhci/sdhci_fsl_fdt.c

1268

wnd_end = reg & SDHCI_FSL_TBPTR_WND_MASK;

sys/dev/sdhci/sdhci_fsl_fdt.c

1297

reg = RD4(sc, SDHCI_FSL_SDTIMINGCTL);

sys/dev/sdhci/sdhci_fsl_fdt.c

1298

reg |= SDHCI_FSL_SDTIMINGCTL_FLW_CTL;

sys/dev/sdhci/sdhci_fsl_fdt.c

1299

WR4(sc, SDHCI_FSL_SDTIMINGCTL, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1338

uint32_t reg;

sys/dev/sdhci/sdhci_fsl_fdt.c

1342

reg = RD4(sc, SDHCI_FSL_TBCTL);

sys/dev/sdhci/sdhci_fsl_fdt.c

1343

if ((reg & SDHCI_FSL_TBCTL_HS400_EN) == 0)

sys/dev/sdhci/sdhci_fsl_fdt.c

1346

reg = RD4(sc, SDHCI_FSL_SDTIMINGCTL);

sys/dev/sdhci/sdhci_fsl_fdt.c

1347

reg &= ~SDHCI_FSL_SDTIMINGCTL_FLW_CTL;

sys/dev/sdhci/sdhci_fsl_fdt.c

1348

WR4(sc, SDHCI_FSL_SDTIMINGCTL, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1350

reg = RD4(sc, SDHCI_FSL_SDCLKCTL);

sys/dev/sdhci/sdhci_fsl_fdt.c

1351

reg &= ~SDHCI_FSL_SDCLKCTL_CMD_CLK_CTL;

sys/dev/sdhci/sdhci_fsl_fdt.c

1352

WR4(sc, SDHCI_FSL_SDCLKCTL, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1361

reg = RD4(sc, SDHCI_FSL_TBCTL);

sys/dev/sdhci/sdhci_fsl_fdt.c

1362

reg &= ~SDHCI_FSL_TBCTL_HS400_EN;

sys/dev/sdhci/sdhci_fsl_fdt.c

1363

WR4(sc, SDHCI_FSL_TBCTL, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1374

reg = RD4(sc, SDHCI_FSL_DLLCFG0);

sys/dev/sdhci/sdhci_fsl_fdt.c

1375

reg &= ~(SDHCI_FSL_DLLCFG0_EN |

sys/dev/sdhci/sdhci_fsl_fdt.c

1377

WR4(sc, SDHCI_FSL_DLLCFG0, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1379

reg = RD4(sc, SDHCI_FSL_TBCTL);

sys/dev/sdhci/sdhci_fsl_fdt.c

1380

reg &= ~SDHCI_FSL_TBCTL_HS400_WND_ADJ;

sys/dev/sdhci/sdhci_fsl_fdt.c

1381

WR4(sc, SDHCI_FSL_TBCTL, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1390

uint32_t reg;

sys/dev/sdhci/sdhci_fsl_fdt.c

1402

reg = RD4(sc, SDHCI_FSL_TBCTL);

sys/dev/sdhci/sdhci_fsl_fdt.c

1403

reg |= SDHCI_FSL_TBCTL_HS400_EN;

sys/dev/sdhci/sdhci_fsl_fdt.c

1404

WR4(sc, SDHCI_FSL_TBCTL, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1405

reg = RD4(sc, SDHCI_FSL_SDCLKCTL);

sys/dev/sdhci/sdhci_fsl_fdt.c

1406

reg |= SDHCI_FSL_SDCLKCTL_CMD_CLK_CTL;

sys/dev/sdhci/sdhci_fsl_fdt.c

1407

WR4(sc, SDHCI_FSL_SDCLKCTL, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1417

reg = RD4(sc, SDHCI_FSL_DLLCFG0);

sys/dev/sdhci/sdhci_fsl_fdt.c

1418

reg |= SDHCI_FSL_DLLCFG0_EN | SDHCI_FSL_DLLCFG0_RESET |

sys/dev/sdhci/sdhci_fsl_fdt.c

1420

WR4(sc, SDHCI_FSL_DLLCFG0, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1427

reg &= ~SDHCI_FSL_DLLCFG0_RESET;

sys/dev/sdhci/sdhci_fsl_fdt.c

1428

WR4(sc, SDHCI_FSL_DLLCFG0, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1436

reg = RD4(sc, SDHCI_FSL_TBCTL);

sys/dev/sdhci/sdhci_fsl_fdt.c

1437

reg |= SDHCI_FSL_TBCTL_HS400_WND_ADJ;

sys/dev/sdhci/sdhci_fsl_fdt.c

1438

WR4(sc, SDHCI_FSL_TBCTL, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1448

reg = RD4(sc, SDHCI_FSL_ESDHC_CTRL);

sys/dev/sdhci/sdhci_fsl_fdt.c

1449

reg |= SDHCI_FSL_ESDHC_CTRL_FAF;

sys/dev/sdhci/sdhci_fsl_fdt.c

1450

WR4(sc, SDHCI_FSL_ESDHC_CTRL, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

1473

uint32_t mode, reg;

sys/dev/sdhci/sdhci_fsl_fdt.c

1497

reg = RD4(sc, SDHCI_FSL_AUTOCERR);

sys/dev/sdhci/sdhci_fsl_fdt.c

1498

reg &= ~SDHCI_FSL_AUTOCERR_UHMS;

sys/dev/sdhci/sdhci_fsl_fdt.c

1512

reg |= mode << SDHCI_FSL_AUTOCERR_UHMS_SHIFT;

sys/dev/sdhci/sdhci_fsl_fdt.c

1513

WR4(sc, SDHCI_FSL_AUTOCERR, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

645

uint32_t reg;

sys/dev/sdhci/sdhci_fsl_fdt.c

660

reg = SYSCON_READ_4(syscon, SCFG_SDHCIOVSELCR);

sys/dev/sdhci/sdhci_fsl_fdt.c

661

reg &= ~SCFG_SDHCIOVSELCR_VSELVAL_MASK;

sys/dev/sdhci/sdhci_fsl_fdt.c

662

reg |= SCFG_SDHCIOVSELCR_TGLEN;

sys/dev/sdhci/sdhci_fsl_fdt.c

666

reg |= SCFG_SDHCIOVSELCR_VSELVAL_1_8;

sys/dev/sdhci/sdhci_fsl_fdt.c

667

SYSCON_WRITE_4(syscon, SCFG_SDHCIOVSELCR, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

671

reg = SYSCON_READ_4(syscon, SCFG_SDHCIOVSELCR);

sys/dev/sdhci/sdhci_fsl_fdt.c

672

reg |= SCFG_SDHCIOVSELCR_VS;

sys/dev/sdhci/sdhci_fsl_fdt.c

675

reg |= SCFG_SDHCIOVSELCR_VSELVAL_3_3;

sys/dev/sdhci/sdhci_fsl_fdt.c

676

SYSCON_WRITE_4(syscon, SCFG_SDHCIOVSELCR, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

680

reg = SYSCON_READ_4(syscon, SCFG_SDHCIOVSELCR);

sys/dev/sdhci/sdhci_fsl_fdt.c

681

reg &= ~SCFG_SDHCIOVSELCR_VS;

sys/dev/sdhci/sdhci_fsl_fdt.c

688

SYSCON_WRITE_4(syscon, SCFG_SDHCIOVSELCR, reg);

sys/dev/sdhci/sdhci_fsl_fdt.c

846

uint32_t reg, uint32_t mask, int value)

sys/dev/sdhci/sdhci_fsl_fdt.c

852

while ((RD4(sc, reg) & mask) != value) {

sys/dev/sdhci/sdhci_xenon.c

195

uint32_t reg;

sys/dev/sdhci/sdhci_xenon.c

198

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);

sys/dev/sdhci/sdhci_xenon.c

199

reg |= XENON_SAMPL_INV_QSP_PHASE_SELECT;

sys/dev/sdhci/sdhci_xenon.c

206

reg |= XENON_TIMING_ADJUST_SLOW_MODE;

sys/dev/sdhci/sdhci_xenon.c

209

reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;

sys/dev/sdhci/sdhci_xenon.c

212

reg |= XENON_TIMING_ADJUST_SLOW_MODE;

sys/dev/sdhci/sdhci_xenon.c

213

bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);

sys/dev/sdhci/sdhci_xenon.c

215

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);

sys/dev/sdhci/sdhci_xenon.c

216

reg |= XENON_PHY_INITIALIZATION;

sys/dev/sdhci/sdhci_xenon.c

217

bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);

sys/dev/sdhci/sdhci_xenon.c

223

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);

sys/dev/sdhci/sdhci_xenon.c

224

if ((reg & XENON_PHY_INITIALIZATION) == 0)

sys/dev/sdhci/sdhci_xenon.c

240

uint32_t reg;

sys/dev/sdhci/sdhci_xenon.c

244

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL);

sys/dev/sdhci/sdhci_xenon.c

245

reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN |

sys/dev/sdhci/sdhci_xenon.c

248

reg |= XENON_FC_ALL_CMOS_RECEIVER;

sys/dev/sdhci/sdhci_xenon.c

249

bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL, reg);

sys/dev/sdhci/sdhci_xenon.c

252

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1);

sys/dev/sdhci/sdhci_xenon.c

253

reg |= (XENON_EMMC_FC_CMD_PU | XENON_EMMC_FC_DQ_PU);

sys/dev/sdhci/sdhci_xenon.c

254

reg &= ~(XENON_EMMC_FC_CMD_PD | XENON_EMMC_FC_DQ_PD);

sys/dev/sdhci/sdhci_xenon.c

255

bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg);

sys/dev/sdhci/sdhci_xenon.c

261

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST);

sys/dev/sdhci/sdhci_xenon.c

262

reg &= ~XENON_TIMING_ADJUST_SDIO_MODE;

sys/dev/sdhci/sdhci_xenon.c

263

bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg);

sys/dev/sdhci/sdhci_xenon.c

270

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2);

sys/dev/sdhci/sdhci_xenon.c

271

reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK);

sys/dev/sdhci/sdhci_xenon.c

272

reg |= ((sc->znr << XENON_ZNR_SHIFT) | sc->zpr);

sys/dev/sdhci/sdhci_xenon.c

273

bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2, reg);

sys/dev/sdhci/sdhci_xenon.c

276

reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL);

sys/dev/sdhci/sdhci_xenon.c

277

reg &= ~SDHCI_CLOCK_CARD_EN;

sys/dev/sdhci/sdhci_xenon.c

278

bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg);

sys/dev/sdhci/sdhci_xenon.c

280

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL);

sys/dev/sdhci/sdhci_xenon.c

283

reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |

sys/dev/sdhci/sdhci_xenon.c

285

reg &= ~XENON_DQ_ASYNC_MODE;

sys/dev/sdhci/sdhci_xenon.c

289

reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |

sys/dev/sdhci/sdhci_xenon.c

293

reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |

sys/dev/sdhci/sdhci_xenon.c

295

reg |= XENON_DQ_ASYNC_MODE;

sys/dev/sdhci/sdhci_xenon.c

297

bus_write_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL, reg);

sys/dev/sdhci/sdhci_xenon.c

300

reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL);

sys/dev/sdhci/sdhci_xenon.c

301

reg |= SDHCI_CLOCK_CARD_EN;

sys/dev/sdhci/sdhci_xenon.c

302

bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg);

sys/dev/sdhci/sdhci_xenon.c

309

reg = bus_read_4(sc->mem_res, XENON_SLOT_EMMC_CTRL);

sys/dev/sdhci/sdhci_xenon.c

310

reg &= ~(XENON_ENABLE_DATA_STROBE | XENON_ENABLE_RESP_STROBE);

sys/dev/sdhci/sdhci_xenon.c

311

bus_write_4(sc->mem_res, XENON_SLOT_EMMC_CTRL, reg);

sys/dev/sdhci/sdhci_xenon.c

314

reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1);

sys/dev/sdhci/sdhci_xenon.c

315

reg &= ~(XENON_EMMC_FC_QSP_PD | XENON_EMMC_FC_QSP_PU);

sys/dev/sdhci/sdhci_xenon.c

316

bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg);

sys/dev/sdhci/sdhci_xenon.c

329

uint32_t reg;

sys/dev/sdhci/sdhci_xenon.c

368

reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);

sys/dev/sdhci/sdhci_xenon.c

369

reg |= 1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id);

sys/dev/sdhci/sdhci_xenon.c

370

bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);

sys/dev/sdhci/sdhci_xenon.c

497

uint32_t reg;

sys/dev/sdhci/sdhci_xenon.c

547

reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);

sys/dev/sdhci/sdhci_xenon.c

548

reg |= XENON_AUTO_CLKGATE_DISABLE;

sys/dev/sdhci/sdhci_xenon.c

549

bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);

sys/dev/sdhci/sdhci_xenon.c

552

reg |= (1 << sc->slot_id);

sys/dev/sdhci/sdhci_xenon.c

553

bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);

sys/dev/sdhci/sdhci_xenon.c

556

reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL);

sys/dev/sdhci/sdhci_xenon.c

557

reg |= (1 << sc->slot_id);

sys/dev/sdhci/sdhci_xenon.c

558

bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg);

sys/dev/sdhci/sdhci_xenon.c

561

reg &= ~XENON_AUTO_CLKGATE_DISABLE;

sys/dev/sdhci/sdhci_xenon.c

562

bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);

sys/dev/sdhci/sdhci_xenon.c

565

reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL);

sys/dev/sdhci/sdhci_xenon.c

566

reg &= ~(1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id));

sys/dev/sdhci/sdhci_xenon.c

567

bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg);

sys/dev/sdhci/sdhci_xenon.c

570

reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL);

sys/dev/sdhci/sdhci_xenon.c

571

reg |= XENON_MASK_CMD_CONFLICT_ERR;

sys/dev/sdhci/sdhci_xenon.c

572

bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg);

sys/dev/sec/sec.c

644

uint64_t reg;

sys/dev/sec/sec.c

647

reg = SEC_READ(sc, SEC_CHAN_CCR(channel));

sys/dev/sec/sec.c

648

SEC_WRITE(sc, SEC_CHAN_CCR(channel), reg | bit);

sys/dev/sec/sec.c

662

reg = SEC_CHAN_CCR_CDIE | SEC_CHAN_CCR_NT | SEC_CHAN_CCR_BS;

sys/dev/sec/sec.c

666

reg |= SEC_CHAN_CCR_CDWE;

sys/dev/sec/sec.c

669

reg |= SEC_CHAN_CCR_AWSE | SEC_CHAN_CCR_WGN;

sys/dev/sec/sec.c

673

SEC_WRITE(sc, SEC_CHAN_CCR(channel), reg);

sys/dev/sec/sec.c

682

uint64_t reg;

sys/dev/sec/sec.c

702

reg = SEC_INT_ITO;

sys/dev/sec/sec.c

704

reg |= SEC_INT_CH_DN(i) | SEC_INT_CH_ERR(i);

sys/dev/sec/sec.c

706

SEC_WRITE(sc, SEC_IER, reg);

sys/dev/sec/sec.c

926

uint64_t reg;

sys/dev/sec/sec.c

931

reg = SEC_READ(sc, SEC_EUASR);

sys/dev/sec/sec.c

935

channel = SEC_EUASR_AFEU(reg);

sys/dev/sec/sec.c

938

channel = SEC_EUASR_DEU(reg);

sys/dev/sec/sec.c

942

channel = SEC_EUASR_MDEU(reg);

sys/dev/sec/sec.c

945

channel = SEC_EUASR_RNGU(reg);

sys/dev/sec/sec.c

948

channel = SEC_EUASR_PKEU(reg);

sys/dev/sec/sec.c

951

channel = SEC_EUASR_AESU(reg);

sys/dev/sec/sec.c

954

channel = SEC_EUASR_KEU(reg);

sys/dev/sec/sec.c

957

channel = SEC_EUASR_CRCU(reg);

sys/dev/sec/sec.c

968

uint64_t reg;

sys/dev/sec/sec.c

976

reg = SEC_READ(sc, SEC_CHAN_CSR(channel));

sys/dev/sec/sec.c

978

if ((reg & sc->sc_channel_idle_mask) == 0) {

sys/dev/sec/sec.c

990

reg = SEC_READ(sc, SEC_CHAN_CSR(channel));

sys/dev/sec/sec.c

994

fflvl = (reg >> SEC_CHAN_CSR2_FFLVL_S) & SEC_CHAN_CSR2_FFLVL_M;

sys/dev/sec/sec.c

997

fflvl = (reg >> SEC_CHAN_CSR3_FFLVL_S) & SEC_CHAN_CSR3_FFLVL_M;

sys/dev/sec/sec.h

221

#define SEC_READ(sc, reg) \

sys/dev/sec/sec.h

222

bus_space_read_8((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg))

sys/dev/sec/sec.h

223

#define SEC_WRITE(sc, reg, val) \

sys/dev/sec/sec.h

224

bus_space_write_8((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg), (val))

sys/dev/sfxge/common/siena_nic.c

625

efx_oword_t reg;

sys/dev/sfxge/common/siena_nic.c

642

reg = original;

sys/dev/sfxge/common/siena_nic.c

643

EFX_AND_OWORD(reg, rsp->mask);

sys/dev/sfxge/common/siena_nic.c

644

EFX_SET_OWORD_BIT(reg, bit);

sys/dev/sfxge/common/siena_nic.c

646

EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &reg,

sys/dev/sfxge/common/siena_nic.c

652

if (memcmp(&reg, &buf, sizeof (reg))) {

sys/dev/sfxge/common/siena_nic.c

658

EFX_OR_OWORD(reg, rsp->mask);

sys/dev/sfxge/common/siena_nic.c

659

EFX_CLEAR_OWORD_BIT(reg, bit);

sys/dev/sfxge/common/siena_nic.c

661

EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &reg,

sys/dev/sfxge/common/siena_nic.c

667

if (memcmp(&reg, &buf, sizeof (reg))) {

sys/dev/sfxge/common/siena_nic.c

704

efx_oword_t reg;

sys/dev/sfxge/common/siena_nic.c

715

func(2 * index + 0, B_FALSE, &reg.eo_qword[0]);

sys/dev/sfxge/common/siena_nic.c

716

func(2 * index + 1, B_FALSE, &reg.eo_qword[1]);

sys/dev/sfxge/common/siena_nic.c

717

EFX_AND_OWORD(reg, rsp->mask);

sys/dev/sfxge/common/siena_nic.c

718

EFSYS_BAR_WRITEO(enp->en_esbp, address, &reg, B_TRUE);

sys/dev/sfxge/common/siena_nic.c

726

func(2 * index + 0, B_FALSE, &reg.eo_qword[0]);

sys/dev/sfxge/common/siena_nic.c

727

func(2 * index + 1, B_FALSE, &reg.eo_qword[1]);

sys/dev/sfxge/common/siena_nic.c

728

EFX_AND_OWORD(reg, rsp->mask);

sys/dev/sfxge/common/siena_nic.c

730

if (memcmp(&reg, &buf, sizeof (reg))) {

sys/dev/sge/if_sge.c

180

#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sge_res, reg, val)

sys/dev/sge/if_sge.c

181

#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->sge_res, reg, val)

sys/dev/sge/if_sge.c

182

#define CSR_WRITE_1(cs, reg, val) bus_write_1(sc->sge_res, reg, val)

sys/dev/sge/if_sge.c

184

#define CSR_READ_4(sc, reg) bus_read_4(sc->sge_res, reg)

sys/dev/sge/if_sge.c

185

#define CSR_READ_2(sc, reg) bus_read_2(sc->sge_res, reg)

sys/dev/sge/if_sge.c

186

#define CSR_READ_1(sc, reg) bus_read_1(sc->sge_res, reg)

sys/dev/sge/if_sge.c

276

uint8_t reg;

sys/dev/sge/if_sge.c

307

reg = pci_read_config(dev, 0x48, 1);

sys/dev/sge/if_sge.c

308

pci_write_config(dev, 0x48, reg & ~0x02, 1);

sys/dev/sge/if_sge.c

320

pci_write_config(dev, 0x48, reg, 1);

sys/dev/sge/if_sge.c

329

sge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/sge/if_sge.c

337

(reg << GMI_REG_SHIFT) | GMI_OP_RD | GMI_REQ);

sys/dev/sge/if_sge.c

346

device_printf(sc->sge_dev, "PHY read timeout : %d\n", reg);

sys/dev/sge/if_sge.c

353

sge_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/sge/if_sge.c

361

(reg << GMI_REG_SHIFT) | (data << GMI_DATA_SHIFT) |

sys/dev/sge/if_sge.c

371

device_printf(sc->sge_dev, "PHY write timeout : %d\n", reg);

sys/dev/sis/if_sis.c

118

#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val)

sys/dev/sis/if_sis.c

120

#define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg)

sys/dev/sis/if_sis.c

122

#define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg)

sys/dev/sis/if_sis.c

124

#define CSR_BARRIER(sc, reg, length, flags) \

sys/dev/sis/if_sis.c

125

bus_barrier(sc->sis_res[0], reg, length, flags)

sys/dev/sis/if_sis.c

194

#define SIS_SETBIT(sc, reg, x) \

sys/dev/sis/if_sis.c

195

CSR_WRITE_4(sc, reg, \

sys/dev/sis/if_sis.c

196

CSR_READ_4(sc, reg) | (x))

sys/dev/sis/if_sis.c

198

#define SIS_CLRBIT(sc, reg, x) \

sys/dev/sis/if_sis.c

199

CSR_WRITE_4(sc, reg, \

sys/dev/sis/if_sis.c

200

CSR_READ_4(sc, reg) & ~(x))

sys/dev/sis/if_sis.c

387

uint8_t reg;

sys/dev/sis/if_sis.c

394

reg = pci_read_config(bridge, 0x48, 1);

sys/dev/sis/if_sis.c

395

pci_write_config(bridge, 0x48, reg|0x40, 1);

sys/dev/sis/if_sis.c

407

pci_write_config(bridge, 0x48, reg & ~0x40, 1);

sys/dev/sis/if_sis.c

468

sis_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/sis/if_sis.c

489

return CSR_READ_4(sc, NS_BMCR + (reg * 4));

sys/dev/sis/if_sis.c

505

(phy << 11) | (reg << 6) | SIS_PHYOP_READ);

sys/dev/sis/if_sis.c

527

reg));

sys/dev/sis/if_sis.c

531

sis_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/sis/if_sis.c

540

CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);

sys/dev/sis/if_sis.c

557

(reg << 6) | SIS_PHYOP_WRITE);

sys/dev/sis/if_sis.c

569

mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, reg,

sys/dev/sis/if_sis.c

580

uint32_t reg;

sys/dev/sis/if_sis.c

643

reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;

sys/dev/sis/if_sis.c

644

CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);

sys/dev/sis/if_sis.c

646

reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;

sys/dev/sis/if_sis.c

647

if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {

sys/dev/sis/if_sis.c

649

"Applying short cable fix (reg=%x)\n", reg);

sys/dev/sk/if_sk.c

3121

while(bhack[i].reg) {

sys/dev/sk/if_sk.c

3123

bhack[i].reg, bhack[i].val);

sys/dev/sk/if_sk.c

3225

u_int16_t reg;

sys/dev/sk/if_sk.c

3281

reg = SK_YU_READ_2(sc_if, YUKON_PAR);

sys/dev/sk/if_sk.c

3284

reg |= YU_PAR_MIB_CLR;

sys/dev/sk/if_sk.c

3285

SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);

sys/dev/sk/if_sk.c

3288

reg &= ~YU_PAR_MIB_CLR;

sys/dev/sk/if_sk.c

3289

SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);

sys/dev/sk/if_sk.c

3299

reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);

sys/dev/sk/if_sk.c

3301

reg |= YU_SMR_MFL_JUMBO;

sys/dev/sk/if_sk.c

3302

SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);

sys/dev/sk/if_sk.c

3372

u_int16_t reg;

sys/dev/sk/if_sk.c

344

#define SK_SETBIT(sc, reg, x) \

sys/dev/sk/if_sk.c

345

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)

sys/dev/sk/if_sk.c

347

#define SK_CLRBIT(sc, reg, x) \

sys/dev/sk/if_sk.c

348

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)

sys/dev/sk/if_sk.c

350

#define SK_WIN_SETBIT_4(sc, reg, x) \

sys/dev/sk/if_sk.c

351

sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)

sys/dev/sk/if_sk.c

353

#define SK_WIN_CLRBIT_4(sc, reg, x) \

sys/dev/sk/if_sk.c

3535

reg = SK_YU_READ_2(sc_if, YUKON_GPCR);

sys/dev/sk/if_sk.c

3536

reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;

sys/dev/sk/if_sk.c

3539

reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);

sys/dev/sk/if_sk.c

354

sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)

sys/dev/sk/if_sk.c

3541

SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);

sys/dev/sk/if_sk.c

356

#define SK_WIN_SETBIT_2(sc, reg, x) \

sys/dev/sk/if_sk.c

357

sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)

sys/dev/sk/if_sk.c

359

#define SK_WIN_CLRBIT_2(sc, reg, x) \

sys/dev/sk/if_sk.c

360

sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)

sys/dev/sk/if_sk.c

363

sk_win_read_4(struct sk_softc *sc, int reg)

sys/dev/sk/if_sk.c

366

CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));

sys/dev/sk/if_sk.c

367

return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));

sys/dev/sk/if_sk.c

369

return(CSR_READ_4(sc, reg));

sys/dev/sk/if_sk.c

374

sk_win_read_2(struct sk_softc *sc, int reg)

sys/dev/sk/if_sk.c

377

CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));

sys/dev/sk/if_sk.c

378

return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));

sys/dev/sk/if_sk.c

380

return(CSR_READ_2(sc, reg));

sys/dev/sk/if_sk.c

385

sk_win_read_1(struct sk_softc *sc, int reg)

sys/dev/sk/if_sk.c

388

CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));

sys/dev/sk/if_sk.c

389

return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));

sys/dev/sk/if_sk.c

391

return(CSR_READ_1(sc, reg));

sys/dev/sk/if_sk.c

396

sk_win_write_4(struct sk_softc *sc, int reg, u_int32_t val)

sys/dev/sk/if_sk.c

399

CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));

sys/dev/sk/if_sk.c

400

CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);

sys/dev/sk/if_sk.c

402

CSR_WRITE_4(sc, reg, val);

sys/dev/sk/if_sk.c

408

sk_win_write_2(struct sk_softc *sc, int reg, u_int32_t val)

sys/dev/sk/if_sk.c

411

CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));

sys/dev/sk/if_sk.c

412

CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);

sys/dev/sk/if_sk.c

414

CSR_WRITE_2(sc, reg, val);

sys/dev/sk/if_sk.c

420

sk_win_write_1(struct sk_softc *sc, int reg, u_int32_t val)

sys/dev/sk/if_sk.c

423

CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));

sys/dev/sk/if_sk.c

424

CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);

sys/dev/sk/if_sk.c

426

CSR_WRITE_1(sc, reg, val);

sys/dev/sk/if_sk.c

432

sk_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/sk/if_sk.c

442

v = sk_xmac_miibus_readreg(sc_if, phy, reg);

sys/dev/sk/if_sk.c

447

v = sk_marv_miibus_readreg(sc_if, phy, reg);

sys/dev/sk/if_sk.c

459

sk_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/sk/if_sk.c

469

v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);

sys/dev/sk/if_sk.c

474

v = sk_marv_miibus_writereg(sc_if, phy, reg, val);

sys/dev/sk/if_sk.c

509

sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)

sys/dev/sk/if_sk.c

513

SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));

sys/dev/sk/if_sk.c

535

sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)

sys/dev/sk/if_sk.c

539

SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));

sys/dev/sk/if_sk.c

583

sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)

sys/dev/sk/if_sk.c

594

YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);

sys/dev/sk/if_sk.c

614

sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)

sys/dev/sk/if_sk.c

620

YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);

sys/dev/sk/if_skreg.h

1161

#define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \

sys/dev/sk/if_skreg.h

1165

#define SK_XM_READ_4(sc, reg) \

sys/dev/sk/if_skreg.h

1167

SK_XMAC_REG(sc, reg)) & 0xFFFF) | \

sys/dev/sk/if_skreg.h

1169

SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16))

sys/dev/sk/if_skreg.h

1171

#define SK_XM_WRITE_4(sc, reg, val) \

sys/dev/sk/if_skreg.h

1172

sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \

sys/dev/sk/if_skreg.h

1174

sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \

sys/dev/sk/if_skreg.h

1177

#define SK_XM_READ_4(sc, reg) \

sys/dev/sk/if_skreg.h

1178

sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg))

sys/dev/sk/if_skreg.h

1180

#define SK_XM_WRITE_4(sc, reg, val) \

sys/dev/sk/if_skreg.h

1181

sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val))

sys/dev/sk/if_skreg.h

1184

#define SK_XM_READ_2(sc, reg) \

sys/dev/sk/if_skreg.h

1185

sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg))

sys/dev/sk/if_skreg.h

1187

#define SK_XM_WRITE_2(sc, reg, val) \

sys/dev/sk/if_skreg.h

1188

sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val)

sys/dev/sk/if_skreg.h

1190

#define SK_XM_SETBIT_4(sc, reg, x) \

sys/dev/sk/if_skreg.h

1191

SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x))

sys/dev/sk/if_skreg.h

1193

#define SK_XM_CLRBIT_4(sc, reg, x) \

sys/dev/sk/if_skreg.h

1194

SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x))

sys/dev/sk/if_skreg.h

1196

#define SK_XM_SETBIT_2(sc, reg, x) \

sys/dev/sk/if_skreg.h

1197

SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x))

sys/dev/sk/if_skreg.h

1199

#define SK_XM_CLRBIT_2(sc, reg, x) \

sys/dev/sk/if_skreg.h

1200

SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x))

sys/dev/sk/if_skreg.h

1203

#define SK_YU_REG(sc, reg) \

sys/dev/sk/if_skreg.h

1204

((reg) + SK_MARV1_BASE + \

sys/dev/sk/if_skreg.h

1207

#define SK_YU_READ_4(sc, reg) \

sys/dev/sk/if_skreg.h

1208

sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg)))

sys/dev/sk/if_skreg.h

1210

#define SK_YU_READ_2(sc, reg) \

sys/dev/sk/if_skreg.h

1211

sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg)))

sys/dev/sk/if_skreg.h

1213

#define SK_YU_WRITE_4(sc, reg, val) \

sys/dev/sk/if_skreg.h

1214

sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))

sys/dev/sk/if_skreg.h

1216

#define SK_YU_WRITE_2(sc, reg, val) \

sys/dev/sk/if_skreg.h

1217

sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))

sys/dev/sk/if_skreg.h

1219

#define SK_YU_SETBIT_4(sc, reg, x) \

sys/dev/sk/if_skreg.h

1220

SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x))

sys/dev/sk/if_skreg.h

1222

#define SK_YU_CLRBIT_4(sc, reg, x) \

sys/dev/sk/if_skreg.h

1223

SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x))

sys/dev/sk/if_skreg.h

1225

#define SK_YU_SETBIT_2(sc, reg, x) \

sys/dev/sk/if_skreg.h

1226

SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x))

sys/dev/sk/if_skreg.h

1228

#define SK_YU_CLRBIT_2(sc, reg, x) \

sys/dev/sk/if_skreg.h

1229

SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x))

sys/dev/sk/if_skreg.h

1274

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/sk/if_skreg.h

1275

bus_write_4((sc)->sk_res[0], (reg), (val))

sys/dev/sk/if_skreg.h

1276

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/sk/if_skreg.h

1277

bus_write_2((sc)->sk_res[0], (reg), (val))

sys/dev/sk/if_skreg.h

1278

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/sk/if_skreg.h

1279

bus_write_1((sc)->sk_res[0], (reg), (val))

sys/dev/sk/if_skreg.h

1281

#define CSR_READ_4(sc, reg) \

sys/dev/sk/if_skreg.h

1282

bus_read_4((sc)->sk_res[0], (reg))

sys/dev/sk/if_skreg.h

1283

#define CSR_READ_2(sc, reg) \

sys/dev/sk/if_skreg.h

1284

bus_read_2((sc)->sk_res[0], (reg))

sys/dev/sk/if_skreg.h

1285

#define CSR_READ_1(sc, reg) \

sys/dev/sk/if_skreg.h

1286

bus_read_1((sc)->sk_res[0], (reg))

sys/dev/sk/if_skreg.h

1429

int reg;

sys/dev/sk/if_skreg.h

144

#define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN)

sys/dev/sk/if_skreg.h

147

#define SK_REG(reg) ((reg) & SK_REG_MASK)

sys/dev/sk/if_skreg.h

174

#define SK_IF_READ_4(sc_if, skip, reg) \

sys/dev/sk/if_skreg.h

175

sk_win_read_4(sc_if->sk_softc, reg + \

sys/dev/sk/if_skreg.h

177

#define SK_IF_READ_2(sc_if, skip, reg) \

sys/dev/sk/if_skreg.h

178

sk_win_read_2(sc_if->sk_softc, reg + \

sys/dev/sk/if_skreg.h

180

#define SK_IF_READ_1(sc_if, skip, reg) \

sys/dev/sk/if_skreg.h

181

sk_win_read_1(sc_if->sk_softc, reg + \

sys/dev/sk/if_skreg.h

184

#define SK_IF_WRITE_4(sc_if, skip, reg, val) \

sys/dev/sk/if_skreg.h

186

reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)

sys/dev/sk/if_skreg.h

187

#define SK_IF_WRITE_2(sc_if, skip, reg, val) \

sys/dev/sk/if_skreg.h

189

reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)

sys/dev/sk/if_skreg.h

190

#define SK_IF_WRITE_1(sc_if, skip, reg, val) \

sys/dev/sk/if_skreg.h

192

reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)

sys/dev/sk/if_skreg.h

594

#define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE)

sys/dev/smc/if_smc.c

1003

smc_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/smc/if_smc.c

1014

val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg);

sys/dev/smc/if_smc.c

1021

smc_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/smc/if_smc.c

1031

mii_bitbang_writereg(dev, &smc_mii_bitbang_ops, phy, reg, data);

sys/dev/smc/if_smc.c

227

struct resource *reg;

sys/dev/smc/if_smc.c

237

reg = bus_alloc_resource_anywhere(dev, type, &rid, 16, RF_ACTIVE);

sys/dev/smc/if_smc.c

238

if (reg == NULL) {

sys/dev/smc/if_smc.c

246

val = bus_read_2(reg, BSR);

sys/dev/smc/if_smc.c

258

bus_write_2(reg, BSR, 0);

sys/dev/smc/if_smc.c

259

val = bus_read_2(reg, BSR);

sys/dev/smc/if_smc.c

270

bus_write_2(reg, BSR, 1);

sys/dev/smc/if_smc.c

271

val = bus_read_2(reg, BAR);

sys/dev/smc/if_smc.c

273

if (rman_get_start(reg) != val) {

sys/dev/smc/if_smc.c

277

rman_get_start(reg));

sys/dev/smc/if_smc.c

284

bus_write_2(reg, BSR, 3);

sys/dev/smc/if_smc.c

285

val = bus_read_2(reg, REV);

sys/dev/smc/if_smc.c

297

bus_release_resource(dev, type, rid, reg);

sys/dev/sound/dummy.c

305

dummy_mpu_read(struct mpu401 *arg, void *sc, int reg)

sys/dev/sound/dummy.c

311

dummy_mpu_write(struct mpu401 *arg, void *sc, int reg, unsigned char b)

sys/dev/sound/macio/aoa.c

235

dma->reg = sc->sc_odma;

sys/dev/sound/macio/aoa.c

239

err = dbdma_allocate_channel(dma->reg, 0, bus_get_dma_tag(sc->sc_dev),

sys/dev/sound/macio/aoa.c

58

struct resource *reg; /* DBDMA registers */

sys/dev/sound/macio/davbus.c

181

bus_read_4(d->reg, DAVBUS_CODEC_STATUS)));

sys/dev/sound/macio/davbus.c

203

burgundy_write_locked(struct davbus_softc *d, u_int reg, u_int val)

sys/dev/sound/macio/davbus.c

207

size = (reg & 0x00FF0000) >> 16;

sys/dev/sound/macio/davbus.c

208

addr = (reg & 0x0000FF00) >> 8;

sys/dev/sound/macio/davbus.c

209

offset = reg & 0xFF;

sys/dev/sound/macio/davbus.c

217

bus_write_4(d->reg, DAVBUS_CODEC_CTRL, data);

sys/dev/sound/macio/davbus.c

219

while (bus_read_4(d->reg, DAVBUS_CODEC_CTRL) &

sys/dev/sound/macio/davbus.c

348

bus_read_4(d->reg, DAVBUS_CODEC_STATUS)));

sys/dev/sound/macio/davbus.c

375

screamer_write_locked(struct davbus_softc *d, u_int reg, u_int val)

sys/dev/sound/macio/davbus.c

381

while (bus_read_4(d->reg, DAVBUS_CODEC_CTRL) & DAVBUS_CODEC_BUSY)

sys/dev/sound/macio/davbus.c

384

x = reg;

sys/dev/sound/macio/davbus.c

387

bus_write_4(d->reg, DAVBUS_CODEC_CTRL, x);

sys/dev/sound/macio/davbus.c

389

while (bus_read_4(d->reg, DAVBUS_CODEC_CTRL) & DAVBUS_CODEC_BUSY)

sys/dev/sound/macio/davbus.c

509

sc->reg = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);

sys/dev/sound/macio/davbus.c

510

if (sc->reg == NULL)

sys/dev/sound/macio/davbus.c

557

bus_write_4(sc->reg, DAVBUS_SOUND_CTRL, DAVBUS_INPUT_SUBFRAME0 |

sys/dev/sound/macio/davbus.c

578

u_int reg, status, mask;

sys/dev/sound/macio/davbus.c

582

reg = bus_read_4(d->reg, DAVBUS_SOUND_CTRL);

sys/dev/sound/macio/davbus.c

583

if (reg & DAVBUS_PORTCHG) {

sys/dev/sound/macio/davbus.c

585

status = bus_read_4(d->reg, DAVBUS_CODEC_STATUS);

sys/dev/sound/macio/davbus.c

593

bus_write_4(d->reg, DAVBUS_SOUND_CTRL, reg);

sys/dev/sound/macio/davbus.c

63

struct resource *reg;

sys/dev/sound/macio/i2s.c

209

sc->reg = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);

sys/dev/sound/macio/i2s.c

210

if (sc->reg == NULL)

sys/dev/sound/macio/i2s.c

446

u_int reg = 0, x, wordformat;

sys/dev/sound/macio/i2s.c

466

reg = clksrc[i].cs_reg;

sys/dev/sound/macio/i2s.c

471

if (reg == 0)

sys/dev/sound/macio/i2s.c

489

reg |= (x << 24) & MCLK_DIV_MASK;

sys/dev/sound/macio/i2s.c

502

reg |= (x << 20) & SCLK_DIV_MASK;

sys/dev/sound/macio/i2s.c

508

reg |= SCLK_MASTER;

sys/dev/sound/macio/i2s.c

512

reg |= SERIAL_64x;

sys/dev/sound/macio/i2s.c

515

reg |= SERIAL_32x;

sys/dev/sound/macio/i2s.c

533

x = bus_read_4(sc->reg, I2S_WORDSIZE);

sys/dev/sound/macio/i2s.c

535

bus_write_4(sc->reg, I2S_WORDSIZE, wordformat);

sys/dev/sound/macio/i2s.c

537

x = bus_read_4(sc->reg, I2S_FORMAT);

sys/dev/sound/macio/i2s.c

538

if (x != reg) {

sys/dev/sound/macio/i2s.c

568

bus_space_write_4(sc->sc_tag, sc->sc_bsh, I2S_FORMAT, reg);

sys/dev/sound/macio/i2s.c

610

u_int reg;

sys/dev/sound/macio/i2s.c

615

reg = GPIO_DDR_OUTPUT;

sys/dev/sound/macio/i2s.c

617

reg |= GPIO_DATA;

sys/dev/sound/macio/i2s.c

619

macgpio_write(sc->dev, reg);

sys/dev/sound/macio/i2s.c

89

struct resource *reg;

sys/dev/sound/macio/onyx.c

169

onyx_write(struct onyx_softc *sc, uint8_t reg, const uint8_t value)

sys/dev/sound/macio/onyx.c

180

buf[0] = reg;

sys/dev/sound/macio/snapper.c

321

snapper_write(struct snapper_softc *sc, uint8_t reg, const void *data)

sys/dev/sound/macio/snapper.c

330

KASSERT(reg < sizeof(snapper_regsize), ("bad reg"));

sys/dev/sound/macio/snapper.c

331

size = snapper_regsize[reg];

sys/dev/sound/macio/snapper.c

333

buf[0] = reg;

sys/dev/sound/macio/snapper.c

442

u_char reg[6];

sys/dev/sound/macio/snapper.c

456

reg[0] = (l & 0xff0000) >> 16;

sys/dev/sound/macio/snapper.c

457

reg[1] = (l & 0x00ff00) >> 8;

sys/dev/sound/macio/snapper.c

458

reg[2] = l & 0x0000ff;

sys/dev/sound/macio/snapper.c

459

reg[3] = (r & 0xff0000) >> 16;

sys/dev/sound/macio/snapper.c

460

reg[4] = (r & 0x00ff00) >> 8;

sys/dev/sound/macio/snapper.c

461

reg[5] = r & 0x0000ff;

sys/dev/sound/macio/snapper.c

473

snapper_write(sc, SNAPPER_VOLUME, reg);

sys/dev/sound/macio/tumbler.c

282

tumbler_write(struct tumbler_softc *sc, uint8_t reg, const void *data)

sys/dev/sound/macio/tumbler.c

291

KASSERT(reg < sizeof(tumbler_regsize), ("bad reg"));

sys/dev/sound/macio/tumbler.c

292

size = tumbler_regsize[reg];

sys/dev/sound/macio/tumbler.c

294

buf[0] = reg;

sys/dev/sound/macio/tumbler.c

389

u_char reg[6];

sys/dev/sound/macio/tumbler.c

403

reg[0] = (l & 0xff0000) >> 16;

sys/dev/sound/macio/tumbler.c

404

reg[1] = (l & 0x00ff00) >> 8;

sys/dev/sound/macio/tumbler.c

405

reg[2] = l & 0x0000ff;

sys/dev/sound/macio/tumbler.c

406

reg[3] = (r & 0xff0000) >> 16;

sys/dev/sound/macio/tumbler.c

407

reg[4] = (r & 0x00ff00) >> 8;

sys/dev/sound/macio/tumbler.c

408

reg[5] = r & 0x0000ff;

sys/dev/sound/macio/tumbler.c

420

tumbler_write(sc, TUMBLER_VOLUME, reg);

sys/dev/sound/pci/als4000.c

736

if (sc->reg) {

sys/dev/sound/pci/als4000.c

737

bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);

sys/dev/sound/pci/als4000.c

738

sc->reg = NULL;

sys/dev/sound/pci/als4000.c

759

sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid,

sys/dev/sound/pci/als4000.c

761

if (sc->reg == NULL) {

sys/dev/sound/pci/als4000.c

765

sc->st = rman_get_bustag(sc->reg);

sys/dev/sound/pci/als4000.c

766

sc->sh = rman_get_bushandle(sc->reg);

sys/dev/sound/pci/als4000.c

79

struct resource *reg, *irq;

sys/dev/sound/pci/als4000.c

846

rman_get_start(sc->reg), rman_get_start(sc->irq),

sys/dev/sound/pci/atiixp.c

1098

rman_get_start(sc->reg), rman_get_start(sc->irq),

sys/dev/sound/pci/atiixp.c

1135

if (sc->reg) {

sys/dev/sound/pci/atiixp.c

1136

bus_release_resource(sc->dev, sc->regtype, sc->regid, sc->reg);

sys/dev/sound/pci/atiixp.c

1137

sc->reg = NULL;

sys/dev/sound/pci/atiixp.c

117

struct resource *reg, *irq;

sys/dev/sound/pci/atiixp.c

1206

sc->reg = bus_alloc_resource_any(dev, sc->regtype,

sys/dev/sound/pci/atiixp.c

1209

if (!sc->reg) {

sys/dev/sound/pci/atiixp.c

1214

sc->st = rman_get_bustag(sc->reg);

sys/dev/sound/pci/atiixp.c

1215

sc->sh = rman_get_bushandle(sc->reg);

sys/dev/sound/pci/atiixp.c

376

atiixp_rdcd(kobj_t obj, void *devinfo, int reg)

sys/dev/sound/pci/atiixp.c

385

data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |

sys/dev/sound/pci/atiixp.c

401

if (reg < 0x7c)

sys/dev/sound/pci/atiixp.c

402

device_printf(sc->dev, "codec read timeout! (reg 0x%x)\n", reg);

sys/dev/sound/pci/atiixp.c

408

atiixp_wrcd(kobj_t obj, void *devinfo, int reg, uint32_t data)

sys/dev/sound/pci/atiixp.c

416

(((uint32_t)reg) << ATI_REG_PHYS_OUT_ADDR_SHIFT) |

sys/dev/sound/pci/atiixp.c

609

uint32_t reg, addr, sz, retry;

sys/dev/sound/pci/atiixp.c

612

reg = ch->dt_cur_bit;

sys/dev/sound/pci/atiixp.c

618

ptr = atiixp_rd(sc, reg);

sys/dev/sound/pci/cmi.c

1009

if (sc->reg)

sys/dev/sound/pci/cmi.c

1010

bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);

sys/dev/sound/pci/cmi.c

1035

bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);

sys/dev/sound/pci/cmi.c

116

struct resource *reg, *irq;

sys/dev/sound/pci/cmi.c

182

int reg, int shift, u_int32_t mask, u_int32_t val)

sys/dev/sound/pci/cmi.c

186

r = cmi_rd(sc, reg, 4);

sys/dev/sound/pci/cmi.c

189

cmi_wr(sc, reg, r, 4);

sys/dev/sound/pci/cmi.c

193

cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask)

sys/dev/sound/pci/cmi.c

197

r = cmi_rd(sc, reg, 4);

sys/dev/sound/pci/cmi.c

199

cmi_wr(sc, reg, r, 4);

sys/dev/sound/pci/cmi.c

203

cmi_set4(struct sc_info *sc, int reg, u_int32_t mask)

sys/dev/sound/pci/cmi.c

207

r = cmi_rd(sc, reg, 4);

sys/dev/sound/pci/cmi.c

209

cmi_wr(sc, reg, r, 4);

sys/dev/sound/pci/cmi.c

780

cmi_mread(struct mpu401 *arg, void *sc, int reg)

sys/dev/sound/pci/cmi.c

784

d = bus_space_read_1(0,0, 0x330 + reg);

sys/dev/sound/pci/cmi.c

791

cmi_mwrite(struct mpu401 *arg, void *sc, int reg, unsigned char b)

sys/dev/sound/pci/cmi.c

794

bus_space_write_1(0,0,0x330 + reg , b);

sys/dev/sound/pci/cmi.c

942

sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid,

sys/dev/sound/pci/cmi.c

944

if (!sc->reg) {

sys/dev/sound/pci/cmi.c

948

sc->st = rman_get_bustag(sc->reg);

sys/dev/sound/pci/cmi.c

949

sc->sh = rman_get_bushandle(sc->reg);

sys/dev/sound/pci/cmi.c

994

rman_get_start(sc->reg), rman_get_start(sc->irq),

sys/dev/sound/pci/cs4281.c

777

sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid, RF_ACTIVE);

sys/dev/sound/pci/cs4281.c

778

if (!sc->reg) {

sys/dev/sound/pci/cs4281.c

780

sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,

sys/dev/sound/pci/cs4281.c

782

if (!sc->reg) {

sys/dev/sound/pci/cs4281.c

787

sc->st = rman_get_bustag(sc->reg);

sys/dev/sound/pci/cs4281.c

788

sc->sh = rman_get_bushandle(sc->reg);

sys/dev/sound/pci/cs4281.c

849

rman_get_start(sc->reg), rman_get_start(sc->irq),

sys/dev/sound/pci/cs4281.c

859

if (sc->reg)

sys/dev/sound/pci/cs4281.c

860

bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);

sys/dev/sound/pci/cs4281.c

889

bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);

sys/dev/sound/pci/cs4281.c

91

struct resource *reg, *irq, *mem;

sys/dev/sound/pci/csamidi.c

108

csamidi_mread(struct mpu401 *arg __unused, void *cookie, int reg)

sys/dev/sound/pci/csamidi.c

116

switch (reg) {

sys/dev/sound/pci/csamidi.c

128

printf("csamidi_mread: unknown register %d\n", reg);

sys/dev/sound/pci/csamidi.c

135

csamidi_mwrite(struct mpu401 *arg __unused, void *cookie, int reg, unsigned char b)

sys/dev/sound/pci/csamidi.c

140

switch (reg) {

sys/dev/sound/pci/csamidi.c

165

printf("csamidi_mwrite: unknown register %d\n", reg);

sys/dev/sound/pci/emu10k1.c

1154

emu_mread(struct mpu401 *arg, void *sc, int reg)

sys/dev/sound/pci/emu10k1.c

1158

d = emu_rd((struct sc_info *)sc, 0x18 + reg, 1);

sys/dev/sound/pci/emu10k1.c

1163

emu_mwrite(struct mpu401 *arg, void *sc, int reg, unsigned char b)

sys/dev/sound/pci/emu10k1.c

1166

emu_wr((struct sc_info *)sc, 0x18 + reg, b, 1);

sys/dev/sound/pci/emu10k1.c

2087

sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &i, RF_ACTIVE);

sys/dev/sound/pci/emu10k1.c

2088

if (sc->reg == NULL) {

sys/dev/sound/pci/emu10k1.c

2092

sc->st = rman_get_bustag(sc->reg);

sys/dev/sound/pci/emu10k1.c

2093

sc->sh = rman_get_bushandle(sc->reg);

sys/dev/sound/pci/emu10k1.c

2131

rman_get_start(sc->reg), rman_get_start(sc->irq),

sys/dev/sound/pci/emu10k1.c

2147

if (sc->reg) bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg);

sys/dev/sound/pci/emu10k1.c

2170

bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg);

sys/dev/sound/pci/emu10k1.c

219

struct resource *reg, *irq;

sys/dev/sound/pci/emu10k1.c

331

emu_rdptr(struct sc_info *sc, int chn, int reg)

sys/dev/sound/pci/emu10k1.c

335

ptr = ((reg << 16) & sc->addrmask) | (chn & EMU_PTR_CHNO_MASK);

sys/dev/sound/pci/emu10k1.c

338

if (reg & 0xff000000) {

sys/dev/sound/pci/emu10k1.c

339

size = (reg >> 24) & 0x3f;

sys/dev/sound/pci/emu10k1.c

340

offset = (reg >> 16) & 0x1f;

sys/dev/sound/pci/emu10k1.c

349

emu_wrptr(struct sc_info *sc, int chn, int reg, u_int32_t data)

sys/dev/sound/pci/emu10k1.c

353

ptr = ((reg << 16) & sc->addrmask) | (chn & EMU_PTR_CHNO_MASK);

sys/dev/sound/pci/emu10k1.c

355

if (reg & 0xff000000) {

sys/dev/sound/pci/emu10k1.c

356

size = (reg >> 24) & 0x3f;

sys/dev/sound/pci/emu10k1.c

357

offset = (reg >> 16) & 0x1f;

sys/dev/sound/pci/emu10k1.c

461

int reg = (channel & 0x20) ? EMU_SOLEH : EMU_SOLEL;

sys/dev/sound/pci/emu10k1.c

463

reg |= 1 << 24;

sys/dev/sound/pci/emu10k1.c

464

reg |= channel << 16;

sys/dev/sound/pci/emu10k1.c

465

emu_wrptr(sc, 0, reg, enable);

sys/dev/sound/pci/emu10kx-midi.c

70

emu_mread(struct mpu401 *arg __unused, void *cookie, int reg)

sys/dev/sound/pci/emu10kx-midi.c

77

d = emu_rd(sc->card, 0x18 + reg, 1);

sys/dev/sound/pci/emu10kx-midi.c

79

d = emu_rdptr(sc->card, 0, sc->port + reg);

sys/dev/sound/pci/emu10kx-midi.c

85

emu_mwrite(struct mpu401 *arg __unused, void *cookie, int reg, unsigned char b)

sys/dev/sound/pci/emu10kx-midi.c

90

emu_wr(sc->card, 0x18 + reg, b, 1);

sys/dev/sound/pci/emu10kx-midi.c

92

emu_wrptr(sc->card, 0, sc->port + reg, b);

sys/dev/sound/pci/emu10kx.c

1442

int reg;

sys/dev/sound/pci/emu10kx.c

1444

reg = (channel & 0x20) ? EMU_SOLEH : EMU_SOLEL;

sys/dev/sound/pci/emu10kx.c

1446

reg |= 1 << 24;

sys/dev/sound/pci/emu10kx.c

1447

reg |= channel << 16;

sys/dev/sound/pci/emu10kx.c

1448

emu_wrptr(sc, 0, reg, enable);

sys/dev/sound/pci/emu10kx.c

3157

sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &i, RF_ACTIVE);

sys/dev/sound/pci/emu10kx.c

3158

if (sc->reg == NULL) {

sys/dev/sound/pci/emu10kx.c

3162

sc->st = rman_get_bustag(sc->reg);

sys/dev/sound/pci/emu10kx.c

3163

sc->sh = rman_get_bushandle(sc->reg);

sys/dev/sound/pci/emu10kx.c

3193

snprintf(status, 255, "rev %d at io 0x%jx irq %jd", sc->rev, rman_get_start(sc->reg), rman_get_start(sc->irq));

sys/dev/sound/pci/emu10kx.c

329

struct resource *reg;

sys/dev/sound/pci/emu10kx.c

3330

if (sc->reg)

sys/dev/sound/pci/emu10kx.c

3331

bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg);

sys/dev/sound/pci/emu10kx.c

3376

if (sc->reg)

sys/dev/sound/pci/emu10kx.c

3377

bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg);

sys/dev/sound/pci/emu10kx.c

646

emu_rdptr(struct emu_sc_info *sc, unsigned int chn, unsigned int reg)

sys/dev/sound/pci/emu10kx.c

650

ptr = ((reg << 16) & sc->address_mask) | (chn & EMU_PTR_CHNO_MASK);

sys/dev/sound/pci/emu10kx.c

662

if (reg & 0xff000000) {

sys/dev/sound/pci/emu10kx.c

663

size = (reg >> 24) & 0x3f;

sys/dev/sound/pci/emu10kx.c

664

offset = (reg >> 16) & 0x1f;

sys/dev/sound/pci/emu10kx.c

673

emu_wrptr(struct emu_sc_info *sc, unsigned int chn, unsigned int reg, uint32_t data)

sys/dev/sound/pci/emu10kx.c

677

ptr = ((reg << 16) & sc->address_mask) | (chn & EMU_PTR_CHNO_MASK);

sys/dev/sound/pci/emu10kx.c

686

if (reg & 0xff000000) {

sys/dev/sound/pci/emu10kx.c

687

size = (reg >> 24) & 0x3f;

sys/dev/sound/pci/emu10kx.c

688

offset = (reg >> 16) & 0x1f;

sys/dev/sound/pci/emu10kx.c

703

emu_rd_p16vptr(struct emu_sc_info *sc, uint16_t chn, uint16_t reg)

sys/dev/sound/pci/emu10kx.c

709

emu_wr_nolock(sc, EMU_A2_PTR, (reg << 16) | chn, 4);

sys/dev/sound/pci/emu10kx.c

718

emu_wr_p16vptr(struct emu_sc_info *sc, uint16_t chn, uint16_t reg, uint32_t data)

sys/dev/sound/pci/emu10kx.c

722

emu_wr_nolock(sc, EMU_A2_PTR, (reg << 16) | chn, 4);

sys/dev/sound/pci/emu10kx.h

153

uint32_t emu_rdptr(struct emu_sc_info *sc, unsigned int chn, unsigned int reg);

sys/dev/sound/pci/emu10kx.h

154

void emu_wrptr(struct emu_sc_info *sc, unsigned int chn, unsigned int reg, uint32_t data);

sys/dev/sound/pci/emu10kx.h

156

uint32_t emu_rd_p16vptr(struct emu_sc_info *sc, uint16_t chn, uint16_t reg);

sys/dev/sound/pci/emu10kx.h

157

void emu_wr_p16vptr(struct emu_sc_info *sc, uint16_t chn, uint16_t reg, uint32_t data);

sys/dev/sound/pci/emuxkireg.h

48

#define EMU_MKSUBREG(sz, idx, reg) (((sz) << 24) | ((idx) << 16) | (reg))

sys/dev/sound/pci/envy24.c

1333

u_int32_t reg, mask;

sys/dev/sound/pci/envy24.c

1356

reg = class | class << 2 |

sys/dev/sound/pci/envy24.c

1360

device_printf(sc->dev, "envy24_route(): MT_SPDOUT-->0x%04x\n", reg);

sys/dev/sound/pci/envy24.c

1362

envy24_wrmt(sc, ENVY24_MT_SPDOUT, reg, 2);

sys/dev/sound/pci/envy24.c

1366

reg = envy24_rdmt(sc, ENVY24_MT_PSDOUT, 2);

sys/dev/sound/pci/envy24.c

1367

reg = (reg & mask) | ((class | class << 8) << dac * 2);

sys/dev/sound/pci/envy24.c

1369

device_printf(sc->dev, "envy24_route(): MT_PSDOUT-->0x%04x\n", reg);

sys/dev/sound/pci/envy24.c

1371

envy24_wrmt(sc, ENVY24_MT_PSDOUT, reg, 2);

sys/dev/sound/pci/envy24.c

1373

reg = envy24_rdmt(sc, ENVY24_MT_RECORD, 4);

sys/dev/sound/pci/envy24.c

1374

reg = (reg & mask) |

sys/dev/sound/pci/envy24.c

1378

device_printf(sc->dev, "envy24_route(): MT_RECORD-->0x%08x\n", reg);

sys/dev/sound/pci/envy24.c

1380

envy24_wrmt(sc, ENVY24_MT_RECORD, reg, 4);

sys/dev/sound/pci/envy24.c

882

i2c_wr(void *codec, void (*ctrl)(void*, unsigned int, unsigned int), u_int32_t dev, int reg, u_int8_t val)

sys/dev/sound/pci/envy24.c

893

if (reg != 0xff) {

sys/dev/sound/pci/envy24.c

895

i2c_wrbit(ptr, ctrl, reg & mask);

sys/dev/sound/pci/es137x.c

1202

es1371_src_read(struct es_info *es, unsigned short reg)

sys/dev/sound/pci/es137x.c

1208

r |= ES1371_SRC_RAM_ADDRO(reg);

sys/dev/sound/pci/es137x.c

1214

es1371_src_write(struct es_info *es, unsigned short reg, unsigned short data)

sys/dev/sound/pci/es137x.c

1220

r |= ES1371_SRC_RAM_ADDRO(reg) | ES1371_SRC_RAM_DATAO(data);

sys/dev/sound/pci/es137x.c

1721

es->reg = bus_alloc_resource_any(dev, es->regtype, &es->regid,

sys/dev/sound/pci/es137x.c

1723

if (es->reg)

sys/dev/sound/pci/es137x.c

1729

es->reg = bus_alloc_resource_any(dev, es->regtype, &es->regid,

sys/dev/sound/pci/es137x.c

1731

if (es->reg)

sys/dev/sound/pci/es137x.c

1739

es->st = rman_get_bustag(es->reg);

sys/dev/sound/pci/es137x.c

1740

es->sh = rman_get_bushandle(es->reg);

sys/dev/sound/pci/es137x.c

1858

rman_get_start(es->reg), rman_get_start(es->irq),

sys/dev/sound/pci/es137x.c

1886

if (es->reg)

sys/dev/sound/pci/es137x.c

1887

bus_release_resource(dev, es->regtype, es->regid, es->reg);

sys/dev/sound/pci/es137x.c

1915

bus_release_resource(dev, es->regtype, es->regid, es->reg);

sys/dev/sound/pci/es137x.c

214

struct resource *reg, *irq;

sys/dev/sound/pci/es137x.c

691

uint32_t reg, ptr;

sys/dev/sound/pci/es137x.c

699

reg = ES1370_REG_DAC1_FRAMECNT;

sys/dev/sound/pci/es137x.c

701

reg = ES1370_REG_DAC2_FRAMECNT;

sys/dev/sound/pci/es137x.c

703

reg = ES1370_REG_ADC_FRAMECNT;

sys/dev/sound/pci/es137x.c

705

es_wr(es, ES1370_REG_MEMPAGE, reg >> 8, 4);

sys/dev/sound/pci/es137x.c

706

ptr = es_rd(es, reg & 0x000000ff, 4) >> 16;

sys/dev/sound/pci/es137x.c

857

uint32_t reg, cnt;

sys/dev/sound/pci/es137x.c

865

reg = ES1370_REG_DAC1_FRAMECNT;

sys/dev/sound/pci/es137x.c

867

reg = ES1370_REG_DAC2_FRAMECNT;

sys/dev/sound/pci/es137x.c

869

reg = ES1370_REG_ADC_FRAMECNT;

sys/dev/sound/pci/es137x.c

870

es_wr(es, ES1370_REG_MEMPAGE, reg >> 8, 4);

sys/dev/sound/pci/es137x.c

871

cnt = es_rd(es, reg & 0x000000ff, 4) >> 16;

sys/dev/sound/pci/fm801.c

143

struct resource *reg, *irq;

sys/dev/sound/pci/fm801.c

586

fm801->reg = bus_alloc_resource_any(dev, fm801->regtype,

sys/dev/sound/pci/fm801.c

588

if(!fm801->reg)

sys/dev/sound/pci/fm801.c

591

fm801->reg = bus_alloc_resource_any(dev,

sys/dev/sound/pci/fm801.c

597

if(fm801->reg) {

sys/dev/sound/pci/fm801.c

598

fm801->st = rman_get_bustag(fm801->reg);

sys/dev/sound/pci/fm801.c

599

fm801->sh = rman_get_bushandle(fm801->reg);

sys/dev/sound/pci/fm801.c

641

rman_get_start(fm801->reg), rman_get_start(fm801->irq),

sys/dev/sound/pci/fm801.c

658

if (fm801->reg) bus_release_resource(dev, fm801->regtype, fm801->regid, fm801->reg);

sys/dev/sound/pci/fm801.c

684

bus_release_resource(dev, fm801->regtype, fm801->regid, fm801->reg);

sys/dev/sound/pci/fm801.c

720

return (fm801->reg);

sys/dev/sound/pci/hda/hdac.c

1251

if (hdac_pcie_snoop[i].reg == 0x00)

sys/dev/sound/pci/hda/hdac.c

1253

v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);

sys/dev/sound/pci/hda/hdac.c

1259

pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);

sys/dev/sound/pci/hda/hdac.c

1260

v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);

sys/dev/sound/pci/hda/hdac.c

226

uint8_t reg;

sys/dev/sound/pci/hdsp-pcm.c

375

int reg;

sys/dev/sound/pci/hdsp-pcm.c

381

reg = HDSP_OUT_ENABLE_BASE;

sys/dev/sound/pci/hdsp-pcm.c

383

reg = HDSP_IN_ENABLE_BASE;

sys/dev/sound/pci/hdsp-pcm.c

393

hdsp_write_1(sc, reg + (4 * offset), value);

sys/dev/sound/pci/hdsp-pcm.c

68

uint32_t reg;

sys/dev/sound/pci/hdsp-pcm.c

887

sc->ctrl_register |= hr->reg;

sys/dev/sound/pci/hdspe-pcm.c

358

int reg;

sys/dev/sound/pci/hdspe-pcm.c

365

reg = HDSPE_OUT_ENABLE_BASE;

sys/dev/sound/pci/hdspe-pcm.c

367

reg = HDSPE_IN_ENABLE_BASE;

sys/dev/sound/pci/hdspe-pcm.c

381

hdspe_write_1(sc, reg + (4 * slot), value);

sys/dev/sound/pci/hdspe-pcm.c

66

uint32_t reg;

sys/dev/sound/pci/hdspe-pcm.c

877

sc->ctrl_register |= hr->reg;

sys/dev/sound/pci/maestro3.c

1356

sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,

sys/dev/sound/pci/maestro3.c

1358

if (!sc->reg) {

sys/dev/sound/pci/maestro3.c

1360

sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,

sys/dev/sound/pci/maestro3.c

1363

if (!sc->reg) {

sys/dev/sound/pci/maestro3.c

1367

sc->st = rman_get_bustag(sc->reg);

sys/dev/sound/pci/maestro3.c

1368

sc->sh = rman_get_bushandle(sc->reg);

sys/dev/sound/pci/maestro3.c

144

struct resource *reg;

sys/dev/sound/pci/maestro3.c

1441

rman_get_start(sc->reg), rman_get_start(sc->irq),

sys/dev/sound/pci/maestro3.c

1464

if (sc->reg)

sys/dev/sound/pci/maestro3.c

1465

bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);

sys/dev/sound/pci/maestro3.c

1492

bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);

sys/dev/sound/pci/neomagic.c

134

bus_space_tag_t st = rman_get_bustag(sc->reg);

sys/dev/sound/pci/neomagic.c

135

bus_space_handle_t sh = rman_get_bushandle(sc->reg);

sys/dev/sound/pci/neomagic.c

152

bus_space_tag_t st = rman_get_bustag(sc->reg);

sys/dev/sound/pci/neomagic.c

153

bus_space_handle_t sh = rman_get_bushandle(sc->reg);

sys/dev/sound/pci/neomagic.c

620

sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,

sys/dev/sound/pci/neomagic.c

624

if (!sc->reg) {

sys/dev/sound/pci/neomagic.c

643

sc->reg);

sys/dev/sound/pci/neomagic.c

66

struct resource *reg, *irq, *buf;

sys/dev/sound/pci/neomagic.c

680

sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->regid,

sys/dev/sound/pci/neomagic.c

683

if (!sc->buf || !sc->reg) {

sys/dev/sound/pci/neomagic.c

706

rman_get_start(sc->buf), rman_get_start(sc->reg),

sys/dev/sound/pci/neomagic.c

721

if (sc->reg) bus_release_resource(dev, SYS_RES_MEMORY, sc->regid, sc->reg);

sys/dev/sound/pci/neomagic.c

740

bus_release_resource(dev, SYS_RES_MEMORY, sc->regid, sc->reg);

sys/dev/sound/pci/solo.c

107

static int ess_rd(struct ess_info *sc, int reg);

sys/dev/sound/pci/solo.c

108

static void ess_wr(struct ess_info *sc, int reg, u_int8_t val);

sys/dev/sound/pci/solo.c

117

static int ess_write(struct ess_info *sc, u_char reg, int val);

sys/dev/sound/pci/solo.c

118

static int ess_read(struct ess_info *sc, u_char reg);

sys/dev/sound/pci/solo.c

179

ess_rd(struct ess_info *sc, int reg)

sys/dev/sound/pci/solo.c

181

return port_rd(sc->sb, reg, 1);

sys/dev/sound/pci/solo.c

185

ess_wr(struct ess_info *sc, int reg, u_int8_t val)

sys/dev/sound/pci/solo.c

187

port_wr(sc->sb, reg, val, 1);

sys/dev/sound/pci/solo.c

266

ess_write(struct ess_info *sc, u_char reg, int val)

sys/dev/sound/pci/solo.c

268

return ess_cmd1(sc, reg, val);

sys/dev/sound/pci/solo.c

272

ess_read(struct ess_info *sc, u_char reg)

sys/dev/sound/pci/solo.c

274

return (ess_cmd(sc, 0xc0) && ess_cmd(sc, reg))? ess_get_byte(sc) : -1;

sys/dev/sound/pci/spicds.c

110

spicds_wrbit(codec, reg & mask);

sys/dev/sound/pci/spicds.c

120

spicds_wrbit(codec, reg & mask);

sys/dev/sound/pci/spicds.c

76

spicds_wrcd(struct spicds_info *codec, int reg, u_int16_t val)

sys/dev/sound/pci/spicds.c

81

device_printf(codec->dev, "spicds_wrcd(codec, 0x%02x, 0x%02x)\n", reg, val);

sys/dev/sound/pci/t4dwave.c

336

u_int32_t i, reg;

sys/dev/sound/pci/t4dwave.c

342

reg = bank? TR_REG_INTENB : TR_REG_INTENA;

sys/dev/sound/pci/t4dwave.c

344

i = tr_rd(tr, reg, 4);

sys/dev/sound/pci/t4dwave.c

349

tr_wr(tr, reg, i, 4);

sys/dev/sound/pci/t4dwave.c

859

tr->reg = bus_alloc_resource_any(dev, tr->regtype, &tr->regid,

sys/dev/sound/pci/t4dwave.c

861

if (tr->reg) {

sys/dev/sound/pci/t4dwave.c

862

tr->st = rman_get_bustag(tr->reg);

sys/dev/sound/pci/t4dwave.c

863

tr->sh = rman_get_bushandle(tr->reg);

sys/dev/sound/pci/t4dwave.c

922

rman_get_start(tr->reg), rman_get_start(tr->irq),

sys/dev/sound/pci/t4dwave.c

936

if (tr->reg) bus_release_resource(dev, tr->regtype, tr->regid, tr->reg);

sys/dev/sound/pci/t4dwave.c

956

bus_release_resource(dev, tr->regtype, tr->regid, tr->reg);

sys/dev/sound/pci/t4dwave.c

98

struct resource *reg, *irq;

sys/dev/sound/pci/via8233.c

1010

int i, reg, stat;

sys/dev/sound/pci/via8233.c

1021

reg = via->pch[i].rbase + VIA_RP_STATUS;

sys/dev/sound/pci/via8233.c

1022

stat = via_rd(via, reg, 1);

sys/dev/sound/pci/via8233.c

1029

via_wr(via, reg, stat, 1);

sys/dev/sound/pci/via8233.c

1037

reg = via->rch[i].rbase + VIA_RP_STATUS;

sys/dev/sound/pci/via8233.c

1038

stat = via_rd(via, reg, 1);

sys/dev/sound/pci/via8233.c

1045

via_wr(via, reg, stat, 1);

sys/dev/sound/pci/via8233.c

110

struct resource *reg, *irq;

sys/dev/sound/pci/via8233.c

1188

via->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &via->regid,

sys/dev/sound/pci/via8233.c

1190

if (!via->reg) {

sys/dev/sound/pci/via8233.c

1194

via->st = rman_get_bustag(via->reg);

sys/dev/sound/pci/via8233.c

1195

via->sh = rman_get_bushandle(via->reg);

sys/dev/sound/pci/via8233.c

1349

rman_get_start(via->reg), rman_get_start(via->irq),

sys/dev/sound/pci/via8233.c

1373

if (via->reg)

sys/dev/sound/pci/via8233.c

1374

bus_release_resource(dev, SYS_RES_IOPORT, via->regid, via->reg);

sys/dev/sound/pci/via8233.c

1412

bus_release_resource(dev, SYS_RES_IOPORT, via->regid, via->reg);

sys/dev/sound/pci/via8233.c

339

via_write_codec(kobj_t obj, void *addr, int reg, uint32_t val)

sys/dev/sound/pci/via8233.c

347

VIA_AC97_CODEC00_VALID | VIA_AC97_INDEX(reg) |

sys/dev/sound/pci/via8233.c

354

via_read_codec(kobj_t obj, void *addr, int reg)

sys/dev/sound/pci/via8233.c

362

VIA_AC97_READ | VIA_AC97_INDEX(reg), 4);

sys/dev/sound/pci/via82c686.c

177

via_write_codec(kobj_t obj, void *addr, int reg, u_int32_t val)

sys/dev/sound/pci/via82c686.c

183

via_wr(via, VIA_CODEC_CTL, VIA_CODEC_PRIVALID | VIA_CODEC_INDEX(reg) | val, 4);

sys/dev/sound/pci/via82c686.c

189

via_read_codec(kobj_t obj, void *addr, int reg)

sys/dev/sound/pci/via82c686.c

196

via_wr(via, VIA_CODEC_CTL, VIA_CODEC_PRIVALID | VIA_CODEC_READ | VIA_CODEC_INDEX(reg),4);

sys/dev/sound/pci/via82c686.c

308

int reg;

sys/dev/sound/pci/via82c686.c

320

reg = (ch->dir == PCMDIR_PLAY)? AC97_REGEXT_FDACRATE : AC97_REGEXT_LADCRATE;

sys/dev/sound/pci/via82c686.c

321

return ac97_setrate(via->codec, reg, speed);

sys/dev/sound/pci/via82c686.c

512

via->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT,

sys/dev/sound/pci/via82c686.c

514

if (!via->reg) {

sys/dev/sound/pci/via82c686.c

518

via->st = rman_get_bustag(via->reg);

sys/dev/sound/pci/via82c686.c

519

via->sh = rman_get_bushandle(via->reg);

sys/dev/sound/pci/via82c686.c

584

rman_get_start(via->reg), rman_get_start(via->irq),

sys/dev/sound/pci/via82c686.c

596

if (via->reg) bus_release_resource(dev, SYS_RES_IOPORT, via->regid, via->reg);

sys/dev/sound/pci/via82c686.c

619

bus_release_resource(dev, SYS_RES_IOPORT, via->regid, via->reg);

sys/dev/sound/pci/via82c686.c

83

struct resource *reg, *irq;

sys/dev/sound/pci/vibes.c

121

sv_direct_get(struct sc_info *sc, u_int8_t reg)

sys/dev/sound/pci/vibes.c

123

return bus_space_read_1(sc->enh_st, sc->enh_sh, reg);

sys/dev/sound/pci/vibes.c

127

_sv_direct_set(struct sc_info *sc, u_int8_t reg, u_int8_t val, int line)

sys/dev/sound/pci/vibes.c

130

bus_space_write_1(sc->enh_st, sc->enh_sh, reg, val);

sys/dev/sound/pci/vibes.c

132

n = sv_direct_get(sc, reg);

sys/dev/sound/pci/vibes.c

134

device_printf(sc->dev, "sv_direct_set register 0x%02x %d != %d from line %d\n", reg, n, val, line);

sys/dev/sound/pci/vibes.c

139

sv_indirect_get(struct sc_info *sc, u_int8_t reg)

sys/dev/sound/pci/vibes.c

141

if (reg == SV_REG_FORMAT || reg == SV_REG_ANALOG_PWR)

sys/dev/sound/pci/vibes.c

142

reg |= SV_CM_INDEX_MCE;

sys/dev/sound/pci/vibes.c

144

bus_space_write_1(sc->enh_st, sc->enh_sh, SV_CM_INDEX, reg);

sys/dev/sound/pci/vibes.c

151

_sv_indirect_set(struct sc_info *sc, u_int8_t reg, u_int8_t val, int line)

sys/dev/sound/pci/vibes.c

153

if (reg == SV_REG_FORMAT || reg == SV_REG_ANALOG_PWR)

sys/dev/sound/pci/vibes.c

154

reg |= SV_CM_INDEX_MCE;

sys/dev/sound/pci/vibes.c

156

bus_space_write_1(sc->enh_st, sc->enh_sh, SV_CM_INDEX, reg);

sys/dev/sound/pci/vibes.c

159

reg &= ~SV_CM_INDEX_MCE;

sys/dev/sound/pci/vibes.c

160

if (reg != SV_REG_ADC_PLLM) {

sys/dev/sound/pci/vibes.c

162

n = sv_indirect_get(sc, reg);

sys/dev/sound/pci/vibes.c

164

device_printf(sc->dev, "sv_indirect_set register 0x%02x %d != %d line %d\n", reg, n, val, line);

sys/dev/sound/pci/vibes.c

462

u_int8_t reg; /* Register */

sys/dev/sound/pci/vibes.c

489

v = sv_indirect_get(sc, mt[dev].reg + channel) & ~mt[dev].max;

sys/dev/sound/pci/vibes.c

499

sv_indirect_set(sc, mt[dev].reg + channel, v);

sys/dev/sound/pci/vibes.c

516

if (mt[i].reg) sv_gain(sc, i, 0, 0);

sys/dev/sound/pcm/ac97.c

306

ac97_rdcd(struct ac97_info *codec, int reg)

sys/dev/sound/pcm/ac97.c

311

i[0] = AC97_READ(codec->methods, codec->devinfo, reg);

sys/dev/sound/pcm/ac97.c

312

i[1] = AC97_READ(codec->methods, codec->devinfo, reg);

sys/dev/sound/pcm/ac97.c

314

i[j-- & 1] = AC97_READ(codec->methods, codec->devinfo, reg);

sys/dev/sound/pcm/ac97.c

317

return AC97_READ(codec->methods, codec->devinfo, reg);

sys/dev/sound/pcm/ac97.c

321

ac97_wrcd(struct ac97_info *codec, int reg, u_int16_t val)

sys/dev/sound/pcm/ac97.c

323

AC97_WRITE(codec->methods, codec->devinfo, reg, val);

sys/dev/sound/pcm/ac97.c

432

if (e->reg && e->enable && e->bits) {

sys/dev/sound/pcm/ac97.c

433

int mask, max, val, reg;

sys/dev/sound/pcm/ac97.c

435

reg = (e->reg >= 0) ? e->reg : -e->reg; /* AC97 register */

sys/dev/sound/pcm/ac97.c

448

if (e->reg > 0) {

sys/dev/sound/pcm/ac97.c

45

int reg; /* register index */

sys/dev/sound/pcm/ac97.c

461

if (e->reg > 0) {

sys/dev/sound/pcm/ac97.c

492

int cur = ac97_rdcd(codec, reg);

sys/dev/sound/pcm/ac97.c

495

ac97_wrcd(codec, reg, val);

sys/dev/sound/pcm/ac97.c

528

codec->mix[SOUND_MIXER_OGAIN].reg = AC97_MIXEXT_SURROUND;

sys/dev/sound/pcm/ac97.c

594

int reg;

sys/dev/sound/pcm/ac97.c

683

reg = codec->mix[i].reg;

sys/dev/sound/pcm/ac97.c

684

if (reg < 0)

sys/dev/sound/pcm/ac97.c

685

reg = -reg;

sys/dev/sound/pcm/ac97.c

686

if (k && reg) {

sys/dev/sound/pcm/ac97.c

687

j = old = ac97_rdcd(codec, reg);

sys/dev/sound/pcm/ac97.c

693

ac97_wrcd(codec, reg, j | 0x8000);

sys/dev/sound/pcm/ac97.c

694

j = ac97_rdcd(codec, reg);

sys/dev/sound/pcm/ac97.c

711

ac97_wrcd(codec, reg,

sys/dev/sound/pcm/ac97.c

713

k = ac97_rdcd(codec, reg) & j;

sys/dev/sound/pcm/ac97.c

715

if (reg == AC97_MIX_TONE &&

sys/dev/sound/pcm/ac97.c

723

} else if (reg == AC97_MIX_BEEP) {

sys/dev/sound/pcm/ac97.c

734

ac97_wrcd(codec, reg, old);

sys/dev/sound/pcm/ac97.h

106

u_int16_t ac97_rdcd(struct ac97_info *codec, int reg);

sys/dev/sound/pcm/ac97.h

107

void ac97_wrcd(struct ac97_info *codec, int reg, u_int16_t val);

sys/dev/spibus/controller/allwinner/aw_spi.c

159

#define AW_SPI_READ_1(sc, reg) bus_read_1((sc)->res[0], (reg))

sys/dev/spibus/controller/allwinner/aw_spi.c

160

#define AW_SPI_WRITE_1(sc, reg, val) bus_write_1((sc)->res[0], (reg), (val))

sys/dev/spibus/controller/allwinner/aw_spi.c

161

#define AW_SPI_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/dev/spibus/controller/allwinner/aw_spi.c

162

#define AW_SPI_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/dev/spibus/controller/allwinner/aw_spi.c

283

uint32_t reg;

sys/dev/spibus/controller/allwinner/aw_spi.c

286

reg = AW_SPI_READ_4(sc, AW_SPI_GCR);

sys/dev/spibus/controller/allwinner/aw_spi.c

287

reg |= AW_SPI_GCR_MODE_MASTER;

sys/dev/spibus/controller/allwinner/aw_spi.c

288

AW_SPI_WRITE_4(sc, AW_SPI_GCR, reg);

sys/dev/spibus/controller/allwinner/aw_spi.c

291

reg = AW_SPI_READ_4(sc, AW_SPI_TCR);

sys/dev/spibus/controller/allwinner/aw_spi.c

293

reg |= AW_SPI_TCR_CPHA;

sys/dev/spibus/controller/allwinner/aw_spi.c

295

reg |= AW_SPI_TCR_CPOL;

sys/dev/spibus/controller/allwinner/aw_spi.c

297

AW_SPI_WRITE_4(sc, AW_SPI_TCR, reg);

sys/dev/spibus/controller/allwinner/aw_spi.c

303

uint32_t reg;

sys/dev/spibus/controller/allwinner/aw_spi.c

306

reg = AW_SPI_READ_4(sc, AW_SPI_TCR);

sys/dev/spibus/controller/allwinner/aw_spi.c

307

reg &= ~(AW_SPI_TCR_SSSEL_MASK);

sys/dev/spibus/controller/allwinner/aw_spi.c

308

reg |= cs << AW_SPI_TCR_SSSEL_SHIFT;

sys/dev/spibus/controller/allwinner/aw_spi.c

309

reg |= AW_SPI_TCR_SS_OWNER;

sys/dev/spibus/controller/allwinner/aw_spi.c

311

reg &= ~(AW_SPI_TCR_SS_LEVEL);

sys/dev/spibus/controller/allwinner/aw_spi.c

313

reg |= AW_SPI_TCR_SS_LEVEL;

sys/dev/spibus/controller/allwinner/aw_spi.c

315

AW_SPI_WRITE_4(sc, AW_SPI_TCR, reg);

sys/dev/spibus/controller/allwinner/aw_spi.c

382

uint32_t reg, txcnt;

sys/dev/spibus/controller/allwinner/aw_spi.c

388

reg = AW_SPI_READ_4(sc, AW_SPI_FSR);

sys/dev/spibus/controller/allwinner/aw_spi.c

389

reg &= AW_SPI_FSR_TF_CNT_MASK;

sys/dev/spibus/controller/allwinner/aw_spi.c

390

txcnt = reg >> AW_SPI_FSR_TF_CNT_SHIFT;

sys/dev/spibus/controller/allwinner/aw_spi.c

404

uint32_t reg;

sys/dev/spibus/controller/allwinner/aw_spi.c

411

reg = AW_SPI_READ_4(sc, AW_SPI_FSR);

sys/dev/spibus/controller/allwinner/aw_spi.c

412

reg = (reg & AW_SPI_FSR_RF_CNT_MASK) >> AW_SPI_FSR_RF_CNT_SHIFT;

sys/dev/spibus/controller/allwinner/aw_spi.c

414

for (i = 0; i < reg; i++) {

sys/dev/spibus/controller/allwinner/aw_spi.c

464

uint32_t reg;

sys/dev/spibus/controller/allwinner/aw_spi.c

478

reg = AW_SPI_READ_4(sc, AW_SPI_FCR);

sys/dev/spibus/controller/allwinner/aw_spi.c

479

if (reg == 0)

sys/dev/spibus/controller/allwinner/aw_spi.c

504

reg = AW_SPI_READ_4(sc, AW_SPI_TCR);

sys/dev/spibus/controller/allwinner/aw_spi.c

505

reg |= AW_SPI_TCR_XCH;

sys/dev/spibus/controller/allwinner/aw_spi.c

506

AW_SPI_WRITE_4(sc, AW_SPI_TCR, reg);

sys/dev/spibus/controller/allwinner/aw_spi.c

529

uint32_t cs, mode, clock, reg;

sys/dev/spibus/controller/allwinner/aw_spi.c

549

reg = AW_SPI_READ_4(sc, AW_SPI_GCR);

sys/dev/spibus/controller/allwinner/aw_spi.c

550

reg |= AW_SPI_GCR_EN | AW_SPI_GCR_SRST;

sys/dev/spibus/controller/allwinner/aw_spi.c

551

AW_SPI_WRITE_4(sc, AW_SPI_GCR, reg);

sys/dev/spibus/controller/allwinner/aw_spi.c

576

reg = AW_SPI_READ_4(sc, AW_SPI_GCR);

sys/dev/spibus/controller/allwinner/aw_spi.c

577

reg &= ~AW_SPI_GCR_EN;

sys/dev/spibus/controller/allwinner/aw_spi.c

578

AW_SPI_WRITE_4(sc, AW_SPI_GCR, reg);

sys/dev/spibus/controller/rockchip/rk_spi.c

123

#define RK_SPI_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg))

sys/dev/spibus/controller/rockchip/rk_spi.c

124

#define RK_SPI_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))

sys/dev/spibus/controller/rockchip/rk_spi.c

141

uint32_t reg;

sys/dev/spibus/controller/rockchip/rk_spi.c

151

reg = RK_SPI_READ_4(sc, RK_SPI_SER);

sys/dev/spibus/controller/rockchip/rk_spi.c

153

reg |= (1 << cs);

sys/dev/spibus/controller/rockchip/rk_spi.c

155

reg &= ~(1 << cs);

sys/dev/spibus/controller/rockchip/rk_spi.c

156

RK_SPI_WRITE_4(sc, RK_SPI_SER, reg);

sys/dev/spibus/controller/rockchip/rk_spi.c

192

uint32_t txftlr, reg;

sys/dev/spibus/controller/rockchip/rk_spi.c

196

reg = RK_SPI_READ_4(sc, RK_SPI_TXFTLR);

sys/dev/spibus/controller/rockchip/rk_spi.c

197

if (reg != txftlr)

sys/dev/ste/if_ste.c

182

#define STE_SETBIT4(sc, reg, x) \

sys/dev/ste/if_ste.c

183

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/ste/if_ste.c

185

#define STE_CLRBIT4(sc, reg, x) \

sys/dev/ste/if_ste.c

186

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/ste/if_ste.c

188

#define STE_SETBIT2(sc, reg, x) \

sys/dev/ste/if_ste.c

189

CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))

sys/dev/ste/if_ste.c

191

#define STE_CLRBIT2(sc, reg, x) \

sys/dev/ste/if_ste.c

192

CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))

sys/dev/ste/if_ste.c

194

#define STE_SETBIT1(sc, reg, x) \

sys/dev/ste/if_ste.c

195

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))

sys/dev/ste/if_ste.c

197

#define STE_CLRBIT1(sc, reg, x) \

sys/dev/ste/if_ste.c

198

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))

sys/dev/ste/if_ste.c

234

ste_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/ste/if_ste.c

237

return (mii_bitbang_readreg(dev, &ste_mii_bitbang_ops, phy, reg));

sys/dev/ste/if_ste.c

241

ste_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/ste/if_ste.c

244

mii_bitbang_writereg(dev, &ste_mii_bitbang_ops, phy, reg, data);

sys/dev/ste/if_stereg.h

481

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/ste/if_stereg.h

482

bus_write_4((sc)->ste_res, reg, val)

sys/dev/ste/if_stereg.h

483

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/ste/if_stereg.h

484

bus_write_2((sc)->ste_res, reg, val)

sys/dev/ste/if_stereg.h

485

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/ste/if_stereg.h

486

bus_write_1((sc)->ste_res, reg, val)

sys/dev/ste/if_stereg.h

488

#define CSR_READ_4(sc, reg) \

sys/dev/ste/if_stereg.h

489

bus_read_4((sc)->ste_res, reg)

sys/dev/ste/if_stereg.h

490

#define CSR_READ_2(sc, reg) \

sys/dev/ste/if_stereg.h

491

bus_read_2((sc)->ste_res, reg)

sys/dev/ste/if_stereg.h

492

#define CSR_READ_1(sc, reg) \

sys/dev/ste/if_stereg.h

493

bus_read_1((sc)->ste_res, reg)

sys/dev/ste/if_stereg.h

495

#define CSR_BARRIER(sc, reg, length, flags) \

sys/dev/ste/if_stereg.h

496

bus_barrier((sc)->ste_res, reg, length, flags)

sys/dev/stge/if_stge.c

284

stge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/stge/if_stge.c

291

if (reg == STGE_PhyCtrl) {

sys/dev/stge/if_stge.c

300

val = mii_bitbang_readreg(dev, &stge_mii_bitbang_ops, phy, reg);

sys/dev/stge/if_stge.c

311

stge_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/stge/if_stge.c

318

mii_bitbang_writereg(dev, &stge_mii_bitbang_ops, phy, reg, val);

sys/dev/stge/if_stgereg.h

100

#define CSR_READ_1(_sc, reg) \

sys/dev/stge/if_stgereg.h

101

bus_read_1((_sc)->sc_res[0], (reg))

sys/dev/stge/if_stgereg.h

103

#define CSR_BARRIER(_sc, reg, length, flags) \

sys/dev/stge/if_stgereg.h

104

bus_barrier((_sc)->sc_res[0], reg, length, flags)

sys/dev/stge/if_stgereg.h

89

#define CSR_WRITE_4(_sc, reg, val) \

sys/dev/stge/if_stgereg.h

90

bus_write_4((_sc)->sc_res[0], (reg), (val))

sys/dev/stge/if_stgereg.h

91

#define CSR_WRITE_2(_sc, reg, val) \

sys/dev/stge/if_stgereg.h

92

bus_write_2((_sc)->sc_res[0], (reg), (val))

sys/dev/stge/if_stgereg.h

93

#define CSR_WRITE_1(_sc, reg, val) \

sys/dev/stge/if_stgereg.h

94

bus_write_1((_sc)->sc_res[0], (reg), (val))

sys/dev/stge/if_stgereg.h

96

#define CSR_READ_4(_sc, reg) \

sys/dev/stge/if_stgereg.h

97

bus_read_4((_sc)->sc_res[0], (reg))

sys/dev/stge/if_stgereg.h

98

#define CSR_READ_2(_sc, reg) \

sys/dev/stge/if_stgereg.h

99

bus_read_2((_sc)->sc_res[0], (reg))

sys/dev/sume/if_sume.c

564

uint32_t reg, devctl, linkctl;

sys/dev/sume/if_sume.c

628

reg = read_reg(adapter, RIFFA_INFO_REG_OFF);

sys/dev/sume/if_sume.c

629

adapter->num_sg = RIFFA_SG_ELEMS * ((reg >> 19) & 0xf);

sys/dev/sume/if_sume.c

630

adapter->sg_buf_size = RIFFA_SG_BUF_SIZE * ((reg >> 19) & 0xf);

sys/dev/sume/if_sume.c

634

if (((reg >> 4) & 0x1) != 1) {

sys/dev/sume/if_sume.c

636

(reg >> 4) & 0x1);

sys/dev/sume/if_sume.c

640

if (((reg >> 5) & 0x3f) == 0 || ((reg >> 11) & 0x3) == 0) {

sys/dev/sume/if_sume.c

642

(reg >> 5) & 0x3f, (reg >> 11) & 0x3);

sys/dev/sume/if_sume.c

646

if ((reg & 0xf) == 0 || (reg & 0xf) > RIFFA_MAX_CHNLS) {

sys/dev/sume/if_sume.c

648

reg & 0xf);

sys/dev/sume/if_sume.c

652

if (((reg >> 19) & 0xf) == 0 ||

sys/dev/sume/if_sume.c

653

((reg >> 19) & 0xf) > RIFFA_MAX_BUS_WIDTH_PARAM) {

sys/dev/sume/if_sume.c

655

(reg >> 19) & 0xf);

sys/dev/sume/if_sume.c

660

reg & 0xf);

sys/dev/sume/if_sume.c

662

((reg >> 19) & 0xf) << 5);

sys/dev/sume/if_sume.c

664

(reg >> 4) & 0x1);

sys/dev/sume/if_sume.c

666

(reg >> 5) & 0x3f);

sys/dev/sume/if_sume.c

668

((reg >> 11) & 0x3) * 2500);

sys/dev/sume/if_sume.c

670

128 << ((reg >> 13) & 0x7));

sys/dev/sume/if_sume.c

672

128 << ((reg >> 16) & 0x7));

sys/dev/superio/superio.c

108

sio_read(struct resource* res, uint8_t reg)

sys/dev/superio/superio.c

110

bus_write_1(res, 0, reg);

sys/dev/superio/superio.c

116

sio_readw(struct resource* res, uint8_t reg)

sys/dev/superio/superio.c

120

v = sio_read(res, reg);

sys/dev/superio/superio.c

122

v |= sio_read(res, reg + 1);

sys/dev/superio/superio.c

127

sio_write(struct resource* res, uint8_t reg, uint8_t val)

sys/dev/superio/superio.c

129

bus_write_1(res, 0, reg);

sys/dev/superio/superio.c

144

sio_ldn_read(struct siosc *sc, uint8_t ldn, uint8_t reg)

sys/dev/superio/superio.c

147

if (reg >= sc->enable_reg) {

sys/dev/superio/superio.c

151

return (sio_read(sc->io_res, reg));

sys/dev/superio/superio.c

155

sio_ldn_readw(struct siosc *sc, uint8_t ldn, uint8_t reg)

sys/dev/superio/superio.c

158

if (reg >= sc->enable_reg) {

sys/dev/superio/superio.c

162

return (sio_readw(sc->io_res, reg));

sys/dev/superio/superio.c

166

sio_ldn_write(struct siosc *sc, uint8_t ldn, uint8_t reg, uint8_t val)

sys/dev/superio/superio.c

169

if (reg <= sc->ldn_reg) {

sys/dev/superio/superio.c

170

printf("ignored attempt to write special register 0x%x\n", reg);

sys/dev/superio/superio.c

175

sio_write(sc->io_res, reg, val);

sys/dev/superio/superio.c

943

superio_ldn_read(device_t dev, uint8_t ldn, uint8_t reg)

sys/dev/superio/superio.c

950

v = sio_ldn_read(sc, ldn, reg);

sys/dev/superio/superio.c

956

superio_read(device_t dev, uint8_t reg)

sys/dev/superio/superio.c

960

return (superio_ldn_read(dev, dinfo->ldn, reg));

sys/dev/superio/superio.c

964

superio_ldn_write(device_t dev, uint8_t ldn, uint8_t reg, uint8_t val)

sys/dev/superio/superio.c

970

sio_ldn_write(sc, ldn, reg, val);

sys/dev/superio/superio.c

975

superio_write(device_t dev, uint8_t reg, uint8_t val)

sys/dev/superio/superio.c

979

return (superio_ldn_write(dev, dinfo->ldn, reg, val));

sys/dev/superio/superio.h

51

uint8_t superio_read(device_t dev, uint8_t reg);

sys/dev/superio/superio.h

52

uint8_t superio_ldn_read(device_t dev, uint8_t ldn, uint8_t reg);

sys/dev/superio/superio.h

53

void superio_write(device_t dev, uint8_t reg, uint8_t val);

sys/dev/superio/superio.h

54

void superio_ldn_write(device_t dev, uint8_t ldn, uint8_t reg, uint8_t val);

sys/dev/sym/sym_defs.h

728

#define SCR_SFBR_REG(reg,op,data) \

sys/dev/sym/sym_defs.h

729

(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))

sys/dev/sym/sym_defs.h

731

#define SCR_REG_SFBR(reg,op,data) \

sys/dev/sym/sym_defs.h

732

(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))

sys/dev/sym/sym_defs.h

734

#define SCR_REG_REG(reg,op,data) \

sys/dev/sym/sym_defs.h

735

(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))

sys/dev/sym/sym_defs.h

765

#define SCR_FROM_REG(reg) \

sys/dev/sym/sym_defs.h

766

SCR_REG_SFBR(reg,SCR_OR,0)

sys/dev/sym/sym_defs.h

768

#define SCR_TO_REG(reg) \

sys/dev/sym/sym_defs.h

769

SCR_SFBR_REG(reg,SCR_OR,0)

sys/dev/sym/sym_defs.h

771

#define SCR_LOAD_REG(reg,data) \

sys/dev/sym/sym_defs.h

772

SCR_REG_REG(reg,SCR_LOAD,data)

sys/dev/sym/sym_defs.h

799

#define SCR_LOAD_R(reg, how, n) \

sys/dev/sym/sym_defs.h

800

(0xe1000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n))

sys/dev/sym/sym_defs.h

802

#define SCR_STORE_R(reg, how, n) \

sys/dev/sym/sym_defs.h

803

(0xe0000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n))

sys/dev/sym/sym_defs.h

805

#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)

sys/dev/sym/sym_defs.h

806

#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)

sys/dev/sym/sym_defs.h

807

#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)

sys/dev/sym/sym_defs.h

808

#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)

sys/dev/sym/sym_defs.h

810

#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)

sys/dev/sym/sym_defs.h

811

#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)

sys/dev/sym/sym_defs.h

812

#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)

sys/dev/sym/sym_defs.h

813

#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)

sys/dev/thunderbolt/nhi_pci.c

393

reg = offset / 32; \

sys/dev/thunderbolt/nhi_pci.c

395

ivr[reg] &= ~(mask << offset); \

sys/dev/thunderbolt/nhi_pci.c

396

ivr[reg] |= (val << offset); \

sys/dev/thunderbolt/nhi_pci.c

404

u_int offset, reg;

sys/dev/thunderbolt/nhi_var.h

222

int nhi_read_lc_mailbox(struct nhi_softc *, u_int reg, uint32_t *val);

sys/dev/thunderbolt/nhi_var.h

223

int nhi_write_lc_mailbox(struct nhi_softc *, u_int reg, uint32_t val);

sys/dev/ti/if_tireg.h

475

#define CPU_REG(reg, cpu) ((reg) + (cpu) * 0x100)

sys/dev/ti/if_tireg.h

896

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/ti/if_tireg.h

897

bus_space_write_4((sc)->ti_btag, (sc)->ti_bhandle, (reg), (val))

sys/dev/ti/if_tireg.h

899

#define CSR_READ_4(sc, reg) \

sys/dev/ti/if_tireg.h

900

bus_space_read_4((sc)->ti_btag, (sc)->ti_bhandle, (reg))

sys/dev/ti/if_tireg.h

902

#define TI_SETBIT(sc, reg, x) \

sys/dev/ti/if_tireg.h

903

CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) | (x)))

sys/dev/ti/if_tireg.h

904

#define TI_CLRBIT(sc, reg, x) \

sys/dev/ti/if_tireg.h

905

CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & ~(x)))

sys/dev/tpm/tpm.c

292

u_int8_t save, reg;

sys/dev/tpm/tpm.c

311

reg = bus_space_read_1(bt, bh, TPM_ACCESS);

sys/dev/tpm/tpm.c

312

if ((reg & TPM_ACCESS_VALID) && (reg & TPM_ACCESS_ACTIVE_LOCALITY) &&

sys/dev/tpm/tpm.c

952

tpm_legacy_in(bus_space_tag_t iot, bus_space_handle_t ioh, int reg)

sys/dev/tpm/tpm.c

954

bus_space_write_1(iot, ioh, 0, reg);

sys/dev/tpm/tpm.c

961

tpm_legacy_out(bus_space_tag_t iot, bus_space_handle_t ioh, int reg, u_int8_t v)

sys/dev/tpm/tpm.c

963

bus_space_write_1(iot, ioh, 0, reg);

sys/dev/tpm/tpm_tis_core.c

184

uint32_t reg;

sys/dev/tpm/tpm_tis_core.c

203

reg = TPM_READ_4(sc->dev, TPM_INT_STS);

sys/dev/tpm/tpm_tis_core.c

204

TPM_WRITE_4(sc->dev, TPM_INT_STS, reg);

sys/dev/tpm/tpm_tis_core.c

206

reg = TPM_READ_4(sc->dev, TPM_INT_ENABLE);

sys/dev/tpm/tpm_tis_core.c

207

reg |= TPM_INT_ENABLE_GLOBAL_ENABLE |

sys/dev/tpm/tpm_tis_core.c

212

TPM_WRITE_4(sc->dev, TPM_INT_ENABLE, reg);

sys/dev/tsec/if_tsec.c

1563

tsec_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/tsec/if_tsec.c

1572

TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);

sys/dev/tsec/if_tsec.c

1587

tsec_miibus_writereg(device_t dev, int phy, int reg, int value)

sys/dev/tsec/if_tsec.c

1595

TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);

sys/dev/tsec/if_tsec.c

1812

uint32_t reg;

sys/dev/tsec/if_tsec.c

1816

reg = TSEC_READ(sc, TSEC_REG_TCTRL);

sys/dev/tsec/if_tsec.c

1817

reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN;

sys/dev/tsec/if_tsec.c

1824

TSEC_WRITE(sc, TSEC_REG_TCTRL, reg);

sys/dev/tsec/if_tsec.c

1826

reg = TSEC_READ(sc, TSEC_REG_RCTRL);

sys/dev/tsec/if_tsec.c

1827

reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP);

sys/dev/tsec/if_tsec.c

1828

reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX;

sys/dev/tsec/if_tsec.c

1831

reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN |

sys/dev/tsec/if_tsec.c

1834

TSEC_WRITE(sc, TSEC_REG_RCTRL, reg);

sys/dev/tsec/if_tsec.h

175

#define TSEC_READ(sc, reg) \

sys/dev/tsec/if_tsec.h

176

bus_space_read_4((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg))

sys/dev/tsec/if_tsec.h

177

#define TSEC_WRITE(sc, reg, val) \

sys/dev/tsec/if_tsec.h

178

bus_space_write_4((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg), (val))

sys/dev/tsec/if_tsec.h

183

#define TSEC_PHY_READ(sc, reg) \

sys/dev/tsec/if_tsec.h

185

(reg) + (sc)->phy_regoff)

sys/dev/tsec/if_tsec.h

186

#define TSEC_PHY_WRITE(sc, reg, val) \

sys/dev/tsec/if_tsec.h

188

(reg) + (sc)->phy_regoff, (val))

sys/dev/tsec/if_tsec.h

298

int tsec_miibus_readreg(device_t dev, int phy, int reg);

sys/dev/tsec/if_tsec.h

299

int tsec_miibus_writereg(device_t dev, int phy, int reg, int value);

sys/dev/tsec/if_tsec_fdt.c

359

uint32_t reg[2];

sys/dev/tsec/if_tsec_fdt.c

364

hw.reg[0] = hw.reg[1] = 0;

sys/dev/tsec/if_tsec_fdt.c

368

if (i == 6 && (hw.reg[0] != 0 || hw.reg[1] != 0)) {

sys/dev/tsec/if_tsec_fdt.c

375

if (i == 6 && (hw.reg[0] != 0 || hw.reg[1] != 0)) {

sys/dev/tsec/if_tsec_fdt.c

384

hw.reg[0] = TSEC_READ(sc, TSEC_REG_MACSTNADDR1);

sys/dev/tsec/if_tsec_fdt.c

385

hw.reg[1] = TSEC_READ(sc, TSEC_REG_MACSTNADDR2);

sys/dev/tws/tws.c

350

u_int32_t reg __tws_debug;

sys/dev/tws/tws.c

362

reg = tws_read_reg(sc, TWS_I2O0_HIMASK, 4);

sys/dev/tws/tws.c

363

TWS_TRACE_DEBUG(sc, "turn-off-intr", reg, 0);

sys/dev/tws/tws.c

510

u_int32_t reg;

sys/dev/tws/tws.c

621

reg = tws_read_reg(sc, TWS_I2O0_CTL, 4);

sys/dev/tws/tws.c

622

TWS_TRACE_DEBUG(sc, "i20 ctl", reg, TWS_I2O0_CTL);

sys/dev/tws/tws.c

623

tws_write_reg(sc, TWS_I2O0_CTL, reg | TWS_BIT1, 4);

sys/dev/tws/tws_cam.c

1195

u_int32_t reg;

sys/dev/tws/tws_cam.c

1211

reg = tws_read_reg(sc, TWS_I2O0_SCRPD3, 4);

sys/dev/tws/tws_cam.c

1212

if ( reg & TWS_BIT13 ) {

sys/dev/tws/tws_cam.c

448

u_int32_t reg, status;

sys/dev/tws/tws_cam.c

484

reg = (u_int32_t)( mfa>>32);

sys/dev/tws/tws_cam.c

485

tws_write_reg(sc, TWS_I2O0_HOBQPH, reg, 4);

sys/dev/tws/tws_cam.c

486

reg = (u_int32_t)(mfa);

sys/dev/tws/tws_cam.c

487

tws_write_reg(sc, TWS_I2O0_HOBQPL, reg, 4);

sys/dev/tws/tws_hdm.c

405

u_int32_t reg;

sys/dev/tws/tws_hdm.c

407

reg = tws_read_reg(sc, TWS_I2O0_SCRPD3, 4);

sys/dev/tws/tws_hdm.c

408

if ( reg & TWS_BIT13 )

sys/dev/tws/tws_hdm.c

437

u_int32_t reg;

sys/dev/tws/tws_hdm.c

440

reg = tws_read_reg(sc, TWS_I2O0_HIMASK, 4);

sys/dev/tws/tws_hdm.c

441

reg = reg | TWS_BIT2;

sys/dev/tws/tws_hdm.c

442

tws_write_reg(sc, TWS_I2O0_HIMASK, reg, 4);

sys/dev/tws/tws_hdm.c

448

u_int32_t reg;

sys/dev/tws/tws_hdm.c

451

reg = tws_read_reg(sc, TWS_I2O0_HIMASK, 4);

sys/dev/tws/tws_hdm.c

452

reg = reg & ~TWS_BIT2;

sys/dev/tws/tws_hdm.c

453

tws_write_reg(sc, TWS_I2O0_HIMASK, reg, 4);

sys/dev/tws/tws_hdm.c

460

u_int32_t reg;

sys/dev/tws/tws_hdm.c

469

reg = tws_read_reg(sc, TWS_I2O0_SCRPD3, 4);

sys/dev/tws/tws_hdm.c

470

} while ( reg & TWS_BIT13 );

sys/dev/tws/tws_hdm.c

484

u_int32_t reg;

sys/dev/tws/tws_hdm.c

486

reg = tws_read_reg(sc, TWS_I2O0_HIBDB, 4);

sys/dev/tws/tws_hdm.c

487

TWS_TRACE_DEBUG(sc, "in bound door bell read ", reg, TWS_I2O0_HIBDB);

sys/dev/tws/tws_hdm.c

488

tws_write_reg(sc, TWS_I2O0_HIBDB, reg | TWS_BIT8, 4);

sys/dev/tws/tws_hdm.c

83

u_int64_t reg __tws_debug;

sys/dev/tws/tws_hdm.c

98

reg = (((u_int64_t)regh) << 32) | regl;

sys/dev/tws/tws_hdm.c

99

TWS_TRACE_DEBUG(sc, "host outbound cleanup",reg, regl);

sys/dev/uart/uart.h

52

#define uart_regofs(bas, reg) ((reg) << (bas)->regshft)

sys/dev/uart/uart.h

56

uart_getreg(struct uart_bas *bas, int reg)

sys/dev/uart/uart.h

63

ret = bus_space_read_8(bas->bst, bas->bsh, uart_regofs(bas, reg));

sys/dev/uart/uart.h

67

ret = bus_space_read_4(bas->bst, bas->bsh, uart_regofs(bas, reg));

sys/dev/uart/uart.h

70

ret = bus_space_read_2(bas->bst, bas->bsh, uart_regofs(bas, reg));

sys/dev/uart/uart.h

73

ret = bus_space_read_1(bas->bst, bas->bsh, uart_regofs(bas, reg));

sys/dev/uart/uart.h

81

uart_setreg(struct uart_bas *bas, int reg, uint32_t value)

sys/dev/uart/uart.h

87

bus_space_write_8(bas->bst, bas->bsh, uart_regofs(bas, reg), value);

sys/dev/uart/uart.h

91

bus_space_write_4(bas->bst, bas->bsh, uart_regofs(bas, reg), value);

sys/dev/uart/uart.h

94

bus_space_write_2(bas->bst, bas->bsh, uart_regofs(bas, reg), value);

sys/dev/uart/uart.h

97

bus_space_write_1(bas->bst, bas->bsh, uart_regofs(bas, reg), value);

sys/dev/uart/uart_dev_imx.c

155

uint32_t baseclk, reg;

sys/dev/uart/uart_dev_imx.c

203

reg = GETREG(bas, REG(UFCR));

sys/dev/uart/uart_dev_imx.c

204

reg = (reg & ~IMXUART_UFCR_RFDIV_MASK) | IMXUART_UFCR_RFDIV_DIV1;

sys/dev/uart/uart_dev_imx.c

205

SETREG(bas, REG(UFCR), reg);

sys/dev/uart/uart_dev_imx.c

215

reg = GETREG(bas, REG(UFCR));

sys/dev/uart/uart_dev_imx.c

216

reg &= ~(IMXUART_UFCR_TXTL_MASK | IMXUART_UFCR_RXTL_MASK);

sys/dev/uart/uart_dev_imx.c

217

reg |= (IMX_FIFOSZ - IMX_TXFIFO_LEVEL) << IMXUART_UFCR_TXTL_SHIFT;

sys/dev/uart/uart_dev_imx.c

218

reg |= IMX_RXFIFO_LEVEL << IMXUART_UFCR_RXTL_SHIFT;

sys/dev/uart/uart_dev_imx.c

219

SETREG(bas, REG(UFCR), reg);

sys/dev/uart/uart_dev_imx.h

201

#define GETREG(bas, reg) \

sys/dev/uart/uart_dev_imx.h

202

bus_space_read_4((bas)->bst, (bas)->bsh, (reg))

sys/dev/uart/uart_dev_imx.h

203

#define SETREG(bas, reg, value) \

sys/dev/uart/uart_dev_imx.h

204

bus_space_write_4((bas)->bst, (bas)->bsh, (reg), (value))

sys/dev/uart/uart_dev_lowrisc.c

126

uint32_t reg;

sys/dev/uart/uart_dev_lowrisc.c

130

reg = GETREG(bas, UART_DR);

sys/dev/uart/uart_dev_lowrisc.c

133

return (reg & 0xff);

sys/dev/uart/uart_dev_lowrisc.c

321

uint32_t reg;

sys/dev/uart/uart_dev_lowrisc.c

333

reg = GETREG(bas, UART_DR);

sys/dev/uart/uart_dev_lowrisc.c

335

uart_rx_put(sc, reg & 0xff);

sys/dev/uart/uart_dev_lowrisc.c

336

} while ((reg & DR_RX_FIFO_EMPTY) == 0);

sys/dev/uart/uart_dev_lowrisc.h

59

#define GETREG(bas, reg) \

sys/dev/uart/uart_dev_lowrisc.h

60

bus_space_read_2((bas)->bst, (bas)->bsh, (reg))

sys/dev/uart/uart_dev_lowrisc.h

61

#define SETREG(bas, reg, value) \

sys/dev/uart/uart_dev_lowrisc.h

62

bus_space_write_2((bas)->bst, (bas)->bsh, (reg), (value))

sys/dev/uart/uart_dev_msm.c

49

#define GETREG(bas, reg) \

sys/dev/uart/uart_dev_msm.c

50

bus_space_read_4((bas)->bst, (bas)->bsh, (reg))

sys/dev/uart/uart_dev_msm.c

51

#define SETREG(bas, reg, value) \

sys/dev/uart/uart_dev_msm.c

52

bus_space_write_4((bas)->bst, (bas)->bsh, (reg), (value))

sys/dev/uart/uart_dev_mu.c

126

#define __uart_getreg(bas, reg) \

sys/dev/uart/uart_dev_mu.c

127

bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))

sys/dev/uart/uart_dev_mu.c

128

#define __uart_setreg(bas, reg, value) \

sys/dev/uart/uart_dev_mu.c

129

bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)

sys/dev/uart/uart_dev_pl011.c

147

#define __uart_getreg(bas, reg) \

sys/dev/uart/uart_dev_pl011.c

148

bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))

sys/dev/uart/uart_dev_pl011.c

149

#define __uart_setreg(bas, reg, value) \

sys/dev/uart/uart_dev_pl011.c

150

bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)

sys/dev/uart/uart_dev_quicc.c

46

#define quicc_read2(bas, reg) \

sys/dev/uart/uart_dev_quicc.c

47

bus_space_read_2((bas)->bst, (bas)->bsh, reg)

sys/dev/uart/uart_dev_quicc.c

48

#define quicc_read4(bas, reg) \

sys/dev/uart/uart_dev_quicc.c

49

bus_space_read_4((bas)->bst, (bas)->bsh, reg)

sys/dev/uart/uart_dev_quicc.c

51

#define quicc_write2(bas, reg, val) \

sys/dev/uart/uart_dev_quicc.c

52

bus_space_write_2((bas)->bst, (bas)->bsh, reg, val)

sys/dev/uart/uart_dev_quicc.c

53

#define quicc_write4(bas, reg, val) \

sys/dev/uart/uart_dev_quicc.c

54

bus_space_write_4((bas)->bst, (bas)->bsh, reg, val)

sys/dev/uart/uart_dev_z8530.c

54

uart_setmreg(struct uart_bas *bas, int reg, int val)

sys/dev/uart/uart_dev_z8530.c

57

uart_setreg(bas, REG_CTRL, reg);

sys/dev/uart/uart_dev_z8530.c

63

uart_getmreg(struct uart_bas *bas, int reg)

sys/dev/uart/uart_dev_z8530.c

66

uart_setreg(bas, REG_CTRL, reg);

sys/dev/ufshci/ufshci_private.h

415

#define ufshci_mmio_offsetof(reg) offsetof(struct ufshci_registers, reg)

sys/dev/ufshci/ufshci_private.h

417

#define ufshci_mmio_read_4(sc, reg) \

sys/dev/ufshci/ufshci_private.h

419

ufshci_mmio_offsetof(reg))

sys/dev/ufshci/ufshci_private.h

421

#define ufshci_mmio_write_4(sc, reg, val) \

sys/dev/ufshci/ufshci_private.h

423

ufshci_mmio_offsetof(reg), val)

sys/dev/usb/controller/atmegadci.h

175

#define ATMEGA_READ_1(sc, reg) \

sys/dev/usb/controller/atmegadci.h

176

bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)

sys/dev/usb/controller/atmegadci.h

178

#define ATMEGA_WRITE_1(sc, reg, data) \

sys/dev/usb/controller/atmegadci.h

179

bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)

sys/dev/usb/controller/atmegadci.h

181

#define ATMEGA_WRITE_MULTI_1(sc, reg, ptr, len) \

sys/dev/usb/controller/atmegadci.h

182

bus_space_write_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len)

sys/dev/usb/controller/atmegadci.h

184

#define ATMEGA_READ_MULTI_1(sc, reg, ptr, len) \

sys/dev/usb/controller/atmegadci.h

185

bus_space_read_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len)

sys/dev/usb/controller/avr32dci.h

141

#define AVR32_READ_4(sc, reg) \

sys/dev/usb/controller/avr32dci.h

142

bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)

sys/dev/usb/controller/avr32dci.h

144

#define AVR32_WRITE_4(sc, reg, data) \

sys/dev/usb/controller/avr32dci.h

145

bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)

sys/dev/usb/controller/avr32dci.h

147

#define AVR32_WRITE_MULTI_4(sc, reg, ptr, len) \

sys/dev/usb/controller/avr32dci.h

148

bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len)

sys/dev/usb/controller/avr32dci.h

150

#define AVR32_READ_MULTI_4(sc, reg, ptr, len) \

sys/dev/usb/controller/avr32dci.h

151

bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len)

sys/dev/usb/controller/dwc3/dwc3.c

188

uint32_t reg;

sys/dev/usb/controller/dwc3/dwc3.c

195

reg = DWC3_READ(sc, DWC3_GCTL);

sys/dev/usb/controller/dwc3/dwc3.c

196

device_printf(sc->dev, "GCTL: %#012x\n", reg);

sys/dev/usb/controller/dwc3/dwc3.c

197

reg = DWC3_READ(sc, DWC3_GUCTL);

sys/dev/usb/controller/dwc3/dwc3.c

198

device_printf(sc->dev, "GUCTL: %#012x\n", reg);

sys/dev/usb/controller/dwc3/dwc3.c

199

reg = DWC3_READ(sc, DWC3_GUCTL1);

sys/dev/usb/controller/dwc3/dwc3.c

200

device_printf(sc->dev, "GUCTL1: %#012x\n", reg);

sys/dev/usb/controller/dwc3/dwc3.c

201

reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0);

sys/dev/usb/controller/dwc3/dwc3.c

202

device_printf(sc->dev, "GUSB2PHYCFG0: %#012x\n", reg);

sys/dev/usb/controller/dwc3/dwc3.c

203

reg = DWC3_READ(sc, DWC3_GUSB3PIPECTL0);

sys/dev/usb/controller/dwc3/dwc3.c

204

device_printf(sc->dev, "GUSB3PIPECTL0: %#012x\n", reg);

sys/dev/usb/controller/dwc3/dwc3.c

205

reg = DWC3_READ(sc, DWC3_DCFG);

sys/dev/usb/controller/dwc3/dwc3.c

206

device_printf(sc->dev, "DCFG: %#012x\n", reg);

sys/dev/usb/controller/dwc3/dwc3.c

220

uint32_t reg;

sys/dev/usb/controller/dwc3/dwc3.c

224

reg = DWC3_READ(sc, offs[i]);

sys/dev/usb/controller/dwc3/dwc3.c

226

device_printf(sc->dev, "hwparams[%d]: %#012x\n", i, reg);

sys/dev/usb/controller/dwc3/dwc3.c

272

uint32_t reg;

sys/dev/usb/controller/dwc3/dwc3.c

274

reg = DWC3_READ(sc, DWC3_GCTL);

sys/dev/usb/controller/dwc3/dwc3.c

275

reg &= ~DWC3_GCTL_PRTCAPDIR_MASK;

sys/dev/usb/controller/dwc3/dwc3.c

276

reg |= DWC3_GCTL_PRTCAPDIR_HOST;

sys/dev/usb/controller/dwc3/dwc3.c

277

DWC3_WRITE(sc, DWC3_GCTL, reg);

sys/dev/usb/controller/dwc3/dwc3.c

284

reg = DWC3_READ(sc, DWC3_GUCTL);

sys/dev/usb/controller/dwc3/dwc3.c

285

reg |= DWC3_GUCTL_HOST_AUTO_RETRY;

sys/dev/usb/controller/dwc3/dwc3.c

286

DWC3_WRITE(sc, DWC3_GUCTL, reg);

sys/dev/usb/controller/dwc3/dwc3.c

294

uint32_t reg;

sys/dev/usb/controller/dwc3/dwc3.c

302

reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0);

sys/dev/usb/controller/dwc3/dwc3.c

304

reg &= ~(DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(0xf));

sys/dev/usb/controller/dwc3/dwc3.c

305

reg |= DWC3_GUSB2PHYCFG0_PHYIF |

sys/dev/usb/controller/dwc3/dwc3.c

308

reg &= ~(DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(0xf));

sys/dev/usb/controller/dwc3/dwc3.c

309

reg |= DWC3_GUSB2PHYCFG0_PHYIF |

sys/dev/usb/controller/dwc3/dwc3.c

312

DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, reg);

sys/dev/usb/controller/dwc3/dwc3.c

321

uint32_t ghwp0, reg;

sys/dev/usb/controller/dwc3/dwc3.c

324

reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0);

sys/dev/usb/controller/dwc3/dwc3.c

326

reg &= ~DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS;

sys/dev/usb/controller/dwc3/dwc3.c

328

reg |= DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS;

sys/dev/usb/controller/dwc3/dwc3.c

330

reg &= ~DWC3_GUSB2PHYCFG0_SUSPENDUSB20;

sys/dev/usb/controller/dwc3/dwc3.c

333

reg |= DWC3_GUSB2PHYCFG0_SUSPENDUSB20;

sys/dev/usb/controller/dwc3/dwc3.c

335

reg &= ~DWC3_GUSB2PHYCFG0_ENBLSLPM;

sys/dev/usb/controller/dwc3/dwc3.c

337

reg |= DWC3_GUSB2PHYCFG0_ENBLSLPM;

sys/dev/usb/controller/dwc3/dwc3.c

338

DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, reg);

sys/dev/usb/controller/dwc3/dwc3.c

340

reg = DWC3_READ(sc, DWC3_GUCTL1);

sys/dev/usb/controller/dwc3/dwc3.c

342

reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;

sys/dev/usb/controller/dwc3/dwc3.c

343

DWC3_WRITE(sc, DWC3_GUCTL1, reg);

sys/dev/usb/controller/dwc3/dwc3.c

345

reg = DWC3_READ(sc, DWC3_GUSB3PIPECTL0);

sys/dev/usb/controller/dwc3/dwc3.c

347

reg &= ~DWC3_GUSB3PIPECTL0_DELAYP1TRANS;

sys/dev/usb/controller/dwc3/dwc3.c

349

reg |= DWC3_GUSB3PIPECTL0_DISRXDETINP3;

sys/dev/usb/controller/dwc3/dwc3.c

351

reg &= ~DWC3_GUSB3PIPECTL0_SUSPENDUSB3;

sys/dev/usb/controller/dwc3/dwc3.c

354

reg |= DWC3_GUSB3PIPECTL0_SUSPENDUSB3;

sys/dev/usb/controller/dwc3/dwc3.c

355

DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, reg);

sys/dev/usb/controller/dwc3/dwc3.c

394

uint32_t reg;

sys/dev/usb/controller/dwc3/dwc3.c

485

reg = DWC3_READ(sc, DWC3_GUCTL1);

sys/dev/usb/controller/dwc3/dwc3.c

488

reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;

sys/dev/usb/controller/dwc3/dwc3.c

489

DWC3_WRITE(sc, DWC3_GUCTL1, reg);

sys/dev/usb/controller/dwc_otg.c

3654

uint32_t reg;

sys/dev/usb/controller/dwc_otg.c

3675

reg = DOTG_DIEPCTL(ep_no & UE_ADDR);

sys/dev/usb/controller/dwc_otg.c

3678

reg = DOTG_DOEPCTL(ep_no & UE_ADDR);

sys/dev/usb/controller/dwc_otg.c

3683

DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);

sys/dev/usb/controller/dwc_otg.c

3684

DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL);

sys/dev/usb/controller/dwc_otg.c

3707

uint32_t reg;

sys/dev/usb/controller/dwc_otg.c

3716

reg = DOTG_DIEPCTL(ep_no);

sys/dev/usb/controller/dwc_otg.c

3718

reg = DOTG_DOEPCTL(ep_no);

sys/dev/usb/controller/dwc_otg.c

3747

DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);

sys/dev/usb/controller/dwc_otg.c

3748

DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID);

sys/dev/usb/controller/dwc_otg.c

3749

DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK);

sys/dev/usb/controller/dwc_otg.h

45

#define DWC_OTG_READ_4(sc, reg) \

sys/dev/usb/controller/dwc_otg.h

46

bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)

sys/dev/usb/controller/dwc_otg.h

48

#define DWC_OTG_WRITE_4(sc, reg, data) \

sys/dev/usb/controller/dwc_otg.h

49

bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)

sys/dev/usb/controller/ehci_imx.c

157

uint32_t reg;

sys/dev/usb/controller/ehci_imx.c

160

reg = bus_read_4(sc->mmio, index * sizeof(uint32_t));

sys/dev/usb/controller/ehci_imx.c

161

bus_write_4(sc->mmio, index * sizeof(uint32_t), reg | bits);

sys/dev/usb/controller/ehci_imx.c

169

uint32_t reg;

sys/dev/usb/controller/ehci_imx.c

172

reg = bus_read_4(sc->mmio, index * sizeof(uint32_t));

sys/dev/usb/controller/ehci_imx.c

173

bus_write_4(sc->mmio, index * sizeof(uint32_t), reg & ~bits);

sys/dev/usb/controller/musb_otg.c

3555

uint8_t reg;

sys/dev/usb/controller/musb_otg.c

3887

reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);

sys/dev/usb/controller/musb_otg.c

3888

reg |= MUSB2_MASK_RESET;

sys/dev/usb/controller/musb_otg.c

3889

MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);

sys/dev/usb/controller/musb_otg.c

3894

reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);

sys/dev/usb/controller/musb_otg.c

3895

reg &= ~MUSB2_MASK_RESET;

sys/dev/usb/controller/musb_otg.c

3896

MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);

sys/dev/usb/controller/musb_otg.c

3899

reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);

sys/dev/usb/controller/musb_otg.c

3900

if (reg & MUSB2_MASK_HSMODE)

sys/dev/usb/controller/musb_otg.h

288

#define MUSB2_READ_2(sc, reg) \

sys/dev/usb/controller/musb_otg.h

289

bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)

sys/dev/usb/controller/musb_otg.h

291

#define MUSB2_WRITE_2(sc, reg, data) \

sys/dev/usb/controller/musb_otg.h

292

bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)

sys/dev/usb/controller/musb_otg.h

294

#define MUSB2_READ_1(sc, reg) \

sys/dev/usb/controller/musb_otg.h

295

bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)

sys/dev/usb/controller/musb_otg.h

297

#define MUSB2_WRITE_1(sc, reg, data) \

sys/dev/usb/controller/musb_otg.h

298

bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)

sys/dev/usb/controller/ohci_pci.c

100

uint32_t reg;

sys/dev/usb/controller/ohci_pci.c

106

reg = pci_read_config(self, PCI_CBMEM, 4);

sys/dev/usb/controller/ohci_pci.c

109

pci_write_config(self, PCI_CBMEM, reg, 4);

sys/dev/usb/controller/uss820dci.c

163

uss820dci_update_shared_1(struct uss820dci_softc *sc, uint8_t reg,

sys/dev/usb/controller/uss820dci.c

169

temp = USS820_READ_1(sc, reg);

sys/dev/usb/controller/uss820dci.c

172

USS820_WRITE_1(sc, reg, temp);

sys/dev/usb/controller/uss820dci.h

263

#define USS820_READ_1(sc, reg) \

sys/dev/usb/controller/uss820dci.h

264

bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (reg) * USS820_REG_STRIDE)

sys/dev/usb/controller/uss820dci.h

266

#define USS820_WRITE_1(sc, reg, data) \

sys/dev/usb/controller/uss820dci.h

267

bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (reg) * USS820_REG_STRIDE, (data))

sys/dev/usb/net/if_aue.c

299

#define AUE_SETBIT(sc, reg, x) \

sys/dev/usb/net/if_aue.c

300

aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) | (x))

sys/dev/usb/net/if_aue.c

302

#define AUE_CLRBIT(sc, reg, x) \

sys/dev/usb/net/if_aue.c

303

aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) & ~(x))

sys/dev/usb/net/if_aue.c

306

aue_csr_read_1(struct aue_softc *sc, uint16_t reg)

sys/dev/usb/net/if_aue.c

315

USETW(req.wIndex, reg);

sys/dev/usb/net/if_aue.c

325

aue_csr_read_2(struct aue_softc *sc, uint16_t reg)

sys/dev/usb/net/if_aue.c

334

USETW(req.wIndex, reg);

sys/dev/usb/net/if_aue.c

344

aue_csr_write_1(struct aue_softc *sc, uint16_t reg, uint8_t val)

sys/dev/usb/net/if_aue.c

352

USETW(req.wIndex, reg);

sys/dev/usb/net/if_aue.c

361

aue_csr_write_2(struct aue_softc *sc, uint16_t reg, uint16_t val)

sys/dev/usb/net/if_aue.c

368

USETW(req.wIndex, reg);

sys/dev/usb/net/if_aue.c

419

aue_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_aue.c

445

aue_csr_write_1(sc, AUE_PHY_CTL, reg | AUE_PHYCTL_READ);

sys/dev/usb/net/if_aue.c

466

aue_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/usb/net/if_aue.c

481

aue_csr_write_1(sc, AUE_PHY_CTL, reg | AUE_PHYCTL_WRITE);

sys/dev/usb/net/if_axe.c

318

axe_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_axe.c

329

axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val);

sys/dev/usb/net/if_axe.c

333

if (AXE_IS_772(sc) && reg == MII_BMSR) {

sys/dev/usb/net/if_axe.c

349

axe_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/usb/net/if_axe.c

360

axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val);

sys/dev/usb/net/if_axge.c

253

axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg)

sys/dev/usb/net/if_axge.c

257

axge_read_mem(sc, cmd, 1, reg, &val, 1);

sys/dev/usb/net/if_axge.c

263

uint16_t reg)

sys/dev/usb/net/if_axge.c

267

axge_read_mem(sc, cmd, index, reg, &val, 2);

sys/dev/usb/net/if_axge.c

272

axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg, uint8_t val)

sys/dev/usb/net/if_axge.c

274

axge_write_mem(sc, cmd, 1, reg, &val, 1);

sys/dev/usb/net/if_axge.c

279

uint16_t reg, uint16_t val)

sys/dev/usb/net/if_axge.c

284

axge_write_mem(sc, cmd, index, reg, &temp, 2);

sys/dev/usb/net/if_axge.c

288

axge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_axge.c

299

val = axge_read_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy);

sys/dev/usb/net/if_axge.c

308

axge_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/usb/net/if_axge.c

318

axge_write_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy, val);

sys/dev/usb/net/if_cue.c

189

#define CUE_SETBIT(sc, reg, x) \

sys/dev/usb/net/if_cue.c

190

cue_csr_write_1(sc, reg, cue_csr_read_1(sc, reg) | (x))

sys/dev/usb/net/if_cue.c

192

#define CUE_CLRBIT(sc, reg, x) \

sys/dev/usb/net/if_cue.c

193

cue_csr_write_1(sc, reg, cue_csr_read_1(sc, reg) & ~(x))

sys/dev/usb/net/if_cue.c

196

cue_csr_read_1(struct cue_softc *sc, uint16_t reg)

sys/dev/usb/net/if_cue.c

204

USETW(req.wIndex, reg);

sys/dev/usb/net/if_cue.c

214

cue_csr_read_2(struct cue_softc *sc, uint8_t reg)

sys/dev/usb/net/if_cue.c

222

USETW(req.wIndex, reg);

sys/dev/usb/net/if_cue.c

230

cue_csr_write_1(struct cue_softc *sc, uint16_t reg, uint16_t val)

sys/dev/usb/net/if_cue.c

237

USETW(req.wIndex, reg);

sys/dev/usb/net/if_mos.c

266

mos_reg_read_1(struct mos_softc *sc, int reg)

sys/dev/usb/net/if_mos.c

275

USETW(req.wIndex, reg);

sys/dev/usb/net/if_mos.c

281

MOS_DPRINTFN("mos_reg_read_1 error, reg: %d\n", reg);

sys/dev/usb/net/if_mos.c

288

mos_reg_read_2(struct mos_softc *sc, int reg)

sys/dev/usb/net/if_mos.c

299

USETW(req.wIndex, reg);

sys/dev/usb/net/if_mos.c

305

MOS_DPRINTFN("mos_reg_read_2 error, reg: %d", reg);

sys/dev/usb/net/if_mos.c

312

mos_reg_write_1(struct mos_softc *sc, int reg, int aval)

sys/dev/usb/net/if_mos.c

322

USETW(req.wIndex, reg);

sys/dev/usb/net/if_mos.c

328

MOS_DPRINTFN("mos_reg_write_1 error, reg: %d", reg);

sys/dev/usb/net/if_mos.c

335

mos_reg_write_2(struct mos_softc *sc, int reg, int aval)

sys/dev/usb/net/if_mos.c

346

USETW(req.wIndex, reg);

sys/dev/usb/net/if_mos.c

352

MOS_DPRINTFN("mos_reg_write_2 error, reg: %d", reg);

sys/dev/usb/net/if_mos.c

421

mos_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_mos.c

433

mos_reg_write_1(sc, MOS_PHY_STS, (reg & MOS_PHYSTS_PHYREG) |

sys/dev/usb/net/if_mos.c

451

mos_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/usb/net/if_mos.c

463

mos_reg_write_1(sc, MOS_PHY_STS, (reg & MOS_PHYSTS_PHYREG) |

sys/dev/usb/net/if_muge.c

344

lan78xx_wait_for_bits(struct muge_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/usb/net/if_muge.c

355

if ((err = lan78xx_read_reg(sc, reg, &val)) != 0)

sys/dev/usb/net/if_muge.c

654

lan78xx_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_muge.c

671

addr = (phy << 11) | (reg << 6) |

sys/dev/usb/net/if_muge.c

707

lan78xx_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/usb/net/if_muge.c

729

addr = (phy << 11) | (reg << 6) |

sys/dev/usb/net/if_rue.c

233

#define RUE_SETBIT(sc, reg, x) \

sys/dev/usb/net/if_rue.c

234

rue_csr_write_1(sc, reg, rue_csr_read_1(sc, reg) | (x))

sys/dev/usb/net/if_rue.c

236

#define RUE_CLRBIT(sc, reg, x) \

sys/dev/usb/net/if_rue.c

237

rue_csr_write_1(sc, reg, rue_csr_read_1(sc, reg) & ~(x))

sys/dev/usb/net/if_rue.c

268

rue_csr_read_1(struct rue_softc *sc, uint16_t reg)

sys/dev/usb/net/if_rue.c

272

rue_read_mem(sc, reg, &val, 1);

sys/dev/usb/net/if_rue.c

277

rue_csr_read_2(struct rue_softc *sc, uint16_t reg)

sys/dev/usb/net/if_rue.c

281

rue_read_mem(sc, reg, &val, 2);

sys/dev/usb/net/if_rue.c

286

rue_csr_write_1(struct rue_softc *sc, uint16_t reg, uint8_t val)

sys/dev/usb/net/if_rue.c

288

return (rue_write_mem(sc, reg, &val, 1));

sys/dev/usb/net/if_rue.c

292

rue_csr_write_2(struct rue_softc *sc, uint16_t reg, uint16_t val)

sys/dev/usb/net/if_rue.c

297

return (rue_write_mem(sc, reg, &temp, 2));

sys/dev/usb/net/if_rue.c

301

rue_csr_write_4(struct rue_softc *sc, int reg, uint32_t val)

sys/dev/usb/net/if_rue.c

306

return (rue_write_mem(sc, reg, &temp, 4));

sys/dev/usb/net/if_rue.c

310

rue_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_rue.c

324

switch (reg) {

sys/dev/usb/net/if_rue.c

345

if (RUE_REG_MIN <= reg && reg <= RUE_REG_MAX) {

sys/dev/usb/net/if_rue.c

346

rval = rue_csr_read_1(sc, reg);

sys/dev/usb/net/if_rue.c

362

rue_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/usb/net/if_rue.c

375

switch (reg) {

sys/dev/usb/net/if_rue.c

395

if (RUE_REG_MIN <= reg && reg <= RUE_REG_MAX) {

sys/dev/usb/net/if_rue.c

396

rue_csr_write_1(sc, reg, data);

sys/dev/usb/net/if_smsc.c

335

smsc_wait_for_bits(struct smsc_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/usb/net/if_smsc.c

346

if ((err = smsc_read_reg(sc, reg, &val)) != 0)

sys/dev/usb/net/if_smsc.c

443

smsc_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_smsc.c

459

addr = (phy << 11) | (reg << 6) | SMSC_MII_READ | SMSC_MII_BUSY;

sys/dev/usb/net/if_smsc.c

491

smsc_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/usb/net/if_smsc.c

512

addr = (phy << 11) | (reg << 6) | SMSC_MII_WRITE | SMSC_MII_BUSY;

sys/dev/usb/net/if_udav.c

223

#define UDAV_SETBIT(sc, reg, x) \

sys/dev/usb/net/if_udav.c

224

udav_csr_write1(sc, reg, udav_csr_read1(sc, reg) | (x))

sys/dev/usb/net/if_udav.c

226

#define UDAV_CLRBIT(sc, reg, x) \

sys/dev/usb/net/if_udav.c

227

udav_csr_write1(sc, reg, udav_csr_read1(sc, reg) & ~(x))

sys/dev/usb/net/if_udav.c

802

udav_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_udav.c

819

UDAV_EPAR_PHY_ADR0 | (reg & UDAV_EPAR_EROA_MASK));

sys/dev/usb/net/if_udav.c

835

phy, reg, data16);

sys/dev/usb/net/if_udav.c

843

udav_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/usb/net/if_udav.c

859

UDAV_EPAR_PHY_ADR0 | (reg & UDAV_EPAR_EROA_MASK));

sys/dev/usb/net/if_ure.c

1121

uint32_t reg;

sys/dev/usb/net/if_ure.c

1146

reg = URE_COALESCE_SUPER / 8;

sys/dev/usb/net/if_ure.c

1149

reg = URE_COALESCE_HIGH / 8;

sys/dev/usb/net/if_ure.c

1152

reg = URE_COALESCE_SLOW / 8;

sys/dev/usb/net/if_ure.c

1155

ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, reg);

sys/dev/usb/net/if_ure.c

1156

reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +

sys/dev/usb/net/if_ure.c

1158

ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 4);

sys/dev/usb/net/if_ure.c

1162

reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +

sys/dev/usb/net/if_ure.c

1164

ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8);

sys/dev/usb/net/if_ure.c

1170

reg = URE_8156_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +

sys/dev/usb/net/if_ure.c

1172

ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8);

sys/dev/usb/net/if_ure.c

1348

int reg;

sys/dev/usb/net/if_ure.c

1361

reg = ure_ocp_reg_read(sc, 0xa5d4);

sys/dev/usb/net/if_ure.c

1362

reg &= ~URE_ADV_2500TFDX;

sys/dev/usb/net/if_ure.c

1369

reg |= URE_ADV_2500TFDX;

sys/dev/usb/net/if_ure.c

1374

reg |= URE_ADV_2500TFDX;

sys/dev/usb/net/if_ure.c

1400

ure_ocp_reg_write(sc, 0xa5d4, reg);

sys/dev/usb/net/if_ure.c

221

#define URE_SETBIT_1(sc, reg, index, x) \

sys/dev/usb/net/if_ure.c

222

ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x))

sys/dev/usb/net/if_ure.c

223

#define URE_SETBIT_2(sc, reg, index, x) \

sys/dev/usb/net/if_ure.c

224

ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x))

sys/dev/usb/net/if_ure.c

2241

uint32_t reg;

sys/dev/usb/net/if_ure.c

225

#define URE_SETBIT_4(sc, reg, index, x) \

sys/dev/usb/net/if_ure.c

226

ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x))

sys/dev/usb/net/if_ure.c

2270

reg = 0;

sys/dev/usb/net/if_ure.c

2273

reg |= URE_TXPKT_IPV4_CS;

sys/dev/usb/net/if_ure.c

228

#define URE_CLRBIT_1(sc, reg, index, x) \

sys/dev/usb/net/if_ure.c

2281

reg |= URE_TXPKT_IPV4_CS;

sys/dev/usb/net/if_ure.c

2283

reg |= URE_TXPKT_TCP_CS;

sys/dev/usb/net/if_ure.c

2285

reg |= URE_TXPKT_UDP_CS;

sys/dev/usb/net/if_ure.c

2286

reg |= l4off << URE_L4_OFFSET_SHIFT;

sys/dev/usb/net/if_ure.c

229

ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x))

sys/dev/usb/net/if_ure.c

2296

reg |= URE_TXPKT_IPV6_CS;

sys/dev/usb/net/if_ure.c

2298

reg |= URE_TXPKT_TCP_CS;

sys/dev/usb/net/if_ure.c

230

#define URE_CLRBIT_2(sc, reg, index, x) \

sys/dev/usb/net/if_ure.c

2300

reg |= URE_TXPKT_UDP_CS;

sys/dev/usb/net/if_ure.c

2301

reg |= l4off << URE_L4_OFFSET_SHIFT;

sys/dev/usb/net/if_ure.c

2304

*regout = reg;

sys/dev/usb/net/if_ure.c

231

ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x))

sys/dev/usb/net/if_ure.c

232

#define URE_CLRBIT_4(sc, reg, index, x) \

sys/dev/usb/net/if_ure.c

233

ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x))

sys/dev/usb/net/if_ure.c

272

ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)

sys/dev/usb/net/if_ure.c

278

shift = (reg & 3) << 3;

sys/dev/usb/net/if_ure.c

279

reg &= ~3;

sys/dev/usb/net/if_ure.c

281

ure_read_mem(sc, reg, index, &temp, 4);

sys/dev/usb/net/if_ure.c

289

ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index)

sys/dev/usb/net/if_ure.c

295

shift = (reg & 2) << 3;

sys/dev/usb/net/if_ure.c

296

reg &= ~3;

sys/dev/usb/net/if_ure.c

298

ure_read_mem(sc, reg, index, &temp, 4);

sys/dev/usb/net/if_ure.c

306

ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index)

sys/dev/usb/net/if_ure.c

310

ure_read_mem(sc, reg, index, &temp, 4);

sys/dev/usb/net/if_ure.c

315

ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)

sys/dev/usb/net/if_ure.c

322

shift = reg & 3;

sys/dev/usb/net/if_ure.c

325

if (reg & 3) {

sys/dev/usb/net/if_ure.c

328

reg &= ~3;

sys/dev/usb/net/if_ure.c

332

return (ure_write_mem(sc, reg, index | byen, &temp, 4));

sys/dev/usb/net/if_ure.c

336

ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)

sys/dev/usb/net/if_ure.c

343

shift = reg & 2;

sys/dev/usb/net/if_ure.c

346

if (reg & 2) {

sys/dev/usb/net/if_ure.c

349

reg &= ~3;

sys/dev/usb/net/if_ure.c

353

return (ure_write_mem(sc, reg, index | byen, &temp, 4));

sys/dev/usb/net/if_ure.c

357

ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)

sys/dev/usb/net/if_ure.c

362

return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4));

sys/dev/usb/net/if_ure.c

368

uint16_t reg;

sys/dev/usb/net/if_ure.c

371

reg = (addr & 0x0fff) | 0xb000;

sys/dev/usb/net/if_ure.c

373

return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA));

sys/dev/usb/net/if_ure.c

379

uint16_t reg;

sys/dev/usb/net/if_ure.c

382

reg = (addr & 0x0fff) | 0xb000;

sys/dev/usb/net/if_ure.c

384

ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data);

sys/dev/usb/net/if_ure.c

395

ure_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/usb/net/if_ure.c

407

if (reg == URE_GMEDIASTAT) {

sys/dev/usb/net/if_ure.c

413

val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2);

sys/dev/usb/net/if_ure.c

421

ure_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/usb/net/if_ure.c

434

ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val);

sys/dev/usb/net/ruephy.c

116

int reg;

sys/dev/usb/net/ruephy.c

138

reg = PHY_READ(sc, RUEPHY_MII_MSR) |

sys/dev/usb/net/ruephy.c

140

if (reg & RUEPHY_MSR_LINK)

sys/dev/usb/serial/ufintek.c

632

ufintek_cfg_write(struct ufintek_softc *sc, uint16_t reg, uint8_t val)

sys/dev/usb/serial/ufintek.c

640

USETW(req.wValue, reg);

sys/dev/usb/serial/ufintek.c

653

ufintek_cfg_read(struct ufintek_softc *sc, uint16_t reg)

sys/dev/usb/serial/ufintek.c

660

USETW(req.wValue, reg);

sys/dev/usb/serial/ufintek.c

667

DPRINTF("reg=0x%04x, val=0x%02x\n", reg, val);

sys/dev/usb/serial/umcs.c

1002

device_printf(sc->sc_dev, "Reading UART%d register %d failed: invalid length %d\n", portno, reg, len);

sys/dev/usb/serial/umcs.c

1005

device_printf(sc->sc_dev, "Reading UART%d register %d failed: %s\n", portno, reg, usbd_errstr(err));

sys/dev/usb/serial/umcs.c

1010

umcs7840_set_UART_reg_sync(struct umcs7840_softc *sc, uint8_t portno, uint8_t reg, uint8_t data)

sys/dev/usb/serial/umcs.c

1022

USETW(req.wIndex, reg);

sys/dev/usb/serial/umcs.c

1027

device_printf(sc->sc_dev, "Writing UART%d register %d failed: %s\n", portno, reg, usbd_errstr(err));

sys/dev/usb/serial/umcs.c

943

umcs7840_get_reg_sync(struct umcs7840_softc *sc, uint8_t reg, uint8_t *data)

sys/dev/usb/serial/umcs.c

952

USETW(req.wIndex, reg);

sys/dev/usb/serial/umcs.c

957

device_printf(sc->sc_dev, "Reading register %d failed: invalid length %d\n", reg, len);

sys/dev/usb/serial/umcs.c

960

device_printf(sc->sc_dev, "Reading register %d failed: %s\n", reg, usbd_errstr(err));

sys/dev/usb/serial/umcs.c

965

umcs7840_set_reg_sync(struct umcs7840_softc *sc, uint8_t reg, uint8_t data)

sys/dev/usb/serial/umcs.c

973

USETW(req.wIndex, reg);

sys/dev/usb/serial/umcs.c

978

device_printf(sc->sc_dev, "Writing register %d failed: %s\n", reg, usbd_errstr(err));

sys/dev/usb/serial/umcs.c

984

umcs7840_get_UART_reg_sync(struct umcs7840_softc *sc, uint8_t portno, uint8_t reg, uint8_t *data)

sys/dev/usb/serial/umcs.c

997

USETW(req.wIndex, reg);

sys/dev/usb/serial/umoscom.c

551

umoscom_cfg_write(struct umoscom_softc *sc, uint16_t reg, uint16_t val)

sys/dev/usb/serial/umoscom.c

558

USETW(req.wIndex, reg);

sys/dev/usb/serial/umoscom.c

566

umoscom_cfg_read(struct umoscom_softc *sc, uint16_t reg)

sys/dev/usb/serial/umoscom.c

574

USETW(req.wIndex, reg);

sys/dev/usb/serial/umoscom.c

580

DPRINTF("reg=0x%04x, val=0x%02x\n", reg, val);

sys/dev/usb/video/udl.c

917

udl_cmd_write_reg_1(struct udl_cmd_buf *cb, uint8_t reg, uint8_t val)

sys/dev/usb/video/udl.c

922

udl_cmd_insert_int_1(cb, reg);

sys/dev/usb/video/udl.c

927

udl_cmd_write_reg_3(struct udl_cmd_buf *cb, uint8_t reg, uint32_t val)

sys/dev/usb/video/udl.c

930

udl_cmd_write_reg_1(cb, reg + 0, (val >> 16) & 0xff);

sys/dev/usb/video/udl.c

931

udl_cmd_write_reg_1(cb, reg + 1, (val >> 8) & 0xff);

sys/dev/usb/video/udl.c

932

udl_cmd_write_reg_1(cb, reg + 2, (val >> 0) & 0xff);

sys/dev/usb/wlan/if_mtw.c

1004

mtw_write_cfg(struct mtw_softc *sc, uint16_t reg, uint32_t val)

sys/dev/usb/wlan/if_mtw.c

1012

USETW(req.wIndex, reg);

sys/dev/usb/wlan/if_mtw.c

1246

mtw_read(struct mtw_softc *sc, uint16_t reg, uint32_t *val)

sys/dev/usb/wlan/if_mtw.c

1251

error = mtw_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof tmp);

sys/dev/usb/wlan/if_mtw.c

1260

mtw_read_region_1(struct mtw_softc *sc, uint16_t reg, uint8_t *buf, int len)

sys/dev/usb/wlan/if_mtw.c

1267

USETW(req.wIndex, reg);

sys/dev/usb/wlan/if_mtw.c

1274

mtw_write_2(struct mtw_softc *sc, uint16_t reg, uint16_t val)

sys/dev/usb/wlan/if_mtw.c

1281

USETW(req.wIndex, reg);

sys/dev/usb/wlan/if_mtw.c

1287

mtw_write(struct mtw_softc *sc, uint16_t reg, uint32_t val)

sys/dev/usb/wlan/if_mtw.c

1292

if ((error = mtw_write_2(sc, reg, val & 0xffff)) == 0) {

sys/dev/usb/wlan/if_mtw.c

1294

error = mtw_write_2(sc, reg + 2, val >> 16);

sys/dev/usb/wlan/if_mtw.c

1301

mtw_write_region_1(struct mtw_softc *sc, uint16_t reg, const uint8_t *buf,

sys/dev/usb/wlan/if_mtw.c

1309

USETW(req.wIndex, reg);

sys/dev/usb/wlan/if_mtw.c

1316

mtw_set_region_4(struct mtw_softc *sc, uint16_t reg, uint32_t val, int count)

sys/dev/usb/wlan/if_mtw.c

1322

error = mtw_write(sc, reg + i, val);

sys/dev/usb/wlan/if_mtw.c

1331

uint16_t reg;

sys/dev/usb/wlan/if_mtw.c

1363

reg = MTW_EFUSE_DATA0 + (addr & 0xc);

sys/dev/usb/wlan/if_mtw.c

1364

if ((error = mtw_read(sc, reg, &tmp)) != 0)

sys/dev/usb/wlan/if_mtw.c

1379

mtw_bbp_read(struct mtw_softc *sc, uint8_t reg, uint8_t *val)

sys/dev/usb/wlan/if_mtw.c

1393

tmp = MTW_BBP_CSR_READ | MTW_BBP_CSR_KICK | reg << 8;

sys/dev/usb/wlan/if_mtw.c

1411

mtw_bbp_write(struct mtw_softc *sc, uint8_t reg, uint8_t val)

sys/dev/usb/wlan/if_mtw.c

1425

tmp = MTW_BBP_CSR_KICK | reg << 8 | val;

sys/dev/usb/wlan/if_mtw.c

1584

uint32_t reg;

sys/dev/usb/wlan/if_mtw.c

1587

reg = val;

sys/dev/usb/wlan/if_mtw.c

1589

reg |= (uint32_t)val << 16;

sys/dev/usb/wlan/if_mtw.c

1591

sc->txpow20mhz[ridx] = reg;

sys/dev/usb/wlan/if_mtw.c

1592

sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);

sys/dev/usb/wlan/if_mtw.c

1593

sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);

sys/dev/usb/wlan/if_mtw.c

260

uint8_t reg;

sys/dev/usb/wlan/if_mtw.c

266

uint32_t reg;

sys/dev/usb/wlan/if_mtw.c

270

uint8_t reg;

sys/dev/usb/wlan/if_mtw.c

3575

mtw_rf_write(struct mtw_softc *sc, uint8_t bank, uint8_t reg, uint8_t val)

sys/dev/usb/wlan/if_mtw.c

3595

reg << 8 | val;

sys/dev/usb/wlan/if_mtw.c

3637

mtw_rf_read(struct mtw_softc *sc, uint8_t bank, uint8_t reg, uint8_t *val)

sys/dev/usb/wlan/if_mtw.c

3656

tmp = MTW_RF_CSR_KICK | (bank & 0xf) << shift | reg << 8;

sys/dev/usb/wlan/if_mtw.c

4177

if ((error = mtw_bbp_write(sc, mt7601_def_bbp[i].reg,

sys/dev/usb/wlan/if_mtw.c

4194

error = mtw_rf_write(sc, 0, mt7601_rf_bank0[i].reg,

sys/dev/usb/wlan/if_mtw.c

4201

error = mtw_rf_write(sc, 4, mt7601_rf_bank4[i].reg,

sys/dev/usb/wlan/if_mtw.c

4208

error = mtw_rf_write(sc, 5, mt7601_rf_bank5[i].reg,

sys/dev/usb/wlan/if_mtw.c

4473

mtw_write(sc, mt7601_def_mac[i].reg,

sys/dev/usb/wlan/if_mtw.c

475

mtw_read_cfg(struct mtw_softc *sc, uint16_t reg, uint32_t *val)

sys/dev/usb/wlan/if_mtw.c

485

USETW(req.wIndex, reg);

sys/dev/usb/wlan/if_rsu.c

1161

uint32_t reg;

sys/dev/usb/wlan/if_rsu.c

1164

reg = rsu_read_4(sc, R92S_EFUSE_CTRL);

sys/dev/usb/wlan/if_rsu.c

1165

reg = RW(reg, R92S_EFUSE_CTRL_ADDR, addr);

sys/dev/usb/wlan/if_rsu.c

1166

reg &= ~R92S_EFUSE_CTRL_VALID;

sys/dev/usb/wlan/if_rsu.c

1167

rsu_write_4(sc, R92S_EFUSE_CTRL, reg);

sys/dev/usb/wlan/if_rsu.c

1170

reg = rsu_read_4(sc, R92S_EFUSE_CTRL);

sys/dev/usb/wlan/if_rsu.c

1171

if (reg & R92S_EFUSE_CTRL_VALID)

sys/dev/usb/wlan/if_rsu.c

1172

return (MS(reg, R92S_EFUSE_CTRL_DATA));

sys/dev/usb/wlan/if_rsu.c

1185

uint32_t reg;

sys/dev/usb/wlan/if_rsu.c

1190

reg = rsu_read_1(sc, R92S_EE_9346CR);

sys/dev/usb/wlan/if_rsu.c

1191

if ((reg & (R92S_9356SEL | R92S_EEPROM_EN)) != R92S_EEPROM_EN)

sys/dev/usb/wlan/if_rsu.c

1195

reg = rsu_read_1(sc, R92S_EFUSE_TEST + 3);

sys/dev/usb/wlan/if_rsu.c

1196

rsu_write_1(sc, R92S_EFUSE_TEST + 3, reg | 0x80);

sys/dev/usb/wlan/if_rsu.c

1198

rsu_write_1(sc, R92S_EFUSE_TEST + 3, reg & ~0x80);

sys/dev/usb/wlan/if_rsu.c

1203

reg = rsu_efuse_read_1(sc, addr);

sys/dev/usb/wlan/if_rsu.c

1204

if (reg == 0xff)

sys/dev/usb/wlan/if_rsu.c

1207

off = reg >> 4;

sys/dev/usb/wlan/if_rsu.c

1208

msk = reg & 0xf;

sys/dev/usb/wlan/if_rsu.c

1293

uint32_t reg;

sys/dev/usb/wlan/if_rsu.c

1306

reg = rsu_read_1(sc, R92S_GPIO_CTRL);

sys/dev/usb/wlan/if_rsu.c

1307

if (reg != 0xff && (reg & R92S_GPIO_WPS))

sys/dev/usb/wlan/if_rsu.c

3106

uint32_t reg;

sys/dev/usb/wlan/if_rsu.c

3166

reg = rsu_read_2(sc, R92S_SYS_CLKR);

sys/dev/usb/wlan/if_rsu.c

3167

reg = (reg & ~R92S_SWHW_SEL) | R92S_FWHW_SEL;

sys/dev/usb/wlan/if_rsu.c

3168

rsu_write_2(sc, R92S_SYS_CLKR, reg);

sys/dev/usb/wlan/if_rsu.c

3188

uint32_t reg;

sys/dev/usb/wlan/if_rsu.c

3197

reg = rsu_read_2(sc, R92S_SYS_CLKR);

sys/dev/usb/wlan/if_rsu.c

3198

if (reg & R92S_FWHW_SEL) {

sys/dev/usb/wlan/if_rsu.c

3200

reg & ~(R92S_SWHW_SEL | R92S_FWHW_SEL));

sys/dev/usb/wlan/if_rsu.c

3209

reg = rsu_read_1(sc, R92S_AFE_MISC);

sys/dev/usb/wlan/if_rsu.c

3210

rsu_write_1(sc, R92S_AFE_MISC, reg | R92S_AFE_MISC_BGEN);

sys/dev/usb/wlan/if_rsu.c

3211

rsu_write_1(sc, R92S_AFE_MISC, reg | R92S_AFE_MISC_BGEN |

sys/dev/usb/wlan/if_rsu.c

3235

reg = rsu_read_1(sc, R92S_AFE_PLL_CTRL);

sys/dev/usb/wlan/if_rsu.c

3236

rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x11);

sys/dev/usb/wlan/if_rsu.c

3238

rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x51);

sys/dev/usb/wlan/if_rsu.c

3240

rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x11);

sys/dev/usb/wlan/if_rsu.c

3267

reg = rsu_read_2(sc, R92S_SYS_CLKR);

sys/dev/usb/wlan/if_rsu.c

3268

reg = (reg & ~R92S_SWHW_SEL) | R92S_FWHW_SEL;

sys/dev/usb/wlan/if_rsu.c

3269

rsu_write_2(sc, R92S_SYS_CLKR, reg);

sys/dev/usb/wlan/if_rsu.c

3284

reg = rsu_read_1(sc, R92S_TCR);

sys/dev/usb/wlan/if_rsu.c

3285

if ((reg & (R92S_TCR_IMEM_CHK_RPT | R92S_TCR_EMEM_CHK_RPT)) ==

sys/dev/usb/wlan/if_rsu.c

3295

reg = rsu_read_1(sc, R92S_CR);

sys/dev/usb/wlan/if_rsu.c

3296

rsu_write_1(sc, R92S_CR, reg & ~R92S_CR_TXDMA_EN);

sys/dev/usb/wlan/if_rsu.c

3298

rsu_write_1(sc, R92S_CR, reg | R92S_CR_TXDMA_EN);

sys/dev/usb/wlan/if_rsu.c

3381

uint32_t reg;

sys/dev/usb/wlan/if_rsu.c

3449

reg = rsu_read_1(sc, R92S_TCR);

sys/dev/usb/wlan/if_rsu.c

3450

if (reg & R92S_TCR_IMEM_CODE_DONE)

sys/dev/usb/wlan/if_rsu.c

3468

reg = rsu_read_2(sc, R92S_TCR);

sys/dev/usb/wlan/if_rsu.c

3469

if (reg & R92S_TCR_EMEM_CODE_DONE)

sys/dev/usb/wlan/if_rsu.c

3593

uint32_t reg;

sys/dev/usb/wlan/if_rsu.c

3601

reg = rsu_read_4(sc, R92S_RCR);

sys/dev/usb/wlan/if_rsu.c

3602

reg &= ~R92S_RCR_AICV;

sys/dev/usb/wlan/if_rsu.c

3603

reg |= R92S_RCR_APP_PHYSTS;

sys/dev/usb/wlan/if_rsu.c

3605

reg |= R92S_RCR_TCP_OFFLD_EN;

sys/dev/usb/wlan/if_rsu.c

3606

rsu_write_4(sc, R92S_RCR, reg);

sys/dev/usb/wlan/if_rum.c

1809

rum_read(struct rum_softc *sc, uint16_t reg)

sys/dev/usb/wlan/if_rum.c

1813

rum_read_multi(sc, reg, &val, sizeof val);

sys/dev/usb/wlan/if_rum.c

1819

rum_read_multi(struct rum_softc *sc, uint16_t reg, void *buf, int len)

sys/dev/usb/wlan/if_rum.c

1827

USETW(req.wIndex, reg);

sys/dev/usb/wlan/if_rum.c

1839

rum_write(struct rum_softc *sc, uint16_t reg, uint32_t val)

sys/dev/usb/wlan/if_rum.c

1843

return (rum_write_multi(sc, reg, &tmp, sizeof tmp));

sys/dev/usb/wlan/if_rum.c

1847

rum_write_multi(struct rum_softc *sc, uint16_t reg, const void *buf,

sys/dev/usb/wlan/if_rum.c

1860

USETW(req.wIndex, reg + offset);

sys/dev/usb/wlan/if_rum.c

1877

rum_setbits(struct rum_softc *sc, uint16_t reg, uint32_t mask)

sys/dev/usb/wlan/if_rum.c

1879

return (rum_write(sc, reg, rum_read(sc, reg) | mask));

sys/dev/usb/wlan/if_rum.c

1883

rum_clrbits(struct rum_softc *sc, uint16_t reg, uint32_t mask)

sys/dev/usb/wlan/if_rum.c

1885

return (rum_write(sc, reg, rum_read(sc, reg) & ~mask));

sys/dev/usb/wlan/if_rum.c

1889

rum_modbits(struct rum_softc *sc, uint16_t reg, uint32_t set, uint32_t unset)

sys/dev/usb/wlan/if_rum.c

1891

return (rum_write(sc, reg, (rum_read(sc, reg) & ~unset) | set));

sys/dev/usb/wlan/if_rum.c

1912

rum_bbp_write(struct rum_softc *sc, uint8_t reg, uint8_t val)

sys/dev/usb/wlan/if_rum.c

1916

DPRINTFN(2, "reg=0x%08x\n", reg);

sys/dev/usb/wlan/if_rum.c

1923

tmp = RT2573_BBP_BUSY | (reg & 0x7f) << 8 | val;

sys/dev/usb/wlan/if_rum.c

1928

rum_bbp_read(struct rum_softc *sc, uint8_t reg)

sys/dev/usb/wlan/if_rum.c

1933

DPRINTFN(2, "reg=0x%08x\n", reg);

sys/dev/usb/wlan/if_rum.c

1940

val = RT2573_BBP_BUSY | RT2573_BBP_READ | reg << 8;

sys/dev/usb/wlan/if_rum.c

1956

rum_rf_write(struct rum_softc *sc, uint8_t reg, uint32_t val)

sys/dev/usb/wlan/if_rum.c

1973

(reg & 3);

sys/dev/usb/wlan/if_rum.c

1977

sc->rf_regs[reg] = val;

sys/dev/usb/wlan/if_rum.c

1979

DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0xfffff);

sys/dev/usb/wlan/if_rum.c

2477

if (sc->bbp_prom[i].reg == 0 || sc->bbp_prom[i].reg == 0xff)

sys/dev/usb/wlan/if_rum.c

2479

DPRINTF("BBP R%d=%02x\n", sc->bbp_prom[i].reg,

sys/dev/usb/wlan/if_rum.c

2526

rum_bbp_write(sc, rum_def_bbp[i].reg, rum_def_bbp[i].val);

sys/dev/usb/wlan/if_rum.c

2530

if (sc->bbp_prom[i].reg == 0 || sc->bbp_prom[i].reg == 0xff)

sys/dev/usb/wlan/if_rum.c

2532

rum_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);

sys/dev/usb/wlan/if_rum.c

2562

rum_write(sc, rum_def_mac[i].reg, rum_def_mac[i].val);

sys/dev/usb/wlan/if_rum.c

2663

uint16_t reg = RT2573_MCU_CODE_BASE;

sys/dev/usb/wlan/if_rum.c

2667

for (; size >= 4; reg += 4, ucode += 4, size -= 4) {

sys/dev/usb/wlan/if_rum.c

2668

err = rum_write(sc, reg, UGETDW(ucode));

sys/dev/usb/wlan/if_rum.c

279

uint32_t reg;

sys/dev/usb/wlan/if_rum.c

307

uint8_t reg;

sys/dev/usb/wlan/if_rumvar.h

156

uint8_t reg;

sys/dev/usb/wlan/if_run.c

1350

run_read(struct run_softc *sc, uint16_t reg, uint32_t *val)

sys/dev/usb/wlan/if_run.c

1355

error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof tmp);

sys/dev/usb/wlan/if_run.c

1364

run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len)

sys/dev/usb/wlan/if_run.c

1371

USETW(req.wIndex, reg);

sys/dev/usb/wlan/if_run.c

1378

run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val)

sys/dev/usb/wlan/if_run.c

1385

USETW(req.wIndex, reg);

sys/dev/usb/wlan/if_run.c

1392

run_write(struct run_softc *sc, uint16_t reg, uint32_t val)

sys/dev/usb/wlan/if_run.c

1396

if ((error = run_write_2(sc, reg, val & 0xffff)) == 0)

sys/dev/usb/wlan/if_run.c

1397

error = run_write_2(sc, reg + 2, val >> 16);

sys/dev/usb/wlan/if_run.c

1402

run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf,

sys/dev/usb/wlan/if_run.c

1413

error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8);

sys/dev/usb/wlan/if_run.c

1433

USETW(req.wIndex, reg);

sys/dev/usb/wlan/if_run.c

1438

reg += delta;

sys/dev/usb/wlan/if_run.c

1447

run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int len)

sys/dev/usb/wlan/if_run.c

1453

error = run_write(sc, reg + i, val);

sys/dev/usb/wlan/if_run.c

1461

uint16_t reg;

sys/dev/usb/wlan/if_run.c

1494

reg = RT3070_EFUSE_DATA3 - (addr & 0xc);

sys/dev/usb/wlan/if_run.c

1495

if ((error = run_read(sc, reg, &tmp)) != 0)

sys/dev/usb/wlan/if_run.c

1559

run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val)

sys/dev/usb/wlan/if_run.c

1573

tmp = RT3070_RF_KICK | reg << 8;

sys/dev/usb/wlan/if_run.c

1591

run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val)

sys/dev/usb/wlan/if_run.c

1605

tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;

sys/dev/usb/wlan/if_run.c

1610

run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val)

sys/dev/usb/wlan/if_run.c

1624

tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8;

sys/dev/usb/wlan/if_run.c

1642

run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val)

sys/dev/usb/wlan/if_run.c

1656

tmp = RT2860_BBP_CSR_KICK | reg << 8 | val;

sys/dev/usb/wlan/if_run.c

1886

sc->bbp[i].reg = val >> 8;

sys/dev/usb/wlan/if_run.c

1888

"BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val);

sys/dev/usb/wlan/if_run.c

1896

sc->rf[i].reg = val >> 8;

sys/dev/usb/wlan/if_run.c

1898

sc->rf[i].reg, sc->rf[i].val);

sys/dev/usb/wlan/if_run.c

2008

uint32_t reg;

sys/dev/usb/wlan/if_run.c

2011

reg = val;

sys/dev/usb/wlan/if_run.c

2013

reg |= (uint32_t)val << 16;

sys/dev/usb/wlan/if_run.c

2015

sc->txpow20mhz[ridx] = reg;

sys/dev/usb/wlan/if_run.c

2016

sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);

sys/dev/usb/wlan/if_run.c

2017

sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);

sys/dev/usb/wlan/if_run.c

4730

uint8_t reg, rf, txpow_bound;

sys/dev/usb/wlan/if_run.c

4783

run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg,

sys/dev/usb/wlan/if_run.c

4797

reg = 2;

sys/dev/usb/wlan/if_run.c

4802

run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg,

sys/dev/usb/wlan/if_run.c

4808

run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg,

sys/dev/usb/wlan/if_run.c

4817

reg = 3;

sys/dev/usb/wlan/if_run.c

4824

rf |= (reg << 6);

sys/dev/usb/wlan/if_run.c

4833

rf |= (reg << 6);

sys/dev/usb/wlan/if_run.c

5439

run_bbp_write(sc, rt5592_def_bbp[i].reg,

sys/dev/usb/wlan/if_run.c

5448

run_bbp_write(sc, rt5390_def_bbp[i].reg,

sys/dev/usb/wlan/if_run.c

5501

run_bbp_write(sc, rt2860_def_bbp[i].reg,

sys/dev/usb/wlan/if_run.c

5546

run_rt3070_rf_write(sc, rt3572_def_rf[i].reg,

sys/dev/usb/wlan/if_run.c

5551

run_rt3070_rf_write(sc, rt3070_def_rf[i].reg,

sys/dev/usb/wlan/if_run.c

5688

run_rt3070_rf_write(sc, rt3593_def_rf[i].reg,

sys/dev/usb/wlan/if_run.c

570

uint16_t reg;

sys/dev/usb/wlan/if_run.c

5744

run_rt3070_rf_write(sc, rt5592_def_rf[i].reg,

sys/dev/usb/wlan/if_run.c

5751

run_rt3070_rf_write(sc, rt5392_def_rf[i].reg,

sys/dev/usb/wlan/if_run.c

5764

run_rt3070_rf_write(sc, rt5390_def_rf[i].reg,

sys/dev/usb/wlan/if_run.c

577

uint8_t reg;

sys/dev/usb/wlan/if_run.c

5924

if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff)

sys/dev/usb/wlan/if_run.c

5926

run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);

sys/dev/usb/wlan/if_run.c

6182

run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val);

sys/dev/usb/wlan/if_run.c

625

uint8_t reg;

sys/dev/usb/wlan/if_run.c

6259

if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)

sys/dev/usb/wlan/if_run.c

6261

run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);

sys/dev/usb/wlan/if_run.c

648

uint8_t reg;

sys/dev/usb/wlan/if_runvar.h

204

uint8_t reg;

sys/dev/usb/wlan/if_uath.c

1180

uath_config(struct uath_softc *sc, uint32_t reg, uint32_t val)

sys/dev/usb/wlan/if_uath.c

1185

write.reg = htobe32(reg);

sys/dev/usb/wlan/if_uath.c

1193

reg);

sys/dev/usb/wlan/if_uath.c

1199

uath_config_multi(struct uath_softc *sc, uint32_t reg, const void *data,

sys/dev/usb/wlan/if_uath.c

1205

write.reg = htobe32(reg);

sys/dev/usb/wlan/if_uath.c

1214

"could not write %d bytes to register 0x%02x\n", len, reg);

sys/dev/usb/wlan/if_uathreg.h

225

uint32_t reg;

sys/dev/usb/wlan/if_ural.c

1401

ural_read(struct ural_softc *sc, uint16_t reg)

sys/dev/usb/wlan/if_ural.c

1410

USETW(req.wIndex, reg);

sys/dev/usb/wlan/if_ural.c

1424

ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len)

sys/dev/usb/wlan/if_ural.c

1432

USETW(req.wIndex, reg);

sys/dev/usb/wlan/if_ural.c

1443

ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val)

sys/dev/usb/wlan/if_ural.c

1451

USETW(req.wIndex, reg);

sys/dev/usb/wlan/if_ural.c

1462

ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len)

sys/dev/usb/wlan/if_ural.c

1470

USETW(req.wIndex, reg);

sys/dev/usb/wlan/if_ural.c

1481

ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val)

sys/dev/usb/wlan/if_ural.c

1497

tmp = reg << 8 | val;

sys/dev/usb/wlan/if_ural.c

1502

ural_bbp_read(struct ural_softc *sc, uint8_t reg)

sys/dev/usb/wlan/if_ural.c

1507

val = RAL_BBP_WRITE | reg << 8;

sys/dev/usb/wlan/if_ural.c

1525

ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val)

sys/dev/usb/wlan/if_ural.c

1541

tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3);

sys/dev/usb/wlan/if_ural.c

1546

sc->rf_regs[reg] = val;

sys/dev/usb/wlan/if_ural.c

1548

DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff);

sys/dev/usb/wlan/if_ural.c

1950

ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val);

sys/dev/usb/wlan/if_ural.c

1955

if (sc->bbp_prom[i].reg == 0xff)

sys/dev/usb/wlan/if_ural.c

1957

ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);

sys/dev/usb/wlan/if_ural.c

199

uint16_t reg;

sys/dev/usb/wlan/if_ural.c

2030

ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val);

sys/dev/usb/wlan/if_ural.c

225

uint8_t reg;

sys/dev/usb/wlan/if_uralvar.h

119

uint8_t reg;

sys/dev/usb/wlan/if_urtw.c

178

uint32_t reg;

sys/dev/usb/wlan/if_urtw.c

1971

return urtw_ratetable[i].reg;

sys/dev/usb/wlan/if_urtw.c

2521

urtw_8225_write(sc, urtw_8225_rf_part1[i].reg,

sys/dev/usb/wlan/if_urtw.c

2553

urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg,

sys/dev/usb/wlan/if_urtw.c

2563

urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg,

sys/dev/usb/wlan/if_urtw.c

2903

urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg,

sys/dev/usb/wlan/if_urtw.c

2958

urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg,

sys/dev/usb/wlan/if_urtw.c

2967

urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg,

sys/dev/usb/wlan/if_urtw.c

3266

urtw_write8_m(sc, urtw_8225v2b_rf_part1[i].reg,

sys/dev/usb/wlan/if_urtw.c

3299

urtw_8225_write(sc, urtw_8225v2b_rf_part0[i].reg,

sys/dev/usb/wlan/if_zyd.c

1028

zyd_write16_m(sc, phyini[i].reg, phyini[i].val);

sys/dev/usb/wlan/if_zyd.c

1032

zyd_write16_m(sc, phy2230s[i].reg, phy2230s[i].val);

sys/dev/usb/wlan/if_zyd.c

1056

zyd_write16_m(sc, phypll[i].reg, phypll[i].val);

sys/dev/usb/wlan/if_zyd.c

1075

zyd_write16_m(sc, phy[i].reg, phy[i].val);

sys/dev/usb/wlan/if_zyd.c

1101

zyd_write16_m(sc, phy1[i].reg, phy1[i].val);

sys/dev/usb/wlan/if_zyd.c

1105

zyd_write16_m(sc, phyini[i].reg, phyini[i].val);

sys/dev/usb/wlan/if_zyd.c

1109

zyd_write16_m(sc, phy2230s[i].reg, phy2230s[i].val);

sys/dev/usb/wlan/if_zyd.c

1138

zyd_write16_m(sc, phy2[i].reg, phy2[i].val);

sys/dev/usb/wlan/if_zyd.c

1147

zyd_write16_m(sc, phy3[i].reg, phy3[i].val);

sys/dev/usb/wlan/if_zyd.c

1189

zyd_write16_m(sc, phy1[i].reg, phy1[i].val);

sys/dev/usb/wlan/if_zyd.c

1205

zyd_write16_m(sc, phy1[i].reg, phy1[i].val);

sys/dev/usb/wlan/if_zyd.c

1240

zyd_write16_m(sc, r[i].reg, r[i].val);

sys/dev/usb/wlan/if_zyd.c

1263

zyd_write16_m(sc, phyini_1[i].reg, phyini_1[i].val);

sys/dev/usb/wlan/if_zyd.c

1272

zyd_write16_m(sc, phyini_2[i].reg, phyini_2[i].val);

sys/dev/usb/wlan/if_zyd.c

1281

zyd_write16_m(sc, phyini_3[i].reg, phyini_3[i].val);

sys/dev/usb/wlan/if_zyd.c

1355

zyd_write16_m(sc, phyini[i].reg, phyini[i].val);

sys/dev/usb/wlan/if_zyd.c

1425

zyd_write16_m(sc, phyini[i].reg, phyini[i].val);

sys/dev/usb/wlan/if_zyd.c

1546

zyd_write16_m(sc, cmd[i].reg, cmd[i].val);

sys/dev/usb/wlan/if_zyd.c

1585

zyd_write16_m(sc, phyini[i].reg, phyini[i].val);

sys/dev/usb/wlan/if_zyd.c

1628

zyd_write16_m(sc, phyini[i].reg, phyini[i].val);

sys/dev/usb/wlan/if_zyd.c

1762

for (; phyp->reg != 0; phyp++)

sys/dev/usb/wlan/if_zyd.c

1763

zyd_write16_m(sc, phyp->reg, phyp->val);

sys/dev/usb/wlan/if_zyd.c

705

(((struct zyd_pair *)cmd->data) + i)->reg)

sys/dev/usb/wlan/if_zyd.c

837

zyd_read16(struct zyd_softc *sc, uint16_t reg, uint16_t *val)

sys/dev/usb/wlan/if_zyd.c

842

reg = htole16(reg);

sys/dev/usb/wlan/if_zyd.c

843

error = zyd_cmd(sc, ZYD_CMD_IORD, &reg, sizeof(reg), &tmp, sizeof(tmp),

sys/dev/usb/wlan/if_zyd.c

851

zyd_read32(struct zyd_softc *sc, uint16_t reg, uint32_t *val)

sys/dev/usb/wlan/if_zyd.c

857

regs[0] = htole16(ZYD_REG32_HI(reg));

sys/dev/usb/wlan/if_zyd.c

858

regs[1] = htole16(ZYD_REG32_LO(reg));

sys/dev/usb/wlan/if_zyd.c

867

zyd_write16(struct zyd_softc *sc, uint16_t reg, uint16_t val)

sys/dev/usb/wlan/if_zyd.c

871

pair.reg = htole16(reg);

sys/dev/usb/wlan/if_zyd.c

878

zyd_write32(struct zyd_softc *sc, uint16_t reg, uint32_t val)

sys/dev/usb/wlan/if_zyd.c

882

pair[0].reg = htole16(ZYD_REG32_HI(reg));

sys/dev/usb/wlan/if_zyd.c

884

pair[1].reg = htole16(ZYD_REG32_LO(reg));

sys/dev/usb/wlan/if_zyd.c

964

zyd_write16_m(sc, phyini[i].reg, phyini[i].val);

sys/dev/usb/wlan/if_zydreg.h

1113

uint16_t reg;

sys/dev/usb/wlan/if_zydreg.h

1115

#define ZYD_REG32_LO(reg) (reg)

sys/dev/usb/wlan/if_zydreg.h

1116

#define ZYD_REG32_HI(reg) \

sys/dev/usb/wlan/if_zydreg.h

1117

((reg) + ((((reg) & 0xf000) == 0x9000) ? 2 : 1))

sys/dev/usb/wlan/if_zydreg.h

1155

uint16_t reg;

sys/dev/usb/wlan/if_zydreg.h

1160

uint16_t reg;

sys/dev/vge/if_vge.c

358

vge_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/vge/if_vge.c

369

CSR_WRITE_1(sc, VGE_MIIADDR, reg);

sys/dev/vge/if_vge.c

392

vge_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/vge/if_vge.c

402

CSR_WRITE_1(sc, VGE_MIIADDR, reg);

sys/dev/vge/if_vgevar.h

214

#define CSR_WRITE_STREAM_4(sc, reg, val) \

sys/dev/vge/if_vgevar.h

215

bus_write_stream_4(sc->vge_res, reg, val)

sys/dev/vge/if_vgevar.h

216

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/vge/if_vgevar.h

217

bus_write_4(sc->vge_res, reg, val)

sys/dev/vge/if_vgevar.h

218

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/vge/if_vgevar.h

219

bus_write_2(sc->vge_res, reg, val)

sys/dev/vge/if_vgevar.h

220

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/vge/if_vgevar.h

221

bus_write_1(sc->vge_res, reg, val)

sys/dev/vge/if_vgevar.h

223

#define CSR_READ_4(sc, reg) \

sys/dev/vge/if_vgevar.h

224

bus_read_4(sc->vge_res, reg)

sys/dev/vge/if_vgevar.h

225

#define CSR_READ_2(sc, reg) \

sys/dev/vge/if_vgevar.h

226

bus_read_2(sc->vge_res, reg)

sys/dev/vge/if_vgevar.h

227

#define CSR_READ_1(sc, reg) \

sys/dev/vge/if_vgevar.h

228

bus_read_1(sc->vge_res, reg)

sys/dev/vge/if_vgevar.h

230

#define CSR_SETBIT_1(sc, reg, x) \

sys/dev/vge/if_vgevar.h

231

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))

sys/dev/vge/if_vgevar.h

232

#define CSR_SETBIT_2(sc, reg, x) \

sys/dev/vge/if_vgevar.h

233

CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))

sys/dev/vge/if_vgevar.h

234

#define CSR_SETBIT_4(sc, reg, x) \

sys/dev/vge/if_vgevar.h

235

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/vge/if_vgevar.h

237

#define CSR_CLRBIT_1(sc, reg, x) \

sys/dev/vge/if_vgevar.h

238

CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))

sys/dev/vge/if_vgevar.h

239

#define CSR_CLRBIT_2(sc, reg, x) \

sys/dev/vge/if_vgevar.h

240

CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))

sys/dev/vge/if_vgevar.h

241

#define CSR_CLRBIT_4(sc, reg, x) \

sys/dev/vge/if_vgevar.h

242

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/viawd/viawd.c

148

uint32_t pmbase, reg;

sys/dev/viawd/viawd.c

183

reg = viawd_read_4(sc, VIAWD_MEM_CTRL);

sys/dev/viawd/viawd.c

184

if (reg & VIAWD_MEM_CTRL_FIRED) {

sys/dev/viawd/viawd.c

188

viawd_write_4(sc, VIAWD_MEM_CTRL, reg);

sys/dev/viawd/viawd.c

206

uint32_t reg;

sys/dev/viawd/viawd.c

219

reg = viawd_read_4(sc, VIAWD_MEM_CTRL);

sys/dev/viawd/viawd.c

220

if (reg & VIAWD_MEM_CTRL_ENABLE) {

sys/dev/viawd/viawd.c

61

uint32_t reg;

sys/dev/viawd/viawd.c

63

reg = viawd_read_4(sc, VIAWD_MEM_CTRL);

sys/dev/viawd/viawd.c

65

reg |= VIAWD_MEM_CTRL_TRIGGER | VIAWD_MEM_CTRL_ENABLE;

sys/dev/viawd/viawd.c

67

reg &= ~VIAWD_MEM_CTRL_ENABLE;

sys/dev/viawd/viawd.c

68

viawd_write_4(sc, VIAWD_MEM_CTRL, reg);

sys/dev/vmd/vmd.c

174

vmd_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)

sys/dev/vmd/vmd.c

183

offset = ((b - sc->vmd_bus_start) << 20) + (s << 15) + (f << 12) + reg;

sys/dev/vmd/vmd.c

199

vmd_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg,

sys/dev/vmd/vmd.c

209

offset = ((b - sc->vmd_bus_start) << 20) + (s << 15) + (f << 12) + reg;

sys/dev/vnic/nicvf_main.c

1556

#define GET_RX_STATS(reg) \

sys/dev/vnic/nicvf_main.c

1557

nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | ((reg) << 3))

sys/dev/vnic/nicvf_main.c

1558

#define GET_TX_STATS(reg) \

sys/dev/vnic/nicvf_main.c

1559

nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | ((reg) << 3))

sys/dev/vnic/nicvf_queues.c

123

uint64_t reg, int bit_pos, int bits, int val)

sys/dev/vnic/nicvf_queues.c

133

reg_val = nicvf_queue_reg_read(nic, reg, qidx);

sys/dev/vnic/nicvf_queues.c

140

device_printf(nic->dev, "Poll on reg 0x%lx failed\n", reg);

sys/dev/vnic/nicvf_queues.c

2203

#define GET_RQ_STATS(reg) \

sys/dev/vnic/nicvf_queues.c

2205

(rq_idx << NIC_Q_NUM_SHIFT) | (reg << 3))

sys/dev/vnic/nicvf_queues.c

2217

#define GET_SQ_STATS(reg) \

sys/dev/vnic/nicvf_queues.c

2219

(sq_idx << NIC_Q_NUM_SHIFT) | (reg << 3))

sys/dev/vnic/thunder_bgx.c

244

bgx_poll_reg(struct bgx *bgx, uint8_t lmac, uint64_t reg, uint64_t mask,

sys/dev/vnic/thunder_bgx.c

251

reg_val = bgx_reg_read(bgx, lmac, reg);

sys/dev/vnic/thunder_bgx_fdt.c

207

uint32_t *reg;

sys/dev/vnic/thunder_bgx_fdt.c

261

err = OF_getencprop_alloc_multi(node, "reg", sizeof(*reg),

sys/dev/vnic/thunder_bgx_fdt.c

262

(void **)&reg);

sys/dev/vnic/thunder_bgx_fdt.c

264

free(reg, M_OFWPROP);

sys/dev/vnic/thunder_bgx_fdt.c

269

if ((BGX_DEVFN_0 + unit) == (reg[0] >> 8)) {

sys/dev/vnic/thunder_bgx_fdt.c

270

free(reg, M_OFWPROP);

sys/dev/vnic/thunder_bgx_fdt.c

274

free(reg, M_OFWPROP);

sys/dev/vnic/thunder_mdio.c

141

#define mdio_reg_read(sc, reg) \

sys/dev/vnic/thunder_mdio.c

142

bus_read_8((sc)->reg_base, (reg))

sys/dev/vnic/thunder_mdio.c

144

#define mdio_reg_write(sc, reg, val) \

sys/dev/vnic/thunder_mdio.c

145

bus_write_8((sc)->reg_base, (reg), (val))

sys/dev/vnic/thunder_mdio.c

212

thunder_mdio_c45_addr(struct thunder_mdio_softc *sc, int phy, int reg)

sys/dev/vnic/thunder_mdio.c

220

mdio_reg_write(sc, SMI_WR_DAT, reg & SMI_WR_DAT_DAT_MASK);

sys/dev/vnic/thunder_mdio.c

231

smi_cmd |= ((reg << SMI_CMD_PHY_REG_ADR_SHIFT) &

sys/dev/vnic/thunder_mdio.c

252

thunder_mdio_read(device_t dev, int phy, int reg)

sys/dev/vnic/thunder_mdio.c

273

err = thunder_mdio_c45_addr(sc, phy, reg);

sys/dev/vnic/thunder_mdio.c

277

reg = (reg >> 16) & 0x1F;

sys/dev/vnic/thunder_mdio.c

283

smi_cmd |= ((reg << SMI_CMD_PHY_REG_ADR_SHIFT) &

sys/dev/vnic/thunder_mdio.c

304

thunder_mdio_write(device_t dev, int phy, int reg, int data)

sys/dev/vnic/thunder_mdio.c

330

smi_cmd |= ((reg << SMI_CMD_PHY_REG_ADR_SHIFT) &

sys/dev/vr/if_vr.c

240

vr_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/vr/if_vr.c

248

CSR_WRITE_1(sc, VR_MIIADDR, reg);

sys/dev/vr/if_vr.c

257

device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg);

sys/dev/vr/if_vr.c

263

vr_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/vr/if_vr.c

271

CSR_WRITE_1(sc, VR_MIIADDR, reg);

sys/dev/vr/if_vr.c

282

reg);

sys/dev/vr/if_vrreg.h

749

#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->vr_res, reg, val)

sys/dev/vr/if_vrreg.h

750

#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->vr_res, reg, val)

sys/dev/vr/if_vrreg.h

751

#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->vr_res, reg, val)

sys/dev/vr/if_vrreg.h

753

#define CSR_READ_2(sc, reg) bus_read_2(sc->vr_res, reg)

sys/dev/vr/if_vrreg.h

754

#define CSR_READ_1(sc, reg) bus_read_1(sc->vr_res, reg)

sys/dev/vr/if_vrreg.h

756

#define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))

sys/dev/vr/if_vrreg.h

757

#define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))

sys/dev/vr/if_vrreg.h

759

#define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))

sys/dev/vr/if_vrreg.h

760

#define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))

sys/dev/vt/hw/vga/vt_vga.c

70

#define REG_READ1(sc, reg) \

sys/dev/vt/hw/vga/vt_vga.c

71

bus_space_read_1(sc->vga_reg_tag, sc->vga_reg_handle, reg)

sys/dev/vt/hw/vga/vt_vga.c

72

#define REG_WRITE1(sc, reg, val) \

sys/dev/vt/hw/vga/vt_vga.c

73

bus_space_write_1(sc->vga_reg_tag, sc->vga_reg_handle, reg, val)

sys/dev/vte/if_vte.c

168

vte_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/vte/if_vte.c

176

(phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT));

sys/dev/vte/if_vte.c

184

device_printf(sc->vte_dev, "phy read timeout : %d\n", reg);

sys/dev/vte/if_vte.c

192

vte_miibus_writereg(device_t dev, int phy, int reg, int val)

sys/dev/vte/if_vte.c

201

(phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT));

sys/dev/vte/if_vte.c

209

device_printf(sc->vte_dev, "phy write timeout : %d\n", reg);

sys/dev/vte/if_vtevar.h

149

#define CSR_WRITE_2(_sc, reg, val) \

sys/dev/vte/if_vtevar.h

150

bus_write_2((_sc)->vte_res, (reg), (val))

sys/dev/vte/if_vtevar.h

151

#define CSR_READ_2(_sc, reg) \

sys/dev/vte/if_vtevar.h

152

bus_read_2((_sc)->vte_res, (reg))

sys/dev/wpi/if_wpi.c

3801

uint32_t max, reg;

sys/dev/wpi/if_wpi.c

3819

reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 1);

sys/dev/wpi/if_wpi.c

3820

if (!(reg & PCIEM_LINK_CTL_ASPMC_L0S)) /* L0s Entry disabled. */

sys/dev/wpi/if_wpi.c

5141

uint32_t reg;

sys/dev/wpi/if_wpi.c

5155

reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 1);

sys/dev/wpi/if_wpi.c

5157

if (reg & PCIEM_LINK_CTL_ASPMC_L1) /* L1 Entry enabled. */

sys/dev/wpi/if_wpireg.h

1010

#define WPI_READ(sc, reg) \

sys/dev/wpi/if_wpireg.h

1011

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/wpi/if_wpireg.h

1013

#define WPI_WRITE(sc, reg, val) \

sys/dev/wpi/if_wpireg.h

1014

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/wpi/if_wpireg.h

1020

#define WPI_SETBITS(sc, reg, mask) \

sys/dev/wpi/if_wpireg.h

1021

WPI_WRITE(sc, reg, WPI_READ(sc, reg) | (mask))

sys/dev/wpi/if_wpireg.h

1023

#define WPI_CLRBITS(sc, reg, mask) \

sys/dev/wpi/if_wpireg.h

1024

WPI_WRITE(sc, reg, WPI_READ(sc, reg) & ~(mask))

sys/dev/xdma/controller/pl330.c

195

emit_mov(uint8_t *buf, uint32_t reg, uint32_t val)

sys/dev/xdma/controller/pl330.c

199

buf[1] = reg;

sys/dev/xdma/controller/pl330.c

428

uint32_t reg;

sys/dev/xdma/controller/pl330.c

430

reg = 0;

sys/dev/xdma/controller/pl330.c

434

reg |= CCR_SRC_BURST_SIZE_1;

sys/dev/xdma/controller/pl330.c

437

reg |= CCR_SRC_BURST_SIZE_2;

sys/dev/xdma/controller/pl330.c

440

reg |= CCR_SRC_BURST_SIZE_4;

sys/dev/xdma/controller/pl330.c

448

reg |= CCR_DST_BURST_SIZE_1;

sys/dev/xdma/controller/pl330.c

451

reg |= CCR_DST_BURST_SIZE_2;

sys/dev/xdma/controller/pl330.c

454

reg |= CCR_DST_BURST_SIZE_4;

sys/dev/xdma/controller/pl330.c

460

*addr |= reg;

sys/dev/xdma/controller/pl330.c

476

uint32_t reg;

sys/dev/xdma/controller/pl330.c

499

reg = CCR_DST_INC;

sys/dev/xdma/controller/pl330.c

501

reg = CCR_SRC_INC;

sys/dev/xdma/controller/pl330.c

502

reg |= (CCR_DST_PROT_PRIV);

sys/dev/xdma/controller/pl330.c

505

err = pl330_ccr_port_width(&sg[i], &reg);

sys/dev/xdma/controller/pl330.c

509

offs += emit_mov(&chan->ibuf[offs], R_CCR, reg);

sys/dev/xdma/controller/pl330.c

549

reg = (dbuf[1] << 24) | (dbuf[0] << 16);

sys/dev/xdma/controller/pl330.c

550

WRITE4(sc, DBGINST0, reg);

sys/dev/xdma/controller/pl330.c

551

reg = (dbuf[5] << 24) | (dbuf[4] << 16) | (dbuf[3] << 8) | dbuf[2];

sys/dev/xdma/controller/pl330.c

552

WRITE4(sc, DBGINST1, reg);

sys/dev/xdma/xdma.c

361

pcell_t reg[FDT_REG_CELLS * FDT_MEM_REGIONS];

sys/dev/xdma/xdma.c

376

if (reg_len <= 0 || reg_len > sizeof(reg))

sys/dev/xdma/xdma.c

379

if (OF_getprop(memory, "reg", reg, reg_len) <= 0)

sys/dev/xdma/xdma.c

383

regp = (pcell_t *)®

sys/dev/xen/cpu/xen_acpi_cpu.c

102

struct xen_pct_register *reg)

sys/dev/xen/cpu/xen_acpi_cpu.c

116

reg->descriptor = raw.descriptor;

sys/dev/xen/cpu/xen_acpi_cpu.c

117

reg->length = raw.length;

sys/dev/xen/cpu/xen_acpi_cpu.c

118

reg->space_id = raw.gas.SpaceId;

sys/dev/xen/cpu/xen_acpi_cpu.c

119

reg->bit_width = raw.gas.BitWidth;

sys/dev/xen/cpu/xen_acpi_cpu.c

120

reg->bit_offset = raw.gas.BitOffset;

sys/dev/xen/cpu/xen_acpi_cpu.c

121

reg->reserved = raw.gas.AccessWidth;

sys/dev/xen/cpu/xen_acpi_cpu.c

122

reg->address = raw.gas.Address;

sys/dev/xen/cpu/xen_acpi_cpu.c

311

cx_ptr->reg.space_id = gas.SpaceId;

sys/dev/xen/cpu/xen_acpi_cpu.c

312

cx_ptr->reg.bit_width = gas.BitWidth;

sys/dev/xen/cpu/xen_acpi_cpu.c

313

cx_ptr->reg.bit_offset = gas.BitOffset;

sys/dev/xen/cpu/xen_acpi_cpu.c

314

cx_ptr->reg.access_size = gas.AccessWidth;

sys/dev/xen/cpu/xen_acpi_cpu.c

315

cx_ptr->reg.address = gas.Address;

sys/dev/xen/pcifront/pcifront.c

591

int reg, int bytes)

sys/dev/xen/pcifront/pcifront.c

599

.offset = reg,

sys/dev/xen/pcifront/pcifront.c

607

bus, slot, func, reg, bytes, op.value, err);

sys/dev/xen/pcifront/pcifront.c

618

int reg, u_int32_t data, int bytes)

sys/dev/xen/pcifront/pcifront.c

626

.offset = reg,

sys/dev/xen/pcifront/pcifront.c

635

bus, slot, func, reg, bytes, data, err);

sys/dev/xilinx/axi_quad_spi.c

132

uint32_t reg;

sys/dev/xilinx/axi_quad_spi.c

150

reg = (CR_MASTER | CR_MSS | CR_RST_RX | CR_RST_TX);

sys/dev/xilinx/axi_quad_spi.c

151

WRITE4(sc, SPI_CR, reg);

sys/dev/xilinx/axi_quad_spi.c

154

reg = (CR_MASTER | CR_MSS | CR_SPE);

sys/dev/xilinx/axi_quad_spi.c

155

WRITE4(sc, SPI_CR, reg);

sys/dev/xilinx/axi_quad_spi.c

187

uint32_t reg;

sys/dev/xilinx/axi_quad_spi.c

203

reg = READ4(sc, SPI_SSR);

sys/dev/xilinx/axi_quad_spi.c

204

reg &= ~(1 << cs);

sys/dev/xilinx/axi_quad_spi.c

205

WRITE4(sc, SPI_SSR, reg);

sys/dev/xilinx/axi_quad_spi.c

214

reg = READ4(sc, SPI_SSR);

sys/dev/xilinx/axi_quad_spi.c

215

reg |= (1 << cs);

sys/dev/xilinx/axi_quad_spi.c

216

WRITE4(sc, SPI_SSR, reg);

sys/dev/xilinx/if_xae.c

100

PHY_WR(sc, MII_MMDAADR, reg); \

sys/dev/xilinx/if_xae.c

1126

reg = AXIDMA_RD4(sc, AXI_DMACR(AXIDMA_TX_CHAN));

sys/dev/xilinx/if_xae.c

1127

reg |= DMACR_IOC_IRQEN | DMACR_DLY_IRQEN | DMACR_ERR_IRQEN;

sys/dev/xilinx/if_xae.c

1128

AXIDMA_WR4(sc, AXI_DMACR(AXIDMA_TX_CHAN), reg);

sys/dev/xilinx/if_xae.c

1129

reg |= DMACR_RS;

sys/dev/xilinx/if_xae.c

1130

AXIDMA_WR4(sc, AXI_DMACR(AXIDMA_TX_CHAN), reg);

sys/dev/xilinx/if_xae.c

1133

reg = AXIDMA_RD4(sc, AXI_DMACR(AXIDMA_RX_CHAN));

sys/dev/xilinx/if_xae.c

1134

reg |= DMACR_IOC_IRQEN | DMACR_DLY_IRQEN | DMACR_ERR_IRQEN;

sys/dev/xilinx/if_xae.c

1135

AXIDMA_WR4(sc, AXI_DMACR(AXIDMA_RX_CHAN), reg);

sys/dev/xilinx/if_xae.c

1136

reg |= DMACR_RS;

sys/dev/xilinx/if_xae.c

1137

AXIDMA_WR4(sc, AXI_DMACR(AXIDMA_RX_CHAN), reg);

sys/dev/xilinx/if_xae.c

1173

uint32_t reg;

sys/dev/xilinx/if_xae.c

1222

reg = (MDIO_CLK_DIV_DEFAULT << MDIO_SETUP_CLK_DIV_S);

sys/dev/xilinx/if_xae.c

1223

reg |= MDIO_SETUP_ENABLE;

sys/dev/xilinx/if_xae.c

1224

XAE_WR4(sc, XAE_MDIO_SETUP, reg);

sys/dev/xilinx/if_xae.c

1309

uint32_t reg;

sys/dev/xilinx/if_xae.c

1330

reg = SPEED_1000;

sys/dev/xilinx/if_xae.c

1333

reg = SPEED_100;

sys/dev/xilinx/if_xae.c

1336

reg = SPEED_10;

sys/dev/xilinx/if_xae.c

1348

XAE_WR4(sc, XAE_SPEED, reg);

sys/dev/xilinx/if_xae.c

461

uint32_t reg;

sys/dev/xilinx/if_xae.c

469

reg = XAE_RD4(sc, XAE_FFC) & 0xffffff00;

sys/dev/xilinx/if_xae.c

470

reg |= cnt;

sys/dev/xilinx/if_xae.c

471

XAE_WR4(sc, XAE_FFC, reg);

sys/dev/xilinx/if_xae.c

473

reg = (ma[0]);

sys/dev/xilinx/if_xae.c

474

reg |= (ma[1] << 8);

sys/dev/xilinx/if_xae.c

475

reg |= (ma[2] << 16);

sys/dev/xilinx/if_xae.c

476

reg |= (ma[3] << 24);

sys/dev/xilinx/if_xae.c

477

XAE_WR4(sc, XAE_FFV(0), reg);

sys/dev/xilinx/if_xae.c

479

reg = ma[4];

sys/dev/xilinx/if_xae.c

480

reg |= ma[5] << 8;

sys/dev/xilinx/if_xae.c

481

XAE_WR4(sc, XAE_FFV(1), reg);

sys/dev/xilinx/if_xae.c

490

uint32_t reg;

sys/dev/xilinx/if_xae.c

500

reg = XAE_RD4(sc, XAE_FFC);

sys/dev/xilinx/if_xae.c

501

reg |= FFC_PM;

sys/dev/xilinx/if_xae.c

502

XAE_WR4(sc, XAE_FFC, reg);

sys/dev/xilinx/if_xae.c

504

reg = XAE_RD4(sc, XAE_FFC);

sys/dev/xilinx/if_xae.c

505

reg &= ~FFC_PM;

sys/dev/xilinx/if_xae.c

506

XAE_WR4(sc, XAE_FFC, reg);

sys/dev/xilinx/if_xae.c

514

reg = sc->macaddr[0];

sys/dev/xilinx/if_xae.c

515

reg |= (sc->macaddr[1] << 8);

sys/dev/xilinx/if_xae.c

516

reg |= (sc->macaddr[2] << 16);

sys/dev/xilinx/if_xae.c

517

reg |= (sc->macaddr[3] << 24);

sys/dev/xilinx/if_xae.c

518

XAE_WR4(sc, XAE_UAW0, reg);

sys/dev/xilinx/if_xae.c

520

reg = sc->macaddr[4];

sys/dev/xilinx/if_xae.c

521

reg |= (sc->macaddr[5] << 8);

sys/dev/xilinx/if_xae.c

522

XAE_WR4(sc, XAE_UAW1, reg);

sys/dev/xilinx/if_xae.c

549

uint32_t reg;

sys/dev/xilinx/if_xae.c

558

reg = XAE_RD4(sc, XAE_TC);

sys/dev/xilinx/if_xae.c

559

reg &= ~TC_TX;

sys/dev/xilinx/if_xae.c

560

XAE_WR4(sc, XAE_TC, reg);

sys/dev/xilinx/if_xae.c

563

reg = XAE_RD4(sc, XAE_RCW1);

sys/dev/xilinx/if_xae.c

564

reg &= ~RCW1_RX;

sys/dev/xilinx/if_xae.c

565

XAE_WR4(sc, XAE_RCW1, reg);

sys/dev/xilinx/if_xae.c

813

uint32_t reg;

sys/dev/xilinx/if_xae.c

819

reg = XAE_RD4(sc, XAE_MDIO_CTRL);

sys/dev/xilinx/if_xae.c

820

if (reg & MDIO_CTRL_READY)

sys/dev/xilinx/if_xae.c

834

xae_miibus_read_reg(device_t dev, int phy, int reg)

sys/dev/xilinx/if_xae.c

846

mii |= (reg << MDIO_TX_REGAD_S);

sys/dev/xilinx/if_xae.c

860

xae_miibus_write_reg(device_t dev, int phy, int reg, int val)

sys/dev/xilinx/if_xae.c

871

mii |= (reg << MDIO_TX_REGAD_S);

sys/dev/xilinx/if_xae.c

886

uint32_t reg;

sys/dev/xilinx/if_xae.c

892

reg = PHY_RD(sc, DP83867_CFG2);

sys/dev/xilinx/if_xae.c

893

reg &= ~CFG2_SPEED_OPT_ATTEMPT_CNT_M;

sys/dev/xilinx/if_xae.c

894

reg |= (CFG2_SPEED_OPT_ATTEMPT_CNT_4);

sys/dev/xilinx/if_xae.c

895

reg |= CFG2_INTERRUPT_POLARITY;

sys/dev/xilinx/if_xae.c

896

reg |= CFG2_SPEED_OPT_ENHANCED_EN;

sys/dev/xilinx/if_xae.c

897

reg |= CFG2_SPEED_OPT_10M_EN;

sys/dev/xilinx/if_xae.c

898

PHY_WR(sc, DP83867_CFG2, reg);

sys/dev/xilinx/if_xae.c

955

uint32_t reg;

sys/dev/xilinx/if_xae.c

98

#define WRITE_TI_EREG(sc, reg, data) { \

sys/dev/xilinx/xlnx_pcib.c

117

uint32_t reg;

sys/dev/xilinx/xlnx_pcib.c

119

reg = bus_read_4(sc->res, XLNX_PCIE_RPERRFRR);

sys/dev/xilinx/xlnx_pcib.c

121

if (reg & RPERRFRR_VALID) {

sys/dev/xilinx/xlnx_pcib.c

123

reg & RPERRFRR_REQ_ID_M);

sys/dev/xilinx/xlnx_pcib.c

212

int reg;

sys/dev/xilinx/xlnx_pcib.c

221

reg = bus_read_4(sc->res, msireg);

sys/dev/xilinx/xlnx_pcib.c

224

if (reg & (1 << i)) {

sys/dev/xilinx/xlnx_pcib.c

241

} while (reg != 0);

sys/dev/xilinx/xlnx_pcib.c

293

int reg;

sys/dev/xilinx/xlnx_pcib.c

299

reg = bus_read_4(sc->res[0], XLNX_PCIE_IDR);

sys/dev/xilinx/xlnx_pcib.c

300

bus_write_4(sc->res[0], XLNX_PCIE_IDR, reg);

sys/dev/xilinx/xlnx_pcib.c

310

reg = bus_read_4(sc->res[0], XLNX_PCIE_RPSCR);

sys/dev/xilinx/xlnx_pcib.c

311

reg |= RPSCR_BE;

sys/dev/xilinx/xlnx_pcib.c

312

bus_write_4(sc->res[0], XLNX_PCIE_RPSCR, reg);

sys/dev/xilinx/xlnx_pcib.c

315

reg = IMR_LINK_DOWN

sys/dev/xilinx/xlnx_pcib.c

332

bus_write_4(sc->res[0], XLNX_PCIE_IMR, reg);

sys/dev/xilinx/xlnx_pcib.c

427

u_int bus, u_int slot, u_int func, u_int reg)

sys/dev/xilinx/xlnx_pcib.c

439

(reg > PCIE_REGMAX))

sys/dev/xilinx/xlnx_pcib.c

458

u_int func, u_int reg, int bytes)

sys/dev/xilinx/xlnx_pcib.c

472

if (!xlnx_pcib_req_valid(sc, bus, slot, func, reg))

sys/dev/xilinx/xlnx_pcib.c

475

offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);

sys/dev/xilinx/xlnx_pcib.c

502

u_int func, u_int reg, uint32_t val, int bytes)

sys/dev/xilinx/xlnx_pcib.c

516

if (!xlnx_pcib_req_valid(sc, bus, slot, func, reg))

sys/dev/xilinx/xlnx_pcib.c

519

offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);

sys/dev/xilinx/xlnx_pcib.c

685

uint32_t reg;

sys/dev/xilinx/xlnx_pcib.c

699

reg = bus_read_4(sc->res, msireg);

sys/dev/xilinx/xlnx_pcib.c

701

reg &= ~(1 << irq);

sys/dev/xilinx/xlnx_pcib.c

703

reg |= (1 << irq);

sys/dev/xilinx/xlnx_pcib.c

704

bus_write_4(sc->res, msireg, reg);

sys/dev/xl/if_xl.c

412

xl_miibus_readreg(device_t dev, int phy, int reg)

sys/dev/xl/if_xl.c

421

return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg));

sys/dev/xl/if_xl.c

425

xl_miibus_writereg(device_t dev, int phy, int reg, int data)

sys/dev/xl/if_xl.c

434

mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data);

sys/dev/xl/if_xlreg.h

651

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/xl/if_xlreg.h

652

bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val)

sys/dev/xl/if_xlreg.h

653

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/xl/if_xlreg.h

654

bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val)

sys/dev/xl/if_xlreg.h

655

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/xl/if_xlreg.h

656

bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val)

sys/dev/xl/if_xlreg.h

658

#define CSR_READ_4(sc, reg) \

sys/dev/xl/if_xlreg.h

659

bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg)

sys/dev/xl/if_xlreg.h

660

#define CSR_READ_2(sc, reg) \

sys/dev/xl/if_xlreg.h

661

bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg)

sys/dev/xl/if_xlreg.h

662

#define CSR_READ_1(sc, reg) \

sys/dev/xl/if_xlreg.h

663

bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg)

sys/dev/xl/if_xlreg.h

665

#define CSR_BARRIER(sc, reg, length, flags) \

sys/dev/xl/if_xlreg.h

666

bus_space_barrier(sc->xl_btag, sc->xl_bhandle, reg, length, flags)

sys/fs/procfs/procfs_regs.c

79

struct reg r;

sys/gdb/gdb_main.c

876

uintmax_t reg;

sys/gdb/gdb_main.c

877

if (gdb_rx_varhex(&reg)) {

sys/gdb/gdb_main.c

882

gdb_tx_reg(reg);

sys/gdb/gdb_main.c

888

uintmax_t reg;

sys/gdb/gdb_main.c

890

if (gdb_rx_varhex(&reg) || gdb_rx_char() != '=' ||

sys/gdb/gdb_main.c

891

!gdb_rx_mem(val, gdb_cpu_regsz(reg))) {

sys/gdb/gdb_main.c

895

gdb_cpu_setreg(reg, val);

sys/i386/i386/db_trace.c

105

uint16_t *reg;

sys/i386/i386/db_trace.c

115

reg = (uint16_t *)&tfp->tf_cs;

sys/i386/i386/db_trace.c

118

reg = (uint16_t *)&tfp->tf_vm86_ds;

sys/i386/i386/db_trace.c

121

reg = (uint16_t *)&tfp->tf_vm86_es;

sys/i386/i386/db_trace.c

124

reg = (uint16_t *)&tfp->tf_vm86_fs;

sys/i386/i386/db_trace.c

128

reg = (uint16_t *)((uintptr_t)kdb_frame + off);

sys/i386/i386/db_trace.c

130

*valuep = *reg;

sys/i386/i386/db_trace.c

132

*reg = *valuep;

sys/i386/i386/db_trace.c

87

int *reg;

sys/i386/i386/db_trace.c

92

reg = (int *)((uintptr_t)kdb_frame + (db_expr_t)vp->valuep);

sys/i386/i386/db_trace.c

94

*valuep = *reg;

sys/i386/i386/db_trace.c

96

*reg = *valuep;

sys/i386/i386/exec_machdep.c

1006

fill_regs(struct thread *td, struct reg *regs)

sys/i386/i386/exec_machdep.c

1018

fill_frame_regs(struct trapframe *tp, struct reg *regs)

sys/i386/i386/exec_machdep.c

1042

set_regs(struct thread *td, struct reg *regs)

sys/i386/i386/k6_mem.c

101

u_int64_t reg;

sys/i386/i386/k6_mem.c

112

reg = rdmsr(UWCCR);

sys/i386/i386/k6_mem.c

114

u_int32_t one = (reg & (0xffffffff << (32 * d))) >> (32 * d);

sys/i386/i386/k6_mem.c

131

u_int64_t reg;

sys/i386/i386/k6_mem.c

165

reg = rdmsr(UWCCR);

sys/i386/i386/k6_mem.c

166

reg &= ~(0xffffffff << (32 * d));

sys/i386/i386/k6_mem.c

167

reg |= mtrr << (32 * d);

sys/i386/i386/k6_mem.c

168

wrmsr(UWCCR, reg);

sys/i386/i386/k6_mem.c

52

#define K6_REG_GET(reg, addr, mask, wc, uc) do { \

sys/i386/i386/k6_mem.c

53

addr = (reg) & 0xfffe0000; \

sys/i386/i386/k6_mem.c

54

mask = ((reg) & 0x1fffc) >> 2; \

sys/i386/i386/k6_mem.c

55

wc = ((reg) & 0x2) >> 1; \

sys/i386/i386/k6_mem.c

56

uc = (reg) & 0x1; \

sys/i386/i386/ptrace_machdep.c

56

struct segbasereg *reg;

sys/i386/i386/ptrace_machdep.c

59

KASSERT(*sizep == sizeof(*reg), ("%s: invalid size", __func__));

sys/i386/i386/ptrace_machdep.c

60

reg = buf;

sys/i386/i386/ptrace_machdep.c

61

reg->r_fsbase = get_segbase(&td->td_pcb->pcb_fsd);

sys/i386/i386/ptrace_machdep.c

62

reg->r_gsbase = get_segbase(&td->td_pcb->pcb_gsd);

sys/i386/i386/ptrace_machdep.c

64

*sizep = sizeof(*reg);

sys/i386/i386/ptrace_machdep.c

72

struct segbasereg *reg;

sys/i386/i386/ptrace_machdep.c

74

KASSERT(size == sizeof(*reg), ("%s: invalid size", __func__));

sys/i386/i386/ptrace_machdep.c

75

reg = buf;

sys/i386/i386/ptrace_machdep.c

77

fill_based_sd(&td->td_pcb->pcb_fsd, reg->r_fsbase);

sys/i386/i386/ptrace_machdep.c

79

fill_based_sd(&td->td_pcb->pcb_gsd, reg->r_gsbase);

sys/i386/include/asmacros.h

94

#define PCPU_ADDR(member, reg) \

sys/i386/include/asmacros.h

95

movl %fs:PC_PRVSPACE, reg ; \

sys/i386/include/asmacros.h

96

addl $PC_ ## member, reg

sys/i386/include/cpufunc.h

442

rxcr(u_int reg)

sys/i386/include/cpufunc.h

446

__asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));

sys/i386/include/cpufunc.h

451

load_xcr(u_int reg, uint64_t val)

sys/i386/include/cpufunc.h

457

__asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));

sys/i386/include/cpufunc.h

652

read_cyrix_reg(u_char reg)

sys/i386/include/cpufunc.h

654

outb(0x22, reg);

sys/i386/include/cpufunc.h

659

write_cyrix_reg(u_char reg, u_char data)

sys/i386/include/cpufunc.h

661

outb(0x22, reg);

sys/i386/include/xen/hypercall.h

219

int reg, unsigned long value)

sys/i386/include/xen/hypercall.h

221

return _hypercall2(int, set_debugreg, reg, value);

sys/i386/include/xen/hypercall.h

226

int reg)

sys/i386/include/xen/hypercall.h

228

return _hypercall1(unsigned long, get_debugreg, reg);

sys/i386/linux/linux.h

385

struct reg;

sys/i386/linux/linux.h

387

void bsd_to_linux_regset(const struct reg *b_reg,

sys/i386/linux/linux_machdep.c

596

bsd_to_linux_regset(const struct reg *b_reg,

sys/i386/linux/linux_ptrace_machdep.c

116

map_regs_to_linux(struct reg *bsd_r, struct linux_pt_reg *linux_r)

sys/i386/linux/linux_ptrace_machdep.c

138

map_regs_from_linux(struct reg *bsd_r, struct linux_pt_reg *linux_r)

sys/i386/linux/linux_ptrace_machdep.c

237

struct linux_pt_reg reg;

sys/i386/linux/linux_ptrace_machdep.c

242

struct reg bsd_reg;

sys/i386/linux/linux_ptrace_machdep.c

291

map_regs_to_linux(&u.bsd_reg, &r.reg);

sys/i386/linux/linux_ptrace_machdep.c

292

error = copyout(&r.reg, (void *)uap->data,

sys/i386/linux/linux_ptrace_machdep.c

293

sizeof(r.reg));

sys/i386/linux/linux_ptrace_machdep.c

298

error = copyin((void *)uap->data, &r.reg, sizeof(r.reg));

sys/i386/linux/linux_ptrace_machdep.c

300

map_regs_from_linux(&u.bsd_reg, &r.reg);

sys/i386/linux/linux_ptrace_machdep.c

420

map_regs_to_linux(&u.bsd_reg, &r.reg);

sys/i386/linux/linux_ptrace_machdep.c

422

error = copyout((char *)&r.reg + uap->addr,

sys/i386/linux/linux_ptrace_machdep.c

427

*(l_int *)((char *)&r.reg + uap->addr) =

sys/i386/linux/linux_ptrace_machdep.c

430

map_regs_from_linux(&u.bsd_reg, &r.reg);

sys/i386/pci/pci_cfgreg.c

175

pci_docfgregread(int domain, int bus, int slot, int func, int reg, int bytes)

sys/i386/pci/pci_cfgreg.c

178

return (pcireg_cfgread(bus, slot, func, reg, bytes));

sys/i386/pci/pci_cfgreg.c

185

return (pciereg_cfgread(region, bus, slot, func, reg,

sys/i386/pci/pci_cfgreg.c

190

return (pcireg_cfgread(bus, slot, func, reg, bytes));

sys/i386/pci/pci_cfgreg.c

199

pci_cfgregread(int domain, int bus, int slot, int func, int reg, int bytes)

sys/i386/pci/pci_cfgreg.c

208

if (reg == PCIR_INTLINE && bytes == 1) {

sys/i386/pci/pci_cfgreg.c

213

return (pci_docfgregread(domain, bus, slot, func, reg, bytes));

sys/i386/pci/pci_cfgreg.c

220

pci_cfgregwrite(int domain, int bus, int slot, int func, int reg, uint32_t data,

sys/i386/pci/pci_cfgreg.c

224

pcireg_cfgwrite(bus, slot, func, reg, data, bytes);

sys/i386/pci/pci_cfgreg.c

233

pciereg_cfgwrite(region, bus, slot, func, reg, data,

sys/i386/pci/pci_cfgreg.c

240

pcireg_cfgwrite(bus, slot, func, reg, data, bytes);

sys/i386/pci/pci_cfgreg.c

249

pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)

sys/i386/pci/pci_cfgreg.c

256

&& (unsigned)reg <= PCI_REGMAX

sys/i386/pci/pci_cfgreg.c

259

&& (reg & (bytes - 1)) == 0) {

sys/i386/pci/pci_cfgreg.c

265

| (func << 8) | (reg & ~0x03));

sys/i386/pci/pci_cfgreg.c

266

dataport = CONF1_DATA_PORT + (reg & 0x03);

sys/i386/pci/pci_cfgreg.c

271

dataport = 0xc000 | (slot << 8) | reg;

sys/i386/pci/pci_cfgreg.c

299

pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)

sys/i386/pci/pci_cfgreg.c

305

port = pci_cfgenable(bus, slot, func, reg, bytes);

sys/i386/pci/pci_cfgreg.c

325

pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)

sys/i386/pci/pci_cfgreg.c

330

port = pci_cfgenable(bus, slot, func, reg, bytes);

sys/i386/pci/pci_cfgreg.c

592

#define PCIE_PADDR(base, reg, bus, slot, func) \

sys/i386/pci/pci_cfgreg.c

597

((reg) & 0xfff)))

sys/i386/pci/pci_cfgreg.c

601

unsigned func, unsigned reg)

sys/i386/pci/pci_cfgreg.c

609

pa = PCIE_PADDR(region->base, reg, bus - region->minbus, slot, func);

sys/i386/pci/pci_cfgreg.c

651

unsigned func, unsigned reg, unsigned bytes)

sys/i386/pci/pci_cfgreg.c

656

if (slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)

sys/i386/pci/pci_cfgreg.c

660

va = pciereg_findaddr(region, bus, slot, func, reg);

sys/i386/pci/pci_cfgreg.c

683

unsigned func, unsigned reg, int data, unsigned bytes)

sys/i386/pci/pci_cfgreg.c

687

if (slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)

sys/i386/pci/pci_cfgreg.c

691

va = pciereg_findaddr(region, bus, slot, func, reg);

sys/i386/pci/pci_cfgreg.c

87

int reg, int bytes);

sys/i386/pci/pci_cfgreg.c

89

static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);

sys/i386/pci/pci_cfgreg.c

90

static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);

sys/i386/pci/pci_cfgreg.c

93

unsigned slot, unsigned func, unsigned reg, unsigned bytes);

sys/i386/pci/pci_cfgreg.c

95

unsigned slot, unsigned func, unsigned reg, int data,

sys/isa/rtc.h

116

int rtcin(int reg);

sys/isa/rtc.h

118

void writertc(int reg, u_char val);

sys/kern/kern_umtx.c

4324

static void umtx_shm_free_reg(struct umtx_shm_reg *reg);

sys/kern/kern_umtx.c

4330

struct umtx_shm_reg *reg, *reg1;

sys/kern/kern_umtx.c

4336

TAILQ_FOREACH_SAFE(reg, &d, ushm_reg_link, reg1) {

sys/kern/kern_umtx.c

4337

TAILQ_REMOVE(&d, reg, ushm_reg_link);

sys/kern/kern_umtx.c

4338

umtx_shm_free_reg(reg);

sys/kern/kern_umtx.c

4357

struct umtx_shm_reg *reg;

sys/kern/kern_umtx.c

4363

TAILQ_FOREACH(reg, reg_head, ushm_reg_link) {

sys/kern/kern_umtx.c

4364

KASSERT(reg->ushm_key.shared,

sys/kern/kern_umtx.c

4365

("non-shared key on reg %p %d", reg, reg->ushm_key.shared));

sys/kern/kern_umtx.c

4366

if (reg->ushm_key.info.shared.object ==

sys/kern/kern_umtx.c

4368

reg->ushm_key.info.shared.offset ==

sys/kern/kern_umtx.c

4370

KASSERT(reg->ushm_key.type == TYPE_SHM, ("TYPE_USHM"));

sys/kern/kern_umtx.c

4371

KASSERT(reg->ushm_refcnt != 0,

sys/kern/kern_umtx.c

4372

("reg %p refcnt 0 onlist", reg));

sys/kern/kern_umtx.c

4373

KASSERT((reg->ushm_flags & USHMF_LINKED) != 0,

sys/kern/kern_umtx.c

4374

("reg %p not linked", reg));

sys/kern/kern_umtx.c

4381

if (__predict_false(reg->ushm_refcnt == UINT_MAX))

sys/kern/kern_umtx.c

4383

reg->ushm_refcnt++;

sys/kern/kern_umtx.c

4384

*oreg = reg;

sys/kern/kern_umtx.c

4406

umtx_shm_free_reg(struct umtx_shm_reg *reg)

sys/kern/kern_umtx.c

4409

chgumtxcnt(reg->ushm_cred->cr_ruidinfo, -1, 0);

sys/kern/kern_umtx.c

4410

crfree(reg->ushm_cred);

sys/kern/kern_umtx.c

4411

shm_drop(reg->ushm_obj);

sys/kern/kern_umtx.c

4412

uma_zfree(umtx_shm_reg_zone, reg);

sys/kern/kern_umtx.c

4416

umtx_shm_unref_reg_locked(struct umtx_shm_reg *reg, bool linked_ref)

sys/kern/kern_umtx.c

4419

KASSERT(reg->ushm_refcnt != 0, ("ushm_reg %p refcnt 0", reg));

sys/kern/kern_umtx.c

4422

if ((reg->ushm_flags & USHMF_LINKED) == 0)

sys/kern/kern_umtx.c

4429

TAILQ_REMOVE(&umtx_shm_registry[reg->ushm_key.hash], reg,

sys/kern/kern_umtx.c

4431

LIST_REMOVE(reg, ushm_obj_link);

sys/kern/kern_umtx.c

4432

reg->ushm_flags &= ~USHMF_LINKED;

sys/kern/kern_umtx.c

4435

reg->ushm_refcnt--;

sys/kern/kern_umtx.c

4436

return (reg->ushm_refcnt == 0);

sys/kern/kern_umtx.c

4440

umtx_shm_unref_reg(struct umtx_shm_reg *reg, bool linked_ref)

sys/kern/kern_umtx.c

4452

object = reg->ushm_obj->shm_object;

sys/kern/kern_umtx.c

4458

dofree = umtx_shm_unref_reg_locked(reg, linked_ref);

sys/kern/kern_umtx.c

4461

umtx_shm_free_reg(reg);

sys/kern/kern_umtx.c

4474

struct umtx_shm_reg *reg, *reg1;

sys/kern/kern_umtx.c

4482

LIST_FOREACH_SAFE(reg, USHM_OBJ_UMTX(object), ushm_obj_link, reg1) {

sys/kern/kern_umtx.c

4483

if (umtx_shm_unref_reg_locked(reg, true)) {

sys/kern/kern_umtx.c

4484

TAILQ_INSERT_TAIL(&umtx_shm_reg_delfree, reg,

sys/kern/kern_umtx.c

4499

struct umtx_shm_reg *reg, *reg1;

sys/kern/kern_umtx.c

4523

reg = uma_zalloc(umtx_shm_reg_zone, M_WAITOK | M_ZERO);

sys/kern/kern_umtx.c

4524

bcopy(key, &reg->ushm_key, sizeof(*key));

sys/kern/kern_umtx.c

4525

reg->ushm_obj = shm;

sys/kern/kern_umtx.c

4526

reg->ushm_cred = crhold(cred);

sys/kern/kern_umtx.c

4527

error = shm_dotruncate(reg->ushm_obj, PAGE_SIZE);

sys/kern/kern_umtx.c

4529

umtx_shm_free_reg(reg);

sys/kern/kern_umtx.c

4538

umtx_shm_free_reg(reg);

sys/kern/kern_umtx.c

4545

umtx_shm_free_reg(reg);

sys/kern/kern_umtx.c

4548

TAILQ_INSERT_TAIL(&umtx_shm_registry[key->hash], reg, ushm_reg_link);

sys/kern/kern_umtx.c

4549

LIST_INSERT_HEAD(USHM_OBJ_UMTX(key->info.shared.object), reg,

sys/kern/kern_umtx.c

4551

reg->ushm_flags = USHMF_LINKED;

sys/kern/kern_umtx.c

4558

reg->ushm_refcnt = 2;

sys/kern/kern_umtx.c

4560

*res = reg;

sys/kern/kern_umtx.c

4604

struct umtx_shm_reg *reg;

sys/kern/kern_umtx.c

4618

umtx_shm_create_reg(td, &key, &reg) :

sys/kern/kern_umtx.c

4619

umtx_shm_find_reg(&key, &reg);

sys/kern/kern_umtx.c

4623

KASSERT(reg != NULL, ("no reg"));

sys/kern/kern_umtx.c

4625

umtx_shm_unref_reg(reg, true);

sys/kern/kern_umtx.c

4630

reg->ushm_obj, FFLAGS(O_RDWR));

sys/kern/kern_umtx.c

4633

error = shm_access(reg->ushm_obj, td->td_ucred,

sys/kern/kern_umtx.c

4639

shm_hold(reg->ushm_obj);

sys/kern/kern_umtx.c

4640

finit(fp, FFLAGS(O_RDWR), DTYPE_SHM, reg->ushm_obj,

sys/kern/kern_umtx.c

4646

umtx_shm_unref_reg(reg, false);

sys/kern/sys_process.c

102

proc_read_regs(struct thread *td, struct reg *regs)

sys/kern/sys_process.c

109

proc_write_regs(struct thread *td, struct reg *regs)

sys/kern/sys_process.c

611

struct reg reg;

sys/kern/sys_process.c

636

bzero(&r.reg, sizeof(r.reg));

sys/kern/sys_process.c

649

error = copyin(uap->addr, &r.reg, sizeof(r.reg));

sys/kern/sys_process.c

715

error = copyout(&r.reg, uap->addr, sizeof(r.reg));

sys/libkern/gsb_crc32.c

765

uint64_t reg;

sys/libkern/gsb_crc32.c

767

get_kernel_reg(ID_AA64ISAR0_EL1, &reg);

sys/libkern/gsb_crc32.c

768

if (ID_AA64ISAR0_CRC32_VAL(reg) >= ID_AA64ISAR0_CRC32_BASE)

sys/net/netmap.h

691

struct nmreq_register reg;

sys/net80211/ieee80211_ioctl.c

2185

struct ieee80211_regdomain_req *reg;

sys/net80211/ieee80211_ioctl.c

2196

reg = (struct ieee80211_regdomain_req *)

sys/net80211/ieee80211_ioctl.c

2199

if (reg == NULL) {

sys/net80211/ieee80211_ioctl.c

2204

error = copyin(ireq->i_data, reg, IEEE80211_REGDOMAIN_SIZE(nchans));

sys/net80211/ieee80211_ioctl.c

2207

if (reg->chaninfo.ic_nchans != nchans) {

sys/net80211/ieee80211_ioctl.c

2210

reg->chaninfo.ic_nchans, nchans);

sys/net80211/ieee80211_ioctl.c

2213

error = ieee80211_setregdomain(vap, reg);

sys/net80211/ieee80211_ioctl.c

2215

IEEE80211_FREE(reg, M_TEMP);

sys/net80211/ieee80211_regdomain.c

356

struct ieee80211_regdomain_req *reg)

sys/net80211/ieee80211_regdomain.c

363

if (reg->rd.location != 'I' && reg->rd.location != 'O' &&

sys/net80211/ieee80211_regdomain.c

364

reg->rd.location != ' ') {

sys/net80211/ieee80211_regdomain.c

366

"%s: invalid location 0x%x\n", __func__, reg->rd.location);

sys/net80211/ieee80211_regdomain.c

369

if (reg->rd.isocc[0] == '\0' || reg->rd.isocc[1] == '\0') {

sys/net80211/ieee80211_regdomain.c

372

reg->rd.isocc[0], reg->rd.isocc[1]);

sys/net80211/ieee80211_regdomain.c

375

if (reg->chaninfo.ic_nchans > IEEE80211_CHAN_MAX) {

sys/net80211/ieee80211_regdomain.c

378

reg->chaninfo.ic_nchans, IEEE80211_CHAN_MAX);

sys/net80211/ieee80211_regdomain.c

386

for (i = 0; i < reg->chaninfo.ic_nchans; i++) {

sys/net80211/ieee80211_regdomain.c

387

c = &reg->chaninfo.ic_chans[i];

sys/net80211/ieee80211_regdomain.c

417

error = ic->ic_setregdomain(ic, &reg->rd,

sys/net80211/ieee80211_regdomain.c

418

reg->chaninfo.ic_nchans, reg->chaninfo.ic_chans);

sys/net80211/ieee80211_regdomain.c

443

memcpy(&ic->ic_regdomain, &reg->rd, sizeof(reg->rd));

sys/net80211/ieee80211_regdomain.c

445

memcpy(ic->ic_channels, reg->chaninfo.ic_chans,

sys/net80211/ieee80211_regdomain.c

446

reg->chaninfo.ic_nchans * sizeof(struct ieee80211_channel));

sys/net80211/ieee80211_regdomain.c

447

ic->ic_nchans = reg->chaninfo.ic_nchans;

sys/netipsec/key.c

7417

struct secreg *reg, *newreg = NULL;

sys/netipsec/key.c

7434

LIST_FOREACH(reg, &V_regtree[mhp->msg->sadb_msg_satype], chain) {

sys/netipsec/key.c

7435

if (reg->so == so) {

sys/netipsec/key.c

7564

struct secreg *reg;

sys/netipsec/key.c

7576

LIST_FOREACH(reg, &V_regtree[i], chain) {

sys/netipsec/key.c

7577

if (reg->so == so && __LIST_CHAINED(reg)) {

sys/netipsec/key.c

7578

LIST_REMOVE(reg, chain);

sys/netipsec/key.c

7579

free(reg, M_IPSEC_SAR);

sys/netipsec/key.c

8682

struct secreg *reg;

sys/netipsec/key.c

8737

LIST_FOREACH(reg, &V_regtree[i], chain) {

sys/netipsec/key.c

8738

if (__LIST_CHAINED(reg)) {

sys/netipsec/key.c

8739

LIST_REMOVE(reg, chain);

sys/netipsec/key.c

8740

free(reg, M_IPSEC_SAR);

sys/powerpc/aim/mp_cpudep.c

309

register_t reg;

sys/powerpc/aim/mp_cpudep.c

347

: "=r"(reg) : "K"(SPR_HID0), "b"(bsp_state));

sys/powerpc/aim/mp_cpudep.c

350

: "=r"(reg) : "K"(SPR_HID1), "b"(bsp_state));

sys/powerpc/aim/mp_cpudep.c

62

register_t reg;

sys/powerpc/aim/mp_cpudep.c

81

: "=r"(reg) : "K"(SPR_HID4), "b"(bsp_state));

sys/powerpc/aim/mp_cpudep.c

84

: "=r"(reg) : "K"(SPR_HID5), "b"(bsp_state));

sys/powerpc/cpufreq/mpc85xx_jog.c

181

uint32_t reg;

sys/powerpc/cpufreq/mpc85xx_jog.c

197

reg = ccsr_read4(GUTS_PORPLLSR);

sys/powerpc/cpufreq/mpc85xx_jog.c

203

sc->high = PMJCR_GET_CORE_MULT(reg, sc->cpu);

sys/powerpc/cpufreq/mpc85xx_jog.c

249

uint32_t reg;

sys/powerpc/cpufreq/mpc85xx_jog.c

252

reg = ccsr_read4(GUTS_PMJCR);

sys/powerpc/cpufreq/mpc85xx_jog.c

253

reg &= ~PMJCR_CORE_MULT(PMJCR_RATIO_M, args->cpu);

sys/powerpc/cpufreq/mpc85xx_jog.c

254

reg |= PMJCR_CORE_MULT(args->mult, args->cpu);

sys/powerpc/cpufreq/mpc85xx_jog.c

256

reg &= ~(1 << (12 + args->cpu));

sys/powerpc/cpufreq/mpc85xx_jog.c

258

reg |= (1 << (12 + args->cpu));

sys/powerpc/cpufreq/mpc85xx_jog.c

260

ccsr_write4(GUTS_PMJCR, reg);

sys/powerpc/cpufreq/mpc85xx_jog.c

262

reg = ccsr_read4(GUTS_POWMGTCSR);

sys/powerpc/cpufreq/mpc85xx_jog.c

263

reg |= POWMGTCSR_JOG | POWMGTCSR_INT_MASK;

sys/powerpc/cpufreq/mpc85xx_jog.c

264

ccsr_write4(GUTS_POWMGTCSR, reg);

sys/powerpc/cpufreq/mpc85xx_jog.c

269

reg = ccsr_read4(GUTS_POWMGTCSR);

sys/powerpc/cpufreq/mpc85xx_jog.c

270

} while (reg & POWMGTCSR_JOG);

sys/powerpc/cpufreq/mpc85xx_jog.c

272

reg = ccsr_read4(GUTS_POWMGTCSR);

sys/powerpc/cpufreq/mpc85xx_jog.c

273

ccsr_write4(GUTS_POWMGTCSR, reg & ~POWMGTCSR_INT_MASK);

sys/powerpc/fpu/fpu_explode.c

206

fpu_explode(struct fpemu *fe, struct fpn *fp, int type, int reg)

sys/powerpc/fpu/fpu_explode.c

211

xspace = (u_int64_t *)&fe->fe_fpstate->fpr[reg].fpr;

sys/powerpc/fpu/fpu_explode.c

213

space = (u_int *)&fe->fe_fpstate->fpr[reg].fpr;

sys/powerpc/fpu/fpu_explode.c

256

reg));

sys/powerpc/include/asm.h

147

#define LOAD_ADDR(reg, var) \

sys/powerpc/include/asm.h

148

lis reg, var@highest; \

sys/powerpc/include/asm.h

149

ori reg, reg, var@higher; \

sys/powerpc/include/asm.h

150

rldicr reg, reg, 32, 31; \

sys/powerpc/include/asm.h

151

oris reg, reg, var@h; \

sys/powerpc/include/asm.h

152

ori reg, reg, var@l;

sys/powerpc/include/asm.h

167

#define LOAD_ADDR(reg, var) \

sys/powerpc/include/asm.h

168

lis reg, var@ha; \

sys/powerpc/include/asm.h

169

ori reg, reg, var@l;

sys/powerpc/include/pmc_mdep.h

24

#define mtpmr(reg, val) \

sys/powerpc/include/pmc_mdep.h

25

__asm __volatile("mtpmr %0,%1" : : "K"(reg), "r"(val))

sys/powerpc/include/pmc_mdep.h

26

#define mfpmr(reg) \

sys/powerpc/include/pmc_mdep.h

28

__asm __volatile("mfpmr %0,%1" : "=r"(val) : "K"(reg)); \

sys/powerpc/include/reg.h

65

int fill_regs(struct thread *, struct reg *);

sys/powerpc/include/reg.h

66

int set_regs(struct thread *, struct reg *);

sys/powerpc/include/reg.h

79

#define fill_fpregs32(td, reg) fill_fpregs(td,(struct fpreg *)reg)

sys/powerpc/include/reg.h

80

#define set_fpregs32(td, reg) set_fpregs(td,(struct fpreg *)reg)

sys/powerpc/include/reg.h

81

#define fill_dbregs32(td, reg) fill_dbregs(td,(struct dbreg *)reg)

sys/powerpc/include/reg.h

82

#define set_dbregs32(td, reg) set_dbregs(td,(struct dbreg *)reg)

sys/powerpc/include/spr.h

34

#define mtspr(reg, val) \

sys/powerpc/include/spr.h

35

__asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val))

sys/powerpc/include/spr.h

36

#define mfspr(reg) \

sys/powerpc/include/spr.h

38

__asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \

sys/powerpc/include/spr.h

46

#define mtspr64(reg,valhi,vallo,scratch) \

sys/powerpc/include/spr.h

61

: "=r"(scratch), "=r"(valhi) : "r"(vallo), "K"(reg), "r"(32), "r"(1))

sys/powerpc/include/spr.h

63

#define mfspr64upper(reg,scratch) \

sys/powerpc/include/spr.h

77

: "=r"(scratch), "=r"(val) : "K"(reg), "r"(32), "r"(1)); \

sys/powerpc/mpc85xx/fsl_diu.c

200

int reg;

sys/powerpc/mpc85xx/fsl_diu.c

205

reg = bus_read_4(sc->res[0], DIU_INT_STATUS);

sys/powerpc/mpc85xx/fsl_diu.c

206

bus_write_4(sc->res[0], DIU_INT_STATUS, reg);

sys/powerpc/mpc85xx/fsl_diu.c

241

int reg;

sys/powerpc/mpc85xx/fsl_diu.c

246

reg = bus_read_4(sc->res[0], DIU_DIU_MODE);

sys/powerpc/mpc85xx/fsl_diu.c

247

reg &= ~(DIU_MODE_M << DIU_MODE_S);

sys/powerpc/mpc85xx/fsl_diu.c

248

bus_write_4(sc->res[0], DIU_DIU_MODE, reg);

sys/powerpc/mpc85xx/fsl_diu.c

260

reg = ((sc->sc_info.fb_height) << DELTA_Y_S);

sys/powerpc/mpc85xx/fsl_diu.c

261

reg |= sc->sc_info.fb_width;

sys/powerpc/mpc85xx/fsl_diu.c

262

bus_write_4(sc->res[0], DIU_DISP_SIZE, reg);

sys/powerpc/mpc85xx/fsl_diu.c

264

reg = (panel->panel_hbp << BP_H_SHIFT);

sys/powerpc/mpc85xx/fsl_diu.c

265

reg |= (panel->panel_hpw << PW_H_SHIFT);

sys/powerpc/mpc85xx/fsl_diu.c

266

reg |= (panel->panel_hfp << FP_H_SHIFT);

sys/powerpc/mpc85xx/fsl_diu.c

267

bus_write_4(sc->res[0], DIU_HSYN_PARA, reg);

sys/powerpc/mpc85xx/fsl_diu.c

269

reg = (panel->panel_vbp << BP_V_SHIFT);

sys/powerpc/mpc85xx/fsl_diu.c

270

reg |= (panel->panel_vpw << PW_V_SHIFT);

sys/powerpc/mpc85xx/fsl_diu.c

271

reg |= (panel->panel_vfp << FP_V_SHIFT);

sys/powerpc/mpc85xx/fsl_diu.c

272

bus_write_4(sc->res[0], DIU_VSYN_PARA, reg);

sys/powerpc/mpc85xx/fsl_diu.c

296

reg = MAKE_PXLFMT(8, 8, 8, 8, 3, 2, 1, 0, 1, 3);

sys/powerpc/mpc85xx/fsl_diu.c

297

sc->sc_planes[0]->pixel_format = reg;

sys/powerpc/mpc85xx/fsl_diu.c

301

reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 12));

sys/powerpc/mpc85xx/fsl_diu.c

302

sc->sc_planes[0]->source_size = htole32(reg);

sys/powerpc/mpc85xx/fsl_diu.c

304

reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 16));

sys/powerpc/mpc85xx/fsl_diu.c

305

sc->sc_planes[0]->aoi_size = htole32(reg);

sys/powerpc/mpc85xx/fsl_diu.c

313

reg = 255 << 16 | 255 << 8 | 255;

sys/powerpc/mpc85xx/fsl_diu.c

314

sc->sc_planes[0]->chroma_key_min = htole32(reg);

sys/powerpc/mpc85xx/fsl_diu.c

322

reg = bus_read_4(sc->res[0], DIU_DIU_MODE);

sys/powerpc/mpc85xx/fsl_diu.c

323

reg &= ~(DIU_MODE_M << DIU_MODE_S);

sys/powerpc/mpc85xx/fsl_diu.c

324

reg |= (DIU_MODE_NORMAL << DIU_MODE_S);

sys/powerpc/mpc85xx/fsl_diu.c

325

bus_write_4(sc->res[0], DIU_DIU_MODE, reg);

sys/powerpc/mpc85xx/lbc.c

371

pcell_t *reg, *regptr;

sys/powerpc/mpc85xx/lbc.c

381

(void **)&reg);

sys/powerpc/mpc85xx/lbc.c

388

regptr = reg;

sys/powerpc/mpc85xx/lbc.c

390

bank = fdt_data_get((void *)reg, 1);

sys/powerpc/mpc85xx/lbc.c

392

reg += 1;

sys/powerpc/mpc85xx/lbc.c

398

start |= reg[j];

sys/powerpc/mpc85xx/lbc.c

402

count |= reg[addr_cells + j - 1];

sys/powerpc/mpc85xx/lbc.c

404

reg += addr_cells - 1 + size_cells;

sys/powerpc/mpc85xx/pci_mpc85xx.c

450

u_int reg, int bytes)

sys/powerpc/mpc85xx/pci_mpc85xx.c

458

addr |= reg & 0xfc;

sys/powerpc/mpc85xx/pci_mpc85xx.c

460

addr |= (reg & 0xf00) << 16;

sys/powerpc/mpc85xx/pci_mpc85xx.c

468

REG_CFG_DATA + (reg & 3));

sys/powerpc/mpc85xx/pci_mpc85xx.c

472

REG_CFG_DATA + (reg & 2)));

sys/powerpc/mpc85xx/pci_mpc85xx.c

488

u_int reg, uint32_t data, int bytes)

sys/powerpc/mpc85xx/pci_mpc85xx.c

496

addr |= reg & 0xfc;

sys/powerpc/mpc85xx/pci_mpc85xx.c

498

addr |= (reg & 0xf00) << 16;

sys/powerpc/mpc85xx/pci_mpc85xx.c

506

REG_CFG_DATA + (reg & 3), data);

sys/powerpc/mpc85xx/pci_mpc85xx.c

510

REG_CFG_DATA + (reg & 2), htole16(data));

sys/powerpc/mpc85xx/pci_mpc85xx.c

560

u_int reg, int bytes)

sys/powerpc/mpc85xx/pci_mpc85xx.c

568

return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes));

sys/powerpc/mpc85xx/pci_mpc85xx.c

573

u_int reg, uint32_t val, int bytes)

sys/powerpc/mpc85xx/pci_mpc85xx.c

580

fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes);

sys/powerpc/mpc85xx/pci_mpc85xx.c

872

vm_offset_t reg;

sys/powerpc/mpc85xx/pci_mpc85xx.c

880

uint32_t reg;

sys/powerpc/mpc85xx/pci_mpc85xx.c

883

reg = ccsr_read4(ccsrbar_va + data->reg);

sys/powerpc/mpc85xx/pci_mpc85xx.c

885

while (reg != 0) {

sys/powerpc/mpc85xx/pci_mpc85xx.c

886

if (reg & 1)

sys/powerpc/mpc85xx/pci_mpc85xx.c

888

reg >>= 1;

sys/powerpc/mpc85xx/pci_mpc85xx.c

928

irq->reg = sc->sc_base + 16 * i;

sys/powerpc/mpc85xx/platform_mpc85xx.c

306

pcell_t reg;

sys/powerpc/mpc85xx/platform_mpc85xx.c

318

if (OF_getencprop(node, "reg", &reg, sizeof(reg)) > 0)

sys/powerpc/mpc85xx/platform_mpc85xx.c

319

cpuref->cr_hwref = reg;

sys/powerpc/mpc85xx/platform_mpc85xx.c

391

uint32_t reg;

sys/powerpc/mpc85xx/platform_mpc85xx.c

399

reg = ccsr_read4(OCP85XX_COREDISR);

sys/powerpc/mpc85xx/platform_mpc85xx.c

402

if ((reg & (1 << cpuid)) != 0) {

sys/powerpc/mpc85xx/platform_mpc85xx.c

430

reg = ccsr_read4(brr);

sys/powerpc/mpc85xx/platform_mpc85xx.c

431

if ((reg & (1 << cpuid)) != 0) {

sys/powerpc/mpc85xx/platform_mpc85xx.c

453

reg = ccsr_read4(OCP85XX_DDR1_CS0_CONFIG);

sys/powerpc/mpc85xx/platform_mpc85xx.c

454

if (reg & (1 << 29))

sys/powerpc/mpc85xx/platform_mpc85xx.c

475

reg = ccsr_read4(CCSR_CTBCKSELR);

sys/powerpc/mpc85xx/platform_mpc85xx.c

476

ccsr_write4(CCSR_CTBCKSELR, reg & ~(1 << pc->pc_cpuid));

sys/powerpc/mpc85xx/platform_mpc85xx.c

479

reg = ccsr_read4(CCSR_CTBENR);

sys/powerpc/mpc85xx/platform_mpc85xx.c

480

ccsr_write4(CCSR_CTBENR, reg | (1 << pc->pc_cpuid));

sys/powerpc/mpc85xx/platform_mpc85xx.c

493

reg = ccsr_read4(brr);

sys/powerpc/mpc85xx/platform_mpc85xx.c

494

ccsr_write4(brr, reg | (1 << cpuid));

sys/powerpc/ofw/ofw_pcib_pci.c

131

struct ofw_pci_register reg;

sys/powerpc/ofw/ofw_pcib_pci.c

142

bzero(&reg, sizeof(reg));

sys/powerpc/ofw/ofw_pcib_pci.c

143

reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |

sys/powerpc/ofw/ofw_pcib_pci.c

147

intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), ii, &reg,

sys/powerpc/ofw/ofw_pcib_pci.c

148

sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr),

sys/powerpc/powermac/atibl.c

165

atibl_pll_rreg(struct atibl_softc *sc, uint32_t reg)

sys/powerpc/powermac/atibl.c

169

bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, (reg & 0x3f));

sys/powerpc/powermac/atibl.c

186

atibl_pll_wreg(struct atibl_softc *sc, uint32_t reg, uint32_t val)

sys/powerpc/powermac/atibl.c

191

((reg & 0x3f) | RADEON_PLL_WR_EN));

sys/powerpc/powermac/cpcht.c

175

u_int32_t reg[3];

sys/powerpc/powermac/cpcht.c

181

if (OF_getencprop(node, "reg", reg, sizeof(reg)) < 12)

sys/powerpc/powermac/cpcht.c

187

sc->sc_data = (vm_offset_t)pmap_mapdev(reg[1], reg[2]);

sys/powerpc/powermac/cpcht.c

314

cpcht_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,

sys/powerpc/powermac/cpcht.c

322

(((((slot & 0x1f) << 3) | (func & 0x07)) << 8) | reg);

sys/powerpc/powermac/cpcht.c

347

u_int reg, u_int32_t val, int width)

sys/powerpc/powermac/cpcht.c

354

(((((slot & 0x1f) << 3) | (func & 0x07)) << 8) | reg);

sys/powerpc/powermac/cuda.c

146

uint8_t reg;

sys/powerpc/powermac/cuda.c

200

reg = cuda_read_reg(sc, vDirB);

sys/powerpc/powermac/cuda.c

201

reg |= 0x30; /* register B bits 4 and 5: outputs */

sys/powerpc/powermac/cuda.c

202

cuda_write_reg(sc, vDirB, reg);

sys/powerpc/powermac/cuda.c

204

reg = cuda_read_reg(sc, vDirB);

sys/powerpc/powermac/cuda.c

205

reg &= 0xf7; /* register B bit 3: input */

sys/powerpc/powermac/cuda.c

206

cuda_write_reg(sc, vDirB, reg);

sys/powerpc/powermac/cuda.c

208

reg = cuda_read_reg(sc, vACR);

sys/powerpc/powermac/cuda.c

209

reg &= ~vSR_OUT; /* make sure SR is set to IN */

sys/powerpc/powermac/cuda.c

210

cuda_write_reg(sc, vACR, reg);

sys/powerpc/powermac/cuda.c

292

uint8_t reg;

sys/powerpc/powermac/cuda.c

294

reg = cuda_read_reg(sc, vBufB);

sys/powerpc/powermac/cuda.c

295

reg |= (vPB4 | vPB5);

sys/powerpc/powermac/cuda.c

296

cuda_write_reg(sc, vBufB, reg);

sys/powerpc/powermac/cuda.c

302

uint8_t reg;

sys/powerpc/powermac/cuda.c

304

reg = cuda_read_reg(sc, vBufB);

sys/powerpc/powermac/cuda.c

305

reg &= ~vPB5;

sys/powerpc/powermac/cuda.c

306

cuda_write_reg(sc, vBufB, reg);

sys/powerpc/powermac/cuda.c

312

uint8_t reg;

sys/powerpc/powermac/cuda.c

314

reg = cuda_read_reg(sc, vBufB);

sys/powerpc/powermac/cuda.c

315

reg |= vPB5;

sys/powerpc/powermac/cuda.c

316

cuda_write_reg(sc, vBufB, reg);

sys/powerpc/powermac/cuda.c

322

uint8_t reg;

sys/powerpc/powermac/cuda.c

324

reg = cuda_read_reg(sc, vACR);

sys/powerpc/powermac/cuda.c

325

reg &= ~vSR_OUT;

sys/powerpc/powermac/cuda.c

326

cuda_write_reg(sc, vACR, reg);

sys/powerpc/powermac/cuda.c

332

uint8_t reg;

sys/powerpc/powermac/cuda.c

334

reg = cuda_read_reg(sc, vACR);

sys/powerpc/powermac/cuda.c

335

reg |= vSR_OUT;

sys/powerpc/powermac/cuda.c

336

cuda_write_reg(sc, vACR, reg);

sys/powerpc/powermac/cuda.c

342

uint8_t reg;

sys/powerpc/powermac/cuda.c

344

reg = cuda_read_reg(sc, vBufB);

sys/powerpc/powermac/cuda.c

345

reg ^= vPB4;

sys/powerpc/powermac/cuda.c

346

cuda_write_reg(sc, vBufB, reg);

sys/powerpc/powermac/cuda.c

352

uint8_t reg;

sys/powerpc/powermac/cuda.c

354

reg = cuda_read_reg(sc, vBufB);

sys/powerpc/powermac/cuda.c

355

reg |= vPB4;

sys/powerpc/powermac/cuda.c

356

cuda_write_reg(sc, vBufB, reg);

sys/powerpc/powermac/cuda.c

527

uint8_t reg;

sys/powerpc/powermac/cuda.c

535

reg = cuda_read_reg(sc, vIFR);

sys/powerpc/powermac/cuda.c

536

if ((reg & vSR_INT) != vSR_INT) {

sys/powerpc/powermac/fcu.c

113

static int fcu_write(device_t dev, uint32_t addr, uint8_t reg, uint8_t *buf,

sys/powerpc/powermac/fcu.c

115

static int fcu_read_1(device_t dev, uint32_t addr, uint8_t reg, uint8_t *data);

sys/powerpc/powermac/fcu.c

134

fcu_write(device_t dev, uint32_t addr, uint8_t reg, uint8_t *buff,

sys/powerpc/powermac/fcu.c

145

buf[0] = reg;

sys/powerpc/powermac/fcu.c

162

fcu_read_1(device_t dev, uint32_t addr, uint8_t reg, uint8_t *data)

sys/powerpc/powermac/fcu.c

168

{ addr, IIC_M_WR | IIC_M_NOSTOP, 1, &reg },

sys/powerpc/powermac/fcu.c

267

uint8_t reg;

sys/powerpc/powermac/fcu.c

278

reg = FCU_RPM_SET(fan->id);

sys/powerpc/powermac/fcu.c

288

if (fcu_write(sc->sc_dev, sc->sc_addr, reg, buf, 2) < 0)

sys/powerpc/powermac/fcu.c

297

uint8_t reg;

sys/powerpc/powermac/fcu.c

307

reg = FCU_RPM_AVAILABLE;

sys/powerpc/powermac/fcu.c

308

if (fcu_read_1(sc->sc_dev, sc->sc_addr, reg, &avail) < 0)

sys/powerpc/powermac/fcu.c

316

reg = FCU_RPM_FAIL;

sys/powerpc/powermac/fcu.c

317

if (fcu_read_1(sc->sc_dev, sc->sc_addr, reg, &fail) < 0)

sys/powerpc/powermac/fcu.c

325

reg = FCU_RPM_ACTIVE;

sys/powerpc/powermac/fcu.c

326

if (fcu_read_1(sc->sc_dev, sc->sc_addr, reg, &active) < 0)

sys/powerpc/powermac/fcu.c

333

reg = FCU_RPM_READ(fan->id);

sys/powerpc/powermac/fcu.c

341

if (fcu_read_1(sc->sc_dev, sc->sc_addr, reg, buff) < 0)

sys/powerpc/powermac/fcu.c

352

uint8_t reg;

sys/powerpc/powermac/fcu.c

363

reg = FCU_PWM_SGET(fan->id);

sys/powerpc/powermac/fcu.c

376

if (fcu_write(sc->sc_dev, sc->sc_addr, reg, buf, 1) < 0)

sys/powerpc/powermac/fcu.c

384

uint8_t reg;

sys/powerpc/powermac/fcu.c

393

reg = FCU_PWM_AVAILABLE;

sys/powerpc/powermac/fcu.c

394

if (fcu_read_1(sc->sc_dev, sc->sc_addr, reg, &avail) < 0)

sys/powerpc/powermac/fcu.c

402

reg = FCU_PWM_FAIL;

sys/powerpc/powermac/fcu.c

403

if (fcu_read_1(sc->sc_dev, sc->sc_addr, reg, &fail) < 0)

sys/powerpc/powermac/fcu.c

410

reg = FCU_PWM_ACTIVE;

sys/powerpc/powermac/fcu.c

411

if (fcu_read_1(sc->sc_dev, sc->sc_addr, reg, &active) < 0)

sys/powerpc/powermac/fcu.c

418

reg = FCU_PWM_SGET(fan->id);

sys/powerpc/powermac/fcu.c

425

if (fcu_read_1(sc->sc_dev, sc->sc_addr, reg, buf) < 0)

sys/powerpc/powermac/fcu.c

431

reg = FCU_PWM_RPM(fan->id);

sys/powerpc/powermac/fcu.c

432

if (fcu_read_1(sc->sc_dev, sc->sc_addr, reg, buf) < 0)

sys/powerpc/powermac/grackle.c

140

grackle_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,

sys/powerpc/powermac/grackle.c

148

caoff = sc->sc_data + (reg & 0x03);

sys/powerpc/powermac/grackle.c

150

if (grackle_enable_config(sc, bus, slot, func, reg) != 0) {

sys/powerpc/powermac/grackle.c

181

u_int reg, u_int32_t val, int width)

sys/powerpc/powermac/grackle.c

187

caoff = sc->sc_data + (reg & 0x03);

sys/powerpc/powermac/grackle.c

189

if (grackle_enable_config(sc, bus, slot, func, reg)) {

sys/powerpc/powermac/grackle.c

210

u_int func, u_int reg)

sys/powerpc/powermac/grackle.c

218

cfgval = (bus << 16) | (slot << 11) | (func << 8) | (reg & 0xFC)

sys/powerpc/powermac/hrowpic.c

101

reg += HPIC_1ST_OFFSET;

sys/powerpc/powermac/hrowpic.c

103

return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));

sys/powerpc/powermac/hrowpic.c

107

hrowpic_write_reg(struct hrowpic_softc *sc, u_int reg, u_int bank,

sys/powerpc/powermac/hrowpic.c

112

reg += HPIC_1ST_OFFSET;

sys/powerpc/powermac/hrowpic.c

114

bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);

sys/powerpc/powermac/hrowpic.c

117

bus_space_read_4(sc->sc_bt, sc->sc_bh, reg);

sys/powerpc/powermac/hrowpic.c

214

uint32_t reg;

sys/powerpc/powermac/hrowpic.c

220

reg = hrowpic_read_reg(sc, HPIC_STATUS, HPIC_PRIMARY);

sys/powerpc/powermac/hrowpic.c

221

mask = (mask << 32) | reg;

sys/powerpc/powermac/hrowpic.c

98

hrowpic_read_reg(struct hrowpic_softc *sc, u_int reg, u_int bank)

sys/powerpc/powermac/kiic.c

214

phandle_t reg;

sys/powerpc/powermac/kiic.c

215

if (OF_getprop(node, "reg", &reg, sizeof(reg)) > 0)

sys/powerpc/powermac/kiic.c

216

sc->sc_i2c_base = reg << 8;

sys/powerpc/powermac/kiic.c

249

kiic_writereg(struct kiic_softc *sc, u_int reg, u_int val)

sys/powerpc/powermac/kiic.c

251

bus_write_4(sc->sc_reg, sc->sc_regstep * reg, val);

sys/powerpc/powermac/kiic.c

256

kiic_readreg(struct kiic_softc *sc, u_int reg)

sys/powerpc/powermac/kiic.c

258

return bus_read_4(sc->sc_reg, sc->sc_regstep * reg) & 0xff;

sys/powerpc/powermac/macio.c

250

struct macio_reg *reg, *regp;

sys/powerpc/powermac/macio.c

255

nreg = OF_getprop_alloc_multi(devnode, "reg", sizeof(*reg), (void **)&reg);

sys/powerpc/powermac/macio.c

268

if (reg[0].mr_base == 0) {

sys/powerpc/powermac/macio.c

283

reg[0] = regp[0];

sys/powerpc/powermac/macio.c

284

reg[1].mr_base = regp[1].mr_base;

sys/powerpc/powermac/macio.c

285

reg[2].mr_base = regp[1].mr_base + reg[1].mr_size;

sys/powerpc/powermac/macio.c

291

reg[i].mr_base, reg[i].mr_base + reg[i].mr_size,

sys/powerpc/powermac/macio.c

292

reg[i].mr_size);

sys/powerpc/powermac/macio.c

329

u_int reg[3];

sys/powerpc/powermac/macio.c

340

reg, sizeof(reg)) < (ssize_t)sizeof(reg)) {

sys/powerpc/powermac/macio.c

347

sc->sc_base = reg[2];

sys/powerpc/powermac/pmu.c

339

uint8_t reg;

sys/powerpc/powermac/pmu.c

381

reg = PMU_DEFAULTS;

sys/powerpc/powermac/pmu.c

382

pmu_send(sc, PMU_SET_IMASK, 1, &reg, 16, resp);

sys/powerpc/powermac/pmu.c

656

uint8_t reg;

sys/powerpc/powermac/pmu.c

658

reg = pmu_read_reg(sc, vACR);

sys/powerpc/powermac/pmu.c

659

reg &= ~vSR_OUT;

sys/powerpc/powermac/pmu.c

660

reg |= 0x0c;

sys/powerpc/powermac/pmu.c

661

pmu_write_reg(sc, vACR, reg);

sys/powerpc/powermac/pmu.c

667

uint8_t reg;

sys/powerpc/powermac/pmu.c

669

reg = pmu_read_reg(sc, vACR);

sys/powerpc/powermac/pmu.c

670

reg |= vSR_OUT;

sys/powerpc/powermac/pmu.c

671

reg |= 0x0c;

sys/powerpc/powermac/pmu.c

672

pmu_write_reg(sc, vACR, reg);

sys/powerpc/powermac/pmu.c

678

uint8_t reg;

sys/powerpc/powermac/pmu.c

680

reg = pmu_read_reg(sc, vBufB);

sys/powerpc/powermac/pmu.c

681

reg &= ~vPB4;

sys/powerpc/powermac/pmu.c

682

pmu_write_reg(sc, vBufB, reg);

sys/powerpc/powermac/pmu.c

688

uint8_t reg;

sys/powerpc/powermac/pmu.c

690

reg = pmu_read_reg(sc, vBufB);

sys/powerpc/powermac/pmu.c

691

reg |= vPB4;

sys/powerpc/powermac/pmu.c

692

pmu_write_reg(sc, vBufB, reg);

sys/powerpc/powermac/pmu.c

888

uint8_t reg;

sys/powerpc/powermac/pmu.c

892

reg = batt + 1;

sys/powerpc/powermac/pmu.c

895

len = pmu_send(sc, PMU_SMART_BATTERY_STATE, 1, &reg, 16, resp);

sys/powerpc/powermac/smu.c

100

cell_t reg;

sys/powerpc/powermac/smu.c

1094

cmd.data[0] = sens->reg;

sys/powerpc/powermac/smu.c

1226

OF_getprop(child, "reg", &sens->reg, sizeof(cell_t));

sys/powerpc/powermac/smu.c

677

cmd.data[1] = fan->reg;

sys/powerpc/powermac/smu.c

707

cmd.data[1] = fan->reg;

sys/powerpc/powermac/smu.c

717

cmd.data[1] = 1 << fan->reg;

sys/powerpc/powermac/smu.c

718

cmd.data[2 + 2*fan->reg] = (rpm >> 8) & 0xff;

sys/powerpc/powermac/smu.c

719

cmd.data[3 + 2*fan->reg] = rpm & 0xff;

sys/powerpc/powermac/smu.c

742

cmd.data[1] = fan->reg;

sys/powerpc/powermac/smu.c

760

rpm = (cmd.data[fan->reg*2+1] << 8) | cmd.data[fan->reg*2+2];

sys/powerpc/powermac/smu.c

77

cell_t reg;

sys/powerpc/powermac/smu.c

788

cmd.data[1] = fan->reg;

sys/powerpc/powermac/smu.c

800

cmd.data[1] = 1 << fan->reg;

sys/powerpc/powermac/smu.c

801

cmd.data[2 + 2*fan->reg] = (pwm >> 8) & 0xff;

sys/powerpc/powermac/smu.c

802

cmd.data[3 + 2*fan->reg] = pwm & 0xff;

sys/powerpc/powermac/smu.c

823

cmd.data[1] = fan->reg;

sys/powerpc/powermac/smu.c

841

*rpm = (cmd.data[fan->reg*2+1] << 8) | cmd.data[fan->reg*2+2];

sys/powerpc/powermac/smu.c

847

cmd.data[1] = 1 << fan->reg;

sys/powerpc/powermac/smu.c

853

*pwm = cmd.data[fan->reg*2+2];

sys/powerpc/powermac/smu.c

927

OF_getprop(child, "reg", &fan->reg,

sys/powerpc/powermac/smusat.c

141

sens->reg = 0;

sys/powerpc/powermac/smusat.c

142

OF_getprop(child, "reg", &sens->reg, sizeof(sens->reg));

sys/powerpc/powermac/smusat.c

143

if (sens->reg < 0x30)

sys/powerpc/powermac/smusat.c

145

sens->reg -= 0x30;

sys/powerpc/powermac/smusat.c

201

uint8_t reg = 0x3f;

sys/powerpc/powermac/smusat.c

206

{0, IIC_M_WR | IIC_M_NOSTOP, 1, &reg},

sys/powerpc/powermac/smusat.c

236

value = (sc->sc_cache[sens->reg*2] << 8) +

sys/powerpc/powermac/smusat.c

237

sc->sc_cache[sens->reg*2 + 1];

sys/powerpc/powermac/smusat.c

51

cell_t reg;

sys/powerpc/powermac/uninorth.c

213

struct unin_chip_reg *reg;

sys/powerpc/powermac/uninorth.c

216

nreg = OF_getprop_alloc_multi(devnode, "reg", sizeof(*reg), (void **)&reg);

sys/powerpc/powermac/uninorth.c

222

reg[i].mr_base,

sys/powerpc/powermac/uninorth.c

223

reg[i].mr_base + reg[i].mr_size,

sys/powerpc/powermac/uninorth.c

224

reg[i].mr_size);

sys/powerpc/powermac/uninorth.c

231

volatile u_int *reg;

sys/powerpc/powermac/uninorth.c

236

reg = (void *)(sc->sc_addr + regoff);

sys/powerpc/powermac/uninorth.c

237

tmpl = inl(reg);

sys/powerpc/powermac/uninorth.c

240

outl(reg, tmpl);

sys/powerpc/powermac/uninorth.c

285

u_int irq, reg[3];

sys/powerpc/powermac/uninorth.c

291

if (OF_getprop(root, "reg", reg, sizeof(reg)) < 8)

sys/powerpc/powermac/uninorth.c

299

sc->sc_physaddr = reg[i++];

sys/powerpc/powermac/uninorth.c

302

sc->sc_physaddr |= reg[i++];

sys/powerpc/powermac/uninorth.c

304

sc->sc_size = reg[i++];

sys/powerpc/powermac/uninorth.c

307

sc->sc_size |= reg[i++];

sys/powerpc/powermac/uninorthpci.c

136

uint32_t reg[3];

sys/powerpc/powermac/uninorthpci.c

146

if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)

sys/powerpc/powermac/uninorthpci.c

159

regbase = reg[0];

sys/powerpc/powermac/uninorthpci.c

162

regbase |= reg[1];

sys/powerpc/powermac/uninorthpci.c

177

uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,

sys/powerpc/powermac/uninorthpci.c

185

caoff = sc->sc_data + (reg & 0x07);

sys/powerpc/powermac/uninorthpci.c

189

if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) {

sys/powerpc/powermac/uninorthpci.c

209

u_int reg, u_int32_t val, int width)

sys/powerpc/powermac/uninorthpci.c

215

caoff = sc->sc_data + (reg & 0x07);

sys/powerpc/powermac/uninorthpci.c

218

if (uninorth_enable_config(sc, bus, slot, func, reg)) {

sys/powerpc/powermac/uninorthpci.c

236

u_int func, u_int reg)

sys/powerpc/powermac/uninorthpci.c

259

cfgval = (1 << slot) | (func << 8) | (reg & 0xfc);

sys/powerpc/powermac/uninorthpci.c

262

(reg & 0xfc) | 1;

sys/powerpc/powermac/uninorthpci.c

267

cfgval |= (reg >> 8) << 28;

sys/powerpc/powernv/opal_console.c

194

uint32_t reg;

sys/powerpc/powernv/opal_console.c

205

reg = -1;

sys/powerpc/powernv/opal_console.c

206

OF_getencprop(node, "reg", &reg, sizeof(reg));

sys/powerpc/powernv/opal_console.c

207

if (reg == -1)

sys/powerpc/powernv/opal_console.c

209

sc->vtermid = reg;

sys/powerpc/powernv/opal_dbg.c

58

cell_t reg;

sys/powerpc/powernv/opal_dbg.c

76

reg = ~0U;

sys/powerpc/powernv/opal_dbg.c

77

OF_getencprop(dev, "reg", &reg, sizeof(reg));

sys/powerpc/powernv/opal_dbg.c

78

if (reg == ~0U)

sys/powerpc/powernv/opal_dbg.c

80

termnum = reg;

sys/powerpc/powernv/opal_pci.c

499

opalpci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,

sys/powerpc/powernv/opal_pci.c

517

config_addr, reg, vtophys(&byte));

sys/powerpc/powernv/opal_pci.c

522

config_addr, reg, vtophys(&half));

sys/powerpc/powernv/opal_pci.c

527

config_addr, reg, vtophys(&word));

sys/powerpc/powernv/opal_pci.c

562

u_int reg, uint32_t val, int width)

sys/powerpc/powernv/opal_pci.c

575

config_addr, reg, val);

sys/powerpc/powernv/opal_pci.c

579

config_addr, reg, val);

sys/powerpc/powernv/opal_pci.c

583

config_addr, reg, val);

sys/powerpc/powerpc/db_disasm.c

408

int reg;

sys/powerpc/powerpc/db_disasm.c

801

if (spr == regs[i].reg)

sys/powerpc/powerpc/db_disasm.c

947

const char *reg;

sys/powerpc/powerpc/db_disasm.c

954

reg = "tbl";

sys/powerpc/powerpc/db_disasm.c

957

reg = "tbu";

sys/powerpc/powerpc/db_disasm.c

960

reg = NULL;

sys/powerpc/powerpc/db_disasm.c

962

if (reg == NULL)

sys/powerpc/powerpc/db_disasm.c

965

APP_PSTR(", %s", reg);

sys/powerpc/powerpc/db_trace.c

116

register_t *reg;

sys/powerpc/powerpc/db_trace.c

120

reg = (register_t*)((uintptr_t)kdb_frame + (uintptr_t)vp->valuep);

sys/powerpc/powerpc/db_trace.c

122

*valuep = *reg;

sys/powerpc/powerpc/db_trace.c

124

*reg = *valuep;

sys/powerpc/powerpc/exec_machdep.c

1210

emulate_mfspr(int spr, int reg, struct trapframe *frame){

sys/powerpc/powerpc/exec_machdep.c

1222

frame->fixreg[reg] = td->td_pcb->pcb_dscr;

sys/powerpc/powerpc/exec_machdep.c

1230

emulate_mtspr(int spr, int reg, struct trapframe *frame){

sys/powerpc/powerpc/exec_machdep.c

1239

td->td_pcb->pcb_dscr = frame->fixreg[reg];

sys/powerpc/powerpc/exec_machdep.c

1240

mtspr(SPR_DSCRP, frame->fixreg[reg]);

sys/powerpc/powerpc/exec_machdep.c

1253

int reg, sig;

sys/powerpc/powerpc/exec_machdep.c

1260

reg = (instr & ~0xfc1fffff) >> 21;

sys/powerpc/powerpc/exec_machdep.c

1261

frame->fixreg[reg] = mfpvr();

sys/powerpc/powerpc/exec_machdep.c

732

fill_regs(struct thread *td, struct reg *regs)

sys/powerpc/powerpc/exec_machdep.c

737

memcpy(regs, tf, sizeof(struct reg));

sys/powerpc/powerpc/exec_machdep.c

770

set_regs(struct thread *td, struct reg *regs)

sys/powerpc/powerpc/exec_machdep.c

775

memcpy(tf, regs, sizeof(struct reg));

sys/powerpc/powerpc/fpu.c

256

register_t reg;

sys/powerpc/powerpc/fpu.c

263

reg = mffs();

sys/powerpc/powerpc/fpu.c

270

if (reg & FPSCR_ZX)

sys/powerpc/powerpc/fpu.c

272

else if (reg & FPSCR_OX)

sys/powerpc/powerpc/fpu.c

274

else if (reg & FPSCR_UX)

sys/powerpc/powerpc/fpu.c

276

else if (reg & FPSCR_XX)

sys/powerpc/powerpc/machdep.c

800

long reg;

sys/powerpc/powerpc/machdep.c

811

reg = tf->fixreg[i];

sys/powerpc/powerpc/machdep.c

812

db_printf(" r%d:\t%#lx (%ld)\n", i, reg, reg);

sys/powerpc/powerpc/machdep.c

814

reg = tf->lr;

sys/powerpc/powerpc/machdep.c

815

db_printf(" lr:\t%#lx\n", reg);

sys/powerpc/powerpc/machdep.c

816

reg = tf->cr;

sys/powerpc/powerpc/machdep.c

817

db_printf(" cr:\t%#lx\n", reg);

sys/powerpc/powerpc/machdep.c

818

reg = tf->xer;

sys/powerpc/powerpc/machdep.c

819

db_printf(" xer:\t%#lx\n", reg);

sys/powerpc/powerpc/machdep.c

820

reg = tf->ctr;

sys/powerpc/powerpc/machdep.c

821

db_printf(" ctr:\t%#lx (%ld)\n", reg, reg);

sys/powerpc/powerpc/machdep.c

822

reg = tf->srr0;

sys/powerpc/powerpc/machdep.c

823

db_printf(" srr0:\t%#lx\n", reg);

sys/powerpc/powerpc/machdep.c

824

reg = tf->srr1;

sys/powerpc/powerpc/machdep.c

825

db_printf(" srr1:\t%#lx\n", reg);

sys/powerpc/powerpc/machdep.c

826

reg = tf->exc;

sys/powerpc/powerpc/machdep.c

827

db_printf(" exc:\t%#lx\n", reg);

sys/powerpc/powerpc/machdep.c

828

reg = tf->dar;

sys/powerpc/powerpc/machdep.c

829

db_printf(" dar:\t%#lx\n", reg);

sys/powerpc/powerpc/machdep.c

831

reg = tf->cpu.aim.dsisr;

sys/powerpc/powerpc/machdep.c

832

db_printf(" dsisr:\t%#lx\n", reg);

sys/powerpc/powerpc/machdep.c

834

reg = tf->cpu.booke.esr;

sys/powerpc/powerpc/machdep.c

835

db_printf(" esr:\t%#lx\n", reg);

sys/powerpc/powerpc/machdep.c

836

reg = tf->cpu.booke.dbcr0;

sys/powerpc/powerpc/machdep.c

837

db_printf(" dbcr0:\t%#lx\n", reg);

sys/powerpc/powerpc/openpic.c

61

openpic_read(struct openpic_softc *sc, u_int reg)

sys/powerpc/powerpc/openpic.c

63

return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));

sys/powerpc/powerpc/openpic.c

67

openpic_write(struct openpic_softc *sc, u_int reg, uint32_t val)

sys/powerpc/powerpc/openpic.c

69

bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);

sys/powerpc/powerpc/trap.c

861

int indicator, reg;

sys/powerpc/powerpc/trap.c

876

reg = EXC_ALI_INST_RST(inst);

sys/powerpc/powerpc/trap.c

878

reg = EXC_ALI_RST(frame->cpu.aim.dsisr);

sys/powerpc/powerpc/trap.c

880

fpr = &td->td_pcb->pcb_fpu.fpr[reg].fpr;

sys/powerpc/pseries/phyp_console.c

134

uint32_t reg;

sys/powerpc/pseries/phyp_console.c

150

reg = -1;

sys/powerpc/pseries/phyp_console.c

151

OF_getencprop(node, "reg", &reg, sizeof(reg));

sys/powerpc/pseries/phyp_console.c

152

if (reg == -1)

sys/powerpc/pseries/phyp_console.c

154

sc->vtermid = reg;

sys/powerpc/pseries/phyp_dbg.c

58

cell_t reg;

sys/powerpc/pseries/phyp_dbg.c

82

reg = ~0U;

sys/powerpc/pseries/phyp_dbg.c

83

OF_getencprop(vty, "reg", &reg, sizeof(reg));

sys/powerpc/pseries/phyp_dbg.c

84

if (reg == ~0U)

sys/powerpc/pseries/phyp_dbg.c

87

dbgport.vtermid = reg;

sys/powerpc/pseries/platform_chrp.c

385

get_cpu_reg(phandle_t cpu, cell_t *reg)

sys/powerpc/pseries/platform_chrp.c

392

OF_getencprop(cpu, "reg", reg, res);

sys/powerpc/pseries/platform_chrp.c

403

cell_t interrupt_servers[32], addr_cells, size_cells, reg, bsp_reg;

sys/powerpc/pseries/platform_chrp.c

462

get_cpu_reg(cpu, &reg);

sys/powerpc/pseries/platform_chrp.c

463

if (reg == bsp_reg)

sys/powerpc/pseries/rtas_pci.c

147

rtaspci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,

sys/powerpc/pseries/rtas_pci.c

158

((func & 0x7) << 8) | (reg & 0xff);

sys/powerpc/pseries/rtas_pci.c

160

config_addr |= (reg & 0xf00) << 16;

sys/powerpc/pseries/rtas_pci.c

188

u_int reg, uint32_t val, int width)

sys/powerpc/pseries/rtas_pci.c

197

((func & 0x7) << 8) | (reg & 0xff);

sys/powerpc/pseries/rtas_pci.c

199

config_addr |= (reg & 0xf00) << 16;

sys/powerpc/psim/iobus.c

193

u_int reg[2];

sys/powerpc/psim/iobus.c

203

size = OF_getprop(sc->sc_node, "reg", reg, sizeof(reg));

sys/powerpc/psim/iobus.c

204

if (size == sizeof(reg)) {

sys/powerpc/psim/iobus.c

205

sc->sc_addr = reg[0];

sys/powerpc/psim/iobus.c

206

sc->sc_size = reg[1];

sys/riscv/cvitek/cvitek_restart.c

111

sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->reg_rid,

sys/riscv/cvitek/cvitek_restart.c

113

if (sc->reg == NULL) {

sys/riscv/cvitek/cvitek_restart.c

119

bus_write_4(sc->reg, RTC_EN_SHDN_REQ, 0x1);

sys/riscv/cvitek/cvitek_restart.c

120

bus_write_4(sc->reg, RTC_EN_PWR_CYC_REQ, 0x1);

sys/riscv/cvitek/cvitek_restart.c

121

bus_write_4(sc->reg, RTC_EN_WARM_RST_REQ, 0x1);

sys/riscv/cvitek/cvitek_restart.c

135

if (sc->reg == NULL)

sys/riscv/cvitek/cvitek_restart.c

138

bus_write_4(sc->reg, RTC_EN_SHDN_REQ, 0x0);

sys/riscv/cvitek/cvitek_restart.c

139

bus_write_4(sc->reg, RTC_EN_PWR_CYC_REQ, 0x0);

sys/riscv/cvitek/cvitek_restart.c

140

bus_write_4(sc->reg, RTC_EN_WARM_RST_REQ, 0x0);

sys/riscv/cvitek/cvitek_restart.c

142

bus_release_resource(dev, SYS_RES_MEMORY, sc->reg_rid, sc->reg);

sys/riscv/cvitek/cvitek_restart.c

64

struct resource *reg;

sys/riscv/cvitek/cvitek_restart.c

84

bus_write_4(sc->reg, RTC_CTRL0_UNLOCK, RTC_CTRL0_UNLOCK_KEY);

sys/riscv/cvitek/cvitek_restart.c

85

bus_write_4(sc->reg, RTC_CTRL0, val);

sys/riscv/eswin/eswin_reset.c

115

uint32_t reg;

sys/riscv/eswin/eswin_reset.c

125

reg = ERST_READ(sc, base);

sys/riscv/eswin/eswin_reset.c

127

reg &= ~(1 << bit);

sys/riscv/eswin/eswin_reset.c

129

reg |= (1 << bit);

sys/riscv/eswin/eswin_reset.c

130

ERST_WRITE(sc, base, reg);

sys/riscv/eswin/eswin_reset.c

140

uint32_t reg;

sys/riscv/eswin/eswin_reset.c

150

reg = ERST_READ(sc, base);

sys/riscv/eswin/eswin_reset.c

151

*reset = (reg & (1 << bit)) == 0;

sys/riscv/include/vmm.h

158

int vm_get_register(struct vcpu *vcpu, int reg, uint64_t *retval);

sys/riscv/include/vmm.h

159

int vm_set_register(struct vcpu *vcpu, int reg, uint64_t val);

sys/riscv/include/vmm.h

190

enum vm_reg_name reg;

sys/riscv/include/vmm.h

196

enum vm_reg_name reg;

sys/riscv/riscv/aplic.c

159

#define aplic_read(sc, reg) bus_read_4(sc->mem_res, (reg))

sys/riscv/riscv/aplic.c

160

#define aplic_write(sc, reg, val) bus_write_4(sc->mem_res, (reg), (val))

sys/riscv/riscv/db_interface.c

50

long *reg;

sys/riscv/riscv/db_interface.c

55

reg = (long *)((uintptr_t)kdb_frame + (db_expr_t)vp->valuep);

sys/riscv/riscv/db_interface.c

57

*valuep = *reg;

sys/riscv/riscv/db_interface.c

59

*reg = *valuep;

sys/riscv/riscv/exec_machdep.c

199

sizeof((struct reg *)0)->a);

sys/riscv/riscv/exec_machdep.c

201

sizeof((struct reg *)0)->s);

sys/riscv/riscv/exec_machdep.c

203

sizeof((struct reg *)0)->t);

sys/riscv/riscv/exec_machdep.c

79

fill_regs(struct thread *td, struct reg *regs)

sys/riscv/riscv/exec_machdep.c

99

set_regs(struct thread *td, struct reg *regs)

sys/riscv/riscv/fpe.c

46

uint64_t reg;

sys/riscv/riscv/fpe.c

48

reg = SSTATUS_FS_INITIAL;

sys/riscv/riscv/fpe.c

50

csr_set(sstatus, reg);

sys/riscv/riscv/identcpu.c

372

pcell_t reg;

sys/riscv/riscv/identcpu.c

393

if (OF_getencprop(node, "reg", &reg, sizeof(reg)) <= 0 ||

sys/riscv/riscv/identcpu.c

394

reg != hart)

sys/riscv/riscv/intc.c

80

pcell_t reg;

sys/riscv/riscv/intc.c

95

if (OF_searchencprop(node, "reg", &reg, sizeof(reg)) == -1)

sys/riscv/riscv/intc.c

98

if (reg == hartid)

sys/riscv/riscv/machdep.c

243

register_t reg;

sys/riscv/riscv/machdep.c

247

reg = intr_disable();

sys/riscv/riscv/machdep.c

249

td->td_md.md_saved_sstatus_ie = reg;

sys/riscv/riscv/mp_machdep.c

314

pcell_t *reg __unused)

sys/riscv/riscv/mp_machdep.c

327

cpu_init_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)

sys/riscv/riscv/mp_machdep.c

336

if (!cpu_check_mmu(id, node, addr_size, reg))

sys/riscv/riscv/mp_machdep.c

343

cpu_reg[id][0] = reg[0];

sys/riscv/riscv/mp_machdep.c

345

cpu_reg[id][1] = reg[1];

sys/riscv/riscv/mp_machdep.c

348

hart = reg[0];

sys/riscv/riscv/mp_machdep.c

351

hart |= reg[1];

sys/riscv/riscv/plic.c

112

#define RD4(sc, reg) \

sys/riscv/riscv/plic.c

113

bus_read_4(sc->mem_res, (reg))

sys/riscv/riscv/plic.c

114

#define WR4(sc, reg, val) \

sys/riscv/riscv/plic.c

115

bus_write_4(sc->mem_res, (reg), (val))

sys/riscv/riscv/plic.c

486

uint32_t reg;

sys/riscv/riscv/plic.c

494

reg = RD4(sc, PLIC_ENABLE(sc, src->irq, cpu));

sys/riscv/riscv/plic.c

495

reg &= ~(1 << (src->irq % 32));

sys/riscv/riscv/plic.c

496

WR4(sc, PLIC_ENABLE(sc, src->irq, cpu), reg);

sys/riscv/riscv/plic.c

511

reg = RD4(sc, PLIC_ENABLE(sc, src->irq, cpu));

sys/riscv/riscv/plic.c

512

reg |= (1 << (src->irq % 32));

sys/riscv/riscv/plic.c

513

WR4(sc, PLIC_ENABLE(sc, src->irq, cpu), reg);

sys/riscv/sifive/fe310_aon.c

107

#define FEAON_READ_4(sc, reg) bus_read_4(sc->reg_res, reg)

sys/riscv/sifive/fe310_aon.c

108

#define FEAON_WRITE_4(sc, reg, val) bus_write_4(sc->reg_res, reg, val)

sys/riscv/sifive/fe310_aon.c

110

#define FEAON_WDT_WRITE_4(sc, reg, val) do { \

sys/riscv/sifive/fe310_aon.c

112

FEAON_WRITE_4(sc, reg, val); \

sys/riscv/sifive/fu740_pci_dw.c

111

fupci_phy_read(struct fupci_softc *sc, int phy, uint32_t reg, uint32_t *val)

sys/riscv/sifive/fu740_pci_dw.c

116

FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ADDR), reg);

sys/riscv/sifive/fu740_pci_dw.c

152

fupci_phy_write(struct fupci_softc *sc, int phy, uint32_t reg, uint32_t val)

sys/riscv/sifive/fu740_pci_dw.c

157

FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ADDR), reg);

sys/riscv/sifive/fu740_pci_dw.c

289

uint32_t reg;

sys/riscv/sifive/fu740_pci_dw.c

291

reg = pci_dw_dbi_rd4(sc->dev, DW_MISC_CONTROL_1);

sys/riscv/sifive/fu740_pci_dw.c

293

reg &= ~DBI_RO_WR_EN;

sys/riscv/sifive/fu740_pci_dw.c

295

reg |= DBI_RO_WR_EN;

sys/riscv/sifive/fu740_pci_dw.c

296

pci_dw_dbi_wr4(sc->dev, DW_MISC_CONTROL_1, reg);

sys/riscv/sifive/fu740_pci_dw.c

439

uint32_t reg;

sys/riscv/sifive/fu740_pci_dw.c

441

reg = pci_dw_dbi_rd4(dev, FUDW_DBI_PORT_DBG1);

sys/riscv/sifive/fu740_pci_dw.c

442

*status = (reg & FUDW_DBI_PORT_DBG1_LINK_UP) != 0 &&

sys/riscv/sifive/fu740_pci_dw.c

443

(reg & FUDW_DBI_PORT_DBG1_LINK_IN_TRAINING) == 0;

sys/riscv/sifive/sifive_gpio.c

209

uint32_t reg;

sys/riscv/sifive/sifive_gpio.c

217

reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_VAL);

sys/riscv/sifive/sifive_gpio.c

219

reg |= (1u << pin);

sys/riscv/sifive/sifive_gpio.c

221

reg &= ~(1u << pin);

sys/riscv/sifive/sifive_gpio.c

222

SFGPIO_WRITE(sc, SFGPIO_OUTPUT_VAL, reg);

sys/riscv/sifive/sifive_gpio.c

232

uint32_t reg;

sys/riscv/sifive/sifive_gpio.c

241

reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_VAL);

sys/riscv/sifive/sifive_gpio.c

243

reg = SFGPIO_READ(sc, SFGPIO_INPUT_VAL);

sys/riscv/sifive/sifive_gpio.c

244

*val = (reg & (1u << pin)) ? 1 : 0;

sys/riscv/sifive/sifive_gpio.c

254

uint32_t reg;

sys/riscv/sifive/sifive_gpio.c

262

reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_VAL);

sys/riscv/sifive/sifive_gpio.c

263

reg ^= (1u << pin);

sys/riscv/sifive/sifive_gpio.c

264

SFGPIO_WRITE(sc, SFGPIO_OUTPUT_VAL, reg);

sys/riscv/sifive/sifive_gpio.c

325

uint32_t reg;

sys/riscv/sifive/sifive_gpio.c

334

reg = SFGPIO_READ(sc, SFGPIO_INPUT_EN);

sys/riscv/sifive/sifive_gpio.c

336

reg |= (1u << pin);

sys/riscv/sifive/sifive_gpio.c

339

reg &= ~(1u << pin);

sys/riscv/sifive/sifive_gpio.c

342

SFGPIO_WRITE(sc, SFGPIO_INPUT_EN, reg);

sys/riscv/sifive/sifive_gpio.c

344

reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_EN);

sys/riscv/sifive/sifive_gpio.c

346

reg |= (1u << pin);

sys/riscv/sifive/sifive_gpio.c

349

reg &= ~(1u << pin);

sys/riscv/sifive/sifive_gpio.c

352

SFGPIO_WRITE(sc, SFGPIO_OUTPUT_EN, reg);

sys/riscv/sifive/sifive_gpio.c

364

uint32_t reg;

sys/riscv/sifive/sifive_gpio.c

373

reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_VAL);

sys/riscv/sifive/sifive_gpio.c

378

(reg & SFGPIO_READ(sc, SFGPIO_OUTPUT_EN));

sys/riscv/sifive/sifive_gpio.c

382

(reg & ~clear_pins) ^ change_pins);

sys/riscv/sifive/sifive_prci.c

108

uint32_t reg;

sys/riscv/sifive/sifive_prci.c

115

.reg = (_base), \

sys/riscv/sifive/sifive_prci.c

124

uint32_t reg;

sys/riscv/sifive/sifive_prci.c

133

.reg = (_base), \

sys/riscv/sifive/sifive_prci.c

143

uint32_t reg;

sys/riscv/sifive/sifive_prci.c

151

.reg = (_base), \

sys/riscv/sifive/sifive_prci.c

308

val = PRCI_READ(sc->parent_sc, sc->reg);

sys/riscv/sifive/sifive_prci.c

366

div = PRCI_READ(sc->parent_sc, sc->reg);

sys/riscv/sifive/sifive_prci.c

402

uint32_t reg)

sys/riscv/sifive/sifive_prci.c

414

sc->reg = reg;

sys/riscv/sifive/sifive_prci.c

421

uint32_t reg, uint32_t bias)

sys/riscv/sifive/sifive_prci.c

433

sc->reg = reg;

sys/riscv/sifive/sifive_prci.c

504

prci_pll_register(sc, &clkdef, pll_clk->reg);

sys/riscv/sifive/sifive_prci.c

514

prci_div_register(sc, &clkdef_div, div_clk->reg,

sys/riscv/sifive/sifive_prci.c

526

clkdef_gate.offset = gate_clk->reg;

sys/riscv/sifive/sifive_prci.c

597

uint32_t reg;

sys/riscv/sifive/sifive_prci.c

601

reg = PRCI_READ(sc, addr);

sys/riscv/sifive/sifive_prci.c

602

reg &= ~clr;

sys/riscv/sifive/sifive_prci.c

603

reg |= set;

sys/riscv/sifive/sifive_prci.c

604

PRCI_WRITE(sc, addr, reg);

sys/riscv/sifive/sifive_prci.c

631

uint32_t reg;

sys/riscv/sifive/sifive_prci.c

639

reg = PRCI_READ(sc, PRCI_DEVICES_RESET_N);

sys/riscv/sifive/sifive_prci.c

641

reg &= ~(1u << id);

sys/riscv/sifive/sifive_prci.c

643

reg |= (1u << id);

sys/riscv/sifive/sifive_prci.c

644

PRCI_WRITE(sc, PRCI_DEVICES_RESET_N, reg);

sys/riscv/sifive/sifive_prci.c

654

uint32_t reg;

sys/riscv/sifive/sifive_prci.c

662

reg = PRCI_READ(sc, PRCI_DEVICES_RESET_N);

sys/riscv/sifive/sifive_prci.c

663

*reset = (reg & (1u << id)) == 0;

sys/riscv/sifive/sifive_prci.c

76

uint32_t reg;

sys/riscv/sifive/sifive_prci.c

81

uint32_t reg;

sys/riscv/sifive/sifive_uart.c

100

uint32_t reg;

sys/riscv/sifive/sifive_uart.c

106

reg = SFUART_RXCTRL_ENABLE;

sys/riscv/sifive/sifive_uart.c

107

reg |= (0 << SFUART_RXCTRL_RXCNT_SHIFT);

sys/riscv/sifive/sifive_uart.c

108

uart_setreg(bas, SFUART_RXCTRL, reg);

sys/riscv/sifive/sifive_uart.c

113

reg = SFUART_TXCTRL_ENABLE;

sys/riscv/sifive/sifive_uart.c

114

reg |= (1 << SFUART_TXCTRL_TXCNT_SHIFT);

sys/riscv/sifive/sifive_uart.c

116

reg |= SFUART_TXCTRL_NSTOP;

sys/riscv/sifive/sifive_uart.c

117

uart_setreg(bas, SFUART_TXCTRL, reg);

sys/riscv/sifive/sifive_uart.c

192

uint32_t reg;

sys/riscv/sifive/sifive_uart.c

220

reg = SFUART_RXCTRL_ENABLE;

sys/riscv/sifive/sifive_uart.c

221

reg |= (0 << SFUART_RXCTRL_RXCNT_SHIFT);

sys/riscv/sifive/sifive_uart.c

222

uart_setreg(bas, SFUART_RXCTRL, reg);

sys/riscv/sifive/sifive_uart.c

224

reg = SFUART_TXCTRL_ENABLE;

sys/riscv/sifive/sifive_uart.c

225

reg |= (1 << SFUART_TXCTRL_TXCNT_SHIFT);

sys/riscv/sifive/sifive_uart.c

226

uart_setreg(bas, SFUART_TXCTRL, reg);

sys/riscv/sifive/sifive_uart.c

259

uint32_t reg;

sys/riscv/sifive/sifive_uart.c

266

reg = uart_getreg(bas, SFUART_TXDATA);

sys/riscv/sifive/sifive_uart.c

267

} while ((reg & SFUART_TXDATA_FULL) != 0);

sys/riscv/sifive/sifive_uart.c

272

reg = uart_getreg(bas, SFUART_RXDATA);

sys/riscv/sifive/sifive_uart.c

273

} while ((reg & SFUART_RXDATA_EMPTY) == 0);

sys/riscv/sifive/sifive_uart.c

328

uint32_t reg;

sys/riscv/sifive/sifive_uart.c

337

reg = uart_getreg(bas, SFUART_DIV);

sys/riscv/sifive/sifive_uart.c

338

if (reg == 0) {

sys/riscv/sifive/sifive_uart.c

343

*(int*)data = bas->rclk / (reg + 1);

sys/riscv/sifive/sifive_uart.c

361

uint32_t reg, ie;

sys/riscv/sifive/sifive_uart.c

367

reg = uart_getreg(bas, SFUART_IRQ_PENDING);

sys/riscv/sifive/sifive_uart.c

370

if ((reg & SFUART_IRQ_PENDING_TXWM) != 0 &&

sys/riscv/sifive/sifive_uart.c

379

if ((reg & SFUART_IRQ_PENDING_RXQM) != 0)

sys/riscv/sifive/sifive_uart.c

392

uint32_t reg;

sys/riscv/sifive/sifive_uart.c

404

reg = uart_getreg(bas, SFUART_TXCTRL);

sys/riscv/sifive/sifive_uart.c

406

reg |= SFUART_TXCTRL_NSTOP;

sys/riscv/sifive/sifive_uart.c

408

reg &= ~SFUART_TXCTRL_NSTOP;

sys/riscv/sifive/sifive_uart.c

415

reg = (bas->rclk / baudrate) - 1;

sys/riscv/sifive/sifive_uart.c

416

uart_setreg(bas, SFUART_DIV, reg);

sys/riscv/sifive/sifive_uart.c

427

uint32_t reg;

sys/riscv/sifive/sifive_uart.c

432

reg = uart_getreg(bas, SFUART_RXDATA);

sys/riscv/sifive/sifive_uart.c

433

while ((reg & SFUART_RXDATA_EMPTY) == 0) {

sys/riscv/sifive/sifive_uart.c

439

uart_rx_put(sc, reg & 0xff);

sys/riscv/sifive/sifive_uart.c

441

reg = uart_getreg(bas, SFUART_RXDATA);

sys/riscv/sifive/sifive_uart.c

454

uint32_t reg;

sys/riscv/sifive/sifive_uart.c

459

reg = uart_getreg(bas, SFUART_IRQ_ENABLE);

sys/riscv/sifive/sifive_uart.c

460

reg |= SFUART_IRQ_ENABLE_TXWM;

sys/riscv/sifive/sifive_uart.c

461

uart_setreg(bas, SFUART_IRQ_ENABLE, reg);

sys/riscv/sifive/sifive_uart.c

477

uint32_t reg;

sys/riscv/sifive/sifive_uart.c

482

reg = uart_getreg(bas, SFUART_IRQ_ENABLE);

sys/riscv/sifive/sifive_uart.c

483

reg &= ~(SFUART_IRQ_ENABLE_TXWM | SFUART_IRQ_PENDING_RXQM);

sys/riscv/sifive/sifive_uart.c

484

uart_setreg(bas, SFUART_IRQ_ENABLE, reg);

sys/riscv/sifive/sifive_uart.c

493

uint32_t reg;

sys/riscv/sifive/sifive_uart.c

498

reg = uart_getreg(bas, SFUART_IRQ_ENABLE);

sys/riscv/sifive/sifive_uart.c

499

reg |= SFUART_IRQ_ENABLE_TXWM | SFUART_IRQ_PENDING_RXQM;

sys/riscv/sifive/sifive_uart.c

500

uart_setreg(bas, SFUART_IRQ_ENABLE, reg);

sys/riscv/starfive/jh7110_gpio.c

102

uint32_t reg;

sys/riscv/starfive/jh7110_gpio.c

111

reg = JH7110_GPIO_READ(sc, GPIO_DIN_LOW);

sys/riscv/starfive/jh7110_gpio.c

112

*val = (reg >> pin) & 0x1;

sys/riscv/starfive/jh7110_gpio.c

114

reg = JH7110_GPIO_READ(sc, GPIO_DIN_HIGH);

sys/riscv/starfive/jh7110_gpio.c

115

*val = (reg >> (pin - GPIO_PINS / GPIO_REGS)) & 0x1;

sys/riscv/starfive/jh7110_gpio.c

126

uint32_t reg;

sys/riscv/starfive/jh7110_gpio.c

134

reg = JH7110_GPIO_READ(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin));

sys/riscv/starfive/jh7110_gpio.c

135

reg &= ~(DATA_OUT_MASK << GPIO_SHIFT(pin));

sys/riscv/starfive/jh7110_gpio.c

137

reg |= 0x1 << GPIO_SHIFT(pin);

sys/riscv/starfive/jh7110_gpio.c

138

JH7110_GPIO_WRITE(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin), reg);

sys/riscv/starfive/jh7110_gpio.c

148

uint32_t reg;

sys/riscv/starfive/jh7110_gpio.c

156

reg = JH7110_GPIO_READ(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin));

sys/riscv/starfive/jh7110_gpio.c

157

if (reg & 0x1 << GPIO_SHIFT(pin)) {

sys/riscv/starfive/jh7110_gpio.c

158

reg &= ~(DATA_OUT_MASK << GPIO_SHIFT(pin));

sys/riscv/starfive/jh7110_gpio.c

160

reg &= ~(DATA_OUT_MASK << GPIO_SHIFT(pin));

sys/riscv/starfive/jh7110_gpio.c

161

reg |= 0x1 << GPIO_SHIFT(pin);

sys/riscv/starfive/jh7110_gpio.c

163

JH7110_GPIO_WRITE(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin), reg);

sys/riscv/starfive/jh7110_gpio.c

195

uint32_t reg;

sys/riscv/starfive/jh7110_gpio.c

204

reg = JH7110_GPIO_READ(sc, GP0_DOEN_CFG + GPIO_RW_OFFSET(pin));

sys/riscv/starfive/jh7110_gpio.c

205

if ((reg & ENABLE_MASK << GPIO_SHIFT(pin)) == 0)

sys/riscv/starfive/jh7110_gpio.c

218

uint32_t reg;

sys/riscv/starfive/jh7110_gpio.c

230

reg = JH7110_GPIO_READ(sc, IOMUX_SYSCFG_288 + PAD_OFFSET(pin));

sys/riscv/starfive/jh7110_gpio.c

231

reg |= (PAD_INPUT_EN | PAD_HYST);

sys/riscv/starfive/jh7110_gpio.c

232

JH7110_GPIO_WRITE(sc, IOMUX_SYSCFG_288 + PAD_OFFSET(pin), reg);

sys/riscv/starfive/jh7110_gpio.c

235

reg = JH7110_GPIO_READ(sc, GP0_DOEN_CFG + GPIO_RW_OFFSET(pin));

sys/riscv/starfive/jh7110_gpio.c

236

reg &= ~(ENABLE_MASK << GPIO_SHIFT(pin));

sys/riscv/starfive/jh7110_gpio.c

238

reg |= DIROUT_DISABLE << GPIO_SHIFT(pin);

sys/riscv/starfive/jh7110_gpio.c

240

JH7110_GPIO_WRITE(sc, GP0_DOEN_CFG + GPIO_RW_OFFSET(pin), reg);

sys/riscv/starfive/jh7110_gpio.c

243

reg = JH7110_GPIO_READ(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin));

sys/riscv/starfive/jh7110_gpio.c

244

reg &= ~(ENABLE_MASK << GPIO_SHIFT(pin));

sys/riscv/starfive/jh7110_gpio.c

245

reg |= 0x1 << GPIO_SHIFT(pin);

sys/riscv/starfive/jh7110_gpio.c

246

JH7110_GPIO_WRITE(sc, GP0_DOUT_CFG + GPIO_RW_OFFSET(pin), reg);

sys/riscv/starfive/jh7110_gpio.c

248

reg = JH7110_GPIO_READ(sc, IOMUX_SYSCFG_288 + PAD_OFFSET(pin));

sys/riscv/starfive/jh7110_gpio.c

249

reg &= ~(PAD_INPUT_EN | PAD_PULLUP | PAD_PULLDOWN | PAD_HYST);

sys/riscv/starfive/jh7110_gpio.c

250

JH7110_GPIO_WRITE(sc, IOMUX_SYSCFG_288 + PAD_OFFSET(pin), reg);

sys/riscv/starfive/jh7110_gpio.c

77

#define JH7110_GPIO_READ(sc, reg) bus_read_4((sc)->res, (reg))

sys/riscv/starfive/jh7110_gpio.c

78

#define JH7110_GPIO_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))

sys/riscv/starfive/jh7110_pcie.c

161

#define RD4(sc, reg) bus_read_4((sc)->reg_mem_res, (reg))

sys/riscv/starfive/jh7110_pcie.c

162

#define WR4(sc, reg, val) bus_write_4((sc)->reg_mem_res, (reg), (val))

sys/riscv/starfive/jh7110_pcie.c

166

u_int reg, int bytes)

sys/riscv/starfive/jh7110_pcie.c

172

offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);

sys/riscv/starfive/jh7110_pcie.c

197

u_int reg, uint32_t val, int bytes)

sys/riscv/starfive/jh7110_pcie.c

203

offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);

sys/riscv/starfive/jh7110_pcie.c

230

uint32_t reg, irqbits;

sys/riscv/starfive/jh7110_pcie.c

236

reg = RD4(sc, IRQ_LOCAL_STATUS);

sys/riscv/starfive/jh7110_pcie.c

237

if (reg == 0)

sys/riscv/starfive/jh7110_pcie.c

240

if ((reg & MSI_MASK) != 0) {

sys/riscv/starfive/jh7110_pcie.c

256

if ((reg & INTX_MASK) != 0) {

sys/riscv/starfive/jh7110_pcie.c

257

irqbits = (reg & INTX_MASK);

sys/riscv/starfive/jh7110_pcie.c

260

if ((reg & ERROR_MASK) != 0) {

sys/riscv/starfive/jh7110_pcie.c

261

irqbits = (reg & ERROR_MASK);

sys/riscv/starfive/jh7110_pcie.c

262

if ((reg & PLDA_AXI_POST_ERR) != 0)

sys/riscv/starfive/jh7110_pcie.c

264

if ((reg & PLDA_AXI_FETCH_ERR) != 0)

sys/riscv/starfive/jh7110_pcie.c

266

if ((reg & PLDA_AXI_DISCARD_ERR) != 0)

sys/riscv/starfive/jh7110_pcie.c

268

if ((reg & PLDA_PCIE_POST_ERR) != 0)

sys/riscv/starfive/jh7110_pcie.c

270

if ((reg & PLDA_PCIE_FETCH_ERR) != 0)

sys/riscv/starfive/jh7110_pcie.c

272

if ((reg & PLDA_PCIE_DISCARD_ERR) != 0)

sys/riscv/starfive/jh7110_pcie.c

274

if ((reg & PLDA_SYS_ERR) != 0)

sys/riscv/starfive/jh7110_pcie.c

460

uint32_t reg, irq;

sys/riscv/starfive/jh7110_pcie.c

465

reg = bus_read_4(sc->cfg_mem_res, sc->msi_mask_offset);

sys/riscv/starfive/jh7110_pcie.c

467

reg &= ~(1U << irq);

sys/riscv/starfive/jh7110_pcie.c

469

reg |= (1U << irq);

sys/riscv/starfive/jh7110_pcie.c

470

bus_write_4(sc->cfg_mem_res, sc->msi_mask_offset, reg);

sys/riscv/vmm/vmm.c

470

vm_get_register(struct vcpu *vcpu, int reg, uint64_t *retval)

sys/riscv/vmm/vmm.c

472

if (reg < 0 || reg >= VM_REG_LAST)

sys/riscv/vmm/vmm.c

475

return (vmmops_getreg(vcpu->cookie, reg, retval));

sys/riscv/vmm/vmm.c

479

vm_set_register(struct vcpu *vcpu, int reg, uint64_t val)

sys/riscv/vmm/vmm.c

483

if (reg < 0 || reg >= VM_REG_LAST)

sys/riscv/vmm/vmm.c

485

error = vmmops_setreg(vcpu->cookie, reg, val);

sys/riscv/vmm/vmm.c

486

if (error || reg != VM_REG_GUEST_SEPC)

sys/riscv/vmm/vmm_aplic.c

242

aplic_handle_idc(struct hyp *hyp, struct aplic *aplic, int cpu, int reg,

sys/riscv/vmm/vmm_aplic.c

247

switch (reg + APLIC_IDC(0)) {

sys/riscv/vmm/vmm_aplic.c

265

aplic_mmio_access(struct hyp *hyp, struct aplic *aplic, uint64_t reg,

sys/riscv/vmm/vmm_aplic.c

273

dprintf("%s: reg %lx\n", __func__, reg);

sys/riscv/vmm/vmm_aplic.c

275

if ((reg >= APLIC_SOURCECFG(1)) &&

sys/riscv/vmm/vmm_aplic.c

276

(reg <= APLIC_SOURCECFG(aplic->nirqs))) {

sys/riscv/vmm/vmm_aplic.c

277

i = ((reg - APLIC_SOURCECFG(1)) >> 2) + 1;

sys/riscv/vmm/vmm_aplic.c

282

if ((reg >= APLIC_TARGET(1)) && (reg <= APLIC_TARGET(aplic->nirqs))) {

sys/riscv/vmm/vmm_aplic.c

283

i = ((reg - APLIC_TARGET(1)) >> 2) + 1;

sys/riscv/vmm/vmm_aplic.c

288

if ((reg >= APLIC_IDC(0)) && (reg < APLIC_IDC(mp_ncpus))) {

sys/riscv/vmm/vmm_aplic.c

289

cpu = (reg - APLIC_IDC(0)) >> 5;

sys/riscv/vmm/vmm_aplic.c

290

r = (reg - APLIC_IDC(0)) % 32;

sys/riscv/vmm/vmm_aplic.c

295

if ((reg >= APLIC_CLRIE) && (reg < (APLIC_CLRIE + aplic->nirqs * 4))) {

sys/riscv/vmm/vmm_aplic.c

296

i = (reg - APLIC_CLRIE) >> 2;

sys/riscv/vmm/vmm_aplic.c

301

switch (reg) {

sys/riscv/vmm/vmm_aplic.c

318

dprintf("%s: unknown reg %lx", __func__, reg);

sys/riscv/vmm/vmm_aplic.c

333

uint64_t reg;

sys/riscv/vmm/vmm_aplic.c

346

reg = fault_ipa - aplic->mem_start;

sys/riscv/vmm/vmm_aplic.c

348

error = aplic_mmio_access(hyp, aplic, reg, false, &val);

sys/riscv/vmm/vmm_aplic.c

362

uint64_t reg;

sys/riscv/vmm/vmm_aplic.c

376

reg = fault_ipa - aplic->mem_start;

sys/riscv/vmm/vmm_aplic.c

380

error = aplic_mmio_access(hyp, aplic, reg, true, &val);

sys/riscv/vmm/vmm_instruction_emul.c

101

error = vm_get_register(vcpu, vre->reg, &val);

sys/riscv/vmm/vmm_instruction_emul.c

73

error = vm_set_register(vcpu, vie->reg, val);

sys/riscv/vmm/vmm_instruction_emul.c

75

error = vm_get_register(vcpu, vie->reg, &val);

sys/riscv/vmm/vmm_instruction_emul.c

99

error = vm_set_register(vcpu, vre->reg, val);

sys/riscv/vmm/vmm_riscv.c

440

vie->reg = reg_num;

sys/riscv/vmm/vmm_riscv.c

779

hypctx_regptr(struct hypctx *hypctx, int reg)

sys/riscv/vmm/vmm_riscv.c

782

switch (reg) {

sys/riscv/vmm/vmm_riscv.c

855

vmmops_getreg(void *vcpui, int reg, uint64_t *retval)

sys/riscv/vmm/vmm_riscv.c

868

if (reg == VM_REG_GUEST_ZERO) {

sys/riscv/vmm/vmm_riscv.c

873

regp = hypctx_regptr(hypctx, reg);

sys/riscv/vmm/vmm_riscv.c

883

vmmops_setreg(void *vcpui, int reg, uint64_t val)

sys/riscv/vmm/vmm_riscv.c

896

regp = hypctx_regptr(hypctx, reg);

sys/sys/procfs.h

35

typedef struct reg gregset_t;

sys/sys/ptrace.h

239

struct reg;

sys/sys/ptrace.h

243

int proc_read_regs(struct thread *_td, struct reg *_reg);

sys/sys/ptrace.h

244

int proc_write_regs(struct thread *_td, struct reg *_reg);

sys/sys/reg.h

67

int fill_regs(struct thread *, struct reg *);

sys/sys/reg.h

68

int set_regs(struct thread *, struct reg *);

sys/x86/include/legacyvar.h

51

u_int func, u_int reg, int bytes);

sys/x86/include/legacyvar.h

55

u_int func, u_int reg, uint32_t data, int bytes);

sys/x86/include/pci_cfgreg.h

61

u_int32_t pci_cfgregread(int domain, int bus, int slot, int func, int reg, int bytes);

sys/x86/include/pci_cfgreg.h

62

void pci_cfgregwrite(int domain, int bus, int slot, int func, int reg, u_int32_t data, int bytes);

sys/x86/include/reg.h

265

int fill_frame_regs(struct trapframe *, struct reg *);

sys/x86/include/reg.h

83

#define __reg32 reg

sys/x86/include/reg.h

89

#define __reg64 reg

sys/x86/include/x86_var.h

103

struct reg;

sys/x86/iommu/amd_iommu.h

144

amdiommu_read4(const struct amdiommu_unit *unit, int reg)

sys/x86/iommu/amd_iommu.h

147

return (bus_read_4(unit->mmio_res, reg));

sys/x86/iommu/amd_iommu.h

151

amdiommu_read8(const struct amdiommu_unit *unit, int reg)

sys/x86/iommu/amd_iommu.h

156

low = bus_read_4(unit->mmio_res, reg);

sys/x86/iommu/amd_iommu.h

157

high = bus_read_4(unit->mmio_res, reg + 4);

sys/x86/iommu/amd_iommu.h

160

return (bus_read_8(unit->mmio_res, reg));

sys/x86/iommu/amd_iommu.h

165

amdiommu_write4(const struct amdiommu_unit *unit, int reg, uint32_t val)

sys/x86/iommu/amd_iommu.h

167

bus_write_4(unit->mmio_res, reg, val);

sys/x86/iommu/amd_iommu.h

171

amdiommu_write8(const struct amdiommu_unit *unit, int reg, uint64_t val)

sys/x86/iommu/amd_iommu.h

178

bus_write_4(unit->mmio_res, reg, low);

sys/x86/iommu/amd_iommu.h

179

bus_write_4(unit->mmio_res, reg + 4, high);

sys/x86/iommu/amd_iommu.h

181

bus_write_8(unit->mmio_res, reg, val);

sys/x86/iommu/intel_dmar.h

272

dmar_read4(const struct dmar_unit *unit, int reg)

sys/x86/iommu/intel_dmar.h

275

return (bus_read_4(unit->regs, reg));

sys/x86/iommu/intel_dmar.h

279

dmar_read8(const struct dmar_unit *unit, int reg)

sys/x86/iommu/intel_dmar.h

284

low = bus_read_4(unit->regs, reg);

sys/x86/iommu/intel_dmar.h

285

high = bus_read_4(unit->regs, reg + 4);

sys/x86/iommu/intel_dmar.h

288

return (bus_read_8(unit->regs, reg));

sys/x86/iommu/intel_dmar.h

293

dmar_write4(const struct dmar_unit *unit, int reg, uint32_t val)

sys/x86/iommu/intel_dmar.h

296

KASSERT(reg != DMAR_GCMD_REG || (val & DMAR_GCMD_TE) ==

sys/x86/iommu/intel_dmar.h

300

bus_write_4(unit->regs, reg, val);

sys/x86/iommu/intel_dmar.h

304

dmar_write8(const struct dmar_unit *unit, int reg, uint64_t val)

sys/x86/iommu/intel_dmar.h

307

KASSERT(reg != DMAR_GCMD_REG, ("8byte GCMD write"));

sys/x86/iommu/intel_dmar.h

313

bus_write_4(unit->regs, reg, low);

sys/x86/iommu/intel_dmar.h

314

bus_write_4(unit->regs, reg + 4, high);

sys/x86/iommu/intel_dmar.h

316

bus_write_8(unit->regs, reg, val);

sys/x86/iommu/intel_utils.c

317

int error, reg;

sys/x86/iommu/intel_utils.c

322

reg = 16 * DMAR_ECAP_IRO(unit->hw_ecap);

sys/x86/iommu/intel_utils.c

324

dmar_write8(unit, reg + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT |

sys/x86/iommu/intel_utils.c

326

DMAR_WAIT_UNTIL(((dmar_read4(unit, reg + DMAR_IOTLB_REG_OFF + 4) &

sys/x86/iommu/intel_utils.c

363

uint32_t reg;

sys/x86/iommu/intel_utils.c

372

reg = dmar_read4(unit, DMAR_PMEN_REG);

sys/x86/iommu/intel_utils.c

373

if ((reg & DMAR_PMEN_EPM) == 0)

sys/x86/iommu/intel_utils.c

376

reg &= ~DMAR_PMEN_EPM;

sys/x86/iommu/intel_utils.c

377

dmar_write4(unit, DMAR_PMEN_REG, reg);

sys/x86/isa/atrtc.c

102

if (rtc_reg != reg) {

sys/x86/isa/atrtc.c

104

outb(IO_RTC, reg);

sys/x86/isa/atrtc.c

105

rtc_reg = reg;

sys/x86/isa/atrtc.c

112

rtcout_locked(int reg, u_char val)

sys/x86/isa/atrtc.c

115

if (rtc_reg != reg) {

sys/x86/isa/atrtc.c

117

outb(IO_RTC, reg);

sys/x86/isa/atrtc.c

118

rtc_reg = reg;

sys/x86/isa/atrtc.c

126

rtcin(int reg)

sys/x86/isa/atrtc.c

131

val = rtcin_locked(reg);

sys/x86/isa/atrtc.c

137

writertc(int reg, u_char val)

sys/x86/isa/atrtc.c

141

rtcout_locked(reg, val);

sys/x86/isa/atrtc.c

273

rtcin_region(int reg, void *buf, int len)

sys/x86/isa/atrtc.c

279

*ptr++ = rtcin(reg++) & 0xff;

sys/x86/isa/atrtc.c

283

rtcout_region(int reg, const void *buf, int len)

sys/x86/isa/atrtc.c

288

writertc(reg++, *ptr++);

sys/x86/isa/atrtc.c

99

rtcin_locked(int reg)

sys/x86/pci/pci_bus.c

64

u_int reg, int bytes)

sys/x86/pci/pci_bus.c

66

return(pci_cfgregread(0, bus, slot, func, reg, bytes));

sys/x86/pci/pci_bus.c

73

u_int reg, uint32_t data, int bytes)

sys/x86/pci/pci_bus.c

75

pci_cfgregwrite(0, bus, slot, func, reg, data, bytes);

sys/x86/x86/cpu_machdep.c

427

register_t reg;

sys/x86/x86/cpu_machdep.c

454

reg = intr_disable();

sys/x86/x86/cpu_machdep.c

463

intr_restore(reg);

sys/x86/x86/cpu_machdep.c

475

intr_restore(reg);

sys/x86/x86/io_apic.c

111

static u_int ioapic_read(volatile ioapic_t *apic, int reg);

sys/x86/x86/io_apic.c

112

static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val);

sys/x86/x86/io_apic.c

1207

db_ioapic_read(volatile ioapic_t *apic, int reg)

sys/x86/x86/io_apic.c

1210

apic->ioregsel = reg;

sys/x86/x86/io_apic.c

207

ioapic_read(volatile ioapic_t *apic, int reg)

sys/x86/x86/io_apic.c

211

apic->ioregsel = reg;

sys/x86/x86/io_apic.c

216

ioapic_write(volatile ioapic_t *apic, int reg, u_int val)

sys/x86/x86/io_apic.c

220

apic->ioregsel = reg;

sys/x86/x86/local_apic.c

354

lapic_read32(enum LAPIC_REGISTERS reg)

sys/x86/x86/local_apic.c

359

res = rdmsr32(MSR_APIC_000 + reg);

sys/x86/x86/local_apic.c

361

res = *(volatile uint32_t *)(lapic_map + reg * LAPIC_MEM_MUL);

sys/x86/x86/local_apic.c

367

lapic_write32(enum LAPIC_REGISTERS reg, uint32_t val)

sys/x86/x86/local_apic.c

373

wrmsr(MSR_APIC_000 + reg, val);

sys/x86/x86/local_apic.c

375

*(volatile uint32_t *)(lapic_map + reg * LAPIC_MEM_MUL) = val;

sys/x86/x86/local_apic.c

380

lapic_write32_nofence(enum LAPIC_REGISTERS reg, uint32_t val)

sys/x86/x86/local_apic.c

384

wrmsr(MSR_APIC_000 + reg, val);

sys/x86/x86/local_apic.c

386

*(volatile uint32_t *)(lapic_map + reg * LAPIC_MEM_MUL) = val;

tests/sys/arch/aarch64/sve.c

242

struct reg reg;

tests/sys/arch/aarch64/sve.c

326

ATF_REQUIRE(ptrace(PT_GETREGS, wpid, (caddr_t)&reg, 0) != -1);

tests/sys/arch/aarch64/sve.c

327

reg.elr += 4;

tests/sys/arch/aarch64/sve.c

328

ATF_REQUIRE(ptrace(PT_SETREGS, wpid, (caddr_t)&reg, 0) != -1);

tests/sys/arch/aarch64/sve.c

65

uint64_t reg, val;

tests/sys/arch/aarch64/sve.c

70

reg = READ_SPECIALREG(id_aa64pfr0_el1);

tests/sys/arch/aarch64/sve.c

71

ATF_REQUIRE((reg & ID_AA64PFR0_SVE_MASK) >= ID_AA64PFR0_SVE_IMPL);

tests/sys/kern/ptrace_test.c

3795

struct reg reg;

tests/sys/kern/ptrace_test.c

3869

ATF_REQUIRE(ptrace(PT_GETREGS, pl.pl_lwpid, (caddr_t)&reg, 0) != -1);

tests/sys/kern/ptrace_test.c

3870

SKIP_BREAK(&reg);

tests/sys/kern/ptrace_test.c

3871

ATF_REQUIRE(ptrace(PT_SETREGS, pl.pl_lwpid, (caddr_t)&reg, 0) != -1);

tests/sys/kern/ptrace_test.c

3909

ATF_REQUIRE(ptrace(PT_GETREGS, pl.pl_lwpid, (caddr_t)&reg,

tests/sys/kern/ptrace_test.c

3911

SKIP_BREAK(&reg);

tests/sys/kern/ptrace_test.c

3912

ATF_REQUIRE(ptrace(PT_SETREGS, pl.pl_lwpid, (caddr_t)&reg,

tests/sys/kern/ptrace_test.c

67

#define SKIP_BREAK(reg) ((reg)->elr += 4)

tests/sys/kern/ptrace_test.c

69

#define SKIP_BREAK(reg)

tests/sys/kern/ptrace_test.c

71

#define SKIP_BREAK(reg) ((reg)->r_pc += 4)

tests/sys/kern/ptrace_test.c

73

#define SKIP_BREAK(reg) ((reg)->sepc += 4)

tests/sys/netmap/ctrl-api-test.c

1896

struct nmreq_register *reg)

tests/sys/netmap/ctrl-api-test.c

1903

orig_reg = *reg;

tests/sys/netmap/ctrl-api-test.c

1906

if (nmreq_register_decode(&ctx->ifparse, reg, ctx->nmctx) < 0) {

tests/sys/netmap/ctrl-api-test.c

1917

if (memcmp(&orig_reg, reg, sizeof(*reg))) {

tests/sys/netmap/ctrl-api-test.c

1930

if (reg->nr_mode != t->exp_mode) {

tests/sys/netmap/ctrl-api-test.c

1931

printf("!!! got nr_mode '%d', want '%d'\n", reg->nr_mode, t->exp_mode);

tests/sys/netmap/ctrl-api-test.c

1934

if (reg->nr_ringid != t->exp_ringid) {

tests/sys/netmap/ctrl-api-test.c

1935

printf("!!! got nr_ringid '%d', want '%d'\n", reg->nr_ringid, t->exp_ringid);

tests/sys/netmap/ctrl-api-test.c

1938

if (reg->nr_flags != t->exp_flags) {

tests/sys/netmap/ctrl-api-test.c

1939

printf("!!! got nm_flags '%llx', want '%llx\n", (unsigned long long)reg->nr_flags,

tests/sys/netmap/ctrl-api-test.c

1943

if (reg->nr_offset != orig_reg.nr_offset ||

tests/sys/netmap/ctrl-api-test.c

1944

reg->nr_memsize != orig_reg.nr_memsize ||

tests/sys/netmap/ctrl-api-test.c

1945

reg->nr_tx_slots != orig_reg.nr_tx_slots ||

tests/sys/netmap/ctrl-api-test.c

1946

reg->nr_rx_slots != orig_reg.nr_rx_slots ||

tests/sys/netmap/ctrl-api-test.c

1947

reg->nr_tx_rings != orig_reg.nr_tx_rings ||

tests/sys/netmap/ctrl-api-test.c

1948

reg->nr_rx_rings != orig_reg.nr_rx_rings ||

tests/sys/netmap/ctrl-api-test.c

1949

reg->nr_extra_bufs != orig_reg.nr_extra_bufs)

tests/sys/netmap/ctrl-api-test.c

1969

struct nmreq_register reg;

tests/sys/netmap/ctrl-api-test.c

1986

randomize(&reg, sizeof(reg));

tests/sys/netmap/ctrl-api-test.c

1987

reg.nr_mem_id = 0;

tests/sys/netmap/ctrl-api-test.c

1990

} else if (t->exp_error <= 0 && nmreq_reg_parsing(ctx, t, &reg) < 0) {

tests/sys/netmap/ctrl-api-test.c

560

req.reg.nr_mem_id = ctx->nr_mem_id;

tests/sys/netmap/ctrl-api-test.c

564

req.reg.nr_mode = ctx->nr_mode;

tests/sys/netmap/ctrl-api-test.c

570

printf("nr_mem_id %u\n", req.reg.nr_mem_id);

tests/sys/netmap/ctrl-api-test.c

572

return ((!ctx->nr_mem_id && req.reg.nr_mem_id > 1) ||

tests/sys/netmap/ctrl-api-test.c

573

(ctx->nr_mem_id == req.reg.nr_mem_id)) &&

tests/sys/netmap/ctrl-api-test.c

574

(ctx->nr_flags == req.reg.nr_flags)

tools/test/popss/popss.c

55

struct reg r;

tools/tools/ath/arcode/arcode.c

108

a.op, a.reg, a.val);

tools/tools/ath/arcode/arcode.c

45

printf("read\t%.8x = %.8x\n", a->reg, a->val);

tools/tools/ath/arcode/arcode.c

51

printf("write\t%.8x = %.8x\n", a->reg, a->val);

tools/tools/ath/arcode/arcode.c

57

printf("device\t0x%x/0x%x\n", a->reg, a->val);

tools/tools/ath/arcode/arcode.c

64

if (a->reg <= MAX_MARKERS)

tools/tools/ath/arcode/arcode.c

65

s = markers[a->reg];

tools/tools/ath/arcode/arcode.c

67

printf("mark\t%s (%d): %d\n", s, a->reg, a->val);

tools/tools/ath/athdecode/main.c

112

switch (r->reg) {

tools/tools/ath/athdecode/main.c

190

fprintf(fd, "mark #%u value %u/0x%x", r->reg, r->val, r->val);

tools/tools/ath/athdecode/main.c

352

findreg(int reg)

tools/tools/ath/athdecode/main.c

359

if (dr->addr == reg &&

tools/tools/ath/athdecode/main.c

381

dr = findreg(r->reg);

tools/tools/ath/athdecode/main.c

383

snprintf(buf, sizeof (buf), "AR_%s (0x%x)", dr->name, r->reg);

tools/tools/ath/athdecode/main.c

385

} else if (AR_KEYTABLE(0) <= r->reg && r->reg < AR_KEYTABLE(128)) {

tools/tools/ath/athdecode/main.c

387

((r->reg - AR_KEYTABLE_0) >> 2) & 7,

tools/tools/ath/athdecode/main.c

388

(r->reg - AR_KEYTABLE_0) >> 5, r->reg);

tools/tools/ath/athdecode/main.c

391

} else if (AR_PHY_PCDAC_TX_POWER(0) <= r->reg && r->reg < AR_PHY_PCDAC_TX_POWER(PWR_TABLE_SIZE/2)) {

tools/tools/ath/athdecode/main.c

393

(r->reg - AR_PHY_PCDAC_TX_POWER_0) >> 2, r->reg);

tools/tools/ath/athdecode/main.c

396

} else if (AR_RATE_DURATION(0) <= r->reg && r->reg < AR_RATE_DURATION(32)) {

tools/tools/ath/athdecode/main.c

398

(r->reg - AR_RATE_DURATION_0) >> 2, r->reg);

tools/tools/ath/athdecode/main.c

400

} else if (AR_PHY_BASE <= r->reg) {

tools/tools/ath/athdecode/main.c

402

(r->reg - AR_PHY_BASE) >> 2, r->reg);

tools/tools/ath/athdecode/main.c

405

snprintf(buf, sizeof (buf), "0x%x", r->reg);

tools/tools/ath/athpoke/athpoke.c

100

uint32_t reg;

tools/tools/ath/athpoke/athpoke.c

108

reg = (uint32_t) strtoul(argv[0], &eptr, 0);

tools/tools/ath/athpoke/athpoke.c

112

reg = dr->addr;

tools/tools/ath/athpoke/athpoke.c

114

regwrite(s, &atd, reg, (uint32_t) strtoul(cp, NULL, 0));

tools/tools/ath/athpoke/athpoke.c

115

printf("%s = %08x\n", argv[0], regread(s, &atd, reg));

tools/tools/cxgbtool/cxgbtool.c

1135

struct ch_reg reg;

tools/tools/cxgbtool/cxgbtool.c

1140

if (doit(iff_name, CHELSIO_GET_QSET_NUM, &reg) < 0)

tools/tools/cxgbtool/cxgbtool.c

1142

printf("%u\n", reg.val);

tools/tools/cxgbtool/cxgbtool.c

157

struct ch_reg reg;

tools/tools/cxgbtool/cxgbtool.c

159

reg.addr = addr;

tools/tools/cxgbtool/cxgbtool.c

161

if (doit(iff_name, CHELSIO_GETREG, &reg) < 0)

tools/tools/cxgbtool/cxgbtool.c

163

return reg.val;

tools/tools/cxgbtool/cxgbtool.c

211

unsigned int cmd, phy_addr, reg, mmd, val;

tools/tools/cxgbtool/cxgbtool.c

222

get_int_arg(argv[start_arg + 2], &reg) ||

tools/tools/cxgbtool/cxgbtool.c

227

p.reg_num = reg;

tools/tools/netmap/bridge.c

300

pa->hdr.nr_name, pa->first_rx_ring, pa->reg.nr_rx_rings,

tools/tools/netmap/bridge.c

301

pb->hdr.nr_name, pb->first_rx_ring, pb->reg.nr_rx_rings);

tools/tools/netmap/bridge.c

303

pa_sw_rings = (pa->reg.nr_mode == NR_REG_SW ||

tools/tools/netmap/bridge.c

304

pa->reg.nr_mode == NR_REG_ONE_SW);

tools/tools/netmap/bridge.c

305

pb_sw_rings = (pb->reg.nr_mode == NR_REG_SW ||

tools/tools/netmap/bridge.c

306

pb->reg.nr_mode == NR_REG_ONE_SW);

tools/tools/netmap/lb.c

734

rxport->nmd->reg.nr_extra_bufs = glob_arg.extra_bufs;

tools/tools/netmap/lb.c

742

uint32_t extra_bufs = rxport->nmd->reg.nr_extra_bufs;

tools/tools/netmap/lb.c

810

rxport->nmd->reg.nr_mem_id);

tools/tools/netmap/lb.c

828

k + 1, p->interface, p->nmd->reg.nr_tx_slots);

tools/tools/netmap/pkt-gen.c

2645

g->nmd->reg.nr_rx_rings :

tools/tools/netmap/pkt-gen.c

2646

g->nmd->reg.nr_tx_rings);

tools/tools/netmap/pkt-gen.c

2661

t->nmd->reg.nr_mode = NR_REG_ONE_SW;

tools/tools/netmap/pkt-gen.c

2664

t->nmd->reg.nr_ringid = j & NETMAP_RING_MASK;

tools/tools/netmap/pkt-gen.c

2667

t->nmd->reg.nr_flags |= NETMAP_NO_TX_POLL;

tools/tools/netmap/pkt-gen.c

3232

parse_nmr_config(g.nmr_config, &g.nmd->reg);

tools/tools/netmap/pkt-gen.c

3234

g.nmd->reg.nr_flags |= NR_ACCEPT_VNET_HDR;

tools/tools/netmap/pkt-gen.c

3243

g.orig_mode = g.nmd->reg.nr_mode;

tools/tools/netmap/pkt-gen.c

3248

g.nmd->reg.nr_mode = NR_REG_ONE_NIC;

tools/tools/netmap/pkt-gen.c

3251

g.nmd->reg.nr_mode = NR_REG_ONE_SW;

tools/tools/netmap/pkt-gen.c

3256

g.nmd->reg.nr_ringid = 0;

tools/tools/netmap/pkt-gen.c

3276

devqueues = g.nmd->reg.nr_tx_rings + g.nmd->reg.nr_host_tx_rings;

tools/tools/netmap/pkt-gen.c

3278

devqueues = g.nmd->reg.nr_rx_rings + g.nmd->reg.nr_host_rx_rings;

tools/tools/netmap/pkt-gen.c

3298

struct nmreq_register *req = &g.nmd->reg;

usr.bin/script/script.c

498

consume(FILE *fp, off_t len, char *buf, int reg)

usr.bin/script/script.c

502

if (reg) {

usr.bin/script/script.c

561

int reg;

usr.bin/script/script.c

566

reg = S_ISREG(pst.st_mode);

usr.bin/script/script.c

569

for (nread = 0; !reg || nread < pst.st_size; nread += save_len) {

usr.bin/script/script.c

571

if (reg)

usr.bin/script/script.c

579

if (reg && stamp.scr_len >

usr.bin/script/script.c

596

(void)consume(fp, stamp.scr_len, buf, reg);

usr.bin/script/script.c

605

(void)consume(fp, stamp.scr_len, buf, reg);

usr.bin/script/script.c

609

(void)consume(fp, stamp.scr_len, buf, reg);

usr.sbin/bhyve/aarch64/bhyverun_machdep.c

262

long reg;

usr.sbin/bhyve/aarch64/bhyverun_machdep.c

264

reg = (addr - arg2) >> 2;

usr.sbin/bhyve/aarch64/bhyverun_machdep.c

266

uart_pl011_write(sc, reg, *val);

usr.sbin/bhyve/aarch64/bhyverun_machdep.c

268

*val = uart_pl011_read(sc, reg);

usr.sbin/bhyve/aarch64/bhyverun_machdep.c

328

long reg;

usr.sbin/bhyve/aarch64/bhyverun_machdep.c

330

reg = addr - arg2;

usr.sbin/bhyve/aarch64/bhyverun_machdep.c

332

rtc_pl031_write(sc, reg, *val);

usr.sbin/bhyve/aarch64/bhyverun_machdep.c

334

*val = rtc_pl031_read(sc, reg);

usr.sbin/bhyve/aarch64/fdt.c

79

void *reg;

usr.sbin/bhyve/aarch64/fdt.c

81

fdt_property_placeholder(fdt, "reg", 2 * sizeof(uint64_t), &reg);

usr.sbin/bhyve/aarch64/fdt.c

82

SET_PROP_U64(reg, 0, start);

usr.sbin/bhyve/aarch64/fdt.c

83

SET_PROP_U64(reg, 1, len);

usr.sbin/bhyve/aarch64/vmexit.c

100

vme->pc, vre->inst_syndrome, vre->reg);

usr.sbin/bhyve/amd64/pci_irq.c

106

if (pirq->reg != (val & (PIRQ_DIS | PIRQ_IRQ))) {

usr.sbin/bhyve/amd64/pci_irq.c

107

if (pirq->active_count != 0 && pirq_valid_irq(pirq->reg))

usr.sbin/bhyve/amd64/pci_irq.c

108

vm_isa_deassert_irq(ctx, pirq->reg & PIRQ_IRQ, -1);

usr.sbin/bhyve/amd64/pci_irq.c

109

pirq->reg = val & (PIRQ_DIS | PIRQ_IRQ);

usr.sbin/bhyve/amd64/pci_irq.c

110

if (pirq->active_count != 0 && pirq_valid_irq(pirq->reg))

usr.sbin/bhyve/amd64/pci_irq.c

111

vm_isa_assert_irq(ctx, pirq->reg & PIRQ_IRQ, -1);

usr.sbin/bhyve/amd64/pci_irq.c

142

pirqs[i].reg = PIRQ_DIS;

usr.sbin/bhyve/amd64/pci_irq.c

167

if (pirq->active_count == 1 && pirq_valid_irq(pirq->reg)) {

usr.sbin/bhyve/amd64/pci_irq.c

168

vm_isa_assert_irq(pi->pi_vmctx, pirq->reg & PIRQ_IRQ,

usr.sbin/bhyve/amd64/pci_irq.c

190

if (pirq->active_count == 0 && pirq_valid_irq(pirq->reg)) {

usr.sbin/bhyve/amd64/pci_irq.c

191

vm_isa_deassert_irq(pi->pi_vmctx, pirq->reg & PIRQ_IRQ,

usr.sbin/bhyve/amd64/pci_irq.c

226

if (pirqs[best_pin].reg == PIRQ_DIS) {

usr.sbin/bhyve/amd64/pci_irq.c

239

pirqs[best_pin].reg = best_irq;

usr.sbin/bhyve/amd64/pci_irq.c

250

return (pirqs[pin - 1].reg & PIRQ_IRQ);

usr.sbin/bhyve/amd64/pci_irq.c

66

uint8_t reg;

usr.sbin/bhyve/amd64/pci_irq.c

82

pirq_valid_irq(int reg)

usr.sbin/bhyve/amd64/pci_irq.c

85

if (reg & PIRQ_DIS)

usr.sbin/bhyve/amd64/pci_irq.c

87

return (IRQ_PERMITTED(reg & PIRQ_IRQ));

usr.sbin/bhyve/amd64/pci_irq.c

95

return (pirqs[pin - 1].reg);

usr.sbin/bhyve/amd64/task_switch.c

100

GETREG(struct vcpu *vcpu, int reg)

usr.sbin/bhyve/amd64/task_switch.c

105

error = vm_get_register(vcpu, reg, &val);

usr.sbin/bhyve/amd64/task_switch.c

111

SETREG(struct vcpu *vcpu, int reg, uint64_t val)

usr.sbin/bhyve/amd64/task_switch.c

115

error = vm_set_register(vcpu, reg, val);

usr.sbin/bhyve/amd64/task_switch.c

177

int error, reg;

usr.sbin/bhyve/amd64/task_switch.c

179

reg = ISLDT(sel) ? VM_REG_GUEST_LDTR : VM_REG_GUEST_GDTR;

usr.sbin/bhyve/amd64/task_switch.c

180

error = vm_get_desc(vcpu, reg, &base, &limit, &access);

usr.sbin/bhyve/amd64/task_switch.c

183

if (reg == VM_REG_GUEST_LDTR) {

usr.sbin/bhyve/amd64/task_switch.c

210

int error, reg;

usr.sbin/bhyve/amd64/task_switch.c

212

reg = ISLDT(sel) ? VM_REG_GUEST_LDTR : VM_REG_GUEST_GDTR;

usr.sbin/bhyve/amd64/task_switch.c

213

error = vm_get_desc(vcpu, reg, &base, &limit, &access);

usr.sbin/bhyve/amd64/task_switch.c

467

update_seg_desc(struct vcpu *vcpu, int reg, struct seg_desc *sd)

usr.sbin/bhyve/amd64/task_switch.c

471

error = vm_set_desc(vcpu, reg, sd->base, sd->limit, sd->access);

usr.sbin/bhyve/gdb.c

1221

uintmax_t reg;

usr.sbin/bhyve/gdb.c

1223

reg = parse_integer(data, len);

usr.sbin/bhyve/gdb.c

1224

if (reg >= nitems(gdb_regset)) {

usr.sbin/bhyve/gdb.c

1229

if (vm_get_register(vcpus[cur_vcpu], gdb_regset[reg].id, &regval) ==

usr.sbin/bhyve/gdb.c

1236

append_unsigned_native(regval, gdb_regset[reg].size);

usr.sbin/bhyve/pci_e82545.c

102

#define E82545_ARRAY_ENTRY(reg, offset) (reg + (offset<<2))

usr.sbin/bhyve/pci_e82545.c

1567

e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval)

usr.sbin/bhyve/pci_e82545.c

1572

idx = reg >> 1;

usr.sbin/bhyve/pci_e82545.c

1577

if (reg & 0x1) {

usr.sbin/bhyve/pci_e82545.c

1593

e82545_read_ra(struct e82545_softc *sc, int reg)

usr.sbin/bhyve/pci_e82545.c

1599

idx = reg >> 1;

usr.sbin/bhyve/pci_e82545.c

1604

if (reg & 0x1) {

usr.sbin/bhyve/pci_emul.c

357

const uint32_t reg, const uint8_t size, const uint32_t def)

usr.sbin/bhyve/pci_emul.c

370

switch (reg) {

usr.sbin/bhyve/pci_emul.h

234

uint32_t reg, uint8_t size, uint32_t def);

usr.sbin/bhyve/pci_passthru.c

170

host_read_config(int fd, const struct pcisel *sel, long reg, int width)

usr.sbin/bhyve/pci_passthru.c

176

pi.pi_reg = reg;

usr.sbin/bhyve/pci_passthru.c

186

passthru_read_config(const struct pcisel *sel, long reg, int width)

usr.sbin/bhyve/pci_passthru.c

188

return (host_read_config(pcifd, sel, reg, width));

usr.sbin/bhyve/pci_passthru.c

192

pci_host_read_config(const struct pcisel *sel, long reg, int width)

usr.sbin/bhyve/pci_passthru.c

200

ret = host_read_config(fd, sel, reg, width);

usr.sbin/bhyve/pci_passthru.c

206

host_write_config(int fd, const struct pcisel *sel, long reg, int width,

usr.sbin/bhyve/pci_passthru.c

213

pi.pi_reg = reg;

usr.sbin/bhyve/pci_passthru.c

221

passthru_write_config(const struct pcisel *sel, long reg, int width,

usr.sbin/bhyve/pci_passthru.c

224

host_write_config(pcifd, sel, reg, width, data);

usr.sbin/bhyve/pci_passthru.c

228

pci_host_write_config(const struct pcisel *sel, long reg, int width,

usr.sbin/bhyve/pci_passthru.c

236

host_write_config(fd, sel, reg, width, data);

usr.sbin/bhyve/pci_passthru.c

739

set_pcir_handler(struct passthru_softc *sc, int reg, int len,

usr.sbin/bhyve/pci_passthru.c

742

if (reg > PCI_REGMAX || reg + len > PCI_REGMAX + 1)

usr.sbin/bhyve/pci_passthru.c

745

for (int i = reg; i < reg + len; ++i) {

usr.sbin/bhyve/pci_passthru.h

43

uint32_t pci_host_read_config(const struct pcisel *sel, long reg, int width);

usr.sbin/bhyve/pci_passthru.h

44

void pci_host_write_config(const struct pcisel *sel, long reg, int width,

usr.sbin/bhyve/pci_passthru.h

54

int set_pcir_handler(struct passthru_softc *sc, int reg, int len,

usr.sbin/bhyve/pci_xhci.c

2180

uint32_t reg;

usr.sbin/bhyve/pci_xhci.c

2199

reg = portregs->portsc;

usr.sbin/bhyve/pci_xhci.c

2202

reg = portregs->portpmsc;

usr.sbin/bhyve/pci_xhci.c

2205

reg = portregs->portli;

usr.sbin/bhyve/pci_xhci.c

2208

reg = portregs->porthlpmc;

usr.sbin/bhyve/pci_xhci.c

2213

reg = 0xffffffff;

usr.sbin/bhyve/pci_xhci.c

2218

offset, port, reg));

usr.sbin/bhyve/pci_xhci.c

2220

return (reg);

usr.sbin/bhyve/riscv/bhyverun_machdep.c

261

long reg;

usr.sbin/bhyve/riscv/bhyverun_machdep.c

263

reg = addr - arg2;

usr.sbin/bhyve/riscv/bhyverun_machdep.c

265

uart_ns16550_write(sc, reg, *val);

usr.sbin/bhyve/riscv/bhyverun_machdep.c

267

*val = uart_ns16550_read(sc, reg);

usr.sbin/bhyve/riscv/fdt.c

81

void *reg;

usr.sbin/bhyve/riscv/fdt.c

83

fdt_property_placeholder(fdt, "reg", 2 * sizeof(uint64_t), &reg);

usr.sbin/bhyve/riscv/fdt.c

84

SET_PROP_U64(reg, 0, start);

usr.sbin/bhyve/riscv/fdt.c

85

SET_PROP_U64(reg, 1, len);

usr.sbin/bhyve/rtc_pl031.c

208

uint32_t reg;

usr.sbin/bhyve/rtc_pl031.c

214

reg = sc->dr;

usr.sbin/bhyve/rtc_pl031.c

217

reg = sc->mr;

usr.sbin/bhyve/rtc_pl031.c

220

reg = sc->lr;

usr.sbin/bhyve/rtc_pl031.c

224

reg = 1;

usr.sbin/bhyve/rtc_pl031.c

227

reg = sc->imsc;

usr.sbin/bhyve/rtc_pl031.c

230

reg = sc->ris;

usr.sbin/bhyve/rtc_pl031.c

233

reg = sc->ris & sc->imsc;

usr.sbin/bhyve/rtc_pl031.c

239

reg = RTCPeriphID_VAL(offset - RTCPeriphID0);

usr.sbin/bhyve/rtc_pl031.c

245

reg = RTCCellID_VAL(offset - RTCCellID0);

usr.sbin/bhyve/rtc_pl031.c

249

reg = 0;

usr.sbin/bhyve/rtc_pl031.c

254

return (reg);

usr.sbin/bhyve/uart_emul.c

337

uint8_t iir, intr_reason, reg;

usr.sbin/bhyve/uart_emul.c

346

reg = sc->dll;

usr.sbin/bhyve/uart_emul.c

351

reg = sc->dlh;

usr.sbin/bhyve/uart_emul.c

358

reg = uart_rxfifo_getchar(sc->backend);

usr.sbin/bhyve/uart_emul.c

361

reg = sc->ier;

usr.sbin/bhyve/uart_emul.c

376

reg = iir;

usr.sbin/bhyve/uart_emul.c

379

reg = sc->lcr;

usr.sbin/bhyve/uart_emul.c

382

reg = sc->mcr;

usr.sbin/bhyve/uart_emul.c

394

reg = sc->lsr;

usr.sbin/bhyve/uart_emul.c

403

reg = sc->msr;

usr.sbin/bhyve/uart_emul.c

407

reg = sc->scr;

usr.sbin/bhyve/uart_emul.c

410

reg = 0xFF;

usr.sbin/bhyve/uart_emul.c

418

return (reg);

usr.sbin/bhyve/uart_pl011.c

273

uint32_t reg;

usr.sbin/bhyve/uart_pl011.c

276

reg = 0;

usr.sbin/bhyve/uart_pl011.c

280

reg = uart_rxfifo_getchar(sc->backend);

usr.sbin/bhyve/uart_pl011.c

288

reg |= sc->rsr << UARTDR_RSR_SHIFT;

usr.sbin/bhyve/uart_pl011.c

295

reg = sc->rsr;

usr.sbin/bhyve/uart_pl011.c

299

reg = UARTFR_TXFE;

usr.sbin/bhyve/uart_pl011.c

304

reg |= UARTFR_RXFF;

usr.sbin/bhyve/uart_pl011.c

306

reg |= UARTFR_RXFE;

usr.sbin/bhyve/uart_pl011.c

310

reg = sc->ibrd;

usr.sbin/bhyve/uart_pl011.c

313

reg = sc->fbrd;

usr.sbin/bhyve/uart_pl011.c

316

reg = sc->lcr_h;

usr.sbin/bhyve/uart_pl011.c

319

reg = sc->cr;

usr.sbin/bhyve/uart_pl011.c

322

reg = sc->imsc;

usr.sbin/bhyve/uart_pl011.c

325

reg = sc->irq_state;

usr.sbin/bhyve/uart_pl011.c

328

reg = sc->irq_state & sc->imsc;

usr.sbin/bhyve/uart_pl011.c

331

reg = 0;

usr.sbin/bhyve/uart_pl011.c

334

reg = UARTPeriphID0_VAL;

usr.sbin/bhyve/uart_pl011.c

337

reg =UARTPeriphID1_VAL;

usr.sbin/bhyve/uart_pl011.c

340

reg = UARTPeriphID2_VAL;

usr.sbin/bhyve/uart_pl011.c

343

reg = UARTPeriphID3_VAL;

usr.sbin/bhyve/uart_pl011.c

346

reg = UARTPCellID0_VAL;

usr.sbin/bhyve/uart_pl011.c

349

reg = UARTPCellID1_VAL;

usr.sbin/bhyve/uart_pl011.c

352

reg = UARTPCellID2_VAL;

usr.sbin/bhyve/uart_pl011.c

355

reg = UARTPCellID3_VAL;

usr.sbin/bhyve/uart_pl011.c

359

reg = 0;

usr.sbin/bhyve/uart_pl011.c

365

return (reg);

usr.sbin/bhyveload/bhyveload.c

605

cb_vm_set_register(void *arg __unused, int vcpuid, int reg, uint64_t val)

usr.sbin/bhyveload/bhyveload.c

609

return (vm_set_register(vcpu, reg, val));

usr.sbin/bhyveload/bhyveload.c

613

cb_vm_set_desc(void *arg __unused, int vcpuid, int reg, uint64_t base,

usr.sbin/bhyveload/bhyveload.c

618

return (vm_set_desc(vcpu, reg, base, limit, access));

usr.sbin/bsnmpd/modules/snmp_netgraph/snmp_netgraph.h

45

void ng_unregister_cookie(void *reg);

usr.sbin/bsnmpd/modules/snmp_netgraph/snmp_netgraph.h

49

void ng_unregister_hook(void *reg);

usr.sbin/cxgbetool/cxgbetool.c

176

struct t4_reg reg;

usr.sbin/cxgbetool/cxgbetool.c

179

reg.addr = (uint32_t) addr;

usr.sbin/cxgbetool/cxgbetool.c

180

reg.size = (uint32_t) size;

usr.sbin/cxgbetool/cxgbetool.c

181

reg.val = 0;

usr.sbin/cxgbetool/cxgbetool.c

183

rc = doit(CHELSIO_T4_GETREG, &reg);

usr.sbin/cxgbetool/cxgbetool.c

185

*val = reg.val;

usr.sbin/cxgbetool/cxgbetool.c

193

struct t4_reg reg;

usr.sbin/cxgbetool/cxgbetool.c

195

reg.addr = (uint32_t) addr;

usr.sbin/cxgbetool/cxgbetool.c

196

reg.size = (uint32_t) size;

usr.sbin/cxgbetool/cxgbetool.c

197

reg.val = (uint64_t) val;

usr.sbin/cxgbetool/cxgbetool.c

199

return doit(CHELSIO_T4_SETREG, &reg);

usr.sbin/dconschat/dconschat.c

275

struct csrreg *reg;

usr.sbin/dconschat/dconschat.c

277

reg = (struct csrreg *)&buf;

usr.sbin/dconschat/dconschat.c

288

printf("%d %02x %06x\n", state, reg->key, reg->val);

usr.sbin/dconschat/dconschat.c

291

if (reg->key == CSRKEY_SPEC &&

usr.sbin/dconschat/dconschat.c

292

reg->val == CSRVAL_VENDOR_PRIVATE)

usr.sbin/dconschat/dconschat.c

296

if (reg->key == CSRKEY_VER &&

usr.sbin/dconschat/dconschat.c

297

reg->val == DCONS_CSR_VAL_VER)

usr.sbin/dconschat/dconschat.c

301

switch (reg->key) {

usr.sbin/dconschat/dconschat.c

303

hi = reg->val;

usr.sbin/dconschat/dconschat.c

306

lo = reg->val;

usr.sbin/dconschat/dconschat.c

309

reset_hi = reg->val;

usr.sbin/dconschat/dconschat.c

312

reset_lo = reg->val;

usr.sbin/dumpcis/cardinfo.h

161

unsigned char reg;

usr.sbin/fwcontrol/fwcontrol.c

337

u_int32_t max, reg, old;

usr.sbin/fwcontrol/fwcontrol.c

349

reg = read_write_quad(fd, devinfo->eui, BUGET_REG, 1, 0);

usr.sbin/fwcontrol/fwcontrol.c

353

devinfo->dst, addr, reg);

usr.sbin/fwcontrol/fwcontrol.c

354

if (reg > 0) {

usr.sbin/fwcontrol/fwcontrol.c

355

old = (reg & 0x3f);

usr.sbin/fwcontrol/fwcontrol.c

356

max = (reg & 0x3f00) >> 8;

usr.sbin/fwcontrol/fwcontrol.c

429

struct csrreg *reg;

usr.sbin/fwcontrol/fwcontrol.c

442

reg = (struct csrreg *)hdr;

usr.sbin/fwcontrol/fwcontrol.c

443

printf("vendor ID: 0x%06x\n", reg->val);

usr.sbin/fwcontrol/fwcontrol.c

472

reg = crom_get(&cc);

usr.sbin/fwcontrol/fwcontrol.c

476

reg->key,

usr.sbin/fwcontrol/fwcontrol.c

477

key_types[(reg->key & CSRTYPE_MASK)>>6],

usr.sbin/fwcontrol/fwcontrol.c

478

reg->key & CSRKEY_MASK, reg->val,

usr.sbin/fwcontrol/fwcontrol.c

562

struct fw_reg_req_t reg;

usr.sbin/fwcontrol/fwcontrol.c

566

reg.addr = offset + i;

usr.sbin/fwcontrol/fwcontrol.c

567

if (ioctl(fd, FWOHCI_RDPHYREG, &reg) < 0)

usr.sbin/fwcontrol/fwcontrol.c

569

buf[i] = (u_int8_t) reg.data;

usr.sbin/fwcontrol/fwcontrol.c

570

printf("0x%02x ", reg.data);

usr.sbin/fwcontrol/fwcontrol.c

578

struct fw_reg_req_t reg;

usr.sbin/fwcontrol/fwcontrol.c

580

reg.addr = 0x7;

usr.sbin/fwcontrol/fwcontrol.c

581

reg.data = ((page & 7) << 5) | (port & 0xf);

usr.sbin/fwcontrol/fwcontrol.c

582

if (ioctl(fd, FWOHCI_WRPHYREG, &reg) < 0)

usr.sbin/pciconf/cap.c

223

uint32_t reg;

usr.sbin/pciconf/cap.c

260

reg = read_config(fd, &p->pc_sel,

usr.sbin/pciconf/cap.c

262

if (reg != 0)

usr.sbin/pciconf/cap.c

263

printf("%08x", reg);

usr.sbin/pciconf/cap.c

264

reg = read_config(fd, &p->pc_sel,

usr.sbin/pciconf/cap.c

266

printf("%08x", reg);

usr.sbin/pciconf/pciconf.c

1174

read_config(int fd, struct pcisel *sel, long reg, int width)

usr.sbin/pciconf/pciconf.c

1179

pi.pi_reg = reg;

usr.sbin/pciconf/pciconf.c

1293

readone(int fd, struct pcisel *sel, long reg, int width)

usr.sbin/pciconf/pciconf.c

1296

printf("%0*x", width*2, read_config(fd, sel, reg, width));

usr.sbin/pciconf/pciconf.c

1300

readit(const char *name, const char *reg, int width)

usr.sbin/pciconf/pciconf.c

1314

rend = rstart = strtol(reg, &end, 0);

usr.sbin/pciconf/pciconf.c

1332

writeit(const char *name, const char *reg, const char *data, int width)

usr.sbin/pciconf/pciconf.c

1338

pi.pi_reg = strtoul(reg, (char **)0, 0); /* XXX error check */

usr.sbin/pciconf/pciconf.c

1372

dump_bar(const char *name, const char *reg, const char *bar_start,

usr.sbin/pciconf/pciconf.c

1400

pbm.pbm_reg = strtoul(reg, &el, 0);

usr.sbin/pciconf/pciconf.c

1401

if (*reg == '\0' || *el != '\0')

usr.sbin/pciconf/pciconf.c

1402

errx(1, "Invalid bar specification %s", reg);

usr.sbin/pciconf/pciconf.c

598

print_window(int reg, const char *type, int range, uint64_t base,

usr.sbin/pciconf/pciconf.c

603

reg, type, range, (uintmax_t)base, (uintmax_t)limit,

usr.sbin/pciconf/pciconf.c

92

static void dump_bar(const char *name, const char *reg, const char *bar_start,

usr.sbin/pciconf/pciconf.h

41

uint32_t read_config(int fd, struct pcisel *sel, long reg, int width);

usr.sbin/pmcstat/pmcstat.c

178

regex_t reg;

usr.sbin/pmcstat/pmcstat.c

204

if ((rv = regcomp(&reg, spec, REG_EXTENDED|REG_NOSUB)) != 0) {

usr.sbin/pmcstat/pmcstat.c

205

regerror(rv, &reg, errbuf, sizeof(errbuf));

usr.sbin/pmcstat/pmcstat.c

211

if ((rv = regexec(&reg, kp->ki_comm, 1, &regmatch, 0)) == 0) {

usr.sbin/pmcstat/pmcstat.c

217

regerror(rv, &reg, errbuf, sizeof(errbuf));

usr.sbin/pmcstat/pmcstat.c

223

regfree(&reg);

usr.sbin/pmcstudy/pmcstudy.c

2340

u_int reg[4];

usr.sbin/pmcstudy/pmcstudy.c

2491

do_cpuid(0xa, 0, reg);

usr.sbin/pmcstudy/pmcstudy.c

2492

max_pmc_counters = (reg[3] & 0x0000000f) + 1;

usr.sbin/rpcbind/pmap_svc.c

164

struct pmap reg;

usr.sbin/rpcbind/pmap_svc.c

171

if (!svc_getargs(xprt, (xdrproc_t) xdr_pmap, (char *)&reg)) {

usr.sbin/rpcbind/pmap_svc.c

180

reg.pm_prog, reg.pm_vers);

usr.sbin/rpcbind/pmap_svc.c

183

if (!check_access(xprt, op, &reg, PMAPVERS)) {

usr.sbin/rpcbind/pmap_svc.c

204

rpcbreg.r_prog = reg.pm_prog;

usr.sbin/rpcbind/pmap_svc.c

205

rpcbreg.r_vers = reg.pm_vers;

usr.sbin/rpcbind/pmap_svc.c

211

(int)((reg.pm_port >> 8) & 0xff),

usr.sbin/rpcbind/pmap_svc.c

212

(int)(reg.pm_port & 0xff));

usr.sbin/rpcbind/pmap_svc.c

214

if (reg.pm_prot == IPPROTO_UDP) {

usr.sbin/rpcbind/pmap_svc.c

216

} else if (reg.pm_prot == IPPROTO_TCP) {

usr.sbin/rpcbind/pmap_svc.c

258

struct pmap reg;

usr.sbin/rpcbind/pmap_svc.c

266

if (!svc_getargs(xprt, (xdrproc_t) xdr_pmap, (char *)&reg)) {

usr.sbin/rpcbind/pmap_svc.c

271

if (!check_access(xprt, PMAPPROC_GETPORT, &reg, PMAPVERS)) {

usr.sbin/rpcbind/pmap_svc.c

281

reg.pm_prog, reg.pm_vers,

usr.sbin/rpcbind/pmap_svc.c

282

reg.pm_prot == IPPROTO_UDP ? "udp" : "tcp", uaddr);

usr.sbin/rpcbind/pmap_svc.c

286

fnd = find_service_pmap(reg.pm_prog, reg.pm_vers, reg.pm_prot);

usr.sbin/rpcbind/pmap_svc.c

292

if (reg.pm_prot == IPPROTO_UDP) {

usr.sbin/rpcbind/pmap_svc.c

311

delete_prog(reg.pm_prog);

usr.sbin/rpcbind/pmap_svc.c

328

rpcbs_getaddr(RPCBVERS_2_STAT, reg.pm_prog, reg.pm_vers,

usr.sbin/rpcbind/pmap_svc.c

329

reg.pm_prot == IPPROTO_UDP ? udptrans : tcptrans,

usr.sbin/rpcbind/rpcb_svc_com.c

150

RPCB reg, *a;

usr.sbin/rpcbind/rpcb_svc_com.c

153

reg = *regp;

usr.sbin/rpcbind/rpcb_svc_com.c

159

fnd = find_service(reg.r_prog, reg.r_vers, reg.r_netid);

usr.sbin/rpcbind/rpcb_svc_com.c

160

if (fnd && (fnd->rpcb_map.r_vers == reg.r_vers)) {

usr.sbin/rpcbind/rpcb_svc_com.c

161

if (!strcmp(fnd->rpcb_map.r_addr, reg.r_addr))

usr.sbin/rpcbind/rpcb_svc_com.c

177

a->r_prog = reg.r_prog;

usr.sbin/rpcbind/rpcb_svc_com.c

178

a->r_vers = reg.r_vers;

usr.sbin/rpcbind/rpcb_svc_com.c

179

a->r_netid = strdup(reg.r_netid);

usr.sbin/rpcbind/rpcb_svc_com.c

180

a->r_addr = strdup(reg.r_addr);

usr.sbin/rpcbind/rpcb_svc_com.c

286

RPCB reg;

usr.sbin/rpcbind/rpcb_svc_com.c

294

reg.r_prog = rbl->rpcb_map.r_prog;

usr.sbin/rpcbind/rpcb_svc_com.c

295

reg.r_vers = rbl->rpcb_map.r_vers;

usr.sbin/rpcbind/rpcb_svc_com.c

296

reg.r_netid = strdup(rbl->rpcb_map.r_netid);

usr.sbin/rpcbind/rpcb_svc_com.c

297

if (reg.r_netid == NULL)

usr.sbin/rpcbind/rpcb_svc_com.c

300

(void)map_unset(&reg, rpcbind_superuser);

usr.sbin/rpcbind/rpcb_svc_com.c

301

free(reg.r_netid);

usr.sbin/uhsoctl/uhsoctl.c

725

int n, reg;

usr.sbin/uhsoctl/uhsoctl.c

727

n = sscanf(resp, "+CREG: %*d,%d", &reg);

usr.sbin/uhsoctl/uhsoctl.c

729

n = sscanf(resp, "+CREG: %d", &reg);

usr.sbin/uhsoctl/uhsoctl.c

741

if (ctx->con_net_stat == reg)

usr.sbin/uhsoctl/uhsoctl.c

744

ctx->con_net_stat = reg;

usr.sbin/uhsoctl/uhsoctl.c

752

int n, reg;

usr.sbin/uhsoctl/uhsoctl.c

754

n = sscanf(resp, "+CGREG: %*d,%d", &reg);

usr.sbin/uhsoctl/uhsoctl.c

756

n = sscanf(resp, "+CGREG: %d", &reg);

usr.sbin/uhsoctl/uhsoctl.c

768

if (ctx->con_net_stat == reg)

usr.sbin/uhsoctl/uhsoctl.c

771

ctx->con_net_stat = reg;

usr.sbin/valectl/valectl.c

255

vale_attach.reg.nr_mode = a->nr_mode;

usr.sbin/valectl/valectl.c

257

&vale_attach.reg.nr_tx_slots,

usr.sbin/valectl/valectl.c

258

&vale_attach.reg.nr_rx_slots,

usr.sbin/valectl/valectl.c

259

&vale_attach.reg.nr_tx_rings,

usr.sbin/valectl/valectl.c

260

&vale_attach.reg.nr_rx_rings);

usr.sbin/valectl/valectl.c

264

vale_attach.reg.nr_mem_id = mem_id;