struct iwx_rx_radiotap_header {
struct ieee80211_radiotap_header wr_ihdr;
uint64_t wr_tsft;
uint8_t wr_flags;
uint8_t wr_rate;
uint16_t wr_chan_freq;
uint16_t wr_chan_flags;
int8_t wr_dbm_antsignal;
int8_t wr_dbm_antnoise;
} __packed;
#define IWX_RX_RADIOTAP_PRESENT \
((1 << IEEE80211_RADIOTAP_TSFT) | \
(1 << IEEE80211_RADIOTAP_FLAGS) | \
(1 << IEEE80211_RADIOTAP_RATE) | \
(1 << IEEE80211_RADIOTAP_CHANNEL) | \
(1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
(1 << IEEE80211_RADIOTAP_DBM_ANTNOISE))
struct iwx_tx_radiotap_header {
struct ieee80211_radiotap_header wt_ihdr;
uint8_t wt_flags;
uint8_t wt_rate;
uint16_t wt_chan_freq;
uint16_t wt_chan_flags;
} __packed;
#define IWX_TX_RADIOTAP_PRESENT \
((1 << IEEE80211_RADIOTAP_FLAGS) | \
(1 << IEEE80211_RADIOTAP_RATE) | \
(1 << IEEE80211_RADIOTAP_CHANNEL))
#define IWX_UCODE_SECT_MAX 57
#define IWX_FW_STATUS_NONE 0
#define IWX_FW_STATUS_INPROGRESS 1
#define IWX_FW_STATUS_DONE 2
enum iwx_ucode_type {
IWX_UCODE_TYPE_REGULAR,
IWX_UCODE_TYPE_INIT,
IWX_UCODE_TYPE_WOW,
IWX_UCODE_TYPE_REGULAR_USNIFFER,
IWX_UCODE_TYPE_MAX
};
struct iwx_fw_info {
void *fw_rawdata;
size_t fw_rawsize;
int fw_status;
struct iwx_fw_sects {
struct iwx_fw_onesect {
const void *fws_data;
uint32_t fws_len;
uint32_t fws_devoff;
} fw_sect[IWX_UCODE_SECT_MAX];
size_t fw_totlen;
int fw_count;
} fw_sects[IWX_UCODE_TYPE_MAX];
int dbg_dest_tlv_init;
const uint8_t *dbg_dest_ver;
uint8_t n_dest_reg;
const struct iwx_fw_dbg_dest_tlv_v1 *dbg_dest_tlv_v1;
const struct iwx_fw_dbg_conf_tlv *dbg_conf_tlv[IWX_FW_DBG_CONF_MAX];
size_t dbg_conf_tlv_len[IWX_FW_DBG_CONF_MAX];
struct iwx_fw_dbg_trigger_tlv *dbg_trigger_tlv[IWX_FW_DBG_TRIGGER_MAX];
size_t dbg_trigger_tlv_len[IWX_FW_DBG_TRIGGER_MAX];
struct iwx_fw_dbg_mem_seg_tlv *dbg_mem_tlv;
size_t n_mem_tlv;
uint8_t *iml;
size_t iml_len;
};
struct iwx_nvm_data {
int n_hw_addrs;
uint8_t hw_addr[ETHER_ADDR_LEN];
int sku_cap_band_24GHz_enable;
int sku_cap_band_52GHz_enable;
int sku_cap_11n_enable;
int sku_cap_11ac_enable;
int sku_cap_11ax_enable;
int sku_cap_amt_enable;
int sku_cap_ipan_enable;
int sku_cap_mimo_disable;
int lar_enabled;
uint8_t valid_tx_ant, valid_rx_ant;
uint16_t nvm_version;
};
#define IWX_MAX_CMD_TBS_PER_TFD 2
struct iwx_host_cmd {
const void *data[IWX_MAX_CMD_TBS_PER_TFD];
struct iwx_rx_packet *resp_pkt;
size_t resp_pkt_len;
unsigned long _rx_page_addr;
uint32_t _rx_page_order;
int handler_status;
uint32_t flags;
uint16_t len[IWX_MAX_CMD_TBS_PER_TFD];
uint8_t dataflags[IWX_MAX_CMD_TBS_PER_TFD];
uint32_t id;
};
struct iwx_dma_info {
bus_dma_tag_t tag;
bus_dmamap_t map;
bus_dma_segment_t seg;
bus_addr_t paddr;
void *vaddr;
bus_size_t size;
};
#define IWX_TX_RING_COUNT IWX_DEFAULT_QUEUE_SIZE
#define IWX_TX_RING_LOMARK 192
#define IWX_TX_RING_HIMARK 224
struct iwx_tx_data {
bus_dmamap_t map;
bus_addr_t cmd_paddr;
struct mbuf *m;
struct iwx_node *in;
int flags;
#define IWX_TXDATA_FLAG_CMD_IS_NARROW 0x01
};
struct iwx_tx_ring {
struct iwx_dma_info desc_dma;
struct iwx_dma_info cmd_dma;
struct iwx_dma_info bc_tbl;
struct iwx_tfh_tfd *desc;
struct iwx_device_cmd *cmd;
struct iwx_tx_data data[IWX_TX_RING_COUNT];
int qid;
int queued;
int cur;
int cur_hw;
int tail;
int tail_hw;
int tid;
bus_dma_tag_t data_dmat;
};
#define IWX_RX_MQ_RING_COUNT 512
#define IWX_RBUF_SIZE 4096
struct iwx_rx_data {
struct mbuf *m;
bus_dmamap_t map;
};
struct iwx_rx_ring {
struct iwx_dma_info free_desc_dma;
struct iwx_dma_info stat_dma;
struct iwx_dma_info used_desc_dma;
void *desc;
struct iwx_rb_status *stat;
struct iwx_rx_data data[IWX_RX_MQ_RING_COUNT];
int cur;
bus_dma_tag_t data_dmat;
};
#define IWX_FLAG_USE_ICT 0x01
#define IWX_FLAG_RFKILL 0x02
#define IWX_FLAG_SCANNING 0x04
#define IWX_FLAG_MAC_ACTIVE 0x08
#define IWX_FLAG_BINDING_ACTIVE 0x10
#define IWX_FLAG_STA_ACTIVE 0x20
#define IWX_FLAG_TE_ACTIVE 0x40
#define IWX_FLAG_HW_ERR 0x80
#define IWX_FLAG_SHUTDOWN 0x100
#define IWX_FLAG_BGSCAN 0x200
#define IWX_FLAG_TXFLUSH 0x400
#define IWX_FLAG_HW_INITED 0x800
struct iwx_ucode_status {
uint32_t uc_lmac_error_event_table[2];
uint32_t uc_umac_error_event_table;
uint32_t uc_log_event_table;
unsigned int error_event_table_tlv_status;
int uc_ok;
int uc_intr;
};
#define IWX_ERROR_EVENT_TABLE_LMAC1 (1 << 0)
#define IWX_ERROR_EVENT_TABLE_LMAC2 (1 << 1)
#define IWX_ERROR_EVENT_TABLE_UMAC (1 << 2)
#define IWX_CMD_RESP_MAX PAGE_SIZE
#define IWX_OTP_LOW_IMAGE_SIZE_FAMILY_7000 16384
#define IWX_OTP_LOW_IMAGE_SIZE_FAMILY_8000 32768
#define IWX_TE_SESSION_PROTECTION_MAX_TIME_MS 1000
#define IWX_TE_SESSION_PROTECTION_MIN_TIME_MS 400
enum IWX_CMD_MODE {
IWX_CMD_ASYNC = (1 << 0),
IWX_CMD_WANT_RESP = (1 << 1),
IWX_CMD_SEND_IN_RFKILL = (1 << 2),
};
enum iwx_hcmd_dataflag {
IWX_HCMD_DFL_NOCOPY = (1 << 0),
IWX_HCMD_DFL_DUP = (1 << 1),
};
#define IWX_NUM_PAPD_CH_GROUPS 9
#define IWX_NUM_TXP_CH_GROUPS 9
struct iwx_phy_ctxt {
uint16_t id;
uint16_t color;
uint32_t ref;
struct ieee80211_channel *channel;
uint8_t sco;
uint8_t vht_chan_width;
};
struct iwx_bf_data {
int bf_enabled;
int ba_enabled;
int ave_beacon_signal;
int last_cqm_event;
};
struct iwx_self_init_dram {
struct iwx_dma_info *fw;
int lmac_cnt;
int umac_cnt;
struct iwx_dma_info *paging;
int paging_cnt;
};
struct iwx_reorder_buffer {
uint16_t head_sn;
uint16_t num_stored;
uint16_t buf_size;
uint16_t last_amsdu;
uint8_t last_sub_index;
struct callout reorder_timer;
int removed;
int valid;
unsigned int consec_oldsn_drops;
uint32_t consec_oldsn_ampdu_gp2;
unsigned int consec_oldsn_prev_drop;
#define IWX_AMPDU_CONSEC_DROPS_DELBA 10
};
struct iwx_reorder_buf_entry {
struct mbufq frames;
struct timeval reorder_time;
uint32_t rx_pkt_status;
int chanidx;
int is_shortpre;
uint32_t rate_n_flags;
uint32_t device_timestamp;
struct ieee80211_rx_stats rxi;
};
struct iwx_rxba_data {
uint8_t sta_id;
uint8_t tid;
uint8_t baid;
uint16_t timeout;
uint16_t entries_per_queue;
struct timeval last_rx;
struct callout session_timer;
struct iwx_softc *sc;
struct iwx_reorder_buffer reorder_buf;
struct iwx_reorder_buf_entry entries[IEEE80211_AGGR_BAWMAX];
};
static inline struct iwx_rxba_data *
iwx_rxba_data_from_reorder_buf(struct iwx_reorder_buffer *buf)
{
return (void *)((uint8_t *)buf -
offsetof(struct iwx_rxba_data, reorder_buf));
}
struct iwx_rxq_dup_data {
uint16_t last_seq[IWX_MAX_TID_COUNT + 1];
uint8_t last_sub_frame[IWX_MAX_TID_COUNT + 1];
};
struct iwx_setkey_task_arg {
int sta_id;
struct ieee80211_node *ni;
struct ieee80211_key *k;
};
struct iwx_ba_task_data {
uint32_t start_tidmask;
uint32_t stop_tidmask;
};
struct iwx_device_cfg {
const char *fw_name;
const char *pnvm_name;
int tx_with_siso_diversity;
int uhb_supported;
int xtal_latency;
int low_latency_xtal;
};
#define IWX_CC_A_FW "iwlwifi-cc-a0-77.ucode"
#define IWX_TY_A_GF_A_FW "iwlwifi-ty-a0-gf-a0-77.ucode"
#define IWX_TY_A_GF_A_PNVM "iwlwifi-ty-a0-gf-a0.pnvm"
#define IWX_QU_B_HR_B_FW "iwlwifi-Qu-b0-hr-b0-77.ucode"
#define IWX_QU_B_JF_B_FW "iwlwifi-Qu-b0-jf-b0-77.ucode"
#define IWX_QU_C_HR_B_FW "iwlwifi-Qu-c0-hr-b0-77.ucode"
#define IWX_QU_C_JF_B_FW "iwlwifi-Qu-c0-jf-b0-77.ucode"
#define IWX_QUZ_A_HR_B_FW "iwlwifi-QuZ-a0-hr-b0-77.ucode"
#define IWX_QUZ_A_JF_B_FW "iwlwifi-QuZ-a0-jf-b0-77.ucode"
#define IWX_SO_A_GF_A_FW "iwlwifi-so-a0-gf-a0-77.ucode"
#define IWX_SO_A_GF_A_PNVM "iwlwifi-so-a0-gf-a0.pnvm"
#define IWX_SO_A_GF4_A_FW "iwlwifi-so-a0-gf4-a0-77.ucode"
#define IWX_SO_A_GF4_A_PNVM "iwlwifi-so-a0-gf4-a0.pnvm"
#define IWX_SO_A_HR_B_FW "iwlwifi-so-a0-hr-b0-77.ucode"
#define IWX_SO_A_JF_B_FW "iwlwifi-so-a0-jf-b0-77.ucode"
const struct iwx_device_cfg iwx_9560_quz_a0_jf_b0_cfg = {
.fw_name = IWX_QUZ_A_JF_B_FW,
};
const struct iwx_device_cfg iwx_9560_qu_c0_jf_b0_cfg = {
.fw_name = IWX_QU_C_JF_B_FW,
};
const struct iwx_device_cfg iwx_qu_b0_hr1_b0 = {
.fw_name = IWX_QU_B_HR_B_FW,
.tx_with_siso_diversity = true,
};
const struct iwx_device_cfg iwx_qu_b0_hr_b0 = {
.fw_name = IWX_QU_B_HR_B_FW,
};
const struct iwx_device_cfg iwx_ax201_cfg_qu_hr = {
.fw_name = IWX_QU_B_HR_B_FW,
};
const struct iwx_device_cfg iwx_qu_c0_hr1_b0 = {
.fw_name = IWX_QU_C_HR_B_FW,
.tx_with_siso_diversity = true,
};
const struct iwx_device_cfg iwx_qu_c0_hr_b0 = {
.fw_name = IWX_QU_C_HR_B_FW,
};
const struct iwx_device_cfg iwx_ax201_cfg_qu_c0_hr_b0 = {
.fw_name = IWX_QU_C_HR_B_FW,
};
const struct iwx_device_cfg iwx_quz_a0_hr1_b0 = {
.fw_name = IWX_QUZ_A_HR_B_FW,
};
const struct iwx_device_cfg iwx_ax201_cfg_quz_hr = {
.fw_name = IWX_QUZ_A_HR_B_FW,
};
const struct iwx_device_cfg iwx_cfg_so_a0_hr_b0 = {
.fw_name = IWX_SO_A_HR_B_FW,
};
const struct iwx_device_cfg iwx_cfg_quz_a0_hr_b0 = {
.fw_name = IWX_QUZ_A_HR_B_FW,
};
const struct iwx_device_cfg iwx_2ax_cfg_so_gf_a0 = {
.fw_name = IWX_SO_A_GF_A_FW,
.pnvm_name = IWX_SO_A_GF_A_PNVM,
.uhb_supported = 1,
};
const struct iwx_device_cfg iwx_2ax_cfg_so_gf_a0_long = {
.fw_name = IWX_SO_A_GF_A_FW,
.pnvm_name = IWX_SO_A_GF_A_PNVM,
.uhb_supported = 1,
.xtal_latency = 12000,
.low_latency_xtal = 1,
};
const struct iwx_device_cfg iwx_2ax_cfg_so_gf4_a0 = {
.fw_name = IWX_SO_A_GF4_A_FW,
.pnvm_name = IWX_SO_A_GF4_A_PNVM,
.uhb_supported = 1,
.xtal_latency = 12000,
.low_latency_xtal = 1,
};
const struct iwx_device_cfg iwx_2ax_cfg_so_gf4_a0_long = {
.fw_name = IWX_SO_A_GF4_A_FW,
.pnvm_name = IWX_SO_A_GF4_A_PNVM,
.uhb_supported = 1,
};
const struct iwx_device_cfg iwx_2ax_cfg_ty_gf_a0 = {
.fw_name = IWX_TY_A_GF_A_FW,
.pnvm_name = IWX_TY_A_GF_A_PNVM,
};
const struct iwx_device_cfg iwx_2ax_cfg_so_jf_b0 = {
.fw_name = IWX_SO_A_JF_B_FW,
};
#define IWX_CFG_ANY (~0)
#define IWX_CFG_MAC_TYPE_QU 0x33
#define IWX_CFG_MAC_TYPE_QUZ 0x35
#define IWX_CFG_MAC_TYPE_QNJ 0x36
#define IWX_CFG_MAC_TYPE_SO 0x37
#define IWX_CFG_MAC_TYPE_SNJ 0x42
#define IWX_CFG_MAC_TYPE_SOF 0x43
#define IWX_CFG_MAC_TYPE_MA 0x44
#define IWX_CFG_MAC_TYPE_BZ 0x46
#define IWX_CFG_MAC_TYPE_GL 0x47
#define IWX_CFG_RF_TYPE_JF2 0x105
#define IWX_CFG_RF_TYPE_JF1 0x108
#define IWX_CFG_RF_TYPE_HR2 0x10a
#define IWX_CFG_RF_TYPE_HR1 0x10c
#define IWX_CFG_RF_TYPE_GF 0x10d
#define IWX_CFG_RF_TYPE_MR 0x110
#define IWX_CFG_RF_TYPE_MS 0x111
#define IWX_CFG_RF_TYPE_FM 0x112
#define IWX_CFG_RF_ID_JF 0x3
#define IWX_CFG_RF_ID_JF1 0x6
#define IWX_CFG_RF_ID_JF1_DIV 0xa
#define IWX_CFG_NO_160 0x1
#define IWX_CFG_160 0x0
#define IWX_CFG_CORES_BT 0x0
#define IWX_CFG_NO_CDB 0x0
#define IWX_CFG_CDB 0x1
#define IWX_SUBDEVICE_RF_ID(subdevice) ((uint16_t)((subdevice) & 0x00f0) >> 4)
#define IWX_SUBDEVICE_NO_160(subdevice) ((uint16_t)((subdevice) & 0x0200) >> 9)
#define IWX_SUBDEVICE_CORES(subdevice) ((uint16_t)((subdevice) & 0x1c00) >> 10)
struct iwx_rx_ba {
int ba_timeout_val;
u_int16_t ba_params;
u_int16_t ba_winstart;
u_int16_t ba_winend;
u_int16_t ba_winsize;
#define IWX_BA_DONE 1
int ba_flags;
};
struct iwx_softc {
device_t sc_dev;
struct ieee80211com sc_ic;
int (*sc_newstate)(struct ieee80211com *, enum ieee80211_state, int);
int sc_newstate_pending;
int attached;
struct task init_task;
struct task newstate_task;
enum ieee80211_state ns_nstate;
int ns_arg;
struct task ba_rx_task;
struct task ba_tx_task;
struct iwx_ba_task_data ba_rx;
struct iwx_ba_task_data ba_tx;
struct task setkey_task;
struct iwx_setkey_task_arg setkey_arg[2];
int setkey_cur;
int setkey_tail;
int setkey_nkeys;
struct task mac_ctxt_task;
struct task phy_ctxt_task;
bus_space_tag_t sc_st;
bus_space_handle_t sc_sh;
bus_size_t sc_sz;
bus_dma_tag_t sc_dmat;
u_int16_t sc_pid;
void *sc_pct;
u_int32_t sc_pcitag;
void *sc_ih;
int sc_msix;
struct iwx_tx_ring txq[IWX_NUM_TX_QUEUES];
struct iwx_rx_ring rxq;
int qfullmsk;
int qenablemsk;
int first_data_qid;
int aggqid[WME_NUM_TID];
int max_tfd_queue_size;
int sc_sf_state;
struct iwx_dma_info ict_dma;
int ict_cur;
int sc_hw_rev;
#define IWX_SILICON_A_STEP 0
#define IWX_SILICON_B_STEP 1
#define IWX_SILICON_C_STEP 2
#define IWX_SILICON_Z_STEP 0xf
int sc_hw_id;
int sc_hw_rf_id;
int sc_device_family;
#define IWX_DEVICE_FAMILY_22000 1
#define IWX_DEVICE_FAMILY_AX210 2
uint32_t sc_sku_id[3];
uint32_t mac_addr_from_csr;
struct iwx_dma_info ctxt_info_dma;
struct iwx_self_init_dram init_dram;
struct iwx_dma_info prph_scratch_dma;
struct iwx_dma_info prph_info_dma;
struct iwx_dma_info iml_dma;
struct iwx_dma_info pnvm_dma;
uint32_t sc_pnvm_ver;
int sc_fw_chunk_done;
int sc_init_complete;
#define IWX_INIT_COMPLETE 0x01
#define IWX_CALIB_COMPLETE 0x02
#define IWX_PNVM_COMPLETE 0x04
struct iwx_ucode_status sc_uc;
char sc_fwver[32];
int sc_capaflags;
int sc_capa_max_probe_len;
int sc_capa_n_scan_channels;
uint8_t sc_ucode_api[howmany(IWX_NUM_UCODE_TLV_API, NBBY)];
uint8_t sc_enabled_capa[howmany(IWX_NUM_UCODE_TLV_CAPA, NBBY)];
#define IWX_MAX_FW_CMD_VERSIONS 704
struct iwx_fw_cmd_version cmd_versions[IWX_MAX_FW_CMD_VERSIONS];
int n_cmd_versions;
int sc_rate_n_flags_version;
int sc_intmask;
int sc_flags;
uint32_t sc_fh_init_mask;
uint32_t sc_hw_init_mask;
uint32_t sc_fh_mask;
uint32_t sc_hw_mask;
int sc_generation;
struct rwlock ioctl_rwl;
int sc_cap_off;
const char *sc_fwname;
struct iwx_fw_info sc_fw;
struct iwx_dma_info fw_mon;
int sc_fw_phy_config;
struct iwx_tlv_calib_ctrl sc_default_calib[IWX_UCODE_TYPE_MAX];
struct iwx_nvm_data sc_nvm;
struct iwx_bf_data sc_bf;
const char *sc_pnvm_name;
int sc_tx_timer[IWX_NUM_TX_QUEUES];
int sc_rx_ba_sessions;
struct task bgscan_done_task;
struct ieee80211_node_switch_bss_arg *bgscan_unref_arg;
size_t bgscan_unref_arg_size;
int sc_scan_last_antenna;
int sc_staid;
int sc_nodecolor;
uint8_t *sc_cmd_resp_pkt[IWX_TX_RING_COUNT];
size_t sc_cmd_resp_len[IWX_TX_RING_COUNT];
int sc_nic_locks;
struct taskq *sc_nswq;
struct iwx_rx_phy_info sc_last_phy_info;
int sc_ampdu_ref;
struct iwx_rxba_data sc_rxba_data[IWX_MAX_BAID];
uint32_t sc_time_event_uid;
struct iwx_phy_ctxt sc_phyctxt[IWX_NUM_PHY_CTX];
struct iwx_notif_statistics sc_stats;
int sc_noise;
int sc_pm_support;
int sc_ltr_enabled;
int sc_integrated;
int sc_tx_with_siso_diversity;
int sc_max_tfd_queue_size;
int sc_ltr_delay;
int sc_xtal_latency;
int sc_low_latency_xtal;
int sc_uhb_supported;
int sc_umac_prph_offset;
int sc_imr_enabled;
caddr_t sc_drvbpf;
union {
struct iwx_rx_radiotap_header th;
uint8_t pad[IEEE80211_RADIOTAP_HDRLEN];
} sc_rxtapu;
#define sc_rxtap sc_rxtapu.th
int sc_rxtap_len;
union {
struct iwx_tx_radiotap_header th;
uint8_t pad[IEEE80211_RADIOTAP_HDRLEN];
} sc_txtapu;
#define sc_txtap sc_txtapu.th
int sc_txtap_len;
struct mtx sc_mtx;
struct resource *sc_mem;
struct resource *sc_irq;
struct intr_config_hook sc_preinit_hook;
struct task sc_es_task;
struct mbufq sc_snd;
struct iwx_rx_ba ni_rx_ba[WME_NUM_TID];
struct taskqueue *sc_tq;
int (*sc_ampdu_rx_start)(struct ieee80211_node *,
struct ieee80211_rx_ampdu *, int, int, int);
void (*sc_ampdu_rx_stop)(struct ieee80211_node *,
struct ieee80211_rx_ampdu *);
int (*sc_addba_request)(struct ieee80211_node *,
struct ieee80211_tx_ampdu *, int, int, int);
int (*sc_addba_response)(struct ieee80211_node *,
struct ieee80211_tx_ampdu *, int, int, int);
struct callout watchdog_to;
const struct firmware *sc_fwp;
const struct firmware *sc_pnvm;
struct iwx_scan_req_umac_v14 sc_umac_v14_cmd;
int sc_rsp_vers;
union {
struct iwx_nvm_get_info_rsp rsp_v4;
struct iwx_nvm_get_info_rsp_v3 rsp_v3;
} sc_rsp_info;
uint32_t sc_debug;
};
#define IWX_LOCK_INIT(_sc) \
mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
MTX_NETWORK_LOCK, MTX_DEF);
#define IWX_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
#define IWX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
#define IWX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
#define IWX_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED);
struct iwx_vap {
struct ieee80211vap iv_vap;
int is_uploaded;
int iv_auth;
int (*iv_newstate)(struct ieee80211vap *,
enum ieee80211_state, int);
struct iwx_phy_ctxt *phy_ctxt;
uint16_t id;
uint16_t color;
boolean_t have_wme;
struct {
uint16_t cw_min;
uint16_t cw_max;
uint16_t edca_txop;
uint8_t aifsn;
} queue_params[WME_NUM_AC];
boolean_t ps_disabled;
};
#define IWX_VAP(_vap) ((struct iwx_vap *)(_vap))
struct iwx_node {
struct ieee80211_node in_ni;
struct iwx_phy_ctxt *in_phyctxt;
uint8_t in_macaddr[ETHER_ADDR_LEN];
uint16_t in_id;
uint16_t in_color;
struct iwx_rxq_dup_data dup_data;
int in_flags;
#define IWX_NODE_FLAG_HAVE_PAIRWISE_KEY 0x01
#define IWX_NODE_FLAG_HAVE_GROUP_KEY 0x02
};
#define IWX_NODE(_ni) ((struct iwx_node *)(_ni))
#define IWX_STATION_ID 0
#define IWX_AUX_STA_ID 1
#define IWX_DEFAULT_MACID 0
#define IWX_DEFAULT_COLOR 0
#define IWX_DEFAULT_TSFID 0
#define IWX_STATION_ID 0
#define IWX_AUX_STA_ID 1
#define IWX_MONITOR_STA_ID 2
#define IWX_ICT_SIZE 4096
#define IWX_ICT_COUNT (IWX_ICT_SIZE / sizeof (uint32_t))
#define IWX_ICT_PADDR_SHIFT 12