#include "opt_platform.h"
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/devmap.h>
#include <sys/lock.h>
#include <sys/reboot.h>
#include <sys/systm.h>
#include <vm/vm.h>
#include <machine/bus.h>
#include <machine/fdt.h>
#include <machine/intr.h>
#include <machine/machdep.h>
#include <machine/platformvar.h>
#include <dev/ofw/openfirm.h>
#include <arm/nvidia/tegra124/tegra124_mp.h>
#include "platform_if.h"
#define PMC_PHYSBASE 0x7000e400
#define PMC_SIZE 0x400
#define PMC_CONTROL_REG 0x0
#define PMC_SCRATCH0 0x50
#define PMC_SCRATCH0_MODE_RECOVERY (1 << 31)
#define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30)
#define PMC_SCRATCH0_MODE_RCM (1 << 1)
#define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
PMC_SCRATCH0_MODE_BOOTLOADER | \
PMC_SCRATCH0_MODE_RCM)
static platform_attach_t tegra124_attach;
static platform_devmap_init_t tegra124_devmap_init;
static platform_late_init_t tegra124_late_init;
static platform_cpu_reset_t tegra124_cpu_reset;
static int
tegra124_attach(platform_t plat)
{
return (0);
}
static void
tegra124_late_init(platform_t plat)
{
}
static int
tegra124_devmap_init(platform_t plat)
{
devmap_add_entry(0x70000000, 0x01000000);
return (0);
}
static void
tegra124_cpu_reset(platform_t plat)
{
bus_space_handle_t pmc;
uint32_t reg;
printf("Resetting...\n");
bus_space_map(fdtbus_bs_tag, PMC_PHYSBASE, PMC_SIZE, 0, &pmc);
reg = bus_space_read_4(fdtbus_bs_tag, pmc, PMC_SCRATCH0);
reg &= PMC_SCRATCH0_MODE_MASK;
bus_space_write_4(fdtbus_bs_tag, pmc, PMC_SCRATCH0,
reg | PMC_SCRATCH0_MODE_BOOTLOADER);
bus_space_read_4(fdtbus_bs_tag, pmc, PMC_SCRATCH0);
reg = bus_space_read_4(fdtbus_bs_tag, pmc, PMC_CONTROL_REG);
spinlock_enter();
dsb();
bus_space_write_4(fdtbus_bs_tag, pmc, PMC_CONTROL_REG, reg | 0x10);
bus_space_read_4(fdtbus_bs_tag, pmc, PMC_CONTROL_REG);
while(1)
;
}
#if 0
#ifdef EARLY_PRINTF
static void
tegra124_early_putc(int c)
{
volatile uint32_t * UART_STAT_REG = (uint32_t *)(0x70006314);
volatile uint32_t * UART_TX_REG = (uint32_t *)(0x70006300);
const uint32_t UART_TXRDY = (1 << 6);
while ((*UART_STAT_REG & UART_TXRDY) == 0)
continue;
*UART_TX_REG = c;
}
early_putc_t *early_putc = tegra124_early_putc;
#endif
#endif
static platform_method_t tegra124_methods[] = {
PLATFORMMETHOD(platform_attach, tegra124_attach),
PLATFORMMETHOD(platform_devmap_init, tegra124_devmap_init),
PLATFORMMETHOD(platform_late_init, tegra124_late_init),
PLATFORMMETHOD(platform_cpu_reset, tegra124_cpu_reset),
#ifdef SMP
PLATFORMMETHOD(platform_mp_start_ap, tegra124_mp_start_ap),
PLATFORMMETHOD(platform_mp_setmaxid, tegra124_mp_setmaxid),
#endif
PLATFORMMETHOD_END,
};
FDT_PLATFORM_DEF(tegra124, "Nvidia Jetson-TK1", 0, "nvidia,jetson-tk1", 120);