lib/libc/arch/aarch64/gen/fpsetmask.c

50

| __SHIFTIN(mask, FPCR_ESUM);

lib/libc/arch/aarch64/gen/fpsetround.c

50

| __SHIFTIN(rnd, FPCR_RMODE);

lib/libc/arch/aarch64/gen/fpsetsticky.c

50

| __SHIFTIN(sticky, FPSR_CSUM);

lib/libc/arch/arm/hardfloat/fpsetround.c

66

fpscr ^= __SHIFTIN(new_rnd ^ old_rnd, VFP_FPSCR_RMODE);

lib/libc/arch/m68k/hardfloat/fpsetmask.c

46

new_fpcr = (old_fpcr & ~FPCR_EXCP2) | __SHIFTIN(new, FPCR_EXCP2);

lib/libc/arch/m68k/hardfloat/fpsetround.c

46

new_fpcr = (old_fpcr & ~FPCR_ROUND) | __SHIFTIN(new, FPCR_ROUND);

lib/libc/arch/m68k/hardfloat/fpsetsticky.c

46

new_fpsr = (old_fpsr & ~FPSR_AEX) | __SHIFTIN(new, FPSR_AEX);

lib/libc/arch/riscv/gen/fpsetmask.c

53

return __SHIFTOUT(fcsr_fmask_write(__SHIFTIN(mask, FCSR_MASK)), FCSR_FMASK);

lib/libc/locale/c16rtomb.c

180

c32 = __SHIFTIN(__SHIFTOUT(w1, __BITS(9,0)), __BITS(19,10)) |

lib/libc/locale/c16rtomb.c

181

__SHIFTIN(__SHIFTOUT(w2, __BITS(9,0)), __BITS(9,0));

lib/libc/locale/c8rtomb.c

216

__SHIFTIN(state, __BITS(31,24)) |

lib/libc/locale/c8rtomb.c

217

__SHIFTIN(c32, __BITS(23,0));

lib/libm/arch/aarch64/fenv.c

111

fpsr |= __SHIFTIN(excepts, FPSR_CSUM);

lib/libm/arch/aarch64/fenv.c

132

fpsr &= ~__SHIFTIN(excepts, FPSR_CSUM);

lib/libm/arch/aarch64/fenv.c

133

fpsr |= __SHIFTIN((*flagp & excepts), FPSR_CSUM);

lib/libm/arch/aarch64/fenv.c

171

fpcr |= __SHIFTIN(round, FPCR_RMODE);

lib/libm/arch/aarch64/fenv.c

240

reg_fpcr_write((__fpcr & ~FPCR_ESUM) | __SHIFTIN(excepts, FPCR_ESUM));

lib/libm/arch/aarch64/fenv.c

248

reg_fpcr_write(__fpcr & ~__SHIFTIN(excepts, FPCR_ESUM));

lib/libm/arch/aarch64/fenv.c

66

.__fpcr = __SHIFTIN(FPCR_RN, FPCR_RMODE),

lib/libm/arch/aarch64/fenv.c

79

unsigned int tmp = reg_fpsr_read() & ~__SHIFTIN(excepts, FPSR_CSUM);

lib/libm/arch/arm/fenv.c

110

fpscr |= __SHIFTIN(excepts, VFP_FPSCR_CSUM);

lib/libm/arch/arm/fenv.c

131

fpscr &= ~__SHIFTIN(excepts, VFP_FPSCR_CSUM);

lib/libm/arch/arm/fenv.c

132

fpscr |= __SHIFTIN((*flagp & excepts), VFP_FPSCR_CSUM);

lib/libm/arch/arm/fenv.c

144

armreg_fpscr_write(fpscr | __SHIFTIN((excepts), VFP_FPSCR_ESUM));

lib/libm/arch/arm/fenv.c

155

armreg_fpscr_write(fpscr & ~__SHIFTIN((excepts), VFP_FPSCR_ESUM));

lib/libm/arch/arm/fenv.c

198

fpscr |= __SHIFTIN(round, VFP_FPSCR_RMODE);

lib/libm/arch/arm/fenv.c

78

int tmp = armreg_fpscr_read() & ~__SHIFTIN(excepts, VFP_FPSCR_CSUM);

lib/libm/arch/riscv/fenv.c

72

const fenv_t __fe_dfl_env = __SHIFTIN(FCSR_FRM_RNE, FCSR_FRM);

lib/libnvmm/libnvmm_x86.c

3387

val = __SHIFTIN(val, instr->dst.u.reg->mask);

lib/libnvmm/libnvmm_x86.c

3402

val = __SHIFTIN(val, instr->src.u.reg->mask);

sbin/efi/devpath5.c

69

#define BIOS_STATUS_MEDIA_NONE __SHIFTIN(0, BIOS_STATUS_MEDIA)

sbin/efi/devpath5.c

70

#define BIOS_STATUS_MEDIA_UNKNOWN __SHIFTIN(1, BIOS_STATUS_MEDIA)

sbin/efi/devpath5.c

71

#define BIOS_STATUS_MEDIA_PRESENT __SHIFTIN(2, BIOS_STATUS_MEDIA)

sbin/efi/devpath5.c

72

#define BIOS_STATUS_MEDIA_RESVD __SHIFTIN(3, BIOS_STATUS_MEDIA)

sys/arch/aarch64/aarch64/aarch64_tlb.c

58

__SHIFTIN(asid, TTBR_ASID) |

sys/arch/aarch64/aarch64/aarch64_tlb.c

59

__SHIFTIN(pmap_l0pa(pm), TTBR_BADDR);

sys/arch/aarch64/aarch64/cpufunc.c

64

reg_csselr_el1_write(__SHIFTIN(level, CSSELR_LEVEL) |

sys/arch/aarch64/aarch64/cpufunc.c

65

__SHIFTIN(insn ? 1 : 0, CSSELR_IND));

sys/arch/aarch64/aarch64/db_machdep.c

720

__SHIFTIN(0, DBGBCR_BT) |

sys/arch/aarch64/aarch64/db_machdep.c

721

__SHIFTIN(0, DBGBCR_LBN) |

sys/arch/aarch64/aarch64/db_machdep.c

722

__SHIFTIN(0, DBGBCR_SSC) |

sys/arch/aarch64/aarch64/db_machdep.c

723

__SHIFTIN(0, DBGBCR_HMC) |

sys/arch/aarch64/aarch64/db_machdep.c

724

__SHIFTIN(15, DBGBCR_BAS) |

sys/arch/aarch64/aarch64/db_machdep.c

725

__SHIFTIN(3, DBGBCR_PMC) |

sys/arch/aarch64/aarch64/db_machdep.c

726

__SHIFTIN(1, DBGBCR_E);

sys/arch/aarch64/aarch64/db_machdep.c

761

__SHIFTIN(0, DBGWCR_MASK) | /* MASK: no mask */

sys/arch/aarch64/aarch64/db_machdep.c

762

__SHIFTIN(0, DBGWCR_WT) | /* WT: 0 */

sys/arch/aarch64/aarch64/db_machdep.c

763

__SHIFTIN(0, DBGWCR_LBN) | /* LBN: 0 */

sys/arch/aarch64/aarch64/db_machdep.c

764

__SHIFTIN(0, DBGWCR_SSC) | /* SSC: 00 */

sys/arch/aarch64/aarch64/db_machdep.c

765

__SHIFTIN(0, DBGWCR_HMC) | /* HMC: 0 */

sys/arch/aarch64/aarch64/db_machdep.c

766

__SHIFTIN(matchbytebit, DBGWCR_BAS) | /* BAS: 0-8byte */

sys/arch/aarch64/aarch64/db_machdep.c

767

__SHIFTIN(accesstype, DBGWCR_LSC) | /* LSC: Load/Store */

sys/arch/aarch64/aarch64/db_machdep.c

768

__SHIFTIN(3, DBGWCR_PAC) | /* PAC: 11 */

sys/arch/aarch64/aarch64/db_machdep.c

769

__SHIFTIN(1, DBGWCR_E); /* Enable */

sys/arch/aarch64/aarch64/fpu.c

101

fpcr |= __SHIFTIN(FPCR_RN, FPCR_RMODE);

sys/arch/aarch64/include/armreg.h

1130

#define TCR_IPS_4PB __SHIFTIN(6,TCR_IPS) /* 52 bits ( 4 PB) */

sys/arch/aarch64/include/armreg.h

1131

#define TCR_IPS_256TB __SHIFTIN(5,TCR_IPS) /* 48 bits (256 TB) */

sys/arch/aarch64/include/armreg.h

1132

#define TCR_IPS_16TB __SHIFTIN(4,TCR_IPS) /* 44 bits (16 TB) */

sys/arch/aarch64/include/armreg.h

1133

#define TCR_IPS_4TB __SHIFTIN(3,TCR_IPS) /* 42 bits ( 4 TB) */

sys/arch/aarch64/include/armreg.h

1134

#define TCR_IPS_1TB __SHIFTIN(2,TCR_IPS) /* 40 bits ( 1 TB) */

sys/arch/aarch64/include/armreg.h

1135

#define TCR_IPS_64GB __SHIFTIN(1,TCR_IPS) /* 36 bits (64 GB) */

sys/arch/aarch64/include/armreg.h

1136

#define TCR_IPS_4GB __SHIFTIN(0,TCR_IPS) /* 32 bits (4 GB) */

sys/arch/aarch64/include/armreg.h

1138

#define TCR_TG1_16KB __SHIFTIN(1,TCR_TG1) /* 16KB page size */

sys/arch/aarch64/include/armreg.h

1139

#define TCR_TG1_4KB __SHIFTIN(2,TCR_TG1) /* 4KB page size */

sys/arch/aarch64/include/armreg.h

1140

#define TCR_TG1_64KB __SHIFTIN(3,TCR_TG1) /* 64KB page size */

sys/arch/aarch64/include/armreg.h

1142

#define TCR_SH1_NONE __SHIFTIN(0,TCR_SH1)

sys/arch/aarch64/include/armreg.h

1143

#define TCR_SH1_OUTER __SHIFTIN(2,TCR_SH1)

sys/arch/aarch64/include/armreg.h

1144

#define TCR_SH1_INNER __SHIFTIN(3,TCR_SH1)

sys/arch/aarch64/include/armreg.h

1146

#define TCR_ORGN1_NC __SHIFTIN(0,TCR_ORGN1) /* Non Cacheable */

sys/arch/aarch64/include/armreg.h

1147

#define TCR_ORGN1_WB_WA __SHIFTIN(1,TCR_ORGN1) /* WriteBack WriteAllocate */

sys/arch/aarch64/include/armreg.h

1148

#define TCR_ORGN1_WT __SHIFTIN(2,TCR_ORGN1) /* WriteThrough */

sys/arch/aarch64/include/armreg.h

1149

#define TCR_ORGN1_WB __SHIFTIN(3,TCR_ORGN1) /* WriteBack */

sys/arch/aarch64/include/armreg.h

1151

#define TCR_IRGN1_NC __SHIFTIN(0,TCR_IRGN1) /* Non Cacheable */

sys/arch/aarch64/include/armreg.h

1152

#define TCR_IRGN1_WB_WA __SHIFTIN(1,TCR_IRGN1) /* WriteBack WriteAllocate */

sys/arch/aarch64/include/armreg.h

1153

#define TCR_IRGN1_WT __SHIFTIN(2,TCR_IRGN1) /* WriteThrough */

sys/arch/aarch64/include/armreg.h

1154

#define TCR_IRGN1_WB __SHIFTIN(3,TCR_IRGN1) /* WriteBack */

sys/arch/aarch64/include/armreg.h

1159

#define TCR_TG0_4KB __SHIFTIN(0,TCR_TG0) /* 4KB page size */

sys/arch/aarch64/include/armreg.h

1160

#define TCR_TG0_64KB __SHIFTIN(1,TCR_TG0) /* 64KB page size */

sys/arch/aarch64/include/armreg.h

1161

#define TCR_TG0_16KB __SHIFTIN(2,TCR_TG0) /* 16KB page size */

sys/arch/aarch64/include/armreg.h

1163

#define TCR_SH0_NONE __SHIFTIN(0,TCR_SH0)

sys/arch/aarch64/include/armreg.h

1164

#define TCR_SH0_OUTER __SHIFTIN(2,TCR_SH0)

sys/arch/aarch64/include/armreg.h

1165

#define TCR_SH0_INNER __SHIFTIN(3,TCR_SH0)

sys/arch/aarch64/include/armreg.h

1167

#define TCR_ORGN0_NC __SHIFTIN(0,TCR_ORGN0) /* Non Cacheable */

sys/arch/aarch64/include/armreg.h

1168

#define TCR_ORGN0_WB_WA __SHIFTIN(1,TCR_ORGN0) /* WriteBack WriteAllocate */

sys/arch/aarch64/include/armreg.h

1169

#define TCR_ORGN0_WT __SHIFTIN(2,TCR_ORGN0) /* WriteThrough */

sys/arch/aarch64/include/armreg.h

1170

#define TCR_ORGN0_WB __SHIFTIN(3,TCR_ORGN0) /* WriteBack */

sys/arch/aarch64/include/armreg.h

1172

#define TCR_IRGN0_NC __SHIFTIN(0,TCR_IRGN0) /* Non Cacheable */

sys/arch/aarch64/include/armreg.h

1173

#define TCR_IRGN0_WB_WA __SHIFTIN(1,TCR_IRGN0) /* WriteBack WriteAllocate */

sys/arch/aarch64/include/armreg.h

1174

#define TCR_IRGN0_WT __SHIFTIN(2,TCR_IRGN0) /* WriteThrough */

sys/arch/aarch64/include/armreg.h

1175

#define TCR_IRGN0_WB __SHIFTIN(3,TCR_IRGN0) /* WriteBack */

sys/arch/aarch64/include/armreg.h

1201

#define TCR_EL2_TG0_4KB __SHIFTIN(0,TCR_EL2_TG0) // 4KB page size

sys/arch/aarch64/include/armreg.h

1202

#define TCR_EL2_TG0_64KB __SHIFTIN(1,TCR_EL2_TG0) // 64KB page size

sys/arch/aarch64/include/armreg.h

1203

#define TCR_EL2_TG0_16KB __SHIFTIN(2,TCR_EL2_TG0) // 16KB page size

sys/arch/aarch64/include/armreg.h

1205

#define TCR_EL2_SH0_NONE __SHIFTIN(0,TCR_EL2_SH0) // non-shareable

sys/arch/aarch64/include/armreg.h

1206

#define TCR_EL2_SH0_OUTER __SHIFTIN(2,TCR_EL2_SH0) // Outer shareable

sys/arch/aarch64/include/armreg.h

1207

#define TCR_EL2_SH0_INNER __SHIFTIN(3,TCR_EL2_SH0) // Inner shareable

sys/arch/aarch64/include/armreg.h

1209

#define TCR_EL2_ORGN0_NC __SHIFTIN(0,TCR_EL2_ORGN0) // Non Cacheable

sys/arch/aarch64/include/armreg.h

1210

#define TCR_EL2_ORGN0_WB_WA __SHIFTIN(1,TCR_EL2_ORGN0) // WriteBack WriteAllocate

sys/arch/aarch64/include/armreg.h

1211

#define TCR_EL2_ORGN0_WT __SHIFTIN(2,TCR_EL2_ORGN0) // WriteThrough

sys/arch/aarch64/include/armreg.h

1212

#define TCR_EL2_ORGN0_WB __SHIFTIN(3,TCR_EL2_ORGN0) // WriteBack

sys/arch/aarch64/include/armreg.h

1214

#define TCR_EL2_IRGN0_NC __SHIFTIN(0,TCR_EL2_IRGN0) // Non Cacheable

sys/arch/aarch64/include/armreg.h

1215

#define TCR_EL2_IRGN0_WB_WA __SHIFTIN(1,TCR_EL2_IRGN0) // WriteBack WriteAllocate

sys/arch/aarch64/include/armreg.h

1216

#define TCR_EL2_IRGN0_WT __SHIFTIN(2,TCR_EL2_IRGN0) // WriteThrough

sys/arch/aarch64/include/armreg.h

1217

#define TCR_EL2_IRGN0_WB __SHIFTIN(3,TCR_EL2_IRGN0) // WriteBack

sys/arch/aarch64/include/armreg.h

635

#define CPACR_FPEN_NONE __SHIFTIN(0, CPACR_FPEN)

sys/arch/aarch64/include/armreg.h

636

#define CPACR_FPEN_EL1 __SHIFTIN(1, CPACR_FPEN)

sys/arch/aarch64/include/armreg.h

637

#define CPACR_FPEN_NONE_2 __SHIFTIN(2, CPACR_FPEN)

sys/arch/aarch64/include/armreg.h

638

#define CPACR_FPEN_ALL __SHIFTIN(3, CPACR_FPEN)

sys/arch/aarch64/include/pmap.h

185

#define ARM_MMAP_WRITECOMBINE __SHIFTIN(AARCH64_MMAP_WRITECOMBINE, ARM_MMAP_MASK)

sys/arch/aarch64/include/pmap.h

186

#define ARM_MMAP_WRITEBACK __SHIFTIN(AARCH64_MMAP_WRITEBACK, ARM_MMAP_MASK)

sys/arch/aarch64/include/pmap.h

187

#define ARM_MMAP_NOCACHE __SHIFTIN(AARCH64_MMAP_NOCACHE, ARM_MMAP_MASK)

sys/arch/aarch64/include/pmap.h

188

#define ARM_MMAP_DEVICE __SHIFTIN(AARCH64_MMAP_DEVICE, ARM_MMAP_MASK)

sys/arch/aarch64/include/pmap.h

423

__SHIFTIN(asid, TTBR_ASID) |

sys/arch/aarch64/include/pmap.h

424

__SHIFTIN(pmap_l0pa(pm), TTBR_BADDR);

sys/arch/aarch64/include/pmap.h

87

#define LX_BLKPAG_ATTR_NORMAL_WB __SHIFTIN(0, LX_BLKPAG_ATTR_INDX)

sys/arch/aarch64/include/pmap.h

88

#define LX_BLKPAG_ATTR_NORMAL_NC __SHIFTIN(1, LX_BLKPAG_ATTR_INDX)

sys/arch/aarch64/include/pmap.h

89

#define LX_BLKPAG_ATTR_NORMAL_WT __SHIFTIN(2, LX_BLKPAG_ATTR_INDX)

sys/arch/aarch64/include/pmap.h

90

#define LX_BLKPAG_ATTR_DEVICE_MEM __SHIFTIN(3, LX_BLKPAG_ATTR_INDX)

sys/arch/aarch64/include/pmap.h

91

#define LX_BLKPAG_ATTR_DEVICE_MEM_NP __SHIFTIN(4, LX_BLKPAG_ATTR_INDX)

sys/arch/aarch64/include/pte.h

100

#define LX_S2_BLKPAG_MEMATTR_nGRE __SHIFTIN(0x2,LX_S2_BLKPAG_MEMATTR)

sys/arch/aarch64/include/pte.h

101

#define LX_S2_BLKPAG_MEMATTR_GRE __SHIFTIN(0x3,LX_S2_BLKPAG_MEMATTR)

sys/arch/aarch64/include/pte.h

102

#define LX_S2_BLKPAG_MEMATTR_NC __SHIFTIN(0x5,LX_S2_BLKPAG_MEMATTR)

sys/arch/aarch64/include/pte.h

103

#define LX_S2_BLKPAG_MEMATTR_WT __SHIFTIN(0xa,LX_S2_BLKPAG_MEMATTR)

sys/arch/aarch64/include/pte.h

104

#define LX_S2_BLKPAG_MEMATTR_WB __SHIFTIN(0xf,LX_S2_BLKPAG_MEMATTR)

sys/arch/aarch64/include/pte.h

107

#define LX_TYPE_BLK __SHIFTIN(0, LX_TYPE)

sys/arch/aarch64/include/pte.h

108

#define LX_TYPE_TBL __SHIFTIN(1, LX_TYPE)

sys/arch/aarch64/include/pte.h

109

#define L3_TYPE_PAG __SHIFTIN(1, LX_TYPE)

sys/arch/aarch64/include/pte.h

53

#define LX_TBL_APTABLE_NOEFFECT __SHIFTIN(0,LX_TBL_APTABLE)

sys/arch/aarch64/include/pte.h

54

#define LX_TBL_APTABLE_EL0_NOACCESS __SHIFTIN(1,LX_TBL_APTABLE)

sys/arch/aarch64/include/pte.h

55

#define LX_TBL_APTABLE_RO __SHIFTIN(2,LX_TBL_APTABLE)

sys/arch/aarch64/include/pte.h

56

#define LX_TBL_APTABLE_RO_EL0_NOREAD __SHIFTIN(3,LX_TBL_APTABLE)

sys/arch/aarch64/include/pte.h

60

#define LX_BLKPAG_OS_0 __SHIFTIN(1,LX_BLKPAG_OS)

sys/arch/aarch64/include/pte.h

61

#define LX_BLKPAG_OS_1 __SHIFTIN(2,LX_BLKPAG_OS)

sys/arch/aarch64/include/pte.h

62

#define LX_BLKPAG_OS_2 __SHIFTIN(4,LX_BLKPAG_OS)

sys/arch/aarch64/include/pte.h

63

#define LX_BLKPAG_OS_3 __SHIFTIN(8,LX_BLKPAG_OS)

sys/arch/aarch64/include/pte.h

68

#define LX_S2_BLKPAG_XN_XN __SHIFTIN(1,LX_S2_BLKPAG_XN)

sys/arch/aarch64/include/pte.h

78

#define LX_BLKPAG_SH_NS __SHIFTIN(0,LX_BLKPAG_SH) /* Non Shareable */

sys/arch/aarch64/include/pte.h

79

#define LX_BLKPAG_SH_OS __SHIFTIN(2,LX_BLKPAG_SH) /* Outer Shareable */

sys/arch/aarch64/include/pte.h

80

#define LX_BLKPAG_SH_IS __SHIFTIN(3,LX_BLKPAG_SH) /* Inner Shareable */

sys/arch/aarch64/include/pte.h

82

#define LX_BLKPAG_AP_RW __SHIFTIN(0,LX_BLKPAG_AP) /* RW */

sys/arch/aarch64/include/pte.h

83

#define LX_BLKPAG_AP_RO __SHIFTIN(1,LX_BLKPAG_AP) /* RO */

sys/arch/aarch64/include/pte.h

87

#define LX_S2_BLKPAG_S2AP_NA __SHIFTIN(0,LX_S2_BLKPAG_S2AP) /* No access */

sys/arch/aarch64/include/pte.h

88

#define LX_S2_BLKPAG_S2AP_RO __SHIFTIN(1,LX_S2_BLKPAG_S2AP) /* Read-only */

sys/arch/aarch64/include/pte.h

89

#define LX_S2_BLKPAG_S2AP_WO __SHIFTIN(2,LX_S2_BLKPAG_S2AP) /* Write-only */

sys/arch/aarch64/include/pte.h

90

#define LX_S2_BLKPAG_S2AP_RW __SHIFTIN(3,LX_S2_BLKPAG_S2AP) /* Read/Write */

sys/arch/aarch64/include/pte.h

93

#define LX_BLKPAG_ATTR_INDX_0 __SHIFTIN(0,LX_BLKPAG_ATTR_INDX)

sys/arch/aarch64/include/pte.h

94

#define LX_BLKPAG_ATTR_INDX_1 __SHIFTIN(1,LX_BLKPAG_ATTR_INDX)

sys/arch/aarch64/include/pte.h

95

#define LX_BLKPAG_ATTR_INDX_2 __SHIFTIN(2,LX_BLKPAG_ATTR_INDX)

sys/arch/aarch64/include/pte.h

96

#define LX_BLKPAG_ATTR_INDX_3 __SHIFTIN(3,LX_BLKPAG_ATTR_INDX)

sys/arch/aarch64/include/pte.h

98

#define LX_S2_BLKPAG_MEMATTR_nGnRnE __SHIFTIN(0x0,LX_S2_BLKPAG_MEMATTR)

sys/arch/aarch64/include/pte.h

99

#define LX_S2_BLKPAG_MEMATTR_nGnRE __SHIFTIN(0x1,LX_S2_BLKPAG_MEMATTR)

sys/arch/alpha/alpha/fp_complete.c

662

fpcr = (fpcr & ~FPCR_DYN_RM) | __SHIFTIN(rm, FPCR_DYN_RM);

sys/arch/alpha/include/fpu.h

76

#define FPCR_DEFAULT (__SHIFTIN(FP_RN, FPCR_DYN_RM) | \

sys/arch/alpha/pci/lca_pci.c

72

return PCI_CONF_TYPE0_IDSEL(d) | __SHIFTIN(f, PCI_CONF_TYPE0_FUNCTION);

sys/arch/alpha/pci/pci_machdep.c

464

ihp->value = __SHIFTIN(irq, ALPHA_PCI_INTR_HANDLE_IRQ) |

sys/arch/alpha/pci/pci_machdep.c

465

__SHIFTIN(flags, ALPHA_PCI_INTR_HANDLE_FLAGS);

sys/arch/alpha/pci/pci_machdep.c

472

__SHIFTIN(irq, ALPHA_PCI_INTR_HANDLE_IRQ);

sys/arch/alpha/pci/pci_machdep.c

486

__SHIFTIN(flags, ALPHA_PCI_INTR_HANDLE_FLAGS);

sys/arch/alpha/pci/pci_machdep.c

526

return __SHIFTIN(bus, PCI_CONF_TYPE1_BUS) |

sys/arch/alpha/pci/pci_machdep.c

527

__SHIFTIN(dev, PCI_CONF_TYPE1_DEVICE) |

sys/arch/alpha/pci/pci_machdep.c

528

__SHIFTIN(func, PCI_CONF_TYPE1_FUNCTION);

sys/arch/alpha/pci/ttwoga_pci.c

104

return PCI_CONF_TYPE0_IDSEL(d) | __SHIFTIN(f, PCI_CONF_TYPE1_FUNCTION);

sys/arch/amd64/include/msan.h

201

ret |= __SHIFTIN(type, __MD_ORIG_TYPE);

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

91

val |= __SHIFTIN(page_index, PAB_CTRL_PAGE_SEL);

sys/arch/arm/amlogic/gxlphy.c

111

__SHIFTIN(bank, TSTCNTL_REG_BANK_SEL) |

sys/arch/arm/amlogic/gxlphy.c

112

__SHIFTIN(reg, TSTCNTL_READ_ADDR));

sys/arch/arm/amlogic/gxlphy.c

126

__SHIFTIN(bank, TSTCNTL_REG_BANK_SEL) |

sys/arch/arm/amlogic/gxlphy.c

127

__SHIFTIN(reg, TSTCNTL_WRITE_ADDR));

sys/arch/arm/amlogic/meson6_timer.c

148

mask |= __SHIFTIN(MESON_TIMER_MUX_TIMERE_INPUT_CLOCK_1US, MESON_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK);

sys/arch/arm/amlogic/meson8b_clkc.c

151

cntl |= __SHIFTIN(new_mul, HHI_SYS_PLL_CNTL_MUL);

sys/arch/arm/amlogic/meson8b_clkc.c

153

cntl |= __SHIFTIN(new_div, HHI_SYS_PLL_CNTL_DIV);

sys/arch/arm/amlogic/meson8b_clkc.c

155

cntl |= __SHIFTIN(new_od, HHI_SYS_PLL_CNTL_OD);

sys/arch/arm/amlogic/meson_clk.h

396

_cwb_tmp_ |= __SHIFTIN((val), (mask)); \

sys/arch/arm/amlogic/meson_clk_div.c

128

val |= __SHIFTIN(raw_div, div->div);

sys/arch/arm/amlogic/meson_dwmac.c

151

val |= __SHIFTIN((tx_delay >> 1), TX_CLK_DELAY);

sys/arch/arm/amlogic/meson_dwmac.c

153

val |= __SHIFTIN(div, MP2_CLK_OUT_DIV);

sys/arch/arm/amlogic/meson_genfb.c

309

datal |= __SHIFTIN(w & 7, DC_CAV_LUT_DATAL_WIDTH_L);

sys/arch/arm/amlogic/meson_genfb.c

311

datal |= __SHIFTIN(pa >> 3, DC_CAV_LUT_DATAL_FBADDR);

sys/arch/arm/amlogic/meson_genfb.c

315

datah |= __SHIFTIN(DC_CAV_LUT_DATAH_BLKMODE_LINEAR,

sys/arch/arm/amlogic/meson_genfb.c

318

datah |= __SHIFTIN(w >> 3, DC_CAV_LUT_DATAH_WIDTH_H);

sys/arch/arm/amlogic/meson_genfb.c

320

datah |= __SHIFTIN(h, DC_CAV_LUT_DATAH_HEIGHT);

sys/arch/arm/amlogic/meson_genfb.c

343

cs |= __SHIFTIN(0xff, VIU_OSD_CTRL_STAT_GLOBAL_ALPHA);

sys/arch/arm/amlogic/meson_genfb.c

350

tc = __SHIFTIN(0, VIU_OSD_TCOLOR_R) |

sys/arch/arm/amlogic/meson_genfb.c

351

__SHIFTIN(0, VIU_OSD_TCOLOR_G) |

sys/arch/arm/amlogic/meson_genfb.c

352

__SHIFTIN(0, VIU_OSD_TCOLOR_B) |

sys/arch/arm/amlogic/meson_genfb.c

353

__SHIFTIN(255, VIU_OSD_TCOLOR_A);

sys/arch/arm/amlogic/meson_genfb.c

363

w0 |= __SHIFTIN(VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_32BPP,

sys/arch/arm/amlogic/meson_genfb.c

365

w0 |= __SHIFTIN(VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_ARGB,

sys/arch/arm/amlogic/meson_genfb.c

369

w0 |= __SHIFTIN(VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_24BPP,

sys/arch/arm/amlogic/meson_genfb.c

371

w0 |= __SHIFTIN(VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_RGB,

sys/arch/arm/amlogic/meson_genfb.c

375

w0 |= __SHIFTIN(VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_16BPP,

sys/arch/arm/amlogic/meson_genfb.c

377

w0 |= __SHIFTIN(VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_RGB565,

sys/arch/arm/amlogic/meson_genfb.c

391

w1 = __SHIFTIN(width - 1, VIU_OSD_BLK_CFG_W1_X_END) |

sys/arch/arm/amlogic/meson_genfb.c

392

__SHIFTIN(0, VIU_OSD_BLK_CFG_W1_X_START);

sys/arch/arm/amlogic/meson_genfb.c

393

w2 = __SHIFTIN(height - 1, VIU_OSD_BLK_CFG_W2_Y_END) |

sys/arch/arm/amlogic/meson_genfb.c

394

__SHIFTIN(0, VIU_OSD_BLK_CFG_W2_Y_START);

sys/arch/arm/amlogic/meson_genfb.c

395

w3 = __SHIFTIN(width - 1, VIU_OSD_BLK_CFG_W3_H_END) |

sys/arch/arm/amlogic/meson_genfb.c

396

__SHIFTIN(0, VIU_OSD_BLK_CFG_W3_H_START);

sys/arch/arm/amlogic/meson_genfb.c

397

w4 = __SHIFTIN(height - 1, VIU_OSD_BLK_CFG_W4_V_END) |

sys/arch/arm/amlogic/meson_genfb.c

398

__SHIFTIN(0, VIU_OSD_BLK_CFG_W4_V_START);

sys/arch/arm/amlogic/meson_genfb.c

430

scctl |= __SHIFTIN(1, VPP_OSD_SC_CTRL0_OSD_SC_SEL); /* OSD2 */

sys/arch/arm/amlogic/meson_genfb.c

432

scctl |= __SHIFTIN(0, VPP_OSD_SC_CTRL0_DEFAULT_ALPHA);

sys/arch/arm/amlogic/meson_genfb.c

435

sci_wh = __SHIFTIN(width - 1, VPP_OSD_SCI_WH_M1_WIDTH) |

sys/arch/arm/amlogic/meson_genfb.c

436

__SHIFTIN((height >> interlace_p) - 1, VPP_OSD_SCI_WH_M1_HEIGHT);

sys/arch/arm/amlogic/meson_genfb.c

437

sco_h = __SHIFTIN(margin_w, VPP_OSD_SCO_H_START) |

sys/arch/arm/amlogic/meson_genfb.c

438

__SHIFTIN(width - margin_w - 1, VPP_OSD_SCO_H_END);

sys/arch/arm/amlogic/meson_genfb.c

439

sco_v = __SHIFTIN(margin_h >> interlace_p, VPP_OSD_SCO_V_START) |

sys/arch/arm/amlogic/meson_genfb.c

440

__SHIFTIN(((height - margin_h) >> interlace_p) - 1,

sys/arch/arm/amlogic/meson_genfb.c

451

hsc |= __SHIFTIN(4, VPP_OSD_HSC_CTRL0_BANK_LENGTH);

sys/arch/arm/amlogic/meson_genfb.c

453

hsc |= __SHIFTIN(4, VPP_OSD_HSC_CTRL0_INI_RCV_NUM0);

sys/arch/arm/amlogic/meson_genfb.c

455

hsc |= __SHIFTIN(1, VPP_OSD_HSC_CTRL0_RPT_P0_NUM0);

sys/arch/arm/amlogic/meson_genfb.c

466

vsc |= __SHIFTIN(4, VPP_OSD_VSC_CTRL0_BANK_LENGTH);

sys/arch/arm/amlogic/meson_genfb.c

468

vsc |= __SHIFTIN(4, VPP_OSD_VSC_CTRL0_TOP_INI_RCV_NUM0);

sys/arch/arm/amlogic/meson_genfb.c

470

vsc |= __SHIFTIN(1, VPP_OSD_VSC_CTRL0_TOP_RPT_P0_NUM0);

sys/arch/arm/amlogic/meson_genfb.c

477

vsc |= __SHIFTIN(6, VPP_OSD_VSC_CTRL0_BOT_INI_RCV_NUM0);

sys/arch/arm/amlogic/meson_genfb.c

478

vsc |= __SHIFTIN(2, VPP_OSD_VSC_CTRL0_BOT_RPT_P0_NUM0);

sys/arch/arm/amlogic/meson_genfb.c

495

hps |= __SHIFTIN(hf_phase_step, VPP_OSD_HSC_PHASE_STEP_FORMAT);

sys/arch/arm/amlogic/meson_genfb.c

504

vps |= __SHIFTIN(hf_phase_step, VPP_OSD_VSC_PHASE_STEP_FORMAT);

sys/arch/arm/amlogic/meson_genfb.c

509

vip |= __SHIFTIN(0, VPP_OSD_VSC_INI_PHASE_1);

sys/arch/arm/amlogic/meson_genfb.c

511

vip |= __SHIFTIN(bot_ini_phase, VPP_OSD_VSC_INI_PHASE_0);

sys/arch/arm/amlogic/meson_pinctrl.c

152

val |= __SHIFTIN(group->func, group->mask);

sys/arch/arm/amlogic/meson_platform.c

316

MESON8B_WATCHDOG_TC_CPUS | MESON8B_WATCHDOG_TC_ENABLE | __SHIFTIN(0xfff, MESON8B_WATCHDOG_TC_TCNT));

sys/arch/arm/amlogic/meson_pwm.c

223

val |= __SHIFTIN(clk_div, MESON_PWM_MISC_AB_A_CLK_DIV);

sys/arch/arm/amlogic/meson_pwm.c

225

val |= __SHIFTIN(sc->sc_clksource, MESON_PWM_MISC_AB_A_CLK_SEL);

sys/arch/arm/amlogic/meson_pwm.c

234

__SHIFTIN(hi, MESON_PWM_DUTYCYCLE_HIGH) |

sys/arch/arm/amlogic/meson_pwm.c

235

__SHIFTIN(lo, MESON_PWM_DUTYCYCLE_LOW));

sys/arch/arm/amlogic/meson_pwm.c

243

val |= __SHIFTIN(clk_div, MESON_PWM_MISC_AB_B_CLK_DIV);

sys/arch/arm/amlogic/meson_pwm.c

245

val |= __SHIFTIN(sc->sc_clksource, MESON_PWM_MISC_AB_B_CLK_SEL);

sys/arch/arm/amlogic/meson_pwm.c

254

__SHIFTIN(hi, MESON_PWM_DUTYCYCLE_HIGH) |

sys/arch/arm/amlogic/meson_pwm.c

255

__SHIFTIN(lo, MESON_PWM_DUTYCYCLE_LOW));

sys/arch/arm/amlogic/meson_rtc.c

281

u |= __SHIFTIN(data, AO_RTC_REG4_STATIC_REG_MSB);

sys/arch/arm/amlogic/meson_rtc.c

287

u |= __SHIFTIN(data, AO_RTC_REG0_STATIC_REG_LSB);

sys/arch/arm/amlogic/meson_sdhc.c

408

clkc |= __SHIFTIN(SD_CLKC_CLK_IN_SEL_FCLK_DIV3,

sys/arch/arm/amlogic/meson_sdhc.c

414

clkc |= __SHIFTIN(clk_div - 1, SD_CLKC_CLK_DIV);

sys/arch/arm/amlogic/meson_sdhc.c

428

clk2 |= __SHIFTIN(1, SD_CLK2_SD_CLK_PHASE);

sys/arch/arm/amlogic/meson_sdhc.c

430

clk2 |= __SHIFTIN(meson_sdhc_default_rx_phase(sc),

sys/arch/arm/amlogic/meson_sdhc.c

495

__SHIFTIN(0x7, SD_CNTL_TX_ENDIAN_CTRL) |

sys/arch/arm/amlogic/meson_sdhc.c

496

__SHIFTIN(0x7, SD_CNTL_RX_ENDIAN_CTRL) |

sys/arch/arm/amlogic/meson_sdhc.c

497

__SHIFTIN(0xf, SD_CNTL_RX_PERIOD) |

sys/arch/arm/amlogic/meson_sdhc.c

498

__SHIFTIN(0x7f, SD_CNTL_RX_TIMEOUT));

sys/arch/arm/amlogic/meson_sdhc.c

504

__SHIFTIN(7, SD_PDMA_TX_BURST_LEN) |

sys/arch/arm/amlogic/meson_sdhc.c

505

__SHIFTIN(49, SD_PDMA_TXFIFO_THRESHOLD) |

sys/arch/arm/amlogic/meson_sdhc.c

506

__SHIFTIN(15, SD_PDMA_RX_BURST_LEN) |

sys/arch/arm/amlogic/meson_sdhc.c

507

__SHIFTIN(7, SD_PDMA_RXFIFO_THRESHOLD) |

sys/arch/arm/amlogic/meson_sdhc.c

511

__SHIFTIN(7, SD_MISC_TXSTART_THRESHOLD) |

sys/arch/arm/amlogic/meson_sdhc.c

512

__SHIFTIN(5, SD_MISC_WCRC_ERR_PATTERN) |

sys/arch/arm/amlogic/meson_sdhc.c

513

__SHIFTIN(2, SD_MISC_WCRC_OK_PATTERN));

sys/arch/arm/amlogic/meson_sdhc.c

517

enhc |= __SHIFTIN(63, SD_ENHC_RXFIFO_THRESHOLD);

sys/arch/arm/amlogic/meson_sdhc.c

521

enhc |= __SHIFTIN(12, SD_ENHC_SDIO_IRQ_PERIOD);

sys/arch/arm/amlogic/meson_sdhc.c

523

enhc |= __SHIFTIN(0xff, SD_ENHC_RX_TIMEOUT);

sys/arch/arm/amlogic/meson_sdhc.c

603

cntl |= __SHIFTIN(0, SD_CNTL_DAT_TYPE);

sys/arch/arm/amlogic/meson_sdhc.c

606

cntl |= __SHIFTIN(1, SD_CNTL_DAT_TYPE);

sys/arch/arm/amlogic/meson_sdhc.c

609

cntl |= __SHIFTIN(2, SD_CNTL_DAT_TYPE);

sys/arch/arm/amlogic/meson_sdhc.c

678

cntl |= __SHIFTIN(cmd->c_blklen & 0x1ff, SD_CNTL_PACK_LEN);

sys/arch/arm/amlogic/meson_sdhc.c

680

cmdval |= __SHIFTIN(nblks - 1, SD_SEND_TOTAL_PACK);

sys/arch/arm/amlogic/meson_sdhc.c

767

pdma |= __SHIFTIN(i, SD_PDMA_PIO_RDRESP);

sys/arch/arm/amlogic/meson_sdhc.c

783

pdma |= __SHIFTIN(0, SD_PDMA_PIO_RDRESP);

sys/arch/arm/amlogic/meson_sdhc.c

930

__SHIFTIN(ph, SD_CLK2_RX_CLK_PHASE), SD_CLK2_RX_CLK_PHASE);

sys/arch/arm/amlogic/meson_sdhc.c

982

__SHIFTIN(rx_phase, SD_CLK2_RX_CLK_PHASE), SD_CLK2_RX_CLK_PHASE);

sys/arch/arm/amlogic/meson_sdio.c

330

conf |= __SHIFTIN(clk_div - 1, SDIO_CONF_COMMAND_CLK_DIV);

sys/arch/arm/amlogic/meson_sdio.c

371

__SHIFTIN(2, SDIO_CONF_WRITE_CRC_OK_STATUS) |

sys/arch/arm/amlogic/meson_sdio.c

372

__SHIFTIN(2, SDIO_CONF_WRITE_NWR) |

sys/arch/arm/amlogic/meson_sdio.c

373

__SHIFTIN(3, SDIO_CONF_M_ENDIAN) |

sys/arch/arm/amlogic/meson_sdio.c

374

__SHIFTIN(39, SDIO_CONF_COMMAND_ARG_BITS) |

sys/arch/arm/amlogic/meson_sdio.c

375

__SHIFTIN(0x1f4, SDIO_CONF_COMMAND_CLK_DIV));

sys/arch/arm/amlogic/meson_sdio.c

378

__SHIFTIN(sc->sc_cur_port, SDIO_MULT_PORT_SEL));

sys/arch/arm/amlogic/meson_sdio.c

527

send |= __SHIFTIN(133, SDIO_SEND_RESPONSE_BITS);

sys/arch/arm/amlogic/meson_sdio.c

530

send |= __SHIFTIN(45, SDIO_SEND_RESPONSE_BITS);

sys/arch/arm/amlogic/meson_sdio.c

548

send |= __SHIFTIN(nblks - 1, SDIO_SEND_REPEAT_PACKAGE);

sys/arch/arm/amlogic/meson_sdio.c

549

ext |= __SHIFTIN(packlen, SDIO_EXT_DATA_RW_NUMBER);

sys/arch/arm/amlogic/meson_sdio.c

574

send |= __SHIFTIN(cmd->c_opcode | 0x40, SDIO_SEND_COMMAND_INDEX);

sys/arch/arm/amlogic/meson_sdio.c

576

mult |= __SHIFTIN(sc->sc_cur_port, SDIO_MULT_PORT_SEL);

sys/arch/arm/amlogic/meson_thermal.c

121

val |= __SHIFTIN(3, TS_CFG_REG1_ANA_CH_SEL);

sys/arch/arm/amlogic/meson_uart.c

240

misc |= __SHIFTIN(0, UART_MISC_TX_IRQ_CNT);

sys/arch/arm/amlogic/meson_uart.c

242

misc |= __SHIFTIN(1, UART_MISC_RX_IRQ_CNT);

sys/arch/arm/amlogic/meson_usbctrl.c

194

val |= __SHIFTIN(0x20, USB_R1_U3H_FLADJ_30MHZ_REG_MASK);

sys/arch/arm/amlogic/meson_usbctrl.c

207

val |= __SHIFTIN(0xff, USB_R5_ID_DIG_TH_MASK);

sys/arch/arm/amlogic/meson_usbctrl.c

219

val |= __SHIFTIN(2, USB_R3_P30_SSC_RANGE_MASK);

sys/arch/arm/amlogic/meson_usbctrl.c

227

val |= __SHIFTIN(0x15, USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK);

sys/arch/arm/amlogic/meson_usbctrl.c

232

val |= __SHIFTIN(0x20, USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK);

sys/arch/arm/amlogic/meson_usbctrl.c

243

val |= __SHIFTIN(127, USB_R1_P30_PCS_TX_SWING_FULL_MASK);

sys/arch/arm/amlogic/meson_usbphy.c

146

val |= __SHIFTIN(PREI_USB_PHY_CTRL_FSEL_24M,

sys/arch/arm/amlogic/meson_wdt.c

100

__SHIFTIN(tcnt, WATCHDOG_TC_TCNT));

sys/arch/arm/amlogic/mesong12_clkc.c

1375

val |= __SHIFTIN(new_m, __BITS(7,0));

sys/arch/arm/amlogic/mesong12_clkc.c

1377

val |= __SHIFTIN(new_n, __BITS(14,10));

sys/arch/arm/amlogic/mesong12_clkc.c

1379

val |= __SHIFTIN(new_div, __BITS(18,16));

sys/arch/arm/amlogic/mesong12_clkc.c

1424

cntl0 = __SHIFTIN(9, HHI_PCIE_PLL_CNTL0_PCIE_APLL_OD) |

sys/arch/arm/amlogic/mesong12_clkc.c

1425

__SHIFTIN(1, HHI_PCIE_PLL_CNTL0_PCIE_APLL_PREDIV_SEL) |

sys/arch/arm/amlogic/mesong12_clkc.c

1426

__SHIFTIN(150, HHI_PCIE_PLL_CNTL0_PCIE_APLL_FBKDIV);

sys/arch/arm/amlogic/mesong12_clkc.c

1427

cntl4 = __SHIFTIN(1, HHI_PCIE_PLL_CNTL4_PCIE_APLL_LPF_CAPADJ) |

sys/arch/arm/amlogic/mesong12_clkc.c

1430

cntl3 = __SHIFTIN(1, HHI_PCIE_PLL_CNTL3_PCIE_APLL_AFC_HOLD_T) |

sys/arch/arm/amlogic/mesong12_clkc.c

1431

__SHIFTIN(2, HHI_PCIE_PLL_CNTL3_PCIE_APLL_AFC_DIV) |

sys/arch/arm/amlogic/mesong12_clkc.c

1433

__SHIFTIN(8, HHI_PCIE_PLL_CNTL3_PCIE_APLL_CP_ICAP) |

sys/arch/arm/amlogic/mesong12_clkc.c

1434

__SHIFTIN(14, HHI_PCIE_PLL_CNTL3_PCIE_APLL_CP_IRES);

sys/arch/arm/amlogic/mesong12_clkc.c

1435

cntl5 = __SHIFTIN(6, HHI_PCIE_PLL_CNTL5_PCIE_HCSL_ADJ_LDO) |

sys/arch/arm/amlogic/mesong12_clkc.c

1449

__SHIFTIN(0x1100, HHI_PCIE_PLL_CNTL2_PCIE_APLL_RESERVE));

sys/arch/arm/amlogic/mesong12_clkc.c

1468

__SHIFTIN(0x1000, HHI_PCIE_PLL_CNTL2_PCIE_APLL_RESERVE));

sys/arch/arm/amlogic/mesong12_usb2phy.c

210

__SHIFTIN(1, USB2PHY_R16_USB2_MPLL_LOCK_LONG) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

212

__SHIFTIN(1, USB2PHY_R16_USB2_MPLL_N) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

213

__SHIFTIN(20, USB2PHY_R16_USB2_MPLL_M));

sys/arch/arm/amlogic/mesong12_usb2phy.c

215

__SHIFTIN(0, USB2PHY_R17_USB2_MPLL_FILTER_PVT1) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

216

__SHIFTIN(7, USB2PHY_R17_USB2_MPLL_FILTER_PVT2) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

217

__SHIFTIN(7, USB2PHY_R17_USB2_MPLL_LAMBDA0) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

218

__SHIFTIN(2, USB2PHY_R17_USB2_MPLL_LAMBDA1) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

219

__SHIFTIN(9, USB2PHY_R17_USB2_MPLL_FRAC_IN));

sys/arch/arm/amlogic/mesong12_usb2phy.c

222

__SHIFTIN(1, USB2PHY_R18_USB2_MPLL_ADJ_LDO) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

223

__SHIFTIN(3, USB2PHY_R18_USB2_MPLL_ALPHA) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

224

__SHIFTIN(0, USB2PHY_R18_USB2_MPLL_BB_MODE) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

225

__SHIFTIN(1, USB2PHY_R18_USB2_MPLL_BIAS_ADJ) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

226

__SHIFTIN(3, USB2PHY_R18_USB2_MPLL_DATA_SEL) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

227

__SHIFTIN(7, USB2PHY_R18_USB2_MPLL_ROU) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

228

__SHIFTIN(1, USB2PHY_R18_USB2_MPLL_PFD_GAIN) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

229

__SHIFTIN(39, USB2PHY_R18_USB2_MPLL_LK_S) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

230

__SHIFTIN(9, USB2PHY_R18_USB2_MPLL_LK_W) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

231

__SHIFTIN(1, USB2PHY_R18_USB2_MPLL_LKW_SEL));

sys/arch/arm/amlogic/mesong12_usb2phy.c

236

__SHIFTIN(1, USB2PHY_R16_USB2_MPLL_LOCK_LONG) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

238

__SHIFTIN(1, USB2PHY_R16_USB2_MPLL_N) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

239

__SHIFTIN(20, USB2PHY_R16_USB2_MPLL_M));

sys/arch/arm/amlogic/mesong12_usb2phy.c

243

__SHIFTIN(0, USB2PHY_R20_USB2_BGR_DBG_1_0) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

244

__SHIFTIN(0, USB2PHY_R20_USB2_BGR_VREF_4_0) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

245

__SHIFTIN(0, USB2PHY_R20_USB2_BGR_ADJ_4_0) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

246

__SHIFTIN(3, USB2PHY_R20_USB2_EDGE_DRV_TRIM_1_0) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

248

__SHIFTIN(15, USB2PHY_R20_USB2_DMON_SEL_3_0) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

250

__SHIFTIN(4, USB2PHY_R20_USB2_OTG_VBUS_TRIM_2_0));

sys/arch/arm/amlogic/mesong12_usb2phy.c

253

__SHIFTIN(0, USB2PHY_R04_I_C2L_BIAS_TRIM) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

255

__SHIFTIN(0xfff, USB2PHY_R04_CALIBRATION_CODE_VALUE));

sys/arch/arm/amlogic/mesong12_usb2phy.c

259

__SHIFTIN(3, USB2PHY_R03_DISC_THRESH) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

260

__SHIFTIN(1, USB2PHY_R03_HSDIC_REF) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

261

__SHIFTIN(0, USB2PHY_R03_SQUELCH_REF));

sys/arch/arm/amlogic/mesong12_usb2phy.c

265

__SHIFTIN(0, USB2PHY_R14_BYPASS_CTRL) |

sys/arch/arm/amlogic/mesong12_usb2phy.c

266

__SHIFTIN(0, USB2PHY_R14_I_RPU_SW2_EN));

sys/arch/arm/amlogic/mesong12_usb2phy.c

268

__SHIFTIN(7, USB2PHY_R13_MINIMUM_COUNT_FOR_SYNC_DETECTION) |

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

147

val = __SHIFTIN(addr, USB3PCIEPHY_R4_PHY_CR_DATA_IN);

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

188

val = __SHIFTIN(addr, USB3PCIEPHY_R4_PHY_CR_DATA_IN);

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

228

val |= __SHIFTIN(3, USB3PCIEPHY_R0_PCIE_USB3_SWITCH);

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

241

val |= __SHIFTIN(2, __BITS(11,4));

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

248

val |= __SHIFTIN(2, __BITS(7,6));

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

250

val |= __SHIFTIN(3, __BITS(10,8));

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

258

val |= __SHIFTIN(0x16, __BITS(13,7));

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

260

val |= __SHIFTIN(0x7f, __BITS(6,0));

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

267

val |= __SHIFTIN(8, __BITS(7,4));

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

273

val |= __SHIFTIN(4, USB3PCIEPHY_R2_PHY_TX_VBOOST_LVL);

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

278

val |= __SHIFTIN(4, USB3PCIEPHY_R1_PHY_LOS_BIAS);

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

280

val |= __SHIFTIN(9, USB3PCIEPHY_R1_PHY_LOS_LEVEL);

sys/arch/arm/amlogic/mesongx_mmc.c

516

val |= __SHIFTIN(0, CLOCK_CFG_RX_PHASE);

sys/arch/arm/amlogic/mesongx_mmc.c

518

val |= __SHIFTIN(0, CLOCK_CFG_TX_PHASE);

sys/arch/arm/amlogic/mesongx_mmc.c

520

val |= __SHIFTIN(2, CLOCK_CFG_CO_PHASE);

sys/arch/arm/amlogic/mesongx_mmc.c

522

val |= __SHIFTIN(best_sel, CLOCK_CFG_SRC);

sys/arch/arm/amlogic/mesongx_mmc.c

524

val |= __SHIFTIN(best_div, CLOCK_CFG_DIV);

sys/arch/arm/amlogic/mesongx_mmc.c

682

val |= __SHIFTIN(ilog2(16), CFG_RC_CC);

sys/arch/arm/amlogic/mesongx_mmc.c

766

val |= __SHIFTIN(CFG_BUS_WIDTH_1, CFG_BUS_WIDTH);

sys/arch/arm/amlogic/mesongx_mmc.c

769

val |= __SHIFTIN(CFG_BUS_WIDTH_4, CFG_BUS_WIDTH);

sys/arch/arm/amlogic/mesongx_mmc.c

772

val |= __SHIFTIN(CFG_BUS_WIDTH_8, CFG_BUS_WIDTH);

sys/arch/arm/amlogic/mesongx_mmc.c

894

flags |= __SHIFTIN(blen % 512, MESONGX_MMC_FLAGS_LENGTH);

sys/arch/arm/amlogic/mesongx_mmc.c

975

cmdflags |= __SHIFTIN(12, MESONGX_MMC_FLAGS_TIMEOUT); /* 2^12 = 4096 ms timeout */

sys/arch/arm/amlogic/mesongx_mmc.c

976

cmdflags |= __SHIFTIN(cmd->c_opcode, MESONGX_MMC_FLAGS_CMD_INDEX);

sys/arch/arm/amlogic/mesongx_mmc.c

997

val |= __SHIFTIN(ilog2(cmd->c_blklen), CFG_BL_LEN);

sys/arch/arm/amlogic/mesongx_wdt.c

102

__SHIFTIN(tcnt, CNTL_CLK_DIV_TCNT) |

sys/arch/arm/amlogic/mesongxl_usb3phy.c

107

val |= __SHIFTIN(0xff, REG5_ID_DIG_TH);

sys/arch/arm/amlogic/mesongxl_usb3phy.c

142

val |= __SHIFTIN(0x20, REG1_U3H_FLADJ_30MHZ_REG);

sys/arch/arm/apple/apple_dart.c

100

#define DART_L2_END(addr) __SHIFTIN(DART_L2_SUBPAGE(addr), DART_L2_END_MASK)

sys/arch/arm/apple/apple_dart.c

233

addr = __SHIFTIN(DART_READ(sc, DART_ERR_ADDRL), __BITS(31, 0));

sys/arch/arm/apple/apple_dart.c

234

addr |= __SHIFTIN(DART_READ(sc, DART_ERR_ADDRH), __BITS(63, 32));

sys/arch/arm/apple/apple_dart.c

99

#define DART_L2_START(addr) __SHIFTIN(DART_L2_SUBPAGE(addr), DART_L2_START_MASK)

sys/arch/arm/apple/apple_iic.c

236

__SHIFTIN(sc->sc_clkdiv, I2C_CTL_CLK_MASK) |

sys/arch/arm/apple/apple_pcie.c

482

ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK);

sys/arch/arm/apple/apple_pcie.c

608

__SHIFTIN(msino, ARM_PCI_INTR_IRQ) |

sys/arch/arm/apple/apple_pcie.c

609

__SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) |

sys/arch/arm/apple/apple_pcie.c

610

__SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME);

sys/arch/arm/apple/apple_pcie.c

668

__SHIFTIN(msino, ARM_PCI_INTR_IRQ) |

sys/arch/arm/apple/apple_pcie.c

669

__SHIFTIN(msix_vec, ARM_PCI_INTR_MSI_VEC) |

sys/arch/arm/apple/apple_pcie.c

670

__SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME);

sys/arch/arm/apple/apple_pcie.c

81

#define PCIE_PORT_MSI_CTRL_32 __SHIFTIN(5U, __BITS(7,4))

sys/arch/arm/apple/apple_pinctrl.c

224

reg |= __SHIFTIN(func, GPIO_PIN_FUNC_MASK);

sys/arch/arm/apple/apple_pinctrl.c

69

#define GPIO_PIN_MODE_INPUT __SHIFTIN(0, GPIO_PIN_MODE_MASK);

sys/arch/arm/apple/apple_pinctrl.c

70

#define GPIO_PIN_MODE_OUTPUT __SHIFTIN(1, GPIO_PIN_MODE_MASK);

sys/arch/arm/apple/apple_pinctrl.c

71

#define GPIO_PIN_MODE_IRQ_HI __SHIFTIN(2, GPIO_PIN_MODE_MASK);

sys/arch/arm/apple/apple_pinctrl.c

72

#define GPIO_PIN_MODE_IRQ_LO __SHIFTIN(3, GPIO_PIN_MODE_MASK);

sys/arch/arm/apple/apple_pinctrl.c

73

#define GPIO_PIN_MODE_IRQ_UP __SHIFTIN(4, GPIO_PIN_MODE_MASK);

sys/arch/arm/apple/apple_pinctrl.c

74

#define GPIO_PIN_MODE_IRQ_DN __SHIFTIN(5, GPIO_PIN_MODE_MASK);

sys/arch/arm/apple/apple_pinctrl.c

75

#define GPIO_PIN_MODE_IRQ_ANY __SHIFTIN(6, GPIO_PIN_MODE_MASK);

sys/arch/arm/apple/apple_pinctrl.c

76

#define GPIO_PIN_MODE_IRQ_OFF __SHIFTIN(7, GPIO_PIN_MODE_MASK);

sys/arch/arm/apple/apple_pmgr.c

88

val |= __SHIFTIN(pstate, PMGR_PS_TARGET_MASK);

sys/arch/arm/apple/apple_rtkit.c

106

msg.data0 = __SHIFTIN(type, RTKIT_MGMT_TYPE_MASK) | data;

sys/arch/arm/apple/apple_rtkit.c

117

reply = __SHIFTIN(endpoint, RTKIT_MGMT_STARTEP_EP_MASK);

sys/arch/arm/apple/apple_rtkit.c

147

__SHIFTIN(ver, RTKIT_MGMT_HELLO_MINVER_MASK) |

sys/arch/arm/apple/apple_rtkit.c

148

__SHIFTIN(ver, RTKIT_MGMT_HELLO_MAXVER_MASK));

sys/arch/arm/apple/apple_rtkit.c

161

reply = __SHIFTIN(base, RTKIT_MGMT_EPMAP_BASE_MASK);

sys/arch/arm/apple/apple_rtkit.c

213

__SHIFTIN(size, RTKIT_BUFFER_SIZE_MASK) | addr);

sys/arch/arm/apple/apple_rtkit.c

242

__SHIFTIN(size, RTKIT_BUFFER_SIZE_MASK) | addr);

sys/arch/arm/apple/apple_smc.c

159

__SHIFTIN(key, SMC_DATA) |

sys/arch/arm/apple/apple_smc.c

160

__SHIFTIN(cmd, SMC_CMD) |

sys/arch/arm/apple/apple_smc.c

161

__SHIFTIN(len, SMC_LENGTH) |

sys/arch/arm/apple/apple_smc.c

162

__SHIFTIN((sc->sc_msgid++ & 0xf), SMC_ID)

sys/arch/arm/apple/apple_smc.c

283

key |= __SHIFTIN(digits[__SHIFTOUT(pn, __BITS(3, 0))], __BITS(7, 0));

sys/arch/arm/apple/apple_smc.c

284

key |= __SHIFTIN(digits[__SHIFTOUT(pn, __BITS(7, 4))], __BITS(15, 8));

sys/arch/arm/arm/cpufunc.c

3015

__SHIFTIN(__SHIFTOUT(lcputype, CPU_ID_VARIANT_MASK), __BITS(7,4)) |

sys/arch/arm/arm/cpufunc.c

3016

__SHIFTIN(__SHIFTOUT(lcputype, CPU_ID_REVISION_MASK), __BITS(3,0)) |

sys/arch/arm/arm/psci.c

98

return __SHIFTIN(0, PSCI_VERSION_MAJOR) |

sys/arch/arm/arm/psci.c

99

__SHIFTIN(1, PSCI_VERSION_MINOR);

sys/arch/arm/arm/undefined.c

270

if (!arm_cond_ok_p(__SHIFTIN(insn, INSN_COND_MASK), frame->tf_spsr)) {

sys/arch/arm/arm32/arm32_kvminit.c

1073

KASSERT(armreg_ttbcr_read() == __SHIFTIN(1, TTBCR_S_N));

sys/arch/arm/arm32/arm32_machdep.c

786

KASSERT(armreg_ttbcr_read() == __SHIFTIN(1, TTBCR_S_N));

sys/arch/arm/arm32/arm32_tlb.c

157

__SHIFTIN(way, ARM_TLBDATAOP_WAY)

sys/arch/arm/arm32/arm32_tlb.c

158

| __SHIFTIN(va_index, ARM_A5_TLBDATAOP_INDEX));

sys/arch/arm/arm32/arm32_tlb.c

189

__SHIFTIN(way, ARM_TLBDATAOP_WAY)

sys/arch/arm/arm32/arm32_tlb.c

190

| __SHIFTIN(va_index, ARM_A7_TLBDATAOP_INDEX));

sys/arch/arm/arm32/db_machdep.c

424

__SHIFTIN(va_index, dti->dti_index)

sys/arch/arm/arm32/db_machdep.c

425

| __SHIFTIN(way, ARM_TLBDATAOP_WAY));

sys/arch/arm/arm32/db_machdep.c

445

__SHIFTIN(way, ARM_TLBDATAOP_WAY)

sys/arch/arm/arm32/db_machdep.c

446

| __SHIFTIN(va_index, dti->dti_index));

sys/arch/arm/broadcom/bcm2835_bsc.c

105

__SHIFTIN(divider, BSC_DIV_CDIV));

sys/arch/arm/broadcom/bcm2835_bscreg.h

40

#define BSC_C_CLEAR_NONE __SHIFTIN(0, BSC_C_CLEAR)

sys/arch/arm/broadcom/bcm2835_bscreg.h

41

#define BSC_C_CLEAR_CLEAR __SHIFTIN(3, BSC_C_CLEAR)

sys/arch/arm/broadcom/bcm2835_cm.c

175

ctl |= __SHIFTIN(CM_PASSWD, CM_CTL_PASSWD);

sys/arch/arm/broadcom/bcm2835_cm.c

177

div |= __SHIFTIN(CM_PASSWD, CM_DIV_PASSWD);

sys/arch/arm/broadcom/bcm2835_cm.c

186

r |= __SHIFTIN(CM_PASSWD, CM_CTL_PASSWD);

sys/arch/arm/broadcom/bcm2835_emmc.c

289

__SHIFTIN(11, DMAC_TI_PERMAP); /* e.MMC */

sys/arch/arm/broadcom/bcm2835_gpio.c

856

reg |= __SHIFTIN(pud, mask);

sys/arch/arm/broadcom/bcm2835_pwm.c

239

ctl = (w & ~pwm->ctlmask) | __SHIFTIN(ctl, pwm->ctlmask);

sys/arch/arm/broadcom/bcm2835_pwm.c

266

w = __SHIFTIN(__SHIFTOUT(w, pwm->stamask), PWM_STA_STA)

sys/arch/arm/broadcom/bcm2835_pwm.c

267

| __SHIFTIN(__SHIFTOUT(w, pwm->gapomask), PWM_STA_GAPO)

sys/arch/arm/broadcom/bcm2835_pwm.c

346

| __SHIFTIN(7, PWM_DMAC_PANIC)

sys/arch/arm/broadcom/bcm2835_pwm.c

347

| __SHIFTIN(7, PWM_DMAC_DREQ);

sys/arch/arm/broadcom/bcm2835_sdhost.c

356

__SHIFTIN(13, DMAC_TI_PERMAP); /* SD HOST */

sys/arch/arm/broadcom/bcm2835_sdhost.c

504

edm |= __SHIFTIN(4, SDEDM_RD_FIFO);

sys/arch/arm/broadcom/bcm2835_sdhost.c

505

edm |= __SHIFTIN(4, SDEDM_WR_FIFO);

sys/arch/arm/broadcom/bcm2835_spi.c

183

clk = __SHIFTIN(clk, SPI_CLK_CDIV);

sys/arch/arm/broadcom/bcm2835_spi.c

222

cs |= __SHIFTIN(st->st_slave, SPI_CS_CS);

sys/arch/arm/broadcom/bcm2838_pcie.c

411

__SHIFTIN(base, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE)

sys/arch/arm/broadcom/bcm2838_pcie.c

412

| __SHIFTIN(limit, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT));

sys/arch/arm/broadcom/bcm2838_pcie.c

419

__SHIFTIN(base, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE));

sys/arch/arm/broadcom/bcm2838_pcie.c

423

__SHIFTIN(base, PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT));

sys/arch/arm/broadcom/bcm2838_pcie.c

477

w = (__SHIFTIN(ad, PCIE_MISC_RC_BARx_CONFIG_LO_MATCH_ADDRESS)

sys/arch/arm/broadcom/bcm2838_pcie.c

479

| __SHIFTIN(sz, PCIE_MISC_RC_BARx_CONFIG_LO_SIZE);

sys/arch/arm/broadcom/bcm2838_pcie.c

485

__SHIFTIN(sz, PCIE_MISC_MISC_CTRL_SCB0_SIZE));

sys/arch/arm/broadcom/bcm2838_pcie.c

529

__SHIFTIN(0x3, PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT));

sys/arch/arm/broadcom/bcm2838_pcie.c

534

__SHIFTIN(0x60400, PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE));

sys/arch/arm/broadcom/bcm2838_pcie.c

606

idx = __SHIFTIN(bus, PCIE_EXT_CFG_INDEX_BUSNUM)

sys/arch/arm/broadcom/bcm2838_pcie.c

607

| __SHIFTIN(dev, PCIE_EXT_CFG_INDEX_SLOT)

sys/arch/arm/broadcom/bcm2838_pcie.c

608

| __SHIFTIN(fn, PCIE_EXT_CFG_INDEX_FUNC);

sys/arch/arm/broadcom/bcm2838_pcie.c

635

idx = __SHIFTIN(bus, PCIE_EXT_CFG_INDEX_BUSNUM)

sys/arch/arm/broadcom/bcm2838_pcie.c

636

| __SHIFTIN(dev, PCIE_EXT_CFG_INDEX_SLOT)

sys/arch/arm/broadcom/bcm2838_pcie.c

637

| __SHIFTIN(fn, PCIE_EXT_CFG_INDEX_FUNC);

sys/arch/arm/broadcom/bcm2838_pcie.c

661

idx = __SHIFTIN(bus, PCIE_EXT_CFG_INDEX_BUSNUM)

sys/arch/arm/broadcom/bcm2838_pcie.c

662

| __SHIFTIN(dev, PCIE_EXT_CFG_INDEX_SLOT)

sys/arch/arm/broadcom/bcm2838_pcie.c

663

| __SHIFTIN(fn, PCIE_EXT_CFG_INDEX_FUNC);

sys/arch/arm/broadcom/bcm53xx_board.c

289

usb2_control |= __SHIFTIN(new_ndiv, USB2_CONTROL_NDIV_INT);

sys/arch/arm/broadcom/bcm53xx_board.c

626

__SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN);

sys/arch/arm/broadcom/bcm53xx_board.c

645

__SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN);

sys/arch/arm/broadcom/bcm53xx_board.c

666

__SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN);

sys/arch/arm/broadcom/bcm53xx_board.c

684

__SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN);

sys/arch/arm/broadcom/bcm53xx_eth.c

507

| __SHIFTIN(ETH_SPEED_1000, ETH_SPEED)

sys/arch/arm/broadcom/bcm53xx_eth.c

541

__SHIFTIN(sc->sc_rcvoffset, RCVCTL_RCVOFFSET)

sys/arch/arm/broadcom/bcm53xx_eth.c

544

| __SHIFTIN(3, RCVCTL_BURSTLEN));

sys/arch/arm/broadcom/bcm53xx_eth.c

551

| __SHIFTIN(3, XMTCTL_BURSTLEN));

sys/arch/arm/broadcom/bcm53xx_eth.c

569

sc->sc_rcvlazy = __SHIFTIN(4, INTRCVLAZY_FRAMECOUNT)

sys/arch/arm/broadcom/bcm53xx_eth.c

570

| __SHIFTIN(cpu->cpu_clk.clk_apb / 1000, INTRCVLAZY_TIMEOUT);

sys/arch/arm/broadcom/bcm53xx_idm.c

87

v |= __SHIFTIN(AXCACHE_WA, IO_CONTROL_DIRECT_ARCACHE);

sys/arch/arm/broadcom/bcm53xx_idm.c

88

v |= __SHIFTIN(AXCACHE_RA, IO_CONTROL_DIRECT_AWCACHE);

sys/arch/arm/broadcom/bcm53xx_idm.c

90

v |= __SHIFTIN(AXCACHE_C|AXCACHE_B, IO_CONTROL_DIRECT_ARCACHE);

sys/arch/arm/broadcom/bcm53xx_idm.c

91

v |= __SHIFTIN(AXCACHE_C|AXCACHE_B, IO_CONTROL_DIRECT_AWCACHE);

sys/arch/arm/broadcom/bcm53xx_idm.c

96

v |= __SHIFTIN(0x1F, IO_CONTROL_DIRECT_ARUSER);

sys/arch/arm/broadcom/bcm53xx_idm.c

97

v |= __SHIFTIN(0x1F, IO_CONTROL_DIRECT_AWUSER);

sys/arch/arm/broadcom/bcm53xx_mdio.c

99

miimgt |= __SHIFTIN(div, MIIMGT_MDCDIV);

sys/arch/arm/broadcom/bcm53xx_pax.c

403

return __SHIFTIN(bus, CFG_ADDR_BUS)

sys/arch/arm/broadcom/bcm53xx_pax.c

404

| __SHIFTIN(dev, CFG_ADDR_DEV)

sys/arch/arm/broadcom/bcm53xx_pax.c

405

| __SHIFTIN(func, CFG_ADDR_FUNC)

sys/arch/arm/broadcom/bcm53xx_pax.c

416

__SHIFTIN(func, CFG_IND_ADDR_FUNC)

sys/arch/arm/broadcom/bcm53xx_pax.c

417

| __SHIFTIN(reg, CFG_IND_ADDR_REG));

sys/arch/arm/broadcom/bcm53xx_reg.h

280

#define MIICMD_SB_DEF __SHIFTIN(1, MIICMD_SB)

sys/arch/arm/broadcom/bcm53xx_reg.h

282

#define MIICMD_OP_RD __SHIFTIN(2, MIICMD_OP)

sys/arch/arm/broadcom/bcm53xx_reg.h

283

#define MIICMD_OP_WR __SHIFTIN(1, MIICMD_OP)

sys/arch/arm/broadcom/bcm53xx_reg.h

287

#define MIICMD_TA_DEF __SHIFTIN(2, MIICMD_TA)

sys/arch/arm/broadcom/bcm53xx_reg.h

292

#define MIICMD__PHYREG(p,r) (__SHIFTIN(p,MIICMD_PHY)|__SHIFTIN(r,MIICMD_REG))

sys/arch/arm/broadcom/bcm53xx_reg.h

469

#define CFG_ADDR_TYPE0 __SHIFTIN(0, CFG_ADDR_TYPE)

sys/arch/arm/broadcom/bcm53xx_reg.h

470

#define CFG_ADDR_TYPE1 __SHIFTIN(1, CFG_ADDR_TYPE)

sys/arch/arm/cortex/a9ptmr.c

164

sc->sc_ctl |= __SHIFTIN(sc->sc_prescaler - 1, TMR_CTL_PRESCALER);

sys/arch/arm/cortex/a9wdt.c

151

| __SHIFTIN(sc->sc_wdog_prescaler - 1, TMR_CTL_PRESCALER);

sys/arch/arm/cortex/a9wdt.c

173

| __SHIFTIN(sc->sc_wdog_prescaler - 1, TMR_CTL_PRESCALER);

sys/arch/arm/cortex/gic.c

305

| __SHIFTIN(level, GICD_SGIR_SGIINTID);

sys/arch/arm/cortex/gic.c

576

uint32_t sgir = __SHIFTIN(ARMGIC_SGI_IPIBASE + ipi, GICD_SGIR_SGIINTID);

sys/arch/arm/cortex/gic.c

583

sgir |= __SHIFTIN(targets_val, GICD_SGIR_TargetList);

sys/arch/arm/cortex/gic_reg.h

185

#define GICD_SGIR_TargetListFilter_List __SHIFTIN(0, GICD_SGIR_TargetListFilter)

sys/arch/arm/cortex/gic_reg.h

186

#define GICD_SGIR_TargetListFilter_NotMe __SHIFTIN(1, GICD_SGIR_TargetListFilter)

sys/arch/arm/cortex/gic_reg.h

187

#define GICD_SGIR_TargetListFilter_Me __SHIFTIN(2, GICD_SGIR_TargetListFilter)

sys/arch/arm/cortex/gic_v2m.c

139

ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK);

sys/arch/arm/cortex/gic_v2m.c

257

__SHIFTIN(spi, ARM_PCI_INTR_IRQ) |

sys/arch/arm/cortex/gic_v2m.c

258

__SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) |

sys/arch/arm/cortex/gic_v2m.c

259

__SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME);

sys/arch/arm/cortex/gic_v2m.c

318

__SHIFTIN(spi, ARM_PCI_INTR_IRQ) |

sys/arch/arm/cortex/gic_v2m.c

319

__SHIFTIN(msix_vec, ARM_PCI_INTR_MSI_VEC) |

sys/arch/arm/cortex/gic_v2m.c

320

__SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME);

sys/arch/arm/cortex/gicv3.c

349

return __SHIFTIN(aff0, GICR_TYPER_Affinity_Value_Aff0) |

sys/arch/arm/cortex/gicv3.c

350

__SHIFTIN(aff1, GICR_TYPER_Affinity_Value_Aff1) |

sys/arch/arm/cortex/gicv3.c

351

__SHIFTIN(aff2, GICR_TYPER_Affinity_Value_Aff2) |

sys/arch/arm/cortex/gicv3.c

352

__SHIFTIN(aff3, GICR_TYPER_Affinity_Value_Aff3);

sys/arch/arm/cortex/gicv3.c

388

return __SHIFTIN(__BIT(aff0), ICC_SGIR_EL1_TargetList) |

sys/arch/arm/cortex/gicv3.c

389

__SHIFTIN(aff1, ICC_SGIR_EL1_Aff1) |

sys/arch/arm/cortex/gicv3.c

390

__SHIFTIN(aff2, ICC_SGIR_EL1_Aff2) |

sys/arch/arm/cortex/gicv3.c

391

__SHIFTIN(aff3, ICC_SGIR_EL1_Aff3);

sys/arch/arm/cortex/gicv3.c

446

sgir = __SHIFTIN(ipi, ICC_SGIR_EL1_INTID);

sys/arch/arm/cortex/gicv3.c

603

__SHIFTIN(ffs(pic->pic_maxsources) - 1, GICR_PROPBASER_IDbits) |

sys/arch/arm/cortex/gicv3.c

604

__SHIFTIN(GICR_Shareability_IS, GICR_PROPBASER_Shareability) |

sys/arch/arm/cortex/gicv3.c

605

__SHIFTIN(GICR_Cache_NORMAL_RA_WA_WB, GICR_PROPBASER_InnerCache);

sys/arch/arm/cortex/gicv3.c

611

propbase |= __SHIFTIN(GICR_Shareability_NS, GICR_PROPBASER_Shareability);

sys/arch/arm/cortex/gicv3.c

613

propbase |= __SHIFTIN(GICR_Cache_NORMAL_NC, GICR_PROPBASER_InnerCache);

sys/arch/arm/cortex/gicv3.c

621

__SHIFTIN(GICR_Shareability_IS, GICR_PENDBASER_Shareability) |

sys/arch/arm/cortex/gicv3.c

622

__SHIFTIN(GICR_Cache_NORMAL_RA_WA_WB, GICR_PENDBASER_InnerCache);

sys/arch/arm/cortex/gicv3.c

627

pendbase |= __SHIFTIN(GICR_Shareability_NS, GICR_PENDBASER_Shareability);

sys/arch/arm/cortex/gicv3.c

629

pendbase |= __SHIFTIN(GICR_Cache_NORMAL_NC, GICR_PENDBASER_InnerCache);

sys/arch/arm/cortex/gicv3_its.c

1020

baser |= __SHIFTIN(howmany(table_size, page_size) - 1, GITS_BASER_Size);

sys/arch/arm/cortex/gicv3_its.c

1024

baser |= __SHIFTIN(innercache, GITS_BASER_InnerCache);

sys/arch/arm/cortex/gicv3_its.c

1026

baser |= __SHIFTIN(share, GITS_BASER_Shareability);

sys/arch/arm/cortex/gicv3_its.c

1039

baser |= __SHIFTIN(GITS_Cache_NORMAL_NC, GITS_BASER_InnerCache);

sys/arch/arm/cortex/gicv3_its.c

559

ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK);

sys/arch/arm/cortex/gicv3_its.c

678

__SHIFTIN(lpi, ARM_PCI_INTR_IRQ) |

sys/arch/arm/cortex/gicv3_its.c

679

__SHIFTIN(eventid + n, ARM_PCI_INTR_MSI_VEC) |

sys/arch/arm/cortex/gicv3_its.c

680

__SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME);

sys/arch/arm/cortex/gicv3_its.c

76

(__SHIFTIN(GITS_IIDR_IMP_CAVIUM, GITS_IIDR_Implementor) | \

sys/arch/arm/cortex/gicv3_its.c

764

__SHIFTIN(lpi, ARM_PCI_INTR_IRQ) |

sys/arch/arm/cortex/gicv3_its.c

765

__SHIFTIN(eventid + n, ARM_PCI_INTR_MSI_VEC) |

sys/arch/arm/cortex/gicv3_its.c

766

__SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME);

sys/arch/arm/cortex/gicv3_its.c

77

__SHIFTIN(GITS_IIDR_PID_CAVIUM_THUNDERX, GITS_IIDR_ProductID) | \

sys/arch/arm/cortex/gicv3_its.c

78

__SHIFTIN(0, GITS_IIDR_Variant))

sys/arch/arm/cortex/gicv3_its.c

862

cbaser |= __SHIFTIN((its->its_cmd.len / 4096) - 1, GITS_CBASER_Size);

sys/arch/arm/cortex/gicv3_its.c

865

cbaser |= __SHIFTIN(GITS_Cache_NORMAL_WA_WB, GITS_CBASER_InnerCache);

sys/arch/arm/cortex/gicv3_its.c

866

cbaser |= __SHIFTIN(GITS_Shareability_IS, GITS_CBASER_Shareability);

sys/arch/arm/cortex/gicv3_its.c

873

cbaser |= __SHIFTIN(GITS_Cache_NORMAL_NC, GITS_CBASER_InnerCache);

sys/arch/arm/cortex/gicv3_its.c

875

cbaser |= __SHIFTIN(GITS_Shareability_NS, GITS_CBASER_Shareability);

sys/arch/arm/fdt/pcihost_fdt.c

498

__SHIFTIN(pa->pa_bus, PHYS_HI_BUS) |

sys/arch/arm/fdt/pcihost_fdt.c

499

__SHIFTIN(pa->pa_device, PHYS_HI_DEVICE) |

sys/arch/arm/fdt/pcihost_fdt.c

500

__SHIFTIN(pa->pa_function, PHYS_HI_FUNCTION)

sys/arch/arm/fdt/plfb_fdt.c

303

__SHIFTIN(timing.hback_porch - 1, LCDTIMING0_HBP) |

sys/arch/arm/fdt/plfb_fdt.c

304

__SHIFTIN(timing.hfront_porch - 1, LCDTIMING0_HFP) |

sys/arch/arm/fdt/plfb_fdt.c

305

__SHIFTIN(timing.hsync_len - 1, LCDTIMING0_HSW) |

sys/arch/arm/fdt/plfb_fdt.c

306

__SHIFTIN((timing.hactive / 16) - 1, LCDTIMING0_PPL));

sys/arch/arm/fdt/plfb_fdt.c

308

__SHIFTIN(timing.vback_porch - 1, LCDTIMING1_VBP) |

sys/arch/arm/fdt/plfb_fdt.c

309

__SHIFTIN(timing.vfront_porch - 1, LCDTIMING1_VFP) |

sys/arch/arm/fdt/plfb_fdt.c

310

__SHIFTIN(timing.vsync_len - 1, LCDTIMING1_VSW) |

sys/arch/arm/fdt/plfb_fdt.c

311

__SHIFTIN(timing.vactive - 1, LCDTIMING1_LPP));

sys/arch/arm/fdt/plfb_fdt.c

69

#define LCDCONTROL_BPP_24 __SHIFTIN(5, LCDCONTROL_BPP)

sys/arch/arm/fdt/pmu_fdt.c

208

__SHIFTIN(ci->ci_core_id, MPIDR_AFF0) |

sys/arch/arm/fdt/pmu_fdt.c

209

__SHIFTIN(ci->ci_package_id, MPIDR_AFF1);

sys/arch/arm/imx/if_enet.c

1788

ENET_REG_WRITE(sc, ENET_MSCR, __SHIFTIN(val, ENET_MSCR_MII_SPEED));

sys/arch/arm/imx/if_enetreg.h

108

# define ENET_RCR_MAX_FL(n) __SHIFTIN(n, __BITS(29, 16))

sys/arch/arm/imx/if_enetreg.h

143

# define ENET_TFWR_FIFO(n) __SHIFTIN(((n) / 64), __BITS(5, 0))

sys/arch/arm/imx/if_enetreg.h

92

# define ENET_MMFR_PHY_ADDR(phy) __SHIFTIN(phy, __BITS(27, 23))

sys/arch/arm/imx/if_enetreg.h

93

# define ENET_MMFR_PHY_REG(reg) __SHIFTIN(reg, __BITS(22, 18))

sys/arch/arm/imx/imx23_apbdma.c

250

chan->chan_cmds[0].control = __SHIFTIN(0, APBDMA_CMD_XFER_COUNT) |

sys/arch/arm/imx/imx23_apbdma.c

251

__SHIFTIN(req->dreq_datalen, APBDMA_CMD_CMDPIOWORDS) |

sys/arch/arm/imx/imx23_apbdma.c

252

__SHIFTIN(APBDMA_CMD_NO_DMA_XFER, APBDMA_CMD_COMMAND) |

sys/arch/arm/imx/imx23_apbdma.c

287

dma_dir = __SHIFTIN(APBDMA_CMD_DMA_READ, APBDMA_CMD_COMMAND);

sys/arch/arm/imx/imx23_apbdma.c

289

dma_dir = __SHIFTIN(APBDMA_CMD_DMA_WRITE, APBDMA_CMD_COMMAND);

sys/arch/arm/imx/imx23_apbdma.c

296

__SHIFTIN(req->dreq_segs[i].ds_len, APBDMA_CMD_XFER_COUNT) |

sys/arch/arm/imx/imx23_apbdma.c

297

__SHIFTIN(0, APBDMA_CMD_CMDPIOWORDS) | dma_dir |

sys/arch/arm/imx/imx23_apbdma.c

308

__SHIFTIN(req->dreq_datalen, APBDMA_CMD_CMDPIOWORDS);

sys/arch/arm/imx/imx23_apbdma.c

356

val = __SHIFTIN(1, HW_APBH_CH0_SEMA_INCREMENT_SEMA);

sys/arch/arm/imx/imx23_apbdma.c

359

val = __SHIFTIN(1, HW_APBX_CH0_SEMA_INCREMENT_SEMA);

sys/arch/arm/imx/imx23_apbdma.c

414

__SHIFTIN((1 << chan->chan_index),

sys/arch/arm/imx/imx23_apbdma.c

420

__SHIFTIN((1 << chan->chan_index),

sys/arch/arm/imx/imx23_digfilt.c

402

val |= __SHIFTIN(nvol, HW_AUDIOOUT_DACVOLUME_VOLUME_LEFT);

sys/arch/arm/imx/imx23_digfilt.c

408

val |= __SHIFTIN(nvol, HW_AUDIOOUT_DACVOLUME_VOLUME_RIGHT);

sys/arch/arm/imx/imx23_digfilt.c

425

val |= __SHIFTIN(nvol, HW_AUDIOOUT_HPVOL_VOL_LEFT);

sys/arch/arm/imx/imx23_digfilt.c

432

val |= __SHIFTIN(nvol, HW_AUDIOOUT_HPVOL_VOL_RIGHT);

sys/arch/arm/imx/imx23_digfilt.c

844

val |= (__SHIFTIN(0x1 ,HW_AUDIOOUT_DACSRR_BASEMULT) |

sys/arch/arm/imx/imx23_digfilt.c

845

__SHIFTIN(0x3, HW_AUDIOOUT_DACSRR_SRC_HOLD) |

sys/arch/arm/imx/imx23_digfilt.c

846

__SHIFTIN(0x17, HW_AUDIOOUT_DACSRR_SRC_INT) |

sys/arch/arm/imx/imx23_digfilt.c

847

__SHIFTIN(0x0E00, HW_AUDIOOUT_DACSRR_SRC_FRAC));

sys/arch/arm/imx/imx23_digfilt.c

850

val |= (__SHIFTIN(0x1 ,HW_AUDIOOUT_DACSRR_BASEMULT) |

sys/arch/arm/imx/imx23_digfilt.c

851

__SHIFTIN(0x3, HW_AUDIOOUT_DACSRR_SRC_HOLD) |

sys/arch/arm/imx/imx23_digfilt.c

852

__SHIFTIN(0x11, HW_AUDIOOUT_DACSRR_SRC_INT) |

sys/arch/arm/imx/imx23_digfilt.c

853

__SHIFTIN(0x0037, HW_AUDIOOUT_DACSRR_SRC_FRAC));

sys/arch/arm/imx/imx23_digfilt.c

856

val |= (__SHIFTIN(0x1 ,HW_AUDIOOUT_DACSRR_BASEMULT) |

sys/arch/arm/imx/imx23_digfilt.c

857

__SHIFTIN(0x3, HW_AUDIOOUT_DACSRR_SRC_HOLD) |

sys/arch/arm/imx/imx23_digfilt.c

858

__SHIFTIN(0x0F, HW_AUDIOOUT_DACSRR_SRC_INT) |

sys/arch/arm/imx/imx23_digfilt.c

859

__SHIFTIN(0x13FF, HW_AUDIOOUT_DACSRR_SRC_FRAC));

sys/arch/arm/imx/imx23_digfilt.c

862

val |= (__SHIFTIN(0x1 ,HW_AUDIOOUT_DACSRR_BASEMULT) |

sys/arch/arm/imx/imx23_digfilt.c

863

__SHIFTIN(0x1, HW_AUDIOOUT_DACSRR_SRC_HOLD) |

sys/arch/arm/imx/imx23_digfilt.c

864

__SHIFTIN(0x17, HW_AUDIOOUT_DACSRR_SRC_INT) |

sys/arch/arm/imx/imx23_digfilt.c

865

__SHIFTIN(0x0E00, HW_AUDIOOUT_DACSRR_SRC_FRAC));

sys/arch/arm/imx/imx23_digfilt.c

868

val |= (__SHIFTIN(0x1 ,HW_AUDIOOUT_DACSRR_BASEMULT) |

sys/arch/arm/imx/imx23_digfilt.c

869

__SHIFTIN(0x1, HW_AUDIOOUT_DACSRR_SRC_HOLD) |

sys/arch/arm/imx/imx23_digfilt.c

870

__SHIFTIN(0x11, HW_AUDIOOUT_DACSRR_SRC_INT) |

sys/arch/arm/imx/imx23_digfilt.c

871

__SHIFTIN(0x0037, HW_AUDIOOUT_DACSRR_SRC_FRAC));

sys/arch/arm/imx/imx23_digfilt.c

874

val |= (__SHIFTIN(0x1 ,HW_AUDIOOUT_DACSRR_BASEMULT) |

sys/arch/arm/imx/imx23_digfilt.c

875

__SHIFTIN(0x1, HW_AUDIOOUT_DACSRR_SRC_HOLD) |

sys/arch/arm/imx/imx23_digfilt.c

876

__SHIFTIN(0x0F, HW_AUDIOOUT_DACSRR_SRC_INT) |

sys/arch/arm/imx/imx23_digfilt.c

877

__SHIFTIN(0x13FF, HW_AUDIOOUT_DACSRR_SRC_FRAC));

sys/arch/arm/imx/imx23_digfilt.c

880

val |= (__SHIFTIN(0x1 ,HW_AUDIOOUT_DACSRR_BASEMULT) |

sys/arch/arm/imx/imx23_digfilt.c

881

__SHIFTIN(0x0, HW_AUDIOOUT_DACSRR_SRC_HOLD) |

sys/arch/arm/imx/imx23_digfilt.c

882

__SHIFTIN(0x17, HW_AUDIOOUT_DACSRR_SRC_INT) |

sys/arch/arm/imx/imx23_digfilt.c

883

__SHIFTIN(0x0E00, HW_AUDIOOUT_DACSRR_SRC_FRAC));

sys/arch/arm/imx/imx23_digfilt.c

888

val |= (__SHIFTIN(0x1 ,HW_AUDIOOUT_DACSRR_BASEMULT) |

sys/arch/arm/imx/imx23_digfilt.c

889

__SHIFTIN(0x0, HW_AUDIOOUT_DACSRR_SRC_HOLD) |

sys/arch/arm/imx/imx23_digfilt.c

890

__SHIFTIN(0x11, HW_AUDIOOUT_DACSRR_SRC_INT) |

sys/arch/arm/imx/imx23_digfilt.c

891

__SHIFTIN(0x0037, HW_AUDIOOUT_DACSRR_SRC_FRAC));

sys/arch/arm/imx/imx23_icoll.c

174

__SHIFTIN(0x3fffffff, HW_ICOLL_VECTOR_IRQVECTOR));

sys/arch/arm/imx/imx23_mmc.c

515

reg |= __SHIFTIN(BUS_WIDTH_1_BIT, HW_SSP_CTRL0_BUS_WIDTH) |

sys/arch/arm/imx/imx23_mmc.c

523

reg |= __SHIFTIN(DATA_TIMEOUT, HW_SSP_TIMING_TIMEOUT);

sys/arch/arm/imx/imx23_mmc.c

542

reg |= __SHIFTIN(0x7, HW_SSP_CTRL1_WORD_LENGTH) |

sys/arch/arm/imx/imx23_mmc.c

543

__SHIFTIN(0x3, HW_SSP_CTRL1_SSP_MODE);

sys/arch/arm/imx/imx23_mmc.c

583

reg |= __SHIFTIN(div, HW_SSP_TIMING_CLOCK_DIVIDE) |

sys/arch/arm/imx/imx23_mmc.c

584

__SHIFTIN(rate, HW_SSP_TIMING_CLOCK_RATE);

sys/arch/arm/imx/imx23_mmc.c

653

__SHIFTIN(sc->sc_bus_width, HW_SSP_CTRL0_BUS_WIDTH) |

sys/arch/arm/imx/imx23_mmc.c

655

__SHIFTIN(cmd->c_datalen, HW_SSP_CTRL0_XFER_COUNT) |

sys/arch/arm/imx/imx23_mmc.c

676

__SHIFTIN(ffs(cmd->c_blklen) - 1, HW_SSP_CMD0_BLOCK_SIZE) |

sys/arch/arm/imx/imx23_mmc.c

677

__SHIFTIN(block_count - 1, HW_SSP_CMD0_BLOCK_COUNT) |

sys/arch/arm/imx/imx23_mmc.c

678

__SHIFTIN(cmd->c_opcode, HW_SSP_CMD0_CMD);

sys/arch/arm/imx/imx23_mmc.c

701

__SHIFTIN(sc->sc_bus_width, HW_SSP_CTRL0_BUS_WIDTH) |

sys/arch/arm/imx/imx23_mmc.c

715

__SHIFTIN(cmd->c_opcode, HW_SSP_CMD0_CMD);

sys/arch/arm/imx/imx23_pinctrl.c

586

tmpr |= __SHIFTIN(MUXEL_GPIO_MODE, PIN2MUXSEL_MASK(pin));

sys/arch/arm/imx/imx23_pinctrl.c

592

tmpr |= __SHIFTIN(DRIVE_STRENGTH_4MA, PIN2DRIVE_MASK(pin));

sys/arch/arm/imx/imx23_timrot.c

177

__SHIFTIN(SOURCE_32KHZ_HZ / hz - 1,

sys/arch/arm/imx/imx23_timrot.c

183

__SHIFTIN(SOURCE_32KHZ_HZ / stathz - 1,

sys/arch/arm/imx/imx23_timrot.c

197

__SHIFTIN(SOURCE_32KHZ_HZ / newhz - 1,

sys/arch/arm/imx/imx51_ccm.c

603

reg |= __SHIFTIN(5, EPDC_ASM_SLOW_DIV);

sys/arch/arm/imx/imx51_ccm.c

632

reg |= __SHIFTIN(clk_base, CLKSEQ_EPDC_AXI_CLK);

sys/arch/arm/imx/imx51_ccm.c

651

reg |= __SHIFTIN(div, EPDC_AXI_DIV);

sys/arch/arm/imx/imx51_ccm.c

659

reg |= __SHIFTIN(clk_base, CLKSEQ_EPDC_PIX_CLK);

sys/arch/arm/imx/imx51_ccm.c

681

reg |= __SHIFTIN(div, EPDC_PIX_CLK_PRED);

sys/arch/arm/imx/imx51_ccmreg.h

154

#define EPDC_PIX_CLKGATE_OFF __SHIFTIN(0, EPDC_AXI_CLKGATE)

sys/arch/arm/imx/imx51_ccmreg.h

155

#define EPDC_PIX_CLKGATE_RUNMODE __SHIFTIN(1, EPDC_AXI_CLKGATE)

sys/arch/arm/imx/imx51_ccmreg.h

156

#define EPDC_PIX_CLKGATE_ALWAYS __SHIFTIN(2, EPDC_AXI_CLKGATE)

sys/arch/arm/imx/imx51_ccmreg.h

157

#define EPDC_PIX_CLKGATE_EXCEPTSTOP __SHIFTIN(3, EPDC_AXI_CLKGATE)

sys/arch/arm/imx/imx51_ccmreg.h

162

#define EPDC_AXI_CLKGATE_OFF __SHIFTIN(0, EPDC_AXI_CLKGATE)

sys/arch/arm/imx/imx51_ccmreg.h

163

#define EPDC_AXI_CLKGATE_RUNMODE __SHIFTIN(1, EPDC_AXI_CLKGATE)

sys/arch/arm/imx/imx51_ccmreg.h

164

#define EPDC_AXI_CLKGATE_ALWAYS __SHIFTIN(2, EPDC_AXI_CLKGATE)

sys/arch/arm/imx/imx51_ccmreg.h

165

#define EPDC_AXI_CLKGATE_EXCEPTSTOP __SHIFTIN(3, EPDC_AXI_CLKGATE)

sys/arch/arm/imx/imx51_dpllreg.h

39

#define DP_CTL_REF_CLK_SEL_COSC __SHIFTIN(0x2, DP_CTL_REF_CLK_SEL)

sys/arch/arm/imx/imx51_dpllreg.h

40

#define DP_CTL_REF_CLK_SEL_FPM __SHIFTIN(0x3, DP_CTL_REF_CLK_SEL)

sys/arch/arm/imx/imx51_ipuv3.c

343

reg |= __SHIFTIN(repeat, DI_STP_REP(no));

sys/arch/arm/imx/imx51_ipuv3.c

386

__SHIFTIN(div / 16, DI_BS_CLKGEN1_DOWN));

sys/arch/arm/imx/imx51_ipuv3.c

394

reg = __SHIFTIN(div / 16 - 1, DI_DW_GEN_ACCESS_SIZE) |

sys/arch/arm/imx/imx51_ipuv3.c

395

__SHIFTIN(div / 16 - 1, DI_DW_GEN_COMPONNENT_SIZE) |

sys/arch/arm/imx/imx51_ipuv3.c

396

__SHIFTIN(3, DI_DW_GEN_PIN(15));

sys/arch/arm/imx/imx51_ipuv3.c

405

reg = __SHIFTIN(div / 16 * 2, DI_DW_SET_DOWN);

sys/arch/arm/imx/imx51_ipuv3.c

465

reg = __SHIFTIN(3 - 1, DI_SYNC_AS_GEN_VSYNC_SEL) |

sys/arch/arm/imx/imx51_ipuv3.c

466

__SHIFTIN(0x2, DI_SYNC_AS_GEN_SYNC_START);

sys/arch/arm/imx/imx51_ipuv3.c

550

__SHIFTIN(0x8, CM_DISP_GEN_MCU_T);

sys/arch/arm/imx/imx51reg.h

299

#define PAD_CTL_PUS_100K_PD __SHIFTIN(0x0, PAD_CTL_PUS_MASK)

sys/arch/arm/imx/imx51reg.h

300

#define PAD_CTL_PUS_47K_PU __SHIFTIN(0x1, PAD_CTL_PUS_MASK)

sys/arch/arm/imx/imx51reg.h

301

#define PAD_CTL_PUS_100K_PU __SHIFTIN(0x2, PAD_CTL_PUS_MASK)

sys/arch/arm/imx/imx51reg.h

302

#define PAD_CTL_PUS_22K_PU __SHIFTIN(0x3, PAD_CTL_PUS_MASK)

sys/arch/arm/imx/imx51reg.h

305

#define PAD_CTL_DSE_LOW __SHIFTIN(0x0, PAD_CTL_DSE_MASK)

sys/arch/arm/imx/imx51reg.h

306

#define PAD_CTL_DSE_MID __SHIFTIN(0x1, PAD_CTL_DSE_MASK)

sys/arch/arm/imx/imx51reg.h

307

#define PAD_CTL_DSE_HIGH __SHIFTIN(0x2, PAD_CTL_DSE_MASK)

sys/arch/arm/imx/imx51reg.h

308

#define PAD_CTL_DSE_MAX __SHIFTIN(0x3, PAD_CTL_DSE_MASK)

sys/arch/arm/imx/imxgpio.c

159

v |= __SHIFTIN(gtype, mask);

sys/arch/arm/imx/imxpciereg.h

190

#define PCIE_PL_IATURC1_TYPE_IO __SHIFTIN(0, PCIE_PL_IATURC1_TYPE)

sys/arch/arm/imx/imxpciereg.h

191

#define PCIE_PL_IATURC1_TYPE_MEM __SHIFTIN(2, PCIE_PL_IATURC1_TYPE)

sys/arch/arm/imx/imxpciereg.h

192

#define PCIE_PL_IATURC1_TYPE_CFG0 __SHIFTIN(4, PCIE_PL_IATURC1_TYPE)

sys/arch/arm/imx/imxpciereg.h

193

#define PCIE_PL_IATURC1_TYPE_CFG1 __SHIFTIN(5, PCIE_PL_IATURC1_TYPE)

sys/arch/arm/imx/imxpciereg.h

87

#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 __SHIFTIN(0x1, PCIE_RC_LCR_MAX_LINK_SPEEDS)

sys/arch/arm/imx/imxpciereg.h

88

#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 __SHIFTIN(0x2, PCIE_RC_LCR_MAX_LINK_SPEEDS)

sys/arch/arm/imx/imxpwm.c

123

pr = __SHIFTIN(cycles - 2, PWM_PR_PERIOD);

sys/arch/arm/imx/imxpwm.c

127

cr |= __SHIFTIN(div - 1, PWM_CR_PRESCALER);

sys/arch/arm/imx/imxpwm.c

130

cr |= __SHIFTIN(1, PWM_CR_POUTC);

sys/arch/arm/imx/imxpwm.c

133

sar = __SHIFTIN(act_cycles, PWM_PR_PERIOD);

sys/arch/arm/imx/imxpwm.c

165

reg |= __SHIFTIN(CLKSRC_IPG_CLK, PWM_CR_CLKSRC);

sys/arch/arm/imx/imxsnvs.c

179

h = __SHIFTIN((c >> 32) & SNVS_LPSRTCMR_SRTC, SNVS_LPSRTCMR_SRTC);

sys/arch/arm/imx/imxspi.c

112

__SHIFTIN(0, IMXSPI_TYPE(CON_DRCTL)) |

sys/arch/arm/imx/imxspi.c

113

__SHIFTIN(8 - 1, IMXSPI_TYPE(CON_BITCOUNT)) |

sys/arch/arm/imx/imxspi.c

114

__SHIFTIN(0xf, IMXSPI(CON_MODE)) | IMXSPI(CON_ENABLE));

sys/arch/arm/imx/imxspi.c

145

contrl |= __SHIFTIN(div_cnt, CSPI_CON_DIV);

sys/arch/arm/imx/imxspi.c

193

contrl |= __SHIFTIN(div_cnt, ECSPI_CON_DIV);

sys/arch/arm/imx/imxspi.c

194

contrl |= __SHIFTIN(slave, ECSPI_CON_CS);

sys/arch/arm/imx/imxspi.c

195

contrl |= __SHIFTIN(__BIT(slave), ECSPI_CON_MODE);

sys/arch/arm/imx/imxspi.c

199

config &= ~(__SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL) |

sys/arch/arm/imx/imxspi.c

200

__SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL) |

sys/arch/arm/imx/imxspi.c

201

__SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA));

sys/arch/arm/imx/imxspi.c

208

config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA);

sys/arch/arm/imx/imxspi.c

212

config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL);

sys/arch/arm/imx/imxspi.c

213

config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL);

sys/arch/arm/imx/imxspi.c

217

config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA);

sys/arch/arm/imx/imxspi.c

218

config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL);

sys/arch/arm/imx/imxspi.c

219

config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL);

sys/arch/arm/imx/imxspi.c

224

config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SSB_CTL);

sys/arch/arm/imx/imxspi.c

312

chipselect |= __SHIFTIN(st->st_slave, IMXSPI_TYPE(CON_CS));

sys/arch/arm/imx/imxusb.c

309

reg = ULPI_RUN | __SHIFTIN(addr, ULPI_ADDR);

sys/arch/arm/imx/imxusb.c

324

reg = ULPI_RUN | ULPI_RW | __SHIFTIN(addr, ULPI_ADDR) | __SHIFTIN(data, ULPI_DATWR);

sys/arch/arm/imx/imxusbreg.h

100

#define PORTSC_PTS_ULPI __SHIFTIN(2,PORTSC_PTS)

sys/arch/arm/imx/imxusbreg.h

101

#define PORTSC_PTS_SERIAL __SHIFTIN(3,PORTSC_PTS)

sys/arch/arm/imx/imxusbreg.h

89

#define USBMODE_CM_IDLE __SHIFTIN(0,USBMODE_CM)

sys/arch/arm/imx/imxusbreg.h

90

#define USBMODE_CM_DEVICE __SHIFTIN(2,USBMODE_CM)

sys/arch/arm/imx/imxusbreg.h

91

#define USBMODE_CM_HOST __SHIFTIN(3,USBMODE_CM)

sys/arch/arm/imx/imxusbreg.h

98

#define PORTSC_PTS_UTMI __SHIFTIN(0,PORTSC_PTS)

sys/arch/arm/imx/imxusbreg.h

99

#define PORTSC_PTS_PHILIPS __SHIFTIN(1,PORTSC_PTS) /* not in i.MX51*/

sys/arch/arm/imx/imxwdog.c

126

reg |= __SHIFTIN(sc->sc_wdog_period * 2 - 1, WCR_WT);

sys/arch/arm/imx/imxwdog.c

159

reg |= __SHIFTIN(sc->sc_wdog_period * 2 - 1, WCR_WT);

sys/arch/arm/include/armreg.h

522

#define TTBR_RGN_NC __SHIFTIN(0, TTBR_RGN_MASK)

sys/arch/arm/include/armreg.h

523

#define TTBR_RGN_WBWA __SHIFTIN(1, TTBR_RGN_MASK)

sys/arch/arm/include/armreg.h

524

#define TTBR_RGN_WT __SHIFTIN(2, TTBR_RGN_MASK)

sys/arch/arm/include/armreg.h

525

#define TTBR_RGN_WBNWA __SHIFTIN(3, TTBR_RGN_MASK)

sys/arch/arm/include/fenv.h

49

*(__envp) = __SHIFTIN((__val), VFP_FPSCR_CSUM)

sys/arch/arm/include/fenv.h

51

*(__envp) = __SHIFTIN((__val), VFP_FPSCR_ESUM)

sys/arch/arm/include/fenv.h

53

*(__envp) = __SHIFTIN((__val), VFP_FPSCR_RMODE)

sys/arch/arm/nvidia/tegra124_car.c

1073

bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE,

sys/arch/arm/nvidia/tegra124_car.c

1076

bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM,

sys/arch/arm/nvidia/tegra124_car.c

1084

base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM);

sys/arch/arm/nvidia/tegra124_car.c

1085

base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN);

sys/arch/arm/nvidia/tegra124_car.c

1086

base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP);

sys/arch/arm/nvidia/tegra124_car.c

1098

bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN,

sys/arch/arm/nvidia/tegra124_car.c

1101

bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ,

sys/arch/arm/nvidia/tegra124_car.c

1113

__SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) |

sys/arch/arm/nvidia/tegra124_car.c

1114

__SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) |

sys/arch/arm/nvidia/tegra124_car.c

1115

__SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP),

sys/arch/arm/nvidia/tegra124_car.c

1178

v |= __SHIFTIN(src, tmux->bits);

sys/arch/arm/nvidia/tegra124_car.c

1354

v |= __SHIFTIN(raw_div, tdiv->bits);

sys/arch/arm/nvidia/tegra124_car.c

837

__SHIFTIN(stable_count, CAR_UTMIP_PLL_CFG2_STABLE_COUNT) |

sys/arch/arm/nvidia/tegra124_car.c

838

__SHIFTIN(active_dly_count, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT),

sys/arch/arm/nvidia/tegra124_car.c

846

__SHIFTIN(enable_dly_count, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT) |

sys/arch/arm/nvidia/tegra124_car.c

847

__SHIFTIN(xtal_freq_count, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT),

sys/arch/arm/nvidia/tegra124_car.c

871

val = __SHIFTIN(25, CAR_PLLREFE_BASE_DIVN) |

sys/arch/arm/nvidia/tegra124_car.c

872

__SHIFTIN(1, CAR_PLLREFE_BASE_DIVM);

sys/arch/arm/nvidia/tegra124_xusbpad.c

123

__SHIFTIN(XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_SATA,

sys/arch/arm/nvidia/tegra124_xusbpad.c

217

__SHIFTIN(hsl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL) |

sys/arch/arm/nvidia/tegra124_xusbpad.c

218

__SHIFTIN(XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL,

sys/arch/arm/nvidia/tegra124_xusbpad.c

225

__SHIFTIN(hcl[0],

sys/arch/arm/nvidia/tegra124_xusbpad.c

227

__SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL,

sys/arch/arm/nvidia/tegra124_xusbpad.c

229

__SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(0),

sys/arch/arm/nvidia/tegra124_xusbpad.c

239

__SHIFTIN(hcl[1],

sys/arch/arm/nvidia/tegra124_xusbpad.c

241

__SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL,

sys/arch/arm/nvidia/tegra124_xusbpad.c

243

__SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(1),

sys/arch/arm/nvidia/tegra124_xusbpad.c

253

__SHIFTIN(hcl[2],

sys/arch/arm/nvidia/tegra124_xusbpad.c

255

__SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL,

sys/arch/arm/nvidia/tegra124_xusbpad.c

257

__SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(2),

sys/arch/arm/nvidia/tegra124_xusbpad.c

268

__SHIFTIN(htra,

sys/arch/arm/nvidia/tegra124_xusbpad.c

270

__SHIFTIN(hic,

sys/arch/arm/nvidia/tegra124_xusbpad.c

279

__SHIFTIN(htra,

sys/arch/arm/nvidia/tegra124_xusbpad.c

281

__SHIFTIN(hic,

sys/arch/arm/nvidia/tegra124_xusbpad.c

290

__SHIFTIN(htra,

sys/arch/arm/nvidia/tegra124_xusbpad.c

292

__SHIFTIN(hic,

sys/arch/arm/nvidia/tegra210_car.c

1016

__SHIFTIN(0xe, CAR_PLLE_BASE_DIVP_CML) |

sys/arch/arm/nvidia/tegra210_car.c

1017

__SHIFTIN(0x7d, CAR_PLLE_BASE_DIVN) |

sys/arch/arm/nvidia/tegra210_car.c

1018

__SHIFTIN(0x2, CAR_PLLE_BASE_DIVM),

sys/arch/arm/nvidia/tegra210_car.c

1031

__SHIFTIN(1, CAR_PLLE_SS_CNTL_SSCINC) |

sys/arch/arm/nvidia/tegra210_car.c

1032

__SHIFTIN(0x23, CAR_PLLE_SS_CNTL_SSCINCINTRV) |

sys/arch/arm/nvidia/tegra210_car.c

1033

__SHIFTIN(0x21, CAR_PLLE_SS_CNTL_SSCMAX),

sys/arch/arm/nvidia/tegra210_car.c

1201

bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE,

sys/arch/arm/nvidia/tegra210_car.c

1204

bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM,

sys/arch/arm/nvidia/tegra210_car.c

1212

base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM);

sys/arch/arm/nvidia/tegra210_car.c

1213

base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN);

sys/arch/arm/nvidia/tegra210_car.c

1214

base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP);

sys/arch/arm/nvidia/tegra210_car.c

1226

bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN,

sys/arch/arm/nvidia/tegra210_car.c

1229

bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ,

sys/arch/arm/nvidia/tegra210_car.c

1241

__SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) |

sys/arch/arm/nvidia/tegra210_car.c

1242

__SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) |

sys/arch/arm/nvidia/tegra210_car.c

1243

__SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP),

sys/arch/arm/nvidia/tegra210_car.c

1284

v |= __SHIFTIN(src, tmux->bits);

sys/arch/arm/nvidia/tegra210_car.c

1452

v |= __SHIFTIN(raw_div, tdiv->bits);

sys/arch/arm/nvidia/tegra210_car.c

952

__SHIFTIN(0x19, CAR_PLLU_BASE_DIVN) |

sys/arch/arm/nvidia/tegra210_car.c

953

__SHIFTIN(0x2, CAR_PLLU_BASE_DIVM) |

sys/arch/arm/nvidia/tegra210_car.c

954

__SHIFTIN(0x1, CAR_PLLU_BASE_DIVP),

sys/arch/arm/nvidia/tegra210_car.c

993

__SHIFTIN(0x4, CAR_PLLREFE_BASE_DIVM) |

sys/arch/arm/nvidia/tegra210_car.c

994

__SHIFTIN(0x41, CAR_PLLREFE_BASE_DIVN) |

sys/arch/arm/nvidia/tegra210_car.c

995

__SHIFTIN(0x0, CAR_PLLREFE_BASE_DIVP) |

sys/arch/arm/nvidia/tegra210_car.c

996

__SHIFTIN(0x0, CAR_PLLREFE_BASE_KCP),

sys/arch/arm/nvidia/tegra210_xusbpad.c

237

__SHIFTIN(0x136, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_CTRL),

sys/arch/arm/nvidia/tegra210_xusbpad.c

240

__SHIFTIN(0x2a, XUSB_PADCTL_UPHY_PLL_P0_CTL_5_DCO_CTRL),

sys/arch/arm/nvidia/tegra210_xusbpad.c

250

__SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REFCLK_SEL),

sys/arch/arm/nvidia/tegra210_xusbpad.c

253

__SHIFTIN(2, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TXCLKREF_SEL),

sys/arch/arm/nvidia/tegra210_xusbpad.c

259

__SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_MDIV),

sys/arch/arm/nvidia/tegra210_xusbpad.c

262

__SHIFTIN(0x19, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_NDIV),

sys/arch/arm/nvidia/tegra210_xusbpad.c

265

__SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_PSDIV),

sys/arch/arm/nvidia/tegra210_xusbpad.c

386

__SHIFTIN(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB,

sys/arch/arm/nvidia/tegra210_xusbpad.c

391

__SHIFTIN(0x7, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_HS_DISCON_LEVEL) |

sys/arch/arm/nvidia/tegra210_xusbpad.c

392

__SHIFTIN(0x0, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_HS_SQUELCH_LEVEL),

sys/arch/arm/nvidia/tegra210_xusbpad.c

396

__SHIFTIN(hs_curr_level, XUSB_PADCTL_USB2_OTG_PADn_CTL_0_HS_CURR_LEVEL),

sys/arch/arm/nvidia/tegra210_xusbpad.c

402

__SHIFTIN(hs_term_range_adj, XUSB_PADCTL_USB2_OTG_PADn_CTL_1_TERM_RANGE_ADJ) |

sys/arch/arm/nvidia/tegra210_xusbpad.c

403

__SHIFTIN(ext_rpd_ctrl, XUSB_PADCTL_USB2_OTG_PADn_CTL_1_RPD_CTRL),

sys/arch/arm/nvidia/tegra210_xusbpad.c

414

__SHIFTIN(0x1e, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_TRK_START_TIMER) |

sys/arch/arm/nvidia/tegra210_xusbpad.c

415

__SHIFTIN(0xa, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_TRK_DONE_RESET_TIMER),

sys/arch/arm/nvidia/tegra210_xusbpad.c

435

__SHIFTIN(0x136, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_CTRL),

sys/arch/arm/nvidia/tegra210_xusbpad.c

438

__SHIFTIN(0x2a, XUSB_PADCTL_UPHY_PLL_S0_CTL_5_DCO_CTRL),

sys/arch/arm/nvidia/tegra210_xusbpad.c

448

__SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REFCLK_SEL),

sys/arch/arm/nvidia/tegra210_xusbpad.c

451

__SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_TXCLKREF_SEL),

sys/arch/arm/nvidia/tegra210_xusbpad.c

457

__SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_MDIV),

sys/arch/arm/nvidia/tegra210_xusbpad.c

460

__SHIFTIN(0x1e, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_NDIV),

sys/arch/arm/nvidia/tegra210_xusbpad.c

463

__SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_PSDIV),

sys/arch/arm/nvidia/tegra210_xusbpad.c

712

SETCLR4(sc, lane->reg, __SHIFTIN(func, lane->mask), lane->mask);

sys/arch/arm/nvidia/tegra210_xusbpad.c

849

SETCLR4(sc, port->reg, __SHIFTIN(internal, port->internal_mask), port->internal_mask);

sys/arch/arm/nvidia/tegra210_xusbpad.c

850

SETCLR4(sc, port->reg, __SHIFTIN(modeval, port->mask), port->mask);

sys/arch/arm/nvidia/tegra210_xusbpad.c

869

SETCLR4(sc, port->reg, __SHIFTIN(internal, port->internal_mask), port->internal_mask);

sys/arch/arm/nvidia/tegra210_xusbpad.c

870

SETCLR4(sc, port->reg, __SHIFTIN(companion, port->mask), port->mask);

sys/arch/arm/nvidia/tegra210_xusbpad.c

873

__SHIFTIN(2, XUSB_PADCTL_UPHY_USB3_PADn_ECTL_2_TX_TERM_CTRL),

sys/arch/arm/nvidia/tegra210_xusbpad.c

876

__SHIFTIN(0xfc, XUSB_PADCTL_UPHY_USB3_PADn_ECTL_2_RX_CTLE),

sys/arch/arm/nvidia/tegra210_xusbpad.c

880

__SHIFTIN(0x01c7, XUSB_PADCTL_UPHY_USB3_PADn_ECTL_4_RX_CDR_CTRL),

sys/arch/arm/nvidia/tegra_ahcisata.c

280

__SHIFTIN(0x7, TEGRA_T_SATA0_NVOOB_COMMA_CNT) |

sys/arch/arm/nvidia/tegra_ahcisata.c

281

__SHIFTIN(0x3, TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH) |

sys/arch/arm/nvidia/tegra_ahcisata.c

282

__SHIFTIN(0x1, TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_MODE),

sys/arch/arm/nvidia/tegra_ahcisata.c

288

__SHIFTIN(0xc, TEGRA_T_SATA0_CFG_2NVOOB_2_COMWAKE_IDLE_CNT_LOW),

sys/arch/arm/nvidia/tegra_ahcisata.c

301

__SHIFTIN(gen1_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP) |

sys/arch/arm/nvidia/tegra_ahcisata.c

302

__SHIFTIN(gen1_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK),

sys/arch/arm/nvidia/tegra_ahcisata.c

306

__SHIFTIN(gen2_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP) |

sys/arch/arm/nvidia/tegra_ahcisata.c

307

__SHIFTIN(gen2_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK),

sys/arch/arm/nvidia/tegra_ahcisata.c

311

__SHIFTIN(0x2800, TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ));

sys/arch/arm/nvidia/tegra_ahcisata.c

313

__SHIFTIN(0x23, TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1));

sys/arch/arm/nvidia/tegra_ahcisata.c

322

__SHIFTIN(0x0106, TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE) |

sys/arch/arm/nvidia/tegra_ahcisata.c

323

__SHIFTIN(0x1, TEGRA_T_SATA0_BKDOOR_CC_PROG_IF));

sys/arch/arm/nvidia/tegra_ahcisata.c

351

__SHIFTIN(0x10000, TEGRA_SATA_FPCI_BAR_START) |

sys/arch/arm/nvidia/tegra_ahcisata.c

355

__SHIFTIN(0x8000, TEGRA_T_SATA0_CFG9_BASE_ADDRESS));

sys/arch/arm/nvidia/tegra_apbdma.c

285

csr |= __SHIFTIN(ch->ch_req, APBDMACHAN_CSR_REQ_SEL);

sys/arch/arm/nvidia/tegra_apbdma.c

323

ahb_seq |= __SHIFTIN(APBDMACHAN_AHB_SEQ_BUS_WIDTH_32,

sys/arch/arm/nvidia/tegra_apbdma.c

337

ahb_seq |= __SHIFTIN(APBDMACHAN_AHB_SEQ_BURST_1,

sys/arch/arm/nvidia/tegra_apbdma.c

341

ahb_seq |= __SHIFTIN(APBDMACHAN_AHB_SEQ_BURST_4,

sys/arch/arm/nvidia/tegra_apbdma.c

345

ahb_seq |= __SHIFTIN(APBDMACHAN_AHB_SEQ_BURST_8,

sys/arch/arm/nvidia/tegra_apbdma.c

369

ahb_seq |= __SHIFTIN(APBDMACHAN_AHB_SEQ_WRAP_NO_WRAP,

sys/arch/arm/nvidia/tegra_apbdma.c

373

ahb_seq |= __SHIFTIN(APBDMACHAN_AHB_SEQ_WRAP_32,

sys/arch/arm/nvidia/tegra_apbdma.c

377

ahb_seq |= __SHIFTIN(APBDMACHAN_AHB_SEQ_WRAP_64,

sys/arch/arm/nvidia/tegra_apbdma.c

381

ahb_seq |= __SHIFTIN(APBDMACHAN_AHB_SEQ_WRAP_128,

sys/arch/arm/nvidia/tegra_apbdma.c

385

ahb_seq |= __SHIFTIN(APBDMACHAN_AHB_SEQ_WRAP_256,

sys/arch/arm/nvidia/tegra_apbdma.c

389

ahb_seq |= __SHIFTIN(APBDMACHAN_AHB_SEQ_WRAP_512,

sys/arch/arm/nvidia/tegra_apbdma.c

393

ahb_seq |= __SHIFTIN(APBDMACHAN_AHB_SEQ_WRAP_1024,

sys/arch/arm/nvidia/tegra_apbdma.c

397

ahb_seq |= __SHIFTIN(APBDMACHAN_AHB_SEQ_WRAP_2048,

sys/arch/arm/nvidia/tegra_apbdma.c

409

apb_seq |= __SHIFTIN(APBDMACHAN_APB_SEQ_BUS_WIDTH_8,

sys/arch/arm/nvidia/tegra_apbdma.c

413

apb_seq |= __SHIFTIN(APBDMACHAN_APB_SEQ_BUS_WIDTH_16,

sys/arch/arm/nvidia/tegra_apbdma.c

417

apb_seq |= __SHIFTIN(APBDMACHAN_APB_SEQ_BUS_WIDTH_32,

sys/arch/arm/nvidia/tegra_apbdma.c

435

apb_seq |= __SHIFTIN(APBDMACHAN_APB_SEQ_WRAP_NO_WRAP,

sys/arch/arm/nvidia/tegra_apbdma.c

439

apb_seq |= __SHIFTIN(APBDMACHAN_APB_SEQ_WRAP_1,

sys/arch/arm/nvidia/tegra_apbdma.c

443

apb_seq |= __SHIFTIN(APBDMACHAN_APB_SEQ_WRAP_2,

sys/arch/arm/nvidia/tegra_apbdma.c

447

apb_seq |= __SHIFTIN(APBDMACHAN_APB_SEQ_WRAP_4,

sys/arch/arm/nvidia/tegra_apbdma.c

451

apb_seq |= __SHIFTIN(APBDMACHAN_APB_SEQ_WRAP_8,

sys/arch/arm/nvidia/tegra_apbdma.c

455

apb_seq |= __SHIFTIN(APBDMACHAN_APB_SEQ_WRAP_16,

sys/arch/arm/nvidia/tegra_apbdma.c

459

apb_seq |= __SHIFTIN(APBDMACHAN_APB_SEQ_WRAP_32,

sys/arch/arm/nvidia/tegra_apbdma.c

463

apb_seq |= __SHIFTIN(APBDMACHAN_APB_SEQ_WRAP_64,

sys/arch/arm/nvidia/tegra_cec.c

235

val = __SHIFTIN(sc->sc_txbuf[sc->sc_txcur],

sys/arch/arm/nvidia/tegra_cec.c

357

__SHIFTIN(val, CEC_HW_CONTROL_RX_LOGICAL_ADDRS),

sys/arch/arm/nvidia/tegra_drm_mode.c

1002

__SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_OWNER) |

sys/arch/arm/nvidia/tegra_drm_mode.c

1003

__SHIFTIN(3, HDMI_NV_PDISP_SOR_STATE2_ASY_SUBOWNER) |

sys/arch/arm/nvidia/tegra_drm_mode.c

1004

__SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_CRCMODE) |

sys/arch/arm/nvidia/tegra_drm_mode.c

1005

__SHIFTIN(1, HDMI_NV_PDISP_SOR_STATE2_ASY_PROTOCOL);

sys/arch/arm/nvidia/tegra_drm_mode.c

1013

__SHIFTIN(HDMI_NV_PDISP_SOR_STATE1_ASY_HEAD_OPMODE_AWAKE,

sys/arch/arm/nvidia/tegra_drm_mode.c

1033

__SHIFTIN(rekey, HDMI_NV_PDISP_HDMI_CTRL_REKEY) |

sys/arch/arm/nvidia/tegra_drm_mode.c

1034

__SHIFTIN(max_ac_packet, HDMI_NV_PDISP_HDMI_CTRL_MAX_AC_PACKET);

sys/arch/arm/nvidia/tegra_drm_mode.c

1050

__SHIFTIN(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO,

sys/arch/arm/nvidia/tegra_drm_mode.c

1056

__SHIFTIN(n - 1, HDMI_NV_PDISP_AUDIO_N_VALUE));

sys/arch/arm/nvidia/tegra_drm_mode.c

1061

__SHIFTIN(1, HDMI_NV_PDISP_HDMI_SPARE_CTS_RESET_VAL));

sys/arch/arm/nvidia/tegra_drm_mode.c

418

cfg = __SHIFTIN(DC_DISP_CURSOR_START_ADDR_CLIPPING_DISPLAY,

sys/arch/arm/nvidia/tegra_drm_mode.c

422

cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_32,

sys/arch/arm/nvidia/tegra_drm_mode.c

426

cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_64,

sys/arch/arm/nvidia/tegra_drm_mode.c

430

cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_128,

sys/arch/arm/nvidia/tegra_drm_mode.c

434

cfg |= __SHIFTIN(DC_DISP_CURSOR_START_ADDR_SIZE_256,

sys/arch/arm/nvidia/tegra_drm_mode.c

450

cfg |= __SHIFTIN((paddr >> 10) & 0x3fffff,

sys/arch/arm/nvidia/tegra_drm_mode.c

460

cfg |= __SHIFTIN(2, DC_DISP_BLEND_CURSOR_CONTROL_DST_BLEND_FACTOR_SEL);

sys/arch/arm/nvidia/tegra_drm_mode.c

462

cfg |= __SHIFTIN(1, DC_DISP_BLEND_CURSOR_CONTROL_SRC_BLEND_FACTOR_SEL);

sys/arch/arm/nvidia/tegra_drm_mode.c

464

cfg |= __SHIFTIN(255, DC_DISP_BLEND_CURSOR_CONTROL_ALPHA);

sys/arch/arm/nvidia/tegra_drm_mode.c

470

__SHIFTIN(tegra_crtc->cursor_x, DC_DISP_CURSOR_POSITION_H) |

sys/arch/arm/nvidia/tegra_drm_mode.c

471

__SHIFTIN(tegra_crtc->cursor_y, DC_DISP_CURSOR_POSITION_V));

sys/arch/arm/nvidia/tegra_drm_mode.c

518

__SHIFTIN(x & 0x3fff, DC_DISP_CURSOR_POSITION_H) |

sys/arch/arm/nvidia/tegra_drm_mode.c

519

__SHIFTIN(y & 0x3fff, DC_DISP_CURSOR_POSITION_V));

sys/arch/arm/nvidia/tegra_drm_mode.c

584

__SHIFTIN(DC_WINC_A_COLOR_DEPTH_DEPTH_T_A8R8G8B8,

sys/arch/arm/nvidia/tegra_drm_mode.c

589

__SHIFTIN(DC_WINC_A_BYTE_SWAP_SWAP_NOSWAP,

sys/arch/arm/nvidia/tegra_drm_mode.c

599

__SHIFTIN(0, DC_WINC_A_POSITION_V) |

sys/arch/arm/nvidia/tegra_drm_mode.c

600

__SHIFTIN(0, DC_WINC_A_POSITION_H));

sys/arch/arm/nvidia/tegra_drm_mode.c

602

__SHIFTIN(mode->crtc_vdisplay, DC_WINC_A_SIZE_V) |

sys/arch/arm/nvidia/tegra_drm_mode.c

603

__SHIFTIN(mode->crtc_hdisplay, DC_WINC_A_SIZE_H));

sys/arch/arm/nvidia/tegra_drm_mode.c

605

__SHIFTIN(mode->crtc_vdisplay, DC_WINC_A_PRESCALED_SIZE_V) |

sys/arch/arm/nvidia/tegra_drm_mode.c

606

__SHIFTIN(mode->crtc_hdisplay * (TEGRA_DC_DEPTH / 8),

sys/arch/arm/nvidia/tegra_drm_mode.c

609

__SHIFTIN(mode->crtc_hdisplay * (TEGRA_DC_DEPTH / 8),

sys/arch/arm/nvidia/tegra_drm_mode.c

620

__SHIFTIN(1, DC_DISP_DISP_TIMING_OPTIONS_VSYNC_POS));

sys/arch/arm/nvidia/tegra_drm_mode.c

622

__SHIFTIN(DC_DISP_DISP_COLOR_CONTROL_BASE_COLOR_SIZE_888,

sys/arch/arm/nvidia/tegra_drm_mode.c

627

__SHIFTIN(DC_DISP_H_PULSE2_CONTROL_V_QUAL_VACTIVE,

sys/arch/arm/nvidia/tegra_drm_mode.c

629

__SHIFTIN(DC_DISP_H_PULSE2_CONTROL_LAST_END_A,

sys/arch/arm/nvidia/tegra_drm_mode.c

634

__SHIFTIN(pulse_start, DC_DISP_H_PULSE2_POSITION_A_START) |

sys/arch/arm/nvidia/tegra_drm_mode.c

635

__SHIFTIN(pulse_start + 8, DC_DISP_H_PULSE2_POSITION_A_END));

sys/arch/arm/nvidia/tegra_drm_mode.c

641

__SHIFTIN(0, DC_DISP_DISP_CLOCK_CONTROL_PIXEL_CLK_DIVIDER) |

sys/arch/arm/nvidia/tegra_drm_mode.c

642

__SHIFTIN(div, DC_DISP_DISP_CLOCK_CONTROL_SHIFT_CLK_DIVIDER));

sys/arch/arm/nvidia/tegra_drm_mode.c

646

__SHIFTIN(1, DC_DISP_REF_TO_SYNC_V) |

sys/arch/arm/nvidia/tegra_drm_mode.c

647

__SHIFTIN(1, DC_DISP_REF_TO_SYNC_H));

sys/arch/arm/nvidia/tegra_drm_mode.c

649

__SHIFTIN(vspw, DC_DISP_SYNC_WIDTH_V) |

sys/arch/arm/nvidia/tegra_drm_mode.c

650

__SHIFTIN(hspw, DC_DISP_SYNC_WIDTH_H));

sys/arch/arm/nvidia/tegra_drm_mode.c

652

__SHIFTIN(vbp, DC_DISP_BACK_PORCH_V) |

sys/arch/arm/nvidia/tegra_drm_mode.c

653

__SHIFTIN(hbp, DC_DISP_BACK_PORCH_H));

sys/arch/arm/nvidia/tegra_drm_mode.c

655

__SHIFTIN(vfp, DC_DISP_FRONT_PORCH_V) |

sys/arch/arm/nvidia/tegra_drm_mode.c

656

__SHIFTIN(hfp, DC_DISP_FRONT_PORCH_H));

sys/arch/arm/nvidia/tegra_drm_mode.c

658

__SHIFTIN(mode->crtc_vdisplay, DC_DISP_DISP_ACTIVE_V) |

sys/arch/arm/nvidia/tegra_drm_mode.c

659

__SHIFTIN(mode->crtc_hdisplay, DC_DISP_DISP_ACTIVE_H));

sys/arch/arm/nvidia/tegra_drm_mode.c

685

__SHIFTIN(DC_WINBUF_A_SURFACE_KIND_SURFACE_KIND_PITCH,

sys/arch/arm/nvidia/tegra_drm_mode.c

750

__SHIFTIN(DC_CMD_DISPLAY_COMMAND_DISPLAY_CTRL_MODE_C_DISPLAY,

sys/arch/arm/nvidia/tegra_drm_mode.c

946

__SHIFTIN(div >> 2, HDMI_NV_PDISP_SOR_REFCLK_DIV_INT) |

sys/arch/arm/nvidia/tegra_drm_mode.c

947

__SHIFTIN(div & 3, HDMI_NV_PDISP_SOR_REFCLK_DIV_FRAC));

sys/arch/arm/nvidia/tegra_drm_mode.c

950

__SHIFTIN(HDMI_NV_PDISP_SOR_CSTM_MODE_TMDS,

sys/arch/arm/nvidia/tegra_drm_mode.c

952

__SHIFTIN(2, HDMI_NV_PDISP_SOR_CSTM_ROTCLK) |

sys/arch/arm/nvidia/tegra_drm_mode.c

961

__SHIFTIN(2, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_UNITS) |

sys/arch/arm/nvidia/tegra_drm_mode.c

962

__SHIFTIN(1, HDMI_NV_PDISP_SOR_SEQ_INST_WAIT_TIME);

sys/arch/arm/nvidia/tegra_drm_mode.c

966

input_ctrl = __SHIFTIN(tegra_crtc->index,

sys/arch/arm/nvidia/tegra_ehci.c

165

usbmode |= __SHIFTIN(TEGRA_EHCI_USBMODE_CM_HOST,

sys/arch/arm/nvidia/tegra_ehci.c

174

__SHIFTIN(TEGRA_EHCI_HOSTPC1_DEVLC_PTS_UTMI,

sys/arch/arm/nvidia/tegra_ehci.c

180

__SHIFTIN(0x10, TEGRA_EHCI_TXFILLTUNING_TXFIFOTHRES));

sys/arch/arm/nvidia/tegra_i2c.c

190

__SHIFTIN(0x19, I2C_CLK_DIVISOR_STD_FAST_MODE) |

sys/arch/arm/nvidia/tegra_i2c.c

191

__SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE));

sys/arch/arm/nvidia/tegra_i2c.c

198

__SHIFTIN(7, I2C_FIFO_CONTROL_TX_FIFO_TRIG) |

sys/arch/arm/nvidia/tegra_i2c.c

199

__SHIFTIN(0, I2C_FIFO_CONTROL_RX_FIFO_TRIG));

sys/arch/arm/nvidia/tegra_i2c.c

363

__SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ,

sys/arch/arm/nvidia/tegra_i2c.c

365

__SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) |

sys/arch/arm/nvidia/tegra_i2c.c

366

__SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) |

sys/arch/arm/nvidia/tegra_i2c.c

367

__SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C,

sys/arch/arm/nvidia/tegra_i2c.c

369

__SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ,

sys/arch/arm/nvidia/tegra_i2c.c

373

__SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE));

sys/arch/arm/nvidia/tegra_i2c.c

378

__SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR));

sys/arch/arm/nvidia/tegra_i2c.c

421

__SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ,

sys/arch/arm/nvidia/tegra_i2c.c

423

__SHIFTIN(sc->sc_cid, I2C_IOPACKET_WORD0_CONTROLLERID) |

sys/arch/arm/nvidia/tegra_i2c.c

424

__SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) |

sys/arch/arm/nvidia/tegra_i2c.c

425

__SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C,

sys/arch/arm/nvidia/tegra_i2c.c

427

__SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ,

sys/arch/arm/nvidia/tegra_i2c.c

431

__SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE));

sys/arch/arm/nvidia/tegra_i2c.c

435

__SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR));

sys/arch/arm/nvidia/tegra_pcie.c

466

cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_4_1,

sys/arch/arm/nvidia/tegra_pcie.c

471

cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_2_1,

sys/arch/arm/nvidia/tegra_pinmux.c

139

cfg |= __SHIFTIN(func, PINMUX_PM);

sys/arch/arm/nvidia/tegra_pinmux.c

143

cfg |= __SHIFTIN(val, PINMUX_PUPD);

sys/arch/arm/nvidia/tegra_pinmux.c

147

cfg |= __SHIFTIN(val, PINMUX_TRISTATE);

sys/arch/arm/nvidia/tegra_pinmux.c

151

cfg |= __SHIFTIN(val, PINMUX_E_OD);

sys/arch/arm/nvidia/tegra_pinmux.c

155

cfg |= __SHIFTIN(val, PINMUX_LOCK);

sys/arch/arm/nvidia/tegra_pinmux.c

159

cfg |= __SHIFTIN(val, PINMUX_E_IO_HV);

sys/arch/arm/nvidia/tegra_pinmux.c

163

cfg |= __SHIFTIN(val, PINMUX_E_HSM);

sys/arch/arm/nvidia/tegra_pinmux.c

167

cfg |= __SHIFTIN(val, PINMUX_E_SCHMT);

sys/arch/arm/nvidia/tegra_pinmux.c

171

cfg |= __SHIFTIN(val, PINMUX_DRV_TYPE);

sys/arch/arm/nvidia/tegra_pinmux.c

184

cfg |= __SHIFTIN(val, pin_def->tpp_dg.drvdn_mask);

sys/arch/arm/nvidia/tegra_pinmux.c

188

cfg |= __SHIFTIN(val, pin_def->tpp_dg.drvup_mask);

sys/arch/arm/nvidia/tegra_pinmux.c

192

cfg |= __SHIFTIN(val, pin_def->tpp_dg.slwrf_mask);

sys/arch/arm/nvidia/tegra_pinmux.c

196

cfg |= __SHIFTIN(val, pin_def->tpp_dg.slwrr_mask);

sys/arch/arm/nvidia/tegra_pmc.c

164

__SHIFTIN(partid, PMC_PWRGATE_TOGGLE_0_PARTID) |

sys/arch/arm/nvidia/tegra_soctherm.c

347

__SHIFTIN(config->tall, SOC_THERM_TSENSOR_CONFIG0_TALL) |

sys/arch/arm/nvidia/tegra_soctherm.c

351

__SHIFTIN(config->tsample - 1, SOC_THERM_TSENSOR_CONFIG1_TSAMPLE) |

sys/arch/arm/nvidia/tegra_soctherm.c

352

__SHIFTIN(config->tiddq_en, SOC_THERM_TSENSOR_CONFIG1_TIDDQ_EN) |

sys/arch/arm/nvidia/tegra_soctherm.c

353

__SHIFTIN(config->ten_count, SOC_THERM_TSENSOR_CONFIG1_TEN_COUNT) |

sys/arch/arm/nvidia/tegra_soctherm.c

357

__SHIFTIN((uint16_t)s->s_therm_a,

sys/arch/arm/nvidia/tegra_soctherm.c

359

__SHIFTIN((uint16_t)s->s_therm_b,

sys/arch/arm/nvidia/tegra_timer.c

147

TMR_PTV_EN | TMR_PTV_PER | __SHIFTIN(tval, TMR_PTV_VAL));

sys/arch/arm/nvidia/tegra_usbphy.c

226

__SHIFTIN(4, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP) |

sys/arch/arm/nvidia/tegra_usbphy.c

227

__SHIFTIN(3, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB) |

sys/arch/arm/nvidia/tegra_usbphy.c

228

__SHIFTIN(sc->sc_xcvr_hsslew,

sys/arch/arm/nvidia/tegra_usbphy.c

234

__SHIFTIN(sc->sc_term_range_adj,

sys/arch/arm/nvidia/tegra_usbphy.c

241

__SHIFTIN(sc->sc_hsdiscon_level,

sys/arch/arm/nvidia/tegra_usbphy.c

257

__SHIFTIN(5, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT),

sys/arch/arm/nvidia/tegra_usbphy.c

262

__SHIFTIN(0x7530, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A),

sys/arch/arm/nvidia/tegra_usbphy.c

279

__SHIFTIN(sc->sc_idle_wait_delay,

sys/arch/arm/nvidia/tegra_usbphy.c

281

__SHIFTIN(sc->sc_elastic_limit,

sys/arch/arm/nvidia/tegra_usbphy.c

286

__SHIFTIN(sc->sc_hssync_start_delay,

sys/arch/arm/nvidia/tegra_xusb.c

565

msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) |

sys/arch/arm/nvidia/tegra_xusb.c

566

__SHIFTIN(rate / 1000, MAILBOX_DATA_DATA);

sys/arch/arm/nvidia/tegra_xusb.c

569

msg = __SHIFTIN(129, MAILBOX_DATA_TYPE) |

sys/arch/arm/nvidia/tegra_xusb.c

570

__SHIFTIN(rate / 1000, MAILBOX_DATA_DATA);

sys/arch/arm/nvidia/tegra_xusb.c

572

msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) |

sys/arch/arm/nvidia/tegra_xusb.c

573

__SHIFTIN(data, MAILBOX_DATA_DATA);

sys/arch/arm/nvidia/tegra_xusb.c

578

msg = __SHIFTIN(data, MAILBOX_DATA_DATA) |

sys/arch/arm/nvidia/tegra_xusb.c

579

__SHIFTIN(128, MAILBOX_DATA_TYPE);

sys/arch/arm/nvidia/tegra_xusb.c

854

__SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL,

sys/arch/arm/nvidia/tegra_xusb.c

868

__SHIFTIN(code_tag_blocks,

sys/arch/arm/nvidia/tegra_xusb.c

870

__SHIFTIN(code_size_blocks,

sys/arch/arm/nvidia/tegra_xusb.c

878

__SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT,

sys/arch/arm/nvidia/tegra_xusb.c

892

__SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) |

sys/arch/arm/nvidia/tegra_xusb.c

893

__SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI));

sys/arch/arm/nxp/imx6_ccm.c

367

v |= __SHIFTIN(sel, mux->mask);

sys/arch/arm/nxp/imx6_ccm.c

444

v |= __SHIFTIN(n, div->mask);

sys/arch/arm/nxp/imx6_ccm.c

448

v |= __SHIFTIN(divider - 1, div->mask);

sys/arch/arm/nxp/imx6_ccmreg.h

497

#define CCM_ANALOG_MISC1_LVDS_CLK1_SRC_PCIE __SHIFTIN(0xa, CCM_ANALOG_MISC1_LVDS_CLK1_SRC)

sys/arch/arm/nxp/imx6_ccmreg.h

498

#define CCM_ANALOG_MISC1_LVDS_CLK1_SRC_SATA __SHIFTIN(0xb, CCM_ANALOG_MISC1_LVDS_CLK1_SRC)

sys/arch/arm/nxp/imx6_iomux.c

102

reg |= __SHIFTIN(sel, mask);

sys/arch/arm/nxp/imx6_iomuxreg.h

2238

#define PAD_CTL_DDR_SEL_0 __SHIFTIN(0, PAD_CTL_DDR_SEL_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2239

#define PAD_CTL_DDR_SEL_1 __SHIFTIN(1, PAD_CTL_DDR_SEL_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2240

#define PAD_CTL_DDR_SEL_2 __SHIFTIN(2, PAD_CTL_DDR_SEL_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2241

#define PAD_CTL_DDR_SEL_3 __SHIFTIN(3, PAD_CTL_DDR_SEL_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2244

#define PAD_CTL_PUS_100K_PD __SHIFTIN(0x0, PAD_CTL_PUS_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2245

#define PAD_CTL_PUS_47K_PU __SHIFTIN(0x1, PAD_CTL_PUS_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2246

#define PAD_CTL_PUS_100K_PU __SHIFTIN(0x2, PAD_CTL_PUS_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2247

#define PAD_CTL_PUS_22K_PU __SHIFTIN(0x3, PAD_CTL_PUS_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2255

#define PAD_CTL_SPEED_LOW50MHZ __SHIFTIN(0, PAD_CTL_SPEED_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2256

#define PAD_CTL_SPEED_50MHZ __SHIFTIN(1, PAD_CTL_SPEED_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2257

#define PAD_CTL_SPEED_100MHZ __SHIFTIN(2, PAD_CTL_SPEED_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2258

#define PAD_CTL_SPEED_200MHZ __SHIFTIN(3, PAD_CTL_SPEED_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2260

#define PAD_CTL_DSE_HIZ __SHIFTIN(0x0, PAD_CTL_DSE_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2261

#define PAD_CTL_DSE_290OHM __SHIFTIN(0x1, PAD_CTL_DSE_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2262

#define PAD_CTL_DSE_240OHM __SHIFTIN(0x1, PAD_CTL_DSE_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2263

#define PAD_CTL_DSE_121OHM __SHIFTIN(0x2, PAD_CTL_DSE_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2264

#define PAD_CTL_DSE_120OHM __SHIFTIN(0x2, PAD_CTL_DSE_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2265

#define PAD_CTL_DSE_80OHM __SHIFTIN(0x3, PAD_CTL_DSE_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2266

#define PAD_CTL_DSE_76OHM __SHIFTIN(0x3, PAD_CTL_DSE_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2267

#define PAD_CTL_DSE_60OHM __SHIFTIN(0x4, PAD_CTL_DSE_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2268

#define PAD_CTL_DSE_48OHM __SHIFTIN(0x5, PAD_CTL_DSE_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2269

#define PAD_CTL_DSE_47OHM __SHIFTIN(0x4, PAD_CTL_DSE_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2270

#define PAD_CTL_DSE_45OHM __SHIFTIN(0x5, PAD_CTL_DSE_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2271

#define PAD_CTL_DSE_40OHM __SHIFTIN(0x6, PAD_CTL_DSE_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2272

#define PAD_CTL_DSE_37OHM __SHIFTIN(0x6, PAD_CTL_DSE_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2273

#define PAD_CTL_DSE_34OHM __SHIFTIN(0x7, PAD_CTL_DSE_MASK)

sys/arch/arm/nxp/imx6_iomuxreg.h

2274

#define PAD_CTL_DSE_31OHM __SHIFTIN(0x7, PAD_CTL_DSE_MASK)

sys/arch/arm/nxp/imx6_usb.c

277

v |= __SHIFTIN(USBC_UH_USBMODE_CM, USBC_UH_USBMODE_CM_HOST_CONTROLLER);

sys/arch/arm/nxp/imx_ahcisata.c

419

v |= __SHIFTIN(val, gpr13_sata_phy_settings[i].mask);

sys/arch/arm/nxp/imx_ahcisata.c

421

v |= __SHIFTIN(0x12, IOMUX_GPR13_SATA_PHY_7); /* Rx SATA2m */

sys/arch/arm/nxp/imx_ahcisata.c

422

v |= __SHIFTIN(3, IOMUX_GPR13_SATA_PHY_6); /* Rx DPLL mode */

sys/arch/arm/nxp/imx_ahcisata.c

423

v |= __SHIFTIN(1, IOMUX_GPR13_SATA_SPEED); /* 3.0GHz */

sys/arch/arm/nxp/imx_ahcisata.c

424

v |= __SHIFTIN(sc->sc_ss, IOMUX_GPR13_SATA_PHY_5);

sys/arch/arm/nxp/imx_ahcisata.c

425

v |= __SHIFTIN(1, IOMUX_GPR13_SATA_PHY_1); /* PLL clock enable */

sys/arch/arm/nxp/imx_ahcisatareg.h

48

#define SATA_P0DMACR_RXTS(n) __SHIFTIN(n, __BITS(7, 4))

sys/arch/arm/nxp/imx_ahcisatareg.h

49

#define SATA_P0DMACR_TXTS(n) __SHIFTIN(n, __BITS(3, 0))

sys/arch/arm/nxp/imx_ahcisatareg.h

71

#define SATA_PHY_LANE0_TX_OVRD_TX_EN(n) __SHIFTIN(n, __BITS(3, 1))

sys/arch/arm/nxp/imx_ccm_composite.c

156

val |= __SHIFTIN(best_prediv - 1, TARGET_ROOT_PRE_PODF);

sys/arch/arm/nxp/imx_ccm_composite.c

158

val |= __SHIFTIN(best_postdiv - 1, TARGET_ROOT_POST_PODF);

sys/arch/arm/nxp/imx_ccm_composite.c

194

val |= __SHIFTIN(mux, TARGET_ROOT_MUX);

sys/arch/arm/nxp/imx_ccm_div.c

109

val |= __SHIFTIN(best_n, div->mask);

sys/arch/arm/nxp/imx_ccm_mux.c

71

val |= __SHIFTIN(sel, mux->sel);

sys/arch/arm/nxp/imxpcie.c

124

v |= __SHIFTIN(9, IOMUX_GPR12_LOS_LEVEL);

sys/arch/arm/nxp/imxpcie.c

128

v |= __SHIFTIN(0x7f, IOMUX_GPR8_PCS_TX_SWING_LOW);

sys/arch/arm/nxp/imxpcie.c

129

v |= __SHIFTIN(0x7f, IOMUX_GPR8_PCS_TX_SWING_FULL);

sys/arch/arm/nxp/imxpcie.c

130

v |= __SHIFTIN(20, IOMUX_GPR8_PCS_TX_DEEMPH_GEN2_6DB);

sys/arch/arm/nxp/imxpcie.c

131

v |= __SHIFTIN(20, IOMUX_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB);

sys/arch/arm/nxp/imxpcie.c

132

v |= __SHIFTIN(20, IOMUX_GPR8_PCS_TX_DEEMPH_GEN1);

sys/arch/arm/nxp/imxpcie.c

164

v = __SHIFTIN(addr, PCIE_PL_PHY_CTRL_DATA);

sys/arch/arm/nxp/imxpcie.c

173

v = __SHIFTIN(addr, PCIE_PL_PHY_CTRL_DATA);

sys/arch/arm/nxp/imxpcie.c

190

PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, __SHIFTIN(data, PCIE_PL_PHY_CTRL_DATA));

sys/arch/arm/nxp/imxpcie.c

193

PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, __SHIFTIN(data, PCIE_PL_PHY_CTRL_DATA) | PCIE_PL_PHY_CTRL_CAP_DAT);

sys/arch/arm/nxp/imxpcie.c

198

PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, __SHIFTIN(data, PCIE_PL_PHY_CTRL_DATA));

sys/arch/arm/nxp/imxpcie.c

208

PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, __SHIFTIN(data, PCIE_PL_PHY_CTRL_DATA));

sys/arch/arm/nxp/imxpcie.c

355

val |= __SHIFTIN(mult, MPLL_MULTIPLIER);

sys/arch/arm/nxp/imxpcie.c

361

val |= __SHIFTIN(div, REF_CLKDIV2);

sys/arch/arm/nxp/imxpcie.c

557

v |= __SHIFTIN(1, PCIE_PL_PLCR_LINK_MODE_ENABLE);

sys/arch/arm/nxp/imxpcie.c

562

v |= __SHIFTIN(1, PCIE_PL_G2CR_PREDETERMINED_NUMBER_OF_LANES);

sys/arch/arm/nxp/imxwdog.c

144

reg |= __SHIFTIN(sc->sc_wdog_period * 2 - 1, WCR_WT);

sys/arch/arm/nxp/imxwdog.c

204

reg |= __SHIFTIN(sc->sc_wdog_period * 2 - 1, WCR_WT);

sys/arch/arm/rockchip/rk3328_iomux.c

167

__SHIFTIN(GRF_GPIO_P_CTL_MASK, GRF_GPIO_P_WRITE_EN(idx)) |

sys/arch/arm/rockchip/rk3328_iomux.c

168

__SHIFTIN(bias, GRF_GPIO_P_CTL(idx)));

sys/arch/arm/rockchip/rk3328_iomux.c

175

__SHIFTIN(GRF_GPIO_E_CTL_MASK, GRF_GPIO_E_WRITE_EN(idx)) |

sys/arch/arm/rockchip/rk3328_iomux.c

176

__SHIFTIN(drv, GRF_GPIO_E_CTL(idx)));

sys/arch/arm/rockchip/rk3328_iomux.c

187

WR4(sc, reg, (mask << 16) | __SHIFTIN(mux, mask));

sys/arch/arm/rockchip/rk3399_cru.c

156

__SHIFTIN((_aclkm), RK3399_ACLKM_MASK), \

sys/arch/arm/rockchip/rk3399_cru.c

158

__SHIFTIN((_atclk), RK3399_ATCLK_MASK)|__SHIFTIN((_pdbg), RK3399_PDBG_MASK))

sys/arch/arm/rockchip/rk3399_cru.c

163

__SHIFTIN((_aclkm), RK3399_ACLKM_MASK), \

sys/arch/arm/rockchip/rk3399_cru.c

165

__SHIFTIN((_atclk), RK3399_ATCLK_MASK)|__SHIFTIN((_pdbg), RK3399_PDBG_MASK))

sys/arch/arm/rockchip/rk3399_cru.c

303

val = __SHIFTIN(PLL_WORK_MODE_SLOW, PLL_WORK_MODE) | (PLL_WORK_MODE << 16);

sys/arch/arm/rockchip/rk3399_cru.c

307

__SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) | (PLL_FBDIV << 16));

sys/arch/arm/rockchip/rk3399_cru.c

310

__SHIFTIN(pll_rate->postdiv2, PLL_POSTDIV2) |

sys/arch/arm/rockchip/rk3399_cru.c

311

__SHIFTIN(pll_rate->postdiv1, PLL_POSTDIV1) |

sys/arch/arm/rockchip/rk3399_cru.c

312

__SHIFTIN(pll_rate->refdiv, PLL_REFDIV) |

sys/arch/arm/rockchip/rk3399_cru.c

317

val |= __SHIFTIN(pll_rate->fracdiv, PLL_FRACDIV);

sys/arch/arm/rockchip/rk3399_cru.c

320

val = __SHIFTIN(pll_rate->dsmpd, PLL_DSMPD) | (PLL_DSMPD << 16);

sys/arch/arm/rockchip/rk3399_cru.c

334

val = __SHIFTIN(PLL_WORK_MODE_NORMAL, PLL_WORK_MODE) | (PLL_WORK_MODE << 16);

sys/arch/arm/rockchip/rk3399_iomux.c

244

const uint32_t bias_val = __SHIFTIN(bias, GRF_GPIO_P_CTL(idx));

sys/arch/arm/rockchip/rk3399_iomux.c

333

drv_val = __SHIFTIN(val, drv_mask);

sys/arch/arm/rockchip/rk3399_iomux.c

376

WR4(syscon, reg, (mask << 16) | __SHIFTIN(mux, mask));

sys/arch/arm/rockchip/rk3399_iomux.c

473

val |= __SHIFTIN(0x2, GRF_GPIO4B_IOMUX_TCK);

sys/arch/arm/rockchip/rk3399_iomux.c

474

val |= __SHIFTIN(0x2, GRF_GPIO4B_IOMUX_TMS);

sys/arch/arm/rockchip/rk3399_pcie.c

402

status &= ~__SHIFTIN(1, PCIE_LCAP_ASPM);

sys/arch/arm/rockchip/rk3399_pcie.c

42

#define SETREG(m, v) ((m)<<16|__SHIFTIN((v), (m)))

sys/arch/arm/rockchip/rk3399_pmucru.c

225

val = __SHIFTIN(PLL_WORK_MODE_SLOW, PLL_WORK_MODE) | (PLL_WORK_MODE << 16);

sys/arch/arm/rockchip/rk3399_pmucru.c

229

__SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) |

sys/arch/arm/rockchip/rk3399_pmucru.c

233

__SHIFTIN(pll_rate->postdiv2, PLL_POSTDIV2) |

sys/arch/arm/rockchip/rk3399_pmucru.c

234

__SHIFTIN(pll_rate->postdiv1, PLL_POSTDIV1) |

sys/arch/arm/rockchip/rk3399_pmucru.c

235

__SHIFTIN(pll_rate->refdiv, PLL_REFDIV) |

sys/arch/arm/rockchip/rk3399_pmucru.c

240

val |= __SHIFTIN(pll_rate->fracdiv, PLL_FRACDIV);

sys/arch/arm/rockchip/rk3399_pmucru.c

243

val = __SHIFTIN(pll_rate->dsmpd, PLL_DSMPD) | (PLL_DSMPD << 16);

sys/arch/arm/rockchip/rk3399_pmucru.c

261

val = __SHIFTIN(PLL_WORK_MODE_NORMAL, PLL_WORK_MODE) | (PLL_WORK_MODE << 16);

sys/arch/arm/rockchip/rk3588_cru.c

104

__SHIFTIN((aclkm) - 1, RK3588_ACLKM_DSU_DIV_MASK) | \

sys/arch/arm/rockchip/rk3588_cru.c

105

__SHIFTIN((aclkmp) - 1, RK3588_ACLKMP_DSU_DIV_MASK)|\

sys/arch/arm/rockchip/rk3588_cru.c

106

__SHIFTIN((aclks) - 1, RK3588_ACLKS_DSU_DIV_MASK) \

sys/arch/arm/rockchip/rk3588_cru.c

113

.val = __SHIFTIN((periph) - 1, RK3588_PERIPH_DSU_DIV_MASK)\

sys/arch/arm/rockchip/rk3588_cru.c

123

__SHIFTIN((gicclk) - 1, RK3588_GICCLK_DSU_DIV_MASK) |\

sys/arch/arm/rockchip/rk3588_cru.c

124

__SHIFTIN((atclk) - 1, RK3588_ATCLK_DSU_DIV_MASK) \

sys/arch/arm/rockchip/rk3588_cru.c

199

.val = __SHIFTIN((_apllcore), \

sys/arch/arm/rockchip/rk3588_cru.c

201

__SHIFTIN(0, \

sys/arch/arm/rockchip/rk3588_cru.c

207

.val = __SHIFTIN((_apllcore), \

sys/arch/arm/rockchip/rk3588_cru.c

80

.val = __SHIFTIN((apllcore), RK3588_CLK_CORE_L_SEL_MASK)\

sys/arch/arm/rockchip/rk3588_cru.c

91

__SHIFTIN((seldsu), RK3588_CLK_DSU_DF_SRC_MASK) | \

sys/arch/arm/rockchip/rk3588_cru.c

92

__SHIFTIN((divdsu) - 1, RK3588_CLK_DSU_DF_DIV_MASK) |\

sys/arch/arm/rockchip/rk3588_cru.c

93

__SHIFTIN(0, RK3588_CLK_DSU_SEL_DF_MASK) \

sys/arch/arm/rockchip/rk3588_iomux.c

874

val = (mask << 16) | __SHIFTIN(val, mask);

sys/arch/arm/rockchip/rk3588_iomux.c

895

uint32_t val = (mask << 16) | __SHIFTIN(drv, mask);

sys/arch/arm/rockchip/rk3588_iomux.c

914

val = (mask << 16) | __SHIFTIN(__BIT(3), mask);

sys/arch/arm/rockchip/rk3588_iomux.c

918

val = (mask << 16) | __SHIFTIN(mux, mask);

sys/arch/arm/rockchip/rk_cru_arm.c

107

const uint32_t write_val = __SHIFTIN(arm_rate->div - 1,

sys/arch/arm/rockchip/rk_cru_arm.c

172

write_val = __SHIFTIN(0, arm->divs[i].mask);

sys/arch/arm/rockchip/rk_cru_arm.c

223

const uint32_t write_val = __SHIFTIN(mux, arm->mux_mask);

sys/arch/arm/rockchip/rk_cru_composite.c

205

uint32_t write_val = __SHIFTIN(best_div - 1, composite->div_mask);

sys/arch/arm/rockchip/rk_cru_composite.c

208

write_val |= __SHIFTIN(best_mux, composite->mux_mask);

sys/arch/arm/rockchip/rk_cru_composite.c

250

const uint32_t write_val = __SHIFTIN(mux, composite->mux_mask);

sys/arch/arm/rockchip/rk_cru_mux.c

78

const uint32_t write_val = __SHIFTIN(index, mux->mask);

sys/arch/arm/rockchip/rk_cru_pll.c

189

__SHIFTIN(PLL_MODE_SLOW, pll->mode_mask));

sys/arch/arm/rockchip/rk_cru_pll.c

196

__SHIFTIN(1, RK3588_PLLCON1_PWRDOWN));

sys/arch/arm/rockchip/rk_cru_pll.c

201

__SHIFTIN(pll_rate->m, RK3588_PLLCON0_M));

sys/arch/arm/rockchip/rk_cru_pll.c

205

__SHIFTIN(pll_rate->p, RK3588_PLLCON1_P) |

sys/arch/arm/rockchip/rk_cru_pll.c

206

__SHIFTIN(pll_rate->s, RK3588_PLLCON1_S));

sys/arch/arm/rockchip/rk_cru_pll.c

209

__SHIFTIN(pll_rate->k, RK3588_PLLCON2_K));

sys/arch/arm/rockchip/rk_cru_pll.c

214

__SHIFTIN(0, RK3588_PLLCON1_PWRDOWN));

sys/arch/arm/rockchip/rk_cru_pll.c

232

__SHIFTIN(PLL_MODE_NORM, pll->mode_mask));

sys/arch/arm/rockchip/rk_cru_pll.c

236

__SHIFTIN(pll_rate->postdiv1, PLL_POSTDIV1) |

sys/arch/arm/rockchip/rk_cru_pll.c

237

__SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) |

sys/arch/arm/rockchip/rk_cru_pll.c

241

__SHIFTIN(pll_rate->dsmpd, PLL_DSMPD) |

sys/arch/arm/rockchip/rk_cru_pll.c

242

__SHIFTIN(pll_rate->postdiv2, PLL_POSTDIV2) |

sys/arch/arm/rockchip/rk_cru_pll.c

243

__SHIFTIN(pll_rate->refdiv, PLL_REFDIV) |

sys/arch/arm/rockchip/rk_cru_pll.c

248

val |= __SHIFTIN(pll_rate->fracdiv, PLL_FRACDIV);

sys/arch/arm/rockchip/rk_emmcphy.c

145

val = __SHIFTIN(0, PHYCTRL_DR_TY);

sys/arch/arm/rockchip/rk_emmcphy.c

150

val = PHYCTRL_OTAPDLYENA | __SHIFTIN(4, PHYCTRL_OTAPDLYSEL);

sys/arch/arm/rockchip/rk_emmcphy.c

197

val = __SHIFTIN(frqsel, PHYCTRL_FRQSEL);

sys/arch/arm/rockchip/rk_eqos.c

132

__SHIFTIN(txen, RK3588_GMAC_TXCLK_DELAY_EN(id)) | /* values */

sys/arch/arm/rockchip/rk_eqos.c

133

__SHIFTIN(rxen, RK3588_GMAC_RXCLK_DELAY_EN(id)));

sys/arch/arm/rockchip/rk_eqos.c

137

__SHIFTIN(tx_delay, RK3588_GMAC_TXCLK_DELAY_CFG) | /* values */

sys/arch/arm/rockchip/rk_eqos.c

138

__SHIFTIN(rx_delay, RK3588_GMAC_RXCLK_DELAY_CFG));

sys/arch/arm/rockchip/rk_eqos.c

144

__SHIFTIN(RK3588_GMAC_PHY_IFACE_SEL_RGMII, /* value */

sys/arch/arm/rockchip/rk_eqos.c

148

__SHIFTIN(RK3588_GMAC_CLK_MODE_RGMII, /* value */

sys/arch/arm/rockchip/rk_eqos.c

175

__SHIFTIN(clksel, RK3588_GMAC_CLK_RGMII_DIV(id))); /* value */

sys/arch/arm/rockchip/rk_eqos.c

205

__SHIFTIN(clksel, RK3588_GMAC_CLK_SELECT(id)) |

sys/arch/arm/rockchip/rk_eqos.c

206

__SHIFTIN(gate, RK3588_GMAC_CLK_RMII_GATE_EN(id)));

sys/arch/arm/rockchip/rk_gmac.c

113

write_val = __SHIFTIN(RK3288_GRF_SOC_CON1_GMAC_PHY_INTF_SEL_RGMII,

sys/arch/arm/rockchip/rk_gmac.c

126

__SHIFTIN(tx_delay,

sys/arch/arm/rockchip/rk_gmac.c

131

__SHIFTIN(rx_delay,

sys/arch/arm/rockchip/rk_gmac.c

196

write_val = __SHIFTIN(RK3328_GRF_MAC_CON1_SEL_RGMII,

sys/arch/arm/rockchip/rk_gmac.c

206

__SHIFTIN(tx_delay, RK3328_GRF_MAC_CON0_TXDLY) |

sys/arch/arm/rockchip/rk_gmac.c

207

__SHIFTIN(rx_delay, RK3328_GRF_MAC_CON0_RXDLY);

sys/arch/arm/rockchip/rk_gmac.c

247

__SHIFTIN(RK3328_GRF_MAC_CON1_CLKSEL_125M, RK3328_GRF_MAC_CON1_CLKSEL));

sys/arch/arm/rockchip/rk_gmac.c

283

write_val = __SHIFTIN(1, RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL);

sys/arch/arm/rockchip/rk_gmac.c

295

__SHIFTIN(rx_delay, RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG) |

sys/arch/arm/rockchip/rk_gmac.c

296

__SHIFTIN(tx_delay, RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG);

sys/arch/arm/rockchip/rk_gmac.c

324

__SHIFTIN(clksel, RK3399_GRF_SOC_CON5_GMAC_CLK_SEL);

sys/arch/arm/rockchip/rk_gpio.c

372

val |= __SHIFTIN(mode, SUNXI_GPIO_INT_MODEMASK(eint->eint_num));

sys/arch/arm/rockchip/rk_i2c.c

155

__SHIFTIN(divh, RKI2C_CLKDIV_CLKDIVH) |

sys/arch/arm/rockchip/rk_i2c.c

156

__SHIFTIN(divl, RKI2C_CLKDIV_CLKDIVL));

sys/arch/arm/rockchip/rk_i2c.c

248

con = RKI2C_CON_I2C_EN | __SHIFTIN(mode, RKI2C_CON_I2C_MODE);

sys/arch/arm/rockchip/rk_i2c.c

264

WR4(sc, RKI2C_MTXCNT, __SHIFTIN(len + 1, RKI2C_MTXCNT_MTXCNT));

sys/arch/arm/rockchip/rk_i2c.c

288

con = RKI2C_CON_I2C_EN | __SHIFTIN(mode, RKI2C_CON_I2C_MODE);

sys/arch/arm/rockchip/rk_i2c.c

295

mrxaddr = __SHIFTIN((addr << 1) | 1, RKI2C_MRXADDR_SADDR) |

sys/arch/arm/rockchip/rk_i2c.c

311

WR4(sc, RKI2C_MRXCNT, __SHIFTIN(buflen, RKI2C_MRXCNT_MRXCNT));

sys/arch/arm/rockchip/rk_i2s.c

193

ckr |= __SHIFTIN(bclk_div - 1, CKR_MDIV);

sys/arch/arm/rockchip/rk_i2s.c

195

ckr |= __SHIFTIN(lrck_div - 1, CKR_TSD);

sys/arch/arm/rockchip/rk_i2s.c

197

ckr |= __SHIFTIN(lrck_div - 1, CKR_RSD);

sys/arch/arm/rockchip/rk_i2s.c

201

ckr |= __SHIFTIN(0, CKR_TRCM);

sys/arch/arm/rockchip/rk_i2s.c

209

txcr |= __SHIFTIN(play->validbits - 1, TXCR_VDW);

sys/arch/arm/rockchip/rk_i2s.c

211

txcr |= __SHIFTIN(play->channels / 2 - 1, TXCR_TCSR);

sys/arch/arm/rockchip/rk_i2s.c

220

rxcr |= __SHIFTIN(rec->validbits - 1, RXCR_VDW);

sys/arch/arm/rockchip/rk_i2s.c

222

rxcr |= __SHIFTIN(rec->channels / 2 - 1, RXCR_RCSR);

sys/arch/arm/rockchip/rk_i2s.c

268

val |= __SHIFTIN(RK_I2S_FIFO_DEPTH / 2, INTCR_TFT);

sys/arch/arm/rockchip/rk_i2s.c

452

txcr |= __SHIFTIN(0, TXCR_IBM);

sys/arch/arm/rockchip/rk_i2s.c

453

rxcr |= __SHIFTIN(0, RXCR_IBM);

sys/arch/arm/rockchip/rk_i2s.c

456

txcr |= __SHIFTIN(1, TXCR_IBM);

sys/arch/arm/rockchip/rk_i2s.c

457

rxcr |= __SHIFTIN(1, RXCR_IBM);

sys/arch/arm/rockchip/rk_i2s.c

460

txcr |= __SHIFTIN(2, TXCR_IBM);

sys/arch/arm/rockchip/rk_i2s.c

461

rxcr |= __SHIFTIN(2, RXCR_IBM);

sys/arch/arm/rockchip/rk_i2s.c

464

txcr |= __SHIFTIN(0, TXCR_PBM);

sys/arch/arm/rockchip/rk_i2s.c

466

rxcr |= __SHIFTIN(0, RXCR_PBM);

sys/arch/arm/rockchip/rk_i2s.c

470

txcr |= __SHIFTIN(1, TXCR_PBM);

sys/arch/arm/rockchip/rk_i2s.c

472

rxcr |= __SHIFTIN(1, RXCR_PBM);

sys/arch/arm/rockchip/rk_i2s.c

597

val = __SHIFTIN(sc->sc_conf->oe_val, sc->sc_conf->oe_mask);

sys/arch/arm/rockchip/rk_pwm.c

180

ctrl |= __SHIFTIN(CTRL_PWM_MODE_CONTINUOUS, CTRL_PWM_MODE);

sys/arch/arm/rockchip/rk_spi.c

275

ctrlr0 = SPI_CTRLR0_BHT | __SHIFTIN(SPI_CTRLR0_DFS_8BIT, SPI_CTRLR0_DFS);

sys/arch/arm/rockchip/rk_v1crypto.c

191

ctrl |= __SHIFTIN(100, RK_V1CRYPTO_TRNG_CTRL_CYCLES);

sys/arch/arm/rockchip/rk_v1crypto.c

224

ctrl |= __SHIFTIN(RK_V1CRYPTO_AES_CTRL_MODE_ECB,

sys/arch/arm/rockchip/rk_v1crypto.c

226

ctrl |= __SHIFTIN(RK_V1CRYPTO_AES_CTRL_KEYSIZE_128,

sys/arch/arm/rockchip/rk_v1crypto.c

228

ctrl |= __SHIFTIN(RK_V1CRYPTO_AES_CTRL_DIR_ENC,

sys/arch/arm/rockchip/rk_v1crypto.c

93

c |= __SHIFTIN(m, RK_V1CRYPTO_CTRL_MASK);

sys/arch/arm/rockchip/rk_v1crypto.c

94

c |= __SHIFTIN(v, m);

sys/arch/arm/rockchip/rk_vop.c

247

val |= __SHIFTIN(pol, mask);

sys/arch/arm/rockchip/rk_vop.c

323

val = __SHIFTIN(act_width - 1, WIN0_ACT_WIDTH) |

sys/arch/arm/rockchip/rk_vop.c

324

__SHIFTIN(act_height - 1, WIN0_ACT_HEIGHT);

sys/arch/arm/rockchip/rk_vop.c

329

val = __SHIFTIN(dsp_width - 1, WIN0_DSP_WIDTH) |

sys/arch/arm/rockchip/rk_vop.c

330

__SHIFTIN(dsp_height - 1, WIN0_DSP_HEIGHT);

sys/arch/arm/rockchip/rk_vop.c

337

val = __SHIFTIN(dst->x1 + htotal - hsync_start, WIN0_DSP_XST) |

sys/arch/arm/rockchip/rk_vop.c

338

__SHIFTIN(dst->y1 + vtotal - vsync_start, WIN0_DSP_YST);

sys/arch/arm/rockchip/rk_vop.c

351

val = __SHIFTIN(lb_mode, WIN0_LB_MODE) |

sys/arch/arm/rockchip/rk_vop.c

352

__SHIFTIN(WIN0_DATA_FMT_ARGB888, WIN0_DATA_FMT) |

sys/arch/arm/rockchip/rk_vop.c

373

val = __SHIFTIN(sfb->base.pitches[0] / 4, WIN0_VIR_STRIDE);

sys/arch/arm/rockchip/rk_vop.c

523

val |= __SHIFTIN(sc->sc_conf->out_mode, DSP_OUT_MODE);

sys/arch/arm/rockchip/rk_vop.c

526

val = __SHIFTIN(hsync_len + hback_porch, DSP_HACT_ST_POST) |

sys/arch/arm/rockchip/rk_vop.c

527

__SHIFTIN(hsync_len + hback_porch + hactive, DSP_HACT_END_POST);

sys/arch/arm/rockchip/rk_vop.c

530

val = __SHIFTIN(hsync_len + hback_porch, DSP_HACT_ST) |

sys/arch/arm/rockchip/rk_vop.c

531

__SHIFTIN(hsync_len + hback_porch + hactive, DSP_HACT_END);

sys/arch/arm/rockchip/rk_vop.c

534

val = __SHIFTIN(hsync_len, DSP_HTOTAL) |

sys/arch/arm/rockchip/rk_vop.c

535

__SHIFTIN(hsync_len + hback_porch + hactive + hfront_porch, DSP_HS_END);

sys/arch/arm/rockchip/rk_vop.c

538

val = __SHIFTIN(vsync_len + vback_porch, DSP_VACT_ST_POST) |

sys/arch/arm/rockchip/rk_vop.c

539

__SHIFTIN(vsync_len + vback_porch + vactive, DSP_VACT_END_POST);

sys/arch/arm/rockchip/rk_vop.c

542

val = __SHIFTIN(vsync_len + vback_porch, DSP_VACT_ST) |

sys/arch/arm/rockchip/rk_vop.c

543

__SHIFTIN(vsync_len + vback_porch + vactive, DSP_VACT_END);

sys/arch/arm/rockchip/rk_vop.c

546

val = __SHIFTIN(vsync_len, DSP_VTOTAL) |

sys/arch/arm/rockchip/rk_vop.c

547

__SHIFTIN(vsync_len + vback_porch + vactive + vfront_porch, DSP_VS_END);

sys/arch/arm/samsung/exynos5410_clock.c

709

__SHIFTIN(pll_rate->pll_m, PLL2650X_CON0_M) |

sys/arch/arm/samsung/exynos5410_clock.c

710

__SHIFTIN(pll_rate->pll_p, PLL2650X_CON0_P) |

sys/arch/arm/samsung/exynos5410_clock.c

711

__SHIFTIN(pll_rate->pll_s, PLL2650X_CON0_S);

sys/arch/arm/samsung/exynos5410_clock.c

714

__SHIFTIN(pll_rate->pll_k, PLL2650X_CON1_K);

sys/arch/arm/samsung/exynos5410_clock.c

755

v |= __SHIFTIN(sel, emux->bits);

sys/arch/arm/samsung/exynos5410_clock.c

821

v |= __SHIFTIN(new_div, ediv->bits);

sys/arch/arm/samsung/exynos5422_clock.c

802

v |= __SHIFTIN(sel, emux->bits);

sys/arch/arm/samsung/exynos5422_clock.c

868

v |= __SHIFTIN(new_div, ediv->bits);

sys/arch/arm/samsung/exynos5_reg.h

435

#define OTG_SYS_REFCLKSEL_XTAL __SHIFTIN(OTG_SYS_REFCLKSEL_MASK, 0)

sys/arch/arm/samsung/exynos5_reg.h

436

#define OTG_SYS_REFCLKSEL_EXTL __SHIFTIN(OTG_SYS_REFCLKSEL_MASK, 1)

sys/arch/arm/samsung/exynos5_reg.h

437

#define OTG_SYS_REFCLKSEL_CLKCORE __SHIFTIN(OTG_SYS_REFCLKSEL_MASK, 2)

sys/arch/arm/samsung/exynos_combiner.c

279

iesr |= __SHIFTIN((1 << intr), COMBINER_GROUP_MASK(group));

sys/arch/arm/samsung/exynos_reg.h

157

#define WTCON_CLOCK_SELECT_16 __SHIFTIN(0, WTCON_CLOCK_SELECT)

sys/arch/arm/samsung/exynos_reg.h

158

#define WTCON_CLOCK_SELECT_32 __SHIFTIN(1, WTCON_CLOCK_SELECT)

sys/arch/arm/samsung/exynos_reg.h

159

#define WTCON_CLOCK_SELECT_64 __SHIFTIN(2, WTCON_CLOCK_SELECT)

sys/arch/arm/samsung/exynos_reg.h

160

#define WTCON_CLOCK_SELECT_128 __SHIFTIN(3, WTCON_CLOCK_SELECT)

sys/arch/arm/samsung/exynos_soc.c

327

regval = __SHIFTIN(M, PLL35XX_CON0_M) |

sys/arch/arm/samsung/exynos_soc.c

328

__SHIFTIN(P, PLL35XX_CON0_P) |

sys/arch/arm/samsung/exynos_soc.c

329

__SHIFTIN(S, PLL35XX_CON0_S);

sys/arch/arm/samsung/exynos_soc.c

782

phyhost |= __SHIFTIN(FSEL_CLKSEL_24M, HOST_CTRL0_FSEL_MASK);

sys/arch/arm/samsung/exynos_soc.c

806

__SHIFTIN(HSIC_CTRL_REFCLKDIV_12, HSIC_CTRL_REFCLKDIV_MASK) |

sys/arch/arm/samsung/exynos_soc.c

807

__SHIFTIN(HSIC_CTRL_REFCLKSEL_DEFAULT, HSIC_CTRL_REFCLKSEL_MASK) |

sys/arch/arm/samsung/exynos_soc.c

830

phyotg |= __SHIFTIN(OTG_SYS_FSEL_MASK, FSEL_CLKSEL_24M);

sys/arch/arm/samsung/exynos_uart.c

278

__SHIFTIN(2, UFCON_TXTRIGGER) |

sys/arch/arm/samsung/exynos_uart.c

279

__SHIFTIN(1, UFCON_RXTRIGGER) |

sys/arch/arm/samsung/exynos_uart.c

290

WR4(sc, SSCOM_UCON, ucon | __SHIFTIN(3, UCON_RXTO));

sys/arch/arm/samsung/exynos_usbdrdphy.c

181

val |= __SHIFTIN(9, PHY_PARAM0_REF_LOSLEVEL);

sys/arch/arm/samsung/exynos_usbdrdphy.c

189

val |= __SHIFTIN(0x20, PHY_LINK_SYSTEM_FLADJ);

sys/arch/arm/samsung/exynos_usbdrdphy.c

194

val |= __SHIFTIN(0x1c, PHY_PARAM1_TXDEEMPH);

sys/arch/arm/samsung/exynos_usbdrdphy.c

208

val = __SHIFTIN(PHY_CLK_RST_REFCLKSEL_EXT, PHY_CLK_RST_REFCLKSEL);

sys/arch/arm/samsung/exynos_usbdrdphy.c

209

val |= __SHIFTIN(PHY_CLK_RST_FSEL_24M, PHY_CLK_RST_FSEL);

sys/arch/arm/samsung/exynos_usbdrdphy.c

210

val |= __SHIFTIN(PHY_CLK_RST_MPLL_MULT_24M, PHY_CLK_RST_MPLL_MULT);

sys/arch/arm/samsung/exynos_usbdrdphy.c

211

val |= __SHIFTIN(0x88, PHY_CLK_RST_SSC_REFCLKSEL);

sys/arch/arm/samsung/exynos_usbphy.c

171

val |= __SHIFTIN(FSEL_CLKSEL_24M, HOST_CTRL0_FSEL_MASK);

sys/arch/arm/samsung/exynos_usbphy.c

194

val |= __SHIFTIN(HSIC_CTRL_REFCLKDIV_12, HSIC_CTRL_REFCLKDIV_MASK);

sys/arch/arm/samsung/exynos_usbphy.c

195

val |= __SHIFTIN(HSIC_CTRL_REFCLKSEL_DEFAULT, HSIC_CTRL_REFCLKSEL_MASK);

sys/arch/arm/samsung/exynos_wdt.c

138

| __SHIFTIN(sc->sc_wdog_clock_select, WTCON_CLOCK_SELECT)

sys/arch/arm/samsung/exynos_wdt.c

139

| __SHIFTIN(sc->sc_wdog_prescaler - 1, WTCON_PRESCALER);

sys/arch/arm/samsung/exynos_wdt.c

162

| __SHIFTIN(sc->sc_wdog_clock_select, WTCON_CLOCK_SELECT)

sys/arch/arm/samsung/exynos_wdt.c

163

| __SHIFTIN(sc->sc_wdog_prescaler - 1, WTCON_PRESCALER);

sys/arch/arm/samsung/sscom_reg.h

46

#define ULCON_PARITY_NONE __SHIFTIN(0, ULCON_PARITY)

sys/arch/arm/samsung/sscom_reg.h

47

#define ULCON_PARITY_ODD __SHIFTIN(4, ULCON_PARITY)

sys/arch/arm/samsung/sscom_reg.h

48

#define ULCON_PARITY_EVEN __SHIFTIN(5, ULCON_PARITY)

sys/arch/arm/samsung/sscom_reg.h

49

#define ULCON_PARITY_ONE __SHIFTIN(6, ULCON_PARITY)

sys/arch/arm/samsung/sscom_reg.h

50

#define ULCON_PARITY_ZERO __SHIFTIN(7, ULCON_PARITY)

sys/arch/arm/samsung/sscom_reg.h

59

#define UCON_TXDMA_BRST_1 __SHIFTIN(0, UCON_TXDMA)

sys/arch/arm/samsung/sscom_reg.h

60

#define UCON_TXDMA_BRST_4 __SHIFTIN(1, UCON_TXDMA)

sys/arch/arm/samsung/sscom_reg.h

61

#define UCON_TXDMA_BRST_8 __SHIFTIN(2, UCON_TXDMA)

sys/arch/arm/samsung/sscom_reg.h

62

#define UCON_TXDMA_BRST_16 __SHIFTIN(3, UCON_TXDMA)

sys/arch/arm/samsung/sscom_reg.h

64

#define UCON_RXDMA_BRST_1 __SHIFTIN(0, UCON_RXDMA)

sys/arch/arm/samsung/sscom_reg.h

65

#define UCON_RXDMA_BRST_4 __SHIFTIN(1, UCON_RXDMA)

sys/arch/arm/samsung/sscom_reg.h

66

#define UCON_RXDMA_BRST_8 __SHIFTIN(2, UCON_RXDMA)

sys/arch/arm/samsung/sscom_reg.h

67

#define UCON_RXDMA_BRST_16 __SHIFTIN(3, UCON_RXDMA)

sys/arch/arm/samsung/sscom_reg.h

79

#define UCON_RXINT_TYPE_PULSE __SHIFTIN(0,UCON_RXINT_TYPE)

sys/arch/arm/samsung/sscom_reg.h

85

#define UCON_TXMODE_DISABLE __SHIFTIN(0, UCON_TXMODE)

sys/arch/arm/samsung/sscom_reg.h

86

#define UCON_TXMODE_INT __SHIFTIN(1, UCON_TXMODE)

sys/arch/arm/samsung/sscom_reg.h

87

#define UCON_TXMODE_DMA __SHIFTIN(2, UCON_TXMODE)

sys/arch/arm/samsung/sscom_reg.h

88

#define UCON_TXMODE_MASK __SHIFTIN(3, UCON_TXMODE)

sys/arch/arm/samsung/sscom_reg.h

90

#define UCON_RXMODE_DISABLE __SHIFTIN(1, UCON_RXMODE)

sys/arch/arm/samsung/sscom_reg.h

91

#define UCON_RXMODE_INT __SHIFTIN(1, UCON_RXMODE)

sys/arch/arm/samsung/sscom_reg.h

92

#define UCON_RXMODE_DMA __SHIFTIN(2, UCON_RXMODE)

sys/arch/arm/samsung/sscom_reg.h

93

#define UCON_RXMODE_MASK __SHIFTIN(3, UCON_RXMODE)

sys/arch/arm/sunxi/sun4i_a10_codec.c

126

SET4(sc, A10_DAC_ACTRL, __SHIFTIN(A10_DEFAULT_PAVOL, A10_PAVOL));

sys/arch/arm/sunxi/sun4i_a10_codec.c

164

val |= __SHIFTIN(nvol, mix->mask);

sys/arch/arm/sunxi/sun4i_dma.c

205

mem_cfg = __SHIFTIN(mem_width, NDMA_CTRL_SRC_DATA_WIDTH) |

sys/arch/arm/sunxi/sun4i_dma.c

206

__SHIFTIN(mem_burst, NDMA_CTRL_SRC_BST_LEN) |

sys/arch/arm/sunxi/sun4i_dma.c

207

__SHIFTIN(DRQ_TYPE_SDRAM, NDMA_CTRL_SRC_DRQ_TYPE);

sys/arch/arm/sunxi/sun4i_dma.c

208

dev_cfg = __SHIFTIN(dev_width, NDMA_CTRL_SRC_DATA_WIDTH) |

sys/arch/arm/sunxi/sun4i_dma.c

209

__SHIFTIN(dev_burst, NDMA_CTRL_SRC_BST_LEN) |

sys/arch/arm/sunxi/sun4i_dma.c

210

__SHIFTIN(ch->ch_drq, NDMA_CTRL_SRC_DRQ_TYPE) |

sys/arch/arm/sunxi/sun4i_dma.c

245

mem_cfg = __SHIFTIN(mem_width, DDMA_CTRL_SRC_DATA_WIDTH) |

sys/arch/arm/sunxi/sun4i_dma.c

246

__SHIFTIN(mem_burst, DDMA_CTRL_SRC_BST_LEN) |

sys/arch/arm/sunxi/sun4i_dma.c

247

__SHIFTIN(DRQ_TYPE_SDRAM, DDMA_CTRL_SRC_DRQ_TYPE) |

sys/arch/arm/sunxi/sun4i_dma.c

248

__SHIFTIN(0, DDMA_CTRL_SRC_ADDR_MODE);

sys/arch/arm/sunxi/sun4i_dma.c

249

dev_cfg = __SHIFTIN(dev_width, DDMA_CTRL_SRC_DATA_WIDTH) |

sys/arch/arm/sunxi/sun4i_dma.c

250

__SHIFTIN(dev_burst, DDMA_CTRL_SRC_BST_LEN) |

sys/arch/arm/sunxi/sun4i_dma.c

251

__SHIFTIN(ch->ch_drq, DDMA_CTRL_SRC_DRQ_TYPE) |

sys/arch/arm/sunxi/sun4i_dma.c

252

__SHIFTIN(1, DDMA_CTRL_SRC_ADDR_MODE);

sys/arch/arm/sunxi/sun4i_dma.c

94

(__SHIFTIN(1, DDMA_PARA_DST_DATA_BLK_SIZE) | \

sys/arch/arm/sunxi/sun4i_dma.c

95

__SHIFTIN(1, DDMA_PARA_SRC_DATA_BLK_SIZE) | \

sys/arch/arm/sunxi/sun4i_dma.c

96

__SHIFTIN(2, DDMA_PARA_DST_WAIT_CLK_CYC) | \

sys/arch/arm/sunxi/sun4i_dma.c

97

__SHIFTIN(2, DDMA_PARA_SRC_WAIT_CLK_CYC))

sys/arch/arm/sunxi/sun4i_emac.c

769

EMAC_MAC_MCFG_CLK, __SHIFTIN(0xd, EMAC_MAC_MCFG_CLK));

sys/arch/arm/sunxi/sun4i_emac.c

795

__SHIFTIN(0x0c, EMAC_MAC_IPGR_IPG1) |

sys/arch/arm/sunxi/sun4i_emac.c

796

__SHIFTIN(0x12, EMAC_MAC_IPGR_IPG2));

sys/arch/arm/sunxi/sun4i_emac.c

799

__SHIFTIN(0x0f, EMAC_MAC_CLRT_RM) |

sys/arch/arm/sunxi/sun4i_emac.c

800

__SHIFTIN(0x37, EMAC_MAC_CLRT_CW));

sys/arch/arm/sunxi/sun4i_spi.c

200

cctl = __SHIFTIN(cctl, SPI_CCTL_CDR1);

sys/arch/arm/sunxi/sun4i_spi.c

203

cctl = SPI_CCTL_DRS|__SHIFTIN(cctl, SPI_CCTL_CDR2);

sys/arch/arm/sunxi/sun4i_spi.c

356

SPIREG_WRITE(sc, SPI_BC, __SHIFTIN(burstcount, SPI_BC_BC));

sys/arch/arm/sunxi/sun4i_spi.c

357

SPIREG_WRITE(sc, SPI_TC, __SHIFTIN(burstcount, SPI_TC_WTC));

sys/arch/arm/sunxi/sun4i_spi.c

363

ctl = sc->sc_CTL | __SHIFTIN(st->st_slave, SPI_CTL_SS) | SPI_CTL_XCH;

sys/arch/arm/sunxi/sun50i_a64_acodec.c

176

val |= __SHIFTIN(addr, A64_AC_PR_ADDR);

sys/arch/arm/sunxi/sun50i_a64_acodec.c

197

val |= __SHIFTIN(addr, A64_AC_PR_ADDR);

sys/arch/arm/sunxi/sun50i_a64_acodec.c

202

val |= __SHIFTIN(data, A64_ACDA_PR_WDAT);

sys/arch/arm/sunxi/sun50i_a64_acodec.c

300

val |= __SHIFTIN(nvol, mix->mask);

sys/arch/arm/sunxi/sun6i_a31_codec.c

175

SET4(sc, OMIXER_DACA_CTRL, __SHIFTIN(A31_DEFAULT_HPVOL, HPVOL));

sys/arch/arm/sunxi/sun6i_a31_codec.c

225

val |= __SHIFTIN(nvol, mix->mask);

sys/arch/arm/sunxi/sun6i_dma.c

335

mem_cfg = __SHIFTIN(mem_width, DMA_CFG_SRC_DATA_WIDTH) |

sys/arch/arm/sunxi/sun6i_dma.c

336

__SHIFTIN(mem_burst, sc->sc_burst_mask) |

sys/arch/arm/sunxi/sun6i_dma.c

337

__SHIFTIN(DMA_CFG_ADDR_MODE_LINEAR, DMA_CFG_SRC_ADDR_MODE) |

sys/arch/arm/sunxi/sun6i_dma.c

338

__SHIFTIN(DMA_CFG_DRQ_TYPE_SDRAM, DMA_CFG_SRC_DRQ_TYPE);

sys/arch/arm/sunxi/sun6i_dma.c

339

dev_cfg = __SHIFTIN(dev_width, DMA_CFG_SRC_DATA_WIDTH) |

sys/arch/arm/sunxi/sun6i_dma.c

340

__SHIFTIN(dev_burst, sc->sc_burst_mask) |

sys/arch/arm/sunxi/sun6i_dma.c

341

__SHIFTIN(DMA_CFG_ADDR_MODE_IO, DMA_CFG_SRC_ADDR_MODE) |

sys/arch/arm/sunxi/sun6i_dma.c

342

__SHIFTIN(ch->ch_portid, DMA_CFG_SRC_DRQ_TYPE);

sys/arch/arm/sunxi/sun6i_dma.c

85

#define DMA_MODE_DST(m) __SHIFTIN((m), __BIT(3))

sys/arch/arm/sunxi/sun6i_dma.c

86

#define DMA_MODE_SRC(m) __SHIFTIN((m), __BIT(2))

sys/arch/arm/sunxi/sun6i_spi.c

234

cctl = __SHIFTIN(cctl, SPI_CCTL_CDR1);

sys/arch/arm/sunxi/sun6i_spi.c

237

cctl = SPI_CCTL_DRS|__SHIFTIN(cctl, SPI_CCTL_CDR2);

sys/arch/arm/sunxi/sun6i_spi.c

292

SPIREG_WRITE(sc, SPI_BC, __SHIFTIN(burstcount, SPI_BC_MBC));

sys/arch/arm/sunxi/sun6i_spi.c

293

SPIREG_WRITE(sc, SPI_TC, __SHIFTIN(burstcount, SPI_TC_MWTC));

sys/arch/arm/sunxi/sun6i_spi.c

294

SPIREG_WRITE(sc, SPI_BCC, __SHIFTIN(burstcount, SPI_BCC_STC));

sys/arch/arm/sunxi/sun6i_spi.c

297

tcr = sc->sc_TCR | __SHIFTIN(st->st_slave, SPI_TCR_SS_SEL);

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

157

val |= __SHIFTIN(n, PLL_CxCPUX_CTRL_PLL_FACTOR_N);

sys/arch/arm/sunxi/sun8i_codec.c

223

val |= __SHIFTIN(AIF1_DATA_FMT_I2S, AIF1_DATA_FMT);

sys/arch/arm/sunxi/sun8i_codec.c

226

val |= __SHIFTIN(AIF1_DATA_FMT_RJ, AIF1_DATA_FMT);

sys/arch/arm/sunxi/sun8i_codec.c

229

val |= __SHIFTIN(AIF1_DATA_FMT_LJ, AIF1_DATA_FMT);

sys/arch/arm/sunxi/sun8i_codec.c

233

val |= __SHIFTIN(AIF1_DATA_FMT_DSP, AIF1_DATA_FMT);

sys/arch/arm/sunxi/sun8i_codec.c

258

val |= __SHIFTIN(AIF1_LRCK_DIV_64, AIF1_LRCK_DIV);

sys/arch/arm/sunxi/sun8i_codec.c

261

val |= __SHIFTIN(AIF1_BCLK_DIV_16, AIF1_BCLK_DIV);

sys/arch/arm/sunxi/sun8i_codec.c

424

val |= __SHIFTIN(AIF1CLK_SRC_PLL, AIF1CLK_SRC);

sys/arch/arm/sunxi/sun8i_codec.c

438

val |= __SHIFTIN(AIF_FS_48KHZ, AIF1_FS);

sys/arch/arm/sunxi/sun8i_codec.c

444

val |= __SHIFTIN(AIF1_WORD_SIZ_16, AIF1_WORD_SIZ);

sys/arch/arm/sunxi/sun8i_codec.c

456

val |= __SHIFTIN(DACL_MXR_SRC_AIF1_DAC0L, DACL_MXR_SRC);

sys/arch/arm/sunxi/sun8i_codec.c

458

val |= __SHIFTIN(DACR_MXR_SRC_AIF1_DAC0R, DACR_MXR_SRC);

sys/arch/arm/sunxi/sun8i_codec.c

468

val |= __SHIFTIN(0xff, HMIC_CTRL1_N);

sys/arch/arm/sunxi/sun8i_codec.c

473

val |= __SHIFTIN(0x17, HMIC_CTRL2_MDATA_THRES);

sys/arch/arm/sunxi/sun8i_crypto.c

1217

icr &= ~__SHIFTIN(SUN8I_CRYPTO_ICR_INTR_EN_CHAN(i),

sys/arch/arm/sunxi/sun8i_crypto.c

2323

tdqc |= __SHIFTIN(dir, SUN8I_CRYPTO_TDQC_OP_DIR);

sys/arch/arm/sunxi/sun8i_crypto.c

2376

tdqc |= __SHIFTIN(method, SUN8I_CRYPTO_TDQC_METHOD);

sys/arch/arm/sunxi/sun8i_crypto.c

2379

tdqs |= __SHIFTIN(SUN8I_CRYPTO_TDQS_SKEY_SELECT_SS_KEYx,

sys/arch/arm/sunxi/sun8i_crypto.c

2417

tdqs |= __SHIFTIN(mode, SUN8I_CRYPTO_TDQS_OP_MODE);

sys/arch/arm/sunxi/sun8i_crypto.c

2425

tdqs |= __SHIFTIN(ctrwidth, SUN8I_CRYPTO_TDQS_CTR_WIDTH);

sys/arch/arm/sunxi/sun8i_crypto.c

2483

tdqs |= __SHIFTIN(aeskeysize, SUN8I_CRYPTO_TDQS_AES_KEYSIZE);

sys/arch/arm/sunxi/sun8i_crypto.c

826

tdqc |= __SHIFTIN(SUN8I_CRYPTO_TDQC_METHOD_TRNG,

sys/arch/arm/sunxi/sun8i_crypto.c

847

tdqc |= __SHIFTIN(SUN8I_CRYPTO_TDQC_METHOD_AES,

sys/arch/arm/sunxi/sun8i_crypto.c

849

tdqc |= __SHIFTIN(dir, SUN8I_CRYPTO_TDQC_OP_DIR);

sys/arch/arm/sunxi/sun8i_crypto.c

866

tdqs |= __SHIFTIN(SUN8I_CRYPTO_TDQS_SKEY_SELECT_SS_KEYx,

sys/arch/arm/sunxi/sun8i_crypto.c

868

tdqs |= __SHIFTIN(SUN8I_CRYPTO_TDQS_OP_MODE_ECB,

sys/arch/arm/sunxi/sun8i_crypto.c

870

tdqs |= __SHIFTIN(keysize, SUN8I_CRYPTO_TDQS_AES_KEYSIZE);

sys/arch/arm/sunxi/sun8i_crypto.c

931

icr |= __SHIFTIN(SUN8I_CRYPTO_ICR_INTR_EN_CHAN(i),

sys/arch/arm/sunxi/sun8i_h3_ccu.c

514

val |= __SHIFTIN(AHB2_CLK_CFG_PLL_PERIPH0_2, AHB2_CLK_CFG);

sys/arch/arm/sunxi/sun8i_h3_codec.c

165

val |= __SHIFTIN(addr, H3_AC_PR_ADDR);

sys/arch/arm/sunxi/sun8i_h3_codec.c

186

val |= __SHIFTIN(addr, H3_AC_PR_ADDR);

sys/arch/arm/sunxi/sun8i_h3_codec.c

191

val |= __SHIFTIN(data, H3_ACDA_PR_WDAT);

sys/arch/arm/sunxi/sun8i_h3_codec.c

300

val |= __SHIFTIN(nvol, mix->mask);

sys/arch/arm/sunxi/sun8i_v3s_ccu.c

380

val |= __SHIFTIN(AHB2_CLK_CFG_PLL_PERIPH0_2, AHB2_CLK_CFG);

sys/arch/arm/sunxi/sun8i_v3s_codec.c

152

val |= __SHIFTIN(addr, V3S_PR_ADDR);

sys/arch/arm/sunxi/sun8i_v3s_codec.c

173

val |= __SHIFTIN(addr, V3S_PR_ADDR);

sys/arch/arm/sunxi/sun8i_v3s_codec.c

178

val |= __SHIFTIN(data, V3S_ADDA_PR_WDAT);

sys/arch/arm/sunxi/sun8i_v3s_codec.c

282

val |= __SHIFTIN(nvol, mix->mask);

sys/arch/arm/sunxi/sun9i_a80_ccu.c

159

val |= __SHIFTIN(n, nkmp->n);

sys/arch/arm/sunxi/sunxi_ccu_div.c

177

val |= __SHIFTIN(raw_div, div->div);

sys/arch/arm/sunxi/sunxi_ccu_div.c

206

val |= __SHIFTIN(index, div->sel);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

130

val |= __SHIFTIN(fractional->prediv_val - 1,

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

143

val |= __SHIFTIN(i, fractional->frac_sel);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

174

val |= __SHIFTIN(best_m, fractional->m);

sys/arch/arm/sunxi/sunxi_ccu_mux.c

62

val |= __SHIFTIN(index, mux->sel);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

160

val |= __SHIFTIN(tab->p, nkmp->p);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

166

val |= __SHIFTIN(tab->m, nkmp->m);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

172

val |= __SHIFTIN(tab->n, nkmp->n);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

176

val |= __SHIFTIN(tab->k, nkmp->k);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

182

val |= __SHIFTIN(tab->m, nkmp->m);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

188

val |= __SHIFTIN(tab->p, nkmp->p);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

195

val |= __SHIFTIN(tab->n, nkmp->n);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

199

val |= __SHIFTIN(tab->k, nkmp->k);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

203

val |= __SHIFTIN(tab->m, nkmp->m);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

207

val |= __SHIFTIN(tab->p, nkmp->p);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

132

val |= __SHIFTIN(pindex, nm->sel);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

179

val |= __SHIFTIN(best_parent, nm->sel);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

181

val |= __SHIFTIN(best_n, nm->n);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

183

val |= __SHIFTIN(best_m, nm->m);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

212

val |= __SHIFTIN(index, nm->sel);

sys/arch/arm/sunxi/sunxi_ccu_phase.c

111

val |= __SHIFTIN(delay, phase->mask);

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

119

val |= __SHIFTIN(index, prediv->sel);

sys/arch/arm/sunxi/sunxi_codec.c

310

__SHIFTIN(DAC_FS_48KHZ, DAC_FIFOC_FS) |

sys/arch/arm/sunxi/sunxi_codec.c

311

__SHIFTIN(FIFO_MODE_16_15_0, DAC_FIFOC_FIFO_MODE) |

sys/arch/arm/sunxi/sunxi_codec.c

312

__SHIFTIN(DRQ_CLR_CNT, DAC_FIFOC_DRQ_CLR_CNT) |

sys/arch/arm/sunxi/sunxi_codec.c

313

__SHIFTIN(TX_TRIG_LEVEL, DAC_FIFOC_TX_TRIG_LEVEL));

sys/arch/arm/sunxi/sunxi_codec.c

375

__SHIFTIN(ADC_FS_48KHZ, ADC_FIFOC_FS) |

sys/arch/arm/sunxi/sunxi_codec.c

376

__SHIFTIN(RX_TRIG_LEVEL, ADC_FIFOC_RX_TRIG_LEVEL) |

sys/arch/arm/sunxi/sunxi_debe.c

423

__SHIFTIN(yy, SUNXI_DEBE_HWCCTL_YCOOR) |

sys/arch/arm/sunxi/sunxi_debe.c

424

__SHIFTIN(xx, SUNXI_DEBE_HWCCTL_XCOOR));

sys/arch/arm/sunxi/sunxi_debe.c

427

__SHIFTIN(SUNXI_DEBE_HWCFBCTL_YSIZE_32, SUNXI_DEBE_HWCFBCTL_YSIZE) |

sys/arch/arm/sunxi/sunxi_debe.c

428

__SHIFTIN(SUNXI_DEBE_HWCFBCTL_XSIZE_32, SUNXI_DEBE_HWCFBCTL_XSIZE) |

sys/arch/arm/sunxi/sunxi_debe.c

430

__SHIFTIN(SUNXI_DEBE_HWCFBCTL_YSIZE_64, SUNXI_DEBE_HWCFBCTL_YSIZE) |

sys/arch/arm/sunxi/sunxi_debe.c

431

__SHIFTIN(SUNXI_DEBE_HWCFBCTL_XSIZE_64, SUNXI_DEBE_HWCFBCTL_XSIZE) |

sys/arch/arm/sunxi/sunxi_debe.c

433

__SHIFTIN(SUNXI_DEBE_HWCFBCTL_FBFMT_2BPP, SUNXI_DEBE_HWCFBCTL_FBFMT) |

sys/arch/arm/sunxi/sunxi_debe.c

434

__SHIFTIN(yoff, SUNXI_DEBE_HWCFBCTL_YCOOROFF) |

sys/arch/arm/sunxi/sunxi_debe.c

435

__SHIFTIN(xoff, SUNXI_DEBE_HWCFBCTL_XCOOROFF));

sys/arch/arm/sunxi/sunxi_debe.c

617

val |= __SHIFTIN(SUNXI_DEBE_ATTCTL1_LAY_FBFMT_XRGB8888,

sys/arch/arm/sunxi/sunxi_debe.c

627

val |= __SHIFTIN(SUNXI_DEBE_ATTCTL1_LAY_FBPS_32BPP_BGRA,

sys/arch/arm/sunxi/sunxi_debe.c

630

val |= __SHIFTIN(SUNXI_DEBE_ATTCTL1_LAY_FBPS_32BPP_ARGB,

sys/arch/arm/sunxi/sunxi_debe.c

644

val |= __SHIFTIN(SUNXI_DEBE_MODCTL_OUT_SEL_LCD1,

sys/arch/arm/sunxi/sunxi_gmacclk.c

183

val |= __SHIFTIN(GMAC_CLK_PIT_MII, GMAC_CLK_PIT);

sys/arch/arm/sunxi/sunxi_gmacclk.c

184

val |= __SHIFTIN(GMAC_CLK_SRC_MII, GMAC_CLK_SRC);

sys/arch/arm/sunxi/sunxi_gmacclk.c

187

val |= __SHIFTIN(GMAC_CLK_PIT_RGMII, GMAC_CLK_PIT);

sys/arch/arm/sunxi/sunxi_gmacclk.c

188

val |= __SHIFTIN(GMAC_CLK_SRC_RGMII, GMAC_CLK_SRC);

sys/arch/arm/sunxi/sunxi_gpio.c

243

cfg |= __SHIFTIN(n, cfg_mask);

sys/arch/arm/sunxi/sunxi_gpio.c

274

pull |= __SHIFTIN(SUNXI_GPIO_PULL_UP, pull_mask);

sys/arch/arm/sunxi/sunxi_gpio.c

276

pull |= __SHIFTIN(SUNXI_GPIO_PULL_DOWN, pull_mask);

sys/arch/arm/sunxi/sunxi_gpio.c

278

pull |= __SHIFTIN(SUNXI_GPIO_PULL_DISABLE, pull_mask);

sys/arch/arm/sunxi/sunxi_gpio.c

304

drv |= __SHIFTIN((drive_strength / 10) - 1, drv_mask);

sys/arch/arm/sunxi/sunxi_gpio.c

425

data |= __SHIFTIN(val, data_mask);

sys/arch/arm/sunxi/sunxi_gpio.c

509

val |= __SHIFTIN(mode, SUNXI_GPIO_INT_MODEMASK(eint->eint_num));

sys/arch/arm/sunxi/sunxi_gpio.c

824

val |= __SHIFTIN(val, SUNXI_GPIO_GRP_IO_BIAS_CONFIGMASK);

sys/arch/arm/sunxi/sunxi_hdmi.c

1040

val |= __SHIFTIN(1, SUNXI_HDMI_AUD_FMT_SRC_CH_CFG);

sys/arch/arm/sunxi/sunxi_hdmi.c

1053

val = __SHIFTIN(SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ_48,

sys/arch/arm/sunxi/sunxi_hdmi.c

1062

val |= __SHIFTIN(5, SUNXI_HDMI_AUD_CH_STATUS1_WORD_LEN);

sys/arch/arm/sunxi/sunxi_hdmi.c

344

val |= __SHIFTIN(block, SUNXI_HDMI_DDC_SLAVE_ADDR_0);

sys/arch/arm/sunxi/sunxi_hdmi.c

345

val |= __SHIFTIN(0x60, SUNXI_HDMI_DDC_SLAVE_ADDR_1);

sys/arch/arm/sunxi/sunxi_hdmi.c

346

val |= __SHIFTIN(reg, SUNXI_HDMI_DDC_SLAVE_ADDR_2);

sys/arch/arm/sunxi/sunxi_hdmi.c

347

val |= __SHIFTIN(addr, SUNXI_HDMI_DDC_SLAVE_ADDR_3);

sys/arch/arm/sunxi/sunxi_hdmi.c

393

val = __SHIFTIN(block, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_SEG_PTR);

sys/arch/arm/sunxi/sunxi_hdmi.c

394

val |= __SHIFTIN(0x60, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_DDC_CMD);

sys/arch/arm/sunxi/sunxi_hdmi.c

395

val |= __SHIFTIN(reg, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_OFF_ADR);

sys/arch/arm/sunxi/sunxi_hdmi.c

396

val |= __SHIFTIN(addr, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_DEV_ADR);

sys/arch/arm/sunxi/sunxi_hdmi.c

400

__SHIFTIN(len, SUNXI_A31_HDMI_DDC_COMMAND_DTC) |

sys/arch/arm/sunxi/sunxi_hdmi.c

401

__SHIFTIN(type, SUNXI_A31_HDMI_DDC_COMMAND_CMD));

sys/arch/arm/sunxi/sunxi_hdmi.c

467

__SHIFTIN(5, SUNXI_HDMI_DDC_CLOCK_N) |

sys/arch/arm/sunxi/sunxi_hdmi.c

468

__SHIFTIN(1, SUNXI_HDMI_DDC_CLOCK_M));

sys/arch/arm/sunxi/sunxi_hdmi.c

477

__SHIFTIN(1, SUNXI_HDMI_DDC_CLOCK_N) |

sys/arch/arm/sunxi/sunxi_hdmi.c

478

__SHIFTIN(12, SUNXI_HDMI_DDC_CLOCK_M));

sys/arch/arm/sunxi/sunxi_hdmi.c

814

val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_SRC_SEL_CBGEN,

sys/arch/arm/sunxi/sunxi_hdmi.c

817

val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_SRC_SEL_RGB,

sys/arch/arm/sunxi/sunxi_hdmi.c

908

pll_ctrl |= __SHIFTIN(best_div - 1, SUNXI_HDMI_PLL_CTRL_PREDIV);

sys/arch/arm/sunxi/sunxi_hdmi.c

913

pll_ctrl |= __SHIFTIN(best_div, SUNXI_HDMI_PLL_CTRL_PREDIV);

sys/arch/arm/sunxi/sunxi_hdmi.c

936

val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_HDMI_MODE_DVI,

sys/arch/arm/sunxi/sunxi_hdmi.c

939

val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_HDMI_MODE_HDMI,

sys/arch/arm/sunxi/sunxi_hdmi.c

944

val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_REPEATER_SEL_2X,

sys/arch/arm/sunxi/sunxi_hdmi.c

949

val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_OUTPUT_FMT_INTERLACE,

sys/arch/arm/sunxi/sunxi_hdmi.c

954

val = __SHIFTIN((mode->hdisplay << dblscan_p) - 1,

sys/arch/arm/sunxi/sunxi_hdmi.c

956

val |= __SHIFTIN(mode->vdisplay - 1,

sys/arch/arm/sunxi/sunxi_hdmi.c

960

val = __SHIFTIN((hbp << dblscan_p) - 1,

sys/arch/arm/sunxi/sunxi_hdmi.c

962

val |= __SHIFTIN(vbp - 1,

sys/arch/arm/sunxi/sunxi_hdmi.c

966

val = __SHIFTIN((hfp << dblscan_p) - 1,

sys/arch/arm/sunxi/sunxi_hdmi.c

968

val |= __SHIFTIN(vfp - 1,

sys/arch/arm/sunxi/sunxi_hdmi.c

972

val = __SHIFTIN((hspw << dblscan_p) - 1,

sys/arch/arm/sunxi/sunxi_hdmi.c

974

val |= __SHIFTIN(vspw - 1,

sys/arch/arm/sunxi/sunxi_hdmi.c

985

val |= __SHIFTIN(SUNXI_HDMI_VID_TIMING_4_TX_CLOCK_NORMAL,

sys/arch/arm/sunxi/sunxi_hdmiphy.c

234

PHY_SET_CLEAR(sc, ANA_CFG1, __SHIFTIN(0x7, ANA_CFG1_ENP2S), ANA_CFG1_ENP2S);

sys/arch/arm/sunxi/sunxi_hdmiphy.c

246

PHY_SET_CLEAR(sc, ANA_CFG1, __SHIFTIN(0xf, ANA_CFG1_BIASEN), ANA_CFG1_BIASEN);

sys/arch/arm/sunxi/sunxi_hdmiphy.c

249

PHY_SET_CLEAR(sc, ANA_CFG1, __SHIFTIN(0xf, ANA_CFG1_ENP2S), ANA_CFG1_ENP2S);

sys/arch/arm/sunxi/sunxi_hdmiphy.c

347

PHY_SET(sc, PLL_CFG1, __SHIFTIN(b_out, PLL_CFG1_B_IN));

sys/arch/arm/sunxi/sunxi_hdmiphy.c

390

PHY_SET_CLEAR(sc, PLL_CFG2, __SHIFTIN(best_prediv, PLL_CFG2_PREDIV), PLL_CFG2_PREDIV);

sys/arch/arm/sunxi/sunxi_hdmiphy.c

482

pol |= __SHIFTIN(DBG_CTRL_POL_NHSYNC, DBG_CTRL_POL);

sys/arch/arm/sunxi/sunxi_hdmiphy.c

484

pol |= __SHIFTIN(DBG_CTRL_POL_NVSYNC, DBG_CTRL_POL);

sys/arch/arm/sunxi/sunxi_i2s.c

678

val |= __SHIFTIN(bclk_val, DA_CLKD_BCLKDIV_SUN4I);

sys/arch/arm/sunxi/sunxi_i2s.c

682

val |= __SHIFTIN(bclk_val, DA_CLKD_BCLKDIV_SUN8I);

sys/arch/arm/sunxi/sunxi_i2s.c

685

val |= __SHIFTIN(mclk_val, DA_CLKD_MCLKDIV);

sys/arch/arm/sunxi/sunxi_i2s.c

709

fat0 |= __SHIFTIN(DA_FMT_I2S, DA_FAT0_FMT);

sys/arch/arm/sunxi/sunxi_i2s.c

712

fat0 |= __SHIFTIN(DA_FMT_RJ, DA_FAT0_FMT);

sys/arch/arm/sunxi/sunxi_i2s.c

715

fat0 |= __SHIFTIN(DA_FMT_LJ, DA_FAT0_FMT);

sys/arch/arm/sunxi/sunxi_i2s.c

725

ctl |= __SHIFTIN(DA_CTL_MODE_SEL_LJ, DA_CTL_MODE_SEL);

sys/arch/arm/sunxi/sunxi_i2s.c

729

ctl |= __SHIFTIN(DA_CTL_MODE_SEL_LJ, DA_CTL_MODE_SEL);

sys/arch/arm/sunxi/sunxi_i2s.c

733

ctl |= __SHIFTIN(DA_CTL_MODE_SEL_RJ, DA_CTL_MODE_SEL);

sys/arch/arm/sunxi/sunxi_i2s.c

737

ctl |= __SHIFTIN(DA_CTL_MODE_SEL_PCM, DA_CTL_MODE_SEL);

sys/arch/arm/sunxi/sunxi_i2s.c

741

ctl |= __SHIFTIN(DA_CTL_MODE_SEL_PCM, DA_CTL_MODE_SEL);

sys/arch/arm/sunxi/sunxi_i2s.c

750

chsel |= __SHIFTIN(offset, DA_CHSEL_OFFSET);

sys/arch/arm/sunxi/sunxi_i2s.c

755

chsel |= __SHIFTIN(offset, DA_CHSEL_OFFSET);

sys/arch/arm/sunxi/sunxi_i2s.c

762

fat0 |= __SHIFTIN(DA_BCP_INVERTED, DA_FAT0_BCP);

sys/arch/arm/sunxi/sunxi_i2s.c

764

fat0 |= __SHIFTIN(DA_LRCP_INVERTED, DA_FAT0_LRCP);

sys/arch/arm/sunxi/sunxi_i2s.c

767

fat0 |= __SHIFTIN(DA_BCP_INVERTED, DA_FAT0_BCP);

sys/arch/arm/sunxi/sunxi_i2s.c

769

fat0 |= __SHIFTIN(DA_LRCP_INVERTED, DA_FAT0_LRCP);

sys/arch/arm/sunxi/sunxi_i2s.c

772

fat0 |= __SHIFTIN(32 - 1, DA_FAT0_LRCK_PERIOD);

sys/arch/arm/sunxi/sunxi_i2s.c

932

val |= __SHIFTIN(3, DA_CHSEL_EN);

sys/arch/arm/sunxi/sunxi_i2s.c

934

val |= __SHIFTIN(1, DA_CHSEL_SEL);

sys/arch/arm/sunxi/sunxi_i2s.c

939

val |= __SHIFTIN(3, DA_CHSEL_EN);

sys/arch/arm/sunxi/sunxi_i2s.c

941

val |= __SHIFTIN(1, DA_CHSEL_SEL);

sys/arch/arm/sunxi/sunxi_i2s.c

947

val |= __SHIFTIN(1, DA_CHCFG_TX_SLOT_NUM);

sys/arch/arm/sunxi/sunxi_i2s.c

949

val |= __SHIFTIN(1, DA_CHCFG_RX_SLOT_NUM);

sys/arch/arm/sunxi/sunxi_lcdc.c

227

__SHIFTIN(start_delay, TCON0_CTL_START_DELAY);

sys/arch/arm/sunxi/sunxi_lcdc.c

280

__SHIFTIN(start_delay, TCON1_CTL_START_DELAY);

sys/arch/arm/sunxi/sunxi_lcdc.c

291

__SHIFTIN(start_delay + 2, TCON_GINT1_TCON1_LINE_INT_NUM));

sys/arch/arm/sunxi/sunxi_mc_smp.c

150

printf("CPU %#llx failed to start\n", __SHIFTIN(cluster, MPIDR_AFF1) | __SHIFTIN(cpu, MPIDR_AFF0));

sys/arch/arm/sunxi/sunxi_mixer.c

325

__SHIFTIN(OVL_UI_ATTR_CTL_LAY_FBFMT_XRGB_8888,

sys/arch/arm/sunxi/sunxi_mixer.c

335

val |= __SHIFTIN(haddr, OVL_UI_TOP_HADD_LAYER0);

sys/arch/arm/sunxi/sunxi_mixer.c

417

val |= __SHIFTIN(1, BLD_CH_RTCTL_P0);

sys/arch/arm/sunxi/sunxi_mmc.c

890

clkcr |= __SHIFTIN(dbl, SUNXI_MMC_CLKCR_DIV);

sys/arch/arm/sunxi/sunxi_nand.c

235

__SHIFTIN(chip->chip_addr_count - 1, NDFC_CMD_ADR_NUM));

sys/arch/arm/sunxi/sunxi_nand.c

375

ctl |= __SHIFTIN(chip->chip_cs, NDFC_CTL_CE_SEL);

sys/arch/arm/sunxi/sunxi_nand.c

377

ctl |= __SHIFTIN(chip->chip_rb, NDFC_CTL_RB_SEL);

sys/arch/arm/sunxi/sunxi_nand.c

383

ctl |= __SHIFTIN(__builtin_ffs(nc->nc_page_size) - 11,

sys/arch/arm/sunxi/sunxi_nmi.c

154

val |= __SHIFTIN(irq_type, NMI_CTRL_IRQ_TYPE);

sys/arch/arm/sunxi/sunxi_platform.c

389

__SHIFTIN(SUN4I_TIMER_1_CTRL_CLK_SRC_OSC24M,

sys/arch/arm/sunxi/sunxi_pwm.c

158

ctrl |= __SHIFTIN(0, PWM_CH0_PRESCAL);

sys/arch/arm/sunxi/sunxi_pwm.c

170

ch_period = __SHIFTIN(cycles - 1, PWM_CH0_ENTIRE_CYS);

sys/arch/arm/sunxi/sunxi_pwm.c

171

ch_period |= __SHIFTIN(act_cycles, PWM_CH0_ENTIRE_ACT_CYS);

sys/arch/arm/sunxi/sunxi_rsb.c

290

dar = __SHIFTIN(rta, RSB_DAR_RTA);

sys/arch/arm/sunxi/sunxi_rsb.c

291

dar |= __SHIFTIN(da, RSB_DAR_DA);

sys/arch/arm/sunxi/sunxi_rsb.c

411

dlen = __SHIFTIN(len - 1, RSB_DLEN_ACCESS_LENGTH);

sys/arch/arm/sunxi/sunxi_rtc.c

482

yymmdd = __SHIFTIN(dt->dt_year - conf->base_year, conf->year);

sys/arch/arm/sunxi/sunxi_rtc.c

483

yymmdd |= __SHIFTIN(dt->dt_mon, conf->month);

sys/arch/arm/sunxi/sunxi_rtc.c

484

yymmdd |= __SHIFTIN(dt->dt_day, conf->day);

sys/arch/arm/sunxi/sunxi_rtc.c

486

hhmmss = __SHIFTIN(dt->dt_wday, conf->wk_no);

sys/arch/arm/sunxi/sunxi_rtc.c

487

hhmmss |= __SHIFTIN(dt->dt_hour, conf->hour);

sys/arch/arm/sunxi/sunxi_rtc.c

488

hhmmss |= __SHIFTIN(dt->dt_min, conf->minute);

sys/arch/arm/sunxi/sunxi_rtc.c

489

hhmmss |= __SHIFTIN(dt->dt_sec, conf->second);

sys/arch/arm/sunxi/sunxi_sramc.c

262

val |= __SHIFTIN(config, node->area->mask);

sys/arch/arm/sunxi/sunxi_tcon.c

230

__SHIFTIN(0x20, SUNXI_TCON_GINT1_TCON0_LINENO));

sys/arch/arm/sunxi/sunxi_tcon.c

302

__SHIFTIN(SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC_CLOSE,

sys/arch/arm/sunxi/sunxi_tcon.c

514

val = __SHIFTIN(start_delay, SUNXI_TCONx_CTL_START_DELAY);

sys/arch/arm/sunxi/sunxi_tcon.c

519

val |= __SHIFTIN(SUNXI_TCONx_CTL_SRC_SEL_DE0,

sys/arch/arm/sunxi/sunxi_tcon.c

545

__SHIFTIN(start_delay + 2, SUNXI_TCON_GINT1_TCON0_LINENO));

sys/arch/arm/sunxi/sunxi_tcon.c

549

val |= __SHIFTIN(best_div, SUNXI_TCON0_DCLK_DIV);

sys/arch/arm/sunxi/sunxi_tcon.c

696

val |= __SHIFTIN(SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC_LCDC0_TCON1,

sys/arch/arm/sunxi/sunxi_tcon.c

700

val |= __SHIFTIN(SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC_LCDC1_TCON1,

sys/arch/arm/sunxi/sunxi_tcon.c

751

val |= __SHIFTIN(start_delay, SUNXI_TCONx_CTL_START_DELAY);

sys/arch/arm/sunxi/sunxi_tcon.c

753

val |= __SHIFTIN(SUNXI_TCONx_CTL_SRC_SEL_BLUEDATA,

sys/arch/arm/sunxi/sunxi_tcon.c

760

val |= __SHIFTIN(SUNXI_TCONx_CTL_SRC_SEL_DE0,

sys/arch/arm/sunxi/sunxi_tcon.c

803

__SHIFTIN(start_delay + 2, SUNXI_TCON_GINT1_TCON1_LINENO));

sys/arch/arm/sunxi/sunxi_timer.c

226

__SHIFTIN(TMR0_CTRL_CLK_SRC_OSC24M, TMR0_CTRL_CLK_SRC) |

sys/arch/arm/sunxi/sunxi_timer.c

231

__SHIFTIN(TMR2_CTRL_CLK_SRC_OSC24M, TMR2_CTRL_CLK_SRC) |

sys/arch/arm/sunxi/sunxi_timer.c

255

reg = __SHIFTIN(LOSC_CTRL_KEY_FIELD_V, LOSC_CTRL_KEY_FIELD) |

sys/arch/arm/sunxi/sunxi_ts.c

197

val |= __SHIFTIN(1, TP_INT_FIFO_TRIG_LEVEL);

sys/arch/arm/sunxi/sunxi_ts.c

315

__SHIFTIN(0, TP_CTRL0_ADC_CLK_SELECT) |

sys/arch/arm/sunxi/sunxi_ts.c

316

__SHIFTIN(2, TP_CTRL0_ADC_CLK_DIVIDER) |

sys/arch/arm/sunxi/sunxi_ts.c

317

__SHIFTIN(7, TP_CTRL0_FS_DIV) |

sys/arch/arm/sunxi/sunxi_ts.c

318

__SHIFTIN(63, TP_CTRL0_T_ACQ));

sys/arch/arm/sunxi/sunxi_ts.c

320

__SHIFTIN(0, TP_CTRL2_MODE_SELECT) |

sys/arch/arm/sunxi/sunxi_ts.c

321

__SHIFTIN(tp_sensitivity_adjust, TP_CTRL2_SENSITIVE_ADJUST));

sys/arch/arm/sunxi/sunxi_ts.c

324

__SHIFTIN(filter_type, TP_CTRL3_FILTER_TYPE));

sys/arch/arm/sunxi/sunxi_ts.c

328

__SHIFTIN(5, TP_CTRL1_STYLUS_UP_DEBOUNCE));

sys/arch/arm/sunxi/sunxi_ts.c

332

TP_TPR_TEMP_EN | __SHIFTIN(1953, TP_TPR_TEMP_PER));

sys/arch/arm/sunxi/sunxi_twi.c

104

baud = __SHIFTIN(n, TWI_CCR_CLK_N) |

sys/arch/arm/sunxi/sunxi_twi.c

105

__SHIFTIN(m, TWI_CCR_CLK_M);

sys/arch/arm/sunxi/sunxi_usb3phy.c

139

val |= __SHIFTIN(0x55, PTH_TX_SWING_FULL);

sys/arch/arm/sunxi/sunxi_usb3phy.c

141

val |= __SHIFTIN(0x20, PTH_TX_DEEMPH_6DB);

sys/arch/arm/sunxi/sunxi_usb3phy.c

143

val |= __SHIFTIN(0x15, PTH_TX_DEEMPH_3P5DB);

sys/arch/arm/sunxi/sunxi_usbphy.c

172

val |= __SHIFTIN(bit_addr, PHYCTL_ADDR);

sys/arch/arm/sunxi/sunxi_usbphy.c

177

val |= __SHIFTIN(bits & 1, PHYCTL_DATA);

sys/arch/arm/sunxi/sunxi_usbphy.c

305

val |= __SHIFTIN(PHYCTL_ICR_FORCE_ID_LOW, PHYCTL_ICR_FORCE_ID);

sys/arch/arm/sunxi/sunxi_usbphy.c

307

val |= __SHIFTIN(PHYCTL_ICR_FORCE_VBUS_HIGH, PHYCTL_ICR_FORCE_VBUS);

sys/arch/arm/sunxi/sunxi_wdt.c

146

__SHIFTIN(intv, SUN4I_WDT_MODE_INTV);

sys/arch/arm/sunxi/sunxi_wdt.c

159

__SHIFTIN(SUN4I_WDT_CTRL_KEY_FIELD_V, SUN4I_WDT_CTRL_KEY_FIELD);

sys/arch/arm/sunxi/sunxi_wdt.c

183

cfg = __SHIFTIN(SUN6I_WDT_CFG_CONFIG_SYS, SUN6I_WDT_CFG_CONFIG);

sys/arch/arm/sunxi/sunxi_wdt.c

184

mode = SUN6I_WDT_MODE_EN | __SHIFTIN(intv, SUN6I_WDT_MODE_INTV);

sys/arch/arm/sunxi/sunxi_wdt.c

198

__SHIFTIN(SUN6I_WDT_CTRL_KEY_FIELD_V, SUN6I_WDT_CTRL_KEY_FIELD);

sys/arch/arm/sunxi/sunxi_wdt.c

213

mode = __SHIFTIN(SUNXI_WDT_KEY_FIELD_V, SUNXI_WDT_KEY_FIELD);

sys/arch/arm/sunxi/sunxi_wdt.c

223

cfg = __SHIFTIN(SUN6I_WDT_CFG_CONFIG_SYS, SUN6I_WDT_CFG_CONFIG);

sys/arch/arm/sunxi/sunxi_wdt.c

224

cfg |= __SHIFTIN(SUNXI_WDT_KEY_FIELD_V, SUNXI_WDT_KEY_FIELD);

sys/arch/arm/sunxi/sunxi_wdt.c

225

mode = SUN6I_WDT_MODE_EN | __SHIFTIN(intv, SUN6I_WDT_MODE_INTV);

sys/arch/arm/sunxi/sunxi_wdt.c

226

mode |= __SHIFTIN(SUNXI_WDT_KEY_FIELD_V, SUNXI_WDT_KEY_FIELD);

sys/arch/arm/sunxi/sunxi_wdt.c

292

mode = __SHIFTIN(SUNXI_WDT_KEY_FIELD_V, SUNXI_WDT_KEY_FIELD);

sys/arch/arm/ti/am3_prcm.c

100

__SHIFTIN(AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN_MN_BYPASS,

sys/arch/arm/ti/am3_prcm.c

110

val = __SHIFTIN(DPLL_DISP_RATE / 1000000, AM3_PRCM_CM_CLKSEL_DPLL_DISP_DPLL_MULT);

sys/arch/arm/ti/am3_prcm.c

111

val |= __SHIFTIN(24 - 1, AM3_PRCM_CM_CLKSEL_DPLL_DISP_DPLL_DIV);

sys/arch/arm/ti/am3_prcm.c

116

__SHIFTIN(AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN_LOCK,

sys/arch/arm/ti/am3_prcm.c

84

val |= __SHIFTIN(AM3_PRCM_CLKCTRL_MODULEMODE_ENABLE,

sys/arch/arm/ti/omap3_platform.c

389

val |= __SHIFTIN(0xf, i * 4);

sys/arch/arm/ti/omap4_prcm.c

113

val |= __SHIFTIN(CLKCTRL_MODULEMODE_AUTO,

sys/arch/arm/ti/omap4_prcm.c

116

val |= __SHIFTIN(CLKCTRL_MODULEMODE_DISABLE,

sys/arch/arm/ti/omap4_prcm.c

87

val |= __SHIFTIN(CLKCTRL_MODULEMODE_ENABLE,

sys/arch/arm/ti/omap4_prcm.c

90

val |= __SHIFTIN(CLKCTRL_MODULEMODE_DISABLE,

sys/arch/arm/ti/ti_dpll_clock.c

298

control |= __SHIFTIN(AM3_DPLL_EN_NM_BYPASS, AM3_DPLL_EN);

sys/arch/arm/ti/ti_dpll_clock.c

304

mult_div1 = __SHIFTIN(mult, DPLL_MULT);

sys/arch/arm/ti/ti_dpll_clock.c

305

mult_div1 |= __SHIFTIN(div, DPLL_DIV);

sys/arch/arm/ti/ti_dpll_clock.c

309

control |= __SHIFTIN(AM3_DPLL_EN_LOCK, AM3_DPLL_EN);

sys/arch/arm/ti/ti_dpll_clock.c

338

control |= __SHIFTIN(OMAP3_EN_MPU_DPLL_BYPASS, OMAP3_EN_MPU_DPLL);

sys/arch/arm/ti/ti_dpll_clock.c

343

mult_div1 = __SHIFTIN(mult, DPLL_MULT);

sys/arch/arm/ti/ti_dpll_clock.c

344

mult_div1 |= __SHIFTIN(div, DPLL_DIV);

sys/arch/arm/ti/ti_dpll_clock.c

348

control |= __SHIFTIN(OMAP3_EN_MPU_DPLL_LOCK, OMAP3_EN_MPU_DPLL);

sys/arch/arm/ti/ti_edma.c

184

__SHIFTIN(0, EDMA_DCHMAP_PAENTRY));

sys/arch/arm/ti/ti_edma.c

211

__SHIFTIN(ep->ep_bcnt, EDMA_PARAM_CNT_BCNT) |

sys/arch/arm/ti/ti_edma.c

212

__SHIFTIN(ep->ep_acnt, EDMA_PARAM_CNT_ACNT));

sys/arch/arm/ti/ti_edma.c

215

__SHIFTIN(ep->ep_dstbidx, EDMA_PARAM_BIDX_DSTBIDX) |

sys/arch/arm/ti/ti_edma.c

216

__SHIFTIN(ep->ep_srcbidx, EDMA_PARAM_BIDX_SRCBIDX));

sys/arch/arm/ti/ti_edma.c

218

__SHIFTIN(ep->ep_bcntrld, EDMA_PARAM_LNK_BCNTRLD) |

sys/arch/arm/ti/ti_edma.c

219

__SHIFTIN(ep->ep_link, EDMA_PARAM_LNK_LINK));

sys/arch/arm/ti/ti_edma.c

221

__SHIFTIN(ep->ep_dstcidx, EDMA_PARAM_CIDX_DSTCIDX) |

sys/arch/arm/ti/ti_edma.c

222

__SHIFTIN(ep->ep_srccidx, EDMA_PARAM_CIDX_SRCCIDX));

sys/arch/arm/ti/ti_edma.c

224

__SHIFTIN(ep->ep_ccnt, EDMA_PARAM_CCNT_CCNT));

sys/arch/arm/ti/ti_edma.c

437

__SHIFTIN(param_entry, EDMA_DCHMAP_PAENTRY));

sys/arch/arm/ti/ti_edma.c

484

__SHIFTIN(0, EDMA_DCHMAP_PAENTRY));

sys/arch/arm/ti/ti_mux_clock.c

212

val |= __SHIFTIN(sel, sc->sc_mask);

sys/arch/arm/ti/ti_omapmusb.c

150

val = __SHIFTIN(IDLEMODE_SMART, OTG_SYSCONFIG_MIDLEMODE) |

sys/arch/arm/ti/ti_omapmusb.c

151

__SHIFTIN(IDLEMODE_SMART, OTG_SYSCONFIG_SIDLEMODE) |

sys/arch/arm/ti/ti_rng.c

105

__SHIFTIN(0x21, TRNG_CONFIG_MIN_REFILL) |

sys/arch/arm/ti/ti_rng.c

106

__SHIFTIN(0x22, TRNG_CONFIG_MAX_REFILL));

sys/arch/arm/ti/ti_rng.c

108

__SHIFTIN(0x21, TRNG_CONTROL_STARTUP_CYCLES) |

sys/arch/arm/ti/ti_sdhc.c

609

ep.ep_opt = __SHIFTIN(2, EDMA_PARAM_OPT_FWID) /* 32-bit */;

sys/arch/arm/ti/ti_sdhc.c

610

ep.ep_opt |= __SHIFTIN(edma_channel_index(edma),

sys/arch/arm/ti/ti_usb.c

172

val |= __SHIFTIN(mode, UHH_HOSTCONFIG_PN_MODE_MASK(port));

sys/arch/arm/ti/ti_usb.c

196

val |= __SHIFTIN(UHH_SYSCONFIG_IDLEMODE_NOIDLE, UHH_SYSCONFIG_IDLEMODE_MASK);

sys/arch/arm/ti/ti_usb.c

198

val |= __SHIFTIN(UHH_SYSCONFIG_STANDBYMODE_NOSTDBY, UHH_SYSCONFIG_STANDBYMODE_MASK);

sys/arch/arm/ti/ti_wdt.c

176

WR4(sc, WDT_WCLR, WCLR_PRE | __SHIFTIN(1, WCLR_PTV));

sys/arch/arm/vexpress/vexpress_platform.c

209

__SHIFTIN(SYS_CFGCTRL_FUNCTION_REBOOT,

sys/arch/arm/vexpress/vexpress_sysreg.c

74

__SHIFTIN(func, SYS_CFGCTRL_FUNCTION) |

sys/arch/arm/vexpress/vexpress_sysreg.c

75

__SHIFTIN(site, SYS_CFGCTRL_SITE);

sys/arch/arm/vfp/vfp_init.c

269

cpacr |= __SHIFTIN(CPACR_ALL, cpacr_vfp);

sys/arch/arm/vfp/vfp_init.c

270

cpacr |= __SHIFTIN(CPACR_ALL, cpacr_vfp2);

sys/arch/arm/xilinx/zynq_uartreg.h

45

#define NBSTOP_1 __SHIFTIN(0, MR_NBSTOP)

sys/arch/arm/xilinx/zynq_uartreg.h

46

#define NBSTOP_15 __SHIFTIN(1, MR_NBSTOP)

sys/arch/arm/xilinx/zynq_uartreg.h

47

#define NBSTOP_2 __SHIFTIN(2, MR_NBSTOP)

sys/arch/arm/xilinx/zynq_uartreg.h

49

#define PAR_EVEN __SHIFTIN(0, MR_PAR)

sys/arch/arm/xilinx/zynq_uartreg.h

50

#define PAR_ODD __SHIFTIN(1, MR_PAR)

sys/arch/arm/xilinx/zynq_uartreg.h

51

#define PAR_ZERO __SHIFTIN(2, MR_PAR)

sys/arch/arm/xilinx/zynq_uartreg.h

52

#define PAR_ONE __SHIFTIN(3, MR_PAR)

sys/arch/arm/xilinx/zynq_uartreg.h

53

#define PAR_NONE __SHIFTIN(4, MR_PAR)

sys/arch/arm/xilinx/zynq_uartreg.h

55

#define CHRL_6BIT __SHIFTIN(3, MR_CHRL)

sys/arch/arm/xilinx/zynq_uartreg.h

56

#define CHRL_7BIT __SHIFTIN(2, MR_CHRL)

sys/arch/arm/xilinx/zynq_uartreg.h

57

#define CHRL_8BIT __SHIFTIN(1, MR_CHRL)

sys/arch/arm/xilinx/zynq_usb.c

273

data = ULPI_RUN | __SHIFTIN(addr, ULPI_ADDR);

sys/arch/arm/xilinx/zynq_usb.c

288

reg = ULPI_RUN | ULPI_RW | __SHIFTIN(addr, ULPI_ADDR) | __SHIFTIN(data, ULPI_DATWR);

sys/arch/arm/xilinx/zynq_usbreg.h

100

#define PORTSC_PTS_UTMI __SHIFTIN(0, PORTSC_PTS)

sys/arch/arm/xilinx/zynq_usbreg.h

101

#define PORTSC_PTS_PHILIPS __SHIFTIN(1, PORTSC_PTS)

sys/arch/arm/xilinx/zynq_usbreg.h

102

#define PORTSC_PTS_ULPI __SHIFTIN(2, PORTSC_PTS)

sys/arch/arm/xilinx/zynq_usbreg.h

103

#define PORTSC_PTS_SERIAL __SHIFTIN(3, PORTSC_PTS)

sys/arch/arm/xilinx/zynq_usbreg.h

92

#define USBMODE_CM_IDLE __SHIFTIN(0, USBMODE_CM)

sys/arch/arm/xilinx/zynq_usbreg.h

93

#define USBMODE_CM_DEVICE __SHIFTIN(2, USBMODE_CM)

sys/arch/arm/xilinx/zynq_usbreg.h

94

#define USBMODE_CM_HOST __SHIFTIN(3, USBMODE_CM)

sys/arch/arm/xilinx/zynq_xadc.c

234

val |= __SHIFTIN(CFG_TCKRATE_DIV4, CFG_TCKRATE);

sys/arch/arm/xilinx/zynq_xadc.c

244

__SHIFTIN(CONF1_SEQ_CONT, CONF1_SEQ));

sys/arch/arm/xilinx/zynq_xadc.c

94

(__SHIFTIN(cmd, XADC_COMMAND_CMD) | \

sys/arch/arm/xilinx/zynq_xadc.c

95

__SHIFTIN(addr, XADC_COMMAND_DRP_ADDR) | \

sys/arch/arm/xilinx/zynq_xadc.c

96

__SHIFTIN(data, XADC_COMMAND_DRP_DATA))

sys/arch/arm/xscale/i80312.c

272

__SHIFTIN(0, PCI_BRIDGE_BUS_PRIMARY) |

sys/arch/arm/xscale/i80312.c

273

__SHIFTIN(1, PCI_BRIDGE_BUS_SECONDARY) |

sys/arch/arm/xscale/i80312.c

274

__SHIFTIN(1, PCI_BRIDGE_BUS_SUBORDINATE));

sys/arch/evbarm/dev/plcom.c

549

case PL011_DESIGNER_ARM | __SHIFTIN(0, PL011_HWREV_MASK):

sys/arch/evbarm/dev/plcom.c

550

case PL011_DESIGNER_ARM | __SHIFTIN(1, PL011_HWREV_MASK):

sys/arch/evbarm/dev/plcom.c

551

case PL011_DESIGNER_ARM | __SHIFTIN(2, PL011_HWREV_MASK):

sys/arch/evbmips/cavium/machdep.c

275

wdog |= __SHIFTIN(3, CIU_WDOGX_MODE);

sys/arch/evbppc/mpc85xx/cadmusreg.h

69

#define CM_PCI_PSPEED_33 __SHIFTIN(0, CM_PCI_PSPEED)

sys/arch/evbppc/mpc85xx/cadmusreg.h

70

#define CM_PCI_PSPEED_66 __SHIFTIN(1, CM_PCI_PSPEED)

sys/arch/evbppc/nintendo/dev/avenc.c

159

val = __SHIFTIN(left, AVENC_VOLUME_LEFT) |

sys/arch/evbppc/nintendo/dev/avenc.c

160

__SHIFTIN(right, AVENC_VOLUME_RIGHT);

sys/arch/evbppc/nintendo/dev/exi.c

211

val |= __SHIFTIN(__BIT(dev), EXI_CSR_CS);

sys/arch/evbppc/nintendo/dev/exi.c

213

val |= __SHIFTIN(freq, EXI_CSR_CLK);

sys/arch/evbppc/nintendo/dev/exi.c

274

__SHIFTIN(datalen - 1, EXI_CR_TLEN));

sys/arch/evbppc/nintendo/dev/exi.c

293

__SHIFTIN(datalen - 1, EXI_CR_TLEN));

sys/arch/evbppc/nintendo/dev/exi.c

339

__SHIFTIN(datalen - 1, EXI_CR_TLEN));

sys/arch/evbppc/nintendo/dev/exireg.h

42

#define EXI_CR_RW_READ __SHIFTIN(0, EXI_CR_RW)

sys/arch/evbppc/nintendo/dev/exireg.h

43

#define EXI_CR_RW_WRITE __SHIFTIN(1, EXI_CR_RW)

sys/arch/evbppc/nintendo/dev/exireg.h

44

#define EXI_CR_RW_READWRITE __SHIFTIN(2, EXI_CR_RW)

sys/arch/evbppc/nintendo/dev/gecko.c

53

(__SHIFTIN(1, EXI_CSR_CS) | \

sys/arch/evbppc/nintendo/dev/gecko.c

54

__SHIFTIN(EXI_FREQ_32MHZ, EXI_CSR_CLK))

sys/arch/evbppc/nintendo/dev/gecko.c

56

(__SHIFTIN((len) - 1, EXI_CR_TLEN) | \

sys/arch/evbppc/nintendo/dev/hwaes.c

263

ctrl |= __SHIFTIN(blocks - 1, AES_CTRL_BLOCKS);

sys/arch/evbppc/nintendo/dev/si.c

205

__SHIFTIN(7, SIPOLL_X) |

sys/arch/evbppc/nintendo/dev/si.c

206

__SHIFTIN(1, SIPOLL_Y));

sys/arch/evbppc/nintendo/dev/wiifb.c

273

__SHIFTIN(1, VI_DI_VCT) |

sys/arch/evbppc/nintendo/dev/wiifb.c

274

__SHIFTIN(1, VI_DI_HCT));

sys/arch/evbppc/nintendo/dev/wiifb.c

714

dcr = __SHIFTIN(sc->sc_format, VI_DCR_FMT) |

sys/arch/evbppc/nintendo/dev/wiifb.c

792

__SHIFTIN(strides, VI_PICCONF_STRIDES) |

sys/arch/evbppc/nintendo/dev/wiifb.c

793

__SHIFTIN(reads, VI_PICCONF_READS));

sys/arch/evbppc/nintendo/dev/wiifb.c

797

WR2(sc, VI_HSR, __SHIFTIN(256, VI_HSR_STP));

sys/arch/evbppc/nintendo/dev/wiifb.c

799

WR2(sc, VI_HSR, __SHIFTIN(244, VI_HSR_STP) | VI_HSR_HS_EN);

sys/arch/evbppc/nintendo/dev/wiifb.c

825

__SHIFTIN((taddr >> 5), VI_TFBL_FBB) |

sys/arch/evbppc/nintendo/dev/wiifb.c

826

__SHIFTIN((taddr / 2) & 0xf, VI_TFBL_XOF));

sys/arch/evbppc/nintendo/dev/wiifb.c

831

__SHIFTIN((baddr >> 5), VI_BFBL_FBB) |

sys/arch/evbppc/nintendo/dev/wiifb.c

832

__SHIFTIN((baddr / 2) & 0xf, VI_BFBL_XOF));

sys/arch/evbppc/nintendo/dev/wiifb.c

874

out32(HW_VIDIM, __SHIFTIN(7, VIDIM_Y) |

sys/arch/evbppc/nintendo/dev/wiifb.c

875

__SHIFTIN(7, VIDIM_C) |

sys/arch/evbppc/nintendo/dev/wiiufb.c

68

#define DGRPH_SWAP_ENDIAN_SWAP_8IN32 __SHIFTIN(2, DGRPH_SWAP_ENDIAN_SWAP)

sys/arch/evbppc/nintendo/dev/wiiufb.c

74

#define DCUR_CONTROL_MODE_ARGB_PM __SHIFTIN(2, DCUR_CONTROL_MODE)

sys/arch/evbppc/stand/wii/gecko.c

45

#define EXI_CR_RW_READ __SHIFTIN(0, EXI_CR_RW)

sys/arch/evbppc/stand/wii/gecko.c

46

#define EXI_CR_RW_WRITE __SHIFTIN(1, EXI_CR_RW)

sys/arch/evbppc/stand/wii/gecko.c

47

#define EXI_CR_RW_READWRITE __SHIFTIN(2, EXI_CR_RW)

sys/arch/evbppc/stand/wii/gecko.c

58

(__SHIFTIN(1, EXI_CSR_CS) | \

sys/arch/evbppc/stand/wii/gecko.c

59

__SHIFTIN(EXI_FREQ_32MHZ, EXI_CSR_CLK))

sys/arch/evbppc/stand/wii/gecko.c

61

(__SHIFTIN((len) - 1, EXI_CR_TLEN) | \

sys/arch/evbppc/stand/wii/miniipc.c

133

__SHIFTIN(index_in, HW_IPC_PPCMSG_INDEX_IN_MASK));

sys/arch/evbppc/stand/wii/miniipc.c

178

__SHIFTIN(index_out, HW_IPC_PPCMSG_INDEX_OUT_MASK));

sys/arch/hppa/hppa/trap.c

487

(__SHIFTIN(1, __PABITS(0, 5)) | \

sys/arch/hppa/hppa/trap.c

488

__SHIFTIN(0x4d, __PABITS(18, 25)))

sys/arch/hppa/hppa/trap.c

503

((__SHIFTIN(1, __PABITS(0, 5)) | \

sys/arch/hppa/hppa/trap.c

504

__SHIFTIN(PROBE_ENCS, __PABITS(18, 25)) | \

sys/arch/hppa/hppa/trap.c

505

__SHIFTIN(0, __PABIT(26))) ^ \

sys/arch/i386/pci/elan520.c

1000

pcihostmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_PCIHOSTMAP_PCI_IRQ_MAP);

sys/arch/i386/pci/elan520.c

1147

wpvmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_WPVMAP_INT_MAP);

sys/arch/i386/pci/elan520.c

814

par |= __SHIFTIN(sz / blksz - 1, size_field);

sys/arch/i386/pci/elan520.c

815

par |= __SHIFTIN(addr / blksz, addr_field);

sys/arch/i386/pci/elan520reg.h

237

#define MMCR_WPVSTA_WPV_MSTR_CPU __SHIFTIN(0, MMCR_WPVSTA_WPV_MSTR)

sys/arch/i386/pci/elan520reg.h

238

#define MMCR_WPVSTA_WPV_MSTR_PCI __SHIFTIN(1, MMCR_WPVSTA_WPV_MSTR)

sys/arch/i386/pci/elan520reg.h

239

#define MMCR_WPVSTA_WPV_MSTR_GP __SHIFTIN(2, MMCR_WPVSTA_WPV_MSTR)

sys/arch/i386/pci/elan520reg.h

240

#define MMCR_WPVSTA_WPV_MSTR_RSVD __SHIFTIN(3, MMCR_WPVSTA_WPV_MSTR)

sys/arch/i386/pci/elan520reg.h

246

#define MMCR_PAR_TARGET_OFF __SHIFTIN(0, MMCR_PAR_TARGET)

sys/arch/i386/pci/elan520reg.h

247

#define MMCR_PAR_TARGET_GPIO __SHIFTIN(1, MMCR_PAR_TARGET)

sys/arch/i386/pci/elan520reg.h

248

#define MMCR_PAR_TARGET_GPMEM __SHIFTIN(2, MMCR_PAR_TARGET)

sys/arch/i386/pci/elan520reg.h

249

#define MMCR_PAR_TARGET_PCI __SHIFTIN(3, MMCR_PAR_TARGET)

sys/arch/i386/pci/elan520reg.h

250

#define MMCR_PAR_TARGET_BOOTCS __SHIFTIN(4, MMCR_PAR_TARGET)

sys/arch/i386/pci/elan520reg.h

251

#define MMCR_PAR_TARGET_ROMCS1 __SHIFTIN(5, MMCR_PAR_TARGET)

sys/arch/i386/pci/elan520reg.h

252

#define MMCR_PAR_TARGET_ROMCS2 __SHIFTIN(6, MMCR_PAR_TARGET)

sys/arch/i386/pci/elan520reg.h

253

#define MMCR_PAR_TARGET_SDRAM __SHIFTIN(7, MMCR_PAR_TARGET)

sys/arch/i386/pci/elan520reg.h

255

#define MMCR_PAR_ATTR_NOEXEC __SHIFTIN(__BIT(2), MMCR_PAR_ATTR)

sys/arch/i386/pci/elan520reg.h

256

#define MMCR_PAR_ATTR_NOCACHE __SHIFTIN(__BIT(1), MMCR_PAR_ATTR)

sys/arch/i386/pci/elan520reg.h

257

#define MMCR_PAR_ATTR_NOWRITE __SHIFTIN(__BIT(0), MMCR_PAR_ATTR)

sys/arch/i386/pci/elan520reg.h

67

#define MMCR_DBCTL_WB_WM_28DW __SHIFTIN(0, MMCR_DBCTL_WB_WM_MASK)

sys/arch/i386/pci/elan520reg.h

68

#define MMCR_DBCTL_WB_WM_24DW __SHIFTIN(1, MMCR_DBCTL_WB_WM_MASK)

sys/arch/i386/pci/elan520reg.h

69

#define MMCR_DBCTL_WB_WM_16DW __SHIFTIN(2, MMCR_DBCTL_WB_WM_MASK)

sys/arch/i386/pci/elan520reg.h

70

#define MMCR_DBCTL_WB_WM_8DW __SHIFTIN(3, MMCR_DBCTL_WB_WM_MASK)

sys/arch/i386/pci/elan520reg.h

78

__SHIFTIN(0, MMCR_HBCTL_T_DLYTR_ENB_MASK)

sys/arch/i386/pci/elan520reg.h

80

__SHIFTIN(1, MMCR_HBCTL_T_DLYTR_ENB_MASK)

sys/arch/i386/pci/elan520reg.h

82

__SHIFTIN(2, MMCR_HBCTL_T_DLYTR_ENB_MASK)

sys/arch/i386/pci/elan520reg.h

84

__SHIFTIN(3, MMCR_HBCTL_T_DLYTR_ENB_MASK)

sys/arch/i386/pci/geodereg.h

69

#define SC1100_WDCNFG_WDTYPE2_NOACTION __SHIFTIN(0, SC1100_WDCNFG_WDTYPE2_MASK)

sys/arch/i386/pci/geodereg.h

70

#define SC1100_WDCNFG_WDTYPE2_INTERRUPT __SHIFTIN(1, SC1100_WDCNFG_WDTYPE2_MASK)

sys/arch/i386/pci/geodereg.h

71

#define SC1100_WDCNFG_WDTYPE2_SMI __SHIFTIN(2, SC1100_WDCNFG_WDTYPE2_MASK)

sys/arch/i386/pci/geodereg.h

72

#define SC1100_WDCNFG_WDTYPE2_RESET __SHIFTIN(3, SC1100_WDCNFG_WDTYPE2_MASK)

sys/arch/i386/pci/geodereg.h

74

#define SC1100_WDCNFG_WDTYPE1_NOACTION __SHIFTIN(0, SC1100_WDCNFG_WDTYPE1_MASK)

sys/arch/i386/pci/geodereg.h

75

#define SC1100_WDCNFG_WDTYPE1_INTERRUPT __SHIFTIN(1, SC1100_WDCNFG_WDTYPE1_MASK)

sys/arch/i386/pci/geodereg.h

76

#define SC1100_WDCNFG_WDTYPE1_SMI __SHIFTIN(2, SC1100_WDCNFG_WDTYPE1_MASK)

sys/arch/i386/pci/geodereg.h

77

#define SC1100_WDCNFG_WDTYPE1_RESET __SHIFTIN(3, SC1100_WDCNFG_WDTYPE1_MASK)

sys/arch/i386/pci/geodewdg.c

135

wdcnfg |= __SHIFTIN(sc->sc_prescale, SC1100_WDCNFG_WDPRES_MASK);

sys/arch/luna68k/include/pmap.h

25

__SHIFTIN(0x3f,TT30_LAM) | \

sys/arch/luna68k/include/pmap.h

27

__SHIFTIN(4,TT30_FCBASE) | \

sys/arch/luna68k/include/pmap.h

28

__SHIFTIN(3,TT30_FCMASK))

sys/arch/luna68k/include/pmap.h

30

__SHIFTIN(0x7f,TT30_LAM) | \

sys/arch/luna68k/include/pmap.h

32

__SHIFTIN(4,TT30_FCBASE) | \

sys/arch/luna68k/include/pmap.h

33

__SHIFTIN(3,TT30_FCMASK))

sys/arch/luna68k/include/pmap.h

36

__SHIFTIN(0x3f,TTR40_LAM) | \

sys/arch/luna68k/include/pmap.h

40

__SHIFTIN(0x7f,TTR40_LAM) | \

sys/arch/m68k/include/mmu_30.h

88

#define TT30_USERD __SHIFTIN(FC_USERD,TT30_FCBASE)

sys/arch/m68k/include/mmu_30.h

89

#define TT30_USERP __SHIFTIN(FC_USERP,TT30_FCBASE)

sys/arch/m68k/include/mmu_30.h

90

#define TT30_SUPERD __SHIFTIN(FC_SUPERD,TT30_FCBASE)

sys/arch/m68k/include/mmu_30.h

91

#define TT30_SUPERP __SHIFTIN(FC_SUPERP,TT30_FCBASE)

sys/arch/m68k/include/mmu_40.h

110

#define UTE40_INVALID __SHIFTIN(0, UTE40_UDT)

sys/arch/m68k/include/mmu_40.h

111

#define UTE40_RESIDENT __SHIFTIN(2, UTE40_UDT)

sys/arch/m68k/include/mmu_40.h

150

#define PTE40_CM_WT __SHIFTIN(0, PTE40_CM)

sys/arch/m68k/include/mmu_40.h

151

#define PTE40_CM_CB __SHIFTIN(1, PTE40_CM)

sys/arch/m68k/include/mmu_40.h

152

#define PTE40_CM_NC_SER __SHIFTIN(2, PTE40_CM)

sys/arch/m68k/include/mmu_40.h

153

#define PTE40_CM_NC __SHIFTIN(3, PTE40_CM)

sys/arch/m68k/include/mmu_40.h

155

#define PTE40_INVALID __SHIFTIN(0, PTE40_PDT)

sys/arch/m68k/include/mmu_40.h

156

#define PTE40_RESIDENT __SHIFTIN(1, PTE40_PDT)

sys/arch/m68k/include/mmu_40.h

157

#define PTE40_INDIRECT __SHIFTIN(2, PTE40_PDT)

sys/arch/m68k/include/mmu_40.h

193

#define TTR40_USER __SHIFTIN(0, TTR40_SFIELD)

sys/arch/m68k/include/mmu_40.h

194

#define TTR40_SUPER __SHIFTIN(1, TTR40_SFIELD)

sys/arch/m68k/include/mmu_40.h

195

#define TTR40_BOTH __SHIFTIN(2, TTR40_SFIELD)

sys/arch/m68k/include/mmu_51.h

227

#define TCR51_PS_256 __SHIFTIN(0x8, TCR51_PS)

sys/arch/m68k/include/mmu_51.h

228

#define TCR51_PS_512 __SHIFTIN(0x9, TCR51_PS)

sys/arch/m68k/include/mmu_51.h

229

#define TCR51_PS_1K __SHIFTIN(0xa, TCR51_PS)

sys/arch/m68k/include/mmu_51.h

230

#define TCR51_PS_2K __SHIFTIN(0xb, TCR51_PS)

sys/arch/m68k/include/mmu_51.h

231

#define TCR51_PS_4K __SHIFTIN(0xc, TCR51_PS)

sys/arch/m68k/include/mmu_51.h

232

#define TCR51_PS_8K __SHIFTIN(0xd, TCR51_PS)

sys/arch/m68k/include/mmu_51.h

233

#define TCR51_PS_16K __SHIFTIN(0xe, TCR51_PS)

sys/arch/m68k/include/mmu_51.h

234

#define TCR51_PS_32K __SHIFTIN(0xf, TCR51_PS)

sys/arch/m68k/include/pmap_68k.h

300

__SHIFTIN(PAGE_SHIFT, TCR51_PS) | \

sys/arch/m68k/include/pmap_68k.h

301

__SHIFTIN(LA2L_L1_NBITS, TCR51_TIA) | \

sys/arch/m68k/include/pmap_68k.h

302

__SHIFTIN(LA2L_L2_NBITS, TCR51_TIB))

sys/arch/m68k/include/pmap_68k.h

305

__SHIFTIN(PAGE_SHIFT, TCR51_PS) | \

sys/arch/m68k/include/pmap_68k.h

306

__SHIFTIN(LA40_L1_NBITS, TCR51_TIA) | \

sys/arch/m68k/include/pmap_68k.h

307

__SHIFTIN(LA40_L2_NBITS, TCR51_TIB) | \

sys/arch/m68k/include/pmap_68k.h

308

__SHIFTIN(LA40_L3_NBITS, TCR51_TIC))

sys/arch/m68k/include/pmap_68k.h

311

__SHIFTIN(PAGE_SHIFT - 12, TCR40_P))

sys/arch/m68k/include/pmap_motorola.h

163

__SHIFTIN(PAGE_SHIFT, TCR51_PS) | \

sys/arch/m68k/include/pmap_motorola.h

164

__SHIFTIN(TIA_SHIFT, TCR51_TIA) | \

sys/arch/m68k/include/pmap_motorola.h

165

__SHIFTIN(TIB_SHIFT, TCR51_TIB))

sys/arch/m68k/include/pmap_motorola.h

167

__SHIFTIN(PAGE_SHIFT - 12, TCR40_P))

sys/arch/mac68k/include/pmap.h

56

__SHIFTIN(0xff,TT30_LAM) | \

sys/arch/mips/adm5120/adm5120_extio.c

238

__SHIFTIN(2, ADM5120_MPMC_SWW_WWE));

sys/arch/mips/adm5120/adm5120_extio.c

245

__SHIFTIN(3, ADM5120_MPMC_SWO_WOE));

sys/arch/mips/adm5120/adm5120_extio.c

251

__SHIFTIN(26, ADM5120_MPMC_SWR_NMRW));

sys/arch/mips/adm5120/adm5120_extio.c

257

__SHIFTIN(29, ADM5120_MPMC_SWP_WPS));

sys/arch/mips/adm5120/adm5120_extio.c

263

__SHIFTIN(20, ADM5120_MPMC_SWWR_WWS));

sys/arch/mips/adm5120/adm5120_extio.c

269

__SHIFTIN(9, ADM5120_MPMC_SWT_WAITTURN));

sys/arch/mips/adm5120/dev/admgpio.c

102

mask = __SHIFTIN(1 << pin, ADM5120_GPIO0_OV);

sys/arch/mips/adm5120/dev/admgpio.c

67

mask = __SHIFTIN(1 << pin, ADM5120_GPIO0_OE);

sys/arch/mips/adm5120/dev/admgpio.c

85

mask = __SHIFTIN(1 << pin, ADM5120_GPIO0_IV);

sys/arch/mips/adm5120/dev/admgpio.c

87

mask = __SHIFTIN(1 << pin, ADM5120_GPIO0_OV);

sys/arch/mips/adm5120/dev/admpci.c

294

return __SHIFTIN(bus, ADMPCI_TAG_BUS_MASK) |

sys/arch/mips/adm5120/dev/admpci.c

295

__SHIFTIN(device, ADMPCI_TAG_DEVICE_MASK) |

sys/arch/mips/adm5120/dev/admpci.c

296

__SHIFTIN(function, ADMPCI_TAG_FUNCTION_MASK);

sys/arch/mips/adm5120/dev/admpci.c

331

*addrp = 0x80000000 | tag | __SHIFTIN(reg, ADMPCI_TAG_REGISTER_MASK);

sys/arch/mips/adm5120/dev/admwdog.c

73

wdog0 = __SHIFTIN(sc->sc_smw.smw_period * 100, ADM5120_WDOG_WTS_MASK) |

sys/arch/mips/adm5120/dev/admwdog.c

74

__SHIFTIN(1, ADM5120_WDOG_WT_MASK);

sys/arch/mips/adm5120/include/adm5120reg.h

265

#define ADM5120_MPMC_SC_MW_8B __SHIFTIN(0, ADM5120_MPMC_SC_MW_MASK)

sys/arch/mips/adm5120/include/adm5120reg.h

266

#define ADM5120_MPMC_SC_MW_16B __SHIFTIN(1, ADM5120_MPMC_SC_MW_MASK)

sys/arch/mips/adm5120/include/adm5120reg.h

267

#define ADM5120_MPMC_SC_MW_32B __SHIFTIN(2, ADM5120_MPMC_SC_MW_MASK)

sys/arch/mips/adm5120/include/adm5120reg.h

268

#define ADM5120_MPMC_SC_MW_RSVD __SHIFTIN(3, ADM5120_MPMC_SC_MW_MASK)

sys/arch/mips/atheros/ar5312_board.c

81

__SHIFTIN(1, AR5312_FLASHCTL_IDCY) |

sys/arch/mips/atheros/ar5312_board.c

82

__SHIFTIN(7, AR5312_FLASHCTL_WST1) |

sys/arch/mips/atheros/ar5312_board.c

83

__SHIFTIN(7, AR5312_FLASHCTL_WST2);

sys/arch/mips/atheros/dev/ehci_arbus.c

60

#define USBMODE_CM_IDLE __SHIFTIN(0,USBMODE_CM) /* Idle (both) */

sys/arch/mips/atheros/dev/ehci_arbus.c

61

#define USBMODE_CM_DEVICE __SHIFTIN(2,USBMODE_CM) /* Device Controller */

sys/arch/mips/atheros/dev/ehci_arbus.c

62

#define USBMODE_CM_HOST __SHIFTIN(3,USBMODE_CM) /* Host Controller */

sys/arch/mips/atheros/include/ar9344reg.h

302

#define AR7100_PCI_LCL_CFG_CMD_READ __SHIFTIN(0, AR7100_PCI_LCL_CFG_CMD_CMD)

sys/arch/mips/atheros/include/ar9344reg.h

303

#define AR7100_PCI_LCL_CFG_CMD_WRITE __SHIFTIN(1, AR7100_PCI_LCL_CFG_CMD_CMD)

sys/arch/mips/cavium/dev/octeon_dwctwo.c

216

clk |= __SHIFTIN(0x4, USBN_CLK_CTL_DIVIDE) | /* XXXXXX magic 0x4 */

sys/arch/mips/cavium/dev/octeon_dwctwo.c

217

__SHIFTIN(0x0, USBN_CLK_CTL_DIVIDE2);

sys/arch/mips/cavium/dev/octeon_dwctwo.c

235

clk |= __SHIFTIN(0x4, USBN_CLK_CTL_DIVIDE); /* XXXXXX magic 0x4 */

sys/arch/mips/cavium/dev/octeon_fau.c

53

__SHIFTIN(args, OCTEON_ADDR_OFFSET);

sys/arch/mips/cavium/dev/octeon_fau.c

62

__SHIFTIN(args, OCTEON_ADDR_OFFSET);

sys/arch/mips/cavium/dev/octeon_fau.c

81

__SHIFTIN(incval, POW_LOAD_INCVAL) |

sys/arch/mips/cavium/dev/octeon_fau.c

82

__SHIFTIN(tagwait, POW_LOAD_TAGWAIT) |

sys/arch/mips/cavium/dev/octeon_fau.c

83

__SHIFTIN(reg, POW_LOAD_REG);

sys/arch/mips/cavium/dev/octeon_fau.c

95

uint64_t args = POW_STORE_NOADD | __SHIFTIN(reg, POW_STORE_REG);

sys/arch/mips/cavium/dev/octeon_fauvar.h

109

__SHIFTIN(incval, POW_IOBDMA_INCVAL) |

sys/arch/mips/cavium/dev/octeon_fauvar.h

110

__SHIFTIN(tagwait, POW_IOBDMA_TAGWAIT) |

sys/arch/mips/cavium/dev/octeon_fauvar.h

111

__SHIFTIN(size, POW_IOBDMA_SIZE) |

sys/arch/mips/cavium/dev/octeon_fauvar.h

112

__SHIFTIN(reg, POW_IOBDMA_REG);

sys/arch/mips/cavium/dev/octeon_fpavar.h

119

__SHIFTIN(addr, FPA_OPS_STORE_ADDR);

sys/arch/mips/cavium/dev/octeon_fpavar.h

123

__SHIFTIN(dwbcount, FPA_OPS_STORE_DATA_DWBCOUNT));

sys/arch/mips/cavium/dev/octeon_gmx.c

1027

__SHIFTIN((1600 * cpu_freq_mhz) >> 10, PCS_LINK_TIMER_COUNT_MASK));

sys/arch/mips/cavium/dev/octeon_gmx.c

438

CLR(ovr_bp, __SHIFTIN(__BIT(index), TX_OVR_BP_EN));

sys/arch/mips/cavium/dev/octeon_gmx.c

439

SET(ovr_bp, __SHIFTIN(__BIT(index), TX_OVR_BP_BP));

sys/arch/mips/cavium/dev/octeon_gmx.c

441

SET(ovr_bp, __SHIFTIN(__BIT(index), TX_OVR_BP_IGN_FULL));

sys/arch/mips/cavium/dev/octeon_gmx.c

443

SET(ovr_bp, __SHIFTIN(__BIT(index), TX_OVR_BP_EN));

sys/arch/mips/cavium/dev/octeon_gmx.c

444

CLR(ovr_bp, __SHIFTIN(__BIT(index), TX_OVR_BP_BP));

sys/arch/mips/cavium/dev/octeon_gmx.c

446

SET(ovr_bp, __SHIFTIN(__BIT(index), TX_OVR_BP_IGN_FULL));

sys/arch/mips/cavium/dev/octeon_gmx.c

661

ctl |= __SHIFTIN(RXN_ADR_CTL_MCST_ACCEPT, RXN_ADR_CTL_MCST);

sys/arch/mips/cavium/dev/octeon_gmx.c

666

ctl |= __SHIFTIN(RXN_ADR_CTL_MCST_AFCAM, RXN_ADR_CTL_MCST);

sys/arch/mips/cavium/dev/octeon_gmx.c

671

ctl |= __SHIFTIN(RXN_ADR_CTL_MCST_REJECT, RXN_ADR_CTL_MCST);

sys/arch/mips/cavium/dev/octeon_ipd.c

135

__SHIFTIN(IPD_CTL_STATUS_OPC_MODE_ALL, IPD_CTL_STATUS_OPC_MODE));

sys/arch/mips/cavium/dev/octeon_pip.c

221

SET(prt_cfg, __SHIFTIN(sc->sc_port, PIP_PRT_CFGN_QOS));

sys/arch/mips/cavium/dev/octeon_pip.c

241

SET(prt_tag, __SHIFTIN(PIP_PRT_TAGN_TCP6_TAG_ORDERED, PIP_PRT_TAGN_TCP6_TAG));

sys/arch/mips/cavium/dev/octeon_pip.c

242

SET(prt_tag, __SHIFTIN(PIP_PRT_TAGN_TCP4_TAG_ORDERED, PIP_PRT_TAGN_TCP4_TAG));

sys/arch/mips/cavium/dev/octeon_pip.c

243

SET(prt_tag, __SHIFTIN(PIP_PRT_TAGN_IP6_TAG_ORDERED, PIP_PRT_TAGN_IP6_TAG));

sys/arch/mips/cavium/dev/octeon_pip.c

244

SET(prt_tag, __SHIFTIN(PIP_PRT_TAGN_IP4_TAG_ORDERED, PIP_PRT_TAGN_IP4_TAG));

sys/arch/mips/cavium/dev/octeon_pip.c

245

SET(prt_tag, __SHIFTIN(PIP_PRT_TAGN_NON_TAG_ORDERED, PIP_PRT_TAGN_NON_TAG));

sys/arch/mips/cavium/dev/octeon_pko.c

113

SET(mem_queue_qos, __SHIFTIN(sc->sc_port, PKO_MEM_QUEUE_QOS_PID));

sys/arch/mips/cavium/dev/octeon_pko.c

114

SET(mem_queue_qos, __SHIFTIN(sc->sc_port, PKO_MEM_QUEUE_QOS_QID));

sys/arch/mips/cavium/dev/octeon_pko.c

142

SET(mem_queue_ptrs, __SHIFTIN(0, PKO_MEM_QUEUE_PTRS_IDX));

sys/arch/mips/cavium/dev/octeon_pko.c

143

SET(mem_queue_ptrs, __SHIFTIN(sc->sc_port, PKO_MEM_QUEUE_PTRS_PID));

sys/arch/mips/cavium/dev/octeon_pko.c

144

SET(mem_queue_ptrs, __SHIFTIN(sc->sc_port, PKO_MEM_QUEUE_PTRS_QID));

sys/arch/mips/cavium/dev/octeon_pko.c

145

SET(mem_queue_ptrs, __SHIFTIN(0xff, PKO_MEM_QUEUE_PTRS_QOS_MASK));

sys/arch/mips/cavium/dev/octeon_pko.c

146

SET(mem_queue_ptrs, __SHIFTIN(buf_ptr, PKO_MEM_QUEUE_PTRS_BUF_PTR));

sys/arch/mips/cavium/dev/octeon_pko.c

96

SET(reg_cmd_buf, __SHIFTIN(sc->sc_cmd_buf_pool, PKO_REG_CMD_BUF_POOL));

sys/arch/mips/cavium/dev/octeon_pko.c

97

SET(reg_cmd_buf, __SHIFTIN(sc->sc_cmd_buf_size, PKO_REG_CMD_BUF_SIZE));

sys/arch/mips/cavium/dev/octeon_pkovar.h

100

__SHIFTIN(s0, PKO_CMD_WORD0_S0) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

101

__SHIFTIN(reg0, PKO_CMD_WORD0_REG0) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

102

__SHIFTIN(le, PKO_CMD_WORD0_LE) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

103

__SHIFTIN(n2, PKO_CMD_WORD0_N2) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

104

__SHIFTIN(q, PKO_CMD_WORD0_Q) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

105

__SHIFTIN(r, PKO_CMD_WORD0_R) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

106

__SHIFTIN(g, PKO_CMD_WORD0_G) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

107

__SHIFTIN(ipoffp1, PKO_CMD_WORD0_IPOFFP1) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

108

__SHIFTIN(ii, PKO_CMD_WORD0_II) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

109

__SHIFTIN(df, PKO_CMD_WORD0_DF) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

110

__SHIFTIN(segs, PKO_CMD_WORD0_SEGS) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

111

__SHIFTIN(totalbytes, PKO_CMD_WORD0_TOTALBYTES);

sys/arch/mips/cavium/dev/octeon_pkovar.h

120

__SHIFTIN(i, PKO_CMD_WORD1_I) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

121

__SHIFTIN(back, PKO_CMD_WORD1_BACK) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

122

__SHIFTIN(pool, PKO_CMD_WORD1_POOL) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

123

__SHIFTIN(size, PKO_CMD_WORD1_SIZE) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

124

__SHIFTIN(addr, PKO_CMD_WORD1_ADDR);

sys/arch/mips/cavium/dev/octeon_pkovar.h

150

__SHIFTIN(pid, PKO_DOORBELL_WRITE_PID) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

151

__SHIFTIN(qid, PKO_DOORBELL_WRITE_QID);

sys/arch/mips/cavium/dev/octeon_pkovar.h

152

value = __SHIFTIN(wdc, PKO_DOORBELL_WRITE_WDC);

sys/arch/mips/cavium/dev/octeon_pkovar.h

96

__SHIFTIN(sz1, PKO_CMD_WORD0_SZ1) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

97

__SHIFTIN(sz0, PKO_CMD_WORD0_SZ0) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

98

__SHIFTIN(s1, PKO_CMD_WORD0_S1) |

sys/arch/mips/cavium/dev/octeon_pkovar.h

99

__SHIFTIN(reg1, PKO_CMD_WORD0_REG1) |

sys/arch/mips/cavium/dev/octeon_pow.c

71

__SHIFTIN(tc_thr, POW_WQ_INT_THRX_TC_THR) |

sys/arch/mips/cavium/dev/octeon_pow.c

72

__SHIFTIN(ds_thr, POW_WQ_INT_THRX_DS_THR) |

sys/arch/mips/cavium/dev/octeon_pow.c

73

__SHIFTIN(iq_thr, POW_WQ_INT_THRX_IQ_THR);

sys/arch/mips/cavium/dev/octeon_powvar.h

162

__SHIFTIN(addr, POW_PHY_ADDR_STORE_ADDR);

sys/arch/mips/cavium/dev/octeon_powvar.h

166

__SHIFTIN(no_sched, POW_STORE_DATA_NO_SCHED) |

sys/arch/mips/cavium/dev/octeon_powvar.h

167

__SHIFTIN(index, POW_STORE_DATA_INDEX) |

sys/arch/mips/cavium/dev/octeon_powvar.h

168

__SHIFTIN(op, POW_STORE_DATA_OP) |

sys/arch/mips/cavium/dev/octeon_powvar.h

169

__SHIFTIN(qos, POW_STORE_DATA_QOS) |

sys/arch/mips/cavium/dev/octeon_powvar.h

170

__SHIFTIN(grp, POW_STORE_DATA_GRP) |

sys/arch/mips/cavium/dev/octeon_powvar.h

171

__SHIFTIN(type, POW_STORE_DATA_TYPE) |

sys/arch/mips/cavium/dev/octeon_powvar.h

172

__SHIFTIN(tag, POW_STORE_DATA_TAG);

sys/arch/mips/cavium/dev/octeon_powvar.h

401

wq_int_pc = __SHIFTIN(pc_thr, POW_WQ_INT_PC_PC_THR);

sys/arch/mips/cavium/dev/octeon_rnm.c

325

ctl |= __SHIFTIN(rogroup, RNM_CTL_STATUS_ENT_SEL_MASK);

sys/arch/mips/cavium/dev/octeon_smi.c

188

__SHIFTIN(0x4, SMI_CLK_SAMPLE) | /* XXX magic 0x4 */

sys/arch/mips/cavium/dev/octeon_smi.c

189

__SHIFTIN(0x64, SMI_CLK_PHASE); /* XXX magic 0x64 */

sys/arch/mips/cavium/dev/octeon_smi.c

201

__SHIFTIN(SMI_CMD_PHY_OP_READ, SMI_CMD_PHY_OP) |

sys/arch/mips/cavium/dev/octeon_smi.c

202

__SHIFTIN(phy_addr, SMI_CMD_PHY_ADR) |

sys/arch/mips/cavium/dev/octeon_smi.c

203

__SHIFTIN(reg, SMI_CMD_REG_ADR));

sys/arch/mips/cavium/dev/octeon_smi.c

233

__SHIFTIN(SMI_CMD_PHY_OP_WRITE, SMI_CMD_PHY_OP) |

sys/arch/mips/cavium/dev/octeon_smi.c

234

__SHIFTIN(phy_addr, SMI_CMD_PHY_ADR) |

sys/arch/mips/cavium/dev/octeon_smi.c

235

__SHIFTIN(reg, SMI_CMD_REG_ADR));

sys/arch/mips/cavium/dev/octeon_twsi.c

243

__SHIFTIN(MIO_TWS_SW_TWSI_OP_FOUR, MIO_TWS_SW_TWSI_OP) |

sys/arch/mips/cavium/dev/octeon_twsi.c

245

__SHIFTIN(addr, MIO_TWS_SW_TWSI_A);

sys/arch/mips/cavium/dev/octeon_twsi.c

255

__SHIFTIN(MIO_TWS_SW_TWSI_OP_ONE, MIO_TWS_SW_TWSI_OP) |

sys/arch/mips/cavium/dev/octeon_twsi.c

257

__SHIFTIN(addr, MIO_TWS_SW_TWSI_A);

sys/arch/mips/cavium/dev/octeon_twsi.c

287

__SHIFTIN(MIO_TWS_SW_TWSI_OP_FOUR, MIO_TWS_SW_TWSI_OP) |

sys/arch/mips/cavium/dev/octeon_twsi.c

288

__SHIFTIN(addr, MIO_TWS_SW_TWSI_A) |

sys/arch/mips/cavium/dev/octeon_twsi.c

289

__SHIFTIN(_BUFTOLE32(&buf[len - 1 - resid]), MIO_TWS_SW_TWSI_D);

sys/arch/mips/cavium/dev/octeon_twsi.c

297

__SHIFTIN(MIO_TWS_SW_TWSI_OP_ONE, MIO_TWS_SW_TWSI_OP) |

sys/arch/mips/cavium/dev/octeon_twsi.c

298

__SHIFTIN(addr, MIO_TWS_SW_TWSI_A) |

sys/arch/mips/cavium/dev/octeon_twsi.c

299

__SHIFTIN(buf[len - 1 - resid], MIO_TWS_SW_TWSI_D);

sys/arch/mips/cavium/dev/octeon_twsi.c

382

__SHIFTIN(MIO_TWS_SW_TWSI_OP_EXTEND, MIO_TWS_SW_TWSI_OP) |

sys/arch/mips/cavium/dev/octeon_twsi.c

383

__SHIFTIN(addr, MIO_TWS_SW_TWSI_A) |

sys/arch/mips/cavium/dev/octeon_twsi.c

384

__SHIFTIN(eop_ia, MIO_TWS_SW_TWSI_EOP_IA);

sys/arch/mips/cavium/dev/octeon_twsi.c

397

__SHIFTIN(MIO_TWS_SW_TWSI_OP_EXTEND, MIO_TWS_SW_TWSI_OP) |

sys/arch/mips/cavium/dev/octeon_twsi.c

398

__SHIFTIN(addr, MIO_TWS_SW_TWSI_A_SHIFT) |

sys/arch/mips/cavium/dev/octeon_twsi.c

399

__SHIFTIN(eop_ia, MIO_TWS_SW_TWSI_EOP_IA) |

sys/arch/mips/cavium/dev/octeon_twsi.c

400

__SHIFTIN(_BUFTOLE32(&buf[len - 1 - resid]), MIO_TWS_SW_TWSI_D);

sys/arch/mips/cavium/dev/octeon_xhci.c

333

val |= __SHIFTIN(XCTL_SHIM_ENDIAN_BIG, XCTL_SHIM_CFG_DMA_BYTE_SWAP);

sys/arch/mips/cavium/dev/octeon_xhci.c

334

val |= __SHIFTIN(XCTL_SHIM_ENDIAN_BIG, XCTL_SHIM_CFG_CSR_BYTE_SWAP);

sys/arch/mips/cavium/octeon_cpunode.c

406

wdog |= __SHIFTIN(3, CIU_WDOGX_MODE);

sys/arch/mips/cavium/octeon_cpunode.c

407

wdog |= __SHIFTIN(wdog_len >> 16, CIU_WDOGX_LEN);

sys/arch/mips/cavium/octeonreg.h

126

__SHIFTIN((scr), IOBDMA_SCRADDR) | \

sys/arch/mips/cavium/octeonreg.h

127

__SHIFTIN((len), IOBDMA_LEN) | \

sys/arch/mips/cavium/octeonreg.h

128

__SHIFTIN((offset), IOBDMA_OFFSET))

sys/arch/mips/cavium/octeonreg.h

75

__SHIFTIN((major), OCTEON_ADDR_MAJOR_DID) | \

sys/arch/mips/cavium/octeonreg.h

76

__SHIFTIN((sub), OCTEON_ADDR_SUB_DID))

sys/arch/mips/ralink/ralink_com.c

360

r |= __SHIFTIN(0, ra_uart2gpiomode(rtsc->sc_addr));

sys/arch/mips/ralink/ralink_com.c

420

r |= __SHIFTIN(1, ra_uart2gpiomode(RALINK_CONADDR));

sys/arch/mips/ralink/ralink_com.c

426

r |= __SHIFTIN(0, ra_uart2gpiomode(RALINK_CONADDR));

sys/arch/mips/ralink/ralink_gpio.c

826

r |= __SHIFTIN(gpio_mux_map[i].mode,

sys/arch/news68k/include/pmap.h

25

__SHIFTIN(0x1f,TT30_LAM) | \

sys/arch/news68k/include/pmap.h

27

__SHIFTIN(4,TT30_FCBASE) | \

sys/arch/news68k/include/pmap.h

28

__SHIFTIN(3,TT30_FCMASK))

sys/arch/news68k/include/pmap.h

31

__SHIFTIN(0x1f,TT30_LAM) | \

sys/arch/news68k/include/pmap.h

33

__SHIFTIN(4,TT30_FCBASE) | \

sys/arch/news68k/include/pmap.h

34

__SHIFTIN(3,TT30_FCMASK))

sys/arch/next68k/include/pmap.h

34

__SHIFTIN(0x03,TTR40_LAM) | \

sys/arch/next68k/include/pmap.h

46

__SHIFTIN(0x03,TT30_LAM) | \

sys/arch/next68k/include/pmap.h

48

__SHIFTIN(4,TT30_FCBASE) | \

sys/arch/next68k/include/pmap.h

49

__SHIFTIN(3,TT30_FCMASK))

sys/arch/or1k/include/spr.h

38

#define SPR_MAKE(g,r) (__SHIFTIN((g), SPR_GROUP)|__SHIFTIN((r), SPR_REG))

sys/arch/powerpc/booke/dev/e500wdog.c

129

tcr |= __SHIFTIN(wp, TCR_WP) | __SHIFTIN(wp >> 2, TCR_WPEXT);

sys/arch/powerpc/booke/dev/pq3ddrc.c

88

sc->sc_ev_sbe.ev_count += __SHIFTIN(v, ERR_SBE_SBEC);

sys/arch/powerpc/booke/dev/pq3ehci.c

65

#define USBMODE_CM_IDLE __SHIFTIN(0,USBMODE_CM) /* Idle (both) */

sys/arch/powerpc/booke/dev/pq3ehci.c

66

#define USBMODE_CM_DEVICE __SHIFTIN(2,USBMODE_CM) /* Device Controller */

sys/arch/powerpc/booke/dev/pq3ehci.c

67

#define USBMODE_CM_HOST __SHIFTIN(3,USBMODE_CM) /* Host Controller */

sys/arch/powerpc/booke/dev/pq3etsec.c

417

__SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG));

sys/arch/powerpc/booke/dev/pq3etsec.c

449

__SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG));

sys/arch/powerpc/booke/dev/pq3nandfcm.c

132

lbc_write_4(sc->sc_obio, FCR, __SHIFTIN(command, FCR_CMD0));

sys/arch/powerpc/booke/dev/pq3nandfcm.c

133

lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_CM0, FIR_OP0));

sys/arch/powerpc/booke/dev/pq3nandfcm.c

145

lbc_write_4(sc->sc_obio, MDR, __SHIFTIN(address, MDR_AS0));

sys/arch/powerpc/booke/dev/pq3nandfcm.c

146

lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_UA, FIR_OP0));

sys/arch/powerpc/booke/dev/pq3nandfcm.c

180

lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_RSW, FIR_OP0));

sys/arch/powerpc/booke/dev/pq3nandfcm.c

198

lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_WS, FIR_OP0));

sys/arch/powerpc/booke/dev/pq3nandfcm.c

216

lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_RBW, FIR_OP0));

sys/arch/powerpc/booke/dev/pq3nandfcm.c

258

lbc_write_4(sc->sc_obio, FIR, __SHIFTIN(FIR_OP_WB, FIR_OP0));

sys/arch/powerpc/booke/e500_tlb.c

1031

kxtlb->e_hwtlb.hwtlb_mas0 |= __SHIFTIN(kslot, MAS0_ESEL);

sys/arch/powerpc/booke/e500_tlb.c

1137

tmp_xtlb->e_hwtlb.hwtlb_mas0 |= __SHIFTIN(tmp_slot, MAS0_ESEL);

sys/arch/powerpc/booke/e500_tlb.c

1149

text_xtlb->e_hwtlb.hwtlb_mas0 |= __SHIFTIN(text_slot, MAS0_ESEL);

sys/arch/powerpc/booke/e500_tlb.c

1160

data_xtlb->e_hwtlb.hwtlb_mas0 |= __SHIFTIN(data_slot, MAS0_ESEL);

sys/arch/powerpc/booke/e500_tlb.c

326

MAS0_TLBSEL_TLB1 | __SHIFTIN(slot, MAS0_ESEL);

sys/arch/powerpc/booke/e500_tlb.c

337

KASSERT(xtlb->e_hwtlb.hwtlb_mas0 == (MAS0_TLBSEL_TLB1|__SHIFTIN(slot, MAS0_ESEL)));

sys/arch/powerpc/booke/e500_tlb.c

438

asid_lo = __SHIFTIN(asid_lo, MAS1_TID);

sys/arch/powerpc/booke/e500_tlb.c

439

asid_hi = __SHIFTIN(asid_hi, MAS1_TID);

sys/arch/powerpc/booke/e500_tlb.c

548

mtspr(SPR_MAS6, asid ? __SHIFTIN(asid, MAS6_SPID0) | MAS6_SAS : 0);

sys/arch/powerpc/booke/e500_tlb.c

806

xtlb->e_hwtlb.hwtlb_mas0 |= __SHIFTIN(slot, MAS0_ESEL);

sys/arch/powerpc/booke/pci/pq3pci.c

100

__SHIFTIN(field##_##value, PORDEVSR_##field), result), \

sys/arch/powerpc/booke/pci/pq3pci.c

102

__SHIFTIN(field##_##value, PORDEVSR_##field), result)

sys/arch/powerpc/booke/pci/pq3pci.c

106

__SHIFTIN(field##_##value, PORDEVSR_##field), result)

sys/arch/powerpc/booke/pci/pq3pci.c

75

__SHIFTIN(field##_##MPC8536##_##value, PORDEVSR_##field), result)

sys/arch/powerpc/booke/pci/pq3pci.c

78

__SHIFTIN(field##_##MPC8544##_##value, PORDEVSR_##field), result)

sys/arch/powerpc/booke/pci/pq3pci.c

81

__SHIFTIN(field##_##MPC8548##_##value, PORDEVSR_##field), result)

sys/arch/powerpc/booke/pci/pq3pci.c

84

__SHIFTIN(field##_##MPC8555##_##value, PORDEVSR_##field), result)

sys/arch/powerpc/booke/pci/pq3pci.c

87

__SHIFTIN(field##_##MPC8572##_##value, PORDEVSR_##field), result)

sys/arch/powerpc/booke/pci/pq3pci.c

881

|__SHIFTIN(30-__builtin_clz(pmemsize),PEXIWAR_IWS),

sys/arch/powerpc/booke/pci/pq3pci.c

90

__SHIFTIN(field##_##P20x0##_##value, PORDEVSR_##field), result), \

sys/arch/powerpc/booke/pci/pq3pci.c

911

|__SHIFTIN(ilog2(PCI_MEMSIZE)-1,PEXOWAR_OWS),

sys/arch/powerpc/booke/pci/pq3pci.c

92

__SHIFTIN(field##_##P20x0##_##value, PORDEVSR_##field), result)

sys/arch/powerpc/booke/pci/pq3pci.c

936

|__SHIFTIN(ilog2(PCI_IOSIZE)-1,PEXOWAR_OWS),

sys/arch/powerpc/booke/pci/pq3pci.c

95

__SHIFTIN(field##_##P20x0##_##value, PORDEVSR_##field), result), \

sys/arch/powerpc/booke/pci/pq3pci.c

97

__SHIFTIN(field##_##P20x0##_##value, PORDEVSR_##field), result)

sys/arch/powerpc/include/booke/e500reg.h

164

#define PEXOWAR_TC0 __SHIFTIN(0, PEXOWAR_TC)

sys/arch/powerpc/include/booke/e500reg.h

165

#define PEXOWAR_TC1 __SHIFTIN(1, PEXOWAR_TC)

sys/arch/powerpc/include/booke/e500reg.h

166

#define PEXOWAR_TC2 __SHIFTIN(2, PEXOWAR_TC)

sys/arch/powerpc/include/booke/e500reg.h

167

#define PEXOWAR_TC3 __SHIFTIN(3, PEXOWAR_TC)

sys/arch/powerpc/include/booke/e500reg.h

168

#define PEXOWAR_TC4 __SHIFTIN(4, PEXOWAR_TC)

sys/arch/powerpc/include/booke/e500reg.h

169

#define PEXOWAR_TC5 __SHIFTIN(5, PEXOWAR_TC)

sys/arch/powerpc/include/booke/e500reg.h

170

#define PEXOWAR_TC6 __SHIFTIN(6, PEXOWAR_TC)

sys/arch/powerpc/include/booke/e500reg.h

171

#define PEXOWAR_TC7 __SHIFTIN(7, PEXOWAR_TC)

sys/arch/powerpc/include/booke/e500reg.h

173

#define PEXOWAR_RTT_CONF __SHIFTIN(2, PEXOWAR_RTT) /* PCIEX only */

sys/arch/powerpc/include/booke/e500reg.h

174

#define PEXOWAR_RTT_MEM __SHIFTIN(4, PEXOWAR_RTT)

sys/arch/powerpc/include/booke/e500reg.h

175

#define PEXOWAR_RTT_IO __SHIFTIN(8, PEXOWAR_RTT)

sys/arch/powerpc/include/booke/e500reg.h

177

#define PEXOWAR_WTT_CONF __SHIFTIN(2, PEXOWAR_WTT) /* PCIEX only */

sys/arch/powerpc/include/booke/e500reg.h

178

#define PEXOWAR_WTT_MEM __SHIFTIN(4, PEXOWAR_WTT)

sys/arch/powerpc/include/booke/e500reg.h

179

#define PEXOWAR_WTT_IO __SHIFTIN(8, PEXOWAR_WTT)

sys/arch/powerpc/include/booke/e500reg.h

186

#define PEXIWAR_TRGT_PCI1 __SHIFTIN(0, PEXIWAR_TRGT)

sys/arch/powerpc/include/booke/e500reg.h

187

#define PEXIWAR_TRGT_PCI2 __SHIFTIN(1, PEXIWAR_TRGT)

sys/arch/powerpc/include/booke/e500reg.h

188

#define PEXIWAR_TRGT_PCIEX __SHIFTIN(2, PEXIWAR_TRGT)

sys/arch/powerpc/include/booke/e500reg.h

189

#define PEXIWAR_TRGT_SRIO __SHIFTIN(12, PEXIWAR_TRGT)

sys/arch/powerpc/include/booke/e500reg.h

190

#define PEXIWAR_TRGT_LOCALMEM __SHIFTIN(15, PEXIWAR_TRGT)

sys/arch/powerpc/include/booke/e500reg.h

192

#define PEXIWAR_RTT_MEM __SHIFTIN(4, PEXIWAR_RTT)

sys/arch/powerpc/include/booke/e500reg.h

193

#define PEXIWAR_RTT_MEM_NOSNOOP __SHIFTIN(4, PEXIWAR_RTT)

sys/arch/powerpc/include/booke/e500reg.h

194

#define PEXIWAR_RTT_MEM_SNOOP __SHIFTIN(5, PEXIWAR_RTT)

sys/arch/powerpc/include/booke/e500reg.h

195

#define PEXIWAR_RTT_MEM_ULCKL2 __SHIFTIN(7, PEXIWAR_RTT)

sys/arch/powerpc/include/booke/e500reg.h

197

#define PEXIWAR_WTT_MEM_NOSNOOP __SHIFTIN(4, PEXIWAR_WTT)

sys/arch/powerpc/include/booke/e500reg.h

198

#define PEXIWAR_WTT_MEM_SNOOP __SHIFTIN(5, PEXIWAR_WTT)

sys/arch/powerpc/include/booke/e500reg.h

199

#define PEXIWAR_WTT_MEM_ALLOL2 __SHIFTIN(6, PEXIWAR_WTT)

sys/arch/powerpc/include/booke/e500reg.h

200

#define PEXIWAR_WTT_MEM_ALCKL2 __SHIFTIN(7, PEXIWAR_WTT)

sys/arch/powerpc/include/booke/e500reg.h

661

#define BR_PS_8BIT __SHIFTIN(1,BR_PS)

sys/arch/powerpc/include/booke/e500reg.h

662

#define BR_PS_16BIT __SHIFTIN(2,BR_PS)

sys/arch/powerpc/include/booke/e500reg.h

663

#define BR_PS_32BIT __SHIFTIN(3,BR_PS)

sys/arch/powerpc/include/booke/e500reg.h

665

#define BR_DECC_NONE __SHIFTIN(0,BR_DECC)

sys/arch/powerpc/include/booke/e500reg.h

666

#define BR_DECC_PARITY __SHIFTIN(1,BR_DECC)

sys/arch/powerpc/include/booke/e500reg.h

667

#define BR_DECC_RMWPAR __SHIFTIN(2,BR_DECC)

sys/arch/powerpc/include/booke/e500reg.h

670

#define BR_MSEL_GPCM __SHIFTIN(0,BR_MSEL)

sys/arch/powerpc/include/booke/e500reg.h

671

#define BR_MSEL_FCM __SHIFTIN(1,BR_MSEL)

sys/arch/powerpc/include/booke/e500reg.h

672

#define BR_MSEL_SDRAM __SHIFTIN(3,BR_MSEL)

sys/arch/powerpc/include/booke/e500reg.h

673

#define BR_MSEL_UPMA __SHIFTIN(4,BR_MSEL)

sys/arch/powerpc/include/booke/e500reg.h

674

#define BR_MSEL_UPMB __SHIFTIN(5,BR_MSEL)

sys/arch/powerpc/include/booke/e500reg.h

675

#define BR_MSEL_UPMC __SHIFTIN(6,BR_MSEL)

sys/arch/powerpc/include/booke/e500reg.h

677

#define BR_ATOM_NONE __SHIFTIN(0,BR_ATOM)

sys/arch/powerpc/include/booke/e500reg.h

678

#define BR_ATOM_RAWA __SHIFTIN(1,BR_ATOM)

sys/arch/powerpc/include/booke/e500reg.h

679

#define BR_ATOM_WARA __SHIFTIN(2,BR_ATOM)

sys/arch/powerpc/include/booke/e500reg.h

825

#define MXMR_OP_NORMAL __SHIFTIN(0, MXMR_OP) /* Normal Operation */

sys/arch/powerpc/include/booke/e500reg.h

826

#define MXMR_OP_WRITE __SHIFTIN(1, MXMR_OP) /* Write to UPM memory */

sys/arch/powerpc/include/booke/e500reg.h

827

#define MXMR_OP_READ __SHIFTIN(2, MXMR_OP) /* Read from UPM memory */

sys/arch/powerpc/include/booke/e500reg.h

828

#define MXMR_OP_RUN __SHIFTIN(3, MXMR_OP) /* Run Pattern */

sys/arch/powerpc/include/booke/e500reg.h

832

#define MXMR_DS_1CYCLE __SHIFTIN(0,MXMR_DS)

sys/arch/powerpc/include/booke/e500reg.h

833

#define MXMR_DS_2CYCLE __SHIFTIN(1,MXMR_DS)

sys/arch/powerpc/include/booke/e500reg.h

834

#define MXMR_DS_3CYCLE __SHIFTIN(2,MXMR_DS)

sys/arch/powerpc/include/booke/e500reg.h

835

#define MXMR_DS_4CYCLE __SHIFTIN(3,MXMR_DS)

sys/arch/powerpc/include/booke/e500reg.h

837

#define MXMR_G0CL_A12 __SHIFTIN(0,MXMR_G0CL)

sys/arch/powerpc/include/booke/e500reg.h

838

#define MXMR_G0CL_A11 __SHIFTIN(1,MXMR_G0CL)

sys/arch/powerpc/include/booke/e500reg.h

839

#define MXMR_G0CL_A10 __SHIFTIN(2,MXMR_G0CL)

sys/arch/powerpc/include/booke/e500reg.h

840

#define MXMR_G0CL_A9 __SHIFTIN(3,MXMR_G0CL)

sys/arch/powerpc/include/booke/e500reg.h

841

#define MXMR_G0CL_A8 __SHIFTIN(4,MXMR_G0CL)

sys/arch/powerpc/include/booke/e500reg.h

842

#define MXMR_G0CL_A7 __SHIFTIN(5,MXMR_G0CL)

sys/arch/powerpc/include/booke/e500reg.h

843

#define MXMR_G0CL_A6 __SHIFTIN(6,MXMR_G0CL)

sys/arch/powerpc/include/booke/e500reg.h

844

#define MXMR_G0CL_A5 __SHIFTIN(7,MXMR_G0CL)

sys/arch/powerpc/include/booke/etsecreg.h

194

#define TCTRL_TXSCHED_SINGLE __SHIFTIN(0,TCTRL_TXSCHED)

sys/arch/powerpc/include/booke/etsecreg.h

195

#define TCTRL_TXSCHED_PRIO __SHIFTIN(1,TCTRL_TXSCHED)

sys/arch/powerpc/include/booke/etsecreg.h

196

#define TCTRL_TXSCHED_MWRR __SHIFTIN(2,TCTRL_TXSCHED)

sys/arch/powerpc/include/booke/etsecreg.h

226

#define TXIC_ICFT_SET(n) __SHIFTIN((n),TXIC_ICFT)

sys/arch/powerpc/include/booke/etsecreg.h

228

#define TXIC_ICTT_SET(n) __SHIFTIN((n),TXIC_ICTT)

sys/arch/powerpc/include/booke/etsecreg.h

273

#define RCTRL_L2OFF_SET(n) __SHIFTIN((n),RCTRL_L2OFF)

sys/arch/powerpc/include/booke/etsecreg.h

284

#define RCTRL_PRSDEP_L4 __SHIFTIN(3,RCTRL_PRSDEP)

sys/arch/powerpc/include/booke/etsecreg.h

285

#define RCTRL_PRSDEP_L3 __SHIFTIN(2,RCTRL_PRSDEP)

sys/arch/powerpc/include/booke/etsecreg.h

286

#define RCTRL_PRSDEP_L2 __SHIFTIN(1,RCTRL_PRSDEP)

sys/arch/powerpc/include/booke/etsecreg.h

287

#define RCTRL_PRSDEP_OFF __SHIFTIN(0,RCTRL_PRSDEP)

sys/arch/powerpc/include/booke/etsecreg.h

292

#define RCTRL_DEFAULT (__SHIFTIN(2, RCTRL_PAL)|RCTRL_EMEN)

sys/arch/powerpc/include/booke/etsecreg.h

320

#define RXIC_ICFT_SET(n) __SHIFTIN((n),TXIC_ICFT)

sys/arch/powerpc/include/booke/etsecreg.h

322

#define RXIC_ICTT_SET(n) __SHIFTIN((n),TXIC_ICTT)

sys/arch/powerpc/include/booke/etsecreg.h

354

#define RQFCR_HASHTBL_Q __SHIFTIN(0,RQFCR_HASHTBL)

sys/arch/powerpc/include/booke/etsecreg.h

355

#define RQFCR_HASHTBL_0 __SHIFTIN(1,RQFCR_HASHTBL)

sys/arch/powerpc/include/booke/etsecreg.h

356

#define RQFCR_HASHTBL_1 __SHIFTIN(2,RQFCR_HASHTBL)

sys/arch/powerpc/include/booke/etsecreg.h

357

#define RQFCR_HASHTBL_2 __SHIFTIN(3,RQFCR_HASHTBL)

sys/arch/powerpc/include/booke/etsecreg.h

358

#define RQFCR_HASHTBL_3 __SHIFTIN(4,RQFCR_HASHTBL)

sys/arch/powerpc/include/booke/etsecreg.h

361

#define RQFCR_QUEUE_SET(n) __SHIFTIN((n),RQFCR_QUEUE)

sys/arch/powerpc/include/booke/etsecreg.h

366

#define RQFCR_CMP_EXACT __SHIFTIN(0,RQFCR_CMP)

sys/arch/powerpc/include/booke/etsecreg.h

367

#define RQFCR_CMP_MATCH __SHIFTIN(1,RQFCR_CMP)

sys/arch/powerpc/include/booke/etsecreg.h

368

#define RQFCR_CMP_NOEXACT __SHIFTIN(2,RQFCR_CMP)

sys/arch/powerpc/include/booke/etsecreg.h

369

#define RQFCR_CMP_NOMATCH __SHIFTIN(3,RQFCR_CMP)

sys/arch/powerpc/include/booke/etsecreg.h

444

#define MACCFG2_PRELEN_DEFAULT __SHIFTIN(7,MACCFG2_PRELEN)

sys/arch/powerpc/include/booke/etsecreg.h

446

#define MACCFG2_IFMODE_MII __SHIFTIN(1,MACCFG2_IFMODE)

sys/arch/powerpc/include/booke/etsecreg.h

447

#define MACCFG2_IFMODE_GMII __SHIFTIN(2,MACCFG2_IFMODE)

sys/arch/powerpc/include/booke/etsecreg.h

601

#define ATTR_ELCWT_L2 __SHIFTIN(2, ATTR_ELCWT)

sys/arch/powerpc/include/booke/etsecreg.h

603

#define ATTR_BDLWT_L2 __SHIFTIN(2, ATTR_BDLWT)

sys/arch/powerpc/include/booke/etsecreg.h

611

#define ATTRELI_DEFAULT (__SHIFTIN(72, ATTRELI_EL))

sys/arch/powerpc/include/booke/etsecreg.h

625

#define RQPRM_FBTHR_SET(n) __SHIFTIN((n),RQPRM_FBTHR)

sys/arch/powerpc/include/booke/etsecreg.h

627

#define RQPRM_LEN_SET(n) __SHIFTIN((n),RQPRM_LEN)

sys/arch/powerpc/include/booke/spr.h

287

#define TCR_WP_2_N(n) (__SHIFTIN((n), TCR_WP) | __SHIFTIN((n) >> 2, TCR_WPEXT))

sys/arch/riscv/fdt/clint_fdt.c

98

__SHIFTIN(hi, __BITS(63, 32)) |

sys/arch/riscv/fdt/clint_fdt.c

99

__SHIFTIN(lo, __BITS(31, 0));

sys/arch/riscv/fdt/pcihost_fdt.c

479

__SHIFTIN(pa->pa_bus, PHYS_HI_BUS) |

sys/arch/riscv/fdt/pcihost_fdt.c

480

__SHIFTIN(pa->pa_device, PHYS_HI_DEVICE) |

sys/arch/riscv/fdt/pcihost_fdt.c

481

__SHIFTIN(pa->pa_function, PHYS_HI_FUNCTION)

sys/arch/riscv/include/mutex.h

84

| __SHIFTIN(ipl, MTX_IPL);

sys/arch/riscv/include/pmap.h

264

__SHIFTIN(SATP_MODE_SV39, SATP_MODE) |

sys/arch/riscv/include/pmap.h

266

__SHIFTIN(SATP_MODE_SV32, SATP_MODE) |

sys/arch/riscv/include/pmap.h

268

__SHIFTIN(asid, SATP_ASID) |

sys/arch/riscv/include/pmap.h

269

__SHIFTIN(pmap->pm_md.md_ppn, SATP_PPN);

sys/arch/riscv/include/pte.h

72

#define PTE_PBMT_PMA __SHIFTIN(0, PTE_PBMT)

sys/arch/riscv/include/pte.h

73

#define PTE_PBMT_NC __SHIFTIN(1, PTE_PBMT)

sys/arch/riscv/include/pte.h

74

#define PTE_PBMT_IO __SHIFTIN(2, PTE_PBMT)

sys/arch/riscv/include/sysreg.h

237

#define SR_USER64 (SR_SPIE | __SHIFTIN(SR_UXL_64, SR_UXL))

sys/arch/riscv/include/sysreg.h

238

#define SR_USER32 (SR_SPIE | __SHIFTIN(SR_UXL_32, SR_UXL))

sys/arch/riscv/include/sysreg.h

298

__SHIFTIN(__hi0, __BITS(63, 32)) |

sys/arch/riscv/include/sysreg.h

299

__SHIFTIN(__lo0, __BITS(31, 0));

sys/arch/riscv/include/sysreg.h

338

satp |= __SHIFTIN(asid, SATP_ASID);

sys/arch/riscv/riscv/fpu.c

146

tf->tf_sr |= __SHIFTIN(SR_FS_CLEAN, SR_FS);

sys/arch/riscv/riscv/fpu.c

69

csr_sstatus_set(__SHIFTIN(SR_FS_CLEAN, SR_FS));

sys/arch/riscv/riscv/kobj_machdep.c

294

*bwhere = (*bwhere & ~mask) | __SHIFTIN(addend, mask);

sys/arch/riscv/riscv/kobj_machdep.c

347

__SHIFTIN(immA, __BIT(31)) |

sys/arch/riscv/riscv/kobj_machdep.c

348

__SHIFTIN(immB, __BITS(30, 25)) |

sys/arch/riscv/riscv/kobj_machdep.c

349

__SHIFTIN(immC, __BITS(11, 8)) |

sys/arch/riscv/riscv/kobj_machdep.c

350

__SHIFTIN(immD, __BIT(7));

sys/arch/riscv/riscv/kobj_machdep.c

369

__SHIFTIN(immA, __BIT(31)) |

sys/arch/riscv/riscv/kobj_machdep.c

370

__SHIFTIN(immB, __BITS(30, 21)) |

sys/arch/riscv/riscv/kobj_machdep.c

371

__SHIFTIN(immC, __BIT(20)) |

sys/arch/riscv/riscv/kobj_machdep.c

372

__SHIFTIN(immD, __BITS(19,12));

sys/arch/riscv/riscv/kobj_machdep.c

411

__SHIFTIN(immA, __BITS(31, 25)) |

sys/arch/riscv/riscv/kobj_machdep.c

412

__SHIFTIN(immB, __BITS(11, 7));

sys/arch/riscv/riscv/kobj_machdep.c

445

__SHIFTIN(immA, __BIT(31)) |

sys/arch/riscv/riscv/kobj_machdep.c

446

__SHIFTIN(immB, __BITS(30, 21)) |

sys/arch/riscv/riscv/kobj_machdep.c

447

__SHIFTIN(immC, __BIT(20)) |

sys/arch/riscv/riscv/kobj_machdep.c

448

__SHIFTIN(immD, __BITS(19,12));

sys/arch/riscv/riscv/kobj_machdep.c

480

__SHIFTIN(immA, __BIT(12)) |

sys/arch/riscv/riscv/kobj_machdep.c

481

__SHIFTIN(immB, __BITS(11, 10)) |

sys/arch/riscv/riscv/kobj_machdep.c

482

__SHIFTIN(immC, __BITS( 6, 5)) |

sys/arch/riscv/riscv/kobj_machdep.c

483

__SHIFTIN(immD, __BITS( 4, 3)) |

sys/arch/riscv/riscv/kobj_machdep.c

484

__SHIFTIN(immE, __BIT(2));

sys/arch/riscv/riscv/kobj_machdep.c

507

__SHIFTIN(immA, __BIT(12)) |

sys/arch/riscv/riscv/kobj_machdep.c

508

__SHIFTIN(immB, __BIT(11)) |

sys/arch/riscv/riscv/kobj_machdep.c

509

__SHIFTIN(immC, __BITS(10, 9)) |

sys/arch/riscv/riscv/kobj_machdep.c

510

__SHIFTIN(immD, __BIT(8)) |

sys/arch/riscv/riscv/kobj_machdep.c

511

__SHIFTIN(immE, __BIT(7)) |

sys/arch/riscv/riscv/kobj_machdep.c

512

__SHIFTIN(immF, __BIT(6)) |

sys/arch/riscv/riscv/kobj_machdep.c

513

__SHIFTIN(immG, __BITS(5, 3)) |

sys/arch/riscv/riscv/kobj_machdep.c

514

__SHIFTIN(immH, __BIT(2));

sys/arch/riscv/riscv/kobj_machdep.c

531

__SHIFTIN(immA, __BIT(12)) |

sys/arch/riscv/riscv/kobj_machdep.c

532

__SHIFTIN(immB, __BITS(6, 2));

sys/arch/riscv/starfive/jh7100_pinctrl.c

190

*val |= __SHIFTIN(ds, PAD_DRIVE_STRENGTH_MASK);

sys/arch/riscv/starfive/jh7100_pinctrl.c

220

*val |= __SHIFTIN(slew_rate, PAD_SLEW_RATE_MASK);

sys/arch/riscv/starfive/jh7100_pinctrl.c

295

__SHIFTIN(doutrev, GPO_DOUT_REVERSE) |

sys/arch/riscv/starfive/jh7100_pinctrl.c

296

__SHIFTIN(dout, GPO_DOUT_MASK);

sys/arch/riscv/starfive/jh7100_pinctrl.c

298

__SHIFTIN(doenrev, GPO_DOEN_REVERSE) |

sys/arch/riscv/starfive/jh7100_pinctrl.c

299

__SHIFTIN(doen, GPO_DOEN_MASK);

sys/arch/riscv/starfive/jh7110_pcie.c

156

__SHIFTIN((x), STG_SYSCON_AXI4_SLVL_PHY_AR_MASK)

sys/arch/riscv/starfive/jh7110_pcie.c

164

__SHIFTIN((x), STG_SYSCON_AXI4_SLVL_PHY_AW_MASK)

sys/arch/riscv/starfive/jh7110_pcie.c

194

__SHIFTIN(bus, ECAM_BUS_MASK) |

sys/arch/riscv/starfive/jh7110_pcie.c

195

__SHIFTIN(dev, ECAM_DEV_MASK) |

sys/arch/riscv/starfive/jh7110_pcie.c

196

__SHIFTIN(fn, ECAM_FUNC_MASK) |

sys/arch/riscv/starfive/jh7110_pcie.c

243

__SHIFTIN(bus, ECAM_BUS_MASK) |

sys/arch/riscv/starfive/jh7110_pcie.c

244

__SHIFTIN(dev, ECAM_DEV_MASK) |

sys/arch/riscv/starfive/jh7110_pcie.c

245

__SHIFTIN(fn, ECAM_FUNC_MASK) |

sys/arch/riscv/starfive/jh7110_pcie.c

268

__SHIFTIN(bus, ECAM_BUS_MASK) |

sys/arch/riscv/starfive/jh7110_pcie.c

269

__SHIFTIN(dev, ECAM_DEV_MASK) |

sys/arch/riscv/starfive/jh7110_pcie.c

270

__SHIFTIN(fn, ECAM_FUNC_MASK) |

sys/arch/riscv/starfive/jh7110_pcie.c

404

__SHIFTIN(2, STG_SYSCON_CKREF_SRC_MASK));

sys/arch/riscv/starfive/jh7110_pcie.c

440

__SHIFTIN(i, STG_SYSCON_AXI4_SLVL_PHY_AR_MASK));

sys/arch/riscv/starfive/jh7110_pcie.c

444

__SHIFTIN(i, STG_SYSCON_AXI4_SLVL_PHY_AW_MASK));

sys/arch/riscv/starfive/jh7110_pcie.c

518

__SHIFTIN(ilog2(sc->sc_cfg_size) - 1, PLDA_ATR_SIZE_MASK) |

sys/arch/riscv/starfive/jh7110_pcie.c

537

__SHIFTIN(be32toh(ranges[i + 1]), __BITS(63, 32)) |

sys/arch/riscv/starfive/jh7110_pcie.c

538

__SHIFTIN(be32toh(ranges[i + 2]), __BITS(31, 0));

sys/arch/riscv/starfive/jh7110_pcie.c

540

__SHIFTIN(be32toh(ranges[i + 3]), __BITS(63, 32)) |

sys/arch/riscv/starfive/jh7110_pcie.c

541

__SHIFTIN(be32toh(ranges[i + 4]), __BITS(31, 0));

sys/arch/riscv/starfive/jh7110_pcie.c

546

__SHIFTIN(ilog2(size) /* - 1 */, PLDA_ATR_SIZE_MASK) |

sys/arch/riscv/starfive/jh7110_pinctrl.c

110

#define JH7110_PADCFG_DS_2MA __SHIFTIN(0, JH7110_PADCFG_DS_MASK)

sys/arch/riscv/starfive/jh7110_pinctrl.c

111

#define JH7110_PADCFG_DS_4MA __SHIFTIN(1, JH7110_PADCFG_DS_MASK)

sys/arch/riscv/starfive/jh7110_pinctrl.c

112

#define JH7110_PADCFG_DS_8MA __SHIFTIN(2, JH7110_PADCFG_DS_MASK)

sys/arch/riscv/starfive/jh7110_pinctrl.c

113

#define JH7110_PADCFG_DS_12MA __SHIFTIN(3, JH7110_PADCFG_DS_MASK)

sys/arch/riscv/starfive/jh7110_pinctrl.c

320

funcval |= __SHIFTIN(func, jfs->jfs_mask);

sys/arch/riscv/starfive/jh7110_pinctrl.c

345

doutval |= __SHIFTIN(dout, dout_mask);

sys/arch/riscv/starfive/jh7110_pinctrl.c

349

doenval |= __SHIFTIN(doen, doen_mask);

sys/arch/riscv/starfive/jh7110_pinctrl.c

366

dinval |= __SHIFTIN(pin_no + 2, din_mask);

sys/arch/riscv/starfive/jh7110_pinctrl.c

678

bank |= __SHIFTIN(val != 0 ? GPOUT_HIGH : GPOUT_LOW, mask);

sys/arch/riscv/starfive/jh71x0_clkc.c

160

val |= __SHIFTIN(i, JH71X0_CLK_MUX_MASK);

sys/arch/riscv/starfive/jh71x0_clkc.c

263

__SHIFTIN(div, JH71X0_CLK_DIV_MASK), JH71X0_CLK_DIV_MASK);

sys/arch/riscv/starfive/jh71x0_clkc.c

336

__SHIFTIN(div, JH71X0_CLK_DIV_MASK), JH71X0_CLK_DIV_MASK);

sys/arch/riscv/starfive/jh71x0_clkc.c

380

val |= __SHIFTIN(i, JH71X0_CLK_MUX_MASK);

sys/arch/riscv/starfive/jh71x0_clkc.c

452

__SHIFTIN(div, JH71X0_CLK_DIV_MASK), JH71X0_CLK_DIV_MASK);

sys/arch/shark/ofw/vlpci.c

187

val |= __SHIFTIN(VLPCI_INT_CTL_IRQ(VLPCI_IRQ),

sys/arch/shark/ofw/vlpci.c

232

regwrite_1(sc, VLPCI_MISC_CTL_REG, __SHIFTIN(VLPCI_MISC_CTL_HIADDR_DIS,

sys/arch/shark/ofw/vlpci.c

235

__SHIFTIN(VLPCI_CFG_MISC_CTL_INT_CTL_CONV,

sys/arch/shark/ofw/vlpci.c

261

__SHIFTIN(VLPCI_PCI_WND_ATTR_SZ_MEM(VLPCI_VL_MEM_SZ),

sys/arch/shark/ofw/vlpci.c

280

__SHIFTIN(VLPCI_PCI_WND_ATTR_SZ_MEM(VLPCI_PCI_MEM_SZ),

sys/arch/sparc/sparc/pci_fixup.c

324

__SHIFTIN(startbus & 0xff, PCI_BRIDGE_BUS_SECONDARY) |

sys/arch/sparc/sparc/pci_fixup.c

325

__SHIFTIN(0xff, PCI_BRIDGE_BUS_SUBORDINATE));

sys/arch/sparc/sparc/pci_fixup.c

442

__SHIFTIN(startbus & 0xff, PCI_BRIDGE_BUS_SECONDARY) |

sys/arch/sparc/sparc/pci_fixup.c

443

__SHIFTIN(*maxbus & 0xff, PCI_BRIDGE_BUS_SUBORDINATE));

sys/arch/x86/acpi/acpi_cpu_md.c

936

val |= __SHIFTIN(fid, MSR_0FH_CONTROL_FID);

sys/arch/x86/acpi/acpi_cpu_md.c

937

val |= __SHIFTIN(vid, MSR_0FH_CONTROL_VID);

sys/arch/x86/acpi/acpi_cpu_md.c

938

val |= __SHIFTIN(cnt, MSR_0FH_CONTROL_CNT);

sys/arch/x86/acpi/acpi_cpu_md.c

939

val |= __SHIFTIN(0x1, MSR_0FH_CONTROL_CHG);

sys/arch/x86/include/i82489reg.h

111

# define LAPIC_DSTMODE_PHYS __SHIFTIN(0, LAPIC_DSTMODE_MASK)

sys/arch/x86/include/i82489reg.h

112

# define LAPIC_DSTMODE_LOG __SHIFTIN(1, LAPIC_DSTMODE_MASK)

sys/arch/x86/include/i82489reg.h

115

# define LAPIC_DEST_DEFAULT __SHIFTIN(0, LAPIC_DEST_MASK)

sys/arch/x86/include/i82489reg.h

116

# define LAPIC_DEST_SELF __SHIFTIN(1, LAPIC_DEST_MASK)

sys/arch/x86/include/i82489reg.h

117

# define LAPIC_DEST_ALLINCL __SHIFTIN(2, LAPIC_DEST_MASK)

sys/arch/x86/include/i82489reg.h

118

# define LAPIC_DEST_ALLEXCL __SHIFTIN(3, LAPIC_DEST_MASK)

sys/arch/x86/include/i82489reg.h

124

# define LAPIC_LVT_TMM_ONESHOT __SHIFTIN(0, LAPIC_LVT_TMM)

sys/arch/x86/include/i82489reg.h

125

# define LAPIC_LVT_TMM_PERIODIC __SHIFTIN(1, LAPIC_LVT_TMM)

sys/arch/x86/include/i82489reg.h

126

# define LAPIC_LVT_TMM_TSCDLT __SHIFTIN(2, LAPIC_LVT_TMM)

sys/arch/x86/include/i82489reg.h

85

#define LAPIC_DLMODE_FIXED __SHIFTIN(0, LAPIC_DLMODE_MASK)

sys/arch/x86/include/i82489reg.h

86

#define LAPIC_DLMODE_LOW __SHIFTIN(1, LAPIC_DLMODE_MASK) /* NA in x2APIC */

sys/arch/x86/include/i82489reg.h

87

#define LAPIC_DLMODE_SMI __SHIFTIN(2, LAPIC_DLMODE_MASK)

sys/arch/x86/include/i82489reg.h

88

#define LAPIC_DLMODE_NMI __SHIFTIN(4, LAPIC_DLMODE_MASK)

sys/arch/x86/include/i82489reg.h

89

#define LAPIC_DLMODE_INIT __SHIFTIN(5, LAPIC_DLMODE_MASK)

sys/arch/x86/include/i82489reg.h

90

#define LAPIC_DLMODE_STARTUP __SHIFTIN(6, LAPIC_DLMODE_MASK) /* NA in LVT,MSI*/

sys/arch/x86/include/i82489reg.h

91

#define LAPIC_DLMODE_EXTINT __SHIFTIN(7, LAPIC_DLMODE_MASK) /* NA in x2APIC */

sys/arch/x86/pci/msipic.c

413

addr = LAPIC_MSIADDR_BASE | __SHIFTIN(ci->ci_cpuid,

sys/arch/x86/pci/msipic.c

416

data = __SHIFTIN(idt_vec, LAPIC_VECTOR_MASK)

sys/arch/x86/pci/msipic.c

606

addr = LAPIC_MSIADDR_BASE | __SHIFTIN(ci->ci_cpuid,

sys/arch/x86/pci/msipic.c

609

data = __SHIFTIN(idt_vec, LAPIC_VECTOR_MASK)

sys/arch/x86/pci/msipic.c

826

ctl |= __SHIFTIN(ilog2(count), PCI_MSI_CTL_MME_MASK);

sys/arch/x86/pci/pci_msi_machdep.c

77

pih = __SHIFTIN((uint64_t)msipic_get_devid(msi_pic), MSI_INT_DEV_MASK)

sys/arch/x86/pci/pci_msi_machdep.c

78

| __SHIFTIN((uint64_t)vector, MSI_INT_VEC_MASK)

sys/arch/x86/x86/intr.c

316

pih = __SHIFTIN((uint64_t)dev, MSI_INT_DEV_MASK)

sys/arch/x86/x86/intr.c

317

| __SHIFTIN((uint64_t)vec, MSI_INT_VEC_MASK)

sys/arch/x86/x86/pmap.c

6126

ret = __SHIFTIN(TYPE_UC, EPT_T);

sys/arch/x86/x86/pmap.c

6129

ret = __SHIFTIN(TYPE_WC, EPT_T);

sys/arch/x86/x86/pmap.c

6133

ret = __SHIFTIN(TYPE_WB, EPT_T);

sys/arch/x86/x86/svs.c

501

svs_pcid_ucr3 = __SHIFTIN(PMAP_PCID_USER, CR3_PCID) | CR3_NO_TLB_FLUSH;

sys/arch/x86/x86/svs.c

502

svs_pcid_kcr3 = __SHIFTIN(PMAP_PCID_KERN, CR3_PCID) | CR3_NO_TLB_FLUSH;

sys/arch/xen/x86/xen_intr.c

469

pih = __SHIFTIN((uint64_t)dev, MSI_INT_DEV_MASK)

sys/arch/xen/x86/xen_intr.c

470

| __SHIFTIN((uint64_t)vec, MSI_INT_VEC_MASK)

sys/crypto/aes/aes_ccm.c

109

auth[0] = __SHIFTIN(adlen == 0 ? 0 : 1, CCM_AFLAGS_ADATA);

sys/crypto/aes/aes_ccm.c

110

auth[0] |= __SHIFTIN((M - 2)/2, CCM_AFLAGS_M);

sys/crypto/aes/aes_ccm.c

111

auth[0] |= __SHIFTIN(L - 1, CCM_AFLAGS_L);

sys/crypto/aes/aes_ccm.c

175

ctr[0] = __SHIFTIN(L - 1, CCM_EFLAGS_L);

sys/dev/acpi/acpi_cpu.h

345

val.u64 |= __SHIFTIN(newval, reg_mask);

sys/dev/acpi/acpi_pcc.c

281

tmp |= __SHIFTIN(val, mask);

sys/dev/acpi/qcomgpio.c

581

val |= __SHIFTIN(dect, TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK);

sys/dev/acpi/qcomgpio.c

585

val |= __SHIFTIN(TLMM_GPIO_INTR_CFG_TARGET_PROC_RPM,

sys/dev/acpi/qcomipcc.c

218

__SHIFTIN(ih->ih_client_id, IPCC_CLIENT_ID_MASK) |

sys/dev/acpi/qcomipcc.c

219

__SHIFTIN(ih->ih_signal_id, IPCC_SIGNAL_ID_MASK));

sys/dev/acpi/qcomipcc.c

229

__SHIFTIN(ih->ih_client_id, IPCC_CLIENT_ID_MASK) |

sys/dev/acpi/qcomipcc.c

230

__SHIFTIN(ih->ih_signal_id, IPCC_SIGNAL_ID_MASK));

sys/dev/acpi/qcomipcc.c

258

__SHIFTIN(ch->ch_client_id, IPCC_CLIENT_ID_MASK) |

sys/dev/acpi/qcomipcc.c

259

__SHIFTIN(ch->ch_signal_id, IPCC_SIGNAL_ID_MASK));

sys/dev/cadence/cemacreg.h

142

#define ETH_CFG_CLK_8 __SHIFTIN(0, ETH_CFG_CLK)

sys/dev/cadence/cemacreg.h

143

#define ETH_CFG_CLK_16 __SHIFTIN(1, ETH_CFG_CLK)

sys/dev/cadence/cemacreg.h

144

#define ETH_CFG_CLK_32 __SHIFTIN(2, ETH_CFG_CLK)

sys/dev/cadence/cemacreg.h

145

#define ETH_CFG_CLK_64 __SHIFTIN(3, ETH_CFG_CLK)

sys/dev/cadence/cemacreg.h

158

#define GEM_CFG_CLK_8 __SHIFTIN(0, GEM_CFG_CLK)

sys/dev/cadence/cemacreg.h

159

#define GEM_CFG_CLK_16 __SHIFTIN(1, GEM_CFG_CLK)

sys/dev/cadence/cemacreg.h

160

#define GEM_CFG_CLK_32 __SHIFTIN(2, GEM_CFG_CLK)

sys/dev/cadence/cemacreg.h

161

#define GEM_CFG_CLK_48 __SHIFTIN(3, GEM_CFG_CLK)

sys/dev/cadence/cemacreg.h

162

#define GEM_CFG_CLK_64 __SHIFTIN(4, GEM_CFG_CLK)

sys/dev/cadence/cemacreg.h

163

#define GEM_CFG_CLK_96 __SHIFTIN(5, GEM_CFG_CLK)

sys/dev/cadence/cemacreg.h

164

#define GEM_CFG_CLK_128 __SHIFTIN(6, GEM_CFG_CLK)

sys/dev/cadence/cemacreg.h

165

#define GEM_CFG_CLK_224 __SHIFTIN(7, GEM_CFG_CLK)

sys/dev/cadence/cemacreg.h

167

#define GEM_CFG_DBW_32 __SHIFTIN(0, GEM_CFG_DBW)

sys/dev/cadence/cemacreg.h

168

#define GEM_CFG_DBW_64 __SHIFTIN(1, GEM_CFG_DBW)

sys/dev/cadence/cemacreg.h

169

#define GEM_CFG_DBW_128 __SHIFTIN(2, GEM_CFG_DBW)

sys/dev/cadence/cemacreg.h

220

#define ETH_MAN_RW_RD __SHIFTIN(2, ETH_MAN_RW)

sys/dev/cadence/cemacreg.h

221

#define ETH_MAN_RW_WR __SHIFTIN(1, ETH_MAN_RW)

sys/dev/cadence/cemacreg.h

229

__SHIFTIN(2, ETH_MAN_CODE)

sys/dev/cadence/cemacreg.h

260

#define ETH_RDSC_I_CHKSUM_NONE __SHIFTIN(0, ETH_RDSC_I_CHKSUM)

sys/dev/cadence/cemacreg.h

261

#define ETH_RDSC_I_CHKSUM_IP __SHIFTIN(1, ETH_RDSC_I_CHKSUM)

sys/dev/cadence/cemacreg.h

262

#define ETH_RDSC_I_CHKSUM_TCP __SHIFTIN(2, ETH_RDSC_I_CHKSUM)

sys/dev/cadence/cemacreg.h

263

#define ETH_RDSC_I_CHKSUM_UDP __SHIFTIN(3, ETH_RDSC_I_CHKSUM)

sys/dev/cadence/cemacreg.h

272

#define ETH_TDSC_I_CHKSUM_GEN_STAT_NO_ERR __SHIFTIN(0, ETH_TDSC_I_CHKSUM)

sys/dev/cadence/cemacreg.h

273

#define ETH_TDSC_I_CHKSUM_GEN_STAT_VLAN_HDR_ERR __SHIFTIN(1, ETH_TDSC_I_CHKSUM)

sys/dev/cadence/cemacreg.h

274

#define ETH_TDSC_I_CHKSUM_GEN_STAT_SNAP_HDR_ERR __SHIFTIN(2, ETH_TDSC_I_CHKSUM)

sys/dev/cadence/cemacreg.h

275

#define ETH_TDSC_I_CHKSUM_GEN_STAT_IP_HDR_ERR __SHIFTIN(3, ETH_TDSC_I_CHKSUM)

sys/dev/cadence/cemacreg.h

276

#define ETH_TDSC_I_CHKSUM_GEN_STAT_UNKNOWN_TYPE __SHIFTIN(4, ETH_TDSC_I_CHKSUM)

sys/dev/cadence/cemacreg.h

277

#define ETH_TDSC_I_CHKSUM_GEN_STAT_UNSUPP_FRAG __SHIFTIN(5, ETH_TDSC_I_CHKSUM)

sys/dev/cadence/cemacreg.h

278

#define ETH_TDSC_I_CHKSUM_GEN_STAT_NOT_TCPUDP __SHIFTIN(6, ETH_TDSC_I_CHKSUM)

sys/dev/cadence/cemacreg.h

279

#define ETH_TDSC_I_CHKSUM_GEN_STAT_SHORT_PKT __SHIFTIN(7, ETH_TDSC_I_CHKSUM)

sys/dev/cadence/if_cemac.c

448

__SHIFTIN((MCLBYTES + 63) / 64, GEM_DMA_CFG_RX_BUF_SIZE) |

sys/dev/cadence/if_cemac.c

449

__SHIFTIN(3, GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL) |

sys/dev/cadence/if_cemac.c

451

__SHIFTIN(16, GEM_DMA_CFG_AHB_FIXED_BURST_LEN) |

sys/dev/cadence/if_cemac.c

945

__SHIFTIN(m->m_pkthdr.len, ETH_TDSC_I_LEN) |

sys/dev/cardbus/rbus_ppb.c

379

__SHIFTIN((start >> 8)

sys/dev/cardbus/rbus_ppb.c

381

__SHIFTIN(((start + rct.bussize_ioreqs[busnum] + 4095) >> 8)

sys/dev/cardbus/rbus_ppb.c

415

__SHIFTIN((start >> 16) & PCI_BRIDGE_MEMORY_ADDR,

sys/dev/cardbus/rbus_ppb.c

417

__SHIFTIN(((start + rct.bussize_memreqs[busnum]

sys/dev/cardbus/rbus_ppb.c

423

__SHIFTIN((start >> 16) & PCI_BRIDGE_PREFETCHMEM_ADDR,

sys/dev/cardbus/rbus_ppb.c

425

__SHIFTIN(((start + rct.bussize_memreqs[busnum]

sys/dev/fdt/arasan_sdhc_fdt.c

187

val = __SHIFTIN((xin_rate + (1000000 / 2)) / 1000000, RK3399_CORECFG_BASECLKFREQ);

sys/dev/fdt/ausoc.c

420

*format = __SHIFTIN(fmt, AUDIO_DAI_FORMAT_MASK) |

sys/dev/fdt/ausoc.c

421

__SHIFTIN(pol, AUDIO_DAI_POLARITY_MASK) |

sys/dev/fdt/ausoc.c

422

__SHIFTIN(clk, AUDIO_DAI_CLOCK_MASK);

sys/dev/fdt/dwc3_fdt.c

145

val |= __SHIFTIN(5, GUSB2PHYCFG_USBTRDTIM);

sys/dev/fdt/dwc3_fdt.c

149

val |= __SHIFTIN(9, GUSB2PHYCFG_USBTRDTIM);

sys/dev/fdt/dwc3_fdt.c

182

val |= __SHIFTIN(DCFG_SPEED_LS, DCFG_SPEED);

sys/dev/fdt/dwc3_fdt.c

184

val |= __SHIFTIN(DCFG_SPEED_FS, DCFG_SPEED);

sys/dev/fdt/dwc3_fdt.c

186

val |= __SHIFTIN(DCFG_SPEED_HS, DCFG_SPEED);

sys/dev/fdt/dwc3_fdt.c

188

val |= __SHIFTIN(DCFG_SPEED_SS, DCFG_SPEED);

sys/dev/fdt/dwc3_fdt.c

190

val |= __SHIFTIN(DCFG_SPEED_SS, DCFG_SPEED); /* default to super speed */

sys/dev/fdt/dwc3_fdt.c

201

val |= __SHIFTIN(mode, GCTL_PRTCAP);

sys/dev/i2c/act8846.c

254

val = __SHIFTIN(n, ACT_VSET_VSET);

sys/dev/i2c/anxedp.c

179

ctrl[0] = __SHIFTIN(comm, ANX_AUX_TX_COMM);

sys/dev/i2c/anxedp.c

181

ctrl[0] |= __SHIFTIN(buflen - 1, ANX_AUX_LENGTH);

sys/dev/i2c/as3722.c

293

__SHIFTIN(AS3722_GPIO0_CTRL_IOSF_GPIO,

sys/dev/i2c/as3722.c

295

__SHIFTIN(AS3722_GPIO0_CTRL_MODE_PULLDOWN,

sys/dev/i2c/as3722.c

299

__SHIFTIN(1, AS3722_WATCHDOG_CTRL_MODE), 0, 0);

sys/dev/i2c/as3722.c

398

__SHIFTIN(sc->sc_smw.smw_period - 1, AS3722_WATCHDOG_TIMER_TIMER),

sys/dev/i2c/axp809.c

236

val |= __SHIFTIN(reg_val, c->c_voltage_mask);

sys/dev/i2c/axppmic.c

629

val |= __SHIFTIN(reg_val, c->c_voltage_mask);

sys/dev/i2c/cwfg.c

258

config |= __SHIFTIN(sc->sc_alert_level, CONFIG_ATHD);

sys/dev/i2c/cwfg.c

329

mode |= __SHIFTIN(MODE_SLEEP_WAKE, MODE_SLEEP);

sys/dev/i2c/es8316ac.c

366

val |= __SHIFTIN(nvol, mix->mask[ch]);

sys/dev/i2c/es8316ac.c

546

val |= __SHIFTIN(SD_FMT_I2S, SD_FMT_MASK);

sys/dev/i2c/es8316ac.c

553

val |= __SHIFTIN(SD_FMT_I2S, SD_FMT_MASK);

sys/dev/i2c/es8316ac.c

616

val |= __SHIFTIN(SD_FMT_WL_16, SD_FMT_WL);

sys/dev/i2c/es8316ac.c

621

val |= __SHIFTIN(SD_FMT_WL_16, SD_FMT_WL);

sys/dev/i2c/fan53555.c

179

val |= __SHIFTIN((min_uvol - sc->sc_base) / sc->sc_step, VSEL_NSEL);

sys/dev/i2c/fan53555.c

280

control |= __SHIFTIN(fan53555_slew_rates[n], CONTROL_SLEW);

sys/dev/i2c/max77620.c

239

gpio |= __SHIFTIN(val, MAX_GPIO_OUTPUT_VAL);

sys/dev/i2c/rkpmic.c

590

val |= __SHIFTIN(vsel, c->vsel_mask);

sys/dev/i2c/sdtemp.c

711

__SHIFTIN(SDTEMP_CAP_RESOLUTION_MAX, SDTEMP_CAP_RESOLUTION));

sys/dev/i2c/tcagpio.c

221

gpio |= __SHIFTIN(val, PORT_BIT(gpin->pin_num));

sys/dev/ic/anx_dp.c

110

#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) __SHIFTIN((x), __BITS(10,8))

sys/dev/ic/anx_dp.c

111

#define AUX_HW_RETRY_INTERVAL_600_US __SHIFTIN(0, __BITS(4,3))

sys/dev/ic/anx_dp.c

112

#define AUX_HW_RETRY_INTERVAL_800_US __SHIFTIN(1, __BITS(4,3))

sys/dev/ic/anx_dp.c

113

#define AUX_HW_RETRY_INTERVAL_1000_US __SHIFTIN(2, __BITS(4,3))

sys/dev/ic/anx_dp.c

114

#define AUX_HW_RETRY_INTERVAL_1800_US __SHIFTIN(3, __BITS(4,3))

sys/dev/ic/anx_dp.c

115

#define AUX_HW_RETRY_COUNT_SEL(x) __SHIFTIN((x), __BITS(2,0))

sys/dev/ic/anx_dp.c

146

#define SW_TRAINING_PATTERN_SET_PTN2 __SHIFTIN(2, __BITS(1,0))

sys/dev/ic/anx_dp.c

147

#define SW_TRAINING_PATTERN_SET_PTN1 __SHIFTIN(1, __BITS(1,0))

sys/dev/ic/anx_dp.c

150

#define PRE_EMPHASIS_SET(x) __SHIFTIN((x), __BITS(4,3))

sys/dev/ic/anx_dp.c

152

#define DRIVE_CURRENT_SET(x) __SHIFTIN((x), __BITS(1,0))

sys/dev/ic/anx_dp.c

170

#define DEFER_COUNT(x) __SHIFTIN((x), __BITS(6,0))

sys/dev/ic/anx_dp.c

176

#define BUF_DATA_COUNT(x) __SHIFTIN((x), __BITS(4,0))

sys/dev/ic/anx_dp.c

178

#define AUX_LENGTH(x) __SHIFTIN((x) - 1, __BITS(7,4))

sys/dev/ic/atw.c

1024

tofs2 = __SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */

sys/dev/ic/atw.c

1025

__SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */

sys/dev/ic/atw.c

1026

__SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */

sys/dev/ic/atw.c

1027

__SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */

sys/dev/ic/atw.c

1028

__SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */

sys/dev/ic/atw.c

1029

__SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */

sys/dev/ic/atw.c

1030

__SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */

sys/dev/ic/atw.c

1031

__SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */

sys/dev/ic/atw.c

1034

tofs2 = __SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */

sys/dev/ic/atw.c

1035

__SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */

sys/dev/ic/atw.c

1036

__SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */

sys/dev/ic/atw.c

1037

__SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */

sys/dev/ic/atw.c

1038

__SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */

sys/dev/ic/atw.c

1039

__SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */

sys/dev/ic/atw.c

1040

__SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */

sys/dev/ic/atw.c

1041

__SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */

sys/dev/ic/atw.c

1055

ATW_WRITE(sc, ATW_TXLMT, __SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) |

sys/dev/ic/atw.c

1056

__SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK));

sys/dev/ic/atw.c

1067

test1 |= __SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL;

sys/dev/ic/atw.c

1090

cfpp |= __SHIFTIN(16, ATW_CFPP_CFPMD);

sys/dev/ic/atw.c

1106

__SHIFTIN(22, ATW_TOFS0_USCNT_MASK) |

sys/dev/ic/atw.c

1118

ifst = __SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) |

sys/dev/ic/atw.c

1119

__SHIFTIN(22 * 10 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */,

sys/dev/ic/atw.c

1121

__SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) |

sys/dev/ic/atw.c

1122

__SHIFTIN(IEEE80211_DUR_DS_EIFS, ATW_IFST_EIFS_MASK);

sys/dev/ic/atw.c

1136

ATW_WRITE(sc, ATW_RSPT, __SHIFTIN(0xffff, ATW_RSPT_MART_MASK) |

sys/dev/ic/atw.c

1137

__SHIFTIN(0xff, ATW_RSPT_MIRT_MASK));

sys/dev/ic/atw.c

1224

ATW_WRITE(sc, ATW_PLCPHD, __SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) |

sys/dev/ic/atw.c

1225

__SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK));

sys/dev/ic/atw.c

1247

__SHIFTIN(1, ATW_RMD_PCNT) | __SHIFTIN(0xffff, ATW_RMD_RMRD_MASK));

sys/dev/ic/atw.c

1569

gain = __SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK);

sys/dev/ic/atw.c

1608

gpio |= __SHIFTIN(1, ATW_GPIO_EN_MASK);

sys/dev/ic/atw.c

1616

gpio |= __SHIFTIN(1, ATW_GPIO_O_MASK);

sys/dev/ic/atw.c

1641

__SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK));

sys/dev/ic/atw.c

1654

__SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK));

sys/dev/ic/atw.c

1661

__SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK));

sys/dev/ic/atw.c

1745

__SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0)

sys/dev/ic/atw.c

1774

reg |= __SHIFTIN(__SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK),

sys/dev/ic/atw.c

1794

__SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) |

sys/dev/ic/atw.c

1795

__SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK);

sys/dev/ic/atw.c

1844

reg = sc->sc_bbpctl_rd | __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK);

sys/dev/ic/atw.c

1883

bits = __SHIFTIN(val, SI4126_TWI_DATA_MASK) |

sys/dev/ic/atw.c

1884

__SHIFTIN(addr, SI4126_TWI_ADDR_MASK);

sys/dev/ic/atw.c

1934

reg = sc->sc_synctl_rd | __SHIFTIN(addr, ATW_SYNCTL_DATA_MASK);

sys/dev/ic/atw.c

2052

__SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) |

sys/dev/ic/atw.c

2053

__SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) |

sys/dev/ic/atw.c

2054

__SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) |

sys/dev/ic/atw.c

2055

__SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK));

sys/dev/ic/atw.c

2060

__SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) |

sys/dev/ic/atw.c

2061

__SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK));

sys/dev/ic/atw.c

2089

__SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK));

sys/dev/ic/atw.c

2093

__SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK));

sys/dev/ic/atw.c

2210

reg |= __SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK);

sys/dev/ic/atw.c

2362

bpli = __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) |

sys/dev/ic/atw.c

2363

__SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK);

sys/dev/ic/atw.c

2367

bcnt |= __SHIFTIN(len, ATW_BCNT_BCNT_MASK);

sys/dev/ic/atw.c

2368

cap0 |= __SHIFTIN(chan, ATW_CAP0_CHN_MASK);

sys/dev/ic/atw.c

2369

cap1 |= __SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK);

sys/dev/ic/atw.c

2462

__SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) |

sys/dev/ic/atw.c

2463

__SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) |

sys/dev/ic/atw.c

2464

__SHIFTIN(__SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU,

sys/dev/ic/atw.c

2523

__SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) |

sys/dev/ic/atw.c

2524

__SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval,

sys/dev/ic/atw.c

3792

ctl = htole32(__SHIFTIN(8, ATW_TXCTL_TL_MASK));

sys/dev/ic/atw.c

3796

ctl |= htole32(__SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK));

sys/dev/ic/atw.c

3816

htole32(__SHIFTIN(dmamap->dm_segs[seg].ds_len,

sys/dev/ic/atw.c

642

reg = __SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK);

sys/dev/ic/atw.c

658

reg = __SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK);

sys/dev/ic/atw.c

995

wcsr |= __SHIFTIN(7, ATW_WCSR_BLN_MASK);

sys/dev/ic/atwreg.h

149

#define ATW_PAR_CAL_8DW __SHIFTIN(0x1, ATW_PAR_CAL_MASK)

sys/dev/ic/atwreg.h

151

#define ATW_PAR_CAL_16DW __SHIFTIN(0x2, ATW_PAR_CAL_MASK)

sys/dev/ic/atwreg.h

153

#define ATW_PAR_CAL_32DW __SHIFTIN(0x3, ATW_PAR_CAL_MASK)

sys/dev/ic/atwreg.h

156

#define ATW_PAR_PBL_1DW __SHIFTIN(0x1, ATW_PAR_PBL_MASK)

sys/dev/ic/atwreg.h

157

#define ATW_PAR_PBL_2DW __SHIFTIN(0x2, ATW_PAR_PBL_MASK)

sys/dev/ic/atwreg.h

158

#define ATW_PAR_PBL_4DW __SHIFTIN(0x4, ATW_PAR_PBL_MASK)

sys/dev/ic/atwreg.h

159

#define ATW_PAR_PBL_8DW __SHIFTIN(0x8, ATW_PAR_PBL_MASK)

sys/dev/ic/atwreg.h

160

#define ATW_PAR_PBL_16DW __SHIFTIN(0x16, ATW_PAR_PBL_MASK)

sys/dev/ic/atwreg.h

161

#define ATW_PAR_PBL_32DW __SHIFTIN(0x32, ATW_PAR_PBL_MASK)

sys/dev/ic/atwreg.h

272

#define ATW_NAR_TR_L64 __SHIFTIN(0x0, ATW_NAR_TR_MASK)

sys/dev/ic/atwreg.h

273

#define ATW_NAR_TR_L160 __SHIFTIN(0x2, ATW_NAR_TR_MASK)

sys/dev/ic/atwreg.h

274

#define ATW_NAR_TR_L192 __SHIFTIN(0x3, ATW_NAR_TR_MASK)

sys/dev/ic/atwreg.h

275

#define ATW_NAR_TR_H96 __SHIFTIN(0x0, ATW_NAR_TR_MASK)

sys/dev/ic/atwreg.h

276

#define ATW_NAR_TR_H288 __SHIFTIN(0x2, ATW_NAR_TR_MASK)

sys/dev/ic/atwreg.h

277

#define ATW_NAR_TR_H544 __SHIFTIN(0x3, ATW_NAR_TR_MASK)

sys/dev/ic/atwreg.h

281

#define ATW_NAR_OM_LOOPBACK __SHIFTIN(0x1, ATW_NAR_OM_MASK)

sys/dev/ic/atwreg.h

344

#define ATW_TEST1_TXWP_TDBD __SHIFTIN(0x0, ATW_TEST1_TXWP_MASK)

sys/dev/ic/atwreg.h

345

#define ATW_TEST1_TXWP_TDBH __SHIFTIN(0x1, ATW_TEST1_TXWP_MASK)

sys/dev/ic/atwreg.h

346

#define ATW_TEST1_TXWP_TDBB __SHIFTIN(0x2, ATW_TEST1_TXWP_MASK)

sys/dev/ic/atwreg.h

347

#define ATW_TEST1_TXWP_TDBP __SHIFTIN(0x3, ATW_TEST1_TXWP_MASK)

sys/dev/ic/atwreg.h

351

#define ATW_TEST1_TESTMODE_NORMAL __SHIFTIN(0x0, ATW_TEST1_TESTMODE_MASK)

sys/dev/ic/atwreg.h

353

#define ATW_TEST1_TESTMODE_MACONLY __SHIFTIN(0x1, ATW_TEST1_TESTMODE_MASK)

sys/dev/ic/atwreg.h

355

#define ATW_TEST1_TESTMODE_NORMAL2 __SHIFTIN(0x2, ATW_TEST1_TESTMODE_MASK)

sys/dev/ic/atwreg.h

357

#define ATW_TEST1_TESTMODE_MONITOR __SHIFTIN(0x3, ATW_TEST1_TESTMODE_MASK)

sys/dev/ic/atwreg.h

373

#define ATW_TEST0_TS_STOPPED __SHIFTIN(0, ATW_TEST0_TS_MASK)

sys/dev/ic/atwreg.h

375

#define ATW_TEST0_TS_FETCH __SHIFTIN(1, ATW_TEST0_TS_MASK)

sys/dev/ic/atwreg.h

377

#define ATW_TEST0_TS_WAIT __SHIFTIN(2, ATW_TEST0_TS_MASK)

sys/dev/ic/atwreg.h

379

#define ATW_TEST0_TS_READING __SHIFTIN(3, ATW_TEST0_TS_MASK)

sys/dev/ic/atwreg.h

380

#define ATW_TEST0_TS_RESERVED1 __SHIFTIN(4, ATW_TEST0_TS_MASK)

sys/dev/ic/atwreg.h

381

#define ATW_TEST0_TS_RESERVED2 __SHIFTIN(5, ATW_TEST0_TS_MASK)

sys/dev/ic/atwreg.h

383

#define ATW_TEST0_TS_SUSPENDED __SHIFTIN(6, ATW_TEST0_TS_MASK)

sys/dev/ic/atwreg.h

385

#define ATW_TEST0_TS_CLOSE __SHIFTIN(7, ATW_TEST0_TS_MASK)

sys/dev/ic/atwreg.h

389

#define ATW_C_TEST0_TS_SUSPENDED __SHIFTIN(4, ATW_TEST0_TS_MASK)

sys/dev/ic/atwreg.h

391

#define ATW_C_TEST0_TS_CLOSE __SHIFTIN(5, ATW_TEST0_TS_MASK)

sys/dev/ic/atwreg.h

393

#define ATW_C_TEST0_TS_CLOSELAST __SHIFTIN(6, ATW_TEST0_TS_MASK)

sys/dev/ic/atwreg.h

395

#define ATW_C_TEST0_TS_FIFOFULL __SHIFTIN(7, ATW_TEST0_TS_MASK)

sys/dev/ic/atwreg.h

400

#define ATW_TEST0_RS_STOPPED __SHIFTIN(0, ATW_TEST0_RS_MASK)

sys/dev/ic/atwreg.h

402

#define ATW_TEST0_RS_FETCH __SHIFTIN(1, ATW_TEST0_RS_MASK)

sys/dev/ic/atwreg.h

404

#define ATW_TEST0_RS_CHECK __SHIFTIN(2, ATW_TEST0_RS_MASK)

sys/dev/ic/atwreg.h

406

#define ATW_TEST0_RS_WAIT __SHIFTIN(3, ATW_TEST0_RS_MASK)

sys/dev/ic/atwreg.h

408

#define ATW_TEST0_RS_SUSPENDED __SHIFTIN(4, ATW_TEST0_RS_MASK)

sys/dev/ic/atwreg.h

410

#define ATW_TEST0_RS_CLOSE __SHIFTIN(5, ATW_TEST0_RS_MASK)

sys/dev/ic/atwreg.h

412

#define ATW_TEST0_RS_FLUSH __SHIFTIN(6, ATW_TEST0_RS_MASK)

sys/dev/ic/atwreg.h

414

#define ATW_TEST0_RS_QUEUE __SHIFTIN(7, ATW_TEST0_RS_MASK)

sys/dev/ic/atwreg.h

466

#define ATW_BBPCTL_RF3KADDR_ADDR __SHIFTIN(0x20, ATW_BBPCTL_RF3KADDR_MASK)

sys/dev/ic/atwreg.h

531

(__SHIFTIN(HFA3861A_CR6, ATW_MMIWADDR_GAIN_MASK) | \

sys/dev/ic/atwreg.h

532

__SHIFTIN(HFA3861A_CR5, ATW_MMIWADDR_RATE_MASK) | \

sys/dev/ic/atwreg.h

533

__SHIFTIN(HFA3861A_CR7, ATW_MMIWADDR_LENHI_MASK) | \

sys/dev/ic/atwreg.h

534

__SHIFTIN(HFA3861A_CR8, ATW_MMIWADDR_LENLO_MASK))

sys/dev/ic/atwreg.h

543

(__SHIFTIN(RF3000_TWI_AI|RF3000_GAINCTL, ATW_MMIWADDR_GAIN_MASK) | \

sys/dev/ic/atwreg.h

544

__SHIFTIN(RF3000_CTL, ATW_MMIWADDR_RATE_MASK))

sys/dev/ic/atwreg.h

553

(__SHIFTIN(HFA3861A_CR61, ATW_MMIRADDR1_RSSI_MASK) | \

sys/dev/ic/atwreg.h

554

__SHIFTIN(HFA3861A_CR62, ATW_MMIRADDR1_RXSTAT_MASK))

sys/dev/ic/atwreg.h

558

(__SHIFTIN(RF3000_RSSI, ATW_MMIRADDR1_RSSI_MASK) | \

sys/dev/ic/atwreg.h

559

__SHIFTIN(RF3000_RXSTAT, ATW_MMIRADDR1_RXSTAT_MASK))

sys/dev/ic/atwreg.h

563

(__SHIFTIN(0x0, ATW_MMIRADDR2_ID_MASK) | \

sys/dev/ic/atwreg.h

564

__SHIFTIN(0x10, ATW_MMIRADDR2_RXPECNT_MASK))

sys/dev/ic/atwreg.h

568

(__SHIFTIN(0x7e, ATW_MMIRADDR2_ID_MASK) | \

sys/dev/ic/atwreg.h

569

__SHIFTIN(0x10, ATW_MMIRADDR2_RXPECNT_MASK))

sys/dev/ic/atwreg.h

636

#define ATW_CMDR_DRT_8DW __SHIFTIN(0x0, ATW_CMDR_DRT_MASK)

sys/dev/ic/atwreg.h

638

#define ATW_CMDR_DRT_16DW __SHIFTIN(0x1, ATW_CMDR_DRT_MASK)

sys/dev/ic/atwreg.h

640

#define ATW_CMDR_DRT_SF __SHIFTIN(0x2, ATW_CMDR_DRT_MASK)

sys/dev/ic/atwreg.h

642

#define ATW_CMDR_DRT_RSVD __SHIFTIN(0x3, ATW_CMDR_DRT_MASK)

sys/dev/ic/atwvar.h

412

htole32(__SHIFTIN(((m->m_ext.ext_size - 1) & ~0x3U),

sys/dev/ic/bcmgenet.c

100

__SHIFTIN(phy, GENET_MDIO_PMD) |

sys/dev/ic/bcmgenet.c

101

__SHIFTIN(reg, GENET_MDIO_REG));

sys/dev/ic/bcmgenet.c

127

__SHIFTIN(phy, GENET_MDIO_PMD) |

sys/dev/ic/bcmgenet.c

128

__SHIFTIN(reg, GENET_MDIO_REG));

sys/dev/ic/bcmgenet.c

171

val |= __SHIFTIN(speed, GENET_UMAC_CMD_SPEED);

sys/dev/ic/bcmgenet.c

189

status = flags | __SHIFTIN(len, GENET_TX_DESC_STATUS_BUFLEN);

sys/dev/ic/bcmgenet.c

482

__SHIFTIN(TX_DESC_COUNT, GENET_TX_DMA_RING_BUF_SIZE_DESC_COUNT) |

sys/dev/ic/bcmgenet.c

483

__SHIFTIN(MCLBYTES, GENET_TX_DMA_RING_BUF_SIZE_BUF_LENGTH));

sys/dev/ic/bcmgenet.c

515

__SHIFTIN(RX_DESC_COUNT, GENET_RX_DMA_RING_BUF_SIZE_DESC_COUNT) |

sys/dev/ic/bcmgenet.c

516

__SHIFTIN(MCLBYTES, GENET_RX_DMA_RING_BUF_SIZE_BUF_LENGTH));

sys/dev/ic/bcmgenet.c

523

__SHIFTIN(5, GENET_RX_DMA_XON_XOFF_THRES_LO) |

sys/dev/ic/bcmgenet.c

524

__SHIFTIN(RX_DESC_COUNT >> 4, GENET_RX_DMA_XON_XOFF_THRES_HI));

sys/dev/ic/bwi.c

10228

__SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);

sys/dev/ic/bwi.c

10237

__SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);

sys/dev/ic/bwi.c

10256

__SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);

sys/dev/ic/bwi.c

10276

__SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);

sys/dev/ic/bwi.c

10285

__SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);

sys/dev/ic/bwi.c

1352

__SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |

sys/dev/ic/bwi.c

1353

__SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));

sys/dev/ic/bwi.c

1513

state_lo &= ~__SHIFTIN(BWI_STATE_LO_FLAG_PHYRST,

sys/dev/ic/bwi.c

1576

__SHIFTIN(tpctl->tp_ctrl1, BWI_RFR_TXPWR1_MASK));

sys/dev/ic/bwi.c

3140

__SHIFTIN(bbp_atten, mask));

sys/dev/ic/bwi.c

3147

__SHIFTIN(bbp_atten, mask));

sys/dev/ic/bwi.c

5981

thr = __SHIFTIN((uint32_t)thr1, NRSSI_THR1_MASK) |

sys/dev/ic/bwi.c

5982

__SHIFTIN((uint32_t)thr2, NRSSI_THR2_MASK);

sys/dev/ic/bwi.c

5998

val = __SHIFTIN(BWI_INVALID_TSSI, BWI_LO_TSSI_MASK) |

sys/dev/ic/bwi.c

5999

__SHIFTIN(BWI_INVALID_TSSI, BWI_HI_TSSI_MASK);

sys/dev/ic/bwi.c

6475

addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |

sys/dev/ic/bwi.c

6476

__SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);

sys/dev/ic/bwi.c

6478

ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |

sys/dev/ic/bwi.c

6479

__SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);

sys/dev/ic/bwi.c

6892

info = __SHIFTIN(revid, BWI_INFO_BBPREV_MASK) |

sys/dev/ic/bwi.c

6893

__SHIFTIN(0, BWI_INFO_BBPPKG_MASK);

sys/dev/ic/bwi.c

7051

__SHIFTIN(BWI_CONF_LO_SERVTO,

sys/dev/ic/bwi.c

7053

__SHIFTIN(BWI_CONF_LO_REQTO,

sys/dev/ic/bwi.c

8567

val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |

sys/dev/ic/bwi.c

8568

__SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,

sys/dev/ic/bwi.c

8572

val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |

sys/dev/ic/bwi.c

8588

val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |

sys/dev/ic/bwi.c

8589

__SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,

sys/dev/ic/bwi.c

8593

val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |

sys/dev/ic/bwi.c

8594

__SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |

sys/dev/ic/bwi.c

9423

plcp = __SHIFTIN(bwi_ieee80211_rate2plcp(rate, IEEE80211_MODE_11G),

sys/dev/ic/bwi.c

9425

__SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);

sys/dev/ic/bwi.c

9736

__SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |

sys/dev/ic/bwi.c

9737

__SHIFTIN(idx, BWI_TXH_ID_IDX_MASK));

sys/dev/ic/bwi.c

9743

phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,

sys/dev/ic/cdnsiic.c

130

__SHIFTIN(best_diva, CR_DIV_A) |

sys/dev/ic/cdnsiic.c

131

__SHIFTIN(best_divb, CR_DIV_B) |

sys/dev/ic/dw_hdmi.c

356

val = __SHIFTIN(HDMI_VP_PR_CD_COLOR_DEPTH_24, HDMI_VP_PR_CD_COLOR_DEPTH) |

sys/dev/ic/dw_hdmi.c

357

__SHIFTIN(HDMI_VP_PR_CD_DESIRED_PR_FACTOR_NONE, HDMI_VP_PR_CD_DESIRED_PR_FACTOR);

sys/dev/ic/dw_hdmi.c

368

val = __SHIFTIN(HDMI_VP_REMAP_YCC422_SIZE_16, HDMI_VP_REMAP_YCC422_SIZE);

sys/dev/ic/dw_hdmi.c

374

__SHIFTIN(HDMI_VP_CONF_OUTPUT_SELECT_BYPASS, HDMI_VP_CONF_OUTPUT_SELECT);

sys/dev/ic/dw_hdmi.c

384

val = __SHIFTIN(HDMI_TX_INVID0_VIDEO_MAPPING_DEFAULT, HDMI_TX_INVID0_VIDEO_MAPPING);

sys/dev/ic/dw_hdmi.c

532

val |= __SHIFTIN(1, HDMI_AUD_CONF0_I2S_IN_EN); /* XXX 2ch */

sys/dev/ic/dw_hdmi.c

535

val = __SHIFTIN(16, HDMI_AUD_CONF1_I2S_WIDTH);

sys/dev/ic/dwc_eqos.c

631

val = __SHIFTIN(val, GMAC_MAC_ADDRESS_HIGH_ADDR)

sys/dev/ic/dwc_eqos.c

795

val |= __SHIFTIN(tqs, GMAC_MTL_TXQ0_OPERATION_MODE_TQS);

sys/dev/ic/dwc_eqos.c

802

val |= __SHIFTIN(rqs, GMAC_MTL_RXQ0_OPERATION_MODE_RQS);

sys/dev/ic/dwc_eqos.c

813

val = __SHIFTIN(GMAC_RXQ_CTRL0_EN_DCB, GMAC_RXQ_CTRL0_EN_MASK);

sys/dev/ic/dwc_gmac.c

1530

__SHIFTIN(len, DDESC_CNTL_SIZE1MASK));

sys/dev/ic/dwc_gmac.c

1585

__SHIFTIN(len, DDESC_DES1_SIZE1MASK));

sys/dev/ic/dwc_gmac.c

419

mii = __SHIFTIN(phy, GMAC_MII_PHY_MASK)

sys/dev/ic/dwc_gmac.c

420

| __SHIFTIN(reg, GMAC_MII_REG_MASK)

sys/dev/ic/dwc_gmac.c

421

| __SHIFTIN(sc->sc_mii_clk, GMAC_MII_CLKMASK)

sys/dev/ic/dwc_gmac.c

452

mii = __SHIFTIN(phy, GMAC_MII_PHY_MASK)

sys/dev/ic/dwc_gmac.c

453

| __SHIFTIN(reg, GMAC_MII_REG_MASK)

sys/dev/ic/dwc_gmac.c

454

| __SHIFTIN(sc->sc_mii_clk, GMAC_MII_CLKMASK)

sys/dev/ic/dwc_gmac.c

844

flow |= __SHIFTIN(0x200, AWIN_GMAC_MAC_FLOWCTRL_PAUSE);

sys/dev/ic/dwc_gmac.c

883

__SHIFTIN(sc->sc_rxpbl, GMAC_BUSMODE_RPBL) |

sys/dev/ic/dwc_gmac.c

884

__SHIFTIN(sc->sc_txpbl, GMAC_BUSMODE_PBL));

sys/dev/ic/dwc_mmc.c

252

fifoth = __SHIFTIN(DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_16,

sys/dev/ic/dwc_mmc.c

254

fifoth |= __SHIFTIN(rx_wmark, DWC_MMC_FIFOTH_RX_WMARK);

sys/dev/ic/dwc_mmc.c

255

fifoth |= __SHIFTIN(tx_wmark, DWC_MMC_FIFOTH_TX_WMARK);

sys/dev/ic/dwc_mmc.c

693

__SHIFTIN(cmd->c_blklen, DWC_MMC_CARDTHRCTL_RDTHR) |

sys/dev/ic/dwc_wdt.c

114

__SHIFTIN(WDT_CRR_CNT_RESTART_MAGIC, WDT_CRR_CNT_RESTART);

sys/dev/ic/dwc_wdt.c

141

torr = __SHIFTIN(intv, WDT_TORR_TIMEOUT_PERIOD);

sys/dev/ic/hfa3861areg.h

44

#define HFA3861A_CR5_RATE_1 __SHIFTIN(0, HFA3861A_CR5_RATE_MASK)

sys/dev/ic/hfa3861areg.h

45

#define HFA3861A_CR5_RATE_2 __SHIFTIN(1, HFA3861A_CR5_RATE_MASK)

sys/dev/ic/hfa3861areg.h

46

#define HFA3861A_CR5_RATE_5 __SHIFTIN(2, HFA3861A_CR5_RATE_MASK)

sys/dev/ic/hfa3861areg.h

47

#define HFA3861A_CR5_RATE_11 __SHIFTIN(3, HFA3861A_CR5_RATE_MASK)

sys/dev/ic/hfa3861areg.h

70

#define HFA3861A_CR63_SIGNAL_1MBPS __SHIFTIN(0, HFA3861A_CR63_SIGNAL)

sys/dev/ic/hfa3861areg.h

72

#define HFA3861A_CR63_SIGNAL_2MBPS __SHIFTIN(2, HFA3861A_CR63_SIGNAL)

sys/dev/ic/hfa3861areg.h

74

#define HFA3861A_CR63_SIGNAL_OTHER_MBPS __SHIFTIN(1, HFA3861A_CR63_SIGNAL)

sys/dev/ic/i82801lpcreg.h

323

#define SB_PORT(id) __SHIFTIN(id, SB_PORTID)

sys/dev/ic/max2820reg.h

115

#define MAX2820_SYNTH_R_22MHZ __SHIFTIN(0, MAX2820_SYNTH_R_MASK)

sys/dev/ic/max2820reg.h

116

#define MAX2820_SYNTH_R_44MHZ __SHIFTIN(1, MAX2820_SYNTH_R_MASK)

sys/dev/ic/max2820reg.h

118

#define MAX2820_SYNTH_R_DEFAULT __SHIFTIN(0, MAX2820_SYNTH_R_MASK)

sys/dev/ic/max2820reg.h

125

#define MAX2820_CHANNEL_RSVD_DEFAULT __SHIFTIN(0, MAX2820_CHANNEL_RSVD)

sys/dev/ic/max2820reg.h

126

#define MAX2820_CHANNEL_CF_DEFAULT __SHIFTIN(37, MAX2820_CHANNEL_CF_MASK)

sys/dev/ic/max2820reg.h

152

#define MAX2820_RECEIVE_BW_8_5MHZ __SHIFTIN(0, MAX2820_RECEIVE_BW_MASK)

sys/dev/ic/max2820reg.h

153

#define MAX2820_RECEIVE_BW_8MHZ __SHIFTIN(1, MAX2820_RECEIVE_BW_MASK)

sys/dev/ic/max2820reg.h

154

#define MAX2820_RECEIVE_BW_7_5MHZ __SHIFTIN(2, MAX2820_RECEIVE_BW_MASK)

sys/dev/ic/max2820reg.h

155

#define MAX2820_RECEIVE_BW_7MHZ __SHIFTIN(3, MAX2820_RECEIVE_BW_MASK)

sys/dev/ic/max2820reg.h

156

#define MAX2820_RECEIVE_BW_6_5MHZ __SHIFTIN(4, MAX2820_RECEIVE_BW_MASK)

sys/dev/ic/max2820reg.h

157

#define MAX2820_RECEIVE_BW_6MHZ __SHIFTIN(5, MAX2820_RECEIVE_BW_MASK)

sys/dev/ic/max2820reg.h

158

#define MAX2820_RECEIVE_2C_DEFAULT __SHIFTIN(7, MAX2820_RECEIVE_2C_MASK)

sys/dev/ic/max2820reg.h

159

#define MAX2820_RECEIVE_1C_DEFAULT __SHIFTIN(7, MAX2820_RECEIVE_1C_MASK)

sys/dev/ic/max2820reg.h

160

#define MAX2820_RECEIVE_DL_DEFAULT __SHIFTIN(1, MAX2820_RECEIVE_DL_MASK)

sys/dev/ic/max2820reg.h

161

#define MAX2820_RECEIVE_SF_DEFAULT __SHIFTIN(0, MAX2820_RECEIVE_SF)

sys/dev/ic/max2820reg.h

169

#define MAX2820A_RECEIVE_2C_DEFAULT __SHIFTIN(7, MAX2820A_RECEIVE_2C_MASK)

sys/dev/ic/max2820reg.h

172

#define MAX2820A_RECEIVE_1C_DEFAULT __SHIFTIN(7, MAX2820A_RECEIVE_1C_MASK)

sys/dev/ic/max2820reg.h

174

#define MAX2820A_RECEIVE_RSVD0_DEFAULT __SHIFTIN(2, MAX2820A_RECEIVE_RSVD0_MASK)

sys/dev/ic/max2820reg.h

176

#define MAX2820A_RECEIVE_RSVD1_DEFAULT __SHIFTIN(2,MAX2820_RECEIVE_RSVD1_MASK)

sys/dev/ic/max2820reg.h

184

#define MAX2820_TRANSMIT_PA_DEFAULT __SHIFTIN(0, MAX2820_TRANSMIT_PA_MASK)

sys/dev/ic/pl041.c

51

#define AACITXCR_TSIZE_16 __SHIFTIN(0, AACITXCR_TSIZE)

sys/dev/ic/pl181.c

347

clock |= __SHIFTIN(clk_div, MMCI_CLOCK_CLKDIV);

sys/dev/ic/pl181.c

423

__SHIFTIN(dir, MMCI_DATA_CTRL_DIRECTION) |

sys/dev/ic/pl181.c

424

__SHIFTIN(blksize, MMCI_DATA_CTRL_BLOCKSIZE) |

sys/dev/ic/rtw.c

1025

cfg4 |= __SHIFTIN(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK);

sys/dev/ic/rtw.c

1363

ctl = __SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) |

sys/dev/ic/rtw.c

2604

tcr |= __SHIFTIN(4, RTW_TCR_SRL_MASK) | __SHIFTIN(4, RTW_TCR_LRL_MASK);

sys/dev/ic/rtw.c

3386

__SHIFTIN(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK);

sys/dev/ic/rtw.c

3413

ctl0 |= __SHIFTIN(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) &

sys/dev/ic/rtw.c

3439

ctl1 = __SHIFTIN(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) |

sys/dev/ic/rtw.c

3440

__SHIFTIN(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK);

sys/dev/ic/rtw.c

3637

bcnitv |= __SHIFTIN(intval, RTW_BCNITV_BCNITV_MASK);

sys/dev/ic/rtw.c

3641

bintritv |= __SHIFTIN(1000, RTW_BINTRITV_BINTRITV);

sys/dev/ic/rtw.c

3644

RTW_WRITE16(regs, RTW_ATIMWND, __SHIFTIN(1, RTW_ATIMWND_ATIMWND));

sys/dev/ic/rtw.c

3645

RTW_WRITE16(regs, RTW_ATIMTRITV, __SHIFTIN(2, RTW_ATIMTRITV_ATIMTRITV));

sys/dev/ic/rtw.c

4019

uint8_t phydelay = __SHIFTIN(0x6, RTW_PHYDELAY_PHYDELAY);

sys/dev/ic/rtw.c

523

__SHIFTIN(7, RTW_TCR_SRL_MASK) | __SHIFTIN(7, RTW_TCR_LRL_MASK);

sys/dev/ic/rtw.c

868

*rcr |= __SHIFTIN(__SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM),

sys/dev/ic/rtwphy.c

197

syna = __SHIFTIN(nf, SA2400_SYNA_NF_MASK) | __SHIFTIN(n, SA2400_SYNA_N_MASK);

sys/dev/ic/rtwphy.c

204

synb = __SHIFTIN(11, SA2400_SYNB_R_MASK) | SA2400_SYNB_L_NORMAL |

sys/dev/ic/rtwphy.c

206

__SHIFTIN(80, SA2400_SYNB_FC_MASK); /* agrees w/ SA2400_SYNA_FM = 0 */

sys/dev/ic/rtwphy.c

258

manrx |= __SHIFTIN(1023, SA2400_MANRX_RXGAIN_MASK);

sys/dev/ic/rtwphy.c

347

agc = __SHIFTIN(25, SA2400_AGC_MAXGAIN_MASK);

sys/dev/ic/rtwphy.c

348

agc |= __SHIFTIN(7, SA2400_AGC_BBPDELAY_MASK);

sys/dev/ic/rtwphy.c

349

agc |= __SHIFTIN(15, SA2400_AGC_LNADELAY_MASK);

sys/dev/ic/rtwphy.c

350

agc |= __SHIFTIN(27, SA2400_AGC_RXONDELAY_MASK);

sys/dev/ic/rtwphy.c

637

__SHIFTIN(freq - 2400, MAX2820_CHANNEL_CF_MASK));

sys/dev/ic/rtwphy.c

683

__SHIFTIN(4, MAX2820A_RECEIVE_1C_MASK) |

sys/dev/ic/rtwphy.c

684

__SHIFTIN(1, MAX2820A_RECEIVE_2C_MASK))) != 0)

sys/dev/ic/rtwphy.c

92

__SHIFTIN(cs_threshold, RTW_BBP_SYS3_CSTHRESH_MASK);

sys/dev/ic/rtwphyio.c

222

return __SHIFTIN(data_and_addr,

sys/dev/ic/rtwphyio.c

264

bits = __SHIFTIN(val, MAX2820_TWI_DATA_MASK) |

sys/dev/ic/rtwphyio.c

265

__SHIFTIN(addr, MAX2820_TWI_ADDR_MASK);

sys/dev/ic/rtwphyio.c

270

bits = __SHIFTIN(val, SA2400_TWI_DATA_MASK) |

sys/dev/ic/rtwphyio.c

271

__SHIFTIN(addr, SA2400_TWI_ADDR_MASK) | SA2400_TWI_WREN;

sys/dev/ic/rtwphyio.c

285

bits = __SHIFTIN(val, SI4126_TWI_DATA_MASK) |

sys/dev/ic/rtwphyio.c

286

__SHIFTIN(addr, SI4126_TWI_ADDR_MASK);

sys/dev/ic/rtwphyio.c

309

return __SHIFTIN(lodata, RTW_PHYCFG_MAC_MAXIM_LODATA_MASK) |

sys/dev/ic/rtwphyio.c

310

__SHIFTIN(hidata, RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK) |

sys/dev/ic/rtwphyio.c

311

__SHIFTIN(addr, RTW_PHYCFG_MAC_MAXIM_ADDR_MASK);

sys/dev/ic/rtwphyio.c

338

reg = __SHIFTIN(addr, RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK) |

sys/dev/ic/rtwphyio.c

339

__SHIFTIN(val, RTW_PHYCFG_MAC_PHILIPS_DATA_MASK);

sys/dev/ic/rtwphyio.c

67

__SHIFTIN(addr, RTW_BB_ADDR_MASK) | RTW_BB_RD_MASK | RTW_BB_WR_MASK);

sys/dev/ic/rtwphyio.c

87

wrbbp = __SHIFTIN(addr, RTW_BB_ADDR_MASK) | RTW_BB_WREN |

sys/dev/ic/rtwphyio.c

88

__SHIFTIN(val, RTW_BB_WR_MASK) | RTW_BB_RD_MASK;

sys/dev/ic/rtwphyio.c

90

rdbbp = __SHIFTIN(addr, RTW_BB_ADDR_MASK) |

sys/dev/ic/rtwreg.h

158

#define RTW_TCR_HWVERID_D __SHIFTIN(26, RTW_TCR_HWVERID_MASK)

sys/dev/ic/rtwreg.h

159

#define RTW_TCR_HWVERID_F __SHIFTIN(27, RTW_TCR_HWVERID_MASK)

sys/dev/ic/rtwreg.h

169

#define RTW_TCR_MXDMA_16 __SHIFTIN(0, RTW_TCR_MXDMA_MASK)

sys/dev/ic/rtwreg.h

170

#define RTW_TCR_MXDMA_32 __SHIFTIN(1, RTW_TCR_MXDMA_MASK)

sys/dev/ic/rtwreg.h

171

#define RTW_TCR_MXDMA_64 __SHIFTIN(2, RTW_TCR_MXDMA_MASK)

sys/dev/ic/rtwreg.h

172

#define RTW_TCR_MXDMA_128 __SHIFTIN(3, RTW_TCR_MXDMA_MASK)

sys/dev/ic/rtwreg.h

173

#define RTW_TCR_MXDMA_256 __SHIFTIN(4, RTW_TCR_MXDMA_MASK)

sys/dev/ic/rtwreg.h

174

#define RTW_TCR_MXDMA_512 __SHIFTIN(5, RTW_TCR_MXDMA_MASK)

sys/dev/ic/rtwreg.h

175

#define RTW_TCR_MXDMA_1024 __SHIFTIN(6, RTW_TCR_MXDMA_MASK)

sys/dev/ic/rtwreg.h

176

#define RTW_TCR_MXDMA_2048 __SHIFTIN(7, RTW_TCR_MXDMA_MASK)

sys/dev/ic/rtwreg.h

186

#define RTW_TCR_LBK_NORMAL __SHIFTIN(0, RTW_TCR_LBK_MASK) /* normal ops */

sys/dev/ic/rtwreg.h

187

#define RTW_TCR_LBK_MAC __SHIFTIN(1, RTW_TCR_LBK_MASK) /* MAC loopback */

sys/dev/ic/rtwreg.h

188

#define RTW_TCR_LBK_BBP __SHIFTIN(2, RTW_TCR_LBK_MASK) /* baseband loop. */

sys/dev/ic/rtwreg.h

189

#define RTW_TCR_LBK_CONT __SHIFTIN(3, RTW_TCR_LBK_MASK) /* continuous Tx */

sys/dev/ic/rtwreg.h

228

#define RTW_RCR_RXFTH_64 __SHIFTIN(2, RTW_RCR_RXFTH_MASK)

sys/dev/ic/rtwreg.h

229

#define RTW_RCR_RXFTH_128 __SHIFTIN(3, RTW_RCR_RXFTH_MASK)

sys/dev/ic/rtwreg.h

230

#define RTW_RCR_RXFTH_256 __SHIFTIN(4, RTW_RCR_RXFTH_MASK)

sys/dev/ic/rtwreg.h

231

#define RTW_RCR_RXFTH_512 __SHIFTIN(5, RTW_RCR_RXFTH_MASK)

sys/dev/ic/rtwreg.h

232

#define RTW_RCR_RXFTH_1024 __SHIFTIN(6, RTW_RCR_RXFTH_MASK)

sys/dev/ic/rtwreg.h

233

#define RTW_RCR_RXFTH_WHOLE __SHIFTIN(7, RTW_RCR_RXFTH_MASK)

sys/dev/ic/rtwreg.h

239

#define RTW_RCR_MXDMA_16 __SHIFTIN(0, RTW_RCR_MXDMA_MASK)

sys/dev/ic/rtwreg.h

240

#define RTW_RCR_MXDMA_32 __SHIFTIN(1, RTW_RCR_MXDMA_MASK)

sys/dev/ic/rtwreg.h

241

#define RTW_RCR_MXDMA_64 __SHIFTIN(2, RTW_RCR_MXDMA_MASK)

sys/dev/ic/rtwreg.h

242

#define RTW_RCR_MXDMA_128 __SHIFTIN(3, RTW_RCR_MXDMA_MASK)

sys/dev/ic/rtwreg.h

243

#define RTW_RCR_MXDMA_256 __SHIFTIN(4, RTW_RCR_MXDMA_MASK)

sys/dev/ic/rtwreg.h

244

#define RTW_RCR_MXDMA_512 __SHIFTIN(5, RTW_RCR_MXDMA_MASK)

sys/dev/ic/rtwreg.h

245

#define RTW_RCR_MXDMA_1024 __SHIFTIN(6, RTW_RCR_MXDMA_MASK)

sys/dev/ic/rtwreg.h

246

#define RTW_RCR_MXDMA_UNLIMITED __SHIFTIN(7, RTW_RCR_MXDMA_MASK)

sys/dev/ic/rtwreg.h

296

#define RTW_9346CR_EEM_NORMAL __SHIFTIN(0, RTW_9346CR_EEM_MASK)

sys/dev/ic/rtwreg.h

301

#define RTW_9346CR_EEM_AUTOLOAD __SHIFTIN(1, RTW_9346CR_EEM_MASK)

sys/dev/ic/rtwreg.h

306

#define RTW_9346CR_EEM_PROGRAM __SHIFTIN(2, RTW_9346CR_EEM_MASK)

sys/dev/ic/rtwreg.h

308

#define RTW_9346CR_EEM_CONFIG __SHIFTIN(3, RTW_9346CR_EEM_MASK)

sys/dev/ic/rtwreg.h

338

#define _RTW_CONFIG0_GL_USA __SHIFTIN(3, RTW_CONFIG0_GL_MASK)

sys/dev/ic/rtwreg.h

339

#define RTW_CONFIG0_GL_EUROPE __SHIFTIN(2, RTW_CONFIG0_GL_MASK)

sys/dev/ic/rtwreg.h

340

#define RTW_CONFIG0_GL_JAPAN __SHIFTIN(1, RTW_CONFIG0_GL_MASK)

sys/dev/ic/rtwreg.h

341

#define RTW_CONFIG0_GL_USA __SHIFTIN(0, RTW_CONFIG0_GL_MASK)

sys/dev/ic/rtwreg.h

356

#define RTW_CONFIG1_LEDS_ACT_INFRA __SHIFTIN(0, RTW_CONFIG1_LEDS_MASK)

sys/dev/ic/rtwreg.h

357

#define RTW_CONFIG1_LEDS_ACT_LINK __SHIFTIN(1, RTW_CONFIG1_LEDS_MASK)

sys/dev/ic/rtwreg.h

358

#define RTW_CONFIG1_LEDS_TX_RX __SHIFTIN(2, RTW_CONFIG1_LEDS_MASK)

sys/dev/ic/rtwreg.h

359

#define RTW_CONFIG1_LEDS_LINKACT_INFRA __SHIFTIN(3, RTW_CONFIG1_LEDS_MASK)

sys/dev/ic/rtwreg.h

414

#define RTW_ANAPARM_RFPOW_MAXIM_ON __SHIFTIN(0x8, RTW_ANAPARM_RFPOW1_MASK)

sys/dev/ic/rtwreg.h

417

#define RTW_ANAPARM_RFPOW_MAXIM_SLEEP __SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK)

sys/dev/ic/rtwreg.h

420

#define RTW_ANAPARM_RFPOW_MAXIM_OFF __SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK)

sys/dev/ic/rtwreg.h

425

#define RTW_ANAPARM_RFPOW_RFMD_ON __SHIFTIN(0x408, RTW_ANAPARM_RFPOW1_MASK)

sys/dev/ic/rtwreg.h

428

#define RTW_ANAPARM_RFPOW_RFMD_SLEEP __SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK)

sys/dev/ic/rtwreg.h

431

#define RTW_ANAPARM_RFPOW_RFMD_OFF __SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK)

sys/dev/ic/rtwreg.h

437

__SHIFTIN(0x328, RTW_ANAPARM_RFPOW1_MASK)

sys/dev/ic/rtwreg.h

439

__SHIFTIN(0x008, RTW_ANAPARM_RFPOW1_MASK)

sys/dev/ic/rtwreg.h

443

__SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK)

sys/dev/ic/rtwreg.h

447

__SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK)

sys/dev/ic/rtwreg.h

449

#define RTW_ANAPARM_RFPOW_PHILIPS_ON __SHIFTIN(0x328, RTW_ANAPARM_RFPOW1_MASK)

sys/dev/ic/rtwreg.h

461

#define RTW_MSR_NETYPE_AP_OK __SHIFTIN(3, RTW_MSR_NETYPE_MASK)

sys/dev/ic/rtwreg.h

463

#define RTW_MSR_NETYPE_INFRA_OK __SHIFTIN(2, RTW_MSR_NETYPE_MASK)

sys/dev/ic/rtwreg.h

465

#define RTW_MSR_NETYPE_ADHOC_OK __SHIFTIN(1, RTW_MSR_NETYPE_MASK)

sys/dev/ic/rtwreg.h

467

#define RTW_MSR_NETYPE_NOLINK __SHIFTIN(0, RTW_MSR_NETYPE_MASK)

sys/dev/ic/rtwreg.h

526

#define RTW_CONFIG4_RFTYPE_INTERSIL __SHIFTIN(1, RTW_CONFIG4_RFTYPE_MASK)

sys/dev/ic/rtwreg.h

527

#define RTW_CONFIG4_RFTYPE_RFMD __SHIFTIN(2, RTW_CONFIG4_RFTYPE_MASK)

sys/dev/ic/rtwreg.h

528

#define RTW_CONFIG4_RFTYPE_PHILIPS __SHIFTIN(3, RTW_CONFIG4_RFTYPE_MASK)

sys/dev/ic/rtwreg.h

546

#define RTW_SCR_KM_WEP104 __SHIFTIN(1, RTW_SCR_KM_MASK)

sys/dev/ic/rtwreg.h

547

#define RTW_SCR_KM_WEP40 __SHIFTIN(0, RTW_SCR_KM_MASK)

sys/dev/ic/rtwreg.h

610

#define RTW_PHYCFG_MAC_RFTYPE_INTERSIL __SHIFTIN(0, RTW_PHYCFG_MAC_RFTYPE_MASK)

sys/dev/ic/rtwreg.h

611

#define RTW_PHYCFG_MAC_RFTYPE_RFMD __SHIFTIN(1, RTW_PHYCFG_MAC_RFTYPE_MASK)

sys/dev/ic/rtwreg.h

613

#define RTW_PHYCFG_MAC_RFTYPE_PHILIPS __SHIFTIN(3, RTW_PHYCFG_MAC_RFTYPE_MASK)

sys/dev/ic/rtwreg.h

63

#define RTW_BRSR_MBR8180_1MBPS __SHIFTIN(0, RTW_BRSR_MBR8180_MASK)

sys/dev/ic/rtwreg.h

64

#define RTW_BRSR_MBR8180_2MBPS __SHIFTIN(1, RTW_BRSR_MBR8180_MASK)

sys/dev/ic/rtwreg.h

65

#define RTW_BRSR_MBR8180_5MBPS __SHIFTIN(2, RTW_BRSR_MBR8180_MASK)

sys/dev/ic/rtwreg.h

66

#define RTW_BRSR_MBR8180_11MBPS __SHIFTIN(3, RTW_BRSR_MBR8180_MASK)

sys/dev/ic/rtwreg.h

851

#define RTW_TXCTL0_RATE_1MBPS __SHIFTIN(0, RTW_TXCTL0_RATE_MASK)

sys/dev/ic/rtwreg.h

852

#define RTW_TXCTL0_RATE_2MBPS __SHIFTIN(1, RTW_TXCTL0_RATE_MASK)

sys/dev/ic/rtwreg.h

853

#define RTW_TXCTL0_RATE_5MBPS __SHIFTIN(2, RTW_TXCTL0_RATE_MASK)

sys/dev/ic/rtwreg.h

854

#define RTW_TXCTL0_RATE_11MBPS __SHIFTIN(3, RTW_TXCTL0_RATE_MASK)

sys/dev/ic/rtwreg.h

859

#define RTW_TXCTL0_RTSRATE_1MBPS __SHIFTIN(0, RTW_TXCTL0_RTSRATE_MASK)

sys/dev/ic/rtwreg.h

860

#define RTW_TXCTL0_RTSRATE_2MBPS __SHIFTIN(1, RTW_TXCTL0_RTSRATE_MASK)

sys/dev/ic/rtwreg.h

861

#define RTW_TXCTL0_RTSRATE_5MBPS __SHIFTIN(2, RTW_TXCTL0_RTSRATE_MASK)

sys/dev/ic/rtwreg.h

862

#define RTW_TXCTL0_RTSRATE_11MBPS __SHIFTIN(3, RTW_TXCTL0_RTSRATE_MASK)

sys/dev/ic/rtwreg.h

929

#define RTW_RXSTAT_RATE_1MBPS __SHIFTIN(0, RTW_RXSTAT_RATE_MASK)

sys/dev/ic/rtwreg.h

930

#define RTW_RXSTAT_RATE_2MBPS __SHIFTIN(1, RTW_RXSTAT_RATE_MASK)

sys/dev/ic/rtwreg.h

931

#define RTW_RXSTAT_RATE_5MBPS __SHIFTIN(2, RTW_RXSTAT_RATE_MASK)

sys/dev/ic/rtwreg.h

932

#define RTW_RXSTAT_RATE_11MBPS __SHIFTIN(3, RTW_RXSTAT_RATE_MASK)

sys/dev/ic/sa2400reg.h

144

#define SA2400_OPMODE_MODE_SLEEP __SHIFTIN(0, SA2400_OPMODE_MODE_MASK)

sys/dev/ic/sa2400reg.h

145

#define SA2400_OPMODE_MODE_TXRX __SHIFTIN(1, SA2400_OPMODE_MODE_MASK)

sys/dev/ic/sa2400reg.h

146

#define SA2400_OPMODE_MODE_WAIT __SHIFTIN(2, SA2400_OPMODE_MODE_MASK)

sys/dev/ic/sa2400reg.h

147

#define SA2400_OPMODE_MODE_RXMGC __SHIFTIN(3, SA2400_OPMODE_MODE_MASK)

sys/dev/ic/sa2400reg.h

148

#define SA2400_OPMODE_MODE_FCALIB __SHIFTIN(4, SA2400_OPMODE_MODE_MASK)

sys/dev/ic/sa2400reg.h

149

#define SA2400_OPMODE_MODE_DCALIB __SHIFTIN(5, SA2400_OPMODE_MODE_MASK)

sys/dev/ic/sa2400reg.h

150

#define SA2400_OPMODE_MODE_FASTTXRXMGC __SHIFTIN(6, SA2400_OPMODE_MODE_MASK)

sys/dev/ic/sa2400reg.h

151

#define SA2400_OPMODE_MODE_RESET __SHIFTIN(7, SA2400_OPMODE_MODE_MASK)

sys/dev/ic/sa2400reg.h

152

#define SA2400_OPMODE_MODE_VCOCALIB __SHIFTIN(8, SA2400_OPMODE_MODE_MASK)

sys/dev/ic/sa2400reg.h

156

SA2400_OPMODE_I0P3 | __SHIFTIN(3, SA2400_OPMODE_FILTTUNE_MASK))

sys/dev/ic/sa2400reg.h

61

#define SA2400_SYNB_L_INACTIVE0 __SHIFTIN(0, SA2400_SYNB_L_MASK)

sys/dev/ic/sa2400reg.h

62

#define SA2400_SYNB_L_INACTIVE1 __SHIFTIN(1, SA2400_SYNB_L_MASK)

sys/dev/ic/sa2400reg.h

63

#define SA2400_SYNB_L_NORMAL __SHIFTIN(2, SA2400_SYNB_L_MASK)

sys/dev/ic/sa2400reg.h

64

#define SA2400_SYNB_L_INACTIVE2 __SHIFTIN(3, SA2400_SYNB_L_MASK)

sys/dev/ic/sa2400reg.h

81

#define SA2400_SYNC_CP_NORMAL_ __SHIFTIN(0, SA2400_SYNC_CP_MASK)

sys/dev/ic/sa2400reg.h

82

#define SA2400_SYNC_CP_THIRD_ __SHIFTIN(1, SA2400_SYNC_CP_MASK)

sys/dev/ic/sa2400reg.h

83

#define SA2400_SYNC_CP_NORMAL __SHIFTIN(2, SA2400_SYNC_CP_MASK) /* recommended */

sys/dev/ic/sa2400reg.h

84

#define SA2400_SYNC_CP_THIRD __SHIFTIN(3, SA2400_SYNC_CP_MASK)

sys/dev/ic/si4136reg.h

46

#define SI4126_MAIN_AUXSEL_RSVD __SHIFTIN(0x0, SI4126_MAIN_AUXSEL_MASK)

sys/dev/ic/si4136reg.h

48

#define SI4126_MAIN_AUXSEL_FRCLOW __SHIFTIN(0x1, SI4126_MAIN_AUXSEL_MASK)

sys/dev/ic/si4136reg.h

50

#define SI4126_MAIN_AUXSEL_LDETB __SHIFTIN(0x3, SI4126_MAIN_AUXSEL_MASK)

sys/dev/ic/siisatareg.h

146

#define GR_GC_PXIE(n) __SHIFTIN(__BIT(n), GR_GC_PXIE_MASK)

sys/dev/ic/siisatareg.h

151

#define GR_GIS_PXIS(n) __SHIFTIN(__BIT(n), GR_GIS_PXIS_MASK)

sys/dev/ic/siisatareg.h

261

#define PR_PXSS(n) __SHIFTIN(__BIT(n), PR_PSS_SLOT_MASK)

sys/dev/ic/ssdfb.c

224

| __SHIFTIN(2, SSD1353_REMAP_PIXEL_FORMAT_MASK),

sys/dev/ic/ssdfb.c

243

| __SHIFTIN(2, SSD1353_REMAP_PIXEL_FORMAT_MASK),

sys/dev/ic/ssdfb.c

754

__SHIFTIN(sc->sc_p->p_fosc, SSDFB_DISPLAY_CLOCK_OSCILLATOR_MASK) |

sys/dev/ic/ssdfb.c

755

__SHIFTIN(sc->sc_p->p_fosc_div, SSDFB_DISPLAY_CLOCK_DIVIDER_MASK));

sys/dev/ic/ssdfb.c

762

__SHIFTIN(sc->sc_p->p_precharge, SSDFB_PRECHARGE_MASK) |

sys/dev/ic/ssdfb.c

763

__SHIFTIN(sc->sc_p->p_discharge, SSDFB_DISCHARGE_MASK));

sys/dev/ic/ssdfb.c

839

__SHIFTIN(sc->sc_p->p_fosc, SSD1322_FREQUENCY_MASK) |

sys/dev/ic/ssdfb.c

840

__SHIFTIN(sc->sc_p->p_fosc_div, SSD1322_DIVIDER_MASK));

sys/dev/ic/ssdfb.c

844

__SHIFTIN(SSD1322_DEFAULT_PHASE_2,

sys/dev/ic/ssdfb.c

846

__SHIFTIN(SSD1322_DEFAULT_PHASE_1,

sys/dev/ic/ssdfb.c

962

__SHIFTIN(sc->sc_p->p_fosc, SSD1322_FREQUENCY_MASK) |

sys/dev/ic/ssdfb.c

963

__SHIFTIN(sc->sc_p->p_fosc_div, SSD1322_DIVIDER_MASK));

sys/dev/ic/ssdfb.c

967

__SHIFTIN(SSD1353_DEFAULT_PHASE_2,

sys/dev/ic/ssdfb.c

969

__SHIFTIN(SSD1353_DEFAULT_PHASE_1,

sys/dev/ic/tpmreg.h

149

#define TPM_INT_LEVEL_HIGH __SHIFTIN(0, TPM_TYPE_POLARITY)

sys/dev/ic/tpmreg.h

150

#define TPM_INT_LEVEL_LOW __SHIFTIN(1, TPM_TYPE_POLARITY)

sys/dev/ic/tpmreg.h

151

#define TPM_INT_EDGE_RISING __SHIFTIN(2, TPM_TYPE_POLARITY)

sys/dev/ic/tpmreg.h

152

#define TPM_INT_EDGE_FALLING __SHIFTIN(3, TPM_TYPE_POLARITY)

sys/dev/ipmivar.h

154

#define IPMI_WDOG_USE_USE_RSVD __SHIFTIN(0, IPMI_WDOG_USE_USE_MASK);

sys/dev/ipmivar.h

155

#define IPMI_WDOG_USE_USE_FRB2 __SHIFTIN(1, IPMI_WDOG_USE_USE_MASK);

sys/dev/ipmivar.h

156

#define IPMI_WDOG_USE_USE_POST __SHIFTIN(2, IPMI_WDOG_USE_USE_MASK);

sys/dev/ipmivar.h

157

#define IPMI_WDOG_USE_USE_OSLOAD __SHIFTIN(3, IPMI_WDOG_USE_USE_MASK);

sys/dev/ipmivar.h

158

#define IPMI_WDOG_USE_USE_OS __SHIFTIN(4, IPMI_WDOG_USE_USE_MASK);

sys/dev/ipmivar.h

159

#define IPMI_WDOG_USE_USE_OEM __SHIFTIN(5, IPMI_WDOG_USE_USE_MASK);

sys/dev/ipmivar.h

163

#define IPMI_WDOG_ACT_PRE_DISABLED __SHIFTIN(0, IPMI_WDOG_ACT_MASK)

sys/dev/ipmivar.h

164

#define IPMI_WDOG_ACT_PRE_SMI __SHIFTIN(1, IPMI_WDOG_ACT_MASK)

sys/dev/ipmivar.h

165

#define IPMI_WDOG_ACT_PRE_NMI __SHIFTIN(2, IPMI_WDOG_ACT_MASK)

sys/dev/ipmivar.h

166

#define IPMI_WDOG_ACT_PRE_INTERRUPT __SHIFTIN(3, IPMI_WDOG_ACT_MASK)

sys/dev/ipmivar.h

169

#define IPMI_WDOG_ACT_DISABLED __SHIFTIN(0, IPMI_WDOG_ACT_MASK)

sys/dev/ipmivar.h

170

#define IPMI_WDOG_ACT_RESET __SHIFTIN(1, IPMI_WDOG_ACT_MASK)

sys/dev/ipmivar.h

171

#define IPMI_WDOG_ACT_PWROFF __SHIFTIN(2, IPMI_WDOG_ACT_MASK)

sys/dev/ipmivar.h

172

#define IPMI_WDOG_ACT_PWRCYCLE __SHIFTIN(3, IPMI_WDOG_ACT_MASK)

sys/dev/isa/isv.c

52

#define ISV_CONTROL_MODE_CAPTURE __SHIFTIN(0, ISV_CONTROL_MODE_MASK)

sys/dev/isa/isv.c

53

#define ISV_CONTROL_MODE_READ __SHIFTIN(1, ISV_CONTROL_MODE_MASK)

sys/dev/isa/isv.c

55

#define ISV_CONTROL_COUNTER_RESET __SHIFTIN(1, ISV_CONTROL_COUNTER_MASK)

sys/dev/isa/isv.c

56

#define ISV_CONTROL_COUNTER_AUTOINC __SHIFTIN(0, ISV_CONTROL_COUNTER_MASK)

sys/dev/isa/isv.c

62

#define ISV_STATUS_VIDEO_RETRACE __SHIFTIN(0, ISV_STATUS_VIDEO_MASK)

sys/dev/isa/isv.c

63

#define ISV_STATUS_VIDEO_WRITE __SHIFTIN(1, ISV_STATUS_VIDEO_MASK)

sys/dev/marvell/mvgbereg.h

455

#define MVGBE_PTFUT_IPGINTTX_V1(x) __SHIFTIN(x, MVGBE_PTFUT_IPGINTTX_V1_MASK)

sys/dev/marvell/mvgbereg.h

456

#define MVGBE_PTFUT_IPGINTTX_V2(x) __SHIFTIN(x, MVGBE_PTFUT_IPGINTTX_V2_MASK)

sys/dev/mii/atphy.c

138

PHY_WRITE(sc, 0x0e, reg | __SHIFTIN(data, __BITS(4, 3)));

sys/dev/mii/mcommphy.c

301

data |= __SHIFTIN(YT8511_CLK_25M_SEL_125M, YT8511_CLK_25M_SEL);

sys/dev/mii/mcommphy.c

309

data |= __SHIFTIN(0xf, YT8511_TX_CLK_DELAY_SEL);

sys/dev/mii/mcommphy.c

311

data |= __SHIFTIN(0x2, YT8511_TX_CLK_DELAY_SEL);

sys/dev/mii/mcommphy.c

375

__SHIFTIN(rx_delay_val, YT8521_RX_DELAY_SEL_MASK) |

sys/dev/mii/mcommphy.c

376

__SHIFTIN(tx_delay_val, YT8521_GE_TX_DELAY_SEL_MASK);

sys/dev/mii/mcommphy.c

476

__SHIFTIN(rx_clk_ds, YT8531_RGMII_RXC_DS_MASK) |

sys/dev/mii/mcommphy.c

477

__SHIFTIN(rx_data_ds_hi, YT8531_RGMII_RXD_DS_HIMASK) |

sys/dev/mii/mcommphy.c

478

__SHIFTIN(rx_data_ds_lo, YT8531_RGMII_RXD_DS_LOMASK);

sys/dev/mii/mcommphy.c

494

data |= __SHIFTIN(YT8531_CLK_SRC_SEL_PLL_125M, YT8531_CLK_SRC_SEL_MASK);

sys/dev/mii/mcommphy.c

499

data |= __SHIFTIN(YT8531_CLK_SRC_SEL_REF_25M, YT8531_CLK_SRC_SEL_MASK);

sys/dev/nvmm/x86/nvmm_x86_svm.c

1959

__SHIFTIN(seg->attrib.type, SVM_SEG_ATTRIB_TYPE) |

sys/dev/nvmm/x86/nvmm_x86_svm.c

1960

__SHIFTIN(seg->attrib.s, SVM_SEG_ATTRIB_S) |

sys/dev/nvmm/x86/nvmm_x86_svm.c

1961

__SHIFTIN(seg->attrib.dpl, SVM_SEG_ATTRIB_DPL) |

sys/dev/nvmm/x86/nvmm_x86_svm.c

1962

__SHIFTIN(seg->attrib.p, SVM_SEG_ATTRIB_P) |

sys/dev/nvmm/x86/nvmm_x86_svm.c

1963

__SHIFTIN(seg->attrib.avl, SVM_SEG_ATTRIB_AVL) |

sys/dev/nvmm/x86/nvmm_x86_svm.c

1964

__SHIFTIN(seg->attrib.l, SVM_SEG_ATTRIB_L) |

sys/dev/nvmm/x86/nvmm_x86_svm.c

1965

__SHIFTIN(seg->attrib.def, SVM_SEG_ATTRIB_DEF) |

sys/dev/nvmm/x86/nvmm_x86_svm.c

1966

__SHIFTIN(seg->attrib.g, SVM_SEG_ATTRIB_G);

sys/dev/nvmm/x86/nvmm_x86_svm.c

2075

vmcb->ctrl.v |= __SHIFTIN(state->crs[NVMM_X64_CR_CR8],

sys/dev/nvmm/x86/nvmm_x86_svm.c

790

__SHIFTIN(vector, VMCB_CTRL_EVENTINJ_VECTOR) |

sys/dev/nvmm/x86/nvmm_x86_svm.c

791

__SHIFTIN(type, VMCB_CTRL_EVENTINJ_TYPE) |

sys/dev/nvmm/x86/nvmm_x86_svm.c

792

__SHIFTIN(err, VMCB_CTRL_EVENTINJ_EV) |

sys/dev/nvmm/x86/nvmm_x86_svm.c

793

__SHIFTIN(1, VMCB_CTRL_EVENTINJ_V) |

sys/dev/nvmm/x86/nvmm_x86_svm.c

794

__SHIFTIN(error, VMCB_CTRL_EVENTINJ_ERRORCODE);

sys/dev/nvmm/x86/nvmm_x86_svm.c

922

cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid,

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1129

__SHIFTIN(vector, INTR_INFO_VECTOR) |

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1130

__SHIFTIN(type, INTR_INFO_TYPE) |

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1131

__SHIFTIN(err, INTR_INFO_ERROR) |

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1132

__SHIFTIN(1, INTR_INFO_VALID);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1320

cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid,

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1392

__SHIFTIN(ecx, CPUID_TOP_LVLNUM) |

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1393

__SHIFTIN(CPUID_TOP_LVLTYPE_SMT, CPUID_TOP_LVLTYPE);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1401

__SHIFTIN(ecx, CPUID_TOP_LVLNUM) |

sys/dev/nvmm/x86/nvmm_x86_vmx.c

1402

__SHIFTIN(CPUID_TOP_LVLTYPE_CORE, CPUID_TOP_LVLTYPE);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2671

__SHIFTIN(segs[idx].attrib.type, VMX_SEG_ATTRIB_TYPE) |

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2672

__SHIFTIN(segs[idx].attrib.s, VMX_SEG_ATTRIB_S) |

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2673

__SHIFTIN(segs[idx].attrib.dpl, VMX_SEG_ATTRIB_DPL) |

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2674

__SHIFTIN(segs[idx].attrib.p, VMX_SEG_ATTRIB_P) |

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2675

__SHIFTIN(segs[idx].attrib.avl, VMX_SEG_ATTRIB_AVL) |

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2676

__SHIFTIN(segs[idx].attrib.l, VMX_SEG_ATTRIB_L) |

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2677

__SHIFTIN(segs[idx].attrib.def, VMX_SEG_ATTRIB_DEF) |

sys/dev/nvmm/x86/nvmm_x86_vmx.c

2678

__SHIFTIN(segs[idx].attrib.g, VMX_SEG_ATTRIB_G) |

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3088

vmcs->ident = __SHIFTIN(rev, VMCS_IDENT_REVISION);

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3167

__SHIFTIN(vmx_eptp_type, EPTP_TYPE) |

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3168

__SHIFTIN(4-1, EPTP_WALKLEN) |

sys/dev/nvmm/x86/nvmm_x86_vmx.c

3889

vmxon->ident = __SHIFTIN(revision, VMXON_IDENT_REVISION);

sys/dev/pci/cx23885reg.h

103

#define CX_RISC_CNT_CTL_NOOP __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_NOOP)

sys/dev/pci/cx23885reg.h

104

#define CX_RISC_CNT_CTL_INCR __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_INCR)

sys/dev/pci/cx23885reg.h

105

#define CX_RISC_CNT_CTL_ZERO __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_ZERO)

sys/dev/pci/cxdtvreg.h

154

#define CX_RISC_CNT_CTL_NOOP __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_NOOP)

sys/dev/pci/cxdtvreg.h

155

#define CX_RISC_CNT_CTL_INCR __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_INCR)

sys/dev/pci/cxdtvreg.h

156

#define CX_RISC_CNT_CTL_ZERO __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_ZERO)

sys/dev/pci/if_aq.c

1001

_v |= __SHIFTIN((val), (mask)); \

sys/dev/pci/if_aq.c

2719

mpictrl |= __SHIFTIN(mode, FW1X_MPI_STATE_MODE);

sys/dev/pci/if_aq.c

2720

mpictrl |= __SHIFTIN(mpispeed, FW1X_MPI_STATE_SPEED);

sys/dev/pci/if_aq.c

3119

RPF_L2UC_MSW_TAG, __SHIFTIN(1, AQ2_RPF_TAG_UC_MASK));

sys/dev/pci/if_aq.c

3296

RPF_L2UC_MSW_TAG, __SHIFTIN(1, AQ2_RPF_TAG_UC_MASK));

sys/dev/pci/if_aq.c

3298

AQ2_RPF_L2BC_TAG_MASK, __SHIFTIN(1, AQ2_RPF_TAG_UC_MASK));

sys/dev/pci/if_aq.c

3309

__SHIFTIN(i, AQ2_RPF_TAG_PCP_MASK), AQ2_RPF_TAG_PCP_MASK,

sys/dev/pci/if_aq.c

4077

v = __SHIFTIN(tx_min, AQ2_TX_INTR_MODERATION_CTL_MIN) |

sys/dev/pci/if_aq.c

4078

__SHIFTIN(tx_max, AQ2_TX_INTR_MODERATION_CTL_MAX) |

sys/dev/pci/if_aq.c

4085

v = __SHIFTIN(tx_min, TX_INTR_MODERATION_CTL_MIN) |

sys/dev/pci/if_aq.c

4086

__SHIFTIN(tx_max, TX_INTR_MODERATION_CTL_MAX) |

sys/dev/pci/if_aq.c

4096

__SHIFTIN(rx_min, RX_INTR_MODERATION_CTL_MIN) |

sys/dev/pci/if_aq.c

4097

__SHIFTIN(rx_max, RX_INTR_MODERATION_CTL_MAX) |

sys/dev/pci/if_aq.c

4407

__SHIFTIN(i + 2, AQ2_RPF_TAG_VLAN_MASK),

sys/dev/pci/if_aq.c

5348

ctl2 = __SHIFTIN(m->m_pkthdr.len, AQ_TXDESC_CTL2_LEN);

sys/dev/pci/if_aq.c

5352

ctl1 |= __SHIFTIN(vlan_get_tag(m), AQ_TXDESC_CTL1_VID);

sys/dev/pci/if_aq.c

5376

__SHIFTIN(map->dm_segs[i].ds_len, AQ_TXDESC_CTL1_BLEN);

sys/dev/pci/if_aq.c

564

(__SHIFTIN((act), AQ2_ART_ACTION_ACT_MASK) | \

sys/dev/pci/if_aq.c

565

__SHIFTIN((rss), AQ2_ART_ACTION_RSS_MASK) | \

sys/dev/pci/if_aq.c

566

__SHIFTIN((idx), AQ2_ART_ACTION_INDEX_MASK) | \

sys/dev/pci/if_aq.c

567

__SHIFTIN((en), AQ2_ART_ACTION_ENABLE_MASK))

sys/dev/pci/if_et.c

1562

val = __SHIFTIN(56, ET_IPG_NONB2B_1) |

sys/dev/pci/if_et.c

1563

__SHIFTIN(88, ET_IPG_NONB2B_2) |

sys/dev/pci/if_et.c

1564

__SHIFTIN(80, ET_IPG_MINIFG) |

sys/dev/pci/if_et.c

1565

__SHIFTIN(96, ET_IPG_B2B);

sys/dev/pci/if_et.c

1571

val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) |

sys/dev/pci/if_et.c

1572

__SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) |

sys/dev/pci/if_et.c

1573

__SHIFTIN(55, ET_MAC_HDX_COLLWIN) |

sys/dev/pci/if_et.c

1644

val = __SHIFTIN(16, ET_RXMAC_MC_SEGSZ_MAX) |

sys/dev/pci/if_et.c

1667

val = __SHIFTIN(ETHER_MIN_LEN, ET_PKTFILT_MINLEN) | ET_PKTFILT_FRAG;

sys/dev/pci/if_et.c

1700

val |= __SHIFTIN(sc->sc_rx_data[0].rbd_bufsize,

sys/dev/pci/if_et.c

1703

val |= __SHIFTIN(sc->sc_rx_data[1].rbd_bufsize,

sys/dev/pci/if_et.c

1768

rxstat_pos = __SHIFTIN(rxst_ring->rsr_index,

sys/dev/pci/if_et.c

1821

rxring_pos = __SHIFTIN(rx_ring->rr_index, ET_RX_RING_POS_INDEX);

sys/dev/pci/if_et.c

1921

__SHIFTIN(map->dm_segs[i].ds_len, ET_TDCTRL1_LEN);

sys/dev/pci/if_et.c

1948

tx_ready_pos = __SHIFTIN(tx_ring->tr_ready_index,

sys/dev/pci/if_et.c

2132

desc->rd_ctrl = __SHIFTIN(buf_idx, ET_RDCTRL_BUFIDX);

sys/dev/pci/if_et.c

370

data = __SHIFTIN(phy, ET_MII_ADDR_PHY) |

sys/dev/pci/if_et.c

371

__SHIFTIN(reg, ET_MII_ADDR_REG);

sys/dev/pci/if_et.c

416

data = __SHIFTIN(phy, ET_MII_ADDR_PHY) |

sys/dev/pci/if_et.c

417

__SHIFTIN(reg, ET_MII_ADDR_REG);

sys/dev/pci/if_et.c

421

CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val, ET_MII_CTRL_VALUE));

sys/dev/pci/if_et.c

483

__SHIFTIN(7, ET_MAC_CFG2_PREAMBLE_LEN);

sys/dev/pci/if_et.c

994

val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) |

sys/dev/pci/if_et.c

995

__SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) |

sys/dev/pci/if_et.c

996

__SHIFTIN(55, ET_MAC_HDX_COLLWIN) |

sys/dev/pci/if_sip.c

2716

__SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) |

sys/dev/pci/if_sip.c

2738

sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK);

sys/dev/pci/if_wm.c

18036

uint32_t reg = __SHIFTIN(link, LTRV_NONSNOOP_REQ)

sys/dev/pci/if_wm.c

18037

| __SHIFTIN(link, LTRV_SNOOP_REQ) | LTRV_SEND;

sys/dev/pci/if_wm.c

18099

lat_enc = (uint16_t)(__SHIFTIN(scale, LTRV_SCALE) | value);

sys/dev/pci/if_wm.c

18131

reg |= lat_enc | __SHIFTIN(lat_enc, LTRV_NONSNOOP);

sys/dev/pci/if_wm.c

4900

phy_data |= __SHIFTIN((freq & 0x01) != 0,

sys/dev/pci/if_wm.c

4902

phy_data |= __SHIFTIN((freq & 0x02) != 0,

sys/dev/pci/if_wm.c

6034

reta_ent = __SHIFTIN(qid,

sys/dev/pci/if_wm.c

6038

reta_ent = __SHIFTIN(qid,

sys/dev/pci/if_wm.c

6042

reta_ent = __SHIFTIN(qid, RETA_ENT_QINDEX_MASK);

sys/dev/pci/if_wm.c

6048

reta_reg |= __SHIFTIN(reta_ent, RETA_ENTRY_MASK_Q(i));

sys/dev/pci/if_wm.c

6405

uint32_t eitr = __SHIFTIN(wmq->wmq_itr, EITR_ITR_INT_MASK);

sys/dev/pci/if_wm.c

6412

eitr |= __SHIFTIN(wmq->wmq_itr,

sys/dev/pci/if_wm.c

7314

ivar |= __SHIFTIN((IVAR_VALID_82574|qintr_idx),

sys/dev/pci/if_wm.c

7316

ivar |= __SHIFTIN((IVAR_VALID_82574|qintr_idx),

sys/dev/pci/if_wm.c

7320

ivar |= __SHIFTIN((IVAR_VALID_82574

sys/dev/pci/if_wm.c

7342

ivar |= __SHIFTIN((qintr_idx

sys/dev/pci/if_wm.c

7346

ivar |= __SHIFTIN((qintr_idx

sys/dev/pci/if_wm.c

7362

ivar |= __SHIFTIN((qintr_idx

sys/dev/pci/if_wm.c

7366

ivar |= __SHIFTIN((qintr_idx

sys/dev/pci/if_wm.c

7378

ivar = __SHIFTIN((sc->sc_link_intr_idx | IVAR_VALID),

sys/dev/pci/if_wm.c

7515

| __SHIFTIN(sc->sc_mchash_type, RCTL_MO);

sys/dev/pci/if_wmreg.h

1780

#define NQTXC_CMD_IP4 __SHIFTIN(1, NQTXC_CMD_IPV_MASK)

sys/dev/pci/if_wmreg.h

1781

#define NQTXC_CMD_IP6 __SHIFTIN(0, NQTXC_CMD_IPV_MASK)

sys/dev/pci/if_wmreg.h

1783

#define NQTXC_CMD_TCP __SHIFTIN(1, NQTXC_CMD_TP_MASK)

sys/dev/pci/if_wmreg.h

1784

#define NQTXC_CMD_UDP __SHIFTIN(0, NQTXC_CMD_TP_MASK)

sys/dev/pci/if_wmreg.h

361

#define WTX_DTYP_C __SHIFTIN(0, WTX_DTYP_MASK) /* context */

sys/dev/pci/if_wmreg.h

362

#define WTX_DTYP_D __SHIFTIN(1, WTX_DTYP_MASK) /* data */

sys/dev/pci/if_wmreg.h

571

#define MDIC_OP_WRITE __SHIFTIN(1, MDIC_OP_RW_MASK)

sys/dev/pci/if_wmreg.h

572

#define MDIC_OP_READ __SHIFTIN(2, MDIC_OP_RW_MASK)

sys/dev/pci/if_wmreg.h

783

#define RCTL_DTYP(x) __SHIFTIN(x,RCTL_DTYP_MASK)

sys/dev/pci/if_wmreg.h

924

#define TIPG_IPGT(x) __SHIFTIN((x), TIPG_IPGT_MASK) /* IPG transmit time */

sys/dev/pci/ixgbe/ixgbe_osdep.c

82

__SHIFTIN(value, __BITS(31, 16)) | old);

sys/dev/pci/pciconf.c

1152

iohigh = __SHIFTIN(io_base >> 16, PCI_BRIDGE_IOHIGH_BASE) |

sys/dev/pci/pciconf.c

1153

__SHIFTIN(io_limit >> 16, PCI_BRIDGE_IOHIGH_LIMIT);

sys/dev/pci/pciconf.c

1166

io |= __SHIFTIN((io_base >> 8) & PCI_BRIDGE_STATIO_IOADDR,

sys/dev/pci/pciconf.c

1168

io |= __SHIFTIN((io_limit >> 8) & PCI_BRIDGE_STATIO_IOADDR,

sys/dev/pci/pciconf.c

1190

mem = __SHIFTIN((mem_base >> 16) & PCI_BRIDGE_MEMORY_ADDR,

sys/dev/pci/pciconf.c

1192

mem |= __SHIFTIN((mem_limit >> 16) & PCI_BRIDGE_MEMORY_ADDR,

sys/dev/pci/pciconf.c

1216

mem = __SHIFTIN((mem_base >> 16) & PCI_BRIDGE_PREFETCHMEM_ADDR,

sys/dev/pci/pciconf.c

1218

mem |= __SHIFTIN((mem_limit >> 16) & PCI_BRIDGE_PREFETCHMEM_ADDR,

sys/dev/pci/pciconf.c

394

busreg = __SHIFTIN(prim, PCI_BRIDGE_BUS_PRIMARY);

sys/dev/pci/pciconf.c

395

busreg |= __SHIFTIN(sec, PCI_BRIDGE_BUS_SECONDARY);

sys/dev/pci/pciconf.c

396

busreg |= __SHIFTIN(sub, PCI_BRIDGE_BUS_SUBORDINATE);

sys/dev/pci/pciconf.c

650

__SHIFTIN(pb->busno, PCI_BRIDGE_BUS_PRIMARY) |

sys/dev/pci/pciconf.c

651

__SHIFTIN(pb->next_busno, PCI_BRIDGE_BUS_SECONDARY) |

sys/dev/pci/pciconf.c

652

__SHIFTIN(pb->next_busno, PCI_BRIDGE_BUS_SUBORDINATE);

sys/dev/pci/pcireg.h

713

#define PCI_MSI_CTL_EXTMDATA_EN __SHIFTIN(__BIT(10), PCI_MSI_CTL_MASK)

sys/dev/pci/pcireg.h

714

#define PCI_MSI_CTL_EXTMDATA_CAP __SHIFTIN(__BIT(9), PCI_MSI_CTL_MASK)

sys/dev/pci/pcireg.h

715

#define PCI_MSI_CTL_PERVEC_MASK __SHIFTIN(__BIT(8), PCI_MSI_CTL_MASK)

sys/dev/pci/pcireg.h

716

#define PCI_MSI_CTL_64BIT_ADDR __SHIFTIN(__BIT(7), PCI_MSI_CTL_MASK)

sys/dev/pci/pcireg.h

717

#define PCI_MSI_CTL_MME_MASK __SHIFTIN(__BITS(6, 4), PCI_MSI_CTL_MASK)

sys/dev/pci/pcireg.h

719

#define PCI_MSI_CTL_MMC_MASK __SHIFTIN(__BITS(3, 1), PCI_MSI_CTL_MASK)

sys/dev/pci/pcireg.h

721

#define PCI_MSI_CTL_MSI_ENABLE __SHIFTIN(__BIT(0), PCI_MSI_CTL_MASK)

sys/dev/pci/pcireg.h

983

#define PCIE_XCAP_VER_MASK __SHIFTIN(__BITS(3, 0), PCIE_XCAP_MASK)

sys/dev/pci/pcireg.h

987

#define PCIE_XCAP_TYPE_MASK __SHIFTIN(__BITS(7, 4), PCIE_XCAP_MASK)

sys/dev/pci/pcireg.h

998

#define PCIE_XCAP_SI __SHIFTIN(__BIT(8), PCIE_XCAP_MASK) /* Slot Implemented */

sys/dev/pci/pcireg.h

999

#define PCIE_XCAP_IRQ __SHIFTIN(__BITS(13, 9), PCIE_XCAP_MASK)

sys/dev/pci/piixpm.c

572

reg |= __SHIFTIN(smbus->sda, mask);

sys/dev/pci/piixpm.c

610

reg |= __SHIFTIN(smbus->sda_save, mask);

sys/dev/pci/ppb.c

313

val |= __SHIFTIN(PCIE_SLCSR_IND_OFF,

sys/dev/pci/ppb.c

328

val |= __SHIFTIN(PCIE_SLCSR_IND_OFF,

sys/dev/pci/ppb.c

331

val |= __SHIFTIN(PCIE_SLCSR_IND_ON,

sys/dev/pci/qat/qat.c

948

dest[nae] = __SHIFTIN(ae, ETR_AP_DEST_AE) |

sys/dev/pci/qat/qat.c

949

__SHIFTIN(mailbox, ETR_AP_DEST_MAILBOX) |

sys/dev/pci/qat/qat_ae.c

1045

reset &= ~(__SHIFTIN(sc->sc_ae_mask, CAP_GLOBAL_CTL_RESET_AE_MASK));

sys/dev/pci/qat/qat_ae.c

1046

reset &= ~(__SHIFTIN(sc->sc_accel_mask, CAP_GLOBAL_CTL_RESET_ACCEL_MASK));

sys/dev/pci/qat/qat_ae.c

1055

} while ((__SHIFTIN(sc->sc_ae_mask, CAP_GLOBAL_CTL_RESET_AE_MASK) |

sys/dev/pci/qat/qat_ae.c

1056

__SHIFTIN(sc->sc_accel_mask, CAP_GLOBAL_CTL_RESET_ACCEL_MASK))

sys/dev/pci/qat/qat_ae.c

1061

clock |= __SHIFTIN(sc->sc_ae_mask, CAP_GLOBAL_CTL_CLK_EN_AE_MASK);

sys/dev/pci/qat/qat_ae.c

1062

clock |= __SHIFTIN(sc->sc_accel_mask, CAP_GLOBAL_CTL_CLK_EN_ACCEL_MASK);

sys/dev/pci/qat/qat_ae.c

2656

FCU_CTRL_CMD_LOAD | __SHIFTIN(ae, FCU_CTRL_AE));

sys/dev/pci/qat/qat_ae.c

720

ctxen |= __SHIFTIN(ctx_mask, CTX_ENABLES_ENABLE);

sys/dev/pci/qat/qat_ae.c

731

ctxen &= ~(__SHIFTIN(ctx_mask & AE_ALL_CTX, CTX_ENABLES_ENABLE));

sys/dev/pci/qat/qat_ae.c

861

val |= __SHIFTIN(cs_reload, AE_MISC_CONTROL_CS_RELOAD) |

sys/dev/pci/qat/qat_ae.c

862

__SHIFTIN(shared_mode, AE_MISC_CONTROL_ONE_CTX_RELOAD);

sys/dev/pci/qat/qat_hw15reg.h

538

#define LA_FLAGS_PROTO_SNOW_3G __SHIFTIN(4, LA_FLAGS_PROTO)

sys/dev/pci/qat/qat_hw15reg.h

539

#define LA_FLAGS_PROTO_GCM __SHIFTIN(2, LA_FLAGS_PROTO)

sys/dev/pci/qat/qat_hw15reg.h

540

#define LA_FLAGS_PROTO_CCM __SHIFTIN(1, LA_FLAGS_PROTO)

sys/dev/pci/qat/qat_hw15reg.h

541

#define LA_FLAGS_PROTO_NO __SHIFTIN(0, LA_FLAGS_PROTO)

sys/dev/pci/qat/qatreg.h

1359

__SHIFTIN(mode, HW_AUTH_CONFIG_MODE) | \

sys/dev/pci/qat/qatreg.h

1360

__SHIFTIN(algo, HW_AUTH_CONFIG_ALGO) | \

sys/dev/pci/qat/qatreg.h

1361

__SHIFTIN(cmp_len, HW_AUTH_CONFIG_CMPLEN)

sys/dev/pci/qat/qatreg.h

1466

__SHIFTIN(mode, CIPHER_CONFIG_MODE) | \

sys/dev/pci/qat/qatreg.h

1467

__SHIFTIN(algo, CIPHER_CONFIG_ALGO) | \

sys/dev/pci/qat/qatreg.h

1468

__SHIFTIN(convert, CIPHER_CONFIG_CONVERT) | \

sys/dev/pci/qat/qatreg.h

1469

__SHIFTIN(dir, CIPHER_CONFIG_DIR)

sys/dev/pci/qat/qatreg.h

201

(__SHIFTIN(ETR_RING_CONFIG_NEAR_WM_0, \

sys/dev/pci/qat/qatreg.h

203

__SHIFTIN(ETR_RING_CONFIG_NEAR_WM_0, \

sys/dev/pci/qat/qatreg.h

205

__SHIFTIN((size), ETR_RING_CONFIG_RING_SIZE))

sys/dev/pci/qat/qatreg.h

209

(__SHIFTIN((wm_nf), ETR_RING_CONFIG_NEAR_FULL_WM) | \

sys/dev/pci/qat/qatreg.h

210

__SHIFTIN((wm_ne), ETR_RING_CONFIG_NEAR_EMPTY_WM) | \

sys/dev/pci/qat/qatreg.h

211

__SHIFTIN((size), ETR_RING_CONFIG_RING_SIZE))

sys/dev/pci/qat/qatvar.h

1012

offset = __SHIFTIN(ae & sc->sc_ae_mask, AE_LOCAL_AE_MASK) |

sys/dev/pci/qat/qatvar.h

1023

offset = __SHIFTIN(ae & sc->sc_ae_mask, AE_LOCAL_AE_MASK) |

sys/dev/pci/qat/qatvar.h

1033

offset = __SHIFTIN(ae & sc->sc_ae_mask, AE_XFER_AE_MASK) |

sys/dev/pci/qat/qatvar.h

1034

__SHIFTIN(offset, AE_XFER_CSR_MASK);

sys/dev/pci/veritefb.c

931

__SHIFTIN((uint32_t)n, VFB_PCLKPLL_N_MASK) |

sys/dev/pci/veritefb.c

932

__SHIFTIN((uint32_t)p, VFB_PCLKPLL_P_MASK) |

sys/dev/pci/veritefb.c

933

__SHIFTIN((uint32_t)m, VFB_PCLKPLL_M_MASK));

sys/dev/pci/veritefb.c

939

__SHIFTIN((uint32_t)(vm->hsync_start - vm->hdisplay) / 8 - 1,

sys/dev/pci/veritefb.c

941

__SHIFTIN((uint32_t)(vm->hsync_end - vm->hsync_start) / 8 - 1,

sys/dev/pci/veritefb.c

943

__SHIFTIN((uint32_t)(vm->htotal - vm->hsync_end) / 8 - 1,

sys/dev/pci/veritefb.c

945

__SHIFTIN((uint32_t)vm->hdisplay / 8 - 1,

sys/dev/pci/veritefb.c

948

__SHIFTIN((uint32_t)(vm->vsync_start - vm->vdisplay) - 1,

sys/dev/pci/veritefb.c

950

__SHIFTIN((uint32_t)(vm->vsync_end - vm->vsync_start) - 1,

sys/dev/pci/veritefb.c

952

__SHIFTIN((uint32_t)(vm->vtotal - vm->vsync_end) - 1,

sys/dev/pci/veritefb.c

954

__SHIFTIN((uint32_t)vm->vdisplay - 1,

sys/dev/sdmmc/if_bwfm_sdio.c

1420

tmp |= __SHIFTIN(tab[i].val, mask);

sys/dev/sdmmc/sdmmc_mem.c

1695

cmd.c_arg = __SHIFTIN((uint32_t)mio, SD_EXTR_MIO) |

sys/dev/sdmmc/sdmmc_mem.c

1696

__SHIFTIN((uint32_t)fno, SD_EXTR_FNO) |

sys/dev/sdmmc/sdmmc_mem.c

1697

__SHIFTIN(addr, SD_EXTR_ADDR) |

sys/dev/sdmmc/sdmmc_mem.c

1698

__SHIFTIN(datalen - 1, SD_EXTR_LEN);

sys/dev/sdmmc/sdmmc_mem.c

1769

cmd.c_arg = __SHIFTIN((uint32_t)mio, SD_EXTR_MIO) |

sys/dev/sdmmc/sdmmc_mem.c

1770

__SHIFTIN((uint32_t)fno, SD_EXTR_FNO) |

sys/dev/sdmmc/sdmmc_mem.c

1771

__SHIFTIN(addr, SD_EXTR_ADDR) |

sys/dev/sdmmc/sdmmc_mem.c

1772

__SHIFTIN(0, SD_EXTR_LEN);

sys/dev/tprof/tprof.c

726

__SHIFTIN(tfi->tfi_counter, TPROF_SAMPLE_COUNTER_MASK);

sys/dev/tprof/tprof_armv7.c

176

uint32_t pmevtyper = __SHIFTIN(param->p_event, PMEVTYPER_EVTCOUNT);

sys/dev/tprof/tprof_armv8.c

149

uint64_t pmevtyper = __SHIFTIN(param->p_event, PMEVTYPER_EVTCOUNT);

sys/dev/tprof/tprof_types.h

66

#define TPROF_PARAM_VALUE2_SCALE __SHIFTIN(1, TPROF_PARAM_VALUE2_MASK)

sys/dev/tprof/tprof_types.h

67

#define TPROF_PARAM_VALUE2_TRIGGERCOUNT __SHIFTIN(2, TPROF_PARAM_VALUE2_MASK)

sys/dev/tprof/tprof_x86_amd.c

151

__SHIFTIN(event_lo, PESR_EVENT_MASK_LO) |

sys/dev/tprof/tprof_x86_amd.c

152

__SHIFTIN(event_hi, PESR_EVENT_MASK_HI) |

sys/dev/tprof/tprof_x86_amd.c

153

__SHIFTIN(0, PESR_COUNTER_MASK) |

sys/dev/tprof/tprof_x86_amd.c

154

__SHIFTIN(param->p_unit, PESR_UNIT_MASK);

sys/dev/tprof/tprof_x86_intel.c

141

__SHIFTIN(param->p_event, PERFEVTSEL_EVENT_SELECT) |

sys/dev/tprof/tprof_x86_intel.c

142

__SHIFTIN(param->p_unit, PERFEVTSEL_UNIT_MASK) |

sys/dev/usb/ehcireg.h

214

#define EHCI_ITD_SET_STATUS(x) __SHIFTIN((x), EHCI_ITD_STATUS_MASK)

sys/dev/usb/ehcireg.h

221

#define EHCI_ITD_SET_LEN(x) __SHIFTIN((x), EHCI_ITD_LEN_MASK)

sys/dev/usb/ehcireg.h

224

#define EHCI_ITD_SET_IOC(x) __SHIFTIN((x), EHCI_ITD_IOC)

sys/dev/usb/ehcireg.h

227

#define EHCI_ITD_SET_PG(x) __SHIFTIN((x), EHCI_ITD_PG_MASK)

sys/dev/usb/ehcireg.h

230

#define EHCI_ITD_SET_OFFS(x) __SHIFTIN((x), EHCI_ITD_OFFSET_MASK)

sys/dev/usb/ehcireg.h

237

#define EHCI_ITD_SET_EP(x) __SHIFTIN((x), EHCI_ITD_EP_MASK)

sys/dev/usb/ehcireg.h

240

#define EHCI_ITD_SET_DADDR(x) __SHIFTIN((x), EHCI_ITD_DADDR_MASK)

sys/dev/usb/ehcireg.h

243

#define EHCI_ITD_SET_DIR(x) __SHIFTIN((x), EHCI_ITD_DIR_MASK)

sys/dev/usb/ehcireg.h

246

#define EHCI_ITD_SET_MAXPKT(x) __SHIFTIN((x), EHCI_ITD_MAXPKT_MASK)

sys/dev/usb/ehcireg.h

249

#define EHCI_ITD_SET_MULTI(x) __SHIFTIN((x), EHCI_ITD_MULTI_MASK)

sys/dev/usb/ehcireg.h

266

#define EHCI_SITD_SET_DIR(x) __SHIFTIN((x), EHCI_SITD_DIR_MASK)

sys/dev/usb/ehcireg.h

267

#define EHCI_SITD_SET_PORT(x) __SHIFTIN((x), EHCI_SITD_PORT_MASK)

sys/dev/usb/ehcireg.h

268

#define EHCI_SITD_SET_HUBA(x) __SHIFTIN((x), EHCI_SITD_HUBA_MASK)

sys/dev/usb/ehcireg.h

269

#define EHCI_SITD_SET_ENDPT(x) __SHIFTIN((x), EHCI_SITD_ENDPT_MASK)

sys/dev/usb/ehcireg.h

270

#define EHCI_SITD_SET_DADDR(x) __SHIFTIN((x), EHCI_SITD_DADDR_MASK)

sys/dev/usb/ehcireg.h

274

#define EHCI_SITD_SET_SMASK(x) __SHIFTIN((x), EHCI_SITD_SMASK_MASK)

sys/dev/usb/ehcireg.h

275

#define EHCI_SITD_SET_CMASK(x) __SHIFTIN((x), EHCI_SITD_CMASK_MASK)

sys/dev/usb/ehcireg.h

281

#define EHCI_SITD_SET_LEN(x) __SHIFTIN((x), EHCI_SITD_LENGTH_MASK)

sys/dev/usb/ehcireg.h

316

#define EHCI_QTD_SET_STATUS(x) __SHIFTIN((x), EHCI_QTD_STATUS_MASK)

sys/dev/usb/ehcireg.h

328

#define EHCI_QTD_SET_PID(x) __SHIFTIN((x), EHCI_QTD_PID_MASK)

sys/dev/usb/ehcireg.h

334

#define EHCI_QTD_SET_CERR(x) __SHIFTIN((x), EHCI_QTD_CERR_MASK)

sys/dev/usb/ehcireg.h

337

#define EHCI_QTD_SET_C_PAGE(x) __SHIFTIN((x), EHCI_QTD_C_PAGE_MASK)

sys/dev/usb/ehcireg.h

342

#define EHCI_QTD_SET_BYTES(x) __SHIFTIN((x), EHCI_QTD_BYTES_MASK)

sys/dev/usb/ehcireg.h

345

#define EHCI_QTD_SET_TOGGLE(x) __SHIFTIN((x), EHCI_QTD_TOGGLE_MASK)

sys/dev/usb/ehcireg.h

360

#define EHCI_QH_SET_ADDR(x) __SHIFTIN((x), EHCI_QH_ADDR_MASK)

sys/dev/usb/ehcireg.h

365

#define EHCI_QH_SET_ENDPT(x) __SHIFTIN((x), EHCI_QH_ENDPT_MASK)

sys/dev/usb/ehcireg.h

368

#define EHCI_QH_SET_EPS(x) __SHIFTIN((x), EHCI_QH_EPS_MASK)

sys/dev/usb/ehcireg.h

378

#define EHCI_QH_SET_MPL(x) __SHIFTIN((x), EHCI_QH_MPL_MASK)

sys/dev/usb/ehcireg.h

383

#define EHCI_QH_SET_NRL(x) __SHIFTIN((x), EHCI_QH_NRL_MASK)

sys/dev/usb/ehcireg.h

387

#define EHCI_QH_SET_SMASK(x) __SHIFTIN((x), EHCI_QH_SMASK_MASK)

sys/dev/usb/ehcireg.h

390

#define EHCI_QH_SET_CMASK(x) __SHIFTIN((x), EHCI_QH_CMASK_MASK)

sys/dev/usb/ehcireg.h

393

#define EHCI_QH_SET_HUBA(x) __SHIFTIN((x), EHCI_QH_HUBA_MASK)

sys/dev/usb/ehcireg.h

396

#define EHCI_QH_SET_PORT(x) __SHIFTIN((x), EHCI_QH_PORT_MASK)

sys/dev/usb/ehcireg.h

399

#define EHCI_QH_SET_MULT(x) __SHIFTIN((x), EHCI_QH_MULTI_MASK)

sys/dev/usb/ehcivar.h

266

val |= __SHIFTIN(data, mask);

sys/dev/usb/ehcivar.h

282

val |= __SHIFTIN(data, mask);

sys/dev/usb/if_muevar.h

37

#define MUE_RX_CMD_A_PID_TCP __SHIFTIN(1, MUE_RX_CMD_A_PID)

sys/dev/usb/if_muevar.h

38

#define MUE_RX_CMD_A_PID_UDP __SHIFTIN(2, MUE_RX_CMD_A_PID)

sys/dev/usb/if_muevar.h

39

#define MUE_RX_CMD_A_PID_IP __SHIFTIN(3, MUE_RX_CMD_A_PID)

sys/dev/usb/ohcireg.h

105

#define OHCI_FM_SET_FSMPS(x) __SHIFTIN((x), OHCI_FM_FSMPS_MASK)

sys/dev/usb/ohcireg.h

121

#define OHCI_RHD_SET_POTPGT(x) __SHIFTIN((x), OHCI_RHD_POTPGT_MASK)

sys/dev/usb/ohcireg.h

160

#define OHCI_ED_SET_FA(x) __SHIFTIN((x), OHCI_ED_ADDR_MASK)

sys/dev/usb/ohcireg.h

163

#define OHCI_ED_SET_EN(x) __SHIFTIN((x), OHCI_ED_EN_MASK)

sys/dev/usb/ohcireg.h

166

#define OHCI_ED_SET_DIR(x) __SHIFTIN((x), OHCI_ED_DIR_MASK)

sys/dev/usb/ohcireg.h

174

#define OHCI_ED_SET_FORMAT(x) __SHIFTIN((x), OHCI_ED_FORMAT_MASK)

sys/dev/usb/ohcireg.h

179

#define OHCI_ED_SET_MAXP(x) __SHIFTIN((x), OHCI_ED_MAXP_MASK)

sys/dev/usb/ohcireg.h

199

#define OHCI_TD_SET_DP(x) __SHIFTIN((x), OHCI_TD_DP_MASK)

sys/dev/usb/ohcireg.h

205

#define OHCI_TD_SET_DI(x) __SHIFTIN((x), OHCI_TD_DI_MASK)

sys/dev/usb/ohcireg.h

209

#define OHCI_TD_SET_TOGGLE(x) __SHIFTIN((x), OHCI_TD_TOGGLE_MASK)

sys/dev/usb/ohcireg.h

217

#define OHCI_TD_SET_CC(x) __SHIFTIN((x), OHCI_TD_CC_MASK)

sys/dev/usb/ohcireg.h

237

#define OHCI_ITD_SET_SF(x) __SHIFTIN((x), OHCI_ITD_SF_MASK)

sys/dev/usb/ohcireg.h

240

#define OHCI_ITD_SET_DI(x) __SHIFTIN((x), OHCI_ITD_DI_MASK)

sys/dev/usb/ohcireg.h

243

#define OHCI_ITD_SET_FC(x) __SHIFTIN(((x) - 1), OHCI_ITD_FC_MASK)

sys/dev/usb/ohcireg.h

246

#define OHCI_ITD_SET_CC(x) __SHIFTIN((x), OHCI_ITD_CC_MASK)

sys/dev/usb/ohcireg.h

55

#define OHCI_CBSR_SET(x) __SHIFTIN((x), OHCI_CBSR_MASK)

sys/dev/usb/ohcireg.h

65

#define OHCI_SET_HCFS(x) __SHIFTIN((x), OHCI_HCFS_MASK)

sys/dev/usb/slurm.c

375

sysconfig2 |= __SHIFTIN(volume / SI470X_VOLFACT, SI470X_VOLUME);

sys/dev/usb/uhcireg.h

166

#define UHCI_TD_SET_ERRCNT(n) __SHIFTIN((n), UHCI_TD_ERRCNT_MASK)

sys/dev/usb/uhcireg.h

173

#define UHCI_TD_SET_PID(p) __SHIFTIN((p), UHCI_TD_PID_MASK)

sys/dev/usb/uhcireg.h

176

#define UHCI_TD_SET_DEVADDR(a) __SHIFTIN((a), UHCI_TD_DEVADDR_MASK)

sys/dev/usb/uhcireg.h

179

#define UHCI_TD_SET_ENDPT(e) __SHIFTIN((e), UHCI_TD_ENDPT_MASK)

sys/dev/usb/uhcireg.h

182

#define UHCI_TD_SET_DT(t) __SHIFTIN((t), UHCI_TD_DT_MASK)

sys/dev/usb/uhcireg.h

186

__SHIFTIN((((l)-1) & __SHIFTOUT_MASK(UHCI_TD_MAXLEN_MASK)), UHCI_TD_MAXLEN_MASK)

sys/dev/usb/usb.h

600

#define UPS_PORT_LS_SET(x) __SHIFTIN(x, UPS_PORT_LS_MASK)

sys/dev/usb/uslsa.c

555

SERIAL_CTS_HANDSHAKE | __SHIFTIN(1, SERIAL_DTR_MASK);

sys/dev/usb/uslsa.c

556

ulFlowReplace = __SHIFTIN(2, SERIAL_RTS_MASK);

sys/dev/usb/uslsa.c

558

ulControlHandshake = __SHIFTIN(1, SERIAL_DTR_MASK);

sys/dev/usb/uslsa.c

559

ulFlowReplace = __SHIFTIN(1, SERIAL_RTS_MASK);

sys/dev/usb/uslsareg.h

83

#define SLSA_RV_LINE_CTL_STOP_1 __SHIFTIN(0, SLSA_RV_LINE_CTL_STOP)

sys/dev/usb/uslsareg.h

84

#define SLSA_RV_LINE_CTL_STOP_1_5 __SHIFTIN(1, SLSA_RV_LINE_CTL_STOP)

sys/dev/usb/uslsareg.h

85

#define SLSA_RV_LINE_CTL_STOP_2 __SHIFTIN(2, SLSA_RV_LINE_CTL_STOP)

sys/dev/usb/uslsareg.h

87

#define SLSA_RV_LINE_CTL_PARITY_NONE __SHIFTIN(0, SLSA_RV_LINE_CTL_PARITY)

sys/dev/usb/uslsareg.h

88

#define SLSA_RV_LINE_CTL_PARITY_ODD __SHIFTIN(1, SLSA_RV_LINE_CTL_PARITY)

sys/dev/usb/uslsareg.h

89

#define SLSA_RV_LINE_CTL_PARITY_EVEN __SHIFTIN(2, SLSA_RV_LINE_CTL_PARITY)

sys/dev/usb/uslsareg.h

90

#define SLSA_RV_LINE_CTL_PARITY_MARK __SHIFTIN(3, SLSA_RV_LINE_CTL_PARITY)

sys/dev/usb/uslsareg.h

91

#define SLSA_RV_LINE_CTL_PARITY_SPACE __SHIFTIN(4, SLSA_RV_LINE_CTL_PARITY)

sys/dev/usb/uslsareg.h

93

#define SLSA_RV_LINE_CTL_LEN_5 __SHIFTIN(5, SLSA_RV_LINE_CTL_LEN)

sys/dev/usb/uslsareg.h

94

#define SLSA_RV_LINE_CTL_LEN_6 __SHIFTIN(6, SLSA_RV_LINE_CTL_LEN)

sys/dev/usb/uslsareg.h

95

#define SLSA_RV_LINE_CTL_LEN_7 __SHIFTIN(7, SLSA_RV_LINE_CTL_LEN)

sys/dev/usb/uslsareg.h

96

#define SLSA_RV_LINE_CTL_LEN_8 __SHIFTIN(8, SLSA_RV_LINE_CTL_LEN)

sys/dev/usb/xhci.c

327

val |= __SHIFTIN(value, mask);

sys/dev/usb/xhcireg.h

198

#define XHCI_PS_PLS_SET(x) __SHIFTIN((x), XHCI_PS_PLS_MASK) /* RW - port link state */

sys/dev/usb/xhcireg.h

230

#define XHCI_PS_PIC_SET(x) __SHIFTIN((x), XHCI_PS_PIC_MASK)

sys/dev/usb/xhcireg.h

252

#define XHCI_PM3_U1TO_SET(x) __SHIFTIN((x), XHCI_PM3_U1TO_MASK)

sys/dev/usb/xhcireg.h

255

#define XHCI_PM3_U2TO_SET(x) __SHIFTIN((x), XHCI_PM3_U2TO_MASK)

sys/dev/usb/xhcireg.h

264

#define XHCI_PM2_BESL_SET(x) __SHIFTIN((x), XHCI_PM2_BESL_MASK)

sys/dev/usb/xhcireg.h

267

#define XHCI_PM2_L1SLOT_SET(x) __SHIFTIN((x), XHCI_PM2_L1SLOT_MASK)

sys/dev/usb/xhcireg.h

305

#define XHCI_IMOD_IVAL_SET(x) __SHIFTIN((x), XHCI_IMOD_IVAL_MASK)

sys/dev/usb/xhcireg.h

308

#define XHCI_IMOD_ICNT_SET(x) __SHIFTIN((x), XHCI_IMOD_ICNT_MASK)

sys/dev/usb/xhcireg.h

317

#define XHCI_ERSTS_SET(x) __SHIFTIN((x), XHCI_ERSTS_MASK)

sys/dev/usb/xhcireg.h

336

#define XHCI_DB_TARGET_SET(x) __SHIFTIN((x), XHCI_DB_TARGET_MASK)

sys/dev/usb/xhcireg.h

339

#define XHCI_DB_SID_SET(x) __SHIFTIN((x), XHCI_DB_SID_MASK)

sys/dev/usb/xhcireg.h

405

#define XHCI_TRB_2_ERROR_SET(x) __SHIFTIN((x), XHCI_TRB_2_ERROR_MASK)

sys/dev/usb/xhcireg.h

409

#define XHCI_TRB_2_TDSZ_SET(x) __SHIFTIN((x), XHCI_TRB_2_TDSZ_MASK)

sys/dev/usb/xhcireg.h

412

#define XHCI_TRB_2_REM_SET(x) __SHIFTIN((x), XHCI_TRB_2_REM_MASK)

sys/dev/usb/xhcireg.h

416

#define XHCI_TRB_2_BYTES_SET(x) __SHIFTIN((x), XHCI_TRB_2_BYTES_MASK)

sys/dev/usb/xhcireg.h

419

#define XHCI_TRB_2_IRQ_SET(x) __SHIFTIN((x), XHCI_TRB_2_IRQ_MASK)

sys/dev/usb/xhcireg.h

422

#define XHCI_TRB_2_STREAM_SET(x) __SHIFTIN((x), XHCI_TRB_2_STREAM_MASK)

sys/dev/usb/xhcireg.h

426

#define XHCI_TRB_3_TYPE_SET(x) __SHIFTIN((x), XHCI_TRB_3_TYPE_MASK)

sys/dev/usb/xhcireg.h

437

#define XHCI_TRB_3_TBC_SET(x) __SHIFTIN((x), XHCI_TRB_3_TBC_MASK)

sys/dev/usb/xhcireg.h

444

#define XHCI_TRB_3_TRT_NONE __SHIFTIN(0U, XHCI_TRB_3_TRT_MASK)

sys/dev/usb/xhcireg.h

445

#define XHCI_TRB_3_TRT_OUT __SHIFTIN(2U, XHCI_TRB_3_TRT_MASK)

sys/dev/usb/xhcireg.h

446

#define XHCI_TRB_3_TRT_IN __SHIFTIN(3U, XHCI_TRB_3_TRT_MASK)

sys/dev/usb/xhcireg.h

450

#define XHCI_TRB_3_TLBPC_SET(x) __SHIFTIN((x), XHCI_TRB_3_TLBPC_MASK)

sys/dev/usb/xhcireg.h

453

#define XHCI_TRB_3_EP_SET(x) __SHIFTIN((x), XHCI_TRB_3_EP_MASK)

sys/dev/usb/xhcireg.h

456

#define XHCI_TRB_3_FRID_SET(x) __SHIFTIN((x), XHCI_TRB_3_FRID_MASK)

sys/dev/usb/xhcireg.h

461

#define XHCI_TRB_3_VFID_SET(x) __SHIFTIN((x), XHCI_TRB_3_VFID_MASK)

sys/dev/usb/xhcireg.h

464

#define XHCI_TRB_3_SLOT_SET(x) __SHIFTIN((x), XHCI_TRB_3_SLOT_MASK)

sys/dev/usb/xhcireg.h

547

#define XHCI_SCTX_0_ROUTE_SET(x) __SHIFTIN((x), XHCI_SCTX_0_ROUTE_MASK)

sys/dev/usb/xhcireg.h

550

#define XHCI_SCTX_0_SPEED_SET(x) __SHIFTIN((x), XHCI_SCTX_0_SPEED_MASK)

sys/dev/usb/xhcireg.h

552

#define XHCI_SCTX_0_MTT_SET(x) __SHIFTIN((x), XHCI_SCTX_0_MTT_MASK)

sys/dev/usb/xhcireg.h

555

#define XHCI_SCTX_0_HUB_SET(x) __SHIFTIN((x), XHCI_SCTX_0_HUB_MASK)

sys/dev/usb/xhcireg.h

558

#define XHCI_SCTX_0_CTX_NUM_SET(x) __SHIFTIN((x), XHCI_SCTX_0_CTX_NUM_MASK)

sys/dev/usb/xhcireg.h

562

#define XHCI_SCTX_1_MAX_EL_SET(x) __SHIFTIN((x), XHCI_SCTX_1_MAX_EL_MASK)

sys/dev/usb/xhcireg.h

565

#define XHCI_SCTX_1_RH_PORT_SET(x) __SHIFTIN((x), XHCI_SCTX_1_RH_PORT_MASK)

sys/dev/usb/xhcireg.h

568

#define XHCI_SCTX_1_NUM_PORTS_SET(x) __SHIFTIN((x), XHCI_SCTX_1_NUM_PORTS_MASK)

sys/dev/usb/xhcireg.h

572

#define XHCI_SCTX_2_TT_HUB_SID_SET(x) __SHIFTIN((x), XHCI_SCTX_2_TT_HUB_SID_MASK)

sys/dev/usb/xhcireg.h

575

#define XHCI_SCTX_2_TT_PORT_NUM_SET(x) __SHIFTIN((x), XHCI_SCTX_2_TT_PORT_NUM_MASK)

sys/dev/usb/xhcireg.h

578

#define XHCI_SCTX_2_TT_THINK_TIME_SET(x) __SHIFTIN((x), XHCI_SCTX_2_TT_THINK_TIME_MASK)

sys/dev/usb/xhcireg.h

581

#define XHCI_SCTX_2_IRQ_TARGET_SET(x) __SHIFTIN((x), XHCI_SCTX_2_IRQ_TARGET_MASK)

sys/dev/usb/xhcireg.h

585

#define XHCI_SCTX_3_DEV_ADDR_SET(x) __SHIFTIN((x), XHCI_SCTX_3_DEV_ADDR_MASK)

sys/dev/usb/xhcireg.h

588

#define XHCI_SCTX_3_SLOT_STATE_SET(x) __SHIFTIN((x), XHCI_SCTX_3_SLOT_STATE_MASK)

sys/dev/usb/xhcireg.h

600

#define XHCI_EPCTX_0_EPSTATE_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_EPSTATE_MASK)

sys/dev/usb/xhcireg.h

608

#define XHCI_EPCTX_0_MULT_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_MULT_MASK)

sys/dev/usb/xhcireg.h

611

#define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_MAXP_STREAMS_MASK)

sys/dev/usb/xhcireg.h

614

#define XHCI_EPCTX_0_LSA_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_LSA_MASK)

sys/dev/usb/xhcireg.h

617

#define XHCI_EPCTX_0_IVAL_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_IVAL_MASK)

sys/dev/usb/xhcireg.h

620

#define XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_MASK)

sys/dev/usb/xhcireg.h

624

#define XHCI_EPCTX_1_CERR_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_CERR_MASK)

sys/dev/usb/xhcireg.h

627

#define XHCI_EPCTX_1_EPTYPE_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_EPTYPE_MASK)

sys/dev/usb/xhcireg.h

630

#define XHCI_EPCTX_1_HID_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_HID_MASK)

sys/dev/usb/xhcireg.h

633

#define XHCI_EPCTX_1_MAXB_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_MAXB_MASK)

sys/dev/usb/xhcireg.h

636

#define XHCI_EPCTX_1_MAXP_SIZE_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_MAXP_SIZE_MASK)

sys/dev/usb/xhcireg.h

641

#define XHCI_EPCTX_2_DCS_SET(x) __SHIFTIN((x), XHCI_EPCTX_2_DCS_MASK)

sys/dev/usb/xhcireg.h

646

#define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) __SHIFTIN((x), XHCI_EPCTX_4_AVG_TRB_LEN_MASK)

sys/dev/usb/xhcireg.h

649

#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) __SHIFTIN((x), XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_MASK)

sys/dev/vmt/vmtvar.h

147

#define X86_IO_W7_SIZE(n) __SHIFTIN((n), X86_IO_W7_SIZE_MASK)

sys/dev/vmt/vmtvar.h

153

#define X86_IO_W7_IMM(imm) __SHIFTIN((imm), X86_IO_W7_IMM_MASK)

sys/dev/vmt/vmtvar.h

44

(__SHIFTIN((hi), VM_REG_HIGH_MASK) | __SHIFTIN((low), VM_REG_LOW_MASK))

sys/kern/subr_xcall.c

199

return __SHIFTIN(XC_IPL_SOFTSERIAL, XC_IPL_MASK);

sys/kern/subr_xcall.c

203

return __SHIFTIN(XC_IPL_SOFTNET, XC_IPL_MASK);

sys/kern/subr_xcall.c

207

return __SHIFTIN(XC_IPL_SOFTBIO, XC_IPL_MASK);

sys/kern/subr_xcall.c

211

return __SHIFTIN(XC_IPL_SOFTCLOCK, XC_IPL_MASK);

sys/sys/agpio.h

56

| __SHIFTIN((v), AGP_MODE_RQ))

sys/sys/agpio.h

58

| __SHIFTIN((v), AGP_MODE_ARQSZ))

sys/sys/agpio.h

60

| __SHIFTIN((v), ~AGP_MODE_CAL))

sys/sys/agpio.h

62

| __SHIFTIN((v), AGP_MODE_SBA))

sys/sys/agpio.h

64

| __SHIFTIN((v), AGP_MODE_AGP))

sys/sys/agpio.h

66

| __SHIFTIN((v), AGP_MODE_4G))

sys/sys/agpio.h

68

| __SHIFTIN((v), AGP_MODE_FW))

sys/sys/agpio.h

70

| __SHIFTIN((v), AGP_MODE_MODE_3))

sys/sys/agpio.h

72

| __SHIFTIN((v), AGP_MODE_RATE))

sys/sys/futex.h

101

(__SHIFTIN((op) & 0xf, FUTEX_OP_OP_MASK) |\

sys/sys/futex.h

102

__SHIFTIN((oparg) & 0xfff, FUTEX_OP_OPARG_MASK)|\

sys/sys/futex.h

103

__SHIFTIN((cmp) & 0xf, FUTEX_OP_CMP_MASK) |\

sys/sys/futex.h

104

__SHIFTIN((cmparg) & 0xfff, FUTEX_OP_CMPARG_MASK))

sys/uvm/uvm_page.h

465

pg->phys_addr |= __SHIFTIN(fl, UVM_PHYSADDR_FREELIST);

sys/uvm/uvm_page.h

473

pg->phys_addr |= __SHIFTIN(b, UVM_PHYSADDR_BUCKET);

tests/kernel/arch/hppa/execregs.c

66

| __SHIFTIN(1, __BITS(42,41)) /* round toward zero */

tests/kernel/arch/hppa/execregs.c

67

| __SHIFTIN(0, __BIT(38)) /* no delayed trap */

tests/kernel/arch/hppa/execregs.c

68

| __SHIFTIN(1, __BIT(37)) /* Denormalized As Zero */

tests/kernel/arch/hppa/execregs.c

69

| __SHIFTIN(0, __BITS(36,32)) /* exceptions masked */

tests/kernel/arch/x86/sig_fpu.c

145

rcpc_exc |= __SHIFTIN(3, X87_CW_PC); /* extended */

tests/kernel/arch/x86/sig_fpu.c

293

before.mxcsr |= __SHIFTIN(exc, MXCSR_EXCMASK);

tests/kernel/arch/x86/sig_fpu.c

294

before.mxcsr |= __SHIFTIN(exc, MXCSR_EXCFLAG);