#ifndef _OCTEON_POWVAR_H_
#define _OCTEON_POWVAR_H_
#include <sys/cpu.h>
#include <mips/cavium/octeonreg.h>
#define POW_TAG_TYPE_ORDERED 0
#define POW_TAG_TYPE_ATOMIC 1
#define POW_TAG_TYPE_NULL 2
#define POW_TAG_TYPE_NULL_NULL 3
#define POW_TAG_OP_SWTAG 0
#define POW_TAG_OP_SWTAG_FULL 1
#define POW_TAG_OP_SWTAG_DESCHED 2
#define POW_TAG_OP_DESCHED 3
#define POW_TAG_OP_ADDWQ 4
#define POW_TAG_OP_UPD_WQP_GRP 5
#define POW_TAG_OP_CLR_NSCHED 7
#define POW_TAG_OP_NOP 15
#define POW_WAIT 1
#define POW_NO_WAIT 0
#define POW_WORKQ_IRQ(group) (group)
struct octpow_softc {
device_t sc_dev;
bus_space_tag_t sc_regt;
bus_space_handle_t sc_regh;
int sc_port;
int sc_int_pc_base;
};
struct octpow_attach_args {
int aa_port;
bus_space_tag_t aa_regt;
};
void octpow_config(struct octpow_softc *, int);
void octpow_error_int_enable(void *, int);
uint64_t octpow_error_int_summary(void *);
int octpow_ring_reduce(void *);
int octpow_ring_grow(void *);
int octpow_ring_size(void);
int octpow_ring_intr(void);
#define _POW_RD8(sc, off) \
bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off))
#define _POW_WR8(sc, off, v) \
bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v))
#define _POW_GROUP_RD8(sc, pi, off) \
bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, \
(off) + sizeof(uint64_t) * (pi)->pi_group)
#define _POW_GROUP_WR8(sc, pi, off, v) \
bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, \
(off) + sizeof(uint64_t) * (pi)->pi_group, (v))
extern struct octpow_softc octpow_softc;
static __inline uint64_t
octpow_ops_get_work_load(
int wait)
{
uint64_t ptr =
OCTEON_ADDR_IO_DID(POW_MAJOR_DID, POW_OP_SUBDID_GET_WORK) |
(wait ? POW_GET_WORK_LOAD_WAIT : 0);
return octeon_xkphys_read_8(ptr);
}
static __inline void
octpow_ops_get_work_iobdma(
int scraddr,
int wait)
{
const int scrindex = scraddr / sizeof(uint64_t);
uint64_t value = IOBDMA_CREATE(POW_MAJOR_DID,
POW_IOBDMA_SUBDID_GET_WORK, scrindex, POW_IOBDMA_LEN,
wait ? POW_IOBDMA_GET_WORK_WAIT : 0);
octeon_iobdma_write_8(value);
}
static __inline void
octpow_ops_null_rd_iobdma(
int scraddr)
{
const int scrindex = scraddr / sizeof(uint64_t);
uint64_t value = IOBDMA_CREATE(POW_MAJOR_DID,
POW_IOBDMA_SUBDID_NULL_RD, scrindex, POW_IOBDMA_LEN, 0);
octeon_iobdma_write_8(value);
}
static __inline void
octpow_store(
int subdid,
uint64_t addr,
int no_sched,
int index,
int op,
int qos,
int grp,
int type,
uint32_t tag)
{
uint64_t ptr = OCTEON_ADDR_IO_DID(POW_MAJOR_DID, subdid) |
__SHIFTIN(addr, POW_PHY_ADDR_STORE_ADDR);
uint64_t args =
__SHIFTIN(no_sched, POW_STORE_DATA_NO_SCHED) |
__SHIFTIN(index, POW_STORE_DATA_INDEX) |
__SHIFTIN(op, POW_STORE_DATA_OP) |
__SHIFTIN(qos, POW_STORE_DATA_QOS) |
__SHIFTIN(grp, POW_STORE_DATA_GRP) |
__SHIFTIN(type, POW_STORE_DATA_TYPE) |
__SHIFTIN(tag, POW_STORE_DATA_TAG);
octeon_xkphys_write_8(ptr, args);
}
static __inline void
octpow_ops_swtag(int type, uint32_t tag)
{
octpow_store(
POW_STORE_SUBDID_OTHER,
0,
0,
0,
POW_TAG_OP_SWTAG,
0,
0,
type,
tag);
}
static __inline void
octpow_ops_swtag_full(paddr_t addr, int grp, int type, uint32_t tag)
{
octpow_store(
POW_STORE_SUBDID_SWTAG_FULL,
addr,
0,
0,
POW_TAG_OP_SWTAG_FULL,
0,
grp,
type,
tag);
}
static __inline void
octpow_ops_swtag_desched(int no_sched, int grp, int type, uint32_t tag)
{
octpow_store(
POW_STORE_SUBDID_DESCHED,
0,
no_sched,
0,
POW_TAG_OP_SWTAG_DESCHED,
0,
grp,
type,
tag);
}
static __inline void
octpow_ops_desched(int no_sched)
{
octpow_store(
POW_STORE_SUBDID_DESCHED,
0,
no_sched,
0,
POW_TAG_OP_DESCHED,
0,
0,
0,
0);
}
static __inline void
octpow_ops_addwq(paddr_t addr, int qos, int grp, int type, uint32_t tag)
{
octpow_store(
POW_STORE_SUBDID_OTHER,
addr,
0,
0,
POW_TAG_OP_ADDWQ,
qos,
grp,
type,
tag);
}
static __inline void
octpow_ops_upd_wqp_grp(paddr_t addr, int grp)
{
octpow_store(
POW_STORE_SUBDID_OTHER,
addr,
0,
0,
POW_TAG_OP_UPD_WQP_GRP,
0,
grp,
0,
0);
}
static __inline void
octpow_ops_clr_nsched(paddr_t addr, int index)
{
octpow_store(
POW_STORE_SUBDID_OTHER,
addr,
0,
index,
POW_TAG_OP_CLR_NSCHED,
0,
0,
0,
0);
}
static __inline void
octpow_ops_nop(void)
{
octpow_store(
POW_STORE_SUBDID_OTHER,
0,
0,
0,
POW_TAG_OP_NOP,
0,
0,
0,
0);
}
static __inline int
octpow_tag_sw_pending(void)
{
int result;
__asm volatile (
" .set push\n"
" .set noreorder\n"
" .set arch=mips64r2\n"
" rdhwr %0, $30\n"
" .set pop\n"
: "=r" (result));
return result == 0;
}
static inline void
octpow_tag_sw_wait(void)
{
while (octpow_tag_sw_pending())
continue;
}
static __inline void
octpow_work_request_async(uint64_t scraddr, uint64_t wait)
{
octpow_ops_get_work_iobdma(scraddr, wait);
}
static __inline uint64_t *
octpow_work_response_async(uint64_t scraddr)
{
uint64_t result;
OCTEON_SYNCIOBDMA;
result = octeon_cvmseg_read_8(scraddr);
paddr_t addr = result & POW_IOBDMA_GET_WORK_RESULT_ADDR;
if (result & POW_IOBDMA_GET_WORK_RESULT_NO_WORK)
return NULL;
#ifdef __mips_n32
KASSERT(addr < MIPS_PHYS_MASK);
return (uint64_t *)MIPS_PHYS_TO_KSEG0(addr);
#else
return (uint64_t *)MIPS_PHYS_TO_XKPHYS_CACHED(addr);
#endif
}
static __inline void
octpow_config_int_pc(struct octpow_softc *sc, int unit)
{
uint64_t wq_int_pc;
uint64_t pc_thr;
static uint64_t cpu_clock_hz;
if (cpu_clock_hz == 0)
cpu_clock_hz = curcpu()->ci_cpu_freq;
pc_thr = (cpu_clock_hz) / (unit * 16 * 256);
wq_int_pc = __SHIFTIN(pc_thr, POW_WQ_INT_PC_PC_THR);
_POW_WR8(sc, POW_WQ_INT_PC_OFFSET, wq_int_pc);
}
static __inline void
octpow_config_int_pc_rate(struct octpow_softc *sc, int rate)
{
octpow_config_int_pc(sc, sc->sc_int_pc_base / rate);
}
#endif