arch/arm/include/asm/vdso/cp15.h

14

#define __ACCESS_CP15(CRn, Op1, CRm, Op2) \

arch/arm/include/asm/vdso/cp15.h

15

"mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32

arch/arm/include/asm/vdso/cp15.h

16

#define __ACCESS_CP15_64(Op1, CRm) \

arch/arm/include/asm/vdso/cp15.h

17

"mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64

arch/arm64/kvm/emulate-nested.c

2442

encoding = sys_reg(sr->Op0, sr->Op1, sr->CRn, sr->CRm, sr->Op2);

arch/arm64/kvm/hyp/nvhe/sys_regs.c

383

Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \

arch/arm64/kvm/sys_regs.c

2742

Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \

arch/arm64/kvm/sys_regs.c

3885

u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

3896

u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

3914

u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

3941

u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

4033

u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

4057

u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

4112

u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

4138

u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

4150

u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

arch/arm64/kvm/sys_regs.c

4411

{ AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), \

arch/arm64/kvm/sys_regs.c

4414

{ Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_dbg_wb_reg, NULL, n }, \

arch/arm64/kvm/sys_regs.c

4416

{ Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_dbg_wb_reg, NULL, n }, \

arch/arm64/kvm/sys_regs.c

4418

{ Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_dbg_wb_reg, NULL, n }

arch/arm64/kvm/sys_regs.c

4421

{ AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), \

arch/arm64/kvm/sys_regs.c

4431

{ Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },

arch/arm64/kvm/sys_regs.c

4433

{ Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4437

{ Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4440

{ Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },

arch/arm64/kvm/sys_regs.c

4442

{ Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },

arch/arm64/kvm/sys_regs.c

4445

{ Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4447

{ Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4452

{ Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4454

{ Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4457

{ Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },

arch/arm64/kvm/sys_regs.c

4469

{ Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4473

{ Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 },

arch/arm64/kvm/sys_regs.c

4476

{ Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 },

arch/arm64/kvm/sys_regs.c

4480

{ Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4483

{ Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4497

{ Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4500

{ Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4502

{ Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4504

{ Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4506

{ Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4508

{ Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4510

{ Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },

arch/arm64/kvm/sys_regs.c

4516

{ Op1( 0), CRm( 1), .access = trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4519

{ Op1( 0), CRm( 2), .access = trap_raz_wi },

arch/arm64/kvm/sys_regs.c

4524

Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \

arch/arm64/kvm/sys_regs.c

4544

{ Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },

arch/arm64/kvm/sys_regs.c

4545

{ Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },

arch/arm64/kvm/sys_regs.c

4547

{ AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },

arch/arm64/kvm/sys_regs.c

4549

{ AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },

arch/arm64/kvm/sys_regs.c

4550

{ Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },

arch/arm64/kvm/sys_regs.c

4551

{ Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },

arch/arm64/kvm/sys_regs.c

4553

{ AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },

arch/arm64/kvm/sys_regs.c

4555

{ AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },

arch/arm64/kvm/sys_regs.c

4556

{ Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },

arch/arm64/kvm/sys_regs.c

4559

{ Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },

arch/arm64/kvm/sys_regs.c

4560

{ Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },

arch/arm64/kvm/sys_regs.c

4562

{ Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },

arch/arm64/kvm/sys_regs.c

4564

{ Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },

arch/arm64/kvm/sys_regs.c

4566

{ AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },

arch/arm64/kvm/sys_regs.c

4568

{ AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },

arch/arm64/kvm/sys_regs.c

4573

{ Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },

arch/arm64/kvm/sys_regs.c

4574

{ Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },

arch/arm64/kvm/sys_regs.c

4575

{ Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },

arch/arm64/kvm/sys_regs.c

4599

{ AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },

arch/arm64/kvm/sys_regs.c

4601

{ AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },

arch/arm64/kvm/sys_regs.c

4603

{ AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },

arch/arm64/kvm/sys_regs.c

4605

{ AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },

arch/arm64/kvm/sys_regs.c

4630

{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },

arch/arm64/kvm/sys_regs.c

4703

{ Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },

arch/arm64/kvm/sys_regs.c

4704

{ Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },

arch/arm64/kvm/sys_regs.c

4707

{ Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access },

arch/arm64/kvm/sys_regs.c

4709

{ Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },

arch/arm64/kvm/sys_regs.c

4713

{ Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },

arch/arm64/kvm/sys_regs.c

4715

{ Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */

arch/arm64/kvm/sys_regs.c

4717

{ Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },

arch/arm64/kvm/sys_regs.c

4718

{ Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */

arch/arm64/kvm/sys_regs.c

4720

{ Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */

arch/arm64/kvm/sys_regs.c

4856

params.Op1 = (esr >> 16) & 0xf;

arch/arm64/kvm/sys_regs.c

4902

params->Op1 = 0;

arch/arm64/kvm/sys_regs.c

5048

if (params.Op1 == 0 && params.CRn == 0 &&

arch/arm64/kvm/sys_regs.c

5051

if (params.Op1 == 1 && params.CRn == 0 &&

arch/arm64/kvm/sys_regs.c

5346

params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)

arch/arm64/kvm/sys_regs.c

5559

(reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |

arch/arm64/kvm/sys_regs.c

622

switch (p->Op1) {

arch/arm64/kvm/sys_regs.c

660

if (p->Op1 == 4) { /* ICC_SRE_EL2 */

arch/arm64/kvm/sys_regs.h

121

p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, str_write_read(p->is_write));

arch/arm64/kvm/sys_regs.h

17

sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \

arch/arm64/kvm/sys_regs.h

199

if (i1->Op1 != i2->Op1)

arch/arm64/kvm/sys_regs.h

200

return i1->Op1 - i2->Op1;

arch/arm64/kvm/sys_regs.h

22

u8 Op1;

arch/arm64/kvm/sys_regs.h

242

#define Op1(_x) .Op1 = _x

arch/arm64/kvm/sys_regs.h

249

Op0(sys_reg_Op0(reg)), Op1(sys_reg_Op1(reg)), \

arch/arm64/kvm/sys_regs.h

256

Op0(0), Op1(sys_reg_Op1(reg)), \

arch/arm64/kvm/sys_regs.h

32

.Op1 = sys_reg_Op1(reg), \

arch/arm64/kvm/sys_regs.h

39

.Op1 = ((esr) >> 14) & 0x7, \

arch/arm64/kvm/sys_regs.h

46

((struct sys_reg_params){ .Op1 = ((esr) >> 14) & 0x7, \

arch/arm64/kvm/sys_regs.h

58

return (p->Op0 == 3 && !(p->Op1 & 0b100) && p->Op1 != 2 &&

arch/arm64/kvm/sys_regs.h

74

u8 Op1;

arch/arm64/kvm/trace_handle_exit.h

106

__entry->Op1 = reg->Op1;

arch/arm64/kvm/trace_handle_exit.h

114

__entry->Op0, __entry->Op1, __entry->CRn,

arch/arm64/kvm/trace_handle_exit.h

94

__field(u8, Op1)