lib/librumpuser/rumpfiber.c

459

clockid_t clk;

lib/librumpuser/rumpfiber.c

464

clk = CLOCK_REALTIME;

lib/librumpuser/rumpfiber.c

467

clk = CLOCK_MONOTONIC;

lib/librumpuser/rumpfiber.c

473

if (clock_gettime(clk, &ts) == -1) {

lib/librumpuser/rumpuser.c

102

if (clock_gettime(clk, &ts) == -1) {

lib/librumpuser/rumpuser.c

84

clockid_t clk;

lib/librumpuser/rumpuser.c

89

clk = CLOCK_REALTIME;

lib/librumpuser/rumpuser.c

93

clk = CLOCK_MONOTONIC;

lib/librumpuser/rumpuser.c

95

clk = CLOCK_REALTIME;

lib/librumpuser/rumpuser_port.h

132

clock_gettime(clockid_t clk, struct timespec *ts)

sbin/routed/defs.h

470

extern struct timeval clk; /* system clock's idea of time */

sbin/routed/input.c

961

|| (u_long)ap->start > (u_long)clk.tv_sec+DAY

sbin/routed/input.c

962

|| (u_long)ap->end+DAY < (u_long)clk.tv_sec)

sbin/routed/main.c

125

gettimeofday(&clk, 0);

sbin/routed/main.c

126

prev_clk = clk;

sbin/routed/main.c

127

epoch = clk;

sbin/routed/main.c

353

prev_clk = clk;

sbin/routed/main.c

354

gettimeofday(&clk, 0);

sbin/routed/main.c

355

if (prev_clk.tv_sec == clk.tv_sec

sbin/routed/main.c

356

&& prev_clk.tv_usec == clk.tv_usec+usec_fudge) {

sbin/routed/main.c

363

clk.tv_usec += ++usec_fudge;

sbin/routed/main.c

368

timevalsub(&t2, &clk, &prev_clk);

sbin/routed/main.c

381

timevalsub(&now, &clk, &epoch);

sbin/routed/main.c

75

struct timeval clk, prev_clk;

sbin/routed/output.c

246

if ((u_long)ap->start > (u_long)clk.tv_sec)

sbin/routed/output.c

249

if ((u_long)ap->end < (u_long)clk.tv_sec) {

sbin/routed/output.c

291

na->au.a_md5.md5_seqno = htonl(clk.tv_sec);

sys/arch/acorn32/podulebus/sbicreg.h

132

#define SBIC_TIMEOUT(val,clk) ((((val) * (clk)) / 800) + 1)

sys/arch/amiga/dev/clock.c

512

register struct clkreg *clk = (struct clkreg *)clkstd[0];

sys/arch/amiga/dev/clock.c

514

clk->clk_msb2 = -1; clk->clk_lsb2 = -1;

sys/arch/amiga/dev/clock.c

515

clk->clk_msb3 = -1; clk->clk_lsb3 = -1;

sys/arch/amiga/dev/clock.c

517

clk->clk_cr2 = CLK_CR3;

sys/arch/amiga/dev/clock.c

518

clk->clk_cr3 = CLK_OENAB|CLK_8BIT;

sys/arch/amiga/dev/clock.c

519

clk->clk_cr2 = CLK_CR1;

sys/arch/amiga/dev/clock.c

520

clk->clk_cr1 = CLK_IENAB;

sys/arch/amiga/dev/clock.c

526

register struct clkreg *clk = (struct clkreg *)clkstd[0];

sys/arch/amiga/dev/clock.c

528

clk->clk_cr2 = CLK_CR3;

sys/arch/amiga/dev/clock.c

529

clk->clk_cr3 = 0;

sys/arch/amiga/dev/clock.c

530

clk->clk_cr2 = CLK_CR1;

sys/arch/amiga/dev/clock.c

531

clk->clk_cr1 = CLK_IENAB;

sys/arch/amiga/dev/sbicreg.h

132

#define SBIC_TIMEOUT(val,clk) ((((val) * (clk)) / 800) + 1)

sys/arch/arm/altera/cycv_clkmgr.c

227

struct cycv_clk *clk = &sc->sc_clocks[clkno];

sys/arch/arm/altera/cycv_clkmgr.c

232

clk->base.domain = &sc->sc_clkdom;

sys/arch/arm/altera/cycv_clkmgr.c

233

clk->base.name = fdtbus_get_string(handle, "name");

sys/arch/arm/altera/cycv_clkmgr.c

234

clk->base.flags = 0;

sys/arch/arm/altera/cycv_clkmgr.c

236

clk->id = handle;

sys/arch/arm/altera/cycv_clkmgr.c

237

clk->parent = NULL;

sys/arch/arm/altera/cycv_clkmgr.c

238

clk->parent_id = 0;

sys/arch/arm/altera/cycv_clkmgr.c

239

clk->refcnt = 0;

sys/arch/arm/altera/cycv_clkmgr.c

245

clk->type = dce->value;

sys/arch/arm/altera/cycv_clkmgr.c

247

if (clk->type == CYCV_CLK_TYPE_FIXED) {

sys/arch/arm/altera/cycv_clkmgr.c

249

&clk->u.fixed_freq) == 0) {

sys/arch/arm/altera/cycv_clkmgr.c

252

} else if (clk->type == CYCV_CLK_TYPE_PLL) {

sys/arch/arm/altera/cycv_clkmgr.c

253

if (fdtbus_get_reg(handle, 0, &clk->u.pll_addr, NULL) != 0)

sys/arch/arm/altera/cycv_clkmgr.c

256

} else if (clk->type == CYCV_CLK_TYPE_PERIP) {

sys/arch/arm/altera/cycv_clkmgr.c

258

&clk->u.fixed_div) == 0) {

sys/arch/arm/altera/cycv_clkmgr.c

259

clk->type = CYCV_CLK_TYPE_FIXED_DIV;

sys/arch/arm/altera/cycv_clkmgr.c

260

} else if (fdtbus_get_reg(handle, 0, &clk->u.div.addr, NULL) ==

sys/arch/arm/altera/cycv_clkmgr.c

262

clk->type = CYCV_CLK_TYPE_DIV;

sys/arch/arm/altera/cycv_clkmgr.c

263

clk->u.div.shift = 0;

sys/arch/arm/altera/cycv_clkmgr.c

264

clk->u.div.mask = 0xff;

sys/arch/arm/altera/cycv_clkmgr.c

270

clk->type = CYCV_CLK_TYPE_DIV;

sys/arch/arm/altera/cycv_clkmgr.c

271

clk->u.div.addr = of_decode_int(buf);

sys/arch/arm/altera/cycv_clkmgr.c

272

clk->u.div.shift = of_decode_int(buf + 4);

sys/arch/arm/altera/cycv_clkmgr.c

273

clk->u.div.mask = ((1 << of_decode_int(buf + 8)) - 1) <<

sys/arch/arm/altera/cycv_clkmgr.c

274

clk->u.div.shift;

sys/arch/arm/altera/cycv_clkmgr.c

277

clk->type = CYCV_CLK_TYPE_FIXED_DIV;

sys/arch/arm/altera/cycv_clkmgr.c

278

clk->u.fixed_div = 1;

sys/arch/arm/altera/cycv_clkmgr.c

285

clk->gate_addr = of_decode_int(buf);

sys/arch/arm/altera/cycv_clkmgr.c

286

clk->gate_shift = of_decode_int(buf + 4);

sys/arch/arm/altera/cycv_clkmgr.c

29

static struct clk *cycv_clkmgr_clock_decode(device_t, int, const void *,

sys/arch/arm/altera/cycv_clkmgr.c

292

clk->parent_id =

sys/arch/arm/altera/cycv_clkmgr.c

296

clk->flags = flags;

sys/arch/arm/altera/cycv_clkmgr.c

304

clk->base.name, handle);

sys/arch/arm/altera/cycv_clkmgr.c

36

static struct clk *cycv_clkmgr_clock_get(void *, const char *);

sys/arch/arm/altera/cycv_clkmgr.c

369

cycv_clkmgr_clock_print(struct cycv_clkmgr_softc *sc, struct cycv_clk *clk)

sys/arch/arm/altera/cycv_clkmgr.c

37

static void cycv_clkmgr_clock_put(void *, struct clk *);

sys/arch/arm/altera/cycv_clkmgr.c

375

aprint_debug("clock %s, id %d, frequency %uHz:\n", clk->base.name,

sys/arch/arm/altera/cycv_clkmgr.c

376

clk->id, cycv_clkmgr_clock_get_rate(sc, &clk->base));

sys/arch/arm/altera/cycv_clkmgr.c

377

if (clk->parent != NULL)

sys/arch/arm/altera/cycv_clkmgr.c

378

aprint_debug("parent: %s", clk->parent->base.name);

sys/arch/arm/altera/cycv_clkmgr.c

38

static u_int cycv_clkmgr_clock_get_rate(void *, struct clk *);

sys/arch/arm/altera/cycv_clkmgr.c

380

aprint_debug("parent_id: %d", clk->parent_id);

sys/arch/arm/altera/cycv_clkmgr.c

381

aprint_debug(", flags: %d\n", clk->flags);

sys/arch/arm/altera/cycv_clkmgr.c

382

switch (clk->type) {

sys/arch/arm/altera/cycv_clkmgr.c

384

tmp = bus_space_read_4(sc->sc_bst, sc->sc_bsh, clk->u.pll_addr);

sys/arch/arm/altera/cycv_clkmgr.c

39

static int cycv_clkmgr_clock_set_rate(void *, struct clk *, u_int);

sys/arch/arm/altera/cycv_clkmgr.c

390

aprint_debug(" Fixed frequency = %u\n", clk->u.fixed_freq);

sys/arch/arm/altera/cycv_clkmgr.c

393

aprint_debug(" Fixed divisor = %u\n", clk->u.fixed_div);

sys/arch/arm/altera/cycv_clkmgr.c

396

tmp = bus_space_read_4(sc->sc_bst, sc->sc_bsh, clk->u.div.addr);

sys/arch/arm/altera/cycv_clkmgr.c

397

tmp = (tmp & clk->u.div.mask) >> clk->u.div.shift;

sys/arch/arm/altera/cycv_clkmgr.c

398

if (__SHIFTOUT_MASK(clk->u.div.mask) > 0xf)

sys/arch/arm/altera/cycv_clkmgr.c

40

static int cycv_clkmgr_clock_enable(void *, struct clk *);

sys/arch/arm/altera/cycv_clkmgr.c

409

if (clk->flags & CYCV_CLK_FLAG_HAVE_GATE) {

sys/arch/arm/altera/cycv_clkmgr.c

41

static int cycv_clkmgr_clock_disable(void *, struct clk *);

sys/arch/arm/altera/cycv_clkmgr.c

410

tmp = bus_space_read_4(sc->sc_bst, sc->sc_bsh, clk->gate_addr);

sys/arch/arm/altera/cycv_clkmgr.c

411

tmp &= (1 << clk->gate_shift);

sys/arch/arm/altera/cycv_clkmgr.c

418

static struct clk *

sys/arch/arm/altera/cycv_clkmgr.c

42

static int cycv_clkmgr_clock_set_parent(void *, struct clk *, struct clk *);

sys/arch/arm/altera/cycv_clkmgr.c

423

struct cycv_clk *clk;

sys/arch/arm/altera/cycv_clkmgr.c

43

static struct clk *cycv_clkmgr_clock_get_parent(void *, struct clk *);

sys/arch/arm/altera/cycv_clkmgr.c

430

clk = cycv_clkmgr_clock_lookup_by_id(sc, cc_phandle);

sys/arch/arm/altera/cycv_clkmgr.c

432

return clk == NULL? NULL : &clk->base;

sys/arch/arm/altera/cycv_clkmgr.c

435

static struct clk *

sys/arch/arm/altera/cycv_clkmgr.c

446

cycv_clkmgr_clock_put(void *priv, struct clk *clk)

sys/arch/arm/altera/cycv_clkmgr.c

452

cycv_clkmgr_clock_get_rate(void *priv, struct clk *base_clk)

sys/arch/arm/altera/cycv_clkmgr.c

455

struct cycv_clk *clk = (struct cycv_clk *) base_clk;

sys/arch/arm/altera/cycv_clkmgr.c

462

if (clk->type == CYCV_CLK_TYPE_FIXED)

sys/arch/arm/altera/cycv_clkmgr.c

463

return clk->u.fixed_freq;

sys/arch/arm/altera/cycv_clkmgr.c

469

clk->base.name);

sys/arch/arm/altera/cycv_clkmgr.c

474

if (strncmp(clk->base.name, "mpuclk@", strlen("mpuclk@")) == 0)

sys/arch/arm/altera/cycv_clkmgr.c

476

else if (strncmp(clk->base.name, "mainclk@", strlen("mainclk@")) == 0)

sys/arch/arm/altera/cycv_clkmgr.c

478

else if (strncmp(clk->base.name, "dbgatclk@", strlen("dbgatclk@")) == 0)

sys/arch/arm/altera/cycv_clkmgr.c

481

switch (clk->type) {

sys/arch/arm/altera/cycv_clkmgr.c

483

return parent_rate / clk->u.fixed_div;

sys/arch/arm/altera/cycv_clkmgr.c

487

clk->u.div.addr);

sys/arch/arm/altera/cycv_clkmgr.c

488

divisor = (divisor & clk->u.div.mask) >> clk->u.div.shift;

sys/arch/arm/altera/cycv_clkmgr.c

489

if (__SHIFTOUT_MASK(clk->u.div.mask) > 0xf)

sys/arch/arm/altera/cycv_clkmgr.c

497

tmp = bus_space_read_4(sc->sc_bst, sc->sc_bsh, clk->u.pll_addr);

sys/arch/arm/altera/cycv_clkmgr.c

504

aprint_debug_dev(sc->sc_dev, "unknown clock type %d\n", clk->type);

sys/arch/arm/altera/cycv_clkmgr.c

510

cycv_clkmgr_clock_set_rate(void *priv, struct clk *clk, u_int rate)

sys/arch/arm/altera/cycv_clkmgr.c

517

cycv_clkmgr_clock_set(void *priv, struct clk *base_clk, int val)

sys/arch/arm/altera/cycv_clkmgr.c

520

struct cycv_clk *clk = (struct cycv_clk *) base_clk;

sys/arch/arm/altera/cycv_clkmgr.c

522

if (clk->flags & CYCV_CLK_FLAG_HAVE_GATE) {

sys/arch/arm/altera/cycv_clkmgr.c

524

clk->gate_addr);

sys/arch/arm/altera/cycv_clkmgr.c

525

tmp &= ~(1 << clk->gate_shift);

sys/arch/arm/altera/cycv_clkmgr.c

526

tmp |= val << clk->gate_shift;

sys/arch/arm/altera/cycv_clkmgr.c

527

bus_space_write_4(sc->sc_bst, sc->sc_bsh, clk->gate_addr, tmp);

sys/arch/arm/altera/cycv_clkmgr.c

536

cycv_clkmgr_clock_enable(void *priv, struct clk *clk)

sys/arch/arm/altera/cycv_clkmgr.c

538

return cycv_clkmgr_clock_set(priv, clk, 1);

sys/arch/arm/altera/cycv_clkmgr.c

542

cycv_clkmgr_clock_disable(void *priv, struct clk *clk)

sys/arch/arm/altera/cycv_clkmgr.c

544

return cycv_clkmgr_clock_set(priv, clk, 0);

sys/arch/arm/altera/cycv_clkmgr.c

548

cycv_clkmgr_clock_set_parent(void *priv, struct clk *clk,

sys/arch/arm/altera/cycv_clkmgr.c

549

struct clk *clk_parent)

sys/arch/arm/altera/cycv_clkmgr.c

560

static struct clk *

sys/arch/arm/altera/cycv_clkmgr.c

561

cycv_clkmgr_clock_get_parent(void *priv, struct clk *base_clk)

sys/arch/arm/altera/cycv_clkmgr.c

564

struct cycv_clk *clk = (struct cycv_clk *) base_clk;

sys/arch/arm/altera/cycv_clkmgr.c

566

struct cycv_clk *parent = clk->parent;

sys/arch/arm/altera/cycv_clkmgr.c

57

struct clk base;

sys/arch/arm/altera/cycv_clkmgr.c

573

if (clk->parent_id != 0) {

sys/arch/arm/altera/cycv_clkmgr.c

574

parent = cycv_clkmgr_clock_lookup_by_id(sc, clk->parent_id);

sys/arch/arm/altera/cycv_clkmgr.c

578

mux = cycv_clkmgr_get_mux_info(clk->base.name);

sys/arch/arm/altera/cycv_clkmgr.c

593

clk->base.name, parent_index);

sys/arch/arm/altera/cycv_clkmgr.c

601

clk->parent = parent;

sys/arch/arm/altera/cycv_dwcmmc.c

59

struct clk *sc_clk_biu;

sys/arch/arm/altera/cycv_dwcmmc.c

60

struct clk *sc_clk_ciu;

sys/arch/arm/altera/cycv_gmac.c

80

struct clk *clk_gmac;

sys/arch/arm/amlogic/meson6_timer.c

135

struct clk *clk;

sys/arch/arm/amlogic/meson6_timer.c

136

for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++) {

sys/arch/arm/amlogic/meson6_timer.c

137

if (clk_enable(clk) != 0) {

sys/arch/arm/amlogic/meson8b_clkc.c

100

struct meson_clk_clk *clk, u_int rate)

sys/arch/arm/amlogic/meson8b_clkc.c

102

struct clk *clkp, *clkp_parent;

sys/arch/arm/amlogic/meson8b_clkc.c

105

KASSERT(clk->type == MESON_CLK_PLL);

sys/arch/arm/amlogic/meson8b_clkc.c

107

clkp = &clk->base;

sys/arch/arm/amlogic/meson_clk.c

105

static struct clk *

sys/arch/arm/amlogic/meson_clk.c

110

struct meson_clk_clk *clk;

sys/arch/arm/amlogic/meson_clk.c

119

clk = &sc->sc_clks[clock_id];

sys/arch/arm/amlogic/meson_clk.c

120

if (clk->type == MESON_CLK_UNKNOWN)

sys/arch/arm/amlogic/meson_clk.c

123

return &clk->base;

sys/arch/arm/amlogic/meson_clk.c

130

static struct clk *

sys/arch/arm/amlogic/meson_clk.c

134

struct meson_clk_clk *clk;

sys/arch/arm/amlogic/meson_clk.c

136

clk = meson_clk_clock_find(sc, name);

sys/arch/arm/amlogic/meson_clk.c

137

if (clk == NULL)

sys/arch/arm/amlogic/meson_clk.c

140

return &clk->base;

sys/arch/arm/amlogic/meson_clk.c

144

meson_clk_clock_put(void *priv, struct clk *clk)

sys/arch/arm/amlogic/meson_clk.c

149

meson_clk_clock_get_rate(void *priv, struct clk *clkp)

sys/arch/arm/amlogic/meson_clk.c

152

struct meson_clk_clk *clk = (struct meson_clk_clk *)clkp;

sys/arch/arm/amlogic/meson_clk.c

153

struct clk *clkp_parent;

sys/arch/arm/amlogic/meson_clk.c

155

if (clk->get_rate)

sys/arch/arm/amlogic/meson_clk.c

156

return clk->get_rate(sc, clk);

sys/arch/arm/amlogic/meson_clk.c

160

aprint_debug("%s: no parent for %s\n", __func__, clk->base.name);

sys/arch/arm/amlogic/meson_clk.c

168

meson_clk_clock_set_rate(void *priv, struct clk *clkp, u_int rate)

sys/arch/arm/amlogic/meson_clk.c

171

struct meson_clk_clk *clk = (struct meson_clk_clk *)clkp;

sys/arch/arm/amlogic/meson_clk.c

172

struct clk *clkp_parent;

sys/arch/arm/amlogic/meson_clk.c

177

aprint_debug("%s: no parent for %s\n", __func__, clk->base.name);

sys/arch/arm/amlogic/meson_clk.c

183

if (clk->set_rate)

sys/arch/arm/amlogic/meson_clk.c

184

return clk->set_rate(sc, clk, rate);

sys/arch/arm/amlogic/meson_clk.c

190

meson_clk_clock_round_rate(void *priv, struct clk *clkp, u_int rate)

sys/arch/arm/amlogic/meson_clk.c

193

struct meson_clk_clk *clk = (struct meson_clk_clk *)clkp;

sys/arch/arm/amlogic/meson_clk.c

194

struct clk *clkp_parent;

sys/arch/arm/amlogic/meson_clk.c

199

aprint_debug("%s: no parent for %s\n", __func__, clk->base.name);

sys/arch/arm/amlogic/meson_clk.c

205

if (clk->round_rate)

sys/arch/arm/amlogic/meson_clk.c

206

return clk->round_rate(sc, clk, rate);

sys/arch/arm/amlogic/meson_clk.c

212

meson_clk_clock_enable(void *priv, struct clk *clkp)

sys/arch/arm/amlogic/meson_clk.c

215

struct meson_clk_clk *clk = (struct meson_clk_clk *)clkp;

sys/arch/arm/amlogic/meson_clk.c

216

struct clk *clkp_parent;

sys/arch/arm/amlogic/meson_clk.c

226

if (clk->enable)

sys/arch/arm/amlogic/meson_clk.c

227

error = clk->enable(sc, clk, 1);

sys/arch/arm/amlogic/meson_clk.c

233

meson_clk_clock_disable(void *priv, struct clk *clkp)

sys/arch/arm/amlogic/meson_clk.c

236

struct meson_clk_clk *clk = (struct meson_clk_clk *)clkp;

sys/arch/arm/amlogic/meson_clk.c

239

if (clk->enable)

sys/arch/arm/amlogic/meson_clk.c

240

error = clk->enable(sc, clk, 0);

sys/arch/arm/amlogic/meson_clk.c

246

meson_clk_clock_set_parent(void *priv, struct clk *clkp,

sys/arch/arm/amlogic/meson_clk.c

247

struct clk *clkp_parent)

sys/arch/arm/amlogic/meson_clk.c

250

struct meson_clk_clk *clk = (struct meson_clk_clk *)clkp;

sys/arch/arm/amlogic/meson_clk.c

252

if (clk->set_parent == NULL)

sys/arch/arm/amlogic/meson_clk.c

255

return clk->set_parent(sc, clk, clkp_parent->name);

sys/arch/arm/amlogic/meson_clk.c

258

static struct clk *

sys/arch/arm/amlogic/meson_clk.c

259

meson_clk_clock_get_parent(void *priv, struct clk *clkp)

sys/arch/arm/amlogic/meson_clk.c

262

struct meson_clk_clk *clk = (struct meson_clk_clk *)clkp;

sys/arch/arm/amlogic/meson_clk.c

266

if (clk->get_parent == NULL)

sys/arch/arm/amlogic/meson_clk.c

269

parent = clk->get_parent(sc, clk);

sys/arch/arm/amlogic/meson_clk.c

331

struct meson_clk_clk *clk;

sys/arch/arm/amlogic/meson_clk.c

332

struct clk *clkp_parent;

sys/arch/arm/amlogic/meson_clk.c

337

clk = &sc->sc_clks[i];

sys/arch/arm/amlogic/meson_clk.c

338

if (clk->type == MESON_CLK_UNKNOWN)

sys/arch/arm/amlogic/meson_clk.c

341

clkp_parent = clk_get_parent(&clk->base);

sys/arch/arm/amlogic/meson_clk.c

343

switch (clk->type) {

sys/arch/arm/amlogic/meson_clk.c

357

clk->base.name,

sys/arch/arm/amlogic/meson_clk.c

361

aprint_debug("%10u Hz\n", clk_get_rate(&clk->base));

sys/arch/arm/amlogic/meson_clk.h

333

struct clk base;

sys/arch/arm/amlogic/meson_clk_div.c

141

struct meson_clk_clk *clk)

sys/arch/arm/amlogic/meson_clk_div.c

143

struct meson_clk_div *div = &clk->u.div;

sys/arch/arm/amlogic/meson_clk_div.c

145

KASSERT(clk->type == MESON_CLK_DIV);

sys/arch/arm/amlogic/meson_clk_div.c

41

struct meson_clk_clk *clk)

sys/arch/arm/amlogic/meson_clk_div.c

43

struct meson_clk_div *div = &clk->u.div;

sys/arch/arm/amlogic/meson_clk_div.c

44

struct clk *clkp, *clkp_parent;

sys/arch/arm/amlogic/meson_clk_div.c

48

KASSERT(clk->type == MESON_CLK_DIV);

sys/arch/arm/amlogic/meson_clk_div.c

50

clkp = &clk->base;

sys/arch/arm/amlogic/meson_clk_div.c

81

struct meson_clk_clk *clk, u_int new_rate)

sys/arch/arm/amlogic/meson_clk_div.c

83

struct meson_clk_div *div = &clk->u.div;

sys/arch/arm/amlogic/meson_clk_div.c

84

struct clk *clkp, *clkp_parent;

sys/arch/arm/amlogic/meson_clk_div.c

89

KASSERT(clk->type == MESON_CLK_DIV);

sys/arch/arm/amlogic/meson_clk_div.c

91

clkp = &clk->base;

sys/arch/arm/amlogic/meson_clk_fixed.c

40

meson_clk_fixed_get_rate(struct meson_clk_softc *sc, struct meson_clk_clk *clk)

sys/arch/arm/amlogic/meson_clk_fixed.c

42

struct meson_clk_fixed *fixed = &clk->u.fixed;

sys/arch/arm/amlogic/meson_clk_fixed.c

44

KASSERT(clk->type == MESON_CLK_FIXED);

sys/arch/arm/amlogic/meson_clk_fixed_factor.c

100

KASSERT(clk->type == MESON_CLK_FIXED_FACTOR);

sys/arch/arm/amlogic/meson_clk_fixed_factor.c

40

meson_clk_fixed_factor_get_parent_rate(struct clk *clkp)

sys/arch/arm/amlogic/meson_clk_fixed_factor.c

42

struct clk *clkp_parent;

sys/arch/arm/amlogic/meson_clk_fixed_factor.c

53

struct meson_clk_clk *clk)

sys/arch/arm/amlogic/meson_clk_fixed_factor.c

55

struct meson_clk_fixed_factor *fixed_factor = &clk->u.fixed_factor;

sys/arch/arm/amlogic/meson_clk_fixed_factor.c

56

struct clk *clkp = &clk->base;

sys/arch/arm/amlogic/meson_clk_fixed_factor.c

58

KASSERT(clk->type == MESON_CLK_FIXED_FACTOR);

sys/arch/arm/amlogic/meson_clk_fixed_factor.c

68

meson_clk_fixed_factor_set_parent_rate(struct clk *clkp, u_int rate)

sys/arch/arm/amlogic/meson_clk_fixed_factor.c

70

struct clk *clkp_parent;

sys/arch/arm/amlogic/meson_clk_fixed_factor.c

81

struct meson_clk_clk *clk, u_int rate)

sys/arch/arm/amlogic/meson_clk_fixed_factor.c

83

struct meson_clk_fixed_factor *fixed_factor = &clk->u.fixed_factor;

sys/arch/arm/amlogic/meson_clk_fixed_factor.c

84

struct clk *clkp = &clk->base;

sys/arch/arm/amlogic/meson_clk_fixed_factor.c

86

KASSERT(clk->type == MESON_CLK_FIXED_FACTOR);

sys/arch/arm/amlogic/meson_clk_fixed_factor.c

96

struct meson_clk_clk *clk)

sys/arch/arm/amlogic/meson_clk_fixed_factor.c

98

struct meson_clk_fixed_factor *fixed_factor = &clk->u.fixed_factor;

sys/arch/arm/amlogic/meson_clk_gate.c

40

meson_clk_gate_enable(struct meson_clk_softc *sc, struct meson_clk_clk *clk,

sys/arch/arm/amlogic/meson_clk_gate.c

43

struct meson_clk_gate *gate = &clk->u.gate;

sys/arch/arm/amlogic/meson_clk_gate.c

47

KASSERT(clk->type == MESON_CLK_GATE);

sys/arch/arm/amlogic/meson_clk_gate.c

66

meson_clk_gate_get_parent(struct meson_clk_softc *sc, struct meson_clk_clk *clk)

sys/arch/arm/amlogic/meson_clk_gate.c

68

struct meson_clk_gate *gate = &clk->u.gate;

sys/arch/arm/amlogic/meson_clk_gate.c

70

KASSERT(clk->type == MESON_CLK_GATE);

sys/arch/arm/amlogic/meson_clk_mpll.c

43

struct meson_clk_clk *clk)

sys/arch/arm/amlogic/meson_clk_mpll.c

45

struct meson_clk_mpll *mpll = &clk->u.mpll;

sys/arch/arm/amlogic/meson_clk_mpll.c

46

struct clk *clkp, *clkp_parent;

sys/arch/arm/amlogic/meson_clk_mpll.c

50

KASSERT(clk->type == MESON_CLK_MPLL);

sys/arch/arm/amlogic/meson_clk_mpll.c

52

clkp = &clk->base;

sys/arch/arm/amlogic/meson_clk_mpll.c

80

struct meson_clk_clk *clk)

sys/arch/arm/amlogic/meson_clk_mpll.c

82

struct meson_clk_mpll *mpll = &clk->u.mpll;

sys/arch/arm/amlogic/meson_clk_mpll.c

84

KASSERT(clk->type == MESON_CLK_MPLL);

sys/arch/arm/amlogic/meson_clk_mux.c

40

meson_clk_mux_get_parent(struct meson_clk_softc *sc, struct meson_clk_clk *clk)

sys/arch/arm/amlogic/meson_clk_mux.c

42

struct meson_clk_mux *mux = &clk->u.mux;

sys/arch/arm/amlogic/meson_clk_mux.c

46

KASSERT(clk->type == MESON_CLK_MUX);

sys/arch/arm/amlogic/meson_clk_pll.c

102

struct meson_clk_pll *pll = &clk->u.pll;

sys/arch/arm/amlogic/meson_clk_pll.c

103

struct clk *clkp, *clkp_parent;

sys/arch/arm/amlogic/meson_clk_pll.c

108

KASSERT(clk->type == MESON_CLK_PLL);

sys/arch/arm/amlogic/meson_clk_pll.c

110

clkp = &clk->base;

sys/arch/arm/amlogic/meson_clk_pll.c

175

struct meson_clk_clk *clk)

sys/arch/arm/amlogic/meson_clk_pll.c

177

struct meson_clk_pll *pll = &clk->u.pll;

sys/arch/arm/amlogic/meson_clk_pll.c

179

KASSERT(clk->type == MESON_CLK_PLL);

sys/arch/arm/amlogic/meson_clk_pll.c

41

struct meson_clk_clk *clk)

sys/arch/arm/amlogic/meson_clk_pll.c

43

struct meson_clk_pll *pll = &clk->u.pll;

sys/arch/arm/amlogic/meson_clk_pll.c

44

struct clk *clkp, *clkp_parent;

sys/arch/arm/amlogic/meson_clk_pll.c

49

KASSERT(clk->type == MESON_CLK_PLL);

sys/arch/arm/amlogic/meson_clk_pll.c

51

clkp = &clk->base;

sys/arch/arm/amlogic/meson_clk_pll.c

99

meson_clk_pll_set_rate(struct meson_clk_softc *sc, struct meson_clk_clk *clk,

sys/arch/arm/amlogic/meson_dwmac.c

137

bus_space_handle_t bsh, struct clk *clkin)

sys/arch/arm/amlogic/meson_dwmac.c

199

struct clk *clk_gmac, *clk_in[2];

sys/arch/arm/amlogic/meson_i2c.c

106

struct clk *sc_clk;

sys/arch/arm/amlogic/meson_pwm.c

340

struct clk *clk;

sys/arch/arm/amlogic/meson_pwm.c

347

clk = fdtbus_clock_get_index(phandle, 0);

sys/arch/arm/amlogic/meson_pwm.c

348

if (clk == NULL) {

sys/arch/arm/amlogic/meson_pwm.c

352

sc->sc_clkfreq = clk_get_rate(clk);

sys/arch/arm/amlogic/meson_pwm.c

354

if (clk == fdtbus_clock_byname("vid_pll"))

sys/arch/arm/amlogic/meson_pwm.c

356

else if (clk == fdtbus_clock_byname("fclk_div4"))

sys/arch/arm/amlogic/meson_pwm.c

358

else if (clk == fdtbus_clock_byname("fclk_div3"))

sys/arch/arm/amlogic/meson_rng.c

77

struct clk *clk;

sys/arch/arm/amlogic/meson_rng.c

94

clk = fdtbus_clock_get(phandle, "core");

sys/arch/arm/amlogic/meson_rng.c

95

if (clk != NULL && clk_enable(clk) != 0) {

sys/arch/arm/amlogic/meson_sdhc.c

179

struct clk *clk_clkin, *clk_core;

sys/arch/arm/amlogic/meson_sdio.c

158

struct clk *clk_clkin, *clk_core;

sys/arch/arm/amlogic/meson_usbphy.c

200

struct clk *clk;

sys/arch/arm/amlogic/meson_usbphy.c

220

for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)

sys/arch/arm/amlogic/meson_usbphy.c

221

if (clk_enable(clk) != 0) {

sys/arch/arm/amlogic/mesong12_clkc.c

1254

mesong12_cpuclk_get_rate(struct meson_clk_softc *sc, struct meson_clk_clk *clk)

sys/arch/arm/amlogic/mesong12_clkc.c

1261

KASSERT(clk->type == MESON_CLK_MUX);

sys/arch/arm/amlogic/mesong12_clkc.c

1265

switch (clk->u.mux.reg) {

sys/arch/arm/amlogic/mesong12_clkc.c

1278

if ((CLK_READ(sc, clk->u.mux.reg) & __BIT(11)) == 0) {

sys/arch/arm/amlogic/mesong12_clkc.c

1282

struct clk *clkp;

sys/arch/arm/amlogic/mesong12_clkc.c

1284

switch (clk->u.mux.reg) {

sys/arch/arm/amlogic/mesong12_clkc.c

1286

clkp = (struct clk *)meson_clk_clock_find(sc,

sys/arch/arm/amlogic/mesong12_clkc.c

1291

clkp = (struct clk *)meson_clk_clock_find(sc,

sys/arch/arm/amlogic/mesong12_clkc.c

1313

mesong12_cpuclk_set_rate(struct meson_clk_softc *sc, struct meson_clk_clk *clk,

sys/arch/arm/amlogic/mesong12_clkc.c

1321

KASSERT(clk->type == MESON_CLK_MUX);

sys/arch/arm/amlogic/mesong12_clkc.c

1325

switch (clk->u.mux.reg) {

sys/arch/arm/amlogic/mesong12_clkc.c

1351

val = CLK_READ(sc, clk->u.mux.reg);

sys/arch/arm/amlogic/mesong12_clkc.c

1352

CLK_WRITE(sc, clk->u.mux.reg, val & ~__BIT(11));

sys/arch/arm/amlogic/mesong12_clkc.c

1400

val = CLK_READ(sc, clk->u.mux.reg);

sys/arch/arm/amlogic/mesong12_clkc.c

1401

CLK_WRITE(sc, clk->u.mux.reg, val | __BIT(11));

sys/arch/arm/amlogic/mesong12_clkc.c

1411

struct meson_clk_clk *clk, u_int new_rate)

sys/arch/arm/amlogic/mesong12_clkc.c

1413

struct meson_clk_pll *pll = &clk->u.pll;

sys/arch/arm/amlogic/mesong12_clkc.c

1415

KASSERT(clk->type == MESON_CLK_PLL);

sys/arch/arm/amlogic/mesong12_clkc.c

1477

return meson_clk_pll_set_rate(sc, clk, new_rate);

sys/arch/arm/amlogic/mesong12_usb2phy.c

162

struct clk *sc_clk;

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

82

struct clk *sc_clk;

sys/arch/arm/amlogic/mesongx_mmc.c

237

struct clk *sc_clk_core;

sys/arch/arm/amlogic/mesongx_mmc.c

238

struct clk *sc_clk_clkin[2];

sys/arch/arm/amlogic/mesongx_wdt.c

133

struct clk *clk;

sys/arch/arm/amlogic/mesongx_wdt.c

152

clk = fdtbus_clock_get_index(phandle, 0);

sys/arch/arm/amlogic/mesongx_wdt.c

153

if (clk != NULL)

sys/arch/arm/amlogic/mesongx_wdt.c

154

sc->sc_rate = clk_get_rate(clk);

sys/arch/arm/amlogic/mesongxl_usb2phy.c

61

struct clk *sc_clk;

sys/arch/arm/amlogic/mesongxl_usb3phy.c

69

struct clk *sc_clk_phy;

sys/arch/arm/amlogic/mesongxl_usb3phy.c

70

struct clk *sc_clk_peripheral;

sys/arch/arm/apple/apple_iic.c

92

struct clk * sc_clk;

sys/arch/arm/broadcom/bcm2835_aux.c

160

static struct clk *

sys/arch/arm/broadcom/bcm2835_aux.c

176

static struct clk *

sys/arch/arm/broadcom/bcm2835_aux.c

190

bcmaux_put(void *priv, struct clk *clk)

sys/arch/arm/broadcom/bcm2835_aux.c

195

bcmaux_get_rate(void *priv, struct clk *clk)

sys/arch/arm/broadcom/bcm2835_aux.c

203

bcmaux_enable(void *priv, struct clk *clk)

sys/arch/arm/broadcom/bcm2835_aux.c

206

struct bcmaux_clk *auxclk = (struct bcmaux_clk *)clk;

sys/arch/arm/broadcom/bcm2835_aux.c

217

bcmaux_disable(void *priv, struct clk *clk)

sys/arch/arm/broadcom/bcm2835_aux.c

220

struct bcmaux_clk *auxclk = (struct bcmaux_clk *)clk;

sys/arch/arm/broadcom/bcm2835_aux.c

55

static struct clk *bcmaux_decode(device_t, int, const void *, size_t);

sys/arch/arm/broadcom/bcm2835_aux.c

61

static struct clk *bcmaux_get(void *, const char *);

sys/arch/arm/broadcom/bcm2835_aux.c

62

static void bcmaux_put(void *, struct clk *);

sys/arch/arm/broadcom/bcm2835_aux.c

63

static u_int bcmaux_get_rate(void *, struct clk *);

sys/arch/arm/broadcom/bcm2835_aux.c

64

static int bcmaux_enable(void *, struct clk *);

sys/arch/arm/broadcom/bcm2835_aux.c

65

static int bcmaux_disable(void *, struct clk *);

sys/arch/arm/broadcom/bcm2835_aux.c

76

struct clk base;

sys/arch/arm/broadcom/bcm2835_aux.c

86

struct clk *sc_pclk;

sys/arch/arm/broadcom/bcm2835_bscvar.h

59

struct clk *sc_clk;

sys/arch/arm/broadcom/bcm2835_cm.c

137

bcm_cm_set(enum bcm_cm_clock clk, uint32_t ctl, uint32_t div)

sys/arch/arm/broadcom/bcm2835_cm.c

149

switch (clk) {

sys/arch/arm/broadcom/bcm2835_cm.c

207

bcm_cm_get(enum bcm_cm_clock clk, uint32_t *ctlp, uint32_t *divp)

sys/arch/arm/broadcom/bcm2835_cm.c

218

switch (clk) {

sys/arch/arm/broadcom/bcm2835_com.c

104

sc->sc_frequency = clk_get_rate(clk);

sys/arch/arm/broadcom/bcm2835_com.c

96

struct clk *clk;

sys/arch/arm/broadcom/bcm2835_com.c

97

for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++) {

sys/arch/arm/broadcom/bcm2835_com.c

98

if (clk_enable(clk) != 0) {

sys/arch/arm/broadcom/bcm2835_cprman.c

103

static struct clk *

sys/arch/arm/broadcom/bcm2835_cprman.c

120

cprman_put(void *priv, struct clk *clk)

sys/arch/arm/broadcom/bcm2835_cprman.c

125

cprman_get_rate(void *priv, struct clk *baseclk)

sys/arch/arm/broadcom/bcm2835_cprman.c

128

struct cprman_clk *clk = container_of(baseclk, struct cprman_clk, base);

sys/arch/arm/broadcom/bcm2835_cprman.c

130

switch (clk->id) {

sys/arch/arm/broadcom/bcm2835_cprman.c

140

panic("unsupported clock id %d\n", clk->id);

sys/arch/arm/broadcom/bcm2835_cprman.c

64

struct clk base;

sys/arch/arm/broadcom/bcm2835_cprman.c

77

static struct clk *

sys/arch/arm/broadcom/bcm2835_cprman.c

81

struct cprman_clk *clk;

sys/arch/arm/broadcom/bcm2835_cprman.c

92

clk = &sc->sc_clk[id];

sys/arch/arm/broadcom/bcm2835_cprman.c

93

if (clk->base.name == NULL)

sys/arch/arm/broadcom/bcm2835_cprman.c

96

return &clk->base;

sys/arch/arm/broadcom/bcm2835_emmc.c

148

struct clk *clk;

sys/arch/arm/broadcom/bcm2835_emmc.c

149

for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++) {

sys/arch/arm/broadcom/bcm2835_emmc.c

150

if (clk_enable(clk) != 0) {

sys/arch/arm/broadcom/bcm2835_emmc.c

155

sc->sc.sc_clkbase = clk_get_rate(clk) / 1000;

sys/arch/arm/broadcom/bcm2835_pwm.c

73

struct clk *sc_clk;

sys/arch/arm/broadcom/bcm2835_sdhost.c

223

struct clk *clk;

sys/arch/arm/broadcom/bcm2835_sdhost.c

224

for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++) {

sys/arch/arm/broadcom/bcm2835_sdhost.c

225

if (clk_enable(clk) != 0) {

sys/arch/arm/broadcom/bcm2835_sdhost.c

230

sc->sc_rate = clk_get_rate(clk);

sys/arch/arm/broadcom/bcm2835_spi.c

147

uint32_t cs, clk;

sys/arch/arm/broadcom/bcm2835_spi.c

178

clk = 2 * 250000000 / speed; /* XXX 250MHz */

sys/arch/arm/broadcom/bcm2835_spi.c

179

clk = (clk / 2) + (clk & 1);

sys/arch/arm/broadcom/bcm2835_spi.c

180

clk = roundup(clk, 2);

sys/arch/arm/broadcom/bcm2835_spi.c

181

if (clk >= 0xfffe)

sys/arch/arm/broadcom/bcm2835_spi.c

182

clk = 0xfffe;

sys/arch/arm/broadcom/bcm2835_spi.c

183

clk = __SHIFTIN(clk, SPI_CLK_CDIV);

sys/arch/arm/broadcom/bcm2835_spi.c

184

bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_CLK, clk);

sys/arch/arm/broadcom/bcm53xx_board.c

195

bcm53xx_freq_calc(struct bcm53xx_clock_info *clk,

sys/arch/arm/broadcom/bcm53xx_board.c

199

return ndiv_int * clk->clk_ref;

sys/arch/arm/broadcom/bcm53xx_board.c

202

freq64 *= clk->clk_ref;

sys/arch/arm/broadcom/bcm53xx_board.c

218

bcm53xx_genpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control5,

sys/arch/arm/broadcom/bcm53xx_board.c

228

clk->clk_genpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac);

sys/arch/arm/broadcom/bcm53xx_board.c

239

clk->clk_mac = clk->clk_genpll / ch0_mdiv; // GENPLL CH0

sys/arch/arm/broadcom/bcm53xx_board.c

240

clk->clk_robo = clk->clk_genpll / ch1_mdiv; // GENPLL CH1

sys/arch/arm/broadcom/bcm53xx_board.c

241

clk->clk_usb2 = clk->clk_genpll / ch2_mdiv; // GENPLL CH2

sys/arch/arm/broadcom/bcm53xx_board.c

242

clk->clk_iproc = clk->clk_genpll / ch3_mdiv; // GENPLL CH3

sys/arch/arm/broadcom/bcm53xx_board.c

246

bcm53xx_lcpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control1,

sys/arch/arm/broadcom/bcm53xx_board.c

256

clk->clk_lcpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac);

sys/arch/arm/broadcom/bcm53xx_board.c

267

clk->clk_pcie_ref = clk->clk_lcpll / ch0_mdiv; // LCPLL CH0

sys/arch/arm/broadcom/bcm53xx_board.c

268

clk->clk_sdio = clk->clk_lcpll / ch1_mdiv; // LCPLL CH1

sys/arch/arm/broadcom/bcm53xx_board.c

269

clk->clk_ddr_ref = clk->clk_lcpll / ch2_mdiv; // LCPLL CH2

sys/arch/arm/broadcom/bcm53xx_board.c

270

clk->clk_axi = clk->clk_lcpll / ch3_mdiv; // LCPLL CH3

sys/arch/arm/broadcom/bcm53xx_board.c

274

bcm53xx_usb_clock_init(struct bcm53xx_clock_info *clk, uint32_t usb2_control)

sys/arch/arm/broadcom/bcm53xx_board.c

281

uint32_t usb_ref = (clk->clk_usb2 / pdiv) * ndiv;

sys/arch/arm/broadcom/bcm53xx_board.c

287

uint32_t new_ndiv = (USB2_REF_CLK / clk->clk_usb2) * pdiv;

sys/arch/arm/broadcom/bcm53xx_board.c

303

usb_ref = (clk->clk_usb2 / pdiv) * new_ndiv;

sys/arch/arm/broadcom/bcm53xx_board.c

306

clk->clk_usb_ref = usb_ref;

sys/arch/arm/broadcom/bcm53xx_board.c

311

bcm53xx_clock_init(struct bcm53xx_clock_info *clk)

sys/arch/arm/broadcom/bcm53xx_board.c

313

clk->clk_ref = BCM53XX_REF_CLK;

sys/arch/arm/broadcom/bcm53xx_board.c

314

clk->clk_sys = 8*clk->clk_ref;

sys/arch/arm/broadcom/bcm53xx_board.c

321

bcm53xx_get_ddr_freq(struct bcm53xx_clock_info *clk, uint32_t pll_status,

sys/arch/arm/broadcom/bcm53xx_board.c

331

clk->clk_ddr_mhz = __SHIFTOUT(pll_status, PLL_STATUS_MHZ);

sys/arch/arm/broadcom/bcm53xx_board.c

332

clk->clk_ddr = (clk->clk_ddr_ref / pdiv) * ndiv / (2 + post_div);

sys/arch/arm/broadcom/bcm53xx_board.c

339

bcm53xx_get_cpu_freq(struct bcm53xx_clock_info *clk,

sys/arch/arm/broadcom/bcm53xx_board.c

345

clk->clk_cpu = clk->clk_ref;

sys/arch/arm/broadcom/bcm53xx_board.c

346

clk->clk_apb = clk->clk_cpu;

sys/arch/arm/broadcom/bcm53xx_board.c

351

clk->clk_cpu = clk->clk_sys;

sys/arch/arm/broadcom/bcm53xx_board.c

352

clk->clk_apb = clk->clk_cpu / 4;

sys/arch/arm/broadcom/bcm53xx_board.c

363

clk->clk_cpu = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac) / cpu_div;

sys/arch/arm/broadcom/bcm53xx_board.c

364

clk->clk_apb = clk->clk_cpu / 4;

sys/arch/arm/broadcom/bcm53xx_board.c

443

const struct bcm53xx_clock_info * const clk = &cpu_softc.cpu_clk;

sys/arch/arm/broadcom/bcm53xx_board.c

444

printf("ref clk = %u (%#x)\n", clk->clk_ref, clk->clk_ref);

sys/arch/arm/broadcom/bcm53xx_board.c

445

printf("sys clk = %u (%#x)\n", clk->clk_sys, clk->clk_sys);

sys/arch/arm/broadcom/bcm53xx_board.c

446

printf("lcpll clk = %u (%#x)\n", clk->clk_lcpll, clk->clk_lcpll);

sys/arch/arm/broadcom/bcm53xx_board.c

447

printf("pcie ref clk = %u (%#x) [CH0]\n", clk->clk_pcie_ref, clk->clk_pcie_ref);

sys/arch/arm/broadcom/bcm53xx_board.c

448

printf("sdio clk = %u (%#x) [CH1]\n", clk->clk_sdio, clk->clk_sdio);

sys/arch/arm/broadcom/bcm53xx_board.c

449

printf("ddr ref clk = %u (%#x) [CH2]\n", clk->clk_ddr_ref, clk->clk_ddr_ref);

sys/arch/arm/broadcom/bcm53xx_board.c

450

printf("axi clk = %u (%#x) [CH3]\n", clk->clk_axi, clk->clk_axi);

sys/arch/arm/broadcom/bcm53xx_board.c

451

printf("genpll clk = %u (%#x)\n", clk->clk_genpll, clk->clk_genpll);

sys/arch/arm/broadcom/bcm53xx_board.c

452

printf("mac clk = %u (%#x) [CH0]\n", clk->clk_mac, clk->clk_mac);

sys/arch/arm/broadcom/bcm53xx_board.c

453

printf("robo clk = %u (%#x) [CH1]\n", clk->clk_robo, clk->clk_robo);

sys/arch/arm/broadcom/bcm53xx_board.c

454

printf("usb2 clk = %u (%#x) [CH2]\n", clk->clk_usb2, clk->clk_usb2);

sys/arch/arm/broadcom/bcm53xx_board.c

455

printf("iproc clk = %u (%#x) [CH3]\n", clk->clk_iproc, clk->clk_iproc);

sys/arch/arm/broadcom/bcm53xx_board.c

456

printf("ddr clk = %u (%#x)\n", clk->clk_ddr, clk->clk_ddr);

sys/arch/arm/broadcom/bcm53xx_board.c

457

printf("ddr mhz = %u (%#x)\n", clk->clk_ddr_mhz, clk->clk_ddr_mhz);

sys/arch/arm/broadcom/bcm53xx_board.c

458

printf("cpu clk = %u (%#x)\n", clk->clk_cpu, clk->clk_cpu);

sys/arch/arm/broadcom/bcm53xx_board.c

459

printf("apb clk = %u (%#x)\n", clk->clk_apb, clk->clk_apb);

sys/arch/arm/broadcom/bcm53xx_board.c

460

printf("usb ref clk = %u (%#x)\n", clk->clk_usb_ref, clk->clk_usb_ref);

sys/arch/arm/broadcom/bcm53xx_board.c

489

struct bcm53xx_clock_info * const clk = &cpu_softc.cpu_clk;

sys/arch/arm/broadcom/bcm53xx_board.c

491

bcm53xx_clock_init(clk);

sys/arch/arm/broadcom/bcm53xx_board.c

492

bcm53xx_lcpll_clock_init(clk, bcs.bcs_lcpll_control1,

sys/arch/arm/broadcom/bcm53xx_board.c

494

bcm53xx_genpll_clock_init(clk, bcs.bcs_genpll_control5,

sys/arch/arm/broadcom/bcm53xx_board.c

496

bcm53xx_usb_clock_init(clk, bcs.bcs_usb2_control);

sys/arch/arm/broadcom/bcm53xx_board.c

497

bcm53xx_get_ddr_freq(clk, bcs.bcs_ddr_phy_ctl_pll_status,

sys/arch/arm/broadcom/bcm53xx_board.c

499

bcm53xx_get_cpu_freq(clk, bcs.bcs_armcore_clk_pllarma,

sys/arch/arm/broadcom/bcm53xx_board.c

502

curcpu()->ci_data.cpu_cc_freq = clk->clk_cpu;

sys/arch/arm/fdt/a9ptmr_fdt.c

57

struct clk *sc_clk;

sys/arch/arm/fdt/a9tmr_fdt.c

57

struct clk *sc_clk;

sys/arch/arm/fdt/a9wdt_fdt.c

64

struct clk *sc_clk;

sys/arch/arm/fdt/aaci_fdt.c

68

struct clk *clk;

sys/arch/arm/fdt/aaci_fdt.c

83

for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++)

sys/arch/arm/fdt/aaci_fdt.c

84

if (clk_enable(clk) != 0) {

sys/arch/arm/fdt/plcom_fdt.c

71

struct clk *clk;

sys/arch/arm/fdt/plcom_fdt.c

91

for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++) {

sys/arch/arm/fdt/plcom_fdt.c

92

if (clk_enable(clk) != 0) {

sys/arch/arm/fdt/plcom_fdt.c

98

sc->sc_frequency = clk_get_rate(clk);

sys/arch/arm/fdt/plfb_fdt.c

128

struct clk *clk;

sys/arch/arm/fdt/plfb_fdt.c

137

for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++)

sys/arch/arm/fdt/plfb_fdt.c

138

if (clk_enable(clk) != 0) {

sys/arch/arm/fdt/plkmi_fdt.c

68

struct clk *clk;

sys/arch/arm/fdt/plkmi_fdt.c

84

for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++)

sys/arch/arm/fdt/plkmi_fdt.c

85

if (clk_enable(clk) != 0) {

sys/arch/arm/fdt/plmmc_fdt.c

69

struct clk *clk;

sys/arch/arm/fdt/plmmc_fdt.c

79

clk = fdtbus_clock_get_index(phandle, 0);

sys/arch/arm/fdt/plmmc_fdt.c

80

if (clk == NULL) {

sys/arch/arm/fdt/plmmc_fdt.c

85

if (clk_enable(clk) != 0) {

sys/arch/arm/fdt/plmmc_fdt.c

97

sc->sc_clock_freq = clk_get_rate(clk);

sys/arch/arm/gemini/gemini_lpc.c

104

device_xname(self), clk, susp);

sys/arch/arm/gemini/gemini_lpc.c

73

uint8_t id1, id2, vers, clk, susp;

sys/arch/arm/gemini/gemini_lpc.c

97

clk = it8712_pnp_read(sc, GEMINI_LPC_LDN_ALL, IT8712_CLKSEL);

sys/arch/arm/imx/if_enetvar.h

64

struct clk *sc_clk_ipg;

sys/arch/arm/imx/if_enetvar.h

65

struct clk *sc_clk_enet;

sys/arch/arm/imx/if_enetvar.h

66

struct clk *sc_clk_enet_ref;

sys/arch/arm/imx/imx31_clock.c

117

struct imx31_clocks clk;

sys/arch/arm/imx/imx31_clock.c

118

imx31_get_clocks(&clk);

sys/arch/arm/imx/imx31_clock.c

120

return clk.ipg_clk;

sys/arch/arm/imx/imx51_ccm.c

148

imx51_get_clock(enum imx51_clock clk)

sys/arch/arm/imx/imx51_ccm.c

164

switch (clk) {

sys/arch/arm/imx/imx51_ccm.c

168

return ccm_softc->sc_pll[clk - IMX51CLK_PLL1].pll_freq;

sys/arch/arm/imx/imx51_ccm.c

337

if (clk == IMX51CLK_ESDHC2_CLK_ROOT)

sys/arch/arm/imx/imx51_ccm.c

339

else if (clk == IMX51CLK_ESDHC4_CLK_ROOT)

sys/arch/arm/imx/imx51_ccm.c

355

if (clk == IMX51CLK_ESDHC1_CLK_ROOT)

sys/arch/arm/imx/imx51_ccm.c

357

else if (clk == IMX51CLK_ESDHC3_CLK_ROOT)

sys/arch/arm/imx/imx51_ccm.c

383

if (clk == IMX51CLK_ESDHC1_CLK_ROOT)

sys/arch/arm/imx/imx51_ccm.c

386

else if (clk == IMX51CLK_ESDHC3_CLK_ROOT)

sys/arch/arm/imx/imx51_ccm.c

396

if (clk == IMX51CLK_ESDHC3_CLK_ROOT)

sys/arch/arm/imx/imx51_ccm.c

398

else if (clk == IMX51CLK_ESDHC4_CLK_ROOT)

sys/arch/arm/imx/imx51_ccm.c

414

if (clk == IMX51CLK_ESDHC1_CLK_ROOT)

sys/arch/arm/imx/imx51_ccm.c

416

else if (clk == IMX51CLK_ESDHC2_CLK_ROOT)

sys/arch/arm/imx/imx51_ccm.c

430

if (clk == IMX51CLK_ESDHC1_CLK_ROOT)

sys/arch/arm/imx/imx51_ccm.c

433

else if (clk == IMX51CLK_ESDHC2_CLK_ROOT)

sys/arch/arm/imx/imx51_ccm.c

467

freq = imx51_get_pfd_freq(clk - IMX50CLK_PFD0_CLK_ROOT);

sys/arch/arm/imx/imx51_ccm.c

472

"clock %d: not supported yet\n", clk);

sys/arch/arm/imx/imx51_ccmreg.h

177

#define CCMR_CCGR_MODULE(clk) ((clk) / CCMR_CCGR_NSOURCE)

sys/arch/arm/imx/imxi2cvar.h

39

struct clk *sc_clk;

sys/arch/arm/imx/imxpcievar.h

54

struct clk *sc_clk_pcie;

sys/arch/arm/imx/imxpcievar.h

55

struct clk *sc_clk_pcie_bus;

sys/arch/arm/imx/imxpcievar.h

56

struct clk *sc_clk_pcie_phy;

sys/arch/arm/imx/imxpcievar.h

57

struct clk *sc_clk_pcie_ext;

sys/arch/arm/imx/imxpcievar.h

58

struct clk *sc_clk_pcie_ext_src;

sys/arch/arm/imx/imxpwmvar.h

41

struct clk *sc_clk;

sys/arch/arm/imx/imxusbvar.h

45

struct clk *sc_clk;

sys/arch/arm/nvidia/tegra124_car.c

1008

tegra124_car_clock_put(void *priv, struct clk *clk)

sys/arch/arm/nvidia/tegra124_car.c

1010

struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);

sys/arch/arm/nvidia/tegra124_car.c

1056

struct clk *clk_parent;

sys/arch/arm/nvidia/tegra124_car.c

1211

struct clk *clk_parent;

sys/arch/arm/nvidia/tegra124_car.c

1238

struct clk *clk_parent;

sys/arch/arm/nvidia/tegra124_car.c

1285

struct clk *clk_parent;

sys/arch/arm/nvidia/tegra124_car.c

1401

tegra124_car_clock_get_rate(void *priv, struct clk *clk)

sys/arch/arm/nvidia/tegra124_car.c

1403

struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);

sys/arch/arm/nvidia/tegra124_car.c

1404

struct clk *clk_parent;

sys/arch/arm/nvidia/tegra124_car.c

1413

clk_parent = tegra124_car_clock_get_parent(priv, clk);

sys/arch/arm/nvidia/tegra124_car.c

1427

tegra124_car_clock_set_rate(void *priv, struct clk *clk, u_int rate)

sys/arch/arm/nvidia/tegra124_car.c

1429

struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);

sys/arch/arm/nvidia/tegra124_car.c

1430

struct clk *clk_parent;

sys/arch/arm/nvidia/tegra124_car.c

1432

KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0);

sys/arch/arm/nvidia/tegra124_car.c

1439

clk_parent = tegra124_car_clock_get_parent(priv, clk);

sys/arch/arm/nvidia/tegra124_car.c

1456

tegra124_car_clock_enable(void *priv, struct clk *clk)

sys/arch/arm/nvidia/tegra124_car.c

1458

struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);

sys/arch/arm/nvidia/tegra124_car.c

1459

struct clk *clk_parent;

sys/arch/arm/nvidia/tegra124_car.c

1462

clk_parent = tegra124_car_clock_get_parent(priv, clk);

sys/arch/arm/nvidia/tegra124_car.c

1472

tegra124_car_clock_disable(void *priv, struct clk *clk)

sys/arch/arm/nvidia/tegra124_car.c

1474

struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);

sys/arch/arm/nvidia/tegra124_car.c

1483

tegra124_car_clock_set_parent(void *priv, struct clk *clk,

sys/arch/arm/nvidia/tegra124_car.c

1484

struct clk *clk_parent)

sys/arch/arm/nvidia/tegra124_car.c

1486

struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);

sys/arch/arm/nvidia/tegra124_car.c

1488

struct clk *nclk_parent;

sys/arch/arm/nvidia/tegra124_car.c

1491

nclk_parent = tegra124_car_clock_get_parent(priv, clk);

sys/arch/arm/nvidia/tegra124_car.c

1501

static struct clk *

sys/arch/arm/nvidia/tegra124_car.c

1502

tegra124_car_clock_get_parent(void *priv, struct clk *clk)

sys/arch/arm/nvidia/tegra124_car.c

1504

struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);

sys/arch/arm/nvidia/tegra124_car.c

271

static struct clk *tegra124_car_clock_get(void *, const char *);

sys/arch/arm/nvidia/tegra124_car.c

272

static void tegra124_car_clock_put(void *, struct clk *);

sys/arch/arm/nvidia/tegra124_car.c

273

static u_int tegra124_car_clock_get_rate(void *, struct clk *);

sys/arch/arm/nvidia/tegra124_car.c

274

static int tegra124_car_clock_set_rate(void *, struct clk *, u_int);

sys/arch/arm/nvidia/tegra124_car.c

275

static int tegra124_car_clock_enable(void *, struct clk *);

sys/arch/arm/nvidia/tegra124_car.c

276

static int tegra124_car_clock_disable(void *, struct clk *);

sys/arch/arm/nvidia/tegra124_car.c

277

static int tegra124_car_clock_set_parent(void *, struct clk *,

sys/arch/arm/nvidia/tegra124_car.c

278

struct clk *);

sys/arch/arm/nvidia/tegra124_car.c

279

static struct clk *tegra124_car_clock_get_parent(void *, struct clk *);

sys/arch/arm/nvidia/tegra124_car.c

55

static struct clk *tegra124_car_clock_decode(device_t, int, const void *,

sys/arch/arm/nvidia/tegra124_car.c

803

struct clk *clk, *clk_parent;

sys/arch/arm/nvidia/tegra124_car.c

808

clk = clk_get(&sc->sc_clkdom, tegra124_init_parents[n].clock);

sys/arch/arm/nvidia/tegra124_car.c

809

KASSERT(clk != NULL);

sys/arch/arm/nvidia/tegra124_car.c

814

error = clk_set_parent(clk, clk_parent);

sys/arch/arm/nvidia/tegra124_car.c

818

clk->name, clk_parent->name, error);

sys/arch/arm/nvidia/tegra124_car.c

821

clk_put(clk);

sys/arch/arm/nvidia/tegra124_car.c

973

static struct clk *

sys/arch/arm/nvidia/tegra124_car.c

993

static struct clk *

sys/arch/arm/nvidia/tegra124_cpu.c

119

static struct clk *tegra124_clk_pllx = NULL;

sys/arch/arm/nvidia/tegra210_car.c

1095

static struct clk *

sys/arch/arm/nvidia/tegra210_car.c

1115

static struct clk *

sys/arch/arm/nvidia/tegra210_car.c

1130

tegra210_car_clock_put(void *priv, struct clk *clk)

sys/arch/arm/nvidia/tegra210_car.c

1132

struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);

sys/arch/arm/nvidia/tegra210_car.c

1184

struct clk *clk_parent;

sys/arch/arm/nvidia/tegra210_car.c

1317

struct clk *clk_parent;

sys/arch/arm/nvidia/tegra210_car.c

1334

struct clk *clk_parent;

sys/arch/arm/nvidia/tegra210_car.c

1389

struct clk *clk_parent;

sys/arch/arm/nvidia/tegra210_car.c

1491

tegra210_car_clock_get_rate(void *priv, struct clk *clk)

sys/arch/arm/nvidia/tegra210_car.c

1493

struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);

sys/arch/arm/nvidia/tegra210_car.c

1494

struct clk *clk_parent;

sys/arch/arm/nvidia/tegra210_car.c

1503

clk_parent = tegra210_car_clock_get_parent(priv, clk);

sys/arch/arm/nvidia/tegra210_car.c

1517

tegra210_car_clock_set_rate(void *priv, struct clk *clk, u_int rate)

sys/arch/arm/nvidia/tegra210_car.c

1519

struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);

sys/arch/arm/nvidia/tegra210_car.c

1520

struct clk *clk_parent;

sys/arch/arm/nvidia/tegra210_car.c

1522

KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0);

sys/arch/arm/nvidia/tegra210_car.c

1529

clk_parent = tegra210_car_clock_get_parent(priv, clk);

sys/arch/arm/nvidia/tegra210_car.c

1546

tegra210_car_clock_enable(void *priv, struct clk *clk)

sys/arch/arm/nvidia/tegra210_car.c

1548

struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);

sys/arch/arm/nvidia/tegra210_car.c

1549

struct clk *clk_parent;

sys/arch/arm/nvidia/tegra210_car.c

1552

clk_parent = tegra210_car_clock_get_parent(priv, clk);

sys/arch/arm/nvidia/tegra210_car.c

1562

tegra210_car_clock_disable(void *priv, struct clk *clk)

sys/arch/arm/nvidia/tegra210_car.c

1564

struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);

sys/arch/arm/nvidia/tegra210_car.c

1573

tegra210_car_clock_set_parent(void *priv, struct clk *clk,

sys/arch/arm/nvidia/tegra210_car.c

1574

struct clk *clk_parent)

sys/arch/arm/nvidia/tegra210_car.c

1576

struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);

sys/arch/arm/nvidia/tegra210_car.c

1578

struct clk *nclk_parent;

sys/arch/arm/nvidia/tegra210_car.c

1581

nclk_parent = tegra210_car_clock_get_parent(priv, clk);

sys/arch/arm/nvidia/tegra210_car.c

1591

static struct clk *

sys/arch/arm/nvidia/tegra210_car.c

1592

tegra210_car_clock_get_parent(void *priv, struct clk *clk)

sys/arch/arm/nvidia/tegra210_car.c

1594

struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);

sys/arch/arm/nvidia/tegra210_car.c

283

static struct clk *tegra210_car_clock_get(void *, const char *);

sys/arch/arm/nvidia/tegra210_car.c

284

static void tegra210_car_clock_put(void *, struct clk *);

sys/arch/arm/nvidia/tegra210_car.c

285

static u_int tegra210_car_clock_get_rate(void *, struct clk *);

sys/arch/arm/nvidia/tegra210_car.c

286

static int tegra210_car_clock_set_rate(void *, struct clk *, u_int);

sys/arch/arm/nvidia/tegra210_car.c

287

static int tegra210_car_clock_enable(void *, struct clk *);

sys/arch/arm/nvidia/tegra210_car.c

288

static int tegra210_car_clock_disable(void *, struct clk *);

sys/arch/arm/nvidia/tegra210_car.c

289

static int tegra210_car_clock_set_parent(void *, struct clk *,

sys/arch/arm/nvidia/tegra210_car.c

290

struct clk *);

sys/arch/arm/nvidia/tegra210_car.c

291

static struct clk *tegra210_car_clock_get_parent(void *, struct clk *);

sys/arch/arm/nvidia/tegra210_car.c

55

static struct clk *tegra210_car_clock_decode(device_t, int, const void *,

sys/arch/arm/nvidia/tegra210_car.c

804

struct clk *clk = TEGRA_CLK_BASE(&tegra210_car_clocks[n]);

sys/arch/arm/nvidia/tegra210_car.c

805

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/arm/nvidia/tegra210_car.c

806

device_printf(self, "clk %s (parent %s): ", clk->name,

sys/arch/arm/nvidia/tegra210_car.c

808

printf("%u Hz\n", clk_get_rate(clk));

sys/arch/arm/nvidia/tegra210_car.c

825

struct clk *clk, *clk_parent;

sys/arch/arm/nvidia/tegra210_car.c

830

clk = clk_get(&sc->sc_clkdom, tegra210_init_parents[n].clock);

sys/arch/arm/nvidia/tegra210_car.c

831

KASSERTMSG(clk != NULL, "tegra210 clock %s not found", tegra210_init_parents[n].clock);

sys/arch/arm/nvidia/tegra210_car.c

838

error = clk_set_parent(clk, clk_parent);

sys/arch/arm/nvidia/tegra210_car.c

842

clk->name, clk_parent->name, error);

sys/arch/arm/nvidia/tegra210_car.c

847

error = clk_set_rate(clk, tegra210_init_parents[n].rate);

sys/arch/arm/nvidia/tegra210_car.c

851

clk->name, tegra210_init_parents[n].rate,

sys/arch/arm/nvidia/tegra210_car.c

856

error = clk_enable(clk);

sys/arch/arm/nvidia/tegra210_car.c

859

"couldn't enable '%s': %d\n", clk->name,

sys/arch/arm/nvidia/tegra210_car.c

863

clk_put(clk);

sys/arch/arm/nvidia/tegra210_xusbpad.c

723

struct clk *clk;

sys/arch/arm/nvidia/tegra210_xusbpad.c

743

clk = fdtbus_clock_get_index(phandle, 0);

sys/arch/arm/nvidia/tegra210_xusbpad.c

744

if (clk == NULL || clk_enable(clk) != 0) {

sys/arch/arm/nvidia/tegra_ahcisata.c

61

struct clk *sc_clk_sata;

sys/arch/arm/nvidia/tegra_ahcisata.c

62

struct clk *sc_clk_sata_oob;

sys/arch/arm/nvidia/tegra_ahcisata.c

63

struct clk *sc_clk_cml1;

sys/arch/arm/nvidia/tegra_ahcisata.c

64

struct clk *sc_clk_pll_e;

sys/arch/arm/nvidia/tegra_apbdma.c

115

struct clk *clk;

sys/arch/arm/nvidia/tegra_apbdma.c

126

clk = fdtbus_clock_get_index(phandle, 0);

sys/arch/arm/nvidia/tegra_apbdma.c

127

if (clk == NULL) {

sys/arch/arm/nvidia/tegra_apbdma.c

138

error = clk_enable(clk);

sys/arch/arm/nvidia/tegra_cec.c

64

struct clk *sc_clk;

sys/arch/arm/nvidia/tegra_clock.h

75

struct clk base; /* must be first */

sys/arch/arm/nvidia/tegra_com.c

66

struct clk *tsc_clk;

sys/arch/arm/nvidia/tegra_drm.h

102

struct clk *clk_parent;

sys/arch/arm/nvidia/tegra_drm.h

65

struct clk *sc_clk_host1x;

sys/arch/arm/nvidia/tegra_drm.h

68

struct clk *sc_clk_dc[2];

sys/arch/arm/nvidia/tegra_drm.h

69

struct clk *sc_clk_dc_parent[2];

sys/arch/arm/nvidia/tegra_drm.h

72

struct clk *sc_clk_hdmi;

sys/arch/arm/nvidia/tegra_drm.h

73

struct clk *sc_clk_hdmi_parent;

sys/arch/arm/nvidia/tegra_fuse.c

52

struct clk *sc_clk;

sys/arch/arm/nvidia/tegra_hdaudio.c

70

struct clk *sc_clk_hda;

sys/arch/arm/nvidia/tegra_hdaudio.c

71

struct clk *sc_clk_hda2hdmi;

sys/arch/arm/nvidia/tegra_hdaudio.c

72

struct clk *sc_clk_hda2codec_2x;

sys/arch/arm/nvidia/tegra_i2c.c

55

struct clk * sc_clk;

sys/arch/arm/nvidia/tegra_nouveau.c

71

struct clk *sc_clk_gpu;

sys/arch/arm/nvidia/tegra_nouveau.c

72

struct clk *sc_clk_pwr;

sys/arch/arm/nvidia/tegra_pcie.c

354

struct clk *clk;

sys/arch/arm/nvidia/tegra_pcie.c

358

clk = fdtbus_clock_get(sc->sc_phandle, clock_names[n]);

sys/arch/arm/nvidia/tegra_pcie.c

359

if (clk == NULL || clk_enable(clk) != 0)

sys/arch/arm/nvidia/tegra_sdhc.c

62

struct clk *sc_clk;

sys/arch/arm/nvidia/tegra_soctherm.c

123

struct clk *sc_clk_tsensor;

sys/arch/arm/nvidia/tegra_soctherm.c

124

struct clk *sc_clk_soctherm;

sys/arch/arm/nvidia/tegra_usbphy.c

54

struct clk *sc_clk_reg;

sys/arch/arm/nvidia/tegra_usbphy.c

55

struct clk *sc_clk_pll;

sys/arch/arm/nvidia/tegra_usbphy.c

56

struct clk *sc_clk_utmip;

sys/arch/arm/nvidia/tegra_xusb.c

171

struct clk *sc_clk_ss_src;

sys/arch/arm/nvidia/tegra_xusb.c

219

struct clk *clk;

sys/arch/arm/nvidia/tegra_xusb.c

312

clk = fdtbus_clock_get(faa->faa_phandle, "pll_e");

sys/arch/arm/nvidia/tegra_xusb.c

313

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

314

error = clk_enable(clk); /* XXX set frequency */

sys/arch/arm/nvidia/tegra_xusb.c

318

clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src");

sys/arch/arm/nvidia/tegra_xusb.c

319

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

321

error = clk_set_rate(clk, 102000000);

sys/arch/arm/nvidia/tegra_xusb.c

324

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

325

error = clk_enable(clk); /* XXX set frequency */

sys/arch/arm/nvidia/tegra_xusb.c

329

clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src");

sys/arch/arm/nvidia/tegra_xusb.c

330

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

332

error = clk_set_rate(clk, 204000000);

sys/arch/arm/nvidia/tegra_xusb.c

335

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

336

error = clk_enable(clk);

sys/arch/arm/nvidia/tegra_xusb.c

340

clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host");

sys/arch/arm/nvidia/tegra_xusb.c

341

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

342

error = clk_enable(clk); /* XXX set frequency */

sys/arch/arm/nvidia/tegra_xusb.c

345

clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss");

sys/arch/arm/nvidia/tegra_xusb.c

346

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

347

error = clk_enable(clk); /* XXX set frequency */

sys/arch/arm/nvidia/tegra_xusb.c

379

clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src");

sys/arch/arm/nvidia/tegra_xusb.c

381

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

385

clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src");

sys/arch/arm/nvidia/tegra_xusb.c

386

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

387

error = clk_enable(clk); /* XXX set frequency */

sys/arch/arm/nvidia/tegra_xusb.c

428

struct clk *clk;

sys/arch/arm/nvidia/tegra_xusb.c

445

clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src");

sys/arch/arm/nvidia/tegra_xusb.c

446

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

447

error = clk_enable(clk);

sys/arch/arm/nvidia/tegra_xusb.c

450

clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src");

sys/arch/arm/nvidia/tegra_xusb.c

451

rate = clk_get_rate(clk);

sys/arch/arm/nvidia/tegra_xusb.c

452

error = clk_enable(clk);

sys/arch/arm/nxp/imx6_ccm.c

102

aprint_verbose_dev(self, "%s (%s) : %u Hz\n", clk->name,

sys/arch/arm/nxp/imx6_ccm.c

103

parent_str, clk_get_rate(clk));

sys/arch/arm/nxp/imx6_ccm.c

107

struct clk *

sys/arch/arm/nxp/imx6_ccm.c

137

struct clk *clk;

sys/arch/arm/nxp/imx6_ccm.c

138

struct clk *clk_parent;

sys/arch/arm/nxp/imx6_ccm.c

141

clk = clk_get(&sc->sc_clkdom, imxccm_init_parents[n].clock);

sys/arch/arm/nxp/imx6_ccm.c

142

KASSERT(clk != NULL);

sys/arch/arm/nxp/imx6_ccm.c

146

int error = clk_set_parent(clk, clk_parent);

sys/arch/arm/nxp/imx6_ccm.c

150

clk->name, clk_parent->name, error);

sys/arch/arm/nxp/imx6_ccm.c

153

clk_put(clk);

sys/arch/arm/nxp/imx6_ccm.c

161

struct imx6_clk_pll *pll = &iclk->clk.pll;

sys/arch/arm/nxp/imx6_ccm.c

177

struct imx6_clk_pll *pll = &iclk->clk.pll;

sys/arch/arm/nxp/imx6_ccm.c

195

struct imx6_clk_pll *pll = &iclk->clk.pll;

sys/arch/arm/nxp/imx6_ccm.c

216

struct imx6_clk_pll *pll = &iclk->clk.pll;

sys/arch/arm/nxp/imx6_ccm.c

226

struct imx6_clk_fixed_factor *fixed_factor = &iclk->clk.fixed_factor;

sys/arch/arm/nxp/imx6_ccm.c

242

struct imx6_clk_pll *pll = &iclk->clk.pll;

sys/arch/arm/nxp/imx6_ccm.c

271

struct imx6_clk_div *div = &iclk->clk.div;

sys/arch/arm/nxp/imx6_ccm.c

306

struct imx6_clk_pfd *pfd = &iclk->clk.pfd;

sys/arch/arm/nxp/imx6_ccm.c

344

struct imx6_clk *iclk, struct clk *parent)

sys/arch/arm/nxp/imx6_ccm.c

346

struct imx6_clk_mux *mux = &iclk->clk.mux;

sys/arch/arm/nxp/imx6_ccm.c

382

struct imx6_clk_mux *mux = &iclk->clk.mux;

sys/arch/arm/nxp/imx6_ccm.c

416

struct imx6_clk_div *div = &iclk->clk.div;

sys/arch/arm/nxp/imx6_ccm.c

458

static struct clk *

sys/arch/arm/nxp/imx6_ccm.c

474

imxccm_clk_put(void *priv, struct clk *clk)

sys/arch/arm/nxp/imx6_ccm.c

476

struct imx6_clk *iclk = (struct imx6_clk *)clk;

sys/arch/arm/nxp/imx6_ccm.c

484

imxccm_clk_get_rate(void *priv, struct clk *clk)

sys/arch/arm/nxp/imx6_ccm.c

486

struct imx6_clk *iclk = (struct imx6_clk *)clk;

sys/arch/arm/nxp/imx6_ccm.c

487

struct clk *parent;

sys/arch/arm/nxp/imx6_ccm.c

492

return iclk->clk.fixed.rate;

sys/arch/arm/nxp/imx6_ccm.c

499

parent = imxccm_clk_get_parent(sc, clk);

sys/arch/arm/nxp/imx6_ccm.c

511

imxccm_clk_set_rate(void *priv, struct clk *clk, u_int rate)

sys/arch/arm/nxp/imx6_ccm.c

513

struct imx6_clk *iclk = (struct imx6_clk *)clk;

sys/arch/arm/nxp/imx6_ccm.c

538

struct imx6_clk_pll *pll = &iclk->clk.pll;

sys/arch/arm/nxp/imx6_ccm.c

566

struct imx6_clk_gate *gate = &iclk->clk.gate;

sys/arch/arm/nxp/imx6_ccm.c

57

static struct clk *imxccm_clk_get(void *, const char *);

sys/arch/arm/nxp/imx6_ccm.c

58

static void imxccm_clk_put(void *, struct clk *);

sys/arch/arm/nxp/imx6_ccm.c

59

static u_int imxccm_clk_get_rate(void *, struct clk *);

sys/arch/arm/nxp/imx6_ccm.c

592

imxccm_clk_enable(void *priv, struct clk *clk)

sys/arch/arm/nxp/imx6_ccm.c

594

struct imx6_clk *iclk = (struct imx6_clk *)clk;

sys/arch/arm/nxp/imx6_ccm.c

60

static int imxccm_clk_set_rate(void *, struct clk *, u_int);

sys/arch/arm/nxp/imx6_ccm.c

61

static int imxccm_clk_enable(void *, struct clk *);

sys/arch/arm/nxp/imx6_ccm.c

619

imxccm_clk_disable(void *priv, struct clk *clk)

sys/arch/arm/nxp/imx6_ccm.c

62

static int imxccm_clk_disable(void *, struct clk *);

sys/arch/arm/nxp/imx6_ccm.c

621

struct imx6_clk *iclk = (struct imx6_clk *)clk;

sys/arch/arm/nxp/imx6_ccm.c

63

static int imxccm_clk_set_parent(void *, struct clk *, struct clk *);

sys/arch/arm/nxp/imx6_ccm.c

64

static struct clk *imxccm_clk_get_parent(void *, struct clk *);

sys/arch/arm/nxp/imx6_ccm.c

642

imxccm_clk_set_parent(void *priv, struct clk *clk, struct clk *parent)

sys/arch/arm/nxp/imx6_ccm.c

644

struct imx6_clk *iclk = (struct imx6_clk *)clk;

sys/arch/arm/nxp/imx6_ccm.c

662

static struct clk *

sys/arch/arm/nxp/imx6_ccm.c

663

imxccm_clk_get_parent(void *priv, struct clk *clk)

sys/arch/arm/nxp/imx6_ccm.c

665

struct imx6_clk *iclk = (struct imx6_clk *)clk;

sys/arch/arm/nxp/imx6_ccm.c

686

return (struct clk *)parent;

sys/arch/arm/nxp/imx6_ccm.c

98

struct clk *clk = &imx6_clks[n].base;

sys/arch/arm/nxp/imx6_ccm.c

99

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/arm/nxp/imx6_ccmvar.h

144

struct clk base; /* must be first */

sys/arch/arm/nxp/imx6_ccmvar.h

158

} clk;

sys/arch/arm/nxp/imx6_ccmvar.h

164

.clk = { \

sys/arch/arm/nxp/imx6_ccmvar.h

175

.clk = { \

sys/arch/arm/nxp/imx6_ccmvar.h

187

.clk = { \

sys/arch/arm/nxp/imx6_ccmvar.h

199

.clk = { \

sys/arch/arm/nxp/imx6_ccmvar.h

214

.clk = { \

sys/arch/arm/nxp/imx6_ccmvar.h

228

.clk = { \

sys/arch/arm/nxp/imx6_ccmvar.h

244

.clk = { \

sys/arch/arm/nxp/imx6_ccmvar.h

258

.clk = { \

sys/arch/arm/nxp/imx6_ccmvar.h

273

.clk = { \

sys/arch/arm/nxp/imx6_ccmvar.h

291

.clk = { \

sys/arch/arm/nxp/imx6_ccmvar.h

305

.clk = { \

sys/arch/arm/nxp/imx6_ccmvar.h

50

struct clk *imx6_get_clock(struct imx6ccm_softc *, const char *);

sys/arch/arm/nxp/imx6_clk.c

1174

static struct clk *

sys/arch/arm/nxp/imx6_clk.c

1186

static struct clk *imx6q_clk_decode(device_t, int, const void *, size_t);

sys/arch/arm/nxp/imx6_clk.c

1192

static struct clk *

sys/arch/arm/nxp/imx6_clk.c

1195

struct clk *clk;

sys/arch/arm/nxp/imx6_clk.c

1204

clk = imx6q_get_clock_by_id(sc, clock_id);

sys/arch/arm/nxp/imx6_clk.c

1205

if (clk)

sys/arch/arm/nxp/imx6_clk.c

1206

return clk;

sys/arch/arm/nxp/imx6_clk.c

1223

if (of_getprop_uint32(phandle, "clock-frequency", &iclk->clk.fixed.rate) != 0)

sys/arch/arm/nxp/imx6_clk.c

1224

iclk->clk.fixed.rate = 0;

sys/arch/arm/nxp/imx6_ocotp.c

53

struct clk *sc_clk;

sys/arch/arm/nxp/imx6_spi.c

48

struct clk *sc_clk;

sys/arch/arm/nxp/imx6_usbphy.c

52

struct clk *sc_clk;

sys/arch/arm/nxp/imx6sx_clk.c

1282

static struct clk *

sys/arch/arm/nxp/imx6sx_clk.c

1294

static struct clk *imx6sx_clk_decode(device_t, int, const void *, size_t);

sys/arch/arm/nxp/imx6sx_clk.c

1300

static struct clk *

sys/arch/arm/nxp/imx6sx_clk.c

1303

struct clk *clk;

sys/arch/arm/nxp/imx6sx_clk.c

1312

clk = imx6sx_get_clock_by_id(sc, clock_id);

sys/arch/arm/nxp/imx6sx_clk.c

1313

if (clk)

sys/arch/arm/nxp/imx6sx_clk.c

1314

return clk;

sys/arch/arm/nxp/imx6sx_clk.c

1336

if (of_getprop_uint32(phandle, "clock-frequency", &iclk->clk.fixed.rate) != 0)

sys/arch/arm/nxp/imx6sx_clk.c

1337

iclk->clk.fixed.rate = 0;

sys/arch/arm/nxp/imx_ahcisata.c

67

struct clk *sc_clk_sata;

sys/arch/arm/nxp/imx_ahcisata.c

68

struct clk *sc_clk_sata_ref;

sys/arch/arm/nxp/imx_ahcisata.c

69

struct clk *sc_clk_ahb;

sys/arch/arm/nxp/imx_ccm.c

105

imx_ccm_clock_set_rate(void *priv, struct clk *clkp, u_int rate)

sys/arch/arm/nxp/imx_ccm.c

108

struct imx_ccm_clk *clk = (struct imx_ccm_clk *)clkp;

sys/arch/arm/nxp/imx_ccm.c

109

struct clk *clkp_parent;

sys/arch/arm/nxp/imx_ccm.c

114

aprint_error("%s: no parent for %s\n", __func__, clk->base.name);

sys/arch/arm/nxp/imx_ccm.c

120

if (clk->set_rate)

sys/arch/arm/nxp/imx_ccm.c

121

return clk->set_rate(sc, clk, rate);

sys/arch/arm/nxp/imx_ccm.c

127

imx_ccm_clock_round_rate(void *priv, struct clk *clkp, u_int rate)

sys/arch/arm/nxp/imx_ccm.c

130

struct imx_ccm_clk *clk = (struct imx_ccm_clk *)clkp;

sys/arch/arm/nxp/imx_ccm.c

131

struct clk *clkp_parent;

sys/arch/arm/nxp/imx_ccm.c

136

aprint_error("%s: no parent for %s\n", __func__, clk->base.name);

sys/arch/arm/nxp/imx_ccm.c

142

if (clk->round_rate)

sys/arch/arm/nxp/imx_ccm.c

143

return clk->round_rate(sc, clk, rate);

sys/arch/arm/nxp/imx_ccm.c

149

imx_ccm_clock_enable(void *priv, struct clk *clkp)

sys/arch/arm/nxp/imx_ccm.c

152

struct imx_ccm_clk *clk = (struct imx_ccm_clk *)clkp;

sys/arch/arm/nxp/imx_ccm.c

153

struct clk *clkp_parent;

sys/arch/arm/nxp/imx_ccm.c

163

if (clk->enable)

sys/arch/arm/nxp/imx_ccm.c

164

error = clk->enable(sc, clk, 1);

sys/arch/arm/nxp/imx_ccm.c

170

imx_ccm_clock_disable(void *priv, struct clk *clkp)

sys/arch/arm/nxp/imx_ccm.c

173

struct imx_ccm_clk *clk = (struct imx_ccm_clk *)clkp;

sys/arch/arm/nxp/imx_ccm.c

176

if (clk->enable)

sys/arch/arm/nxp/imx_ccm.c

177

error = clk->enable(sc, clk, 0);

sys/arch/arm/nxp/imx_ccm.c

183

imx_ccm_clock_set_parent(void *priv, struct clk *clkp,

sys/arch/arm/nxp/imx_ccm.c

184

struct clk *clkp_parent)

sys/arch/arm/nxp/imx_ccm.c

187

struct imx_ccm_clk *clk = (struct imx_ccm_clk *)clkp;

sys/arch/arm/nxp/imx_ccm.c

189

if (clk->set_parent == NULL)

sys/arch/arm/nxp/imx_ccm.c

192

return clk->set_parent(sc, clk, clkp_parent->name);

sys/arch/arm/nxp/imx_ccm.c

195

static struct clk *

sys/arch/arm/nxp/imx_ccm.c

196

imx_ccm_clock_get_parent(void *priv, struct clk *clkp)

sys/arch/arm/nxp/imx_ccm.c

199

struct imx_ccm_clk *clk = (struct imx_ccm_clk *)clkp;

sys/arch/arm/nxp/imx_ccm.c

203

if (clk->get_parent == NULL)

sys/arch/arm/nxp/imx_ccm.c

206

parent = clk->get_parent(sc, clk);

sys/arch/arm/nxp/imx_ccm.c

276

struct imx_ccm_clk *clk;

sys/arch/arm/nxp/imx_ccm.c

277

struct clk *clkp_parent;

sys/arch/arm/nxp/imx_ccm.c

282

clk = &sc->sc_clks[i];

sys/arch/arm/nxp/imx_ccm.c

283

if (clk->type == IMX_CCM_UNKNOWN)

sys/arch/arm/nxp/imx_ccm.c

286

clkp_parent = clk_get_parent(&clk->base);

sys/arch/arm/nxp/imx_ccm.c

288

switch (clk->type) {

sys/arch/arm/nxp/imx_ccm.c

302

clk->id,

sys/arch/arm/nxp/imx_ccm.c

303

clk->base.name,

sys/arch/arm/nxp/imx_ccm.c

307

aprint_debug("%10d Hz\n", clk_get_rate(&clk->base));

sys/arch/arm/nxp/imx_ccm.c

43

static struct clk *

sys/arch/arm/nxp/imx_ccm.c

47

struct imx_ccm_clk *clk;

sys/arch/arm/nxp/imx_ccm.c

55

clk = &sc->sc_clks[i];

sys/arch/arm/nxp/imx_ccm.c

56

if (clk->id == clock_id)

sys/arch/arm/nxp/imx_ccm.c

57

return &clk->base;

sys/arch/arm/nxp/imx_ccm.c

67

static struct clk *

sys/arch/arm/nxp/imx_ccm.c

71

struct imx_ccm_clk *clk;

sys/arch/arm/nxp/imx_ccm.c

73

clk = imx_ccm_clock_find(sc, name);

sys/arch/arm/nxp/imx_ccm.c

74

if (clk == NULL)

sys/arch/arm/nxp/imx_ccm.c

77

return &clk->base;

sys/arch/arm/nxp/imx_ccm.c

81

imx_ccm_clock_put(void *priv, struct clk *clk)

sys/arch/arm/nxp/imx_ccm.c

86

imx_ccm_clock_get_rate(void *priv, struct clk *clkp)

sys/arch/arm/nxp/imx_ccm.c

89

struct imx_ccm_clk *clk = (struct imx_ccm_clk *)clkp;

sys/arch/arm/nxp/imx_ccm.c

90

struct clk *clkp_parent;

sys/arch/arm/nxp/imx_ccm.c

92

if (clk->get_rate)

sys/arch/arm/nxp/imx_ccm.c

93

return clk->get_rate(sc, clk);

sys/arch/arm/nxp/imx_ccm.c

97

aprint_debug("%s: no parent for %s\n", __func__, clk->base.name);

sys/arch/arm/nxp/imx_ccm.h

291

struct clk base;

sys/arch/arm/nxp/imx_ccm_composite.c

101

KASSERT(clk->type == IMX_CCM_COMPOSITE);

sys/arch/arm/nxp/imx_ccm_composite.c

104

clk_parent = clk_get_parent(&clk->base);

sys/arch/arm/nxp/imx_ccm_composite.c

114

val = CCM_READ(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT);

sys/arch/arm/nxp/imx_ccm_composite.c

154

val = CCM_READ(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT);

sys/arch/arm/nxp/imx_ccm_composite.c

159

CCM_WRITE(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT, val);

sys/arch/arm/nxp/imx_ccm_composite.c

166

struct imx_ccm_clk *clk)

sys/arch/arm/nxp/imx_ccm_composite.c

168

struct imx_ccm_composite *composite = &clk->u.composite;

sys/arch/arm/nxp/imx_ccm_composite.c

170

KASSERT(clk->type == IMX_CCM_COMPOSITE);

sys/arch/arm/nxp/imx_ccm_composite.c

172

const uint32_t val = CCM_READ(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT);

sys/arch/arm/nxp/imx_ccm_composite.c

183

struct imx_ccm_clk *clk, const char *parent)

sys/arch/arm/nxp/imx_ccm_composite.c

185

struct imx_ccm_composite *composite = &clk->u.composite;

sys/arch/arm/nxp/imx_ccm_composite.c

188

KASSERT(clk->type == IMX_CCM_COMPOSITE);

sys/arch/arm/nxp/imx_ccm_composite.c

192

val = CCM_READ(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT);

sys/arch/arm/nxp/imx_ccm_composite.c

195

CCM_WRITE(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT, val);

sys/arch/arm/nxp/imx_ccm_composite.c

48

imx_ccm_composite_enable(struct imx_ccm_softc *sc, struct imx_ccm_clk *clk,

sys/arch/arm/nxp/imx_ccm_composite.c

51

struct imx_ccm_composite *composite = &clk->u.composite;

sys/arch/arm/nxp/imx_ccm_composite.c

54

KASSERT(clk->type == IMX_CCM_COMPOSITE);

sys/arch/arm/nxp/imx_ccm_composite.c

56

val = CCM_READ(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT);

sys/arch/arm/nxp/imx_ccm_composite.c

61

CCM_WRITE(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT, val);

sys/arch/arm/nxp/imx_ccm_composite.c

68

struct imx_ccm_clk *clk)

sys/arch/arm/nxp/imx_ccm_composite.c

70

struct imx_ccm_composite *composite = &clk->u.composite;

sys/arch/arm/nxp/imx_ccm_composite.c

71

struct clk *clkp, *clkp_parent;

sys/arch/arm/nxp/imx_ccm_composite.c

73

KASSERT(clk->type == IMX_CCM_COMPOSITE);

sys/arch/arm/nxp/imx_ccm_composite.c

75

clkp = &clk->base;

sys/arch/arm/nxp/imx_ccm_composite.c

84

const uint32_t val = CCM_READ(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT);

sys/arch/arm/nxp/imx_ccm_composite.c

93

struct imx_ccm_clk *clk, u_int rate)

sys/arch/arm/nxp/imx_ccm_composite.c

95

struct imx_ccm_composite *composite = &clk->u.composite;

sys/arch/arm/nxp/imx_ccm_composite.c

98

struct clk *clk_parent;

sys/arch/arm/nxp/imx_ccm_div.c

107

val = CCM_READ(sc, clk->regidx, div->reg);

sys/arch/arm/nxp/imx_ccm_div.c

110

CCM_WRITE(sc, clk->regidx, div->reg, val);

sys/arch/arm/nxp/imx_ccm_div.c

117

struct imx_ccm_clk *clk)

sys/arch/arm/nxp/imx_ccm_div.c

119

struct imx_ccm_div *div = &clk->u.div;

sys/arch/arm/nxp/imx_ccm_div.c

121

KASSERT(clk->type == IMX_CCM_DIV);

sys/arch/arm/nxp/imx_ccm_div.c

43

struct imx_ccm_clk *clk)

sys/arch/arm/nxp/imx_ccm_div.c

45

struct imx_ccm_div *div = &clk->u.div;

sys/arch/arm/nxp/imx_ccm_div.c

46

struct clk *clkp, *clkp_parent;

sys/arch/arm/nxp/imx_ccm_div.c

48

KASSERT(clk->type == IMX_CCM_DIV);

sys/arch/arm/nxp/imx_ccm_div.c

50

clkp = &clk->base;

sys/arch/arm/nxp/imx_ccm_div.c

59

const uint32_t val = CCM_READ(sc, clk->regidx, div->reg);

sys/arch/arm/nxp/imx_ccm_div.c

67

struct imx_ccm_clk *clk, u_int rate)

sys/arch/arm/nxp/imx_ccm_div.c

69

struct imx_ccm_div *div = &clk->u.div;

sys/arch/arm/nxp/imx_ccm_div.c

70

struct clk *clkp, *clkp_parent;

sys/arch/arm/nxp/imx_ccm_div.c

75

KASSERT(clk->type == IMX_CCM_DIV);

sys/arch/arm/nxp/imx_ccm_div.c

77

clkp = &clk->base;

sys/arch/arm/nxp/imx_ccm_extclk.c

42

imx_ccm_extclk_enable(struct imx_ccm_softc *sc, struct imx_ccm_clk *clk,

sys/arch/arm/nxp/imx_ccm_extclk.c

45

struct clk *extclk;

sys/arch/arm/nxp/imx_ccm_extclk.c

47

KASSERT(clk->type == IMX_CCM_EXTCLK);

sys/arch/arm/nxp/imx_ccm_extclk.c

49

if ((extclk = fdtbus_clock_byname(clk->u.extclk)) == NULL)

sys/arch/arm/nxp/imx_ccm_extclk.c

57

struct imx_ccm_clk *clk)

sys/arch/arm/nxp/imx_ccm_extclk.c

59

struct clk *extclk;

sys/arch/arm/nxp/imx_ccm_extclk.c

61

KASSERT(clk->type == IMX_CCM_EXTCLK);

sys/arch/arm/nxp/imx_ccm_extclk.c

63

if ((extclk = fdtbus_clock_byname(clk->u.extclk)) == NULL)

sys/arch/arm/nxp/imx_ccm_extclk.c

71

struct imx_ccm_clk *clk, u_int rate)

sys/arch/arm/nxp/imx_ccm_extclk.c

73

struct clk *extclk;

sys/arch/arm/nxp/imx_ccm_extclk.c

75

KASSERT(clk->type == IMX_CCM_EXTCLK);

sys/arch/arm/nxp/imx_ccm_extclk.c

77

if ((extclk = fdtbus_clock_byname(clk->u.extclk)) == NULL)

sys/arch/arm/nxp/imx_ccm_extclk.c

85

struct imx_ccm_clk *clk)

sys/arch/arm/nxp/imx_ccm_extclk.c

87

struct clk *extclk, *clkp;

sys/arch/arm/nxp/imx_ccm_extclk.c

89

KASSERT(clk->type == IMX_CCM_EXTCLK);

sys/arch/arm/nxp/imx_ccm_extclk.c

91

if ((extclk = fdtbus_clock_byname(clk->u.extclk)) == NULL)

sys/arch/arm/nxp/imx_ccm_fixed.c

41

struct imx_ccm_clk *clk)

sys/arch/arm/nxp/imx_ccm_fixed.c

43

struct imx_ccm_fixed *fixed = &clk->u.fixed;

sys/arch/arm/nxp/imx_ccm_fixed.c

45

KASSERT(clk->type == IMX_CCM_FIXED);

sys/arch/arm/nxp/imx_ccm_fixed_factor.c

100

KASSERT(clk->type == IMX_CCM_FIXED_FACTOR);

sys/arch/arm/nxp/imx_ccm_fixed_factor.c

40

imx_ccm_fixed_factor_get_parent_rate(struct clk *clkp)

sys/arch/arm/nxp/imx_ccm_fixed_factor.c

42

struct clk *clkp_parent;

sys/arch/arm/nxp/imx_ccm_fixed_factor.c

53

struct imx_ccm_clk *clk)

sys/arch/arm/nxp/imx_ccm_fixed_factor.c

55

struct imx_ccm_fixed_factor *fixed_factor = &clk->u.fixed_factor;

sys/arch/arm/nxp/imx_ccm_fixed_factor.c

56

struct clk *clkp = &clk->base;

sys/arch/arm/nxp/imx_ccm_fixed_factor.c

58

KASSERT(clk->type == IMX_CCM_FIXED_FACTOR);

sys/arch/arm/nxp/imx_ccm_fixed_factor.c

68

imx_ccm_fixed_factor_set_parent_rate(struct clk *clkp, u_int rate)

sys/arch/arm/nxp/imx_ccm_fixed_factor.c

70

struct clk *clkp_parent;

sys/arch/arm/nxp/imx_ccm_fixed_factor.c

81

struct imx_ccm_clk *clk, u_int rate)

sys/arch/arm/nxp/imx_ccm_fixed_factor.c

83

struct imx_ccm_fixed_factor *fixed_factor = &clk->u.fixed_factor;

sys/arch/arm/nxp/imx_ccm_fixed_factor.c

84

struct clk *clkp = &clk->base;

sys/arch/arm/nxp/imx_ccm_fixed_factor.c

86

KASSERT(clk->type == IMX_CCM_FIXED_FACTOR);

sys/arch/arm/nxp/imx_ccm_fixed_factor.c

96

struct imx_ccm_clk *clk)

sys/arch/arm/nxp/imx_ccm_fixed_factor.c

98

struct imx_ccm_fixed_factor *fixed_factor = &clk->u.fixed_factor;

sys/arch/arm/nxp/imx_ccm_gate.c

40

imx_ccm_gate_enable(struct imx_ccm_softc *sc, struct imx_ccm_clk *clk,

sys/arch/arm/nxp/imx_ccm_gate.c

43

struct imx_ccm_gate *gate = &clk->u.gate;

sys/arch/arm/nxp/imx_ccm_gate.c

46

KASSERT(clk->type == IMX_CCM_GATE);

sys/arch/arm/nxp/imx_ccm_gate.c

48

val = CCM_READ(sc, clk->regidx, gate->reg);

sys/arch/arm/nxp/imx_ccm_gate.c

53

CCM_WRITE(sc, clk->regidx, gate->reg, val);

sys/arch/arm/nxp/imx_ccm_gate.c

60

struct imx_ccm_clk *clk)

sys/arch/arm/nxp/imx_ccm_gate.c

62

struct imx_ccm_gate *gate = &clk->u.gate;

sys/arch/arm/nxp/imx_ccm_gate.c

64

KASSERT(clk->type == IMX_CCM_GATE);

sys/arch/arm/nxp/imx_ccm_mux.c

43

struct imx_ccm_clk *clk)

sys/arch/arm/nxp/imx_ccm_mux.c

45

struct imx_ccm_mux *mux = &clk->u.mux;

sys/arch/arm/nxp/imx_ccm_mux.c

47

KASSERT(clk->type == IMX_CCM_MUX);

sys/arch/arm/nxp/imx_ccm_mux.c

49

const uint32_t val = CCM_READ(sc, clk->regidx, mux->reg);

sys/arch/arm/nxp/imx_ccm_mux.c

60

struct imx_ccm_clk *clk, const char *parent)

sys/arch/arm/nxp/imx_ccm_mux.c

62

struct imx_ccm_mux *mux = &clk->u.mux;

sys/arch/arm/nxp/imx_ccm_mux.c

65

KASSERT(clk->type == IMX_CCM_MUX);

sys/arch/arm/nxp/imx_ccm_mux.c

69

val = CCM_READ(sc, clk->regidx, mux->reg);

sys/arch/arm/nxp/imx_ccm_mux.c

72

CCM_WRITE(sc, clk->regidx, mux->reg, val);

sys/arch/arm/nxp/imx_ccm_pll.c

107

struct imx_ccm_clk *clk)

sys/arch/arm/nxp/imx_ccm_pll.c

109

struct imx_ccm_pll *pll = &clk->u.pll;

sys/arch/arm/nxp/imx_ccm_pll.c

111

KASSERT(clk->type == IMX_CCM_PLL);

sys/arch/arm/nxp/imx_ccm_pll.c

45

imx_ccm_pll_enable(struct imx_ccm_softc *sc, struct imx_ccm_clk *clk,

sys/arch/arm/nxp/imx_ccm_pll.c

48

struct imx_ccm_pll *pll = &clk->u.pll;

sys/arch/arm/nxp/imx_ccm_pll.c

51

KASSERT(clk->type == IMX_CCM_PLL);

sys/arch/arm/nxp/imx_ccm_pll.c

58

val = CCM_READ(sc, clk->regidx, pll->reg);

sys/arch/arm/nxp/imx_ccm_pll.c

63

CCM_WRITE(sc, clk->regidx, pll->reg, val);

sys/arch/arm/nxp/imx_ccm_pll.c

70

struct imx_ccm_clk *clk)

sys/arch/arm/nxp/imx_ccm_pll.c

72

struct imx_ccm_pll *pll= &clk->u.pll;

sys/arch/arm/nxp/imx_ccm_pll.c

73

struct clk *clkp, *clkp_parent;

sys/arch/arm/nxp/imx_ccm_pll.c

75

KASSERT(clk->type == IMX_CCM_PLL);

sys/arch/arm/nxp/imx_ccm_pll.c

77

clkp = &clk->base;

sys/arch/arm/nxp/imx_ccm_pll.c

91

const uint32_t val = CCM_READ(sc, clk->regidx, pll->reg);

sys/arch/arm/nxp/imx_com.c

73

struct clk *per;

sys/arch/arm/nxp/imx_sdhc.c

64

struct clk *sc_clk_per;

sys/arch/arm/rockchip/rk3399_cru.c

1108

const char *clk;

sys/arch/arm/rockchip/rk3399_cru.c

1111

{ .clk = "clk_i2s0_mux", .parent = "clk_i2s0_frac" },

sys/arch/arm/rockchip/rk3399_cru.c

1112

{ .clk = "clk_i2s1_mux", .parent = "clk_i2s1_frac" },

sys/arch/arm/rockchip/rk3399_cru.c

1113

{ .clk = "clk_i2s2_mux", .parent = "clk_i2s2_frac" },

sys/arch/arm/rockchip/rk3399_cru.c

1114

{ .clk = "dclk_vop0_div", .parent = "gpll" },

sys/arch/arm/rockchip/rk3399_cru.c

1115

{ .clk = "dclk_vop1_div", .parent = "gpll" },

sys/arch/arm/rockchip/rk3399_cru.c

1116

{ .clk = "dclk_vop0", .parent = "dclk_vop0_frac" },

sys/arch/arm/rockchip/rk3399_cru.c

1117

{ .clk = "dclk_vop1", .parent = "dclk_vop1_frac" },

sys/arch/arm/rockchip/rk3399_cru.c

1123

struct rk_cru_clk *clk, *pclk;

sys/arch/arm/rockchip/rk3399_cru.c

1131

clk = rk_cru_clock_find(sc, "armclkb");

sys/arch/arm/rockchip/rk3399_cru.c

1132

clk_set_rate(&clk->base, clk_get_rate(&clk->base));

sys/arch/arm/rockchip/rk3399_cru.c

1147

clk = rk_cru_clock_find(sc, param->clk);

sys/arch/arm/rockchip/rk3399_cru.c

1148

KASSERTMSG(clk != NULL, "couldn't find clock %s", param->clk);

sys/arch/arm/rockchip/rk3399_cru.c

1152

error = clk_set_parent(&clk->base, &pclk->base);

sys/arch/arm/rockchip/rk3399_cru.c

1155

param->clk, param->parent, error);

sys/arch/arm/rockchip/rk3399_cru.c

234

struct rk_cru_clk *clk)

sys/arch/arm/rockchip/rk3399_cru.c

236

struct rk_cru_pll *pll = &clk->u.pll;

sys/arch/arm/rockchip/rk3399_cru.c

237

struct clk *clkp, *clkp_parent;

sys/arch/arm/rockchip/rk3399_cru.c

240

KASSERT(clk->type == RK_CRU_PLL);

sys/arch/arm/rockchip/rk3399_cru.c

242

clkp = &clk->base;

sys/arch/arm/rockchip/rk3399_cru.c

277

struct rk_cru_clk *clk, u_int rate)

sys/arch/arm/rockchip/rk3399_cru.c

279

struct rk_cru_pll *pll = &clk->u.pll;

sys/arch/arm/rockchip/rk3399_cru.c

284

KASSERT(clk->type == RK_CRU_PLL);

sys/arch/arm/rockchip/rk3399_cru.c

331

clk->base.name);

sys/arch/arm/rockchip/rk3399_pcie.c

174

struct clk * clk = fdtbus_clock_get_index(phandle, i);

sys/arch/arm/rockchip/rk3399_pcie.c

175

if (clk == NULL)

sys/arch/arm/rockchip/rk3399_pcie.c

177

if (clk_enable(clk) != 0)

sys/arch/arm/rockchip/rk3399_pcie_phy.c

68

struct clk * clk = fdtbus_clock_get(phandle, name);

sys/arch/arm/rockchip/rk3399_pcie_phy.c

69

if (clk == NULL)

sys/arch/arm/rockchip/rk3399_pcie_phy.c

71

if (clk_enable(clk) != 0)

sys/arch/arm/rockchip/rk3399_pmucru.c

162

struct rk_cru_clk *clk)

sys/arch/arm/rockchip/rk3399_pmucru.c

164

struct rk_cru_pll *pll = &clk->u.pll;

sys/arch/arm/rockchip/rk3399_pmucru.c

165

struct clk *clkp, *clkp_parent;

sys/arch/arm/rockchip/rk3399_pmucru.c

168

KASSERT(clk->type == RK_CRU_PLL);

sys/arch/arm/rockchip/rk3399_pmucru.c

170

clkp = &clk->base;

sys/arch/arm/rockchip/rk3399_pmucru.c

205

struct rk_cru_clk *clk, u_int rate)

sys/arch/arm/rockchip/rk3399_pmucru.c

207

struct rk_cru_pll *pll = &clk->u.pll;

sys/arch/arm/rockchip/rk3399_pmucru.c

212

KASSERT(clk->type == RK_CRU_PLL);

sys/arch/arm/rockchip/rk3399_pmucru.c

259

clk->base.name);

sys/arch/arm/rockchip/rk_cru.c

105

clk = &sc->sc_clks[i];

sys/arch/arm/rockchip/rk_cru.c

106

if (clk->id == clock_id)

sys/arch/arm/rockchip/rk_cru.c

107

return &clk->base;

sys/arch/arm/rockchip/rk_cru.c

117

static struct clk *

sys/arch/arm/rockchip/rk_cru.c

121

struct rk_cru_clk *clk;

sys/arch/arm/rockchip/rk_cru.c

123

clk = rk_cru_clock_find(sc, name);

sys/arch/arm/rockchip/rk_cru.c

124

if (clk == NULL)

sys/arch/arm/rockchip/rk_cru.c

127

return &clk->base;

sys/arch/arm/rockchip/rk_cru.c

131

rk_cru_clock_put(void *priv, struct clk *clk)

sys/arch/arm/rockchip/rk_cru.c

136

rk_cru_clock_get_rate(void *priv, struct clk *clkp)

sys/arch/arm/rockchip/rk_cru.c

139

struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp;

sys/arch/arm/rockchip/rk_cru.c

140

struct clk *clkp_parent;

sys/arch/arm/rockchip/rk_cru.c

142

if (clk->get_rate)

sys/arch/arm/rockchip/rk_cru.c

143

return clk->get_rate(sc, clk);

sys/arch/arm/rockchip/rk_cru.c

148

clk->base.name);

sys/arch/arm/rockchip/rk_cru.c

156

rk_cru_clock_set_rate(void *priv, struct clk *clkp, u_int rate)

sys/arch/arm/rockchip/rk_cru.c

159

struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp;

sys/arch/arm/rockchip/rk_cru.c

160

struct clk *clkp_parent;

sys/arch/arm/rockchip/rk_cru.c

166

clk->base.name);

sys/arch/arm/rockchip/rk_cru.c

172

if (clk->set_rate)

sys/arch/arm/rockchip/rk_cru.c

173

return clk->set_rate(sc, clk, rate);

sys/arch/arm/rockchip/rk_cru.c

179

rk_cru_clock_round_rate(void *priv, struct clk *clkp, u_int rate)

sys/arch/arm/rockchip/rk_cru.c

182

struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp;

sys/arch/arm/rockchip/rk_cru.c

183

struct clk *clkp_parent;

sys/arch/arm/rockchip/rk_cru.c

189

clk->base.name);

sys/arch/arm/rockchip/rk_cru.c

195

if (clk->round_rate)

sys/arch/arm/rockchip/rk_cru.c

196

return clk->round_rate(sc, clk, rate);

sys/arch/arm/rockchip/rk_cru.c

202

rk_cru_clock_enable(void *priv, struct clk *clkp)

sys/arch/arm/rockchip/rk_cru.c

205

struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp;

sys/arch/arm/rockchip/rk_cru.c

206

struct clk *clkp_parent;

sys/arch/arm/rockchip/rk_cru.c

216

if (clk->enable)

sys/arch/arm/rockchip/rk_cru.c

217

error = clk->enable(sc, clk, 1);

sys/arch/arm/rockchip/rk_cru.c

223

rk_cru_clock_disable(void *priv, struct clk *clkp)

sys/arch/arm/rockchip/rk_cru.c

226

struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp;

sys/arch/arm/rockchip/rk_cru.c

229

if (clk->enable)

sys/arch/arm/rockchip/rk_cru.c

230

error = clk->enable(sc, clk, 0);

sys/arch/arm/rockchip/rk_cru.c

236

rk_cru_clock_set_parent(void *priv, struct clk *clkp, struct clk *clkp_parent)

sys/arch/arm/rockchip/rk_cru.c

239

struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp;

sys/arch/arm/rockchip/rk_cru.c

241

if (clk->set_parent == NULL)

sys/arch/arm/rockchip/rk_cru.c

244

return clk->set_parent(sc, clk, clkp_parent->name);

sys/arch/arm/rockchip/rk_cru.c

247

static struct clk *

sys/arch/arm/rockchip/rk_cru.c

248

rk_cru_clock_get_parent(void *priv, struct clk *clkp)

sys/arch/arm/rockchip/rk_cru.c

251

struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp;

sys/arch/arm/rockchip/rk_cru.c

255

if (clk->get_parent == NULL)

sys/arch/arm/rockchip/rk_cru.c

258

parent = clk->get_parent(sc, clk);

sys/arch/arm/rockchip/rk_cru.c

340

struct rk_cru_clk *clk;

sys/arch/arm/rockchip/rk_cru.c

341

struct clk *clkp_parent;

sys/arch/arm/rockchip/rk_cru.c

346

clk = &sc->sc_clks[i];

sys/arch/arm/rockchip/rk_cru.c

347

if (clk->type == RK_CRU_UNKNOWN)

sys/arch/arm/rockchip/rk_cru.c

350

clkp_parent = clk_get_parent(&clk->base);

sys/arch/arm/rockchip/rk_cru.c

352

switch (clk->type) {

sys/arch/arm/rockchip/rk_cru.c

363

clk->id,

sys/arch/arm/rockchip/rk_cru.c

364

clk->base.name,

sys/arch/arm/rockchip/rk_cru.c

368

aprint_debug("%10d Hz\n", clk_get_rate(&clk->base));

sys/arch/arm/rockchip/rk_cru.c

93

static struct clk *

sys/arch/arm/rockchip/rk_cru.c

97

struct rk_cru_clk *clk;

sys/arch/arm/rockchip/rk_cru.h

415

struct clk base;

sys/arch/arm/rockchip/rk_cru_arm.c

113

rk_cru_arm_set_parent(sc, clk, arm->parents[arm->mux_main]);

sys/arch/arm/rockchip/rk_cru_arm.c

119

struct rk_cru_clk *clk, u_int rate)

sys/arch/arm/rockchip/rk_cru_arm.c

121

struct rk_cru_arm *arm = &clk->u.arm;

sys/arch/arm/rockchip/rk_cru_arm.c

127

KASSERT(clk->type == RK_CRU_ARM);

sys/arch/arm/rockchip/rk_cru_arm.c

149

error = rk_cru_arm_set_parent(sc, clk, arm->parents[arm->mux_alt]);

sys/arch/arm/rockchip/rk_cru_arm.c

179

rk_cru_arm_set_parent(sc, clk, arm->parents[arm->mux_main]);

sys/arch/arm/rockchip/rk_cru_arm.c

186

struct rk_cru_clk *clk, u_int rate)

sys/arch/arm/rockchip/rk_cru_arm.c

188

struct rk_cru_arm *arm = &clk->u.arm;

sys/arch/arm/rockchip/rk_cru_arm.c

191

return rk_cru_arm_set_rate_rates(sc, clk, rate);

sys/arch/arm/rockchip/rk_cru_arm.c

193

return rk_cru_arm_set_rate_cpurates(sc, clk, rate);

sys/arch/arm/rockchip/rk_cru_arm.c

200

struct rk_cru_clk *clk)

sys/arch/arm/rockchip/rk_cru_arm.c

202

struct rk_cru_arm *arm = &clk->u.arm;

sys/arch/arm/rockchip/rk_cru_arm.c

204

KASSERT(clk->type == RK_CRU_ARM);

sys/arch/arm/rockchip/rk_cru_arm.c

214

struct rk_cru_clk *clk, const char *parent)

sys/arch/arm/rockchip/rk_cru_arm.c

216

struct rk_cru_arm *arm = &clk->u.arm;

sys/arch/arm/rockchip/rk_cru_arm.c

218

KASSERT(clk->type == RK_CRU_ARM);

sys/arch/arm/rockchip/rk_cru_arm.c

41

struct rk_cru_clk *clk)

sys/arch/arm/rockchip/rk_cru_arm.c

43

struct rk_cru_arm *arm = &clk->u.arm;

sys/arch/arm/rockchip/rk_cru_arm.c

44

struct clk *clkp, *clkp_parent;

sys/arch/arm/rockchip/rk_cru_arm.c

46

KASSERT(clk->type == RK_CRU_ARM);

sys/arch/arm/rockchip/rk_cru_arm.c

48

clkp = &clk->base;

sys/arch/arm/rockchip/rk_cru_arm.c

65

struct rk_cru_clk *clk, u_int rate)

sys/arch/arm/rockchip/rk_cru_arm.c

67

struct rk_cru_arm *arm = &clk->u.arm;

sys/arch/arm/rockchip/rk_cru_arm.c

72

KASSERT(clk->type == RK_CRU_ARM);

sys/arch/arm/rockchip/rk_cru_arm.c

92

error = rk_cru_arm_set_parent(sc, clk, arm->parents[arm->mux_alt]);

sys/arch/arm/rockchip/rk_cru_composite.c

117

struct rk_cru_clk *clk, u_int rate)

sys/arch/arm/rockchip/rk_cru_composite.c

119

struct rk_cru_composite *composite = &clk->u.composite;

sys/arch/arm/rockchip/rk_cru_composite.c

120

struct clk *clk_parent;

sys/arch/arm/rockchip/rk_cru_composite.c

122

clk_parent = clk_get_parent(&clk->base);

sys/arch/arm/rockchip/rk_cru_composite.c

140

struct rk_cru_clk *clk, u_int rate)

sys/arch/arm/rockchip/rk_cru_composite.c

142

struct rk_cru_composite *composite = &clk->u.composite;

sys/arch/arm/rockchip/rk_cru_composite.c

145

struct clk *clk_parent;

sys/arch/arm/rockchip/rk_cru_composite.c

147

KASSERT(clk->type == RK_CRU_COMPOSITE);

sys/arch/arm/rockchip/rk_cru_composite.c

150

clk_parent = clk_get_parent(&clk->base);

sys/arch/arm/rockchip/rk_cru_composite.c

157

return rk_cru_composite_set_rate_frac(sc, clk, rate);

sys/arch/arm/rockchip/rk_cru_composite.c

218

struct rk_cru_clk *clk)

sys/arch/arm/rockchip/rk_cru_composite.c

220

struct rk_cru_composite *composite = &clk->u.composite;

sys/arch/arm/rockchip/rk_cru_composite.c

224

KASSERT(clk->type == RK_CRU_COMPOSITE);

sys/arch/arm/rockchip/rk_cru_composite.c

238

struct rk_cru_clk *clk, const char *parent)

sys/arch/arm/rockchip/rk_cru_composite.c

240

struct rk_cru_composite *composite = &clk->u.composite;

sys/arch/arm/rockchip/rk_cru_composite.c

242

KASSERT(clk->type == RK_CRU_COMPOSITE);

sys/arch/arm/rockchip/rk_cru_composite.c

42

rk_cru_composite_enable(struct rk_cru_softc *sc, struct rk_cru_clk *clk,

sys/arch/arm/rockchip/rk_cru_composite.c

45

struct rk_cru_composite *composite = &clk->u.composite;

sys/arch/arm/rockchip/rk_cru_composite.c

47

KASSERT(clk->type == RK_CRU_COMPOSITE);

sys/arch/arm/rockchip/rk_cru_composite.c

62

struct rk_cru_clk *clk)

sys/arch/arm/rockchip/rk_cru_composite.c

64

struct rk_cru_composite *composite = &clk->u.composite;

sys/arch/arm/rockchip/rk_cru_composite.c

65

struct clk *clkp, *clkp_parent;

sys/arch/arm/rockchip/rk_cru_composite.c

67

KASSERT(clk->type == RK_CRU_COMPOSITE);

sys/arch/arm/rockchip/rk_cru_composite.c

69

clkp = &clk->base;

sys/arch/arm/rockchip/rk_cru_gate.c

40

rk_cru_gate_enable(struct rk_cru_softc *sc, struct rk_cru_clk *clk,

sys/arch/arm/rockchip/rk_cru_gate.c

43

struct rk_cru_gate *gate = &clk->u.gate;

sys/arch/arm/rockchip/rk_cru_gate.c

45

KASSERT(clk->type == RK_CRU_GATE);

sys/arch/arm/rockchip/rk_cru_gate.c

57

struct rk_cru_clk *clk)

sys/arch/arm/rockchip/rk_cru_gate.c

59

struct rk_cru_gate *gate = &clk->u.gate;

sys/arch/arm/rockchip/rk_cru_gate.c

61

KASSERT(clk->type == RK_CRU_GATE);

sys/arch/arm/rockchip/rk_cru_mux.c

41

struct rk_cru_clk *clk)

sys/arch/arm/rockchip/rk_cru_mux.c

43

struct rk_cru_mux *mux = &clk->u.mux;

sys/arch/arm/rockchip/rk_cru_mux.c

47

KASSERT(clk->type == RK_CRU_MUX);

sys/arch/arm/rockchip/rk_cru_mux.c

65

struct rk_cru_clk *clk, const char *parent)

sys/arch/arm/rockchip/rk_cru_mux.c

67

struct rk_cru_mux *mux = &clk->u.mux;

sys/arch/arm/rockchip/rk_cru_mux.c

70

KASSERT(clk->type == RK_CRU_MUX);

sys/arch/arm/rockchip/rk_cru_pll.c

158

struct rk_cru_clk *clk, u_int rate)

sys/arch/arm/rockchip/rk_cru_pll.c

160

struct rk_cru_pll *pll = &clk->u.pll;

sys/arch/arm/rockchip/rk_cru_pll.c

165

KASSERT(clk->type == RK_CRU_PLL);

sys/arch/arm/rockchip/rk_cru_pll.c

226

"WARNING: %s failed to lock\n", clk->base.name);

sys/arch/arm/rockchip/rk_cru_pll.c

267

"WARNING: %s failed to lock\n", clk->base.name);

sys/arch/arm/rockchip/rk_cru_pll.c

275

struct rk_cru_clk *clk)

sys/arch/arm/rockchip/rk_cru_pll.c

277

struct rk_cru_pll *pll = &clk->u.pll;

sys/arch/arm/rockchip/rk_cru_pll.c

279

KASSERT(clk->type == RK_CRU_PLL);

sys/arch/arm/rockchip/rk_cru_pll.c

88

struct rk_cru_clk *clk)

sys/arch/arm/rockchip/rk_cru_pll.c

90

struct rk_cru_pll *pll = &clk->u.pll;

sys/arch/arm/rockchip/rk_cru_pll.c

91

struct clk *clkp, *clkp_parent;

sys/arch/arm/rockchip/rk_cru_pll.c

94

KASSERT(clk->type == RK_CRU_PLL);

sys/arch/arm/rockchip/rk_cru_pll.c

96

clkp = &clk->base;

sys/arch/arm/rockchip/rk_dwhdmi.c

85

struct clk *sc_clk_vpll;

sys/arch/arm/rockchip/rk_emmcphy.c

100

struct clk *sc_clk;

sys/arch/arm/rockchip/rk_eqos.c

341

struct clk *clk;

sys/arch/arm/rockchip/rk_eqos.c

343

for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++) {

sys/arch/arm/rockchip/rk_eqos.c

344

if (clk_enable(clk) != 0) {

sys/arch/arm/rockchip/rk_gmac.c

392

struct clk *clk;

sys/arch/arm/rockchip/rk_gmac.c

398

clk = fdtbus_clock_get(phandle, clknames[n]);

sys/arch/arm/rockchip/rk_gmac.c

399

if (clk == NULL) {

sys/arch/arm/rockchip/rk_gmac.c

403

error = clk_enable(clk);

sys/arch/arm/rockchip/rk_gpio.c

612

struct clk *clk;

sys/arch/arm/rockchip/rk_gpio.c

623

if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL || clk_enable(clk) != 0) {

sys/arch/arm/rockchip/rk_i2c.c

116

struct clk *sc_sclk;

sys/arch/arm/rockchip/rk_i2c.c

117

struct clk *sc_pclk;

sys/arch/arm/rockchip/rk_i2s.c

147

struct clk *sc_clk;

sys/arch/arm/rockchip/rk_i2s.c

442

const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK);

sys/arch/arm/rockchip/rk_i2s.c

493

switch (clk) {

sys/arch/arm/rockchip/rk_pwm.c

210

struct clk *clk;

sys/arch/arm/rockchip/rk_pwm.c

220

clk = fdtbus_clock_get_index(phandle, 0);

sys/arch/arm/rockchip/rk_pwm.c

221

if (clk == NULL) {

sys/arch/arm/rockchip/rk_pwm.c

227

sc->sc_clkfreq = clk_get_rate(clk);

sys/arch/arm/rockchip/rk_spi.c

203

struct clk *sclk, *pclk;

sys/arch/arm/rockchip/rk_tcphy.c

123

struct clk *sc_core_clk;

sys/arch/arm/rockchip/rk_tcphy.c

124

struct clk *sc_phy_ref_clk;

sys/arch/arm/rockchip/rk_tsadc.c

208

struct clk *sc_clock;

sys/arch/arm/rockchip/rk_tsadc.c

209

struct clk *sc_clockapb;

sys/arch/arm/rockchip/rk_usb.c

107

rk_usb_clk_put(void *priv, struct clk *clk)

sys/arch/arm/rockchip/rk_usb.c

112

rk_usb_clk_get_rate(void *priv, struct clk *clk)

sys/arch/arm/rockchip/rk_usb.c

118

rk_usb_clk_enable(void *priv, struct clk *clk)

sys/arch/arm/rockchip/rk_usb.c

148

rk_usb_clk_disable(void *priv, struct clk *clk)

sys/arch/arm/rockchip/rk_usb.c

185

static struct clk *

sys/arch/arm/rockchip/rk_usb.c

214

struct clk *clk;

sys/arch/arm/rockchip/rk_usb.c

223

clk = fdtbus_clock_get(phandle, "phyclk");

sys/arch/arm/rockchip/rk_usb.c

224

if (clk && clk_enable(clk) != 0) {

sys/arch/arm/rockchip/rk_usb.c

78

struct clk base;

sys/arch/arm/rockchip/rk_usb.c

95

static struct clk *

sys/arch/arm/rockchip/rk_vop.c

166

struct clk *sc_dclk;

sys/arch/arm/samsung/exynos5410_clock.c

1008

return (struct clk *)eclk_parent;

sys/arch/arm/samsung/exynos5410_clock.c

139

static struct clk *exynos5410_clock_get(void *, const char *);

sys/arch/arm/samsung/exynos5410_clock.c

140

static void exynos5410_clock_put(void *, struct clk *);

sys/arch/arm/samsung/exynos5410_clock.c

141

static u_int exynos5410_clock_get_rate(void *, struct clk *);

sys/arch/arm/samsung/exynos5410_clock.c

142

static int exynos5410_clock_set_rate(void *, struct clk *, u_int);

sys/arch/arm/samsung/exynos5410_clock.c

143

static int exynos5410_clock_enable(void *, struct clk *);

sys/arch/arm/samsung/exynos5410_clock.c

144

static int exynos5410_clock_disable(void *, struct clk *);

sys/arch/arm/samsung/exynos5410_clock.c

145

static int exynos5410_clock_set_parent(void *, struct clk *, struct clk *);

sys/arch/arm/samsung/exynos5410_clock.c

146

static struct clk *exynos5410_clock_get_parent(void *, struct clk *);

sys/arch/arm/samsung/exynos5410_clock.c

48

static struct clk *exynos5410_clock_decode(device_t, int, const void *, size_t);

sys/arch/arm/samsung/exynos5410_clock.c

513

struct clk * clk = fdtbus_clock_get_index(phandle, 0);

sys/arch/arm/samsung/exynos5410_clock.c

514

if (clk_get_rate(clk) == 24 * 1000 * 1000) {

sys/arch/arm/samsung/exynos5410_clock.c

577

struct clk *clk_parent;

sys/arch/arm/samsung/exynos5410_clock.c

609

static struct clk *

sys/arch/arm/samsung/exynos5410_clock.c

782

struct clk *clk_parent;

sys/arch/arm/samsung/exynos5410_clock.c

800

struct clk *clk_parent;

sys/arch/arm/samsung/exynos5410_clock.c

850

static struct clk *

sys/arch/arm/samsung/exynos5410_clock.c

865

exynos5410_clock_put(void *priv, struct clk *clk)

sys/arch/arm/samsung/exynos5410_clock.c

867

struct exynos_clk *eclk = (struct exynos_clk *)clk;

sys/arch/arm/samsung/exynos5410_clock.c

875

exynos5410_clock_get_rate(void *priv, struct clk *clk)

sys/arch/arm/samsung/exynos5410_clock.c

877

struct exynos_clk *eclk = (struct exynos_clk *)clk;

sys/arch/arm/samsung/exynos5410_clock.c

878

struct clk *clk_parent;

sys/arch/arm/samsung/exynos5410_clock.c

889

clk_parent = exynos5410_clock_get_parent(priv, clk);

sys/arch/arm/samsung/exynos5410_clock.c

899

exynos5410_clock_set_rate(void *priv, struct clk *clk, u_int rate)

sys/arch/arm/samsung/exynos5410_clock.c

901

struct exynos_clk *eclk = (struct exynos_clk *)clk;

sys/arch/arm/samsung/exynos5410_clock.c

903

KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0);

sys/arch/arm/samsung/exynos5410_clock.c

924

exynos5410_clock_enable(void *priv, struct clk *clk)

sys/arch/arm/samsung/exynos5410_clock.c

926

struct exynos_clk *eclk = (struct exynos_clk *)clk;

sys/arch/arm/samsung/exynos5410_clock.c

945

exynos5410_clock_disable(void *priv, struct clk *clk)

sys/arch/arm/samsung/exynos5410_clock.c

947

struct exynos_clk *eclk = (struct exynos_clk *)clk;

sys/arch/arm/samsung/exynos5410_clock.c

966

exynos5410_clock_set_parent(void *priv, struct clk *clk, struct clk *clk_parent)

sys/arch/arm/samsung/exynos5410_clock.c

968

struct exynos_clk *eclk = (struct exynos_clk *)clk;

sys/arch/arm/samsung/exynos5410_clock.c

985

static struct clk *

sys/arch/arm/samsung/exynos5410_clock.c

986

exynos5410_clock_get_parent(void *priv, struct clk *clk)

sys/arch/arm/samsung/exynos5410_clock.c

988

struct exynos_clk *eclk = (struct exynos_clk *)clk;

sys/arch/arm/samsung/exynos5422_clock.c

1007

exynos5422_clock_set_parent(void *priv, struct clk *clk, struct clk *clk_parent)

sys/arch/arm/samsung/exynos5422_clock.c

1009

struct exynos_clk *eclk = (struct exynos_clk *)clk;

sys/arch/arm/samsung/exynos5422_clock.c

1025

static struct clk *

sys/arch/arm/samsung/exynos5422_clock.c

1026

exynos5422_clock_get_parent(void *priv, struct clk *clk)

sys/arch/arm/samsung/exynos5422_clock.c

1028

struct exynos_clk *eclk = (struct exynos_clk *)clk;

sys/arch/arm/samsung/exynos5422_clock.c

1047

return (struct clk *)eclk_parent;

sys/arch/arm/samsung/exynos5422_clock.c

255

static struct clk *exynos5422_clock_get(void *, const char *);

sys/arch/arm/samsung/exynos5422_clock.c

256

static void exynos5422_clock_put(void *, struct clk *);

sys/arch/arm/samsung/exynos5422_clock.c

257

static u_int exynos5422_clock_get_rate(void *, struct clk *);

sys/arch/arm/samsung/exynos5422_clock.c

258

static int exynos5422_clock_set_rate(void *, struct clk *, u_int);

sys/arch/arm/samsung/exynos5422_clock.c

259

static int exynos5422_clock_enable(void *, struct clk *);

sys/arch/arm/samsung/exynos5422_clock.c

260

static int exynos5422_clock_disable(void *, struct clk *);

sys/arch/arm/samsung/exynos5422_clock.c

261

static int exynos5422_clock_set_parent(void *, struct clk *, struct clk *);

sys/arch/arm/samsung/exynos5422_clock.c

262

static struct clk *exynos5422_clock_get_parent(void *, struct clk *);

sys/arch/arm/samsung/exynos5422_clock.c

50

static struct clk *exynos5422_clock_decode(device_t, int, const void *, size_t);

sys/arch/arm/samsung/exynos5422_clock.c

702

struct clk *clk_parent;

sys/arch/arm/samsung/exynos5422_clock.c

734

static struct clk *

sys/arch/arm/samsung/exynos5422_clock.c

829

struct clk *clk_parent;

sys/arch/arm/samsung/exynos5422_clock.c

847

struct clk *clk_parent;

sys/arch/arm/samsung/exynos5422_clock.c

897

static struct clk *

sys/arch/arm/samsung/exynos5422_clock.c

912

exynos5422_clock_put(void *priv, struct clk *clk)

sys/arch/arm/samsung/exynos5422_clock.c

914

struct exynos_clk *eclk = (struct exynos_clk *)clk;

sys/arch/arm/samsung/exynos5422_clock.c

922

exynos5422_clock_get_rate(void *priv, struct clk *clk)

sys/arch/arm/samsung/exynos5422_clock.c

924

struct exynos_clk *eclk = (struct exynos_clk *)clk;

sys/arch/arm/samsung/exynos5422_clock.c

925

struct clk *clk_parent;

sys/arch/arm/samsung/exynos5422_clock.c

934

clk_parent = exynos5422_clock_get_parent(priv, clk);

sys/arch/arm/samsung/exynos5422_clock.c

944

exynos5422_clock_set_rate(void *priv, struct clk *clk, u_int rate)

sys/arch/arm/samsung/exynos5422_clock.c

946

struct exynos_clk *eclk = (struct exynos_clk *)clk;

sys/arch/arm/samsung/exynos5422_clock.c

948

KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0);

sys/arch/arm/samsung/exynos5422_clock.c

967

exynos5422_clock_enable(void *priv, struct clk *clk)

sys/arch/arm/samsung/exynos5422_clock.c

969

struct exynos_clk *eclk = (struct exynos_clk *)clk;

sys/arch/arm/samsung/exynos5422_clock.c

987

exynos5422_clock_disable(void *priv, struct clk *clk)

sys/arch/arm/samsung/exynos5422_clock.c

989

struct exynos_clk *eclk = (struct exynos_clk *)clk;

sys/arch/arm/samsung/exynos_clock.h

71

struct clk base; /* must be first */

sys/arch/arm/samsung/exynos_dwcmmc.c

63

struct clk *sc_clk_biu;

sys/arch/arm/samsung/exynos_dwcmmc.c

64

struct clk *sc_clk_ciu;

sys/arch/arm/samsung/exynos_ehci.c

75

struct clk *clk;

sys/arch/arm/samsung/exynos_ehci.c

88

clk = fdtbus_clock_get(phandle, "usbhost");

sys/arch/arm/samsung/exynos_ehci.c

89

if (clk == NULL || clk_enable(clk) != 0) {

sys/arch/arm/samsung/exynos_i2c.c

61

struct clk * sc_clk;

sys/arch/arm/samsung/exynos_ohci.c

75

struct clk *clk;

sys/arch/arm/samsung/exynos_ohci.c

88

clk = fdtbus_clock_get(phandle, "usbhost");

sys/arch/arm/samsung/exynos_ohci.c

89

if (clk == NULL || clk_enable(clk) != 0) {

sys/arch/arm/samsung/exynos_pwm.c

213

struct clk *clk;

sys/arch/arm/samsung/exynos_pwm.c

223

clk = fdtbus_clock_get(phandle, "timers");

sys/arch/arm/samsung/exynos_pwm.c

224

if (clk == NULL || clk_enable(clk) != 0) {

sys/arch/arm/samsung/exynos_pwm.c

230

sc->sc_clkfreq = clk_get_rate(clk);

sys/arch/arm/samsung/exynos_uart.c

193

struct clk *clk_uart, *clk_uart_baud0;

sys/arch/arm/samsung/exynos_usbdrdphy.c

239

struct clk *clk;

sys/arch/arm/samsung/exynos_usbdrdphy.c

271

clk = fdtbus_clock_get(phandle, "phy");

sys/arch/arm/samsung/exynos_usbdrdphy.c

272

if (clk == NULL || clk_enable(clk) != 0) {

sys/arch/arm/samsung/exynos_usbdrdphy.c

276

clk = fdtbus_clock_get(phandle, "ref");

sys/arch/arm/samsung/exynos_usbdrdphy.c

277

if (clk == NULL || clk_enable(clk) != 0) {

sys/arch/arm/samsung/exynos_usbphy.c

242

struct clk *clk;

sys/arch/arm/samsung/exynos_usbphy.c

278

clk = fdtbus_clock_get(phandle, "phy");

sys/arch/arm/samsung/exynos_usbphy.c

279

if (clk == NULL || clk_enable(clk) != 0) {

sys/arch/arm/samsung/exynos_usbphy.c

283

clk = fdtbus_clock_get(phandle, "ref");

sys/arch/arm/samsung/exynos_usbphy.c

284

if (clk == NULL || clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sun4i_a10_ccu.c

682

struct sunxi_ccu_clk * clk, u_int rate)

sys/arch/arm/sunxi/sun4i_a10_ccu.c

685

error = sunxi_ccu_lcdxch0_set_rate(sc, clk,

sys/arch/arm/sunxi/sun4i_a10_ccu.c

694

struct sunxi_ccu_clk * clk, u_int rate)

sys/arch/arm/sunxi/sun4i_a10_ccu.c

696

return sunxi_ccu_lcdxch0_set_rate(sc, clk,

sys/arch/arm/sunxi/sun4i_a10_ccu.c

704

struct sunxi_ccu_clk * clk, u_int rate)

sys/arch/arm/sunxi/sun4i_a10_ccu.c

706

return sunxi_ccu_lcdxch0_round_rate(sc, clk,

sys/arch/arm/sunxi/sun4i_a10_ccu.c

714

struct sunxi_ccu_clk * clk, u_int rate)

sys/arch/arm/sunxi/sun4i_a10_ccu.c

716

return sunxi_ccu_lcdxch0_round_rate(sc, clk,

sys/arch/arm/sunxi/sun4i_a10_ccu.c

724

struct sunxi_ccu_clk * clk, u_int rate)

sys/arch/arm/sunxi/sun4i_a10_ccu.c

726

return sunxi_ccu_lcdxch1_set_rate(sc, clk,

sys/arch/arm/sunxi/sun4i_a10_ccu.c

734

struct sunxi_ccu_clk * clk, u_int rate)

sys/arch/arm/sunxi/sun4i_a10_ccu.c

736

return sunxi_ccu_lcdxch1_set_rate(sc, clk,

sys/arch/arm/sunxi/sun4i_a10_ccu.c

745

struct sunxi_ccu_clk * clk, u_int rate, int unit)

sys/arch/arm/sunxi/sun4i_a10_ccu.c

748

struct clk *clkp;

sys/arch/arm/sunxi/sun4i_a10_ccu.c

762

error = clk_set_parent(&clk->base, clkp);

sys/arch/arm/sunxi/sun4i_a10_ccu.c

769

struct sunxi_ccu_clk * clk, u_int try_rate, int unit)

sys/arch/arm/sunxi/sun4i_a10_ccu.c

772

struct clk *clkp;

sys/arch/arm/sunxi/sun4i_a10_ccu.c

813

struct sunxi_ccu_clk *clk, u_int rate, int unit)

sys/arch/arm/sunxi/sun4i_a10_ccu.c

816

struct clk *clkp, *pllclk;

sys/arch/arm/sunxi/sun4i_a10_ccu.c

837

error = clk_set_parent(&clk->base, clkp);

sys/arch/arm/sunxi/sun4i_a10_ccu.c

839

error = sunxi_ccu_div_set_rate(sc, clk, rate);

sys/arch/arm/sunxi/sun4i_a10_ccu.c

860

struct clk *clk, *clkp;

sys/arch/arm/sunxi/sun4i_a10_ccu.c

890

clk = &sun4i_a10_ccu_clks[A10_CLK_DE_BE0].base;

sys/arch/arm/sunxi/sun4i_a10_ccu.c

891

error = clk_set_parent(clk, clkp);

sys/arch/arm/sunxi/sun4i_a10_ccu.c

893

clk = &sun4i_a10_ccu_clks[A10_CLK_DE_BE1].base;

sys/arch/arm/sunxi/sun4i_a10_ccu.c

894

error = clk_set_parent(clk, clkp);

sys/arch/arm/sunxi/sun4i_dma.c

357

struct clk *clk;

sys/arch/arm/sunxi/sun4i_dma.c

368

if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL ||

sys/arch/arm/sunxi/sun4i_dma.c

369

clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sun4i_emac.c

248

struct clk *clk;

sys/arch/arm/sunxi/sun4i_emac.c

263

clk = fdtbus_clock_get_index(phandle, 0);

sys/arch/arm/sunxi/sun4i_emac.c

264

if (clk == NULL) {

sys/arch/arm/sunxi/sun4i_emac.c

268

if (clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sun4i_spi.c

100

struct clk *clk, *modclk;

sys/arch/arm/sunxi/sun4i_spi.c

107

if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL

sys/arch/arm/sunxi/sun4i_spi.c

108

|| clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sun4i_spi.c

114

|| clk_set_rate(modclk, clk_get_rate(clk)) != 0

sys/arch/arm/sunxi/sun6i_dma.c

453

struct clk *clk;

sys/arch/arm/sunxi/sun6i_dma.c

465

if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL ||

sys/arch/arm/sunxi/sun6i_dma.c

466

clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sun6i_spi.c

109

struct clk *clk, *modclk;

sys/arch/arm/sunxi/sun6i_spi.c

117

if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL

sys/arch/arm/sunxi/sun6i_spi.c

118

|| clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

134

static struct clk *

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

146

static struct clk *

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

158

sun8i_a23_apbclk_put(void *priv, struct clk *clk)

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

163

sun8i_a23_apbclk_set_rate(void *priv, struct clk *clk, u_int rate)

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

169

sun8i_a23_apbclk_get_rate(void *priv, struct clk *clk)

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

172

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

180

static struct clk *

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

181

sun8i_a23_apbclk_get_parent(void *priv, struct clk *clk)

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

47

static struct clk *sun8i_a23_apbclk_decode(device_t, int, const void *, size_t);

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

53

static struct clk *sun8i_a23_apbclk_get(void *, const char *);

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

54

static void sun8i_a23_apbclk_put(void *, struct clk *);

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

55

static int sun8i_a23_apbclk_set_rate(void *, struct clk *, u_int);

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

56

static u_int sun8i_a23_apbclk_get_rate(void *, struct clk *);

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

57

static struct clk *sun8i_a23_apbclk_get_parent(void *, struct clk *);

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

74

struct clk sc_clk;

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

75

struct clk *sc_parent;

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

136

struct sunxi_ccu_clk *clk, u_int rate)

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

138

const int cluster = clk->u.nkmp.reg == PLL_C0CPUX_CTRL_REG ? 0 : 1;

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

139

struct sunxi_ccu_nkmp *nkmp = &clk->u.nkmp;

sys/arch/arm/sunxi/sun8i_codec.c

125

struct clk *sc_clk_gate;

sys/arch/arm/sunxi/sun8i_codec.c

126

struct clk *sc_clk_mod;

sys/arch/arm/sunxi/sun8i_codec.c

216

const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK);

sys/arch/arm/sunxi/sun8i_codec.c

246

switch (clk) {

sys/arch/arm/sunxi/sun8i_crypto.c

385

struct clk *clk;

sys/arch/arm/sunxi/sun8i_crypto.c

437

if ((clk = fdtbus_clock_get(phandle, "mod")) != NULL) {

sys/arch/arm/sunxi/sun8i_crypto.c

438

if (clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sun8i_crypto.c

442

if (clk_set_rate(clk, mod_rate) != 0) {

sys/arch/arm/sunxi/sun8i_crypto.c

459

aprint_debug_dev(self, ": clock freq %d\n", clk_get_rate(clk));

sys/arch/arm/sunxi/sun9i_a80_ccu.c

138

struct sunxi_ccu_clk *clk, u_int rate)

sys/arch/arm/sunxi/sun9i_a80_ccu.c

140

const int cluster = clk->u.nkmp.reg == PLL_C0CPUX_CTRL_REG ? 0 : 1;

sys/arch/arm/sunxi/sun9i_a80_ccu.c

141

struct sunxi_ccu_nkmp *nkmp = &clk->u.nkmp;

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

135

static struct clk *

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

147

static struct clk *

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

159

sun9i_a80_cpusclk_put(void *priv, struct clk *clk)

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

164

sun9i_a80_cpusclk_set_rate(void *priv, struct clk *clk, u_int rate)

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

170

sun9i_a80_cpusclk_get_rate(void *priv, struct clk *clk)

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

173

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

188

static struct clk *

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

189

sun9i_a80_cpusclk_get_parent(void *priv, struct clk *clk)

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

50

static struct clk *sun9i_a80_cpusclk_decode(device_t, int, const void *, size_t);

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

56

static struct clk *sun9i_a80_cpusclk_get(void *, const char *);

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

57

static void sun9i_a80_cpusclk_put(void *, struct clk *);

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

58

static int sun9i_a80_cpusclk_set_rate(void *, struct clk *, u_int);

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

59

static u_int sun9i_a80_cpusclk_get_rate(void *, struct clk *);

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

60

static struct clk *sun9i_a80_cpusclk_get_parent(void *, struct clk *);

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

77

struct clk sc_clk;

sys/arch/arm/sunxi/sun9i_a80_mmcclk.c

84

struct clk *clk;

sys/arch/arm/sunxi/sun9i_a80_mmcclk.c

96

clk = fdtbus_clock_get(phandle, "ahb");

sys/arch/arm/sunxi/sun9i_a80_mmcclk.c

97

if (clk == NULL || clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sun9i_a80_usbclk.c

122

struct clk *clk;

sys/arch/arm/sunxi/sun9i_a80_usbclk.c

134

clk = fdtbus_clock_get(phandle, "bus");

sys/arch/arm/sunxi/sun9i_a80_usbclk.c

135

if (clk == NULL || clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sun9i_a80_usbphy.c

67

struct clk *sc_clk_phy;

sys/arch/arm/sunxi/sun9i_a80_usbphy.c

68

struct clk *sc_clk_hsic;

sys/arch/arm/sunxi/sunxi_can.c

141

struct clk *clk;

sys/arch/arm/sunxi/sunxi_can.c

163

if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL) {

sys/arch/arm/sunxi/sunxi_can.c

164

if (clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sunxi_can.c

187

sc->sc_timecaps.cltc_clock_freq = clk_get_rate(clk);

sys/arch/arm/sunxi/sunxi_ccu.c

104

static struct clk *

sys/arch/arm/sunxi/sunxi_ccu.c

109

struct sunxi_ccu_clk *clk;

sys/arch/arm/sunxi/sunxi_ccu.c

118

clk = &sc->sc_clks[clock_id];

sys/arch/arm/sunxi/sunxi_ccu.c

119

if (clk->type == SUNXI_CCU_UNKNOWN)

sys/arch/arm/sunxi/sunxi_ccu.c

122

return &clk->base;

sys/arch/arm/sunxi/sunxi_ccu.c

129

static struct clk *

sys/arch/arm/sunxi/sunxi_ccu.c

133

struct sunxi_ccu_clk *clk;

sys/arch/arm/sunxi/sunxi_ccu.c

135

clk = sunxi_ccu_clock_find(sc, name);

sys/arch/arm/sunxi/sunxi_ccu.c

136

if (clk == NULL)

sys/arch/arm/sunxi/sunxi_ccu.c

139

return &clk->base;

sys/arch/arm/sunxi/sunxi_ccu.c

143

sunxi_ccu_clock_put(void *priv, struct clk *clk)

sys/arch/arm/sunxi/sunxi_ccu.c

148

sunxi_ccu_clock_get_rate(void *priv, struct clk *clkp)

sys/arch/arm/sunxi/sunxi_ccu.c

151

struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;

sys/arch/arm/sunxi/sunxi_ccu.c

152

struct clk *clkp_parent;

sys/arch/arm/sunxi/sunxi_ccu.c

154

if (clk->get_rate)

sys/arch/arm/sunxi/sunxi_ccu.c

155

return clk->get_rate(sc, clk);

sys/arch/arm/sunxi/sunxi_ccu.c

159

aprint_error("%s: no parent for %s\n", __func__, clk->base.name);

sys/arch/arm/sunxi/sunxi_ccu.c

167

sunxi_ccu_clock_set_rate(void *priv, struct clk *clkp, u_int rate)

sys/arch/arm/sunxi/sunxi_ccu.c

170

struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;

sys/arch/arm/sunxi/sunxi_ccu.c

171

struct clk *clkp_parent;

sys/arch/arm/sunxi/sunxi_ccu.c

176

aprint_error("%s: no parent for %s\n", __func__, clk->base.name);

sys/arch/arm/sunxi/sunxi_ccu.c

182

if (clk->set_rate)

sys/arch/arm/sunxi/sunxi_ccu.c

183

return clk->set_rate(sc, clk, rate);

sys/arch/arm/sunxi/sunxi_ccu.c

189

sunxi_ccu_clock_round_rate(void *priv, struct clk *clkp, u_int rate)

sys/arch/arm/sunxi/sunxi_ccu.c

192

struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;

sys/arch/arm/sunxi/sunxi_ccu.c

193

struct clk *clkp_parent;

sys/arch/arm/sunxi/sunxi_ccu.c

198

aprint_error("%s: no parent for %s\n", __func__, clk->base.name);

sys/arch/arm/sunxi/sunxi_ccu.c

204

if (clk->round_rate)

sys/arch/arm/sunxi/sunxi_ccu.c

205

return clk->round_rate(sc, clk, rate);

sys/arch/arm/sunxi/sunxi_ccu.c

211

sunxi_ccu_clock_enable(void *priv, struct clk *clkp)

sys/arch/arm/sunxi/sunxi_ccu.c

214

struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;

sys/arch/arm/sunxi/sunxi_ccu.c

215

struct clk *clkp_parent;

sys/arch/arm/sunxi/sunxi_ccu.c

225

if (clk->enable)

sys/arch/arm/sunxi/sunxi_ccu.c

226

error = clk->enable(sc, clk, 1);

sys/arch/arm/sunxi/sunxi_ccu.c

232

sunxi_ccu_clock_disable(void *priv, struct clk *clkp)

sys/arch/arm/sunxi/sunxi_ccu.c

235

struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;

sys/arch/arm/sunxi/sunxi_ccu.c

238

if (clk->enable)

sys/arch/arm/sunxi/sunxi_ccu.c

239

error = clk->enable(sc, clk, 0);

sys/arch/arm/sunxi/sunxi_ccu.c

245

sunxi_ccu_clock_set_parent(void *priv, struct clk *clkp,

sys/arch/arm/sunxi/sunxi_ccu.c

246

struct clk *clkp_parent)

sys/arch/arm/sunxi/sunxi_ccu.c

249

struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;

sys/arch/arm/sunxi/sunxi_ccu.c

251

if (clk->set_parent == NULL)

sys/arch/arm/sunxi/sunxi_ccu.c

254

return clk->set_parent(sc, clk, clkp_parent->name);

sys/arch/arm/sunxi/sunxi_ccu.c

257

static struct clk *

sys/arch/arm/sunxi/sunxi_ccu.c

258

sunxi_ccu_clock_get_parent(void *priv, struct clk *clkp)

sys/arch/arm/sunxi/sunxi_ccu.c

261

struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;

sys/arch/arm/sunxi/sunxi_ccu.c

265

if (clk->get_parent == NULL)

sys/arch/arm/sunxi/sunxi_ccu.c

268

parent = clk->get_parent(sc, clk);

sys/arch/arm/sunxi/sunxi_ccu.c

341

struct sunxi_ccu_clk *clk;

sys/arch/arm/sunxi/sunxi_ccu.c

342

struct clk *clkp_parent;

sys/arch/arm/sunxi/sunxi_ccu.c

347

clk = &sc->sc_clks[i];

sys/arch/arm/sunxi/sunxi_ccu.c

348

if (clk->type == SUNXI_CCU_UNKNOWN)

sys/arch/arm/sunxi/sunxi_ccu.c

351

clkp_parent = clk_get_parent(&clk->base);

sys/arch/arm/sunxi/sunxi_ccu.c

353

switch (clk->type) {

sys/arch/arm/sunxi/sunxi_ccu.c

369

clk->base.name,

sys/arch/arm/sunxi/sunxi_ccu.c

373

aprint_debug("%10u Hz\n", clk_get_rate(&clk->base));

sys/arch/arm/sunxi/sunxi_ccu.h

261

struct sunxi_ccu_clk *clk, struct sunxi_ccu_clk *pclk,

sys/arch/arm/sunxi/sunxi_ccu.h

447

struct clk base;

sys/arch/arm/sunxi/sunxi_ccu_display.c

100

struct sunxi_ccu_clk * clk, struct sunxi_ccu_clk *pllclk,

sys/arch/arm/sunxi/sunxi_ccu_display.c

103

struct clk *clkp, *pllclkp;

sys/arch/arm/sunxi/sunxi_ccu_display.c

137

error = clk_set_parent(&clk->base, clkp);

sys/arch/arm/sunxi/sunxi_ccu_display.c

141

error = sunxi_ccu_div_set_rate(sc, clk, new_rate);

sys/arch/arm/sunxi/sunxi_ccu_display.c

44

struct sunxi_ccu_clk *clk, struct sunxi_ccu_clk *pllclk,

sys/arch/arm/sunxi/sunxi_ccu_display.c

47

struct clk *clkp;

sys/arch/arm/sunxi/sunxi_ccu_display.c

65

error = clk_set_parent(&clk->base, &pllclk_x2->base);

sys/arch/arm/sunxi/sunxi_ccu_display.c

70

error = clk_set_parent(&clk->base, clkp);

sys/arch/arm/sunxi/sunxi_ccu_display.c

79

struct sunxi_ccu_clk * clk, struct sunxi_ccu_clk *pllclk,

sys/arch/arm/sunxi/sunxi_ccu_display.c

82

struct clk *clkp;

sys/arch/arm/sunxi/sunxi_ccu_div.c

103

struct sunxi_ccu_clk *clk, u_int new_rate)

sys/arch/arm/sunxi/sunxi_ccu_div.c

105

struct sunxi_ccu_div *div = &clk->u.div;

sys/arch/arm/sunxi/sunxi_ccu_div.c

107

struct clk *best_parent;

sys/arch/arm/sunxi/sunxi_ccu_div.c

130

return clk_set_parent(&clk->base, best_parent);

sys/arch/arm/sunxi/sunxi_ccu_div.c

135

struct sunxi_ccu_clk *clk, u_int new_rate)

sys/arch/arm/sunxi/sunxi_ccu_div.c

137

struct sunxi_ccu_div *div = &clk->u.div;

sys/arch/arm/sunxi/sunxi_ccu_div.c

138

struct clk *clkp, *clkp_parent;

sys/arch/arm/sunxi/sunxi_ccu_div.c

143

KASSERT(clk->type == SUNXI_CCU_DIV);

sys/arch/arm/sunxi/sunxi_ccu_div.c

145

clkp = &clk->base;

sys/arch/arm/sunxi/sunxi_ccu_div.c

154

return sunxi_ccu_div_select_parent(sc, clk, new_rate);

sys/arch/arm/sunxi/sunxi_ccu_div.c

185

struct sunxi_ccu_clk *clk, const char *name)

sys/arch/arm/sunxi/sunxi_ccu_div.c

187

struct sunxi_ccu_div *div = &clk->u.div;

sys/arch/arm/sunxi/sunxi_ccu_div.c

191

KASSERT(clk->type == SUNXI_CCU_DIV);

sys/arch/arm/sunxi/sunxi_ccu_div.c

214

struct sunxi_ccu_clk *clk)

sys/arch/arm/sunxi/sunxi_ccu_div.c

216

struct sunxi_ccu_div *div = &clk->u.div;

sys/arch/arm/sunxi/sunxi_ccu_div.c

220

KASSERT(clk->type == SUNXI_CCU_DIV);

sys/arch/arm/sunxi/sunxi_ccu_div.c

40

sunxi_ccu_div_enable(struct sunxi_ccu_softc *sc, struct sunxi_ccu_clk *clk,

sys/arch/arm/sunxi/sunxi_ccu_div.c

43

struct sunxi_ccu_div *div = &clk->u.div;

sys/arch/arm/sunxi/sunxi_ccu_div.c

46

KASSERT(clk->type == SUNXI_CCU_DIV);

sys/arch/arm/sunxi/sunxi_ccu_div.c

63

struct sunxi_ccu_clk *clk)

sys/arch/arm/sunxi/sunxi_ccu_div.c

65

struct sunxi_ccu_div *div = &clk->u.div;

sys/arch/arm/sunxi/sunxi_ccu_div.c

66

struct clk *clkp, *clkp_parent;

sys/arch/arm/sunxi/sunxi_ccu_div.c

70

KASSERT(clk->type == SUNXI_CCU_DIV);

sys/arch/arm/sunxi/sunxi_ccu_div.c

72

clkp = &clk->base;

sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c

100

KASSERT(clk->type == SUNXI_CCU_FIXED_FACTOR);

sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c

40

sunxi_ccu_fixed_factor_get_parent_rate(struct clk *clkp)

sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c

42

struct clk *clkp_parent;

sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c

53

struct sunxi_ccu_clk *clk)

sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c

55

struct sunxi_ccu_fixed_factor *fixed_factor = &clk->u.fixed_factor;

sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c

56

struct clk *clkp = &clk->base;

sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c

58

KASSERT(clk->type == SUNXI_CCU_FIXED_FACTOR);

sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c

68

sunxi_ccu_fixed_factor_set_parent_rate(struct clk *clkp, u_int rate)

sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c

70

struct clk *clkp_parent;

sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c

81

struct sunxi_ccu_clk *clk, u_int rate)

sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c

83

struct sunxi_ccu_fixed_factor *fixed_factor = &clk->u.fixed_factor;

sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c

84

struct clk *clkp = &clk->base;

sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c

86

KASSERT(clk->type == SUNXI_CCU_FIXED_FACTOR);

sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c

96

struct sunxi_ccu_clk *clk)

sys/arch/arm/sunxi/sunxi_ccu_fixed_factor.c

98

struct sunxi_ccu_fixed_factor *fixed_factor = &clk->u.fixed_factor;

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

106

struct sunxi_ccu_clk *clk, u_int new_rate)

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

108

struct sunxi_ccu_fractional *fractional = &clk->u.fractional;

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

109

struct clk *clkp, *clkp_parent;

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

116

clkp = &clk->base;

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

185

struct sunxi_ccu_clk *clk, u_int try_rate)

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

187

struct sunxi_ccu_fractional *fractional = &clk->u.fractional;

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

188

struct clk *clkp, *clkp_parent;

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

195

clkp = &clk->base;

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

238

struct sunxi_ccu_clk *clk)

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

240

struct sunxi_ccu_fractional *fractional = &clk->u.fractional;

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

242

KASSERT(clk->type == SUNXI_CCU_FRACTIONAL);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

41

struct sunxi_ccu_clk *clk, int enable)

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

43

struct sunxi_ccu_fractional *fractional = &clk->u.fractional;

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

46

KASSERT(clk->type == SUNXI_CCU_FRACTIONAL);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

63

struct sunxi_ccu_clk *clk)

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

65

struct sunxi_ccu_fractional *fractional = &clk->u.fractional;

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

66

struct clk *clkp, *clkp_parent;

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

70

KASSERT(clk->type == SUNXI_CCU_FRACTIONAL);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

72

clkp = &clk->base;

sys/arch/arm/sunxi/sunxi_ccu_gate.c

40

sunxi_ccu_gate_enable(struct sunxi_ccu_softc *sc, struct sunxi_ccu_clk *clk,

sys/arch/arm/sunxi/sunxi_ccu_gate.c

43

struct sunxi_ccu_gate *gate = &clk->u.gate;

sys/arch/arm/sunxi/sunxi_ccu_gate.c

46

KASSERT(clk->type == SUNXI_CCU_GATE);

sys/arch/arm/sunxi/sunxi_ccu_gate.c

59

sunxi_ccu_gate_get_parent(struct sunxi_ccu_softc *sc, struct sunxi_ccu_clk *clk)

sys/arch/arm/sunxi/sunxi_ccu_gate.c

61

struct sunxi_ccu_gate *gate = &clk->u.gate;

sys/arch/arm/sunxi/sunxi_ccu_gate.c

63

KASSERT(clk->type == SUNXI_CCU_GATE);

sys/arch/arm/sunxi/sunxi_ccu_mux.c

41

struct sunxi_ccu_clk *clk, const char *name)

sys/arch/arm/sunxi/sunxi_ccu_mux.c

43

struct sunxi_ccu_mux *mux = &clk->u.mux;

sys/arch/arm/sunxi/sunxi_ccu_mux.c

47

KASSERT(clk->type == SUNXI_CCU_MUX);

sys/arch/arm/sunxi/sunxi_ccu_mux.c

70

struct sunxi_ccu_clk *clk)

sys/arch/arm/sunxi/sunxi_ccu_mux.c

72

struct sunxi_ccu_mux *mux = &clk->u.mux;

sys/arch/arm/sunxi/sunxi_ccu_mux.c

76

KASSERT(clk->type == SUNXI_CCU_MUX);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

138

struct sunxi_ccu_clk *clk, u_int rate)

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

140

struct sunxi_ccu_nkmp *nkmp = &clk->u.nkmp;

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

144

KASSERT(clk->type == SUNXI_CCU_NKMP);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

217

struct sunxi_ccu_clk *clk)

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

219

struct sunxi_ccu_nkmp *nkmp = &clk->u.nkmp;

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

221

KASSERT(clk->type == SUNXI_CCU_NKMP);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

40

sunxi_ccu_nkmp_enable(struct sunxi_ccu_softc *sc, struct sunxi_ccu_clk *clk,

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

43

struct sunxi_ccu_nkmp *nkmp = &clk->u.nkmp;

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

47

KASSERT(clk->type == SUNXI_CCU_NKMP);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

75

struct sunxi_ccu_clk *clk)

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

77

struct sunxi_ccu_nkmp *nkmp = &clk->u.nkmp;

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

78

struct clk *clkp, *clkp_parent;

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

82

KASSERT(clk->type == SUNXI_CCU_NKMP);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

84

clkp = &clk->base;

sys/arch/arm/sunxi/sunxi_ccu_nm.c

103

struct sunxi_ccu_clk *clk, u_int new_rate)

sys/arch/arm/sunxi/sunxi_ccu_nm.c

105

struct sunxi_ccu_nm *nm = &clk->u.nm;

sys/arch/arm/sunxi/sunxi_ccu_nm.c

106

struct clk *clkp, *clkp_parent;

sys/arch/arm/sunxi/sunxi_ccu_nm.c

115

clkp = &clk->base;

sys/arch/arm/sunxi/sunxi_ccu_nm.c

191

struct sunxi_ccu_clk *clk, const char *name)

sys/arch/arm/sunxi/sunxi_ccu_nm.c

193

struct sunxi_ccu_nm *nm = &clk->u.nm;

sys/arch/arm/sunxi/sunxi_ccu_nm.c

197

KASSERT(clk->type == SUNXI_CCU_NM);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

220

struct sunxi_ccu_clk *clk)

sys/arch/arm/sunxi/sunxi_ccu_nm.c

222

struct sunxi_ccu_nm *nm = &clk->u.nm;

sys/arch/arm/sunxi/sunxi_ccu_nm.c

226

KASSERT(clk->type == SUNXI_CCU_NM);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

40

sunxi_ccu_nm_enable(struct sunxi_ccu_softc *sc, struct sunxi_ccu_clk *clk,

sys/arch/arm/sunxi/sunxi_ccu_nm.c

43

struct sunxi_ccu_nm *nm = &clk->u.nm;

sys/arch/arm/sunxi/sunxi_ccu_nm.c

46

KASSERT(clk->type == SUNXI_CCU_NM);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

63

struct sunxi_ccu_clk *clk)

sys/arch/arm/sunxi/sunxi_ccu_nm.c

65

struct sunxi_ccu_nm *nm = &clk->u.nm;

sys/arch/arm/sunxi/sunxi_ccu_nm.c

66

struct clk *clkp, *clkp_parent;

sys/arch/arm/sunxi/sunxi_ccu_nm.c

70

KASSERT(clk->type == SUNXI_CCU_NM);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

72

clkp = &clk->base;

sys/arch/arm/sunxi/sunxi_ccu_phase.c

119

struct sunxi_ccu_clk *clk)

sys/arch/arm/sunxi/sunxi_ccu_phase.c

121

struct sunxi_ccu_phase *phase = &clk->u.phase;

sys/arch/arm/sunxi/sunxi_ccu_phase.c

123

KASSERT(clk->type == SUNXI_CCU_PHASE);

sys/arch/arm/sunxi/sunxi_ccu_phase.c

40

sunxi_ccu_phase_get_parent_rate(struct clk *clkp)

sys/arch/arm/sunxi/sunxi_ccu_phase.c

42

struct clk *clkp_parent;

sys/arch/arm/sunxi/sunxi_ccu_phase.c

59

struct sunxi_ccu_clk *clk)

sys/arch/arm/sunxi/sunxi_ccu_phase.c

61

struct sunxi_ccu_phase *phase = &clk->u.phase;

sys/arch/arm/sunxi/sunxi_ccu_phase.c

62

struct clk *clkp = &clk->base;

sys/arch/arm/sunxi/sunxi_ccu_phase.c

66

KASSERT(clk->type == SUNXI_CCU_PHASE);

sys/arch/arm/sunxi/sunxi_ccu_phase.c

85

struct sunxi_ccu_clk *clk, u_int new_rate)

sys/arch/arm/sunxi/sunxi_ccu_phase.c

87

struct sunxi_ccu_phase *phase = &clk->u.phase;

sys/arch/arm/sunxi/sunxi_ccu_phase.c

88

struct clk *clkp = &clk->base;

sys/arch/arm/sunxi/sunxi_ccu_phase.c

92

KASSERT(clk->type == SUNXI_CCU_PHASE);

sys/arch/arm/sunxi/sunxi_ccu_phase.c

94

clkp = &clk->base;

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

100

struct sunxi_ccu_prediv *prediv = &clk->u.prediv;

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

104

KASSERT(clk->type == SUNXI_CCU_PREDIV);

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

127

struct sunxi_ccu_clk *clk)

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

129

struct sunxi_ccu_prediv *prediv = &clk->u.prediv;

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

133

KASSERT(clk->type == SUNXI_CCU_PREDIV);

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

41

struct sunxi_ccu_clk *clk)

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

43

struct sunxi_ccu_prediv *prediv = &clk->u.prediv;

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

44

struct clk *clkp, *clkp_parent;

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

48

KASSERT(clk->type == SUNXI_CCU_PREDIV);

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

50

clkp = &clk->base;

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

91

struct sunxi_ccu_clk *clk, u_int new_rate)

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

98

struct sunxi_ccu_clk *clk, const char *name)

sys/arch/arm/sunxi/sunxi_codec.c

528

struct clk *clk;

sys/arch/arm/sunxi/sunxi_codec.c

532

clk = fdtbus_clock_get(phandle, "codec");

sys/arch/arm/sunxi/sunxi_codec.c

533

if (clk == NULL) {

sys/arch/arm/sunxi/sunxi_codec.c

537

error = clk_set_rate(clk, 24576000);

sys/arch/arm/sunxi/sunxi_codec.c

542

error = clk_enable(clk);

sys/arch/arm/sunxi/sunxi_codec.c

549

clk = fdtbus_clock_get(phandle, "apb");

sys/arch/arm/sunxi/sunxi_codec.c

550

if (clk == NULL) {

sys/arch/arm/sunxi/sunxi_codec.c

554

error = clk_enable(clk);

sys/arch/arm/sunxi/sunxi_de2_ccu.c

128

struct clk *clk_bus, *clk_mod;

sys/arch/arm/sunxi/sunxi_debe.c

77

struct clk *sc_clk_ahb;

sys/arch/arm/sunxi/sunxi_debe.c

78

struct clk *sc_clk_mod;

sys/arch/arm/sunxi/sunxi_debe.c

79

struct clk *sc_clk_ram;

sys/arch/arm/sunxi/sunxi_dwhdmi.c

233

struct clk *clk_iahb, *clk_isfr, *clk_tmds;

sys/arch/arm/sunxi/sunxi_dwhdmi.c

65

struct clk *sc_clk;

sys/arch/arm/sunxi/sunxi_emac.c

178

struct clk *clk_ahb;

sys/arch/arm/sunxi/sunxi_emac.c

179

struct clk *clk_ephy;

sys/arch/arm/sunxi/sunxi_gates.c

110

sunxi_gates_clock_put(void *priv, struct clk *clk)

sys/arch/arm/sunxi/sunxi_gates.c

115

sunxi_gates_clock_get_rate(void *priv, struct clk *clkp)

sys/arch/arm/sunxi/sunxi_gates.c

119

struct clk *clkp_parent;

sys/arch/arm/sunxi/sunxi_gates.c

135

sunxi_gates_clock_enable(void *priv, struct clk *clkp)

sys/arch/arm/sunxi/sunxi_gates.c

152

sunxi_gates_clock_disable(void *priv, struct clk *clkp)

sys/arch/arm/sunxi/sunxi_gates.c

168

static struct clk *

sys/arch/arm/sunxi/sunxi_gates.c

169

sunxi_gates_clock_get_parent(void *priv, struct clk *clkp)

sys/arch/arm/sunxi/sunxi_gates.c

189

struct clk *clkp_parent;

sys/arch/arm/sunxi/sunxi_gates.c

52

struct clk base;

sys/arch/arm/sunxi/sunxi_gates.c

73

static struct clk *

sys/arch/arm/sunxi/sunxi_gates.c

96

static struct clk *

sys/arch/arm/sunxi/sunxi_gmac.c

129

struct clk *clk_gmac, *clk_gmac_tx;

sys/arch/arm/sunxi/sunxi_gmacclk.c

145

static struct clk *

sys/arch/arm/sunxi/sunxi_gmacclk.c

157

static struct clk *

sys/arch/arm/sunxi/sunxi_gmacclk.c

169

sunxi_gmacclk_put(void *priv, struct clk *clk)

sys/arch/arm/sunxi/sunxi_gmacclk.c

174

sunxi_gmacclk_set_rate(void *priv, struct clk *clk, u_int rate)

sys/arch/arm/sunxi/sunxi_gmacclk.c

198

sunxi_gmacclk_get_rate(void *priv, struct clk *clk)

sys/arch/arm/sunxi/sunxi_gmacclk.c

200

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/arm/sunxi/sunxi_gmacclk.c

205

static struct clk *

sys/arch/arm/sunxi/sunxi_gmacclk.c

206

sunxi_gmacclk_get_parent(void *priv, struct clk *clk)

sys/arch/arm/sunxi/sunxi_gmacclk.c

53

static struct clk *sunxi_gmacclk_decode(device_t, int, const void *, size_t);

sys/arch/arm/sunxi/sunxi_gmacclk.c

59

static struct clk *sunxi_gmacclk_get(void *, const char *);

sys/arch/arm/sunxi/sunxi_gmacclk.c

60

static void sunxi_gmacclk_put(void *, struct clk *);

sys/arch/arm/sunxi/sunxi_gmacclk.c

61

static int sunxi_gmacclk_set_rate(void *, struct clk *, u_int);

sys/arch/arm/sunxi/sunxi_gmacclk.c

62

static u_int sunxi_gmacclk_get_rate(void *, struct clk *);

sys/arch/arm/sunxi/sunxi_gmacclk.c

63

static struct clk *sunxi_gmacclk_get_parent(void *, struct clk *);

sys/arch/arm/sunxi/sunxi_gmacclk.c

80

struct clk sc_clk;

sys/arch/arm/sunxi/sunxi_gmacclk.c

81

struct clk *sc_parent[2];

sys/arch/arm/sunxi/sunxi_gpio.c

1002

struct clk *clk;

sys/arch/arm/sunxi/sunxi_gpio.c

1012

if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL)

sys/arch/arm/sunxi/sunxi_gpio.c

1013

if (clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sunxi_hdmi.c

575

struct clk *clk;

sys/arch/arm/sunxi/sunxi_hdmi.c

586

clk = sc->sc_clk_pll0;

sys/arch/arm/sunxi/sunxi_hdmi.c

590

clk = sc->sc_clk_pll1;

sys/arch/arm/sunxi/sunxi_hdmi.c

596

error = clk_set_rate(clk, 270000000);

sys/arch/arm/sunxi/sunxi_hdmi.c

598

clk = clk_get_parent(clk);

sys/arch/arm/sunxi/sunxi_hdmi.c

600

error = clk_set_rate(clk, 270000000);

sys/arch/arm/sunxi/sunxi_hdmi.c

606

error = clk_set_parent(sc->sc_clk_mod, clk);

sys/arch/arm/sunxi/sunxi_hdmi.c

68

struct clk *sc_clk_ahb;

sys/arch/arm/sunxi/sunxi_hdmi.c

69

struct clk *sc_clk_mod;

sys/arch/arm/sunxi/sunxi_hdmi.c

70

struct clk *sc_clk_pll0;

sys/arch/arm/sunxi/sunxi_hdmi.c

71

struct clk *sc_clk_pll1;

sys/arch/arm/sunxi/sunxi_hdmi.c

847

struct clk *clk_pll;

sys/arch/arm/sunxi/sunxi_hdmiphy.c

135

struct clk *sc_clk_bus;

sys/arch/arm/sunxi/sunxi_hdmiphy.c

136

struct clk *sc_clk_mod;

sys/arch/arm/sunxi/sunxi_hdmiphy.c

137

struct clk *sc_clk_pll0;

sys/arch/arm/sunxi/sunxi_hdmiphy.c

409

struct clk *clk_bus, *clk_mod, *clk_pll0;

sys/arch/arm/sunxi/sunxi_hstimer.c

145

struct clk *clk;

sys/arch/arm/sunxi/sunxi_hstimer.c

151

if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL

sys/arch/arm/sunxi/sunxi_hstimer.c

152

|| clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sunxi_hstimer.c

179

tc->tc_frequency = clk_get_rate(clk);

sys/arch/arm/sunxi/sunxi_i2s.c

187

struct clk *sc_clk;

sys/arch/arm/sunxi/sunxi_i2s.c

700

const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK);

sys/arch/arm/sunxi/sunxi_i2s.c

775

switch (clk) {

sys/arch/arm/sunxi/sunxi_i2s.c

822

struct clk *clk;

sys/arch/arm/sunxi/sunxi_i2s.c

832

clk = fdtbus_clock_get(phandle, "apb");

sys/arch/arm/sunxi/sunxi_i2s.c

833

if (clk == NULL) {

sys/arch/arm/sunxi/sunxi_i2s.c

837

error = clk_enable(clk);

sys/arch/arm/sunxi/sunxi_lcdc.c

134

struct clk *sc_clk_ch[2];

sys/arch/arm/sunxi/sunxi_lcdc.c

489

struct clk *clk;

sys/arch/arm/sunxi/sunxi_lcdc.c

510

clk = fdtbus_clock_get(phandle, "ahb");

sys/arch/arm/sunxi/sunxi_lcdc.c

511

if (clk == NULL || clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sunxi_lradc.c

106

struct clk *clk;

sys/arch/arm/sunxi/sunxi_lradc.c

128

if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL) {

sys/arch/arm/sunxi/sunxi_lradc.c

129

if (clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sunxi_mixer.c

626

struct clk *clk_bus, *clk_mod;

sys/arch/arm/sunxi/sunxi_mmc.c

179

struct clk *sc_clk_ahb;

sys/arch/arm/sunxi/sunxi_mmc.c

180

struct clk *sc_clk_mmc;

sys/arch/arm/sunxi/sunxi_mmc.c

181

struct clk *sc_clk_output;

sys/arch/arm/sunxi/sunxi_mmc.c

182

struct clk *sc_clk_sample;

sys/arch/arm/sunxi/sunxi_musb.c

309

struct clk *clk;

sys/arch/arm/sunxi/sunxi_musb.c

330

for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)

sys/arch/arm/sunxi/sunxi_musb.c

331

if (clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sunxi_nand.c

143

struct clk *sc_clk_mod;

sys/arch/arm/sunxi/sunxi_nand.c

144

struct clk *sc_clk_ahb;

sys/arch/arm/sunxi/sunxi_pwm.c

195

struct clk *clk;

sys/arch/arm/sunxi/sunxi_pwm.c

205

clk = fdtbus_clock_get_index(phandle, 0);

sys/arch/arm/sunxi/sunxi_pwm.c

206

if (clk == NULL) {

sys/arch/arm/sunxi/sunxi_pwm.c

212

sc->sc_clkfreq = clk_get_rate(clk);

sys/arch/arm/sunxi/sunxi_rsb.c

132

struct clk *clk;

sys/arch/arm/sunxi/sunxi_rsb.c

147

if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL)

sys/arch/arm/sunxi/sunxi_rsb.c

148

if (clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sunxi_rtc.c

281

struct clk *sc_parent_clk; /* external oscillator */

sys/arch/arm/sunxi/sunxi_rtc.c

299

struct clk sc_clks[SUNXI_RTC_NCLKS];

sys/arch/arm/sunxi/sunxi_rtc.c

315

static struct clk *

sys/arch/arm/sunxi/sunxi_rtc.c

317

static u_int sunxi_rtc_clk_get_rate(void *, struct clk *);

sys/arch/arm/sunxi/sunxi_rtc.c

318

static int sunxi_rtc_clk_enable(void *, struct clk *);

sys/arch/arm/sunxi/sunxi_rtc.c

319

static int sunxi_rtc_clk_disable(void *, struct clk *);

sys/arch/arm/sunxi/sunxi_rtc.c

320

static int sunxi_rtc_clk_set_parent(void *, struct clk *, struct clk *);

sys/arch/arm/sunxi/sunxi_rtc.c

321

static struct clk *

sys/arch/arm/sunxi/sunxi_rtc.c

322

sunxi_rtc_clk_get_parent(void *, struct clk *);

sys/arch/arm/sunxi/sunxi_rtc.c

333

static struct clk *

sys/arch/arm/sunxi/sunxi_rtc.c

497

static struct clk *

sys/arch/arm/sunxi/sunxi_rtc.c

514

sunxi_rtc_clk_get_rate(void *priv, struct clk *clk)

sys/arch/arm/sunxi/sunxi_rtc.c

518

if (clk == &sc->sc_clks[SUNXI_RTC_CLK_IOSC]) {

sys/arch/arm/sunxi/sunxi_rtc.c

544

sunxi_rtc_clk_enable(void *priv, struct clk *clk)

sys/arch/arm/sunxi/sunxi_rtc.c

548

if (clk != &sc->sc_clks[SUNXI_RTC_CLK_LOSC_GATE])

sys/arch/arm/sunxi/sunxi_rtc.c

563

sunxi_rtc_clk_disable(void *priv, struct clk *clk)

sys/arch/arm/sunxi/sunxi_rtc.c

567

if (clk != &sc->sc_clks[SUNXI_RTC_CLK_LOSC_GATE])

sys/arch/arm/sunxi/sunxi_rtc.c

582

sunxi_rtc_clk_set_parent(void *priv, struct clk *clk, struct clk *parent_clk)

sys/arch/arm/sunxi/sunxi_rtc.c

586

if (clk == &sc->sc_clks[SUNXI_RTC_CLK_IOSC])

sys/arch/arm/sunxi/sunxi_rtc.c

605

static struct clk *

sys/arch/arm/sunxi/sunxi_rtc.c

606

sunxi_rtc_clk_get_parent(void *priv, struct clk *clk)

sys/arch/arm/sunxi/sunxi_rtc.c

611

if (clk == &sc->sc_clks[SUNXI_RTC_CLK_IOSC])

sys/arch/arm/sunxi/sunxi_sata.c

106

for (i = 0; (clk = fdtbus_clock_get_index(phandle, i)) != NULL; i++)

sys/arch/arm/sunxi/sunxi_sata.c

107

if (clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sunxi_sata.c

78

struct clk *clk;

sys/arch/arm/sunxi/sunxi_tcon.c

65

struct clk *sc_clk_ahb;

sys/arch/arm/sunxi/sunxi_tcon.c

66

struct clk *sc_clk_ch0;

sys/arch/arm/sunxi/sunxi_tcon.c

67

struct clk *sc_clk_ch1;

sys/arch/arm/sunxi/sunxi_tcon.c

783

u_int clk = mode->htotal * (mode->vtotal * 2 + 1) *

sys/arch/arm/sunxi/sunxi_tcon.c

785

if ((clk / 2) == mode->dot_clock * 1000)

sys/arch/arm/sunxi/sunxi_thermal.c

520

struct clk *clk;

sys/arch/arm/sunxi/sunxi_thermal.c

523

clk = fdtbus_clock_get(sc->phandle, "bus");

sys/arch/arm/sunxi/sunxi_thermal.c

524

if (clk == NULL) {

sys/arch/arm/sunxi/sunxi_thermal.c

526

clk = fdtbus_clock_get(sc->phandle, "ahb");

sys/arch/arm/sunxi/sunxi_thermal.c

528

if (clk) {

sys/arch/arm/sunxi/sunxi_thermal.c

529

error = clk_enable(clk);

sys/arch/arm/sunxi/sunxi_thermal.c

534

clk = fdtbus_clock_get(sc->phandle, "mod");

sys/arch/arm/sunxi/sunxi_thermal.c

535

if (clk == NULL) {

sys/arch/arm/sunxi/sunxi_thermal.c

537

clk = fdtbus_clock_get(sc->phandle, "ths");

sys/arch/arm/sunxi/sunxi_thermal.c

539

if (clk) {

sys/arch/arm/sunxi/sunxi_thermal.c

540

error = clk_set_rate(clk, sc->conf->clk_rate);

sys/arch/arm/sunxi/sunxi_thermal.c

543

error = clk_enable(clk);

sys/arch/arm/sunxi/sunxi_timer.c

104

struct clk *sc_clk;

sys/arch/arm/sunxi/sunxi_twi.c

132

struct clk *clk;

sys/arch/arm/sunxi/sunxi_twi.c

153

if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL)

sys/arch/arm/sunxi/sunxi_twi.c

154

if (clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sunxi_twi.c

173

if (clk != NULL)

sys/arch/arm/sunxi/sunxi_twi.c

174

sunxi_twi_set_clock(sc, clk_get_rate(clk), 100000);

sys/arch/arm/sunxi/sunxi_usb3phy.c

174

struct clk *clk;

sys/arch/arm/sunxi/sunxi_usb3phy.c

197

for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)

sys/arch/arm/sunxi/sunxi_usb3phy.c

198

if (clk_enable(clk) != 0) {

sys/arch/arm/sunxi/sunxi_usbphy.c

353

struct clk *clk;

sys/arch/arm/sunxi/sunxi_usbphy.c

388

for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)

sys/arch/arm/sunxi/sunxi_usbphy.c

389

if (clk_enable(clk) != 0) {

sys/arch/arm/ti/am18xx_aclk.c

108

static struct clk *

sys/arch/arm/ti/am18xx_aclk.c

113

if (strcmp(sc->sc_config->clk->name, name) == 0) {

sys/arch/arm/ti/am18xx_aclk.c

114

return sc->sc_config->clk;

sys/arch/arm/ti/am18xx_aclk.c

121

am18xx_aclk_clk_get_rate(void *priv, struct clk *clkp)

sys/arch/arm/ti/am18xx_aclk.c

128

static struct clk *

sys/arch/arm/ti/am18xx_aclk.c

129

am18xx_aclk_clk_get_parent(void *priv, struct clk *clkp)

sys/arch/arm/ti/am18xx_aclk.c

136

static struct clk *

sys/arch/arm/ti/am18xx_aclk.c

141

return sc->sc_config->clk;

sys/arch/arm/ti/am18xx_aclk.c

187

sc->sc_config->clk->domain = &sc->sc_clkdom;

sys/arch/arm/ti/am18xx_aclk.c

188

clk_attach(sc->sc_config->clk);

sys/arch/arm/ti/am18xx_aclk.c

48

struct clk *clk; /* double wrap clk because the config must be const */

sys/arch/arm/ti/am18xx_aclk.c

55

struct clk *sc_parent_clk;

sys/arch/arm/ti/am18xx_aclk.c

60

static struct clk * am18xx_aclk_decode(device_t, int, const void *, size_t);

sys/arch/arm/ti/am18xx_aclk.c

61

static struct clk * am18xx_aclk_clk_get(void *, const char *);

sys/arch/arm/ti/am18xx_aclk.c

62

static u_int am18xx_aclk_clk_get_rate(void *, struct clk *);

sys/arch/arm/ti/am18xx_aclk.c

63

static struct clk * am18xx_aclk_clk_get_parent(void *, struct clk *);

sys/arch/arm/ti/am18xx_aclk.c

72

static struct clk am18xx_aclk_async1_clk = {

sys/arch/arm/ti/am18xx_aclk.c

76

static struct clk am18xx_aclk_async3_clk = {

sys/arch/arm/ti/am18xx_aclk.c

82

.clk = &am18xx_aclk_async1_clk,

sys/arch/arm/ti/am18xx_aclk.c

86

.clk = &am18xx_aclk_async3_clk,

sys/arch/arm/ti/am18xx_ohci.c

52

struct clk *sc_clk;

sys/arch/arm/ti/am18xx_pllc.c

145

static struct clk *

sys/arch/arm/ti/am18xx_pllc.c

165

am18xx_pllc_clk_get_rate(void *priv, struct clk *clkp)

sys/arch/arm/ti/am18xx_pllc.c

168

struct am18xx_pllc_clk *clk = (struct am18xx_pllc_clk *)clkp;

sys/arch/arm/ti/am18xx_pllc.c

170

return clk->get_rate(sc, clk);

sys/arch/arm/ti/am18xx_pllc.c

173

static struct clk *

sys/arch/arm/ti/am18xx_pllc.c

174

am18xx_pllc_clk_get_parent(void *priv, struct clk *clkp)

sys/arch/arm/ti/am18xx_pllc.c

183

struct am18xx_pllc_clk *clk)

sys/arch/arm/ti/am18xx_pllc.c

197

if (clk->clk_index <= 2) {

sys/arch/arm/ti/am18xx_pllc.c

198

plldiv_regaddr = AM18XX_PLLC_PLLDIV1 + 4 * clk->clk_index;

sys/arch/arm/ti/am18xx_pllc.c

200

plldiv_regaddr = AM18XX_PLLC_PLLDIV4 + 4 * (clk->clk_index - 3);

sys/arch/arm/ti/am18xx_pllc.c

224

struct am18xx_pllc_clk *clk)

sys/arch/arm/ti/am18xx_pllc.c

229

static struct clk *

sys/arch/arm/ti/am18xx_pllc.c

49

struct clk clk_base; /* must be first */

sys/arch/arm/ti/am18xx_pllc.c

67

struct clk *sc_ref_clk;

sys/arch/arm/ti/am18xx_pllc.c

76

static struct clk * am18xx_pllc_decode(device_t, int, const void *, size_t);

sys/arch/arm/ti/am18xx_pllc.c

77

static struct clk * am18xx_pllc_clk_get(void *, const char *);

sys/arch/arm/ti/am18xx_pllc.c

78

static u_int am18xx_pllc_clk_get_rate(void *, struct clk *);

sys/arch/arm/ti/am18xx_pllc.c

79

static struct clk * am18xx_pllc_clk_get_parent(void *, struct clk *);

sys/arch/arm/ti/am18xx_psc.c

189

struct am18xx_psc_clk *clk, uint32_t state)

sys/arch/arm/ti/am18xx_psc.c

192

uint32_t mdctl_reg = AM18XX_PSC_MDCTL0 + 4*clk->clk_index;

sys/arch/arm/ti/am18xx_psc.c

201

static struct clk *

sys/arch/arm/ti/am18xx_psc.c

215

am18xx_psc_clk_get_rate(void *priv, struct clk *clkp)

sys/arch/arm/ti/am18xx_psc.c

217

struct am18xx_psc_clk *clk = (struct am18xx_psc_clk *)clkp;

sys/arch/arm/ti/am18xx_psc.c

220

return clk_get_rate(clk->u.clk_parent);

sys/arch/arm/ti/am18xx_psc.c

224

am18xx_psc_clk_enable(void *priv, struct clk *clkp)

sys/arch/arm/ti/am18xx_psc.c

227

struct am18xx_psc_clk *clk = (struct am18xx_psc_clk *)clkp;

sys/arch/arm/ti/am18xx_psc.c

231

clk->clk_refcount += 1;

sys/arch/arm/ti/am18xx_psc.c

233

am18xx_psc_clk_transition(sc, clk, AM18XX_PSC_MDCTL_ENABLE);

sys/arch/arm/ti/am18xx_psc.c

241

am18xx_psc_clk_disable(void *priv, struct clk *clkp)

sys/arch/arm/ti/am18xx_psc.c

244

struct am18xx_psc_clk *clk = (struct am18xx_psc_clk *)clkp;

sys/arch/arm/ti/am18xx_psc.c

248

KASSERT(clk->clk_refcount > 0);

sys/arch/arm/ti/am18xx_psc.c

249

clk->clk_refcount -= 1;

sys/arch/arm/ti/am18xx_psc.c

251

if (clk->clk_refcount == 0) {

sys/arch/arm/ti/am18xx_psc.c

252

am18xx_psc_clk_transition(sc, clk, AM18XX_PSC_MDCTL_DISABLE);

sys/arch/arm/ti/am18xx_psc.c

260

static struct clk *

sys/arch/arm/ti/am18xx_psc.c

261

am18xx_psc_clk_get_parent(void *priv, struct clk *clkp)

sys/arch/arm/ti/am18xx_psc.c

263

struct am18xx_psc_clk *clk = (struct am18xx_psc_clk *)clkp;

sys/arch/arm/ti/am18xx_psc.c

265

return clk->u.clk_parent;

sys/arch/arm/ti/am18xx_psc.c

268

static struct clk *

sys/arch/arm/ti/am18xx_psc.c

281

struct am18xx_psc_clk *clk = &sc->sc_clks[clock_index];

sys/arch/arm/ti/am18xx_psc.c

283

return &clk->clk_base;

sys/arch/arm/ti/am18xx_psc.c

333

struct clk *parent_clk =

sys/arch/arm/ti/am18xx_psc.c

52

struct clk clk_base; /* must be first */

sys/arch/arm/ti/am18xx_psc.c

56

struct clk *clk_parent;

sys/arch/arm/ti/am18xx_psc.c

79

static struct clk * am18xx_psc_decode(device_t, int, const void *, size_t);

sys/arch/arm/ti/am18xx_psc.c

80

static struct clk * am18xx_psc_clk_get(void *, const char *);

sys/arch/arm/ti/am18xx_psc.c

81

static u_int am18xx_psc_clk_get_rate(void *, struct clk *);

sys/arch/arm/ti/am18xx_psc.c

82

static int am18xx_psc_clk_enable(void *, struct clk *);

sys/arch/arm/ti/am18xx_psc.c

83

static int am18xx_psc_clk_disable(void *, struct clk *);

sys/arch/arm/ti/am18xx_psc.c

84

static struct clk * am18xx_psc_clk_get_parent(void *, struct clk *);

sys/arch/arm/ti/am18xx_usbphy.c

52

struct clk *phy_clk48; /* must be first */

sys/arch/arm/ti/am18xx_usbphyclk.c

182

am18xx_usbphyclk_clk_enable(void *priv, struct clk *clkp)

sys/arch/arm/ti/am18xx_usbphyclk.c

227

am18xx_usbphyclk_clk_disable(void *priv, struct clk *clkp)

sys/arch/arm/ti/am18xx_usbphyclk.c

271

static struct clk *

sys/arch/arm/ti/am18xx_usbphyclk.c

286

am18xx_usbphyclk_clk_get_rate(void *priv, struct clk *clkp)

sys/arch/arm/ti/am18xx_usbphyclk.c

308

static struct clk *

sys/arch/arm/ti/am18xx_usbphyclk.c

309

am18xx_usbphyclk_clk_get_parent(void *priv, struct clk *clkp)

sys/arch/arm/ti/am18xx_usbphyclk.c

316

static struct clk *

sys/arch/arm/ti/am18xx_usbphyclk.c

57

struct clk clk_base; /* must be first */

sys/arch/arm/ti/am18xx_usbphyclk.c

65

struct clk *sc_ref_clk;

sys/arch/arm/ti/am18xx_usbphyclk.c

66

struct clk *sc_phy_logic_clk;

sys/arch/arm/ti/am18xx_usbphyclk.c

73

static struct clk *am18xx_usbphyclk_decode(device_t, int, const void *, size_t);

sys/arch/arm/ti/am18xx_usbphyclk.c

74

static struct clk *am18xx_usbphyclk_clk_get(void *, const char *);

sys/arch/arm/ti/am18xx_usbphyclk.c

75

static u_int am18xx_usbphyclk_clk_get_rate(void *, struct clk *);

sys/arch/arm/ti/am18xx_usbphyclk.c

76

static struct clk *am18xx_usbphyclk_clk_get_parent(void *, struct clk *);

sys/arch/arm/ti/am18xx_usbphyclk.c

77

static int am18xx_usbphyclk_clk_enable(void *, struct clk *);

sys/arch/arm/ti/am18xx_usbphyclk.c

78

static int am18xx_usbphyclk_clk_disable(void *, struct clk *);

sys/arch/arm/ti/am3_prcm.c

206

static struct clk *

sys/arch/arm/ti/omap4_prcm.c

234

static struct clk *

sys/arch/arm/ti/ti_comp_clock.c

123

static struct clk *

sys/arch/arm/ti/ti_comp_clock.c

132

static struct clk *

sys/arch/arm/ti/ti_comp_clock.c

141

ti_comp_clock_put(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_comp_clock.c

146

ti_comp_clock_get_rate(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_comp_clock.c

148

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/arm/ti/ti_comp_clock.c

157

ti_comp_clock_enable(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_comp_clock.c

160

struct clk *clk_gate = fdtbus_clock_get_index(sc->sc_phandle, 0);

sys/arch/arm/ti/ti_comp_clock.c

166

ti_comp_clock_disable(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_comp_clock.c

169

struct clk *clk_gate = fdtbus_clock_get_index(sc->sc_phandle, 0);

sys/arch/arm/ti/ti_comp_clock.c

174

static struct clk *

sys/arch/arm/ti/ti_comp_clock.c

175

ti_comp_clock_get_parent(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_comp_clock.c

183

ti_comp_clock_set_parent(void *priv, struct clk *clk, struct clk *parent_clk)

sys/arch/arm/ti/ti_comp_clock.c

185

return clk_set_parent(clk, parent_clk);

sys/arch/arm/ti/ti_comp_clock.c

46

static struct clk *ti_comp_clock_decode(device_t, int, const void *, size_t);

sys/arch/arm/ti/ti_comp_clock.c

52

static struct clk *ti_comp_clock_get(void *, const char *);

sys/arch/arm/ti/ti_comp_clock.c

53

static void ti_comp_clock_put(void *, struct clk *);

sys/arch/arm/ti/ti_comp_clock.c

54

static u_int ti_comp_clock_get_rate(void *, struct clk *);

sys/arch/arm/ti/ti_comp_clock.c

55

static int ti_comp_clock_enable(void *, struct clk *);

sys/arch/arm/ti/ti_comp_clock.c

56

static int ti_comp_clock_disable(void *, struct clk *);

sys/arch/arm/ti/ti_comp_clock.c

57

static struct clk *ti_comp_clock_get_parent(void *, struct clk *);

sys/arch/arm/ti/ti_comp_clock.c

58

static int ti_comp_clock_set_parent(void *, struct clk *, struct clk *);

sys/arch/arm/ti/ti_comp_clock.c

75

struct clk sc_clk;

sys/arch/arm/ti/ti_div_clock.c

134

static struct clk *

sys/arch/arm/ti/ti_div_clock.c

143

static struct clk *

sys/arch/arm/ti/ti_div_clock.c

152

ti_div_clock_put(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_div_clock.c

157

ti_div_clock_enable(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_div_clock.c

159

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/arm/ti/ti_div_clock.c

165

ti_div_clock_get_rate(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_div_clock.c

168

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/arm/ti/ti_div_clock.c

207

static struct clk *

sys/arch/arm/ti/ti_div_clock.c

208

ti_div_clock_get_parent(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_div_clock.c

51

static struct clk *ti_div_clock_decode(device_t, int, const void *, size_t);

sys/arch/arm/ti/ti_div_clock.c

57

static struct clk *ti_div_clock_get(void *, const char *);

sys/arch/arm/ti/ti_div_clock.c

58

static void ti_div_clock_put(void *, struct clk *);

sys/arch/arm/ti/ti_div_clock.c

59

static int ti_div_clock_enable(void *, struct clk *);

sys/arch/arm/ti/ti_div_clock.c

60

static u_int ti_div_clock_get_rate(void *, struct clk *);

sys/arch/arm/ti/ti_div_clock.c

61

static struct clk *ti_div_clock_get_parent(void *, struct clk *);

sys/arch/arm/ti/ti_div_clock.c

78

struct clk sc_clk;

sys/arch/arm/ti/ti_dpll_clock.c

106

static u_int omap4_dpll_clock_get_rate(void *, struct clk *);

sys/arch/arm/ti/ti_dpll_clock.c

155

struct clk sc_clk;

sys/arch/arm/ti/ti_dpll_clock.c

225

static struct clk *

sys/arch/arm/ti/ti_dpll_clock.c

234

static struct clk *

sys/arch/arm/ti/ti_dpll_clock.c

243

ti_dpll_clock_put(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_dpll_clock.c

248

ti_dpll_clock_get_rate(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_dpll_clock.c

251

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/arm/ti/ti_dpll_clock.c

267

static struct clk *

sys/arch/arm/ti/ti_dpll_clock.c

268

ti_dpll_clock_get_parent(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_dpll_clock.c

277

am3_dpll_clock_set_rate(void *priv, struct clk *clk, u_int rate)

sys/arch/arm/ti/ti_dpll_clock.c

280

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/arm/ti/ti_dpll_clock.c

319

omap3_dpll_clock_set_rate(void *priv, struct clk *clk, u_int rate)

sys/arch/arm/ti/ti_dpll_clock.c

322

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/arm/ti/ti_dpll_clock.c

358

omap3_dpll_core_clock_get_rate(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_dpll_clock.c

361

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/arm/ti/ti_dpll_clock.c

379

omap4_dpll_clock_get_rate(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_dpll_clock.c

382

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/arm/ti/ti_dpll_clock.c

66

static struct clk *ti_dpll_clock_decode(device_t, int, const void *, size_t);

sys/arch/arm/ti/ti_dpll_clock.c

72

static struct clk *ti_dpll_clock_get(void *, const char *);

sys/arch/arm/ti/ti_dpll_clock.c

73

static void ti_dpll_clock_put(void *, struct clk *);

sys/arch/arm/ti/ti_dpll_clock.c

74

static u_int ti_dpll_clock_get_rate(void *, struct clk *);

sys/arch/arm/ti/ti_dpll_clock.c

75

static struct clk *ti_dpll_clock_get_parent(void *, struct clk *);

sys/arch/arm/ti/ti_dpll_clock.c

77

static int am3_dpll_clock_set_rate(void *, struct clk *, u_int);

sys/arch/arm/ti/ti_dpll_clock.c

87

static int omap3_dpll_clock_set_rate(void *, struct clk *, u_int);

sys/arch/arm/ti/ti_dpll_clock.c

97

static u_int omap3_dpll_core_clock_get_rate(void *, struct clk *);

sys/arch/arm/ti/ti_ehci.c

78

struct clk *clk;

sys/arch/arm/ti/ti_ehci.c

92

for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)

sys/arch/arm/ti/ti_ehci.c

93

if (clk_enable(clk) != 0) {

sys/arch/arm/ti/ti_gate_clock.c

143

static struct clk *

sys/arch/arm/ti/ti_gate_clock.c

152

static struct clk *

sys/arch/arm/ti/ti_gate_clock.c

161

ti_gate_clock_put(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_gate_clock.c

166

ti_gate_clock_enable(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_gate_clock.c

169

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/arm/ti/ti_gate_clock.c

180

ti_gate_clock_disable(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_gate_clock.c

183

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/arm/ti/ti_gate_clock.c

193

static struct clk *

sys/arch/arm/ti/ti_gate_clock.c

194

ti_gate_clock_get_parent(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_gate_clock.c

46

static struct clk *ti_gate_clock_decode(device_t, int, const void *, size_t);

sys/arch/arm/ti/ti_gate_clock.c

52

static struct clk *ti_gate_clock_get(void *, const char *);

sys/arch/arm/ti/ti_gate_clock.c

53

static void ti_gate_clock_put(void *, struct clk *);

sys/arch/arm/ti/ti_gate_clock.c

54

static int ti_gate_clock_enable(void *, struct clk *);

sys/arch/arm/ti/ti_gate_clock.c

55

static int ti_gate_clock_disable(void *, struct clk *);

sys/arch/arm/ti/ti_gate_clock.c

56

static struct clk *ti_gate_clock_get_parent(void *, struct clk *);

sys/arch/arm/ti/ti_gate_clock.c

73

struct clk sc_clk;

sys/arch/arm/ti/ti_lcdc.h

76

struct clk *sc_clk;

sys/arch/arm/ti/ti_mux_clock.c

150

static struct clk *

sys/arch/arm/ti/ti_mux_clock.c

159

static struct clk *

sys/arch/arm/ti/ti_mux_clock.c

168

ti_mux_clock_put(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_mux_clock.c

173

ti_mux_clock_get_rate(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_mux_clock.c

175

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/arm/ti/ti_mux_clock.c

183

static struct clk *

sys/arch/arm/ti/ti_mux_clock.c

184

ti_mux_clock_get_parent(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_mux_clock.c

197

ti_mux_clock_set_parent(void *priv, struct clk *clk, struct clk *parent_clk)

sys/arch/arm/ti/ti_mux_clock.c

45

static struct clk *ti_mux_clock_decode(device_t, int, const void *, size_t);

sys/arch/arm/ti/ti_mux_clock.c

51

static struct clk *ti_mux_clock_get(void *, const char *);

sys/arch/arm/ti/ti_mux_clock.c

52

static void ti_mux_clock_put(void *, struct clk *);

sys/arch/arm/ti/ti_mux_clock.c

53

static u_int ti_mux_clock_get_rate(void *, struct clk *);

sys/arch/arm/ti/ti_mux_clock.c

54

static struct clk *ti_mux_clock_get_parent(void *, struct clk *);

sys/arch/arm/ti/ti_mux_clock.c

55

static int ti_mux_clock_set_parent(void *, struct clk *, struct clk *);

sys/arch/arm/ti/ti_mux_clock.c

72

struct clk sc_clk;

sys/arch/arm/ti/ti_omaptimer.c

188

struct clk *hwmod;

sys/arch/arm/ti/ti_prcm.c

100

return clk->set_rate(sc, clk, rate);

sys/arch/arm/ti/ti_prcm.c

106

ti_prcm_clock_enable(void *priv, struct clk *clkp)

sys/arch/arm/ti/ti_prcm.c

109

struct ti_prcm_clk *clk = (struct ti_prcm_clk *)clkp;

sys/arch/arm/ti/ti_prcm.c

110

struct clk *clkp_parent;

sys/arch/arm/ti/ti_prcm.c

120

if (clk->enable)

sys/arch/arm/ti/ti_prcm.c

121

error = clk->enable(sc, clk, 1);

sys/arch/arm/ti/ti_prcm.c

127

ti_prcm_clock_disable(void *priv, struct clk *clkp)

sys/arch/arm/ti/ti_prcm.c

130

struct ti_prcm_clk *clk = (struct ti_prcm_clk *)clkp;

sys/arch/arm/ti/ti_prcm.c

133

if (clk->enable)

sys/arch/arm/ti/ti_prcm.c

134

error = clk->enable(sc, clk, 0);

sys/arch/arm/ti/ti_prcm.c

140

ti_prcm_clock_set_parent(void *priv, struct clk *clkp,

sys/arch/arm/ti/ti_prcm.c

141

struct clk *clkp_parent)

sys/arch/arm/ti/ti_prcm.c

144

struct ti_prcm_clk *clk = (struct ti_prcm_clk *)clkp;

sys/arch/arm/ti/ti_prcm.c

146

if (clk->set_parent == NULL)

sys/arch/arm/ti/ti_prcm.c

149

return clk->set_parent(sc, clk, clkp_parent->name);

sys/arch/arm/ti/ti_prcm.c

152

static struct clk *

sys/arch/arm/ti/ti_prcm.c

153

ti_prcm_clock_get_parent(void *priv, struct clk *clkp)

sys/arch/arm/ti/ti_prcm.c

156

struct ti_prcm_clk *clk = (struct ti_prcm_clk *)clkp;

sys/arch/arm/ti/ti_prcm.c

160

if (clk->get_parent == NULL)

sys/arch/arm/ti/ti_prcm.c

163

parent = clk->get_parent(sc, clk);

sys/arch/arm/ti/ti_prcm.c

226

struct clk *

sys/arch/arm/ti/ti_prcm.c

266

struct clk *clk;

sys/arch/arm/ti/ti_prcm.c

268

clk = ti_prcm_get_hwmod(phandle, index);

sys/arch/arm/ti/ti_prcm.c

269

if (clk == NULL)

sys/arch/arm/ti/ti_prcm.c

272

return clk_enable(clk);

sys/arch/arm/ti/ti_prcm.c

46

static struct clk *

sys/arch/arm/ti/ti_prcm.c

50

struct ti_prcm_clk *clk;

sys/arch/arm/ti/ti_prcm.c

52

clk = ti_prcm_clock_find(sc, name);

sys/arch/arm/ti/ti_prcm.c

53

if (clk == NULL)

sys/arch/arm/ti/ti_prcm.c

56

return &clk->base;

sys/arch/arm/ti/ti_prcm.c

60

ti_prcm_clock_put(void *priv, struct clk *clk)

sys/arch/arm/ti/ti_prcm.c

65

ti_prcm_clock_get_rate(void *priv, struct clk *clkp)

sys/arch/arm/ti/ti_prcm.c

68

struct ti_prcm_clk *clk = (struct ti_prcm_clk *)clkp;

sys/arch/arm/ti/ti_prcm.c

69

struct clk *clkp_parent;

sys/arch/arm/ti/ti_prcm.c

71

if (clk->get_rate)

sys/arch/arm/ti/ti_prcm.c

72

return clk->get_rate(sc, clk);

sys/arch/arm/ti/ti_prcm.c

76

aprint_error("%s: no parent for %s\n", __func__, clk->base.name);

sys/arch/arm/ti/ti_prcm.c

84

ti_prcm_clock_set_rate(void *priv, struct clk *clkp, u_int rate)

sys/arch/arm/ti/ti_prcm.c

87

struct ti_prcm_clk *clk = (struct ti_prcm_clk *)clkp;

sys/arch/arm/ti/ti_prcm.c

88

struct clk *clkp_parent;

sys/arch/arm/ti/ti_prcm.c

93

aprint_error("%s: no parent for %s\n", __func__, clk->base.name);

sys/arch/arm/ti/ti_prcm.c

99

if (clk->set_rate)

sys/arch/arm/ti/ti_prcm.h

176

struct clk * ti_prcm_get_hwmod(const int, u_int);

sys/arch/arm/ti/ti_prcm.h

66

struct clk base;

sys/arch/arm/ti/ti_wdt.c

214

struct clk *clk;

sys/arch/arm/ti/ti_wdt.c

223

clk = ti_prcm_get_hwmod(phandle, 0);

sys/arch/arm/ti/ti_wdt.c

224

if (clk == NULL || clk_enable(clk) != 0) {

sys/arch/arm/ti/ti_wdt.c

235

sc->sc_rate = clk_get_rate(clk);

sys/arch/arm/xilinx/zynq7000_clkc.c

129

static u_int zynq7000_clkc_clk_get_rate(void *, struct clk *);

sys/arch/arm/xilinx/zynq7000_clkc.c

139

struct clk sc_clk[num_clkid];

sys/arch/arm/xilinx/zynq7000_clkc.c

148

static struct clk *

sys/arch/arm/xilinx/zynq7000_clkc.c

164

zynq7000_clkc_clk_put(void *priv, struct clk *clk)

sys/arch/arm/xilinx/zynq7000_clkc.c

208

zynq7000_clkc_clk_get_rate(void *priv, struct clk *clk)

sys/arch/arm/xilinx/zynq7000_clkc.c

214

if (clk == &sc->sc_clk[clkid_armpll]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

216

} else if (clk == &sc->sc_clk[clkid_iopll]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

218

} else if (clk == &sc->sc_clk[clkid_cpu_6or4x]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

226

} else if (clk == &sc->sc_clk[clkid_cpu_3or2x]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

234

} else if (clk == &sc->sc_clk[clkid_cpu_2x]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

238

} else if (clk == &sc->sc_clk[clkid_cpu_1x]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

245

} else if (clk == &sc->sc_clk[clkid_sdio0] ||

sys/arch/arm/xilinx/zynq7000_clkc.c

246

clk == &sc->sc_clk[clkid_sdio1]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

248

} else if (clk == &sc->sc_clk[clkid_uart0] ||

sys/arch/arm/xilinx/zynq7000_clkc.c

249

clk == &sc->sc_clk[clkid_uart1]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

251

} else if (clk == &sc->sc_clk[clkid_pcap]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

253

} else if (clk == &sc->sc_clk[clkid_uart0_aper] ||

sys/arch/arm/xilinx/zynq7000_clkc.c

254

clk == &sc->sc_clk[clkid_uart1_aper] ||

sys/arch/arm/xilinx/zynq7000_clkc.c

255

clk == &sc->sc_clk[clkid_i2c0_aper] ||

sys/arch/arm/xilinx/zynq7000_clkc.c

256

clk == &sc->sc_clk[clkid_i2c1_aper]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

266

zynq7000_clkc_clk_enable(void *priv, struct clk *clk)

sys/arch/arm/xilinx/zynq7000_clkc.c

272

if (clk == &sc->sc_clk[clkid_cpu_1x]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

275

} else if (clk == &sc->sc_clk[clkid_cpu_2x]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

278

} else if (clk == &sc->sc_clk[clkid_cpu_3or2x]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

281

} else if (clk == &sc->sc_clk[clkid_cpu_6or4x]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

284

} else if (clk == &sc->sc_clk[clkid_sdio0]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

287

} else if (clk == &sc->sc_clk[clkid_sdio1]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

290

} else if (clk == &sc->sc_clk[clkid_uart0]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

293

} else if (clk == &sc->sc_clk[clkid_uart1]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

296

} else if (clk == &sc->sc_clk[clkid_pcap]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

299

} else if (clk == &sc->sc_clk[clkid_sdio0_aper]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

302

} else if (clk == &sc->sc_clk[clkid_sdio1_aper]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

305

} else if (clk == &sc->sc_clk[clkid_uart0_aper]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

308

} else if (clk == &sc->sc_clk[clkid_uart1_aper]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

311

} else if (clk == &sc->sc_clk[clkid_i2c0_aper]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

314

} else if (clk == &sc->sc_clk[clkid_i2c1_aper]) {

sys/arch/arm/xilinx/zynq7000_clkc.c

330

zynq7000_clkc_clk_disable(void *priv, struct clk *clk)

sys/arch/arm/xilinx/zynq7000_clkc.c

343

static struct clk *

sys/arch/arm/xilinx/zynq_xadc.c

226

zynq_xadc_init(struct zynq_xadc_softc *sc, struct clk *clk)

sys/arch/arm/xilinx/zynq_xadc.c

304

struct clk *clk;

sys/arch/arm/xilinx/zynq_xadc.c

313

clk = fdtbus_clock_get_index(phandle, 0);

sys/arch/arm/xilinx/zynq_xadc.c

314

if (clk == NULL || clk_enable(clk) != 0) {

sys/arch/arm/xilinx/zynq_xadc.c

330

zynq_xadc_init(sc, clk);

sys/arch/arm/xscale/pxa2x0.c

493

pxa2x0_clkman_config(u_int clk, bool enable)

sys/arch/arm/xscale/pxa2x0.c

506

rv &= ~clk;

sys/arch/arm/xscale/pxa2x0.c

508

rv |= clk;

sys/arch/arm/xscale/pxa2x0.c

513

rv &= ~clk;

sys/arch/arm/xscale/pxa2x0.c

515

rv |= clk;

sys/arch/evbarm/rpi/vcprop.h

290

struct vcprop_clock clk[VCPROP_MAXCLOCKS];

sys/arch/evbarm/stand/board/sscom.c

192

long clk;

sys/arch/evbarm/stand/board/sscom.c

211

clk = (XTAL_CLK * 1000000 * (8 + mdiv)) / ((pdiv + 2) << sdiv);

sys/arch/evbarm/stand/board/sscom.c

213

clk = (XTAL_CLK * (8 + mdiv)) / ((pdiv + 2) << sdiv);

sys/arch/evbarm/stand/board/sscom.c

219

clk /= 2;

sys/arch/evbarm/stand/board/sscom.c

221

clk /= 2;

sys/arch/evbarm/stand/board/sscom.c

223

return clk;

sys/arch/evbarm/stand/boot2440/s3csdi.c

112

int clk = pclk/1000; /*Peripheral bus clock in KHz*/

sys/arch/evbarm/stand/boot2440/s3csdi.c

115

clk = (clk / 1000) * 1000;

sys/arch/evbarm/stand/boot2440/s3csdi.c

126

if ( clk / div <= freq) {

sys/arch/evbarm/stand/boot2440/s3csdi.c

127

DPRINTF(("Using divisor %d: %d/%d = %d\n", div, clk,

sys/arch/evbarm/stand/boot2440/s3csdi.c

128

div, clk/div));

sys/arch/evbmips/loongson/loongson_clock.c

100

cycles[clk] =

sys/arch/evbmips/loongson/loongson_clock.c

101

(rscale(curcpu()->ci_cpu_freq, clk) + hz / 2) / (2 * hz);

sys/arch/evbmips/loongson/loongson_clock.c

104

for (clk = 1; clk < 8; clk++) {

sys/arch/evbmips/loongson/loongson_clock.c

105

aprint_normal("frequencies: %d/8: %d\n", clk + 1,

sys/arch/evbmips/loongson/loongson_clock.c

106

sc_scale[clk]);

sys/arch/evbmips/loongson/loongson_clock.c

87

int clk;

sys/arch/evbmips/loongson/loongson_clock.c

98

for (clk = 1; clk < 8; clk++) {

sys/arch/evbmips/loongson/loongson_clock.c

99

sc_scale[clk] = rscale(curcpu()->ci_cpu_freq / 1000000, clk);

sys/arch/hp300/hp300/clock.c

109

volatile struct clkreg *clk;

sys/arch/hp300/hp300/clock.c

114

clk = (volatile struct clkreg *)clkstd[0];

sys/arch/hp300/hp300/clock.c

127

clk->clk_cr2 = CLK_CR1;

sys/arch/hp300/hp300/clock.c

128

clk->clk_cr1 = CLK_RESET;

sys/arch/hp300/hp300/clock.c

136

__asm volatile(" movpw %0,%1@(5)" : : "d" (intvl), "a" (clk));

sys/arch/hp300/hp300/clock.c

139

clk->clk_cr2 = CLK_CR1;

sys/arch/hp300/hp300/clock.c

140

clk->clk_cr1 = CLK_IENAB;

sys/arch/hp300/hp300/clock.c

145

csr = clk->clk_sr;

sys/arch/hp300/hp300/clock.c

151

"a" (clk), "d" (intvl));

sys/arch/hp300/hp300/clock.c

160

csr = clk->clk_sr;

sys/arch/hp300/hp300/clock.c

163

__asm volatile(" movpw %0@(5),%1" : : "a" (clk), "d" (intvl));

sys/arch/hp300/hp300/clock.c

171

clk->clk_cr2 = CLK_CR1;

sys/arch/hp300/hp300/clock.c

172

clk->clk_cr1 = CLK_RESET;

sys/arch/hp300/hp300/clock.c

192

volatile struct clkreg *clk;

sys/arch/hp300/hp300/clock.c

203

clk = (volatile struct clkreg *)clkstd[0];

sys/arch/hp300/hp300/clock.c

249

clk->clk_cr2 = CLK_CR1;

sys/arch/hp300/hp300/clock.c

250

clk->clk_cr1 = CLK_RESET;

sys/arch/hp300/hp300/clock.c

251

__asm volatile(" movpw %0,%1@(5)" : : "d" (intvl), "a" (clk));

sys/arch/hp300/hp300/clock.c

252

__asm volatile(" movpw %0,%1@(9)" : : "d" (0), "a" (clk));

sys/arch/hp300/hp300/clock.c

253

__asm volatile(" movpw %0,%1@(13)" : : "d" (statint), "a" (clk));

sys/arch/hp300/hp300/clock.c

254

clk->clk_cr2 = CLK_CR1;

sys/arch/hp300/hp300/clock.c

255

clk->clk_cr1 = CLK_IENAB;

sys/arch/hp300/hp300/clock.c

256

clk->clk_cr2 = CLK_CR3;

sys/arch/hp300/hp300/clock.c

257

clk->clk_cr3 = CLK_IENAB;

sys/arch/hp300/hp300/clock.c

286

volatile struct clkreg *clk;

sys/arch/hp300/hp300/clock.c

289

clk = (volatile struct clkreg *)clkstd[0];

sys/arch/hp300/hp300/clock.c

303

__asm volatile(" clrl %0; movpw %1@(13),%0" : "=d" (r) : "a" (clk));

sys/arch/hp300/hp300/clock.c

306

__asm volatile(" movpw %0,%1@(13)" : : "d" (newint), "a" (clk));

sys/arch/hp300/hp300/clock.c

314

volatile struct clkreg *clk;

sys/arch/hp300/hp300/clock.c

319

clk = (volatile struct clkreg *)clkstd[0];

sys/arch/hp300/hp300/clock.c

325

: "=d" (count) : "a" (clk));

sys/arch/ia64/ia64/interrupt.c

110

clk = ci->ci_clock;

sys/arch/ia64/ia64/interrupt.c

111

delta = itc - clk;

sys/arch/ia64/ia64/interrupt.c

120

clk += ia64_clock_reload;

sys/arch/ia64/ia64/interrupt.c

132

ci->ci_clock = clk;

sys/arch/ia64/ia64/interrupt.c

80

uint64_t adj, clk, itc;

sys/arch/luna68k/dev/psgpam.c

388

int clk;

sys/arch/luna68k/dev/psgpam.c

419

clk = sc->sc_xp_cycle_clk + i * sc->sc_xp_rept_clk;

sys/arch/luna68k/dev/psgpam.c

420

freq = XP_CPU_FREQ / clk;

sys/arch/luna68k/dev/psgpam.c

429

clk = sc->sc_xp_cycle_clk + i * sc->sc_xp_rept_clk;

sys/arch/luna68k/dev/psgpam.c

430

freq = XP_CPU_FREQ / clk;

sys/arch/mac68k/dev/zs.c

291

xcs->cs_clocks[0].clk = PCLK;

sys/arch/mac68k/dev/zs.c

299

xcs->cs_clocks[1].clk = mac68k_machine.modem_dcd_clk;

sys/arch/mac68k/dev/zs.c

300

xcs->cs_clocks[2].clk = mac68k_machine.modem_cts_clk;

sys/arch/mac68k/dev/zs.c

310

xcs->cs_clocks[1].clk = mac68k_machine.print_dcd_clk;

sys/arch/mac68k/dev/zs.c

311

xcs->cs_clocks[2].clk = mac68k_machine.print_cts_clk;

sys/arch/mac68k/dev/zs.c

313

if (xcs->cs_clocks[1].clk)

sys/arch/mac68k/dev/zs.c

315

if (xcs->cs_clocks[2].clk)

sys/arch/mac68k/dev/zs.c

320

xcs->cs_clocks[1].clk, xcs->cs_clocks[2].clk);

sys/arch/mac68k/dev/zs.c

521

if (xcs->cs_clocks[i].clk <= 0)

sys/arch/mac68k/dev/zs.c

525

tc1 = BPS_TO_TCONST(xcs->cs_clocks[i].clk >> 4, bps);

sys/arch/mac68k/dev/zs.c

527

rate1 = TCONST_TO_BPS(xcs->cs_clocks[i].clk >> 4, tc1);

sys/arch/mac68k/dev/zs.c

544

int b0 = xcs->cs_clocks[i].clk, e0 = abs(b0-bps);

sys/arch/mac68k/dev/zs.c

591

cs->cs_brg_clk = xcs->cs_clocks[i].clk >> 4;

sys/arch/mac68k/include/z8530var.h

92

long clk; /* clock rate, in MHz, present on signal line */

sys/arch/macppc/dev/zs.c

321

xcs->cs_clocks[0].clk = PCLK;

sys/arch/macppc/dev/zs.c

331

xcs->cs_clocks[1].clk = 0;

sys/arch/macppc/dev/zs.c

332

xcs->cs_clocks[2].clk = 0;

sys/arch/macppc/dev/zs.c

344

xcs->cs_clocks[1].clk = 0;

sys/arch/macppc/dev/zs.c

345

xcs->cs_clocks[2].clk = 0;

sys/arch/macppc/dev/zs.c

347

if (xcs->cs_clocks[1].clk)

sys/arch/macppc/dev/zs.c

349

if (xcs->cs_clocks[2].clk)

sys/arch/macppc/dev/zs.c

585

if (xcs->cs_clocks[i].clk <= 0)

sys/arch/macppc/dev/zs.c

589

tc1 = BPS_TO_TCONST(xcs->cs_clocks[i].clk >> 4, bps);

sys/arch/macppc/dev/zs.c

591

rate1 = TCONST_TO_BPS(xcs->cs_clocks[i].clk >> 4, tc1);

sys/arch/macppc/dev/zs.c

608

int b0 = xcs->cs_clocks[i].clk, e0 = abs(b0-bps);

sys/arch/macppc/dev/zs.c

655

cs->cs_brg_clk = xcs->cs_clocks[i].clk >> 4;

sys/arch/macppc/include/z8530var.h

93

long clk; /* clock rate, in MHz, present on signal line */

sys/arch/mips/cavium/dev/if_cnmac.c

232

prop_object_t clk;

sys/arch/mips/cavium/dev/if_cnmac.c

353

clk = prop_dictionary_get(dict, "rgmii-tx");

sys/arch/mips/cavium/dev/if_cnmac.c

354

if (clk)

sys/arch/mips/cavium/dev/if_cnmac.c

356

prop_number_signed_value(clk);

sys/arch/mips/cavium/dev/if_cnmac.c

357

clk = prop_dictionary_get(dict, "rgmii-rx");

sys/arch/mips/cavium/dev/if_cnmac.c

358

if (clk)

sys/arch/mips/cavium/dev/if_cnmac.c

360

prop_number_signed_value(clk);

sys/arch/mips/cavium/dev/octeon_dwctwo.c

158

uint64_t clk;

sys/arch/mips/cavium/dev/octeon_dwctwo.c

199

clk = octeon_dwc2_reg_rd(sc, USBN_CLK_CTL_OFFSET);

sys/arch/mips/cavium/dev/octeon_dwctwo.c

200

clk |= USBN_CLK_CTL_POR;

sys/arch/mips/cavium/dev/octeon_dwctwo.c

201

clk &= ~(USBN_CLK_CTL_HRST | USBN_CLK_CTL_PRST |

sys/arch/mips/cavium/dev/octeon_dwctwo.c

208

clk &= ~(USBN_CLK_CTL_P_C_SEL | USBN_CLK_CTL_P_RTYPE |

sys/arch/mips/cavium/dev/octeon_dwctwo.c

215

clk &= ~(USBN_CLK_CTL_DIVIDE | USBN_CLK_CTL_DIVIDE2);

sys/arch/mips/cavium/dev/octeon_dwctwo.c

216

clk |= __SHIFTIN(0x4, USBN_CLK_CTL_DIVIDE) | /* XXXXXX magic 0x4 */

sys/arch/mips/cavium/dev/octeon_dwctwo.c

218

octeon_dwc2_reg_wr(sc, USBN_CLK_CTL_OFFSET, clk);

sys/arch/mips/cavium/dev/octeon_dwctwo.c

234

clk = octeon_dwc2_reg_rd(sc, USBN_CLK_CTL_OFFSET);

sys/arch/mips/cavium/dev/octeon_dwctwo.c

235

clk |= __SHIFTIN(0x4, USBN_CLK_CTL_DIVIDE); /* XXXXXX magic 0x4 */

sys/arch/mips/cavium/dev/octeon_dwctwo.c

236

octeon_dwc2_reg_wr(sc, USBN_CLK_CTL_OFFSET, clk);

sys/arch/mips/mips/mips_mcclock.c

104

clk[MC_REGA].datum = MC_BASE_32_KHz | MC_RATE_256_Hz;

sys/arch/mips/mips/mips_mcclock.c

105

clk[MC_REGB].datum = MC_REGB_BINARY|MC_REGB_24HR|MC_REGB_PIE| MC_REGB_SQWE;

sys/arch/mips/mips/mips_mcclock.c

111

clk[MC_REGA].datum = saved_rega;

sys/arch/mips/mips/mips_mcclock.c

112

clk[MC_REGB].datum = saved_regb;

sys/arch/mips/mips/mips_mcclock.c

145

volatile struct mcclock_pad32_clockdatum *clk = mcclock_addr;

sys/arch/mips/mips/mips_mcclock.c

148

junk = clk[MC_REGC].datum;

sys/arch/mips/mips/mips_mcclock.c

156

junk = clk[MC_REGC].datum;

sys/arch/mips/mips/mips_mcclock.c

167

junk = clk[MC_REGC].datum;

sys/arch/mips/mips/mips_mcclock.c

85

volatile struct mcclock_pad32_clockdatum *clk = (void *)mcclock_addr;

sys/arch/mips/mips/mips_mcclock.c

97

saved_rega = clk[MC_REGA].datum;

sys/arch/mips/mips/mips_mcclock.c

98

saved_regb = clk[MC_REGB].datum;

sys/arch/mvme68k/dev/sbicreg.h

132

#define SBIC_TIMEOUT(val,clk) ((((val) * (clk)) / 800) + 1)

sys/arch/news68k/dev/zs.c

190

int s, channel, clk;

sys/arch/news68k/dev/zs.c

196

clk = cf->cf_flags;

sys/arch/news68k/dev/zs.c

197

if (clk < 0 || clk >= NPCLK)

sys/arch/news68k/dev/zs.c

198

clk = 0;

sys/arch/news68k/dev/zs.c

234

cs->cs_brg_clk = pclk[clk] / 16;

sys/arch/riscv/sifive/fu540_prci.c

110

fu540_prci_clk_put(void *priv, struct clk *clk)

sys/arch/riscv/sifive/fu540_prci.c

131

fu540_prci_clk_get_rate(void *priv, struct clk *clk)

sys/arch/riscv/sifive/fu540_prci.c

136

if (clk == &sc->sc_clk[clkid_corepll] ||

sys/arch/riscv/sifive/fu540_prci.c

137

clk == &sc->sc_clk[clkid_tlclk]) {

sys/arch/riscv/sifive/fu540_prci.c

139

if (clk == &sc->sc_clk[clkid_tlclk]) {

sys/arch/riscv/sifive/fu540_prci.c

143

} else if (clk == &sc->sc_clk[clkid_ddrpll]) {

sys/arch/riscv/sifive/fu540_prci.c

145

} else if (clk == &sc->sc_clk[clkid_gemgxlpll]) {

sys/arch/riscv/sifive/fu540_prci.c

154

fu540_prci_clk_enable(void *priv, struct clk *clk)

sys/arch/riscv/sifive/fu540_prci.c

159

if (clk == &sc->sc_clk[clkid_corepll] ||

sys/arch/riscv/sifive/fu540_prci.c

160

clk == &sc->sc_clk[clkid_tlclk]) {

sys/arch/riscv/sifive/fu540_prci.c

163

} else if (clk == &sc->sc_clk[clkid_ddrpll]) {

sys/arch/riscv/sifive/fu540_prci.c

167

} else if (clk == &sc->sc_clk[clkid_gemgxlpll]) {

sys/arch/riscv/sifive/fu540_prci.c

178

fu540_prci_clk_disable(void *priv, struct clk *clk)

sys/arch/riscv/sifive/fu540_prci.c

191

static struct clk *

sys/arch/riscv/sifive/fu540_prci.c

228

struct clk *clk;

sys/arch/riscv/sifive/fu540_prci.c

245

clk = fdtbus_clock_get(phandle, "hfclk");

sys/arch/riscv/sifive/fu540_prci.c

246

if (clk == NULL) {

sys/arch/riscv/sifive/fu540_prci.c

250

sc->sc_hfclk = clk_get_rate(clk);

sys/arch/riscv/sifive/fu540_prci.c

252

clk = fdtbus_clock_get(phandle, "rtcclk");

sys/arch/riscv/sifive/fu540_prci.c

253

if (clk == NULL) {

sys/arch/riscv/sifive/fu540_prci.c

257

sc->sc_rtcclk = clk_get_rate(clk);

sys/arch/riscv/sifive/fu540_prci.c

68

static u_int fu540_prci_clk_get_rate(void *, struct clk *);

sys/arch/riscv/sifive/fu540_prci.c

80

struct clk sc_clk[num_clkid];

sys/arch/riscv/sifive/fu540_prci.c

94

static struct clk *

sys/arch/riscv/starfive/jh7100_clkc.c

429

static struct clk *

sys/arch/riscv/starfive/jh7100_clkc.c

492

struct clk * const osclk = fdtbus_clock_get(phandle, "osc_sys");

sys/arch/riscv/starfive/jh7100_clkc.c

499

struct clk * const oaclk = fdtbus_clock_get(phandle, "osc_aud");

sys/arch/riscv/starfive/jh7100_clkc.c

531

struct clk * const clk = &sc->sc_clk[id].jcc_clk;

sys/arch/riscv/starfive/jh7100_clkc.c

534

clk->name ? clk->name : "<none>", clk_get_rate(clk));

sys/arch/riscv/starfive/jh7110_clkc.c

1064

static struct clk *

sys/arch/riscv/starfive/jh7110_clkc.c

1154

struct clk * const clk = &sc->sc_clk[id].jcc_clk;

sys/arch/riscv/starfive/jh7110_clkc.c

1157

clk->name ? clk->name : "<none>", clk_get_rate(clk));

sys/arch/riscv/starfive/jh7110_pcie.c

410

struct clk *clk;

sys/arch/riscv/starfive/jh7110_pcie.c

413

(clk = fdtbus_clock_get_index(phsc->sc_phandle, c)) != NULL;

sys/arch/riscv/starfive/jh7110_pcie.c

415

if (clk_enable(clk) != 0) {

sys/arch/riscv/starfive/jh71x0_clkc.c

113

struct clk *clk = &jcc->jcc_clk;

sys/arch/riscv/starfive/jh71x0_clkc.c

120

return jh71x0_clkc_fixed_factor_set_parent_rate(clk, tmp);

sys/arch/riscv/starfive/jh71x0_clkc.c

221

struct clk * const clk = &jcc->jcc_clk;

sys/arch/riscv/starfive/jh71x0_clkc.c

222

struct clk * const clk_parent = clk_get_parent(clk);

sys/arch/riscv/starfive/jh71x0_clkc.c

244

struct clk * const clk = &jcc->jcc_clk;

sys/arch/riscv/starfive/jh71x0_clkc.c

245

struct clk * const clk_parent = clk_get_parent(clk);

sys/arch/riscv/starfive/jh71x0_clkc.c

290

struct clk * const clk = &jcc->jcc_clk;

sys/arch/riscv/starfive/jh71x0_clkc.c

291

struct clk * const clk_parent = clk_get_parent(clk);

sys/arch/riscv/starfive/jh71x0_clkc.c

315

struct clk * const clk = &jcc->jcc_clk;

sys/arch/riscv/starfive/jh71x0_clkc.c

316

struct clk * const clk_parent = clk_get_parent(clk);

sys/arch/riscv/starfive/jh71x0_clkc.c

410

struct clk * const clk = &jcc->jcc_clk;

sys/arch/riscv/starfive/jh71x0_clkc.c

411

struct clk * const clk_parent = clk_get_parent(clk);

sys/arch/riscv/starfive/jh71x0_clkc.c

433

struct clk * const clk = &jcc->jcc_clk;

sys/arch/riscv/starfive/jh71x0_clkc.c

434

struct clk * const clk_parent = clk_get_parent(clk);

sys/arch/riscv/starfive/jh71x0_clkc.c

514

static struct clk *

sys/arch/riscv/starfive/jh71x0_clkc.c

531

jh71x0_clkc_put(void *priv, struct clk *clk)

sys/arch/riscv/starfive/jh71x0_clkc.c

537

jh71x0_clkc_set_rate(void *priv, struct clk *clk, u_int rate)

sys/arch/riscv/starfive/jh71x0_clkc.c

541

container_of(clk, struct jh71x0_clkc_clk, jcc_clk);

sys/arch/riscv/starfive/jh71x0_clkc.c

543

if (clk->flags & CLK_SET_RATE_PARENT) {

sys/arch/riscv/starfive/jh71x0_clkc.c

544

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/riscv/starfive/jh71x0_clkc.c

560

jh71x0_clkc_get_rate(void *priv, struct clk *clk)

sys/arch/riscv/starfive/jh71x0_clkc.c

564

container_of(clk, struct jh71x0_clkc_clk, jcc_clk);

sys/arch/riscv/starfive/jh71x0_clkc.c

569

struct clk * const clk_parent = clk_get_parent(clk);

sys/arch/riscv/starfive/jh71x0_clkc.c

580

jh71x0_clkc_enable(void *priv, struct clk *clk)

sys/arch/riscv/starfive/jh71x0_clkc.c

584

container_of(clk, struct jh71x0_clkc_clk, jcc_clk);

sys/arch/riscv/starfive/jh71x0_clkc.c

586

struct clk * const clk_parent = clk_get_parent(clk);

sys/arch/riscv/starfive/jh71x0_clkc.c

627

jh71x0_clkc_disable(void *priv, struct clk *clk)

sys/arch/riscv/starfive/jh71x0_clkc.c

631

container_of(clk, struct jh71x0_clkc_clk, jcc_clk);

sys/arch/riscv/starfive/jh71x0_clkc.c

68

jh71x0_clkc_fixed_factor_get_parent_rate(struct clk *clk)

sys/arch/riscv/starfive/jh71x0_clkc.c

685

jh71x0_clkc_set_parent(void *priv, struct clk *clk,

sys/arch/riscv/starfive/jh71x0_clkc.c

686

struct clk *clk_parent)

sys/arch/riscv/starfive/jh71x0_clkc.c

690

container_of(clk, struct jh71x0_clkc_clk, jcc_clk);

sys/arch/riscv/starfive/jh71x0_clkc.c

699

static struct clk *

sys/arch/riscv/starfive/jh71x0_clkc.c

70

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/riscv/starfive/jh71x0_clkc.c

700

jh71x0_clkc_get_parent(void *priv, struct clk *clk)

sys/arch/riscv/starfive/jh71x0_clkc.c

704

container_of(clk, struct jh71x0_clkc_clk, jcc_clk);

sys/arch/riscv/starfive/jh71x0_clkc.c

84

struct clk *clk = &jcc->jcc_clk;

sys/arch/riscv/starfive/jh71x0_clkc.c

86

uint64_t rate = jh71x0_clkc_fixed_factor_get_parent_rate(clk);

sys/arch/riscv/starfive/jh71x0_clkc.c

97

jh71x0_clkc_fixed_factor_set_parent_rate(struct clk *clk, u_int rate)

sys/arch/riscv/starfive/jh71x0_clkc.c

99

struct clk *clk_parent = clk_get_parent(clk);

sys/arch/riscv/starfive/jh71x0_clkc.h

369

struct clk jcc_clk;

sys/arch/riscv/starfive/jh71x0_eth.c

132

struct clk *clk;

sys/arch/riscv/starfive/jh71x0_eth.c

134

for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++) {

sys/arch/riscv/starfive/jh71x0_eth.c

135

if (clk_enable(clk) != 0) {

sys/arch/riscv/starfive/jh71x0_eth.h

52

struct clk * sc_clk_tx;

sys/arch/sgimips/stand/common/iris_scsireg.h

199

#define SBIC_TIMEOUT(val,clk) ((((val) * (clk)) / 800) + 1)

sys/arch/sparc64/dev/pcfiic_ebus.c

119

int clk = prom_getpropint(findroot(), "clock-frequency", 0);

sys/arch/sparc64/dev/pcfiic_ebus.c

121

if (clk < 105000000)

sys/arch/sparc64/dev/pcfiic_ebus.c

123

else if (clk < 160000000)

sys/arch/sparc64/sparc64/clock.c

629

int64_t clk = (ctime.tv_sec * 1000000LL + ctime.tv_usec);

sys/arch/sparc64/sparc64/clock.c

632

if (t - clk > hz) {

sys/arch/sparc64/sparc64/clock.c

635

(long long)t, (long long)clk, (long long)tk, (long long)tick_base);

sys/arch/sparc64/sparc64/cpu.c

482

uint64_t clk, sclk = 0;

sys/arch/sparc64/sparc64/cpu.c

526

clk = prom_getpropuint64(node, "clock-frequency64", 0);

sys/arch/sparc64/sparc64/cpu.c

527

if (clk == 0)

sys/arch/sparc64/sparc64/cpu.c

528

clk = prom_getpropint(node, "clock-frequency", 0);

sys/arch/sparc64/sparc64/cpu.c

529

if (clk == 0) {

sys/arch/sparc64/sparc64/cpu.c

533

clk = prom_getpropint(findroot(), "clock-frequency", 0);

sys/arch/sparc64/sparc64/cpu.c

535

if (clk) {

sys/arch/sparc64/sparc64/cpu.c

537

ci->ci_cpu_clockrate[0] = clk;

sys/arch/sparc64/sparc64/cpu.c

538

ci->ci_cpu_clockrate[1] = clk / 1000000;

sys/arch/sparc64/sparc64/cpu.c

548

snprintf(buf, sizeof buf, "%s @ %s MHz", ci->ci_name, clockfreq(clk));

sys/arch/vax/vax/ka410.c

154

volatile struct ka410_clock *clk = (volatile void *)clk_page;

sys/arch/vax/vax/ka410.c

160

clk->cpmbx = (clk->cpmbx & ~0x30);

sys/arch/vax/vax/ka43.c

352

volatile struct ka43_clock *clk = (volatile void *)clk_page;

sys/arch/vax/vax/ka43.c

362

clk->req = 0;

sys/arch/vax/vax/ka43.c

368

volatile struct ka43_clock *clk = (volatile void *)clk_page;

sys/arch/vax/vax/ka43.c

369

clk->req = 3; /* 3 is halt. */

sys/arch/vax/vax/ka43.c

376

volatile struct ka43_clock *clk = (volatile void *)clk_page;

sys/arch/vax/vax/ka43.c

377

clk->req = 2; /* 2 is reboot. */

sys/arch/x68k/dev/opm.c

150

adpcm_chgclk(u_char clk)

sys/arch/x68k/dev/opm.c

152

writeopm(0x1b, (readopm(0x1b) & ~OPM1B_CT1MSK) | clk);

sys/arch/x68k/dev/vs.c

147

u_char clk;

sys/arch/x68k/dev/vs.c

349

adpcm_chgclk(vs_l2r[rate].clk);

sys/arch/x68k/x68k/clock.c

342

struct clkreg *clk = (struct clkreg *)clkstd[0];

sys/arch/x68k/x68k/clock.c

344

clk->clk_msb2 = -1; clk->clk_lsb2 = -1;

sys/arch/x68k/x68k/clock.c

345

clk->clk_msb3 = -1; clk->clk_lsb3 = -1;

sys/arch/x68k/x68k/clock.c

347

clk->clk_cr2 = CLK_CR3;

sys/arch/x68k/x68k/clock.c

348

clk->clk_cr3 = CLK_OENAB|CLK_8BIT;

sys/arch/x68k/x68k/clock.c

349

clk->clk_cr2 = CLK_CR1;

sys/arch/x68k/x68k/clock.c

350

clk->clk_cr1 = CLK_IENAB;

sys/arch/x68k/x68k/clock.c

356

struct clkreg *clk = (struct clkreg *)clkstd[0];

sys/arch/x68k/x68k/clock.c

358

clk->clk_cr2 = CLK_CR3;

sys/arch/x68k/x68k/clock.c

359

clk->clk_cr3 = 0;

sys/arch/x68k/x68k/clock.c

360

clk->clk_cr2 = CLK_CR1;

sys/arch/x68k/x68k/clock.c

361

clk->clk_cr1 = CLK_IENAB;

sys/dev/clk/clk.c

107

struct clk *clk, *clk_parent;

sys/dev/clk/clk.c

110

clk = node.sysctl_data;

sys/dev/clk/clk.c

112

clk_parent = clk_get_parent(clk);

sys/dev/clk/clk.c

125

struct clk *clk, *clk_parent;

sys/dev/clk/clk.c

128

clk = node.sysctl_data;

sys/dev/clk/clk.c

130

clk_parent = clk_get_parent(clk);

sys/dev/clk/clk.c

150

clk_attach(struct clk *clk)

sys/dev/clk/clk.c

153

struct clk_domain *domain = clk->domain;

sys/dev/clk/clk.c

160

if (!domain->name || !clk->name) {

sys/dev/clk/clk.c

165

namelen = strlen(clk->name) + 1;

sys/dev/clk/clk.c

167

memcpy(name, clk->name, namelen);

sys/dev/clk/clk.c

182

clk_sysctl_rate_helper, 0, (void *)clk, 0,

sys/dev/clk/clk.c

189

clk_sysctl_parent_helper, 0, (void *)clk, 0,

sys/dev/clk/clk.c

196

clk_sysctl_parent_domain_helper, 0, (void *)clk, 0,

sys/dev/clk/clk.c

204

domain->name, clk->name, name, error);

sys/dev/clk/clk.c

210

struct clk *

sys/dev/clk/clk.c

217

clk_put(struct clk *clk)

sys/dev/clk/clk.c

219

if (clk->domain->funcs->put)

sys/dev/clk/clk.c

220

clk->domain->funcs->put(clk->domain->priv, clk);

sys/dev/clk/clk.c

224

clk_get_rate(struct clk *clk)

sys/dev/clk/clk.c

226

return clk->domain->funcs->get_rate(clk->domain->priv, clk);

sys/dev/clk/clk.c

230

clk_set_rate(struct clk *clk, u_int rate)

sys/dev/clk/clk.c

232

KASSERT(clk != NULL);

sys/dev/clk/clk.c

234

if (clk->flags & CLK_SET_RATE_PARENT)

sys/dev/clk/clk.c

235

return clk_set_rate(clk_get_parent(clk), rate);

sys/dev/clk/clk.c

237

if (clk->domain->funcs->set_rate)

sys/dev/clk/clk.c

238

return clk->domain->funcs->set_rate(clk->domain->priv,

sys/dev/clk/clk.c

239

clk, rate);

sys/dev/clk/clk.c

241

if (clk_get_rate(clk) == rate)

sys/dev/clk/clk.c

248

clk_round_rate(struct clk *clk, u_int rate)

sys/dev/clk/clk.c

250

if (clk->domain->funcs->round_rate) {

sys/dev/clk/clk.c

251

return clk->domain->funcs->round_rate(clk->domain->priv,

sys/dev/clk/clk.c

252

clk, rate);

sys/dev/clk/clk.c

258

clk_enable(struct clk *clk)

sys/dev/clk/clk.c

260

if (clk->domain->funcs->enable)

sys/dev/clk/clk.c

261

return clk->domain->funcs->enable(clk->domain->priv, clk);

sys/dev/clk/clk.c

267

clk_disable(struct clk *clk)

sys/dev/clk/clk.c

269

if (clk->domain->funcs->disable)

sys/dev/clk/clk.c

270

return clk->domain->funcs->disable(clk->domain->priv, clk);

sys/dev/clk/clk.c

276

clk_set_parent(struct clk *clk, struct clk *parent_clk)

sys/dev/clk/clk.c

278

if (clk->domain->funcs->set_parent)

sys/dev/clk/clk.c

279

return clk->domain->funcs->set_parent(clk->domain->priv,

sys/dev/clk/clk.c

280

clk, parent_clk);

sys/dev/clk/clk.c

285

struct clk *

sys/dev/clk/clk.c

286

clk_get_parent(struct clk *clk)

sys/dev/clk/clk.c

288

if (clk->domain->funcs->get_parent)

sys/dev/clk/clk.c

289

return clk->domain->funcs->get_parent(clk->domain->priv, clk);

sys/dev/clk/clk.c

91

struct clk *clk;

sys/dev/clk/clk.c

95

clk = node.sysctl_data;

sys/dev/clk/clk.c

98

rate = clk_get_rate(clk);

sys/dev/clk/clk.h

33

struct clk;

sys/dev/clk/clk.h

35

struct clk * clk_get(struct clk_domain *, const char *);

sys/dev/clk/clk.h

36

void clk_put(struct clk *);

sys/dev/clk/clk.h

37

u_int clk_get_rate(struct clk *);

sys/dev/clk/clk.h

38

int clk_set_rate(struct clk *, u_int);

sys/dev/clk/clk.h

39

u_int clk_round_rate(struct clk *, u_int);

sys/dev/clk/clk.h

40

int clk_enable(struct clk *);

sys/dev/clk/clk.h

41

int clk_disable(struct clk *);

sys/dev/clk/clk.h

42

int clk_set_parent(struct clk *, struct clk *);

sys/dev/clk/clk.h

43

struct clk * clk_get_parent(struct clk *);

sys/dev/clk/clk_backend.h

51

struct clk *(*get)(void *, const char *);

sys/dev/clk/clk_backend.h

52

void (*put)(void *, struct clk *);

sys/dev/clk/clk_backend.h

54

u_int (*get_rate)(void *, struct clk *);

sys/dev/clk/clk_backend.h

55

int (*set_rate)(void *, struct clk *, u_int);

sys/dev/clk/clk_backend.h

56

u_int (*round_rate)(void *, struct clk *, u_int);

sys/dev/clk/clk_backend.h

57

int (*enable)(void *, struct clk *);

sys/dev/clk/clk_backend.h

58

int (*disable)(void *, struct clk *);

sys/dev/clk/clk_backend.h

59

int (*set_parent)(void *, struct clk *, struct clk *);

sys/dev/clk/clk_backend.h

60

struct clk *(*get_parent)(void *, struct clk *);

sys/dev/clk/clk_backend.h

63

int clk_attach(struct clk *);

sys/dev/fdt/ahcisata_fdt.c

65

struct clk *clk;

sys/dev/fdt/ahcisata_fdt.c

92

for (i = 0; (clk = fdtbus_clock_get_index(phandle, i)) != NULL; i++)

sys/dev/fdt/ahcisata_fdt.c

93

if (clk_enable(clk) != 0) {

sys/dev/fdt/arasan_sdhc_fdt.c

106

static struct clk *

sys/dev/fdt/arasan_sdhc_fdt.c

118

arasan_sdhc_clk_get_rate(void *priv, struct clk *clk)

sys/dev/fdt/arasan_sdhc_fdt.c

69

struct clk *sc_clk_xin;

sys/dev/fdt/arasan_sdhc_fdt.c

70

struct clk *sc_clk_ahb;

sys/dev/fdt/arasan_sdhc_fdt.c

73

struct clk sc_clk_card;

sys/dev/fdt/arasan_sdhc_fdt.c

91

static struct clk *

sys/dev/fdt/ausoc.c

380

u_int fmt, pol, clk;

sys/dev/fdt/ausoc.c

403

clk = bitclock_master ?

sys/dev/fdt/ausoc.c

406

clk = bitclock_master ?

sys/dev/fdt/ausoc.c

422

__SHIFTIN(clk, AUDIO_DAI_CLOCK_MASK);

sys/dev/fdt/cpufreq_dt.c

65

struct clk *sc_clk;

sys/dev/fdt/dw_apb_uart.c

58

struct clk *ssc_clk;

sys/dev/fdt/dw_apb_uart.c

59

struct clk *ssc_pclk;

sys/dev/fdt/dwc2_fdt.c

121

struct clk *clk;

sys/dev/fdt/dwc2_fdt.c

137

clk = fdtbus_clock_get(phandle, "otg");

sys/dev/fdt/dwc2_fdt.c

138

if (clk == NULL || clk_enable(clk) != 0) {

sys/dev/fdt/dwc3_fdt.c

237

struct clk *clk;

sys/dev/fdt/dwc3_fdt.c

289

for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)

sys/dev/fdt/dwc3_fdt.c

290

if (clk_enable(clk) != 0) {

sys/dev/fdt/dwcmmc_fdt.c

83

struct clk *sc_clk_biu;

sys/dev/fdt/dwcmmc_fdt.c

84

struct clk *sc_clk_ciu;

sys/dev/fdt/dwcwdt_fdt.c

65

struct clk *clk;

sys/dev/fdt/dwcwdt_fdt.c

74

clk = fdtbus_clock_get_index(phandle, 0);

sys/dev/fdt/dwcwdt_fdt.c

75

if (clk == NULL || clk_enable(clk) != 0) {

sys/dev/fdt/dwcwdt_fdt.c

95

sc->sc_clkrate = clk_get_rate(clk);

sys/dev/fdt/dwiic_fdt.c

93

struct clk *clk;

sys/dev/fdt/dwiic_fdt.c

95

for (c = 0; (clk = fdtbus_clock_get_index(phandle, c)) != NULL; c++) {

sys/dev/fdt/dwiic_fdt.c

96

if (clk_enable(clk) != 0) {

sys/dev/fdt/ehci_fdt.c

76

struct clk *clk;

sys/dev/fdt/ehci_fdt.c

90

for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)

sys/dev/fdt/ehci_fdt.c

91

if (clk_enable(clk) != 0) {

sys/dev/fdt/fdt_clock.c

106

clk = cc->cc_funcs->decode(cc->cc_dev, cc_phandle,

sys/dev/fdt/fdt_clock.c

114

return clk;

sys/dev/fdt/fdt_clock.c

117

struct clk *

sys/dev/fdt/fdt_clock.c

123

static struct clk *

sys/dev/fdt/fdt_clock.c

158

struct clk *

sys/dev/fdt/fdt_clock.c

167

struct clk *clk;

sys/dev/fdt/fdt_clock.c

169

clk = fdtbus_clock_get(phandle, clkname);

sys/dev/fdt/fdt_clock.c

170

if (clk == NULL)

sys/dev/fdt/fdt_clock.c

173

return clk_enable(clk);

sys/dev/fdt/fdt_clock.c

179

struct clk *clk;

sys/dev/fdt/fdt_clock.c

181

clk = fdtbus_clock_get_index(phandle, index);

sys/dev/fdt/fdt_clock.c

182

if (clk == NULL)

sys/dev/fdt/fdt_clock.c

185

return clk_enable(clk);

sys/dev/fdt/fdt_clock.c

194

struct clk *

sys/dev/fdt/fdt_clock.c

227

struct clk *clk, *clk_parent;

sys/dev/fdt/fdt_clock.c

239

clk = fdtbus_clock_get_index_prop(phandle, index, "assigned-clocks");

sys/dev/fdt/fdt_clock.c

240

if (clk == NULL) {

sys/dev/fdt/fdt_clock.c

248

error = clk_set_parent(clk, clk_parent);

sys/dev/fdt/fdt_clock.c

251

clk->name, clk_parent->name, error);

sys/dev/fdt/fdt_clock.c

254

aprint_debug("clk: failed to set %s parent (not found)\n", clk->name);

sys/dev/fdt/fdt_clock.c

261

error = clk_set_rate(clk, rate);

sys/dev/fdt/fdt_clock.c

264

clk->name, rate, error);

sys/dev/fdt/fdt_clock.c

84

static struct clk *

sys/dev/fdt/fdt_clock.c

88

struct clk *clk = NULL;

sys/dev/fdt/fdt_clock.h

36

struct clk * (*decode)(device_t, int, const void *, size_t);

sys/dev/fdt/fdt_clock.h

42

struct clk * fdtbus_clock_get(int, const char *);

sys/dev/fdt/fdt_clock.h

43

struct clk * fdtbus_clock_get_index(int, u_int);

sys/dev/fdt/fdt_clock.h

44

struct clk * fdtbus_clock_byname(const char *);

sys/dev/fdt/fixedclock.c

122

static struct clk *

sys/dev/fdt/fixedclock.c

134

static struct clk *

sys/dev/fdt/fixedclock.c

146

fixedclock_put(void *priv, struct clk *clk)

sys/dev/fdt/fixedclock.c

151

fixedclock_get_rate(void *priv, struct clk *clk)

sys/dev/fdt/fixedclock.c

153

struct fixedclock_clk *fclk = (struct fixedclock_clk *)clk;

sys/dev/fdt/fixedclock.c

45

static struct clk *fixedclock_decode(device_t, int, const void *, size_t);

sys/dev/fdt/fixedclock.c

51

static struct clk *fixedclock_get(void *, const char *);

sys/dev/fdt/fixedclock.c

52

static void fixedclock_put(void *, struct clk *);

sys/dev/fdt/fixedclock.c

53

static u_int fixedclock_get_rate(void *, struct clk *);

sys/dev/fdt/fixedclock.c

62

struct clk base;

sys/dev/fdt/fixedfactorclock.c

130

static struct clk *

sys/dev/fdt/fixedfactorclock.c

143

static struct clk *

sys/dev/fdt/fixedfactorclock.c

155

fixedfactorclock_put(void *priv, struct clk *clk)

sys/dev/fdt/fixedfactorclock.c

160

fixedfactorclock_get_rate(void *priv, struct clk *clk)

sys/dev/fdt/fixedfactorclock.c

163

struct fixedfactorclock_clk *fclk = (struct fixedfactorclock_clk *)clk;

sys/dev/fdt/fixedfactorclock.c

164

struct clk *clkp_parent;

sys/dev/fdt/fixedfactorclock.c

45

static struct clk *fixedfactorclock_decode(device_t, int, const void *, size_t);

sys/dev/fdt/fixedfactorclock.c

51

static struct clk *fixedfactorclock_get(void *, const char *);

sys/dev/fdt/fixedfactorclock.c

52

static void fixedfactorclock_put(void *, struct clk *);

sys/dev/fdt/fixedfactorclock.c

53

static u_int fixedfactorclock_get_rate(void *, struct clk *);

sys/dev/fdt/fixedfactorclock.c

62

struct clk base;

sys/dev/fdt/mmc_pwrseq_simple.c

51

struct clk *sc_clk;

sys/dev/fdt/ns8250_uart.c

111

struct clk *clk;

sys/dev/fdt/ns8250_uart.c

133

clk = fdtbus_clock_get_index(phandle, 0);

sys/dev/fdt/ns8250_uart.c

134

if (clk != NULL)

sys/dev/fdt/ns8250_uart.c

135

sc->sc_frequency = clk_get_rate(clk);

sys/dev/fdt/ohci_fdt.c

76

struct clk *clk;

sys/dev/fdt/ohci_fdt.c

90

for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)

sys/dev/fdt/ohci_fdt.c

91

if (clk_enable(clk) != 0) {

sys/dev/fdt/pcfiic_fdt.c

100

clk = fdtbus_clock_get_index(phandle, 0);

sys/dev/fdt/pcfiic_fdt.c

101

if (clk != NULL) {

sys/dev/fdt/pcfiic_fdt.c

102

frequency = clk_get_rate(clk);

sys/dev/fdt/pcfiic_fdt.c

76

struct clk *clk;

sys/dev/fdt/usbnopphy.c

53

struct clk *sc_clk;

sys/dev/i2c/es8316ac.c

115

struct clk *sc_clk;

sys/dev/i2c/es8316ac.c

509

const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK);

sys/dev/i2c/es8316ac.c

515

if (clk != AUDIO_DAI_CLOCK_CBS_CFS)

sys/dev/i2c/pca9685.c

528

struct clk *clk;

sys/dev/i2c/pca9685.c

546

clk = fdtbus_clock_get_index(phandle, 0);

sys/dev/i2c/pca9685.c

547

if (clk != NULL) {

sys/dev/i2c/pca9685.c

549

sc->sc_clk_freq = clk_get_rate(clk);

sys/dev/i2c/rkpmic.c

206

struct clk base;

sys/dev/i2c/rkpmic.c

346

static struct clk *

sys/dev/i2c/rkpmic.c

365

static struct clk *

sys/dev/i2c/rkpmic.c

380

rkpmic_clk_get_rate(void *priv, struct clk *clk)

sys/dev/i2c/rkpmic.c

386

rkpmic_clk_enable(void *priv, struct clk *clk)

sys/dev/i2c/rkpmic.c

391

if (clk != &sc->sc_clk[1].base)

sys/dev/i2c/rkpmic.c

404

rkpmic_clk_disable(void *priv, struct clk *clk)

sys/dev/i2c/rkpmic.c

409

if (clk != &sc->sc_clk[1].base)

sys/dev/ic/cdnsiicvar.h

42

struct clk *sc_pclk;

sys/dev/ic/cissreg.h

167

u_int8_t clk[4]; /* unaligned dumbness */

sys/dev/ic/w83l518d_sdmmc.c

276

uint8_t clk;

sys/dev/ic/w83l518d_sdmmc.c

281

clk = WB_CLK_24M;

sys/dev/ic/w83l518d_sdmmc.c

283

clk = WB_CLK_16M;

sys/dev/ic/w83l518d_sdmmc.c

285

clk = WB_CLK_12M;

sys/dev/ic/w83l518d_sdmmc.c

287

clk = WB_CLK_375K;

sys/dev/ic/w83l518d_sdmmc.c

289

wb->wb_sdmmc_clk = clk;

sys/dev/ic/w83l518d_sdmmc.c

291

if (wb_idx_read(wb, WB_INDEX_CLK) != clk)

sys/dev/ic/w83l518d_sdmmc.c

292

wb_idx_write(wb, WB_INDEX_CLK, clk);

sys/dev/ic/wd33c93reg.h

173

#define SBIC_TIMEOUT(val,clk) ((((val) * (clk)) / 800) + 1)

sys/dev/mvme/osiop_pcctwo.c

110

int clk, ctest7;

sys/dev/mvme/osiop_pcctwo.c

123

clk = cpuspeed_khz / 1000;

sys/dev/mvme/osiop_pcctwo.c

126

clk = (cpuspeed_khz / 1000) * 2;

sys/dev/mvme/osiop_pcctwo.c

139

sc->sc_osiop.sc_clock_freq = clk;

sys/dev/pci/cxgb/cxgb_t3_hw.c

2996

unsigned int clk = adap->params.vpd.cclk * 1000;

sys/dev/pci/cxgb/cxgb_t3_hw.c

3002

tps = clk / cpt;

sys/dev/pci/cxgb/cxgb_vsc7323.c

201

int mode, clk, r;

sys/dev/pci/cxgb/cxgb_vsc7323.c

205

mode = clk = 1;

sys/dev/pci/cxgb/cxgb_vsc7323.c

207

mode = 1, clk = 2;

sys/dev/pci/cxgb/cxgb_vsc7323.c

209

mode = clk = 3;

sys/dev/pci/cxgb/cxgb_vsc7323.c

216

0x91 | (clk << 1))) ||

sys/dev/pci/cxgb/cxgb_vsc7323.c

218

0x90 | (clk << 1))) ||

sys/dev/pci/if_alc.c

240

uint32_t clk, v;

sys/dev/pci/if_alc.c

247

clk = MDIO_CLK_25_128;

sys/dev/pci/if_alc.c

249

clk = MDIO_CLK_25_4;

sys/dev/pci/if_alc.c

251

MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg));

sys/dev/pci/if_alc.c

311

uint32_t clk, v;

sys/dev/pci/if_alc.c

315

clk = MDIO_CLK_25_128;

sys/dev/pci/if_alc.c

317

clk = MDIO_CLK_25_4;

sys/dev/pci/if_alc.c

320

MDIO_SUP_PREAMBLE | clk);

sys/dev/pci/if_alc.c

412

uint32_t clk, v;

sys/dev/pci/if_alc.c

418

clk = MDIO_CLK_25_128;

sys/dev/pci/if_alc.c

420

clk = MDIO_CLK_25_4;

sys/dev/pci/if_alc.c

422

MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT);

sys/dev/pci/if_alc.c

443

uint32_t clk, v;

sys/dev/pci/if_alc.c

449

clk = MDIO_CLK_25_128;

sys/dev/pci/if_alc.c

451

clk = MDIO_CLK_25_4;

sys/dev/pci/if_alc.c

454

MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT);

sys/dev/pci/unichromefb.c

1099

uni_get_clkval(struct unichromefb_softc *sc, int clk)

sys/dev/pci/unichromefb.c

1104

if (clk == pll_value[i].clk) {

sys/dev/pci/unichromefb.c

1116

uni_set_vclk(struct unichromefb_softc *sc, uint32_t clk, int iga)

sys/dev/pci/unichromefb.c

1126

uni_wr(sc, VIASR, SR44, clk / 0x10000);

sys/dev/pci/unichromefb.c

1127

uni_wr(sc, VIASR, SR45, (clk & 0xffff) / 0x100);

sys/dev/pci/unichromefb.c

1128

uni_wr(sc, VIASR, SR46, clk % 0x100);

sys/dev/pci/unichromefb.c

801

pll_d_n = uni_get_clkval(sc, ctbl[index].clk);

sys/dev/pci/unichromehw.h

551

uint32_t clk;

sys/dev/pci/unichromereg.h

713

unsigned long clk;

sys/dev/pci/voyager/pwmclock.c

127

int i, clk;

sys/dev/pci/voyager/pwmclock.c

155

for (clk = 1; clk < 8; clk++) {

sys/dev/pci/voyager/pwmclock.c

158

(REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) | clk;

sys/dev/pci/voyager/pwmclock.c

169

sc->sc_scale[clk] = (acc >> 4) / 5000;

sys/dev/pci/voyager/pwmclock.c

172

for (clk = 1; clk < 8; clk++) {

sys/dev/pci/voyager/pwmclock.c

173

aprint_normal_dev(sc->sc_dev, "%d/8: %d\n", clk + 1,

sys/dev/pci/voyager/pwmclock.c

174

sc->sc_scale[clk]);

sys/dev/pci/voyager/voyagerfb.c

478

bus_size_t clk = voyagerfb_active_clock_reg(sc);

sys/dev/pci/voyager/voyagerfb.c

492

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, clk);

sys/dev/pci/voyager/voyagerfb.c

495

bus_space_write_4(sc->sc_memt, sc->sc_regh, clk, reg);

sys/dev/pci/voyager/voyagerfb.c

499

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, clk);

sys/dev/pci/voyager/voyagerfb.c

501

bus_space_write_4(sc->sc_memt, sc->sc_regh, clk, reg);

sys/dev/sdmmc/if_bwfm_sdio.c

475

uint32_t reg, clk;

sys/dev/sdmmc/if_bwfm_sdio.c

528

clk = bwfm_sdio_read_1(sc, BWFM_SDIO_FUNC1_CHIPCLKCSR);

sys/dev/sdmmc/if_bwfm_sdio.c

530

clk | BWFM_SDIO_FUNC1_CHIPCLKCSR_FORCE_HT);

sys/dev/sdmmc/if_bwfm_sdio.c

554

bwfm_sdio_write_1(sc, BWFM_SDIO_FUNC1_CHIPCLKCSR, clk);

sys/dev/usb/uftdi.c

638

uint32_t clk, divisor, fastclk_flag, frac, hwspeed;

sys/dev/usb/uftdi.c

645

clk = 12000000;

sys/dev/usb/uftdi.c

648

clk = 3000000;

sys/dev/usb/uftdi.c

656

if (speed < (clk >> 14) || speed > clk)

sys/dev/usb/uftdi.c

681

divisor = (clk << 4) / speed;

sys/dev/usb/uftdi.c

694

hwspeed = (clk << 3) / divisor;

sys/dev/usb/umcs.c

445

uint8_t clk;

sys/dev/usb/umcs.c

450

if (umcs7840_calc_baudrate(rate, &divisor, &clk)) {

sys/dev/usb/umcs.c

454

if (divisor == 0 || (clk & MCS7840_DEV_SPx_CLOCK_MASK) != clk) {

sys/dev/usb/umcs.c

459

DPRINTF(("Port %d set speed: %d (%02x / %d)\n", portno, rate, clk, divisor));

sys/dev/usb/umcs.c

466

data |= clk;

sys/dev/usb/umcs.c

493

umcs7840_calc_baudrate(uint32_t rate, uint16_t *divisor, uint8_t *clk)

sys/dev/usb/umcs.c

511

*clk = i << MCS7840_DEV_SPx_CLOCK_SHIFT;

sys/dev/videomode/videomode.c

25

#define M(nm,hr,vr,clk,hs,he,ht,vs,ve,vt,f) \

sys/dev/videomode/videomode.c

26

{ clk, hr, hs, he, ht, vr, vs, ve, vt, f, nm }

usr.bin/systat/main.c

101

struct clockinfo clk;

usr.bin/systat/main.c

226

len = sizeof(clk);

usr.bin/systat/main.c

227

if (sysctlbyname("kern.clockrate", &clk, &len, NULL, 0))

usr.bin/systat/main.c

229

hz = clk.hz;

usr.bin/systat/main.c

230

stathz = clk.stathz;

usr.sbin/inetd/inetd.c

1476

time_t clk;

usr.sbin/inetd/inetd.c

1479

clk = time((time_t *) 0);

usr.sbin/inetd/inetd.c

1481

len = snprintf(buffer, sizeof buffer, "%.24s\r\n", ctime(&clk));

usr.sbin/inetd/inetd.c

1491

time_t clk;

usr.sbin/inetd/inetd.c

1497

clk = time((time_t *) 0);

usr.sbin/inetd/inetd.c

1508

len = snprintf(buffer, sizeof buffer, "%.24s\r\n", ctime(&clk));